diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..79cc09e --- /dev/null +++ b/Makefile @@ -0,0 +1,20 @@ +test: build + ./anyRead/test + ./anyWrite/test + ./jumpTest/test + ./regTest/test + #./stackmemory + ./demo/demo + +build: anyRead/test.v anyRead/test.asm + python assembler.py anyRead/test.asm + python assembler.py anyWrite/test.asm + python assembler.py jumpTest/test.asm + python assembler.py regTest/test.asm + python assembler.py demo/demo.asm + iverilog -o anyRead/test anyRead/test.v + iverilog -o anyWrite/test anyWrite/test.v + iverilog -o jumpTest/test jumpTest/test.v + iverilog -o regTest/test regTest/test.v + #iverilog -o stackmemory stackmemory.t.v + iverilog -o demo/demo demo/demo.v diff --git a/README.md b/README.md index 81361ca..d6a9fcc 100644 --- a/README.md +++ b/README.md @@ -1,87 +1,5 @@ -# CompArch Final Project - -The goal of the final project is for you to explore a topic of interest within Computer Architecture, driven by your personal learning goals. This could build on and extend something we discussed in class, or dive into some other area of Computer Architecture (broadly defined). - -You may work in teams of any size, as long as they are appropriately scaled for your proposed project. Groups with > 4 members will face heavy skepticism about meeting this requirement. - -In terms of scale, this is not a months-long capstone but rather more like an extended Lab. You will have about 2 weeks to complete it, and it will comprise 15% of your final grade. Be ambitious but realistic. - -## Timeline - -- Nov 17 (in class) – project ideation and team formation fair -- Nov 28 (in class) – draft project proposal due , consultations with teams -- Nov 29 – revised project proposal and work plan due -- Dec 5 – mid-point check in (self-defined in work plan, highly recommended) -- Dec 12 – final project due - -## Proposal (10%) -Your project proposal should be about 1-2 pages, and must include: - -- Project title -- Team members -- Brief description of project (1-3 paragraphs) -- 2-3 references you plan to use -- Minimum, planned, and stretch deliverables -- Work plan (by Tuesday) - -We will discuss your proposal in class on November 28 (first class after break). These meetings will be quick and to-the-point, so you must come prepared with a printed out copy of your proposal. You should have done some background research by this point and have a good idea of your planned project trajectory. - -Based on the feedback from this meeting, you will revise your proposal and submit the final version including a work plan the following day. - -## Documentation (55%) -The documentation counts for 55% of your grade whether you succeed at your goal or not. Did you shoot for the moon and land among the harsh vacuum of space? You still learned something from the process, and as long as you document it well, you will get full credit. - -Documentation should be posted in the form of a project website (PDF or MarkDown in a repo can also be acceptable depending on the project) and must answer the following questions: - -### What did you do? -Your project abstract: one catchy sentence followed by a paragraph or two. The intended audience should include people that aren't necessarily versed in Computer Architecture, but are technically competent. -### Why did you do it? -A paragraph or so about why the project you chose is worthwhile and interesting. -### How did you do it? -This portion can assume an audience that has taken Computer Architecture, but don't let the story you’re telling get bogged down by buzzwords. A sure sign of a bad engineer is ORA (over reliance on acronyms). - -### How can someone else build on it? -Include everything necessary to pick up where you left off. This should include (as appropriate): - -- code -- schematics -- scripts and build instructions -- proper attribution for resources used and anything you did not write yourself -- list of difficulties and ‘gotchas’ while doing this project -- reflection on the project as a whole as well as your work plan -- possible TODOs to extend the depth of the project - -This should all be posted somewhere accessible, e.g. your project webpage or repository. Please do not literally include these question prompts and then answer them (you're better than that) - instead, use them to check that you've covered all the bases as you tell the story in the way that best makes sense for your project. - -## Choosing and Achieving your Goal (30%) -There is a lot of flexibility available in what your actual final project can be. As a first pass, it needs to satisfy the following criteria: - -1. Build upon what we have learned in class this semester or other "Computer Architecture" topics -1. Have well-defined criteria for when it is finished and successful -1. Be achievable within the time allotted - -## Possible broad directions: - -- Extending something you started in Computer Architecture -- Teaching somebody something cool about Computer Architecture -- Something useful to someone that uses Computer Architecture -- Something that needs the skills learned in Computer Architecture -- Something that you can present at Expo that will make people want to take Computer Architecture - -Append one of the following phrases to a cool project idea to make it more CompArch-y: - -- ... with an FPGA -- ... in assembly -- ... on a GPU -- ... inside a nested series of black boxes -- ... hardware accelerated - -As you put your project plans together, remember that a major portion of the project is communicating it to others. - -## Demo (5%) -We’ll present your project work during the time blocked out for "final exam" period – December 12 from 12 – 3PM. This is mainly an opportunity to show off and celebrate your great work (small percentage of overall grade), and the details are up to you. - -The "default" option is a poster version of your project documentation (along with a running live demo if appropriate), so that folks can walk around in a studio session and see what you did. Maybe you feel that a presentation is more appropriate for your project work. Perhaps a tutorial session with everyone participating makes the most sense. It could be that only a puppet show truly captures the essence of your project. Think about final demo format as you put together your proposal, but you don't need to make a final decision just yet. - -Good luck, and have fun! - +# TIS-100 CPU in verilog +This is an implementation of the TIS-100 cpu from the [game of the same name](http://www.zachtronics.com/tis-100/). Information about the functions of this machine can be found in our [ISA](https://github.com/TShapinsky/FinalProject/blob/master/TIS_100_ISA.pdf) +## Running +To run rebuild all verilog and asm files and run all the tests as well as the demo use + ``make test`` diff --git a/TIS_100_ISA.pdf b/TIS_100_ISA.pdf new file mode 100644 index 0000000..c1e6477 Binary files /dev/null and b/TIS_100_ISA.pdf differ diff --git a/anyRead/center.dat b/anyRead/center.dat new file mode 100644 index 0000000..c2f1dc1 --- /dev/null +++ b/anyRead/center.dat @@ -0,0 +1,16 @@ +001100111100000000 +001100111100000000 +001100111100000000 +001100111100000000 +001100111000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/anyRead/down.dat b/anyRead/down.dat new file mode 100644 index 0000000..ae53de8 --- /dev/null +++ b/anyRead/down.dat @@ -0,0 +1,16 @@ +010010000000000100 +010010000000000101 +011100000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/anyRead/left.dat b/anyRead/left.dat new file mode 100644 index 0000000..4b226e2 --- /dev/null +++ b/anyRead/left.dat @@ -0,0 +1,16 @@ +010001100000000001 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/anyRead/right.dat b/anyRead/right.dat new file mode 100644 index 0000000..4f2da29 --- /dev/null +++ b/anyRead/right.dat @@ -0,0 +1,16 @@ +010001000000000010 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L_0x29ef000; 1 drivers +v0x29cf790_0 .net "L2C", 14 0, L_0x29e37e0; 1 drivers +v0x29cf8a0_0 .net "R2C", 14 0, L_0x29e70f0; 1 drivers +v0x29cf9b0_0 .net "U2C", 14 0, L_0x29eb450; 1 drivers +v0x29cfac0_0 .net/s "accOutCenter", 10 0, L_0x29efe30; 1 drivers +v0x29cfc10_0 .var "clk", 0 0; +v0x29cfcb0_0 .var "dutPassed", 0 0; +v0x29cfd50 .array/s "expected", 6 0, 10 0; +v0x29cfe10_0 .var "i", 32 0; +S_0x29511f0 .scope module, "center" "tis100" 2 26, 3 49 0, S_0x2901970; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x28ff5d0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x28ff610 .param/str "memFile" 0 3 60, "anyRead/center.dat"; +L_0x29efe30 .functor BUFZ 11, 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L_0x29f0ba0; +L_0x29f0ba0 .part L_0x29ef000, 11, 1; +L_0x29f0c90 .reduce/or L_0x29f0aa0; +L_0x29f0d80 .part L_0x29e37e0, 12, 1; +L_0x29f0e20 .part L_0x29e70f0, 12, 1; +L_0x29f0f30 .part L_0x29eb450, 12, 1; +L_0x29f0fd0 .concat8 [ 1 1 1 1], L_0x29f0d80, L_0x29f0e20, L_0x29f0f30, L_0x29f1140; +L_0x29f1140 .part L_0x29ef000, 12, 1; +L_0x29f1230 .reduce/or L_0x29f0fd0; +L_0x29f13b0 .part L_0x29e37e0, 13, 1; +L_0x29f1450 .part L_0x29e70f0, 13, 1; +L_0x29f1590 .part L_0x29eb450, 13, 1; +L_0x29f1630 .concat8 [ 1 1 1 1], L_0x29f13b0, L_0x29f1450, L_0x29f1590, L_0x29f14f0; +L_0x29f14f0 .part L_0x29ef000, 13, 1; +L_0x29f18c0 .reduce/or L_0x29f1630; +L_0x29f17c0 .part L_0x29e37e0, 14, 1; +L_0x29f1b80 .part L_0x29e70f0, 14, 1; +L_0x29f19b0 .part L_0x29eb450, 14, 1; +L_0x29f1f10 .concat8 [ 1 1 1 1], L_0x29f17c0, L_0x29f1b80, L_0x29f19b0, L_0x29f1d30; +L_0x29f1d30 .part L_0x29ef000, 14, 1; +L_0x29f21f0 .reduce/or L_0x29f1f10; +L_0x29f1fb0 .part v0x29b9ae0_0, 0, 1; +L_0x29f2380 .part v0x29b9ae0_0, 1, 1; +L_0x29f2290 .part v0x29b9ae0_0, 2, 1; +L_0x29f2570 .part v0x29b9ae0_0, 3, 1; +L_0x29f2470 .part v0x29ba570_0, 0, 1; +L_0x29f27b0 .part v0x29ba570_0, 1, 1; +L_0x29f26a0 .part v0x29ba570_0, 2, 1; +L_0x29f2970 .part v0x29ba570_0, 3, 1; +L_0x29f2850 .part v0x29ba3b0_0, 0, 1; +L_0x29f2bd0 .part v0x29ba3b0_0, 1, 1; +L_0x29f2aa0 .part v0x29ba3b0_0, 2, 1; +L_0x29f2db0 .part v0x29ba3b0_0, 3, 1; +L_0x29f2c70 .part v0x29ba2d0_0, 0, 1; +L_0x29f2fa0 .part v0x29ba2d0_0, 1, 1; +L_0x29f2e50 .part v0x29ba2d0_0, 2, 1; +L_0x29f2ef0 .part v0x29ba2d0_0, 3, 1; +L_0x29f3040 .array/port v0x29b8fd0, L_0x29f33a0; +L_0x29f33a0 .concat [ 4 2 0 0], v0x29b61a0_0, L_0x2acb326b42a0; +LS_0x29f3230_0_0 .concat8 [ 11 1 1 1], v0x29b9410_2, L_0x29f2e50, L_0x29f2aa0, L_0x29f26a0; +LS_0x29f3230_0_4 .concat8 [ 1 0 0 0], L_0x29f2290; +L_0x29f3230 .concat8 [ 14 1 0 0], LS_0x29f3230_0_0, LS_0x29f3230_0_4; +LS_0x29f37e0_0_0 .concat8 [ 11 1 1 1], v0x29b9410_3, L_0x29f2ef0, L_0x29f2db0, L_0x29f2970; +LS_0x29f37e0_0_4 .concat8 [ 1 0 0 0], L_0x29f2570; +L_0x29f37e0 .concat8 [ 14 1 0 0], LS_0x29f37e0_0_0, LS_0x29f37e0_0_4; +LS_0x29f3500_0_0 .concat8 [ 11 1 1 1], v0x29b9410_0, L_0x29f2c70, L_0x29f2850, L_0x29f2470; +LS_0x29f3500_0_4 .concat8 [ 1 0 0 0], L_0x29f1fb0; +L_0x29f3500 .concat8 [ 14 1 0 0], LS_0x29f3500_0_0, LS_0x29f3500_0_4; +LS_0x29f3ed0_0_0 .concat8 [ 11 1 1 1], v0x29b9410_1, L_0x29f2fa0, L_0x29f2bd0, L_0x29f27b0; +LS_0x29f3ed0_0_4 .concat8 [ 1 0 0 0], L_0x29f2380; +L_0x29f3ed0 .concat8 [ 14 1 0 0], LS_0x29f3ed0_0_0, LS_0x29f3ed0_0_4; +L_0x29f3b40 .part L_0x29f0ec0, 14, 4; +L_0x29f4360 .part L_0x29f0ec0, 11, 3; +L_0x29f4170 .part L_0x29f0ec0, 8, 3; +L_0x29f45b0 .part L_0x29f0ec0, 10, 4; +L_0x29f4400 .part L_0x29f0ec0, 0, 11; +S_0x29ba9b0 .scope module, "down" "tis100" 2 25, 3 49 0, S_0x2901970; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x29baba0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x29babe0 .param/str "memFile" 0 3 60, "anyRead/down.dat"; +L_0x29ebd50 .functor BUFZ 11, v0x29baee0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29ebf50 .functor BUFZ 11, v0x29baee0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29ece00 .functor BUFZ 18, L_0x29eed70, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x29baee0_0 .var/s "ACC", 10 0; +v0x29bafe0_0 .var/s "BAK", 10 0; +v0x29bb0c0_0 .net "DST", 2 0, L_0x29efef0; 1 drivers +v0x29bb180_0 .net/s "IMM", 10 0, L_0x29eff90; 1 drivers +v0x29bb260_0 .net "INST", 3 0, L_0x29ef7d0; 1 drivers +v0x29bb390_0 .net "LABEL", 3 0, L_0x29f0140; 1 drivers +v0x29bb470_0 .var "PC", 3 0; +v0x29bb550_0 .var "PCNEXT", 3 0; +v0x29bb630_0 .net "SRC", 2 0, L_0x29efd00; 1 drivers +v0x29bb7a0_0 .net *"_s103", 0 0, L_0x29ee0b0; 1 drivers +v0x29bb880_0 .net *"_s107", 0 0, L_0x29edfc0; 1 drivers +v0x29bb960_0 .net *"_s111", 0 0, L_0x29ee2a0; 1 drivers +v0x29bba40_0 .net *"_s115", 0 0, L_0x29ee1a0; 1 drivers +v0x29bbb20_0 .net *"_s119", 0 0, L_0x29ee4e0; 1 drivers +v0x29bbc00_0 .net *"_s123", 0 0, L_0x29ee3d0; 1 drivers +v0x29bbce0_0 .net *"_s127", 0 0, L_0x29ee6a0; 1 drivers +v0x29bbdc0_0 .net *"_s131", 0 0, L_0x29ee580; 1 drivers +v0x29bbf70_0 .net *"_s135", 0 0, L_0x29ee900; 1 drivers +v0x29bc010_0 .net *"_s139", 0 0, L_0x29ee7d0; 1 drivers +v0x29bc0f0_0 .net *"_s143", 0 0, L_0x29eeae0; 1 drivers +v0x29bc1d0_0 .net *"_s147", 0 0, L_0x29ee9a0; 1 drivers +v0x29bc2b0_0 .net *"_s151", 0 0, L_0x29eecd0; 1 drivers +v0x29bc390_0 .net *"_s155", 0 0, L_0x29eeb80; 1 drivers +v0x29bc470_0 .net *"_s159", 0 0, L_0x29eec20; 1 drivers +v0x29bc550_0 .net *"_s160", 17 0, L_0x29eed70; 1 drivers +v0x29bc630_0 .net *"_s162", 5 0, L_0x29ef0d0; 1 drivers +L_0x2acb326b4210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x29bc710_0 .net *"_s165", 1 0, L_0x2acb326b4210; 1 drivers +v0x29be6a0_2 .array/port v0x29be6a0, 2; +v0x29bc7f0_0 .net *"_s173", 10 0, v0x29be6a0_2; 1 drivers +v0x29be6a0_3 .array/port v0x29be6a0, 3; +v0x29bc8d0_0 .net *"_s179", 10 0, v0x29be6a0_3; 1 drivers +v0x29be6a0_0 .array/port v0x29be6a0, 0; +v0x29bc9b0_0 .net *"_s185", 10 0, v0x29be6a0_0; 1 drivers +v0x29be6a0_1 .array/port v0x29be6a0, 1; +v0x29bca90_0 .net *"_s191", 10 0, v0x29be6a0_1; 1 drivers +v0x29bcb70_0 .net *"_s23", 0 0, L_0x29ec590; 1 drivers +v0x29bcc50_0 .net *"_s27", 0 0, L_0x29ec6b0; 1 drivers +v0x29bbea0_0 .net *"_s31", 0 0, L_0x29ec7a0; 1 drivers +v0x29bcf20_0 .net *"_s36", 0 0, L_0x29eca90; 1 drivers +v0x29bd000_0 .net *"_s42", 0 0, L_0x29eccc0; 1 drivers +v0x29bd0e0_0 .net *"_s46", 0 0, L_0x29ecd60; 1 drivers +v0x29bd1c0_0 .net *"_s50", 0 0, L_0x29ece70; 1 drivers +v0x29bd2a0_0 .net *"_s55", 0 0, L_0x29ed080; 1 drivers +v0x29bd380_0 .net *"_s61", 0 0, L_0x29ed2f0; 1 drivers +v0x29bd460_0 .net *"_s65", 0 0, L_0x29ed420; 1 drivers +v0x29bd540_0 .net *"_s69", 0 0, L_0x29ed5f0; 1 drivers +v0x29bd620_0 .net *"_s74", 0 0, L_0x29ed550; 1 drivers +v0x29bd700_0 .net *"_s80", 0 0, L_0x29ed780; 1 drivers +v0x29bd7e0_0 .net *"_s84", 0 0, L_0x29eda70; 1 drivers +v0x29bd8c0_0 .net *"_s88", 0 0, L_0x29ed9b0; 1 drivers +v0x29bd9a0_0 .net *"_s93", 0 0, L_0x29edb10; 1 drivers +v0x29bda80_0 .net *"_s99", 0 0, L_0x29edda0; 1 drivers +v0x29bdb60_0 .net/s "accOut", 10 0, L_0x29ebd50; 1 drivers +v0x29bdc40_0 .net "anyHasData", 0 0, L_0x29ecbd0; 1 drivers +v0x29bdd00_0 .net "anyReadAck", 0 0, L_0x29ed910; 1 drivers +v0x29bddc0_0 .net "anyWantData", 0 0, L_0x29ed170; 1 drivers +v0x29bde80_0 .net "anyWriteAck", 0 0, L_0x29eded0; 1 drivers +v0x29bdf40_0 .net "clk", 0 0, v0x29cfc10_0; alias, 1 drivers +o0x2acb32684cc8 .functor BUFZ 15, C4; HiZ drive +v0x29bdfe0_0 .net "down", 14 0, o0x2acb32684cc8; 0 drivers +v0x29be0a0_0 .net "downOut", 14 0, L_0x29ef4f0; 1 drivers +v0x29be180_0 .net "instruction", 17 0, L_0x29ece00; 1 drivers +v0x29be260 .array "instructions", 15 0, 17 0; +v0x29be320_0 .var "last", 2 0; +o0x2acb32684d88 .functor BUFZ 15, C4; HiZ drive +v0x29be400_0 .net "left", 14 0, o0x2acb32684d88; 0 drivers +v0x29be4e0_0 .net "leftOut", 14 0, L_0x29ef230; 1 drivers +v0x29be5c0_0 .var "mode", 2 0; +v0x29be6a0 .array/s "outVals", 2 5, 10 0; +v0x29be7e0_0 .var "phase", 2 0; +v0x29be8c0_0 .net "portsHaveData", 5 2, L_0x29ec8d0; 1 drivers +v0x29bccf0_0 .net "portsWantData", 5 2, L_0x29ecf10; 1 drivers +v0x29bcdd0_0 .net "readAckIn", 5 2, L_0x29ed690; 1 drivers +v0x29bed70_0 .var "readAckOut", 5 2; +v0x29bee10_0 .var "readTarget", 2 0; +v0x29beeb0_0 .var/s "readValue", 10 0; +L_0x2acb326b41c8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x29bef50 .array "regVals", 0 7; +v0x29bef50_0 .net/s v0x29bef50 0, 10 0, L_0x2acb326b41c8; 1 drivers +v0x29bef50_1 .net/s v0x29bef50 1, 10 0, L_0x29ebf50; 1 drivers +v0x29bef50_2 .net/s v0x29bef50 2, 10 0, L_0x29ebfc0; 1 drivers +v0x29bef50_3 .net/s v0x29bef50 3, 10 0, L_0x29ec2c0; 1 drivers +v0x29bef50_4 .net/s v0x29bef50 4, 10 0, L_0x29ec390; 1 drivers +v0x29bef50_5 .net/s v0x29bef50 5, 10 0, L_0x29ec460; 1 drivers +o0x2acb32685148 .functor BUFZ 11, C4; HiZ drive +v0x29bef50_6 .net/s v0x29bef50 6, 10 0, o0x2acb32685148; 0 drivers +o0x2acb32685178 .functor BUFZ 11, C4; HiZ drive +v0x29bef50_7 .net/s v0x29bef50 7, 10 0, o0x2acb32685178; 0 drivers +o0x2acb326851a8 .functor BUFZ 15, C4; HiZ drive +v0x29bf160_0 .net "right", 14 0, o0x2acb326851a8; 0 drivers +v0x29bf240_0 .net "rightOut", 14 0, L_0x29efae0; 1 drivers +v0x29bf320_0 .net "up", 14 0, L_0x29f37e0; alias, 1 drivers +v0x29bf410_0 .net "upOut", 14 0, L_0x29ef000; alias, 1 drivers +v0x29bf4e0_0 .var "weHaveData", 5 2; +v0x29bf5a0_0 .var "weWantData", 5 2; +v0x29bf680_0 .net "writeAckIn", 5 2, L_0x29edbe0; 1 drivers +v0x29bf760_0 .var "writeAckOut", 5 2; +v0x29bf840_0 .var "writeTarget", 2 0; +v0x29bf920_0 .var/s "writeValue", 10 0; +L_0x29ebfc0 .part o0x2acb32684d88, 0, 11; +L_0x29ec2c0 .part o0x2acb326851a8, 0, 11; +L_0x29ec390 .part L_0x29f37e0, 0, 11; +L_0x29ec460 .part o0x2acb32684cc8, 0, 11; +L_0x29ec590 .part o0x2acb32684d88, 11, 1; +L_0x29ec6b0 .part o0x2acb326851a8, 11, 1; +L_0x29ec7a0 .part L_0x29f37e0, 11, 1; +L_0x29ec8d0 .concat8 [ 1 1 1 1], L_0x29ec590, L_0x29ec6b0, L_0x29ec7a0, L_0x29eca90; +L_0x29eca90 .part o0x2acb32684cc8, 11, 1; +L_0x29ecbd0 .reduce/or L_0x29ec8d0; +L_0x29eccc0 .part o0x2acb32684d88, 12, 1; +L_0x29ecd60 .part o0x2acb326851a8, 12, 1; +L_0x29ece70 .part L_0x29f37e0, 12, 1; +L_0x29ecf10 .concat8 [ 1 1 1 1], L_0x29eccc0, L_0x29ecd60, L_0x29ece70, L_0x29ed080; +L_0x29ed080 .part o0x2acb32684cc8, 12, 1; +L_0x29ed170 .reduce/or L_0x29ecf10; +L_0x29ed2f0 .part o0x2acb32684d88, 13, 1; +L_0x29ed420 .part o0x2acb326851a8, 13, 1; +L_0x29ed5f0 .part L_0x29f37e0, 13, 1; +L_0x29ed690 .concat8 [ 1 1 1 1], L_0x29ed2f0, L_0x29ed420, L_0x29ed5f0, L_0x29ed550; +L_0x29ed550 .part o0x2acb32684cc8, 13, 1; +L_0x29ed910 .reduce/or L_0x29ed690; +L_0x29ed780 .part o0x2acb32684d88, 14, 1; +L_0x29eda70 .part o0x2acb326851a8, 14, 1; +L_0x29ed9b0 .part L_0x29f37e0, 14, 1; +L_0x29edbe0 .concat8 [ 1 1 1 1], L_0x29ed780, L_0x29eda70, L_0x29ed9b0, L_0x29edb10; +L_0x29edb10 .part o0x2acb32684cc8, 14, 1; +L_0x29eded0 .reduce/or L_0x29edbe0; +L_0x29edda0 .part v0x29bed70_0, 0, 1; +L_0x29ee0b0 .part v0x29bed70_0, 1, 1; +L_0x29edfc0 .part v0x29bed70_0, 2, 1; +L_0x29ee2a0 .part v0x29bed70_0, 3, 1; +L_0x29ee1a0 .part v0x29bf760_0, 0, 1; +L_0x29ee4e0 .part v0x29bf760_0, 1, 1; +L_0x29ee3d0 .part v0x29bf760_0, 2, 1; +L_0x29ee6a0 .part v0x29bf760_0, 3, 1; +L_0x29ee580 .part v0x29bf5a0_0, 0, 1; +L_0x29ee900 .part v0x29bf5a0_0, 1, 1; +L_0x29ee7d0 .part v0x29bf5a0_0, 2, 1; +L_0x29eeae0 .part v0x29bf5a0_0, 3, 1; +L_0x29ee9a0 .part v0x29bf4e0_0, 0, 1; +L_0x29eecd0 .part v0x29bf4e0_0, 1, 1; +L_0x29eeb80 .part v0x29bf4e0_0, 2, 1; +L_0x29eec20 .part v0x29bf4e0_0, 3, 1; +L_0x29eed70 .array/port v0x29be260, L_0x29ef0d0; +L_0x29ef0d0 .concat [ 4 2 0 0], v0x29bb470_0, L_0x2acb326b4210; +LS_0x29ef000_0_0 .concat8 [ 11 1 1 1], v0x29be6a0_2, L_0x29eeb80, L_0x29ee7d0, L_0x29ee3d0; +LS_0x29ef000_0_4 .concat8 [ 1 0 0 0], L_0x29edfc0; +L_0x29ef000 .concat8 [ 14 1 0 0], LS_0x29ef000_0_0, LS_0x29ef000_0_4; +LS_0x29ef4f0_0_0 .concat8 [ 11 1 1 1], v0x29be6a0_3, L_0x29eec20, L_0x29eeae0, L_0x29ee6a0; +LS_0x29ef4f0_0_4 .concat8 [ 1 0 0 0], L_0x29ee2a0; +L_0x29ef4f0 .concat8 [ 14 1 0 0], LS_0x29ef4f0_0_0, LS_0x29ef4f0_0_4; +LS_0x29ef230_0_0 .concat8 [ 11 1 1 1], v0x29be6a0_0, L_0x29ee9a0, L_0x29ee580, L_0x29ee1a0; +LS_0x29ef230_0_4 .concat8 [ 1 0 0 0], L_0x29edda0; +L_0x29ef230 .concat8 [ 14 1 0 0], LS_0x29ef230_0_0, LS_0x29ef230_0_4; +LS_0x29efae0_0_0 .concat8 [ 11 1 1 1], v0x29be6a0_1, L_0x29eecd0, L_0x29ee900, L_0x29ee4e0; +LS_0x29efae0_0_4 .concat8 [ 1 0 0 0], L_0x29ee0b0; +L_0x29efae0 .concat8 [ 14 1 0 0], LS_0x29efae0_0_0, LS_0x29efae0_0_4; +L_0x29ef7d0 .part L_0x29ece00, 14, 4; +L_0x29efef0 .part L_0x29ece00, 11, 3; +L_0x29efd00 .part L_0x29ece00, 8, 3; +L_0x29f0140 .part L_0x29ece00, 10, 4; +L_0x29eff90 .part L_0x29ece00, 0, 11; +S_0x29bfba0 .scope module, "left" "tis100" 2 22, 3 49 0, S_0x2901970; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x29bfda0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x29bfde0 .param/str "memFile" 0 3 60, "anyRead/left.dat"; +L_0x29cfef0 .functor BUFZ 11, v0x29c00e0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29dff90 .functor BUFZ 11, v0x29c00e0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29e0bf0 .functor BUFZ 18, L_0x29e2bb0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x29c00e0_0 .var/s "ACC", 10 0; +v0x29c01e0_0 .var/s "BAK", 10 0; +v0x29c02c0_0 .net "DST", 2 0, L_0x29e3bf0; 1 drivers +v0x29c0380_0 .net/s "IMM", 10 0, L_0x29e3c90; 1 drivers +v0x29c0460_0 .net "INST", 3 0, L_0x29e34d0; 1 drivers +v0x29c0590_0 .net "LABEL", 3 0, L_0x29e3e40; 1 drivers +v0x29c0670_0 .var "PC", 3 0; +v0x29c0750_0 .var "PCNEXT", 3 0; +v0x29c0830_0 .net "SRC", 2 0, L_0x29e3a00; 1 drivers +v0x29c09a0_0 .net *"_s103", 0 0, L_0x29e1ef0; 1 drivers +v0x29c0a80_0 .net *"_s107", 0 0, L_0x29e1e00; 1 drivers +v0x29c0b60_0 .net *"_s111", 0 0, L_0x29e20e0; 1 drivers +v0x29c0c40_0 .net *"_s115", 0 0, L_0x29e1fe0; 1 drivers +v0x29c0d20_0 .net *"_s119", 0 0, L_0x29e2320; 1 drivers +v0x29c0e00_0 .net *"_s123", 0 0, L_0x29e2210; 1 drivers +v0x29c0ee0_0 .net *"_s127", 0 0, L_0x29e24e0; 1 drivers +v0x29c0fc0_0 .net *"_s131", 0 0, L_0x29e23c0; 1 drivers +v0x29c1170_0 .net *"_s135", 0 0, L_0x29e2740; 1 drivers +v0x29c1210_0 .net *"_s139", 0 0, L_0x29e2610; 1 drivers +v0x29c12f0_0 .net *"_s143", 0 0, L_0x29e2920; 1 drivers +v0x29c13d0_0 .net *"_s147", 0 0, L_0x29e27e0; 1 drivers +v0x29c14b0_0 .net *"_s151", 0 0, L_0x29e2b10; 1 drivers +v0x29c1590_0 .net *"_s155", 0 0, L_0x29e29c0; 1 drivers +v0x29c1670_0 .net *"_s159", 0 0, L_0x29e2a60; 1 drivers +v0x29c1750_0 .net *"_s160", 17 0, L_0x29e2bb0; 1 drivers +v0x29c1830_0 .net *"_s162", 5 0, L_0x29e2f10; 1 drivers +L_0x2acb326b4060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x29c1910_0 .net *"_s165", 1 0, L_0x2acb326b4060; 1 drivers +v0x29c37f0_2 .array/port v0x29c37f0, 2; +v0x29c19f0_0 .net *"_s173", 10 0, v0x29c37f0_2; 1 drivers +v0x29c37f0_3 .array/port v0x29c37f0, 3; +v0x29c1ad0_0 .net *"_s179", 10 0, v0x29c37f0_3; 1 drivers +v0x29c37f0_0 .array/port v0x29c37f0, 0; +v0x29c1bb0_0 .net *"_s185", 10 0, v0x29c37f0_0; 1 drivers +v0x29c37f0_1 .array/port v0x29c37f0, 1; +v0x29c1c90_0 .net *"_s191", 10 0, v0x29c37f0_1; 1 drivers +v0x29c1d70_0 .net *"_s23", 0 0, L_0x29e0310; 1 drivers +v0x29c1e50_0 .net *"_s27", 0 0, L_0x29e0430; 1 drivers +v0x29bff40_0 .net *"_s31", 0 0, L_0x29e05a0; 1 drivers +v0x29c1060_0 .net *"_s36", 0 0, L_0x29e0820; 1 drivers +v0x29c2100_0 .net *"_s42", 0 0, L_0x29e0ab0; 1 drivers +v0x29c21c0_0 .net *"_s46", 0 0, L_0x29e0b50; 1 drivers +v0x29c22a0_0 .net *"_s50", 0 0, L_0x29e0c60; 1 drivers +v0x29c2380_0 .net *"_s55", 0 0, L_0x29e0ef0; 1 drivers +v0x29c2460_0 .net *"_s61", 0 0, L_0x29e1160; 1 drivers +v0x29c2540_0 .net *"_s65", 0 0, L_0x29e1290; 1 drivers +v0x29c2620_0 .net *"_s69", 0 0, L_0x29e13d0; 1 drivers +v0x29c2700_0 .net *"_s74", 0 0, L_0x29e1330; 1 drivers +v0x29c27e0_0 .net *"_s80", 0 0, L_0x29e15c0; 1 drivers +v0x29c28c0_0 .net *"_s84", 0 0, L_0x29e18b0; 1 drivers +v0x29c29a0_0 .net *"_s88", 0 0, L_0x29e17f0; 1 drivers +v0x29c2a80_0 .net *"_s93", 0 0, L_0x29e1950; 1 drivers +v0x29c2b60_0 .net *"_s99", 0 0, L_0x29e1be0; 1 drivers +v0x29c2c40_0 .net/s "accOut", 10 0, L_0x29cfef0; 1 drivers +v0x29c2d20_0 .net "anyHasData", 0 0, L_0x29e0960; 1 drivers +v0x29c2de0_0 .net "anyReadAck", 0 0, L_0x29e1750; 1 drivers +v0x29c2ea0_0 .net "anyWantData", 0 0, L_0x29e0fe0; 1 drivers +v0x29c2f60_0 .net "anyWriteAck", 0 0, L_0x29e1d10; 1 drivers +v0x29c3020_0 .net "clk", 0 0, v0x29cfc10_0; alias, 1 drivers +o0x2acb32685ef8 .functor BUFZ 15, C4; HiZ drive +v0x29c3110_0 .net "down", 14 0, o0x2acb32685ef8; 0 drivers +v0x29c31f0_0 .net "downOut", 14 0, L_0x29e31f0; 1 drivers +v0x29c32d0_0 .net "instruction", 17 0, L_0x29e0bf0; 1 drivers +v0x29c33b0 .array "instructions", 15 0, 17 0; +v0x29c3470_0 .var "last", 2 0; +o0x2acb32685fb8 .functor BUFZ 15, C4; HiZ drive +v0x29c3550_0 .net "left", 14 0, o0x2acb32685fb8; 0 drivers +v0x29c3630_0 .net "leftOut", 14 0, L_0x29e3070; 1 drivers +v0x29c3710_0 .var "mode", 2 0; +v0x29c37f0 .array/s "outVals", 2 5, 10 0; +v0x29c3930_0 .var "phase", 2 0; +v0x29c3a10_0 .net "portsHaveData", 5 2, L_0x29e0640; 1 drivers +v0x29c1f30_0 .net "portsWantData", 5 2, L_0x29e0d00; 1 drivers +v0x29c2010_0 .net "readAckIn", 5 2, L_0x29e1470; 1 drivers +v0x29c3ec0_0 .var "readAckOut", 5 2; +v0x29c3fa0_0 .var "readTarget", 2 0; +v0x29c4080_0 .var/s "readValue", 10 0; +L_0x2acb326b4018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x29c4160 .array "regVals", 0 7; +v0x29c4160_0 .net/s v0x29c4160 0, 10 0, L_0x2acb326b4018; 1 drivers +v0x29c4160_1 .net/s v0x29c4160 1, 10 0, L_0x29dff90; 1 drivers +v0x29c4160_2 .net/s v0x29c4160 2, 10 0, L_0x29e0000; 1 drivers +v0x29c4160_3 .net/s v0x29c4160 3, 10 0, L_0x29e00a0; 1 drivers +v0x29c4160_4 .net/s v0x29c4160 4, 10 0, L_0x29e0140; 1 drivers +v0x29c4160_5 .net/s v0x29c4160 5, 10 0, L_0x29e01e0; 1 drivers +o0x2acb32686378 .functor BUFZ 11, C4; HiZ drive +v0x29c4160_6 .net/s v0x29c4160 6, 10 0, o0x2acb32686378; 0 drivers +o0x2acb326863a8 .functor BUFZ 11, C4; HiZ drive +v0x29c4160_7 .net/s v0x29c4160 7, 10 0, o0x2acb326863a8; 0 drivers +v0x29c4370_0 .net "right", 14 0, L_0x29f3500; alias, 1 drivers +v0x29c4460_0 .net "rightOut", 14 0, L_0x29e37e0; alias, 1 drivers +o0x2acb326863d8 .functor BUFZ 15, C4; HiZ drive +v0x29c4530_0 .net "up", 14 0, o0x2acb326863d8; 0 drivers +v0x29c45f0_0 .net "upOut", 14 0, L_0x29c4290; 1 drivers +v0x29c46d0_0 .var "weHaveData", 5 2; +v0x29c47b0_0 .var "weWantData", 5 2; +v0x29c4890_0 .net "writeAckIn", 5 2, L_0x29e1a20; 1 drivers +v0x29c4970_0 .var "writeAckOut", 5 2; +v0x29c4a50_0 .var "writeTarget", 2 0; +v0x29c4b30_0 .var/s "writeValue", 10 0; +L_0x29e0000 .part o0x2acb32685fb8, 0, 11; +L_0x29e00a0 .part L_0x29f3500, 0, 11; +L_0x29e0140 .part o0x2acb326863d8, 0, 11; +L_0x29e01e0 .part o0x2acb32685ef8, 0, 11; +L_0x29e0310 .part o0x2acb32685fb8, 11, 1; +L_0x29e0430 .part L_0x29f3500, 11, 1; +L_0x29e05a0 .part o0x2acb326863d8, 11, 1; +L_0x29e0640 .concat8 [ 1 1 1 1], L_0x29e0310, L_0x29e0430, L_0x29e05a0, L_0x29e0820; +L_0x29e0820 .part o0x2acb32685ef8, 11, 1; +L_0x29e0960 .reduce/or L_0x29e0640; +L_0x29e0ab0 .part o0x2acb32685fb8, 12, 1; +L_0x29e0b50 .part L_0x29f3500, 12, 1; +L_0x29e0c60 .part o0x2acb326863d8, 12, 1; +L_0x29e0d00 .concat8 [ 1 1 1 1], L_0x29e0ab0, L_0x29e0b50, L_0x29e0c60, L_0x29e0ef0; +L_0x29e0ef0 .part o0x2acb32685ef8, 12, 1; +L_0x29e0fe0 .reduce/or L_0x29e0d00; +L_0x29e1160 .part o0x2acb32685fb8, 13, 1; +L_0x29e1290 .part L_0x29f3500, 13, 1; +L_0x29e13d0 .part o0x2acb326863d8, 13, 1; +L_0x29e1470 .concat8 [ 1 1 1 1], L_0x29e1160, L_0x29e1290, L_0x29e13d0, L_0x29e1330; +L_0x29e1330 .part o0x2acb32685ef8, 13, 1; +L_0x29e1750 .reduce/or L_0x29e1470; +L_0x29e15c0 .part o0x2acb32685fb8, 14, 1; +L_0x29e18b0 .part L_0x29f3500, 14, 1; +L_0x29e17f0 .part o0x2acb326863d8, 14, 1; +L_0x29e1a20 .concat8 [ 1 1 1 1], L_0x29e15c0, L_0x29e18b0, L_0x29e17f0, L_0x29e1950; +L_0x29e1950 .part o0x2acb32685ef8, 14, 1; +L_0x29e1d10 .reduce/or L_0x29e1a20; +L_0x29e1be0 .part v0x29c3ec0_0, 0, 1; +L_0x29e1ef0 .part v0x29c3ec0_0, 1, 1; +L_0x29e1e00 .part v0x29c3ec0_0, 2, 1; +L_0x29e20e0 .part v0x29c3ec0_0, 3, 1; +L_0x29e1fe0 .part v0x29c4970_0, 0, 1; +L_0x29e2320 .part v0x29c4970_0, 1, 1; +L_0x29e2210 .part v0x29c4970_0, 2, 1; +L_0x29e24e0 .part v0x29c4970_0, 3, 1; +L_0x29e23c0 .part v0x29c47b0_0, 0, 1; +L_0x29e2740 .part v0x29c47b0_0, 1, 1; +L_0x29e2610 .part v0x29c47b0_0, 2, 1; +L_0x29e2920 .part v0x29c47b0_0, 3, 1; +L_0x29e27e0 .part v0x29c46d0_0, 0, 1; +L_0x29e2b10 .part v0x29c46d0_0, 1, 1; +L_0x29e29c0 .part v0x29c46d0_0, 2, 1; +L_0x29e2a60 .part v0x29c46d0_0, 3, 1; +L_0x29e2bb0 .array/port v0x29c33b0, L_0x29e2f10; +L_0x29e2f10 .concat [ 4 2 0 0], v0x29c0670_0, L_0x2acb326b4060; +LS_0x29c4290_0_0 .concat8 [ 11 1 1 1], v0x29c37f0_2, L_0x29e29c0, L_0x29e2610, L_0x29e2210; +LS_0x29c4290_0_4 .concat8 [ 1 0 0 0], L_0x29e1e00; +L_0x29c4290 .concat8 [ 14 1 0 0], LS_0x29c4290_0_0, LS_0x29c4290_0_4; +LS_0x29e31f0_0_0 .concat8 [ 11 1 1 1], v0x29c37f0_3, L_0x29e2a60, L_0x29e2920, L_0x29e24e0; +LS_0x29e31f0_0_4 .concat8 [ 1 0 0 0], L_0x29e20e0; +L_0x29e31f0 .concat8 [ 14 1 0 0], LS_0x29e31f0_0_0, LS_0x29e31f0_0_4; +LS_0x29e3070_0_0 .concat8 [ 11 1 1 1], v0x29c37f0_0, L_0x29e27e0, L_0x29e23c0, L_0x29e1fe0; +LS_0x29e3070_0_4 .concat8 [ 1 0 0 0], L_0x29e1be0; +L_0x29e3070 .concat8 [ 14 1 0 0], LS_0x29e3070_0_0, LS_0x29e3070_0_4; +LS_0x29e37e0_0_0 .concat8 [ 11 1 1 1], v0x29c37f0_1, L_0x29e2b10, L_0x29e2740, L_0x29e2320; +LS_0x29e37e0_0_4 .concat8 [ 1 0 0 0], L_0x29e1ef0; +L_0x29e37e0 .concat8 [ 14 1 0 0], LS_0x29e37e0_0_0, LS_0x29e37e0_0_4; +L_0x29e34d0 .part L_0x29e0bf0, 14, 4; +L_0x29e3bf0 .part L_0x29e0bf0, 11, 3; +L_0x29e3a00 .part L_0x29e0bf0, 8, 3; +L_0x29e3e40 .part L_0x29e0bf0, 10, 4; +L_0x29e3c90 .part L_0x29e0bf0, 0, 11; +S_0x29c4db0 .scope module, "right" "tis100" 2 23, 3 49 0, S_0x2901970; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x29c4f80 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x29c4fc0 .param/str "memFile" 0 3 60, "anyRead/right.dat"; +L_0x29e3b30 .functor BUFZ 11, v0x29c5330_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29e3d30 .functor BUFZ 11, v0x29c5330_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29e4c40 .functor BUFZ 18, L_0x29e6c30, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x29c5330_0 .var/s "ACC", 10 0; +v0x29c5430_0 .var/s "BAK", 10 0; +v0x29c5510_0 .net "DST", 2 0, L_0x29e7d30; 1 drivers +v0x29c55d0_0 .net/s "IMM", 10 0, L_0x29e7dd0; 1 drivers +v0x29c56b0_0 .net "INST", 3 0, L_0x29e7650; 1 drivers +v0x29c5790_0 .net "LABEL", 3 0, L_0x29e7f80; 1 drivers +v0x29c5870_0 .var "PC", 3 0; +v0x29c5950_0 .var "PCNEXT", 3 0; +v0x29c5a30_0 .net "SRC", 2 0, L_0x29e7b40; 1 drivers +v0x29c5ba0_0 .net *"_s103", 0 0, L_0x29e5f70; 1 drivers +v0x29c5c80_0 .net *"_s107", 0 0, L_0x29e5e80; 1 drivers +v0x29c5d60_0 .net *"_s111", 0 0, L_0x29e6160; 1 drivers +v0x29c5e40_0 .net *"_s115", 0 0, L_0x29e6060; 1 drivers +v0x29c5f20_0 .net *"_s119", 0 0, L_0x29e63a0; 1 drivers +v0x29c6000_0 .net *"_s123", 0 0, L_0x29e6290; 1 drivers +v0x29c60e0_0 .net *"_s127", 0 0, L_0x29e6560; 1 drivers +v0x29c61c0_0 .net *"_s131", 0 0, L_0x29e6440; 1 drivers +v0x29c6370_0 .net *"_s135", 0 0, L_0x29e67c0; 1 drivers +v0x29c6410_0 .net *"_s139", 0 0, L_0x29e6690; 1 drivers +v0x29c64f0_0 .net *"_s143", 0 0, L_0x29e69a0; 1 drivers +v0x29c65d0_0 .net *"_s147", 0 0, L_0x29e6860; 1 drivers +v0x29c66b0_0 .net *"_s151", 0 0, L_0x29e6b90; 1 drivers +v0x29c6790_0 .net *"_s155", 0 0, L_0x29e6a40; 1 drivers +v0x29c6870_0 .net *"_s159", 0 0, L_0x29e6ae0; 1 drivers +v0x29c6950_0 .net *"_s160", 17 0, L_0x29e6c30; 1 drivers +v0x29c6a30_0 .net *"_s162", 5 0, L_0x29e6f90; 1 drivers +L_0x2acb326b40f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x29c6b10_0 .net *"_s165", 1 0, L_0x2acb326b40f0; 1 drivers +v0x29c8a40_2 .array/port v0x29c8a40, 2; +v0x29c6bf0_0 .net *"_s173", 10 0, v0x29c8a40_2; 1 drivers +v0x29c8a40_3 .array/port v0x29c8a40, 3; +v0x29c6cd0_0 .net *"_s179", 10 0, v0x29c8a40_3; 1 drivers +v0x29c8a40_0 .array/port v0x29c8a40, 0; +v0x29c6db0_0 .net *"_s185", 10 0, v0x29c8a40_0; 1 drivers +v0x29c8a40_1 .array/port v0x29c8a40, 1; +v0x29c6e90_0 .net *"_s191", 10 0, v0x29c8a40_1; 1 drivers +v0x29c6f70_0 .net *"_s23", 0 0, L_0x29e4370; 1 drivers +v0x29c7050_0 .net *"_s27", 0 0, L_0x29e44d0; 1 drivers +v0x29c62a0_0 .net *"_s31", 0 0, L_0x29e45a0; 1 drivers +v0x29c7320_0 .net *"_s36", 0 0, L_0x29e4870; 1 drivers +v0x29c7400_0 .net *"_s42", 0 0, L_0x29e4b00; 1 drivers +v0x29c74e0_0 .net *"_s46", 0 0, L_0x29e4ba0; 1 drivers +v0x29c75c0_0 .net *"_s50", 0 0, L_0x29e4cb0; 1 drivers +v0x29c76a0_0 .net *"_s55", 0 0, L_0x29e4f40; 1 drivers +v0x29c7780_0 .net *"_s61", 0 0, L_0x29e51b0; 1 drivers +v0x29c7860_0 .net *"_s65", 0 0, L_0x29e5250; 1 drivers +v0x29c7940_0 .net *"_s69", 0 0, L_0x29e5420; 1 drivers +v0x29c7a20_0 .net *"_s74", 0 0, L_0x29e5380; 1 drivers +v0x29c7b00_0 .net *"_s80", 0 0, L_0x29e5610; 1 drivers +v0x29c7be0_0 .net *"_s84", 0 0, L_0x29e5900; 1 drivers +v0x29c7cc0_0 .net *"_s88", 0 0, L_0x29e5840; 1 drivers +v0x29c7da0_0 .net *"_s93", 0 0, L_0x29e59a0; 1 drivers +v0x29c7e80_0 .net *"_s99", 0 0, L_0x29e5c60; 1 drivers +v0x29c7f60_0 .net/s "accOut", 10 0, L_0x29e3b30; 1 drivers +v0x29c8040_0 .net "anyHasData", 0 0, L_0x29e49b0; 1 drivers +v0x29c8100_0 .net "anyReadAck", 0 0, L_0x29e57a0; 1 drivers +v0x29c81c0_0 .net "anyWantData", 0 0, L_0x29e5030; 1 drivers +v0x29c8280_0 .net "anyWriteAck", 0 0, L_0x29e5d90; 1 drivers +v0x29c8340_0 .net "clk", 0 0, v0x29cfc10_0; alias, 1 drivers +o0x2acb32687128 .functor BUFZ 15, C4; HiZ drive +v0x29c83e0_0 .net "down", 14 0, o0x2acb32687128; 0 drivers +v0x29c84c0_0 .net "downOut", 14 0, L_0x29e73b0; 1 drivers +v0x29c85a0_0 .net "instruction", 17 0, L_0x29e4c40; 1 drivers +v0x29c8680 .array "instructions", 15 0, 17 0; +v0x29c8740_0 .var "last", 2 0; +v0x29c8820_0 .net "left", 14 0, L_0x29f3ed0; alias, 1 drivers +v0x29c88e0_0 .net "leftOut", 14 0, L_0x29e70f0; alias, 1 drivers +v0x29c8980_0 .var "mode", 2 0; +v0x29c8a40 .array/s "outVals", 2 5, 10 0; +v0x29c8bb0_0 .var "phase", 2 0; +v0x29c8c90_0 .net "portsHaveData", 5 2, L_0x29e4690; 1 drivers +v0x29c70f0_0 .net "portsWantData", 5 2, L_0x29e4d50; 1 drivers +v0x29c71d0_0 .net "readAckIn", 5 2, L_0x29e54c0; 1 drivers +v0x29c9140_0 .var "readAckOut", 5 2; +v0x29c91e0_0 .var "readTarget", 2 0; +v0x29c9280_0 .var/s "readValue", 10 0; +L_0x2acb326b40a8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x29c9320 .array "regVals", 0 7; +v0x29c9320_0 .net/s v0x29c9320 0, 10 0, L_0x2acb326b40a8; 1 drivers +v0x29c9320_1 .net/s v0x29c9320 1, 10 0, L_0x29e3d30; 1 drivers +v0x29c9320_2 .net/s v0x29c9320 2, 10 0, L_0x29e3da0; 1 drivers +v0x29c9320_3 .net/s v0x29c9320 3, 10 0, L_0x29e40a0; 1 drivers +v0x29c9320_4 .net/s v0x29c9320 4, 10 0, L_0x29e4140; 1 drivers +v0x29c9320_5 .net/s v0x29c9320 5, 10 0, L_0x29e4240; 1 drivers +o0x2acb32687548 .functor BUFZ 11, C4; HiZ drive +v0x29c9320_6 .net/s v0x29c9320 6, 10 0, o0x2acb32687548; 0 drivers +o0x2acb32687578 .functor BUFZ 11, C4; HiZ drive +v0x29c9320_7 .net/s v0x29c9320 7, 10 0, o0x2acb32687578; 0 drivers +o0x2acb326875a8 .functor BUFZ 15, C4; HiZ drive +v0x29c9530_0 .net "right", 14 0, o0x2acb326875a8; 0 drivers +v0x29c9610_0 .net "rightOut", 14 0, L_0x29e7920; 1 drivers +o0x2acb32687608 .functor BUFZ 15, C4; HiZ drive +v0x29c96f0_0 .net "up", 14 0, o0x2acb32687608; 0 drivers +v0x29c97d0_0 .net "upOut", 14 0, L_0x29e6ea0; 1 drivers +v0x29c98b0_0 .var "weHaveData", 5 2; +v0x29c9990_0 .var "weWantData", 5 2; +v0x29c9a70_0 .net "writeAckIn", 5 2, L_0x29e5a70; 1 drivers +v0x29c9b50_0 .var "writeAckOut", 5 2; +v0x29c9c30_0 .var "writeTarget", 2 0; +v0x29c9d10_0 .var/s "writeValue", 10 0; +L_0x29e3da0 .part L_0x29f3ed0, 0, 11; +L_0x29e40a0 .part o0x2acb326875a8, 0, 11; +L_0x29e4140 .part o0x2acb32687608, 0, 11; +L_0x29e4240 .part o0x2acb32687128, 0, 11; +L_0x29e4370 .part L_0x29f3ed0, 11, 1; +L_0x29e44d0 .part o0x2acb326875a8, 11, 1; +L_0x29e45a0 .part o0x2acb32687608, 11, 1; +L_0x29e4690 .concat8 [ 1 1 1 1], L_0x29e4370, L_0x29e44d0, L_0x29e45a0, L_0x29e4870; +L_0x29e4870 .part o0x2acb32687128, 11, 1; +L_0x29e49b0 .reduce/or L_0x29e4690; +L_0x29e4b00 .part L_0x29f3ed0, 12, 1; +L_0x29e4ba0 .part o0x2acb326875a8, 12, 1; +L_0x29e4cb0 .part o0x2acb32687608, 12, 1; +L_0x29e4d50 .concat8 [ 1 1 1 1], L_0x29e4b00, L_0x29e4ba0, L_0x29e4cb0, L_0x29e4f40; +L_0x29e4f40 .part o0x2acb32687128, 12, 1; +L_0x29e5030 .reduce/or L_0x29e4d50; +L_0x29e51b0 .part L_0x29f3ed0, 13, 1; +L_0x29e5250 .part o0x2acb326875a8, 13, 1; +L_0x29e5420 .part o0x2acb32687608, 13, 1; +L_0x29e54c0 .concat8 [ 1 1 1 1], L_0x29e51b0, L_0x29e5250, L_0x29e5420, L_0x29e5380; +L_0x29e5380 .part o0x2acb32687128, 13, 1; +L_0x29e57a0 .reduce/or L_0x29e54c0; +L_0x29e5610 .part L_0x29f3ed0, 14, 1; +L_0x29e5900 .part o0x2acb326875a8, 14, 1; +L_0x29e5840 .part o0x2acb32687608, 14, 1; +L_0x29e5a70 .concat8 [ 1 1 1 1], L_0x29e5610, L_0x29e5900, L_0x29e5840, L_0x29e59a0; +L_0x29e59a0 .part o0x2acb32687128, 14, 1; +L_0x29e5d90 .reduce/or L_0x29e5a70; +L_0x29e5c60 .part v0x29c9140_0, 0, 1; +L_0x29e5f70 .part v0x29c9140_0, 1, 1; +L_0x29e5e80 .part v0x29c9140_0, 2, 1; +L_0x29e6160 .part v0x29c9140_0, 3, 1; +L_0x29e6060 .part v0x29c9b50_0, 0, 1; +L_0x29e63a0 .part v0x29c9b50_0, 1, 1; +L_0x29e6290 .part v0x29c9b50_0, 2, 1; +L_0x29e6560 .part v0x29c9b50_0, 3, 1; +L_0x29e6440 .part v0x29c9990_0, 0, 1; +L_0x29e67c0 .part v0x29c9990_0, 1, 1; +L_0x29e6690 .part v0x29c9990_0, 2, 1; +L_0x29e69a0 .part v0x29c9990_0, 3, 1; +L_0x29e6860 .part v0x29c98b0_0, 0, 1; +L_0x29e6b90 .part v0x29c98b0_0, 1, 1; +L_0x29e6a40 .part v0x29c98b0_0, 2, 1; +L_0x29e6ae0 .part v0x29c98b0_0, 3, 1; +L_0x29e6c30 .array/port v0x29c8680, L_0x29e6f90; +L_0x29e6f90 .concat [ 4 2 0 0], v0x29c5870_0, L_0x2acb326b40f0; +LS_0x29e6ea0_0_0 .concat8 [ 11 1 1 1], v0x29c8a40_2, L_0x29e6a40, L_0x29e6690, L_0x29e6290; +LS_0x29e6ea0_0_4 .concat8 [ 1 0 0 0], L_0x29e5e80; +L_0x29e6ea0 .concat8 [ 14 1 0 0], LS_0x29e6ea0_0_0, LS_0x29e6ea0_0_4; +LS_0x29e73b0_0_0 .concat8 [ 11 1 1 1], v0x29c8a40_3, L_0x29e6ae0, L_0x29e69a0, L_0x29e6560; +LS_0x29e73b0_0_4 .concat8 [ 1 0 0 0], L_0x29e6160; +L_0x29e73b0 .concat8 [ 14 1 0 0], LS_0x29e73b0_0_0, LS_0x29e73b0_0_4; +LS_0x29e70f0_0_0 .concat8 [ 11 1 1 1], v0x29c8a40_0, L_0x29e6860, L_0x29e6440, L_0x29e6060; +LS_0x29e70f0_0_4 .concat8 [ 1 0 0 0], L_0x29e5c60; +L_0x29e70f0 .concat8 [ 14 1 0 0], LS_0x29e70f0_0_0, LS_0x29e70f0_0_4; +LS_0x29e7920_0_0 .concat8 [ 11 1 1 1], v0x29c8a40_1, L_0x29e6b90, L_0x29e67c0, L_0x29e63a0; +LS_0x29e7920_0_4 .concat8 [ 1 0 0 0], L_0x29e5f70; +L_0x29e7920 .concat8 [ 14 1 0 0], LS_0x29e7920_0_0, LS_0x29e7920_0_4; +L_0x29e7650 .part L_0x29e4c40, 14, 4; +L_0x29e7d30 .part L_0x29e4c40, 11, 3; +L_0x29e7b40 .part L_0x29e4c40, 8, 3; +L_0x29e7f80 .part L_0x29e4c40, 10, 4; +L_0x29e7dd0 .part L_0x29e4c40, 0, 11; +S_0x29c9f90 .scope module, "up" "tis100" 2 24, 3 49 0, S_0x2901970; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x29ca1b0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x29ca1f0 .param/str "memFile" 0 3 60, "anyRead/up.dat"; +L_0x29e7c70 .functor BUFZ 11, v0x29ca4b0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29e7e70 .functor BUFZ 11, v0x29ca4b0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x29e8d30 .functor BUFZ 18, L_0x29eacd0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x29ca4b0_0 .var/s "ACC", 10 0; +v0x29ca5b0_0 .var/s "BAK", 10 0; +v0x29ca690_0 .net "DST", 2 0, L_0x29ebe10; 1 drivers +v0x29ca750_0 .net/s "IMM", 10 0, L_0x29ebeb0; 1 drivers +v0x29ca830_0 .net "INST", 3 0, L_0x29eb6f0; 1 drivers +v0x29ca960_0 .net "LABEL", 3 0, L_0x29ec060; 1 drivers +v0x29caa40_0 .var "PC", 3 0; +v0x29cab20_0 .var "PCNEXT", 3 0; +v0x29cac00_0 .net "SRC", 2 0, L_0x29ebc20; 1 drivers +v0x29cad70_0 .net *"_s103", 0 0, L_0x29ea010; 1 drivers +v0x29cae50_0 .net *"_s107", 0 0, L_0x29e9f20; 1 drivers +v0x29caf30_0 .net *"_s111", 0 0, L_0x29ea200; 1 drivers +v0x29cb010_0 .net *"_s115", 0 0, L_0x29ea100; 1 drivers +v0x29cb0f0_0 .net *"_s119", 0 0, L_0x29ea440; 1 drivers +v0x29cb1d0_0 .net *"_s123", 0 0, L_0x29ea330; 1 drivers +v0x29cb2b0_0 .net *"_s127", 0 0, L_0x29ea600; 1 drivers +v0x29cb390_0 .net *"_s131", 0 0, L_0x29ea4e0; 1 drivers +v0x29cb540_0 .net *"_s135", 0 0, L_0x29ea860; 1 drivers +v0x29cb5e0_0 .net *"_s139", 0 0, L_0x29ea730; 1 drivers +v0x29cb6c0_0 .net *"_s143", 0 0, L_0x29eaa40; 1 drivers +v0x29cb7a0_0 .net *"_s147", 0 0, L_0x29ea900; 1 drivers +v0x29cb880_0 .net *"_s151", 0 0, L_0x29eac30; 1 drivers +v0x29cb960_0 .net *"_s155", 0 0, L_0x29eaae0; 1 drivers +v0x29cba40_0 .net *"_s159", 0 0, L_0x29eab80; 1 drivers +v0x29cbb20_0 .net *"_s160", 17 0, L_0x29eacd0; 1 drivers +v0x29cbc00_0 .net *"_s162", 5 0, L_0x29eb030; 1 drivers +L_0x2acb326b4180 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x29cbce0_0 .net *"_s165", 1 0, L_0x2acb326b4180; 1 drivers +v0x29cdca0_2 .array/port v0x29cdca0, 2; +v0x29cbdc0_0 .net *"_s173", 10 0, v0x29cdca0_2; 1 drivers +v0x29cdca0_3 .array/port v0x29cdca0, 3; +v0x29cbea0_0 .net *"_s179", 10 0, v0x29cdca0_3; 1 drivers +v0x29cdca0_0 .array/port v0x29cdca0, 0; +v0x29cbf80_0 .net *"_s185", 10 0, v0x29cdca0_0; 1 drivers +v0x29cdca0_1 .array/port v0x29cdca0, 1; +v0x29cc060_0 .net *"_s191", 10 0, v0x29cdca0_1; 1 drivers +v0x29cc140_0 .net *"_s23", 0 0, L_0x29e84f0; 1 drivers +v0x29cc220_0 .net *"_s27", 0 0, L_0x29e8610; 1 drivers +v0x29cb470_0 .net *"_s31", 0 0, L_0x29e8700; 1 drivers +v0x29cc4f0_0 .net *"_s36", 0 0, L_0x29e89d0; 1 drivers +v0x29cc5d0_0 .net *"_s42", 0 0, L_0x29e8bf0; 1 drivers +v0x29cc6b0_0 .net *"_s46", 0 0, L_0x29e8c90; 1 drivers +v0x29cc790_0 .net *"_s50", 0 0, L_0x29e8da0; 1 drivers +v0x29cc870_0 .net *"_s55", 0 0, L_0x29e8fe0; 1 drivers +v0x29cc950_0 .net *"_s61", 0 0, L_0x29e9250; 1 drivers +v0x29cca30_0 .net *"_s65", 0 0, L_0x29e9380; 1 drivers +v0x29ccb10_0 .net *"_s69", 0 0, L_0x29e9550; 1 drivers +v0x29ccbf0_0 .net *"_s74", 0 0, L_0x29e94b0; 1 drivers +v0x29cccd0_0 .net *"_s80", 0 0, L_0x29e96f0; 1 drivers +v0x29ccdb0_0 .net *"_s84", 0 0, L_0x29e99a0; 1 drivers +v0x29cce90_0 .net *"_s88", 0 0, L_0x29e98e0; 1 drivers +v0x29ccf70_0 .net *"_s93", 0 0, L_0x29e9a40; 1 drivers +v0x29cd050_0 .net *"_s99", 0 0, L_0x29e9d00; 1 drivers +v0x29cd130_0 .net/s "accOut", 10 0, L_0x29e7c70; 1 drivers +v0x29cd210_0 .net "anyHasData", 0 0, L_0x29e8b50; 1 drivers +v0x29cd2d0_0 .net "anyReadAck", 0 0, L_0x29e97f0; 1 drivers +v0x29cd390_0 .net "anyWantData", 0 0, L_0x29e90d0; 1 drivers +v0x29cd450_0 .net "anyWriteAck", 0 0, L_0x29e9e30; 1 drivers +v0x29cd510_0 .net "clk", 0 0, v0x29cfc10_0; alias, 1 drivers +v0x29cd640_0 .net "down", 14 0, L_0x29f3230; alias, 1 drivers +v0x29cd700_0 .net "downOut", 14 0, L_0x29eb450; alias, 1 drivers +v0x29cd7a0_0 .net "instruction", 17 0, L_0x29e8d30; 1 drivers +v0x29cd860 .array "instructions", 15 0, 17 0; +v0x29cd920_0 .var "last", 2 0; +o0x2acb326883b8 .functor BUFZ 15, C4; HiZ drive +v0x29cda00_0 .net "left", 14 0, o0x2acb326883b8; 0 drivers +v0x29cdae0_0 .net "leftOut", 14 0, L_0x29eb190; 1 drivers +v0x29cdbc0_0 .var "mode", 2 0; +v0x29cdca0 .array/s "outVals", 2 5, 10 0; +v0x29cde10_0 .var "phase", 2 0; +v0x29cdef0_0 .net "portsHaveData", 5 2, L_0x29e87f0; 1 drivers +v0x29cc2c0_0 .net "portsWantData", 5 2, L_0x29e8e40; 1 drivers +v0x29cc3a0_0 .net "readAckIn", 5 2, L_0x29e95f0; 1 drivers +v0x29ce3a0_0 .var "readAckOut", 5 2; +v0x29ce440_0 .var "readTarget", 2 0; +v0x29ce4e0_0 .var/s "readValue", 10 0; +L_0x2acb326b4138 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x29ce580 .array "regVals", 0 7; +v0x29ce580_0 .net/s v0x29ce580 0, 10 0, L_0x2acb326b4138; 1 drivers +v0x29ce580_1 .net/s v0x29ce580 1, 10 0, L_0x29e7e70; 1 drivers +v0x29ce580_2 .net/s v0x29ce580 2, 10 0, L_0x29e81e0; 1 drivers +v0x29ce580_3 .net/s v0x29ce580 3, 10 0, L_0x29e8280; 1 drivers +v0x29ce580_4 .net/s v0x29ce580 4, 10 0, L_0x29e8320; 1 drivers +v0x29ce580_5 .net/s v0x29ce580 5, 10 0, L_0x29e83f0; 1 drivers +o0x2acb32688778 .functor BUFZ 11, C4; HiZ drive +v0x29ce580_6 .net/s v0x29ce580 6, 10 0, o0x2acb32688778; 0 drivers +o0x2acb326887a8 .functor BUFZ 11, C4; HiZ drive +v0x29ce580_7 .net/s v0x29ce580 7, 10 0, o0x2acb326887a8; 0 drivers +o0x2acb326887d8 .functor BUFZ 15, C4; HiZ drive +v0x29ce790_0 .net "right", 14 0, o0x2acb326887d8; 0 drivers +v0x29ce870_0 .net "rightOut", 14 0, L_0x29eba00; 1 drivers +o0x2acb32688838 .functor BUFZ 15, C4; HiZ drive +v0x29ce950_0 .net "up", 14 0, o0x2acb32688838; 0 drivers +v0x29cea30_0 .net "upOut", 14 0, L_0x29eaf40; 1 drivers +v0x29ceb10_0 .var "weHaveData", 5 2; +v0x29cebf0_0 .var "weWantData", 5 2; +v0x29cecd0_0 .net "writeAckIn", 5 2, L_0x29e9b10; 1 drivers +v0x29cedb0_0 .var "writeAckOut", 5 2; +v0x29cee90_0 .var "writeTarget", 2 0; +v0x29cef70_0 .var/s "writeValue", 10 0; +L_0x29e81e0 .part o0x2acb326883b8, 0, 11; +L_0x29e8280 .part o0x2acb326887d8, 0, 11; +L_0x29e8320 .part o0x2acb32688838, 0, 11; +L_0x29e83f0 .part L_0x29f3230, 0, 11; +L_0x29e84f0 .part o0x2acb326883b8, 11, 1; +L_0x29e8610 .part o0x2acb326887d8, 11, 1; +L_0x29e8700 .part o0x2acb32688838, 11, 1; +L_0x29e87f0 .concat8 [ 1 1 1 1], L_0x29e84f0, L_0x29e8610, L_0x29e8700, L_0x29e89d0; +L_0x29e89d0 .part L_0x29f3230, 11, 1; +L_0x29e8b50 .reduce/or L_0x29e87f0; +L_0x29e8bf0 .part o0x2acb326883b8, 12, 1; +L_0x29e8c90 .part o0x2acb326887d8, 12, 1; +L_0x29e8da0 .part o0x2acb32688838, 12, 1; +L_0x29e8e40 .concat8 [ 1 1 1 1], L_0x29e8bf0, L_0x29e8c90, L_0x29e8da0, L_0x29e8fe0; +L_0x29e8fe0 .part L_0x29f3230, 12, 1; +L_0x29e90d0 .reduce/or L_0x29e8e40; +L_0x29e9250 .part o0x2acb326883b8, 13, 1; +L_0x29e9380 .part o0x2acb326887d8, 13, 1; +L_0x29e9550 .part o0x2acb32688838, 13, 1; +L_0x29e95f0 .concat8 [ 1 1 1 1], L_0x29e9250, L_0x29e9380, L_0x29e9550, L_0x29e94b0; +L_0x29e94b0 .part L_0x29f3230, 13, 1; +L_0x29e97f0 .reduce/or L_0x29e95f0; +L_0x29e96f0 .part o0x2acb326883b8, 14, 1; +L_0x29e99a0 .part o0x2acb326887d8, 14, 1; +L_0x29e98e0 .part o0x2acb32688838, 14, 1; +L_0x29e9b10 .concat8 [ 1 1 1 1], L_0x29e96f0, L_0x29e99a0, L_0x29e98e0, L_0x29e9a40; +L_0x29e9a40 .part L_0x29f3230, 14, 1; +L_0x29e9e30 .reduce/or L_0x29e9b10; +L_0x29e9d00 .part v0x29ce3a0_0, 0, 1; +L_0x29ea010 .part v0x29ce3a0_0, 1, 1; +L_0x29e9f20 .part v0x29ce3a0_0, 2, 1; +L_0x29ea200 .part v0x29ce3a0_0, 3, 1; +L_0x29ea100 .part v0x29cedb0_0, 0, 1; +L_0x29ea440 .part v0x29cedb0_0, 1, 1; +L_0x29ea330 .part v0x29cedb0_0, 2, 1; +L_0x29ea600 .part v0x29cedb0_0, 3, 1; +L_0x29ea4e0 .part v0x29cebf0_0, 0, 1; +L_0x29ea860 .part v0x29cebf0_0, 1, 1; +L_0x29ea730 .part v0x29cebf0_0, 2, 1; +L_0x29eaa40 .part v0x29cebf0_0, 3, 1; +L_0x29ea900 .part v0x29ceb10_0, 0, 1; +L_0x29eac30 .part v0x29ceb10_0, 1, 1; +L_0x29eaae0 .part v0x29ceb10_0, 2, 1; +L_0x29eab80 .part v0x29ceb10_0, 3, 1; +L_0x29eacd0 .array/port v0x29cd860, L_0x29eb030; +L_0x29eb030 .concat [ 4 2 0 0], v0x29caa40_0, L_0x2acb326b4180; +LS_0x29eaf40_0_0 .concat8 [ 11 1 1 1], v0x29cdca0_2, L_0x29eaae0, L_0x29ea730, L_0x29ea330; +LS_0x29eaf40_0_4 .concat8 [ 1 0 0 0], L_0x29e9f20; +L_0x29eaf40 .concat8 [ 14 1 0 0], LS_0x29eaf40_0_0, LS_0x29eaf40_0_4; +LS_0x29eb450_0_0 .concat8 [ 11 1 1 1], v0x29cdca0_3, L_0x29eab80, L_0x29eaa40, L_0x29ea600; +LS_0x29eb450_0_4 .concat8 [ 1 0 0 0], L_0x29ea200; +L_0x29eb450 .concat8 [ 14 1 0 0], LS_0x29eb450_0_0, LS_0x29eb450_0_4; +LS_0x29eb190_0_0 .concat8 [ 11 1 1 1], v0x29cdca0_0, L_0x29ea900, L_0x29ea4e0, L_0x29ea100; +LS_0x29eb190_0_4 .concat8 [ 1 0 0 0], L_0x29e9d00; +L_0x29eb190 .concat8 [ 14 1 0 0], LS_0x29eb190_0_0, LS_0x29eb190_0_4; +LS_0x29eba00_0_0 .concat8 [ 11 1 1 1], v0x29cdca0_1, L_0x29eac30, L_0x29ea860, L_0x29ea440; +LS_0x29eba00_0_4 .concat8 [ 1 0 0 0], L_0x29ea010; +L_0x29eba00 .concat8 [ 14 1 0 0], LS_0x29eba00_0_0, LS_0x29eba00_0_4; +L_0x29eb6f0 .part L_0x29e8d30, 14, 4; +L_0x29ebe10 .part L_0x29e8d30, 11, 3; +L_0x29ebc20 .part L_0x29e8d30, 8, 3; +L_0x29ec060 .part L_0x29e8d30, 10, 4; +L_0x29ebeb0 .part L_0x29e8d30, 0, 11; + .scope S_0x29bfba0; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29c3710_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29c3930_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29c3470_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29c00e0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29c01e0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c0670_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c3ec0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c47b0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c4970_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c46d0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c37f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c37f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c37f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c37f0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x29bfde0, v0x29c33b0 {0 0 0}; + %end; + .thread T_0; + .scope S_0x29bfba0; +T_1 ; + %wait E_0x2934f90; + %load/vec4 v0x29c3710_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %jmp T_1.3; +T_1.0 ; + %load/vec4 v0x29c3930_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.6, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0x29c0460_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_1.8, 5; + %load/vec4 v0x29c0830_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_1.10, 5; + %load/vec4 v0x29c0830_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0x29c0830_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_1.12, 5; + %load/vec4 v0x29c3a10_0; + %load/vec4 v0x29c0830_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0x29c0830_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c0830_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %load/vec4 v0x29c0830_0; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.15; +T_1.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %load/vec4 v0x29c0830_0; + %assign/vec4 v0x29c3fa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c0830_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; + %load/vec4 v0x29c0830_0; + %assign/vec4 v0x29c3470_0, 0; +T_1.15 ; + %jmp T_1.13; +T_1.12 ; + %load/vec4 v0x29c0830_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.16, 4; + %load/vec4 v0x29c3470_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_1.18, 4; + %load/vec4 v0x29c3470_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %jmp T_1.19; +T_1.18 ; + %load/vec4 v0x29c3a10_0; + %load/vec4 v0x29c3470_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.20, 8; + %load/vec4 v0x29c3470_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c3470_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %jmp T_1.21; +T_1.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %load/vec4 v0x29c3470_0; + %assign/vec4 v0x29c3fa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c3470_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; +T_1.21 ; +T_1.19 ; + %jmp T_1.17; +T_1.16 ; + %load/vec4 v0x29c0830_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.22, 4; + %load/vec4 v0x29c2d20_0; + %flag_set/vec4 8; + %jmp/0xz T_1.24, 8; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.27; +T_1.26 ; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.29; +T_1.28 ; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.31; +T_1.30 ; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c3470_0, 0; +T_1.32 ; +T_1.31 ; +T_1.29 ; +T_1.27 ; + %jmp T_1.25; +T_1.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %load/vec4 v0x29c0830_0; + %assign/vec4 v0x29c3fa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; +T_1.25 ; +T_1.22 ; +T_1.17 ; +T_1.13 ; +T_1.11 ; +T_1.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0x29c0460_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_1.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_1.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_1.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_1.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_1.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_1.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_1.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_1.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_1.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_1.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_1.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_1.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_1.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_1.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_1.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_1.49, 6; + %jmp T_1.50; +T_1.34 ; + %load/vec4 v0x29c00e0_0; + %load/vec4 v0x29c4080_0; + %add; + %assign/vec4 v0x29c00e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.35 ; + %load/vec4 v0x29c00e0_0; + %load/vec4 v0x29c4080_0; + %sub; + %assign/vec4 v0x29c00e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.36 ; + %load/vec4 v0x29c0670_0; + %pad/u 11; + %load/vec4 v0x29c4080_0; + %add; + %pad/u 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.37 ; + %load/vec4 v0x29c4080_0; + %assign/vec4 v0x29c4b30_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.38 ; + %load/vec4 v0x29c0380_0; + %assign/vec4 v0x29c4b30_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.39 ; + %load/vec4 v0x29c00e0_0; + %load/vec4 v0x29c0380_0; + %add; + %assign/vec4 v0x29c00e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.40 ; + %load/vec4 v0x29c00e0_0; + %load/vec4 v0x29c0380_0; + %sub; + %assign/vec4 v0x29c00e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.41 ; + %load/vec4 v0x29c0670_0; + %pad/u 11; + %load/vec4 v0x29c0380_0; + %add; + %pad/u 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.42 ; + %load/vec4 v0x29c01e0_0; + %assign/vec4 v0x29c00e0_0, 0; + %load/vec4 v0x29c00e0_0; + %assign/vec4 v0x29c01e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.43 ; + %load/vec4 v0x29c00e0_0; + %assign/vec4 v0x29c01e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.44 ; + %load/vec4 v0x29c00e0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x29c00e0_0, 0; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.45 ; + %load/vec4 v0x29c0590_0; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.50; +T_1.46 ; + %load/vec4 v0x29c00e0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_1.51, 4; + %load/vec4 v0x29c0590_0; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.52; +T_1.51 ; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; +T_1.52 ; + %jmp T_1.50; +T_1.47 ; + %load/vec4 v0x29c00e0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.53, 4; + %load/vec4 v0x29c0590_0; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.54; +T_1.53 ; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; +T_1.54 ; + %jmp T_1.50; +T_1.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x29c00e0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_1.55, 5; + %load/vec4 v0x29c0590_0; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.56; +T_1.55 ; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; +T_1.56 ; + %jmp T_1.50; +T_1.49 ; + %load/vec4 v0x29c00e0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_1.57, 5; + %load/vec4 v0x29c0590_0; + %assign/vec4 v0x29c0750_0, 0; + %jmp T_1.58; +T_1.57 ; + %load/vec4 v0x29c0670_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c0750_0, 0; +T_1.58 ; + %jmp T_1.50; +T_1.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x29c0460_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x29c0460_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_1.59, 4; + %load/vec4 v0x29c02c0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x29c02c0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29c3470_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_1.61, 9; + %load/vec4 v0x29c02c0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_1.63, 4; + %load/vec4 v0x29c4b30_0; + %assign/vec4 v0x29c00e0_0, 0; +T_1.63 ; + %jmp T_1.62; +T_1.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %load/vec4 v0x29c02c0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.65, 4; + %load/vec4 v0x29c3470_0; + %assign/vec4 v0x29c4a50_0, 0; + %load/vec4 v0x29c4b30_0; + %load/vec4 v0x29c3470_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c3470_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %jmp T_1.66; +T_1.65 ; + %load/vec4 v0x29c02c0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.67, 4; + %load/vec4 v0x29c02c0_0; + %assign/vec4 v0x29c4a50_0, 0; + %load/vec4 v0x29c4b30_0; + %load/vec4 v0x29c02c0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c02c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c02c0_0; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.68; +T_1.67 ; + %load/vec4 v0x29c2ea0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.69, 8; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.72; +T_1.71 ; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.74; +T_1.73 ; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.76; +T_1.75 ; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c3470_0, 0; +T_1.77 ; +T_1.76 ; +T_1.74 ; +T_1.72 ; + %jmp T_1.70; +T_1.69 ; + %load/vec4 v0x29c02c0_0; + %assign/vec4 v0x29c4a50_0, 0; +T_1.70 ; +T_1.68 ; +T_1.66 ; +T_1.62 ; +T_1.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.1 ; + %load/vec4 v0x29c3930_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.81, 6; + %jmp T_1.82; +T_1.79 ; + %load/vec4 v0x29c3fa0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.83, 4; + %load/vec4 v0x29c2d20_0; + %flag_set/vec4 8; + %jmp/0xz T_1.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c47b0_0, 0, 4; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.88; +T_1.87 ; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.90; +T_1.89 ; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.92; +T_1.91 ; + %load/vec4 v0x29c3a10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c3470_0, 0; +T_1.93 ; +T_1.92 ; +T_1.90 ; +T_1.88 ; +T_1.85 ; + %jmp T_1.84; +T_1.83 ; + %load/vec4 v0x29c3a10_0; + %load/vec4 v0x29c3fa0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %load/vec4 v0x29c3fa0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c4160, 4; + %assign/vec4 v0x29c4080_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c3fa0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c3ec0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c3fa0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c47b0_0, 4, 5; + %load/vec4 v0x29c3fa0_0; + %assign/vec4 v0x29c3470_0, 0; +T_1.95 ; +T_1.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.82; +T_1.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.82; +T_1.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.82; +T_1.82 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x29c3930_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.99, 6; + %jmp T_1.100; +T_1.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.100; +T_1.98 ; + %load/vec4 v0x29c4a50_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.101, 4; + %load/vec4 v0x29c2ea0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.103, 8; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.106; +T_1.105 ; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.108; +T_1.107 ; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c3470_0, 0; + %jmp T_1.110; +T_1.109 ; + %load/vec4 v0x29c1f30_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c4a50_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c46d0_0, 4, 5; + %load/vec4 v0x29c4b30_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c37f0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c3470_0, 0; +T_1.111 ; +T_1.110 ; +T_1.108 ; +T_1.106 ; +T_1.103 ; +T_1.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.100; +T_1.99 ; + %load/vec4 v0x29c4a50_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.113, 4; + %load/vec4 v0x29c4890_0; + %load/vec4 v0x29c4a50_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x29c4a50_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x29c46d0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c3710_0, 0; + %load/vec4 v0x29c4a50_0; + %assign/vec4 v0x29c3470_0, 0; +T_1.115 ; +T_1.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c3930_0, 0; + %jmp T_1.100; +T_1.100 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.3 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1; + .scope S_0x29bfba0; +T_2 ; + %wait E_0x2912800; + %load/vec4 v0x29c3930_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29c3710_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x29c0750_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %load/vec4 v0x29c0750_0; + %assign/vec4 v0x29c0670_0, 0; +T_2.0 ; + %load/vec4 v0x29c3930_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_2.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c3ec0_0, 0, 4; +T_2.2 ; + %jmp T_2; + .thread T_2; + .scope S_0x29c4db0; +T_3 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29c8980_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29c8bb0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29c8740_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29c5330_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29c5430_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c5870_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c9140_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c9990_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c9b50_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c98b0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c8a40, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c8a40, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c8a40, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29c8a40, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x29c4fc0, v0x29c8680 {0 0 0}; + %end; + .thread T_3; + .scope S_0x29c4db0; +T_4 ; + %wait E_0x2934f90; + %load/vec4 v0x29c8980_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0x29c8bb0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.6, 6; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0x29c56b0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_4.8, 5; + %load/vec4 v0x29c5a30_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_4.10, 5; + %load/vec4 v0x29c5a30_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %jmp T_4.11; +T_4.10 ; + %load/vec4 v0x29c5a30_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_4.12, 5; + %load/vec4 v0x29c8c90_0; + %load/vec4 v0x29c5a30_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.14, 8; + %load/vec4 v0x29c5a30_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c5a30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %load/vec4 v0x29c5a30_0; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.15; +T_4.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %load/vec4 v0x29c5a30_0; + %assign/vec4 v0x29c91e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c5a30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c9990_0, 4, 5; + %load/vec4 v0x29c5a30_0; + %assign/vec4 v0x29c8740_0, 0; +T_4.15 ; + %jmp T_4.13; +T_4.12 ; + %load/vec4 v0x29c5a30_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.16, 4; + %load/vec4 v0x29c8740_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_4.18, 4; + %load/vec4 v0x29c8740_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %jmp T_4.19; +T_4.18 ; + %load/vec4 v0x29c8c90_0; + %load/vec4 v0x29c8740_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.20, 8; + %load/vec4 v0x29c8740_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c8740_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %jmp T_4.21; +T_4.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %load/vec4 v0x29c8740_0; + %assign/vec4 v0x29c91e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c8740_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c9990_0, 4, 5; +T_4.21 ; +T_4.19 ; + %jmp T_4.17; +T_4.16 ; + %load/vec4 v0x29c5a30_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.22, 4; + %load/vec4 v0x29c8040_0; + %flag_set/vec4 8; + %jmp/0xz T_4.24, 8; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.27; +T_4.26 ; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.29; +T_4.28 ; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.31; +T_4.30 ; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c8740_0, 0; +T_4.32 ; +T_4.31 ; +T_4.29 ; +T_4.27 ; + %jmp T_4.25; +T_4.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %load/vec4 v0x29c5a30_0; + %assign/vec4 v0x29c91e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9990_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9990_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9990_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9990_0, 4, 5; +T_4.25 ; +T_4.22 ; +T_4.17 ; +T_4.13 ; +T_4.11 ; +T_4.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0x29c56b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_4.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_4.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_4.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_4.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_4.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_4.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_4.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_4.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_4.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_4.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_4.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_4.49, 6; + %jmp T_4.50; +T_4.34 ; + %load/vec4 v0x29c5330_0; + %load/vec4 v0x29c9280_0; + %add; + %assign/vec4 v0x29c5330_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.35 ; + %load/vec4 v0x29c5330_0; + %load/vec4 v0x29c9280_0; + %sub; + %assign/vec4 v0x29c5330_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.36 ; + %load/vec4 v0x29c5870_0; + %pad/u 11; + %load/vec4 v0x29c9280_0; + %add; + %pad/u 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.37 ; + %load/vec4 v0x29c9280_0; + %assign/vec4 v0x29c9d10_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.38 ; + %load/vec4 v0x29c55d0_0; + %assign/vec4 v0x29c9d10_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.39 ; + %load/vec4 v0x29c5330_0; + %load/vec4 v0x29c55d0_0; + %add; + %assign/vec4 v0x29c5330_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.40 ; + %load/vec4 v0x29c5330_0; + %load/vec4 v0x29c55d0_0; + %sub; + %assign/vec4 v0x29c5330_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.41 ; + %load/vec4 v0x29c5870_0; + %pad/u 11; + %load/vec4 v0x29c55d0_0; + %add; + %pad/u 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.42 ; + %load/vec4 v0x29c5430_0; + %assign/vec4 v0x29c5330_0, 0; + %load/vec4 v0x29c5330_0; + %assign/vec4 v0x29c5430_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.43 ; + %load/vec4 v0x29c5330_0; + %assign/vec4 v0x29c5430_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.44 ; + %load/vec4 v0x29c5330_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x29c5330_0, 0; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.45 ; + %load/vec4 v0x29c5790_0; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.50; +T_4.46 ; + %load/vec4 v0x29c5330_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_4.51, 4; + %load/vec4 v0x29c5790_0; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.52; +T_4.51 ; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; +T_4.52 ; + %jmp T_4.50; +T_4.47 ; + %load/vec4 v0x29c5330_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_4.53, 4; + %load/vec4 v0x29c5790_0; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.54; +T_4.53 ; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; +T_4.54 ; + %jmp T_4.50; +T_4.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x29c5330_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_4.55, 5; + %load/vec4 v0x29c5790_0; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.56; +T_4.55 ; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; +T_4.56 ; + %jmp T_4.50; +T_4.49 ; + %load/vec4 v0x29c5330_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_4.57, 5; + %load/vec4 v0x29c5790_0; + %assign/vec4 v0x29c5950_0, 0; + %jmp T_4.58; +T_4.57 ; + %load/vec4 v0x29c5870_0; + %addi 1, 0, 4; + %assign/vec4 v0x29c5950_0, 0; +T_4.58 ; + %jmp T_4.50; +T_4.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.7; +T_4.6 ; + %load/vec4 v0x29c56b0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x29c56b0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_4.59, 4; + %load/vec4 v0x29c5510_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x29c5510_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29c8740_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_4.61, 9; + %load/vec4 v0x29c5510_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_4.63, 4; + %load/vec4 v0x29c9d10_0; + %assign/vec4 v0x29c5330_0, 0; +T_4.63 ; + %jmp T_4.62; +T_4.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %load/vec4 v0x29c5510_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.65, 4; + %load/vec4 v0x29c8740_0; + %assign/vec4 v0x29c9c30_0, 0; + %load/vec4 v0x29c9d10_0; + %load/vec4 v0x29c8740_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c8740_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %jmp T_4.66; +T_4.65 ; + %load/vec4 v0x29c5510_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.67, 4; + %load/vec4 v0x29c5510_0; + %assign/vec4 v0x29c9c30_0, 0; + %load/vec4 v0x29c9d10_0; + %load/vec4 v0x29c5510_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c5510_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c5510_0; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.68; +T_4.67 ; + %load/vec4 v0x29c81c0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.69, 8; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.72; +T_4.71 ; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.74; +T_4.73 ; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.76; +T_4.75 ; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c8740_0, 0; +T_4.77 ; +T_4.76 ; +T_4.74 ; +T_4.72 ; + %jmp T_4.70; +T_4.69 ; + %load/vec4 v0x29c5510_0; + %assign/vec4 v0x29c9c30_0, 0; +T_4.70 ; +T_4.68 ; +T_4.66 ; +T_4.62 ; +T_4.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.1 ; + %load/vec4 v0x29c8bb0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.81, 6; + %jmp T_4.82; +T_4.79 ; + %load/vec4 v0x29c91e0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.83, 4; + %load/vec4 v0x29c8040_0; + %flag_set/vec4 8; + %jmp/0xz T_4.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c9990_0, 0, 4; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.88; +T_4.87 ; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.90; +T_4.89 ; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.92; +T_4.91 ; + %load/vec4 v0x29c8c90_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c8740_0, 0; +T_4.93 ; +T_4.92 ; +T_4.90 ; +T_4.88 ; +T_4.85 ; + %jmp T_4.84; +T_4.83 ; + %load/vec4 v0x29c8c90_0; + %load/vec4 v0x29c91e0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %load/vec4 v0x29c91e0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29c9320, 4; + %assign/vec4 v0x29c9280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c91e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c9140_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29c91e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29c9990_0, 4, 5; + %load/vec4 v0x29c91e0_0; + %assign/vec4 v0x29c8740_0, 0; +T_4.95 ; +T_4.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.82; +T_4.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.82; +T_4.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.82; +T_4.82 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x29c8bb0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.99, 6; + %jmp T_4.100; +T_4.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.100; +T_4.98 ; + %load/vec4 v0x29c9c30_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.101, 4; + %load/vec4 v0x29c81c0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.103, 8; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.106; +T_4.105 ; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.108; +T_4.107 ; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29c8740_0, 0; + %jmp T_4.110; +T_4.109 ; + %load/vec4 v0x29c70f0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c9c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29c98b0_0, 4, 5; + %load/vec4 v0x29c9d10_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29c8a40, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29c8740_0, 0; +T_4.111 ; +T_4.110 ; +T_4.108 ; +T_4.106 ; +T_4.103 ; +T_4.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.100; +T_4.99 ; + %load/vec4 v0x29c9c30_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.113, 4; + %load/vec4 v0x29c9a70_0; + %load/vec4 v0x29c9c30_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x29c9c30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x29c98b0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c8980_0, 0; + %load/vec4 v0x29c9c30_0; + %assign/vec4 v0x29c8740_0, 0; +T_4.115 ; +T_4.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29c8bb0_0, 0; + %jmp T_4.100; +T_4.100 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0x29c4db0; +T_5 ; + %wait E_0x2912800; + %load/vec4 v0x29c8bb0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29c8980_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x29c5950_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %load/vec4 v0x29c5950_0; + %assign/vec4 v0x29c5870_0, 0; +T_5.0 ; + %load/vec4 v0x29c8bb0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_5.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29c9140_0, 0, 4; +T_5.2 ; + %jmp T_5; + .thread T_5; + .scope S_0x29c9f90; +T_6 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29cdbc0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29cde10_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29cd920_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29ca4b0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29ca5b0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29caa40_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ce3a0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29cebf0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29cedb0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ceb10_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cdca0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cdca0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cdca0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cdca0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x29ca1f0, v0x29cd860 {0 0 0}; + %end; + .thread T_6; + .scope S_0x29c9f90; +T_7 ; + %wait E_0x2934f90; + %load/vec4 v0x29cdbc0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.2, 6; + %jmp T_7.3; +T_7.0 ; + %load/vec4 v0x29cde10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.6, 6; + %jmp T_7.7; +T_7.4 ; + %load/vec4 v0x29ca830_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_7.8, 5; + %load/vec4 v0x29cac00_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_7.10, 5; + %load/vec4 v0x29cac00_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %jmp T_7.11; +T_7.10 ; + %load/vec4 v0x29cac00_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_7.12, 5; + %load/vec4 v0x29cdef0_0; + %load/vec4 v0x29cac00_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.14, 8; + %load/vec4 v0x29cac00_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29cac00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %load/vec4 v0x29cac00_0; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.15; +T_7.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %load/vec4 v0x29cac00_0; + %assign/vec4 v0x29ce440_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29cac00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; + %load/vec4 v0x29cac00_0; + %assign/vec4 v0x29cd920_0, 0; +T_7.15 ; + %jmp T_7.13; +T_7.12 ; + %load/vec4 v0x29cac00_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.16, 4; + %load/vec4 v0x29cd920_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_7.18, 4; + %load/vec4 v0x29cd920_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %jmp T_7.19; +T_7.18 ; + %load/vec4 v0x29cdef0_0; + %load/vec4 v0x29cd920_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.20, 8; + %load/vec4 v0x29cd920_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29cd920_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %jmp T_7.21; +T_7.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %load/vec4 v0x29cd920_0; + %assign/vec4 v0x29ce440_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29cd920_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; +T_7.21 ; +T_7.19 ; + %jmp T_7.17; +T_7.16 ; + %load/vec4 v0x29cac00_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.22, 4; + %load/vec4 v0x29cd210_0; + %flag_set/vec4 8; + %jmp/0xz T_7.24, 8; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.27; +T_7.26 ; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.29; +T_7.28 ; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.31; +T_7.30 ; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29cd920_0, 0; +T_7.32 ; +T_7.31 ; +T_7.29 ; +T_7.27 ; + %jmp T_7.25; +T_7.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %load/vec4 v0x29cac00_0; + %assign/vec4 v0x29ce440_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; +T_7.25 ; +T_7.22 ; +T_7.17 ; +T_7.13 ; +T_7.11 ; +T_7.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.7; +T_7.5 ; + %load/vec4 v0x29ca830_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_7.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_7.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_7.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_7.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_7.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_7.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_7.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_7.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_7.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_7.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_7.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_7.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_7.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_7.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_7.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_7.49, 6; + %jmp T_7.50; +T_7.34 ; + %load/vec4 v0x29ca4b0_0; + %load/vec4 v0x29ce4e0_0; + %add; + %assign/vec4 v0x29ca4b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.35 ; + %load/vec4 v0x29ca4b0_0; + %load/vec4 v0x29ce4e0_0; + %sub; + %assign/vec4 v0x29ca4b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.36 ; + %load/vec4 v0x29caa40_0; + %pad/u 11; + %load/vec4 v0x29ce4e0_0; + %add; + %pad/u 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.37 ; + %load/vec4 v0x29ce4e0_0; + %assign/vec4 v0x29cef70_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.38 ; + %load/vec4 v0x29ca750_0; + %assign/vec4 v0x29cef70_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.39 ; + %load/vec4 v0x29ca4b0_0; + %load/vec4 v0x29ca750_0; + %add; + %assign/vec4 v0x29ca4b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.40 ; + %load/vec4 v0x29ca4b0_0; + %load/vec4 v0x29ca750_0; + %sub; + %assign/vec4 v0x29ca4b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.41 ; + %load/vec4 v0x29caa40_0; + %pad/u 11; + %load/vec4 v0x29ca750_0; + %add; + %pad/u 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.42 ; + %load/vec4 v0x29ca5b0_0; + %assign/vec4 v0x29ca4b0_0, 0; + %load/vec4 v0x29ca4b0_0; + %assign/vec4 v0x29ca5b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.43 ; + %load/vec4 v0x29ca4b0_0; + %assign/vec4 v0x29ca5b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.44 ; + %load/vec4 v0x29ca4b0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x29ca4b0_0, 0; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.45 ; + %load/vec4 v0x29ca960_0; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.50; +T_7.46 ; + %load/vec4 v0x29ca4b0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_7.51, 4; + %load/vec4 v0x29ca960_0; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.52; +T_7.51 ; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; +T_7.52 ; + %jmp T_7.50; +T_7.47 ; + %load/vec4 v0x29ca4b0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_7.53, 4; + %load/vec4 v0x29ca960_0; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.54; +T_7.53 ; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; +T_7.54 ; + %jmp T_7.50; +T_7.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x29ca4b0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_7.55, 5; + %load/vec4 v0x29ca960_0; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.56; +T_7.55 ; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; +T_7.56 ; + %jmp T_7.50; +T_7.49 ; + %load/vec4 v0x29ca4b0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_7.57, 5; + %load/vec4 v0x29ca960_0; + %assign/vec4 v0x29cab20_0, 0; + %jmp T_7.58; +T_7.57 ; + %load/vec4 v0x29caa40_0; + %addi 1, 0, 4; + %assign/vec4 v0x29cab20_0, 0; +T_7.58 ; + %jmp T_7.50; +T_7.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.7; +T_7.6 ; + %load/vec4 v0x29ca830_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x29ca830_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_7.59, 4; + %load/vec4 v0x29ca690_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x29ca690_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29cd920_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_7.61, 9; + %load/vec4 v0x29ca690_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_7.63, 4; + %load/vec4 v0x29cef70_0; + %assign/vec4 v0x29ca4b0_0, 0; +T_7.63 ; + %jmp T_7.62; +T_7.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %load/vec4 v0x29ca690_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.65, 4; + %load/vec4 v0x29cd920_0; + %assign/vec4 v0x29cee90_0, 0; + %load/vec4 v0x29cef70_0; + %load/vec4 v0x29cd920_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29cd920_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %jmp T_7.66; +T_7.65 ; + %load/vec4 v0x29ca690_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.67, 4; + %load/vec4 v0x29ca690_0; + %assign/vec4 v0x29cee90_0, 0; + %load/vec4 v0x29cef70_0; + %load/vec4 v0x29ca690_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29ca690_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29ca690_0; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.68; +T_7.67 ; + %load/vec4 v0x29cd390_0; + %flag_set/vec4 8; + %jmp/0xz T_7.69, 8; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.72; +T_7.71 ; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.74; +T_7.73 ; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.76; +T_7.75 ; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29cd920_0, 0; +T_7.77 ; +T_7.76 ; +T_7.74 ; +T_7.72 ; + %jmp T_7.70; +T_7.69 ; + %load/vec4 v0x29ca690_0; + %assign/vec4 v0x29cee90_0, 0; +T_7.70 ; +T_7.68 ; +T_7.66 ; +T_7.62 ; +T_7.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.7; +T_7.7 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.1 ; + %load/vec4 v0x29cde10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.81, 6; + %jmp T_7.82; +T_7.79 ; + %load/vec4 v0x29ce440_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.83, 4; + %load/vec4 v0x29cd210_0; + %flag_set/vec4 8; + %jmp/0xz T_7.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29cebf0_0, 0, 4; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.88; +T_7.87 ; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.90; +T_7.89 ; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.92; +T_7.91 ; + %load/vec4 v0x29cdef0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29cd920_0, 0; +T_7.93 ; +T_7.92 ; +T_7.90 ; +T_7.88 ; +T_7.85 ; + %jmp T_7.84; +T_7.83 ; + %load/vec4 v0x29cdef0_0; + %load/vec4 v0x29ce440_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %load/vec4 v0x29ce440_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29ce580, 4; + %assign/vec4 v0x29ce4e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29ce440_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ce3a0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29ce440_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29cebf0_0, 4, 5; + %load/vec4 v0x29ce440_0; + %assign/vec4 v0x29cd920_0, 0; +T_7.95 ; +T_7.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.82; +T_7.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.82; +T_7.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.82; +T_7.82 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0x29cde10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.99, 6; + %jmp T_7.100; +T_7.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.100; +T_7.98 ; + %load/vec4 v0x29cee90_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.101, 4; + %load/vec4 v0x29cd390_0; + %flag_set/vec4 8; + %jmp/0xz T_7.103, 8; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.106; +T_7.105 ; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.108; +T_7.107 ; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29cd920_0, 0; + %jmp T_7.110; +T_7.109 ; + %load/vec4 v0x29cc2c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29cee90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ceb10_0, 4, 5; + %load/vec4 v0x29cef70_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29cdca0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29cd920_0, 0; +T_7.111 ; +T_7.110 ; +T_7.108 ; +T_7.106 ; +T_7.103 ; +T_7.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.100; +T_7.99 ; + %load/vec4 v0x29cee90_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.113, 4; + %load/vec4 v0x29cecd0_0; + %load/vec4 v0x29cee90_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x29cee90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x29ceb10_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29cdbc0_0, 0; + %load/vec4 v0x29cee90_0; + %assign/vec4 v0x29cd920_0, 0; +T_7.115 ; +T_7.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29cde10_0, 0; + %jmp T_7.100; +T_7.100 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.3 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7; + .scope S_0x29c9f90; +T_8 ; + %wait E_0x2912800; + %load/vec4 v0x29cde10_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29cdbc0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x29cab20_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x29cab20_0; + %assign/vec4 v0x29caa40_0, 0; +T_8.0 ; + %load/vec4 v0x29cde10_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_8.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ce3a0_0, 0, 4; +T_8.2 ; + %jmp T_8; + .thread T_8; + .scope S_0x29ba9b0; +T_9 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29be5c0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29be7e0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29be320_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29baee0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29bafe0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bb470_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bed70_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bf5a0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bf760_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bf4e0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29be6a0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29be6a0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29be6a0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29be6a0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x29babe0, v0x29be260 {0 0 0}; + %end; + .thread T_9; + .scope S_0x29ba9b0; +T_10 ; + %wait E_0x2934f90; + %load/vec4 v0x29be5c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.2, 6; + %jmp T_10.3; +T_10.0 ; + %load/vec4 v0x29be7e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.6, 6; + %jmp T_10.7; +T_10.4 ; + %load/vec4 v0x29bb260_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_10.8, 5; + %load/vec4 v0x29bb630_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_10.10, 5; + %load/vec4 v0x29bb630_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %jmp T_10.11; +T_10.10 ; + %load/vec4 v0x29bb630_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_10.12, 5; + %load/vec4 v0x29be8c0_0; + %load/vec4 v0x29bb630_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.14, 8; + %load/vec4 v0x29bb630_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29bb630_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %load/vec4 v0x29bb630_0; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.15; +T_10.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %load/vec4 v0x29bb630_0; + %assign/vec4 v0x29bee10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29bb630_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; + %load/vec4 v0x29bb630_0; + %assign/vec4 v0x29be320_0, 0; +T_10.15 ; + %jmp T_10.13; +T_10.12 ; + %load/vec4 v0x29bb630_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.16, 4; + %load/vec4 v0x29be320_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_10.18, 4; + %load/vec4 v0x29be320_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %jmp T_10.19; +T_10.18 ; + %load/vec4 v0x29be8c0_0; + %load/vec4 v0x29be320_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.20, 8; + %load/vec4 v0x29be320_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29be320_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %jmp T_10.21; +T_10.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %load/vec4 v0x29be320_0; + %assign/vec4 v0x29bee10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29be320_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; +T_10.21 ; +T_10.19 ; + %jmp T_10.17; +T_10.16 ; + %load/vec4 v0x29bb630_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.22, 4; + %load/vec4 v0x29bdc40_0; + %flag_set/vec4 8; + %jmp/0xz T_10.24, 8; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.27; +T_10.26 ; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.29; +T_10.28 ; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.31; +T_10.30 ; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29be320_0, 0; +T_10.32 ; +T_10.31 ; +T_10.29 ; +T_10.27 ; + %jmp T_10.25; +T_10.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %load/vec4 v0x29bb630_0; + %assign/vec4 v0x29bee10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; +T_10.25 ; +T_10.22 ; +T_10.17 ; +T_10.13 ; +T_10.11 ; +T_10.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.7; +T_10.5 ; + %load/vec4 v0x29bb260_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_10.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_10.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_10.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_10.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_10.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_10.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_10.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_10.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_10.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_10.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_10.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_10.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_10.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_10.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_10.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_10.49, 6; + %jmp T_10.50; +T_10.34 ; + %load/vec4 v0x29baee0_0; + %load/vec4 v0x29beeb0_0; + %add; + %assign/vec4 v0x29baee0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.35 ; + %load/vec4 v0x29baee0_0; + %load/vec4 v0x29beeb0_0; + %sub; + %assign/vec4 v0x29baee0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.36 ; + %load/vec4 v0x29bb470_0; + %pad/u 11; + %load/vec4 v0x29beeb0_0; + %add; + %pad/u 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.37 ; + %load/vec4 v0x29beeb0_0; + %assign/vec4 v0x29bf920_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.38 ; + %load/vec4 v0x29bb180_0; + %assign/vec4 v0x29bf920_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.39 ; + %load/vec4 v0x29baee0_0; + %load/vec4 v0x29bb180_0; + %add; + %assign/vec4 v0x29baee0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.40 ; + %load/vec4 v0x29baee0_0; + %load/vec4 v0x29bb180_0; + %sub; + %assign/vec4 v0x29baee0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.41 ; + %load/vec4 v0x29bb470_0; + %pad/u 11; + %load/vec4 v0x29bb180_0; + %add; + %pad/u 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.42 ; + %load/vec4 v0x29bafe0_0; + %assign/vec4 v0x29baee0_0, 0; + %load/vec4 v0x29baee0_0; + %assign/vec4 v0x29bafe0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.43 ; + %load/vec4 v0x29baee0_0; + %assign/vec4 v0x29bafe0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.44 ; + %load/vec4 v0x29baee0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x29baee0_0, 0; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.45 ; + %load/vec4 v0x29bb390_0; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.50; +T_10.46 ; + %load/vec4 v0x29baee0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_10.51, 4; + %load/vec4 v0x29bb390_0; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.52; +T_10.51 ; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; +T_10.52 ; + %jmp T_10.50; +T_10.47 ; + %load/vec4 v0x29baee0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_10.53, 4; + %load/vec4 v0x29bb390_0; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.54; +T_10.53 ; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; +T_10.54 ; + %jmp T_10.50; +T_10.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x29baee0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_10.55, 5; + %load/vec4 v0x29bb390_0; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.56; +T_10.55 ; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; +T_10.56 ; + %jmp T_10.50; +T_10.49 ; + %load/vec4 v0x29baee0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_10.57, 5; + %load/vec4 v0x29bb390_0; + %assign/vec4 v0x29bb550_0, 0; + %jmp T_10.58; +T_10.57 ; + %load/vec4 v0x29bb470_0; + %addi 1, 0, 4; + %assign/vec4 v0x29bb550_0, 0; +T_10.58 ; + %jmp T_10.50; +T_10.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.7; +T_10.6 ; + %load/vec4 v0x29bb260_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x29bb260_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_10.59, 4; + %load/vec4 v0x29bb0c0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x29bb0c0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29be320_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_10.61, 9; + %load/vec4 v0x29bb0c0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_10.63, 4; + %load/vec4 v0x29bf920_0; + %assign/vec4 v0x29baee0_0, 0; +T_10.63 ; + %jmp T_10.62; +T_10.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %load/vec4 v0x29bb0c0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.65, 4; + %load/vec4 v0x29be320_0; + %assign/vec4 v0x29bf840_0, 0; + %load/vec4 v0x29bf920_0; + %load/vec4 v0x29be320_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29be320_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %jmp T_10.66; +T_10.65 ; + %load/vec4 v0x29bb0c0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.67, 4; + %load/vec4 v0x29bb0c0_0; + %assign/vec4 v0x29bf840_0, 0; + %load/vec4 v0x29bf920_0; + %load/vec4 v0x29bb0c0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29bb0c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bb0c0_0; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.68; +T_10.67 ; + %load/vec4 v0x29bddc0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.69, 8; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.72; +T_10.71 ; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.74; +T_10.73 ; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.76; +T_10.75 ; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29be320_0, 0; +T_10.77 ; +T_10.76 ; +T_10.74 ; +T_10.72 ; + %jmp T_10.70; +T_10.69 ; + %load/vec4 v0x29bb0c0_0; + %assign/vec4 v0x29bf840_0, 0; +T_10.70 ; +T_10.68 ; +T_10.66 ; +T_10.62 ; +T_10.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.7; +T_10.7 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.1 ; + %load/vec4 v0x29be7e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.81, 6; + %jmp T_10.82; +T_10.79 ; + %load/vec4 v0x29bee10_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.83, 4; + %load/vec4 v0x29bdc40_0; + %flag_set/vec4 8; + %jmp/0xz T_10.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bf5a0_0, 0, 4; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.88; +T_10.87 ; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.90; +T_10.89 ; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.92; +T_10.91 ; + %load/vec4 v0x29be8c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29be320_0, 0; +T_10.93 ; +T_10.92 ; +T_10.90 ; +T_10.88 ; +T_10.85 ; + %jmp T_10.84; +T_10.83 ; + %load/vec4 v0x29be8c0_0; + %load/vec4 v0x29bee10_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %load/vec4 v0x29bee10_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29bef50, 4; + %assign/vec4 v0x29beeb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29bee10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bed70_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29bee10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29bf5a0_0, 4, 5; + %load/vec4 v0x29bee10_0; + %assign/vec4 v0x29be320_0, 0; +T_10.95 ; +T_10.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.82; +T_10.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.82; +T_10.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.82; +T_10.82 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0x29be7e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.99, 6; + %jmp T_10.100; +T_10.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.100; +T_10.98 ; + %load/vec4 v0x29bf840_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.101, 4; + %load/vec4 v0x29bddc0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.103, 8; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.106; +T_10.105 ; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.108; +T_10.107 ; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29be320_0, 0; + %jmp T_10.110; +T_10.109 ; + %load/vec4 v0x29bccf0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29bf840_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29bf4e0_0, 4, 5; + %load/vec4 v0x29bf920_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29be6a0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29be320_0, 0; +T_10.111 ; +T_10.110 ; +T_10.108 ; +T_10.106 ; +T_10.103 ; +T_10.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.100; +T_10.99 ; + %load/vec4 v0x29bf840_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.113, 4; + %load/vec4 v0x29bf680_0; + %load/vec4 v0x29bf840_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x29bf840_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x29bf4e0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29be5c0_0, 0; + %load/vec4 v0x29bf840_0; + %assign/vec4 v0x29be320_0, 0; +T_10.115 ; +T_10.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29be7e0_0, 0; + %jmp T_10.100; +T_10.100 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.3 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10; + .scope S_0x29ba9b0; +T_11 ; + %wait E_0x2912800; + %load/vec4 v0x29be7e0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29be5c0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x29bb550_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0x29bb550_0; + %assign/vec4 v0x29bb470_0, 0; +T_11.0 ; + %load/vec4 v0x29be7e0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_11.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29bed70_0, 0, 4; +T_11.2 ; + %jmp T_11; + .thread T_11; + .scope S_0x29511f0; +T_12 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29b9330_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29b9550_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x29b9090_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29775b0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x29b5ce0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29b61a0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29b9ae0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ba3b0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ba570_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ba2d0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29b9410, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29b9410, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29b9410, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29b9410, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x28ff610, v0x29b8fd0 {0 0 0}; + %end; + .thread T_12; + .scope S_0x29511f0; +T_13 ; + %wait E_0x2934f90; + %load/vec4 v0x29b9330_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.2, 6; + %jmp T_13.3; +T_13.0 ; + %load/vec4 v0x29b9550_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.6, 6; + %jmp T_13.7; +T_13.4 ; + %load/vec4 v0x29b5f90_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_13.8, 5; + %load/vec4 v0x29b6360_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_13.10, 5; + %load/vec4 v0x29b6360_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %jmp T_13.11; +T_13.10 ; + %load/vec4 v0x29b6360_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_13.12, 5; + %load/vec4 v0x29b9630_0; + %load/vec4 v0x29b6360_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.14, 8; + %load/vec4 v0x29b6360_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b6360_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %load/vec4 v0x29b6360_0; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.15; +T_13.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %load/vec4 v0x29b6360_0; + %assign/vec4 v0x29b9b80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b6360_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; + %load/vec4 v0x29b6360_0; + %assign/vec4 v0x29b9090_0, 0; +T_13.15 ; + %jmp T_13.13; +T_13.12 ; + %load/vec4 v0x29b6360_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.16, 4; + %load/vec4 v0x29b9090_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_13.18, 4; + %load/vec4 v0x29b9090_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %jmp T_13.19; +T_13.18 ; + %load/vec4 v0x29b9630_0; + %load/vec4 v0x29b9090_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.20, 8; + %load/vec4 v0x29b9090_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b9090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %jmp T_13.21; +T_13.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %load/vec4 v0x29b9090_0; + %assign/vec4 v0x29b9b80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b9090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; +T_13.21 ; +T_13.19 ; + %jmp T_13.17; +T_13.16 ; + %load/vec4 v0x29b6360_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.22, 4; + %load/vec4 v0x29b8970_0; + %flag_set/vec4 8; + %jmp/0xz T_13.24, 8; + %load/vec4 v0x29b9630_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.27; +T_13.26 ; + %load/vec4 v0x29b9630_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.29; +T_13.28 ; + %load/vec4 v0x29b9630_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.31; +T_13.30 ; + %load/vec4 v0x29b9630_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29b9090_0, 0; +T_13.32 ; +T_13.31 ; +T_13.29 ; +T_13.27 ; + %jmp T_13.25; +T_13.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %load/vec4 v0x29b6360_0; + %assign/vec4 v0x29b9b80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; +T_13.25 ; +T_13.22 ; +T_13.17 ; +T_13.13 ; +T_13.11 ; +T_13.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.7; +T_13.5 ; + %load/vec4 v0x29b5f90_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_13.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_13.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_13.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_13.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_13.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_13.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_13.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_13.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_13.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_13.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_13.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_13.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_13.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_13.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_13.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_13.49, 6; + %jmp T_13.50; +T_13.34 ; + %load/vec4 v0x29775b0_0; + %load/vec4 v0x29b9c60_0; + %add; + %assign/vec4 v0x29775b0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.35 ; + %load/vec4 v0x29775b0_0; + %load/vec4 v0x29b9c60_0; + %sub; + %assign/vec4 v0x29775b0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.36 ; + %load/vec4 v0x29b61a0_0; + %pad/u 11; + %load/vec4 v0x29b9c60_0; + %add; + %pad/u 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.37 ; + %load/vec4 v0x29b9c60_0; + %assign/vec4 v0x29ba730_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.38 ; + %load/vec4 v0x29b5eb0_0; + %assign/vec4 v0x29ba730_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.39 ; + %load/vec4 v0x29775b0_0; + %load/vec4 v0x29b5eb0_0; + %add; + %assign/vec4 v0x29775b0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.40 ; + %load/vec4 v0x29775b0_0; + %load/vec4 v0x29b5eb0_0; + %sub; + %assign/vec4 v0x29775b0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.41 ; + %load/vec4 v0x29b61a0_0; + %pad/u 11; + %load/vec4 v0x29b5eb0_0; + %add; + %pad/u 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.42 ; + %load/vec4 v0x29b5ce0_0; + %assign/vec4 v0x29775b0_0, 0; + %load/vec4 v0x29775b0_0; + %assign/vec4 v0x29b5ce0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.43 ; + %load/vec4 v0x29775b0_0; + %assign/vec4 v0x29b5ce0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.44 ; + %load/vec4 v0x29775b0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x29775b0_0, 0; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.45 ; + %load/vec4 v0x29b60c0_0; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.50; +T_13.46 ; + %load/vec4 v0x29775b0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_13.51, 4; + %load/vec4 v0x29b60c0_0; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.52; +T_13.51 ; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; +T_13.52 ; + %jmp T_13.50; +T_13.47 ; + %load/vec4 v0x29775b0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_13.53, 4; + %load/vec4 v0x29b60c0_0; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.54; +T_13.53 ; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; +T_13.54 ; + %jmp T_13.50; +T_13.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x29775b0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_13.55, 5; + %load/vec4 v0x29b60c0_0; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.56; +T_13.55 ; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; +T_13.56 ; + %jmp T_13.50; +T_13.49 ; + %load/vec4 v0x29775b0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_13.57, 5; + %load/vec4 v0x29b60c0_0; + %assign/vec4 v0x29b6280_0, 0; + %jmp T_13.58; +T_13.57 ; + %load/vec4 v0x29b61a0_0; + %addi 1, 0, 4; + %assign/vec4 v0x29b6280_0, 0; +T_13.58 ; + %jmp T_13.50; +T_13.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.7; +T_13.6 ; + %load/vec4 v0x29b5f90_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x29b5f90_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_13.59, 4; + %load/vec4 v0x29b5dc0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x29b5dc0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29b9090_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_13.61, 9; + %load/vec4 v0x29b5dc0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_13.63, 4; + %load/vec4 v0x29ba730_0; + %assign/vec4 v0x29775b0_0, 0; +T_13.63 ; + %jmp T_13.62; +T_13.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %load/vec4 v0x29b5dc0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.65, 4; + %load/vec4 v0x29b9090_0; + %assign/vec4 v0x29ba650_0, 0; + %load/vec4 v0x29ba730_0; + %load/vec4 v0x29b9090_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b9090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %jmp T_13.66; +T_13.65 ; + %load/vec4 v0x29b5dc0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.67, 4; + %load/vec4 v0x29b5dc0_0; + %assign/vec4 v0x29ba650_0, 0; + %load/vec4 v0x29ba730_0; + %load/vec4 v0x29b5dc0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b5dc0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29b5dc0_0; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.68; +T_13.67 ; + %load/vec4 v0x29b8af0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.69, 8; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.72; +T_13.71 ; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.74; +T_13.73 ; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.76; +T_13.75 ; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29b9090_0, 0; +T_13.77 ; +T_13.76 ; +T_13.74 ; +T_13.72 ; + %jmp T_13.70; +T_13.69 ; + %load/vec4 v0x29b5dc0_0; + %assign/vec4 v0x29ba650_0, 0; +T_13.70 ; +T_13.68 ; +T_13.66 ; +T_13.62 ; +T_13.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.7; +T_13.7 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.1 ; + %load/vec4 v0x29b9550_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.81, 6; + %jmp T_13.82; +T_13.79 ; + %load/vec4 v0x29b9b80_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.83, 4; + %load/vec4 v0x29b8970_0; + %flag_set/vec4 8; + %jmp/0xz T_13.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29ba3b0_0, 0, 4; + %load/vec4 v0x29b9630_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.88; +T_13.87 ; + %load/vec4 v0x29b9630_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.90; +T_13.89 ; + %load/vec4 v0x29b9630_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.92; +T_13.91 ; + %load/vec4 v0x29b9630_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29b9090_0, 0; +T_13.93 ; +T_13.92 ; +T_13.90 ; +T_13.88 ; +T_13.85 ; + %jmp T_13.84; +T_13.83 ; + %load/vec4 v0x29b9630_0; + %load/vec4 v0x29b9b80_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %load/vec4 v0x29b9b80_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x29b9d40, 4; + %assign/vec4 v0x29b9c60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b9b80_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29b9ae0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x29b9b80_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x29ba3b0_0, 4, 5; + %load/vec4 v0x29b9b80_0; + %assign/vec4 v0x29b9090_0, 0; +T_13.95 ; +T_13.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.82; +T_13.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.82; +T_13.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.82; +T_13.82 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x29b9550_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.99, 6; + %jmp T_13.100; +T_13.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.100; +T_13.98 ; + %load/vec4 v0x29ba650_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.101, 4; + %load/vec4 v0x29b8af0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.103, 8; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.106; +T_13.105 ; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.108; +T_13.107 ; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x29b9090_0, 0; + %jmp T_13.110; +T_13.109 ; + %load/vec4 v0x29b7a20_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29ba650_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x29ba2d0_0, 4, 5; + %load/vec4 v0x29ba730_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x29b9410, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x29b9090_0, 0; +T_13.111 ; +T_13.110 ; +T_13.108 ; +T_13.106 ; +T_13.103 ; +T_13.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.100; +T_13.99 ; + %load/vec4 v0x29ba650_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.113, 4; + %load/vec4 v0x29ba490_0; + %load/vec4 v0x29ba650_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x29ba650_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x29ba2d0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29b9330_0, 0; + %load/vec4 v0x29ba650_0; + %assign/vec4 v0x29b9090_0, 0; +T_13.115 ; +T_13.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x29b9550_0, 0; + %jmp T_13.100; +T_13.100 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.3 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13; + .scope S_0x29511f0; +T_14 ; + %wait E_0x2912800; + %load/vec4 v0x29b9550_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x29b9330_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x29b6280_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %load/vec4 v0x29b6280_0; + %assign/vec4 v0x29b61a0_0, 0; +T_14.0 ; + %load/vec4 v0x29b9550_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_14.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x29b9ae0_0, 0, 4; +T_14.2 ; + %jmp T_14; + .thread T_14; + .scope S_0x2901970; +T_15 ; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x29cfe10_0, 0, 33; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x29cfcb0_0, 0, 1; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 1, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 2, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 3, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 4, 0, 11; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 4, 0, 11; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 5, 0, 11; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x29cfd50, 4, 0; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x29cfe10_0, 0, 33; +T_15.0 ; + %load/vec4 v0x29cfe10_0; + %cmpi/u 7, 0, 33; + %jmp/0xz T_15.1, 5; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x29cfc10_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x29cfc10_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x29cfc10_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x29cfc10_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x29cfc10_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x29cfc10_0, 0, 1; + %delay 1, 0; + %load/vec4 v0x29cfac0_0; + %ix/getv 4, v0x29cfe10_0; + %load/vec4a v0x29cfd50, 4; + %cmp/ne; + %jmp/0xz T_15.2, 4; + %vpi_call 2 54 "$display", "anyRead failed on test %d", v0x29cfe10_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x29cfcb0_0, 0, 1; +T_15.2 ; + %load/vec4 v0x29cfe10_0; + %addi 1, 0, 33; + %store/vec4 v0x29cfe10_0, 0, 33; + %jmp T_15.0; +T_15.1 ; + %load/vec4 v0x29cfcb0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.4, 8; + %vpi_call 2 59 "$display", "DUT passed anyRead" {0 0 0}; +T_15.4 ; + %end; + .thread T_15; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "anyRead/test.v"; + "./tis100.v"; diff --git a/anyRead/test.asm b/anyRead/test.asm new file mode 100644 index 0000000..bece3a3 --- /dev/null +++ b/anyRead/test.asm @@ -0,0 +1,24 @@ +:center +MOV ANY ACC +MOV ANY ACC +MOV ANY ACC +MOV ANY ACC +MOV LAST ACC +JRO 0 + +:up +MOV 3 DOWN +JRO 0 + +:left +MOV 1 RIGHT +JRO 0 + +:right +MOV 2 LEFT +JRO 0 + +:down +MOV 4 UP +MOV 5 UP +JRO 0 diff --git a/anyRead/test.v b/anyRead/test.v new file mode 100644 index 0000000..eee8046 --- /dev/null +++ b/anyRead/test.v @@ -0,0 +1,63 @@ +`include "tis100.v" +module tis100Test(); + +reg clk; +wire signed[10:0] accOutCenter; +reg[32:0] i; + +wire[14:0] L2C; +wire[14:0] C2L; + +wire[14:0] R2C; +wire[14:0] C2R; + +wire[14:0] U2C; +wire[14:0] C2U; + +wire[14:0] D2C; +wire[14:0] C2D; + +reg dutPassed; + +tis100 #("anyRead/left.dat") left( .clk(clk), .rightOut(L2C), .right(C2L)); +tis100 #("anyRead/right.dat") right( .clk(clk), .leftOut(R2C), .left(C2R)); +tis100 #("anyRead/up.dat") up( .clk(clk), .downOut(U2C), .down(C2U)); +tis100 #("anyRead/down.dat") down( .clk(clk), .upOut(D2C), .up(C2D)); +tis100 #("anyRead/center.dat") center(.clk(clk), + .upOut(C2U), .up(U2C), + .downOut(C2D), .down(D2C), + .leftOut(C2L), .left(L2C), + .rightOut(C2R), .right(R2C), + .accOut(accOutCenter) + ); + +reg signed[10:0] expected[0:6]; + +initial begin + i = 0; + dutPassed = 1; + expected[0] = 0; + expected[1] = 1; + expected[2] = 2; + expected[3] = 3; + expected[4] = 4; + expected[5] = 4; + expected[6] = 5; + for( i = 0; i<7; i=i+1) begin + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + if(accOutCenter != expected[i]) begin + $display("anyRead failed on test %d",i); + dutPassed = 0; + end + end + if(dutPassed) begin + $display("DUT passed anyRead"); + end +end + +endmodule diff --git a/anyRead/up.dat b/anyRead/up.dat new file mode 100644 index 0000000..ac98802 --- /dev/null +++ b/anyRead/up.dat @@ -0,0 +1,16 @@ +010010100000000011 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/anyWrite/center.dat b/anyWrite/center.dat new file mode 100644 index 0000000..afb975f --- /dev/null +++ b/anyWrite/center.dat @@ -0,0 +1,16 @@ +010011100000000001 +010011100000000010 +010011100000000011 +010011100000000100 +001100111000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/anyWrite/down.dat b/anyWrite/down.dat new file mode 100644 index 0000000..1a856b9 --- /dev/null +++ b/anyWrite/down.dat @@ -0,0 +1,16 @@ +001100110000000000 +010010000000000101 +011100000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/anyWrite/left.dat b/anyWrite/left.dat new file mode 100644 index 0000000..515671a --- /dev/null +++ b/anyWrite/left.dat @@ -0,0 +1,16 @@ +001100101100000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/anyWrite/right.dat b/anyWrite/right.dat new file mode 100644 index 0000000..05f61fe --- /dev/null +++ b/anyWrite/right.dat @@ -0,0 +1,16 @@ +001100101000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/anyWrite/test b/anyWrite/test new file mode 100755 index 0000000..f33073c --- /dev/null +++ b/anyWrite/test @@ -0,0 +1,6103 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x10151e0 .scope module, "tis100Test" "tis100Test" 2 2; + .timescale 0 0; +v0x10bbe40_0 .net "C2D", 14 0, L_0x10e06c0; 1 drivers +v0x10bbf70_0 .net "C2L", 14 0, L_0x10e03e0; 1 drivers +v0x10bc080_0 .net "C2R", 14 0, L_0x10e0db0; 1 drivers +v0x10bc170_0 .net "C2U", 14 0, L_0x10e0110; 1 drivers +v0x10bc280_0 .net "D2C", 14 0, L_0x10dbf20; 1 drivers +v0x10bc3e0_0 .net "L2C", 14 0, L_0x10d06c0; 1 drivers +v0x10bc4f0_0 .net "R2C", 14 0, L_0x10d4010; 1 drivers +v0x10bc600_0 .net "U2C", 14 0, L_0x10d8380; 1 drivers +v0x10bc710_0 .net/s "accOutCenter", 10 0, L_0x10dcce0; 1 drivers +v0x10bc860_0 .net/s "accOutDown", 10 0, L_0x10d8c80; 1 drivers +v0x10bc900_0 .net/s "accOutLeft", 10 0, L_0x10bcd00; 1 drivers +v0x10bc9a0_0 .net/s "accOutRight", 10 0, L_0x10d0a10; 1 drivers +v0x10bca40_0 .net/s "accOutUp", 10 0, L_0x10d4bd0; 1 drivers +v0x10bcae0_0 .var "clk", 0 0; +v0x10bcb80_0 .var "dutPassed", 0 0; +v0x10bcc20_0 .var "i", 32 0; +S_0xfed540 .scope module, "center" "tis100" 2 31, 3 49 0, S_0x10151e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x103d600 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x103d640 .param/str "memFile" 0 3 60, "anyWrite/center.dat"; +L_0x10dcce0 .functor BUFZ 11, v0x1063240_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10dcf70 .functor BUFZ 11, v0x1063240_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10ddda0 .functor BUFZ 18, L_0x10dff20, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x1063240_0 .var/s "ACC", 10 0; +v0x10a2930_0 .var/s "BAK", 10 0; +v0x10a2a10_0 .net "DST", 2 0, L_0x10e1240; 1 drivers +v0x10a2b00_0 .net/s "IMM", 10 0, L_0x10e12e0; 1 drivers +v0x10a2be0_0 .net "INST", 3 0, L_0x10e0a20; 1 drivers +v0x10a2d10_0 .net "LABEL", 3 0, L_0x10e1490; 1 drivers +v0x10a2df0_0 .var "PC", 3 0; +v0x10a2ed0_0 .var "PCNEXT", 3 0; +v0x10a2fb0_0 .net "SRC", 2 0, L_0x10e1050; 1 drivers +v0x10a3120_0 .net *"_s103", 0 0, L_0x10df260; 1 drivers +v0x10a3200_0 .net *"_s107", 0 0, L_0x10df170; 1 drivers +v0x10a32e0_0 .net *"_s111", 0 0, L_0x10df450; 1 drivers +v0x10a33c0_0 .net *"_s115", 0 0, L_0x10df350; 1 drivers +v0x10a34a0_0 .net *"_s119", 0 0, L_0x10df690; 1 drivers +v0x10a3580_0 .net *"_s123", 0 0, L_0x10df580; 1 drivers +v0x10a3660_0 .net *"_s127", 0 0, L_0x10df850; 1 drivers +v0x10a3740_0 .net *"_s131", 0 0, L_0x10df730; 1 drivers +v0x10a38f0_0 .net *"_s135", 0 0, L_0x10dfab0; 1 drivers +v0x10a3990_0 .net *"_s139", 0 0, L_0x10df980; 1 drivers +v0x10a3a70_0 .net *"_s143", 0 0, L_0x10dfc90; 1 drivers +v0x10a3b50_0 .net *"_s147", 0 0, L_0x10dfb50; 1 drivers +v0x10a3c30_0 .net *"_s151", 0 0, L_0x10dfe80; 1 drivers +v0x10a3d10_0 .net *"_s155", 0 0, L_0x10dfd30; 1 drivers +v0x10a3df0_0 .net *"_s159", 0 0, L_0x10dfdd0; 1 drivers +v0x10a3ed0_0 .net *"_s160", 17 0, L_0x10dff20; 1 drivers +v0x10a3fb0_0 .net *"_s162", 5 0, L_0x10e0280; 1 drivers +L_0x2b8038e7d2a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x10a4090_0 .net *"_s165", 1 0, L_0x2b8038e7d2a0; 1 drivers +v0x10a6060_2 .array/port v0x10a6060, 2; +v0x10a4170_0 .net *"_s173", 10 0, v0x10a6060_2; 1 drivers +v0x10a6060_3 .array/port v0x10a6060, 3; +v0x10a4250_0 .net *"_s179", 10 0, v0x10a6060_3; 1 drivers +v0x10a6060_0 .array/port v0x10a6060, 0; +v0x10a4330_0 .net *"_s185", 10 0, v0x10a6060_0; 1 drivers +v0x10a6060_1 .array/port v0x10a6060, 1; +v0x10a4410_0 .net *"_s191", 10 0, v0x10a6060_1; 1 drivers +v0x10a44f0_0 .net *"_s23", 0 0, L_0x10dd740; 1 drivers +v0x10a45d0_0 .net *"_s27", 0 0, L_0x10dd810; 1 drivers +v0x10a3820_0 .net *"_s31", 0 0, L_0x10dd8e0; 1 drivers +v0x10a48a0_0 .net *"_s36", 0 0, L_0x10dda80; 1 drivers +v0x10a4980_0 .net *"_s42", 0 0, L_0x10ddc60; 1 drivers +v0x10a4a60_0 .net *"_s46", 0 0, L_0x10ddd00; 1 drivers +v0x10a4b40_0 .net *"_s50", 0 0, L_0x10dde10; 1 drivers +v0x10a4c20_0 .net *"_s55", 0 0, L_0x10de020; 1 drivers +v0x10a4d00_0 .net *"_s61", 0 0, L_0x10de290; 1 drivers +v0x10a4de0_0 .net *"_s65", 0 0, L_0x10de330; 1 drivers +v0x10a4ec0_0 .net *"_s69", 0 0, L_0x10de470; 1 drivers +v0x10a4fa0_0 .net *"_s74", 0 0, L_0x10de3d0; 1 drivers +v0x10a5080_0 .net *"_s80", 0 0, L_0x10de6a0; 1 drivers +v0x10a5160_0 .net *"_s84", 0 0, L_0x10dea60; 1 drivers +v0x10a5240_0 .net *"_s88", 0 0, L_0x10de890; 1 drivers +v0x10a5320_0 .net *"_s93", 0 0, L_0x10dec10; 1 drivers +v0x10a5400_0 .net *"_s99", 0 0, L_0x10dee90; 1 drivers +v0x10a54e0_0 .net/s "accOut", 10 0, L_0x10dcce0; alias, 1 drivers +v0x10a55c0_0 .net "anyHasData", 0 0, L_0x10ddb70; 1 drivers +v0x10a5680_0 .net "anyReadAck", 0 0, L_0x10de7a0; 1 drivers +v0x10a5740_0 .net "anyWantData", 0 0, L_0x10de110; 1 drivers +v0x10a5800_0 .net "anyWriteAck", 0 0, L_0x10df0d0; 1 drivers +v0x10a58c0_0 .net "clk", 0 0, v0x10bcae0_0; 1 drivers +v0x10a5980_0 .net "down", 14 0, L_0x10dbf20; alias, 1 drivers +v0x10a5a60_0 .net "downOut", 14 0, L_0x10e06c0; alias, 1 drivers +v0x10a5b40_0 .net "instruction", 17 0, L_0x10ddda0; 1 drivers +v0x10a5c20 .array "instructions", 15 0, 17 0; +v0x10a5ce0_0 .var "last", 2 0; +v0x10a5dc0_0 .net "left", 14 0, L_0x10d06c0; alias, 1 drivers +v0x10a5ea0_0 .net "leftOut", 14 0, L_0x10e03e0; alias, 1 drivers +v0x10a5f80_0 .var "mode", 2 0; +v0x10a6060 .array/s "outVals", 2 5, 10 0; +v0x10a61a0_0 .var "phase", 2 0; +v0x10a6280_0 .net "portsHaveData", 5 2, L_0x10dd980; 1 drivers +v0x10a4670_0 .net "portsWantData", 5 2, L_0x10ddeb0; 1 drivers +v0x10a4750_0 .net "readAckIn", 5 2, L_0x10de510; 1 drivers +v0x10a6730_0 .var "readAckOut", 5 2; +v0x10a67d0_0 .var "readTarget", 2 0; +v0x10a68b0_0 .var/s "readValue", 10 0; +L_0x2b8038e7d258 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x10a6990 .array "regVals", 0 7; +v0x10a6990_0 .net/s v0x10a6990 0, 10 0, L_0x2b8038e7d258; 1 drivers +v0x10a6990_1 .net/s v0x10a6990 1, 10 0, L_0x10dcf70; 1 drivers +v0x10a6990_2 .net/s v0x10a6990 2, 10 0, L_0x10dd250; 1 drivers +v0x10a6990_3 .net/s v0x10a6990 3, 10 0, L_0x10dd380; 1 drivers +v0x10a6990_4 .net/s v0x10a6990 4, 10 0, L_0x10dd4b0; 1 drivers +v0x10a6990_5 .net/s v0x10a6990 5, 10 0, L_0x10dd5e0; 1 drivers +o0x2b8038e4ceb8 .functor BUFZ 11, C4; HiZ drive +v0x10a6990_6 .net/s v0x10a6990 6, 10 0, o0x2b8038e4ceb8; 0 drivers +o0x2b8038e4cee8 .functor BUFZ 11, C4; HiZ drive +v0x10a6990_7 .net/s v0x10a6990 7, 10 0, o0x2b8038e4cee8; 0 drivers +v0x10a6ba0_0 .net "right", 14 0, L_0x10d4010; alias, 1 drivers +v0x10a6c80_0 .net "rightOut", 14 0, L_0x10e0db0; alias, 1 drivers +v0x10a6d60_0 .net "up", 14 0, L_0x10d8380; alias, 1 drivers +v0x10a6e40_0 .net "upOut", 14 0, L_0x10e0110; alias, 1 drivers +v0x10a6f20_0 .var "weHaveData", 5 2; +v0x10a7000_0 .var "weWantData", 5 2; +v0x10a70e0_0 .net "writeAckIn", 5 2, L_0x10dedf0; 1 drivers +v0x10a71c0_0 .var "writeAckOut", 5 2; +v0x10a72a0_0 .var "writeTarget", 2 0; +v0x10a7380_0 .var/s "writeValue", 10 0; +E_0xffe3d0 .event negedge, v0x10a58c0_0; +E_0x1020b80 .event posedge, v0x10a58c0_0; +L_0x10dd250 .part L_0x10d06c0, 0, 11; +L_0x10dd380 .part L_0x10d4010, 0, 11; +L_0x10dd4b0 .part L_0x10d8380, 0, 11; +L_0x10dd5e0 .part L_0x10dbf20, 0, 11; +L_0x10dd740 .part L_0x10d06c0, 11, 1; +L_0x10dd810 .part L_0x10d4010, 11, 1; +L_0x10dd8e0 .part L_0x10d8380, 11, 1; +L_0x10dd980 .concat8 [ 1 1 1 1], L_0x10dd740, L_0x10dd810, L_0x10dd8e0, L_0x10dda80; +L_0x10dda80 .part L_0x10dbf20, 11, 1; +L_0x10ddb70 .reduce/or L_0x10dd980; +L_0x10ddc60 .part L_0x10d06c0, 12, 1; +L_0x10ddd00 .part L_0x10d4010, 12, 1; +L_0x10dde10 .part L_0x10d8380, 12, 1; +L_0x10ddeb0 .concat8 [ 1 1 1 1], L_0x10ddc60, L_0x10ddd00, L_0x10dde10, L_0x10de020; +L_0x10de020 .part L_0x10dbf20, 12, 1; +L_0x10de110 .reduce/or L_0x10ddeb0; +L_0x10de290 .part L_0x10d06c0, 13, 1; +L_0x10de330 .part L_0x10d4010, 13, 1; +L_0x10de470 .part L_0x10d8380, 13, 1; +L_0x10de510 .concat8 [ 1 1 1 1], L_0x10de290, L_0x10de330, L_0x10de470, L_0x10de3d0; +L_0x10de3d0 .part L_0x10dbf20, 13, 1; +L_0x10de7a0 .reduce/or L_0x10de510; +L_0x10de6a0 .part L_0x10d06c0, 14, 1; +L_0x10dea60 .part L_0x10d4010, 14, 1; +L_0x10de890 .part L_0x10d8380, 14, 1; +L_0x10dedf0 .concat8 [ 1 1 1 1], L_0x10de6a0, L_0x10dea60, L_0x10de890, L_0x10dec10; +L_0x10dec10 .part L_0x10dbf20, 14, 1; +L_0x10df0d0 .reduce/or L_0x10dedf0; +L_0x10dee90 .part v0x10a6730_0, 0, 1; +L_0x10df260 .part v0x10a6730_0, 1, 1; +L_0x10df170 .part v0x10a6730_0, 2, 1; +L_0x10df450 .part v0x10a6730_0, 3, 1; +L_0x10df350 .part v0x10a71c0_0, 0, 1; +L_0x10df690 .part v0x10a71c0_0, 1, 1; +L_0x10df580 .part v0x10a71c0_0, 2, 1; +L_0x10df850 .part v0x10a71c0_0, 3, 1; +L_0x10df730 .part v0x10a7000_0, 0, 1; +L_0x10dfab0 .part v0x10a7000_0, 1, 1; +L_0x10df980 .part v0x10a7000_0, 2, 1; +L_0x10dfc90 .part v0x10a7000_0, 3, 1; +L_0x10dfb50 .part v0x10a6f20_0, 0, 1; +L_0x10dfe80 .part v0x10a6f20_0, 1, 1; +L_0x10dfd30 .part v0x10a6f20_0, 2, 1; +L_0x10dfdd0 .part v0x10a6f20_0, 3, 1; +L_0x10dff20 .array/port v0x10a5c20, L_0x10e0280; +L_0x10e0280 .concat [ 4 2 0 0], v0x10a2df0_0, L_0x2b8038e7d2a0; +LS_0x10e0110_0_0 .concat8 [ 11 1 1 1], v0x10a6060_2, L_0x10dfd30, L_0x10df980, L_0x10df580; +LS_0x10e0110_0_4 .concat8 [ 1 0 0 0], L_0x10df170; +L_0x10e0110 .concat8 [ 14 1 0 0], LS_0x10e0110_0_0, LS_0x10e0110_0_4; +LS_0x10e06c0_0_0 .concat8 [ 11 1 1 1], v0x10a6060_3, L_0x10dfdd0, L_0x10dfc90, L_0x10df850; +LS_0x10e06c0_0_4 .concat8 [ 1 0 0 0], L_0x10df450; +L_0x10e06c0 .concat8 [ 14 1 0 0], LS_0x10e06c0_0_0, LS_0x10e06c0_0_4; +LS_0x10e03e0_0_0 .concat8 [ 11 1 1 1], v0x10a6060_0, L_0x10dfb50, L_0x10df730, L_0x10df350; +LS_0x10e03e0_0_4 .concat8 [ 1 0 0 0], L_0x10dee90; +L_0x10e03e0 .concat8 [ 14 1 0 0], LS_0x10e03e0_0_0, LS_0x10e03e0_0_4; +LS_0x10e0db0_0_0 .concat8 [ 11 1 1 1], v0x10a6060_1, L_0x10dfe80, L_0x10dfab0, L_0x10df690; +LS_0x10e0db0_0_4 .concat8 [ 1 0 0 0], L_0x10df260; +L_0x10e0db0 .concat8 [ 14 1 0 0], LS_0x10e0db0_0_0, LS_0x10e0db0_0_4; +L_0x10e0a20 .part L_0x10ddda0, 14, 4; +L_0x10e1240 .part L_0x10ddda0, 11, 3; +L_0x10e1050 .part L_0x10ddda0, 8, 3; +L_0x10e1490 .part L_0x10ddda0, 10, 4; +L_0x10e12e0 .part L_0x10ddda0, 0, 11; +S_0x10a7600 .scope module, "down" "tis100" 2 30, 3 49 0, S_0x10151e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x10a77f0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x10a7830 .param/str "memFile" 0 3 60, "anyWrite/down.dat"; +L_0x10d8c80 .functor BUFZ 11, v0x10a7b80_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10d8e80 .functor BUFZ 11, v0x10a7b80_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10d9d40 .functor BUFZ 18, L_0x10dbcb0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x10a7b80_0 .var/s "ACC", 10 0; +v0x10a7c80_0 .var/s "BAK", 10 0; +v0x10a7d60_0 .net "DST", 2 0, L_0x10dcda0; 1 drivers +v0x10a7e20_0 .net/s "IMM", 10 0, L_0x10dce40; 1 drivers +v0x10a7f00_0 .net "INST", 3 0, L_0x10dc680; 1 drivers +v0x10a7fe0_0 .net "LABEL", 3 0, L_0x10dcff0; 1 drivers +v0x10a80c0_0 .var "PC", 3 0; +v0x10a81a0_0 .var "PCNEXT", 3 0; +v0x10a8280_0 .net "SRC", 2 0, L_0x10dcbb0; 1 drivers +v0x10a83f0_0 .net *"_s103", 0 0, L_0x10daff0; 1 drivers +v0x10a84d0_0 .net *"_s107", 0 0, L_0x10daf00; 1 drivers +v0x10a85b0_0 .net *"_s111", 0 0, L_0x10db1e0; 1 drivers +v0x10a8690_0 .net *"_s115", 0 0, L_0x10db0e0; 1 drivers +v0x10a8770_0 .net *"_s119", 0 0, L_0x10db420; 1 drivers +v0x10a8850_0 .net *"_s123", 0 0, L_0x10db310; 1 drivers +v0x10a8930_0 .net *"_s127", 0 0, L_0x10db5e0; 1 drivers +v0x10a8a10_0 .net *"_s131", 0 0, L_0x10db4c0; 1 drivers +v0x10a8bc0_0 .net *"_s135", 0 0, L_0x10db840; 1 drivers +v0x10a8c60_0 .net *"_s139", 0 0, L_0x10db710; 1 drivers +v0x10a8d40_0 .net *"_s143", 0 0, L_0x10dba20; 1 drivers +v0x10a8e20_0 .net *"_s147", 0 0, L_0x10db8e0; 1 drivers +v0x10a8f00_0 .net *"_s151", 0 0, L_0x10dbc10; 1 drivers +v0x10a8fe0_0 .net *"_s155", 0 0, L_0x10dbac0; 1 drivers +v0x10a90c0_0 .net *"_s159", 0 0, L_0x10dbb60; 1 drivers +v0x10a91a0_0 .net *"_s160", 17 0, L_0x10dbcb0; 1 drivers +v0x10a9280_0 .net *"_s162", 5 0, L_0x10dc010; 1 drivers +L_0x2b8038e7d210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x10a9360_0 .net *"_s165", 1 0, L_0x2b8038e7d210; 1 drivers +v0x10ab2f0_2 .array/port v0x10ab2f0, 2; +v0x10a9440_0 .net *"_s173", 10 0, v0x10ab2f0_2; 1 drivers +v0x10ab2f0_3 .array/port v0x10ab2f0, 3; +v0x10a9520_0 .net *"_s179", 10 0, v0x10ab2f0_3; 1 drivers +v0x10ab2f0_0 .array/port v0x10ab2f0, 0; +v0x10a9600_0 .net *"_s185", 10 0, v0x10ab2f0_0; 1 drivers +v0x10ab2f0_1 .array/port v0x10ab2f0, 1; +v0x10a96e0_0 .net *"_s191", 10 0, v0x10ab2f0_1; 1 drivers +v0x10a97c0_0 .net *"_s23", 0 0, L_0x10d94d0; 1 drivers +v0x10a98a0_0 .net *"_s27", 0 0, L_0x10d95f0; 1 drivers +v0x10a8af0_0 .net *"_s31", 0 0, L_0x10d96e0; 1 drivers +v0x10a9b70_0 .net *"_s36", 0 0, L_0x10d99d0; 1 drivers +v0x10a9c50_0 .net *"_s42", 0 0, L_0x10d9c00; 1 drivers +v0x10a9d30_0 .net *"_s46", 0 0, L_0x10d9ca0; 1 drivers +v0x10a9e10_0 .net *"_s50", 0 0, L_0x10d9db0; 1 drivers +v0x10a9ef0_0 .net *"_s55", 0 0, L_0x10d9fc0; 1 drivers +v0x10a9fd0_0 .net *"_s61", 0 0, L_0x10da230; 1 drivers +v0x10aa0b0_0 .net *"_s65", 0 0, L_0x10da360; 1 drivers +v0x10aa190_0 .net *"_s69", 0 0, L_0x10da530; 1 drivers +v0x10aa270_0 .net *"_s74", 0 0, L_0x10da490; 1 drivers +v0x10aa350_0 .net *"_s80", 0 0, L_0x10da6c0; 1 drivers +v0x10aa430_0 .net *"_s84", 0 0, L_0x10da9b0; 1 drivers +v0x10aa510_0 .net *"_s88", 0 0, L_0x10da8f0; 1 drivers +v0x10aa5f0_0 .net *"_s93", 0 0, L_0x10daa50; 1 drivers +v0x10aa6d0_0 .net *"_s99", 0 0, L_0x10dace0; 1 drivers +v0x10aa7b0_0 .net/s "accOut", 10 0, L_0x10d8c80; alias, 1 drivers +v0x10aa890_0 .net "anyHasData", 0 0, L_0x10d9b10; 1 drivers +v0x10aa950_0 .net "anyReadAck", 0 0, L_0x10da850; 1 drivers +v0x10aaa10_0 .net "anyWantData", 0 0, L_0x10da0b0; 1 drivers +v0x10aaad0_0 .net "anyWriteAck", 0 0, L_0x10dae10; 1 drivers +v0x10aab90_0 .net "clk", 0 0, v0x10bcae0_0; alias, 1 drivers +o0x2b8038e4dcc8 .functor BUFZ 15, C4; HiZ drive +v0x10aac30_0 .net "down", 14 0, o0x2b8038e4dcc8; 0 drivers +v0x10aacf0_0 .net "downOut", 14 0, L_0x10dc3e0; 1 drivers +v0x10aadd0_0 .net "instruction", 17 0, L_0x10d9d40; 1 drivers +v0x10aaeb0 .array "instructions", 15 0, 17 0; +v0x10aaf70_0 .var "last", 2 0; +o0x2b8038e4dd88 .functor BUFZ 15, C4; HiZ drive +v0x10ab050_0 .net "left", 14 0, o0x2b8038e4dd88; 0 drivers +v0x10ab130_0 .net "leftOut", 14 0, L_0x10dc170; 1 drivers +v0x10ab210_0 .var "mode", 2 0; +v0x10ab2f0 .array/s "outVals", 2 5, 10 0; +v0x10ab430_0 .var "phase", 2 0; +v0x10ab510_0 .net "portsHaveData", 5 2, L_0x10d9810; 1 drivers +v0x10a9940_0 .net "portsWantData", 5 2, L_0x10d9e50; 1 drivers +v0x10a9a20_0 .net "readAckIn", 5 2, L_0x10da5d0; 1 drivers +v0x10ab9c0_0 .var "readAckOut", 5 2; +v0x10aba60_0 .var "readTarget", 2 0; +v0x10abb00_0 .var/s "readValue", 10 0; +L_0x2b8038e7d1c8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x10abba0 .array "regVals", 0 7; +v0x10abba0_0 .net/s v0x10abba0 0, 10 0, L_0x2b8038e7d1c8; 1 drivers +v0x10abba0_1 .net/s v0x10abba0 1, 10 0, L_0x10d8e80; 1 drivers +v0x10abba0_2 .net/s v0x10abba0 2, 10 0, L_0x10d91f0; 1 drivers +v0x10abba0_3 .net/s v0x10abba0 3, 10 0, L_0x10d9290; 1 drivers +v0x10abba0_4 .net/s v0x10abba0 4, 10 0, L_0x10d9330; 1 drivers +v0x10abba0_5 .net/s v0x10abba0 5, 10 0, L_0x10d93d0; 1 drivers +o0x2b8038e4e148 .functor BUFZ 11, C4; HiZ drive +v0x10abba0_6 .net/s v0x10abba0 6, 10 0, o0x2b8038e4e148; 0 drivers +o0x2b8038e4e178 .functor BUFZ 11, C4; HiZ drive +v0x10abba0_7 .net/s v0x10abba0 7, 10 0, o0x2b8038e4e178; 0 drivers +o0x2b8038e4e1a8 .functor BUFZ 15, C4; HiZ drive +v0x10abdb0_0 .net "right", 14 0, o0x2b8038e4e1a8; 0 drivers +v0x10abe90_0 .net "rightOut", 14 0, L_0x10dc990; 1 drivers +v0x10abf70_0 .net "up", 14 0, L_0x10e06c0; alias, 1 drivers +v0x10ac060_0 .net "upOut", 14 0, L_0x10dbf20; alias, 1 drivers +v0x10ac130_0 .var "weHaveData", 5 2; +v0x10ac1f0_0 .var "weWantData", 5 2; +v0x10ac2d0_0 .net "writeAckIn", 5 2, L_0x10dab20; 1 drivers +v0x10ac3b0_0 .var "writeAckOut", 5 2; +v0x10ac490_0 .var "writeTarget", 2 0; +v0x10ac570_0 .var/s "writeValue", 10 0; +L_0x10d91f0 .part o0x2b8038e4dd88, 0, 11; +L_0x10d9290 .part o0x2b8038e4e1a8, 0, 11; +L_0x10d9330 .part L_0x10e06c0, 0, 11; +L_0x10d93d0 .part o0x2b8038e4dcc8, 0, 11; +L_0x10d94d0 .part o0x2b8038e4dd88, 11, 1; +L_0x10d95f0 .part o0x2b8038e4e1a8, 11, 1; +L_0x10d96e0 .part L_0x10e06c0, 11, 1; +L_0x10d9810 .concat8 [ 1 1 1 1], L_0x10d94d0, L_0x10d95f0, L_0x10d96e0, L_0x10d99d0; +L_0x10d99d0 .part o0x2b8038e4dcc8, 11, 1; +L_0x10d9b10 .reduce/or L_0x10d9810; +L_0x10d9c00 .part o0x2b8038e4dd88, 12, 1; +L_0x10d9ca0 .part o0x2b8038e4e1a8, 12, 1; +L_0x10d9db0 .part L_0x10e06c0, 12, 1; +L_0x10d9e50 .concat8 [ 1 1 1 1], L_0x10d9c00, L_0x10d9ca0, L_0x10d9db0, L_0x10d9fc0; +L_0x10d9fc0 .part o0x2b8038e4dcc8, 12, 1; +L_0x10da0b0 .reduce/or L_0x10d9e50; +L_0x10da230 .part o0x2b8038e4dd88, 13, 1; +L_0x10da360 .part o0x2b8038e4e1a8, 13, 1; +L_0x10da530 .part L_0x10e06c0, 13, 1; +L_0x10da5d0 .concat8 [ 1 1 1 1], L_0x10da230, L_0x10da360, L_0x10da530, L_0x10da490; +L_0x10da490 .part o0x2b8038e4dcc8, 13, 1; +L_0x10da850 .reduce/or L_0x10da5d0; +L_0x10da6c0 .part o0x2b8038e4dd88, 14, 1; +L_0x10da9b0 .part o0x2b8038e4e1a8, 14, 1; +L_0x10da8f0 .part L_0x10e06c0, 14, 1; +L_0x10dab20 .concat8 [ 1 1 1 1], L_0x10da6c0, L_0x10da9b0, L_0x10da8f0, L_0x10daa50; +L_0x10daa50 .part o0x2b8038e4dcc8, 14, 1; +L_0x10dae10 .reduce/or L_0x10dab20; +L_0x10dace0 .part v0x10ab9c0_0, 0, 1; +L_0x10daff0 .part v0x10ab9c0_0, 1, 1; +L_0x10daf00 .part v0x10ab9c0_0, 2, 1; +L_0x10db1e0 .part v0x10ab9c0_0, 3, 1; +L_0x10db0e0 .part v0x10ac3b0_0, 0, 1; +L_0x10db420 .part v0x10ac3b0_0, 1, 1; +L_0x10db310 .part v0x10ac3b0_0, 2, 1; +L_0x10db5e0 .part v0x10ac3b0_0, 3, 1; +L_0x10db4c0 .part v0x10ac1f0_0, 0, 1; +L_0x10db840 .part v0x10ac1f0_0, 1, 1; +L_0x10db710 .part v0x10ac1f0_0, 2, 1; +L_0x10dba20 .part v0x10ac1f0_0, 3, 1; +L_0x10db8e0 .part v0x10ac130_0, 0, 1; +L_0x10dbc10 .part v0x10ac130_0, 1, 1; +L_0x10dbac0 .part v0x10ac130_0, 2, 1; +L_0x10dbb60 .part v0x10ac130_0, 3, 1; +L_0x10dbcb0 .array/port v0x10aaeb0, L_0x10dc010; +L_0x10dc010 .concat [ 4 2 0 0], v0x10a80c0_0, L_0x2b8038e7d210; +LS_0x10dbf20_0_0 .concat8 [ 11 1 1 1], v0x10ab2f0_2, L_0x10dbac0, L_0x10db710, L_0x10db310; +LS_0x10dbf20_0_4 .concat8 [ 1 0 0 0], L_0x10daf00; +L_0x10dbf20 .concat8 [ 14 1 0 0], LS_0x10dbf20_0_0, LS_0x10dbf20_0_4; +LS_0x10dc3e0_0_0 .concat8 [ 11 1 1 1], v0x10ab2f0_3, L_0x10dbb60, L_0x10dba20, L_0x10db5e0; +LS_0x10dc3e0_0_4 .concat8 [ 1 0 0 0], L_0x10db1e0; +L_0x10dc3e0 .concat8 [ 14 1 0 0], LS_0x10dc3e0_0_0, LS_0x10dc3e0_0_4; +LS_0x10dc170_0_0 .concat8 [ 11 1 1 1], v0x10ab2f0_0, L_0x10db8e0, L_0x10db4c0, L_0x10db0e0; +LS_0x10dc170_0_4 .concat8 [ 1 0 0 0], L_0x10dace0; +L_0x10dc170 .concat8 [ 14 1 0 0], LS_0x10dc170_0_0, LS_0x10dc170_0_4; +LS_0x10dc990_0_0 .concat8 [ 11 1 1 1], v0x10ab2f0_1, L_0x10dbc10, L_0x10db840, L_0x10db420; +LS_0x10dc990_0_4 .concat8 [ 1 0 0 0], L_0x10daff0; +L_0x10dc990 .concat8 [ 14 1 0 0], LS_0x10dc990_0_0, LS_0x10dc990_0_4; +L_0x10dc680 .part L_0x10d9d40, 14, 4; +L_0x10dcda0 .part L_0x10d9d40, 11, 3; +L_0x10dcbb0 .part L_0x10d9d40, 8, 3; +L_0x10dcff0 .part L_0x10d9d40, 10, 4; +L_0x10dce40 .part L_0x10d9d40, 0, 11; +S_0x10ac7f0 .scope module, "left" "tis100" 2 27, 3 49 0, S_0x10151e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x10ac9f0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x10aca30 .param/str "memFile" 0 3 60, "anyWrite/left.dat"; +L_0x10bcd00 .functor BUFZ 11, v0x10acd80_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10ccda0 .functor BUFZ 11, v0x10acd80_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10cfaf0 .functor BUFZ 18, L_0x10cf900, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x10acd80_0 .var/s "ACC", 10 0; +v0x10ace80_0 .var/s "BAK", 10 0; +v0x10acb90_0 .net "DST", 2 0, L_0x10d0ad0; 1 drivers +v0x10acf60_0 .net/s "IMM", 10 0, L_0x10d0b70; 1 drivers +v0x10ad020_0 .net "INST", 3 0, L_0x10d03b0; 1 drivers +v0x10ad150_0 .net "LABEL", 3 0, L_0x10d0d20; 1 drivers +v0x10ad230_0 .var "PC", 3 0; +v0x10ad310_0 .var "PCNEXT", 3 0; +v0x10ad3f0_0 .net "SRC", 2 0, L_0x10d08e0; 1 drivers +v0x10ad560_0 .net *"_s103", 0 0, L_0x10cec40; 1 drivers +v0x10ad640_0 .net *"_s107", 0 0, L_0x10ceb50; 1 drivers +v0x10ad720_0 .net *"_s111", 0 0, L_0x10cee30; 1 drivers +v0x10ad800_0 .net *"_s115", 0 0, L_0x10ced30; 1 drivers +v0x10ad8e0_0 .net *"_s119", 0 0, L_0x10cf070; 1 drivers +v0x10ad9c0_0 .net *"_s123", 0 0, L_0x10cef60; 1 drivers +v0x10adaa0_0 .net *"_s127", 0 0, L_0x10cf230; 1 drivers +v0x10adb80_0 .net *"_s131", 0 0, L_0x10cf110; 1 drivers +v0x10add30_0 .net *"_s135", 0 0, L_0x10cf490; 1 drivers +v0x10addd0_0 .net *"_s139", 0 0, L_0x10cf360; 1 drivers +v0x10adeb0_0 .net *"_s143", 0 0, L_0x10cf670; 1 drivers +v0x10adf90_0 .net *"_s147", 0 0, L_0x10cf530; 1 drivers +v0x10ae070_0 .net *"_s151", 0 0, L_0x10cf860; 1 drivers +v0x10ae150_0 .net *"_s155", 0 0, L_0x10cf710; 1 drivers +v0x10ae230_0 .net *"_s159", 0 0, L_0x10cf7b0; 1 drivers +v0x10ae310_0 .net *"_s160", 17 0, L_0x10cf900; 1 drivers +v0x10ae3f0_0 .net *"_s162", 5 0, L_0x10cfc60; 1 drivers +L_0x2b8038e7d060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x10ae4d0_0 .net *"_s165", 1 0, L_0x2b8038e7d060; 1 drivers +v0x10b0480_2 .array/port v0x10b0480, 2; +v0x10ae5b0_0 .net *"_s173", 10 0, v0x10b0480_2; 1 drivers +v0x10b0480_3 .array/port v0x10b0480, 3; +v0x10ae690_0 .net *"_s179", 10 0, v0x10b0480_3; 1 drivers +v0x10b0480_0 .array/port v0x10b0480, 0; +v0x10ae770_0 .net *"_s185", 10 0, v0x10b0480_0; 1 drivers +v0x10b0480_1 .array/port v0x10b0480, 1; +v0x10ae850_0 .net *"_s191", 10 0, v0x10b0480_1; 1 drivers +v0x10ae930_0 .net *"_s23", 0 0, L_0x10cd200; 1 drivers +v0x10aea10_0 .net *"_s27", 0 0, L_0x10cd320; 1 drivers +v0x10adc60_0 .net *"_s31", 0 0, L_0x10cd490; 1 drivers +v0x10aece0_0 .net *"_s36", 0 0, L_0x10cd740; 1 drivers +v0x10aedc0_0 .net *"_s42", 0 0, L_0x10cd9d0; 1 drivers +v0x10aeea0_0 .net *"_s46", 0 0, L_0x10cda70; 1 drivers +v0x10aef80_0 .net *"_s50", 0 0, L_0x10cdb80; 1 drivers +v0x10af060_0 .net *"_s55", 0 0, L_0x10cde10; 1 drivers +v0x10af140_0 .net *"_s61", 0 0, L_0x10cdff0; 1 drivers +v0x10af220_0 .net *"_s65", 0 0, L_0x10ce120; 1 drivers +v0x10af300_0 .net *"_s69", 0 0, L_0x10ce1c0; 1 drivers +v0x10af3e0_0 .net *"_s74", 0 0, L_0x10b0ee0; 1 drivers +v0x10af4c0_0 .net *"_s80", 0 0, L_0x10ce390; 1 drivers +v0x10af5a0_0 .net *"_s84", 0 0, L_0x10ce630; 1 drivers +v0x10af680_0 .net *"_s88", 0 0, L_0x10ce570; 1 drivers +v0x10af760_0 .net *"_s93", 0 0, L_0x10ce6d0; 1 drivers +v0x10af840_0 .net *"_s99", 0 0, L_0x10ce930; 1 drivers +v0x10af920_0 .net/s "accOut", 10 0, L_0x10bcd00; alias, 1 drivers +v0x10afa00_0 .net "anyHasData", 0 0, L_0x10cd880; 1 drivers +v0x10afac0_0 .net "anyReadAck", 0 0, L_0x10ce4d0; 1 drivers +v0x10afb80_0 .net "anyWantData", 0 0, L_0x10cdf00; 1 drivers +v0x10afc40_0 .net "anyWriteAck", 0 0, L_0x10cea60; 1 drivers +v0x10afd00_0 .net "clk", 0 0, v0x10bcae0_0; alias, 1 drivers +o0x2b8038e4eef8 .functor BUFZ 15, C4; HiZ drive +v0x10afda0_0 .net "down", 14 0, o0x2b8038e4eef8; 0 drivers +v0x10afe80_0 .net "downOut", 14 0, L_0x10d00d0; 1 drivers +v0x10aff60_0 .net "instruction", 17 0, L_0x10cfaf0; 1 drivers +v0x10b0040 .array "instructions", 15 0, 17 0; +v0x10b0100_0 .var "last", 2 0; +o0x2b8038e4efb8 .functor BUFZ 15, C4; HiZ drive +v0x10b01e0_0 .net "left", 14 0, o0x2b8038e4efb8; 0 drivers +v0x10b02c0_0 .net "leftOut", 14 0, L_0x10cfdc0; 1 drivers +v0x10b03a0_0 .var "mode", 2 0; +v0x10b0480 .array/s "outVals", 2 5, 10 0; +v0x10b05c0_0 .var "phase", 2 0; +v0x10b06a0_0 .net "portsHaveData", 5 2, L_0x10cd530; 1 drivers +v0x10aeab0_0 .net "portsWantData", 5 2, L_0x10cdc20; 1 drivers +v0x10aeb90_0 .net "readAckIn", 5 2, L_0x10ce2f0; 1 drivers +v0x10b0b50_0 .var "readAckOut", 5 2; +v0x10b0bf0_0 .var "readTarget", 2 0; +v0x10b0cd0_0 .var/s "readValue", 10 0; +L_0x2b8038e7d018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x10b0db0 .array "regVals", 0 7; +v0x10b0db0_0 .net/s v0x10b0db0 0, 10 0, L_0x2b8038e7d018; 1 drivers +v0x10b0db0_1 .net/s v0x10b0db0 1, 10 0, L_0x10ccda0; 1 drivers +v0x10b0db0_2 .net/s v0x10b0db0 2, 10 0, L_0x10cce60; 1 drivers +v0x10b0db0_3 .net/s v0x10b0db0 3, 10 0, L_0x10ccf00; 1 drivers +v0x10b0db0_4 .net/s v0x10b0db0 4, 10 0, L_0x10ccfd0; 1 drivers +v0x10b0db0_5 .net/s v0x10b0db0 5, 10 0, L_0x10cd0d0; 1 drivers +o0x2b8038e4f378 .functor BUFZ 11, C4; HiZ drive +v0x10b0db0_6 .net/s v0x10b0db0 6, 10 0, o0x2b8038e4f378; 0 drivers +o0x2b8038e4f3a8 .functor BUFZ 11, C4; HiZ drive +v0x10b0db0_7 .net/s v0x10b0db0 7, 10 0, o0x2b8038e4f3a8; 0 drivers +v0x10b0fc0_0 .net "right", 14 0, L_0x10e03e0; alias, 1 drivers +v0x10b10b0_0 .net "rightOut", 14 0, L_0x10d06c0; alias, 1 drivers +o0x2b8038e4f3d8 .functor BUFZ 15, C4; HiZ drive +v0x10b1180_0 .net "up", 14 0, o0x2b8038e4f3d8; 0 drivers +v0x10b1240_0 .net "upOut", 14 0, L_0x10cfe80; 1 drivers +v0x10b1320_0 .var "weHaveData", 5 2; +v0x10b1400_0 .var "weWantData", 5 2; +v0x10b14e0_0 .net "writeAckIn", 5 2, L_0x10ce7a0; 1 drivers +v0x10b15c0_0 .var "writeAckOut", 5 2; +v0x10b16a0_0 .var "writeTarget", 2 0; +v0x10b1780_0 .var/s "writeValue", 10 0; +L_0x10cce60 .part o0x2b8038e4efb8, 0, 11; +L_0x10ccf00 .part L_0x10e03e0, 0, 11; +L_0x10ccfd0 .part o0x2b8038e4f3d8, 0, 11; +L_0x10cd0d0 .part o0x2b8038e4eef8, 0, 11; +L_0x10cd200 .part o0x2b8038e4efb8, 11, 1; +L_0x10cd320 .part L_0x10e03e0, 11, 1; +L_0x10cd490 .part o0x2b8038e4f3d8, 11, 1; +L_0x10cd530 .concat8 [ 1 1 1 1], L_0x10cd200, L_0x10cd320, L_0x10cd490, L_0x10cd740; +L_0x10cd740 .part o0x2b8038e4eef8, 11, 1; +L_0x10cd880 .reduce/or L_0x10cd530; +L_0x10cd9d0 .part o0x2b8038e4efb8, 12, 1; +L_0x10cda70 .part L_0x10e03e0, 12, 1; +L_0x10cdb80 .part o0x2b8038e4f3d8, 12, 1; +L_0x10cdc20 .concat8 [ 1 1 1 1], L_0x10cd9d0, L_0x10cda70, L_0x10cdb80, L_0x10cde10; +L_0x10cde10 .part o0x2b8038e4eef8, 12, 1; +L_0x10cdf00 .reduce/or L_0x10cdc20; +L_0x10cdff0 .part o0x2b8038e4efb8, 13, 1; +L_0x10ce120 .part L_0x10e03e0, 13, 1; +L_0x10ce1c0 .part o0x2b8038e4f3d8, 13, 1; +L_0x10ce2f0 .concat8 [ 1 1 1 1], L_0x10cdff0, L_0x10ce120, L_0x10ce1c0, L_0x10b0ee0; +L_0x10b0ee0 .part o0x2b8038e4eef8, 13, 1; +L_0x10ce4d0 .reduce/or L_0x10ce2f0; +L_0x10ce390 .part o0x2b8038e4efb8, 14, 1; +L_0x10ce630 .part L_0x10e03e0, 14, 1; +L_0x10ce570 .part o0x2b8038e4f3d8, 14, 1; +L_0x10ce7a0 .concat8 [ 1 1 1 1], L_0x10ce390, L_0x10ce630, L_0x10ce570, L_0x10ce6d0; +L_0x10ce6d0 .part o0x2b8038e4eef8, 14, 1; +L_0x10cea60 .reduce/or L_0x10ce7a0; +L_0x10ce930 .part v0x10b0b50_0, 0, 1; +L_0x10cec40 .part v0x10b0b50_0, 1, 1; +L_0x10ceb50 .part v0x10b0b50_0, 2, 1; +L_0x10cee30 .part v0x10b0b50_0, 3, 1; +L_0x10ced30 .part v0x10b15c0_0, 0, 1; +L_0x10cf070 .part v0x10b15c0_0, 1, 1; +L_0x10cef60 .part v0x10b15c0_0, 2, 1; +L_0x10cf230 .part v0x10b15c0_0, 3, 1; +L_0x10cf110 .part v0x10b1400_0, 0, 1; +L_0x10cf490 .part v0x10b1400_0, 1, 1; +L_0x10cf360 .part v0x10b1400_0, 2, 1; +L_0x10cf670 .part v0x10b1400_0, 3, 1; +L_0x10cf530 .part v0x10b1320_0, 0, 1; +L_0x10cf860 .part v0x10b1320_0, 1, 1; +L_0x10cf710 .part v0x10b1320_0, 2, 1; +L_0x10cf7b0 .part v0x10b1320_0, 3, 1; +L_0x10cf900 .array/port v0x10b0040, L_0x10cfc60; +L_0x10cfc60 .concat [ 4 2 0 0], v0x10ad230_0, L_0x2b8038e7d060; +LS_0x10cfe80_0_0 .concat8 [ 11 1 1 1], v0x10b0480_2, L_0x10cf710, L_0x10cf360, L_0x10cef60; +LS_0x10cfe80_0_4 .concat8 [ 1 0 0 0], L_0x10ceb50; +L_0x10cfe80 .concat8 [ 14 1 0 0], LS_0x10cfe80_0_0, LS_0x10cfe80_0_4; +LS_0x10d00d0_0_0 .concat8 [ 11 1 1 1], v0x10b0480_3, L_0x10cf7b0, L_0x10cf670, L_0x10cf230; +LS_0x10d00d0_0_4 .concat8 [ 1 0 0 0], L_0x10cee30; +L_0x10d00d0 .concat8 [ 14 1 0 0], LS_0x10d00d0_0_0, LS_0x10d00d0_0_4; +LS_0x10cfdc0_0_0 .concat8 [ 11 1 1 1], v0x10b0480_0, L_0x10cf530, L_0x10cf110, L_0x10ced30; +LS_0x10cfdc0_0_4 .concat8 [ 1 0 0 0], L_0x10ce930; +L_0x10cfdc0 .concat8 [ 14 1 0 0], LS_0x10cfdc0_0_0, LS_0x10cfdc0_0_4; +LS_0x10d06c0_0_0 .concat8 [ 11 1 1 1], v0x10b0480_1, L_0x10cf860, L_0x10cf490, L_0x10cf070; +LS_0x10d06c0_0_4 .concat8 [ 1 0 0 0], L_0x10cec40; +L_0x10d06c0 .concat8 [ 14 1 0 0], LS_0x10d06c0_0_0, LS_0x10d06c0_0_4; +L_0x10d03b0 .part L_0x10cfaf0, 14, 4; +L_0x10d0ad0 .part L_0x10cfaf0, 11, 3; +L_0x10d08e0 .part L_0x10cfaf0, 8, 3; +L_0x10d0d20 .part L_0x10cfaf0, 10, 4; +L_0x10d0b70 .part L_0x10cfaf0, 0, 11; +S_0x10b1a00 .scope module, "right" "tis100" 2 28, 3 49 0, S_0x10151e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x10b1bd0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x10b1c10 .param/str "memFile" 0 3 60, "anyWrite/right.dat"; +L_0x10d0a10 .functor BUFZ 11, v0x10b1f80_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10d0c10 .functor BUFZ 11, v0x10b1f80_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10d1b60 .functor BUFZ 18, L_0x10d3b50, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x10b1f80_0 .var/s "ACC", 10 0; +v0x10b2080_0 .var/s "BAK", 10 0; +v0x10b2160_0 .net "DST", 2 0, L_0x10d4c90; 1 drivers +v0x10b2220_0 .net/s "IMM", 10 0, L_0x10d4d30; 1 drivers +v0x10b2300_0 .net "INST", 3 0, L_0x10d4570; 1 drivers +v0x10b23e0_0 .net "LABEL", 3 0, L_0x10d4ee0; 1 drivers +v0x10b24c0_0 .var "PC", 3 0; +v0x10b25a0_0 .var "PCNEXT", 3 0; +v0x10b2680_0 .net "SRC", 2 0, L_0x10d4aa0; 1 drivers +v0x10b27f0_0 .net *"_s103", 0 0, L_0x10d2e90; 1 drivers +v0x10b28d0_0 .net *"_s107", 0 0, L_0x10d2da0; 1 drivers +v0x10b29b0_0 .net *"_s111", 0 0, L_0x10d3080; 1 drivers +v0x10b2a90_0 .net *"_s115", 0 0, L_0x10d2f80; 1 drivers +v0x10b2b70_0 .net *"_s119", 0 0, L_0x10d32c0; 1 drivers +v0x10b2c50_0 .net *"_s123", 0 0, L_0x10d31b0; 1 drivers +v0x10b2d30_0 .net *"_s127", 0 0, L_0x10d3480; 1 drivers +v0x10b2e10_0 .net *"_s131", 0 0, L_0x10d3360; 1 drivers +v0x10b2fc0_0 .net *"_s135", 0 0, L_0x10d36e0; 1 drivers +v0x10b3060_0 .net *"_s139", 0 0, L_0x10d35b0; 1 drivers +v0x10b3140_0 .net *"_s143", 0 0, L_0x10d38c0; 1 drivers +v0x10b3220_0 .net *"_s147", 0 0, L_0x10d3780; 1 drivers +v0x10b3300_0 .net *"_s151", 0 0, L_0x10d3ab0; 1 drivers +v0x10b33e0_0 .net *"_s155", 0 0, L_0x10d3960; 1 drivers +v0x10b34c0_0 .net *"_s159", 0 0, L_0x10d3a00; 1 drivers +v0x10b35a0_0 .net *"_s160", 17 0, L_0x10d3b50; 1 drivers +v0x10b3680_0 .net *"_s162", 5 0, L_0x10d3eb0; 1 drivers +L_0x2b8038e7d0f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x10b3760_0 .net *"_s165", 1 0, L_0x2b8038e7d0f0; 1 drivers +v0x10b5690_2 .array/port v0x10b5690, 2; +v0x10b3840_0 .net *"_s173", 10 0, v0x10b5690_2; 1 drivers +v0x10b5690_3 .array/port v0x10b5690, 3; +v0x10b3920_0 .net *"_s179", 10 0, v0x10b5690_3; 1 drivers +v0x10b5690_0 .array/port v0x10b5690, 0; +v0x10b3a00_0 .net *"_s185", 10 0, v0x10b5690_0; 1 drivers +v0x10b5690_1 .array/port v0x10b5690, 1; +v0x10b3ae0_0 .net *"_s191", 10 0, v0x10b5690_1; 1 drivers +v0x10b3bc0_0 .net *"_s23", 0 0, L_0x10d1290; 1 drivers +v0x10b3ca0_0 .net *"_s27", 0 0, L_0x10d13f0; 1 drivers +v0x10b2ef0_0 .net *"_s31", 0 0, L_0x10d14c0; 1 drivers +v0x10b3f70_0 .net *"_s36", 0 0, L_0x10d1790; 1 drivers +v0x10b4050_0 .net *"_s42", 0 0, L_0x10d1a20; 1 drivers +v0x10b4130_0 .net *"_s46", 0 0, L_0x10d1ac0; 1 drivers +v0x10b4210_0 .net *"_s50", 0 0, L_0x10d1bd0; 1 drivers +v0x10b42f0_0 .net *"_s55", 0 0, L_0x10d1e60; 1 drivers +v0x10b43d0_0 .net *"_s61", 0 0, L_0x10d20d0; 1 drivers +v0x10b44b0_0 .net *"_s65", 0 0, L_0x10d2170; 1 drivers +v0x10b4590_0 .net *"_s69", 0 0, L_0x10d2340; 1 drivers +v0x10b4670_0 .net *"_s74", 0 0, L_0x10d22a0; 1 drivers +v0x10b4750_0 .net *"_s80", 0 0, L_0x10d2530; 1 drivers +v0x10b4830_0 .net *"_s84", 0 0, L_0x10d2820; 1 drivers +v0x10b4910_0 .net *"_s88", 0 0, L_0x10d2760; 1 drivers +v0x10b49f0_0 .net *"_s93", 0 0, L_0x10d28c0; 1 drivers +v0x10b4ad0_0 .net *"_s99", 0 0, L_0x10d2b80; 1 drivers +v0x10b4bb0_0 .net/s "accOut", 10 0, L_0x10d0a10; alias, 1 drivers +v0x10b4c90_0 .net "anyHasData", 0 0, L_0x10d18d0; 1 drivers +v0x10b4d50_0 .net "anyReadAck", 0 0, L_0x10d26c0; 1 drivers +v0x10b4e10_0 .net "anyWantData", 0 0, L_0x10d1f50; 1 drivers +v0x10b4ed0_0 .net "anyWriteAck", 0 0, L_0x10d2cb0; 1 drivers +v0x10b4f90_0 .net "clk", 0 0, v0x10bcae0_0; alias, 1 drivers +o0x2b8038e50128 .functor BUFZ 15, C4; HiZ drive +v0x10b5030_0 .net "down", 14 0, o0x2b8038e50128; 0 drivers +v0x10b5110_0 .net "downOut", 14 0, L_0x10d42d0; 1 drivers +v0x10b51f0_0 .net "instruction", 17 0, L_0x10d1b60; 1 drivers +v0x10b52d0 .array "instructions", 15 0, 17 0; +v0x10b5390_0 .var "last", 2 0; +v0x10b5470_0 .net "left", 14 0, L_0x10e0db0; alias, 1 drivers +v0x10b5530_0 .net "leftOut", 14 0, L_0x10d4010; alias, 1 drivers +v0x10b55d0_0 .var "mode", 2 0; +v0x10b5690 .array/s "outVals", 2 5, 10 0; +v0x10b5800_0 .var "phase", 2 0; +v0x10b58e0_0 .net "portsHaveData", 5 2, L_0x10d15b0; 1 drivers +v0x10b3d40_0 .net "portsWantData", 5 2, L_0x10d1c70; 1 drivers +v0x10b3e20_0 .net "readAckIn", 5 2, L_0x10d23e0; 1 drivers +v0x10b5d90_0 .var "readAckOut", 5 2; +v0x10b5e30_0 .var "readTarget", 2 0; +v0x10b5ed0_0 .var/s "readValue", 10 0; +L_0x2b8038e7d0a8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x10b5f70 .array "regVals", 0 7; +v0x10b5f70_0 .net/s v0x10b5f70 0, 10 0, L_0x2b8038e7d0a8; 1 drivers +v0x10b5f70_1 .net/s v0x10b5f70 1, 10 0, L_0x10d0c10; 1 drivers +v0x10b5f70_2 .net/s v0x10b5f70 2, 10 0, L_0x10d0f80; 1 drivers +v0x10b5f70_3 .net/s v0x10b5f70 3, 10 0, L_0x10d1020; 1 drivers +v0x10b5f70_4 .net/s v0x10b5f70 4, 10 0, L_0x10d10c0; 1 drivers +v0x10b5f70_5 .net/s v0x10b5f70 5, 10 0, L_0x10d1160; 1 drivers +o0x2b8038e50548 .functor BUFZ 11, C4; HiZ drive +v0x10b5f70_6 .net/s v0x10b5f70 6, 10 0, o0x2b8038e50548; 0 drivers +o0x2b8038e50578 .functor BUFZ 11, C4; HiZ drive +v0x10b5f70_7 .net/s v0x10b5f70 7, 10 0, o0x2b8038e50578; 0 drivers +o0x2b8038e505a8 .functor BUFZ 15, C4; HiZ drive +v0x10b6180_0 .net "right", 14 0, o0x2b8038e505a8; 0 drivers +v0x10b6260_0 .net "rightOut", 14 0, L_0x10d4880; 1 drivers +o0x2b8038e50608 .functor BUFZ 15, C4; HiZ drive +v0x10b6340_0 .net "up", 14 0, o0x2b8038e50608; 0 drivers +v0x10b6420_0 .net "upOut", 14 0, L_0x10d3dc0; 1 drivers +v0x10b6500_0 .var "weHaveData", 5 2; +v0x10b65e0_0 .var "weWantData", 5 2; +v0x10b66c0_0 .net "writeAckIn", 5 2, L_0x10d2990; 1 drivers +v0x10b67a0_0 .var "writeAckOut", 5 2; +v0x10b6880_0 .var "writeTarget", 2 0; +v0x10b6960_0 .var/s "writeValue", 10 0; +L_0x10d0f80 .part L_0x10e0db0, 0, 11; +L_0x10d1020 .part o0x2b8038e505a8, 0, 11; +L_0x10d10c0 .part o0x2b8038e50608, 0, 11; +L_0x10d1160 .part o0x2b8038e50128, 0, 11; +L_0x10d1290 .part L_0x10e0db0, 11, 1; +L_0x10d13f0 .part o0x2b8038e505a8, 11, 1; +L_0x10d14c0 .part o0x2b8038e50608, 11, 1; +L_0x10d15b0 .concat8 [ 1 1 1 1], L_0x10d1290, L_0x10d13f0, L_0x10d14c0, L_0x10d1790; +L_0x10d1790 .part o0x2b8038e50128, 11, 1; +L_0x10d18d0 .reduce/or L_0x10d15b0; +L_0x10d1a20 .part L_0x10e0db0, 12, 1; +L_0x10d1ac0 .part o0x2b8038e505a8, 12, 1; +L_0x10d1bd0 .part o0x2b8038e50608, 12, 1; +L_0x10d1c70 .concat8 [ 1 1 1 1], L_0x10d1a20, L_0x10d1ac0, L_0x10d1bd0, L_0x10d1e60; +L_0x10d1e60 .part o0x2b8038e50128, 12, 1; +L_0x10d1f50 .reduce/or L_0x10d1c70; +L_0x10d20d0 .part L_0x10e0db0, 13, 1; +L_0x10d2170 .part o0x2b8038e505a8, 13, 1; +L_0x10d2340 .part o0x2b8038e50608, 13, 1; +L_0x10d23e0 .concat8 [ 1 1 1 1], L_0x10d20d0, L_0x10d2170, L_0x10d2340, L_0x10d22a0; +L_0x10d22a0 .part o0x2b8038e50128, 13, 1; +L_0x10d26c0 .reduce/or L_0x10d23e0; +L_0x10d2530 .part L_0x10e0db0, 14, 1; +L_0x10d2820 .part o0x2b8038e505a8, 14, 1; +L_0x10d2760 .part o0x2b8038e50608, 14, 1; +L_0x10d2990 .concat8 [ 1 1 1 1], L_0x10d2530, L_0x10d2820, L_0x10d2760, L_0x10d28c0; +L_0x10d28c0 .part o0x2b8038e50128, 14, 1; +L_0x10d2cb0 .reduce/or L_0x10d2990; +L_0x10d2b80 .part v0x10b5d90_0, 0, 1; +L_0x10d2e90 .part v0x10b5d90_0, 1, 1; +L_0x10d2da0 .part v0x10b5d90_0, 2, 1; +L_0x10d3080 .part v0x10b5d90_0, 3, 1; +L_0x10d2f80 .part v0x10b67a0_0, 0, 1; +L_0x10d32c0 .part v0x10b67a0_0, 1, 1; +L_0x10d31b0 .part v0x10b67a0_0, 2, 1; +L_0x10d3480 .part v0x10b67a0_0, 3, 1; +L_0x10d3360 .part v0x10b65e0_0, 0, 1; +L_0x10d36e0 .part v0x10b65e0_0, 1, 1; +L_0x10d35b0 .part v0x10b65e0_0, 2, 1; +L_0x10d38c0 .part v0x10b65e0_0, 3, 1; +L_0x10d3780 .part v0x10b6500_0, 0, 1; +L_0x10d3ab0 .part v0x10b6500_0, 1, 1; +L_0x10d3960 .part v0x10b6500_0, 2, 1; +L_0x10d3a00 .part v0x10b6500_0, 3, 1; +L_0x10d3b50 .array/port v0x10b52d0, L_0x10d3eb0; +L_0x10d3eb0 .concat [ 4 2 0 0], v0x10b24c0_0, L_0x2b8038e7d0f0; +LS_0x10d3dc0_0_0 .concat8 [ 11 1 1 1], v0x10b5690_2, L_0x10d3960, L_0x10d35b0, L_0x10d31b0; +LS_0x10d3dc0_0_4 .concat8 [ 1 0 0 0], L_0x10d2da0; +L_0x10d3dc0 .concat8 [ 14 1 0 0], LS_0x10d3dc0_0_0, LS_0x10d3dc0_0_4; +LS_0x10d42d0_0_0 .concat8 [ 11 1 1 1], v0x10b5690_3, L_0x10d3a00, L_0x10d38c0, L_0x10d3480; +LS_0x10d42d0_0_4 .concat8 [ 1 0 0 0], L_0x10d3080; +L_0x10d42d0 .concat8 [ 14 1 0 0], LS_0x10d42d0_0_0, LS_0x10d42d0_0_4; +LS_0x10d4010_0_0 .concat8 [ 11 1 1 1], v0x10b5690_0, L_0x10d3780, L_0x10d3360, L_0x10d2f80; +LS_0x10d4010_0_4 .concat8 [ 1 0 0 0], L_0x10d2b80; +L_0x10d4010 .concat8 [ 14 1 0 0], LS_0x10d4010_0_0, LS_0x10d4010_0_4; +LS_0x10d4880_0_0 .concat8 [ 11 1 1 1], v0x10b5690_1, L_0x10d3ab0, L_0x10d36e0, L_0x10d32c0; +LS_0x10d4880_0_4 .concat8 [ 1 0 0 0], L_0x10d2e90; +L_0x10d4880 .concat8 [ 14 1 0 0], LS_0x10d4880_0_0, LS_0x10d4880_0_4; +L_0x10d4570 .part L_0x10d1b60, 14, 4; +L_0x10d4c90 .part L_0x10d1b60, 11, 3; +L_0x10d4aa0 .part L_0x10d1b60, 8, 3; +L_0x10d4ee0 .part L_0x10d1b60, 10, 4; +L_0x10d4d30 .part L_0x10d1b60, 0, 11; +S_0x10b6be0 .scope module, "up" "tis100" 2 29, 3 49 0, S_0x10151e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x10b6e00 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x10b6e40 .param/str "memFile" 0 3 60, "anyWrite/up.dat"; +L_0x10d4bd0 .functor BUFZ 11, v0x10b7100_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10d4e20 .functor BUFZ 11, v0x10b7100_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10d5c60 .functor BUFZ 18, L_0x10d7c00, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x10b7100_0 .var/s "ACC", 10 0; +v0x10b7200_0 .var/s "BAK", 10 0; +v0x10b72e0_0 .net "DST", 2 0, L_0x10d8d40; 1 drivers +v0x10b73a0_0 .net/s "IMM", 10 0, L_0x10d8de0; 1 drivers +v0x10b7480_0 .net "INST", 3 0, L_0x10d8620; 1 drivers +v0x10b75b0_0 .net "LABEL", 3 0, L_0x10d8f90; 1 drivers +v0x10b7690_0 .var "PC", 3 0; +v0x10b7770_0 .var "PCNEXT", 3 0; +v0x10b7850_0 .net "SRC", 2 0, L_0x10d8b50; 1 drivers +v0x10b79c0_0 .net *"_s103", 0 0, L_0x10d6f40; 1 drivers +v0x10b7aa0_0 .net *"_s107", 0 0, L_0x10d6e50; 1 drivers +v0x10b7b80_0 .net *"_s111", 0 0, L_0x10d7130; 1 drivers +v0x10b7c60_0 .net *"_s115", 0 0, L_0x10d7030; 1 drivers +v0x10b7d40_0 .net *"_s119", 0 0, L_0x10d7370; 1 drivers +v0x10b7e20_0 .net *"_s123", 0 0, L_0x10d7260; 1 drivers +v0x10b7f00_0 .net *"_s127", 0 0, L_0x10d7530; 1 drivers +v0x10b7fe0_0 .net *"_s131", 0 0, L_0x10d7410; 1 drivers +v0x10b8190_0 .net *"_s135", 0 0, L_0x10d7790; 1 drivers +v0x10b8230_0 .net *"_s139", 0 0, L_0x10d7660; 1 drivers +v0x10b8310_0 .net *"_s143", 0 0, L_0x10d7970; 1 drivers +v0x10b83f0_0 .net *"_s147", 0 0, L_0x10d7830; 1 drivers +v0x10b84d0_0 .net *"_s151", 0 0, L_0x10d7b60; 1 drivers +v0x10b85b0_0 .net *"_s155", 0 0, L_0x10d7a10; 1 drivers +v0x10b8690_0 .net *"_s159", 0 0, L_0x10d7ab0; 1 drivers +v0x10b8770_0 .net *"_s160", 17 0, L_0x10d7c00; 1 drivers +v0x10b8850_0 .net *"_s162", 5 0, L_0x10d7f60; 1 drivers +L_0x2b8038e7d180 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x10b8930_0 .net *"_s165", 1 0, L_0x2b8038e7d180; 1 drivers +v0x10ba8f0_2 .array/port v0x10ba8f0, 2; +v0x10b8a10_0 .net *"_s173", 10 0, v0x10ba8f0_2; 1 drivers +v0x10ba8f0_3 .array/port v0x10ba8f0, 3; +v0x10b8af0_0 .net *"_s179", 10 0, v0x10ba8f0_3; 1 drivers +v0x10ba8f0_0 .array/port v0x10ba8f0, 0; +v0x10b8bd0_0 .net *"_s185", 10 0, v0x10ba8f0_0; 1 drivers +v0x10ba8f0_1 .array/port v0x10ba8f0, 1; +v0x10b8cb0_0 .net *"_s191", 10 0, v0x10ba8f0_1; 1 drivers +v0x10b8d90_0 .net *"_s23", 0 0, L_0x10d5420; 1 drivers +v0x10b8e70_0 .net *"_s27", 0 0, L_0x10d5540; 1 drivers +v0x10b80c0_0 .net *"_s31", 0 0, L_0x10d5630; 1 drivers +v0x10b9140_0 .net *"_s36", 0 0, L_0x10d5900; 1 drivers +v0x10b9220_0 .net *"_s42", 0 0, L_0x10d5b20; 1 drivers +v0x10b9300_0 .net *"_s46", 0 0, L_0x10d5bc0; 1 drivers +v0x10b93e0_0 .net *"_s50", 0 0, L_0x10d5cd0; 1 drivers +v0x10b94c0_0 .net *"_s55", 0 0, L_0x10d5f10; 1 drivers +v0x10b95a0_0 .net *"_s61", 0 0, L_0x10d6180; 1 drivers +v0x10b9680_0 .net *"_s65", 0 0, L_0x10d62b0; 1 drivers +v0x10b9760_0 .net *"_s69", 0 0, L_0x10d6480; 1 drivers +v0x10b9840_0 .net *"_s74", 0 0, L_0x10d63e0; 1 drivers +v0x10b9920_0 .net *"_s80", 0 0, L_0x10d6620; 1 drivers +v0x10b9a00_0 .net *"_s84", 0 0, L_0x10d68d0; 1 drivers +v0x10b9ae0_0 .net *"_s88", 0 0, L_0x10d6810; 1 drivers +v0x10b9bc0_0 .net *"_s93", 0 0, L_0x10d6970; 1 drivers +v0x10b9ca0_0 .net *"_s99", 0 0, L_0x10d6c30; 1 drivers +v0x10b9d80_0 .net/s "accOut", 10 0, L_0x10d4bd0; alias, 1 drivers +v0x10b9e60_0 .net "anyHasData", 0 0, L_0x10d5a80; 1 drivers +v0x10b9f20_0 .net "anyReadAck", 0 0, L_0x10d6720; 1 drivers +v0x10b9fe0_0 .net "anyWantData", 0 0, L_0x10d6000; 1 drivers +v0x10ba0a0_0 .net "anyWriteAck", 0 0, L_0x10d6d60; 1 drivers +v0x10ba160_0 .net "clk", 0 0, v0x10bcae0_0; alias, 1 drivers +v0x10ba290_0 .net "down", 14 0, L_0x10e0110; alias, 1 drivers +v0x10ba350_0 .net "downOut", 14 0, L_0x10d8380; alias, 1 drivers +v0x10ba3f0_0 .net "instruction", 17 0, L_0x10d5c60; 1 drivers +v0x10ba4b0 .array "instructions", 15 0, 17 0; +v0x10ba570_0 .var "last", 2 0; +o0x2b8038e513b8 .functor BUFZ 15, C4; HiZ drive +v0x10ba650_0 .net "left", 14 0, o0x2b8038e513b8; 0 drivers +v0x10ba730_0 .net "leftOut", 14 0, L_0x10d80c0; 1 drivers +v0x10ba810_0 .var "mode", 2 0; +v0x10ba8f0 .array/s "outVals", 2 5, 10 0; +v0x10baa60_0 .var "phase", 2 0; +v0x10bab40_0 .net "portsHaveData", 5 2, L_0x10d5720; 1 drivers +v0x10b8f10_0 .net "portsWantData", 5 2, L_0x10d5d70; 1 drivers +v0x10b8ff0_0 .net "readAckIn", 5 2, L_0x10d6520; 1 drivers +v0x10baff0_0 .var "readAckOut", 5 2; +v0x10bb090_0 .var "readTarget", 2 0; +v0x10bb130_0 .var/s "readValue", 10 0; +L_0x2b8038e7d138 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x10bb1d0 .array "regVals", 0 7; +v0x10bb1d0_0 .net/s v0x10bb1d0 0, 10 0, L_0x2b8038e7d138; 1 drivers +v0x10bb1d0_1 .net/s v0x10bb1d0 1, 10 0, L_0x10d4e20; 1 drivers +v0x10bb1d0_2 .net/s v0x10bb1d0 2, 10 0, L_0x10d5140; 1 drivers +v0x10bb1d0_3 .net/s v0x10bb1d0 3, 10 0, L_0x10d51e0; 1 drivers +v0x10bb1d0_4 .net/s v0x10bb1d0 4, 10 0, L_0x10d5280; 1 drivers +v0x10bb1d0_5 .net/s v0x10bb1d0 5, 10 0, L_0x10d5320; 1 drivers +o0x2b8038e51778 .functor BUFZ 11, C4; HiZ drive +v0x10bb1d0_6 .net/s v0x10bb1d0 6, 10 0, o0x2b8038e51778; 0 drivers +o0x2b8038e517a8 .functor BUFZ 11, C4; HiZ drive +v0x10bb1d0_7 .net/s v0x10bb1d0 7, 10 0, o0x2b8038e517a8; 0 drivers +o0x2b8038e517d8 .functor BUFZ 15, C4; HiZ drive +v0x10bb3e0_0 .net "right", 14 0, o0x2b8038e517d8; 0 drivers +v0x10bb4c0_0 .net "rightOut", 14 0, L_0x10d8930; 1 drivers +o0x2b8038e51838 .functor BUFZ 15, C4; HiZ drive +v0x10bb5a0_0 .net "up", 14 0, o0x2b8038e51838; 0 drivers +v0x10bb680_0 .net "upOut", 14 0, L_0x10d7e70; 1 drivers +v0x10bb760_0 .var "weHaveData", 5 2; +v0x10bb840_0 .var "weWantData", 5 2; +v0x10bb920_0 .net "writeAckIn", 5 2, L_0x10d6a40; 1 drivers +v0x10bba00_0 .var "writeAckOut", 5 2; +v0x10bbae0_0 .var "writeTarget", 2 0; +v0x10bbbc0_0 .var/s "writeValue", 10 0; +L_0x10d5140 .part o0x2b8038e513b8, 0, 11; +L_0x10d51e0 .part o0x2b8038e517d8, 0, 11; +L_0x10d5280 .part o0x2b8038e51838, 0, 11; +L_0x10d5320 .part L_0x10e0110, 0, 11; +L_0x10d5420 .part o0x2b8038e513b8, 11, 1; +L_0x10d5540 .part o0x2b8038e517d8, 11, 1; +L_0x10d5630 .part o0x2b8038e51838, 11, 1; +L_0x10d5720 .concat8 [ 1 1 1 1], L_0x10d5420, L_0x10d5540, L_0x10d5630, L_0x10d5900; +L_0x10d5900 .part L_0x10e0110, 11, 1; +L_0x10d5a80 .reduce/or L_0x10d5720; +L_0x10d5b20 .part o0x2b8038e513b8, 12, 1; +L_0x10d5bc0 .part o0x2b8038e517d8, 12, 1; +L_0x10d5cd0 .part o0x2b8038e51838, 12, 1; +L_0x10d5d70 .concat8 [ 1 1 1 1], L_0x10d5b20, L_0x10d5bc0, L_0x10d5cd0, L_0x10d5f10; +L_0x10d5f10 .part L_0x10e0110, 12, 1; +L_0x10d6000 .reduce/or L_0x10d5d70; +L_0x10d6180 .part o0x2b8038e513b8, 13, 1; +L_0x10d62b0 .part o0x2b8038e517d8, 13, 1; +L_0x10d6480 .part o0x2b8038e51838, 13, 1; +L_0x10d6520 .concat8 [ 1 1 1 1], L_0x10d6180, L_0x10d62b0, L_0x10d6480, L_0x10d63e0; +L_0x10d63e0 .part L_0x10e0110, 13, 1; +L_0x10d6720 .reduce/or L_0x10d6520; +L_0x10d6620 .part o0x2b8038e513b8, 14, 1; +L_0x10d68d0 .part o0x2b8038e517d8, 14, 1; +L_0x10d6810 .part o0x2b8038e51838, 14, 1; +L_0x10d6a40 .concat8 [ 1 1 1 1], L_0x10d6620, L_0x10d68d0, L_0x10d6810, L_0x10d6970; +L_0x10d6970 .part L_0x10e0110, 14, 1; +L_0x10d6d60 .reduce/or L_0x10d6a40; +L_0x10d6c30 .part v0x10baff0_0, 0, 1; +L_0x10d6f40 .part v0x10baff0_0, 1, 1; +L_0x10d6e50 .part v0x10baff0_0, 2, 1; +L_0x10d7130 .part v0x10baff0_0, 3, 1; +L_0x10d7030 .part v0x10bba00_0, 0, 1; +L_0x10d7370 .part v0x10bba00_0, 1, 1; +L_0x10d7260 .part v0x10bba00_0, 2, 1; +L_0x10d7530 .part v0x10bba00_0, 3, 1; +L_0x10d7410 .part v0x10bb840_0, 0, 1; +L_0x10d7790 .part v0x10bb840_0, 1, 1; +L_0x10d7660 .part v0x10bb840_0, 2, 1; +L_0x10d7970 .part v0x10bb840_0, 3, 1; +L_0x10d7830 .part v0x10bb760_0, 0, 1; +L_0x10d7b60 .part v0x10bb760_0, 1, 1; +L_0x10d7a10 .part v0x10bb760_0, 2, 1; +L_0x10d7ab0 .part v0x10bb760_0, 3, 1; +L_0x10d7c00 .array/port v0x10ba4b0, L_0x10d7f60; +L_0x10d7f60 .concat [ 4 2 0 0], v0x10b7690_0, L_0x2b8038e7d180; +LS_0x10d7e70_0_0 .concat8 [ 11 1 1 1], v0x10ba8f0_2, L_0x10d7a10, L_0x10d7660, L_0x10d7260; +LS_0x10d7e70_0_4 .concat8 [ 1 0 0 0], L_0x10d6e50; +L_0x10d7e70 .concat8 [ 14 1 0 0], LS_0x10d7e70_0_0, LS_0x10d7e70_0_4; +LS_0x10d8380_0_0 .concat8 [ 11 1 1 1], v0x10ba8f0_3, L_0x10d7ab0, L_0x10d7970, L_0x10d7530; +LS_0x10d8380_0_4 .concat8 [ 1 0 0 0], L_0x10d7130; +L_0x10d8380 .concat8 [ 14 1 0 0], LS_0x10d8380_0_0, LS_0x10d8380_0_4; +LS_0x10d80c0_0_0 .concat8 [ 11 1 1 1], v0x10ba8f0_0, L_0x10d7830, L_0x10d7410, L_0x10d7030; +LS_0x10d80c0_0_4 .concat8 [ 1 0 0 0], L_0x10d6c30; +L_0x10d80c0 .concat8 [ 14 1 0 0], LS_0x10d80c0_0_0, LS_0x10d80c0_0_4; +LS_0x10d8930_0_0 .concat8 [ 11 1 1 1], v0x10ba8f0_1, L_0x10d7b60, L_0x10d7790, L_0x10d7370; +LS_0x10d8930_0_4 .concat8 [ 1 0 0 0], L_0x10d6f40; +L_0x10d8930 .concat8 [ 14 1 0 0], LS_0x10d8930_0_0, LS_0x10d8930_0_4; +L_0x10d8620 .part L_0x10d5c60, 14, 4; +L_0x10d8d40 .part L_0x10d5c60, 11, 3; +L_0x10d8b50 .part L_0x10d5c60, 8, 3; +L_0x10d8f90 .part L_0x10d5c60, 10, 4; +L_0x10d8de0 .part L_0x10d5c60, 0, 11; + .scope S_0x10ac7f0; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10b03a0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10b05c0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10b0100_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10acd80_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10ace80_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ad230_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b0b50_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b1400_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b15c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b1320_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b0480, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b0480, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b0480, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b0480, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x10aca30, v0x10b0040 {0 0 0}; + %end; + .thread T_0; + .scope S_0x10ac7f0; +T_1 ; + %wait E_0x1020b80; + %load/vec4 v0x10b03a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %jmp T_1.3; +T_1.0 ; + %load/vec4 v0x10b05c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.6, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0x10ad020_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_1.8, 5; + %load/vec4 v0x10ad3f0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_1.10, 5; + %load/vec4 v0x10ad3f0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0x10ad3f0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_1.12, 5; + %load/vec4 v0x10b06a0_0; + %load/vec4 v0x10ad3f0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0x10ad3f0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10ad3f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %load/vec4 v0x10ad3f0_0; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.15; +T_1.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %load/vec4 v0x10ad3f0_0; + %assign/vec4 v0x10b0bf0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10ad3f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b1400_0, 4, 5; + %load/vec4 v0x10ad3f0_0; + %assign/vec4 v0x10b0100_0, 0; +T_1.15 ; + %jmp T_1.13; +T_1.12 ; + %load/vec4 v0x10ad3f0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.16, 4; + %load/vec4 v0x10b0100_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_1.18, 4; + %load/vec4 v0x10b0100_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %jmp T_1.19; +T_1.18 ; + %load/vec4 v0x10b06a0_0; + %load/vec4 v0x10b0100_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.20, 8; + %load/vec4 v0x10b0100_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b0100_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %jmp T_1.21; +T_1.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %load/vec4 v0x10b0100_0; + %assign/vec4 v0x10b0bf0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b0100_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b1400_0, 4, 5; +T_1.21 ; +T_1.19 ; + %jmp T_1.17; +T_1.16 ; + %load/vec4 v0x10ad3f0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.22, 4; + %load/vec4 v0x10afa00_0; + %flag_set/vec4 8; + %jmp/0xz T_1.24, 8; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.27; +T_1.26 ; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.29; +T_1.28 ; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.31; +T_1.30 ; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b0100_0, 0; +T_1.32 ; +T_1.31 ; +T_1.29 ; +T_1.27 ; + %jmp T_1.25; +T_1.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %load/vec4 v0x10ad3f0_0; + %assign/vec4 v0x10b0bf0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1400_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1400_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1400_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1400_0, 4, 5; +T_1.25 ; +T_1.22 ; +T_1.17 ; +T_1.13 ; +T_1.11 ; +T_1.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0x10ad020_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_1.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_1.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_1.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_1.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_1.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_1.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_1.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_1.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_1.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_1.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_1.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_1.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_1.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_1.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_1.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_1.49, 6; + %jmp T_1.50; +T_1.34 ; + %load/vec4 v0x10acd80_0; + %load/vec4 v0x10b0cd0_0; + %add; + %assign/vec4 v0x10acd80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.35 ; + %load/vec4 v0x10acd80_0; + %load/vec4 v0x10b0cd0_0; + %sub; + %assign/vec4 v0x10acd80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.36 ; + %load/vec4 v0x10ad230_0; + %pad/u 11; + %load/vec4 v0x10b0cd0_0; + %add; + %pad/u 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.37 ; + %load/vec4 v0x10b0cd0_0; + %assign/vec4 v0x10b1780_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.38 ; + %load/vec4 v0x10acf60_0; + %assign/vec4 v0x10b1780_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.39 ; + %load/vec4 v0x10acd80_0; + %load/vec4 v0x10acf60_0; + %add; + %assign/vec4 v0x10acd80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.40 ; + %load/vec4 v0x10acd80_0; + %load/vec4 v0x10acf60_0; + %sub; + %assign/vec4 v0x10acd80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.41 ; + %load/vec4 v0x10ad230_0; + %pad/u 11; + %load/vec4 v0x10acf60_0; + %add; + %pad/u 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.42 ; + %load/vec4 v0x10ace80_0; + %assign/vec4 v0x10acd80_0, 0; + %load/vec4 v0x10acd80_0; + %assign/vec4 v0x10ace80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.43 ; + %load/vec4 v0x10acd80_0; + %assign/vec4 v0x10ace80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.44 ; + %load/vec4 v0x10acd80_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x10acd80_0, 0; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.45 ; + %load/vec4 v0x10ad150_0; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.50; +T_1.46 ; + %load/vec4 v0x10acd80_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_1.51, 4; + %load/vec4 v0x10ad150_0; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.52; +T_1.51 ; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; +T_1.52 ; + %jmp T_1.50; +T_1.47 ; + %load/vec4 v0x10acd80_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.53, 4; + %load/vec4 v0x10ad150_0; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.54; +T_1.53 ; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; +T_1.54 ; + %jmp T_1.50; +T_1.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x10acd80_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_1.55, 5; + %load/vec4 v0x10ad150_0; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.56; +T_1.55 ; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; +T_1.56 ; + %jmp T_1.50; +T_1.49 ; + %load/vec4 v0x10acd80_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_1.57, 5; + %load/vec4 v0x10ad150_0; + %assign/vec4 v0x10ad310_0, 0; + %jmp T_1.58; +T_1.57 ; + %load/vec4 v0x10ad230_0; + %addi 1, 0, 4; + %assign/vec4 v0x10ad310_0, 0; +T_1.58 ; + %jmp T_1.50; +T_1.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x10ad020_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x10ad020_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_1.59, 4; + %load/vec4 v0x10acb90_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x10acb90_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10b0100_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_1.61, 9; + %load/vec4 v0x10acb90_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_1.63, 4; + %load/vec4 v0x10b1780_0; + %assign/vec4 v0x10acd80_0, 0; +T_1.63 ; + %jmp T_1.62; +T_1.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %load/vec4 v0x10acb90_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.65, 4; + %load/vec4 v0x10b0100_0; + %assign/vec4 v0x10b16a0_0, 0; + %load/vec4 v0x10b1780_0; + %load/vec4 v0x10b0100_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b0100_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %jmp T_1.66; +T_1.65 ; + %load/vec4 v0x10acb90_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.67, 4; + %load/vec4 v0x10acb90_0; + %assign/vec4 v0x10b16a0_0, 0; + %load/vec4 v0x10b1780_0; + %load/vec4 v0x10acb90_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10acb90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10acb90_0; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.68; +T_1.67 ; + %load/vec4 v0x10afb80_0; + %flag_set/vec4 8; + %jmp/0xz T_1.69, 8; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.72; +T_1.71 ; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.74; +T_1.73 ; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.76; +T_1.75 ; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b0100_0, 0; +T_1.77 ; +T_1.76 ; +T_1.74 ; +T_1.72 ; + %jmp T_1.70; +T_1.69 ; + %load/vec4 v0x10acb90_0; + %assign/vec4 v0x10b16a0_0, 0; +T_1.70 ; +T_1.68 ; +T_1.66 ; +T_1.62 ; +T_1.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.1 ; + %load/vec4 v0x10b05c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.81, 6; + %jmp T_1.82; +T_1.79 ; + %load/vec4 v0x10b0bf0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.83, 4; + %load/vec4 v0x10afa00_0; + %flag_set/vec4 8; + %jmp/0xz T_1.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b1400_0, 0, 4; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.88; +T_1.87 ; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.90; +T_1.89 ; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.92; +T_1.91 ; + %load/vec4 v0x10b06a0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b0100_0, 0; +T_1.93 ; +T_1.92 ; +T_1.90 ; +T_1.88 ; +T_1.85 ; + %jmp T_1.84; +T_1.83 ; + %load/vec4 v0x10b06a0_0; + %load/vec4 v0x10b0bf0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %load/vec4 v0x10b0bf0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b0db0, 4; + %assign/vec4 v0x10b0cd0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b0bf0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b0b50_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b0bf0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b1400_0, 4, 5; + %load/vec4 v0x10b0bf0_0; + %assign/vec4 v0x10b0100_0, 0; +T_1.95 ; +T_1.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.82; +T_1.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.82; +T_1.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.82; +T_1.82 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x10b05c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.99, 6; + %jmp T_1.100; +T_1.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.100; +T_1.98 ; + %load/vec4 v0x10b16a0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.101, 4; + %load/vec4 v0x10afb80_0; + %flag_set/vec4 8; + %jmp/0xz T_1.103, 8; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.106; +T_1.105 ; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.108; +T_1.107 ; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b0100_0, 0; + %jmp T_1.110; +T_1.109 ; + %load/vec4 v0x10aeab0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b16a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b1320_0, 4, 5; + %load/vec4 v0x10b1780_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b0480, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b0100_0, 0; +T_1.111 ; +T_1.110 ; +T_1.108 ; +T_1.106 ; +T_1.103 ; +T_1.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.100; +T_1.99 ; + %load/vec4 v0x10b16a0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.113, 4; + %load/vec4 v0x10b14e0_0; + %load/vec4 v0x10b16a0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x10b16a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x10b1320_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b03a0_0, 0; + %load/vec4 v0x10b16a0_0; + %assign/vec4 v0x10b0100_0, 0; +T_1.115 ; +T_1.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b05c0_0, 0; + %jmp T_1.100; +T_1.100 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.3 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1; + .scope S_0x10ac7f0; +T_2 ; + %wait E_0xffe3d0; + %load/vec4 v0x10b05c0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10b03a0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x10ad310_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %load/vec4 v0x10ad310_0; + %assign/vec4 v0x10ad230_0, 0; +T_2.0 ; + %load/vec4 v0x10b05c0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_2.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b0b50_0, 0, 4; +T_2.2 ; + %jmp T_2; + .thread T_2; + .scope S_0x10b1a00; +T_3 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10b55d0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10b5800_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10b5390_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10b1f80_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10b2080_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b24c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b5d90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b65e0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b67a0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b6500_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b5690, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b5690, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b5690, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10b5690, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x10b1c10, v0x10b52d0 {0 0 0}; + %end; + .thread T_3; + .scope S_0x10b1a00; +T_4 ; + %wait E_0x1020b80; + %load/vec4 v0x10b55d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0x10b5800_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.6, 6; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0x10b2300_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_4.8, 5; + %load/vec4 v0x10b2680_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_4.10, 5; + %load/vec4 v0x10b2680_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %jmp T_4.11; +T_4.10 ; + %load/vec4 v0x10b2680_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_4.12, 5; + %load/vec4 v0x10b58e0_0; + %load/vec4 v0x10b2680_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.14, 8; + %load/vec4 v0x10b2680_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b2680_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %load/vec4 v0x10b2680_0; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.15; +T_4.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %load/vec4 v0x10b2680_0; + %assign/vec4 v0x10b5e30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b2680_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; + %load/vec4 v0x10b2680_0; + %assign/vec4 v0x10b5390_0, 0; +T_4.15 ; + %jmp T_4.13; +T_4.12 ; + %load/vec4 v0x10b2680_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.16, 4; + %load/vec4 v0x10b5390_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_4.18, 4; + %load/vec4 v0x10b5390_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %jmp T_4.19; +T_4.18 ; + %load/vec4 v0x10b58e0_0; + %load/vec4 v0x10b5390_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.20, 8; + %load/vec4 v0x10b5390_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b5390_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %jmp T_4.21; +T_4.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %load/vec4 v0x10b5390_0; + %assign/vec4 v0x10b5e30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b5390_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; +T_4.21 ; +T_4.19 ; + %jmp T_4.17; +T_4.16 ; + %load/vec4 v0x10b2680_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.22, 4; + %load/vec4 v0x10b4c90_0; + %flag_set/vec4 8; + %jmp/0xz T_4.24, 8; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.27; +T_4.26 ; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.29; +T_4.28 ; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.31; +T_4.30 ; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b5390_0, 0; +T_4.32 ; +T_4.31 ; +T_4.29 ; +T_4.27 ; + %jmp T_4.25; +T_4.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %load/vec4 v0x10b2680_0; + %assign/vec4 v0x10b5e30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; +T_4.25 ; +T_4.22 ; +T_4.17 ; +T_4.13 ; +T_4.11 ; +T_4.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0x10b2300_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_4.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_4.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_4.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_4.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_4.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_4.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_4.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_4.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_4.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_4.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_4.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_4.49, 6; + %jmp T_4.50; +T_4.34 ; + %load/vec4 v0x10b1f80_0; + %load/vec4 v0x10b5ed0_0; + %add; + %assign/vec4 v0x10b1f80_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.35 ; + %load/vec4 v0x10b1f80_0; + %load/vec4 v0x10b5ed0_0; + %sub; + %assign/vec4 v0x10b1f80_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.36 ; + %load/vec4 v0x10b24c0_0; + %pad/u 11; + %load/vec4 v0x10b5ed0_0; + %add; + %pad/u 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.37 ; + %load/vec4 v0x10b5ed0_0; + %assign/vec4 v0x10b6960_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.38 ; + %load/vec4 v0x10b2220_0; + %assign/vec4 v0x10b6960_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.39 ; + %load/vec4 v0x10b1f80_0; + %load/vec4 v0x10b2220_0; + %add; + %assign/vec4 v0x10b1f80_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.40 ; + %load/vec4 v0x10b1f80_0; + %load/vec4 v0x10b2220_0; + %sub; + %assign/vec4 v0x10b1f80_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.41 ; + %load/vec4 v0x10b24c0_0; + %pad/u 11; + %load/vec4 v0x10b2220_0; + %add; + %pad/u 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.42 ; + %load/vec4 v0x10b2080_0; + %assign/vec4 v0x10b1f80_0, 0; + %load/vec4 v0x10b1f80_0; + %assign/vec4 v0x10b2080_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.43 ; + %load/vec4 v0x10b1f80_0; + %assign/vec4 v0x10b2080_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.44 ; + %load/vec4 v0x10b1f80_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x10b1f80_0, 0; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.45 ; + %load/vec4 v0x10b23e0_0; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.50; +T_4.46 ; + %load/vec4 v0x10b1f80_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_4.51, 4; + %load/vec4 v0x10b23e0_0; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.52; +T_4.51 ; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; +T_4.52 ; + %jmp T_4.50; +T_4.47 ; + %load/vec4 v0x10b1f80_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_4.53, 4; + %load/vec4 v0x10b23e0_0; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.54; +T_4.53 ; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; +T_4.54 ; + %jmp T_4.50; +T_4.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x10b1f80_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_4.55, 5; + %load/vec4 v0x10b23e0_0; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.56; +T_4.55 ; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; +T_4.56 ; + %jmp T_4.50; +T_4.49 ; + %load/vec4 v0x10b1f80_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_4.57, 5; + %load/vec4 v0x10b23e0_0; + %assign/vec4 v0x10b25a0_0, 0; + %jmp T_4.58; +T_4.57 ; + %load/vec4 v0x10b24c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b25a0_0, 0; +T_4.58 ; + %jmp T_4.50; +T_4.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.7; +T_4.6 ; + %load/vec4 v0x10b2300_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x10b2300_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_4.59, 4; + %load/vec4 v0x10b2160_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x10b2160_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10b5390_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_4.61, 9; + %load/vec4 v0x10b2160_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_4.63, 4; + %load/vec4 v0x10b6960_0; + %assign/vec4 v0x10b1f80_0, 0; +T_4.63 ; + %jmp T_4.62; +T_4.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %load/vec4 v0x10b2160_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.65, 4; + %load/vec4 v0x10b5390_0; + %assign/vec4 v0x10b6880_0, 0; + %load/vec4 v0x10b6960_0; + %load/vec4 v0x10b5390_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b5390_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %jmp T_4.66; +T_4.65 ; + %load/vec4 v0x10b2160_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.67, 4; + %load/vec4 v0x10b2160_0; + %assign/vec4 v0x10b6880_0, 0; + %load/vec4 v0x10b6960_0; + %load/vec4 v0x10b2160_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b2160_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b2160_0; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.68; +T_4.67 ; + %load/vec4 v0x10b4e10_0; + %flag_set/vec4 8; + %jmp/0xz T_4.69, 8; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.72; +T_4.71 ; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.74; +T_4.73 ; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.76; +T_4.75 ; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b5390_0, 0; +T_4.77 ; +T_4.76 ; +T_4.74 ; +T_4.72 ; + %jmp T_4.70; +T_4.69 ; + %load/vec4 v0x10b2160_0; + %assign/vec4 v0x10b6880_0, 0; +T_4.70 ; +T_4.68 ; +T_4.66 ; +T_4.62 ; +T_4.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.1 ; + %load/vec4 v0x10b5800_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.81, 6; + %jmp T_4.82; +T_4.79 ; + %load/vec4 v0x10b5e30_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.83, 4; + %load/vec4 v0x10b4c90_0; + %flag_set/vec4 8; + %jmp/0xz T_4.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b65e0_0, 0, 4; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.88; +T_4.87 ; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.90; +T_4.89 ; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.92; +T_4.91 ; + %load/vec4 v0x10b58e0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b5390_0, 0; +T_4.93 ; +T_4.92 ; +T_4.90 ; +T_4.88 ; +T_4.85 ; + %jmp T_4.84; +T_4.83 ; + %load/vec4 v0x10b58e0_0; + %load/vec4 v0x10b5e30_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %load/vec4 v0x10b5e30_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10b5f70, 4; + %assign/vec4 v0x10b5ed0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b5e30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b5d90_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b5e30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10b65e0_0, 4, 5; + %load/vec4 v0x10b5e30_0; + %assign/vec4 v0x10b5390_0, 0; +T_4.95 ; +T_4.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.82; +T_4.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.82; +T_4.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.82; +T_4.82 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x10b5800_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.99, 6; + %jmp T_4.100; +T_4.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.100; +T_4.98 ; + %load/vec4 v0x10b6880_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.101, 4; + %load/vec4 v0x10b4e10_0; + %flag_set/vec4 8; + %jmp/0xz T_4.103, 8; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.106; +T_4.105 ; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.108; +T_4.107 ; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10b5390_0, 0; + %jmp T_4.110; +T_4.109 ; + %load/vec4 v0x10b3d40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b6880_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10b6500_0, 4, 5; + %load/vec4 v0x10b6960_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10b5690, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10b5390_0, 0; +T_4.111 ; +T_4.110 ; +T_4.108 ; +T_4.106 ; +T_4.103 ; +T_4.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.100; +T_4.99 ; + %load/vec4 v0x10b6880_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.113, 4; + %load/vec4 v0x10b66c0_0; + %load/vec4 v0x10b6880_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x10b6880_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x10b6500_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b55d0_0, 0; + %load/vec4 v0x10b6880_0; + %assign/vec4 v0x10b5390_0, 0; +T_4.115 ; +T_4.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10b5800_0, 0; + %jmp T_4.100; +T_4.100 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0x10b1a00; +T_5 ; + %wait E_0xffe3d0; + %load/vec4 v0x10b5800_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10b55d0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x10b25a0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %load/vec4 v0x10b25a0_0; + %assign/vec4 v0x10b24c0_0, 0; +T_5.0 ; + %load/vec4 v0x10b5800_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_5.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b5d90_0, 0, 4; +T_5.2 ; + %jmp T_5; + .thread T_5; + .scope S_0x10b6be0; +T_6 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10ba810_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10baa60_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10ba570_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10b7100_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10b7200_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10b7690_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10baff0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10bb840_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10bba00_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10bb760_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ba8f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ba8f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ba8f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ba8f0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x10b6e40, v0x10ba4b0 {0 0 0}; + %end; + .thread T_6; + .scope S_0x10b6be0; +T_7 ; + %wait E_0x1020b80; + %load/vec4 v0x10ba810_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.2, 6; + %jmp T_7.3; +T_7.0 ; + %load/vec4 v0x10baa60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.6, 6; + %jmp T_7.7; +T_7.4 ; + %load/vec4 v0x10b7480_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_7.8, 5; + %load/vec4 v0x10b7850_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_7.10, 5; + %load/vec4 v0x10b7850_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %jmp T_7.11; +T_7.10 ; + %load/vec4 v0x10b7850_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_7.12, 5; + %load/vec4 v0x10bab40_0; + %load/vec4 v0x10b7850_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.14, 8; + %load/vec4 v0x10b7850_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b7850_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %load/vec4 v0x10b7850_0; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.15; +T_7.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %load/vec4 v0x10b7850_0; + %assign/vec4 v0x10bb090_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b7850_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10bb840_0, 4, 5; + %load/vec4 v0x10b7850_0; + %assign/vec4 v0x10ba570_0, 0; +T_7.15 ; + %jmp T_7.13; +T_7.12 ; + %load/vec4 v0x10b7850_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.16, 4; + %load/vec4 v0x10ba570_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_7.18, 4; + %load/vec4 v0x10ba570_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %jmp T_7.19; +T_7.18 ; + %load/vec4 v0x10bab40_0; + %load/vec4 v0x10ba570_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.20, 8; + %load/vec4 v0x10ba570_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10ba570_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %jmp T_7.21; +T_7.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %load/vec4 v0x10ba570_0; + %assign/vec4 v0x10bb090_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10ba570_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10bb840_0, 4, 5; +T_7.21 ; +T_7.19 ; + %jmp T_7.17; +T_7.16 ; + %load/vec4 v0x10b7850_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.22, 4; + %load/vec4 v0x10b9e60_0; + %flag_set/vec4 8; + %jmp/0xz T_7.24, 8; + %load/vec4 v0x10bab40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.27; +T_7.26 ; + %load/vec4 v0x10bab40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.29; +T_7.28 ; + %load/vec4 v0x10bab40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.31; +T_7.30 ; + %load/vec4 v0x10bab40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10ba570_0, 0; +T_7.32 ; +T_7.31 ; +T_7.29 ; +T_7.27 ; + %jmp T_7.25; +T_7.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %load/vec4 v0x10b7850_0; + %assign/vec4 v0x10bb090_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb840_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb840_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb840_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb840_0, 4, 5; +T_7.25 ; +T_7.22 ; +T_7.17 ; +T_7.13 ; +T_7.11 ; +T_7.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.7; +T_7.5 ; + %load/vec4 v0x10b7480_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_7.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_7.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_7.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_7.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_7.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_7.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_7.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_7.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_7.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_7.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_7.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_7.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_7.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_7.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_7.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_7.49, 6; + %jmp T_7.50; +T_7.34 ; + %load/vec4 v0x10b7100_0; + %load/vec4 v0x10bb130_0; + %add; + %assign/vec4 v0x10b7100_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.35 ; + %load/vec4 v0x10b7100_0; + %load/vec4 v0x10bb130_0; + %sub; + %assign/vec4 v0x10b7100_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.36 ; + %load/vec4 v0x10b7690_0; + %pad/u 11; + %load/vec4 v0x10bb130_0; + %add; + %pad/u 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.37 ; + %load/vec4 v0x10bb130_0; + %assign/vec4 v0x10bbbc0_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.38 ; + %load/vec4 v0x10b73a0_0; + %assign/vec4 v0x10bbbc0_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.39 ; + %load/vec4 v0x10b7100_0; + %load/vec4 v0x10b73a0_0; + %add; + %assign/vec4 v0x10b7100_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.40 ; + %load/vec4 v0x10b7100_0; + %load/vec4 v0x10b73a0_0; + %sub; + %assign/vec4 v0x10b7100_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.41 ; + %load/vec4 v0x10b7690_0; + %pad/u 11; + %load/vec4 v0x10b73a0_0; + %add; + %pad/u 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.42 ; + %load/vec4 v0x10b7200_0; + %assign/vec4 v0x10b7100_0, 0; + %load/vec4 v0x10b7100_0; + %assign/vec4 v0x10b7200_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.43 ; + %load/vec4 v0x10b7100_0; + %assign/vec4 v0x10b7200_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.44 ; + %load/vec4 v0x10b7100_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x10b7100_0, 0; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.45 ; + %load/vec4 v0x10b75b0_0; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.50; +T_7.46 ; + %load/vec4 v0x10b7100_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_7.51, 4; + %load/vec4 v0x10b75b0_0; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.52; +T_7.51 ; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; +T_7.52 ; + %jmp T_7.50; +T_7.47 ; + %load/vec4 v0x10b7100_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_7.53, 4; + %load/vec4 v0x10b75b0_0; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.54; +T_7.53 ; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; +T_7.54 ; + %jmp T_7.50; +T_7.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x10b7100_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_7.55, 5; + %load/vec4 v0x10b75b0_0; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.56; +T_7.55 ; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; +T_7.56 ; + %jmp T_7.50; +T_7.49 ; + %load/vec4 v0x10b7100_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_7.57, 5; + %load/vec4 v0x10b75b0_0; + %assign/vec4 v0x10b7770_0, 0; + %jmp T_7.58; +T_7.57 ; + %load/vec4 v0x10b7690_0; + %addi 1, 0, 4; + %assign/vec4 v0x10b7770_0, 0; +T_7.58 ; + %jmp T_7.50; +T_7.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.7; +T_7.6 ; + %load/vec4 v0x10b7480_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x10b7480_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_7.59, 4; + %load/vec4 v0x10b72e0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x10b72e0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10ba570_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_7.61, 9; + %load/vec4 v0x10b72e0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_7.63, 4; + %load/vec4 v0x10bbbc0_0; + %assign/vec4 v0x10b7100_0, 0; +T_7.63 ; + %jmp T_7.62; +T_7.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %load/vec4 v0x10b72e0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.65, 4; + %load/vec4 v0x10ba570_0; + %assign/vec4 v0x10bbae0_0, 0; + %load/vec4 v0x10bbbc0_0; + %load/vec4 v0x10ba570_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10ba570_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %jmp T_7.66; +T_7.65 ; + %load/vec4 v0x10b72e0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.67, 4; + %load/vec4 v0x10b72e0_0; + %assign/vec4 v0x10bbae0_0, 0; + %load/vec4 v0x10bbbc0_0; + %load/vec4 v0x10b72e0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10b72e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10b72e0_0; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.68; +T_7.67 ; + %load/vec4 v0x10b9fe0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.69, 8; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.72; +T_7.71 ; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.74; +T_7.73 ; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.76; +T_7.75 ; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10ba570_0, 0; +T_7.77 ; +T_7.76 ; +T_7.74 ; +T_7.72 ; + %jmp T_7.70; +T_7.69 ; + %load/vec4 v0x10b72e0_0; + %assign/vec4 v0x10bbae0_0, 0; +T_7.70 ; +T_7.68 ; +T_7.66 ; +T_7.62 ; +T_7.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.7; +T_7.7 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.1 ; + %load/vec4 v0x10baa60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.81, 6; + %jmp T_7.82; +T_7.79 ; + %load/vec4 v0x10bb090_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.83, 4; + %load/vec4 v0x10b9e60_0; + %flag_set/vec4 8; + %jmp/0xz T_7.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10bb840_0, 0, 4; + %load/vec4 v0x10bab40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.88; +T_7.87 ; + %load/vec4 v0x10bab40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.90; +T_7.89 ; + %load/vec4 v0x10bab40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.92; +T_7.91 ; + %load/vec4 v0x10bab40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10ba570_0, 0; +T_7.93 ; +T_7.92 ; +T_7.90 ; +T_7.88 ; +T_7.85 ; + %jmp T_7.84; +T_7.83 ; + %load/vec4 v0x10bab40_0; + %load/vec4 v0x10bb090_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %load/vec4 v0x10bb090_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10bb1d0, 4; + %assign/vec4 v0x10bb130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10bb090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10baff0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10bb090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10bb840_0, 4, 5; + %load/vec4 v0x10bb090_0; + %assign/vec4 v0x10ba570_0, 0; +T_7.95 ; +T_7.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.82; +T_7.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.82; +T_7.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.82; +T_7.82 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0x10baa60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.99, 6; + %jmp T_7.100; +T_7.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.100; +T_7.98 ; + %load/vec4 v0x10bbae0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.101, 4; + %load/vec4 v0x10b9fe0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.103, 8; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.106; +T_7.105 ; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.108; +T_7.107 ; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10ba570_0, 0; + %jmp T_7.110; +T_7.109 ; + %load/vec4 v0x10b8f10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10bbae0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10bb760_0, 4, 5; + %load/vec4 v0x10bbbc0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ba8f0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10ba570_0, 0; +T_7.111 ; +T_7.110 ; +T_7.108 ; +T_7.106 ; +T_7.103 ; +T_7.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.100; +T_7.99 ; + %load/vec4 v0x10bbae0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.113, 4; + %load/vec4 v0x10bb920_0; + %load/vec4 v0x10bbae0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x10bbae0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x10bb760_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ba810_0, 0; + %load/vec4 v0x10bbae0_0; + %assign/vec4 v0x10ba570_0, 0; +T_7.115 ; +T_7.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10baa60_0, 0; + %jmp T_7.100; +T_7.100 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.3 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7; + .scope S_0x10b6be0; +T_8 ; + %wait E_0xffe3d0; + %load/vec4 v0x10baa60_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10ba810_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x10b7770_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x10b7770_0; + %assign/vec4 v0x10b7690_0, 0; +T_8.0 ; + %load/vec4 v0x10baa60_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_8.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10baff0_0, 0, 4; +T_8.2 ; + %jmp T_8; + .thread T_8; + .scope S_0x10a7600; +T_9 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10ab210_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10ab430_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10aaf70_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10a7b80_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10a7c80_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a80c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ab9c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ac1f0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ac3b0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ac130_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ab2f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ab2f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ab2f0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10ab2f0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x10a7830, v0x10aaeb0 {0 0 0}; + %end; + .thread T_9; + .scope S_0x10a7600; +T_10 ; + %wait E_0x1020b80; + %load/vec4 v0x10ab210_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.2, 6; + %jmp T_10.3; +T_10.0 ; + %load/vec4 v0x10ab430_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.6, 6; + %jmp T_10.7; +T_10.4 ; + %load/vec4 v0x10a7f00_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_10.8, 5; + %load/vec4 v0x10a8280_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_10.10, 5; + %load/vec4 v0x10a8280_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %jmp T_10.11; +T_10.10 ; + %load/vec4 v0x10a8280_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_10.12, 5; + %load/vec4 v0x10ab510_0; + %load/vec4 v0x10a8280_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.14, 8; + %load/vec4 v0x10a8280_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a8280_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %load/vec4 v0x10a8280_0; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.15; +T_10.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %load/vec4 v0x10a8280_0; + %assign/vec4 v0x10aba60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a8280_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; + %load/vec4 v0x10a8280_0; + %assign/vec4 v0x10aaf70_0, 0; +T_10.15 ; + %jmp T_10.13; +T_10.12 ; + %load/vec4 v0x10a8280_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.16, 4; + %load/vec4 v0x10aaf70_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_10.18, 4; + %load/vec4 v0x10aaf70_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %jmp T_10.19; +T_10.18 ; + %load/vec4 v0x10ab510_0; + %load/vec4 v0x10aaf70_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.20, 8; + %load/vec4 v0x10aaf70_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10aaf70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %jmp T_10.21; +T_10.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %load/vec4 v0x10aaf70_0; + %assign/vec4 v0x10aba60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10aaf70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; +T_10.21 ; +T_10.19 ; + %jmp T_10.17; +T_10.16 ; + %load/vec4 v0x10a8280_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.22, 4; + %load/vec4 v0x10aa890_0; + %flag_set/vec4 8; + %jmp/0xz T_10.24, 8; + %load/vec4 v0x10ab510_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.27; +T_10.26 ; + %load/vec4 v0x10ab510_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.29; +T_10.28 ; + %load/vec4 v0x10ab510_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.31; +T_10.30 ; + %load/vec4 v0x10ab510_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; +T_10.32 ; +T_10.31 ; +T_10.29 ; +T_10.27 ; + %jmp T_10.25; +T_10.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %load/vec4 v0x10a8280_0; + %assign/vec4 v0x10aba60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; +T_10.25 ; +T_10.22 ; +T_10.17 ; +T_10.13 ; +T_10.11 ; +T_10.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.7; +T_10.5 ; + %load/vec4 v0x10a7f00_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_10.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_10.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_10.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_10.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_10.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_10.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_10.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_10.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_10.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_10.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_10.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_10.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_10.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_10.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_10.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_10.49, 6; + %jmp T_10.50; +T_10.34 ; + %load/vec4 v0x10a7b80_0; + %load/vec4 v0x10abb00_0; + %add; + %assign/vec4 v0x10a7b80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.35 ; + %load/vec4 v0x10a7b80_0; + %load/vec4 v0x10abb00_0; + %sub; + %assign/vec4 v0x10a7b80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.36 ; + %load/vec4 v0x10a80c0_0; + %pad/u 11; + %load/vec4 v0x10abb00_0; + %add; + %pad/u 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.37 ; + %load/vec4 v0x10abb00_0; + %assign/vec4 v0x10ac570_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.38 ; + %load/vec4 v0x10a7e20_0; + %assign/vec4 v0x10ac570_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.39 ; + %load/vec4 v0x10a7b80_0; + %load/vec4 v0x10a7e20_0; + %add; + %assign/vec4 v0x10a7b80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.40 ; + %load/vec4 v0x10a7b80_0; + %load/vec4 v0x10a7e20_0; + %sub; + %assign/vec4 v0x10a7b80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.41 ; + %load/vec4 v0x10a80c0_0; + %pad/u 11; + %load/vec4 v0x10a7e20_0; + %add; + %pad/u 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.42 ; + %load/vec4 v0x10a7c80_0; + %assign/vec4 v0x10a7b80_0, 0; + %load/vec4 v0x10a7b80_0; + %assign/vec4 v0x10a7c80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.43 ; + %load/vec4 v0x10a7b80_0; + %assign/vec4 v0x10a7c80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.44 ; + %load/vec4 v0x10a7b80_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x10a7b80_0, 0; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.45 ; + %load/vec4 v0x10a7fe0_0; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.50; +T_10.46 ; + %load/vec4 v0x10a7b80_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_10.51, 4; + %load/vec4 v0x10a7fe0_0; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.52; +T_10.51 ; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; +T_10.52 ; + %jmp T_10.50; +T_10.47 ; + %load/vec4 v0x10a7b80_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_10.53, 4; + %load/vec4 v0x10a7fe0_0; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.54; +T_10.53 ; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; +T_10.54 ; + %jmp T_10.50; +T_10.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x10a7b80_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_10.55, 5; + %load/vec4 v0x10a7fe0_0; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.56; +T_10.55 ; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; +T_10.56 ; + %jmp T_10.50; +T_10.49 ; + %load/vec4 v0x10a7b80_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_10.57, 5; + %load/vec4 v0x10a7fe0_0; + %assign/vec4 v0x10a81a0_0, 0; + %jmp T_10.58; +T_10.57 ; + %load/vec4 v0x10a80c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a81a0_0, 0; +T_10.58 ; + %jmp T_10.50; +T_10.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.7; +T_10.6 ; + %load/vec4 v0x10a7f00_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x10a7f00_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_10.59, 4; + %load/vec4 v0x10a7d60_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x10a7d60_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10aaf70_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_10.61, 9; + %load/vec4 v0x10a7d60_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_10.63, 4; + %load/vec4 v0x10ac570_0; + %assign/vec4 v0x10a7b80_0, 0; +T_10.63 ; + %jmp T_10.62; +T_10.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %load/vec4 v0x10a7d60_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.65, 4; + %load/vec4 v0x10aaf70_0; + %assign/vec4 v0x10ac490_0, 0; + %load/vec4 v0x10ac570_0; + %load/vec4 v0x10aaf70_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10aaf70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %jmp T_10.66; +T_10.65 ; + %load/vec4 v0x10a7d60_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.67, 4; + %load/vec4 v0x10a7d60_0; + %assign/vec4 v0x10ac490_0, 0; + %load/vec4 v0x10ac570_0; + %load/vec4 v0x10a7d60_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a7d60_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10a7d60_0; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.68; +T_10.67 ; + %load/vec4 v0x10aaa10_0; + %flag_set/vec4 8; + %jmp/0xz T_10.69, 8; + %load/vec4 v0x10a9940_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.72; +T_10.71 ; + %load/vec4 v0x10a9940_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.74; +T_10.73 ; + %load/vec4 v0x10a9940_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.76; +T_10.75 ; + %load/vec4 v0x10a9940_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; +T_10.77 ; +T_10.76 ; +T_10.74 ; +T_10.72 ; + %jmp T_10.70; +T_10.69 ; + %load/vec4 v0x10a7d60_0; + %assign/vec4 v0x10ac490_0, 0; +T_10.70 ; +T_10.68 ; +T_10.66 ; +T_10.62 ; +T_10.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.7; +T_10.7 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.1 ; + %load/vec4 v0x10ab430_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.81, 6; + %jmp T_10.82; +T_10.79 ; + %load/vec4 v0x10aba60_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.83, 4; + %load/vec4 v0x10aa890_0; + %flag_set/vec4 8; + %jmp/0xz T_10.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ac1f0_0, 0, 4; + %load/vec4 v0x10ab510_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.88; +T_10.87 ; + %load/vec4 v0x10ab510_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.90; +T_10.89 ; + %load/vec4 v0x10ab510_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.92; +T_10.91 ; + %load/vec4 v0x10ab510_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; +T_10.93 ; +T_10.92 ; +T_10.90 ; +T_10.88 ; +T_10.85 ; + %jmp T_10.84; +T_10.83 ; + %load/vec4 v0x10ab510_0; + %load/vec4 v0x10aba60_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %load/vec4 v0x10aba60_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10abba0, 4; + %assign/vec4 v0x10abb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10aba60_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ab9c0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10aba60_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10ac1f0_0, 4, 5; + %load/vec4 v0x10aba60_0; + %assign/vec4 v0x10aaf70_0, 0; +T_10.95 ; +T_10.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.82; +T_10.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.82; +T_10.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.82; +T_10.82 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0x10ab430_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.99, 6; + %jmp T_10.100; +T_10.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.100; +T_10.98 ; + %load/vec4 v0x10ac490_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.101, 4; + %load/vec4 v0x10aaa10_0; + %flag_set/vec4 8; + %jmp/0xz T_10.103, 8; + %load/vec4 v0x10a9940_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.106; +T_10.105 ; + %load/vec4 v0x10a9940_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.108; +T_10.107 ; + %load/vec4 v0x10a9940_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; + %jmp T_10.110; +T_10.109 ; + %load/vec4 v0x10a9940_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10ac490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10ac130_0, 4, 5; + %load/vec4 v0x10ac570_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10ab2f0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10aaf70_0, 0; +T_10.111 ; +T_10.110 ; +T_10.108 ; +T_10.106 ; +T_10.103 ; +T_10.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.100; +T_10.99 ; + %load/vec4 v0x10ac490_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.113, 4; + %load/vec4 v0x10ac2d0_0; + %load/vec4 v0x10ac490_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x10ac490_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x10ac130_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ab210_0, 0; + %load/vec4 v0x10ac490_0; + %assign/vec4 v0x10aaf70_0, 0; +T_10.115 ; +T_10.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10ab430_0, 0; + %jmp T_10.100; +T_10.100 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.3 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10; + .scope S_0x10a7600; +T_11 ; + %wait E_0xffe3d0; + %load/vec4 v0x10ab430_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10ab210_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x10a81a0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0x10a81a0_0; + %assign/vec4 v0x10a80c0_0, 0; +T_11.0 ; + %load/vec4 v0x10ab430_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_11.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10ab9c0_0, 0, 4; +T_11.2 ; + %jmp T_11; + .thread T_11; + .scope S_0xfed540; +T_12 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10a5f80_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10a61a0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x10a5ce0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x1063240_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x10a2930_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a2df0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a6730_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a7000_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a71c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a6f20_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10a6060, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10a6060, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10a6060, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x10a6060, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x103d640, v0x10a5c20 {0 0 0}; + %end; + .thread T_12; + .scope S_0xfed540; +T_13 ; + %wait E_0x1020b80; + %load/vec4 v0x10a5f80_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.2, 6; + %jmp T_13.3; +T_13.0 ; + %load/vec4 v0x10a61a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.6, 6; + %jmp T_13.7; +T_13.4 ; + %load/vec4 v0x10a2be0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_13.8, 5; + %load/vec4 v0x10a2fb0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_13.10, 5; + %load/vec4 v0x10a2fb0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %jmp T_13.11; +T_13.10 ; + %load/vec4 v0x10a2fb0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_13.12, 5; + %load/vec4 v0x10a6280_0; + %load/vec4 v0x10a2fb0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.14, 8; + %load/vec4 v0x10a2fb0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a2fb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %load/vec4 v0x10a2fb0_0; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.15; +T_13.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %load/vec4 v0x10a2fb0_0; + %assign/vec4 v0x10a67d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a2fb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a7000_0, 4, 5; + %load/vec4 v0x10a2fb0_0; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.15 ; + %jmp T_13.13; +T_13.12 ; + %load/vec4 v0x10a2fb0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.16, 4; + %load/vec4 v0x10a5ce0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_13.18, 4; + %load/vec4 v0x10a5ce0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %jmp T_13.19; +T_13.18 ; + %load/vec4 v0x10a6280_0; + %load/vec4 v0x10a5ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.20, 8; + %load/vec4 v0x10a5ce0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a5ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %jmp T_13.21; +T_13.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %load/vec4 v0x10a5ce0_0; + %assign/vec4 v0x10a67d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a5ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a7000_0, 4, 5; +T_13.21 ; +T_13.19 ; + %jmp T_13.17; +T_13.16 ; + %load/vec4 v0x10a2fb0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.22, 4; + %load/vec4 v0x10a55c0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.24, 8; + %load/vec4 v0x10a6280_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.27; +T_13.26 ; + %load/vec4 v0x10a6280_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.29; +T_13.28 ; + %load/vec4 v0x10a6280_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.31; +T_13.30 ; + %load/vec4 v0x10a6280_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.32 ; +T_13.31 ; +T_13.29 ; +T_13.27 ; + %jmp T_13.25; +T_13.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %load/vec4 v0x10a2fb0_0; + %assign/vec4 v0x10a67d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a7000_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a7000_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a7000_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a7000_0, 4, 5; +T_13.25 ; +T_13.22 ; +T_13.17 ; +T_13.13 ; +T_13.11 ; +T_13.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.7; +T_13.5 ; + %load/vec4 v0x10a2be0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_13.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_13.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_13.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_13.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_13.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_13.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_13.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_13.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_13.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_13.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_13.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_13.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_13.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_13.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_13.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_13.49, 6; + %jmp T_13.50; +T_13.34 ; + %load/vec4 v0x1063240_0; + %load/vec4 v0x10a68b0_0; + %add; + %assign/vec4 v0x1063240_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.35 ; + %load/vec4 v0x1063240_0; + %load/vec4 v0x10a68b0_0; + %sub; + %assign/vec4 v0x1063240_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.36 ; + %load/vec4 v0x10a2df0_0; + %pad/u 11; + %load/vec4 v0x10a68b0_0; + %add; + %pad/u 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.37 ; + %load/vec4 v0x10a68b0_0; + %assign/vec4 v0x10a7380_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.38 ; + %load/vec4 v0x10a2b00_0; + %assign/vec4 v0x10a7380_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.39 ; + %load/vec4 v0x1063240_0; + %load/vec4 v0x10a2b00_0; + %add; + %assign/vec4 v0x1063240_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.40 ; + %load/vec4 v0x1063240_0; + %load/vec4 v0x10a2b00_0; + %sub; + %assign/vec4 v0x1063240_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.41 ; + %load/vec4 v0x10a2df0_0; + %pad/u 11; + %load/vec4 v0x10a2b00_0; + %add; + %pad/u 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.42 ; + %load/vec4 v0x10a2930_0; + %assign/vec4 v0x1063240_0, 0; + %load/vec4 v0x1063240_0; + %assign/vec4 v0x10a2930_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.43 ; + %load/vec4 v0x1063240_0; + %assign/vec4 v0x10a2930_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.44 ; + %load/vec4 v0x1063240_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x1063240_0, 0; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.45 ; + %load/vec4 v0x10a2d10_0; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.50; +T_13.46 ; + %load/vec4 v0x1063240_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_13.51, 4; + %load/vec4 v0x10a2d10_0; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.52; +T_13.51 ; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; +T_13.52 ; + %jmp T_13.50; +T_13.47 ; + %load/vec4 v0x1063240_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_13.53, 4; + %load/vec4 v0x10a2d10_0; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.54; +T_13.53 ; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; +T_13.54 ; + %jmp T_13.50; +T_13.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x1063240_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_13.55, 5; + %load/vec4 v0x10a2d10_0; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.56; +T_13.55 ; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; +T_13.56 ; + %jmp T_13.50; +T_13.49 ; + %load/vec4 v0x1063240_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_13.57, 5; + %load/vec4 v0x10a2d10_0; + %assign/vec4 v0x10a2ed0_0, 0; + %jmp T_13.58; +T_13.57 ; + %load/vec4 v0x10a2df0_0; + %addi 1, 0, 4; + %assign/vec4 v0x10a2ed0_0, 0; +T_13.58 ; + %jmp T_13.50; +T_13.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.7; +T_13.6 ; + %load/vec4 v0x10a2be0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x10a2be0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_13.59, 4; + %load/vec4 v0x10a2a10_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x10a2a10_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10a5ce0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_13.61, 9; + %load/vec4 v0x10a2a10_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_13.63, 4; + %load/vec4 v0x10a7380_0; + %assign/vec4 v0x1063240_0, 0; +T_13.63 ; + %jmp T_13.62; +T_13.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %load/vec4 v0x10a2a10_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.65, 4; + %load/vec4 v0x10a5ce0_0; + %assign/vec4 v0x10a72a0_0, 0; + %load/vec4 v0x10a7380_0; + %load/vec4 v0x10a5ce0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a5ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %jmp T_13.66; +T_13.65 ; + %load/vec4 v0x10a2a10_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.67, 4; + %load/vec4 v0x10a2a10_0; + %assign/vec4 v0x10a72a0_0, 0; + %load/vec4 v0x10a7380_0; + %load/vec4 v0x10a2a10_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a2a10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a2a10_0; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.68; +T_13.67 ; + %load/vec4 v0x10a5740_0; + %flag_set/vec4 8; + %jmp/0xz T_13.69, 8; + %load/vec4 v0x10a4670_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.72; +T_13.71 ; + %load/vec4 v0x10a4670_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.74; +T_13.73 ; + %load/vec4 v0x10a4670_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.76; +T_13.75 ; + %load/vec4 v0x10a4670_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.77 ; +T_13.76 ; +T_13.74 ; +T_13.72 ; + %jmp T_13.70; +T_13.69 ; + %load/vec4 v0x10a2a10_0; + %assign/vec4 v0x10a72a0_0, 0; +T_13.70 ; +T_13.68 ; +T_13.66 ; +T_13.62 ; +T_13.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.7; +T_13.7 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.1 ; + %load/vec4 v0x10a61a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.81, 6; + %jmp T_13.82; +T_13.79 ; + %load/vec4 v0x10a67d0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.83, 4; + %load/vec4 v0x10a55c0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a7000_0, 0, 4; + %load/vec4 v0x10a6280_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.88; +T_13.87 ; + %load/vec4 v0x10a6280_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.90; +T_13.89 ; + %load/vec4 v0x10a6280_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.92; +T_13.91 ; + %load/vec4 v0x10a6280_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.93 ; +T_13.92 ; +T_13.90 ; +T_13.88 ; +T_13.85 ; + %jmp T_13.84; +T_13.83 ; + %load/vec4 v0x10a6280_0; + %load/vec4 v0x10a67d0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %load/vec4 v0x10a67d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x10a6990, 4; + %assign/vec4 v0x10a68b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a67d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a6730_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x10a67d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x10a7000_0, 4, 5; + %load/vec4 v0x10a67d0_0; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.95 ; +T_13.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.82; +T_13.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.82; +T_13.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.82; +T_13.82 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x10a61a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.99, 6; + %jmp T_13.100; +T_13.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.100; +T_13.98 ; + %load/vec4 v0x10a72a0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.101, 4; + %load/vec4 v0x10a5740_0; + %flag_set/vec4 8; + %jmp/0xz T_13.103, 8; + %load/vec4 v0x10a4670_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.106; +T_13.105 ; + %load/vec4 v0x10a4670_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.108; +T_13.107 ; + %load/vec4 v0x10a4670_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; + %jmp T_13.110; +T_13.109 ; + %load/vec4 v0x10a4670_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10a72a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x10a6f20_0, 4, 5; + %load/vec4 v0x10a7380_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x10a6060, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.111 ; +T_13.110 ; +T_13.108 ; +T_13.106 ; +T_13.103 ; +T_13.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.100; +T_13.99 ; + %load/vec4 v0x10a72a0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.113, 4; + %load/vec4 v0x10a70e0_0; + %load/vec4 v0x10a72a0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x10a72a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x10a6f20_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10a5f80_0, 0; + %load/vec4 v0x10a72a0_0; + %assign/vec4 v0x10a5ce0_0, 0; +T_13.115 ; +T_13.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x10a61a0_0, 0; + %jmp T_13.100; +T_13.100 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.3 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13; + .scope S_0xfed540; +T_14 ; + %wait E_0xffe3d0; + %load/vec4 v0x10a61a0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x10a5f80_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x10a2ed0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %load/vec4 v0x10a2ed0_0; + %assign/vec4 v0x10a2df0_0, 0; +T_14.0 ; + %load/vec4 v0x10a61a0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_14.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x10a6730_0, 0, 4; +T_14.2 ; + %jmp T_14; + .thread T_14; + .scope S_0x10151e0; +T_15 ; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x10bcc20_0, 0, 33; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x10bcb80_0, 0, 1; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x10bcc20_0, 0, 33; +T_15.0 ; + %load/vec4 v0x10bcc20_0; + %cmpi/u 10, 0, 33; + %jmp/0xz T_15.1, 5; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcae0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x10bcae0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcae0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x10bcae0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcae0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x10bcae0_0, 0, 1; + %delay 1, 0; + %load/vec4 v0x10bcc20_0; + %addi 1, 0, 33; + %store/vec4 v0x10bcc20_0, 0, 33; + %jmp T_15.0; +T_15.1 ; + %load/vec4 v0x10bca40_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.2, 4; + %vpi_call 2 51 "$display", "Failed on up test of anyWrite" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcb80_0, 0, 1; +T_15.2 ; + %load/vec4 v0x10bc900_0; + %pad/s 32; + %cmpi/ne 2, 0, 32; + %jmp/0xz T_15.4, 4; + %vpi_call 2 55 "$display", "Failed on left test of anyWrite" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcb80_0, 0, 1; +T_15.4 ; + %load/vec4 v0x10bc9a0_0; + %pad/s 32; + %cmpi/ne 3, 0, 32; + %jmp/0xz T_15.6, 4; + %vpi_call 2 59 "$display", "Failed on right test of anyWrite" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcb80_0, 0, 1; +T_15.6 ; + %load/vec4 v0x10bc860_0; + %pad/s 32; + %cmpi/ne 4, 0, 32; + %jmp/0xz T_15.8, 4; + %vpi_call 2 63 "$display", "Failed on down test of anyWrite" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcb80_0, 0, 1; +T_15.8 ; + %load/vec4 v0x10bc710_0; + %pad/s 32; + %cmpi/ne 5, 0, 32; + %jmp/0xz T_15.10, 4; + %vpi_call 2 67 "$display", "Failed on center test of anyWrite" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x10bcb80_0, 0, 1; +T_15.10 ; + %load/vec4 v0x10bcb80_0; + %flag_set/vec4 8; + %jmp/0xz T_15.12, 8; + %vpi_call 2 71 "$display", "DUT passed anyWrite" {0 0 0}; +T_15.12 ; + %end; + .thread T_15; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "anyWrite/test.v"; + "./tis100.v"; diff --git a/anyWrite/test.asm b/anyWrite/test.asm new file mode 100644 index 0000000..8671828 --- /dev/null +++ b/anyWrite/test.asm @@ -0,0 +1,24 @@ +:center +MOV 1 ANY +MOV 2 ANY +MOV 3 ANY +MOV 4 ANY +MOV LAST ACC +JRO 0 + +:up +MOV DOWN ACC +JRO 0 + +:left +MOV RIGHT ACC +JRO 0 + +:right +MOV LEFT ACC +JRO 0 + +:down +MOV UP ACC +MOV 5 UP +JRO 0 diff --git a/anyWrite/test.v b/anyWrite/test.v new file mode 100644 index 0000000..8ee0b68 --- /dev/null +++ b/anyWrite/test.v @@ -0,0 +1,75 @@ +`include "tis100.v" +module tis100Test(); + +reg clk; +wire signed[10:0] accOutCenter; +wire signed[10:0] accOutUp; +wire signed[10:0] accOutDown; +wire signed[10:0] accOutLeft; +wire signed[10:0] accOutRight; + +reg[32:0] i; + +wire[14:0] L2C; +wire[14:0] C2L; + +wire[14:0] R2C; +wire[14:0] C2R; + +wire[14:0] U2C; +wire[14:0] C2U; + +wire[14:0] D2C; +wire[14:0] C2D; + +reg dutPassed; + +tis100 #("anyWrite/left.dat") left( .clk(clk), .rightOut(L2C), .right(C2L), .accOut(accOutLeft)); +tis100 #("anyWrite/right.dat") right( .clk(clk), .leftOut(R2C), .left(C2R), .accOut(accOutRight)); +tis100 #("anyWrite/up.dat") up( .clk(clk), .downOut(U2C), .down(C2U), .accOut(accOutUp)); +tis100 #("anyWrite/down.dat") down( .clk(clk), .upOut(D2C), .up(C2D), .accOut(accOutDown)); +tis100 #("anyWrite/center.dat") center(.clk(clk), + .upOut(C2U), .up(U2C), + .downOut(C2D), .down(D2C), + .leftOut(C2L), .left(L2C), + .rightOut(C2R), .right(R2C), + .accOut(accOutCenter) + ); + +initial begin + i = 0; + dutPassed = 1; + for( i = 0; i<10; i=i+1) begin + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + end + if(accOutUp != 1) begin + $display("Failed on up test of anyWrite"); + dutPassed = 0; + end + if(accOutLeft != 2) begin + $display("Failed on left test of anyWrite"); + dutPassed = 0; + end + if(accOutRight != 3) begin + $display("Failed on right test of anyWrite"); + dutPassed = 0; + end + if(accOutDown != 4) begin + $display("Failed on down test of anyWrite"); + dutPassed = 0; + end + if(accOutCenter!= 5) begin + $display("Failed on center test of anyWrite"); + dutPassed = 0; + end + if(dutPassed) begin + $display("DUT passed anyWrite"); + end +end + +endmodule diff --git a/anyWrite/up.dat b/anyWrite/up.dat new file mode 100644 index 0000000..0868014 --- /dev/null +++ b/anyWrite/up.dat @@ -0,0 +1,16 @@ +001100110100000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/assembler.py b/assembler.py new file mode 100644 index 0000000..467990d --- /dev/null +++ b/assembler.py @@ -0,0 +1,139 @@ +from bitstring import Bits +import sys + +NIL_ADDR = 0 +ACC_ADDR = 1 +#ports +LEFT_ADDR = 2 +RIGHT_ADDR= 3 +UP_ADDR = 4 +DOWN_ADDR = 5 +#pseudo ports +LAST_ADDR = 6 +ANY_ADDR = 7 + +addresses = {"NIL": NIL_ADDR, + "ACC": ACC_ADDR, + "LEFT": LEFT_ADDR, + "RIGHT": RIGHT_ADDR, + "UP": UP_ADDR, + "DOWN": DOWN_ADDR, + "LAST": LAST_ADDR, + "ANY": ANY_ADDR} + +registers = ["NIL", "ACC", "LEFT", "RIGHT", "UP", "DOWN", "LAST", "ANY"]; + +ADDR_SIZE = 3 +INST_SIZE = 18 +PC_SIZE = 4 + +instructions = {"ADD" :0, + "SUB" :1, + "JRO" :2, + "MOV" :3, + "MOVI" :4, + "ADDI" :5, + "SUBI" :6, + "JROI" :7, + "SWP" :8, + "SAV" :9, + "NEG" :10, + "JMP" :11, + "JEZ" :12, + "JNZ" :13, + "JGZ" :14, + "JLZ" :15} + +srcLsit = ["ADD", "SUB", "JRO"] +immList = ["ADDI", "SUBI", "JROI"] + +srcDst = ["MOV"] +immDst = ["MOVI"] +labelList = ["JMP", "JEZ", "JNZ", "JGZ", "JLZ"] + +symbols = {} + +def assemble(line): + line = line.replace(',', '') + if(line.startswith("NOP")): + line = "ADD NIL" + tokens = line.split() + instruction = tokens[0]; + if(instruction in srcLsit or instruction in srcDst): + source = tokens[1] + if(source not in registers): + instruction = instruction + "I" + inst = Bits(uint=instructions[instruction],length = 4).bin + + if instruction in srcLsit: + dst = Bits(uint=0, length=3).bin + src = Bits(uint=addresses[tokens[1]],length = 3).bin + pad = Bits(uint = 0,length = 8).bin + return inst+dst+src+pad + if instruction in immList: + imm = Bits(int=int(tokens[1]), length=11).bin + dst = Bits(uint=0, length=3).bin + return inst+dst+imm + if instruction in srcDst: + src = Bits(uint=addresses[tokens[1]], length=3).bin + dst = Bits(uint=addresses[tokens[2]], length=3).bin + pad = Bits(uint = 0,length = 8).bin + return inst+dst+src+pad + if instruction in immDst: + imm = Bits(int=int(tokens[1]), length=11).bin + dst = Bits(uint=addresses[tokens[2]], length=3).bin + return inst+dst+imm + if instruction in labelList: + try: + label = Bits(uint=int(tokens[1]), length=4).bin + except: + label = Bits(uint=symbols[tokens[1]], length=4).bin + pad = Bits(uint=0, length=10).bin + return inst+label+pad + pad = Bits(uint=0, length = 14).bin; + return inst+pad + + + +if __name__ == '__main__': + infile = sys.argv[1] + prefix = infile.split("/")[0]+"/" + infile = open(infile, 'r') + lines = infile.readlines() + + fName = "" + f = None + nLines = 0; + currentLines = []; + for line in lines: + line = line.replace("\n","") + if(line.startswith(":")): + for line2 in currentLines: + f.write(assemble(line2)+"\n") + while nLines < 16 and f is not None: + f.write(assemble("JMP 0")+"\n") + nLines += 1 + fName = prefix+line[1:]+".dat" + nLines = 0 + symbols = {} + currentLines = [] + if f is not None: + f.close() + f = open(fName,'w') + elif(line == ""): + continue + else: + if(line.endswith(":")): + symbols[line[:-1]]=nLines + else: + currentLines.append(line) + nLines += 1 + + for line2 in currentLines: + f.write(assemble(line2)+"\n") + while nLines < 16: + f.write("000000000000000000\n") + nLines += 1 + + + infile.close() diff --git a/demo/demo b/demo/demo new file mode 100755 index 0000000..be2f732 --- /dev/null +++ b/demo/demo @@ -0,0 +1,11130 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x21d2520 .scope module, "stackMemory" "stackMemory" 2 11; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "in" + .port_info 2 /OUTPUT 15 "out" +P_0x230f510 .param/l "initialpointer" 0 2 15, +C4<00000000000000000000000000000000>; +P_0x230f550 .param/l "loadmemory" 0 2 13, +C4<00000000000000000000000000000000>; +P_0x230f590 .param/str "memoryfile" 0 2 14, "mem.dat"; +v0x2247fc0_0 .net *"_s2", 0 0, L_0x234a7c0; 1 drivers +v0x231a7d0_0 .net *"_s6", 0 0, L_0x234a860; 1 drivers +o0x2b7d4c4a4078 .functor BUFZ 1, C4; HiZ drive +v0x231a8b0_0 .net "clk", 0 0, o0x2b7d4c4a4078; 0 drivers +o0x2b7d4c4a40a8 .functor BUFZ 15, C4; HiZ drive +v0x231a980_0 .net "in", 14 0, o0x2b7d4c4a40a8; 0 drivers +v0x231aa60 .array "mem", 1 15, 10 0; +v0x231ab70_0 .var "out", 14 0; +v0x231ac50_0 .var "phase", 2 0; +v0x231ad30_0 .var "pointer", 3 0; +E_0x21dde80 .event negedge, v0x231a8b0_0; +E_0x220a2b0 .event posedge, v0x231a8b0_0; +E_0x2206010 .event edge, v0x231ad30_0; +E_0x21faa10 .event posedge, L_0x234a860; +E_0x2282200 .event posedge, L_0x234a7c0; +L_0x234a7c0 .part o0x2b7d4c4a40a8, 14, 1; +L_0x234a860 .part o0x2b7d4c4a40a8, 13, 1; +S_0x220a8e0 .scope module, "tis100Test" "tis100Test" 3 3; + .timescale 0 0; +v0x2349280_0 .var "clk", 0 0; +v0x2349340_0 .var "dutPassed", 0 0; +v0x2349400 .array/s "expected", 6 0, 10 0; +v0x23494d0_0 .net "fiveToFour", 14 0, L_0x236de20; 1 drivers +v0x23495e0_0 .net "fiveToSeven", 14 0, L_0x236e150; 1 drivers +v0x2349740_0 .net "fiveToTwo", 14 0, L_0x236dbd0; 1 drivers +v0x2349850_0 .net "fourToFive", 14 0, L_0x236a550; 1 drivers +v0x2349960_0 .net "fourToThree", 14 0, L_0x2369c70; 1 drivers +v0x2349a70_0 .var "i", 32 0; +v0x2349be0_0 .net "inToOne", 14 0, L_0x237a520; 1 drivers +v0x2349ca0_0 .net "oneToIn", 14 0, L_0x235d750; 1 drivers +v0x2349db0_0 .net "oneToThree", 14 0, L_0x235dc10; 1 drivers +v0x2349ec0_0 .net "outToSix", 14 0, L_0x237d8f0; 1 drivers +v0x2349fd0_0 .net "sevenToFive", 14 0, L_0x2375e00; 1 drivers +v0x234a0e0_0 .net "sevenToSix", 14 0, L_0x2376050; 1 drivers +v0x234a1f0_0 .net "sixToOut", 14 0, L_0x23721e0; 1 drivers +v0x234a300_0 .net "sixToSeven", 14 0, L_0x2372750; 1 drivers +v0x234a4b0_0 .net "threeToFour", 14 0, L_0x23663e0; 1 drivers +v0x234a5a0_0 .net "threeToOne", 14 0, L_0x23658f0; 1 drivers +v0x234a6b0_0 .net "twoToFive", 14 0, L_0x2361ce0; 1 drivers +S_0x231ae90 .scope module, "five" "tis100" 3 49, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x231b060 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x231b0a0 .param/str "memFile" 0 4 60, "demo/five.dat"; +L_0x236a8a0 .functor BUFZ 11, v0x231b450_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x236ab30 .functor BUFZ 11, v0x231b450_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x236b8f0 .functor BUFZ 18, L_0x236d960, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x231b450_0 .var/s "ACC", 10 0; +v0x231b550_0 .var/s "BAK", 10 0; +v0x231b630_0 .net "DST", 2 0, L_0x236eb50; 1 drivers +v0x231b6f0_0 .net/s "IMM", 10 0, L_0x236ebf0; 1 drivers +v0x231b7d0_0 .net "INST", 3 0, L_0x236e3f0; 1 drivers +v0x231b900_0 .net "LABEL", 3 0, L_0x236eda0; 1 drivers +v0x231b9e0_0 .var "PC", 3 0; +v0x231bac0_0 .var "PCNEXT", 3 0; +v0x231bba0_0 .net "SRC", 2 0, L_0x236e960; 1 drivers +v0x231bd10_0 .net *"_s103", 0 0, L_0x236cca0; 1 drivers +v0x231bdf0_0 .net *"_s107", 0 0, L_0x236cbb0; 1 drivers +v0x231bed0_0 .net *"_s111", 0 0, L_0x236ce90; 1 drivers +v0x231bfb0_0 .net *"_s115", 0 0, L_0x236cd90; 1 drivers +v0x231c090_0 .net *"_s119", 0 0, L_0x236d0d0; 1 drivers +v0x231c170_0 .net *"_s123", 0 0, L_0x236cfc0; 1 drivers +v0x231c250_0 .net *"_s127", 0 0, L_0x236d290; 1 drivers +v0x231c330_0 .net *"_s131", 0 0, L_0x236d170; 1 drivers +v0x231c4e0_0 .net *"_s135", 0 0, L_0x236d4f0; 1 drivers +v0x231c580_0 .net *"_s139", 0 0, L_0x236d3c0; 1 drivers +v0x231c660_0 .net *"_s143", 0 0, L_0x236d6d0; 1 drivers +v0x231c740_0 .net *"_s147", 0 0, L_0x236d590; 1 drivers +v0x231c820_0 .net *"_s151", 0 0, L_0x236d8c0; 1 drivers +v0x231c900_0 .net *"_s155", 0 0, L_0x236d770; 1 drivers +v0x231c9e0_0 .net *"_s159", 0 0, L_0x236d810; 1 drivers +v0x231cac0_0 .net *"_s160", 17 0, L_0x236d960; 1 drivers +v0x231cba0_0 .net *"_s162", 5 0, L_0x236dcc0; 1 drivers +L_0x2b7d4c4d52a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x231cc80_0 .net *"_s165", 1 0, L_0x2b7d4c4d52a0; 1 drivers +v0x231ec50_2 .array/port v0x231ec50, 2; +v0x231cd60_0 .net *"_s173", 10 0, v0x231ec50_2; 1 drivers +v0x231ec50_3 .array/port v0x231ec50, 3; +v0x231ce40_0 .net *"_s179", 10 0, v0x231ec50_3; 1 drivers +v0x231ec50_0 .array/port v0x231ec50, 0; +v0x231cf20_0 .net *"_s185", 10 0, v0x231ec50_0; 1 drivers +v0x231ec50_1 .array/port v0x231ec50, 1; +v0x231d000_0 .net *"_s191", 10 0, v0x231ec50_1; 1 drivers +v0x231d0e0_0 .net *"_s23", 0 0, L_0x236b1e0; 1 drivers +v0x231d1c0_0 .net *"_s27", 0 0, L_0x236b2b0; 1 drivers +v0x231c410_0 .net *"_s31", 0 0, L_0x236b380; 1 drivers +v0x231d490_0 .net *"_s36", 0 0, L_0x236b590; 1 drivers +v0x231d570_0 .net *"_s42", 0 0, L_0x236b7b0; 1 drivers +v0x231d650_0 .net *"_s46", 0 0, L_0x236b850; 1 drivers +v0x231d730_0 .net *"_s50", 0 0, L_0x236b960; 1 drivers +v0x231d810_0 .net *"_s55", 0 0, L_0x236bba0; 1 drivers +v0x231d8f0_0 .net *"_s61", 0 0, L_0x236be10; 1 drivers +v0x231d9d0_0 .net *"_s65", 0 0, L_0x236beb0; 1 drivers +v0x231dab0_0 .net *"_s69", 0 0, L_0x236c080; 1 drivers +v0x231db90_0 .net *"_s74", 0 0, L_0x236bfe0; 1 drivers +v0x231dc70_0 .net *"_s80", 0 0, L_0x236c260; 1 drivers +v0x231dd50_0 .net *"_s84", 0 0, L_0x236c620; 1 drivers +v0x231de30_0 .net *"_s88", 0 0, L_0x236c450; 1 drivers +v0x231df10_0 .net *"_s93", 0 0, L_0x236c6c0; 1 drivers +v0x231dff0_0 .net *"_s99", 0 0, L_0x236c990; 1 drivers +v0x231e0d0_0 .net/s "accOut", 10 0, L_0x236a8a0; 1 drivers +v0x231e1b0_0 .net "anyHasData", 0 0, L_0x236b710; 1 drivers +v0x231e270_0 .net "anyReadAck", 0 0, L_0x236c360; 1 drivers +v0x231e330_0 .net "anyWantData", 0 0, L_0x236bc90; 1 drivers +v0x231e3f0_0 .net "anyWriteAck", 0 0, L_0x236cac0; 1 drivers +v0x231e4b0_0 .net "clk", 0 0, v0x2349280_0; 1 drivers +v0x231e570_0 .net "down", 14 0, L_0x2375e00; alias, 1 drivers +v0x231e650_0 .net "downOut", 14 0, L_0x236e150; alias, 1 drivers +v0x231e730_0 .net "instruction", 17 0, L_0x236b8f0; 1 drivers +v0x231e810 .array "instructions", 15 0, 17 0; +v0x231e8d0_0 .var "last", 2 0; +v0x231e9b0_0 .net "left", 14 0, L_0x236a550; alias, 1 drivers +v0x231ea90_0 .net "leftOut", 14 0, L_0x236de20; alias, 1 drivers +v0x231eb70_0 .var "mode", 2 0; +v0x231ec50 .array/s "outVals", 2 5, 10 0; +v0x231ed90_0 .var "phase", 2 0; +v0x231ee70_0 .net "portsHaveData", 5 2, L_0x236b420; 1 drivers +v0x231d260_0 .net "portsWantData", 5 2, L_0x236ba00; 1 drivers +v0x231d340_0 .net "readAckIn", 5 2, L_0x236c120; 1 drivers +v0x231f320_0 .var "readAckOut", 5 2; +v0x231f3c0_0 .var "readTarget", 2 0; +v0x231f480_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d5258 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x231f560 .array "regVals", 0 7; +v0x231f560_0 .net/s v0x231f560 0, 10 0, L_0x2b7d4c4d5258; 1 drivers +v0x231f560_1 .net/s v0x231f560 1, 10 0, L_0x236ab30; 1 drivers +v0x231f560_2 .net/s v0x231f560 2, 10 0, L_0x236ae10; 1 drivers +v0x231f560_3 .net/s v0x231f560 3, 10 0, L_0x236af40; 1 drivers +v0x231f560_4 .net/s v0x231f560 4, 10 0, L_0x236afe0; 1 drivers +v0x231f560_5 .net/s v0x231f560 5, 10 0, L_0x236b110; 1 drivers +o0x2b7d4c4a5098 .functor BUFZ 11, C4; HiZ drive +v0x231f560_6 .net/s v0x231f560 6, 10 0, o0x2b7d4c4a5098; 0 drivers +o0x2b7d4c4a50c8 .functor BUFZ 11, C4; HiZ drive +v0x231f560_7 .net/s v0x231f560 7, 10 0, o0x2b7d4c4a50c8; 0 drivers +o0x2b7d4c4a50f8 .functor BUFZ 15, C4; HiZ drive +v0x231f770_0 .net "right", 14 0, o0x2b7d4c4a50f8; 0 drivers +v0x231f850_0 .net "rightOut", 14 0, L_0x236e780; 1 drivers +v0x231f930_0 .net "up", 14 0, L_0x2361ce0; alias, 1 drivers +v0x231fa10_0 .net "upOut", 14 0, L_0x236dbd0; alias, 1 drivers +v0x231faf0_0 .var "weHaveData", 5 2; +v0x231fbd0_0 .var "weWantData", 5 2; +v0x231fcb0_0 .net "writeAckIn", 5 2, L_0x236c8a0; 1 drivers +v0x231fd90_0 .var "writeAckOut", 5 2; +v0x231fe70_0 .var "writeTarget", 2 0; +v0x231ff50_0 .var/s "writeValue", 10 0; +E_0x231b1f0 .event negedge, v0x231e4b0_0; +E_0x231b3f0 .event posedge, v0x231e4b0_0; +L_0x236ae10 .part L_0x236a550, 0, 11; +L_0x236af40 .part o0x2b7d4c4a50f8, 0, 11; +L_0x236afe0 .part L_0x2361ce0, 0, 11; +L_0x236b110 .part L_0x2375e00, 0, 11; +L_0x236b1e0 .part L_0x236a550, 11, 1; +L_0x236b2b0 .part o0x2b7d4c4a50f8, 11, 1; +L_0x236b380 .part L_0x2361ce0, 11, 1; +L_0x236b420 .concat8 [ 1 1 1 1], L_0x236b1e0, L_0x236b2b0, L_0x236b380, L_0x236b590; +L_0x236b590 .part L_0x2375e00, 11, 1; +L_0x236b710 .reduce/or L_0x236b420; +L_0x236b7b0 .part L_0x236a550, 12, 1; +L_0x236b850 .part o0x2b7d4c4a50f8, 12, 1; +L_0x236b960 .part L_0x2361ce0, 12, 1; +L_0x236ba00 .concat8 [ 1 1 1 1], L_0x236b7b0, L_0x236b850, L_0x236b960, L_0x236bba0; +L_0x236bba0 .part L_0x2375e00, 12, 1; +L_0x236bc90 .reduce/or L_0x236ba00; +L_0x236be10 .part L_0x236a550, 13, 1; +L_0x236beb0 .part o0x2b7d4c4a50f8, 13, 1; +L_0x236c080 .part L_0x2361ce0, 13, 1; +L_0x236c120 .concat8 [ 1 1 1 1], L_0x236be10, L_0x236beb0, L_0x236c080, L_0x236bfe0; +L_0x236bfe0 .part L_0x2375e00, 13, 1; +L_0x236c360 .reduce/or L_0x236c120; +L_0x236c260 .part L_0x236a550, 14, 1; +L_0x236c620 .part o0x2b7d4c4a50f8, 14, 1; +L_0x236c450 .part L_0x2361ce0, 14, 1; +L_0x236c8a0 .concat8 [ 1 1 1 1], L_0x236c260, L_0x236c620, L_0x236c450, L_0x236c6c0; +L_0x236c6c0 .part L_0x2375e00, 14, 1; +L_0x236cac0 .reduce/or L_0x236c8a0; +L_0x236c990 .part v0x231f320_0, 0, 1; +L_0x236cca0 .part v0x231f320_0, 1, 1; +L_0x236cbb0 .part v0x231f320_0, 2, 1; +L_0x236ce90 .part v0x231f320_0, 3, 1; +L_0x236cd90 .part v0x231fd90_0, 0, 1; +L_0x236d0d0 .part v0x231fd90_0, 1, 1; +L_0x236cfc0 .part v0x231fd90_0, 2, 1; +L_0x236d290 .part v0x231fd90_0, 3, 1; +L_0x236d170 .part v0x231fbd0_0, 0, 1; +L_0x236d4f0 .part v0x231fbd0_0, 1, 1; +L_0x236d3c0 .part v0x231fbd0_0, 2, 1; +L_0x236d6d0 .part v0x231fbd0_0, 3, 1; +L_0x236d590 .part v0x231faf0_0, 0, 1; +L_0x236d8c0 .part v0x231faf0_0, 1, 1; +L_0x236d770 .part v0x231faf0_0, 2, 1; +L_0x236d810 .part v0x231faf0_0, 3, 1; +L_0x236d960 .array/port v0x231e810, L_0x236dcc0; +L_0x236dcc0 .concat [ 4 2 0 0], v0x231b9e0_0, L_0x2b7d4c4d52a0; +LS_0x236dbd0_0_0 .concat8 [ 11 1 1 1], v0x231ec50_2, L_0x236d770, L_0x236d3c0, L_0x236cfc0; +LS_0x236dbd0_0_4 .concat8 [ 1 0 0 0], L_0x236cbb0; +L_0x236dbd0 .concat8 [ 14 1 0 0], LS_0x236dbd0_0_0, LS_0x236dbd0_0_4; +LS_0x236e150_0_0 .concat8 [ 11 1 1 1], v0x231ec50_3, L_0x236d810, L_0x236d6d0, L_0x236d290; +LS_0x236e150_0_4 .concat8 [ 1 0 0 0], L_0x236ce90; +L_0x236e150 .concat8 [ 14 1 0 0], LS_0x236e150_0_0, LS_0x236e150_0_4; +LS_0x236de20_0_0 .concat8 [ 11 1 1 1], v0x231ec50_0, L_0x236d590, L_0x236d170, L_0x236cd90; +LS_0x236de20_0_4 .concat8 [ 1 0 0 0], L_0x236c990; +L_0x236de20 .concat8 [ 14 1 0 0], LS_0x236de20_0_0, LS_0x236de20_0_4; +LS_0x236e780_0_0 .concat8 [ 11 1 1 1], v0x231ec50_1, L_0x236d8c0, L_0x236d4f0, L_0x236d0d0; +LS_0x236e780_0_4 .concat8 [ 1 0 0 0], L_0x236cca0; +L_0x236e780 .concat8 [ 14 1 0 0], LS_0x236e780_0_0, LS_0x236e780_0_4; +L_0x236e3f0 .part L_0x236b8f0, 14, 4; +L_0x236eb50 .part L_0x236b8f0, 11, 3; +L_0x236e960 .part L_0x236b8f0, 8, 3; +L_0x236eda0 .part L_0x236b8f0, 10, 4; +L_0x236ebf0 .part L_0x236b8f0, 0, 11; +S_0x23201d0 .scope module, "four" "tis100" 3 45, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x23203c0 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x2320400 .param/str "memFile" 0 4 60, "demo/four.dat"; +L_0x2366730 .functor BUFZ 11, v0x23206c0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x2366930 .functor BUFZ 11, v0x23206c0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x23677d0 .functor BUFZ 18, L_0x23697b0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x23206c0_0 .var/s "ACC", 10 0; +v0x23207c0_0 .var/s "BAK", 10 0; +v0x23208a0_0 .net "DST", 2 0, L_0x236a960; 1 drivers +v0x2320960_0 .net/s "IMM", 10 0, L_0x236aa00; 1 drivers +v0x2320a40_0 .net "INST", 3 0, L_0x236a1c0; 1 drivers +v0x2320b70_0 .net "LABEL", 3 0, L_0x236abb0; 1 drivers +v0x2320c50_0 .var "PC", 3 0; +v0x2320d30_0 .var "PCNEXT", 3 0; +v0x2320e10_0 .net "SRC", 2 0, L_0x236a770; 1 drivers +v0x2320f80_0 .net *"_s103", 0 0, L_0x2368af0; 1 drivers +v0x2321060_0 .net *"_s107", 0 0, L_0x2368a00; 1 drivers +v0x2321140_0 .net *"_s111", 0 0, L_0x2368ce0; 1 drivers +v0x2321220_0 .net *"_s115", 0 0, L_0x2368be0; 1 drivers +v0x2321300_0 .net *"_s119", 0 0, L_0x2368f20; 1 drivers +v0x23213e0_0 .net *"_s123", 0 0, L_0x2368e10; 1 drivers +v0x23214c0_0 .net *"_s127", 0 0, L_0x23690e0; 1 drivers +v0x23215a0_0 .net *"_s131", 0 0, L_0x2368fc0; 1 drivers +v0x2321750_0 .net *"_s135", 0 0, L_0x2369340; 1 drivers +v0x23217f0_0 .net *"_s139", 0 0, L_0x2369210; 1 drivers +v0x23218d0_0 .net *"_s143", 0 0, L_0x2369520; 1 drivers +v0x23219b0_0 .net *"_s147", 0 0, L_0x23693e0; 1 drivers +v0x2321a90_0 .net *"_s151", 0 0, L_0x2369710; 1 drivers +v0x2321b70_0 .net *"_s155", 0 0, L_0x23695c0; 1 drivers +v0x2321c50_0 .net *"_s159", 0 0, L_0x2369660; 1 drivers +v0x2321d30_0 .net *"_s160", 17 0, L_0x23697b0; 1 drivers +v0x2321e10_0 .net *"_s162", 5 0, L_0x2369b10; 1 drivers +L_0x2b7d4c4d5210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x2321ef0_0 .net *"_s165", 1 0, L_0x2b7d4c4d5210; 1 drivers +v0x2323e80_2 .array/port v0x2323e80, 2; +v0x2321fd0_0 .net *"_s173", 10 0, v0x2323e80_2; 1 drivers +v0x2323e80_3 .array/port v0x2323e80, 3; +v0x23220b0_0 .net *"_s179", 10 0, v0x2323e80_3; 1 drivers +v0x2323e80_0 .array/port v0x2323e80, 0; +v0x2322190_0 .net *"_s185", 10 0, v0x2323e80_0; 1 drivers +v0x2323e80_1 .array/port v0x2323e80, 1; +v0x2322270_0 .net *"_s191", 10 0, v0x2323e80_1; 1 drivers +v0x2322350_0 .net *"_s23", 0 0, L_0x2366fd0; 1 drivers +v0x2322430_0 .net *"_s27", 0 0, L_0x23670a0; 1 drivers +v0x2321680_0 .net *"_s31", 0 0, L_0x2367200; 1 drivers +v0x2322700_0 .net *"_s36", 0 0, L_0x2367460; 1 drivers +v0x23227e0_0 .net *"_s42", 0 0, L_0x2367690; 1 drivers +v0x23228c0_0 .net *"_s46", 0 0, L_0x2367730; 1 drivers +v0x23229a0_0 .net *"_s50", 0 0, L_0x2367840; 1 drivers +v0x2322a80_0 .net *"_s55", 0 0, L_0x2367a50; 1 drivers +v0x2322b60_0 .net *"_s61", 0 0, L_0x2367cc0; 1 drivers +v0x2322c40_0 .net *"_s65", 0 0, L_0x2367d60; 1 drivers +v0x2322d20_0 .net *"_s69", 0 0, L_0x2367ea0; 1 drivers +v0x2322e00_0 .net *"_s74", 0 0, L_0x2367e00; 1 drivers +v0x2322ee0_0 .net *"_s80", 0 0, L_0x23680e0; 1 drivers +v0x2322fc0_0 .net *"_s84", 0 0, L_0x23684e0; 1 drivers +v0x23230a0_0 .net *"_s88", 0 0, L_0x2368310; 1 drivers +v0x2323180_0 .net *"_s93", 0 0, L_0x2368580; 1 drivers +v0x2323260_0 .net *"_s99", 0 0, L_0x23687e0; 1 drivers +v0x2323340_0 .net/s "accOut", 10 0, L_0x2366730; 1 drivers +v0x2323420_0 .net "anyHasData", 0 0, L_0x23675a0; 1 drivers +v0x23234e0_0 .net "anyReadAck", 0 0, L_0x2368270; 1 drivers +v0x23235a0_0 .net "anyWantData", 0 0, L_0x2367b40; 1 drivers +v0x2323660_0 .net "anyWriteAck", 0 0, L_0x2368910; 1 drivers +v0x2323720_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +o0x2b7d4c4a5ea8 .functor BUFZ 15, C4; HiZ drive +v0x23237c0_0 .net "down", 14 0, o0x2b7d4c4a5ea8; 0 drivers +v0x2323880_0 .net "downOut", 14 0, L_0x2369ee0; 1 drivers +v0x2323960_0 .net "instruction", 17 0, L_0x23677d0; 1 drivers +v0x2323a40 .array "instructions", 15 0, 17 0; +v0x2323b00_0 .var "last", 2 0; +v0x2323be0_0 .net "left", 14 0, L_0x23663e0; alias, 1 drivers +v0x2323cc0_0 .net "leftOut", 14 0, L_0x2369c70; alias, 1 drivers +v0x2323da0_0 .var "mode", 2 0; +v0x2323e80 .array/s "outVals", 2 5, 10 0; +v0x2323fc0_0 .var "phase", 2 0; +v0x23240a0_0 .net "portsHaveData", 5 2, L_0x23672a0; 1 drivers +v0x23224d0_0 .net "portsWantData", 5 2, L_0x23678e0; 1 drivers +v0x23225b0_0 .net "readAckIn", 5 2, L_0x2367f40; 1 drivers +v0x2324550_0 .var "readAckOut", 5 2; +v0x23245f0_0 .var "readTarget", 2 0; +v0x2324690_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d51c8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2324770 .array "regVals", 0 7; +v0x2324770_0 .net/s v0x2324770 0, 10 0, L_0x2b7d4c4d51c8; 1 drivers +v0x2324770_1 .net/s v0x2324770 1, 10 0, L_0x2366930; 1 drivers +v0x2324770_2 .net/s v0x2324770 2, 10 0, L_0x23669a0; 1 drivers +v0x2324770_3 .net/s v0x2324770 3, 10 0, L_0x2366d30; 1 drivers +v0x2324770_4 .net/s v0x2324770 4, 10 0, L_0x2366dd0; 1 drivers +v0x2324770_5 .net/s v0x2324770 5, 10 0, L_0x2366ea0; 1 drivers +o0x2b7d4c4a6328 .functor BUFZ 11, C4; HiZ drive +v0x2324770_6 .net/s v0x2324770 6, 10 0, o0x2b7d4c4a6328; 0 drivers +o0x2b7d4c4a6358 .functor BUFZ 11, C4; HiZ drive +v0x2324770_7 .net/s v0x2324770 7, 10 0, o0x2b7d4c4a6358; 0 drivers +v0x2324980_0 .net "right", 14 0, L_0x236de20; alias, 1 drivers +v0x2324a70_0 .net "rightOut", 14 0, L_0x236a550; alias, 1 drivers +o0x2b7d4c4a6388 .functor BUFZ 15, C4; HiZ drive +v0x2324b40_0 .net "up", 14 0, o0x2b7d4c4a6388; 0 drivers +v0x2324c00_0 .net "upOut", 14 0, L_0x23699f0; 1 drivers +v0x2324ce0_0 .var "weHaveData", 5 2; +v0x2324dc0_0 .var "weWantData", 5 2; +v0x2324ea0_0 .net "writeAckIn", 5 2, L_0x2368650; 1 drivers +v0x2324f80_0 .var "writeAckOut", 5 2; +v0x2325060_0 .var "writeTarget", 2 0; +v0x2325140_0 .var/s "writeValue", 10 0; +L_0x23669a0 .part L_0x23663e0, 0, 11; +L_0x2366d30 .part L_0x236de20, 0, 11; +L_0x2366dd0 .part o0x2b7d4c4a6388, 0, 11; +L_0x2366ea0 .part o0x2b7d4c4a5ea8, 0, 11; +L_0x2366fd0 .part L_0x23663e0, 11, 1; +L_0x23670a0 .part L_0x236de20, 11, 1; +L_0x2367200 .part o0x2b7d4c4a6388, 11, 1; +L_0x23672a0 .concat8 [ 1 1 1 1], L_0x2366fd0, L_0x23670a0, L_0x2367200, L_0x2367460; +L_0x2367460 .part o0x2b7d4c4a5ea8, 11, 1; +L_0x23675a0 .reduce/or L_0x23672a0; +L_0x2367690 .part L_0x23663e0, 12, 1; +L_0x2367730 .part L_0x236de20, 12, 1; +L_0x2367840 .part o0x2b7d4c4a6388, 12, 1; +L_0x23678e0 .concat8 [ 1 1 1 1], L_0x2367690, L_0x2367730, L_0x2367840, L_0x2367a50; +L_0x2367a50 .part o0x2b7d4c4a5ea8, 12, 1; +L_0x2367b40 .reduce/or L_0x23678e0; +L_0x2367cc0 .part L_0x23663e0, 13, 1; +L_0x2367d60 .part L_0x236de20, 13, 1; +L_0x2367ea0 .part o0x2b7d4c4a6388, 13, 1; +L_0x2367f40 .concat8 [ 1 1 1 1], L_0x2367cc0, L_0x2367d60, L_0x2367ea0, L_0x2367e00; +L_0x2367e00 .part o0x2b7d4c4a5ea8, 13, 1; +L_0x2368270 .reduce/or L_0x2367f40; +L_0x23680e0 .part L_0x23663e0, 14, 1; +L_0x23684e0 .part L_0x236de20, 14, 1; +L_0x2368310 .part o0x2b7d4c4a6388, 14, 1; +L_0x2368650 .concat8 [ 1 1 1 1], L_0x23680e0, L_0x23684e0, L_0x2368310, L_0x2368580; +L_0x2368580 .part o0x2b7d4c4a5ea8, 14, 1; +L_0x2368910 .reduce/or L_0x2368650; +L_0x23687e0 .part v0x2324550_0, 0, 1; +L_0x2368af0 .part v0x2324550_0, 1, 1; +L_0x2368a00 .part v0x2324550_0, 2, 1; +L_0x2368ce0 .part v0x2324550_0, 3, 1; +L_0x2368be0 .part v0x2324f80_0, 0, 1; +L_0x2368f20 .part v0x2324f80_0, 1, 1; +L_0x2368e10 .part v0x2324f80_0, 2, 1; +L_0x23690e0 .part v0x2324f80_0, 3, 1; +L_0x2368fc0 .part v0x2324dc0_0, 0, 1; +L_0x2369340 .part v0x2324dc0_0, 1, 1; +L_0x2369210 .part v0x2324dc0_0, 2, 1; +L_0x2369520 .part v0x2324dc0_0, 3, 1; +L_0x23693e0 .part v0x2324ce0_0, 0, 1; +L_0x2369710 .part v0x2324ce0_0, 1, 1; +L_0x23695c0 .part v0x2324ce0_0, 2, 1; +L_0x2369660 .part v0x2324ce0_0, 3, 1; +L_0x23697b0 .array/port v0x2323a40, L_0x2369b10; +L_0x2369b10 .concat [ 4 2 0 0], v0x2320c50_0, L_0x2b7d4c4d5210; +LS_0x23699f0_0_0 .concat8 [ 11 1 1 1], v0x2323e80_2, L_0x23695c0, L_0x2369210, L_0x2368e10; +LS_0x23699f0_0_4 .concat8 [ 1 0 0 0], L_0x2368a00; +L_0x23699f0 .concat8 [ 14 1 0 0], LS_0x23699f0_0_0, LS_0x23699f0_0_4; +LS_0x2369ee0_0_0 .concat8 [ 11 1 1 1], v0x2323e80_3, L_0x2369660, L_0x2369520, L_0x23690e0; +LS_0x2369ee0_0_4 .concat8 [ 1 0 0 0], L_0x2368ce0; +L_0x2369ee0 .concat8 [ 14 1 0 0], LS_0x2369ee0_0_0, LS_0x2369ee0_0_4; +LS_0x2369c70_0_0 .concat8 [ 11 1 1 1], v0x2323e80_0, L_0x23693e0, L_0x2368fc0, L_0x2368be0; +LS_0x2369c70_0_4 .concat8 [ 1 0 0 0], L_0x23687e0; +L_0x2369c70 .concat8 [ 14 1 0 0], LS_0x2369c70_0_0, LS_0x2369c70_0_4; +LS_0x236a550_0_0 .concat8 [ 11 1 1 1], v0x2323e80_1, L_0x2369710, L_0x2369340, L_0x2368f20; +LS_0x236a550_0_4 .concat8 [ 1 0 0 0], L_0x2368af0; +L_0x236a550 .concat8 [ 14 1 0 0], LS_0x236a550_0_0, LS_0x236a550_0_4; +L_0x236a1c0 .part L_0x23677d0, 14, 4; +L_0x236a960 .part L_0x23677d0, 11, 3; +L_0x236a770 .part L_0x23677d0, 8, 3; +L_0x236abb0 .part L_0x23677d0, 10, 4; +L_0x236aa00 .part L_0x23677d0, 0, 11; +S_0x23253c0 .scope module, "in" "tis100" 3 62, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x23255c0 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x2325600 .param/str "memFile" 0 4 60, "demo/in.dat"; +L_0x2376cc0 .functor BUFZ 11, v0x23258c0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x2376ec0 .functor BUFZ 11, v0x23258c0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x2377d40 .functor BUFZ 18, L_0x2379da0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x23258c0_0 .var/s "ACC", 10 0; +v0x23259c0_0 .var/s "BAK", 10 0; +v0x2325aa0_0 .net "DST", 2 0, L_0x237af20; 1 drivers +v0x2325b60_0 .net/s "IMM", 10 0, L_0x231f690; 1 drivers +v0x2325c40_0 .net "INST", 3 0, L_0x237a880; 1 drivers +v0x2325d70_0 .net "LABEL", 3 0, L_0x233e2e0; 1 drivers +v0x2325e50_0 .var "PC", 3 0; +v0x2325f30_0 .var "PCNEXT", 3 0; +v0x2326010_0 .net "SRC", 2 0, L_0x2329aa0; 1 drivers +v0x2326180_0 .net *"_s103", 0 0, L_0x23790e0; 1 drivers +v0x2326260_0 .net *"_s107", 0 0, L_0x2378ff0; 1 drivers +v0x2326340_0 .net *"_s111", 0 0, L_0x23792d0; 1 drivers +v0x2326420_0 .net *"_s115", 0 0, L_0x23791d0; 1 drivers +v0x2326500_0 .net *"_s119", 0 0, L_0x2379510; 1 drivers +v0x23265e0_0 .net *"_s123", 0 0, L_0x2379400; 1 drivers +v0x23266c0_0 .net *"_s127", 0 0, L_0x23796d0; 1 drivers +v0x23267a0_0 .net *"_s131", 0 0, L_0x23795b0; 1 drivers +v0x2326950_0 .net *"_s135", 0 0, L_0x2379930; 1 drivers +v0x23269f0_0 .net *"_s139", 0 0, L_0x2379800; 1 drivers +v0x2326ad0_0 .net *"_s143", 0 0, L_0x2379b10; 1 drivers +v0x2326bb0_0 .net *"_s147", 0 0, L_0x23799d0; 1 drivers +v0x2326c90_0 .net *"_s151", 0 0, L_0x2379d00; 1 drivers +v0x2326d70_0 .net *"_s155", 0 0, L_0x2379bb0; 1 drivers +v0x2326e50_0 .net *"_s159", 0 0, L_0x2379c50; 1 drivers +v0x2326f30_0 .net *"_s160", 17 0, L_0x2379da0; 1 drivers +v0x2327010_0 .net *"_s162", 5 0, L_0x237a100; 1 drivers +L_0x2b7d4c4d5450 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x23270f0_0 .net *"_s165", 1 0, L_0x2b7d4c4d5450; 1 drivers +v0x23290a0_2 .array/port v0x23290a0, 2; +v0x23271d0_0 .net *"_s173", 10 0, v0x23290a0_2; 1 drivers +v0x23290a0_3 .array/port v0x23290a0, 3; +v0x23272b0_0 .net *"_s179", 10 0, v0x23290a0_3; 1 drivers +v0x23290a0_0 .array/port v0x23290a0, 0; +v0x2327390_0 .net *"_s185", 10 0, v0x23290a0_0; 1 drivers +v0x23290a0_1 .array/port v0x23290a0, 1; +v0x2327470_0 .net *"_s191", 10 0, v0x23290a0_1; 1 drivers +v0x2327550_0 .net *"_s23", 0 0, L_0x2377560; 1 drivers +v0x2327630_0 .net *"_s27", 0 0, L_0x2377630; 1 drivers +v0x2326880_0 .net *"_s31", 0 0, L_0x2377720; 1 drivers +v0x2327900_0 .net *"_s36", 0 0, L_0x2377a20; 1 drivers +v0x23279e0_0 .net *"_s42", 0 0, L_0x2377c00; 1 drivers +v0x2327ac0_0 .net *"_s46", 0 0, L_0x2377ca0; 1 drivers +v0x2327ba0_0 .net *"_s50", 0 0, L_0x2377db0; 1 drivers +v0x2327c80_0 .net *"_s55", 0 0, L_0x2377ff0; 1 drivers +v0x2327d60_0 .net *"_s61", 0 0, L_0x2378260; 1 drivers +v0x2327e40_0 .net *"_s65", 0 0, L_0x2378390; 1 drivers +v0x2327f20_0 .net *"_s69", 0 0, L_0x2378560; 1 drivers +v0x2328000_0 .net *"_s74", 0 0, L_0x23784c0; 1 drivers +v0x23280e0_0 .net *"_s80", 0 0, L_0x2378700; 1 drivers +v0x23281c0_0 .net *"_s84", 0 0, L_0x23789b0; 1 drivers +v0x23282a0_0 .net *"_s88", 0 0, L_0x23788f0; 1 drivers +v0x2328380_0 .net *"_s93", 0 0, L_0x2378a50; 1 drivers +v0x2328460_0 .net *"_s99", 0 0, L_0x2378d10; 1 drivers +v0x2328540_0 .net/s "accOut", 10 0, L_0x2376cc0; 1 drivers +v0x2328620_0 .net "anyHasData", 0 0, L_0x2377b10; 1 drivers +v0x23286e0_0 .net "anyReadAck", 0 0, L_0x2378800; 1 drivers +v0x23287a0_0 .net "anyWantData", 0 0, L_0x23780e0; 1 drivers +v0x2328860_0 .net "anyWriteAck", 0 0, L_0x2378f50; 1 drivers +v0x2328920_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +v0x23289c0_0 .net "down", 14 0, L_0x235d750; alias, 1 drivers +v0x2328aa0_0 .net "downOut", 14 0, L_0x237a520; alias, 1 drivers +v0x2328b80_0 .net "instruction", 17 0, L_0x2377d40; 1 drivers +v0x2328c60 .array "instructions", 15 0, 17 0; +v0x2328d20_0 .var "last", 2 0; +o0x2b7d4c4a7198 .functor BUFZ 15, C4; HiZ drive +v0x2328e00_0 .net "left", 14 0, o0x2b7d4c4a7198; 0 drivers +v0x2328ee0_0 .net "leftOut", 14 0, L_0x237a260; 1 drivers +v0x2328fc0_0 .var "mode", 2 0; +v0x23290a0 .array/s "outVals", 2 5, 10 0; +v0x23291e0_0 .var "phase", 2 0; +v0x23292c0_0 .net "portsHaveData", 5 2, L_0x2377810; 1 drivers +v0x23276d0_0 .net "portsWantData", 5 2, L_0x2377e50; 1 drivers +v0x23277b0_0 .net "readAckIn", 5 2, L_0x2378600; 1 drivers +v0x2329770_0 .var "readAckOut", 5 2; +v0x2329810_0 .var "readTarget", 2 0; +v0x23298b0_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d5408 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2329970 .array "regVals", 0 7; +v0x2329970_0 .net/s v0x2329970 0, 10 0, L_0x2b7d4c4d5408; 1 drivers +v0x2329970_1 .net/s v0x2329970 1, 10 0, L_0x2376ec0; 1 drivers +v0x2329970_2 .net/s v0x2329970 2, 10 0, L_0x2376f30; 1 drivers +v0x2329970_3 .net/s v0x2329970 3, 10 0, L_0x2377230; 1 drivers +v0x2329970_4 .net/s v0x2329970 4, 10 0, L_0x23772d0; 1 drivers +v0x2329970_5 .net/s v0x2329970 5, 10 0, L_0x23773d0; 1 drivers +o0x2b7d4c4a7558 .functor BUFZ 11, C4; HiZ drive +v0x2329970_6 .net/s v0x2329970 6, 10 0, o0x2b7d4c4a7558; 0 drivers +o0x2b7d4c4a7588 .functor BUFZ 11, C4; HiZ drive +v0x2329970_7 .net/s v0x2329970 7, 10 0, o0x2b7d4c4a7588; 0 drivers +o0x2b7d4c4a75b8 .functor BUFZ 15, C4; HiZ drive +v0x2329b80_0 .net "right", 14 0, o0x2b7d4c4a75b8; 0 drivers +v0x2329c60_0 .net "rightOut", 14 0, L_0x237ab50; 1 drivers +o0x2b7d4c4a7618 .functor BUFZ 15, C4; HiZ drive +v0x2329d40_0 .net "up", 14 0, o0x2b7d4c4a7618; 0 drivers +v0x2329e20_0 .net "upOut", 14 0, L_0x237a010; 1 drivers +v0x2329f00_0 .var "weHaveData", 5 2; +v0x2329fe0_0 .var "weWantData", 5 2; +v0x232a0c0_0 .net "writeAckIn", 5 2, L_0x2378b20; 1 drivers +v0x232a1a0_0 .var "writeAckOut", 5 2; +v0x232a280_0 .var "writeTarget", 2 0; +v0x232a360_0 .var/s "writeValue", 10 0; +L_0x2376f30 .part o0x2b7d4c4a7198, 0, 11; +L_0x2377230 .part o0x2b7d4c4a75b8, 0, 11; +L_0x23772d0 .part o0x2b7d4c4a7618, 0, 11; +L_0x23773d0 .part L_0x235d750, 0, 11; +L_0x2377560 .part o0x2b7d4c4a7198, 11, 1; +L_0x2377630 .part o0x2b7d4c4a75b8, 11, 1; +L_0x2377720 .part o0x2b7d4c4a7618, 11, 1; +L_0x2377810 .concat8 [ 1 1 1 1], L_0x2377560, L_0x2377630, L_0x2377720, L_0x2377a20; +L_0x2377a20 .part L_0x235d750, 11, 1; +L_0x2377b10 .reduce/or L_0x2377810; +L_0x2377c00 .part o0x2b7d4c4a7198, 12, 1; +L_0x2377ca0 .part o0x2b7d4c4a75b8, 12, 1; +L_0x2377db0 .part o0x2b7d4c4a7618, 12, 1; +L_0x2377e50 .concat8 [ 1 1 1 1], L_0x2377c00, L_0x2377ca0, L_0x2377db0, L_0x2377ff0; +L_0x2377ff0 .part L_0x235d750, 12, 1; +L_0x23780e0 .reduce/or L_0x2377e50; +L_0x2378260 .part o0x2b7d4c4a7198, 13, 1; +L_0x2378390 .part o0x2b7d4c4a75b8, 13, 1; +L_0x2378560 .part o0x2b7d4c4a7618, 13, 1; +L_0x2378600 .concat8 [ 1 1 1 1], L_0x2378260, L_0x2378390, L_0x2378560, L_0x23784c0; +L_0x23784c0 .part L_0x235d750, 13, 1; +L_0x2378800 .reduce/or L_0x2378600; +L_0x2378700 .part o0x2b7d4c4a7198, 14, 1; +L_0x23789b0 .part o0x2b7d4c4a75b8, 14, 1; +L_0x23788f0 .part o0x2b7d4c4a7618, 14, 1; +L_0x2378b20 .concat8 [ 1 1 1 1], L_0x2378700, L_0x23789b0, L_0x23788f0, L_0x2378a50; +L_0x2378a50 .part L_0x235d750, 14, 1; +L_0x2378f50 .reduce/or L_0x2378b20; +L_0x2378d10 .part v0x2329770_0, 0, 1; +L_0x23790e0 .part v0x2329770_0, 1, 1; +L_0x2378ff0 .part v0x2329770_0, 2, 1; +L_0x23792d0 .part v0x2329770_0, 3, 1; +L_0x23791d0 .part v0x232a1a0_0, 0, 1; +L_0x2379510 .part v0x232a1a0_0, 1, 1; +L_0x2379400 .part v0x232a1a0_0, 2, 1; +L_0x23796d0 .part v0x232a1a0_0, 3, 1; +L_0x23795b0 .part v0x2329fe0_0, 0, 1; +L_0x2379930 .part v0x2329fe0_0, 1, 1; +L_0x2379800 .part v0x2329fe0_0, 2, 1; +L_0x2379b10 .part v0x2329fe0_0, 3, 1; +L_0x23799d0 .part v0x2329f00_0, 0, 1; +L_0x2379d00 .part v0x2329f00_0, 1, 1; +L_0x2379bb0 .part v0x2329f00_0, 2, 1; +L_0x2379c50 .part v0x2329f00_0, 3, 1; +L_0x2379da0 .array/port v0x2328c60, L_0x237a100; +L_0x237a100 .concat [ 4 2 0 0], v0x2325e50_0, L_0x2b7d4c4d5450; +LS_0x237a010_0_0 .concat8 [ 11 1 1 1], v0x23290a0_2, L_0x2379bb0, L_0x2379800, L_0x2379400; +LS_0x237a010_0_4 .concat8 [ 1 0 0 0], L_0x2378ff0; +L_0x237a010 .concat8 [ 14 1 0 0], LS_0x237a010_0_0, LS_0x237a010_0_4; +LS_0x237a520_0_0 .concat8 [ 11 1 1 1], v0x23290a0_3, L_0x2379c50, L_0x2379b10, L_0x23796d0; +LS_0x237a520_0_4 .concat8 [ 1 0 0 0], L_0x23792d0; +L_0x237a520 .concat8 [ 14 1 0 0], LS_0x237a520_0_0, LS_0x237a520_0_4; +LS_0x237a260_0_0 .concat8 [ 11 1 1 1], v0x23290a0_0, L_0x23799d0, L_0x23795b0, L_0x23791d0; +LS_0x237a260_0_4 .concat8 [ 1 0 0 0], L_0x2378d10; +L_0x237a260 .concat8 [ 14 1 0 0], LS_0x237a260_0_0, LS_0x237a260_0_4; +LS_0x237ab50_0_0 .concat8 [ 11 1 1 1], v0x23290a0_1, L_0x2379d00, L_0x2379930, L_0x2379510; +LS_0x237ab50_0_4 .concat8 [ 1 0 0 0], L_0x23790e0; +L_0x237ab50 .concat8 [ 14 1 0 0], LS_0x237ab50_0_0, LS_0x237ab50_0_4; +L_0x237a880 .part L_0x2377d40, 14, 4; +L_0x237af20 .part L_0x2377d40, 11, 3; +L_0x2329aa0 .part L_0x2377d40, 8, 3; +L_0x233e2e0 .part L_0x2377d40, 10, 4; +L_0x231f690 .part L_0x2377d40, 0, 11; +S_0x232a5e0 .scope module, "one" "tis100" 3 34, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x232a7b0 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x232a7f0 .param/str "memFile" 0 4 60, "demo/one.dat"; +L_0x234a950 .functor BUFZ 11, v0x232aad0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x235a9d0 .functor BUFZ 11, v0x232aad0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x235b510 .functor BUFZ 18, L_0x235d4e0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x232aad0_0 .var/s "ACC", 10 0; +v0x232abd0_0 .var/s "BAK", 10 0; +v0x232acb0_0 .net "DST", 2 0, L_0x235e5d0; 1 drivers +v0x232ad70_0 .net/s "IMM", 10 0, L_0x235e670; 1 drivers +v0x232ae50_0 .net "INST", 3 0, L_0x235deb0; 1 drivers +v0x232af80_0 .net "LABEL", 3 0, L_0x235e820; 1 drivers +v0x232b020_0 .var "PC", 3 0; +v0x232b0c0_0 .var "PCNEXT", 3 0; +v0x232b180_0 .net "SRC", 2 0, L_0x235e3e0; 1 drivers +v0x232b2f0_0 .net *"_s103", 0 0, L_0x235c820; 1 drivers +v0x232b3d0_0 .net *"_s107", 0 0, L_0x235c730; 1 drivers +v0x232b4b0_0 .net *"_s111", 0 0, L_0x235ca10; 1 drivers +v0x232b590_0 .net *"_s115", 0 0, L_0x235c910; 1 drivers +v0x232b670_0 .net *"_s119", 0 0, L_0x235cc50; 1 drivers +v0x232b750_0 .net *"_s123", 0 0, L_0x235cb40; 1 drivers +v0x232b830_0 .net *"_s127", 0 0, L_0x235ce10; 1 drivers +v0x232b910_0 .net *"_s131", 0 0, L_0x235ccf0; 1 drivers +v0x232bac0_0 .net *"_s135", 0 0, L_0x235d070; 1 drivers +v0x232bb60_0 .net *"_s139", 0 0, L_0x235cf40; 1 drivers +v0x232bc40_0 .net *"_s143", 0 0, L_0x235d250; 1 drivers +v0x232bd20_0 .net *"_s147", 0 0, L_0x235d110; 1 drivers +v0x232be00_0 .net *"_s151", 0 0, L_0x235d440; 1 drivers +v0x232bee0_0 .net *"_s155", 0 0, L_0x235d2f0; 1 drivers +v0x232bfc0_0 .net *"_s159", 0 0, L_0x235d390; 1 drivers +v0x232c0a0_0 .net *"_s160", 17 0, L_0x235d4e0; 1 drivers +v0x232c180_0 .net *"_s162", 5 0, L_0x235d840; 1 drivers +L_0x2b7d4c4d5060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x232c260_0 .net *"_s165", 1 0, L_0x2b7d4c4d5060; 1 drivers +v0x232e210_2 .array/port v0x232e210, 2; +v0x232c340_0 .net *"_s173", 10 0, v0x232e210_2; 1 drivers +v0x232e210_3 .array/port v0x232e210, 3; +v0x232c420_0 .net *"_s179", 10 0, v0x232e210_3; 1 drivers +v0x232e210_0 .array/port v0x232e210, 0; +v0x232c500_0 .net *"_s185", 10 0, v0x232e210_0; 1 drivers +v0x232e210_1 .array/port v0x232e210, 1; +v0x232c5e0_0 .net *"_s191", 10 0, v0x232e210_1; 1 drivers +v0x232c6c0_0 .net *"_s23", 0 0, L_0x235acc0; 1 drivers +v0x232c7a0_0 .net *"_s27", 0 0, L_0x235ad60; 1 drivers +v0x232b9f0_0 .net *"_s31", 0 0, L_0x235ae90; 1 drivers +v0x232ca70_0 .net *"_s36", 0 0, L_0x235b150; 1 drivers +v0x232cb50_0 .net *"_s42", 0 0, L_0x235b3d0; 1 drivers +v0x232cc30_0 .net *"_s46", 0 0, L_0x235b470; 1 drivers +v0x232cd10_0 .net *"_s50", 0 0, L_0x235b580; 1 drivers +v0x232cdf0_0 .net *"_s55", 0 0, L_0x235b7e0; 1 drivers +v0x232ced0_0 .net *"_s61", 0 0, L_0x235ba50; 1 drivers +v0x232cfb0_0 .net *"_s65", 0 0, L_0x235bb80; 1 drivers +v0x232d090_0 .net *"_s69", 0 0, L_0x235bd50; 1 drivers +v0x232d170_0 .net *"_s74", 0 0, L_0x235bcb0; 1 drivers +v0x232d250_0 .net *"_s80", 0 0, L_0x235bf30; 1 drivers +v0x232d330_0 .net *"_s84", 0 0, L_0x235c1e0; 1 drivers +v0x232d410_0 .net *"_s88", 0 0, L_0x235c120; 1 drivers +v0x232d4f0_0 .net *"_s93", 0 0, L_0x235c280; 1 drivers +v0x232d5d0_0 .net *"_s99", 0 0, L_0x235c510; 1 drivers +v0x232d6b0_0 .net/s "accOut", 10 0, L_0x234a950; 1 drivers +v0x232d790_0 .net "anyHasData", 0 0, L_0x235b2d0; 1 drivers +v0x232d850_0 .net "anyReadAck", 0 0, L_0x235c030; 1 drivers +v0x232d910_0 .net "anyWantData", 0 0, L_0x235b8d0; 1 drivers +v0x232d9d0_0 .net "anyWriteAck", 0 0, L_0x235c640; 1 drivers +v0x232da90_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +v0x232db30_0 .net "down", 14 0, L_0x23658f0; alias, 1 drivers +v0x232dc10_0 .net "downOut", 14 0, L_0x235dc10; alias, 1 drivers +v0x232dcf0_0 .net "instruction", 17 0, L_0x235b510; 1 drivers +v0x232ddd0 .array "instructions", 15 0, 17 0; +v0x232de90_0 .var "last", 2 0; +o0x2b7d4c4a8428 .functor BUFZ 15, C4; HiZ drive +v0x232df70_0 .net "left", 14 0, o0x2b7d4c4a8428; 0 drivers +v0x232e050_0 .net "leftOut", 14 0, L_0x235d9a0; 1 drivers +v0x232e130_0 .var "mode", 2 0; +v0x232e210 .array/s "outVals", 2 5, 10 0; +v0x232e380_0 .var "phase", 2 0; +v0x232e460_0 .net "portsHaveData", 5 2, L_0x235afc0; 1 drivers +v0x232c840_0 .net "portsWantData", 5 2, L_0x235b620; 1 drivers +v0x232c920_0 .net "readAckIn", 5 2, L_0x235bdf0; 1 drivers +v0x232e910_0 .var "readAckOut", 5 2; +v0x232e9b0_0 .var "readTarget", 2 0; +v0x232ea90_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d5018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x232eb70 .array "regVals", 0 7; +v0x232eb70_0 .net/s v0x232eb70 0, 10 0, L_0x2b7d4c4d5018; 1 drivers +v0x232eb70_1 .net/s v0x232eb70 1, 10 0, L_0x235a9d0; 1 drivers +v0x232eb70_2 .net/s v0x232eb70 2, 10 0, L_0x235aa40; 1 drivers +v0x232eb70_3 .net/s v0x232eb70 3, 10 0, L_0x235aae0; 1 drivers +v0x232eb70_4 .net/s v0x232eb70 4, 10 0, L_0x235ab80; 1 drivers +v0x232eb70_5 .net/s v0x232eb70 5, 10 0, L_0x235ac20; 1 drivers +o0x2b7d4c4a87e8 .functor BUFZ 11, C4; HiZ drive +v0x232eb70_6 .net/s v0x232eb70 6, 10 0, o0x2b7d4c4a87e8; 0 drivers +o0x2b7d4c4a8818 .functor BUFZ 11, C4; HiZ drive +v0x232eb70_7 .net/s v0x232eb70 7, 10 0, o0x2b7d4c4a8818; 0 drivers +o0x2b7d4c4a8848 .functor BUFZ 15, C4; HiZ drive +v0x232ed80_0 .net "right", 14 0, o0x2b7d4c4a8848; 0 drivers +v0x232ee60_0 .net "rightOut", 14 0, L_0x235e1c0; 1 drivers +v0x232ef40_0 .net "up", 14 0, L_0x237a520; alias, 1 drivers +v0x232f030_0 .net "upOut", 14 0, L_0x235d750; alias, 1 drivers +v0x232f100_0 .var "weHaveData", 5 2; +v0x232f1c0_0 .var "weWantData", 5 2; +v0x232f2a0_0 .net "writeAckIn", 5 2, L_0x235c350; 1 drivers +v0x232f380_0 .var "writeAckOut", 5 2; +v0x232f460_0 .var "writeTarget", 2 0; +v0x232f540_0 .var/s "writeValue", 10 0; +L_0x235aa40 .part o0x2b7d4c4a8428, 0, 11; +L_0x235aae0 .part o0x2b7d4c4a8848, 0, 11; +L_0x235ab80 .part L_0x237a520, 0, 11; +L_0x235ac20 .part L_0x23658f0, 0, 11; +L_0x235acc0 .part o0x2b7d4c4a8428, 11, 1; +L_0x235ad60 .part o0x2b7d4c4a8848, 11, 1; +L_0x235ae90 .part L_0x237a520, 11, 1; +L_0x235afc0 .concat8 [ 1 1 1 1], L_0x235acc0, L_0x235ad60, L_0x235ae90, L_0x235b150; +L_0x235b150 .part L_0x23658f0, 11, 1; +L_0x235b2d0 .reduce/or L_0x235afc0; +L_0x235b3d0 .part o0x2b7d4c4a8428, 12, 1; +L_0x235b470 .part o0x2b7d4c4a8848, 12, 1; +L_0x235b580 .part L_0x237a520, 12, 1; +L_0x235b620 .concat8 [ 1 1 1 1], L_0x235b3d0, L_0x235b470, L_0x235b580, L_0x235b7e0; +L_0x235b7e0 .part L_0x23658f0, 12, 1; +L_0x235b8d0 .reduce/or L_0x235b620; +L_0x235ba50 .part o0x2b7d4c4a8428, 13, 1; +L_0x235bb80 .part o0x2b7d4c4a8848, 13, 1; +L_0x235bd50 .part L_0x237a520, 13, 1; +L_0x235bdf0 .concat8 [ 1 1 1 1], L_0x235ba50, L_0x235bb80, L_0x235bd50, L_0x235bcb0; +L_0x235bcb0 .part L_0x23658f0, 13, 1; +L_0x235c030 .reduce/or L_0x235bdf0; +L_0x235bf30 .part o0x2b7d4c4a8428, 14, 1; +L_0x235c1e0 .part o0x2b7d4c4a8848, 14, 1; +L_0x235c120 .part L_0x237a520, 14, 1; +L_0x235c350 .concat8 [ 1 1 1 1], L_0x235bf30, L_0x235c1e0, L_0x235c120, L_0x235c280; +L_0x235c280 .part L_0x23658f0, 14, 1; +L_0x235c640 .reduce/or L_0x235c350; +L_0x235c510 .part v0x232e910_0, 0, 1; +L_0x235c820 .part v0x232e910_0, 1, 1; +L_0x235c730 .part v0x232e910_0, 2, 1; +L_0x235ca10 .part v0x232e910_0, 3, 1; +L_0x235c910 .part v0x232f380_0, 0, 1; +L_0x235cc50 .part v0x232f380_0, 1, 1; +L_0x235cb40 .part v0x232f380_0, 2, 1; +L_0x235ce10 .part v0x232f380_0, 3, 1; +L_0x235ccf0 .part v0x232f1c0_0, 0, 1; +L_0x235d070 .part v0x232f1c0_0, 1, 1; +L_0x235cf40 .part v0x232f1c0_0, 2, 1; +L_0x235d250 .part v0x232f1c0_0, 3, 1; +L_0x235d110 .part v0x232f100_0, 0, 1; +L_0x235d440 .part v0x232f100_0, 1, 1; +L_0x235d2f0 .part v0x232f100_0, 2, 1; +L_0x235d390 .part v0x232f100_0, 3, 1; +L_0x235d4e0 .array/port v0x232ddd0, L_0x235d840; +L_0x235d840 .concat [ 4 2 0 0], v0x232b020_0, L_0x2b7d4c4d5060; +LS_0x235d750_0_0 .concat8 [ 11 1 1 1], v0x232e210_2, L_0x235d2f0, L_0x235cf40, L_0x235cb40; +LS_0x235d750_0_4 .concat8 [ 1 0 0 0], L_0x235c730; +L_0x235d750 .concat8 [ 14 1 0 0], LS_0x235d750_0_0, LS_0x235d750_0_4; +LS_0x235dc10_0_0 .concat8 [ 11 1 1 1], v0x232e210_3, L_0x235d390, L_0x235d250, L_0x235ce10; +LS_0x235dc10_0_4 .concat8 [ 1 0 0 0], L_0x235ca10; +L_0x235dc10 .concat8 [ 14 1 0 0], LS_0x235dc10_0_0, LS_0x235dc10_0_4; +LS_0x235d9a0_0_0 .concat8 [ 11 1 1 1], v0x232e210_0, L_0x235d110, L_0x235ccf0, L_0x235c910; +LS_0x235d9a0_0_4 .concat8 [ 1 0 0 0], L_0x235c510; +L_0x235d9a0 .concat8 [ 14 1 0 0], LS_0x235d9a0_0_0, LS_0x235d9a0_0_4; +LS_0x235e1c0_0_0 .concat8 [ 11 1 1 1], v0x232e210_1, L_0x235d440, L_0x235d070, L_0x235cc50; +LS_0x235e1c0_0_4 .concat8 [ 1 0 0 0], L_0x235c820; +L_0x235e1c0 .concat8 [ 14 1 0 0], LS_0x235e1c0_0_0, LS_0x235e1c0_0_4; +L_0x235deb0 .part L_0x235b510, 14, 4; +L_0x235e5d0 .part L_0x235b510, 11, 3; +L_0x235e3e0 .part L_0x235b510, 8, 3; +L_0x235e820 .part L_0x235b510, 10, 4; +L_0x235e670 .part L_0x235b510, 0, 11; +S_0x232f7c0 .scope module, "out" "tis100" 3 63, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x232f9e0 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000001>; +P_0x232fa20 .param/str "memFile" 0 4 60, "demo/out.dat"; +L_0x2329160 .functor BUFZ 11, v0x232fce0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x23387e0 .functor BUFZ 11, v0x232fce0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x237b630 .functor BUFZ 18, L_0x237d680, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x232fce0_0 .var/s "ACC", 10 0; +v0x232fde0_0 .var/s "BAK", 10 0; +v0x232fec0_0 .net "DST", 2 0, L_0x237e7b0; 1 drivers +v0x232ff80_0 .net/s "IMM", 10 0, L_0x237e850; 1 drivers +v0x2330060_0 .net "INST", 3 0, L_0x237e110; 1 drivers +v0x2330190_0 .net "LABEL", 3 0, L_0x237ea00; 1 drivers +v0x2330270_0 .var "PC", 3 0; +v0x2330350_0 .var "PCNEXT", 3 0; +v0x2330430_0 .net "SRC", 2 0, L_0x237e5c0; 1 drivers +v0x23305a0_0 .net *"_s103", 0 0, L_0x237c9c0; 1 drivers +v0x2330680_0 .net *"_s107", 0 0, L_0x237c8d0; 1 drivers +v0x2330760_0 .net *"_s111", 0 0, L_0x237cbb0; 1 drivers +v0x2330840_0 .net *"_s115", 0 0, L_0x237cab0; 1 drivers +v0x2330920_0 .net *"_s119", 0 0, L_0x237cdf0; 1 drivers +v0x2330a00_0 .net *"_s123", 0 0, L_0x237cce0; 1 drivers +v0x2330ae0_0 .net *"_s127", 0 0, L_0x237cfb0; 1 drivers +v0x2330bc0_0 .net *"_s131", 0 0, L_0x237ce90; 1 drivers +v0x2330d70_0 .net *"_s135", 0 0, L_0x237d210; 1 drivers +v0x2330e10_0 .net *"_s139", 0 0, L_0x237d0e0; 1 drivers +v0x2330ef0_0 .net *"_s143", 0 0, L_0x237d3f0; 1 drivers +v0x2330fd0_0 .net *"_s147", 0 0, L_0x237d2b0; 1 drivers +v0x23310b0_0 .net *"_s151", 0 0, L_0x237d5e0; 1 drivers +v0x2331190_0 .net *"_s155", 0 0, L_0x237d490; 1 drivers +v0x2331270_0 .net *"_s159", 0 0, L_0x237d530; 1 drivers +v0x2331350_0 .net *"_s160", 17 0, L_0x237d680; 1 drivers +v0x2331430_0 .net *"_s162", 5 0, L_0x237d9e0; 1 drivers +L_0x2b7d4c4d54e0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x2331510_0 .net *"_s165", 1 0, L_0x2b7d4c4d54e0; 1 drivers +v0x2333550_2 .array/port v0x2333550, 2; +v0x23315f0_0 .net *"_s173", 10 0, v0x2333550_2; 1 drivers +v0x2333550_3 .array/port v0x2333550, 3; +v0x23316d0_0 .net *"_s179", 10 0, v0x2333550_3; 1 drivers +v0x2333550_0 .array/port v0x2333550, 0; +v0x23317b0_0 .net *"_s185", 10 0, v0x2333550_0; 1 drivers +v0x2333550_1 .array/port v0x2333550, 1; +v0x2331890_0 .net *"_s191", 10 0, v0x2333550_1; 1 drivers +v0x2331970_0 .net *"_s23", 0 0, L_0x2348720; 1 drivers +v0x2331a50_0 .net *"_s27", 0 0, L_0x237b180; 1 drivers +v0x2330ca0_0 .net *"_s31", 0 0, L_0x237b220; 1 drivers +v0x2331d20_0 .net *"_s36", 0 0, L_0x237b360; 1 drivers +v0x2331e00_0 .net *"_s42", 0 0, L_0x237b4f0; 1 drivers +v0x2331ee0_0 .net *"_s46", 0 0, L_0x237b590; 1 drivers +v0x2331fc0_0 .net *"_s50", 0 0, L_0x237b6a0; 1 drivers +v0x23320a0_0 .net *"_s55", 0 0, L_0x237b950; 1 drivers +v0x2332180_0 .net *"_s61", 0 0, L_0x237bbc0; 1 drivers +v0x2332260_0 .net *"_s65", 0 0, L_0x237bcf0; 1 drivers +v0x2332340_0 .net *"_s69", 0 0, L_0x237bec0; 1 drivers +v0x2332420_0 .net *"_s74", 0 0, L_0x237be20; 1 drivers +v0x2332500_0 .net *"_s80", 0 0, L_0x237c000; 1 drivers +v0x23325e0_0 .net *"_s84", 0 0, L_0x237c2f0; 1 drivers +v0x23326c0_0 .net *"_s88", 0 0, L_0x237c230; 1 drivers +v0x23327a0_0 .net *"_s93", 0 0, L_0x237c390; 1 drivers +v0x2332880_0 .net *"_s99", 0 0, L_0x237c6b0; 1 drivers +v0x2332960_0 .net/s "accOut", 10 0, L_0x2329160; 1 drivers +v0x2332a40_0 .net "anyHasData", 0 0, L_0x237b400; 1 drivers +v0x2332b00_0 .net "anyReadAck", 0 0, L_0x237c190; 1 drivers +v0x2332bc0_0 .net "anyWantData", 0 0, L_0x237ba40; 1 drivers +v0x2332c80_0 .net "anyWriteAck", 0 0, L_0x237c7e0; 1 drivers +v0x2332d40_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +o0x2b7d4c4a9598 .functor BUFZ 15, C4; HiZ drive +v0x2332e70_0 .net "down", 14 0, o0x2b7d4c4a9598; 0 drivers +v0x2332f50_0 .net "downOut", 14 0, L_0x237de70; 1 drivers +v0x2333030_0 .net "instruction", 17 0, L_0x237b630; 1 drivers +v0x2333110 .array "instructions", 15 0, 17 0; +v0x23331d0_0 .var "last", 2 0; +o0x2b7d4c4a9658 .functor BUFZ 15, C4; HiZ drive +v0x23332b0_0 .net "left", 14 0, o0x2b7d4c4a9658; 0 drivers +v0x2333390_0 .net "leftOut", 14 0, L_0x237db40; 1 drivers +v0x2333470_0 .var "mode", 2 0; +v0x2333550 .array/s "outVals", 2 5, 10 0; +v0x2333690_0 .var "phase", 2 0; +v0x2333770_0 .net "portsHaveData", 5 2, L_0x237b2c0; 1 drivers +v0x2331af0_0 .net "portsWantData", 5 2, L_0x237b740; 1 drivers +v0x2331bb0_0 .net "readAckIn", 5 2, L_0x237bf60; 1 drivers +v0x2333c20_0 .var "readAckOut", 5 2; +v0x2333cc0_0 .var "readTarget", 2 0; +v0x2333d60_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d5498 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2333e00 .array "regVals", 0 7; +v0x2333e00_0 .net/s v0x2333e00 0, 10 0, L_0x2b7d4c4d5498; 1 drivers +v0x2333e00_1 .net/s v0x2333e00 1, 10 0, L_0x23387e0; 1 drivers +v0x2333e00_2 .net/s v0x2333e00 2, 10 0, L_0x23248a0; 1 drivers +v0x2333e00_3 .net/s v0x2333e00 3, 10 0, L_0x23434d0; 1 drivers +v0x2333e00_4 .net/s v0x2333e00 4, 10 0, L_0x232eca0; 1 drivers +v0x2333e00_5 .net/s v0x2333e00 5, 10 0, L_0x2379a70; 1 drivers +o0x2b7d4c4a9a18 .functor BUFZ 11, C4; HiZ drive +v0x2333e00_6 .net/s v0x2333e00 6, 10 0, o0x2b7d4c4a9a18; 0 drivers +o0x2b7d4c4a9a48 .functor BUFZ 11, C4; HiZ drive +v0x2333e00_7 .net/s v0x2333e00 7, 10 0, o0x2b7d4c4a9a48; 0 drivers +o0x2b7d4c4a9a78 .functor BUFZ 15, C4; HiZ drive +v0x2333ff0_0 .net "right", 14 0, o0x2b7d4c4a9a78; 0 drivers +v0x23340d0_0 .net "rightOut", 14 0, L_0x237e3e0; 1 drivers +v0x23341b0_0 .net "up", 14 0, L_0x23721e0; alias, 1 drivers +v0x2334290_0 .net "upOut", 14 0, L_0x237d8f0; alias, 1 drivers +v0x2334370_0 .var "weHaveData", 5 2; +v0x2334450_0 .var "weWantData", 5 2; +v0x2334530_0 .net "writeAckIn", 5 2, L_0x237c570; 1 drivers +v0x2334610_0 .var "writeAckOut", 5 2; +v0x23346f0_0 .var "writeTarget", 2 0; +v0x23347d0_0 .var/s "writeValue", 10 0; +L_0x23248a0 .part o0x2b7d4c4a9658, 0, 11; +L_0x23434d0 .part o0x2b7d4c4a9a78, 0, 11; +L_0x232eca0 .part L_0x23721e0, 0, 11; +L_0x2379a70 .part o0x2b7d4c4a9598, 0, 11; +L_0x2348720 .part o0x2b7d4c4a9658, 11, 1; +L_0x237b180 .part o0x2b7d4c4a9a78, 11, 1; +L_0x237b220 .part L_0x23721e0, 11, 1; +L_0x237b2c0 .concat8 [ 1 1 1 1], L_0x2348720, L_0x237b180, L_0x237b220, L_0x237b360; +L_0x237b360 .part o0x2b7d4c4a9598, 11, 1; +L_0x237b400 .reduce/or L_0x237b2c0; +L_0x237b4f0 .part o0x2b7d4c4a9658, 12, 1; +L_0x237b590 .part o0x2b7d4c4a9a78, 12, 1; +L_0x237b6a0 .part L_0x23721e0, 12, 1; +L_0x237b740 .concat8 [ 1 1 1 1], L_0x237b4f0, L_0x237b590, L_0x237b6a0, L_0x237b950; +L_0x237b950 .part o0x2b7d4c4a9598, 12, 1; +L_0x237ba40 .reduce/or L_0x237b740; +L_0x237bbc0 .part o0x2b7d4c4a9658, 13, 1; +L_0x237bcf0 .part o0x2b7d4c4a9a78, 13, 1; +L_0x237bec0 .part L_0x23721e0, 13, 1; +L_0x237bf60 .concat8 [ 1 1 1 1], L_0x237bbc0, L_0x237bcf0, L_0x237bec0, L_0x237be20; +L_0x237be20 .part o0x2b7d4c4a9598, 13, 1; +L_0x237c190 .reduce/or L_0x237bf60; +L_0x237c000 .part o0x2b7d4c4a9658, 14, 1; +L_0x237c2f0 .part o0x2b7d4c4a9a78, 14, 1; +L_0x237c230 .part L_0x23721e0, 14, 1; +L_0x237c570 .concat8 [ 1 1 1 1], L_0x237c000, L_0x237c2f0, L_0x237c230, L_0x237c390; +L_0x237c390 .part o0x2b7d4c4a9598, 14, 1; +L_0x237c7e0 .reduce/or L_0x237c570; +L_0x237c6b0 .part v0x2333c20_0, 0, 1; +L_0x237c9c0 .part v0x2333c20_0, 1, 1; +L_0x237c8d0 .part v0x2333c20_0, 2, 1; +L_0x237cbb0 .part v0x2333c20_0, 3, 1; +L_0x237cab0 .part v0x2334610_0, 0, 1; +L_0x237cdf0 .part v0x2334610_0, 1, 1; +L_0x237cce0 .part v0x2334610_0, 2, 1; +L_0x237cfb0 .part v0x2334610_0, 3, 1; +L_0x237ce90 .part v0x2334450_0, 0, 1; +L_0x237d210 .part v0x2334450_0, 1, 1; +L_0x237d0e0 .part v0x2334450_0, 2, 1; +L_0x237d3f0 .part v0x2334450_0, 3, 1; +L_0x237d2b0 .part v0x2334370_0, 0, 1; +L_0x237d5e0 .part v0x2334370_0, 1, 1; +L_0x237d490 .part v0x2334370_0, 2, 1; +L_0x237d530 .part v0x2334370_0, 3, 1; +L_0x237d680 .array/port v0x2333110, L_0x237d9e0; +L_0x237d9e0 .concat [ 4 2 0 0], v0x2330270_0, L_0x2b7d4c4d54e0; +LS_0x237d8f0_0_0 .concat8 [ 11 1 1 1], v0x2333550_2, L_0x237d490, L_0x237d0e0, L_0x237cce0; +LS_0x237d8f0_0_4 .concat8 [ 1 0 0 0], L_0x237c8d0; +L_0x237d8f0 .concat8 [ 14 1 0 0], LS_0x237d8f0_0_0, LS_0x237d8f0_0_4; +LS_0x237de70_0_0 .concat8 [ 11 1 1 1], v0x2333550_3, L_0x237d530, L_0x237d3f0, L_0x237cfb0; +LS_0x237de70_0_4 .concat8 [ 1 0 0 0], L_0x237cbb0; +L_0x237de70 .concat8 [ 14 1 0 0], LS_0x237de70_0_0, LS_0x237de70_0_4; +LS_0x237db40_0_0 .concat8 [ 11 1 1 1], v0x2333550_0, L_0x237d2b0, L_0x237ce90, L_0x237cab0; +LS_0x237db40_0_4 .concat8 [ 1 0 0 0], L_0x237c6b0; +L_0x237db40 .concat8 [ 14 1 0 0], LS_0x237db40_0_0, LS_0x237db40_0_4; +LS_0x237e3e0_0_0 .concat8 [ 11 1 1 1], v0x2333550_1, L_0x237d5e0, L_0x237d210, L_0x237cdf0; +LS_0x237e3e0_0_4 .concat8 [ 1 0 0 0], L_0x237c9c0; +L_0x237e3e0 .concat8 [ 14 1 0 0], LS_0x237e3e0_0_0, LS_0x237e3e0_0_4; +L_0x237e110 .part L_0x237b630, 14, 4; +L_0x237e7b0 .part L_0x237b630, 11, 3; +L_0x237e5c0 .part L_0x237b630, 8, 3; +L_0x237ea00 .part L_0x237b630, 10, 4; +L_0x237e850 .part L_0x237b630, 0, 11; +S_0x2334a50 .scope module, "seven" "tis100" 3 58, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x2334c20 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x2334c60 .param/str "memFile" 0 4 60, "demo/seven.dat"; +L_0x2372aa0 .functor BUFZ 11, v0x2334f40_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x2372ca0 .functor BUFZ 11, v0x2334f40_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x2373b10 .functor BUFZ 18, L_0x2375b90, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x2334f40_0 .var/s "ACC", 10 0; +v0x2335040_0 .var/s "BAK", 10 0; +v0x2335120_0 .net "DST", 2 0, L_0x2376d80; 1 drivers +v0x23351e0_0 .net/s "IMM", 10 0, L_0x2376e20; 1 drivers +v0x23352c0_0 .net "INST", 3 0, L_0x2376620; 1 drivers +v0x23353f0_0 .net "LABEL", 3 0, L_0x2376fd0; 1 drivers +v0x23354d0_0 .var "PC", 3 0; +v0x23355b0_0 .var "PCNEXT", 3 0; +v0x2335690_0 .net "SRC", 2 0, L_0x2376b90; 1 drivers +v0x2335800_0 .net *"_s103", 0 0, L_0x2374ed0; 1 drivers +v0x23358e0_0 .net *"_s107", 0 0, L_0x2374de0; 1 drivers +v0x23359c0_0 .net *"_s111", 0 0, L_0x23750c0; 1 drivers +v0x2335aa0_0 .net *"_s115", 0 0, L_0x2374fc0; 1 drivers +v0x2335b80_0 .net *"_s119", 0 0, L_0x2375300; 1 drivers +v0x2335c60_0 .net *"_s123", 0 0, L_0x23751f0; 1 drivers +v0x2335d40_0 .net *"_s127", 0 0, L_0x23754c0; 1 drivers +v0x2335e20_0 .net *"_s131", 0 0, L_0x23753a0; 1 drivers +v0x2335fd0_0 .net *"_s135", 0 0, L_0x2375720; 1 drivers +v0x2336070_0 .net *"_s139", 0 0, L_0x23755f0; 1 drivers +v0x2336150_0 .net *"_s143", 0 0, L_0x2375900; 1 drivers +v0x2336230_0 .net *"_s147", 0 0, L_0x23757c0; 1 drivers +v0x2336310_0 .net *"_s151", 0 0, L_0x2375af0; 1 drivers +v0x23363f0_0 .net *"_s155", 0 0, L_0x23759a0; 1 drivers +v0x23364d0_0 .net *"_s159", 0 0, L_0x2375a40; 1 drivers +v0x23365b0_0 .net *"_s160", 17 0, L_0x2375b90; 1 drivers +v0x2336690_0 .net *"_s162", 5 0, L_0x2375ef0; 1 drivers +L_0x2b7d4c4d53c0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x2336770_0 .net *"_s165", 1 0, L_0x2b7d4c4d53c0; 1 drivers +v0x2338720_2 .array/port v0x2338720, 2; +v0x2336850_0 .net *"_s173", 10 0, v0x2338720_2; 1 drivers +v0x2338720_3 .array/port v0x2338720, 3; +v0x2336930_0 .net *"_s179", 10 0, v0x2338720_3; 1 drivers +v0x2338720_0 .array/port v0x2338720, 0; +v0x2336a10_0 .net *"_s185", 10 0, v0x2338720_0; 1 drivers +v0x2338720_1 .array/port v0x2338720, 1; +v0x2336af0_0 .net *"_s191", 10 0, v0x2338720_1; 1 drivers +v0x2336bd0_0 .net *"_s23", 0 0, L_0x23733a0; 1 drivers +v0x2336cb0_0 .net *"_s27", 0 0, L_0x2373470; 1 drivers +v0x2335f00_0 .net *"_s31", 0 0, L_0x2373540; 1 drivers +v0x2336f80_0 .net *"_s36", 0 0, L_0x23737a0; 1 drivers +v0x2337060_0 .net *"_s42", 0 0, L_0x23739d0; 1 drivers +v0x2337140_0 .net *"_s46", 0 0, L_0x2373a70; 1 drivers +v0x2337220_0 .net *"_s50", 0 0, L_0x2373b80; 1 drivers +v0x2337300_0 .net *"_s55", 0 0, L_0x2373d90; 1 drivers +v0x23373e0_0 .net *"_s61", 0 0, L_0x2374000; 1 drivers +v0x23374c0_0 .net *"_s65", 0 0, L_0x23740a0; 1 drivers +v0x23375a0_0 .net *"_s69", 0 0, L_0x2374270; 1 drivers +v0x2337680_0 .net *"_s74", 0 0, L_0x23741d0; 1 drivers +v0x2337760_0 .net *"_s80", 0 0, L_0x2374450; 1 drivers +v0x2337840_0 .net *"_s84", 0 0, L_0x2374850; 1 drivers +v0x2337920_0 .net *"_s88", 0 0, L_0x2374680; 1 drivers +v0x2337a00_0 .net *"_s93", 0 0, L_0x23748f0; 1 drivers +v0x2337ae0_0 .net *"_s99", 0 0, L_0x2374bc0; 1 drivers +v0x2337bc0_0 .net/s "accOut", 10 0, L_0x2372aa0; 1 drivers +v0x2337ca0_0 .net "anyHasData", 0 0, L_0x23738e0; 1 drivers +v0x2337d60_0 .net "anyReadAck", 0 0, L_0x23745e0; 1 drivers +v0x2337e20_0 .net "anyWantData", 0 0, L_0x2373e80; 1 drivers +v0x2337ee0_0 .net "anyWriteAck", 0 0, L_0x2374cf0; 1 drivers +v0x2337fa0_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +o0x2b7d4c4aa828 .functor BUFZ 15, C4; HiZ drive +v0x2338040_0 .net "down", 14 0, o0x2b7d4c4aa828; 0 drivers +v0x2338120_0 .net "downOut", 14 0, L_0x2376380; 1 drivers +v0x2338200_0 .net "instruction", 17 0, L_0x2373b10; 1 drivers +v0x23382e0 .array "instructions", 15 0, 17 0; +v0x23383a0_0 .var "last", 2 0; +v0x2338480_0 .net "left", 14 0, L_0x2372750; alias, 1 drivers +v0x2338560_0 .net "leftOut", 14 0, L_0x2376050; alias, 1 drivers +v0x2338640_0 .var "mode", 2 0; +v0x2338720 .array/s "outVals", 2 5, 10 0; +v0x2338860_0 .var "phase", 2 0; +v0x2338940_0 .net "portsHaveData", 5 2, L_0x23735e0; 1 drivers +v0x2336d50_0 .net "portsWantData", 5 2, L_0x2373c20; 1 drivers +v0x2336e10_0 .net "readAckIn", 5 2, L_0x2374310; 1 drivers +v0x2338df0_0 .var "readAckOut", 5 2; +v0x2338e90_0 .var "readTarget", 2 0; +v0x2338f30_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d5378 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2338ff0 .array "regVals", 0 7; +v0x2338ff0_0 .net/s v0x2338ff0 0, 10 0, L_0x2b7d4c4d5378; 1 drivers +v0x2338ff0_1 .net/s v0x2338ff0 1, 10 0, L_0x2372ca0; 1 drivers +v0x2338ff0_2 .net/s v0x2338ff0 2, 10 0, L_0x2372d10; 1 drivers +v0x2338ff0_3 .net/s v0x2338ff0 3, 10 0, L_0x23730a0; 1 drivers +v0x2338ff0_4 .net/s v0x2338ff0 4, 10 0, L_0x2373140; 1 drivers +v0x2338ff0_5 .net/s v0x2338ff0 5, 10 0, L_0x2373270; 1 drivers +o0x2b7d4c4aaca8 .functor BUFZ 11, C4; HiZ drive +v0x2338ff0_6 .net/s v0x2338ff0 6, 10 0, o0x2b7d4c4aaca8; 0 drivers +o0x2b7d4c4aacd8 .functor BUFZ 11, C4; HiZ drive +v0x2338ff0_7 .net/s v0x2338ff0 7, 10 0, o0x2b7d4c4aacd8; 0 drivers +o0x2b7d4c4aad08 .functor BUFZ 15, C4; HiZ drive +v0x2339200_0 .net "right", 14 0, o0x2b7d4c4aad08; 0 drivers +v0x23392e0_0 .net "rightOut", 14 0, L_0x23769b0; 1 drivers +v0x23393c0_0 .net "up", 14 0, L_0x236e150; alias, 1 drivers +v0x23394b0_0 .net "upOut", 14 0, L_0x2375e00; alias, 1 drivers +v0x2339580_0 .var "weHaveData", 5 2; +v0x2339640_0 .var "weWantData", 5 2; +v0x2339720_0 .net "writeAckIn", 5 2, L_0x2374ad0; 1 drivers +v0x2339800_0 .var "writeAckOut", 5 2; +v0x23398e0_0 .var "writeTarget", 2 0; +v0x23399c0_0 .var/s "writeValue", 10 0; +L_0x2372d10 .part L_0x2372750, 0, 11; +L_0x23730a0 .part o0x2b7d4c4aad08, 0, 11; +L_0x2373140 .part L_0x236e150, 0, 11; +L_0x2373270 .part o0x2b7d4c4aa828, 0, 11; +L_0x23733a0 .part L_0x2372750, 11, 1; +L_0x2373470 .part o0x2b7d4c4aad08, 11, 1; +L_0x2373540 .part L_0x236e150, 11, 1; +L_0x23735e0 .concat8 [ 1 1 1 1], L_0x23733a0, L_0x2373470, L_0x2373540, L_0x23737a0; +L_0x23737a0 .part o0x2b7d4c4aa828, 11, 1; +L_0x23738e0 .reduce/or L_0x23735e0; +L_0x23739d0 .part L_0x2372750, 12, 1; +L_0x2373a70 .part o0x2b7d4c4aad08, 12, 1; +L_0x2373b80 .part L_0x236e150, 12, 1; +L_0x2373c20 .concat8 [ 1 1 1 1], L_0x23739d0, L_0x2373a70, L_0x2373b80, L_0x2373d90; +L_0x2373d90 .part o0x2b7d4c4aa828, 12, 1; +L_0x2373e80 .reduce/or L_0x2373c20; +L_0x2374000 .part L_0x2372750, 13, 1; +L_0x23740a0 .part o0x2b7d4c4aad08, 13, 1; +L_0x2374270 .part L_0x236e150, 13, 1; +L_0x2374310 .concat8 [ 1 1 1 1], L_0x2374000, L_0x23740a0, L_0x2374270, L_0x23741d0; +L_0x23741d0 .part o0x2b7d4c4aa828, 13, 1; +L_0x23745e0 .reduce/or L_0x2374310; +L_0x2374450 .part L_0x2372750, 14, 1; +L_0x2374850 .part o0x2b7d4c4aad08, 14, 1; +L_0x2374680 .part L_0x236e150, 14, 1; +L_0x2374ad0 .concat8 [ 1 1 1 1], L_0x2374450, L_0x2374850, L_0x2374680, L_0x23748f0; +L_0x23748f0 .part o0x2b7d4c4aa828, 14, 1; +L_0x2374cf0 .reduce/or L_0x2374ad0; +L_0x2374bc0 .part v0x2338df0_0, 0, 1; +L_0x2374ed0 .part v0x2338df0_0, 1, 1; +L_0x2374de0 .part v0x2338df0_0, 2, 1; +L_0x23750c0 .part v0x2338df0_0, 3, 1; +L_0x2374fc0 .part v0x2339800_0, 0, 1; +L_0x2375300 .part v0x2339800_0, 1, 1; +L_0x23751f0 .part v0x2339800_0, 2, 1; +L_0x23754c0 .part v0x2339800_0, 3, 1; +L_0x23753a0 .part v0x2339640_0, 0, 1; +L_0x2375720 .part v0x2339640_0, 1, 1; +L_0x23755f0 .part v0x2339640_0, 2, 1; +L_0x2375900 .part v0x2339640_0, 3, 1; +L_0x23757c0 .part v0x2339580_0, 0, 1; +L_0x2375af0 .part v0x2339580_0, 1, 1; +L_0x23759a0 .part v0x2339580_0, 2, 1; +L_0x2375a40 .part v0x2339580_0, 3, 1; +L_0x2375b90 .array/port v0x23382e0, L_0x2375ef0; +L_0x2375ef0 .concat [ 4 2 0 0], v0x23354d0_0, L_0x2b7d4c4d53c0; +LS_0x2375e00_0_0 .concat8 [ 11 1 1 1], v0x2338720_2, L_0x23759a0, L_0x23755f0, L_0x23751f0; +LS_0x2375e00_0_4 .concat8 [ 1 0 0 0], L_0x2374de0; +L_0x2375e00 .concat8 [ 14 1 0 0], LS_0x2375e00_0_0, LS_0x2375e00_0_4; +LS_0x2376380_0_0 .concat8 [ 11 1 1 1], v0x2338720_3, L_0x2375a40, L_0x2375900, L_0x23754c0; +LS_0x2376380_0_4 .concat8 [ 1 0 0 0], L_0x23750c0; +L_0x2376380 .concat8 [ 14 1 0 0], LS_0x2376380_0_0, LS_0x2376380_0_4; +LS_0x2376050_0_0 .concat8 [ 11 1 1 1], v0x2338720_0, L_0x23757c0, L_0x23753a0, L_0x2374fc0; +LS_0x2376050_0_4 .concat8 [ 1 0 0 0], L_0x2374bc0; +L_0x2376050 .concat8 [ 14 1 0 0], LS_0x2376050_0_0, LS_0x2376050_0_4; +LS_0x23769b0_0_0 .concat8 [ 11 1 1 1], v0x2338720_1, L_0x2375af0, L_0x2375720, L_0x2375300; +LS_0x23769b0_0_4 .concat8 [ 1 0 0 0], L_0x2374ed0; +L_0x23769b0 .concat8 [ 14 1 0 0], LS_0x23769b0_0_0, LS_0x23769b0_0_4; +L_0x2376620 .part L_0x2373b10, 14, 4; +L_0x2376d80 .part L_0x2373b10, 11, 3; +L_0x2376b90 .part L_0x2373b10, 8, 3; +L_0x2376fd0 .part L_0x2373b10, 10, 4; +L_0x2376e20 .part L_0x2373b10, 0, 11; +S_0x2339c40 .scope module, "six" "tis100" 3 54, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x2339e10 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x2339e50 .param/str "memFile" 0 4 60, "demo/six.dat"; +L_0x236ea90 .functor BUFZ 11, v0x233a130_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x236ec90 .functor BUFZ 11, v0x233a130_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x236fb00 .functor BUFZ 18, L_0x2371a60, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x233a130_0 .var/s "ACC", 10 0; +v0x233a230_0 .var/s "BAK", 10 0; +v0x233a310_0 .net "DST", 2 0, L_0x2372b60; 1 drivers +v0x233a3d0_0 .net/s "IMM", 10 0, L_0x2372c00; 1 drivers +v0x233a4b0_0 .net "INST", 3 0, L_0x2372480; 1 drivers +v0x233a5e0_0 .net "LABEL", 3 0, L_0x2372db0; 1 drivers +v0x233a6c0_0 .var "PC", 3 0; +v0x233a7a0_0 .var "PCNEXT", 3 0; +v0x233a880_0 .net "SRC", 2 0, L_0x2372970; 1 drivers +v0x233a9f0_0 .net *"_s103", 0 0, L_0x2370da0; 1 drivers +v0x233aad0_0 .net *"_s107", 0 0, L_0x2370cb0; 1 drivers +v0x233abb0_0 .net *"_s111", 0 0, L_0x2370f90; 1 drivers +v0x233ac90_0 .net *"_s115", 0 0, L_0x2370e90; 1 drivers +v0x233ad70_0 .net *"_s119", 0 0, L_0x23711d0; 1 drivers +v0x233ae50_0 .net *"_s123", 0 0, L_0x23710c0; 1 drivers +v0x233af30_0 .net *"_s127", 0 0, L_0x2371390; 1 drivers +v0x233b010_0 .net *"_s131", 0 0, L_0x2371270; 1 drivers +v0x233b1c0_0 .net *"_s135", 0 0, L_0x23715f0; 1 drivers +v0x233b260_0 .net *"_s139", 0 0, L_0x23714c0; 1 drivers +v0x233b340_0 .net *"_s143", 0 0, L_0x23717d0; 1 drivers +v0x233b420_0 .net *"_s147", 0 0, L_0x2371690; 1 drivers +v0x233b500_0 .net *"_s151", 0 0, L_0x23719c0; 1 drivers +v0x233b5e0_0 .net *"_s155", 0 0, L_0x2371870; 1 drivers +v0x233b6c0_0 .net *"_s159", 0 0, L_0x2371910; 1 drivers +v0x233b7a0_0 .net *"_s160", 17 0, L_0x2371a60; 1 drivers +v0x233b880_0 .net *"_s162", 5 0, L_0x2371dc0; 1 drivers +L_0x2b7d4c4d5330 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x233b960_0 .net *"_s165", 1 0, L_0x2b7d4c4d5330; 1 drivers +v0x233d890_2 .array/port v0x233d890, 2; +v0x233ba40_0 .net *"_s173", 10 0, v0x233d890_2; 1 drivers +v0x233d890_3 .array/port v0x233d890, 3; +v0x233bb20_0 .net *"_s179", 10 0, v0x233d890_3; 1 drivers +v0x233d890_0 .array/port v0x233d890, 0; +v0x233bc00_0 .net *"_s185", 10 0, v0x233d890_0; 1 drivers +v0x233d890_1 .array/port v0x233d890, 1; +v0x233bce0_0 .net *"_s191", 10 0, v0x233d890_1; 1 drivers +v0x233bdc0_0 .net *"_s23", 0 0, L_0x236f2a0; 1 drivers +v0x233bea0_0 .net *"_s27", 0 0, L_0x236f3c0; 1 drivers +v0x233b0f0_0 .net *"_s31", 0 0, L_0x236f4f0; 1 drivers +v0x233c170_0 .net *"_s36", 0 0, L_0x236f7a0; 1 drivers +v0x233c250_0 .net *"_s42", 0 0, L_0x236f9c0; 1 drivers +v0x233c330_0 .net *"_s46", 0 0, L_0x236fa60; 1 drivers +v0x233c410_0 .net *"_s50", 0 0, L_0x236fb70; 1 drivers +v0x233c4f0_0 .net *"_s55", 0 0, L_0x236fdb0; 1 drivers +v0x233c5d0_0 .net *"_s61", 0 0, L_0x2370020; 1 drivers +v0x233c6b0_0 .net *"_s65", 0 0, L_0x2370150; 1 drivers +v0x233c790_0 .net *"_s69", 0 0, L_0x2370290; 1 drivers +v0x233c870_0 .net *"_s74", 0 0, L_0x23701f0; 1 drivers +v0x233c950_0 .net *"_s80", 0 0, L_0x2370480; 1 drivers +v0x233ca30_0 .net *"_s84", 0 0, L_0x2370730; 1 drivers +v0x233cb10_0 .net *"_s88", 0 0, L_0x2370670; 1 drivers +v0x233cbf0_0 .net *"_s93", 0 0, L_0x23707d0; 1 drivers +v0x233ccd0_0 .net *"_s99", 0 0, L_0x2370a90; 1 drivers +v0x233cdb0_0 .net/s "accOut", 10 0, L_0x236ea90; 1 drivers +v0x233ce90_0 .net "anyHasData", 0 0, L_0x236f920; 1 drivers +v0x233cf50_0 .net "anyReadAck", 0 0, L_0x2370580; 1 drivers +v0x233d010_0 .net "anyWantData", 0 0, L_0x236fea0; 1 drivers +v0x233d0d0_0 .net "anyWriteAck", 0 0, L_0x2370bc0; 1 drivers +v0x233d190_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +v0x233d230_0 .net "down", 14 0, L_0x237d8f0; alias, 1 drivers +v0x233d2f0_0 .net "downOut", 14 0, L_0x23721e0; alias, 1 drivers +v0x233d390_0 .net "instruction", 17 0, L_0x236fb00; 1 drivers +v0x233d450 .array "instructions", 15 0, 17 0; +v0x233d510_0 .var "last", 2 0; +o0x2b7d4c4abab8 .functor BUFZ 15, C4; HiZ drive +v0x233d5f0_0 .net "left", 14 0, o0x2b7d4c4abab8; 0 drivers +v0x233d6d0_0 .net "leftOut", 14 0, L_0x2371f20; 1 drivers +v0x233d7b0_0 .var "mode", 2 0; +v0x233d890 .array/s "outVals", 2 5, 10 0; +v0x233da00_0 .var "phase", 2 0; +v0x233dae0_0 .net "portsHaveData", 5 2, L_0x236f590; 1 drivers +v0x233bf40_0 .net "portsWantData", 5 2, L_0x236fc10; 1 drivers +v0x233c020_0 .net "readAckIn", 5 2, L_0x2370330; 1 drivers +v0x233df90_0 .var "readAckOut", 5 2; +v0x233e030_0 .var "readTarget", 2 0; +v0x233e0d0_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d52e8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x233e1b0 .array "regVals", 0 7; +v0x233e1b0_0 .net/s v0x233e1b0 0, 10 0, L_0x2b7d4c4d52e8; 1 drivers +v0x233e1b0_1 .net/s v0x233e1b0 1, 10 0, L_0x236ec90; 1 drivers +v0x233e1b0_2 .net/s v0x233e1b0 2, 10 0, L_0x236ed00; 1 drivers +v0x233e1b0_3 .net/s v0x233e1b0 3, 10 0, L_0x236f000; 1 drivers +v0x233e1b0_4 .net/s v0x233e1b0 4, 10 0, L_0x236f0a0; 1 drivers +v0x233e1b0_5 .net/s v0x233e1b0 5, 10 0, L_0x236f1a0; 1 drivers +o0x2b7d4c4abe78 .functor BUFZ 11, C4; HiZ drive +v0x233e1b0_6 .net/s v0x233e1b0 6, 10 0, o0x2b7d4c4abe78; 0 drivers +o0x2b7d4c4abea8 .functor BUFZ 11, C4; HiZ drive +v0x233e1b0_7 .net/s v0x233e1b0 7, 10 0, o0x2b7d4c4abea8; 0 drivers +v0x233e3c0_0 .net "right", 14 0, L_0x2376050; alias, 1 drivers +v0x233e4b0_0 .net "rightOut", 14 0, L_0x2372750; alias, 1 drivers +o0x2b7d4c4abed8 .functor BUFZ 15, C4; HiZ drive +v0x233e580_0 .net "up", 14 0, o0x2b7d4c4abed8; 0 drivers +v0x233e640_0 .net "upOut", 14 0, L_0x2371cd0; 1 drivers +v0x233e720_0 .var "weHaveData", 5 2; +v0x233e800_0 .var "weWantData", 5 2; +v0x233e8e0_0 .net "writeAckIn", 5 2, L_0x23708a0; 1 drivers +v0x233e9c0_0 .var "writeAckOut", 5 2; +v0x233eaa0_0 .var "writeTarget", 2 0; +v0x233eb80_0 .var/s "writeValue", 10 0; +L_0x236ed00 .part o0x2b7d4c4abab8, 0, 11; +L_0x236f000 .part L_0x2376050, 0, 11; +L_0x236f0a0 .part o0x2b7d4c4abed8, 0, 11; +L_0x236f1a0 .part L_0x237d8f0, 0, 11; +L_0x236f2a0 .part o0x2b7d4c4abab8, 11, 1; +L_0x236f3c0 .part L_0x2376050, 11, 1; +L_0x236f4f0 .part o0x2b7d4c4abed8, 11, 1; +L_0x236f590 .concat8 [ 1 1 1 1], L_0x236f2a0, L_0x236f3c0, L_0x236f4f0, L_0x236f7a0; +L_0x236f7a0 .part L_0x237d8f0, 11, 1; +L_0x236f920 .reduce/or L_0x236f590; +L_0x236f9c0 .part o0x2b7d4c4abab8, 12, 1; +L_0x236fa60 .part L_0x2376050, 12, 1; +L_0x236fb70 .part o0x2b7d4c4abed8, 12, 1; +L_0x236fc10 .concat8 [ 1 1 1 1], L_0x236f9c0, L_0x236fa60, L_0x236fb70, L_0x236fdb0; +L_0x236fdb0 .part L_0x237d8f0, 12, 1; +L_0x236fea0 .reduce/or L_0x236fc10; +L_0x2370020 .part o0x2b7d4c4abab8, 13, 1; +L_0x2370150 .part L_0x2376050, 13, 1; +L_0x2370290 .part o0x2b7d4c4abed8, 13, 1; +L_0x2370330 .concat8 [ 1 1 1 1], L_0x2370020, L_0x2370150, L_0x2370290, L_0x23701f0; +L_0x23701f0 .part L_0x237d8f0, 13, 1; +L_0x2370580 .reduce/or L_0x2370330; +L_0x2370480 .part o0x2b7d4c4abab8, 14, 1; +L_0x2370730 .part L_0x2376050, 14, 1; +L_0x2370670 .part o0x2b7d4c4abed8, 14, 1; +L_0x23708a0 .concat8 [ 1 1 1 1], L_0x2370480, L_0x2370730, L_0x2370670, L_0x23707d0; +L_0x23707d0 .part L_0x237d8f0, 14, 1; +L_0x2370bc0 .reduce/or L_0x23708a0; +L_0x2370a90 .part v0x233df90_0, 0, 1; +L_0x2370da0 .part v0x233df90_0, 1, 1; +L_0x2370cb0 .part v0x233df90_0, 2, 1; +L_0x2370f90 .part v0x233df90_0, 3, 1; +L_0x2370e90 .part v0x233e9c0_0, 0, 1; +L_0x23711d0 .part v0x233e9c0_0, 1, 1; +L_0x23710c0 .part v0x233e9c0_0, 2, 1; +L_0x2371390 .part v0x233e9c0_0, 3, 1; +L_0x2371270 .part v0x233e800_0, 0, 1; +L_0x23715f0 .part v0x233e800_0, 1, 1; +L_0x23714c0 .part v0x233e800_0, 2, 1; +L_0x23717d0 .part v0x233e800_0, 3, 1; +L_0x2371690 .part v0x233e720_0, 0, 1; +L_0x23719c0 .part v0x233e720_0, 1, 1; +L_0x2371870 .part v0x233e720_0, 2, 1; +L_0x2371910 .part v0x233e720_0, 3, 1; +L_0x2371a60 .array/port v0x233d450, L_0x2371dc0; +L_0x2371dc0 .concat [ 4 2 0 0], v0x233a6c0_0, L_0x2b7d4c4d5330; +LS_0x2371cd0_0_0 .concat8 [ 11 1 1 1], v0x233d890_2, L_0x2371870, L_0x23714c0, L_0x23710c0; +LS_0x2371cd0_0_4 .concat8 [ 1 0 0 0], L_0x2370cb0; +L_0x2371cd0 .concat8 [ 14 1 0 0], LS_0x2371cd0_0_0, LS_0x2371cd0_0_4; +LS_0x23721e0_0_0 .concat8 [ 11 1 1 1], v0x233d890_3, L_0x2371910, L_0x23717d0, L_0x2371390; +LS_0x23721e0_0_4 .concat8 [ 1 0 0 0], L_0x2370f90; +L_0x23721e0 .concat8 [ 14 1 0 0], LS_0x23721e0_0_0, LS_0x23721e0_0_4; +LS_0x2371f20_0_0 .concat8 [ 11 1 1 1], v0x233d890_0, L_0x2371690, L_0x2371270, L_0x2370e90; +LS_0x2371f20_0_4 .concat8 [ 1 0 0 0], L_0x2370a90; +L_0x2371f20 .concat8 [ 14 1 0 0], LS_0x2371f20_0_0, LS_0x2371f20_0_4; +LS_0x2372750_0_0 .concat8 [ 11 1 1 1], v0x233d890_1, L_0x23719c0, L_0x23715f0, L_0x23711d0; +LS_0x2372750_0_4 .concat8 [ 1 0 0 0], L_0x2370da0; +L_0x2372750 .concat8 [ 14 1 0 0], LS_0x2372750_0_0, LS_0x2372750_0_4; +L_0x2372480 .part L_0x236fb00, 14, 4; +L_0x2372b60 .part L_0x236fb00, 11, 3; +L_0x2372970 .part L_0x236fb00, 8, 3; +L_0x2372db0 .part L_0x236fb00, 10, 4; +L_0x2372c00 .part L_0x236fb00, 0, 11; +S_0x233ee00 .scope module, "three" "tis100" 3 41, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x233efd0 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x233f010 .param/str "memFile" 0 4 60, "demo/three.dat"; +L_0x23625e0 .functor BUFZ 11, v0x233f2f0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x23627e0 .functor BUFZ 11, v0x233f2f0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x23636c0 .functor BUFZ 18, L_0x2365680, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x233f2f0_0 .var/s "ACC", 10 0; +v0x233f3f0_0 .var/s "BAK", 10 0; +v0x233f4d0_0 .net "DST", 2 0, L_0x23667f0; 1 drivers +v0x233f590_0 .net/s "IMM", 10 0, L_0x2366890; 1 drivers +v0x233f670_0 .net "INST", 3 0, L_0x2366110; 1 drivers +v0x233f7a0_0 .net "LABEL", 3 0, L_0x2366a40; 1 drivers +v0x233f880_0 .var "PC", 3 0; +v0x233f960_0 .var "PCNEXT", 3 0; +v0x233fa40_0 .net "SRC", 2 0, L_0x2366600; 1 drivers +v0x233fbb0_0 .net *"_s103", 0 0, L_0x23649c0; 1 drivers +v0x233fc90_0 .net *"_s107", 0 0, L_0x23648d0; 1 drivers +v0x233fd70_0 .net *"_s111", 0 0, L_0x2364bb0; 1 drivers +v0x233fe50_0 .net *"_s115", 0 0, L_0x2364ab0; 1 drivers +v0x233ff30_0 .net *"_s119", 0 0, L_0x2364df0; 1 drivers +v0x2340010_0 .net *"_s123", 0 0, L_0x2364ce0; 1 drivers +v0x23400f0_0 .net *"_s127", 0 0, L_0x2364fb0; 1 drivers +v0x23401d0_0 .net *"_s131", 0 0, L_0x2364e90; 1 drivers +v0x2340380_0 .net *"_s135", 0 0, L_0x2365210; 1 drivers +v0x2340420_0 .net *"_s139", 0 0, L_0x23650e0; 1 drivers +v0x2340500_0 .net *"_s143", 0 0, L_0x23653f0; 1 drivers +v0x23405e0_0 .net *"_s147", 0 0, L_0x23652b0; 1 drivers +v0x23406c0_0 .net *"_s151", 0 0, L_0x23655e0; 1 drivers +v0x23407a0_0 .net *"_s155", 0 0, L_0x2365490; 1 drivers +v0x2340880_0 .net *"_s159", 0 0, L_0x2365530; 1 drivers +v0x2340960_0 .net *"_s160", 17 0, L_0x2365680; 1 drivers +v0x2340a40_0 .net *"_s162", 5 0, L_0x23659e0; 1 drivers +L_0x2b7d4c4d5180 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x2340b20_0 .net *"_s165", 1 0, L_0x2b7d4c4d5180; 1 drivers +v0x2342ad0_2 .array/port v0x2342ad0, 2; +v0x2340c00_0 .net *"_s173", 10 0, v0x2342ad0_2; 1 drivers +v0x2342ad0_3 .array/port v0x2342ad0, 3; +v0x2340ce0_0 .net *"_s179", 10 0, v0x2342ad0_3; 1 drivers +v0x2342ad0_0 .array/port v0x2342ad0, 0; +v0x2340dc0_0 .net *"_s185", 10 0, v0x2342ad0_0; 1 drivers +v0x2342ad0_1 .array/port v0x2342ad0, 1; +v0x2340ea0_0 .net *"_s191", 10 0, v0x2342ad0_1; 1 drivers +v0x2340f80_0 .net *"_s23", 0 0, L_0x2362ec0; 1 drivers +v0x2341060_0 .net *"_s27", 0 0, L_0x2362f90; 1 drivers +v0x23402b0_0 .net *"_s31", 0 0, L_0x23630c0; 1 drivers +v0x2341330_0 .net *"_s36", 0 0, L_0x2363350; 1 drivers +v0x2341410_0 .net *"_s42", 0 0, L_0x2363580; 1 drivers +v0x23414f0_0 .net *"_s46", 0 0, L_0x2363620; 1 drivers +v0x23415d0_0 .net *"_s50", 0 0, L_0x2363730; 1 drivers +v0x23416b0_0 .net *"_s55", 0 0, L_0x2363940; 1 drivers +v0x2341790_0 .net *"_s61", 0 0, L_0x2363bb0; 1 drivers +v0x2341870_0 .net *"_s65", 0 0, L_0x2363ce0; 1 drivers +v0x2341950_0 .net *"_s69", 0 0, L_0x2363e20; 1 drivers +v0x2341a30_0 .net *"_s74", 0 0, L_0x2363d80; 1 drivers +v0x2341b10_0 .net *"_s80", 0 0, L_0x2364000; 1 drivers +v0x2341bf0_0 .net *"_s84", 0 0, L_0x23642f0; 1 drivers +v0x2341cd0_0 .net *"_s88", 0 0, L_0x2364230; 1 drivers +v0x2341db0_0 .net *"_s93", 0 0, L_0x2364390; 1 drivers +v0x2341e90_0 .net *"_s99", 0 0, L_0x23646b0; 1 drivers +v0x2341f70_0 .net/s "accOut", 10 0, L_0x23625e0; 1 drivers +v0x2342050_0 .net "anyHasData", 0 0, L_0x2363490; 1 drivers +v0x2342110_0 .net "anyReadAck", 0 0, L_0x2364190; 1 drivers +v0x23421d0_0 .net "anyWantData", 0 0, L_0x2363a30; 1 drivers +v0x2342290_0 .net "anyWriteAck", 0 0, L_0x23647e0; 1 drivers +v0x2342350_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +o0x2b7d4c4acc28 .functor BUFZ 15, C4; HiZ drive +v0x23423f0_0 .net "down", 14 0, o0x2b7d4c4acc28; 0 drivers +v0x23424d0_0 .net "downOut", 14 0, L_0x2365e70; 1 drivers +v0x23425b0_0 .net "instruction", 17 0, L_0x23636c0; 1 drivers +v0x2342690 .array "instructions", 15 0, 17 0; +v0x2342750_0 .var "last", 2 0; +o0x2b7d4c4acce8 .functor BUFZ 15, C4; HiZ drive +v0x2342830_0 .net "left", 14 0, o0x2b7d4c4acce8; 0 drivers +v0x2342910_0 .net "leftOut", 14 0, L_0x2365b40; 1 drivers +v0x23429f0_0 .var "mode", 2 0; +v0x2342ad0 .array/s "outVals", 2 5, 10 0; +v0x2342c10_0 .var "phase", 2 0; +v0x2342cf0_0 .net "portsHaveData", 5 2, L_0x2363160; 1 drivers +v0x2341100_0 .net "portsWantData", 5 2, L_0x23637d0; 1 drivers +v0x23411c0_0 .net "readAckIn", 5 2, L_0x2363ec0; 1 drivers +v0x23431a0_0 .var "readAckOut", 5 2; +v0x2343240_0 .var "readTarget", 2 0; +v0x23432e0_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d5138 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x23433a0 .array "regVals", 0 7; +v0x23433a0_0 .net/s v0x23433a0 0, 10 0, L_0x2b7d4c4d5138; 1 drivers +v0x23433a0_1 .net/s v0x23433a0 1, 10 0, L_0x23627e0; 1 drivers +v0x23433a0_2 .net/s v0x23433a0 2, 10 0, L_0x2362b50; 1 drivers +v0x23433a0_3 .net/s v0x23433a0 3, 10 0, L_0x2362bf0; 1 drivers +v0x23433a0_4 .net/s v0x23433a0 4, 10 0, L_0x2362c90; 1 drivers +v0x23433a0_5 .net/s v0x23433a0 5, 10 0, L_0x2362dc0; 1 drivers +o0x2b7d4c4ad0a8 .functor BUFZ 11, C4; HiZ drive +v0x23433a0_6 .net/s v0x23433a0 6, 10 0, o0x2b7d4c4ad0a8; 0 drivers +o0x2b7d4c4ad0d8 .functor BUFZ 11, C4; HiZ drive +v0x23433a0_7 .net/s v0x23433a0 7, 10 0, o0x2b7d4c4ad0d8; 0 drivers +v0x23435b0_0 .net "right", 14 0, L_0x2369c70; alias, 1 drivers +v0x23436a0_0 .net "rightOut", 14 0, L_0x23663e0; alias, 1 drivers +v0x2343770_0 .net "up", 14 0, L_0x235dc10; alias, 1 drivers +v0x2343840_0 .net "upOut", 14 0, L_0x23658f0; alias, 1 drivers +v0x2343910_0 .var "weHaveData", 5 2; +v0x23439d0_0 .var "weWantData", 5 2; +v0x2343ab0_0 .net "writeAckIn", 5 2, L_0x2364570; 1 drivers +v0x2343b90_0 .var "writeAckOut", 5 2; +v0x2343c70_0 .var "writeTarget", 2 0; +v0x2343d50_0 .var/s "writeValue", 10 0; +L_0x2362b50 .part o0x2b7d4c4acce8, 0, 11; +L_0x2362bf0 .part L_0x2369c70, 0, 11; +L_0x2362c90 .part L_0x235dc10, 0, 11; +L_0x2362dc0 .part o0x2b7d4c4acc28, 0, 11; +L_0x2362ec0 .part o0x2b7d4c4acce8, 11, 1; +L_0x2362f90 .part L_0x2369c70, 11, 1; +L_0x23630c0 .part L_0x235dc10, 11, 1; +L_0x2363160 .concat8 [ 1 1 1 1], L_0x2362ec0, L_0x2362f90, L_0x23630c0, L_0x2363350; +L_0x2363350 .part o0x2b7d4c4acc28, 11, 1; +L_0x2363490 .reduce/or L_0x2363160; +L_0x2363580 .part o0x2b7d4c4acce8, 12, 1; +L_0x2363620 .part L_0x2369c70, 12, 1; +L_0x2363730 .part L_0x235dc10, 12, 1; +L_0x23637d0 .concat8 [ 1 1 1 1], L_0x2363580, L_0x2363620, L_0x2363730, L_0x2363940; +L_0x2363940 .part o0x2b7d4c4acc28, 12, 1; +L_0x2363a30 .reduce/or L_0x23637d0; +L_0x2363bb0 .part o0x2b7d4c4acce8, 13, 1; +L_0x2363ce0 .part L_0x2369c70, 13, 1; +L_0x2363e20 .part L_0x235dc10, 13, 1; +L_0x2363ec0 .concat8 [ 1 1 1 1], L_0x2363bb0, L_0x2363ce0, L_0x2363e20, L_0x2363d80; +L_0x2363d80 .part o0x2b7d4c4acc28, 13, 1; +L_0x2364190 .reduce/or L_0x2363ec0; +L_0x2364000 .part o0x2b7d4c4acce8, 14, 1; +L_0x23642f0 .part L_0x2369c70, 14, 1; +L_0x2364230 .part L_0x235dc10, 14, 1; +L_0x2364570 .concat8 [ 1 1 1 1], L_0x2364000, L_0x23642f0, L_0x2364230, L_0x2364390; +L_0x2364390 .part o0x2b7d4c4acc28, 14, 1; +L_0x23647e0 .reduce/or L_0x2364570; +L_0x23646b0 .part v0x23431a0_0, 0, 1; +L_0x23649c0 .part v0x23431a0_0, 1, 1; +L_0x23648d0 .part v0x23431a0_0, 2, 1; +L_0x2364bb0 .part v0x23431a0_0, 3, 1; +L_0x2364ab0 .part v0x2343b90_0, 0, 1; +L_0x2364df0 .part v0x2343b90_0, 1, 1; +L_0x2364ce0 .part v0x2343b90_0, 2, 1; +L_0x2364fb0 .part v0x2343b90_0, 3, 1; +L_0x2364e90 .part v0x23439d0_0, 0, 1; +L_0x2365210 .part v0x23439d0_0, 1, 1; +L_0x23650e0 .part v0x23439d0_0, 2, 1; +L_0x23653f0 .part v0x23439d0_0, 3, 1; +L_0x23652b0 .part v0x2343910_0, 0, 1; +L_0x23655e0 .part v0x2343910_0, 1, 1; +L_0x2365490 .part v0x2343910_0, 2, 1; +L_0x2365530 .part v0x2343910_0, 3, 1; +L_0x2365680 .array/port v0x2342690, L_0x23659e0; +L_0x23659e0 .concat [ 4 2 0 0], v0x233f880_0, L_0x2b7d4c4d5180; +LS_0x23658f0_0_0 .concat8 [ 11 1 1 1], v0x2342ad0_2, L_0x2365490, L_0x23650e0, L_0x2364ce0; +LS_0x23658f0_0_4 .concat8 [ 1 0 0 0], L_0x23648d0; +L_0x23658f0 .concat8 [ 14 1 0 0], LS_0x23658f0_0_0, LS_0x23658f0_0_4; +LS_0x2365e70_0_0 .concat8 [ 11 1 1 1], v0x2342ad0_3, L_0x2365530, L_0x23653f0, L_0x2364fb0; +LS_0x2365e70_0_4 .concat8 [ 1 0 0 0], L_0x2364bb0; +L_0x2365e70 .concat8 [ 14 1 0 0], LS_0x2365e70_0_0, LS_0x2365e70_0_4; +LS_0x2365b40_0_0 .concat8 [ 11 1 1 1], v0x2342ad0_0, L_0x23652b0, L_0x2364e90, L_0x2364ab0; +LS_0x2365b40_0_4 .concat8 [ 1 0 0 0], L_0x23646b0; +L_0x2365b40 .concat8 [ 14 1 0 0], LS_0x2365b40_0_0, LS_0x2365b40_0_4; +LS_0x23663e0_0_0 .concat8 [ 11 1 1 1], v0x2342ad0_1, L_0x23655e0, L_0x2365210, L_0x2364df0; +LS_0x23663e0_0_4 .concat8 [ 1 0 0 0], L_0x23649c0; +L_0x23663e0 .concat8 [ 14 1 0 0], LS_0x23663e0_0_0, LS_0x23663e0_0_4; +L_0x2366110 .part L_0x23636c0, 14, 4; +L_0x23667f0 .part L_0x23636c0, 11, 3; +L_0x2366600 .part L_0x23636c0, 8, 3; +L_0x2366a40 .part L_0x23636c0, 10, 4; +L_0x2366890 .part L_0x23636c0, 0, 11; +S_0x2343fd0 .scope module, "two" "tis100" 3 38, 4 49 0, S_0x220a8e0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x2344230 .param/l "debug" 0 4 61, +C4<00000000000000000000000000000000>; +P_0x2344270 .param/str "memFile" 0 4 60, "demo/two.dat"; +L_0x235e510 .functor BUFZ 11, v0x2344500_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x235e710 .functor BUFZ 11, v0x2344500_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x235f5c0 .functor BUFZ 18, L_0x2361560, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x2344500_0 .var/s "ACC", 10 0; +v0x2344600_0 .var/s "BAK", 10 0; +v0x23446e0_0 .net "DST", 2 0, L_0x23626a0; 1 drivers +v0x23447a0_0 .net/s "IMM", 10 0, L_0x2362740; 1 drivers +v0x2344880_0 .net "INST", 3 0, L_0x2361f80; 1 drivers +v0x23449b0_0 .net "LABEL", 3 0, L_0x23628f0; 1 drivers +v0x2344a90_0 .var "PC", 3 0; +v0x2344b70_0 .var "PCNEXT", 3 0; +v0x2344c50_0 .net "SRC", 2 0, L_0x23624b0; 1 drivers +v0x2344dc0_0 .net *"_s103", 0 0, L_0x23608a0; 1 drivers +v0x2344ea0_0 .net *"_s107", 0 0, L_0x23607b0; 1 drivers +v0x2344f80_0 .net *"_s111", 0 0, L_0x2360a90; 1 drivers +v0x2345060_0 .net *"_s115", 0 0, L_0x2360990; 1 drivers +v0x2345140_0 .net *"_s119", 0 0, L_0x2360cd0; 1 drivers +v0x2345220_0 .net *"_s123", 0 0, L_0x2360bc0; 1 drivers +v0x2345300_0 .net *"_s127", 0 0, L_0x2360e90; 1 drivers +v0x23453e0_0 .net *"_s131", 0 0, L_0x2360d70; 1 drivers +v0x2345590_0 .net *"_s135", 0 0, L_0x23610f0; 1 drivers +v0x2345630_0 .net *"_s139", 0 0, L_0x2360fc0; 1 drivers +v0x2345710_0 .net *"_s143", 0 0, L_0x23612d0; 1 drivers +v0x23457f0_0 .net *"_s147", 0 0, L_0x2361190; 1 drivers +v0x23458d0_0 .net *"_s151", 0 0, L_0x23614c0; 1 drivers +v0x23459b0_0 .net *"_s155", 0 0, L_0x2361370; 1 drivers +v0x2345a90_0 .net *"_s159", 0 0, L_0x2361410; 1 drivers +v0x2345b70_0 .net *"_s160", 17 0, L_0x2361560; 1 drivers +v0x2345c50_0 .net *"_s162", 5 0, L_0x23618c0; 1 drivers +L_0x2b7d4c4d50f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x2345d30_0 .net *"_s165", 1 0, L_0x2b7d4c4d50f0; 1 drivers +v0x2347cf0_2 .array/port v0x2347cf0, 2; +v0x2345e10_0 .net *"_s173", 10 0, v0x2347cf0_2; 1 drivers +v0x2347cf0_3 .array/port v0x2347cf0, 3; +v0x2345ef0_0 .net *"_s179", 10 0, v0x2347cf0_3; 1 drivers +v0x2347cf0_0 .array/port v0x2347cf0, 0; +v0x2345fd0_0 .net *"_s185", 10 0, v0x2347cf0_0; 1 drivers +v0x2347cf0_1 .array/port v0x2347cf0, 1; +v0x23460b0_0 .net *"_s191", 10 0, v0x2347cf0_1; 1 drivers +v0x2346190_0 .net *"_s23", 0 0, L_0x235ed80; 1 drivers +v0x2346270_0 .net *"_s27", 0 0, L_0x235eea0; 1 drivers +v0x23454c0_0 .net *"_s31", 0 0, L_0x235ef90; 1 drivers +v0x2346540_0 .net *"_s36", 0 0, L_0x235f260; 1 drivers +v0x2346620_0 .net *"_s42", 0 0, L_0x235f480; 1 drivers +v0x2346700_0 .net *"_s46", 0 0, L_0x235f520; 1 drivers +v0x23467e0_0 .net *"_s50", 0 0, L_0x235f630; 1 drivers +v0x23468c0_0 .net *"_s55", 0 0, L_0x235f870; 1 drivers +v0x23469a0_0 .net *"_s61", 0 0, L_0x235fae0; 1 drivers +v0x2346a80_0 .net *"_s65", 0 0, L_0x235fc10; 1 drivers +v0x2346b60_0 .net *"_s69", 0 0, L_0x235fde0; 1 drivers +v0x2346c40_0 .net *"_s74", 0 0, L_0x235fd40; 1 drivers +v0x2346d20_0 .net *"_s80", 0 0, L_0x235ff80; 1 drivers +v0x2346e00_0 .net *"_s84", 0 0, L_0x2360230; 1 drivers +v0x2346ee0_0 .net *"_s88", 0 0, L_0x2360170; 1 drivers +v0x2346fc0_0 .net *"_s93", 0 0, L_0x23602d0; 1 drivers +v0x23470a0_0 .net *"_s99", 0 0, L_0x2360590; 1 drivers +v0x2347180_0 .net/s "accOut", 10 0, L_0x235e510; 1 drivers +v0x2347260_0 .net "anyHasData", 0 0, L_0x235f3e0; 1 drivers +v0x2347320_0 .net "anyReadAck", 0 0, L_0x2360080; 1 drivers +v0x23473e0_0 .net "anyWantData", 0 0, L_0x235f960; 1 drivers +v0x23474a0_0 .net "anyWriteAck", 0 0, L_0x23606c0; 1 drivers +v0x2347560_0 .net "clk", 0 0, v0x2349280_0; alias, 1 drivers +v0x2347710_0 .net "down", 14 0, L_0x236dbd0; alias, 1 drivers +v0x23477b0_0 .net "downOut", 14 0, L_0x2361ce0; alias, 1 drivers +v0x2347850_0 .net "instruction", 17 0, L_0x235f5c0; 1 drivers +v0x23478f0 .array "instructions", 15 0, 17 0; +v0x2347990_0 .var "last", 2 0; +o0x2b7d4c4ade58 .functor BUFZ 15, C4; HiZ drive +v0x2347a50_0 .net "left", 14 0, o0x2b7d4c4ade58; 0 drivers +v0x2347b30_0 .net "leftOut", 14 0, L_0x2361a20; 1 drivers +v0x2347c10_0 .var "mode", 2 0; +v0x2347cf0 .array/s "outVals", 2 5, 10 0; +v0x2347e60_0 .var "phase", 2 0; +v0x2347f40_0 .net "portsHaveData", 5 2, L_0x235f080; 1 drivers +v0x2346310_0 .net "portsWantData", 5 2, L_0x235f6d0; 1 drivers +v0x23463f0_0 .net "readAckIn", 5 2, L_0x235fe80; 1 drivers +v0x23483f0_0 .var "readAckOut", 5 2; +v0x2348490_0 .var "readTarget", 2 0; +v0x2348530_0 .var/s "readValue", 10 0; +L_0x2b7d4c4d50a8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2348610 .array "regVals", 0 7; +v0x2348610_0 .net/s v0x2348610 0, 10 0, L_0x2b7d4c4d50a8; 1 drivers +v0x2348610_1 .net/s v0x2348610 1, 10 0, L_0x235e710; 1 drivers +v0x2348610_2 .net/s v0x2348610 2, 10 0, L_0x235e780; 1 drivers +v0x2348610_3 .net/s v0x2348610 3, 10 0, L_0x235ea80; 1 drivers +v0x2348610_4 .net/s v0x2348610 4, 10 0, L_0x235eb80; 1 drivers +v0x2348610_5 .net/s v0x2348610 5, 10 0, L_0x235ec80; 1 drivers +o0x2b7d4c4ae218 .functor BUFZ 11, C4; HiZ drive +v0x2348610_6 .net/s v0x2348610 6, 10 0, o0x2b7d4c4ae218; 0 drivers +o0x2b7d4c4ae248 .functor BUFZ 11, C4; HiZ drive +v0x2348610_7 .net/s v0x2348610 7, 10 0, o0x2b7d4c4ae248; 0 drivers +o0x2b7d4c4ae278 .functor BUFZ 15, C4; HiZ drive +v0x2348820_0 .net "right", 14 0, o0x2b7d4c4ae278; 0 drivers +v0x2348900_0 .net "rightOut", 14 0, L_0x2362290; 1 drivers +o0x2b7d4c4ae2d8 .functor BUFZ 15, C4; HiZ drive +v0x23489e0_0 .net "up", 14 0, o0x2b7d4c4ae2d8; 0 drivers +v0x2348ac0_0 .net "upOut", 14 0, L_0x23617d0; 1 drivers +v0x2348ba0_0 .var "weHaveData", 5 2; +v0x2348c80_0 .var "weWantData", 5 2; +v0x2348d60_0 .net "writeAckIn", 5 2, L_0x23603a0; 1 drivers +v0x2348e40_0 .var "writeAckOut", 5 2; +v0x2348f20_0 .var "writeTarget", 2 0; +v0x2349000_0 .var/s "writeValue", 10 0; +L_0x235e780 .part o0x2b7d4c4ade58, 0, 11; +L_0x235ea80 .part o0x2b7d4c4ae278, 0, 11; +L_0x235eb80 .part o0x2b7d4c4ae2d8, 0, 11; +L_0x235ec80 .part L_0x236dbd0, 0, 11; +L_0x235ed80 .part o0x2b7d4c4ade58, 11, 1; +L_0x235eea0 .part o0x2b7d4c4ae278, 11, 1; +L_0x235ef90 .part o0x2b7d4c4ae2d8, 11, 1; +L_0x235f080 .concat8 [ 1 1 1 1], L_0x235ed80, L_0x235eea0, L_0x235ef90, L_0x235f260; +L_0x235f260 .part L_0x236dbd0, 11, 1; +L_0x235f3e0 .reduce/or L_0x235f080; +L_0x235f480 .part o0x2b7d4c4ade58, 12, 1; +L_0x235f520 .part o0x2b7d4c4ae278, 12, 1; +L_0x235f630 .part o0x2b7d4c4ae2d8, 12, 1; +L_0x235f6d0 .concat8 [ 1 1 1 1], L_0x235f480, L_0x235f520, L_0x235f630, L_0x235f870; +L_0x235f870 .part L_0x236dbd0, 12, 1; +L_0x235f960 .reduce/or L_0x235f6d0; +L_0x235fae0 .part o0x2b7d4c4ade58, 13, 1; +L_0x235fc10 .part o0x2b7d4c4ae278, 13, 1; +L_0x235fde0 .part o0x2b7d4c4ae2d8, 13, 1; +L_0x235fe80 .concat8 [ 1 1 1 1], L_0x235fae0, L_0x235fc10, L_0x235fde0, L_0x235fd40; +L_0x235fd40 .part L_0x236dbd0, 13, 1; +L_0x2360080 .reduce/or L_0x235fe80; +L_0x235ff80 .part o0x2b7d4c4ade58, 14, 1; +L_0x2360230 .part o0x2b7d4c4ae278, 14, 1; +L_0x2360170 .part o0x2b7d4c4ae2d8, 14, 1; +L_0x23603a0 .concat8 [ 1 1 1 1], L_0x235ff80, L_0x2360230, L_0x2360170, L_0x23602d0; +L_0x23602d0 .part L_0x236dbd0, 14, 1; +L_0x23606c0 .reduce/or L_0x23603a0; +L_0x2360590 .part v0x23483f0_0, 0, 1; +L_0x23608a0 .part v0x23483f0_0, 1, 1; +L_0x23607b0 .part v0x23483f0_0, 2, 1; +L_0x2360a90 .part v0x23483f0_0, 3, 1; +L_0x2360990 .part v0x2348e40_0, 0, 1; +L_0x2360cd0 .part v0x2348e40_0, 1, 1; +L_0x2360bc0 .part v0x2348e40_0, 2, 1; +L_0x2360e90 .part v0x2348e40_0, 3, 1; +L_0x2360d70 .part v0x2348c80_0, 0, 1; +L_0x23610f0 .part v0x2348c80_0, 1, 1; +L_0x2360fc0 .part v0x2348c80_0, 2, 1; +L_0x23612d0 .part v0x2348c80_0, 3, 1; +L_0x2361190 .part v0x2348ba0_0, 0, 1; +L_0x23614c0 .part v0x2348ba0_0, 1, 1; +L_0x2361370 .part v0x2348ba0_0, 2, 1; +L_0x2361410 .part v0x2348ba0_0, 3, 1; +L_0x2361560 .array/port v0x23478f0, L_0x23618c0; +L_0x23618c0 .concat [ 4 2 0 0], v0x2344a90_0, L_0x2b7d4c4d50f0; +LS_0x23617d0_0_0 .concat8 [ 11 1 1 1], v0x2347cf0_2, L_0x2361370, L_0x2360fc0, L_0x2360bc0; +LS_0x23617d0_0_4 .concat8 [ 1 0 0 0], L_0x23607b0; +L_0x23617d0 .concat8 [ 14 1 0 0], LS_0x23617d0_0_0, LS_0x23617d0_0_4; +LS_0x2361ce0_0_0 .concat8 [ 11 1 1 1], v0x2347cf0_3, L_0x2361410, L_0x23612d0, L_0x2360e90; +LS_0x2361ce0_0_4 .concat8 [ 1 0 0 0], L_0x2360a90; +L_0x2361ce0 .concat8 [ 14 1 0 0], LS_0x2361ce0_0_0, LS_0x2361ce0_0_4; +LS_0x2361a20_0_0 .concat8 [ 11 1 1 1], v0x2347cf0_0, L_0x2361190, L_0x2360d70, L_0x2360990; +LS_0x2361a20_0_4 .concat8 [ 1 0 0 0], L_0x2360590; +L_0x2361a20 .concat8 [ 14 1 0 0], LS_0x2361a20_0_0, LS_0x2361a20_0_4; +LS_0x2362290_0_0 .concat8 [ 11 1 1 1], v0x2347cf0_1, L_0x23614c0, L_0x23610f0, L_0x2360cd0; +LS_0x2362290_0_4 .concat8 [ 1 0 0 0], L_0x23608a0; +L_0x2362290 .concat8 [ 14 1 0 0], LS_0x2362290_0_0, LS_0x2362290_0_4; +L_0x2361f80 .part L_0x235f5c0, 14, 4; +L_0x23626a0 .part L_0x235f5c0, 11, 3; +L_0x23624b0 .part L_0x235f5c0, 8, 3; +L_0x23628f0 .part L_0x235f5c0, 10, 4; +L_0x2362740 .part L_0x235f5c0, 0, 11; + .scope S_0x21d2520; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x231ac50_0, 0, 3; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231ad30_0, 0, 4; + %pushi/vec4 0, 0, 15; + %store/vec4 v0x231ab70_0, 0, 15; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_0.0, 5; + %load/vec4 v0x231ad30_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x231aa60, 4; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x231ab70_0, 4, 11; +T_0.0 ; + %end; + .thread T_0; + .scope S_0x21d2520; +T_1 ; + %wait E_0x2282200; + %load/vec4 v0x231ad30_0; + %subi 1, 0, 4; + %store/vec4 v0x231ad30_0, 0, 4; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_1.0, 5; + %load/vec4 v0x231ad30_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x231aa60, 4; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x231ab70_0, 4, 11; +T_1.0 ; + %jmp T_1; + .thread T_1; + .scope S_0x21d2520; +T_2 ; + %wait E_0x21faa10; + %load/vec4 v0x231ad30_0; + %subi 1, 0, 4; + %store/vec4 v0x231ad30_0, 0, 4; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_2.0, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; + %load/vec4 v0x231ad30_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x231aa60, 4; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; + %jmp T_2.1; +T_2.0 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x21d2520; +T_3 ; + %wait E_0x2206010; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmpi/u 15, 0, 32; + %jmp/0xz T_3.0, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 12, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; + %jmp T_3.1; +T_3.0 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 12, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; +T_3.1 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_3.2, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; + %jmp T_3.3; +T_3.2 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; +T_3.3 ; + %jmp T_3; + .thread T_3, $push; + .scope S_0x21d2520; +T_4 ; + %wait E_0x220a2b0; + %load/vec4 v0x231ac50_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0x231a980_0; + %parti/s 1, 11, 5; + %flag_set/vec4 8; + %jmp/0xz T_4.4, 8; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmpi/u 15, 0, 32; + %jmp/0xz T_4.6, 5; + %load/vec4 v0x231ad30_0; + %addi 1, 0, 4; + %store/vec4 v0x231ad30_0, 0, 4; + %load/vec4 v0x231a980_0; + %parti/s 11, 0, 2; + %load/vec4 v0x231ad30_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %store/vec4a v0x231aa60, 4, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 13, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; +T_4.6 ; +T_4.4 ; + %jmp T_4.3; +T_4.1 ; + %jmp T_4.3; +T_4.2 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x231ad30_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_4.8, 5; + %load/vec4 v0x231ad30_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x231aa60, 4; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; + %load/vec4 v0x231a980_0; + %parti/s 1, 12, 5; + %flag_set/vec4 8; + %jmp/0xz T_4.10, 8; + %load/vec4 v0x231ad30_0; + %subi 1, 0, 4; + %store/vec4 v0x231ad30_0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 4, 14, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231ab70_0, 4, 5; +T_4.10 ; +T_4.8 ; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0x21d2520; +T_5 ; + %wait E_0x21dde80; + %load/vec4 v0x231ac50_0; + %cmpi/e 2, 0, 3; + %jmp/0xz T_5.0, 4; + %pushi/vec4 0, 0, 1; + %ix/load 4, 13, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x231ab70_0, 4, 1; + %pushi/vec4 0, 0, 1; + %ix/load 4, 14, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x231ab70_0, 4, 1; +T_5.0 ; + %load/vec4 v0x231ac50_0; + %pad/u 32; + %addi 1, 0, 32; + %pushi/vec4 3, 0, 32; + %mod; + %pad/u 3; + %store/vec4 v0x231ac50_0, 0, 3; + %jmp T_5; + .thread T_5; + .scope S_0x232a5e0; +T_6 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x232e130_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x232e380_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x232de90_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x232aad0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x232abd0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232b020_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232e910_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232f1c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232f380_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232f100_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x232e210, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x232e210, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x232e210, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x232e210, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x232a7f0, v0x232ddd0 {0 0 0}; + %end; + .thread T_6; + .scope S_0x232a5e0; +T_7 ; + %wait E_0x231b3f0; + %load/vec4 v0x232e130_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.2, 6; + %jmp T_7.3; +T_7.0 ; + %load/vec4 v0x232e380_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.6, 6; + %jmp T_7.7; +T_7.4 ; + %load/vec4 v0x232ae50_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_7.8, 5; + %load/vec4 v0x232b180_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_7.10, 5; + %load/vec4 v0x232b180_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %jmp T_7.11; +T_7.10 ; + %load/vec4 v0x232b180_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_7.12, 5; + %load/vec4 v0x232e460_0; + %load/vec4 v0x232b180_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.14, 8; + %load/vec4 v0x232b180_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232b180_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %load/vec4 v0x232b180_0; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.15; +T_7.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %load/vec4 v0x232b180_0; + %assign/vec4 v0x232e9b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232b180_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; + %load/vec4 v0x232b180_0; + %assign/vec4 v0x232de90_0, 0; +T_7.15 ; + %jmp T_7.13; +T_7.12 ; + %load/vec4 v0x232b180_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.16, 4; + %load/vec4 v0x232de90_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_7.18, 4; + %load/vec4 v0x232de90_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %jmp T_7.19; +T_7.18 ; + %load/vec4 v0x232e460_0; + %load/vec4 v0x232de90_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.20, 8; + %load/vec4 v0x232de90_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232de90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %jmp T_7.21; +T_7.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %load/vec4 v0x232de90_0; + %assign/vec4 v0x232e9b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232de90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; +T_7.21 ; +T_7.19 ; + %jmp T_7.17; +T_7.16 ; + %load/vec4 v0x232b180_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.22, 4; + %load/vec4 v0x232d790_0; + %flag_set/vec4 8; + %jmp/0xz T_7.24, 8; + %load/vec4 v0x232e460_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.27; +T_7.26 ; + %load/vec4 v0x232e460_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.29; +T_7.28 ; + %load/vec4 v0x232e460_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.31; +T_7.30 ; + %load/vec4 v0x232e460_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232de90_0, 0; +T_7.32 ; +T_7.31 ; +T_7.29 ; +T_7.27 ; + %jmp T_7.25; +T_7.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %load/vec4 v0x232b180_0; + %assign/vec4 v0x232e9b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; +T_7.25 ; +T_7.22 ; +T_7.17 ; +T_7.13 ; +T_7.11 ; +T_7.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.7; +T_7.5 ; + %load/vec4 v0x232ae50_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_7.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_7.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_7.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_7.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_7.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_7.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_7.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_7.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_7.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_7.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_7.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_7.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_7.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_7.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_7.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_7.49, 6; + %jmp T_7.50; +T_7.34 ; + %load/vec4 v0x232aad0_0; + %load/vec4 v0x232ea90_0; + %add; + %assign/vec4 v0x232aad0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.35 ; + %load/vec4 v0x232aad0_0; + %load/vec4 v0x232ea90_0; + %sub; + %assign/vec4 v0x232aad0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.36 ; + %load/vec4 v0x232b020_0; + %pad/u 11; + %load/vec4 v0x232ea90_0; + %add; + %pad/u 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.37 ; + %load/vec4 v0x232ea90_0; + %assign/vec4 v0x232f540_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.38 ; + %load/vec4 v0x232ad70_0; + %assign/vec4 v0x232f540_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.39 ; + %load/vec4 v0x232aad0_0; + %load/vec4 v0x232ad70_0; + %add; + %assign/vec4 v0x232aad0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.40 ; + %load/vec4 v0x232aad0_0; + %load/vec4 v0x232ad70_0; + %sub; + %assign/vec4 v0x232aad0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.41 ; + %load/vec4 v0x232b020_0; + %pad/u 11; + %load/vec4 v0x232ad70_0; + %add; + %pad/u 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.42 ; + %load/vec4 v0x232abd0_0; + %assign/vec4 v0x232aad0_0, 0; + %load/vec4 v0x232aad0_0; + %assign/vec4 v0x232abd0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.43 ; + %load/vec4 v0x232aad0_0; + %assign/vec4 v0x232abd0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.44 ; + %load/vec4 v0x232aad0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x232aad0_0, 0; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.45 ; + %load/vec4 v0x232af80_0; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.50; +T_7.46 ; + %load/vec4 v0x232aad0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_7.51, 4; + %load/vec4 v0x232af80_0; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.52; +T_7.51 ; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; +T_7.52 ; + %jmp T_7.50; +T_7.47 ; + %load/vec4 v0x232aad0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_7.53, 4; + %load/vec4 v0x232af80_0; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.54; +T_7.53 ; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; +T_7.54 ; + %jmp T_7.50; +T_7.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x232aad0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_7.55, 5; + %load/vec4 v0x232af80_0; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.56; +T_7.55 ; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; +T_7.56 ; + %jmp T_7.50; +T_7.49 ; + %load/vec4 v0x232aad0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_7.57, 5; + %load/vec4 v0x232af80_0; + %assign/vec4 v0x232b0c0_0, 0; + %jmp T_7.58; +T_7.57 ; + %load/vec4 v0x232b020_0; + %addi 1, 0, 4; + %assign/vec4 v0x232b0c0_0, 0; +T_7.58 ; + %jmp T_7.50; +T_7.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.7; +T_7.6 ; + %load/vec4 v0x232ae50_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x232ae50_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_7.59, 4; + %load/vec4 v0x232acb0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x232acb0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x232de90_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_7.61, 9; + %load/vec4 v0x232acb0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_7.63, 4; + %load/vec4 v0x232f540_0; + %assign/vec4 v0x232aad0_0, 0; +T_7.63 ; + %jmp T_7.62; +T_7.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %load/vec4 v0x232acb0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.65, 4; + %load/vec4 v0x232de90_0; + %assign/vec4 v0x232f460_0, 0; + %load/vec4 v0x232f540_0; + %load/vec4 v0x232de90_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232de90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %jmp T_7.66; +T_7.65 ; + %load/vec4 v0x232acb0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.67, 4; + %load/vec4 v0x232acb0_0; + %assign/vec4 v0x232f460_0, 0; + %load/vec4 v0x232f540_0; + %load/vec4 v0x232acb0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232acb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232acb0_0; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.68; +T_7.67 ; + %load/vec4 v0x232d910_0; + %flag_set/vec4 8; + %jmp/0xz T_7.69, 8; + %load/vec4 v0x232c840_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.72; +T_7.71 ; + %load/vec4 v0x232c840_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.74; +T_7.73 ; + %load/vec4 v0x232c840_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.76; +T_7.75 ; + %load/vec4 v0x232c840_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232de90_0, 0; +T_7.77 ; +T_7.76 ; +T_7.74 ; +T_7.72 ; + %jmp T_7.70; +T_7.69 ; + %load/vec4 v0x232acb0_0; + %assign/vec4 v0x232f460_0, 0; +T_7.70 ; +T_7.68 ; +T_7.66 ; +T_7.62 ; +T_7.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.7; +T_7.7 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.1 ; + %load/vec4 v0x232e380_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.81, 6; + %jmp T_7.82; +T_7.79 ; + %load/vec4 v0x232e9b0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.83, 4; + %load/vec4 v0x232d790_0; + %flag_set/vec4 8; + %jmp/0xz T_7.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232f1c0_0, 0, 4; + %load/vec4 v0x232e460_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.88; +T_7.87 ; + %load/vec4 v0x232e460_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.90; +T_7.89 ; + %load/vec4 v0x232e460_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.92; +T_7.91 ; + %load/vec4 v0x232e460_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232de90_0, 0; +T_7.93 ; +T_7.92 ; +T_7.90 ; +T_7.88 ; +T_7.85 ; + %jmp T_7.84; +T_7.83 ; + %load/vec4 v0x232e460_0; + %load/vec4 v0x232e9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %load/vec4 v0x232e9b0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x232eb70, 4; + %assign/vec4 v0x232ea90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232e9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232e910_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232e9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x232f1c0_0, 4, 5; + %load/vec4 v0x232e9b0_0; + %assign/vec4 v0x232de90_0, 0; +T_7.95 ; +T_7.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.82; +T_7.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.82; +T_7.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.82; +T_7.82 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0x232e380_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.99, 6; + %jmp T_7.100; +T_7.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.100; +T_7.98 ; + %load/vec4 v0x232f460_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.101, 4; + %load/vec4 v0x232d910_0; + %flag_set/vec4 8; + %jmp/0xz T_7.103, 8; + %load/vec4 v0x232c840_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.106; +T_7.105 ; + %load/vec4 v0x232c840_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.108; +T_7.107 ; + %load/vec4 v0x232c840_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232de90_0, 0; + %jmp T_7.110; +T_7.109 ; + %load/vec4 v0x232c840_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232f460_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x232f100_0, 4, 5; + %load/vec4 v0x232f540_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x232e210, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232de90_0, 0; +T_7.111 ; +T_7.110 ; +T_7.108 ; +T_7.106 ; +T_7.103 ; +T_7.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.100; +T_7.99 ; + %load/vec4 v0x232f460_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.113, 4; + %load/vec4 v0x232f2a0_0; + %load/vec4 v0x232f460_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x232f460_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x232f100_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x232e130_0, 0; + %load/vec4 v0x232f460_0; + %assign/vec4 v0x232de90_0, 0; +T_7.115 ; +T_7.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x232e380_0, 0; + %jmp T_7.100; +T_7.100 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.3 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7; + .scope S_0x232a5e0; +T_8 ; + %wait E_0x231b1f0; + %load/vec4 v0x232e380_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x232e130_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x232b0c0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x232b0c0_0; + %assign/vec4 v0x232b020_0, 0; +T_8.0 ; + %load/vec4 v0x232e380_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_8.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232e910_0, 0, 4; +T_8.2 ; + %jmp T_8; + .thread T_8; + .scope S_0x2343fd0; +T_9 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2347c10_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2347e60_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2347990_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x2344500_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x2344600_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2344a90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23483f0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2348c80_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2348e40_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2348ba0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2347cf0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2347cf0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2347cf0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2347cf0, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x2344270, v0x23478f0 {0 0 0}; + %end; + .thread T_9; + .scope S_0x2343fd0; +T_10 ; + %wait E_0x231b3f0; + %load/vec4 v0x2347c10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.2, 6; + %jmp T_10.3; +T_10.0 ; + %load/vec4 v0x2347e60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.6, 6; + %jmp T_10.7; +T_10.4 ; + %load/vec4 v0x2344880_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_10.8, 5; + %load/vec4 v0x2344c50_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_10.10, 5; + %load/vec4 v0x2344c50_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %jmp T_10.11; +T_10.10 ; + %load/vec4 v0x2344c50_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_10.12, 5; + %load/vec4 v0x2347f40_0; + %load/vec4 v0x2344c50_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.14, 8; + %load/vec4 v0x2344c50_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2344c50_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %load/vec4 v0x2344c50_0; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.15; +T_10.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %load/vec4 v0x2344c50_0; + %assign/vec4 v0x2348490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2344c50_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2348c80_0, 4, 5; + %load/vec4 v0x2344c50_0; + %assign/vec4 v0x2347990_0, 0; +T_10.15 ; + %jmp T_10.13; +T_10.12 ; + %load/vec4 v0x2344c50_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.16, 4; + %load/vec4 v0x2347990_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_10.18, 4; + %load/vec4 v0x2347990_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %jmp T_10.19; +T_10.18 ; + %load/vec4 v0x2347f40_0; + %load/vec4 v0x2347990_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.20, 8; + %load/vec4 v0x2347990_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2347990_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %jmp T_10.21; +T_10.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %load/vec4 v0x2347990_0; + %assign/vec4 v0x2348490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2347990_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2348c80_0, 4, 5; +T_10.21 ; +T_10.19 ; + %jmp T_10.17; +T_10.16 ; + %load/vec4 v0x2344c50_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.22, 4; + %load/vec4 v0x2347260_0; + %flag_set/vec4 8; + %jmp/0xz T_10.24, 8; + %load/vec4 v0x2347f40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.27; +T_10.26 ; + %load/vec4 v0x2347f40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.29; +T_10.28 ; + %load/vec4 v0x2347f40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.31; +T_10.30 ; + %load/vec4 v0x2347f40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2347990_0, 0; +T_10.32 ; +T_10.31 ; +T_10.29 ; +T_10.27 ; + %jmp T_10.25; +T_10.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %load/vec4 v0x2344c50_0; + %assign/vec4 v0x2348490_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348c80_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348c80_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348c80_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348c80_0, 4, 5; +T_10.25 ; +T_10.22 ; +T_10.17 ; +T_10.13 ; +T_10.11 ; +T_10.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.7; +T_10.5 ; + %load/vec4 v0x2344880_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_10.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_10.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_10.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_10.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_10.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_10.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_10.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_10.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_10.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_10.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_10.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_10.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_10.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_10.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_10.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_10.49, 6; + %jmp T_10.50; +T_10.34 ; + %load/vec4 v0x2344500_0; + %load/vec4 v0x2348530_0; + %add; + %assign/vec4 v0x2344500_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.35 ; + %load/vec4 v0x2344500_0; + %load/vec4 v0x2348530_0; + %sub; + %assign/vec4 v0x2344500_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.36 ; + %load/vec4 v0x2344a90_0; + %pad/u 11; + %load/vec4 v0x2348530_0; + %add; + %pad/u 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.37 ; + %load/vec4 v0x2348530_0; + %assign/vec4 v0x2349000_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.38 ; + %load/vec4 v0x23447a0_0; + %assign/vec4 v0x2349000_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.39 ; + %load/vec4 v0x2344500_0; + %load/vec4 v0x23447a0_0; + %add; + %assign/vec4 v0x2344500_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.40 ; + %load/vec4 v0x2344500_0; + %load/vec4 v0x23447a0_0; + %sub; + %assign/vec4 v0x2344500_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.41 ; + %load/vec4 v0x2344a90_0; + %pad/u 11; + %load/vec4 v0x23447a0_0; + %add; + %pad/u 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.42 ; + %load/vec4 v0x2344600_0; + %assign/vec4 v0x2344500_0, 0; + %load/vec4 v0x2344500_0; + %assign/vec4 v0x2344600_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.43 ; + %load/vec4 v0x2344500_0; + %assign/vec4 v0x2344600_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.44 ; + %load/vec4 v0x2344500_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x2344500_0, 0; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.45 ; + %load/vec4 v0x23449b0_0; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.50; +T_10.46 ; + %load/vec4 v0x2344500_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_10.51, 4; + %load/vec4 v0x23449b0_0; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.52; +T_10.51 ; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; +T_10.52 ; + %jmp T_10.50; +T_10.47 ; + %load/vec4 v0x2344500_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_10.53, 4; + %load/vec4 v0x23449b0_0; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.54; +T_10.53 ; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; +T_10.54 ; + %jmp T_10.50; +T_10.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x2344500_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_10.55, 5; + %load/vec4 v0x23449b0_0; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.56; +T_10.55 ; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; +T_10.56 ; + %jmp T_10.50; +T_10.49 ; + %load/vec4 v0x2344500_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_10.57, 5; + %load/vec4 v0x23449b0_0; + %assign/vec4 v0x2344b70_0, 0; + %jmp T_10.58; +T_10.57 ; + %load/vec4 v0x2344a90_0; + %addi 1, 0, 4; + %assign/vec4 v0x2344b70_0, 0; +T_10.58 ; + %jmp T_10.50; +T_10.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.7; +T_10.6 ; + %load/vec4 v0x2344880_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x2344880_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_10.59, 4; + %load/vec4 v0x23446e0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x23446e0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2347990_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_10.61, 9; + %load/vec4 v0x23446e0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_10.63, 4; + %load/vec4 v0x2349000_0; + %assign/vec4 v0x2344500_0, 0; +T_10.63 ; + %jmp T_10.62; +T_10.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %load/vec4 v0x23446e0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.65, 4; + %load/vec4 v0x2347990_0; + %assign/vec4 v0x2348f20_0, 0; + %load/vec4 v0x2349000_0; + %load/vec4 v0x2347990_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2347990_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %jmp T_10.66; +T_10.65 ; + %load/vec4 v0x23446e0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.67, 4; + %load/vec4 v0x23446e0_0; + %assign/vec4 v0x2348f20_0, 0; + %load/vec4 v0x2349000_0; + %load/vec4 v0x23446e0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23446e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x23446e0_0; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.68; +T_10.67 ; + %load/vec4 v0x23473e0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.69, 8; + %load/vec4 v0x2346310_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.72; +T_10.71 ; + %load/vec4 v0x2346310_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.74; +T_10.73 ; + %load/vec4 v0x2346310_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.76; +T_10.75 ; + %load/vec4 v0x2346310_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2347990_0, 0; +T_10.77 ; +T_10.76 ; +T_10.74 ; +T_10.72 ; + %jmp T_10.70; +T_10.69 ; + %load/vec4 v0x23446e0_0; + %assign/vec4 v0x2348f20_0, 0; +T_10.70 ; +T_10.68 ; +T_10.66 ; +T_10.62 ; +T_10.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.7; +T_10.7 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.1 ; + %load/vec4 v0x2347e60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.81, 6; + %jmp T_10.82; +T_10.79 ; + %load/vec4 v0x2348490_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.83, 4; + %load/vec4 v0x2347260_0; + %flag_set/vec4 8; + %jmp/0xz T_10.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2348c80_0, 0, 4; + %load/vec4 v0x2347f40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.88; +T_10.87 ; + %load/vec4 v0x2347f40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.90; +T_10.89 ; + %load/vec4 v0x2347f40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.92; +T_10.91 ; + %load/vec4 v0x2347f40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2347990_0, 0; +T_10.93 ; +T_10.92 ; +T_10.90 ; +T_10.88 ; +T_10.85 ; + %jmp T_10.84; +T_10.83 ; + %load/vec4 v0x2347f40_0; + %load/vec4 v0x2348490_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %load/vec4 v0x2348490_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2348610, 4; + %assign/vec4 v0x2348530_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2348490_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23483f0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2348490_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2348c80_0, 4, 5; + %load/vec4 v0x2348490_0; + %assign/vec4 v0x2347990_0, 0; +T_10.95 ; +T_10.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.82; +T_10.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.82; +T_10.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.82; +T_10.82 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0x2347e60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.99, 6; + %jmp T_10.100; +T_10.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.100; +T_10.98 ; + %load/vec4 v0x2348f20_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.101, 4; + %load/vec4 v0x23473e0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.103, 8; + %load/vec4 v0x2346310_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.106; +T_10.105 ; + %load/vec4 v0x2346310_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.108; +T_10.107 ; + %load/vec4 v0x2346310_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2347990_0, 0; + %jmp T_10.110; +T_10.109 ; + %load/vec4 v0x2346310_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2348f20_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2348ba0_0, 4, 5; + %load/vec4 v0x2349000_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2347cf0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2347990_0, 0; +T_10.111 ; +T_10.110 ; +T_10.108 ; +T_10.106 ; +T_10.103 ; +T_10.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.100; +T_10.99 ; + %load/vec4 v0x2348f20_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.113, 4; + %load/vec4 v0x2348d60_0; + %load/vec4 v0x2348f20_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x2348f20_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2348ba0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2347c10_0, 0; + %load/vec4 v0x2348f20_0; + %assign/vec4 v0x2347990_0, 0; +T_10.115 ; +T_10.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2347e60_0, 0; + %jmp T_10.100; +T_10.100 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.3 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10; + .scope S_0x2343fd0; +T_11 ; + %wait E_0x231b1f0; + %load/vec4 v0x2347e60_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2347c10_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x2344b70_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0x2344b70_0; + %assign/vec4 v0x2344a90_0, 0; +T_11.0 ; + %load/vec4 v0x2347e60_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_11.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23483f0_0, 0, 4; +T_11.2 ; + %jmp T_11; + .thread T_11; + .scope S_0x233ee00; +T_12 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x23429f0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2342c10_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2342750_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x233f2f0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x233f3f0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233f880_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23431a0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23439d0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2343b90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2343910_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2342ad0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2342ad0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2342ad0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2342ad0, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x233f010, v0x2342690 {0 0 0}; + %end; + .thread T_12; + .scope S_0x233ee00; +T_13 ; + %wait E_0x231b3f0; + %load/vec4 v0x23429f0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.2, 6; + %jmp T_13.3; +T_13.0 ; + %load/vec4 v0x2342c10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.6, 6; + %jmp T_13.7; +T_13.4 ; + %load/vec4 v0x233f670_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_13.8, 5; + %load/vec4 v0x233fa40_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_13.10, 5; + %load/vec4 v0x233fa40_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %jmp T_13.11; +T_13.10 ; + %load/vec4 v0x233fa40_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_13.12, 5; + %load/vec4 v0x2342cf0_0; + %load/vec4 v0x233fa40_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.14, 8; + %load/vec4 v0x233fa40_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233fa40_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %load/vec4 v0x233fa40_0; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.15; +T_13.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %load/vec4 v0x233fa40_0; + %assign/vec4 v0x2343240_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233fa40_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23439d0_0, 4, 5; + %load/vec4 v0x233fa40_0; + %assign/vec4 v0x2342750_0, 0; +T_13.15 ; + %jmp T_13.13; +T_13.12 ; + %load/vec4 v0x233fa40_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.16, 4; + %load/vec4 v0x2342750_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_13.18, 4; + %load/vec4 v0x2342750_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %jmp T_13.19; +T_13.18 ; + %load/vec4 v0x2342cf0_0; + %load/vec4 v0x2342750_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.20, 8; + %load/vec4 v0x2342750_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2342750_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %jmp T_13.21; +T_13.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %load/vec4 v0x2342750_0; + %assign/vec4 v0x2343240_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2342750_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23439d0_0, 4, 5; +T_13.21 ; +T_13.19 ; + %jmp T_13.17; +T_13.16 ; + %load/vec4 v0x233fa40_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.22, 4; + %load/vec4 v0x2342050_0; + %flag_set/vec4 8; + %jmp/0xz T_13.24, 8; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.27; +T_13.26 ; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.29; +T_13.28 ; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.31; +T_13.30 ; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2342750_0, 0; +T_13.32 ; +T_13.31 ; +T_13.29 ; +T_13.27 ; + %jmp T_13.25; +T_13.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %load/vec4 v0x233fa40_0; + %assign/vec4 v0x2343240_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23439d0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23439d0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23439d0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23439d0_0, 4, 5; +T_13.25 ; +T_13.22 ; +T_13.17 ; +T_13.13 ; +T_13.11 ; +T_13.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.7; +T_13.5 ; + %load/vec4 v0x233f670_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_13.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_13.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_13.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_13.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_13.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_13.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_13.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_13.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_13.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_13.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_13.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_13.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_13.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_13.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_13.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_13.49, 6; + %jmp T_13.50; +T_13.34 ; + %load/vec4 v0x233f2f0_0; + %load/vec4 v0x23432e0_0; + %add; + %assign/vec4 v0x233f2f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.35 ; + %load/vec4 v0x233f2f0_0; + %load/vec4 v0x23432e0_0; + %sub; + %assign/vec4 v0x233f2f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.36 ; + %load/vec4 v0x233f880_0; + %pad/u 11; + %load/vec4 v0x23432e0_0; + %add; + %pad/u 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.37 ; + %load/vec4 v0x23432e0_0; + %assign/vec4 v0x2343d50_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.38 ; + %load/vec4 v0x233f590_0; + %assign/vec4 v0x2343d50_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.39 ; + %load/vec4 v0x233f2f0_0; + %load/vec4 v0x233f590_0; + %add; + %assign/vec4 v0x233f2f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.40 ; + %load/vec4 v0x233f2f0_0; + %load/vec4 v0x233f590_0; + %sub; + %assign/vec4 v0x233f2f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.41 ; + %load/vec4 v0x233f880_0; + %pad/u 11; + %load/vec4 v0x233f590_0; + %add; + %pad/u 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.42 ; + %load/vec4 v0x233f3f0_0; + %assign/vec4 v0x233f2f0_0, 0; + %load/vec4 v0x233f2f0_0; + %assign/vec4 v0x233f3f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.43 ; + %load/vec4 v0x233f2f0_0; + %assign/vec4 v0x233f3f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.44 ; + %load/vec4 v0x233f2f0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x233f2f0_0, 0; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.45 ; + %load/vec4 v0x233f7a0_0; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.50; +T_13.46 ; + %load/vec4 v0x233f2f0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_13.51, 4; + %load/vec4 v0x233f7a0_0; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.52; +T_13.51 ; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; +T_13.52 ; + %jmp T_13.50; +T_13.47 ; + %load/vec4 v0x233f2f0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_13.53, 4; + %load/vec4 v0x233f7a0_0; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.54; +T_13.53 ; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; +T_13.54 ; + %jmp T_13.50; +T_13.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x233f2f0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_13.55, 5; + %load/vec4 v0x233f7a0_0; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.56; +T_13.55 ; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; +T_13.56 ; + %jmp T_13.50; +T_13.49 ; + %load/vec4 v0x233f2f0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_13.57, 5; + %load/vec4 v0x233f7a0_0; + %assign/vec4 v0x233f960_0, 0; + %jmp T_13.58; +T_13.57 ; + %load/vec4 v0x233f880_0; + %addi 1, 0, 4; + %assign/vec4 v0x233f960_0, 0; +T_13.58 ; + %jmp T_13.50; +T_13.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.7; +T_13.6 ; + %load/vec4 v0x233f670_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x233f670_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_13.59, 4; + %load/vec4 v0x233f4d0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x233f4d0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2342750_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_13.61, 9; + %load/vec4 v0x233f4d0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_13.63, 4; + %load/vec4 v0x2343d50_0; + %assign/vec4 v0x233f2f0_0, 0; +T_13.63 ; + %jmp T_13.62; +T_13.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %load/vec4 v0x233f4d0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.65, 4; + %load/vec4 v0x2342750_0; + %assign/vec4 v0x2343c70_0, 0; + %load/vec4 v0x2343d50_0; + %load/vec4 v0x2342750_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2342750_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %jmp T_13.66; +T_13.65 ; + %load/vec4 v0x233f4d0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.67, 4; + %load/vec4 v0x233f4d0_0; + %assign/vec4 v0x2343c70_0, 0; + %load/vec4 v0x2343d50_0; + %load/vec4 v0x233f4d0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233f4d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x233f4d0_0; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.68; +T_13.67 ; + %load/vec4 v0x23421d0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.69, 8; + %load/vec4 v0x2341100_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.72; +T_13.71 ; + %load/vec4 v0x2341100_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.74; +T_13.73 ; + %load/vec4 v0x2341100_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.76; +T_13.75 ; + %load/vec4 v0x2341100_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2342750_0, 0; +T_13.77 ; +T_13.76 ; +T_13.74 ; +T_13.72 ; + %jmp T_13.70; +T_13.69 ; + %load/vec4 v0x233f4d0_0; + %assign/vec4 v0x2343c70_0, 0; +T_13.70 ; +T_13.68 ; +T_13.66 ; +T_13.62 ; +T_13.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.7; +T_13.7 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.1 ; + %load/vec4 v0x2342c10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.81, 6; + %jmp T_13.82; +T_13.79 ; + %load/vec4 v0x2343240_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.83, 4; + %load/vec4 v0x2342050_0; + %flag_set/vec4 8; + %jmp/0xz T_13.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23439d0_0, 0, 4; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.88; +T_13.87 ; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.90; +T_13.89 ; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.92; +T_13.91 ; + %load/vec4 v0x2342cf0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2342750_0, 0; +T_13.93 ; +T_13.92 ; +T_13.90 ; +T_13.88 ; +T_13.85 ; + %jmp T_13.84; +T_13.83 ; + %load/vec4 v0x2342cf0_0; + %load/vec4 v0x2343240_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %load/vec4 v0x2343240_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x23433a0, 4; + %assign/vec4 v0x23432e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2343240_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23431a0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2343240_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x23439d0_0, 4, 5; + %load/vec4 v0x2343240_0; + %assign/vec4 v0x2342750_0, 0; +T_13.95 ; +T_13.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.82; +T_13.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.82; +T_13.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.82; +T_13.82 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x2342c10_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.99, 6; + %jmp T_13.100; +T_13.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.100; +T_13.98 ; + %load/vec4 v0x2343c70_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.101, 4; + %load/vec4 v0x23421d0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.103, 8; + %load/vec4 v0x2341100_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.106; +T_13.105 ; + %load/vec4 v0x2341100_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.108; +T_13.107 ; + %load/vec4 v0x2341100_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2342750_0, 0; + %jmp T_13.110; +T_13.109 ; + %load/vec4 v0x2341100_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2343c70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2343910_0, 4, 5; + %load/vec4 v0x2343d50_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2342ad0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2342750_0, 0; +T_13.111 ; +T_13.110 ; +T_13.108 ; +T_13.106 ; +T_13.103 ; +T_13.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.100; +T_13.99 ; + %load/vec4 v0x2343c70_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.113, 4; + %load/vec4 v0x2343ab0_0; + %load/vec4 v0x2343c70_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x2343c70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2343910_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x23429f0_0, 0; + %load/vec4 v0x2343c70_0; + %assign/vec4 v0x2342750_0, 0; +T_13.115 ; +T_13.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2342c10_0, 0; + %jmp T_13.100; +T_13.100 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.3 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13; + .scope S_0x233ee00; +T_14 ; + %wait E_0x231b1f0; + %load/vec4 v0x2342c10_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x23429f0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x233f960_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %load/vec4 v0x233f960_0; + %assign/vec4 v0x233f880_0, 0; +T_14.0 ; + %load/vec4 v0x2342c10_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_14.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23431a0_0, 0, 4; +T_14.2 ; + %jmp T_14; + .thread T_14; + .scope S_0x23201d0; +T_15 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2323da0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2323fc0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2323b00_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x23206c0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x23207c0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2320c50_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2324550_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2324dc0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2324f80_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2324ce0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2323e80, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2323e80, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2323e80, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2323e80, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x2320400, v0x2323a40 {0 0 0}; + %end; + .thread T_15; + .scope S_0x23201d0; +T_16 ; + %wait E_0x231b3f0; + %load/vec4 v0x2323da0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_16.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_16.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_16.2, 6; + %jmp T_16.3; +T_16.0 ; + %load/vec4 v0x2323fc0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_16.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_16.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_16.6, 6; + %jmp T_16.7; +T_16.4 ; + %load/vec4 v0x2320a40_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_16.8, 5; + %load/vec4 v0x2320e10_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_16.10, 5; + %load/vec4 v0x2320e10_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %jmp T_16.11; +T_16.10 ; + %load/vec4 v0x2320e10_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_16.12, 5; + %load/vec4 v0x23240a0_0; + %load/vec4 v0x2320e10_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_16.14, 8; + %load/vec4 v0x2320e10_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2320e10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %load/vec4 v0x2320e10_0; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.15; +T_16.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %load/vec4 v0x2320e10_0; + %assign/vec4 v0x23245f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2320e10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; + %load/vec4 v0x2320e10_0; + %assign/vec4 v0x2323b00_0, 0; +T_16.15 ; + %jmp T_16.13; +T_16.12 ; + %load/vec4 v0x2320e10_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_16.16, 4; + %load/vec4 v0x2323b00_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_16.18, 4; + %load/vec4 v0x2323b00_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %jmp T_16.19; +T_16.18 ; + %load/vec4 v0x23240a0_0; + %load/vec4 v0x2323b00_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_16.20, 8; + %load/vec4 v0x2323b00_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2323b00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %jmp T_16.21; +T_16.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %load/vec4 v0x2323b00_0; + %assign/vec4 v0x23245f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2323b00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; +T_16.21 ; +T_16.19 ; + %jmp T_16.17; +T_16.16 ; + %load/vec4 v0x2320e10_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_16.22, 4; + %load/vec4 v0x2323420_0; + %flag_set/vec4 8; + %jmp/0xz T_16.24, 8; + %load/vec4 v0x23240a0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.27; +T_16.26 ; + %load/vec4 v0x23240a0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.29; +T_16.28 ; + %load/vec4 v0x23240a0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.31; +T_16.30 ; + %load/vec4 v0x23240a0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2323b00_0, 0; +T_16.32 ; +T_16.31 ; +T_16.29 ; +T_16.27 ; + %jmp T_16.25; +T_16.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %load/vec4 v0x2320e10_0; + %assign/vec4 v0x23245f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; +T_16.25 ; +T_16.22 ; +T_16.17 ; +T_16.13 ; +T_16.11 ; +T_16.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.7; +T_16.5 ; + %load/vec4 v0x2320a40_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_16.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_16.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_16.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_16.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_16.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_16.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_16.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_16.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_16.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_16.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_16.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_16.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_16.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_16.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_16.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_16.49, 6; + %jmp T_16.50; +T_16.34 ; + %load/vec4 v0x23206c0_0; + %load/vec4 v0x2324690_0; + %add; + %assign/vec4 v0x23206c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.35 ; + %load/vec4 v0x23206c0_0; + %load/vec4 v0x2324690_0; + %sub; + %assign/vec4 v0x23206c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.36 ; + %load/vec4 v0x2320c50_0; + %pad/u 11; + %load/vec4 v0x2324690_0; + %add; + %pad/u 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.37 ; + %load/vec4 v0x2324690_0; + %assign/vec4 v0x2325140_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.38 ; + %load/vec4 v0x2320960_0; + %assign/vec4 v0x2325140_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.39 ; + %load/vec4 v0x23206c0_0; + %load/vec4 v0x2320960_0; + %add; + %assign/vec4 v0x23206c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.40 ; + %load/vec4 v0x23206c0_0; + %load/vec4 v0x2320960_0; + %sub; + %assign/vec4 v0x23206c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.41 ; + %load/vec4 v0x2320c50_0; + %pad/u 11; + %load/vec4 v0x2320960_0; + %add; + %pad/u 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.42 ; + %load/vec4 v0x23207c0_0; + %assign/vec4 v0x23206c0_0, 0; + %load/vec4 v0x23206c0_0; + %assign/vec4 v0x23207c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.43 ; + %load/vec4 v0x23206c0_0; + %assign/vec4 v0x23207c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.44 ; + %load/vec4 v0x23206c0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x23206c0_0, 0; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.45 ; + %load/vec4 v0x2320b70_0; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.50; +T_16.46 ; + %load/vec4 v0x23206c0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_16.51, 4; + %load/vec4 v0x2320b70_0; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.52; +T_16.51 ; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; +T_16.52 ; + %jmp T_16.50; +T_16.47 ; + %load/vec4 v0x23206c0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_16.53, 4; + %load/vec4 v0x2320b70_0; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.54; +T_16.53 ; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; +T_16.54 ; + %jmp T_16.50; +T_16.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x23206c0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_16.55, 5; + %load/vec4 v0x2320b70_0; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.56; +T_16.55 ; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; +T_16.56 ; + %jmp T_16.50; +T_16.49 ; + %load/vec4 v0x23206c0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_16.57, 5; + %load/vec4 v0x2320b70_0; + %assign/vec4 v0x2320d30_0, 0; + %jmp T_16.58; +T_16.57 ; + %load/vec4 v0x2320c50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2320d30_0, 0; +T_16.58 ; + %jmp T_16.50; +T_16.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.7; +T_16.6 ; + %load/vec4 v0x2320a40_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x2320a40_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_16.59, 4; + %load/vec4 v0x23208a0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x23208a0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2323b00_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_16.61, 9; + %load/vec4 v0x23208a0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_16.63, 4; + %load/vec4 v0x2325140_0; + %assign/vec4 v0x23206c0_0, 0; +T_16.63 ; + %jmp T_16.62; +T_16.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %load/vec4 v0x23208a0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_16.65, 4; + %load/vec4 v0x2323b00_0; + %assign/vec4 v0x2325060_0, 0; + %load/vec4 v0x2325140_0; + %load/vec4 v0x2323b00_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2323b00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %jmp T_16.66; +T_16.65 ; + %load/vec4 v0x23208a0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_16.67, 4; + %load/vec4 v0x23208a0_0; + %assign/vec4 v0x2325060_0, 0; + %load/vec4 v0x2325140_0; + %load/vec4 v0x23208a0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23208a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x23208a0_0; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.68; +T_16.67 ; + %load/vec4 v0x23235a0_0; + %flag_set/vec4 8; + %jmp/0xz T_16.69, 8; + %load/vec4 v0x23224d0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.72; +T_16.71 ; + %load/vec4 v0x23224d0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.74; +T_16.73 ; + %load/vec4 v0x23224d0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.76; +T_16.75 ; + %load/vec4 v0x23224d0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2323b00_0, 0; +T_16.77 ; +T_16.76 ; +T_16.74 ; +T_16.72 ; + %jmp T_16.70; +T_16.69 ; + %load/vec4 v0x23208a0_0; + %assign/vec4 v0x2325060_0, 0; +T_16.70 ; +T_16.68 ; +T_16.66 ; +T_16.62 ; +T_16.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.7; +T_16.7 ; + %pop/vec4 1; + %jmp T_16.3; +T_16.1 ; + %load/vec4 v0x2323fc0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_16.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_16.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_16.81, 6; + %jmp T_16.82; +T_16.79 ; + %load/vec4 v0x23245f0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_16.83, 4; + %load/vec4 v0x2323420_0; + %flag_set/vec4 8; + %jmp/0xz T_16.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2324dc0_0, 0, 4; + %load/vec4 v0x23240a0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.88; +T_16.87 ; + %load/vec4 v0x23240a0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.90; +T_16.89 ; + %load/vec4 v0x23240a0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.92; +T_16.91 ; + %load/vec4 v0x23240a0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2323b00_0, 0; +T_16.93 ; +T_16.92 ; +T_16.90 ; +T_16.88 ; +T_16.85 ; + %jmp T_16.84; +T_16.83 ; + %load/vec4 v0x23240a0_0; + %load/vec4 v0x23245f0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_16.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %load/vec4 v0x23245f0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2324770, 4; + %assign/vec4 v0x2324690_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23245f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324550_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23245f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2324dc0_0, 4, 5; + %load/vec4 v0x23245f0_0; + %assign/vec4 v0x2323b00_0, 0; +T_16.95 ; +T_16.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.82; +T_16.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.82; +T_16.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.82; +T_16.82 ; + %pop/vec4 1; + %jmp T_16.3; +T_16.2 ; + %load/vec4 v0x2323fc0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_16.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_16.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_16.99, 6; + %jmp T_16.100; +T_16.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.100; +T_16.98 ; + %load/vec4 v0x2325060_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_16.101, 4; + %load/vec4 v0x23235a0_0; + %flag_set/vec4 8; + %jmp/0xz T_16.103, 8; + %load/vec4 v0x23224d0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.106; +T_16.105 ; + %load/vec4 v0x23224d0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.108; +T_16.107 ; + %load/vec4 v0x23224d0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_16.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2323b00_0, 0; + %jmp T_16.110; +T_16.109 ; + %load/vec4 v0x23224d0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_16.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2325060_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2324ce0_0, 4, 5; + %load/vec4 v0x2325140_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2323e80, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2323b00_0, 0; +T_16.111 ; +T_16.110 ; +T_16.108 ; +T_16.106 ; +T_16.103 ; +T_16.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.100; +T_16.99 ; + %load/vec4 v0x2325060_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_16.113, 4; + %load/vec4 v0x2324ea0_0; + %load/vec4 v0x2325060_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_16.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x2325060_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2324ce0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2323da0_0, 0; + %load/vec4 v0x2325060_0; + %assign/vec4 v0x2323b00_0, 0; +T_16.115 ; +T_16.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2323fc0_0, 0; + %jmp T_16.100; +T_16.100 ; + %pop/vec4 1; + %jmp T_16.3; +T_16.3 ; + %pop/vec4 1; + %jmp T_16; + .thread T_16; + .scope S_0x23201d0; +T_17 ; + %wait E_0x231b1f0; + %load/vec4 v0x2323fc0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2323da0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x2320d30_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_17.0, 8; + %load/vec4 v0x2320d30_0; + %assign/vec4 v0x2320c50_0, 0; +T_17.0 ; + %load/vec4 v0x2323fc0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_17.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2324550_0, 0, 4; +T_17.2 ; + %jmp T_17; + .thread T_17; + .scope S_0x231ae90; +T_18 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x231eb70_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x231ed90_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x231e8d0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x231b450_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x231b550_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231b9e0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231f320_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231fbd0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231fd90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231faf0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x231ec50, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x231ec50, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x231ec50, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x231ec50, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x231b0a0, v0x231e810 {0 0 0}; + %end; + .thread T_18; + .scope S_0x231ae90; +T_19 ; + %wait E_0x231b3f0; + %load/vec4 v0x231eb70_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_19.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_19.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_19.2, 6; + %jmp T_19.3; +T_19.0 ; + %load/vec4 v0x231ed90_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_19.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_19.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_19.6, 6; + %jmp T_19.7; +T_19.4 ; + %load/vec4 v0x231b7d0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_19.8, 5; + %load/vec4 v0x231bba0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_19.10, 5; + %load/vec4 v0x231bba0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %jmp T_19.11; +T_19.10 ; + %load/vec4 v0x231bba0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_19.12, 5; + %load/vec4 v0x231ee70_0; + %load/vec4 v0x231bba0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_19.14, 8; + %load/vec4 v0x231bba0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231bba0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %load/vec4 v0x231bba0_0; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.15; +T_19.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %load/vec4 v0x231bba0_0; + %assign/vec4 v0x231f3c0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231bba0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; + %load/vec4 v0x231bba0_0; + %assign/vec4 v0x231e8d0_0, 0; +T_19.15 ; + %jmp T_19.13; +T_19.12 ; + %load/vec4 v0x231bba0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_19.16, 4; + %load/vec4 v0x231e8d0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_19.18, 4; + %load/vec4 v0x231e8d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %jmp T_19.19; +T_19.18 ; + %load/vec4 v0x231ee70_0; + %load/vec4 v0x231e8d0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_19.20, 8; + %load/vec4 v0x231e8d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231e8d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %jmp T_19.21; +T_19.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %load/vec4 v0x231e8d0_0; + %assign/vec4 v0x231f3c0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231e8d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; +T_19.21 ; +T_19.19 ; + %jmp T_19.17; +T_19.16 ; + %load/vec4 v0x231bba0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_19.22, 4; + %load/vec4 v0x231e1b0_0; + %flag_set/vec4 8; + %jmp/0xz T_19.24, 8; + %load/vec4 v0x231ee70_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.27; +T_19.26 ; + %load/vec4 v0x231ee70_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.29; +T_19.28 ; + %load/vec4 v0x231ee70_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.31; +T_19.30 ; + %load/vec4 v0x231ee70_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; +T_19.32 ; +T_19.31 ; +T_19.29 ; +T_19.27 ; + %jmp T_19.25; +T_19.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %load/vec4 v0x231bba0_0; + %assign/vec4 v0x231f3c0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; +T_19.25 ; +T_19.22 ; +T_19.17 ; +T_19.13 ; +T_19.11 ; +T_19.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.7; +T_19.5 ; + %load/vec4 v0x231b7d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_19.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_19.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_19.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_19.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_19.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_19.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_19.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_19.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_19.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_19.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_19.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_19.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_19.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_19.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_19.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_19.49, 6; + %jmp T_19.50; +T_19.34 ; + %load/vec4 v0x231b450_0; + %load/vec4 v0x231f480_0; + %add; + %assign/vec4 v0x231b450_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.35 ; + %load/vec4 v0x231b450_0; + %load/vec4 v0x231f480_0; + %sub; + %assign/vec4 v0x231b450_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.36 ; + %load/vec4 v0x231b9e0_0; + %pad/u 11; + %load/vec4 v0x231f480_0; + %add; + %pad/u 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.37 ; + %load/vec4 v0x231f480_0; + %assign/vec4 v0x231ff50_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.38 ; + %load/vec4 v0x231b6f0_0; + %assign/vec4 v0x231ff50_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.39 ; + %load/vec4 v0x231b450_0; + %load/vec4 v0x231b6f0_0; + %add; + %assign/vec4 v0x231b450_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.40 ; + %load/vec4 v0x231b450_0; + %load/vec4 v0x231b6f0_0; + %sub; + %assign/vec4 v0x231b450_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.41 ; + %load/vec4 v0x231b9e0_0; + %pad/u 11; + %load/vec4 v0x231b6f0_0; + %add; + %pad/u 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.42 ; + %load/vec4 v0x231b550_0; + %assign/vec4 v0x231b450_0, 0; + %load/vec4 v0x231b450_0; + %assign/vec4 v0x231b550_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.43 ; + %load/vec4 v0x231b450_0; + %assign/vec4 v0x231b550_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.44 ; + %load/vec4 v0x231b450_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x231b450_0, 0; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.45 ; + %load/vec4 v0x231b900_0; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.50; +T_19.46 ; + %load/vec4 v0x231b450_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_19.51, 4; + %load/vec4 v0x231b900_0; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.52; +T_19.51 ; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; +T_19.52 ; + %jmp T_19.50; +T_19.47 ; + %load/vec4 v0x231b450_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_19.53, 4; + %load/vec4 v0x231b900_0; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.54; +T_19.53 ; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; +T_19.54 ; + %jmp T_19.50; +T_19.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x231b450_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_19.55, 5; + %load/vec4 v0x231b900_0; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.56; +T_19.55 ; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; +T_19.56 ; + %jmp T_19.50; +T_19.49 ; + %load/vec4 v0x231b450_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_19.57, 5; + %load/vec4 v0x231b900_0; + %assign/vec4 v0x231bac0_0, 0; + %jmp T_19.58; +T_19.57 ; + %load/vec4 v0x231b9e0_0; + %addi 1, 0, 4; + %assign/vec4 v0x231bac0_0, 0; +T_19.58 ; + %jmp T_19.50; +T_19.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.7; +T_19.6 ; + %load/vec4 v0x231b7d0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x231b7d0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_19.59, 4; + %load/vec4 v0x231b630_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x231b630_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x231e8d0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_19.61, 9; + %load/vec4 v0x231b630_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_19.63, 4; + %load/vec4 v0x231ff50_0; + %assign/vec4 v0x231b450_0, 0; +T_19.63 ; + %jmp T_19.62; +T_19.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %load/vec4 v0x231b630_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_19.65, 4; + %load/vec4 v0x231e8d0_0; + %assign/vec4 v0x231fe70_0, 0; + %load/vec4 v0x231ff50_0; + %load/vec4 v0x231e8d0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231e8d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %jmp T_19.66; +T_19.65 ; + %load/vec4 v0x231b630_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_19.67, 4; + %load/vec4 v0x231b630_0; + %assign/vec4 v0x231fe70_0, 0; + %load/vec4 v0x231ff50_0; + %load/vec4 v0x231b630_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231b630_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231b630_0; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.68; +T_19.67 ; + %load/vec4 v0x231e330_0; + %flag_set/vec4 8; + %jmp/0xz T_19.69, 8; + %load/vec4 v0x231d260_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.72; +T_19.71 ; + %load/vec4 v0x231d260_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.74; +T_19.73 ; + %load/vec4 v0x231d260_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.76; +T_19.75 ; + %load/vec4 v0x231d260_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; +T_19.77 ; +T_19.76 ; +T_19.74 ; +T_19.72 ; + %jmp T_19.70; +T_19.69 ; + %load/vec4 v0x231b630_0; + %assign/vec4 v0x231fe70_0, 0; +T_19.70 ; +T_19.68 ; +T_19.66 ; +T_19.62 ; +T_19.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.7; +T_19.7 ; + %pop/vec4 1; + %jmp T_19.3; +T_19.1 ; + %load/vec4 v0x231ed90_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_19.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_19.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_19.81, 6; + %jmp T_19.82; +T_19.79 ; + %load/vec4 v0x231f3c0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_19.83, 4; + %load/vec4 v0x231e1b0_0; + %flag_set/vec4 8; + %jmp/0xz T_19.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231fbd0_0, 0, 4; + %load/vec4 v0x231ee70_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.88; +T_19.87 ; + %load/vec4 v0x231ee70_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.90; +T_19.89 ; + %load/vec4 v0x231ee70_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.92; +T_19.91 ; + %load/vec4 v0x231ee70_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; +T_19.93 ; +T_19.92 ; +T_19.90 ; +T_19.88 ; +T_19.85 ; + %jmp T_19.84; +T_19.83 ; + %load/vec4 v0x231ee70_0; + %load/vec4 v0x231f3c0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_19.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %load/vec4 v0x231f3c0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x231f560, 4; + %assign/vec4 v0x231f480_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231f3c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231f320_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x231f3c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x231fbd0_0, 4, 5; + %load/vec4 v0x231f3c0_0; + %assign/vec4 v0x231e8d0_0, 0; +T_19.95 ; +T_19.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.82; +T_19.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.82; +T_19.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.82; +T_19.82 ; + %pop/vec4 1; + %jmp T_19.3; +T_19.2 ; + %load/vec4 v0x231ed90_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_19.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_19.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_19.99, 6; + %jmp T_19.100; +T_19.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.100; +T_19.98 ; + %load/vec4 v0x231fe70_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_19.101, 4; + %load/vec4 v0x231e330_0; + %flag_set/vec4 8; + %jmp/0xz T_19.103, 8; + %load/vec4 v0x231d260_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.106; +T_19.105 ; + %load/vec4 v0x231d260_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.108; +T_19.107 ; + %load/vec4 v0x231d260_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_19.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; + %jmp T_19.110; +T_19.109 ; + %load/vec4 v0x231d260_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_19.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x231fe70_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x231faf0_0, 4, 5; + %load/vec4 v0x231ff50_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x231ec50, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x231e8d0_0, 0; +T_19.111 ; +T_19.110 ; +T_19.108 ; +T_19.106 ; +T_19.103 ; +T_19.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.100; +T_19.99 ; + %load/vec4 v0x231fe70_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_19.113, 4; + %load/vec4 v0x231fcb0_0; + %load/vec4 v0x231fe70_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_19.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x231fe70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x231faf0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x231eb70_0, 0; + %load/vec4 v0x231fe70_0; + %assign/vec4 v0x231e8d0_0, 0; +T_19.115 ; +T_19.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x231ed90_0, 0; + %jmp T_19.100; +T_19.100 ; + %pop/vec4 1; + %jmp T_19.3; +T_19.3 ; + %pop/vec4 1; + %jmp T_19; + .thread T_19; + .scope S_0x231ae90; +T_20 ; + %wait E_0x231b1f0; + %load/vec4 v0x231ed90_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x231eb70_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x231bac0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_20.0, 8; + %load/vec4 v0x231bac0_0; + %assign/vec4 v0x231b9e0_0, 0; +T_20.0 ; + %load/vec4 v0x231ed90_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_20.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x231f320_0, 0, 4; +T_20.2 ; + %jmp T_20; + .thread T_20; + .scope S_0x2339c40; +T_21 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x233d7b0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x233da00_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x233d510_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x233a130_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x233a230_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233a6c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233df90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233e800_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233e9c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233e720_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x233d890, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x233d890, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x233d890, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x233d890, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x2339e50, v0x233d450 {0 0 0}; + %end; + .thread T_21; + .scope S_0x2339c40; +T_22 ; + %wait E_0x231b3f0; + %load/vec4 v0x233d7b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_22.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_22.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_22.2, 6; + %jmp T_22.3; +T_22.0 ; + %load/vec4 v0x233da00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_22.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_22.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_22.6, 6; + %jmp T_22.7; +T_22.4 ; + %load/vec4 v0x233a4b0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_22.8, 5; + %load/vec4 v0x233a880_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_22.10, 5; + %load/vec4 v0x233a880_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %jmp T_22.11; +T_22.10 ; + %load/vec4 v0x233a880_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_22.12, 5; + %load/vec4 v0x233dae0_0; + %load/vec4 v0x233a880_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_22.14, 8; + %load/vec4 v0x233a880_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233a880_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %load/vec4 v0x233a880_0; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.15; +T_22.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %load/vec4 v0x233a880_0; + %assign/vec4 v0x233e030_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233a880_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233e800_0, 4, 5; + %load/vec4 v0x233a880_0; + %assign/vec4 v0x233d510_0, 0; +T_22.15 ; + %jmp T_22.13; +T_22.12 ; + %load/vec4 v0x233a880_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_22.16, 4; + %load/vec4 v0x233d510_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_22.18, 4; + %load/vec4 v0x233d510_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %jmp T_22.19; +T_22.18 ; + %load/vec4 v0x233dae0_0; + %load/vec4 v0x233d510_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_22.20, 8; + %load/vec4 v0x233d510_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233d510_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %jmp T_22.21; +T_22.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %load/vec4 v0x233d510_0; + %assign/vec4 v0x233e030_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233d510_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233e800_0, 4, 5; +T_22.21 ; +T_22.19 ; + %jmp T_22.17; +T_22.16 ; + %load/vec4 v0x233a880_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_22.22, 4; + %load/vec4 v0x233ce90_0; + %flag_set/vec4 8; + %jmp/0xz T_22.24, 8; + %load/vec4 v0x233dae0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.27; +T_22.26 ; + %load/vec4 v0x233dae0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.29; +T_22.28 ; + %load/vec4 v0x233dae0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.31; +T_22.30 ; + %load/vec4 v0x233dae0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x233d510_0, 0; +T_22.32 ; +T_22.31 ; +T_22.29 ; +T_22.27 ; + %jmp T_22.25; +T_22.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %load/vec4 v0x233a880_0; + %assign/vec4 v0x233e030_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e800_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e800_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e800_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e800_0, 4, 5; +T_22.25 ; +T_22.22 ; +T_22.17 ; +T_22.13 ; +T_22.11 ; +T_22.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.7; +T_22.5 ; + %load/vec4 v0x233a4b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_22.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_22.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_22.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_22.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_22.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_22.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_22.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_22.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_22.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_22.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_22.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_22.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_22.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_22.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_22.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_22.49, 6; + %jmp T_22.50; +T_22.34 ; + %load/vec4 v0x233a130_0; + %load/vec4 v0x233e0d0_0; + %add; + %assign/vec4 v0x233a130_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.35 ; + %load/vec4 v0x233a130_0; + %load/vec4 v0x233e0d0_0; + %sub; + %assign/vec4 v0x233a130_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.36 ; + %load/vec4 v0x233a6c0_0; + %pad/u 11; + %load/vec4 v0x233e0d0_0; + %add; + %pad/u 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.37 ; + %load/vec4 v0x233e0d0_0; + %assign/vec4 v0x233eb80_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.38 ; + %load/vec4 v0x233a3d0_0; + %assign/vec4 v0x233eb80_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.39 ; + %load/vec4 v0x233a130_0; + %load/vec4 v0x233a3d0_0; + %add; + %assign/vec4 v0x233a130_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.40 ; + %load/vec4 v0x233a130_0; + %load/vec4 v0x233a3d0_0; + %sub; + %assign/vec4 v0x233a130_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.41 ; + %load/vec4 v0x233a6c0_0; + %pad/u 11; + %load/vec4 v0x233a3d0_0; + %add; + %pad/u 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.42 ; + %load/vec4 v0x233a230_0; + %assign/vec4 v0x233a130_0, 0; + %load/vec4 v0x233a130_0; + %assign/vec4 v0x233a230_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.43 ; + %load/vec4 v0x233a130_0; + %assign/vec4 v0x233a230_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.44 ; + %load/vec4 v0x233a130_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x233a130_0, 0; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.45 ; + %load/vec4 v0x233a5e0_0; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.50; +T_22.46 ; + %load/vec4 v0x233a130_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_22.51, 4; + %load/vec4 v0x233a5e0_0; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.52; +T_22.51 ; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; +T_22.52 ; + %jmp T_22.50; +T_22.47 ; + %load/vec4 v0x233a130_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_22.53, 4; + %load/vec4 v0x233a5e0_0; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.54; +T_22.53 ; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; +T_22.54 ; + %jmp T_22.50; +T_22.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x233a130_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_22.55, 5; + %load/vec4 v0x233a5e0_0; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.56; +T_22.55 ; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; +T_22.56 ; + %jmp T_22.50; +T_22.49 ; + %load/vec4 v0x233a130_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_22.57, 5; + %load/vec4 v0x233a5e0_0; + %assign/vec4 v0x233a7a0_0, 0; + %jmp T_22.58; +T_22.57 ; + %load/vec4 v0x233a6c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x233a7a0_0, 0; +T_22.58 ; + %jmp T_22.50; +T_22.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.7; +T_22.6 ; + %load/vec4 v0x233a4b0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x233a4b0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_22.59, 4; + %load/vec4 v0x233a310_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x233a310_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x233d510_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_22.61, 9; + %load/vec4 v0x233a310_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_22.63, 4; + %load/vec4 v0x233eb80_0; + %assign/vec4 v0x233a130_0, 0; +T_22.63 ; + %jmp T_22.62; +T_22.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %load/vec4 v0x233a310_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_22.65, 4; + %load/vec4 v0x233d510_0; + %assign/vec4 v0x233eaa0_0, 0; + %load/vec4 v0x233eb80_0; + %load/vec4 v0x233d510_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233d510_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %jmp T_22.66; +T_22.65 ; + %load/vec4 v0x233a310_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_22.67, 4; + %load/vec4 v0x233a310_0; + %assign/vec4 v0x233eaa0_0, 0; + %load/vec4 v0x233eb80_0; + %load/vec4 v0x233a310_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233a310_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233a310_0; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.68; +T_22.67 ; + %load/vec4 v0x233d010_0; + %flag_set/vec4 8; + %jmp/0xz T_22.69, 8; + %load/vec4 v0x233bf40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.72; +T_22.71 ; + %load/vec4 v0x233bf40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.74; +T_22.73 ; + %load/vec4 v0x233bf40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.76; +T_22.75 ; + %load/vec4 v0x233bf40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x233d510_0, 0; +T_22.77 ; +T_22.76 ; +T_22.74 ; +T_22.72 ; + %jmp T_22.70; +T_22.69 ; + %load/vec4 v0x233a310_0; + %assign/vec4 v0x233eaa0_0, 0; +T_22.70 ; +T_22.68 ; +T_22.66 ; +T_22.62 ; +T_22.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.7; +T_22.7 ; + %pop/vec4 1; + %jmp T_22.3; +T_22.1 ; + %load/vec4 v0x233da00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_22.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_22.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_22.81, 6; + %jmp T_22.82; +T_22.79 ; + %load/vec4 v0x233e030_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_22.83, 4; + %load/vec4 v0x233ce90_0; + %flag_set/vec4 8; + %jmp/0xz T_22.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233e800_0, 0, 4; + %load/vec4 v0x233dae0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.88; +T_22.87 ; + %load/vec4 v0x233dae0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.90; +T_22.89 ; + %load/vec4 v0x233dae0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.92; +T_22.91 ; + %load/vec4 v0x233dae0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x233d510_0, 0; +T_22.93 ; +T_22.92 ; +T_22.90 ; +T_22.88 ; +T_22.85 ; + %jmp T_22.84; +T_22.83 ; + %load/vec4 v0x233dae0_0; + %load/vec4 v0x233e030_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_22.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %load/vec4 v0x233e030_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x233e1b0, 4; + %assign/vec4 v0x233e0d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233e030_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233df90_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x233e030_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x233e800_0, 4, 5; + %load/vec4 v0x233e030_0; + %assign/vec4 v0x233d510_0, 0; +T_22.95 ; +T_22.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.82; +T_22.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.82; +T_22.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.82; +T_22.82 ; + %pop/vec4 1; + %jmp T_22.3; +T_22.2 ; + %load/vec4 v0x233da00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_22.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_22.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_22.99, 6; + %jmp T_22.100; +T_22.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.100; +T_22.98 ; + %load/vec4 v0x233eaa0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_22.101, 4; + %load/vec4 v0x233d010_0; + %flag_set/vec4 8; + %jmp/0xz T_22.103, 8; + %load/vec4 v0x233bf40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.106; +T_22.105 ; + %load/vec4 v0x233bf40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.108; +T_22.107 ; + %load/vec4 v0x233bf40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_22.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x233d510_0, 0; + %jmp T_22.110; +T_22.109 ; + %load/vec4 v0x233bf40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_22.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x233eaa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x233e720_0, 4, 5; + %load/vec4 v0x233eb80_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x233d890, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x233d510_0, 0; +T_22.111 ; +T_22.110 ; +T_22.108 ; +T_22.106 ; +T_22.103 ; +T_22.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.100; +T_22.99 ; + %load/vec4 v0x233eaa0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_22.113, 4; + %load/vec4 v0x233e8e0_0; + %load/vec4 v0x233eaa0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_22.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x233eaa0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x233e720_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x233d7b0_0, 0; + %load/vec4 v0x233eaa0_0; + %assign/vec4 v0x233d510_0, 0; +T_22.115 ; +T_22.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x233da00_0, 0; + %jmp T_22.100; +T_22.100 ; + %pop/vec4 1; + %jmp T_22.3; +T_22.3 ; + %pop/vec4 1; + %jmp T_22; + .thread T_22; + .scope S_0x2339c40; +T_23 ; + %wait E_0x231b1f0; + %load/vec4 v0x233da00_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x233d7b0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x233a7a0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_23.0, 8; + %load/vec4 v0x233a7a0_0; + %assign/vec4 v0x233a6c0_0, 0; +T_23.0 ; + %load/vec4 v0x233da00_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_23.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x233df90_0, 0, 4; +T_23.2 ; + %jmp T_23; + .thread T_23; + .scope S_0x2334a50; +T_24 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2338640_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2338860_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x23383a0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x2334f40_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x2335040_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x23354d0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2338df0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2339640_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2339800_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2339580_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2338720, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2338720, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2338720, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2338720, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x2334c60, v0x23382e0 {0 0 0}; + %end; + .thread T_24; + .scope S_0x2334a50; +T_25 ; + %wait E_0x231b3f0; + %load/vec4 v0x2338640_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_25.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_25.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_25.2, 6; + %jmp T_25.3; +T_25.0 ; + %load/vec4 v0x2338860_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_25.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_25.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_25.6, 6; + %jmp T_25.7; +T_25.4 ; + %load/vec4 v0x23352c0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_25.8, 5; + %load/vec4 v0x2335690_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_25.10, 5; + %load/vec4 v0x2335690_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %jmp T_25.11; +T_25.10 ; + %load/vec4 v0x2335690_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_25.12, 5; + %load/vec4 v0x2338940_0; + %load/vec4 v0x2335690_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_25.14, 8; + %load/vec4 v0x2335690_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2335690_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %load/vec4 v0x2335690_0; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.15; +T_25.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %load/vec4 v0x2335690_0; + %assign/vec4 v0x2338e90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2335690_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2339640_0, 4, 5; + %load/vec4 v0x2335690_0; + %assign/vec4 v0x23383a0_0, 0; +T_25.15 ; + %jmp T_25.13; +T_25.12 ; + %load/vec4 v0x2335690_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_25.16, 4; + %load/vec4 v0x23383a0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_25.18, 4; + %load/vec4 v0x23383a0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %jmp T_25.19; +T_25.18 ; + %load/vec4 v0x2338940_0; + %load/vec4 v0x23383a0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_25.20, 8; + %load/vec4 v0x23383a0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23383a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %jmp T_25.21; +T_25.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %load/vec4 v0x23383a0_0; + %assign/vec4 v0x2338e90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23383a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2339640_0, 4, 5; +T_25.21 ; +T_25.19 ; + %jmp T_25.17; +T_25.16 ; + %load/vec4 v0x2335690_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_25.22, 4; + %load/vec4 v0x2337ca0_0; + %flag_set/vec4 8; + %jmp/0xz T_25.24, 8; + %load/vec4 v0x2338940_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.27; +T_25.26 ; + %load/vec4 v0x2338940_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.29; +T_25.28 ; + %load/vec4 v0x2338940_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.31; +T_25.30 ; + %load/vec4 v0x2338940_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23383a0_0, 0; +T_25.32 ; +T_25.31 ; +T_25.29 ; +T_25.27 ; + %jmp T_25.25; +T_25.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %load/vec4 v0x2335690_0; + %assign/vec4 v0x2338e90_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339640_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339640_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339640_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339640_0, 4, 5; +T_25.25 ; +T_25.22 ; +T_25.17 ; +T_25.13 ; +T_25.11 ; +T_25.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.7; +T_25.5 ; + %load/vec4 v0x23352c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_25.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_25.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_25.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_25.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_25.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_25.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_25.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_25.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_25.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_25.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_25.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_25.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_25.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_25.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_25.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_25.49, 6; + %jmp T_25.50; +T_25.34 ; + %load/vec4 v0x2334f40_0; + %load/vec4 v0x2338f30_0; + %add; + %assign/vec4 v0x2334f40_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.35 ; + %load/vec4 v0x2334f40_0; + %load/vec4 v0x2338f30_0; + %sub; + %assign/vec4 v0x2334f40_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.36 ; + %load/vec4 v0x23354d0_0; + %pad/u 11; + %load/vec4 v0x2338f30_0; + %add; + %pad/u 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.37 ; + %load/vec4 v0x2338f30_0; + %assign/vec4 v0x23399c0_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.38 ; + %load/vec4 v0x23351e0_0; + %assign/vec4 v0x23399c0_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.39 ; + %load/vec4 v0x2334f40_0; + %load/vec4 v0x23351e0_0; + %add; + %assign/vec4 v0x2334f40_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.40 ; + %load/vec4 v0x2334f40_0; + %load/vec4 v0x23351e0_0; + %sub; + %assign/vec4 v0x2334f40_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.41 ; + %load/vec4 v0x23354d0_0; + %pad/u 11; + %load/vec4 v0x23351e0_0; + %add; + %pad/u 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.42 ; + %load/vec4 v0x2335040_0; + %assign/vec4 v0x2334f40_0, 0; + %load/vec4 v0x2334f40_0; + %assign/vec4 v0x2335040_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.43 ; + %load/vec4 v0x2334f40_0; + %assign/vec4 v0x2335040_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.44 ; + %load/vec4 v0x2334f40_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x2334f40_0, 0; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.45 ; + %load/vec4 v0x23353f0_0; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.50; +T_25.46 ; + %load/vec4 v0x2334f40_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_25.51, 4; + %load/vec4 v0x23353f0_0; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.52; +T_25.51 ; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; +T_25.52 ; + %jmp T_25.50; +T_25.47 ; + %load/vec4 v0x2334f40_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_25.53, 4; + %load/vec4 v0x23353f0_0; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.54; +T_25.53 ; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; +T_25.54 ; + %jmp T_25.50; +T_25.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x2334f40_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_25.55, 5; + %load/vec4 v0x23353f0_0; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.56; +T_25.55 ; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; +T_25.56 ; + %jmp T_25.50; +T_25.49 ; + %load/vec4 v0x2334f40_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_25.57, 5; + %load/vec4 v0x23353f0_0; + %assign/vec4 v0x23355b0_0, 0; + %jmp T_25.58; +T_25.57 ; + %load/vec4 v0x23354d0_0; + %addi 1, 0, 4; + %assign/vec4 v0x23355b0_0, 0; +T_25.58 ; + %jmp T_25.50; +T_25.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.7; +T_25.6 ; + %load/vec4 v0x23352c0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x23352c0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_25.59, 4; + %load/vec4 v0x2335120_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x2335120_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x23383a0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_25.61, 9; + %load/vec4 v0x2335120_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_25.63, 4; + %load/vec4 v0x23399c0_0; + %assign/vec4 v0x2334f40_0, 0; +T_25.63 ; + %jmp T_25.62; +T_25.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %load/vec4 v0x2335120_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_25.65, 4; + %load/vec4 v0x23383a0_0; + %assign/vec4 v0x23398e0_0, 0; + %load/vec4 v0x23399c0_0; + %load/vec4 v0x23383a0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23383a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %jmp T_25.66; +T_25.65 ; + %load/vec4 v0x2335120_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_25.67, 4; + %load/vec4 v0x2335120_0; + %assign/vec4 v0x23398e0_0, 0; + %load/vec4 v0x23399c0_0; + %load/vec4 v0x2335120_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2335120_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x2335120_0; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.68; +T_25.67 ; + %load/vec4 v0x2337e20_0; + %flag_set/vec4 8; + %jmp/0xz T_25.69, 8; + %load/vec4 v0x2336d50_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.72; +T_25.71 ; + %load/vec4 v0x2336d50_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.74; +T_25.73 ; + %load/vec4 v0x2336d50_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.76; +T_25.75 ; + %load/vec4 v0x2336d50_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23383a0_0, 0; +T_25.77 ; +T_25.76 ; +T_25.74 ; +T_25.72 ; + %jmp T_25.70; +T_25.69 ; + %load/vec4 v0x2335120_0; + %assign/vec4 v0x23398e0_0, 0; +T_25.70 ; +T_25.68 ; +T_25.66 ; +T_25.62 ; +T_25.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.7; +T_25.7 ; + %pop/vec4 1; + %jmp T_25.3; +T_25.1 ; + %load/vec4 v0x2338860_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_25.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_25.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_25.81, 6; + %jmp T_25.82; +T_25.79 ; + %load/vec4 v0x2338e90_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_25.83, 4; + %load/vec4 v0x2337ca0_0; + %flag_set/vec4 8; + %jmp/0xz T_25.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2339640_0, 0, 4; + %load/vec4 v0x2338940_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.88; +T_25.87 ; + %load/vec4 v0x2338940_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.90; +T_25.89 ; + %load/vec4 v0x2338940_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.92; +T_25.91 ; + %load/vec4 v0x2338940_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23383a0_0, 0; +T_25.93 ; +T_25.92 ; +T_25.90 ; +T_25.88 ; +T_25.85 ; + %jmp T_25.84; +T_25.83 ; + %load/vec4 v0x2338940_0; + %load/vec4 v0x2338e90_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_25.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %load/vec4 v0x2338e90_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2338ff0, 4; + %assign/vec4 v0x2338f30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2338e90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2338df0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2338e90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2339640_0, 4, 5; + %load/vec4 v0x2338e90_0; + %assign/vec4 v0x23383a0_0, 0; +T_25.95 ; +T_25.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.82; +T_25.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.82; +T_25.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.82; +T_25.82 ; + %pop/vec4 1; + %jmp T_25.3; +T_25.2 ; + %load/vec4 v0x2338860_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_25.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_25.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_25.99, 6; + %jmp T_25.100; +T_25.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.100; +T_25.98 ; + %load/vec4 v0x23398e0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_25.101, 4; + %load/vec4 v0x2337e20_0; + %flag_set/vec4 8; + %jmp/0xz T_25.103, 8; + %load/vec4 v0x2336d50_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.106; +T_25.105 ; + %load/vec4 v0x2336d50_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.108; +T_25.107 ; + %load/vec4 v0x2336d50_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_25.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23383a0_0, 0; + %jmp T_25.110; +T_25.109 ; + %load/vec4 v0x2336d50_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_25.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23398e0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2339580_0, 4, 5; + %load/vec4 v0x23399c0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2338720, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23383a0_0, 0; +T_25.111 ; +T_25.110 ; +T_25.108 ; +T_25.106 ; +T_25.103 ; +T_25.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.100; +T_25.99 ; + %load/vec4 v0x23398e0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_25.113, 4; + %load/vec4 v0x2339720_0; + %load/vec4 v0x23398e0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_25.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x23398e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2339580_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2338640_0, 0; + %load/vec4 v0x23398e0_0; + %assign/vec4 v0x23383a0_0, 0; +T_25.115 ; +T_25.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2338860_0, 0; + %jmp T_25.100; +T_25.100 ; + %pop/vec4 1; + %jmp T_25.3; +T_25.3 ; + %pop/vec4 1; + %jmp T_25; + .thread T_25; + .scope S_0x2334a50; +T_26 ; + %wait E_0x231b1f0; + %load/vec4 v0x2338860_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2338640_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x23355b0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_26.0, 8; + %load/vec4 v0x23355b0_0; + %assign/vec4 v0x23354d0_0, 0; +T_26.0 ; + %load/vec4 v0x2338860_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_26.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2338df0_0, 0, 4; +T_26.2 ; + %jmp T_26; + .thread T_26; + .scope S_0x23253c0; +T_27 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2328fc0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x23291e0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2328d20_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x23258c0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x23259c0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2325e50_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2329770_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2329fe0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x232a1a0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2329f00_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x23290a0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x23290a0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x23290a0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x23290a0, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x2325600, v0x2328c60 {0 0 0}; + %end; + .thread T_27; + .scope S_0x23253c0; +T_28 ; + %wait E_0x231b3f0; + %load/vec4 v0x2328fc0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_28.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_28.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_28.2, 6; + %jmp T_28.3; +T_28.0 ; + %load/vec4 v0x23291e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_28.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_28.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_28.6, 6; + %jmp T_28.7; +T_28.4 ; + %load/vec4 v0x2325c40_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_28.8, 5; + %load/vec4 v0x2326010_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_28.10, 5; + %load/vec4 v0x2326010_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %jmp T_28.11; +T_28.10 ; + %load/vec4 v0x2326010_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_28.12, 5; + %load/vec4 v0x23292c0_0; + %load/vec4 v0x2326010_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_28.14, 8; + %load/vec4 v0x2326010_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2326010_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %load/vec4 v0x2326010_0; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.15; +T_28.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %load/vec4 v0x2326010_0; + %assign/vec4 v0x2329810_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2326010_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; + %load/vec4 v0x2326010_0; + %assign/vec4 v0x2328d20_0, 0; +T_28.15 ; + %jmp T_28.13; +T_28.12 ; + %load/vec4 v0x2326010_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_28.16, 4; + %load/vec4 v0x2328d20_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_28.18, 4; + %load/vec4 v0x2328d20_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %jmp T_28.19; +T_28.18 ; + %load/vec4 v0x23292c0_0; + %load/vec4 v0x2328d20_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_28.20, 8; + %load/vec4 v0x2328d20_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2328d20_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %jmp T_28.21; +T_28.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %load/vec4 v0x2328d20_0; + %assign/vec4 v0x2329810_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2328d20_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; +T_28.21 ; +T_28.19 ; + %jmp T_28.17; +T_28.16 ; + %load/vec4 v0x2326010_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_28.22, 4; + %load/vec4 v0x2328620_0; + %flag_set/vec4 8; + %jmp/0xz T_28.24, 8; + %load/vec4 v0x23292c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.27; +T_28.26 ; + %load/vec4 v0x23292c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.29; +T_28.28 ; + %load/vec4 v0x23292c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.31; +T_28.30 ; + %load/vec4 v0x23292c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2328d20_0, 0; +T_28.32 ; +T_28.31 ; +T_28.29 ; +T_28.27 ; + %jmp T_28.25; +T_28.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %load/vec4 v0x2326010_0; + %assign/vec4 v0x2329810_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; +T_28.25 ; +T_28.22 ; +T_28.17 ; +T_28.13 ; +T_28.11 ; +T_28.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.7; +T_28.5 ; + %load/vec4 v0x2325c40_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_28.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_28.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_28.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_28.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_28.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_28.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_28.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_28.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_28.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_28.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_28.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_28.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_28.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_28.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_28.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_28.49, 6; + %jmp T_28.50; +T_28.34 ; + %load/vec4 v0x23258c0_0; + %load/vec4 v0x23298b0_0; + %add; + %assign/vec4 v0x23258c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.35 ; + %load/vec4 v0x23258c0_0; + %load/vec4 v0x23298b0_0; + %sub; + %assign/vec4 v0x23258c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.36 ; + %load/vec4 v0x2325e50_0; + %pad/u 11; + %load/vec4 v0x23298b0_0; + %add; + %pad/u 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.37 ; + %load/vec4 v0x23298b0_0; + %assign/vec4 v0x232a360_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.38 ; + %load/vec4 v0x2325b60_0; + %assign/vec4 v0x232a360_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.39 ; + %load/vec4 v0x23258c0_0; + %load/vec4 v0x2325b60_0; + %add; + %assign/vec4 v0x23258c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.40 ; + %load/vec4 v0x23258c0_0; + %load/vec4 v0x2325b60_0; + %sub; + %assign/vec4 v0x23258c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.41 ; + %load/vec4 v0x2325e50_0; + %pad/u 11; + %load/vec4 v0x2325b60_0; + %add; + %pad/u 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.42 ; + %load/vec4 v0x23259c0_0; + %assign/vec4 v0x23258c0_0, 0; + %load/vec4 v0x23258c0_0; + %assign/vec4 v0x23259c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.43 ; + %load/vec4 v0x23258c0_0; + %assign/vec4 v0x23259c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.44 ; + %load/vec4 v0x23258c0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x23258c0_0, 0; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.45 ; + %load/vec4 v0x2325d70_0; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.50; +T_28.46 ; + %load/vec4 v0x23258c0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_28.51, 4; + %load/vec4 v0x2325d70_0; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.52; +T_28.51 ; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; +T_28.52 ; + %jmp T_28.50; +T_28.47 ; + %load/vec4 v0x23258c0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_28.53, 4; + %load/vec4 v0x2325d70_0; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.54; +T_28.53 ; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; +T_28.54 ; + %jmp T_28.50; +T_28.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x23258c0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_28.55, 5; + %load/vec4 v0x2325d70_0; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.56; +T_28.55 ; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; +T_28.56 ; + %jmp T_28.50; +T_28.49 ; + %load/vec4 v0x23258c0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_28.57, 5; + %load/vec4 v0x2325d70_0; + %assign/vec4 v0x2325f30_0, 0; + %jmp T_28.58; +T_28.57 ; + %load/vec4 v0x2325e50_0; + %addi 1, 0, 4; + %assign/vec4 v0x2325f30_0, 0; +T_28.58 ; + %jmp T_28.50; +T_28.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.7; +T_28.6 ; + %load/vec4 v0x2325c40_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x2325c40_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_28.59, 4; + %load/vec4 v0x2325aa0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x2325aa0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2328d20_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_28.61, 9; + %load/vec4 v0x2325aa0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_28.63, 4; + %load/vec4 v0x232a360_0; + %assign/vec4 v0x23258c0_0, 0; +T_28.63 ; + %jmp T_28.62; +T_28.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %load/vec4 v0x2325aa0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_28.65, 4; + %load/vec4 v0x2328d20_0; + %assign/vec4 v0x232a280_0, 0; + %load/vec4 v0x232a360_0; + %load/vec4 v0x2328d20_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2328d20_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %jmp T_28.66; +T_28.65 ; + %load/vec4 v0x2325aa0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_28.67, 4; + %load/vec4 v0x2325aa0_0; + %assign/vec4 v0x232a280_0, 0; + %load/vec4 v0x232a360_0; + %load/vec4 v0x2325aa0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2325aa0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x2325aa0_0; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.68; +T_28.67 ; + %load/vec4 v0x23287a0_0; + %flag_set/vec4 8; + %jmp/0xz T_28.69, 8; + %load/vec4 v0x23276d0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.72; +T_28.71 ; + %load/vec4 v0x23276d0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.74; +T_28.73 ; + %load/vec4 v0x23276d0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.76; +T_28.75 ; + %load/vec4 v0x23276d0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2328d20_0, 0; +T_28.77 ; +T_28.76 ; +T_28.74 ; +T_28.72 ; + %jmp T_28.70; +T_28.69 ; + %load/vec4 v0x2325aa0_0; + %assign/vec4 v0x232a280_0, 0; +T_28.70 ; +T_28.68 ; +T_28.66 ; +T_28.62 ; +T_28.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.7; +T_28.7 ; + %pop/vec4 1; + %jmp T_28.3; +T_28.1 ; + %load/vec4 v0x23291e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_28.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_28.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_28.81, 6; + %jmp T_28.82; +T_28.79 ; + %load/vec4 v0x2329810_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_28.83, 4; + %load/vec4 v0x2328620_0; + %flag_set/vec4 8; + %jmp/0xz T_28.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2329fe0_0, 0, 4; + %load/vec4 v0x23292c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.88; +T_28.87 ; + %load/vec4 v0x23292c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.90; +T_28.89 ; + %load/vec4 v0x23292c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.92; +T_28.91 ; + %load/vec4 v0x23292c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2328d20_0, 0; +T_28.93 ; +T_28.92 ; +T_28.90 ; +T_28.88 ; +T_28.85 ; + %jmp T_28.84; +T_28.83 ; + %load/vec4 v0x23292c0_0; + %load/vec4 v0x2329810_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_28.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %load/vec4 v0x2329810_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2329970, 4; + %assign/vec4 v0x23298b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2329810_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329770_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2329810_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2329fe0_0, 4, 5; + %load/vec4 v0x2329810_0; + %assign/vec4 v0x2328d20_0, 0; +T_28.95 ; +T_28.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.82; +T_28.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.82; +T_28.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.82; +T_28.82 ; + %pop/vec4 1; + %jmp T_28.3; +T_28.2 ; + %load/vec4 v0x23291e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_28.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_28.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_28.99, 6; + %jmp T_28.100; +T_28.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.100; +T_28.98 ; + %load/vec4 v0x232a280_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_28.101, 4; + %load/vec4 v0x23287a0_0; + %flag_set/vec4 8; + %jmp/0xz T_28.103, 8; + %load/vec4 v0x23276d0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.106; +T_28.105 ; + %load/vec4 v0x23276d0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.108; +T_28.107 ; + %load/vec4 v0x23276d0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_28.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2328d20_0, 0; + %jmp T_28.110; +T_28.109 ; + %load/vec4 v0x23276d0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_28.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x232a280_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2329f00_0, 4, 5; + %load/vec4 v0x232a360_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x23290a0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2328d20_0, 0; +T_28.111 ; +T_28.110 ; +T_28.108 ; +T_28.106 ; +T_28.103 ; +T_28.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.100; +T_28.99 ; + %load/vec4 v0x232a280_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_28.113, 4; + %load/vec4 v0x232a0c0_0; + %load/vec4 v0x232a280_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_28.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x232a280_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2329f00_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2328fc0_0, 0; + %load/vec4 v0x232a280_0; + %assign/vec4 v0x2328d20_0, 0; +T_28.115 ; +T_28.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x23291e0_0, 0; + %jmp T_28.100; +T_28.100 ; + %pop/vec4 1; + %jmp T_28.3; +T_28.3 ; + %pop/vec4 1; + %jmp T_28; + .thread T_28; + .scope S_0x23253c0; +T_29 ; + %wait E_0x231b1f0; + %load/vec4 v0x23291e0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2328fc0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x2325f30_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_29.0, 8; + %load/vec4 v0x2325f30_0; + %assign/vec4 v0x2325e50_0, 0; +T_29.0 ; + %load/vec4 v0x23291e0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_29.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2329770_0, 0, 4; +T_29.2 ; + %jmp T_29; + .thread T_29; + .scope S_0x232f7c0; +T_30 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2333470_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2333690_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x23331d0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x232fce0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x232fde0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2330270_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2333c20_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2334450_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2334610_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2334370_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2333550, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2333550, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2333550, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2333550, 4, 0; + %vpi_call 4 187 "$readmemb", P_0x232fa20, v0x2333110 {0 0 0}; + %end; + .thread T_30; + .scope S_0x232f7c0; +T_31 ; + %wait E_0x231b3f0; + %load/vec4 v0x2333470_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_31.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_31.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_31.2, 6; + %jmp T_31.3; +T_31.0 ; + %load/vec4 v0x2333690_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_31.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_31.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_31.6, 6; + %jmp T_31.7; +T_31.4 ; + %load/vec4 v0x2330060_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_31.8, 5; + %load/vec4 v0x2330430_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_31.10, 5; + %load/vec4 v0x2330430_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %jmp T_31.11; +T_31.10 ; + %load/vec4 v0x2330430_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_31.12, 5; + %load/vec4 v0x2333770_0; + %load/vec4 v0x2330430_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_31.14, 8; + %load/vec4 v0x2330430_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2330430_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %load/vec4 v0x2330430_0; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.15; +T_31.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %load/vec4 v0x2330430_0; + %assign/vec4 v0x2333cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2330430_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2334450_0, 4, 5; + %load/vec4 v0x2330430_0; + %assign/vec4 v0x23331d0_0, 0; +T_31.15 ; + %jmp T_31.13; +T_31.12 ; + %load/vec4 v0x2330430_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_31.16, 4; + %load/vec4 v0x23331d0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_31.18, 4; + %load/vec4 v0x23331d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %jmp T_31.19; +T_31.18 ; + %load/vec4 v0x2333770_0; + %load/vec4 v0x23331d0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_31.20, 8; + %load/vec4 v0x23331d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23331d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %jmp T_31.21; +T_31.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %load/vec4 v0x23331d0_0; + %assign/vec4 v0x2333cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23331d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2334450_0, 4, 5; +T_31.21 ; +T_31.19 ; + %jmp T_31.17; +T_31.16 ; + %load/vec4 v0x2330430_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_31.22, 4; + %load/vec4 v0x2332a40_0; + %flag_set/vec4 8; + %jmp/0xz T_31.24, 8; + %load/vec4 v0x2333770_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.27; +T_31.26 ; + %load/vec4 v0x2333770_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.29; +T_31.28 ; + %load/vec4 v0x2333770_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.31; +T_31.30 ; + %load/vec4 v0x2333770_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23331d0_0, 0; +T_31.32 ; +T_31.31 ; +T_31.29 ; +T_31.27 ; + %jmp T_31.25; +T_31.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %load/vec4 v0x2330430_0; + %assign/vec4 v0x2333cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334450_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334450_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334450_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334450_0, 4, 5; +T_31.25 ; +T_31.22 ; +T_31.17 ; +T_31.13 ; +T_31.11 ; +T_31.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.7; +T_31.5 ; + %load/vec4 v0x2330060_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_31.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_31.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_31.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_31.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_31.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_31.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_31.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_31.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_31.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_31.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_31.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_31.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_31.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_31.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_31.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_31.49, 6; + %jmp T_31.50; +T_31.34 ; + %load/vec4 v0x232fce0_0; + %load/vec4 v0x2333d60_0; + %add; + %assign/vec4 v0x232fce0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.35 ; + %load/vec4 v0x232fce0_0; + %load/vec4 v0x2333d60_0; + %sub; + %assign/vec4 v0x232fce0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.36 ; + %load/vec4 v0x2330270_0; + %pad/u 11; + %load/vec4 v0x2333d60_0; + %add; + %pad/u 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.37 ; + %load/vec4 v0x2333d60_0; + %assign/vec4 v0x23347d0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.38 ; + %load/vec4 v0x232ff80_0; + %assign/vec4 v0x23347d0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.39 ; + %load/vec4 v0x232fce0_0; + %load/vec4 v0x232ff80_0; + %add; + %assign/vec4 v0x232fce0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.40 ; + %load/vec4 v0x232fce0_0; + %load/vec4 v0x232ff80_0; + %sub; + %assign/vec4 v0x232fce0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.41 ; + %load/vec4 v0x2330270_0; + %pad/u 11; + %load/vec4 v0x232ff80_0; + %add; + %pad/u 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.42 ; + %load/vec4 v0x232fde0_0; + %assign/vec4 v0x232fce0_0, 0; + %load/vec4 v0x232fce0_0; + %assign/vec4 v0x232fde0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.43 ; + %load/vec4 v0x232fce0_0; + %assign/vec4 v0x232fde0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.44 ; + %load/vec4 v0x232fce0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x232fce0_0, 0; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.45 ; + %load/vec4 v0x2330190_0; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.50; +T_31.46 ; + %load/vec4 v0x232fce0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_31.51, 4; + %load/vec4 v0x2330190_0; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.52; +T_31.51 ; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; +T_31.52 ; + %jmp T_31.50; +T_31.47 ; + %load/vec4 v0x232fce0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_31.53, 4; + %load/vec4 v0x2330190_0; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.54; +T_31.53 ; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; +T_31.54 ; + %jmp T_31.50; +T_31.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x232fce0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_31.55, 5; + %load/vec4 v0x2330190_0; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.56; +T_31.55 ; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; +T_31.56 ; + %jmp T_31.50; +T_31.49 ; + %load/vec4 v0x232fce0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_31.57, 5; + %load/vec4 v0x2330190_0; + %assign/vec4 v0x2330350_0, 0; + %jmp T_31.58; +T_31.57 ; + %load/vec4 v0x2330270_0; + %addi 1, 0, 4; + %assign/vec4 v0x2330350_0, 0; +T_31.58 ; + %jmp T_31.50; +T_31.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.7; +T_31.6 ; + %load/vec4 v0x2330060_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x2330060_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_31.59, 4; + %load/vec4 v0x232fec0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x232fec0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x23331d0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_31.61, 9; + %load/vec4 v0x232fec0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_31.63, 4; + %load/vec4 v0x23347d0_0; + %assign/vec4 v0x232fce0_0, 0; + %vpi_call 4 336 "$display", "ACC = %d", v0x23347d0_0 {0 0 0}; +T_31.63 ; + %jmp T_31.62; +T_31.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %load/vec4 v0x232fec0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_31.65, 4; + %load/vec4 v0x23331d0_0; + %assign/vec4 v0x23346f0_0, 0; + %load/vec4 v0x23347d0_0; + %load/vec4 v0x23331d0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x23331d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %jmp T_31.66; +T_31.65 ; + %load/vec4 v0x232fec0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_31.67, 4; + %load/vec4 v0x232fec0_0; + %assign/vec4 v0x23346f0_0, 0; + %load/vec4 v0x23347d0_0; + %load/vec4 v0x232fec0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x232fec0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x232fec0_0; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.68; +T_31.67 ; + %load/vec4 v0x2332bc0_0; + %flag_set/vec4 8; + %jmp/0xz T_31.69, 8; + %load/vec4 v0x2331af0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.72; +T_31.71 ; + %load/vec4 v0x2331af0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.74; +T_31.73 ; + %load/vec4 v0x2331af0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.76; +T_31.75 ; + %load/vec4 v0x2331af0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23331d0_0, 0; +T_31.77 ; +T_31.76 ; +T_31.74 ; +T_31.72 ; + %jmp T_31.70; +T_31.69 ; + %load/vec4 v0x232fec0_0; + %assign/vec4 v0x23346f0_0, 0; +T_31.70 ; +T_31.68 ; +T_31.66 ; +T_31.62 ; +T_31.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.7; +T_31.7 ; + %pop/vec4 1; + %jmp T_31.3; +T_31.1 ; + %load/vec4 v0x2333690_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_31.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_31.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_31.81, 6; + %jmp T_31.82; +T_31.79 ; + %load/vec4 v0x2333cc0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_31.83, 4; + %load/vec4 v0x2332a40_0; + %flag_set/vec4 8; + %jmp/0xz T_31.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2334450_0, 0, 4; + %load/vec4 v0x2333770_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.88; +T_31.87 ; + %load/vec4 v0x2333770_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.90; +T_31.89 ; + %load/vec4 v0x2333770_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.92; +T_31.91 ; + %load/vec4 v0x2333770_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23331d0_0, 0; +T_31.93 ; +T_31.92 ; +T_31.90 ; +T_31.88 ; +T_31.85 ; + %jmp T_31.84; +T_31.83 ; + %load/vec4 v0x2333770_0; + %load/vec4 v0x2333cc0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_31.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %load/vec4 v0x2333cc0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2333e00, 4; + %assign/vec4 v0x2333d60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2333cc0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2333c20_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2333cc0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2334450_0, 4, 5; + %load/vec4 v0x2333cc0_0; + %assign/vec4 v0x23331d0_0, 0; +T_31.95 ; +T_31.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.82; +T_31.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.82; +T_31.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.82; +T_31.82 ; + %pop/vec4 1; + %jmp T_31.3; +T_31.2 ; + %load/vec4 v0x2333690_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_31.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_31.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_31.99, 6; + %jmp T_31.100; +T_31.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.100; +T_31.98 ; + %load/vec4 v0x23346f0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_31.101, 4; + %load/vec4 v0x2332bc0_0; + %flag_set/vec4 8; + %jmp/0xz T_31.103, 8; + %load/vec4 v0x2331af0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.106; +T_31.105 ; + %load/vec4 v0x2331af0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.108; +T_31.107 ; + %load/vec4 v0x2331af0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_31.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x23331d0_0, 0; + %jmp T_31.110; +T_31.109 ; + %load/vec4 v0x2331af0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_31.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23346f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2334370_0, 4, 5; + %load/vec4 v0x23347d0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2333550, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x23331d0_0, 0; +T_31.111 ; +T_31.110 ; +T_31.108 ; +T_31.106 ; +T_31.103 ; +T_31.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.100; +T_31.99 ; + %load/vec4 v0x23346f0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_31.113, 4; + %load/vec4 v0x2334530_0; + %load/vec4 v0x23346f0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_31.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x23346f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2334370_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2333470_0, 0; + %load/vec4 v0x23346f0_0; + %assign/vec4 v0x23331d0_0, 0; +T_31.115 ; +T_31.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2333690_0, 0; + %jmp T_31.100; +T_31.100 ; + %pop/vec4 1; + %jmp T_31.3; +T_31.3 ; + %pop/vec4 1; + %jmp T_31; + .thread T_31; + .scope S_0x232f7c0; +T_32 ; + %wait E_0x231b1f0; + %load/vec4 v0x2333690_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2333470_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x2330350_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_32.0, 8; + %load/vec4 v0x2330350_0; + %assign/vec4 v0x2330270_0, 0; +T_32.0 ; + %load/vec4 v0x2333690_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_32.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2333c20_0, 0, 4; +T_32.2 ; + %jmp T_32; + .thread T_32; + .scope S_0x220a8e0; +T_33 ; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x2349a70_0, 0, 33; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2349340_0, 0, 1; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 1, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 2, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 3, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 4, 0, 11; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 4, 0, 11; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 5, 0, 11; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2349400, 4, 0; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x2349a70_0, 0, 33; +T_33.0 ; + %load/vec4 v0x2349a70_0; + %cmpi/u 50000, 0, 33; + %jmp/0xz T_33.1, 5; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2349280_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2349280_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2349280_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2349280_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x2349280_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x2349280_0, 0, 1; + %delay 1, 0; + %load/vec4 v0x2349a70_0; + %addi 1, 0, 33; + %store/vec4 v0x2349a70_0, 0, 33; + %jmp T_33.0; +T_33.1 ; + %end; + .thread T_33; +# The file index is used to find the file name in the following table. +:file_names 5; + "N/A"; + ""; + "./stackmemory.v"; + "demo/demo.v"; + "./tis100.v"; diff --git a/demo/demo.asm b/demo/demo.asm new file mode 100644 index 0000000..3d0041e --- /dev/null +++ b/demo/demo.asm @@ -0,0 +1,86 @@ +:in +MOV 4 DOWN +MOV 5 DOWN +MOV 6 DOWN +MOV 0 DOWN +MOV 7 DOWN +MOV 8 DOWN +MOV 0 DOWN +JRO 0 + +:out +MOV UP ACC +JMP 0 + +:one +END: +MOV 6 ACC +SAV +LOOP: +SWP +JEZ END +SUB 1 +SAV +MOV UP ACC +JEZ FILL +MOV ACC DOWN +JMP LOOP +FILL: +SWP +FLP: +MOV 0 DOWN +JEZ END +SUB 1 +JMP FLP + +:two +MOV DOWN ACC +SAV +MOV DOWN ACC +MOV ACC DOWN +SWP +MOV ACC DOWN + +:three +MOV UP RIGHT + +:four +MOV LEFT RIGHT + +:five +MOV LEFT UP +MOV LEFT UP +MOV LEFT ACC +SAV +MOV LEFT ACC +MOV LEFT DOWN +MOV LEFT DOWN +MOV ACC DOWN +SWP +MOV ACC DOWN +MOV UP DOWN +MOV UP DOWN + +:six +MOV 6 ACC +SAV +LOOP: +SWP +JEZ END +SUB 1 +SAV +MOV RIGHT ACC +JEZ LOOP +MOV ACC DOWN +JMP LOOP +END: +MOV 0 DOWN + +:seven +MOV UP ACC +MOV UP LEFT +MOV ACC LEFT +MOV UP LEFT +MOV UP LEFT +MOV UP LEFT +MOV UP LEFT diff --git a/demo/demo.v b/demo/demo.v new file mode 100644 index 0000000..570a899 --- /dev/null +++ b/demo/demo.v @@ -0,0 +1,87 @@ +`include "tis100.v" +`include "stackmemory.v" +module tis100Test(); + +reg clk; +reg[32:0] i; + +wire[14:0] inToOne; +wire[14:0] oneToIn; + +wire[14:0] oneToThree; +wire[14:0] threeToOne; + +wire[14:0] twoToFive; +wire[14:0] fiveToTwo; + +wire[14:0] threeToFour; +wire[14:0] fourToThree; + +wire[14:0] fourToFive; +wire[14:0] fiveToFour; + +wire[14:0] sixToSeven; +wire[14:0] sevenToSix; + +wire[14:0] sevenToFive; +wire[14:0] fiveToSeven; + +wire[14:0] sixToOut; +wire[14:0] outToSix; + +reg dutPassed; + +tis100 #("demo/one.dat") one(.clk(clk), + .downOut(oneToThree), .down(threeToOne), + .upOut(oneToIn), .up(inToOne)); + +tis100 #("demo/two.dat") two(.clk(clk), + .downOut(twoToFive), .down(fiveToTwo)); + +tis100 #("demo/three.dat") three(.clk(clk), + .rightOut(threeToFour), .right(fourToThree), + .upOut(threeToOne), .up(oneToThree)); + +tis100 #("demo/four.dat") four(.clk(clk), + .leftOut(fourToThree), .left(threeToFour), + .rightOut(fourToFive), .right(fiveToFour)); + +tis100 #("demo/five.dat") five(.clk(clk), + .leftOut(fiveToFour), .left(fourToFive), + .upOut(fiveToTwo), .up(twoToFive), + .downOut(fiveToSeven), .down(sevenToFive)); + +tis100 #("demo/six.dat") six(.clk(clk), + .rightOut(sixToSeven), .right(sevenToSix), + .downOut(sixToOut), .down(outToSix)); + +tis100 #("demo/seven.dat") seven(.clk(clk), + .leftOut(sevenToSix), .left(sixToSeven), + .upOut(sevenToFive), .up(fiveToSeven)); + +tis100 #("demo/in.dat") in(.clk(clk), .down(oneToIn), .downOut(inToOne)); +tis100 #("demo/out.dat",1) out(.clk(clk), .up(sixToOut), .upOut(outToSix)); + +reg signed[10:0] expected[0:6]; + +initial begin + i = 0; + dutPassed = 1; + expected[0] = 0; + expected[1] = 1; + expected[2] = 2; + expected[3] = 3; + expected[4] = 4; + expected[5] = 4; + expected[6] = 5; + for( i = 0; i<50000; i=i+1) begin + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + end +end + +endmodule diff --git a/demo/five.dat b/demo/five.dat new file mode 100644 index 0000000..46c185b --- /dev/null +++ b/demo/five.dat @@ -0,0 +1,16 @@ +001110001000000000 +001110001000000000 +001100101000000000 +100100000000000000 +001100101000000000 +001110101000000000 +001110101000000000 +001110100100000000 +100000000000000000 +001110100100000000 +001110110000000000 +001110110000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/demo/four.dat b/demo/four.dat new file mode 100644 index 0000000..c94d8de --- /dev/null +++ b/demo/four.dat @@ -0,0 +1,16 @@ +001101101000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/demo/in.dat b/demo/in.dat new file mode 100644 index 0000000..cf9622d --- /dev/null +++ b/demo/in.dat @@ -0,0 +1,16 @@ +010010100000000100 +010010100000000101 +010010100000000110 +010010100000000000 +010010100000000111 +010010100000001000 +010010100000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/demo/one.dat b/demo/one.dat new file mode 100644 index 0000000..b87138c --- /dev/null +++ b/demo/one.dat @@ -0,0 +1,16 @@ +010000100000000110 +100100000000000000 +100000000000000000 +110000000000000000 +011000000000000001 +100100000000000000 +001100110000000000 +110010100000000000 +001110100100000000 +101100100000000000 +100000000000000000 +010010100000000000 +110000000000000000 +011000000000000001 +101110110000000000 +101100000000000000 diff --git a/demo/out.dat b/demo/out.dat new file mode 100644 index 0000000..e9b9712 --- /dev/null +++ b/demo/out.dat @@ -0,0 +1,16 @@ +001100110000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/demo/seven.dat b/demo/seven.dat new file mode 100644 index 0000000..702c76a --- /dev/null +++ b/demo/seven.dat @@ -0,0 +1,16 @@ +001100110000000000 +001101010000000000 +001101000100000000 +001101010000000000 +001101010000000000 +001101010000000000 +001101010000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/demo/six.dat b/demo/six.dat new file mode 100644 index 0000000..e4702b8 --- /dev/null +++ b/demo/six.dat @@ -0,0 +1,16 @@ +010000100000000110 +100100000000000000 +100000000000000000 +110010100000000000 +011000000000000001 +100100000000000000 +001100101100000000 +110000100000000000 +001110100100000000 +101100100000000000 +010010100000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/demo/testmem.dat b/demo/testmem.dat new file mode 100644 index 0000000..d56c7be --- /dev/null +++ b/demo/testmem.dat @@ -0,0 +1,6 @@ +0000000000 +0101001001 +0100101101 +0010100100 +1001010100 +0101010100 diff --git a/demo/three.dat b/demo/three.dat new file mode 100644 index 0000000..6555908 --- /dev/null +++ b/demo/three.dat @@ -0,0 +1,16 @@ +001101110000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/demo/two.dat b/demo/two.dat new file mode 100644 index 0000000..a1a6feb --- /dev/null +++ b/demo/two.dat @@ -0,0 +1,16 @@ +001100110100000000 +100100000000000000 +001100110100000000 +001110100100000000 +100000000000000000 +001110100100000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/jumpTest/center.dat b/jumpTest/center.dat new file mode 100644 index 0000000..81366c1 --- /dev/null +++ b/jumpTest/center.dat @@ -0,0 +1,16 @@ +010000100000000001 +101100110000000000 +010000100000101000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/jumpTest/down.dat b/jumpTest/down.dat new file mode 100644 index 0000000..c957f3a --- /dev/null +++ b/jumpTest/down.dat @@ -0,0 +1,16 @@ +010000111111111111 +111100110000000000 +010000100000101000 +010100000000000010 +011100000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/jumpTest/left.dat b/jumpTest/left.dat new file mode 100644 index 0000000..97f8c31 --- /dev/null +++ b/jumpTest/left.dat @@ -0,0 +1,16 @@ +010000100000000001 +110100110000000000 +010000100000101000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/jumpTest/right.dat b/jumpTest/right.dat new file mode 100644 index 0000000..1aef359 --- /dev/null +++ b/jumpTest/right.dat @@ -0,0 +1,16 @@ +010000100000000001 +111000110000000000 +010000100000101000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/jumpTest/test b/jumpTest/test new file mode 100755 index 0000000..d3311de --- /dev/null +++ b/jumpTest/test @@ -0,0 +1,6103 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0xf12740 .scope module, "tis100Test" "tis100Test" 2 2; + .timescale 0 0; +v0xfe1460_0 .net "C2D", 14 0, L_0x1005cd0; 1 drivers +v0xfe1590_0 .net "C2L", 14 0, L_0x10059f0; 1 drivers +v0xfe16a0_0 .net "C2R", 14 0, L_0x10063c0; 1 drivers +v0xfe1790_0 .net "C2U", 14 0, L_0x1005720; 1 drivers +v0xfe18a0_0 .net "D2C", 14 0, L_0x1001530; 1 drivers +v0xfe1a00_0 .net "L2C", 14 0, L_0xff5db0; 1 drivers +v0xfe1b10_0 .net "R2C", 14 0, L_0xff9620; 1 drivers +v0xfe1c20_0 .net "U2C", 14 0, L_0xffd990; 1 drivers +v0xfe1d30_0 .net/s "accOutCenter", 10 0, L_0x10022f0; 1 drivers +v0xfe1e80_0 .net/s "accOutDown", 10 0, L_0xffe290; 1 drivers +v0xfe1f20_0 .net/s "accOutLeft", 10 0, L_0xfe2320; 1 drivers +v0xfe1fc0_0 .net/s "accOutRight", 10 0, L_0xff6100; 1 drivers +v0xfe2060_0 .net/s "accOutUp", 10 0, L_0xffa1e0; 1 drivers +v0xfe2100_0 .var "clk", 0 0; +v0xfe21a0_0 .var "dutPassed", 0 0; +v0xfe2240_0 .var "i", 32 0; +S_0xf727f0 .scope module, "center" "tis100" 2 31, 3 49 0, S_0xf12740; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0xf2f5c0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0xf2f600 .param/str "memFile" 0 3 60, "jumpTest/center.dat"; +L_0x10022f0 .functor BUFZ 11, v0xf88400_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x1002580 .functor BUFZ 11, v0xf88400_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x10033b0 .functor BUFZ 18, L_0x1005530, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0xf88400_0 .var/s "ACC", 10 0; +v0xfc7f60_0 .var/s "BAK", 10 0; +v0xfc8040_0 .net "DST", 2 0, L_0x1006850; 1 drivers +v0xfc8130_0 .net/s "IMM", 10 0, L_0x10068f0; 1 drivers +v0xfc8210_0 .net "INST", 3 0, L_0x1006030; 1 drivers +v0xfc8340_0 .net "LABEL", 3 0, L_0x1006aa0; 1 drivers +v0xfc8420_0 .var "PC", 3 0; +v0xfc8500_0 .var "PCNEXT", 3 0; +v0xfc85e0_0 .net "SRC", 2 0, L_0x1006660; 1 drivers +v0xfc8750_0 .net *"_s103", 0 0, L_0x1004870; 1 drivers +v0xfc8830_0 .net *"_s107", 0 0, L_0x1004780; 1 drivers +v0xfc8910_0 .net *"_s111", 0 0, L_0x1004a60; 1 drivers +v0xfc89f0_0 .net *"_s115", 0 0, L_0x1004960; 1 drivers +v0xfc8ad0_0 .net *"_s119", 0 0, L_0x1004ca0; 1 drivers +v0xfc8bb0_0 .net *"_s123", 0 0, L_0x1004b90; 1 drivers +v0xfc8c90_0 .net *"_s127", 0 0, L_0x1004e60; 1 drivers +v0xfc8d70_0 .net *"_s131", 0 0, L_0x1004d40; 1 drivers +v0xfc8f20_0 .net *"_s135", 0 0, L_0x10050c0; 1 drivers +v0xfc8fc0_0 .net *"_s139", 0 0, L_0x1004f90; 1 drivers +v0xfc90a0_0 .net *"_s143", 0 0, L_0x10052a0; 1 drivers +v0xfc9180_0 .net *"_s147", 0 0, L_0x1005160; 1 drivers +v0xfc9260_0 .net *"_s151", 0 0, L_0x1005490; 1 drivers +v0xfc9340_0 .net *"_s155", 0 0, L_0x1005340; 1 drivers +v0xfc9420_0 .net *"_s159", 0 0, L_0x10053e0; 1 drivers +v0xfc9500_0 .net *"_s160", 17 0, L_0x1005530; 1 drivers +v0xfc95e0_0 .net *"_s162", 5 0, L_0x1005890; 1 drivers +L_0x2b99d7e1a2a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0xfc96c0_0 .net *"_s165", 1 0, L_0x2b99d7e1a2a0; 1 drivers +v0xfcb690_2 .array/port v0xfcb690, 2; +v0xfc97a0_0 .net *"_s173", 10 0, v0xfcb690_2; 1 drivers +v0xfcb690_3 .array/port v0xfcb690, 3; +v0xfc9880_0 .net *"_s179", 10 0, v0xfcb690_3; 1 drivers +v0xfcb690_0 .array/port v0xfcb690, 0; +v0xfc9960_0 .net *"_s185", 10 0, v0xfcb690_0; 1 drivers +v0xfcb690_1 .array/port v0xfcb690, 1; +v0xfc9a40_0 .net *"_s191", 10 0, v0xfcb690_1; 1 drivers +v0xfc9b20_0 .net *"_s23", 0 0, L_0x1002d50; 1 drivers +v0xfc9c00_0 .net *"_s27", 0 0, L_0x1002e20; 1 drivers +v0xfc8e50_0 .net *"_s31", 0 0, L_0x1002ef0; 1 drivers +v0xfc9ed0_0 .net *"_s36", 0 0, L_0x1003090; 1 drivers +v0xfc9fb0_0 .net *"_s42", 0 0, L_0x1003270; 1 drivers +v0xfca090_0 .net *"_s46", 0 0, L_0x1003310; 1 drivers +v0xfca170_0 .net *"_s50", 0 0, L_0x1003420; 1 drivers +v0xfca250_0 .net *"_s55", 0 0, L_0x1003630; 1 drivers +v0xfca330_0 .net *"_s61", 0 0, L_0x10038a0; 1 drivers +v0xfca410_0 .net *"_s65", 0 0, L_0x1003940; 1 drivers +v0xfca4f0_0 .net *"_s69", 0 0, L_0x1003a80; 1 drivers +v0xfca5d0_0 .net *"_s74", 0 0, L_0x10039e0; 1 drivers +v0xfca6b0_0 .net *"_s80", 0 0, L_0x1003cb0; 1 drivers +v0xfca790_0 .net *"_s84", 0 0, L_0x1004070; 1 drivers +v0xfca870_0 .net *"_s88", 0 0, L_0x1003ea0; 1 drivers +v0xfca950_0 .net *"_s93", 0 0, L_0x1004220; 1 drivers +v0xfcaa30_0 .net *"_s99", 0 0, L_0x10044a0; 1 drivers +v0xfcab10_0 .net/s "accOut", 10 0, L_0x10022f0; alias, 1 drivers +v0xfcabf0_0 .net "anyHasData", 0 0, L_0x1003180; 1 drivers +v0xfcacb0_0 .net "anyReadAck", 0 0, L_0x1003db0; 1 drivers +v0xfcad70_0 .net "anyWantData", 0 0, L_0x1003720; 1 drivers +v0xfcae30_0 .net "anyWriteAck", 0 0, L_0x10046e0; 1 drivers +v0xfcaef0_0 .net "clk", 0 0, v0xfe2100_0; 1 drivers +v0xfcafb0_0 .net "down", 14 0, L_0x1001530; alias, 1 drivers +v0xfcb090_0 .net "downOut", 14 0, L_0x1005cd0; alias, 1 drivers +v0xfcb170_0 .net "instruction", 17 0, L_0x10033b0; 1 drivers +v0xfcb250 .array "instructions", 15 0, 17 0; +v0xfcb310_0 .var "last", 2 0; +v0xfcb3f0_0 .net "left", 14 0, L_0xff5db0; alias, 1 drivers +v0xfcb4d0_0 .net "leftOut", 14 0, L_0x10059f0; alias, 1 drivers +v0xfcb5b0_0 .var "mode", 2 0; +v0xfcb690 .array/s "outVals", 2 5, 10 0; +v0xfcb7d0_0 .var "phase", 2 0; +v0xfcb8b0_0 .net "portsHaveData", 5 2, L_0x1002f90; 1 drivers +v0xfc9ca0_0 .net "portsWantData", 5 2, L_0x10034c0; 1 drivers +v0xfc9d80_0 .net "readAckIn", 5 2, L_0x1003b20; 1 drivers +v0xfcbd60_0 .var "readAckOut", 5 2; +v0xfcbe00_0 .var "readTarget", 2 0; +v0xfcbee0_0 .var/s "readValue", 10 0; +L_0x2b99d7e1a258 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0xfcbfc0 .array "regVals", 0 7; +v0xfcbfc0_0 .net/s v0xfcbfc0 0, 10 0, L_0x2b99d7e1a258; 1 drivers +v0xfcbfc0_1 .net/s v0xfcbfc0 1, 10 0, L_0x1002580; 1 drivers +v0xfcbfc0_2 .net/s v0xfcbfc0 2, 10 0, L_0x1002860; 1 drivers +v0xfcbfc0_3 .net/s v0xfcbfc0 3, 10 0, L_0x1002990; 1 drivers +v0xfcbfc0_4 .net/s v0xfcbfc0 4, 10 0, L_0x1002ac0; 1 drivers +v0xfcbfc0_5 .net/s v0xfcbfc0 5, 10 0, L_0x1002bf0; 1 drivers +o0x2b99d7de9eb8 .functor BUFZ 11, C4; HiZ drive +v0xfcbfc0_6 .net/s v0xfcbfc0 6, 10 0, o0x2b99d7de9eb8; 0 drivers +o0x2b99d7de9ee8 .functor BUFZ 11, C4; HiZ drive +v0xfcbfc0_7 .net/s v0xfcbfc0 7, 10 0, o0x2b99d7de9ee8; 0 drivers +v0xfcc1d0_0 .net "right", 14 0, L_0xff9620; alias, 1 drivers +v0xfcc2b0_0 .net "rightOut", 14 0, L_0x10063c0; alias, 1 drivers +v0xfcc390_0 .net "up", 14 0, L_0xffd990; alias, 1 drivers +v0xfcc470_0 .net "upOut", 14 0, L_0x1005720; alias, 1 drivers +v0xfcc550_0 .var "weHaveData", 5 2; +v0xfcc630_0 .var "weWantData", 5 2; +v0xfcc710_0 .net "writeAckIn", 5 2, L_0x1004400; 1 drivers +v0xfcc7f0_0 .var "writeAckOut", 5 2; +v0xfcc8d0_0 .var "writeTarget", 2 0; +v0xfcc9b0_0 .var/s "writeValue", 10 0; +E_0xf235d0 .event negedge, v0xfcaef0_0; +E_0xf45d10 .event posedge, v0xfcaef0_0; +L_0x1002860 .part L_0xff5db0, 0, 11; +L_0x1002990 .part L_0xff9620, 0, 11; +L_0x1002ac0 .part L_0xffd990, 0, 11; +L_0x1002bf0 .part L_0x1001530, 0, 11; +L_0x1002d50 .part L_0xff5db0, 11, 1; +L_0x1002e20 .part L_0xff9620, 11, 1; +L_0x1002ef0 .part L_0xffd990, 11, 1; +L_0x1002f90 .concat8 [ 1 1 1 1], L_0x1002d50, L_0x1002e20, L_0x1002ef0, L_0x1003090; +L_0x1003090 .part L_0x1001530, 11, 1; +L_0x1003180 .reduce/or L_0x1002f90; +L_0x1003270 .part L_0xff5db0, 12, 1; +L_0x1003310 .part L_0xff9620, 12, 1; +L_0x1003420 .part L_0xffd990, 12, 1; +L_0x10034c0 .concat8 [ 1 1 1 1], L_0x1003270, L_0x1003310, L_0x1003420, L_0x1003630; +L_0x1003630 .part L_0x1001530, 12, 1; +L_0x1003720 .reduce/or L_0x10034c0; +L_0x10038a0 .part L_0xff5db0, 13, 1; +L_0x1003940 .part L_0xff9620, 13, 1; +L_0x1003a80 .part L_0xffd990, 13, 1; +L_0x1003b20 .concat8 [ 1 1 1 1], L_0x10038a0, L_0x1003940, L_0x1003a80, L_0x10039e0; +L_0x10039e0 .part L_0x1001530, 13, 1; +L_0x1003db0 .reduce/or L_0x1003b20; +L_0x1003cb0 .part L_0xff5db0, 14, 1; +L_0x1004070 .part L_0xff9620, 14, 1; +L_0x1003ea0 .part L_0xffd990, 14, 1; +L_0x1004400 .concat8 [ 1 1 1 1], L_0x1003cb0, L_0x1004070, L_0x1003ea0, L_0x1004220; +L_0x1004220 .part L_0x1001530, 14, 1; +L_0x10046e0 .reduce/or L_0x1004400; +L_0x10044a0 .part v0xfcbd60_0, 0, 1; +L_0x1004870 .part v0xfcbd60_0, 1, 1; +L_0x1004780 .part v0xfcbd60_0, 2, 1; +L_0x1004a60 .part v0xfcbd60_0, 3, 1; +L_0x1004960 .part v0xfcc7f0_0, 0, 1; +L_0x1004ca0 .part v0xfcc7f0_0, 1, 1; +L_0x1004b90 .part v0xfcc7f0_0, 2, 1; +L_0x1004e60 .part v0xfcc7f0_0, 3, 1; +L_0x1004d40 .part v0xfcc630_0, 0, 1; +L_0x10050c0 .part v0xfcc630_0, 1, 1; +L_0x1004f90 .part v0xfcc630_0, 2, 1; +L_0x10052a0 .part v0xfcc630_0, 3, 1; +L_0x1005160 .part v0xfcc550_0, 0, 1; +L_0x1005490 .part v0xfcc550_0, 1, 1; +L_0x1005340 .part v0xfcc550_0, 2, 1; +L_0x10053e0 .part v0xfcc550_0, 3, 1; +L_0x1005530 .array/port v0xfcb250, L_0x1005890; +L_0x1005890 .concat [ 4 2 0 0], v0xfc8420_0, L_0x2b99d7e1a2a0; +LS_0x1005720_0_0 .concat8 [ 11 1 1 1], v0xfcb690_2, L_0x1005340, L_0x1004f90, L_0x1004b90; +LS_0x1005720_0_4 .concat8 [ 1 0 0 0], L_0x1004780; +L_0x1005720 .concat8 [ 14 1 0 0], LS_0x1005720_0_0, LS_0x1005720_0_4; +LS_0x1005cd0_0_0 .concat8 [ 11 1 1 1], v0xfcb690_3, L_0x10053e0, L_0x10052a0, L_0x1004e60; +LS_0x1005cd0_0_4 .concat8 [ 1 0 0 0], L_0x1004a60; +L_0x1005cd0 .concat8 [ 14 1 0 0], LS_0x1005cd0_0_0, LS_0x1005cd0_0_4; +LS_0x10059f0_0_0 .concat8 [ 11 1 1 1], v0xfcb690_0, L_0x1005160, L_0x1004d40, L_0x1004960; +LS_0x10059f0_0_4 .concat8 [ 1 0 0 0], L_0x10044a0; +L_0x10059f0 .concat8 [ 14 1 0 0], LS_0x10059f0_0_0, LS_0x10059f0_0_4; +LS_0x10063c0_0_0 .concat8 [ 11 1 1 1], v0xfcb690_1, L_0x1005490, L_0x10050c0, L_0x1004ca0; +LS_0x10063c0_0_4 .concat8 [ 1 0 0 0], L_0x1004870; +L_0x10063c0 .concat8 [ 14 1 0 0], LS_0x10063c0_0_0, LS_0x10063c0_0_4; +L_0x1006030 .part L_0x10033b0, 14, 4; +L_0x1006850 .part L_0x10033b0, 11, 3; +L_0x1006660 .part L_0x10033b0, 8, 3; +L_0x1006aa0 .part L_0x10033b0, 10, 4; +L_0x10068f0 .part L_0x10033b0, 0, 11; +S_0xfccc30 .scope module, "down" "tis100" 2 30, 3 49 0, S_0xf12740; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0xfcce20 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0xfcce60 .param/str "memFile" 0 3 60, "jumpTest/down.dat"; +L_0xffe290 .functor BUFZ 11, v0xfcd1b0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xffe490 .functor BUFZ 11, v0xfcd1b0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xfff350 .functor BUFZ 18, L_0x10012c0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0xfcd1b0_0 .var/s "ACC", 10 0; +v0xfcd2b0_0 .var/s "BAK", 10 0; +v0xfcd390_0 .net "DST", 2 0, L_0x10023b0; 1 drivers +v0xfcd450_0 .net/s "IMM", 10 0, L_0x1002450; 1 drivers +v0xfcd530_0 .net "INST", 3 0, L_0x1001c90; 1 drivers +v0xfcd610_0 .net "LABEL", 3 0, L_0x1002600; 1 drivers +v0xfcd6f0_0 .var "PC", 3 0; +v0xfcd7d0_0 .var "PCNEXT", 3 0; +v0xfcd8b0_0 .net "SRC", 2 0, L_0x10021c0; 1 drivers +v0xfcda20_0 .net *"_s103", 0 0, L_0x1000600; 1 drivers +v0xfcdb00_0 .net *"_s107", 0 0, L_0x1000510; 1 drivers +v0xfcdbe0_0 .net *"_s111", 0 0, L_0x10007f0; 1 drivers +v0xfcdcc0_0 .net *"_s115", 0 0, L_0x10006f0; 1 drivers +v0xfcdda0_0 .net *"_s119", 0 0, L_0x1000a30; 1 drivers +v0xfcde80_0 .net *"_s123", 0 0, L_0x1000920; 1 drivers +v0xfcdf60_0 .net *"_s127", 0 0, L_0x1000bf0; 1 drivers +v0xfce040_0 .net *"_s131", 0 0, L_0x1000ad0; 1 drivers +v0xfce1f0_0 .net *"_s135", 0 0, L_0x1000e50; 1 drivers +v0xfce290_0 .net *"_s139", 0 0, L_0x1000d20; 1 drivers +v0xfce370_0 .net *"_s143", 0 0, L_0x1001030; 1 drivers +v0xfce450_0 .net *"_s147", 0 0, L_0x1000ef0; 1 drivers +v0xfce530_0 .net *"_s151", 0 0, L_0x1001220; 1 drivers +v0xfce610_0 .net *"_s155", 0 0, L_0x10010d0; 1 drivers +v0xfce6f0_0 .net *"_s159", 0 0, L_0x1001170; 1 drivers +v0xfce7d0_0 .net *"_s160", 17 0, L_0x10012c0; 1 drivers +v0xfce8b0_0 .net *"_s162", 5 0, L_0x1001620; 1 drivers +L_0x2b99d7e1a210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0xfce990_0 .net *"_s165", 1 0, L_0x2b99d7e1a210; 1 drivers +v0xfd0920_2 .array/port v0xfd0920, 2; +v0xfcea70_0 .net *"_s173", 10 0, v0xfd0920_2; 1 drivers +v0xfd0920_3 .array/port v0xfd0920, 3; +v0xfceb50_0 .net *"_s179", 10 0, v0xfd0920_3; 1 drivers +v0xfd0920_0 .array/port v0xfd0920, 0; +v0xfcec30_0 .net *"_s185", 10 0, v0xfd0920_0; 1 drivers +v0xfd0920_1 .array/port v0xfd0920, 1; +v0xfced10_0 .net *"_s191", 10 0, v0xfd0920_1; 1 drivers +v0xfcedf0_0 .net *"_s23", 0 0, L_0xffeae0; 1 drivers +v0xfceed0_0 .net *"_s27", 0 0, L_0xffec00; 1 drivers +v0xfce120_0 .net *"_s31", 0 0, L_0xffecf0; 1 drivers +v0xfcf1a0_0 .net *"_s36", 0 0, L_0xffefe0; 1 drivers +v0xfcf280_0 .net *"_s42", 0 0, L_0xfff210; 1 drivers +v0xfcf360_0 .net *"_s46", 0 0, L_0xfff2b0; 1 drivers +v0xfcf440_0 .net *"_s50", 0 0, L_0xfff3c0; 1 drivers +v0xfcf520_0 .net *"_s55", 0 0, L_0xfff5d0; 1 drivers +v0xfcf600_0 .net *"_s61", 0 0, L_0xfff840; 1 drivers +v0xfcf6e0_0 .net *"_s65", 0 0, L_0xfff970; 1 drivers +v0xfcf7c0_0 .net *"_s69", 0 0, L_0xfffb40; 1 drivers +v0xfcf8a0_0 .net *"_s74", 0 0, L_0xfffaa0; 1 drivers +v0xfcf980_0 .net *"_s80", 0 0, L_0xfffcd0; 1 drivers +v0xfcfa60_0 .net *"_s84", 0 0, L_0xffffc0; 1 drivers +v0xfcfb40_0 .net *"_s88", 0 0, L_0xffff00; 1 drivers +v0xfcfc20_0 .net *"_s93", 0 0, L_0x1000060; 1 drivers +v0xfcfd00_0 .net *"_s99", 0 0, L_0x10002f0; 1 drivers +v0xfcfde0_0 .net/s "accOut", 10 0, L_0xffe290; alias, 1 drivers +v0xfcfec0_0 .net "anyHasData", 0 0, L_0xfff120; 1 drivers +v0xfcff80_0 .net "anyReadAck", 0 0, L_0xfffe60; 1 drivers +v0xfd0040_0 .net "anyWantData", 0 0, L_0xfff6c0; 1 drivers +v0xfd0100_0 .net "anyWriteAck", 0 0, L_0x1000420; 1 drivers +v0xfd01c0_0 .net "clk", 0 0, v0xfe2100_0; alias, 1 drivers +o0x2b99d7deacc8 .functor BUFZ 15, C4; HiZ drive +v0xfd0260_0 .net "down", 14 0, o0x2b99d7deacc8; 0 drivers +v0xfd0320_0 .net "downOut", 14 0, L_0x10019f0; 1 drivers +v0xfd0400_0 .net "instruction", 17 0, L_0xfff350; 1 drivers +v0xfd04e0 .array "instructions", 15 0, 17 0; +v0xfd05a0_0 .var "last", 2 0; +o0x2b99d7dead88 .functor BUFZ 15, C4; HiZ drive +v0xfd0680_0 .net "left", 14 0, o0x2b99d7dead88; 0 drivers +v0xfd0760_0 .net "leftOut", 14 0, L_0x1001780; 1 drivers +v0xfd0840_0 .var "mode", 2 0; +v0xfd0920 .array/s "outVals", 2 5, 10 0; +v0xfd0a60_0 .var "phase", 2 0; +v0xfd0b40_0 .net "portsHaveData", 5 2, L_0xffee20; 1 drivers +v0xfcef70_0 .net "portsWantData", 5 2, L_0xfff460; 1 drivers +v0xfcf050_0 .net "readAckIn", 5 2, L_0xfffbe0; 1 drivers +v0xfd0ff0_0 .var "readAckOut", 5 2; +v0xfd1090_0 .var "readTarget", 2 0; +v0xfd1130_0 .var/s "readValue", 10 0; +L_0x2b99d7e1a1c8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0xfd11d0 .array "regVals", 0 7; +v0xfd11d0_0 .net/s v0xfd11d0 0, 10 0, L_0x2b99d7e1a1c8; 1 drivers +v0xfd11d0_1 .net/s v0xfd11d0 1, 10 0, L_0xffe490; 1 drivers +v0xfd11d0_2 .net/s v0xfd11d0 2, 10 0, L_0xffe800; 1 drivers +v0xfd11d0_3 .net/s v0xfd11d0 3, 10 0, L_0xffe8a0; 1 drivers +v0xfd11d0_4 .net/s v0xfd11d0 4, 10 0, L_0xffe940; 1 drivers +v0xfd11d0_5 .net/s v0xfd11d0 5, 10 0, L_0xffe9e0; 1 drivers +o0x2b99d7deb148 .functor BUFZ 11, C4; HiZ drive +v0xfd11d0_6 .net/s v0xfd11d0 6, 10 0, o0x2b99d7deb148; 0 drivers +o0x2b99d7deb178 .functor BUFZ 11, C4; HiZ drive +v0xfd11d0_7 .net/s v0xfd11d0 7, 10 0, o0x2b99d7deb178; 0 drivers +o0x2b99d7deb1a8 .functor BUFZ 15, C4; HiZ drive +v0xfd13e0_0 .net "right", 14 0, o0x2b99d7deb1a8; 0 drivers +v0xfd14c0_0 .net "rightOut", 14 0, L_0x1001fa0; 1 drivers +v0xfd15a0_0 .net "up", 14 0, L_0x1005cd0; alias, 1 drivers +v0xfd1690_0 .net "upOut", 14 0, L_0x1001530; alias, 1 drivers +v0xfd1760_0 .var "weHaveData", 5 2; +v0xfd1820_0 .var "weWantData", 5 2; +v0xfd1900_0 .net "writeAckIn", 5 2, L_0x1000130; 1 drivers +v0xfd19e0_0 .var "writeAckOut", 5 2; +v0xfd1ac0_0 .var "writeTarget", 2 0; +v0xfd1ba0_0 .var/s "writeValue", 10 0; +L_0xffe800 .part o0x2b99d7dead88, 0, 11; +L_0xffe8a0 .part o0x2b99d7deb1a8, 0, 11; +L_0xffe940 .part L_0x1005cd0, 0, 11; +L_0xffe9e0 .part o0x2b99d7deacc8, 0, 11; +L_0xffeae0 .part o0x2b99d7dead88, 11, 1; +L_0xffec00 .part o0x2b99d7deb1a8, 11, 1; +L_0xffecf0 .part L_0x1005cd0, 11, 1; +L_0xffee20 .concat8 [ 1 1 1 1], L_0xffeae0, L_0xffec00, L_0xffecf0, L_0xffefe0; +L_0xffefe0 .part o0x2b99d7deacc8, 11, 1; +L_0xfff120 .reduce/or L_0xffee20; +L_0xfff210 .part o0x2b99d7dead88, 12, 1; +L_0xfff2b0 .part o0x2b99d7deb1a8, 12, 1; +L_0xfff3c0 .part L_0x1005cd0, 12, 1; +L_0xfff460 .concat8 [ 1 1 1 1], L_0xfff210, L_0xfff2b0, L_0xfff3c0, L_0xfff5d0; +L_0xfff5d0 .part o0x2b99d7deacc8, 12, 1; +L_0xfff6c0 .reduce/or L_0xfff460; +L_0xfff840 .part o0x2b99d7dead88, 13, 1; +L_0xfff970 .part o0x2b99d7deb1a8, 13, 1; +L_0xfffb40 .part L_0x1005cd0, 13, 1; +L_0xfffbe0 .concat8 [ 1 1 1 1], L_0xfff840, L_0xfff970, L_0xfffb40, L_0xfffaa0; +L_0xfffaa0 .part o0x2b99d7deacc8, 13, 1; +L_0xfffe60 .reduce/or L_0xfffbe0; +L_0xfffcd0 .part o0x2b99d7dead88, 14, 1; +L_0xffffc0 .part o0x2b99d7deb1a8, 14, 1; +L_0xffff00 .part L_0x1005cd0, 14, 1; +L_0x1000130 .concat8 [ 1 1 1 1], L_0xfffcd0, L_0xffffc0, L_0xffff00, L_0x1000060; +L_0x1000060 .part o0x2b99d7deacc8, 14, 1; +L_0x1000420 .reduce/or L_0x1000130; +L_0x10002f0 .part v0xfd0ff0_0, 0, 1; +L_0x1000600 .part v0xfd0ff0_0, 1, 1; +L_0x1000510 .part v0xfd0ff0_0, 2, 1; +L_0x10007f0 .part v0xfd0ff0_0, 3, 1; +L_0x10006f0 .part v0xfd19e0_0, 0, 1; +L_0x1000a30 .part v0xfd19e0_0, 1, 1; +L_0x1000920 .part v0xfd19e0_0, 2, 1; +L_0x1000bf0 .part v0xfd19e0_0, 3, 1; +L_0x1000ad0 .part v0xfd1820_0, 0, 1; +L_0x1000e50 .part v0xfd1820_0, 1, 1; +L_0x1000d20 .part v0xfd1820_0, 2, 1; +L_0x1001030 .part v0xfd1820_0, 3, 1; +L_0x1000ef0 .part v0xfd1760_0, 0, 1; +L_0x1001220 .part v0xfd1760_0, 1, 1; +L_0x10010d0 .part v0xfd1760_0, 2, 1; +L_0x1001170 .part v0xfd1760_0, 3, 1; +L_0x10012c0 .array/port v0xfd04e0, L_0x1001620; +L_0x1001620 .concat [ 4 2 0 0], v0xfcd6f0_0, L_0x2b99d7e1a210; +LS_0x1001530_0_0 .concat8 [ 11 1 1 1], v0xfd0920_2, L_0x10010d0, L_0x1000d20, L_0x1000920; +LS_0x1001530_0_4 .concat8 [ 1 0 0 0], L_0x1000510; +L_0x1001530 .concat8 [ 14 1 0 0], LS_0x1001530_0_0, LS_0x1001530_0_4; +LS_0x10019f0_0_0 .concat8 [ 11 1 1 1], v0xfd0920_3, L_0x1001170, L_0x1001030, L_0x1000bf0; +LS_0x10019f0_0_4 .concat8 [ 1 0 0 0], L_0x10007f0; +L_0x10019f0 .concat8 [ 14 1 0 0], LS_0x10019f0_0_0, LS_0x10019f0_0_4; +LS_0x1001780_0_0 .concat8 [ 11 1 1 1], v0xfd0920_0, L_0x1000ef0, L_0x1000ad0, L_0x10006f0; +LS_0x1001780_0_4 .concat8 [ 1 0 0 0], L_0x10002f0; +L_0x1001780 .concat8 [ 14 1 0 0], LS_0x1001780_0_0, LS_0x1001780_0_4; +LS_0x1001fa0_0_0 .concat8 [ 11 1 1 1], v0xfd0920_1, L_0x1001220, L_0x1000e50, L_0x1000a30; +LS_0x1001fa0_0_4 .concat8 [ 1 0 0 0], L_0x1000600; +L_0x1001fa0 .concat8 [ 14 1 0 0], LS_0x1001fa0_0_0, LS_0x1001fa0_0_4; +L_0x1001c90 .part L_0xfff350, 14, 4; +L_0x10023b0 .part L_0xfff350, 11, 3; +L_0x10021c0 .part L_0xfff350, 8, 3; +L_0x1002600 .part L_0xfff350, 10, 4; +L_0x1002450 .part L_0xfff350, 0, 11; +S_0xfd1e20 .scope module, "left" "tis100" 2 27, 3 49 0, S_0xf12740; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0xfd1ff0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0xfd2030 .param/str "memFile" 0 3 60, "jumpTest/left.dat"; +L_0xfe2320 .functor BUFZ 11, v0xfd23b0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xff23c0 .functor BUFZ 11, v0xfd23b0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xff3090 .functor BUFZ 18, L_0xff5080, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0xfd23b0_0 .var/s "ACC", 10 0; +v0xfd24b0_0 .var/s "BAK", 10 0; +v0xfd2590_0 .net "DST", 2 0, L_0xff61c0; 1 drivers +v0xfd2650_0 .net/s "IMM", 10 0, L_0xff6260; 1 drivers +v0xfd2730_0 .net "INST", 3 0, L_0xff5aa0; 1 drivers +v0xfd2810_0 .net "LABEL", 3 0, L_0xff6410; 1 drivers +v0xfd28f0_0 .var "PC", 3 0; +v0xfd29d0_0 .var "PCNEXT", 3 0; +v0xfd2ab0_0 .net "SRC", 2 0, L_0xff5fd0; 1 drivers +v0xfd2c20_0 .net *"_s103", 0 0, L_0xff43c0; 1 drivers +v0xfd2d00_0 .net *"_s107", 0 0, L_0xff42d0; 1 drivers +v0xfd2de0_0 .net *"_s111", 0 0, L_0xff45b0; 1 drivers +v0xfd2ec0_0 .net *"_s115", 0 0, L_0xff44b0; 1 drivers +v0xfd2fa0_0 .net *"_s119", 0 0, L_0xff47f0; 1 drivers +v0xfd3080_0 .net *"_s123", 0 0, L_0xff46e0; 1 drivers +v0xfd3160_0 .net *"_s127", 0 0, L_0xff49b0; 1 drivers +v0xfd3240_0 .net *"_s131", 0 0, L_0xff4890; 1 drivers +v0xfd33f0_0 .net *"_s135", 0 0, L_0xff4c10; 1 drivers +v0xfd3490_0 .net *"_s139", 0 0, L_0xff4ae0; 1 drivers +v0xfd3570_0 .net *"_s143", 0 0, L_0xff4df0; 1 drivers +v0xfd3650_0 .net *"_s147", 0 0, L_0xff4cb0; 1 drivers +v0xfd3730_0 .net *"_s151", 0 0, L_0xff4fe0; 1 drivers +v0xfd3810_0 .net *"_s155", 0 0, L_0xff4e90; 1 drivers +v0xfd38f0_0 .net *"_s159", 0 0, L_0xff4f30; 1 drivers +v0xfd39d0_0 .net *"_s160", 17 0, L_0xff5080; 1 drivers +v0xfd3ab0_0 .net *"_s162", 5 0, L_0xff53e0; 1 drivers +L_0x2b99d7e1a060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0xfd3b90_0 .net *"_s165", 1 0, L_0x2b99d7e1a060; 1 drivers +v0xfd5b40_2 .array/port v0xfd5b40, 2; +v0xfd3c70_0 .net *"_s173", 10 0, v0xfd5b40_2; 1 drivers +v0xfd5b40_3 .array/port v0xfd5b40, 3; +v0xfd3d50_0 .net *"_s179", 10 0, v0xfd5b40_3; 1 drivers +v0xfd5b40_0 .array/port v0xfd5b40, 0; +v0xfd3e30_0 .net *"_s185", 10 0, v0xfd5b40_0; 1 drivers +v0xfd5b40_1 .array/port v0xfd5b40, 1; +v0xfd3f10_0 .net *"_s191", 10 0, v0xfd5b40_1; 1 drivers +v0xfd3ff0_0 .net *"_s23", 0 0, L_0xff2820; 1 drivers +v0xfd40d0_0 .net *"_s27", 0 0, L_0xff2940; 1 drivers +v0xfd3320_0 .net *"_s31", 0 0, L_0xff2ab0; 1 drivers +v0xfd43a0_0 .net *"_s36", 0 0, L_0xff2d60; 1 drivers +v0xfd4480_0 .net *"_s42", 0 0, L_0xfd6500; 1 drivers +v0xfd4560_0 .net *"_s46", 0 0, L_0xff2ff0; 1 drivers +v0xfd4640_0 .net *"_s50", 0 0, L_0xff3100; 1 drivers +v0xfd4720_0 .net *"_s55", 0 0, L_0xff3360; 1 drivers +v0xfd4800_0 .net *"_s61", 0 0, L_0xff35d0; 1 drivers +v0xfd48e0_0 .net *"_s65", 0 0, L_0xff3700; 1 drivers +v0xfd49c0_0 .net *"_s69", 0 0, L_0xff3840; 1 drivers +v0xfd4aa0_0 .net *"_s74", 0 0, L_0xff37a0; 1 drivers +v0xfd4b80_0 .net *"_s80", 0 0, L_0xff3a60; 1 drivers +v0xfd4c60_0 .net *"_s84", 0 0, L_0xff3d50; 1 drivers +v0xfd4d40_0 .net *"_s88", 0 0, L_0xff3c90; 1 drivers +v0xfd4e20_0 .net *"_s93", 0 0, L_0xff3df0; 1 drivers +v0xfd4f00_0 .net *"_s99", 0 0, L_0xff40b0; 1 drivers +v0xfd4fe0_0 .net/s "accOut", 10 0, L_0xfe2320; alias, 1 drivers +v0xfd50c0_0 .net "anyHasData", 0 0, L_0xff2ea0; 1 drivers +v0xfd5180_0 .net "anyReadAck", 0 0, L_0xff3bf0; 1 drivers +v0xfd5240_0 .net "anyWantData", 0 0, L_0xff3450; 1 drivers +v0xfd5300_0 .net "anyWriteAck", 0 0, L_0xff41e0; 1 drivers +v0xfd53c0_0 .net "clk", 0 0, v0xfe2100_0; alias, 1 drivers +o0x2b99d7debef8 .functor BUFZ 15, C4; HiZ drive +v0xfd5460_0 .net "down", 14 0, o0x2b99d7debef8; 0 drivers +v0xfd5540_0 .net "downOut", 14 0, L_0xff5800; 1 drivers +v0xfd5620_0 .net "instruction", 17 0, L_0xff3090; 1 drivers +v0xfd5700 .array "instructions", 15 0, 17 0; +v0xfd57c0_0 .var "last", 2 0; +o0x2b99d7debfb8 .functor BUFZ 15, C4; HiZ drive +v0xfd58a0_0 .net "left", 14 0, o0x2b99d7debfb8; 0 drivers +v0xfd5980_0 .net "leftOut", 14 0, L_0xff5540; 1 drivers +v0xfd5a60_0 .var "mode", 2 0; +v0xfd5b40 .array/s "outVals", 2 5, 10 0; +v0xfd5c80_0 .var "phase", 2 0; +v0xfd5d60_0 .net "portsHaveData", 5 2, L_0xff2b50; 1 drivers +v0xfd2160_0 .net "portsWantData", 5 2, L_0xff31a0; 1 drivers +v0xfd41b0_0 .net "readAckIn", 5 2, L_0xff3970; 1 drivers +v0xfd4290_0 .var "readAckOut", 5 2; +v0xfd6210_0 .var "readTarget", 2 0; +v0xfd62f0_0 .var/s "readValue", 10 0; +L_0x2b99d7e1a018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0xfd63d0 .array "regVals", 0 7; +v0xfd63d0_0 .net/s v0xfd63d0 0, 10 0, L_0x2b99d7e1a018; 1 drivers +v0xfd63d0_1 .net/s v0xfd63d0 1, 10 0, L_0xff23c0; 1 drivers +v0xfd63d0_2 .net/s v0xfd63d0 2, 10 0, L_0xff2480; 1 drivers +v0xfd63d0_3 .net/s v0xfd63d0 3, 10 0, L_0xff2520; 1 drivers +v0xfd63d0_4 .net/s v0xfd63d0 4, 10 0, L_0xff25f0; 1 drivers +v0xfd63d0_5 .net/s v0xfd63d0 5, 10 0, L_0xff26f0; 1 drivers +o0x2b99d7dec378 .functor BUFZ 11, C4; HiZ drive +v0xfd63d0_6 .net/s v0xfd63d0 6, 10 0, o0x2b99d7dec378; 0 drivers +o0x2b99d7dec3a8 .functor BUFZ 11, C4; HiZ drive +v0xfd63d0_7 .net/s v0xfd63d0 7, 10 0, o0x2b99d7dec3a8; 0 drivers +v0xfd65e0_0 .net "right", 14 0, L_0x10059f0; alias, 1 drivers +v0xfd66d0_0 .net "rightOut", 14 0, L_0xff5db0; alias, 1 drivers +o0x2b99d7dec3d8 .functor BUFZ 15, C4; HiZ drive +v0xfd67a0_0 .net "up", 14 0, o0x2b99d7dec3d8; 0 drivers +v0xfd6860_0 .net "upOut", 14 0, L_0xff52f0; 1 drivers +v0xfd6940_0 .var "weHaveData", 5 2; +v0xfd6a20_0 .var "weWantData", 5 2; +v0xfd6b00_0 .net "writeAckIn", 5 2, L_0xff3ec0; 1 drivers +v0xfd6be0_0 .var "writeAckOut", 5 2; +v0xfd6cc0_0 .var "writeTarget", 2 0; +v0xfd6da0_0 .var/s "writeValue", 10 0; +L_0xff2480 .part o0x2b99d7debfb8, 0, 11; +L_0xff2520 .part L_0x10059f0, 0, 11; +L_0xff25f0 .part o0x2b99d7dec3d8, 0, 11; +L_0xff26f0 .part o0x2b99d7debef8, 0, 11; +L_0xff2820 .part o0x2b99d7debfb8, 11, 1; +L_0xff2940 .part L_0x10059f0, 11, 1; +L_0xff2ab0 .part o0x2b99d7dec3d8, 11, 1; +L_0xff2b50 .concat8 [ 1 1 1 1], L_0xff2820, L_0xff2940, L_0xff2ab0, L_0xff2d60; +L_0xff2d60 .part o0x2b99d7debef8, 11, 1; +L_0xff2ea0 .reduce/or L_0xff2b50; +L_0xfd6500 .part o0x2b99d7debfb8, 12, 1; +L_0xff2ff0 .part L_0x10059f0, 12, 1; +L_0xff3100 .part o0x2b99d7dec3d8, 12, 1; +L_0xff31a0 .concat8 [ 1 1 1 1], L_0xfd6500, L_0xff2ff0, L_0xff3100, L_0xff3360; +L_0xff3360 .part o0x2b99d7debef8, 12, 1; +L_0xff3450 .reduce/or L_0xff31a0; +L_0xff35d0 .part o0x2b99d7debfb8, 13, 1; +L_0xff3700 .part L_0x10059f0, 13, 1; +L_0xff3840 .part o0x2b99d7dec3d8, 13, 1; +L_0xff3970 .concat8 [ 1 1 1 1], L_0xff35d0, L_0xff3700, L_0xff3840, L_0xff37a0; +L_0xff37a0 .part o0x2b99d7debef8, 13, 1; +L_0xff3bf0 .reduce/or L_0xff3970; +L_0xff3a60 .part o0x2b99d7debfb8, 14, 1; +L_0xff3d50 .part L_0x10059f0, 14, 1; +L_0xff3c90 .part o0x2b99d7dec3d8, 14, 1; +L_0xff3ec0 .concat8 [ 1 1 1 1], L_0xff3a60, L_0xff3d50, L_0xff3c90, L_0xff3df0; +L_0xff3df0 .part o0x2b99d7debef8, 14, 1; +L_0xff41e0 .reduce/or L_0xff3ec0; +L_0xff40b0 .part v0xfd4290_0, 0, 1; +L_0xff43c0 .part v0xfd4290_0, 1, 1; +L_0xff42d0 .part v0xfd4290_0, 2, 1; +L_0xff45b0 .part v0xfd4290_0, 3, 1; +L_0xff44b0 .part v0xfd6be0_0, 0, 1; +L_0xff47f0 .part v0xfd6be0_0, 1, 1; +L_0xff46e0 .part v0xfd6be0_0, 2, 1; +L_0xff49b0 .part v0xfd6be0_0, 3, 1; +L_0xff4890 .part v0xfd6a20_0, 0, 1; +L_0xff4c10 .part v0xfd6a20_0, 1, 1; +L_0xff4ae0 .part v0xfd6a20_0, 2, 1; +L_0xff4df0 .part v0xfd6a20_0, 3, 1; +L_0xff4cb0 .part v0xfd6940_0, 0, 1; +L_0xff4fe0 .part v0xfd6940_0, 1, 1; +L_0xff4e90 .part v0xfd6940_0, 2, 1; +L_0xff4f30 .part v0xfd6940_0, 3, 1; +L_0xff5080 .array/port v0xfd5700, L_0xff53e0; +L_0xff53e0 .concat [ 4 2 0 0], v0xfd28f0_0, L_0x2b99d7e1a060; +LS_0xff52f0_0_0 .concat8 [ 11 1 1 1], v0xfd5b40_2, L_0xff4e90, L_0xff4ae0, L_0xff46e0; +LS_0xff52f0_0_4 .concat8 [ 1 0 0 0], L_0xff42d0; +L_0xff52f0 .concat8 [ 14 1 0 0], LS_0xff52f0_0_0, LS_0xff52f0_0_4; +LS_0xff5800_0_0 .concat8 [ 11 1 1 1], v0xfd5b40_3, L_0xff4f30, L_0xff4df0, L_0xff49b0; +LS_0xff5800_0_4 .concat8 [ 1 0 0 0], L_0xff45b0; +L_0xff5800 .concat8 [ 14 1 0 0], LS_0xff5800_0_0, LS_0xff5800_0_4; +LS_0xff5540_0_0 .concat8 [ 11 1 1 1], v0xfd5b40_0, L_0xff4cb0, L_0xff4890, L_0xff44b0; +LS_0xff5540_0_4 .concat8 [ 1 0 0 0], L_0xff40b0; +L_0xff5540 .concat8 [ 14 1 0 0], LS_0xff5540_0_0, LS_0xff5540_0_4; +LS_0xff5db0_0_0 .concat8 [ 11 1 1 1], v0xfd5b40_1, L_0xff4fe0, L_0xff4c10, L_0xff47f0; +LS_0xff5db0_0_4 .concat8 [ 1 0 0 0], L_0xff43c0; +L_0xff5db0 .concat8 [ 14 1 0 0], LS_0xff5db0_0_0, LS_0xff5db0_0_4; +L_0xff5aa0 .part L_0xff3090, 14, 4; +L_0xff61c0 .part L_0xff3090, 11, 3; +L_0xff5fd0 .part L_0xff3090, 8, 3; +L_0xff6410 .part L_0xff3090, 10, 4; +L_0xff6260 .part L_0xff3090, 0, 11; +S_0xfd7020 .scope module, "right" "tis100" 2 28, 3 49 0, S_0xf12740; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0xfd71f0 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0xfd7230 .param/str "memFile" 0 3 60, "jumpTest/right.dat"; +L_0xff6100 .functor BUFZ 11, v0xfd75a0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xff6300 .functor BUFZ 11, v0xfd75a0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xff71f0 .functor BUFZ 18, L_0xff9160, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0xfd75a0_0 .var/s "ACC", 10 0; +v0xfd76a0_0 .var/s "BAK", 10 0; +v0xfd7780_0 .net "DST", 2 0, L_0xffa2a0; 1 drivers +v0xfd7840_0 .net/s "IMM", 10 0, L_0xffa340; 1 drivers +v0xfd7920_0 .net "INST", 3 0, L_0xff9b80; 1 drivers +v0xfd7a00_0 .net "LABEL", 3 0, L_0xffa4f0; 1 drivers +v0xfd7ae0_0 .var "PC", 3 0; +v0xfd7bc0_0 .var "PCNEXT", 3 0; +v0xfd7ca0_0 .net "SRC", 2 0, L_0xffa0b0; 1 drivers +v0xfd7e10_0 .net *"_s103", 0 0, L_0xff84a0; 1 drivers +v0xfd7ef0_0 .net *"_s107", 0 0, L_0xff83b0; 1 drivers +v0xfd7fd0_0 .net *"_s111", 0 0, L_0xff8690; 1 drivers +v0xfd80b0_0 .net *"_s115", 0 0, L_0xff8590; 1 drivers +v0xfd8190_0 .net *"_s119", 0 0, L_0xff88d0; 1 drivers +v0xfd8270_0 .net *"_s123", 0 0, L_0xff87c0; 1 drivers +v0xfd8350_0 .net *"_s127", 0 0, L_0xff8a90; 1 drivers +v0xfd8430_0 .net *"_s131", 0 0, L_0xff8970; 1 drivers +v0xfd85e0_0 .net *"_s135", 0 0, L_0xff8cf0; 1 drivers +v0xfd8680_0 .net *"_s139", 0 0, L_0xff8bc0; 1 drivers +v0xfd8760_0 .net *"_s143", 0 0, L_0xff8ed0; 1 drivers +v0xfd8840_0 .net *"_s147", 0 0, L_0xff8d90; 1 drivers +v0xfd8920_0 .net *"_s151", 0 0, L_0xff90c0; 1 drivers +v0xfd8a00_0 .net *"_s155", 0 0, L_0xff8f70; 1 drivers +v0xfd8ae0_0 .net *"_s159", 0 0, L_0xff9010; 1 drivers +v0xfd8bc0_0 .net *"_s160", 17 0, L_0xff9160; 1 drivers +v0xfd8ca0_0 .net *"_s162", 5 0, L_0xff94c0; 1 drivers +L_0x2b99d7e1a0f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0xfd8d80_0 .net *"_s165", 1 0, L_0x2b99d7e1a0f0; 1 drivers +v0xfdacb0_2 .array/port v0xfdacb0, 2; +v0xfd8e60_0 .net *"_s173", 10 0, v0xfdacb0_2; 1 drivers +v0xfdacb0_3 .array/port v0xfdacb0, 3; +v0xfd8f40_0 .net *"_s179", 10 0, v0xfdacb0_3; 1 drivers +v0xfdacb0_0 .array/port v0xfdacb0, 0; +v0xfd9020_0 .net *"_s185", 10 0, v0xfdacb0_0; 1 drivers +v0xfdacb0_1 .array/port v0xfdacb0, 1; +v0xfd9100_0 .net *"_s191", 10 0, v0xfdacb0_1; 1 drivers +v0xfd91e0_0 .net *"_s23", 0 0, L_0xff6980; 1 drivers +v0xfd92c0_0 .net *"_s27", 0 0, L_0xff6ae0; 1 drivers +v0xfd8510_0 .net *"_s31", 0 0, L_0xff6bb0; 1 drivers +v0xfd9590_0 .net *"_s36", 0 0, L_0xff6e80; 1 drivers +v0xfd9670_0 .net *"_s42", 0 0, L_0xff70b0; 1 drivers +v0xfd9750_0 .net *"_s46", 0 0, L_0xff7150; 1 drivers +v0xfd9830_0 .net *"_s50", 0 0, L_0xff7260; 1 drivers +v0xfd9910_0 .net *"_s55", 0 0, L_0xff7470; 1 drivers +v0xfd99f0_0 .net *"_s61", 0 0, L_0xff76e0; 1 drivers +v0xfd9ad0_0 .net *"_s65", 0 0, L_0xff7780; 1 drivers +v0xfd9bb0_0 .net *"_s69", 0 0, L_0xff7950; 1 drivers +v0xfd9c90_0 .net *"_s74", 0 0, L_0xff78b0; 1 drivers +v0xfd9d70_0 .net *"_s80", 0 0, L_0xff7b40; 1 drivers +v0xfd9e50_0 .net *"_s84", 0 0, L_0xff7e30; 1 drivers +v0xfd9f30_0 .net *"_s88", 0 0, L_0xff7d70; 1 drivers +v0xfda010_0 .net *"_s93", 0 0, L_0xff7ed0; 1 drivers +v0xfda0f0_0 .net *"_s99", 0 0, L_0xff8190; 1 drivers +v0xfda1d0_0 .net/s "accOut", 10 0, L_0xff6100; alias, 1 drivers +v0xfda2b0_0 .net "anyHasData", 0 0, L_0xff6fc0; 1 drivers +v0xfda370_0 .net "anyReadAck", 0 0, L_0xff7cd0; 1 drivers +v0xfda430_0 .net "anyWantData", 0 0, L_0xff7560; 1 drivers +v0xfda4f0_0 .net "anyWriteAck", 0 0, L_0xff82c0; 1 drivers +v0xfda5b0_0 .net "clk", 0 0, v0xfe2100_0; alias, 1 drivers +o0x2b99d7ded128 .functor BUFZ 15, C4; HiZ drive +v0xfda650_0 .net "down", 14 0, o0x2b99d7ded128; 0 drivers +v0xfda730_0 .net "downOut", 14 0, L_0xff98e0; 1 drivers +v0xfda810_0 .net "instruction", 17 0, L_0xff71f0; 1 drivers +v0xfda8f0 .array "instructions", 15 0, 17 0; +v0xfda9b0_0 .var "last", 2 0; +v0xfdaa90_0 .net "left", 14 0, L_0x10063c0; alias, 1 drivers +v0xfdab50_0 .net "leftOut", 14 0, L_0xff9620; alias, 1 drivers +v0xfdabf0_0 .var "mode", 2 0; +v0xfdacb0 .array/s "outVals", 2 5, 10 0; +v0xfdae20_0 .var "phase", 2 0; +v0xfdaf00_0 .net "portsHaveData", 5 2, L_0xff6ca0; 1 drivers +v0xfd9360_0 .net "portsWantData", 5 2, L_0xff7300; 1 drivers +v0xfd9440_0 .net "readAckIn", 5 2, L_0xff79f0; 1 drivers +v0xfdb3b0_0 .var "readAckOut", 5 2; +v0xfdb450_0 .var "readTarget", 2 0; +v0xfdb4f0_0 .var/s "readValue", 10 0; +L_0x2b99d7e1a0a8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0xfdb590 .array "regVals", 0 7; +v0xfdb590_0 .net/s v0xfdb590 0, 10 0, L_0x2b99d7e1a0a8; 1 drivers +v0xfdb590_1 .net/s v0xfdb590 1, 10 0, L_0xff6300; 1 drivers +v0xfdb590_2 .net/s v0xfdb590 2, 10 0, L_0xff6670; 1 drivers +v0xfdb590_3 .net/s v0xfdb590 3, 10 0, L_0xff6710; 1 drivers +v0xfdb590_4 .net/s v0xfdb590 4, 10 0, L_0xff67b0; 1 drivers +v0xfdb590_5 .net/s v0xfdb590 5, 10 0, L_0xff6850; 1 drivers +o0x2b99d7ded548 .functor BUFZ 11, C4; HiZ drive +v0xfdb590_6 .net/s v0xfdb590 6, 10 0, o0x2b99d7ded548; 0 drivers +o0x2b99d7ded578 .functor BUFZ 11, C4; HiZ drive +v0xfdb590_7 .net/s v0xfdb590 7, 10 0, o0x2b99d7ded578; 0 drivers +o0x2b99d7ded5a8 .functor BUFZ 15, C4; HiZ drive +v0xfdb7a0_0 .net "right", 14 0, o0x2b99d7ded5a8; 0 drivers +v0xfdb880_0 .net "rightOut", 14 0, L_0xff9e90; 1 drivers +o0x2b99d7ded608 .functor BUFZ 15, C4; HiZ drive +v0xfdb960_0 .net "up", 14 0, o0x2b99d7ded608; 0 drivers +v0xfdba40_0 .net "upOut", 14 0, L_0xff93d0; 1 drivers +v0xfdbb20_0 .var "weHaveData", 5 2; +v0xfdbc00_0 .var "weWantData", 5 2; +v0xfdbce0_0 .net "writeAckIn", 5 2, L_0xff7fa0; 1 drivers +v0xfdbdc0_0 .var "writeAckOut", 5 2; +v0xfdbea0_0 .var "writeTarget", 2 0; +v0xfdbf80_0 .var/s "writeValue", 10 0; +L_0xff6670 .part L_0x10063c0, 0, 11; +L_0xff6710 .part o0x2b99d7ded5a8, 0, 11; +L_0xff67b0 .part o0x2b99d7ded608, 0, 11; +L_0xff6850 .part o0x2b99d7ded128, 0, 11; +L_0xff6980 .part L_0x10063c0, 11, 1; +L_0xff6ae0 .part o0x2b99d7ded5a8, 11, 1; +L_0xff6bb0 .part o0x2b99d7ded608, 11, 1; +L_0xff6ca0 .concat8 [ 1 1 1 1], L_0xff6980, L_0xff6ae0, L_0xff6bb0, L_0xff6e80; +L_0xff6e80 .part o0x2b99d7ded128, 11, 1; +L_0xff6fc0 .reduce/or L_0xff6ca0; +L_0xff70b0 .part L_0x10063c0, 12, 1; +L_0xff7150 .part o0x2b99d7ded5a8, 12, 1; +L_0xff7260 .part o0x2b99d7ded608, 12, 1; +L_0xff7300 .concat8 [ 1 1 1 1], L_0xff70b0, L_0xff7150, L_0xff7260, L_0xff7470; +L_0xff7470 .part o0x2b99d7ded128, 12, 1; +L_0xff7560 .reduce/or L_0xff7300; +L_0xff76e0 .part L_0x10063c0, 13, 1; +L_0xff7780 .part o0x2b99d7ded5a8, 13, 1; +L_0xff7950 .part o0x2b99d7ded608, 13, 1; +L_0xff79f0 .concat8 [ 1 1 1 1], L_0xff76e0, L_0xff7780, L_0xff7950, L_0xff78b0; +L_0xff78b0 .part o0x2b99d7ded128, 13, 1; +L_0xff7cd0 .reduce/or L_0xff79f0; +L_0xff7b40 .part L_0x10063c0, 14, 1; +L_0xff7e30 .part o0x2b99d7ded5a8, 14, 1; +L_0xff7d70 .part o0x2b99d7ded608, 14, 1; +L_0xff7fa0 .concat8 [ 1 1 1 1], L_0xff7b40, L_0xff7e30, L_0xff7d70, L_0xff7ed0; +L_0xff7ed0 .part o0x2b99d7ded128, 14, 1; +L_0xff82c0 .reduce/or L_0xff7fa0; +L_0xff8190 .part v0xfdb3b0_0, 0, 1; +L_0xff84a0 .part v0xfdb3b0_0, 1, 1; +L_0xff83b0 .part v0xfdb3b0_0, 2, 1; +L_0xff8690 .part v0xfdb3b0_0, 3, 1; +L_0xff8590 .part v0xfdbdc0_0, 0, 1; +L_0xff88d0 .part v0xfdbdc0_0, 1, 1; +L_0xff87c0 .part v0xfdbdc0_0, 2, 1; +L_0xff8a90 .part v0xfdbdc0_0, 3, 1; +L_0xff8970 .part v0xfdbc00_0, 0, 1; +L_0xff8cf0 .part v0xfdbc00_0, 1, 1; +L_0xff8bc0 .part v0xfdbc00_0, 2, 1; +L_0xff8ed0 .part v0xfdbc00_0, 3, 1; +L_0xff8d90 .part v0xfdbb20_0, 0, 1; +L_0xff90c0 .part v0xfdbb20_0, 1, 1; +L_0xff8f70 .part v0xfdbb20_0, 2, 1; +L_0xff9010 .part v0xfdbb20_0, 3, 1; +L_0xff9160 .array/port v0xfda8f0, L_0xff94c0; +L_0xff94c0 .concat [ 4 2 0 0], v0xfd7ae0_0, L_0x2b99d7e1a0f0; +LS_0xff93d0_0_0 .concat8 [ 11 1 1 1], v0xfdacb0_2, L_0xff8f70, L_0xff8bc0, L_0xff87c0; +LS_0xff93d0_0_4 .concat8 [ 1 0 0 0], L_0xff83b0; +L_0xff93d0 .concat8 [ 14 1 0 0], LS_0xff93d0_0_0, LS_0xff93d0_0_4; +LS_0xff98e0_0_0 .concat8 [ 11 1 1 1], v0xfdacb0_3, L_0xff9010, L_0xff8ed0, L_0xff8a90; +LS_0xff98e0_0_4 .concat8 [ 1 0 0 0], L_0xff8690; +L_0xff98e0 .concat8 [ 14 1 0 0], LS_0xff98e0_0_0, LS_0xff98e0_0_4; +LS_0xff9620_0_0 .concat8 [ 11 1 1 1], v0xfdacb0_0, L_0xff8d90, L_0xff8970, L_0xff8590; +LS_0xff9620_0_4 .concat8 [ 1 0 0 0], L_0xff8190; +L_0xff9620 .concat8 [ 14 1 0 0], LS_0xff9620_0_0, LS_0xff9620_0_4; +LS_0xff9e90_0_0 .concat8 [ 11 1 1 1], v0xfdacb0_1, L_0xff90c0, L_0xff8cf0, L_0xff88d0; +LS_0xff9e90_0_4 .concat8 [ 1 0 0 0], L_0xff84a0; +L_0xff9e90 .concat8 [ 14 1 0 0], LS_0xff9e90_0_0, LS_0xff9e90_0_4; +L_0xff9b80 .part L_0xff71f0, 14, 4; +L_0xffa2a0 .part L_0xff71f0, 11, 3; +L_0xffa0b0 .part L_0xff71f0, 8, 3; +L_0xffa4f0 .part L_0xff71f0, 10, 4; +L_0xffa340 .part L_0xff71f0, 0, 11; +S_0xfdc200 .scope module, "up" "tis100" 2 29, 3 49 0, S_0xf12740; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0xfdc420 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0xfdc460 .param/str "memFile" 0 3 60, "jumpTest/up.dat"; +L_0xffa1e0 .functor BUFZ 11, v0xfdc720_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xffa430 .functor BUFZ 11, v0xfdc720_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0xffb270 .functor BUFZ 18, L_0xffd210, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0xfdc720_0 .var/s "ACC", 10 0; +v0xfdc820_0 .var/s "BAK", 10 0; +v0xfdc900_0 .net "DST", 2 0, L_0xffe350; 1 drivers +v0xfdc9c0_0 .net/s "IMM", 10 0, L_0xffe3f0; 1 drivers +v0xfdcaa0_0 .net "INST", 3 0, L_0xffdc30; 1 drivers +v0xfdcbd0_0 .net "LABEL", 3 0, L_0xffe5a0; 1 drivers +v0xfdccb0_0 .var "PC", 3 0; +v0xfdcd90_0 .var "PCNEXT", 3 0; +v0xfdce70_0 .net "SRC", 2 0, L_0xffe160; 1 drivers +v0xfdcfe0_0 .net *"_s103", 0 0, L_0xffc550; 1 drivers +v0xfdd0c0_0 .net *"_s107", 0 0, L_0xffc460; 1 drivers +v0xfdd1a0_0 .net *"_s111", 0 0, L_0xffc740; 1 drivers +v0xfdd280_0 .net *"_s115", 0 0, L_0xffc640; 1 drivers +v0xfdd360_0 .net *"_s119", 0 0, L_0xffc980; 1 drivers +v0xfdd440_0 .net *"_s123", 0 0, L_0xffc870; 1 drivers +v0xfdd520_0 .net *"_s127", 0 0, L_0xffcb40; 1 drivers +v0xfdd600_0 .net *"_s131", 0 0, L_0xffca20; 1 drivers +v0xfdd7b0_0 .net *"_s135", 0 0, L_0xffcda0; 1 drivers +v0xfdd850_0 .net *"_s139", 0 0, L_0xffcc70; 1 drivers +v0xfdd930_0 .net *"_s143", 0 0, L_0xffcf80; 1 drivers +v0xfdda10_0 .net *"_s147", 0 0, L_0xffce40; 1 drivers +v0xfddaf0_0 .net *"_s151", 0 0, L_0xffd170; 1 drivers +v0xfddbd0_0 .net *"_s155", 0 0, L_0xffd020; 1 drivers +v0xfddcb0_0 .net *"_s159", 0 0, L_0xffd0c0; 1 drivers +v0xfddd90_0 .net *"_s160", 17 0, L_0xffd210; 1 drivers +v0xfdde70_0 .net *"_s162", 5 0, L_0xffd570; 1 drivers +L_0x2b99d7e1a180 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0xfddf50_0 .net *"_s165", 1 0, L_0x2b99d7e1a180; 1 drivers +v0xfdff10_2 .array/port v0xfdff10, 2; +v0xfde030_0 .net *"_s173", 10 0, v0xfdff10_2; 1 drivers +v0xfdff10_3 .array/port v0xfdff10, 3; +v0xfde110_0 .net *"_s179", 10 0, v0xfdff10_3; 1 drivers +v0xfdff10_0 .array/port v0xfdff10, 0; +v0xfde1f0_0 .net *"_s185", 10 0, v0xfdff10_0; 1 drivers +v0xfdff10_1 .array/port v0xfdff10, 1; +v0xfde2d0_0 .net *"_s191", 10 0, v0xfdff10_1; 1 drivers +v0xfde3b0_0 .net *"_s23", 0 0, L_0xffaa30; 1 drivers +v0xfde490_0 .net *"_s27", 0 0, L_0xffab50; 1 drivers +v0xfdd6e0_0 .net *"_s31", 0 0, L_0xffac40; 1 drivers +v0xfde760_0 .net *"_s36", 0 0, L_0xffaf10; 1 drivers +v0xfde840_0 .net *"_s42", 0 0, L_0xffb130; 1 drivers +v0xfde920_0 .net *"_s46", 0 0, L_0xffb1d0; 1 drivers +v0xfdea00_0 .net *"_s50", 0 0, L_0xffb2e0; 1 drivers +v0xfdeae0_0 .net *"_s55", 0 0, L_0xffb520; 1 drivers +v0xfdebc0_0 .net *"_s61", 0 0, L_0xffb790; 1 drivers +v0xfdeca0_0 .net *"_s65", 0 0, L_0xffb8c0; 1 drivers +v0xfded80_0 .net *"_s69", 0 0, L_0xffba90; 1 drivers +v0xfdee60_0 .net *"_s74", 0 0, L_0xffb9f0; 1 drivers +v0xfdef40_0 .net *"_s80", 0 0, L_0xffbc30; 1 drivers +v0xfdf020_0 .net *"_s84", 0 0, L_0xffbee0; 1 drivers +v0xfdf100_0 .net *"_s88", 0 0, L_0xffbe20; 1 drivers +v0xfdf1e0_0 .net *"_s93", 0 0, L_0xffbf80; 1 drivers +v0xfdf2c0_0 .net *"_s99", 0 0, L_0xffc240; 1 drivers +v0xfdf3a0_0 .net/s "accOut", 10 0, L_0xffa1e0; alias, 1 drivers +v0xfdf480_0 .net "anyHasData", 0 0, L_0xffb090; 1 drivers +v0xfdf540_0 .net "anyReadAck", 0 0, L_0xffbd30; 1 drivers +v0xfdf600_0 .net "anyWantData", 0 0, L_0xffb610; 1 drivers +v0xfdf6c0_0 .net "anyWriteAck", 0 0, L_0xffc370; 1 drivers +v0xfdf780_0 .net "clk", 0 0, v0xfe2100_0; alias, 1 drivers +v0xfdf8b0_0 .net "down", 14 0, L_0x1005720; alias, 1 drivers +v0xfdf970_0 .net "downOut", 14 0, L_0xffd990; alias, 1 drivers +v0xfdfa10_0 .net "instruction", 17 0, L_0xffb270; 1 drivers +v0xfdfad0 .array "instructions", 15 0, 17 0; +v0xfdfb90_0 .var "last", 2 0; +o0x2b99d7dee3b8 .functor BUFZ 15, C4; HiZ drive +v0xfdfc70_0 .net "left", 14 0, o0x2b99d7dee3b8; 0 drivers +v0xfdfd50_0 .net "leftOut", 14 0, L_0xffd6d0; 1 drivers +v0xfdfe30_0 .var "mode", 2 0; +v0xfdff10 .array/s "outVals", 2 5, 10 0; +v0xfe0080_0 .var "phase", 2 0; +v0xfe0160_0 .net "portsHaveData", 5 2, L_0xffad30; 1 drivers +v0xfde530_0 .net "portsWantData", 5 2, L_0xffb380; 1 drivers +v0xfde610_0 .net "readAckIn", 5 2, L_0xffbb30; 1 drivers +v0xfe0610_0 .var "readAckOut", 5 2; +v0xfe06b0_0 .var "readTarget", 2 0; +v0xfe0750_0 .var/s "readValue", 10 0; +L_0x2b99d7e1a138 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0xfe07f0 .array "regVals", 0 7; +v0xfe07f0_0 .net/s v0xfe07f0 0, 10 0, L_0x2b99d7e1a138; 1 drivers +v0xfe07f0_1 .net/s v0xfe07f0 1, 10 0, L_0xffa430; 1 drivers +v0xfe07f0_2 .net/s v0xfe07f0 2, 10 0, L_0xffa750; 1 drivers +v0xfe07f0_3 .net/s v0xfe07f0 3, 10 0, L_0xffa7f0; 1 drivers +v0xfe07f0_4 .net/s v0xfe07f0 4, 10 0, L_0xffa890; 1 drivers +v0xfe07f0_5 .net/s v0xfe07f0 5, 10 0, L_0xffa930; 1 drivers +o0x2b99d7dee778 .functor BUFZ 11, C4; HiZ drive +v0xfe07f0_6 .net/s v0xfe07f0 6, 10 0, o0x2b99d7dee778; 0 drivers +o0x2b99d7dee7a8 .functor BUFZ 11, C4; HiZ drive +v0xfe07f0_7 .net/s v0xfe07f0 7, 10 0, o0x2b99d7dee7a8; 0 drivers +o0x2b99d7dee7d8 .functor BUFZ 15, C4; HiZ drive +v0xfe0a00_0 .net "right", 14 0, o0x2b99d7dee7d8; 0 drivers +v0xfe0ae0_0 .net "rightOut", 14 0, L_0xffdf40; 1 drivers +o0x2b99d7dee838 .functor BUFZ 15, C4; HiZ drive +v0xfe0bc0_0 .net "up", 14 0, o0x2b99d7dee838; 0 drivers +v0xfe0ca0_0 .net "upOut", 14 0, L_0xffd480; 1 drivers +v0xfe0d80_0 .var "weHaveData", 5 2; +v0xfe0e60_0 .var "weWantData", 5 2; +v0xfe0f40_0 .net "writeAckIn", 5 2, L_0xffc050; 1 drivers +v0xfe1020_0 .var "writeAckOut", 5 2; +v0xfe1100_0 .var "writeTarget", 2 0; +v0xfe11e0_0 .var/s "writeValue", 10 0; +L_0xffa750 .part o0x2b99d7dee3b8, 0, 11; +L_0xffa7f0 .part o0x2b99d7dee7d8, 0, 11; +L_0xffa890 .part o0x2b99d7dee838, 0, 11; +L_0xffa930 .part L_0x1005720, 0, 11; +L_0xffaa30 .part o0x2b99d7dee3b8, 11, 1; +L_0xffab50 .part o0x2b99d7dee7d8, 11, 1; +L_0xffac40 .part o0x2b99d7dee838, 11, 1; +L_0xffad30 .concat8 [ 1 1 1 1], L_0xffaa30, L_0xffab50, L_0xffac40, L_0xffaf10; +L_0xffaf10 .part L_0x1005720, 11, 1; +L_0xffb090 .reduce/or L_0xffad30; +L_0xffb130 .part o0x2b99d7dee3b8, 12, 1; +L_0xffb1d0 .part o0x2b99d7dee7d8, 12, 1; +L_0xffb2e0 .part o0x2b99d7dee838, 12, 1; +L_0xffb380 .concat8 [ 1 1 1 1], L_0xffb130, L_0xffb1d0, L_0xffb2e0, L_0xffb520; +L_0xffb520 .part L_0x1005720, 12, 1; +L_0xffb610 .reduce/or L_0xffb380; +L_0xffb790 .part o0x2b99d7dee3b8, 13, 1; +L_0xffb8c0 .part o0x2b99d7dee7d8, 13, 1; +L_0xffba90 .part o0x2b99d7dee838, 13, 1; +L_0xffbb30 .concat8 [ 1 1 1 1], L_0xffb790, L_0xffb8c0, L_0xffba90, L_0xffb9f0; +L_0xffb9f0 .part L_0x1005720, 13, 1; +L_0xffbd30 .reduce/or L_0xffbb30; +L_0xffbc30 .part o0x2b99d7dee3b8, 14, 1; +L_0xffbee0 .part o0x2b99d7dee7d8, 14, 1; +L_0xffbe20 .part o0x2b99d7dee838, 14, 1; +L_0xffc050 .concat8 [ 1 1 1 1], L_0xffbc30, L_0xffbee0, L_0xffbe20, L_0xffbf80; +L_0xffbf80 .part L_0x1005720, 14, 1; +L_0xffc370 .reduce/or L_0xffc050; +L_0xffc240 .part v0xfe0610_0, 0, 1; +L_0xffc550 .part v0xfe0610_0, 1, 1; +L_0xffc460 .part v0xfe0610_0, 2, 1; +L_0xffc740 .part v0xfe0610_0, 3, 1; +L_0xffc640 .part v0xfe1020_0, 0, 1; +L_0xffc980 .part v0xfe1020_0, 1, 1; +L_0xffc870 .part v0xfe1020_0, 2, 1; +L_0xffcb40 .part v0xfe1020_0, 3, 1; +L_0xffca20 .part v0xfe0e60_0, 0, 1; +L_0xffcda0 .part v0xfe0e60_0, 1, 1; +L_0xffcc70 .part v0xfe0e60_0, 2, 1; +L_0xffcf80 .part v0xfe0e60_0, 3, 1; +L_0xffce40 .part v0xfe0d80_0, 0, 1; +L_0xffd170 .part v0xfe0d80_0, 1, 1; +L_0xffd020 .part v0xfe0d80_0, 2, 1; +L_0xffd0c0 .part v0xfe0d80_0, 3, 1; +L_0xffd210 .array/port v0xfdfad0, L_0xffd570; +L_0xffd570 .concat [ 4 2 0 0], v0xfdccb0_0, L_0x2b99d7e1a180; +LS_0xffd480_0_0 .concat8 [ 11 1 1 1], v0xfdff10_2, L_0xffd020, L_0xffcc70, L_0xffc870; +LS_0xffd480_0_4 .concat8 [ 1 0 0 0], L_0xffc460; +L_0xffd480 .concat8 [ 14 1 0 0], LS_0xffd480_0_0, LS_0xffd480_0_4; +LS_0xffd990_0_0 .concat8 [ 11 1 1 1], v0xfdff10_3, L_0xffd0c0, L_0xffcf80, L_0xffcb40; +LS_0xffd990_0_4 .concat8 [ 1 0 0 0], L_0xffc740; +L_0xffd990 .concat8 [ 14 1 0 0], LS_0xffd990_0_0, LS_0xffd990_0_4; +LS_0xffd6d0_0_0 .concat8 [ 11 1 1 1], v0xfdff10_0, L_0xffce40, L_0xffca20, L_0xffc640; +LS_0xffd6d0_0_4 .concat8 [ 1 0 0 0], L_0xffc240; +L_0xffd6d0 .concat8 [ 14 1 0 0], LS_0xffd6d0_0_0, LS_0xffd6d0_0_4; +LS_0xffdf40_0_0 .concat8 [ 11 1 1 1], v0xfdff10_1, L_0xffd170, L_0xffcda0, L_0xffc980; +LS_0xffdf40_0_4 .concat8 [ 1 0 0 0], L_0xffc550; +L_0xffdf40 .concat8 [ 14 1 0 0], LS_0xffdf40_0_0, LS_0xffdf40_0_4; +L_0xffdc30 .part L_0xffb270, 14, 4; +L_0xffe350 .part L_0xffb270, 11, 3; +L_0xffe160 .part L_0xffb270, 8, 3; +L_0xffe5a0 .part L_0xffb270, 10, 4; +L_0xffe3f0 .part L_0xffb270, 0, 11; + .scope S_0xfd1e20; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfd5a60_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfd5c80_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfd57c0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfd23b0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfd24b0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd28f0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd4290_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd6a20_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd6be0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd6940_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd5b40, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd5b40, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd5b40, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd5b40, 4, 0; + %vpi_call 3 187 "$readmemb", P_0xfd2030, v0xfd5700 {0 0 0}; + %end; + .thread T_0; + .scope S_0xfd1e20; +T_1 ; + %wait E_0xf45d10; + %load/vec4 v0xfd5a60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %jmp T_1.3; +T_1.0 ; + %load/vec4 v0xfd5c80_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.6, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0xfd2730_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_1.8, 5; + %load/vec4 v0xfd2ab0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_1.10, 5; + %load/vec4 v0xfd2ab0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0xfd2ab0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_1.12, 5; + %load/vec4 v0xfd5d60_0; + %load/vec4 v0xfd2ab0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0xfd2ab0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd2ab0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %load/vec4 v0xfd2ab0_0; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.15; +T_1.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %load/vec4 v0xfd2ab0_0; + %assign/vec4 v0xfd6210_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd2ab0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; + %load/vec4 v0xfd2ab0_0; + %assign/vec4 v0xfd57c0_0, 0; +T_1.15 ; + %jmp T_1.13; +T_1.12 ; + %load/vec4 v0xfd2ab0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.16, 4; + %load/vec4 v0xfd57c0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_1.18, 4; + %load/vec4 v0xfd57c0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %jmp T_1.19; +T_1.18 ; + %load/vec4 v0xfd5d60_0; + %load/vec4 v0xfd57c0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.20, 8; + %load/vec4 v0xfd57c0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd57c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %jmp T_1.21; +T_1.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %load/vec4 v0xfd57c0_0; + %assign/vec4 v0xfd6210_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd57c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; +T_1.21 ; +T_1.19 ; + %jmp T_1.17; +T_1.16 ; + %load/vec4 v0xfd2ab0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.22, 4; + %load/vec4 v0xfd50c0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.24, 8; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.27; +T_1.26 ; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.29; +T_1.28 ; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.31; +T_1.30 ; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; +T_1.32 ; +T_1.31 ; +T_1.29 ; +T_1.27 ; + %jmp T_1.25; +T_1.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %load/vec4 v0xfd2ab0_0; + %assign/vec4 v0xfd6210_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; +T_1.25 ; +T_1.22 ; +T_1.17 ; +T_1.13 ; +T_1.11 ; +T_1.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0xfd2730_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_1.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_1.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_1.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_1.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_1.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_1.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_1.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_1.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_1.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_1.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_1.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_1.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_1.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_1.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_1.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_1.49, 6; + %jmp T_1.50; +T_1.34 ; + %load/vec4 v0xfd23b0_0; + %load/vec4 v0xfd62f0_0; + %add; + %assign/vec4 v0xfd23b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.35 ; + %load/vec4 v0xfd23b0_0; + %load/vec4 v0xfd62f0_0; + %sub; + %assign/vec4 v0xfd23b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.36 ; + %load/vec4 v0xfd28f0_0; + %pad/u 11; + %load/vec4 v0xfd62f0_0; + %add; + %pad/u 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.37 ; + %load/vec4 v0xfd62f0_0; + %assign/vec4 v0xfd6da0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.38 ; + %load/vec4 v0xfd2650_0; + %assign/vec4 v0xfd6da0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.39 ; + %load/vec4 v0xfd23b0_0; + %load/vec4 v0xfd2650_0; + %add; + %assign/vec4 v0xfd23b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.40 ; + %load/vec4 v0xfd23b0_0; + %load/vec4 v0xfd2650_0; + %sub; + %assign/vec4 v0xfd23b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.41 ; + %load/vec4 v0xfd28f0_0; + %pad/u 11; + %load/vec4 v0xfd2650_0; + %add; + %pad/u 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.42 ; + %load/vec4 v0xfd24b0_0; + %assign/vec4 v0xfd23b0_0, 0; + %load/vec4 v0xfd23b0_0; + %assign/vec4 v0xfd24b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.43 ; + %load/vec4 v0xfd23b0_0; + %assign/vec4 v0xfd24b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.44 ; + %load/vec4 v0xfd23b0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0xfd23b0_0, 0; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.45 ; + %load/vec4 v0xfd2810_0; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.50; +T_1.46 ; + %load/vec4 v0xfd23b0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_1.51, 4; + %load/vec4 v0xfd2810_0; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.52; +T_1.51 ; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; +T_1.52 ; + %jmp T_1.50; +T_1.47 ; + %load/vec4 v0xfd23b0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.53, 4; + %load/vec4 v0xfd2810_0; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.54; +T_1.53 ; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; +T_1.54 ; + %jmp T_1.50; +T_1.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0xfd23b0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_1.55, 5; + %load/vec4 v0xfd2810_0; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.56; +T_1.55 ; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; +T_1.56 ; + %jmp T_1.50; +T_1.49 ; + %load/vec4 v0xfd23b0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_1.57, 5; + %load/vec4 v0xfd2810_0; + %assign/vec4 v0xfd29d0_0, 0; + %jmp T_1.58; +T_1.57 ; + %load/vec4 v0xfd28f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd29d0_0, 0; +T_1.58 ; + %jmp T_1.50; +T_1.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0xfd2730_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0xfd2730_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_1.59, 4; + %load/vec4 v0xfd2590_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0xfd2590_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfd57c0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_1.61, 9; + %load/vec4 v0xfd2590_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_1.63, 4; + %load/vec4 v0xfd6da0_0; + %assign/vec4 v0xfd23b0_0, 0; +T_1.63 ; + %jmp T_1.62; +T_1.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %load/vec4 v0xfd2590_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.65, 4; + %load/vec4 v0xfd57c0_0; + %assign/vec4 v0xfd6cc0_0, 0; + %load/vec4 v0xfd6da0_0; + %load/vec4 v0xfd57c0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd57c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %jmp T_1.66; +T_1.65 ; + %load/vec4 v0xfd2590_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.67, 4; + %load/vec4 v0xfd2590_0; + %assign/vec4 v0xfd6cc0_0, 0; + %load/vec4 v0xfd6da0_0; + %load/vec4 v0xfd2590_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd2590_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd2590_0; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.68; +T_1.67 ; + %load/vec4 v0xfd5240_0; + %flag_set/vec4 8; + %jmp/0xz T_1.69, 8; + %load/vec4 v0xfd2160_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.72; +T_1.71 ; + %load/vec4 v0xfd2160_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.74; +T_1.73 ; + %load/vec4 v0xfd2160_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.76; +T_1.75 ; + %load/vec4 v0xfd2160_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; +T_1.77 ; +T_1.76 ; +T_1.74 ; +T_1.72 ; + %jmp T_1.70; +T_1.69 ; + %load/vec4 v0xfd2590_0; + %assign/vec4 v0xfd6cc0_0, 0; +T_1.70 ; +T_1.68 ; +T_1.66 ; +T_1.62 ; +T_1.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.1 ; + %load/vec4 v0xfd5c80_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.81, 6; + %jmp T_1.82; +T_1.79 ; + %load/vec4 v0xfd6210_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.83, 4; + %load/vec4 v0xfd50c0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd6a20_0, 0, 4; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.88; +T_1.87 ; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.90; +T_1.89 ; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.92; +T_1.91 ; + %load/vec4 v0xfd5d60_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; +T_1.93 ; +T_1.92 ; +T_1.90 ; +T_1.88 ; +T_1.85 ; + %jmp T_1.84; +T_1.83 ; + %load/vec4 v0xfd5d60_0; + %load/vec4 v0xfd6210_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %load/vec4 v0xfd6210_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd63d0, 4; + %assign/vec4 v0xfd62f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd6210_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd4290_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd6210_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd6a20_0, 4, 5; + %load/vec4 v0xfd6210_0; + %assign/vec4 v0xfd57c0_0, 0; +T_1.95 ; +T_1.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.82; +T_1.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.82; +T_1.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.82; +T_1.82 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0xfd5c80_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.99, 6; + %jmp T_1.100; +T_1.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.100; +T_1.98 ; + %load/vec4 v0xfd6cc0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.101, 4; + %load/vec4 v0xfd5240_0; + %flag_set/vec4 8; + %jmp/0xz T_1.103, 8; + %load/vec4 v0xfd2160_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.106; +T_1.105 ; + %load/vec4 v0xfd2160_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.108; +T_1.107 ; + %load/vec4 v0xfd2160_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; + %jmp T_1.110; +T_1.109 ; + %load/vec4 v0xfd2160_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd6cc0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd6940_0, 4, 5; + %load/vec4 v0xfd6da0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd5b40, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd57c0_0, 0; +T_1.111 ; +T_1.110 ; +T_1.108 ; +T_1.106 ; +T_1.103 ; +T_1.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.100; +T_1.99 ; + %load/vec4 v0xfd6cc0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.113, 4; + %load/vec4 v0xfd6b00_0; + %load/vec4 v0xfd6cc0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0xfd6cc0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0xfd6940_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd5a60_0, 0; + %load/vec4 v0xfd6cc0_0; + %assign/vec4 v0xfd57c0_0, 0; +T_1.115 ; +T_1.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd5c80_0, 0; + %jmp T_1.100; +T_1.100 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.3 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1; + .scope S_0xfd1e20; +T_2 ; + %wait E_0xf235d0; + %load/vec4 v0xfd5c80_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfd5a60_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0xfd29d0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %load/vec4 v0xfd29d0_0; + %assign/vec4 v0xfd28f0_0, 0; +T_2.0 ; + %load/vec4 v0xfd5c80_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_2.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd4290_0, 0, 4; +T_2.2 ; + %jmp T_2; + .thread T_2; + .scope S_0xfd7020; +T_3 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfdabf0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfdae20_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfda9b0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfd75a0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfd76a0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd7ae0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdb3b0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdbc00_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdbdc0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdbb20_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdacb0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdacb0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdacb0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdacb0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0xfd7230, v0xfda8f0 {0 0 0}; + %end; + .thread T_3; + .scope S_0xfd7020; +T_4 ; + %wait E_0xf45d10; + %load/vec4 v0xfdabf0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0xfdae20_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.6, 6; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0xfd7920_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_4.8, 5; + %load/vec4 v0xfd7ca0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_4.10, 5; + %load/vec4 v0xfd7ca0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %jmp T_4.11; +T_4.10 ; + %load/vec4 v0xfd7ca0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_4.12, 5; + %load/vec4 v0xfdaf00_0; + %load/vec4 v0xfd7ca0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.14, 8; + %load/vec4 v0xfd7ca0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd7ca0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %load/vec4 v0xfd7ca0_0; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.15; +T_4.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %load/vec4 v0xfd7ca0_0; + %assign/vec4 v0xfdb450_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd7ca0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; + %load/vec4 v0xfd7ca0_0; + %assign/vec4 v0xfda9b0_0, 0; +T_4.15 ; + %jmp T_4.13; +T_4.12 ; + %load/vec4 v0xfd7ca0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.16, 4; + %load/vec4 v0xfda9b0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_4.18, 4; + %load/vec4 v0xfda9b0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %jmp T_4.19; +T_4.18 ; + %load/vec4 v0xfdaf00_0; + %load/vec4 v0xfda9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.20, 8; + %load/vec4 v0xfda9b0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfda9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %jmp T_4.21; +T_4.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %load/vec4 v0xfda9b0_0; + %assign/vec4 v0xfdb450_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfda9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; +T_4.21 ; +T_4.19 ; + %jmp T_4.17; +T_4.16 ; + %load/vec4 v0xfd7ca0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.22, 4; + %load/vec4 v0xfda2b0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.24, 8; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.27; +T_4.26 ; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.29; +T_4.28 ; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.31; +T_4.30 ; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; +T_4.32 ; +T_4.31 ; +T_4.29 ; +T_4.27 ; + %jmp T_4.25; +T_4.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %load/vec4 v0xfd7ca0_0; + %assign/vec4 v0xfdb450_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; +T_4.25 ; +T_4.22 ; +T_4.17 ; +T_4.13 ; +T_4.11 ; +T_4.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0xfd7920_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_4.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_4.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_4.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_4.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_4.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_4.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_4.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_4.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_4.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_4.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_4.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_4.49, 6; + %jmp T_4.50; +T_4.34 ; + %load/vec4 v0xfd75a0_0; + %load/vec4 v0xfdb4f0_0; + %add; + %assign/vec4 v0xfd75a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.35 ; + %load/vec4 v0xfd75a0_0; + %load/vec4 v0xfdb4f0_0; + %sub; + %assign/vec4 v0xfd75a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.36 ; + %load/vec4 v0xfd7ae0_0; + %pad/u 11; + %load/vec4 v0xfdb4f0_0; + %add; + %pad/u 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.37 ; + %load/vec4 v0xfdb4f0_0; + %assign/vec4 v0xfdbf80_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.38 ; + %load/vec4 v0xfd7840_0; + %assign/vec4 v0xfdbf80_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.39 ; + %load/vec4 v0xfd75a0_0; + %load/vec4 v0xfd7840_0; + %add; + %assign/vec4 v0xfd75a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.40 ; + %load/vec4 v0xfd75a0_0; + %load/vec4 v0xfd7840_0; + %sub; + %assign/vec4 v0xfd75a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.41 ; + %load/vec4 v0xfd7ae0_0; + %pad/u 11; + %load/vec4 v0xfd7840_0; + %add; + %pad/u 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.42 ; + %load/vec4 v0xfd76a0_0; + %assign/vec4 v0xfd75a0_0, 0; + %load/vec4 v0xfd75a0_0; + %assign/vec4 v0xfd76a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.43 ; + %load/vec4 v0xfd75a0_0; + %assign/vec4 v0xfd76a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.44 ; + %load/vec4 v0xfd75a0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0xfd75a0_0, 0; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.45 ; + %load/vec4 v0xfd7a00_0; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.50; +T_4.46 ; + %load/vec4 v0xfd75a0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_4.51, 4; + %load/vec4 v0xfd7a00_0; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.52; +T_4.51 ; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; +T_4.52 ; + %jmp T_4.50; +T_4.47 ; + %load/vec4 v0xfd75a0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_4.53, 4; + %load/vec4 v0xfd7a00_0; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.54; +T_4.53 ; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; +T_4.54 ; + %jmp T_4.50; +T_4.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0xfd75a0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_4.55, 5; + %load/vec4 v0xfd7a00_0; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.56; +T_4.55 ; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; +T_4.56 ; + %jmp T_4.50; +T_4.49 ; + %load/vec4 v0xfd75a0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_4.57, 5; + %load/vec4 v0xfd7a00_0; + %assign/vec4 v0xfd7bc0_0, 0; + %jmp T_4.58; +T_4.57 ; + %load/vec4 v0xfd7ae0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfd7bc0_0, 0; +T_4.58 ; + %jmp T_4.50; +T_4.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.7; +T_4.6 ; + %load/vec4 v0xfd7920_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0xfd7920_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_4.59, 4; + %load/vec4 v0xfd7780_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0xfd7780_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfda9b0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_4.61, 9; + %load/vec4 v0xfd7780_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_4.63, 4; + %load/vec4 v0xfdbf80_0; + %assign/vec4 v0xfd75a0_0, 0; +T_4.63 ; + %jmp T_4.62; +T_4.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %load/vec4 v0xfd7780_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.65, 4; + %load/vec4 v0xfda9b0_0; + %assign/vec4 v0xfdbea0_0, 0; + %load/vec4 v0xfdbf80_0; + %load/vec4 v0xfda9b0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfda9b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %jmp T_4.66; +T_4.65 ; + %load/vec4 v0xfd7780_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.67, 4; + %load/vec4 v0xfd7780_0; + %assign/vec4 v0xfdbea0_0, 0; + %load/vec4 v0xfdbf80_0; + %load/vec4 v0xfd7780_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd7780_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfd7780_0; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.68; +T_4.67 ; + %load/vec4 v0xfda430_0; + %flag_set/vec4 8; + %jmp/0xz T_4.69, 8; + %load/vec4 v0xfd9360_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.72; +T_4.71 ; + %load/vec4 v0xfd9360_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.74; +T_4.73 ; + %load/vec4 v0xfd9360_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.76; +T_4.75 ; + %load/vec4 v0xfd9360_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; +T_4.77 ; +T_4.76 ; +T_4.74 ; +T_4.72 ; + %jmp T_4.70; +T_4.69 ; + %load/vec4 v0xfd7780_0; + %assign/vec4 v0xfdbea0_0, 0; +T_4.70 ; +T_4.68 ; +T_4.66 ; +T_4.62 ; +T_4.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.1 ; + %load/vec4 v0xfdae20_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.81, 6; + %jmp T_4.82; +T_4.79 ; + %load/vec4 v0xfdb450_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.83, 4; + %load/vec4 v0xfda2b0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdbc00_0, 0, 4; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.88; +T_4.87 ; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.90; +T_4.89 ; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.92; +T_4.91 ; + %load/vec4 v0xfdaf00_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; +T_4.93 ; +T_4.92 ; +T_4.90 ; +T_4.88 ; +T_4.85 ; + %jmp T_4.84; +T_4.83 ; + %load/vec4 v0xfdaf00_0; + %load/vec4 v0xfdb450_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %load/vec4 v0xfdb450_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfdb590, 4; + %assign/vec4 v0xfdb4f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdb450_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdb3b0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdb450_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfdbc00_0, 4, 5; + %load/vec4 v0xfdb450_0; + %assign/vec4 v0xfda9b0_0, 0; +T_4.95 ; +T_4.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.82; +T_4.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.82; +T_4.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.82; +T_4.82 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0xfdae20_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.99, 6; + %jmp T_4.100; +T_4.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.100; +T_4.98 ; + %load/vec4 v0xfdbea0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.101, 4; + %load/vec4 v0xfda430_0; + %flag_set/vec4 8; + %jmp/0xz T_4.103, 8; + %load/vec4 v0xfd9360_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.106; +T_4.105 ; + %load/vec4 v0xfd9360_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.108; +T_4.107 ; + %load/vec4 v0xfd9360_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; + %jmp T_4.110; +T_4.109 ; + %load/vec4 v0xfd9360_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfdbea0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfdbb20_0, 4, 5; + %load/vec4 v0xfdbf80_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdacb0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfda9b0_0, 0; +T_4.111 ; +T_4.110 ; +T_4.108 ; +T_4.106 ; +T_4.103 ; +T_4.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.100; +T_4.99 ; + %load/vec4 v0xfdbea0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.113, 4; + %load/vec4 v0xfdbce0_0; + %load/vec4 v0xfdbea0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0xfdbea0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0xfdbb20_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdabf0_0, 0; + %load/vec4 v0xfdbea0_0; + %assign/vec4 v0xfda9b0_0, 0; +T_4.115 ; +T_4.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdae20_0, 0; + %jmp T_4.100; +T_4.100 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0xfd7020; +T_5 ; + %wait E_0xf235d0; + %load/vec4 v0xfdae20_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfdabf0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0xfd7bc0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %load/vec4 v0xfd7bc0_0; + %assign/vec4 v0xfd7ae0_0, 0; +T_5.0 ; + %load/vec4 v0xfdae20_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_5.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdb3b0_0, 0, 4; +T_5.2 ; + %jmp T_5; + .thread T_5; + .scope S_0xfdc200; +T_6 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfdfe30_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfe0080_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfdfb90_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfdc720_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfdc820_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfdccb0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfe0610_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfe0e60_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfe1020_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfe0d80_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdff10, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdff10, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdff10, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfdff10, 4, 0; + %vpi_call 3 187 "$readmemb", P_0xfdc460, v0xfdfad0 {0 0 0}; + %end; + .thread T_6; + .scope S_0xfdc200; +T_7 ; + %wait E_0xf45d10; + %load/vec4 v0xfdfe30_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.2, 6; + %jmp T_7.3; +T_7.0 ; + %load/vec4 v0xfe0080_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.6, 6; + %jmp T_7.7; +T_7.4 ; + %load/vec4 v0xfdcaa0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_7.8, 5; + %load/vec4 v0xfdce70_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_7.10, 5; + %load/vec4 v0xfdce70_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %jmp T_7.11; +T_7.10 ; + %load/vec4 v0xfdce70_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_7.12, 5; + %load/vec4 v0xfe0160_0; + %load/vec4 v0xfdce70_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.14, 8; + %load/vec4 v0xfdce70_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdce70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %load/vec4 v0xfdce70_0; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.15; +T_7.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %load/vec4 v0xfdce70_0; + %assign/vec4 v0xfe06b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdce70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; + %load/vec4 v0xfdce70_0; + %assign/vec4 v0xfdfb90_0, 0; +T_7.15 ; + %jmp T_7.13; +T_7.12 ; + %load/vec4 v0xfdce70_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.16, 4; + %load/vec4 v0xfdfb90_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_7.18, 4; + %load/vec4 v0xfdfb90_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %jmp T_7.19; +T_7.18 ; + %load/vec4 v0xfe0160_0; + %load/vec4 v0xfdfb90_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.20, 8; + %load/vec4 v0xfdfb90_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdfb90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %jmp T_7.21; +T_7.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %load/vec4 v0xfdfb90_0; + %assign/vec4 v0xfe06b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdfb90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; +T_7.21 ; +T_7.19 ; + %jmp T_7.17; +T_7.16 ; + %load/vec4 v0xfdce70_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.22, 4; + %load/vec4 v0xfdf480_0; + %flag_set/vec4 8; + %jmp/0xz T_7.24, 8; + %load/vec4 v0xfe0160_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.27; +T_7.26 ; + %load/vec4 v0xfe0160_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.29; +T_7.28 ; + %load/vec4 v0xfe0160_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.31; +T_7.30 ; + %load/vec4 v0xfe0160_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; +T_7.32 ; +T_7.31 ; +T_7.29 ; +T_7.27 ; + %jmp T_7.25; +T_7.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %load/vec4 v0xfdce70_0; + %assign/vec4 v0xfe06b0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; +T_7.25 ; +T_7.22 ; +T_7.17 ; +T_7.13 ; +T_7.11 ; +T_7.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.7; +T_7.5 ; + %load/vec4 v0xfdcaa0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_7.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_7.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_7.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_7.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_7.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_7.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_7.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_7.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_7.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_7.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_7.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_7.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_7.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_7.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_7.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_7.49, 6; + %jmp T_7.50; +T_7.34 ; + %load/vec4 v0xfdc720_0; + %load/vec4 v0xfe0750_0; + %add; + %assign/vec4 v0xfdc720_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.35 ; + %load/vec4 v0xfdc720_0; + %load/vec4 v0xfe0750_0; + %sub; + %assign/vec4 v0xfdc720_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.36 ; + %load/vec4 v0xfdccb0_0; + %pad/u 11; + %load/vec4 v0xfe0750_0; + %add; + %pad/u 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.37 ; + %load/vec4 v0xfe0750_0; + %assign/vec4 v0xfe11e0_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.38 ; + %load/vec4 v0xfdc9c0_0; + %assign/vec4 v0xfe11e0_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.39 ; + %load/vec4 v0xfdc720_0; + %load/vec4 v0xfdc9c0_0; + %add; + %assign/vec4 v0xfdc720_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.40 ; + %load/vec4 v0xfdc720_0; + %load/vec4 v0xfdc9c0_0; + %sub; + %assign/vec4 v0xfdc720_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.41 ; + %load/vec4 v0xfdccb0_0; + %pad/u 11; + %load/vec4 v0xfdc9c0_0; + %add; + %pad/u 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.42 ; + %load/vec4 v0xfdc820_0; + %assign/vec4 v0xfdc720_0, 0; + %load/vec4 v0xfdc720_0; + %assign/vec4 v0xfdc820_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.43 ; + %load/vec4 v0xfdc720_0; + %assign/vec4 v0xfdc820_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.44 ; + %load/vec4 v0xfdc720_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0xfdc720_0, 0; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.45 ; + %load/vec4 v0xfdcbd0_0; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.50; +T_7.46 ; + %load/vec4 v0xfdc720_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_7.51, 4; + %load/vec4 v0xfdcbd0_0; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.52; +T_7.51 ; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; +T_7.52 ; + %jmp T_7.50; +T_7.47 ; + %load/vec4 v0xfdc720_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_7.53, 4; + %load/vec4 v0xfdcbd0_0; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.54; +T_7.53 ; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; +T_7.54 ; + %jmp T_7.50; +T_7.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0xfdc720_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_7.55, 5; + %load/vec4 v0xfdcbd0_0; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.56; +T_7.55 ; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; +T_7.56 ; + %jmp T_7.50; +T_7.49 ; + %load/vec4 v0xfdc720_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_7.57, 5; + %load/vec4 v0xfdcbd0_0; + %assign/vec4 v0xfdcd90_0, 0; + %jmp T_7.58; +T_7.57 ; + %load/vec4 v0xfdccb0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfdcd90_0, 0; +T_7.58 ; + %jmp T_7.50; +T_7.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.7; +T_7.6 ; + %load/vec4 v0xfdcaa0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0xfdcaa0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_7.59, 4; + %load/vec4 v0xfdc900_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0xfdc900_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfdfb90_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_7.61, 9; + %load/vec4 v0xfdc900_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_7.63, 4; + %load/vec4 v0xfe11e0_0; + %assign/vec4 v0xfdc720_0, 0; +T_7.63 ; + %jmp T_7.62; +T_7.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %load/vec4 v0xfdc900_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.65, 4; + %load/vec4 v0xfdfb90_0; + %assign/vec4 v0xfe1100_0, 0; + %load/vec4 v0xfe11e0_0; + %load/vec4 v0xfdfb90_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdfb90_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %jmp T_7.66; +T_7.65 ; + %load/vec4 v0xfdc900_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.67, 4; + %load/vec4 v0xfdc900_0; + %assign/vec4 v0xfe1100_0, 0; + %load/vec4 v0xfe11e0_0; + %load/vec4 v0xfdc900_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfdc900_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfdc900_0; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.68; +T_7.67 ; + %load/vec4 v0xfdf600_0; + %flag_set/vec4 8; + %jmp/0xz T_7.69, 8; + %load/vec4 v0xfde530_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.72; +T_7.71 ; + %load/vec4 v0xfde530_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.74; +T_7.73 ; + %load/vec4 v0xfde530_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.76; +T_7.75 ; + %load/vec4 v0xfde530_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; +T_7.77 ; +T_7.76 ; +T_7.74 ; +T_7.72 ; + %jmp T_7.70; +T_7.69 ; + %load/vec4 v0xfdc900_0; + %assign/vec4 v0xfe1100_0, 0; +T_7.70 ; +T_7.68 ; +T_7.66 ; +T_7.62 ; +T_7.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.7; +T_7.7 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.1 ; + %load/vec4 v0xfe0080_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.81, 6; + %jmp T_7.82; +T_7.79 ; + %load/vec4 v0xfe06b0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.83, 4; + %load/vec4 v0xfdf480_0; + %flag_set/vec4 8; + %jmp/0xz T_7.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfe0e60_0, 0, 4; + %load/vec4 v0xfe0160_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.88; +T_7.87 ; + %load/vec4 v0xfe0160_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.90; +T_7.89 ; + %load/vec4 v0xfe0160_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.92; +T_7.91 ; + %load/vec4 v0xfe0160_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; +T_7.93 ; +T_7.92 ; +T_7.90 ; +T_7.88 ; +T_7.85 ; + %jmp T_7.84; +T_7.83 ; + %load/vec4 v0xfe0160_0; + %load/vec4 v0xfe06b0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %load/vec4 v0xfe06b0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfe07f0, 4; + %assign/vec4 v0xfe0750_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfe06b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0610_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfe06b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfe0e60_0, 4, 5; + %load/vec4 v0xfe06b0_0; + %assign/vec4 v0xfdfb90_0, 0; +T_7.95 ; +T_7.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.82; +T_7.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.82; +T_7.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.82; +T_7.82 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0xfe0080_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.99, 6; + %jmp T_7.100; +T_7.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.100; +T_7.98 ; + %load/vec4 v0xfe1100_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.101, 4; + %load/vec4 v0xfdf600_0; + %flag_set/vec4 8; + %jmp/0xz T_7.103, 8; + %load/vec4 v0xfde530_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.106; +T_7.105 ; + %load/vec4 v0xfde530_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.108; +T_7.107 ; + %load/vec4 v0xfde530_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; + %jmp T_7.110; +T_7.109 ; + %load/vec4 v0xfde530_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfe1100_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfe0d80_0, 4, 5; + %load/vec4 v0xfe11e0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfdff10, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfdfb90_0, 0; +T_7.111 ; +T_7.110 ; +T_7.108 ; +T_7.106 ; +T_7.103 ; +T_7.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.100; +T_7.99 ; + %load/vec4 v0xfe1100_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.113, 4; + %load/vec4 v0xfe0f40_0; + %load/vec4 v0xfe1100_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0xfe1100_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0xfe0d80_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfdfe30_0, 0; + %load/vec4 v0xfe1100_0; + %assign/vec4 v0xfdfb90_0, 0; +T_7.115 ; +T_7.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfe0080_0, 0; + %jmp T_7.100; +T_7.100 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.3 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7; + .scope S_0xfdc200; +T_8 ; + %wait E_0xf235d0; + %load/vec4 v0xfe0080_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfdfe30_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0xfdcd90_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0xfdcd90_0; + %assign/vec4 v0xfdccb0_0, 0; +T_8.0 ; + %load/vec4 v0xfe0080_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_8.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfe0610_0, 0, 4; +T_8.2 ; + %jmp T_8; + .thread T_8; + .scope S_0xfccc30; +T_9 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfd0840_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfd0a60_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfd05a0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfcd1b0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfcd2b0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcd6f0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd0ff0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd1820_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd19e0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd1760_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd0920, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd0920, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd0920, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfd0920, 4, 0; + %vpi_call 3 187 "$readmemb", P_0xfcce60, v0xfd04e0 {0 0 0}; + %end; + .thread T_9; + .scope S_0xfccc30; +T_10 ; + %wait E_0xf45d10; + %load/vec4 v0xfd0840_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.2, 6; + %jmp T_10.3; +T_10.0 ; + %load/vec4 v0xfd0a60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.6, 6; + %jmp T_10.7; +T_10.4 ; + %load/vec4 v0xfcd530_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_10.8, 5; + %load/vec4 v0xfcd8b0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_10.10, 5; + %load/vec4 v0xfcd8b0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %jmp T_10.11; +T_10.10 ; + %load/vec4 v0xfcd8b0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_10.12, 5; + %load/vec4 v0xfd0b40_0; + %load/vec4 v0xfcd8b0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.14, 8; + %load/vec4 v0xfcd8b0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcd8b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %load/vec4 v0xfcd8b0_0; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.15; +T_10.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %load/vec4 v0xfcd8b0_0; + %assign/vec4 v0xfd1090_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcd8b0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd1820_0, 4, 5; + %load/vec4 v0xfcd8b0_0; + %assign/vec4 v0xfd05a0_0, 0; +T_10.15 ; + %jmp T_10.13; +T_10.12 ; + %load/vec4 v0xfcd8b0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.16, 4; + %load/vec4 v0xfd05a0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_10.18, 4; + %load/vec4 v0xfd05a0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %jmp T_10.19; +T_10.18 ; + %load/vec4 v0xfd0b40_0; + %load/vec4 v0xfd05a0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.20, 8; + %load/vec4 v0xfd05a0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd05a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %jmp T_10.21; +T_10.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %load/vec4 v0xfd05a0_0; + %assign/vec4 v0xfd1090_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd05a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd1820_0, 4, 5; +T_10.21 ; +T_10.19 ; + %jmp T_10.17; +T_10.16 ; + %load/vec4 v0xfcd8b0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.22, 4; + %load/vec4 v0xfcfec0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.24, 8; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.27; +T_10.26 ; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.29; +T_10.28 ; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.31; +T_10.30 ; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; +T_10.32 ; +T_10.31 ; +T_10.29 ; +T_10.27 ; + %jmp T_10.25; +T_10.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %load/vec4 v0xfcd8b0_0; + %assign/vec4 v0xfd1090_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1820_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1820_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1820_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1820_0, 4, 5; +T_10.25 ; +T_10.22 ; +T_10.17 ; +T_10.13 ; +T_10.11 ; +T_10.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.7; +T_10.5 ; + %load/vec4 v0xfcd530_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_10.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_10.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_10.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_10.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_10.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_10.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_10.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_10.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_10.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_10.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_10.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_10.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_10.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_10.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_10.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_10.49, 6; + %jmp T_10.50; +T_10.34 ; + %load/vec4 v0xfcd1b0_0; + %load/vec4 v0xfd1130_0; + %add; + %assign/vec4 v0xfcd1b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.35 ; + %load/vec4 v0xfcd1b0_0; + %load/vec4 v0xfd1130_0; + %sub; + %assign/vec4 v0xfcd1b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.36 ; + %load/vec4 v0xfcd6f0_0; + %pad/u 11; + %load/vec4 v0xfd1130_0; + %add; + %pad/u 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.37 ; + %load/vec4 v0xfd1130_0; + %assign/vec4 v0xfd1ba0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.38 ; + %load/vec4 v0xfcd450_0; + %assign/vec4 v0xfd1ba0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.39 ; + %load/vec4 v0xfcd1b0_0; + %load/vec4 v0xfcd450_0; + %add; + %assign/vec4 v0xfcd1b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.40 ; + %load/vec4 v0xfcd1b0_0; + %load/vec4 v0xfcd450_0; + %sub; + %assign/vec4 v0xfcd1b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.41 ; + %load/vec4 v0xfcd6f0_0; + %pad/u 11; + %load/vec4 v0xfcd450_0; + %add; + %pad/u 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.42 ; + %load/vec4 v0xfcd2b0_0; + %assign/vec4 v0xfcd1b0_0, 0; + %load/vec4 v0xfcd1b0_0; + %assign/vec4 v0xfcd2b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.43 ; + %load/vec4 v0xfcd1b0_0; + %assign/vec4 v0xfcd2b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.44 ; + %load/vec4 v0xfcd1b0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0xfcd1b0_0, 0; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.45 ; + %load/vec4 v0xfcd610_0; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.50; +T_10.46 ; + %load/vec4 v0xfcd1b0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_10.51, 4; + %load/vec4 v0xfcd610_0; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.52; +T_10.51 ; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; +T_10.52 ; + %jmp T_10.50; +T_10.47 ; + %load/vec4 v0xfcd1b0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_10.53, 4; + %load/vec4 v0xfcd610_0; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.54; +T_10.53 ; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; +T_10.54 ; + %jmp T_10.50; +T_10.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0xfcd1b0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_10.55, 5; + %load/vec4 v0xfcd610_0; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.56; +T_10.55 ; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; +T_10.56 ; + %jmp T_10.50; +T_10.49 ; + %load/vec4 v0xfcd1b0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_10.57, 5; + %load/vec4 v0xfcd610_0; + %assign/vec4 v0xfcd7d0_0, 0; + %jmp T_10.58; +T_10.57 ; + %load/vec4 v0xfcd6f0_0; + %addi 1, 0, 4; + %assign/vec4 v0xfcd7d0_0, 0; +T_10.58 ; + %jmp T_10.50; +T_10.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.7; +T_10.6 ; + %load/vec4 v0xfcd530_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0xfcd530_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_10.59, 4; + %load/vec4 v0xfcd390_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0xfcd390_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfd05a0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_10.61, 9; + %load/vec4 v0xfcd390_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_10.63, 4; + %load/vec4 v0xfd1ba0_0; + %assign/vec4 v0xfcd1b0_0, 0; +T_10.63 ; + %jmp T_10.62; +T_10.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %load/vec4 v0xfcd390_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.65, 4; + %load/vec4 v0xfd05a0_0; + %assign/vec4 v0xfd1ac0_0, 0; + %load/vec4 v0xfd1ba0_0; + %load/vec4 v0xfd05a0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd05a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %jmp T_10.66; +T_10.65 ; + %load/vec4 v0xfcd390_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.67, 4; + %load/vec4 v0xfcd390_0; + %assign/vec4 v0xfd1ac0_0, 0; + %load/vec4 v0xfd1ba0_0; + %load/vec4 v0xfcd390_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcd390_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfcd390_0; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.68; +T_10.67 ; + %load/vec4 v0xfd0040_0; + %flag_set/vec4 8; + %jmp/0xz T_10.69, 8; + %load/vec4 v0xfcef70_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.72; +T_10.71 ; + %load/vec4 v0xfcef70_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.74; +T_10.73 ; + %load/vec4 v0xfcef70_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.76; +T_10.75 ; + %load/vec4 v0xfcef70_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; +T_10.77 ; +T_10.76 ; +T_10.74 ; +T_10.72 ; + %jmp T_10.70; +T_10.69 ; + %load/vec4 v0xfcd390_0; + %assign/vec4 v0xfd1ac0_0, 0; +T_10.70 ; +T_10.68 ; +T_10.66 ; +T_10.62 ; +T_10.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.7; +T_10.7 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.1 ; + %load/vec4 v0xfd0a60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.81, 6; + %jmp T_10.82; +T_10.79 ; + %load/vec4 v0xfd1090_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.83, 4; + %load/vec4 v0xfcfec0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd1820_0, 0, 4; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.88; +T_10.87 ; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.90; +T_10.89 ; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.92; +T_10.91 ; + %load/vec4 v0xfd0b40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; +T_10.93 ; +T_10.92 ; +T_10.90 ; +T_10.88 ; +T_10.85 ; + %jmp T_10.84; +T_10.83 ; + %load/vec4 v0xfd0b40_0; + %load/vec4 v0xfd1090_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %load/vec4 v0xfd1090_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfd11d0, 4; + %assign/vec4 v0xfd1130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd1090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd0ff0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfd1090_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfd1820_0, 4, 5; + %load/vec4 v0xfd1090_0; + %assign/vec4 v0xfd05a0_0, 0; +T_10.95 ; +T_10.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.82; +T_10.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.82; +T_10.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.82; +T_10.82 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0xfd0a60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.99, 6; + %jmp T_10.100; +T_10.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.100; +T_10.98 ; + %load/vec4 v0xfd1ac0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.101, 4; + %load/vec4 v0xfd0040_0; + %flag_set/vec4 8; + %jmp/0xz T_10.103, 8; + %load/vec4 v0xfcef70_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.106; +T_10.105 ; + %load/vec4 v0xfcef70_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.108; +T_10.107 ; + %load/vec4 v0xfcef70_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; + %jmp T_10.110; +T_10.109 ; + %load/vec4 v0xfcef70_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd1ac0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfd1760_0, 4, 5; + %load/vec4 v0xfd1ba0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfd0920, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfd05a0_0, 0; +T_10.111 ; +T_10.110 ; +T_10.108 ; +T_10.106 ; +T_10.103 ; +T_10.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.100; +T_10.99 ; + %load/vec4 v0xfd1ac0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.113, 4; + %load/vec4 v0xfd1900_0; + %load/vec4 v0xfd1ac0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0xfd1ac0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0xfd1760_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd0840_0, 0; + %load/vec4 v0xfd1ac0_0; + %assign/vec4 v0xfd05a0_0, 0; +T_10.115 ; +T_10.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfd0a60_0, 0; + %jmp T_10.100; +T_10.100 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.3 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10; + .scope S_0xfccc30; +T_11 ; + %wait E_0xf235d0; + %load/vec4 v0xfd0a60_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfd0840_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0xfcd7d0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0xfcd7d0_0; + %assign/vec4 v0xfcd6f0_0, 0; +T_11.0 ; + %load/vec4 v0xfd0a60_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_11.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfd0ff0_0, 0, 4; +T_11.2 ; + %jmp T_11; + .thread T_11; + .scope S_0xf727f0; +T_12 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfcb5b0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfcb7d0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0xfcb310_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xf88400_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0xfc7f60_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfc8420_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcbd60_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcc630_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcc7f0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcc550_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfcb690, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfcb690, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfcb690, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0xfcb690, 4, 0; + %vpi_call 3 187 "$readmemb", P_0xf2f600, v0xfcb250 {0 0 0}; + %end; + .thread T_12; + .scope S_0xf727f0; +T_13 ; + %wait E_0xf45d10; + %load/vec4 v0xfcb5b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.2, 6; + %jmp T_13.3; +T_13.0 ; + %load/vec4 v0xfcb7d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.6, 6; + %jmp T_13.7; +T_13.4 ; + %load/vec4 v0xfc8210_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_13.8, 5; + %load/vec4 v0xfc85e0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_13.10, 5; + %load/vec4 v0xfc85e0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %jmp T_13.11; +T_13.10 ; + %load/vec4 v0xfc85e0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_13.12, 5; + %load/vec4 v0xfcb8b0_0; + %load/vec4 v0xfc85e0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.14, 8; + %load/vec4 v0xfc85e0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfc85e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %load/vec4 v0xfc85e0_0; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.15; +T_13.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %load/vec4 v0xfc85e0_0; + %assign/vec4 v0xfcbe00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfc85e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcc630_0, 4, 5; + %load/vec4 v0xfc85e0_0; + %assign/vec4 v0xfcb310_0, 0; +T_13.15 ; + %jmp T_13.13; +T_13.12 ; + %load/vec4 v0xfc85e0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.16, 4; + %load/vec4 v0xfcb310_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_13.18, 4; + %load/vec4 v0xfcb310_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %jmp T_13.19; +T_13.18 ; + %load/vec4 v0xfcb8b0_0; + %load/vec4 v0xfcb310_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.20, 8; + %load/vec4 v0xfcb310_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcb310_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %jmp T_13.21; +T_13.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %load/vec4 v0xfcb310_0; + %assign/vec4 v0xfcbe00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcb310_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcc630_0, 4, 5; +T_13.21 ; +T_13.19 ; + %jmp T_13.17; +T_13.16 ; + %load/vec4 v0xfc85e0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.22, 4; + %load/vec4 v0xfcabf0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.24, 8; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.27; +T_13.26 ; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.29; +T_13.28 ; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.31; +T_13.30 ; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfcb310_0, 0; +T_13.32 ; +T_13.31 ; +T_13.29 ; +T_13.27 ; + %jmp T_13.25; +T_13.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %load/vec4 v0xfc85e0_0; + %assign/vec4 v0xfcbe00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc630_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc630_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc630_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc630_0, 4, 5; +T_13.25 ; +T_13.22 ; +T_13.17 ; +T_13.13 ; +T_13.11 ; +T_13.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.7; +T_13.5 ; + %load/vec4 v0xfc8210_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_13.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_13.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_13.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_13.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_13.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_13.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_13.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_13.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_13.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_13.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_13.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_13.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_13.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_13.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_13.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_13.49, 6; + %jmp T_13.50; +T_13.34 ; + %load/vec4 v0xf88400_0; + %load/vec4 v0xfcbee0_0; + %add; + %assign/vec4 v0xf88400_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.35 ; + %load/vec4 v0xf88400_0; + %load/vec4 v0xfcbee0_0; + %sub; + %assign/vec4 v0xf88400_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.36 ; + %load/vec4 v0xfc8420_0; + %pad/u 11; + %load/vec4 v0xfcbee0_0; + %add; + %pad/u 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.37 ; + %load/vec4 v0xfcbee0_0; + %assign/vec4 v0xfcc9b0_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.38 ; + %load/vec4 v0xfc8130_0; + %assign/vec4 v0xfcc9b0_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.39 ; + %load/vec4 v0xf88400_0; + %load/vec4 v0xfc8130_0; + %add; + %assign/vec4 v0xf88400_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.40 ; + %load/vec4 v0xf88400_0; + %load/vec4 v0xfc8130_0; + %sub; + %assign/vec4 v0xf88400_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.41 ; + %load/vec4 v0xfc8420_0; + %pad/u 11; + %load/vec4 v0xfc8130_0; + %add; + %pad/u 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.42 ; + %load/vec4 v0xfc7f60_0; + %assign/vec4 v0xf88400_0, 0; + %load/vec4 v0xf88400_0; + %assign/vec4 v0xfc7f60_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.43 ; + %load/vec4 v0xf88400_0; + %assign/vec4 v0xfc7f60_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.44 ; + %load/vec4 v0xf88400_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0xf88400_0, 0; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.45 ; + %load/vec4 v0xfc8340_0; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.50; +T_13.46 ; + %load/vec4 v0xf88400_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_13.51, 4; + %load/vec4 v0xfc8340_0; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.52; +T_13.51 ; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; +T_13.52 ; + %jmp T_13.50; +T_13.47 ; + %load/vec4 v0xf88400_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_13.53, 4; + %load/vec4 v0xfc8340_0; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.54; +T_13.53 ; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; +T_13.54 ; + %jmp T_13.50; +T_13.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0xf88400_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_13.55, 5; + %load/vec4 v0xfc8340_0; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.56; +T_13.55 ; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; +T_13.56 ; + %jmp T_13.50; +T_13.49 ; + %load/vec4 v0xf88400_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_13.57, 5; + %load/vec4 v0xfc8340_0; + %assign/vec4 v0xfc8500_0, 0; + %jmp T_13.58; +T_13.57 ; + %load/vec4 v0xfc8420_0; + %addi 1, 0, 4; + %assign/vec4 v0xfc8500_0, 0; +T_13.58 ; + %jmp T_13.50; +T_13.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.7; +T_13.6 ; + %load/vec4 v0xfc8210_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0xfc8210_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_13.59, 4; + %load/vec4 v0xfc8040_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0xfc8040_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfcb310_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_13.61, 9; + %load/vec4 v0xfc8040_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_13.63, 4; + %load/vec4 v0xfcc9b0_0; + %assign/vec4 v0xf88400_0, 0; +T_13.63 ; + %jmp T_13.62; +T_13.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %load/vec4 v0xfc8040_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.65, 4; + %load/vec4 v0xfcb310_0; + %assign/vec4 v0xfcc8d0_0, 0; + %load/vec4 v0xfcc9b0_0; + %load/vec4 v0xfcb310_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcb310_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %jmp T_13.66; +T_13.65 ; + %load/vec4 v0xfc8040_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.67, 4; + %load/vec4 v0xfc8040_0; + %assign/vec4 v0xfcc8d0_0, 0; + %load/vec4 v0xfcc9b0_0; + %load/vec4 v0xfc8040_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfc8040_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfc8040_0; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.68; +T_13.67 ; + %load/vec4 v0xfcad70_0; + %flag_set/vec4 8; + %jmp/0xz T_13.69, 8; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.72; +T_13.71 ; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.74; +T_13.73 ; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.76; +T_13.75 ; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfcb310_0, 0; +T_13.77 ; +T_13.76 ; +T_13.74 ; +T_13.72 ; + %jmp T_13.70; +T_13.69 ; + %load/vec4 v0xfc8040_0; + %assign/vec4 v0xfcc8d0_0, 0; +T_13.70 ; +T_13.68 ; +T_13.66 ; +T_13.62 ; +T_13.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.7; +T_13.7 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.1 ; + %load/vec4 v0xfcb7d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.81, 6; + %jmp T_13.82; +T_13.79 ; + %load/vec4 v0xfcbe00_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.83, 4; + %load/vec4 v0xfcabf0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcc630_0, 0, 4; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.88; +T_13.87 ; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.90; +T_13.89 ; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.92; +T_13.91 ; + %load/vec4 v0xfcb8b0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfcb310_0, 0; +T_13.93 ; +T_13.92 ; +T_13.90 ; +T_13.88 ; +T_13.85 ; + %jmp T_13.84; +T_13.83 ; + %load/vec4 v0xfcb8b0_0; + %load/vec4 v0xfcbe00_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %load/vec4 v0xfcbe00_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0xfcbfc0, 4; + %assign/vec4 v0xfcbee0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcbe00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcbd60_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0xfcbe00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0xfcc630_0, 4, 5; + %load/vec4 v0xfcbe00_0; + %assign/vec4 v0xfcb310_0, 0; +T_13.95 ; +T_13.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.82; +T_13.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.82; +T_13.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.82; +T_13.82 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0xfcb7d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.99, 6; + %jmp T_13.100; +T_13.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.100; +T_13.98 ; + %load/vec4 v0xfcc8d0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.101, 4; + %load/vec4 v0xfcad70_0; + %flag_set/vec4 8; + %jmp/0xz T_13.103, 8; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.106; +T_13.105 ; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.108; +T_13.107 ; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0xfcb310_0, 0; + %jmp T_13.110; +T_13.109 ; + %load/vec4 v0xfc9ca0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfcc8d0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0xfcc550_0, 4, 5; + %load/vec4 v0xfcc9b0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0xfcb690, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0xfcb310_0, 0; +T_13.111 ; +T_13.110 ; +T_13.108 ; +T_13.106 ; +T_13.103 ; +T_13.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.100; +T_13.99 ; + %load/vec4 v0xfcc8d0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.113, 4; + %load/vec4 v0xfcc710_0; + %load/vec4 v0xfcc8d0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0xfcc8d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0xfcc550_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfcb5b0_0, 0; + %load/vec4 v0xfcc8d0_0; + %assign/vec4 v0xfcb310_0, 0; +T_13.115 ; +T_13.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0xfcb7d0_0, 0; + %jmp T_13.100; +T_13.100 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.3 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13; + .scope S_0xf727f0; +T_14 ; + %wait E_0xf235d0; + %load/vec4 v0xfcb7d0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0xfcb5b0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0xfc8500_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %load/vec4 v0xfc8500_0; + %assign/vec4 v0xfc8420_0, 0; +T_14.0 ; + %load/vec4 v0xfcb7d0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_14.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0xfcbd60_0, 0, 4; +T_14.2 ; + %jmp T_14; + .thread T_14; + .scope S_0xf12740; +T_15 ; + %pushi/vec4 0, 0, 33; + %store/vec4 v0xfe2240_0, 0, 33; + %pushi/vec4 1, 0, 1; + %store/vec4 v0xfe21a0_0, 0, 1; + %pushi/vec4 0, 0, 33; + %store/vec4 v0xfe2240_0, 0, 33; +T_15.0 ; + %load/vec4 v0xfe2240_0; + %cmpi/u 10, 0, 33; + %jmp/0xz T_15.1, 5; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe2100_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0xfe2100_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe2100_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0xfe2100_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe2100_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0xfe2100_0, 0, 1; + %delay 1, 0; + %load/vec4 v0xfe2240_0; + %addi 1, 0, 33; + %store/vec4 v0xfe2240_0, 0, 33; + %jmp T_15.0; +T_15.1 ; + %load/vec4 v0xfe2060_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.2, 4; + %vpi_call 2 51 "$display", "Failed on up test of jumpTest, %d", v0xfe2060_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe21a0_0, 0, 1; +T_15.2 ; + %load/vec4 v0xfe1f20_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.4, 4; + %vpi_call 2 55 "$display", "Failed on left test of jumpTest, %d", v0xfe1f20_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe21a0_0, 0, 1; +T_15.4 ; + %load/vec4 v0xfe1fc0_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.6, 4; + %vpi_call 2 59 "$display", "Failed on right test of jumpTest, %d", v0xfe1fc0_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe21a0_0, 0, 1; +T_15.6 ; + %load/vec4 v0xfe1e80_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.8, 4; + %vpi_call 2 63 "$display", "Failed on down test of jumpTest, %d", v0xfe1e80_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe21a0_0, 0, 1; +T_15.8 ; + %load/vec4 v0xfe1d30_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.10, 4; + %vpi_call 2 67 "$display", "Failed on center test of jumpTest, %d", v0xfe1d30_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0xfe21a0_0, 0, 1; +T_15.10 ; + %load/vec4 v0xfe21a0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.12, 8; + %vpi_call 2 71 "$display", "DUT passed jumpTest" {0 0 0}; +T_15.12 ; + %end; + .thread T_15; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "jumpTest/test.v"; + "./tis100.v"; diff --git a/jumpTest/test.asm b/jumpTest/test.asm new file mode 100644 index 0000000..2916630 --- /dev/null +++ b/jumpTest/test.asm @@ -0,0 +1,31 @@ +:center +MOV 1 ACC +JMP 3 +MOV 40 ACC +JRO 0 + +:up +MOV 0 ACC +JEZ 3 +MOV 40 ACC +ADD 1 +JRO 0 + +:left +MOV 1 ACC +JNZ 3 +MOV 40 ACC +JRO 0 + +:right +MOV 1 ACC +JGZ 3 +MOV 40 ACC +JRO 0 + +:down +MOV -1 ACC +JLZ 3 +MOV 40 ACC +ADD 2 +JRO 0 diff --git a/jumpTest/test.v b/jumpTest/test.v new file mode 100644 index 0000000..8de75b5 --- /dev/null +++ b/jumpTest/test.v @@ -0,0 +1,75 @@ +`include "tis100.v" +module tis100Test(); + +reg clk; +wire signed[10:0] accOutCenter; +wire signed[10:0] accOutUp; +wire signed[10:0] accOutDown; +wire signed[10:0] accOutLeft; +wire signed[10:0] accOutRight; + +reg[32:0] i; + +wire[14:0] L2C; +wire[14:0] C2L; + +wire[14:0] R2C; +wire[14:0] C2R; + +wire[14:0] U2C; +wire[14:0] C2U; + +wire[14:0] D2C; +wire[14:0] C2D; + +reg dutPassed; + +tis100 #("jumpTest/left.dat") left( .clk(clk), .rightOut(L2C), .right(C2L), .accOut(accOutLeft)); +tis100 #("jumpTest/right.dat") right( .clk(clk), .leftOut(R2C), .left(C2R), .accOut(accOutRight)); +tis100 #("jumpTest/up.dat") up( .clk(clk), .downOut(U2C), .down(C2U), .accOut(accOutUp)); +tis100 #("jumpTest/down.dat") down( .clk(clk), .upOut(D2C), .up(C2D), .accOut(accOutDown)); +tis100 #("jumpTest/center.dat") center(.clk(clk), + .upOut(C2U), .up(U2C), + .downOut(C2D), .down(D2C), + .leftOut(C2L), .left(L2C), + .rightOut(C2R), .right(R2C), + .accOut(accOutCenter) + ); + +initial begin + i = 0; + dutPassed = 1; + for( i = 0; i<10; i=i+1) begin + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + end + if(accOutUp != 1) begin + $display("Failed on up test of jumpTest, %d", accOutUp); + dutPassed = 0; + end + if(accOutLeft != 1) begin + $display("Failed on left test of jumpTest, %d", accOutLeft); + dutPassed = 0; + end + if(accOutRight != 1) begin + $display("Failed on right test of jumpTest, %d", accOutRight); + dutPassed = 0; + end + if(accOutDown != 1) begin + $display("Failed on down test of jumpTest, %d", accOutDown); + dutPassed = 0; + end + if(accOutCenter != 1) begin + $display("Failed on center test of jumpTest, %d",accOutCenter); + dutPassed = 0; + end + if(dutPassed) begin + $display("DUT passed jumpTest"); + end +end + +endmodule diff --git a/jumpTest/up.dat b/jumpTest/up.dat new file mode 100644 index 0000000..d302a47 --- /dev/null +++ b/jumpTest/up.dat @@ -0,0 +1,16 @@ +010000100000000000 +110000110000000000 +010000100000101000 +010100000000000001 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/left.dat b/left.dat new file mode 100644 index 0000000..4350ee8 --- /dev/null +++ b/left.dat @@ -0,0 +1,2 @@ +001100101100000000 +011100000000000000 diff --git a/leftAsm.txt b/leftAsm.txt new file mode 100644 index 0000000..ad6f8f0 --- /dev/null +++ b/leftAsm.txt @@ -0,0 +1,2 @@ +MOV RIGHT ACC +JRO 0 diff --git a/mem.dat b/mem.dat new file mode 100644 index 0000000..e1e3845 --- /dev/null +++ b/mem.dat @@ -0,0 +1,15 @@ +00000000000 +10101110110 +11100100001 +10101110010 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 +00000000000 \ No newline at end of file diff --git a/regTest/center.dat b/regTest/center.dat new file mode 100644 index 0000000..cbe5732 --- /dev/null +++ b/regTest/center.dat @@ -0,0 +1,16 @@ +010000100000000011 +000100010000000000 +011000000000000001 +000000000100000000 +000000000100000000 +000000000100000000 +011000000000000111 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/regTest/down.dat b/regTest/down.dat new file mode 100644 index 0000000..2bea4af --- /dev/null +++ b/regTest/down.dat @@ -0,0 +1,16 @@ +011100000000000010 +010100000000101000 +010100000000000001 +011100000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 +000000000000000000 diff --git a/regTest/left.dat b/regTest/left.dat new file mode 100644 index 0000000..95f6689 --- /dev/null +++ b/regTest/left.dat @@ -0,0 +1,16 @@ +010000111111111111 +101000000000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/regTest/right.dat b/regTest/right.dat new file mode 100644 index 0000000..ceab32c --- /dev/null +++ b/regTest/right.dat @@ -0,0 +1,16 @@ +010000100000000101 +100000000000000000 +010000100000000001 +100100000000000000 +100000000000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/regTest/test b/regTest/test new file mode 100755 index 0000000..a91c058 --- /dev/null +++ b/regTest/test @@ -0,0 +1,6103 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x25d8690 .scope module, "tis100Test" "tis100Test" 2 2; + .timescale 0 0; +v0x26a72a0_0 .net "C2D", 14 0, L_0x26cbb80; 1 drivers +v0x26a73d0_0 .net "C2L", 14 0, L_0x26cb8a0; 1 drivers +v0x26a74e0_0 .net "C2R", 14 0, L_0x26cc270; 1 drivers +v0x26a75d0_0 .net "C2U", 14 0, L_0x26cb5d0; 1 drivers +v0x26a76e0_0 .net "D2C", 14 0, L_0x26c73a0; 1 drivers +v0x26a7840_0 .net "L2C", 14 0, L_0x26bbbe0; 1 drivers +v0x26a7950_0 .net "R2C", 14 0, L_0x26bf4b0; 1 drivers +v0x26a7a60_0 .net "U2C", 14 0, L_0x26c37e0; 1 drivers +v0x26a7b70_0 .net/s "accOutCenter", 10 0, L_0x26c81d0; 1 drivers +v0x26a7cc0_0 .net/s "accOutDown", 10 0, L_0x26c40e0; 1 drivers +v0x26a7d60_0 .net/s "accOutLeft", 10 0, L_0x26a8160; 1 drivers +v0x26a7e00_0 .net/s "accOutRight", 10 0, L_0x26bbf30; 1 drivers +v0x26a7ea0_0 .net/s "accOutUp", 10 0, L_0x26c0030; 1 drivers +v0x26a7f40_0 .var "clk", 0 0; +v0x26a7fe0_0 .var "dutPassed", 0 0; +v0x26a8080_0 .var "i", 32 0; +S_0x2601820 .scope module, "center" "tis100" 2 31, 3 49 0, S_0x25d8690; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x25f5510 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x25f5550 .param/str "memFile" 0 3 60, "regTest/center.dat"; +L_0x26c81d0 .functor BUFZ 11, v0x264e310_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26c8460 .functor BUFZ 11, v0x264e310_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26c9260 .functor BUFZ 18, L_0x26cb3e0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x264e310_0 .var/s "ACC", 10 0; +v0x268dd90_0 .var/s "BAK", 10 0; +v0x268de70_0 .net "DST", 2 0, L_0x26cc700; 1 drivers +v0x268df60_0 .net/s "IMM", 10 0, L_0x26cc7a0; 1 drivers +v0x268e040_0 .net "INST", 3 0, L_0x26cbee0; 1 drivers +v0x268e170_0 .net "LABEL", 3 0, L_0x26cc950; 1 drivers +v0x268e250_0 .var "PC", 3 0; +v0x268e330_0 .var "PCNEXT", 3 0; +v0x268e410_0 .net "SRC", 2 0, L_0x26cc510; 1 drivers +v0x268e580_0 .net *"_s103", 0 0, L_0x26ca720; 1 drivers +v0x268e660_0 .net *"_s107", 0 0, L_0x26ca630; 1 drivers +v0x268e740_0 .net *"_s111", 0 0, L_0x26ca910; 1 drivers +v0x268e820_0 .net *"_s115", 0 0, L_0x26ca810; 1 drivers +v0x268e900_0 .net *"_s119", 0 0, L_0x26cab50; 1 drivers +v0x268e9e0_0 .net *"_s123", 0 0, L_0x26caa40; 1 drivers +v0x268eac0_0 .net *"_s127", 0 0, L_0x26cad10; 1 drivers +v0x268eba0_0 .net *"_s131", 0 0, L_0x26cabf0; 1 drivers +v0x268ed50_0 .net *"_s135", 0 0, L_0x26caf70; 1 drivers +v0x268edf0_0 .net *"_s139", 0 0, L_0x26cae40; 1 drivers +v0x268eed0_0 .net *"_s143", 0 0, L_0x26cb150; 1 drivers +v0x268efb0_0 .net *"_s147", 0 0, L_0x26cb010; 1 drivers +v0x268f090_0 .net *"_s151", 0 0, L_0x26cb340; 1 drivers +v0x268f170_0 .net *"_s155", 0 0, L_0x26cb1f0; 1 drivers +v0x268f250_0 .net *"_s159", 0 0, L_0x26cb290; 1 drivers +v0x268f330_0 .net *"_s160", 17 0, L_0x26cb3e0; 1 drivers +v0x268f410_0 .net *"_s162", 5 0, L_0x26cb740; 1 drivers +L_0x2ace9a32a2a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x268f4f0_0 .net *"_s165", 1 0, L_0x2ace9a32a2a0; 1 drivers +v0x26914c0_2 .array/port v0x26914c0, 2; +v0x268f5d0_0 .net *"_s173", 10 0, v0x26914c0_2; 1 drivers +v0x26914c0_3 .array/port v0x26914c0, 3; +v0x268f6b0_0 .net *"_s179", 10 0, v0x26914c0_3; 1 drivers +v0x26914c0_0 .array/port v0x26914c0, 0; +v0x268f790_0 .net *"_s185", 10 0, v0x26914c0_0; 1 drivers +v0x26914c0_1 .array/port v0x26914c0, 1; +v0x268f870_0 .net *"_s191", 10 0, v0x26914c0_1; 1 drivers +v0x268f950_0 .net *"_s23", 0 0, L_0x26c8c00; 1 drivers +v0x268fa30_0 .net *"_s27", 0 0, L_0x26c8cd0; 1 drivers +v0x268ec80_0 .net *"_s31", 0 0, L_0x26c8da0; 1 drivers +v0x268fd00_0 .net *"_s36", 0 0, L_0x26c8f40; 1 drivers +v0x268fde0_0 .net *"_s42", 0 0, L_0x26c9120; 1 drivers +v0x268fec0_0 .net *"_s46", 0 0, L_0x26c91c0; 1 drivers +v0x268ffa0_0 .net *"_s50", 0 0, L_0x26c92d0; 1 drivers +v0x2690080_0 .net *"_s55", 0 0, L_0x26c94e0; 1 drivers +v0x2690160_0 .net *"_s61", 0 0, L_0x26c9750; 1 drivers +v0x2690240_0 .net *"_s65", 0 0, L_0x26c97f0; 1 drivers +v0x2690320_0 .net *"_s69", 0 0, L_0x26c9930; 1 drivers +v0x2690400_0 .net *"_s74", 0 0, L_0x26c9890; 1 drivers +v0x26904e0_0 .net *"_s80", 0 0, L_0x26c9b60; 1 drivers +v0x26905c0_0 .net *"_s84", 0 0, L_0x26c9f20; 1 drivers +v0x26906a0_0 .net *"_s88", 0 0, L_0x26c9d50; 1 drivers +v0x2690780_0 .net *"_s93", 0 0, L_0x26ca0d0; 1 drivers +v0x2690860_0 .net *"_s99", 0 0, L_0x26ca350; 1 drivers +v0x2690940_0 .net/s "accOut", 10 0, L_0x26c81d0; alias, 1 drivers +v0x2690a20_0 .net "anyHasData", 0 0, L_0x26c9030; 1 drivers +v0x2690ae0_0 .net "anyReadAck", 0 0, L_0x26c9c60; 1 drivers +v0x2690ba0_0 .net "anyWantData", 0 0, L_0x26c95d0; 1 drivers +v0x2690c60_0 .net "anyWriteAck", 0 0, L_0x26ca590; 1 drivers +v0x2690d20_0 .net "clk", 0 0, v0x26a7f40_0; 1 drivers +v0x2690de0_0 .net "down", 14 0, L_0x26c73a0; alias, 1 drivers +v0x2690ec0_0 .net "downOut", 14 0, L_0x26cbb80; alias, 1 drivers +v0x2690fa0_0 .net "instruction", 17 0, L_0x26c9260; 1 drivers +v0x2691080 .array "instructions", 15 0, 17 0; +v0x2691140_0 .var "last", 2 0; +v0x2691220_0 .net "left", 14 0, L_0x26bbbe0; alias, 1 drivers +v0x2691300_0 .net "leftOut", 14 0, L_0x26cb8a0; alias, 1 drivers +v0x26913e0_0 .var "mode", 2 0; +v0x26914c0 .array/s "outVals", 2 5, 10 0; +v0x2691600_0 .var "phase", 2 0; +v0x26916e0_0 .net "portsHaveData", 5 2, L_0x26c8e40; 1 drivers +v0x268fad0_0 .net "portsWantData", 5 2, L_0x26c9370; 1 drivers +v0x268fbb0_0 .net "readAckIn", 5 2, L_0x26c99d0; 1 drivers +v0x2691b90_0 .var "readAckOut", 5 2; +v0x2691c30_0 .var "readTarget", 2 0; +v0x2691d10_0 .var/s "readValue", 10 0; +L_0x2ace9a32a258 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2691df0 .array "regVals", 0 7; +v0x2691df0_0 .net/s v0x2691df0 0, 10 0, L_0x2ace9a32a258; 1 drivers +v0x2691df0_1 .net/s v0x2691df0 1, 10 0, L_0x26c8460; 1 drivers +v0x2691df0_2 .net/s v0x2691df0 2, 10 0, L_0x26c8740; 1 drivers +v0x2691df0_3 .net/s v0x2691df0 3, 10 0, L_0x26c8870; 1 drivers +v0x2691df0_4 .net/s v0x2691df0 4, 10 0, L_0x26c89a0; 1 drivers +v0x2691df0_5 .net/s v0x2691df0 5, 10 0, L_0x26c8ad0; 1 drivers +o0x2ace9a2f9eb8 .functor BUFZ 11, C4; HiZ drive +v0x2691df0_6 .net/s v0x2691df0 6, 10 0, o0x2ace9a2f9eb8; 0 drivers +o0x2ace9a2f9ee8 .functor BUFZ 11, C4; HiZ drive +v0x2691df0_7 .net/s v0x2691df0 7, 10 0, o0x2ace9a2f9ee8; 0 drivers +v0x2692000_0 .net "right", 14 0, L_0x26bf4b0; alias, 1 drivers +v0x26920e0_0 .net "rightOut", 14 0, L_0x26cc270; alias, 1 drivers +v0x26921c0_0 .net "up", 14 0, L_0x26c37e0; alias, 1 drivers +v0x26922a0_0 .net "upOut", 14 0, L_0x26cb5d0; alias, 1 drivers +v0x2692380_0 .var "weHaveData", 5 2; +v0x2692460_0 .var "weWantData", 5 2; +v0x2692540_0 .net "writeAckIn", 5 2, L_0x26ca2b0; 1 drivers +v0x2692620_0 .var "writeAckOut", 5 2; +v0x2692700_0 .var "writeTarget", 2 0; +v0x26927e0_0 .var/s "writeValue", 10 0; +E_0x25e9520 .event negedge, v0x2690d20_0; +E_0x260bcc0 .event posedge, v0x2690d20_0; +L_0x26c8740 .part L_0x26bbbe0, 0, 11; +L_0x26c8870 .part L_0x26bf4b0, 0, 11; +L_0x26c89a0 .part L_0x26c37e0, 0, 11; +L_0x26c8ad0 .part L_0x26c73a0, 0, 11; +L_0x26c8c00 .part L_0x26bbbe0, 11, 1; +L_0x26c8cd0 .part L_0x26bf4b0, 11, 1; +L_0x26c8da0 .part L_0x26c37e0, 11, 1; +L_0x26c8e40 .concat8 [ 1 1 1 1], L_0x26c8c00, L_0x26c8cd0, L_0x26c8da0, L_0x26c8f40; +L_0x26c8f40 .part L_0x26c73a0, 11, 1; +L_0x26c9030 .reduce/or L_0x26c8e40; +L_0x26c9120 .part L_0x26bbbe0, 12, 1; +L_0x26c91c0 .part L_0x26bf4b0, 12, 1; +L_0x26c92d0 .part L_0x26c37e0, 12, 1; +L_0x26c9370 .concat8 [ 1 1 1 1], L_0x26c9120, L_0x26c91c0, L_0x26c92d0, L_0x26c94e0; +L_0x26c94e0 .part L_0x26c73a0, 12, 1; +L_0x26c95d0 .reduce/or L_0x26c9370; +L_0x26c9750 .part L_0x26bbbe0, 13, 1; +L_0x26c97f0 .part L_0x26bf4b0, 13, 1; +L_0x26c9930 .part L_0x26c37e0, 13, 1; +L_0x26c99d0 .concat8 [ 1 1 1 1], L_0x26c9750, L_0x26c97f0, L_0x26c9930, L_0x26c9890; +L_0x26c9890 .part L_0x26c73a0, 13, 1; +L_0x26c9c60 .reduce/or L_0x26c99d0; +L_0x26c9b60 .part L_0x26bbbe0, 14, 1; +L_0x26c9f20 .part L_0x26bf4b0, 14, 1; +L_0x26c9d50 .part L_0x26c37e0, 14, 1; +L_0x26ca2b0 .concat8 [ 1 1 1 1], L_0x26c9b60, L_0x26c9f20, L_0x26c9d50, L_0x26ca0d0; +L_0x26ca0d0 .part L_0x26c73a0, 14, 1; +L_0x26ca590 .reduce/or L_0x26ca2b0; +L_0x26ca350 .part v0x2691b90_0, 0, 1; +L_0x26ca720 .part v0x2691b90_0, 1, 1; +L_0x26ca630 .part v0x2691b90_0, 2, 1; +L_0x26ca910 .part v0x2691b90_0, 3, 1; +L_0x26ca810 .part v0x2692620_0, 0, 1; +L_0x26cab50 .part v0x2692620_0, 1, 1; +L_0x26caa40 .part v0x2692620_0, 2, 1; +L_0x26cad10 .part v0x2692620_0, 3, 1; +L_0x26cabf0 .part v0x2692460_0, 0, 1; +L_0x26caf70 .part v0x2692460_0, 1, 1; +L_0x26cae40 .part v0x2692460_0, 2, 1; +L_0x26cb150 .part v0x2692460_0, 3, 1; +L_0x26cb010 .part v0x2692380_0, 0, 1; +L_0x26cb340 .part v0x2692380_0, 1, 1; +L_0x26cb1f0 .part v0x2692380_0, 2, 1; +L_0x26cb290 .part v0x2692380_0, 3, 1; +L_0x26cb3e0 .array/port v0x2691080, L_0x26cb740; +L_0x26cb740 .concat [ 4 2 0 0], v0x268e250_0, L_0x2ace9a32a2a0; +LS_0x26cb5d0_0_0 .concat8 [ 11 1 1 1], v0x26914c0_2, L_0x26cb1f0, L_0x26cae40, L_0x26caa40; +LS_0x26cb5d0_0_4 .concat8 [ 1 0 0 0], L_0x26ca630; +L_0x26cb5d0 .concat8 [ 14 1 0 0], LS_0x26cb5d0_0_0, LS_0x26cb5d0_0_4; +LS_0x26cbb80_0_0 .concat8 [ 11 1 1 1], v0x26914c0_3, L_0x26cb290, L_0x26cb150, L_0x26cad10; +LS_0x26cbb80_0_4 .concat8 [ 1 0 0 0], L_0x26ca910; +L_0x26cbb80 .concat8 [ 14 1 0 0], LS_0x26cbb80_0_0, LS_0x26cbb80_0_4; +LS_0x26cb8a0_0_0 .concat8 [ 11 1 1 1], v0x26914c0_0, L_0x26cb010, L_0x26cabf0, L_0x26ca810; +LS_0x26cb8a0_0_4 .concat8 [ 1 0 0 0], L_0x26ca350; +L_0x26cb8a0 .concat8 [ 14 1 0 0], LS_0x26cb8a0_0_0, LS_0x26cb8a0_0_4; +LS_0x26cc270_0_0 .concat8 [ 11 1 1 1], v0x26914c0_1, L_0x26cb340, L_0x26caf70, L_0x26cab50; +LS_0x26cc270_0_4 .concat8 [ 1 0 0 0], L_0x26ca720; +L_0x26cc270 .concat8 [ 14 1 0 0], LS_0x26cc270_0_0, LS_0x26cc270_0_4; +L_0x26cbee0 .part L_0x26c9260, 14, 4; +L_0x26cc700 .part L_0x26c9260, 11, 3; +L_0x26cc510 .part L_0x26c9260, 8, 3; +L_0x26cc950 .part L_0x26c9260, 10, 4; +L_0x26cc7a0 .part L_0x26c9260, 0, 11; +S_0x2692a60 .scope module, "down" "tis100" 2 30, 3 49 0, S_0x25d8690; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x2692c50 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x2692c90 .param/str "memFile" 0 3 60, "regTest/down.dat"; +L_0x26c40e0 .functor BUFZ 11, v0x2692f90_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26c42e0 .functor BUFZ 11, v0x2692f90_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26c51a0 .functor BUFZ 18, L_0x26c7110, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x2692f90_0 .var/s "ACC", 10 0; +v0x2693090_0 .var/s "BAK", 10 0; +v0x2693170_0 .net "DST", 2 0, L_0x26c8290; 1 drivers +v0x2693230_0 .net/s "IMM", 10 0, L_0x26c8330; 1 drivers +v0x2693310_0 .net "INST", 3 0, L_0x26c7b70; 1 drivers +v0x2693440_0 .net "LABEL", 3 0, L_0x26c84e0; 1 drivers +v0x2693520_0 .var "PC", 3 0; +v0x2693600_0 .var "PCNEXT", 3 0; +v0x26936e0_0 .net "SRC", 2 0, L_0x26c80a0; 1 drivers +v0x2693850_0 .net *"_s103", 0 0, L_0x26c6450; 1 drivers +v0x2693930_0 .net *"_s107", 0 0, L_0x26c6360; 1 drivers +v0x2693a10_0 .net *"_s111", 0 0, L_0x26c6640; 1 drivers +v0x2693af0_0 .net *"_s115", 0 0, L_0x26c6540; 1 drivers +v0x2693bd0_0 .net *"_s119", 0 0, L_0x26c6880; 1 drivers +v0x2693cb0_0 .net *"_s123", 0 0, L_0x26c6770; 1 drivers +v0x2693d90_0 .net *"_s127", 0 0, L_0x26c6a40; 1 drivers +v0x2693e70_0 .net *"_s131", 0 0, L_0x26c6920; 1 drivers +v0x2694020_0 .net *"_s135", 0 0, L_0x26c6ca0; 1 drivers +v0x26940c0_0 .net *"_s139", 0 0, L_0x26c6b70; 1 drivers +v0x26941a0_0 .net *"_s143", 0 0, L_0x26c6e80; 1 drivers +v0x2694280_0 .net *"_s147", 0 0, L_0x26c6d40; 1 drivers +v0x2694360_0 .net *"_s151", 0 0, L_0x26c7070; 1 drivers +v0x2694440_0 .net *"_s155", 0 0, L_0x26c6f20; 1 drivers +v0x2694520_0 .net *"_s159", 0 0, L_0x26c6fc0; 1 drivers +v0x2694600_0 .net *"_s160", 17 0, L_0x26c7110; 1 drivers +v0x26946e0_0 .net *"_s162", 5 0, L_0x26c7470; 1 drivers +L_0x2ace9a32a210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x26947c0_0 .net *"_s165", 1 0, L_0x2ace9a32a210; 1 drivers +v0x2696750_2 .array/port v0x2696750, 2; +v0x26948a0_0 .net *"_s173", 10 0, v0x2696750_2; 1 drivers +v0x2696750_3 .array/port v0x2696750, 3; +v0x2694980_0 .net *"_s179", 10 0, v0x2696750_3; 1 drivers +v0x2696750_0 .array/port v0x2696750, 0; +v0x2694a60_0 .net *"_s185", 10 0, v0x2696750_0; 1 drivers +v0x2696750_1 .array/port v0x2696750, 1; +v0x2694b40_0 .net *"_s191", 10 0, v0x2696750_1; 1 drivers +v0x2694c20_0 .net *"_s23", 0 0, L_0x26c4930; 1 drivers +v0x2694d00_0 .net *"_s27", 0 0, L_0x26c4a50; 1 drivers +v0x2693f50_0 .net *"_s31", 0 0, L_0x26c4b40; 1 drivers +v0x2694fd0_0 .net *"_s36", 0 0, L_0x26c4e30; 1 drivers +v0x26950b0_0 .net *"_s42", 0 0, L_0x26c5060; 1 drivers +v0x2695190_0 .net *"_s46", 0 0, L_0x26c5100; 1 drivers +v0x2695270_0 .net *"_s50", 0 0, L_0x26c5210; 1 drivers +v0x2695350_0 .net *"_s55", 0 0, L_0x26c5420; 1 drivers +v0x2695430_0 .net *"_s61", 0 0, L_0x26c5690; 1 drivers +v0x2695510_0 .net *"_s65", 0 0, L_0x26c57c0; 1 drivers +v0x26955f0_0 .net *"_s69", 0 0, L_0x26c5990; 1 drivers +v0x26956d0_0 .net *"_s74", 0 0, L_0x26c58f0; 1 drivers +v0x26957b0_0 .net *"_s80", 0 0, L_0x26c5b20; 1 drivers +v0x2695890_0 .net *"_s84", 0 0, L_0x26c5e10; 1 drivers +v0x2695970_0 .net *"_s88", 0 0, L_0x26c5d50; 1 drivers +v0x2695a50_0 .net *"_s93", 0 0, L_0x26c5eb0; 1 drivers +v0x2695b30_0 .net *"_s99", 0 0, L_0x26c6140; 1 drivers +v0x2695c10_0 .net/s "accOut", 10 0, L_0x26c40e0; alias, 1 drivers +v0x2695cf0_0 .net "anyHasData", 0 0, L_0x26c4f70; 1 drivers +v0x2695db0_0 .net "anyReadAck", 0 0, L_0x26c5cb0; 1 drivers +v0x2695e70_0 .net "anyWantData", 0 0, L_0x26c5510; 1 drivers +v0x2695f30_0 .net "anyWriteAck", 0 0, L_0x26c6270; 1 drivers +v0x2695ff0_0 .net "clk", 0 0, v0x26a7f40_0; alias, 1 drivers +o0x2ace9a2facc8 .functor BUFZ 15, C4; HiZ drive +v0x2696090_0 .net "down", 14 0, o0x2ace9a2facc8; 0 drivers +v0x2696150_0 .net "downOut", 14 0, L_0x26c7890; 1 drivers +v0x2696230_0 .net "instruction", 17 0, L_0x26c51a0; 1 drivers +v0x2696310 .array "instructions", 15 0, 17 0; +v0x26963d0_0 .var "last", 2 0; +o0x2ace9a2fad88 .functor BUFZ 15, C4; HiZ drive +v0x26964b0_0 .net "left", 14 0, o0x2ace9a2fad88; 0 drivers +v0x2696590_0 .net "leftOut", 14 0, L_0x26c75d0; 1 drivers +v0x2696670_0 .var "mode", 2 0; +v0x2696750 .array/s "outVals", 2 5, 10 0; +v0x2696890_0 .var "phase", 2 0; +v0x2696970_0 .net "portsHaveData", 5 2, L_0x26c4c70; 1 drivers +v0x2694da0_0 .net "portsWantData", 5 2, L_0x26c52b0; 1 drivers +v0x2694e80_0 .net "readAckIn", 5 2, L_0x26c5a30; 1 drivers +v0x2696e20_0 .var "readAckOut", 5 2; +v0x2696ec0_0 .var "readTarget", 2 0; +v0x2696f60_0 .var/s "readValue", 10 0; +L_0x2ace9a32a1c8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x2697000 .array "regVals", 0 7; +v0x2697000_0 .net/s v0x2697000 0, 10 0, L_0x2ace9a32a1c8; 1 drivers +v0x2697000_1 .net/s v0x2697000 1, 10 0, L_0x26c42e0; 1 drivers +v0x2697000_2 .net/s v0x2697000 2, 10 0, L_0x26c4650; 1 drivers +v0x2697000_3 .net/s v0x2697000 3, 10 0, L_0x26c46f0; 1 drivers +v0x2697000_4 .net/s v0x2697000 4, 10 0, L_0x26c4790; 1 drivers +v0x2697000_5 .net/s v0x2697000 5, 10 0, L_0x26c4830; 1 drivers +o0x2ace9a2fb148 .functor BUFZ 11, C4; HiZ drive +v0x2697000_6 .net/s v0x2697000 6, 10 0, o0x2ace9a2fb148; 0 drivers +o0x2ace9a2fb178 .functor BUFZ 11, C4; HiZ drive +v0x2697000_7 .net/s v0x2697000 7, 10 0, o0x2ace9a2fb178; 0 drivers +o0x2ace9a2fb1a8 .functor BUFZ 15, C4; HiZ drive +v0x2697210_0 .net "right", 14 0, o0x2ace9a2fb1a8; 0 drivers +v0x26972f0_0 .net "rightOut", 14 0, L_0x26c7e80; 1 drivers +v0x26973d0_0 .net "up", 14 0, L_0x26cbb80; alias, 1 drivers +v0x26974c0_0 .net "upOut", 14 0, L_0x26c73a0; alias, 1 drivers +v0x2697590_0 .var "weHaveData", 5 2; +v0x2697650_0 .var "weWantData", 5 2; +v0x2697730_0 .net "writeAckIn", 5 2, L_0x26c5f80; 1 drivers +v0x2697810_0 .var "writeAckOut", 5 2; +v0x26978f0_0 .var "writeTarget", 2 0; +v0x26979d0_0 .var/s "writeValue", 10 0; +L_0x26c4650 .part o0x2ace9a2fad88, 0, 11; +L_0x26c46f0 .part o0x2ace9a2fb1a8, 0, 11; +L_0x26c4790 .part L_0x26cbb80, 0, 11; +L_0x26c4830 .part o0x2ace9a2facc8, 0, 11; +L_0x26c4930 .part o0x2ace9a2fad88, 11, 1; +L_0x26c4a50 .part o0x2ace9a2fb1a8, 11, 1; +L_0x26c4b40 .part L_0x26cbb80, 11, 1; +L_0x26c4c70 .concat8 [ 1 1 1 1], L_0x26c4930, L_0x26c4a50, L_0x26c4b40, L_0x26c4e30; +L_0x26c4e30 .part o0x2ace9a2facc8, 11, 1; +L_0x26c4f70 .reduce/or L_0x26c4c70; +L_0x26c5060 .part o0x2ace9a2fad88, 12, 1; +L_0x26c5100 .part o0x2ace9a2fb1a8, 12, 1; +L_0x26c5210 .part L_0x26cbb80, 12, 1; +L_0x26c52b0 .concat8 [ 1 1 1 1], L_0x26c5060, L_0x26c5100, L_0x26c5210, L_0x26c5420; +L_0x26c5420 .part o0x2ace9a2facc8, 12, 1; +L_0x26c5510 .reduce/or L_0x26c52b0; +L_0x26c5690 .part o0x2ace9a2fad88, 13, 1; +L_0x26c57c0 .part o0x2ace9a2fb1a8, 13, 1; +L_0x26c5990 .part L_0x26cbb80, 13, 1; +L_0x26c5a30 .concat8 [ 1 1 1 1], L_0x26c5690, L_0x26c57c0, L_0x26c5990, L_0x26c58f0; +L_0x26c58f0 .part o0x2ace9a2facc8, 13, 1; +L_0x26c5cb0 .reduce/or L_0x26c5a30; +L_0x26c5b20 .part o0x2ace9a2fad88, 14, 1; +L_0x26c5e10 .part o0x2ace9a2fb1a8, 14, 1; +L_0x26c5d50 .part L_0x26cbb80, 14, 1; +L_0x26c5f80 .concat8 [ 1 1 1 1], L_0x26c5b20, L_0x26c5e10, L_0x26c5d50, L_0x26c5eb0; +L_0x26c5eb0 .part o0x2ace9a2facc8, 14, 1; +L_0x26c6270 .reduce/or L_0x26c5f80; +L_0x26c6140 .part v0x2696e20_0, 0, 1; +L_0x26c6450 .part v0x2696e20_0, 1, 1; +L_0x26c6360 .part v0x2696e20_0, 2, 1; +L_0x26c6640 .part v0x2696e20_0, 3, 1; +L_0x26c6540 .part v0x2697810_0, 0, 1; +L_0x26c6880 .part v0x2697810_0, 1, 1; +L_0x26c6770 .part v0x2697810_0, 2, 1; +L_0x26c6a40 .part v0x2697810_0, 3, 1; +L_0x26c6920 .part v0x2697650_0, 0, 1; +L_0x26c6ca0 .part v0x2697650_0, 1, 1; +L_0x26c6b70 .part v0x2697650_0, 2, 1; +L_0x26c6e80 .part v0x2697650_0, 3, 1; +L_0x26c6d40 .part v0x2697590_0, 0, 1; +L_0x26c7070 .part v0x2697590_0, 1, 1; +L_0x26c6f20 .part v0x2697590_0, 2, 1; +L_0x26c6fc0 .part v0x2697590_0, 3, 1; +L_0x26c7110 .array/port v0x2696310, L_0x26c7470; +L_0x26c7470 .concat [ 4 2 0 0], v0x2693520_0, L_0x2ace9a32a210; +LS_0x26c73a0_0_0 .concat8 [ 11 1 1 1], v0x2696750_2, L_0x26c6f20, L_0x26c6b70, L_0x26c6770; +LS_0x26c73a0_0_4 .concat8 [ 1 0 0 0], L_0x26c6360; +L_0x26c73a0 .concat8 [ 14 1 0 0], LS_0x26c73a0_0_0, LS_0x26c73a0_0_4; +LS_0x26c7890_0_0 .concat8 [ 11 1 1 1], v0x2696750_3, L_0x26c6fc0, L_0x26c6e80, L_0x26c6a40; +LS_0x26c7890_0_4 .concat8 [ 1 0 0 0], L_0x26c6640; +L_0x26c7890 .concat8 [ 14 1 0 0], LS_0x26c7890_0_0, LS_0x26c7890_0_4; +LS_0x26c75d0_0_0 .concat8 [ 11 1 1 1], v0x2696750_0, L_0x26c6d40, L_0x26c6920, L_0x26c6540; +LS_0x26c75d0_0_4 .concat8 [ 1 0 0 0], L_0x26c6140; +L_0x26c75d0 .concat8 [ 14 1 0 0], LS_0x26c75d0_0_0, LS_0x26c75d0_0_4; +LS_0x26c7e80_0_0 .concat8 [ 11 1 1 1], v0x2696750_1, L_0x26c7070, L_0x26c6ca0, L_0x26c6880; +LS_0x26c7e80_0_4 .concat8 [ 1 0 0 0], L_0x26c6450; +L_0x26c7e80 .concat8 [ 14 1 0 0], LS_0x26c7e80_0_0, LS_0x26c7e80_0_4; +L_0x26c7b70 .part L_0x26c51a0, 14, 4; +L_0x26c8290 .part L_0x26c51a0, 11, 3; +L_0x26c80a0 .part L_0x26c51a0, 8, 3; +L_0x26c84e0 .part L_0x26c51a0, 10, 4; +L_0x26c8330 .part L_0x26c51a0, 0, 11; +S_0x2697c50 .scope module, "left" "tis100" 2 27, 3 49 0, S_0x25d8690; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x2697e50 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x2697e90 .param/str "memFile" 0 3 60, "regTest/left.dat"; +L_0x26a8160 .functor BUFZ 11, v0x26980f0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26b8200 .functor BUFZ 11, v0x26980f0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26b8f70 .functor BUFZ 18, L_0x26bae70, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x26980f0_0 .var/s "ACC", 10 0; +v0x26981b0_0 .var/s "BAK", 10 0; +v0x2698290_0 .net "DST", 2 0, L_0x26bbff0; 1 drivers +v0x2698380_0 .net/s "IMM", 10 0, L_0x26bc090; 1 drivers +v0x2698460_0 .net "INST", 3 0, L_0x26bb8d0; 1 drivers +v0x2698590_0 .net "LABEL", 3 0, L_0x26bc240; 1 drivers +v0x2698670_0 .var "PC", 3 0; +v0x2698750_0 .var "PCNEXT", 3 0; +v0x2698830_0 .net "SRC", 2 0, L_0x26bbe00; 1 drivers +v0x26989a0_0 .net *"_s103", 0 0, L_0x26ba1b0; 1 drivers +v0x2698a80_0 .net *"_s107", 0 0, L_0x26ba0c0; 1 drivers +v0x2698b60_0 .net *"_s111", 0 0, L_0x26ba3a0; 1 drivers +v0x2698c40_0 .net *"_s115", 0 0, L_0x26ba2a0; 1 drivers +v0x2698d20_0 .net *"_s119", 0 0, L_0x26ba5e0; 1 drivers +v0x2698e00_0 .net *"_s123", 0 0, L_0x26ba4d0; 1 drivers +v0x2698ee0_0 .net *"_s127", 0 0, L_0x26ba7a0; 1 drivers +v0x2698fc0_0 .net *"_s131", 0 0, L_0x26ba680; 1 drivers +v0x2699170_0 .net *"_s135", 0 0, L_0x26baa00; 1 drivers +v0x2699210_0 .net *"_s139", 0 0, L_0x26ba8d0; 1 drivers +v0x26992f0_0 .net *"_s143", 0 0, L_0x26babe0; 1 drivers +v0x26993d0_0 .net *"_s147", 0 0, L_0x26baaa0; 1 drivers +v0x26994b0_0 .net *"_s151", 0 0, L_0x26badd0; 1 drivers +v0x2699590_0 .net *"_s155", 0 0, L_0x26bac80; 1 drivers +v0x2699670_0 .net *"_s159", 0 0, L_0x26bad20; 1 drivers +v0x2699750_0 .net *"_s160", 17 0, L_0x26bae70; 1 drivers +v0x2699830_0 .net *"_s162", 5 0, L_0x26bb1d0; 1 drivers +L_0x2ace9a32a060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x2699910_0 .net *"_s165", 1 0, L_0x2ace9a32a060; 1 drivers +v0x269b8c0_2 .array/port v0x269b8c0, 2; +v0x26999f0_0 .net *"_s173", 10 0, v0x269b8c0_2; 1 drivers +v0x269b8c0_3 .array/port v0x269b8c0, 3; +v0x2699ad0_0 .net *"_s179", 10 0, v0x269b8c0_3; 1 drivers +v0x269b8c0_0 .array/port v0x269b8c0, 0; +v0x2699bb0_0 .net *"_s185", 10 0, v0x269b8c0_0; 1 drivers +v0x269b8c0_1 .array/port v0x269b8c0, 1; +v0x2699c90_0 .net *"_s191", 10 0, v0x269b8c0_1; 1 drivers +v0x2699d70_0 .net *"_s23", 0 0, L_0x26b8660; 1 drivers +v0x2699e50_0 .net *"_s27", 0 0, L_0x26b8780; 1 drivers +v0x26990a0_0 .net *"_s31", 0 0, L_0x26b88f0; 1 drivers +v0x269a120_0 .net *"_s36", 0 0, L_0x26b8ba0; 1 drivers +v0x269a200_0 .net *"_s42", 0 0, L_0x26b8e30; 1 drivers +v0x269a2e0_0 .net *"_s46", 0 0, L_0x26b8ed0; 1 drivers +v0x269a3c0_0 .net *"_s50", 0 0, L_0x269c340; 1 drivers +v0x269a4a0_0 .net *"_s55", 0 0, L_0x26b9150; 1 drivers +v0x269a580_0 .net *"_s61", 0 0, L_0x26b93c0; 1 drivers +v0x269a660_0 .net *"_s65", 0 0, L_0x26b94f0; 1 drivers +v0x269a740_0 .net *"_s69", 0 0, L_0x26b9630; 1 drivers +v0x269a820_0 .net *"_s74", 0 0, L_0x26b9590; 1 drivers +v0x269a900_0 .net *"_s80", 0 0, L_0x26b9850; 1 drivers +v0x269a9e0_0 .net *"_s84", 0 0, L_0x26b9b40; 1 drivers +v0x269aac0_0 .net *"_s88", 0 0, L_0x26b9a80; 1 drivers +v0x269aba0_0 .net *"_s93", 0 0, L_0x26b9be0; 1 drivers +v0x269ac80_0 .net *"_s99", 0 0, L_0x26b9ea0; 1 drivers +v0x269ad60_0 .net/s "accOut", 10 0, L_0x26a8160; alias, 1 drivers +v0x269ae40_0 .net "anyHasData", 0 0, L_0x26b8ce0; 1 drivers +v0x269af00_0 .net "anyReadAck", 0 0, L_0x26b99e0; 1 drivers +v0x269afc0_0 .net "anyWantData", 0 0, L_0x26b9240; 1 drivers +v0x269b080_0 .net "anyWriteAck", 0 0, L_0x26b9fd0; 1 drivers +v0x269b140_0 .net "clk", 0 0, v0x26a7f40_0; alias, 1 drivers +o0x2ace9a2fbef8 .functor BUFZ 15, C4; HiZ drive +v0x269b1e0_0 .net "down", 14 0, o0x2ace9a2fbef8; 0 drivers +v0x269b2c0_0 .net "downOut", 14 0, L_0x26bb5f0; 1 drivers +v0x269b3a0_0 .net "instruction", 17 0, L_0x26b8f70; 1 drivers +v0x269b480 .array "instructions", 15 0, 17 0; +v0x269b540_0 .var "last", 2 0; +o0x2ace9a2fbfb8 .functor BUFZ 15, C4; HiZ drive +v0x269b620_0 .net "left", 14 0, o0x2ace9a2fbfb8; 0 drivers +v0x269b700_0 .net "leftOut", 14 0, L_0x26bb330; 1 drivers +v0x269b7e0_0 .var "mode", 2 0; +v0x269b8c0 .array/s "outVals", 2 5, 10 0; +v0x269ba00_0 .var "phase", 2 0; +v0x269bae0_0 .net "portsHaveData", 5 2, L_0x26b8990; 1 drivers +v0x2699f10_0 .net "portsWantData", 5 2, L_0x26b8fe0; 1 drivers +v0x2699ff0_0 .net "readAckIn", 5 2, L_0x26b9760; 1 drivers +v0x269bf90_0 .var "readAckOut", 5 2; +v0x269c050_0 .var "readTarget", 2 0; +v0x269c130_0 .var/s "readValue", 10 0; +L_0x2ace9a32a018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x269c210 .array "regVals", 0 7; +v0x269c210_0 .net/s v0x269c210 0, 10 0, L_0x2ace9a32a018; 1 drivers +v0x269c210_1 .net/s v0x269c210 1, 10 0, L_0x26b8200; 1 drivers +v0x269c210_2 .net/s v0x269c210 2, 10 0, L_0x26b82c0; 1 drivers +v0x269c210_3 .net/s v0x269c210 3, 10 0, L_0x26b8360; 1 drivers +v0x269c210_4 .net/s v0x269c210 4, 10 0, L_0x26b8430; 1 drivers +v0x269c210_5 .net/s v0x269c210 5, 10 0, L_0x26b8530; 1 drivers +o0x2ace9a2fc378 .functor BUFZ 11, C4; HiZ drive +v0x269c210_6 .net/s v0x269c210 6, 10 0, o0x2ace9a2fc378; 0 drivers +o0x2ace9a2fc3a8 .functor BUFZ 11, C4; HiZ drive +v0x269c210_7 .net/s v0x269c210 7, 10 0, o0x2ace9a2fc3a8; 0 drivers +v0x269c420_0 .net "right", 14 0, L_0x26cb8a0; alias, 1 drivers +v0x269c510_0 .net "rightOut", 14 0, L_0x26bbbe0; alias, 1 drivers +o0x2ace9a2fc3d8 .functor BUFZ 15, C4; HiZ drive +v0x269c5e0_0 .net "up", 14 0, o0x2ace9a2fc3d8; 0 drivers +v0x269c6a0_0 .net "upOut", 14 0, L_0x26bb100; 1 drivers +v0x269c780_0 .var "weHaveData", 5 2; +v0x269c860_0 .var "weWantData", 5 2; +v0x269c940_0 .net "writeAckIn", 5 2, L_0x26b9cb0; 1 drivers +v0x269ca20_0 .var "writeAckOut", 5 2; +v0x269cb00_0 .var "writeTarget", 2 0; +v0x269cbe0_0 .var/s "writeValue", 10 0; +L_0x26b82c0 .part o0x2ace9a2fbfb8, 0, 11; +L_0x26b8360 .part L_0x26cb8a0, 0, 11; +L_0x26b8430 .part o0x2ace9a2fc3d8, 0, 11; +L_0x26b8530 .part o0x2ace9a2fbef8, 0, 11; +L_0x26b8660 .part o0x2ace9a2fbfb8, 11, 1; +L_0x26b8780 .part L_0x26cb8a0, 11, 1; +L_0x26b88f0 .part o0x2ace9a2fc3d8, 11, 1; +L_0x26b8990 .concat8 [ 1 1 1 1], L_0x26b8660, L_0x26b8780, L_0x26b88f0, L_0x26b8ba0; +L_0x26b8ba0 .part o0x2ace9a2fbef8, 11, 1; +L_0x26b8ce0 .reduce/or L_0x26b8990; +L_0x26b8e30 .part o0x2ace9a2fbfb8, 12, 1; +L_0x26b8ed0 .part L_0x26cb8a0, 12, 1; +L_0x269c340 .part o0x2ace9a2fc3d8, 12, 1; +L_0x26b8fe0 .concat8 [ 1 1 1 1], L_0x26b8e30, L_0x26b8ed0, L_0x269c340, L_0x26b9150; +L_0x26b9150 .part o0x2ace9a2fbef8, 12, 1; +L_0x26b9240 .reduce/or L_0x26b8fe0; +L_0x26b93c0 .part o0x2ace9a2fbfb8, 13, 1; +L_0x26b94f0 .part L_0x26cb8a0, 13, 1; +L_0x26b9630 .part o0x2ace9a2fc3d8, 13, 1; +L_0x26b9760 .concat8 [ 1 1 1 1], L_0x26b93c0, L_0x26b94f0, L_0x26b9630, L_0x26b9590; +L_0x26b9590 .part o0x2ace9a2fbef8, 13, 1; +L_0x26b99e0 .reduce/or L_0x26b9760; +L_0x26b9850 .part o0x2ace9a2fbfb8, 14, 1; +L_0x26b9b40 .part L_0x26cb8a0, 14, 1; +L_0x26b9a80 .part o0x2ace9a2fc3d8, 14, 1; +L_0x26b9cb0 .concat8 [ 1 1 1 1], L_0x26b9850, L_0x26b9b40, L_0x26b9a80, L_0x26b9be0; +L_0x26b9be0 .part o0x2ace9a2fbef8, 14, 1; +L_0x26b9fd0 .reduce/or L_0x26b9cb0; +L_0x26b9ea0 .part v0x269bf90_0, 0, 1; +L_0x26ba1b0 .part v0x269bf90_0, 1, 1; +L_0x26ba0c0 .part v0x269bf90_0, 2, 1; +L_0x26ba3a0 .part v0x269bf90_0, 3, 1; +L_0x26ba2a0 .part v0x269ca20_0, 0, 1; +L_0x26ba5e0 .part v0x269ca20_0, 1, 1; +L_0x26ba4d0 .part v0x269ca20_0, 2, 1; +L_0x26ba7a0 .part v0x269ca20_0, 3, 1; +L_0x26ba680 .part v0x269c860_0, 0, 1; +L_0x26baa00 .part v0x269c860_0, 1, 1; +L_0x26ba8d0 .part v0x269c860_0, 2, 1; +L_0x26babe0 .part v0x269c860_0, 3, 1; +L_0x26baaa0 .part v0x269c780_0, 0, 1; +L_0x26badd0 .part v0x269c780_0, 1, 1; +L_0x26bac80 .part v0x269c780_0, 2, 1; +L_0x26bad20 .part v0x269c780_0, 3, 1; +L_0x26bae70 .array/port v0x269b480, L_0x26bb1d0; +L_0x26bb1d0 .concat [ 4 2 0 0], v0x2698670_0, L_0x2ace9a32a060; +LS_0x26bb100_0_0 .concat8 [ 11 1 1 1], v0x269b8c0_2, L_0x26bac80, L_0x26ba8d0, L_0x26ba4d0; +LS_0x26bb100_0_4 .concat8 [ 1 0 0 0], L_0x26ba0c0; +L_0x26bb100 .concat8 [ 14 1 0 0], LS_0x26bb100_0_0, LS_0x26bb100_0_4; +LS_0x26bb5f0_0_0 .concat8 [ 11 1 1 1], v0x269b8c0_3, L_0x26bad20, L_0x26babe0, L_0x26ba7a0; +LS_0x26bb5f0_0_4 .concat8 [ 1 0 0 0], L_0x26ba3a0; +L_0x26bb5f0 .concat8 [ 14 1 0 0], LS_0x26bb5f0_0_0, LS_0x26bb5f0_0_4; +LS_0x26bb330_0_0 .concat8 [ 11 1 1 1], v0x269b8c0_0, L_0x26baaa0, L_0x26ba680, L_0x26ba2a0; +LS_0x26bb330_0_4 .concat8 [ 1 0 0 0], L_0x26b9ea0; +L_0x26bb330 .concat8 [ 14 1 0 0], LS_0x26bb330_0_0, LS_0x26bb330_0_4; +LS_0x26bbbe0_0_0 .concat8 [ 11 1 1 1], v0x269b8c0_1, L_0x26badd0, L_0x26baa00, L_0x26ba5e0; +LS_0x26bbbe0_0_4 .concat8 [ 1 0 0 0], L_0x26ba1b0; +L_0x26bbbe0 .concat8 [ 14 1 0 0], LS_0x26bbbe0_0_0, LS_0x26bbbe0_0_4; +L_0x26bb8d0 .part L_0x26b8f70, 14, 4; +L_0x26bbff0 .part L_0x26b8f70, 11, 3; +L_0x26bbe00 .part L_0x26b8f70, 8, 3; +L_0x26bc240 .part L_0x26b8f70, 10, 4; +L_0x26bc090 .part L_0x26b8f70, 0, 11; +S_0x269ce60 .scope module, "right" "tis100" 2 28, 3 49 0, S_0x25d8690; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x269d030 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x269d070 .param/str "memFile" 0 3 60, "regTest/right.dat"; +L_0x26bbf30 .functor BUFZ 11, v0x269d3e0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26bc130 .functor BUFZ 11, v0x269d3e0_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26bd080 .functor BUFZ 18, L_0x26beff0, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x269d3e0_0 .var/s "ACC", 10 0; +v0x269d4e0_0 .var/s "BAK", 10 0; +v0x269d5c0_0 .net "DST", 2 0, L_0x26c00f0; 1 drivers +v0x269d680_0 .net/s "IMM", 10 0, L_0x26c0190; 1 drivers +v0x269d760_0 .net "INST", 3 0, L_0x26bfa10; 1 drivers +v0x269d840_0 .net "LABEL", 3 0, L_0x26c0340; 1 drivers +v0x269d920_0 .var "PC", 3 0; +v0x269da00_0 .var "PCNEXT", 3 0; +v0x269dae0_0 .net "SRC", 2 0, L_0x26bff00; 1 drivers +v0x269dc50_0 .net *"_s103", 0 0, L_0x26be330; 1 drivers +v0x269dd30_0 .net *"_s107", 0 0, L_0x26be240; 1 drivers +v0x269de10_0 .net *"_s111", 0 0, L_0x26be520; 1 drivers +v0x269def0_0 .net *"_s115", 0 0, L_0x26be420; 1 drivers +v0x269dfd0_0 .net *"_s119", 0 0, L_0x26be760; 1 drivers +v0x269e0b0_0 .net *"_s123", 0 0, L_0x26be650; 1 drivers +v0x269e190_0 .net *"_s127", 0 0, L_0x26be920; 1 drivers +v0x269e270_0 .net *"_s131", 0 0, L_0x26be800; 1 drivers +v0x269e420_0 .net *"_s135", 0 0, L_0x26beb80; 1 drivers +v0x269e4c0_0 .net *"_s139", 0 0, L_0x26bea50; 1 drivers +v0x269e5a0_0 .net *"_s143", 0 0, L_0x26bed60; 1 drivers +v0x269e680_0 .net *"_s147", 0 0, L_0x26bec20; 1 drivers +v0x269e760_0 .net *"_s151", 0 0, L_0x26bef50; 1 drivers +v0x269e840_0 .net *"_s155", 0 0, L_0x26bee00; 1 drivers +v0x269e920_0 .net *"_s159", 0 0, L_0x26beea0; 1 drivers +v0x269ea00_0 .net *"_s160", 17 0, L_0x26beff0; 1 drivers +v0x269eae0_0 .net *"_s162", 5 0, L_0x26bf350; 1 drivers +L_0x2ace9a32a0f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x269ebc0_0 .net *"_s165", 1 0, L_0x2ace9a32a0f0; 1 drivers +v0x26a0af0_2 .array/port v0x26a0af0, 2; +v0x269eca0_0 .net *"_s173", 10 0, v0x26a0af0_2; 1 drivers +v0x26a0af0_3 .array/port v0x26a0af0, 3; +v0x269ed80_0 .net *"_s179", 10 0, v0x26a0af0_3; 1 drivers +v0x26a0af0_0 .array/port v0x26a0af0, 0; +v0x269ee60_0 .net *"_s185", 10 0, v0x26a0af0_0; 1 drivers +v0x26a0af0_1 .array/port v0x26a0af0, 1; +v0x269ef40_0 .net *"_s191", 10 0, v0x26a0af0_1; 1 drivers +v0x269f020_0 .net *"_s23", 0 0, L_0x26bc7b0; 1 drivers +v0x269f100_0 .net *"_s27", 0 0, L_0x26bc910; 1 drivers +v0x269e350_0 .net *"_s31", 0 0, L_0x26bc9e0; 1 drivers +v0x269f3d0_0 .net *"_s36", 0 0, L_0x26bccb0; 1 drivers +v0x269f4b0_0 .net *"_s42", 0 0, L_0x26bcf40; 1 drivers +v0x269f590_0 .net *"_s46", 0 0, L_0x26bcfe0; 1 drivers +v0x269f670_0 .net *"_s50", 0 0, L_0x26bd0f0; 1 drivers +v0x269f750_0 .net *"_s55", 0 0, L_0x26bd300; 1 drivers +v0x269f830_0 .net *"_s61", 0 0, L_0x26bd570; 1 drivers +v0x269f910_0 .net *"_s65", 0 0, L_0x26bd610; 1 drivers +v0x269f9f0_0 .net *"_s69", 0 0, L_0x26bd7e0; 1 drivers +v0x269fad0_0 .net *"_s74", 0 0, L_0x26bd740; 1 drivers +v0x269fbb0_0 .net *"_s80", 0 0, L_0x26bd9d0; 1 drivers +v0x269fc90_0 .net *"_s84", 0 0, L_0x26bdcc0; 1 drivers +v0x269fd70_0 .net *"_s88", 0 0, L_0x26bdc00; 1 drivers +v0x269fe50_0 .net *"_s93", 0 0, L_0x26bdd60; 1 drivers +v0x269ff30_0 .net *"_s99", 0 0, L_0x26be020; 1 drivers +v0x26a0010_0 .net/s "accOut", 10 0, L_0x26bbf30; alias, 1 drivers +v0x26a00f0_0 .net "anyHasData", 0 0, L_0x26bcdf0; 1 drivers +v0x26a01b0_0 .net "anyReadAck", 0 0, L_0x26bdb60; 1 drivers +v0x26a0270_0 .net "anyWantData", 0 0, L_0x26bd3f0; 1 drivers +v0x26a0330_0 .net "anyWriteAck", 0 0, L_0x26be150; 1 drivers +v0x26a03f0_0 .net "clk", 0 0, v0x26a7f40_0; alias, 1 drivers +o0x2ace9a2fd128 .functor BUFZ 15, C4; HiZ drive +v0x26a0490_0 .net "down", 14 0, o0x2ace9a2fd128; 0 drivers +v0x26a0570_0 .net "downOut", 14 0, L_0x26bf770; 1 drivers +v0x26a0650_0 .net "instruction", 17 0, L_0x26bd080; 1 drivers +v0x26a0730 .array "instructions", 15 0, 17 0; +v0x26a07f0_0 .var "last", 2 0; +v0x26a08d0_0 .net "left", 14 0, L_0x26cc270; alias, 1 drivers +v0x26a0990_0 .net "leftOut", 14 0, L_0x26bf4b0; alias, 1 drivers +v0x26a0a30_0 .var "mode", 2 0; +v0x26a0af0 .array/s "outVals", 2 5, 10 0; +v0x26a0c60_0 .var "phase", 2 0; +v0x26a0d40_0 .net "portsHaveData", 5 2, L_0x26bcad0; 1 drivers +v0x269f1a0_0 .net "portsWantData", 5 2, L_0x26bd190; 1 drivers +v0x269f280_0 .net "readAckIn", 5 2, L_0x26bd880; 1 drivers +v0x26a11f0_0 .var "readAckOut", 5 2; +v0x26a1290_0 .var "readTarget", 2 0; +v0x26a1330_0 .var/s "readValue", 10 0; +L_0x2ace9a32a0a8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x26a13d0 .array "regVals", 0 7; +v0x26a13d0_0 .net/s v0x26a13d0 0, 10 0, L_0x2ace9a32a0a8; 1 drivers +v0x26a13d0_1 .net/s v0x26a13d0 1, 10 0, L_0x26bc130; 1 drivers +v0x26a13d0_2 .net/s v0x26a13d0 2, 10 0, L_0x26bc4a0; 1 drivers +v0x26a13d0_3 .net/s v0x26a13d0 3, 10 0, L_0x26bc540; 1 drivers +v0x26a13d0_4 .net/s v0x26a13d0 4, 10 0, L_0x26bc5e0; 1 drivers +v0x26a13d0_5 .net/s v0x26a13d0 5, 10 0, L_0x26bc680; 1 drivers +o0x2ace9a2fd548 .functor BUFZ 11, C4; HiZ drive +v0x26a13d0_6 .net/s v0x26a13d0 6, 10 0, o0x2ace9a2fd548; 0 drivers +o0x2ace9a2fd578 .functor BUFZ 11, C4; HiZ drive +v0x26a13d0_7 .net/s v0x26a13d0 7, 10 0, o0x2ace9a2fd578; 0 drivers +o0x2ace9a2fd5a8 .functor BUFZ 15, C4; HiZ drive +v0x26a15e0_0 .net "right", 14 0, o0x2ace9a2fd5a8; 0 drivers +v0x26a16c0_0 .net "rightOut", 14 0, L_0x26bfce0; 1 drivers +o0x2ace9a2fd608 .functor BUFZ 15, C4; HiZ drive +v0x26a17a0_0 .net "up", 14 0, o0x2ace9a2fd608; 0 drivers +v0x26a1880_0 .net "upOut", 14 0, L_0x26bf260; 1 drivers +v0x26a1960_0 .var "weHaveData", 5 2; +v0x26a1a40_0 .var "weWantData", 5 2; +v0x26a1b20_0 .net "writeAckIn", 5 2, L_0x26bde30; 1 drivers +v0x26a1c00_0 .var "writeAckOut", 5 2; +v0x26a1ce0_0 .var "writeTarget", 2 0; +v0x26a1dc0_0 .var/s "writeValue", 10 0; +L_0x26bc4a0 .part L_0x26cc270, 0, 11; +L_0x26bc540 .part o0x2ace9a2fd5a8, 0, 11; +L_0x26bc5e0 .part o0x2ace9a2fd608, 0, 11; +L_0x26bc680 .part o0x2ace9a2fd128, 0, 11; +L_0x26bc7b0 .part L_0x26cc270, 11, 1; +L_0x26bc910 .part o0x2ace9a2fd5a8, 11, 1; +L_0x26bc9e0 .part o0x2ace9a2fd608, 11, 1; +L_0x26bcad0 .concat8 [ 1 1 1 1], L_0x26bc7b0, L_0x26bc910, L_0x26bc9e0, L_0x26bccb0; +L_0x26bccb0 .part o0x2ace9a2fd128, 11, 1; +L_0x26bcdf0 .reduce/or L_0x26bcad0; +L_0x26bcf40 .part L_0x26cc270, 12, 1; +L_0x26bcfe0 .part o0x2ace9a2fd5a8, 12, 1; +L_0x26bd0f0 .part o0x2ace9a2fd608, 12, 1; +L_0x26bd190 .concat8 [ 1 1 1 1], L_0x26bcf40, L_0x26bcfe0, L_0x26bd0f0, L_0x26bd300; +L_0x26bd300 .part o0x2ace9a2fd128, 12, 1; +L_0x26bd3f0 .reduce/or L_0x26bd190; +L_0x26bd570 .part L_0x26cc270, 13, 1; +L_0x26bd610 .part o0x2ace9a2fd5a8, 13, 1; +L_0x26bd7e0 .part o0x2ace9a2fd608, 13, 1; +L_0x26bd880 .concat8 [ 1 1 1 1], L_0x26bd570, L_0x26bd610, L_0x26bd7e0, L_0x26bd740; +L_0x26bd740 .part o0x2ace9a2fd128, 13, 1; +L_0x26bdb60 .reduce/or L_0x26bd880; +L_0x26bd9d0 .part L_0x26cc270, 14, 1; +L_0x26bdcc0 .part o0x2ace9a2fd5a8, 14, 1; +L_0x26bdc00 .part o0x2ace9a2fd608, 14, 1; +L_0x26bde30 .concat8 [ 1 1 1 1], L_0x26bd9d0, L_0x26bdcc0, L_0x26bdc00, L_0x26bdd60; +L_0x26bdd60 .part o0x2ace9a2fd128, 14, 1; +L_0x26be150 .reduce/or L_0x26bde30; +L_0x26be020 .part v0x26a11f0_0, 0, 1; +L_0x26be330 .part v0x26a11f0_0, 1, 1; +L_0x26be240 .part v0x26a11f0_0, 2, 1; +L_0x26be520 .part v0x26a11f0_0, 3, 1; +L_0x26be420 .part v0x26a1c00_0, 0, 1; +L_0x26be760 .part v0x26a1c00_0, 1, 1; +L_0x26be650 .part v0x26a1c00_0, 2, 1; +L_0x26be920 .part v0x26a1c00_0, 3, 1; +L_0x26be800 .part v0x26a1a40_0, 0, 1; +L_0x26beb80 .part v0x26a1a40_0, 1, 1; +L_0x26bea50 .part v0x26a1a40_0, 2, 1; +L_0x26bed60 .part v0x26a1a40_0, 3, 1; +L_0x26bec20 .part v0x26a1960_0, 0, 1; +L_0x26bef50 .part v0x26a1960_0, 1, 1; +L_0x26bee00 .part v0x26a1960_0, 2, 1; +L_0x26beea0 .part v0x26a1960_0, 3, 1; +L_0x26beff0 .array/port v0x26a0730, L_0x26bf350; +L_0x26bf350 .concat [ 4 2 0 0], v0x269d920_0, L_0x2ace9a32a0f0; +LS_0x26bf260_0_0 .concat8 [ 11 1 1 1], v0x26a0af0_2, L_0x26bee00, L_0x26bea50, L_0x26be650; +LS_0x26bf260_0_4 .concat8 [ 1 0 0 0], L_0x26be240; +L_0x26bf260 .concat8 [ 14 1 0 0], LS_0x26bf260_0_0, LS_0x26bf260_0_4; +LS_0x26bf770_0_0 .concat8 [ 11 1 1 1], v0x26a0af0_3, L_0x26beea0, L_0x26bed60, L_0x26be920; +LS_0x26bf770_0_4 .concat8 [ 1 0 0 0], L_0x26be520; +L_0x26bf770 .concat8 [ 14 1 0 0], LS_0x26bf770_0_0, LS_0x26bf770_0_4; +LS_0x26bf4b0_0_0 .concat8 [ 11 1 1 1], v0x26a0af0_0, L_0x26bec20, L_0x26be800, L_0x26be420; +LS_0x26bf4b0_0_4 .concat8 [ 1 0 0 0], L_0x26be020; +L_0x26bf4b0 .concat8 [ 14 1 0 0], LS_0x26bf4b0_0_0, LS_0x26bf4b0_0_4; +LS_0x26bfce0_0_0 .concat8 [ 11 1 1 1], v0x26a0af0_1, L_0x26bef50, L_0x26beb80, L_0x26be760; +LS_0x26bfce0_0_4 .concat8 [ 1 0 0 0], L_0x26be330; +L_0x26bfce0 .concat8 [ 14 1 0 0], LS_0x26bfce0_0_0, LS_0x26bfce0_0_4; +L_0x26bfa10 .part L_0x26bd080, 14, 4; +L_0x26c00f0 .part L_0x26bd080, 11, 3; +L_0x26bff00 .part L_0x26bd080, 8, 3; +L_0x26c0340 .part L_0x26bd080, 10, 4; +L_0x26c0190 .part L_0x26bd080, 0, 11; +S_0x26a2040 .scope module, "up" "tis100" 2 29, 3 49 0, S_0x25d8690; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x26a2260 .param/l "debug" 0 3 61, +C4<00000000000000000000000000000000>; +P_0x26a22a0 .param/str "memFile" 0 3 60, "regTest/up.dat"; +L_0x26c0030 .functor BUFZ 11, v0x26a2560_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26c0280 .functor BUFZ 11, v0x26a2560_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x26c10c0 .functor BUFZ 18, L_0x26c3060, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x26a2560_0 .var/s "ACC", 10 0; +v0x26a2660_0 .var/s "BAK", 10 0; +v0x26a2740_0 .net "DST", 2 0, L_0x26c41a0; 1 drivers +v0x26a2800_0 .net/s "IMM", 10 0, L_0x26c4240; 1 drivers +v0x26a28e0_0 .net "INST", 3 0, L_0x26c3a80; 1 drivers +v0x26a2a10_0 .net "LABEL", 3 0, L_0x26c43f0; 1 drivers +v0x26a2af0_0 .var "PC", 3 0; +v0x26a2bd0_0 .var "PCNEXT", 3 0; +v0x26a2cb0_0 .net "SRC", 2 0, L_0x26c3fb0; 1 drivers +v0x26a2e20_0 .net *"_s103", 0 0, L_0x26c23a0; 1 drivers +v0x26a2f00_0 .net *"_s107", 0 0, L_0x26c22b0; 1 drivers +v0x26a2fe0_0 .net *"_s111", 0 0, L_0x26c2590; 1 drivers +v0x26a30c0_0 .net *"_s115", 0 0, L_0x26c2490; 1 drivers +v0x26a31a0_0 .net *"_s119", 0 0, L_0x26c27d0; 1 drivers +v0x26a3280_0 .net *"_s123", 0 0, L_0x26c26c0; 1 drivers +v0x26a3360_0 .net *"_s127", 0 0, L_0x26c2990; 1 drivers +v0x26a3440_0 .net *"_s131", 0 0, L_0x26c2870; 1 drivers +v0x26a35f0_0 .net *"_s135", 0 0, L_0x26c2bf0; 1 drivers +v0x26a3690_0 .net *"_s139", 0 0, L_0x26c2ac0; 1 drivers +v0x26a3770_0 .net *"_s143", 0 0, L_0x26c2dd0; 1 drivers +v0x26a3850_0 .net *"_s147", 0 0, L_0x26c2c90; 1 drivers +v0x26a3930_0 .net *"_s151", 0 0, L_0x26c2fc0; 1 drivers +v0x26a3a10_0 .net *"_s155", 0 0, L_0x26c2e70; 1 drivers +v0x26a3af0_0 .net *"_s159", 0 0, L_0x26c2f10; 1 drivers +v0x26a3bd0_0 .net *"_s160", 17 0, L_0x26c3060; 1 drivers +v0x26a3cb0_0 .net *"_s162", 5 0, L_0x26c33c0; 1 drivers +L_0x2ace9a32a180 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x26a3d90_0 .net *"_s165", 1 0, L_0x2ace9a32a180; 1 drivers +v0x26a5d50_2 .array/port v0x26a5d50, 2; +v0x26a3e70_0 .net *"_s173", 10 0, v0x26a5d50_2; 1 drivers +v0x26a5d50_3 .array/port v0x26a5d50, 3; +v0x26a3f50_0 .net *"_s179", 10 0, v0x26a5d50_3; 1 drivers +v0x26a5d50_0 .array/port v0x26a5d50, 0; +v0x26a4030_0 .net *"_s185", 10 0, v0x26a5d50_0; 1 drivers +v0x26a5d50_1 .array/port v0x26a5d50, 1; +v0x26a4110_0 .net *"_s191", 10 0, v0x26a5d50_1; 1 drivers +v0x26a41f0_0 .net *"_s23", 0 0, L_0x26c0880; 1 drivers +v0x26a42d0_0 .net *"_s27", 0 0, L_0x26c09a0; 1 drivers +v0x26a3520_0 .net *"_s31", 0 0, L_0x26c0a90; 1 drivers +v0x26a45a0_0 .net *"_s36", 0 0, L_0x26c0d60; 1 drivers +v0x26a4680_0 .net *"_s42", 0 0, L_0x26c0f80; 1 drivers +v0x26a4760_0 .net *"_s46", 0 0, L_0x26c1020; 1 drivers +v0x26a4840_0 .net *"_s50", 0 0, L_0x26c1130; 1 drivers +v0x26a4920_0 .net *"_s55", 0 0, L_0x26c1370; 1 drivers +v0x26a4a00_0 .net *"_s61", 0 0, L_0x26c15e0; 1 drivers +v0x26a4ae0_0 .net *"_s65", 0 0, L_0x26c1710; 1 drivers +v0x26a4bc0_0 .net *"_s69", 0 0, L_0x26c18e0; 1 drivers +v0x26a4ca0_0 .net *"_s74", 0 0, L_0x26c1840; 1 drivers +v0x26a4d80_0 .net *"_s80", 0 0, L_0x26c1a80; 1 drivers +v0x26a4e60_0 .net *"_s84", 0 0, L_0x26c1d30; 1 drivers +v0x26a4f40_0 .net *"_s88", 0 0, L_0x26c1c70; 1 drivers +v0x26a5020_0 .net *"_s93", 0 0, L_0x26c1dd0; 1 drivers +v0x26a5100_0 .net *"_s99", 0 0, L_0x26c2090; 1 drivers +v0x26a51e0_0 .net/s "accOut", 10 0, L_0x26c0030; alias, 1 drivers +v0x26a52c0_0 .net "anyHasData", 0 0, L_0x26c0ee0; 1 drivers +v0x26a5380_0 .net "anyReadAck", 0 0, L_0x26c1b80; 1 drivers +v0x26a5440_0 .net "anyWantData", 0 0, L_0x26c1460; 1 drivers +v0x26a5500_0 .net "anyWriteAck", 0 0, L_0x26c21c0; 1 drivers +v0x26a55c0_0 .net "clk", 0 0, v0x26a7f40_0; alias, 1 drivers +v0x26a56f0_0 .net "down", 14 0, L_0x26cb5d0; alias, 1 drivers +v0x26a57b0_0 .net "downOut", 14 0, L_0x26c37e0; alias, 1 drivers +v0x26a5850_0 .net "instruction", 17 0, L_0x26c10c0; 1 drivers +v0x26a5910 .array "instructions", 15 0, 17 0; +v0x26a59d0_0 .var "last", 2 0; +o0x2ace9a2fe3b8 .functor BUFZ 15, C4; HiZ drive +v0x26a5ab0_0 .net "left", 14 0, o0x2ace9a2fe3b8; 0 drivers +v0x26a5b90_0 .net "leftOut", 14 0, L_0x26c3520; 1 drivers +v0x26a5c70_0 .var "mode", 2 0; +v0x26a5d50 .array/s "outVals", 2 5, 10 0; +v0x26a5ec0_0 .var "phase", 2 0; +v0x26a5fa0_0 .net "portsHaveData", 5 2, L_0x26c0b80; 1 drivers +v0x26a4370_0 .net "portsWantData", 5 2, L_0x26c11d0; 1 drivers +v0x26a4450_0 .net "readAckIn", 5 2, L_0x26c1980; 1 drivers +v0x26a6450_0 .var "readAckOut", 5 2; +v0x26a64f0_0 .var "readTarget", 2 0; +v0x26a6590_0 .var/s "readValue", 10 0; +L_0x2ace9a32a138 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x26a6630 .array "regVals", 0 7; +v0x26a6630_0 .net/s v0x26a6630 0, 10 0, L_0x2ace9a32a138; 1 drivers +v0x26a6630_1 .net/s v0x26a6630 1, 10 0, L_0x26c0280; 1 drivers +v0x26a6630_2 .net/s v0x26a6630 2, 10 0, L_0x26c05a0; 1 drivers +v0x26a6630_3 .net/s v0x26a6630 3, 10 0, L_0x26c0640; 1 drivers +v0x26a6630_4 .net/s v0x26a6630 4, 10 0, L_0x26c06e0; 1 drivers +v0x26a6630_5 .net/s v0x26a6630 5, 10 0, L_0x26c0780; 1 drivers +o0x2ace9a2fe778 .functor BUFZ 11, C4; HiZ drive +v0x26a6630_6 .net/s v0x26a6630 6, 10 0, o0x2ace9a2fe778; 0 drivers +o0x2ace9a2fe7a8 .functor BUFZ 11, C4; HiZ drive +v0x26a6630_7 .net/s v0x26a6630 7, 10 0, o0x2ace9a2fe7a8; 0 drivers +o0x2ace9a2fe7d8 .functor BUFZ 15, C4; HiZ drive +v0x26a6840_0 .net "right", 14 0, o0x2ace9a2fe7d8; 0 drivers +v0x26a6920_0 .net "rightOut", 14 0, L_0x26c3d90; 1 drivers +o0x2ace9a2fe838 .functor BUFZ 15, C4; HiZ drive +v0x26a6a00_0 .net "up", 14 0, o0x2ace9a2fe838; 0 drivers +v0x26a6ae0_0 .net "upOut", 14 0, L_0x26c32d0; 1 drivers +v0x26a6bc0_0 .var "weHaveData", 5 2; +v0x26a6ca0_0 .var "weWantData", 5 2; +v0x26a6d80_0 .net "writeAckIn", 5 2, L_0x26c1ea0; 1 drivers +v0x26a6e60_0 .var "writeAckOut", 5 2; +v0x26a6f40_0 .var "writeTarget", 2 0; +v0x26a7020_0 .var/s "writeValue", 10 0; +L_0x26c05a0 .part o0x2ace9a2fe3b8, 0, 11; +L_0x26c0640 .part o0x2ace9a2fe7d8, 0, 11; +L_0x26c06e0 .part o0x2ace9a2fe838, 0, 11; +L_0x26c0780 .part L_0x26cb5d0, 0, 11; +L_0x26c0880 .part o0x2ace9a2fe3b8, 11, 1; +L_0x26c09a0 .part o0x2ace9a2fe7d8, 11, 1; +L_0x26c0a90 .part o0x2ace9a2fe838, 11, 1; +L_0x26c0b80 .concat8 [ 1 1 1 1], L_0x26c0880, L_0x26c09a0, L_0x26c0a90, L_0x26c0d60; +L_0x26c0d60 .part L_0x26cb5d0, 11, 1; +L_0x26c0ee0 .reduce/or L_0x26c0b80; +L_0x26c0f80 .part o0x2ace9a2fe3b8, 12, 1; +L_0x26c1020 .part o0x2ace9a2fe7d8, 12, 1; +L_0x26c1130 .part o0x2ace9a2fe838, 12, 1; +L_0x26c11d0 .concat8 [ 1 1 1 1], L_0x26c0f80, L_0x26c1020, L_0x26c1130, L_0x26c1370; +L_0x26c1370 .part L_0x26cb5d0, 12, 1; +L_0x26c1460 .reduce/or L_0x26c11d0; +L_0x26c15e0 .part o0x2ace9a2fe3b8, 13, 1; +L_0x26c1710 .part o0x2ace9a2fe7d8, 13, 1; +L_0x26c18e0 .part o0x2ace9a2fe838, 13, 1; +L_0x26c1980 .concat8 [ 1 1 1 1], L_0x26c15e0, L_0x26c1710, L_0x26c18e0, L_0x26c1840; +L_0x26c1840 .part L_0x26cb5d0, 13, 1; +L_0x26c1b80 .reduce/or L_0x26c1980; +L_0x26c1a80 .part o0x2ace9a2fe3b8, 14, 1; +L_0x26c1d30 .part o0x2ace9a2fe7d8, 14, 1; +L_0x26c1c70 .part o0x2ace9a2fe838, 14, 1; +L_0x26c1ea0 .concat8 [ 1 1 1 1], L_0x26c1a80, L_0x26c1d30, L_0x26c1c70, L_0x26c1dd0; +L_0x26c1dd0 .part L_0x26cb5d0, 14, 1; +L_0x26c21c0 .reduce/or L_0x26c1ea0; +L_0x26c2090 .part v0x26a6450_0, 0, 1; +L_0x26c23a0 .part v0x26a6450_0, 1, 1; +L_0x26c22b0 .part v0x26a6450_0, 2, 1; +L_0x26c2590 .part v0x26a6450_0, 3, 1; +L_0x26c2490 .part v0x26a6e60_0, 0, 1; +L_0x26c27d0 .part v0x26a6e60_0, 1, 1; +L_0x26c26c0 .part v0x26a6e60_0, 2, 1; +L_0x26c2990 .part v0x26a6e60_0, 3, 1; +L_0x26c2870 .part v0x26a6ca0_0, 0, 1; +L_0x26c2bf0 .part v0x26a6ca0_0, 1, 1; +L_0x26c2ac0 .part v0x26a6ca0_0, 2, 1; +L_0x26c2dd0 .part v0x26a6ca0_0, 3, 1; +L_0x26c2c90 .part v0x26a6bc0_0, 0, 1; +L_0x26c2fc0 .part v0x26a6bc0_0, 1, 1; +L_0x26c2e70 .part v0x26a6bc0_0, 2, 1; +L_0x26c2f10 .part v0x26a6bc0_0, 3, 1; +L_0x26c3060 .array/port v0x26a5910, L_0x26c33c0; +L_0x26c33c0 .concat [ 4 2 0 0], v0x26a2af0_0, L_0x2ace9a32a180; +LS_0x26c32d0_0_0 .concat8 [ 11 1 1 1], v0x26a5d50_2, L_0x26c2e70, L_0x26c2ac0, L_0x26c26c0; +LS_0x26c32d0_0_4 .concat8 [ 1 0 0 0], L_0x26c22b0; +L_0x26c32d0 .concat8 [ 14 1 0 0], LS_0x26c32d0_0_0, LS_0x26c32d0_0_4; +LS_0x26c37e0_0_0 .concat8 [ 11 1 1 1], v0x26a5d50_3, L_0x26c2f10, L_0x26c2dd0, L_0x26c2990; +LS_0x26c37e0_0_4 .concat8 [ 1 0 0 0], L_0x26c2590; +L_0x26c37e0 .concat8 [ 14 1 0 0], LS_0x26c37e0_0_0, LS_0x26c37e0_0_4; +LS_0x26c3520_0_0 .concat8 [ 11 1 1 1], v0x26a5d50_0, L_0x26c2c90, L_0x26c2870, L_0x26c2490; +LS_0x26c3520_0_4 .concat8 [ 1 0 0 0], L_0x26c2090; +L_0x26c3520 .concat8 [ 14 1 0 0], LS_0x26c3520_0_0, LS_0x26c3520_0_4; +LS_0x26c3d90_0_0 .concat8 [ 11 1 1 1], v0x26a5d50_1, L_0x26c2fc0, L_0x26c2bf0, L_0x26c27d0; +LS_0x26c3d90_0_4 .concat8 [ 1 0 0 0], L_0x26c23a0; +L_0x26c3d90 .concat8 [ 14 1 0 0], LS_0x26c3d90_0_0, LS_0x26c3d90_0_4; +L_0x26c3a80 .part L_0x26c10c0, 14, 4; +L_0x26c41a0 .part L_0x26c10c0, 11, 3; +L_0x26c3fb0 .part L_0x26c10c0, 8, 3; +L_0x26c43f0 .part L_0x26c10c0, 10, 4; +L_0x26c4240 .part L_0x26c10c0, 0, 11; + .scope S_0x2697c50; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x269b7e0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x269ba00_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x269b540_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x26980f0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x26981b0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2698670_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269bf90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269c860_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269ca20_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269c780_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x269b8c0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x269b8c0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x269b8c0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x269b8c0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x2697e90, v0x269b480 {0 0 0}; + %end; + .thread T_0; + .scope S_0x2697c50; +T_1 ; + %wait E_0x260bcc0; + %load/vec4 v0x269b7e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %jmp T_1.3; +T_1.0 ; + %load/vec4 v0x269ba00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.6, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0x2698460_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_1.8, 5; + %load/vec4 v0x2698830_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_1.10, 5; + %load/vec4 v0x2698830_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0x2698830_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_1.12, 5; + %load/vec4 v0x269bae0_0; + %load/vec4 v0x2698830_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0x2698830_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2698830_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %load/vec4 v0x2698830_0; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.15; +T_1.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %load/vec4 v0x2698830_0; + %assign/vec4 v0x269c050_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2698830_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269c860_0, 4, 5; + %load/vec4 v0x2698830_0; + %assign/vec4 v0x269b540_0, 0; +T_1.15 ; + %jmp T_1.13; +T_1.12 ; + %load/vec4 v0x2698830_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.16, 4; + %load/vec4 v0x269b540_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_1.18, 4; + %load/vec4 v0x269b540_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %jmp T_1.19; +T_1.18 ; + %load/vec4 v0x269bae0_0; + %load/vec4 v0x269b540_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.20, 8; + %load/vec4 v0x269b540_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269b540_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %jmp T_1.21; +T_1.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %load/vec4 v0x269b540_0; + %assign/vec4 v0x269c050_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269b540_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269c860_0, 4, 5; +T_1.21 ; +T_1.19 ; + %jmp T_1.17; +T_1.16 ; + %load/vec4 v0x2698830_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.22, 4; + %load/vec4 v0x269ae40_0; + %flag_set/vec4 8; + %jmp/0xz T_1.24, 8; + %load/vec4 v0x269bae0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.27; +T_1.26 ; + %load/vec4 v0x269bae0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.29; +T_1.28 ; + %load/vec4 v0x269bae0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.31; +T_1.30 ; + %load/vec4 v0x269bae0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x269b540_0, 0; +T_1.32 ; +T_1.31 ; +T_1.29 ; +T_1.27 ; + %jmp T_1.25; +T_1.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %load/vec4 v0x2698830_0; + %assign/vec4 v0x269c050_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c860_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c860_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c860_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c860_0, 4, 5; +T_1.25 ; +T_1.22 ; +T_1.17 ; +T_1.13 ; +T_1.11 ; +T_1.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0x2698460_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_1.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_1.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_1.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_1.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_1.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_1.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_1.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_1.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_1.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_1.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_1.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_1.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_1.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_1.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_1.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_1.49, 6; + %jmp T_1.50; +T_1.34 ; + %load/vec4 v0x26980f0_0; + %load/vec4 v0x269c130_0; + %add; + %assign/vec4 v0x26980f0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.35 ; + %load/vec4 v0x26980f0_0; + %load/vec4 v0x269c130_0; + %sub; + %assign/vec4 v0x26980f0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.36 ; + %load/vec4 v0x2698670_0; + %pad/u 11; + %load/vec4 v0x269c130_0; + %add; + %pad/u 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.37 ; + %load/vec4 v0x269c130_0; + %assign/vec4 v0x269cbe0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.38 ; + %load/vec4 v0x2698380_0; + %assign/vec4 v0x269cbe0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.39 ; + %load/vec4 v0x26980f0_0; + %load/vec4 v0x2698380_0; + %add; + %assign/vec4 v0x26980f0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.40 ; + %load/vec4 v0x26980f0_0; + %load/vec4 v0x2698380_0; + %sub; + %assign/vec4 v0x26980f0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.41 ; + %load/vec4 v0x2698670_0; + %pad/u 11; + %load/vec4 v0x2698380_0; + %add; + %pad/u 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.42 ; + %load/vec4 v0x26981b0_0; + %assign/vec4 v0x26980f0_0, 0; + %load/vec4 v0x26980f0_0; + %assign/vec4 v0x26981b0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.43 ; + %load/vec4 v0x26980f0_0; + %assign/vec4 v0x26981b0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.44 ; + %load/vec4 v0x26980f0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x26980f0_0, 0; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.45 ; + %load/vec4 v0x2698590_0; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.50; +T_1.46 ; + %load/vec4 v0x26980f0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_1.51, 4; + %load/vec4 v0x2698590_0; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.52; +T_1.51 ; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; +T_1.52 ; + %jmp T_1.50; +T_1.47 ; + %load/vec4 v0x26980f0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.53, 4; + %load/vec4 v0x2698590_0; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.54; +T_1.53 ; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; +T_1.54 ; + %jmp T_1.50; +T_1.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x26980f0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_1.55, 5; + %load/vec4 v0x2698590_0; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.56; +T_1.55 ; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; +T_1.56 ; + %jmp T_1.50; +T_1.49 ; + %load/vec4 v0x26980f0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_1.57, 5; + %load/vec4 v0x2698590_0; + %assign/vec4 v0x2698750_0, 0; + %jmp T_1.58; +T_1.57 ; + %load/vec4 v0x2698670_0; + %addi 1, 0, 4; + %assign/vec4 v0x2698750_0, 0; +T_1.58 ; + %jmp T_1.50; +T_1.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x2698460_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x2698460_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_1.59, 4; + %load/vec4 v0x2698290_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x2698290_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x269b540_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_1.61, 9; + %load/vec4 v0x2698290_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_1.63, 4; + %load/vec4 v0x269cbe0_0; + %assign/vec4 v0x26980f0_0, 0; +T_1.63 ; + %jmp T_1.62; +T_1.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %load/vec4 v0x2698290_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.65, 4; + %load/vec4 v0x269b540_0; + %assign/vec4 v0x269cb00_0, 0; + %load/vec4 v0x269cbe0_0; + %load/vec4 v0x269b540_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269b540_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %jmp T_1.66; +T_1.65 ; + %load/vec4 v0x2698290_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.67, 4; + %load/vec4 v0x2698290_0; + %assign/vec4 v0x269cb00_0, 0; + %load/vec4 v0x269cbe0_0; + %load/vec4 v0x2698290_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2698290_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x2698290_0; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.68; +T_1.67 ; + %load/vec4 v0x269afc0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.69, 8; + %load/vec4 v0x2699f10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.72; +T_1.71 ; + %load/vec4 v0x2699f10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.74; +T_1.73 ; + %load/vec4 v0x2699f10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.76; +T_1.75 ; + %load/vec4 v0x2699f10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x269b540_0, 0; +T_1.77 ; +T_1.76 ; +T_1.74 ; +T_1.72 ; + %jmp T_1.70; +T_1.69 ; + %load/vec4 v0x2698290_0; + %assign/vec4 v0x269cb00_0, 0; +T_1.70 ; +T_1.68 ; +T_1.66 ; +T_1.62 ; +T_1.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.1 ; + %load/vec4 v0x269ba00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.81, 6; + %jmp T_1.82; +T_1.79 ; + %load/vec4 v0x269c050_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.83, 4; + %load/vec4 v0x269ae40_0; + %flag_set/vec4 8; + %jmp/0xz T_1.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269c860_0, 0, 4; + %load/vec4 v0x269bae0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.88; +T_1.87 ; + %load/vec4 v0x269bae0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.90; +T_1.89 ; + %load/vec4 v0x269bae0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.92; +T_1.91 ; + %load/vec4 v0x269bae0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x269b540_0, 0; +T_1.93 ; +T_1.92 ; +T_1.90 ; +T_1.88 ; +T_1.85 ; + %jmp T_1.84; +T_1.83 ; + %load/vec4 v0x269bae0_0; + %load/vec4 v0x269c050_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %load/vec4 v0x269c050_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x269c210, 4; + %assign/vec4 v0x269c130_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269c050_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269bf90_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269c050_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x269c860_0, 4, 5; + %load/vec4 v0x269c050_0; + %assign/vec4 v0x269b540_0, 0; +T_1.95 ; +T_1.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.82; +T_1.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.82; +T_1.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.82; +T_1.82 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x269ba00_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.99, 6; + %jmp T_1.100; +T_1.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.100; +T_1.98 ; + %load/vec4 v0x269cb00_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.101, 4; + %load/vec4 v0x269afc0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.103, 8; + %load/vec4 v0x2699f10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.106; +T_1.105 ; + %load/vec4 v0x2699f10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.108; +T_1.107 ; + %load/vec4 v0x2699f10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x269b540_0, 0; + %jmp T_1.110; +T_1.109 ; + %load/vec4 v0x2699f10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x269cb00_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x269c780_0, 4, 5; + %load/vec4 v0x269cbe0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x269b8c0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x269b540_0, 0; +T_1.111 ; +T_1.110 ; +T_1.108 ; +T_1.106 ; +T_1.103 ; +T_1.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.100; +T_1.99 ; + %load/vec4 v0x269cb00_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.113, 4; + %load/vec4 v0x269c940_0; + %load/vec4 v0x269cb00_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x269cb00_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x269c780_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x269b7e0_0, 0; + %load/vec4 v0x269cb00_0; + %assign/vec4 v0x269b540_0, 0; +T_1.115 ; +T_1.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x269ba00_0, 0; + %jmp T_1.100; +T_1.100 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.3 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1; + .scope S_0x2697c50; +T_2 ; + %wait E_0x25e9520; + %load/vec4 v0x269ba00_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x269b7e0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x2698750_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %load/vec4 v0x2698750_0; + %assign/vec4 v0x2698670_0, 0; +T_2.0 ; + %load/vec4 v0x269ba00_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_2.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269bf90_0, 0, 4; +T_2.2 ; + %jmp T_2; + .thread T_2; + .scope S_0x269ce60; +T_3 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26a0a30_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26a0c60_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26a07f0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x269d3e0_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x269d4e0_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x269d920_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a11f0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a1a40_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a1c00_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a1960_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a0af0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a0af0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a0af0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a0af0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x269d070, v0x26a0730 {0 0 0}; + %end; + .thread T_3; + .scope S_0x269ce60; +T_4 ; + %wait E_0x260bcc0; + %load/vec4 v0x26a0a30_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0x26a0c60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.6, 6; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0x269d760_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_4.8, 5; + %load/vec4 v0x269dae0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_4.10, 5; + %load/vec4 v0x269dae0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %jmp T_4.11; +T_4.10 ; + %load/vec4 v0x269dae0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_4.12, 5; + %load/vec4 v0x26a0d40_0; + %load/vec4 v0x269dae0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.14, 8; + %load/vec4 v0x269dae0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269dae0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %load/vec4 v0x269dae0_0; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.15; +T_4.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %load/vec4 v0x269dae0_0; + %assign/vec4 v0x26a1290_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269dae0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; + %load/vec4 v0x269dae0_0; + %assign/vec4 v0x26a07f0_0, 0; +T_4.15 ; + %jmp T_4.13; +T_4.12 ; + %load/vec4 v0x269dae0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.16, 4; + %load/vec4 v0x26a07f0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_4.18, 4; + %load/vec4 v0x26a07f0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %jmp T_4.19; +T_4.18 ; + %load/vec4 v0x26a0d40_0; + %load/vec4 v0x26a07f0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.20, 8; + %load/vec4 v0x26a07f0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a07f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %jmp T_4.21; +T_4.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %load/vec4 v0x26a07f0_0; + %assign/vec4 v0x26a1290_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a07f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; +T_4.21 ; +T_4.19 ; + %jmp T_4.17; +T_4.16 ; + %load/vec4 v0x269dae0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.22, 4; + %load/vec4 v0x26a00f0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.24, 8; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.27; +T_4.26 ; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.29; +T_4.28 ; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.31; +T_4.30 ; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; +T_4.32 ; +T_4.31 ; +T_4.29 ; +T_4.27 ; + %jmp T_4.25; +T_4.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %load/vec4 v0x269dae0_0; + %assign/vec4 v0x26a1290_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; +T_4.25 ; +T_4.22 ; +T_4.17 ; +T_4.13 ; +T_4.11 ; +T_4.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0x269d760_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_4.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_4.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_4.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_4.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_4.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_4.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_4.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_4.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_4.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_4.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_4.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_4.49, 6; + %jmp T_4.50; +T_4.34 ; + %load/vec4 v0x269d3e0_0; + %load/vec4 v0x26a1330_0; + %add; + %assign/vec4 v0x269d3e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.35 ; + %load/vec4 v0x269d3e0_0; + %load/vec4 v0x26a1330_0; + %sub; + %assign/vec4 v0x269d3e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.36 ; + %load/vec4 v0x269d920_0; + %pad/u 11; + %load/vec4 v0x26a1330_0; + %add; + %pad/u 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.37 ; + %load/vec4 v0x26a1330_0; + %assign/vec4 v0x26a1dc0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.38 ; + %load/vec4 v0x269d680_0; + %assign/vec4 v0x26a1dc0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.39 ; + %load/vec4 v0x269d3e0_0; + %load/vec4 v0x269d680_0; + %add; + %assign/vec4 v0x269d3e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.40 ; + %load/vec4 v0x269d3e0_0; + %load/vec4 v0x269d680_0; + %sub; + %assign/vec4 v0x269d3e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.41 ; + %load/vec4 v0x269d920_0; + %pad/u 11; + %load/vec4 v0x269d680_0; + %add; + %pad/u 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.42 ; + %load/vec4 v0x269d4e0_0; + %assign/vec4 v0x269d3e0_0, 0; + %load/vec4 v0x269d3e0_0; + %assign/vec4 v0x269d4e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.43 ; + %load/vec4 v0x269d3e0_0; + %assign/vec4 v0x269d4e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.44 ; + %load/vec4 v0x269d3e0_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x269d3e0_0, 0; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.45 ; + %load/vec4 v0x269d840_0; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.50; +T_4.46 ; + %load/vec4 v0x269d3e0_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_4.51, 4; + %load/vec4 v0x269d840_0; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.52; +T_4.51 ; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; +T_4.52 ; + %jmp T_4.50; +T_4.47 ; + %load/vec4 v0x269d3e0_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_4.53, 4; + %load/vec4 v0x269d840_0; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.54; +T_4.53 ; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; +T_4.54 ; + %jmp T_4.50; +T_4.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x269d3e0_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_4.55, 5; + %load/vec4 v0x269d840_0; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.56; +T_4.55 ; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; +T_4.56 ; + %jmp T_4.50; +T_4.49 ; + %load/vec4 v0x269d3e0_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_4.57, 5; + %load/vec4 v0x269d840_0; + %assign/vec4 v0x269da00_0, 0; + %jmp T_4.58; +T_4.57 ; + %load/vec4 v0x269d920_0; + %addi 1, 0, 4; + %assign/vec4 v0x269da00_0, 0; +T_4.58 ; + %jmp T_4.50; +T_4.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.7; +T_4.6 ; + %load/vec4 v0x269d760_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x269d760_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_4.59, 4; + %load/vec4 v0x269d5c0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x269d5c0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x26a07f0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_4.61, 9; + %load/vec4 v0x269d5c0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_4.63, 4; + %load/vec4 v0x26a1dc0_0; + %assign/vec4 v0x269d3e0_0, 0; +T_4.63 ; + %jmp T_4.62; +T_4.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %load/vec4 v0x269d5c0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.65, 4; + %load/vec4 v0x26a07f0_0; + %assign/vec4 v0x26a1ce0_0, 0; + %load/vec4 v0x26a1dc0_0; + %load/vec4 v0x26a07f0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a07f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %jmp T_4.66; +T_4.65 ; + %load/vec4 v0x269d5c0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.67, 4; + %load/vec4 v0x269d5c0_0; + %assign/vec4 v0x26a1ce0_0, 0; + %load/vec4 v0x26a1dc0_0; + %load/vec4 v0x269d5c0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x269d5c0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x269d5c0_0; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.68; +T_4.67 ; + %load/vec4 v0x26a0270_0; + %flag_set/vec4 8; + %jmp/0xz T_4.69, 8; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.72; +T_4.71 ; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.74; +T_4.73 ; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.76; +T_4.75 ; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; +T_4.77 ; +T_4.76 ; +T_4.74 ; +T_4.72 ; + %jmp T_4.70; +T_4.69 ; + %load/vec4 v0x269d5c0_0; + %assign/vec4 v0x26a1ce0_0, 0; +T_4.70 ; +T_4.68 ; +T_4.66 ; +T_4.62 ; +T_4.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.1 ; + %load/vec4 v0x26a0c60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.81, 6; + %jmp T_4.82; +T_4.79 ; + %load/vec4 v0x26a1290_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.83, 4; + %load/vec4 v0x26a00f0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a1a40_0, 0, 4; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.88; +T_4.87 ; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.90; +T_4.89 ; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.92; +T_4.91 ; + %load/vec4 v0x26a0d40_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; +T_4.93 ; +T_4.92 ; +T_4.90 ; +T_4.88 ; +T_4.85 ; + %jmp T_4.84; +T_4.83 ; + %load/vec4 v0x26a0d40_0; + %load/vec4 v0x26a1290_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %load/vec4 v0x26a1290_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a13d0, 4; + %assign/vec4 v0x26a1330_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a1290_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a11f0_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a1290_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a1a40_0, 4, 5; + %load/vec4 v0x26a1290_0; + %assign/vec4 v0x26a07f0_0, 0; +T_4.95 ; +T_4.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.82; +T_4.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.82; +T_4.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.82; +T_4.82 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x26a0c60_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.99, 6; + %jmp T_4.100; +T_4.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.100; +T_4.98 ; + %load/vec4 v0x26a1ce0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.101, 4; + %load/vec4 v0x26a0270_0; + %flag_set/vec4 8; + %jmp/0xz T_4.103, 8; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.106; +T_4.105 ; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.108; +T_4.107 ; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; + %jmp T_4.110; +T_4.109 ; + %load/vec4 v0x269f1a0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a1ce0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a1960_0, 4, 5; + %load/vec4 v0x26a1dc0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a0af0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a07f0_0, 0; +T_4.111 ; +T_4.110 ; +T_4.108 ; +T_4.106 ; +T_4.103 ; +T_4.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.100; +T_4.99 ; + %load/vec4 v0x26a1ce0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.113, 4; + %load/vec4 v0x26a1b20_0; + %load/vec4 v0x26a1ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x26a1ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x26a1960_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a0a30_0, 0; + %load/vec4 v0x26a1ce0_0; + %assign/vec4 v0x26a07f0_0, 0; +T_4.115 ; +T_4.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a0c60_0, 0; + %jmp T_4.100; +T_4.100 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0x269ce60; +T_5 ; + %wait E_0x25e9520; + %load/vec4 v0x26a0c60_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x26a0a30_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x269da00_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %load/vec4 v0x269da00_0; + %assign/vec4 v0x269d920_0, 0; +T_5.0 ; + %load/vec4 v0x26a0c60_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_5.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a11f0_0, 0, 4; +T_5.2 ; + %jmp T_5; + .thread T_5; + .scope S_0x26a2040; +T_6 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26a5c70_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26a5ec0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26a59d0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x26a2560_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x26a2660_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a2af0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a6450_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a6ca0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a6e60_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a6bc0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a5d50, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a5d50, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a5d50, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26a5d50, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x26a22a0, v0x26a5910 {0 0 0}; + %end; + .thread T_6; + .scope S_0x26a2040; +T_7 ; + %wait E_0x260bcc0; + %load/vec4 v0x26a5c70_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.2, 6; + %jmp T_7.3; +T_7.0 ; + %load/vec4 v0x26a5ec0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.6, 6; + %jmp T_7.7; +T_7.4 ; + %load/vec4 v0x26a28e0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_7.8, 5; + %load/vec4 v0x26a2cb0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_7.10, 5; + %load/vec4 v0x26a2cb0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %jmp T_7.11; +T_7.10 ; + %load/vec4 v0x26a2cb0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_7.12, 5; + %load/vec4 v0x26a5fa0_0; + %load/vec4 v0x26a2cb0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.14, 8; + %load/vec4 v0x26a2cb0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a2cb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %load/vec4 v0x26a2cb0_0; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.15; +T_7.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %load/vec4 v0x26a2cb0_0; + %assign/vec4 v0x26a64f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a2cb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; + %load/vec4 v0x26a2cb0_0; + %assign/vec4 v0x26a59d0_0, 0; +T_7.15 ; + %jmp T_7.13; +T_7.12 ; + %load/vec4 v0x26a2cb0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.16, 4; + %load/vec4 v0x26a59d0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_7.18, 4; + %load/vec4 v0x26a59d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %jmp T_7.19; +T_7.18 ; + %load/vec4 v0x26a5fa0_0; + %load/vec4 v0x26a59d0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.20, 8; + %load/vec4 v0x26a59d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a59d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %jmp T_7.21; +T_7.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %load/vec4 v0x26a59d0_0; + %assign/vec4 v0x26a64f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a59d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; +T_7.21 ; +T_7.19 ; + %jmp T_7.17; +T_7.16 ; + %load/vec4 v0x26a2cb0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.22, 4; + %load/vec4 v0x26a52c0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.24, 8; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.27; +T_7.26 ; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.29; +T_7.28 ; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.31; +T_7.30 ; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; +T_7.32 ; +T_7.31 ; +T_7.29 ; +T_7.27 ; + %jmp T_7.25; +T_7.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %load/vec4 v0x26a2cb0_0; + %assign/vec4 v0x26a64f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; +T_7.25 ; +T_7.22 ; +T_7.17 ; +T_7.13 ; +T_7.11 ; +T_7.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.7; +T_7.5 ; + %load/vec4 v0x26a28e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_7.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_7.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_7.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_7.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_7.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_7.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_7.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_7.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_7.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_7.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_7.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_7.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_7.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_7.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_7.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_7.49, 6; + %jmp T_7.50; +T_7.34 ; + %load/vec4 v0x26a2560_0; + %load/vec4 v0x26a6590_0; + %add; + %assign/vec4 v0x26a2560_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.35 ; + %load/vec4 v0x26a2560_0; + %load/vec4 v0x26a6590_0; + %sub; + %assign/vec4 v0x26a2560_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.36 ; + %load/vec4 v0x26a2af0_0; + %pad/u 11; + %load/vec4 v0x26a6590_0; + %add; + %pad/u 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.37 ; + %load/vec4 v0x26a6590_0; + %assign/vec4 v0x26a7020_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.38 ; + %load/vec4 v0x26a2800_0; + %assign/vec4 v0x26a7020_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.39 ; + %load/vec4 v0x26a2560_0; + %load/vec4 v0x26a2800_0; + %add; + %assign/vec4 v0x26a2560_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.40 ; + %load/vec4 v0x26a2560_0; + %load/vec4 v0x26a2800_0; + %sub; + %assign/vec4 v0x26a2560_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.41 ; + %load/vec4 v0x26a2af0_0; + %pad/u 11; + %load/vec4 v0x26a2800_0; + %add; + %pad/u 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.42 ; + %load/vec4 v0x26a2660_0; + %assign/vec4 v0x26a2560_0, 0; + %load/vec4 v0x26a2560_0; + %assign/vec4 v0x26a2660_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.43 ; + %load/vec4 v0x26a2560_0; + %assign/vec4 v0x26a2660_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.44 ; + %load/vec4 v0x26a2560_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x26a2560_0, 0; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.45 ; + %load/vec4 v0x26a2a10_0; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.50; +T_7.46 ; + %load/vec4 v0x26a2560_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_7.51, 4; + %load/vec4 v0x26a2a10_0; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.52; +T_7.51 ; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; +T_7.52 ; + %jmp T_7.50; +T_7.47 ; + %load/vec4 v0x26a2560_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_7.53, 4; + %load/vec4 v0x26a2a10_0; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.54; +T_7.53 ; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; +T_7.54 ; + %jmp T_7.50; +T_7.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x26a2560_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_7.55, 5; + %load/vec4 v0x26a2a10_0; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.56; +T_7.55 ; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; +T_7.56 ; + %jmp T_7.50; +T_7.49 ; + %load/vec4 v0x26a2560_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_7.57, 5; + %load/vec4 v0x26a2a10_0; + %assign/vec4 v0x26a2bd0_0, 0; + %jmp T_7.58; +T_7.57 ; + %load/vec4 v0x26a2af0_0; + %addi 1, 0, 4; + %assign/vec4 v0x26a2bd0_0, 0; +T_7.58 ; + %jmp T_7.50; +T_7.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.7; +T_7.6 ; + %load/vec4 v0x26a28e0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x26a28e0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_7.59, 4; + %load/vec4 v0x26a2740_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x26a2740_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x26a59d0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_7.61, 9; + %load/vec4 v0x26a2740_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_7.63, 4; + %load/vec4 v0x26a7020_0; + %assign/vec4 v0x26a2560_0, 0; +T_7.63 ; + %jmp T_7.62; +T_7.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %load/vec4 v0x26a2740_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_7.65, 4; + %load/vec4 v0x26a59d0_0; + %assign/vec4 v0x26a6f40_0, 0; + %load/vec4 v0x26a7020_0; + %load/vec4 v0x26a59d0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a59d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %jmp T_7.66; +T_7.65 ; + %load/vec4 v0x26a2740_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.67, 4; + %load/vec4 v0x26a2740_0; + %assign/vec4 v0x26a6f40_0, 0; + %load/vec4 v0x26a7020_0; + %load/vec4 v0x26a2740_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a2740_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a2740_0; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.68; +T_7.67 ; + %load/vec4 v0x26a5440_0; + %flag_set/vec4 8; + %jmp/0xz T_7.69, 8; + %load/vec4 v0x26a4370_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.72; +T_7.71 ; + %load/vec4 v0x26a4370_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.74; +T_7.73 ; + %load/vec4 v0x26a4370_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.76; +T_7.75 ; + %load/vec4 v0x26a4370_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; +T_7.77 ; +T_7.76 ; +T_7.74 ; +T_7.72 ; + %jmp T_7.70; +T_7.69 ; + %load/vec4 v0x26a2740_0; + %assign/vec4 v0x26a6f40_0, 0; +T_7.70 ; +T_7.68 ; +T_7.66 ; +T_7.62 ; +T_7.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.7; +T_7.7 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.1 ; + %load/vec4 v0x26a5ec0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.81, 6; + %jmp T_7.82; +T_7.79 ; + %load/vec4 v0x26a64f0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.83, 4; + %load/vec4 v0x26a52c0_0; + %flag_set/vec4 8; + %jmp/0xz T_7.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a6ca0_0, 0, 4; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.88; +T_7.87 ; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.90; +T_7.89 ; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.92; +T_7.91 ; + %load/vec4 v0x26a5fa0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; +T_7.93 ; +T_7.92 ; +T_7.90 ; +T_7.88 ; +T_7.85 ; + %jmp T_7.84; +T_7.83 ; + %load/vec4 v0x26a5fa0_0; + %load/vec4 v0x26a64f0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %load/vec4 v0x26a64f0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x26a6630, 4; + %assign/vec4 v0x26a6590_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a64f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6450_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26a64f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x26a6ca0_0, 4, 5; + %load/vec4 v0x26a64f0_0; + %assign/vec4 v0x26a59d0_0, 0; +T_7.95 ; +T_7.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.82; +T_7.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.82; +T_7.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.82; +T_7.82 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0x26a5ec0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_7.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_7.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_7.99, 6; + %jmp T_7.100; +T_7.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.100; +T_7.98 ; + %load/vec4 v0x26a6f40_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_7.101, 4; + %load/vec4 v0x26a5440_0; + %flag_set/vec4 8; + %jmp/0xz T_7.103, 8; + %load/vec4 v0x26a4370_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.106; +T_7.105 ; + %load/vec4 v0x26a4370_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.108; +T_7.107 ; + %load/vec4 v0x26a4370_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_7.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; + %jmp T_7.110; +T_7.109 ; + %load/vec4 v0x26a4370_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_7.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a6f40_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x26a6bc0_0, 4, 5; + %load/vec4 v0x26a7020_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26a5d50, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26a59d0_0, 0; +T_7.111 ; +T_7.110 ; +T_7.108 ; +T_7.106 ; +T_7.103 ; +T_7.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.100; +T_7.99 ; + %load/vec4 v0x26a6f40_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_7.113, 4; + %load/vec4 v0x26a6d80_0; + %load/vec4 v0x26a6f40_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_7.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x26a6f40_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x26a6bc0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a5c70_0, 0; + %load/vec4 v0x26a6f40_0; + %assign/vec4 v0x26a59d0_0, 0; +T_7.115 ; +T_7.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26a5ec0_0, 0; + %jmp T_7.100; +T_7.100 ; + %pop/vec4 1; + %jmp T_7.3; +T_7.3 ; + %pop/vec4 1; + %jmp T_7; + .thread T_7; + .scope S_0x26a2040; +T_8 ; + %wait E_0x25e9520; + %load/vec4 v0x26a5ec0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x26a5c70_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x26a2bd0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x26a2bd0_0; + %assign/vec4 v0x26a2af0_0, 0; +T_8.0 ; + %load/vec4 v0x26a5ec0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_8.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x26a6450_0, 0, 4; +T_8.2 ; + %jmp T_8; + .thread T_8; + .scope S_0x2692a60; +T_9 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2696670_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2696890_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26963d0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x2692f90_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x2693090_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2693520_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2696e20_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2697650_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2697810_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2697590_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2696750, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2696750, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2696750, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x2696750, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x2692c90, v0x2696310 {0 0 0}; + %end; + .thread T_9; + .scope S_0x2692a60; +T_10 ; + %wait E_0x260bcc0; + %load/vec4 v0x2696670_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.2, 6; + %jmp T_10.3; +T_10.0 ; + %load/vec4 v0x2696890_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.6, 6; + %jmp T_10.7; +T_10.4 ; + %load/vec4 v0x2693310_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_10.8, 5; + %load/vec4 v0x26936e0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_10.10, 5; + %load/vec4 v0x26936e0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %jmp T_10.11; +T_10.10 ; + %load/vec4 v0x26936e0_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_10.12, 5; + %load/vec4 v0x2696970_0; + %load/vec4 v0x26936e0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.14, 8; + %load/vec4 v0x26936e0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26936e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %load/vec4 v0x26936e0_0; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.15; +T_10.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %load/vec4 v0x26936e0_0; + %assign/vec4 v0x2696ec0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26936e0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2697650_0, 4, 5; + %load/vec4 v0x26936e0_0; + %assign/vec4 v0x26963d0_0, 0; +T_10.15 ; + %jmp T_10.13; +T_10.12 ; + %load/vec4 v0x26936e0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.16, 4; + %load/vec4 v0x26963d0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_10.18, 4; + %load/vec4 v0x26963d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %jmp T_10.19; +T_10.18 ; + %load/vec4 v0x2696970_0; + %load/vec4 v0x26963d0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.20, 8; + %load/vec4 v0x26963d0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26963d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %jmp T_10.21; +T_10.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %load/vec4 v0x26963d0_0; + %assign/vec4 v0x2696ec0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26963d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2697650_0, 4, 5; +T_10.21 ; +T_10.19 ; + %jmp T_10.17; +T_10.16 ; + %load/vec4 v0x26936e0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.22, 4; + %load/vec4 v0x2695cf0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.24, 8; + %load/vec4 v0x2696970_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.27; +T_10.26 ; + %load/vec4 v0x2696970_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.29; +T_10.28 ; + %load/vec4 v0x2696970_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.31; +T_10.30 ; + %load/vec4 v0x2696970_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26963d0_0, 0; +T_10.32 ; +T_10.31 ; +T_10.29 ; +T_10.27 ; + %jmp T_10.25; +T_10.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %load/vec4 v0x26936e0_0; + %assign/vec4 v0x2696ec0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697650_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697650_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697650_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697650_0, 4, 5; +T_10.25 ; +T_10.22 ; +T_10.17 ; +T_10.13 ; +T_10.11 ; +T_10.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.7; +T_10.5 ; + %load/vec4 v0x2693310_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_10.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_10.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_10.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_10.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_10.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_10.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_10.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_10.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_10.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_10.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_10.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_10.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_10.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_10.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_10.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_10.49, 6; + %jmp T_10.50; +T_10.34 ; + %load/vec4 v0x2692f90_0; + %load/vec4 v0x2696f60_0; + %add; + %assign/vec4 v0x2692f90_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.35 ; + %load/vec4 v0x2692f90_0; + %load/vec4 v0x2696f60_0; + %sub; + %assign/vec4 v0x2692f90_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.36 ; + %load/vec4 v0x2693520_0; + %pad/u 11; + %load/vec4 v0x2696f60_0; + %add; + %pad/u 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.37 ; + %load/vec4 v0x2696f60_0; + %assign/vec4 v0x26979d0_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.38 ; + %load/vec4 v0x2693230_0; + %assign/vec4 v0x26979d0_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.39 ; + %load/vec4 v0x2692f90_0; + %load/vec4 v0x2693230_0; + %add; + %assign/vec4 v0x2692f90_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.40 ; + %load/vec4 v0x2692f90_0; + %load/vec4 v0x2693230_0; + %sub; + %assign/vec4 v0x2692f90_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.41 ; + %load/vec4 v0x2693520_0; + %pad/u 11; + %load/vec4 v0x2693230_0; + %add; + %pad/u 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.42 ; + %load/vec4 v0x2693090_0; + %assign/vec4 v0x2692f90_0, 0; + %load/vec4 v0x2692f90_0; + %assign/vec4 v0x2693090_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.43 ; + %load/vec4 v0x2692f90_0; + %assign/vec4 v0x2693090_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.44 ; + %load/vec4 v0x2692f90_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x2692f90_0, 0; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.45 ; + %load/vec4 v0x2693440_0; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.50; +T_10.46 ; + %load/vec4 v0x2692f90_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_10.51, 4; + %load/vec4 v0x2693440_0; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.52; +T_10.51 ; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; +T_10.52 ; + %jmp T_10.50; +T_10.47 ; + %load/vec4 v0x2692f90_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_10.53, 4; + %load/vec4 v0x2693440_0; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.54; +T_10.53 ; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; +T_10.54 ; + %jmp T_10.50; +T_10.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x2692f90_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_10.55, 5; + %load/vec4 v0x2693440_0; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.56; +T_10.55 ; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; +T_10.56 ; + %jmp T_10.50; +T_10.49 ; + %load/vec4 v0x2692f90_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_10.57, 5; + %load/vec4 v0x2693440_0; + %assign/vec4 v0x2693600_0, 0; + %jmp T_10.58; +T_10.57 ; + %load/vec4 v0x2693520_0; + %addi 1, 0, 4; + %assign/vec4 v0x2693600_0, 0; +T_10.58 ; + %jmp T_10.50; +T_10.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.7; +T_10.6 ; + %load/vec4 v0x2693310_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x2693310_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_10.59, 4; + %load/vec4 v0x2693170_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x2693170_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x26963d0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_10.61, 9; + %load/vec4 v0x2693170_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_10.63, 4; + %load/vec4 v0x26979d0_0; + %assign/vec4 v0x2692f90_0, 0; +T_10.63 ; + %jmp T_10.62; +T_10.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %load/vec4 v0x2693170_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_10.65, 4; + %load/vec4 v0x26963d0_0; + %assign/vec4 v0x26978f0_0, 0; + %load/vec4 v0x26979d0_0; + %load/vec4 v0x26963d0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x26963d0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %jmp T_10.66; +T_10.65 ; + %load/vec4 v0x2693170_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.67, 4; + %load/vec4 v0x2693170_0; + %assign/vec4 v0x26978f0_0, 0; + %load/vec4 v0x26979d0_0; + %load/vec4 v0x2693170_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2693170_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x2693170_0; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.68; +T_10.67 ; + %load/vec4 v0x2695e70_0; + %flag_set/vec4 8; + %jmp/0xz T_10.69, 8; + %load/vec4 v0x2694da0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.72; +T_10.71 ; + %load/vec4 v0x2694da0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.74; +T_10.73 ; + %load/vec4 v0x2694da0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.76; +T_10.75 ; + %load/vec4 v0x2694da0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26963d0_0, 0; +T_10.77 ; +T_10.76 ; +T_10.74 ; +T_10.72 ; + %jmp T_10.70; +T_10.69 ; + %load/vec4 v0x2693170_0; + %assign/vec4 v0x26978f0_0, 0; +T_10.70 ; +T_10.68 ; +T_10.66 ; +T_10.62 ; +T_10.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.7; +T_10.7 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.1 ; + %load/vec4 v0x2696890_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.81, 6; + %jmp T_10.82; +T_10.79 ; + %load/vec4 v0x2696ec0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.83, 4; + %load/vec4 v0x2695cf0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2697650_0, 0, 4; + %load/vec4 v0x2696970_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.88; +T_10.87 ; + %load/vec4 v0x2696970_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.90; +T_10.89 ; + %load/vec4 v0x2696970_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.92; +T_10.91 ; + %load/vec4 v0x2696970_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26963d0_0, 0; +T_10.93 ; +T_10.92 ; +T_10.90 ; +T_10.88 ; +T_10.85 ; + %jmp T_10.84; +T_10.83 ; + %load/vec4 v0x2696970_0; + %load/vec4 v0x2696ec0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %load/vec4 v0x2696ec0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2697000, 4; + %assign/vec4 v0x2696f60_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2696ec0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2696e20_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2696ec0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2697650_0, 4, 5; + %load/vec4 v0x2696ec0_0; + %assign/vec4 v0x26963d0_0, 0; +T_10.95 ; +T_10.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.82; +T_10.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.82; +T_10.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.82; +T_10.82 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.2 ; + %load/vec4 v0x2696890_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_10.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_10.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_10.99, 6; + %jmp T_10.100; +T_10.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.100; +T_10.98 ; + %load/vec4 v0x26978f0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_10.101, 4; + %load/vec4 v0x2695e70_0; + %flag_set/vec4 8; + %jmp/0xz T_10.103, 8; + %load/vec4 v0x2694da0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.106; +T_10.105 ; + %load/vec4 v0x2694da0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.108; +T_10.107 ; + %load/vec4 v0x2694da0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_10.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x26963d0_0, 0; + %jmp T_10.110; +T_10.109 ; + %load/vec4 v0x2694da0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_10.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26978f0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2697590_0, 4, 5; + %load/vec4 v0x26979d0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x2696750, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x26963d0_0, 0; +T_10.111 ; +T_10.110 ; +T_10.108 ; +T_10.106 ; +T_10.103 ; +T_10.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.100; +T_10.99 ; + %load/vec4 v0x26978f0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_10.113, 4; + %load/vec4 v0x2697730_0; + %load/vec4 v0x26978f0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_10.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x26978f0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2697590_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2696670_0, 0; + %load/vec4 v0x26978f0_0; + %assign/vec4 v0x26963d0_0, 0; +T_10.115 ; +T_10.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2696890_0, 0; + %jmp T_10.100; +T_10.100 ; + %pop/vec4 1; + %jmp T_10.3; +T_10.3 ; + %pop/vec4 1; + %jmp T_10; + .thread T_10; + .scope S_0x2692a60; +T_11 ; + %wait E_0x25e9520; + %load/vec4 v0x2696890_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2696670_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x2693600_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0x2693600_0; + %assign/vec4 v0x2693520_0, 0; +T_11.0 ; + %load/vec4 v0x2696890_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_11.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2696e20_0, 0, 4; +T_11.2 ; + %jmp T_11; + .thread T_11; + .scope S_0x2601820; +T_12 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x26913e0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2691600_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2691140_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x264e310_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x268dd90_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x268e250_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2691b90_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2692460_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2692620_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2692380_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26914c0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26914c0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26914c0, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x26914c0, 4, 0; + %vpi_call 3 187 "$readmemb", P_0x25f5550, v0x2691080 {0 0 0}; + %end; + .thread T_12; + .scope S_0x2601820; +T_13 ; + %wait E_0x260bcc0; + %load/vec4 v0x26913e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.2, 6; + %jmp T_13.3; +T_13.0 ; + %load/vec4 v0x2691600_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.6, 6; + %jmp T_13.7; +T_13.4 ; + %load/vec4 v0x268e040_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_13.8, 5; + %load/vec4 v0x268e410_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_13.10, 5; + %load/vec4 v0x268e410_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %jmp T_13.11; +T_13.10 ; + %load/vec4 v0x268e410_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_13.12, 5; + %load/vec4 v0x26916e0_0; + %load/vec4 v0x268e410_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.14, 8; + %load/vec4 v0x268e410_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x268e410_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %load/vec4 v0x268e410_0; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.15; +T_13.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %load/vec4 v0x268e410_0; + %assign/vec4 v0x2691c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x268e410_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2692460_0, 4, 5; + %load/vec4 v0x268e410_0; + %assign/vec4 v0x2691140_0, 0; +T_13.15 ; + %jmp T_13.13; +T_13.12 ; + %load/vec4 v0x268e410_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.16, 4; + %load/vec4 v0x2691140_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_13.18, 4; + %load/vec4 v0x2691140_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %jmp T_13.19; +T_13.18 ; + %load/vec4 v0x26916e0_0; + %load/vec4 v0x2691140_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.20, 8; + %load/vec4 v0x2691140_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2691140_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %jmp T_13.21; +T_13.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %load/vec4 v0x2691140_0; + %assign/vec4 v0x2691c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2691140_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2692460_0, 4, 5; +T_13.21 ; +T_13.19 ; + %jmp T_13.17; +T_13.16 ; + %load/vec4 v0x268e410_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.22, 4; + %load/vec4 v0x2690a20_0; + %flag_set/vec4 8; + %jmp/0xz T_13.24, 8; + %load/vec4 v0x26916e0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.27; +T_13.26 ; + %load/vec4 v0x26916e0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.29; +T_13.28 ; + %load/vec4 v0x26916e0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.31; +T_13.30 ; + %load/vec4 v0x26916e0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2691140_0, 0; +T_13.32 ; +T_13.31 ; +T_13.29 ; +T_13.27 ; + %jmp T_13.25; +T_13.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %load/vec4 v0x268e410_0; + %assign/vec4 v0x2691c30_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692460_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692460_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692460_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692460_0, 4, 5; +T_13.25 ; +T_13.22 ; +T_13.17 ; +T_13.13 ; +T_13.11 ; +T_13.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.7; +T_13.5 ; + %load/vec4 v0x268e040_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_13.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_13.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_13.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_13.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_13.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_13.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_13.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_13.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_13.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_13.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_13.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_13.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_13.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_13.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_13.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_13.49, 6; + %jmp T_13.50; +T_13.34 ; + %load/vec4 v0x264e310_0; + %load/vec4 v0x2691d10_0; + %add; + %assign/vec4 v0x264e310_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.35 ; + %load/vec4 v0x264e310_0; + %load/vec4 v0x2691d10_0; + %sub; + %assign/vec4 v0x264e310_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.36 ; + %load/vec4 v0x268e250_0; + %pad/u 11; + %load/vec4 v0x2691d10_0; + %add; + %pad/u 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.37 ; + %load/vec4 v0x2691d10_0; + %assign/vec4 v0x26927e0_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.38 ; + %load/vec4 v0x268df60_0; + %assign/vec4 v0x26927e0_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.39 ; + %load/vec4 v0x264e310_0; + %load/vec4 v0x268df60_0; + %add; + %assign/vec4 v0x264e310_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.40 ; + %load/vec4 v0x264e310_0; + %load/vec4 v0x268df60_0; + %sub; + %assign/vec4 v0x264e310_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.41 ; + %load/vec4 v0x268e250_0; + %pad/u 11; + %load/vec4 v0x268df60_0; + %add; + %pad/u 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.42 ; + %load/vec4 v0x268dd90_0; + %assign/vec4 v0x264e310_0, 0; + %load/vec4 v0x264e310_0; + %assign/vec4 v0x268dd90_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.43 ; + %load/vec4 v0x264e310_0; + %assign/vec4 v0x268dd90_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.44 ; + %load/vec4 v0x264e310_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x264e310_0, 0; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.45 ; + %load/vec4 v0x268e170_0; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.50; +T_13.46 ; + %load/vec4 v0x264e310_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_13.51, 4; + %load/vec4 v0x268e170_0; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.52; +T_13.51 ; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; +T_13.52 ; + %jmp T_13.50; +T_13.47 ; + %load/vec4 v0x264e310_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_13.53, 4; + %load/vec4 v0x268e170_0; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.54; +T_13.53 ; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; +T_13.54 ; + %jmp T_13.50; +T_13.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x264e310_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_13.55, 5; + %load/vec4 v0x268e170_0; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.56; +T_13.55 ; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; +T_13.56 ; + %jmp T_13.50; +T_13.49 ; + %load/vec4 v0x264e310_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_13.57, 5; + %load/vec4 v0x268e170_0; + %assign/vec4 v0x268e330_0, 0; + %jmp T_13.58; +T_13.57 ; + %load/vec4 v0x268e250_0; + %addi 1, 0, 4; + %assign/vec4 v0x268e330_0, 0; +T_13.58 ; + %jmp T_13.50; +T_13.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.7; +T_13.6 ; + %load/vec4 v0x268e040_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x268e040_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_13.59, 4; + %load/vec4 v0x268de70_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x268de70_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x2691140_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_13.61, 9; + %load/vec4 v0x268de70_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_13.63, 4; + %load/vec4 v0x26927e0_0; + %assign/vec4 v0x264e310_0, 0; +T_13.63 ; + %jmp T_13.62; +T_13.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %load/vec4 v0x268de70_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_13.65, 4; + %load/vec4 v0x2691140_0; + %assign/vec4 v0x2692700_0, 0; + %load/vec4 v0x26927e0_0; + %load/vec4 v0x2691140_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2691140_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %jmp T_13.66; +T_13.65 ; + %load/vec4 v0x268de70_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.67, 4; + %load/vec4 v0x268de70_0; + %assign/vec4 v0x2692700_0, 0; + %load/vec4 v0x26927e0_0; + %load/vec4 v0x268de70_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x268de70_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x268de70_0; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.68; +T_13.67 ; + %load/vec4 v0x2690ba0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.69, 8; + %load/vec4 v0x268fad0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.72; +T_13.71 ; + %load/vec4 v0x268fad0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.74; +T_13.73 ; + %load/vec4 v0x268fad0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.76; +T_13.75 ; + %load/vec4 v0x268fad0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2691140_0, 0; +T_13.77 ; +T_13.76 ; +T_13.74 ; +T_13.72 ; + %jmp T_13.70; +T_13.69 ; + %load/vec4 v0x268de70_0; + %assign/vec4 v0x2692700_0, 0; +T_13.70 ; +T_13.68 ; +T_13.66 ; +T_13.62 ; +T_13.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.7; +T_13.7 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.1 ; + %load/vec4 v0x2691600_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.81, 6; + %jmp T_13.82; +T_13.79 ; + %load/vec4 v0x2691c30_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.83, 4; + %load/vec4 v0x2690a20_0; + %flag_set/vec4 8; + %jmp/0xz T_13.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2692460_0, 0, 4; + %load/vec4 v0x26916e0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.88; +T_13.87 ; + %load/vec4 v0x26916e0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.90; +T_13.89 ; + %load/vec4 v0x26916e0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.92; +T_13.91 ; + %load/vec4 v0x26916e0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2691140_0, 0; +T_13.93 ; +T_13.92 ; +T_13.90 ; +T_13.88 ; +T_13.85 ; + %jmp T_13.84; +T_13.83 ; + %load/vec4 v0x26916e0_0; + %load/vec4 v0x2691c30_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %load/vec4 v0x2691c30_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x2691df0, 4; + %assign/vec4 v0x2691d10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2691c30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2691b90_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x2691c30_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x2692460_0, 4, 5; + %load/vec4 v0x2691c30_0; + %assign/vec4 v0x2691140_0, 0; +T_13.95 ; +T_13.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.82; +T_13.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.82; +T_13.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.82; +T_13.82 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.2 ; + %load/vec4 v0x2691600_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_13.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_13.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_13.99, 6; + %jmp T_13.100; +T_13.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.100; +T_13.98 ; + %load/vec4 v0x2692700_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_13.101, 4; + %load/vec4 v0x2690ba0_0; + %flag_set/vec4 8; + %jmp/0xz T_13.103, 8; + %load/vec4 v0x268fad0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.106; +T_13.105 ; + %load/vec4 v0x268fad0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.108; +T_13.107 ; + %load/vec4 v0x268fad0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_13.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x2691140_0, 0; + %jmp T_13.110; +T_13.109 ; + %load/vec4 v0x268fad0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_13.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2692700_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x2692380_0, 4, 5; + %load/vec4 v0x26927e0_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x26914c0, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x2691140_0, 0; +T_13.111 ; +T_13.110 ; +T_13.108 ; +T_13.106 ; +T_13.103 ; +T_13.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.100; +T_13.99 ; + %load/vec4 v0x2692700_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_13.113, 4; + %load/vec4 v0x2692540_0; + %load/vec4 v0x2692700_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_13.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x2692700_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x2692380_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x26913e0_0, 0; + %load/vec4 v0x2692700_0; + %assign/vec4 v0x2691140_0, 0; +T_13.115 ; +T_13.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x2691600_0, 0; + %jmp T_13.100; +T_13.100 ; + %pop/vec4 1; + %jmp T_13.3; +T_13.3 ; + %pop/vec4 1; + %jmp T_13; + .thread T_13; + .scope S_0x2601820; +T_14 ; + %wait E_0x25e9520; + %load/vec4 v0x2691600_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x26913e0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x268e330_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %load/vec4 v0x268e330_0; + %assign/vec4 v0x268e250_0, 0; +T_14.0 ; + %load/vec4 v0x2691600_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_14.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2691b90_0, 0, 4; +T_14.2 ; + %jmp T_14; + .thread T_14; + .scope S_0x25d8690; +T_15 ; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x26a8080_0, 0, 33; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x26a7fe0_0, 0, 1; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x26a8080_0, 0, 33; +T_15.0 ; + %load/vec4 v0x26a8080_0; + %cmpi/u 10, 0, 33; + %jmp/0xz T_15.1, 5; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7f40_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x26a7f40_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7f40_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x26a7f40_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7f40_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x26a7f40_0, 0, 1; + %delay 1, 0; + %load/vec4 v0x26a8080_0; + %addi 1, 0, 33; + %store/vec4 v0x26a8080_0, 0, 33; + %jmp T_15.0; +T_15.1 ; + %load/vec4 v0x26a7ea0_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.2, 4; + %vpi_call 2 51 "$display", "Failed on up test of regTest, %d", v0x26a7ea0_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7fe0_0, 0, 1; +T_15.2 ; + %load/vec4 v0x26a7d60_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.4, 4; + %vpi_call 2 55 "$display", "Failed on left test of regTest, %d", v0x26a7d60_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7fe0_0, 0, 1; +T_15.4 ; + %load/vec4 v0x26a7e00_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.6, 4; + %vpi_call 2 59 "$display", "Failed on right test of regTest, %d", v0x26a7e00_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7fe0_0, 0, 1; +T_15.6 ; + %load/vec4 v0x26a7cc0_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.8, 4; + %vpi_call 2 63 "$display", "Failed on down test of regTest, %d", v0x26a7cc0_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7fe0_0, 0, 1; +T_15.8 ; + %load/vec4 v0x26a7b70_0; + %pad/s 32; + %cmpi/ne 1, 0, 32; + %jmp/0xz T_15.10, 4; + %vpi_call 2 67 "$display", "Failed on center test of regTest, %d", v0x26a7b70_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x26a7fe0_0, 0, 1; +T_15.10 ; + %load/vec4 v0x26a7fe0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.12, 8; + %vpi_call 2 71 "$display", "DUT passed regTest" {0 0 0}; +T_15.12 ; + %end; + .thread T_15; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "regTest/test.v"; + "./tis100.v"; diff --git a/regTest/test.asm b/regTest/test.asm new file mode 100644 index 0000000..aa75232 --- /dev/null +++ b/regTest/test.asm @@ -0,0 +1,36 @@ +:center +MOV 3 ACC +SUB UP +SUB 1 +ADD ACC +ADD ACC +ADD ACC +SUB 7 +JRO 0 + +:up +MOV 1 DOWN +MOV 1 ACC +SAV +MOV 5 ACC +SWP +JRO 0 + +:left +MOV -1 ACC +NEG +JRO 0 + +:right +MOV 5 ACC +SWP +MOV 1 ACC +SAV +SWP +JRO 0 + +:down +JRO 2 +ADD 40 +ADD 1 +JRO 0 diff --git a/regTest/test.v b/regTest/test.v new file mode 100644 index 0000000..e847652 --- /dev/null +++ b/regTest/test.v @@ -0,0 +1,75 @@ +`include "tis100.v" +module tis100Test(); + +reg clk; +wire signed[10:0] accOutCenter; +wire signed[10:0] accOutUp; +wire signed[10:0] accOutDown; +wire signed[10:0] accOutLeft; +wire signed[10:0] accOutRight; + +reg[32:0] i; + +wire[14:0] L2C; +wire[14:0] C2L; + +wire[14:0] R2C; +wire[14:0] C2R; + +wire[14:0] U2C; +wire[14:0] C2U; + +wire[14:0] D2C; +wire[14:0] C2D; + +reg dutPassed; + +tis100 #("regTest/left.dat") left( .clk(clk), .rightOut(L2C), .right(C2L), .accOut(accOutLeft)); +tis100 #("regTest/right.dat") right( .clk(clk), .leftOut(R2C), .left(C2R), .accOut(accOutRight)); +tis100 #("regTest/up.dat") up( .clk(clk), .downOut(U2C), .down(C2U), .accOut(accOutUp)); +tis100 #("regTest/down.dat") down( .clk(clk), .upOut(D2C), .up(C2D), .accOut(accOutDown)); +tis100 #("regTest/center.dat") center(.clk(clk), + .upOut(C2U), .up(U2C), + .downOut(C2D), .down(D2C), + .leftOut(C2L), .left(L2C), + .rightOut(C2R), .right(R2C), + .accOut(accOutCenter) + ); + +initial begin + i = 0; + dutPassed = 1; + for( i = 0; i<10; i=i+1) begin + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + end + if(accOutUp != 1) begin + $display("Failed on up test of regTest, %d", accOutUp); + dutPassed = 0; + end + if(accOutLeft != 1) begin + $display("Failed on left test of regTest, %d", accOutLeft); + dutPassed = 0; + end + if(accOutRight != 1) begin + $display("Failed on right test of regTest, %d", accOutRight); + dutPassed = 0; + end + if(accOutDown != 1) begin + $display("Failed on down test of regTest, %d", accOutDown); + dutPassed = 0; + end + if(accOutCenter != 1) begin + $display("Failed on center test of regTest, %d",accOutCenter); + dutPassed = 0; + end + if(dutPassed) begin + $display("DUT passed regTest"); + end +end + +endmodule diff --git a/regTest/up.dat b/regTest/up.dat new file mode 100644 index 0000000..d1eebf1 --- /dev/null +++ b/regTest/up.dat @@ -0,0 +1,16 @@ +010010100000000001 +010000100000000001 +100100000000000000 +010000100000000101 +100000000000000000 +011100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 +101100000000000000 diff --git a/right.dat b/right.dat new file mode 100644 index 0000000..57342cc --- /dev/null +++ b/right.dat @@ -0,0 +1,5 @@ +000000000000000000 +000000000000000000 +010001000000000101 +010000100000001100 +011100000000000000 diff --git a/rightAsm.txt b/rightAsm.txt new file mode 100644 index 0000000..9a32e3e --- /dev/null +++ b/rightAsm.txt @@ -0,0 +1,5 @@ +NOP +NOP +MOV 5 LEFT +MOV 12 ACC +JRO 0 diff --git a/stackmemory b/stackmemory new file mode 100755 index 0000000..a2a3ad1 --- /dev/null +++ b/stackmemory @@ -0,0 +1,588 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x11b76b0 .scope module, "stackMemoryTestBench" "stackMemoryTestBench" 2 2; + .timescale 0 0; +v0x11edbb0_0 .net *"_s12", 0 0, L_0x11ee9c0; 1 drivers +v0x11edc90_0 .net *"_s16", 0 0, L_0x11eea60; 1 drivers +v0x11edd70_0 .net *"_s20", 0 0, L_0x11eebc0; 1 drivers +v0x11ede30_0 .net *"_s24", 0 0, L_0x11eecc0; 1 drivers +v0x11edf10_0 .net *"_s6", 0 0, L_0x11ee8a0; 1 drivers +v0x11ee040_0 .var "clk", 0 0; +v0x11ee0e0_0 .var "counter", 5 0; +v0x11ee1a0_0 .var "dutpassed", 0 0; +v0x11ee260_0 .var "in", 14 0; +v0x11ee3e0_0 .net "out", 14 0, v0x11ed890_0; 1 drivers +v0x11ee4b0_0 .var "phase", 2 0; +v0x11ee570_0 .var "testcase", 3 0; +v0x11ee650_0 .var "val", 10 0; +E_0x11c26f0 .event negedge, v0x11ee1a0_0; +E_0x11c1650 .event negedge, L_0x11eecc0; +E_0x11c1e50 .event posedge, L_0x11eebc0; +E_0x11c1890 .event negedge, L_0x11eea60; +E_0x11c2410 .event posedge, L_0x11ee9c0; +E_0x11c2130 .event posedge, L_0x11ee8a0; +L_0x11ee8a0 .part v0x11ed890_0, 13, 1; +L_0x11ee9c0 .part v0x11ed890_0, 14, 1; +L_0x11eea60 .part v0x11ed890_0, 11, 1; +L_0x11eebc0 .part v0x11ed890_0, 13, 1; +L_0x11eecc0 .part v0x11ed890_0, 12, 1; +S_0x11b7830 .scope module, "dut" "stackMemory" 2 17, 3 11 0, S_0x11b76b0; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "in" + .port_info 2 /OUTPUT 15 "out" +P_0x11b5a10 .param/l "initialpointer" 0 3 15, +C4<00000000000000000000000000000100>; +P_0x11b5a50 .param/l "loadmemory" 0 3 13, +C4<00000000000000000000000000000001>; +P_0x11b5a90 .param/str "memoryfile" 0 3 14, "mem.dat"; +v0x11aeb90_0 .net *"_s2", 0 0, L_0x11ee730; 1 drivers +v0x11ed4f0_0 .net *"_s6", 0 0, L_0x11ee800; 1 drivers +v0x11ed5d0_0 .net "clk", 0 0, v0x11ee040_0; 1 drivers +v0x11ed6a0_0 .net "in", 14 0, v0x11ee260_0; 1 drivers +v0x11ed780 .array "mem", 1 15, 10 0; +v0x11ed890_0 .var "out", 14 0; +v0x11ed970_0 .var "phase", 2 0; +v0x11eda50_0 .var "pointer", 3 0; +E_0x11b7f50 .event negedge, v0x11ed5d0_0; +E_0x11b8340 .event posedge, v0x11ed5d0_0; +E_0x11b8b00 .event edge, v0x11eda50_0; +E_0x11b8720 .event posedge, L_0x11ee800; +E_0x11b90f0 .event posedge, L_0x11ee730; +L_0x11ee730 .part v0x11ee260_0, 14, 1; +L_0x11ee800 .part v0x11ee260_0, 13, 1; + .scope S_0x11b7830; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x11ed970_0, 0, 3; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x11eda50_0, 0, 4; + %pushi/vec4 0, 0, 15; + %store/vec4 v0x11ed890_0, 0, 15; + %vpi_call 3 30 "$readmemb", P_0x11b5a90, v0x11ed780 {0 0 0}; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_0.0, 5; + %load/vec4 v0x11eda50_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x11ed780, 4; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ed890_0, 4, 11; +T_0.0 ; + %end; + .thread T_0; + .scope S_0x11b7830; +T_1 ; + %wait E_0x11b90f0; + %load/vec4 v0x11eda50_0; + %subi 1, 0, 4; + %store/vec4 v0x11eda50_0, 0, 4; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_1.0, 5; + %load/vec4 v0x11eda50_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x11ed780, 4; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ed890_0, 4, 11; +T_1.0 ; + %jmp T_1; + .thread T_1; + .scope S_0x11b7830; +T_2 ; + %wait E_0x11b8720; + %load/vec4 v0x11eda50_0; + %subi 1, 0, 4; + %store/vec4 v0x11eda50_0, 0, 4; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_2.0, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; + %load/vec4 v0x11eda50_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x11ed780, 4; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; + %jmp T_2.1; +T_2.0 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x11b7830; +T_3 ; + %wait E_0x11b8b00; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmpi/u 15, 0, 32; + %jmp/0xz T_3.0, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 12, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; + %jmp T_3.1; +T_3.0 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 12, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; +T_3.1 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_3.2, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; + %jmp T_3.3; +T_3.2 ; + %pushi/vec4 0, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; +T_3.3 ; + %jmp T_3; + .thread T_3, $push; + .scope S_0x11b7830; +T_4 ; + %wait E_0x11b8340; + %load/vec4 v0x11ed970_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0x11ed6a0_0; + %parti/s 1, 11, 5; + %flag_set/vec4 8; + %jmp/0xz T_4.4, 8; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmpi/u 15, 0, 32; + %jmp/0xz T_4.6, 5; + %load/vec4 v0x11eda50_0; + %addi 1, 0, 4; + %store/vec4 v0x11eda50_0, 0, 4; + %load/vec4 v0x11ed6a0_0; + %parti/s 11, 0, 2; + %load/vec4 v0x11eda50_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %store/vec4a v0x11ed780, 4, 0; + %vpi_call 3 72 "$display", "%b", v0x11ed6a0_0 {0 0 0}; + %pushi/vec4 1, 0, 1; + %ix/load 4, 13, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; +T_4.6 ; +T_4.4 ; + %jmp T_4.3; +T_4.1 ; + %jmp T_4.3; +T_4.2 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x11eda50_0; + %pad/u 32; + %cmp/u; + %jmp/0xz T_4.8, 5; + %load/vec4 v0x11eda50_0; + %pad/u 6; + %subi 1, 0, 6; + %ix/vec4 4; + %load/vec4a v0x11ed780, 4; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; + %load/vec4 v0x11ed6a0_0; + %parti/s 1, 12, 5; + %flag_set/vec4 8; + %jmp/0xz T_4.10, 8; + %load/vec4 v0x11eda50_0; + %subi 1, 0, 4; + %store/vec4 v0x11eda50_0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 4, 14, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ed890_0, 4, 5; +T_4.10 ; +T_4.8 ; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0x11b7830; +T_5 ; + %wait E_0x11b7f50; + %load/vec4 v0x11ed970_0; + %cmpi/e 2, 0, 3; + %jmp/0xz T_5.0, 4; + %pushi/vec4 0, 0, 1; + %ix/load 4, 13, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ed890_0, 4, 1; + %pushi/vec4 0, 0, 1; + %ix/load 4, 14, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ed890_0, 4, 1; +T_5.0 ; + %load/vec4 v0x11ed970_0; + %pad/u 32; + %addi 1, 0, 32; + %pushi/vec4 3, 0, 32; + %mod; + %pad/u 3; + %store/vec4 v0x11ed970_0, 0, 3; + %jmp T_5; + .thread T_5; + .scope S_0x11b76b0; +T_6 ; + %delay 10, 0; + %load/vec4 v0x11ee040_0; + %nor/r; + %store/vec4 v0x11ee040_0, 0, 1; + %jmp T_6; + .thread T_6; + .scope S_0x11b76b0; +T_7 ; + %vpi_call 2 26 "$dumpfile", "test.vcd" {0 0 0}; + %vpi_call 2 27 "$dumpvars", 32'sb00000000000000000000000000000000 {0 0 0}; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x11ee040_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0x11ee1a0_0, 0; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11ee4b0_0, 0; + %pushi/vec4 0, 0, 15; + %assign/vec4 v0x11ee260_0, 0; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x11ee570_0, 0; + %pushi/vec4 1, 0, 6; + %assign/vec4 v0x11ee0e0_0, 0; + %delay 30, 0; + %load/vec4 v0x11ee3e0_0; + %parti/s 1, 11, 5; + %nor/r; + %flag_set/vec4 8; + %load/vec4 v0x11ee3e0_0; + %parti/s 1, 12, 5; + %nor/r; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x11ee3e0_0; + %parti/s 1, 13, 5; + %flag_set/vec4 8; + %flag_or 8, 9; + %load/vec4 v0x11ee3e0_0; + %parti/s 1, 14, 5; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_7.0, 9; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x11ee1a0_0, 0, 1; +T_7.0 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 12, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x11ee570_0, 0, 4; + %end; + .thread T_7; + .scope S_0x11b76b0; +T_8 ; + %wait E_0x11b8340; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %pushi/vec4 1, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x11ee4b0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %load/vec4 v0x11ee3e0_0; + %parti/s 11, 0, 2; + %assign/vec4 v0x11ee650_0, 0; + %load/vec4 v0x11ee650_0; + %cmpi/ne 1394, 0, 11; + %jmp/0xz T_8.2, 4; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x11ee1a0_0, 0, 1; +T_8.2 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 14, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ee260_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 4, 12, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ee260_0, 4, 5; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x11ee570_0, 0, 4; +T_8.0 ; + %jmp T_8; + .thread T_8; + .scope S_0x11b76b0; +T_9 ; + %wait E_0x11b8340; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %pushi/vec4 2, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x11ee4b0_0; + %pushi/vec4 2, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_9.0, 8; + %pushi/vec4 186, 0, 11; + %store/vec4 v0x11ee650_0, 0, 11; + %load/vec4 v0x11ee650_0; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ee260_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ee260_0, 4, 5; +T_9.0 ; + %jmp T_9; + .thread T_9; + .scope S_0x11b76b0; +T_10 ; + %wait E_0x11c2130; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %cmpi/e 2, 0, 32; + %jmp/0xz T_10.0, 4; + %pushi/vec4 0, 0, 1; + %ix/load 4, 11, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x11ee260_0, 4, 5; + %pushi/vec4 3, 0, 4; + %store/vec4 v0x11ee570_0, 0, 4; +T_10.0 ; + %jmp T_10; + .thread T_10; + .scope S_0x11b76b0; +T_11 ; + %wait E_0x11b8340; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %pushi/vec4 3, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x11ee4b0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0x11ee3e0_0; + %parti/s 11, 0, 2; + %store/vec4 v0x11ee650_0, 0, 11; + %load/vec4 v0x11ee650_0; + %cmpi/ne 186, 0, 11; + %jmp/0xz T_11.2, 4; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x11ee1a0_0, 0, 1; + %jmp T_11.3; +T_11.2 ; + %pushi/vec4 1, 0, 1; + %ix/load 4, 14, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x11ee570_0, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 4, 12, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; +T_11.3 ; +T_11.0 ; + %jmp T_11; + .thread T_11; + .scope S_0x11b76b0; +T_12 ; + %wait E_0x11c2410; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %cmpi/e 4, 0, 32; + %jmp/0xz T_12.0, 4; + %load/vec4 v0x11ee0e0_0; + %addi 1, 0, 6; + %store/vec4 v0x11ee0e0_0, 0, 6; +T_12.0 ; + %jmp T_12; + .thread T_12; + .scope S_0x11b76b0; +T_13 ; + %wait E_0x11c1890; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %cmpi/e 4, 0, 32; + %jmp/0xz T_13.0, 4; + %load/vec4 v0x11ee0e0_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_13.2, 4; + %pushi/vec4 0, 0, 1; + %ix/load 4, 12, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; + %pushi/vec4 0, 0, 6; + %store/vec4 v0x11ee0e0_0, 0, 6; + %load/vec4 v0x11ee0e0_0; + %pad/u 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 11; + %pushi/vec4 1, 0, 1; + %ix/load 4, 11, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x11ee570_0, 0, 4; + %jmp T_13.3; +T_13.2 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x11ee1a0_0, 0, 1; +T_13.3 ; +T_13.0 ; + %jmp T_13; + .thread T_13; + .scope S_0x11b76b0; +T_14 ; + %wait E_0x11c1e50; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %cmpi/e 5, 0, 32; + %jmp/0xz T_14.0, 4; + %load/vec4 v0x11ee0e0_0; + %addi 1, 0, 6; + %store/vec4 v0x11ee0e0_0, 0, 6; + %load/vec4 v0x11ee0e0_0; + %pad/u 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 11; +T_14.0 ; + %jmp T_14; + .thread T_14; + .scope S_0x11b76b0; +T_15 ; + %wait E_0x11c1650; + %load/vec4 v0x11ee570_0; + %pad/u 32; + %cmpi/e 5, 0, 32; + %jmp/0xz T_15.0, 4; + %load/vec4 v0x11ee0e0_0; + %pad/u 32; + %cmpi/ne 15, 0, 32; + %jmp/0xz T_15.2, 4; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x11ee1a0_0, 0, 1; + %jmp T_15.3; +T_15.2 ; + %vpi_call 2 123 "$display", "DUT Passed" {0 0 0}; + %vpi_call 2 124 "$finish" {0 0 0}; +T_15.3 ; +T_15.0 ; + %jmp T_15; + .thread T_15; + .scope S_0x11b76b0; +T_16 ; + %wait E_0x11b7f50; + %load/vec4 v0x11ee4b0_0; + %cmpi/e 2, 0, 3; + %jmp/0xz T_16.0, 4; + %pushi/vec4 0, 0, 1; + %ix/load 4, 13, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; + %pushi/vec4 0, 0, 1; + %ix/load 4, 14, 0; + %flag_set/imm 4, 0; + %store/vec4 v0x11ee260_0, 4, 1; +T_16.0 ; + %load/vec4 v0x11ee4b0_0; + %pad/u 32; + %addi 1, 0, 32; + %pushi/vec4 3, 0, 32; + %mod; + %pad/u 3; + %store/vec4 v0x11ee4b0_0, 0, 3; + %jmp T_16; + .thread T_16; + .scope S_0x11b76b0; +T_17 ; + %wait E_0x11c26f0; + %vpi_call 2 138 "$display", "DUT Failed Test: %d", v0x11ee570_0 {0 0 0}; + %vpi_call 2 139 "$finish" {0 0 0}; + %jmp T_17; + .thread T_17; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "stackmemory.t.v"; + "./stackmemory.v"; diff --git a/stackmemory.t.v b/stackmemory.t.v new file mode 100644 index 0000000..fcb0322 --- /dev/null +++ b/stackmemory.t.v @@ -0,0 +1,142 @@ +`include "stackmemory.v" +module stackMemoryTestBench + (); + + reg clk; + reg dutpassed; + wire [14:0] out; + reg [10:0] val; + reg [14:0] in; + reg [3:0] testcase; + reg [2:0] phase; + reg [5:0] counter; + + + always #10 clk = !clk; + + stackMemory #( .loadmemory(1), .initialpointer(4)) dut + ( + .clk(clk), + .in(in), + .out(out) + ); + + + initial begin + $dumpfile("test.vcd"); + $dumpvars(0); + clk <= 0; + dutpassed <= 1; + phase <= `READ_PHASE; + in <= 0; + testcase <= 0; + counter <= 1; + + #30;//time to cycle clock + //Test Case 0: check flags + if(!out[`READ_REQ_BIT] || !out[`WRITE_REQ_BIT] || out[`READ_ACK_BIT] || out[`WRITE_ACK_BIT]) + dutpassed = 0; + in[`WRITE_REQ_BIT] = 1; + testcase = 1; + end + + //Test Case 1: read a value + always @(posedge clk) begin + if(testcase == 1 && phase == `READ_PHASE) begin + val <= out[10:0]; + + if(val != 11'b10101110010) + dutpassed = 0; + in[`WRITE_ACK_BIT] <= 1; + in[`WRITE_REQ_BIT] <= 0; + + testcase = 2; + end + end + + //Test Case 2: write a value + always @(posedge clk) begin + if(testcase == 2 && phase == `WRITE_PHASE) begin + val = 11'hBA; + in[10:0] <= val; + in[`READ_REQ_BIT] <= 1; + end + end + + always @(posedge out[`READ_ACK_BIT]) begin + if(testcase == 2) begin + in[`READ_REQ_BIT] <= 0; + + testcase = 3; + end + end + + //Test Case 3: read that value + always @(posedge clk) begin + if(testcase == 3 && phase == `READ_PHASE) begin + val = out[10:0]; + + if(val != 11'hBA) begin + dutpassed = 0; + end + else begin + in[`WRITE_ACK_BIT] = 1; + testcase = 4; + in[`WRITE_REQ_BIT] = 1; + end + end + end + + //Test Case 4: read until empty + always @(posedge out[`WRITE_ACK_BIT]) begin + if(testcase == 4) + counter = counter +1; + end + + always @(negedge out[`READ_REQ_BIT]) begin + if(testcase == 4) begin + if(counter == 3) begin + in[`WRITE_REQ_BIT] = 0; + counter = 0; + in[10:0] = counter; + in[`READ_REQ_BIT] = 1; + testcase = 5; + end + else + dutpassed = 0; + end + end // always @ (negedge out[`READ_REQ_BIT]) + + //Test Case 5: write until full + always @(posedge out[`READ_ACK_BIT]) begin + if(testcase == 5) begin + counter = counter + 1; + in[10:0] = counter; + end + end + + always @(negedge out[`WRITE_REQ_BIT]) begin + if(testcase == 5) begin + if(counter != 15) + dutpassed = 0; + else begin + $display("DUT Passed"); + $finish(); + end + end + end + + always @(negedge clk) begin + if (phase == `WRITE_PHASE) begin + in[`READ_ACK_BIT] = 0; + in[`WRITE_ACK_BIT] = 0; + end + phase = (phase + 1) % 3; + end + + always @(negedge dutpassed) begin + $display("DUT Failed Test: %d", testcase); + $finish(); + end + +endmodule diff --git a/stackmemory.v b/stackmemory.v new file mode 100644 index 0000000..b283954 --- /dev/null +++ b/stackmemory.v @@ -0,0 +1,99 @@ +//acts as read ANY, write ANY in terms of read, write presedence +//15 stack entries +`define READ_REQ_BIT 11 +`define WRITE_REQ_BIT 12 +`define READ_ACK_BIT 13 +`define WRITE_ACK_BIT 14 + +`define READ_PHASE 2'd0 +`define EX_PHASE 2'd1 +`define WRITE_PHASE 2'd2 +module stackMemory + #( + parameter loadmemory = 0, + parameter memoryfile = "mem.dat", + parameter initialpointer = 0 + ) + (input clk, + input [14:0] in, + output reg [14:0] out); + reg [10:0] mem [15:1]; + reg [3:0] pointer; + reg [2:0] phase; + + initial begin + phase = `READ_PHASE; + pointer = initialpointer; + out = 0; + + if(loadmemory) + $readmemb(memoryfile, mem); + if (pointer > 0) begin + out[10:0] = mem[pointer]; + end + end + + always @(posedge in[`WRITE_ACK_BIT]) begin + pointer = pointer - 1; + if(pointer > 0) begin + out[10:0] = mem[pointer]; + end + end + + always @(posedge in[`READ_ACK_BIT]) begin + pointer = pointer -1; + if (pointer > 0) begin + out[`READ_REQ_BIT] <= 1; + out[10:0] <= mem[pointer]; + end + else + out[`READ_REQ_BIT] <= 0; + end + + always @(pointer) begin + if(pointer < 15) + out[`WRITE_REQ_BIT] <= 1; + else + out[`WRITE_REQ_BIT] <= 0; + + if (pointer > 0) + out[`READ_REQ_BIT] <= 1; + else + out[`READ_REQ_BIT] <= 0; + end // always @ (pointer) + + always @(posedge clk) begin + case(phase) + `READ_PHASE: + if(in[`READ_REQ_BIT]) begin + if(pointer < 15) begin + pointer = pointer + 1; + mem[pointer] = in[10:0]; + out[`READ_ACK_BIT] <= 1; + end + end + `EX_PHASE: begin + + end + `WRITE_PHASE: + if(pointer > 0) begin + out[10:0] <= mem[pointer]; + if(in[`WRITE_REQ_BIT]) begin + pointer = pointer - 1; + out[`WRITE_ACK_BIT] <= 1; + end + end + + endcase + end // always @ (posedge clk) + + always @(negedge clk) begin + if (phase == `WRITE_PHASE) begin + out[`READ_ACK_BIT] = 0; + out[`WRITE_ACK_BIT] = 0; + end + phase = (phase + 1) % 3; + end + + +endmodule diff --git a/test.vcd b/test.vcd new file mode 100644 index 0000000..0a06cdb --- /dev/null +++ b/test.vcd @@ -0,0 +1,577 @@ +$date + Mon Dec 11 22:36:46 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module stackMemoryTestBench $end +$var wire 15 ! out [14:0] $end +$var reg 1 " clk $end +$var reg 6 # counter [5:0] $end +$var reg 1 $ dutpassed $end +$var reg 15 % in [14:0] $end +$var reg 3 & phase [2:0] $end +$var reg 4 ' testcase [3:0] $end +$var reg 11 ( val [10:0] $end +$scope module dut $end +$var wire 1 " clk $end +$var wire 15 ) in [14:0] $end +$var reg 15 * out [14:0] $end +$var reg 3 + phase [2:0] $end +$var reg 4 , pointer [3:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b100 , +b1 + +b1110101110010 * +b0 ) +bx ( +b0 ' +b1 & +b0 % +1$ +b1 # +0" +b1110101110010 ! +$end +#10 +1" +#20 +b10 & +b10 + +0" +#30 +b101110101110010 ! +b101110101110010 * +b11 , +1" +b1 ' +b1000000000000 % +b1000000000000 ) +#40 +b0 + +b1110101110010 ! +b1110101110010 * +b0 & +0" +#50 +b1110101110110 ! +b1110101110110 * +b10 , +b100000000000000 % +b100000000000000 ) +b10101110010 ( +b10 ' +1" +#60 +b1 & +b1 + +0" +#70 +1" +#80 +b10 + +b10 & +0" +#90 +b100100010111010 % +b100100010111010 ) +b10111010 ( +1" +#100 +b0 & +b100010111010 % +b100010111010 ) +b0 + +0" +#110 +b10111010 % +b10111010 ) +b11 ' +b11110101110110 ! +b11110101110110 * +b11 , +1" +#120 +b1 + +b1 & +0" +#130 +1" +#140 +b10 & +b10 + +0" +#150 +b11100010111010 ! +b11100010111010 * +1" +#160 +b0 + +b1100010111010 ! +b1100010111010 * +b0 & +0" +#170 +b1110101110110 ! +b1110101110110 * +b10 , +b100 ' +b101000010111010 % +b101000010111010 ) +1" +#180 +b1 & +b1 + +0" +#190 +1" +#200 +b10 + +b10 & +0" +#210 +b10 # +b101110101110110 ! +b101110101110110 * +b1 , +1" +#220 +b0 & +b1000010111010 % +b1000010111010 ) +b0 + +b1110101110110 ! +b1110101110110 * +0" +#230 +1" +#240 +b1 + +b1 & +0" +#250 +1" +#260 +b10 & +b10 + +0" +#270 +b101 ' +b100000000000 % +b100000000000 ) +b0 # +b101000000000000 ! +b101000000000000 * +b0 , +1" +#280 +b0 + +b1000000000000 ! +b1000000000000 * +b0 & +0" +#290 +b100000000001 % +b100000000001 ) +b1 # +b11100000000000 ! +b11100000000000 * +b1 , +1" +#300 +b1 & +b1 + +0" +#310 +1" +#320 +b10 + +b10 & +0" +#330 +1" +#340 +b0 & +b0 + +b1100000000000 ! +b1100000000000 * +0" +#350 +b100000000010 % +b100000000010 ) +b10 # +b11100000000000 ! +b11100000000000 * +b10 , +1" +#360 +b1 + +b1 & +0" +#370 +1" +#380 +b10 & +b10 + +0" +#390 +b11100000000001 ! +b11100000000001 * +1" +#400 +b0 + +b1100000000001 ! +b1100000000001 * +b0 & +0" +#410 +b100000000011 % +b100000000011 ) +b11 # +b11100000000001 ! +b11100000000001 * +b11 , +1" +#420 +b1 & +b1 + +0" +#430 +1" +#440 +b10 + +b10 & +0" +#450 +b11100000000010 ! +b11100000000010 * +1" +#460 +b0 & +b0 + +b1100000000010 ! +b1100000000010 * +0" +#470 +b100000000100 % +b100000000100 ) +b100 # +b11100000000010 ! +b11100000000010 * +b100 , +1" +#480 +b1 + +b1 & +0" +#490 +1" +#500 +b10 & +b10 + +0" +#510 +b11100000000011 ! +b11100000000011 * +1" +#520 +b0 + +b1100000000011 ! +b1100000000011 * +b0 & +0" +#530 +b100000000101 % +b100000000101 ) +b101 # +b11100000000011 ! +b11100000000011 * +b101 , +1" +#540 +b1 & +b1 + +0" +#550 +1" +#560 +b10 + +b10 & +0" +#570 +b11100000000100 ! +b11100000000100 * +1" +#580 +b0 & +b0 + +b1100000000100 ! +b1100000000100 * +0" +#590 +b100000000110 % +b100000000110 ) +b110 # +b11100000000100 ! +b11100000000100 * +b110 , +1" +#600 +b1 + +b1 & +0" +#610 +1" +#620 +b10 & +b10 + +0" +#630 +b11100000000101 ! +b11100000000101 * +1" +#640 +b0 + +b1100000000101 ! +b1100000000101 * +b0 & +0" +#650 +b100000000111 % +b100000000111 ) +b111 # +b11100000000101 ! +b11100000000101 * +b111 , +1" +#660 +b1 & +b1 + +0" +#670 +1" +#680 +b10 + +b10 & +0" +#690 +b11100000000110 ! +b11100000000110 * +1" +#700 +b0 & +b0 + +b1100000000110 ! +b1100000000110 * +0" +#710 +b100000001000 % +b100000001000 ) +b1000 # +b11100000000110 ! +b11100000000110 * +b1000 , +1" +#720 +b1 + +b1 & +0" +#730 +1" +#740 +b10 & +b10 + +0" +#750 +b11100000000111 ! +b11100000000111 * +1" +#760 +b0 + +b1100000000111 ! +b1100000000111 * +b0 & +0" +#770 +b100000001001 % +b100000001001 ) +b1001 # +b11100000000111 ! +b11100000000111 * +b1001 , +1" +#780 +b1 & +b1 + +0" +#790 +1" +#800 +b10 + +b10 & +0" +#810 +b11100000001000 ! +b11100000001000 * +1" +#820 +b0 & +b0 + +b1100000001000 ! +b1100000001000 * +0" +#830 +b100000001010 % +b100000001010 ) +b1010 # +b11100000001000 ! +b11100000001000 * +b1010 , +1" +#840 +b1 + +b1 & +0" +#850 +1" +#860 +b10 & +b10 + +0" +#870 +b11100000001001 ! +b11100000001001 * +1" +#880 +b0 + +b1100000001001 ! +b1100000001001 * +b0 & +0" +#890 +b100000001011 % +b100000001011 ) +b1011 # +b11100000001001 ! +b11100000001001 * +b1011 , +1" +#900 +b1 & +b1 + +0" +#910 +1" +#920 +b10 + +b10 & +0" +#930 +b11100000001010 ! +b11100000001010 * +1" +#940 +b0 & +b0 + +b1100000001010 ! +b1100000001010 * +0" +#950 +b100000001100 % +b100000001100 ) +b1100 # +b11100000001010 ! +b11100000001010 * +b1100 , +1" +#960 +b1 + +b1 & +0" +#970 +1" +#980 +b10 & +b10 + +0" +#990 +b11100000001011 ! +b11100000001011 * +1" +#1000 +b0 + +b1100000001011 ! +b1100000001011 * +b0 & +0" +#1010 +b100000001101 % +b100000001101 ) +b1101 # +b11100000001011 ! +b11100000001011 * +b1101 , +1" +#1020 +b1 & +b1 + +0" +#1030 +1" +#1040 +b10 + +b10 & +0" +#1050 +b11100000001100 ! +b11100000001100 * +1" +#1060 +b0 & +b0 + +b1100000001100 ! +b1100000001100 * +0" +#1070 +b100000001110 % +b100000001110 ) +b1110 # +b11100000001100 ! +b11100000001100 * +b1110 , +1" +#1080 +b1 + +b1 & +0" +#1090 +1" +#1100 +b10 & +b10 + +0" +#1110 +b11100000001101 ! +b11100000001101 * +1" +#1120 +b0 + +b1100000001101 ! +b1100000001101 * +b0 & +0" +#1130 +b100000001111 % +b100000001111 ) +b1111 # +b10100000001101 ! +b10100000001101 * +b1111 , +1" diff --git a/tis100 b/tis100 new file mode 100755 index 0000000..2a7d711 --- /dev/null +++ b/tis100 @@ -0,0 +1,2448 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x1117100 .scope module, "tis100Test" "tis100Test" 2 2; + .timescale 0 0; +v0x1163a00_0 .net "L2R", 14 0, L_0x1177b30; 1 drivers +v0x1163b30_0 .net "R2L", 14 0, L_0x117b450; 1 drivers +v0x1163c40_0 .net/s "accOutLeft", 10 0, L_0x1163fb0; 1 drivers +v0x1163ce0_0 .net/s "accOutRight", 10 0, L_0x1177e80; 1 drivers +v0x1163db0_0 .var "clk", 0 0; +v0x1163ef0_0 .var "i", 32 0; +S_0x10b3c70 .scope module, "left" "tis100" 2 12, 3 49 0, S_0x1117100; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x1116830 .param/str "memFile" 0 3 60, "left.dat"; +L_0x1163fb0 .functor BUFZ 11, v0x113d270_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x11740a0 .functor BUFZ 11, v0x113d270_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x1174e40 .functor BUFZ 18, L_0x1176e00, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x113d270_0 .var/s "ACC", 10 0; +v0x1159c00_0 .var/s "BAK", 10 0; +v0x1159ce0_0 .net "DST", 2 0, L_0x1177f40; 1 drivers +v0x1159dd0_0 .net/s "IMM", 10 0, L_0x1177fe0; 1 drivers +v0x1159eb0_0 .net "INST", 3 0, L_0x1177820; 1 drivers +v0x1159fe0_0 .net "LABEL", 3 0, L_0x1178190; 1 drivers +v0x115a0c0_0 .var "PC", 3 0; +v0x115a1a0_0 .var "PCNEXT", 3 0; +v0x115a280_0 .net "SRC", 2 0, L_0x1177d50; 1 drivers +v0x115a3f0_0 .net *"_s103", 0 0, L_0x1176140; 1 drivers +v0x115a4d0_0 .net *"_s107", 0 0, L_0x1176050; 1 drivers +v0x115a5b0_0 .net *"_s111", 0 0, L_0x1176330; 1 drivers +v0x115a690_0 .net *"_s115", 0 0, L_0x1176230; 1 drivers +v0x115a770_0 .net *"_s119", 0 0, L_0x1176570; 1 drivers +v0x115a850_0 .net *"_s123", 0 0, L_0x1176460; 1 drivers +v0x115a930_0 .net *"_s127", 0 0, L_0x1176730; 1 drivers +v0x115aa10_0 .net *"_s131", 0 0, L_0x1176610; 1 drivers +v0x115abc0_0 .net *"_s135", 0 0, L_0x1176990; 1 drivers +v0x115ac60_0 .net *"_s139", 0 0, L_0x1176860; 1 drivers +v0x115ad40_0 .net *"_s143", 0 0, L_0x1176b70; 1 drivers +v0x115ae20_0 .net *"_s147", 0 0, L_0x1176a30; 1 drivers +v0x115af00_0 .net *"_s151", 0 0, L_0x1176d60; 1 drivers +v0x115afe0_0 .net *"_s155", 0 0, L_0x1176c10; 1 drivers +v0x115b0c0_0 .net *"_s159", 0 0, L_0x1176cb0; 1 drivers +v0x115b1a0_0 .net *"_s160", 17 0, L_0x1176e00; 1 drivers +v0x115b280_0 .net *"_s162", 5 0, L_0x1177160; 1 drivers +L_0x2b8432d3a060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x115b360_0 .net *"_s165", 1 0, L_0x2b8432d3a060; 1 drivers +v0x115d330_2 .array/port v0x115d330, 2; +v0x115b440_0 .net *"_s173", 10 0, v0x115d330_2; 1 drivers +v0x115d330_3 .array/port v0x115d330, 3; +v0x115b520_0 .net *"_s179", 10 0, v0x115d330_3; 1 drivers +v0x115d330_0 .array/port v0x115d330, 0; +v0x115b600_0 .net *"_s185", 10 0, v0x115d330_0; 1 drivers +v0x115d330_1 .array/port v0x115d330, 1; +v0x115b6e0_0 .net *"_s191", 10 0, v0x115d330_1; 1 drivers +v0x115b7c0_0 .net *"_s23", 0 0, L_0x1174530; 1 drivers +v0x115b8a0_0 .net *"_s27", 0 0, L_0x1174650; 1 drivers +v0x115aaf0_0 .net *"_s31", 0 0, L_0x11747c0; 1 drivers +v0x115bb70_0 .net *"_s36", 0 0, L_0x1174a70; 1 drivers +v0x115bc50_0 .net *"_s42", 0 0, L_0x1174d00; 1 drivers +v0x115bd30_0 .net *"_s46", 0 0, L_0x1174da0; 1 drivers +v0x115be10_0 .net *"_s50", 0 0, L_0x1174eb0; 1 drivers +v0x115bef0_0 .net *"_s55", 0 0, L_0x1175110; 1 drivers +v0x115bfd0_0 .net *"_s61", 0 0, L_0x1175380; 1 drivers +v0x115c0b0_0 .net *"_s65", 0 0, L_0x11754b0; 1 drivers +v0x115c190_0 .net *"_s69", 0 0, L_0x11755f0; 1 drivers +v0x115c270_0 .net *"_s74", 0 0, L_0x1175550; 1 drivers +v0x115c350_0 .net *"_s80", 0 0, L_0x11757e0; 1 drivers +v0x115c430_0 .net *"_s84", 0 0, L_0x1175ad0; 1 drivers +v0x115c510_0 .net *"_s88", 0 0, L_0x1175a10; 1 drivers +v0x115c5f0_0 .net *"_s93", 0 0, L_0x1175b70; 1 drivers +v0x115c6d0_0 .net *"_s99", 0 0, L_0x1175e30; 1 drivers +v0x115c7b0_0 .net/s "accOut", 10 0, L_0x1163fb0; alias, 1 drivers +v0x115c890_0 .net "anyHasData", 0 0, L_0x1174bb0; 1 drivers +v0x115c950_0 .net "anyReadAck", 0 0, L_0x1175970; 1 drivers +v0x115ca10_0 .net "anyWantData", 0 0, L_0x1175200; 1 drivers +v0x115cad0_0 .net "anyWriteAck", 0 0, L_0x1175f60; 1 drivers +v0x115cb90_0 .net "clk", 0 0, v0x1163db0_0; 1 drivers +o0x2b8432d09a38 .functor BUFZ 15, C4; HiZ drive +v0x115cc50_0 .net "down", 14 0, o0x2b8432d09a38; 0 drivers +v0x115cd30_0 .net "downOut", 14 0, L_0x1177580; 1 drivers +v0x115ce10_0 .net "instruction", 17 0, L_0x1174e40; 1 drivers +v0x115cef0 .array "instructions", 0 15, 17 0; +v0x115cfb0_0 .var "last", 2 0; +o0x2b8432d09af8 .functor BUFZ 15, C4; HiZ drive +v0x115d090_0 .net "left", 14 0, o0x2b8432d09af8; 0 drivers +v0x115d170_0 .net "leftOut", 14 0, L_0x11772c0; 1 drivers +v0x115d250_0 .var "mode", 2 0; +v0x115d330 .array/s "outVals", 2 5, 10 0; +v0x115d470_0 .var "phase", 2 0; +v0x115d550_0 .net "portsHaveData", 5 2, L_0x1174860; 1 drivers +v0x115b940_0 .net "portsWantData", 5 2, L_0x1174f50; 1 drivers +v0x115ba20_0 .net "readAckIn", 5 2, L_0x1175690; 1 drivers +v0x115da00_0 .var "readAckOut", 5 2; +v0x115daa0_0 .var "readTarget", 2 0; +v0x115db80_0 .var/s "readValue", 10 0; +L_0x2b8432d3a018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x115dc60 .array "regVals", 0 7; +v0x115dc60_0 .net/s v0x115dc60 0, 10 0, L_0x2b8432d3a018; 1 drivers +v0x115dc60_1 .net/s v0x115dc60 1, 10 0, L_0x11740a0; 1 drivers +v0x115dc60_2 .net/s v0x115dc60 2, 10 0, L_0x1174160; 1 drivers +v0x115dc60_3 .net/s v0x115dc60 3, 10 0, L_0x1174230; 1 drivers +v0x115dc60_4 .net/s v0x115dc60 4, 10 0, L_0x1174300; 1 drivers +v0x115dc60_5 .net/s v0x115dc60 5, 10 0, L_0x1174400; 1 drivers +o0x2b8432d09eb8 .functor BUFZ 11, C4; HiZ drive +v0x115dc60_6 .net/s v0x115dc60 6, 10 0, o0x2b8432d09eb8; 0 drivers +o0x2b8432d09ee8 .functor BUFZ 11, C4; HiZ drive +v0x115dc60_7 .net/s v0x115dc60 7, 10 0, o0x2b8432d09ee8; 0 drivers +v0x115de70_0 .net "right", 14 0, L_0x117b450; alias, 1 drivers +v0x115df50_0 .net "rightOut", 14 0, L_0x1177b30; alias, 1 drivers +o0x2b8432d09f78 .functor BUFZ 15, C4; HiZ drive +v0x115e030_0 .net "up", 14 0, o0x2b8432d09f78; 0 drivers +v0x115e110_0 .net "upOut", 14 0, L_0x1177070; 1 drivers +v0x115e1f0_0 .var "weHaveData", 5 2; +v0x115e2d0_0 .var "weWantData", 5 2; +v0x115e3b0_0 .net "writeAckIn", 5 2, L_0x1175c40; 1 drivers +v0x115e490_0 .var "writeAckOut", 5 2; +v0x115e570_0 .var "writeTarget", 2 0; +v0x115e650_0 .var/s "writeValue", 10 0; +E_0x1122a60 .event negedge, v0x115cb90_0; +E_0x1100460 .event posedge, v0x115cb90_0; +L_0x1174160 .part o0x2b8432d09af8, 0, 11; +L_0x1174230 .part L_0x117b450, 0, 11; +L_0x1174300 .part o0x2b8432d09f78, 0, 11; +L_0x1174400 .part o0x2b8432d09a38, 0, 11; +L_0x1174530 .part o0x2b8432d09af8, 11, 1; +L_0x1174650 .part L_0x117b450, 11, 1; +L_0x11747c0 .part o0x2b8432d09f78, 11, 1; +L_0x1174860 .concat8 [ 1 1 1 1], L_0x1174530, L_0x1174650, L_0x11747c0, L_0x1174a70; +L_0x1174a70 .part o0x2b8432d09a38, 11, 1; +L_0x1174bb0 .reduce/or L_0x1174860; +L_0x1174d00 .part o0x2b8432d09af8, 12, 1; +L_0x1174da0 .part L_0x117b450, 12, 1; +L_0x1174eb0 .part o0x2b8432d09f78, 12, 1; +L_0x1174f50 .concat8 [ 1 1 1 1], L_0x1174d00, L_0x1174da0, L_0x1174eb0, L_0x1175110; +L_0x1175110 .part o0x2b8432d09a38, 12, 1; +L_0x1175200 .reduce/or L_0x1174f50; +L_0x1175380 .part o0x2b8432d09af8, 13, 1; +L_0x11754b0 .part L_0x117b450, 13, 1; +L_0x11755f0 .part o0x2b8432d09f78, 13, 1; +L_0x1175690 .concat8 [ 1 1 1 1], L_0x1175380, L_0x11754b0, L_0x11755f0, L_0x1175550; +L_0x1175550 .part o0x2b8432d09a38, 13, 1; +L_0x1175970 .reduce/or L_0x1175690; +L_0x11757e0 .part o0x2b8432d09af8, 14, 1; +L_0x1175ad0 .part L_0x117b450, 14, 1; +L_0x1175a10 .part o0x2b8432d09f78, 14, 1; +L_0x1175c40 .concat8 [ 1 1 1 1], L_0x11757e0, L_0x1175ad0, L_0x1175a10, L_0x1175b70; +L_0x1175b70 .part o0x2b8432d09a38, 14, 1; +L_0x1175f60 .reduce/or L_0x1175c40; +L_0x1175e30 .part v0x115da00_0, 0, 1; +L_0x1176140 .part v0x115da00_0, 1, 1; +L_0x1176050 .part v0x115da00_0, 2, 1; +L_0x1176330 .part v0x115da00_0, 3, 1; +L_0x1176230 .part v0x115e490_0, 0, 1; +L_0x1176570 .part v0x115e490_0, 1, 1; +L_0x1176460 .part v0x115e490_0, 2, 1; +L_0x1176730 .part v0x115e490_0, 3, 1; +L_0x1176610 .part v0x115e2d0_0, 0, 1; +L_0x1176990 .part v0x115e2d0_0, 1, 1; +L_0x1176860 .part v0x115e2d0_0, 2, 1; +L_0x1176b70 .part v0x115e2d0_0, 3, 1; +L_0x1176a30 .part v0x115e1f0_0, 0, 1; +L_0x1176d60 .part v0x115e1f0_0, 1, 1; +L_0x1176c10 .part v0x115e1f0_0, 2, 1; +L_0x1176cb0 .part v0x115e1f0_0, 3, 1; +L_0x1176e00 .array/port v0x115cef0, L_0x1177160; +L_0x1177160 .concat [ 4 2 0 0], v0x115a0c0_0, L_0x2b8432d3a060; +LS_0x1177070_0_0 .concat8 [ 11 1 1 1], v0x115d330_2, L_0x1176c10, L_0x1176860, L_0x1176460; +LS_0x1177070_0_4 .concat8 [ 1 0 0 0], L_0x1176050; +L_0x1177070 .concat8 [ 14 1 0 0], LS_0x1177070_0_0, LS_0x1177070_0_4; +LS_0x1177580_0_0 .concat8 [ 11 1 1 1], v0x115d330_3, L_0x1176cb0, L_0x1176b70, L_0x1176730; +LS_0x1177580_0_4 .concat8 [ 1 0 0 0], L_0x1176330; +L_0x1177580 .concat8 [ 14 1 0 0], LS_0x1177580_0_0, LS_0x1177580_0_4; +LS_0x11772c0_0_0 .concat8 [ 11 1 1 1], v0x115d330_0, L_0x1176a30, L_0x1176610, L_0x1176230; +LS_0x11772c0_0_4 .concat8 [ 1 0 0 0], L_0x1175e30; +L_0x11772c0 .concat8 [ 14 1 0 0], LS_0x11772c0_0_0, LS_0x11772c0_0_4; +LS_0x1177b30_0_0 .concat8 [ 11 1 1 1], v0x115d330_1, L_0x1176d60, L_0x1176990, L_0x1176570; +LS_0x1177b30_0_4 .concat8 [ 1 0 0 0], L_0x1176140; +L_0x1177b30 .concat8 [ 14 1 0 0], LS_0x1177b30_0_0, LS_0x1177b30_0_4; +L_0x1177820 .part L_0x1174e40, 14, 4; +L_0x1177f40 .part L_0x1174e40, 11, 3; +L_0x1177d50 .part L_0x1174e40, 8, 3; +L_0x1178190 .part L_0x1174e40, 10, 4; +L_0x1177fe0 .part L_0x1174e40, 0, 11; +S_0x115e8d0 .scope module, "right" "tis100" 2 13, 3 49 0, S_0x1117100; + .timescale 0 0; + .port_info 0 /INPUT 1 "clk" + .port_info 1 /INPUT 15 "up" + .port_info 2 /INPUT 15 "down" + .port_info 3 /INPUT 15 "left" + .port_info 4 /INPUT 15 "right" + .port_info 5 /OUTPUT 15 "upOut" + .port_info 6 /OUTPUT 15 "downOut" + .port_info 7 /OUTPUT 15 "leftOut" + .port_info 8 /OUTPUT 15 "rightOut" + .port_info 9 /OUTPUT 11 "accOut" +P_0x115eac0 .param/str "memFile" 0 3 60, "right.dat"; +L_0x1177e80 .functor BUFZ 11, v0x115ed00_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x1178080 .functor BUFZ 11, v0x115ed00_0, C4<00000000000>, C4<00000000000>, C4<00000000000>; +L_0x1178f70 .functor BUFZ 18, L_0x117af90, C4<000000000000000000>, C4<000000000000000000>, C4<000000000000000000>; +v0x115ed00_0 .var/s "ACC", 10 0; +v0x115ee00_0 .var/s "BAK", 10 0; +v0x115eee0_0 .net "DST", 2 0, L_0x117c140; 1 drivers +v0x115efa0_0 .net/s "IMM", 10 0, L_0x117c1e0; 1 drivers +v0x115f080_0 .net "INST", 3 0, L_0x117b9a0; 1 drivers +v0x115f1b0_0 .net "LABEL", 3 0, L_0x117c390; 1 drivers +v0x115f290_0 .var "PC", 3 0; +v0x115f370_0 .var "PCNEXT", 3 0; +v0x115f450_0 .net "SRC", 2 0, L_0x117bf50; 1 drivers +v0x115f5c0_0 .net *"_s103", 0 0, L_0x117a2d0; 1 drivers +v0x115f6a0_0 .net *"_s107", 0 0, L_0x117a1e0; 1 drivers +v0x115f780_0 .net *"_s111", 0 0, L_0x117a4c0; 1 drivers +v0x115f860_0 .net *"_s115", 0 0, L_0x117a3c0; 1 drivers +v0x115f940_0 .net *"_s119", 0 0, L_0x117a700; 1 drivers +v0x115fa20_0 .net *"_s123", 0 0, L_0x117a5f0; 1 drivers +v0x115fb00_0 .net *"_s127", 0 0, L_0x117a8c0; 1 drivers +v0x115fbe0_0 .net *"_s131", 0 0, L_0x117a7a0; 1 drivers +v0x115fd90_0 .net *"_s135", 0 0, L_0x117ab20; 1 drivers +v0x115fe30_0 .net *"_s139", 0 0, L_0x117a9f0; 1 drivers +v0x115ff10_0 .net *"_s143", 0 0, L_0x117ad00; 1 drivers +v0x115fff0_0 .net *"_s147", 0 0, L_0x117abc0; 1 drivers +v0x11600d0_0 .net *"_s151", 0 0, L_0x117aef0; 1 drivers +v0x11601b0_0 .net *"_s155", 0 0, L_0x117ada0; 1 drivers +v0x1160290_0 .net *"_s159", 0 0, L_0x117ae40; 1 drivers +v0x1160370_0 .net *"_s160", 17 0, L_0x117af90; 1 drivers +v0x1160450_0 .net *"_s162", 5 0, L_0x117b2f0; 1 drivers +L_0x2b8432d3a0f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x1160530_0 .net *"_s165", 1 0, L_0x2b8432d3a0f0; 1 drivers +v0x1162470_2 .array/port v0x1162470, 2; +v0x1160610_0 .net *"_s173", 10 0, v0x1162470_2; 1 drivers +v0x1162470_3 .array/port v0x1162470, 3; +v0x11606f0_0 .net *"_s179", 10 0, v0x1162470_3; 1 drivers +v0x1162470_0 .array/port v0x1162470, 0; +v0x11607d0_0 .net *"_s185", 10 0, v0x1162470_0; 1 drivers +v0x1162470_1 .array/port v0x1162470, 1; +v0x11608b0_0 .net *"_s191", 10 0, v0x1162470_1; 1 drivers +v0x1160990_0 .net *"_s23", 0 0, L_0x1178790; 1 drivers +v0x1160a70_0 .net *"_s27", 0 0, L_0x1178860; 1 drivers +v0x115fcc0_0 .net *"_s31", 0 0, L_0x1178930; 1 drivers +v0x1160d40_0 .net *"_s36", 0 0, L_0x1178c00; 1 drivers +v0x1160e20_0 .net *"_s42", 0 0, L_0x1178e30; 1 drivers +v0x1160f00_0 .net *"_s46", 0 0, L_0x1178ed0; 1 drivers +v0x1160fe0_0 .net *"_s50", 0 0, L_0x1178fe0; 1 drivers +v0x11610c0_0 .net *"_s55", 0 0, L_0x11791f0; 1 drivers +v0x11611a0_0 .net *"_s61", 0 0, L_0x1179460; 1 drivers +v0x1161280_0 .net *"_s65", 0 0, L_0x1179500; 1 drivers +v0x1161360_0 .net *"_s69", 0 0, L_0x11796d0; 1 drivers +v0x1161440_0 .net *"_s74", 0 0, L_0x1179630; 1 drivers +v0x1161520_0 .net *"_s80", 0 0, L_0x11798c0; 1 drivers +v0x1161600_0 .net *"_s84", 0 0, L_0x1179cc0; 1 drivers +v0x11616e0_0 .net *"_s88", 0 0, L_0x1179af0; 1 drivers +v0x11617c0_0 .net *"_s93", 0 0, L_0x1179d60; 1 drivers +v0x11618a0_0 .net *"_s99", 0 0, L_0x1179fc0; 1 drivers +v0x1161980_0 .net/s "accOut", 10 0, L_0x1177e80; alias, 1 drivers +v0x1161a60_0 .net "anyHasData", 0 0, L_0x1178d40; 1 drivers +v0x1161b20_0 .net "anyReadAck", 0 0, L_0x1179a50; 1 drivers +v0x1161be0_0 .net "anyWantData", 0 0, L_0x11792e0; 1 drivers +v0x1161ca0_0 .net "anyWriteAck", 0 0, L_0x117a0f0; 1 drivers +v0x1161d60_0 .net "clk", 0 0, v0x1163db0_0; alias, 1 drivers +o0x2b8432d0acc8 .functor BUFZ 15, C4; HiZ drive +v0x1161e00_0 .net "down", 14 0, o0x2b8432d0acc8; 0 drivers +v0x1161ec0_0 .net "downOut", 14 0, L_0x117b6c0; 1 drivers +v0x1161fa0_0 .net "instruction", 17 0, L_0x1178f70; 1 drivers +v0x1162080 .array "instructions", 0 15, 17 0; +v0x1162140_0 .var "last", 2 0; +v0x1162220_0 .net "left", 14 0, L_0x1177b30; alias, 1 drivers +v0x11622e0_0 .net "leftOut", 14 0, L_0x117b450; alias, 1 drivers +v0x11623b0_0 .var "mode", 2 0; +v0x1162470 .array/s "outVals", 2 5, 10 0; +v0x11625e0_0 .var "phase", 2 0; +v0x11626c0_0 .net "portsHaveData", 5 2, L_0x1178a20; 1 drivers +v0x1160b10_0 .net "portsWantData", 5 2, L_0x1179080; 1 drivers +v0x1160bf0_0 .net "readAckIn", 5 2, L_0x1179770; 1 drivers +v0x1162b70_0 .var "readAckOut", 5 2; +v0x1162c10_0 .var "readTarget", 2 0; +v0x1162cb0_0 .var/s "readValue", 10 0; +L_0x2b8432d3a0a8 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x1162d90 .array "regVals", 0 7; +v0x1162d90_0 .net/s v0x1162d90 0, 10 0, L_0x2b8432d3a0a8; 1 drivers +v0x1162d90_1 .net/s v0x1162d90 1, 10 0, L_0x1178080; 1 drivers +v0x1162d90_2 .net/s v0x1162d90 2, 10 0, L_0x11783f0; 1 drivers +v0x1162d90_3 .net/s v0x1162d90 3, 10 0, L_0x1178520; 1 drivers +v0x1162d90_4 .net/s v0x1162d90 4, 10 0, L_0x11785c0; 1 drivers +v0x1162d90_5 .net/s v0x1162d90 5, 10 0, L_0x1178660; 1 drivers +o0x2b8432d0b0e8 .functor BUFZ 11, C4; HiZ drive +v0x1162d90_6 .net/s v0x1162d90 6, 10 0, o0x2b8432d0b0e8; 0 drivers +o0x2b8432d0b118 .functor BUFZ 11, C4; HiZ drive +v0x1162d90_7 .net/s v0x1162d90 7, 10 0, o0x2b8432d0b118; 0 drivers +o0x2b8432d0b148 .functor BUFZ 15, C4; HiZ drive +v0x1162fa0_0 .net "right", 14 0, o0x2b8432d0b148; 0 drivers +v0x1163080_0 .net "rightOut", 14 0, L_0x117bd30; 1 drivers +o0x2b8432d0b1a8 .functor BUFZ 15, C4; HiZ drive +v0x1163160_0 .net "up", 14 0, o0x2b8432d0b1a8; 0 drivers +v0x1163240_0 .net "upOut", 14 0, L_0x117b1d0; 1 drivers +v0x1163320_0 .var "weHaveData", 5 2; +v0x1163400_0 .var "weWantData", 5 2; +v0x11634e0_0 .net "writeAckIn", 5 2, L_0x1179e30; 1 drivers +v0x11635c0_0 .var "writeAckOut", 5 2; +v0x11636a0_0 .var "writeTarget", 2 0; +v0x1163780_0 .var/s "writeValue", 10 0; +L_0x11783f0 .part L_0x1177b30, 0, 11; +L_0x1178520 .part o0x2b8432d0b148, 0, 11; +L_0x11785c0 .part o0x2b8432d0b1a8, 0, 11; +L_0x1178660 .part o0x2b8432d0acc8, 0, 11; +L_0x1178790 .part L_0x1177b30, 11, 1; +L_0x1178860 .part o0x2b8432d0b148, 11, 1; +L_0x1178930 .part o0x2b8432d0b1a8, 11, 1; +L_0x1178a20 .concat8 [ 1 1 1 1], L_0x1178790, L_0x1178860, L_0x1178930, L_0x1178c00; +L_0x1178c00 .part o0x2b8432d0acc8, 11, 1; +L_0x1178d40 .reduce/or L_0x1178a20; +L_0x1178e30 .part L_0x1177b30, 12, 1; +L_0x1178ed0 .part o0x2b8432d0b148, 12, 1; +L_0x1178fe0 .part o0x2b8432d0b1a8, 12, 1; +L_0x1179080 .concat8 [ 1 1 1 1], L_0x1178e30, L_0x1178ed0, L_0x1178fe0, L_0x11791f0; +L_0x11791f0 .part o0x2b8432d0acc8, 12, 1; +L_0x11792e0 .reduce/or L_0x1179080; +L_0x1179460 .part L_0x1177b30, 13, 1; +L_0x1179500 .part o0x2b8432d0b148, 13, 1; +L_0x11796d0 .part o0x2b8432d0b1a8, 13, 1; +L_0x1179770 .concat8 [ 1 1 1 1], L_0x1179460, L_0x1179500, L_0x11796d0, L_0x1179630; +L_0x1179630 .part o0x2b8432d0acc8, 13, 1; +L_0x1179a50 .reduce/or L_0x1179770; +L_0x11798c0 .part L_0x1177b30, 14, 1; +L_0x1179cc0 .part o0x2b8432d0b148, 14, 1; +L_0x1179af0 .part o0x2b8432d0b1a8, 14, 1; +L_0x1179e30 .concat8 [ 1 1 1 1], L_0x11798c0, L_0x1179cc0, L_0x1179af0, L_0x1179d60; +L_0x1179d60 .part o0x2b8432d0acc8, 14, 1; +L_0x117a0f0 .reduce/or L_0x1179e30; +L_0x1179fc0 .part v0x1162b70_0, 0, 1; +L_0x117a2d0 .part v0x1162b70_0, 1, 1; +L_0x117a1e0 .part v0x1162b70_0, 2, 1; +L_0x117a4c0 .part v0x1162b70_0, 3, 1; +L_0x117a3c0 .part v0x11635c0_0, 0, 1; +L_0x117a700 .part v0x11635c0_0, 1, 1; +L_0x117a5f0 .part v0x11635c0_0, 2, 1; +L_0x117a8c0 .part v0x11635c0_0, 3, 1; +L_0x117a7a0 .part v0x1163400_0, 0, 1; +L_0x117ab20 .part v0x1163400_0, 1, 1; +L_0x117a9f0 .part v0x1163400_0, 2, 1; +L_0x117ad00 .part v0x1163400_0, 3, 1; +L_0x117abc0 .part v0x1163320_0, 0, 1; +L_0x117aef0 .part v0x1163320_0, 1, 1; +L_0x117ada0 .part v0x1163320_0, 2, 1; +L_0x117ae40 .part v0x1163320_0, 3, 1; +L_0x117af90 .array/port v0x1162080, L_0x117b2f0; +L_0x117b2f0 .concat [ 4 2 0 0], v0x115f290_0, L_0x2b8432d3a0f0; +LS_0x117b1d0_0_0 .concat8 [ 11 1 1 1], v0x1162470_2, L_0x117ada0, L_0x117a9f0, L_0x117a5f0; +LS_0x117b1d0_0_4 .concat8 [ 1 0 0 0], L_0x117a1e0; +L_0x117b1d0 .concat8 [ 14 1 0 0], LS_0x117b1d0_0_0, LS_0x117b1d0_0_4; +LS_0x117b6c0_0_0 .concat8 [ 11 1 1 1], v0x1162470_3, L_0x117ae40, L_0x117ad00, L_0x117a8c0; +LS_0x117b6c0_0_4 .concat8 [ 1 0 0 0], L_0x117a4c0; +L_0x117b6c0 .concat8 [ 14 1 0 0], LS_0x117b6c0_0_0, LS_0x117b6c0_0_4; +LS_0x117b450_0_0 .concat8 [ 11 1 1 1], v0x1162470_0, L_0x117abc0, L_0x117a7a0, L_0x117a3c0; +LS_0x117b450_0_4 .concat8 [ 1 0 0 0], L_0x1179fc0; +L_0x117b450 .concat8 [ 14 1 0 0], LS_0x117b450_0_0, LS_0x117b450_0_4; +LS_0x117bd30_0_0 .concat8 [ 11 1 1 1], v0x1162470_1, L_0x117aef0, L_0x117ab20, L_0x117a700; +LS_0x117bd30_0_4 .concat8 [ 1 0 0 0], L_0x117a2d0; +L_0x117bd30 .concat8 [ 14 1 0 0], LS_0x117bd30_0_0, LS_0x117bd30_0_4; +L_0x117b9a0 .part L_0x1178f70, 14, 4; +L_0x117c140 .part L_0x1178f70, 11, 3; +L_0x117bf50 .part L_0x1178f70, 8, 3; +L_0x117c390 .part L_0x1178f70, 10, 4; +L_0x117c1e0 .part L_0x1178f70, 0, 11; + .scope S_0x10b3c70; +T_0 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x115d250_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x115d470_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x115cfb0_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x113d270_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x1159c00_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115a0c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115da00_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115e2d0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115e490_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115e1f0_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x115d330, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x115d330, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x115d330, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x115d330, 4, 0; + %vpi_call 3 185 "$readmemb", P_0x1116830, v0x115cef0 {0 0 0}; + %end; + .thread T_0; + .scope S_0x10b3c70; +T_1 ; + %wait E_0x1100460; + %load/vec4 v0x115d250_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.2, 6; + %jmp T_1.3; +T_1.0 ; + %load/vec4 v0x115d470_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.6, 6; + %jmp T_1.7; +T_1.4 ; + %load/vec4 v0x1159eb0_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_1.8, 5; + %load/vec4 v0x115a280_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_1.10, 5; + %load/vec4 v0x115a280_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %jmp T_1.11; +T_1.10 ; + %load/vec4 v0x115a280_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_1.12, 5; + %load/vec4 v0x115d550_0; + %load/vec4 v0x115a280_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.14, 8; + %load/vec4 v0x115a280_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115a280_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %load/vec4 v0x115a280_0; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.15; +T_1.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x115d250_0, 0; + %load/vec4 v0x115a280_0; + %assign/vec4 v0x115daa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115a280_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; +T_1.15 ; + %jmp T_1.13; +T_1.12 ; + %load/vec4 v0x115a280_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.16, 4; + %load/vec4 v0x115cfb0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_1.18, 4; + %load/vec4 v0x115cfb0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %jmp T_1.19; +T_1.18 ; + %load/vec4 v0x115d550_0; + %load/vec4 v0x115cfb0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.20, 8; + %load/vec4 v0x115cfb0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115cfb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %jmp T_1.21; +T_1.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x115d250_0, 0; + %load/vec4 v0x115cfb0_0; + %assign/vec4 v0x115daa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115cfb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; +T_1.21 ; +T_1.19 ; + %jmp T_1.17; +T_1.16 ; + %load/vec4 v0x115a280_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.22, 4; + %load/vec4 v0x115c890_0; + %flag_set/vec4 8; + %jmp/0xz T_1.24, 8; + %load/vec4 v0x115d550_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.27; +T_1.26 ; + %load/vec4 v0x115d550_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.29; +T_1.28 ; + %load/vec4 v0x115d550_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.31; +T_1.30 ; + %load/vec4 v0x115d550_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; +T_1.32 ; +T_1.31 ; +T_1.29 ; +T_1.27 ; + %jmp T_1.25; +T_1.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x115d250_0, 0; + %load/vec4 v0x115a280_0; + %assign/vec4 v0x115daa0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; +T_1.25 ; +T_1.22 ; +T_1.17 ; +T_1.13 ; +T_1.11 ; +T_1.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.7; +T_1.5 ; + %load/vec4 v0x1159eb0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_1.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_1.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_1.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_1.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_1.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_1.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_1.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_1.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_1.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_1.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_1.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_1.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_1.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_1.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_1.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_1.49, 6; + %jmp T_1.50; +T_1.34 ; + %load/vec4 v0x113d270_0; + %load/vec4 v0x115db80_0; + %add; + %assign/vec4 v0x113d270_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.35 ; + %load/vec4 v0x113d270_0; + %load/vec4 v0x115db80_0; + %sub; + %assign/vec4 v0x113d270_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.36 ; + %load/vec4 v0x115a0c0_0; + %pad/u 11; + %load/vec4 v0x115db80_0; + %add; + %pad/u 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.37 ; + %load/vec4 v0x115db80_0; + %assign/vec4 v0x115e650_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.38 ; + %vpi_call 3 278 "$display", "here" {0 0 0}; + %load/vec4 v0x1159dd0_0; + %assign/vec4 v0x115e650_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.39 ; + %load/vec4 v0x113d270_0; + %load/vec4 v0x1159dd0_0; + %add; + %assign/vec4 v0x113d270_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.40 ; + %load/vec4 v0x113d270_0; + %load/vec4 v0x1159dd0_0; + %sub; + %assign/vec4 v0x113d270_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.41 ; + %load/vec4 v0x115a0c0_0; + %pad/u 11; + %load/vec4 v0x1159dd0_0; + %add; + %pad/u 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.42 ; + %load/vec4 v0x1159c00_0; + %assign/vec4 v0x113d270_0, 0; + %load/vec4 v0x113d270_0; + %assign/vec4 v0x1159c00_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.43 ; + %load/vec4 v0x113d270_0; + %assign/vec4 v0x1159c00_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.44 ; + %load/vec4 v0x113d270_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x113d270_0, 0; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.45 ; + %load/vec4 v0x1159fe0_0; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.50; +T_1.46 ; + %load/vec4 v0x113d270_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_1.51, 4; + %load/vec4 v0x1159fe0_0; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.52; +T_1.51 ; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; +T_1.52 ; + %jmp T_1.50; +T_1.47 ; + %load/vec4 v0x113d270_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.53, 4; + %load/vec4 v0x1159fe0_0; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.54; +T_1.53 ; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; +T_1.54 ; + %jmp T_1.50; +T_1.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x113d270_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_1.55, 5; + %load/vec4 v0x1159fe0_0; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.56; +T_1.55 ; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; +T_1.56 ; + %jmp T_1.50; +T_1.49 ; + %load/vec4 v0x113d270_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_1.57, 5; + %load/vec4 v0x1159fe0_0; + %assign/vec4 v0x115a1a0_0, 0; + %jmp T_1.58; +T_1.57 ; + %load/vec4 v0x115a0c0_0; + %addi 1, 0, 4; + %assign/vec4 v0x115a1a0_0, 0; +T_1.58 ; + %jmp T_1.50; +T_1.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.7; +T_1.6 ; + %load/vec4 v0x1159eb0_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x1159eb0_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_1.59, 4; + %load/vec4 v0x1159ce0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x1159ce0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x115cfb0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_1.61, 9; + %load/vec4 v0x1159ce0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_1.63, 4; + %load/vec4 v0x115e650_0; + %assign/vec4 v0x113d270_0, 0; +T_1.63 ; + %jmp T_1.62; +T_1.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115d250_0, 0; + %load/vec4 v0x1159ce0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_1.65, 4; + %load/vec4 v0x115cfb0_0; + %assign/vec4 v0x115e570_0, 0; + %load/vec4 v0x115e650_0; + %load/vec4 v0x115cfb0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115cfb0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %jmp T_1.66; +T_1.65 ; + %load/vec4 v0x1159ce0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.67, 4; + %load/vec4 v0x1159ce0_0; + %assign/vec4 v0x115e570_0, 0; + %load/vec4 v0x115e650_0; + %load/vec4 v0x1159ce0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x1159ce0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x1159ce0_0; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.68; +T_1.67 ; + %load/vec4 v0x115ca10_0; + %flag_set/vec4 8; + %jmp/0xz T_1.69, 8; + %load/vec4 v0x115b940_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.72; +T_1.71 ; + %load/vec4 v0x115b940_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.74; +T_1.73 ; + %load/vec4 v0x115b940_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.76; +T_1.75 ; + %load/vec4 v0x115b940_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; +T_1.77 ; +T_1.76 ; +T_1.74 ; +T_1.72 ; + %jmp T_1.70; +T_1.69 ; + %load/vec4 v0x1159ce0_0; + %assign/vec4 v0x115e570_0, 0; +T_1.70 ; +T_1.68 ; +T_1.66 ; +T_1.62 ; +T_1.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.7; +T_1.7 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.1 ; + %load/vec4 v0x115d470_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.81, 6; + %jmp T_1.82; +T_1.79 ; + %load/vec4 v0x115daa0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.83, 4; + %load/vec4 v0x115c890_0; + %flag_set/vec4 8; + %jmp/0xz T_1.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x115d250_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115e2d0_0, 0, 4; + %load/vec4 v0x115d550_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.88; +T_1.87 ; + %load/vec4 v0x115d550_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.90; +T_1.89 ; + %load/vec4 v0x115d550_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.92; +T_1.91 ; + %load/vec4 v0x115d550_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; +T_1.93 ; +T_1.92 ; +T_1.90 ; +T_1.88 ; +T_1.85 ; + %jmp T_1.84; +T_1.83 ; + %load/vec4 v0x115d550_0; + %load/vec4 v0x115daa0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x115d250_0, 0; + %load/vec4 v0x115daa0_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x115dc60, 4; + %assign/vec4 v0x115db80_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115daa0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115da00_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115daa0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x115e2d0_0, 4, 5; + %load/vec4 v0x115daa0_0; + %assign/vec4 v0x115cfb0_0, 0; +T_1.95 ; +T_1.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.82; +T_1.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.82; +T_1.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.82; +T_1.82 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0x115d470_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_1.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_1.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_1.99, 6; + %jmp T_1.100; +T_1.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.100; +T_1.98 ; + %load/vec4 v0x115e570_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_1.101, 4; + %load/vec4 v0x115ca10_0; + %flag_set/vec4 8; + %jmp/0xz T_1.103, 8; + %load/vec4 v0x115b940_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.106; +T_1.105 ; + %load/vec4 v0x115b940_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.108; +T_1.107 ; + %load/vec4 v0x115b940_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_1.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; + %jmp T_1.110; +T_1.109 ; + %load/vec4 v0x115b940_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_1.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x115e570_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x115e1f0_0, 4, 5; + %load/vec4 v0x115e650_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x115d330, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x115cfb0_0, 0; +T_1.111 ; +T_1.110 ; +T_1.108 ; +T_1.106 ; +T_1.103 ; +T_1.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.100; +T_1.99 ; + %load/vec4 v0x115e570_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_1.113, 4; + %load/vec4 v0x115e3b0_0; + %load/vec4 v0x115e570_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_1.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x115e570_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x115e1f0_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x115d250_0, 0; +T_1.115 ; +T_1.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x115d470_0, 0; + %jmp T_1.100; +T_1.100 ; + %pop/vec4 1; + %jmp T_1.3; +T_1.3 ; + %pop/vec4 1; + %jmp T_1; + .thread T_1; + .scope S_0x10b3c70; +T_2 ; + %wait E_0x1122a60; + %load/vec4 v0x115d470_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x115d250_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x115a1a0_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %load/vec4 v0x115a1a0_0; + %assign/vec4 v0x115a0c0_0, 0; +T_2.0 ; + %load/vec4 v0x115d470_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_2.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115da00_0, 0, 4; +T_2.2 ; + %jmp T_2; + .thread T_2; + .scope S_0x115e8d0; +T_3 ; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x11623b0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x11625e0_0, 0, 3; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x1162140_0, 0, 3; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x115ed00_0, 0, 11; + %pushi/vec4 0, 0, 11; + %store/vec4 v0x115ee00_0, 0, 11; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x115f290_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x1162b70_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x1163400_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x11635c0_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x1163320_0, 0, 4; + %pushi/vec4 0, 0, 11; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x1162470, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x1162470, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x1162470, 4, 0; + %pushi/vec4 0, 0, 11; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x1162470, 4, 0; + %vpi_call 3 185 "$readmemb", P_0x115eac0, v0x1162080 {0 0 0}; + %end; + .thread T_3; + .scope S_0x115e8d0; +T_4 ; + %wait E_0x1100460; + %load/vec4 v0x11623b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.2, 6; + %jmp T_4.3; +T_4.0 ; + %load/vec4 v0x11625e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.4, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.5, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.6, 6; + %jmp T_4.7; +T_4.4 ; + %load/vec4 v0x115f080_0; + %pad/u 32; + %cmpi/u 4, 0, 32; + %jmp/0xz T_4.8, 5; + %load/vec4 v0x115f450_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %jmp/0xz T_4.10, 5; + %load/vec4 v0x115f450_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %jmp T_4.11; +T_4.10 ; + %load/vec4 v0x115f450_0; + %pad/u 32; + %cmpi/u 6, 0, 32; + %jmp/0xz T_4.12, 5; + %load/vec4 v0x11626c0_0; + %load/vec4 v0x115f450_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.14, 8; + %load/vec4 v0x115f450_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115f450_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %load/vec4 v0x115f450_0; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.15; +T_4.14 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x11623b0_0, 0; + %load/vec4 v0x115f450_0; + %assign/vec4 v0x1162c10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115f450_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1163400_0, 4, 5; +T_4.15 ; + %jmp T_4.13; +T_4.12 ; + %load/vec4 v0x115f450_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.16, 4; + %load/vec4 v0x1162140_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_4.18, 4; + %load/vec4 v0x1162140_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %jmp T_4.19; +T_4.18 ; + %load/vec4 v0x11626c0_0; + %load/vec4 v0x1162140_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.20, 8; + %load/vec4 v0x1162140_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x1162140_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %jmp T_4.21; +T_4.20 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x11623b0_0, 0; + %load/vec4 v0x1162140_0; + %assign/vec4 v0x1162c10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x1162140_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1163400_0, 4, 5; +T_4.21 ; +T_4.19 ; + %jmp T_4.17; +T_4.16 ; + %load/vec4 v0x115f450_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.22, 4; + %load/vec4 v0x1161a60_0; + %flag_set/vec4 8; + %jmp/0xz T_4.24, 8; + %load/vec4 v0x11626c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.26, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.27; +T_4.26 ; + %load/vec4 v0x11626c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.28, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.29; +T_4.28 ; + %load/vec4 v0x11626c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.30, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.31; +T_4.30 ; + %load/vec4 v0x11626c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.32, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x1162140_0, 0; +T_4.32 ; +T_4.31 ; +T_4.29 ; +T_4.27 ; + %jmp T_4.25; +T_4.24 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x11623b0_0, 0; + %load/vec4 v0x115f450_0; + %assign/vec4 v0x1162c10_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163400_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163400_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163400_0, 4, 5; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163400_0, 4, 5; +T_4.25 ; +T_4.22 ; +T_4.17 ; +T_4.13 ; +T_4.11 ; +T_4.8 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.7; +T_4.5 ; + %load/vec4 v0x115f080_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_4.34, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_4.35, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_4.36, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_4.37, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_4.38, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_4.39, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_4.40, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_4.41, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_4.42, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_4.43, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_4.44, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_4.45, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_4.46, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_4.47, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_4.48, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_4.49, 6; + %jmp T_4.50; +T_4.34 ; + %load/vec4 v0x115ed00_0; + %load/vec4 v0x1162cb0_0; + %add; + %assign/vec4 v0x115ed00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.35 ; + %load/vec4 v0x115ed00_0; + %load/vec4 v0x1162cb0_0; + %sub; + %assign/vec4 v0x115ed00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.36 ; + %load/vec4 v0x115f290_0; + %pad/u 11; + %load/vec4 v0x1162cb0_0; + %add; + %pad/u 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.37 ; + %load/vec4 v0x1162cb0_0; + %assign/vec4 v0x1163780_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.38 ; + %vpi_call 3 278 "$display", "here" {0 0 0}; + %load/vec4 v0x115efa0_0; + %assign/vec4 v0x1163780_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.39 ; + %load/vec4 v0x115ed00_0; + %load/vec4 v0x115efa0_0; + %add; + %assign/vec4 v0x115ed00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.40 ; + %load/vec4 v0x115ed00_0; + %load/vec4 v0x115efa0_0; + %sub; + %assign/vec4 v0x115ed00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.41 ; + %load/vec4 v0x115f290_0; + %pad/u 11; + %load/vec4 v0x115efa0_0; + %add; + %pad/u 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.42 ; + %load/vec4 v0x115ee00_0; + %assign/vec4 v0x115ed00_0, 0; + %load/vec4 v0x115ed00_0; + %assign/vec4 v0x115ee00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.43 ; + %load/vec4 v0x115ed00_0; + %assign/vec4 v0x115ee00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.44 ; + %load/vec4 v0x115ed00_0; + %inv; + %pushi/vec4 1, 0, 11; + %add; + %assign/vec4 v0x115ed00_0, 0; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.45 ; + %load/vec4 v0x115f1b0_0; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.50; +T_4.46 ; + %load/vec4 v0x115ed00_0; + %pad/s 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_4.51, 4; + %load/vec4 v0x115f1b0_0; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.52; +T_4.51 ; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; +T_4.52 ; + %jmp T_4.50; +T_4.47 ; + %load/vec4 v0x115ed00_0; + %pad/s 32; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_4.53, 4; + %load/vec4 v0x115f1b0_0; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.54; +T_4.53 ; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; +T_4.54 ; + %jmp T_4.50; +T_4.48 ; + %pushi/vec4 0, 0, 32; + %load/vec4 v0x115ed00_0; + %pad/s 32; + %cmp/s; + %jmp/0xz T_4.55, 5; + %load/vec4 v0x115f1b0_0; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.56; +T_4.55 ; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; +T_4.56 ; + %jmp T_4.50; +T_4.49 ; + %load/vec4 v0x115ed00_0; + %pad/s 32; + %cmpi/s 0, 0, 32; + %jmp/0xz T_4.57, 5; + %load/vec4 v0x115f1b0_0; + %assign/vec4 v0x115f370_0, 0; + %jmp T_4.58; +T_4.57 ; + %load/vec4 v0x115f290_0; + %addi 1, 0, 4; + %assign/vec4 v0x115f370_0, 0; +T_4.58 ; + %jmp T_4.50; +T_4.50 ; + %pop/vec4 1; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.7; +T_4.6 ; + %load/vec4 v0x115f080_0; + %cmpi/e 3, 0, 4; + %flag_mov 8, 4; + %load/vec4 v0x115f080_0; + %cmpi/e 4, 0, 4; + %flag_or 4, 8; + %jmp/0xz T_4.59, 4; + %load/vec4 v0x115eee0_0; + %pad/u 32; + %cmpi/u 2, 0, 32; + %flag_mov 8, 5; + %load/vec4 v0x115eee0_0; + %pushi/vec4 6, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x1162140_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 9; + %flag_or 9, 8; + %jmp/0xz T_4.61, 9; + %load/vec4 v0x115eee0_0; + %cmpi/e 1, 0, 3; + %jmp/0xz T_4.63, 4; + %load/vec4 v0x1163780_0; + %assign/vec4 v0x115ed00_0, 0; +T_4.63 ; + %jmp T_4.62; +T_4.61 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x11623b0_0, 0; + %load/vec4 v0x115eee0_0; + %cmpi/e 6, 0, 3; + %jmp/0xz T_4.65, 4; + %load/vec4 v0x1162140_0; + %assign/vec4 v0x11636a0_0, 0; + %load/vec4 v0x1163780_0; + %load/vec4 v0x1162140_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x1162140_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %jmp T_4.66; +T_4.65 ; + %load/vec4 v0x115eee0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.67, 4; + %load/vec4 v0x115eee0_0; + %assign/vec4 v0x11636a0_0, 0; + %load/vec4 v0x1163780_0; + %load/vec4 v0x115eee0_0; + %pad/u 4; + %subi 2, 0, 4; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x115eee0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x115eee0_0; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.68; +T_4.67 ; + %load/vec4 v0x1161be0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.69, 8; + %load/vec4 v0x1160b10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.71, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.72; +T_4.71 ; + %load/vec4 v0x1160b10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.73, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.74; +T_4.73 ; + %load/vec4 v0x1160b10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.75, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.76; +T_4.75 ; + %load/vec4 v0x1160b10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.77, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x1162140_0, 0; +T_4.77 ; +T_4.76 ; +T_4.74 ; +T_4.72 ; + %jmp T_4.70; +T_4.69 ; + %load/vec4 v0x115eee0_0; + %assign/vec4 v0x11636a0_0, 0; +T_4.70 ; +T_4.68 ; +T_4.66 ; +T_4.62 ; +T_4.59 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.7; +T_4.7 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.1 ; + %load/vec4 v0x11625e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.81, 6; + %jmp T_4.82; +T_4.79 ; + %load/vec4 v0x1162c10_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.83, 4; + %load/vec4 v0x1161a60_0; + %flag_set/vec4 8; + %jmp/0xz T_4.85, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11623b0_0, 0; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x1163400_0, 0, 4; + %load/vec4 v0x11626c0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.87, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.88; +T_4.87 ; + %load/vec4 v0x11626c0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.89, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.90; +T_4.89 ; + %load/vec4 v0x11626c0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.91, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.92; +T_4.91 ; + %load/vec4 v0x11626c0_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.93, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x1162140_0, 0; +T_4.93 ; +T_4.92 ; +T_4.90 ; +T_4.88 ; +T_4.85 ; + %jmp T_4.84; +T_4.83 ; + %load/vec4 v0x11626c0_0; + %load/vec4 v0x1162c10_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.95, 8; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11623b0_0, 0; + %load/vec4 v0x1162c10_0; + %pad/u 5; + %ix/vec4 4; + %load/vec4a v0x1162d90, 4; + %assign/vec4 v0x1162cb0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x1162c10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1162b70_0, 4, 5; + %pushi/vec4 0, 0, 1; + %ix/load 5, 0, 0; + %load/vec4 v0x1162c10_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %assign/vec4/off/d v0x1163400_0, 4, 5; + %load/vec4 v0x1162c10_0; + %assign/vec4 v0x1162140_0, 0; +T_4.95 ; +T_4.84 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.82; +T_4.80 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.82; +T_4.81 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.82; +T_4.82 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.2 ; + %load/vec4 v0x11625e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_4.97, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_4.98, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_4.99, 6; + %jmp T_4.100; +T_4.97 ; + %pushi/vec4 1, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.100; +T_4.98 ; + %load/vec4 v0x11636a0_0; + %cmpi/e 7, 0, 3; + %jmp/0xz T_4.101, 4; + %load/vec4 v0x1161be0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.103, 8; + %load/vec4 v0x1160b10_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.105, 8; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 2, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 2, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 4, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.106; +T_4.105 ; + %load/vec4 v0x1160b10_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.107, 8; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 0, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.108; +T_4.107 ; + %load/vec4 v0x1160b10_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0xz T_4.109, 8; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 1, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 3, 0, 3; + %assign/vec4 v0x1162140_0, 0; + %jmp T_4.110; +T_4.109 ; + %load/vec4 v0x1160b10_0; + %parti/s 1, 3, 3; + %flag_set/vec4 8; + %jmp/0xz T_4.111, 8; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x11636a0_0, 0; + %pushi/vec4 1, 0, 1; + %ix/load 4, 3, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x1163320_0, 4, 5; + %load/vec4 v0x1163780_0; + %ix/load 3, 3, 0; + %flag_set/imm 4, 0; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x1162470, 0, 4; + %pushi/vec4 5, 0, 3; + %assign/vec4 v0x1162140_0, 0; +T_4.111 ; +T_4.110 ; +T_4.108 ; +T_4.106 ; +T_4.103 ; +T_4.101 ; + %pushi/vec4 2, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.100; +T_4.99 ; + %load/vec4 v0x11636a0_0; + %cmpi/ne 7, 0, 3; + %jmp/0xz T_4.113, 4; + %load/vec4 v0x11634e0_0; + %load/vec4 v0x11636a0_0; + %pad/u 5; + %subi 2, 0, 5; + %part/s 1; + %flag_set/vec4 8; + %jmp/0xz T_4.115, 8; + %pushi/vec4 0, 0, 1; + %load/vec4 v0x11636a0_0; + %pad/u 5; + %subi 2, 0, 5; + %ix/vec4/s 4; + %store/vec4 v0x1163320_0, 4, 1; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11623b0_0, 0; +T_4.115 ; +T_4.113 ; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x11625e0_0, 0; + %jmp T_4.100; +T_4.100 ; + %pop/vec4 1; + %jmp T_4.3; +T_4.3 ; + %pop/vec4 1; + %jmp T_4; + .thread T_4; + .scope S_0x115e8d0; +T_5 ; + %wait E_0x1122a60; + %load/vec4 v0x11625e0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x11623b0_0; + %pushi/vec4 0, 0, 3; + %cmp/e; + %flag_get/vec4 4; + %and; + %load/vec4 v0x115f370_0; + %xor/r; + %pushi/vec4 1, 1, 1; + %cmp/e; + %flag_get/vec4 6; + %inv; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %load/vec4 v0x115f370_0; + %assign/vec4 v0x115f290_0, 0; +T_5.0 ; + %load/vec4 v0x11625e0_0; + %cmpi/e 0, 0, 3; + %jmp/0xz T_5.2, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x1162b70_0, 0, 4; +T_5.2 ; + %jmp T_5; + .thread T_5; + .scope S_0x1117100; +T_6 ; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x1163ef0_0, 0, 33; + %pushi/vec4 0, 0, 33; + %store/vec4 v0x1163ef0_0, 0, 33; +T_6.0 ; + %load/vec4 v0x1163ef0_0; + %cmpi/u 10, 0, 33; + %jmp/0xz T_6.1, 5; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1163db0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x1163db0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1163db0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x1163db0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x1163db0_0, 0, 1; + %delay 1, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x1163db0_0, 0, 1; + %delay 1, 0; + %vpi_call 2 24 "$display", "accLeft = %d \012accRight= %d\012", v0x1163c40_0, v0x1163ce0_0 {0 0 0}; + %load/vec4 v0x1163ef0_0; + %addi 1, 0, 33; + %store/vec4 v0x1163ef0_0, 0, 33; + %jmp T_6.0; +T_6.1 ; + %end; + .thread T_6; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "tis100.t.v"; + "./tis100.v"; diff --git a/tis100.t.v b/tis100.t.v new file mode 100644 index 0000000..ca376bc --- /dev/null +++ b/tis100.t.v @@ -0,0 +1,28 @@ +`include "tis100.v" +module tis100Test(); + +reg clk; +wire signed[10:0] accOutLeft; +wire signed[10:0] accOutRight; +reg[32:0] i; + +wire[14:0] L2R; +wire[14:0] R2L; + +tis100 #("left.dat") left( .clk(clk), .accOut(accOutLeft), .rightOut(L2R), .right(R2L)); +tis100 #("right.dat") right(.clk(clk), .accOut(accOutRight), .left(L2R), .leftOut(R2L)); + +initial begin + i = 0; + for( i = 0; i<10; i=i+1) begin + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + clk = 0; #1; + clk = 1; #1; + $display("accLeft = %d \naccRight= %d\n",accOutLeft,accOutRight); + end +end + +endmodule diff --git a/tis100.v b/tis100.v new file mode 100644 index 0000000..b91635f --- /dev/null +++ b/tis100.v @@ -0,0 +1,541 @@ +`define RUN_MODE 2'd0 +`define READ_MODE 2'd1 +`define WRITE_MODE 2'd2 + +`define READ_PHASE 2'd0 +`define EX_PHASE 2'd1 +`define WRITE_PHASE 2'd2 + +`define READ_REQ_BIT 11 +`define WRITE_REQ_BIT 12 +`define READ_ACK_BIT 13 +`define WRITE_ACK_BIT 14 + +//registers +`define NIL_ADDR 3'd0 +`define ACC_ADDR 3'd1 +//ports +`define LEFT_ADDR 3'd2 +`define RIGHT_ADDR 3'd3 +`define UP_ADDR 3'd4 +`define DOWN_ADDR 3'd5 +//pseudo ports +`define LAST_ADDR 3'd6 +`define ANY_ADDR 3'd7 + +`define ADDR_SIZE 3 +`define INST_SIZE 18 + + +`define ADD 4'd0 +`define SUB 4'd1 +`define JRO 4'd2 +`define MOV 4'd3 +`define MOVI 4'd4 +`define ADDI 4'd5 +`define SUBI 4'd6 +`define JROI 4'd7 +`define SWP 4'd8 +`define SAV 4'd9 +`define NEG 4'd10 +`define JMP 4'd11 +`define JEZ 4'd12 +`define JNZ 4'd13 +`define JGZ 4'd14 +`define JLZ 4'd15 + + + +module tis100(input clk, + input[14:0] up, + input[14:0] down, + input[14:0] left, + input[14:0] right, + output[14:0] upOut, + output[14:0] downOut, + output[14:0] leftOut, + output[14:0] rightOut, + output signed[10:0] accOut); + +parameter memFile = "memory.dat"; +parameter debug = 0; + + +//internal registers +reg[2:0] mode; +reg[2:0] phase; +reg[`ADDR_SIZE-1:0] last; +reg[`ADDR_SIZE-1:0] writeTarget; +reg[`ADDR_SIZE-1:0] readTarget; +reg signed[10:0] readValue; +reg signed[10:0] writeValue; + +reg[`INST_SIZE-1:0] instructions[0:15]; +reg[3:0] PC; +reg[3:0] PCNEXT; + +reg signed[10:0] ACC; +reg signed[10:0] BAK; +assign accOut = ACC; + +//port stuff +wire signed[10:0] regVals[7:0]; +assign regVals[`NIL_ADDR] = 0; +assign regVals[`ACC_ADDR] = ACC; +assign regVals[`LEFT_ADDR] = left[10:0]; +assign regVals[`RIGHT_ADDR] = right[10:0]; +assign regVals[`UP_ADDR] = up[10:0]; +assign regVals[`DOWN_ADDR] = down[10:0]; + +wire[5:2] portsHaveData; +assign portsHaveData[`LEFT_ADDR] = left[`READ_REQ_BIT]; +assign portsHaveData[`RIGHT_ADDR] = right[`READ_REQ_BIT]; +assign portsHaveData[`UP_ADDR] = up[`READ_REQ_BIT]; +assign portsHaveData[`DOWN_ADDR] = down[`READ_REQ_BIT]; +wire anyHasData; +assign anyHasData = |portsHaveData[5:2]; + +wire[5:2] portsWantData; +assign portsWantData[`LEFT_ADDR] = left[`WRITE_REQ_BIT]; +assign portsWantData[`RIGHT_ADDR] = right[`WRITE_REQ_BIT]; +assign portsWantData[`UP_ADDR] = up[`WRITE_REQ_BIT]; +assign portsWantData[`DOWN_ADDR] = down[`WRITE_REQ_BIT]; +wire anyWantData; +assign anyWantData = |portsWantData[5:2]; + +wire[5:2] readAckIn; +assign readAckIn[`LEFT_ADDR] = left[`READ_ACK_BIT]; +assign readAckIn[`RIGHT_ADDR] = right[`READ_ACK_BIT]; +assign readAckIn[`UP_ADDR] = up[`READ_ACK_BIT]; +assign readAckIn[`DOWN_ADDR] = down[`READ_ACK_BIT]; +wire anyReadAck; +assign anyReadAck = |readAckIn[5:2]; + +wire[5:2] writeAckIn; +assign writeAckIn[`LEFT_ADDR] = left[`WRITE_ACK_BIT]; +assign writeAckIn[`RIGHT_ADDR] = right[`WRITE_ACK_BIT]; +assign writeAckIn[`UP_ADDR] = up[`WRITE_ACK_BIT]; +assign writeAckIn[`DOWN_ADDR] = down[`WRITE_ACK_BIT]; +wire anyWriteAck; +assign anyWriteAck = |writeAckIn[5:2]; + +reg[5:2] readAckOut; +assign leftOut[`WRITE_ACK_BIT] = readAckOut[`LEFT_ADDR]; +assign rightOut[`WRITE_ACK_BIT] = readAckOut[`RIGHT_ADDR]; +assign upOut[`WRITE_ACK_BIT] = readAckOut[`UP_ADDR]; +assign downOut[`WRITE_ACK_BIT] = readAckOut[`DOWN_ADDR]; + +reg[5:2] writeAckOut; +assign leftOut[`READ_ACK_BIT] = writeAckOut[`LEFT_ADDR]; +assign rightOut[`READ_ACK_BIT] = writeAckOut[`RIGHT_ADDR]; +assign upOut[`READ_ACK_BIT] = writeAckOut[`UP_ADDR]; +assign downOut[`READ_ACK_BIT] = writeAckOut[`DOWN_ADDR]; + +reg[5:2] weWantData; +assign leftOut[`WRITE_REQ_BIT] = weWantData[`LEFT_ADDR]; +assign rightOut[`WRITE_REQ_BIT] = weWantData[`RIGHT_ADDR]; +assign upOut[`WRITE_REQ_BIT] = weWantData[`UP_ADDR]; +assign downOut[`WRITE_REQ_BIT] = weWantData[`DOWN_ADDR]; + +reg[5:2] weHaveData; +assign leftOut[`READ_REQ_BIT] = weHaveData[`LEFT_ADDR]; +assign rightOut[`READ_REQ_BIT] = weHaveData[`RIGHT_ADDR]; +assign upOut[`READ_REQ_BIT] = weHaveData[`UP_ADDR]; +assign downOut[`READ_REQ_BIT] = weHaveData[`DOWN_ADDR]; + +//decode +wire[`INST_SIZE-1:0] instruction; +assign instruction = instructions[PC]; + +reg signed[10:0] outVals[5:2]; + +assign upOut[10:0] = outVals[`UP_ADDR]; +assign downOut[10:0] = outVals[`DOWN_ADDR]; +assign leftOut[10:0] = outVals[`LEFT_ADDR]; +assign rightOut[10:0] = outVals[`RIGHT_ADDR]; + + +wire[3:0] INST; +assign INST[3:0] = instruction[17:14]; +wire[`ADDR_SIZE-1:0] DST; +assign DST[`ADDR_SIZE-1:0] = instruction[13:11]; +wire[`ADDR_SIZE-1:0] SRC; +assign SRC[`ADDR_SIZE-1:0] = instruction[10:8]; +wire[3:0] LABEL; +assign LABEL[3:0] = instruction[13:10]; +wire signed[10:0] IMM; +assign IMM[10:0] = instruction[10:0]; + + +initial begin + mode = `RUN_MODE; + phase = `READ_PHASE; + last = `NIL_ADDR; + ACC = 0; + BAK = 0; + PC = 0; + readAckOut = 0; + weWantData = 0; + writeAckOut = 0; + weHaveData = 0; + + outVals[`UP_ADDR] = 0; + outVals[`DOWN_ADDR] = 0; + outVals[`LEFT_ADDR] = 0; + outVals[`RIGHT_ADDR] = 0; + + $readmemb(memFile, instructions); +end + +always @(posedge clk) begin + case(mode) + `RUN_MODE: begin + case(phase) + `READ_PHASE: begin + if(INST < 4) begin //instruction has a SRC + if(SRC < 2) begin //SRC is a register, not a port + readValue <= regVals[SRC]; + end + else if(SRC < 6) begin//src is a port, not a register + if(portsHaveData[SRC]) begin//src has data now + readValue <= regVals[SRC]; + readAckOut[SRC] <= 1; + last <= SRC; + end + else begin //src has no data now + mode <= `READ_MODE; + readTarget <= SRC; + weWantData[SRC] <= 1; + last <= SRC; + end + end//src is a port + else if (SRC == `LAST_ADDR) begin//src is LAST + if(last == `NIL_ADDR) begin//edge case, last is NIL still + readValue <= regVals[last]; + end + else begin//last is a port + if(portsHaveData[last]) begin//last has data now + readValue <= regVals[last]; + readAckOut[last] <= 1; + end + else begin + mode <= `READ_MODE; + readTarget <= last; + weWantData[last] <= 1; + end + end//last is a port + end//src is last + else if (SRC == `ANY_ADDR) begin//src is ANY + if(anyHasData) begin//any port has data + if(portsHaveData[`LEFT_ADDR]) begin + readValue <= regVals[`LEFT_ADDR]; + readAckOut[`LEFT_ADDR] <= 1; + last <= `LEFT_ADDR; + end + else if(portsHaveData[`RIGHT_ADDR]) begin + readValue <= regVals[`RIGHT_ADDR]; + readAckOut[`RIGHT_ADDR] <= 1; + last <= `RIGHT_ADDR; + end + else if(portsHaveData[`UP_ADDR]) begin + readValue <= regVals[`UP_ADDR]; + readAckOut[`UP_ADDR] <= 1; + last <= `UP_ADDR; + end + else if(portsHaveData[`DOWN_ADDR]) begin + readValue <= regVals[`DOWN_ADDR]; + readAckOut[`DOWN_ADDR] <= 1; + last <= `DOWN_ADDR; + end + end//any port has data + else begin//no port has data + mode <= `READ_MODE; + readTarget <= SRC; + weWantData[`UP_ADDR] <= 1; + weWantData[`DOWN_ADDR] <= 1; + weWantData[`LEFT_ADDR] <= 1; + weWantData[`RIGHT_ADDR] <= 1; + end + end//src is ANY + end//instruction has a SRC + phase <= `EX_PHASE; + end//READ_PHASE + `EX_PHASE: begin + case(INST) + `ADD: begin + ACC <= ACC + readValue; + PCNEXT <= PC + 1; + end + `SUB: begin + ACC <= ACC - readValue; + PCNEXT <= PC + 1; + end + `JRO: begin + PCNEXT <= PC + readValue; + end + `MOV: begin + writeValue <= readValue; + PCNEXT <= PC + 1; + end + `MOVI: begin + writeValue <= IMM; + PCNEXT <= PC + 1; + end + `ADDI: begin + ACC <= ACC + IMM; + PCNEXT <= PC + 1; + end + `SUBI: begin + ACC <= ACC - IMM; + PCNEXT <= PC + 1; + end + `JROI: begin + PCNEXT <= PC + IMM; + end + `SWP: begin + ACC <= BAK; + BAK <= ACC; + PCNEXT <= PC + 1; + end + `SAV: begin + BAK <= ACC; + PCNEXT <= PC + 1; + end + `NEG: begin + ACC <= -ACC; + PCNEXT <= PC + 1; + end + `JMP: begin + PCNEXT <= LABEL; + end + `JEZ: begin + if(ACC == 0) PCNEXT <= LABEL; + else PCNEXT <= PC + 1; + end + `JNZ: begin + if(ACC != 0) PCNEXT <= LABEL; + else PCNEXT <= PC + 1; + end + `JGZ: begin + if(ACC > 0) PCNEXT <= LABEL; + else PCNEXT <= PC + 1; + end + `JLZ: begin + if(ACC < 0) PCNEXT <= LABEL; + else PCNEXT <= PC + 1; + end + endcase + phase <= `WRITE_PHASE; + end//ex phase + `WRITE_PHASE: begin + if(INST == `MOV || INST == `MOVI) begin //inst has dst + if(DST < 2 || (DST == `LAST_ADDR && last == `NIL_ADDR)) begin//DST is a register + if(DST == `ACC_ADDR) begin + ACC <= writeValue; + if(debug) begin + $display("ACC = %d", writeValue); + end + end + end//dst is a register + else begin//dst is a port or pseudo port + mode <= `WRITE_MODE; + if(DST == `LAST_ADDR) begin + writeTarget <= last; + outVals[last] <= writeValue; + weHaveData[last] <= 1; + end + else if(DST != `ANY_ADDR) begin + writeTarget <= DST; + outVals[DST] <= writeValue; + weHaveData[DST] <= 1; + last <= DST; + end + else begin//ANY + if(anyWantData) begin//someone wants data + if(portsWantData[`UP_ADDR]) begin + writeTarget <= `UP_ADDR; + weHaveData[`UP_ADDR] <= 1; + outVals[`UP_ADDR] <= writeValue; + last <= `UP_ADDR; + end + else if(portsWantData[`LEFT_ADDR]) begin + writeTarget <= `LEFT_ADDR; + weHaveData[`LEFT_ADDR] <= 1; + outVals[`LEFT_ADDR] <= writeValue; + last <= `LEFT_ADDR; + end + else if(portsWantData[`RIGHT_ADDR]) begin + writeTarget <= `RIGHT_ADDR; + weHaveData[`RIGHT_ADDR] <= 1; + outVals[`RIGHT_ADDR] <= writeValue; + last <= `RIGHT_ADDR; + end + else if(portsWantData[`DOWN_ADDR]) begin + writeTarget <= `DOWN_ADDR; + weHaveData[`DOWN_ADDR] <= 1; + outVals[`DOWN_ADDR] <= writeValue; + last <= `DOWN_ADDR; + end + end + else begin//no one wants data + writeTarget <= DST; + end + end + end + end//inst has dst + phase <= `READ_PHASE; + end + endcase + end + `READ_MODE: begin + case(phase) + `READ_PHASE: begin + if(readTarget == `ANY_ADDR) begin + if(anyHasData) begin + mode <= `RUN_MODE; + weWantData = 4'd0; + if(portsHaveData[`LEFT_ADDR]) begin + readValue <= regVals[`LEFT_ADDR]; + readAckOut[`LEFT_ADDR] <= 1; + last <= `LEFT_ADDR; + end + else if(portsHaveData[`RIGHT_ADDR]) begin + readValue <= regVals[`RIGHT_ADDR]; + readAckOut[`RIGHT_ADDR] <= 1; + last <= `RIGHT_ADDR; + end + else if(portsHaveData[`UP_ADDR]) begin + readValue <= regVals[`UP_ADDR]; + readAckOut[`UP_ADDR] <= 1; + last <= `UP_ADDR; + end + else if(portsHaveData[`DOWN_ADDR]) begin + readValue <= regVals[`DOWN_ADDR]; + readAckOut[`DOWN_ADDR] <= 1; + last <= `DOWN_ADDR; + end + end + end//target is not ANY + else begin + if(portsHaveData[readTarget]) begin//readTarget has data now + mode <= `RUN_MODE; + readValue <= regVals[readTarget]; + readAckOut[readTarget] <= 1; + weWantData[readTarget] <= 0; + last <= readTarget; + end + end + phase <= `EX_PHASE; + end + `EX_PHASE: begin + phase <= `WRITE_PHASE; + end + `WRITE_PHASE: begin + phase <= `READ_PHASE; + end + endcase + end + `WRITE_MODE: begin + case(phase) + `READ_PHASE: begin + phase <= `EX_PHASE; + end + `EX_PHASE: begin + if(writeTarget == `ANY_ADDR) begin + if(anyWantData) begin//someone wants data + if(portsWantData[`UP_ADDR]) begin + writeTarget <= `UP_ADDR; + weHaveData[`UP_ADDR] <= 1; + outVals[`UP_ADDR] <= writeValue; + last <= `UP_ADDR; + end + else if(portsWantData[`LEFT_ADDR]) begin + writeTarget <= `LEFT_ADDR; + weHaveData[`LEFT_ADDR] <= 1; + outVals[`LEFT_ADDR] <= writeValue; + last <= `LEFT_ADDR; + end + else if(portsWantData[`RIGHT_ADDR]) begin + writeTarget <= `RIGHT_ADDR; + weHaveData[`RIGHT_ADDR] <= 1; + outVals[`RIGHT_ADDR] <= writeValue; + last <= `RIGHT_ADDR; + end + else if(portsWantData[`DOWN_ADDR]) begin + writeTarget <= `DOWN_ADDR; + weHaveData[`DOWN_ADDR] <= 1; + outVals[`DOWN_ADDR] <= writeValue; + last <= `DOWN_ADDR; + end + end + end + phase <= `WRITE_PHASE; + end + `WRITE_PHASE: begin + if(writeTarget != `ANY_ADDR) begin//target is not any + if(writeAckIn[writeTarget]) begin//write was acked + weHaveData[writeTarget] = 0; + mode <= `RUN_MODE; + last <= writeTarget; + end + end + phase <= `READ_PHASE; + end + endcase + end + endcase +end + +always @(negedge clk) begin + if(phase == `READ_PHASE && mode == `RUN_MODE && ^PCNEXT !== 1'bx) begin + PC <= PCNEXT; + end + if(phase == `READ_PHASE) begin + readAckOut = 4'd0; + end +end + +endmodule + + + +//writing: set requestWrite high, block until ackWrite goes high +//reading: block until dataReady goes high, pulse ackRead + +//instructions: +//NO ARG: + + +//R/I +//ADD : SRC +//SUB : SRC +//JRO : SRC +//MOV : SRC DST + +//R +//NOP = ADD NIL +//SWP +//SAV +//NEG + +//J type +//JMP : LABEL +//JEZ : LABEL +//JNZ : LABEL +//JGZ : LABEL +//JLZ : LABEL + +//SRC : port or ACC or immediate +//DST : port or ACC +//LABEL : immediate + +//registers: +//ACC +//BAK + +//ports: +//LEFT,RIGHT,UP,DOWN + +//pseudo ports: +//ANY : UP, LEFT, RIGHT, DOWN for write. LEFT, RIGHT, UP, DOWN for read +//LAST : If no last operation ignored