diff --git a/Adder.vcd b/Adder.vcd
new file mode 100644
index 0000000..bcd4861
--- /dev/null
+++ b/Adder.vcd
@@ -0,0 +1,118 @@
+$date
+	Thu Sep 21 00:00:54 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module behavioralFullAdder $end
+$var wire 1 ! a $end
+$var wire 1 " b $end
+$var wire 1 # carryin $end
+$var wire 1 $ carryout $end
+$var wire 1 % sum $end
+$upscope $end
+$scope module testFullAdder $end
+$var wire 1 & carryout $end
+$var wire 1 ' sum $end
+$var reg 1 ( a $end
+$var reg 1 ) b $end
+$var reg 1 * carryin $end
+$scope module potatoz $end
+$var wire 1 + a $end
+$var wire 1 , aandb $end
+$var wire 1 - axorb $end
+$var wire 1 . b $end
+$var wire 1 / candaxorb $end
+$var wire 1 0 carryin $end
+$var wire 1 & carryout $end
+$var wire 1 ' sum $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+00
+z/
+0.
+z-
+z,
+0+
+0*
+0)
+0(
+x'
+x&
+x%
+x$
+z#
+z"
+z!
+$end
+#50000
+0/
+0,
+0-
+#100000
+0&
+0'
+#1000000
+1(
+1+
+#1050000
+1-
+#1100000
+1'
+#2000000
+1)
+1.
+0(
+0+
+#3000000
+1(
+1+
+#3050000
+0-
+1,
+#3100000
+0'
+1&
+#4000000
+1*
+10
+0)
+0.
+0(
+0+
+#4050000
+1'
+0,
+#4100000
+0&
+#5000000
+1(
+1+
+#5050000
+1-
+#5100000
+0'
+1/
+#5150000
+1&
+#6000000
+1)
+1.
+0(
+0+
+#7000000
+1(
+1+
+#7050000
+0-
+1,
+#7100000
+1'
+0/
+#8000000
diff --git a/CompArch_HW_2.pdf b/CompArch_HW_2.pdf
new file mode 100644
index 0000000..f484291
Binary files /dev/null and b/CompArch_HW_2.pdf differ
diff --git a/Decoder.vcd b/Decoder.vcd
new file mode 100644
index 0000000..8480f86
--- /dev/null
+++ b/Decoder.vcd
@@ -0,0 +1,162 @@
+$date
+	Thu Sep 21 00:01:30 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module behavioralDecoder $end
+$var wire 1 ! address0 $end
+$var wire 1 " address1 $end
+$var wire 1 # enable $end
+$var wire 1 $ out0 $end
+$var wire 1 % out1 $end
+$var wire 1 & out2 $end
+$var wire 1 ' out3 $end
+$upscope $end
+$scope module testDecoder $end
+$var wire 1 ( out0 $end
+$var wire 1 ) out1 $end
+$var wire 1 * out2 $end
+$var wire 1 + out3 $end
+$var reg 1 , addr0 $end
+$var reg 1 - addr1 $end
+$var reg 1 . enable $end
+$scope module decode $end
+$var wire 1 / A0 $end
+$var wire 1 0 A0andA1 $end
+$var wire 1 1 A0andnA1 $end
+$var wire 1 2 A1 $end
+$var wire 1 3 enable $end
+$var wire 1 4 nA0 $end
+$var wire 1 5 nA0andA1 $end
+$var wire 1 6 nA0andnA1 $end
+$var wire 1 7 nA1 $end
+$var wire 1 ( out0 $end
+$var wire 1 ) out1 $end
+$var wire 1 * out2 $end
+$var wire 1 + out3 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z7
+x6
+z5
+z4
+03
+02
+z1
+z0
+0/
+0.
+0-
+0,
+z+
+z*
+z)
+z(
+x'
+x&
+x%
+x$
+z#
+z"
+z!
+$end
+#50000
+0+
+0*
+0)
+0(
+00
+05
+01
+14
+17
+#100000
+16
+#1000000
+1,
+1/
+#1050000
+04
+11
+#1100000
+06
+#2000000
+1-
+12
+0,
+0/
+#2050000
+07
+14
+01
+#2100000
+15
+#3000000
+1,
+1/
+#3050000
+04
+10
+#3100000
+05
+#4000000
+0-
+02
+0,
+0/
+1.
+13
+#4050000
+17
+14
+00
+1+
+#4100000
+16
+0+
+#4150000
+1(
+#5000000
+1,
+1/
+#5050000
+04
+11
+#5100000
+06
+1)
+#5150000
+0(
+#6000000
+1-
+12
+0,
+0/
+#6050000
+07
+14
+01
+#6100000
+15
+0)
+#6150000
+1*
+#7000000
+1,
+1/
+#7050000
+04
+10
+#7100000
+05
+1+
+#7150000
+0*
+#8000000
diff --git a/Multiplexer.vcd b/Multiplexer.vcd
new file mode 100644
index 0000000..af555df
--- /dev/null
+++ b/Multiplexer.vcd
@@ -0,0 +1,185 @@
+$date
+	Thu Sep 21 00:00:06 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module behavioralMultiplexer $end
+$var wire 2 ! address [1:0] $end
+$var wire 1 " address0 $end
+$var wire 1 # address1 $end
+$var wire 1 $ in0 $end
+$var wire 1 % in1 $end
+$var wire 1 & in2 $end
+$var wire 1 ' in3 $end
+$var wire 4 ( inputs [3:0] $end
+$var wire 1 ) out $end
+$upscope $end
+$scope module testMultiplexer $end
+$var wire 1 * out $end
+$var reg 1 + S0 $end
+$var reg 1 , S1 $end
+$var reg 1 - in0 $end
+$var reg 1 . in1 $end
+$var reg 1 / in2 $end
+$var reg 1 0 in3 $end
+$scope module newpotato $end
+$var wire 1 1 S0 $end
+$var wire 1 2 S1 $end
+$var wire 1 3 in0 $end
+$var wire 1 4 in1 $end
+$var wire 1 5 in2 $end
+$var wire 1 6 in3 $end
+$var wire 1 7 nS0 $end
+$var wire 1 8 nS1 $end
+$var wire 1 * out $end
+$var wire 1 9 out0 $end
+$var wire 1 : out1 $end
+$var wire 1 ; out2 $end
+$var wire 1 < out3 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+z<
+z;
+z:
+x9
+z8
+z7
+06
+05
+04
+13
+02
+01
+00
+0/
+0.
+1-
+0,
+0+
+z*
+x)
+bz (
+z'
+z&
+z%
+z$
+z#
+z"
+bz !
+$end
+#50000
+x*
+1<
+1;
+1:
+17
+18
+#100000
+09
+#150000
+1*
+#1000000
+1+
+11
+1.
+14
+0-
+03
+#1050000
+07
+0:
+19
+#2000000
+1,
+12
+0+
+01
+1/
+15
+0.
+04
+#2050000
+08
+17
+1:
+#2100000
+0;
+0*
+#2150000
+1*
+#3000000
+1+
+11
+10
+16
+0/
+05
+#3050000
+07
+0<
+1;
+#4000000
+0,
+02
+0+
+01
+1/
+15
+1.
+14
+#4050000
+18
+17
+1<
+#4100000
+0*
+#5000000
+1+
+11
+0.
+04
+1-
+13
+#5050000
+07
+09
+#5100000
+19
+1*
+#5150000
+0*
+#6000000
+1,
+12
+0+
+01
+0/
+05
+1.
+14
+#6050000
+08
+17
+#7000000
+1+
+11
+00
+06
+1/
+15
+#7050000
+07
+0;
+#7100000
+1;
+1*
+#7150000
+0*
+#8000000
diff --git a/adder.t.v b/adder.t.v
index 76109ed..284cdfc 100644
--- a/adder.t.v
+++ b/adder.t.v
@@ -3,12 +3,39 @@
 `include "adder.v"
 
 module testFullAdder();
-    reg a, b, carryin;
+
     wire sum, carryout;
+    reg a, b, carryin;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    //behavioralFullAdder potatoe(sum, carryout, a, b, carryin);
+    structuralFullAdder potatoz(sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+
+    	$dumpfile("Adder.vcd");
+    	$dumpvars();
+
+    $display("a b CarIn | Sum CarO | ExSum ExCar ");
+
+    a=0; b=0; carryin=0; #1000 
+    $display("%b %b   %b   |  %b   %b   |   0   0   ", a, b, carryin, sum, carryout);
+    a=1; b=0; carryin=0; #1000 
+    $display("%b %b   %b   |  %b   %b   |   1   0   ", a, b, carryin, sum, carryout);
+    a=0; b=1; carryin=0; #1000 
+    $display("%b %b   %b   |  %b   %b   |   1   0   ", a, b, carryin, sum, carryout);
+    a=1; b=1; carryin=0; #1000 
+    $display("%b %b   %b   |  %b   %b   |   0   1   ", a, b, carryin, sum, carryout);
+    
+    a=0; b=0; carryin=1; #1000 
+    $display("%b %b   %b   |  %b   %b   |   1   0   ", a, b, carryin, sum, carryout);
+    a=1; b=0; carryin=1; #1000 
+    $display("%b %b   %b   |  %b   %b   |   0   1   ", a, b, carryin, sum, carryout);
+    a=0; b=1; carryin=1; #1000 
+    $display("%b %b   %b   |  %b   %b   |   0   1   ", a, b, carryin, sum, carryout);
+    a=1; b=1; carryin=1; #1000 
+    $display("%b %b   %b   |  %b   %b   |   1   1   ", a, b, carryin, sum, carryout);
+  
+    
     end
+  
 endmodule
diff --git a/adder.v b/adder.v
index d21f7e4..dba379d 100644
--- a/adder.v
+++ b/adder.v
@@ -1,5 +1,9 @@
 // Adder circuit
 
+`define Xor xor #50
+`define And and #50
+`define Or or #50
+
 module behavioralFullAdder
 (
     output sum, 
@@ -16,9 +20,18 @@ module structuralFullAdder
 (
     output sum, 
     output carryout,
-    input a, 
-    input b, 
+    input a, b, 
     input carryin
 );
-    // Your adder code here
+    wire axorb; 
+    wire aandb; 
+    wire candaxorb;	
+	
+	`Xor xor1(axorb, a, b); 
+	`And and2(aandb, a, b);
+	`Xor xor3(sum, axorb, carryin);
+	`And and4(candaxorb, carryin, axorb); 
+	`Or or5(carryout, aandb, candaxorb);
+
+
 endmodule
diff --git a/decoder.t.v b/decoder.t.v
index e0e925f..fcd9971 100644
--- a/decoder.t.v
+++ b/decoder.t.v
@@ -1,16 +1,20 @@
 // Decoder testbench
-`timescale 1 ns / 1 ps
+`timescale 1 ns / 1 ps // ns timescale, ps resolution 
 `include "decoder.v"
 
 module testDecoder (); 
+    wire out0,out1,out2,out3;
     reg addr0, addr1;
     reg enable;
-    wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decode(out0,out1,out2,out3,addr0,addr1,enable); // remove things in .v file
 
     initial begin
+    
+    	$dumpfile("Decoder.vcd");
+    	$dumpvars();
+    
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);
diff --git a/decoder.v b/decoder.v
index 17836e0..d1e887e 100644
--- a/decoder.v
+++ b/decoder.v
@@ -1,4 +1,6 @@
 // Decoder circuit
+`define And and #50
+`define Not not #50
 
 module behavioralDecoder
 (
@@ -6,17 +8,37 @@ module behavioralDecoder
     input address0, address1,
     input enable
 );
-    // Uses concatenation and shift operators
     assign {out3,out2,out1,out0}=enable<<{address1,address0};
 endmodule
 
+///////////////////////////////////////  My decoder  /////////////////////////////////////////////////
+
 
 module structuralDecoder
 (
-    output out0, out1, out2, out3,
-    input address0, address1,
+    output out0, out1, out2, out3, 
+    input A0, A1,
     input enable
 );
-    // Your decoder code here
+    wire nA0;  
+    wire nA1; 
+    wire nA0andnA1; 
+    wire A0andnA1; 
+    wire nA0andA1; 
+    wire A0andA1; 
+
+    `Not A0inv(nA0, A0);  
+    `Not A1inv(nA1, A1); 
+
+    `And and0(nA0andnA1, nA0, nA1);
+    `And and1(A0andnA1 , A0 , nA1);
+    `And and2(nA0andA1 , nA0, A1);
+    `And and3(A0andA1  , A0 , A1);
+
+    `And and_0(out0, nA0andnA1, enable); 
+    `And and_1(out1, A0andnA1 , enable); 
+    `And and_2(out2, nA0andA1 , enable); 
+    `And and_3(out3, A0andA1  , enable); 
+
 endmodule
 
diff --git a/multiplexer.t.v b/multiplexer.t.v
index fd475c4..299cef5 100644
--- a/multiplexer.t.v
+++ b/multiplexer.t.v
@@ -3,5 +3,38 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+    wire out;
+    reg S0, S1;
+    reg in0, in1, in2, in3; 
+
+    // behavioralMultiplexer potato(out, S0, S1, in0, in1, in2, in3); 
+    structM newpotato(out, S0, S1, in0, in1, in2, in3); 
+
+initial begin
+
+    	$dumpfile("Multiplexer.vcd");
+    	$dumpvars();
+
+    $display("S0 S1| O0 O1 O2 O3 |output| Expected Output");
+    in0=1;in1=0;in2=0;in3=0;S0=0;S1=0; #1000 
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in0", S0, S1, in0, in1, in2, in3, out);
+    in0=0;in1=1;in2=0;in3=0;S0=1;S1=0; #1000
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in1", S0, S1, in0, in1, in2, in3, out);
+    in0=0;in1=0;in2=1;in3=0;S0=0;S1=1; #1000 
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in2", S0, S1, in0, in1, in2, in3, out);
+    in0=0;in1=0;in2=0;in3=1;S0=1;S1=1; #1000 
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in3", S0, S1, in0, in1, in2, in3, out);
+    
+    in0=0;in1=1;in2=1;in3=1;S0=0;S1=0; #1000 
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in0", S0, S1, in0, in1, in2, in3, out);
+    in0=1;in1=0;in2=1;in3=1;S0=1;S1=0; #1000
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in1", S0, S1, in0, in1, in2, in3, out);
+    in0=1;in1=1;in2=0;in3=1;S0=0;S1=1; #1000 
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in2", S0, S1, in0, in1, in2, in3, out);
+    in0=1;in1=1;in2=1;in3=0;S0=1;S1=1; #1000 
+    $display("%b  %b |  %b  %b  %b  %b |  %b   | in3", S0, S1, in0, in1, in2, in3, out);
+    
+    end
+
+
 endmodule
diff --git a/multiplexer.v b/multiplexer.v
index b05820f..14d8094 100644
--- a/multiplexer.v
+++ b/multiplexer.v
@@ -1,4 +1,7 @@
 // Multiplexer circuit
+`define Not not #50
+`define Nand nand #50
+`define Or or #50
 
 module behavioralMultiplexer
 (
@@ -13,12 +16,33 @@ module behavioralMultiplexer
 endmodule
 
 
-module structuralMultiplexer
+module structM
 (
     output out,
-    input address0, address1,
+    input S0, S1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    
+    wire nS0; 
+    wire nS1; 
+
+    wire out0; 
+    wire out1; 
+    wire out2; 
+    wire out3; 
+
+
+    `Not S0inv(nS0, S0);
+    `Not S1inv(nS1, S1);
+
+    `Nand n0(out0, nS0, nS1, in0);
+    `Nand n1(out1, S0,  nS1, in1);
+    `Nand n2(out2, nS0, S1, in2);
+    `Nand n3(out3, S0,  S1, in3);
+
+    `Nand addthem(out, out0, out1, out2, out3);
+
+
 endmodule
 
+