diff --git a/deliverable1_6.png b/deliverable1_6.png
new file mode 100644
index 0000000..78d29dd
Binary files /dev/null and b/deliverable1_6.png differ
diff --git a/regfile.t.v b/regfile.t.v
index f13815a..852f94f 100644
--- a/regfile.t.v
+++ b/regfile.t.v
@@ -1,3 +1,5 @@
+`include "regfile.v"
+
 //------------------------------------------------------------------------------
 // Test harness validates hw4testbench by connecting it to various functional 
 // or broken register files, and verifying that it correctly identifies each
@@ -139,10 +141,79 @@ output reg		Clk
   end
 
 
+  // Test Case 3: 
+  // Check whether 'enable' is working
+  WriteRegister = 5'd2;
+  WriteData = 32'd20;
+  RegWrite = 0;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if((ReadData1 == 20) || (ReadData2 == 20)) begin
+    dutpassed = 0;
+    $display("Test Case 3 Failed. Enable flag is not working");
+  end
+
+  // Test Case 4: 
+  // Check whether decoder is working properly
+  WriteRegister = 5'd2;
+  WriteData = 32'd20;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  WriteRegister = 5'd3;
+  WriteData = 32'd25;
+  RegWrite = 1;
+  ReadRegister1 = 5'd2;
+  ReadRegister2 = 5'd3;
+  #5 Clk=1; #5 Clk=0;
+
+  if(ReadData1 == 25) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed. Enable flag is not working");
+  end
+
+  // Test Case 5: 
+  // Check whether register zero is working properly
+  WriteRegister = 5'd0;
+  WriteData = 32'd20;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  if(ReadData1 == 20) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed. Enable flag is not working");
+  end
+
+  // Test Case 6: 
+  // Check whether port 2 is working properly
+  WriteRegister = 5'd14;
+  WriteData = 32'd30;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd2;
+  #5 Clk=1; #5 Clk=0;
+
+  WriteRegister = 5'd15;
+  WriteData = 32'd50;
+  RegWrite = 1;
+  ReadRegister1 = 5'd0;
+  ReadRegister2 = 5'd15;
+  #5 Clk=1; #5 Clk=0;
+  if(ReadData2 != 50) begin
+    dutpassed = 0;
+    $display("Test Case 4 Failed. Enable flag is not working");
+  end
+
   // All done!  Wait a moment and signal test completion.
   #5
   endtest = 1;
 
 end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/regfile.v b/regfile.v
index b8a3c74..1f2cc01 100644
--- a/regfile.v
+++ b/regfile.v
@@ -1,3 +1,5 @@
+`include "register.v"
+`include "decoders.v"
 //------------------------------------------------------------------------------
 // MIPS register file
 //   width: 32 bits
@@ -18,10 +20,47 @@ input		RegWrite,	// Enable writing of register when High
 input		Clk		// Clock (Positive Edge Triggered)
 );
 
-  // These two lines are clearly wrong.  They are included to showcase how the 
-  // test harness works. Delete them after you understand the testing process, 
-  // and replace them with your actual code.
-  assign ReadData1 = 42;
-  assign ReadData2 = 42;
+    wire[31:0] decoderOutputs;
+    wire[31:0] input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31;
 
-endmodule
\ No newline at end of file
+    decoder1to32 decoder(decoderOutputs, RegWrite, WriteRegister);
+
+    register32zero zeroRegister(input0, WriteData, decoderOutputs[0], Clk);
+    register32 register1(input1, WriteData, decoderOutputs[1], Clk);
+    register32 register2(input2, WriteData, decoderOutputs[2], Clk);
+    register32 register3(input3, WriteData, decoderOutputs[3], Clk);
+    register32 register4(input4, WriteData, decoderOutputs[4], Clk);
+    register32 register5(input5, WriteData, decoderOutputs[5], Clk);
+    register32 register6(input6, WriteData, decoderOutputs[6], Clk);
+    register32 register7(input7, WriteData, decoderOutputs[7], Clk);
+    register32 register8(input8, WriteData, decoderOutputs[8], Clk);
+    register32 register9(input9, WriteData, decoderOutputs[9], Clk);
+    register32 register10(input10, WriteData, decoderOutputs[10], Clk);
+    register32 register11(input11, WriteData, decoderOutputs[11], Clk);
+    register32 register12(input12, WriteData, decoderOutputs[12], Clk);
+    register32 register13(input13, WriteData, decoderOutputs[13], Clk);
+    register32 register14(input14, WriteData, decoderOutputs[14], Clk);
+    register32 register15(input15, WriteData, decoderOutputs[15], Clk);
+    register32 register16(input16, WriteData, decoderOutputs[16], Clk);
+    register32 register17(input17, WriteData, decoderOutputs[17], Clk);
+    register32 register18(input18, WriteData, decoderOutputs[18], Clk);
+    register32 register19(input19, WriteData, decoderOutputs[19], Clk);
+    register32 register20(input20, WriteData, decoderOutputs[20], Clk);
+    register32 register21(input21, WriteData, decoderOutputs[21], Clk);
+    register32 register22(input22, WriteData, decoderOutputs[22], Clk);
+    register32 register23(input23, WriteData, decoderOutputs[23], Clk);
+    register32 register24(input24, WriteData, decoderOutputs[24], Clk);
+    register32 register25(input25, WriteData, decoderOutputs[25], Clk);
+    register32 register26(input26, WriteData, decoderOutputs[26], Clk);
+    register32 register27(input27, WriteData, decoderOutputs[27], Clk);
+    register32 register28(input28, WriteData, decoderOutputs[28], Clk);
+    register32 register29(input29, WriteData, decoderOutputs[29], Clk);
+    register32 register30(input30, WriteData, decoderOutputs[30], Clk);
+    register32 register31(input31, WriteData, decoderOutputs[31], Clk);
+
+    mux32to1by32 mux1(ReadData1, ReadRegister1, input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31);
+
+    mux32to1by32 mux2(ReadData2, ReadRegister2, input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31);
+
+
+endmodule
diff --git a/register.t.v b/register.t.v
new file mode 100644
index 0000000..143e22e
--- /dev/null
+++ b/register.t.v
@@ -0,0 +1,25 @@
+`timescale 1 ns / 1 ps
+`include "register.v"
+
+module test32BitRegister ();
+    reg[31:0] d;
+    reg wrenable, clk;
+    wire[31:0] q;
+    wire[31:0] zeroQ;
+
+    register32 register (q, d, wrenable, clk);
+    register32zero zeroRegister (zeroQ, d, wrenable, clk);
+
+    initial begin
+    $display("d   wrenable   clk   |    q");
+    d=32'b00000000000000000000000000000001;wrenable=1;clk=1; #1000
+    $display("%b   %b   %b   |   %b", d, wrenable, clk, q);
+
+    d=32'b00000000000000000000000000000011;wrenable=1;clk=0; #1000
+    $display("%b   %b   %b   |   %b", d, wrenable, clk, q);
+
+    $display("testing zero register");
+    d=32'b00000000000000000000000000000001;wrenable=1;clk=1; #1000
+    $display("%b   %b   %b   |   %b", d, wrenable, clk, zeroQ);
+    end
+endmodule
diff --git a/register.v b/register.v
index dc9b8cb..db8ca0d 100644
--- a/register.v
+++ b/register.v
@@ -14,4 +14,86 @@ input		clk
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule
+
+module register32
+(
+output reg[31:0]    q,
+input[31:0]         d,
+input               wrenable,
+input               clk
+);
+
+    always @(posedge clk) begin
+        if(wrenable) begin
+            q = d;
+        end
+    end
+
+endmodule
+
+module register32zero
+(
+output wire[31:0]    q,
+input[31:0]         d,
+input               wrenable,
+input               clk
+);
+
+    assign q = 32'b00000000000000000000000000000000;
+
+endmodule
+
+module mux32to1by1
+(
+output      out,
+input[3:0]  address,
+input[31:0] inputs
+);
+
+    assign out = inputs[address];
+
+endmodule
+
+module mux32to1by32
+(
+output[31:0]    out,
+input[4:0]      address,
+input[31:0]     input0, input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31
+);
+
+    wire[31:0] mux[31:0];
+    assign mux[0] = input0;
+    assign mux[1] = input1;
+    assign mux[2] = input2;
+    assign mux[3] = input3;
+    assign mux[4] = input4;
+    assign mux[5] = input5;
+    assign mux[6] = input6;
+    assign mux[7] = input7;
+    assign mux[8] = input8;
+    assign mux[9] = input9;
+    assign mux[10] = input10;
+    assign mux[11] = input11;
+    assign mux[12] = input12;
+    assign mux[13] = input13;
+    assign mux[14] = input14;
+    assign mux[15] = input15;
+    assign mux[16] = input16;
+    assign mux[17] = input17;
+    assign mux[18] = input18;
+    assign mux[19] = input19;
+    assign mux[20] = input20;
+    assign mux[21] = input21;
+    assign mux[22] = input22;
+    assign mux[23] = input23;
+    assign mux[24] = input24;
+    assign mux[25] = input25;
+    assign mux[26] = input26;
+    assign mux[27] = input27;
+    assign mux[28] = input28;
+    assign mux[29] = input29;
+    assign mux[30] = input30;
+    assign mux[31] = input31;
+    assign out = mux[address];
+endmodule