diff --git a/Lab0 Writeup.pdf b/Lab0 Writeup.pdf
new file mode 100644
index 0000000..3f6b1cf
Binary files /dev/null and b/Lab0 Writeup.pdf differ
diff --git a/adder.t.v b/adder.t.v
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--- /dev/null
+++ b/adder.t.v
@@ -0,0 +1,55 @@
+// Adder testbench
+`timescale 1 ns / 1 ps
+`include "adder.v"
+
+// Test a subset of the possible 2^8 inputs of the adder.
+module testFullAdder4bit();
+    reg [3:0] a;
+    reg [3:0] b;
+    wire [3:0] sum;
+    wire carryout, overflow;
+
+    FullAdder4bit adder (sum[3:0], carryout, overflow, a[3:0], b[3:0]);
+
+    initial begin
+    $dumpfile("adder.vcd");
+    $dumpvars();
+
+    // The 16 chosen test cases that match the inputs to the FPGA board.
+    $display(" A    B   | Cout Overflow   S  | Expected Output");
+    a='b0000;b='b0000; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 0000 ", a, b, carryout, overflow, sum);
+    a='b1111;b='b1111; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 1110 ", a, b, carryout, overflow, sum);
+    a='b1111;b='b0000; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 1111 ", a, b, carryout, overflow, sum);
+    a='b0010;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 0110 ", a, b, carryout, overflow, sum);
+    a='b1110;b='b1100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 1010 ", a, b, carryout, overflow, sum);
+    a='b0010;b='b1100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 1110 ", a, b, carryout, overflow, sum);
+    a='b0101;b='b0011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1000 ", a, b, carryout, overflow, sum);
+    a='b1110;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 0010 ", a, b, carryout, overflow, sum);
+    a='b1000;b='b0001; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 1001 ", a, b, carryout, overflow, sum);
+    a='b0101;b='b0010; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 0 S: 0111 ", a, b, carryout, overflow, sum);
+    a='b1001;b='b1110; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 1 S: 0111 ", a, b, carryout, overflow, sum);
+    a='b1101;b='b1011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 0 S: 1000 ", a, b, carryout, overflow, sum);
+    a='b0111;b='b0011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1010 ", a, b, carryout, overflow, sum);
+    a='b1100;b='b1011; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 1 Overflow: 1 S: 0111 ", a, b, carryout, overflow, sum);
+    a='b0101;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1001 ", a, b, carryout, overflow, sum);
+    a='b0110;b='b0100; #1000
+    $display("%b %b |   %b     %b     %b | Cout: 0 Overflow: 1 S: 1010 ", a, b, carryout, overflow, sum);
+    
+    $finish();
+    end
+endmodule
diff --git a/adder.v b/adder.v
new file mode 100644
index 0000000..7e9ae35
--- /dev/null
+++ b/adder.v
@@ -0,0 +1,57 @@
+`define AND and #50
+`define XOR xor #50
+`define OR or #50
+
+// Implementation of a 1-bit full adder.
+module FullAdder1bit
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    wire cout1;
+    wire cout2;
+    wire sumAB;
+
+    `XOR AxorB(sumAB, a, b);
+    `XOR sumABxorCin(sum, sumAB, carryin);
+
+    `AND AandB(cout1, a, b);
+    `AND sumABandCin(cout2, sumAB, carryin);
+
+    `OR orcarries(carryout, cout1, cout2);
+endmodule
+
+// Implementation of a 4-bit full adder. Four 1-bit full adders
+// are linked together in order to add 4-bit inputs. Each 1-bit 
+// adder outputs a single bit of the sum, and the carry out of 
+// each adder becomes the carryin input of the adder for the 
+// next significant bit.
+module FullAdder4bit
+(
+  output[3:0] sum,  // 2's complement sum of a and b
+  output carryout,  // Carry out of the summation of a and b
+  output overflow,  // True if the calculation resulted in an overflow
+  input[3:0] a,     // First operand in 2's complement format
+  input[3:0] b      // Second operand in 2's complement format
+);
+    wire carryout0;
+    wire carryout1;
+    wire carryout2;
+
+    // The carry in of this adder is always set to 0.
+    FullAdder1bit adder0 (sum[0], carryout0, a[0], b[0], 1'b0);
+
+    FullAdder1bit adder1 (sum[1], carryout1, a[1], b[1], carryout0);
+
+    FullAdder1bit adder2 (sum[2], carryout2, a[2], b[2], carryout1);
+
+    FullAdder1bit adder3 (sum[3], carryout, a[3], b[3], carryout2);
+
+    // An overflow occurs when the final carryout is not equal to the 
+    // carryin of the most significant bit.
+    `XOR oveflowdetection(overflow, carryout, carryout2);
+
+endmodule
\ No newline at end of file
diff --git a/adder.vcd b/adder.vcd
new file mode 100644
index 0000000..2b7e87a
--- /dev/null
+++ b/adder.vcd
@@ -0,0 +1,608 @@
+$date
+	Tue Sep 26 15:54:01 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testFullAdder4bit $end
+$var wire 4 ! sum [3:0] $end
+$var wire 1 " overflow $end
+$var wire 1 # carryout $end
+$var reg 4 $ a [3:0] $end
+$var reg 4 % b [3:0] $end
+$scope module adder $end
+$var wire 4 & a [3:0] $end
+$var wire 4 ' b [3:0] $end
+$var wire 1 " overflow $end
+$var wire 4 ( sum [3:0] $end
+$var wire 1 ) carryout2 $end
+$var wire 1 * carryout1 $end
+$var wire 1 + carryout0 $end
+$var wire 1 # carryout $end
+$scope module adder0 $end
+$var wire 1 , a $end
+$var wire 1 - b $end
+$var wire 1 . carryin $end
+$var wire 1 + carryout $end
+$var wire 1 / cout1 $end
+$var wire 1 0 cout2 $end
+$var wire 1 1 sum $end
+$var wire 1 2 sumAB $end
+$upscope $end
+$scope module adder1 $end
+$var wire 1 3 a $end
+$var wire 1 4 b $end
+$var wire 1 + carryin $end
+$var wire 1 * carryout $end
+$var wire 1 5 cout1 $end
+$var wire 1 6 cout2 $end
+$var wire 1 7 sum $end
+$var wire 1 8 sumAB $end
+$upscope $end
+$scope module adder2 $end
+$var wire 1 9 a $end
+$var wire 1 : b $end
+$var wire 1 * carryin $end
+$var wire 1 ) carryout $end
+$var wire 1 ; cout1 $end
+$var wire 1 < cout2 $end
+$var wire 1 = sum $end
+$var wire 1 > sumAB $end
+$upscope $end
+$scope module adder3 $end
+$var wire 1 ? a $end
+$var wire 1 @ b $end
+$var wire 1 ) carryin $end
+$var wire 1 # carryout $end
+$var wire 1 A cout1 $end
+$var wire 1 B cout2 $end
+$var wire 1 C sum $end
+$var wire 1 D sumAB $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+xD
+xC
+xB
+xA
+0@
+0?
+x>
+x=
+x<
+x;
+0:
+09
+x8
+x7
+x6
+x5
+04
+03
+x2
+x1
+x0
+x/
+0.
+0-
+0,
+x+
+x*
+x)
+bx (
+b0 '
+b0 &
+b0 %
+b0 $
+x#
+x"
+bx !
+$end
+#50000
+02
+0/
+08
+05
+0>
+0;
+0D
+0A
+00
+#100000
+bx0 !
+bx0 (
+01
+06
+0<
+0B
+0+
+#150000
+0*
+0)
+0#
+bx00 !
+bx00 (
+07
+#200000
+0=
+b0 !
+b0 (
+0C
+0"
+#1000000
+1-
+14
+1:
+1@
+1,
+13
+19
+1?
+b1111 %
+b1111 '
+b1111 $
+b1111 &
+#1050000
+1/
+15
+1;
+1A
+#1100000
+1+
+1*
+1)
+1#
+#1150000
+17
+1=
+b1110 !
+b1110 (
+1C
+#2000000
+0-
+04
+0:
+0@
+b0 %
+b0 '
+#2050000
+12
+0/
+18
+05
+1>
+0;
+1D
+0A
+#2100000
+11
+0+
+07
+16
+0*
+0=
+1<
+0)
+b1 !
+b1 (
+0C
+1B
+0#
+#2150000
+17
+06
+1*
+1=
+0<
+1)
+b1111 !
+b1111 (
+1C
+0B
+1#
+#2200000
+0*
+0=
+1<
+0)
+b11 !
+b11 (
+0C
+1B
+0#
+#2250000
+1=
+0<
+1)
+b1111 !
+b1111 (
+1C
+0B
+1#
+#2300000
+0)
+b111 !
+b111 (
+0C
+1B
+0#
+#2350000
+b1111 !
+b1111 (
+1C
+0B
+1#
+#2400000
+0#
+1"
+#2450000
+0"
+#3000000
+1:
+0,
+09
+0?
+b100 %
+b100 '
+b10 $
+b10 &
+#3050000
+02
+0D
+#3100000
+01
+b110 !
+b110 (
+0C
+#4000000
+1@
+19
+1?
+b1100 %
+b1100 '
+b1110 $
+b1110 &
+#4050000
+0>
+1;
+1A
+#4100000
+b10 !
+b10 (
+0=
+1)
+1#
+#4150000
+b1010 !
+b1010 (
+1C
+#5000000
+09
+0?
+b10 $
+b10 &
+#5050000
+1>
+0;
+1D
+0A
+#5100000
+1=
+0)
+b110 !
+b110 (
+0C
+1B
+0#
+#5150000
+b1110 !
+b1110 (
+1C
+0B
+1#
+#5200000
+0#
+1"
+#5250000
+0"
+#6000000
+1-
+14
+0:
+0@
+1,
+03
+19
+b11 %
+b11 '
+b101 $
+b101 &
+#6050000
+0D
+1/
+#6100000
+b110 !
+b110 (
+0C
+1+
+#6150000
+b100 !
+b100 (
+07
+16
+#6200000
+1*
+#6250000
+b0 !
+b0 (
+0=
+1<
+#6300000
+1)
+#6350000
+b1000 !
+b1000 (
+1C
+1"
+#7000000
+0-
+04
+1:
+0,
+13
+1?
+b100 %
+b100 '
+b1110 $
+b1110 &
+#7050000
+0>
+1;
+0/
+1D
+#7100000
+1=
+0<
+0+
+b100 !
+b100 (
+0C
+1B
+#7150000
+b110 !
+b110 (
+17
+06
+1#
+#7200000
+0*
+0"
+#7250000
+b10 !
+b10 (
+0=
+#8000000
+1-
+0:
+03
+09
+b1 %
+b1 '
+b1000 $
+b1000 &
+#8050000
+12
+08
+0;
+#8100000
+11
+b1 !
+b1 (
+07
+0)
+#8150000
+b1001 !
+b1001 (
+1C
+0B
+1"
+#8200000
+0#
+#8250000
+0"
+#9000000
+0-
+14
+1,
+19
+0?
+b10 %
+b10 '
+b101 $
+b101 &
+#9050000
+18
+1>
+0D
+#9100000
+17
+1=
+b111 !
+b111 (
+0C
+#10000000
+1:
+1@
+09
+1?
+b1110 %
+b1110 '
+b1001 $
+b1001 &
+#10050000
+1A
+#10100000
+1#
+#10150000
+1"
+#11000000
+1-
+0:
+19
+b1011 %
+b1011 '
+b1101 $
+b1101 &
+#11050000
+02
+1/
+#11100000
+b110 !
+b110 (
+01
+1+
+#11150000
+b100 !
+b100 (
+07
+16
+#11200000
+1*
+#11250000
+b0 !
+b0 (
+0=
+1<
+#11300000
+1)
+#11350000
+b1000 !
+b1000 (
+1C
+0"
+#12000000
+0@
+13
+0?
+b11 %
+b11 '
+b111 $
+b111 &
+#12050000
+08
+15
+0A
+#12100000
+b1010 !
+b1010 (
+17
+06
+0#
+#12150000
+1"
+#13000000
+1@
+0,
+03
+1?
+b1011 %
+b1011 '
+b1100 $
+b1100 &
+#13050000
+12
+0/
+18
+05
+1A
+#13100000
+11
+0+
+b1001 !
+b1001 (
+07
+16
+0*
+1#
+#13150000
+17
+06
+1*
+b1111 !
+b1111 (
+1=
+0<
+0"
+#13200000
+0*
+b1011 !
+b1011 (
+0=
+1<
+0)
+#13250000
+1=
+0<
+1)
+b111 !
+b111 (
+0C
+1"
+#13300000
+0)
+b1111 !
+b1111 (
+1C
+0"
+#13350000
+b111 !
+b111 (
+0C
+1"
+#14000000
+0-
+04
+1:
+0@
+1,
+0?
+b100 %
+b100 '
+b101 $
+b101 &
+#14050000
+08
+0>
+1;
+0A
+#14100000
+07
+b1 !
+b1 (
+0=
+1)
+0#
+#14150000
+b1001 !
+b1001 (
+1C
+#15000000
+0,
+13
+b110 $
+b110 &
+#15050000
+02
+18
+#15100000
+01
+b1010 !
+b1010 (
+17
+#16000000
diff --git a/waveforms.pdf b/waveforms.pdf
new file mode 100644
index 0000000..06221f5
Binary files /dev/null and b/waveforms.pdf differ