diff --git a/4badder b/4badder new file mode 100755 index 0000000..0be1b7a --- /dev/null +++ b/4badder @@ -0,0 +1,302 @@ +#! /usr/local/bin/vvp +:ivl_version "11.0 (devel)" "(s20150603-477-gc855b89)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "vhdl_textio"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x2720c40 .scope module, "test4BitFullAdder" "test4BitFullAdder" 2 4; + .timescale -9 -12; +v0x2751770_0 .var "a", 3 0; +v0x2751850_0 .var "b", 3 0; +v0x27518f0_0 .net "carryout", 0 0, L_0x2753de0; 1 drivers +v0x27519e0_0 .net "carryout2", 0 0, L_0x2753490; 1 drivers +v0x2751a80_0 .net "overflow", 0 0, L_0x2754370; 1 drivers +v0x2751b70_0 .net "sum", 3 0, L_0x2753f40; 1 drivers +S_0x271f1f0 .scope module, "adder" "FullAdder4bit" 2 12, 3 27 0, S_0x2720c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 4 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "carryout2" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 4 "a" + .port_info 5 /INPUT 4 "b" +L_0x2754370/d .functor XOR 1, L_0x2753490, L_0x2753de0, C4<0>, C4<0>; +L_0x2754370 .delay 1 (50000,50000,50000) L_0x2754370/d; +v0x2750f40_0 .net "a", 3 0, v0x2751770_0; 1 drivers +v0x2751040_0 .net "b", 3 0, v0x2751850_0; 1 drivers +v0x2751120_0 .net "carryout", 0 0, L_0x2753de0; alias, 1 drivers +v0x27511f0_0 .net "carryout0", 0 0, L_0x2752240; 1 drivers +v0x27512e0_0 .net "carryout1", 0 0, L_0x2752bb0; 1 drivers +v0x2751420_0 .net "carryout2", 0 0, L_0x2753490; alias, 1 drivers +v0x2751510_0 .net "overflow", 0 0, L_0x2754370; alias, 1 drivers +v0x27515b0_0 .net "sum", 3 0, L_0x2753f40; alias, 1 drivers +L_0x27523f0 .part v0x2751770_0, 0, 1; +L_0x2752550 .part v0x2751850_0, 0, 1; +L_0x2752d10 .part v0x2751770_0, 1, 1; +L_0x2752e70 .part v0x2751850_0, 1, 1; +L_0x2753630 .part v0x2751770_0, 2, 1; +L_0x2753820 .part v0x2751850_0, 2, 1; +L_0x2753f40 .concat8 [ 1 1 1 1], L_0x2751d30, L_0x27526b0, L_0x2752f90, L_0x27539c0; +L_0x27541e0 .part v0x2751770_0, 3, 1; +L_0x27542d0 .part v0x2751850_0, 3, 1; +S_0x271c0b0 .scope module, "a0" "structFullAdder" 3 39, 3 8 0, S_0x271f1f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x2751c10/d .functor XOR 1, L_0x27523f0, L_0x2752550, C4<0>, C4<0>; +L_0x2751c10 .delay 1 (50000,50000,50000) L_0x2751c10/d; +L_0x7f2d2c679018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2751d30/d .functor XOR 1, L_0x2751c10, L_0x7f2d2c679018, C4<0>, C4<0>; +L_0x2751d30 .delay 1 (50000,50000,50000) L_0x2751d30/d; +L_0x2751ee0/d .functor AND 1, L_0x27523f0, L_0x2752550, C4<1>, C4<1>; +L_0x2751ee0 .delay 1 (50000,50000,50000) L_0x2751ee0/d; +L_0x27520e0/d .functor AND 1, L_0x2751c10, L_0x7f2d2c679018, C4<1>, C4<1>; +L_0x27520e0 .delay 1 (50000,50000,50000) L_0x27520e0/d; +L_0x2752240/d .functor OR 1, L_0x27520e0, L_0x2751ee0, C4<0>, C4<0>; +L_0x2752240 .delay 1 (50000,50000,50000) L_0x2752240/d; +v0x2720970_0 .net "AandB", 0 0, L_0x2751ee0; 1 drivers +v0x274eca0_0 .net "AxorB", 0 0, L_0x2751c10; 1 drivers +v0x274ed60_0 .net "AxorBandCarryIn", 0 0, L_0x27520e0; 1 drivers +v0x274ee30_0 .net "a", 0 0, L_0x27523f0; 1 drivers +v0x274eef0_0 .net "b", 0 0, L_0x2752550; 1 drivers +v0x274f000_0 .net "carryin", 0 0, L_0x7f2d2c679018; 1 drivers +v0x274f0c0_0 .net "carryout", 0 0, L_0x2752240; alias, 1 drivers +v0x274f180_0 .net "sum", 0 0, L_0x2751d30; 1 drivers +S_0x274f2e0 .scope module, "a1" "structFullAdder" 3 40, 3 8 0, S_0x271f1f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x2752640/d .functor XOR 1, L_0x2752d10, L_0x2752e70, C4<0>, C4<0>; +L_0x2752640 .delay 1 (50000,50000,50000) L_0x2752640/d; +L_0x27526b0/d .functor XOR 1, L_0x2752640, L_0x2752240, C4<0>, C4<0>; +L_0x27526b0 .delay 1 (50000,50000,50000) L_0x27526b0/d; +L_0x27528a0/d .functor AND 1, L_0x2752d10, L_0x2752e70, C4<1>, C4<1>; +L_0x27528a0 .delay 1 (50000,50000,50000) L_0x27528a0/d; +L_0x2752a50/d .functor AND 1, L_0x2752640, L_0x2752240, C4<1>, C4<1>; +L_0x2752a50 .delay 1 (50000,50000,50000) L_0x2752a50/d; +L_0x2752bb0/d .functor OR 1, L_0x2752a50, L_0x27528a0, C4<0>, C4<0>; +L_0x2752bb0 .delay 1 (50000,50000,50000) L_0x2752bb0/d; +v0x274f560_0 .net "AandB", 0 0, L_0x27528a0; 1 drivers +v0x274f620_0 .net "AxorB", 0 0, L_0x2752640; 1 drivers +v0x274f6e0_0 .net "AxorBandCarryIn", 0 0, L_0x2752a50; 1 drivers +v0x274f7b0_0 .net "a", 0 0, L_0x2752d10; 1 drivers +v0x274f870_0 .net "b", 0 0, L_0x2752e70; 1 drivers +v0x274f980_0 .net "carryin", 0 0, L_0x2752240; alias, 1 drivers +v0x274fa20_0 .net "carryout", 0 0, L_0x2752bb0; alias, 1 drivers +v0x274fac0_0 .net "sum", 0 0, L_0x27526b0; 1 drivers +S_0x274fc50 .scope module, "a2" "structFullAdder" 3 41, 3 8 0, S_0x271f1f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x2752db0/d .functor XOR 1, L_0x2753630, L_0x2753820, C4<0>, C4<0>; +L_0x2752db0 .delay 1 (50000,50000,50000) L_0x2752db0/d; +L_0x2752f90/d .functor XOR 1, L_0x2752db0, L_0x2752bb0, C4<0>, C4<0>; +L_0x2752f90 .delay 1 (50000,50000,50000) L_0x2752f90/d; +L_0x2753180/d .functor AND 1, L_0x2753630, L_0x2753820, C4<1>, C4<1>; +L_0x2753180 .delay 1 (50000,50000,50000) L_0x2753180/d; +L_0x2753330/d .functor AND 1, L_0x2752db0, L_0x2752bb0, C4<1>, C4<1>; +L_0x2753330 .delay 1 (50000,50000,50000) L_0x2753330/d; +L_0x2753490/d .functor OR 1, L_0x2753330, L_0x2753180, C4<0>, C4<0>; +L_0x2753490 .delay 1 (50000,50000,50000) L_0x2753490/d; +v0x274fee0_0 .net "AandB", 0 0, L_0x2753180; 1 drivers +v0x274ffa0_0 .net "AxorB", 0 0, L_0x2752db0; 1 drivers +v0x2750060_0 .net "AxorBandCarryIn", 0 0, L_0x2753330; 1 drivers +v0x2750130_0 .net "a", 0 0, L_0x2753630; 1 drivers +v0x27501f0_0 .net "b", 0 0, L_0x2753820; 1 drivers +v0x2750300_0 .net "carryin", 0 0, L_0x2752bb0; alias, 1 drivers +v0x27503a0_0 .net "carryout", 0 0, L_0x2753490; alias, 1 drivers +v0x2750440_0 .net "sum", 0 0, L_0x2752f90; 1 drivers +S_0x27505d0 .scope module, "a3" "structFullAdder" 3 42, 3 8 0, S_0x271f1f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x2753950/d .functor XOR 1, L_0x27541e0, L_0x27542d0, C4<0>, C4<0>; +L_0x2753950 .delay 1 (50000,50000,50000) L_0x2753950/d; +L_0x27539c0/d .functor XOR 1, L_0x2753950, L_0x2753490, C4<0>, C4<0>; +L_0x27539c0 .delay 1 (50000,50000,50000) L_0x27539c0/d; +L_0x2753ad0/d .functor AND 1, L_0x27541e0, L_0x27542d0, C4<1>, C4<1>; +L_0x2753ad0 .delay 1 (50000,50000,50000) L_0x2753ad0/d; +L_0x2753c80/d .functor AND 1, L_0x2753950, L_0x2753490, C4<1>, C4<1>; +L_0x2753c80 .delay 1 (50000,50000,50000) L_0x2753c80/d; +L_0x2753de0/d .functor OR 1, L_0x2753c80, L_0x2753ad0, C4<0>, C4<0>; +L_0x2753de0 .delay 1 (50000,50000,50000) L_0x2753de0/d; +v0x2750830_0 .net "AandB", 0 0, L_0x2753ad0; 1 drivers +v0x2750910_0 .net "AxorB", 0 0, L_0x2753950; 1 drivers +v0x27509d0_0 .net "AxorBandCarryIn", 0 0, L_0x2753c80; 1 drivers +v0x2750aa0_0 .net "a", 0 0, L_0x27541e0; 1 drivers +v0x2750b60_0 .net "b", 0 0, L_0x27542d0; 1 drivers +v0x2750c70_0 .net "carryin", 0 0, L_0x2753490; alias, 1 drivers +v0x2750d10_0 .net "carryout", 0 0, L_0x2753de0; alias, 1 drivers +v0x2750db0_0 .net "sum", 0 0, L_0x27539c0; 1 drivers + .scope S_0x2720c40; +T_0 ; + %vpi_call 2 15 "$dumpfile", "fulladder.vcd" {0 0 0}; + %vpi_call 2 16 "$dumpvars", 32'sb00000000000000000000000000000000, v0x2751770_0, v0x2751850_0, v0x2751b70_0, v0x27518f0_0, v0x27519e0_0, v0x2751a80_0 {0 0 0}; + %vpi_call 2 19 "$display", " a | b | S C2 | COut | OverFlow | Sum | ECout | EOvrflow" {0 0 0}; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 23 "$display", " %d | %d | %d %b | %b | %b | 0 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 15, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 15, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 27 "$display", " %d | %d | %d %b | %b | %b | -2 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 31 "$display", " %d | %d | %d %b | %b | %b | 2 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 7, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 9, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 35 "$display", " %d | %d | %d %b | %b | %b | 0 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 6, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 14, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 39 "$display", " %d | %d | %d %b | %b | %b | 4 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 6, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 43 "$display", " %d | %d | %d %b | %b | %b |11(-5)| 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 9, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 47 "$display", " %d | %d | %d %b | %b | %b | -2 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 7, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 3, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 51 "$display", " %d | %d | %d %b | %b | %b |10(-6)| 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 11, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 11, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 55 "$display", " %d | %d | %d %b | %b | %b |-10(6)| 1 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 59 "$display", " %d | %d | %d %b | %b | %b |-16(0)| 1 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 7, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 63 "$display", " %d | %d | %d %b | %b | %b | -1 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 7, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 7, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 67 "$display", " %d | %d | %d %b | %b | %b |14(-2)| 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 71 "$display", " %d | %d | %d %b | %b | %b | 7 | 0 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 3, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 75 "$display", " %d | %d | %d %b | %b | %b |8(-8) | 0 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 11, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 13, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 79 "$display", " %d | %d | %d %b | %b | %b | -8 | 1 | 0 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %pushi/vec4 11, 0, 4; + %store/vec4 v0x2751770_0, 0, 4; + %pushi/vec4 12, 0, 4; + %store/vec4 v0x2751850_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0x2751770_0; + %load/vec4 v0x2751850_0; + %load/vec4 v0x2751b70_0; + %vpi_call 2 83 "$display", " %d | %d | %d %b | %b | %b |-9(7) | 1 | 1 ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0x27519e0_0, v0x27518f0_0, v0x2751a80_0 {3 0 0}; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "adder.t.v"; + "./adder.v"; diff --git a/4bitFullAdder.v b/4bitFullAdder.v new file mode 100644 index 0000000..7f3091f --- /dev/null +++ b/4bitFullAdder.v @@ -0,0 +1,33 @@ +`timescale 1 ns / 1 ps +`include "adder.v" + +module test4BitFullAdder(); + reg[3:0] a; + reg[3:0] b; + wire[3:0] sum; + wire carryout; + wire overflow; + integer i; + integer j; + + FullAdder4bit adder(sum, carryout, overflow, a, b); + + initial begin + $dumpfile("fulladder.vcd"); + $dumpvars(0, a[3:0], b[3:0], sum[3:0], carryout, overflow); + + $display(" a | b | S | COut | OverFlow"); + for(i = -8; i < 8; i = i + 1) + begin + for(j = -8; j < 8; j = j + 1) + begin + + a = i; + b = j; + #1000 + $display(" %d | %d | %d | %b | %b ", $signed(a), $signed(b), $signed(sum), carryout, overflow); + end + end + + end +endmodule diff --git a/Comp_Arch.pdf b/Comp_Arch.pdf new file mode 100644 index 0000000..bc68bc5 Binary files /dev/null and b/Comp_Arch.pdf differ diff --git a/ZYBO_Master.xdc b/ZYBO_Master.xdc new file mode 100755 index 0000000..a66f9ee --- /dev/null +++ b/ZYBO_Master.xdc @@ -0,0 +1,146 @@ +## This file is a general .xdc for the ZYBO Rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used signals according to the project + + +##Clock signal +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; + + +##Switches +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 + + +##Buttons +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 + + +##LEDs +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 + + +##I2S Audio Codec +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC + + +##Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B + + +##HDMI Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA + + +##Pmod Header JA (XADC) +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N + + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N + + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N + + +##Pmod Header JE +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 + + +##USB-OTG overcurrent detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC + + +##VGA Connector +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS diff --git a/adder b/adder new file mode 100644 index 0000000..3a22d50 --- /dev/null +++ b/adder @@ -0,0 +1,192 @@ +#! c:/iverilog-x64/bin/vvp +:ivl_version "10.1 (stable)" "(v10_1_1)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0000000000bfe600 .scope module, "test4BitFullAdder" "test4BitFullAdder" 2 4; + .timescale -9 -12; +v0000000000c57060_0 .var "a", 3 0; +v0000000000c57600_0 .var "b", 3 0; +v0000000000c576a0_0 .net "carryout", 0 0, L_0000000000ce8e00; 1 drivers +v0000000000c57b00_0 .net "carryout2", 0 0, L_0000000000ce8150; 1 drivers +v0000000000c57ba0_0 .var/i "i", 31 0; +v0000000000c57c40_0 .var/i "j", 31 0; +v0000000000c57ce0_0 .net "overflow", 0 0, L_0000000000ce81c0; 1 drivers +v0000000000c56700_0 .net "sum", 3 0, L_0000000000c57f60; 1 drivers +S_0000000000c00df0 .scope module, "adder" "FullAdder4bit" 2 14, 3 39 0, S_0000000000bfe600; + .timescale -9 -12; + .port_info 0 /OUTPUT 4 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "carryout2" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 4 "a" + .port_info 5 /INPUT 4 "b" +L_0000000000ce81c0/d .functor XOR 1, L_0000000000ce8150, L_0000000000ce8e00, C4<0>, C4<0>; +L_0000000000ce81c0 .delay 1 (50000,50000,50000) L_0000000000ce81c0/d; +v0000000000c56160_0 .net "a", 3 0, v0000000000c57060_0; 1 drivers +v0000000000c56a20_0 .net "b", 3 0, v0000000000c57600_0; 1 drivers +v0000000000c56480_0 .net "carryout", 0 0, L_0000000000ce8e00; alias, 1 drivers +v0000000000c57a60_0 .net "carryout0", 0 0, L_0000000000bfb200; 1 drivers +v0000000000c56ac0_0 .net "carryout1", 0 0, L_0000000000ce8a80; 1 drivers +v0000000000c577e0_0 .net "carryout2", 0 0, L_0000000000ce8150; alias, 1 drivers +v0000000000c57560_0 .net "overflow", 0 0, L_0000000000ce81c0; alias, 1 drivers +v0000000000c56fc0_0 .net "sum", 3 0, L_0000000000c57f60; alias, 1 drivers +L_0000000000c56b60 .part v0000000000c57060_0, 0, 1; +L_0000000000c56ca0 .part v0000000000c57600_0, 0, 1; +L_0000000000c57e20 .part v0000000000c57060_0, 1, 1; +L_0000000000c57100 .part v0000000000c57600_0, 1, 1; +L_0000000000c57ec0 .part v0000000000c57060_0, 2, 1; +L_0000000000c56340 .part v0000000000c57600_0, 2, 1; +L_0000000000c57f60 .concat8 [ 1 1 1 1], L_0000000000bfb3c0, L_0000000000bfb270, L_0000000000ce8af0, L_0000000000ce8310; +L_0000000000c562a0 .part v0000000000c57060_0, 3, 1; +L_0000000000c560c0 .part v0000000000c57600_0, 3, 1; +S_000000000127e800 .scope module, "a0" "structFullAdder" 3 51, 3 20 0, S_0000000000c00df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000bfb0b0/d .functor XOR 1, L_0000000000c56b60, L_0000000000c56ca0, C4<0>, C4<0>; +L_0000000000bfb0b0 .delay 1 (50000,50000,50000) L_0000000000bfb0b0/d; +L_0000000000ca0088 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0000000000bfb3c0/d .functor XOR 1, L_0000000000bfb0b0, L_0000000000ca0088, C4<0>, C4<0>; +L_0000000000bfb3c0 .delay 1 (50000,50000,50000) L_0000000000bfb3c0/d; +L_0000000000bfb430/d .functor AND 1, L_0000000000c56b60, L_0000000000c56ca0, C4<1>, C4<1>; +L_0000000000bfb430 .delay 1 (50000,50000,50000) L_0000000000bfb430/d; +L_0000000000bfb190/d .functor AND 1, L_0000000000bfb0b0, L_0000000000ca0088, C4<1>, C4<1>; +L_0000000000bfb190 .delay 1 (50000,50000,50000) L_0000000000bfb190/d; +L_0000000000bfb200/d .functor OR 1, L_0000000000bfb190, L_0000000000bfb430, C4<0>, C4<0>; +L_0000000000bfb200 .delay 1 (50000,50000,50000) L_0000000000bfb200/d; +v0000000000bf8370_0 .net "AandB", 0 0, L_0000000000bfb430; 1 drivers +v0000000000bf8730_0 .net "AxorB", 0 0, L_0000000000bfb0b0; 1 drivers +v0000000000bf8870_0 .net "AxorBandCarryIn", 0 0, L_0000000000bfb190; 1 drivers +v0000000000bf89b0_0 .net "a", 0 0, L_0000000000c56b60; 1 drivers +v0000000000bf87d0_0 .net "b", 0 0, L_0000000000c56ca0; 1 drivers +v0000000000bf8910_0 .net "carryin", 0 0, L_0000000000ca0088; 1 drivers +v0000000000bf7f10_0 .net "carryout", 0 0, L_0000000000bfb200; alias, 1 drivers +v0000000000bf7bf0_0 .net "sum", 0 0, L_0000000000bfb3c0; 1 drivers +S_000000000127e980 .scope module, "a1" "structFullAdder" 3 52, 3 20 0, S_0000000000c00df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000bfb4a0/d .functor XOR 1, L_0000000000c57e20, L_0000000000c57100, C4<0>, C4<0>; +L_0000000000bfb4a0 .delay 1 (50000,50000,50000) L_0000000000bfb4a0/d; +L_0000000000bfb270/d .functor XOR 1, L_0000000000bfb4a0, L_0000000000bfb200, C4<0>, C4<0>; +L_0000000000bfb270 .delay 1 (50000,50000,50000) L_0000000000bfb270/d; +L_0000000000bfae10/d .functor AND 1, L_0000000000c57e20, L_0000000000c57100, C4<1>, C4<1>; +L_0000000000bfae10 .delay 1 (50000,50000,50000) L_0000000000bfae10/d; +L_0000000000ce82a0/d .functor AND 1, L_0000000000bfb4a0, L_0000000000bfb200, C4<1>, C4<1>; +L_0000000000ce82a0 .delay 1 (50000,50000,50000) L_0000000000ce82a0/d; +L_0000000000ce8a80/d .functor OR 1, L_0000000000ce82a0, L_0000000000bfae10, C4<0>, C4<0>; +L_0000000000ce8a80 .delay 1 (50000,50000,50000) L_0000000000ce8a80/d; +v0000000000bf7c90_0 .net "AandB", 0 0, L_0000000000bfae10; 1 drivers +v0000000000bf7fb0_0 .net "AxorB", 0 0, L_0000000000bfb4a0; 1 drivers +v0000000000c57240_0 .net "AxorBandCarryIn", 0 0, L_0000000000ce82a0; 1 drivers +v0000000000c56c00_0 .net "a", 0 0, L_0000000000c57e20; 1 drivers +v0000000000c572e0_0 .net "b", 0 0, L_0000000000c57100; 1 drivers +v0000000000c56de0_0 .net "carryin", 0 0, L_0000000000bfb200; alias, 1 drivers +v0000000000c57920_0 .net "carryout", 0 0, L_0000000000ce8a80; alias, 1 drivers +v0000000000c57380_0 .net "sum", 0 0, L_0000000000bfb270; 1 drivers +S_00000000012766b0 .scope module, "a2" "structFullAdder" 3 53, 3 20 0, S_0000000000c00df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000ce8540/d .functor XOR 1, L_0000000000c57ec0, L_0000000000c56340, C4<0>, C4<0>; +L_0000000000ce8540 .delay 1 (50000,50000,50000) L_0000000000ce8540/d; +L_0000000000ce8af0/d .functor XOR 1, L_0000000000ce8540, L_0000000000ce8a80, C4<0>, C4<0>; +L_0000000000ce8af0 .delay 1 (50000,50000,50000) L_0000000000ce8af0/d; +L_0000000000ce8b60/d .functor AND 1, L_0000000000c57ec0, L_0000000000c56340, C4<1>, C4<1>; +L_0000000000ce8b60 .delay 1 (50000,50000,50000) L_0000000000ce8b60/d; +L_0000000000ce8ee0/d .functor AND 1, L_0000000000ce8540, L_0000000000ce8a80, C4<1>, C4<1>; +L_0000000000ce8ee0 .delay 1 (50000,50000,50000) L_0000000000ce8ee0/d; +L_0000000000ce8150/d .functor OR 1, L_0000000000ce8ee0, L_0000000000ce8b60, C4<0>, C4<0>; +L_0000000000ce8150 .delay 1 (50000,50000,50000) L_0000000000ce8150/d; +v0000000000c57d80_0 .net "AandB", 0 0, L_0000000000ce8b60; 1 drivers +v0000000000c56520_0 .net "AxorB", 0 0, L_0000000000ce8540; 1 drivers +v0000000000c567a0_0 .net "AxorBandCarryIn", 0 0, L_0000000000ce8ee0; 1 drivers +v0000000000c57880_0 .net "a", 0 0, L_0000000000c57ec0; 1 drivers +v0000000000c56e80_0 .net "b", 0 0, L_0000000000c56340; 1 drivers +v0000000000c565c0_0 .net "carryin", 0 0, L_0000000000ce8a80; alias, 1 drivers +v0000000000c56660_0 .net "carryout", 0 0, L_0000000000ce8150; alias, 1 drivers +v0000000000c57420_0 .net "sum", 0 0, L_0000000000ce8af0; 1 drivers +S_0000000001276830 .scope module, "a3" "structFullAdder" 3 54, 3 20 0, S_0000000000c00df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0000000000ce8700/d .functor XOR 1, L_0000000000c562a0, L_0000000000c560c0, C4<0>, C4<0>; +L_0000000000ce8700 .delay 1 (50000,50000,50000) L_0000000000ce8700/d; +L_0000000000ce8310/d .functor XOR 1, L_0000000000ce8700, L_0000000000ce8150, C4<0>, C4<0>; +L_0000000000ce8310 .delay 1 (50000,50000,50000) L_0000000000ce8310/d; +L_0000000000ce8cb0/d .functor AND 1, L_0000000000c562a0, L_0000000000c560c0, C4<1>, C4<1>; +L_0000000000ce8cb0 .delay 1 (50000,50000,50000) L_0000000000ce8cb0/d; +L_0000000000ce80e0/d .functor AND 1, L_0000000000ce8700, L_0000000000ce8150, C4<1>, C4<1>; +L_0000000000ce80e0 .delay 1 (50000,50000,50000) L_0000000000ce80e0/d; +L_0000000000ce8e00/d .functor OR 1, L_0000000000ce80e0, L_0000000000ce8cb0, C4<0>, C4<0>; +L_0000000000ce8e00 .delay 1 (50000,50000,50000) L_0000000000ce8e00/d; +v0000000000c57740_0 .net "AandB", 0 0, L_0000000000ce8cb0; 1 drivers +v0000000000c56840_0 .net "AxorB", 0 0, L_0000000000ce8700; 1 drivers +v0000000000c579c0_0 .net "AxorBandCarryIn", 0 0, L_0000000000ce80e0; 1 drivers +v0000000000c574c0_0 .net "a", 0 0, L_0000000000c562a0; 1 drivers +v0000000000c568e0_0 .net "b", 0 0, L_0000000000c560c0; 1 drivers +v0000000000c571a0_0 .net "carryin", 0 0, L_0000000000ce8150; alias, 1 drivers +v0000000000c56f20_0 .net "carryout", 0 0, L_0000000000ce8e00; alias, 1 drivers +v0000000000c56980_0 .net "sum", 0 0, L_0000000000ce8310; 1 drivers + .scope S_0000000000bfe600; +T_0 ; + %vpi_call 2 17 "$dumpfile", "fulladder.vcd" {0 0 0}; + %vpi_call 2 18 "$dumpvars", 32'sb00000000000000000000000000000000, v0000000000c57060_0, v0000000000c57600_0, v0000000000c56700_0, v0000000000c576a0_0, v0000000000c57b00_0, v0000000000c57ce0_0 {0 0 0}; + %vpi_call 2 20 "$display", " a | b | S C2 | COut | OverFlow" {0 0 0}; + %pushi/vec4 4294967288, 0, 32; + %store/vec4 v0000000000c57ba0_0, 0, 32; +T_0.0 ; + %load/vec4 v0000000000c57ba0_0; + %cmpi/s 8, 0, 32; + %jmp/0xz T_0.1, 5; + %pushi/vec4 4294967288, 0, 32; + %store/vec4 v0000000000c57c40_0, 0, 32; +T_0.2 ; + %load/vec4 v0000000000c57c40_0; + %cmpi/s 8, 0, 32; + %jmp/0xz T_0.3, 5; + %load/vec4 v0000000000c57ba0_0; + %pad/s 4; + %store/vec4 v0000000000c57060_0, 0, 4; + %load/vec4 v0000000000c57c40_0; + %pad/s 4; + %store/vec4 v0000000000c57600_0, 0, 4; + %delay 1000000, 0; + %load/vec4 v0000000000c57060_0; + %load/vec4 v0000000000c57600_0; + %load/vec4 v0000000000c56700_0; + %vpi_call 2 29 "$display", " %d | %d | %d %b | %b | %b ", S<2,vec4,s4>, S<1,vec4,s4>, S<0,vec4,s4>, v0000000000c57b00_0, v0000000000c576a0_0, v0000000000c57ce0_0 {3 0 0}; + %load/vec4 v0000000000c57c40_0; + %addi 1, 0, 32; + %store/vec4 v0000000000c57c40_0, 0, 32; + %jmp T_0.2; +T_0.3 ; + %load/vec4 v0000000000c57ba0_0; + %addi 7, 0, 32; + %store/vec4 v0000000000c57ba0_0, 0, 32; + %jmp T_0.0; +T_0.1 ; + %end; + .thread T_0; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "adder.t.v"; + "./adder.v"; diff --git a/adder.t.v b/adder.t.v new file mode 100644 index 0000000..15be0b5 --- /dev/null +++ b/adder.t.v @@ -0,0 +1,89 @@ +`timescale 1 ns / 1 ps +`include "adder.v" + +module test4BitFullAdder(); + reg[3:0] a; //Bus for a registers. + reg[3:0] b; //Bus for b registers. + wire[3:0] sum; //Bus for the individual sums. + wire carryout; //final carryout wire. + wire carryout2; + wire overflow; //Overflow wire. + + FullAdder4bit adder(sum, carryout, carryout2, overflow, a, b); + + initial begin + $dumpfile("fulladder.vcd"); + $dumpvars(0, a[3:0], b[3:0], sum[3:0], carryout, carryout2, overflow); + + + $display(" a | b | S C2 | COut | OverFlow | Sum | ECout | EOvrflow"); + a = 0; //Set register a. + b = 0; //Set register b. + #1000 //Delay. + $display(" %d | %d | %d %b | %b | %b | 0 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -1; + b = -1; + #1000 + $display(" %d | %d | %d %b | %b | %b | -2 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 1; + b = 1; + #1000 + $display(" %d | %d | %d %b | %b | %b | 2 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = -7; + #1000 + $display(" %d | %d | %d %b | %b | %b | 0 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 6; + b = -2; + #1000 + $display(" %d | %d | %d %b | %b | %b | 4 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 6; + b = 5; + #1000 + $display(" %d | %d | %d %b | %b | %b |11(-5)| 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 5; + b = -7; + #1000 + $display(" %d | %d | %d %b | %b | %b | -2 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = 3; + #1000 + $display(" %d | %d | %d %b | %b | %b |10(-6)| 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -5; + b = -5; + #1000 + $display(" %d | %d | %d %b | %b | %b |-10(6)| 1 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -8; + b = -8; + #1000 + $display(" %d | %d | %d %b | %b | %b |-16(0)| 1 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = -8; + #1000 + $display(" %d | %d | %d %b | %b | %b | -1 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 7; + b = 7; + #1000 + $display(" %d | %d | %d %b | %b | %b |14(-2)| 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 5; + b = 2; + #1000 + $display(" %d | %d | %d %b | %b | %b | 7 | 0 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = 5; + b = 3; + #1000 + $display(" %d | %d | %d %b | %b | %b |8(-8) | 0 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -5; + b = -3; + #1000 + $display(" %d | %d | %d %b | %b | %b | -8 | 1 | 0 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + a = -5; + b = -4; + #1000 + $display(" %d | %d | %d %b | %b | %b |-9(7) | 1 | 1 ", $signed(a), $signed(b), $signed(sum), carryout2, carryout, overflow); + + //end + //end + + end +endmodule diff --git a/adder.v b/adder.v new file mode 100644 index 0000000..1f87b87 --- /dev/null +++ b/adder.v @@ -0,0 +1,45 @@ +`define AND and #50 +`define OR or #50 +`define XOR xor #50 +`define NOT not #50 + +// Adder circuit + +module structFullAdder +( + output sum, + output carryout, + input a, + input b, + input carryin +); + wire AxorB; + wire AandB; + wire AxorBandCarryIn; + + `XOR (AxorB, a, b); + `XOR (sum, AxorB, carryin); + `AND (AandB, a, b); + `AND (AxorBandCarryIn, AxorB, carryin); + `OR (carryout, AxorBandCarryIn, AandB); +endmodule + +module FullAdder4bit +( + output[3:0] sum, // 2's complement sum of a and b + output carryout, carryout2, // Carry out of the summation of a and b + output overflow, // True if the calculation resulted in an overflow + input[3:0] a, // First operand in 2's complement format + input[3:0] b // Second operand in 2's complement format +); + + wire carryout0; //Carryout of first adder. + wire carryout1; //Carryout of second adder. + + structFullAdder a0(sum[0], carryout0, a[0], b[0], 1'b0); //Structural Full Adder with specific initial values. + structFullAdder a1(sum[1], carryout1, a[1], b[1], carryout0); + structFullAdder a2(sum[2], carryout2, a[2], b[2], carryout1); + structFullAdder a3(sum[3], carryout, a[3], b[3], carryout2); + + `XOR (overflow, carryout2, carryout); //XOR handles overflow. +endmodule diff --git a/fulladder.vcd b/fulladder.vcd new file mode 100644 index 0000000..77bfd42 --- /dev/null +++ b/fulladder.vcd @@ -0,0 +1,212 @@ +$date + Thu Sep 28 02:02:13 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module test4BitFullAdder $end +$var reg 4 ! a [3:0] $end +$upscope $end +$scope module test4BitFullAdder $end +$var reg 4 " b [3:0] $end +$upscope $end +$scope module test4BitFullAdder $end +$var wire 4 # sum [3:0] $end +$upscope $end +$scope module test4BitFullAdder $end +$var wire 1 $ carryout $end +$upscope $end +$scope module test4BitFullAdder $end +$var wire 1 % carryout2 $end +$upscope $end +$scope module test4BitFullAdder $end +$var wire 1 & overflow $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +x& +x% +x$ +bx # +b0 " +b0 ! +$end +#100000 +bx0 # +#150000 +0% +0$ +bx00 # +#200000 +b0 # +0& +#1000000 +b1111 " +b1111 ! +#1100000 +1% +1$ +#1150000 +b1110 # +#2000000 +b1 " +b1 ! +#2100000 +0% +0$ +#2150000 +b10 # +#3000000 +b1001 " +b111 ! +#3100000 +b1100 # +#3200000 +b1000 # +#3250000 +1% +#3300000 +b0 # +1& +#3350000 +1$ +#3400000 +0& +#4000000 +b1110 " +b110 ! +#4100000 +b110 # +#4150000 +b100 # +#5000000 +b101 " +#5100000 +b1111 # +#5150000 +b1011 # +0$ +#5200000 +1& +#6000000 +b1001 " +b101 ! +#6100000 +0% +b100 # +#6150000 +0& +1$ +b1110 # +#6200000 +0$ +1& +#6250000 +0& +#7000000 +b11 " +b111 ! +#7100000 +b110 # +#7150000 +b10 # +#7200000 +1% +#7250000 +b1010 # +1& +#8000000 +b1011 " +b1011 ! +#8100000 +b1110 # +1$ +#8150000 +0% +0& +#8200000 +b110 # +1& +#9000000 +b1000 " +b1000 ! +#9150000 +b0 # +#10000000 +b111 ! +#10100000 +b1111 # +0$ +#10150000 +0& +#11000000 +b111 " +#11100000 +1% +b0 # +#11150000 +b1110 # +1& +#12000000 +b10 " +b101 ! +#12100000 +0% +b1001 # +#12150000 +1% +0& +b111 # +#12200000 +1& +b1011 # +0% +#12250000 +1% +b111 # +0& +#12300000 +0% +b1111 # +1& +#12350000 +b111 # +0& +#13000000 +b11 " +#13100000 +b110 # +#13150000 +b100 # +#13250000 +b0 # +#13300000 +1% +#13350000 +b1000 # +1& +#14000000 +b1101 " +b1011 ! +#14100000 +1$ +#14150000 +0& +#15000000 +b1100 " +#15100000 +b1001 # +#15150000 +b1011 # +#15250000 +b1111 # +#15300000 +0% +#15350000 +b111 # +1& +#16000000 diff --git a/lab0_wrapper.v b/lab0_wrapper.v index 3270bd2..14949f6 100644 --- a/lab0_wrapper.v +++ b/lab0_wrapper.v @@ -25,7 +25,7 @@ //-------------------------------------------------------------------------------- `timescale 1ns / 1ps - +`include "adder.v" //-------------------------------------------------------------------------------- // Basic building block modules @@ -104,6 +104,7 @@ module lab0_wrapper wire res_sel; // Select between display options wire cout; // Carry out from adder wire ovf; // Overflow from adder + wire cout2; // Memory for stored operands (parametric width set to 4 bits) dff #(4) opA_mem(.trigger(clk), .enable(btn[0]), .d(sw), .q(opA)); @@ -114,12 +115,12 @@ module lab0_wrapper mux2 #(4) output_select(.in0(res0), .in1(res1), .sel(res_sel), .out(led)); // TODO: You write this in your adder.v - FullAdder4bit adder(.sum(res0), .carryout(cout), .overflow(ovf), .a(opA), .b(opB)); + FullAdder4bit adder(.sum(res0), .carryout(cout), .carryout2(cout2), .overflow(ovf), .a(opA), .b(opB)); // Assign bits of second display output to show carry out and overflow - assign res1[0] = cout; - assign res1[1] = ovf; - assign res1[2] = 1'b0; + assign res1[0] = cout2; + assign res1[1] = cout; + assign res1[2] = ovf; assign res1[3] = 1'b0; endmodule