diff --git a/adder.t.v b/adder.t.v new file mode 100644 index 0000000..8f62fa8 --- /dev/null +++ b/adder.t.v @@ -0,0 +1,60 @@ +// Adder testbench +`timescale 1 ns / 1 ps +`include "adder.v" + +module testFullAdder(); + reg [3:0] a; + reg [3:0] b; + wire[3:0] s; + wire carryout; + wire overflow; + + FullAdder4bit adder (s, carryout, overflow, a, b); + + initial begin + $dumpfile("adder.vcd"); + $dumpvars(0,testFullAdder); + // Your test code here + + $display("general case for no carryout and no overflow"); + $display("a0 a1 a2 a3 b0 b1 b2 b3 | s0 s1 s2 s3 | carryout overflow"); + a=4'b0000;b=4'b0101; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b0011;b=4'b0001; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b0100;b=4'b0011; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b0010;b=4'b0011; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + + $display("case with overflow and no carryout"); + a=4'b0101;b=4'b0011; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b0111;b=4'b0110; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b0111;b=4'b0111; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b0010;b=4'b0110; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + + $display("case with overflow and carrayout"); + a=4'b1001;b=4'b1110; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b1011;b=4'b1011; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b1000;b=4'b1100; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b1001;b=4'b1001; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + + $display("case with no overblow but carryout"); + a=4'b1101;b=4'b1011; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b1111;b=4'b1010; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b1110;b=4'b1101; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + a=4'b1011;b=4'b1110; #1000 + $display("%b %b %b %b %b %b %b %b | %b %b %b %b | %b %b", a[0], a[1], a[2], a[3], b[0], b[1], b[2], b[3], s[0], s[1], s[2], s[3], carryout, overflow); + end +endmodule diff --git a/adder.v b/adder.v new file mode 100644 index 0000000..5896f0c --- /dev/null +++ b/adder.v @@ -0,0 +1,73 @@ +// Adder circuit +`define AND and #50 +`define OR or #50 +`define NOT not #50 +`define XOR xor #50 + +module behavioralFullAdder +( + output sum, + output carryout, + input a, + input b, + input carryin +); + // Uses concatenation operator and built-in '+' + assign {carryout, sum}=a+b+carryin; +endmodule + +module structuralFullAdder +( + output sum, + output carryout, + input a, + input b, + input carryin +); + // Your adder code here + wire axorb; + wire nCarryIn; + wire notaxorb; + wire sumWire0; + wire sumWire1; + + `XOR abxorgate(axorb, a, b); + `AND andgate0(sumWire0, axorb, nCarryIn); + `NOT invCarryIn(nCarryIn, carryin); + `NOT invaxorb(notaxorb, axorb); + `AND andgate1(sumWire1, carryin, notaxorb); + `OR orgate0(sum, sumWire0, sumWire1); + + wire aandb; + wire aorb; + wire carryOutWire; + + `AND abandgate(aandb, a, b); + `OR orgate1(aorb, a, b); + `AND andgate2(carryOutWire, carryin, aorb); + `OR orgate2(carryout, aandb, carryOutWire); +endmodule + +module FullAdder4bit +( + output[3:0] sum, // 2's complement sum of a and b + output carryout, // Carry out of the summation of a and b + output overflow, // True if the calculation resulted in an overflow + input[3:0] a, // First operand in 2's complement format + input[3:0] b // Second operand in 2's complement format +); + // Your Code Here + // carryin wires + wire carryin1; + wire carryin2; + wire carryin3; + + // 1-bit adder + structuralFullAdder adder0(sum[0],carryin1,a[0],b[0],0); + structuralFullAdder adder1(sum[1],carryin2,a[1],b[1],carryin1); + structuralFullAdder adder2(sum[2],carryin3,a[2],b[2],carryin2); + structuralFullAdder adder3(sum[3],carryout,a[3],b[3],carryin3); + + // xor gate for determining overflow + `XOR overflowxorgate(overflow, carryin3, carryout); +endmodule diff --git a/adder.vcd b/adder.vcd new file mode 100644 index 0000000..7b136c7 --- /dev/null +++ b/adder.vcd @@ -0,0 +1,797 @@ +$date + Tue Sep 26 14:11:10 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testFullAdder $end +$var wire 1 ! carryout $end +$var wire 1 " overflow $end +$var wire 4 # s [3:0] $end +$var reg 4 $ a [3:0] $end +$var reg 4 % b [3:0] $end +$scope module adder $end +$var wire 4 & a [3:0] $end +$var wire 4 ' b [3:0] $end +$var wire 1 ( carryin1 $end +$var wire 1 ) carryin2 $end +$var wire 1 * carryin3 $end +$var wire 1 ! carryout $end +$var wire 1 " overflow $end +$var wire 4 + sum [3:0] $end +$scope module adder0 $end +$var wire 1 , a $end +$var wire 1 - aandb $end +$var wire 1 . aorb $end +$var wire 1 / axorb $end +$var wire 1 0 b $end +$var wire 1 1 carryOutWire $end +$var wire 1 2 carryin $end +$var wire 1 ( carryout $end +$var wire 1 3 nCarryIn $end +$var wire 1 4 notaxorb $end +$var wire 1 5 sum $end +$var wire 1 6 sumWire0 $end +$var wire 1 7 sumWire1 $end +$upscope $end +$scope module adder1 $end +$var wire 1 8 a $end +$var wire 1 9 aandb $end +$var wire 1 : aorb $end +$var wire 1 ; axorb $end +$var wire 1 < b $end +$var wire 1 = carryOutWire $end +$var wire 1 ( carryin $end +$var wire 1 ) carryout $end +$var wire 1 > nCarryIn $end +$var wire 1 ? notaxorb $end +$var wire 1 @ sum $end +$var wire 1 A sumWire0 $end +$var wire 1 B sumWire1 $end +$upscope $end +$scope module adder2 $end +$var wire 1 C a $end +$var wire 1 D aandb $end +$var wire 1 E aorb $end +$var wire 1 F axorb $end +$var wire 1 G b $end +$var wire 1 H carryOutWire $end +$var wire 1 ) carryin $end +$var wire 1 * carryout $end +$var wire 1 I nCarryIn $end +$var wire 1 J notaxorb $end +$var wire 1 K sum $end +$var wire 1 L sumWire0 $end +$var wire 1 M sumWire1 $end +$upscope $end +$scope module adder3 $end +$var wire 1 N a $end +$var wire 1 O aandb $end +$var wire 1 P aorb $end +$var wire 1 Q axorb $end +$var wire 1 R b $end +$var wire 1 S carryOutWire $end +$var wire 1 * carryin $end +$var wire 1 ! carryout $end +$var wire 1 T nCarryIn $end +$var wire 1 U notaxorb $end +$var wire 1 V sum $end +$var wire 1 W sumWire0 $end +$var wire 1 X sumWire1 $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +xX +xW +xV +zU +xT +xS +0R +zQ +zP +zO +0N +xM +xL +xK +zJ +xI +xH +1G +zF +zE +zD +0C +xB +xA +x@ +z? +x> +x= +0< +z; +z: +z9 +08 +z7 +x6 +x5 +z4 +z3 +02 +z1 +10 +z/ +z. +z- +0, +bx + +x* +x) +x( +b101 ' +b0 & +b101 % +b0 $ +bx # +x" +x! +$end +#50000 +0P +0O +0Q +1E +0D +1F +0: +09 +0; +01 +1. +0- +07 +13 +1/ +#100000 +0S +0W +1U +0J +0= +0A +1? +0( +16 +04 +#150000 +0! +0M +0) +1> +0B +15 +bx1 # +bx1 + +#200000 +1I +0H +0@ +bx01 # +bx01 + +#250000 +1L +0* +#300000 +1K +bx101 # +bx101 + +1T +0X +0" +#350000 +0V +b101 # +b101 + +#1000000 +0G +1, +18 +b1 % +b1 ' +b11 $ +b11 & +#1050000 +0F +0E +0/ +1- +1; +1: +#1100000 +0L +1J +06 +14 +1( +1A +0? +#1150000 +0K +05 +0> +1= +1@ +b10 # +b10 + +#1200000 +0A +1) +#1250000 +0@ +b0 # +b0 + +0I +1M +#1300000 +1K +b100 # +b100 + +#2000000 +1< +0, +08 +1C +b11 % +b11 ' +b100 $ +b100 & +#2050000 +1/ +0- +1F +1E +#2100000 +16 +04 +0( +0J +1H +#2150000 +15 +b101 # +b101 + +1> +0= +0M +1* +#2200000 +1A +0) +0K +b1 # +b1 + +0T +1X +1" +#2250000 +1@ +1I +0H +1V +b1011 # +b1011 + +#2300000 +1L +0* +#2350000 +1K +b1111 # +b1111 + +1T +0X +0" +#2400000 +0V +b111 # +b111 + +#3000000 +18 +0C +b10 $ +b10 & +#3050000 +0; +19 +0F +0E +#3100000 +0A +1? +1) +0L +1J +#3150000 +0@ +0I +0K +b1 # +b1 + +1M +#3200000 +1K +b101 # +b101 + +#4000000 +1, +08 +1C +b101 $ +b101 & +#4050000 +0/ +1- +1; +09 +1F +1E +#4100000 +06 +14 +1( +1A +0? +0) +0J +1H +#4150000 +05 +0> +1= +1@ +b110 # +b110 + +1I +0H +0M +1* +#4200000 +0A +1) +1L +0* +0K +b10 # +b10 + +0T +1X +1" +#4250000 +0@ +0I +1H +1K +1T +0X +0" +1V +b1100 # +b1100 + +#4300000 +0L +1* +0V +b100 # +b100 + +#4350000 +0K +b0 # +b0 + +0T +1X +1" +#4400000 +1V +b1000 # +b1000 + +#5000000 +00 +1G +18 +b110 % +b110 ' +b111 $ +b111 & +#5050000 +1/ +0- +0F +1D +0; +19 +#5100000 +16 +04 +0( +1J +1? +#5150000 +15 +b1001 # +b1001 + +1> +0= +1M +#5200000 +1K +b1101 # +b1101 + +#6000000 +10 +b111 % +b111 ' +#6050000 +0/ +1- +#6100000 +06 +14 +1( +#6150000 +05 +b1100 # +b1100 + +0> +1B +1= +#6200000 +1@ +b1110 # +b1110 + +#7000000 +00 +0, +0C +b110 % +b110 ' +b10 $ +b10 & +#7050000 +0- +0. +1F +0D +#7100000 +0( +0J +#7150000 +1> +0B +0= +0M +#7200000 +0@ +0K +b1000 # +b1000 + +#8000000 +1R +1, +08 +1N +b1110 % +b1110 ' +b1001 $ +b1001 & +#8050000 +1/ +1. +1; +09 +1O +1P +#8100000 +16 +04 +1A +0? +0) +1! +1S +#8150000 +15 +1@ +b1011 # +b1011 + +1I +0H +0" +#8200000 +1L +0* +#8250000 +1K +b1111 # +b1111 + +1T +0X +0S +1" +#8300000 +0V +b111 # +b111 + +#9000000 +10 +0G +18 +b1011 % +b1011 ' +b1011 $ +b1011 & +#9050000 +0/ +1- +0F +0E +0; +19 +#9100000 +06 +14 +1( +0L +1J +0A +1? +1) +#9150000 +05 +0> +1= +0K +0@ +b0 # +b0 + +1B +0I +1M +#9200000 +1@ +1K +b110 # +b110 + +#10000000 +00 +0< +1G +0, +08 +b1100 % +b1100 ' +b1000 $ +b1000 & +#10050000 +1F +1E +0- +0. +09 +0: +#10100000 +0J +1H +0( +0= +#10150000 +0M +1* +1> +0B +0) +#10200000 +0K +0T +1X +1S +0" +0@ +b0 # +b0 + +1I +0H +#10250000 +1V +b1000 # +b1000 + +1L +0* +#10300000 +1K +b1100 # +b1100 + +1T +0X +0S +1" +#10350000 +0V +b100 # +b100 + +#11000000 +10 +0G +1, +b1001 % +b1001 ' +b1001 $ +b1001 & +#11050000 +0F +0E +1- +1. +#11100000 +0L +1J +1( +#11150000 +0K +b0 # +b0 + +0> +1B +#11200000 +1@ +b10 # +b10 + +#12000000 +1< +1C +b1011 % +b1011 ' +b1101 $ +b1101 & +#12050000 +1; +1: +1F +1E +#12100000 +0? +1= +1L +0J +#12150000 +0B +1) +1K +b110 # +b110 + +#12200000 +0@ +b100 # +b100 + +0I +1H +#12250000 +0L +1* +#12300000 +0K +b0 # +b0 + +0T +1X +1S +0" +#12350000 +1V +b1000 # +b1000 + +#13000000 +00 +18 +b1010 % +b1010 ' +b1111 $ +b1111 & +#13050000 +1/ +0- +0; +19 +#13100000 +16 +04 +0( +1? +#13150000 +15 +b1001 # +b1001 + +1> +0= +#14000000 +10 +0< +1G +0, +b1101 % +b1101 ' +b1110 $ +b1110 & +#14050000 +1; +09 +0F +1D +#14100000 +1A +0? +0) +1J +#14150000 +1@ +b1011 # +b1011 + +1I +0H +#15000000 +00 +1< +1, +0C +b1110 % +b1110 ' +b1011 $ +b1011 & +#15050000 +0; +19 +1F +0D +#15100000 +0A +1? +1) +1L +0J +0* +#15150000 +0@ +0I +1H +1K +b1101 # +b1101 + +1T +0X +0S +1" +#15200000 +0L +1* +0V +b101 # +b101 + +#15250000 +0K +b1 # +b1 + +0T +1X +1S +0" +#15300000 +1V +b1001 # +b1001 + +#16000000 diff --git a/images/lab0/A input.jpg b/images/lab0/A input.jpg new file mode 100644 index 0000000..f9a4cd3 Binary files /dev/null and b/images/lab0/A input.jpg differ diff --git a/images/lab0/B input.jpg b/images/lab0/B input.jpg new file mode 100644 index 0000000..503c604 Binary files /dev/null and b/images/lab0/B input.jpg differ diff --git a/images/lab0/Carryout output.jpg b/images/lab0/Carryout output.jpg new file mode 100644 index 0000000..1480361 Binary files /dev/null and b/images/lab0/Carryout output.jpg differ diff --git a/images/lab0/Sum output.jpg b/images/lab0/Sum output.jpg new file mode 100644 index 0000000..0adb8f6 Binary files /dev/null and b/images/lab0/Sum output.jpg differ diff --git a/images/lab0/Timing.png b/images/lab0/Timing.png new file mode 100644 index 0000000..270a7e2 Binary files /dev/null and b/images/lab0/Timing.png differ diff --git a/images/lab0/Utilization.png b/images/lab0/Utilization.png new file mode 100644 index 0000000..ecaaba3 Binary files /dev/null and b/images/lab0/Utilization.png differ diff --git a/images/lab0/power.png b/images/lab0/power.png new file mode 100644 index 0000000..22c17c0 Binary files /dev/null and b/images/lab0/power.png differ diff --git a/images/lab0/test_bench.png b/images/lab0/test_bench.png new file mode 100644 index 0000000..650d0d4 Binary files /dev/null and b/images/lab0/test_bench.png differ diff --git a/images/lab0/waveform.png b/images/lab0/waveform.png new file mode 100644 index 0000000..11a2d98 Binary files /dev/null and b/images/lab0/waveform.png differ diff --git a/lab0_report.md b/lab0_report.md new file mode 100644 index 0000000..64980d7 --- /dev/null +++ b/lab0_report.md @@ -0,0 +1,79 @@ +# Lab 0 Report + +### Changjun Lim, Sungwoo Park + + +### Waveform + +![Waveform image](images/lab0/waveform.png) + + +Above figure shows the waveform of our adder going through few test cases. Notice that even though there are some glitches right after the inputs change, the sum output value stabilizes shortly after. + +It seems like the worst delay occurs when the all bits of two input values changes, which results in change in individual sum bits and intermediate carry-in values between the adders. + +##### Test case + We chose the following 16 test cases among the total 256 test cases. There are two interesting situations that are involved in this operation, namely overflow and carryout. We wanted to comprehensively test each possible scenario involving overflow and carryout. In order to do this, we grouped the test cases into 4 scenarios(whether there is an overflow or a carryout). We selected 4 test cases for each scenario. + + The test case 1-4 show the cases with no sum and carryout. The test case 5-8 are for the cases with overflow but no carryout. The test case 9-12 have only overflow and the test case 13-16 have both carryout and overflow. + +Note: Least significant binary digit has an index 0 in the variables. + +(a: a[3],a[2],a[1],a[0], b: b[3],b[2],b[1],b[0], s: s[3],s[2],s[1],s[0]) + +       Input value          / Expected result +1. a=0000, b=0101 / sum=0101 carryout=0 overflow=0 +2. a=0011, b=0001 / sum=0100 carryout=0 overflow=0 +3. a=0100, b=0011 / sum=0111 carryout=0 overflow=0 +4. a=0010, b=0011 / sum=0101 carryout=0 overflow=0 +5. a=0101, b=0011 / sum=1000 carryout=0 overflow=1 +6. a=0111, b=0110 / sum=1101 carryout=0 overflow=1 +7. a=0111, b=0111 / sum=1110 carryout=0 overflow=1 +8. a=0010, b=0110 / sum=1000 carryout=0 overflow=1 +9. a=1001, b=1110 / sum=0111 carryout=1 overflow=1 +10. a=1011, b=1011 / sum=0110 carryout=1 overflow=1 +11. a=1000, b=1100 / sum=0100 carryout=1 overflow=1 +12. a=1001, b=1001 / sum=0010 carryout=1 overflow=1 +13. a=1101, b=1011 / sum=1000 carryout=1 overflow=0 +14. a=1111, b=1010 / sum=1001 carryout=1 overflow=0 +15. a=1110, b=1101 / sum=1011 carryout=1 overflow=0 +16. a=1011, b=1110 / sum=1001 carryout=1 overflow=0 + +### Result of test bench output + +![test bench result](images/lab0/test_bench.png) + +### Failed test cases + +Our code passed all our initial test cases. + + +### Test Result on FPGA + +Following pictures are the documentation of our testing process for case 9 (1001 + 1110) using FPGA board. + +A input +![A input](images/lab0/A%20input.jpg) + +B input +![B input](images/lab0/B%20input.jpg) + +Sum output +![Sum output](images/lab0/Sum%20output.jpg) + +Carryout/overflow output +![Carryout output](images/lab0/Carryout%20output.jpg) + +### The summary statistics from Vivado. + +Following pictures are the summary statistics of our circuit in FPGA. The circuit in this lab is so small that it uses only little part of power(2% and 1% for signals and logi, respectively) and uilization(0.03% for LUT and FF). And the timing is not measured because we constructed the combinational circuit without clock. + +Power +![Power](images/lab0/power.png) + +Utilization +![Utilization](images/lab0/Utilization.png) + +Timing +![Timing](images/lab0/Timing.png) + diff --git a/lab0_wrapper.v b/lab0_wrapper.v index 3270bd2..661cc7c 100644 --- a/lab0_wrapper.v +++ b/lab0_wrapper.v @@ -1,3 +1,4 @@ +`include "adder.v" //-------------------------------------------------------------------------------- // Wrapper for Lab 0: Full Adder //