diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..13aa783
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+# Ignore all
+*
+
+# Unignore all with extensions
+!*.*
\ No newline at end of file
diff --git a/adder.v b/adder.v
new file mode 100644
index 0000000..cc610e8
--- /dev/null
+++ b/adder.v
@@ -0,0 +1,76 @@
+// Adder circuit
+
+module behavioralFullAdder
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    // Uses concatenation operator and built-in '+'
+    assign {carryout, sum}=a+b+carryin;
+endmodule
+
+module structuralFullAdder
+(
+    output sum, 
+    output carryout,
+    input a, 
+    input b, 
+    input carryin
+);
+    wire ab;    //setting up wires
+    wire acarryin;
+    wire bcarryin;
+    wire orpairintermediate;
+    wire orsingleintermediate;
+    wire orall;
+    wire andsumintermediate;
+    wire andsingleintermediate;
+    wire andall;
+    wire invcarryout;
+    and #(50) andab(ab, a, b);  // a and b
+    and #(50) andacarryin(acarryin, a, carryin);    // a and carryin
+    and #(50) andbcarryin(bcarryin, b, carryin);    // b and carryin
+    or #(50) orpair(orpairintermediate, ab, acarryin);  // (a and b) or (a and carryin)
+    or #(50) orcarryout(carryout, orpairintermediate, bcarryin);    // ((a and b) or (a and carryin)) or (b and carryin)
+    or #(50) orintermediate(orsingleintermediate, a, b);    // a or b
+    or #(50) orallinputs(orall, orsingleintermediate, carryin); // (a or b) or carryin
+    not #(50) inv(invcarryout, carryout);   // not carryout
+    and #(50) sumintermediate(andsumintermediate, invcarryout, orall);  // (a or b or carryin) and not carryout
+    and #(50) andintermediate(andsingleintermediate, a, b); // a and b
+    and #(50) andallinputs(andall, andsingleintermediate, carryin); // (a and b) and carryin
+    or #(50) adder(sum, andsumintermediate, andall);    // ((a or b or carryin) and not carryout) or (a and b and c)
+endmodule
+
+module FullAdder4bit
+(
+  output[3:0] sum,  // 2's complement sum of a and b
+  output carryout,  // Carry out of the summation of a and b
+  output overflow,  // True if the calculation resulted in an overflow
+  input[3:0] a,     // First operand in 2's complement format
+  input[3:0] b,      // Second operand in 2's complement format
+  input carryin
+);
+    wire carryout1; // wire setup for carryouts from each adder
+    wire carryout2;
+    wire carryout3;
+    wire aandb;
+    wire anorb;
+    wire bandsum;
+    wire bnorsum;
+    wire abandnoror;
+    wire bsumandnornor;
+    structuralFullAdder #50 adder1(sum[0], carryout1, a[0], b[0], carryin);   // first adder to handle the first added bits
+    structuralFullAdder #50 adder2(sum[1], carryout2, a[1], b[1], carryout1);   // second adder to take the carryout from the first adder and the next added bits
+    structuralFullAdder #50 adder3(sum[2], carryout3, a[2], b[2], carryout2);   // third adder to take the second carryout and the third added bits
+    structuralFullAdder #50 adder4(sum[3], carryout, a[3], b[3], carryout3);    // fourth adder to take the third carryout and the fourth bits
+    and #50 andinputs(aandb, a[3], b[3]);   // logic to determine overflow (overflow occurs when two positives result in a negative or two negatives result in a positive, the larges bit in both inputs are equal and the largest bit in the output is not the same)
+    nor #50 norinputs(anorb, a[3], b[3]);
+    and #50 andsum(bandsum, b[3], sum[3]);
+    nor #50 norsum(bnorsum, b[3], sum[3]);
+    or #50 orinputcombs(abandnoror, aandb, anorb);
+    nor #50 norsumcombs(bsumandnornor, bandsum, bnorsum);
+    and #50 finaland(overflow, abandnoror, bsumandnornor);
+endmodule
\ No newline at end of file
diff --git a/adder_subtracter.t.v b/adder_subtracter.t.v
new file mode 100644
index 0000000..e2c0aa1
--- /dev/null
+++ b/adder_subtracter.t.v
@@ -0,0 +1,60 @@
+// Adder_subtacter testbench
+
+`timescale 1 ns / 1 ps
+`include "adder_subtracter.v"
+
+module test32bitAdder();
+    reg[31:0] a;
+    reg[31:0] b;
+    reg[2:0] carryin;
+    wire[31:0] ans;
+    wire carryout, overflow;
+
+    adder_subtracter adder0(ans[31:0], carryout, overflow, a[31:0], b[31:0], carryin[2:0]);
+
+    initial begin
+       $display("Input A                          Input B                          Command | Output                         Flag  Carryout");
+
+        // Addition tests
+        a=32'b00000000000000000000000000000001;
+        b=32'b00000000000000000000000000000001;
+        carryin=3'b100; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        a=32'b10000000000000000000000000000001;
+        b=32'b10000000000000000000000000000001;
+        carryin=3'b000; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        // Subtraction Tests
+        a=32'b00000000000000000000000000000001;
+        b=32'b00000000000000000000000000000001;
+        carryin=3'b001; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        a=32'b00000000001000000000000000000000;
+        b=32'b00000000000000000000000010000000;
+        carryin=3'b001; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        a=32'b10000000001000010000000000000000;
+        b=32'b10000000000000010000000010000000;
+        carryin=3'b001; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        a=32'b10000000000000000000000000000001;
+        b=32'b10000000000000000000000000000001;
+        carryin=3'b001; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        a=32'b00000000000000000000000000000000;
+        b=32'b10000000000000000000000000000001;
+        carryin=3'b001; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+
+        a=32'b10000000000000000000000000000001;
+        b=32'b10000000000000000000000000000001;
+        carryin=3'b000; #5000 
+        $display("%b  %b  %b |  %b  %b    %b", a[31:0],b[31:0],carryin,ans[31:0],carryout, overflow);
+    end
+endmodule
\ No newline at end of file
diff --git a/adder_subtracter.v b/adder_subtracter.v
new file mode 100644
index 0000000..f59fd57
--- /dev/null
+++ b/adder_subtracter.v
@@ -0,0 +1,256 @@
+`include "adder.v"
+
+// 32 bit mux
+module mux
+  (
+    output[31:0] out,
+    input address,
+    input[31:0] in0,
+    input[31:0] in1
+  );
+  wire invaddr;
+  wire in00addr; // input 0 bit 0 andded with address
+  wire in01addr;
+  wire in02addr;
+  wire in03addr;
+  wire in04addr;
+  wire in05addr;
+  wire in06addr;
+  wire in07addr;
+  wire in08addr;
+  wire in09addr;
+  wire in010addr;
+  wire in011addr;
+  wire in012addr;
+  wire in013addr;
+  wire in014addr;
+  wire in015addr;
+  wire in016addr;
+  wire in017addr;
+  wire in018addr;
+  wire in019addr;
+  wire in020addr;
+  wire in021addr;
+  wire in022addr;
+  wire in023addr;
+  wire in024addr;
+  wire in025addr;
+  wire in026addr;
+  wire in027addr;
+  wire in028addr;
+  wire in029addr;
+  wire in030addr;
+  wire in031addr;
+  wire in10addr;
+  wire in11addr;
+  wire in12addr;
+  wire in13addr;
+  wire in14addr;
+  wire in15addr;
+  wire in16addr;
+  wire in17addr;
+  wire in18addr;
+  wire in19addr;
+  wire in110addr;
+  wire in111addr;
+  wire in112addr;
+  wire in113addr;
+  wire in114addr;
+  wire in115addr;
+  wire in116addr;
+  wire in117addr;
+  wire in118addr;
+  wire in119addr;
+  wire in120addr;
+  wire in121addr;
+  wire in122addr;
+  wire in123addr;
+  wire in124addr;
+  wire in125addr;
+  wire in126addr;
+  wire in127addr;
+  wire in128addr;
+  wire in129addr;
+  wire in130addr;
+  wire in131addr;
+
+  // inverting address
+  not #10 inv(invaddr, address);
+  // and all bits in input 0 with inverted address
+  and #20 and00(in00addr, in0[0], invaddr);
+  and #20 and01(in01addr, in0[1], invaddr);
+  and #20 and02(in02addr, in0[2], invaddr);
+  and #20 and03(in03addr, in0[3], invaddr);
+  and #20 and04(in04addr, in0[4], invaddr);
+  and #20 and05(in05addr, in0[5], invaddr);
+  and #20 and06(in06addr, in0[6], invaddr);
+  and #20 and07(in07addr, in0[7], invaddr);
+  and #20 and08(in08addr, in0[8], invaddr);
+  and #20 and09(in09addr, in0[9], invaddr);
+  and #20 and010(in010addr, in0[10], invaddr);
+  and #20 and011(in011addr, in0[11], invaddr);
+  and #20 and012(in012addr, in0[12], invaddr);
+  and #20 and013(in013addr, in0[13], invaddr);
+  and #20 and014(in014addr, in0[14], invaddr);
+  and #20 and015(in015addr, in0[15], invaddr);
+  and #20 and016(in016addr, in0[16], invaddr);
+  and #20 and017(in017addr, in0[17], invaddr);
+  and #20 and018(in018addr, in0[18], invaddr);
+  and #20 and019(in019addr, in0[19], invaddr);
+  and #20 and020(in020addr, in0[20], invaddr);
+  and #20 and021(in021addr, in0[21], invaddr);
+  and #20 and022(in022addr, in0[22], invaddr);
+  and #20 and023(in023addr, in0[23], invaddr);
+  and #20 and024(in024addr, in0[24], invaddr);
+  and #20 and025(in025addr, in0[25], invaddr);
+  and #20 and026(in026addr, in0[26], invaddr);
+  and #20 and027(in027addr, in0[27], invaddr);
+  and #20 and028(in028addr, in0[28], invaddr);
+  and #20 and029(in029addr, in0[29], invaddr);
+  and #20 and030(in030addr, in0[30], invaddr);
+  and #20 and031(in031addr, in0[31], invaddr);
+  // and all bits in input 1 with address
+  and #20 and10(in10addr, in1[0], address);
+  and #20 and11(in11addr, in1[1], address);
+  and #20 and12(in12addr, in1[2], address);
+  and #20 and13(in13addr, in1[3], address);
+  and #20 and14(in14addr, in1[4], address);
+  and #20 and15(in15addr, in1[5], address);
+  and #20 and16(in16addr, in1[6], address);
+  and #20 and17(in17addr, in1[7], address);
+  and #20 and18(in18addr, in1[8], address);
+  and #20 and19(in19addr, in1[9], address);
+  and #20 and110(in110addr, in1[10], address);
+  and #20 and111(in111addr, in1[11], address);
+  and #20 and112(in112addr, in1[12], address);
+  and #20 and113(in113addr, in1[13], address);
+  and #20 and114(in114addr, in1[14], address);
+  and #20 and115(in115addr, in1[15], address);
+  and #20 and116(in116addr, in1[16], address);
+  and #20 and117(in117addr, in1[17], address);
+  and #20 and118(in118addr, in1[18], address);
+  and #20 and119(in119addr, in1[19], address);
+  and #20 and120(in120addr, in1[20], address);
+  and #20 and121(in121addr, in1[21], address);
+  and #20 and122(in122addr, in1[22], address);
+  and #20 and123(in123addr, in1[23], address);
+  and #20 and124(in124addr, in1[24], address);
+  and #20 and125(in125addr, in1[25], address);
+  and #20 and126(in126addr, in1[26], address);
+  and #20 and127(in127addr, in1[27], address);
+  and #20 and128(in128addr, in1[28], address);
+  and #20 and129(in129addr, in1[29], address);
+  and #20 and130(in130addr, in1[30], address);
+  and #20 and131(in131addr, in1[31], address);
+
+  // or the and gates
+  or #20 or0(out[0], in00addr, in10addr);
+  or #20 or1(out[1], in01addr, in11addr);
+  or #20 or2(out[2], in02addr, in12addr);
+  or #20 or3(out[3], in03addr, in13addr);
+  or #20 or4(out[4], in04addr, in14addr);
+  or #20 or5(out[5], in05addr, in15addr);
+  or #20 or6(out[6], in06addr, in16addr);
+  or #20 or7(out[7], in07addr, in17addr);
+  or #20 or8(out[8], in08addr, in18addr);
+  or #20 or9(out[9], in09addr, in19addr);
+  or #20 or10(out[10], in010addr, in110addr);
+  or #20 or11(out[11], in011addr, in111addr);
+  or #20 or12(out[12], in012addr, in112addr);
+  or #20 or13(out[13], in013addr, in113addr);
+  or #20 or14(out[14], in014addr, in114addr);
+  or #20 or15(out[15], in015addr, in115addr);
+  or #20 or16(out[16], in016addr, in116addr);
+  or #20 or17(out[17], in017addr, in117addr);
+  or #20 or18(out[18], in018addr, in118addr);
+  or #20 or19(out[19], in019addr, in119addr);
+  or #20 or20(out[20], in020addr, in120addr);
+  or #20 or21(out[21], in021addr, in121addr);
+  or #20 or22(out[22], in022addr, in122addr);
+  or #20 or23(out[23], in023addr, in123addr);
+  or #20 or24(out[24], in024addr, in124addr);
+  or #20 or25(out[25], in025addr, in125addr);
+  or #20 or26(out[26], in026addr, in126addr);
+  or #20 or27(out[27], in027addr, in127addr);
+  or #20 or28(out[28], in028addr, in128addr);
+  or #20 or29(out[29], in029addr, in129addr);
+  or #20 or30(out[30], in030addr, in130addr);
+  or #20 or31(out[31], in031addr, in131addr);
+endmodule
+
+// 32 bit adder/subtracter that determines what operation to conduct based on the input command
+module adder_subtracter
+  (
+    output[31:0] ans,
+    output carryout,
+    output overflow,
+    input[31:0] opA,
+    input[31:0] opB,
+    input[2:0] command
+  );
+  wire[31:0] invertedB; //wire to invert b in the event of a subtraction
+  wire[31:0] finalB;
+  wire normalB; //added b
+  wire cout0;
+  wire cout1;
+  wire cout2;
+  wire cout3;
+  wire cout4;
+  wire cout5;
+  wire cout6;
+  wire _;
+  wire _1;
+  wire _2;
+  wire _3;
+  wire _4;
+  wire _5;
+  wire _6;
+  
+  // invert B in the case of two's complement
+  not #10 invertB0(invertedB[0], opB[0]);
+  not #10 invertB1(invertedB[1], opB[1]);
+  not #10 invertB2(invertedB[2], opB[2]);
+  not #10 invertB3(invertedB[3], opB[3]);
+  not #10 invertB4(invertedB[4], opB[4]);
+  not #10 invertB5(invertedB[5], opB[5]);
+  not #10 invertB6(invertedB[6], opB[6]);
+  not #10 invertB7(invertedB[7], opB[7]);
+  not #10 invertB8(invertedB[8], opB[8]);
+  not #10 invertB9(invertedB[9], opB[9]);
+  not #10 invertB10(invertedB[10], opB[10]);
+  not #10 invertB11(invertedB[11], opB[11]);
+  not #10 invertB12(invertedB[12], opB[12]);
+  not #10 invertB13(invertedB[13], opB[13]);
+  not #10 invertB14(invertedB[14], opB[14]);
+  not #10 invertB15(invertedB[15], opB[15]);
+  not #10 invertB16(invertedB[16], opB[16]);
+  not #10 invertB17(invertedB[17], opB[17]);
+  not #10 invertB18(invertedB[18], opB[18]);
+  not #10 invertB19(invertedB[19], opB[19]);
+  not #10 invertB20(invertedB[20], opB[20]);
+  not #10 invertB21(invertedB[21], opB[21]);
+  not #10 invertB22(invertedB[22], opB[22]);
+  not #10 invertB23(invertedB[23], opB[23]);
+  not #10 invertB24(invertedB[24], opB[24]);
+  not #10 invertB25(invertedB[25], opB[25]);
+  not #10 invertB26(invertedB[26], opB[26]);
+  not #10 invertB27(invertedB[27], opB[27]);
+  not #10 invertB28(invertedB[28], opB[28]);
+  not #10 invertB29(invertedB[29], opB[29]);
+  not #10 invertB30(invertedB[30], opB[30]);
+  not #10 invertB31(invertedB[31], opB[31]);
+
+  // mux chooses between inverted B or normal B based on addition or subtraction
+  mux addsubmux(finalB[31:0],command[0],opB[31:0], invertedB[31:0]);
+  
+  // coupling 4 adders makes a 32-bit adder, note that overflow flags do not matter except for the last one
+  FullAdder4bit #50 adder0(ans[3:0], cout0, _, opA[3:0], finalB[3:0], command[0]);  // put least significant command bit into the adder carryin since it adds 1 for when subtracting, and 0 when adding
+  FullAdder4bit #50 adder1(ans[7:4], cout1, _1, opA[7:4], finalB[7:4], cout0);
+  FullAdder4bit #50 adder2(ans[11:8], cout2, _2, opA[11:8], finalB[11:8], cout1);
+  FullAdder4bit #50 adder3(ans[15:12], cout3, _3, opA[15:12], finalB[15:12], cout2);
+  FullAdder4bit #50 adder4(ans[19:16], cout4, _4, opA[19:16], finalB[19:16], cout3);
+  FullAdder4bit #50 adder5(ans[23:20], cout5, _5, opA[23:20], finalB[23:20], cout4);
+  FullAdder4bit #50 adder6(ans[27:24], cout6, _6, opA[27:24], finalB[27:24], cout5);
+  FullAdder4bit #50 adder7(ans[31:28], carryout, overflow, opA[31:28], finalB[31:28], cout6);
+
+endmodule
\ No newline at end of file
diff --git a/alu.t.v b/alu.t.v
new file mode 100644
index 0000000..0d35733
--- /dev/null
+++ b/alu.t.v
@@ -0,0 +1,507 @@
+`timescale 1 ns / 1 ps
+`include "alu.v"
+
+module testALU32bit();
+  reg[31:0] a;
+  reg[31:0] b;
+  reg[2:0] ALUcommand; 
+  wire[31:0] finalALUsig;
+  wire flag;
+  wire cout;
+
+  ALUcontrolLUT alu(cout, flag, finalALUsig[31:0], ALUcommand[2:0], a[31:0], b[31:0]);
+
+  initial begin
+    $display("ALU Command  Input A                          Input B                           | Output                           Flag  Carryout");
+    //Test cases add
+    ALUcommand = 3'b000;
+    
+    // 0 + 0
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+  	// 1 + 1
+    a = 32'b00000000000000000000000000000001;
+    b = 32'b00000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000010) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+  	// positive overflow
+    a = 32'b01111111111111111111111111111111;
+    b = 32'b01111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+
+    if((finalALUsig != 32'b11111111111111111111111111111110) || (flag != 1) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+  	// negative overflow
+    a = 32'b10000000000000000000000000000001;
+    b = 32'b10000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+    
+    if((finalALUsig != 32'b00000000000000000000000000000010) || (flag != 1) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+
+    // carryout
+    a = 32'b11111111111111111111111111111111;
+    b = 32'b00000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+    
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+
+
+    //Test cases sub
+    ALUcommand = 3'b001;
+             
+    // a=b=0
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+    
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+
+    // a=b
+    a = 32'b00000000000000000000000000000001;
+    b = 32'b00000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+
+    // a>b, both positive
+    a = 32'b00000000000000000000000000000111;
+    b = 32'b00000000000000000000000000000101;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+    if((finalALUsig != 32'b00000000000000000000000000000010) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end       
+
+    // a<b, both positive
+    a = 32'b00000001000000000000000000000101;
+    b = 32'b00000010000000000000000000000101;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+    
+    if((finalALUsig != 32'b11111111000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end            
+       
+    // |a|>|b|, both negative
+    a = 32'b11111111111111111111111111111101;
+    b = 32'b11111111111111111111111111111110;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    // |a|<|b|, both negative
+    a = 32'b111111111111111111111111111111110;
+    b = 32'b111111111111111111111111111111000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+             
+    if((finalALUsig != 32'b00000000000000000000000000000110) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+
+    // a negative, b positive, no overflow
+    a = 32'b11111111111111111111111111111101;
+    b = 32'b00000000000000000000000000000101;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+
+    if((finalALUsig != 32'b11111111111111111111111111111000) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+
+    // a negative, b positive, overflow
+    a = 32'b10000000000000000000000000000101;
+    b = 32'b01111100000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+
+    if((finalALUsig != 32'b00000100000000000000000000000101) || (flag != 1) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end 
+             
+    // a positive, b negative, no overflow
+    a = 32'b00000000000000000000000000000101;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+      
+         //Here
+               
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000110) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    // a positive, b negative, overflow
+    a = 32'b01111111111111111111101111111111;
+    b = 32'b10000000000000001100000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+      
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111110011101111111111) || (flag != 1) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    //Test cases xor
+    ALUcommand = 3'b010;
+    
+    //a is all 0's
+    a = 32'b00000000000000000000000000000000;
+  	b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+          
+    //b is all 0's
+    b = 32'b00000000000000000000000000000000;
+  	a = 32'b11111111111111111111111111111111;  
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+             
+    //a and b are all 0's
+    a = 32'b00000000000000000000000000000000;
+  	b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    //a and b are all 1's
+  	a = 32'b11111111111111111111111111111111;
+  	b = 32'b11111111111111111111111111111111; 
+    #25000          
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+             
+    //Test cases slt
+    ALUcommand = 3'b011;
+    
+    //a>b, all positive
+  	a = 32'b00000000000000000000000000000010;
+  	b = 32'b00000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+           
+    //a<b, all positive
+    a = 32'b00000000000000000000000000000001;
+  	b = 32'b00000000000000000000000000000010;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000001) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    //a<b, all negative
+    a = 32'b10000000000000000000000000000001;
+  	b = 32'b10000000000000000000000000000010;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000001) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+             
+    //a>b, all negative
+    a = 32'b10000000000000000000000000000010;
+  	b = 32'b10000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+             
+    //a>b, a positive, b negative
+    a = 32'b00000000000000000000000000000001;
+  	b = 32'b10000000000000000000000000000010;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    //a<b, a negative, b positive
+    a = 32'b10000000000000000000000000000001;
+  	b = 32'b00000000000000000000000000000001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);   
+                 
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000001) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end           
+             
+    //Test cases and
+    ALUcommand = 3'b100;
+    // 0 and 0
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    // 0 and 1
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);    
+
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    // 1 and 1
+    a = 32'b11111111111111111111111111111111;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    //Test cases nand
+    ALUcommand = 3'b101;
+    // 0 nand 0
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+                     
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+
+    // 0 nand 1
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end 
+    
+    // 1 nand 1
+    a = 32'b11111111111111111111111111111111;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    //Test cases nor
+    ALUcommand = 3'b110;
+    // 0 nor 0
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+             
+    // 0 nor 1
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+                
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // 1 nor 1
+    a = 32'b11111111111111111111111111111111;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    //Test cases or
+    ALUcommand = 3'b111;
+    // 0 or 0
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b00000000000000000000000000000000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // 0 or 1
+    a = 32'b00000000000000000000000000000000;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+    
+    // 1 or 1
+    a = 32'b11111111111111111111111111111111;
+    b = 32'b11111111111111111111111111111111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // add
+    ALUcommand = 3'b000;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111110) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end
+
+    // sub
+    ALUcommand = 3'b001;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 1)) begin
+      $display("Test Case Failed");
+    end
+
+    // xor
+    ALUcommand = 3'b010;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // slt
+    ALUcommand = 3'b011;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // and
+    ALUcommand = 3'b100;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // nand
+    ALUcommand = 3'b101;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // nor
+    ALUcommand = 3'b110;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b00000000000000000000000000000000) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+
+    // or
+    ALUcommand = 3'b111;
+    #25000
+    $display("%b           %b %b | %b %b     %b", ALUcommand, a, b, finalALUsig, flag, cout);
+    // Verify expectations and report test result
+    if((finalALUsig != 32'b11111111111111111111111111111111) || (flag != 0) || (cout != 0)) begin
+      $display("Test Case Failed");
+    end
+  end
+endmodule
\ No newline at end of file
diff --git a/alu.v b/alu.v
new file mode 100644
index 0000000..8ee1ec0
--- /dev/null
+++ b/alu.v
@@ -0,0 +1,57 @@
+//final 32-bit ALU
+
+`include "adder_subtracter.v"
+`include "slt.v" 
+`include "and_32bit.v"
+`include "nand_32bit.v"
+`include "xor_32bit.v"
+`include "nor_32bit.v"
+`include "or_32bit.v"
+
+module ALUcontrolLUT 
+(
+	output reg cout, //addsub only
+	output reg flag, //addsub only
+	output reg[31:0] finalsignal,
+	input [2:0]ALUcommand,
+	input [31:0]a,
+	input [31:0]b
+
+
+);
+//everything going through the different parts
+wire [31:0]addsub;
+wire [31:0]xorin;
+wire [31:0]slt;
+wire [31:0]andin;
+wire [31:0]nandin;
+wire [31:0]norin;
+wire [31:0]orin;
+wire adder_cout;
+wire adder_flag;
+
+adder_subtracter addsub0(addsub[31:0],adder_cout,adder_flag,a[31:0],b[31:0],ALUcommand[2:0]);
+xor_32bit xor0(xorin[31:0],a[31:0],b[31:0]);
+full_slt_32bit slt0(slt[31:0],a[31:0],b[31:0]);
+and_32bit and0(andin[31:0],a[31:0],b[31:0]);
+nand_32bit nand0(nandin[31:0],a[31:0],b[31:0]);
+nor_32bit nor0(norin[31:0],a[31:0],b[31:0]);
+or_32bit or0(orin[31:0],a[31:0],b[31:0]);
+
+
+  // update on changes to ALUcommand, a, or b
+  always @(ALUcommand or a or b) 
+  	begin
+    #5000
+    case (ALUcommand)
+      3'b000:  begin finalsignal[31:0] = addsub[31:0]; cout = adder_cout; flag = adder_flag; end
+      3'b001:  begin finalsignal[31:0] = addsub[31:0]; cout = adder_cout; flag = adder_flag; end
+      3'b010:  begin finalsignal[31:0] = xorin[31:0]; cout = 0; flag = 0; end // carryout and flag should be 0 for all non-add/sub operations
+      3'b011:  begin finalsignal[31:0] = slt[31:0]; cout = 0; flag = 0; end
+      3'b100:  begin finalsignal[31:0] = andin[31:0]; cout = 0; flag = 0; end
+      3'b101: begin finalsignal[31:0] = nandin[31:0]; cout = 0; flag = 0; end
+      3'b110:  begin finalsignal[31:0] = norin[31:0]; cout = 0; flag = 0; end
+      3'b111:   begin finalsignal[31:0] = orin[31:0]; cout = 0; flag = 0; end
+    endcase
+    end
+endmodule
diff --git a/and_32bit.t.v b/and_32bit.t.v
new file mode 100644
index 0000000..5857179
--- /dev/null
+++ b/and_32bit.t.v
@@ -0,0 +1,36 @@
+`timescale 1 ns / 1 ps
+`include "and_32bit.v"
+
+module test32bitand();
+	reg[31:0] a;
+	reg[31:0] b;
+	wire[31:0] ans;
+
+	and_32bit and32(ans, a[31:0], b[31:0]);
+
+	initial begin
+		// 00000000000000000000000000000000 00000000000000000000000000000000
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=0; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000001 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000010 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000000 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 11000000000000000000000000000000 10000000000000000000000000000001
+		a[31]=1;a[30]=1;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 10000000000000000000000000000000 11000000000000000000000000000001
+		a[31]=1;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=1;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+	end
+endmodule
\ No newline at end of file
diff --git a/and_32bit.v b/and_32bit.v
new file mode 100644
index 0000000..2657eb5
--- /dev/null
+++ b/and_32bit.v
@@ -0,0 +1,40 @@
+// 32 bit and module
+module and_32bit
+	(	output[31:0] out,
+		input[31:0] a,
+		input[31:0] b
+	);
+    // and each bit
+	and #20 bit0(out[0], a[0], b[0]);
+	and #20 bit1(out[1], a[1], b[1]);
+    and #20 bit2(out[2], a[2], b[2]);
+    and #20 bit3(out[3], a[3], b[3]);
+    and #20 bit4(out[4], a[4], b[4]);
+    and #20 bit5(out[5], a[5], b[5]);
+    and #20 bit6(out[6], a[6], b[6]);
+    and #20 bit7(out[7], a[7], b[7]);
+    and #20 bit8(out[8], a[8], b[8]);
+    and #20 bit9(out[9], a[9], b[9]);
+    and #20 bit10(out[10], a[10], b[10]);
+    and #20 bit11(out[11], a[11], b[11]);
+    and #20 bit12(out[12], a[12], b[12]);
+    and #20 bit13(out[13], a[13], b[13]);
+    and #20 bit14(out[14], a[14], b[14]);
+    and #20 bit15(out[15], a[15], b[15]);
+    and #20 bit16(out[16], a[16], b[16]);
+    and #20 bit17(out[17], a[17], b[17]);
+    and #20 bit18(out[18], a[18], b[18]);
+    and #20 bit19(out[19], a[19], b[19]);
+    and #20 bit20(out[20], a[20], b[20]);
+    and #20 bit21(out[21], a[21], b[21]);
+    and #20 bit22(out[22], a[22], b[22]);
+    and #20 bit23(out[23], a[23], b[23]);
+    and #20 bit24(out[24], a[24], b[24]);
+    and #20 bit25(out[25], a[25], b[25]);
+    and #20 bit26(out[26], a[26], b[26]);
+    and #20 bit27(out[27], a[27], b[27]);
+    and #20 bit28(out[28], a[28], b[28]);
+    and #20 bit29(out[29], a[29], b[29]);
+    and #20 bit30(out[30], a[30], b[30]);
+    and #20 bit31(out[31], a[31], b[31]);
+endmodule
diff --git a/nand_32bit.t.v b/nand_32bit.t.v
new file mode 100644
index 0000000..28a4791
--- /dev/null
+++ b/nand_32bit.t.v
@@ -0,0 +1,36 @@
+`timescale 1 ns / 1 ps
+`include "nand_32bit.v"
+
+module test32bitnand();
+	reg[31:0] a;
+	reg[31:0] b;
+	wire[31:0] ans;
+
+	nand_32bit nand32(ans, a[31:0], b[31:0]);
+
+	initial begin
+		// 00000000000000000000000000000000 00000000000000000000000000000000
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=0; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000001 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000010 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000000 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 11000000000000000000000000000000 10000000000000000000000000000001
+		a[31]=1;a[30]=1;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 10000000000000000000000000000000 11000000000000000000000000000001
+		a[31]=1;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=1;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+	end
+endmodule
\ No newline at end of file
diff --git a/nand_32bit.v b/nand_32bit.v
new file mode 100644
index 0000000..80eb02d
--- /dev/null
+++ b/nand_32bit.v
@@ -0,0 +1,40 @@
+// 32 bit nand module
+module nand_32bit
+	(	output[31:0] out,
+		input[31:0] a,
+		input[31:0] b
+	);
+    // nand each bit
+	nand #10 bit0(out[0], a[0], b[0]);
+	nand #10 bit1(out[1], a[1], b[1]);
+    nand #10 bit2(out[2], a[2], b[2]);
+    nand #10 bit3(out[3], a[3], b[3]);
+    nand #10 bit4(out[4], a[4], b[4]);
+    nand #10 bit5(out[5], a[5], b[5]);
+    nand #10 bit6(out[6], a[6], b[6]);
+    nand #10 bit7(out[7], a[7], b[7]);
+    nand #10 bit8(out[8], a[8], b[8]);
+    nand #10 bit9(out[9], a[9], b[9]);
+    nand #10 bit10(out[10], a[10], b[10]);
+    nand #10 bit11(out[11], a[11], b[11]);
+    nand #10 bit12(out[12], a[12], b[12]);
+    nand #10 bit13(out[13], a[13], b[13]);
+    nand #10 bit14(out[14], a[14], b[14]);
+    nand #10 bit15(out[15], a[15], b[15]);
+    nand #10 bit16(out[16], a[16], b[16]);
+    nand #10 bit17(out[17], a[17], b[17]);
+    nand #10 bit18(out[18], a[18], b[18]);
+    nand #10 bit19(out[19], a[19], b[19]);
+    nand #10 bit20(out[20], a[20], b[20]);
+    nand #10 bit21(out[21], a[21], b[21]);
+    nand #10 bit22(out[22], a[22], b[22]);
+    nand #10 bit23(out[23], a[23], b[23]);
+    nand #10 bit24(out[24], a[24], b[24]);
+    nand #10 bit25(out[25], a[25], b[25]);
+    nand #10 bit26(out[26], a[26], b[26]);
+    nand #10 bit27(out[27], a[27], b[27]);
+    nand #10 bit28(out[28], a[28], b[28]);
+    nand #10 bit29(out[29], a[29], b[29]);
+    nand #10 bit30(out[30], a[30], b[30]);
+    nand #10 bit31(out[31], a[31], b[31]);
+endmodule
diff --git a/nor_32bit.t.v b/nor_32bit.t.v
new file mode 100644
index 0000000..619fd4a
--- /dev/null
+++ b/nor_32bit.t.v
@@ -0,0 +1,36 @@
+`timescale 1 ns / 1 ps
+`include "nor_32bit.v"
+
+module test32bitnor();
+	reg[31:0] a;
+	reg[31:0] b;
+	wire[31:0] ans;
+
+	nor_32bit nor32(ans, a[31:0], b[31:0]);
+
+	initial begin
+		// 00000000000000000000000000000000 00000000000000000000000000000000
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=0; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000001 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000010 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000000 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 11000000000000000000000000000000 10000000000000000000000000000001
+		a[31]=1;a[30]=1;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 10000000000000000000000000000000 11000000000000000000000000000001
+		a[31]=1;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=1;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+	end
+endmodule
\ No newline at end of file
diff --git a/nor_32bit.v b/nor_32bit.v
new file mode 100644
index 0000000..74e3787
--- /dev/null
+++ b/nor_32bit.v
@@ -0,0 +1,40 @@
+// 32 bit nor module
+module nor_32bit
+	(	output[31:0] out,
+		input[31:0] a,
+		input[31:0] b
+	);
+    //  nor each bit
+	nor #10 bit0(out[0], a[0], b[0]);
+	nor #10 bit1(out[1], a[1], b[1]);
+    nor #10 bit2(out[2], a[2], b[2]);
+    nor #10 bit3(out[3], a[3], b[3]);
+    nor #10 bit4(out[4], a[4], b[4]);
+    nor #10 bit5(out[5], a[5], b[5]);
+    nor #10 bit6(out[6], a[6], b[6]);
+    nor #10 bit7(out[7], a[7], b[7]);
+    nor #10 bit8(out[8], a[8], b[8]);
+    nor #10 bit9(out[9], a[9], b[9]);
+    nor #10 bit10(out[10], a[10], b[10]);
+    nor #10 bit11(out[11], a[11], b[11]);
+    nor #10 bit12(out[12], a[12], b[12]);
+    nor #10 bit13(out[13], a[13], b[13]);
+    nor #10 bit14(out[14], a[14], b[14]);
+    nor #10 bit15(out[15], a[15], b[15]);
+    nor #10 bit16(out[16], a[16], b[16]);
+    nor #10 bit17(out[17], a[17], b[17]);
+    nor #10 bit18(out[18], a[18], b[18]);
+    nor #10 bit19(out[19], a[19], b[19]);
+    nor #10 bit20(out[20], a[20], b[20]);
+    nor #10 bit21(out[21], a[21], b[21]);
+    nor #10 bit22(out[22], a[22], b[22]);
+    nor #10 bit23(out[23], a[23], b[23]);
+    nor #10 bit24(out[24], a[24], b[24]);
+    nor #10 bit25(out[25], a[25], b[25]);
+    nor #10 bit26(out[26], a[26], b[26]);
+    nor #10 bit27(out[27], a[27], b[27]);
+    nor #10 bit28(out[28], a[28], b[28]);
+    nor #10 bit29(out[29], a[29], b[29]);
+    nor #10 bit30(out[30], a[30], b[30]);
+    nor #10 bit31(out[31], a[31], b[31]);
+endmodule
diff --git a/or_32bit.t.v b/or_32bit.t.v
new file mode 100644
index 0000000..bb19ef6
--- /dev/null
+++ b/or_32bit.t.v
@@ -0,0 +1,30 @@
+`timescale 1 ns / 1 ps
+`include "or_32bit.v"
+
+module test32bitor();
+	reg[31:0] a;
+	reg[31:0] b;
+	wire[31:0] ans;
+
+	or_32bit or32(ans, a[31:0], b[31:0]);
+
+	initial begin
+		a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000000; #5000
+		$display("%b %b | %b", a, b, ans);
+
+		a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000001; #5000
+		$display("%b %b | %b", a, b, ans);
+
+		a=32'b00000000000000000000000000000010; b=32'b00000000000000000000000000000001; #5000
+		$display("%b %b | %b", a, b, ans);
+
+		a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001; #5000
+		$display("%b %b | %b", a, b, ans);
+
+		a=32'b11000000000000000000000000000000; b=32'b10000000000000000000000000000001; #5000
+		$display("%b %b | %b", a, b, ans);
+
+		a=32'b10000000000000000000000000000000; b=32'b11000000000000000000000000000001; #5000
+		$display("%b %b | %b", a, b, ans);
+	end
+endmodule
\ No newline at end of file
diff --git a/or_32bit.v b/or_32bit.v
new file mode 100644
index 0000000..58abb22
--- /dev/null
+++ b/or_32bit.v
@@ -0,0 +1,40 @@
+// 32 bit or module
+module or_32bit
+    (   output[31:0] out,
+        input[31:0] a,
+        input[31:0] b
+    );
+    // or each bit
+    or #20 bit0(out[0], a[0], b[0]);
+    or #20 bit1(out[1], a[1], b[1]);
+    or #20 bit2(out[2], a[2], b[2]);
+    or #20 bit3(out[3], a[3], b[3]);
+    or #20 bit4(out[4], a[4], b[4]);
+    or #20 bit5(out[5], a[5], b[5]);
+    or #20 bit6(out[6], a[6], b[6]);
+    or #20 bit7(out[7], a[7], b[7]);
+    or #20 bit8(out[8], a[8], b[8]);
+    or #20 bit9(out[9], a[9], b[9]);
+    or #20 bit10(out[10], a[10], b[10]);
+    or #20 bit11(out[11], a[11], b[11]);
+    or #20 bit12(out[12], a[12], b[12]);
+    or #20 bit13(out[13], a[13], b[13]);
+    or #20 bit14(out[14], a[14], b[14]);
+    or #20 bit15(out[15], a[15], b[15]);
+    or #20 bit16(out[16], a[16], b[16]);
+    or #20 bit17(out[17], a[17], b[17]);
+    or #20 bit18(out[18], a[18], b[18]);
+    or #20 bit19(out[19], a[19], b[19]);
+    or #20 bit20(out[20], a[20], b[20]);
+    or #20 bit21(out[21], a[21], b[21]);
+    or #20 bit22(out[22], a[22], b[22]);
+    or #20 bit23(out[23], a[23], b[23]);
+    or #20 bit24(out[24], a[24], b[24]);
+    or #20 bit25(out[25], a[25], b[25]);
+    or #20 bit26(out[26], a[26], b[26]);
+    or #20 bit27(out[27], a[27], b[27]);
+    or #20 bit28(out[28], a[28], b[28]);
+    or #20 bit29(out[29], a[29], b[29]);
+    or #20 bit30(out[30], a[30], b[30]);
+    or #20 bit31(out[31], a[31], b[31]);
+endmodule
\ No newline at end of file
diff --git a/report.pdf b/report.pdf
new file mode 100644
index 0000000..3ca2630
Binary files /dev/null and b/report.pdf differ
diff --git a/slt.t.v b/slt.t.v
new file mode 100644
index 0000000..b5415f9
--- /dev/null
+++ b/slt.t.v
@@ -0,0 +1,40 @@
+`timescale 1 ns / 1 ps
+`include "slt.v"
+
+module test32bitslt();
+	reg[31:0] a;
+	reg[31:0] b;
+	wire[31:0] ans;
+
+	full_slt_32bit slt(ans, a[31:0], b[31:0]);
+
+	initial begin
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=0; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=0; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a[31]=1;a[30]=1;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a[31]=1;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=1;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a = 32'b00000000000000000000000000001111;
+		b = 32'b11111111111111111111111111110000;
+		#5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		a = 32'b11111111111111111111111111110000;
+		b = 32'b00000000000000000000000000001111;
+		#5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+	end
+endmodule
\ No newline at end of file
diff --git a/slt.v b/slt.v
new file mode 100644
index 0000000..ba7127f
--- /dev/null
+++ b/slt.v
@@ -0,0 +1,110 @@
+// single bit slt that performs (a<b)?1:0
+module single_slt
+	(
+		output out,
+		input a,
+		input b,
+		input defaultCompare
+	);
+	wire abxor;
+	wire bxorand;
+	wire xornot;
+	wire xornotand;
+	xor #10 axb(abxor, a, b);
+	and #20 baxb(bxorand, b, abxor);
+	not #10 invxor(xornot, abxor);
+	and #20 xorandinput(xornotand, xornot, defaultCompare);
+	or #20 compare(out, bxorand, xornotand);
+endmodule
+
+// single bit slt that performs (b<a)?1:0
+module single_slt_reversed
+    (
+        output out,
+        input a,
+        input b,
+        input defaultCompare
+    );
+    wire abxor;
+    wire axorand;
+    wire xornot;
+    wire xornotand;
+    xor #10 axb(abxor, a, b);
+    and #20 aaxb(axorand, a, abxor);
+    not #10 invxor(xornot, abxor);
+    and #20 xorandinput(xornotand, xornot, defaultCompare);
+    or #20 compare(out, axorand, xornotand);
+endmodule
+
+// 32 bit slt that handles two's complement
+module full_slt_32bit
+	(
+		output[31:0] out,
+		input[31:0] a,
+		input[31:0] b
+	);
+	wire slt0;
+	wire slt1;
+    wire slt2;
+    wire slt3;
+    wire slt4;
+    wire slt5;
+    wire slt6;
+    wire slt7;
+    wire slt8;
+    wire slt9;
+    wire slt10;
+    wire slt11;
+    wire slt12;
+    wire slt13;
+    wire slt14;
+    wire slt15;
+    wire slt16;
+    wire slt17;
+    wire slt18;
+    wire slt19;
+    wire slt20;
+    wire slt21;
+    wire slt22;
+    wire slt23;
+    wire slt24;
+    wire slt25;
+    wire slt26;
+    wire slt27;
+    wire slt28;
+    wire slt29;
+    wire slt30;
+    // each smaller slt feeds into one higher significant bit
+    single_slt bit0(slt0, a[0], b[0], 0);
+    single_slt bit1(slt1, a[1], b[1], slt0);
+    single_slt bit2(slt2, a[2], b[2], slt1);
+    single_slt bit3(slt3, a[3], b[3], slt2);
+    single_slt bit4(slt4, a[4], b[4], slt3);
+    single_slt bit5(slt5, a[5], b[5], slt4);
+    single_slt bit6(slt6, a[6], b[6], slt5);
+    single_slt bit7(slt7, a[7], b[7], slt6);
+    single_slt bit8(slt8, a[8], b[8], slt7);
+    single_slt bit9(slt9, a[9], b[9], slt8);
+    single_slt bit10(slt10, a[10], b[10], slt9);
+    single_slt bit11(slt11, a[11], b[11], slt10);
+    single_slt bit12(slt12, a[12], b[12], slt11);
+    single_slt bit13(slt13, a[13], b[13], slt12);
+    single_slt bit14(slt14, a[14], b[14], slt13);
+    single_slt bit15(slt15, a[15], b[15], slt14);
+    single_slt bit16(slt16, a[16], b[16], slt15);
+    single_slt bit17(slt17, a[17], b[17], slt16);
+    single_slt bit18(slt18, a[18], b[18], slt17);
+    single_slt bit19(slt19, a[19], b[19], slt18);
+    single_slt bit20(slt20, a[20], b[20], slt19);
+    single_slt bit21(slt21, a[21], b[21], slt20);
+    single_slt bit22(slt22, a[22], b[22], slt21);
+    single_slt bit23(slt23, a[23], b[23], slt22);
+    single_slt bit24(slt24, a[24], b[24], slt23);
+    single_slt bit25(slt25, a[25], b[25], slt24);
+    single_slt bit26(slt26, a[26], b[26], slt25);
+    single_slt bit27(slt27, a[27], b[27], slt26);
+    single_slt bit28(slt28, a[28], b[28], slt27);
+    single_slt bit29(slt29, a[29], b[29], slt28);
+    single_slt bit30(slt30, a[30], b[30], slt29);
+    single_slt_reversed bit31(out, a[31], b[31], slt30);
+endmodule
\ No newline at end of file
diff --git a/work_plan.txt b/work_plan.txt
new file mode 100644
index 0000000..9f6eef3
--- /dev/null
+++ b/work_plan.txt
@@ -0,0 +1,12 @@
+Create ALU in Verilog
+	Implement ADD, SUB, XOR, SLT -  1 hour - 10/8
+
+	Implement AND, NAND, OR, NOR - 0.5 hours - 10/8
+
+Create testbenches - 1.5 hours - 10/9
+
+Set timing - 1 hour- 10/9
+
+Test ALU in Verilog - 1 hour - 10/9
+
+Write report- 2 hours - 10/11
diff --git a/xor_32bit.t.v b/xor_32bit.t.v
new file mode 100644
index 0000000..bbd0725
--- /dev/null
+++ b/xor_32bit.t.v
@@ -0,0 +1,36 @@
+`timescale 1 ns / 1 ps
+`include "xor_32bit.v"
+
+module test32bitxor();
+	reg[31:0] a;
+	reg[31:0] b;
+	wire[31:0] ans;
+
+	xor_32bit xor32(ans, a[31:0], b[31:0]);
+
+	initial begin
+		// 00000000000000000000000000000000 00000000000000000000000000000000
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=0; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000001 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000010 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 00000000000000000000000000000000 00000000000000000000000000000001
+		a[31]=0;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=0;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 11000000000000000000000000000000 10000000000000000000000000000001
+		a[31]=1;a[30]=1;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=0;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+
+		// 10000000000000000000000000000000 11000000000000000000000000000001
+		a[31]=1;a[30]=0;a[29]=0;a[28]=0;a[27]=0;a[26]=0;a[25]=0;a[24]=0;a[23]=0;a[22]=0;a[21]=0;a[20]=0;a[19]=0;a[18]=0;a[17]=0;a[16]=0;a[15]=0;a[14]=0;a[13]=0;a[12]=0;a[11]=0;a[10]=0;a[9]=0;a[8]=0;a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; b[31]=1;b[30]=1;b[29]=0;b[28]=0;b[27]=0;b[26]=0;b[25]=0;b[24]=0;b[23]=0;b[22]=0;b[21]=0;b[20]=0;b[19]=0;b[18]=0;b[17]=0;b[16]=0;b[15]=0;b[14]=0;b[13]=0;b[12]=0;b[11]=0;b[10]=0;b[9]=0;b[8]=0;b[7]=0;b[6]=0;b[5]=0;b[4]=0;b[3]=0;b[2]=0;b[1]=0;b[0]=1; #5000
+		$display("%b %b | %b", a[31:0], b[31:0], ans[31:0]);
+	end
+endmodule
\ No newline at end of file
diff --git a/xor_32bit.v b/xor_32bit.v
new file mode 100644
index 0000000..8f749b3
--- /dev/null
+++ b/xor_32bit.v
@@ -0,0 +1,40 @@
+// 32 bit xor module
+module xor_32bit
+    (   output[31:0] out,
+        input[31:0] a,
+        input[31:0] b
+    );
+    // xor each bit
+    xor #10 bit0(out[0], a[0], b[0]);
+    xor #10 bit1(out[1], a[1], b[1]);
+    xor #10 bit2(out[2], a[2], b[2]);
+    xor #10 bit3(out[3], a[3], b[3]);
+    xor #10 bit4(out[4], a[4], b[4]);
+    xor #10 bit5(out[5], a[5], b[5]);
+    xor #10 bit6(out[6], a[6], b[6]);
+    xor #10 bit7(out[7], a[7], b[7]);
+    xor #10 bit8(out[8], a[8], b[8]);
+    xor #10 bit9(out[9], a[9], b[9]);
+    xor #10 bit10(out[10], a[10], b[10]);
+    xor #10 bit11(out[11], a[11], b[11]);
+    xor #10 bit12(out[12], a[12], b[12]);
+    xor #10 bit13(out[13], a[13], b[13]);
+    xor #10 bit14(out[14], a[14], b[14]);
+    xor #10 bit15(out[15], a[15], b[15]);
+    xor #10 bit16(out[16], a[16], b[16]);
+    xor #10 bit17(out[17], a[17], b[17]);
+    xor #10 bit18(out[18], a[18], b[18]);
+    xor #10 bit19(out[19], a[19], b[19]);
+    xor #10 bit20(out[20], a[20], b[20]);
+    xor #10 bit21(out[21], a[21], b[21]);
+    xor #10 bit22(out[22], a[22], b[22]);
+    xor #10 bit23(out[23], a[23], b[23]);
+    xor #10 bit24(out[24], a[24], b[24]);
+    xor #10 bit25(out[25], a[25], b[25]);
+    xor #10 bit26(out[26], a[26], b[26]);
+    xor #10 bit27(out[27], a[27], b[27]);
+    xor #10 bit28(out[28], a[28], b[28]);
+    xor #10 bit29(out[29], a[29], b[29]);
+    xor #10 bit30(out[30], a[30], b[30]);
+    xor #10 bit31(out[31], a[31], b[31]);
+endmodule