diff --git a/AND.PNG b/AND.PNG new file mode 100644 index 0000000..1e3e569 Binary files /dev/null and b/AND.PNG differ diff --git a/Diagram_Page_1.png b/Diagram_Page_1.png new file mode 100644 index 0000000..42b4363 Binary files /dev/null and b/Diagram_Page_1.png differ diff --git a/Diagram_Page_2.png b/Diagram_Page_2.png new file mode 100644 index 0000000..60d10f6 Binary files /dev/null and b/Diagram_Page_2.png differ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..447df6d --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +test: build + ./alu + +build: alu.t.v alu.v alu1.v + iverilog alu.t.v -o alu + +clean: + rm alu + diff --git a/NAND.PNG b/NAND.PNG new file mode 100644 index 0000000..ad25e8b Binary files /dev/null and b/NAND.PNG differ diff --git a/NOR.PNG b/NOR.PNG new file mode 100644 index 0000000..8b74417 Binary files /dev/null and b/NOR.PNG differ diff --git a/OR.PNG b/OR.PNG new file mode 100644 index 0000000..d382074 Binary files /dev/null and b/OR.PNG differ diff --git a/SLT.PNG b/SLT.PNG new file mode 100644 index 0000000..45f39e4 Binary files /dev/null and b/SLT.PNG differ diff --git a/Subtraction.PNG b/Subtraction.PNG new file mode 100644 index 0000000..3442488 Binary files /dev/null and b/Subtraction.PNG differ diff --git a/Writeup.md b/Writeup.md new file mode 100644 index 0000000..0fd3c5c --- /dev/null +++ b/Writeup.md @@ -0,0 +1,56 @@ +## Implementation +Going into this lab we knew the bigget decision to be made for the ALU would be whether to implement it through a bit slice method or individualy via several independent logic circuits through a decoder. In the end we decided to use a bit slice because it is much easier to define dynamically and in the end should result in a more compact design. + +### Bit Slice +We broke up the alu into a bit sliced implementation. Basically we made a bunch of one bit ALUs and strung their carryouts to the next ALUs carryin. The bit slices accepted their opcodes in unary instead of binary, meaning that they had eight wires, one for each opcode, one of which would be high at a time. The meant we needed only one decoder, but we had to invent a unary multiplexer to output the result. + +Only three of the opcodes use carry functionality: add, sub, and slt. + +### SLT +Our bit sliced SLT uses carryin and carryout to compare numbers without addition or subtraction. It's Basically a recursive compare algorithm. Ignoring sign for now, if the last bit of A is greater than the last bit of B, A is greater than B. If it is less, A is not greater than B. If they are equal, then you move on to the next bit, and compare them. By sending the result up the carry chain when the nth bit of A matches the nth bit of B, we get a bit by bit comparison of A and B, which doesn't even always need to wait for the carry to go all the way through. By passing a 0 to the first carry in, we get SLT. If we passed a 1 to the first carry in, we would have LTE. + +Finally, we just set the first bit of the result to the value of carryout. This is done outside of the bit slice. + +This implemenation is always wrong if the signs of the operands are different, so we just negate the output if that is the case. + +### ALU +The first thing that the ALU does when it recieves information (op A, op B, command) is expand the command from a 3 bit binary bus to a 7 bit one-hot bus. This operation if not implemented in the top level of the ALU would be required in each ALU sliced bit individually, so in this case implementing it once for the top level gives a 32 fold gate reduction. + +#### Subtraction +In the case of subtraction the LSB of the carryin bus is flipped to a 1 and each individual bit of the B operand is flipped by the 1 bit ALU slices which then do single bit addition, resulting in a subtraction action. + +#### Addition +In the case of addition each the LSB of the carryin bus is left empty and the carryout of each 1 bit ALU slice is connected to the carryin of the next bit, with the final connected to an AND gate to enable the carryout flag. + +### Implementation Diagram +![dg1](https://github.com/TShapinsky/Lab1/blob/master/Diagram_Page_1.png?raw=true) +![dg2](https://github.com/TShapinsky/Lab1/blob/master/Diagram_Page_2.png?raw=true) + +## Test Results +After some difficulties with post processing, we got our tests to pass. We weren't sure if carryout and zero were flags that should not be set for other operands beside ADD and SUB, so we didn't test that. + +### Test Choice +We chose tests that would cover edge cases for the difficult operands: overflow and underflow for subtraction and addition, and all the +/- permutations for SLT. We also chose some more standard tests for each operator. + +### Test Driven Development Catches Bugs +We waited until after writing the ALU to begin writing comprehensive test cases. After writing just two test cases we were able to find and fix two bugs in post-processing. We were incorrectly diagnosing overflow on subtraction, because the signs must not match for overflow to occur in subtraction. We also found a typo where we were XORin instead of ORing. + +## Timing +### Addition +![add](https://github.com/TShapinsky/Lab1/blob/master/addition.PNG?raw=true) +### Subtraction +![sub](https://github.com/TShapinsky/Lab1/blob/master/Subtraction.PNG?raw=true) +### XOR +![xor](https://github.com/TShapinsky/Lab1/blob/master/XOR.PNG?raw=true) +### SLT +![slt](https://github.com/TShapinsky/Lab1/blob/master/SLT.PNG?raw=true) +### AND +![and](https://github.com/TShapinsky/Lab1/blob/master/AND.PNG?raw=true) +### NAND +![nand](https://github.com/TShapinsky/Lab1/blob/master/NAND.PNG?raw=true) +### NOR +![nor](https://github.com/TShapinsky/Lab1/blob/master/NOR.PNG?raw=true) +### OR +![or](https://github.com/TShapinsky/Lab1/blob/master/OR.PNG?raw=true) +## Work Plan Reflection +Writing the implementation happened fairly quickly in about the time we predicted, however the act of gathering information and creating visuals for the final write up turned out to be more time intensive than we had planned diff --git a/XOR.PNG b/XOR.PNG new file mode 100644 index 0000000..dfcafd0 Binary files /dev/null and b/XOR.PNG differ diff --git a/ZYBO_Master.xdc b/ZYBO_Master.xdc new file mode 100644 index 0000000..f3dbb71 --- /dev/null +++ b/ZYBO_Master.xdc @@ -0,0 +1,146 @@ +## This file is a general .xdc for the ZYBO Rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used signals according to the project + + +##Clock signal +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; + + +##Switches +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 + + +##Buttons +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 + + +##LEDs +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 + + +##I2S Audio Codec +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC + + +##Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B + + +##HDMI Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA + + +##Pmod Header JA (XADC) +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N + + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N + + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N + + +##Pmod Header JE +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 + + +##USB-OTG overcurrent detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC + + +##VGA Connector +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS diff --git a/addition.PNG b/addition.PNG new file mode 100644 index 0000000..edc5e77 Binary files /dev/null and b/addition.PNG differ diff --git a/alu b/alu new file mode 100755 index 0000000..2d42b94 --- /dev/null +++ b/alu @@ -0,0 +1,19233 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0xc983a0 .scope module, "testALU" "testALU" 2 4; + .timescale -9 -12; +v0x127adc0_0 .var/s "a", 31 0; +v0x127aed0_0 .var/s "b", 31 0; +v0x127afa0_0 .net "carryout", 0 0, L_0x13d1e20; 1 drivers +v0x127b0a0_0 .var "command", 2 0; +v0x127b170_0 .net "overflow", 0 0, L_0x13db5a0; 1 drivers +v0x127b210_0 .net/s "result", 31 0, L_0x13dffe0; 1 drivers +v0x127b300_0 .net "zero", 0 0, L_0x13da990; 1 drivers +S_0xc4eec0 .scope module, "dut" "ALU" 2 14, 3 2 0, S_0xc983a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 3 "command" +L_0x13d0b90/d .functor OR 1, L_0x13d2f40, L_0x13d1d80, C4<0>, C4<0>; +L_0x13d0b90 .delay 1 (30000,30000,30000) L_0x13d0b90/d; +L_0x13d1e20/d .functor OR 1, L_0x13d1e90, L_0x13d1f30, C4<0>, C4<0>; +L_0x13d1e20 .delay 1 (30000,30000,30000) L_0x13d1e20/d; +L_0x13daca0/d .functor XNOR 1, L_0x13dadb0, L_0x13d2fe0, C4<0>, C4<0>; +L_0x13daca0 .delay 1 (20000,20000,20000) L_0x13daca0/d; +L_0x13d30d0/d .functor NOT 1, L_0x13daca0, C4<0>, C4<0>, C4<0>; +L_0x13d30d0 .delay 1 (10000,10000,10000) L_0x13d30d0/d; +L_0x13d31e0/d .functor XOR 1, L_0x13db2b0, L_0x13d1e20, C4<0>, C4<0>; +L_0x13d31e0 .delay 1 (30000,30000,30000) L_0x13d31e0/d; +L_0x13dba40/d .functor OR 1, L_0x13dbb50, L_0x13db3a0, C4<0>, C4<0>; +L_0x13dba40 .delay 1 (30000,30000,30000) L_0x13dba40/d; +L_0x13db490/d .functor AND 1, L_0x13d31e0, L_0x13db7a0, C4<1>, C4<1>; +L_0x13db490 .delay 1 (30000,30000,30000) L_0x13db490/d; +L_0x13db5a0/d .functor AND 1, L_0x13db490, L_0x13dba40, C4<1>, C4<1>; +L_0x13db5a0 .delay 1 (30000,30000,30000) L_0x13db5a0/d; +L_0x13dc110/d .functor XOR 1, L_0x13d1e20, L_0x13d30d0, C4<0>, C4<0>; +L_0x13dc110 .delay 1 (30000,30000,30000) L_0x13dc110/d; +L_0x13dbcb0/d .functor AND 1, L_0x13dc110, L_0x13dbe10, C4<1>, C4<1>; +L_0x13dbcb0 .delay 1 (30000,30000,30000) L_0x13dbcb0/d; +v0x1277610_0 .net *"_s106", 0 0, L_0x12de490; 1 drivers +v0x12776f0_0 .net *"_s117", 0 0, L_0x12e6a20; 1 drivers +v0x12777d0_0 .net *"_s128", 0 0, L_0x12f11f0; 1 drivers +v0x1277890_0 .net *"_s139", 0 0, L_0x12fdd80; 1 drivers +v0x1277970_0 .net *"_s150", 0 0, L_0x1306300; 1 drivers +v0x1277aa0_0 .net *"_s161", 0 0, L_0x1310ad0; 1 drivers +v0x1277b80_0 .net *"_s172", 0 0, L_0x131d860; 1 drivers +v0x1277c60_0 .net *"_s18", 0 0, L_0x12863c0; 1 drivers +v0x1277d40_0 .net *"_s183", 0 0, L_0x1325f10; 1 drivers +v0x1277eb0_0 .net *"_s194", 0 0, L_0x1330720; 1 drivers +v0x1277f90_0 .net *"_s205", 0 0, L_0x12ddc60; 1 drivers +v0x1278070_0 .net *"_s216", 0 0, L_0x1346050; 1 drivers +v0x1278150_0 .net *"_s227", 0 0, L_0x13508b0; 1 drivers +v0x1278230_0 .net *"_s238", 0 0, L_0x135d410; 1 drivers +v0x1278310_0 .net *"_s249", 0 0, L_0x1367910; 1 drivers +v0x12783f0_0 .net *"_s260", 0 0, L_0x1372160; 1 drivers +v0x12784d0_0 .net *"_s271", 0 0, L_0x137ecc0; 1 drivers +v0x1278680_0 .net *"_s282", 0 0, L_0x1387200; 1 drivers +v0x1278720_0 .net *"_s29", 0 0, L_0x1287cb0; 1 drivers +v0x1278800_0 .net *"_s293", 0 0, L_0x1391a30; 1 drivers +v0x12788e0_0 .net *"_s304", 0 0, L_0x139e5b0; 1 drivers +v0x12789c0_0 .net *"_s315", 0 0, L_0x13a6b10; 1 drivers +v0x1278aa0_0 .net *"_s326", 0 0, L_0x13b1330; 1 drivers +v0x1278b80_0 .net *"_s337", 0 0, L_0x13c5b30; 1 drivers +v0x1278c60_0 .net *"_s350", 0 0, L_0x13c67f0; 1 drivers +v0x1278d40_0 .net *"_s352", 0 0, L_0x13d0b90; 1 drivers +v0x1278e20_0 .net *"_s356", 0 0, L_0x13d2f40; 1 drivers +v0x1278f00_0 .net *"_s358", 0 0, L_0x13d1d80; 1 drivers +v0x1278fe0_0 .net *"_s360", 0 0, L_0x13d1e90; 1 drivers +v0x12790c0_0 .net *"_s362", 0 0, L_0x13d1f30; 1 drivers +v0x12791a0_0 .net *"_s364", 0 0, L_0x13dadb0; 1 drivers +v0x1279280_0 .net *"_s366", 0 0, L_0x13d2fe0; 1 drivers +v0x1279360_0 .net *"_s368", 0 0, L_0x13db2b0; 1 drivers +v0x12785b0_0 .net *"_s372", 0 0, L_0x13dbb50; 1 drivers +v0x1279630_0 .net *"_s374", 0 0, L_0x13db3a0; 1 drivers +v0x1279710_0 .net *"_s375", 0 0, L_0x13dbcb0; 1 drivers +v0x12797f0_0 .net *"_s379", 0 0, L_0x13dbe10; 1 drivers +v0x12798d0_0 .net *"_s40", 0 0, L_0x12a56c0; 1 drivers +v0x12799b0_0 .net *"_s51", 0 0, L_0x129da40; 1 drivers +v0x1279a90_0 .net *"_s62", 0 0, L_0x12b0960; 1 drivers +v0x1279b70_0 .net *"_s73", 0 0, L_0x12bc230; 1 drivers +v0x1279c50_0 .net *"_s84", 0 0, L_0x12c6be0; 1 drivers +v0x1279d30_0 .net *"_s95", 0 0, L_0x12d1480; 1 drivers +v0x1279e10_0 .net "addOrSub", 0 0, L_0x13dba40; 1 drivers +v0x1279ed0_0 .net "carryinbus", 32 0, L_0x13d0af0; 1 drivers +v0x1279fb0_0 .net "carryout", 0 0, L_0x13d1e20; alias, 1 drivers +v0x127a070_0 .net "command", 2 0, v0x127b0a0_0; 1 drivers +v0x127a150_0 .var "commandslice", 7 0; +v0x127a210_0 .net "mixedSigns", 0 0, L_0x13d30d0; 1 drivers +v0x127a2b0_0 .net "operandA", 31 0, v0x127adc0_0; 1 drivers +v0x127a370_0 .net "operandB", 31 0, v0x127aed0_0; 1 drivers +v0x127a450_0 .net "overFlowPossible", 0 0, L_0x13db7a0; 1 drivers +v0x127a520_0 .net "overflow", 0 0, L_0x13db5a0; alias, 1 drivers +v0x127a5c0_0 .net "overflowPre", 0 0, L_0x13db490; 1 drivers +v0x127a680_0 .net "overrideBus", 31 0, L_0x13dc340; 1 drivers +v0x127a770_0 .net "possibleOverflow", 0 0, L_0x13d31e0; 1 drivers +v0x127a810_0 .net "result", 31 0, L_0x13dffe0; alias, 1 drivers +v0x127a900_0 .net "resultBus", 31 0, L_0x13d0740; 1 drivers +v0x127a9d0_0 .net "sameSigns", 0 0, L_0x13daca0; 1 drivers +v0x127aaa0_0 .net "sltPre", 0 0, L_0x13dc110; 1 drivers +v0x127ab40_0 .net "zero", 0 0, L_0x13da990; alias, 1 drivers +v0x127ac10_0 .net "zerobus", 31 0, L_0x131abd0; 1 drivers +E_0x1020b00 .event edge, v0x127a070_0; +L_0x1285c30 .part v0x127adc0_0, 0, 1; +L_0x1285d90 .part v0x127aed0_0, 0, 1; +L_0x1285e80 .part L_0x13d0af0, 0, 1; +L_0x1290400 .part v0x127adc0_0, 1, 1; +L_0x1290560 .part v0x127aed0_0, 1, 1; +L_0x1290600 .part L_0x13d0af0, 1, 1; +L_0x129ad30 .part v0x127adc0_0, 2, 1; +L_0x129af20 .part v0x127aed0_0, 2, 1; +L_0x129b050 .part L_0x13d0af0, 2, 1; +L_0x12a5620 .part v0x127adc0_0, 3, 1; +L_0x12a5780 .part v0x127aed0_0, 3, 1; +L_0x12a5820 .part L_0x13d0af0, 3, 1; +L_0x12b0030 .part v0x127adc0_0, 4, 1; +L_0x12b0190 .part v0x127aed0_0, 4, 1; +L_0x12b02b0 .part L_0x13d0af0, 4, 1; +L_0x12bb900 .part v0x127adc0_0, 5, 1; +L_0x12bb9a0 .part v0x127aed0_0, 5, 1; +L_0x12bba40 .part L_0x13d0af0, 5, 1; +L_0x12c6100 .part v0x127adc0_0, 6, 1; +L_0x12c6370 .part v0x127aed0_0, 6, 1; +L_0x12bbae0 .part L_0x13d0af0, 6, 1; +L_0x12d0a90 .part v0x127adc0_0, 7, 1; +L_0x12c6520 .part v0x127aed0_0, 7, 1; +L_0x12d0cb0 .part L_0x13d0af0, 7, 1; +L_0x12db380 .part v0x127adc0_0, 8, 1; +L_0x12db4e0 .part v0x127aed0_0, 8, 1; +L_0x12d0e60 .part L_0x13d0af0, 8, 1; +L_0x12e6070 .part v0x127adc0_0, 9, 1; +L_0x12db580 .part v0x127aed0_0, 9, 1; +L_0x12e62c0 .part L_0x13d0af0, 9, 1; +L_0x12f08d0 .part v0x127adc0_0, 10, 1; +L_0x12f0a30 .part v0x127aed0_0, 10, 1; +L_0x12e6360 .part L_0x13d0af0, 10, 1; +L_0x12fb0f0 .part v0x127adc0_0, 11, 1; +L_0x12f0ad0 .part v0x127aed0_0, 11, 1; +L_0x12fb370 .part L_0x13d0af0, 11, 1; +L_0x1305960 .part v0x127adc0_0, 12, 1; +L_0x1305ac0 .part v0x127aed0_0, 12, 1; +L_0x12fb410 .part L_0x13d0af0, 12, 1; +L_0x13101b0 .part v0x127adc0_0, 13, 1; +L_0x1305b60 .part v0x127aed0_0, 13, 1; +L_0x1305c00 .part L_0x13d0af0, 13, 1; +L_0x131a9d0 .part v0x127adc0_0, 14, 1; +L_0x12c6260 .part v0x127aed0_0, 14, 1; +L_0x12c6410 .part L_0x13d0af0, 14, 1; +L_0x1325440 .part v0x127adc0_0, 15, 1; +L_0x131af50 .part v0x127aed0_0, 15, 1; +L_0x131aff0 .part L_0x13d0af0, 15, 1; +L_0x132fe10 .part v0x127adc0_0, 16, 1; +L_0x132ff70 .part v0x127aed0_0, 16, 1; +L_0x1325930 .part L_0x13d0af0, 16, 1; +L_0x133a620 .part v0x127adc0_0, 17, 1; +L_0x1330010 .part v0x127aed0_0, 17, 1; +L_0x13300b0 .part L_0x13d0af0, 17, 1; +L_0x13456c0 .part v0x127adc0_0, 18, 1; +L_0x1345820 .part v0x127aed0_0, 18, 1; +L_0x133a780 .part L_0x13d0af0, 18, 1; +L_0x134ff50 .part v0x127adc0_0, 19, 1; +L_0x13458c0 .part v0x127aed0_0, 19, 1; +L_0x1345960 .part L_0x13d0af0, 19, 1; +L_0x135a7b0 .part v0x127adc0_0, 20, 1; +L_0x135a910 .part v0x127aed0_0, 20, 1; +L_0x13500b0 .part L_0x13d0af0, 20, 1; +L_0x12ba890 .part v0x127adc0_0, 21, 1; +L_0x12ba930 .part v0x127aed0_0, 21, 1; +L_0x12ba9d0 .part L_0x13d0af0, 21, 1; +L_0x1371830 .part v0x127adc0_0, 22, 1; +L_0x1371990 .part v0x127aed0_0, 22, 1; +L_0x1367240 .part L_0x13d0af0, 22, 1; +L_0x137c060 .part v0x127adc0_0, 23, 1; +L_0x1371a30 .part v0x127aed0_0, 23, 1; +L_0x1371ad0 .part L_0x13d0af0, 23, 1; +L_0x13868a0 .part v0x127adc0_0, 24, 1; +L_0x1386a00 .part v0x127aed0_0, 24, 1; +L_0x137c1c0 .part L_0x13d0af0, 24, 1; +L_0x1391100 .part v0x127adc0_0, 25, 1; +L_0x1386aa0 .part v0x127aed0_0, 25, 1; +L_0x1386b40 .part L_0x13d0af0, 25, 1; +L_0x139b930 .part v0x127adc0_0, 26, 1; +L_0x139ba90 .part v0x127aed0_0, 26, 1; +L_0x1391260 .part L_0x13d0af0, 26, 1; +L_0x13a6190 .part v0x127adc0_0, 27, 1; +L_0x139bb30 .part v0x127aed0_0, 27, 1; +L_0x139bbd0 .part L_0x13d0af0, 27, 1; +L_0x13b0a10 .part v0x127adc0_0, 28, 1; +L_0x13b0b70 .part v0x127aed0_0, 28, 1; +L_0x13a62f0 .part L_0x13d0af0, 28, 1; +L_0x13bb230 .part v0x127adc0_0, 29, 1; +L_0x13b0c10 .part v0x127aed0_0, 29, 1; +L_0x13b0cb0 .part L_0x13d0af0, 29, 1; +L_0x13c5a90 .part v0x127adc0_0, 30, 1; +L_0x131ab30 .part v0x127aed0_0, 30, 1; +L_0x13bb390 .part L_0x13d0af0, 30, 1; +LS_0x13d0740_0_0 .concat8 [ 1 1 1 1], L_0x1281d90, L_0x128c510, L_0x1296e90, L_0x12a1780; +LS_0x13d0740_0_4 .concat8 [ 1 1 1 1], L_0x12ac190, L_0x12b69c0, L_0x12c2260, L_0x12ccbf0; +LS_0x13d0740_0_8 .concat8 [ 1 1 1 1], L_0x12d74e0, L_0x12e21d0, L_0x12eca30, L_0x12f7250; +LS_0x13d0740_0_12 .concat8 [ 1 1 1 1], L_0x1301ac0, L_0x130c310, L_0x1316b30, L_0x13215a0; +LS_0x13d0740_0_16 .concat8 [ 1 1 1 1], L_0x132bf70, L_0x1336780, L_0x1341820, L_0x134c0b0; +LS_0x13d0740_0_20 .concat8 [ 1 1 1 1], L_0x1356910, L_0x1361150, L_0x136d990, L_0x13781c0; +LS_0x13d0740_0_24 .concat8 [ 1 1 1 1], L_0x1382a00, L_0x138d260, L_0x1397a90, L_0x13a22f0; +LS_0x13d0740_0_28 .concat8 [ 1 1 1 1], L_0x13acb70, L_0x13b7390, L_0x13c1bf0, L_0x13cc8a0; +LS_0x13d0740_1_0 .concat8 [ 4 4 4 4], LS_0x13d0740_0_0, LS_0x13d0740_0_4, LS_0x13d0740_0_8, LS_0x13d0740_0_12; +LS_0x13d0740_1_4 .concat8 [ 4 4 4 4], LS_0x13d0740_0_16, LS_0x13d0740_0_20, LS_0x13d0740_0_24, LS_0x13d0740_0_28; +L_0x13d0740 .concat8 [ 16 16 0 0], LS_0x13d0740_1_0, LS_0x13d0740_1_4; +LS_0x131abd0_0_0 .concat8 [ 1 1 1 1], L_0x1285b30, L_0x12902b0, L_0x129ac30, L_0x12a5520; +LS_0x131abd0_0_4 .concat8 [ 1 1 1 1], L_0x12aff30, L_0x12bb6a0, L_0x12c6000, L_0x12d0990; +LS_0x131abd0_0_8 .concat8 [ 1 1 1 1], L_0x12db280, L_0x12e5f70, L_0x12f07d0, L_0x12faff0; +LS_0x131abd0_0_12 .concat8 [ 1 1 1 1], L_0x1305860, L_0x13100b0, L_0x131a8d0, L_0x1325340; +LS_0x131abd0_0_16 .concat8 [ 1 1 1 1], L_0x132fd10, L_0x133a520, L_0x13455c0, L_0x134fe50; +LS_0x131abd0_0_20 .concat8 [ 1 1 1 1], L_0x135a6b0, L_0x12ba630, L_0x1371730, L_0x137bf60; +LS_0x131abd0_0_24 .concat8 [ 1 1 1 1], L_0x13867a0, L_0x1391000, L_0x139b830, L_0x13a6090; +LS_0x131abd0_0_28 .concat8 [ 1 1 1 1], L_0x13b0910, L_0x13bb130, L_0x13c5990, L_0x13d0640; +LS_0x131abd0_1_0 .concat8 [ 4 4 4 4], LS_0x131abd0_0_0, LS_0x131abd0_0_4, LS_0x131abd0_0_8, LS_0x131abd0_0_12; +LS_0x131abd0_1_4 .concat8 [ 4 4 4 4], LS_0x131abd0_0_16, LS_0x131abd0_0_20, LS_0x131abd0_0_24, LS_0x131abd0_0_28; +L_0x131abd0 .concat8 [ 16 16 0 0], LS_0x131abd0_1_0, LS_0x131abd0_1_4; +L_0x13d15c0 .part v0x127adc0_0, 31, 1; +L_0x13d09b0 .part v0x127aed0_0, 31, 1; +L_0x13d0a50 .part L_0x13d0af0, 31, 1; +LS_0x13d0af0_0_0 .concat8 [ 1 1 1 1], L_0x13d0b90, L_0x12857d0, L_0x128ff50, L_0x129a8d0; +LS_0x13d0af0_0_4 .concat8 [ 1 1 1 1], L_0x12a51c0, L_0x12afbd0, L_0x12bb340, L_0x12c5ca0; +LS_0x13d0af0_0_8 .concat8 [ 1 1 1 1], L_0x12d0630, L_0x12daf20, L_0x12e5c10, L_0x12f0470; +LS_0x13d0af0_0_12 .concat8 [ 1 1 1 1], L_0x12fac90, L_0x1305500, L_0x130fd50, L_0x131a570; +LS_0x13d0af0_0_16 .concat8 [ 1 1 1 1], L_0x1324fe0, L_0x132f9b0, L_0x133a1c0, L_0x1345260; +LS_0x13d0af0_0_20 .concat8 [ 1 1 1 1], L_0x134faf0, L_0x135a350, L_0x12ba2d0, L_0x13713d0; +LS_0x13d0af0_0_24 .concat8 [ 1 1 1 1], L_0x137bc00, L_0x1386440, L_0x1390ca0, L_0x139b4d0; +LS_0x13d0af0_0_28 .concat8 [ 1 1 1 1], L_0x13a5d30, L_0x13b05b0, L_0x13badd0, L_0x13c5630; +LS_0x13d0af0_0_32 .concat8 [ 1 0 0 0], L_0x13d02e0; +LS_0x13d0af0_1_0 .concat8 [ 4 4 4 4], LS_0x13d0af0_0_0, LS_0x13d0af0_0_4, LS_0x13d0af0_0_8, LS_0x13d0af0_0_12; +LS_0x13d0af0_1_4 .concat8 [ 4 4 4 4], LS_0x13d0af0_0_16, LS_0x13d0af0_0_20, LS_0x13d0af0_0_24, LS_0x13d0af0_0_28; +LS_0x13d0af0_1_8 .concat8 [ 1 0 0 0], LS_0x13d0af0_0_32; +L_0x13d0af0 .concat8 [ 16 16 1 0], LS_0x13d0af0_1_0, LS_0x13d0af0_1_4, LS_0x13d0af0_1_8; +L_0x13d2f40 .part v0x127a150_0, 1, 1; +L_0x13d1d80 .part v0x127a150_0, 1, 1; +L_0x13d1e90 .part L_0x13d0af0, 32, 1; +L_0x13d1f30 .part L_0x13d0af0, 32, 1; +L_0x13dadb0 .part v0x127adc0_0, 31, 1; +L_0x13d2fe0 .part v0x127aed0_0, 31, 1; +L_0x13db2b0 .part L_0x13dffe0, 31, 1; +L_0x13db9a0 .part v0x127a150_0, 0, 1; +L_0x13dbb50 .part v0x127a150_0, 0, 1; +L_0x13db3a0 .part v0x127a150_0, 1, 1; +LS_0x13dc340_0_0 .concat8 [ 1 1 1 1], L_0x13dbcb0, L_0x12863c0, L_0x1287cb0, L_0x12a56c0; +LS_0x13dc340_0_4 .concat8 [ 1 1 1 1], L_0x129da40, L_0x12b0960, L_0x12bc230, L_0x12c6be0; +LS_0x13dc340_0_8 .concat8 [ 1 1 1 1], L_0x12d1480, L_0x12de490, L_0x12e6a20, L_0x12f11f0; +LS_0x13dc340_0_12 .concat8 [ 1 1 1 1], L_0x12fdd80, L_0x1306300, L_0x1310ad0, L_0x131d860; +LS_0x13dc340_0_16 .concat8 [ 1 1 1 1], L_0x1325f10, L_0x1330720, L_0x12ddc60, L_0x1346050; +LS_0x13dc340_0_20 .concat8 [ 1 1 1 1], L_0x13508b0, L_0x135d410, L_0x1367910, L_0x1372160; +LS_0x13dc340_0_24 .concat8 [ 1 1 1 1], L_0x137ecc0, L_0x1387200, L_0x1391a30, L_0x139e5b0; +LS_0x13dc340_0_28 .concat8 [ 1 1 1 1], L_0x13a6b10, L_0x13b1330, L_0x13c5b30, L_0x13c67f0; +LS_0x13dc340_1_0 .concat8 [ 4 4 4 4], LS_0x13dc340_0_0, LS_0x13dc340_0_4, LS_0x13dc340_0_8, LS_0x13dc340_0_12; +LS_0x13dc340_1_4 .concat8 [ 4 4 4 4], LS_0x13dc340_0_16, LS_0x13dc340_0_20, LS_0x13dc340_0_24, LS_0x13dc340_0_28; +L_0x13dc340 .concat8 [ 16 16 0 0], LS_0x13dc340_1_0, LS_0x13dc340_1_4; +L_0x13dbe10 .part v0x127a150_0, 3, 1; +S_0xb981f0 .scope generate, "alu_slices[0]" "alu_slices[0]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x101b510 .param/l "i" 0 3 39, +C4<00>; +S_0xd742a0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0xb981f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x127b3f0/d .functor NOT 1, L_0x1285c30, C4<0>, C4<0>, C4<0>; +L_0x127b3f0 .delay 1 (10000,10000,10000) L_0x127b3f0/d; +L_0x127b500/d .functor NOT 1, L_0x1285d90, C4<0>, C4<0>, C4<0>; +L_0x127b500 .delay 1 (10000,10000,10000) L_0x127b500/d; +L_0x127c740/d .functor XOR 1, L_0x1285c30, L_0x1285d90, C4<0>, C4<0>; +L_0x127c740 .delay 1 (30000,30000,30000) L_0x127c740/d; +L_0x2ac432883018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127c8a0/d .functor OR 1, L_0x2ac432883018, L_0x2ac432883060, C4<0>, C4<0>; +L_0x127c8a0 .delay 1 (30000,30000,30000) L_0x127c8a0/d; +L_0x2ac4328830a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328830f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127d040/d .functor OR 1, L_0x2ac4328830a8, L_0x2ac4328830f0, C4<0>, C4<0>; +L_0x127d040 .delay 1 (30000,30000,30000) L_0x127d040/d; +L_0x127d240/d .functor AND 1, L_0x1285c30, L_0x1285d90, C4<1>, C4<1>; +L_0x127d240 .delay 1 (30000,30000,30000) L_0x127d240/d; +L_0x2ac432883138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127d300/d .functor OR 1, L_0x2ac432883138, L_0x2ac432883180, C4<0>, C4<0>; +L_0x127d300 .delay 1 (30000,30000,30000) L_0x127d300/d; +L_0x127d550/d .functor NAND 1, L_0x1285c30, L_0x1285d90, C4<1>, C4<1>; +L_0x127d550 .delay 1 (20000,20000,20000) L_0x127d550/d; +L_0x2ac4328831c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127d660/d .functor OR 1, L_0x2ac4328831c8, L_0x2ac432883210, C4<0>, C4<0>; +L_0x127d660 .delay 1 (30000,30000,30000) L_0x127d660/d; +L_0x127d810/d .functor NOR 1, L_0x1285c30, L_0x1285d90, C4<0>, C4<0>; +L_0x127d810 .delay 1 (20000,20000,20000) L_0x127d810/d; +L_0x2ac432883258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328832a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127dae0/d .functor OR 1, L_0x2ac432883258, L_0x2ac4328832a0, C4<0>, C4<0>; +L_0x127dae0 .delay 1 (30000,30000,30000) L_0x127dae0/d; +L_0x127df30/d .functor OR 1, L_0x1285c30, L_0x1285d90, C4<0>, C4<0>; +L_0x127df30 .delay 1 (30000,30000,30000) L_0x127df30/d; +L_0x2ac4328832e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127e3d0/d .functor OR 1, L_0x2ac4328832e8, L_0x2ac432883330, C4<0>, C4<0>; +L_0x127e3d0 .delay 1 (30000,30000,30000) L_0x127e3d0/d; +L_0x1285b30/d .functor NOT 1, L_0x1281d90, C4<0>, C4<0>, C4<0>; +L_0x1285b30 .delay 1 (10000,10000,10000) L_0x1285b30/d; +v0xd1d0e0_0 .net "A", 0 0, L_0x1285c30; 1 drivers +v0xd1d180_0 .net "A_", 0 0, L_0x127b3f0; 1 drivers +v0xd1a3f0_0 .net "B", 0 0, L_0x1285d90; 1 drivers +v0xd1a490_0 .net "B_", 0 0, L_0x127b500; 1 drivers +v0xd29d30_0 .net *"_s11", 0 0, L_0x127c8a0; 1 drivers +v0xd299a0_0 .net/2s *"_s13", 0 0, L_0x2ac432883018; 1 drivers +v0xd29a40_0 .net/2s *"_s15", 0 0, L_0x2ac432883060; 1 drivers +v0xd26cf0_0 .net *"_s19", 0 0, L_0x127d040; 1 drivers +v0xce6430_0 .net/2s *"_s21", 0 0, L_0x2ac4328830a8; 1 drivers +v0xce4ec0_0 .net/2s *"_s23", 0 0, L_0x2ac4328830f0; 1 drivers +v0xce84b0_0 .net *"_s25", 0 0, L_0x127d240; 1 drivers +v0xcf8930_0 .net *"_s28", 0 0, L_0x127d300; 1 drivers +v0xcf84f0_0 .net/2s *"_s30", 0 0, L_0x2ac432883138; 1 drivers +v0xcf5800_0 .net/2s *"_s32", 0 0, L_0x2ac432883180; 1 drivers +v0xd05270_0 .net *"_s34", 0 0, L_0x127d550; 1 drivers +v0xd04ee0_0 .net *"_s37", 0 0, L_0x127d660; 1 drivers +v0xd02230_0 .net/2s *"_s39", 0 0, L_0x2ac4328831c8; 1 drivers +v0xd022d0_0 .net/2s *"_s41", 0 0, L_0x2ac432883210; 1 drivers +v0xcc1510_0 .net *"_s43", 0 0, L_0x127d810; 1 drivers +v0xcc0290_0 .net *"_s46", 0 0, L_0x127dae0; 1 drivers +v0xcc38a0_0 .net/2s *"_s48", 0 0, L_0x2ac432883258; 1 drivers +v0xcbff70_0 .net/2s *"_s50", 0 0, L_0x2ac4328832a0; 1 drivers +v0xcd3d40_0 .net *"_s52", 0 0, L_0x127df30; 1 drivers +v0xcd3900_0 .net *"_s56", 0 0, L_0x127e3d0; 1 drivers +v0xce0700_0 .net/2s *"_s59", 0 0, L_0x2ac4328832e8; 1 drivers +v0xce0370_0 .net/2s *"_s61", 0 0, L_0x2ac432883330; 1 drivers +v0xcdd4f0_0 .net *"_s8", 0 0, L_0x127c740; 1 drivers +v0xcac240_0 .net "carryin", 0 0, L_0x1285e80; 1 drivers +v0xcac2e0_0 .net "carryout", 0 0, L_0x12857d0; 1 drivers +v0xcbba80_0 .net "carryouts", 7 0, L_0x127e040; 1 drivers +v0xcbb640_0 .net "command", 7 0, v0x127a150_0; 1 drivers +v0xcbb700_0 .net "result", 0 0, L_0x1281d90; 1 drivers +v0xcb8950_0 .net "results", 7 0, L_0x127dcb0; 1 drivers +v0xcb89f0_0 .net "zero", 0 0, L_0x1285b30; 1 drivers +LS_0x127dcb0_0_0 .concat8 [ 1 1 1 1], L_0x127ba40, L_0x127c1d0, L_0x127c740, L_0x127d040; +LS_0x127dcb0_0_4 .concat8 [ 1 1 1 1], L_0x127d240, L_0x127d550, L_0x127d810, L_0x127df30; +L_0x127dcb0 .concat8 [ 4 4 0 0], LS_0x127dcb0_0_0, LS_0x127dcb0_0_4; +LS_0x127e040_0_0 .concat8 [ 1 1 1 1], L_0x127bd60, L_0x127c5e0, L_0x127c8a0, L_0x127ce90; +LS_0x127e040_0_4 .concat8 [ 1 1 1 1], L_0x127d300, L_0x127d660, L_0x127dae0, L_0x127e3d0; +L_0x127e040 .concat8 [ 4 4 0 0], LS_0x127e040_0_0, LS_0x127e040_0_4; +S_0xbbc1d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xd742a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x127bd60/d .functor OR 1, L_0x127b7f0, L_0x127bbd0, C4<0>, C4<0>; +L_0x127bd60 .delay 1 (30000,30000,30000) L_0x127bd60/d; +v0x1007650_0 .net "a", 0 0, L_0x1285c30; alias, 1 drivers +v0x1007710_0 .net "b", 0 0, L_0x1285d90; alias, 1 drivers +v0x10072c0_0 .net "c1", 0 0, L_0x127b7f0; 1 drivers +v0x1004490_0 .net "c2", 0 0, L_0x127bbd0; 1 drivers +v0xfc5dd0_0 .net "carryin", 0 0, L_0x1285e80; alias, 1 drivers +v0xfc5e70_0 .net "carryout", 0 0, L_0x127bd60; 1 drivers +v0xfd5d80_0 .net "s1", 0 0, L_0x127b6f0; 1 drivers +v0xfd32d0_0 .net "sum", 0 0, L_0x127ba40; 1 drivers +S_0x10232e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xbbc1d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x127b6f0/d .functor XOR 1, L_0x1285c30, L_0x1285d90, C4<0>, C4<0>; +L_0x127b6f0 .delay 1 (30000,30000,30000) L_0x127b6f0/d; +L_0x127b7f0/d .functor AND 1, L_0x1285c30, L_0x1285d90, C4<1>, C4<1>; +L_0x127b7f0 .delay 1 (30000,30000,30000) L_0x127b7f0/d; +v0xd988a0_0 .net "a", 0 0, L_0x1285c30; alias, 1 drivers +v0x100caf0_0 .net "b", 0 0, L_0x1285d90; alias, 1 drivers +v0x100cbb0_0 .net "carryout", 0 0, L_0x127b7f0; alias, 1 drivers +v0xfe8800_0 .net "sum", 0 0, L_0x127b6f0; alias, 1 drivers +S_0xfe84f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xbbc1d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x127ba40/d .functor XOR 1, L_0x127b6f0, L_0x1285e80, C4<0>, C4<0>; +L_0x127ba40 .delay 1 (30000,30000,30000) L_0x127ba40/d; +L_0x127bbd0/d .functor AND 1, L_0x127b6f0, L_0x1285e80, C4<1>, C4<1>; +L_0x127bbd0 .delay 1 (30000,30000,30000) L_0x127bbd0/d; +v0xfea880_0 .net "a", 0 0, L_0x127b6f0; alias, 1 drivers +v0xfea920_0 .net "b", 0 0, L_0x1285e80; alias, 1 drivers +v0xfface0_0 .net "carryout", 0 0, L_0x127bbd0; alias, 1 drivers +v0xffa8a0_0 .net "sum", 0 0, L_0x127ba40; alias, 1 drivers +S_0xfe6f50 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0xd742a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0xebd350_0 .net "ands", 7 0, L_0x12837d0; 1 drivers +v0xebcf10_0 .net "in", 7 0, L_0x127e040; alias, 1 drivers +v0xebcfd0_0 .net "out", 0 0, L_0x12857d0; alias, 1 drivers +v0xeba220_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0xf963b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xfe6f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0xf31360_0 .net "A", 7 0, L_0x127e040; alias, 1 drivers +v0xf2fdf0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0xf333e0_0 .net *"_s0", 0 0, L_0x12820f0; 1 drivers +v0xf334a0_0 .net *"_s12", 0 0, L_0x1282a60; 1 drivers +v0xf438d0_0 .net *"_s16", 0 0, L_0x1282dc0; 1 drivers +v0xf43490_0 .net *"_s20", 0 0, L_0x1283190; 1 drivers +v0xf407a0_0 .net *"_s24", 0 0, L_0x12834c0; 1 drivers +v0xf500c0_0 .net *"_s28", 0 0, L_0x1283450; 1 drivers +v0xf4fd30_0 .net *"_s4", 0 0, L_0x1282440; 1 drivers +v0xf4d080_0 .net *"_s8", 0 0, L_0x1282750; 1 drivers +v0xf0c7e0_0 .net "out", 7 0, L_0x12837d0; alias, 1 drivers +L_0x12821b0 .part L_0x127e040, 0, 1; +L_0x12823a0 .part v0x127a150_0, 0, 1; +L_0x1282500 .part L_0x127e040, 1, 1; +L_0x1282660 .part v0x127a150_0, 1, 1; +L_0x1282810 .part L_0x127e040, 2, 1; +L_0x1282970 .part v0x127a150_0, 2, 1; +L_0x1282b20 .part L_0x127e040, 3, 1; +L_0x1282c80 .part v0x127a150_0, 3, 1; +L_0x1282e80 .part L_0x127e040, 4, 1; +L_0x12830f0 .part v0x127a150_0, 4, 1; +L_0x1283200 .part L_0x127e040, 5, 1; +L_0x1283360 .part v0x127a150_0, 5, 1; +L_0x1283580 .part L_0x127e040, 6, 1; +L_0x12836e0 .part v0x127a150_0, 6, 1; +LS_0x12837d0_0_0 .concat8 [ 1 1 1 1], L_0x12820f0, L_0x1282440, L_0x1282750, L_0x1282a60; +LS_0x12837d0_0_4 .concat8 [ 1 1 1 1], L_0x1282dc0, L_0x1283190, L_0x12834c0, L_0x1283450; +L_0x12837d0 .concat8 [ 4 4 0 0], LS_0x12837d0_0_0, LS_0x12837d0_0_4; +L_0x1283b90 .part L_0x127e040, 7, 1; +L_0x1283d80 .part v0x127a150_0, 7, 1; +S_0xf54540 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xfe2a70 .param/l "i" 0 4 54, +C4<00>; +L_0x12820f0/d .functor AND 1, L_0x12821b0, L_0x12823a0, C4<1>, C4<1>; +L_0x12820f0 .delay 1 (30000,30000,30000) L_0x12820f0/d; +v0xfe2630_0 .net *"_s0", 0 0, L_0x12821b0; 1 drivers +v0xfb1850_0 .net *"_s1", 0 0, L_0x12823a0; 1 drivers +S_0xf31050 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xfe2b50 .param/l "i" 0 4 54, +C4<01>; +L_0x1282440/d .functor AND 1, L_0x1282500, L_0x1282660, C4<1>, C4<1>; +L_0x1282440 .delay 1 (30000,30000,30000) L_0x1282440/d; +v0xfb14c0_0 .net *"_s0", 0 0, L_0x1282500; 1 drivers +v0xfae810_0 .net *"_s1", 0 0, L_0x1282660; 1 drivers +S_0xf2fab0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xfb15a0 .param/l "i" 0 4 54, +C4<010>; +L_0x1282750/d .functor AND 1, L_0x1282810, L_0x1282970, C4<1>, C4<1>; +L_0x1282750 .delay 1 (30000,30000,30000) L_0x1282750/d; +v0xfbdfb0_0 .net *"_s0", 0 0, L_0x1282810; 1 drivers +v0xfbdb20_0 .net *"_s1", 0 0, L_0x1282970; 1 drivers +S_0xf0c4d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xfbae30 .param/l "i" 0 4 54, +C4<011>; +L_0x1282a60/d .functor AND 1, L_0x1282b20, L_0x1282c80, C4<1>, C4<1>; +L_0x1282a60 .delay 1 (30000,30000,30000) L_0x1282a60/d; +v0xfbaef0_0 .net *"_s0", 0 0, L_0x1282b20; 1 drivers +v0xf8ce80_0 .net *"_s1", 0 0, L_0x1282c80; 1 drivers +S_0xf0af30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xf8cb40 .param/l "i" 0 4 54, +C4<0100>; +L_0x1282dc0/d .functor AND 1, L_0x1282e80, L_0x12830f0, C4<1>, C4<1>; +L_0x1282dc0 .delay 1 (30000,30000,30000) L_0x1282dc0/d; +v0xf89e40_0 .net *"_s0", 0 0, L_0x1282e80; 1 drivers +v0xf990b0_0 .net *"_s1", 0 0, L_0x12830f0; 1 drivers +S_0xee78e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xf8cc00 .param/l "i" 0 4 54, +C4<0101>; +L_0x1283190/d .functor AND 1, L_0x1283200, L_0x1283360, C4<1>, C4<1>; +L_0x1283190 .delay 1 (30000,30000,30000) L_0x1283190/d; +v0xf54880_0 .net *"_s0", 0 0, L_0x1283200; 1 drivers +v0xf68470_0 .net *"_s1", 0 0, L_0x1283360; 1 drivers +S_0xee6340 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xf54980 .param/l "i" 0 4 54, +C4<0110>; +L_0x12834c0/d .functor AND 1, L_0x1283580, L_0x12836e0, C4<1>, C4<1>; +L_0x12834c0 .delay 1 (30000,30000,30000) L_0x12834c0/d; +v0xf68150_0 .net *"_s0", 0 0, L_0x1283580; 1 drivers +v0xf65430_0 .net *"_s1", 0 0, L_0x12836e0; 1 drivers +S_0xed5160 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xf963b0; + .timescale -9 -12; +P_0xf74b40 .param/l "i" 0 4 54, +C4<0111>; +L_0x1283450/d .functor AND 1, L_0x1283b90, L_0x1283d80, C4<1>, C4<1>; +L_0x1283450 .delay 1 (30000,30000,30000) L_0x1283450/d; +v0xf74790_0 .net *"_s0", 0 0, L_0x1283b90; 1 drivers +v0xf71ae0_0 .net *"_s1", 0 0, L_0x1283d80; 1 drivers +S_0xe30440 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xfe6f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12857d0/d .functor OR 1, L_0x1285890, L_0x1285a40, C4<0>, C4<0>; +L_0x12857d0 .delay 1 (30000,30000,30000) L_0x12857d0/d; +v0xee1a30_0 .net *"_s10", 0 0, L_0x1285890; 1 drivers +v0xeb0bc0_0 .net *"_s12", 0 0, L_0x1285a40; 1 drivers +v0xeb0830_0 .net "in", 7 0, L_0x12837d0; alias, 1 drivers +v0xeb08d0_0 .net "ors", 1 0, L_0x12855f0; 1 drivers +v0xeadb80_0 .net "out", 0 0, L_0x12857d0; alias, 1 drivers +L_0x12849c0 .part L_0x12837d0, 0, 4; +L_0x12855f0 .concat8 [ 1 1 0 0], L_0x12846b0, L_0x12852e0; +L_0x1285730 .part L_0x12837d0, 4, 4; +L_0x1285890 .part L_0x12855f0, 0, 1; +L_0x1285a40 .part L_0x12855f0, 1, 1; +S_0xe2eea0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xe30440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1283e70/d .functor OR 1, L_0x1283f30, L_0x1284090, C4<0>, C4<0>; +L_0x1283e70 .delay 1 (30000,30000,30000) L_0x1283e70/d; +L_0x12842c0/d .functor OR 1, L_0x12843d0, L_0x1284530, C4<0>, C4<0>; +L_0x12842c0 .delay 1 (30000,30000,30000) L_0x12842c0/d; +L_0x12846b0/d .functor OR 1, L_0x1284720, L_0x12848d0, C4<0>, C4<0>; +L_0x12846b0 .delay 1 (30000,30000,30000) L_0x12846b0/d; +v0xf0b270_0 .net *"_s0", 0 0, L_0x1283e70; 1 drivers +v0xf0e860_0 .net *"_s10", 0 0, L_0x12843d0; 1 drivers +v0xf1ed00_0 .net *"_s12", 0 0, L_0x1284530; 1 drivers +v0xf1edc0_0 .net *"_s14", 0 0, L_0x1284720; 1 drivers +v0xf1e8c0_0 .net *"_s16", 0 0, L_0x12848d0; 1 drivers +v0xf1bbd0_0 .net *"_s3", 0 0, L_0x1283f30; 1 drivers +v0xf2b630_0 .net *"_s5", 0 0, L_0x1284090; 1 drivers +v0xf2b2a0_0 .net *"_s6", 0 0, L_0x12842c0; 1 drivers +v0xf285f0_0 .net "in", 3 0, L_0x12849c0; 1 drivers +v0xee7bf0_0 .net "ors", 1 0, L_0x12841d0; 1 drivers +v0xee6680_0 .net "out", 0 0, L_0x12846b0; 1 drivers +L_0x1283f30 .part L_0x12849c0, 0, 1; +L_0x1284090 .part L_0x12849c0, 1, 1; +L_0x12841d0 .concat8 [ 1 1 0 0], L_0x1283e70, L_0x12842c0; +L_0x12843d0 .part L_0x12849c0, 2, 1; +L_0x1284530 .part L_0x12849c0, 3, 1; +L_0x1284720 .part L_0x12841d0, 0, 1; +L_0x12848d0 .part L_0x12841d0, 1, 1; +S_0xe0b810 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xe30440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1284af0/d .functor OR 1, L_0x1284b60, L_0x1284cc0, C4<0>, C4<0>; +L_0x1284af0 .delay 1 (30000,30000,30000) L_0x1284af0/d; +L_0x1284ef0/d .functor OR 1, L_0x1285000, L_0x1285160, C4<0>, C4<0>; +L_0x1284ef0 .delay 1 (30000,30000,30000) L_0x1284ef0/d; +L_0x12852e0/d .functor OR 1, L_0x1285350, L_0x1285500, C4<0>, C4<0>; +L_0x12852e0 .delay 1 (30000,30000,30000) L_0x12852e0/d; +v0xee9c70_0 .net *"_s0", 0 0, L_0x1284af0; 1 drivers +v0xefa0f0_0 .net *"_s10", 0 0, L_0x1285000; 1 drivers +v0xef9cb0_0 .net *"_s12", 0 0, L_0x1285160; 1 drivers +v0xef9d70_0 .net *"_s14", 0 0, L_0x1285350; 1 drivers +v0xef6fc0_0 .net *"_s16", 0 0, L_0x1285500; 1 drivers +v0xf06ab0_0 .net *"_s3", 0 0, L_0x1284b60; 1 drivers +v0xf06720_0 .net *"_s5", 0 0, L_0x1284cc0; 1 drivers +v0xf038a0_0 .net *"_s6", 0 0, L_0x1284ef0; 1 drivers +v0xec51c0_0 .net "in", 3 0, L_0x1285730; 1 drivers +v0xed26c0_0 .net "ors", 1 0, L_0x1284e00; 1 drivers +v0xee1e70_0 .net "out", 0 0, L_0x12852e0; 1 drivers +L_0x1284b60 .part L_0x1285730, 0, 1; +L_0x1284cc0 .part L_0x1285730, 1, 1; +L_0x1284e00 .concat8 [ 1 1 0 0], L_0x1284af0, L_0x1284ef0; +L_0x1285000 .part L_0x1285730, 2, 1; +L_0x1285160 .part L_0x1285730, 3, 1; +L_0x1285350 .part L_0x1284e00, 0, 1; +L_0x1285500 .part L_0x1284e00, 1, 1; +S_0xe0a270 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0xd742a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0xd88450_0 .net "ands", 7 0, L_0x127fd90; 1 drivers +v0xd97bc0_0 .net "in", 7 0, L_0x127dcb0; alias, 1 drivers +v0xd97c80_0 .net "out", 0 0, L_0x1281d90; alias, 1 drivers +v0xd97780_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0xde6cf0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xe0a270; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0xe4f460_0 .net "A", 7 0, L_0x127dcb0; alias, 1 drivers +v0xe4f0d0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0xe4c420_0 .net *"_s0", 0 0, L_0x127e580; 1 drivers +v0xe4c4e0_0 .net *"_s12", 0 0, L_0x127ef40; 1 drivers +v0xe0bb20_0 .net *"_s16", 0 0, L_0x127f2a0; 1 drivers +v0xe0a5b0_0 .net *"_s20", 0 0, L_0x127f6d0; 1 drivers +v0xe0dba0_0 .net *"_s24", 0 0, L_0x127fa00; 1 drivers +v0xe1e190_0 .net *"_s28", 0 0, L_0x127f990; 1 drivers +v0xe1dd50_0 .net *"_s4", 0 0, L_0x127e920; 1 drivers +v0xe1b060_0 .net *"_s8", 0 0, L_0x127ec30; 1 drivers +v0xe2aa20_0 .net "out", 7 0, L_0x127fd90; alias, 1 drivers +L_0x127e690 .part L_0x127dcb0, 0, 1; +L_0x127e880 .part v0x127a150_0, 0, 1; +L_0x127e9e0 .part L_0x127dcb0, 1, 1; +L_0x127eb40 .part v0x127a150_0, 1, 1; +L_0x127ecf0 .part L_0x127dcb0, 2, 1; +L_0x127ee50 .part v0x127a150_0, 2, 1; +L_0x127f000 .part L_0x127dcb0, 3, 1; +L_0x127f160 .part v0x127a150_0, 3, 1; +L_0x127f360 .part L_0x127dcb0, 4, 1; +L_0x127f5d0 .part v0x127a150_0, 4, 1; +L_0x127f740 .part L_0x127dcb0, 5, 1; +L_0x127f8a0 .part v0x127a150_0, 5, 1; +L_0x127fac0 .part L_0x127dcb0, 6, 1; +L_0x127fc20 .part v0x127a150_0, 6, 1; +LS_0x127fd90_0_0 .concat8 [ 1 1 1 1], L_0x127e580, L_0x127e920, L_0x127ec30, L_0x127ef40; +LS_0x127fd90_0_4 .concat8 [ 1 1 1 1], L_0x127f2a0, L_0x127f6d0, L_0x127fa00, L_0x127f990; +L_0x127fd90 .concat8 [ 4 4 0 0], LS_0x127fd90_0_0, LS_0x127fd90_0_4; +L_0x1280150 .part L_0x127dcb0, 7, 1; +L_0x1280340 .part v0x127a150_0, 7, 1; +S_0xde5750 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xf501a0 .param/l "i" 0 4 54, +C4<00>; +L_0x127e580/d .functor AND 1, L_0x127e690, L_0x127e880, C4<1>, C4<1>; +L_0x127e580 .delay 1 (30000,30000,30000) L_0x127e580/d; +v0xe8c1d0_0 .net *"_s0", 0 0, L_0x127e690; 1 drivers +v0xe8be40_0 .net *"_s1", 0 0, L_0x127e880; 1 drivers +S_0xd70010 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xe8bf40 .param/l "i" 0 4 54, +C4<01>; +L_0x127e920/d .functor AND 1, L_0x127e9e0, L_0x127eb40, C4<1>, C4<1>; +L_0x127e920 .delay 1 (30000,30000,30000) L_0x127e920/d; +v0xe89190_0 .net *"_s0", 0 0, L_0x127e9e0; 1 drivers +v0xe98890_0 .net *"_s1", 0 0, L_0x127eb40; 1 drivers +S_0xd2e4d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xf1bcb0 .param/l "i" 0 4 54, +C4<010>; +L_0x127ec30/d .functor AND 1, L_0x127ecf0, L_0x127ee50, C4<1>, C4<1>; +L_0x127ec30 .delay 1 (30000,30000,30000) L_0x127ec30/d; +v0xe98450_0 .net *"_s0", 0 0, L_0x127ecf0; 1 drivers +v0xe98510_0 .net *"_s1", 0 0, L_0x127ee50; 1 drivers +S_0xd2e1b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xee7cd0 .param/l "i" 0 4 54, +C4<011>; +L_0x127ef40/d .functor AND 1, L_0x127f000, L_0x127f160, C4<1>, C4<1>; +L_0x127ef40 .delay 1 (30000,30000,30000) L_0x127ef40/d; +v0xe95760_0 .net *"_s0", 0 0, L_0x127f000; 1 drivers +v0xe678f0_0 .net *"_s1", 0 0, L_0x127f160; 1 drivers +S_0xd0ac90 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xf06800 .param/l "i" 0 4 54, +C4<0100>; +L_0x127f2a0/d .functor AND 1, L_0x127f360, L_0x127f5d0, C4<1>, C4<1>; +L_0x127f2a0 .delay 1 (30000,30000,30000) L_0x127f2a0/d; +v0xe67560_0 .net *"_s0", 0 0, L_0x127f360; 1 drivers +v0xe648b0_0 .net *"_s1", 0 0, L_0x127f5d0; 1 drivers +S_0xd096f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xed27a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x127f6d0/d .functor AND 1, L_0x127f740, L_0x127f8a0, C4<1>, C4<1>; +L_0x127f6d0 .delay 1 (30000,30000,30000) L_0x127f6d0/d; +v0xe70f50_0 .net *"_s0", 0 0, L_0x127f740; 1 drivers +v0xe30750_0 .net *"_s1", 0 0, L_0x127f8a0; 1 drivers +S_0xce6120 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xeb0ca0 .param/l "i" 0 4 54, +C4<0110>; +L_0x127fa00/d .functor AND 1, L_0x127fac0, L_0x127fc20, C4<1>, C4<1>; +L_0x127fa00 .delay 1 (30000,30000,30000) L_0x127fa00/d; +v0xe2f1e0_0 .net *"_s0", 0 0, L_0x127fac0; 1 drivers +v0xe42ce0_0 .net *"_s1", 0 0, L_0x127fc20; 1 drivers +S_0xce4b80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xde6cf0; + .timescale -9 -12; +P_0xe95840 .param/l "i" 0 4 54, +C4<0111>; +L_0x127f990/d .functor AND 1, L_0x1280150, L_0x1280340, C4<1>, C4<1>; +L_0x127f990 .delay 1 (30000,30000,30000) L_0x127f990/d; +v0xe428a0_0 .net *"_s0", 0 0, L_0x1280150; 1 drivers +v0xe3fbb0_0 .net *"_s1", 0 0, L_0x1280340; 1 drivers +S_0xcaf130 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xe0a270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1281d90/d .functor OR 1, L_0x1281e50, L_0x1282000, C4<0>, C4<0>; +L_0x1281d90 .delay 1 (30000,30000,30000) L_0x1281d90/d; +v0xdbc2a0_0 .net *"_s10", 0 0, L_0x1281e50; 1 drivers +v0xdb95b0_0 .net *"_s12", 0 0, L_0x1282000; 1 drivers +v0xd8b490_0 .net "in", 7 0, L_0x127fd90; alias, 1 drivers +v0xd8b530_0 .net "ors", 1 0, L_0x1281bb0; 1 drivers +v0xd8b100_0 .net "out", 0 0, L_0x1281d90; alias, 1 drivers +L_0x1280f80 .part L_0x127fd90, 0, 4; +L_0x1281bb0 .concat8 [ 1 1 0 0], L_0x1280c70, L_0x12818a0; +L_0x1281cf0 .part L_0x127fd90, 4, 4; +L_0x1281e50 .part L_0x1281bb0, 0, 1; +L_0x1282000 .part L_0x1281bb0, 1, 1; +S_0xc2ead0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xcaf130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1280430/d .functor OR 1, L_0x12804f0, L_0x1280650, C4<0>, C4<0>; +L_0x1280430 .delay 1 (30000,30000,30000) L_0x1280430/d; +L_0x1280880/d .functor OR 1, L_0x1280990, L_0x1280af0, C4<0>, C4<0>; +L_0x1280880 .delay 1 (30000,30000,30000) L_0x1280880/d; +L_0x1280c70/d .functor OR 1, L_0x1280ce0, L_0x1280e90, C4<0>, C4<0>; +L_0x1280c70 .delay 1 (30000,30000,30000) L_0x1280c70/d; +v0xe2a690_0 .net *"_s0", 0 0, L_0x1280430; 1 drivers +v0xe279e0_0 .net *"_s10", 0 0, L_0x1280990; 1 drivers +v0xde7000_0 .net *"_s12", 0 0, L_0x1280af0; 1 drivers +v0xde70c0_0 .net *"_s14", 0 0, L_0x1280ce0; 1 drivers +v0xde5a90_0 .net *"_s16", 0 0, L_0x1280e90; 1 drivers +v0xde9080_0 .net *"_s3", 0 0, L_0x12804f0; 1 drivers +v0xdf94b0_0 .net *"_s5", 0 0, L_0x1280650; 1 drivers +v0xdf9070_0 .net *"_s6", 0 0, L_0x1280880; 1 drivers +v0xdf6380_0 .net "in", 3 0, L_0x1280f80; 1 drivers +v0xe05df0_0 .net "ors", 1 0, L_0x1280790; 1 drivers +v0xe05a60_0 .net "out", 0 0, L_0x1280c70; 1 drivers +L_0x12804f0 .part L_0x1280f80, 0, 1; +L_0x1280650 .part L_0x1280f80, 1, 1; +L_0x1280790 .concat8 [ 1 1 0 0], L_0x1280430, L_0x1280880; +L_0x1280990 .part L_0x1280f80, 2, 1; +L_0x1280af0 .part L_0x1280f80, 3, 1; +L_0x1280ce0 .part L_0x1280790, 0, 1; +L_0x1280e90 .part L_0x1280790, 1, 1; +S_0xc2d530 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xcaf130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12810b0/d .functor OR 1, L_0x1281120, L_0x1281280, C4<0>, C4<0>; +L_0x12810b0 .delay 1 (30000,30000,30000) L_0x12810b0/d; +L_0x12814b0/d .functor OR 1, L_0x12815c0, L_0x1281720, C4<0>, C4<0>; +L_0x12814b0 .delay 1 (30000,30000,30000) L_0x12814b0/d; +L_0x12818a0/d .functor OR 1, L_0x1281910, L_0x1281ac0, C4<0>, C4<0>; +L_0x12818a0 .delay 1 (30000,30000,30000) L_0x12818a0/d; +v0xe02db0_0 .net *"_s0", 0 0, L_0x12810b0; 1 drivers +v0xdc4510_0 .net *"_s10", 0 0, L_0x12815c0; 1 drivers +v0xdd4500_0 .net *"_s12", 0 0, L_0x1281720; 1 drivers +v0xdd45c0_0 .net *"_s14", 0 0, L_0x1281910; 1 drivers +v0xdd1970_0 .net *"_s16", 0 0, L_0x1281ac0; 1 drivers +v0xde11f0_0 .net *"_s3", 0 0, L_0x1281120; 1 drivers +v0xde0db0_0 .net *"_s5", 0 0, L_0x1281280; 1 drivers +v0xdaff10_0 .net *"_s6", 0 0, L_0x12814b0; 1 drivers +v0xdafb80_0 .net "in", 3 0, L_0x1281cf0; 1 drivers +v0xdaced0_0 .net "ors", 1 0, L_0x12813c0; 1 drivers +v0xdbc6e0_0 .net "out", 0 0, L_0x12818a0; 1 drivers +L_0x1281120 .part L_0x1281cf0, 0, 1; +L_0x1281280 .part L_0x1281cf0, 1, 1; +L_0x12813c0 .concat8 [ 1 1 0 0], L_0x12810b0, L_0x12814b0; +L_0x12815c0 .part L_0x1281cf0, 2, 1; +L_0x1281720 .part L_0x1281cf0, 3, 1; +L_0x1281910 .part L_0x12813c0, 0, 1; +L_0x1281ac0 .part L_0x12813c0, 1, 1; +S_0xc09f30 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0xd742a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x127caa0/d .functor XNOR 1, L_0x1285c30, L_0x1285d90, C4<0>, C4<0>; +L_0x127caa0 .delay 1 (20000,20000,20000) L_0x127caa0/d; +L_0x127cc20/d .functor AND 1, L_0x1285c30, L_0x127b500, C4<1>, C4<1>; +L_0x127cc20 .delay 1 (30000,30000,30000) L_0x127cc20/d; +L_0x127cd80/d .functor AND 1, L_0x127caa0, L_0x1285e80, C4<1>, C4<1>; +L_0x127cd80 .delay 1 (30000,30000,30000) L_0x127cd80/d; +L_0x127ce90/d .functor OR 1, L_0x127cd80, L_0x127cc20, C4<0>, C4<0>; +L_0x127ce90 .delay 1 (30000,30000,30000) L_0x127ce90/d; +v0xd94b30_0 .net "a", 0 0, L_0x1285c30; alias, 1 drivers +v0xd66b00_0 .net "a_", 0 0, L_0x127b3f0; alias, 1 drivers +v0xd66ba0_0 .net "b", 0 0, L_0x1285d90; alias, 1 drivers +v0xd66770_0 .net "b_", 0 0, L_0x127b500; alias, 1 drivers +v0xd66810_0 .net "carryin", 0 0, L_0x1285e80; alias, 1 drivers +v0xd63ac0_0 .net "eq", 0 0, L_0x127caa0; 1 drivers +v0xd63b60_0 .net "lt", 0 0, L_0x127cc20; 1 drivers +v0xd72d10_0 .net "out", 0 0, L_0x127ce90; 1 drivers +v0xd72db0_0 .net "w0", 0 0, L_0x127cd80; 1 drivers +S_0xc08990 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xd742a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x127c5e0/d .functor OR 1, L_0x127c020, L_0x127c4d0, C4<0>, C4<0>; +L_0x127c5e0 .delay 1 (30000,30000,30000) L_0x127c5e0/d; +v0xd4b740_0 .net "a", 0 0, L_0x1285c30; alias, 1 drivers +v0xd0afa0_0 .net "b", 0 0, L_0x127b500; alias, 1 drivers +v0xd0b060_0 .net "c1", 0 0, L_0x127c020; 1 drivers +v0xd09a30_0 .net "c2", 0 0, L_0x127c4d0; 1 drivers +v0xd09ad0_0 .net "carryin", 0 0, L_0x1285e80; alias, 1 drivers +v0xd0d0b0_0 .net "carryout", 0 0, L_0x127c5e0; 1 drivers +v0xd1d520_0 .net "s1", 0 0, L_0x127bec0; 1 drivers +v0xd1d5c0_0 .net "sum", 0 0, L_0x127c1d0; 1 drivers +S_0xbe53c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xc08990; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x127bec0/d .functor XOR 1, L_0x1285c30, L_0x127b500, C4<0>, C4<0>; +L_0x127bec0 .delay 1 (30000,30000,30000) L_0x127bec0/d; +L_0x127c020/d .functor AND 1, L_0x1285c30, L_0x127b500, C4<1>, C4<1>; +L_0x127c020 .delay 1 (30000,30000,30000) L_0x127c020/d; +v0xd41d40_0 .net "a", 0 0, L_0x1285c30; alias, 1 drivers +v0xd41e00_0 .net "b", 0 0, L_0x127b500; alias, 1 drivers +v0xd3ef20_0 .net "carryout", 0 0, L_0x127c020; alias, 1 drivers +v0xd3efc0_0 .net "sum", 0 0, L_0x127bec0; alias, 1 drivers +S_0xbe3e20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xc08990; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x127c1d0/d .functor XOR 1, L_0x127bec0, L_0x1285e80, C4<0>, C4<0>; +L_0x127c1d0 .delay 1 (30000,30000,30000) L_0x127c1d0/d; +L_0x127c4d0/d .functor AND 1, L_0x127bec0, L_0x1285e80, C4<1>, C4<1>; +L_0x127c4d0 .delay 1 (30000,30000,30000) L_0x127c4d0/d; +v0xd4e780_0 .net "a", 0 0, L_0x127bec0; alias, 1 drivers +v0xd4e840_0 .net "b", 0 0, L_0x1285e80; alias, 1 drivers +v0xd4e3f0_0 .net "carryout", 0 0, L_0x127c4d0; alias, 1 drivers +v0xd4e490_0 .net "sum", 0 0, L_0x127c1d0; alias, 1 drivers +S_0xb98bc0 .scope generate, "alu_slices[1]" "alu_slices[1]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0xde0e90 .param/l "i" 0 3 39, +C4<01>; +S_0xcd1120 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0xb98bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x127b9d0/d .functor NOT 1, L_0x1290400, C4<0>, C4<0>, C4<0>; +L_0x127b9d0 .delay 1 (10000,10000,10000) L_0x127b9d0/d; +L_0x1285fc0/d .functor NOT 1, L_0x1290560, C4<0>, C4<0>, C4<0>; +L_0x1285fc0 .delay 1 (10000,10000,10000) L_0x1285fc0/d; +L_0x1286f40/d .functor XOR 1, L_0x1290400, L_0x1290560, C4<0>, C4<0>; +L_0x1286f40 .delay 1 (30000,30000,30000) L_0x1286f40/d; +L_0x2ac432883378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328833c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1287000/d .functor OR 1, L_0x2ac432883378, L_0x2ac4328833c0, C4<0>, C4<0>; +L_0x1287000 .delay 1 (30000,30000,30000) L_0x1287000/d; +L_0x2ac432883408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12877a0/d .functor OR 1, L_0x2ac432883408, L_0x2ac432883450, C4<0>, C4<0>; +L_0x12877a0 .delay 1 (30000,30000,30000) L_0x12877a0/d; +L_0x12879a0/d .functor AND 1, L_0x1290400, L_0x1290560, C4<1>, C4<1>; +L_0x12879a0 .delay 1 (30000,30000,30000) L_0x12879a0/d; +L_0x2ac432883498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328834e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1287a60/d .functor OR 1, L_0x2ac432883498, L_0x2ac4328834e0, C4<0>, C4<0>; +L_0x1287a60 .delay 1 (30000,30000,30000) L_0x1287a60/d; +L_0x1287d20/d .functor NAND 1, L_0x1290400, L_0x1290560, C4<1>, C4<1>; +L_0x1287d20 .delay 1 (20000,20000,20000) L_0x1287d20/d; +L_0x2ac432883528 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883570 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1287e30/d .functor OR 1, L_0x2ac432883528, L_0x2ac432883570, C4<0>, C4<0>; +L_0x1287e30 .delay 1 (30000,30000,30000) L_0x1287e30/d; +L_0x1287fe0/d .functor NOR 1, L_0x1290400, L_0x1290560, C4<0>, C4<0>; +L_0x1287fe0 .delay 1 (20000,20000,20000) L_0x1287fe0/d; +L_0x2ac4328835b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12882b0/d .functor OR 1, L_0x2ac4328835b8, L_0x2ac432883600, C4<0>, C4<0>; +L_0x12882b0 .delay 1 (30000,30000,30000) L_0x12882b0/d; +L_0x12886b0/d .functor OR 1, L_0x1290400, L_0x1290560, C4<0>, C4<0>; +L_0x12886b0 .delay 1 (30000,30000,30000) L_0x12886b0/d; +L_0x2ac432883648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1288b50/d .functor OR 1, L_0x2ac432883648, L_0x2ac432883690, C4<0>, C4<0>; +L_0x1288b50 .delay 1 (30000,30000,30000) L_0x1288b50/d; +L_0x12902b0/d .functor NOT 1, L_0x128c510, C4<0>, C4<0>, C4<0>; +L_0x12902b0 .delay 1 (10000,10000,10000) L_0x12902b0/d; +v0xe400d0_0 .net "A", 0 0, L_0x1290400; 1 drivers +v0xe40190_0 .net "A_", 0 0, L_0x127b9d0; 1 drivers +v0xe2cb00_0 .net "B", 0 0, L_0x1290560; 1 drivers +v0xe2cba0_0 .net "B_", 0 0, L_0x1285fc0; 1 drivers +v0xe2c780_0 .net *"_s11", 0 0, L_0x1287000; 1 drivers +v0xe2c870_0 .net/2s *"_s13", 0 0, L_0x2ac432883378; 1 drivers +v0xe1b580_0 .net/2s *"_s15", 0 0, L_0x2ac4328833c0; 1 drivers +v0xe1b660_0 .net *"_s19", 0 0, L_0x12877a0; 1 drivers +v0xe07ed0_0 .net/2s *"_s21", 0 0, L_0x2ac432883408; 1 drivers +v0xe07b50_0 .net/2s *"_s23", 0 0, L_0x2ac432883450; 1 drivers +v0xe07c30_0 .net *"_s25", 0 0, L_0x12879a0; 1 drivers +v0xdf68a0_0 .net *"_s28", 0 0, L_0x1287a60; 1 drivers +v0xdf6980_0 .net/2s *"_s30", 0 0, L_0x2ac432883498; 1 drivers +v0xde33b0_0 .net/2s *"_s32", 0 0, L_0x2ac4328834e0; 1 drivers +v0xde3490_0 .net *"_s34", 0 0, L_0x1287d20; 1 drivers +v0xde3030_0 .net *"_s37", 0 0, L_0x1287e30; 1 drivers +v0xde3110_0 .net/2s *"_s39", 0 0, L_0x2ac432883528; 1 drivers +v0xdd48d0_0 .net/2s *"_s41", 0 0, L_0x2ac432883570; 1 drivers +v0xdd4990_0 .net *"_s43", 0 0, L_0x1287fe0; 1 drivers +v0xdde5e0_0 .net *"_s46", 0 0, L_0x12882b0; 1 drivers +v0xdde6c0_0 .net/2s *"_s48", 0 0, L_0x2ac4328835b8; 1 drivers +v0xd9d7e0_0 .net/2s *"_s50", 0 0, L_0x2ac432883600; 1 drivers +v0xd9d8c0_0 .net *"_s52", 0 0, L_0x12886b0; 1 drivers +v0xdb9ad0_0 .net *"_s56", 0 0, L_0x1288b50; 1 drivers +v0xdb9b90_0 .net/2s *"_s59", 0 0, L_0x2ac432883648; 1 drivers +v0xd78d90_0 .net/2s *"_s61", 0 0, L_0x2ac432883690; 1 drivers +v0xd78e70_0 .net *"_s8", 0 0, L_0x1286f40; 1 drivers +v0xd94fb0_0 .net "carryin", 0 0, L_0x1290600; 1 drivers +v0xd95050_0 .net "carryout", 0 0, L_0x128ff50; 1 drivers +v0xd542a0_0 .net "carryouts", 7 0, L_0x12887c0; 1 drivers +v0xd730d0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0xd73190_0 .net "result", 0 0, L_0x128c510; 1 drivers +v0xd70540_0 .net "results", 7 0, L_0x1288480; 1 drivers +v0xd705e0_0 .net "zero", 0 0, L_0x12902b0; 1 drivers +LS_0x1288480_0_0 .concat8 [ 1 1 1 1], L_0x1286430, L_0x1286a40, L_0x1286f40, L_0x12877a0; +LS_0x1288480_0_4 .concat8 [ 1 1 1 1], L_0x12879a0, L_0x1287d20, L_0x1287fe0, L_0x12886b0; +L_0x1288480 .concat8 [ 4 4 0 0], LS_0x1288480_0_0, LS_0x1288480_0_4; +LS_0x12887c0_0_0 .concat8 [ 1 1 1 1], L_0x1286730, L_0x1286de0, L_0x1287000, L_0x12875f0; +LS_0x12887c0_0_4 .concat8 [ 1 1 1 1], L_0x1287a60, L_0x1287e30, L_0x12882b0, L_0x1288b50; +L_0x12887c0 .concat8 [ 4 4 0 0], LS_0x12887c0_0_0, LS_0x12887c0_0_4; +S_0xc3e7d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xcd1120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1286730/d .functor OR 1, L_0x12861c0, L_0x12865d0, C4<0>, C4<0>; +L_0x1286730 .delay 1 (30000,30000,30000) L_0x1286730/d; +v0xc93e00_0 .net "a", 0 0, L_0x1290400; alias, 1 drivers +v0xc93ec0_0 .net "b", 0 0, L_0x1290560; alias, 1 drivers +v0xc65e90_0 .net "c1", 0 0, L_0x12861c0; 1 drivers +v0xc65b00_0 .net "c2", 0 0, L_0x12865d0; 1 drivers +v0xc62e50_0 .net "carryin", 0 0, L_0x1290600; alias, 1 drivers +v0xc720a0_0 .net "carryout", 0 0, L_0x1286730; 1 drivers +v0xc72140_0 .net "s1", 0 0, L_0x1286150; 1 drivers +v0xc2d870_0 .net "sum", 0 0, L_0x1286430; 1 drivers +S_0xc19c60 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xc3e7d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1286150/d .functor XOR 1, L_0x1290400, L_0x1290560, C4<0>, C4<0>; +L_0x1286150 .delay 1 (30000,30000,30000) L_0x1286150/d; +L_0x12861c0/d .functor AND 1, L_0x1290400, L_0x1290560, C4<1>, C4<1>; +L_0x12861c0 .delay 1 (30000,30000,30000) L_0x12861c0/d; +v0xc8a7f0_0 .net "a", 0 0, L_0x1290400; alias, 1 drivers +v0xc8a460_0 .net "b", 0 0, L_0x1290560; alias, 1 drivers +v0xc8a520_0 .net "carryout", 0 0, L_0x12861c0; alias, 1 drivers +v0xc877b0_0 .net "sum", 0 0, L_0x1286150; alias, 1 drivers +S_0xbbf4f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xc3e7d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1286430/d .functor XOR 1, L_0x1286150, L_0x1290600, C4<0>, C4<0>; +L_0x1286430 .delay 1 (30000,30000,30000) L_0x1286430/d; +L_0x12865d0/d .functor AND 1, L_0x1286150, L_0x1290600, C4<1>, C4<1>; +L_0x12865d0 .delay 1 (30000,30000,30000) L_0x12865d0/d; +v0xc96f30_0 .net "a", 0 0, L_0x1286150; alias, 1 drivers +v0xc96ff0_0 .net "b", 0 0, L_0x1290600; alias, 1 drivers +v0xc96af0_0 .net "carryout", 0 0, L_0x12865d0; alias, 1 drivers +v0xc96b90_0 .net "sum", 0 0, L_0x1286430; alias, 1 drivers +S_0xc73620 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0xcd1120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0xebf4d0_0 .net "ands", 7 0, L_0x128df50; 1 drivers +v0xebf140_0 .net "in", 7 0, L_0x12887c0; alias, 1 drivers +v0xebf200_0 .net "out", 0 0, L_0x128ff50; alias, 1 drivers +v0xebed90_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0xbbbcc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xc73620; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0xbf7be0_0 .net "A", 7 0, L_0x12887c0; alias, 1 drivers +v0xbf77a0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0xbf7860_0 .net *"_s0", 0 0, L_0x128c870; 1 drivers +v0xbf4ab0_0 .net *"_s12", 0 0, L_0x128d1e0; 1 drivers +v0xbf4b70_0 .net *"_s16", 0 0, L_0x128d540; 1 drivers +v0xc04510_0 .net *"_s20", 0 0, L_0x128d910; 1 drivers +v0xc04180_0 .net *"_s24", 0 0, L_0x128dc40; 1 drivers +v0xc014d0_0 .net *"_s28", 0 0, L_0x128dbd0; 1 drivers +v0xbc0b10_0 .net *"_s4", 0 0, L_0x128cbc0; 1 drivers +v0xbc0820_0 .net *"_s8", 0 0, L_0x128ced0; 1 drivers +v0xbc2bb0_0 .net "out", 7 0, L_0x128df50; alias, 1 drivers +L_0x128c930 .part L_0x12887c0, 0, 1; +L_0x128cb20 .part v0x127a150_0, 0, 1; +L_0x128cc80 .part L_0x12887c0, 1, 1; +L_0x128cde0 .part v0x127a150_0, 1, 1; +L_0x128cf90 .part L_0x12887c0, 2, 1; +L_0x128d0f0 .part v0x127a150_0, 2, 1; +L_0x128d2a0 .part L_0x12887c0, 3, 1; +L_0x128d400 .part v0x127a150_0, 3, 1; +L_0x128d600 .part L_0x12887c0, 4, 1; +L_0x128d870 .part v0x127a150_0, 4, 1; +L_0x128d980 .part L_0x12887c0, 5, 1; +L_0x128dae0 .part v0x127a150_0, 5, 1; +L_0x128dd00 .part L_0x12887c0, 6, 1; +L_0x128de60 .part v0x127a150_0, 6, 1; +LS_0x128df50_0_0 .concat8 [ 1 1 1 1], L_0x128c870, L_0x128cbc0, L_0x128ced0, L_0x128d1e0; +LS_0x128df50_0_4 .concat8 [ 1 1 1 1], L_0x128d540, L_0x128d910, L_0x128dc40, L_0x128dbd0; +L_0x128df50 .concat8 [ 4 4 0 0], LS_0x128df50_0_0, LS_0x128df50_0_4; +L_0x128e310 .part L_0x12887c0, 7, 1; +L_0x128e500 .part v0x127a150_0, 7, 1; +S_0xd740b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xd04fc0 .param/l "i" 0 4 54, +C4<00>; +L_0x128c870/d .functor AND 1, L_0x128c930, L_0x128cb20, C4<1>, C4<1>; +L_0x128c870 .delay 1 (30000,30000,30000) L_0x128c870/d; +v0xc41480_0 .net *"_s0", 0 0, L_0x128c930; 1 drivers +v0xc410f0_0 .net *"_s1", 0 0, L_0x128cb20; 1 drivers +S_0xfe4bf0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xcc3980 .param/l "i" 0 4 54, +C4<01>; +L_0x128cbc0/d .functor AND 1, L_0x128cc80, L_0x128cde0, C4<1>, C4<1>; +L_0x128cbc0 .delay 1 (30000,30000,30000) L_0x128cbc0/d; +v0xc4db30_0 .net *"_s0", 0 0, L_0x128cc80; 1 drivers +v0xc4d7a0_0 .net *"_s1", 0 0, L_0x128cde0; 1 drivers +S_0xfe4860 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xcd3e20 .param/l "i" 0 4 54, +C4<010>; +L_0x128ced0/d .functor AND 1, L_0x128cf90, L_0x128d0f0, C4<1>, C4<1>; +L_0x128ced0 .delay 1 (30000,30000,30000) L_0x128ced0/d; +v0xc4aaf0_0 .net *"_s0", 0 0, L_0x128cf90; 1 drivers +v0xc0a240_0 .net *"_s1", 0 0, L_0x128d0f0; 1 drivers +S_0xfe44b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xce0450 .param/l "i" 0 4 54, +C4<011>; +L_0x128d1e0/d .functor AND 1, L_0x128d2a0, L_0x128d400, C4<1>, C4<1>; +L_0x128d1e0 .delay 1 (30000,30000,30000) L_0x128d1e0/d; +v0xc08cd0_0 .net *"_s0", 0 0, L_0x128d2a0; 1 drivers +v0xc0c2c0_0 .net *"_s1", 0 0, L_0x128d400; 1 drivers +S_0xfc00e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xc411d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x128d540/d .functor AND 1, L_0x128d600, L_0x128d870, C4<1>, C4<1>; +L_0x128d540 .delay 1 (30000,30000,30000) L_0x128d540/d; +v0xc1c880_0 .net *"_s0", 0 0, L_0x128d600; 1 drivers +v0xc1c440_0 .net *"_s1", 0 0, L_0x128d870; 1 drivers +S_0xfbfd50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xc0a320 .param/l "i" 0 4 54, +C4<0101>; +L_0x128d910/d .functor AND 1, L_0x128d980, L_0x128dae0, C4<1>, C4<1>; +L_0x128d910 .delay 1 (30000,30000,30000) L_0x128d910/d; +v0xc290b0_0 .net *"_s0", 0 0, L_0x128d980; 1 drivers +v0xc28d20_0 .net *"_s1", 0 0, L_0x128dae0; 1 drivers +S_0xfbf9a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xc29190 .param/l "i" 0 4 54, +C4<0110>; +L_0x128dc40/d .functor AND 1, L_0x128dd00, L_0x128de60, C4<1>, C4<1>; +L_0x128dc40 .delay 1 (30000,30000,30000) L_0x128dc40/d; +v0xc26070_0 .net *"_s0", 0 0, L_0x128dd00; 1 drivers +v0xbe56d0_0 .net *"_s1", 0 0, L_0x128de60; 1 drivers +S_0xf9b6a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xbbbcc0; + .timescale -9 -12; +P_0xbe57b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x128dbd0/d .functor AND 1, L_0x128e310, L_0x128e500, C4<1>, C4<1>; +L_0x128dbd0 .delay 1 (30000,30000,30000) L_0x128dbd0/d; +v0xbe4160_0 .net *"_s0", 0 0, L_0x128e310; 1 drivers +v0xbe7750_0 .net *"_s1", 0 0, L_0x128e500; 1 drivers +S_0xf9b310 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xc73620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x128ff50/d .functor OR 1, L_0x1290010, L_0x12901c0, C4<0>, C4<0>; +L_0x128ff50 .delay 1 (30000,30000,30000) L_0x128ff50/d; +v0xee3fe0_0 .net *"_s10", 0 0, L_0x1290010; 1 drivers +v0xee40c0_0 .net *"_s12", 0 0, L_0x12901c0; 1 drivers +v0xee3c50_0 .net "in", 7 0, L_0x128df50; alias, 1 drivers +v0xee3cf0_0 .net "ors", 1 0, L_0x128fd70; 1 drivers +v0xee38a0_0 .net "out", 0 0, L_0x128ff50; alias, 1 drivers +L_0x128f140 .part L_0x128df50, 0, 4; +L_0x128fd70 .concat8 [ 1 1 0 0], L_0x128ee30, L_0x128fa60; +L_0x128feb0 .part L_0x128df50, 4, 4; +L_0x1290010 .part L_0x128fd70, 0, 1; +L_0x12901c0 .part L_0x128fd70, 1, 1; +S_0xf9af60 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xf9b310; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x128e5f0/d .functor OR 1, L_0x128e6b0, L_0x128e810, C4<0>, C4<0>; +L_0x128e5f0 .delay 1 (30000,30000,30000) L_0x128e5f0/d; +L_0x128ea40/d .functor OR 1, L_0x128eb50, L_0x128ecb0, C4<0>, C4<0>; +L_0x128ea40 .delay 1 (30000,30000,30000) L_0x128ea40/d; +L_0x128ee30/d .functor OR 1, L_0x128eea0, L_0x128f050, C4<0>, C4<0>; +L_0x128ee30 .delay 1 (30000,30000,30000) L_0x128ee30/d; +v0xbd3000_0 .net *"_s0", 0 0, L_0x128e5f0; 1 drivers +v0xbd2bc0_0 .net *"_s10", 0 0, L_0x128eb50; 1 drivers +v0xbdf9a0_0 .net *"_s12", 0 0, L_0x128ecb0; 1 drivers +v0xbdfa60_0 .net *"_s14", 0 0, L_0x128eea0; 1 drivers +v0xbdf610_0 .net *"_s16", 0 0, L_0x128f050; 1 drivers +v0xbdc7b0_0 .net *"_s3", 0 0, L_0x128e6b0; 1 drivers +v0xbae580_0 .net *"_s5", 0 0, L_0x128e810; 1 drivers +v0xbae1f0_0 .net *"_s6", 0 0, L_0x128ea40; 1 drivers +v0xbab540_0 .net "in", 3 0, L_0x128f140; 1 drivers +v0xbbad60_0 .net "ors", 1 0, L_0x128e950; 1 drivers +v0xbba920_0 .net "out", 0 0, L_0x128ee30; 1 drivers +L_0x128e6b0 .part L_0x128f140, 0, 1; +L_0x128e810 .part L_0x128f140, 1, 1; +L_0x128e950 .concat8 [ 1 1 0 0], L_0x128e5f0, L_0x128ea40; +L_0x128eb50 .part L_0x128f140, 2, 1; +L_0x128ecb0 .part L_0x128f140, 3, 1; +L_0x128eea0 .part L_0x128e950, 0, 1; +L_0x128f050 .part L_0x128e950, 1, 1; +S_0xf76c00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xf9b310; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x128f270/d .functor OR 1, L_0x128f2e0, L_0x128f440, C4<0>, C4<0>; +L_0x128f270 .delay 1 (30000,30000,30000) L_0x128f270/d; +L_0x128f670/d .functor OR 1, L_0x128f780, L_0x128f8e0, C4<0>, C4<0>; +L_0x128f670 .delay 1 (30000,30000,30000) L_0x128f670/d; +L_0x128fa60/d .functor OR 1, L_0x128fad0, L_0x128fc80, C4<0>, C4<0>; +L_0x128fa60 .delay 1 (30000,30000,30000) L_0x128fa60/d; +v0xbb7c30_0 .net *"_s0", 0 0, L_0x128f270; 1 drivers +v0xb8a620_0 .net *"_s10", 0 0, L_0x128f780; 1 drivers +v0xb8a290_0 .net *"_s12", 0 0, L_0x128f8e0; 1 drivers +v0xb8a350_0 .net *"_s14", 0 0, L_0x128fad0; 1 drivers +v0xb875e0_0 .net *"_s16", 0 0, L_0x128fc80; 1 drivers +v0xb96d20_0 .net *"_s3", 0 0, L_0x128f2e0; 1 drivers +v0xb968e0_0 .net *"_s5", 0 0, L_0x128f440; 1 drivers +v0xb93bf0_0 .net *"_s6", 0 0, L_0x128f670; 1 drivers +v0xf76870_0 .net "in", 3 0, L_0x128feb0; 1 drivers +v0xf764c0_0 .net "ors", 1 0, L_0x128f580; 1 drivers +v0xf765a0_0 .net "out", 0 0, L_0x128fa60; 1 drivers +L_0x128f2e0 .part L_0x128feb0, 0, 1; +L_0x128f440 .part L_0x128feb0, 1, 1; +L_0x128f580 .concat8 [ 1 1 0 0], L_0x128f270, L_0x128f670; +L_0x128f780 .part L_0x128feb0, 2, 1; +L_0x128f8e0 .part L_0x128feb0, 3, 1; +L_0x128fad0 .part L_0x128f580, 0, 1; +L_0x128fc80 .part L_0x128f580, 1, 1; +S_0xe9aa10 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0xcd1120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0xf968e0_0 .net "ands", 7 0, L_0x128a510; 1 drivers +v0xf521a0_0 .net "in", 7 0, L_0x1288480; alias, 1 drivers +v0xf52260_0 .net "out", 0 0, L_0x128c510; alias, 1 drivers +v0xf51e20_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0xe9a680 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xe9aa10; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0xc989b0_0 .net "A", 7 0, L_0x1288480; alias, 1 drivers +v0xc74680_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0xc74740_0 .net *"_s0", 0 0, L_0x1288d00; 1 drivers +v0xc742f0_0 .net *"_s12", 0 0, L_0x12896c0; 1 drivers +v0xc743d0_0 .net *"_s16", 0 0, L_0x1289a20; 1 drivers +v0xc73f80_0 .net *"_s20", 0 0, L_0x1289e50; 1 drivers +v0xc4fbd0_0 .net *"_s24", 0 0, L_0x128a180; 1 drivers +v0xc4fcb0_0 .net *"_s28", 0 0, L_0x128a110; 1 drivers +v0xc4f840_0 .net *"_s4", 0 0, L_0x12890a0; 1 drivers +v0xc4f490_0 .net *"_s8", 0 0, L_0x12893b0; 1 drivers +v0xc4f570_0 .net "out", 7 0, L_0x128a510; alias, 1 drivers +L_0x1288e10 .part L_0x1288480, 0, 1; +L_0x1289000 .part v0x127a150_0, 0, 1; +L_0x1289160 .part L_0x1288480, 1, 1; +L_0x12892c0 .part v0x127a150_0, 1, 1; +L_0x1289470 .part L_0x1288480, 2, 1; +L_0x12895d0 .part v0x127a150_0, 2, 1; +L_0x1289780 .part L_0x1288480, 3, 1; +L_0x12898e0 .part v0x127a150_0, 3, 1; +L_0x1289ae0 .part L_0x1288480, 4, 1; +L_0x1289d50 .part v0x127a150_0, 4, 1; +L_0x1289ec0 .part L_0x1288480, 5, 1; +L_0x128a020 .part v0x127a150_0, 5, 1; +L_0x128a240 .part L_0x1288480, 6, 1; +L_0x128a3a0 .part v0x127a150_0, 6, 1; +LS_0x128a510_0_0 .concat8 [ 1 1 1 1], L_0x1288d00, L_0x12890a0, L_0x12893b0, L_0x12896c0; +LS_0x128a510_0_4 .concat8 [ 1 1 1 1], L_0x1289a20, L_0x1289e50, L_0x128a180, L_0x128a110; +L_0x128a510 .concat8 [ 4 4 0 0], LS_0x128a510_0_0, LS_0x128a510_0_4; +L_0x128a8d0 .part L_0x1288480, 7, 1; +L_0x128aac0 .part v0x127a150_0, 7, 1; +S_0xe9a2d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xbae2d0 .param/l "i" 0 4 54, +C4<00>; +L_0x1288d00/d .functor AND 1, L_0x1288e10, L_0x1289000, C4<1>, C4<1>; +L_0x1288d00 .delay 1 (30000,30000,30000) L_0x1288d00/d; +v0xebee70_0 .net *"_s0", 0 0, L_0x1288e10; 1 drivers +v0xe75f90_0 .net *"_s1", 0 0, L_0x1289000; 1 drivers +S_0xe75c00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xb8a700 .param/l "i" 0 4 54, +C4<01>; +L_0x12890a0/d .functor AND 1, L_0x1289160, L_0x12892c0, C4<1>, C4<1>; +L_0x12890a0 .delay 1 (30000,30000,30000) L_0x12890a0/d; +v0xe75850_0 .net *"_s0", 0 0, L_0x1289160; 1 drivers +v0xdbe870_0 .net *"_s1", 0 0, L_0x12892c0; 1 drivers +S_0xdbe4e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xb93cd0 .param/l "i" 0 4 54, +C4<010>; +L_0x12893b0/d .functor AND 1, L_0x1289470, L_0x12895d0, C4<1>, C4<1>; +L_0x12893b0 .delay 1 (30000,30000,30000) L_0x12893b0/d; +v0xdbe950_0 .net *"_s0", 0 0, L_0x1289470; 1 drivers +v0xdbe130_0 .net *"_s1", 0 0, L_0x12895d0; 1 drivers +S_0xd99d50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xe75970 .param/l "i" 0 4 54, +C4<011>; +L_0x12896c0/d .functor AND 1, L_0x1289780, L_0x12898e0, C4<1>, C4<1>; +L_0x12896c0 .delay 1 (30000,30000,30000) L_0x12896c0/d; +v0xd999c0_0 .net *"_s0", 0 0, L_0x1289780; 1 drivers +v0xd99aa0_0 .net *"_s1", 0 0, L_0x12898e0; 1 drivers +S_0xd99610 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xd753c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1289a20/d .functor AND 1, L_0x1289ae0, L_0x1289d50, C4<1>, C4<1>; +L_0x1289a20 .delay 1 (30000,30000,30000) L_0x1289a20/d; +v0xd74f70_0 .net *"_s0", 0 0, L_0x1289ae0; 1 drivers +v0xd75050_0 .net *"_s1", 0 0, L_0x1289d50; 1 drivers +S_0xd50810 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xd74c90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1289e50/d .functor AND 1, L_0x1289ec0, L_0x128a020, C4<1>, C4<1>; +L_0x1289e50 .delay 1 (30000,30000,30000) L_0x1289e50/d; +v0xd50480_0 .net *"_s0", 0 0, L_0x1289ec0; 1 drivers +v0xd50560_0 .net *"_s1", 0 0, L_0x128a020; 1 drivers +S_0xcbdc10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xd501a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x128a180/d .functor AND 1, L_0x128a240, L_0x128a3a0, C4<1>, C4<1>; +L_0x128a180 .delay 1 (30000,30000,30000) L_0x128a180/d; +v0xcbd880_0 .net *"_s0", 0 0, L_0x128a240; 1 drivers +v0xcbd960_0 .net *"_s1", 0 0, L_0x128a3a0; 1 drivers +S_0xc990b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xe9a680; + .timescale -9 -12; +P_0xcbd5a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x128a110/d .functor AND 1, L_0x128a8d0, L_0x128aac0, C4<1>, C4<1>; +L_0x128a110 .delay 1 (30000,30000,30000) L_0x128a110/d; +v0xc98d20_0 .net *"_s0", 0 0, L_0x128a8d0; 1 drivers +v0xc98e00_0 .net *"_s1", 0 0, L_0x128aac0; 1 drivers +S_0xbbcb50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xe9aa10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x128c510/d .functor OR 1, L_0x128c5d0, L_0x128c780, C4<0>, C4<0>; +L_0x128c510 .delay 1 (30000,30000,30000) L_0x128c510/d; +v0xfbb350_0 .net *"_s10", 0 0, L_0x128c5d0; 1 drivers +v0xfbb430_0 .net *"_s12", 0 0, L_0x128c780; 1 drivers +v0xf7a690_0 .net "in", 7 0, L_0x128a510; alias, 1 drivers +v0xf7a730_0 .net "ors", 1 0, L_0x128c330; 1 drivers +v0xf99470_0 .net "out", 0 0, L_0x128c510; alias, 1 drivers +L_0x128b700 .part L_0x128a510, 0, 4; +L_0x128c330 .concat8 [ 1 1 0 0], L_0x128b3f0, L_0x128c020; +L_0x128c470 .part L_0x128a510, 4, 4; +L_0x128c5d0 .part L_0x128c330, 0, 1; +L_0x128c780 .part L_0x128c330, 1, 1; +S_0xbbc7a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xbbcb50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x128abb0/d .functor OR 1, L_0x128ac70, L_0x128add0, C4<0>, C4<0>; +L_0x128abb0 .delay 1 (30000,30000,30000) L_0x128abb0/d; +L_0x128b000/d .functor OR 1, L_0x128b110, L_0x128b270, C4<0>, C4<0>; +L_0x128b000 .delay 1 (30000,30000,30000) L_0x128b000/d; +L_0x128b3f0/d .functor OR 1, L_0x128b460, L_0x128b610, C4<0>, C4<0>; +L_0x128b3f0 .delay 1 (30000,30000,30000) L_0x128b3f0/d; +v0xb98f70_0 .net *"_s0", 0 0, L_0x128abb0; 1 drivers +v0xb98810_0 .net *"_s10", 0 0, L_0x128b110; 1 drivers +v0xb988f0_0 .net *"_s12", 0 0, L_0x128b270; 1 drivers +v0x1026530_0 .net *"_s14", 0 0, L_0x128b460; 1 drivers +v0x1026610_0 .net *"_s16", 0 0, L_0x128b610; 1 drivers +v0xbe08a0_0 .net *"_s3", 0 0, L_0x128ac70; 1 drivers +v0xbe0980_0 .net *"_s5", 0 0, L_0x128add0; 1 drivers +v0x10236d0_0 .net *"_s6", 0 0, L_0x128b000; 1 drivers +v0x10237b0_0 .net "in", 3 0, L_0x128b700; 1 drivers +v0x1015420_0 .net "ors", 1 0, L_0x128af10; 1 drivers +v0x101bdd0_0 .net "out", 0 0, L_0x128b3f0; 1 drivers +L_0x128ac70 .part L_0x128b700, 0, 1; +L_0x128add0 .part L_0x128b700, 1, 1; +L_0x128af10 .concat8 [ 1 1 0 0], L_0x128abb0, L_0x128b000; +L_0x128b110 .part L_0x128b700, 2, 1; +L_0x128b270 .part L_0x128b700, 3, 1; +L_0x128b460 .part L_0x128af10, 0, 1; +L_0x128b610 .part L_0x128af10, 1, 1; +S_0x101eae0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xbbcb50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x128b830/d .functor OR 1, L_0x128b8a0, L_0x128ba00, C4<0>, C4<0>; +L_0x128b830 .delay 1 (30000,30000,30000) L_0x128b830/d; +L_0x128bc30/d .functor OR 1, L_0x128bd40, L_0x128bea0, C4<0>, C4<0>; +L_0x128bc30 .delay 1 (30000,30000,30000) L_0x128bc30/d; +L_0x128c020/d .functor OR 1, L_0x128c090, L_0x128c240, C4<0>, C4<0>; +L_0x128c020 .delay 1 (30000,30000,30000) L_0x128c020/d; +v0x1018090_0 .net *"_s0", 0 0, L_0x128b830; 1 drivers +v0x1018150_0 .net *"_s10", 0 0, L_0x128bd40; 1 drivers +v0xff80d0_0 .net *"_s12", 0 0, L_0x128bea0; 1 drivers +v0xff8190_0 .net *"_s14", 0 0, L_0x128c090; 1 drivers +v0x10049b0_0 .net *"_s16", 0 0, L_0x128c240; 1 drivers +v0xfc3b70_0 .net *"_s3", 0 0, L_0x128b8a0; 1 drivers +v0xfc3c50_0 .net *"_s5", 0 0, L_0x128ba00; 1 drivers +v0xfd6150_0 .net *"_s6", 0 0, L_0x128bc30; 1 drivers +v0xfd6230_0 .net "in", 3 0, L_0x128c470; 1 drivers +v0xfdff10_0 .net "ors", 1 0, L_0x128bb40; 1 drivers +v0xf9f130_0 .net "out", 0 0, L_0x128c020; 1 drivers +L_0x128b8a0 .part L_0x128c470, 0, 1; +L_0x128ba00 .part L_0x128c470, 1, 1; +L_0x128bb40 .concat8 [ 1 1 0 0], L_0x128b830, L_0x128bc30; +L_0x128bd40 .part L_0x128c470, 2, 1; +L_0x128bea0 .part L_0x128c470, 3, 1; +L_0x128c090 .part L_0x128bb40, 0, 1; +L_0x128c240 .part L_0x128bb40, 1, 1; +S_0xf2d710 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0xcd1120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1287200/d .functor XNOR 1, L_0x1290400, L_0x1290560, C4<0>, C4<0>; +L_0x1287200 .delay 1 (20000,20000,20000) L_0x1287200/d; +L_0x1287380/d .functor AND 1, L_0x1290400, L_0x1285fc0, C4<1>, C4<1>; +L_0x1287380 .delay 1 (30000,30000,30000) L_0x1287380/d; +L_0x12874e0/d .functor AND 1, L_0x1287200, L_0x1290600, C4<1>, C4<1>; +L_0x12874e0 .delay 1 (30000,30000,30000) L_0x12874e0/d; +L_0x12875f0/d .functor OR 1, L_0x12874e0, L_0x1287380, C4<0>, C4<0>; +L_0x12875f0 .delay 1 (30000,30000,30000) L_0x12875f0/d; +v0xf2d390_0 .net "a", 0 0, L_0x1290400; alias, 1 drivers +v0xf2d480_0 .net "a_", 0 0, L_0x127b9d0; alias, 1 drivers +v0xf1c0f0_0 .net "b", 0 0, L_0x1290560; alias, 1 drivers +v0xf1c1e0_0 .net "b_", 0 0, L_0x1285fc0; alias, 1 drivers +v0xf08b90_0 .net "carryin", 0 0, L_0x1290600; alias, 1 drivers +v0xf08810_0 .net "eq", 0 0, L_0x1287200; 1 drivers +v0xf088b0_0 .net "lt", 0 0, L_0x1287380; 1 drivers +v0xef74e0_0 .net "out", 0 0, L_0x12875f0; 1 drivers +v0xef75a0_0 .net "w0", 0 0, L_0x12874e0; 1 drivers +S_0xf03dc0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xcd1120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1286de0/d .functor OR 1, L_0x12868e0, L_0xe51540, C4<0>, C4<0>; +L_0x1286de0 .delay 1 (30000,30000,30000) L_0x1286de0/d; +v0xe95d80_0 .net "a", 0 0, L_0x1290400; alias, 1 drivers +v0xe54f50_0 .net "b", 0 0, L_0x1285fc0; alias, 1 drivers +v0xe54ff0_0 .net "c1", 0 0, L_0x12868e0; 1 drivers +v0xe73d80_0 .net "c2", 0 0, L_0xe51540; 1 drivers +v0xe73e20_0 .net "carryin", 0 0, L_0x1290600; alias, 1 drivers +v0xe515d0_0 .net "carryout", 0 0, L_0x1286de0; 1 drivers +v0xe511c0_0 .net "s1", 0 0, L_0xc65f60; 1 drivers +v0xe51260_0 .net "sum", 0 0, L_0x1286a40; 1 drivers +S_0xec2f60 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xf03dc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0xc65f60/d .functor XOR 1, L_0x1290400, L_0x1285fc0, C4<0>, C4<0>; +L_0xc65f60 .delay 1 (30000,30000,30000) L_0xc65f60/d; +L_0x12868e0/d .functor AND 1, L_0x1290400, L_0x1285fc0, C4<1>, C4<1>; +L_0x12868e0 .delay 1 (30000,30000,30000) L_0x12868e0/d; +v0xed5530_0 .net "a", 0 0, L_0x1290400; alias, 1 drivers +v0xed55d0_0 .net "b", 0 0, L_0x1285fc0; alias, 1 drivers +v0xedf260_0 .net "carryout", 0 0, L_0x12868e0; alias, 1 drivers +v0xedf300_0 .net "sum", 0 0, L_0xc65f60; alias, 1 drivers +S_0xe9e4a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xf03dc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1286a40/d .functor XOR 1, L_0xc65f60, L_0x1290600, C4<0>, C4<0>; +L_0x1286a40 .delay 1 (30000,30000,30000) L_0x1286a40/d; +L_0xe51540/d .functor AND 1, L_0xc65f60, L_0x1290600, C4<1>, C4<1>; +L_0xe51540 .delay 1 (30000,30000,30000) L_0xe51540/d; +v0xeba7b0_0 .net "a", 0 0, L_0xc65f60; alias, 1 drivers +v0xe79a20_0 .net "b", 0 0, L_0x1290600; alias, 1 drivers +v0xe79ac0_0 .net "carryout", 0 0, L_0xe51540; alias, 1 drivers +v0xe95c80_0 .net "sum", 0 0, L_0x1286a40; alias, 1 drivers +S_0xd3f440 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0xb98bc0; + .timescale -9 -12; +L_0x2ac4328836d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12863c0/d .functor OR 1, L_0x2ac4328836d8, L_0x2ac432883720, C4<0>, C4<0>; +L_0x12863c0 .delay 1 (30000,30000,30000) L_0x12863c0/d; +v0xd2be10_0 .net/2u *"_s0", 0 0, L_0x2ac4328836d8; 1 drivers +v0xd2bed0_0 .net/2u *"_s2", 0 0, L_0x2ac432883720; 1 drivers +S_0xd2ba90 .scope generate, "alu_slices[2]" "alu_slices[2]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1008760 .param/l "i" 0 3 39, +C4<010>; +S_0xd07350 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0xd2ba90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1290790/d .functor NOT 1, L_0x129ad30, C4<0>, C4<0>, C4<0>; +L_0x1290790 .delay 1 (10000,10000,10000) L_0x1290790/d; +L_0x12908f0/d .functor NOT 1, L_0x129af20, C4<0>, C4<0>, C4<0>; +L_0x12908f0 .delay 1 (10000,10000,10000) L_0x12908f0/d; +L_0x12918a0/d .functor XOR 1, L_0x129ad30, L_0x129af20, C4<0>, C4<0>; +L_0x12918a0 .delay 1 (30000,30000,30000) L_0x12918a0/d; +L_0x2ac432883768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328837b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1291960/d .functor OR 1, L_0x2ac432883768, L_0x2ac4328837b0, C4<0>, C4<0>; +L_0x1291960 .delay 1 (30000,30000,30000) L_0x1291960/d; +L_0x2ac4328837f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883840 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1292100/d .functor OR 1, L_0x2ac4328837f8, L_0x2ac432883840, C4<0>, C4<0>; +L_0x1292100 .delay 1 (30000,30000,30000) L_0x1292100/d; +L_0x1292300/d .functor AND 1, L_0x129ad30, L_0x129af20, C4<1>, C4<1>; +L_0x1292300 .delay 1 (30000,30000,30000) L_0x1292300/d; +L_0x2ac432883888 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328838d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12923c0/d .functor OR 1, L_0x2ac432883888, L_0x2ac4328838d0, C4<0>, C4<0>; +L_0x12923c0 .delay 1 (30000,30000,30000) L_0x12923c0/d; +L_0x12925c0/d .functor NAND 1, L_0x129ad30, L_0x129af20, C4<1>, C4<1>; +L_0x12925c0 .delay 1 (20000,20000,20000) L_0x12925c0/d; +L_0x2ac432883918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12926d0/d .functor OR 1, L_0x2ac432883918, L_0x2ac432883960, C4<0>, C4<0>; +L_0x12926d0 .delay 1 (30000,30000,30000) L_0x12926d0/d; +L_0x1292880/d .functor NOR 1, L_0x129ad30, L_0x129af20, C4<0>, C4<0>; +L_0x1292880 .delay 1 (20000,20000,20000) L_0x1292880/d; +L_0x2ac4328839a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328839f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1290c10/d .functor OR 1, L_0x2ac4328839a8, L_0x2ac4328839f0, C4<0>, C4<0>; +L_0x1290c10 .delay 1 (30000,30000,30000) L_0x1290c10/d; +L_0x1293030/d .functor OR 1, L_0x129ad30, L_0x129af20, C4<0>, C4<0>; +L_0x1293030 .delay 1 (30000,30000,30000) L_0x1293030/d; +L_0x2ac432883a38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883a80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12934d0/d .functor OR 1, L_0x2ac432883a38, L_0x2ac432883a80, C4<0>, C4<0>; +L_0x12934d0 .delay 1 (30000,30000,30000) L_0x12934d0/d; +L_0x129ac30/d .functor NOT 1, L_0x1296e90, C4<0>, C4<0>, C4<0>; +L_0x129ac30 .delay 1 (10000,10000,10000) L_0x129ac30/d; +v0x1056530_0 .net "A", 0 0, L_0x129ad30; 1 drivers +v0x10565f0_0 .net "A_", 0 0, L_0x1290790; 1 drivers +v0x10566b0_0 .net "B", 0 0, L_0x129af20; 1 drivers +v0x1056780_0 .net "B_", 0 0, L_0x12908f0; 1 drivers +v0x1056820_0 .net *"_s11", 0 0, L_0x1291960; 1 drivers +v0x1056910_0 .net/2s *"_s13", 0 0, L_0x2ac432883768; 1 drivers +v0x10569d0_0 .net/2s *"_s15", 0 0, L_0x2ac4328837b0; 1 drivers +v0x1056ab0_0 .net *"_s19", 0 0, L_0x1292100; 1 drivers +v0x1056b90_0 .net/2s *"_s21", 0 0, L_0x2ac4328837f8; 1 drivers +v0x1056d00_0 .net/2s *"_s23", 0 0, L_0x2ac432883840; 1 drivers +v0x1056de0_0 .net *"_s25", 0 0, L_0x1292300; 1 drivers +v0x1056ec0_0 .net *"_s28", 0 0, L_0x12923c0; 1 drivers +v0x1056fa0_0 .net/2s *"_s30", 0 0, L_0x2ac432883888; 1 drivers +v0x1057080_0 .net/2s *"_s32", 0 0, L_0x2ac4328838d0; 1 drivers +v0x1057160_0 .net *"_s34", 0 0, L_0x12925c0; 1 drivers +v0x1057240_0 .net *"_s37", 0 0, L_0x12926d0; 1 drivers +v0x1057320_0 .net/2s *"_s39", 0 0, L_0x2ac432883918; 1 drivers +v0x10574d0_0 .net/2s *"_s41", 0 0, L_0x2ac432883960; 1 drivers +v0x1057570_0 .net *"_s43", 0 0, L_0x1292880; 1 drivers +v0x1057650_0 .net *"_s46", 0 0, L_0x1290c10; 1 drivers +v0x1057730_0 .net/2s *"_s48", 0 0, L_0x2ac4328839a8; 1 drivers +v0x1057810_0 .net/2s *"_s50", 0 0, L_0x2ac4328839f0; 1 drivers +v0x10578f0_0 .net *"_s52", 0 0, L_0x1293030; 1 drivers +v0x10579d0_0 .net *"_s56", 0 0, L_0x12934d0; 1 drivers +v0x1057ab0_0 .net/2s *"_s59", 0 0, L_0x2ac432883a38; 1 drivers +v0x1057b90_0 .net/2s *"_s61", 0 0, L_0x2ac432883a80; 1 drivers +v0x1057c70_0 .net *"_s8", 0 0, L_0x12918a0; 1 drivers +v0x1057d50_0 .net "carryin", 0 0, L_0x129b050; 1 drivers +v0x1057df0_0 .net "carryout", 0 0, L_0x129a8d0; 1 drivers +v0x1057e90_0 .net "carryouts", 7 0, L_0x1293140; 1 drivers +v0x1057fa0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1058060_0 .net "result", 0 0, L_0x1296e90; 1 drivers +v0x1058150_0 .net "results", 7 0, L_0x1292db0; 1 drivers +v0x1057430_0 .net "zero", 0 0, L_0x129ac30; 1 drivers +LS_0x1292db0_0_0 .concat8 [ 1 1 1 1], L_0x1290d20, L_0x12913a0, L_0x12918a0, L_0x1292100; +LS_0x1292db0_0_4 .concat8 [ 1 1 1 1], L_0x1292300, L_0x12925c0, L_0x1292880, L_0x1293030; +L_0x1292db0 .concat8 [ 4 4 0 0], LS_0x1292db0_0_0, LS_0x1292db0_0_4; +LS_0x1293140_0_0 .concat8 [ 1 1 1 1], L_0x1291020, L_0x1291740, L_0x1291960, L_0x1291f50; +LS_0x1293140_0_4 .concat8 [ 1 1 1 1], L_0x12923c0, L_0x12926d0, L_0x1290c10, L_0x12934d0; +L_0x1293140 .concat8 [ 4 4 0 0], LS_0x1293140_0_0, LS_0x1293140_0_4; +S_0xd06fd0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xd07350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1291020/d .functor OR 1, L_0x1290b50, L_0x1290f10, C4<0>, C4<0>; +L_0x1291020 .delay 1 (30000,30000,30000) L_0x1291020/d; +v0xc53660_0 .net "a", 0 0, L_0x129ad30; alias, 1 drivers +v0xc53720_0 .net "b", 0 0, L_0x129af20; alias, 1 drivers +v0xc72470_0 .net "c1", 0 0, L_0x1290b50; 1 drivers +v0xc72510_0 .net "c2", 0 0, L_0x1290f10; 1 drivers +v0xc6f8d0_0 .net "carryin", 0 0, L_0x129b050; alias, 1 drivers +v0xc6f9c0_0 .net "carryout", 0 0, L_0x1291020; 1 drivers +v0xc2b190_0 .net "s1", 0 0, L_0x1290ae0; 1 drivers +v0xc2b280_0 .net "sum", 0 0, L_0x1290d20; 1 drivers +S_0xce27e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xd06fd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1290ae0/d .functor XOR 1, L_0x129ad30, L_0x129af20, C4<0>, C4<0>; +L_0x1290ae0 .delay 1 (30000,30000,30000) L_0x1290ae0/d; +L_0x1290b50/d .functor AND 1, L_0x129ad30, L_0x129af20, C4<1>, C4<1>; +L_0x1290b50 .delay 1 (30000,30000,30000) L_0x1290b50/d; +v0xce2460_0 .net "a", 0 0, L_0x129ad30; alias, 1 drivers +v0xce2500_0 .net "b", 0 0, L_0x129af20; alias, 1 drivers +v0xcdda10_0 .net "carryout", 0 0, L_0x1290b50; alias, 1 drivers +v0xcddab0_0 .net "sum", 0 0, L_0x1290ae0; alias, 1 drivers +S_0xc9cb40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xd06fd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1290d20/d .functor XOR 1, L_0x1290ae0, L_0x129b050, C4<0>, C4<0>; +L_0x1290d20 .delay 1 (30000,30000,30000) L_0x1290d20/d; +L_0x1290f10/d .functor AND 1, L_0x1290ae0, L_0x129b050, C4<1>, C4<1>; +L_0x1290f10 .delay 1 (30000,30000,30000) L_0x1290f10/d; +v0xcb8ee0_0 .net "a", 0 0, L_0x1290ae0; alias, 1 drivers +v0xc78110_0 .net "b", 0 0, L_0x129b050; alias, 1 drivers +v0xc781b0_0 .net "carryout", 0 0, L_0x1290f10; alias, 1 drivers +v0xc94320_0 .net "sum", 0 0, L_0x1290d20; alias, 1 drivers +S_0xc2ae10 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0xd07350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0xa31f50_0 .net "ands", 7 0, L_0x12988d0; 1 drivers +v0xa32010_0 .net "in", 7 0, L_0x1293140; alias, 1 drivers +v0xa27930_0 .net "out", 0 0, L_0x129a8d0; alias, 1 drivers +v0xa279d0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0xc065f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xc2ae10; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0xb4a5b0_0 .net "A", 7 0, L_0x1293140; alias, 1 drivers +v0xb3fef0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0xb35870_0 .net *"_s0", 0 0, L_0x12971f0; 1 drivers +v0xb35930_0 .net *"_s12", 0 0, L_0x1297b60; 1 drivers +v0xb2b250_0 .net *"_s16", 0 0, L_0x1297ec0; 1 drivers +v0xb20c30_0 .net *"_s20", 0 0, L_0x1298290; 1 drivers +v0xb20d10_0 .net *"_s24", 0 0, L_0x12985c0; 1 drivers +v0xb16610_0 .net *"_s28", 0 0, L_0x1298550; 1 drivers +v0xb166f0_0 .net *"_s4", 0 0, L_0x1297540; 1 drivers +v0xb0bff0_0 .net *"_s8", 0 0, L_0x1297850; 1 drivers +v0xb0c0d0_0 .net "out", 7 0, L_0x12988d0; alias, 1 drivers +L_0x12972b0 .part L_0x1293140, 0, 1; +L_0x12974a0 .part v0x127a150_0, 0, 1; +L_0x1297600 .part L_0x1293140, 1, 1; +L_0x1297760 .part v0x127a150_0, 1, 1; +L_0x1297910 .part L_0x1293140, 2, 1; +L_0x1297a70 .part v0x127a150_0, 2, 1; +L_0x1297c20 .part L_0x1293140, 3, 1; +L_0x1297d80 .part v0x127a150_0, 3, 1; +L_0x1297f80 .part L_0x1293140, 4, 1; +L_0x12981f0 .part v0x127a150_0, 4, 1; +L_0x1298300 .part L_0x1293140, 5, 1; +L_0x1298460 .part v0x127a150_0, 5, 1; +L_0x1298680 .part L_0x1293140, 6, 1; +L_0x12987e0 .part v0x127a150_0, 6, 1; +LS_0x12988d0_0_0 .concat8 [ 1 1 1 1], L_0x12971f0, L_0x1297540, L_0x1297850, L_0x1297b60; +LS_0x12988d0_0_4 .concat8 [ 1 1 1 1], L_0x1297ec0, L_0x1298290, L_0x12985c0, L_0x1298550; +L_0x12988d0 .concat8 [ 4 4 0 0], LS_0x12988d0_0_0, LS_0x12988d0_0_4; +L_0x1298c90 .part L_0x1293140, 7, 1; +L_0x1298e80 .part v0x127a150_0, 7, 1; +S_0xbf4fd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xc06330 .param/l "i" 0 4 54, +C4<00>; +L_0x12971f0/d .functor AND 1, L_0x12972b0, L_0x12974a0, C4<1>, C4<1>; +L_0x12971f0 .delay 1 (30000,30000,30000) L_0x12971f0/d; +v0xbe1a80_0 .net *"_s0", 0 0, L_0x12972b0; 1 drivers +v0xbe1b60_0 .net *"_s1", 0 0, L_0x12974a0; 1 drivers +S_0xbe1700 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xbbf2d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1297540/d .functor AND 1, L_0x1297600, L_0x1297760, C4<1>, C4<1>; +L_0x1297540 .delay 1 (30000,30000,30000) L_0x1297540/d; +v0xbd03f0_0 .net *"_s0", 0 0, L_0x1297600; 1 drivers +v0xbd04d0_0 .net *"_s1", 0 0, L_0x1297760; 1 drivers +S_0xbdccd0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xb9be40 .param/l "i" 0 4 54, +C4<010>; +L_0x1297850/d .functor AND 1, L_0x1297910, L_0x1297a70, C4<1>, C4<1>; +L_0x1297850 .delay 1 (30000,30000,30000) L_0x1297850/d; +v0xb9bee0_0 .net *"_s0", 0 0, L_0x1297910; 1 drivers +v0xbb8150_0 .net *"_s1", 0 0, L_0x1297a70; 1 drivers +S_0xb77e80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xbb8280 .param/l "i" 0 4 54, +C4<011>; +L_0x1297b60/d .functor AND 1, L_0x1297c20, L_0x1297d80, C4<1>, C4<1>; +L_0x1297b60 .delay 1 (30000,30000,30000) L_0x1297b60/d; +v0xb94160_0 .net *"_s0", 0 0, L_0x1297c20; 1 drivers +v0xdc2190_0 .net *"_s1", 0 0, L_0x1297d80; 1 drivers +S_0xf512f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xdc22c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1297ec0/d .functor AND 1, L_0x1297f80, L_0x12981f0, C4<1>, C4<1>; +L_0x1297ec0 .delay 1 (30000,30000,30000) L_0x1297ec0/d; +v0xf2c8d0_0 .net *"_s0", 0 0, L_0x1297f80; 1 drivers +v0xf07ce0_0 .net *"_s1", 0 0, L_0x12981f0; 1 drivers +S_0xe50690 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xf07dc0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1298290/d .functor AND 1, L_0x1298300, L_0x1298460, C4<1>, C4<1>; +L_0x1298290 .delay 1 (30000,30000,30000) L_0x1298290/d; +v0xe2bc50_0 .net *"_s0", 0 0, L_0x1298300; 1 drivers +v0xe2bd30_0 .net *"_s1", 0 0, L_0x1298460; 1 drivers +S_0xe07020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xde2570 .param/l "i" 0 4 54, +C4<0110>; +L_0x12985c0/d .functor AND 1, L_0x1298680, L_0x12987e0, C4<1>, C4<1>; +L_0x12985c0 .delay 1 (30000,30000,30000) L_0x12985c0/d; +v0xb69710_0 .net *"_s0", 0 0, L_0x1298680; 1 drivers +v0xb697f0_0 .net *"_s1", 0 0, L_0x12987e0; 1 drivers +S_0xb5f0f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xc065f0; + .timescale -9 -12; +P_0xb54ad0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1298550/d .functor AND 1, L_0x1298c90, L_0x1298e80, C4<1>, C4<1>; +L_0x1298550 .delay 1 (30000,30000,30000) L_0x1298550/d; +v0xb54bb0_0 .net *"_s0", 0 0, L_0x1298c90; 1 drivers +v0xb4a4d0_0 .net *"_s1", 0 0, L_0x1298e80; 1 drivers +S_0xaf73b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xc2ae10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x129a8d0/d .functor OR 1, L_0x129a990, L_0x129ab40, C4<0>, C4<0>; +L_0x129a8d0 .delay 1 (30000,30000,30000) L_0x129a8d0/d; +v0xa511b0_0 .net *"_s10", 0 0, L_0x129a990; 1 drivers +v0xa51270_0 .net *"_s12", 0 0, L_0x129ab40; 1 drivers +v0xa46b90_0 .net "in", 7 0, L_0x12988d0; alias, 1 drivers +v0xa46c30_0 .net "ors", 1 0, L_0x129a6f0; 1 drivers +v0xa3c570_0 .net "out", 0 0, L_0x129a8d0; alias, 1 drivers +L_0x1299ac0 .part L_0x12988d0, 0, 4; +L_0x129a6f0 .concat8 [ 1 1 0 0], L_0x12997b0, L_0x129a3e0; +L_0x129a830 .part L_0x12988d0, 4, 4; +L_0x129a990 .part L_0x129a6f0, 0, 1; +L_0x129ab40 .part L_0x129a6f0, 1, 1; +S_0xaecd90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xaf73b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1298f70/d .functor OR 1, L_0x1299030, L_0x1299190, C4<0>, C4<0>; +L_0x1298f70 .delay 1 (30000,30000,30000) L_0x1298f70/d; +L_0x12993c0/d .functor OR 1, L_0x12994d0, L_0x1299630, C4<0>, C4<0>; +L_0x12993c0 .delay 1 (30000,30000,30000) L_0x12993c0/d; +L_0x12997b0/d .functor OR 1, L_0x1299820, L_0x12999d0, C4<0>, C4<0>; +L_0x12997b0 .delay 1 (30000,30000,30000) L_0x12997b0/d; +v0xae2770_0 .net *"_s0", 0 0, L_0x1298f70; 1 drivers +v0xae2870_0 .net *"_s10", 0 0, L_0x12994d0; 1 drivers +v0xad8150_0 .net *"_s12", 0 0, L_0x1299630; 1 drivers +v0xad8230_0 .net *"_s14", 0 0, L_0x1299820; 1 drivers +v0xacdb30_0 .net *"_s16", 0 0, L_0x12999d0; 1 drivers +v0xacdc40_0 .net *"_s3", 0 0, L_0x1299030; 1 drivers +v0xac3550_0 .net *"_s5", 0 0, L_0x1299190; 1 drivers +v0xab8ef0_0 .net *"_s6", 0 0, L_0x12993c0; 1 drivers +v0xab8fd0_0 .net "in", 3 0, L_0x1299ac0; 1 drivers +v0xaae8f0_0 .net "ors", 1 0, L_0x12992d0; 1 drivers +v0xaae9d0_0 .net "out", 0 0, L_0x12997b0; 1 drivers +L_0x1299030 .part L_0x1299ac0, 0, 1; +L_0x1299190 .part L_0x1299ac0, 1, 1; +L_0x12992d0 .concat8 [ 1 1 0 0], L_0x1298f70, L_0x12993c0; +L_0x12994d0 .part L_0x1299ac0, 2, 1; +L_0x1299630 .part L_0x1299ac0, 3, 1; +L_0x1299820 .part L_0x12992d0, 0, 1; +L_0x12999d0 .part L_0x12992d0, 1, 1; +S_0xa99c90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xaf73b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1299bf0/d .functor OR 1, L_0x1299c60, L_0x1299dc0, C4<0>, C4<0>; +L_0x1299bf0 .delay 1 (30000,30000,30000) L_0x1299bf0/d; +L_0x1299ff0/d .functor OR 1, L_0x129a100, L_0x129a260, C4<0>, C4<0>; +L_0x1299ff0 .delay 1 (30000,30000,30000) L_0x1299ff0/d; +L_0x129a3e0/d .functor OR 1, L_0x129a450, L_0x129a600, C4<0>, C4<0>; +L_0x129a3e0 .delay 1 (30000,30000,30000) L_0x129a3e0/d; +v0xaa4370_0 .net *"_s0", 0 0, L_0x1299bf0; 1 drivers +v0xa8f670_0 .net *"_s10", 0 0, L_0x129a100; 1 drivers +v0xa8f750_0 .net *"_s12", 0 0, L_0x129a260; 1 drivers +v0xa85050_0 .net *"_s14", 0 0, L_0x129a450; 1 drivers +v0xa85130_0 .net *"_s16", 0 0, L_0x129a600; 1 drivers +v0xa7aac0_0 .net *"_s3", 0 0, L_0x1299c60; 1 drivers +v0xa70410_0 .net *"_s5", 0 0, L_0x1299dc0; 1 drivers +v0xa704f0_0 .net *"_s6", 0 0, L_0x1299ff0; 1 drivers +v0xa65df0_0 .net "in", 3 0, L_0x129a830; 1 drivers +v0xa5b7d0_0 .net "ors", 1 0, L_0x1299f00; 1 drivers +v0xa5b8b0_0 .net "out", 0 0, L_0x129a3e0; 1 drivers +L_0x1299c60 .part L_0x129a830, 0, 1; +L_0x1299dc0 .part L_0x129a830, 1, 1; +L_0x1299f00 .concat8 [ 1 1 0 0], L_0x1299bf0, L_0x1299ff0; +L_0x129a100 .part L_0x129a830, 2, 1; +L_0x129a260 .part L_0x129a830, 3, 1; +L_0x129a450 .part L_0x1299f00, 0, 1; +L_0x129a600 .part L_0x1299f00, 1, 1; +S_0xf51a80 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0xd07350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x8f03e0_0 .net "ands", 7 0, L_0x1294e90; 1 drivers +v0x8f04f0_0 .net "in", 7 0, L_0x1292db0; alias, 1 drivers +v0x8f05b0_0 .net "out", 0 0, L_0x1296e90; alias, 1 drivers +v0x8f0650_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0xf2cff0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xf51a80; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x8d1360_0 .net "A", 7 0, L_0x1292db0; alias, 1 drivers +v0x8d1460_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x8d2ab0_0 .net *"_s0", 0 0, L_0x1293680; 1 drivers +v0x8d2b70_0 .net *"_s12", 0 0, L_0x1294040; 1 drivers +v0x8d2c50_0 .net *"_s16", 0 0, L_0x12943a0; 1 drivers +v0x8d2d80_0 .net *"_s20", 0 0, L_0x12947d0; 1 drivers +v0x8cdd00_0 .net *"_s24", 0 0, L_0x1294b00; 1 drivers +v0x8cdde0_0 .net *"_s28", 0 0, L_0x1294a90; 1 drivers +v0x8cdec0_0 .net *"_s4", 0 0, L_0x1293a20; 1 drivers +v0x8cf890_0 .net *"_s8", 0 0, L_0x1293d30; 1 drivers +v0x8cf970_0 .net "out", 7 0, L_0x1294e90; alias, 1 drivers +L_0x1293790 .part L_0x1292db0, 0, 1; +L_0x1293980 .part v0x127a150_0, 0, 1; +L_0x1293ae0 .part L_0x1292db0, 1, 1; +L_0x1293c40 .part v0x127a150_0, 1, 1; +L_0x1293df0 .part L_0x1292db0, 2, 1; +L_0x1293f50 .part v0x127a150_0, 2, 1; +L_0x1294100 .part L_0x1292db0, 3, 1; +L_0x1294260 .part v0x127a150_0, 3, 1; +L_0x1294460 .part L_0x1292db0, 4, 1; +L_0x12946d0 .part v0x127a150_0, 4, 1; +L_0x1294840 .part L_0x1292db0, 5, 1; +L_0x12949a0 .part v0x127a150_0, 5, 1; +L_0x1294bc0 .part L_0x1292db0, 6, 1; +L_0x1294d20 .part v0x127a150_0, 6, 1; +LS_0x1294e90_0_0 .concat8 [ 1 1 1 1], L_0x1293680, L_0x1293a20, L_0x1293d30, L_0x1294040; +LS_0x1294e90_0_4 .concat8 [ 1 1 1 1], L_0x12943a0, L_0x12947d0, L_0x1294b00, L_0x1294a90; +L_0x1294e90 .concat8 [ 4 4 0 0], LS_0x1294e90_0_0, LS_0x1294e90_0_4; +L_0x1295250 .part L_0x1292db0, 7, 1; +L_0x1295440 .part v0x127a150_0, 7, 1; +S_0xf084c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0xe50eb0 .param/l "i" 0 4 54, +C4<00>; +L_0x1293680/d .functor AND 1, L_0x1293790, L_0x1293980, C4<1>, C4<1>; +L_0x1293680 .delay 1 (30000,30000,30000) L_0x1293680/d; +v0xe2c3e0_0 .net *"_s0", 0 0, L_0x1293790; 1 drivers +v0xe2c4c0_0 .net *"_s1", 0 0, L_0x1293980; 1 drivers +S_0xe077b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0xde2c90 .param/l "i" 0 4 54, +C4<01>; +L_0x1293a20/d .functor AND 1, L_0x1293ae0, L_0x1293c40, C4<1>, C4<1>; +L_0x1293a20 .delay 1 (30000,30000,30000) L_0x1293a20/d; +v0xde2d50_0 .net *"_s0", 0 0, L_0x1293ae0; 1 drivers +v0xd2b6f0_0 .net *"_s1", 0 0, L_0x1293c40; 1 drivers +S_0xd06c30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0xd2b840 .param/l "i" 0 4 54, +C4<010>; +L_0x1293d30/d .functor AND 1, L_0x1293df0, L_0x1293f50, C4<1>, C4<1>; +L_0x1293d30 .delay 1 (30000,30000,30000) L_0x1293d30/d; +v0xce2110_0 .net *"_s0", 0 0, L_0x1293df0; 1 drivers +v0xce21f0_0 .net *"_s1", 0 0, L_0x1293f50; 1 drivers +S_0xc2aa70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0xc05f40 .param/l "i" 0 4 54, +C4<011>; +L_0x1294040/d .functor AND 1, L_0x1294100, L_0x1294260, C4<1>, C4<1>; +L_0x1294040 .delay 1 (30000,30000,30000) L_0x1294040/d; +v0xc06000_0 .net *"_s0", 0 0, L_0x1294100; 1 drivers +v0xbe1360_0 .net *"_s1", 0 0, L_0x1294260; 1 drivers +S_0xc05410 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0xf9aa20 .param/l "i" 0 4 54, +C4<0100>; +L_0x12943a0/d .functor AND 1, L_0x1294460, L_0x12946d0, C4<1>, C4<1>; +L_0x12943a0 .delay 1 (30000,30000,30000) L_0x12943a0/d; +v0xf9aae0_0 .net *"_s0", 0 0, L_0x1294460; 1 drivers +v0xe74d90_0 .net *"_s1", 0 0, L_0x12946d0; 1 drivers +S_0x1009380 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0x1009540 .param/l "i" 0 4 54, +C4<0101>; +L_0x12947d0/d .functor AND 1, L_0x1294840, L_0x12949a0, C4<1>, C4<1>; +L_0x12947d0 .delay 1 (30000,30000,30000) L_0x12947d0/d; +v0x1009600_0 .net *"_s0", 0 0, L_0x1294840; 1 drivers +v0xe74e70_0 .net *"_s1", 0 0, L_0x12949a0; 1 drivers +S_0x8e5a30 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0x8e5c40 .param/l "i" 0 4 54, +C4<0110>; +L_0x1294b00/d .functor AND 1, L_0x1294bc0, L_0x1294d20, C4<1>, C4<1>; +L_0x1294b00 .delay 1 (30000,30000,30000) L_0x1294b00/d; +v0x8e5d00_0 .net *"_s0", 0 0, L_0x1294bc0; 1 drivers +v0x8df800_0 .net *"_s1", 0 0, L_0x1294d20; 1 drivers +S_0x8df8e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xf2cff0; + .timescale -9 -12; +P_0x8dfaf0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1294a90/d .functor AND 1, L_0x1295250, L_0x1295440, C4<1>, C4<1>; +L_0x1294a90 .delay 1 (30000,30000,30000) L_0x1294a90/d; +v0x8d11a0_0 .net *"_s0", 0 0, L_0x1295250; 1 drivers +v0x8d1280_0 .net *"_s1", 0 0, L_0x1295440; 1 drivers +S_0x8cfad0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xf51a80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1296e90/d .functor OR 1, L_0x1296f50, L_0x1297100, C4<0>, C4<0>; +L_0x1296e90 .delay 1 (30000,30000,30000) L_0x1296e90/d; +v0x8cc6c0_0 .net *"_s10", 0 0, L_0x1296f50; 1 drivers +v0x8dbad0_0 .net *"_s12", 0 0, L_0x1297100; 1 drivers +v0x8dbbb0_0 .net "in", 7 0, L_0x1294e90; alias, 1 drivers +v0x8dbc50_0 .net "ors", 1 0, L_0x1296cb0; 1 drivers +v0x8dbd10_0 .net "out", 0 0, L_0x1296e90; alias, 1 drivers +L_0x1296080 .part L_0x1294e90, 0, 4; +L_0x1296cb0 .concat8 [ 1 1 0 0], L_0x1295d70, L_0x12969a0; +L_0x1296df0 .part L_0x1294e90, 4, 4; +L_0x1296f50 .part L_0x1296cb0, 0, 1; +L_0x1297100 .part L_0x1296cb0, 1, 1; +S_0x8d43c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x8cfad0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1295530/d .functor OR 1, L_0x12955f0, L_0x1295750, C4<0>, C4<0>; +L_0x1295530 .delay 1 (30000,30000,30000) L_0x1295530/d; +L_0x1295980/d .functor OR 1, L_0x1295a90, L_0x1295bf0, C4<0>, C4<0>; +L_0x1295980 .delay 1 (30000,30000,30000) L_0x1295980/d; +L_0x1295d70/d .functor OR 1, L_0x1295de0, L_0x1295f90, C4<0>, C4<0>; +L_0x1295d70 .delay 1 (30000,30000,30000) L_0x1295d70/d; +v0x8d45b0_0 .net *"_s0", 0 0, L_0x1295530; 1 drivers +v0x8d46b0_0 .net *"_s10", 0 0, L_0x1295a90; 1 drivers +v0x8d9fe0_0 .net *"_s12", 0 0, L_0x1295bf0; 1 drivers +v0x8da0c0_0 .net *"_s14", 0 0, L_0x1295de0; 1 drivers +v0x8da1a0_0 .net *"_s16", 0 0, L_0x1295f90; 1 drivers +v0x8da2d0_0 .net *"_s3", 0 0, L_0x12955f0; 1 drivers +v0x8d8e10_0 .net *"_s5", 0 0, L_0x1295750; 1 drivers +v0x8d8ed0_0 .net *"_s6", 0 0, L_0x1295980; 1 drivers +v0x8d8fb0_0 .net "in", 3 0, L_0x1296080; 1 drivers +v0x8d9090_0 .net "ors", 1 0, L_0x1295890; 1 drivers +v0x8ddc30_0 .net "out", 0 0, L_0x1295d70; 1 drivers +L_0x12955f0 .part L_0x1296080, 0, 1; +L_0x1295750 .part L_0x1296080, 1, 1; +L_0x1295890 .concat8 [ 1 1 0 0], L_0x1295530, L_0x1295980; +L_0x1295a90 .part L_0x1296080, 2, 1; +L_0x1295bf0 .part L_0x1296080, 3, 1; +L_0x1295de0 .part L_0x1295890, 0, 1; +L_0x1295f90 .part L_0x1295890, 1, 1; +S_0x8ddd50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x8cfad0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12961b0/d .functor OR 1, L_0x1296220, L_0x1296380, C4<0>, C4<0>; +L_0x12961b0 .delay 1 (30000,30000,30000) L_0x12961b0/d; +L_0x12965b0/d .functor OR 1, L_0x12966c0, L_0x1296820, C4<0>, C4<0>; +L_0x12965b0 .delay 1 (30000,30000,30000) L_0x12965b0/d; +L_0x12969a0/d .functor OR 1, L_0x1296a10, L_0x1296bc0, C4<0>, C4<0>; +L_0x12969a0 .delay 1 (30000,30000,30000) L_0x12969a0/d; +v0x8ddf10_0 .net *"_s0", 0 0, L_0x12961b0; 1 drivers +v0x8d5ea0_0 .net *"_s10", 0 0, L_0x12966c0; 1 drivers +v0x8d5f80_0 .net *"_s12", 0 0, L_0x1296820; 1 drivers +v0x8d6040_0 .net *"_s14", 0 0, L_0x1296a10; 1 drivers +v0x8d6120_0 .net *"_s16", 0 0, L_0x1296bc0; 1 drivers +v0x8ca710_0 .net *"_s3", 0 0, L_0x1296220; 1 drivers +v0x8ca7f0_0 .net *"_s5", 0 0, L_0x1296380; 1 drivers +v0x8ca8d0_0 .net *"_s6", 0 0, L_0x12965b0; 1 drivers +v0x8ca9b0_0 .net "in", 3 0, L_0x1296df0; 1 drivers +v0x8cc4c0_0 .net "ors", 1 0, L_0x12964c0; 1 drivers +v0x8cc5a0_0 .net "out", 0 0, L_0x12969a0; 1 drivers +L_0x1296220 .part L_0x1296df0, 0, 1; +L_0x1296380 .part L_0x1296df0, 1, 1; +L_0x12964c0 .concat8 [ 1 1 0 0], L_0x12961b0, L_0x12965b0; +L_0x12966c0 .part L_0x1296df0, 2, 1; +L_0x1296820 .part L_0x1296df0, 3, 1; +L_0x1296a10 .part L_0x12964c0, 0, 1; +L_0x1296bc0 .part L_0x12964c0, 1, 1; +S_0x8d7970 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0xd07350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1291b60/d .functor XNOR 1, L_0x129ad30, L_0x129af20, C4<0>, C4<0>; +L_0x1291b60 .delay 1 (20000,20000,20000) L_0x1291b60/d; +L_0x1291ce0/d .functor AND 1, L_0x129ad30, L_0x12908f0, C4<1>, C4<1>; +L_0x1291ce0 .delay 1 (30000,30000,30000) L_0x1291ce0/d; +L_0x1291e40/d .functor AND 1, L_0x1291b60, L_0x129b050, C4<1>, C4<1>; +L_0x1291e40 .delay 1 (30000,30000,30000) L_0x1291e40/d; +L_0x1291f50/d .functor OR 1, L_0x1291e40, L_0x1291ce0, C4<0>, C4<0>; +L_0x1291f50 .delay 1 (30000,30000,30000) L_0x1291f50/d; +v0x8d7be0_0 .net "a", 0 0, L_0x129ad30; alias, 1 drivers +v0x1053e60_0 .net "a_", 0 0, L_0x1290790; alias, 1 drivers +v0x1053f20_0 .net "b", 0 0, L_0x129af20; alias, 1 drivers +v0x1054010_0 .net "b_", 0 0, L_0x12908f0; alias, 1 drivers +v0x10540b0_0 .net "carryin", 0 0, L_0x129b050; alias, 1 drivers +v0x10541f0_0 .net "eq", 0 0, L_0x1291b60; 1 drivers +v0x1054ea0_0 .net "lt", 0 0, L_0x1291ce0; 1 drivers +v0x1054f40_0 .net "out", 0 0, L_0x1291f50; 1 drivers +v0x1054fe0_0 .net "w0", 0 0, L_0x1291e40; 1 drivers +S_0x1055110 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xd07350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1291740/d .functor OR 1, L_0x1291240, L_0x10562a0, C4<0>, C4<0>; +L_0x1291740 .delay 1 (30000,30000,30000) L_0x1291740/d; +v0x1055e30_0 .net "a", 0 0, L_0x129ad30; alias, 1 drivers +v0x1055f80_0 .net "b", 0 0, L_0x12908f0; alias, 1 drivers +v0x1056040_0 .net "c1", 0 0, L_0x1291240; 1 drivers +v0x10560e0_0 .net "c2", 0 0, L_0x10562a0; 1 drivers +v0x10561b0_0 .net "carryin", 0 0, L_0x129b050; alias, 1 drivers +v0x1056330_0 .net "carryout", 0 0, L_0x1291740; 1 drivers +v0x10563d0_0 .net "s1", 0 0, L_0x1291180; 1 drivers +v0x1056470_0 .net "sum", 0 0, L_0x12913a0; 1 drivers +S_0x1055290 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1055110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1291180/d .functor XOR 1, L_0x129ad30, L_0x12908f0, C4<0>, C4<0>; +L_0x1291180 .delay 1 (30000,30000,30000) L_0x1291180/d; +L_0x1291240/d .functor AND 1, L_0x129ad30, L_0x12908f0, C4<1>, C4<1>; +L_0x1291240 .delay 1 (30000,30000,30000) L_0x1291240/d; +v0x10554b0_0 .net "a", 0 0, L_0x129ad30; alias, 1 drivers +v0x1055550_0 .net "b", 0 0, L_0x12908f0; alias, 1 drivers +v0x1055640_0 .net "carryout", 0 0, L_0x1291240; alias, 1 drivers +v0x1055710_0 .net "sum", 0 0, L_0x1291180; alias, 1 drivers +S_0x1055840 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1055110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12913a0/d .functor XOR 1, L_0x1291180, L_0x129b050, C4<0>, C4<0>; +L_0x12913a0 .delay 1 (30000,30000,30000) L_0x12913a0/d; +L_0x10562a0/d .functor AND 1, L_0x1291180, L_0x129b050, C4<1>, C4<1>; +L_0x10562a0 .delay 1 (30000,30000,30000) L_0x10562a0/d; +v0x1055aa0_0 .net "a", 0 0, L_0x1291180; alias, 1 drivers +v0x1055b70_0 .net "b", 0 0, L_0x129b050; alias, 1 drivers +v0x1055c10_0 .net "carryout", 0 0, L_0x10562a0; alias, 1 drivers +v0x1055ce0_0 .net "sum", 0 0, L_0x12913a0; alias, 1 drivers +S_0x1058500 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0xd2ba90; + .timescale -9 -12; +L_0x2ac432883ac8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883b10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1287cb0/d .functor OR 1, L_0x2ac432883ac8, L_0x2ac432883b10, C4<0>, C4<0>; +L_0x1287cb0 .delay 1 (30000,30000,30000) L_0x1287cb0/d; +v0x10586f0_0 .net/2u *"_s0", 0 0, L_0x2ac432883ac8; 1 drivers +v0x10587d0_0 .net/2u *"_s2", 0 0, L_0x2ac432883b10; 1 drivers +S_0x10588b0 .scope generate, "alu_slices[3]" "alu_slices[3]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1058ac0 .param/l "i" 0 3 39, +C4<011>; +S_0x1058b80 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x10588b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x129b190/d .functor NOT 1, L_0x12a5620, C4<0>, C4<0>, C4<0>; +L_0x129b190 .delay 1 (10000,10000,10000) L_0x129b190/d; +L_0x129b2a0/d .functor NOT 1, L_0x12a5780, C4<0>, C4<0>, C4<0>; +L_0x129b2a0 .delay 1 (10000,10000,10000) L_0x129b2a0/d; +L_0x129c2f0/d .functor XOR 1, L_0x12a5620, L_0x12a5780, C4<0>, C4<0>; +L_0x129c2f0 .delay 1 (30000,30000,30000) L_0x129c2f0/d; +L_0x2ac432883b58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883ba0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129c3b0/d .functor OR 1, L_0x2ac432883b58, L_0x2ac432883ba0, C4<0>, C4<0>; +L_0x129c3b0 .delay 1 (30000,30000,30000) L_0x129c3b0/d; +L_0x2ac432883be8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883c30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129cb50/d .functor OR 1, L_0x2ac432883be8, L_0x2ac432883c30, C4<0>, C4<0>; +L_0x129cb50 .delay 1 (30000,30000,30000) L_0x129cb50/d; +L_0x129cd50/d .functor AND 1, L_0x12a5620, L_0x12a5780, C4<1>, C4<1>; +L_0x129cd50 .delay 1 (30000,30000,30000) L_0x129cd50/d; +L_0x2ac432883c78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883cc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129ce10/d .functor OR 1, L_0x2ac432883c78, L_0x2ac432883cc0, C4<0>, C4<0>; +L_0x129ce10 .delay 1 (30000,30000,30000) L_0x129ce10/d; +L_0x129d010/d .functor NAND 1, L_0x12a5620, L_0x12a5780, C4<1>, C4<1>; +L_0x129d010 .delay 1 (20000,20000,20000) L_0x129d010/d; +L_0x2ac432883d08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883d50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129d120/d .functor OR 1, L_0x2ac432883d08, L_0x2ac432883d50, C4<0>, C4<0>; +L_0x129d120 .delay 1 (30000,30000,30000) L_0x129d120/d; +L_0x129d2d0/d .functor NOR 1, L_0x12a5620, L_0x12a5780, C4<0>, C4<0>; +L_0x129d2d0 .delay 1 (20000,20000,20000) L_0x129d2d0/d; +L_0x2ac432883d98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883de0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129b750/d .functor OR 1, L_0x2ac432883d98, L_0x2ac432883de0, C4<0>, C4<0>; +L_0x129b750 .delay 1 (30000,30000,30000) L_0x129b750/d; +L_0x129d930/d .functor OR 1, L_0x12a5620, L_0x12a5780, C4<0>, C4<0>; +L_0x129d930 .delay 1 (30000,30000,30000) L_0x129d930/d; +L_0x2ac432883e28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883e70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129de20/d .functor OR 1, L_0x2ac432883e28, L_0x2ac432883e70, C4<0>, C4<0>; +L_0x129de20 .delay 1 (30000,30000,30000) L_0x129de20/d; +L_0x12a5520/d .functor NOT 1, L_0x12a1780, C4<0>, C4<0>, C4<0>; +L_0x12a5520 .delay 1 (10000,10000,10000) L_0x12a5520/d; +v0x10673b0_0 .net "A", 0 0, L_0x12a5620; 1 drivers +v0x1067470_0 .net "A_", 0 0, L_0x129b190; 1 drivers +v0x1067530_0 .net "B", 0 0, L_0x12a5780; 1 drivers +v0x1067600_0 .net "B_", 0 0, L_0x129b2a0; 1 drivers +v0x10676a0_0 .net *"_s11", 0 0, L_0x129c3b0; 1 drivers +v0x1067790_0 .net/2s *"_s13", 0 0, L_0x2ac432883b58; 1 drivers +v0x1067850_0 .net/2s *"_s15", 0 0, L_0x2ac432883ba0; 1 drivers +v0x1067930_0 .net *"_s19", 0 0, L_0x129cb50; 1 drivers +v0x1067a10_0 .net/2s *"_s21", 0 0, L_0x2ac432883be8; 1 drivers +v0x1067b80_0 .net/2s *"_s23", 0 0, L_0x2ac432883c30; 1 drivers +v0x1067c60_0 .net *"_s25", 0 0, L_0x129cd50; 1 drivers +v0x1067d40_0 .net *"_s28", 0 0, L_0x129ce10; 1 drivers +v0x1067e20_0 .net/2s *"_s30", 0 0, L_0x2ac432883c78; 1 drivers +v0x1067f00_0 .net/2s *"_s32", 0 0, L_0x2ac432883cc0; 1 drivers +v0x1067fe0_0 .net *"_s34", 0 0, L_0x129d010; 1 drivers +v0x10680c0_0 .net *"_s37", 0 0, L_0x129d120; 1 drivers +v0x10681a0_0 .net/2s *"_s39", 0 0, L_0x2ac432883d08; 1 drivers +v0x1068350_0 .net/2s *"_s41", 0 0, L_0x2ac432883d50; 1 drivers +v0x10683f0_0 .net *"_s43", 0 0, L_0x129d2d0; 1 drivers +v0x10684d0_0 .net *"_s46", 0 0, L_0x129b750; 1 drivers +v0x10685b0_0 .net/2s *"_s48", 0 0, L_0x2ac432883d98; 1 drivers +v0x1068690_0 .net/2s *"_s50", 0 0, L_0x2ac432883de0; 1 drivers +v0x1068770_0 .net *"_s52", 0 0, L_0x129d930; 1 drivers +v0x1068850_0 .net *"_s56", 0 0, L_0x129de20; 1 drivers +v0x1068930_0 .net/2s *"_s59", 0 0, L_0x2ac432883e28; 1 drivers +v0x1068a10_0 .net/2s *"_s61", 0 0, L_0x2ac432883e70; 1 drivers +v0x1068af0_0 .net *"_s8", 0 0, L_0x129c2f0; 1 drivers +v0x1068bd0_0 .net "carryin", 0 0, L_0x12a5820; 1 drivers +v0x1068c70_0 .net "carryout", 0 0, L_0x12a51c0; 1 drivers +v0x1068d10_0 .net "carryouts", 7 0, L_0x129dab0; 1 drivers +v0x1068e20_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1068ee0_0 .net "result", 0 0, L_0x12a1780; 1 drivers +v0x1068fd0_0 .net "results", 7 0, L_0x129d700; 1 drivers +v0x10682b0_0 .net "zero", 0 0, L_0x12a5520; 1 drivers +LS_0x129d700_0_0 .concat8 [ 1 1 1 1], L_0x129b7c0, L_0x129bdf0, L_0x129c2f0, L_0x129cb50; +LS_0x129d700_0_4 .concat8 [ 1 1 1 1], L_0x129cd50, L_0x129d010, L_0x129d2d0, L_0x129d930; +L_0x129d700 .concat8 [ 4 4 0 0], LS_0x129d700_0_0, LS_0x129d700_0_4; +LS_0x129dab0_0_0 .concat8 [ 1 1 1 1], L_0x129ba70, L_0x129c190, L_0x129c3b0, L_0x129c9a0; +LS_0x129dab0_0_4 .concat8 [ 1 1 1 1], L_0x129ce10, L_0x129d120, L_0x129b750, L_0x129de20; +L_0x129dab0 .concat8 [ 4 4 0 0], LS_0x129dab0_0_0, LS_0x129dab0_0_4; +S_0x1058e00 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1058b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x129ba70/d .functor OR 1, L_0x129b550, L_0x129b910, C4<0>, C4<0>; +L_0x129ba70 .delay 1 (30000,30000,30000) L_0x129ba70/d; +v0x1059c30_0 .net "a", 0 0, L_0x12a5620; alias, 1 drivers +v0x1059cf0_0 .net "b", 0 0, L_0x12a5780; alias, 1 drivers +v0x1059dc0_0 .net "c1", 0 0, L_0x129b550; 1 drivers +v0x1059ec0_0 .net "c2", 0 0, L_0x129b910; 1 drivers +v0x1059f90_0 .net "carryin", 0 0, L_0x12a5820; alias, 1 drivers +v0x105a080_0 .net "carryout", 0 0, L_0x129ba70; 1 drivers +v0x105a120_0 .net "s1", 0 0, L_0x129b490; 1 drivers +v0x105a210_0 .net "sum", 0 0, L_0x129b7c0; 1 drivers +S_0x1059070 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1058e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x129b490/d .functor XOR 1, L_0x12a5620, L_0x12a5780, C4<0>, C4<0>; +L_0x129b490 .delay 1 (30000,30000,30000) L_0x129b490/d; +L_0x129b550/d .functor AND 1, L_0x12a5620, L_0x12a5780, C4<1>, C4<1>; +L_0x129b550 .delay 1 (30000,30000,30000) L_0x129b550/d; +v0x10592d0_0 .net "a", 0 0, L_0x12a5620; alias, 1 drivers +v0x10593b0_0 .net "b", 0 0, L_0x12a5780; alias, 1 drivers +v0x1059470_0 .net "carryout", 0 0, L_0x129b550; alias, 1 drivers +v0x1059510_0 .net "sum", 0 0, L_0x129b490; alias, 1 drivers +S_0x1059650 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1058e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x129b7c0/d .functor XOR 1, L_0x129b490, L_0x12a5820, C4<0>, C4<0>; +L_0x129b7c0 .delay 1 (30000,30000,30000) L_0x129b7c0/d; +L_0x129b910/d .functor AND 1, L_0x129b490, L_0x12a5820, C4<1>, C4<1>; +L_0x129b910 .delay 1 (30000,30000,30000) L_0x129b910/d; +v0x10598b0_0 .net "a", 0 0, L_0x129b490; alias, 1 drivers +v0x1059950_0 .net "b", 0 0, L_0x12a5820; alias, 1 drivers +v0x10599f0_0 .net "carryout", 0 0, L_0x129b910; alias, 1 drivers +v0x1059ac0_0 .net "sum", 0 0, L_0x129b7c0; alias, 1 drivers +S_0x105a2e0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1058b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x105f6d0_0 .net "ands", 7 0, L_0x12a31c0; 1 drivers +v0x105f7e0_0 .net "in", 7 0, L_0x129dab0; alias, 1 drivers +v0x105f8a0_0 .net "out", 0 0, L_0x12a51c0; alias, 1 drivers +v0x105f970_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x105a500 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x105a2e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x105cc30_0 .net "A", 7 0, L_0x129dab0; alias, 1 drivers +v0x105cd30_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x105cdf0_0 .net *"_s0", 0 0, L_0x12a1ae0; 1 drivers +v0x105ceb0_0 .net *"_s12", 0 0, L_0x12a2450; 1 drivers +v0x105cf90_0 .net *"_s16", 0 0, L_0x12a27b0; 1 drivers +v0x105d0c0_0 .net *"_s20", 0 0, L_0x12a2b80; 1 drivers +v0x105d1a0_0 .net *"_s24", 0 0, L_0x12a2eb0; 1 drivers +v0x105d280_0 .net *"_s28", 0 0, L_0x12a2e40; 1 drivers +v0x105d360_0 .net *"_s4", 0 0, L_0x12a1e30; 1 drivers +v0x105d4d0_0 .net *"_s8", 0 0, L_0x12a2140; 1 drivers +v0x105d5b0_0 .net "out", 7 0, L_0x12a31c0; alias, 1 drivers +L_0x12a1ba0 .part L_0x129dab0, 0, 1; +L_0x12a1d90 .part v0x127a150_0, 0, 1; +L_0x12a1ef0 .part L_0x129dab0, 1, 1; +L_0x12a2050 .part v0x127a150_0, 1, 1; +L_0x12a2200 .part L_0x129dab0, 2, 1; +L_0x12a2360 .part v0x127a150_0, 2, 1; +L_0x12a2510 .part L_0x129dab0, 3, 1; +L_0x12a2670 .part v0x127a150_0, 3, 1; +L_0x12a2870 .part L_0x129dab0, 4, 1; +L_0x12a2ae0 .part v0x127a150_0, 4, 1; +L_0x12a2bf0 .part L_0x129dab0, 5, 1; +L_0x12a2d50 .part v0x127a150_0, 5, 1; +L_0x12a2f70 .part L_0x129dab0, 6, 1; +L_0x12a30d0 .part v0x127a150_0, 6, 1; +LS_0x12a31c0_0_0 .concat8 [ 1 1 1 1], L_0x12a1ae0, L_0x12a1e30, L_0x12a2140, L_0x12a2450; +LS_0x12a31c0_0_4 .concat8 [ 1 1 1 1], L_0x12a27b0, L_0x12a2b80, L_0x12a2eb0, L_0x12a2e40; +L_0x12a31c0 .concat8 [ 4 4 0 0], LS_0x12a31c0_0_0, LS_0x12a31c0_0_4; +L_0x12a3580 .part L_0x129dab0, 7, 1; +L_0x12a3770 .part v0x127a150_0, 7, 1; +S_0x105a760 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105a970 .param/l "i" 0 4 54, +C4<00>; +L_0x12a1ae0/d .functor AND 1, L_0x12a1ba0, L_0x12a1d90, C4<1>, C4<1>; +L_0x12a1ae0 .delay 1 (30000,30000,30000) L_0x12a1ae0/d; +v0x105aa50_0 .net *"_s0", 0 0, L_0x12a1ba0; 1 drivers +v0x105ab30_0 .net *"_s1", 0 0, L_0x12a1d90; 1 drivers +S_0x105ac10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105ae20 .param/l "i" 0 4 54, +C4<01>; +L_0x12a1e30/d .functor AND 1, L_0x12a1ef0, L_0x12a2050, C4<1>, C4<1>; +L_0x12a1e30 .delay 1 (30000,30000,30000) L_0x12a1e30/d; +v0x105aee0_0 .net *"_s0", 0 0, L_0x12a1ef0; 1 drivers +v0x105afc0_0 .net *"_s1", 0 0, L_0x12a2050; 1 drivers +S_0x105b0a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105b2b0 .param/l "i" 0 4 54, +C4<010>; +L_0x12a2140/d .functor AND 1, L_0x12a2200, L_0x12a2360, C4<1>, C4<1>; +L_0x12a2140 .delay 1 (30000,30000,30000) L_0x12a2140/d; +v0x105b350_0 .net *"_s0", 0 0, L_0x12a2200; 1 drivers +v0x105b430_0 .net *"_s1", 0 0, L_0x12a2360; 1 drivers +S_0x105b510 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105b720 .param/l "i" 0 4 54, +C4<011>; +L_0x12a2450/d .functor AND 1, L_0x12a2510, L_0x12a2670, C4<1>, C4<1>; +L_0x12a2450 .delay 1 (30000,30000,30000) L_0x12a2450/d; +v0x105b7e0_0 .net *"_s0", 0 0, L_0x12a2510; 1 drivers +v0x105b8c0_0 .net *"_s1", 0 0, L_0x12a2670; 1 drivers +S_0x105b9a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105bc00 .param/l "i" 0 4 54, +C4<0100>; +L_0x12a27b0/d .functor AND 1, L_0x12a2870, L_0x12a2ae0, C4<1>, C4<1>; +L_0x12a27b0 .delay 1 (30000,30000,30000) L_0x12a27b0/d; +v0x105bcc0_0 .net *"_s0", 0 0, L_0x12a2870; 1 drivers +v0x105bda0_0 .net *"_s1", 0 0, L_0x12a2ae0; 1 drivers +S_0x105be80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105c090 .param/l "i" 0 4 54, +C4<0101>; +L_0x12a2b80/d .functor AND 1, L_0x12a2bf0, L_0x12a2d50, C4<1>, C4<1>; +L_0x12a2b80 .delay 1 (30000,30000,30000) L_0x12a2b80/d; +v0x105c150_0 .net *"_s0", 0 0, L_0x12a2bf0; 1 drivers +v0x105c230_0 .net *"_s1", 0 0, L_0x12a2d50; 1 drivers +S_0x105c310 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105c520 .param/l "i" 0 4 54, +C4<0110>; +L_0x12a2eb0/d .functor AND 1, L_0x12a2f70, L_0x12a30d0, C4<1>, C4<1>; +L_0x12a2eb0 .delay 1 (30000,30000,30000) L_0x12a2eb0/d; +v0x105c5e0_0 .net *"_s0", 0 0, L_0x12a2f70; 1 drivers +v0x105c6c0_0 .net *"_s1", 0 0, L_0x12a30d0; 1 drivers +S_0x105c7a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x105a500; + .timescale -9 -12; +P_0x105c9b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12a2e40/d .functor AND 1, L_0x12a3580, L_0x12a3770, C4<1>, C4<1>; +L_0x12a2e40 .delay 1 (30000,30000,30000) L_0x12a2e40/d; +v0x105ca70_0 .net *"_s0", 0 0, L_0x12a3580; 1 drivers +v0x105cb50_0 .net *"_s1", 0 0, L_0x12a3770; 1 drivers +S_0x105d710 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x105a2e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12a51c0/d .functor OR 1, L_0x12a5280, L_0x12a5430, C4<0>, C4<0>; +L_0x12a51c0 .delay 1 (30000,30000,30000) L_0x12a51c0/d; +v0x105f260_0 .net *"_s10", 0 0, L_0x12a5280; 1 drivers +v0x105f340_0 .net *"_s12", 0 0, L_0x12a5430; 1 drivers +v0x105f420_0 .net "in", 7 0, L_0x12a31c0; alias, 1 drivers +v0x105f4f0_0 .net "ors", 1 0, L_0x12a4fe0; 1 drivers +v0x105f5b0_0 .net "out", 0 0, L_0x12a51c0; alias, 1 drivers +L_0x12a43b0 .part L_0x12a31c0, 0, 4; +L_0x12a4fe0 .concat8 [ 1 1 0 0], L_0x12a40a0, L_0x12a4cd0; +L_0x12a5120 .part L_0x12a31c0, 4, 4; +L_0x12a5280 .part L_0x12a4fe0, 0, 1; +L_0x12a5430 .part L_0x12a4fe0, 1, 1; +S_0x105d8d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x105d710; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12a3860/d .functor OR 1, L_0x12a3920, L_0x12a3a80, C4<0>, C4<0>; +L_0x12a3860 .delay 1 (30000,30000,30000) L_0x12a3860/d; +L_0x12a3cb0/d .functor OR 1, L_0x12a3dc0, L_0x12a3f20, C4<0>, C4<0>; +L_0x12a3cb0 .delay 1 (30000,30000,30000) L_0x12a3cb0/d; +L_0x12a40a0/d .functor OR 1, L_0x12a4110, L_0x12a42c0, C4<0>, C4<0>; +L_0x12a40a0 .delay 1 (30000,30000,30000) L_0x12a40a0/d; +v0x105db20_0 .net *"_s0", 0 0, L_0x12a3860; 1 drivers +v0x105dc20_0 .net *"_s10", 0 0, L_0x12a3dc0; 1 drivers +v0x105dd00_0 .net *"_s12", 0 0, L_0x12a3f20; 1 drivers +v0x105ddc0_0 .net *"_s14", 0 0, L_0x12a4110; 1 drivers +v0x105dea0_0 .net *"_s16", 0 0, L_0x12a42c0; 1 drivers +v0x105dfd0_0 .net *"_s3", 0 0, L_0x12a3920; 1 drivers +v0x105e0b0_0 .net *"_s5", 0 0, L_0x12a3a80; 1 drivers +v0x105e190_0 .net *"_s6", 0 0, L_0x12a3cb0; 1 drivers +v0x105e270_0 .net "in", 3 0, L_0x12a43b0; 1 drivers +v0x105e3e0_0 .net "ors", 1 0, L_0x12a3bc0; 1 drivers +v0x105e4c0_0 .net "out", 0 0, L_0x12a40a0; 1 drivers +L_0x12a3920 .part L_0x12a43b0, 0, 1; +L_0x12a3a80 .part L_0x12a43b0, 1, 1; +L_0x12a3bc0 .concat8 [ 1 1 0 0], L_0x12a3860, L_0x12a3cb0; +L_0x12a3dc0 .part L_0x12a43b0, 2, 1; +L_0x12a3f20 .part L_0x12a43b0, 3, 1; +L_0x12a4110 .part L_0x12a3bc0, 0, 1; +L_0x12a42c0 .part L_0x12a3bc0, 1, 1; +S_0x105e5e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x105d710; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12a44e0/d .functor OR 1, L_0x12a4550, L_0x12a46b0, C4<0>, C4<0>; +L_0x12a44e0 .delay 1 (30000,30000,30000) L_0x12a44e0/d; +L_0x12a48e0/d .functor OR 1, L_0x12a49f0, L_0x12a4b50, C4<0>, C4<0>; +L_0x12a48e0 .delay 1 (30000,30000,30000) L_0x12a48e0/d; +L_0x12a4cd0/d .functor OR 1, L_0x12a4d40, L_0x12a4ef0, C4<0>, C4<0>; +L_0x12a4cd0 .delay 1 (30000,30000,30000) L_0x12a4cd0/d; +v0x105e7a0_0 .net *"_s0", 0 0, L_0x12a44e0; 1 drivers +v0x105e8a0_0 .net *"_s10", 0 0, L_0x12a49f0; 1 drivers +v0x105e980_0 .net *"_s12", 0 0, L_0x12a4b50; 1 drivers +v0x105ea40_0 .net *"_s14", 0 0, L_0x12a4d40; 1 drivers +v0x105eb20_0 .net *"_s16", 0 0, L_0x12a4ef0; 1 drivers +v0x105ec50_0 .net *"_s3", 0 0, L_0x12a4550; 1 drivers +v0x105ed30_0 .net *"_s5", 0 0, L_0x12a46b0; 1 drivers +v0x105ee10_0 .net *"_s6", 0 0, L_0x12a48e0; 1 drivers +v0x105eef0_0 .net "in", 3 0, L_0x12a5120; 1 drivers +v0x105f060_0 .net "ors", 1 0, L_0x12a47f0; 1 drivers +v0x105f140_0 .net "out", 0 0, L_0x12a4cd0; 1 drivers +L_0x12a4550 .part L_0x12a5120, 0, 1; +L_0x12a46b0 .part L_0x12a5120, 1, 1; +L_0x12a47f0 .concat8 [ 1 1 0 0], L_0x12a44e0, L_0x12a48e0; +L_0x12a49f0 .part L_0x12a5120, 2, 1; +L_0x12a4b50 .part L_0x12a5120, 3, 1; +L_0x12a4d40 .part L_0x12a47f0, 0, 1; +L_0x12a4ef0 .part L_0x12a47f0, 1, 1; +S_0x105fc20 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1058b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1064f80_0 .net "ands", 7 0, L_0x129f780; 1 drivers +v0x1065090_0 .net "in", 7 0, L_0x129d700; alias, 1 drivers +v0x1065150_0 .net "out", 0 0, L_0x12a1780; alias, 1 drivers +v0x1065220_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x105fda0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x105fc20; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10624e0_0 .net "A", 7 0, L_0x129d700; alias, 1 drivers +v0x10625e0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10626a0_0 .net *"_s0", 0 0, L_0x129dfd0; 1 drivers +v0x1062760_0 .net *"_s12", 0 0, L_0x129e990; 1 drivers +v0x1062840_0 .net *"_s16", 0 0, L_0x129ecf0; 1 drivers +v0x1062970_0 .net *"_s20", 0 0, L_0x129f0c0; 1 drivers +v0x1062a50_0 .net *"_s24", 0 0, L_0x129f3f0; 1 drivers +v0x1062b30_0 .net *"_s28", 0 0, L_0x129f380; 1 drivers +v0x1062c10_0 .net *"_s4", 0 0, L_0x129e370; 1 drivers +v0x1062d80_0 .net *"_s8", 0 0, L_0x129e680; 1 drivers +v0x1062e60_0 .net "out", 7 0, L_0x129f780; alias, 1 drivers +L_0x129e0e0 .part L_0x129d700, 0, 1; +L_0x129e2d0 .part v0x127a150_0, 0, 1; +L_0x129e430 .part L_0x129d700, 1, 1; +L_0x129e590 .part v0x127a150_0, 1, 1; +L_0x129e740 .part L_0x129d700, 2, 1; +L_0x129e8a0 .part v0x127a150_0, 2, 1; +L_0x129ea50 .part L_0x129d700, 3, 1; +L_0x129ebb0 .part v0x127a150_0, 3, 1; +L_0x129edb0 .part L_0x129d700, 4, 1; +L_0x129f020 .part v0x127a150_0, 4, 1; +L_0x129f130 .part L_0x129d700, 5, 1; +L_0x129f290 .part v0x127a150_0, 5, 1; +L_0x129f4b0 .part L_0x129d700, 6, 1; +L_0x129f610 .part v0x127a150_0, 6, 1; +LS_0x129f780_0_0 .concat8 [ 1 1 1 1], L_0x129dfd0, L_0x129e370, L_0x129e680, L_0x129e990; +LS_0x129f780_0_4 .concat8 [ 1 1 1 1], L_0x129ecf0, L_0x129f0c0, L_0x129f3f0, L_0x129f380; +L_0x129f780 .concat8 [ 4 4 0 0], LS_0x129f780_0_0, LS_0x129f780_0_4; +L_0x129fb40 .part L_0x129d700, 7, 1; +L_0x129fd30 .part v0x127a150_0, 7, 1; +S_0x105ffe0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x10601f0 .param/l "i" 0 4 54, +C4<00>; +L_0x129dfd0/d .functor AND 1, L_0x129e0e0, L_0x129e2d0, C4<1>, C4<1>; +L_0x129dfd0 .delay 1 (30000,30000,30000) L_0x129dfd0/d; +v0x10602d0_0 .net *"_s0", 0 0, L_0x129e0e0; 1 drivers +v0x10603b0_0 .net *"_s1", 0 0, L_0x129e2d0; 1 drivers +S_0x1060490 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x10606a0 .param/l "i" 0 4 54, +C4<01>; +L_0x129e370/d .functor AND 1, L_0x129e430, L_0x129e590, C4<1>, C4<1>; +L_0x129e370 .delay 1 (30000,30000,30000) L_0x129e370/d; +v0x1060760_0 .net *"_s0", 0 0, L_0x129e430; 1 drivers +v0x1060840_0 .net *"_s1", 0 0, L_0x129e590; 1 drivers +S_0x1060920 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x1060b60 .param/l "i" 0 4 54, +C4<010>; +L_0x129e680/d .functor AND 1, L_0x129e740, L_0x129e8a0, C4<1>, C4<1>; +L_0x129e680 .delay 1 (30000,30000,30000) L_0x129e680/d; +v0x1060c00_0 .net *"_s0", 0 0, L_0x129e740; 1 drivers +v0x1060ce0_0 .net *"_s1", 0 0, L_0x129e8a0; 1 drivers +S_0x1060dc0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x1060fd0 .param/l "i" 0 4 54, +C4<011>; +L_0x129e990/d .functor AND 1, L_0x129ea50, L_0x129ebb0, C4<1>, C4<1>; +L_0x129e990 .delay 1 (30000,30000,30000) L_0x129e990/d; +v0x1061090_0 .net *"_s0", 0 0, L_0x129ea50; 1 drivers +v0x1061170_0 .net *"_s1", 0 0, L_0x129ebb0; 1 drivers +S_0x1061250 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x10614b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x129ecf0/d .functor AND 1, L_0x129edb0, L_0x129f020, C4<1>, C4<1>; +L_0x129ecf0 .delay 1 (30000,30000,30000) L_0x129ecf0/d; +v0x1061570_0 .net *"_s0", 0 0, L_0x129edb0; 1 drivers +v0x1061650_0 .net *"_s1", 0 0, L_0x129f020; 1 drivers +S_0x1061730 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x1061940 .param/l "i" 0 4 54, +C4<0101>; +L_0x129f0c0/d .functor AND 1, L_0x129f130, L_0x129f290, C4<1>, C4<1>; +L_0x129f0c0 .delay 1 (30000,30000,30000) L_0x129f0c0/d; +v0x1061a00_0 .net *"_s0", 0 0, L_0x129f130; 1 drivers +v0x1061ae0_0 .net *"_s1", 0 0, L_0x129f290; 1 drivers +S_0x1061bc0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x1061dd0 .param/l "i" 0 4 54, +C4<0110>; +L_0x129f3f0/d .functor AND 1, L_0x129f4b0, L_0x129f610, C4<1>, C4<1>; +L_0x129f3f0 .delay 1 (30000,30000,30000) L_0x129f3f0/d; +v0x1061e90_0 .net *"_s0", 0 0, L_0x129f4b0; 1 drivers +v0x1061f70_0 .net *"_s1", 0 0, L_0x129f610; 1 drivers +S_0x1062050 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x105fda0; + .timescale -9 -12; +P_0x1062260 .param/l "i" 0 4 54, +C4<0111>; +L_0x129f380/d .functor AND 1, L_0x129fb40, L_0x129fd30, C4<1>, C4<1>; +L_0x129f380 .delay 1 (30000,30000,30000) L_0x129f380/d; +v0x1062320_0 .net *"_s0", 0 0, L_0x129fb40; 1 drivers +v0x1062400_0 .net *"_s1", 0 0, L_0x129fd30; 1 drivers +S_0x1062fc0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x105fc20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12a1780/d .functor OR 1, L_0x12a1840, L_0x12a19f0, C4<0>, C4<0>; +L_0x12a1780 .delay 1 (30000,30000,30000) L_0x12a1780/d; +v0x1064b10_0 .net *"_s10", 0 0, L_0x12a1840; 1 drivers +v0x1064bf0_0 .net *"_s12", 0 0, L_0x12a19f0; 1 drivers +v0x1064cd0_0 .net "in", 7 0, L_0x129f780; alias, 1 drivers +v0x1064da0_0 .net "ors", 1 0, L_0x12a15a0; 1 drivers +v0x1064e60_0 .net "out", 0 0, L_0x12a1780; alias, 1 drivers +L_0x12a0970 .part L_0x129f780, 0, 4; +L_0x12a15a0 .concat8 [ 1 1 0 0], L_0x12a0660, L_0x12a1290; +L_0x12a16e0 .part L_0x129f780, 4, 4; +L_0x12a1840 .part L_0x12a15a0, 0, 1; +L_0x12a19f0 .part L_0x12a15a0, 1, 1; +S_0x1063180 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1062fc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x129fe20/d .functor OR 1, L_0x129fee0, L_0x12a0040, C4<0>, C4<0>; +L_0x129fe20 .delay 1 (30000,30000,30000) L_0x129fe20/d; +L_0x12a0270/d .functor OR 1, L_0x12a0380, L_0x12a04e0, C4<0>, C4<0>; +L_0x12a0270 .delay 1 (30000,30000,30000) L_0x12a0270/d; +L_0x12a0660/d .functor OR 1, L_0x12a06d0, L_0x12a0880, C4<0>, C4<0>; +L_0x12a0660 .delay 1 (30000,30000,30000) L_0x12a0660/d; +v0x10633d0_0 .net *"_s0", 0 0, L_0x129fe20; 1 drivers +v0x10634d0_0 .net *"_s10", 0 0, L_0x12a0380; 1 drivers +v0x10635b0_0 .net *"_s12", 0 0, L_0x12a04e0; 1 drivers +v0x1063670_0 .net *"_s14", 0 0, L_0x12a06d0; 1 drivers +v0x1063750_0 .net *"_s16", 0 0, L_0x12a0880; 1 drivers +v0x1063880_0 .net *"_s3", 0 0, L_0x129fee0; 1 drivers +v0x1063960_0 .net *"_s5", 0 0, L_0x12a0040; 1 drivers +v0x1063a40_0 .net *"_s6", 0 0, L_0x12a0270; 1 drivers +v0x1063b20_0 .net "in", 3 0, L_0x12a0970; 1 drivers +v0x1063c90_0 .net "ors", 1 0, L_0x12a0180; 1 drivers +v0x1063d70_0 .net "out", 0 0, L_0x12a0660; 1 drivers +L_0x129fee0 .part L_0x12a0970, 0, 1; +L_0x12a0040 .part L_0x12a0970, 1, 1; +L_0x12a0180 .concat8 [ 1 1 0 0], L_0x129fe20, L_0x12a0270; +L_0x12a0380 .part L_0x12a0970, 2, 1; +L_0x12a04e0 .part L_0x12a0970, 3, 1; +L_0x12a06d0 .part L_0x12a0180, 0, 1; +L_0x12a0880 .part L_0x12a0180, 1, 1; +S_0x1063e90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1062fc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12a0aa0/d .functor OR 1, L_0x12a0b10, L_0x12a0c70, C4<0>, C4<0>; +L_0x12a0aa0 .delay 1 (30000,30000,30000) L_0x12a0aa0/d; +L_0x12a0ea0/d .functor OR 1, L_0x12a0fb0, L_0x12a1110, C4<0>, C4<0>; +L_0x12a0ea0 .delay 1 (30000,30000,30000) L_0x12a0ea0/d; +L_0x12a1290/d .functor OR 1, L_0x12a1300, L_0x12a14b0, C4<0>, C4<0>; +L_0x12a1290 .delay 1 (30000,30000,30000) L_0x12a1290/d; +v0x1064050_0 .net *"_s0", 0 0, L_0x12a0aa0; 1 drivers +v0x1064150_0 .net *"_s10", 0 0, L_0x12a0fb0; 1 drivers +v0x1064230_0 .net *"_s12", 0 0, L_0x12a1110; 1 drivers +v0x10642f0_0 .net *"_s14", 0 0, L_0x12a1300; 1 drivers +v0x10643d0_0 .net *"_s16", 0 0, L_0x12a14b0; 1 drivers +v0x1064500_0 .net *"_s3", 0 0, L_0x12a0b10; 1 drivers +v0x10645e0_0 .net *"_s5", 0 0, L_0x12a0c70; 1 drivers +v0x10646c0_0 .net *"_s6", 0 0, L_0x12a0ea0; 1 drivers +v0x10647a0_0 .net "in", 3 0, L_0x12a16e0; 1 drivers +v0x1064910_0 .net "ors", 1 0, L_0x12a0db0; 1 drivers +v0x10649f0_0 .net "out", 0 0, L_0x12a1290; 1 drivers +L_0x12a0b10 .part L_0x12a16e0, 0, 1; +L_0x12a0c70 .part L_0x12a16e0, 1, 1; +L_0x12a0db0 .concat8 [ 1 1 0 0], L_0x12a0aa0, L_0x12a0ea0; +L_0x12a0fb0 .part L_0x12a16e0, 2, 1; +L_0x12a1110 .part L_0x12a16e0, 3, 1; +L_0x12a1300 .part L_0x12a0db0, 0, 1; +L_0x12a14b0 .part L_0x12a0db0, 1, 1; +S_0x1065300 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1058b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x129c5b0/d .functor XNOR 1, L_0x12a5620, L_0x12a5780, C4<0>, C4<0>; +L_0x129c5b0 .delay 1 (20000,20000,20000) L_0x129c5b0/d; +L_0x129c730/d .functor AND 1, L_0x12a5620, L_0x129b2a0, C4<1>, C4<1>; +L_0x129c730 .delay 1 (30000,30000,30000) L_0x129c730/d; +L_0x129c890/d .functor AND 1, L_0x129c5b0, L_0x12a5820, C4<1>, C4<1>; +L_0x129c890 .delay 1 (30000,30000,30000) L_0x129c890/d; +L_0x129c9a0/d .functor OR 1, L_0x129c890, L_0x129c730, C4<0>, C4<0>; +L_0x129c9a0 .delay 1 (30000,30000,30000) L_0x129c9a0/d; +v0x10655b0_0 .net "a", 0 0, L_0x12a5620; alias, 1 drivers +v0x10656a0_0 .net "a_", 0 0, L_0x129b190; alias, 1 drivers +v0x1065760_0 .net "b", 0 0, L_0x12a5780; alias, 1 drivers +v0x1065850_0 .net "b_", 0 0, L_0x129b2a0; alias, 1 drivers +v0x10658f0_0 .net "carryin", 0 0, L_0x12a5820; alias, 1 drivers +v0x1065a30_0 .net "eq", 0 0, L_0x129c5b0; 1 drivers +v0x1065af0_0 .net "lt", 0 0, L_0x129c730; 1 drivers +v0x1065bb0_0 .net "out", 0 0, L_0x129c9a0; 1 drivers +v0x1065c70_0 .net "w0", 0 0, L_0x129c890; 1 drivers +S_0x1065ec0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1058b80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x129c190/d .functor OR 1, L_0x129bc90, L_0x1067120, C4<0>, C4<0>; +L_0x129c190 .delay 1 (30000,30000,30000) L_0x129c190/d; +v0x1066cb0_0 .net "a", 0 0, L_0x12a5620; alias, 1 drivers +v0x1066e00_0 .net "b", 0 0, L_0x129b2a0; alias, 1 drivers +v0x1066ec0_0 .net "c1", 0 0, L_0x129bc90; 1 drivers +v0x1066f60_0 .net "c2", 0 0, L_0x1067120; 1 drivers +v0x1067030_0 .net "carryin", 0 0, L_0x12a5820; alias, 1 drivers +v0x10671b0_0 .net "carryout", 0 0, L_0x129c190; 1 drivers +v0x1067250_0 .net "s1", 0 0, L_0x129bbd0; 1 drivers +v0x10672f0_0 .net "sum", 0 0, L_0x129bdf0; 1 drivers +S_0x1066110 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1065ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x129bbd0/d .functor XOR 1, L_0x12a5620, L_0x129b2a0, C4<0>, C4<0>; +L_0x129bbd0 .delay 1 (30000,30000,30000) L_0x129bbd0/d; +L_0x129bc90/d .functor AND 1, L_0x12a5620, L_0x129b2a0, C4<1>, C4<1>; +L_0x129bc90 .delay 1 (30000,30000,30000) L_0x129bc90/d; +v0x1066370_0 .net "a", 0 0, L_0x12a5620; alias, 1 drivers +v0x1066430_0 .net "b", 0 0, L_0x129b2a0; alias, 1 drivers +v0x10664f0_0 .net "carryout", 0 0, L_0x129bc90; alias, 1 drivers +v0x1066590_0 .net "sum", 0 0, L_0x129bbd0; alias, 1 drivers +S_0x10666c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1065ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x129bdf0/d .functor XOR 1, L_0x129bbd0, L_0x12a5820, C4<0>, C4<0>; +L_0x129bdf0 .delay 1 (30000,30000,30000) L_0x129bdf0/d; +L_0x1067120/d .functor AND 1, L_0x129bbd0, L_0x12a5820, C4<1>, C4<1>; +L_0x1067120 .delay 1 (30000,30000,30000) L_0x1067120/d; +v0x1066920_0 .net "a", 0 0, L_0x129bbd0; alias, 1 drivers +v0x10669f0_0 .net "b", 0 0, L_0x12a5820; alias, 1 drivers +v0x1066a90_0 .net "carryout", 0 0, L_0x1067120; alias, 1 drivers +v0x1066b60_0 .net "sum", 0 0, L_0x129bdf0; alias, 1 drivers +S_0x1069380 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x10588b0; + .timescale -9 -12; +L_0x2ac432883eb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883f00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a56c0/d .functor OR 1, L_0x2ac432883eb8, L_0x2ac432883f00, C4<0>, C4<0>; +L_0x12a56c0 .delay 1 (30000,30000,30000) L_0x12a56c0/d; +v0x1069570_0 .net/2u *"_s0", 0 0, L_0x2ac432883eb8; 1 drivers +v0x1069650_0 .net/2u *"_s2", 0 0, L_0x2ac432883f00; 1 drivers +S_0x1069730 .scope generate, "alu_slices[4]" "alu_slices[4]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1069990 .param/l "i" 0 3 39, +C4<0100>; +S_0x1069a50 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1069730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12a59f0/d .functor NOT 1, L_0x12b0030, C4<0>, C4<0>, C4<0>; +L_0x12a59f0 .delay 1 (10000,10000,10000) L_0x12a59f0/d; +L_0x12a5b00/d .functor NOT 1, L_0x12b0190, C4<0>, C4<0>, C4<0>; +L_0x12a5b00 .delay 1 (10000,10000,10000) L_0x12a5b00/d; +L_0x12a6a90/d .functor XOR 1, L_0x12b0030, L_0x12b0190, C4<0>, C4<0>; +L_0x12a6a90 .delay 1 (30000,30000,30000) L_0x12a6a90/d; +L_0x2ac432883f48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432883f90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a6b50/d .functor OR 1, L_0x2ac432883f48, L_0x2ac432883f90, C4<0>, C4<0>; +L_0x12a6b50 .delay 1 (30000,30000,30000) L_0x12a6b50/d; +L_0x2ac432883fd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884020 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a72f0/d .functor OR 1, L_0x2ac432883fd8, L_0x2ac432884020, C4<0>, C4<0>; +L_0x12a72f0 .delay 1 (30000,30000,30000) L_0x12a72f0/d; +L_0x12a74f0/d .functor AND 1, L_0x12b0030, L_0x12b0190, C4<1>, C4<1>; +L_0x12a74f0 .delay 1 (30000,30000,30000) L_0x12a74f0/d; +L_0x2ac432884068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328840b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a75b0/d .functor OR 1, L_0x2ac432884068, L_0x2ac4328840b0, C4<0>, C4<0>; +L_0x12a75b0 .delay 1 (30000,30000,30000) L_0x12a75b0/d; +L_0x12a77b0/d .functor NAND 1, L_0x12b0030, L_0x12b0190, C4<1>, C4<1>; +L_0x12a77b0 .delay 1 (20000,20000,20000) L_0x12a77b0/d; +L_0x2ac4328840f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a78c0/d .functor OR 1, L_0x2ac4328840f8, L_0x2ac432884140, C4<0>, C4<0>; +L_0x12a78c0 .delay 1 (30000,30000,30000) L_0x12a78c0/d; +L_0x12a7a70/d .functor NOR 1, L_0x12b0030, L_0x12b0190, C4<0>, C4<0>; +L_0x12a7a70 .delay 1 (20000,20000,20000) L_0x12a7a70/d; +L_0x2ac432884188 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328841d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a7d40/d .functor OR 1, L_0x2ac432884188, L_0x2ac4328841d0, C4<0>, C4<0>; +L_0x12a7d40 .delay 1 (30000,30000,30000) L_0x12a7d40/d; +L_0x12a8140/d .functor OR 1, L_0x12b0030, L_0x12b0190, C4<0>, C4<0>; +L_0x12a8140 .delay 1 (30000,30000,30000) L_0x12a8140/d; +L_0x2ac432884218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884260 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a85e0/d .functor OR 1, L_0x2ac432884218, L_0x2ac432884260, C4<0>, C4<0>; +L_0x12a85e0 .delay 1 (30000,30000,30000) L_0x12a85e0/d; +L_0x12aff30/d .functor NOT 1, L_0x12ac190, C4<0>, C4<0>, C4<0>; +L_0x12aff30 .delay 1 (10000,10000,10000) L_0x12aff30/d; +v0x1078150_0 .net "A", 0 0, L_0x12b0030; 1 drivers +v0x1078210_0 .net "A_", 0 0, L_0x12a59f0; 1 drivers +v0x10782d0_0 .net "B", 0 0, L_0x12b0190; 1 drivers +v0x10783a0_0 .net "B_", 0 0, L_0x12a5b00; 1 drivers +v0x1078440_0 .net *"_s11", 0 0, L_0x12a6b50; 1 drivers +v0x1078530_0 .net/2s *"_s13", 0 0, L_0x2ac432883f48; 1 drivers +v0x10785f0_0 .net/2s *"_s15", 0 0, L_0x2ac432883f90; 1 drivers +v0x10786d0_0 .net *"_s19", 0 0, L_0x12a72f0; 1 drivers +v0x10787b0_0 .net/2s *"_s21", 0 0, L_0x2ac432883fd8; 1 drivers +v0x1078920_0 .net/2s *"_s23", 0 0, L_0x2ac432884020; 1 drivers +v0x1078a00_0 .net *"_s25", 0 0, L_0x12a74f0; 1 drivers +v0x1078ae0_0 .net *"_s28", 0 0, L_0x12a75b0; 1 drivers +v0x1078bc0_0 .net/2s *"_s30", 0 0, L_0x2ac432884068; 1 drivers +v0x1078ca0_0 .net/2s *"_s32", 0 0, L_0x2ac4328840b0; 1 drivers +v0x1078d80_0 .net *"_s34", 0 0, L_0x12a77b0; 1 drivers +v0x1078e60_0 .net *"_s37", 0 0, L_0x12a78c0; 1 drivers +v0x1078f40_0 .net/2s *"_s39", 0 0, L_0x2ac4328840f8; 1 drivers +v0x10790f0_0 .net/2s *"_s41", 0 0, L_0x2ac432884140; 1 drivers +v0x1079190_0 .net *"_s43", 0 0, L_0x12a7a70; 1 drivers +v0x1079270_0 .net *"_s46", 0 0, L_0x12a7d40; 1 drivers +v0x1079350_0 .net/2s *"_s48", 0 0, L_0x2ac432884188; 1 drivers +v0x1079430_0 .net/2s *"_s50", 0 0, L_0x2ac4328841d0; 1 drivers +v0x1079510_0 .net *"_s52", 0 0, L_0x12a8140; 1 drivers +v0x10795f0_0 .net *"_s56", 0 0, L_0x12a85e0; 1 drivers +v0x10796d0_0 .net/2s *"_s59", 0 0, L_0x2ac432884218; 1 drivers +v0x10797b0_0 .net/2s *"_s61", 0 0, L_0x2ac432884260; 1 drivers +v0x1079890_0 .net *"_s8", 0 0, L_0x12a6a90; 1 drivers +v0x1079970_0 .net "carryin", 0 0, L_0x12b02b0; 1 drivers +v0x1079a10_0 .net "carryout", 0 0, L_0x12afbd0; 1 drivers +v0x1079ab0_0 .net "carryouts", 7 0, L_0x12a8250; 1 drivers +v0x1079bc0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1079c80_0 .net "result", 0 0, L_0x12ac190; 1 drivers +v0x1079d70_0 .net "results", 7 0, L_0x12a7f10; 1 drivers +v0x1079050_0 .net "zero", 0 0, L_0x12aff30; 1 drivers +LS_0x12a7f10_0_0 .concat8 [ 1 1 1 1], L_0x1077b10, L_0x12a65e0, L_0x12a6a90, L_0x12a72f0; +LS_0x12a7f10_0_4 .concat8 [ 1 1 1 1], L_0x12a74f0, L_0x12a77b0, L_0x12a7a70, L_0x12a8140; +L_0x12a7f10 .concat8 [ 4 4 0 0], LS_0x12a7f10_0_0, LS_0x12a7f10_0_4; +LS_0x12a8250_0_0 .concat8 [ 1 1 1 1], L_0x12a6260, L_0x12a6930, L_0x12a6b50, L_0x12a7140; +LS_0x12a8250_0_4 .concat8 [ 1 1 1 1], L_0x12a75b0, L_0x12a78c0, L_0x12a7d40, L_0x12a85e0; +L_0x12a8250 .concat8 [ 4 4 0 0], LS_0x12a8250_0_0, LS_0x12a8250_0_4; +S_0x1069cd0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1069a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12a6260/d .functor OR 1, L_0x12a5db0, L_0x12a6100, C4<0>, C4<0>; +L_0x12a6260 .delay 1 (30000,30000,30000) L_0x12a6260/d; +v0x106aad0_0 .net "a", 0 0, L_0x12b0030; alias, 1 drivers +v0x106ab90_0 .net "b", 0 0, L_0x12b0190; alias, 1 drivers +v0x106ac60_0 .net "c1", 0 0, L_0x12a5db0; 1 drivers +v0x106ad60_0 .net "c2", 0 0, L_0x12a6100; 1 drivers +v0x106ae30_0 .net "carryin", 0 0, L_0x12b02b0; alias, 1 drivers +v0x106af20_0 .net "carryout", 0 0, L_0x12a6260; 1 drivers +v0x106afc0_0 .net "s1", 0 0, L_0x12a5cf0; 1 drivers +v0x106b0b0_0 .net "sum", 0 0, L_0x1077b10; 1 drivers +S_0x1069f40 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1069cd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12a5cf0/d .functor XOR 1, L_0x12b0030, L_0x12b0190, C4<0>, C4<0>; +L_0x12a5cf0 .delay 1 (30000,30000,30000) L_0x12a5cf0/d; +L_0x12a5db0/d .functor AND 1, L_0x12b0030, L_0x12b0190, C4<1>, C4<1>; +L_0x12a5db0 .delay 1 (30000,30000,30000) L_0x12a5db0/d; +v0x106a1a0_0 .net "a", 0 0, L_0x12b0030; alias, 1 drivers +v0x106a280_0 .net "b", 0 0, L_0x12b0190; alias, 1 drivers +v0x106a340_0 .net "carryout", 0 0, L_0x12a5db0; alias, 1 drivers +v0x106a3e0_0 .net "sum", 0 0, L_0x12a5cf0; alias, 1 drivers +S_0x106a520 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1069cd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1077b10/d .functor XOR 1, L_0x12a5cf0, L_0x12b02b0, C4<0>, C4<0>; +L_0x1077b10 .delay 1 (30000,30000,30000) L_0x1077b10/d; +L_0x12a6100/d .functor AND 1, L_0x12a5cf0, L_0x12b02b0, C4<1>, C4<1>; +L_0x12a6100 .delay 1 (30000,30000,30000) L_0x12a6100/d; +v0x106a780_0 .net "a", 0 0, L_0x12a5cf0; alias, 1 drivers +v0x106a820_0 .net "b", 0 0, L_0x12b02b0; alias, 1 drivers +v0x106a8c0_0 .net "carryout", 0 0, L_0x12a6100; alias, 1 drivers +v0x106a960_0 .net "sum", 0 0, L_0x1077b10; alias, 1 drivers +S_0x106b180 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1069a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1070570_0 .net "ands", 7 0, L_0x12adbd0; 1 drivers +v0x1070680_0 .net "in", 7 0, L_0x12a8250; alias, 1 drivers +v0x1070740_0 .net "out", 0 0, L_0x12afbd0; alias, 1 drivers +v0x1070810_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x106b3a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x106b180; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x106dad0_0 .net "A", 7 0, L_0x12a8250; alias, 1 drivers +v0x106dbd0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x106dc90_0 .net *"_s0", 0 0, L_0x12ac4f0; 1 drivers +v0x106dd50_0 .net *"_s12", 0 0, L_0x12ace60; 1 drivers +v0x106de30_0 .net *"_s16", 0 0, L_0x12ad1c0; 1 drivers +v0x106df60_0 .net *"_s20", 0 0, L_0x12ad590; 1 drivers +v0x106e040_0 .net *"_s24", 0 0, L_0x12ad8c0; 1 drivers +v0x106e120_0 .net *"_s28", 0 0, L_0x12ad850; 1 drivers +v0x106e200_0 .net *"_s4", 0 0, L_0x12ac840; 1 drivers +v0x106e370_0 .net *"_s8", 0 0, L_0x12acb50; 1 drivers +v0x106e450_0 .net "out", 7 0, L_0x12adbd0; alias, 1 drivers +L_0x12ac5b0 .part L_0x12a8250, 0, 1; +L_0x12ac7a0 .part v0x127a150_0, 0, 1; +L_0x12ac900 .part L_0x12a8250, 1, 1; +L_0x12aca60 .part v0x127a150_0, 1, 1; +L_0x12acc10 .part L_0x12a8250, 2, 1; +L_0x12acd70 .part v0x127a150_0, 2, 1; +L_0x12acf20 .part L_0x12a8250, 3, 1; +L_0x12ad080 .part v0x127a150_0, 3, 1; +L_0x12ad280 .part L_0x12a8250, 4, 1; +L_0x12ad4f0 .part v0x127a150_0, 4, 1; +L_0x12ad600 .part L_0x12a8250, 5, 1; +L_0x12ad760 .part v0x127a150_0, 5, 1; +L_0x12ad980 .part L_0x12a8250, 6, 1; +L_0x12adae0 .part v0x127a150_0, 6, 1; +LS_0x12adbd0_0_0 .concat8 [ 1 1 1 1], L_0x12ac4f0, L_0x12ac840, L_0x12acb50, L_0x12ace60; +LS_0x12adbd0_0_4 .concat8 [ 1 1 1 1], L_0x12ad1c0, L_0x12ad590, L_0x12ad8c0, L_0x12ad850; +L_0x12adbd0 .concat8 [ 4 4 0 0], LS_0x12adbd0_0_0, LS_0x12adbd0_0_4; +L_0x12adf90 .part L_0x12a8250, 7, 1; +L_0x12ae180 .part v0x127a150_0, 7, 1; +S_0x106b600 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106b810 .param/l "i" 0 4 54, +C4<00>; +L_0x12ac4f0/d .functor AND 1, L_0x12ac5b0, L_0x12ac7a0, C4<1>, C4<1>; +L_0x12ac4f0 .delay 1 (30000,30000,30000) L_0x12ac4f0/d; +v0x106b8f0_0 .net *"_s0", 0 0, L_0x12ac5b0; 1 drivers +v0x106b9d0_0 .net *"_s1", 0 0, L_0x12ac7a0; 1 drivers +S_0x106bab0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106bcc0 .param/l "i" 0 4 54, +C4<01>; +L_0x12ac840/d .functor AND 1, L_0x12ac900, L_0x12aca60, C4<1>, C4<1>; +L_0x12ac840 .delay 1 (30000,30000,30000) L_0x12ac840/d; +v0x106bd80_0 .net *"_s0", 0 0, L_0x12ac900; 1 drivers +v0x106be60_0 .net *"_s1", 0 0, L_0x12aca60; 1 drivers +S_0x106bf40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106c150 .param/l "i" 0 4 54, +C4<010>; +L_0x12acb50/d .functor AND 1, L_0x12acc10, L_0x12acd70, C4<1>, C4<1>; +L_0x12acb50 .delay 1 (30000,30000,30000) L_0x12acb50/d; +v0x106c1f0_0 .net *"_s0", 0 0, L_0x12acc10; 1 drivers +v0x106c2d0_0 .net *"_s1", 0 0, L_0x12acd70; 1 drivers +S_0x106c3b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106c5c0 .param/l "i" 0 4 54, +C4<011>; +L_0x12ace60/d .functor AND 1, L_0x12acf20, L_0x12ad080, C4<1>, C4<1>; +L_0x12ace60 .delay 1 (30000,30000,30000) L_0x12ace60/d; +v0x106c680_0 .net *"_s0", 0 0, L_0x12acf20; 1 drivers +v0x106c760_0 .net *"_s1", 0 0, L_0x12ad080; 1 drivers +S_0x106c840 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106caa0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12ad1c0/d .functor AND 1, L_0x12ad280, L_0x12ad4f0, C4<1>, C4<1>; +L_0x12ad1c0 .delay 1 (30000,30000,30000) L_0x12ad1c0/d; +v0x106cb60_0 .net *"_s0", 0 0, L_0x12ad280; 1 drivers +v0x106cc40_0 .net *"_s1", 0 0, L_0x12ad4f0; 1 drivers +S_0x106cd20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106cf30 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ad590/d .functor AND 1, L_0x12ad600, L_0x12ad760, C4<1>, C4<1>; +L_0x12ad590 .delay 1 (30000,30000,30000) L_0x12ad590/d; +v0x106cff0_0 .net *"_s0", 0 0, L_0x12ad600; 1 drivers +v0x106d0d0_0 .net *"_s1", 0 0, L_0x12ad760; 1 drivers +S_0x106d1b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106d3c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ad8c0/d .functor AND 1, L_0x12ad980, L_0x12adae0, C4<1>, C4<1>; +L_0x12ad8c0 .delay 1 (30000,30000,30000) L_0x12ad8c0/d; +v0x106d480_0 .net *"_s0", 0 0, L_0x12ad980; 1 drivers +v0x106d560_0 .net *"_s1", 0 0, L_0x12adae0; 1 drivers +S_0x106d640 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x106b3a0; + .timescale -9 -12; +P_0x106d850 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ad850/d .functor AND 1, L_0x12adf90, L_0x12ae180, C4<1>, C4<1>; +L_0x12ad850 .delay 1 (30000,30000,30000) L_0x12ad850/d; +v0x106d910_0 .net *"_s0", 0 0, L_0x12adf90; 1 drivers +v0x106d9f0_0 .net *"_s1", 0 0, L_0x12ae180; 1 drivers +S_0x106e5b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x106b180; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12afbd0/d .functor OR 1, L_0x12afc90, L_0x12afe40, C4<0>, C4<0>; +L_0x12afbd0 .delay 1 (30000,30000,30000) L_0x12afbd0/d; +v0x1070100_0 .net *"_s10", 0 0, L_0x12afc90; 1 drivers +v0x10701e0_0 .net *"_s12", 0 0, L_0x12afe40; 1 drivers +v0x10702c0_0 .net "in", 7 0, L_0x12adbd0; alias, 1 drivers +v0x1070390_0 .net "ors", 1 0, L_0x12af9f0; 1 drivers +v0x1070450_0 .net "out", 0 0, L_0x12afbd0; alias, 1 drivers +L_0x12aedc0 .part L_0x12adbd0, 0, 4; +L_0x12af9f0 .concat8 [ 1 1 0 0], L_0x12aeab0, L_0x12af6e0; +L_0x12afb30 .part L_0x12adbd0, 4, 4; +L_0x12afc90 .part L_0x12af9f0, 0, 1; +L_0x12afe40 .part L_0x12af9f0, 1, 1; +S_0x106e770 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x106e5b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12ae270/d .functor OR 1, L_0x12ae330, L_0x12ae490, C4<0>, C4<0>; +L_0x12ae270 .delay 1 (30000,30000,30000) L_0x12ae270/d; +L_0x12ae6c0/d .functor OR 1, L_0x12ae7d0, L_0x12ae930, C4<0>, C4<0>; +L_0x12ae6c0 .delay 1 (30000,30000,30000) L_0x12ae6c0/d; +L_0x12aeab0/d .functor OR 1, L_0x12aeb20, L_0x12aecd0, C4<0>, C4<0>; +L_0x12aeab0 .delay 1 (30000,30000,30000) L_0x12aeab0/d; +v0x106e9c0_0 .net *"_s0", 0 0, L_0x12ae270; 1 drivers +v0x106eac0_0 .net *"_s10", 0 0, L_0x12ae7d0; 1 drivers +v0x106eba0_0 .net *"_s12", 0 0, L_0x12ae930; 1 drivers +v0x106ec60_0 .net *"_s14", 0 0, L_0x12aeb20; 1 drivers +v0x106ed40_0 .net *"_s16", 0 0, L_0x12aecd0; 1 drivers +v0x106ee70_0 .net *"_s3", 0 0, L_0x12ae330; 1 drivers +v0x106ef50_0 .net *"_s5", 0 0, L_0x12ae490; 1 drivers +v0x106f030_0 .net *"_s6", 0 0, L_0x12ae6c0; 1 drivers +v0x106f110_0 .net "in", 3 0, L_0x12aedc0; 1 drivers +v0x106f280_0 .net "ors", 1 0, L_0x12ae5d0; 1 drivers +v0x106f360_0 .net "out", 0 0, L_0x12aeab0; 1 drivers +L_0x12ae330 .part L_0x12aedc0, 0, 1; +L_0x12ae490 .part L_0x12aedc0, 1, 1; +L_0x12ae5d0 .concat8 [ 1 1 0 0], L_0x12ae270, L_0x12ae6c0; +L_0x12ae7d0 .part L_0x12aedc0, 2, 1; +L_0x12ae930 .part L_0x12aedc0, 3, 1; +L_0x12aeb20 .part L_0x12ae5d0, 0, 1; +L_0x12aecd0 .part L_0x12ae5d0, 1, 1; +S_0x106f480 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x106e5b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12aeef0/d .functor OR 1, L_0x12aef60, L_0x12af0c0, C4<0>, C4<0>; +L_0x12aeef0 .delay 1 (30000,30000,30000) L_0x12aeef0/d; +L_0x12af2f0/d .functor OR 1, L_0x12af400, L_0x12af560, C4<0>, C4<0>; +L_0x12af2f0 .delay 1 (30000,30000,30000) L_0x12af2f0/d; +L_0x12af6e0/d .functor OR 1, L_0x12af750, L_0x12af900, C4<0>, C4<0>; +L_0x12af6e0 .delay 1 (30000,30000,30000) L_0x12af6e0/d; +v0x106f640_0 .net *"_s0", 0 0, L_0x12aeef0; 1 drivers +v0x106f740_0 .net *"_s10", 0 0, L_0x12af400; 1 drivers +v0x106f820_0 .net *"_s12", 0 0, L_0x12af560; 1 drivers +v0x106f8e0_0 .net *"_s14", 0 0, L_0x12af750; 1 drivers +v0x106f9c0_0 .net *"_s16", 0 0, L_0x12af900; 1 drivers +v0x106faf0_0 .net *"_s3", 0 0, L_0x12aef60; 1 drivers +v0x106fbd0_0 .net *"_s5", 0 0, L_0x12af0c0; 1 drivers +v0x106fcb0_0 .net *"_s6", 0 0, L_0x12af2f0; 1 drivers +v0x106fd90_0 .net "in", 3 0, L_0x12afb30; 1 drivers +v0x106ff00_0 .net "ors", 1 0, L_0x12af200; 1 drivers +v0x106ffe0_0 .net "out", 0 0, L_0x12af6e0; 1 drivers +L_0x12aef60 .part L_0x12afb30, 0, 1; +L_0x12af0c0 .part L_0x12afb30, 1, 1; +L_0x12af200 .concat8 [ 1 1 0 0], L_0x12aeef0, L_0x12af2f0; +L_0x12af400 .part L_0x12afb30, 2, 1; +L_0x12af560 .part L_0x12afb30, 3, 1; +L_0x12af750 .part L_0x12af200, 0, 1; +L_0x12af900 .part L_0x12af200, 1, 1; +S_0x10708f0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1069a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1075d20_0 .net "ands", 7 0, L_0x12aa190; 1 drivers +v0x1075e30_0 .net "in", 7 0, L_0x12a7f10; alias, 1 drivers +v0x1075ef0_0 .net "out", 0 0, L_0x12ac190; alias, 1 drivers +v0x1075fc0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1070b40 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10708f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1073280_0 .net "A", 7 0, L_0x12a7f10; alias, 1 drivers +v0x1073380_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1073440_0 .net *"_s0", 0 0, L_0x12a8790; 1 drivers +v0x1073500_0 .net *"_s12", 0 0, L_0x12a9340; 1 drivers +v0x10735e0_0 .net *"_s16", 0 0, L_0x12a96a0; 1 drivers +v0x1073710_0 .net *"_s20", 0 0, L_0x12a9ad0; 1 drivers +v0x10737f0_0 .net *"_s24", 0 0, L_0x12a9e00; 1 drivers +v0x10738d0_0 .net *"_s28", 0 0, L_0x12a9d90; 1 drivers +v0x10739b0_0 .net *"_s4", 0 0, L_0x1292a30; 1 drivers +v0x1073b20_0 .net *"_s8", 0 0, L_0x12a9030; 1 drivers +v0x1073c00_0 .net "out", 7 0, L_0x12aa190; alias, 1 drivers +L_0x1292990 .part L_0x12a7f10, 0, 1; +L_0x12a8cf0 .part v0x127a150_0, 0, 1; +L_0x12a8de0 .part L_0x12a7f10, 1, 1; +L_0x12a8f40 .part v0x127a150_0, 1, 1; +L_0x12a90f0 .part L_0x12a7f10, 2, 1; +L_0x12a9250 .part v0x127a150_0, 2, 1; +L_0x12a9400 .part L_0x12a7f10, 3, 1; +L_0x12a9560 .part v0x127a150_0, 3, 1; +L_0x12a9760 .part L_0x12a7f10, 4, 1; +L_0x12a99d0 .part v0x127a150_0, 4, 1; +L_0x12a9b40 .part L_0x12a7f10, 5, 1; +L_0x12a9ca0 .part v0x127a150_0, 5, 1; +L_0x12a9ec0 .part L_0x12a7f10, 6, 1; +L_0x12aa020 .part v0x127a150_0, 6, 1; +LS_0x12aa190_0_0 .concat8 [ 1 1 1 1], L_0x12a8790, L_0x1292a30, L_0x12a9030, L_0x12a9340; +LS_0x12aa190_0_4 .concat8 [ 1 1 1 1], L_0x12a96a0, L_0x12a9ad0, L_0x12a9e00, L_0x12a9d90; +L_0x12aa190 .concat8 [ 4 4 0 0], LS_0x12aa190_0_0, LS_0x12aa190_0_4; +L_0x12aa550 .part L_0x12a7f10, 7, 1; +L_0x12aa740 .part v0x127a150_0, 7, 1; +S_0x1070d80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1070f90 .param/l "i" 0 4 54, +C4<00>; +L_0x12a8790/d .functor AND 1, L_0x1292990, L_0x12a8cf0, C4<1>, C4<1>; +L_0x12a8790 .delay 1 (30000,30000,30000) L_0x12a8790/d; +v0x1071070_0 .net *"_s0", 0 0, L_0x1292990; 1 drivers +v0x1071150_0 .net *"_s1", 0 0, L_0x12a8cf0; 1 drivers +S_0x1071230 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1071440 .param/l "i" 0 4 54, +C4<01>; +L_0x1292a30/d .functor AND 1, L_0x12a8de0, L_0x12a8f40, C4<1>, C4<1>; +L_0x1292a30 .delay 1 (30000,30000,30000) L_0x1292a30/d; +v0x1071500_0 .net *"_s0", 0 0, L_0x12a8de0; 1 drivers +v0x10715e0_0 .net *"_s1", 0 0, L_0x12a8f40; 1 drivers +S_0x10716c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1071900 .param/l "i" 0 4 54, +C4<010>; +L_0x12a9030/d .functor AND 1, L_0x12a90f0, L_0x12a9250, C4<1>, C4<1>; +L_0x12a9030 .delay 1 (30000,30000,30000) L_0x12a9030/d; +v0x10719a0_0 .net *"_s0", 0 0, L_0x12a90f0; 1 drivers +v0x1071a80_0 .net *"_s1", 0 0, L_0x12a9250; 1 drivers +S_0x1071b60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1071d70 .param/l "i" 0 4 54, +C4<011>; +L_0x12a9340/d .functor AND 1, L_0x12a9400, L_0x12a9560, C4<1>, C4<1>; +L_0x12a9340 .delay 1 (30000,30000,30000) L_0x12a9340/d; +v0x1071e30_0 .net *"_s0", 0 0, L_0x12a9400; 1 drivers +v0x1071f10_0 .net *"_s1", 0 0, L_0x12a9560; 1 drivers +S_0x1071ff0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1072250 .param/l "i" 0 4 54, +C4<0100>; +L_0x12a96a0/d .functor AND 1, L_0x12a9760, L_0x12a99d0, C4<1>, C4<1>; +L_0x12a96a0 .delay 1 (30000,30000,30000) L_0x12a96a0/d; +v0x1072310_0 .net *"_s0", 0 0, L_0x12a9760; 1 drivers +v0x10723f0_0 .net *"_s1", 0 0, L_0x12a99d0; 1 drivers +S_0x10724d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x10726e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12a9ad0/d .functor AND 1, L_0x12a9b40, L_0x12a9ca0, C4<1>, C4<1>; +L_0x12a9ad0 .delay 1 (30000,30000,30000) L_0x12a9ad0/d; +v0x10727a0_0 .net *"_s0", 0 0, L_0x12a9b40; 1 drivers +v0x1072880_0 .net *"_s1", 0 0, L_0x12a9ca0; 1 drivers +S_0x1072960 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1072b70 .param/l "i" 0 4 54, +C4<0110>; +L_0x12a9e00/d .functor AND 1, L_0x12a9ec0, L_0x12aa020, C4<1>, C4<1>; +L_0x12a9e00 .delay 1 (30000,30000,30000) L_0x12a9e00/d; +v0x1072c30_0 .net *"_s0", 0 0, L_0x12a9ec0; 1 drivers +v0x1072d10_0 .net *"_s1", 0 0, L_0x12aa020; 1 drivers +S_0x1072df0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1070b40; + .timescale -9 -12; +P_0x1073000 .param/l "i" 0 4 54, +C4<0111>; +L_0x12a9d90/d .functor AND 1, L_0x12aa550, L_0x12aa740, C4<1>, C4<1>; +L_0x12a9d90 .delay 1 (30000,30000,30000) L_0x12a9d90/d; +v0x10730c0_0 .net *"_s0", 0 0, L_0x12aa550; 1 drivers +v0x10731a0_0 .net *"_s1", 0 0, L_0x12aa740; 1 drivers +S_0x1073d60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10708f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12ac190/d .functor OR 1, L_0x12ac250, L_0x12ac400, C4<0>, C4<0>; +L_0x12ac190 .delay 1 (30000,30000,30000) L_0x12ac190/d; +v0x10758b0_0 .net *"_s10", 0 0, L_0x12ac250; 1 drivers +v0x1075990_0 .net *"_s12", 0 0, L_0x12ac400; 1 drivers +v0x1075a70_0 .net "in", 7 0, L_0x12aa190; alias, 1 drivers +v0x1075b40_0 .net "ors", 1 0, L_0x12abfb0; 1 drivers +v0x1075c00_0 .net "out", 0 0, L_0x12ac190; alias, 1 drivers +L_0x12ab380 .part L_0x12aa190, 0, 4; +L_0x12abfb0 .concat8 [ 1 1 0 0], L_0x12ab070, L_0x12abca0; +L_0x12ac0f0 .part L_0x12aa190, 4, 4; +L_0x12ac250 .part L_0x12abfb0, 0, 1; +L_0x12ac400 .part L_0x12abfb0, 1, 1; +S_0x1073f20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1073d60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12aa830/d .functor OR 1, L_0x12aa8f0, L_0x12aaa50, C4<0>, C4<0>; +L_0x12aa830 .delay 1 (30000,30000,30000) L_0x12aa830/d; +L_0x12aac80/d .functor OR 1, L_0x12aad90, L_0x12aaef0, C4<0>, C4<0>; +L_0x12aac80 .delay 1 (30000,30000,30000) L_0x12aac80/d; +L_0x12ab070/d .functor OR 1, L_0x12ab0e0, L_0x12ab290, C4<0>, C4<0>; +L_0x12ab070 .delay 1 (30000,30000,30000) L_0x12ab070/d; +v0x1074170_0 .net *"_s0", 0 0, L_0x12aa830; 1 drivers +v0x1074270_0 .net *"_s10", 0 0, L_0x12aad90; 1 drivers +v0x1074350_0 .net *"_s12", 0 0, L_0x12aaef0; 1 drivers +v0x1074410_0 .net *"_s14", 0 0, L_0x12ab0e0; 1 drivers +v0x10744f0_0 .net *"_s16", 0 0, L_0x12ab290; 1 drivers +v0x1074620_0 .net *"_s3", 0 0, L_0x12aa8f0; 1 drivers +v0x1074700_0 .net *"_s5", 0 0, L_0x12aaa50; 1 drivers +v0x10747e0_0 .net *"_s6", 0 0, L_0x12aac80; 1 drivers +v0x10748c0_0 .net "in", 3 0, L_0x12ab380; 1 drivers +v0x1074a30_0 .net "ors", 1 0, L_0x12aab90; 1 drivers +v0x1074b10_0 .net "out", 0 0, L_0x12ab070; 1 drivers +L_0x12aa8f0 .part L_0x12ab380, 0, 1; +L_0x12aaa50 .part L_0x12ab380, 1, 1; +L_0x12aab90 .concat8 [ 1 1 0 0], L_0x12aa830, L_0x12aac80; +L_0x12aad90 .part L_0x12ab380, 2, 1; +L_0x12aaef0 .part L_0x12ab380, 3, 1; +L_0x12ab0e0 .part L_0x12aab90, 0, 1; +L_0x12ab290 .part L_0x12aab90, 1, 1; +S_0x1074c30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1073d60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12ab4b0/d .functor OR 1, L_0x12ab520, L_0x12ab680, C4<0>, C4<0>; +L_0x12ab4b0 .delay 1 (30000,30000,30000) L_0x12ab4b0/d; +L_0x12ab8b0/d .functor OR 1, L_0x12ab9c0, L_0x12abb20, C4<0>, C4<0>; +L_0x12ab8b0 .delay 1 (30000,30000,30000) L_0x12ab8b0/d; +L_0x12abca0/d .functor OR 1, L_0x12abd10, L_0x12abec0, C4<0>, C4<0>; +L_0x12abca0 .delay 1 (30000,30000,30000) L_0x12abca0/d; +v0x1074df0_0 .net *"_s0", 0 0, L_0x12ab4b0; 1 drivers +v0x1074ef0_0 .net *"_s10", 0 0, L_0x12ab9c0; 1 drivers +v0x1074fd0_0 .net *"_s12", 0 0, L_0x12abb20; 1 drivers +v0x1075090_0 .net *"_s14", 0 0, L_0x12abd10; 1 drivers +v0x1075170_0 .net *"_s16", 0 0, L_0x12abec0; 1 drivers +v0x10752a0_0 .net *"_s3", 0 0, L_0x12ab520; 1 drivers +v0x1075380_0 .net *"_s5", 0 0, L_0x12ab680; 1 drivers +v0x1075460_0 .net *"_s6", 0 0, L_0x12ab8b0; 1 drivers +v0x1075540_0 .net "in", 3 0, L_0x12ac0f0; 1 drivers +v0x10756b0_0 .net "ors", 1 0, L_0x12ab7c0; 1 drivers +v0x1075790_0 .net "out", 0 0, L_0x12abca0; 1 drivers +L_0x12ab520 .part L_0x12ac0f0, 0, 1; +L_0x12ab680 .part L_0x12ac0f0, 1, 1; +L_0x12ab7c0 .concat8 [ 1 1 0 0], L_0x12ab4b0, L_0x12ab8b0; +L_0x12ab9c0 .part L_0x12ac0f0, 2, 1; +L_0x12abb20 .part L_0x12ac0f0, 3, 1; +L_0x12abd10 .part L_0x12ab7c0, 0, 1; +L_0x12abec0 .part L_0x12ab7c0, 1, 1; +S_0x10760a0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1069a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12a6d50/d .functor XNOR 1, L_0x12b0030, L_0x12b0190, C4<0>, C4<0>; +L_0x12a6d50 .delay 1 (20000,20000,20000) L_0x12a6d50/d; +L_0x12a6ed0/d .functor AND 1, L_0x12b0030, L_0x12a5b00, C4<1>, C4<1>; +L_0x12a6ed0 .delay 1 (30000,30000,30000) L_0x12a6ed0/d; +L_0x12a7030/d .functor AND 1, L_0x12a6d50, L_0x12b02b0, C4<1>, C4<1>; +L_0x12a7030 .delay 1 (30000,30000,30000) L_0x12a7030/d; +L_0x12a7140/d .functor OR 1, L_0x12a7030, L_0x12a6ed0, C4<0>, C4<0>; +L_0x12a7140 .delay 1 (30000,30000,30000) L_0x12a7140/d; +v0x1076350_0 .net "a", 0 0, L_0x12b0030; alias, 1 drivers +v0x1076440_0 .net "a_", 0 0, L_0x12a59f0; alias, 1 drivers +v0x1076500_0 .net "b", 0 0, L_0x12b0190; alias, 1 drivers +v0x10765f0_0 .net "b_", 0 0, L_0x12a5b00; alias, 1 drivers +v0x1076690_0 .net "carryin", 0 0, L_0x12b02b0; alias, 1 drivers +v0x10767d0_0 .net "eq", 0 0, L_0x12a6d50; 1 drivers +v0x1076890_0 .net "lt", 0 0, L_0x12a6ed0; 1 drivers +v0x1076950_0 .net "out", 0 0, L_0x12a7140; 1 drivers +v0x1076a10_0 .net "w0", 0 0, L_0x12a7030; 1 drivers +S_0x1076c60 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1069a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12a6930/d .functor OR 1, L_0x12a6480, L_0x1077ec0, C4<0>, C4<0>; +L_0x12a6930 .delay 1 (30000,30000,30000) L_0x12a6930/d; +v0x1077a50_0 .net "a", 0 0, L_0x12b0030; alias, 1 drivers +v0x1077ba0_0 .net "b", 0 0, L_0x12a5b00; alias, 1 drivers +v0x1077c60_0 .net "c1", 0 0, L_0x12a6480; 1 drivers +v0x1077d00_0 .net "c2", 0 0, L_0x1077ec0; 1 drivers +v0x1077dd0_0 .net "carryin", 0 0, L_0x12b02b0; alias, 1 drivers +v0x1077f50_0 .net "carryout", 0 0, L_0x12a6930; 1 drivers +v0x1077ff0_0 .net "s1", 0 0, L_0x12a63c0; 1 drivers +v0x1078090_0 .net "sum", 0 0, L_0x12a65e0; 1 drivers +S_0x1076eb0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1076c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12a63c0/d .functor XOR 1, L_0x12b0030, L_0x12a5b00, C4<0>, C4<0>; +L_0x12a63c0 .delay 1 (30000,30000,30000) L_0x12a63c0/d; +L_0x12a6480/d .functor AND 1, L_0x12b0030, L_0x12a5b00, C4<1>, C4<1>; +L_0x12a6480 .delay 1 (30000,30000,30000) L_0x12a6480/d; +v0x1077110_0 .net "a", 0 0, L_0x12b0030; alias, 1 drivers +v0x10771d0_0 .net "b", 0 0, L_0x12a5b00; alias, 1 drivers +v0x1077290_0 .net "carryout", 0 0, L_0x12a6480; alias, 1 drivers +v0x1077330_0 .net "sum", 0 0, L_0x12a63c0; alias, 1 drivers +S_0x1077460 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1076c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12a65e0/d .functor XOR 1, L_0x12a63c0, L_0x12b02b0, C4<0>, C4<0>; +L_0x12a65e0 .delay 1 (30000,30000,30000) L_0x12a65e0/d; +L_0x1077ec0/d .functor AND 1, L_0x12a63c0, L_0x12b02b0, C4<1>, C4<1>; +L_0x1077ec0 .delay 1 (30000,30000,30000) L_0x1077ec0/d; +v0x10776c0_0 .net "a", 0 0, L_0x12a63c0; alias, 1 drivers +v0x1077790_0 .net "b", 0 0, L_0x12b02b0; alias, 1 drivers +v0x1077830_0 .net "carryout", 0 0, L_0x1077ec0; alias, 1 drivers +v0x1077900_0 .net "sum", 0 0, L_0x12a65e0; alias, 1 drivers +S_0x107a120 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1069730; + .timescale -9 -12; +L_0x2ac4328842a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328842f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129da40/d .functor OR 1, L_0x2ac4328842a8, L_0x2ac4328842f0, C4<0>, C4<0>; +L_0x129da40 .delay 1 (30000,30000,30000) L_0x129da40/d; +v0x107a310_0 .net/2u *"_s0", 0 0, L_0x2ac4328842a8; 1 drivers +v0x107a3f0_0 .net/2u *"_s2", 0 0, L_0x2ac4328842f0; 1 drivers +S_0x107a4d0 .scope generate, "alu_slices[5]" "alu_slices[5]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x107a6e0 .param/l "i" 0 3 39, +C4<0101>; +S_0x107a7a0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x107a4d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12a5fb0/d .functor NOT 1, L_0x12bb900, C4<0>, C4<0>, C4<0>; +L_0x12a5fb0 .delay 1 (10000,10000,10000) L_0x12a5fb0/d; +L_0x12b0500/d .functor NOT 1, L_0x12bb9a0, C4<0>, C4<0>, C4<0>; +L_0x12b0500 .delay 1 (10000,10000,10000) L_0x12b0500/d; +L_0x12b14b0/d .functor XOR 1, L_0x12bb900, L_0x12bb9a0, C4<0>, C4<0>; +L_0x12b14b0 .delay 1 (30000,30000,30000) L_0x12b14b0/d; +L_0x2ac432884338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884380 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b1570/d .functor OR 1, L_0x2ac432884338, L_0x2ac432884380, C4<0>, C4<0>; +L_0x12b1570 .delay 1 (30000,30000,30000) L_0x12b1570/d; +L_0x2ac4328843c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884410 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b1d10/d .functor OR 1, L_0x2ac4328843c8, L_0x2ac432884410, C4<0>, C4<0>; +L_0x12b1d10 .delay 1 (30000,30000,30000) L_0x12b1d10/d; +L_0x12b1f10/d .functor AND 1, L_0x12bb900, L_0x12bb9a0, C4<1>, C4<1>; +L_0x12b1f10 .delay 1 (30000,30000,30000) L_0x12b1f10/d; +L_0x2ac432884458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328844a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b1fd0/d .functor OR 1, L_0x2ac432884458, L_0x2ac4328844a0, C4<0>, C4<0>; +L_0x12b1fd0 .delay 1 (30000,30000,30000) L_0x12b1fd0/d; +L_0x12b21d0/d .functor NAND 1, L_0x12bb900, L_0x12bb9a0, C4<1>, C4<1>; +L_0x12b21d0 .delay 1 (20000,20000,20000) L_0x12b21d0/d; +L_0x2ac4328844e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884530 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b22e0/d .functor OR 1, L_0x2ac4328844e8, L_0x2ac432884530, C4<0>, C4<0>; +L_0x12b22e0 .delay 1 (30000,30000,30000) L_0x12b22e0/d; +L_0x12b2490/d .functor NOR 1, L_0x12bb900, L_0x12bb9a0, C4<0>, C4<0>; +L_0x12b2490 .delay 1 (20000,20000,20000) L_0x12b2490/d; +L_0x2ac432884578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328845c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b2760/d .functor OR 1, L_0x2ac432884578, L_0x2ac4328845c0, C4<0>, C4<0>; +L_0x12b2760 .delay 1 (30000,30000,30000) L_0x12b2760/d; +L_0x12b2b60/d .functor OR 1, L_0x12bb900, L_0x12bb9a0, C4<0>, C4<0>; +L_0x12b2b60 .delay 1 (30000,30000,30000) L_0x12b2b60/d; +L_0x2ac432884608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b3000/d .functor OR 1, L_0x2ac432884608, L_0x2ac432884650, C4<0>, C4<0>; +L_0x12b3000 .delay 1 (30000,30000,30000) L_0x12b3000/d; +L_0x12bb6a0/d .functor NOT 1, L_0x12b69c0, C4<0>, C4<0>, C4<0>; +L_0x12bb6a0 .delay 1 (10000,10000,10000) L_0x12bb6a0/d; +v0x1088ed0_0 .net "A", 0 0, L_0x12bb900; 1 drivers +v0x1088f90_0 .net "A_", 0 0, L_0x12a5fb0; 1 drivers +v0x1089050_0 .net "B", 0 0, L_0x12bb9a0; 1 drivers +v0x1089120_0 .net "B_", 0 0, L_0x12b0500; 1 drivers +v0x10891c0_0 .net *"_s11", 0 0, L_0x12b1570; 1 drivers +v0x10892b0_0 .net/2s *"_s13", 0 0, L_0x2ac432884338; 1 drivers +v0x1089370_0 .net/2s *"_s15", 0 0, L_0x2ac432884380; 1 drivers +v0x1089450_0 .net *"_s19", 0 0, L_0x12b1d10; 1 drivers +v0x1089530_0 .net/2s *"_s21", 0 0, L_0x2ac4328843c8; 1 drivers +v0x10896a0_0 .net/2s *"_s23", 0 0, L_0x2ac432884410; 1 drivers +v0x1089780_0 .net *"_s25", 0 0, L_0x12b1f10; 1 drivers +v0x1089860_0 .net *"_s28", 0 0, L_0x12b1fd0; 1 drivers +v0x1089940_0 .net/2s *"_s30", 0 0, L_0x2ac432884458; 1 drivers +v0x1089a20_0 .net/2s *"_s32", 0 0, L_0x2ac4328844a0; 1 drivers +v0x1089b00_0 .net *"_s34", 0 0, L_0x12b21d0; 1 drivers +v0x1089be0_0 .net *"_s37", 0 0, L_0x12b22e0; 1 drivers +v0x1089cc0_0 .net/2s *"_s39", 0 0, L_0x2ac4328844e8; 1 drivers +v0x1089e70_0 .net/2s *"_s41", 0 0, L_0x2ac432884530; 1 drivers +v0x1089f10_0 .net *"_s43", 0 0, L_0x12b2490; 1 drivers +v0x1089ff0_0 .net *"_s46", 0 0, L_0x12b2760; 1 drivers +v0x108a0d0_0 .net/2s *"_s48", 0 0, L_0x2ac432884578; 1 drivers +v0x108a1b0_0 .net/2s *"_s50", 0 0, L_0x2ac4328845c0; 1 drivers +v0x108a290_0 .net *"_s52", 0 0, L_0x12b2b60; 1 drivers +v0x108a370_0 .net *"_s56", 0 0, L_0x12b3000; 1 drivers +v0x108a450_0 .net/2s *"_s59", 0 0, L_0x2ac432884608; 1 drivers +v0x108a530_0 .net/2s *"_s61", 0 0, L_0x2ac432884650; 1 drivers +v0x108a610_0 .net *"_s8", 0 0, L_0x12b14b0; 1 drivers +v0x108a6f0_0 .net "carryin", 0 0, L_0x12bba40; 1 drivers +v0x108a790_0 .net "carryout", 0 0, L_0x12bb340; 1 drivers +v0x108a830_0 .net "carryouts", 7 0, L_0x12b2c70; 1 drivers +v0x108a940_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x108aa00_0 .net "result", 0 0, L_0x12b69c0; 1 drivers +v0x108aaf0_0 .net "results", 7 0, L_0x12b2930; 1 drivers +v0x1089dd0_0 .net "zero", 0 0, L_0x12bb6a0; 1 drivers +LS_0x12b2930_0_0 .concat8 [ 1 1 1 1], L_0x12b09d0, L_0x12b1000, L_0x12b14b0, L_0x12b1d10; +LS_0x12b2930_0_4 .concat8 [ 1 1 1 1], L_0x12b1f10, L_0x12b21d0, L_0x12b2490, L_0x12b2b60; +L_0x12b2930 .concat8 [ 4 4 0 0], LS_0x12b2930_0_0, LS_0x12b2930_0_4; +LS_0x12b2c70_0_0 .concat8 [ 1 1 1 1], L_0x12b0c80, L_0x12b1350, L_0x12b1570, L_0x12b1b60; +LS_0x12b2c70_0_4 .concat8 [ 1 1 1 1], L_0x12b1fd0, L_0x12b22e0, L_0x12b2760, L_0x12b3000; +L_0x12b2c70 .concat8 [ 4 4 0 0], LS_0x12b2c70_0_0, LS_0x12b2c70_0_4; +S_0x107aa20 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x107a7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12b0c80/d .functor OR 1, L_0x12b0760, L_0x12b0b20, C4<0>, C4<0>; +L_0x12b0c80 .delay 1 (30000,30000,30000) L_0x12b0c80/d; +v0x107b850_0 .net "a", 0 0, L_0x12bb900; alias, 1 drivers +v0x107b910_0 .net "b", 0 0, L_0x12bb9a0; alias, 1 drivers +v0x107b9e0_0 .net "c1", 0 0, L_0x12b0760; 1 drivers +v0x107bae0_0 .net "c2", 0 0, L_0x12b0b20; 1 drivers +v0x107bbb0_0 .net "carryin", 0 0, L_0x12bba40; alias, 1 drivers +v0x107bca0_0 .net "carryout", 0 0, L_0x12b0c80; 1 drivers +v0x107bd40_0 .net "s1", 0 0, L_0x12b06f0; 1 drivers +v0x107be30_0 .net "sum", 0 0, L_0x12b09d0; 1 drivers +S_0x107ac90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x107aa20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12b06f0/d .functor XOR 1, L_0x12bb900, L_0x12bb9a0, C4<0>, C4<0>; +L_0x12b06f0 .delay 1 (30000,30000,30000) L_0x12b06f0/d; +L_0x12b0760/d .functor AND 1, L_0x12bb900, L_0x12bb9a0, C4<1>, C4<1>; +L_0x12b0760 .delay 1 (30000,30000,30000) L_0x12b0760/d; +v0x107aef0_0 .net "a", 0 0, L_0x12bb900; alias, 1 drivers +v0x107afd0_0 .net "b", 0 0, L_0x12bb9a0; alias, 1 drivers +v0x107b090_0 .net "carryout", 0 0, L_0x12b0760; alias, 1 drivers +v0x107b130_0 .net "sum", 0 0, L_0x12b06f0; alias, 1 drivers +S_0x107b270 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x107aa20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12b09d0/d .functor XOR 1, L_0x12b06f0, L_0x12bba40, C4<0>, C4<0>; +L_0x12b09d0 .delay 1 (30000,30000,30000) L_0x12b09d0/d; +L_0x12b0b20/d .functor AND 1, L_0x12b06f0, L_0x12bba40, C4<1>, C4<1>; +L_0x12b0b20 .delay 1 (30000,30000,30000) L_0x12b0b20/d; +v0x107b4d0_0 .net "a", 0 0, L_0x12b06f0; alias, 1 drivers +v0x107b570_0 .net "b", 0 0, L_0x12bba40; alias, 1 drivers +v0x107b610_0 .net "carryout", 0 0, L_0x12b0b20; alias, 1 drivers +v0x107b6e0_0 .net "sum", 0 0, L_0x12b09d0; alias, 1 drivers +S_0x107bf00 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x107a7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10812f0_0 .net "ands", 7 0, L_0x12b8400; 1 drivers +v0x1081400_0 .net "in", 7 0, L_0x12b2c70; alias, 1 drivers +v0x10814c0_0 .net "out", 0 0, L_0x12bb340; alias, 1 drivers +v0x1081590_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x107c120 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x107bf00; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x107e850_0 .net "A", 7 0, L_0x12b2c70; alias, 1 drivers +v0x107e950_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x107ea10_0 .net *"_s0", 0 0, L_0x12b6d20; 1 drivers +v0x107ead0_0 .net *"_s12", 0 0, L_0x12b7690; 1 drivers +v0x107ebb0_0 .net *"_s16", 0 0, L_0x12b79f0; 1 drivers +v0x107ece0_0 .net *"_s20", 0 0, L_0x12b7dc0; 1 drivers +v0x107edc0_0 .net *"_s24", 0 0, L_0x12b80f0; 1 drivers +v0x107eea0_0 .net *"_s28", 0 0, L_0x12b8080; 1 drivers +v0x107ef80_0 .net *"_s4", 0 0, L_0x12b7070; 1 drivers +v0x107f0f0_0 .net *"_s8", 0 0, L_0x12b7380; 1 drivers +v0x107f1d0_0 .net "out", 7 0, L_0x12b8400; alias, 1 drivers +L_0x12b6de0 .part L_0x12b2c70, 0, 1; +L_0x12b6fd0 .part v0x127a150_0, 0, 1; +L_0x12b7130 .part L_0x12b2c70, 1, 1; +L_0x12b7290 .part v0x127a150_0, 1, 1; +L_0x12b7440 .part L_0x12b2c70, 2, 1; +L_0x12b75a0 .part v0x127a150_0, 2, 1; +L_0x12b7750 .part L_0x12b2c70, 3, 1; +L_0x12b78b0 .part v0x127a150_0, 3, 1; +L_0x12b7ab0 .part L_0x12b2c70, 4, 1; +L_0x12b7d20 .part v0x127a150_0, 4, 1; +L_0x12b7e30 .part L_0x12b2c70, 5, 1; +L_0x12b7f90 .part v0x127a150_0, 5, 1; +L_0x12b81b0 .part L_0x12b2c70, 6, 1; +L_0x12b8310 .part v0x127a150_0, 6, 1; +LS_0x12b8400_0_0 .concat8 [ 1 1 1 1], L_0x12b6d20, L_0x12b7070, L_0x12b7380, L_0x12b7690; +LS_0x12b8400_0_4 .concat8 [ 1 1 1 1], L_0x12b79f0, L_0x12b7dc0, L_0x12b80f0, L_0x12b8080; +L_0x12b8400 .concat8 [ 4 4 0 0], LS_0x12b8400_0_0, LS_0x12b8400_0_4; +L_0x12b87c0 .part L_0x12b2c70, 7, 1; +L_0x12b89b0 .part v0x127a150_0, 7, 1; +S_0x107c380 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107c590 .param/l "i" 0 4 54, +C4<00>; +L_0x12b6d20/d .functor AND 1, L_0x12b6de0, L_0x12b6fd0, C4<1>, C4<1>; +L_0x12b6d20 .delay 1 (30000,30000,30000) L_0x12b6d20/d; +v0x107c670_0 .net *"_s0", 0 0, L_0x12b6de0; 1 drivers +v0x107c750_0 .net *"_s1", 0 0, L_0x12b6fd0; 1 drivers +S_0x107c830 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107ca40 .param/l "i" 0 4 54, +C4<01>; +L_0x12b7070/d .functor AND 1, L_0x12b7130, L_0x12b7290, C4<1>, C4<1>; +L_0x12b7070 .delay 1 (30000,30000,30000) L_0x12b7070/d; +v0x107cb00_0 .net *"_s0", 0 0, L_0x12b7130; 1 drivers +v0x107cbe0_0 .net *"_s1", 0 0, L_0x12b7290; 1 drivers +S_0x107ccc0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107ced0 .param/l "i" 0 4 54, +C4<010>; +L_0x12b7380/d .functor AND 1, L_0x12b7440, L_0x12b75a0, C4<1>, C4<1>; +L_0x12b7380 .delay 1 (30000,30000,30000) L_0x12b7380/d; +v0x107cf70_0 .net *"_s0", 0 0, L_0x12b7440; 1 drivers +v0x107d050_0 .net *"_s1", 0 0, L_0x12b75a0; 1 drivers +S_0x107d130 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107d340 .param/l "i" 0 4 54, +C4<011>; +L_0x12b7690/d .functor AND 1, L_0x12b7750, L_0x12b78b0, C4<1>, C4<1>; +L_0x12b7690 .delay 1 (30000,30000,30000) L_0x12b7690/d; +v0x107d400_0 .net *"_s0", 0 0, L_0x12b7750; 1 drivers +v0x107d4e0_0 .net *"_s1", 0 0, L_0x12b78b0; 1 drivers +S_0x107d5c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107d820 .param/l "i" 0 4 54, +C4<0100>; +L_0x12b79f0/d .functor AND 1, L_0x12b7ab0, L_0x12b7d20, C4<1>, C4<1>; +L_0x12b79f0 .delay 1 (30000,30000,30000) L_0x12b79f0/d; +v0x107d8e0_0 .net *"_s0", 0 0, L_0x12b7ab0; 1 drivers +v0x107d9c0_0 .net *"_s1", 0 0, L_0x12b7d20; 1 drivers +S_0x107daa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107dcb0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12b7dc0/d .functor AND 1, L_0x12b7e30, L_0x12b7f90, C4<1>, C4<1>; +L_0x12b7dc0 .delay 1 (30000,30000,30000) L_0x12b7dc0/d; +v0x107dd70_0 .net *"_s0", 0 0, L_0x12b7e30; 1 drivers +v0x107de50_0 .net *"_s1", 0 0, L_0x12b7f90; 1 drivers +S_0x107df30 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107e140 .param/l "i" 0 4 54, +C4<0110>; +L_0x12b80f0/d .functor AND 1, L_0x12b81b0, L_0x12b8310, C4<1>, C4<1>; +L_0x12b80f0 .delay 1 (30000,30000,30000) L_0x12b80f0/d; +v0x107e200_0 .net *"_s0", 0 0, L_0x12b81b0; 1 drivers +v0x107e2e0_0 .net *"_s1", 0 0, L_0x12b8310; 1 drivers +S_0x107e3c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x107c120; + .timescale -9 -12; +P_0x107e5d0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12b8080/d .functor AND 1, L_0x12b87c0, L_0x12b89b0, C4<1>, C4<1>; +L_0x12b8080 .delay 1 (30000,30000,30000) L_0x12b8080/d; +v0x107e690_0 .net *"_s0", 0 0, L_0x12b87c0; 1 drivers +v0x107e770_0 .net *"_s1", 0 0, L_0x12b89b0; 1 drivers +S_0x107f330 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x107bf00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12bb340/d .functor OR 1, L_0x12bb400, L_0x12bb5b0, C4<0>, C4<0>; +L_0x12bb340 .delay 1 (30000,30000,30000) L_0x12bb340/d; +v0x1080e80_0 .net *"_s10", 0 0, L_0x12bb400; 1 drivers +v0x1080f60_0 .net *"_s12", 0 0, L_0x12bb5b0; 1 drivers +v0x1081040_0 .net "in", 7 0, L_0x12b8400; alias, 1 drivers +v0x1081110_0 .net "ors", 1 0, L_0x12bb160; 1 drivers +v0x10811d0_0 .net "out", 0 0, L_0x12bb340; alias, 1 drivers +L_0x11f8de0 .part L_0x12b8400, 0, 4; +L_0x12bb160 .concat8 [ 1 1 0 0], L_0x11f8ad0, L_0x12bae50; +L_0x12bb2a0 .part L_0x12b8400, 4, 4; +L_0x12bb400 .part L_0x12bb160, 0, 1; +L_0x12bb5b0 .part L_0x12bb160, 1, 1; +S_0x107f4f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x107f330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12b4940/d .functor OR 1, L_0x11f8350, L_0x11f84b0, C4<0>, C4<0>; +L_0x12b4940 .delay 1 (30000,30000,30000) L_0x12b4940/d; +L_0x11f86e0/d .functor OR 1, L_0x11f87f0, L_0x11f8950, C4<0>, C4<0>; +L_0x11f86e0 .delay 1 (30000,30000,30000) L_0x11f86e0/d; +L_0x11f8ad0/d .functor OR 1, L_0x11f8b40, L_0x11f8cf0, C4<0>, C4<0>; +L_0x11f8ad0 .delay 1 (30000,30000,30000) L_0x11f8ad0/d; +v0x107f740_0 .net *"_s0", 0 0, L_0x12b4940; 1 drivers +v0x107f840_0 .net *"_s10", 0 0, L_0x11f87f0; 1 drivers +v0x107f920_0 .net *"_s12", 0 0, L_0x11f8950; 1 drivers +v0x107f9e0_0 .net *"_s14", 0 0, L_0x11f8b40; 1 drivers +v0x107fac0_0 .net *"_s16", 0 0, L_0x11f8cf0; 1 drivers +v0x107fbf0_0 .net *"_s3", 0 0, L_0x11f8350; 1 drivers +v0x107fcd0_0 .net *"_s5", 0 0, L_0x11f84b0; 1 drivers +v0x107fdb0_0 .net *"_s6", 0 0, L_0x11f86e0; 1 drivers +v0x107fe90_0 .net "in", 3 0, L_0x11f8de0; 1 drivers +v0x1080000_0 .net "ors", 1 0, L_0x11f85f0; 1 drivers +v0x10800e0_0 .net "out", 0 0, L_0x11f8ad0; 1 drivers +L_0x11f8350 .part L_0x11f8de0, 0, 1; +L_0x11f84b0 .part L_0x11f8de0, 1, 1; +L_0x11f85f0 .concat8 [ 1 1 0 0], L_0x12b4940, L_0x11f86e0; +L_0x11f87f0 .part L_0x11f8de0, 2, 1; +L_0x11f8950 .part L_0x11f8de0, 3, 1; +L_0x11f8b40 .part L_0x11f85f0, 0, 1; +L_0x11f8cf0 .part L_0x11f85f0, 1, 1; +S_0x1080200 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x107f330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x11f8f10/d .functor OR 1, L_0x11f8f80, L_0x11f90e0, C4<0>, C4<0>; +L_0x11f8f10 .delay 1 (30000,30000,30000) L_0x11f8f10/d; +L_0x12baab0/d .functor OR 1, L_0x12bab70, L_0x12bacd0, C4<0>, C4<0>; +L_0x12baab0 .delay 1 (30000,30000,30000) L_0x12baab0/d; +L_0x12bae50/d .functor OR 1, L_0x12baec0, L_0x12bb070, C4<0>, C4<0>; +L_0x12bae50 .delay 1 (30000,30000,30000) L_0x12bae50/d; +v0x10803c0_0 .net *"_s0", 0 0, L_0x11f8f10; 1 drivers +v0x10804c0_0 .net *"_s10", 0 0, L_0x12bab70; 1 drivers +v0x10805a0_0 .net *"_s12", 0 0, L_0x12bacd0; 1 drivers +v0x1080660_0 .net *"_s14", 0 0, L_0x12baec0; 1 drivers +v0x1080740_0 .net *"_s16", 0 0, L_0x12bb070; 1 drivers +v0x1080870_0 .net *"_s3", 0 0, L_0x11f8f80; 1 drivers +v0x1080950_0 .net *"_s5", 0 0, L_0x11f90e0; 1 drivers +v0x1080a30_0 .net *"_s6", 0 0, L_0x12baab0; 1 drivers +v0x1080b10_0 .net "in", 3 0, L_0x12bb2a0; 1 drivers +v0x1080c80_0 .net "ors", 1 0, L_0x11f9220; 1 drivers +v0x1080d60_0 .net "out", 0 0, L_0x12bae50; 1 drivers +L_0x11f8f80 .part L_0x12bb2a0, 0, 1; +L_0x11f90e0 .part L_0x12bb2a0, 1, 1; +L_0x11f9220 .concat8 [ 1 1 0 0], L_0x11f8f10, L_0x12baab0; +L_0x12bab70 .part L_0x12bb2a0, 2, 1; +L_0x12bacd0 .part L_0x12bb2a0, 3, 1; +L_0x12baec0 .part L_0x11f9220, 0, 1; +L_0x12bb070 .part L_0x11f9220, 1, 1; +S_0x1081670 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x107a7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1086aa0_0 .net "ands", 7 0, L_0x12b49c0; 1 drivers +v0x1086bb0_0 .net "in", 7 0, L_0x12b2930; alias, 1 drivers +v0x1086c70_0 .net "out", 0 0, L_0x12b69c0; alias, 1 drivers +v0x1086d40_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10818c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1081670; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1084000_0 .net "A", 7 0, L_0x12b2930; alias, 1 drivers +v0x1084100_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10841c0_0 .net *"_s0", 0 0, L_0x12b31b0; 1 drivers +v0x1084280_0 .net *"_s12", 0 0, L_0x12b3b70; 1 drivers +v0x1084360_0 .net *"_s16", 0 0, L_0x12b3ed0; 1 drivers +v0x1084490_0 .net *"_s20", 0 0, L_0x12b4300; 1 drivers +v0x1084570_0 .net *"_s24", 0 0, L_0x12b4630; 1 drivers +v0x1084650_0 .net *"_s28", 0 0, L_0x12b45c0; 1 drivers +v0x1084730_0 .net *"_s4", 0 0, L_0x12b3550; 1 drivers +v0x10848a0_0 .net *"_s8", 0 0, L_0x12b3860; 1 drivers +v0x1084980_0 .net "out", 7 0, L_0x12b49c0; alias, 1 drivers +L_0x12b32c0 .part L_0x12b2930, 0, 1; +L_0x12b34b0 .part v0x127a150_0, 0, 1; +L_0x12b3610 .part L_0x12b2930, 1, 1; +L_0x12b3770 .part v0x127a150_0, 1, 1; +L_0x12b3920 .part L_0x12b2930, 2, 1; +L_0x12b3a80 .part v0x127a150_0, 2, 1; +L_0x12b3c30 .part L_0x12b2930, 3, 1; +L_0x12b3d90 .part v0x127a150_0, 3, 1; +L_0x12b3f90 .part L_0x12b2930, 4, 1; +L_0x12b4200 .part v0x127a150_0, 4, 1; +L_0x12b4370 .part L_0x12b2930, 5, 1; +L_0x12b44d0 .part v0x127a150_0, 5, 1; +L_0x12b46f0 .part L_0x12b2930, 6, 1; +L_0x12b4850 .part v0x127a150_0, 6, 1; +LS_0x12b49c0_0_0 .concat8 [ 1 1 1 1], L_0x12b31b0, L_0x12b3550, L_0x12b3860, L_0x12b3b70; +LS_0x12b49c0_0_4 .concat8 [ 1 1 1 1], L_0x12b3ed0, L_0x12b4300, L_0x12b4630, L_0x12b45c0; +L_0x12b49c0 .concat8 [ 4 4 0 0], LS_0x12b49c0_0_0, LS_0x12b49c0_0_4; +L_0x12b4d80 .part L_0x12b2930, 7, 1; +L_0x12b4f70 .part v0x127a150_0, 7, 1; +S_0x1081b00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x1081d10 .param/l "i" 0 4 54, +C4<00>; +L_0x12b31b0/d .functor AND 1, L_0x12b32c0, L_0x12b34b0, C4<1>, C4<1>; +L_0x12b31b0 .delay 1 (30000,30000,30000) L_0x12b31b0/d; +v0x1081df0_0 .net *"_s0", 0 0, L_0x12b32c0; 1 drivers +v0x1081ed0_0 .net *"_s1", 0 0, L_0x12b34b0; 1 drivers +S_0x1081fb0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x10821c0 .param/l "i" 0 4 54, +C4<01>; +L_0x12b3550/d .functor AND 1, L_0x12b3610, L_0x12b3770, C4<1>, C4<1>; +L_0x12b3550 .delay 1 (30000,30000,30000) L_0x12b3550/d; +v0x1082280_0 .net *"_s0", 0 0, L_0x12b3610; 1 drivers +v0x1082360_0 .net *"_s1", 0 0, L_0x12b3770; 1 drivers +S_0x1082440 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x1082680 .param/l "i" 0 4 54, +C4<010>; +L_0x12b3860/d .functor AND 1, L_0x12b3920, L_0x12b3a80, C4<1>, C4<1>; +L_0x12b3860 .delay 1 (30000,30000,30000) L_0x12b3860/d; +v0x1082720_0 .net *"_s0", 0 0, L_0x12b3920; 1 drivers +v0x1082800_0 .net *"_s1", 0 0, L_0x12b3a80; 1 drivers +S_0x10828e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x1082af0 .param/l "i" 0 4 54, +C4<011>; +L_0x12b3b70/d .functor AND 1, L_0x12b3c30, L_0x12b3d90, C4<1>, C4<1>; +L_0x12b3b70 .delay 1 (30000,30000,30000) L_0x12b3b70/d; +v0x1082bb0_0 .net *"_s0", 0 0, L_0x12b3c30; 1 drivers +v0x1082c90_0 .net *"_s1", 0 0, L_0x12b3d90; 1 drivers +S_0x1082d70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x1082fd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12b3ed0/d .functor AND 1, L_0x12b3f90, L_0x12b4200, C4<1>, C4<1>; +L_0x12b3ed0 .delay 1 (30000,30000,30000) L_0x12b3ed0/d; +v0x1083090_0 .net *"_s0", 0 0, L_0x12b3f90; 1 drivers +v0x1083170_0 .net *"_s1", 0 0, L_0x12b4200; 1 drivers +S_0x1083250 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x1083460 .param/l "i" 0 4 54, +C4<0101>; +L_0x12b4300/d .functor AND 1, L_0x12b4370, L_0x12b44d0, C4<1>, C4<1>; +L_0x12b4300 .delay 1 (30000,30000,30000) L_0x12b4300/d; +v0x1083520_0 .net *"_s0", 0 0, L_0x12b4370; 1 drivers +v0x1083600_0 .net *"_s1", 0 0, L_0x12b44d0; 1 drivers +S_0x10836e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x10838f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12b4630/d .functor AND 1, L_0x12b46f0, L_0x12b4850, C4<1>, C4<1>; +L_0x12b4630 .delay 1 (30000,30000,30000) L_0x12b4630/d; +v0x10839b0_0 .net *"_s0", 0 0, L_0x12b46f0; 1 drivers +v0x1083a90_0 .net *"_s1", 0 0, L_0x12b4850; 1 drivers +S_0x1083b70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10818c0; + .timescale -9 -12; +P_0x1083d80 .param/l "i" 0 4 54, +C4<0111>; +L_0x12b45c0/d .functor AND 1, L_0x12b4d80, L_0x12b4f70, C4<1>, C4<1>; +L_0x12b45c0 .delay 1 (30000,30000,30000) L_0x12b45c0/d; +v0x1083e40_0 .net *"_s0", 0 0, L_0x12b4d80; 1 drivers +v0x1083f20_0 .net *"_s1", 0 0, L_0x12b4f70; 1 drivers +S_0x1084ae0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1081670; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12b69c0/d .functor OR 1, L_0x12b6a80, L_0x12b6c30, C4<0>, C4<0>; +L_0x12b69c0 .delay 1 (30000,30000,30000) L_0x12b69c0/d; +v0x1086630_0 .net *"_s10", 0 0, L_0x12b6a80; 1 drivers +v0x1086710_0 .net *"_s12", 0 0, L_0x12b6c30; 1 drivers +v0x10867f0_0 .net "in", 7 0, L_0x12b49c0; alias, 1 drivers +v0x10868c0_0 .net "ors", 1 0, L_0x12b67e0; 1 drivers +v0x1086980_0 .net "out", 0 0, L_0x12b69c0; alias, 1 drivers +L_0x12b5bb0 .part L_0x12b49c0, 0, 4; +L_0x12b67e0 .concat8 [ 1 1 0 0], L_0x12b58a0, L_0x12b64d0; +L_0x12b6920 .part L_0x12b49c0, 4, 4; +L_0x12b6a80 .part L_0x12b67e0, 0, 1; +L_0x12b6c30 .part L_0x12b67e0, 1, 1; +S_0x1084ca0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1084ae0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12b5060/d .functor OR 1, L_0x12b5120, L_0x12b5280, C4<0>, C4<0>; +L_0x12b5060 .delay 1 (30000,30000,30000) L_0x12b5060/d; +L_0x12b54b0/d .functor OR 1, L_0x12b55c0, L_0x12b5720, C4<0>, C4<0>; +L_0x12b54b0 .delay 1 (30000,30000,30000) L_0x12b54b0/d; +L_0x12b58a0/d .functor OR 1, L_0x12b5910, L_0x12b5ac0, C4<0>, C4<0>; +L_0x12b58a0 .delay 1 (30000,30000,30000) L_0x12b58a0/d; +v0x1084ef0_0 .net *"_s0", 0 0, L_0x12b5060; 1 drivers +v0x1084ff0_0 .net *"_s10", 0 0, L_0x12b55c0; 1 drivers +v0x10850d0_0 .net *"_s12", 0 0, L_0x12b5720; 1 drivers +v0x1085190_0 .net *"_s14", 0 0, L_0x12b5910; 1 drivers +v0x1085270_0 .net *"_s16", 0 0, L_0x12b5ac0; 1 drivers +v0x10853a0_0 .net *"_s3", 0 0, L_0x12b5120; 1 drivers +v0x1085480_0 .net *"_s5", 0 0, L_0x12b5280; 1 drivers +v0x1085560_0 .net *"_s6", 0 0, L_0x12b54b0; 1 drivers +v0x1085640_0 .net "in", 3 0, L_0x12b5bb0; 1 drivers +v0x10857b0_0 .net "ors", 1 0, L_0x12b53c0; 1 drivers +v0x1085890_0 .net "out", 0 0, L_0x12b58a0; 1 drivers +L_0x12b5120 .part L_0x12b5bb0, 0, 1; +L_0x12b5280 .part L_0x12b5bb0, 1, 1; +L_0x12b53c0 .concat8 [ 1 1 0 0], L_0x12b5060, L_0x12b54b0; +L_0x12b55c0 .part L_0x12b5bb0, 2, 1; +L_0x12b5720 .part L_0x12b5bb0, 3, 1; +L_0x12b5910 .part L_0x12b53c0, 0, 1; +L_0x12b5ac0 .part L_0x12b53c0, 1, 1; +S_0x10859b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1084ae0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12b5ce0/d .functor OR 1, L_0x12b5d50, L_0x12b5eb0, C4<0>, C4<0>; +L_0x12b5ce0 .delay 1 (30000,30000,30000) L_0x12b5ce0/d; +L_0x12b60e0/d .functor OR 1, L_0x12b61f0, L_0x12b6350, C4<0>, C4<0>; +L_0x12b60e0 .delay 1 (30000,30000,30000) L_0x12b60e0/d; +L_0x12b64d0/d .functor OR 1, L_0x12b6540, L_0x12b66f0, C4<0>, C4<0>; +L_0x12b64d0 .delay 1 (30000,30000,30000) L_0x12b64d0/d; +v0x1085b70_0 .net *"_s0", 0 0, L_0x12b5ce0; 1 drivers +v0x1085c70_0 .net *"_s10", 0 0, L_0x12b61f0; 1 drivers +v0x1085d50_0 .net *"_s12", 0 0, L_0x12b6350; 1 drivers +v0x1085e10_0 .net *"_s14", 0 0, L_0x12b6540; 1 drivers +v0x1085ef0_0 .net *"_s16", 0 0, L_0x12b66f0; 1 drivers +v0x1086020_0 .net *"_s3", 0 0, L_0x12b5d50; 1 drivers +v0x1086100_0 .net *"_s5", 0 0, L_0x12b5eb0; 1 drivers +v0x10861e0_0 .net *"_s6", 0 0, L_0x12b60e0; 1 drivers +v0x10862c0_0 .net "in", 3 0, L_0x12b6920; 1 drivers +v0x1086430_0 .net "ors", 1 0, L_0x12b5ff0; 1 drivers +v0x1086510_0 .net "out", 0 0, L_0x12b64d0; 1 drivers +L_0x12b5d50 .part L_0x12b6920, 0, 1; +L_0x12b5eb0 .part L_0x12b6920, 1, 1; +L_0x12b5ff0 .concat8 [ 1 1 0 0], L_0x12b5ce0, L_0x12b60e0; +L_0x12b61f0 .part L_0x12b6920, 2, 1; +L_0x12b6350 .part L_0x12b6920, 3, 1; +L_0x12b6540 .part L_0x12b5ff0, 0, 1; +L_0x12b66f0 .part L_0x12b5ff0, 1, 1; +S_0x1086e20 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x107a7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12b1770/d .functor XNOR 1, L_0x12bb900, L_0x12bb9a0, C4<0>, C4<0>; +L_0x12b1770 .delay 1 (20000,20000,20000) L_0x12b1770/d; +L_0x12b18f0/d .functor AND 1, L_0x12bb900, L_0x12b0500, C4<1>, C4<1>; +L_0x12b18f0 .delay 1 (30000,30000,30000) L_0x12b18f0/d; +L_0x12b1a50/d .functor AND 1, L_0x12b1770, L_0x12bba40, C4<1>, C4<1>; +L_0x12b1a50 .delay 1 (30000,30000,30000) L_0x12b1a50/d; +L_0x12b1b60/d .functor OR 1, L_0x12b1a50, L_0x12b18f0, C4<0>, C4<0>; +L_0x12b1b60 .delay 1 (30000,30000,30000) L_0x12b1b60/d; +v0x10870d0_0 .net "a", 0 0, L_0x12bb900; alias, 1 drivers +v0x10871c0_0 .net "a_", 0 0, L_0x12a5fb0; alias, 1 drivers +v0x1087280_0 .net "b", 0 0, L_0x12bb9a0; alias, 1 drivers +v0x1087370_0 .net "b_", 0 0, L_0x12b0500; alias, 1 drivers +v0x1087410_0 .net "carryin", 0 0, L_0x12bba40; alias, 1 drivers +v0x1087550_0 .net "eq", 0 0, L_0x12b1770; 1 drivers +v0x1087610_0 .net "lt", 0 0, L_0x12b18f0; 1 drivers +v0x10876d0_0 .net "out", 0 0, L_0x12b1b60; 1 drivers +v0x1087790_0 .net "w0", 0 0, L_0x12b1a50; 1 drivers +S_0x10879e0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x107a7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12b1350/d .functor OR 1, L_0x12b0ea0, L_0x1088c40, C4<0>, C4<0>; +L_0x12b1350 .delay 1 (30000,30000,30000) L_0x12b1350/d; +v0x10887d0_0 .net "a", 0 0, L_0x12bb900; alias, 1 drivers +v0x1088920_0 .net "b", 0 0, L_0x12b0500; alias, 1 drivers +v0x10889e0_0 .net "c1", 0 0, L_0x12b0ea0; 1 drivers +v0x1088a80_0 .net "c2", 0 0, L_0x1088c40; 1 drivers +v0x1088b50_0 .net "carryin", 0 0, L_0x12bba40; alias, 1 drivers +v0x1088cd0_0 .net "carryout", 0 0, L_0x12b1350; 1 drivers +v0x1088d70_0 .net "s1", 0 0, L_0x12b0de0; 1 drivers +v0x1088e10_0 .net "sum", 0 0, L_0x12b1000; 1 drivers +S_0x1087c30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10879e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12b0de0/d .functor XOR 1, L_0x12bb900, L_0x12b0500, C4<0>, C4<0>; +L_0x12b0de0 .delay 1 (30000,30000,30000) L_0x12b0de0/d; +L_0x12b0ea0/d .functor AND 1, L_0x12bb900, L_0x12b0500, C4<1>, C4<1>; +L_0x12b0ea0 .delay 1 (30000,30000,30000) L_0x12b0ea0/d; +v0x1087e90_0 .net "a", 0 0, L_0x12bb900; alias, 1 drivers +v0x1087f50_0 .net "b", 0 0, L_0x12b0500; alias, 1 drivers +v0x1088010_0 .net "carryout", 0 0, L_0x12b0ea0; alias, 1 drivers +v0x10880b0_0 .net "sum", 0 0, L_0x12b0de0; alias, 1 drivers +S_0x10881e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10879e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12b1000/d .functor XOR 1, L_0x12b0de0, L_0x12bba40, C4<0>, C4<0>; +L_0x12b1000 .delay 1 (30000,30000,30000) L_0x12b1000/d; +L_0x1088c40/d .functor AND 1, L_0x12b0de0, L_0x12bba40, C4<1>, C4<1>; +L_0x1088c40 .delay 1 (30000,30000,30000) L_0x1088c40/d; +v0x1088440_0 .net "a", 0 0, L_0x12b0de0; alias, 1 drivers +v0x1088510_0 .net "b", 0 0, L_0x12bba40; alias, 1 drivers +v0x10885b0_0 .net "carryout", 0 0, L_0x1088c40; alias, 1 drivers +v0x1088680_0 .net "sum", 0 0, L_0x12b1000; alias, 1 drivers +S_0x108aea0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x107a4d0; + .timescale -9 -12; +L_0x2ac432884698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328846e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b0960/d .functor OR 1, L_0x2ac432884698, L_0x2ac4328846e0, C4<0>, C4<0>; +L_0x12b0960 .delay 1 (30000,30000,30000) L_0x12b0960/d; +v0x108b090_0 .net/2u *"_s0", 0 0, L_0x2ac432884698; 1 drivers +v0x108b170_0 .net/2u *"_s2", 0 0, L_0x2ac4328846e0; 1 drivers +S_0x108b250 .scope generate, "alu_slices[6]" "alu_slices[6]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x108b460 .param/l "i" 0 3 39, +C4<0110>; +S_0x108b520 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x108b250; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12bbc20/d .functor NOT 1, L_0x12c6100, C4<0>, C4<0>, C4<0>; +L_0x12bbc20 .delay 1 (10000,10000,10000) L_0x12bbc20/d; +L_0x12bbd80/d .functor NOT 1, L_0x12c6370, C4<0>, C4<0>, C4<0>; +L_0x12bbd80 .delay 1 (10000,10000,10000) L_0x12bbd80/d; +L_0x12bcdd0/d .functor XOR 1, L_0x12c6100, L_0x12c6370, C4<0>, C4<0>; +L_0x12bcdd0 .delay 1 (30000,30000,30000) L_0x12bcdd0/d; +L_0x2ac432884728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bce90/d .functor OR 1, L_0x2ac432884728, L_0x2ac432884770, C4<0>, C4<0>; +L_0x12bce90 .delay 1 (30000,30000,30000) L_0x12bce90/d; +L_0x2ac4328847b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bd630/d .functor OR 1, L_0x2ac4328847b8, L_0x2ac432884800, C4<0>, C4<0>; +L_0x12bd630 .delay 1 (30000,30000,30000) L_0x12bd630/d; +L_0x12bd830/d .functor AND 1, L_0x12c6100, L_0x12c6370, C4<1>, C4<1>; +L_0x12bd830 .delay 1 (30000,30000,30000) L_0x12bd830/d; +L_0x2ac432884848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bd8f0/d .functor OR 1, L_0x2ac432884848, L_0x2ac432884890, C4<0>, C4<0>; +L_0x12bd8f0 .delay 1 (30000,30000,30000) L_0x12bd8f0/d; +L_0x12bdaf0/d .functor NAND 1, L_0x12c6100, L_0x12c6370, C4<1>, C4<1>; +L_0x12bdaf0 .delay 1 (20000,20000,20000) L_0x12bdaf0/d; +L_0x2ac4328848d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884920 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bdc00/d .functor OR 1, L_0x2ac4328848d8, L_0x2ac432884920, C4<0>, C4<0>; +L_0x12bdc00 .delay 1 (30000,30000,30000) L_0x12bdc00/d; +L_0x12bddb0/d .functor NOR 1, L_0x12c6100, L_0x12c6370, C4<0>, C4<0>; +L_0x12bddb0 .delay 1 (20000,20000,20000) L_0x12bddb0/d; +L_0x2ac432884968 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328849b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12be080/d .functor OR 1, L_0x2ac432884968, L_0x2ac4328849b0, C4<0>, C4<0>; +L_0x12be080 .delay 1 (30000,30000,30000) L_0x12be080/d; +L_0x12be480/d .functor OR 1, L_0x12c6100, L_0x12c6370, C4<0>, C4<0>; +L_0x12be480 .delay 1 (30000,30000,30000) L_0x12be480/d; +L_0x2ac4328849f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884a40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12be920/d .functor OR 1, L_0x2ac4328849f8, L_0x2ac432884a40, C4<0>, C4<0>; +L_0x12be920 .delay 1 (30000,30000,30000) L_0x12be920/d; +L_0x12c6000/d .functor NOT 1, L_0x12c2260, C4<0>, C4<0>, C4<0>; +L_0x12c6000 .delay 1 (10000,10000,10000) L_0x12c6000/d; +v0x1099e60_0 .net "A", 0 0, L_0x12c6100; 1 drivers +v0x1099f20_0 .net "A_", 0 0, L_0x12bbc20; 1 drivers +v0x1099fe0_0 .net "B", 0 0, L_0x12c6370; 1 drivers +v0x109a0b0_0 .net "B_", 0 0, L_0x12bbd80; 1 drivers +v0x109a150_0 .net *"_s11", 0 0, L_0x12bce90; 1 drivers +v0x109a240_0 .net/2s *"_s13", 0 0, L_0x2ac432884728; 1 drivers +v0x109a300_0 .net/2s *"_s15", 0 0, L_0x2ac432884770; 1 drivers +v0x109a3e0_0 .net *"_s19", 0 0, L_0x12bd630; 1 drivers +v0x109a4c0_0 .net/2s *"_s21", 0 0, L_0x2ac4328847b8; 1 drivers +v0x109a630_0 .net/2s *"_s23", 0 0, L_0x2ac432884800; 1 drivers +v0x109a710_0 .net *"_s25", 0 0, L_0x12bd830; 1 drivers +v0x109a7f0_0 .net *"_s28", 0 0, L_0x12bd8f0; 1 drivers +v0x109a8d0_0 .net/2s *"_s30", 0 0, L_0x2ac432884848; 1 drivers +v0x109a9b0_0 .net/2s *"_s32", 0 0, L_0x2ac432884890; 1 drivers +v0x109aa90_0 .net *"_s34", 0 0, L_0x12bdaf0; 1 drivers +v0x109ab70_0 .net *"_s37", 0 0, L_0x12bdc00; 1 drivers +v0x109ac50_0 .net/2s *"_s39", 0 0, L_0x2ac4328848d8; 1 drivers +v0x109ae00_0 .net/2s *"_s41", 0 0, L_0x2ac432884920; 1 drivers +v0x109aea0_0 .net *"_s43", 0 0, L_0x12bddb0; 1 drivers +v0x109af80_0 .net *"_s46", 0 0, L_0x12be080; 1 drivers +v0x109b060_0 .net/2s *"_s48", 0 0, L_0x2ac432884968; 1 drivers +v0x109b140_0 .net/2s *"_s50", 0 0, L_0x2ac4328849b0; 1 drivers +v0x109b220_0 .net *"_s52", 0 0, L_0x12be480; 1 drivers +v0x109b300_0 .net *"_s56", 0 0, L_0x12be920; 1 drivers +v0x109b3e0_0 .net/2s *"_s59", 0 0, L_0x2ac4328849f8; 1 drivers +v0x109b4c0_0 .net/2s *"_s61", 0 0, L_0x2ac432884a40; 1 drivers +v0x109b5a0_0 .net *"_s8", 0 0, L_0x12bcdd0; 1 drivers +v0x109b680_0 .net "carryin", 0 0, L_0x12bbae0; 1 drivers +v0x109b720_0 .net "carryout", 0 0, L_0x12c5ca0; 1 drivers +v0x109b7c0_0 .net "carryouts", 7 0, L_0x12be590; 1 drivers +v0x109b8d0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x109b990_0 .net "result", 0 0, L_0x12c2260; 1 drivers +v0x109ba80_0 .net "results", 7 0, L_0x12be250; 1 drivers +v0x109ad60_0 .net "zero", 0 0, L_0x12c6000; 1 drivers +LS_0x12be250_0_0 .concat8 [ 1 1 1 1], L_0x12bc2a0, L_0x12bc8d0, L_0x12bcdd0, L_0x12bd630; +LS_0x12be250_0_4 .concat8 [ 1 1 1 1], L_0x12bd830, L_0x12bdaf0, L_0x12bddb0, L_0x12be480; +L_0x12be250 .concat8 [ 4 4 0 0], LS_0x12be250_0_0, LS_0x12be250_0_4; +LS_0x12be590_0_0 .concat8 [ 1 1 1 1], L_0x12bc550, L_0x12bcc70, L_0x12bce90, L_0x12bd480; +LS_0x12be590_0_4 .concat8 [ 1 1 1 1], L_0x12bd8f0, L_0x12bdc00, L_0x12be080, L_0x12be920; +L_0x12be590 .concat8 [ 4 4 0 0], LS_0x12be590_0_0, LS_0x12be590_0_4; +S_0x108b7a0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x108b520; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12bc550/d .functor OR 1, L_0x12bc030, L_0x12bc3f0, C4<0>, C4<0>; +L_0x12bc550 .delay 1 (30000,30000,30000) L_0x12bc550/d; +v0x108c5d0_0 .net "a", 0 0, L_0x12c6100; alias, 1 drivers +v0x108c690_0 .net "b", 0 0, L_0x12c6370; alias, 1 drivers +v0x108c760_0 .net "c1", 0 0, L_0x12bc030; 1 drivers +v0x108c860_0 .net "c2", 0 0, L_0x12bc3f0; 1 drivers +v0x108c930_0 .net "carryin", 0 0, L_0x12bbae0; alias, 1 drivers +v0x108ca20_0 .net "carryout", 0 0, L_0x12bc550; 1 drivers +v0x108cac0_0 .net "s1", 0 0, L_0x12bbf70; 1 drivers +v0x108cbb0_0 .net "sum", 0 0, L_0x12bc2a0; 1 drivers +S_0x108ba10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x108b7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12bbf70/d .functor XOR 1, L_0x12c6100, L_0x12c6370, C4<0>, C4<0>; +L_0x12bbf70 .delay 1 (30000,30000,30000) L_0x12bbf70/d; +L_0x12bc030/d .functor AND 1, L_0x12c6100, L_0x12c6370, C4<1>, C4<1>; +L_0x12bc030 .delay 1 (30000,30000,30000) L_0x12bc030/d; +v0x108bc70_0 .net "a", 0 0, L_0x12c6100; alias, 1 drivers +v0x108bd50_0 .net "b", 0 0, L_0x12c6370; alias, 1 drivers +v0x108be10_0 .net "carryout", 0 0, L_0x12bc030; alias, 1 drivers +v0x108beb0_0 .net "sum", 0 0, L_0x12bbf70; alias, 1 drivers +S_0x108bff0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x108b7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12bc2a0/d .functor XOR 1, L_0x12bbf70, L_0x12bbae0, C4<0>, C4<0>; +L_0x12bc2a0 .delay 1 (30000,30000,30000) L_0x12bc2a0/d; +L_0x12bc3f0/d .functor AND 1, L_0x12bbf70, L_0x12bbae0, C4<1>, C4<1>; +L_0x12bc3f0 .delay 1 (30000,30000,30000) L_0x12bc3f0/d; +v0x108c250_0 .net "a", 0 0, L_0x12bbf70; alias, 1 drivers +v0x108c2f0_0 .net "b", 0 0, L_0x12bbae0; alias, 1 drivers +v0x108c390_0 .net "carryout", 0 0, L_0x12bc3f0; alias, 1 drivers +v0x108c460_0 .net "sum", 0 0, L_0x12bc2a0; alias, 1 drivers +S_0x108cc80 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x108b520; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1092070_0 .net "ands", 7 0, L_0x12c3ca0; 1 drivers +v0x1092180_0 .net "in", 7 0, L_0x12be590; alias, 1 drivers +v0x1092240_0 .net "out", 0 0, L_0x12c5ca0; alias, 1 drivers +v0x1092310_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x108cea0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x108cc80; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x108f5d0_0 .net "A", 7 0, L_0x12be590; alias, 1 drivers +v0x108f6d0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x108f790_0 .net *"_s0", 0 0, L_0x12c25c0; 1 drivers +v0x108f850_0 .net *"_s12", 0 0, L_0x12c2f30; 1 drivers +v0x108f930_0 .net *"_s16", 0 0, L_0x12c3290; 1 drivers +v0x108fa60_0 .net *"_s20", 0 0, L_0x12c3660; 1 drivers +v0x108fb40_0 .net *"_s24", 0 0, L_0x12c3990; 1 drivers +v0x108fc20_0 .net *"_s28", 0 0, L_0x12c3920; 1 drivers +v0x108fd00_0 .net *"_s4", 0 0, L_0x12c2910; 1 drivers +v0x108fe70_0 .net *"_s8", 0 0, L_0x12c2c20; 1 drivers +v0x108ff50_0 .net "out", 7 0, L_0x12c3ca0; alias, 1 drivers +L_0x12c2680 .part L_0x12be590, 0, 1; +L_0x12c2870 .part v0x127a150_0, 0, 1; +L_0x12c29d0 .part L_0x12be590, 1, 1; +L_0x12c2b30 .part v0x127a150_0, 1, 1; +L_0x12c2ce0 .part L_0x12be590, 2, 1; +L_0x12c2e40 .part v0x127a150_0, 2, 1; +L_0x12c2ff0 .part L_0x12be590, 3, 1; +L_0x12c3150 .part v0x127a150_0, 3, 1; +L_0x12c3350 .part L_0x12be590, 4, 1; +L_0x12c35c0 .part v0x127a150_0, 4, 1; +L_0x12c36d0 .part L_0x12be590, 5, 1; +L_0x12c3830 .part v0x127a150_0, 5, 1; +L_0x12c3a50 .part L_0x12be590, 6, 1; +L_0x12c3bb0 .part v0x127a150_0, 6, 1; +LS_0x12c3ca0_0_0 .concat8 [ 1 1 1 1], L_0x12c25c0, L_0x12c2910, L_0x12c2c20, L_0x12c2f30; +LS_0x12c3ca0_0_4 .concat8 [ 1 1 1 1], L_0x12c3290, L_0x12c3660, L_0x12c3990, L_0x12c3920; +L_0x12c3ca0 .concat8 [ 4 4 0 0], LS_0x12c3ca0_0_0, LS_0x12c3ca0_0_4; +L_0x12c4060 .part L_0x12be590, 7, 1; +L_0x12c4250 .part v0x127a150_0, 7, 1; +S_0x108d100 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108d310 .param/l "i" 0 4 54, +C4<00>; +L_0x12c25c0/d .functor AND 1, L_0x12c2680, L_0x12c2870, C4<1>, C4<1>; +L_0x12c25c0 .delay 1 (30000,30000,30000) L_0x12c25c0/d; +v0x108d3f0_0 .net *"_s0", 0 0, L_0x12c2680; 1 drivers +v0x108d4d0_0 .net *"_s1", 0 0, L_0x12c2870; 1 drivers +S_0x108d5b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108d7c0 .param/l "i" 0 4 54, +C4<01>; +L_0x12c2910/d .functor AND 1, L_0x12c29d0, L_0x12c2b30, C4<1>, C4<1>; +L_0x12c2910 .delay 1 (30000,30000,30000) L_0x12c2910/d; +v0x108d880_0 .net *"_s0", 0 0, L_0x12c29d0; 1 drivers +v0x108d960_0 .net *"_s1", 0 0, L_0x12c2b30; 1 drivers +S_0x108da40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108dc50 .param/l "i" 0 4 54, +C4<010>; +L_0x12c2c20/d .functor AND 1, L_0x12c2ce0, L_0x12c2e40, C4<1>, C4<1>; +L_0x12c2c20 .delay 1 (30000,30000,30000) L_0x12c2c20/d; +v0x108dcf0_0 .net *"_s0", 0 0, L_0x12c2ce0; 1 drivers +v0x108ddd0_0 .net *"_s1", 0 0, L_0x12c2e40; 1 drivers +S_0x108deb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108e0c0 .param/l "i" 0 4 54, +C4<011>; +L_0x12c2f30/d .functor AND 1, L_0x12c2ff0, L_0x12c3150, C4<1>, C4<1>; +L_0x12c2f30 .delay 1 (30000,30000,30000) L_0x12c2f30/d; +v0x108e180_0 .net *"_s0", 0 0, L_0x12c2ff0; 1 drivers +v0x108e260_0 .net *"_s1", 0 0, L_0x12c3150; 1 drivers +S_0x108e340 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108e5a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12c3290/d .functor AND 1, L_0x12c3350, L_0x12c35c0, C4<1>, C4<1>; +L_0x12c3290 .delay 1 (30000,30000,30000) L_0x12c3290/d; +v0x108e660_0 .net *"_s0", 0 0, L_0x12c3350; 1 drivers +v0x108e740_0 .net *"_s1", 0 0, L_0x12c35c0; 1 drivers +S_0x108e820 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108ea30 .param/l "i" 0 4 54, +C4<0101>; +L_0x12c3660/d .functor AND 1, L_0x12c36d0, L_0x12c3830, C4<1>, C4<1>; +L_0x12c3660 .delay 1 (30000,30000,30000) L_0x12c3660/d; +v0x108eaf0_0 .net *"_s0", 0 0, L_0x12c36d0; 1 drivers +v0x108ebd0_0 .net *"_s1", 0 0, L_0x12c3830; 1 drivers +S_0x108ecb0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108eec0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12c3990/d .functor AND 1, L_0x12c3a50, L_0x12c3bb0, C4<1>, C4<1>; +L_0x12c3990 .delay 1 (30000,30000,30000) L_0x12c3990/d; +v0x108ef80_0 .net *"_s0", 0 0, L_0x12c3a50; 1 drivers +v0x108f060_0 .net *"_s1", 0 0, L_0x12c3bb0; 1 drivers +S_0x108f140 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x108cea0; + .timescale -9 -12; +P_0x108f350 .param/l "i" 0 4 54, +C4<0111>; +L_0x12c3920/d .functor AND 1, L_0x12c4060, L_0x12c4250, C4<1>, C4<1>; +L_0x12c3920 .delay 1 (30000,30000,30000) L_0x12c3920/d; +v0x108f410_0 .net *"_s0", 0 0, L_0x12c4060; 1 drivers +v0x108f4f0_0 .net *"_s1", 0 0, L_0x12c4250; 1 drivers +S_0x10900b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x108cc80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12c5ca0/d .functor OR 1, L_0x12c5d60, L_0x12c5f10, C4<0>, C4<0>; +L_0x12c5ca0 .delay 1 (30000,30000,30000) L_0x12c5ca0/d; +v0x1091c00_0 .net *"_s10", 0 0, L_0x12c5d60; 1 drivers +v0x1091ce0_0 .net *"_s12", 0 0, L_0x12c5f10; 1 drivers +v0x1091dc0_0 .net "in", 7 0, L_0x12c3ca0; alias, 1 drivers +v0x1091e90_0 .net "ors", 1 0, L_0x12c5ac0; 1 drivers +v0x1091f50_0 .net "out", 0 0, L_0x12c5ca0; alias, 1 drivers +L_0x12c4e90 .part L_0x12c3ca0, 0, 4; +L_0x12c5ac0 .concat8 [ 1 1 0 0], L_0x12c4b80, L_0x12c57b0; +L_0x12c5c00 .part L_0x12c3ca0, 4, 4; +L_0x12c5d60 .part L_0x12c5ac0, 0, 1; +L_0x12c5f10 .part L_0x12c5ac0, 1, 1; +S_0x1090270 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10900b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12c4340/d .functor OR 1, L_0x12c4400, L_0x12c4560, C4<0>, C4<0>; +L_0x12c4340 .delay 1 (30000,30000,30000) L_0x12c4340/d; +L_0x12c4790/d .functor OR 1, L_0x12c48a0, L_0x12c4a00, C4<0>, C4<0>; +L_0x12c4790 .delay 1 (30000,30000,30000) L_0x12c4790/d; +L_0x12c4b80/d .functor OR 1, L_0x12c4bf0, L_0x12c4da0, C4<0>, C4<0>; +L_0x12c4b80 .delay 1 (30000,30000,30000) L_0x12c4b80/d; +v0x10904c0_0 .net *"_s0", 0 0, L_0x12c4340; 1 drivers +v0x10905c0_0 .net *"_s10", 0 0, L_0x12c48a0; 1 drivers +v0x10906a0_0 .net *"_s12", 0 0, L_0x12c4a00; 1 drivers +v0x1090760_0 .net *"_s14", 0 0, L_0x12c4bf0; 1 drivers +v0x1090840_0 .net *"_s16", 0 0, L_0x12c4da0; 1 drivers +v0x1090970_0 .net *"_s3", 0 0, L_0x12c4400; 1 drivers +v0x1090a50_0 .net *"_s5", 0 0, L_0x12c4560; 1 drivers +v0x1090b30_0 .net *"_s6", 0 0, L_0x12c4790; 1 drivers +v0x1090c10_0 .net "in", 3 0, L_0x12c4e90; 1 drivers +v0x1090d80_0 .net "ors", 1 0, L_0x12c46a0; 1 drivers +v0x1090e60_0 .net "out", 0 0, L_0x12c4b80; 1 drivers +L_0x12c4400 .part L_0x12c4e90, 0, 1; +L_0x12c4560 .part L_0x12c4e90, 1, 1; +L_0x12c46a0 .concat8 [ 1 1 0 0], L_0x12c4340, L_0x12c4790; +L_0x12c48a0 .part L_0x12c4e90, 2, 1; +L_0x12c4a00 .part L_0x12c4e90, 3, 1; +L_0x12c4bf0 .part L_0x12c46a0, 0, 1; +L_0x12c4da0 .part L_0x12c46a0, 1, 1; +S_0x1090f80 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10900b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12c4fc0/d .functor OR 1, L_0x12c5030, L_0x12c5190, C4<0>, C4<0>; +L_0x12c4fc0 .delay 1 (30000,30000,30000) L_0x12c4fc0/d; +L_0x12c53c0/d .functor OR 1, L_0x12c54d0, L_0x12c5630, C4<0>, C4<0>; +L_0x12c53c0 .delay 1 (30000,30000,30000) L_0x12c53c0/d; +L_0x12c57b0/d .functor OR 1, L_0x12c5820, L_0x12c59d0, C4<0>, C4<0>; +L_0x12c57b0 .delay 1 (30000,30000,30000) L_0x12c57b0/d; +v0x1091140_0 .net *"_s0", 0 0, L_0x12c4fc0; 1 drivers +v0x1091240_0 .net *"_s10", 0 0, L_0x12c54d0; 1 drivers +v0x1091320_0 .net *"_s12", 0 0, L_0x12c5630; 1 drivers +v0x10913e0_0 .net *"_s14", 0 0, L_0x12c5820; 1 drivers +v0x10914c0_0 .net *"_s16", 0 0, L_0x12c59d0; 1 drivers +v0x10915f0_0 .net *"_s3", 0 0, L_0x12c5030; 1 drivers +v0x10916d0_0 .net *"_s5", 0 0, L_0x12c5190; 1 drivers +v0x10917b0_0 .net *"_s6", 0 0, L_0x12c53c0; 1 drivers +v0x1091890_0 .net "in", 3 0, L_0x12c5c00; 1 drivers +v0x1091a00_0 .net "ors", 1 0, L_0x12c52d0; 1 drivers +v0x1091ae0_0 .net "out", 0 0, L_0x12c57b0; 1 drivers +L_0x12c5030 .part L_0x12c5c00, 0, 1; +L_0x12c5190 .part L_0x12c5c00, 1, 1; +L_0x12c52d0 .concat8 [ 1 1 0 0], L_0x12c4fc0, L_0x12c53c0; +L_0x12c54d0 .part L_0x12c5c00, 2, 1; +L_0x12c5630 .part L_0x12c5c00, 3, 1; +L_0x12c5820 .part L_0x12c52d0, 0, 1; +L_0x12c59d0 .part L_0x12c52d0, 1, 1; +S_0x10923f0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x108b520; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1097a30_0 .net "ands", 7 0, L_0x12c0260; 1 drivers +v0x1097b40_0 .net "in", 7 0, L_0x12be250; alias, 1 drivers +v0x1097c00_0 .net "out", 0 0, L_0x12c2260; alias, 1 drivers +v0x1097cd0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1092640 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10923f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1094d80_0 .net "A", 7 0, L_0x12be250; alias, 1 drivers +v0x1094e80_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x105fa10_0 .net *"_s0", 0 0, L_0x12bead0; 1 drivers +v0x105fad0_0 .net *"_s12", 0 0, L_0x12bf490; 1 drivers +v0x1095350_0 .net *"_s16", 0 0, L_0x12bf7f0; 1 drivers +v0x1095410_0 .net *"_s20", 0 0, L_0x12bfc20; 1 drivers +v0x10954f0_0 .net *"_s24", 0 0, L_0x12bff50; 1 drivers +v0x10955d0_0 .net *"_s28", 0 0, L_0x12bfee0; 1 drivers +v0x10956b0_0 .net *"_s4", 0 0, L_0x12bee70; 1 drivers +v0x1095820_0 .net *"_s8", 0 0, L_0x12bf180; 1 drivers +v0x1095900_0 .net "out", 7 0, L_0x12c0260; alias, 1 drivers +L_0x12bebe0 .part L_0x12be250, 0, 1; +L_0x12bedd0 .part v0x127a150_0, 0, 1; +L_0x12bef30 .part L_0x12be250, 1, 1; +L_0x12bf090 .part v0x127a150_0, 1, 1; +L_0x12bf240 .part L_0x12be250, 2, 1; +L_0x12bf3a0 .part v0x127a150_0, 2, 1; +L_0x12bf550 .part L_0x12be250, 3, 1; +L_0x12bf6b0 .part v0x127a150_0, 3, 1; +L_0x12bf8b0 .part L_0x12be250, 4, 1; +L_0x12bfb20 .part v0x127a150_0, 4, 1; +L_0x12bfc90 .part L_0x12be250, 5, 1; +L_0x12bfdf0 .part v0x127a150_0, 5, 1; +L_0x12c0010 .part L_0x12be250, 6, 1; +L_0x12c0170 .part v0x127a150_0, 6, 1; +LS_0x12c0260_0_0 .concat8 [ 1 1 1 1], L_0x12bead0, L_0x12bee70, L_0x12bf180, L_0x12bf490; +LS_0x12c0260_0_4 .concat8 [ 1 1 1 1], L_0x12bf7f0, L_0x12bfc20, L_0x12bff50, L_0x12bfee0; +L_0x12c0260 .concat8 [ 4 4 0 0], LS_0x12c0260_0_0, LS_0x12c0260_0_4; +L_0x12c0620 .part L_0x12be250, 7, 1; +L_0x12c0810 .part v0x127a150_0, 7, 1; +S_0x1092880 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1092a90 .param/l "i" 0 4 54, +C4<00>; +L_0x12bead0/d .functor AND 1, L_0x12bebe0, L_0x12bedd0, C4<1>, C4<1>; +L_0x12bead0 .delay 1 (30000,30000,30000) L_0x12bead0/d; +v0x1092b70_0 .net *"_s0", 0 0, L_0x12bebe0; 1 drivers +v0x1092c50_0 .net *"_s1", 0 0, L_0x12bedd0; 1 drivers +S_0x1092d30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1092f40 .param/l "i" 0 4 54, +C4<01>; +L_0x12bee70/d .functor AND 1, L_0x12bef30, L_0x12bf090, C4<1>, C4<1>; +L_0x12bee70 .delay 1 (30000,30000,30000) L_0x12bee70/d; +v0x1093000_0 .net *"_s0", 0 0, L_0x12bef30; 1 drivers +v0x10930e0_0 .net *"_s1", 0 0, L_0x12bf090; 1 drivers +S_0x10931c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1093400 .param/l "i" 0 4 54, +C4<010>; +L_0x12bf180/d .functor AND 1, L_0x12bf240, L_0x12bf3a0, C4<1>, C4<1>; +L_0x12bf180 .delay 1 (30000,30000,30000) L_0x12bf180/d; +v0x10934a0_0 .net *"_s0", 0 0, L_0x12bf240; 1 drivers +v0x1093580_0 .net *"_s1", 0 0, L_0x12bf3a0; 1 drivers +S_0x1093660 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1093870 .param/l "i" 0 4 54, +C4<011>; +L_0x12bf490/d .functor AND 1, L_0x12bf550, L_0x12bf6b0, C4<1>, C4<1>; +L_0x12bf490 .delay 1 (30000,30000,30000) L_0x12bf490/d; +v0x1093930_0 .net *"_s0", 0 0, L_0x12bf550; 1 drivers +v0x1093a10_0 .net *"_s1", 0 0, L_0x12bf6b0; 1 drivers +S_0x1093af0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1093d50 .param/l "i" 0 4 54, +C4<0100>; +L_0x12bf7f0/d .functor AND 1, L_0x12bf8b0, L_0x12bfb20, C4<1>, C4<1>; +L_0x12bf7f0 .delay 1 (30000,30000,30000) L_0x12bf7f0/d; +v0x1093e10_0 .net *"_s0", 0 0, L_0x12bf8b0; 1 drivers +v0x1093ef0_0 .net *"_s1", 0 0, L_0x12bfb20; 1 drivers +S_0x1093fd0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x10941e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12bfc20/d .functor AND 1, L_0x12bfc90, L_0x12bfdf0, C4<1>, C4<1>; +L_0x12bfc20 .delay 1 (30000,30000,30000) L_0x12bfc20/d; +v0x10942a0_0 .net *"_s0", 0 0, L_0x12bfc90; 1 drivers +v0x1094380_0 .net *"_s1", 0 0, L_0x12bfdf0; 1 drivers +S_0x1094460 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1094670 .param/l "i" 0 4 54, +C4<0110>; +L_0x12bff50/d .functor AND 1, L_0x12c0010, L_0x12c0170, C4<1>, C4<1>; +L_0x12bff50 .delay 1 (30000,30000,30000) L_0x12bff50/d; +v0x1094730_0 .net *"_s0", 0 0, L_0x12c0010; 1 drivers +v0x1094810_0 .net *"_s1", 0 0, L_0x12c0170; 1 drivers +S_0x10948f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1092640; + .timescale -9 -12; +P_0x1094b00 .param/l "i" 0 4 54, +C4<0111>; +L_0x12bfee0/d .functor AND 1, L_0x12c0620, L_0x12c0810, C4<1>, C4<1>; +L_0x12bfee0 .delay 1 (30000,30000,30000) L_0x12bfee0/d; +v0x1094bc0_0 .net *"_s0", 0 0, L_0x12c0620; 1 drivers +v0x1094ca0_0 .net *"_s1", 0 0, L_0x12c0810; 1 drivers +S_0x1095a60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10923f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12c2260/d .functor OR 1, L_0x12c2320, L_0x12c24d0, C4<0>, C4<0>; +L_0x12c2260 .delay 1 (30000,30000,30000) L_0x12c2260/d; +v0x1097590_0 .net *"_s10", 0 0, L_0x12c2320; 1 drivers +v0x1097670_0 .net *"_s12", 0 0, L_0x12c24d0; 1 drivers +v0x1097750_0 .net "in", 7 0, L_0x12c0260; alias, 1 drivers +v0x1097850_0 .net "ors", 1 0, L_0x12c2080; 1 drivers +v0x1097910_0 .net "out", 0 0, L_0x12c2260; alias, 1 drivers +L_0x12c1450 .part L_0x12c0260, 0, 4; +L_0x12c2080 .concat8 [ 1 1 0 0], L_0x12c1140, L_0x12c1d70; +L_0x12c21c0 .part L_0x12c0260, 4, 4; +L_0x12c2320 .part L_0x12c2080, 0, 1; +L_0x12c24d0 .part L_0x12c2080, 1, 1; +S_0x1095c20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1095a60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12c0900/d .functor OR 1, L_0x12c09c0, L_0x12c0b20, C4<0>, C4<0>; +L_0x12c0900 .delay 1 (30000,30000,30000) L_0x12c0900/d; +L_0x12c0d50/d .functor OR 1, L_0x12c0e60, L_0x12c0fc0, C4<0>, C4<0>; +L_0x12c0d50 .delay 1 (30000,30000,30000) L_0x12c0d50/d; +L_0x12c1140/d .functor OR 1, L_0x12c11b0, L_0x12c1360, C4<0>, C4<0>; +L_0x12c1140 .delay 1 (30000,30000,30000) L_0x12c1140/d; +v0x1095e70_0 .net *"_s0", 0 0, L_0x12c0900; 1 drivers +v0x1095f70_0 .net *"_s10", 0 0, L_0x12c0e60; 1 drivers +v0x1096050_0 .net *"_s12", 0 0, L_0x12c0fc0; 1 drivers +v0x1096110_0 .net *"_s14", 0 0, L_0x12c11b0; 1 drivers +v0x10961f0_0 .net *"_s16", 0 0, L_0x12c1360; 1 drivers +v0x1096320_0 .net *"_s3", 0 0, L_0x12c09c0; 1 drivers +v0x1096400_0 .net *"_s5", 0 0, L_0x12c0b20; 1 drivers +v0x10964e0_0 .net *"_s6", 0 0, L_0x12c0d50; 1 drivers +v0x10965c0_0 .net "in", 3 0, L_0x12c1450; 1 drivers +v0x1096730_0 .net "ors", 1 0, L_0x12c0c60; 1 drivers +v0x1096810_0 .net "out", 0 0, L_0x12c1140; 1 drivers +L_0x12c09c0 .part L_0x12c1450, 0, 1; +L_0x12c0b20 .part L_0x12c1450, 1, 1; +L_0x12c0c60 .concat8 [ 1 1 0 0], L_0x12c0900, L_0x12c0d50; +L_0x12c0e60 .part L_0x12c1450, 2, 1; +L_0x12c0fc0 .part L_0x12c1450, 3, 1; +L_0x12c11b0 .part L_0x12c0c60, 0, 1; +L_0x12c1360 .part L_0x12c0c60, 1, 1; +S_0x1096930 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1095a60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12c1580/d .functor OR 1, L_0x12c15f0, L_0x12c1750, C4<0>, C4<0>; +L_0x12c1580 .delay 1 (30000,30000,30000) L_0x12c1580/d; +L_0x12c1980/d .functor OR 1, L_0x12c1a90, L_0x12c1bf0, C4<0>, C4<0>; +L_0x12c1980 .delay 1 (30000,30000,30000) L_0x12c1980/d; +L_0x12c1d70/d .functor OR 1, L_0x12c1de0, L_0x12c1f90, C4<0>, C4<0>; +L_0x12c1d70 .delay 1 (30000,30000,30000) L_0x12c1d70/d; +v0x1096af0_0 .net *"_s0", 0 0, L_0x12c1580; 1 drivers +v0x1096bf0_0 .net *"_s10", 0 0, L_0x12c1a90; 1 drivers +v0x1096cd0_0 .net *"_s12", 0 0, L_0x12c1bf0; 1 drivers +v0x1096d90_0 .net *"_s14", 0 0, L_0x12c1de0; 1 drivers +v0x1096e70_0 .net *"_s16", 0 0, L_0x12c1f90; 1 drivers +v0x1096fa0_0 .net *"_s3", 0 0, L_0x12c15f0; 1 drivers +v0x1097060_0 .net *"_s5", 0 0, L_0x12c1750; 1 drivers +v0x1097140_0 .net *"_s6", 0 0, L_0x12c1980; 1 drivers +v0x1097220_0 .net "in", 3 0, L_0x12c21c0; 1 drivers +v0x1097390_0 .net "ors", 1 0, L_0x12c1890; 1 drivers +v0x1097470_0 .net "out", 0 0, L_0x12c1d70; 1 drivers +L_0x12c15f0 .part L_0x12c21c0, 0, 1; +L_0x12c1750 .part L_0x12c21c0, 1, 1; +L_0x12c1890 .concat8 [ 1 1 0 0], L_0x12c1580, L_0x12c1980; +L_0x12c1a90 .part L_0x12c21c0, 2, 1; +L_0x12c1bf0 .part L_0x12c21c0, 3, 1; +L_0x12c1de0 .part L_0x12c1890, 0, 1; +L_0x12c1f90 .part L_0x12c1890, 1, 1; +S_0x1097db0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x108b520; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12bd090/d .functor XNOR 1, L_0x12c6100, L_0x12c6370, C4<0>, C4<0>; +L_0x12bd090 .delay 1 (20000,20000,20000) L_0x12bd090/d; +L_0x12bd210/d .functor AND 1, L_0x12c6100, L_0x12bbd80, C4<1>, C4<1>; +L_0x12bd210 .delay 1 (30000,30000,30000) L_0x12bd210/d; +L_0x12bd370/d .functor AND 1, L_0x12bd090, L_0x12bbae0, C4<1>, C4<1>; +L_0x12bd370 .delay 1 (30000,30000,30000) L_0x12bd370/d; +L_0x12bd480/d .functor OR 1, L_0x12bd370, L_0x12bd210, C4<0>, C4<0>; +L_0x12bd480 .delay 1 (30000,30000,30000) L_0x12bd480/d; +v0x1098060_0 .net "a", 0 0, L_0x12c6100; alias, 1 drivers +v0x1098150_0 .net "a_", 0 0, L_0x12bbc20; alias, 1 drivers +v0x1098210_0 .net "b", 0 0, L_0x12c6370; alias, 1 drivers +v0x1098300_0 .net "b_", 0 0, L_0x12bbd80; alias, 1 drivers +v0x10983a0_0 .net "carryin", 0 0, L_0x12bbae0; alias, 1 drivers +v0x10984e0_0 .net "eq", 0 0, L_0x12bd090; 1 drivers +v0x10985a0_0 .net "lt", 0 0, L_0x12bd210; 1 drivers +v0x1098660_0 .net "out", 0 0, L_0x12bd480; 1 drivers +v0x1098720_0 .net "w0", 0 0, L_0x12bd370; 1 drivers +S_0x1098970 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x108b520; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12bcc70/d .functor OR 1, L_0x12bc770, L_0x1099bd0, C4<0>, C4<0>; +L_0x12bcc70 .delay 1 (30000,30000,30000) L_0x12bcc70/d; +v0x1099760_0 .net "a", 0 0, L_0x12c6100; alias, 1 drivers +v0x10998b0_0 .net "b", 0 0, L_0x12bbd80; alias, 1 drivers +v0x1099970_0 .net "c1", 0 0, L_0x12bc770; 1 drivers +v0x1099a10_0 .net "c2", 0 0, L_0x1099bd0; 1 drivers +v0x1099ae0_0 .net "carryin", 0 0, L_0x12bbae0; alias, 1 drivers +v0x1099c60_0 .net "carryout", 0 0, L_0x12bcc70; 1 drivers +v0x1099d00_0 .net "s1", 0 0, L_0x12bc6b0; 1 drivers +v0x1099da0_0 .net "sum", 0 0, L_0x12bc8d0; 1 drivers +S_0x1098bc0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1098970; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12bc6b0/d .functor XOR 1, L_0x12c6100, L_0x12bbd80, C4<0>, C4<0>; +L_0x12bc6b0 .delay 1 (30000,30000,30000) L_0x12bc6b0/d; +L_0x12bc770/d .functor AND 1, L_0x12c6100, L_0x12bbd80, C4<1>, C4<1>; +L_0x12bc770 .delay 1 (30000,30000,30000) L_0x12bc770/d; +v0x1098e20_0 .net "a", 0 0, L_0x12c6100; alias, 1 drivers +v0x1098ee0_0 .net "b", 0 0, L_0x12bbd80; alias, 1 drivers +v0x1098fa0_0 .net "carryout", 0 0, L_0x12bc770; alias, 1 drivers +v0x1099040_0 .net "sum", 0 0, L_0x12bc6b0; alias, 1 drivers +S_0x1099170 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1098970; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12bc8d0/d .functor XOR 1, L_0x12bc6b0, L_0x12bbae0, C4<0>, C4<0>; +L_0x12bc8d0 .delay 1 (30000,30000,30000) L_0x12bc8d0/d; +L_0x1099bd0/d .functor AND 1, L_0x12bc6b0, L_0x12bbae0, C4<1>, C4<1>; +L_0x1099bd0 .delay 1 (30000,30000,30000) L_0x1099bd0/d; +v0x10993d0_0 .net "a", 0 0, L_0x12bc6b0; alias, 1 drivers +v0x10994a0_0 .net "b", 0 0, L_0x12bbae0; alias, 1 drivers +v0x1099540_0 .net "carryout", 0 0, L_0x1099bd0; alias, 1 drivers +v0x1099610_0 .net "sum", 0 0, L_0x12bc8d0; alias, 1 drivers +S_0x109be30 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x108b250; + .timescale -9 -12; +L_0x2ac432884a88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884ad0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bc230/d .functor OR 1, L_0x2ac432884a88, L_0x2ac432884ad0, C4<0>, C4<0>; +L_0x12bc230 .delay 1 (30000,30000,30000) L_0x12bc230/d; +v0x109c020_0 .net/2u *"_s0", 0 0, L_0x2ac432884a88; 1 drivers +v0x109c100_0 .net/2u *"_s2", 0 0, L_0x2ac432884ad0; 1 drivers +S_0x109c1e0 .scope generate, "alu_slices[7]" "alu_slices[7]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x109c3f0 .param/l "i" 0 3 39, +C4<0111>; +S_0x109c4b0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x109c1e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12c6620/d .functor NOT 1, L_0x12d0a90, C4<0>, C4<0>, C4<0>; +L_0x12c6620 .delay 1 (10000,10000,10000) L_0x12c6620/d; +L_0x12c6730/d .functor NOT 1, L_0x12c6520, C4<0>, C4<0>, C4<0>; +L_0x12c6730 .delay 1 (10000,10000,10000) L_0x12c6730/d; +L_0x12c76e0/d .functor XOR 1, L_0x12d0a90, L_0x12c6520, C4<0>, C4<0>; +L_0x12c76e0 .delay 1 (30000,30000,30000) L_0x12c76e0/d; +L_0x2ac432884b18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884b60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c77a0/d .functor OR 1, L_0x2ac432884b18, L_0x2ac432884b60, C4<0>, C4<0>; +L_0x12c77a0 .delay 1 (30000,30000,30000) L_0x12c77a0/d; +L_0x2ac432884ba8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884bf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c7f40/d .functor OR 1, L_0x2ac432884ba8, L_0x2ac432884bf0, C4<0>, C4<0>; +L_0x12c7f40 .delay 1 (30000,30000,30000) L_0x12c7f40/d; +L_0x12c8140/d .functor AND 1, L_0x12d0a90, L_0x12c6520, C4<1>, C4<1>; +L_0x12c8140 .delay 1 (30000,30000,30000) L_0x12c8140/d; +L_0x2ac432884c38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884c80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c8200/d .functor OR 1, L_0x2ac432884c38, L_0x2ac432884c80, C4<0>, C4<0>; +L_0x12c8200 .delay 1 (30000,30000,30000) L_0x12c8200/d; +L_0x12c8400/d .functor NAND 1, L_0x12d0a90, L_0x12c6520, C4<1>, C4<1>; +L_0x12c8400 .delay 1 (20000,20000,20000) L_0x12c8400/d; +L_0x2ac432884cc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884d10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c8510/d .functor OR 1, L_0x2ac432884cc8, L_0x2ac432884d10, C4<0>, C4<0>; +L_0x12c8510 .delay 1 (30000,30000,30000) L_0x12c8510/d; +L_0x12c86c0/d .functor NOR 1, L_0x12d0a90, L_0x12c6520, C4<0>, C4<0>; +L_0x12c86c0 .delay 1 (20000,20000,20000) L_0x12c86c0/d; +L_0x2ac432884d58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884da0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c8990/d .functor OR 1, L_0x2ac432884d58, L_0x2ac432884da0, C4<0>, C4<0>; +L_0x12c8990 .delay 1 (30000,30000,30000) L_0x12c8990/d; +L_0x12c8d90/d .functor OR 1, L_0x12d0a90, L_0x12c6520, C4<0>, C4<0>; +L_0x12c8d90 .delay 1 (30000,30000,30000) L_0x12c8d90/d; +L_0x2ac432884de8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884e30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c9230/d .functor OR 1, L_0x2ac432884de8, L_0x2ac432884e30, C4<0>, C4<0>; +L_0x12c9230 .delay 1 (30000,30000,30000) L_0x12c9230/d; +L_0x12d0990/d .functor NOT 1, L_0x12ccbf0, C4<0>, C4<0>, C4<0>; +L_0x12d0990 .delay 1 (10000,10000,10000) L_0x12d0990/d; +v0x10aabe0_0 .net "A", 0 0, L_0x12d0a90; 1 drivers +v0x10aaca0_0 .net "A_", 0 0, L_0x12c6620; 1 drivers +v0x10aad60_0 .net "B", 0 0, L_0x12c6520; 1 drivers +v0x10aae30_0 .net "B_", 0 0, L_0x12c6730; 1 drivers +v0x10aaed0_0 .net *"_s11", 0 0, L_0x12c77a0; 1 drivers +v0x10aafc0_0 .net/2s *"_s13", 0 0, L_0x2ac432884b18; 1 drivers +v0x10ab080_0 .net/2s *"_s15", 0 0, L_0x2ac432884b60; 1 drivers +v0x10ab160_0 .net *"_s19", 0 0, L_0x12c7f40; 1 drivers +v0x10ab240_0 .net/2s *"_s21", 0 0, L_0x2ac432884ba8; 1 drivers +v0x10ab3b0_0 .net/2s *"_s23", 0 0, L_0x2ac432884bf0; 1 drivers +v0x10ab490_0 .net *"_s25", 0 0, L_0x12c8140; 1 drivers +v0x10ab570_0 .net *"_s28", 0 0, L_0x12c8200; 1 drivers +v0x10ab650_0 .net/2s *"_s30", 0 0, L_0x2ac432884c38; 1 drivers +v0x10ab730_0 .net/2s *"_s32", 0 0, L_0x2ac432884c80; 1 drivers +v0x10ab810_0 .net *"_s34", 0 0, L_0x12c8400; 1 drivers +v0x10ab8f0_0 .net *"_s37", 0 0, L_0x12c8510; 1 drivers +v0x10ab9d0_0 .net/2s *"_s39", 0 0, L_0x2ac432884cc8; 1 drivers +v0x10abb80_0 .net/2s *"_s41", 0 0, L_0x2ac432884d10; 1 drivers +v0x10abc20_0 .net *"_s43", 0 0, L_0x12c86c0; 1 drivers +v0x10abd00_0 .net *"_s46", 0 0, L_0x12c8990; 1 drivers +v0x10abde0_0 .net/2s *"_s48", 0 0, L_0x2ac432884d58; 1 drivers +v0x10abec0_0 .net/2s *"_s50", 0 0, L_0x2ac432884da0; 1 drivers +v0x10abfa0_0 .net *"_s52", 0 0, L_0x12c8d90; 1 drivers +v0x10ac080_0 .net *"_s56", 0 0, L_0x12c9230; 1 drivers +v0x10ac160_0 .net/2s *"_s59", 0 0, L_0x2ac432884de8; 1 drivers +v0x10ac240_0 .net/2s *"_s61", 0 0, L_0x2ac432884e30; 1 drivers +v0x10ac320_0 .net *"_s8", 0 0, L_0x12c76e0; 1 drivers +v0x10ac400_0 .net "carryin", 0 0, L_0x12d0cb0; 1 drivers +v0x10ac4a0_0 .net "carryout", 0 0, L_0x12d0630; 1 drivers +v0x10ac540_0 .net "carryouts", 7 0, L_0x12c8ea0; 1 drivers +v0x10ac650_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x10ac710_0 .net "result", 0 0, L_0x12ccbf0; 1 drivers +v0x10ac800_0 .net "results", 7 0, L_0x12c8b60; 1 drivers +v0x10abae0_0 .net "zero", 0 0, L_0x12d0990; 1 drivers +LS_0x12c8b60_0_0 .concat8 [ 1 1 1 1], L_0x12c6c50, L_0x12c7230, L_0x12c76e0, L_0x12c7f40; +LS_0x12c8b60_0_4 .concat8 [ 1 1 1 1], L_0x12c8140, L_0x12c8400, L_0x12c86c0, L_0x12c8d90; +L_0x12c8b60 .concat8 [ 4 4 0 0], LS_0x12c8b60_0_0, LS_0x12c8b60_0_4; +LS_0x12c8ea0_0_0 .concat8 [ 1 1 1 1], L_0x12c6f00, L_0x12c7580, L_0x12c77a0, L_0x12c7d90; +LS_0x12c8ea0_0_4 .concat8 [ 1 1 1 1], L_0x12c8200, L_0x12c8510, L_0x12c8990, L_0x12c9230; +L_0x12c8ea0 .concat8 [ 4 4 0 0], LS_0x12c8ea0_0_0, LS_0x12c8ea0_0_4; +S_0x109c730 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x109c4b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12c6f00/d .functor OR 1, L_0x12c69e0, L_0x12c6da0, C4<0>, C4<0>; +L_0x12c6f00 .delay 1 (30000,30000,30000) L_0x12c6f00/d; +v0x109d560_0 .net "a", 0 0, L_0x12d0a90; alias, 1 drivers +v0x109d620_0 .net "b", 0 0, L_0x12c6520; alias, 1 drivers +v0x109d6f0_0 .net "c1", 0 0, L_0x12c69e0; 1 drivers +v0x109d7f0_0 .net "c2", 0 0, L_0x12c6da0; 1 drivers +v0x109d8c0_0 .net "carryin", 0 0, L_0x12d0cb0; alias, 1 drivers +v0x109d9b0_0 .net "carryout", 0 0, L_0x12c6f00; 1 drivers +v0x109da50_0 .net "s1", 0 0, L_0x12c6920; 1 drivers +v0x109db40_0 .net "sum", 0 0, L_0x12c6c50; 1 drivers +S_0x109c9a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x109c730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12c6920/d .functor XOR 1, L_0x12d0a90, L_0x12c6520, C4<0>, C4<0>; +L_0x12c6920 .delay 1 (30000,30000,30000) L_0x12c6920/d; +L_0x12c69e0/d .functor AND 1, L_0x12d0a90, L_0x12c6520, C4<1>, C4<1>; +L_0x12c69e0 .delay 1 (30000,30000,30000) L_0x12c69e0/d; +v0x109cc00_0 .net "a", 0 0, L_0x12d0a90; alias, 1 drivers +v0x109cce0_0 .net "b", 0 0, L_0x12c6520; alias, 1 drivers +v0x109cda0_0 .net "carryout", 0 0, L_0x12c69e0; alias, 1 drivers +v0x109ce40_0 .net "sum", 0 0, L_0x12c6920; alias, 1 drivers +S_0x109cf80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x109c730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12c6c50/d .functor XOR 1, L_0x12c6920, L_0x12d0cb0, C4<0>, C4<0>; +L_0x12c6c50 .delay 1 (30000,30000,30000) L_0x12c6c50/d; +L_0x12c6da0/d .functor AND 1, L_0x12c6920, L_0x12d0cb0, C4<1>, C4<1>; +L_0x12c6da0 .delay 1 (30000,30000,30000) L_0x12c6da0/d; +v0x109d1e0_0 .net "a", 0 0, L_0x12c6920; alias, 1 drivers +v0x109d280_0 .net "b", 0 0, L_0x12d0cb0; alias, 1 drivers +v0x109d320_0 .net "carryout", 0 0, L_0x12c6da0; alias, 1 drivers +v0x109d3f0_0 .net "sum", 0 0, L_0x12c6c50; alias, 1 drivers +S_0x109dc10 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x109c4b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10a3000_0 .net "ands", 7 0, L_0x12ce630; 1 drivers +v0x10a3110_0 .net "in", 7 0, L_0x12c8ea0; alias, 1 drivers +v0x10a31d0_0 .net "out", 0 0, L_0x12d0630; alias, 1 drivers +v0x10a32a0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x109de30 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x109dc10; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10a0560_0 .net "A", 7 0, L_0x12c8ea0; alias, 1 drivers +v0x10a0660_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10a0720_0 .net *"_s0", 0 0, L_0x12ccf50; 1 drivers +v0x10a07e0_0 .net *"_s12", 0 0, L_0x12cd8c0; 1 drivers +v0x10a08c0_0 .net *"_s16", 0 0, L_0x12cdc20; 1 drivers +v0x10a09f0_0 .net *"_s20", 0 0, L_0x12cdff0; 1 drivers +v0x10a0ad0_0 .net *"_s24", 0 0, L_0x12ce320; 1 drivers +v0x10a0bb0_0 .net *"_s28", 0 0, L_0x12ce2b0; 1 drivers +v0x10a0c90_0 .net *"_s4", 0 0, L_0x12cd2a0; 1 drivers +v0x10a0e00_0 .net *"_s8", 0 0, L_0x12cd5b0; 1 drivers +v0x10a0ee0_0 .net "out", 7 0, L_0x12ce630; alias, 1 drivers +L_0x12cd010 .part L_0x12c8ea0, 0, 1; +L_0x12cd200 .part v0x127a150_0, 0, 1; +L_0x12cd360 .part L_0x12c8ea0, 1, 1; +L_0x12cd4c0 .part v0x127a150_0, 1, 1; +L_0x12cd670 .part L_0x12c8ea0, 2, 1; +L_0x12cd7d0 .part v0x127a150_0, 2, 1; +L_0x12cd980 .part L_0x12c8ea0, 3, 1; +L_0x12cdae0 .part v0x127a150_0, 3, 1; +L_0x12cdce0 .part L_0x12c8ea0, 4, 1; +L_0x12cdf50 .part v0x127a150_0, 4, 1; +L_0x12ce060 .part L_0x12c8ea0, 5, 1; +L_0x12ce1c0 .part v0x127a150_0, 5, 1; +L_0x12ce3e0 .part L_0x12c8ea0, 6, 1; +L_0x12ce540 .part v0x127a150_0, 6, 1; +LS_0x12ce630_0_0 .concat8 [ 1 1 1 1], L_0x12ccf50, L_0x12cd2a0, L_0x12cd5b0, L_0x12cd8c0; +LS_0x12ce630_0_4 .concat8 [ 1 1 1 1], L_0x12cdc20, L_0x12cdff0, L_0x12ce320, L_0x12ce2b0; +L_0x12ce630 .concat8 [ 4 4 0 0], LS_0x12ce630_0_0, LS_0x12ce630_0_4; +L_0x12ce9f0 .part L_0x12c8ea0, 7, 1; +L_0x12cebe0 .part v0x127a150_0, 7, 1; +S_0x109e090 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109e2a0 .param/l "i" 0 4 54, +C4<00>; +L_0x12ccf50/d .functor AND 1, L_0x12cd010, L_0x12cd200, C4<1>, C4<1>; +L_0x12ccf50 .delay 1 (30000,30000,30000) L_0x12ccf50/d; +v0x109e380_0 .net *"_s0", 0 0, L_0x12cd010; 1 drivers +v0x109e460_0 .net *"_s1", 0 0, L_0x12cd200; 1 drivers +S_0x109e540 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109e750 .param/l "i" 0 4 54, +C4<01>; +L_0x12cd2a0/d .functor AND 1, L_0x12cd360, L_0x12cd4c0, C4<1>, C4<1>; +L_0x12cd2a0 .delay 1 (30000,30000,30000) L_0x12cd2a0/d; +v0x109e810_0 .net *"_s0", 0 0, L_0x12cd360; 1 drivers +v0x109e8f0_0 .net *"_s1", 0 0, L_0x12cd4c0; 1 drivers +S_0x109e9d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109ebe0 .param/l "i" 0 4 54, +C4<010>; +L_0x12cd5b0/d .functor AND 1, L_0x12cd670, L_0x12cd7d0, C4<1>, C4<1>; +L_0x12cd5b0 .delay 1 (30000,30000,30000) L_0x12cd5b0/d; +v0x109ec80_0 .net *"_s0", 0 0, L_0x12cd670; 1 drivers +v0x109ed60_0 .net *"_s1", 0 0, L_0x12cd7d0; 1 drivers +S_0x109ee40 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109f050 .param/l "i" 0 4 54, +C4<011>; +L_0x12cd8c0/d .functor AND 1, L_0x12cd980, L_0x12cdae0, C4<1>, C4<1>; +L_0x12cd8c0 .delay 1 (30000,30000,30000) L_0x12cd8c0/d; +v0x109f110_0 .net *"_s0", 0 0, L_0x12cd980; 1 drivers +v0x109f1f0_0 .net *"_s1", 0 0, L_0x12cdae0; 1 drivers +S_0x109f2d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109f530 .param/l "i" 0 4 54, +C4<0100>; +L_0x12cdc20/d .functor AND 1, L_0x12cdce0, L_0x12cdf50, C4<1>, C4<1>; +L_0x12cdc20 .delay 1 (30000,30000,30000) L_0x12cdc20/d; +v0x109f5f0_0 .net *"_s0", 0 0, L_0x12cdce0; 1 drivers +v0x109f6d0_0 .net *"_s1", 0 0, L_0x12cdf50; 1 drivers +S_0x109f7b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109f9c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12cdff0/d .functor AND 1, L_0x12ce060, L_0x12ce1c0, C4<1>, C4<1>; +L_0x12cdff0 .delay 1 (30000,30000,30000) L_0x12cdff0/d; +v0x109fa80_0 .net *"_s0", 0 0, L_0x12ce060; 1 drivers +v0x109fb60_0 .net *"_s1", 0 0, L_0x12ce1c0; 1 drivers +S_0x109fc40 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x109fe50 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ce320/d .functor AND 1, L_0x12ce3e0, L_0x12ce540, C4<1>, C4<1>; +L_0x12ce320 .delay 1 (30000,30000,30000) L_0x12ce320/d; +v0x109ff10_0 .net *"_s0", 0 0, L_0x12ce3e0; 1 drivers +v0x109fff0_0 .net *"_s1", 0 0, L_0x12ce540; 1 drivers +S_0x10a00d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x109de30; + .timescale -9 -12; +P_0x10a02e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ce2b0/d .functor AND 1, L_0x12ce9f0, L_0x12cebe0, C4<1>, C4<1>; +L_0x12ce2b0 .delay 1 (30000,30000,30000) L_0x12ce2b0/d; +v0x10a03a0_0 .net *"_s0", 0 0, L_0x12ce9f0; 1 drivers +v0x10a0480_0 .net *"_s1", 0 0, L_0x12cebe0; 1 drivers +S_0x10a1040 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x109dc10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12d0630/d .functor OR 1, L_0x12d06f0, L_0x12d08a0, C4<0>, C4<0>; +L_0x12d0630 .delay 1 (30000,30000,30000) L_0x12d0630/d; +v0x10a2b90_0 .net *"_s10", 0 0, L_0x12d06f0; 1 drivers +v0x10a2c70_0 .net *"_s12", 0 0, L_0x12d08a0; 1 drivers +v0x10a2d50_0 .net "in", 7 0, L_0x12ce630; alias, 1 drivers +v0x10a2e20_0 .net "ors", 1 0, L_0x12d0450; 1 drivers +v0x10a2ee0_0 .net "out", 0 0, L_0x12d0630; alias, 1 drivers +L_0x12cf820 .part L_0x12ce630, 0, 4; +L_0x12d0450 .concat8 [ 1 1 0 0], L_0x12cf510, L_0x12d0140; +L_0x12d0590 .part L_0x12ce630, 4, 4; +L_0x12d06f0 .part L_0x12d0450, 0, 1; +L_0x12d08a0 .part L_0x12d0450, 1, 1; +S_0x10a1200 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10a1040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12cecd0/d .functor OR 1, L_0x12ced90, L_0x12ceef0, C4<0>, C4<0>; +L_0x12cecd0 .delay 1 (30000,30000,30000) L_0x12cecd0/d; +L_0x12cf120/d .functor OR 1, L_0x12cf230, L_0x12cf390, C4<0>, C4<0>; +L_0x12cf120 .delay 1 (30000,30000,30000) L_0x12cf120/d; +L_0x12cf510/d .functor OR 1, L_0x12cf580, L_0x12cf730, C4<0>, C4<0>; +L_0x12cf510 .delay 1 (30000,30000,30000) L_0x12cf510/d; +v0x10a1450_0 .net *"_s0", 0 0, L_0x12cecd0; 1 drivers +v0x10a1550_0 .net *"_s10", 0 0, L_0x12cf230; 1 drivers +v0x10a1630_0 .net *"_s12", 0 0, L_0x12cf390; 1 drivers +v0x10a16f0_0 .net *"_s14", 0 0, L_0x12cf580; 1 drivers +v0x10a17d0_0 .net *"_s16", 0 0, L_0x12cf730; 1 drivers +v0x10a1900_0 .net *"_s3", 0 0, L_0x12ced90; 1 drivers +v0x10a19e0_0 .net *"_s5", 0 0, L_0x12ceef0; 1 drivers +v0x10a1ac0_0 .net *"_s6", 0 0, L_0x12cf120; 1 drivers +v0x10a1ba0_0 .net "in", 3 0, L_0x12cf820; 1 drivers +v0x10a1d10_0 .net "ors", 1 0, L_0x12cf030; 1 drivers +v0x10a1df0_0 .net "out", 0 0, L_0x12cf510; 1 drivers +L_0x12ced90 .part L_0x12cf820, 0, 1; +L_0x12ceef0 .part L_0x12cf820, 1, 1; +L_0x12cf030 .concat8 [ 1 1 0 0], L_0x12cecd0, L_0x12cf120; +L_0x12cf230 .part L_0x12cf820, 2, 1; +L_0x12cf390 .part L_0x12cf820, 3, 1; +L_0x12cf580 .part L_0x12cf030, 0, 1; +L_0x12cf730 .part L_0x12cf030, 1, 1; +S_0x10a1f10 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10a1040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12cf950/d .functor OR 1, L_0x12cf9c0, L_0x12cfb20, C4<0>, C4<0>; +L_0x12cf950 .delay 1 (30000,30000,30000) L_0x12cf950/d; +L_0x12cfd50/d .functor OR 1, L_0x12cfe60, L_0x12cffc0, C4<0>, C4<0>; +L_0x12cfd50 .delay 1 (30000,30000,30000) L_0x12cfd50/d; +L_0x12d0140/d .functor OR 1, L_0x12d01b0, L_0x12d0360, C4<0>, C4<0>; +L_0x12d0140 .delay 1 (30000,30000,30000) L_0x12d0140/d; +v0x10a20d0_0 .net *"_s0", 0 0, L_0x12cf950; 1 drivers +v0x10a21d0_0 .net *"_s10", 0 0, L_0x12cfe60; 1 drivers +v0x10a22b0_0 .net *"_s12", 0 0, L_0x12cffc0; 1 drivers +v0x10a2370_0 .net *"_s14", 0 0, L_0x12d01b0; 1 drivers +v0x10a2450_0 .net *"_s16", 0 0, L_0x12d0360; 1 drivers +v0x10a2580_0 .net *"_s3", 0 0, L_0x12cf9c0; 1 drivers +v0x10a2660_0 .net *"_s5", 0 0, L_0x12cfb20; 1 drivers +v0x10a2740_0 .net *"_s6", 0 0, L_0x12cfd50; 1 drivers +v0x10a2820_0 .net "in", 3 0, L_0x12d0590; 1 drivers +v0x10a2990_0 .net "ors", 1 0, L_0x12cfc60; 1 drivers +v0x10a2a70_0 .net "out", 0 0, L_0x12d0140; 1 drivers +L_0x12cf9c0 .part L_0x12d0590, 0, 1; +L_0x12cfb20 .part L_0x12d0590, 1, 1; +L_0x12cfc60 .concat8 [ 1 1 0 0], L_0x12cf950, L_0x12cfd50; +L_0x12cfe60 .part L_0x12d0590, 2, 1; +L_0x12cffc0 .part L_0x12d0590, 3, 1; +L_0x12d01b0 .part L_0x12cfc60, 0, 1; +L_0x12d0360 .part L_0x12cfc60, 1, 1; +S_0x10a3380 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x109c4b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10a87b0_0 .net "ands", 7 0, L_0x12cabf0; 1 drivers +v0x10a88c0_0 .net "in", 7 0, L_0x12c8b60; alias, 1 drivers +v0x10a8980_0 .net "out", 0 0, L_0x12ccbf0; alias, 1 drivers +v0x10a8a50_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10a35d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10a3380; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10a5d10_0 .net "A", 7 0, L_0x12c8b60; alias, 1 drivers +v0x10a5e10_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10a5ed0_0 .net *"_s0", 0 0, L_0x12c93e0; 1 drivers +v0x10a5f90_0 .net *"_s12", 0 0, L_0x12c9da0; 1 drivers +v0x10a6070_0 .net *"_s16", 0 0, L_0x12ca100; 1 drivers +v0x10a61a0_0 .net *"_s20", 0 0, L_0x12ca530; 1 drivers +v0x10a6280_0 .net *"_s24", 0 0, L_0x12ca860; 1 drivers +v0x10a6360_0 .net *"_s28", 0 0, L_0x12ca7f0; 1 drivers +v0x10a6440_0 .net *"_s4", 0 0, L_0x12c9780; 1 drivers +v0x10a65b0_0 .net *"_s8", 0 0, L_0x12c9a90; 1 drivers +v0x10a6690_0 .net "out", 7 0, L_0x12cabf0; alias, 1 drivers +L_0x12c94f0 .part L_0x12c8b60, 0, 1; +L_0x12c96e0 .part v0x127a150_0, 0, 1; +L_0x12c9840 .part L_0x12c8b60, 1, 1; +L_0x12c99a0 .part v0x127a150_0, 1, 1; +L_0x12c9b50 .part L_0x12c8b60, 2, 1; +L_0x12c9cb0 .part v0x127a150_0, 2, 1; +L_0x12c9e60 .part L_0x12c8b60, 3, 1; +L_0x12c9fc0 .part v0x127a150_0, 3, 1; +L_0x12ca1c0 .part L_0x12c8b60, 4, 1; +L_0x12ca430 .part v0x127a150_0, 4, 1; +L_0x12ca5a0 .part L_0x12c8b60, 5, 1; +L_0x12ca700 .part v0x127a150_0, 5, 1; +L_0x12ca920 .part L_0x12c8b60, 6, 1; +L_0x12caa80 .part v0x127a150_0, 6, 1; +LS_0x12cabf0_0_0 .concat8 [ 1 1 1 1], L_0x12c93e0, L_0x12c9780, L_0x12c9a90, L_0x12c9da0; +LS_0x12cabf0_0_4 .concat8 [ 1 1 1 1], L_0x12ca100, L_0x12ca530, L_0x12ca860, L_0x12ca7f0; +L_0x12cabf0 .concat8 [ 4 4 0 0], LS_0x12cabf0_0_0, LS_0x12cabf0_0_4; +L_0x12cafb0 .part L_0x12c8b60, 7, 1; +L_0x12cb1a0 .part v0x127a150_0, 7, 1; +S_0x10a3810 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a3a20 .param/l "i" 0 4 54, +C4<00>; +L_0x12c93e0/d .functor AND 1, L_0x12c94f0, L_0x12c96e0, C4<1>, C4<1>; +L_0x12c93e0 .delay 1 (30000,30000,30000) L_0x12c93e0/d; +v0x10a3b00_0 .net *"_s0", 0 0, L_0x12c94f0; 1 drivers +v0x10a3be0_0 .net *"_s1", 0 0, L_0x12c96e0; 1 drivers +S_0x10a3cc0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a3ed0 .param/l "i" 0 4 54, +C4<01>; +L_0x12c9780/d .functor AND 1, L_0x12c9840, L_0x12c99a0, C4<1>, C4<1>; +L_0x12c9780 .delay 1 (30000,30000,30000) L_0x12c9780/d; +v0x10a3f90_0 .net *"_s0", 0 0, L_0x12c9840; 1 drivers +v0x10a4070_0 .net *"_s1", 0 0, L_0x12c99a0; 1 drivers +S_0x10a4150 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a4390 .param/l "i" 0 4 54, +C4<010>; +L_0x12c9a90/d .functor AND 1, L_0x12c9b50, L_0x12c9cb0, C4<1>, C4<1>; +L_0x12c9a90 .delay 1 (30000,30000,30000) L_0x12c9a90/d; +v0x10a4430_0 .net *"_s0", 0 0, L_0x12c9b50; 1 drivers +v0x10a4510_0 .net *"_s1", 0 0, L_0x12c9cb0; 1 drivers +S_0x10a45f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a4800 .param/l "i" 0 4 54, +C4<011>; +L_0x12c9da0/d .functor AND 1, L_0x12c9e60, L_0x12c9fc0, C4<1>, C4<1>; +L_0x12c9da0 .delay 1 (30000,30000,30000) L_0x12c9da0/d; +v0x10a48c0_0 .net *"_s0", 0 0, L_0x12c9e60; 1 drivers +v0x10a49a0_0 .net *"_s1", 0 0, L_0x12c9fc0; 1 drivers +S_0x10a4a80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a4ce0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12ca100/d .functor AND 1, L_0x12ca1c0, L_0x12ca430, C4<1>, C4<1>; +L_0x12ca100 .delay 1 (30000,30000,30000) L_0x12ca100/d; +v0x10a4da0_0 .net *"_s0", 0 0, L_0x12ca1c0; 1 drivers +v0x10a4e80_0 .net *"_s1", 0 0, L_0x12ca430; 1 drivers +S_0x10a4f60 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a5170 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ca530/d .functor AND 1, L_0x12ca5a0, L_0x12ca700, C4<1>, C4<1>; +L_0x12ca530 .delay 1 (30000,30000,30000) L_0x12ca530/d; +v0x10a5230_0 .net *"_s0", 0 0, L_0x12ca5a0; 1 drivers +v0x10a5310_0 .net *"_s1", 0 0, L_0x12ca700; 1 drivers +S_0x10a53f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a5600 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ca860/d .functor AND 1, L_0x12ca920, L_0x12caa80, C4<1>, C4<1>; +L_0x12ca860 .delay 1 (30000,30000,30000) L_0x12ca860/d; +v0x10a56c0_0 .net *"_s0", 0 0, L_0x12ca920; 1 drivers +v0x10a57a0_0 .net *"_s1", 0 0, L_0x12caa80; 1 drivers +S_0x10a5880 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10a35d0; + .timescale -9 -12; +P_0x10a5a90 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ca7f0/d .functor AND 1, L_0x12cafb0, L_0x12cb1a0, C4<1>, C4<1>; +L_0x12ca7f0 .delay 1 (30000,30000,30000) L_0x12ca7f0/d; +v0x10a5b50_0 .net *"_s0", 0 0, L_0x12cafb0; 1 drivers +v0x10a5c30_0 .net *"_s1", 0 0, L_0x12cb1a0; 1 drivers +S_0x10a67f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10a3380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12ccbf0/d .functor OR 1, L_0x12cccb0, L_0x12cce60, C4<0>, C4<0>; +L_0x12ccbf0 .delay 1 (30000,30000,30000) L_0x12ccbf0/d; +v0x10a8340_0 .net *"_s10", 0 0, L_0x12cccb0; 1 drivers +v0x10a8420_0 .net *"_s12", 0 0, L_0x12cce60; 1 drivers +v0x10a8500_0 .net "in", 7 0, L_0x12cabf0; alias, 1 drivers +v0x10a85d0_0 .net "ors", 1 0, L_0x12cca10; 1 drivers +v0x10a8690_0 .net "out", 0 0, L_0x12ccbf0; alias, 1 drivers +L_0x12cbde0 .part L_0x12cabf0, 0, 4; +L_0x12cca10 .concat8 [ 1 1 0 0], L_0x12cbad0, L_0x12cc700; +L_0x12ccb50 .part L_0x12cabf0, 4, 4; +L_0x12cccb0 .part L_0x12cca10, 0, 1; +L_0x12cce60 .part L_0x12cca10, 1, 1; +S_0x10a69b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10a67f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12cb290/d .functor OR 1, L_0x12cb350, L_0x12cb4b0, C4<0>, C4<0>; +L_0x12cb290 .delay 1 (30000,30000,30000) L_0x12cb290/d; +L_0x12cb6e0/d .functor OR 1, L_0x12cb7f0, L_0x12cb950, C4<0>, C4<0>; +L_0x12cb6e0 .delay 1 (30000,30000,30000) L_0x12cb6e0/d; +L_0x12cbad0/d .functor OR 1, L_0x12cbb40, L_0x12cbcf0, C4<0>, C4<0>; +L_0x12cbad0 .delay 1 (30000,30000,30000) L_0x12cbad0/d; +v0x10a6c00_0 .net *"_s0", 0 0, L_0x12cb290; 1 drivers +v0x10a6d00_0 .net *"_s10", 0 0, L_0x12cb7f0; 1 drivers +v0x10a6de0_0 .net *"_s12", 0 0, L_0x12cb950; 1 drivers +v0x10a6ea0_0 .net *"_s14", 0 0, L_0x12cbb40; 1 drivers +v0x10a6f80_0 .net *"_s16", 0 0, L_0x12cbcf0; 1 drivers +v0x10a70b0_0 .net *"_s3", 0 0, L_0x12cb350; 1 drivers +v0x10a7190_0 .net *"_s5", 0 0, L_0x12cb4b0; 1 drivers +v0x10a7270_0 .net *"_s6", 0 0, L_0x12cb6e0; 1 drivers +v0x10a7350_0 .net "in", 3 0, L_0x12cbde0; 1 drivers +v0x10a74c0_0 .net "ors", 1 0, L_0x12cb5f0; 1 drivers +v0x10a75a0_0 .net "out", 0 0, L_0x12cbad0; 1 drivers +L_0x12cb350 .part L_0x12cbde0, 0, 1; +L_0x12cb4b0 .part L_0x12cbde0, 1, 1; +L_0x12cb5f0 .concat8 [ 1 1 0 0], L_0x12cb290, L_0x12cb6e0; +L_0x12cb7f0 .part L_0x12cbde0, 2, 1; +L_0x12cb950 .part L_0x12cbde0, 3, 1; +L_0x12cbb40 .part L_0x12cb5f0, 0, 1; +L_0x12cbcf0 .part L_0x12cb5f0, 1, 1; +S_0x10a76c0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10a67f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12cbf10/d .functor OR 1, L_0x12cbf80, L_0x12cc0e0, C4<0>, C4<0>; +L_0x12cbf10 .delay 1 (30000,30000,30000) L_0x12cbf10/d; +L_0x12cc310/d .functor OR 1, L_0x12cc420, L_0x12cc580, C4<0>, C4<0>; +L_0x12cc310 .delay 1 (30000,30000,30000) L_0x12cc310/d; +L_0x12cc700/d .functor OR 1, L_0x12cc770, L_0x12cc920, C4<0>, C4<0>; +L_0x12cc700 .delay 1 (30000,30000,30000) L_0x12cc700/d; +v0x10a7880_0 .net *"_s0", 0 0, L_0x12cbf10; 1 drivers +v0x10a7980_0 .net *"_s10", 0 0, L_0x12cc420; 1 drivers +v0x10a7a60_0 .net *"_s12", 0 0, L_0x12cc580; 1 drivers +v0x10a7b20_0 .net *"_s14", 0 0, L_0x12cc770; 1 drivers +v0x10a7c00_0 .net *"_s16", 0 0, L_0x12cc920; 1 drivers +v0x10a7d30_0 .net *"_s3", 0 0, L_0x12cbf80; 1 drivers +v0x10a7e10_0 .net *"_s5", 0 0, L_0x12cc0e0; 1 drivers +v0x10a7ef0_0 .net *"_s6", 0 0, L_0x12cc310; 1 drivers +v0x10a7fd0_0 .net "in", 3 0, L_0x12ccb50; 1 drivers +v0x10a8140_0 .net "ors", 1 0, L_0x12cc220; 1 drivers +v0x10a8220_0 .net "out", 0 0, L_0x12cc700; 1 drivers +L_0x12cbf80 .part L_0x12ccb50, 0, 1; +L_0x12cc0e0 .part L_0x12ccb50, 1, 1; +L_0x12cc220 .concat8 [ 1 1 0 0], L_0x12cbf10, L_0x12cc310; +L_0x12cc420 .part L_0x12ccb50, 2, 1; +L_0x12cc580 .part L_0x12ccb50, 3, 1; +L_0x12cc770 .part L_0x12cc220, 0, 1; +L_0x12cc920 .part L_0x12cc220, 1, 1; +S_0x10a8b30 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x109c4b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12c79a0/d .functor XNOR 1, L_0x12d0a90, L_0x12c6520, C4<0>, C4<0>; +L_0x12c79a0 .delay 1 (20000,20000,20000) L_0x12c79a0/d; +L_0x12c7b20/d .functor AND 1, L_0x12d0a90, L_0x12c6730, C4<1>, C4<1>; +L_0x12c7b20 .delay 1 (30000,30000,30000) L_0x12c7b20/d; +L_0x12c7c80/d .functor AND 1, L_0x12c79a0, L_0x12d0cb0, C4<1>, C4<1>; +L_0x12c7c80 .delay 1 (30000,30000,30000) L_0x12c7c80/d; +L_0x12c7d90/d .functor OR 1, L_0x12c7c80, L_0x12c7b20, C4<0>, C4<0>; +L_0x12c7d90 .delay 1 (30000,30000,30000) L_0x12c7d90/d; +v0x10a8de0_0 .net "a", 0 0, L_0x12d0a90; alias, 1 drivers +v0x10a8ed0_0 .net "a_", 0 0, L_0x12c6620; alias, 1 drivers +v0x10a8f90_0 .net "b", 0 0, L_0x12c6520; alias, 1 drivers +v0x10a9080_0 .net "b_", 0 0, L_0x12c6730; alias, 1 drivers +v0x10a9120_0 .net "carryin", 0 0, L_0x12d0cb0; alias, 1 drivers +v0x10a9260_0 .net "eq", 0 0, L_0x12c79a0; 1 drivers +v0x10a9320_0 .net "lt", 0 0, L_0x12c7b20; 1 drivers +v0x10a93e0_0 .net "out", 0 0, L_0x12c7d90; 1 drivers +v0x10a94a0_0 .net "w0", 0 0, L_0x12c7c80; 1 drivers +S_0x10a96f0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x109c4b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12c7580/d .functor OR 1, L_0x12c7120, L_0x10aa950, C4<0>, C4<0>; +L_0x12c7580 .delay 1 (30000,30000,30000) L_0x12c7580/d; +v0x10aa4e0_0 .net "a", 0 0, L_0x12d0a90; alias, 1 drivers +v0x10aa630_0 .net "b", 0 0, L_0x12c6730; alias, 1 drivers +v0x10aa6f0_0 .net "c1", 0 0, L_0x12c7120; 1 drivers +v0x10aa790_0 .net "c2", 0 0, L_0x10aa950; 1 drivers +v0x10aa860_0 .net "carryin", 0 0, L_0x12d0cb0; alias, 1 drivers +v0x10aa9e0_0 .net "carryout", 0 0, L_0x12c7580; 1 drivers +v0x10aaa80_0 .net "s1", 0 0, L_0x12c6fc0; 1 drivers +v0x10aab20_0 .net "sum", 0 0, L_0x12c7230; 1 drivers +S_0x10a9940 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10a96f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12c6fc0/d .functor XOR 1, L_0x12d0a90, L_0x12c6730, C4<0>, C4<0>; +L_0x12c6fc0 .delay 1 (30000,30000,30000) L_0x12c6fc0/d; +L_0x12c7120/d .functor AND 1, L_0x12d0a90, L_0x12c6730, C4<1>, C4<1>; +L_0x12c7120 .delay 1 (30000,30000,30000) L_0x12c7120/d; +v0x10a9ba0_0 .net "a", 0 0, L_0x12d0a90; alias, 1 drivers +v0x10a9c60_0 .net "b", 0 0, L_0x12c6730; alias, 1 drivers +v0x10a9d20_0 .net "carryout", 0 0, L_0x12c7120; alias, 1 drivers +v0x10a9dc0_0 .net "sum", 0 0, L_0x12c6fc0; alias, 1 drivers +S_0x10a9ef0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10a96f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12c7230/d .functor XOR 1, L_0x12c6fc0, L_0x12d0cb0, C4<0>, C4<0>; +L_0x12c7230 .delay 1 (30000,30000,30000) L_0x12c7230/d; +L_0x10aa950/d .functor AND 1, L_0x12c6fc0, L_0x12d0cb0, C4<1>, C4<1>; +L_0x10aa950 .delay 1 (30000,30000,30000) L_0x10aa950/d; +v0x10aa150_0 .net "a", 0 0, L_0x12c6fc0; alias, 1 drivers +v0x10aa220_0 .net "b", 0 0, L_0x12d0cb0; alias, 1 drivers +v0x10aa2c0_0 .net "carryout", 0 0, L_0x10aa950; alias, 1 drivers +v0x10aa390_0 .net "sum", 0 0, L_0x12c7230; alias, 1 drivers +S_0x10acbb0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x109c1e0; + .timescale -9 -12; +L_0x2ac432884e78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884ec0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c6be0/d .functor OR 1, L_0x2ac432884e78, L_0x2ac432884ec0, C4<0>, C4<0>; +L_0x12c6be0 .delay 1 (30000,30000,30000) L_0x12c6be0/d; +v0x10acda0_0 .net/2u *"_s0", 0 0, L_0x2ac432884e78; 1 drivers +v0x10ace80_0 .net/2u *"_s2", 0 0, L_0x2ac432884ec0; 1 drivers +S_0x10acf60 .scope generate, "alu_slices[8]" "alu_slices[8]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1069940 .param/l "i" 0 3 39, +C4<01000>; +S_0x10ad270 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x10acf60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12d0c40/d .functor NOT 1, L_0x12db380, C4<0>, C4<0>, C4<0>; +L_0x12d0c40 .delay 1 (10000,10000,10000) L_0x12d0c40/d; +L_0x12d0fd0/d .functor NOT 1, L_0x12db4e0, C4<0>, C4<0>, C4<0>; +L_0x12d0fd0 .delay 1 (10000,10000,10000) L_0x12d0fd0/d; +L_0x12d1fd0/d .functor XOR 1, L_0x12db380, L_0x12db4e0, C4<0>, C4<0>; +L_0x12d1fd0 .delay 1 (30000,30000,30000) L_0x12d1fd0/d; +L_0x2ac432884f08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884f50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d2090/d .functor OR 1, L_0x2ac432884f08, L_0x2ac432884f50, C4<0>, C4<0>; +L_0x12d2090 .delay 1 (30000,30000,30000) L_0x12d2090/d; +L_0x2ac432884f98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432884fe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d2830/d .functor OR 1, L_0x2ac432884f98, L_0x2ac432884fe0, C4<0>, C4<0>; +L_0x12d2830 .delay 1 (30000,30000,30000) L_0x12d2830/d; +L_0x12d2a30/d .functor AND 1, L_0x12db380, L_0x12db4e0, C4<1>, C4<1>; +L_0x12d2a30 .delay 1 (30000,30000,30000) L_0x12d2a30/d; +L_0x2ac432885028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d2af0/d .functor OR 1, L_0x2ac432885028, L_0x2ac432885070, C4<0>, C4<0>; +L_0x12d2af0 .delay 1 (30000,30000,30000) L_0x12d2af0/d; +L_0x12d2cf0/d .functor NAND 1, L_0x12db380, L_0x12db4e0, C4<1>, C4<1>; +L_0x12d2cf0 .delay 1 (20000,20000,20000) L_0x12d2cf0/d; +L_0x2ac4328850b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885100 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d2e00/d .functor OR 1, L_0x2ac4328850b8, L_0x2ac432885100, C4<0>, C4<0>; +L_0x12d2e00 .delay 1 (30000,30000,30000) L_0x12d2e00/d; +L_0x12d2fb0/d .functor NOR 1, L_0x12db380, L_0x12db4e0, C4<0>, C4<0>; +L_0x12d2fb0 .delay 1 (20000,20000,20000) L_0x12d2fb0/d; +L_0x2ac432885148 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d3280/d .functor OR 1, L_0x2ac432885148, L_0x2ac432885190, C4<0>, C4<0>; +L_0x12d3280 .delay 1 (30000,30000,30000) L_0x12d3280/d; +L_0x12d3680/d .functor OR 1, L_0x12db380, L_0x12db4e0, C4<0>, C4<0>; +L_0x12d3680 .delay 1 (30000,30000,30000) L_0x12d3680/d; +L_0x2ac4328851d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d3b20/d .functor OR 1, L_0x2ac4328851d8, L_0x2ac432885220, C4<0>, C4<0>; +L_0x12d3b20 .delay 1 (30000,30000,30000) L_0x12d3b20/d; +L_0x12db280/d .functor NOT 1, L_0x12d74e0, C4<0>, C4<0>, C4<0>; +L_0x12db280 .delay 1 (10000,10000,10000) L_0x12db280/d; +v0x10bb9b0_0 .net "A", 0 0, L_0x12db380; 1 drivers +v0x10bba70_0 .net "A_", 0 0, L_0x12d0c40; 1 drivers +v0x10bbb30_0 .net "B", 0 0, L_0x12db4e0; 1 drivers +v0x10bbc00_0 .net "B_", 0 0, L_0x12d0fd0; 1 drivers +v0x10bbca0_0 .net *"_s11", 0 0, L_0x12d2090; 1 drivers +v0x10bbd90_0 .net/2s *"_s13", 0 0, L_0x2ac432884f08; 1 drivers +v0x10bbe50_0 .net/2s *"_s15", 0 0, L_0x2ac432884f50; 1 drivers +v0x10bbf30_0 .net *"_s19", 0 0, L_0x12d2830; 1 drivers +v0x10bc010_0 .net/2s *"_s21", 0 0, L_0x2ac432884f98; 1 drivers +v0x10bc180_0 .net/2s *"_s23", 0 0, L_0x2ac432884fe0; 1 drivers +v0x10bc260_0 .net *"_s25", 0 0, L_0x12d2a30; 1 drivers +v0x10bc340_0 .net *"_s28", 0 0, L_0x12d2af0; 1 drivers +v0x10bc420_0 .net/2s *"_s30", 0 0, L_0x2ac432885028; 1 drivers +v0x10bc500_0 .net/2s *"_s32", 0 0, L_0x2ac432885070; 1 drivers +v0x10bc5e0_0 .net *"_s34", 0 0, L_0x12d2cf0; 1 drivers +v0x10bc6c0_0 .net *"_s37", 0 0, L_0x12d2e00; 1 drivers +v0x10bc7a0_0 .net/2s *"_s39", 0 0, L_0x2ac4328850b8; 1 drivers +v0x10bc950_0 .net/2s *"_s41", 0 0, L_0x2ac432885100; 1 drivers +v0x10bc9f0_0 .net *"_s43", 0 0, L_0x12d2fb0; 1 drivers +v0x10bcad0_0 .net *"_s46", 0 0, L_0x12d3280; 1 drivers +v0x10bcbb0_0 .net/2s *"_s48", 0 0, L_0x2ac432885148; 1 drivers +v0x10bcc90_0 .net/2s *"_s50", 0 0, L_0x2ac432885190; 1 drivers +v0x10bcd70_0 .net *"_s52", 0 0, L_0x12d3680; 1 drivers +v0x10bce50_0 .net *"_s56", 0 0, L_0x12d3b20; 1 drivers +v0x10bcf30_0 .net/2s *"_s59", 0 0, L_0x2ac4328851d8; 1 drivers +v0x10bd010_0 .net/2s *"_s61", 0 0, L_0x2ac432885220; 1 drivers +v0x10bd0f0_0 .net *"_s8", 0 0, L_0x12d1fd0; 1 drivers +v0x10bd1d0_0 .net "carryin", 0 0, L_0x12d0e60; 1 drivers +v0x10bd270_0 .net "carryout", 0 0, L_0x12daf20; 1 drivers +v0x10bd310_0 .net "carryouts", 7 0, L_0x12d3790; 1 drivers +v0x10bd420_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x10bd4e0_0 .net "result", 0 0, L_0x12d74e0; 1 drivers +v0x10bd5d0_0 .net "results", 7 0, L_0x12d3450; 1 drivers +v0x10bc8b0_0 .net "zero", 0 0, L_0x12db280; 1 drivers +LS_0x12d3450_0_0 .concat8 [ 1 1 1 1], L_0x12d14f0, L_0x12d1b20, L_0x12d1fd0, L_0x12d2830; +LS_0x12d3450_0_4 .concat8 [ 1 1 1 1], L_0x12d2a30, L_0x12d2cf0, L_0x12d2fb0, L_0x12d3680; +L_0x12d3450 .concat8 [ 4 4 0 0], LS_0x12d3450_0_0, LS_0x12d3450_0_4; +LS_0x12d3790_0_0 .concat8 [ 1 1 1 1], L_0x12d17a0, L_0x12d1e70, L_0x12d2090, L_0x12d2680; +LS_0x12d3790_0_4 .concat8 [ 1 1 1 1], L_0x12d2af0, L_0x12d2e00, L_0x12d3280, L_0x12d3b20; +L_0x12d3790 .concat8 [ 4 4 0 0], LS_0x12d3790_0_0, LS_0x12d3790_0_4; +S_0x10ad4f0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10ad270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12d17a0/d .functor OR 1, L_0x12d1280, L_0x12d1640, C4<0>, C4<0>; +L_0x12d17a0 .delay 1 (30000,30000,30000) L_0x12d17a0/d; +v0x10ae320_0 .net "a", 0 0, L_0x12db380; alias, 1 drivers +v0x10ae3e0_0 .net "b", 0 0, L_0x12db4e0; alias, 1 drivers +v0x10ae4b0_0 .net "c1", 0 0, L_0x12d1280; 1 drivers +v0x10ae5b0_0 .net "c2", 0 0, L_0x12d1640; 1 drivers +v0x10ae680_0 .net "carryin", 0 0, L_0x12d0e60; alias, 1 drivers +v0x10ae770_0 .net "carryout", 0 0, L_0x12d17a0; 1 drivers +v0x10ae810_0 .net "s1", 0 0, L_0x12d11c0; 1 drivers +v0x10ae900_0 .net "sum", 0 0, L_0x12d14f0; 1 drivers +S_0x10ad760 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10ad4f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12d11c0/d .functor XOR 1, L_0x12db380, L_0x12db4e0, C4<0>, C4<0>; +L_0x12d11c0 .delay 1 (30000,30000,30000) L_0x12d11c0/d; +L_0x12d1280/d .functor AND 1, L_0x12db380, L_0x12db4e0, C4<1>, C4<1>; +L_0x12d1280 .delay 1 (30000,30000,30000) L_0x12d1280/d; +v0x10ad9c0_0 .net "a", 0 0, L_0x12db380; alias, 1 drivers +v0x10adaa0_0 .net "b", 0 0, L_0x12db4e0; alias, 1 drivers +v0x10adb60_0 .net "carryout", 0 0, L_0x12d1280; alias, 1 drivers +v0x10adc00_0 .net "sum", 0 0, L_0x12d11c0; alias, 1 drivers +S_0x10add40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10ad4f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12d14f0/d .functor XOR 1, L_0x12d11c0, L_0x12d0e60, C4<0>, C4<0>; +L_0x12d14f0 .delay 1 (30000,30000,30000) L_0x12d14f0/d; +L_0x12d1640/d .functor AND 1, L_0x12d11c0, L_0x12d0e60, C4<1>, C4<1>; +L_0x12d1640 .delay 1 (30000,30000,30000) L_0x12d1640/d; +v0x10adfa0_0 .net "a", 0 0, L_0x12d11c0; alias, 1 drivers +v0x10ae040_0 .net "b", 0 0, L_0x12d0e60; alias, 1 drivers +v0x10ae0e0_0 .net "carryout", 0 0, L_0x12d1640; alias, 1 drivers +v0x10ae1b0_0 .net "sum", 0 0, L_0x12d14f0; alias, 1 drivers +S_0x10ae9d0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x10ad270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10b3dc0_0 .net "ands", 7 0, L_0x12d8f20; 1 drivers +v0x10b3ed0_0 .net "in", 7 0, L_0x12d3790; alias, 1 drivers +v0x10b3f90_0 .net "out", 0 0, L_0x12daf20; alias, 1 drivers +v0x10b4060_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10aebf0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10ae9d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10b1320_0 .net "A", 7 0, L_0x12d3790; alias, 1 drivers +v0x10b1420_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10b14e0_0 .net *"_s0", 0 0, L_0x12d7840; 1 drivers +v0x10b15a0_0 .net *"_s12", 0 0, L_0x12d81b0; 1 drivers +v0x10b1680_0 .net *"_s16", 0 0, L_0x12d8510; 1 drivers +v0x10b17b0_0 .net *"_s20", 0 0, L_0x12d88e0; 1 drivers +v0x10b1890_0 .net *"_s24", 0 0, L_0x12d8c10; 1 drivers +v0x10b1970_0 .net *"_s28", 0 0, L_0x12d8ba0; 1 drivers +v0x10b1a50_0 .net *"_s4", 0 0, L_0x12d7b90; 1 drivers +v0x10b1bc0_0 .net *"_s8", 0 0, L_0x12d7ea0; 1 drivers +v0x10b1ca0_0 .net "out", 7 0, L_0x12d8f20; alias, 1 drivers +L_0x12d7900 .part L_0x12d3790, 0, 1; +L_0x12d7af0 .part v0x127a150_0, 0, 1; +L_0x12d7c50 .part L_0x12d3790, 1, 1; +L_0x12d7db0 .part v0x127a150_0, 1, 1; +L_0x12d7f60 .part L_0x12d3790, 2, 1; +L_0x12d80c0 .part v0x127a150_0, 2, 1; +L_0x12d8270 .part L_0x12d3790, 3, 1; +L_0x12d83d0 .part v0x127a150_0, 3, 1; +L_0x12d85d0 .part L_0x12d3790, 4, 1; +L_0x12d8840 .part v0x127a150_0, 4, 1; +L_0x12d8950 .part L_0x12d3790, 5, 1; +L_0x12d8ab0 .part v0x127a150_0, 5, 1; +L_0x12d8cd0 .part L_0x12d3790, 6, 1; +L_0x12d8e30 .part v0x127a150_0, 6, 1; +LS_0x12d8f20_0_0 .concat8 [ 1 1 1 1], L_0x12d7840, L_0x12d7b90, L_0x12d7ea0, L_0x12d81b0; +LS_0x12d8f20_0_4 .concat8 [ 1 1 1 1], L_0x12d8510, L_0x12d88e0, L_0x12d8c10, L_0x12d8ba0; +L_0x12d8f20 .concat8 [ 4 4 0 0], LS_0x12d8f20_0_0, LS_0x12d8f20_0_4; +L_0x12d92e0 .part L_0x12d3790, 7, 1; +L_0x12d94d0 .part v0x127a150_0, 7, 1; +S_0x10aee50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10af060 .param/l "i" 0 4 54, +C4<00>; +L_0x12d7840/d .functor AND 1, L_0x12d7900, L_0x12d7af0, C4<1>, C4<1>; +L_0x12d7840 .delay 1 (30000,30000,30000) L_0x12d7840/d; +v0x10af140_0 .net *"_s0", 0 0, L_0x12d7900; 1 drivers +v0x10af220_0 .net *"_s1", 0 0, L_0x12d7af0; 1 drivers +S_0x10af300 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10af510 .param/l "i" 0 4 54, +C4<01>; +L_0x12d7b90/d .functor AND 1, L_0x12d7c50, L_0x12d7db0, C4<1>, C4<1>; +L_0x12d7b90 .delay 1 (30000,30000,30000) L_0x12d7b90/d; +v0x10af5d0_0 .net *"_s0", 0 0, L_0x12d7c50; 1 drivers +v0x10af6b0_0 .net *"_s1", 0 0, L_0x12d7db0; 1 drivers +S_0x10af790 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10af9a0 .param/l "i" 0 4 54, +C4<010>; +L_0x12d7ea0/d .functor AND 1, L_0x12d7f60, L_0x12d80c0, C4<1>, C4<1>; +L_0x12d7ea0 .delay 1 (30000,30000,30000) L_0x12d7ea0/d; +v0x10afa40_0 .net *"_s0", 0 0, L_0x12d7f60; 1 drivers +v0x10afb20_0 .net *"_s1", 0 0, L_0x12d80c0; 1 drivers +S_0x10afc00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10afe10 .param/l "i" 0 4 54, +C4<011>; +L_0x12d81b0/d .functor AND 1, L_0x12d8270, L_0x12d83d0, C4<1>, C4<1>; +L_0x12d81b0 .delay 1 (30000,30000,30000) L_0x12d81b0/d; +v0x10afed0_0 .net *"_s0", 0 0, L_0x12d8270; 1 drivers +v0x10affb0_0 .net *"_s1", 0 0, L_0x12d83d0; 1 drivers +S_0x10b0090 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10b02f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12d8510/d .functor AND 1, L_0x12d85d0, L_0x12d8840, C4<1>, C4<1>; +L_0x12d8510 .delay 1 (30000,30000,30000) L_0x12d8510/d; +v0x10b03b0_0 .net *"_s0", 0 0, L_0x12d85d0; 1 drivers +v0x10b0490_0 .net *"_s1", 0 0, L_0x12d8840; 1 drivers +S_0x10b0570 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10b0780 .param/l "i" 0 4 54, +C4<0101>; +L_0x12d88e0/d .functor AND 1, L_0x12d8950, L_0x12d8ab0, C4<1>, C4<1>; +L_0x12d88e0 .delay 1 (30000,30000,30000) L_0x12d88e0/d; +v0x10b0840_0 .net *"_s0", 0 0, L_0x12d8950; 1 drivers +v0x10b0920_0 .net *"_s1", 0 0, L_0x12d8ab0; 1 drivers +S_0x10b0a00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10b0c10 .param/l "i" 0 4 54, +C4<0110>; +L_0x12d8c10/d .functor AND 1, L_0x12d8cd0, L_0x12d8e30, C4<1>, C4<1>; +L_0x12d8c10 .delay 1 (30000,30000,30000) L_0x12d8c10/d; +v0x10b0cd0_0 .net *"_s0", 0 0, L_0x12d8cd0; 1 drivers +v0x10b0db0_0 .net *"_s1", 0 0, L_0x12d8e30; 1 drivers +S_0x10b0e90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10aebf0; + .timescale -9 -12; +P_0x10b10a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12d8ba0/d .functor AND 1, L_0x12d92e0, L_0x12d94d0, C4<1>, C4<1>; +L_0x12d8ba0 .delay 1 (30000,30000,30000) L_0x12d8ba0/d; +v0x10b1160_0 .net *"_s0", 0 0, L_0x12d92e0; 1 drivers +v0x10b1240_0 .net *"_s1", 0 0, L_0x12d94d0; 1 drivers +S_0x10b1e00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10ae9d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12daf20/d .functor OR 1, L_0x12dafe0, L_0x12db190, C4<0>, C4<0>; +L_0x12daf20 .delay 1 (30000,30000,30000) L_0x12daf20/d; +v0x10b3950_0 .net *"_s10", 0 0, L_0x12dafe0; 1 drivers +v0x10b3a30_0 .net *"_s12", 0 0, L_0x12db190; 1 drivers +v0x10b3b10_0 .net "in", 7 0, L_0x12d8f20; alias, 1 drivers +v0x10b3be0_0 .net "ors", 1 0, L_0x12dad40; 1 drivers +v0x10b3ca0_0 .net "out", 0 0, L_0x12daf20; alias, 1 drivers +L_0x12da110 .part L_0x12d8f20, 0, 4; +L_0x12dad40 .concat8 [ 1 1 0 0], L_0x12d9e00, L_0x12daa30; +L_0x12dae80 .part L_0x12d8f20, 4, 4; +L_0x12dafe0 .part L_0x12dad40, 0, 1; +L_0x12db190 .part L_0x12dad40, 1, 1; +S_0x10b1fc0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10b1e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12d95c0/d .functor OR 1, L_0x12d9680, L_0x12d97e0, C4<0>, C4<0>; +L_0x12d95c0 .delay 1 (30000,30000,30000) L_0x12d95c0/d; +L_0x12d9a10/d .functor OR 1, L_0x12d9b20, L_0x12d9c80, C4<0>, C4<0>; +L_0x12d9a10 .delay 1 (30000,30000,30000) L_0x12d9a10/d; +L_0x12d9e00/d .functor OR 1, L_0x12d9e70, L_0x12da020, C4<0>, C4<0>; +L_0x12d9e00 .delay 1 (30000,30000,30000) L_0x12d9e00/d; +v0x10b2210_0 .net *"_s0", 0 0, L_0x12d95c0; 1 drivers +v0x10b2310_0 .net *"_s10", 0 0, L_0x12d9b20; 1 drivers +v0x10b23f0_0 .net *"_s12", 0 0, L_0x12d9c80; 1 drivers +v0x10b24b0_0 .net *"_s14", 0 0, L_0x12d9e70; 1 drivers +v0x10b2590_0 .net *"_s16", 0 0, L_0x12da020; 1 drivers +v0x10b26c0_0 .net *"_s3", 0 0, L_0x12d9680; 1 drivers +v0x10b27a0_0 .net *"_s5", 0 0, L_0x12d97e0; 1 drivers +v0x10b2880_0 .net *"_s6", 0 0, L_0x12d9a10; 1 drivers +v0x10b2960_0 .net "in", 3 0, L_0x12da110; 1 drivers +v0x10b2ad0_0 .net "ors", 1 0, L_0x12d9920; 1 drivers +v0x10b2bb0_0 .net "out", 0 0, L_0x12d9e00; 1 drivers +L_0x12d9680 .part L_0x12da110, 0, 1; +L_0x12d97e0 .part L_0x12da110, 1, 1; +L_0x12d9920 .concat8 [ 1 1 0 0], L_0x12d95c0, L_0x12d9a10; +L_0x12d9b20 .part L_0x12da110, 2, 1; +L_0x12d9c80 .part L_0x12da110, 3, 1; +L_0x12d9e70 .part L_0x12d9920, 0, 1; +L_0x12da020 .part L_0x12d9920, 1, 1; +S_0x10b2cd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10b1e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12da240/d .functor OR 1, L_0x12da2b0, L_0x12da410, C4<0>, C4<0>; +L_0x12da240 .delay 1 (30000,30000,30000) L_0x12da240/d; +L_0x12da640/d .functor OR 1, L_0x12da750, L_0x12da8b0, C4<0>, C4<0>; +L_0x12da640 .delay 1 (30000,30000,30000) L_0x12da640/d; +L_0x12daa30/d .functor OR 1, L_0x12daaa0, L_0x12dac50, C4<0>, C4<0>; +L_0x12daa30 .delay 1 (30000,30000,30000) L_0x12daa30/d; +v0x10b2e90_0 .net *"_s0", 0 0, L_0x12da240; 1 drivers +v0x10b2f90_0 .net *"_s10", 0 0, L_0x12da750; 1 drivers +v0x10b3070_0 .net *"_s12", 0 0, L_0x12da8b0; 1 drivers +v0x10b3130_0 .net *"_s14", 0 0, L_0x12daaa0; 1 drivers +v0x10b3210_0 .net *"_s16", 0 0, L_0x12dac50; 1 drivers +v0x10b3340_0 .net *"_s3", 0 0, L_0x12da2b0; 1 drivers +v0x10b3420_0 .net *"_s5", 0 0, L_0x12da410; 1 drivers +v0x10b3500_0 .net *"_s6", 0 0, L_0x12da640; 1 drivers +v0x10b35e0_0 .net "in", 3 0, L_0x12dae80; 1 drivers +v0x10b3750_0 .net "ors", 1 0, L_0x12da550; 1 drivers +v0x10b3830_0 .net "out", 0 0, L_0x12daa30; 1 drivers +L_0x12da2b0 .part L_0x12dae80, 0, 1; +L_0x12da410 .part L_0x12dae80, 1, 1; +L_0x12da550 .concat8 [ 1 1 0 0], L_0x12da240, L_0x12da640; +L_0x12da750 .part L_0x12dae80, 2, 1; +L_0x12da8b0 .part L_0x12dae80, 3, 1; +L_0x12daaa0 .part L_0x12da550, 0, 1; +L_0x12dac50 .part L_0x12da550, 1, 1; +S_0x10b4140 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x10ad270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10b9580_0 .net "ands", 7 0, L_0x12d54e0; 1 drivers +v0x10b9690_0 .net "in", 7 0, L_0x12d3450; alias, 1 drivers +v0x10b9750_0 .net "out", 0 0, L_0x12d74e0; alias, 1 drivers +v0x10b9820_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10b4390 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10b4140; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10b6ad0_0 .net "A", 7 0, L_0x12d3450; alias, 1 drivers +v0x10b6bd0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10b6c90_0 .net *"_s0", 0 0, L_0x12d3cd0; 1 drivers +v0x10b6d50_0 .net *"_s12", 0 0, L_0x12d4690; 1 drivers +v0x10b6e30_0 .net *"_s16", 0 0, L_0x12d49f0; 1 drivers +v0x10b6f60_0 .net *"_s20", 0 0, L_0x12d4e20; 1 drivers +v0x10b7040_0 .net *"_s24", 0 0, L_0x12d5150; 1 drivers +v0x10b7120_0 .net *"_s28", 0 0, L_0x12d50e0; 1 drivers +v0x10b7200_0 .net *"_s4", 0 0, L_0x12d4070; 1 drivers +v0x10b7370_0 .net *"_s8", 0 0, L_0x12d4380; 1 drivers +v0x10b7450_0 .net "out", 7 0, L_0x12d54e0; alias, 1 drivers +L_0x12d3de0 .part L_0x12d3450, 0, 1; +L_0x12d3fd0 .part v0x127a150_0, 0, 1; +L_0x12d4130 .part L_0x12d3450, 1, 1; +L_0x12d4290 .part v0x127a150_0, 1, 1; +L_0x12d4440 .part L_0x12d3450, 2, 1; +L_0x12d45a0 .part v0x127a150_0, 2, 1; +L_0x12d4750 .part L_0x12d3450, 3, 1; +L_0x12d48b0 .part v0x127a150_0, 3, 1; +L_0x12d4ab0 .part L_0x12d3450, 4, 1; +L_0x12d4d20 .part v0x127a150_0, 4, 1; +L_0x12d4e90 .part L_0x12d3450, 5, 1; +L_0x12d4ff0 .part v0x127a150_0, 5, 1; +L_0x12d5210 .part L_0x12d3450, 6, 1; +L_0x12d5370 .part v0x127a150_0, 6, 1; +LS_0x12d54e0_0_0 .concat8 [ 1 1 1 1], L_0x12d3cd0, L_0x12d4070, L_0x12d4380, L_0x12d4690; +LS_0x12d54e0_0_4 .concat8 [ 1 1 1 1], L_0x12d49f0, L_0x12d4e20, L_0x12d5150, L_0x12d50e0; +L_0x12d54e0 .concat8 [ 4 4 0 0], LS_0x12d54e0_0_0, LS_0x12d54e0_0_4; +L_0x12d58a0 .part L_0x12d3450, 7, 1; +L_0x12d5a90 .part v0x127a150_0, 7, 1; +S_0x10b45d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b47e0 .param/l "i" 0 4 54, +C4<00>; +L_0x12d3cd0/d .functor AND 1, L_0x12d3de0, L_0x12d3fd0, C4<1>, C4<1>; +L_0x12d3cd0 .delay 1 (30000,30000,30000) L_0x12d3cd0/d; +v0x10b48c0_0 .net *"_s0", 0 0, L_0x12d3de0; 1 drivers +v0x10b49a0_0 .net *"_s1", 0 0, L_0x12d3fd0; 1 drivers +S_0x10b4a80 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b4c90 .param/l "i" 0 4 54, +C4<01>; +L_0x12d4070/d .functor AND 1, L_0x12d4130, L_0x12d4290, C4<1>, C4<1>; +L_0x12d4070 .delay 1 (30000,30000,30000) L_0x12d4070/d; +v0x10b4d50_0 .net *"_s0", 0 0, L_0x12d4130; 1 drivers +v0x10b4e30_0 .net *"_s1", 0 0, L_0x12d4290; 1 drivers +S_0x10b4f10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b5150 .param/l "i" 0 4 54, +C4<010>; +L_0x12d4380/d .functor AND 1, L_0x12d4440, L_0x12d45a0, C4<1>, C4<1>; +L_0x12d4380 .delay 1 (30000,30000,30000) L_0x12d4380/d; +v0x10b51f0_0 .net *"_s0", 0 0, L_0x12d4440; 1 drivers +v0x10b52d0_0 .net *"_s1", 0 0, L_0x12d45a0; 1 drivers +S_0x10b53b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b55c0 .param/l "i" 0 4 54, +C4<011>; +L_0x12d4690/d .functor AND 1, L_0x12d4750, L_0x12d48b0, C4<1>, C4<1>; +L_0x12d4690 .delay 1 (30000,30000,30000) L_0x12d4690/d; +v0x10b5680_0 .net *"_s0", 0 0, L_0x12d4750; 1 drivers +v0x10b5760_0 .net *"_s1", 0 0, L_0x12d48b0; 1 drivers +S_0x10b5840 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b5aa0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12d49f0/d .functor AND 1, L_0x12d4ab0, L_0x12d4d20, C4<1>, C4<1>; +L_0x12d49f0 .delay 1 (30000,30000,30000) L_0x12d49f0/d; +v0x10b5b60_0 .net *"_s0", 0 0, L_0x12d4ab0; 1 drivers +v0x10b5c40_0 .net *"_s1", 0 0, L_0x12d4d20; 1 drivers +S_0x10b5d20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b5f30 .param/l "i" 0 4 54, +C4<0101>; +L_0x12d4e20/d .functor AND 1, L_0x12d4e90, L_0x12d4ff0, C4<1>, C4<1>; +L_0x12d4e20 .delay 1 (30000,30000,30000) L_0x12d4e20/d; +v0x10b5ff0_0 .net *"_s0", 0 0, L_0x12d4e90; 1 drivers +v0x10b60d0_0 .net *"_s1", 0 0, L_0x12d4ff0; 1 drivers +S_0x10b61b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b63c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12d5150/d .functor AND 1, L_0x12d5210, L_0x12d5370, C4<1>, C4<1>; +L_0x12d5150 .delay 1 (30000,30000,30000) L_0x12d5150/d; +v0x10b6480_0 .net *"_s0", 0 0, L_0x12d5210; 1 drivers +v0x10b6560_0 .net *"_s1", 0 0, L_0x12d5370; 1 drivers +S_0x10b6640 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10b4390; + .timescale -9 -12; +P_0x10b6850 .param/l "i" 0 4 54, +C4<0111>; +L_0x12d50e0/d .functor AND 1, L_0x12d58a0, L_0x12d5a90, C4<1>, C4<1>; +L_0x12d50e0 .delay 1 (30000,30000,30000) L_0x12d50e0/d; +v0x10b6910_0 .net *"_s0", 0 0, L_0x12d58a0; 1 drivers +v0x10b69f0_0 .net *"_s1", 0 0, L_0x12d5a90; 1 drivers +S_0x10b75b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10b4140; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12d74e0/d .functor OR 1, L_0x12d75a0, L_0x12d7750, C4<0>, C4<0>; +L_0x12d74e0 .delay 1 (30000,30000,30000) L_0x12d74e0/d; +v0x10b9110_0 .net *"_s10", 0 0, L_0x12d75a0; 1 drivers +v0x10b91f0_0 .net *"_s12", 0 0, L_0x12d7750; 1 drivers +v0x10b92d0_0 .net "in", 7 0, L_0x12d54e0; alias, 1 drivers +v0x10b93a0_0 .net "ors", 1 0, L_0x12d7300; 1 drivers +v0x10b9460_0 .net "out", 0 0, L_0x12d74e0; alias, 1 drivers +L_0x12d66d0 .part L_0x12d54e0, 0, 4; +L_0x12d7300 .concat8 [ 1 1 0 0], L_0x12d63c0, L_0x12d6ff0; +L_0x12d7440 .part L_0x12d54e0, 4, 4; +L_0x12d75a0 .part L_0x12d7300, 0, 1; +L_0x12d7750 .part L_0x12d7300, 1, 1; +S_0x10b7770 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10b75b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12d5b80/d .functor OR 1, L_0x12d5c40, L_0x12d5da0, C4<0>, C4<0>; +L_0x12d5b80 .delay 1 (30000,30000,30000) L_0x12d5b80/d; +L_0x12d5fd0/d .functor OR 1, L_0x12d60e0, L_0x12d6240, C4<0>, C4<0>; +L_0x12d5fd0 .delay 1 (30000,30000,30000) L_0x12d5fd0/d; +L_0x12d63c0/d .functor OR 1, L_0x12d6430, L_0x12d65e0, C4<0>, C4<0>; +L_0x12d63c0 .delay 1 (30000,30000,30000) L_0x12d63c0/d; +v0x10b79c0_0 .net *"_s0", 0 0, L_0x12d5b80; 1 drivers +v0x10b7ac0_0 .net *"_s10", 0 0, L_0x12d60e0; 1 drivers +v0x10b7ba0_0 .net *"_s12", 0 0, L_0x12d6240; 1 drivers +v0x10b7c60_0 .net *"_s14", 0 0, L_0x12d6430; 1 drivers +v0x10b7d40_0 .net *"_s16", 0 0, L_0x12d65e0; 1 drivers +v0x10b7e70_0 .net *"_s3", 0 0, L_0x12d5c40; 1 drivers +v0x10b7f50_0 .net *"_s5", 0 0, L_0x12d5da0; 1 drivers +v0x10b8010_0 .net *"_s6", 0 0, L_0x12d5fd0; 1 drivers +v0x10b80f0_0 .net "in", 3 0, L_0x12d66d0; 1 drivers +v0x10b8260_0 .net "ors", 1 0, L_0x12d5ee0; 1 drivers +v0x10b8340_0 .net "out", 0 0, L_0x12d63c0; 1 drivers +L_0x12d5c40 .part L_0x12d66d0, 0, 1; +L_0x12d5da0 .part L_0x12d66d0, 1, 1; +L_0x12d5ee0 .concat8 [ 1 1 0 0], L_0x12d5b80, L_0x12d5fd0; +L_0x12d60e0 .part L_0x12d66d0, 2, 1; +L_0x12d6240 .part L_0x12d66d0, 3, 1; +L_0x12d6430 .part L_0x12d5ee0, 0, 1; +L_0x12d65e0 .part L_0x12d5ee0, 1, 1; +S_0x10b8460 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10b75b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12d6800/d .functor OR 1, L_0x12d6870, L_0x12d69d0, C4<0>, C4<0>; +L_0x12d6800 .delay 1 (30000,30000,30000) L_0x12d6800/d; +L_0x12d6c00/d .functor OR 1, L_0x12d6d10, L_0x12d6e70, C4<0>, C4<0>; +L_0x12d6c00 .delay 1 (30000,30000,30000) L_0x12d6c00/d; +L_0x12d6ff0/d .functor OR 1, L_0x12d7060, L_0x12d7210, C4<0>, C4<0>; +L_0x12d6ff0 .delay 1 (30000,30000,30000) L_0x12d6ff0/d; +v0x10b8620_0 .net *"_s0", 0 0, L_0x12d6800; 1 drivers +v0x10b8720_0 .net *"_s10", 0 0, L_0x12d6d10; 1 drivers +v0x10b8800_0 .net *"_s12", 0 0, L_0x12d6e70; 1 drivers +v0x10b88f0_0 .net *"_s14", 0 0, L_0x12d7060; 1 drivers +v0x10b89d0_0 .net *"_s16", 0 0, L_0x12d7210; 1 drivers +v0x10b8b00_0 .net *"_s3", 0 0, L_0x12d6870; 1 drivers +v0x10b8be0_0 .net *"_s5", 0 0, L_0x12d69d0; 1 drivers +v0x10b8cc0_0 .net *"_s6", 0 0, L_0x12d6c00; 1 drivers +v0x10b8da0_0 .net "in", 3 0, L_0x12d7440; 1 drivers +v0x10b8f10_0 .net "ors", 1 0, L_0x12d6b10; 1 drivers +v0x10b8ff0_0 .net "out", 0 0, L_0x12d6ff0; 1 drivers +L_0x12d6870 .part L_0x12d7440, 0, 1; +L_0x12d69d0 .part L_0x12d7440, 1, 1; +L_0x12d6b10 .concat8 [ 1 1 0 0], L_0x12d6800, L_0x12d6c00; +L_0x12d6d10 .part L_0x12d7440, 2, 1; +L_0x12d6e70 .part L_0x12d7440, 3, 1; +L_0x12d7060 .part L_0x12d6b10, 0, 1; +L_0x12d7210 .part L_0x12d6b10, 1, 1; +S_0x10b9900 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x10ad270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12d2290/d .functor XNOR 1, L_0x12db380, L_0x12db4e0, C4<0>, C4<0>; +L_0x12d2290 .delay 1 (20000,20000,20000) L_0x12d2290/d; +L_0x12d2410/d .functor AND 1, L_0x12db380, L_0x12d0fd0, C4<1>, C4<1>; +L_0x12d2410 .delay 1 (30000,30000,30000) L_0x12d2410/d; +L_0x12d2570/d .functor AND 1, L_0x12d2290, L_0x12d0e60, C4<1>, C4<1>; +L_0x12d2570 .delay 1 (30000,30000,30000) L_0x12d2570/d; +L_0x12d2680/d .functor OR 1, L_0x12d2570, L_0x12d2410, C4<0>, C4<0>; +L_0x12d2680 .delay 1 (30000,30000,30000) L_0x12d2680/d; +v0x10b9bb0_0 .net "a", 0 0, L_0x12db380; alias, 1 drivers +v0x10b9ca0_0 .net "a_", 0 0, L_0x12d0c40; alias, 1 drivers +v0x10b9d60_0 .net "b", 0 0, L_0x12db4e0; alias, 1 drivers +v0x10b9e50_0 .net "b_", 0 0, L_0x12d0fd0; alias, 1 drivers +v0x10b9ef0_0 .net "carryin", 0 0, L_0x12d0e60; alias, 1 drivers +v0x10ba030_0 .net "eq", 0 0, L_0x12d2290; 1 drivers +v0x10ba0f0_0 .net "lt", 0 0, L_0x12d2410; 1 drivers +v0x10ba1b0_0 .net "out", 0 0, L_0x12d2680; 1 drivers +v0x10ba270_0 .net "w0", 0 0, L_0x12d2570; 1 drivers +S_0x10ba4c0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10ad270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12d1e70/d .functor OR 1, L_0x12d19c0, L_0x10bb720, C4<0>, C4<0>; +L_0x12d1e70 .delay 1 (30000,30000,30000) L_0x12d1e70/d; +v0x10bb2b0_0 .net "a", 0 0, L_0x12db380; alias, 1 drivers +v0x10bb400_0 .net "b", 0 0, L_0x12d0fd0; alias, 1 drivers +v0x10bb4c0_0 .net "c1", 0 0, L_0x12d19c0; 1 drivers +v0x10bb560_0 .net "c2", 0 0, L_0x10bb720; 1 drivers +v0x10bb630_0 .net "carryin", 0 0, L_0x12d0e60; alias, 1 drivers +v0x10bb7b0_0 .net "carryout", 0 0, L_0x12d1e70; 1 drivers +v0x10bb850_0 .net "s1", 0 0, L_0x12d1900; 1 drivers +v0x10bb8f0_0 .net "sum", 0 0, L_0x12d1b20; 1 drivers +S_0x10ba710 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10ba4c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12d1900/d .functor XOR 1, L_0x12db380, L_0x12d0fd0, C4<0>, C4<0>; +L_0x12d1900 .delay 1 (30000,30000,30000) L_0x12d1900/d; +L_0x12d19c0/d .functor AND 1, L_0x12db380, L_0x12d0fd0, C4<1>, C4<1>; +L_0x12d19c0 .delay 1 (30000,30000,30000) L_0x12d19c0/d; +v0x10ba970_0 .net "a", 0 0, L_0x12db380; alias, 1 drivers +v0x10baa30_0 .net "b", 0 0, L_0x12d0fd0; alias, 1 drivers +v0x10baaf0_0 .net "carryout", 0 0, L_0x12d19c0; alias, 1 drivers +v0x10bab90_0 .net "sum", 0 0, L_0x12d1900; alias, 1 drivers +S_0x10bacc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10ba4c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12d1b20/d .functor XOR 1, L_0x12d1900, L_0x12d0e60, C4<0>, C4<0>; +L_0x12d1b20 .delay 1 (30000,30000,30000) L_0x12d1b20/d; +L_0x10bb720/d .functor AND 1, L_0x12d1900, L_0x12d0e60, C4<1>, C4<1>; +L_0x10bb720 .delay 1 (30000,30000,30000) L_0x10bb720/d; +v0x10baf20_0 .net "a", 0 0, L_0x12d1900; alias, 1 drivers +v0x10baff0_0 .net "b", 0 0, L_0x12d0e60; alias, 1 drivers +v0x10bb090_0 .net "carryout", 0 0, L_0x10bb720; alias, 1 drivers +v0x10bb160_0 .net "sum", 0 0, L_0x12d1b20; alias, 1 drivers +S_0x10bd980 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x10acf60; + .timescale -9 -12; +L_0x2ac432885268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328852b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d1480/d .functor OR 1, L_0x2ac432885268, L_0x2ac4328852b0, C4<0>, C4<0>; +L_0x12d1480 .delay 1 (30000,30000,30000) L_0x12d1480/d; +v0x10bdb70_0 .net/2u *"_s0", 0 0, L_0x2ac432885268; 1 drivers +v0x10bdc50_0 .net/2u *"_s2", 0 0, L_0x2ac4328852b0; 1 drivers +S_0x10bdd30 .scope generate, "alu_slices[9]" "alu_slices[9]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x10bdf40 .param/l "i" 0 3 39, +C4<01001>; +S_0x10be000 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x10bdd30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12db700/d .functor NOT 1, L_0x12e6070, C4<0>, C4<0>, C4<0>; +L_0x12db700 .delay 1 (10000,10000,10000) L_0x12db700/d; +L_0x12db860/d .functor NOT 1, L_0x12db580, C4<0>, C4<0>, C4<0>; +L_0x12db860 .delay 1 (10000,10000,10000) L_0x12db860/d; +L_0x12dc8b0/d .functor XOR 1, L_0x12e6070, L_0x12db580, C4<0>, C4<0>; +L_0x12dc8b0 .delay 1 (30000,30000,30000) L_0x12dc8b0/d; +L_0x2ac4328852f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885340 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12dc970/d .functor OR 1, L_0x2ac4328852f8, L_0x2ac432885340, C4<0>, C4<0>; +L_0x12dc970 .delay 1 (30000,30000,30000) L_0x12dc970/d; +L_0x2ac432885388 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328853d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12dd110/d .functor OR 1, L_0x2ac432885388, L_0x2ac4328853d0, C4<0>, C4<0>; +L_0x12dd110 .delay 1 (30000,30000,30000) L_0x12dd110/d; +L_0x12dd310/d .functor AND 1, L_0x12e6070, L_0x12db580, C4<1>, C4<1>; +L_0x12dd310 .delay 1 (30000,30000,30000) L_0x12dd310/d; +L_0x2ac432885418 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885460 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12dd3d0/d .functor OR 1, L_0x2ac432885418, L_0x2ac432885460, C4<0>, C4<0>; +L_0x12dd3d0 .delay 1 (30000,30000,30000) L_0x12dd3d0/d; +L_0x12a8850/d .functor NAND 1, L_0x12e6070, L_0x12db580, C4<1>, C4<1>; +L_0x12a8850 .delay 1 (20000,20000,20000) L_0x12a8850/d; +L_0x2ac4328854a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328854f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a8960/d .functor OR 1, L_0x2ac4328854a8, L_0x2ac4328854f0, C4<0>, C4<0>; +L_0x12a8960 .delay 1 (30000,30000,30000) L_0x12a8960/d; +L_0x12a8ac0/d .functor NOR 1, L_0x12e6070, L_0x12db580, C4<0>, C4<0>; +L_0x12a8ac0 .delay 1 (20000,20000,20000) L_0x12a8ac0/d; +L_0x2ac432885538 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885580 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12dbcd0/d .functor OR 1, L_0x2ac432885538, L_0x2ac432885580, C4<0>, C4<0>; +L_0x12dbcd0 .delay 1 (30000,30000,30000) L_0x12dbcd0/d; +L_0x12de380/d .functor OR 1, L_0x12e6070, L_0x12db580, C4<0>, C4<0>; +L_0x12de380 .delay 1 (30000,30000,30000) L_0x12de380/d; +L_0x2ac4328855c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885610 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12de870/d .functor OR 1, L_0x2ac4328855c8, L_0x2ac432885610, C4<0>, C4<0>; +L_0x12de870 .delay 1 (30000,30000,30000) L_0x12de870/d; +L_0x12e5f70/d .functor NOT 1, L_0x12e21d0, C4<0>, C4<0>, C4<0>; +L_0x12e5f70 .delay 1 (10000,10000,10000) L_0x12e5f70/d; +v0x10cc730_0 .net "A", 0 0, L_0x12e6070; 1 drivers +v0x10cc7f0_0 .net "A_", 0 0, L_0x12db700; 1 drivers +v0x10cc8b0_0 .net "B", 0 0, L_0x12db580; 1 drivers +v0x10cc980_0 .net "B_", 0 0, L_0x12db860; 1 drivers +v0x10cca20_0 .net *"_s11", 0 0, L_0x12dc970; 1 drivers +v0x10ccb10_0 .net/2s *"_s13", 0 0, L_0x2ac4328852f8; 1 drivers +v0x10ccbd0_0 .net/2s *"_s15", 0 0, L_0x2ac432885340; 1 drivers +v0x10cccb0_0 .net *"_s19", 0 0, L_0x12dd110; 1 drivers +v0x10ccd90_0 .net/2s *"_s21", 0 0, L_0x2ac432885388; 1 drivers +v0x10ccf00_0 .net/2s *"_s23", 0 0, L_0x2ac4328853d0; 1 drivers +v0x10ccfe0_0 .net *"_s25", 0 0, L_0x12dd310; 1 drivers +v0x10cd0c0_0 .net *"_s28", 0 0, L_0x12dd3d0; 1 drivers +v0x10cd1a0_0 .net/2s *"_s30", 0 0, L_0x2ac432885418; 1 drivers +v0x10cd280_0 .net/2s *"_s32", 0 0, L_0x2ac432885460; 1 drivers +v0x10cd360_0 .net *"_s34", 0 0, L_0x12a8850; 1 drivers +v0x10cd440_0 .net *"_s37", 0 0, L_0x12a8960; 1 drivers +v0x10cd520_0 .net/2s *"_s39", 0 0, L_0x2ac4328854a8; 1 drivers +v0x10cd6d0_0 .net/2s *"_s41", 0 0, L_0x2ac4328854f0; 1 drivers +v0x10cd770_0 .net *"_s43", 0 0, L_0x12a8ac0; 1 drivers +v0x10cd850_0 .net *"_s46", 0 0, L_0x12dbcd0; 1 drivers +v0x10cd930_0 .net/2s *"_s48", 0 0, L_0x2ac432885538; 1 drivers +v0x10cda10_0 .net/2s *"_s50", 0 0, L_0x2ac432885580; 1 drivers +v0x10cdaf0_0 .net *"_s52", 0 0, L_0x12de380; 1 drivers +v0x10cdbd0_0 .net *"_s56", 0 0, L_0x12de870; 1 drivers +v0x10cdcb0_0 .net/2s *"_s59", 0 0, L_0x2ac4328855c8; 1 drivers +v0x10cdd90_0 .net/2s *"_s61", 0 0, L_0x2ac432885610; 1 drivers +v0x10cde70_0 .net *"_s8", 0 0, L_0x12dc8b0; 1 drivers +v0x10cdf50_0 .net "carryin", 0 0, L_0x12e62c0; 1 drivers +v0x10cdff0_0 .net "carryout", 0 0, L_0x12e5c10; 1 drivers +v0x10ce090_0 .net "carryouts", 7 0, L_0x12de500; 1 drivers +v0x10ce1a0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x10ce260_0 .net "result", 0 0, L_0x12e21d0; 1 drivers +v0x10ce350_0 .net "results", 7 0, L_0x12de150; 1 drivers +v0x10cd630_0 .net "zero", 0 0, L_0x12e5f70; 1 drivers +LS_0x12de150_0_0 .concat8 [ 1 1 1 1], L_0x12dbd80, L_0x12dc3b0, L_0x12dc8b0, L_0x12dd110; +LS_0x12de150_0_4 .concat8 [ 1 1 1 1], L_0x12dd310, L_0x12a8850, L_0x12a8ac0, L_0x12de380; +L_0x12de150 .concat8 [ 4 4 0 0], LS_0x12de150_0_0, LS_0x12de150_0_4; +LS_0x12de500_0_0 .concat8 [ 1 1 1 1], L_0x12dc030, L_0x12dc750, L_0x12dc970, L_0x12dcf60; +LS_0x12de500_0_4 .concat8 [ 1 1 1 1], L_0x12dd3d0, L_0x12a8960, L_0x12dbcd0, L_0x12de870; +L_0x12de500 .concat8 [ 4 4 0 0], LS_0x12de500_0_0, LS_0x12de500_0_4; +S_0x10be280 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10be000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12dc030/d .functor OR 1, L_0x12dbb10, L_0x12dbed0, C4<0>, C4<0>; +L_0x12dc030 .delay 1 (30000,30000,30000) L_0x12dc030/d; +v0x10bf0b0_0 .net "a", 0 0, L_0x12e6070; alias, 1 drivers +v0x10bf170_0 .net "b", 0 0, L_0x12db580; alias, 1 drivers +v0x10bf240_0 .net "c1", 0 0, L_0x12dbb10; 1 drivers +v0x10bf340_0 .net "c2", 0 0, L_0x12dbed0; 1 drivers +v0x10bf410_0 .net "carryin", 0 0, L_0x12e62c0; alias, 1 drivers +v0x10bf500_0 .net "carryout", 0 0, L_0x12dc030; 1 drivers +v0x10bf5a0_0 .net "s1", 0 0, L_0x12dba50; 1 drivers +v0x10bf690_0 .net "sum", 0 0, L_0x12dbd80; 1 drivers +S_0x10be4f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10be280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12dba50/d .functor XOR 1, L_0x12e6070, L_0x12db580, C4<0>, C4<0>; +L_0x12dba50 .delay 1 (30000,30000,30000) L_0x12dba50/d; +L_0x12dbb10/d .functor AND 1, L_0x12e6070, L_0x12db580, C4<1>, C4<1>; +L_0x12dbb10 .delay 1 (30000,30000,30000) L_0x12dbb10/d; +v0x10be750_0 .net "a", 0 0, L_0x12e6070; alias, 1 drivers +v0x10be830_0 .net "b", 0 0, L_0x12db580; alias, 1 drivers +v0x10be8f0_0 .net "carryout", 0 0, L_0x12dbb10; alias, 1 drivers +v0x10be990_0 .net "sum", 0 0, L_0x12dba50; alias, 1 drivers +S_0x10bead0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10be280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12dbd80/d .functor XOR 1, L_0x12dba50, L_0x12e62c0, C4<0>, C4<0>; +L_0x12dbd80 .delay 1 (30000,30000,30000) L_0x12dbd80/d; +L_0x12dbed0/d .functor AND 1, L_0x12dba50, L_0x12e62c0, C4<1>, C4<1>; +L_0x12dbed0 .delay 1 (30000,30000,30000) L_0x12dbed0/d; +v0x10bed30_0 .net "a", 0 0, L_0x12dba50; alias, 1 drivers +v0x10bedd0_0 .net "b", 0 0, L_0x12e62c0; alias, 1 drivers +v0x10bee70_0 .net "carryout", 0 0, L_0x12dbed0; alias, 1 drivers +v0x10bef40_0 .net "sum", 0 0, L_0x12dbd80; alias, 1 drivers +S_0x10bf760 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x10be000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10c4b50_0 .net "ands", 7 0, L_0x12e3c10; 1 drivers +v0x10c4c60_0 .net "in", 7 0, L_0x12de500; alias, 1 drivers +v0x10c4d20_0 .net "out", 0 0, L_0x12e5c10; alias, 1 drivers +v0x10c4df0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10bf980 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10bf760; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10c20b0_0 .net "A", 7 0, L_0x12de500; alias, 1 drivers +v0x10c21b0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10c2270_0 .net *"_s0", 0 0, L_0x12e2530; 1 drivers +v0x10c2330_0 .net *"_s12", 0 0, L_0x12e2ea0; 1 drivers +v0x10c2410_0 .net *"_s16", 0 0, L_0x12e3200; 1 drivers +v0x10c2540_0 .net *"_s20", 0 0, L_0x12e35d0; 1 drivers +v0x10c2620_0 .net *"_s24", 0 0, L_0x12e3900; 1 drivers +v0x10c2700_0 .net *"_s28", 0 0, L_0x12e3890; 1 drivers +v0x10c27e0_0 .net *"_s4", 0 0, L_0x12e2880; 1 drivers +v0x10c2950_0 .net *"_s8", 0 0, L_0x12e2b90; 1 drivers +v0x10c2a30_0 .net "out", 7 0, L_0x12e3c10; alias, 1 drivers +L_0x12e25f0 .part L_0x12de500, 0, 1; +L_0x12e27e0 .part v0x127a150_0, 0, 1; +L_0x12e2940 .part L_0x12de500, 1, 1; +L_0x12e2aa0 .part v0x127a150_0, 1, 1; +L_0x12e2c50 .part L_0x12de500, 2, 1; +L_0x12e2db0 .part v0x127a150_0, 2, 1; +L_0x12e2f60 .part L_0x12de500, 3, 1; +L_0x12e30c0 .part v0x127a150_0, 3, 1; +L_0x12e32c0 .part L_0x12de500, 4, 1; +L_0x12e3530 .part v0x127a150_0, 4, 1; +L_0x12e3640 .part L_0x12de500, 5, 1; +L_0x12e37a0 .part v0x127a150_0, 5, 1; +L_0x12e39c0 .part L_0x12de500, 6, 1; +L_0x12e3b20 .part v0x127a150_0, 6, 1; +LS_0x12e3c10_0_0 .concat8 [ 1 1 1 1], L_0x12e2530, L_0x12e2880, L_0x12e2b90, L_0x12e2ea0; +LS_0x12e3c10_0_4 .concat8 [ 1 1 1 1], L_0x12e3200, L_0x12e35d0, L_0x12e3900, L_0x12e3890; +L_0x12e3c10 .concat8 [ 4 4 0 0], LS_0x12e3c10_0_0, LS_0x12e3c10_0_4; +L_0x12e3fd0 .part L_0x12de500, 7, 1; +L_0x12e41c0 .part v0x127a150_0, 7, 1; +S_0x10bfbe0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10bfdf0 .param/l "i" 0 4 54, +C4<00>; +L_0x12e2530/d .functor AND 1, L_0x12e25f0, L_0x12e27e0, C4<1>, C4<1>; +L_0x12e2530 .delay 1 (30000,30000,30000) L_0x12e2530/d; +v0x10bfed0_0 .net *"_s0", 0 0, L_0x12e25f0; 1 drivers +v0x10bffb0_0 .net *"_s1", 0 0, L_0x12e27e0; 1 drivers +S_0x10c0090 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c02a0 .param/l "i" 0 4 54, +C4<01>; +L_0x12e2880/d .functor AND 1, L_0x12e2940, L_0x12e2aa0, C4<1>, C4<1>; +L_0x12e2880 .delay 1 (30000,30000,30000) L_0x12e2880/d; +v0x10c0360_0 .net *"_s0", 0 0, L_0x12e2940; 1 drivers +v0x10c0440_0 .net *"_s1", 0 0, L_0x12e2aa0; 1 drivers +S_0x10c0520 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c0730 .param/l "i" 0 4 54, +C4<010>; +L_0x12e2b90/d .functor AND 1, L_0x12e2c50, L_0x12e2db0, C4<1>, C4<1>; +L_0x12e2b90 .delay 1 (30000,30000,30000) L_0x12e2b90/d; +v0x10c07d0_0 .net *"_s0", 0 0, L_0x12e2c50; 1 drivers +v0x10c08b0_0 .net *"_s1", 0 0, L_0x12e2db0; 1 drivers +S_0x10c0990 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c0ba0 .param/l "i" 0 4 54, +C4<011>; +L_0x12e2ea0/d .functor AND 1, L_0x12e2f60, L_0x12e30c0, C4<1>, C4<1>; +L_0x12e2ea0 .delay 1 (30000,30000,30000) L_0x12e2ea0/d; +v0x10c0c60_0 .net *"_s0", 0 0, L_0x12e2f60; 1 drivers +v0x10c0d40_0 .net *"_s1", 0 0, L_0x12e30c0; 1 drivers +S_0x10c0e20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c1080 .param/l "i" 0 4 54, +C4<0100>; +L_0x12e3200/d .functor AND 1, L_0x12e32c0, L_0x12e3530, C4<1>, C4<1>; +L_0x12e3200 .delay 1 (30000,30000,30000) L_0x12e3200/d; +v0x10c1140_0 .net *"_s0", 0 0, L_0x12e32c0; 1 drivers +v0x10c1220_0 .net *"_s1", 0 0, L_0x12e3530; 1 drivers +S_0x10c1300 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c1510 .param/l "i" 0 4 54, +C4<0101>; +L_0x12e35d0/d .functor AND 1, L_0x12e3640, L_0x12e37a0, C4<1>, C4<1>; +L_0x12e35d0 .delay 1 (30000,30000,30000) L_0x12e35d0/d; +v0x10c15d0_0 .net *"_s0", 0 0, L_0x12e3640; 1 drivers +v0x10c16b0_0 .net *"_s1", 0 0, L_0x12e37a0; 1 drivers +S_0x10c1790 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c19a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12e3900/d .functor AND 1, L_0x12e39c0, L_0x12e3b20, C4<1>, C4<1>; +L_0x12e3900 .delay 1 (30000,30000,30000) L_0x12e3900/d; +v0x10c1a60_0 .net *"_s0", 0 0, L_0x12e39c0; 1 drivers +v0x10c1b40_0 .net *"_s1", 0 0, L_0x12e3b20; 1 drivers +S_0x10c1c20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10bf980; + .timescale -9 -12; +P_0x10c1e30 .param/l "i" 0 4 54, +C4<0111>; +L_0x12e3890/d .functor AND 1, L_0x12e3fd0, L_0x12e41c0, C4<1>, C4<1>; +L_0x12e3890 .delay 1 (30000,30000,30000) L_0x12e3890/d; +v0x10c1ef0_0 .net *"_s0", 0 0, L_0x12e3fd0; 1 drivers +v0x10c1fd0_0 .net *"_s1", 0 0, L_0x12e41c0; 1 drivers +S_0x10c2b90 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10bf760; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12e5c10/d .functor OR 1, L_0x12e5cd0, L_0x12e5e80, C4<0>, C4<0>; +L_0x12e5c10 .delay 1 (30000,30000,30000) L_0x12e5c10/d; +v0x10c46e0_0 .net *"_s10", 0 0, L_0x12e5cd0; 1 drivers +v0x10c47c0_0 .net *"_s12", 0 0, L_0x12e5e80; 1 drivers +v0x10c48a0_0 .net "in", 7 0, L_0x12e3c10; alias, 1 drivers +v0x10c4970_0 .net "ors", 1 0, L_0x12e5a30; 1 drivers +v0x10c4a30_0 .net "out", 0 0, L_0x12e5c10; alias, 1 drivers +L_0x12e4e00 .part L_0x12e3c10, 0, 4; +L_0x12e5a30 .concat8 [ 1 1 0 0], L_0x12e4af0, L_0x12e5720; +L_0x12e5b70 .part L_0x12e3c10, 4, 4; +L_0x12e5cd0 .part L_0x12e5a30, 0, 1; +L_0x12e5e80 .part L_0x12e5a30, 1, 1; +S_0x10c2d50 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10c2b90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12e42b0/d .functor OR 1, L_0x12e4370, L_0x12e44d0, C4<0>, C4<0>; +L_0x12e42b0 .delay 1 (30000,30000,30000) L_0x12e42b0/d; +L_0x12e4700/d .functor OR 1, L_0x12e4810, L_0x12e4970, C4<0>, C4<0>; +L_0x12e4700 .delay 1 (30000,30000,30000) L_0x12e4700/d; +L_0x12e4af0/d .functor OR 1, L_0x12e4b60, L_0x12e4d10, C4<0>, C4<0>; +L_0x12e4af0 .delay 1 (30000,30000,30000) L_0x12e4af0/d; +v0x10c2fa0_0 .net *"_s0", 0 0, L_0x12e42b0; 1 drivers +v0x10c30a0_0 .net *"_s10", 0 0, L_0x12e4810; 1 drivers +v0x10c3180_0 .net *"_s12", 0 0, L_0x12e4970; 1 drivers +v0x10c3240_0 .net *"_s14", 0 0, L_0x12e4b60; 1 drivers +v0x10c3320_0 .net *"_s16", 0 0, L_0x12e4d10; 1 drivers +v0x10c3450_0 .net *"_s3", 0 0, L_0x12e4370; 1 drivers +v0x10c3530_0 .net *"_s5", 0 0, L_0x12e44d0; 1 drivers +v0x10c3610_0 .net *"_s6", 0 0, L_0x12e4700; 1 drivers +v0x10c36f0_0 .net "in", 3 0, L_0x12e4e00; 1 drivers +v0x10c3860_0 .net "ors", 1 0, L_0x12e4610; 1 drivers +v0x10c3940_0 .net "out", 0 0, L_0x12e4af0; 1 drivers +L_0x12e4370 .part L_0x12e4e00, 0, 1; +L_0x12e44d0 .part L_0x12e4e00, 1, 1; +L_0x12e4610 .concat8 [ 1 1 0 0], L_0x12e42b0, L_0x12e4700; +L_0x12e4810 .part L_0x12e4e00, 2, 1; +L_0x12e4970 .part L_0x12e4e00, 3, 1; +L_0x12e4b60 .part L_0x12e4610, 0, 1; +L_0x12e4d10 .part L_0x12e4610, 1, 1; +S_0x10c3a60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10c2b90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12e4f30/d .functor OR 1, L_0x12e4fa0, L_0x12e5100, C4<0>, C4<0>; +L_0x12e4f30 .delay 1 (30000,30000,30000) L_0x12e4f30/d; +L_0x12e5330/d .functor OR 1, L_0x12e5440, L_0x12e55a0, C4<0>, C4<0>; +L_0x12e5330 .delay 1 (30000,30000,30000) L_0x12e5330/d; +L_0x12e5720/d .functor OR 1, L_0x12e5790, L_0x12e5940, C4<0>, C4<0>; +L_0x12e5720 .delay 1 (30000,30000,30000) L_0x12e5720/d; +v0x10c3c20_0 .net *"_s0", 0 0, L_0x12e4f30; 1 drivers +v0x10c3d20_0 .net *"_s10", 0 0, L_0x12e5440; 1 drivers +v0x10c3e00_0 .net *"_s12", 0 0, L_0x12e55a0; 1 drivers +v0x10c3ec0_0 .net *"_s14", 0 0, L_0x12e5790; 1 drivers +v0x10c3fa0_0 .net *"_s16", 0 0, L_0x12e5940; 1 drivers +v0x10c40d0_0 .net *"_s3", 0 0, L_0x12e4fa0; 1 drivers +v0x10c41b0_0 .net *"_s5", 0 0, L_0x12e5100; 1 drivers +v0x10c4290_0 .net *"_s6", 0 0, L_0x12e5330; 1 drivers +v0x10c4370_0 .net "in", 3 0, L_0x12e5b70; 1 drivers +v0x10c44e0_0 .net "ors", 1 0, L_0x12e5240; 1 drivers +v0x10c45c0_0 .net "out", 0 0, L_0x12e5720; 1 drivers +L_0x12e4fa0 .part L_0x12e5b70, 0, 1; +L_0x12e5100 .part L_0x12e5b70, 1, 1; +L_0x12e5240 .concat8 [ 1 1 0 0], L_0x12e4f30, L_0x12e5330; +L_0x12e5440 .part L_0x12e5b70, 2, 1; +L_0x12e55a0 .part L_0x12e5b70, 3, 1; +L_0x12e5790 .part L_0x12e5240, 0, 1; +L_0x12e5940 .part L_0x12e5240, 1, 1; +S_0x10c4ed0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x10be000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10ca300_0 .net "ands", 7 0, L_0x12e01d0; 1 drivers +v0x10ca410_0 .net "in", 7 0, L_0x12de150; alias, 1 drivers +v0x10ca4d0_0 .net "out", 0 0, L_0x12e21d0; alias, 1 drivers +v0x10ca5a0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10c5120 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10c4ed0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10c7860_0 .net "A", 7 0, L_0x12de150; alias, 1 drivers +v0x10c7960_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10c7a20_0 .net *"_s0", 0 0, L_0x12dea20; 1 drivers +v0x10c7ae0_0 .net *"_s12", 0 0, L_0x12df3e0; 1 drivers +v0x10c7bc0_0 .net *"_s16", 0 0, L_0x12df740; 1 drivers +v0x10c7cf0_0 .net *"_s20", 0 0, L_0x12dfb10; 1 drivers +v0x10c7dd0_0 .net *"_s24", 0 0, L_0x12dfe40; 1 drivers +v0x10c7eb0_0 .net *"_s28", 0 0, L_0x12dfdd0; 1 drivers +v0x10c7f90_0 .net *"_s4", 0 0, L_0x12dedc0; 1 drivers +v0x10c8100_0 .net *"_s8", 0 0, L_0x12df0d0; 1 drivers +v0x10c81e0_0 .net "out", 7 0, L_0x12e01d0; alias, 1 drivers +L_0x12deb30 .part L_0x12de150, 0, 1; +L_0x12ded20 .part v0x127a150_0, 0, 1; +L_0x12dee80 .part L_0x12de150, 1, 1; +L_0x12defe0 .part v0x127a150_0, 1, 1; +L_0x12df190 .part L_0x12de150, 2, 1; +L_0x12df2f0 .part v0x127a150_0, 2, 1; +L_0x12df4a0 .part L_0x12de150, 3, 1; +L_0x12df600 .part v0x127a150_0, 3, 1; +L_0x12df800 .part L_0x12de150, 4, 1; +L_0x12dfa70 .part v0x127a150_0, 4, 1; +L_0x12dfb80 .part L_0x12de150, 5, 1; +L_0x12dfce0 .part v0x127a150_0, 5, 1; +L_0x12dff00 .part L_0x12de150, 6, 1; +L_0x12e0060 .part v0x127a150_0, 6, 1; +LS_0x12e01d0_0_0 .concat8 [ 1 1 1 1], L_0x12dea20, L_0x12dedc0, L_0x12df0d0, L_0x12df3e0; +LS_0x12e01d0_0_4 .concat8 [ 1 1 1 1], L_0x12df740, L_0x12dfb10, L_0x12dfe40, L_0x12dfdd0; +L_0x12e01d0 .concat8 [ 4 4 0 0], LS_0x12e01d0_0_0, LS_0x12e01d0_0_4; +L_0x12e0590 .part L_0x12de150, 7, 1; +L_0x12e0780 .part v0x127a150_0, 7, 1; +S_0x10c5360 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c5570 .param/l "i" 0 4 54, +C4<00>; +L_0x12dea20/d .functor AND 1, L_0x12deb30, L_0x12ded20, C4<1>, C4<1>; +L_0x12dea20 .delay 1 (30000,30000,30000) L_0x12dea20/d; +v0x10c5650_0 .net *"_s0", 0 0, L_0x12deb30; 1 drivers +v0x10c5730_0 .net *"_s1", 0 0, L_0x12ded20; 1 drivers +S_0x10c5810 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c5a20 .param/l "i" 0 4 54, +C4<01>; +L_0x12dedc0/d .functor AND 1, L_0x12dee80, L_0x12defe0, C4<1>, C4<1>; +L_0x12dedc0 .delay 1 (30000,30000,30000) L_0x12dedc0/d; +v0x10c5ae0_0 .net *"_s0", 0 0, L_0x12dee80; 1 drivers +v0x10c5bc0_0 .net *"_s1", 0 0, L_0x12defe0; 1 drivers +S_0x10c5ca0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c5ee0 .param/l "i" 0 4 54, +C4<010>; +L_0x12df0d0/d .functor AND 1, L_0x12df190, L_0x12df2f0, C4<1>, C4<1>; +L_0x12df0d0 .delay 1 (30000,30000,30000) L_0x12df0d0/d; +v0x10c5f80_0 .net *"_s0", 0 0, L_0x12df190; 1 drivers +v0x10c6060_0 .net *"_s1", 0 0, L_0x12df2f0; 1 drivers +S_0x10c6140 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c6350 .param/l "i" 0 4 54, +C4<011>; +L_0x12df3e0/d .functor AND 1, L_0x12df4a0, L_0x12df600, C4<1>, C4<1>; +L_0x12df3e0 .delay 1 (30000,30000,30000) L_0x12df3e0/d; +v0x10c6410_0 .net *"_s0", 0 0, L_0x12df4a0; 1 drivers +v0x10c64f0_0 .net *"_s1", 0 0, L_0x12df600; 1 drivers +S_0x10c65d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c6830 .param/l "i" 0 4 54, +C4<0100>; +L_0x12df740/d .functor AND 1, L_0x12df800, L_0x12dfa70, C4<1>, C4<1>; +L_0x12df740 .delay 1 (30000,30000,30000) L_0x12df740/d; +v0x10c68f0_0 .net *"_s0", 0 0, L_0x12df800; 1 drivers +v0x10c69d0_0 .net *"_s1", 0 0, L_0x12dfa70; 1 drivers +S_0x10c6ab0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c6cc0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12dfb10/d .functor AND 1, L_0x12dfb80, L_0x12dfce0, C4<1>, C4<1>; +L_0x12dfb10 .delay 1 (30000,30000,30000) L_0x12dfb10/d; +v0x10c6d80_0 .net *"_s0", 0 0, L_0x12dfb80; 1 drivers +v0x10c6e60_0 .net *"_s1", 0 0, L_0x12dfce0; 1 drivers +S_0x10c6f40 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c7150 .param/l "i" 0 4 54, +C4<0110>; +L_0x12dfe40/d .functor AND 1, L_0x12dff00, L_0x12e0060, C4<1>, C4<1>; +L_0x12dfe40 .delay 1 (30000,30000,30000) L_0x12dfe40/d; +v0x10c7210_0 .net *"_s0", 0 0, L_0x12dff00; 1 drivers +v0x10c72f0_0 .net *"_s1", 0 0, L_0x12e0060; 1 drivers +S_0x10c73d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10c5120; + .timescale -9 -12; +P_0x10c75e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12dfdd0/d .functor AND 1, L_0x12e0590, L_0x12e0780, C4<1>, C4<1>; +L_0x12dfdd0 .delay 1 (30000,30000,30000) L_0x12dfdd0/d; +v0x10c76a0_0 .net *"_s0", 0 0, L_0x12e0590; 1 drivers +v0x10c7780_0 .net *"_s1", 0 0, L_0x12e0780; 1 drivers +S_0x10c8340 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10c4ed0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12e21d0/d .functor OR 1, L_0x12e2290, L_0x12e2440, C4<0>, C4<0>; +L_0x12e21d0 .delay 1 (30000,30000,30000) L_0x12e21d0/d; +v0x10c9e90_0 .net *"_s10", 0 0, L_0x12e2290; 1 drivers +v0x10c9f70_0 .net *"_s12", 0 0, L_0x12e2440; 1 drivers +v0x10ca050_0 .net "in", 7 0, L_0x12e01d0; alias, 1 drivers +v0x10ca120_0 .net "ors", 1 0, L_0x12e1ff0; 1 drivers +v0x10ca1e0_0 .net "out", 0 0, L_0x12e21d0; alias, 1 drivers +L_0x12e13c0 .part L_0x12e01d0, 0, 4; +L_0x12e1ff0 .concat8 [ 1 1 0 0], L_0x12e10b0, L_0x12e1ce0; +L_0x12e2130 .part L_0x12e01d0, 4, 4; +L_0x12e2290 .part L_0x12e1ff0, 0, 1; +L_0x12e2440 .part L_0x12e1ff0, 1, 1; +S_0x10c8500 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10c8340; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12e0870/d .functor OR 1, L_0x12e0930, L_0x12e0a90, C4<0>, C4<0>; +L_0x12e0870 .delay 1 (30000,30000,30000) L_0x12e0870/d; +L_0x12e0cc0/d .functor OR 1, L_0x12e0dd0, L_0x12e0f30, C4<0>, C4<0>; +L_0x12e0cc0 .delay 1 (30000,30000,30000) L_0x12e0cc0/d; +L_0x12e10b0/d .functor OR 1, L_0x12e1120, L_0x12e12d0, C4<0>, C4<0>; +L_0x12e10b0 .delay 1 (30000,30000,30000) L_0x12e10b0/d; +v0x10c8750_0 .net *"_s0", 0 0, L_0x12e0870; 1 drivers +v0x10c8850_0 .net *"_s10", 0 0, L_0x12e0dd0; 1 drivers +v0x10c8930_0 .net *"_s12", 0 0, L_0x12e0f30; 1 drivers +v0x10c89f0_0 .net *"_s14", 0 0, L_0x12e1120; 1 drivers +v0x10c8ad0_0 .net *"_s16", 0 0, L_0x12e12d0; 1 drivers +v0x10c8c00_0 .net *"_s3", 0 0, L_0x12e0930; 1 drivers +v0x10c8ce0_0 .net *"_s5", 0 0, L_0x12e0a90; 1 drivers +v0x10c8dc0_0 .net *"_s6", 0 0, L_0x12e0cc0; 1 drivers +v0x10c8ea0_0 .net "in", 3 0, L_0x12e13c0; 1 drivers +v0x10c9010_0 .net "ors", 1 0, L_0x12e0bd0; 1 drivers +v0x10c90f0_0 .net "out", 0 0, L_0x12e10b0; 1 drivers +L_0x12e0930 .part L_0x12e13c0, 0, 1; +L_0x12e0a90 .part L_0x12e13c0, 1, 1; +L_0x12e0bd0 .concat8 [ 1 1 0 0], L_0x12e0870, L_0x12e0cc0; +L_0x12e0dd0 .part L_0x12e13c0, 2, 1; +L_0x12e0f30 .part L_0x12e13c0, 3, 1; +L_0x12e1120 .part L_0x12e0bd0, 0, 1; +L_0x12e12d0 .part L_0x12e0bd0, 1, 1; +S_0x10c9210 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10c8340; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12e14f0/d .functor OR 1, L_0x12e1560, L_0x12e16c0, C4<0>, C4<0>; +L_0x12e14f0 .delay 1 (30000,30000,30000) L_0x12e14f0/d; +L_0x12e18f0/d .functor OR 1, L_0x12e1a00, L_0x12e1b60, C4<0>, C4<0>; +L_0x12e18f0 .delay 1 (30000,30000,30000) L_0x12e18f0/d; +L_0x12e1ce0/d .functor OR 1, L_0x12e1d50, L_0x12e1f00, C4<0>, C4<0>; +L_0x12e1ce0 .delay 1 (30000,30000,30000) L_0x12e1ce0/d; +v0x10c93d0_0 .net *"_s0", 0 0, L_0x12e14f0; 1 drivers +v0x10c94d0_0 .net *"_s10", 0 0, L_0x12e1a00; 1 drivers +v0x10c95b0_0 .net *"_s12", 0 0, L_0x12e1b60; 1 drivers +v0x10c9670_0 .net *"_s14", 0 0, L_0x12e1d50; 1 drivers +v0x10c9750_0 .net *"_s16", 0 0, L_0x12e1f00; 1 drivers +v0x10c9880_0 .net *"_s3", 0 0, L_0x12e1560; 1 drivers +v0x10c9960_0 .net *"_s5", 0 0, L_0x12e16c0; 1 drivers +v0x10c9a40_0 .net *"_s6", 0 0, L_0x12e18f0; 1 drivers +v0x10c9b20_0 .net "in", 3 0, L_0x12e2130; 1 drivers +v0x10c9c90_0 .net "ors", 1 0, L_0x12e1800; 1 drivers +v0x10c9d70_0 .net "out", 0 0, L_0x12e1ce0; 1 drivers +L_0x12e1560 .part L_0x12e2130, 0, 1; +L_0x12e16c0 .part L_0x12e2130, 1, 1; +L_0x12e1800 .concat8 [ 1 1 0 0], L_0x12e14f0, L_0x12e18f0; +L_0x12e1a00 .part L_0x12e2130, 2, 1; +L_0x12e1b60 .part L_0x12e2130, 3, 1; +L_0x12e1d50 .part L_0x12e1800, 0, 1; +L_0x12e1f00 .part L_0x12e1800, 1, 1; +S_0x10ca680 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x10be000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12dcb70/d .functor XNOR 1, L_0x12e6070, L_0x12db580, C4<0>, C4<0>; +L_0x12dcb70 .delay 1 (20000,20000,20000) L_0x12dcb70/d; +L_0x12dccf0/d .functor AND 1, L_0x12e6070, L_0x12db860, C4<1>, C4<1>; +L_0x12dccf0 .delay 1 (30000,30000,30000) L_0x12dccf0/d; +L_0x12dce50/d .functor AND 1, L_0x12dcb70, L_0x12e62c0, C4<1>, C4<1>; +L_0x12dce50 .delay 1 (30000,30000,30000) L_0x12dce50/d; +L_0x12dcf60/d .functor OR 1, L_0x12dce50, L_0x12dccf0, C4<0>, C4<0>; +L_0x12dcf60 .delay 1 (30000,30000,30000) L_0x12dcf60/d; +v0x10ca930_0 .net "a", 0 0, L_0x12e6070; alias, 1 drivers +v0x10caa20_0 .net "a_", 0 0, L_0x12db700; alias, 1 drivers +v0x10caae0_0 .net "b", 0 0, L_0x12db580; alias, 1 drivers +v0x10cabd0_0 .net "b_", 0 0, L_0x12db860; alias, 1 drivers +v0x10cac70_0 .net "carryin", 0 0, L_0x12e62c0; alias, 1 drivers +v0x10cadb0_0 .net "eq", 0 0, L_0x12dcb70; 1 drivers +v0x10cae70_0 .net "lt", 0 0, L_0x12dccf0; 1 drivers +v0x10caf30_0 .net "out", 0 0, L_0x12dcf60; 1 drivers +v0x10caff0_0 .net "w0", 0 0, L_0x12dce50; 1 drivers +S_0x10cb240 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10be000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12dc750/d .functor OR 1, L_0x12dc250, L_0x10cc4a0, C4<0>, C4<0>; +L_0x12dc750 .delay 1 (30000,30000,30000) L_0x12dc750/d; +v0x10cc030_0 .net "a", 0 0, L_0x12e6070; alias, 1 drivers +v0x10cc180_0 .net "b", 0 0, L_0x12db860; alias, 1 drivers +v0x10cc240_0 .net "c1", 0 0, L_0x12dc250; 1 drivers +v0x10cc2e0_0 .net "c2", 0 0, L_0x10cc4a0; 1 drivers +v0x10cc3b0_0 .net "carryin", 0 0, L_0x12e62c0; alias, 1 drivers +v0x10cc530_0 .net "carryout", 0 0, L_0x12dc750; 1 drivers +v0x10cc5d0_0 .net "s1", 0 0, L_0x12dc190; 1 drivers +v0x10cc670_0 .net "sum", 0 0, L_0x12dc3b0; 1 drivers +S_0x10cb490 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10cb240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12dc190/d .functor XOR 1, L_0x12e6070, L_0x12db860, C4<0>, C4<0>; +L_0x12dc190 .delay 1 (30000,30000,30000) L_0x12dc190/d; +L_0x12dc250/d .functor AND 1, L_0x12e6070, L_0x12db860, C4<1>, C4<1>; +L_0x12dc250 .delay 1 (30000,30000,30000) L_0x12dc250/d; +v0x10cb6f0_0 .net "a", 0 0, L_0x12e6070; alias, 1 drivers +v0x10cb7b0_0 .net "b", 0 0, L_0x12db860; alias, 1 drivers +v0x10cb870_0 .net "carryout", 0 0, L_0x12dc250; alias, 1 drivers +v0x10cb910_0 .net "sum", 0 0, L_0x12dc190; alias, 1 drivers +S_0x10cba40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10cb240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12dc3b0/d .functor XOR 1, L_0x12dc190, L_0x12e62c0, C4<0>, C4<0>; +L_0x12dc3b0 .delay 1 (30000,30000,30000) L_0x12dc3b0/d; +L_0x10cc4a0/d .functor AND 1, L_0x12dc190, L_0x12e62c0, C4<1>, C4<1>; +L_0x10cc4a0 .delay 1 (30000,30000,30000) L_0x10cc4a0/d; +v0x10cbca0_0 .net "a", 0 0, L_0x12dc190; alias, 1 drivers +v0x10cbd70_0 .net "b", 0 0, L_0x12e62c0; alias, 1 drivers +v0x10cbe10_0 .net "carryout", 0 0, L_0x10cc4a0; alias, 1 drivers +v0x10cbee0_0 .net "sum", 0 0, L_0x12dc3b0; alias, 1 drivers +S_0x10ce700 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x10bdd30; + .timescale -9 -12; +L_0x2ac432885658 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328856a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12de490/d .functor OR 1, L_0x2ac432885658, L_0x2ac4328856a0, C4<0>, C4<0>; +L_0x12de490 .delay 1 (30000,30000,30000) L_0x12de490/d; +v0x10ce8f0_0 .net/2u *"_s0", 0 0, L_0x2ac432885658; 1 drivers +v0x10ce9d0_0 .net/2u *"_s2", 0 0, L_0x2ac4328856a0; 1 drivers +S_0x10ceab0 .scope generate, "alu_slices[10]" "alu_slices[10]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x10cecc0 .param/l "i" 0 3 39, +C4<01010>; +S_0x10ced80 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x10ceab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12e6460/d .functor NOT 1, L_0x12f08d0, C4<0>, C4<0>, C4<0>; +L_0x12e6460 .delay 1 (10000,10000,10000) L_0x12e6460/d; +L_0x12e6570/d .functor NOT 1, L_0x12f0a30, C4<0>, C4<0>, C4<0>; +L_0x12e6570 .delay 1 (10000,10000,10000) L_0x12e6570/d; +L_0x12e7520/d .functor XOR 1, L_0x12f08d0, L_0x12f0a30, C4<0>, C4<0>; +L_0x12e7520 .delay 1 (30000,30000,30000) L_0x12e7520/d; +L_0x2ac4328856e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885730 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e75e0/d .functor OR 1, L_0x2ac4328856e8, L_0x2ac432885730, C4<0>, C4<0>; +L_0x12e75e0 .delay 1 (30000,30000,30000) L_0x12e75e0/d; +L_0x2ac432885778 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328857c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e7d80/d .functor OR 1, L_0x2ac432885778, L_0x2ac4328857c0, C4<0>, C4<0>; +L_0x12e7d80 .delay 1 (30000,30000,30000) L_0x12e7d80/d; +L_0x12e7f80/d .functor AND 1, L_0x12f08d0, L_0x12f0a30, C4<1>, C4<1>; +L_0x12e7f80 .delay 1 (30000,30000,30000) L_0x12e7f80/d; +L_0x2ac432885808 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885850 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e8040/d .functor OR 1, L_0x2ac432885808, L_0x2ac432885850, C4<0>, C4<0>; +L_0x12e8040 .delay 1 (30000,30000,30000) L_0x12e8040/d; +L_0x12e8240/d .functor NAND 1, L_0x12f08d0, L_0x12f0a30, C4<1>, C4<1>; +L_0x12e8240 .delay 1 (20000,20000,20000) L_0x12e8240/d; +L_0x2ac432885898 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328858e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e8350/d .functor OR 1, L_0x2ac432885898, L_0x2ac4328858e0, C4<0>, C4<0>; +L_0x12e8350 .delay 1 (30000,30000,30000) L_0x12e8350/d; +L_0x12e8500/d .functor NOR 1, L_0x12f08d0, L_0x12f0a30, C4<0>, C4<0>; +L_0x12e8500 .delay 1 (20000,20000,20000) L_0x12e8500/d; +L_0x2ac432885928 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885970 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e87d0/d .functor OR 1, L_0x2ac432885928, L_0x2ac432885970, C4<0>, C4<0>; +L_0x12e87d0 .delay 1 (30000,30000,30000) L_0x12e87d0/d; +L_0x12e8bd0/d .functor OR 1, L_0x12f08d0, L_0x12f0a30, C4<0>, C4<0>; +L_0x12e8bd0 .delay 1 (30000,30000,30000) L_0x12e8bd0/d; +L_0x2ac4328859b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885a00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e9070/d .functor OR 1, L_0x2ac4328859b8, L_0x2ac432885a00, C4<0>, C4<0>; +L_0x12e9070 .delay 1 (30000,30000,30000) L_0x12e9070/d; +L_0x12f07d0/d .functor NOT 1, L_0x12eca30, C4<0>, C4<0>, C4<0>; +L_0x12f07d0 .delay 1 (10000,10000,10000) L_0x12f07d0/d; +v0x10dd4d0_0 .net "A", 0 0, L_0x12f08d0; 1 drivers +v0x10dd590_0 .net "A_", 0 0, L_0x12e6460; 1 drivers +v0x10dd650_0 .net "B", 0 0, L_0x12f0a30; 1 drivers +v0x10dd720_0 .net "B_", 0 0, L_0x12e6570; 1 drivers +v0x10dd7c0_0 .net *"_s11", 0 0, L_0x12e75e0; 1 drivers +v0x10dd8b0_0 .net/2s *"_s13", 0 0, L_0x2ac4328856e8; 1 drivers +v0x10dd970_0 .net/2s *"_s15", 0 0, L_0x2ac432885730; 1 drivers +v0x10dda50_0 .net *"_s19", 0 0, L_0x12e7d80; 1 drivers +v0x10ddb30_0 .net/2s *"_s21", 0 0, L_0x2ac432885778; 1 drivers +v0x10ddca0_0 .net/2s *"_s23", 0 0, L_0x2ac4328857c0; 1 drivers +v0x10ddd80_0 .net *"_s25", 0 0, L_0x12e7f80; 1 drivers +v0x10dde60_0 .net *"_s28", 0 0, L_0x12e8040; 1 drivers +v0x10ddf40_0 .net/2s *"_s30", 0 0, L_0x2ac432885808; 1 drivers +v0x10de020_0 .net/2s *"_s32", 0 0, L_0x2ac432885850; 1 drivers +v0x10de100_0 .net *"_s34", 0 0, L_0x12e8240; 1 drivers +v0x10de1e0_0 .net *"_s37", 0 0, L_0x12e8350; 1 drivers +v0x10de2c0_0 .net/2s *"_s39", 0 0, L_0x2ac432885898; 1 drivers +v0x10de470_0 .net/2s *"_s41", 0 0, L_0x2ac4328858e0; 1 drivers +v0x10de510_0 .net *"_s43", 0 0, L_0x12e8500; 1 drivers +v0x10de5f0_0 .net *"_s46", 0 0, L_0x12e87d0; 1 drivers +v0x10de6d0_0 .net/2s *"_s48", 0 0, L_0x2ac432885928; 1 drivers +v0x10de7b0_0 .net/2s *"_s50", 0 0, L_0x2ac432885970; 1 drivers +v0x10de890_0 .net *"_s52", 0 0, L_0x12e8bd0; 1 drivers +v0x10de970_0 .net *"_s56", 0 0, L_0x12e9070; 1 drivers +v0x10dea50_0 .net/2s *"_s59", 0 0, L_0x2ac4328859b8; 1 drivers +v0x10deb30_0 .net/2s *"_s61", 0 0, L_0x2ac432885a00; 1 drivers +v0x10dec10_0 .net *"_s8", 0 0, L_0x12e7520; 1 drivers +v0x10decf0_0 .net "carryin", 0 0, L_0x12e6360; 1 drivers +v0x10ded90_0 .net "carryout", 0 0, L_0x12f0470; 1 drivers +v0x10dee30_0 .net "carryouts", 7 0, L_0x12e8ce0; 1 drivers +v0x10def40_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x10df000_0 .net "result", 0 0, L_0x12eca30; 1 drivers +v0x10df0f0_0 .net "results", 7 0, L_0x12e89a0; 1 drivers +v0x10de3d0_0 .net "zero", 0 0, L_0x12f07d0; 1 drivers +LS_0x12e89a0_0_0 .concat8 [ 1 1 1 1], L_0x12e6a90, L_0x12e7070, L_0x12e7520, L_0x12e7d80; +LS_0x12e89a0_0_4 .concat8 [ 1 1 1 1], L_0x12e7f80, L_0x12e8240, L_0x12e8500, L_0x12e8bd0; +L_0x12e89a0 .concat8 [ 4 4 0 0], LS_0x12e89a0_0_0, LS_0x12e89a0_0_4; +LS_0x12e8ce0_0_0 .concat8 [ 1 1 1 1], L_0x12e6d40, L_0x12e73c0, L_0x12e75e0, L_0x12e7bd0; +LS_0x12e8ce0_0_4 .concat8 [ 1 1 1 1], L_0x12e8040, L_0x12e8350, L_0x12e87d0, L_0x12e9070; +L_0x12e8ce0 .concat8 [ 4 4 0 0], LS_0x12e8ce0_0_0, LS_0x12e8ce0_0_4; +S_0x10cf000 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10ced80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12e6d40/d .functor OR 1, L_0x12e6820, L_0x12e6be0, C4<0>, C4<0>; +L_0x12e6d40 .delay 1 (30000,30000,30000) L_0x12e6d40/d; +v0x10cfe30_0 .net "a", 0 0, L_0x12f08d0; alias, 1 drivers +v0x10cfef0_0 .net "b", 0 0, L_0x12f0a30; alias, 1 drivers +v0x10cffc0_0 .net "c1", 0 0, L_0x12e6820; 1 drivers +v0x10d00c0_0 .net "c2", 0 0, L_0x12e6be0; 1 drivers +v0x10d0190_0 .net "carryin", 0 0, L_0x12e6360; alias, 1 drivers +v0x10d0280_0 .net "carryout", 0 0, L_0x12e6d40; 1 drivers +v0x10d0320_0 .net "s1", 0 0, L_0x12e6760; 1 drivers +v0x10d0410_0 .net "sum", 0 0, L_0x12e6a90; 1 drivers +S_0x10cf270 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10cf000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12e6760/d .functor XOR 1, L_0x12f08d0, L_0x12f0a30, C4<0>, C4<0>; +L_0x12e6760 .delay 1 (30000,30000,30000) L_0x12e6760/d; +L_0x12e6820/d .functor AND 1, L_0x12f08d0, L_0x12f0a30, C4<1>, C4<1>; +L_0x12e6820 .delay 1 (30000,30000,30000) L_0x12e6820/d; +v0x10cf4d0_0 .net "a", 0 0, L_0x12f08d0; alias, 1 drivers +v0x10cf5b0_0 .net "b", 0 0, L_0x12f0a30; alias, 1 drivers +v0x10cf670_0 .net "carryout", 0 0, L_0x12e6820; alias, 1 drivers +v0x10cf710_0 .net "sum", 0 0, L_0x12e6760; alias, 1 drivers +S_0x10cf850 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10cf000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12e6a90/d .functor XOR 1, L_0x12e6760, L_0x12e6360, C4<0>, C4<0>; +L_0x12e6a90 .delay 1 (30000,30000,30000) L_0x12e6a90/d; +L_0x12e6be0/d .functor AND 1, L_0x12e6760, L_0x12e6360, C4<1>, C4<1>; +L_0x12e6be0 .delay 1 (30000,30000,30000) L_0x12e6be0/d; +v0x10cfab0_0 .net "a", 0 0, L_0x12e6760; alias, 1 drivers +v0x10cfb50_0 .net "b", 0 0, L_0x12e6360; alias, 1 drivers +v0x10cfbf0_0 .net "carryout", 0 0, L_0x12e6be0; alias, 1 drivers +v0x10cfcc0_0 .net "sum", 0 0, L_0x12e6a90; alias, 1 drivers +S_0x10d04e0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x10ced80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10d58d0_0 .net "ands", 7 0, L_0x12ee470; 1 drivers +v0x10d59e0_0 .net "in", 7 0, L_0x12e8ce0; alias, 1 drivers +v0x10d5aa0_0 .net "out", 0 0, L_0x12f0470; alias, 1 drivers +v0x10d5b70_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10d0700 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10d04e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10d2e30_0 .net "A", 7 0, L_0x12e8ce0; alias, 1 drivers +v0x10d2f30_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10d2ff0_0 .net *"_s0", 0 0, L_0x12ecd90; 1 drivers +v0x10d30b0_0 .net *"_s12", 0 0, L_0x12ed700; 1 drivers +v0x10d3190_0 .net *"_s16", 0 0, L_0x12eda60; 1 drivers +v0x10d32c0_0 .net *"_s20", 0 0, L_0x12ede30; 1 drivers +v0x10d33a0_0 .net *"_s24", 0 0, L_0x12ee160; 1 drivers +v0x10d3480_0 .net *"_s28", 0 0, L_0x12ee0f0; 1 drivers +v0x10d3560_0 .net *"_s4", 0 0, L_0x12ed0e0; 1 drivers +v0x10d36d0_0 .net *"_s8", 0 0, L_0x12ed3f0; 1 drivers +v0x10d37b0_0 .net "out", 7 0, L_0x12ee470; alias, 1 drivers +L_0x12ece50 .part L_0x12e8ce0, 0, 1; +L_0x12ed040 .part v0x127a150_0, 0, 1; +L_0x12ed1a0 .part L_0x12e8ce0, 1, 1; +L_0x12ed300 .part v0x127a150_0, 1, 1; +L_0x12ed4b0 .part L_0x12e8ce0, 2, 1; +L_0x12ed610 .part v0x127a150_0, 2, 1; +L_0x12ed7c0 .part L_0x12e8ce0, 3, 1; +L_0x12ed920 .part v0x127a150_0, 3, 1; +L_0x12edb20 .part L_0x12e8ce0, 4, 1; +L_0x12edd90 .part v0x127a150_0, 4, 1; +L_0x12edea0 .part L_0x12e8ce0, 5, 1; +L_0x12ee000 .part v0x127a150_0, 5, 1; +L_0x12ee220 .part L_0x12e8ce0, 6, 1; +L_0x12ee380 .part v0x127a150_0, 6, 1; +LS_0x12ee470_0_0 .concat8 [ 1 1 1 1], L_0x12ecd90, L_0x12ed0e0, L_0x12ed3f0, L_0x12ed700; +LS_0x12ee470_0_4 .concat8 [ 1 1 1 1], L_0x12eda60, L_0x12ede30, L_0x12ee160, L_0x12ee0f0; +L_0x12ee470 .concat8 [ 4 4 0 0], LS_0x12ee470_0_0, LS_0x12ee470_0_4; +L_0x12ee830 .part L_0x12e8ce0, 7, 1; +L_0x12eea20 .part v0x127a150_0, 7, 1; +S_0x10d0960 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d0b70 .param/l "i" 0 4 54, +C4<00>; +L_0x12ecd90/d .functor AND 1, L_0x12ece50, L_0x12ed040, C4<1>, C4<1>; +L_0x12ecd90 .delay 1 (30000,30000,30000) L_0x12ecd90/d; +v0x10d0c50_0 .net *"_s0", 0 0, L_0x12ece50; 1 drivers +v0x10d0d30_0 .net *"_s1", 0 0, L_0x12ed040; 1 drivers +S_0x10d0e10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d1020 .param/l "i" 0 4 54, +C4<01>; +L_0x12ed0e0/d .functor AND 1, L_0x12ed1a0, L_0x12ed300, C4<1>, C4<1>; +L_0x12ed0e0 .delay 1 (30000,30000,30000) L_0x12ed0e0/d; +v0x10d10e0_0 .net *"_s0", 0 0, L_0x12ed1a0; 1 drivers +v0x10d11c0_0 .net *"_s1", 0 0, L_0x12ed300; 1 drivers +S_0x10d12a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d14b0 .param/l "i" 0 4 54, +C4<010>; +L_0x12ed3f0/d .functor AND 1, L_0x12ed4b0, L_0x12ed610, C4<1>, C4<1>; +L_0x12ed3f0 .delay 1 (30000,30000,30000) L_0x12ed3f0/d; +v0x10d1550_0 .net *"_s0", 0 0, L_0x12ed4b0; 1 drivers +v0x10d1630_0 .net *"_s1", 0 0, L_0x12ed610; 1 drivers +S_0x10d1710 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d1920 .param/l "i" 0 4 54, +C4<011>; +L_0x12ed700/d .functor AND 1, L_0x12ed7c0, L_0x12ed920, C4<1>, C4<1>; +L_0x12ed700 .delay 1 (30000,30000,30000) L_0x12ed700/d; +v0x10d19e0_0 .net *"_s0", 0 0, L_0x12ed7c0; 1 drivers +v0x10d1ac0_0 .net *"_s1", 0 0, L_0x12ed920; 1 drivers +S_0x10d1ba0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d1e00 .param/l "i" 0 4 54, +C4<0100>; +L_0x12eda60/d .functor AND 1, L_0x12edb20, L_0x12edd90, C4<1>, C4<1>; +L_0x12eda60 .delay 1 (30000,30000,30000) L_0x12eda60/d; +v0x10d1ec0_0 .net *"_s0", 0 0, L_0x12edb20; 1 drivers +v0x10d1fa0_0 .net *"_s1", 0 0, L_0x12edd90; 1 drivers +S_0x10d2080 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d2290 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ede30/d .functor AND 1, L_0x12edea0, L_0x12ee000, C4<1>, C4<1>; +L_0x12ede30 .delay 1 (30000,30000,30000) L_0x12ede30/d; +v0x10d2350_0 .net *"_s0", 0 0, L_0x12edea0; 1 drivers +v0x10d2430_0 .net *"_s1", 0 0, L_0x12ee000; 1 drivers +S_0x10d2510 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d2720 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ee160/d .functor AND 1, L_0x12ee220, L_0x12ee380, C4<1>, C4<1>; +L_0x12ee160 .delay 1 (30000,30000,30000) L_0x12ee160/d; +v0x10d27e0_0 .net *"_s0", 0 0, L_0x12ee220; 1 drivers +v0x10d28c0_0 .net *"_s1", 0 0, L_0x12ee380; 1 drivers +S_0x10d29a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10d0700; + .timescale -9 -12; +P_0x10d2bb0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ee0f0/d .functor AND 1, L_0x12ee830, L_0x12eea20, C4<1>, C4<1>; +L_0x12ee0f0 .delay 1 (30000,30000,30000) L_0x12ee0f0/d; +v0x10d2c70_0 .net *"_s0", 0 0, L_0x12ee830; 1 drivers +v0x10d2d50_0 .net *"_s1", 0 0, L_0x12eea20; 1 drivers +S_0x10d3910 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10d04e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12f0470/d .functor OR 1, L_0x12f0530, L_0x12f06e0, C4<0>, C4<0>; +L_0x12f0470 .delay 1 (30000,30000,30000) L_0x12f0470/d; +v0x10d5460_0 .net *"_s10", 0 0, L_0x12f0530; 1 drivers +v0x10d5540_0 .net *"_s12", 0 0, L_0x12f06e0; 1 drivers +v0x10d5620_0 .net "in", 7 0, L_0x12ee470; alias, 1 drivers +v0x10d56f0_0 .net "ors", 1 0, L_0x12f0290; 1 drivers +v0x10d57b0_0 .net "out", 0 0, L_0x12f0470; alias, 1 drivers +L_0x12ef660 .part L_0x12ee470, 0, 4; +L_0x12f0290 .concat8 [ 1 1 0 0], L_0x12ef350, L_0x12eff80; +L_0x12f03d0 .part L_0x12ee470, 4, 4; +L_0x12f0530 .part L_0x12f0290, 0, 1; +L_0x12f06e0 .part L_0x12f0290, 1, 1; +S_0x10d3ad0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10d3910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12eeb10/d .functor OR 1, L_0x12eebd0, L_0x12eed30, C4<0>, C4<0>; +L_0x12eeb10 .delay 1 (30000,30000,30000) L_0x12eeb10/d; +L_0x12eef60/d .functor OR 1, L_0x12ef070, L_0x12ef1d0, C4<0>, C4<0>; +L_0x12eef60 .delay 1 (30000,30000,30000) L_0x12eef60/d; +L_0x12ef350/d .functor OR 1, L_0x12ef3c0, L_0x12ef570, C4<0>, C4<0>; +L_0x12ef350 .delay 1 (30000,30000,30000) L_0x12ef350/d; +v0x10d3d20_0 .net *"_s0", 0 0, L_0x12eeb10; 1 drivers +v0x10d3e20_0 .net *"_s10", 0 0, L_0x12ef070; 1 drivers +v0x10d3f00_0 .net *"_s12", 0 0, L_0x12ef1d0; 1 drivers +v0x10d3fc0_0 .net *"_s14", 0 0, L_0x12ef3c0; 1 drivers +v0x10d40a0_0 .net *"_s16", 0 0, L_0x12ef570; 1 drivers +v0x10d41d0_0 .net *"_s3", 0 0, L_0x12eebd0; 1 drivers +v0x10d42b0_0 .net *"_s5", 0 0, L_0x12eed30; 1 drivers +v0x10d4390_0 .net *"_s6", 0 0, L_0x12eef60; 1 drivers +v0x10d4470_0 .net "in", 3 0, L_0x12ef660; 1 drivers +v0x10d45e0_0 .net "ors", 1 0, L_0x12eee70; 1 drivers +v0x10d46c0_0 .net "out", 0 0, L_0x12ef350; 1 drivers +L_0x12eebd0 .part L_0x12ef660, 0, 1; +L_0x12eed30 .part L_0x12ef660, 1, 1; +L_0x12eee70 .concat8 [ 1 1 0 0], L_0x12eeb10, L_0x12eef60; +L_0x12ef070 .part L_0x12ef660, 2, 1; +L_0x12ef1d0 .part L_0x12ef660, 3, 1; +L_0x12ef3c0 .part L_0x12eee70, 0, 1; +L_0x12ef570 .part L_0x12eee70, 1, 1; +S_0x10d47e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10d3910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12ef790/d .functor OR 1, L_0x12ef800, L_0x12ef960, C4<0>, C4<0>; +L_0x12ef790 .delay 1 (30000,30000,30000) L_0x12ef790/d; +L_0x12efb90/d .functor OR 1, L_0x12efca0, L_0x12efe00, C4<0>, C4<0>; +L_0x12efb90 .delay 1 (30000,30000,30000) L_0x12efb90/d; +L_0x12eff80/d .functor OR 1, L_0x12efff0, L_0x12f01a0, C4<0>, C4<0>; +L_0x12eff80 .delay 1 (30000,30000,30000) L_0x12eff80/d; +v0x10d49a0_0 .net *"_s0", 0 0, L_0x12ef790; 1 drivers +v0x10d4aa0_0 .net *"_s10", 0 0, L_0x12efca0; 1 drivers +v0x10d4b80_0 .net *"_s12", 0 0, L_0x12efe00; 1 drivers +v0x10d4c40_0 .net *"_s14", 0 0, L_0x12efff0; 1 drivers +v0x10d4d20_0 .net *"_s16", 0 0, L_0x12f01a0; 1 drivers +v0x10d4e50_0 .net *"_s3", 0 0, L_0x12ef800; 1 drivers +v0x10d4f30_0 .net *"_s5", 0 0, L_0x12ef960; 1 drivers +v0x10d5010_0 .net *"_s6", 0 0, L_0x12efb90; 1 drivers +v0x10d50f0_0 .net "in", 3 0, L_0x12f03d0; 1 drivers +v0x10d5260_0 .net "ors", 1 0, L_0x12efaa0; 1 drivers +v0x10d5340_0 .net "out", 0 0, L_0x12eff80; 1 drivers +L_0x12ef800 .part L_0x12f03d0, 0, 1; +L_0x12ef960 .part L_0x12f03d0, 1, 1; +L_0x12efaa0 .concat8 [ 1 1 0 0], L_0x12ef790, L_0x12efb90; +L_0x12efca0 .part L_0x12f03d0, 2, 1; +L_0x12efe00 .part L_0x12f03d0, 3, 1; +L_0x12efff0 .part L_0x12efaa0, 0, 1; +L_0x12f01a0 .part L_0x12efaa0, 1, 1; +S_0x10d5c50 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x10ced80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10db0a0_0 .net "ands", 7 0, L_0x12eaa30; 1 drivers +v0x10db1b0_0 .net "in", 7 0, L_0x12e89a0; alias, 1 drivers +v0x10db270_0 .net "out", 0 0, L_0x12eca30; alias, 1 drivers +v0x10db340_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10d5ea0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10d5c50; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10d85e0_0 .net "A", 7 0, L_0x12e89a0; alias, 1 drivers +v0x10d86e0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10d87a0_0 .net *"_s0", 0 0, L_0x12e9220; 1 drivers +v0x10d8860_0 .net *"_s12", 0 0, L_0x12e9be0; 1 drivers +v0x10d8940_0 .net *"_s16", 0 0, L_0x12e9f40; 1 drivers +v0x10d8a70_0 .net *"_s20", 0 0, L_0x12ea370; 1 drivers +v0x10d8b50_0 .net *"_s24", 0 0, L_0x12ea6a0; 1 drivers +v0x10d8c30_0 .net *"_s28", 0 0, L_0x12ea630; 1 drivers +v0x10d8d10_0 .net *"_s4", 0 0, L_0x12e95c0; 1 drivers +v0x10d8e80_0 .net *"_s8", 0 0, L_0x12e98d0; 1 drivers +v0x10d8f60_0 .net "out", 7 0, L_0x12eaa30; alias, 1 drivers +L_0x12e9330 .part L_0x12e89a0, 0, 1; +L_0x12e9520 .part v0x127a150_0, 0, 1; +L_0x12e9680 .part L_0x12e89a0, 1, 1; +L_0x12e97e0 .part v0x127a150_0, 1, 1; +L_0x12e9990 .part L_0x12e89a0, 2, 1; +L_0x12e9af0 .part v0x127a150_0, 2, 1; +L_0x12e9ca0 .part L_0x12e89a0, 3, 1; +L_0x12e9e00 .part v0x127a150_0, 3, 1; +L_0x12ea000 .part L_0x12e89a0, 4, 1; +L_0x12ea270 .part v0x127a150_0, 4, 1; +L_0x12ea3e0 .part L_0x12e89a0, 5, 1; +L_0x12ea540 .part v0x127a150_0, 5, 1; +L_0x12ea760 .part L_0x12e89a0, 6, 1; +L_0x12ea8c0 .part v0x127a150_0, 6, 1; +LS_0x12eaa30_0_0 .concat8 [ 1 1 1 1], L_0x12e9220, L_0x12e95c0, L_0x12e98d0, L_0x12e9be0; +LS_0x12eaa30_0_4 .concat8 [ 1 1 1 1], L_0x12e9f40, L_0x12ea370, L_0x12ea6a0, L_0x12ea630; +L_0x12eaa30 .concat8 [ 4 4 0 0], LS_0x12eaa30_0_0, LS_0x12eaa30_0_4; +L_0x12eadf0 .part L_0x12e89a0, 7, 1; +L_0x12eafe0 .part v0x127a150_0, 7, 1; +S_0x10d60e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d62f0 .param/l "i" 0 4 54, +C4<00>; +L_0x12e9220/d .functor AND 1, L_0x12e9330, L_0x12e9520, C4<1>, C4<1>; +L_0x12e9220 .delay 1 (30000,30000,30000) L_0x12e9220/d; +v0x10d63d0_0 .net *"_s0", 0 0, L_0x12e9330; 1 drivers +v0x10d64b0_0 .net *"_s1", 0 0, L_0x12e9520; 1 drivers +S_0x10d6590 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d67a0 .param/l "i" 0 4 54, +C4<01>; +L_0x12e95c0/d .functor AND 1, L_0x12e9680, L_0x12e97e0, C4<1>, C4<1>; +L_0x12e95c0 .delay 1 (30000,30000,30000) L_0x12e95c0/d; +v0x10d6860_0 .net *"_s0", 0 0, L_0x12e9680; 1 drivers +v0x10d6940_0 .net *"_s1", 0 0, L_0x12e97e0; 1 drivers +S_0x10d6a20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d6c60 .param/l "i" 0 4 54, +C4<010>; +L_0x12e98d0/d .functor AND 1, L_0x12e9990, L_0x12e9af0, C4<1>, C4<1>; +L_0x12e98d0 .delay 1 (30000,30000,30000) L_0x12e98d0/d; +v0x10d6d00_0 .net *"_s0", 0 0, L_0x12e9990; 1 drivers +v0x10d6de0_0 .net *"_s1", 0 0, L_0x12e9af0; 1 drivers +S_0x10d6ec0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d70d0 .param/l "i" 0 4 54, +C4<011>; +L_0x12e9be0/d .functor AND 1, L_0x12e9ca0, L_0x12e9e00, C4<1>, C4<1>; +L_0x12e9be0 .delay 1 (30000,30000,30000) L_0x12e9be0/d; +v0x10d7190_0 .net *"_s0", 0 0, L_0x12e9ca0; 1 drivers +v0x10d7270_0 .net *"_s1", 0 0, L_0x12e9e00; 1 drivers +S_0x10d7350 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d75b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12e9f40/d .functor AND 1, L_0x12ea000, L_0x12ea270, C4<1>, C4<1>; +L_0x12e9f40 .delay 1 (30000,30000,30000) L_0x12e9f40/d; +v0x10d7670_0 .net *"_s0", 0 0, L_0x12ea000; 1 drivers +v0x10d7750_0 .net *"_s1", 0 0, L_0x12ea270; 1 drivers +S_0x10d7830 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d7a40 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ea370/d .functor AND 1, L_0x12ea3e0, L_0x12ea540, C4<1>, C4<1>; +L_0x12ea370 .delay 1 (30000,30000,30000) L_0x12ea370/d; +v0x10d7b00_0 .net *"_s0", 0 0, L_0x12ea3e0; 1 drivers +v0x10d7be0_0 .net *"_s1", 0 0, L_0x12ea540; 1 drivers +S_0x10d7cc0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d7ed0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ea6a0/d .functor AND 1, L_0x12ea760, L_0x12ea8c0, C4<1>, C4<1>; +L_0x12ea6a0 .delay 1 (30000,30000,30000) L_0x12ea6a0/d; +v0x10d7f90_0 .net *"_s0", 0 0, L_0x12ea760; 1 drivers +v0x10d8070_0 .net *"_s1", 0 0, L_0x12ea8c0; 1 drivers +S_0x10d8150 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10d5ea0; + .timescale -9 -12; +P_0x10d8360 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ea630/d .functor AND 1, L_0x12eadf0, L_0x12eafe0, C4<1>, C4<1>; +L_0x12ea630 .delay 1 (30000,30000,30000) L_0x12ea630/d; +v0x10d8420_0 .net *"_s0", 0 0, L_0x12eadf0; 1 drivers +v0x10d8500_0 .net *"_s1", 0 0, L_0x12eafe0; 1 drivers +S_0x10d9060 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10d5c50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12eca30/d .functor OR 1, L_0x12ecaf0, L_0x12ecca0, C4<0>, C4<0>; +L_0x12eca30 .delay 1 (30000,30000,30000) L_0x12eca30/d; +v0x10dac30_0 .net *"_s10", 0 0, L_0x12ecaf0; 1 drivers +v0x10dad10_0 .net *"_s12", 0 0, L_0x12ecca0; 1 drivers +v0x10dadf0_0 .net "in", 7 0, L_0x12eaa30; alias, 1 drivers +v0x10daec0_0 .net "ors", 1 0, L_0x12ec850; 1 drivers +v0x10daf80_0 .net "out", 0 0, L_0x12eca30; alias, 1 drivers +L_0x12ebc20 .part L_0x12eaa30, 0, 4; +L_0x12ec850 .concat8 [ 1 1 0 0], L_0x12eb910, L_0x12ec540; +L_0x12ec990 .part L_0x12eaa30, 4, 4; +L_0x12ecaf0 .part L_0x12ec850, 0, 1; +L_0x12ecca0 .part L_0x12ec850, 1, 1; +S_0x10d9270 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10d9060; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12eb0d0/d .functor OR 1, L_0x12eb190, L_0x12eb2f0, C4<0>, C4<0>; +L_0x12eb0d0 .delay 1 (30000,30000,30000) L_0x12eb0d0/d; +L_0x12eb520/d .functor OR 1, L_0x12eb630, L_0x12eb790, C4<0>, C4<0>; +L_0x12eb520 .delay 1 (30000,30000,30000) L_0x12eb520/d; +L_0x12eb910/d .functor OR 1, L_0x12eb980, L_0x12ebb30, C4<0>, C4<0>; +L_0x12eb910 .delay 1 (30000,30000,30000) L_0x12eb910/d; +v0x10d94c0_0 .net *"_s0", 0 0, L_0x12eb0d0; 1 drivers +v0x10d95c0_0 .net *"_s10", 0 0, L_0x12eb630; 1 drivers +v0x10d96a0_0 .net *"_s12", 0 0, L_0x12eb790; 1 drivers +v0x10d9790_0 .net *"_s14", 0 0, L_0x12eb980; 1 drivers +v0x10d9870_0 .net *"_s16", 0 0, L_0x12ebb30; 1 drivers +v0x10d99a0_0 .net *"_s3", 0 0, L_0x12eb190; 1 drivers +v0x10d9a80_0 .net *"_s5", 0 0, L_0x12eb2f0; 1 drivers +v0x10d9b60_0 .net *"_s6", 0 0, L_0x12eb520; 1 drivers +v0x10d9c40_0 .net "in", 3 0, L_0x12ebc20; 1 drivers +v0x10d9db0_0 .net "ors", 1 0, L_0x12eb430; 1 drivers +v0x10d9e90_0 .net "out", 0 0, L_0x12eb910; 1 drivers +L_0x12eb190 .part L_0x12ebc20, 0, 1; +L_0x12eb2f0 .part L_0x12ebc20, 1, 1; +L_0x12eb430 .concat8 [ 1 1 0 0], L_0x12eb0d0, L_0x12eb520; +L_0x12eb630 .part L_0x12ebc20, 2, 1; +L_0x12eb790 .part L_0x12ebc20, 3, 1; +L_0x12eb980 .part L_0x12eb430, 0, 1; +L_0x12ebb30 .part L_0x12eb430, 1, 1; +S_0x10d9fb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10d9060; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12ebd50/d .functor OR 1, L_0x12ebdc0, L_0x12ebf20, C4<0>, C4<0>; +L_0x12ebd50 .delay 1 (30000,30000,30000) L_0x12ebd50/d; +L_0x12ec150/d .functor OR 1, L_0x12ec260, L_0x12ec3c0, C4<0>, C4<0>; +L_0x12ec150 .delay 1 (30000,30000,30000) L_0x12ec150/d; +L_0x12ec540/d .functor OR 1, L_0x12ec5b0, L_0x12ec760, C4<0>, C4<0>; +L_0x12ec540 .delay 1 (30000,30000,30000) L_0x12ec540/d; +v0x10da170_0 .net *"_s0", 0 0, L_0x12ebd50; 1 drivers +v0x10da270_0 .net *"_s10", 0 0, L_0x12ec260; 1 drivers +v0x10da350_0 .net *"_s12", 0 0, L_0x12ec3c0; 1 drivers +v0x10da410_0 .net *"_s14", 0 0, L_0x12ec5b0; 1 drivers +v0x10da4f0_0 .net *"_s16", 0 0, L_0x12ec760; 1 drivers +v0x10da620_0 .net *"_s3", 0 0, L_0x12ebdc0; 1 drivers +v0x10da700_0 .net *"_s5", 0 0, L_0x12ebf20; 1 drivers +v0x10da7e0_0 .net *"_s6", 0 0, L_0x12ec150; 1 drivers +v0x10da8c0_0 .net "in", 3 0, L_0x12ec990; 1 drivers +v0x10daa30_0 .net "ors", 1 0, L_0x12ec060; 1 drivers +v0x10dab10_0 .net "out", 0 0, L_0x12ec540; 1 drivers +L_0x12ebdc0 .part L_0x12ec990, 0, 1; +L_0x12ebf20 .part L_0x12ec990, 1, 1; +L_0x12ec060 .concat8 [ 1 1 0 0], L_0x12ebd50, L_0x12ec150; +L_0x12ec260 .part L_0x12ec990, 2, 1; +L_0x12ec3c0 .part L_0x12ec990, 3, 1; +L_0x12ec5b0 .part L_0x12ec060, 0, 1; +L_0x12ec760 .part L_0x12ec060, 1, 1; +S_0x10db420 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x10ced80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12e77e0/d .functor XNOR 1, L_0x12f08d0, L_0x12f0a30, C4<0>, C4<0>; +L_0x12e77e0 .delay 1 (20000,20000,20000) L_0x12e77e0/d; +L_0x12e7960/d .functor AND 1, L_0x12f08d0, L_0x12e6570, C4<1>, C4<1>; +L_0x12e7960 .delay 1 (30000,30000,30000) L_0x12e7960/d; +L_0x12e7ac0/d .functor AND 1, L_0x12e77e0, L_0x12e6360, C4<1>, C4<1>; +L_0x12e7ac0 .delay 1 (30000,30000,30000) L_0x12e7ac0/d; +L_0x12e7bd0/d .functor OR 1, L_0x12e7ac0, L_0x12e7960, C4<0>, C4<0>; +L_0x12e7bd0 .delay 1 (30000,30000,30000) L_0x12e7bd0/d; +v0x10db6d0_0 .net "a", 0 0, L_0x12f08d0; alias, 1 drivers +v0x10db7c0_0 .net "a_", 0 0, L_0x12e6460; alias, 1 drivers +v0x10db880_0 .net "b", 0 0, L_0x12f0a30; alias, 1 drivers +v0x10db970_0 .net "b_", 0 0, L_0x12e6570; alias, 1 drivers +v0x10dba10_0 .net "carryin", 0 0, L_0x12e6360; alias, 1 drivers +v0x10dbb50_0 .net "eq", 0 0, L_0x12e77e0; 1 drivers +v0x10dbc10_0 .net "lt", 0 0, L_0x12e7960; 1 drivers +v0x10dbcd0_0 .net "out", 0 0, L_0x12e7bd0; 1 drivers +v0x10dbd90_0 .net "w0", 0 0, L_0x12e7ac0; 1 drivers +S_0x10dbfe0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10ced80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12e73c0/d .functor OR 1, L_0x12e6f60, L_0x10dd240, C4<0>, C4<0>; +L_0x12e73c0 .delay 1 (30000,30000,30000) L_0x12e73c0/d; +v0x10dcdd0_0 .net "a", 0 0, L_0x12f08d0; alias, 1 drivers +v0x10dcf20_0 .net "b", 0 0, L_0x12e6570; alias, 1 drivers +v0x10dcfe0_0 .net "c1", 0 0, L_0x12e6f60; 1 drivers +v0x10dd080_0 .net "c2", 0 0, L_0x10dd240; 1 drivers +v0x10dd150_0 .net "carryin", 0 0, L_0x12e6360; alias, 1 drivers +v0x10dd2d0_0 .net "carryout", 0 0, L_0x12e73c0; 1 drivers +v0x10dd370_0 .net "s1", 0 0, L_0x12e6ea0; 1 drivers +v0x10dd410_0 .net "sum", 0 0, L_0x12e7070; 1 drivers +S_0x10dc230 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10dbfe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12e6ea0/d .functor XOR 1, L_0x12f08d0, L_0x12e6570, C4<0>, C4<0>; +L_0x12e6ea0 .delay 1 (30000,30000,30000) L_0x12e6ea0/d; +L_0x12e6f60/d .functor AND 1, L_0x12f08d0, L_0x12e6570, C4<1>, C4<1>; +L_0x12e6f60 .delay 1 (30000,30000,30000) L_0x12e6f60/d; +v0x10dc490_0 .net "a", 0 0, L_0x12f08d0; alias, 1 drivers +v0x10dc550_0 .net "b", 0 0, L_0x12e6570; alias, 1 drivers +v0x10dc610_0 .net "carryout", 0 0, L_0x12e6f60; alias, 1 drivers +v0x10dc6b0_0 .net "sum", 0 0, L_0x12e6ea0; alias, 1 drivers +S_0x10dc7e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10dbfe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12e7070/d .functor XOR 1, L_0x12e6ea0, L_0x12e6360, C4<0>, C4<0>; +L_0x12e7070 .delay 1 (30000,30000,30000) L_0x12e7070/d; +L_0x10dd240/d .functor AND 1, L_0x12e6ea0, L_0x12e6360, C4<1>, C4<1>; +L_0x10dd240 .delay 1 (30000,30000,30000) L_0x10dd240/d; +v0x10dca40_0 .net "a", 0 0, L_0x12e6ea0; alias, 1 drivers +v0x10dcb10_0 .net "b", 0 0, L_0x12e6360; alias, 1 drivers +v0x10dcbb0_0 .net "carryout", 0 0, L_0x10dd240; alias, 1 drivers +v0x10dcc80_0 .net "sum", 0 0, L_0x12e7070; alias, 1 drivers +S_0x10df4a0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x10ceab0; + .timescale -9 -12; +L_0x2ac432885a48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885a90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e6a20/d .functor OR 1, L_0x2ac432885a48, L_0x2ac432885a90, C4<0>, C4<0>; +L_0x12e6a20 .delay 1 (30000,30000,30000) L_0x12e6a20/d; +v0x10df690_0 .net/2u *"_s0", 0 0, L_0x2ac432885a48; 1 drivers +v0x10df770_0 .net/2u *"_s2", 0 0, L_0x2ac432885a90; 1 drivers +S_0x10df850 .scope generate, "alu_slices[11]" "alu_slices[11]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x10dfa60 .param/l "i" 0 3 39, +C4<01011>; +S_0x10dfb20 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x10df850; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12f0c30/d .functor NOT 1, L_0x12fb0f0, C4<0>, C4<0>, C4<0>; +L_0x12f0c30 .delay 1 (10000,10000,10000) L_0x12f0c30/d; +L_0x12f0d40/d .functor NOT 1, L_0x12f0ad0, C4<0>, C4<0>, C4<0>; +L_0x12f0d40 .delay 1 (10000,10000,10000) L_0x12f0d40/d; +L_0x12f1d40/d .functor XOR 1, L_0x12fb0f0, L_0x12f0ad0, C4<0>, C4<0>; +L_0x12f1d40 .delay 1 (30000,30000,30000) L_0x12f1d40/d; +L_0x2ac432885ad8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885b20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f1e00/d .functor OR 1, L_0x2ac432885ad8, L_0x2ac432885b20, C4<0>, C4<0>; +L_0x12f1e00 .delay 1 (30000,30000,30000) L_0x12f1e00/d; +L_0x2ac432885b68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885bb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f25a0/d .functor OR 1, L_0x2ac432885b68, L_0x2ac432885bb0, C4<0>, C4<0>; +L_0x12f25a0 .delay 1 (30000,30000,30000) L_0x12f25a0/d; +L_0x12f27a0/d .functor AND 1, L_0x12fb0f0, L_0x12f0ad0, C4<1>, C4<1>; +L_0x12f27a0 .delay 1 (30000,30000,30000) L_0x12f27a0/d; +L_0x2ac432885bf8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885c40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f2860/d .functor OR 1, L_0x2ac432885bf8, L_0x2ac432885c40, C4<0>, C4<0>; +L_0x12f2860 .delay 1 (30000,30000,30000) L_0x12f2860/d; +L_0x12f2a60/d .functor NAND 1, L_0x12fb0f0, L_0x12f0ad0, C4<1>, C4<1>; +L_0x12f2a60 .delay 1 (20000,20000,20000) L_0x12f2a60/d; +L_0x2ac432885c88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885cd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f2b70/d .functor OR 1, L_0x2ac432885c88, L_0x2ac432885cd0, C4<0>, C4<0>; +L_0x12f2b70 .delay 1 (30000,30000,30000) L_0x12f2b70/d; +L_0x12f2d20/d .functor NOR 1, L_0x12fb0f0, L_0x12f0ad0, C4<0>, C4<0>; +L_0x12f2d20 .delay 1 (20000,20000,20000) L_0x12f2d20/d; +L_0x2ac432885d18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885d60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f2ff0/d .functor OR 1, L_0x2ac432885d18, L_0x2ac432885d60, C4<0>, C4<0>; +L_0x12f2ff0 .delay 1 (30000,30000,30000) L_0x12f2ff0/d; +L_0x12f33f0/d .functor OR 1, L_0x12fb0f0, L_0x12f0ad0, C4<0>, C4<0>; +L_0x12f33f0 .delay 1 (30000,30000,30000) L_0x12f33f0/d; +L_0x2ac432885da8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885df0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f3890/d .functor OR 1, L_0x2ac432885da8, L_0x2ac432885df0, C4<0>, C4<0>; +L_0x12f3890 .delay 1 (30000,30000,30000) L_0x12f3890/d; +L_0x12faff0/d .functor NOT 1, L_0x12f7250, C4<0>, C4<0>, C4<0>; +L_0x12faff0 .delay 1 (10000,10000,10000) L_0x12faff0/d; +v0x10ee250_0 .net "A", 0 0, L_0x12fb0f0; 1 drivers +v0x10ee310_0 .net "A_", 0 0, L_0x12f0c30; 1 drivers +v0x10ee3d0_0 .net "B", 0 0, L_0x12f0ad0; 1 drivers +v0x10ee4a0_0 .net "B_", 0 0, L_0x12f0d40; 1 drivers +v0x10ee540_0 .net *"_s11", 0 0, L_0x12f1e00; 1 drivers +v0x10ee630_0 .net/2s *"_s13", 0 0, L_0x2ac432885ad8; 1 drivers +v0x10ee6f0_0 .net/2s *"_s15", 0 0, L_0x2ac432885b20; 1 drivers +v0x10ee7d0_0 .net *"_s19", 0 0, L_0x12f25a0; 1 drivers +v0x10ee8b0_0 .net/2s *"_s21", 0 0, L_0x2ac432885b68; 1 drivers +v0x10eea20_0 .net/2s *"_s23", 0 0, L_0x2ac432885bb0; 1 drivers +v0x10eeb00_0 .net *"_s25", 0 0, L_0x12f27a0; 1 drivers +v0x10eebe0_0 .net *"_s28", 0 0, L_0x12f2860; 1 drivers +v0x10eecc0_0 .net/2s *"_s30", 0 0, L_0x2ac432885bf8; 1 drivers +v0x10eeda0_0 .net/2s *"_s32", 0 0, L_0x2ac432885c40; 1 drivers +v0x10eee80_0 .net *"_s34", 0 0, L_0x12f2a60; 1 drivers +v0x10eef60_0 .net *"_s37", 0 0, L_0x12f2b70; 1 drivers +v0x10ef040_0 .net/2s *"_s39", 0 0, L_0x2ac432885c88; 1 drivers +v0x10ef1f0_0 .net/2s *"_s41", 0 0, L_0x2ac432885cd0; 1 drivers +v0x10ef290_0 .net *"_s43", 0 0, L_0x12f2d20; 1 drivers +v0x10ef370_0 .net *"_s46", 0 0, L_0x12f2ff0; 1 drivers +v0x10ef450_0 .net/2s *"_s48", 0 0, L_0x2ac432885d18; 1 drivers +v0x10ef530_0 .net/2s *"_s50", 0 0, L_0x2ac432885d60; 1 drivers +v0x10ef610_0 .net *"_s52", 0 0, L_0x12f33f0; 1 drivers +v0x10ef6f0_0 .net *"_s56", 0 0, L_0x12f3890; 1 drivers +v0x10ef7d0_0 .net/2s *"_s59", 0 0, L_0x2ac432885da8; 1 drivers +v0x10ef8b0_0 .net/2s *"_s61", 0 0, L_0x2ac432885df0; 1 drivers +v0x10ef990_0 .net *"_s8", 0 0, L_0x12f1d40; 1 drivers +v0x10efa70_0 .net "carryin", 0 0, L_0x12fb370; 1 drivers +v0x10efb10_0 .net "carryout", 0 0, L_0x12fac90; 1 drivers +v0x10efbb0_0 .net "carryouts", 7 0, L_0x12f3500; 1 drivers +v0x10efcc0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x10efd80_0 .net "result", 0 0, L_0x12f7250; 1 drivers +v0x10efe70_0 .net "results", 7 0, L_0x12f31c0; 1 drivers +v0x10ef150_0 .net "zero", 0 0, L_0x12faff0; 1 drivers +LS_0x12f31c0_0_0 .concat8 [ 1 1 1 1], L_0x12f1260, L_0x12f1890, L_0x12f1d40, L_0x12f25a0; +LS_0x12f31c0_0_4 .concat8 [ 1 1 1 1], L_0x12f27a0, L_0x12f2a60, L_0x12f2d20, L_0x12f33f0; +L_0x12f31c0 .concat8 [ 4 4 0 0], LS_0x12f31c0_0_0, LS_0x12f31c0_0_4; +LS_0x12f3500_0_0 .concat8 [ 1 1 1 1], L_0x12f1510, L_0x12f1be0, L_0x12f1e00, L_0x12f23f0; +LS_0x12f3500_0_4 .concat8 [ 1 1 1 1], L_0x12f2860, L_0x12f2b70, L_0x12f2ff0, L_0x12f3890; +L_0x12f3500 .concat8 [ 4 4 0 0], LS_0x12f3500_0_0, LS_0x12f3500_0_4; +S_0x10dfda0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12f1510/d .functor OR 1, L_0x12f0ff0, L_0x12f13b0, C4<0>, C4<0>; +L_0x12f1510 .delay 1 (30000,30000,30000) L_0x12f1510/d; +v0x10e0bd0_0 .net "a", 0 0, L_0x12fb0f0; alias, 1 drivers +v0x10e0c90_0 .net "b", 0 0, L_0x12f0ad0; alias, 1 drivers +v0x10e0d60_0 .net "c1", 0 0, L_0x12f0ff0; 1 drivers +v0x10e0e60_0 .net "c2", 0 0, L_0x12f13b0; 1 drivers +v0x10e0f30_0 .net "carryin", 0 0, L_0x12fb370; alias, 1 drivers +v0x10e1020_0 .net "carryout", 0 0, L_0x12f1510; 1 drivers +v0x10e10c0_0 .net "s1", 0 0, L_0x12f0f30; 1 drivers +v0x10e11b0_0 .net "sum", 0 0, L_0x12f1260; 1 drivers +S_0x10e0010 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10dfda0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12f0f30/d .functor XOR 1, L_0x12fb0f0, L_0x12f0ad0, C4<0>, C4<0>; +L_0x12f0f30 .delay 1 (30000,30000,30000) L_0x12f0f30/d; +L_0x12f0ff0/d .functor AND 1, L_0x12fb0f0, L_0x12f0ad0, C4<1>, C4<1>; +L_0x12f0ff0 .delay 1 (30000,30000,30000) L_0x12f0ff0/d; +v0x10e0270_0 .net "a", 0 0, L_0x12fb0f0; alias, 1 drivers +v0x10e0350_0 .net "b", 0 0, L_0x12f0ad0; alias, 1 drivers +v0x10e0410_0 .net "carryout", 0 0, L_0x12f0ff0; alias, 1 drivers +v0x10e04b0_0 .net "sum", 0 0, L_0x12f0f30; alias, 1 drivers +S_0x10e05f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10dfda0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12f1260/d .functor XOR 1, L_0x12f0f30, L_0x12fb370, C4<0>, C4<0>; +L_0x12f1260 .delay 1 (30000,30000,30000) L_0x12f1260/d; +L_0x12f13b0/d .functor AND 1, L_0x12f0f30, L_0x12fb370, C4<1>, C4<1>; +L_0x12f13b0 .delay 1 (30000,30000,30000) L_0x12f13b0/d; +v0x10e0850_0 .net "a", 0 0, L_0x12f0f30; alias, 1 drivers +v0x10e08f0_0 .net "b", 0 0, L_0x12fb370; alias, 1 drivers +v0x10e0990_0 .net "carryout", 0 0, L_0x12f13b0; alias, 1 drivers +v0x10e0a60_0 .net "sum", 0 0, L_0x12f1260; alias, 1 drivers +S_0x10e1280 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x10dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10e6670_0 .net "ands", 7 0, L_0x12f8c90; 1 drivers +v0x10e6780_0 .net "in", 7 0, L_0x12f3500; alias, 1 drivers +v0x10e6840_0 .net "out", 0 0, L_0x12fac90; alias, 1 drivers +v0x10e6910_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10e14a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10e1280; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10e3bd0_0 .net "A", 7 0, L_0x12f3500; alias, 1 drivers +v0x10e3cd0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10e3d90_0 .net *"_s0", 0 0, L_0x12f75b0; 1 drivers +v0x10e3e50_0 .net *"_s12", 0 0, L_0x12f7f20; 1 drivers +v0x10e3f30_0 .net *"_s16", 0 0, L_0x12f8280; 1 drivers +v0x10e4060_0 .net *"_s20", 0 0, L_0x12f8650; 1 drivers +v0x10e4140_0 .net *"_s24", 0 0, L_0x12f8980; 1 drivers +v0x10e4220_0 .net *"_s28", 0 0, L_0x12f8910; 1 drivers +v0x10e4300_0 .net *"_s4", 0 0, L_0x12f7900; 1 drivers +v0x10e4470_0 .net *"_s8", 0 0, L_0x12f7c10; 1 drivers +v0x10e4550_0 .net "out", 7 0, L_0x12f8c90; alias, 1 drivers +L_0x12f7670 .part L_0x12f3500, 0, 1; +L_0x12f7860 .part v0x127a150_0, 0, 1; +L_0x12f79c0 .part L_0x12f3500, 1, 1; +L_0x12f7b20 .part v0x127a150_0, 1, 1; +L_0x12f7cd0 .part L_0x12f3500, 2, 1; +L_0x12f7e30 .part v0x127a150_0, 2, 1; +L_0x12f7fe0 .part L_0x12f3500, 3, 1; +L_0x12f8140 .part v0x127a150_0, 3, 1; +L_0x12f8340 .part L_0x12f3500, 4, 1; +L_0x12f85b0 .part v0x127a150_0, 4, 1; +L_0x12f86c0 .part L_0x12f3500, 5, 1; +L_0x12f8820 .part v0x127a150_0, 5, 1; +L_0x12f8a40 .part L_0x12f3500, 6, 1; +L_0x12f8ba0 .part v0x127a150_0, 6, 1; +LS_0x12f8c90_0_0 .concat8 [ 1 1 1 1], L_0x12f75b0, L_0x12f7900, L_0x12f7c10, L_0x12f7f20; +LS_0x12f8c90_0_4 .concat8 [ 1 1 1 1], L_0x12f8280, L_0x12f8650, L_0x12f8980, L_0x12f8910; +L_0x12f8c90 .concat8 [ 4 4 0 0], LS_0x12f8c90_0_0, LS_0x12f8c90_0_4; +L_0x12f9050 .part L_0x12f3500, 7, 1; +L_0x12f9240 .part v0x127a150_0, 7, 1; +S_0x10e1700 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e1910 .param/l "i" 0 4 54, +C4<00>; +L_0x12f75b0/d .functor AND 1, L_0x12f7670, L_0x12f7860, C4<1>, C4<1>; +L_0x12f75b0 .delay 1 (30000,30000,30000) L_0x12f75b0/d; +v0x10e19f0_0 .net *"_s0", 0 0, L_0x12f7670; 1 drivers +v0x10e1ad0_0 .net *"_s1", 0 0, L_0x12f7860; 1 drivers +S_0x10e1bb0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e1dc0 .param/l "i" 0 4 54, +C4<01>; +L_0x12f7900/d .functor AND 1, L_0x12f79c0, L_0x12f7b20, C4<1>, C4<1>; +L_0x12f7900 .delay 1 (30000,30000,30000) L_0x12f7900/d; +v0x10e1e80_0 .net *"_s0", 0 0, L_0x12f79c0; 1 drivers +v0x10e1f60_0 .net *"_s1", 0 0, L_0x12f7b20; 1 drivers +S_0x10e2040 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e2250 .param/l "i" 0 4 54, +C4<010>; +L_0x12f7c10/d .functor AND 1, L_0x12f7cd0, L_0x12f7e30, C4<1>, C4<1>; +L_0x12f7c10 .delay 1 (30000,30000,30000) L_0x12f7c10/d; +v0x10e22f0_0 .net *"_s0", 0 0, L_0x12f7cd0; 1 drivers +v0x10e23d0_0 .net *"_s1", 0 0, L_0x12f7e30; 1 drivers +S_0x10e24b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e26c0 .param/l "i" 0 4 54, +C4<011>; +L_0x12f7f20/d .functor AND 1, L_0x12f7fe0, L_0x12f8140, C4<1>, C4<1>; +L_0x12f7f20 .delay 1 (30000,30000,30000) L_0x12f7f20/d; +v0x10e2780_0 .net *"_s0", 0 0, L_0x12f7fe0; 1 drivers +v0x10e2860_0 .net *"_s1", 0 0, L_0x12f8140; 1 drivers +S_0x10e2940 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e2ba0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12f8280/d .functor AND 1, L_0x12f8340, L_0x12f85b0, C4<1>, C4<1>; +L_0x12f8280 .delay 1 (30000,30000,30000) L_0x12f8280/d; +v0x10e2c60_0 .net *"_s0", 0 0, L_0x12f8340; 1 drivers +v0x10e2d40_0 .net *"_s1", 0 0, L_0x12f85b0; 1 drivers +S_0x10e2e20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e3030 .param/l "i" 0 4 54, +C4<0101>; +L_0x12f8650/d .functor AND 1, L_0x12f86c0, L_0x12f8820, C4<1>, C4<1>; +L_0x12f8650 .delay 1 (30000,30000,30000) L_0x12f8650/d; +v0x10e30f0_0 .net *"_s0", 0 0, L_0x12f86c0; 1 drivers +v0x10e31d0_0 .net *"_s1", 0 0, L_0x12f8820; 1 drivers +S_0x10e32b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e34c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12f8980/d .functor AND 1, L_0x12f8a40, L_0x12f8ba0, C4<1>, C4<1>; +L_0x12f8980 .delay 1 (30000,30000,30000) L_0x12f8980/d; +v0x10e3580_0 .net *"_s0", 0 0, L_0x12f8a40; 1 drivers +v0x10e3660_0 .net *"_s1", 0 0, L_0x12f8ba0; 1 drivers +S_0x10e3740 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10e14a0; + .timescale -9 -12; +P_0x10e3950 .param/l "i" 0 4 54, +C4<0111>; +L_0x12f8910/d .functor AND 1, L_0x12f9050, L_0x12f9240, C4<1>, C4<1>; +L_0x12f8910 .delay 1 (30000,30000,30000) L_0x12f8910/d; +v0x10e3a10_0 .net *"_s0", 0 0, L_0x12f9050; 1 drivers +v0x10e3af0_0 .net *"_s1", 0 0, L_0x12f9240; 1 drivers +S_0x10e46b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10e1280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12fac90/d .functor OR 1, L_0x12fad50, L_0x12faf00, C4<0>, C4<0>; +L_0x12fac90 .delay 1 (30000,30000,30000) L_0x12fac90/d; +v0x10e6200_0 .net *"_s10", 0 0, L_0x12fad50; 1 drivers +v0x10e62e0_0 .net *"_s12", 0 0, L_0x12faf00; 1 drivers +v0x10e63c0_0 .net "in", 7 0, L_0x12f8c90; alias, 1 drivers +v0x10e6490_0 .net "ors", 1 0, L_0x12faab0; 1 drivers +v0x10e6550_0 .net "out", 0 0, L_0x12fac90; alias, 1 drivers +L_0x12f9e80 .part L_0x12f8c90, 0, 4; +L_0x12faab0 .concat8 [ 1 1 0 0], L_0x12f9b70, L_0x12fa7a0; +L_0x12fabf0 .part L_0x12f8c90, 4, 4; +L_0x12fad50 .part L_0x12faab0, 0, 1; +L_0x12faf00 .part L_0x12faab0, 1, 1; +S_0x10e4870 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10e46b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12f9330/d .functor OR 1, L_0x12f93f0, L_0x12f9550, C4<0>, C4<0>; +L_0x12f9330 .delay 1 (30000,30000,30000) L_0x12f9330/d; +L_0x12f9780/d .functor OR 1, L_0x12f9890, L_0x12f99f0, C4<0>, C4<0>; +L_0x12f9780 .delay 1 (30000,30000,30000) L_0x12f9780/d; +L_0x12f9b70/d .functor OR 1, L_0x12f9be0, L_0x12f9d90, C4<0>, C4<0>; +L_0x12f9b70 .delay 1 (30000,30000,30000) L_0x12f9b70/d; +v0x10e4ac0_0 .net *"_s0", 0 0, L_0x12f9330; 1 drivers +v0x10e4bc0_0 .net *"_s10", 0 0, L_0x12f9890; 1 drivers +v0x10e4ca0_0 .net *"_s12", 0 0, L_0x12f99f0; 1 drivers +v0x10e4d60_0 .net *"_s14", 0 0, L_0x12f9be0; 1 drivers +v0x10e4e40_0 .net *"_s16", 0 0, L_0x12f9d90; 1 drivers +v0x10e4f70_0 .net *"_s3", 0 0, L_0x12f93f0; 1 drivers +v0x10e5050_0 .net *"_s5", 0 0, L_0x12f9550; 1 drivers +v0x10e5130_0 .net *"_s6", 0 0, L_0x12f9780; 1 drivers +v0x10e5210_0 .net "in", 3 0, L_0x12f9e80; 1 drivers +v0x10e5380_0 .net "ors", 1 0, L_0x12f9690; 1 drivers +v0x10e5460_0 .net "out", 0 0, L_0x12f9b70; 1 drivers +L_0x12f93f0 .part L_0x12f9e80, 0, 1; +L_0x12f9550 .part L_0x12f9e80, 1, 1; +L_0x12f9690 .concat8 [ 1 1 0 0], L_0x12f9330, L_0x12f9780; +L_0x12f9890 .part L_0x12f9e80, 2, 1; +L_0x12f99f0 .part L_0x12f9e80, 3, 1; +L_0x12f9be0 .part L_0x12f9690, 0, 1; +L_0x12f9d90 .part L_0x12f9690, 1, 1; +S_0x10e5580 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10e46b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12f9fb0/d .functor OR 1, L_0x12fa020, L_0x12fa180, C4<0>, C4<0>; +L_0x12f9fb0 .delay 1 (30000,30000,30000) L_0x12f9fb0/d; +L_0x12fa3b0/d .functor OR 1, L_0x12fa4c0, L_0x12fa620, C4<0>, C4<0>; +L_0x12fa3b0 .delay 1 (30000,30000,30000) L_0x12fa3b0/d; +L_0x12fa7a0/d .functor OR 1, L_0x12fa810, L_0x12fa9c0, C4<0>, C4<0>; +L_0x12fa7a0 .delay 1 (30000,30000,30000) L_0x12fa7a0/d; +v0x10e5740_0 .net *"_s0", 0 0, L_0x12f9fb0; 1 drivers +v0x10e5840_0 .net *"_s10", 0 0, L_0x12fa4c0; 1 drivers +v0x10e5920_0 .net *"_s12", 0 0, L_0x12fa620; 1 drivers +v0x10e59e0_0 .net *"_s14", 0 0, L_0x12fa810; 1 drivers +v0x10e5ac0_0 .net *"_s16", 0 0, L_0x12fa9c0; 1 drivers +v0x10e5bf0_0 .net *"_s3", 0 0, L_0x12fa020; 1 drivers +v0x10e5cd0_0 .net *"_s5", 0 0, L_0x12fa180; 1 drivers +v0x10e5db0_0 .net *"_s6", 0 0, L_0x12fa3b0; 1 drivers +v0x10e5e90_0 .net "in", 3 0, L_0x12fabf0; 1 drivers +v0x10e6000_0 .net "ors", 1 0, L_0x12fa2c0; 1 drivers +v0x10e60e0_0 .net "out", 0 0, L_0x12fa7a0; 1 drivers +L_0x12fa020 .part L_0x12fabf0, 0, 1; +L_0x12fa180 .part L_0x12fabf0, 1, 1; +L_0x12fa2c0 .concat8 [ 1 1 0 0], L_0x12f9fb0, L_0x12fa3b0; +L_0x12fa4c0 .part L_0x12fabf0, 2, 1; +L_0x12fa620 .part L_0x12fabf0, 3, 1; +L_0x12fa810 .part L_0x12fa2c0, 0, 1; +L_0x12fa9c0 .part L_0x12fa2c0, 1, 1; +S_0x10e69f0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x10dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10ebe20_0 .net "ands", 7 0, L_0x12f5250; 1 drivers +v0x10ebf30_0 .net "in", 7 0, L_0x12f31c0; alias, 1 drivers +v0x10ebff0_0 .net "out", 0 0, L_0x12f7250; alias, 1 drivers +v0x10ec0c0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10e6c40 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10e69f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10e9380_0 .net "A", 7 0, L_0x12f31c0; alias, 1 drivers +v0x10e9480_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10e9540_0 .net *"_s0", 0 0, L_0x12f3a40; 1 drivers +v0x10e9600_0 .net *"_s12", 0 0, L_0x12f4400; 1 drivers +v0x10e96e0_0 .net *"_s16", 0 0, L_0x12f4760; 1 drivers +v0x10e9810_0 .net *"_s20", 0 0, L_0x12f4b90; 1 drivers +v0x10e98f0_0 .net *"_s24", 0 0, L_0x12f4ec0; 1 drivers +v0x10e99d0_0 .net *"_s28", 0 0, L_0x12f4e50; 1 drivers +v0x10e9ab0_0 .net *"_s4", 0 0, L_0x12f3de0; 1 drivers +v0x10e9c20_0 .net *"_s8", 0 0, L_0x12f40f0; 1 drivers +v0x10e9d00_0 .net "out", 7 0, L_0x12f5250; alias, 1 drivers +L_0x12f3b50 .part L_0x12f31c0, 0, 1; +L_0x12f3d40 .part v0x127a150_0, 0, 1; +L_0x12f3ea0 .part L_0x12f31c0, 1, 1; +L_0x12f4000 .part v0x127a150_0, 1, 1; +L_0x12f41b0 .part L_0x12f31c0, 2, 1; +L_0x12f4310 .part v0x127a150_0, 2, 1; +L_0x12f44c0 .part L_0x12f31c0, 3, 1; +L_0x12f4620 .part v0x127a150_0, 3, 1; +L_0x12f4820 .part L_0x12f31c0, 4, 1; +L_0x12f4a90 .part v0x127a150_0, 4, 1; +L_0x12f4c00 .part L_0x12f31c0, 5, 1; +L_0x12f4d60 .part v0x127a150_0, 5, 1; +L_0x12f4f80 .part L_0x12f31c0, 6, 1; +L_0x12f50e0 .part v0x127a150_0, 6, 1; +LS_0x12f5250_0_0 .concat8 [ 1 1 1 1], L_0x12f3a40, L_0x12f3de0, L_0x12f40f0, L_0x12f4400; +LS_0x12f5250_0_4 .concat8 [ 1 1 1 1], L_0x12f4760, L_0x12f4b90, L_0x12f4ec0, L_0x12f4e50; +L_0x12f5250 .concat8 [ 4 4 0 0], LS_0x12f5250_0_0, LS_0x12f5250_0_4; +L_0x12f5610 .part L_0x12f31c0, 7, 1; +L_0x12f5800 .part v0x127a150_0, 7, 1; +S_0x10e6e80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e7090 .param/l "i" 0 4 54, +C4<00>; +L_0x12f3a40/d .functor AND 1, L_0x12f3b50, L_0x12f3d40, C4<1>, C4<1>; +L_0x12f3a40 .delay 1 (30000,30000,30000) L_0x12f3a40/d; +v0x10e7170_0 .net *"_s0", 0 0, L_0x12f3b50; 1 drivers +v0x10e7250_0 .net *"_s1", 0 0, L_0x12f3d40; 1 drivers +S_0x10e7330 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e7540 .param/l "i" 0 4 54, +C4<01>; +L_0x12f3de0/d .functor AND 1, L_0x12f3ea0, L_0x12f4000, C4<1>, C4<1>; +L_0x12f3de0 .delay 1 (30000,30000,30000) L_0x12f3de0/d; +v0x10e7600_0 .net *"_s0", 0 0, L_0x12f3ea0; 1 drivers +v0x10e76e0_0 .net *"_s1", 0 0, L_0x12f4000; 1 drivers +S_0x10e77c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e7a00 .param/l "i" 0 4 54, +C4<010>; +L_0x12f40f0/d .functor AND 1, L_0x12f41b0, L_0x12f4310, C4<1>, C4<1>; +L_0x12f40f0 .delay 1 (30000,30000,30000) L_0x12f40f0/d; +v0x10e7aa0_0 .net *"_s0", 0 0, L_0x12f41b0; 1 drivers +v0x10e7b80_0 .net *"_s1", 0 0, L_0x12f4310; 1 drivers +S_0x10e7c60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e7e70 .param/l "i" 0 4 54, +C4<011>; +L_0x12f4400/d .functor AND 1, L_0x12f44c0, L_0x12f4620, C4<1>, C4<1>; +L_0x12f4400 .delay 1 (30000,30000,30000) L_0x12f4400/d; +v0x10e7f30_0 .net *"_s0", 0 0, L_0x12f44c0; 1 drivers +v0x10e8010_0 .net *"_s1", 0 0, L_0x12f4620; 1 drivers +S_0x10e80f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e8350 .param/l "i" 0 4 54, +C4<0100>; +L_0x12f4760/d .functor AND 1, L_0x12f4820, L_0x12f4a90, C4<1>, C4<1>; +L_0x12f4760 .delay 1 (30000,30000,30000) L_0x12f4760/d; +v0x10e8410_0 .net *"_s0", 0 0, L_0x12f4820; 1 drivers +v0x10e84f0_0 .net *"_s1", 0 0, L_0x12f4a90; 1 drivers +S_0x10e85d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e87e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12f4b90/d .functor AND 1, L_0x12f4c00, L_0x12f4d60, C4<1>, C4<1>; +L_0x12f4b90 .delay 1 (30000,30000,30000) L_0x12f4b90/d; +v0x10e88a0_0 .net *"_s0", 0 0, L_0x12f4c00; 1 drivers +v0x10e8980_0 .net *"_s1", 0 0, L_0x12f4d60; 1 drivers +S_0x10e8a60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e8c70 .param/l "i" 0 4 54, +C4<0110>; +L_0x12f4ec0/d .functor AND 1, L_0x12f4f80, L_0x12f50e0, C4<1>, C4<1>; +L_0x12f4ec0 .delay 1 (30000,30000,30000) L_0x12f4ec0/d; +v0x10e8d30_0 .net *"_s0", 0 0, L_0x12f4f80; 1 drivers +v0x10e8e10_0 .net *"_s1", 0 0, L_0x12f50e0; 1 drivers +S_0x10e8ef0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10e6c40; + .timescale -9 -12; +P_0x10e9100 .param/l "i" 0 4 54, +C4<0111>; +L_0x12f4e50/d .functor AND 1, L_0x12f5610, L_0x12f5800, C4<1>, C4<1>; +L_0x12f4e50 .delay 1 (30000,30000,30000) L_0x12f4e50/d; +v0x10e91c0_0 .net *"_s0", 0 0, L_0x12f5610; 1 drivers +v0x10e92a0_0 .net *"_s1", 0 0, L_0x12f5800; 1 drivers +S_0x10e9e60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10e69f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12f7250/d .functor OR 1, L_0x12f7310, L_0x12f74c0, C4<0>, C4<0>; +L_0x12f7250 .delay 1 (30000,30000,30000) L_0x12f7250/d; +v0x10eb9b0_0 .net *"_s10", 0 0, L_0x12f7310; 1 drivers +v0x10eba90_0 .net *"_s12", 0 0, L_0x12f74c0; 1 drivers +v0x10ebb70_0 .net "in", 7 0, L_0x12f5250; alias, 1 drivers +v0x10ebc40_0 .net "ors", 1 0, L_0x12f7070; 1 drivers +v0x10ebd00_0 .net "out", 0 0, L_0x12f7250; alias, 1 drivers +L_0x12f6440 .part L_0x12f5250, 0, 4; +L_0x12f7070 .concat8 [ 1 1 0 0], L_0x12f6130, L_0x12f6d60; +L_0x12f71b0 .part L_0x12f5250, 4, 4; +L_0x12f7310 .part L_0x12f7070, 0, 1; +L_0x12f74c0 .part L_0x12f7070, 1, 1; +S_0x10ea020 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10e9e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12f58f0/d .functor OR 1, L_0x12f59b0, L_0x12f5b10, C4<0>, C4<0>; +L_0x12f58f0 .delay 1 (30000,30000,30000) L_0x12f58f0/d; +L_0x12f5d40/d .functor OR 1, L_0x12f5e50, L_0x12f5fb0, C4<0>, C4<0>; +L_0x12f5d40 .delay 1 (30000,30000,30000) L_0x12f5d40/d; +L_0x12f6130/d .functor OR 1, L_0x12f61a0, L_0x12f6350, C4<0>, C4<0>; +L_0x12f6130 .delay 1 (30000,30000,30000) L_0x12f6130/d; +v0x10ea270_0 .net *"_s0", 0 0, L_0x12f58f0; 1 drivers +v0x10ea370_0 .net *"_s10", 0 0, L_0x12f5e50; 1 drivers +v0x10ea450_0 .net *"_s12", 0 0, L_0x12f5fb0; 1 drivers +v0x10ea510_0 .net *"_s14", 0 0, L_0x12f61a0; 1 drivers +v0x10ea5f0_0 .net *"_s16", 0 0, L_0x12f6350; 1 drivers +v0x10ea720_0 .net *"_s3", 0 0, L_0x12f59b0; 1 drivers +v0x10ea800_0 .net *"_s5", 0 0, L_0x12f5b10; 1 drivers +v0x10ea8e0_0 .net *"_s6", 0 0, L_0x12f5d40; 1 drivers +v0x10ea9c0_0 .net "in", 3 0, L_0x12f6440; 1 drivers +v0x10eab30_0 .net "ors", 1 0, L_0x12f5c50; 1 drivers +v0x10eac10_0 .net "out", 0 0, L_0x12f6130; 1 drivers +L_0x12f59b0 .part L_0x12f6440, 0, 1; +L_0x12f5b10 .part L_0x12f6440, 1, 1; +L_0x12f5c50 .concat8 [ 1 1 0 0], L_0x12f58f0, L_0x12f5d40; +L_0x12f5e50 .part L_0x12f6440, 2, 1; +L_0x12f5fb0 .part L_0x12f6440, 3, 1; +L_0x12f61a0 .part L_0x12f5c50, 0, 1; +L_0x12f6350 .part L_0x12f5c50, 1, 1; +S_0x10ead30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10e9e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12f6570/d .functor OR 1, L_0x12f65e0, L_0x12f6740, C4<0>, C4<0>; +L_0x12f6570 .delay 1 (30000,30000,30000) L_0x12f6570/d; +L_0x12f6970/d .functor OR 1, L_0x12f6a80, L_0x12f6be0, C4<0>, C4<0>; +L_0x12f6970 .delay 1 (30000,30000,30000) L_0x12f6970/d; +L_0x12f6d60/d .functor OR 1, L_0x12f6dd0, L_0x12f6f80, C4<0>, C4<0>; +L_0x12f6d60 .delay 1 (30000,30000,30000) L_0x12f6d60/d; +v0x10eaef0_0 .net *"_s0", 0 0, L_0x12f6570; 1 drivers +v0x10eaff0_0 .net *"_s10", 0 0, L_0x12f6a80; 1 drivers +v0x10eb0d0_0 .net *"_s12", 0 0, L_0x12f6be0; 1 drivers +v0x10eb190_0 .net *"_s14", 0 0, L_0x12f6dd0; 1 drivers +v0x10eb270_0 .net *"_s16", 0 0, L_0x12f6f80; 1 drivers +v0x10eb3a0_0 .net *"_s3", 0 0, L_0x12f65e0; 1 drivers +v0x10eb480_0 .net *"_s5", 0 0, L_0x12f6740; 1 drivers +v0x10eb560_0 .net *"_s6", 0 0, L_0x12f6970; 1 drivers +v0x10eb640_0 .net "in", 3 0, L_0x12f71b0; 1 drivers +v0x10eb7b0_0 .net "ors", 1 0, L_0x12f6880; 1 drivers +v0x10eb890_0 .net "out", 0 0, L_0x12f6d60; 1 drivers +L_0x12f65e0 .part L_0x12f71b0, 0, 1; +L_0x12f6740 .part L_0x12f71b0, 1, 1; +L_0x12f6880 .concat8 [ 1 1 0 0], L_0x12f6570, L_0x12f6970; +L_0x12f6a80 .part L_0x12f71b0, 2, 1; +L_0x12f6be0 .part L_0x12f71b0, 3, 1; +L_0x12f6dd0 .part L_0x12f6880, 0, 1; +L_0x12f6f80 .part L_0x12f6880, 1, 1; +S_0x10ec1a0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x10dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12f2000/d .functor XNOR 1, L_0x12fb0f0, L_0x12f0ad0, C4<0>, C4<0>; +L_0x12f2000 .delay 1 (20000,20000,20000) L_0x12f2000/d; +L_0x12f2180/d .functor AND 1, L_0x12fb0f0, L_0x12f0d40, C4<1>, C4<1>; +L_0x12f2180 .delay 1 (30000,30000,30000) L_0x12f2180/d; +L_0x12f22e0/d .functor AND 1, L_0x12f2000, L_0x12fb370, C4<1>, C4<1>; +L_0x12f22e0 .delay 1 (30000,30000,30000) L_0x12f22e0/d; +L_0x12f23f0/d .functor OR 1, L_0x12f22e0, L_0x12f2180, C4<0>, C4<0>; +L_0x12f23f0 .delay 1 (30000,30000,30000) L_0x12f23f0/d; +v0x10ec450_0 .net "a", 0 0, L_0x12fb0f0; alias, 1 drivers +v0x10ec540_0 .net "a_", 0 0, L_0x12f0c30; alias, 1 drivers +v0x10ec600_0 .net "b", 0 0, L_0x12f0ad0; alias, 1 drivers +v0x10ec6f0_0 .net "b_", 0 0, L_0x12f0d40; alias, 1 drivers +v0x10ec790_0 .net "carryin", 0 0, L_0x12fb370; alias, 1 drivers +v0x10ec8d0_0 .net "eq", 0 0, L_0x12f2000; 1 drivers +v0x10ec990_0 .net "lt", 0 0, L_0x12f2180; 1 drivers +v0x10eca50_0 .net "out", 0 0, L_0x12f23f0; 1 drivers +v0x10ecb10_0 .net "w0", 0 0, L_0x12f22e0; 1 drivers +S_0x10ecd60 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12f1be0/d .functor OR 1, L_0x12f1730, L_0x10edfc0, C4<0>, C4<0>; +L_0x12f1be0 .delay 1 (30000,30000,30000) L_0x12f1be0/d; +v0x10edb50_0 .net "a", 0 0, L_0x12fb0f0; alias, 1 drivers +v0x10edca0_0 .net "b", 0 0, L_0x12f0d40; alias, 1 drivers +v0x10edd60_0 .net "c1", 0 0, L_0x12f1730; 1 drivers +v0x10ede00_0 .net "c2", 0 0, L_0x10edfc0; 1 drivers +v0x10eded0_0 .net "carryin", 0 0, L_0x12fb370; alias, 1 drivers +v0x10ee050_0 .net "carryout", 0 0, L_0x12f1be0; 1 drivers +v0x10ee0f0_0 .net "s1", 0 0, L_0x12f1670; 1 drivers +v0x10ee190_0 .net "sum", 0 0, L_0x12f1890; 1 drivers +S_0x10ecfb0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10ecd60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12f1670/d .functor XOR 1, L_0x12fb0f0, L_0x12f0d40, C4<0>, C4<0>; +L_0x12f1670 .delay 1 (30000,30000,30000) L_0x12f1670/d; +L_0x12f1730/d .functor AND 1, L_0x12fb0f0, L_0x12f0d40, C4<1>, C4<1>; +L_0x12f1730 .delay 1 (30000,30000,30000) L_0x12f1730/d; +v0x10ed210_0 .net "a", 0 0, L_0x12fb0f0; alias, 1 drivers +v0x10ed2d0_0 .net "b", 0 0, L_0x12f0d40; alias, 1 drivers +v0x10ed390_0 .net "carryout", 0 0, L_0x12f1730; alias, 1 drivers +v0x10ed430_0 .net "sum", 0 0, L_0x12f1670; alias, 1 drivers +S_0x10ed560 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10ecd60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12f1890/d .functor XOR 1, L_0x12f1670, L_0x12fb370, C4<0>, C4<0>; +L_0x12f1890 .delay 1 (30000,30000,30000) L_0x12f1890/d; +L_0x10edfc0/d .functor AND 1, L_0x12f1670, L_0x12fb370, C4<1>, C4<1>; +L_0x10edfc0 .delay 1 (30000,30000,30000) L_0x10edfc0/d; +v0x10ed7c0_0 .net "a", 0 0, L_0x12f1670; alias, 1 drivers +v0x10ed890_0 .net "b", 0 0, L_0x12fb370; alias, 1 drivers +v0x10ed930_0 .net "carryout", 0 0, L_0x10edfc0; alias, 1 drivers +v0x10eda00_0 .net "sum", 0 0, L_0x12f1890; alias, 1 drivers +S_0x10f0220 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x10df850; + .timescale -9 -12; +L_0x2ac432885e38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885e80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f11f0/d .functor OR 1, L_0x2ac432885e38, L_0x2ac432885e80, C4<0>, C4<0>; +L_0x12f11f0 .delay 1 (30000,30000,30000) L_0x12f11f0/d; +v0x10f0410_0 .net/2u *"_s0", 0 0, L_0x2ac432885e38; 1 drivers +v0x10f04f0_0 .net/2u *"_s2", 0 0, L_0x2ac432885e80; 1 drivers +S_0x10f05d0 .scope generate, "alu_slices[12]" "alu_slices[12]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x10f07e0 .param/l "i" 0 3 39, +C4<01100>; +S_0x10f08a0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x10f05d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12fb2f0/d .functor NOT 1, L_0x1305960, C4<0>, C4<0>, C4<0>; +L_0x12fb2f0 .delay 1 (10000,10000,10000) L_0x12fb2f0/d; +L_0x12fb5e0/d .functor NOT 1, L_0x1305ac0, C4<0>, C4<0>, C4<0>; +L_0x12fb5e0 .delay 1 (10000,10000,10000) L_0x12fb5e0/d; +L_0x12fc630/d .functor XOR 1, L_0x1305960, L_0x1305ac0, C4<0>, C4<0>; +L_0x12fc630 .delay 1 (30000,30000,30000) L_0x12fc630/d; +L_0x2ac432885ec8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885f10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fc6f0/d .functor OR 1, L_0x2ac432885ec8, L_0x2ac432885f10, C4<0>, C4<0>; +L_0x12fc6f0 .delay 1 (30000,30000,30000) L_0x12fc6f0/d; +L_0x2ac432885f58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432885fa0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fce90/d .functor OR 1, L_0x2ac432885f58, L_0x2ac432885fa0, C4<0>, C4<0>; +L_0x12fce90 .delay 1 (30000,30000,30000) L_0x12fce90/d; +L_0x12fd090/d .functor AND 1, L_0x1305960, L_0x1305ac0, C4<1>, C4<1>; +L_0x12fd090 .delay 1 (30000,30000,30000) L_0x12fd090/d; +L_0x2ac432885fe8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886030 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fd150/d .functor OR 1, L_0x2ac432885fe8, L_0x2ac432886030, C4<0>, C4<0>; +L_0x12fd150 .delay 1 (30000,30000,30000) L_0x12fd150/d; +L_0x12fd350/d .functor NAND 1, L_0x1305960, L_0x1305ac0, C4<1>, C4<1>; +L_0x12fd350 .delay 1 (20000,20000,20000) L_0x12fd350/d; +L_0x2ac432886078 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328860c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fd460/d .functor OR 1, L_0x2ac432886078, L_0x2ac4328860c0, C4<0>, C4<0>; +L_0x12fd460 .delay 1 (30000,30000,30000) L_0x12fd460/d; +L_0x12fd610/d .functor NOR 1, L_0x1305960, L_0x1305ac0, C4<0>, C4<0>; +L_0x12fd610 .delay 1 (20000,20000,20000) L_0x12fd610/d; +L_0x2ac432886108 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886150 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fba90/d .functor OR 1, L_0x2ac432886108, L_0x2ac432886150, C4<0>, C4<0>; +L_0x12fba90 .delay 1 (30000,30000,30000) L_0x12fba90/d; +L_0x12fdc70/d .functor OR 1, L_0x1305960, L_0x1305ac0, C4<0>, C4<0>; +L_0x12fdc70 .delay 1 (30000,30000,30000) L_0x12fdc70/d; +L_0x2ac432886198 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328861e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fe160/d .functor OR 1, L_0x2ac432886198, L_0x2ac4328861e0, C4<0>, C4<0>; +L_0x12fe160 .delay 1 (30000,30000,30000) L_0x12fe160/d; +L_0x1305860/d .functor NOT 1, L_0x1301ac0, C4<0>, C4<0>, C4<0>; +L_0x1305860 .delay 1 (10000,10000,10000) L_0x1305860/d; +v0x10fefe0_0 .net "A", 0 0, L_0x1305960; 1 drivers +v0x10ff0a0_0 .net "A_", 0 0, L_0x12fb2f0; 1 drivers +v0x10ff160_0 .net "B", 0 0, L_0x1305ac0; 1 drivers +v0x10ff230_0 .net "B_", 0 0, L_0x12fb5e0; 1 drivers +v0x10ff2d0_0 .net *"_s11", 0 0, L_0x12fc6f0; 1 drivers +v0x10ff3c0_0 .net/2s *"_s13", 0 0, L_0x2ac432885ec8; 1 drivers +v0x10ff480_0 .net/2s *"_s15", 0 0, L_0x2ac432885f10; 1 drivers +v0x10ff560_0 .net *"_s19", 0 0, L_0x12fce90; 1 drivers +v0x10ff640_0 .net/2s *"_s21", 0 0, L_0x2ac432885f58; 1 drivers +v0x10ff7b0_0 .net/2s *"_s23", 0 0, L_0x2ac432885fa0; 1 drivers +v0x10ff890_0 .net *"_s25", 0 0, L_0x12fd090; 1 drivers +v0x10ff970_0 .net *"_s28", 0 0, L_0x12fd150; 1 drivers +v0x10ffa50_0 .net/2s *"_s30", 0 0, L_0x2ac432885fe8; 1 drivers +v0x10ffb30_0 .net/2s *"_s32", 0 0, L_0x2ac432886030; 1 drivers +v0x10ffc10_0 .net *"_s34", 0 0, L_0x12fd350; 1 drivers +v0x10ffcf0_0 .net *"_s37", 0 0, L_0x12fd460; 1 drivers +v0x10ffdd0_0 .net/2s *"_s39", 0 0, L_0x2ac432886078; 1 drivers +v0x10fff80_0 .net/2s *"_s41", 0 0, L_0x2ac4328860c0; 1 drivers +v0x1100020_0 .net *"_s43", 0 0, L_0x12fd610; 1 drivers +v0x1100100_0 .net *"_s46", 0 0, L_0x12fba90; 1 drivers +v0x11001e0_0 .net/2s *"_s48", 0 0, L_0x2ac432886108; 1 drivers +v0x11002c0_0 .net/2s *"_s50", 0 0, L_0x2ac432886150; 1 drivers +v0x11003a0_0 .net *"_s52", 0 0, L_0x12fdc70; 1 drivers +v0x1100480_0 .net *"_s56", 0 0, L_0x12fe160; 1 drivers +v0x1100560_0 .net/2s *"_s59", 0 0, L_0x2ac432886198; 1 drivers +v0x1100640_0 .net/2s *"_s61", 0 0, L_0x2ac4328861e0; 1 drivers +v0x1100720_0 .net *"_s8", 0 0, L_0x12fc630; 1 drivers +v0x1100800_0 .net "carryin", 0 0, L_0x12fb410; 1 drivers +v0x11008a0_0 .net "carryout", 0 0, L_0x1305500; 1 drivers +v0x1100940_0 .net "carryouts", 7 0, L_0x12fddf0; 1 drivers +v0x1100a50_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1094f40_0 .net "result", 0 0, L_0x1301ac0; 1 drivers +v0x1095030_0 .net "results", 7 0, L_0x12fda40; 1 drivers +v0x10ffe70_0 .net "zero", 0 0, L_0x1305860; 1 drivers +LS_0x12fda40_0_0 .concat8 [ 1 1 1 1], L_0x12fbb00, L_0x12fc130, L_0x12fc630, L_0x12fce90; +LS_0x12fda40_0_4 .concat8 [ 1 1 1 1], L_0x12fd090, L_0x12fd350, L_0x12fd610, L_0x12fdc70; +L_0x12fda40 .concat8 [ 4 4 0 0], LS_0x12fda40_0_0, LS_0x12fda40_0_4; +LS_0x12fddf0_0_0 .concat8 [ 1 1 1 1], L_0x12fbdb0, L_0x12fc4d0, L_0x12fc6f0, L_0x12fcce0; +LS_0x12fddf0_0_4 .concat8 [ 1 1 1 1], L_0x12fd150, L_0x12fd460, L_0x12fba90, L_0x12fe160; +L_0x12fddf0 .concat8 [ 4 4 0 0], LS_0x12fddf0_0_0, LS_0x12fddf0_0_4; +S_0x10f0b20 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12fbdb0/d .functor OR 1, L_0x12fb890, L_0x12fbc50, C4<0>, C4<0>; +L_0x12fbdb0 .delay 1 (30000,30000,30000) L_0x12fbdb0/d; +v0x10f1950_0 .net "a", 0 0, L_0x1305960; alias, 1 drivers +v0x10f1a10_0 .net "b", 0 0, L_0x1305ac0; alias, 1 drivers +v0x10f1ae0_0 .net "c1", 0 0, L_0x12fb890; 1 drivers +v0x10f1be0_0 .net "c2", 0 0, L_0x12fbc50; 1 drivers +v0x10f1cb0_0 .net "carryin", 0 0, L_0x12fb410; alias, 1 drivers +v0x10f1da0_0 .net "carryout", 0 0, L_0x12fbdb0; 1 drivers +v0x10f1e40_0 .net "s1", 0 0, L_0x12fb7d0; 1 drivers +v0x10f1f30_0 .net "sum", 0 0, L_0x12fbb00; 1 drivers +S_0x10f0d90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10f0b20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12fb7d0/d .functor XOR 1, L_0x1305960, L_0x1305ac0, C4<0>, C4<0>; +L_0x12fb7d0 .delay 1 (30000,30000,30000) L_0x12fb7d0/d; +L_0x12fb890/d .functor AND 1, L_0x1305960, L_0x1305ac0, C4<1>, C4<1>; +L_0x12fb890 .delay 1 (30000,30000,30000) L_0x12fb890/d; +v0x10f0ff0_0 .net "a", 0 0, L_0x1305960; alias, 1 drivers +v0x10f10d0_0 .net "b", 0 0, L_0x1305ac0; alias, 1 drivers +v0x10f1190_0 .net "carryout", 0 0, L_0x12fb890; alias, 1 drivers +v0x10f1230_0 .net "sum", 0 0, L_0x12fb7d0; alias, 1 drivers +S_0x10f1370 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10f0b20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12fbb00/d .functor XOR 1, L_0x12fb7d0, L_0x12fb410, C4<0>, C4<0>; +L_0x12fbb00 .delay 1 (30000,30000,30000) L_0x12fbb00/d; +L_0x12fbc50/d .functor AND 1, L_0x12fb7d0, L_0x12fb410, C4<1>, C4<1>; +L_0x12fbc50 .delay 1 (30000,30000,30000) L_0x12fbc50/d; +v0x10f15d0_0 .net "a", 0 0, L_0x12fb7d0; alias, 1 drivers +v0x10f1670_0 .net "b", 0 0, L_0x12fb410; alias, 1 drivers +v0x10f1710_0 .net "carryout", 0 0, L_0x12fbc50; alias, 1 drivers +v0x10f17e0_0 .net "sum", 0 0, L_0x12fbb00; alias, 1 drivers +S_0x10f2000 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x10f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10f73f0_0 .net "ands", 7 0, L_0x1303500; 1 drivers +v0x10f7500_0 .net "in", 7 0, L_0x12fddf0; alias, 1 drivers +v0x10f75c0_0 .net "out", 0 0, L_0x1305500; alias, 1 drivers +v0x10f7690_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10f2220 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10f2000; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10f4950_0 .net "A", 7 0, L_0x12fddf0; alias, 1 drivers +v0x10f4a50_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10f4b10_0 .net *"_s0", 0 0, L_0x1301e20; 1 drivers +v0x10f4bd0_0 .net *"_s12", 0 0, L_0x1302790; 1 drivers +v0x10f4cb0_0 .net *"_s16", 0 0, L_0x1302af0; 1 drivers +v0x10f4de0_0 .net *"_s20", 0 0, L_0x1302ec0; 1 drivers +v0x10f4ec0_0 .net *"_s24", 0 0, L_0x13031f0; 1 drivers +v0x10f4fa0_0 .net *"_s28", 0 0, L_0x1303180; 1 drivers +v0x10f5080_0 .net *"_s4", 0 0, L_0x1302170; 1 drivers +v0x10f51f0_0 .net *"_s8", 0 0, L_0x1302480; 1 drivers +v0x10f52d0_0 .net "out", 7 0, L_0x1303500; alias, 1 drivers +L_0x1301ee0 .part L_0x12fddf0, 0, 1; +L_0x13020d0 .part v0x127a150_0, 0, 1; +L_0x1302230 .part L_0x12fddf0, 1, 1; +L_0x1302390 .part v0x127a150_0, 1, 1; +L_0x1302540 .part L_0x12fddf0, 2, 1; +L_0x13026a0 .part v0x127a150_0, 2, 1; +L_0x1302850 .part L_0x12fddf0, 3, 1; +L_0x13029b0 .part v0x127a150_0, 3, 1; +L_0x1302bb0 .part L_0x12fddf0, 4, 1; +L_0x1302e20 .part v0x127a150_0, 4, 1; +L_0x1302f30 .part L_0x12fddf0, 5, 1; +L_0x1303090 .part v0x127a150_0, 5, 1; +L_0x13032b0 .part L_0x12fddf0, 6, 1; +L_0x1303410 .part v0x127a150_0, 6, 1; +LS_0x1303500_0_0 .concat8 [ 1 1 1 1], L_0x1301e20, L_0x1302170, L_0x1302480, L_0x1302790; +LS_0x1303500_0_4 .concat8 [ 1 1 1 1], L_0x1302af0, L_0x1302ec0, L_0x13031f0, L_0x1303180; +L_0x1303500 .concat8 [ 4 4 0 0], LS_0x1303500_0_0, LS_0x1303500_0_4; +L_0x13038c0 .part L_0x12fddf0, 7, 1; +L_0x1303ab0 .part v0x127a150_0, 7, 1; +S_0x10f2480 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f2690 .param/l "i" 0 4 54, +C4<00>; +L_0x1301e20/d .functor AND 1, L_0x1301ee0, L_0x13020d0, C4<1>, C4<1>; +L_0x1301e20 .delay 1 (30000,30000,30000) L_0x1301e20/d; +v0x10f2770_0 .net *"_s0", 0 0, L_0x1301ee0; 1 drivers +v0x10f2850_0 .net *"_s1", 0 0, L_0x13020d0; 1 drivers +S_0x10f2930 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f2b40 .param/l "i" 0 4 54, +C4<01>; +L_0x1302170/d .functor AND 1, L_0x1302230, L_0x1302390, C4<1>, C4<1>; +L_0x1302170 .delay 1 (30000,30000,30000) L_0x1302170/d; +v0x10f2c00_0 .net *"_s0", 0 0, L_0x1302230; 1 drivers +v0x10f2ce0_0 .net *"_s1", 0 0, L_0x1302390; 1 drivers +S_0x10f2dc0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f2fd0 .param/l "i" 0 4 54, +C4<010>; +L_0x1302480/d .functor AND 1, L_0x1302540, L_0x13026a0, C4<1>, C4<1>; +L_0x1302480 .delay 1 (30000,30000,30000) L_0x1302480/d; +v0x10f3070_0 .net *"_s0", 0 0, L_0x1302540; 1 drivers +v0x10f3150_0 .net *"_s1", 0 0, L_0x13026a0; 1 drivers +S_0x10f3230 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f3440 .param/l "i" 0 4 54, +C4<011>; +L_0x1302790/d .functor AND 1, L_0x1302850, L_0x13029b0, C4<1>, C4<1>; +L_0x1302790 .delay 1 (30000,30000,30000) L_0x1302790/d; +v0x10f3500_0 .net *"_s0", 0 0, L_0x1302850; 1 drivers +v0x10f35e0_0 .net *"_s1", 0 0, L_0x13029b0; 1 drivers +S_0x10f36c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f3920 .param/l "i" 0 4 54, +C4<0100>; +L_0x1302af0/d .functor AND 1, L_0x1302bb0, L_0x1302e20, C4<1>, C4<1>; +L_0x1302af0 .delay 1 (30000,30000,30000) L_0x1302af0/d; +v0x10f39e0_0 .net *"_s0", 0 0, L_0x1302bb0; 1 drivers +v0x10f3ac0_0 .net *"_s1", 0 0, L_0x1302e20; 1 drivers +S_0x10f3ba0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f3db0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1302ec0/d .functor AND 1, L_0x1302f30, L_0x1303090, C4<1>, C4<1>; +L_0x1302ec0 .delay 1 (30000,30000,30000) L_0x1302ec0/d; +v0x10f3e70_0 .net *"_s0", 0 0, L_0x1302f30; 1 drivers +v0x10f3f50_0 .net *"_s1", 0 0, L_0x1303090; 1 drivers +S_0x10f4030 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f4240 .param/l "i" 0 4 54, +C4<0110>; +L_0x13031f0/d .functor AND 1, L_0x13032b0, L_0x1303410, C4<1>, C4<1>; +L_0x13031f0 .delay 1 (30000,30000,30000) L_0x13031f0/d; +v0x10f4300_0 .net *"_s0", 0 0, L_0x13032b0; 1 drivers +v0x10f43e0_0 .net *"_s1", 0 0, L_0x1303410; 1 drivers +S_0x10f44c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10f2220; + .timescale -9 -12; +P_0x10f46d0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1303180/d .functor AND 1, L_0x13038c0, L_0x1303ab0, C4<1>, C4<1>; +L_0x1303180 .delay 1 (30000,30000,30000) L_0x1303180/d; +v0x10f4790_0 .net *"_s0", 0 0, L_0x13038c0; 1 drivers +v0x10f4870_0 .net *"_s1", 0 0, L_0x1303ab0; 1 drivers +S_0x10f5430 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10f2000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1305500/d .functor OR 1, L_0x13055c0, L_0x1305770, C4<0>, C4<0>; +L_0x1305500 .delay 1 (30000,30000,30000) L_0x1305500/d; +v0x10f6f80_0 .net *"_s10", 0 0, L_0x13055c0; 1 drivers +v0x10f7060_0 .net *"_s12", 0 0, L_0x1305770; 1 drivers +v0x10f7140_0 .net "in", 7 0, L_0x1303500; alias, 1 drivers +v0x10f7210_0 .net "ors", 1 0, L_0x1305320; 1 drivers +v0x10f72d0_0 .net "out", 0 0, L_0x1305500; alias, 1 drivers +L_0x13046f0 .part L_0x1303500, 0, 4; +L_0x1305320 .concat8 [ 1 1 0 0], L_0x13043e0, L_0x1305010; +L_0x1305460 .part L_0x1303500, 4, 4; +L_0x13055c0 .part L_0x1305320, 0, 1; +L_0x1305770 .part L_0x1305320, 1, 1; +S_0x10f55f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10f5430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1303ba0/d .functor OR 1, L_0x1303c60, L_0x1303dc0, C4<0>, C4<0>; +L_0x1303ba0 .delay 1 (30000,30000,30000) L_0x1303ba0/d; +L_0x1303ff0/d .functor OR 1, L_0x1304100, L_0x1304260, C4<0>, C4<0>; +L_0x1303ff0 .delay 1 (30000,30000,30000) L_0x1303ff0/d; +L_0x13043e0/d .functor OR 1, L_0x1304450, L_0x1304600, C4<0>, C4<0>; +L_0x13043e0 .delay 1 (30000,30000,30000) L_0x13043e0/d; +v0x10f5840_0 .net *"_s0", 0 0, L_0x1303ba0; 1 drivers +v0x10f5940_0 .net *"_s10", 0 0, L_0x1304100; 1 drivers +v0x10f5a20_0 .net *"_s12", 0 0, L_0x1304260; 1 drivers +v0x10f5ae0_0 .net *"_s14", 0 0, L_0x1304450; 1 drivers +v0x10f5bc0_0 .net *"_s16", 0 0, L_0x1304600; 1 drivers +v0x10f5cf0_0 .net *"_s3", 0 0, L_0x1303c60; 1 drivers +v0x10f5dd0_0 .net *"_s5", 0 0, L_0x1303dc0; 1 drivers +v0x10f5eb0_0 .net *"_s6", 0 0, L_0x1303ff0; 1 drivers +v0x10f5f90_0 .net "in", 3 0, L_0x13046f0; 1 drivers +v0x10f6100_0 .net "ors", 1 0, L_0x1303f00; 1 drivers +v0x10f61e0_0 .net "out", 0 0, L_0x13043e0; 1 drivers +L_0x1303c60 .part L_0x13046f0, 0, 1; +L_0x1303dc0 .part L_0x13046f0, 1, 1; +L_0x1303f00 .concat8 [ 1 1 0 0], L_0x1303ba0, L_0x1303ff0; +L_0x1304100 .part L_0x13046f0, 2, 1; +L_0x1304260 .part L_0x13046f0, 3, 1; +L_0x1304450 .part L_0x1303f00, 0, 1; +L_0x1304600 .part L_0x1303f00, 1, 1; +S_0x10f6300 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10f5430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1304820/d .functor OR 1, L_0x1304890, L_0x13049f0, C4<0>, C4<0>; +L_0x1304820 .delay 1 (30000,30000,30000) L_0x1304820/d; +L_0x1304c20/d .functor OR 1, L_0x1304d30, L_0x1304e90, C4<0>, C4<0>; +L_0x1304c20 .delay 1 (30000,30000,30000) L_0x1304c20/d; +L_0x1305010/d .functor OR 1, L_0x1305080, L_0x1305230, C4<0>, C4<0>; +L_0x1305010 .delay 1 (30000,30000,30000) L_0x1305010/d; +v0x10f64c0_0 .net *"_s0", 0 0, L_0x1304820; 1 drivers +v0x10f65c0_0 .net *"_s10", 0 0, L_0x1304d30; 1 drivers +v0x10f66a0_0 .net *"_s12", 0 0, L_0x1304e90; 1 drivers +v0x10f6760_0 .net *"_s14", 0 0, L_0x1305080; 1 drivers +v0x10f6840_0 .net *"_s16", 0 0, L_0x1305230; 1 drivers +v0x10f6970_0 .net *"_s3", 0 0, L_0x1304890; 1 drivers +v0x10f6a50_0 .net *"_s5", 0 0, L_0x13049f0; 1 drivers +v0x10f6b30_0 .net *"_s6", 0 0, L_0x1304c20; 1 drivers +v0x10f6c10_0 .net "in", 3 0, L_0x1305460; 1 drivers +v0x10f6d80_0 .net "ors", 1 0, L_0x1304b30; 1 drivers +v0x10f6e60_0 .net "out", 0 0, L_0x1305010; 1 drivers +L_0x1304890 .part L_0x1305460, 0, 1; +L_0x13049f0 .part L_0x1305460, 1, 1; +L_0x1304b30 .concat8 [ 1 1 0 0], L_0x1304820, L_0x1304c20; +L_0x1304d30 .part L_0x1305460, 2, 1; +L_0x1304e90 .part L_0x1305460, 3, 1; +L_0x1305080 .part L_0x1304b30, 0, 1; +L_0x1305230 .part L_0x1304b30, 1, 1; +S_0x10f7770 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x10f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x10fcbb0_0 .net "ands", 7 0, L_0x12ffac0; 1 drivers +v0x10fccc0_0 .net "in", 7 0, L_0x12fda40; alias, 1 drivers +v0x10fcd80_0 .net "out", 0 0, L_0x1301ac0; alias, 1 drivers +v0x10fce50_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x10f79c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10f7770; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x10fa0e0_0 .net "A", 7 0, L_0x12fda40; alias, 1 drivers +v0x10fa1e0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x10fa2a0_0 .net *"_s0", 0 0, L_0x12fe310; 1 drivers +v0x10fa390_0 .net *"_s12", 0 0, L_0x12fecd0; 1 drivers +v0x10fa470_0 .net *"_s16", 0 0, L_0x12ff030; 1 drivers +v0x10fa5a0_0 .net *"_s20", 0 0, L_0x12ff400; 1 drivers +v0x10fa680_0 .net *"_s24", 0 0, L_0x12ff730; 1 drivers +v0x10fa760_0 .net *"_s28", 0 0, L_0x12ff6c0; 1 drivers +v0x10fa840_0 .net *"_s4", 0 0, L_0x12fe6b0; 1 drivers +v0x10fa9b0_0 .net *"_s8", 0 0, L_0x12fe9c0; 1 drivers +v0x10faa90_0 .net "out", 7 0, L_0x12ffac0; alias, 1 drivers +L_0x12fe420 .part L_0x12fda40, 0, 1; +L_0x12fe610 .part v0x127a150_0, 0, 1; +L_0x12fe770 .part L_0x12fda40, 1, 1; +L_0x12fe8d0 .part v0x127a150_0, 1, 1; +L_0x12fea80 .part L_0x12fda40, 2, 1; +L_0x12febe0 .part v0x127a150_0, 2, 1; +L_0x12fed90 .part L_0x12fda40, 3, 1; +L_0x12feef0 .part v0x127a150_0, 3, 1; +L_0x12ff0f0 .part L_0x12fda40, 4, 1; +L_0x12ff360 .part v0x127a150_0, 4, 1; +L_0x12ff470 .part L_0x12fda40, 5, 1; +L_0x12ff5d0 .part v0x127a150_0, 5, 1; +L_0x12ff7f0 .part L_0x12fda40, 6, 1; +L_0x12ff950 .part v0x127a150_0, 6, 1; +LS_0x12ffac0_0_0 .concat8 [ 1 1 1 1], L_0x12fe310, L_0x12fe6b0, L_0x12fe9c0, L_0x12fecd0; +LS_0x12ffac0_0_4 .concat8 [ 1 1 1 1], L_0x12ff030, L_0x12ff400, L_0x12ff730, L_0x12ff6c0; +L_0x12ffac0 .concat8 [ 4 4 0 0], LS_0x12ffac0_0_0, LS_0x12ffac0_0_4; +L_0x12ffe80 .part L_0x12fda40, 7, 1; +L_0x1300070 .part v0x127a150_0, 7, 1; +S_0x10f7c00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f7e10 .param/l "i" 0 4 54, +C4<00>; +L_0x12fe310/d .functor AND 1, L_0x12fe420, L_0x12fe610, C4<1>, C4<1>; +L_0x12fe310 .delay 1 (30000,30000,30000) L_0x12fe310/d; +v0x10f7ef0_0 .net *"_s0", 0 0, L_0x12fe420; 1 drivers +v0x10f7fd0_0 .net *"_s1", 0 0, L_0x12fe610; 1 drivers +S_0x10f80b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f82c0 .param/l "i" 0 4 54, +C4<01>; +L_0x12fe6b0/d .functor AND 1, L_0x12fe770, L_0x12fe8d0, C4<1>, C4<1>; +L_0x12fe6b0 .delay 1 (30000,30000,30000) L_0x12fe6b0/d; +v0x10f8380_0 .net *"_s0", 0 0, L_0x12fe770; 1 drivers +v0x10f8460_0 .net *"_s1", 0 0, L_0x12fe8d0; 1 drivers +S_0x10f8540 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f8780 .param/l "i" 0 4 54, +C4<010>; +L_0x12fe9c0/d .functor AND 1, L_0x12fea80, L_0x12febe0, C4<1>, C4<1>; +L_0x12fe9c0 .delay 1 (30000,30000,30000) L_0x12fe9c0/d; +v0x10f8820_0 .net *"_s0", 0 0, L_0x12fea80; 1 drivers +v0x10f8900_0 .net *"_s1", 0 0, L_0x12febe0; 1 drivers +S_0x10f89e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f8bf0 .param/l "i" 0 4 54, +C4<011>; +L_0x12fecd0/d .functor AND 1, L_0x12fed90, L_0x12feef0, C4<1>, C4<1>; +L_0x12fecd0 .delay 1 (30000,30000,30000) L_0x12fecd0/d; +v0x10f8cb0_0 .net *"_s0", 0 0, L_0x12fed90; 1 drivers +v0x10f8d90_0 .net *"_s1", 0 0, L_0x12feef0; 1 drivers +S_0x10f8e70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f90d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12ff030/d .functor AND 1, L_0x12ff0f0, L_0x12ff360, C4<1>, C4<1>; +L_0x12ff030 .delay 1 (30000,30000,30000) L_0x12ff030/d; +v0x10f9190_0 .net *"_s0", 0 0, L_0x12ff0f0; 1 drivers +v0x10f9270_0 .net *"_s1", 0 0, L_0x12ff360; 1 drivers +S_0x10f9350 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f9560 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ff400/d .functor AND 1, L_0x12ff470, L_0x12ff5d0, C4<1>, C4<1>; +L_0x12ff400 .delay 1 (30000,30000,30000) L_0x12ff400/d; +v0x10f9620_0 .net *"_s0", 0 0, L_0x12ff470; 1 drivers +v0x10f9700_0 .net *"_s1", 0 0, L_0x12ff5d0; 1 drivers +S_0x10f97e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f99f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ff730/d .functor AND 1, L_0x12ff7f0, L_0x12ff950, C4<1>, C4<1>; +L_0x12ff730 .delay 1 (30000,30000,30000) L_0x12ff730/d; +v0x10f9ab0_0 .net *"_s0", 0 0, L_0x12ff7f0; 1 drivers +v0x10f9b90_0 .net *"_s1", 0 0, L_0x12ff950; 1 drivers +S_0x10f9c70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10f79c0; + .timescale -9 -12; +P_0x10f9e80 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ff6c0/d .functor AND 1, L_0x12ffe80, L_0x1300070, C4<1>, C4<1>; +L_0x12ff6c0 .delay 1 (30000,30000,30000) L_0x12ff6c0/d; +v0x10f9f40_0 .net *"_s0", 0 0, L_0x12ffe80; 1 drivers +v0x10fa000_0 .net *"_s1", 0 0, L_0x1300070; 1 drivers +S_0x10fabf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10f7770; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1301ac0/d .functor OR 1, L_0x1301b80, L_0x1301d30, C4<0>, C4<0>; +L_0x1301ac0 .delay 1 (30000,30000,30000) L_0x1301ac0/d; +v0x10fc740_0 .net *"_s10", 0 0, L_0x1301b80; 1 drivers +v0x10fc820_0 .net *"_s12", 0 0, L_0x1301d30; 1 drivers +v0x10fc900_0 .net "in", 7 0, L_0x12ffac0; alias, 1 drivers +v0x10fc9d0_0 .net "ors", 1 0, L_0x13018e0; 1 drivers +v0x10fca90_0 .net "out", 0 0, L_0x1301ac0; alias, 1 drivers +L_0x1300cb0 .part L_0x12ffac0, 0, 4; +L_0x13018e0 .concat8 [ 1 1 0 0], L_0x13009a0, L_0x13015d0; +L_0x1301a20 .part L_0x12ffac0, 4, 4; +L_0x1301b80 .part L_0x13018e0, 0, 1; +L_0x1301d30 .part L_0x13018e0, 1, 1; +S_0x10fadb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10fabf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1300160/d .functor OR 1, L_0x1300220, L_0x1300380, C4<0>, C4<0>; +L_0x1300160 .delay 1 (30000,30000,30000) L_0x1300160/d; +L_0x13005b0/d .functor OR 1, L_0x13006c0, L_0x1300820, C4<0>, C4<0>; +L_0x13005b0 .delay 1 (30000,30000,30000) L_0x13005b0/d; +L_0x13009a0/d .functor OR 1, L_0x1300a10, L_0x1300bc0, C4<0>, C4<0>; +L_0x13009a0 .delay 1 (30000,30000,30000) L_0x13009a0/d; +v0x10fb000_0 .net *"_s0", 0 0, L_0x1300160; 1 drivers +v0x10fb100_0 .net *"_s10", 0 0, L_0x13006c0; 1 drivers +v0x10fb1e0_0 .net *"_s12", 0 0, L_0x1300820; 1 drivers +v0x10fb2a0_0 .net *"_s14", 0 0, L_0x1300a10; 1 drivers +v0x10fb380_0 .net *"_s16", 0 0, L_0x1300bc0; 1 drivers +v0x10fb4b0_0 .net *"_s3", 0 0, L_0x1300220; 1 drivers +v0x10fb590_0 .net *"_s5", 0 0, L_0x1300380; 1 drivers +v0x10fb670_0 .net *"_s6", 0 0, L_0x13005b0; 1 drivers +v0x10fb750_0 .net "in", 3 0, L_0x1300cb0; 1 drivers +v0x10fb8c0_0 .net "ors", 1 0, L_0x13004c0; 1 drivers +v0x10fb9a0_0 .net "out", 0 0, L_0x13009a0; 1 drivers +L_0x1300220 .part L_0x1300cb0, 0, 1; +L_0x1300380 .part L_0x1300cb0, 1, 1; +L_0x13004c0 .concat8 [ 1 1 0 0], L_0x1300160, L_0x13005b0; +L_0x13006c0 .part L_0x1300cb0, 2, 1; +L_0x1300820 .part L_0x1300cb0, 3, 1; +L_0x1300a10 .part L_0x13004c0, 0, 1; +L_0x1300bc0 .part L_0x13004c0, 1, 1; +S_0x10fbac0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10fabf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1300de0/d .functor OR 1, L_0x1300e50, L_0x1300fb0, C4<0>, C4<0>; +L_0x1300de0 .delay 1 (30000,30000,30000) L_0x1300de0/d; +L_0x13011e0/d .functor OR 1, L_0x13012f0, L_0x1301450, C4<0>, C4<0>; +L_0x13011e0 .delay 1 (30000,30000,30000) L_0x13011e0/d; +L_0x13015d0/d .functor OR 1, L_0x1301640, L_0x13017f0, C4<0>, C4<0>; +L_0x13015d0 .delay 1 (30000,30000,30000) L_0x13015d0/d; +v0x10fbc80_0 .net *"_s0", 0 0, L_0x1300de0; 1 drivers +v0x10fbd80_0 .net *"_s10", 0 0, L_0x13012f0; 1 drivers +v0x10fbe60_0 .net *"_s12", 0 0, L_0x1301450; 1 drivers +v0x10fbf20_0 .net *"_s14", 0 0, L_0x1301640; 1 drivers +v0x10fc000_0 .net *"_s16", 0 0, L_0x13017f0; 1 drivers +v0x10fc130_0 .net *"_s3", 0 0, L_0x1300e50; 1 drivers +v0x10fc210_0 .net *"_s5", 0 0, L_0x1300fb0; 1 drivers +v0x10fc2f0_0 .net *"_s6", 0 0, L_0x13011e0; 1 drivers +v0x10fc3d0_0 .net "in", 3 0, L_0x1301a20; 1 drivers +v0x10fc540_0 .net "ors", 1 0, L_0x13010f0; 1 drivers +v0x10fc620_0 .net "out", 0 0, L_0x13015d0; 1 drivers +L_0x1300e50 .part L_0x1301a20, 0, 1; +L_0x1300fb0 .part L_0x1301a20, 1, 1; +L_0x13010f0 .concat8 [ 1 1 0 0], L_0x1300de0, L_0x13011e0; +L_0x13012f0 .part L_0x1301a20, 2, 1; +L_0x1301450 .part L_0x1301a20, 3, 1; +L_0x1301640 .part L_0x13010f0, 0, 1; +L_0x13017f0 .part L_0x13010f0, 1, 1; +S_0x10fcf30 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x10f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x12fc8f0/d .functor XNOR 1, L_0x1305960, L_0x1305ac0, C4<0>, C4<0>; +L_0x12fc8f0 .delay 1 (20000,20000,20000) L_0x12fc8f0/d; +L_0x12fca70/d .functor AND 1, L_0x1305960, L_0x12fb5e0, C4<1>, C4<1>; +L_0x12fca70 .delay 1 (30000,30000,30000) L_0x12fca70/d; +L_0x12fcbd0/d .functor AND 1, L_0x12fc8f0, L_0x12fb410, C4<1>, C4<1>; +L_0x12fcbd0 .delay 1 (30000,30000,30000) L_0x12fcbd0/d; +L_0x12fcce0/d .functor OR 1, L_0x12fcbd0, L_0x12fca70, C4<0>, C4<0>; +L_0x12fcce0 .delay 1 (30000,30000,30000) L_0x12fcce0/d; +v0x10fd1e0_0 .net "a", 0 0, L_0x1305960; alias, 1 drivers +v0x10fd2d0_0 .net "a_", 0 0, L_0x12fb2f0; alias, 1 drivers +v0x10fd390_0 .net "b", 0 0, L_0x1305ac0; alias, 1 drivers +v0x10fd480_0 .net "b_", 0 0, L_0x12fb5e0; alias, 1 drivers +v0x10fd520_0 .net "carryin", 0 0, L_0x12fb410; alias, 1 drivers +v0x10fd660_0 .net "eq", 0 0, L_0x12fc8f0; 1 drivers +v0x10fd720_0 .net "lt", 0 0, L_0x12fca70; 1 drivers +v0x10fd7e0_0 .net "out", 0 0, L_0x12fcce0; 1 drivers +v0x10fd8a0_0 .net "w0", 0 0, L_0x12fcbd0; 1 drivers +S_0x10fdaf0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x12fc4d0/d .functor OR 1, L_0x12fbfd0, L_0x10fed50, C4<0>, C4<0>; +L_0x12fc4d0 .delay 1 (30000,30000,30000) L_0x12fc4d0/d; +v0x10fe8e0_0 .net "a", 0 0, L_0x1305960; alias, 1 drivers +v0x10fea30_0 .net "b", 0 0, L_0x12fb5e0; alias, 1 drivers +v0x10feaf0_0 .net "c1", 0 0, L_0x12fbfd0; 1 drivers +v0x10feb90_0 .net "c2", 0 0, L_0x10fed50; 1 drivers +v0x10fec60_0 .net "carryin", 0 0, L_0x12fb410; alias, 1 drivers +v0x10fede0_0 .net "carryout", 0 0, L_0x12fc4d0; 1 drivers +v0x10fee80_0 .net "s1", 0 0, L_0x12fbf10; 1 drivers +v0x10fef20_0 .net "sum", 0 0, L_0x12fc130; 1 drivers +S_0x10fdd40 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10fdaf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12fbf10/d .functor XOR 1, L_0x1305960, L_0x12fb5e0, C4<0>, C4<0>; +L_0x12fbf10 .delay 1 (30000,30000,30000) L_0x12fbf10/d; +L_0x12fbfd0/d .functor AND 1, L_0x1305960, L_0x12fb5e0, C4<1>, C4<1>; +L_0x12fbfd0 .delay 1 (30000,30000,30000) L_0x12fbfd0/d; +v0x10fdfa0_0 .net "a", 0 0, L_0x1305960; alias, 1 drivers +v0x10fe060_0 .net "b", 0 0, L_0x12fb5e0; alias, 1 drivers +v0x10fe120_0 .net "carryout", 0 0, L_0x12fbfd0; alias, 1 drivers +v0x10fe1c0_0 .net "sum", 0 0, L_0x12fbf10; alias, 1 drivers +S_0x10fe2f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10fdaf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x12fc130/d .functor XOR 1, L_0x12fbf10, L_0x12fb410, C4<0>, C4<0>; +L_0x12fc130 .delay 1 (30000,30000,30000) L_0x12fc130/d; +L_0x10fed50/d .functor AND 1, L_0x12fbf10, L_0x12fb410, C4<1>, C4<1>; +L_0x10fed50 .delay 1 (30000,30000,30000) L_0x10fed50/d; +v0x10fe550_0 .net "a", 0 0, L_0x12fbf10; alias, 1 drivers +v0x10fe620_0 .net "b", 0 0, L_0x12fb410; alias, 1 drivers +v0x10fe6c0_0 .net "carryout", 0 0, L_0x10fed50; alias, 1 drivers +v0x10fe790_0 .net "sum", 0 0, L_0x12fc130; alias, 1 drivers +S_0x1101360 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x10f05d0; + .timescale -9 -12; +L_0x2ac432886228 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886270 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fdd80/d .functor OR 1, L_0x2ac432886228, L_0x2ac432886270, C4<0>, C4<0>; +L_0x12fdd80 .delay 1 (30000,30000,30000) L_0x12fdd80/d; +v0x1101550_0 .net/2u *"_s0", 0 0, L_0x2ac432886228; 1 drivers +v0x1101630_0 .net/2u *"_s2", 0 0, L_0x2ac432886270; 1 drivers +S_0x1101710 .scope generate, "alu_slices[13]" "alu_slices[13]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1101920 .param/l "i" 0 3 39, +C4<01101>; +S_0x11019e0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1101710; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1305d40/d .functor NOT 1, L_0x13101b0, C4<0>, C4<0>, C4<0>; +L_0x1305d40 .delay 1 (10000,10000,10000) L_0x1305d40/d; +L_0x1305e50/d .functor NOT 1, L_0x1305b60, C4<0>, C4<0>, C4<0>; +L_0x1305e50 .delay 1 (10000,10000,10000) L_0x1305e50/d; +L_0x1306ea0/d .functor XOR 1, L_0x13101b0, L_0x1305b60, C4<0>, C4<0>; +L_0x1306ea0 .delay 1 (30000,30000,30000) L_0x1306ea0/d; +L_0x2ac4328862b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886300 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1306f60/d .functor OR 1, L_0x2ac4328862b8, L_0x2ac432886300, C4<0>, C4<0>; +L_0x1306f60 .delay 1 (30000,30000,30000) L_0x1306f60/d; +L_0x2ac432886348 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886390 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1307660/d .functor OR 1, L_0x2ac432886348, L_0x2ac432886390, C4<0>, C4<0>; +L_0x1307660 .delay 1 (30000,30000,30000) L_0x1307660/d; +L_0x1307860/d .functor AND 1, L_0x13101b0, L_0x1305b60, C4<1>, C4<1>; +L_0x1307860 .delay 1 (30000,30000,30000) L_0x1307860/d; +L_0x2ac4328863d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886420 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1307920/d .functor OR 1, L_0x2ac4328863d8, L_0x2ac432886420, C4<0>, C4<0>; +L_0x1307920 .delay 1 (30000,30000,30000) L_0x1307920/d; +L_0x1307b20/d .functor NAND 1, L_0x13101b0, L_0x1305b60, C4<1>, C4<1>; +L_0x1307b20 .delay 1 (20000,20000,20000) L_0x1307b20/d; +L_0x2ac432886468 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328864b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1307c30/d .functor OR 1, L_0x2ac432886468, L_0x2ac4328864b0, C4<0>, C4<0>; +L_0x1307c30 .delay 1 (30000,30000,30000) L_0x1307c30/d; +L_0x1307de0/d .functor NOR 1, L_0x13101b0, L_0x1305b60, C4<0>, C4<0>; +L_0x1307de0 .delay 1 (20000,20000,20000) L_0x1307de0/d; +L_0x2ac4328864f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886540 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13080b0/d .functor OR 1, L_0x2ac4328864f8, L_0x2ac432886540, C4<0>, C4<0>; +L_0x13080b0 .delay 1 (30000,30000,30000) L_0x13080b0/d; +L_0x13084b0/d .functor OR 1, L_0x13101b0, L_0x1305b60, C4<0>, C4<0>; +L_0x13084b0 .delay 1 (30000,30000,30000) L_0x13084b0/d; +L_0x2ac432886588 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328865d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1308950/d .functor OR 1, L_0x2ac432886588, L_0x2ac4328865d0, C4<0>, C4<0>; +L_0x1308950 .delay 1 (30000,30000,30000) L_0x1308950/d; +L_0x13100b0/d .functor NOT 1, L_0x130c310, C4<0>, C4<0>, C4<0>; +L_0x13100b0 .delay 1 (10000,10000,10000) L_0x13100b0/d; +v0x11101a0_0 .net "A", 0 0, L_0x13101b0; 1 drivers +v0x1110260_0 .net "A_", 0 0, L_0x1305d40; 1 drivers +v0x1110320_0 .net "B", 0 0, L_0x1305b60; 1 drivers +v0x11103f0_0 .net "B_", 0 0, L_0x1305e50; 1 drivers +v0x1110490_0 .net *"_s11", 0 0, L_0x1306f60; 1 drivers +v0x1110580_0 .net/2s *"_s13", 0 0, L_0x2ac4328862b8; 1 drivers +v0x1110640_0 .net/2s *"_s15", 0 0, L_0x2ac432886300; 1 drivers +v0x1110720_0 .net *"_s19", 0 0, L_0x1307660; 1 drivers +v0x1110800_0 .net/2s *"_s21", 0 0, L_0x2ac432886348; 1 drivers +v0x1110970_0 .net/2s *"_s23", 0 0, L_0x2ac432886390; 1 drivers +v0x1110a50_0 .net *"_s25", 0 0, L_0x1307860; 1 drivers +v0x1110b30_0 .net *"_s28", 0 0, L_0x1307920; 1 drivers +v0x1110c10_0 .net/2s *"_s30", 0 0, L_0x2ac4328863d8; 1 drivers +v0x1110cf0_0 .net/2s *"_s32", 0 0, L_0x2ac432886420; 1 drivers +v0x1110dd0_0 .net *"_s34", 0 0, L_0x1307b20; 1 drivers +v0x1110eb0_0 .net *"_s37", 0 0, L_0x1307c30; 1 drivers +v0x1110f90_0 .net/2s *"_s39", 0 0, L_0x2ac432886468; 1 drivers +v0x1111140_0 .net/2s *"_s41", 0 0, L_0x2ac4328864b0; 1 drivers +v0x11111e0_0 .net *"_s43", 0 0, L_0x1307de0; 1 drivers +v0x11112c0_0 .net *"_s46", 0 0, L_0x13080b0; 1 drivers +v0x11113a0_0 .net/2s *"_s48", 0 0, L_0x2ac4328864f8; 1 drivers +v0x1111480_0 .net/2s *"_s50", 0 0, L_0x2ac432886540; 1 drivers +v0x1111560_0 .net *"_s52", 0 0, L_0x13084b0; 1 drivers +v0x1111640_0 .net *"_s56", 0 0, L_0x1308950; 1 drivers +v0x1111720_0 .net/2s *"_s59", 0 0, L_0x2ac432886588; 1 drivers +v0x1111800_0 .net/2s *"_s61", 0 0, L_0x2ac4328865d0; 1 drivers +v0x11118e0_0 .net *"_s8", 0 0, L_0x1306ea0; 1 drivers +v0x11119c0_0 .net "carryin", 0 0, L_0x1305c00; 1 drivers +v0x1111a60_0 .net "carryout", 0 0, L_0x130fd50; 1 drivers +v0x1111b00_0 .net "carryouts", 7 0, L_0x13085c0; 1 drivers +v0x1111c10_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1111cd0_0 .net "result", 0 0, L_0x130c310; 1 drivers +v0x1111dc0_0 .net "results", 7 0, L_0x1308280; 1 drivers +v0x11110a0_0 .net "zero", 0 0, L_0x13100b0; 1 drivers +LS_0x1308280_0_0 .concat8 [ 1 1 1 1], L_0x1306370, L_0x13069a0, L_0x1306ea0, L_0x1307660; +LS_0x1308280_0_4 .concat8 [ 1 1 1 1], L_0x1307860, L_0x1307b20, L_0x1307de0, L_0x13084b0; +L_0x1308280 .concat8 [ 4 4 0 0], LS_0x1308280_0_0, LS_0x1308280_0_4; +LS_0x13085c0_0_0 .concat8 [ 1 1 1 1], L_0x1306620, L_0x1306d40, L_0x1306f60, L_0x13074b0; +LS_0x13085c0_0_4 .concat8 [ 1 1 1 1], L_0x1307920, L_0x1307c30, L_0x13080b0, L_0x1308950; +L_0x13085c0 .concat8 [ 4 4 0 0], LS_0x13085c0_0_0, LS_0x13085c0_0_4; +S_0x1101c60 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11019e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1306620/d .functor OR 1, L_0x1306100, L_0x13064c0, C4<0>, C4<0>; +L_0x1306620 .delay 1 (30000,30000,30000) L_0x1306620/d; +v0x1102b20_0 .net "a", 0 0, L_0x13101b0; alias, 1 drivers +v0x1102be0_0 .net "b", 0 0, L_0x1305b60; alias, 1 drivers +v0x1102cb0_0 .net "c1", 0 0, L_0x1306100; 1 drivers +v0x1102db0_0 .net "c2", 0 0, L_0x13064c0; 1 drivers +v0x1102e80_0 .net "carryin", 0 0, L_0x1305c00; alias, 1 drivers +v0x1102f70_0 .net "carryout", 0 0, L_0x1306620; 1 drivers +v0x1103010_0 .net "s1", 0 0, L_0x1306040; 1 drivers +v0x1103100_0 .net "sum", 0 0, L_0x1306370; 1 drivers +S_0x1101ed0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1101c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1306040/d .functor XOR 1, L_0x13101b0, L_0x1305b60, C4<0>, C4<0>; +L_0x1306040 .delay 1 (30000,30000,30000) L_0x1306040/d; +L_0x1306100/d .functor AND 1, L_0x13101b0, L_0x1305b60, C4<1>, C4<1>; +L_0x1306100 .delay 1 (30000,30000,30000) L_0x1306100/d; +v0x1102130_0 .net "a", 0 0, L_0x13101b0; alias, 1 drivers +v0x1102210_0 .net "b", 0 0, L_0x1305b60; alias, 1 drivers +v0x11022d0_0 .net "carryout", 0 0, L_0x1306100; alias, 1 drivers +v0x11023a0_0 .net "sum", 0 0, L_0x1306040; alias, 1 drivers +S_0x1102510 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1101c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1306370/d .functor XOR 1, L_0x1306040, L_0x1305c00, C4<0>, C4<0>; +L_0x1306370 .delay 1 (30000,30000,30000) L_0x1306370/d; +L_0x13064c0/d .functor AND 1, L_0x1306040, L_0x1305c00, C4<1>, C4<1>; +L_0x13064c0 .delay 1 (30000,30000,30000) L_0x13064c0/d; +v0x1102770_0 .net "a", 0 0, L_0x1306040; alias, 1 drivers +v0x1102840_0 .net "b", 0 0, L_0x1305c00; alias, 1 drivers +v0x11028e0_0 .net "carryout", 0 0, L_0x13064c0; alias, 1 drivers +v0x11029b0_0 .net "sum", 0 0, L_0x1306370; alias, 1 drivers +S_0x11031d0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11019e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11085c0_0 .net "ands", 7 0, L_0x130dd50; 1 drivers +v0x11086d0_0 .net "in", 7 0, L_0x13085c0; alias, 1 drivers +v0x1108790_0 .net "out", 0 0, L_0x130fd50; alias, 1 drivers +v0x1108860_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11033f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11031d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1105b20_0 .net "A", 7 0, L_0x13085c0; alias, 1 drivers +v0x1105c20_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1105ce0_0 .net *"_s0", 0 0, L_0x130c670; 1 drivers +v0x1105da0_0 .net *"_s12", 0 0, L_0x130cfe0; 1 drivers +v0x1105e80_0 .net *"_s16", 0 0, L_0x130d340; 1 drivers +v0x1105fb0_0 .net *"_s20", 0 0, L_0x130d710; 1 drivers +v0x1106090_0 .net *"_s24", 0 0, L_0x130da40; 1 drivers +v0x1106170_0 .net *"_s28", 0 0, L_0x130d9d0; 1 drivers +v0x1106250_0 .net *"_s4", 0 0, L_0x130c9c0; 1 drivers +v0x11063c0_0 .net *"_s8", 0 0, L_0x130ccd0; 1 drivers +v0x11064a0_0 .net "out", 7 0, L_0x130dd50; alias, 1 drivers +L_0x130c730 .part L_0x13085c0, 0, 1; +L_0x130c920 .part v0x127a150_0, 0, 1; +L_0x130ca80 .part L_0x13085c0, 1, 1; +L_0x130cbe0 .part v0x127a150_0, 1, 1; +L_0x130cd90 .part L_0x13085c0, 2, 1; +L_0x130cef0 .part v0x127a150_0, 2, 1; +L_0x130d0a0 .part L_0x13085c0, 3, 1; +L_0x130d200 .part v0x127a150_0, 3, 1; +L_0x130d400 .part L_0x13085c0, 4, 1; +L_0x130d670 .part v0x127a150_0, 4, 1; +L_0x130d780 .part L_0x13085c0, 5, 1; +L_0x130d8e0 .part v0x127a150_0, 5, 1; +L_0x130db00 .part L_0x13085c0, 6, 1; +L_0x130dc60 .part v0x127a150_0, 6, 1; +LS_0x130dd50_0_0 .concat8 [ 1 1 1 1], L_0x130c670, L_0x130c9c0, L_0x130ccd0, L_0x130cfe0; +LS_0x130dd50_0_4 .concat8 [ 1 1 1 1], L_0x130d340, L_0x130d710, L_0x130da40, L_0x130d9d0; +L_0x130dd50 .concat8 [ 4 4 0 0], LS_0x130dd50_0_0, LS_0x130dd50_0_4; +L_0x130e110 .part L_0x13085c0, 7, 1; +L_0x130e300 .part v0x127a150_0, 7, 1; +S_0x1103650 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x1103860 .param/l "i" 0 4 54, +C4<00>; +L_0x130c670/d .functor AND 1, L_0x130c730, L_0x130c920, C4<1>, C4<1>; +L_0x130c670 .delay 1 (30000,30000,30000) L_0x130c670/d; +v0x1103940_0 .net *"_s0", 0 0, L_0x130c730; 1 drivers +v0x1103a20_0 .net *"_s1", 0 0, L_0x130c920; 1 drivers +S_0x1103b00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x1103d10 .param/l "i" 0 4 54, +C4<01>; +L_0x130c9c0/d .functor AND 1, L_0x130ca80, L_0x130cbe0, C4<1>, C4<1>; +L_0x130c9c0 .delay 1 (30000,30000,30000) L_0x130c9c0/d; +v0x1103dd0_0 .net *"_s0", 0 0, L_0x130ca80; 1 drivers +v0x1103eb0_0 .net *"_s1", 0 0, L_0x130cbe0; 1 drivers +S_0x1103f90 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x11041a0 .param/l "i" 0 4 54, +C4<010>; +L_0x130ccd0/d .functor AND 1, L_0x130cd90, L_0x130cef0, C4<1>, C4<1>; +L_0x130ccd0 .delay 1 (30000,30000,30000) L_0x130ccd0/d; +v0x1104240_0 .net *"_s0", 0 0, L_0x130cd90; 1 drivers +v0x1104320_0 .net *"_s1", 0 0, L_0x130cef0; 1 drivers +S_0x1104400 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x1104610 .param/l "i" 0 4 54, +C4<011>; +L_0x130cfe0/d .functor AND 1, L_0x130d0a0, L_0x130d200, C4<1>, C4<1>; +L_0x130cfe0 .delay 1 (30000,30000,30000) L_0x130cfe0/d; +v0x11046d0_0 .net *"_s0", 0 0, L_0x130d0a0; 1 drivers +v0x11047b0_0 .net *"_s1", 0 0, L_0x130d200; 1 drivers +S_0x1104890 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x1104af0 .param/l "i" 0 4 54, +C4<0100>; +L_0x130d340/d .functor AND 1, L_0x130d400, L_0x130d670, C4<1>, C4<1>; +L_0x130d340 .delay 1 (30000,30000,30000) L_0x130d340/d; +v0x1104bb0_0 .net *"_s0", 0 0, L_0x130d400; 1 drivers +v0x1104c90_0 .net *"_s1", 0 0, L_0x130d670; 1 drivers +S_0x1104d70 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x1104f80 .param/l "i" 0 4 54, +C4<0101>; +L_0x130d710/d .functor AND 1, L_0x130d780, L_0x130d8e0, C4<1>, C4<1>; +L_0x130d710 .delay 1 (30000,30000,30000) L_0x130d710/d; +v0x1105040_0 .net *"_s0", 0 0, L_0x130d780; 1 drivers +v0x1105120_0 .net *"_s1", 0 0, L_0x130d8e0; 1 drivers +S_0x1105200 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x1105410 .param/l "i" 0 4 54, +C4<0110>; +L_0x130da40/d .functor AND 1, L_0x130db00, L_0x130dc60, C4<1>, C4<1>; +L_0x130da40 .delay 1 (30000,30000,30000) L_0x130da40/d; +v0x11054d0_0 .net *"_s0", 0 0, L_0x130db00; 1 drivers +v0x11055b0_0 .net *"_s1", 0 0, L_0x130dc60; 1 drivers +S_0x1105690 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11033f0; + .timescale -9 -12; +P_0x11058a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x130d9d0/d .functor AND 1, L_0x130e110, L_0x130e300, C4<1>, C4<1>; +L_0x130d9d0 .delay 1 (30000,30000,30000) L_0x130d9d0/d; +v0x1105960_0 .net *"_s0", 0 0, L_0x130e110; 1 drivers +v0x1105a40_0 .net *"_s1", 0 0, L_0x130e300; 1 drivers +S_0x1106600 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11031d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x130fd50/d .functor OR 1, L_0x130fe10, L_0x130ffc0, C4<0>, C4<0>; +L_0x130fd50 .delay 1 (30000,30000,30000) L_0x130fd50/d; +v0x1108150_0 .net *"_s10", 0 0, L_0x130fe10; 1 drivers +v0x1108230_0 .net *"_s12", 0 0, L_0x130ffc0; 1 drivers +v0x1108310_0 .net "in", 7 0, L_0x130dd50; alias, 1 drivers +v0x11083e0_0 .net "ors", 1 0, L_0x130fb70; 1 drivers +v0x11084a0_0 .net "out", 0 0, L_0x130fd50; alias, 1 drivers +L_0x130ef40 .part L_0x130dd50, 0, 4; +L_0x130fb70 .concat8 [ 1 1 0 0], L_0x130ec30, L_0x130f860; +L_0x130fcb0 .part L_0x130dd50, 4, 4; +L_0x130fe10 .part L_0x130fb70, 0, 1; +L_0x130ffc0 .part L_0x130fb70, 1, 1; +S_0x11067c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1106600; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x130e3f0/d .functor OR 1, L_0x130e4b0, L_0x130e610, C4<0>, C4<0>; +L_0x130e3f0 .delay 1 (30000,30000,30000) L_0x130e3f0/d; +L_0x130e840/d .functor OR 1, L_0x130e950, L_0x130eab0, C4<0>, C4<0>; +L_0x130e840 .delay 1 (30000,30000,30000) L_0x130e840/d; +L_0x130ec30/d .functor OR 1, L_0x130eca0, L_0x130ee50, C4<0>, C4<0>; +L_0x130ec30 .delay 1 (30000,30000,30000) L_0x130ec30/d; +v0x1106a10_0 .net *"_s0", 0 0, L_0x130e3f0; 1 drivers +v0x1106b10_0 .net *"_s10", 0 0, L_0x130e950; 1 drivers +v0x1106bf0_0 .net *"_s12", 0 0, L_0x130eab0; 1 drivers +v0x1106cb0_0 .net *"_s14", 0 0, L_0x130eca0; 1 drivers +v0x1106d90_0 .net *"_s16", 0 0, L_0x130ee50; 1 drivers +v0x1106ec0_0 .net *"_s3", 0 0, L_0x130e4b0; 1 drivers +v0x1106fa0_0 .net *"_s5", 0 0, L_0x130e610; 1 drivers +v0x1107080_0 .net *"_s6", 0 0, L_0x130e840; 1 drivers +v0x1107160_0 .net "in", 3 0, L_0x130ef40; 1 drivers +v0x11072d0_0 .net "ors", 1 0, L_0x130e750; 1 drivers +v0x11073b0_0 .net "out", 0 0, L_0x130ec30; 1 drivers +L_0x130e4b0 .part L_0x130ef40, 0, 1; +L_0x130e610 .part L_0x130ef40, 1, 1; +L_0x130e750 .concat8 [ 1 1 0 0], L_0x130e3f0, L_0x130e840; +L_0x130e950 .part L_0x130ef40, 2, 1; +L_0x130eab0 .part L_0x130ef40, 3, 1; +L_0x130eca0 .part L_0x130e750, 0, 1; +L_0x130ee50 .part L_0x130e750, 1, 1; +S_0x11074d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1106600; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x130f070/d .functor OR 1, L_0x130f0e0, L_0x130f240, C4<0>, C4<0>; +L_0x130f070 .delay 1 (30000,30000,30000) L_0x130f070/d; +L_0x130f470/d .functor OR 1, L_0x130f580, L_0x130f6e0, C4<0>, C4<0>; +L_0x130f470 .delay 1 (30000,30000,30000) L_0x130f470/d; +L_0x130f860/d .functor OR 1, L_0x130f8d0, L_0x130fa80, C4<0>, C4<0>; +L_0x130f860 .delay 1 (30000,30000,30000) L_0x130f860/d; +v0x1107690_0 .net *"_s0", 0 0, L_0x130f070; 1 drivers +v0x1107790_0 .net *"_s10", 0 0, L_0x130f580; 1 drivers +v0x1107870_0 .net *"_s12", 0 0, L_0x130f6e0; 1 drivers +v0x1107930_0 .net *"_s14", 0 0, L_0x130f8d0; 1 drivers +v0x1107a10_0 .net *"_s16", 0 0, L_0x130fa80; 1 drivers +v0x1107b40_0 .net *"_s3", 0 0, L_0x130f0e0; 1 drivers +v0x1107c20_0 .net *"_s5", 0 0, L_0x130f240; 1 drivers +v0x1107d00_0 .net *"_s6", 0 0, L_0x130f470; 1 drivers +v0x1107de0_0 .net "in", 3 0, L_0x130fcb0; 1 drivers +v0x1107f50_0 .net "ors", 1 0, L_0x130f380; 1 drivers +v0x1108030_0 .net "out", 0 0, L_0x130f860; 1 drivers +L_0x130f0e0 .part L_0x130fcb0, 0, 1; +L_0x130f240 .part L_0x130fcb0, 1, 1; +L_0x130f380 .concat8 [ 1 1 0 0], L_0x130f070, L_0x130f470; +L_0x130f580 .part L_0x130fcb0, 2, 1; +L_0x130f6e0 .part L_0x130fcb0, 3, 1; +L_0x130f8d0 .part L_0x130f380, 0, 1; +L_0x130fa80 .part L_0x130f380, 1, 1; +S_0x1108940 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11019e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x110dd70_0 .net "ands", 7 0, L_0x130a310; 1 drivers +v0x110de80_0 .net "in", 7 0, L_0x1308280; alias, 1 drivers +v0x110df40_0 .net "out", 0 0, L_0x130c310; alias, 1 drivers +v0x110e010_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1108b90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1108940; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x110b2d0_0 .net "A", 7 0, L_0x1308280; alias, 1 drivers +v0x110b3d0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x110b490_0 .net *"_s0", 0 0, L_0x1308b00; 1 drivers +v0x110b550_0 .net *"_s12", 0 0, L_0x13094c0; 1 drivers +v0x110b630_0 .net *"_s16", 0 0, L_0x1309820; 1 drivers +v0x110b760_0 .net *"_s20", 0 0, L_0x1309c50; 1 drivers +v0x110b840_0 .net *"_s24", 0 0, L_0x1309f80; 1 drivers +v0x110b920_0 .net *"_s28", 0 0, L_0x1309f10; 1 drivers +v0x110ba00_0 .net *"_s4", 0 0, L_0x1308ea0; 1 drivers +v0x110bb70_0 .net *"_s8", 0 0, L_0x13091b0; 1 drivers +v0x110bc50_0 .net "out", 7 0, L_0x130a310; alias, 1 drivers +L_0x1308c10 .part L_0x1308280, 0, 1; +L_0x1308e00 .part v0x127a150_0, 0, 1; +L_0x1308f60 .part L_0x1308280, 1, 1; +L_0x13090c0 .part v0x127a150_0, 1, 1; +L_0x1309270 .part L_0x1308280, 2, 1; +L_0x13093d0 .part v0x127a150_0, 2, 1; +L_0x1309580 .part L_0x1308280, 3, 1; +L_0x13096e0 .part v0x127a150_0, 3, 1; +L_0x13098e0 .part L_0x1308280, 4, 1; +L_0x1309b50 .part v0x127a150_0, 4, 1; +L_0x1309cc0 .part L_0x1308280, 5, 1; +L_0x1309e20 .part v0x127a150_0, 5, 1; +L_0x130a040 .part L_0x1308280, 6, 1; +L_0x130a1a0 .part v0x127a150_0, 6, 1; +LS_0x130a310_0_0 .concat8 [ 1 1 1 1], L_0x1308b00, L_0x1308ea0, L_0x13091b0, L_0x13094c0; +LS_0x130a310_0_4 .concat8 [ 1 1 1 1], L_0x1309820, L_0x1309c50, L_0x1309f80, L_0x1309f10; +L_0x130a310 .concat8 [ 4 4 0 0], LS_0x130a310_0_0, LS_0x130a310_0_4; +L_0x130a6d0 .part L_0x1308280, 7, 1; +L_0x130a8c0 .part v0x127a150_0, 7, 1; +S_0x1108dd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x1108fe0 .param/l "i" 0 4 54, +C4<00>; +L_0x1308b00/d .functor AND 1, L_0x1308c10, L_0x1308e00, C4<1>, C4<1>; +L_0x1308b00 .delay 1 (30000,30000,30000) L_0x1308b00/d; +v0x11090c0_0 .net *"_s0", 0 0, L_0x1308c10; 1 drivers +v0x11091a0_0 .net *"_s1", 0 0, L_0x1308e00; 1 drivers +S_0x1109280 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x1109490 .param/l "i" 0 4 54, +C4<01>; +L_0x1308ea0/d .functor AND 1, L_0x1308f60, L_0x13090c0, C4<1>, C4<1>; +L_0x1308ea0 .delay 1 (30000,30000,30000) L_0x1308ea0/d; +v0x1109550_0 .net *"_s0", 0 0, L_0x1308f60; 1 drivers +v0x1109630_0 .net *"_s1", 0 0, L_0x13090c0; 1 drivers +S_0x1109710 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x1109950 .param/l "i" 0 4 54, +C4<010>; +L_0x13091b0/d .functor AND 1, L_0x1309270, L_0x13093d0, C4<1>, C4<1>; +L_0x13091b0 .delay 1 (30000,30000,30000) L_0x13091b0/d; +v0x11099f0_0 .net *"_s0", 0 0, L_0x1309270; 1 drivers +v0x1109ad0_0 .net *"_s1", 0 0, L_0x13093d0; 1 drivers +S_0x1109bb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x1109dc0 .param/l "i" 0 4 54, +C4<011>; +L_0x13094c0/d .functor AND 1, L_0x1309580, L_0x13096e0, C4<1>, C4<1>; +L_0x13094c0 .delay 1 (30000,30000,30000) L_0x13094c0/d; +v0x1109e80_0 .net *"_s0", 0 0, L_0x1309580; 1 drivers +v0x1109f60_0 .net *"_s1", 0 0, L_0x13096e0; 1 drivers +S_0x110a040 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x110a2a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1309820/d .functor AND 1, L_0x13098e0, L_0x1309b50, C4<1>, C4<1>; +L_0x1309820 .delay 1 (30000,30000,30000) L_0x1309820/d; +v0x110a360_0 .net *"_s0", 0 0, L_0x13098e0; 1 drivers +v0x110a440_0 .net *"_s1", 0 0, L_0x1309b50; 1 drivers +S_0x110a520 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x110a730 .param/l "i" 0 4 54, +C4<0101>; +L_0x1309c50/d .functor AND 1, L_0x1309cc0, L_0x1309e20, C4<1>, C4<1>; +L_0x1309c50 .delay 1 (30000,30000,30000) L_0x1309c50/d; +v0x110a7f0_0 .net *"_s0", 0 0, L_0x1309cc0; 1 drivers +v0x110a8d0_0 .net *"_s1", 0 0, L_0x1309e20; 1 drivers +S_0x110a9b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x110abc0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1309f80/d .functor AND 1, L_0x130a040, L_0x130a1a0, C4<1>, C4<1>; +L_0x1309f80 .delay 1 (30000,30000,30000) L_0x1309f80/d; +v0x110ac80_0 .net *"_s0", 0 0, L_0x130a040; 1 drivers +v0x110ad60_0 .net *"_s1", 0 0, L_0x130a1a0; 1 drivers +S_0x110ae40 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1108b90; + .timescale -9 -12; +P_0x110b050 .param/l "i" 0 4 54, +C4<0111>; +L_0x1309f10/d .functor AND 1, L_0x130a6d0, L_0x130a8c0, C4<1>, C4<1>; +L_0x1309f10 .delay 1 (30000,30000,30000) L_0x1309f10/d; +v0x110b110_0 .net *"_s0", 0 0, L_0x130a6d0; 1 drivers +v0x110b1f0_0 .net *"_s1", 0 0, L_0x130a8c0; 1 drivers +S_0x110bdb0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1108940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x130c310/d .functor OR 1, L_0x130c3d0, L_0x130c580, C4<0>, C4<0>; +L_0x130c310 .delay 1 (30000,30000,30000) L_0x130c310/d; +v0x110d900_0 .net *"_s10", 0 0, L_0x130c3d0; 1 drivers +v0x110d9e0_0 .net *"_s12", 0 0, L_0x130c580; 1 drivers +v0x110dac0_0 .net "in", 7 0, L_0x130a310; alias, 1 drivers +v0x110db90_0 .net "ors", 1 0, L_0x130c130; 1 drivers +v0x110dc50_0 .net "out", 0 0, L_0x130c310; alias, 1 drivers +L_0x130b500 .part L_0x130a310, 0, 4; +L_0x130c130 .concat8 [ 1 1 0 0], L_0x130b1f0, L_0x130be20; +L_0x130c270 .part L_0x130a310, 4, 4; +L_0x130c3d0 .part L_0x130c130, 0, 1; +L_0x130c580 .part L_0x130c130, 1, 1; +S_0x110bf70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x110bdb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x130a9b0/d .functor OR 1, L_0x130aa70, L_0x130abd0, C4<0>, C4<0>; +L_0x130a9b0 .delay 1 (30000,30000,30000) L_0x130a9b0/d; +L_0x130ae00/d .functor OR 1, L_0x130af10, L_0x130b070, C4<0>, C4<0>; +L_0x130ae00 .delay 1 (30000,30000,30000) L_0x130ae00/d; +L_0x130b1f0/d .functor OR 1, L_0x130b260, L_0x130b410, C4<0>, C4<0>; +L_0x130b1f0 .delay 1 (30000,30000,30000) L_0x130b1f0/d; +v0x110c1c0_0 .net *"_s0", 0 0, L_0x130a9b0; 1 drivers +v0x110c2c0_0 .net *"_s10", 0 0, L_0x130af10; 1 drivers +v0x110c3a0_0 .net *"_s12", 0 0, L_0x130b070; 1 drivers +v0x110c460_0 .net *"_s14", 0 0, L_0x130b260; 1 drivers +v0x110c540_0 .net *"_s16", 0 0, L_0x130b410; 1 drivers +v0x110c670_0 .net *"_s3", 0 0, L_0x130aa70; 1 drivers +v0x110c750_0 .net *"_s5", 0 0, L_0x130abd0; 1 drivers +v0x110c830_0 .net *"_s6", 0 0, L_0x130ae00; 1 drivers +v0x110c910_0 .net "in", 3 0, L_0x130b500; 1 drivers +v0x110ca80_0 .net "ors", 1 0, L_0x130ad10; 1 drivers +v0x110cb60_0 .net "out", 0 0, L_0x130b1f0; 1 drivers +L_0x130aa70 .part L_0x130b500, 0, 1; +L_0x130abd0 .part L_0x130b500, 1, 1; +L_0x130ad10 .concat8 [ 1 1 0 0], L_0x130a9b0, L_0x130ae00; +L_0x130af10 .part L_0x130b500, 2, 1; +L_0x130b070 .part L_0x130b500, 3, 1; +L_0x130b260 .part L_0x130ad10, 0, 1; +L_0x130b410 .part L_0x130ad10, 1, 1; +S_0x110cc80 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x110bdb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x130b630/d .functor OR 1, L_0x130b6a0, L_0x130b800, C4<0>, C4<0>; +L_0x130b630 .delay 1 (30000,30000,30000) L_0x130b630/d; +L_0x130ba30/d .functor OR 1, L_0x130bb40, L_0x130bca0, C4<0>, C4<0>; +L_0x130ba30 .delay 1 (30000,30000,30000) L_0x130ba30/d; +L_0x130be20/d .functor OR 1, L_0x130be90, L_0x130c040, C4<0>, C4<0>; +L_0x130be20 .delay 1 (30000,30000,30000) L_0x130be20/d; +v0x110ce40_0 .net *"_s0", 0 0, L_0x130b630; 1 drivers +v0x110cf40_0 .net *"_s10", 0 0, L_0x130bb40; 1 drivers +v0x110d020_0 .net *"_s12", 0 0, L_0x130bca0; 1 drivers +v0x110d0e0_0 .net *"_s14", 0 0, L_0x130be90; 1 drivers +v0x110d1c0_0 .net *"_s16", 0 0, L_0x130c040; 1 drivers +v0x110d2f0_0 .net *"_s3", 0 0, L_0x130b6a0; 1 drivers +v0x110d3d0_0 .net *"_s5", 0 0, L_0x130b800; 1 drivers +v0x110d4b0_0 .net *"_s6", 0 0, L_0x130ba30; 1 drivers +v0x110d590_0 .net "in", 3 0, L_0x130c270; 1 drivers +v0x110d700_0 .net "ors", 1 0, L_0x130b940; 1 drivers +v0x110d7e0_0 .net "out", 0 0, L_0x130be20; 1 drivers +L_0x130b6a0 .part L_0x130c270, 0, 1; +L_0x130b800 .part L_0x130c270, 1, 1; +L_0x130b940 .concat8 [ 1 1 0 0], L_0x130b630, L_0x130ba30; +L_0x130bb40 .part L_0x130c270, 2, 1; +L_0x130bca0 .part L_0x130c270, 3, 1; +L_0x130be90 .part L_0x130b940, 0, 1; +L_0x130c040 .part L_0x130b940, 1, 1; +S_0x110e0f0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11019e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1307070/d .functor XNOR 1, L_0x13101b0, L_0x1305b60, C4<0>, C4<0>; +L_0x1307070 .delay 1 (20000,20000,20000) L_0x1307070/d; +L_0x1307240/d .functor AND 1, L_0x13101b0, L_0x1305e50, C4<1>, C4<1>; +L_0x1307240 .delay 1 (30000,30000,30000) L_0x1307240/d; +L_0x13073a0/d .functor AND 1, L_0x1307070, L_0x1305c00, C4<1>, C4<1>; +L_0x13073a0 .delay 1 (30000,30000,30000) L_0x13073a0/d; +L_0x13074b0/d .functor OR 1, L_0x13073a0, L_0x1307240, C4<0>, C4<0>; +L_0x13074b0 .delay 1 (30000,30000,30000) L_0x13074b0/d; +v0x110e3a0_0 .net "a", 0 0, L_0x13101b0; alias, 1 drivers +v0x110e490_0 .net "a_", 0 0, L_0x1305d40; alias, 1 drivers +v0x110e550_0 .net "b", 0 0, L_0x1305b60; alias, 1 drivers +v0x110e640_0 .net "b_", 0 0, L_0x1305e50; alias, 1 drivers +v0x110e6e0_0 .net "carryin", 0 0, L_0x1305c00; alias, 1 drivers +v0x110e820_0 .net "eq", 0 0, L_0x1307070; 1 drivers +v0x110e8e0_0 .net "lt", 0 0, L_0x1307240; 1 drivers +v0x110e9a0_0 .net "out", 0 0, L_0x13074b0; 1 drivers +v0x110ea60_0 .net "w0", 0 0, L_0x13073a0; 1 drivers +S_0x110ecb0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11019e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1306d40/d .functor OR 1, L_0x1306840, L_0x110ff10, C4<0>, C4<0>; +L_0x1306d40 .delay 1 (30000,30000,30000) L_0x1306d40/d; +v0x110faa0_0 .net "a", 0 0, L_0x13101b0; alias, 1 drivers +v0x110fbf0_0 .net "b", 0 0, L_0x1305e50; alias, 1 drivers +v0x110fcb0_0 .net "c1", 0 0, L_0x1306840; 1 drivers +v0x110fd50_0 .net "c2", 0 0, L_0x110ff10; 1 drivers +v0x110fe20_0 .net "carryin", 0 0, L_0x1305c00; alias, 1 drivers +v0x110ffa0_0 .net "carryout", 0 0, L_0x1306d40; 1 drivers +v0x1110040_0 .net "s1", 0 0, L_0x1306780; 1 drivers +v0x11100e0_0 .net "sum", 0 0, L_0x13069a0; 1 drivers +S_0x110ef00 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x110ecb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1306780/d .functor XOR 1, L_0x13101b0, L_0x1305e50, C4<0>, C4<0>; +L_0x1306780 .delay 1 (30000,30000,30000) L_0x1306780/d; +L_0x1306840/d .functor AND 1, L_0x13101b0, L_0x1305e50, C4<1>, C4<1>; +L_0x1306840 .delay 1 (30000,30000,30000) L_0x1306840/d; +v0x110f160_0 .net "a", 0 0, L_0x13101b0; alias, 1 drivers +v0x110f220_0 .net "b", 0 0, L_0x1305e50; alias, 1 drivers +v0x110f2e0_0 .net "carryout", 0 0, L_0x1306840; alias, 1 drivers +v0x110f380_0 .net "sum", 0 0, L_0x1306780; alias, 1 drivers +S_0x110f4b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x110ecb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13069a0/d .functor XOR 1, L_0x1306780, L_0x1305c00, C4<0>, C4<0>; +L_0x13069a0 .delay 1 (30000,30000,30000) L_0x13069a0/d; +L_0x110ff10/d .functor AND 1, L_0x1306780, L_0x1305c00, C4<1>, C4<1>; +L_0x110ff10 .delay 1 (30000,30000,30000) L_0x110ff10/d; +v0x110f710_0 .net "a", 0 0, L_0x1306780; alias, 1 drivers +v0x110f7e0_0 .net "b", 0 0, L_0x1305c00; alias, 1 drivers +v0x110f880_0 .net "carryout", 0 0, L_0x110ff10; alias, 1 drivers +v0x110f950_0 .net "sum", 0 0, L_0x13069a0; alias, 1 drivers +S_0x1112170 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1101710; + .timescale -9 -12; +L_0x2ac432886618 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886660 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1306300/d .functor OR 1, L_0x2ac432886618, L_0x2ac432886660, C4<0>, C4<0>; +L_0x1306300 .delay 1 (30000,30000,30000) L_0x1306300/d; +v0x1112360_0 .net/2u *"_s0", 0 0, L_0x2ac432886618; 1 drivers +v0x1112440_0 .net/2u *"_s2", 0 0, L_0x2ac432886660; 1 drivers +S_0x1112520 .scope generate, "alu_slices[14]" "alu_slices[14]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1112730 .param/l "i" 0 3 39, +C4<01110>; +S_0x11127f0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1112520; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1310510/d .functor NOT 1, L_0x131a9d0, C4<0>, C4<0>, C4<0>; +L_0x1310510 .delay 1 (10000,10000,10000) L_0x1310510/d; +L_0x1310670/d .functor NOT 1, L_0x12c6260, C4<0>, C4<0>, C4<0>; +L_0x1310670 .delay 1 (10000,10000,10000) L_0x1310670/d; +L_0x1311620/d .functor XOR 1, L_0x131a9d0, L_0x12c6260, C4<0>, C4<0>; +L_0x1311620 .delay 1 (30000,30000,30000) L_0x1311620/d; +L_0x2ac4328866a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328866f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13116e0/d .functor OR 1, L_0x2ac4328866a8, L_0x2ac4328866f0, C4<0>, C4<0>; +L_0x13116e0 .delay 1 (30000,30000,30000) L_0x13116e0/d; +L_0x2ac432886738 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886780 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1311e80/d .functor OR 1, L_0x2ac432886738, L_0x2ac432886780, C4<0>, C4<0>; +L_0x1311e80 .delay 1 (30000,30000,30000) L_0x1311e80/d; +L_0x1312080/d .functor AND 1, L_0x131a9d0, L_0x12c6260, C4<1>, C4<1>; +L_0x1312080 .delay 1 (30000,30000,30000) L_0x1312080/d; +L_0x2ac4328867c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886810 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1312140/d .functor OR 1, L_0x2ac4328867c8, L_0x2ac432886810, C4<0>, C4<0>; +L_0x1312140 .delay 1 (30000,30000,30000) L_0x1312140/d; +L_0x1312340/d .functor NAND 1, L_0x131a9d0, L_0x12c6260, C4<1>, C4<1>; +L_0x1312340 .delay 1 (20000,20000,20000) L_0x1312340/d; +L_0x2ac432886858 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328868a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1312450/d .functor OR 1, L_0x2ac432886858, L_0x2ac4328868a0, C4<0>, C4<0>; +L_0x1312450 .delay 1 (30000,30000,30000) L_0x1312450/d; +L_0x1312600/d .functor NOR 1, L_0x131a9d0, L_0x12c6260, C4<0>, C4<0>; +L_0x1312600 .delay 1 (20000,20000,20000) L_0x1312600/d; +L_0x2ac4328868e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886930 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13128d0/d .functor OR 1, L_0x2ac4328868e8, L_0x2ac432886930, C4<0>, C4<0>; +L_0x13128d0 .delay 1 (30000,30000,30000) L_0x13128d0/d; +L_0x1312cd0/d .functor OR 1, L_0x131a9d0, L_0x12c6260, C4<0>, C4<0>; +L_0x1312cd0 .delay 1 (30000,30000,30000) L_0x1312cd0/d; +L_0x2ac432886978 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328869c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1313170/d .functor OR 1, L_0x2ac432886978, L_0x2ac4328869c0, C4<0>, C4<0>; +L_0x1313170 .delay 1 (30000,30000,30000) L_0x1313170/d; +L_0x131a8d0/d .functor NOT 1, L_0x1316b30, C4<0>, C4<0>, C4<0>; +L_0x131a8d0 .delay 1 (10000,10000,10000) L_0x131a8d0/d; +v0x1120f20_0 .net "A", 0 0, L_0x131a9d0; 1 drivers +v0x1120fe0_0 .net "A_", 0 0, L_0x1310510; 1 drivers +v0x11210a0_0 .net "B", 0 0, L_0x12c6260; 1 drivers +v0x1121170_0 .net "B_", 0 0, L_0x1310670; 1 drivers +v0x1121210_0 .net *"_s11", 0 0, L_0x13116e0; 1 drivers +v0x1121300_0 .net/2s *"_s13", 0 0, L_0x2ac4328866a8; 1 drivers +v0x11213c0_0 .net/2s *"_s15", 0 0, L_0x2ac4328866f0; 1 drivers +v0x11214a0_0 .net *"_s19", 0 0, L_0x1311e80; 1 drivers +v0x1121580_0 .net/2s *"_s21", 0 0, L_0x2ac432886738; 1 drivers +v0x11216f0_0 .net/2s *"_s23", 0 0, L_0x2ac432886780; 1 drivers +v0x11217d0_0 .net *"_s25", 0 0, L_0x1312080; 1 drivers +v0x11218b0_0 .net *"_s28", 0 0, L_0x1312140; 1 drivers +v0x1121990_0 .net/2s *"_s30", 0 0, L_0x2ac4328867c8; 1 drivers +v0x1121a70_0 .net/2s *"_s32", 0 0, L_0x2ac432886810; 1 drivers +v0x1121b50_0 .net *"_s34", 0 0, L_0x1312340; 1 drivers +v0x1121c30_0 .net *"_s37", 0 0, L_0x1312450; 1 drivers +v0x1121d10_0 .net/2s *"_s39", 0 0, L_0x2ac432886858; 1 drivers +v0x1121ec0_0 .net/2s *"_s41", 0 0, L_0x2ac4328868a0; 1 drivers +v0x1121f60_0 .net *"_s43", 0 0, L_0x1312600; 1 drivers +v0x1122040_0 .net *"_s46", 0 0, L_0x13128d0; 1 drivers +v0x1122120_0 .net/2s *"_s48", 0 0, L_0x2ac4328868e8; 1 drivers +v0x1122200_0 .net/2s *"_s50", 0 0, L_0x2ac432886930; 1 drivers +v0x11222e0_0 .net *"_s52", 0 0, L_0x1312cd0; 1 drivers +v0x11223c0_0 .net *"_s56", 0 0, L_0x1313170; 1 drivers +v0x11224a0_0 .net/2s *"_s59", 0 0, L_0x2ac432886978; 1 drivers +v0x1122580_0 .net/2s *"_s61", 0 0, L_0x2ac4328869c0; 1 drivers +v0x1122660_0 .net *"_s8", 0 0, L_0x1311620; 1 drivers +v0x1122740_0 .net "carryin", 0 0, L_0x12c6410; 1 drivers +v0x11227e0_0 .net "carryout", 0 0, L_0x131a570; 1 drivers +v0x1122880_0 .net "carryouts", 7 0, L_0x1312de0; 1 drivers +v0x1122990_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1122a50_0 .net "result", 0 0, L_0x1316b30; 1 drivers +v0x1122b40_0 .net "results", 7 0, L_0x1312aa0; 1 drivers +v0x1121e20_0 .net "zero", 0 0, L_0x131a8d0; 1 drivers +LS_0x1312aa0_0_0 .concat8 [ 1 1 1 1], L_0x1310b40, L_0x1311170, L_0x1311620, L_0x1311e80; +LS_0x1312aa0_0_4 .concat8 [ 1 1 1 1], L_0x1312080, L_0x1312340, L_0x1312600, L_0x1312cd0; +L_0x1312aa0 .concat8 [ 4 4 0 0], LS_0x1312aa0_0_0, LS_0x1312aa0_0_4; +LS_0x1312de0_0_0 .concat8 [ 1 1 1 1], L_0x1310df0, L_0x13114c0, L_0x13116e0, L_0x1311cd0; +LS_0x1312de0_0_4 .concat8 [ 1 1 1 1], L_0x1312140, L_0x1312450, L_0x13128d0, L_0x1313170; +L_0x1312de0 .concat8 [ 4 4 0 0], LS_0x1312de0_0_0, LS_0x1312de0_0_4; +S_0x1112a70 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11127f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1310df0/d .functor OR 1, L_0x13108d0, L_0x1310c90, C4<0>, C4<0>; +L_0x1310df0 .delay 1 (30000,30000,30000) L_0x1310df0/d; +v0x11138a0_0 .net "a", 0 0, L_0x131a9d0; alias, 1 drivers +v0x1113960_0 .net "b", 0 0, L_0x12c6260; alias, 1 drivers +v0x1113a30_0 .net "c1", 0 0, L_0x13108d0; 1 drivers +v0x1113b30_0 .net "c2", 0 0, L_0x1310c90; 1 drivers +v0x1113c00_0 .net "carryin", 0 0, L_0x12c6410; alias, 1 drivers +v0x1113cf0_0 .net "carryout", 0 0, L_0x1310df0; 1 drivers +v0x1113d90_0 .net "s1", 0 0, L_0x1310860; 1 drivers +v0x1113e80_0 .net "sum", 0 0, L_0x1310b40; 1 drivers +S_0x1112ce0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1112a70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1310860/d .functor XOR 1, L_0x131a9d0, L_0x12c6260, C4<0>, C4<0>; +L_0x1310860 .delay 1 (30000,30000,30000) L_0x1310860/d; +L_0x13108d0/d .functor AND 1, L_0x131a9d0, L_0x12c6260, C4<1>, C4<1>; +L_0x13108d0 .delay 1 (30000,30000,30000) L_0x13108d0/d; +v0x1112f40_0 .net "a", 0 0, L_0x131a9d0; alias, 1 drivers +v0x1113020_0 .net "b", 0 0, L_0x12c6260; alias, 1 drivers +v0x11130e0_0 .net "carryout", 0 0, L_0x13108d0; alias, 1 drivers +v0x1113180_0 .net "sum", 0 0, L_0x1310860; alias, 1 drivers +S_0x11132c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1112a70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1310b40/d .functor XOR 1, L_0x1310860, L_0x12c6410, C4<0>, C4<0>; +L_0x1310b40 .delay 1 (30000,30000,30000) L_0x1310b40/d; +L_0x1310c90/d .functor AND 1, L_0x1310860, L_0x12c6410, C4<1>, C4<1>; +L_0x1310c90 .delay 1 (30000,30000,30000) L_0x1310c90/d; +v0x1113520_0 .net "a", 0 0, L_0x1310860; alias, 1 drivers +v0x11135c0_0 .net "b", 0 0, L_0x12c6410; alias, 1 drivers +v0x1113660_0 .net "carryout", 0 0, L_0x1310c90; alias, 1 drivers +v0x1113730_0 .net "sum", 0 0, L_0x1310b40; alias, 1 drivers +S_0x1113f50 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11127f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1119340_0 .net "ands", 7 0, L_0x1318570; 1 drivers +v0x1119450_0 .net "in", 7 0, L_0x1312de0; alias, 1 drivers +v0x1119510_0 .net "out", 0 0, L_0x131a570; alias, 1 drivers +v0x11195e0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1114170 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1113f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11168a0_0 .net "A", 7 0, L_0x1312de0; alias, 1 drivers +v0x11169a0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1116a60_0 .net *"_s0", 0 0, L_0x1316e90; 1 drivers +v0x1116b20_0 .net *"_s12", 0 0, L_0x1317800; 1 drivers +v0x1116c00_0 .net *"_s16", 0 0, L_0x1317b60; 1 drivers +v0x1116d30_0 .net *"_s20", 0 0, L_0x1317f30; 1 drivers +v0x1116e10_0 .net *"_s24", 0 0, L_0x1318260; 1 drivers +v0x1116ef0_0 .net *"_s28", 0 0, L_0x13181f0; 1 drivers +v0x1116fd0_0 .net *"_s4", 0 0, L_0x13171e0; 1 drivers +v0x1117140_0 .net *"_s8", 0 0, L_0x13174f0; 1 drivers +v0x1117220_0 .net "out", 7 0, L_0x1318570; alias, 1 drivers +L_0x1316f50 .part L_0x1312de0, 0, 1; +L_0x1317140 .part v0x127a150_0, 0, 1; +L_0x13172a0 .part L_0x1312de0, 1, 1; +L_0x1317400 .part v0x127a150_0, 1, 1; +L_0x13175b0 .part L_0x1312de0, 2, 1; +L_0x1317710 .part v0x127a150_0, 2, 1; +L_0x13178c0 .part L_0x1312de0, 3, 1; +L_0x1317a20 .part v0x127a150_0, 3, 1; +L_0x1317c20 .part L_0x1312de0, 4, 1; +L_0x1317e90 .part v0x127a150_0, 4, 1; +L_0x1317fa0 .part L_0x1312de0, 5, 1; +L_0x1318100 .part v0x127a150_0, 5, 1; +L_0x1318320 .part L_0x1312de0, 6, 1; +L_0x1318480 .part v0x127a150_0, 6, 1; +LS_0x1318570_0_0 .concat8 [ 1 1 1 1], L_0x1316e90, L_0x13171e0, L_0x13174f0, L_0x1317800; +LS_0x1318570_0_4 .concat8 [ 1 1 1 1], L_0x1317b60, L_0x1317f30, L_0x1318260, L_0x13181f0; +L_0x1318570 .concat8 [ 4 4 0 0], LS_0x1318570_0_0, LS_0x1318570_0_4; +L_0x1318930 .part L_0x1312de0, 7, 1; +L_0x1318b20 .part v0x127a150_0, 7, 1; +S_0x11143d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x11145e0 .param/l "i" 0 4 54, +C4<00>; +L_0x1316e90/d .functor AND 1, L_0x1316f50, L_0x1317140, C4<1>, C4<1>; +L_0x1316e90 .delay 1 (30000,30000,30000) L_0x1316e90/d; +v0x11146c0_0 .net *"_s0", 0 0, L_0x1316f50; 1 drivers +v0x11147a0_0 .net *"_s1", 0 0, L_0x1317140; 1 drivers +S_0x1114880 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1114a90 .param/l "i" 0 4 54, +C4<01>; +L_0x13171e0/d .functor AND 1, L_0x13172a0, L_0x1317400, C4<1>, C4<1>; +L_0x13171e0 .delay 1 (30000,30000,30000) L_0x13171e0/d; +v0x1114b50_0 .net *"_s0", 0 0, L_0x13172a0; 1 drivers +v0x1114c30_0 .net *"_s1", 0 0, L_0x1317400; 1 drivers +S_0x1114d10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1114f20 .param/l "i" 0 4 54, +C4<010>; +L_0x13174f0/d .functor AND 1, L_0x13175b0, L_0x1317710, C4<1>, C4<1>; +L_0x13174f0 .delay 1 (30000,30000,30000) L_0x13174f0/d; +v0x1114fc0_0 .net *"_s0", 0 0, L_0x13175b0; 1 drivers +v0x11150a0_0 .net *"_s1", 0 0, L_0x1317710; 1 drivers +S_0x1115180 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1115390 .param/l "i" 0 4 54, +C4<011>; +L_0x1317800/d .functor AND 1, L_0x13178c0, L_0x1317a20, C4<1>, C4<1>; +L_0x1317800 .delay 1 (30000,30000,30000) L_0x1317800/d; +v0x1115450_0 .net *"_s0", 0 0, L_0x13178c0; 1 drivers +v0x1115530_0 .net *"_s1", 0 0, L_0x1317a20; 1 drivers +S_0x1115610 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1115870 .param/l "i" 0 4 54, +C4<0100>; +L_0x1317b60/d .functor AND 1, L_0x1317c20, L_0x1317e90, C4<1>, C4<1>; +L_0x1317b60 .delay 1 (30000,30000,30000) L_0x1317b60/d; +v0x1115930_0 .net *"_s0", 0 0, L_0x1317c20; 1 drivers +v0x1115a10_0 .net *"_s1", 0 0, L_0x1317e90; 1 drivers +S_0x1115af0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1115d00 .param/l "i" 0 4 54, +C4<0101>; +L_0x1317f30/d .functor AND 1, L_0x1317fa0, L_0x1318100, C4<1>, C4<1>; +L_0x1317f30 .delay 1 (30000,30000,30000) L_0x1317f30/d; +v0x1115dc0_0 .net *"_s0", 0 0, L_0x1317fa0; 1 drivers +v0x1115ea0_0 .net *"_s1", 0 0, L_0x1318100; 1 drivers +S_0x1115f80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1116190 .param/l "i" 0 4 54, +C4<0110>; +L_0x1318260/d .functor AND 1, L_0x1318320, L_0x1318480, C4<1>, C4<1>; +L_0x1318260 .delay 1 (30000,30000,30000) L_0x1318260/d; +v0x1116250_0 .net *"_s0", 0 0, L_0x1318320; 1 drivers +v0x1116330_0 .net *"_s1", 0 0, L_0x1318480; 1 drivers +S_0x1116410 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1114170; + .timescale -9 -12; +P_0x1116620 .param/l "i" 0 4 54, +C4<0111>; +L_0x13181f0/d .functor AND 1, L_0x1318930, L_0x1318b20, C4<1>, C4<1>; +L_0x13181f0 .delay 1 (30000,30000,30000) L_0x13181f0/d; +v0x11166e0_0 .net *"_s0", 0 0, L_0x1318930; 1 drivers +v0x11167c0_0 .net *"_s1", 0 0, L_0x1318b20; 1 drivers +S_0x1117380 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1113f50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x131a570/d .functor OR 1, L_0x131a630, L_0x131a7e0, C4<0>, C4<0>; +L_0x131a570 .delay 1 (30000,30000,30000) L_0x131a570/d; +v0x1118ed0_0 .net *"_s10", 0 0, L_0x131a630; 1 drivers +v0x1118fb0_0 .net *"_s12", 0 0, L_0x131a7e0; 1 drivers +v0x1119090_0 .net "in", 7 0, L_0x1318570; alias, 1 drivers +v0x1119160_0 .net "ors", 1 0, L_0x131a390; 1 drivers +v0x1119220_0 .net "out", 0 0, L_0x131a570; alias, 1 drivers +L_0x1319760 .part L_0x1318570, 0, 4; +L_0x131a390 .concat8 [ 1 1 0 0], L_0x1319450, L_0x131a080; +L_0x131a4d0 .part L_0x1318570, 4, 4; +L_0x131a630 .part L_0x131a390, 0, 1; +L_0x131a7e0 .part L_0x131a390, 1, 1; +S_0x1117540 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1117380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1318c10/d .functor OR 1, L_0x1318cd0, L_0x1318e30, C4<0>, C4<0>; +L_0x1318c10 .delay 1 (30000,30000,30000) L_0x1318c10/d; +L_0x1319060/d .functor OR 1, L_0x1319170, L_0x13192d0, C4<0>, C4<0>; +L_0x1319060 .delay 1 (30000,30000,30000) L_0x1319060/d; +L_0x1319450/d .functor OR 1, L_0x13194c0, L_0x1319670, C4<0>, C4<0>; +L_0x1319450 .delay 1 (30000,30000,30000) L_0x1319450/d; +v0x1117790_0 .net *"_s0", 0 0, L_0x1318c10; 1 drivers +v0x1117890_0 .net *"_s10", 0 0, L_0x1319170; 1 drivers +v0x1117970_0 .net *"_s12", 0 0, L_0x13192d0; 1 drivers +v0x1117a30_0 .net *"_s14", 0 0, L_0x13194c0; 1 drivers +v0x1117b10_0 .net *"_s16", 0 0, L_0x1319670; 1 drivers +v0x1117c40_0 .net *"_s3", 0 0, L_0x1318cd0; 1 drivers +v0x1117d20_0 .net *"_s5", 0 0, L_0x1318e30; 1 drivers +v0x1117e00_0 .net *"_s6", 0 0, L_0x1319060; 1 drivers +v0x1117ee0_0 .net "in", 3 0, L_0x1319760; 1 drivers +v0x1118050_0 .net "ors", 1 0, L_0x1318f70; 1 drivers +v0x1118130_0 .net "out", 0 0, L_0x1319450; 1 drivers +L_0x1318cd0 .part L_0x1319760, 0, 1; +L_0x1318e30 .part L_0x1319760, 1, 1; +L_0x1318f70 .concat8 [ 1 1 0 0], L_0x1318c10, L_0x1319060; +L_0x1319170 .part L_0x1319760, 2, 1; +L_0x13192d0 .part L_0x1319760, 3, 1; +L_0x13194c0 .part L_0x1318f70, 0, 1; +L_0x1319670 .part L_0x1318f70, 1, 1; +S_0x1118250 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1117380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1319890/d .functor OR 1, L_0x1319900, L_0x1319a60, C4<0>, C4<0>; +L_0x1319890 .delay 1 (30000,30000,30000) L_0x1319890/d; +L_0x1319c90/d .functor OR 1, L_0x1319da0, L_0x1319f00, C4<0>, C4<0>; +L_0x1319c90 .delay 1 (30000,30000,30000) L_0x1319c90/d; +L_0x131a080/d .functor OR 1, L_0x131a0f0, L_0x131a2a0, C4<0>, C4<0>; +L_0x131a080 .delay 1 (30000,30000,30000) L_0x131a080/d; +v0x1118410_0 .net *"_s0", 0 0, L_0x1319890; 1 drivers +v0x1118510_0 .net *"_s10", 0 0, L_0x1319da0; 1 drivers +v0x11185f0_0 .net *"_s12", 0 0, L_0x1319f00; 1 drivers +v0x11186b0_0 .net *"_s14", 0 0, L_0x131a0f0; 1 drivers +v0x1118790_0 .net *"_s16", 0 0, L_0x131a2a0; 1 drivers +v0x11188c0_0 .net *"_s3", 0 0, L_0x1319900; 1 drivers +v0x11189a0_0 .net *"_s5", 0 0, L_0x1319a60; 1 drivers +v0x1118a80_0 .net *"_s6", 0 0, L_0x1319c90; 1 drivers +v0x1118b60_0 .net "in", 3 0, L_0x131a4d0; 1 drivers +v0x1118cd0_0 .net "ors", 1 0, L_0x1319ba0; 1 drivers +v0x1118db0_0 .net "out", 0 0, L_0x131a080; 1 drivers +L_0x1319900 .part L_0x131a4d0, 0, 1; +L_0x1319a60 .part L_0x131a4d0, 1, 1; +L_0x1319ba0 .concat8 [ 1 1 0 0], L_0x1319890, L_0x1319c90; +L_0x1319da0 .part L_0x131a4d0, 2, 1; +L_0x1319f00 .part L_0x131a4d0, 3, 1; +L_0x131a0f0 .part L_0x1319ba0, 0, 1; +L_0x131a2a0 .part L_0x1319ba0, 1, 1; +S_0x11196c0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11127f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x111eaf0_0 .net "ands", 7 0, L_0x1314b30; 1 drivers +v0x111ec00_0 .net "in", 7 0, L_0x1312aa0; alias, 1 drivers +v0x111ecc0_0 .net "out", 0 0, L_0x1316b30; alias, 1 drivers +v0x111ed90_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1119910 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11196c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x111c050_0 .net "A", 7 0, L_0x1312aa0; alias, 1 drivers +v0x111c150_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x111c210_0 .net *"_s0", 0 0, L_0x1313320; 1 drivers +v0x111c2d0_0 .net *"_s12", 0 0, L_0x1313ce0; 1 drivers +v0x111c3b0_0 .net *"_s16", 0 0, L_0x1314040; 1 drivers +v0x111c4e0_0 .net *"_s20", 0 0, L_0x1314470; 1 drivers +v0x111c5c0_0 .net *"_s24", 0 0, L_0x13147a0; 1 drivers +v0x111c6a0_0 .net *"_s28", 0 0, L_0x1314730; 1 drivers +v0x111c780_0 .net *"_s4", 0 0, L_0x13136c0; 1 drivers +v0x111c8f0_0 .net *"_s8", 0 0, L_0x13139d0; 1 drivers +v0x111c9d0_0 .net "out", 7 0, L_0x1314b30; alias, 1 drivers +L_0x1313430 .part L_0x1312aa0, 0, 1; +L_0x1313620 .part v0x127a150_0, 0, 1; +L_0x1313780 .part L_0x1312aa0, 1, 1; +L_0x13138e0 .part v0x127a150_0, 1, 1; +L_0x1313a90 .part L_0x1312aa0, 2, 1; +L_0x1313bf0 .part v0x127a150_0, 2, 1; +L_0x1313da0 .part L_0x1312aa0, 3, 1; +L_0x1313f00 .part v0x127a150_0, 3, 1; +L_0x1314100 .part L_0x1312aa0, 4, 1; +L_0x1314370 .part v0x127a150_0, 4, 1; +L_0x13144e0 .part L_0x1312aa0, 5, 1; +L_0x1314640 .part v0x127a150_0, 5, 1; +L_0x1314860 .part L_0x1312aa0, 6, 1; +L_0x13149c0 .part v0x127a150_0, 6, 1; +LS_0x1314b30_0_0 .concat8 [ 1 1 1 1], L_0x1313320, L_0x13136c0, L_0x13139d0, L_0x1313ce0; +LS_0x1314b30_0_4 .concat8 [ 1 1 1 1], L_0x1314040, L_0x1314470, L_0x13147a0, L_0x1314730; +L_0x1314b30 .concat8 [ 4 4 0 0], LS_0x1314b30_0_0, LS_0x1314b30_0_4; +L_0x1314ef0 .part L_0x1312aa0, 7, 1; +L_0x13150e0 .part v0x127a150_0, 7, 1; +S_0x1119b50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x1119d60 .param/l "i" 0 4 54, +C4<00>; +L_0x1313320/d .functor AND 1, L_0x1313430, L_0x1313620, C4<1>, C4<1>; +L_0x1313320 .delay 1 (30000,30000,30000) L_0x1313320/d; +v0x1119e40_0 .net *"_s0", 0 0, L_0x1313430; 1 drivers +v0x1119f20_0 .net *"_s1", 0 0, L_0x1313620; 1 drivers +S_0x111a000 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111a210 .param/l "i" 0 4 54, +C4<01>; +L_0x13136c0/d .functor AND 1, L_0x1313780, L_0x13138e0, C4<1>, C4<1>; +L_0x13136c0 .delay 1 (30000,30000,30000) L_0x13136c0/d; +v0x111a2d0_0 .net *"_s0", 0 0, L_0x1313780; 1 drivers +v0x111a3b0_0 .net *"_s1", 0 0, L_0x13138e0; 1 drivers +S_0x111a490 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111a6d0 .param/l "i" 0 4 54, +C4<010>; +L_0x13139d0/d .functor AND 1, L_0x1313a90, L_0x1313bf0, C4<1>, C4<1>; +L_0x13139d0 .delay 1 (30000,30000,30000) L_0x13139d0/d; +v0x111a770_0 .net *"_s0", 0 0, L_0x1313a90; 1 drivers +v0x111a850_0 .net *"_s1", 0 0, L_0x1313bf0; 1 drivers +S_0x111a930 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111ab40 .param/l "i" 0 4 54, +C4<011>; +L_0x1313ce0/d .functor AND 1, L_0x1313da0, L_0x1313f00, C4<1>, C4<1>; +L_0x1313ce0 .delay 1 (30000,30000,30000) L_0x1313ce0/d; +v0x111ac00_0 .net *"_s0", 0 0, L_0x1313da0; 1 drivers +v0x111ace0_0 .net *"_s1", 0 0, L_0x1313f00; 1 drivers +S_0x111adc0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111b020 .param/l "i" 0 4 54, +C4<0100>; +L_0x1314040/d .functor AND 1, L_0x1314100, L_0x1314370, C4<1>, C4<1>; +L_0x1314040 .delay 1 (30000,30000,30000) L_0x1314040/d; +v0x111b0e0_0 .net *"_s0", 0 0, L_0x1314100; 1 drivers +v0x111b1c0_0 .net *"_s1", 0 0, L_0x1314370; 1 drivers +S_0x111b2a0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111b4b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1314470/d .functor AND 1, L_0x13144e0, L_0x1314640, C4<1>, C4<1>; +L_0x1314470 .delay 1 (30000,30000,30000) L_0x1314470/d; +v0x111b570_0 .net *"_s0", 0 0, L_0x13144e0; 1 drivers +v0x111b650_0 .net *"_s1", 0 0, L_0x1314640; 1 drivers +S_0x111b730 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111b940 .param/l "i" 0 4 54, +C4<0110>; +L_0x13147a0/d .functor AND 1, L_0x1314860, L_0x13149c0, C4<1>, C4<1>; +L_0x13147a0 .delay 1 (30000,30000,30000) L_0x13147a0/d; +v0x111ba00_0 .net *"_s0", 0 0, L_0x1314860; 1 drivers +v0x111bae0_0 .net *"_s1", 0 0, L_0x13149c0; 1 drivers +S_0x111bbc0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1119910; + .timescale -9 -12; +P_0x111bdd0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1314730/d .functor AND 1, L_0x1314ef0, L_0x13150e0, C4<1>, C4<1>; +L_0x1314730 .delay 1 (30000,30000,30000) L_0x1314730/d; +v0x111be90_0 .net *"_s0", 0 0, L_0x1314ef0; 1 drivers +v0x111bf70_0 .net *"_s1", 0 0, L_0x13150e0; 1 drivers +S_0x111cb30 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11196c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1316b30/d .functor OR 1, L_0x1316bf0, L_0x1316da0, C4<0>, C4<0>; +L_0x1316b30 .delay 1 (30000,30000,30000) L_0x1316b30/d; +v0x111e680_0 .net *"_s10", 0 0, L_0x1316bf0; 1 drivers +v0x111e760_0 .net *"_s12", 0 0, L_0x1316da0; 1 drivers +v0x111e840_0 .net "in", 7 0, L_0x1314b30; alias, 1 drivers +v0x111e910_0 .net "ors", 1 0, L_0x1316950; 1 drivers +v0x111e9d0_0 .net "out", 0 0, L_0x1316b30; alias, 1 drivers +L_0x1315d20 .part L_0x1314b30, 0, 4; +L_0x1316950 .concat8 [ 1 1 0 0], L_0x1315a10, L_0x1316640; +L_0x1316a90 .part L_0x1314b30, 4, 4; +L_0x1316bf0 .part L_0x1316950, 0, 1; +L_0x1316da0 .part L_0x1316950, 1, 1; +S_0x111ccf0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x111cb30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13151d0/d .functor OR 1, L_0x1315290, L_0x13153f0, C4<0>, C4<0>; +L_0x13151d0 .delay 1 (30000,30000,30000) L_0x13151d0/d; +L_0x1315620/d .functor OR 1, L_0x1315730, L_0x1315890, C4<0>, C4<0>; +L_0x1315620 .delay 1 (30000,30000,30000) L_0x1315620/d; +L_0x1315a10/d .functor OR 1, L_0x1315a80, L_0x1315c30, C4<0>, C4<0>; +L_0x1315a10 .delay 1 (30000,30000,30000) L_0x1315a10/d; +v0x111cf40_0 .net *"_s0", 0 0, L_0x13151d0; 1 drivers +v0x111d040_0 .net *"_s10", 0 0, L_0x1315730; 1 drivers +v0x111d120_0 .net *"_s12", 0 0, L_0x1315890; 1 drivers +v0x111d1e0_0 .net *"_s14", 0 0, L_0x1315a80; 1 drivers +v0x111d2c0_0 .net *"_s16", 0 0, L_0x1315c30; 1 drivers +v0x111d3f0_0 .net *"_s3", 0 0, L_0x1315290; 1 drivers +v0x111d4d0_0 .net *"_s5", 0 0, L_0x13153f0; 1 drivers +v0x111d5b0_0 .net *"_s6", 0 0, L_0x1315620; 1 drivers +v0x111d690_0 .net "in", 3 0, L_0x1315d20; 1 drivers +v0x111d800_0 .net "ors", 1 0, L_0x1315530; 1 drivers +v0x111d8e0_0 .net "out", 0 0, L_0x1315a10; 1 drivers +L_0x1315290 .part L_0x1315d20, 0, 1; +L_0x13153f0 .part L_0x1315d20, 1, 1; +L_0x1315530 .concat8 [ 1 1 0 0], L_0x13151d0, L_0x1315620; +L_0x1315730 .part L_0x1315d20, 2, 1; +L_0x1315890 .part L_0x1315d20, 3, 1; +L_0x1315a80 .part L_0x1315530, 0, 1; +L_0x1315c30 .part L_0x1315530, 1, 1; +S_0x111da00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x111cb30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1315e50/d .functor OR 1, L_0x1315ec0, L_0x1316020, C4<0>, C4<0>; +L_0x1315e50 .delay 1 (30000,30000,30000) L_0x1315e50/d; +L_0x1316250/d .functor OR 1, L_0x1316360, L_0x13164c0, C4<0>, C4<0>; +L_0x1316250 .delay 1 (30000,30000,30000) L_0x1316250/d; +L_0x1316640/d .functor OR 1, L_0x13166b0, L_0x1316860, C4<0>, C4<0>; +L_0x1316640 .delay 1 (30000,30000,30000) L_0x1316640/d; +v0x111dbc0_0 .net *"_s0", 0 0, L_0x1315e50; 1 drivers +v0x111dcc0_0 .net *"_s10", 0 0, L_0x1316360; 1 drivers +v0x111dda0_0 .net *"_s12", 0 0, L_0x13164c0; 1 drivers +v0x111de60_0 .net *"_s14", 0 0, L_0x13166b0; 1 drivers +v0x111df40_0 .net *"_s16", 0 0, L_0x1316860; 1 drivers +v0x111e070_0 .net *"_s3", 0 0, L_0x1315ec0; 1 drivers +v0x111e150_0 .net *"_s5", 0 0, L_0x1316020; 1 drivers +v0x111e230_0 .net *"_s6", 0 0, L_0x1316250; 1 drivers +v0x111e310_0 .net "in", 3 0, L_0x1316a90; 1 drivers +v0x111e480_0 .net "ors", 1 0, L_0x1316160; 1 drivers +v0x111e560_0 .net "out", 0 0, L_0x1316640; 1 drivers +L_0x1315ec0 .part L_0x1316a90, 0, 1; +L_0x1316020 .part L_0x1316a90, 1, 1; +L_0x1316160 .concat8 [ 1 1 0 0], L_0x1315e50, L_0x1316250; +L_0x1316360 .part L_0x1316a90, 2, 1; +L_0x13164c0 .part L_0x1316a90, 3, 1; +L_0x13166b0 .part L_0x1316160, 0, 1; +L_0x1316860 .part L_0x1316160, 1, 1; +S_0x111ee70 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11127f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x13118e0/d .functor XNOR 1, L_0x131a9d0, L_0x12c6260, C4<0>, C4<0>; +L_0x13118e0 .delay 1 (20000,20000,20000) L_0x13118e0/d; +L_0x1311a60/d .functor AND 1, L_0x131a9d0, L_0x1310670, C4<1>, C4<1>; +L_0x1311a60 .delay 1 (30000,30000,30000) L_0x1311a60/d; +L_0x1311bc0/d .functor AND 1, L_0x13118e0, L_0x12c6410, C4<1>, C4<1>; +L_0x1311bc0 .delay 1 (30000,30000,30000) L_0x1311bc0/d; +L_0x1311cd0/d .functor OR 1, L_0x1311bc0, L_0x1311a60, C4<0>, C4<0>; +L_0x1311cd0 .delay 1 (30000,30000,30000) L_0x1311cd0/d; +v0x111f120_0 .net "a", 0 0, L_0x131a9d0; alias, 1 drivers +v0x111f210_0 .net "a_", 0 0, L_0x1310510; alias, 1 drivers +v0x111f2d0_0 .net "b", 0 0, L_0x12c6260; alias, 1 drivers +v0x111f3c0_0 .net "b_", 0 0, L_0x1310670; alias, 1 drivers +v0x111f460_0 .net "carryin", 0 0, L_0x12c6410; alias, 1 drivers +v0x111f5a0_0 .net "eq", 0 0, L_0x13118e0; 1 drivers +v0x111f660_0 .net "lt", 0 0, L_0x1311a60; 1 drivers +v0x111f720_0 .net "out", 0 0, L_0x1311cd0; 1 drivers +v0x111f7e0_0 .net "w0", 0 0, L_0x1311bc0; 1 drivers +S_0x111fa30 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11127f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13114c0/d .functor OR 1, L_0x1311010, L_0x1120c90, C4<0>, C4<0>; +L_0x13114c0 .delay 1 (30000,30000,30000) L_0x13114c0/d; +v0x1120820_0 .net "a", 0 0, L_0x131a9d0; alias, 1 drivers +v0x1120970_0 .net "b", 0 0, L_0x1310670; alias, 1 drivers +v0x1120a30_0 .net "c1", 0 0, L_0x1311010; 1 drivers +v0x1120ad0_0 .net "c2", 0 0, L_0x1120c90; 1 drivers +v0x1120ba0_0 .net "carryin", 0 0, L_0x12c6410; alias, 1 drivers +v0x1120d20_0 .net "carryout", 0 0, L_0x13114c0; 1 drivers +v0x1120dc0_0 .net "s1", 0 0, L_0x1310f50; 1 drivers +v0x1120e60_0 .net "sum", 0 0, L_0x1311170; 1 drivers +S_0x111fc80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x111fa30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1310f50/d .functor XOR 1, L_0x131a9d0, L_0x1310670, C4<0>, C4<0>; +L_0x1310f50 .delay 1 (30000,30000,30000) L_0x1310f50/d; +L_0x1311010/d .functor AND 1, L_0x131a9d0, L_0x1310670, C4<1>, C4<1>; +L_0x1311010 .delay 1 (30000,30000,30000) L_0x1311010/d; +v0x111fee0_0 .net "a", 0 0, L_0x131a9d0; alias, 1 drivers +v0x111ffa0_0 .net "b", 0 0, L_0x1310670; alias, 1 drivers +v0x1120060_0 .net "carryout", 0 0, L_0x1311010; alias, 1 drivers +v0x1120100_0 .net "sum", 0 0, L_0x1310f50; alias, 1 drivers +S_0x1120230 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x111fa30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1311170/d .functor XOR 1, L_0x1310f50, L_0x12c6410, C4<0>, C4<0>; +L_0x1311170 .delay 1 (30000,30000,30000) L_0x1311170/d; +L_0x1120c90/d .functor AND 1, L_0x1310f50, L_0x12c6410, C4<1>, C4<1>; +L_0x1120c90 .delay 1 (30000,30000,30000) L_0x1120c90/d; +v0x1120490_0 .net "a", 0 0, L_0x1310f50; alias, 1 drivers +v0x1120560_0 .net "b", 0 0, L_0x12c6410; alias, 1 drivers +v0x1120600_0 .net "carryout", 0 0, L_0x1120c90; alias, 1 drivers +v0x11206d0_0 .net "sum", 0 0, L_0x1311170; alias, 1 drivers +S_0x1122ef0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1112520; + .timescale -9 -12; +L_0x2ac432886a08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886a50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1310ad0/d .functor OR 1, L_0x2ac432886a08, L_0x2ac432886a50, C4<0>, C4<0>; +L_0x1310ad0 .delay 1 (30000,30000,30000) L_0x1310ad0/d; +v0x11230e0_0 .net/2u *"_s0", 0 0, L_0x2ac432886a08; 1 drivers +v0x11231c0_0 .net/2u *"_s2", 0 0, L_0x2ac432886a50; 1 drivers +S_0x11232a0 .scope generate, "alu_slices[15]" "alu_slices[15]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11234b0 .param/l "i" 0 3 39, +C4<01111>; +S_0x1123570 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11232a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1310310/d .functor NOT 1, L_0x1325440, C4<0>, C4<0>, C4<0>; +L_0x1310310 .delay 1 (10000,10000,10000) L_0x1310310/d; +L_0x131b0c0/d .functor NOT 1, L_0x131af50, C4<0>, C4<0>, C4<0>; +L_0x131b0c0 .delay 1 (10000,10000,10000) L_0x131b0c0/d; +L_0x131c110/d .functor XOR 1, L_0x1325440, L_0x131af50, C4<0>, C4<0>; +L_0x131c110 .delay 1 (30000,30000,30000) L_0x131c110/d; +L_0x2ac432886a98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886ae0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131c1d0/d .functor OR 1, L_0x2ac432886a98, L_0x2ac432886ae0, C4<0>, C4<0>; +L_0x131c1d0 .delay 1 (30000,30000,30000) L_0x131c1d0/d; +L_0x2ac432886b28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886b70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131c970/d .functor OR 1, L_0x2ac432886b28, L_0x2ac432886b70, C4<0>, C4<0>; +L_0x131c970 .delay 1 (30000,30000,30000) L_0x131c970/d; +L_0x131cb70/d .functor AND 1, L_0x1325440, L_0x131af50, C4<1>, C4<1>; +L_0x131cb70 .delay 1 (30000,30000,30000) L_0x131cb70/d; +L_0x2ac432886bb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886c00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131cc30/d .functor OR 1, L_0x2ac432886bb8, L_0x2ac432886c00, C4<0>, C4<0>; +L_0x131cc30 .delay 1 (30000,30000,30000) L_0x131cc30/d; +L_0x131ce30/d .functor NAND 1, L_0x1325440, L_0x131af50, C4<1>, C4<1>; +L_0x131ce30 .delay 1 (20000,20000,20000) L_0x131ce30/d; +L_0x2ac432886c48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886c90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131cf40/d .functor OR 1, L_0x2ac432886c48, L_0x2ac432886c90, C4<0>, C4<0>; +L_0x131cf40 .delay 1 (30000,30000,30000) L_0x131cf40/d; +L_0x131d0f0/d .functor NOR 1, L_0x1325440, L_0x131af50, C4<0>, C4<0>; +L_0x131d0f0 .delay 1 (20000,20000,20000) L_0x131d0f0/d; +L_0x2ac432886cd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886d20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131b570/d .functor OR 1, L_0x2ac432886cd8, L_0x2ac432886d20, C4<0>, C4<0>; +L_0x131b570 .delay 1 (30000,30000,30000) L_0x131b570/d; +L_0x131d750/d .functor OR 1, L_0x1325440, L_0x131af50, C4<0>, C4<0>; +L_0x131d750 .delay 1 (30000,30000,30000) L_0x131d750/d; +L_0x2ac432886d68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886db0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131dc40/d .functor OR 1, L_0x2ac432886d68, L_0x2ac432886db0, C4<0>, C4<0>; +L_0x131dc40 .delay 1 (30000,30000,30000) L_0x131dc40/d; +L_0x1325340/d .functor NOT 1, L_0x13215a0, C4<0>, C4<0>, C4<0>; +L_0x1325340 .delay 1 (10000,10000,10000) L_0x1325340/d; +v0x1131ca0_0 .net "A", 0 0, L_0x1325440; 1 drivers +v0x1131d60_0 .net "A_", 0 0, L_0x1310310; 1 drivers +v0x1131e20_0 .net "B", 0 0, L_0x131af50; 1 drivers +v0x1131ef0_0 .net "B_", 0 0, L_0x131b0c0; 1 drivers +v0x1131f90_0 .net *"_s11", 0 0, L_0x131c1d0; 1 drivers +v0x1132080_0 .net/2s *"_s13", 0 0, L_0x2ac432886a98; 1 drivers +v0x1132140_0 .net/2s *"_s15", 0 0, L_0x2ac432886ae0; 1 drivers +v0x1132220_0 .net *"_s19", 0 0, L_0x131c970; 1 drivers +v0x1132300_0 .net/2s *"_s21", 0 0, L_0x2ac432886b28; 1 drivers +v0x1132470_0 .net/2s *"_s23", 0 0, L_0x2ac432886b70; 1 drivers +v0x1132550_0 .net *"_s25", 0 0, L_0x131cb70; 1 drivers +v0x1132630_0 .net *"_s28", 0 0, L_0x131cc30; 1 drivers +v0x1132710_0 .net/2s *"_s30", 0 0, L_0x2ac432886bb8; 1 drivers +v0x11327f0_0 .net/2s *"_s32", 0 0, L_0x2ac432886c00; 1 drivers +v0x11328d0_0 .net *"_s34", 0 0, L_0x131ce30; 1 drivers +v0x11329b0_0 .net *"_s37", 0 0, L_0x131cf40; 1 drivers +v0x1132a90_0 .net/2s *"_s39", 0 0, L_0x2ac432886c48; 1 drivers +v0x1132c40_0 .net/2s *"_s41", 0 0, L_0x2ac432886c90; 1 drivers +v0x1132ce0_0 .net *"_s43", 0 0, L_0x131d0f0; 1 drivers +v0x1132dc0_0 .net *"_s46", 0 0, L_0x131b570; 1 drivers +v0x1132ea0_0 .net/2s *"_s48", 0 0, L_0x2ac432886cd8; 1 drivers +v0x1132f80_0 .net/2s *"_s50", 0 0, L_0x2ac432886d20; 1 drivers +v0x1133060_0 .net *"_s52", 0 0, L_0x131d750; 1 drivers +v0x1133140_0 .net *"_s56", 0 0, L_0x131dc40; 1 drivers +v0x1133220_0 .net/2s *"_s59", 0 0, L_0x2ac432886d68; 1 drivers +v0x1133300_0 .net/2s *"_s61", 0 0, L_0x2ac432886db0; 1 drivers +v0x11333e0_0 .net *"_s8", 0 0, L_0x131c110; 1 drivers +v0x11334c0_0 .net "carryin", 0 0, L_0x131aff0; 1 drivers +v0x1133560_0 .net "carryout", 0 0, L_0x1324fe0; 1 drivers +v0x1133600_0 .net "carryouts", 7 0, L_0x131d8d0; 1 drivers +v0x1133710_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11337d0_0 .net "result", 0 0, L_0x13215a0; 1 drivers +v0x11338c0_0 .net "results", 7 0, L_0x131d520; 1 drivers +v0x1132ba0_0 .net "zero", 0 0, L_0x1325340; 1 drivers +LS_0x131d520_0_0 .concat8 [ 1 1 1 1], L_0x131b5e0, L_0x131bc10, L_0x131c110, L_0x131c970; +LS_0x131d520_0_4 .concat8 [ 1 1 1 1], L_0x131cb70, L_0x131ce30, L_0x131d0f0, L_0x131d750; +L_0x131d520 .concat8 [ 4 4 0 0], LS_0x131d520_0_0, LS_0x131d520_0_4; +LS_0x131d8d0_0_0 .concat8 [ 1 1 1 1], L_0x131b890, L_0x131bfb0, L_0x131c1d0, L_0x131c7c0; +LS_0x131d8d0_0_4 .concat8 [ 1 1 1 1], L_0x131cc30, L_0x131cf40, L_0x131b570, L_0x131dc40; +L_0x131d8d0 .concat8 [ 4 4 0 0], LS_0x131d8d0_0_0, LS_0x131d8d0_0_4; +S_0x11237f0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1123570; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x131b890/d .functor OR 1, L_0x131b370, L_0x131b730, C4<0>, C4<0>; +L_0x131b890 .delay 1 (30000,30000,30000) L_0x131b890/d; +v0x1124620_0 .net "a", 0 0, L_0x1325440; alias, 1 drivers +v0x11246e0_0 .net "b", 0 0, L_0x131af50; alias, 1 drivers +v0x11247b0_0 .net "c1", 0 0, L_0x131b370; 1 drivers +v0x11248b0_0 .net "c2", 0 0, L_0x131b730; 1 drivers +v0x1124980_0 .net "carryin", 0 0, L_0x131aff0; alias, 1 drivers +v0x1124a70_0 .net "carryout", 0 0, L_0x131b890; 1 drivers +v0x1124b10_0 .net "s1", 0 0, L_0x131b2b0; 1 drivers +v0x1124c00_0 .net "sum", 0 0, L_0x131b5e0; 1 drivers +S_0x1123a60 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11237f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x131b2b0/d .functor XOR 1, L_0x1325440, L_0x131af50, C4<0>, C4<0>; +L_0x131b2b0 .delay 1 (30000,30000,30000) L_0x131b2b0/d; +L_0x131b370/d .functor AND 1, L_0x1325440, L_0x131af50, C4<1>, C4<1>; +L_0x131b370 .delay 1 (30000,30000,30000) L_0x131b370/d; +v0x1123cc0_0 .net "a", 0 0, L_0x1325440; alias, 1 drivers +v0x1123da0_0 .net "b", 0 0, L_0x131af50; alias, 1 drivers +v0x1123e60_0 .net "carryout", 0 0, L_0x131b370; alias, 1 drivers +v0x1123f00_0 .net "sum", 0 0, L_0x131b2b0; alias, 1 drivers +S_0x1124040 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11237f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x131b5e0/d .functor XOR 1, L_0x131b2b0, L_0x131aff0, C4<0>, C4<0>; +L_0x131b5e0 .delay 1 (30000,30000,30000) L_0x131b5e0/d; +L_0x131b730/d .functor AND 1, L_0x131b2b0, L_0x131aff0, C4<1>, C4<1>; +L_0x131b730 .delay 1 (30000,30000,30000) L_0x131b730/d; +v0x11242a0_0 .net "a", 0 0, L_0x131b2b0; alias, 1 drivers +v0x1124340_0 .net "b", 0 0, L_0x131aff0; alias, 1 drivers +v0x11243e0_0 .net "carryout", 0 0, L_0x131b730; alias, 1 drivers +v0x11244b0_0 .net "sum", 0 0, L_0x131b5e0; alias, 1 drivers +S_0x1124cd0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1123570; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x112a0c0_0 .net "ands", 7 0, L_0x1322fe0; 1 drivers +v0x112a1d0_0 .net "in", 7 0, L_0x131d8d0; alias, 1 drivers +v0x112a290_0 .net "out", 0 0, L_0x1324fe0; alias, 1 drivers +v0x112a360_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1124ef0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1124cd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1127620_0 .net "A", 7 0, L_0x131d8d0; alias, 1 drivers +v0x1127720_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11277e0_0 .net *"_s0", 0 0, L_0x1321900; 1 drivers +v0x11278a0_0 .net *"_s12", 0 0, L_0x1322270; 1 drivers +v0x1127980_0 .net *"_s16", 0 0, L_0x13225d0; 1 drivers +v0x1127ab0_0 .net *"_s20", 0 0, L_0x13229a0; 1 drivers +v0x1127b90_0 .net *"_s24", 0 0, L_0x1322cd0; 1 drivers +v0x1127c70_0 .net *"_s28", 0 0, L_0x1322c60; 1 drivers +v0x1127d50_0 .net *"_s4", 0 0, L_0x1321c50; 1 drivers +v0x1127ec0_0 .net *"_s8", 0 0, L_0x1321f60; 1 drivers +v0x1127fa0_0 .net "out", 7 0, L_0x1322fe0; alias, 1 drivers +L_0x13219c0 .part L_0x131d8d0, 0, 1; +L_0x1321bb0 .part v0x127a150_0, 0, 1; +L_0x1321d10 .part L_0x131d8d0, 1, 1; +L_0x1321e70 .part v0x127a150_0, 1, 1; +L_0x1322020 .part L_0x131d8d0, 2, 1; +L_0x1322180 .part v0x127a150_0, 2, 1; +L_0x1322330 .part L_0x131d8d0, 3, 1; +L_0x1322490 .part v0x127a150_0, 3, 1; +L_0x1322690 .part L_0x131d8d0, 4, 1; +L_0x1322900 .part v0x127a150_0, 4, 1; +L_0x1322a10 .part L_0x131d8d0, 5, 1; +L_0x1322b70 .part v0x127a150_0, 5, 1; +L_0x1322d90 .part L_0x131d8d0, 6, 1; +L_0x1322ef0 .part v0x127a150_0, 6, 1; +LS_0x1322fe0_0_0 .concat8 [ 1 1 1 1], L_0x1321900, L_0x1321c50, L_0x1321f60, L_0x1322270; +LS_0x1322fe0_0_4 .concat8 [ 1 1 1 1], L_0x13225d0, L_0x13229a0, L_0x1322cd0, L_0x1322c60; +L_0x1322fe0 .concat8 [ 4 4 0 0], LS_0x1322fe0_0_0, LS_0x1322fe0_0_4; +L_0x13233a0 .part L_0x131d8d0, 7, 1; +L_0x1323590 .part v0x127a150_0, 7, 1; +S_0x1125150 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x1125360 .param/l "i" 0 4 54, +C4<00>; +L_0x1321900/d .functor AND 1, L_0x13219c0, L_0x1321bb0, C4<1>, C4<1>; +L_0x1321900 .delay 1 (30000,30000,30000) L_0x1321900/d; +v0x1125440_0 .net *"_s0", 0 0, L_0x13219c0; 1 drivers +v0x1125520_0 .net *"_s1", 0 0, L_0x1321bb0; 1 drivers +S_0x1125600 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x1125810 .param/l "i" 0 4 54, +C4<01>; +L_0x1321c50/d .functor AND 1, L_0x1321d10, L_0x1321e70, C4<1>, C4<1>; +L_0x1321c50 .delay 1 (30000,30000,30000) L_0x1321c50/d; +v0x11258d0_0 .net *"_s0", 0 0, L_0x1321d10; 1 drivers +v0x11259b0_0 .net *"_s1", 0 0, L_0x1321e70; 1 drivers +S_0x1125a90 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x1125ca0 .param/l "i" 0 4 54, +C4<010>; +L_0x1321f60/d .functor AND 1, L_0x1322020, L_0x1322180, C4<1>, C4<1>; +L_0x1321f60 .delay 1 (30000,30000,30000) L_0x1321f60/d; +v0x1125d40_0 .net *"_s0", 0 0, L_0x1322020; 1 drivers +v0x1125e20_0 .net *"_s1", 0 0, L_0x1322180; 1 drivers +S_0x1125f00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x1126110 .param/l "i" 0 4 54, +C4<011>; +L_0x1322270/d .functor AND 1, L_0x1322330, L_0x1322490, C4<1>, C4<1>; +L_0x1322270 .delay 1 (30000,30000,30000) L_0x1322270/d; +v0x11261d0_0 .net *"_s0", 0 0, L_0x1322330; 1 drivers +v0x11262b0_0 .net *"_s1", 0 0, L_0x1322490; 1 drivers +S_0x1126390 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x11265f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x13225d0/d .functor AND 1, L_0x1322690, L_0x1322900, C4<1>, C4<1>; +L_0x13225d0 .delay 1 (30000,30000,30000) L_0x13225d0/d; +v0x11266b0_0 .net *"_s0", 0 0, L_0x1322690; 1 drivers +v0x1126790_0 .net *"_s1", 0 0, L_0x1322900; 1 drivers +S_0x1126870 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x1126a80 .param/l "i" 0 4 54, +C4<0101>; +L_0x13229a0/d .functor AND 1, L_0x1322a10, L_0x1322b70, C4<1>, C4<1>; +L_0x13229a0 .delay 1 (30000,30000,30000) L_0x13229a0/d; +v0x1126b40_0 .net *"_s0", 0 0, L_0x1322a10; 1 drivers +v0x1126c20_0 .net *"_s1", 0 0, L_0x1322b70; 1 drivers +S_0x1126d00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x1126f10 .param/l "i" 0 4 54, +C4<0110>; +L_0x1322cd0/d .functor AND 1, L_0x1322d90, L_0x1322ef0, C4<1>, C4<1>; +L_0x1322cd0 .delay 1 (30000,30000,30000) L_0x1322cd0/d; +v0x1126fd0_0 .net *"_s0", 0 0, L_0x1322d90; 1 drivers +v0x11270b0_0 .net *"_s1", 0 0, L_0x1322ef0; 1 drivers +S_0x1127190 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1124ef0; + .timescale -9 -12; +P_0x11273a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1322c60/d .functor AND 1, L_0x13233a0, L_0x1323590, C4<1>, C4<1>; +L_0x1322c60 .delay 1 (30000,30000,30000) L_0x1322c60/d; +v0x1127460_0 .net *"_s0", 0 0, L_0x13233a0; 1 drivers +v0x1127540_0 .net *"_s1", 0 0, L_0x1323590; 1 drivers +S_0x1128100 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1124cd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1324fe0/d .functor OR 1, L_0x13250a0, L_0x1325250, C4<0>, C4<0>; +L_0x1324fe0 .delay 1 (30000,30000,30000) L_0x1324fe0/d; +v0x1129c50_0 .net *"_s10", 0 0, L_0x13250a0; 1 drivers +v0x1129d30_0 .net *"_s12", 0 0, L_0x1325250; 1 drivers +v0x1129e10_0 .net "in", 7 0, L_0x1322fe0; alias, 1 drivers +v0x1129ee0_0 .net "ors", 1 0, L_0x1324e00; 1 drivers +v0x1129fa0_0 .net "out", 0 0, L_0x1324fe0; alias, 1 drivers +L_0x13241d0 .part L_0x1322fe0, 0, 4; +L_0x1324e00 .concat8 [ 1 1 0 0], L_0x1323ec0, L_0x1324af0; +L_0x1324f40 .part L_0x1322fe0, 4, 4; +L_0x13250a0 .part L_0x1324e00, 0, 1; +L_0x1325250 .part L_0x1324e00, 1, 1; +S_0x11282c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1128100; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1323680/d .functor OR 1, L_0x1323740, L_0x13238a0, C4<0>, C4<0>; +L_0x1323680 .delay 1 (30000,30000,30000) L_0x1323680/d; +L_0x1323ad0/d .functor OR 1, L_0x1323be0, L_0x1323d40, C4<0>, C4<0>; +L_0x1323ad0 .delay 1 (30000,30000,30000) L_0x1323ad0/d; +L_0x1323ec0/d .functor OR 1, L_0x1323f30, L_0x13240e0, C4<0>, C4<0>; +L_0x1323ec0 .delay 1 (30000,30000,30000) L_0x1323ec0/d; +v0x1128510_0 .net *"_s0", 0 0, L_0x1323680; 1 drivers +v0x1128610_0 .net *"_s10", 0 0, L_0x1323be0; 1 drivers +v0x11286f0_0 .net *"_s12", 0 0, L_0x1323d40; 1 drivers +v0x11287b0_0 .net *"_s14", 0 0, L_0x1323f30; 1 drivers +v0x1128890_0 .net *"_s16", 0 0, L_0x13240e0; 1 drivers +v0x11289c0_0 .net *"_s3", 0 0, L_0x1323740; 1 drivers +v0x1128aa0_0 .net *"_s5", 0 0, L_0x13238a0; 1 drivers +v0x1128b80_0 .net *"_s6", 0 0, L_0x1323ad0; 1 drivers +v0x1128c60_0 .net "in", 3 0, L_0x13241d0; 1 drivers +v0x1128dd0_0 .net "ors", 1 0, L_0x13239e0; 1 drivers +v0x1128eb0_0 .net "out", 0 0, L_0x1323ec0; 1 drivers +L_0x1323740 .part L_0x13241d0, 0, 1; +L_0x13238a0 .part L_0x13241d0, 1, 1; +L_0x13239e0 .concat8 [ 1 1 0 0], L_0x1323680, L_0x1323ad0; +L_0x1323be0 .part L_0x13241d0, 2, 1; +L_0x1323d40 .part L_0x13241d0, 3, 1; +L_0x1323f30 .part L_0x13239e0, 0, 1; +L_0x13240e0 .part L_0x13239e0, 1, 1; +S_0x1128fd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1128100; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1324300/d .functor OR 1, L_0x1324370, L_0x13244d0, C4<0>, C4<0>; +L_0x1324300 .delay 1 (30000,30000,30000) L_0x1324300/d; +L_0x1324700/d .functor OR 1, L_0x1324810, L_0x1324970, C4<0>, C4<0>; +L_0x1324700 .delay 1 (30000,30000,30000) L_0x1324700/d; +L_0x1324af0/d .functor OR 1, L_0x1324b60, L_0x1324d10, C4<0>, C4<0>; +L_0x1324af0 .delay 1 (30000,30000,30000) L_0x1324af0/d; +v0x1129190_0 .net *"_s0", 0 0, L_0x1324300; 1 drivers +v0x1129290_0 .net *"_s10", 0 0, L_0x1324810; 1 drivers +v0x1129370_0 .net *"_s12", 0 0, L_0x1324970; 1 drivers +v0x1129430_0 .net *"_s14", 0 0, L_0x1324b60; 1 drivers +v0x1129510_0 .net *"_s16", 0 0, L_0x1324d10; 1 drivers +v0x1129640_0 .net *"_s3", 0 0, L_0x1324370; 1 drivers +v0x1129720_0 .net *"_s5", 0 0, L_0x13244d0; 1 drivers +v0x1129800_0 .net *"_s6", 0 0, L_0x1324700; 1 drivers +v0x11298e0_0 .net "in", 3 0, L_0x1324f40; 1 drivers +v0x1129a50_0 .net "ors", 1 0, L_0x1324610; 1 drivers +v0x1129b30_0 .net "out", 0 0, L_0x1324af0; 1 drivers +L_0x1324370 .part L_0x1324f40, 0, 1; +L_0x13244d0 .part L_0x1324f40, 1, 1; +L_0x1324610 .concat8 [ 1 1 0 0], L_0x1324300, L_0x1324700; +L_0x1324810 .part L_0x1324f40, 2, 1; +L_0x1324970 .part L_0x1324f40, 3, 1; +L_0x1324b60 .part L_0x1324610, 0, 1; +L_0x1324d10 .part L_0x1324610, 1, 1; +S_0x112a440 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1123570; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x112f870_0 .net "ands", 7 0, L_0x131f5a0; 1 drivers +v0x112f980_0 .net "in", 7 0, L_0x131d520; alias, 1 drivers +v0x112fa40_0 .net "out", 0 0, L_0x13215a0; alias, 1 drivers +v0x112fb10_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x112a690 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x112a440; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x112cdd0_0 .net "A", 7 0, L_0x131d520; alias, 1 drivers +v0x112ced0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x112cf90_0 .net *"_s0", 0 0, L_0x131ddf0; 1 drivers +v0x112d050_0 .net *"_s12", 0 0, L_0x131e7b0; 1 drivers +v0x112d130_0 .net *"_s16", 0 0, L_0x131eb10; 1 drivers +v0x112d260_0 .net *"_s20", 0 0, L_0x131eee0; 1 drivers +v0x112d340_0 .net *"_s24", 0 0, L_0x131f210; 1 drivers +v0x112d420_0 .net *"_s28", 0 0, L_0x131f1a0; 1 drivers +v0x112d500_0 .net *"_s4", 0 0, L_0x131e190; 1 drivers +v0x112d670_0 .net *"_s8", 0 0, L_0x131e4a0; 1 drivers +v0x112d750_0 .net "out", 7 0, L_0x131f5a0; alias, 1 drivers +L_0x131df00 .part L_0x131d520, 0, 1; +L_0x131e0f0 .part v0x127a150_0, 0, 1; +L_0x131e250 .part L_0x131d520, 1, 1; +L_0x131e3b0 .part v0x127a150_0, 1, 1; +L_0x131e560 .part L_0x131d520, 2, 1; +L_0x131e6c0 .part v0x127a150_0, 2, 1; +L_0x131e870 .part L_0x131d520, 3, 1; +L_0x131e9d0 .part v0x127a150_0, 3, 1; +L_0x131ebd0 .part L_0x131d520, 4, 1; +L_0x131ee40 .part v0x127a150_0, 4, 1; +L_0x131ef50 .part L_0x131d520, 5, 1; +L_0x131f0b0 .part v0x127a150_0, 5, 1; +L_0x131f2d0 .part L_0x131d520, 6, 1; +L_0x131f430 .part v0x127a150_0, 6, 1; +LS_0x131f5a0_0_0 .concat8 [ 1 1 1 1], L_0x131ddf0, L_0x131e190, L_0x131e4a0, L_0x131e7b0; +LS_0x131f5a0_0_4 .concat8 [ 1 1 1 1], L_0x131eb10, L_0x131eee0, L_0x131f210, L_0x131f1a0; +L_0x131f5a0 .concat8 [ 4 4 0 0], LS_0x131f5a0_0_0, LS_0x131f5a0_0_4; +L_0x131f960 .part L_0x131d520, 7, 1; +L_0x131fb50 .part v0x127a150_0, 7, 1; +S_0x112a8d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112aae0 .param/l "i" 0 4 54, +C4<00>; +L_0x131ddf0/d .functor AND 1, L_0x131df00, L_0x131e0f0, C4<1>, C4<1>; +L_0x131ddf0 .delay 1 (30000,30000,30000) L_0x131ddf0/d; +v0x112abc0_0 .net *"_s0", 0 0, L_0x131df00; 1 drivers +v0x112aca0_0 .net *"_s1", 0 0, L_0x131e0f0; 1 drivers +S_0x112ad80 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112af90 .param/l "i" 0 4 54, +C4<01>; +L_0x131e190/d .functor AND 1, L_0x131e250, L_0x131e3b0, C4<1>, C4<1>; +L_0x131e190 .delay 1 (30000,30000,30000) L_0x131e190/d; +v0x112b050_0 .net *"_s0", 0 0, L_0x131e250; 1 drivers +v0x112b130_0 .net *"_s1", 0 0, L_0x131e3b0; 1 drivers +S_0x112b210 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112b450 .param/l "i" 0 4 54, +C4<010>; +L_0x131e4a0/d .functor AND 1, L_0x131e560, L_0x131e6c0, C4<1>, C4<1>; +L_0x131e4a0 .delay 1 (30000,30000,30000) L_0x131e4a0/d; +v0x112b4f0_0 .net *"_s0", 0 0, L_0x131e560; 1 drivers +v0x112b5d0_0 .net *"_s1", 0 0, L_0x131e6c0; 1 drivers +S_0x112b6b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112b8c0 .param/l "i" 0 4 54, +C4<011>; +L_0x131e7b0/d .functor AND 1, L_0x131e870, L_0x131e9d0, C4<1>, C4<1>; +L_0x131e7b0 .delay 1 (30000,30000,30000) L_0x131e7b0/d; +v0x112b980_0 .net *"_s0", 0 0, L_0x131e870; 1 drivers +v0x112ba60_0 .net *"_s1", 0 0, L_0x131e9d0; 1 drivers +S_0x112bb40 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112bda0 .param/l "i" 0 4 54, +C4<0100>; +L_0x131eb10/d .functor AND 1, L_0x131ebd0, L_0x131ee40, C4<1>, C4<1>; +L_0x131eb10 .delay 1 (30000,30000,30000) L_0x131eb10/d; +v0x112be60_0 .net *"_s0", 0 0, L_0x131ebd0; 1 drivers +v0x112bf40_0 .net *"_s1", 0 0, L_0x131ee40; 1 drivers +S_0x112c020 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112c230 .param/l "i" 0 4 54, +C4<0101>; +L_0x131eee0/d .functor AND 1, L_0x131ef50, L_0x131f0b0, C4<1>, C4<1>; +L_0x131eee0 .delay 1 (30000,30000,30000) L_0x131eee0/d; +v0x112c2f0_0 .net *"_s0", 0 0, L_0x131ef50; 1 drivers +v0x112c3d0_0 .net *"_s1", 0 0, L_0x131f0b0; 1 drivers +S_0x112c4b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112c6c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x131f210/d .functor AND 1, L_0x131f2d0, L_0x131f430, C4<1>, C4<1>; +L_0x131f210 .delay 1 (30000,30000,30000) L_0x131f210/d; +v0x112c780_0 .net *"_s0", 0 0, L_0x131f2d0; 1 drivers +v0x112c860_0 .net *"_s1", 0 0, L_0x131f430; 1 drivers +S_0x112c940 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x112a690; + .timescale -9 -12; +P_0x112cb50 .param/l "i" 0 4 54, +C4<0111>; +L_0x131f1a0/d .functor AND 1, L_0x131f960, L_0x131fb50, C4<1>, C4<1>; +L_0x131f1a0 .delay 1 (30000,30000,30000) L_0x131f1a0/d; +v0x112cc10_0 .net *"_s0", 0 0, L_0x131f960; 1 drivers +v0x112ccf0_0 .net *"_s1", 0 0, L_0x131fb50; 1 drivers +S_0x112d8b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x112a440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13215a0/d .functor OR 1, L_0x1321660, L_0x1321810, C4<0>, C4<0>; +L_0x13215a0 .delay 1 (30000,30000,30000) L_0x13215a0/d; +v0x112f400_0 .net *"_s10", 0 0, L_0x1321660; 1 drivers +v0x112f4e0_0 .net *"_s12", 0 0, L_0x1321810; 1 drivers +v0x112f5c0_0 .net "in", 7 0, L_0x131f5a0; alias, 1 drivers +v0x112f690_0 .net "ors", 1 0, L_0x13213c0; 1 drivers +v0x112f750_0 .net "out", 0 0, L_0x13215a0; alias, 1 drivers +L_0x1320790 .part L_0x131f5a0, 0, 4; +L_0x13213c0 .concat8 [ 1 1 0 0], L_0x1320480, L_0x13210b0; +L_0x1321500 .part L_0x131f5a0, 4, 4; +L_0x1321660 .part L_0x13213c0, 0, 1; +L_0x1321810 .part L_0x13213c0, 1, 1; +S_0x112da70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x112d8b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x131fc40/d .functor OR 1, L_0x131fd00, L_0x131fe60, C4<0>, C4<0>; +L_0x131fc40 .delay 1 (30000,30000,30000) L_0x131fc40/d; +L_0x1320090/d .functor OR 1, L_0x13201a0, L_0x1320300, C4<0>, C4<0>; +L_0x1320090 .delay 1 (30000,30000,30000) L_0x1320090/d; +L_0x1320480/d .functor OR 1, L_0x13204f0, L_0x13206a0, C4<0>, C4<0>; +L_0x1320480 .delay 1 (30000,30000,30000) L_0x1320480/d; +v0x112dcc0_0 .net *"_s0", 0 0, L_0x131fc40; 1 drivers +v0x112ddc0_0 .net *"_s10", 0 0, L_0x13201a0; 1 drivers +v0x112dea0_0 .net *"_s12", 0 0, L_0x1320300; 1 drivers +v0x112df60_0 .net *"_s14", 0 0, L_0x13204f0; 1 drivers +v0x112e040_0 .net *"_s16", 0 0, L_0x13206a0; 1 drivers +v0x112e170_0 .net *"_s3", 0 0, L_0x131fd00; 1 drivers +v0x112e250_0 .net *"_s5", 0 0, L_0x131fe60; 1 drivers +v0x112e330_0 .net *"_s6", 0 0, L_0x1320090; 1 drivers +v0x112e410_0 .net "in", 3 0, L_0x1320790; 1 drivers +v0x112e580_0 .net "ors", 1 0, L_0x131ffa0; 1 drivers +v0x112e660_0 .net "out", 0 0, L_0x1320480; 1 drivers +L_0x131fd00 .part L_0x1320790, 0, 1; +L_0x131fe60 .part L_0x1320790, 1, 1; +L_0x131ffa0 .concat8 [ 1 1 0 0], L_0x131fc40, L_0x1320090; +L_0x13201a0 .part L_0x1320790, 2, 1; +L_0x1320300 .part L_0x1320790, 3, 1; +L_0x13204f0 .part L_0x131ffa0, 0, 1; +L_0x13206a0 .part L_0x131ffa0, 1, 1; +S_0x112e780 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x112d8b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13208c0/d .functor OR 1, L_0x1320930, L_0x1320a90, C4<0>, C4<0>; +L_0x13208c0 .delay 1 (30000,30000,30000) L_0x13208c0/d; +L_0x1320cc0/d .functor OR 1, L_0x1320dd0, L_0x1320f30, C4<0>, C4<0>; +L_0x1320cc0 .delay 1 (30000,30000,30000) L_0x1320cc0/d; +L_0x13210b0/d .functor OR 1, L_0x1321120, L_0x13212d0, C4<0>, C4<0>; +L_0x13210b0 .delay 1 (30000,30000,30000) L_0x13210b0/d; +v0x112e940_0 .net *"_s0", 0 0, L_0x13208c0; 1 drivers +v0x112ea40_0 .net *"_s10", 0 0, L_0x1320dd0; 1 drivers +v0x112eb20_0 .net *"_s12", 0 0, L_0x1320f30; 1 drivers +v0x112ebe0_0 .net *"_s14", 0 0, L_0x1321120; 1 drivers +v0x112ecc0_0 .net *"_s16", 0 0, L_0x13212d0; 1 drivers +v0x112edf0_0 .net *"_s3", 0 0, L_0x1320930; 1 drivers +v0x112eed0_0 .net *"_s5", 0 0, L_0x1320a90; 1 drivers +v0x112efb0_0 .net *"_s6", 0 0, L_0x1320cc0; 1 drivers +v0x112f090_0 .net "in", 3 0, L_0x1321500; 1 drivers +v0x112f200_0 .net "ors", 1 0, L_0x1320bd0; 1 drivers +v0x112f2e0_0 .net "out", 0 0, L_0x13210b0; 1 drivers +L_0x1320930 .part L_0x1321500, 0, 1; +L_0x1320a90 .part L_0x1321500, 1, 1; +L_0x1320bd0 .concat8 [ 1 1 0 0], L_0x13208c0, L_0x1320cc0; +L_0x1320dd0 .part L_0x1321500, 2, 1; +L_0x1320f30 .part L_0x1321500, 3, 1; +L_0x1321120 .part L_0x1320bd0, 0, 1; +L_0x13212d0 .part L_0x1320bd0, 1, 1; +S_0x112fbf0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1123570; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x131c3d0/d .functor XNOR 1, L_0x1325440, L_0x131af50, C4<0>, C4<0>; +L_0x131c3d0 .delay 1 (20000,20000,20000) L_0x131c3d0/d; +L_0x131c550/d .functor AND 1, L_0x1325440, L_0x131b0c0, C4<1>, C4<1>; +L_0x131c550 .delay 1 (30000,30000,30000) L_0x131c550/d; +L_0x131c6b0/d .functor AND 1, L_0x131c3d0, L_0x131aff0, C4<1>, C4<1>; +L_0x131c6b0 .delay 1 (30000,30000,30000) L_0x131c6b0/d; +L_0x131c7c0/d .functor OR 1, L_0x131c6b0, L_0x131c550, C4<0>, C4<0>; +L_0x131c7c0 .delay 1 (30000,30000,30000) L_0x131c7c0/d; +v0x112fea0_0 .net "a", 0 0, L_0x1325440; alias, 1 drivers +v0x112ff90_0 .net "a_", 0 0, L_0x1310310; alias, 1 drivers +v0x1130050_0 .net "b", 0 0, L_0x131af50; alias, 1 drivers +v0x1130140_0 .net "b_", 0 0, L_0x131b0c0; alias, 1 drivers +v0x11301e0_0 .net "carryin", 0 0, L_0x131aff0; alias, 1 drivers +v0x1130320_0 .net "eq", 0 0, L_0x131c3d0; 1 drivers +v0x11303e0_0 .net "lt", 0 0, L_0x131c550; 1 drivers +v0x11304a0_0 .net "out", 0 0, L_0x131c7c0; 1 drivers +v0x1130560_0 .net "w0", 0 0, L_0x131c6b0; 1 drivers +S_0x11307b0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1123570; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x131bfb0/d .functor OR 1, L_0x131bab0, L_0x1131a10, C4<0>, C4<0>; +L_0x131bfb0 .delay 1 (30000,30000,30000) L_0x131bfb0/d; +v0x11315a0_0 .net "a", 0 0, L_0x1325440; alias, 1 drivers +v0x11316f0_0 .net "b", 0 0, L_0x131b0c0; alias, 1 drivers +v0x11317b0_0 .net "c1", 0 0, L_0x131bab0; 1 drivers +v0x1131850_0 .net "c2", 0 0, L_0x1131a10; 1 drivers +v0x1131920_0 .net "carryin", 0 0, L_0x131aff0; alias, 1 drivers +v0x1131aa0_0 .net "carryout", 0 0, L_0x131bfb0; 1 drivers +v0x1131b40_0 .net "s1", 0 0, L_0x131b9f0; 1 drivers +v0x1131be0_0 .net "sum", 0 0, L_0x131bc10; 1 drivers +S_0x1130a00 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11307b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x131b9f0/d .functor XOR 1, L_0x1325440, L_0x131b0c0, C4<0>, C4<0>; +L_0x131b9f0 .delay 1 (30000,30000,30000) L_0x131b9f0/d; +L_0x131bab0/d .functor AND 1, L_0x1325440, L_0x131b0c0, C4<1>, C4<1>; +L_0x131bab0 .delay 1 (30000,30000,30000) L_0x131bab0/d; +v0x1130c60_0 .net "a", 0 0, L_0x1325440; alias, 1 drivers +v0x1130d20_0 .net "b", 0 0, L_0x131b0c0; alias, 1 drivers +v0x1130de0_0 .net "carryout", 0 0, L_0x131bab0; alias, 1 drivers +v0x1130e80_0 .net "sum", 0 0, L_0x131b9f0; alias, 1 drivers +S_0x1130fb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11307b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x131bc10/d .functor XOR 1, L_0x131b9f0, L_0x131aff0, C4<0>, C4<0>; +L_0x131bc10 .delay 1 (30000,30000,30000) L_0x131bc10/d; +L_0x1131a10/d .functor AND 1, L_0x131b9f0, L_0x131aff0, C4<1>, C4<1>; +L_0x1131a10 .delay 1 (30000,30000,30000) L_0x1131a10/d; +v0x1131210_0 .net "a", 0 0, L_0x131b9f0; alias, 1 drivers +v0x11312e0_0 .net "b", 0 0, L_0x131aff0; alias, 1 drivers +v0x1131380_0 .net "carryout", 0 0, L_0x1131a10; alias, 1 drivers +v0x1131450_0 .net "sum", 0 0, L_0x131bc10; alias, 1 drivers +S_0x1133c70 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11232a0; + .timescale -9 -12; +L_0x2ac432886df8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886e40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x131d860/d .functor OR 1, L_0x2ac432886df8, L_0x2ac432886e40, C4<0>, C4<0>; +L_0x131d860 .delay 1 (30000,30000,30000) L_0x131d860/d; +v0x1133e60_0 .net/2u *"_s0", 0 0, L_0x2ac432886df8; 1 drivers +v0x1133f40_0 .net/2u *"_s2", 0 0, L_0x2ac432886e40; 1 drivers +S_0x1134020 .scope generate, "alu_slices[16]" "alu_slices[16]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x10ad170 .param/l "i" 0 3 39, +C4<010000>; +S_0x1134390 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1134020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x12d0df0/d .functor NOT 1, L_0x132fe10, C4<0>, C4<0>, C4<0>; +L_0x12d0df0 .delay 1 (10000,10000,10000) L_0x12d0df0/d; +L_0x1325ac0/d .functor NOT 1, L_0x132ff70, C4<0>, C4<0>, C4<0>; +L_0x1325ac0 .delay 1 (10000,10000,10000) L_0x1325ac0/d; +L_0x1326ab0/d .functor XOR 1, L_0x132fe10, L_0x132ff70, C4<0>, C4<0>; +L_0x1326ab0 .delay 1 (30000,30000,30000) L_0x1326ab0/d; +L_0x2ac432886e88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886ed0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1326b70/d .functor OR 1, L_0x2ac432886e88, L_0x2ac432886ed0, C4<0>, C4<0>; +L_0x1326b70 .delay 1 (30000,30000,30000) L_0x1326b70/d; +L_0x2ac432886f18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886f60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13272c0/d .functor OR 1, L_0x2ac432886f18, L_0x2ac432886f60, C4<0>, C4<0>; +L_0x13272c0 .delay 1 (30000,30000,30000) L_0x13272c0/d; +L_0x13274c0/d .functor AND 1, L_0x132fe10, L_0x132ff70, C4<1>, C4<1>; +L_0x13274c0 .delay 1 (30000,30000,30000) L_0x13274c0/d; +L_0x2ac432886fa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432886ff0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1327580/d .functor OR 1, L_0x2ac432886fa8, L_0x2ac432886ff0, C4<0>, C4<0>; +L_0x1327580 .delay 1 (30000,30000,30000) L_0x1327580/d; +L_0x1327780/d .functor NAND 1, L_0x132fe10, L_0x132ff70, C4<1>, C4<1>; +L_0x1327780 .delay 1 (20000,20000,20000) L_0x1327780/d; +L_0x2ac432887038 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887080 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1327890/d .functor OR 1, L_0x2ac432887038, L_0x2ac432887080, C4<0>, C4<0>; +L_0x1327890 .delay 1 (30000,30000,30000) L_0x1327890/d; +L_0x1327a40/d .functor NOR 1, L_0x132fe10, L_0x132ff70, C4<0>, C4<0>; +L_0x1327a40 .delay 1 (20000,20000,20000) L_0x1327a40/d; +L_0x2ac4328870c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887110 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1327d10/d .functor OR 1, L_0x2ac4328870c8, L_0x2ac432887110, C4<0>, C4<0>; +L_0x1327d10 .delay 1 (30000,30000,30000) L_0x1327d10/d; +L_0x1328110/d .functor OR 1, L_0x132fe10, L_0x132ff70, C4<0>, C4<0>; +L_0x1328110 .delay 1 (30000,30000,30000) L_0x1328110/d; +L_0x2ac432887158 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328871a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13285b0/d .functor OR 1, L_0x2ac432887158, L_0x2ac4328871a0, C4<0>, C4<0>; +L_0x13285b0 .delay 1 (30000,30000,30000) L_0x13285b0/d; +L_0x132fd10/d .functor NOT 1, L_0x132bf70, C4<0>, C4<0>, C4<0>; +L_0x132fd10 .delay 1 (10000,10000,10000) L_0x132fd10/d; +v0x1142aa0_0 .net "A", 0 0, L_0x132fe10; 1 drivers +v0x1142b60_0 .net "A_", 0 0, L_0x12d0df0; 1 drivers +v0x1142c20_0 .net "B", 0 0, L_0x132ff70; 1 drivers +v0x1142cf0_0 .net "B_", 0 0, L_0x1325ac0; 1 drivers +v0x1142d90_0 .net *"_s11", 0 0, L_0x1326b70; 1 drivers +v0x1142e80_0 .net/2s *"_s13", 0 0, L_0x2ac432886e88; 1 drivers +v0x1142f40_0 .net/2s *"_s15", 0 0, L_0x2ac432886ed0; 1 drivers +v0x1143020_0 .net *"_s19", 0 0, L_0x13272c0; 1 drivers +v0x1143100_0 .net/2s *"_s21", 0 0, L_0x2ac432886f18; 1 drivers +v0x1143270_0 .net/2s *"_s23", 0 0, L_0x2ac432886f60; 1 drivers +v0x1143350_0 .net *"_s25", 0 0, L_0x13274c0; 1 drivers +v0x1143430_0 .net *"_s28", 0 0, L_0x1327580; 1 drivers +v0x1143510_0 .net/2s *"_s30", 0 0, L_0x2ac432886fa8; 1 drivers +v0x11435f0_0 .net/2s *"_s32", 0 0, L_0x2ac432886ff0; 1 drivers +v0x11436d0_0 .net *"_s34", 0 0, L_0x1327780; 1 drivers +v0x11437b0_0 .net *"_s37", 0 0, L_0x1327890; 1 drivers +v0x1143890_0 .net/2s *"_s39", 0 0, L_0x2ac432887038; 1 drivers +v0x1143a40_0 .net/2s *"_s41", 0 0, L_0x2ac432887080; 1 drivers +v0x1143ae0_0 .net *"_s43", 0 0, L_0x1327a40; 1 drivers +v0x1143bc0_0 .net *"_s46", 0 0, L_0x1327d10; 1 drivers +v0x1143ca0_0 .net/2s *"_s48", 0 0, L_0x2ac4328870c8; 1 drivers +v0x1143d80_0 .net/2s *"_s50", 0 0, L_0x2ac432887110; 1 drivers +v0x1143e60_0 .net *"_s52", 0 0, L_0x1328110; 1 drivers +v0x1143f40_0 .net *"_s56", 0 0, L_0x13285b0; 1 drivers +v0x1144020_0 .net/2s *"_s59", 0 0, L_0x2ac432887158; 1 drivers +v0x1144100_0 .net/2s *"_s61", 0 0, L_0x2ac4328871a0; 1 drivers +v0x11441e0_0 .net *"_s8", 0 0, L_0x1326ab0; 1 drivers +v0x11442c0_0 .net "carryin", 0 0, L_0x1325930; 1 drivers +v0x1144360_0 .net "carryout", 0 0, L_0x132f9b0; 1 drivers +v0x1144400_0 .net "carryouts", 7 0, L_0x1328220; 1 drivers +v0x1144510_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11445d0_0 .net "result", 0 0, L_0x132bf70; 1 drivers +v0x11446c0_0 .net "results", 7 0, L_0x1327ee0; 1 drivers +v0x11439a0_0 .net "zero", 0 0, L_0x132fd10; 1 drivers +LS_0x1327ee0_0_0 .concat8 [ 1 1 1 1], L_0x1325f80, L_0x13265b0, L_0x1326ab0, L_0x13272c0; +LS_0x1327ee0_0_4 .concat8 [ 1 1 1 1], L_0x13274c0, L_0x1327780, L_0x1327a40, L_0x1328110; +L_0x1327ee0 .concat8 [ 4 4 0 0], LS_0x1327ee0_0_0, LS_0x1327ee0_0_4; +LS_0x1328220_0_0 .concat8 [ 1 1 1 1], L_0x1326230, L_0x1326950, L_0x1326b70, L_0x1327110; +LS_0x1328220_0_4 .concat8 [ 1 1 1 1], L_0x1327580, L_0x1327890, L_0x1327d10, L_0x13285b0; +L_0x1328220 .concat8 [ 4 4 0 0], LS_0x1328220_0_0, LS_0x1328220_0_4; +S_0x1134610 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1134390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1326230/d .functor OR 1, L_0x1325d10, L_0x13260d0, C4<0>, C4<0>; +L_0x1326230 .delay 1 (30000,30000,30000) L_0x1326230/d; +v0x1135420_0 .net "a", 0 0, L_0x132fe10; alias, 1 drivers +v0x11354e0_0 .net "b", 0 0, L_0x132ff70; alias, 1 drivers +v0x11355b0_0 .net "c1", 0 0, L_0x1325d10; 1 drivers +v0x11356b0_0 .net "c2", 0 0, L_0x13260d0; 1 drivers +v0x1135780_0 .net "carryin", 0 0, L_0x1325930; alias, 1 drivers +v0x1135870_0 .net "carryout", 0 0, L_0x1326230; 1 drivers +v0x1135910_0 .net "s1", 0 0, L_0x1325c50; 1 drivers +v0x1135a00_0 .net "sum", 0 0, L_0x1325f80; 1 drivers +S_0x1134860 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1134610; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1325c50/d .functor XOR 1, L_0x132fe10, L_0x132ff70, C4<0>, C4<0>; +L_0x1325c50 .delay 1 (30000,30000,30000) L_0x1325c50/d; +L_0x1325d10/d .functor AND 1, L_0x132fe10, L_0x132ff70, C4<1>, C4<1>; +L_0x1325d10 .delay 1 (30000,30000,30000) L_0x1325d10/d; +v0x1134ac0_0 .net "a", 0 0, L_0x132fe10; alias, 1 drivers +v0x1134ba0_0 .net "b", 0 0, L_0x132ff70; alias, 1 drivers +v0x1134c60_0 .net "carryout", 0 0, L_0x1325d10; alias, 1 drivers +v0x1134d00_0 .net "sum", 0 0, L_0x1325c50; alias, 1 drivers +S_0x1134e40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1134610; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1325f80/d .functor XOR 1, L_0x1325c50, L_0x1325930, C4<0>, C4<0>; +L_0x1325f80 .delay 1 (30000,30000,30000) L_0x1325f80/d; +L_0x13260d0/d .functor AND 1, L_0x1325c50, L_0x1325930, C4<1>, C4<1>; +L_0x13260d0 .delay 1 (30000,30000,30000) L_0x13260d0/d; +v0x11350a0_0 .net "a", 0 0, L_0x1325c50; alias, 1 drivers +v0x1135140_0 .net "b", 0 0, L_0x1325930; alias, 1 drivers +v0x11351e0_0 .net "carryout", 0 0, L_0x13260d0; alias, 1 drivers +v0x11352b0_0 .net "sum", 0 0, L_0x1325f80; alias, 1 drivers +S_0x1135ad0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1134390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x113aec0_0 .net "ands", 7 0, L_0x132d9b0; 1 drivers +v0x113afd0_0 .net "in", 7 0, L_0x1328220; alias, 1 drivers +v0x113b090_0 .net "out", 0 0, L_0x132f9b0; alias, 1 drivers +v0x113b160_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1135cf0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1135ad0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1138420_0 .net "A", 7 0, L_0x1328220; alias, 1 drivers +v0x1138520_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11385e0_0 .net *"_s0", 0 0, L_0x132c2d0; 1 drivers +v0x11386a0_0 .net *"_s12", 0 0, L_0x132cc40; 1 drivers +v0x1138780_0 .net *"_s16", 0 0, L_0x132cfa0; 1 drivers +v0x11388b0_0 .net *"_s20", 0 0, L_0x132d370; 1 drivers +v0x1138990_0 .net *"_s24", 0 0, L_0x132d6a0; 1 drivers +v0x1138a70_0 .net *"_s28", 0 0, L_0x132d630; 1 drivers +v0x1138b50_0 .net *"_s4", 0 0, L_0x132c620; 1 drivers +v0x1138cc0_0 .net *"_s8", 0 0, L_0x132c930; 1 drivers +v0x1138da0_0 .net "out", 7 0, L_0x132d9b0; alias, 1 drivers +L_0x132c390 .part L_0x1328220, 0, 1; +L_0x132c580 .part v0x127a150_0, 0, 1; +L_0x132c6e0 .part L_0x1328220, 1, 1; +L_0x132c840 .part v0x127a150_0, 1, 1; +L_0x132c9f0 .part L_0x1328220, 2, 1; +L_0x132cb50 .part v0x127a150_0, 2, 1; +L_0x132cd00 .part L_0x1328220, 3, 1; +L_0x132ce60 .part v0x127a150_0, 3, 1; +L_0x132d060 .part L_0x1328220, 4, 1; +L_0x132d2d0 .part v0x127a150_0, 4, 1; +L_0x132d3e0 .part L_0x1328220, 5, 1; +L_0x132d540 .part v0x127a150_0, 5, 1; +L_0x132d760 .part L_0x1328220, 6, 1; +L_0x132d8c0 .part v0x127a150_0, 6, 1; +LS_0x132d9b0_0_0 .concat8 [ 1 1 1 1], L_0x132c2d0, L_0x132c620, L_0x132c930, L_0x132cc40; +LS_0x132d9b0_0_4 .concat8 [ 1 1 1 1], L_0x132cfa0, L_0x132d370, L_0x132d6a0, L_0x132d630; +L_0x132d9b0 .concat8 [ 4 4 0 0], LS_0x132d9b0_0_0, LS_0x132d9b0_0_4; +L_0x132dd70 .part L_0x1328220, 7, 1; +L_0x132df60 .part v0x127a150_0, 7, 1; +S_0x1135f50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x1136160 .param/l "i" 0 4 54, +C4<00>; +L_0x132c2d0/d .functor AND 1, L_0x132c390, L_0x132c580, C4<1>, C4<1>; +L_0x132c2d0 .delay 1 (30000,30000,30000) L_0x132c2d0/d; +v0x1136240_0 .net *"_s0", 0 0, L_0x132c390; 1 drivers +v0x1136320_0 .net *"_s1", 0 0, L_0x132c580; 1 drivers +S_0x1136400 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x1136610 .param/l "i" 0 4 54, +C4<01>; +L_0x132c620/d .functor AND 1, L_0x132c6e0, L_0x132c840, C4<1>, C4<1>; +L_0x132c620 .delay 1 (30000,30000,30000) L_0x132c620/d; +v0x11366d0_0 .net *"_s0", 0 0, L_0x132c6e0; 1 drivers +v0x11367b0_0 .net *"_s1", 0 0, L_0x132c840; 1 drivers +S_0x1136890 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x1136aa0 .param/l "i" 0 4 54, +C4<010>; +L_0x132c930/d .functor AND 1, L_0x132c9f0, L_0x132cb50, C4<1>, C4<1>; +L_0x132c930 .delay 1 (30000,30000,30000) L_0x132c930/d; +v0x1136b40_0 .net *"_s0", 0 0, L_0x132c9f0; 1 drivers +v0x1136c20_0 .net *"_s1", 0 0, L_0x132cb50; 1 drivers +S_0x1136d00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x1136f10 .param/l "i" 0 4 54, +C4<011>; +L_0x132cc40/d .functor AND 1, L_0x132cd00, L_0x132ce60, C4<1>, C4<1>; +L_0x132cc40 .delay 1 (30000,30000,30000) L_0x132cc40/d; +v0x1136fd0_0 .net *"_s0", 0 0, L_0x132cd00; 1 drivers +v0x11370b0_0 .net *"_s1", 0 0, L_0x132ce60; 1 drivers +S_0x1137190 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x11373f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x132cfa0/d .functor AND 1, L_0x132d060, L_0x132d2d0, C4<1>, C4<1>; +L_0x132cfa0 .delay 1 (30000,30000,30000) L_0x132cfa0/d; +v0x11374b0_0 .net *"_s0", 0 0, L_0x132d060; 1 drivers +v0x1137590_0 .net *"_s1", 0 0, L_0x132d2d0; 1 drivers +S_0x1137670 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x1137880 .param/l "i" 0 4 54, +C4<0101>; +L_0x132d370/d .functor AND 1, L_0x132d3e0, L_0x132d540, C4<1>, C4<1>; +L_0x132d370 .delay 1 (30000,30000,30000) L_0x132d370/d; +v0x1137940_0 .net *"_s0", 0 0, L_0x132d3e0; 1 drivers +v0x1137a20_0 .net *"_s1", 0 0, L_0x132d540; 1 drivers +S_0x1137b00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x1137d10 .param/l "i" 0 4 54, +C4<0110>; +L_0x132d6a0/d .functor AND 1, L_0x132d760, L_0x132d8c0, C4<1>, C4<1>; +L_0x132d6a0 .delay 1 (30000,30000,30000) L_0x132d6a0/d; +v0x1137dd0_0 .net *"_s0", 0 0, L_0x132d760; 1 drivers +v0x1137eb0_0 .net *"_s1", 0 0, L_0x132d8c0; 1 drivers +S_0x1137f90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1135cf0; + .timescale -9 -12; +P_0x11381a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x132d630/d .functor AND 1, L_0x132dd70, L_0x132df60, C4<1>, C4<1>; +L_0x132d630 .delay 1 (30000,30000,30000) L_0x132d630/d; +v0x1138260_0 .net *"_s0", 0 0, L_0x132dd70; 1 drivers +v0x1138340_0 .net *"_s1", 0 0, L_0x132df60; 1 drivers +S_0x1138f00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1135ad0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x132f9b0/d .functor OR 1, L_0x132fa70, L_0x132fc20, C4<0>, C4<0>; +L_0x132f9b0 .delay 1 (30000,30000,30000) L_0x132f9b0/d; +v0x113aa50_0 .net *"_s10", 0 0, L_0x132fa70; 1 drivers +v0x113ab30_0 .net *"_s12", 0 0, L_0x132fc20; 1 drivers +v0x113ac10_0 .net "in", 7 0, L_0x132d9b0; alias, 1 drivers +v0x113ace0_0 .net "ors", 1 0, L_0x132f7d0; 1 drivers +v0x113ada0_0 .net "out", 0 0, L_0x132f9b0; alias, 1 drivers +L_0x132eba0 .part L_0x132d9b0, 0, 4; +L_0x132f7d0 .concat8 [ 1 1 0 0], L_0x132e890, L_0x132f4c0; +L_0x132f910 .part L_0x132d9b0, 4, 4; +L_0x132fa70 .part L_0x132f7d0, 0, 1; +L_0x132fc20 .part L_0x132f7d0, 1, 1; +S_0x11390c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1138f00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x132e050/d .functor OR 1, L_0x132e110, L_0x132e270, C4<0>, C4<0>; +L_0x132e050 .delay 1 (30000,30000,30000) L_0x132e050/d; +L_0x132e4a0/d .functor OR 1, L_0x132e5b0, L_0x132e710, C4<0>, C4<0>; +L_0x132e4a0 .delay 1 (30000,30000,30000) L_0x132e4a0/d; +L_0x132e890/d .functor OR 1, L_0x132e900, L_0x132eab0, C4<0>, C4<0>; +L_0x132e890 .delay 1 (30000,30000,30000) L_0x132e890/d; +v0x1139310_0 .net *"_s0", 0 0, L_0x132e050; 1 drivers +v0x1139410_0 .net *"_s10", 0 0, L_0x132e5b0; 1 drivers +v0x11394f0_0 .net *"_s12", 0 0, L_0x132e710; 1 drivers +v0x11395b0_0 .net *"_s14", 0 0, L_0x132e900; 1 drivers +v0x1139690_0 .net *"_s16", 0 0, L_0x132eab0; 1 drivers +v0x11397c0_0 .net *"_s3", 0 0, L_0x132e110; 1 drivers +v0x11398a0_0 .net *"_s5", 0 0, L_0x132e270; 1 drivers +v0x1139980_0 .net *"_s6", 0 0, L_0x132e4a0; 1 drivers +v0x1139a60_0 .net "in", 3 0, L_0x132eba0; 1 drivers +v0x1139bd0_0 .net "ors", 1 0, L_0x132e3b0; 1 drivers +v0x1139cb0_0 .net "out", 0 0, L_0x132e890; 1 drivers +L_0x132e110 .part L_0x132eba0, 0, 1; +L_0x132e270 .part L_0x132eba0, 1, 1; +L_0x132e3b0 .concat8 [ 1 1 0 0], L_0x132e050, L_0x132e4a0; +L_0x132e5b0 .part L_0x132eba0, 2, 1; +L_0x132e710 .part L_0x132eba0, 3, 1; +L_0x132e900 .part L_0x132e3b0, 0, 1; +L_0x132eab0 .part L_0x132e3b0, 1, 1; +S_0x1139dd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1138f00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x132ecd0/d .functor OR 1, L_0x132ed40, L_0x132eea0, C4<0>, C4<0>; +L_0x132ecd0 .delay 1 (30000,30000,30000) L_0x132ecd0/d; +L_0x132f0d0/d .functor OR 1, L_0x132f1e0, L_0x132f340, C4<0>, C4<0>; +L_0x132f0d0 .delay 1 (30000,30000,30000) L_0x132f0d0/d; +L_0x132f4c0/d .functor OR 1, L_0x132f530, L_0x132f6e0, C4<0>, C4<0>; +L_0x132f4c0 .delay 1 (30000,30000,30000) L_0x132f4c0/d; +v0x1139f90_0 .net *"_s0", 0 0, L_0x132ecd0; 1 drivers +v0x113a090_0 .net *"_s10", 0 0, L_0x132f1e0; 1 drivers +v0x113a170_0 .net *"_s12", 0 0, L_0x132f340; 1 drivers +v0x113a230_0 .net *"_s14", 0 0, L_0x132f530; 1 drivers +v0x113a310_0 .net *"_s16", 0 0, L_0x132f6e0; 1 drivers +v0x113a440_0 .net *"_s3", 0 0, L_0x132ed40; 1 drivers +v0x113a520_0 .net *"_s5", 0 0, L_0x132eea0; 1 drivers +v0x113a600_0 .net *"_s6", 0 0, L_0x132f0d0; 1 drivers +v0x113a6e0_0 .net "in", 3 0, L_0x132f910; 1 drivers +v0x113a850_0 .net "ors", 1 0, L_0x132efe0; 1 drivers +v0x113a930_0 .net "out", 0 0, L_0x132f4c0; 1 drivers +L_0x132ed40 .part L_0x132f910, 0, 1; +L_0x132eea0 .part L_0x132f910, 1, 1; +L_0x132efe0 .concat8 [ 1 1 0 0], L_0x132ecd0, L_0x132f0d0; +L_0x132f1e0 .part L_0x132f910, 2, 1; +L_0x132f340 .part L_0x132f910, 3, 1; +L_0x132f530 .part L_0x132efe0, 0, 1; +L_0x132f6e0 .part L_0x132efe0, 1, 1; +S_0x113b240 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1134390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1140670_0 .net "ands", 7 0, L_0x1329f70; 1 drivers +v0x1140780_0 .net "in", 7 0, L_0x1327ee0; alias, 1 drivers +v0x1140840_0 .net "out", 0 0, L_0x132bf70; alias, 1 drivers +v0x1140910_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x113b490 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x113b240; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x113dbd0_0 .net "A", 7 0, L_0x1327ee0; alias, 1 drivers +v0x113dcd0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x113dd90_0 .net *"_s0", 0 0, L_0x1328760; 1 drivers +v0x113de50_0 .net *"_s12", 0 0, L_0x1329120; 1 drivers +v0x113df30_0 .net *"_s16", 0 0, L_0x1329480; 1 drivers +v0x113e060_0 .net *"_s20", 0 0, L_0x13298b0; 1 drivers +v0x113e140_0 .net *"_s24", 0 0, L_0x1329be0; 1 drivers +v0x113e220_0 .net *"_s28", 0 0, L_0x1329b70; 1 drivers +v0x113e300_0 .net *"_s4", 0 0, L_0x1328b00; 1 drivers +v0x113e470_0 .net *"_s8", 0 0, L_0x1328e10; 1 drivers +v0x113e550_0 .net "out", 7 0, L_0x1329f70; alias, 1 drivers +L_0x1328870 .part L_0x1327ee0, 0, 1; +L_0x1328a60 .part v0x127a150_0, 0, 1; +L_0x1328bc0 .part L_0x1327ee0, 1, 1; +L_0x1328d20 .part v0x127a150_0, 1, 1; +L_0x1328ed0 .part L_0x1327ee0, 2, 1; +L_0x1329030 .part v0x127a150_0, 2, 1; +L_0x13291e0 .part L_0x1327ee0, 3, 1; +L_0x1329340 .part v0x127a150_0, 3, 1; +L_0x1329540 .part L_0x1327ee0, 4, 1; +L_0x13297b0 .part v0x127a150_0, 4, 1; +L_0x1329920 .part L_0x1327ee0, 5, 1; +L_0x1329a80 .part v0x127a150_0, 5, 1; +L_0x1329ca0 .part L_0x1327ee0, 6, 1; +L_0x1329e00 .part v0x127a150_0, 6, 1; +LS_0x1329f70_0_0 .concat8 [ 1 1 1 1], L_0x1328760, L_0x1328b00, L_0x1328e10, L_0x1329120; +LS_0x1329f70_0_4 .concat8 [ 1 1 1 1], L_0x1329480, L_0x13298b0, L_0x1329be0, L_0x1329b70; +L_0x1329f70 .concat8 [ 4 4 0 0], LS_0x1329f70_0_0, LS_0x1329f70_0_4; +L_0x132a330 .part L_0x1327ee0, 7, 1; +L_0x132a520 .part v0x127a150_0, 7, 1; +S_0x113b6d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113b8e0 .param/l "i" 0 4 54, +C4<00>; +L_0x1328760/d .functor AND 1, L_0x1328870, L_0x1328a60, C4<1>, C4<1>; +L_0x1328760 .delay 1 (30000,30000,30000) L_0x1328760/d; +v0x113b9c0_0 .net *"_s0", 0 0, L_0x1328870; 1 drivers +v0x113baa0_0 .net *"_s1", 0 0, L_0x1328a60; 1 drivers +S_0x113bb80 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113bd90 .param/l "i" 0 4 54, +C4<01>; +L_0x1328b00/d .functor AND 1, L_0x1328bc0, L_0x1328d20, C4<1>, C4<1>; +L_0x1328b00 .delay 1 (30000,30000,30000) L_0x1328b00/d; +v0x113be50_0 .net *"_s0", 0 0, L_0x1328bc0; 1 drivers +v0x113bf30_0 .net *"_s1", 0 0, L_0x1328d20; 1 drivers +S_0x113c010 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113c250 .param/l "i" 0 4 54, +C4<010>; +L_0x1328e10/d .functor AND 1, L_0x1328ed0, L_0x1329030, C4<1>, C4<1>; +L_0x1328e10 .delay 1 (30000,30000,30000) L_0x1328e10/d; +v0x113c2f0_0 .net *"_s0", 0 0, L_0x1328ed0; 1 drivers +v0x113c3d0_0 .net *"_s1", 0 0, L_0x1329030; 1 drivers +S_0x113c4b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113c6c0 .param/l "i" 0 4 54, +C4<011>; +L_0x1329120/d .functor AND 1, L_0x13291e0, L_0x1329340, C4<1>, C4<1>; +L_0x1329120 .delay 1 (30000,30000,30000) L_0x1329120/d; +v0x113c780_0 .net *"_s0", 0 0, L_0x13291e0; 1 drivers +v0x113c860_0 .net *"_s1", 0 0, L_0x1329340; 1 drivers +S_0x113c940 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113cba0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1329480/d .functor AND 1, L_0x1329540, L_0x13297b0, C4<1>, C4<1>; +L_0x1329480 .delay 1 (30000,30000,30000) L_0x1329480/d; +v0x113cc60_0 .net *"_s0", 0 0, L_0x1329540; 1 drivers +v0x113cd40_0 .net *"_s1", 0 0, L_0x13297b0; 1 drivers +S_0x113ce20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113d030 .param/l "i" 0 4 54, +C4<0101>; +L_0x13298b0/d .functor AND 1, L_0x1329920, L_0x1329a80, C4<1>, C4<1>; +L_0x13298b0 .delay 1 (30000,30000,30000) L_0x13298b0/d; +v0x113d0f0_0 .net *"_s0", 0 0, L_0x1329920; 1 drivers +v0x113d1d0_0 .net *"_s1", 0 0, L_0x1329a80; 1 drivers +S_0x113d2b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113d4c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1329be0/d .functor AND 1, L_0x1329ca0, L_0x1329e00, C4<1>, C4<1>; +L_0x1329be0 .delay 1 (30000,30000,30000) L_0x1329be0/d; +v0x113d580_0 .net *"_s0", 0 0, L_0x1329ca0; 1 drivers +v0x113d660_0 .net *"_s1", 0 0, L_0x1329e00; 1 drivers +S_0x113d740 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x113b490; + .timescale -9 -12; +P_0x113d950 .param/l "i" 0 4 54, +C4<0111>; +L_0x1329b70/d .functor AND 1, L_0x132a330, L_0x132a520, C4<1>, C4<1>; +L_0x1329b70 .delay 1 (30000,30000,30000) L_0x1329b70/d; +v0x113da10_0 .net *"_s0", 0 0, L_0x132a330; 1 drivers +v0x113daf0_0 .net *"_s1", 0 0, L_0x132a520; 1 drivers +S_0x113e6b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x113b240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x132bf70/d .functor OR 1, L_0x132c030, L_0x132c1e0, C4<0>, C4<0>; +L_0x132bf70 .delay 1 (30000,30000,30000) L_0x132bf70/d; +v0x1140200_0 .net *"_s10", 0 0, L_0x132c030; 1 drivers +v0x11402e0_0 .net *"_s12", 0 0, L_0x132c1e0; 1 drivers +v0x11403c0_0 .net "in", 7 0, L_0x1329f70; alias, 1 drivers +v0x1140490_0 .net "ors", 1 0, L_0x132bd90; 1 drivers +v0x1140550_0 .net "out", 0 0, L_0x132bf70; alias, 1 drivers +L_0x132b160 .part L_0x1329f70, 0, 4; +L_0x132bd90 .concat8 [ 1 1 0 0], L_0x132ae50, L_0x132ba80; +L_0x132bed0 .part L_0x1329f70, 4, 4; +L_0x132c030 .part L_0x132bd90, 0, 1; +L_0x132c1e0 .part L_0x132bd90, 1, 1; +S_0x113e870 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x113e6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x132a610/d .functor OR 1, L_0x132a6d0, L_0x132a830, C4<0>, C4<0>; +L_0x132a610 .delay 1 (30000,30000,30000) L_0x132a610/d; +L_0x132aa60/d .functor OR 1, L_0x132ab70, L_0x132acd0, C4<0>, C4<0>; +L_0x132aa60 .delay 1 (30000,30000,30000) L_0x132aa60/d; +L_0x132ae50/d .functor OR 1, L_0x132aec0, L_0x132b070, C4<0>, C4<0>; +L_0x132ae50 .delay 1 (30000,30000,30000) L_0x132ae50/d; +v0x113eac0_0 .net *"_s0", 0 0, L_0x132a610; 1 drivers +v0x113ebc0_0 .net *"_s10", 0 0, L_0x132ab70; 1 drivers +v0x113eca0_0 .net *"_s12", 0 0, L_0x132acd0; 1 drivers +v0x113ed60_0 .net *"_s14", 0 0, L_0x132aec0; 1 drivers +v0x113ee40_0 .net *"_s16", 0 0, L_0x132b070; 1 drivers +v0x113ef70_0 .net *"_s3", 0 0, L_0x132a6d0; 1 drivers +v0x113f050_0 .net *"_s5", 0 0, L_0x132a830; 1 drivers +v0x113f130_0 .net *"_s6", 0 0, L_0x132aa60; 1 drivers +v0x113f210_0 .net "in", 3 0, L_0x132b160; 1 drivers +v0x113f380_0 .net "ors", 1 0, L_0x132a970; 1 drivers +v0x113f460_0 .net "out", 0 0, L_0x132ae50; 1 drivers +L_0x132a6d0 .part L_0x132b160, 0, 1; +L_0x132a830 .part L_0x132b160, 1, 1; +L_0x132a970 .concat8 [ 1 1 0 0], L_0x132a610, L_0x132aa60; +L_0x132ab70 .part L_0x132b160, 2, 1; +L_0x132acd0 .part L_0x132b160, 3, 1; +L_0x132aec0 .part L_0x132a970, 0, 1; +L_0x132b070 .part L_0x132a970, 1, 1; +S_0x113f580 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x113e6b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x132b290/d .functor OR 1, L_0x132b300, L_0x132b460, C4<0>, C4<0>; +L_0x132b290 .delay 1 (30000,30000,30000) L_0x132b290/d; +L_0x132b690/d .functor OR 1, L_0x132b7a0, L_0x132b900, C4<0>, C4<0>; +L_0x132b690 .delay 1 (30000,30000,30000) L_0x132b690/d; +L_0x132ba80/d .functor OR 1, L_0x132baf0, L_0x132bca0, C4<0>, C4<0>; +L_0x132ba80 .delay 1 (30000,30000,30000) L_0x132ba80/d; +v0x113f740_0 .net *"_s0", 0 0, L_0x132b290; 1 drivers +v0x113f840_0 .net *"_s10", 0 0, L_0x132b7a0; 1 drivers +v0x113f920_0 .net *"_s12", 0 0, L_0x132b900; 1 drivers +v0x113f9e0_0 .net *"_s14", 0 0, L_0x132baf0; 1 drivers +v0x113fac0_0 .net *"_s16", 0 0, L_0x132bca0; 1 drivers +v0x113fbf0_0 .net *"_s3", 0 0, L_0x132b300; 1 drivers +v0x113fcd0_0 .net *"_s5", 0 0, L_0x132b460; 1 drivers +v0x113fdb0_0 .net *"_s6", 0 0, L_0x132b690; 1 drivers +v0x113fe90_0 .net "in", 3 0, L_0x132bed0; 1 drivers +v0x1140000_0 .net "ors", 1 0, L_0x132b5a0; 1 drivers +v0x11400e0_0 .net "out", 0 0, L_0x132ba80; 1 drivers +L_0x132b300 .part L_0x132bed0, 0, 1; +L_0x132b460 .part L_0x132bed0, 1, 1; +L_0x132b5a0 .concat8 [ 1 1 0 0], L_0x132b290, L_0x132b690; +L_0x132b7a0 .part L_0x132bed0, 2, 1; +L_0x132b900 .part L_0x132bed0, 3, 1; +L_0x132baf0 .part L_0x132b5a0, 0, 1; +L_0x132bca0 .part L_0x132b5a0, 1, 1; +S_0x11409f0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1134390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1326d70/d .functor XNOR 1, L_0x132fe10, L_0x132ff70, C4<0>, C4<0>; +L_0x1326d70 .delay 1 (20000,20000,20000) L_0x1326d70/d; +L_0x1326ef0/d .functor AND 1, L_0x132fe10, L_0x1325ac0, C4<1>, C4<1>; +L_0x1326ef0 .delay 1 (30000,30000,30000) L_0x1326ef0/d; +L_0x1326fb0/d .functor AND 1, L_0x1326d70, L_0x1325930, C4<1>, C4<1>; +L_0x1326fb0 .delay 1 (30000,30000,30000) L_0x1326fb0/d; +L_0x1327110/d .functor OR 1, L_0x1326fb0, L_0x1326ef0, C4<0>, C4<0>; +L_0x1327110 .delay 1 (30000,30000,30000) L_0x1327110/d; +v0x1140ca0_0 .net "a", 0 0, L_0x132fe10; alias, 1 drivers +v0x1140d90_0 .net "a_", 0 0, L_0x12d0df0; alias, 1 drivers +v0x1140e50_0 .net "b", 0 0, L_0x132ff70; alias, 1 drivers +v0x1140f40_0 .net "b_", 0 0, L_0x1325ac0; alias, 1 drivers +v0x1140fe0_0 .net "carryin", 0 0, L_0x1325930; alias, 1 drivers +v0x1141120_0 .net "eq", 0 0, L_0x1326d70; 1 drivers +v0x11411e0_0 .net "lt", 0 0, L_0x1326ef0; 1 drivers +v0x11412a0_0 .net "out", 0 0, L_0x1327110; 1 drivers +v0x1141360_0 .net "w0", 0 0, L_0x1326fb0; 1 drivers +S_0x11415b0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1134390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1326950/d .functor OR 1, L_0x1326450, L_0x1142810, C4<0>, C4<0>; +L_0x1326950 .delay 1 (30000,30000,30000) L_0x1326950/d; +v0x11423a0_0 .net "a", 0 0, L_0x132fe10; alias, 1 drivers +v0x11424f0_0 .net "b", 0 0, L_0x1325ac0; alias, 1 drivers +v0x11425b0_0 .net "c1", 0 0, L_0x1326450; 1 drivers +v0x1142650_0 .net "c2", 0 0, L_0x1142810; 1 drivers +v0x1142720_0 .net "carryin", 0 0, L_0x1325930; alias, 1 drivers +v0x11428a0_0 .net "carryout", 0 0, L_0x1326950; 1 drivers +v0x1142940_0 .net "s1", 0 0, L_0x1326390; 1 drivers +v0x11429e0_0 .net "sum", 0 0, L_0x13265b0; 1 drivers +S_0x1141800 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11415b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1326390/d .functor XOR 1, L_0x132fe10, L_0x1325ac0, C4<0>, C4<0>; +L_0x1326390 .delay 1 (30000,30000,30000) L_0x1326390/d; +L_0x1326450/d .functor AND 1, L_0x132fe10, L_0x1325ac0, C4<1>, C4<1>; +L_0x1326450 .delay 1 (30000,30000,30000) L_0x1326450/d; +v0x1141a60_0 .net "a", 0 0, L_0x132fe10; alias, 1 drivers +v0x1141b20_0 .net "b", 0 0, L_0x1325ac0; alias, 1 drivers +v0x1141be0_0 .net "carryout", 0 0, L_0x1326450; alias, 1 drivers +v0x1141c80_0 .net "sum", 0 0, L_0x1326390; alias, 1 drivers +S_0x1141db0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11415b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13265b0/d .functor XOR 1, L_0x1326390, L_0x1325930, C4<0>, C4<0>; +L_0x13265b0 .delay 1 (30000,30000,30000) L_0x13265b0/d; +L_0x1142810/d .functor AND 1, L_0x1326390, L_0x1325930, C4<1>, C4<1>; +L_0x1142810 .delay 1 (30000,30000,30000) L_0x1142810/d; +v0x1142010_0 .net "a", 0 0, L_0x1326390; alias, 1 drivers +v0x11420e0_0 .net "b", 0 0, L_0x1325930; alias, 1 drivers +v0x1142180_0 .net "carryout", 0 0, L_0x1142810; alias, 1 drivers +v0x1142250_0 .net "sum", 0 0, L_0x13265b0; alias, 1 drivers +S_0x1144a70 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1134020; + .timescale -9 -12; +L_0x2ac4328871e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887230 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1325f10/d .functor OR 1, L_0x2ac4328871e8, L_0x2ac432887230, C4<0>, C4<0>; +L_0x1325f10 .delay 1 (30000,30000,30000) L_0x1325f10/d; +v0x1144c60_0 .net/2u *"_s0", 0 0, L_0x2ac4328871e8; 1 drivers +v0x1144d40_0 .net/2u *"_s2", 0 0, L_0x2ac432887230; 1 drivers +S_0x1144e20 .scope generate, "alu_slices[17]" "alu_slices[17]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1145030 .param/l "i" 0 3 39, +C4<010001>; +S_0x11450f0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1144e20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13301b0/d .functor NOT 1, L_0x133a620, C4<0>, C4<0>, C4<0>; +L_0x13301b0 .delay 1 (10000,10000,10000) L_0x13301b0/d; +L_0x1330270/d .functor NOT 1, L_0x1330010, C4<0>, C4<0>, C4<0>; +L_0x1330270 .delay 1 (10000,10000,10000) L_0x1330270/d; +L_0x1331270/d .functor XOR 1, L_0x133a620, L_0x1330010, C4<0>, C4<0>; +L_0x1331270 .delay 1 (30000,30000,30000) L_0x1331270/d; +L_0x2ac432887278 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328872c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1331330/d .functor OR 1, L_0x2ac432887278, L_0x2ac4328872c0, C4<0>, C4<0>; +L_0x1331330 .delay 1 (30000,30000,30000) L_0x1331330/d; +L_0x2ac432887308 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887350 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1331ad0/d .functor OR 1, L_0x2ac432887308, L_0x2ac432887350, C4<0>, C4<0>; +L_0x1331ad0 .delay 1 (30000,30000,30000) L_0x1331ad0/d; +L_0x1331cd0/d .functor AND 1, L_0x133a620, L_0x1330010, C4<1>, C4<1>; +L_0x1331cd0 .delay 1 (30000,30000,30000) L_0x1331cd0/d; +L_0x2ac432887398 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328873e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1331d90/d .functor OR 1, L_0x2ac432887398, L_0x2ac4328873e0, C4<0>, C4<0>; +L_0x1331d90 .delay 1 (30000,30000,30000) L_0x1331d90/d; +L_0x1331f90/d .functor NAND 1, L_0x133a620, L_0x1330010, C4<1>, C4<1>; +L_0x1331f90 .delay 1 (20000,20000,20000) L_0x1331f90/d; +L_0x2ac432887428 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887470 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13320a0/d .functor OR 1, L_0x2ac432887428, L_0x2ac432887470, C4<0>, C4<0>; +L_0x13320a0 .delay 1 (30000,30000,30000) L_0x13320a0/d; +L_0x1332250/d .functor NOR 1, L_0x133a620, L_0x1330010, C4<0>, C4<0>; +L_0x1332250 .delay 1 (20000,20000,20000) L_0x1332250/d; +L_0x2ac4328874b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887500 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1332520/d .functor OR 1, L_0x2ac4328874b8, L_0x2ac432887500, C4<0>, C4<0>; +L_0x1332520 .delay 1 (30000,30000,30000) L_0x1332520/d; +L_0x1332920/d .functor OR 1, L_0x133a620, L_0x1330010, C4<0>, C4<0>; +L_0x1332920 .delay 1 (30000,30000,30000) L_0x1332920/d; +L_0x2ac432887548 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887590 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1332dc0/d .functor OR 1, L_0x2ac432887548, L_0x2ac432887590, C4<0>, C4<0>; +L_0x1332dc0 .delay 1 (30000,30000,30000) L_0x1332dc0/d; +L_0x133a520/d .functor NOT 1, L_0x1336780, C4<0>, C4<0>, C4<0>; +L_0x133a520 .delay 1 (10000,10000,10000) L_0x133a520/d; +v0x1153820_0 .net "A", 0 0, L_0x133a620; 1 drivers +v0x11538e0_0 .net "A_", 0 0, L_0x13301b0; 1 drivers +v0x11539a0_0 .net "B", 0 0, L_0x1330010; 1 drivers +v0x1153a70_0 .net "B_", 0 0, L_0x1330270; 1 drivers +v0x1153b10_0 .net *"_s11", 0 0, L_0x1331330; 1 drivers +v0x1153c00_0 .net/2s *"_s13", 0 0, L_0x2ac432887278; 1 drivers +v0x1153cc0_0 .net/2s *"_s15", 0 0, L_0x2ac4328872c0; 1 drivers +v0x1153da0_0 .net *"_s19", 0 0, L_0x1331ad0; 1 drivers +v0x1153e80_0 .net/2s *"_s21", 0 0, L_0x2ac432887308; 1 drivers +v0x1153ff0_0 .net/2s *"_s23", 0 0, L_0x2ac432887350; 1 drivers +v0x11540d0_0 .net *"_s25", 0 0, L_0x1331cd0; 1 drivers +v0x11541b0_0 .net *"_s28", 0 0, L_0x1331d90; 1 drivers +v0x1154290_0 .net/2s *"_s30", 0 0, L_0x2ac432887398; 1 drivers +v0x1154370_0 .net/2s *"_s32", 0 0, L_0x2ac4328873e0; 1 drivers +v0x1154450_0 .net *"_s34", 0 0, L_0x1331f90; 1 drivers +v0x1154530_0 .net *"_s37", 0 0, L_0x13320a0; 1 drivers +v0x1154610_0 .net/2s *"_s39", 0 0, L_0x2ac432887428; 1 drivers +v0x11547c0_0 .net/2s *"_s41", 0 0, L_0x2ac432887470; 1 drivers +v0x1154860_0 .net *"_s43", 0 0, L_0x1332250; 1 drivers +v0x1154940_0 .net *"_s46", 0 0, L_0x1332520; 1 drivers +v0x1154a20_0 .net/2s *"_s48", 0 0, L_0x2ac4328874b8; 1 drivers +v0x1154b00_0 .net/2s *"_s50", 0 0, L_0x2ac432887500; 1 drivers +v0x1154be0_0 .net *"_s52", 0 0, L_0x1332920; 1 drivers +v0x1154cc0_0 .net *"_s56", 0 0, L_0x1332dc0; 1 drivers +v0x1154da0_0 .net/2s *"_s59", 0 0, L_0x2ac432887548; 1 drivers +v0x1154e80_0 .net/2s *"_s61", 0 0, L_0x2ac432887590; 1 drivers +v0x1154f60_0 .net *"_s8", 0 0, L_0x1331270; 1 drivers +v0x1155040_0 .net "carryin", 0 0, L_0x13300b0; 1 drivers +v0x11550e0_0 .net "carryout", 0 0, L_0x133a1c0; 1 drivers +v0x1155180_0 .net "carryouts", 7 0, L_0x1332a30; 1 drivers +v0x1155290_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1155350_0 .net "result", 0 0, L_0x1336780; 1 drivers +v0x1155440_0 .net "results", 7 0, L_0x13326f0; 1 drivers +v0x1154720_0 .net "zero", 0 0, L_0x133a520; 1 drivers +LS_0x13326f0_0_0 .concat8 [ 1 1 1 1], L_0x1330790, L_0x1330dc0, L_0x1331270, L_0x1331ad0; +LS_0x13326f0_0_4 .concat8 [ 1 1 1 1], L_0x1331cd0, L_0x1331f90, L_0x1332250, L_0x1332920; +L_0x13326f0 .concat8 [ 4 4 0 0], LS_0x13326f0_0_0, LS_0x13326f0_0_4; +LS_0x1332a30_0_0 .concat8 [ 1 1 1 1], L_0x1330a40, L_0x1331110, L_0x1331330, L_0x1331920; +LS_0x1332a30_0_4 .concat8 [ 1 1 1 1], L_0x1331d90, L_0x13320a0, L_0x1332520, L_0x1332dc0; +L_0x1332a30 .concat8 [ 4 4 0 0], LS_0x1332a30_0_0, LS_0x1332a30_0_4; +S_0x1145370 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11450f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1330a40/d .functor OR 1, L_0x1330520, L_0x13308e0, C4<0>, C4<0>; +L_0x1330a40 .delay 1 (30000,30000,30000) L_0x1330a40/d; +v0x11461a0_0 .net "a", 0 0, L_0x133a620; alias, 1 drivers +v0x1146260_0 .net "b", 0 0, L_0x1330010; alias, 1 drivers +v0x1146330_0 .net "c1", 0 0, L_0x1330520; 1 drivers +v0x1146430_0 .net "c2", 0 0, L_0x13308e0; 1 drivers +v0x1146500_0 .net "carryin", 0 0, L_0x13300b0; alias, 1 drivers +v0x11465f0_0 .net "carryout", 0 0, L_0x1330a40; 1 drivers +v0x1146690_0 .net "s1", 0 0, L_0x1330460; 1 drivers +v0x1146780_0 .net "sum", 0 0, L_0x1330790; 1 drivers +S_0x11455e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1145370; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1330460/d .functor XOR 1, L_0x133a620, L_0x1330010, C4<0>, C4<0>; +L_0x1330460 .delay 1 (30000,30000,30000) L_0x1330460/d; +L_0x1330520/d .functor AND 1, L_0x133a620, L_0x1330010, C4<1>, C4<1>; +L_0x1330520 .delay 1 (30000,30000,30000) L_0x1330520/d; +v0x1145840_0 .net "a", 0 0, L_0x133a620; alias, 1 drivers +v0x1145920_0 .net "b", 0 0, L_0x1330010; alias, 1 drivers +v0x11459e0_0 .net "carryout", 0 0, L_0x1330520; alias, 1 drivers +v0x1145a80_0 .net "sum", 0 0, L_0x1330460; alias, 1 drivers +S_0x1145bc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1145370; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1330790/d .functor XOR 1, L_0x1330460, L_0x13300b0, C4<0>, C4<0>; +L_0x1330790 .delay 1 (30000,30000,30000) L_0x1330790/d; +L_0x13308e0/d .functor AND 1, L_0x1330460, L_0x13300b0, C4<1>, C4<1>; +L_0x13308e0 .delay 1 (30000,30000,30000) L_0x13308e0/d; +v0x1145e20_0 .net "a", 0 0, L_0x1330460; alias, 1 drivers +v0x1145ec0_0 .net "b", 0 0, L_0x13300b0; alias, 1 drivers +v0x1145f60_0 .net "carryout", 0 0, L_0x13308e0; alias, 1 drivers +v0x1146030_0 .net "sum", 0 0, L_0x1330790; alias, 1 drivers +S_0x1146850 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11450f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x114bc40_0 .net "ands", 7 0, L_0x13381c0; 1 drivers +v0x114bd50_0 .net "in", 7 0, L_0x1332a30; alias, 1 drivers +v0x114be10_0 .net "out", 0 0, L_0x133a1c0; alias, 1 drivers +v0x114bee0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1146a70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1146850; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11491a0_0 .net "A", 7 0, L_0x1332a30; alias, 1 drivers +v0x11492a0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1149360_0 .net *"_s0", 0 0, L_0x1336ae0; 1 drivers +v0x1149420_0 .net *"_s12", 0 0, L_0x1337450; 1 drivers +v0x1149500_0 .net *"_s16", 0 0, L_0x13377b0; 1 drivers +v0x1149630_0 .net *"_s20", 0 0, L_0x1337b80; 1 drivers +v0x1149710_0 .net *"_s24", 0 0, L_0x1337eb0; 1 drivers +v0x11497f0_0 .net *"_s28", 0 0, L_0x1337e40; 1 drivers +v0x11498d0_0 .net *"_s4", 0 0, L_0x1336e30; 1 drivers +v0x1149a40_0 .net *"_s8", 0 0, L_0x1337140; 1 drivers +v0x1149b20_0 .net "out", 7 0, L_0x13381c0; alias, 1 drivers +L_0x1336ba0 .part L_0x1332a30, 0, 1; +L_0x1336d90 .part v0x127a150_0, 0, 1; +L_0x1336ef0 .part L_0x1332a30, 1, 1; +L_0x1337050 .part v0x127a150_0, 1, 1; +L_0x1337200 .part L_0x1332a30, 2, 1; +L_0x1337360 .part v0x127a150_0, 2, 1; +L_0x1337510 .part L_0x1332a30, 3, 1; +L_0x1337670 .part v0x127a150_0, 3, 1; +L_0x1337870 .part L_0x1332a30, 4, 1; +L_0x1337ae0 .part v0x127a150_0, 4, 1; +L_0x1337bf0 .part L_0x1332a30, 5, 1; +L_0x1337d50 .part v0x127a150_0, 5, 1; +L_0x1337f70 .part L_0x1332a30, 6, 1; +L_0x13380d0 .part v0x127a150_0, 6, 1; +LS_0x13381c0_0_0 .concat8 [ 1 1 1 1], L_0x1336ae0, L_0x1336e30, L_0x1337140, L_0x1337450; +LS_0x13381c0_0_4 .concat8 [ 1 1 1 1], L_0x13377b0, L_0x1337b80, L_0x1337eb0, L_0x1337e40; +L_0x13381c0 .concat8 [ 4 4 0 0], LS_0x13381c0_0_0, LS_0x13381c0_0_4; +L_0x1338580 .part L_0x1332a30, 7, 1; +L_0x1338770 .part v0x127a150_0, 7, 1; +S_0x1146cd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1146ee0 .param/l "i" 0 4 54, +C4<00>; +L_0x1336ae0/d .functor AND 1, L_0x1336ba0, L_0x1336d90, C4<1>, C4<1>; +L_0x1336ae0 .delay 1 (30000,30000,30000) L_0x1336ae0/d; +v0x1146fc0_0 .net *"_s0", 0 0, L_0x1336ba0; 1 drivers +v0x11470a0_0 .net *"_s1", 0 0, L_0x1336d90; 1 drivers +S_0x1147180 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1147390 .param/l "i" 0 4 54, +C4<01>; +L_0x1336e30/d .functor AND 1, L_0x1336ef0, L_0x1337050, C4<1>, C4<1>; +L_0x1336e30 .delay 1 (30000,30000,30000) L_0x1336e30/d; +v0x1147450_0 .net *"_s0", 0 0, L_0x1336ef0; 1 drivers +v0x1147530_0 .net *"_s1", 0 0, L_0x1337050; 1 drivers +S_0x1147610 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1147820 .param/l "i" 0 4 54, +C4<010>; +L_0x1337140/d .functor AND 1, L_0x1337200, L_0x1337360, C4<1>, C4<1>; +L_0x1337140 .delay 1 (30000,30000,30000) L_0x1337140/d; +v0x11478c0_0 .net *"_s0", 0 0, L_0x1337200; 1 drivers +v0x11479a0_0 .net *"_s1", 0 0, L_0x1337360; 1 drivers +S_0x1147a80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1147c90 .param/l "i" 0 4 54, +C4<011>; +L_0x1337450/d .functor AND 1, L_0x1337510, L_0x1337670, C4<1>, C4<1>; +L_0x1337450 .delay 1 (30000,30000,30000) L_0x1337450/d; +v0x1147d50_0 .net *"_s0", 0 0, L_0x1337510; 1 drivers +v0x1147e30_0 .net *"_s1", 0 0, L_0x1337670; 1 drivers +S_0x1147f10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1148170 .param/l "i" 0 4 54, +C4<0100>; +L_0x13377b0/d .functor AND 1, L_0x1337870, L_0x1337ae0, C4<1>, C4<1>; +L_0x13377b0 .delay 1 (30000,30000,30000) L_0x13377b0/d; +v0x1148230_0 .net *"_s0", 0 0, L_0x1337870; 1 drivers +v0x1148310_0 .net *"_s1", 0 0, L_0x1337ae0; 1 drivers +S_0x11483f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1148600 .param/l "i" 0 4 54, +C4<0101>; +L_0x1337b80/d .functor AND 1, L_0x1337bf0, L_0x1337d50, C4<1>, C4<1>; +L_0x1337b80 .delay 1 (30000,30000,30000) L_0x1337b80/d; +v0x11486c0_0 .net *"_s0", 0 0, L_0x1337bf0; 1 drivers +v0x11487a0_0 .net *"_s1", 0 0, L_0x1337d50; 1 drivers +S_0x1148880 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1148a90 .param/l "i" 0 4 54, +C4<0110>; +L_0x1337eb0/d .functor AND 1, L_0x1337f70, L_0x13380d0, C4<1>, C4<1>; +L_0x1337eb0 .delay 1 (30000,30000,30000) L_0x1337eb0/d; +v0x1148b50_0 .net *"_s0", 0 0, L_0x1337f70; 1 drivers +v0x1148c30_0 .net *"_s1", 0 0, L_0x13380d0; 1 drivers +S_0x1148d10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1146a70; + .timescale -9 -12; +P_0x1148f20 .param/l "i" 0 4 54, +C4<0111>; +L_0x1337e40/d .functor AND 1, L_0x1338580, L_0x1338770, C4<1>, C4<1>; +L_0x1337e40 .delay 1 (30000,30000,30000) L_0x1337e40/d; +v0x1148fe0_0 .net *"_s0", 0 0, L_0x1338580; 1 drivers +v0x11490c0_0 .net *"_s1", 0 0, L_0x1338770; 1 drivers +S_0x1149c80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1146850; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x133a1c0/d .functor OR 1, L_0x133a280, L_0x133a430, C4<0>, C4<0>; +L_0x133a1c0 .delay 1 (30000,30000,30000) L_0x133a1c0/d; +v0x114b7d0_0 .net *"_s10", 0 0, L_0x133a280; 1 drivers +v0x114b8b0_0 .net *"_s12", 0 0, L_0x133a430; 1 drivers +v0x114b990_0 .net "in", 7 0, L_0x13381c0; alias, 1 drivers +v0x114ba60_0 .net "ors", 1 0, L_0x1339fe0; 1 drivers +v0x114bb20_0 .net "out", 0 0, L_0x133a1c0; alias, 1 drivers +L_0x13393b0 .part L_0x13381c0, 0, 4; +L_0x1339fe0 .concat8 [ 1 1 0 0], L_0x13390a0, L_0x1339cd0; +L_0x133a120 .part L_0x13381c0, 4, 4; +L_0x133a280 .part L_0x1339fe0, 0, 1; +L_0x133a430 .part L_0x1339fe0, 1, 1; +S_0x1149e40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1149c80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1338860/d .functor OR 1, L_0x1338920, L_0x1338a80, C4<0>, C4<0>; +L_0x1338860 .delay 1 (30000,30000,30000) L_0x1338860/d; +L_0x1338cb0/d .functor OR 1, L_0x1338dc0, L_0x1338f20, C4<0>, C4<0>; +L_0x1338cb0 .delay 1 (30000,30000,30000) L_0x1338cb0/d; +L_0x13390a0/d .functor OR 1, L_0x1339110, L_0x13392c0, C4<0>, C4<0>; +L_0x13390a0 .delay 1 (30000,30000,30000) L_0x13390a0/d; +v0x114a090_0 .net *"_s0", 0 0, L_0x1338860; 1 drivers +v0x114a190_0 .net *"_s10", 0 0, L_0x1338dc0; 1 drivers +v0x114a270_0 .net *"_s12", 0 0, L_0x1338f20; 1 drivers +v0x114a330_0 .net *"_s14", 0 0, L_0x1339110; 1 drivers +v0x114a410_0 .net *"_s16", 0 0, L_0x13392c0; 1 drivers +v0x114a540_0 .net *"_s3", 0 0, L_0x1338920; 1 drivers +v0x114a620_0 .net *"_s5", 0 0, L_0x1338a80; 1 drivers +v0x114a700_0 .net *"_s6", 0 0, L_0x1338cb0; 1 drivers +v0x114a7e0_0 .net "in", 3 0, L_0x13393b0; 1 drivers +v0x114a950_0 .net "ors", 1 0, L_0x1338bc0; 1 drivers +v0x114aa30_0 .net "out", 0 0, L_0x13390a0; 1 drivers +L_0x1338920 .part L_0x13393b0, 0, 1; +L_0x1338a80 .part L_0x13393b0, 1, 1; +L_0x1338bc0 .concat8 [ 1 1 0 0], L_0x1338860, L_0x1338cb0; +L_0x1338dc0 .part L_0x13393b0, 2, 1; +L_0x1338f20 .part L_0x13393b0, 3, 1; +L_0x1339110 .part L_0x1338bc0, 0, 1; +L_0x13392c0 .part L_0x1338bc0, 1, 1; +S_0x114ab50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1149c80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13394e0/d .functor OR 1, L_0x1339550, L_0x13396b0, C4<0>, C4<0>; +L_0x13394e0 .delay 1 (30000,30000,30000) L_0x13394e0/d; +L_0x13398e0/d .functor OR 1, L_0x13399f0, L_0x1339b50, C4<0>, C4<0>; +L_0x13398e0 .delay 1 (30000,30000,30000) L_0x13398e0/d; +L_0x1339cd0/d .functor OR 1, L_0x1339d40, L_0x1339ef0, C4<0>, C4<0>; +L_0x1339cd0 .delay 1 (30000,30000,30000) L_0x1339cd0/d; +v0x114ad10_0 .net *"_s0", 0 0, L_0x13394e0; 1 drivers +v0x114ae10_0 .net *"_s10", 0 0, L_0x13399f0; 1 drivers +v0x114aef0_0 .net *"_s12", 0 0, L_0x1339b50; 1 drivers +v0x114afb0_0 .net *"_s14", 0 0, L_0x1339d40; 1 drivers +v0x114b090_0 .net *"_s16", 0 0, L_0x1339ef0; 1 drivers +v0x114b1c0_0 .net *"_s3", 0 0, L_0x1339550; 1 drivers +v0x114b2a0_0 .net *"_s5", 0 0, L_0x13396b0; 1 drivers +v0x114b380_0 .net *"_s6", 0 0, L_0x13398e0; 1 drivers +v0x114b460_0 .net "in", 3 0, L_0x133a120; 1 drivers +v0x114b5d0_0 .net "ors", 1 0, L_0x13397f0; 1 drivers +v0x114b6b0_0 .net "out", 0 0, L_0x1339cd0; 1 drivers +L_0x1339550 .part L_0x133a120, 0, 1; +L_0x13396b0 .part L_0x133a120, 1, 1; +L_0x13397f0 .concat8 [ 1 1 0 0], L_0x13394e0, L_0x13398e0; +L_0x13399f0 .part L_0x133a120, 2, 1; +L_0x1339b50 .part L_0x133a120, 3, 1; +L_0x1339d40 .part L_0x13397f0, 0, 1; +L_0x1339ef0 .part L_0x13397f0, 1, 1; +S_0x114bfc0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11450f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11513f0_0 .net "ands", 7 0, L_0x1334780; 1 drivers +v0x1151500_0 .net "in", 7 0, L_0x13326f0; alias, 1 drivers +v0x11515c0_0 .net "out", 0 0, L_0x1336780; alias, 1 drivers +v0x1151690_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x114c210 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x114bfc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x114e950_0 .net "A", 7 0, L_0x13326f0; alias, 1 drivers +v0x114ea50_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x114eb10_0 .net *"_s0", 0 0, L_0x1332f70; 1 drivers +v0x114ebd0_0 .net *"_s12", 0 0, L_0x1333930; 1 drivers +v0x114ecb0_0 .net *"_s16", 0 0, L_0x1333c90; 1 drivers +v0x114ede0_0 .net *"_s20", 0 0, L_0x13340c0; 1 drivers +v0x114eec0_0 .net *"_s24", 0 0, L_0x13343f0; 1 drivers +v0x114efa0_0 .net *"_s28", 0 0, L_0x1334380; 1 drivers +v0x114f080_0 .net *"_s4", 0 0, L_0x1333310; 1 drivers +v0x114f1f0_0 .net *"_s8", 0 0, L_0x1333620; 1 drivers +v0x114f2d0_0 .net "out", 7 0, L_0x1334780; alias, 1 drivers +L_0x1333080 .part L_0x13326f0, 0, 1; +L_0x1333270 .part v0x127a150_0, 0, 1; +L_0x13333d0 .part L_0x13326f0, 1, 1; +L_0x1333530 .part v0x127a150_0, 1, 1; +L_0x13336e0 .part L_0x13326f0, 2, 1; +L_0x1333840 .part v0x127a150_0, 2, 1; +L_0x13339f0 .part L_0x13326f0, 3, 1; +L_0x1333b50 .part v0x127a150_0, 3, 1; +L_0x1333d50 .part L_0x13326f0, 4, 1; +L_0x1333fc0 .part v0x127a150_0, 4, 1; +L_0x1334130 .part L_0x13326f0, 5, 1; +L_0x1334290 .part v0x127a150_0, 5, 1; +L_0x13344b0 .part L_0x13326f0, 6, 1; +L_0x1334610 .part v0x127a150_0, 6, 1; +LS_0x1334780_0_0 .concat8 [ 1 1 1 1], L_0x1332f70, L_0x1333310, L_0x1333620, L_0x1333930; +LS_0x1334780_0_4 .concat8 [ 1 1 1 1], L_0x1333c90, L_0x13340c0, L_0x13343f0, L_0x1334380; +L_0x1334780 .concat8 [ 4 4 0 0], LS_0x1334780_0_0, LS_0x1334780_0_4; +L_0x1334b40 .part L_0x13326f0, 7, 1; +L_0x1334d30 .part v0x127a150_0, 7, 1; +S_0x114c450 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114c660 .param/l "i" 0 4 54, +C4<00>; +L_0x1332f70/d .functor AND 1, L_0x1333080, L_0x1333270, C4<1>, C4<1>; +L_0x1332f70 .delay 1 (30000,30000,30000) L_0x1332f70/d; +v0x114c740_0 .net *"_s0", 0 0, L_0x1333080; 1 drivers +v0x114c820_0 .net *"_s1", 0 0, L_0x1333270; 1 drivers +S_0x114c900 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114cb10 .param/l "i" 0 4 54, +C4<01>; +L_0x1333310/d .functor AND 1, L_0x13333d0, L_0x1333530, C4<1>, C4<1>; +L_0x1333310 .delay 1 (30000,30000,30000) L_0x1333310/d; +v0x114cbd0_0 .net *"_s0", 0 0, L_0x13333d0; 1 drivers +v0x114ccb0_0 .net *"_s1", 0 0, L_0x1333530; 1 drivers +S_0x114cd90 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114cfd0 .param/l "i" 0 4 54, +C4<010>; +L_0x1333620/d .functor AND 1, L_0x13336e0, L_0x1333840, C4<1>, C4<1>; +L_0x1333620 .delay 1 (30000,30000,30000) L_0x1333620/d; +v0x114d070_0 .net *"_s0", 0 0, L_0x13336e0; 1 drivers +v0x114d150_0 .net *"_s1", 0 0, L_0x1333840; 1 drivers +S_0x114d230 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114d440 .param/l "i" 0 4 54, +C4<011>; +L_0x1333930/d .functor AND 1, L_0x13339f0, L_0x1333b50, C4<1>, C4<1>; +L_0x1333930 .delay 1 (30000,30000,30000) L_0x1333930/d; +v0x114d500_0 .net *"_s0", 0 0, L_0x13339f0; 1 drivers +v0x114d5e0_0 .net *"_s1", 0 0, L_0x1333b50; 1 drivers +S_0x114d6c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114d920 .param/l "i" 0 4 54, +C4<0100>; +L_0x1333c90/d .functor AND 1, L_0x1333d50, L_0x1333fc0, C4<1>, C4<1>; +L_0x1333c90 .delay 1 (30000,30000,30000) L_0x1333c90/d; +v0x114d9e0_0 .net *"_s0", 0 0, L_0x1333d50; 1 drivers +v0x114dac0_0 .net *"_s1", 0 0, L_0x1333fc0; 1 drivers +S_0x114dba0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114ddb0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13340c0/d .functor AND 1, L_0x1334130, L_0x1334290, C4<1>, C4<1>; +L_0x13340c0 .delay 1 (30000,30000,30000) L_0x13340c0/d; +v0x114de70_0 .net *"_s0", 0 0, L_0x1334130; 1 drivers +v0x114df50_0 .net *"_s1", 0 0, L_0x1334290; 1 drivers +S_0x114e030 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114e240 .param/l "i" 0 4 54, +C4<0110>; +L_0x13343f0/d .functor AND 1, L_0x13344b0, L_0x1334610, C4<1>, C4<1>; +L_0x13343f0 .delay 1 (30000,30000,30000) L_0x13343f0/d; +v0x114e300_0 .net *"_s0", 0 0, L_0x13344b0; 1 drivers +v0x114e3e0_0 .net *"_s1", 0 0, L_0x1334610; 1 drivers +S_0x114e4c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x114c210; + .timescale -9 -12; +P_0x114e6d0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1334380/d .functor AND 1, L_0x1334b40, L_0x1334d30, C4<1>, C4<1>; +L_0x1334380 .delay 1 (30000,30000,30000) L_0x1334380/d; +v0x114e790_0 .net *"_s0", 0 0, L_0x1334b40; 1 drivers +v0x114e870_0 .net *"_s1", 0 0, L_0x1334d30; 1 drivers +S_0x114f430 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x114bfc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1336780/d .functor OR 1, L_0x1336840, L_0x13369f0, C4<0>, C4<0>; +L_0x1336780 .delay 1 (30000,30000,30000) L_0x1336780/d; +v0x1150f80_0 .net *"_s10", 0 0, L_0x1336840; 1 drivers +v0x1151060_0 .net *"_s12", 0 0, L_0x13369f0; 1 drivers +v0x1151140_0 .net "in", 7 0, L_0x1334780; alias, 1 drivers +v0x1151210_0 .net "ors", 1 0, L_0x13365a0; 1 drivers +v0x11512d0_0 .net "out", 0 0, L_0x1336780; alias, 1 drivers +L_0x1335970 .part L_0x1334780, 0, 4; +L_0x13365a0 .concat8 [ 1 1 0 0], L_0x1335660, L_0x1336290; +L_0x13366e0 .part L_0x1334780, 4, 4; +L_0x1336840 .part L_0x13365a0, 0, 1; +L_0x13369f0 .part L_0x13365a0, 1, 1; +S_0x114f5f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x114f430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1334e20/d .functor OR 1, L_0x1334ee0, L_0x1335040, C4<0>, C4<0>; +L_0x1334e20 .delay 1 (30000,30000,30000) L_0x1334e20/d; +L_0x1335270/d .functor OR 1, L_0x1335380, L_0x13354e0, C4<0>, C4<0>; +L_0x1335270 .delay 1 (30000,30000,30000) L_0x1335270/d; +L_0x1335660/d .functor OR 1, L_0x13356d0, L_0x1335880, C4<0>, C4<0>; +L_0x1335660 .delay 1 (30000,30000,30000) L_0x1335660/d; +v0x114f840_0 .net *"_s0", 0 0, L_0x1334e20; 1 drivers +v0x114f940_0 .net *"_s10", 0 0, L_0x1335380; 1 drivers +v0x114fa20_0 .net *"_s12", 0 0, L_0x13354e0; 1 drivers +v0x114fae0_0 .net *"_s14", 0 0, L_0x13356d0; 1 drivers +v0x114fbc0_0 .net *"_s16", 0 0, L_0x1335880; 1 drivers +v0x114fcf0_0 .net *"_s3", 0 0, L_0x1334ee0; 1 drivers +v0x114fdd0_0 .net *"_s5", 0 0, L_0x1335040; 1 drivers +v0x114feb0_0 .net *"_s6", 0 0, L_0x1335270; 1 drivers +v0x114ff90_0 .net "in", 3 0, L_0x1335970; 1 drivers +v0x1150100_0 .net "ors", 1 0, L_0x1335180; 1 drivers +v0x11501e0_0 .net "out", 0 0, L_0x1335660; 1 drivers +L_0x1334ee0 .part L_0x1335970, 0, 1; +L_0x1335040 .part L_0x1335970, 1, 1; +L_0x1335180 .concat8 [ 1 1 0 0], L_0x1334e20, L_0x1335270; +L_0x1335380 .part L_0x1335970, 2, 1; +L_0x13354e0 .part L_0x1335970, 3, 1; +L_0x13356d0 .part L_0x1335180, 0, 1; +L_0x1335880 .part L_0x1335180, 1, 1; +S_0x1150300 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x114f430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1335aa0/d .functor OR 1, L_0x1335b10, L_0x1335c70, C4<0>, C4<0>; +L_0x1335aa0 .delay 1 (30000,30000,30000) L_0x1335aa0/d; +L_0x1335ea0/d .functor OR 1, L_0x1335fb0, L_0x1336110, C4<0>, C4<0>; +L_0x1335ea0 .delay 1 (30000,30000,30000) L_0x1335ea0/d; +L_0x1336290/d .functor OR 1, L_0x1336300, L_0x13364b0, C4<0>, C4<0>; +L_0x1336290 .delay 1 (30000,30000,30000) L_0x1336290/d; +v0x11504c0_0 .net *"_s0", 0 0, L_0x1335aa0; 1 drivers +v0x11505c0_0 .net *"_s10", 0 0, L_0x1335fb0; 1 drivers +v0x11506a0_0 .net *"_s12", 0 0, L_0x1336110; 1 drivers +v0x1150760_0 .net *"_s14", 0 0, L_0x1336300; 1 drivers +v0x1150840_0 .net *"_s16", 0 0, L_0x13364b0; 1 drivers +v0x1150970_0 .net *"_s3", 0 0, L_0x1335b10; 1 drivers +v0x1150a50_0 .net *"_s5", 0 0, L_0x1335c70; 1 drivers +v0x1150b30_0 .net *"_s6", 0 0, L_0x1335ea0; 1 drivers +v0x1150c10_0 .net "in", 3 0, L_0x13366e0; 1 drivers +v0x1150d80_0 .net "ors", 1 0, L_0x1335db0; 1 drivers +v0x1150e60_0 .net "out", 0 0, L_0x1336290; 1 drivers +L_0x1335b10 .part L_0x13366e0, 0, 1; +L_0x1335c70 .part L_0x13366e0, 1, 1; +L_0x1335db0 .concat8 [ 1 1 0 0], L_0x1335aa0, L_0x1335ea0; +L_0x1335fb0 .part L_0x13366e0, 2, 1; +L_0x1336110 .part L_0x13366e0, 3, 1; +L_0x1336300 .part L_0x1335db0, 0, 1; +L_0x13364b0 .part L_0x1335db0, 1, 1; +S_0x1151770 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11450f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1331530/d .functor XNOR 1, L_0x133a620, L_0x1330010, C4<0>, C4<0>; +L_0x1331530 .delay 1 (20000,20000,20000) L_0x1331530/d; +L_0x13316b0/d .functor AND 1, L_0x133a620, L_0x1330270, C4<1>, C4<1>; +L_0x13316b0 .delay 1 (30000,30000,30000) L_0x13316b0/d; +L_0x1331810/d .functor AND 1, L_0x1331530, L_0x13300b0, C4<1>, C4<1>; +L_0x1331810 .delay 1 (30000,30000,30000) L_0x1331810/d; +L_0x1331920/d .functor OR 1, L_0x1331810, L_0x13316b0, C4<0>, C4<0>; +L_0x1331920 .delay 1 (30000,30000,30000) L_0x1331920/d; +v0x1151a20_0 .net "a", 0 0, L_0x133a620; alias, 1 drivers +v0x1151b10_0 .net "a_", 0 0, L_0x13301b0; alias, 1 drivers +v0x1151bd0_0 .net "b", 0 0, L_0x1330010; alias, 1 drivers +v0x1151cc0_0 .net "b_", 0 0, L_0x1330270; alias, 1 drivers +v0x1151d60_0 .net "carryin", 0 0, L_0x13300b0; alias, 1 drivers +v0x1151ea0_0 .net "eq", 0 0, L_0x1331530; 1 drivers +v0x1151f60_0 .net "lt", 0 0, L_0x13316b0; 1 drivers +v0x1152020_0 .net "out", 0 0, L_0x1331920; 1 drivers +v0x11520e0_0 .net "w0", 0 0, L_0x1331810; 1 drivers +S_0x1152330 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11450f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1331110/d .functor OR 1, L_0x1330c60, L_0x1153590, C4<0>, C4<0>; +L_0x1331110 .delay 1 (30000,30000,30000) L_0x1331110/d; +v0x1153120_0 .net "a", 0 0, L_0x133a620; alias, 1 drivers +v0x1153270_0 .net "b", 0 0, L_0x1330270; alias, 1 drivers +v0x1153330_0 .net "c1", 0 0, L_0x1330c60; 1 drivers +v0x11533d0_0 .net "c2", 0 0, L_0x1153590; 1 drivers +v0x11534a0_0 .net "carryin", 0 0, L_0x13300b0; alias, 1 drivers +v0x1153620_0 .net "carryout", 0 0, L_0x1331110; 1 drivers +v0x11536c0_0 .net "s1", 0 0, L_0x1330ba0; 1 drivers +v0x1153760_0 .net "sum", 0 0, L_0x1330dc0; 1 drivers +S_0x1152580 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1152330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1330ba0/d .functor XOR 1, L_0x133a620, L_0x1330270, C4<0>, C4<0>; +L_0x1330ba0 .delay 1 (30000,30000,30000) L_0x1330ba0/d; +L_0x1330c60/d .functor AND 1, L_0x133a620, L_0x1330270, C4<1>, C4<1>; +L_0x1330c60 .delay 1 (30000,30000,30000) L_0x1330c60/d; +v0x11527e0_0 .net "a", 0 0, L_0x133a620; alias, 1 drivers +v0x11528a0_0 .net "b", 0 0, L_0x1330270; alias, 1 drivers +v0x1152960_0 .net "carryout", 0 0, L_0x1330c60; alias, 1 drivers +v0x1152a00_0 .net "sum", 0 0, L_0x1330ba0; alias, 1 drivers +S_0x1152b30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1152330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1330dc0/d .functor XOR 1, L_0x1330ba0, L_0x13300b0, C4<0>, C4<0>; +L_0x1330dc0 .delay 1 (30000,30000,30000) L_0x1330dc0/d; +L_0x1153590/d .functor AND 1, L_0x1330ba0, L_0x13300b0, C4<1>, C4<1>; +L_0x1153590 .delay 1 (30000,30000,30000) L_0x1153590/d; +v0x1152d90_0 .net "a", 0 0, L_0x1330ba0; alias, 1 drivers +v0x1152e60_0 .net "b", 0 0, L_0x13300b0; alias, 1 drivers +v0x1152f00_0 .net "carryout", 0 0, L_0x1153590; alias, 1 drivers +v0x1152fd0_0 .net "sum", 0 0, L_0x1330dc0; alias, 1 drivers +S_0x11557f0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1144e20; + .timescale -9 -12; +L_0x2ac4328875d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887620 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1330720/d .functor OR 1, L_0x2ac4328875d8, L_0x2ac432887620, C4<0>, C4<0>; +L_0x1330720 .delay 1 (30000,30000,30000) L_0x1330720/d; +v0x11559e0_0 .net/2u *"_s0", 0 0, L_0x2ac4328875d8; 1 drivers +v0x1155ac0_0 .net/2u *"_s2", 0 0, L_0x2ac432887620; 1 drivers +S_0x1155ba0 .scope generate, "alu_slices[18]" "alu_slices[18]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1155db0 .param/l "i" 0 3 39, +C4<010010>; +S_0x1155e70 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1155ba0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x133a9e0/d .functor NOT 1, L_0x13456c0, C4<0>, C4<0>, C4<0>; +L_0x133a9e0 .delay 1 (10000,10000,10000) L_0x133a9e0/d; +L_0x133aaf0/d .functor NOT 1, L_0x1345820, C4<0>, C4<0>, C4<0>; +L_0x133aaf0 .delay 1 (10000,10000,10000) L_0x133aaf0/d; +L_0x133bb40/d .functor XOR 1, L_0x13456c0, L_0x1345820, C4<0>, C4<0>; +L_0x133bb40 .delay 1 (30000,30000,30000) L_0x133bb40/d; +L_0x2ac432887668 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328876b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x133bc00/d .functor OR 1, L_0x2ac432887668, L_0x2ac4328876b0, C4<0>, C4<0>; +L_0x133bc00 .delay 1 (30000,30000,30000) L_0x133bc00/d; +L_0x2ac4328876f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887740 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x133c3a0/d .functor OR 1, L_0x2ac4328876f8, L_0x2ac432887740, C4<0>, C4<0>; +L_0x133c3a0 .delay 1 (30000,30000,30000) L_0x133c3a0/d; +L_0x133c5a0/d .functor AND 1, L_0x13456c0, L_0x1345820, C4<1>, C4<1>; +L_0x133c5a0 .delay 1 (30000,30000,30000) L_0x133c5a0/d; +L_0x2ac432887788 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328877d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x133c660/d .functor OR 1, L_0x2ac432887788, L_0x2ac4328877d0, C4<0>, C4<0>; +L_0x133c660 .delay 1 (30000,30000,30000) L_0x133c660/d; +L_0x133c860/d .functor NAND 1, L_0x13456c0, L_0x1345820, C4<1>, C4<1>; +L_0x133c860 .delay 1 (20000,20000,20000) L_0x133c860/d; +L_0x2ac432887818 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887860 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x133c970/d .functor OR 1, L_0x2ac432887818, L_0x2ac432887860, C4<0>, C4<0>; +L_0x133c970 .delay 1 (30000,30000,30000) L_0x133c970/d; +L_0x133cad0/d .functor NOR 1, L_0x13456c0, L_0x1345820, C4<0>, C4<0>; +L_0x133cad0 .delay 1 (20000,20000,20000) L_0x133cad0/d; +L_0x2ac4328878a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328878f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x133af60/d .functor OR 1, L_0x2ac4328878a8, L_0x2ac4328878f0, C4<0>, C4<0>; +L_0x133af60 .delay 1 (30000,30000,30000) L_0x133af60/d; +L_0x12dd880/d .functor OR 1, L_0x13456c0, L_0x1345820, C4<0>, C4<0>; +L_0x12dd880 .delay 1 (30000,30000,30000) L_0x12dd880/d; +L_0x2ac432887938 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887980 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x133dec0/d .functor OR 1, L_0x2ac432887938, L_0x2ac432887980, C4<0>, C4<0>; +L_0x133dec0 .delay 1 (30000,30000,30000) L_0x133dec0/d; +L_0x13455c0/d .functor NOT 1, L_0x1341820, C4<0>, C4<0>, C4<0>; +L_0x13455c0 .delay 1 (10000,10000,10000) L_0x13455c0/d; +v0x11645a0_0 .net "A", 0 0, L_0x13456c0; 1 drivers +v0x1164660_0 .net "A_", 0 0, L_0x133a9e0; 1 drivers +v0x1164720_0 .net "B", 0 0, L_0x1345820; 1 drivers +v0x11647f0_0 .net "B_", 0 0, L_0x133aaf0; 1 drivers +v0x1164890_0 .net *"_s11", 0 0, L_0x133bc00; 1 drivers +v0x1164980_0 .net/2s *"_s13", 0 0, L_0x2ac432887668; 1 drivers +v0x1164a40_0 .net/2s *"_s15", 0 0, L_0x2ac4328876b0; 1 drivers +v0x1164b20_0 .net *"_s19", 0 0, L_0x133c3a0; 1 drivers +v0x1164c00_0 .net/2s *"_s21", 0 0, L_0x2ac4328876f8; 1 drivers +v0x1164d70_0 .net/2s *"_s23", 0 0, L_0x2ac432887740; 1 drivers +v0x1164e50_0 .net *"_s25", 0 0, L_0x133c5a0; 1 drivers +v0x1164f30_0 .net *"_s28", 0 0, L_0x133c660; 1 drivers +v0x1165010_0 .net/2s *"_s30", 0 0, L_0x2ac432887788; 1 drivers +v0x11650f0_0 .net/2s *"_s32", 0 0, L_0x2ac4328877d0; 1 drivers +v0x11651d0_0 .net *"_s34", 0 0, L_0x133c860; 1 drivers +v0x11652b0_0 .net *"_s37", 0 0, L_0x133c970; 1 drivers +v0x1165390_0 .net/2s *"_s39", 0 0, L_0x2ac432887818; 1 drivers +v0x1165540_0 .net/2s *"_s41", 0 0, L_0x2ac432887860; 1 drivers +v0x11655e0_0 .net *"_s43", 0 0, L_0x133cad0; 1 drivers +v0x11656c0_0 .net *"_s46", 0 0, L_0x133af60; 1 drivers +v0x11657a0_0 .net/2s *"_s48", 0 0, L_0x2ac4328878a8; 1 drivers +v0x1165880_0 .net/2s *"_s50", 0 0, L_0x2ac4328878f0; 1 drivers +v0x1165960_0 .net *"_s52", 0 0, L_0x12dd880; 1 drivers +v0x1165a40_0 .net *"_s56", 0 0, L_0x133dec0; 1 drivers +v0x1165b20_0 .net/2s *"_s59", 0 0, L_0x2ac432887938; 1 drivers +v0x1165c00_0 .net/2s *"_s61", 0 0, L_0x2ac432887980; 1 drivers +v0x1165ce0_0 .net *"_s8", 0 0, L_0x133bb40; 1 drivers +v0x1165dc0_0 .net "carryin", 0 0, L_0x133a780; 1 drivers +v0x1165e60_0 .net "carryout", 0 0, L_0x1345260; 1 drivers +v0x1165f00_0 .net "carryouts", 7 0, L_0x12ddcd0; 1 drivers +v0x1166010_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11660d0_0 .net "result", 0 0, L_0x1341820; 1 drivers +v0x11661c0_0 .net "results", 7 0, L_0x12dd940; 1 drivers +v0x11654a0_0 .net "zero", 0 0, L_0x13455c0; 1 drivers +LS_0x12dd940_0_0 .concat8 [ 1 1 1 1], L_0x133b010, L_0x133b640, L_0x133bb40, L_0x133c3a0; +LS_0x12dd940_0_4 .concat8 [ 1 1 1 1], L_0x133c5a0, L_0x133c860, L_0x133cad0, L_0x12dd880; +L_0x12dd940 .concat8 [ 4 4 0 0], LS_0x12dd940_0_0, LS_0x12dd940_0_4; +LS_0x12ddcd0_0_0 .concat8 [ 1 1 1 1], L_0x133b2c0, L_0x133b9e0, L_0x133bc00, L_0x133c1f0; +LS_0x12ddcd0_0_4 .concat8 [ 1 1 1 1], L_0x133c660, L_0x133c970, L_0x133af60, L_0x133dec0; +L_0x12ddcd0 .concat8 [ 4 4 0 0], LS_0x12ddcd0_0_0, LS_0x12ddcd0_0_4; +S_0x11560f0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1155e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x133b2c0/d .functor OR 1, L_0x133ada0, L_0x133b160, C4<0>, C4<0>; +L_0x133b2c0 .delay 1 (30000,30000,30000) L_0x133b2c0/d; +v0x1156f20_0 .net "a", 0 0, L_0x13456c0; alias, 1 drivers +v0x1156fe0_0 .net "b", 0 0, L_0x1345820; alias, 1 drivers +v0x11570b0_0 .net "c1", 0 0, L_0x133ada0; 1 drivers +v0x11571b0_0 .net "c2", 0 0, L_0x133b160; 1 drivers +v0x1157280_0 .net "carryin", 0 0, L_0x133a780; alias, 1 drivers +v0x1157370_0 .net "carryout", 0 0, L_0x133b2c0; 1 drivers +v0x1157410_0 .net "s1", 0 0, L_0x133ace0; 1 drivers +v0x1157500_0 .net "sum", 0 0, L_0x133b010; 1 drivers +S_0x1156360 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11560f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x133ace0/d .functor XOR 1, L_0x13456c0, L_0x1345820, C4<0>, C4<0>; +L_0x133ace0 .delay 1 (30000,30000,30000) L_0x133ace0/d; +L_0x133ada0/d .functor AND 1, L_0x13456c0, L_0x1345820, C4<1>, C4<1>; +L_0x133ada0 .delay 1 (30000,30000,30000) L_0x133ada0/d; +v0x11565c0_0 .net "a", 0 0, L_0x13456c0; alias, 1 drivers +v0x11566a0_0 .net "b", 0 0, L_0x1345820; alias, 1 drivers +v0x1156760_0 .net "carryout", 0 0, L_0x133ada0; alias, 1 drivers +v0x1156800_0 .net "sum", 0 0, L_0x133ace0; alias, 1 drivers +S_0x1156940 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11560f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x133b010/d .functor XOR 1, L_0x133ace0, L_0x133a780, C4<0>, C4<0>; +L_0x133b010 .delay 1 (30000,30000,30000) L_0x133b010/d; +L_0x133b160/d .functor AND 1, L_0x133ace0, L_0x133a780, C4<1>, C4<1>; +L_0x133b160 .delay 1 (30000,30000,30000) L_0x133b160/d; +v0x1156ba0_0 .net "a", 0 0, L_0x133ace0; alias, 1 drivers +v0x1156c40_0 .net "b", 0 0, L_0x133a780; alias, 1 drivers +v0x1156ce0_0 .net "carryout", 0 0, L_0x133b160; alias, 1 drivers +v0x1156db0_0 .net "sum", 0 0, L_0x133b010; alias, 1 drivers +S_0x11575d0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1155e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x115c9c0_0 .net "ands", 7 0, L_0x1343260; 1 drivers +v0x115cad0_0 .net "in", 7 0, L_0x12ddcd0; alias, 1 drivers +v0x115cb90_0 .net "out", 0 0, L_0x1345260; alias, 1 drivers +v0x115cc60_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11577f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11575d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1159f20_0 .net "A", 7 0, L_0x12ddcd0; alias, 1 drivers +v0x115a020_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x115a0e0_0 .net *"_s0", 0 0, L_0x1341b80; 1 drivers +v0x115a1a0_0 .net *"_s12", 0 0, L_0x13424f0; 1 drivers +v0x115a280_0 .net *"_s16", 0 0, L_0x1342850; 1 drivers +v0x115a3b0_0 .net *"_s20", 0 0, L_0x1342c20; 1 drivers +v0x115a490_0 .net *"_s24", 0 0, L_0x1342f50; 1 drivers +v0x115a570_0 .net *"_s28", 0 0, L_0x1342ee0; 1 drivers +v0x115a650_0 .net *"_s4", 0 0, L_0x1341ed0; 1 drivers +v0x115a7c0_0 .net *"_s8", 0 0, L_0x13421e0; 1 drivers +v0x115a8a0_0 .net "out", 7 0, L_0x1343260; alias, 1 drivers +L_0x1341c40 .part L_0x12ddcd0, 0, 1; +L_0x1341e30 .part v0x127a150_0, 0, 1; +L_0x1341f90 .part L_0x12ddcd0, 1, 1; +L_0x13420f0 .part v0x127a150_0, 1, 1; +L_0x13422a0 .part L_0x12ddcd0, 2, 1; +L_0x1342400 .part v0x127a150_0, 2, 1; +L_0x13425b0 .part L_0x12ddcd0, 3, 1; +L_0x1342710 .part v0x127a150_0, 3, 1; +L_0x1342910 .part L_0x12ddcd0, 4, 1; +L_0x1342b80 .part v0x127a150_0, 4, 1; +L_0x1342c90 .part L_0x12ddcd0, 5, 1; +L_0x1342df0 .part v0x127a150_0, 5, 1; +L_0x1343010 .part L_0x12ddcd0, 6, 1; +L_0x1343170 .part v0x127a150_0, 6, 1; +LS_0x1343260_0_0 .concat8 [ 1 1 1 1], L_0x1341b80, L_0x1341ed0, L_0x13421e0, L_0x13424f0; +LS_0x1343260_0_4 .concat8 [ 1 1 1 1], L_0x1342850, L_0x1342c20, L_0x1342f50, L_0x1342ee0; +L_0x1343260 .concat8 [ 4 4 0 0], LS_0x1343260_0_0, LS_0x1343260_0_4; +L_0x1343620 .part L_0x12ddcd0, 7, 1; +L_0x1343810 .part v0x127a150_0, 7, 1; +S_0x1157a50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1157c60 .param/l "i" 0 4 54, +C4<00>; +L_0x1341b80/d .functor AND 1, L_0x1341c40, L_0x1341e30, C4<1>, C4<1>; +L_0x1341b80 .delay 1 (30000,30000,30000) L_0x1341b80/d; +v0x1157d40_0 .net *"_s0", 0 0, L_0x1341c40; 1 drivers +v0x1157e20_0 .net *"_s1", 0 0, L_0x1341e30; 1 drivers +S_0x1157f00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1158110 .param/l "i" 0 4 54, +C4<01>; +L_0x1341ed0/d .functor AND 1, L_0x1341f90, L_0x13420f0, C4<1>, C4<1>; +L_0x1341ed0 .delay 1 (30000,30000,30000) L_0x1341ed0/d; +v0x11581d0_0 .net *"_s0", 0 0, L_0x1341f90; 1 drivers +v0x11582b0_0 .net *"_s1", 0 0, L_0x13420f0; 1 drivers +S_0x1158390 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x11585a0 .param/l "i" 0 4 54, +C4<010>; +L_0x13421e0/d .functor AND 1, L_0x13422a0, L_0x1342400, C4<1>, C4<1>; +L_0x13421e0 .delay 1 (30000,30000,30000) L_0x13421e0/d; +v0x1158640_0 .net *"_s0", 0 0, L_0x13422a0; 1 drivers +v0x1158720_0 .net *"_s1", 0 0, L_0x1342400; 1 drivers +S_0x1158800 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1158a10 .param/l "i" 0 4 54, +C4<011>; +L_0x13424f0/d .functor AND 1, L_0x13425b0, L_0x1342710, C4<1>, C4<1>; +L_0x13424f0 .delay 1 (30000,30000,30000) L_0x13424f0/d; +v0x1158ad0_0 .net *"_s0", 0 0, L_0x13425b0; 1 drivers +v0x1158bb0_0 .net *"_s1", 0 0, L_0x1342710; 1 drivers +S_0x1158c90 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1158ef0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1342850/d .functor AND 1, L_0x1342910, L_0x1342b80, C4<1>, C4<1>; +L_0x1342850 .delay 1 (30000,30000,30000) L_0x1342850/d; +v0x1158fb0_0 .net *"_s0", 0 0, L_0x1342910; 1 drivers +v0x1159090_0 .net *"_s1", 0 0, L_0x1342b80; 1 drivers +S_0x1159170 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1159380 .param/l "i" 0 4 54, +C4<0101>; +L_0x1342c20/d .functor AND 1, L_0x1342c90, L_0x1342df0, C4<1>, C4<1>; +L_0x1342c20 .delay 1 (30000,30000,30000) L_0x1342c20/d; +v0x1159440_0 .net *"_s0", 0 0, L_0x1342c90; 1 drivers +v0x1159520_0 .net *"_s1", 0 0, L_0x1342df0; 1 drivers +S_0x1159600 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1159810 .param/l "i" 0 4 54, +C4<0110>; +L_0x1342f50/d .functor AND 1, L_0x1343010, L_0x1343170, C4<1>, C4<1>; +L_0x1342f50 .delay 1 (30000,30000,30000) L_0x1342f50/d; +v0x11598d0_0 .net *"_s0", 0 0, L_0x1343010; 1 drivers +v0x11599b0_0 .net *"_s1", 0 0, L_0x1343170; 1 drivers +S_0x1159a90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11577f0; + .timescale -9 -12; +P_0x1159ca0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1342ee0/d .functor AND 1, L_0x1343620, L_0x1343810, C4<1>, C4<1>; +L_0x1342ee0 .delay 1 (30000,30000,30000) L_0x1342ee0/d; +v0x1159d60_0 .net *"_s0", 0 0, L_0x1343620; 1 drivers +v0x1159e40_0 .net *"_s1", 0 0, L_0x1343810; 1 drivers +S_0x115aa00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11575d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1345260/d .functor OR 1, L_0x1345320, L_0x13454d0, C4<0>, C4<0>; +L_0x1345260 .delay 1 (30000,30000,30000) L_0x1345260/d; +v0x115c550_0 .net *"_s10", 0 0, L_0x1345320; 1 drivers +v0x115c630_0 .net *"_s12", 0 0, L_0x13454d0; 1 drivers +v0x115c710_0 .net "in", 7 0, L_0x1343260; alias, 1 drivers +v0x115c7e0_0 .net "ors", 1 0, L_0x1345080; 1 drivers +v0x115c8a0_0 .net "out", 0 0, L_0x1345260; alias, 1 drivers +L_0x1344450 .part L_0x1343260, 0, 4; +L_0x1345080 .concat8 [ 1 1 0 0], L_0x1344140, L_0x1344d70; +L_0x13451c0 .part L_0x1343260, 4, 4; +L_0x1345320 .part L_0x1345080, 0, 1; +L_0x13454d0 .part L_0x1345080, 1, 1; +S_0x115abc0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x115aa00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1343900/d .functor OR 1, L_0x13439c0, L_0x1343b20, C4<0>, C4<0>; +L_0x1343900 .delay 1 (30000,30000,30000) L_0x1343900/d; +L_0x1343d50/d .functor OR 1, L_0x1343e60, L_0x1343fc0, C4<0>, C4<0>; +L_0x1343d50 .delay 1 (30000,30000,30000) L_0x1343d50/d; +L_0x1344140/d .functor OR 1, L_0x13441b0, L_0x1344360, C4<0>, C4<0>; +L_0x1344140 .delay 1 (30000,30000,30000) L_0x1344140/d; +v0x115ae10_0 .net *"_s0", 0 0, L_0x1343900; 1 drivers +v0x115af10_0 .net *"_s10", 0 0, L_0x1343e60; 1 drivers +v0x115aff0_0 .net *"_s12", 0 0, L_0x1343fc0; 1 drivers +v0x115b0b0_0 .net *"_s14", 0 0, L_0x13441b0; 1 drivers +v0x115b190_0 .net *"_s16", 0 0, L_0x1344360; 1 drivers +v0x115b2c0_0 .net *"_s3", 0 0, L_0x13439c0; 1 drivers +v0x115b3a0_0 .net *"_s5", 0 0, L_0x1343b20; 1 drivers +v0x115b480_0 .net *"_s6", 0 0, L_0x1343d50; 1 drivers +v0x115b560_0 .net "in", 3 0, L_0x1344450; 1 drivers +v0x115b6d0_0 .net "ors", 1 0, L_0x1343c60; 1 drivers +v0x115b7b0_0 .net "out", 0 0, L_0x1344140; 1 drivers +L_0x13439c0 .part L_0x1344450, 0, 1; +L_0x1343b20 .part L_0x1344450, 1, 1; +L_0x1343c60 .concat8 [ 1 1 0 0], L_0x1343900, L_0x1343d50; +L_0x1343e60 .part L_0x1344450, 2, 1; +L_0x1343fc0 .part L_0x1344450, 3, 1; +L_0x13441b0 .part L_0x1343c60, 0, 1; +L_0x1344360 .part L_0x1343c60, 1, 1; +S_0x115b8d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x115aa00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1344580/d .functor OR 1, L_0x13445f0, L_0x1344750, C4<0>, C4<0>; +L_0x1344580 .delay 1 (30000,30000,30000) L_0x1344580/d; +L_0x1344980/d .functor OR 1, L_0x1344a90, L_0x1344bf0, C4<0>, C4<0>; +L_0x1344980 .delay 1 (30000,30000,30000) L_0x1344980/d; +L_0x1344d70/d .functor OR 1, L_0x1344de0, L_0x1344f90, C4<0>, C4<0>; +L_0x1344d70 .delay 1 (30000,30000,30000) L_0x1344d70/d; +v0x115ba90_0 .net *"_s0", 0 0, L_0x1344580; 1 drivers +v0x115bb90_0 .net *"_s10", 0 0, L_0x1344a90; 1 drivers +v0x115bc70_0 .net *"_s12", 0 0, L_0x1344bf0; 1 drivers +v0x115bd30_0 .net *"_s14", 0 0, L_0x1344de0; 1 drivers +v0x115be10_0 .net *"_s16", 0 0, L_0x1344f90; 1 drivers +v0x115bf40_0 .net *"_s3", 0 0, L_0x13445f0; 1 drivers +v0x115c020_0 .net *"_s5", 0 0, L_0x1344750; 1 drivers +v0x115c100_0 .net *"_s6", 0 0, L_0x1344980; 1 drivers +v0x115c1e0_0 .net "in", 3 0, L_0x13451c0; 1 drivers +v0x115c350_0 .net "ors", 1 0, L_0x1344890; 1 drivers +v0x115c430_0 .net "out", 0 0, L_0x1344d70; 1 drivers +L_0x13445f0 .part L_0x13451c0, 0, 1; +L_0x1344750 .part L_0x13451c0, 1, 1; +L_0x1344890 .concat8 [ 1 1 0 0], L_0x1344580, L_0x1344980; +L_0x1344a90 .part L_0x13451c0, 2, 1; +L_0x1344bf0 .part L_0x13451c0, 3, 1; +L_0x1344de0 .part L_0x1344890, 0, 1; +L_0x1344f90 .part L_0x1344890, 1, 1; +S_0x115cd40 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1155e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1162170_0 .net "ands", 7 0, L_0x133f820; 1 drivers +v0x1162280_0 .net "in", 7 0, L_0x12dd940; alias, 1 drivers +v0x1162340_0 .net "out", 0 0, L_0x1341820; alias, 1 drivers +v0x1162410_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x115cf90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x115cd40; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x115f6d0_0 .net "A", 7 0, L_0x12dd940; alias, 1 drivers +v0x115f7d0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x115f890_0 .net *"_s0", 0 0, L_0x133e070; 1 drivers +v0x115f950_0 .net *"_s12", 0 0, L_0x133ea30; 1 drivers +v0x115fa30_0 .net *"_s16", 0 0, L_0x133ed90; 1 drivers +v0x115fb60_0 .net *"_s20", 0 0, L_0x133f160; 1 drivers +v0x115fc40_0 .net *"_s24", 0 0, L_0x133f490; 1 drivers +v0x115fd20_0 .net *"_s28", 0 0, L_0x133f420; 1 drivers +v0x115fe00_0 .net *"_s4", 0 0, L_0x133e410; 1 drivers +v0x115ff70_0 .net *"_s8", 0 0, L_0x133e720; 1 drivers +v0x1160050_0 .net "out", 7 0, L_0x133f820; alias, 1 drivers +L_0x133e180 .part L_0x12dd940, 0, 1; +L_0x133e370 .part v0x127a150_0, 0, 1; +L_0x133e4d0 .part L_0x12dd940, 1, 1; +L_0x133e630 .part v0x127a150_0, 1, 1; +L_0x133e7e0 .part L_0x12dd940, 2, 1; +L_0x133e940 .part v0x127a150_0, 2, 1; +L_0x133eaf0 .part L_0x12dd940, 3, 1; +L_0x133ec50 .part v0x127a150_0, 3, 1; +L_0x133ee50 .part L_0x12dd940, 4, 1; +L_0x133f0c0 .part v0x127a150_0, 4, 1; +L_0x133f1d0 .part L_0x12dd940, 5, 1; +L_0x133f330 .part v0x127a150_0, 5, 1; +L_0x133f550 .part L_0x12dd940, 6, 1; +L_0x133f6b0 .part v0x127a150_0, 6, 1; +LS_0x133f820_0_0 .concat8 [ 1 1 1 1], L_0x133e070, L_0x133e410, L_0x133e720, L_0x133ea30; +LS_0x133f820_0_4 .concat8 [ 1 1 1 1], L_0x133ed90, L_0x133f160, L_0x133f490, L_0x133f420; +L_0x133f820 .concat8 [ 4 4 0 0], LS_0x133f820_0_0, LS_0x133f820_0_4; +L_0x133fbe0 .part L_0x12dd940, 7, 1; +L_0x133fdd0 .part v0x127a150_0, 7, 1; +S_0x115d1d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115d3e0 .param/l "i" 0 4 54, +C4<00>; +L_0x133e070/d .functor AND 1, L_0x133e180, L_0x133e370, C4<1>, C4<1>; +L_0x133e070 .delay 1 (30000,30000,30000) L_0x133e070/d; +v0x115d4c0_0 .net *"_s0", 0 0, L_0x133e180; 1 drivers +v0x115d5a0_0 .net *"_s1", 0 0, L_0x133e370; 1 drivers +S_0x115d680 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115d890 .param/l "i" 0 4 54, +C4<01>; +L_0x133e410/d .functor AND 1, L_0x133e4d0, L_0x133e630, C4<1>, C4<1>; +L_0x133e410 .delay 1 (30000,30000,30000) L_0x133e410/d; +v0x115d950_0 .net *"_s0", 0 0, L_0x133e4d0; 1 drivers +v0x115da30_0 .net *"_s1", 0 0, L_0x133e630; 1 drivers +S_0x115db10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115dd50 .param/l "i" 0 4 54, +C4<010>; +L_0x133e720/d .functor AND 1, L_0x133e7e0, L_0x133e940, C4<1>, C4<1>; +L_0x133e720 .delay 1 (30000,30000,30000) L_0x133e720/d; +v0x115ddf0_0 .net *"_s0", 0 0, L_0x133e7e0; 1 drivers +v0x115ded0_0 .net *"_s1", 0 0, L_0x133e940; 1 drivers +S_0x115dfb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115e1c0 .param/l "i" 0 4 54, +C4<011>; +L_0x133ea30/d .functor AND 1, L_0x133eaf0, L_0x133ec50, C4<1>, C4<1>; +L_0x133ea30 .delay 1 (30000,30000,30000) L_0x133ea30/d; +v0x115e280_0 .net *"_s0", 0 0, L_0x133eaf0; 1 drivers +v0x115e360_0 .net *"_s1", 0 0, L_0x133ec50; 1 drivers +S_0x115e440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115e6a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x133ed90/d .functor AND 1, L_0x133ee50, L_0x133f0c0, C4<1>, C4<1>; +L_0x133ed90 .delay 1 (30000,30000,30000) L_0x133ed90/d; +v0x115e760_0 .net *"_s0", 0 0, L_0x133ee50; 1 drivers +v0x115e840_0 .net *"_s1", 0 0, L_0x133f0c0; 1 drivers +S_0x115e920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115eb30 .param/l "i" 0 4 54, +C4<0101>; +L_0x133f160/d .functor AND 1, L_0x133f1d0, L_0x133f330, C4<1>, C4<1>; +L_0x133f160 .delay 1 (30000,30000,30000) L_0x133f160/d; +v0x115ebf0_0 .net *"_s0", 0 0, L_0x133f1d0; 1 drivers +v0x115ecd0_0 .net *"_s1", 0 0, L_0x133f330; 1 drivers +S_0x115edb0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115efc0 .param/l "i" 0 4 54, +C4<0110>; +L_0x133f490/d .functor AND 1, L_0x133f550, L_0x133f6b0, C4<1>, C4<1>; +L_0x133f490 .delay 1 (30000,30000,30000) L_0x133f490/d; +v0x115f080_0 .net *"_s0", 0 0, L_0x133f550; 1 drivers +v0x115f160_0 .net *"_s1", 0 0, L_0x133f6b0; 1 drivers +S_0x115f240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x115cf90; + .timescale -9 -12; +P_0x115f450 .param/l "i" 0 4 54, +C4<0111>; +L_0x133f420/d .functor AND 1, L_0x133fbe0, L_0x133fdd0, C4<1>, C4<1>; +L_0x133f420 .delay 1 (30000,30000,30000) L_0x133f420/d; +v0x115f510_0 .net *"_s0", 0 0, L_0x133fbe0; 1 drivers +v0x115f5f0_0 .net *"_s1", 0 0, L_0x133fdd0; 1 drivers +S_0x11601b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x115cd40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1341820/d .functor OR 1, L_0x13418e0, L_0x1341a90, C4<0>, C4<0>; +L_0x1341820 .delay 1 (30000,30000,30000) L_0x1341820/d; +v0x1161d00_0 .net *"_s10", 0 0, L_0x13418e0; 1 drivers +v0x1161de0_0 .net *"_s12", 0 0, L_0x1341a90; 1 drivers +v0x1161ec0_0 .net "in", 7 0, L_0x133f820; alias, 1 drivers +v0x1161f90_0 .net "ors", 1 0, L_0x1341640; 1 drivers +v0x1162050_0 .net "out", 0 0, L_0x1341820; alias, 1 drivers +L_0x1340a10 .part L_0x133f820, 0, 4; +L_0x1341640 .concat8 [ 1 1 0 0], L_0x1340700, L_0x1341330; +L_0x1341780 .part L_0x133f820, 4, 4; +L_0x13418e0 .part L_0x1341640, 0, 1; +L_0x1341a90 .part L_0x1341640, 1, 1; +S_0x1160370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11601b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x133fec0/d .functor OR 1, L_0x133ff80, L_0x13400e0, C4<0>, C4<0>; +L_0x133fec0 .delay 1 (30000,30000,30000) L_0x133fec0/d; +L_0x1340310/d .functor OR 1, L_0x1340420, L_0x1340580, C4<0>, C4<0>; +L_0x1340310 .delay 1 (30000,30000,30000) L_0x1340310/d; +L_0x1340700/d .functor OR 1, L_0x1340770, L_0x1340920, C4<0>, C4<0>; +L_0x1340700 .delay 1 (30000,30000,30000) L_0x1340700/d; +v0x11605c0_0 .net *"_s0", 0 0, L_0x133fec0; 1 drivers +v0x11606c0_0 .net *"_s10", 0 0, L_0x1340420; 1 drivers +v0x11607a0_0 .net *"_s12", 0 0, L_0x1340580; 1 drivers +v0x1160860_0 .net *"_s14", 0 0, L_0x1340770; 1 drivers +v0x1160940_0 .net *"_s16", 0 0, L_0x1340920; 1 drivers +v0x1160a70_0 .net *"_s3", 0 0, L_0x133ff80; 1 drivers +v0x1160b50_0 .net *"_s5", 0 0, L_0x13400e0; 1 drivers +v0x1160c30_0 .net *"_s6", 0 0, L_0x1340310; 1 drivers +v0x1160d10_0 .net "in", 3 0, L_0x1340a10; 1 drivers +v0x1160e80_0 .net "ors", 1 0, L_0x1340220; 1 drivers +v0x1160f60_0 .net "out", 0 0, L_0x1340700; 1 drivers +L_0x133ff80 .part L_0x1340a10, 0, 1; +L_0x13400e0 .part L_0x1340a10, 1, 1; +L_0x1340220 .concat8 [ 1 1 0 0], L_0x133fec0, L_0x1340310; +L_0x1340420 .part L_0x1340a10, 2, 1; +L_0x1340580 .part L_0x1340a10, 3, 1; +L_0x1340770 .part L_0x1340220, 0, 1; +L_0x1340920 .part L_0x1340220, 1, 1; +S_0x1161080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11601b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1340b40/d .functor OR 1, L_0x1340bb0, L_0x1340d10, C4<0>, C4<0>; +L_0x1340b40 .delay 1 (30000,30000,30000) L_0x1340b40/d; +L_0x1340f40/d .functor OR 1, L_0x1341050, L_0x13411b0, C4<0>, C4<0>; +L_0x1340f40 .delay 1 (30000,30000,30000) L_0x1340f40/d; +L_0x1341330/d .functor OR 1, L_0x13413a0, L_0x1341550, C4<0>, C4<0>; +L_0x1341330 .delay 1 (30000,30000,30000) L_0x1341330/d; +v0x1161240_0 .net *"_s0", 0 0, L_0x1340b40; 1 drivers +v0x1161340_0 .net *"_s10", 0 0, L_0x1341050; 1 drivers +v0x1161420_0 .net *"_s12", 0 0, L_0x13411b0; 1 drivers +v0x11614e0_0 .net *"_s14", 0 0, L_0x13413a0; 1 drivers +v0x11615c0_0 .net *"_s16", 0 0, L_0x1341550; 1 drivers +v0x11616f0_0 .net *"_s3", 0 0, L_0x1340bb0; 1 drivers +v0x11617d0_0 .net *"_s5", 0 0, L_0x1340d10; 1 drivers +v0x11618b0_0 .net *"_s6", 0 0, L_0x1340f40; 1 drivers +v0x1161990_0 .net "in", 3 0, L_0x1341780; 1 drivers +v0x1161b00_0 .net "ors", 1 0, L_0x1340e50; 1 drivers +v0x1161be0_0 .net "out", 0 0, L_0x1341330; 1 drivers +L_0x1340bb0 .part L_0x1341780, 0, 1; +L_0x1340d10 .part L_0x1341780, 1, 1; +L_0x1340e50 .concat8 [ 1 1 0 0], L_0x1340b40, L_0x1340f40; +L_0x1341050 .part L_0x1341780, 2, 1; +L_0x13411b0 .part L_0x1341780, 3, 1; +L_0x13413a0 .part L_0x1340e50, 0, 1; +L_0x1341550 .part L_0x1340e50, 1, 1; +S_0x11624f0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1155e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x133be00/d .functor XNOR 1, L_0x13456c0, L_0x1345820, C4<0>, C4<0>; +L_0x133be00 .delay 1 (20000,20000,20000) L_0x133be00/d; +L_0x133bf80/d .functor AND 1, L_0x13456c0, L_0x133aaf0, C4<1>, C4<1>; +L_0x133bf80 .delay 1 (30000,30000,30000) L_0x133bf80/d; +L_0x133c0e0/d .functor AND 1, L_0x133be00, L_0x133a780, C4<1>, C4<1>; +L_0x133c0e0 .delay 1 (30000,30000,30000) L_0x133c0e0/d; +L_0x133c1f0/d .functor OR 1, L_0x133c0e0, L_0x133bf80, C4<0>, C4<0>; +L_0x133c1f0 .delay 1 (30000,30000,30000) L_0x133c1f0/d; +v0x11627a0_0 .net "a", 0 0, L_0x13456c0; alias, 1 drivers +v0x1162890_0 .net "a_", 0 0, L_0x133a9e0; alias, 1 drivers +v0x1162950_0 .net "b", 0 0, L_0x1345820; alias, 1 drivers +v0x1162a40_0 .net "b_", 0 0, L_0x133aaf0; alias, 1 drivers +v0x1162ae0_0 .net "carryin", 0 0, L_0x133a780; alias, 1 drivers +v0x1162c20_0 .net "eq", 0 0, L_0x133be00; 1 drivers +v0x1162ce0_0 .net "lt", 0 0, L_0x133bf80; 1 drivers +v0x1162da0_0 .net "out", 0 0, L_0x133c1f0; 1 drivers +v0x1162e60_0 .net "w0", 0 0, L_0x133c0e0; 1 drivers +S_0x11630b0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1155e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x133b9e0/d .functor OR 1, L_0x133b4e0, L_0x1164310, C4<0>, C4<0>; +L_0x133b9e0 .delay 1 (30000,30000,30000) L_0x133b9e0/d; +v0x1163ea0_0 .net "a", 0 0, L_0x13456c0; alias, 1 drivers +v0x1163ff0_0 .net "b", 0 0, L_0x133aaf0; alias, 1 drivers +v0x11640b0_0 .net "c1", 0 0, L_0x133b4e0; 1 drivers +v0x1164150_0 .net "c2", 0 0, L_0x1164310; 1 drivers +v0x1164220_0 .net "carryin", 0 0, L_0x133a780; alias, 1 drivers +v0x11643a0_0 .net "carryout", 0 0, L_0x133b9e0; 1 drivers +v0x1164440_0 .net "s1", 0 0, L_0x133b420; 1 drivers +v0x11644e0_0 .net "sum", 0 0, L_0x133b640; 1 drivers +S_0x1163300 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11630b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x133b420/d .functor XOR 1, L_0x13456c0, L_0x133aaf0, C4<0>, C4<0>; +L_0x133b420 .delay 1 (30000,30000,30000) L_0x133b420/d; +L_0x133b4e0/d .functor AND 1, L_0x13456c0, L_0x133aaf0, C4<1>, C4<1>; +L_0x133b4e0 .delay 1 (30000,30000,30000) L_0x133b4e0/d; +v0x1163560_0 .net "a", 0 0, L_0x13456c0; alias, 1 drivers +v0x1163620_0 .net "b", 0 0, L_0x133aaf0; alias, 1 drivers +v0x11636e0_0 .net "carryout", 0 0, L_0x133b4e0; alias, 1 drivers +v0x1163780_0 .net "sum", 0 0, L_0x133b420; alias, 1 drivers +S_0x11638b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11630b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x133b640/d .functor XOR 1, L_0x133b420, L_0x133a780, C4<0>, C4<0>; +L_0x133b640 .delay 1 (30000,30000,30000) L_0x133b640/d; +L_0x1164310/d .functor AND 1, L_0x133b420, L_0x133a780, C4<1>, C4<1>; +L_0x1164310 .delay 1 (30000,30000,30000) L_0x1164310/d; +v0x1163b10_0 .net "a", 0 0, L_0x133b420; alias, 1 drivers +v0x1163be0_0 .net "b", 0 0, L_0x133a780; alias, 1 drivers +v0x1163c80_0 .net "carryout", 0 0, L_0x1164310; alias, 1 drivers +v0x1163d50_0 .net "sum", 0 0, L_0x133b640; alias, 1 drivers +S_0x1166570 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1155ba0; + .timescale -9 -12; +L_0x2ac4328879c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887a10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12ddc60/d .functor OR 1, L_0x2ac4328879c8, L_0x2ac432887a10, C4<0>, C4<0>; +L_0x12ddc60 .delay 1 (30000,30000,30000) L_0x12ddc60/d; +v0x1166760_0 .net/2u *"_s0", 0 0, L_0x2ac4328879c8; 1 drivers +v0x1166840_0 .net/2u *"_s2", 0 0, L_0x2ac432887a10; 1 drivers +S_0x1166920 .scope generate, "alu_slices[19]" "alu_slices[19]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1166b30 .param/l "i" 0 3 39, +C4<010011>; +S_0x1166bf0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1166920; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1345a90/d .functor NOT 1, L_0x134ff50, C4<0>, C4<0>, C4<0>; +L_0x1345a90 .delay 1 (10000,10000,10000) L_0x1345a90/d; +L_0x1345ba0/d .functor NOT 1, L_0x13458c0, C4<0>, C4<0>, C4<0>; +L_0x1345ba0 .delay 1 (10000,10000,10000) L_0x1345ba0/d; +L_0x1346bf0/d .functor XOR 1, L_0x134ff50, L_0x13458c0, C4<0>, C4<0>; +L_0x1346bf0 .delay 1 (30000,30000,30000) L_0x1346bf0/d; +L_0x2ac432887a58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887aa0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1346cb0/d .functor OR 1, L_0x2ac432887a58, L_0x2ac432887aa0, C4<0>, C4<0>; +L_0x1346cb0 .delay 1 (30000,30000,30000) L_0x1346cb0/d; +L_0x2ac432887ae8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887b30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1347400/d .functor OR 1, L_0x2ac432887ae8, L_0x2ac432887b30, C4<0>, C4<0>; +L_0x1347400 .delay 1 (30000,30000,30000) L_0x1347400/d; +L_0x1347600/d .functor AND 1, L_0x134ff50, L_0x13458c0, C4<1>, C4<1>; +L_0x1347600 .delay 1 (30000,30000,30000) L_0x1347600/d; +L_0x2ac432887b78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887bc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13476c0/d .functor OR 1, L_0x2ac432887b78, L_0x2ac432887bc0, C4<0>, C4<0>; +L_0x13476c0 .delay 1 (30000,30000,30000) L_0x13476c0/d; +L_0x13478c0/d .functor NAND 1, L_0x134ff50, L_0x13458c0, C4<1>, C4<1>; +L_0x13478c0 .delay 1 (20000,20000,20000) L_0x13478c0/d; +L_0x2ac432887c08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887c50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13479d0/d .functor OR 1, L_0x2ac432887c08, L_0x2ac432887c50, C4<0>, C4<0>; +L_0x13479d0 .delay 1 (30000,30000,30000) L_0x13479d0/d; +L_0x1347b80/d .functor NOR 1, L_0x134ff50, L_0x13458c0, C4<0>, C4<0>; +L_0x1347b80 .delay 1 (20000,20000,20000) L_0x1347b80/d; +L_0x2ac432887c98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887ce0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1347e50/d .functor OR 1, L_0x2ac432887c98, L_0x2ac432887ce0, C4<0>, C4<0>; +L_0x1347e50 .delay 1 (30000,30000,30000) L_0x1347e50/d; +L_0x1348250/d .functor OR 1, L_0x134ff50, L_0x13458c0, C4<0>, C4<0>; +L_0x1348250 .delay 1 (30000,30000,30000) L_0x1348250/d; +L_0x2ac432887d28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887d70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13486f0/d .functor OR 1, L_0x2ac432887d28, L_0x2ac432887d70, C4<0>, C4<0>; +L_0x13486f0 .delay 1 (30000,30000,30000) L_0x13486f0/d; +L_0x134fe50/d .functor NOT 1, L_0x134c0b0, C4<0>, C4<0>, C4<0>; +L_0x134fe50 .delay 1 (10000,10000,10000) L_0x134fe50/d; +v0x1195330_0 .net "A", 0 0, L_0x134ff50; 1 drivers +v0x11953f0_0 .net "A_", 0 0, L_0x1345a90; 1 drivers +v0x11954b0_0 .net "B", 0 0, L_0x13458c0; 1 drivers +v0x1195580_0 .net "B_", 0 0, L_0x1345ba0; 1 drivers +v0x1195620_0 .net *"_s11", 0 0, L_0x1346cb0; 1 drivers +v0x1195710_0 .net/2s *"_s13", 0 0, L_0x2ac432887a58; 1 drivers +v0x11957d0_0 .net/2s *"_s15", 0 0, L_0x2ac432887aa0; 1 drivers +v0x11958b0_0 .net *"_s19", 0 0, L_0x1347400; 1 drivers +v0x1195990_0 .net/2s *"_s21", 0 0, L_0x2ac432887ae8; 1 drivers +v0x1195b00_0 .net/2s *"_s23", 0 0, L_0x2ac432887b30; 1 drivers +v0x1195be0_0 .net *"_s25", 0 0, L_0x1347600; 1 drivers +v0x1195cc0_0 .net *"_s28", 0 0, L_0x13476c0; 1 drivers +v0x1195da0_0 .net/2s *"_s30", 0 0, L_0x2ac432887b78; 1 drivers +v0x1195e80_0 .net/2s *"_s32", 0 0, L_0x2ac432887bc0; 1 drivers +v0x1195f60_0 .net *"_s34", 0 0, L_0x13478c0; 1 drivers +v0x1196040_0 .net *"_s37", 0 0, L_0x13479d0; 1 drivers +v0x1196120_0 .net/2s *"_s39", 0 0, L_0x2ac432887c08; 1 drivers +v0x11962d0_0 .net/2s *"_s41", 0 0, L_0x2ac432887c50; 1 drivers +v0x1196370_0 .net *"_s43", 0 0, L_0x1347b80; 1 drivers +v0x1196450_0 .net *"_s46", 0 0, L_0x1347e50; 1 drivers +v0x1196530_0 .net/2s *"_s48", 0 0, L_0x2ac432887c98; 1 drivers +v0x1196610_0 .net/2s *"_s50", 0 0, L_0x2ac432887ce0; 1 drivers +v0x11966f0_0 .net *"_s52", 0 0, L_0x1348250; 1 drivers +v0x11967d0_0 .net *"_s56", 0 0, L_0x13486f0; 1 drivers +v0x11968b0_0 .net/2s *"_s59", 0 0, L_0x2ac432887d28; 1 drivers +v0x1196990_0 .net/2s *"_s61", 0 0, L_0x2ac432887d70; 1 drivers +v0x1196a70_0 .net *"_s8", 0 0, L_0x1346bf0; 1 drivers +v0x1196b50_0 .net "carryin", 0 0, L_0x1345960; 1 drivers +v0x1196bf0_0 .net "carryout", 0 0, L_0x134faf0; 1 drivers +v0x1196c90_0 .net "carryouts", 7 0, L_0x1348360; 1 drivers +v0x1196da0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1196e60_0 .net "result", 0 0, L_0x134c0b0; 1 drivers +v0x1196f50_0 .net "results", 7 0, L_0x1348020; 1 drivers +v0x1196230_0 .net "zero", 0 0, L_0x134fe50; 1 drivers +LS_0x1348020_0_0 .concat8 [ 1 1 1 1], L_0x13460c0, L_0x13466f0, L_0x1346bf0, L_0x1347400; +LS_0x1348020_0_4 .concat8 [ 1 1 1 1], L_0x1347600, L_0x13478c0, L_0x1347b80, L_0x1348250; +L_0x1348020 .concat8 [ 4 4 0 0], LS_0x1348020_0_0, LS_0x1348020_0_4; +LS_0x1348360_0_0 .concat8 [ 1 1 1 1], L_0x1346370, L_0x1346a90, L_0x1346cb0, L_0x1347250; +LS_0x1348360_0_4 .concat8 [ 1 1 1 1], L_0x13476c0, L_0x13479d0, L_0x1347e50, L_0x13486f0; +L_0x1348360 .concat8 [ 4 4 0 0], LS_0x1348360_0_0, LS_0x1348360_0_4; +S_0x1166e70 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1166bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1346370/d .functor OR 1, L_0x1345e50, L_0x1346210, C4<0>, C4<0>; +L_0x1346370 .delay 1 (30000,30000,30000) L_0x1346370/d; +v0x1167ca0_0 .net "a", 0 0, L_0x134ff50; alias, 1 drivers +v0x1167d60_0 .net "b", 0 0, L_0x13458c0; alias, 1 drivers +v0x1167e30_0 .net "c1", 0 0, L_0x1345e50; 1 drivers +v0x1167f30_0 .net "c2", 0 0, L_0x1346210; 1 drivers +v0x1168000_0 .net "carryin", 0 0, L_0x1345960; alias, 1 drivers +v0x11680f0_0 .net "carryout", 0 0, L_0x1346370; 1 drivers +v0x1168190_0 .net "s1", 0 0, L_0x1345d90; 1 drivers +v0x1168280_0 .net "sum", 0 0, L_0x13460c0; 1 drivers +S_0x11670e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1166e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1345d90/d .functor XOR 1, L_0x134ff50, L_0x13458c0, C4<0>, C4<0>; +L_0x1345d90 .delay 1 (30000,30000,30000) L_0x1345d90/d; +L_0x1345e50/d .functor AND 1, L_0x134ff50, L_0x13458c0, C4<1>, C4<1>; +L_0x1345e50 .delay 1 (30000,30000,30000) L_0x1345e50/d; +v0x1167340_0 .net "a", 0 0, L_0x134ff50; alias, 1 drivers +v0x1167420_0 .net "b", 0 0, L_0x13458c0; alias, 1 drivers +v0x11674e0_0 .net "carryout", 0 0, L_0x1345e50; alias, 1 drivers +v0x1167580_0 .net "sum", 0 0, L_0x1345d90; alias, 1 drivers +S_0x11676c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1166e70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13460c0/d .functor XOR 1, L_0x1345d90, L_0x1345960, C4<0>, C4<0>; +L_0x13460c0 .delay 1 (30000,30000,30000) L_0x13460c0/d; +L_0x1346210/d .functor AND 1, L_0x1345d90, L_0x1345960, C4<1>, C4<1>; +L_0x1346210 .delay 1 (30000,30000,30000) L_0x1346210/d; +v0x1167920_0 .net "a", 0 0, L_0x1345d90; alias, 1 drivers +v0x11679c0_0 .net "b", 0 0, L_0x1345960; alias, 1 drivers +v0x1167a60_0 .net "carryout", 0 0, L_0x1346210; alias, 1 drivers +v0x1167b30_0 .net "sum", 0 0, L_0x13460c0; alias, 1 drivers +S_0x1168350 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1166bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x118d750_0 .net "ands", 7 0, L_0x134daf0; 1 drivers +v0x118d860_0 .net "in", 7 0, L_0x1348360; alias, 1 drivers +v0x118d920_0 .net "out", 0 0, L_0x134faf0; alias, 1 drivers +v0x118d9f0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1168570 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1168350; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x116aca0_0 .net "A", 7 0, L_0x1348360; alias, 1 drivers +v0x116ada0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x116ae60_0 .net *"_s0", 0 0, L_0x134c410; 1 drivers +v0x116af20_0 .net *"_s12", 0 0, L_0x134cd80; 1 drivers +v0x116b000_0 .net *"_s16", 0 0, L_0x134d0e0; 1 drivers +v0x116b130_0 .net *"_s20", 0 0, L_0x134d4b0; 1 drivers +v0x116b210_0 .net *"_s24", 0 0, L_0x134d7e0; 1 drivers +v0x116b2f0_0 .net *"_s28", 0 0, L_0x134d770; 1 drivers +v0x116b3d0_0 .net *"_s4", 0 0, L_0x134c760; 1 drivers +v0x116b540_0 .net *"_s8", 0 0, L_0x134ca70; 1 drivers +v0x116b620_0 .net "out", 7 0, L_0x134daf0; alias, 1 drivers +L_0x134c4d0 .part L_0x1348360, 0, 1; +L_0x134c6c0 .part v0x127a150_0, 0, 1; +L_0x134c820 .part L_0x1348360, 1, 1; +L_0x134c980 .part v0x127a150_0, 1, 1; +L_0x134cb30 .part L_0x1348360, 2, 1; +L_0x134cc90 .part v0x127a150_0, 2, 1; +L_0x134ce40 .part L_0x1348360, 3, 1; +L_0x134cfa0 .part v0x127a150_0, 3, 1; +L_0x134d1a0 .part L_0x1348360, 4, 1; +L_0x134d410 .part v0x127a150_0, 4, 1; +L_0x134d520 .part L_0x1348360, 5, 1; +L_0x134d680 .part v0x127a150_0, 5, 1; +L_0x134d8a0 .part L_0x1348360, 6, 1; +L_0x134da00 .part v0x127a150_0, 6, 1; +LS_0x134daf0_0_0 .concat8 [ 1 1 1 1], L_0x134c410, L_0x134c760, L_0x134ca70, L_0x134cd80; +LS_0x134daf0_0_4 .concat8 [ 1 1 1 1], L_0x134d0e0, L_0x134d4b0, L_0x134d7e0, L_0x134d770; +L_0x134daf0 .concat8 [ 4 4 0 0], LS_0x134daf0_0_0, LS_0x134daf0_0_4; +L_0x134deb0 .part L_0x1348360, 7, 1; +L_0x134e0a0 .part v0x127a150_0, 7, 1; +S_0x11687d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x11689e0 .param/l "i" 0 4 54, +C4<00>; +L_0x134c410/d .functor AND 1, L_0x134c4d0, L_0x134c6c0, C4<1>, C4<1>; +L_0x134c410 .delay 1 (30000,30000,30000) L_0x134c410/d; +v0x1168ac0_0 .net *"_s0", 0 0, L_0x134c4d0; 1 drivers +v0x1168ba0_0 .net *"_s1", 0 0, L_0x134c6c0; 1 drivers +S_0x1168c80 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x1168e90 .param/l "i" 0 4 54, +C4<01>; +L_0x134c760/d .functor AND 1, L_0x134c820, L_0x134c980, C4<1>, C4<1>; +L_0x134c760 .delay 1 (30000,30000,30000) L_0x134c760/d; +v0x1168f50_0 .net *"_s0", 0 0, L_0x134c820; 1 drivers +v0x1169030_0 .net *"_s1", 0 0, L_0x134c980; 1 drivers +S_0x1169110 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x1169320 .param/l "i" 0 4 54, +C4<010>; +L_0x134ca70/d .functor AND 1, L_0x134cb30, L_0x134cc90, C4<1>, C4<1>; +L_0x134ca70 .delay 1 (30000,30000,30000) L_0x134ca70/d; +v0x11693c0_0 .net *"_s0", 0 0, L_0x134cb30; 1 drivers +v0x11694a0_0 .net *"_s1", 0 0, L_0x134cc90; 1 drivers +S_0x1169580 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x1169790 .param/l "i" 0 4 54, +C4<011>; +L_0x134cd80/d .functor AND 1, L_0x134ce40, L_0x134cfa0, C4<1>, C4<1>; +L_0x134cd80 .delay 1 (30000,30000,30000) L_0x134cd80/d; +v0x1169850_0 .net *"_s0", 0 0, L_0x134ce40; 1 drivers +v0x1169930_0 .net *"_s1", 0 0, L_0x134cfa0; 1 drivers +S_0x1169a10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x1169c70 .param/l "i" 0 4 54, +C4<0100>; +L_0x134d0e0/d .functor AND 1, L_0x134d1a0, L_0x134d410, C4<1>, C4<1>; +L_0x134d0e0 .delay 1 (30000,30000,30000) L_0x134d0e0/d; +v0x1169d30_0 .net *"_s0", 0 0, L_0x134d1a0; 1 drivers +v0x1169e10_0 .net *"_s1", 0 0, L_0x134d410; 1 drivers +S_0x1169ef0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x116a100 .param/l "i" 0 4 54, +C4<0101>; +L_0x134d4b0/d .functor AND 1, L_0x134d520, L_0x134d680, C4<1>, C4<1>; +L_0x134d4b0 .delay 1 (30000,30000,30000) L_0x134d4b0/d; +v0x116a1c0_0 .net *"_s0", 0 0, L_0x134d520; 1 drivers +v0x116a2a0_0 .net *"_s1", 0 0, L_0x134d680; 1 drivers +S_0x116a380 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x116a590 .param/l "i" 0 4 54, +C4<0110>; +L_0x134d7e0/d .functor AND 1, L_0x134d8a0, L_0x134da00, C4<1>, C4<1>; +L_0x134d7e0 .delay 1 (30000,30000,30000) L_0x134d7e0/d; +v0x116a650_0 .net *"_s0", 0 0, L_0x134d8a0; 1 drivers +v0x116a730_0 .net *"_s1", 0 0, L_0x134da00; 1 drivers +S_0x116a810 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1168570; + .timescale -9 -12; +P_0x116aa20 .param/l "i" 0 4 54, +C4<0111>; +L_0x134d770/d .functor AND 1, L_0x134deb0, L_0x134e0a0, C4<1>, C4<1>; +L_0x134d770 .delay 1 (30000,30000,30000) L_0x134d770/d; +v0x116aae0_0 .net *"_s0", 0 0, L_0x134deb0; 1 drivers +v0x116abc0_0 .net *"_s1", 0 0, L_0x134e0a0; 1 drivers +S_0x116b780 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1168350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x134faf0/d .functor OR 1, L_0x134fbb0, L_0x134fd60, C4<0>, C4<0>; +L_0x134faf0 .delay 1 (30000,30000,30000) L_0x134faf0/d; +v0x118d2b0_0 .net *"_s10", 0 0, L_0x134fbb0; 1 drivers +v0x118d390_0 .net *"_s12", 0 0, L_0x134fd60; 1 drivers +v0x118d470_0 .net "in", 7 0, L_0x134daf0; alias, 1 drivers +v0x118d570_0 .net "ors", 1 0, L_0x134f910; 1 drivers +v0x118d630_0 .net "out", 0 0, L_0x134faf0; alias, 1 drivers +L_0x134ece0 .part L_0x134daf0, 0, 4; +L_0x134f910 .concat8 [ 1 1 0 0], L_0x134e9d0, L_0x134f600; +L_0x134fa50 .part L_0x134daf0, 4, 4; +L_0x134fbb0 .part L_0x134f910, 0, 1; +L_0x134fd60 .part L_0x134f910, 1, 1; +S_0x116b940 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x116b780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x134e190/d .functor OR 1, L_0x134e250, L_0x134e3b0, C4<0>, C4<0>; +L_0x134e190 .delay 1 (30000,30000,30000) L_0x134e190/d; +L_0x134e5e0/d .functor OR 1, L_0x134e6f0, L_0x134e850, C4<0>, C4<0>; +L_0x134e5e0 .delay 1 (30000,30000,30000) L_0x134e5e0/d; +L_0x134e9d0/d .functor OR 1, L_0x134ea40, L_0x134ebf0, C4<0>, C4<0>; +L_0x134e9d0 .delay 1 (30000,30000,30000) L_0x134e9d0/d; +v0x116bb90_0 .net *"_s0", 0 0, L_0x134e190; 1 drivers +v0x116bc90_0 .net *"_s10", 0 0, L_0x134e6f0; 1 drivers +v0x116bd70_0 .net *"_s12", 0 0, L_0x134e850; 1 drivers +v0x116be30_0 .net *"_s14", 0 0, L_0x134ea40; 1 drivers +v0x116bf10_0 .net *"_s16", 0 0, L_0x134ebf0; 1 drivers +v0x116c040_0 .net *"_s3", 0 0, L_0x134e250; 1 drivers +v0x116c120_0 .net *"_s5", 0 0, L_0x134e3b0; 1 drivers +v0x116c200_0 .net *"_s6", 0 0, L_0x134e5e0; 1 drivers +v0x116c2e0_0 .net "in", 3 0, L_0x134ece0; 1 drivers +v0x116c450_0 .net "ors", 1 0, L_0x134e4f0; 1 drivers +v0x116c530_0 .net "out", 0 0, L_0x134e9d0; 1 drivers +L_0x134e250 .part L_0x134ece0, 0, 1; +L_0x134e3b0 .part L_0x134ece0, 1, 1; +L_0x134e4f0 .concat8 [ 1 1 0 0], L_0x134e190, L_0x134e5e0; +L_0x134e6f0 .part L_0x134ece0, 2, 1; +L_0x134e850 .part L_0x134ece0, 3, 1; +L_0x134ea40 .part L_0x134e4f0, 0, 1; +L_0x134ebf0 .part L_0x134e4f0, 1, 1; +S_0x116c650 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x116b780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x134ee10/d .functor OR 1, L_0x134ee80, L_0x134efe0, C4<0>, C4<0>; +L_0x134ee10 .delay 1 (30000,30000,30000) L_0x134ee10/d; +L_0x134f210/d .functor OR 1, L_0x134f320, L_0x134f480, C4<0>, C4<0>; +L_0x134f210 .delay 1 (30000,30000,30000) L_0x134f210/d; +L_0x134f600/d .functor OR 1, L_0x134f670, L_0x134f820, C4<0>, C4<0>; +L_0x134f600 .delay 1 (30000,30000,30000) L_0x134f600/d; +v0x116c810_0 .net *"_s0", 0 0, L_0x134ee10; 1 drivers +v0x116c910_0 .net *"_s10", 0 0, L_0x134f320; 1 drivers +v0x116c9f0_0 .net *"_s12", 0 0, L_0x134f480; 1 drivers +v0x116cab0_0 .net *"_s14", 0 0, L_0x134f670; 1 drivers +v0x116cb90_0 .net *"_s16", 0 0, L_0x134f820; 1 drivers +v0x116ccc0_0 .net *"_s3", 0 0, L_0x134ee80; 1 drivers +v0x116cda0_0 .net *"_s5", 0 0, L_0x134efe0; 1 drivers +v0x118ce60_0 .net *"_s6", 0 0, L_0x134f210; 1 drivers +v0x118cf40_0 .net "in", 3 0, L_0x134fa50; 1 drivers +v0x118d0b0_0 .net "ors", 1 0, L_0x134f120; 1 drivers +v0x118d190_0 .net "out", 0 0, L_0x134f600; 1 drivers +L_0x134ee80 .part L_0x134fa50, 0, 1; +L_0x134efe0 .part L_0x134fa50, 1, 1; +L_0x134f120 .concat8 [ 1 1 0 0], L_0x134ee10, L_0x134f210; +L_0x134f320 .part L_0x134fa50, 2, 1; +L_0x134f480 .part L_0x134fa50, 3, 1; +L_0x134f670 .part L_0x134f120, 0, 1; +L_0x134f820 .part L_0x134f120, 1, 1; +S_0x118dad0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1166bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1192f00_0 .net "ands", 7 0, L_0x134a0b0; 1 drivers +v0x1193010_0 .net "in", 7 0, L_0x1348020; alias, 1 drivers +v0x11930d0_0 .net "out", 0 0, L_0x134c0b0; alias, 1 drivers +v0x11931a0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x118dd20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x118dad0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1190460_0 .net "A", 7 0, L_0x1348020; alias, 1 drivers +v0x1190560_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1190620_0 .net *"_s0", 0 0, L_0x13488a0; 1 drivers +v0x11906e0_0 .net *"_s12", 0 0, L_0x1349260; 1 drivers +v0x11907c0_0 .net *"_s16", 0 0, L_0x13495c0; 1 drivers +v0x11908f0_0 .net *"_s20", 0 0, L_0x13499f0; 1 drivers +v0x11909d0_0 .net *"_s24", 0 0, L_0x1349d20; 1 drivers +v0x1190ab0_0 .net *"_s28", 0 0, L_0x1349cb0; 1 drivers +v0x1190b90_0 .net *"_s4", 0 0, L_0x1348c40; 1 drivers +v0x1190d00_0 .net *"_s8", 0 0, L_0x1348f50; 1 drivers +v0x1190de0_0 .net "out", 7 0, L_0x134a0b0; alias, 1 drivers +L_0x13489b0 .part L_0x1348020, 0, 1; +L_0x1348ba0 .part v0x127a150_0, 0, 1; +L_0x1348d00 .part L_0x1348020, 1, 1; +L_0x1348e60 .part v0x127a150_0, 1, 1; +L_0x1349010 .part L_0x1348020, 2, 1; +L_0x1349170 .part v0x127a150_0, 2, 1; +L_0x1349320 .part L_0x1348020, 3, 1; +L_0x1349480 .part v0x127a150_0, 3, 1; +L_0x1349680 .part L_0x1348020, 4, 1; +L_0x13498f0 .part v0x127a150_0, 4, 1; +L_0x1349a60 .part L_0x1348020, 5, 1; +L_0x1349bc0 .part v0x127a150_0, 5, 1; +L_0x1349de0 .part L_0x1348020, 6, 1; +L_0x1349f40 .part v0x127a150_0, 6, 1; +LS_0x134a0b0_0_0 .concat8 [ 1 1 1 1], L_0x13488a0, L_0x1348c40, L_0x1348f50, L_0x1349260; +LS_0x134a0b0_0_4 .concat8 [ 1 1 1 1], L_0x13495c0, L_0x13499f0, L_0x1349d20, L_0x1349cb0; +L_0x134a0b0 .concat8 [ 4 4 0 0], LS_0x134a0b0_0_0, LS_0x134a0b0_0_4; +L_0x134a470 .part L_0x1348020, 7, 1; +L_0x134a660 .part v0x127a150_0, 7, 1; +S_0x118df60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118e170 .param/l "i" 0 4 54, +C4<00>; +L_0x13488a0/d .functor AND 1, L_0x13489b0, L_0x1348ba0, C4<1>, C4<1>; +L_0x13488a0 .delay 1 (30000,30000,30000) L_0x13488a0/d; +v0x118e250_0 .net *"_s0", 0 0, L_0x13489b0; 1 drivers +v0x118e330_0 .net *"_s1", 0 0, L_0x1348ba0; 1 drivers +S_0x118e410 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118e620 .param/l "i" 0 4 54, +C4<01>; +L_0x1348c40/d .functor AND 1, L_0x1348d00, L_0x1348e60, C4<1>, C4<1>; +L_0x1348c40 .delay 1 (30000,30000,30000) L_0x1348c40/d; +v0x118e6e0_0 .net *"_s0", 0 0, L_0x1348d00; 1 drivers +v0x118e7c0_0 .net *"_s1", 0 0, L_0x1348e60; 1 drivers +S_0x118e8a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118eae0 .param/l "i" 0 4 54, +C4<010>; +L_0x1348f50/d .functor AND 1, L_0x1349010, L_0x1349170, C4<1>, C4<1>; +L_0x1348f50 .delay 1 (30000,30000,30000) L_0x1348f50/d; +v0x118eb80_0 .net *"_s0", 0 0, L_0x1349010; 1 drivers +v0x118ec60_0 .net *"_s1", 0 0, L_0x1349170; 1 drivers +S_0x118ed40 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118ef50 .param/l "i" 0 4 54, +C4<011>; +L_0x1349260/d .functor AND 1, L_0x1349320, L_0x1349480, C4<1>, C4<1>; +L_0x1349260 .delay 1 (30000,30000,30000) L_0x1349260/d; +v0x118f010_0 .net *"_s0", 0 0, L_0x1349320; 1 drivers +v0x118f0f0_0 .net *"_s1", 0 0, L_0x1349480; 1 drivers +S_0x118f1d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118f430 .param/l "i" 0 4 54, +C4<0100>; +L_0x13495c0/d .functor AND 1, L_0x1349680, L_0x13498f0, C4<1>, C4<1>; +L_0x13495c0 .delay 1 (30000,30000,30000) L_0x13495c0/d; +v0x118f4f0_0 .net *"_s0", 0 0, L_0x1349680; 1 drivers +v0x118f5d0_0 .net *"_s1", 0 0, L_0x13498f0; 1 drivers +S_0x118f6b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118f8c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13499f0/d .functor AND 1, L_0x1349a60, L_0x1349bc0, C4<1>, C4<1>; +L_0x13499f0 .delay 1 (30000,30000,30000) L_0x13499f0/d; +v0x118f980_0 .net *"_s0", 0 0, L_0x1349a60; 1 drivers +v0x118fa60_0 .net *"_s1", 0 0, L_0x1349bc0; 1 drivers +S_0x118fb40 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x118fd50 .param/l "i" 0 4 54, +C4<0110>; +L_0x1349d20/d .functor AND 1, L_0x1349de0, L_0x1349f40, C4<1>, C4<1>; +L_0x1349d20 .delay 1 (30000,30000,30000) L_0x1349d20/d; +v0x118fe10_0 .net *"_s0", 0 0, L_0x1349de0; 1 drivers +v0x118fef0_0 .net *"_s1", 0 0, L_0x1349f40; 1 drivers +S_0x118ffd0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x118dd20; + .timescale -9 -12; +P_0x11901e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1349cb0/d .functor AND 1, L_0x134a470, L_0x134a660, C4<1>, C4<1>; +L_0x1349cb0 .delay 1 (30000,30000,30000) L_0x1349cb0/d; +v0x11902a0_0 .net *"_s0", 0 0, L_0x134a470; 1 drivers +v0x1190380_0 .net *"_s1", 0 0, L_0x134a660; 1 drivers +S_0x1190f40 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x118dad0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x134c0b0/d .functor OR 1, L_0x134c170, L_0x134c320, C4<0>, C4<0>; +L_0x134c0b0 .delay 1 (30000,30000,30000) L_0x134c0b0/d; +v0x1192a90_0 .net *"_s10", 0 0, L_0x134c170; 1 drivers +v0x1192b70_0 .net *"_s12", 0 0, L_0x134c320; 1 drivers +v0x1192c50_0 .net "in", 7 0, L_0x134a0b0; alias, 1 drivers +v0x1192d20_0 .net "ors", 1 0, L_0x134bed0; 1 drivers +v0x1192de0_0 .net "out", 0 0, L_0x134c0b0; alias, 1 drivers +L_0x134b2a0 .part L_0x134a0b0, 0, 4; +L_0x134bed0 .concat8 [ 1 1 0 0], L_0x134af90, L_0x134bbc0; +L_0x134c010 .part L_0x134a0b0, 4, 4; +L_0x134c170 .part L_0x134bed0, 0, 1; +L_0x134c320 .part L_0x134bed0, 1, 1; +S_0x1191100 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1190f40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x134a750/d .functor OR 1, L_0x134a810, L_0x134a970, C4<0>, C4<0>; +L_0x134a750 .delay 1 (30000,30000,30000) L_0x134a750/d; +L_0x134aba0/d .functor OR 1, L_0x134acb0, L_0x134ae10, C4<0>, C4<0>; +L_0x134aba0 .delay 1 (30000,30000,30000) L_0x134aba0/d; +L_0x134af90/d .functor OR 1, L_0x134b000, L_0x134b1b0, C4<0>, C4<0>; +L_0x134af90 .delay 1 (30000,30000,30000) L_0x134af90/d; +v0x1191350_0 .net *"_s0", 0 0, L_0x134a750; 1 drivers +v0x1191450_0 .net *"_s10", 0 0, L_0x134acb0; 1 drivers +v0x1191530_0 .net *"_s12", 0 0, L_0x134ae10; 1 drivers +v0x11915f0_0 .net *"_s14", 0 0, L_0x134b000; 1 drivers +v0x11916d0_0 .net *"_s16", 0 0, L_0x134b1b0; 1 drivers +v0x1191800_0 .net *"_s3", 0 0, L_0x134a810; 1 drivers +v0x11918e0_0 .net *"_s5", 0 0, L_0x134a970; 1 drivers +v0x11919c0_0 .net *"_s6", 0 0, L_0x134aba0; 1 drivers +v0x1191aa0_0 .net "in", 3 0, L_0x134b2a0; 1 drivers +v0x1191c10_0 .net "ors", 1 0, L_0x134aab0; 1 drivers +v0x1191cf0_0 .net "out", 0 0, L_0x134af90; 1 drivers +L_0x134a810 .part L_0x134b2a0, 0, 1; +L_0x134a970 .part L_0x134b2a0, 1, 1; +L_0x134aab0 .concat8 [ 1 1 0 0], L_0x134a750, L_0x134aba0; +L_0x134acb0 .part L_0x134b2a0, 2, 1; +L_0x134ae10 .part L_0x134b2a0, 3, 1; +L_0x134b000 .part L_0x134aab0, 0, 1; +L_0x134b1b0 .part L_0x134aab0, 1, 1; +S_0x1191e10 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1190f40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x134b3d0/d .functor OR 1, L_0x134b440, L_0x134b5a0, C4<0>, C4<0>; +L_0x134b3d0 .delay 1 (30000,30000,30000) L_0x134b3d0/d; +L_0x134b7d0/d .functor OR 1, L_0x134b8e0, L_0x134ba40, C4<0>, C4<0>; +L_0x134b7d0 .delay 1 (30000,30000,30000) L_0x134b7d0/d; +L_0x134bbc0/d .functor OR 1, L_0x134bc30, L_0x134bde0, C4<0>, C4<0>; +L_0x134bbc0 .delay 1 (30000,30000,30000) L_0x134bbc0/d; +v0x1191fd0_0 .net *"_s0", 0 0, L_0x134b3d0; 1 drivers +v0x11920d0_0 .net *"_s10", 0 0, L_0x134b8e0; 1 drivers +v0x11921b0_0 .net *"_s12", 0 0, L_0x134ba40; 1 drivers +v0x1192270_0 .net *"_s14", 0 0, L_0x134bc30; 1 drivers +v0x1192350_0 .net *"_s16", 0 0, L_0x134bde0; 1 drivers +v0x1192480_0 .net *"_s3", 0 0, L_0x134b440; 1 drivers +v0x1192560_0 .net *"_s5", 0 0, L_0x134b5a0; 1 drivers +v0x1192640_0 .net *"_s6", 0 0, L_0x134b7d0; 1 drivers +v0x1192720_0 .net "in", 3 0, L_0x134c010; 1 drivers +v0x1192890_0 .net "ors", 1 0, L_0x134b6e0; 1 drivers +v0x1192970_0 .net "out", 0 0, L_0x134bbc0; 1 drivers +L_0x134b440 .part L_0x134c010, 0, 1; +L_0x134b5a0 .part L_0x134c010, 1, 1; +L_0x134b6e0 .concat8 [ 1 1 0 0], L_0x134b3d0, L_0x134b7d0; +L_0x134b8e0 .part L_0x134c010, 2, 1; +L_0x134ba40 .part L_0x134c010, 3, 1; +L_0x134bc30 .part L_0x134b6e0, 0, 1; +L_0x134bde0 .part L_0x134b6e0, 1, 1; +S_0x1193280 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1166bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1346eb0/d .functor XNOR 1, L_0x134ff50, L_0x13458c0, C4<0>, C4<0>; +L_0x1346eb0 .delay 1 (20000,20000,20000) L_0x1346eb0/d; +L_0x1347030/d .functor AND 1, L_0x134ff50, L_0x1345ba0, C4<1>, C4<1>; +L_0x1347030 .delay 1 (30000,30000,30000) L_0x1347030/d; +L_0x13470f0/d .functor AND 1, L_0x1346eb0, L_0x1345960, C4<1>, C4<1>; +L_0x13470f0 .delay 1 (30000,30000,30000) L_0x13470f0/d; +L_0x1347250/d .functor OR 1, L_0x13470f0, L_0x1347030, C4<0>, C4<0>; +L_0x1347250 .delay 1 (30000,30000,30000) L_0x1347250/d; +v0x1193530_0 .net "a", 0 0, L_0x134ff50; alias, 1 drivers +v0x1193620_0 .net "a_", 0 0, L_0x1345a90; alias, 1 drivers +v0x11936e0_0 .net "b", 0 0, L_0x13458c0; alias, 1 drivers +v0x11937d0_0 .net "b_", 0 0, L_0x1345ba0; alias, 1 drivers +v0x1193870_0 .net "carryin", 0 0, L_0x1345960; alias, 1 drivers +v0x11939b0_0 .net "eq", 0 0, L_0x1346eb0; 1 drivers +v0x1193a70_0 .net "lt", 0 0, L_0x1347030; 1 drivers +v0x1193b30_0 .net "out", 0 0, L_0x1347250; 1 drivers +v0x1193bf0_0 .net "w0", 0 0, L_0x13470f0; 1 drivers +S_0x1193e40 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1166bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1346a90/d .functor OR 1, L_0x1346590, L_0x11950a0, C4<0>, C4<0>; +L_0x1346a90 .delay 1 (30000,30000,30000) L_0x1346a90/d; +v0x1194c30_0 .net "a", 0 0, L_0x134ff50; alias, 1 drivers +v0x1194d80_0 .net "b", 0 0, L_0x1345ba0; alias, 1 drivers +v0x1194e40_0 .net "c1", 0 0, L_0x1346590; 1 drivers +v0x1194ee0_0 .net "c2", 0 0, L_0x11950a0; 1 drivers +v0x1194fb0_0 .net "carryin", 0 0, L_0x1345960; alias, 1 drivers +v0x1195130_0 .net "carryout", 0 0, L_0x1346a90; 1 drivers +v0x11951d0_0 .net "s1", 0 0, L_0x13464d0; 1 drivers +v0x1195270_0 .net "sum", 0 0, L_0x13466f0; 1 drivers +S_0x1194090 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1193e40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13464d0/d .functor XOR 1, L_0x134ff50, L_0x1345ba0, C4<0>, C4<0>; +L_0x13464d0 .delay 1 (30000,30000,30000) L_0x13464d0/d; +L_0x1346590/d .functor AND 1, L_0x134ff50, L_0x1345ba0, C4<1>, C4<1>; +L_0x1346590 .delay 1 (30000,30000,30000) L_0x1346590/d; +v0x11942f0_0 .net "a", 0 0, L_0x134ff50; alias, 1 drivers +v0x11943b0_0 .net "b", 0 0, L_0x1345ba0; alias, 1 drivers +v0x1194470_0 .net "carryout", 0 0, L_0x1346590; alias, 1 drivers +v0x1194510_0 .net "sum", 0 0, L_0x13464d0; alias, 1 drivers +S_0x1194640 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1193e40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13466f0/d .functor XOR 1, L_0x13464d0, L_0x1345960, C4<0>, C4<0>; +L_0x13466f0 .delay 1 (30000,30000,30000) L_0x13466f0/d; +L_0x11950a0/d .functor AND 1, L_0x13464d0, L_0x1345960, C4<1>, C4<1>; +L_0x11950a0 .delay 1 (30000,30000,30000) L_0x11950a0/d; +v0x11948a0_0 .net "a", 0 0, L_0x13464d0; alias, 1 drivers +v0x1194970_0 .net "b", 0 0, L_0x1345960; alias, 1 drivers +v0x1194a10_0 .net "carryout", 0 0, L_0x11950a0; alias, 1 drivers +v0x1194ae0_0 .net "sum", 0 0, L_0x13466f0; alias, 1 drivers +S_0x1197300 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1166920; + .timescale -9 -12; +L_0x2ac432887db8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887e00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1346050/d .functor OR 1, L_0x2ac432887db8, L_0x2ac432887e00, C4<0>, C4<0>; +L_0x1346050 .delay 1 (30000,30000,30000) L_0x1346050/d; +v0x11974f0_0 .net/2u *"_s0", 0 0, L_0x2ac432887db8; 1 drivers +v0x11975d0_0 .net/2u *"_s2", 0 0, L_0x2ac432887e00; 1 drivers +S_0x11976b0 .scope generate, "alu_slices[20]" "alu_slices[20]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11978c0 .param/l "i" 0 3 39, +C4<010100>; +S_0x1197980 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11976b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13502f0/d .functor NOT 1, L_0x135a7b0, C4<0>, C4<0>, C4<0>; +L_0x13502f0 .delay 1 (10000,10000,10000) L_0x13502f0/d; +L_0x1350400/d .functor NOT 1, L_0x135a910, C4<0>, C4<0>, C4<0>; +L_0x1350400 .delay 1 (10000,10000,10000) L_0x1350400/d; +L_0x1351400/d .functor XOR 1, L_0x135a7b0, L_0x135a910, C4<0>, C4<0>; +L_0x1351400 .delay 1 (30000,30000,30000) L_0x1351400/d; +L_0x2ac432887e48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887e90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13514c0/d .functor OR 1, L_0x2ac432887e48, L_0x2ac432887e90, C4<0>, C4<0>; +L_0x13514c0 .delay 1 (30000,30000,30000) L_0x13514c0/d; +L_0x2ac432887ed8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887f20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1351c60/d .functor OR 1, L_0x2ac432887ed8, L_0x2ac432887f20, C4<0>, C4<0>; +L_0x1351c60 .delay 1 (30000,30000,30000) L_0x1351c60/d; +L_0x1351e60/d .functor AND 1, L_0x135a7b0, L_0x135a910, C4<1>, C4<1>; +L_0x1351e60 .delay 1 (30000,30000,30000) L_0x1351e60/d; +L_0x2ac432887f68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432887fb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1351f20/d .functor OR 1, L_0x2ac432887f68, L_0x2ac432887fb0, C4<0>, C4<0>; +L_0x1351f20 .delay 1 (30000,30000,30000) L_0x1351f20/d; +L_0x1352120/d .functor NAND 1, L_0x135a7b0, L_0x135a910, C4<1>, C4<1>; +L_0x1352120 .delay 1 (20000,20000,20000) L_0x1352120/d; +L_0x2ac432887ff8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888040 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1352230/d .functor OR 1, L_0x2ac432887ff8, L_0x2ac432888040, C4<0>, C4<0>; +L_0x1352230 .delay 1 (30000,30000,30000) L_0x1352230/d; +L_0x13523e0/d .functor NOR 1, L_0x135a7b0, L_0x135a910, C4<0>, C4<0>; +L_0x13523e0 .delay 1 (20000,20000,20000) L_0x13523e0/d; +L_0x2ac432888088 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328880d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13526b0/d .functor OR 1, L_0x2ac432888088, L_0x2ac4328880d0, C4<0>, C4<0>; +L_0x13526b0 .delay 1 (30000,30000,30000) L_0x13526b0/d; +L_0x1352ab0/d .functor OR 1, L_0x135a7b0, L_0x135a910, C4<0>, C4<0>; +L_0x1352ab0 .delay 1 (30000,30000,30000) L_0x1352ab0/d; +L_0x2ac432888118 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888160 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1352f50/d .functor OR 1, L_0x2ac432888118, L_0x2ac432888160, C4<0>, C4<0>; +L_0x1352f50 .delay 1 (30000,30000,30000) L_0x1352f50/d; +L_0x135a6b0/d .functor NOT 1, L_0x1356910, C4<0>, C4<0>, C4<0>; +L_0x135a6b0 .delay 1 (10000,10000,10000) L_0x135a6b0/d; +v0x11a60b0_0 .net "A", 0 0, L_0x135a7b0; 1 drivers +v0x11a6170_0 .net "A_", 0 0, L_0x13502f0; 1 drivers +v0x11a6230_0 .net "B", 0 0, L_0x135a910; 1 drivers +v0x11a6300_0 .net "B_", 0 0, L_0x1350400; 1 drivers +v0x11a63a0_0 .net *"_s11", 0 0, L_0x13514c0; 1 drivers +v0x11a6490_0 .net/2s *"_s13", 0 0, L_0x2ac432887e48; 1 drivers +v0x11a6550_0 .net/2s *"_s15", 0 0, L_0x2ac432887e90; 1 drivers +v0x11a6630_0 .net *"_s19", 0 0, L_0x1351c60; 1 drivers +v0x11a6710_0 .net/2s *"_s21", 0 0, L_0x2ac432887ed8; 1 drivers +v0x11a6880_0 .net/2s *"_s23", 0 0, L_0x2ac432887f20; 1 drivers +v0x11a6960_0 .net *"_s25", 0 0, L_0x1351e60; 1 drivers +v0x11a6a40_0 .net *"_s28", 0 0, L_0x1351f20; 1 drivers +v0x11a6b20_0 .net/2s *"_s30", 0 0, L_0x2ac432887f68; 1 drivers +v0x11a6c00_0 .net/2s *"_s32", 0 0, L_0x2ac432887fb0; 1 drivers +v0x11a6ce0_0 .net *"_s34", 0 0, L_0x1352120; 1 drivers +v0x11a6dc0_0 .net *"_s37", 0 0, L_0x1352230; 1 drivers +v0x11a6ea0_0 .net/2s *"_s39", 0 0, L_0x2ac432887ff8; 1 drivers +v0x11a7050_0 .net/2s *"_s41", 0 0, L_0x2ac432888040; 1 drivers +v0x11a70f0_0 .net *"_s43", 0 0, L_0x13523e0; 1 drivers +v0x11a71d0_0 .net *"_s46", 0 0, L_0x13526b0; 1 drivers +v0x11a72b0_0 .net/2s *"_s48", 0 0, L_0x2ac432888088; 1 drivers +v0x11a7390_0 .net/2s *"_s50", 0 0, L_0x2ac4328880d0; 1 drivers +v0x11a7470_0 .net *"_s52", 0 0, L_0x1352ab0; 1 drivers +v0x11a7550_0 .net *"_s56", 0 0, L_0x1352f50; 1 drivers +v0x11a7630_0 .net/2s *"_s59", 0 0, L_0x2ac432888118; 1 drivers +v0x11a7710_0 .net/2s *"_s61", 0 0, L_0x2ac432888160; 1 drivers +v0x11a77f0_0 .net *"_s8", 0 0, L_0x1351400; 1 drivers +v0x11a78d0_0 .net "carryin", 0 0, L_0x13500b0; 1 drivers +v0x11a7970_0 .net "carryout", 0 0, L_0x135a350; 1 drivers +v0x11a7a10_0 .net "carryouts", 7 0, L_0x1352bc0; 1 drivers +v0x11a7b20_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11a7be0_0 .net "result", 0 0, L_0x1356910; 1 drivers +v0x11a7cd0_0 .net "results", 7 0, L_0x1352880; 1 drivers +v0x11a6fb0_0 .net "zero", 0 0, L_0x135a6b0; 1 drivers +LS_0x1352880_0_0 .concat8 [ 1 1 1 1], L_0x1350920, L_0x1350f50, L_0x1351400, L_0x1351c60; +LS_0x1352880_0_4 .concat8 [ 1 1 1 1], L_0x1351e60, L_0x1352120, L_0x13523e0, L_0x1352ab0; +L_0x1352880 .concat8 [ 4 4 0 0], LS_0x1352880_0_0, LS_0x1352880_0_4; +LS_0x1352bc0_0_0 .concat8 [ 1 1 1 1], L_0x1350bd0, L_0x13512a0, L_0x13514c0, L_0x1351ab0; +LS_0x1352bc0_0_4 .concat8 [ 1 1 1 1], L_0x1351f20, L_0x1352230, L_0x13526b0, L_0x1352f50; +L_0x1352bc0 .concat8 [ 4 4 0 0], LS_0x1352bc0_0_0, LS_0x1352bc0_0_4; +S_0x1197c00 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1197980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1350bd0/d .functor OR 1, L_0x13506b0, L_0x1350a70, C4<0>, C4<0>; +L_0x1350bd0 .delay 1 (30000,30000,30000) L_0x1350bd0/d; +v0x1198a30_0 .net "a", 0 0, L_0x135a7b0; alias, 1 drivers +v0x1198af0_0 .net "b", 0 0, L_0x135a910; alias, 1 drivers +v0x1198bc0_0 .net "c1", 0 0, L_0x13506b0; 1 drivers +v0x1198cc0_0 .net "c2", 0 0, L_0x1350a70; 1 drivers +v0x1198d90_0 .net "carryin", 0 0, L_0x13500b0; alias, 1 drivers +v0x1198e80_0 .net "carryout", 0 0, L_0x1350bd0; 1 drivers +v0x1198f20_0 .net "s1", 0 0, L_0x13505f0; 1 drivers +v0x1199010_0 .net "sum", 0 0, L_0x1350920; 1 drivers +S_0x1197e70 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1197c00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13505f0/d .functor XOR 1, L_0x135a7b0, L_0x135a910, C4<0>, C4<0>; +L_0x13505f0 .delay 1 (30000,30000,30000) L_0x13505f0/d; +L_0x13506b0/d .functor AND 1, L_0x135a7b0, L_0x135a910, C4<1>, C4<1>; +L_0x13506b0 .delay 1 (30000,30000,30000) L_0x13506b0/d; +v0x11980d0_0 .net "a", 0 0, L_0x135a7b0; alias, 1 drivers +v0x11981b0_0 .net "b", 0 0, L_0x135a910; alias, 1 drivers +v0x1198270_0 .net "carryout", 0 0, L_0x13506b0; alias, 1 drivers +v0x1198310_0 .net "sum", 0 0, L_0x13505f0; alias, 1 drivers +S_0x1198450 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1197c00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1350920/d .functor XOR 1, L_0x13505f0, L_0x13500b0, C4<0>, C4<0>; +L_0x1350920 .delay 1 (30000,30000,30000) L_0x1350920/d; +L_0x1350a70/d .functor AND 1, L_0x13505f0, L_0x13500b0, C4<1>, C4<1>; +L_0x1350a70 .delay 1 (30000,30000,30000) L_0x1350a70/d; +v0x11986b0_0 .net "a", 0 0, L_0x13505f0; alias, 1 drivers +v0x1198750_0 .net "b", 0 0, L_0x13500b0; alias, 1 drivers +v0x11987f0_0 .net "carryout", 0 0, L_0x1350a70; alias, 1 drivers +v0x11988c0_0 .net "sum", 0 0, L_0x1350920; alias, 1 drivers +S_0x11990e0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1197980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x119e4d0_0 .net "ands", 7 0, L_0x1358350; 1 drivers +v0x119e5e0_0 .net "in", 7 0, L_0x1352bc0; alias, 1 drivers +v0x119e6a0_0 .net "out", 0 0, L_0x135a350; alias, 1 drivers +v0x119e770_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1199300 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11990e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x119ba30_0 .net "A", 7 0, L_0x1352bc0; alias, 1 drivers +v0x119bb30_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x119bbf0_0 .net *"_s0", 0 0, L_0x1356c70; 1 drivers +v0x119bcb0_0 .net *"_s12", 0 0, L_0x13575e0; 1 drivers +v0x119bd90_0 .net *"_s16", 0 0, L_0x1357940; 1 drivers +v0x119bec0_0 .net *"_s20", 0 0, L_0x1357d10; 1 drivers +v0x119bfa0_0 .net *"_s24", 0 0, L_0x1358040; 1 drivers +v0x119c080_0 .net *"_s28", 0 0, L_0x1357fd0; 1 drivers +v0x119c160_0 .net *"_s4", 0 0, L_0x1356fc0; 1 drivers +v0x119c2d0_0 .net *"_s8", 0 0, L_0x13572d0; 1 drivers +v0x119c3b0_0 .net "out", 7 0, L_0x1358350; alias, 1 drivers +L_0x1356d30 .part L_0x1352bc0, 0, 1; +L_0x1356f20 .part v0x127a150_0, 0, 1; +L_0x1357080 .part L_0x1352bc0, 1, 1; +L_0x13571e0 .part v0x127a150_0, 1, 1; +L_0x1357390 .part L_0x1352bc0, 2, 1; +L_0x13574f0 .part v0x127a150_0, 2, 1; +L_0x13576a0 .part L_0x1352bc0, 3, 1; +L_0x1357800 .part v0x127a150_0, 3, 1; +L_0x1357a00 .part L_0x1352bc0, 4, 1; +L_0x1357c70 .part v0x127a150_0, 4, 1; +L_0x1357d80 .part L_0x1352bc0, 5, 1; +L_0x1357ee0 .part v0x127a150_0, 5, 1; +L_0x1358100 .part L_0x1352bc0, 6, 1; +L_0x1358260 .part v0x127a150_0, 6, 1; +LS_0x1358350_0_0 .concat8 [ 1 1 1 1], L_0x1356c70, L_0x1356fc0, L_0x13572d0, L_0x13575e0; +LS_0x1358350_0_4 .concat8 [ 1 1 1 1], L_0x1357940, L_0x1357d10, L_0x1358040, L_0x1357fd0; +L_0x1358350 .concat8 [ 4 4 0 0], LS_0x1358350_0_0, LS_0x1358350_0_4; +L_0x1358710 .part L_0x1352bc0, 7, 1; +L_0x1358900 .part v0x127a150_0, 7, 1; +S_0x1199560 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x1199770 .param/l "i" 0 4 54, +C4<00>; +L_0x1356c70/d .functor AND 1, L_0x1356d30, L_0x1356f20, C4<1>, C4<1>; +L_0x1356c70 .delay 1 (30000,30000,30000) L_0x1356c70/d; +v0x1199850_0 .net *"_s0", 0 0, L_0x1356d30; 1 drivers +v0x1199930_0 .net *"_s1", 0 0, L_0x1356f20; 1 drivers +S_0x1199a10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x1199c20 .param/l "i" 0 4 54, +C4<01>; +L_0x1356fc0/d .functor AND 1, L_0x1357080, L_0x13571e0, C4<1>, C4<1>; +L_0x1356fc0 .delay 1 (30000,30000,30000) L_0x1356fc0/d; +v0x1199ce0_0 .net *"_s0", 0 0, L_0x1357080; 1 drivers +v0x1199dc0_0 .net *"_s1", 0 0, L_0x13571e0; 1 drivers +S_0x1199ea0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x119a0b0 .param/l "i" 0 4 54, +C4<010>; +L_0x13572d0/d .functor AND 1, L_0x1357390, L_0x13574f0, C4<1>, C4<1>; +L_0x13572d0 .delay 1 (30000,30000,30000) L_0x13572d0/d; +v0x119a150_0 .net *"_s0", 0 0, L_0x1357390; 1 drivers +v0x119a230_0 .net *"_s1", 0 0, L_0x13574f0; 1 drivers +S_0x119a310 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x119a520 .param/l "i" 0 4 54, +C4<011>; +L_0x13575e0/d .functor AND 1, L_0x13576a0, L_0x1357800, C4<1>, C4<1>; +L_0x13575e0 .delay 1 (30000,30000,30000) L_0x13575e0/d; +v0x119a5e0_0 .net *"_s0", 0 0, L_0x13576a0; 1 drivers +v0x119a6c0_0 .net *"_s1", 0 0, L_0x1357800; 1 drivers +S_0x119a7a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x119aa00 .param/l "i" 0 4 54, +C4<0100>; +L_0x1357940/d .functor AND 1, L_0x1357a00, L_0x1357c70, C4<1>, C4<1>; +L_0x1357940 .delay 1 (30000,30000,30000) L_0x1357940/d; +v0x119aac0_0 .net *"_s0", 0 0, L_0x1357a00; 1 drivers +v0x119aba0_0 .net *"_s1", 0 0, L_0x1357c70; 1 drivers +S_0x119ac80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x119ae90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1357d10/d .functor AND 1, L_0x1357d80, L_0x1357ee0, C4<1>, C4<1>; +L_0x1357d10 .delay 1 (30000,30000,30000) L_0x1357d10/d; +v0x119af50_0 .net *"_s0", 0 0, L_0x1357d80; 1 drivers +v0x119b030_0 .net *"_s1", 0 0, L_0x1357ee0; 1 drivers +S_0x119b110 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x119b320 .param/l "i" 0 4 54, +C4<0110>; +L_0x1358040/d .functor AND 1, L_0x1358100, L_0x1358260, C4<1>, C4<1>; +L_0x1358040 .delay 1 (30000,30000,30000) L_0x1358040/d; +v0x119b3e0_0 .net *"_s0", 0 0, L_0x1358100; 1 drivers +v0x119b4c0_0 .net *"_s1", 0 0, L_0x1358260; 1 drivers +S_0x119b5a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1199300; + .timescale -9 -12; +P_0x119b7b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1357fd0/d .functor AND 1, L_0x1358710, L_0x1358900, C4<1>, C4<1>; +L_0x1357fd0 .delay 1 (30000,30000,30000) L_0x1357fd0/d; +v0x119b870_0 .net *"_s0", 0 0, L_0x1358710; 1 drivers +v0x119b950_0 .net *"_s1", 0 0, L_0x1358900; 1 drivers +S_0x119c510 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11990e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x135a350/d .functor OR 1, L_0x135a410, L_0x135a5c0, C4<0>, C4<0>; +L_0x135a350 .delay 1 (30000,30000,30000) L_0x135a350/d; +v0x119e060_0 .net *"_s10", 0 0, L_0x135a410; 1 drivers +v0x119e140_0 .net *"_s12", 0 0, L_0x135a5c0; 1 drivers +v0x119e220_0 .net "in", 7 0, L_0x1358350; alias, 1 drivers +v0x119e2f0_0 .net "ors", 1 0, L_0x135a170; 1 drivers +v0x119e3b0_0 .net "out", 0 0, L_0x135a350; alias, 1 drivers +L_0x1359540 .part L_0x1358350, 0, 4; +L_0x135a170 .concat8 [ 1 1 0 0], L_0x1359230, L_0x1359e60; +L_0x135a2b0 .part L_0x1358350, 4, 4; +L_0x135a410 .part L_0x135a170, 0, 1; +L_0x135a5c0 .part L_0x135a170, 1, 1; +S_0x119c6d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x119c510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13589f0/d .functor OR 1, L_0x1358ab0, L_0x1358c10, C4<0>, C4<0>; +L_0x13589f0 .delay 1 (30000,30000,30000) L_0x13589f0/d; +L_0x1358e40/d .functor OR 1, L_0x1358f50, L_0x13590b0, C4<0>, C4<0>; +L_0x1358e40 .delay 1 (30000,30000,30000) L_0x1358e40/d; +L_0x1359230/d .functor OR 1, L_0x13592a0, L_0x1359450, C4<0>, C4<0>; +L_0x1359230 .delay 1 (30000,30000,30000) L_0x1359230/d; +v0x119c920_0 .net *"_s0", 0 0, L_0x13589f0; 1 drivers +v0x119ca20_0 .net *"_s10", 0 0, L_0x1358f50; 1 drivers +v0x119cb00_0 .net *"_s12", 0 0, L_0x13590b0; 1 drivers +v0x119cbc0_0 .net *"_s14", 0 0, L_0x13592a0; 1 drivers +v0x119cca0_0 .net *"_s16", 0 0, L_0x1359450; 1 drivers +v0x119cdd0_0 .net *"_s3", 0 0, L_0x1358ab0; 1 drivers +v0x119ceb0_0 .net *"_s5", 0 0, L_0x1358c10; 1 drivers +v0x119cf90_0 .net *"_s6", 0 0, L_0x1358e40; 1 drivers +v0x119d070_0 .net "in", 3 0, L_0x1359540; 1 drivers +v0x119d1e0_0 .net "ors", 1 0, L_0x1358d50; 1 drivers +v0x119d2c0_0 .net "out", 0 0, L_0x1359230; 1 drivers +L_0x1358ab0 .part L_0x1359540, 0, 1; +L_0x1358c10 .part L_0x1359540, 1, 1; +L_0x1358d50 .concat8 [ 1 1 0 0], L_0x13589f0, L_0x1358e40; +L_0x1358f50 .part L_0x1359540, 2, 1; +L_0x13590b0 .part L_0x1359540, 3, 1; +L_0x13592a0 .part L_0x1358d50, 0, 1; +L_0x1359450 .part L_0x1358d50, 1, 1; +S_0x119d3e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x119c510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1359670/d .functor OR 1, L_0x13596e0, L_0x1359840, C4<0>, C4<0>; +L_0x1359670 .delay 1 (30000,30000,30000) L_0x1359670/d; +L_0x1359a70/d .functor OR 1, L_0x1359b80, L_0x1359ce0, C4<0>, C4<0>; +L_0x1359a70 .delay 1 (30000,30000,30000) L_0x1359a70/d; +L_0x1359e60/d .functor OR 1, L_0x1359ed0, L_0x135a080, C4<0>, C4<0>; +L_0x1359e60 .delay 1 (30000,30000,30000) L_0x1359e60/d; +v0x119d5a0_0 .net *"_s0", 0 0, L_0x1359670; 1 drivers +v0x119d6a0_0 .net *"_s10", 0 0, L_0x1359b80; 1 drivers +v0x119d780_0 .net *"_s12", 0 0, L_0x1359ce0; 1 drivers +v0x119d840_0 .net *"_s14", 0 0, L_0x1359ed0; 1 drivers +v0x119d920_0 .net *"_s16", 0 0, L_0x135a080; 1 drivers +v0x119da50_0 .net *"_s3", 0 0, L_0x13596e0; 1 drivers +v0x119db30_0 .net *"_s5", 0 0, L_0x1359840; 1 drivers +v0x119dc10_0 .net *"_s6", 0 0, L_0x1359a70; 1 drivers +v0x119dcf0_0 .net "in", 3 0, L_0x135a2b0; 1 drivers +v0x119de60_0 .net "ors", 1 0, L_0x1359980; 1 drivers +v0x119df40_0 .net "out", 0 0, L_0x1359e60; 1 drivers +L_0x13596e0 .part L_0x135a2b0, 0, 1; +L_0x1359840 .part L_0x135a2b0, 1, 1; +L_0x1359980 .concat8 [ 1 1 0 0], L_0x1359670, L_0x1359a70; +L_0x1359b80 .part L_0x135a2b0, 2, 1; +L_0x1359ce0 .part L_0x135a2b0, 3, 1; +L_0x1359ed0 .part L_0x1359980, 0, 1; +L_0x135a080 .part L_0x1359980, 1, 1; +S_0x119e850 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1197980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11a3c80_0 .net "ands", 7 0, L_0x1354910; 1 drivers +v0x11a3d90_0 .net "in", 7 0, L_0x1352880; alias, 1 drivers +v0x11a3e50_0 .net "out", 0 0, L_0x1356910; alias, 1 drivers +v0x11a3f20_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x119eaa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x119e850; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11a11e0_0 .net "A", 7 0, L_0x1352880; alias, 1 drivers +v0x11a12e0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11a13a0_0 .net *"_s0", 0 0, L_0x1353100; 1 drivers +v0x11a1460_0 .net *"_s12", 0 0, L_0x1353ac0; 1 drivers +v0x11a1540_0 .net *"_s16", 0 0, L_0x1353e20; 1 drivers +v0x11a1670_0 .net *"_s20", 0 0, L_0x1354250; 1 drivers +v0x11a1750_0 .net *"_s24", 0 0, L_0x1354580; 1 drivers +v0x11a1830_0 .net *"_s28", 0 0, L_0x1354510; 1 drivers +v0x11a1910_0 .net *"_s4", 0 0, L_0x13534a0; 1 drivers +v0x11a1a80_0 .net *"_s8", 0 0, L_0x13537b0; 1 drivers +v0x11a1b60_0 .net "out", 7 0, L_0x1354910; alias, 1 drivers +L_0x1353210 .part L_0x1352880, 0, 1; +L_0x1353400 .part v0x127a150_0, 0, 1; +L_0x1353560 .part L_0x1352880, 1, 1; +L_0x13536c0 .part v0x127a150_0, 1, 1; +L_0x1353870 .part L_0x1352880, 2, 1; +L_0x13539d0 .part v0x127a150_0, 2, 1; +L_0x1353b80 .part L_0x1352880, 3, 1; +L_0x1353ce0 .part v0x127a150_0, 3, 1; +L_0x1353ee0 .part L_0x1352880, 4, 1; +L_0x1354150 .part v0x127a150_0, 4, 1; +L_0x13542c0 .part L_0x1352880, 5, 1; +L_0x1354420 .part v0x127a150_0, 5, 1; +L_0x1354640 .part L_0x1352880, 6, 1; +L_0x13547a0 .part v0x127a150_0, 6, 1; +LS_0x1354910_0_0 .concat8 [ 1 1 1 1], L_0x1353100, L_0x13534a0, L_0x13537b0, L_0x1353ac0; +LS_0x1354910_0_4 .concat8 [ 1 1 1 1], L_0x1353e20, L_0x1354250, L_0x1354580, L_0x1354510; +L_0x1354910 .concat8 [ 4 4 0 0], LS_0x1354910_0_0, LS_0x1354910_0_4; +L_0x1354cd0 .part L_0x1352880, 7, 1; +L_0x1354ec0 .part v0x127a150_0, 7, 1; +S_0x119ece0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x119eef0 .param/l "i" 0 4 54, +C4<00>; +L_0x1353100/d .functor AND 1, L_0x1353210, L_0x1353400, C4<1>, C4<1>; +L_0x1353100 .delay 1 (30000,30000,30000) L_0x1353100/d; +v0x119efd0_0 .net *"_s0", 0 0, L_0x1353210; 1 drivers +v0x119f0b0_0 .net *"_s1", 0 0, L_0x1353400; 1 drivers +S_0x119f190 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x119f3a0 .param/l "i" 0 4 54, +C4<01>; +L_0x13534a0/d .functor AND 1, L_0x1353560, L_0x13536c0, C4<1>, C4<1>; +L_0x13534a0 .delay 1 (30000,30000,30000) L_0x13534a0/d; +v0x119f460_0 .net *"_s0", 0 0, L_0x1353560; 1 drivers +v0x119f540_0 .net *"_s1", 0 0, L_0x13536c0; 1 drivers +S_0x119f620 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x119f860 .param/l "i" 0 4 54, +C4<010>; +L_0x13537b0/d .functor AND 1, L_0x1353870, L_0x13539d0, C4<1>, C4<1>; +L_0x13537b0 .delay 1 (30000,30000,30000) L_0x13537b0/d; +v0x119f900_0 .net *"_s0", 0 0, L_0x1353870; 1 drivers +v0x119f9e0_0 .net *"_s1", 0 0, L_0x13539d0; 1 drivers +S_0x119fac0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x119fcd0 .param/l "i" 0 4 54, +C4<011>; +L_0x1353ac0/d .functor AND 1, L_0x1353b80, L_0x1353ce0, C4<1>, C4<1>; +L_0x1353ac0 .delay 1 (30000,30000,30000) L_0x1353ac0/d; +v0x119fd90_0 .net *"_s0", 0 0, L_0x1353b80; 1 drivers +v0x119fe70_0 .net *"_s1", 0 0, L_0x1353ce0; 1 drivers +S_0x119ff50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x11a01b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1353e20/d .functor AND 1, L_0x1353ee0, L_0x1354150, C4<1>, C4<1>; +L_0x1353e20 .delay 1 (30000,30000,30000) L_0x1353e20/d; +v0x11a0270_0 .net *"_s0", 0 0, L_0x1353ee0; 1 drivers +v0x11a0350_0 .net *"_s1", 0 0, L_0x1354150; 1 drivers +S_0x11a0430 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x11a0640 .param/l "i" 0 4 54, +C4<0101>; +L_0x1354250/d .functor AND 1, L_0x13542c0, L_0x1354420, C4<1>, C4<1>; +L_0x1354250 .delay 1 (30000,30000,30000) L_0x1354250/d; +v0x11a0700_0 .net *"_s0", 0 0, L_0x13542c0; 1 drivers +v0x11a07e0_0 .net *"_s1", 0 0, L_0x1354420; 1 drivers +S_0x11a08c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x11a0ad0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1354580/d .functor AND 1, L_0x1354640, L_0x13547a0, C4<1>, C4<1>; +L_0x1354580 .delay 1 (30000,30000,30000) L_0x1354580/d; +v0x11a0b90_0 .net *"_s0", 0 0, L_0x1354640; 1 drivers +v0x11a0c70_0 .net *"_s1", 0 0, L_0x13547a0; 1 drivers +S_0x11a0d50 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x119eaa0; + .timescale -9 -12; +P_0x11a0f60 .param/l "i" 0 4 54, +C4<0111>; +L_0x1354510/d .functor AND 1, L_0x1354cd0, L_0x1354ec0, C4<1>, C4<1>; +L_0x1354510 .delay 1 (30000,30000,30000) L_0x1354510/d; +v0x11a1020_0 .net *"_s0", 0 0, L_0x1354cd0; 1 drivers +v0x11a1100_0 .net *"_s1", 0 0, L_0x1354ec0; 1 drivers +S_0x11a1cc0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x119e850; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1356910/d .functor OR 1, L_0x13569d0, L_0x1356b80, C4<0>, C4<0>; +L_0x1356910 .delay 1 (30000,30000,30000) L_0x1356910/d; +v0x11a3810_0 .net *"_s10", 0 0, L_0x13569d0; 1 drivers +v0x11a38f0_0 .net *"_s12", 0 0, L_0x1356b80; 1 drivers +v0x11a39d0_0 .net "in", 7 0, L_0x1354910; alias, 1 drivers +v0x11a3aa0_0 .net "ors", 1 0, L_0x1356730; 1 drivers +v0x11a3b60_0 .net "out", 0 0, L_0x1356910; alias, 1 drivers +L_0x1355b00 .part L_0x1354910, 0, 4; +L_0x1356730 .concat8 [ 1 1 0 0], L_0x13557f0, L_0x1356420; +L_0x1356870 .part L_0x1354910, 4, 4; +L_0x13569d0 .part L_0x1356730, 0, 1; +L_0x1356b80 .part L_0x1356730, 1, 1; +S_0x11a1e80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11a1cc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1354fb0/d .functor OR 1, L_0x1355070, L_0x13551d0, C4<0>, C4<0>; +L_0x1354fb0 .delay 1 (30000,30000,30000) L_0x1354fb0/d; +L_0x1355400/d .functor OR 1, L_0x1355510, L_0x1355670, C4<0>, C4<0>; +L_0x1355400 .delay 1 (30000,30000,30000) L_0x1355400/d; +L_0x13557f0/d .functor OR 1, L_0x1355860, L_0x1355a10, C4<0>, C4<0>; +L_0x13557f0 .delay 1 (30000,30000,30000) L_0x13557f0/d; +v0x11a20d0_0 .net *"_s0", 0 0, L_0x1354fb0; 1 drivers +v0x11a21d0_0 .net *"_s10", 0 0, L_0x1355510; 1 drivers +v0x11a22b0_0 .net *"_s12", 0 0, L_0x1355670; 1 drivers +v0x11a2370_0 .net *"_s14", 0 0, L_0x1355860; 1 drivers +v0x11a2450_0 .net *"_s16", 0 0, L_0x1355a10; 1 drivers +v0x11a2580_0 .net *"_s3", 0 0, L_0x1355070; 1 drivers +v0x11a2660_0 .net *"_s5", 0 0, L_0x13551d0; 1 drivers +v0x11a2740_0 .net *"_s6", 0 0, L_0x1355400; 1 drivers +v0x11a2820_0 .net "in", 3 0, L_0x1355b00; 1 drivers +v0x11a2990_0 .net "ors", 1 0, L_0x1355310; 1 drivers +v0x11a2a70_0 .net "out", 0 0, L_0x13557f0; 1 drivers +L_0x1355070 .part L_0x1355b00, 0, 1; +L_0x13551d0 .part L_0x1355b00, 1, 1; +L_0x1355310 .concat8 [ 1 1 0 0], L_0x1354fb0, L_0x1355400; +L_0x1355510 .part L_0x1355b00, 2, 1; +L_0x1355670 .part L_0x1355b00, 3, 1; +L_0x1355860 .part L_0x1355310, 0, 1; +L_0x1355a10 .part L_0x1355310, 1, 1; +S_0x11a2b90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11a1cc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1355c30/d .functor OR 1, L_0x1355ca0, L_0x1355e00, C4<0>, C4<0>; +L_0x1355c30 .delay 1 (30000,30000,30000) L_0x1355c30/d; +L_0x1356030/d .functor OR 1, L_0x1356140, L_0x13562a0, C4<0>, C4<0>; +L_0x1356030 .delay 1 (30000,30000,30000) L_0x1356030/d; +L_0x1356420/d .functor OR 1, L_0x1356490, L_0x1356640, C4<0>, C4<0>; +L_0x1356420 .delay 1 (30000,30000,30000) L_0x1356420/d; +v0x11a2d50_0 .net *"_s0", 0 0, L_0x1355c30; 1 drivers +v0x11a2e50_0 .net *"_s10", 0 0, L_0x1356140; 1 drivers +v0x11a2f30_0 .net *"_s12", 0 0, L_0x13562a0; 1 drivers +v0x11a2ff0_0 .net *"_s14", 0 0, L_0x1356490; 1 drivers +v0x11a30d0_0 .net *"_s16", 0 0, L_0x1356640; 1 drivers +v0x11a3200_0 .net *"_s3", 0 0, L_0x1355ca0; 1 drivers +v0x11a32e0_0 .net *"_s5", 0 0, L_0x1355e00; 1 drivers +v0x11a33c0_0 .net *"_s6", 0 0, L_0x1356030; 1 drivers +v0x11a34a0_0 .net "in", 3 0, L_0x1356870; 1 drivers +v0x11a3610_0 .net "ors", 1 0, L_0x1355f40; 1 drivers +v0x11a36f0_0 .net "out", 0 0, L_0x1356420; 1 drivers +L_0x1355ca0 .part L_0x1356870, 0, 1; +L_0x1355e00 .part L_0x1356870, 1, 1; +L_0x1355f40 .concat8 [ 1 1 0 0], L_0x1355c30, L_0x1356030; +L_0x1356140 .part L_0x1356870, 2, 1; +L_0x13562a0 .part L_0x1356870, 3, 1; +L_0x1356490 .part L_0x1355f40, 0, 1; +L_0x1356640 .part L_0x1355f40, 1, 1; +S_0x11a4000 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1197980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x13516c0/d .functor XNOR 1, L_0x135a7b0, L_0x135a910, C4<0>, C4<0>; +L_0x13516c0 .delay 1 (20000,20000,20000) L_0x13516c0/d; +L_0x1351840/d .functor AND 1, L_0x135a7b0, L_0x1350400, C4<1>, C4<1>; +L_0x1351840 .delay 1 (30000,30000,30000) L_0x1351840/d; +L_0x13519a0/d .functor AND 1, L_0x13516c0, L_0x13500b0, C4<1>, C4<1>; +L_0x13519a0 .delay 1 (30000,30000,30000) L_0x13519a0/d; +L_0x1351ab0/d .functor OR 1, L_0x13519a0, L_0x1351840, C4<0>, C4<0>; +L_0x1351ab0 .delay 1 (30000,30000,30000) L_0x1351ab0/d; +v0x11a42b0_0 .net "a", 0 0, L_0x135a7b0; alias, 1 drivers +v0x11a43a0_0 .net "a_", 0 0, L_0x13502f0; alias, 1 drivers +v0x11a4460_0 .net "b", 0 0, L_0x135a910; alias, 1 drivers +v0x11a4550_0 .net "b_", 0 0, L_0x1350400; alias, 1 drivers +v0x11a45f0_0 .net "carryin", 0 0, L_0x13500b0; alias, 1 drivers +v0x11a4730_0 .net "eq", 0 0, L_0x13516c0; 1 drivers +v0x11a47f0_0 .net "lt", 0 0, L_0x1351840; 1 drivers +v0x11a48b0_0 .net "out", 0 0, L_0x1351ab0; 1 drivers +v0x11a4970_0 .net "w0", 0 0, L_0x13519a0; 1 drivers +S_0x11a4bc0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1197980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13512a0/d .functor OR 1, L_0x1350df0, L_0x11a5e20, C4<0>, C4<0>; +L_0x13512a0 .delay 1 (30000,30000,30000) L_0x13512a0/d; +v0x11a59b0_0 .net "a", 0 0, L_0x135a7b0; alias, 1 drivers +v0x11a5b00_0 .net "b", 0 0, L_0x1350400; alias, 1 drivers +v0x11a5bc0_0 .net "c1", 0 0, L_0x1350df0; 1 drivers +v0x11a5c60_0 .net "c2", 0 0, L_0x11a5e20; 1 drivers +v0x11a5d30_0 .net "carryin", 0 0, L_0x13500b0; alias, 1 drivers +v0x11a5eb0_0 .net "carryout", 0 0, L_0x13512a0; 1 drivers +v0x11a5f50_0 .net "s1", 0 0, L_0x1350d30; 1 drivers +v0x11a5ff0_0 .net "sum", 0 0, L_0x1350f50; 1 drivers +S_0x11a4e10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11a4bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1350d30/d .functor XOR 1, L_0x135a7b0, L_0x1350400, C4<0>, C4<0>; +L_0x1350d30 .delay 1 (30000,30000,30000) L_0x1350d30/d; +L_0x1350df0/d .functor AND 1, L_0x135a7b0, L_0x1350400, C4<1>, C4<1>; +L_0x1350df0 .delay 1 (30000,30000,30000) L_0x1350df0/d; +v0x11a5070_0 .net "a", 0 0, L_0x135a7b0; alias, 1 drivers +v0x11a5130_0 .net "b", 0 0, L_0x1350400; alias, 1 drivers +v0x11a51f0_0 .net "carryout", 0 0, L_0x1350df0; alias, 1 drivers +v0x11a5290_0 .net "sum", 0 0, L_0x1350d30; alias, 1 drivers +S_0x11a53c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11a4bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1350f50/d .functor XOR 1, L_0x1350d30, L_0x13500b0, C4<0>, C4<0>; +L_0x1350f50 .delay 1 (30000,30000,30000) L_0x1350f50/d; +L_0x11a5e20/d .functor AND 1, L_0x1350d30, L_0x13500b0, C4<1>, C4<1>; +L_0x11a5e20 .delay 1 (30000,30000,30000) L_0x11a5e20/d; +v0x11a5620_0 .net "a", 0 0, L_0x1350d30; alias, 1 drivers +v0x11a56f0_0 .net "b", 0 0, L_0x13500b0; alias, 1 drivers +v0x11a5790_0 .net "carryout", 0 0, L_0x11a5e20; alias, 1 drivers +v0x11a5860_0 .net "sum", 0 0, L_0x1350f50; alias, 1 drivers +S_0x11a8080 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11976b0; + .timescale -9 -12; +L_0x2ac4328881a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328881f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13508b0/d .functor OR 1, L_0x2ac4328881a8, L_0x2ac4328881f0, C4<0>, C4<0>; +L_0x13508b0 .delay 1 (30000,30000,30000) L_0x13508b0/d; +v0x11a8270_0 .net/2u *"_s0", 0 0, L_0x2ac4328881a8; 1 drivers +v0x11a8350_0 .net/2u *"_s2", 0 0, L_0x2ac4328881f0; 1 drivers +S_0x11a8430 .scope generate, "alu_slices[21]" "alu_slices[21]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11a8640 .param/l "i" 0 3 39, +C4<010101>; +S_0x11a8700 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11a8430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x135abb0/d .functor NOT 1, L_0x12ba890, C4<0>, C4<0>, C4<0>; +L_0x135abb0 .delay 1 (10000,10000,10000) L_0x135abb0/d; +L_0x135ac70/d .functor NOT 1, L_0x12ba930, C4<0>, C4<0>, C4<0>; +L_0x135ac70 .delay 1 (10000,10000,10000) L_0x135ac70/d; +L_0x135bcc0/d .functor XOR 1, L_0x12ba890, L_0x12ba930, C4<0>, C4<0>; +L_0x135bcc0 .delay 1 (30000,30000,30000) L_0x135bcc0/d; +L_0x2ac432888238 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888280 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135bd80/d .functor OR 1, L_0x2ac432888238, L_0x2ac432888280, C4<0>, C4<0>; +L_0x135bd80 .delay 1 (30000,30000,30000) L_0x135bd80/d; +L_0x2ac4328882c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888310 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135c520/d .functor OR 1, L_0x2ac4328882c8, L_0x2ac432888310, C4<0>, C4<0>; +L_0x135c520 .delay 1 (30000,30000,30000) L_0x135c520/d; +L_0x135c720/d .functor AND 1, L_0x12ba890, L_0x12ba930, C4<1>, C4<1>; +L_0x135c720 .delay 1 (30000,30000,30000) L_0x135c720/d; +L_0x2ac432888358 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328883a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135c7e0/d .functor OR 1, L_0x2ac432888358, L_0x2ac4328883a0, C4<0>, C4<0>; +L_0x135c7e0 .delay 1 (30000,30000,30000) L_0x135c7e0/d; +L_0x135c9e0/d .functor NAND 1, L_0x12ba890, L_0x12ba930, C4<1>, C4<1>; +L_0x135c9e0 .delay 1 (20000,20000,20000) L_0x135c9e0/d; +L_0x2ac4328883e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888430 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135caf0/d .functor OR 1, L_0x2ac4328883e8, L_0x2ac432888430, C4<0>, C4<0>; +L_0x135caf0 .delay 1 (30000,30000,30000) L_0x135caf0/d; +L_0x135cca0/d .functor NOR 1, L_0x12ba890, L_0x12ba930, C4<0>, C4<0>; +L_0x135cca0 .delay 1 (20000,20000,20000) L_0x135cca0/d; +L_0x2ac432888478 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328884c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135b120/d .functor OR 1, L_0x2ac432888478, L_0x2ac4328884c0, C4<0>, C4<0>; +L_0x135b120 .delay 1 (30000,30000,30000) L_0x135b120/d; +L_0x135d300/d .functor OR 1, L_0x12ba890, L_0x12ba930, C4<0>, C4<0>; +L_0x135d300 .delay 1 (30000,30000,30000) L_0x135d300/d; +L_0x2ac432888508 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888550 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135d7f0/d .functor OR 1, L_0x2ac432888508, L_0x2ac432888550, C4<0>, C4<0>; +L_0x135d7f0 .delay 1 (30000,30000,30000) L_0x135d7f0/d; +L_0x12ba630/d .functor NOT 1, L_0x1361150, C4<0>, C4<0>, C4<0>; +L_0x12ba630 .delay 1 (10000,10000,10000) L_0x12ba630/d; +v0x11b6e30_0 .net "A", 0 0, L_0x12ba890; 1 drivers +v0x11b6ef0_0 .net "A_", 0 0, L_0x135abb0; 1 drivers +v0x11b6fb0_0 .net "B", 0 0, L_0x12ba930; 1 drivers +v0x11b7080_0 .net "B_", 0 0, L_0x135ac70; 1 drivers +v0x11b7120_0 .net *"_s11", 0 0, L_0x135bd80; 1 drivers +v0x11b7210_0 .net/2s *"_s13", 0 0, L_0x2ac432888238; 1 drivers +v0x11b72d0_0 .net/2s *"_s15", 0 0, L_0x2ac432888280; 1 drivers +v0x11b73b0_0 .net *"_s19", 0 0, L_0x135c520; 1 drivers +v0x11b7490_0 .net/2s *"_s21", 0 0, L_0x2ac4328882c8; 1 drivers +v0x11b7600_0 .net/2s *"_s23", 0 0, L_0x2ac432888310; 1 drivers +v0x11b76e0_0 .net *"_s25", 0 0, L_0x135c720; 1 drivers +v0x11b77c0_0 .net *"_s28", 0 0, L_0x135c7e0; 1 drivers +v0x11b78a0_0 .net/2s *"_s30", 0 0, L_0x2ac432888358; 1 drivers +v0x11b7980_0 .net/2s *"_s32", 0 0, L_0x2ac4328883a0; 1 drivers +v0x11b7a60_0 .net *"_s34", 0 0, L_0x135c9e0; 1 drivers +v0x11b7b40_0 .net *"_s37", 0 0, L_0x135caf0; 1 drivers +v0x11b7c20_0 .net/2s *"_s39", 0 0, L_0x2ac4328883e8; 1 drivers +v0x11b7dd0_0 .net/2s *"_s41", 0 0, L_0x2ac432888430; 1 drivers +v0x11b7e70_0 .net *"_s43", 0 0, L_0x135cca0; 1 drivers +v0x11b7f50_0 .net *"_s46", 0 0, L_0x135b120; 1 drivers +v0x11b8030_0 .net/2s *"_s48", 0 0, L_0x2ac432888478; 1 drivers +v0x11b8110_0 .net/2s *"_s50", 0 0, L_0x2ac4328884c0; 1 drivers +v0x11b81f0_0 .net *"_s52", 0 0, L_0x135d300; 1 drivers +v0x11b82d0_0 .net *"_s56", 0 0, L_0x135d7f0; 1 drivers +v0x11b83b0_0 .net/2s *"_s59", 0 0, L_0x2ac432888508; 1 drivers +v0x11b8490_0 .net/2s *"_s61", 0 0, L_0x2ac432888550; 1 drivers +v0x11b8570_0 .net *"_s8", 0 0, L_0x135bcc0; 1 drivers +v0x11b8650_0 .net "carryin", 0 0, L_0x12ba9d0; 1 drivers +v0x11b86f0_0 .net "carryout", 0 0, L_0x12ba2d0; 1 drivers +v0x11b8790_0 .net "carryouts", 7 0, L_0x135d480; 1 drivers +v0x11b88a0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11b8960_0 .net "result", 0 0, L_0x1361150; 1 drivers +v0x11b8a50_0 .net "results", 7 0, L_0x135d0d0; 1 drivers +v0x11b7d30_0 .net "zero", 0 0, L_0x12ba630; 1 drivers +LS_0x135d0d0_0_0 .concat8 [ 1 1 1 1], L_0x135b190, L_0x135b7c0, L_0x135bcc0, L_0x135c520; +LS_0x135d0d0_0_4 .concat8 [ 1 1 1 1], L_0x135c720, L_0x135c9e0, L_0x135cca0, L_0x135d300; +L_0x135d0d0 .concat8 [ 4 4 0 0], LS_0x135d0d0_0_0, LS_0x135d0d0_0_4; +LS_0x135d480_0_0 .concat8 [ 1 1 1 1], L_0x135b440, L_0x135bb60, L_0x135bd80, L_0x135c370; +LS_0x135d480_0_4 .concat8 [ 1 1 1 1], L_0x135c7e0, L_0x135caf0, L_0x135b120, L_0x135d7f0; +L_0x135d480 .concat8 [ 4 4 0 0], LS_0x135d480_0_0, LS_0x135d480_0_4; +S_0x11a8980 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11a8700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x135b440/d .functor OR 1, L_0x135af20, L_0x135b2e0, C4<0>, C4<0>; +L_0x135b440 .delay 1 (30000,30000,30000) L_0x135b440/d; +v0x11a97b0_0 .net "a", 0 0, L_0x12ba890; alias, 1 drivers +v0x11a9870_0 .net "b", 0 0, L_0x12ba930; alias, 1 drivers +v0x11a9940_0 .net "c1", 0 0, L_0x135af20; 1 drivers +v0x11a9a40_0 .net "c2", 0 0, L_0x135b2e0; 1 drivers +v0x11a9b10_0 .net "carryin", 0 0, L_0x12ba9d0; alias, 1 drivers +v0x11a9c00_0 .net "carryout", 0 0, L_0x135b440; 1 drivers +v0x11a9ca0_0 .net "s1", 0 0, L_0x135ae60; 1 drivers +v0x11a9d90_0 .net "sum", 0 0, L_0x135b190; 1 drivers +S_0x11a8bf0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11a8980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x135ae60/d .functor XOR 1, L_0x12ba890, L_0x12ba930, C4<0>, C4<0>; +L_0x135ae60 .delay 1 (30000,30000,30000) L_0x135ae60/d; +L_0x135af20/d .functor AND 1, L_0x12ba890, L_0x12ba930, C4<1>, C4<1>; +L_0x135af20 .delay 1 (30000,30000,30000) L_0x135af20/d; +v0x11a8e50_0 .net "a", 0 0, L_0x12ba890; alias, 1 drivers +v0x11a8f30_0 .net "b", 0 0, L_0x12ba930; alias, 1 drivers +v0x11a8ff0_0 .net "carryout", 0 0, L_0x135af20; alias, 1 drivers +v0x11a9090_0 .net "sum", 0 0, L_0x135ae60; alias, 1 drivers +S_0x11a91d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11a8980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x135b190/d .functor XOR 1, L_0x135ae60, L_0x12ba9d0, C4<0>, C4<0>; +L_0x135b190 .delay 1 (30000,30000,30000) L_0x135b190/d; +L_0x135b2e0/d .functor AND 1, L_0x135ae60, L_0x12ba9d0, C4<1>, C4<1>; +L_0x135b2e0 .delay 1 (30000,30000,30000) L_0x135b2e0/d; +v0x11a9430_0 .net "a", 0 0, L_0x135ae60; alias, 1 drivers +v0x11a94d0_0 .net "b", 0 0, L_0x12ba9d0; alias, 1 drivers +v0x11a9570_0 .net "carryout", 0 0, L_0x135b2e0; alias, 1 drivers +v0x11a9640_0 .net "sum", 0 0, L_0x135b190; alias, 1 drivers +S_0x11a9e60 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11a8700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11af250_0 .net "ands", 7 0, L_0x1362b90; 1 drivers +v0x11af360_0 .net "in", 7 0, L_0x135d480; alias, 1 drivers +v0x11af420_0 .net "out", 0 0, L_0x12ba2d0; alias, 1 drivers +v0x11af4f0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11aa080 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11a9e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11ac7b0_0 .net "A", 7 0, L_0x135d480; alias, 1 drivers +v0x11ac8b0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11ac970_0 .net *"_s0", 0 0, L_0x13614b0; 1 drivers +v0x11aca30_0 .net *"_s12", 0 0, L_0x1361e20; 1 drivers +v0x11acb10_0 .net *"_s16", 0 0, L_0x1362180; 1 drivers +v0x11acc40_0 .net *"_s20", 0 0, L_0x1362550; 1 drivers +v0x11acd20_0 .net *"_s24", 0 0, L_0x1362880; 1 drivers +v0x11ace00_0 .net *"_s28", 0 0, L_0x1362810; 1 drivers +v0x11acee0_0 .net *"_s4", 0 0, L_0x1361800; 1 drivers +v0x11ad050_0 .net *"_s8", 0 0, L_0x1361b10; 1 drivers +v0x11ad130_0 .net "out", 7 0, L_0x1362b90; alias, 1 drivers +L_0x1361570 .part L_0x135d480, 0, 1; +L_0x1361760 .part v0x127a150_0, 0, 1; +L_0x13618c0 .part L_0x135d480, 1, 1; +L_0x1361a20 .part v0x127a150_0, 1, 1; +L_0x1361bd0 .part L_0x135d480, 2, 1; +L_0x1361d30 .part v0x127a150_0, 2, 1; +L_0x1361ee0 .part L_0x135d480, 3, 1; +L_0x1362040 .part v0x127a150_0, 3, 1; +L_0x1362240 .part L_0x135d480, 4, 1; +L_0x13624b0 .part v0x127a150_0, 4, 1; +L_0x13625c0 .part L_0x135d480, 5, 1; +L_0x1362720 .part v0x127a150_0, 5, 1; +L_0x1362940 .part L_0x135d480, 6, 1; +L_0x1362aa0 .part v0x127a150_0, 6, 1; +LS_0x1362b90_0_0 .concat8 [ 1 1 1 1], L_0x13614b0, L_0x1361800, L_0x1361b10, L_0x1361e20; +LS_0x1362b90_0_4 .concat8 [ 1 1 1 1], L_0x1362180, L_0x1362550, L_0x1362880, L_0x1362810; +L_0x1362b90 .concat8 [ 4 4 0 0], LS_0x1362b90_0_0, LS_0x1362b90_0_4; +L_0x1362f50 .part L_0x135d480, 7, 1; +L_0x1363140 .part v0x127a150_0, 7, 1; +S_0x11aa2e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11aa4f0 .param/l "i" 0 4 54, +C4<00>; +L_0x13614b0/d .functor AND 1, L_0x1361570, L_0x1361760, C4<1>, C4<1>; +L_0x13614b0 .delay 1 (30000,30000,30000) L_0x13614b0/d; +v0x11aa5d0_0 .net *"_s0", 0 0, L_0x1361570; 1 drivers +v0x11aa6b0_0 .net *"_s1", 0 0, L_0x1361760; 1 drivers +S_0x11aa790 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11aa9a0 .param/l "i" 0 4 54, +C4<01>; +L_0x1361800/d .functor AND 1, L_0x13618c0, L_0x1361a20, C4<1>, C4<1>; +L_0x1361800 .delay 1 (30000,30000,30000) L_0x1361800/d; +v0x11aaa60_0 .net *"_s0", 0 0, L_0x13618c0; 1 drivers +v0x11aab40_0 .net *"_s1", 0 0, L_0x1361a20; 1 drivers +S_0x11aac20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11aae30 .param/l "i" 0 4 54, +C4<010>; +L_0x1361b10/d .functor AND 1, L_0x1361bd0, L_0x1361d30, C4<1>, C4<1>; +L_0x1361b10 .delay 1 (30000,30000,30000) L_0x1361b10/d; +v0x11aaed0_0 .net *"_s0", 0 0, L_0x1361bd0; 1 drivers +v0x11aafb0_0 .net *"_s1", 0 0, L_0x1361d30; 1 drivers +S_0x11ab090 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11ab2a0 .param/l "i" 0 4 54, +C4<011>; +L_0x1361e20/d .functor AND 1, L_0x1361ee0, L_0x1362040, C4<1>, C4<1>; +L_0x1361e20 .delay 1 (30000,30000,30000) L_0x1361e20/d; +v0x11ab360_0 .net *"_s0", 0 0, L_0x1361ee0; 1 drivers +v0x11ab440_0 .net *"_s1", 0 0, L_0x1362040; 1 drivers +S_0x11ab520 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11ab780 .param/l "i" 0 4 54, +C4<0100>; +L_0x1362180/d .functor AND 1, L_0x1362240, L_0x13624b0, C4<1>, C4<1>; +L_0x1362180 .delay 1 (30000,30000,30000) L_0x1362180/d; +v0x11ab840_0 .net *"_s0", 0 0, L_0x1362240; 1 drivers +v0x11ab920_0 .net *"_s1", 0 0, L_0x13624b0; 1 drivers +S_0x11aba00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11abc10 .param/l "i" 0 4 54, +C4<0101>; +L_0x1362550/d .functor AND 1, L_0x13625c0, L_0x1362720, C4<1>, C4<1>; +L_0x1362550 .delay 1 (30000,30000,30000) L_0x1362550/d; +v0x11abcd0_0 .net *"_s0", 0 0, L_0x13625c0; 1 drivers +v0x11abdb0_0 .net *"_s1", 0 0, L_0x1362720; 1 drivers +S_0x11abe90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11ac0a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1362880/d .functor AND 1, L_0x1362940, L_0x1362aa0, C4<1>, C4<1>; +L_0x1362880 .delay 1 (30000,30000,30000) L_0x1362880/d; +v0x11ac160_0 .net *"_s0", 0 0, L_0x1362940; 1 drivers +v0x11ac240_0 .net *"_s1", 0 0, L_0x1362aa0; 1 drivers +S_0x11ac320 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11aa080; + .timescale -9 -12; +P_0x11ac530 .param/l "i" 0 4 54, +C4<0111>; +L_0x1362810/d .functor AND 1, L_0x1362f50, L_0x1363140, C4<1>, C4<1>; +L_0x1362810 .delay 1 (30000,30000,30000) L_0x1362810/d; +v0x11ac5f0_0 .net *"_s0", 0 0, L_0x1362f50; 1 drivers +v0x11ac6d0_0 .net *"_s1", 0 0, L_0x1363140; 1 drivers +S_0x11ad290 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11a9e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x12ba2d0/d .functor OR 1, L_0x12ba390, L_0x12ba540, C4<0>, C4<0>; +L_0x12ba2d0 .delay 1 (30000,30000,30000) L_0x12ba2d0/d; +v0x11aede0_0 .net *"_s10", 0 0, L_0x12ba390; 1 drivers +v0x11aeec0_0 .net *"_s12", 0 0, L_0x12ba540; 1 drivers +v0x11aefa0_0 .net "in", 7 0, L_0x1362b90; alias, 1 drivers +v0x11af070_0 .net "ors", 1 0, L_0x12ba0f0; 1 drivers +v0x11af130_0 .net "out", 0 0, L_0x12ba2d0; alias, 1 drivers +L_0x12b94c0 .part L_0x1362b90, 0, 4; +L_0x12ba0f0 .concat8 [ 1 1 0 0], L_0x12b91b0, L_0x12b9de0; +L_0x12ba230 .part L_0x1362b90, 4, 4; +L_0x12ba390 .part L_0x12ba0f0, 0, 1; +L_0x12ba540 .part L_0x12ba0f0, 1, 1; +S_0x11ad450 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11ad290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x135f0d0/d .functor OR 1, L_0x12b8aa0, L_0x12b8c00, C4<0>, C4<0>; +L_0x135f0d0 .delay 1 (30000,30000,30000) L_0x135f0d0/d; +L_0x12b8b40/d .functor OR 1, L_0x12b8ed0, L_0x12b9030, C4<0>, C4<0>; +L_0x12b8b40 .delay 1 (30000,30000,30000) L_0x12b8b40/d; +L_0x12b91b0/d .functor OR 1, L_0x12b9220, L_0x12b93d0, C4<0>, C4<0>; +L_0x12b91b0 .delay 1 (30000,30000,30000) L_0x12b91b0/d; +v0x11ad6a0_0 .net *"_s0", 0 0, L_0x135f0d0; 1 drivers +v0x11ad7a0_0 .net *"_s10", 0 0, L_0x12b8ed0; 1 drivers +v0x11ad880_0 .net *"_s12", 0 0, L_0x12b9030; 1 drivers +v0x11ad940_0 .net *"_s14", 0 0, L_0x12b9220; 1 drivers +v0x11ada20_0 .net *"_s16", 0 0, L_0x12b93d0; 1 drivers +v0x11adb50_0 .net *"_s3", 0 0, L_0x12b8aa0; 1 drivers +v0x11adc30_0 .net *"_s5", 0 0, L_0x12b8c00; 1 drivers +v0x11add10_0 .net *"_s6", 0 0, L_0x12b8b40; 1 drivers +v0x11addf0_0 .net "in", 3 0, L_0x12b94c0; 1 drivers +v0x11adf60_0 .net "ors", 1 0, L_0x12b8d40; 1 drivers +v0x11ae040_0 .net "out", 0 0, L_0x12b91b0; 1 drivers +L_0x12b8aa0 .part L_0x12b94c0, 0, 1; +L_0x12b8c00 .part L_0x12b94c0, 1, 1; +L_0x12b8d40 .concat8 [ 1 1 0 0], L_0x135f0d0, L_0x12b8b40; +L_0x12b8ed0 .part L_0x12b94c0, 2, 1; +L_0x12b9030 .part L_0x12b94c0, 3, 1; +L_0x12b9220 .part L_0x12b8d40, 0, 1; +L_0x12b93d0 .part L_0x12b8d40, 1, 1; +S_0x11ae160 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11ad290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x12b95f0/d .functor OR 1, L_0x12b9660, L_0x12b97c0, C4<0>, C4<0>; +L_0x12b95f0 .delay 1 (30000,30000,30000) L_0x12b95f0/d; +L_0x12b99f0/d .functor OR 1, L_0x12b9b00, L_0x12b9c60, C4<0>, C4<0>; +L_0x12b99f0 .delay 1 (30000,30000,30000) L_0x12b99f0/d; +L_0x12b9de0/d .functor OR 1, L_0x12b9e50, L_0x12ba000, C4<0>, C4<0>; +L_0x12b9de0 .delay 1 (30000,30000,30000) L_0x12b9de0/d; +v0x11ae320_0 .net *"_s0", 0 0, L_0x12b95f0; 1 drivers +v0x11ae420_0 .net *"_s10", 0 0, L_0x12b9b00; 1 drivers +v0x11ae500_0 .net *"_s12", 0 0, L_0x12b9c60; 1 drivers +v0x11ae5c0_0 .net *"_s14", 0 0, L_0x12b9e50; 1 drivers +v0x11ae6a0_0 .net *"_s16", 0 0, L_0x12ba000; 1 drivers +v0x11ae7d0_0 .net *"_s3", 0 0, L_0x12b9660; 1 drivers +v0x11ae8b0_0 .net *"_s5", 0 0, L_0x12b97c0; 1 drivers +v0x11ae990_0 .net *"_s6", 0 0, L_0x12b99f0; 1 drivers +v0x11aea70_0 .net "in", 3 0, L_0x12ba230; 1 drivers +v0x11aebe0_0 .net "ors", 1 0, L_0x12b9900; 1 drivers +v0x11aecc0_0 .net "out", 0 0, L_0x12b9de0; 1 drivers +L_0x12b9660 .part L_0x12ba230, 0, 1; +L_0x12b97c0 .part L_0x12ba230, 1, 1; +L_0x12b9900 .concat8 [ 1 1 0 0], L_0x12b95f0, L_0x12b99f0; +L_0x12b9b00 .part L_0x12ba230, 2, 1; +L_0x12b9c60 .part L_0x12ba230, 3, 1; +L_0x12b9e50 .part L_0x12b9900, 0, 1; +L_0x12ba000 .part L_0x12b9900, 1, 1; +S_0x11af5d0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11a8700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11b4a00_0 .net "ands", 7 0, L_0x135f150; 1 drivers +v0x11b4b10_0 .net "in", 7 0, L_0x135d0d0; alias, 1 drivers +v0x11b4bd0_0 .net "out", 0 0, L_0x1361150; alias, 1 drivers +v0x11b4ca0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11af820 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11af5d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11b1f60_0 .net "A", 7 0, L_0x135d0d0; alias, 1 drivers +v0x11b2060_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11b2120_0 .net *"_s0", 0 0, L_0x135d9a0; 1 drivers +v0x11b21e0_0 .net *"_s12", 0 0, L_0x135e360; 1 drivers +v0x11b22c0_0 .net *"_s16", 0 0, L_0x135e6c0; 1 drivers +v0x11b23f0_0 .net *"_s20", 0 0, L_0x135ea90; 1 drivers +v0x11b24d0_0 .net *"_s24", 0 0, L_0x135edc0; 1 drivers +v0x11b25b0_0 .net *"_s28", 0 0, L_0x135ed50; 1 drivers +v0x11b2690_0 .net *"_s4", 0 0, L_0x135dd40; 1 drivers +v0x11b2800_0 .net *"_s8", 0 0, L_0x135e050; 1 drivers +v0x11b28e0_0 .net "out", 7 0, L_0x135f150; alias, 1 drivers +L_0x135dab0 .part L_0x135d0d0, 0, 1; +L_0x135dca0 .part v0x127a150_0, 0, 1; +L_0x135de00 .part L_0x135d0d0, 1, 1; +L_0x135df60 .part v0x127a150_0, 1, 1; +L_0x135e110 .part L_0x135d0d0, 2, 1; +L_0x135e270 .part v0x127a150_0, 2, 1; +L_0x135e420 .part L_0x135d0d0, 3, 1; +L_0x135e580 .part v0x127a150_0, 3, 1; +L_0x135e780 .part L_0x135d0d0, 4, 1; +L_0x135e9f0 .part v0x127a150_0, 4, 1; +L_0x135eb00 .part L_0x135d0d0, 5, 1; +L_0x135ec60 .part v0x127a150_0, 5, 1; +L_0x135ee80 .part L_0x135d0d0, 6, 1; +L_0x135efe0 .part v0x127a150_0, 6, 1; +LS_0x135f150_0_0 .concat8 [ 1 1 1 1], L_0x135d9a0, L_0x135dd40, L_0x135e050, L_0x135e360; +LS_0x135f150_0_4 .concat8 [ 1 1 1 1], L_0x135e6c0, L_0x135ea90, L_0x135edc0, L_0x135ed50; +L_0x135f150 .concat8 [ 4 4 0 0], LS_0x135f150_0_0, LS_0x135f150_0_4; +L_0x135f510 .part L_0x135d0d0, 7, 1; +L_0x135f700 .part v0x127a150_0, 7, 1; +S_0x11afa60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11afc70 .param/l "i" 0 4 54, +C4<00>; +L_0x135d9a0/d .functor AND 1, L_0x135dab0, L_0x135dca0, C4<1>, C4<1>; +L_0x135d9a0 .delay 1 (30000,30000,30000) L_0x135d9a0/d; +v0x11afd50_0 .net *"_s0", 0 0, L_0x135dab0; 1 drivers +v0x11afe30_0 .net *"_s1", 0 0, L_0x135dca0; 1 drivers +S_0x11aff10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b0120 .param/l "i" 0 4 54, +C4<01>; +L_0x135dd40/d .functor AND 1, L_0x135de00, L_0x135df60, C4<1>, C4<1>; +L_0x135dd40 .delay 1 (30000,30000,30000) L_0x135dd40/d; +v0x11b01e0_0 .net *"_s0", 0 0, L_0x135de00; 1 drivers +v0x11b02c0_0 .net *"_s1", 0 0, L_0x135df60; 1 drivers +S_0x11b03a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b05e0 .param/l "i" 0 4 54, +C4<010>; +L_0x135e050/d .functor AND 1, L_0x135e110, L_0x135e270, C4<1>, C4<1>; +L_0x135e050 .delay 1 (30000,30000,30000) L_0x135e050/d; +v0x11b0680_0 .net *"_s0", 0 0, L_0x135e110; 1 drivers +v0x11b0760_0 .net *"_s1", 0 0, L_0x135e270; 1 drivers +S_0x11b0840 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b0a50 .param/l "i" 0 4 54, +C4<011>; +L_0x135e360/d .functor AND 1, L_0x135e420, L_0x135e580, C4<1>, C4<1>; +L_0x135e360 .delay 1 (30000,30000,30000) L_0x135e360/d; +v0x11b0b10_0 .net *"_s0", 0 0, L_0x135e420; 1 drivers +v0x11b0bf0_0 .net *"_s1", 0 0, L_0x135e580; 1 drivers +S_0x11b0cd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b0f30 .param/l "i" 0 4 54, +C4<0100>; +L_0x135e6c0/d .functor AND 1, L_0x135e780, L_0x135e9f0, C4<1>, C4<1>; +L_0x135e6c0 .delay 1 (30000,30000,30000) L_0x135e6c0/d; +v0x11b0ff0_0 .net *"_s0", 0 0, L_0x135e780; 1 drivers +v0x11b10d0_0 .net *"_s1", 0 0, L_0x135e9f0; 1 drivers +S_0x11b11b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b13c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x135ea90/d .functor AND 1, L_0x135eb00, L_0x135ec60, C4<1>, C4<1>; +L_0x135ea90 .delay 1 (30000,30000,30000) L_0x135ea90/d; +v0x11b1480_0 .net *"_s0", 0 0, L_0x135eb00; 1 drivers +v0x11b1560_0 .net *"_s1", 0 0, L_0x135ec60; 1 drivers +S_0x11b1640 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b1850 .param/l "i" 0 4 54, +C4<0110>; +L_0x135edc0/d .functor AND 1, L_0x135ee80, L_0x135efe0, C4<1>, C4<1>; +L_0x135edc0 .delay 1 (30000,30000,30000) L_0x135edc0/d; +v0x11b1910_0 .net *"_s0", 0 0, L_0x135ee80; 1 drivers +v0x11b19f0_0 .net *"_s1", 0 0, L_0x135efe0; 1 drivers +S_0x11b1ad0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11af820; + .timescale -9 -12; +P_0x11b1ce0 .param/l "i" 0 4 54, +C4<0111>; +L_0x135ed50/d .functor AND 1, L_0x135f510, L_0x135f700, C4<1>, C4<1>; +L_0x135ed50 .delay 1 (30000,30000,30000) L_0x135ed50/d; +v0x11b1da0_0 .net *"_s0", 0 0, L_0x135f510; 1 drivers +v0x11b1e80_0 .net *"_s1", 0 0, L_0x135f700; 1 drivers +S_0x11b2a40 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11af5d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1361150/d .functor OR 1, L_0x1361210, L_0x13613c0, C4<0>, C4<0>; +L_0x1361150 .delay 1 (30000,30000,30000) L_0x1361150/d; +v0x11b4590_0 .net *"_s10", 0 0, L_0x1361210; 1 drivers +v0x11b4670_0 .net *"_s12", 0 0, L_0x13613c0; 1 drivers +v0x11b4750_0 .net "in", 7 0, L_0x135f150; alias, 1 drivers +v0x11b4820_0 .net "ors", 1 0, L_0x1360f70; 1 drivers +v0x11b48e0_0 .net "out", 0 0, L_0x1361150; alias, 1 drivers +L_0x1360340 .part L_0x135f150, 0, 4; +L_0x1360f70 .concat8 [ 1 1 0 0], L_0x1360030, L_0x1360c60; +L_0x13610b0 .part L_0x135f150, 4, 4; +L_0x1361210 .part L_0x1360f70, 0, 1; +L_0x13613c0 .part L_0x1360f70, 1, 1; +S_0x11b2c00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11b2a40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x135f7f0/d .functor OR 1, L_0x135f8b0, L_0x135fa10, C4<0>, C4<0>; +L_0x135f7f0 .delay 1 (30000,30000,30000) L_0x135f7f0/d; +L_0x135fc40/d .functor OR 1, L_0x135fd50, L_0x135feb0, C4<0>, C4<0>; +L_0x135fc40 .delay 1 (30000,30000,30000) L_0x135fc40/d; +L_0x1360030/d .functor OR 1, L_0x13600a0, L_0x1360250, C4<0>, C4<0>; +L_0x1360030 .delay 1 (30000,30000,30000) L_0x1360030/d; +v0x11b2e50_0 .net *"_s0", 0 0, L_0x135f7f0; 1 drivers +v0x11b2f50_0 .net *"_s10", 0 0, L_0x135fd50; 1 drivers +v0x11b3030_0 .net *"_s12", 0 0, L_0x135feb0; 1 drivers +v0x11b30f0_0 .net *"_s14", 0 0, L_0x13600a0; 1 drivers +v0x11b31d0_0 .net *"_s16", 0 0, L_0x1360250; 1 drivers +v0x11b3300_0 .net *"_s3", 0 0, L_0x135f8b0; 1 drivers +v0x11b33e0_0 .net *"_s5", 0 0, L_0x135fa10; 1 drivers +v0x11b34c0_0 .net *"_s6", 0 0, L_0x135fc40; 1 drivers +v0x11b35a0_0 .net "in", 3 0, L_0x1360340; 1 drivers +v0x11b3710_0 .net "ors", 1 0, L_0x135fb50; 1 drivers +v0x11b37f0_0 .net "out", 0 0, L_0x1360030; 1 drivers +L_0x135f8b0 .part L_0x1360340, 0, 1; +L_0x135fa10 .part L_0x1360340, 1, 1; +L_0x135fb50 .concat8 [ 1 1 0 0], L_0x135f7f0, L_0x135fc40; +L_0x135fd50 .part L_0x1360340, 2, 1; +L_0x135feb0 .part L_0x1360340, 3, 1; +L_0x13600a0 .part L_0x135fb50, 0, 1; +L_0x1360250 .part L_0x135fb50, 1, 1; +S_0x11b3910 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11b2a40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1360470/d .functor OR 1, L_0x13604e0, L_0x1360640, C4<0>, C4<0>; +L_0x1360470 .delay 1 (30000,30000,30000) L_0x1360470/d; +L_0x1360870/d .functor OR 1, L_0x1360980, L_0x1360ae0, C4<0>, C4<0>; +L_0x1360870 .delay 1 (30000,30000,30000) L_0x1360870/d; +L_0x1360c60/d .functor OR 1, L_0x1360cd0, L_0x1360e80, C4<0>, C4<0>; +L_0x1360c60 .delay 1 (30000,30000,30000) L_0x1360c60/d; +v0x11b3ad0_0 .net *"_s0", 0 0, L_0x1360470; 1 drivers +v0x11b3bd0_0 .net *"_s10", 0 0, L_0x1360980; 1 drivers +v0x11b3cb0_0 .net *"_s12", 0 0, L_0x1360ae0; 1 drivers +v0x11b3d70_0 .net *"_s14", 0 0, L_0x1360cd0; 1 drivers +v0x11b3e50_0 .net *"_s16", 0 0, L_0x1360e80; 1 drivers +v0x11b3f80_0 .net *"_s3", 0 0, L_0x13604e0; 1 drivers +v0x11b4060_0 .net *"_s5", 0 0, L_0x1360640; 1 drivers +v0x11b4140_0 .net *"_s6", 0 0, L_0x1360870; 1 drivers +v0x11b4220_0 .net "in", 3 0, L_0x13610b0; 1 drivers +v0x11b4390_0 .net "ors", 1 0, L_0x1360780; 1 drivers +v0x11b4470_0 .net "out", 0 0, L_0x1360c60; 1 drivers +L_0x13604e0 .part L_0x13610b0, 0, 1; +L_0x1360640 .part L_0x13610b0, 1, 1; +L_0x1360780 .concat8 [ 1 1 0 0], L_0x1360470, L_0x1360870; +L_0x1360980 .part L_0x13610b0, 2, 1; +L_0x1360ae0 .part L_0x13610b0, 3, 1; +L_0x1360cd0 .part L_0x1360780, 0, 1; +L_0x1360e80 .part L_0x1360780, 1, 1; +S_0x11b4d80 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11a8700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x135bf80/d .functor XNOR 1, L_0x12ba890, L_0x12ba930, C4<0>, C4<0>; +L_0x135bf80 .delay 1 (20000,20000,20000) L_0x135bf80/d; +L_0x135c100/d .functor AND 1, L_0x12ba890, L_0x135ac70, C4<1>, C4<1>; +L_0x135c100 .delay 1 (30000,30000,30000) L_0x135c100/d; +L_0x135c260/d .functor AND 1, L_0x135bf80, L_0x12ba9d0, C4<1>, C4<1>; +L_0x135c260 .delay 1 (30000,30000,30000) L_0x135c260/d; +L_0x135c370/d .functor OR 1, L_0x135c260, L_0x135c100, C4<0>, C4<0>; +L_0x135c370 .delay 1 (30000,30000,30000) L_0x135c370/d; +v0x11b5030_0 .net "a", 0 0, L_0x12ba890; alias, 1 drivers +v0x11b5120_0 .net "a_", 0 0, L_0x135abb0; alias, 1 drivers +v0x11b51e0_0 .net "b", 0 0, L_0x12ba930; alias, 1 drivers +v0x11b52d0_0 .net "b_", 0 0, L_0x135ac70; alias, 1 drivers +v0x11b5370_0 .net "carryin", 0 0, L_0x12ba9d0; alias, 1 drivers +v0x11b54b0_0 .net "eq", 0 0, L_0x135bf80; 1 drivers +v0x11b5570_0 .net "lt", 0 0, L_0x135c100; 1 drivers +v0x11b5630_0 .net "out", 0 0, L_0x135c370; 1 drivers +v0x11b56f0_0 .net "w0", 0 0, L_0x135c260; 1 drivers +S_0x11b5940 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11a8700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x135bb60/d .functor OR 1, L_0x135b660, L_0x11b6ba0, C4<0>, C4<0>; +L_0x135bb60 .delay 1 (30000,30000,30000) L_0x135bb60/d; +v0x11b6730_0 .net "a", 0 0, L_0x12ba890; alias, 1 drivers +v0x11b6880_0 .net "b", 0 0, L_0x135ac70; alias, 1 drivers +v0x11b6940_0 .net "c1", 0 0, L_0x135b660; 1 drivers +v0x11b69e0_0 .net "c2", 0 0, L_0x11b6ba0; 1 drivers +v0x11b6ab0_0 .net "carryin", 0 0, L_0x12ba9d0; alias, 1 drivers +v0x11b6c30_0 .net "carryout", 0 0, L_0x135bb60; 1 drivers +v0x11b6cd0_0 .net "s1", 0 0, L_0x135b5a0; 1 drivers +v0x11b6d70_0 .net "sum", 0 0, L_0x135b7c0; 1 drivers +S_0x11b5b90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11b5940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x135b5a0/d .functor XOR 1, L_0x12ba890, L_0x135ac70, C4<0>, C4<0>; +L_0x135b5a0 .delay 1 (30000,30000,30000) L_0x135b5a0/d; +L_0x135b660/d .functor AND 1, L_0x12ba890, L_0x135ac70, C4<1>, C4<1>; +L_0x135b660 .delay 1 (30000,30000,30000) L_0x135b660/d; +v0x11b5df0_0 .net "a", 0 0, L_0x12ba890; alias, 1 drivers +v0x11b5eb0_0 .net "b", 0 0, L_0x135ac70; alias, 1 drivers +v0x11b5f70_0 .net "carryout", 0 0, L_0x135b660; alias, 1 drivers +v0x11b6010_0 .net "sum", 0 0, L_0x135b5a0; alias, 1 drivers +S_0x11b6140 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11b5940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x135b7c0/d .functor XOR 1, L_0x135b5a0, L_0x12ba9d0, C4<0>, C4<0>; +L_0x135b7c0 .delay 1 (30000,30000,30000) L_0x135b7c0/d; +L_0x11b6ba0/d .functor AND 1, L_0x135b5a0, L_0x12ba9d0, C4<1>, C4<1>; +L_0x11b6ba0 .delay 1 (30000,30000,30000) L_0x11b6ba0/d; +v0x11b63a0_0 .net "a", 0 0, L_0x135b5a0; alias, 1 drivers +v0x11b6470_0 .net "b", 0 0, L_0x12ba9d0; alias, 1 drivers +v0x11b6510_0 .net "carryout", 0 0, L_0x11b6ba0; alias, 1 drivers +v0x11b65e0_0 .net "sum", 0 0, L_0x135b7c0; alias, 1 drivers +S_0x11b8e00 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11a8430; + .timescale -9 -12; +L_0x2ac432888598 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328885e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x135d410/d .functor OR 1, L_0x2ac432888598, L_0x2ac4328885e0, C4<0>, C4<0>; +L_0x135d410 .delay 1 (30000,30000,30000) L_0x135d410/d; +v0x11b8ff0_0 .net/2u *"_s0", 0 0, L_0x2ac432888598; 1 drivers +v0x11b90d0_0 .net/2u *"_s2", 0 0, L_0x2ac4328885e0; 1 drivers +S_0x11b91b0 .scope generate, "alu_slices[22]" "alu_slices[22]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11b93c0 .param/l "i" 0 3 39, +C4<010110>; +S_0x11b9480 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11b91b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x135a9b0/d .functor NOT 1, L_0x1371830, C4<0>, C4<0>, C4<0>; +L_0x135a9b0 .delay 1 (10000,10000,10000) L_0x135a9b0/d; +L_0x1367460/d .functor NOT 1, L_0x1371990, C4<0>, C4<0>, C4<0>; +L_0x1367460 .delay 1 (10000,10000,10000) L_0x1367460/d; +L_0x1368480/d .functor XOR 1, L_0x1371830, L_0x1371990, C4<0>, C4<0>; +L_0x1368480 .delay 1 (30000,30000,30000) L_0x1368480/d; +L_0x2ac432888628 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888670 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1368540/d .functor OR 1, L_0x2ac432888628, L_0x2ac432888670, C4<0>, C4<0>; +L_0x1368540 .delay 1 (30000,30000,30000) L_0x1368540/d; +L_0x2ac4328886b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888700 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1368ce0/d .functor OR 1, L_0x2ac4328886b8, L_0x2ac432888700, C4<0>, C4<0>; +L_0x1368ce0 .delay 1 (30000,30000,30000) L_0x1368ce0/d; +L_0x1368ee0/d .functor AND 1, L_0x1371830, L_0x1371990, C4<1>, C4<1>; +L_0x1368ee0 .delay 1 (30000,30000,30000) L_0x1368ee0/d; +L_0x2ac432888748 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888790 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1368fa0/d .functor OR 1, L_0x2ac432888748, L_0x2ac432888790, C4<0>, C4<0>; +L_0x1368fa0 .delay 1 (30000,30000,30000) L_0x1368fa0/d; +L_0x13691a0/d .functor NAND 1, L_0x1371830, L_0x1371990, C4<1>, C4<1>; +L_0x13691a0 .delay 1 (20000,20000,20000) L_0x13691a0/d; +L_0x2ac4328887d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888820 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13692b0/d .functor OR 1, L_0x2ac4328887d8, L_0x2ac432888820, C4<0>, C4<0>; +L_0x13692b0 .delay 1 (30000,30000,30000) L_0x13692b0/d; +L_0x1369460/d .functor NOR 1, L_0x1371830, L_0x1371990, C4<0>, C4<0>; +L_0x1369460 .delay 1 (20000,20000,20000) L_0x1369460/d; +L_0x2ac432888868 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328888b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1369730/d .functor OR 1, L_0x2ac432888868, L_0x2ac4328888b0, C4<0>, C4<0>; +L_0x1369730 .delay 1 (30000,30000,30000) L_0x1369730/d; +L_0x1369b30/d .functor OR 1, L_0x1371830, L_0x1371990, C4<0>, C4<0>; +L_0x1369b30 .delay 1 (30000,30000,30000) L_0x1369b30/d; +L_0x2ac4328888f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888940 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1369fd0/d .functor OR 1, L_0x2ac4328888f8, L_0x2ac432888940, C4<0>, C4<0>; +L_0x1369fd0 .delay 1 (30000,30000,30000) L_0x1369fd0/d; +L_0x1371730/d .functor NOT 1, L_0x136d990, C4<0>, C4<0>, C4<0>; +L_0x1371730 .delay 1 (10000,10000,10000) L_0x1371730/d; +v0x11c7bc0_0 .net "A", 0 0, L_0x1371830; 1 drivers +v0x11c7c80_0 .net "A_", 0 0, L_0x135a9b0; 1 drivers +v0x11c7d40_0 .net "B", 0 0, L_0x1371990; 1 drivers +v0x11c7e10_0 .net "B_", 0 0, L_0x1367460; 1 drivers +v0x11c7eb0_0 .net *"_s11", 0 0, L_0x1368540; 1 drivers +v0x11c7fa0_0 .net/2s *"_s13", 0 0, L_0x2ac432888628; 1 drivers +v0x11c8060_0 .net/2s *"_s15", 0 0, L_0x2ac432888670; 1 drivers +v0x11c8140_0 .net *"_s19", 0 0, L_0x1368ce0; 1 drivers +v0x11c8220_0 .net/2s *"_s21", 0 0, L_0x2ac4328886b8; 1 drivers +v0x11c8390_0 .net/2s *"_s23", 0 0, L_0x2ac432888700; 1 drivers +v0x11c8470_0 .net *"_s25", 0 0, L_0x1368ee0; 1 drivers +v0x11c8550_0 .net *"_s28", 0 0, L_0x1368fa0; 1 drivers +v0x11c8630_0 .net/2s *"_s30", 0 0, L_0x2ac432888748; 1 drivers +v0x11c8710_0 .net/2s *"_s32", 0 0, L_0x2ac432888790; 1 drivers +v0x11c87f0_0 .net *"_s34", 0 0, L_0x13691a0; 1 drivers +v0x11c88d0_0 .net *"_s37", 0 0, L_0x13692b0; 1 drivers +v0x11c89b0_0 .net/2s *"_s39", 0 0, L_0x2ac4328887d8; 1 drivers +v0x11c8b60_0 .net/2s *"_s41", 0 0, L_0x2ac432888820; 1 drivers +v0x11c8c00_0 .net *"_s43", 0 0, L_0x1369460; 1 drivers +v0x11c8ce0_0 .net *"_s46", 0 0, L_0x1369730; 1 drivers +v0x11c8dc0_0 .net/2s *"_s48", 0 0, L_0x2ac432888868; 1 drivers +v0x11c8ea0_0 .net/2s *"_s50", 0 0, L_0x2ac4328888b0; 1 drivers +v0x11c8f80_0 .net *"_s52", 0 0, L_0x1369b30; 1 drivers +v0x11c9060_0 .net *"_s56", 0 0, L_0x1369fd0; 1 drivers +v0x11c9140_0 .net/2s *"_s59", 0 0, L_0x2ac4328888f8; 1 drivers +v0x11c9220_0 .net/2s *"_s61", 0 0, L_0x2ac432888940; 1 drivers +v0x11c9300_0 .net *"_s8", 0 0, L_0x1368480; 1 drivers +v0x11c93e0_0 .net "carryin", 0 0, L_0x1367240; 1 drivers +v0x11c9480_0 .net "carryout", 0 0, L_0x13713d0; 1 drivers +v0x11c9520_0 .net "carryouts", 7 0, L_0x1369c40; 1 drivers +v0x11c9630_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11c96f0_0 .net "result", 0 0, L_0x136d990; 1 drivers +v0x11c97e0_0 .net "results", 7 0, L_0x1369900; 1 drivers +v0x11c8ac0_0 .net "zero", 0 0, L_0x1371730; 1 drivers +LS_0x1369900_0_0 .concat8 [ 1 1 1 1], L_0x1367980, L_0x1367fb0, L_0x1368480, L_0x1368ce0; +LS_0x1369900_0_4 .concat8 [ 1 1 1 1], L_0x1368ee0, L_0x13691a0, L_0x1369460, L_0x1369b30; +L_0x1369900 .concat8 [ 4 4 0 0], LS_0x1369900_0_0, LS_0x1369900_0_4; +LS_0x1369c40_0_0 .concat8 [ 1 1 1 1], L_0x1367c30, L_0x1368320, L_0x1368540, L_0x1368b30; +LS_0x1369c40_0_4 .concat8 [ 1 1 1 1], L_0x1368fa0, L_0x13692b0, L_0x1369730, L_0x1369fd0; +L_0x1369c40 .concat8 [ 4 4 0 0], LS_0x1369c40_0_0, LS_0x1369c40_0_4; +S_0x11b9700 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11b9480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1367c30/d .functor OR 1, L_0x1367710, L_0x1367ad0, C4<0>, C4<0>; +L_0x1367c30 .delay 1 (30000,30000,30000) L_0x1367c30/d; +v0x11ba530_0 .net "a", 0 0, L_0x1371830; alias, 1 drivers +v0x11ba5f0_0 .net "b", 0 0, L_0x1371990; alias, 1 drivers +v0x11ba6c0_0 .net "c1", 0 0, L_0x1367710; 1 drivers +v0x11ba7c0_0 .net "c2", 0 0, L_0x1367ad0; 1 drivers +v0x11ba890_0 .net "carryin", 0 0, L_0x1367240; alias, 1 drivers +v0x11ba980_0 .net "carryout", 0 0, L_0x1367c30; 1 drivers +v0x11baa20_0 .net "s1", 0 0, L_0x1367650; 1 drivers +v0x11bab10_0 .net "sum", 0 0, L_0x1367980; 1 drivers +S_0x11b9970 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11b9700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1367650/d .functor XOR 1, L_0x1371830, L_0x1371990, C4<0>, C4<0>; +L_0x1367650 .delay 1 (30000,30000,30000) L_0x1367650/d; +L_0x1367710/d .functor AND 1, L_0x1371830, L_0x1371990, C4<1>, C4<1>; +L_0x1367710 .delay 1 (30000,30000,30000) L_0x1367710/d; +v0x11b9bd0_0 .net "a", 0 0, L_0x1371830; alias, 1 drivers +v0x11b9cb0_0 .net "b", 0 0, L_0x1371990; alias, 1 drivers +v0x11b9d70_0 .net "carryout", 0 0, L_0x1367710; alias, 1 drivers +v0x11b9e10_0 .net "sum", 0 0, L_0x1367650; alias, 1 drivers +S_0x11b9f50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11b9700; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1367980/d .functor XOR 1, L_0x1367650, L_0x1367240, C4<0>, C4<0>; +L_0x1367980 .delay 1 (30000,30000,30000) L_0x1367980/d; +L_0x1367ad0/d .functor AND 1, L_0x1367650, L_0x1367240, C4<1>, C4<1>; +L_0x1367ad0 .delay 1 (30000,30000,30000) L_0x1367ad0/d; +v0x11ba1b0_0 .net "a", 0 0, L_0x1367650; alias, 1 drivers +v0x11ba250_0 .net "b", 0 0, L_0x1367240; alias, 1 drivers +v0x11ba2f0_0 .net "carryout", 0 0, L_0x1367ad0; alias, 1 drivers +v0x11ba3c0_0 .net "sum", 0 0, L_0x1367980; alias, 1 drivers +S_0x11babe0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11b9480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11bffd0_0 .net "ands", 7 0, L_0x136f3d0; 1 drivers +v0x11c00c0_0 .net "in", 7 0, L_0x1369c40; alias, 1 drivers +v0x11c0180_0 .net "out", 0 0, L_0x13713d0; alias, 1 drivers +v0x11c0280_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11bae00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11babe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11bd530_0 .net "A", 7 0, L_0x1369c40; alias, 1 drivers +v0x11bd630_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11bd6f0_0 .net *"_s0", 0 0, L_0x136dcf0; 1 drivers +v0x11bd7b0_0 .net *"_s12", 0 0, L_0x136e660; 1 drivers +v0x11bd890_0 .net *"_s16", 0 0, L_0x136e9c0; 1 drivers +v0x11bd9c0_0 .net *"_s20", 0 0, L_0x136ed90; 1 drivers +v0x11bdaa0_0 .net *"_s24", 0 0, L_0x136f0c0; 1 drivers +v0x11bdb80_0 .net *"_s28", 0 0, L_0x136f050; 1 drivers +v0x11bdc60_0 .net *"_s4", 0 0, L_0x136e040; 1 drivers +v0x11bddd0_0 .net *"_s8", 0 0, L_0x136e350; 1 drivers +v0x11bdeb0_0 .net "out", 7 0, L_0x136f3d0; alias, 1 drivers +L_0x136ddb0 .part L_0x1369c40, 0, 1; +L_0x136dfa0 .part v0x127a150_0, 0, 1; +L_0x136e100 .part L_0x1369c40, 1, 1; +L_0x136e260 .part v0x127a150_0, 1, 1; +L_0x136e410 .part L_0x1369c40, 2, 1; +L_0x136e570 .part v0x127a150_0, 2, 1; +L_0x136e720 .part L_0x1369c40, 3, 1; +L_0x136e880 .part v0x127a150_0, 3, 1; +L_0x136ea80 .part L_0x1369c40, 4, 1; +L_0x136ecf0 .part v0x127a150_0, 4, 1; +L_0x136ee00 .part L_0x1369c40, 5, 1; +L_0x136ef60 .part v0x127a150_0, 5, 1; +L_0x136f180 .part L_0x1369c40, 6, 1; +L_0x136f2e0 .part v0x127a150_0, 6, 1; +LS_0x136f3d0_0_0 .concat8 [ 1 1 1 1], L_0x136dcf0, L_0x136e040, L_0x136e350, L_0x136e660; +LS_0x136f3d0_0_4 .concat8 [ 1 1 1 1], L_0x136e9c0, L_0x136ed90, L_0x136f0c0, L_0x136f050; +L_0x136f3d0 .concat8 [ 4 4 0 0], LS_0x136f3d0_0_0, LS_0x136f3d0_0_4; +L_0x136f790 .part L_0x1369c40, 7, 1; +L_0x136f980 .part v0x127a150_0, 7, 1; +S_0x11bb060 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bb270 .param/l "i" 0 4 54, +C4<00>; +L_0x136dcf0/d .functor AND 1, L_0x136ddb0, L_0x136dfa0, C4<1>, C4<1>; +L_0x136dcf0 .delay 1 (30000,30000,30000) L_0x136dcf0/d; +v0x11bb350_0 .net *"_s0", 0 0, L_0x136ddb0; 1 drivers +v0x11bb430_0 .net *"_s1", 0 0, L_0x136dfa0; 1 drivers +S_0x11bb510 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bb720 .param/l "i" 0 4 54, +C4<01>; +L_0x136e040/d .functor AND 1, L_0x136e100, L_0x136e260, C4<1>, C4<1>; +L_0x136e040 .delay 1 (30000,30000,30000) L_0x136e040/d; +v0x11bb7e0_0 .net *"_s0", 0 0, L_0x136e100; 1 drivers +v0x11bb8c0_0 .net *"_s1", 0 0, L_0x136e260; 1 drivers +S_0x11bb9a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bbbb0 .param/l "i" 0 4 54, +C4<010>; +L_0x136e350/d .functor AND 1, L_0x136e410, L_0x136e570, C4<1>, C4<1>; +L_0x136e350 .delay 1 (30000,30000,30000) L_0x136e350/d; +v0x11bbc50_0 .net *"_s0", 0 0, L_0x136e410; 1 drivers +v0x11bbd30_0 .net *"_s1", 0 0, L_0x136e570; 1 drivers +S_0x11bbe10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bc020 .param/l "i" 0 4 54, +C4<011>; +L_0x136e660/d .functor AND 1, L_0x136e720, L_0x136e880, C4<1>, C4<1>; +L_0x136e660 .delay 1 (30000,30000,30000) L_0x136e660/d; +v0x11bc0e0_0 .net *"_s0", 0 0, L_0x136e720; 1 drivers +v0x11bc1c0_0 .net *"_s1", 0 0, L_0x136e880; 1 drivers +S_0x11bc2a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bc500 .param/l "i" 0 4 54, +C4<0100>; +L_0x136e9c0/d .functor AND 1, L_0x136ea80, L_0x136ecf0, C4<1>, C4<1>; +L_0x136e9c0 .delay 1 (30000,30000,30000) L_0x136e9c0/d; +v0x11bc5c0_0 .net *"_s0", 0 0, L_0x136ea80; 1 drivers +v0x11bc6a0_0 .net *"_s1", 0 0, L_0x136ecf0; 1 drivers +S_0x11bc780 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bc990 .param/l "i" 0 4 54, +C4<0101>; +L_0x136ed90/d .functor AND 1, L_0x136ee00, L_0x136ef60, C4<1>, C4<1>; +L_0x136ed90 .delay 1 (30000,30000,30000) L_0x136ed90/d; +v0x11bca50_0 .net *"_s0", 0 0, L_0x136ee00; 1 drivers +v0x11bcb30_0 .net *"_s1", 0 0, L_0x136ef60; 1 drivers +S_0x11bcc10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bce20 .param/l "i" 0 4 54, +C4<0110>; +L_0x136f0c0/d .functor AND 1, L_0x136f180, L_0x136f2e0, C4<1>, C4<1>; +L_0x136f0c0 .delay 1 (30000,30000,30000) L_0x136f0c0/d; +v0x11bcee0_0 .net *"_s0", 0 0, L_0x136f180; 1 drivers +v0x11bcfc0_0 .net *"_s1", 0 0, L_0x136f2e0; 1 drivers +S_0x11bd0a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11bae00; + .timescale -9 -12; +P_0x11bd2b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x136f050/d .functor AND 1, L_0x136f790, L_0x136f980, C4<1>, C4<1>; +L_0x136f050 .delay 1 (30000,30000,30000) L_0x136f050/d; +v0x11bd370_0 .net *"_s0", 0 0, L_0x136f790; 1 drivers +v0x11bd450_0 .net *"_s1", 0 0, L_0x136f980; 1 drivers +S_0x11be010 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11babe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13713d0/d .functor OR 1, L_0x1371490, L_0x1371640, C4<0>, C4<0>; +L_0x13713d0 .delay 1 (30000,30000,30000) L_0x13713d0/d; +v0x11bfb60_0 .net *"_s10", 0 0, L_0x1371490; 1 drivers +v0x11bfc40_0 .net *"_s12", 0 0, L_0x1371640; 1 drivers +v0x11bfd20_0 .net "in", 7 0, L_0x136f3d0; alias, 1 drivers +v0x11bfdf0_0 .net "ors", 1 0, L_0x13711f0; 1 drivers +v0x11bfeb0_0 .net "out", 0 0, L_0x13713d0; alias, 1 drivers +L_0x13705c0 .part L_0x136f3d0, 0, 4; +L_0x13711f0 .concat8 [ 1 1 0 0], L_0x13702b0, L_0x1370ee0; +L_0x1371330 .part L_0x136f3d0, 4, 4; +L_0x1371490 .part L_0x13711f0, 0, 1; +L_0x1371640 .part L_0x13711f0, 1, 1; +S_0x11be1d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11be010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x136fa70/d .functor OR 1, L_0x136fb30, L_0x136fc90, C4<0>, C4<0>; +L_0x136fa70 .delay 1 (30000,30000,30000) L_0x136fa70/d; +L_0x136fec0/d .functor OR 1, L_0x136ffd0, L_0x1370130, C4<0>, C4<0>; +L_0x136fec0 .delay 1 (30000,30000,30000) L_0x136fec0/d; +L_0x13702b0/d .functor OR 1, L_0x1370320, L_0x13704d0, C4<0>, C4<0>; +L_0x13702b0 .delay 1 (30000,30000,30000) L_0x13702b0/d; +v0x11be420_0 .net *"_s0", 0 0, L_0x136fa70; 1 drivers +v0x11be520_0 .net *"_s10", 0 0, L_0x136ffd0; 1 drivers +v0x11be600_0 .net *"_s12", 0 0, L_0x1370130; 1 drivers +v0x11be6c0_0 .net *"_s14", 0 0, L_0x1370320; 1 drivers +v0x11be7a0_0 .net *"_s16", 0 0, L_0x13704d0; 1 drivers +v0x11be8d0_0 .net *"_s3", 0 0, L_0x136fb30; 1 drivers +v0x11be9b0_0 .net *"_s5", 0 0, L_0x136fc90; 1 drivers +v0x11bea90_0 .net *"_s6", 0 0, L_0x136fec0; 1 drivers +v0x11beb70_0 .net "in", 3 0, L_0x13705c0; 1 drivers +v0x11bece0_0 .net "ors", 1 0, L_0x136fdd0; 1 drivers +v0x11bedc0_0 .net "out", 0 0, L_0x13702b0; 1 drivers +L_0x136fb30 .part L_0x13705c0, 0, 1; +L_0x136fc90 .part L_0x13705c0, 1, 1; +L_0x136fdd0 .concat8 [ 1 1 0 0], L_0x136fa70, L_0x136fec0; +L_0x136ffd0 .part L_0x13705c0, 2, 1; +L_0x1370130 .part L_0x13705c0, 3, 1; +L_0x1370320 .part L_0x136fdd0, 0, 1; +L_0x13704d0 .part L_0x136fdd0, 1, 1; +S_0x11beee0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11be010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13706f0/d .functor OR 1, L_0x1370760, L_0x13708c0, C4<0>, C4<0>; +L_0x13706f0 .delay 1 (30000,30000,30000) L_0x13706f0/d; +L_0x1370af0/d .functor OR 1, L_0x1370c00, L_0x1370d60, C4<0>, C4<0>; +L_0x1370af0 .delay 1 (30000,30000,30000) L_0x1370af0/d; +L_0x1370ee0/d .functor OR 1, L_0x1370f50, L_0x1371100, C4<0>, C4<0>; +L_0x1370ee0 .delay 1 (30000,30000,30000) L_0x1370ee0/d; +v0x11bf0a0_0 .net *"_s0", 0 0, L_0x13706f0; 1 drivers +v0x11bf1a0_0 .net *"_s10", 0 0, L_0x1370c00; 1 drivers +v0x11bf280_0 .net *"_s12", 0 0, L_0x1370d60; 1 drivers +v0x11bf340_0 .net *"_s14", 0 0, L_0x1370f50; 1 drivers +v0x11bf420_0 .net *"_s16", 0 0, L_0x1371100; 1 drivers +v0x11bf550_0 .net *"_s3", 0 0, L_0x1370760; 1 drivers +v0x11bf630_0 .net *"_s5", 0 0, L_0x13708c0; 1 drivers +v0x11bf710_0 .net *"_s6", 0 0, L_0x1370af0; 1 drivers +v0x11bf7f0_0 .net "in", 3 0, L_0x1371330; 1 drivers +v0x11bf960_0 .net "ors", 1 0, L_0x1370a00; 1 drivers +v0x11bfa40_0 .net "out", 0 0, L_0x1370ee0; 1 drivers +L_0x1370760 .part L_0x1371330, 0, 1; +L_0x13708c0 .part L_0x1371330, 1, 1; +L_0x1370a00 .concat8 [ 1 1 0 0], L_0x13706f0, L_0x1370af0; +L_0x1370c00 .part L_0x1371330, 2, 1; +L_0x1370d60 .part L_0x1371330, 3, 1; +L_0x1370f50 .part L_0x1370a00, 0, 1; +L_0x1371100 .part L_0x1370a00, 1, 1; +S_0x11c0360 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11b9480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11c5790_0 .net "ands", 7 0, L_0x136b990; 1 drivers +v0x11c58a0_0 .net "in", 7 0, L_0x1369900; alias, 1 drivers +v0x11c5960_0 .net "out", 0 0, L_0x136d990; alias, 1 drivers +v0x11c5a30_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11c05b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11c0360; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11c2cf0_0 .net "A", 7 0, L_0x1369900; alias, 1 drivers +v0x11c2df0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11c2eb0_0 .net *"_s0", 0 0, L_0x136a180; 1 drivers +v0x11c2f70_0 .net *"_s12", 0 0, L_0x136ab40; 1 drivers +v0x11c3050_0 .net *"_s16", 0 0, L_0x136aea0; 1 drivers +v0x11c3180_0 .net *"_s20", 0 0, L_0x136b2d0; 1 drivers +v0x11c3260_0 .net *"_s24", 0 0, L_0x136b600; 1 drivers +v0x11c3340_0 .net *"_s28", 0 0, L_0x136b590; 1 drivers +v0x11c3420_0 .net *"_s4", 0 0, L_0x136a520; 1 drivers +v0x11c3590_0 .net *"_s8", 0 0, L_0x136a830; 1 drivers +v0x11c3670_0 .net "out", 7 0, L_0x136b990; alias, 1 drivers +L_0x136a290 .part L_0x1369900, 0, 1; +L_0x136a480 .part v0x127a150_0, 0, 1; +L_0x136a5e0 .part L_0x1369900, 1, 1; +L_0x136a740 .part v0x127a150_0, 1, 1; +L_0x136a8f0 .part L_0x1369900, 2, 1; +L_0x136aa50 .part v0x127a150_0, 2, 1; +L_0x136ac00 .part L_0x1369900, 3, 1; +L_0x136ad60 .part v0x127a150_0, 3, 1; +L_0x136af60 .part L_0x1369900, 4, 1; +L_0x136b1d0 .part v0x127a150_0, 4, 1; +L_0x136b340 .part L_0x1369900, 5, 1; +L_0x136b4a0 .part v0x127a150_0, 5, 1; +L_0x136b6c0 .part L_0x1369900, 6, 1; +L_0x136b820 .part v0x127a150_0, 6, 1; +LS_0x136b990_0_0 .concat8 [ 1 1 1 1], L_0x136a180, L_0x136a520, L_0x136a830, L_0x136ab40; +LS_0x136b990_0_4 .concat8 [ 1 1 1 1], L_0x136aea0, L_0x136b2d0, L_0x136b600, L_0x136b590; +L_0x136b990 .concat8 [ 4 4 0 0], LS_0x136b990_0_0, LS_0x136b990_0_4; +L_0x136bd50 .part L_0x1369900, 7, 1; +L_0x136bf40 .part v0x127a150_0, 7, 1; +S_0x11c07f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c0a00 .param/l "i" 0 4 54, +C4<00>; +L_0x136a180/d .functor AND 1, L_0x136a290, L_0x136a480, C4<1>, C4<1>; +L_0x136a180 .delay 1 (30000,30000,30000) L_0x136a180/d; +v0x11c0ae0_0 .net *"_s0", 0 0, L_0x136a290; 1 drivers +v0x11c0bc0_0 .net *"_s1", 0 0, L_0x136a480; 1 drivers +S_0x11c0ca0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c0eb0 .param/l "i" 0 4 54, +C4<01>; +L_0x136a520/d .functor AND 1, L_0x136a5e0, L_0x136a740, C4<1>, C4<1>; +L_0x136a520 .delay 1 (30000,30000,30000) L_0x136a520/d; +v0x11c0f70_0 .net *"_s0", 0 0, L_0x136a5e0; 1 drivers +v0x11c1050_0 .net *"_s1", 0 0, L_0x136a740; 1 drivers +S_0x11c1130 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c1370 .param/l "i" 0 4 54, +C4<010>; +L_0x136a830/d .functor AND 1, L_0x136a8f0, L_0x136aa50, C4<1>, C4<1>; +L_0x136a830 .delay 1 (30000,30000,30000) L_0x136a830/d; +v0x11c1410_0 .net *"_s0", 0 0, L_0x136a8f0; 1 drivers +v0x11c14f0_0 .net *"_s1", 0 0, L_0x136aa50; 1 drivers +S_0x11c15d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c17e0 .param/l "i" 0 4 54, +C4<011>; +L_0x136ab40/d .functor AND 1, L_0x136ac00, L_0x136ad60, C4<1>, C4<1>; +L_0x136ab40 .delay 1 (30000,30000,30000) L_0x136ab40/d; +v0x11c18a0_0 .net *"_s0", 0 0, L_0x136ac00; 1 drivers +v0x11c1980_0 .net *"_s1", 0 0, L_0x136ad60; 1 drivers +S_0x11c1a60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c1cc0 .param/l "i" 0 4 54, +C4<0100>; +L_0x136aea0/d .functor AND 1, L_0x136af60, L_0x136b1d0, C4<1>, C4<1>; +L_0x136aea0 .delay 1 (30000,30000,30000) L_0x136aea0/d; +v0x11c1d80_0 .net *"_s0", 0 0, L_0x136af60; 1 drivers +v0x11c1e60_0 .net *"_s1", 0 0, L_0x136b1d0; 1 drivers +S_0x11c1f40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c2150 .param/l "i" 0 4 54, +C4<0101>; +L_0x136b2d0/d .functor AND 1, L_0x136b340, L_0x136b4a0, C4<1>, C4<1>; +L_0x136b2d0 .delay 1 (30000,30000,30000) L_0x136b2d0/d; +v0x11c2210_0 .net *"_s0", 0 0, L_0x136b340; 1 drivers +v0x11c22f0_0 .net *"_s1", 0 0, L_0x136b4a0; 1 drivers +S_0x11c23d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c25e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x136b600/d .functor AND 1, L_0x136b6c0, L_0x136b820, C4<1>, C4<1>; +L_0x136b600 .delay 1 (30000,30000,30000) L_0x136b600/d; +v0x11c26a0_0 .net *"_s0", 0 0, L_0x136b6c0; 1 drivers +v0x11c2780_0 .net *"_s1", 0 0, L_0x136b820; 1 drivers +S_0x11c2860 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11c05b0; + .timescale -9 -12; +P_0x11c2a70 .param/l "i" 0 4 54, +C4<0111>; +L_0x136b590/d .functor AND 1, L_0x136bd50, L_0x136bf40, C4<1>, C4<1>; +L_0x136b590 .delay 1 (30000,30000,30000) L_0x136b590/d; +v0x11c2b30_0 .net *"_s0", 0 0, L_0x136bd50; 1 drivers +v0x11c2c10_0 .net *"_s1", 0 0, L_0x136bf40; 1 drivers +S_0x11c37d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11c0360; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x136d990/d .functor OR 1, L_0x136da50, L_0x136dc00, C4<0>, C4<0>; +L_0x136d990 .delay 1 (30000,30000,30000) L_0x136d990/d; +v0x11c5320_0 .net *"_s10", 0 0, L_0x136da50; 1 drivers +v0x11c5400_0 .net *"_s12", 0 0, L_0x136dc00; 1 drivers +v0x11c54e0_0 .net "in", 7 0, L_0x136b990; alias, 1 drivers +v0x11c55b0_0 .net "ors", 1 0, L_0x136d7b0; 1 drivers +v0x11c5670_0 .net "out", 0 0, L_0x136d990; alias, 1 drivers +L_0x136cb80 .part L_0x136b990, 0, 4; +L_0x136d7b0 .concat8 [ 1 1 0 0], L_0x136c870, L_0x136d4a0; +L_0x136d8f0 .part L_0x136b990, 4, 4; +L_0x136da50 .part L_0x136d7b0, 0, 1; +L_0x136dc00 .part L_0x136d7b0, 1, 1; +S_0x11c3990 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11c37d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x136c030/d .functor OR 1, L_0x136c0f0, L_0x136c250, C4<0>, C4<0>; +L_0x136c030 .delay 1 (30000,30000,30000) L_0x136c030/d; +L_0x136c480/d .functor OR 1, L_0x136c590, L_0x136c6f0, C4<0>, C4<0>; +L_0x136c480 .delay 1 (30000,30000,30000) L_0x136c480/d; +L_0x136c870/d .functor OR 1, L_0x136c8e0, L_0x136ca90, C4<0>, C4<0>; +L_0x136c870 .delay 1 (30000,30000,30000) L_0x136c870/d; +v0x11c3be0_0 .net *"_s0", 0 0, L_0x136c030; 1 drivers +v0x11c3ce0_0 .net *"_s10", 0 0, L_0x136c590; 1 drivers +v0x11c3dc0_0 .net *"_s12", 0 0, L_0x136c6f0; 1 drivers +v0x11c3e80_0 .net *"_s14", 0 0, L_0x136c8e0; 1 drivers +v0x11c3f60_0 .net *"_s16", 0 0, L_0x136ca90; 1 drivers +v0x11c4090_0 .net *"_s3", 0 0, L_0x136c0f0; 1 drivers +v0x11c4170_0 .net *"_s5", 0 0, L_0x136c250; 1 drivers +v0x11c4250_0 .net *"_s6", 0 0, L_0x136c480; 1 drivers +v0x11c4330_0 .net "in", 3 0, L_0x136cb80; 1 drivers +v0x11c44a0_0 .net "ors", 1 0, L_0x136c390; 1 drivers +v0x11c4580_0 .net "out", 0 0, L_0x136c870; 1 drivers +L_0x136c0f0 .part L_0x136cb80, 0, 1; +L_0x136c250 .part L_0x136cb80, 1, 1; +L_0x136c390 .concat8 [ 1 1 0 0], L_0x136c030, L_0x136c480; +L_0x136c590 .part L_0x136cb80, 2, 1; +L_0x136c6f0 .part L_0x136cb80, 3, 1; +L_0x136c8e0 .part L_0x136c390, 0, 1; +L_0x136ca90 .part L_0x136c390, 1, 1; +S_0x11c46a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11c37d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x136ccb0/d .functor OR 1, L_0x136cd20, L_0x136ce80, C4<0>, C4<0>; +L_0x136ccb0 .delay 1 (30000,30000,30000) L_0x136ccb0/d; +L_0x136d0b0/d .functor OR 1, L_0x136d1c0, L_0x136d320, C4<0>, C4<0>; +L_0x136d0b0 .delay 1 (30000,30000,30000) L_0x136d0b0/d; +L_0x136d4a0/d .functor OR 1, L_0x136d510, L_0x136d6c0, C4<0>, C4<0>; +L_0x136d4a0 .delay 1 (30000,30000,30000) L_0x136d4a0/d; +v0x11c4860_0 .net *"_s0", 0 0, L_0x136ccb0; 1 drivers +v0x11c4960_0 .net *"_s10", 0 0, L_0x136d1c0; 1 drivers +v0x11c4a40_0 .net *"_s12", 0 0, L_0x136d320; 1 drivers +v0x11c4b00_0 .net *"_s14", 0 0, L_0x136d510; 1 drivers +v0x11c4be0_0 .net *"_s16", 0 0, L_0x136d6c0; 1 drivers +v0x11c4d10_0 .net *"_s3", 0 0, L_0x136cd20; 1 drivers +v0x11c4df0_0 .net *"_s5", 0 0, L_0x136ce80; 1 drivers +v0x11c4ed0_0 .net *"_s6", 0 0, L_0x136d0b0; 1 drivers +v0x11c4fb0_0 .net "in", 3 0, L_0x136d8f0; 1 drivers +v0x11c5120_0 .net "ors", 1 0, L_0x136cfc0; 1 drivers +v0x11c5200_0 .net "out", 0 0, L_0x136d4a0; 1 drivers +L_0x136cd20 .part L_0x136d8f0, 0, 1; +L_0x136ce80 .part L_0x136d8f0, 1, 1; +L_0x136cfc0 .concat8 [ 1 1 0 0], L_0x136ccb0, L_0x136d0b0; +L_0x136d1c0 .part L_0x136d8f0, 2, 1; +L_0x136d320 .part L_0x136d8f0, 3, 1; +L_0x136d510 .part L_0x136cfc0, 0, 1; +L_0x136d6c0 .part L_0x136cfc0, 1, 1; +S_0x11c5b10 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11b9480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1368740/d .functor XNOR 1, L_0x1371830, L_0x1371990, C4<0>, C4<0>; +L_0x1368740 .delay 1 (20000,20000,20000) L_0x1368740/d; +L_0x13688c0/d .functor AND 1, L_0x1371830, L_0x1367460, C4<1>, C4<1>; +L_0x13688c0 .delay 1 (30000,30000,30000) L_0x13688c0/d; +L_0x1368a20/d .functor AND 1, L_0x1368740, L_0x1367240, C4<1>, C4<1>; +L_0x1368a20 .delay 1 (30000,30000,30000) L_0x1368a20/d; +L_0x1368b30/d .functor OR 1, L_0x1368a20, L_0x13688c0, C4<0>, C4<0>; +L_0x1368b30 .delay 1 (30000,30000,30000) L_0x1368b30/d; +v0x11c5dc0_0 .net "a", 0 0, L_0x1371830; alias, 1 drivers +v0x11c5eb0_0 .net "a_", 0 0, L_0x135a9b0; alias, 1 drivers +v0x11c5f70_0 .net "b", 0 0, L_0x1371990; alias, 1 drivers +v0x11c6060_0 .net "b_", 0 0, L_0x1367460; alias, 1 drivers +v0x11c6100_0 .net "carryin", 0 0, L_0x1367240; alias, 1 drivers +v0x11c6240_0 .net "eq", 0 0, L_0x1368740; 1 drivers +v0x11c6300_0 .net "lt", 0 0, L_0x13688c0; 1 drivers +v0x11c63c0_0 .net "out", 0 0, L_0x1368b30; 1 drivers +v0x11c6480_0 .net "w0", 0 0, L_0x1368a20; 1 drivers +S_0x11c66d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11b9480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1368320/d .functor OR 1, L_0x1367e50, L_0x1368210, C4<0>, C4<0>; +L_0x1368320 .delay 1 (30000,30000,30000) L_0x1368320/d; +v0x11c74c0_0 .net "a", 0 0, L_0x1371830; alias, 1 drivers +v0x11c7610_0 .net "b", 0 0, L_0x1367460; alias, 1 drivers +v0x11c76d0_0 .net "c1", 0 0, L_0x1367e50; 1 drivers +v0x11c7770_0 .net "c2", 0 0, L_0x1368210; 1 drivers +v0x11c7840_0 .net "carryin", 0 0, L_0x1367240; alias, 1 drivers +v0x11c79c0_0 .net "carryout", 0 0, L_0x1368320; 1 drivers +v0x11c7a60_0 .net "s1", 0 0, L_0x1367d90; 1 drivers +v0x11c7b00_0 .net "sum", 0 0, L_0x1367fb0; 1 drivers +S_0x11c6920 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11c66d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1367d90/d .functor XOR 1, L_0x1371830, L_0x1367460, C4<0>, C4<0>; +L_0x1367d90 .delay 1 (30000,30000,30000) L_0x1367d90/d; +L_0x1367e50/d .functor AND 1, L_0x1371830, L_0x1367460, C4<1>, C4<1>; +L_0x1367e50 .delay 1 (30000,30000,30000) L_0x1367e50/d; +v0x11c6b80_0 .net "a", 0 0, L_0x1371830; alias, 1 drivers +v0x11c6c40_0 .net "b", 0 0, L_0x1367460; alias, 1 drivers +v0x11c6d00_0 .net "carryout", 0 0, L_0x1367e50; alias, 1 drivers +v0x11c6da0_0 .net "sum", 0 0, L_0x1367d90; alias, 1 drivers +S_0x11c6ed0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11c66d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1367fb0/d .functor XOR 1, L_0x1367d90, L_0x1367240, C4<0>, C4<0>; +L_0x1367fb0 .delay 1 (30000,30000,30000) L_0x1367fb0/d; +L_0x1368210/d .functor AND 1, L_0x1367d90, L_0x1367240, C4<1>, C4<1>; +L_0x1368210 .delay 1 (30000,30000,30000) L_0x1368210/d; +v0x11c7130_0 .net "a", 0 0, L_0x1367d90; alias, 1 drivers +v0x11c7200_0 .net "b", 0 0, L_0x1367240; alias, 1 drivers +v0x11c72a0_0 .net "carryout", 0 0, L_0x1368210; alias, 1 drivers +v0x11c7370_0 .net "sum", 0 0, L_0x1367fb0; alias, 1 drivers +S_0x11c9b90 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11b91b0; + .timescale -9 -12; +L_0x2ac432888988 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328889d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1367910/d .functor OR 1, L_0x2ac432888988, L_0x2ac4328889d0, C4<0>, C4<0>; +L_0x1367910 .delay 1 (30000,30000,30000) L_0x1367910/d; +v0x11c9d80_0 .net/2u *"_s0", 0 0, L_0x2ac432888988; 1 drivers +v0x11c9e60_0 .net/2u *"_s2", 0 0, L_0x2ac4328889d0; 1 drivers +S_0x11c9f40 .scope generate, "alu_slices[23]" "alu_slices[23]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11ca150 .param/l "i" 0 3 39, +C4<010111>; +S_0x11ca210 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11c9f40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13673d0/d .functor NOT 1, L_0x137c060, C4<0>, C4<0>, C4<0>; +L_0x13673d0 .delay 1 (10000,10000,10000) L_0x13673d0/d; +L_0x1371d00/d .functor NOT 1, L_0x1371a30, C4<0>, C4<0>, C4<0>; +L_0x1371d00 .delay 1 (10000,10000,10000) L_0x1371d00/d; +L_0x1372cb0/d .functor XOR 1, L_0x137c060, L_0x1371a30, C4<0>, C4<0>; +L_0x1372cb0 .delay 1 (30000,30000,30000) L_0x1372cb0/d; +L_0x2ac432888a18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888a60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1372d70/d .functor OR 1, L_0x2ac432888a18, L_0x2ac432888a60, C4<0>, C4<0>; +L_0x1372d70 .delay 1 (30000,30000,30000) L_0x1372d70/d; +L_0x2ac432888aa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888af0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1373510/d .functor OR 1, L_0x2ac432888aa8, L_0x2ac432888af0, C4<0>, C4<0>; +L_0x1373510 .delay 1 (30000,30000,30000) L_0x1373510/d; +L_0x1373710/d .functor AND 1, L_0x137c060, L_0x1371a30, C4<1>, C4<1>; +L_0x1373710 .delay 1 (30000,30000,30000) L_0x1373710/d; +L_0x2ac432888b38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888b80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13737d0/d .functor OR 1, L_0x2ac432888b38, L_0x2ac432888b80, C4<0>, C4<0>; +L_0x13737d0 .delay 1 (30000,30000,30000) L_0x13737d0/d; +L_0x13739d0/d .functor NAND 1, L_0x137c060, L_0x1371a30, C4<1>, C4<1>; +L_0x13739d0 .delay 1 (20000,20000,20000) L_0x13739d0/d; +L_0x2ac432888bc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888c10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1373ae0/d .functor OR 1, L_0x2ac432888bc8, L_0x2ac432888c10, C4<0>, C4<0>; +L_0x1373ae0 .delay 1 (30000,30000,30000) L_0x1373ae0/d; +L_0x1373c90/d .functor NOR 1, L_0x137c060, L_0x1371a30, C4<0>, C4<0>; +L_0x1373c90 .delay 1 (20000,20000,20000) L_0x1373c90/d; +L_0x2ac432888c58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888ca0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1373f60/d .functor OR 1, L_0x2ac432888c58, L_0x2ac432888ca0, C4<0>, C4<0>; +L_0x1373f60 .delay 1 (30000,30000,30000) L_0x1373f60/d; +L_0x1374360/d .functor OR 1, L_0x137c060, L_0x1371a30, C4<0>, C4<0>; +L_0x1374360 .delay 1 (30000,30000,30000) L_0x1374360/d; +L_0x2ac432888ce8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888d30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1374800/d .functor OR 1, L_0x2ac432888ce8, L_0x2ac432888d30, C4<0>, C4<0>; +L_0x1374800 .delay 1 (30000,30000,30000) L_0x1374800/d; +L_0x137bf60/d .functor NOT 1, L_0x13781c0, C4<0>, C4<0>, C4<0>; +L_0x137bf60 .delay 1 (10000,10000,10000) L_0x137bf60/d; +v0x11d8940_0 .net "A", 0 0, L_0x137c060; 1 drivers +v0x11d8a00_0 .net "A_", 0 0, L_0x13673d0; 1 drivers +v0x11d8ac0_0 .net "B", 0 0, L_0x1371a30; 1 drivers +v0x11d8b90_0 .net "B_", 0 0, L_0x1371d00; 1 drivers +v0x11d8c30_0 .net *"_s11", 0 0, L_0x1372d70; 1 drivers +v0x11d8d20_0 .net/2s *"_s13", 0 0, L_0x2ac432888a18; 1 drivers +v0x11d8de0_0 .net/2s *"_s15", 0 0, L_0x2ac432888a60; 1 drivers +v0x11d8ec0_0 .net *"_s19", 0 0, L_0x1373510; 1 drivers +v0x11d8fa0_0 .net/2s *"_s21", 0 0, L_0x2ac432888aa8; 1 drivers +v0x11d9110_0 .net/2s *"_s23", 0 0, L_0x2ac432888af0; 1 drivers +v0x11d91f0_0 .net *"_s25", 0 0, L_0x1373710; 1 drivers +v0x11d92d0_0 .net *"_s28", 0 0, L_0x13737d0; 1 drivers +v0x11d93b0_0 .net/2s *"_s30", 0 0, L_0x2ac432888b38; 1 drivers +v0x11d9490_0 .net/2s *"_s32", 0 0, L_0x2ac432888b80; 1 drivers +v0x11d9570_0 .net *"_s34", 0 0, L_0x13739d0; 1 drivers +v0x11d9650_0 .net *"_s37", 0 0, L_0x1373ae0; 1 drivers +v0x11d9730_0 .net/2s *"_s39", 0 0, L_0x2ac432888bc8; 1 drivers +v0x11d98e0_0 .net/2s *"_s41", 0 0, L_0x2ac432888c10; 1 drivers +v0x11d9980_0 .net *"_s43", 0 0, L_0x1373c90; 1 drivers +v0x11d9a60_0 .net *"_s46", 0 0, L_0x1373f60; 1 drivers +v0x11d9b40_0 .net/2s *"_s48", 0 0, L_0x2ac432888c58; 1 drivers +v0x11d9c20_0 .net/2s *"_s50", 0 0, L_0x2ac432888ca0; 1 drivers +v0x11d9d00_0 .net *"_s52", 0 0, L_0x1374360; 1 drivers +v0x11d9de0_0 .net *"_s56", 0 0, L_0x1374800; 1 drivers +v0x11d9ec0_0 .net/2s *"_s59", 0 0, L_0x2ac432888ce8; 1 drivers +v0x11d9fa0_0 .net/2s *"_s61", 0 0, L_0x2ac432888d30; 1 drivers +v0x11da080_0 .net *"_s8", 0 0, L_0x1372cb0; 1 drivers +v0x11da160_0 .net "carryin", 0 0, L_0x1371ad0; 1 drivers +v0x11da200_0 .net "carryout", 0 0, L_0x137bc00; 1 drivers +v0x11da2a0_0 .net "carryouts", 7 0, L_0x1374470; 1 drivers +v0x11da3b0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11da470_0 .net "result", 0 0, L_0x13781c0; 1 drivers +v0x11da560_0 .net "results", 7 0, L_0x1374130; 1 drivers +v0x11d9840_0 .net "zero", 0 0, L_0x137bf60; 1 drivers +LS_0x1374130_0_0 .concat8 [ 1 1 1 1], L_0x13721d0, L_0x1372800, L_0x1372cb0, L_0x1373510; +LS_0x1374130_0_4 .concat8 [ 1 1 1 1], L_0x1373710, L_0x13739d0, L_0x1373c90, L_0x1374360; +L_0x1374130 .concat8 [ 4 4 0 0], LS_0x1374130_0_0, LS_0x1374130_0_4; +LS_0x1374470_0_0 .concat8 [ 1 1 1 1], L_0x1372480, L_0x1372b50, L_0x1372d70, L_0x1373360; +LS_0x1374470_0_4 .concat8 [ 1 1 1 1], L_0x13737d0, L_0x1373ae0, L_0x1373f60, L_0x1374800; +L_0x1374470 .concat8 [ 4 4 0 0], LS_0x1374470_0_0, LS_0x1374470_0_4; +S_0x11ca490 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11ca210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1372480/d .functor OR 1, L_0x1371f60, L_0x1372320, C4<0>, C4<0>; +L_0x1372480 .delay 1 (30000,30000,30000) L_0x1372480/d; +v0x11cb2c0_0 .net "a", 0 0, L_0x137c060; alias, 1 drivers +v0x11cb380_0 .net "b", 0 0, L_0x1371a30; alias, 1 drivers +v0x11cb450_0 .net "c1", 0 0, L_0x1371f60; 1 drivers +v0x11cb550_0 .net "c2", 0 0, L_0x1372320; 1 drivers +v0x11cb620_0 .net "carryin", 0 0, L_0x1371ad0; alias, 1 drivers +v0x11cb710_0 .net "carryout", 0 0, L_0x1372480; 1 drivers +v0x11cb7b0_0 .net "s1", 0 0, L_0x1371ef0; 1 drivers +v0x11cb8a0_0 .net "sum", 0 0, L_0x13721d0; 1 drivers +S_0x11ca700 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11ca490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1371ef0/d .functor XOR 1, L_0x137c060, L_0x1371a30, C4<0>, C4<0>; +L_0x1371ef0 .delay 1 (30000,30000,30000) L_0x1371ef0/d; +L_0x1371f60/d .functor AND 1, L_0x137c060, L_0x1371a30, C4<1>, C4<1>; +L_0x1371f60 .delay 1 (30000,30000,30000) L_0x1371f60/d; +v0x11ca960_0 .net "a", 0 0, L_0x137c060; alias, 1 drivers +v0x11caa40_0 .net "b", 0 0, L_0x1371a30; alias, 1 drivers +v0x11cab00_0 .net "carryout", 0 0, L_0x1371f60; alias, 1 drivers +v0x11caba0_0 .net "sum", 0 0, L_0x1371ef0; alias, 1 drivers +S_0x11cace0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11ca490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13721d0/d .functor XOR 1, L_0x1371ef0, L_0x1371ad0, C4<0>, C4<0>; +L_0x13721d0 .delay 1 (30000,30000,30000) L_0x13721d0/d; +L_0x1372320/d .functor AND 1, L_0x1371ef0, L_0x1371ad0, C4<1>, C4<1>; +L_0x1372320 .delay 1 (30000,30000,30000) L_0x1372320/d; +v0x11caf40_0 .net "a", 0 0, L_0x1371ef0; alias, 1 drivers +v0x11cafe0_0 .net "b", 0 0, L_0x1371ad0; alias, 1 drivers +v0x11cb080_0 .net "carryout", 0 0, L_0x1372320; alias, 1 drivers +v0x11cb150_0 .net "sum", 0 0, L_0x13721d0; alias, 1 drivers +S_0x11cb970 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11ca210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11d0d60_0 .net "ands", 7 0, L_0x1379c00; 1 drivers +v0x11d0e70_0 .net "in", 7 0, L_0x1374470; alias, 1 drivers +v0x11d0f30_0 .net "out", 0 0, L_0x137bc00; alias, 1 drivers +v0x11d1000_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11cbb90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11cb970; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11ce2c0_0 .net "A", 7 0, L_0x1374470; alias, 1 drivers +v0x11ce3c0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11ce480_0 .net *"_s0", 0 0, L_0x1378520; 1 drivers +v0x11ce540_0 .net *"_s12", 0 0, L_0x1378e90; 1 drivers +v0x11ce620_0 .net *"_s16", 0 0, L_0x13791f0; 1 drivers +v0x11ce750_0 .net *"_s20", 0 0, L_0x13795c0; 1 drivers +v0x11ce830_0 .net *"_s24", 0 0, L_0x13798f0; 1 drivers +v0x11ce910_0 .net *"_s28", 0 0, L_0x1379880; 1 drivers +v0x11ce9f0_0 .net *"_s4", 0 0, L_0x1378870; 1 drivers +v0x11ceb60_0 .net *"_s8", 0 0, L_0x1378b80; 1 drivers +v0x11cec40_0 .net "out", 7 0, L_0x1379c00; alias, 1 drivers +L_0x13785e0 .part L_0x1374470, 0, 1; +L_0x13787d0 .part v0x127a150_0, 0, 1; +L_0x1378930 .part L_0x1374470, 1, 1; +L_0x1378a90 .part v0x127a150_0, 1, 1; +L_0x1378c40 .part L_0x1374470, 2, 1; +L_0x1378da0 .part v0x127a150_0, 2, 1; +L_0x1378f50 .part L_0x1374470, 3, 1; +L_0x13790b0 .part v0x127a150_0, 3, 1; +L_0x13792b0 .part L_0x1374470, 4, 1; +L_0x1379520 .part v0x127a150_0, 4, 1; +L_0x1379630 .part L_0x1374470, 5, 1; +L_0x1379790 .part v0x127a150_0, 5, 1; +L_0x13799b0 .part L_0x1374470, 6, 1; +L_0x1379b10 .part v0x127a150_0, 6, 1; +LS_0x1379c00_0_0 .concat8 [ 1 1 1 1], L_0x1378520, L_0x1378870, L_0x1378b80, L_0x1378e90; +LS_0x1379c00_0_4 .concat8 [ 1 1 1 1], L_0x13791f0, L_0x13795c0, L_0x13798f0, L_0x1379880; +L_0x1379c00 .concat8 [ 4 4 0 0], LS_0x1379c00_0_0, LS_0x1379c00_0_4; +L_0x1379fc0 .part L_0x1374470, 7, 1; +L_0x137a1b0 .part v0x127a150_0, 7, 1; +S_0x11cbdf0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11cc000 .param/l "i" 0 4 54, +C4<00>; +L_0x1378520/d .functor AND 1, L_0x13785e0, L_0x13787d0, C4<1>, C4<1>; +L_0x1378520 .delay 1 (30000,30000,30000) L_0x1378520/d; +v0x11cc0e0_0 .net *"_s0", 0 0, L_0x13785e0; 1 drivers +v0x11cc1c0_0 .net *"_s1", 0 0, L_0x13787d0; 1 drivers +S_0x11cc2a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11cc4b0 .param/l "i" 0 4 54, +C4<01>; +L_0x1378870/d .functor AND 1, L_0x1378930, L_0x1378a90, C4<1>, C4<1>; +L_0x1378870 .delay 1 (30000,30000,30000) L_0x1378870/d; +v0x11cc570_0 .net *"_s0", 0 0, L_0x1378930; 1 drivers +v0x11cc650_0 .net *"_s1", 0 0, L_0x1378a90; 1 drivers +S_0x11cc730 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11cc940 .param/l "i" 0 4 54, +C4<010>; +L_0x1378b80/d .functor AND 1, L_0x1378c40, L_0x1378da0, C4<1>, C4<1>; +L_0x1378b80 .delay 1 (30000,30000,30000) L_0x1378b80/d; +v0x11cc9e0_0 .net *"_s0", 0 0, L_0x1378c40; 1 drivers +v0x11ccac0_0 .net *"_s1", 0 0, L_0x1378da0; 1 drivers +S_0x11ccba0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11ccdb0 .param/l "i" 0 4 54, +C4<011>; +L_0x1378e90/d .functor AND 1, L_0x1378f50, L_0x13790b0, C4<1>, C4<1>; +L_0x1378e90 .delay 1 (30000,30000,30000) L_0x1378e90/d; +v0x11cce70_0 .net *"_s0", 0 0, L_0x1378f50; 1 drivers +v0x11ccf50_0 .net *"_s1", 0 0, L_0x13790b0; 1 drivers +S_0x11cd030 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11cd290 .param/l "i" 0 4 54, +C4<0100>; +L_0x13791f0/d .functor AND 1, L_0x13792b0, L_0x1379520, C4<1>, C4<1>; +L_0x13791f0 .delay 1 (30000,30000,30000) L_0x13791f0/d; +v0x11cd350_0 .net *"_s0", 0 0, L_0x13792b0; 1 drivers +v0x11cd430_0 .net *"_s1", 0 0, L_0x1379520; 1 drivers +S_0x11cd510 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11cd720 .param/l "i" 0 4 54, +C4<0101>; +L_0x13795c0/d .functor AND 1, L_0x1379630, L_0x1379790, C4<1>, C4<1>; +L_0x13795c0 .delay 1 (30000,30000,30000) L_0x13795c0/d; +v0x11cd7e0_0 .net *"_s0", 0 0, L_0x1379630; 1 drivers +v0x11cd8c0_0 .net *"_s1", 0 0, L_0x1379790; 1 drivers +S_0x11cd9a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11cdbb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x13798f0/d .functor AND 1, L_0x13799b0, L_0x1379b10, C4<1>, C4<1>; +L_0x13798f0 .delay 1 (30000,30000,30000) L_0x13798f0/d; +v0x11cdc70_0 .net *"_s0", 0 0, L_0x13799b0; 1 drivers +v0x11cdd50_0 .net *"_s1", 0 0, L_0x1379b10; 1 drivers +S_0x11cde30 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11cbb90; + .timescale -9 -12; +P_0x11ce040 .param/l "i" 0 4 54, +C4<0111>; +L_0x1379880/d .functor AND 1, L_0x1379fc0, L_0x137a1b0, C4<1>, C4<1>; +L_0x1379880 .delay 1 (30000,30000,30000) L_0x1379880/d; +v0x11ce100_0 .net *"_s0", 0 0, L_0x1379fc0; 1 drivers +v0x11ce1e0_0 .net *"_s1", 0 0, L_0x137a1b0; 1 drivers +S_0x11ceda0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11cb970; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x137bc00/d .functor OR 1, L_0x137bcc0, L_0x137be70, C4<0>, C4<0>; +L_0x137bc00 .delay 1 (30000,30000,30000) L_0x137bc00/d; +v0x11d08f0_0 .net *"_s10", 0 0, L_0x137bcc0; 1 drivers +v0x11d09d0_0 .net *"_s12", 0 0, L_0x137be70; 1 drivers +v0x11d0ab0_0 .net "in", 7 0, L_0x1379c00; alias, 1 drivers +v0x11d0b80_0 .net "ors", 1 0, L_0x137ba20; 1 drivers +v0x11d0c40_0 .net "out", 0 0, L_0x137bc00; alias, 1 drivers +L_0x137adf0 .part L_0x1379c00, 0, 4; +L_0x137ba20 .concat8 [ 1 1 0 0], L_0x137aae0, L_0x137b710; +L_0x137bb60 .part L_0x1379c00, 4, 4; +L_0x137bcc0 .part L_0x137ba20, 0, 1; +L_0x137be70 .part L_0x137ba20, 1, 1; +S_0x11cef60 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11ceda0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x137a2a0/d .functor OR 1, L_0x137a360, L_0x137a4c0, C4<0>, C4<0>; +L_0x137a2a0 .delay 1 (30000,30000,30000) L_0x137a2a0/d; +L_0x137a6f0/d .functor OR 1, L_0x137a800, L_0x137a960, C4<0>, C4<0>; +L_0x137a6f0 .delay 1 (30000,30000,30000) L_0x137a6f0/d; +L_0x137aae0/d .functor OR 1, L_0x137ab50, L_0x137ad00, C4<0>, C4<0>; +L_0x137aae0 .delay 1 (30000,30000,30000) L_0x137aae0/d; +v0x11cf1b0_0 .net *"_s0", 0 0, L_0x137a2a0; 1 drivers +v0x11cf2b0_0 .net *"_s10", 0 0, L_0x137a800; 1 drivers +v0x11cf390_0 .net *"_s12", 0 0, L_0x137a960; 1 drivers +v0x11cf450_0 .net *"_s14", 0 0, L_0x137ab50; 1 drivers +v0x11cf530_0 .net *"_s16", 0 0, L_0x137ad00; 1 drivers +v0x11cf660_0 .net *"_s3", 0 0, L_0x137a360; 1 drivers +v0x11cf740_0 .net *"_s5", 0 0, L_0x137a4c0; 1 drivers +v0x11cf820_0 .net *"_s6", 0 0, L_0x137a6f0; 1 drivers +v0x11cf900_0 .net "in", 3 0, L_0x137adf0; 1 drivers +v0x11cfa70_0 .net "ors", 1 0, L_0x137a600; 1 drivers +v0x11cfb50_0 .net "out", 0 0, L_0x137aae0; 1 drivers +L_0x137a360 .part L_0x137adf0, 0, 1; +L_0x137a4c0 .part L_0x137adf0, 1, 1; +L_0x137a600 .concat8 [ 1 1 0 0], L_0x137a2a0, L_0x137a6f0; +L_0x137a800 .part L_0x137adf0, 2, 1; +L_0x137a960 .part L_0x137adf0, 3, 1; +L_0x137ab50 .part L_0x137a600, 0, 1; +L_0x137ad00 .part L_0x137a600, 1, 1; +S_0x11cfc70 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11ceda0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x137af20/d .functor OR 1, L_0x137af90, L_0x137b0f0, C4<0>, C4<0>; +L_0x137af20 .delay 1 (30000,30000,30000) L_0x137af20/d; +L_0x137b320/d .functor OR 1, L_0x137b430, L_0x137b590, C4<0>, C4<0>; +L_0x137b320 .delay 1 (30000,30000,30000) L_0x137b320/d; +L_0x137b710/d .functor OR 1, L_0x137b780, L_0x137b930, C4<0>, C4<0>; +L_0x137b710 .delay 1 (30000,30000,30000) L_0x137b710/d; +v0x11cfe30_0 .net *"_s0", 0 0, L_0x137af20; 1 drivers +v0x11cff30_0 .net *"_s10", 0 0, L_0x137b430; 1 drivers +v0x11d0010_0 .net *"_s12", 0 0, L_0x137b590; 1 drivers +v0x11d00d0_0 .net *"_s14", 0 0, L_0x137b780; 1 drivers +v0x11d01b0_0 .net *"_s16", 0 0, L_0x137b930; 1 drivers +v0x11d02e0_0 .net *"_s3", 0 0, L_0x137af90; 1 drivers +v0x11d03c0_0 .net *"_s5", 0 0, L_0x137b0f0; 1 drivers +v0x11d04a0_0 .net *"_s6", 0 0, L_0x137b320; 1 drivers +v0x11d0580_0 .net "in", 3 0, L_0x137bb60; 1 drivers +v0x11d06f0_0 .net "ors", 1 0, L_0x137b230; 1 drivers +v0x11d07d0_0 .net "out", 0 0, L_0x137b710; 1 drivers +L_0x137af90 .part L_0x137bb60, 0, 1; +L_0x137b0f0 .part L_0x137bb60, 1, 1; +L_0x137b230 .concat8 [ 1 1 0 0], L_0x137af20, L_0x137b320; +L_0x137b430 .part L_0x137bb60, 2, 1; +L_0x137b590 .part L_0x137bb60, 3, 1; +L_0x137b780 .part L_0x137b230, 0, 1; +L_0x137b930 .part L_0x137b230, 1, 1; +S_0x11d10e0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11ca210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11d6510_0 .net "ands", 7 0, L_0x13761c0; 1 drivers +v0x11d6620_0 .net "in", 7 0, L_0x1374130; alias, 1 drivers +v0x11d66e0_0 .net "out", 0 0, L_0x13781c0; alias, 1 drivers +v0x11d67b0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11d1330 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11d10e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11d3a70_0 .net "A", 7 0, L_0x1374130; alias, 1 drivers +v0x11d3b70_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11d3c30_0 .net *"_s0", 0 0, L_0x13749b0; 1 drivers +v0x11d3cf0_0 .net *"_s12", 0 0, L_0x1375370; 1 drivers +v0x11d3dd0_0 .net *"_s16", 0 0, L_0x13756d0; 1 drivers +v0x11d3f00_0 .net *"_s20", 0 0, L_0x1375b00; 1 drivers +v0x11d3fe0_0 .net *"_s24", 0 0, L_0x1375e30; 1 drivers +v0x11d40c0_0 .net *"_s28", 0 0, L_0x1375dc0; 1 drivers +v0x11d41a0_0 .net *"_s4", 0 0, L_0x1374d50; 1 drivers +v0x11d4310_0 .net *"_s8", 0 0, L_0x1375060; 1 drivers +v0x11d43f0_0 .net "out", 7 0, L_0x13761c0; alias, 1 drivers +L_0x1374ac0 .part L_0x1374130, 0, 1; +L_0x1374cb0 .part v0x127a150_0, 0, 1; +L_0x1374e10 .part L_0x1374130, 1, 1; +L_0x1374f70 .part v0x127a150_0, 1, 1; +L_0x1375120 .part L_0x1374130, 2, 1; +L_0x1375280 .part v0x127a150_0, 2, 1; +L_0x1375430 .part L_0x1374130, 3, 1; +L_0x1375590 .part v0x127a150_0, 3, 1; +L_0x1375790 .part L_0x1374130, 4, 1; +L_0x1375a00 .part v0x127a150_0, 4, 1; +L_0x1375b70 .part L_0x1374130, 5, 1; +L_0x1375cd0 .part v0x127a150_0, 5, 1; +L_0x1375ef0 .part L_0x1374130, 6, 1; +L_0x1376050 .part v0x127a150_0, 6, 1; +LS_0x13761c0_0_0 .concat8 [ 1 1 1 1], L_0x13749b0, L_0x1374d50, L_0x1375060, L_0x1375370; +LS_0x13761c0_0_4 .concat8 [ 1 1 1 1], L_0x13756d0, L_0x1375b00, L_0x1375e30, L_0x1375dc0; +L_0x13761c0 .concat8 [ 4 4 0 0], LS_0x13761c0_0_0, LS_0x13761c0_0_4; +L_0x1376580 .part L_0x1374130, 7, 1; +L_0x1376770 .part v0x127a150_0, 7, 1; +S_0x11d1570 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d1780 .param/l "i" 0 4 54, +C4<00>; +L_0x13749b0/d .functor AND 1, L_0x1374ac0, L_0x1374cb0, C4<1>, C4<1>; +L_0x13749b0 .delay 1 (30000,30000,30000) L_0x13749b0/d; +v0x11d1860_0 .net *"_s0", 0 0, L_0x1374ac0; 1 drivers +v0x11d1940_0 .net *"_s1", 0 0, L_0x1374cb0; 1 drivers +S_0x11d1a20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d1c30 .param/l "i" 0 4 54, +C4<01>; +L_0x1374d50/d .functor AND 1, L_0x1374e10, L_0x1374f70, C4<1>, C4<1>; +L_0x1374d50 .delay 1 (30000,30000,30000) L_0x1374d50/d; +v0x11d1cf0_0 .net *"_s0", 0 0, L_0x1374e10; 1 drivers +v0x11d1dd0_0 .net *"_s1", 0 0, L_0x1374f70; 1 drivers +S_0x11d1eb0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d20f0 .param/l "i" 0 4 54, +C4<010>; +L_0x1375060/d .functor AND 1, L_0x1375120, L_0x1375280, C4<1>, C4<1>; +L_0x1375060 .delay 1 (30000,30000,30000) L_0x1375060/d; +v0x11d2190_0 .net *"_s0", 0 0, L_0x1375120; 1 drivers +v0x11d2270_0 .net *"_s1", 0 0, L_0x1375280; 1 drivers +S_0x11d2350 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d2560 .param/l "i" 0 4 54, +C4<011>; +L_0x1375370/d .functor AND 1, L_0x1375430, L_0x1375590, C4<1>, C4<1>; +L_0x1375370 .delay 1 (30000,30000,30000) L_0x1375370/d; +v0x11d2620_0 .net *"_s0", 0 0, L_0x1375430; 1 drivers +v0x11d2700_0 .net *"_s1", 0 0, L_0x1375590; 1 drivers +S_0x11d27e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d2a40 .param/l "i" 0 4 54, +C4<0100>; +L_0x13756d0/d .functor AND 1, L_0x1375790, L_0x1375a00, C4<1>, C4<1>; +L_0x13756d0 .delay 1 (30000,30000,30000) L_0x13756d0/d; +v0x11d2b00_0 .net *"_s0", 0 0, L_0x1375790; 1 drivers +v0x11d2be0_0 .net *"_s1", 0 0, L_0x1375a00; 1 drivers +S_0x11d2cc0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d2ed0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1375b00/d .functor AND 1, L_0x1375b70, L_0x1375cd0, C4<1>, C4<1>; +L_0x1375b00 .delay 1 (30000,30000,30000) L_0x1375b00/d; +v0x11d2f90_0 .net *"_s0", 0 0, L_0x1375b70; 1 drivers +v0x11d3070_0 .net *"_s1", 0 0, L_0x1375cd0; 1 drivers +S_0x11d3150 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d3360 .param/l "i" 0 4 54, +C4<0110>; +L_0x1375e30/d .functor AND 1, L_0x1375ef0, L_0x1376050, C4<1>, C4<1>; +L_0x1375e30 .delay 1 (30000,30000,30000) L_0x1375e30/d; +v0x11d3420_0 .net *"_s0", 0 0, L_0x1375ef0; 1 drivers +v0x11d3500_0 .net *"_s1", 0 0, L_0x1376050; 1 drivers +S_0x11d35e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11d1330; + .timescale -9 -12; +P_0x11d37f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1375dc0/d .functor AND 1, L_0x1376580, L_0x1376770, C4<1>, C4<1>; +L_0x1375dc0 .delay 1 (30000,30000,30000) L_0x1375dc0/d; +v0x11d38b0_0 .net *"_s0", 0 0, L_0x1376580; 1 drivers +v0x11d3990_0 .net *"_s1", 0 0, L_0x1376770; 1 drivers +S_0x11d4550 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11d10e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13781c0/d .functor OR 1, L_0x1378280, L_0x1378430, C4<0>, C4<0>; +L_0x13781c0 .delay 1 (30000,30000,30000) L_0x13781c0/d; +v0x11d60a0_0 .net *"_s10", 0 0, L_0x1378280; 1 drivers +v0x11d6180_0 .net *"_s12", 0 0, L_0x1378430; 1 drivers +v0x11d6260_0 .net "in", 7 0, L_0x13761c0; alias, 1 drivers +v0x11d6330_0 .net "ors", 1 0, L_0x1377fe0; 1 drivers +v0x11d63f0_0 .net "out", 0 0, L_0x13781c0; alias, 1 drivers +L_0x13773b0 .part L_0x13761c0, 0, 4; +L_0x1377fe0 .concat8 [ 1 1 0 0], L_0x13770a0, L_0x1377cd0; +L_0x1378120 .part L_0x13761c0, 4, 4; +L_0x1378280 .part L_0x1377fe0, 0, 1; +L_0x1378430 .part L_0x1377fe0, 1, 1; +S_0x11d4710 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11d4550; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1376860/d .functor OR 1, L_0x1376920, L_0x1376a80, C4<0>, C4<0>; +L_0x1376860 .delay 1 (30000,30000,30000) L_0x1376860/d; +L_0x1376cb0/d .functor OR 1, L_0x1376dc0, L_0x1376f20, C4<0>, C4<0>; +L_0x1376cb0 .delay 1 (30000,30000,30000) L_0x1376cb0/d; +L_0x13770a0/d .functor OR 1, L_0x1377110, L_0x13772c0, C4<0>, C4<0>; +L_0x13770a0 .delay 1 (30000,30000,30000) L_0x13770a0/d; +v0x11d4960_0 .net *"_s0", 0 0, L_0x1376860; 1 drivers +v0x11d4a60_0 .net *"_s10", 0 0, L_0x1376dc0; 1 drivers +v0x11d4b40_0 .net *"_s12", 0 0, L_0x1376f20; 1 drivers +v0x11d4c00_0 .net *"_s14", 0 0, L_0x1377110; 1 drivers +v0x11d4ce0_0 .net *"_s16", 0 0, L_0x13772c0; 1 drivers +v0x11d4e10_0 .net *"_s3", 0 0, L_0x1376920; 1 drivers +v0x11d4ef0_0 .net *"_s5", 0 0, L_0x1376a80; 1 drivers +v0x11d4fd0_0 .net *"_s6", 0 0, L_0x1376cb0; 1 drivers +v0x11d50b0_0 .net "in", 3 0, L_0x13773b0; 1 drivers +v0x11d5220_0 .net "ors", 1 0, L_0x1376bc0; 1 drivers +v0x11d5300_0 .net "out", 0 0, L_0x13770a0; 1 drivers +L_0x1376920 .part L_0x13773b0, 0, 1; +L_0x1376a80 .part L_0x13773b0, 1, 1; +L_0x1376bc0 .concat8 [ 1 1 0 0], L_0x1376860, L_0x1376cb0; +L_0x1376dc0 .part L_0x13773b0, 2, 1; +L_0x1376f20 .part L_0x13773b0, 3, 1; +L_0x1377110 .part L_0x1376bc0, 0, 1; +L_0x13772c0 .part L_0x1376bc0, 1, 1; +S_0x11d5420 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11d4550; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13774e0/d .functor OR 1, L_0x1377550, L_0x13776b0, C4<0>, C4<0>; +L_0x13774e0 .delay 1 (30000,30000,30000) L_0x13774e0/d; +L_0x13778e0/d .functor OR 1, L_0x13779f0, L_0x1377b50, C4<0>, C4<0>; +L_0x13778e0 .delay 1 (30000,30000,30000) L_0x13778e0/d; +L_0x1377cd0/d .functor OR 1, L_0x1377d40, L_0x1377ef0, C4<0>, C4<0>; +L_0x1377cd0 .delay 1 (30000,30000,30000) L_0x1377cd0/d; +v0x11d55e0_0 .net *"_s0", 0 0, L_0x13774e0; 1 drivers +v0x11d56e0_0 .net *"_s10", 0 0, L_0x13779f0; 1 drivers +v0x11d57c0_0 .net *"_s12", 0 0, L_0x1377b50; 1 drivers +v0x11d5880_0 .net *"_s14", 0 0, L_0x1377d40; 1 drivers +v0x11d5960_0 .net *"_s16", 0 0, L_0x1377ef0; 1 drivers +v0x11d5a90_0 .net *"_s3", 0 0, L_0x1377550; 1 drivers +v0x11d5b70_0 .net *"_s5", 0 0, L_0x13776b0; 1 drivers +v0x11d5c50_0 .net *"_s6", 0 0, L_0x13778e0; 1 drivers +v0x11d5d30_0 .net "in", 3 0, L_0x1378120; 1 drivers +v0x11d5ea0_0 .net "ors", 1 0, L_0x13777f0; 1 drivers +v0x11d5f80_0 .net "out", 0 0, L_0x1377cd0; 1 drivers +L_0x1377550 .part L_0x1378120, 0, 1; +L_0x13776b0 .part L_0x1378120, 1, 1; +L_0x13777f0 .concat8 [ 1 1 0 0], L_0x13774e0, L_0x13778e0; +L_0x13779f0 .part L_0x1378120, 2, 1; +L_0x1377b50 .part L_0x1378120, 3, 1; +L_0x1377d40 .part L_0x13777f0, 0, 1; +L_0x1377ef0 .part L_0x13777f0, 1, 1; +S_0x11d6890 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11ca210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1372f70/d .functor XNOR 1, L_0x137c060, L_0x1371a30, C4<0>, C4<0>; +L_0x1372f70 .delay 1 (20000,20000,20000) L_0x1372f70/d; +L_0x13730f0/d .functor AND 1, L_0x137c060, L_0x1371d00, C4<1>, C4<1>; +L_0x13730f0 .delay 1 (30000,30000,30000) L_0x13730f0/d; +L_0x1373250/d .functor AND 1, L_0x1372f70, L_0x1371ad0, C4<1>, C4<1>; +L_0x1373250 .delay 1 (30000,30000,30000) L_0x1373250/d; +L_0x1373360/d .functor OR 1, L_0x1373250, L_0x13730f0, C4<0>, C4<0>; +L_0x1373360 .delay 1 (30000,30000,30000) L_0x1373360/d; +v0x11d6b40_0 .net "a", 0 0, L_0x137c060; alias, 1 drivers +v0x11d6c30_0 .net "a_", 0 0, L_0x13673d0; alias, 1 drivers +v0x11d6cf0_0 .net "b", 0 0, L_0x1371a30; alias, 1 drivers +v0x11d6de0_0 .net "b_", 0 0, L_0x1371d00; alias, 1 drivers +v0x11d6e80_0 .net "carryin", 0 0, L_0x1371ad0; alias, 1 drivers +v0x11d6fc0_0 .net "eq", 0 0, L_0x1372f70; 1 drivers +v0x11d7080_0 .net "lt", 0 0, L_0x13730f0; 1 drivers +v0x11d7140_0 .net "out", 0 0, L_0x1373360; 1 drivers +v0x11d7200_0 .net "w0", 0 0, L_0x1373250; 1 drivers +S_0x11d7450 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11ca210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1372b50/d .functor OR 1, L_0x13726a0, L_0x11d86b0, C4<0>, C4<0>; +L_0x1372b50 .delay 1 (30000,30000,30000) L_0x1372b50/d; +v0x11d8240_0 .net "a", 0 0, L_0x137c060; alias, 1 drivers +v0x11d8390_0 .net "b", 0 0, L_0x1371d00; alias, 1 drivers +v0x11d8450_0 .net "c1", 0 0, L_0x13726a0; 1 drivers +v0x11d84f0_0 .net "c2", 0 0, L_0x11d86b0; 1 drivers +v0x11d85c0_0 .net "carryin", 0 0, L_0x1371ad0; alias, 1 drivers +v0x11d8740_0 .net "carryout", 0 0, L_0x1372b50; 1 drivers +v0x11d87e0_0 .net "s1", 0 0, L_0x13725e0; 1 drivers +v0x11d8880_0 .net "sum", 0 0, L_0x1372800; 1 drivers +S_0x11d76a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11d7450; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13725e0/d .functor XOR 1, L_0x137c060, L_0x1371d00, C4<0>, C4<0>; +L_0x13725e0 .delay 1 (30000,30000,30000) L_0x13725e0/d; +L_0x13726a0/d .functor AND 1, L_0x137c060, L_0x1371d00, C4<1>, C4<1>; +L_0x13726a0 .delay 1 (30000,30000,30000) L_0x13726a0/d; +v0x11d7900_0 .net "a", 0 0, L_0x137c060; alias, 1 drivers +v0x11d79c0_0 .net "b", 0 0, L_0x1371d00; alias, 1 drivers +v0x11d7a80_0 .net "carryout", 0 0, L_0x13726a0; alias, 1 drivers +v0x11d7b20_0 .net "sum", 0 0, L_0x13725e0; alias, 1 drivers +S_0x11d7c50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11d7450; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1372800/d .functor XOR 1, L_0x13725e0, L_0x1371ad0, C4<0>, C4<0>; +L_0x1372800 .delay 1 (30000,30000,30000) L_0x1372800/d; +L_0x11d86b0/d .functor AND 1, L_0x13725e0, L_0x1371ad0, C4<1>, C4<1>; +L_0x11d86b0 .delay 1 (30000,30000,30000) L_0x11d86b0/d; +v0x11d7eb0_0 .net "a", 0 0, L_0x13725e0; alias, 1 drivers +v0x11d7f80_0 .net "b", 0 0, L_0x1371ad0; alias, 1 drivers +v0x11d8020_0 .net "carryout", 0 0, L_0x11d86b0; alias, 1 drivers +v0x11d80f0_0 .net "sum", 0 0, L_0x1372800; alias, 1 drivers +S_0x11da910 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11c9f40; + .timescale -9 -12; +L_0x2ac432888d78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888dc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1372160/d .functor OR 1, L_0x2ac432888d78, L_0x2ac432888dc0, C4<0>, C4<0>; +L_0x1372160 .delay 1 (30000,30000,30000) L_0x1372160/d; +v0x11dab00_0 .net/2u *"_s0", 0 0, L_0x2ac432888d78; 1 drivers +v0x11dabe0_0 .net/2u *"_s2", 0 0, L_0x2ac432888dc0; 1 drivers +S_0x11dacc0 .scope generate, "alu_slices[24]" "alu_slices[24]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11daed0 .param/l "i" 0 3 39, +C4<011000>; +S_0x11daf90 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11dacc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x137c410/d .functor NOT 1, L_0x13868a0, C4<0>, C4<0>, C4<0>; +L_0x137c410 .delay 1 (10000,10000,10000) L_0x137c410/d; +L_0x137c520/d .functor NOT 1, L_0x1386a00, C4<0>, C4<0>, C4<0>; +L_0x137c520 .delay 1 (10000,10000,10000) L_0x137c520/d; +L_0x137d570/d .functor XOR 1, L_0x13868a0, L_0x1386a00, C4<0>, C4<0>; +L_0x137d570 .delay 1 (30000,30000,30000) L_0x137d570/d; +L_0x2ac432888e08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888e50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137d630/d .functor OR 1, L_0x2ac432888e08, L_0x2ac432888e50, C4<0>, C4<0>; +L_0x137d630 .delay 1 (30000,30000,30000) L_0x137d630/d; +L_0x2ac432888e98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888ee0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137ddd0/d .functor OR 1, L_0x2ac432888e98, L_0x2ac432888ee0, C4<0>, C4<0>; +L_0x137ddd0 .delay 1 (30000,30000,30000) L_0x137ddd0/d; +L_0x137dfd0/d .functor AND 1, L_0x13868a0, L_0x1386a00, C4<1>, C4<1>; +L_0x137dfd0 .delay 1 (30000,30000,30000) L_0x137dfd0/d; +L_0x2ac432888f28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432888f70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137e090/d .functor OR 1, L_0x2ac432888f28, L_0x2ac432888f70, C4<0>, C4<0>; +L_0x137e090 .delay 1 (30000,30000,30000) L_0x137e090/d; +L_0x137e290/d .functor NAND 1, L_0x13868a0, L_0x1386a00, C4<1>, C4<1>; +L_0x137e290 .delay 1 (20000,20000,20000) L_0x137e290/d; +L_0x2ac432888fb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889000 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137e3a0/d .functor OR 1, L_0x2ac432888fb8, L_0x2ac432889000, C4<0>, C4<0>; +L_0x137e3a0 .delay 1 (30000,30000,30000) L_0x137e3a0/d; +L_0x137e550/d .functor NOR 1, L_0x13868a0, L_0x1386a00, C4<0>, C4<0>; +L_0x137e550 .delay 1 (20000,20000,20000) L_0x137e550/d; +L_0x2ac432889048 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889090 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137c9d0/d .functor OR 1, L_0x2ac432889048, L_0x2ac432889090, C4<0>, C4<0>; +L_0x137c9d0 .delay 1 (30000,30000,30000) L_0x137c9d0/d; +L_0x137ebb0/d .functor OR 1, L_0x13868a0, L_0x1386a00, C4<0>, C4<0>; +L_0x137ebb0 .delay 1 (30000,30000,30000) L_0x137ebb0/d; +L_0x2ac4328890d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889120 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137f0a0/d .functor OR 1, L_0x2ac4328890d8, L_0x2ac432889120, C4<0>, C4<0>; +L_0x137f0a0 .delay 1 (30000,30000,30000) L_0x137f0a0/d; +L_0x13867a0/d .functor NOT 1, L_0x1382a00, C4<0>, C4<0>, C4<0>; +L_0x13867a0 .delay 1 (10000,10000,10000) L_0x13867a0/d; +v0x11e96c0_0 .net "A", 0 0, L_0x13868a0; 1 drivers +v0x11e9780_0 .net "A_", 0 0, L_0x137c410; 1 drivers +v0x11e9840_0 .net "B", 0 0, L_0x1386a00; 1 drivers +v0x11e9910_0 .net "B_", 0 0, L_0x137c520; 1 drivers +v0x11e99b0_0 .net *"_s11", 0 0, L_0x137d630; 1 drivers +v0x11e9aa0_0 .net/2s *"_s13", 0 0, L_0x2ac432888e08; 1 drivers +v0x11e9b60_0 .net/2s *"_s15", 0 0, L_0x2ac432888e50; 1 drivers +v0x11e9c40_0 .net *"_s19", 0 0, L_0x137ddd0; 1 drivers +v0x11e9d20_0 .net/2s *"_s21", 0 0, L_0x2ac432888e98; 1 drivers +v0x11e9e90_0 .net/2s *"_s23", 0 0, L_0x2ac432888ee0; 1 drivers +v0x11e9f70_0 .net *"_s25", 0 0, L_0x137dfd0; 1 drivers +v0x11ea050_0 .net *"_s28", 0 0, L_0x137e090; 1 drivers +v0x11ea130_0 .net/2s *"_s30", 0 0, L_0x2ac432888f28; 1 drivers +v0x11ea210_0 .net/2s *"_s32", 0 0, L_0x2ac432888f70; 1 drivers +v0x11ea2f0_0 .net *"_s34", 0 0, L_0x137e290; 1 drivers +v0x11ea3d0_0 .net *"_s37", 0 0, L_0x137e3a0; 1 drivers +v0x11ea4b0_0 .net/2s *"_s39", 0 0, L_0x2ac432888fb8; 1 drivers +v0x11ea660_0 .net/2s *"_s41", 0 0, L_0x2ac432889000; 1 drivers +v0x11ea700_0 .net *"_s43", 0 0, L_0x137e550; 1 drivers +v0x11ea7e0_0 .net *"_s46", 0 0, L_0x137c9d0; 1 drivers +v0x11ea8c0_0 .net/2s *"_s48", 0 0, L_0x2ac432889048; 1 drivers +v0x11ea9a0_0 .net/2s *"_s50", 0 0, L_0x2ac432889090; 1 drivers +v0x11eaa80_0 .net *"_s52", 0 0, L_0x137ebb0; 1 drivers +v0x11eab60_0 .net *"_s56", 0 0, L_0x137f0a0; 1 drivers +v0x11eac40_0 .net/2s *"_s59", 0 0, L_0x2ac4328890d8; 1 drivers +v0x11ead20_0 .net/2s *"_s61", 0 0, L_0x2ac432889120; 1 drivers +v0x11eae00_0 .net *"_s8", 0 0, L_0x137d570; 1 drivers +v0x11eaee0_0 .net "carryin", 0 0, L_0x137c1c0; 1 drivers +v0x11eaf80_0 .net "carryout", 0 0, L_0x1386440; 1 drivers +v0x11eb020_0 .net "carryouts", 7 0, L_0x137ed30; 1 drivers +v0x11eb130_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11eb1f0_0 .net "result", 0 0, L_0x1382a00; 1 drivers +v0x11eb2e0_0 .net "results", 7 0, L_0x137e980; 1 drivers +v0x11ea5c0_0 .net "zero", 0 0, L_0x13867a0; 1 drivers +LS_0x137e980_0_0 .concat8 [ 1 1 1 1], L_0x137ca40, L_0x137d070, L_0x137d570, L_0x137ddd0; +LS_0x137e980_0_4 .concat8 [ 1 1 1 1], L_0x137dfd0, L_0x137e290, L_0x137e550, L_0x137ebb0; +L_0x137e980 .concat8 [ 4 4 0 0], LS_0x137e980_0_0, LS_0x137e980_0_4; +LS_0x137ed30_0_0 .concat8 [ 1 1 1 1], L_0x137ccf0, L_0x137d410, L_0x137d630, L_0x137dc20; +LS_0x137ed30_0_4 .concat8 [ 1 1 1 1], L_0x137e090, L_0x137e3a0, L_0x137c9d0, L_0x137f0a0; +L_0x137ed30 .concat8 [ 4 4 0 0], LS_0x137ed30_0_0, LS_0x137ed30_0_4; +S_0x11db210 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11daf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x137ccf0/d .functor OR 1, L_0x137c7d0, L_0x137cb90, C4<0>, C4<0>; +L_0x137ccf0 .delay 1 (30000,30000,30000) L_0x137ccf0/d; +v0x11dc040_0 .net "a", 0 0, L_0x13868a0; alias, 1 drivers +v0x11dc100_0 .net "b", 0 0, L_0x1386a00; alias, 1 drivers +v0x11dc1d0_0 .net "c1", 0 0, L_0x137c7d0; 1 drivers +v0x11dc2d0_0 .net "c2", 0 0, L_0x137cb90; 1 drivers +v0x11dc3a0_0 .net "carryin", 0 0, L_0x137c1c0; alias, 1 drivers +v0x11dc490_0 .net "carryout", 0 0, L_0x137ccf0; 1 drivers +v0x11dc530_0 .net "s1", 0 0, L_0x137c710; 1 drivers +v0x11dc620_0 .net "sum", 0 0, L_0x137ca40; 1 drivers +S_0x11db480 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11db210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x137c710/d .functor XOR 1, L_0x13868a0, L_0x1386a00, C4<0>, C4<0>; +L_0x137c710 .delay 1 (30000,30000,30000) L_0x137c710/d; +L_0x137c7d0/d .functor AND 1, L_0x13868a0, L_0x1386a00, C4<1>, C4<1>; +L_0x137c7d0 .delay 1 (30000,30000,30000) L_0x137c7d0/d; +v0x11db6e0_0 .net "a", 0 0, L_0x13868a0; alias, 1 drivers +v0x11db7c0_0 .net "b", 0 0, L_0x1386a00; alias, 1 drivers +v0x11db880_0 .net "carryout", 0 0, L_0x137c7d0; alias, 1 drivers +v0x11db920_0 .net "sum", 0 0, L_0x137c710; alias, 1 drivers +S_0x11dba60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11db210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x137ca40/d .functor XOR 1, L_0x137c710, L_0x137c1c0, C4<0>, C4<0>; +L_0x137ca40 .delay 1 (30000,30000,30000) L_0x137ca40/d; +L_0x137cb90/d .functor AND 1, L_0x137c710, L_0x137c1c0, C4<1>, C4<1>; +L_0x137cb90 .delay 1 (30000,30000,30000) L_0x137cb90/d; +v0x11dbcc0_0 .net "a", 0 0, L_0x137c710; alias, 1 drivers +v0x11dbd60_0 .net "b", 0 0, L_0x137c1c0; alias, 1 drivers +v0x11dbe00_0 .net "carryout", 0 0, L_0x137cb90; alias, 1 drivers +v0x11dbed0_0 .net "sum", 0 0, L_0x137ca40; alias, 1 drivers +S_0x11dc6f0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11daf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11e1ae0_0 .net "ands", 7 0, L_0x1384440; 1 drivers +v0x11e1bf0_0 .net "in", 7 0, L_0x137ed30; alias, 1 drivers +v0x11e1cb0_0 .net "out", 0 0, L_0x1386440; alias, 1 drivers +v0x11e1d80_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11dc910 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11dc6f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11df040_0 .net "A", 7 0, L_0x137ed30; alias, 1 drivers +v0x11df140_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11df200_0 .net *"_s0", 0 0, L_0x1382d60; 1 drivers +v0x11df2c0_0 .net *"_s12", 0 0, L_0x13836d0; 1 drivers +v0x11df3a0_0 .net *"_s16", 0 0, L_0x1383a30; 1 drivers +v0x11df4d0_0 .net *"_s20", 0 0, L_0x1383e00; 1 drivers +v0x11df5b0_0 .net *"_s24", 0 0, L_0x1384130; 1 drivers +v0x11df690_0 .net *"_s28", 0 0, L_0x13840c0; 1 drivers +v0x11df770_0 .net *"_s4", 0 0, L_0x13830b0; 1 drivers +v0x11df8e0_0 .net *"_s8", 0 0, L_0x13833c0; 1 drivers +v0x11df9c0_0 .net "out", 7 0, L_0x1384440; alias, 1 drivers +L_0x1382e20 .part L_0x137ed30, 0, 1; +L_0x1383010 .part v0x127a150_0, 0, 1; +L_0x1383170 .part L_0x137ed30, 1, 1; +L_0x13832d0 .part v0x127a150_0, 1, 1; +L_0x1383480 .part L_0x137ed30, 2, 1; +L_0x13835e0 .part v0x127a150_0, 2, 1; +L_0x1383790 .part L_0x137ed30, 3, 1; +L_0x13838f0 .part v0x127a150_0, 3, 1; +L_0x1383af0 .part L_0x137ed30, 4, 1; +L_0x1383d60 .part v0x127a150_0, 4, 1; +L_0x1383e70 .part L_0x137ed30, 5, 1; +L_0x1383fd0 .part v0x127a150_0, 5, 1; +L_0x13841f0 .part L_0x137ed30, 6, 1; +L_0x1384350 .part v0x127a150_0, 6, 1; +LS_0x1384440_0_0 .concat8 [ 1 1 1 1], L_0x1382d60, L_0x13830b0, L_0x13833c0, L_0x13836d0; +LS_0x1384440_0_4 .concat8 [ 1 1 1 1], L_0x1383a30, L_0x1383e00, L_0x1384130, L_0x13840c0; +L_0x1384440 .concat8 [ 4 4 0 0], LS_0x1384440_0_0, LS_0x1384440_0_4; +L_0x1384800 .part L_0x137ed30, 7, 1; +L_0x13849f0 .part v0x127a150_0, 7, 1; +S_0x11dcb70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11dcd80 .param/l "i" 0 4 54, +C4<00>; +L_0x1382d60/d .functor AND 1, L_0x1382e20, L_0x1383010, C4<1>, C4<1>; +L_0x1382d60 .delay 1 (30000,30000,30000) L_0x1382d60/d; +v0x11dce60_0 .net *"_s0", 0 0, L_0x1382e20; 1 drivers +v0x11dcf40_0 .net *"_s1", 0 0, L_0x1383010; 1 drivers +S_0x11dd020 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11dd230 .param/l "i" 0 4 54, +C4<01>; +L_0x13830b0/d .functor AND 1, L_0x1383170, L_0x13832d0, C4<1>, C4<1>; +L_0x13830b0 .delay 1 (30000,30000,30000) L_0x13830b0/d; +v0x11dd2f0_0 .net *"_s0", 0 0, L_0x1383170; 1 drivers +v0x11dd3d0_0 .net *"_s1", 0 0, L_0x13832d0; 1 drivers +S_0x11dd4b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11dd6c0 .param/l "i" 0 4 54, +C4<010>; +L_0x13833c0/d .functor AND 1, L_0x1383480, L_0x13835e0, C4<1>, C4<1>; +L_0x13833c0 .delay 1 (30000,30000,30000) L_0x13833c0/d; +v0x11dd760_0 .net *"_s0", 0 0, L_0x1383480; 1 drivers +v0x11dd840_0 .net *"_s1", 0 0, L_0x13835e0; 1 drivers +S_0x11dd920 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11ddb30 .param/l "i" 0 4 54, +C4<011>; +L_0x13836d0/d .functor AND 1, L_0x1383790, L_0x13838f0, C4<1>, C4<1>; +L_0x13836d0 .delay 1 (30000,30000,30000) L_0x13836d0/d; +v0x11ddbf0_0 .net *"_s0", 0 0, L_0x1383790; 1 drivers +v0x11ddcd0_0 .net *"_s1", 0 0, L_0x13838f0; 1 drivers +S_0x11dddb0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11de010 .param/l "i" 0 4 54, +C4<0100>; +L_0x1383a30/d .functor AND 1, L_0x1383af0, L_0x1383d60, C4<1>, C4<1>; +L_0x1383a30 .delay 1 (30000,30000,30000) L_0x1383a30/d; +v0x11de0d0_0 .net *"_s0", 0 0, L_0x1383af0; 1 drivers +v0x11de1b0_0 .net *"_s1", 0 0, L_0x1383d60; 1 drivers +S_0x11de290 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11de4a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1383e00/d .functor AND 1, L_0x1383e70, L_0x1383fd0, C4<1>, C4<1>; +L_0x1383e00 .delay 1 (30000,30000,30000) L_0x1383e00/d; +v0x11de560_0 .net *"_s0", 0 0, L_0x1383e70; 1 drivers +v0x11de640_0 .net *"_s1", 0 0, L_0x1383fd0; 1 drivers +S_0x11de720 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11de930 .param/l "i" 0 4 54, +C4<0110>; +L_0x1384130/d .functor AND 1, L_0x13841f0, L_0x1384350, C4<1>, C4<1>; +L_0x1384130 .delay 1 (30000,30000,30000) L_0x1384130/d; +v0x11de9f0_0 .net *"_s0", 0 0, L_0x13841f0; 1 drivers +v0x11dead0_0 .net *"_s1", 0 0, L_0x1384350; 1 drivers +S_0x11debb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11dc910; + .timescale -9 -12; +P_0x11dedc0 .param/l "i" 0 4 54, +C4<0111>; +L_0x13840c0/d .functor AND 1, L_0x1384800, L_0x13849f0, C4<1>, C4<1>; +L_0x13840c0 .delay 1 (30000,30000,30000) L_0x13840c0/d; +v0x11dee80_0 .net *"_s0", 0 0, L_0x1384800; 1 drivers +v0x11def60_0 .net *"_s1", 0 0, L_0x13849f0; 1 drivers +S_0x11dfb20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11dc6f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1386440/d .functor OR 1, L_0x1386500, L_0x13866b0, C4<0>, C4<0>; +L_0x1386440 .delay 1 (30000,30000,30000) L_0x1386440/d; +v0x11e1670_0 .net *"_s10", 0 0, L_0x1386500; 1 drivers +v0x11e1750_0 .net *"_s12", 0 0, L_0x13866b0; 1 drivers +v0x11e1830_0 .net "in", 7 0, L_0x1384440; alias, 1 drivers +v0x11e1900_0 .net "ors", 1 0, L_0x1386260; 1 drivers +v0x11e19c0_0 .net "out", 0 0, L_0x1386440; alias, 1 drivers +L_0x1385630 .part L_0x1384440, 0, 4; +L_0x1386260 .concat8 [ 1 1 0 0], L_0x1385320, L_0x1385f50; +L_0x13863a0 .part L_0x1384440, 4, 4; +L_0x1386500 .part L_0x1386260, 0, 1; +L_0x13866b0 .part L_0x1386260, 1, 1; +S_0x11dfce0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1384ae0/d .functor OR 1, L_0x1384ba0, L_0x1384d00, C4<0>, C4<0>; +L_0x1384ae0 .delay 1 (30000,30000,30000) L_0x1384ae0/d; +L_0x1384f30/d .functor OR 1, L_0x1385040, L_0x13851a0, C4<0>, C4<0>; +L_0x1384f30 .delay 1 (30000,30000,30000) L_0x1384f30/d; +L_0x1385320/d .functor OR 1, L_0x1385390, L_0x1385540, C4<0>, C4<0>; +L_0x1385320 .delay 1 (30000,30000,30000) L_0x1385320/d; +v0x11dff30_0 .net *"_s0", 0 0, L_0x1384ae0; 1 drivers +v0x11e0030_0 .net *"_s10", 0 0, L_0x1385040; 1 drivers +v0x11e0110_0 .net *"_s12", 0 0, L_0x13851a0; 1 drivers +v0x11e01d0_0 .net *"_s14", 0 0, L_0x1385390; 1 drivers +v0x11e02b0_0 .net *"_s16", 0 0, L_0x1385540; 1 drivers +v0x11e03e0_0 .net *"_s3", 0 0, L_0x1384ba0; 1 drivers +v0x11e04c0_0 .net *"_s5", 0 0, L_0x1384d00; 1 drivers +v0x11e05a0_0 .net *"_s6", 0 0, L_0x1384f30; 1 drivers +v0x11e0680_0 .net "in", 3 0, L_0x1385630; 1 drivers +v0x11e07f0_0 .net "ors", 1 0, L_0x1384e40; 1 drivers +v0x11e08d0_0 .net "out", 0 0, L_0x1385320; 1 drivers +L_0x1384ba0 .part L_0x1385630, 0, 1; +L_0x1384d00 .part L_0x1385630, 1, 1; +L_0x1384e40 .concat8 [ 1 1 0 0], L_0x1384ae0, L_0x1384f30; +L_0x1385040 .part L_0x1385630, 2, 1; +L_0x13851a0 .part L_0x1385630, 3, 1; +L_0x1385390 .part L_0x1384e40, 0, 1; +L_0x1385540 .part L_0x1384e40, 1, 1; +S_0x11e09f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11dfb20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1385760/d .functor OR 1, L_0x13857d0, L_0x1385930, C4<0>, C4<0>; +L_0x1385760 .delay 1 (30000,30000,30000) L_0x1385760/d; +L_0x1385b60/d .functor OR 1, L_0x1385c70, L_0x1385dd0, C4<0>, C4<0>; +L_0x1385b60 .delay 1 (30000,30000,30000) L_0x1385b60/d; +L_0x1385f50/d .functor OR 1, L_0x1385fc0, L_0x1386170, C4<0>, C4<0>; +L_0x1385f50 .delay 1 (30000,30000,30000) L_0x1385f50/d; +v0x11e0bb0_0 .net *"_s0", 0 0, L_0x1385760; 1 drivers +v0x11e0cb0_0 .net *"_s10", 0 0, L_0x1385c70; 1 drivers +v0x11e0d90_0 .net *"_s12", 0 0, L_0x1385dd0; 1 drivers +v0x11e0e50_0 .net *"_s14", 0 0, L_0x1385fc0; 1 drivers +v0x11e0f30_0 .net *"_s16", 0 0, L_0x1386170; 1 drivers +v0x11e1060_0 .net *"_s3", 0 0, L_0x13857d0; 1 drivers +v0x11e1140_0 .net *"_s5", 0 0, L_0x1385930; 1 drivers +v0x11e1220_0 .net *"_s6", 0 0, L_0x1385b60; 1 drivers +v0x11e1300_0 .net "in", 3 0, L_0x13863a0; 1 drivers +v0x11e1470_0 .net "ors", 1 0, L_0x1385a70; 1 drivers +v0x11e1550_0 .net "out", 0 0, L_0x1385f50; 1 drivers +L_0x13857d0 .part L_0x13863a0, 0, 1; +L_0x1385930 .part L_0x13863a0, 1, 1; +L_0x1385a70 .concat8 [ 1 1 0 0], L_0x1385760, L_0x1385b60; +L_0x1385c70 .part L_0x13863a0, 2, 1; +L_0x1385dd0 .part L_0x13863a0, 3, 1; +L_0x1385fc0 .part L_0x1385a70, 0, 1; +L_0x1386170 .part L_0x1385a70, 1, 1; +S_0x11e1e60 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11daf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11e7290_0 .net "ands", 7 0, L_0x1380a00; 1 drivers +v0x11e73a0_0 .net "in", 7 0, L_0x137e980; alias, 1 drivers +v0x11e7460_0 .net "out", 0 0, L_0x1382a00; alias, 1 drivers +v0x11e7530_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11e20b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11e1e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11e47f0_0 .net "A", 7 0, L_0x137e980; alias, 1 drivers +v0x11e48f0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11e49b0_0 .net *"_s0", 0 0, L_0x137f250; 1 drivers +v0x11e4a70_0 .net *"_s12", 0 0, L_0x137fc10; 1 drivers +v0x11e4b50_0 .net *"_s16", 0 0, L_0x137ff70; 1 drivers +v0x11e4c80_0 .net *"_s20", 0 0, L_0x1380340; 1 drivers +v0x11e4d60_0 .net *"_s24", 0 0, L_0x1380670; 1 drivers +v0x11e4e40_0 .net *"_s28", 0 0, L_0x1380600; 1 drivers +v0x11e4f20_0 .net *"_s4", 0 0, L_0x137f5f0; 1 drivers +v0x11e5090_0 .net *"_s8", 0 0, L_0x137f900; 1 drivers +v0x11e5170_0 .net "out", 7 0, L_0x1380a00; alias, 1 drivers +L_0x137f360 .part L_0x137e980, 0, 1; +L_0x137f550 .part v0x127a150_0, 0, 1; +L_0x137f6b0 .part L_0x137e980, 1, 1; +L_0x137f810 .part v0x127a150_0, 1, 1; +L_0x137f9c0 .part L_0x137e980, 2, 1; +L_0x137fb20 .part v0x127a150_0, 2, 1; +L_0x137fcd0 .part L_0x137e980, 3, 1; +L_0x137fe30 .part v0x127a150_0, 3, 1; +L_0x1380030 .part L_0x137e980, 4, 1; +L_0x13802a0 .part v0x127a150_0, 4, 1; +L_0x13803b0 .part L_0x137e980, 5, 1; +L_0x1380510 .part v0x127a150_0, 5, 1; +L_0x1380730 .part L_0x137e980, 6, 1; +L_0x1380890 .part v0x127a150_0, 6, 1; +LS_0x1380a00_0_0 .concat8 [ 1 1 1 1], L_0x137f250, L_0x137f5f0, L_0x137f900, L_0x137fc10; +LS_0x1380a00_0_4 .concat8 [ 1 1 1 1], L_0x137ff70, L_0x1380340, L_0x1380670, L_0x1380600; +L_0x1380a00 .concat8 [ 4 4 0 0], LS_0x1380a00_0_0, LS_0x1380a00_0_4; +L_0x1380dc0 .part L_0x137e980, 7, 1; +L_0x1380fb0 .part v0x127a150_0, 7, 1; +S_0x11e22f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e2500 .param/l "i" 0 4 54, +C4<00>; +L_0x137f250/d .functor AND 1, L_0x137f360, L_0x137f550, C4<1>, C4<1>; +L_0x137f250 .delay 1 (30000,30000,30000) L_0x137f250/d; +v0x11e25e0_0 .net *"_s0", 0 0, L_0x137f360; 1 drivers +v0x11e26c0_0 .net *"_s1", 0 0, L_0x137f550; 1 drivers +S_0x11e27a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e29b0 .param/l "i" 0 4 54, +C4<01>; +L_0x137f5f0/d .functor AND 1, L_0x137f6b0, L_0x137f810, C4<1>, C4<1>; +L_0x137f5f0 .delay 1 (30000,30000,30000) L_0x137f5f0/d; +v0x11e2a70_0 .net *"_s0", 0 0, L_0x137f6b0; 1 drivers +v0x11e2b50_0 .net *"_s1", 0 0, L_0x137f810; 1 drivers +S_0x11e2c30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e2e70 .param/l "i" 0 4 54, +C4<010>; +L_0x137f900/d .functor AND 1, L_0x137f9c0, L_0x137fb20, C4<1>, C4<1>; +L_0x137f900 .delay 1 (30000,30000,30000) L_0x137f900/d; +v0x11e2f10_0 .net *"_s0", 0 0, L_0x137f9c0; 1 drivers +v0x11e2ff0_0 .net *"_s1", 0 0, L_0x137fb20; 1 drivers +S_0x11e30d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e32e0 .param/l "i" 0 4 54, +C4<011>; +L_0x137fc10/d .functor AND 1, L_0x137fcd0, L_0x137fe30, C4<1>, C4<1>; +L_0x137fc10 .delay 1 (30000,30000,30000) L_0x137fc10/d; +v0x11e33a0_0 .net *"_s0", 0 0, L_0x137fcd0; 1 drivers +v0x11e3480_0 .net *"_s1", 0 0, L_0x137fe30; 1 drivers +S_0x11e3560 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e37c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x137ff70/d .functor AND 1, L_0x1380030, L_0x13802a0, C4<1>, C4<1>; +L_0x137ff70 .delay 1 (30000,30000,30000) L_0x137ff70/d; +v0x11e3880_0 .net *"_s0", 0 0, L_0x1380030; 1 drivers +v0x11e3960_0 .net *"_s1", 0 0, L_0x13802a0; 1 drivers +S_0x11e3a40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e3c50 .param/l "i" 0 4 54, +C4<0101>; +L_0x1380340/d .functor AND 1, L_0x13803b0, L_0x1380510, C4<1>, C4<1>; +L_0x1380340 .delay 1 (30000,30000,30000) L_0x1380340/d; +v0x11e3d10_0 .net *"_s0", 0 0, L_0x13803b0; 1 drivers +v0x11e3df0_0 .net *"_s1", 0 0, L_0x1380510; 1 drivers +S_0x11e3ed0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e40e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1380670/d .functor AND 1, L_0x1380730, L_0x1380890, C4<1>, C4<1>; +L_0x1380670 .delay 1 (30000,30000,30000) L_0x1380670/d; +v0x11e41a0_0 .net *"_s0", 0 0, L_0x1380730; 1 drivers +v0x11e4280_0 .net *"_s1", 0 0, L_0x1380890; 1 drivers +S_0x11e4360 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11e20b0; + .timescale -9 -12; +P_0x11e4570 .param/l "i" 0 4 54, +C4<0111>; +L_0x1380600/d .functor AND 1, L_0x1380dc0, L_0x1380fb0, C4<1>, C4<1>; +L_0x1380600 .delay 1 (30000,30000,30000) L_0x1380600/d; +v0x11e4630_0 .net *"_s0", 0 0, L_0x1380dc0; 1 drivers +v0x11e4710_0 .net *"_s1", 0 0, L_0x1380fb0; 1 drivers +S_0x11e52d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11e1e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1382a00/d .functor OR 1, L_0x1382ac0, L_0x1382c70, C4<0>, C4<0>; +L_0x1382a00 .delay 1 (30000,30000,30000) L_0x1382a00/d; +v0x11e6e20_0 .net *"_s10", 0 0, L_0x1382ac0; 1 drivers +v0x11e6f00_0 .net *"_s12", 0 0, L_0x1382c70; 1 drivers +v0x11e6fe0_0 .net "in", 7 0, L_0x1380a00; alias, 1 drivers +v0x11e70b0_0 .net "ors", 1 0, L_0x1382820; 1 drivers +v0x11e7170_0 .net "out", 0 0, L_0x1382a00; alias, 1 drivers +L_0x1381bf0 .part L_0x1380a00, 0, 4; +L_0x1382820 .concat8 [ 1 1 0 0], L_0x13818e0, L_0x1382510; +L_0x1382960 .part L_0x1380a00, 4, 4; +L_0x1382ac0 .part L_0x1382820, 0, 1; +L_0x1382c70 .part L_0x1382820, 1, 1; +S_0x11e5490 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11e52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13810a0/d .functor OR 1, L_0x1381160, L_0x13812c0, C4<0>, C4<0>; +L_0x13810a0 .delay 1 (30000,30000,30000) L_0x13810a0/d; +L_0x13814f0/d .functor OR 1, L_0x1381600, L_0x1381760, C4<0>, C4<0>; +L_0x13814f0 .delay 1 (30000,30000,30000) L_0x13814f0/d; +L_0x13818e0/d .functor OR 1, L_0x1381950, L_0x1381b00, C4<0>, C4<0>; +L_0x13818e0 .delay 1 (30000,30000,30000) L_0x13818e0/d; +v0x11e56e0_0 .net *"_s0", 0 0, L_0x13810a0; 1 drivers +v0x11e57e0_0 .net *"_s10", 0 0, L_0x1381600; 1 drivers +v0x11e58c0_0 .net *"_s12", 0 0, L_0x1381760; 1 drivers +v0x11e5980_0 .net *"_s14", 0 0, L_0x1381950; 1 drivers +v0x11e5a60_0 .net *"_s16", 0 0, L_0x1381b00; 1 drivers +v0x11e5b90_0 .net *"_s3", 0 0, L_0x1381160; 1 drivers +v0x11e5c70_0 .net *"_s5", 0 0, L_0x13812c0; 1 drivers +v0x11e5d50_0 .net *"_s6", 0 0, L_0x13814f0; 1 drivers +v0x11e5e30_0 .net "in", 3 0, L_0x1381bf0; 1 drivers +v0x11e5fa0_0 .net "ors", 1 0, L_0x1381400; 1 drivers +v0x11e6080_0 .net "out", 0 0, L_0x13818e0; 1 drivers +L_0x1381160 .part L_0x1381bf0, 0, 1; +L_0x13812c0 .part L_0x1381bf0, 1, 1; +L_0x1381400 .concat8 [ 1 1 0 0], L_0x13810a0, L_0x13814f0; +L_0x1381600 .part L_0x1381bf0, 2, 1; +L_0x1381760 .part L_0x1381bf0, 3, 1; +L_0x1381950 .part L_0x1381400, 0, 1; +L_0x1381b00 .part L_0x1381400, 1, 1; +S_0x11e61a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11e52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1381d20/d .functor OR 1, L_0x1381d90, L_0x1381ef0, C4<0>, C4<0>; +L_0x1381d20 .delay 1 (30000,30000,30000) L_0x1381d20/d; +L_0x1382120/d .functor OR 1, L_0x1382230, L_0x1382390, C4<0>, C4<0>; +L_0x1382120 .delay 1 (30000,30000,30000) L_0x1382120/d; +L_0x1382510/d .functor OR 1, L_0x1382580, L_0x1382730, C4<0>, C4<0>; +L_0x1382510 .delay 1 (30000,30000,30000) L_0x1382510/d; +v0x11e6360_0 .net *"_s0", 0 0, L_0x1381d20; 1 drivers +v0x11e6460_0 .net *"_s10", 0 0, L_0x1382230; 1 drivers +v0x11e6540_0 .net *"_s12", 0 0, L_0x1382390; 1 drivers +v0x11e6600_0 .net *"_s14", 0 0, L_0x1382580; 1 drivers +v0x11e66e0_0 .net *"_s16", 0 0, L_0x1382730; 1 drivers +v0x11e6810_0 .net *"_s3", 0 0, L_0x1381d90; 1 drivers +v0x11e68f0_0 .net *"_s5", 0 0, L_0x1381ef0; 1 drivers +v0x11e69d0_0 .net *"_s6", 0 0, L_0x1382120; 1 drivers +v0x11e6ab0_0 .net "in", 3 0, L_0x1382960; 1 drivers +v0x11e6c20_0 .net "ors", 1 0, L_0x1382030; 1 drivers +v0x11e6d00_0 .net "out", 0 0, L_0x1382510; 1 drivers +L_0x1381d90 .part L_0x1382960, 0, 1; +L_0x1381ef0 .part L_0x1382960, 1, 1; +L_0x1382030 .concat8 [ 1 1 0 0], L_0x1381d20, L_0x1382120; +L_0x1382230 .part L_0x1382960, 2, 1; +L_0x1382390 .part L_0x1382960, 3, 1; +L_0x1382580 .part L_0x1382030, 0, 1; +L_0x1382730 .part L_0x1382030, 1, 1; +S_0x11e7610 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11daf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x137d830/d .functor XNOR 1, L_0x13868a0, L_0x1386a00, C4<0>, C4<0>; +L_0x137d830 .delay 1 (20000,20000,20000) L_0x137d830/d; +L_0x137d9b0/d .functor AND 1, L_0x13868a0, L_0x137c520, C4<1>, C4<1>; +L_0x137d9b0 .delay 1 (30000,30000,30000) L_0x137d9b0/d; +L_0x137db10/d .functor AND 1, L_0x137d830, L_0x137c1c0, C4<1>, C4<1>; +L_0x137db10 .delay 1 (30000,30000,30000) L_0x137db10/d; +L_0x137dc20/d .functor OR 1, L_0x137db10, L_0x137d9b0, C4<0>, C4<0>; +L_0x137dc20 .delay 1 (30000,30000,30000) L_0x137dc20/d; +v0x11e78c0_0 .net "a", 0 0, L_0x13868a0; alias, 1 drivers +v0x11e79b0_0 .net "a_", 0 0, L_0x137c410; alias, 1 drivers +v0x11e7a70_0 .net "b", 0 0, L_0x1386a00; alias, 1 drivers +v0x11e7b60_0 .net "b_", 0 0, L_0x137c520; alias, 1 drivers +v0x11e7c00_0 .net "carryin", 0 0, L_0x137c1c0; alias, 1 drivers +v0x11e7d40_0 .net "eq", 0 0, L_0x137d830; 1 drivers +v0x11e7e00_0 .net "lt", 0 0, L_0x137d9b0; 1 drivers +v0x11e7ec0_0 .net "out", 0 0, L_0x137dc20; 1 drivers +v0x11e7f80_0 .net "w0", 0 0, L_0x137db10; 1 drivers +S_0x11e81d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11daf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x137d410/d .functor OR 1, L_0x137cf10, L_0x11e9430, C4<0>, C4<0>; +L_0x137d410 .delay 1 (30000,30000,30000) L_0x137d410/d; +v0x11e8fc0_0 .net "a", 0 0, L_0x13868a0; alias, 1 drivers +v0x11e9110_0 .net "b", 0 0, L_0x137c520; alias, 1 drivers +v0x11e91d0_0 .net "c1", 0 0, L_0x137cf10; 1 drivers +v0x11e9270_0 .net "c2", 0 0, L_0x11e9430; 1 drivers +v0x11e9340_0 .net "carryin", 0 0, L_0x137c1c0; alias, 1 drivers +v0x11e94c0_0 .net "carryout", 0 0, L_0x137d410; 1 drivers +v0x11e9560_0 .net "s1", 0 0, L_0x137ce50; 1 drivers +v0x11e9600_0 .net "sum", 0 0, L_0x137d070; 1 drivers +S_0x11e8420 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11e81d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x137ce50/d .functor XOR 1, L_0x13868a0, L_0x137c520, C4<0>, C4<0>; +L_0x137ce50 .delay 1 (30000,30000,30000) L_0x137ce50/d; +L_0x137cf10/d .functor AND 1, L_0x13868a0, L_0x137c520, C4<1>, C4<1>; +L_0x137cf10 .delay 1 (30000,30000,30000) L_0x137cf10/d; +v0x11e8680_0 .net "a", 0 0, L_0x13868a0; alias, 1 drivers +v0x11e8740_0 .net "b", 0 0, L_0x137c520; alias, 1 drivers +v0x11e8800_0 .net "carryout", 0 0, L_0x137cf10; alias, 1 drivers +v0x11e88a0_0 .net "sum", 0 0, L_0x137ce50; alias, 1 drivers +S_0x11e89d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11e81d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x137d070/d .functor XOR 1, L_0x137ce50, L_0x137c1c0, C4<0>, C4<0>; +L_0x137d070 .delay 1 (30000,30000,30000) L_0x137d070/d; +L_0x11e9430/d .functor AND 1, L_0x137ce50, L_0x137c1c0, C4<1>, C4<1>; +L_0x11e9430 .delay 1 (30000,30000,30000) L_0x11e9430/d; +v0x11e8c30_0 .net "a", 0 0, L_0x137ce50; alias, 1 drivers +v0x11e8d00_0 .net "b", 0 0, L_0x137c1c0; alias, 1 drivers +v0x11e8da0_0 .net "carryout", 0 0, L_0x11e9430; alias, 1 drivers +v0x11e8e70_0 .net "sum", 0 0, L_0x137d070; alias, 1 drivers +S_0x11eb690 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11dacc0; + .timescale -9 -12; +L_0x2ac432889168 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328891b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x137ecc0/d .functor OR 1, L_0x2ac432889168, L_0x2ac4328891b0, C4<0>, C4<0>; +L_0x137ecc0 .delay 1 (30000,30000,30000) L_0x137ecc0/d; +v0x11eb880_0 .net/2u *"_s0", 0 0, L_0x2ac432889168; 1 drivers +v0x11eb960_0 .net/2u *"_s2", 0 0, L_0x2ac4328891b0; 1 drivers +S_0x11eba40 .scope generate, "alu_slices[25]" "alu_slices[25]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11ebc50 .param/l "i" 0 3 39, +C4<011001>; +S_0x11ebd10 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11eba40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x137c300/d .functor NOT 1, L_0x1391100, C4<0>, C4<0>, C4<0>; +L_0x137c300 .delay 1 (10000,10000,10000) L_0x137c300/d; +L_0x1386d50/d .functor NOT 1, L_0x1386aa0, C4<0>, C4<0>, C4<0>; +L_0x1386d50 .delay 1 (10000,10000,10000) L_0x1386d50/d; +L_0x1387da0/d .functor XOR 1, L_0x1391100, L_0x1386aa0, C4<0>, C4<0>; +L_0x1387da0 .delay 1 (30000,30000,30000) L_0x1387da0/d; +L_0x2ac4328891f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889240 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1387e60/d .functor OR 1, L_0x2ac4328891f8, L_0x2ac432889240, C4<0>, C4<0>; +L_0x1387e60 .delay 1 (30000,30000,30000) L_0x1387e60/d; +L_0x2ac432889288 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328892d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13885b0/d .functor OR 1, L_0x2ac432889288, L_0x2ac4328892d0, C4<0>, C4<0>; +L_0x13885b0 .delay 1 (30000,30000,30000) L_0x13885b0/d; +L_0x13887b0/d .functor AND 1, L_0x1391100, L_0x1386aa0, C4<1>, C4<1>; +L_0x13887b0 .delay 1 (30000,30000,30000) L_0x13887b0/d; +L_0x2ac432889318 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889360 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1388870/d .functor OR 1, L_0x2ac432889318, L_0x2ac432889360, C4<0>, C4<0>; +L_0x1388870 .delay 1 (30000,30000,30000) L_0x1388870/d; +L_0x1388a70/d .functor NAND 1, L_0x1391100, L_0x1386aa0, C4<1>, C4<1>; +L_0x1388a70 .delay 1 (20000,20000,20000) L_0x1388a70/d; +L_0x2ac4328893a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328893f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1388b80/d .functor OR 1, L_0x2ac4328893a8, L_0x2ac4328893f0, C4<0>, C4<0>; +L_0x1388b80 .delay 1 (30000,30000,30000) L_0x1388b80/d; +L_0x1388d30/d .functor NOR 1, L_0x1391100, L_0x1386aa0, C4<0>, C4<0>; +L_0x1388d30 .delay 1 (20000,20000,20000) L_0x1388d30/d; +L_0x2ac432889438 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889480 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1389000/d .functor OR 1, L_0x2ac432889438, L_0x2ac432889480, C4<0>, C4<0>; +L_0x1389000 .delay 1 (30000,30000,30000) L_0x1389000/d; +L_0x1389400/d .functor OR 1, L_0x1391100, L_0x1386aa0, C4<0>, C4<0>; +L_0x1389400 .delay 1 (30000,30000,30000) L_0x1389400/d; +L_0x2ac4328894c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889510 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13898a0/d .functor OR 1, L_0x2ac4328894c8, L_0x2ac432889510, C4<0>, C4<0>; +L_0x13898a0 .delay 1 (30000,30000,30000) L_0x13898a0/d; +L_0x1391000/d .functor NOT 1, L_0x138d260, C4<0>, C4<0>, C4<0>; +L_0x1391000 .delay 1 (10000,10000,10000) L_0x1391000/d; +v0x11fac40_0 .net "A", 0 0, L_0x1391100; 1 drivers +v0x11fad00_0 .net "A_", 0 0, L_0x137c300; 1 drivers +v0x11fadc0_0 .net "B", 0 0, L_0x1386aa0; 1 drivers +v0x11fae90_0 .net "B_", 0 0, L_0x1386d50; 1 drivers +v0x11faf30_0 .net *"_s11", 0 0, L_0x1387e60; 1 drivers +v0x11fb020_0 .net/2s *"_s13", 0 0, L_0x2ac4328891f8; 1 drivers +v0x11fb0e0_0 .net/2s *"_s15", 0 0, L_0x2ac432889240; 1 drivers +v0x11fb1c0_0 .net *"_s19", 0 0, L_0x13885b0; 1 drivers +v0x11fb2a0_0 .net/2s *"_s21", 0 0, L_0x2ac432889288; 1 drivers +v0x11fb410_0 .net/2s *"_s23", 0 0, L_0x2ac4328892d0; 1 drivers +v0x11fb4f0_0 .net *"_s25", 0 0, L_0x13887b0; 1 drivers +v0x11fb5d0_0 .net *"_s28", 0 0, L_0x1388870; 1 drivers +v0x11fb6b0_0 .net/2s *"_s30", 0 0, L_0x2ac432889318; 1 drivers +v0x11fb790_0 .net/2s *"_s32", 0 0, L_0x2ac432889360; 1 drivers +v0x11fb870_0 .net *"_s34", 0 0, L_0x1388a70; 1 drivers +v0x11fb950_0 .net *"_s37", 0 0, L_0x1388b80; 1 drivers +v0x11fba30_0 .net/2s *"_s39", 0 0, L_0x2ac4328893a8; 1 drivers +v0x11fbbe0_0 .net/2s *"_s41", 0 0, L_0x2ac4328893f0; 1 drivers +v0x11fbc80_0 .net *"_s43", 0 0, L_0x1388d30; 1 drivers +v0x11fbd60_0 .net *"_s46", 0 0, L_0x1389000; 1 drivers +v0x11fbe40_0 .net/2s *"_s48", 0 0, L_0x2ac432889438; 1 drivers +v0x11fbf20_0 .net/2s *"_s50", 0 0, L_0x2ac432889480; 1 drivers +v0x11fc000_0 .net *"_s52", 0 0, L_0x1389400; 1 drivers +v0x11fc0e0_0 .net *"_s56", 0 0, L_0x13898a0; 1 drivers +v0x11fc1c0_0 .net/2s *"_s59", 0 0, L_0x2ac4328894c8; 1 drivers +v0x11fc2a0_0 .net/2s *"_s61", 0 0, L_0x2ac432889510; 1 drivers +v0x11fc380_0 .net *"_s8", 0 0, L_0x1387da0; 1 drivers +v0x11fc460_0 .net "carryin", 0 0, L_0x1386b40; 1 drivers +v0x11fc500_0 .net "carryout", 0 0, L_0x1390ca0; 1 drivers +v0x11fc5a0_0 .net "carryouts", 7 0, L_0x1389510; 1 drivers +v0x11fc6b0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x11fc770_0 .net "result", 0 0, L_0x138d260; 1 drivers +v0x11fc860_0 .net "results", 7 0, L_0x13891d0; 1 drivers +v0x11fbb40_0 .net "zero", 0 0, L_0x1391000; 1 drivers +LS_0x13891d0_0_0 .concat8 [ 1 1 1 1], L_0x1387270, L_0x13878a0, L_0x1387da0, L_0x13885b0; +LS_0x13891d0_0_4 .concat8 [ 1 1 1 1], L_0x13887b0, L_0x1388a70, L_0x1388d30, L_0x1389400; +L_0x13891d0 .concat8 [ 4 4 0 0], LS_0x13891d0_0_0, LS_0x13891d0_0_4; +LS_0x1389510_0_0 .concat8 [ 1 1 1 1], L_0x1387520, L_0x1387c40, L_0x1387e60, L_0x1388400; +LS_0x1389510_0_4 .concat8 [ 1 1 1 1], L_0x1388870, L_0x1388b80, L_0x1389000, L_0x13898a0; +L_0x1389510 .concat8 [ 4 4 0 0], LS_0x1389510_0_0, LS_0x1389510_0_4; +S_0x11ebf90 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11ebd10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1387520/d .functor OR 1, L_0x1387000, L_0x13873c0, C4<0>, C4<0>; +L_0x1387520 .delay 1 (30000,30000,30000) L_0x1387520/d; +v0x11ecdc0_0 .net "a", 0 0, L_0x1391100; alias, 1 drivers +v0x11ece80_0 .net "b", 0 0, L_0x1386aa0; alias, 1 drivers +v0x11ecf50_0 .net "c1", 0 0, L_0x1387000; 1 drivers +v0x11ed050_0 .net "c2", 0 0, L_0x13873c0; 1 drivers +v0x11ed120_0 .net "carryin", 0 0, L_0x1386b40; alias, 1 drivers +v0x11ed210_0 .net "carryout", 0 0, L_0x1387520; 1 drivers +v0x11ed2b0_0 .net "s1", 0 0, L_0x1386f40; 1 drivers +v0x11ed3a0_0 .net "sum", 0 0, L_0x1387270; 1 drivers +S_0x11ec200 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11ebf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1386f40/d .functor XOR 1, L_0x1391100, L_0x1386aa0, C4<0>, C4<0>; +L_0x1386f40 .delay 1 (30000,30000,30000) L_0x1386f40/d; +L_0x1387000/d .functor AND 1, L_0x1391100, L_0x1386aa0, C4<1>, C4<1>; +L_0x1387000 .delay 1 (30000,30000,30000) L_0x1387000/d; +v0x11ec460_0 .net "a", 0 0, L_0x1391100; alias, 1 drivers +v0x11ec540_0 .net "b", 0 0, L_0x1386aa0; alias, 1 drivers +v0x11ec600_0 .net "carryout", 0 0, L_0x1387000; alias, 1 drivers +v0x11ec6a0_0 .net "sum", 0 0, L_0x1386f40; alias, 1 drivers +S_0x11ec7e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11ebf90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1387270/d .functor XOR 1, L_0x1386f40, L_0x1386b40, C4<0>, C4<0>; +L_0x1387270 .delay 1 (30000,30000,30000) L_0x1387270/d; +L_0x13873c0/d .functor AND 1, L_0x1386f40, L_0x1386b40, C4<1>, C4<1>; +L_0x13873c0 .delay 1 (30000,30000,30000) L_0x13873c0/d; +v0x11eca40_0 .net "a", 0 0, L_0x1386f40; alias, 1 drivers +v0x11ecae0_0 .net "b", 0 0, L_0x1386b40; alias, 1 drivers +v0x11ecb80_0 .net "carryout", 0 0, L_0x13873c0; alias, 1 drivers +v0x11ecc50_0 .net "sum", 0 0, L_0x1387270; alias, 1 drivers +S_0x11ed470 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11ebd10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11f2860_0 .net "ands", 7 0, L_0x138eca0; 1 drivers +v0x11f2970_0 .net "in", 7 0, L_0x1389510; alias, 1 drivers +v0x11f2a30_0 .net "out", 0 0, L_0x1390ca0; alias, 1 drivers +v0x11f2b00_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11ed690 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11ed470; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11efdc0_0 .net "A", 7 0, L_0x1389510; alias, 1 drivers +v0x11efec0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11eff80_0 .net *"_s0", 0 0, L_0x138d5c0; 1 drivers +v0x11f0040_0 .net *"_s12", 0 0, L_0x138df30; 1 drivers +v0x11f0120_0 .net *"_s16", 0 0, L_0x138e290; 1 drivers +v0x11f0250_0 .net *"_s20", 0 0, L_0x138e660; 1 drivers +v0x11f0330_0 .net *"_s24", 0 0, L_0x138e990; 1 drivers +v0x11f0410_0 .net *"_s28", 0 0, L_0x138e920; 1 drivers +v0x11f04f0_0 .net *"_s4", 0 0, L_0x138d910; 1 drivers +v0x11f0660_0 .net *"_s8", 0 0, L_0x138dc20; 1 drivers +v0x11f0740_0 .net "out", 7 0, L_0x138eca0; alias, 1 drivers +L_0x138d680 .part L_0x1389510, 0, 1; +L_0x138d870 .part v0x127a150_0, 0, 1; +L_0x138d9d0 .part L_0x1389510, 1, 1; +L_0x138db30 .part v0x127a150_0, 1, 1; +L_0x138dce0 .part L_0x1389510, 2, 1; +L_0x138de40 .part v0x127a150_0, 2, 1; +L_0x138dff0 .part L_0x1389510, 3, 1; +L_0x138e150 .part v0x127a150_0, 3, 1; +L_0x138e350 .part L_0x1389510, 4, 1; +L_0x138e5c0 .part v0x127a150_0, 4, 1; +L_0x138e6d0 .part L_0x1389510, 5, 1; +L_0x138e830 .part v0x127a150_0, 5, 1; +L_0x138ea50 .part L_0x1389510, 6, 1; +L_0x138ebb0 .part v0x127a150_0, 6, 1; +LS_0x138eca0_0_0 .concat8 [ 1 1 1 1], L_0x138d5c0, L_0x138d910, L_0x138dc20, L_0x138df30; +LS_0x138eca0_0_4 .concat8 [ 1 1 1 1], L_0x138e290, L_0x138e660, L_0x138e990, L_0x138e920; +L_0x138eca0 .concat8 [ 4 4 0 0], LS_0x138eca0_0_0, LS_0x138eca0_0_4; +L_0x138f060 .part L_0x1389510, 7, 1; +L_0x138f250 .part v0x127a150_0, 7, 1; +S_0x11ed8f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11edb00 .param/l "i" 0 4 54, +C4<00>; +L_0x138d5c0/d .functor AND 1, L_0x138d680, L_0x138d870, C4<1>, C4<1>; +L_0x138d5c0 .delay 1 (30000,30000,30000) L_0x138d5c0/d; +v0x11edbe0_0 .net *"_s0", 0 0, L_0x138d680; 1 drivers +v0x11edcc0_0 .net *"_s1", 0 0, L_0x138d870; 1 drivers +S_0x11edda0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11edfb0 .param/l "i" 0 4 54, +C4<01>; +L_0x138d910/d .functor AND 1, L_0x138d9d0, L_0x138db30, C4<1>, C4<1>; +L_0x138d910 .delay 1 (30000,30000,30000) L_0x138d910/d; +v0x11ee070_0 .net *"_s0", 0 0, L_0x138d9d0; 1 drivers +v0x11ee150_0 .net *"_s1", 0 0, L_0x138db30; 1 drivers +S_0x11ee230 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11ee440 .param/l "i" 0 4 54, +C4<010>; +L_0x138dc20/d .functor AND 1, L_0x138dce0, L_0x138de40, C4<1>, C4<1>; +L_0x138dc20 .delay 1 (30000,30000,30000) L_0x138dc20/d; +v0x11ee4e0_0 .net *"_s0", 0 0, L_0x138dce0; 1 drivers +v0x11ee5c0_0 .net *"_s1", 0 0, L_0x138de40; 1 drivers +S_0x11ee6a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11ee8b0 .param/l "i" 0 4 54, +C4<011>; +L_0x138df30/d .functor AND 1, L_0x138dff0, L_0x138e150, C4<1>, C4<1>; +L_0x138df30 .delay 1 (30000,30000,30000) L_0x138df30/d; +v0x11ee970_0 .net *"_s0", 0 0, L_0x138dff0; 1 drivers +v0x11eea50_0 .net *"_s1", 0 0, L_0x138e150; 1 drivers +S_0x11eeb30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11eed90 .param/l "i" 0 4 54, +C4<0100>; +L_0x138e290/d .functor AND 1, L_0x138e350, L_0x138e5c0, C4<1>, C4<1>; +L_0x138e290 .delay 1 (30000,30000,30000) L_0x138e290/d; +v0x11eee50_0 .net *"_s0", 0 0, L_0x138e350; 1 drivers +v0x11eef30_0 .net *"_s1", 0 0, L_0x138e5c0; 1 drivers +S_0x11ef010 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11ef220 .param/l "i" 0 4 54, +C4<0101>; +L_0x138e660/d .functor AND 1, L_0x138e6d0, L_0x138e830, C4<1>, C4<1>; +L_0x138e660 .delay 1 (30000,30000,30000) L_0x138e660/d; +v0x11ef2e0_0 .net *"_s0", 0 0, L_0x138e6d0; 1 drivers +v0x11ef3c0_0 .net *"_s1", 0 0, L_0x138e830; 1 drivers +S_0x11ef4a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11ef6b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x138e990/d .functor AND 1, L_0x138ea50, L_0x138ebb0, C4<1>, C4<1>; +L_0x138e990 .delay 1 (30000,30000,30000) L_0x138e990/d; +v0x11ef770_0 .net *"_s0", 0 0, L_0x138ea50; 1 drivers +v0x11ef850_0 .net *"_s1", 0 0, L_0x138ebb0; 1 drivers +S_0x11ef930 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11ed690; + .timescale -9 -12; +P_0x11efb40 .param/l "i" 0 4 54, +C4<0111>; +L_0x138e920/d .functor AND 1, L_0x138f060, L_0x138f250, C4<1>, C4<1>; +L_0x138e920 .delay 1 (30000,30000,30000) L_0x138e920/d; +v0x11efc00_0 .net *"_s0", 0 0, L_0x138f060; 1 drivers +v0x11efce0_0 .net *"_s1", 0 0, L_0x138f250; 1 drivers +S_0x11f08a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11ed470; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1390ca0/d .functor OR 1, L_0x1390d60, L_0x1390f10, C4<0>, C4<0>; +L_0x1390ca0 .delay 1 (30000,30000,30000) L_0x1390ca0/d; +v0x11f23f0_0 .net *"_s10", 0 0, L_0x1390d60; 1 drivers +v0x11f24d0_0 .net *"_s12", 0 0, L_0x1390f10; 1 drivers +v0x11f25b0_0 .net "in", 7 0, L_0x138eca0; alias, 1 drivers +v0x11f2680_0 .net "ors", 1 0, L_0x1390ac0; 1 drivers +v0x11f2740_0 .net "out", 0 0, L_0x1390ca0; alias, 1 drivers +L_0x138fe90 .part L_0x138eca0, 0, 4; +L_0x1390ac0 .concat8 [ 1 1 0 0], L_0x138fb80, L_0x13907b0; +L_0x1390c00 .part L_0x138eca0, 4, 4; +L_0x1390d60 .part L_0x1390ac0, 0, 1; +L_0x1390f10 .part L_0x1390ac0, 1, 1; +S_0x11f0a60 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x138f340/d .functor OR 1, L_0x138f400, L_0x138f560, C4<0>, C4<0>; +L_0x138f340 .delay 1 (30000,30000,30000) L_0x138f340/d; +L_0x138f790/d .functor OR 1, L_0x138f8a0, L_0x138fa00, C4<0>, C4<0>; +L_0x138f790 .delay 1 (30000,30000,30000) L_0x138f790/d; +L_0x138fb80/d .functor OR 1, L_0x138fbf0, L_0x138fda0, C4<0>, C4<0>; +L_0x138fb80 .delay 1 (30000,30000,30000) L_0x138fb80/d; +v0x11f0cb0_0 .net *"_s0", 0 0, L_0x138f340; 1 drivers +v0x11f0db0_0 .net *"_s10", 0 0, L_0x138f8a0; 1 drivers +v0x11f0e90_0 .net *"_s12", 0 0, L_0x138fa00; 1 drivers +v0x11f0f50_0 .net *"_s14", 0 0, L_0x138fbf0; 1 drivers +v0x11f1030_0 .net *"_s16", 0 0, L_0x138fda0; 1 drivers +v0x11f1160_0 .net *"_s3", 0 0, L_0x138f400; 1 drivers +v0x11f1240_0 .net *"_s5", 0 0, L_0x138f560; 1 drivers +v0x11f1320_0 .net *"_s6", 0 0, L_0x138f790; 1 drivers +v0x11f1400_0 .net "in", 3 0, L_0x138fe90; 1 drivers +v0x11f1570_0 .net "ors", 1 0, L_0x138f6a0; 1 drivers +v0x11f1650_0 .net "out", 0 0, L_0x138fb80; 1 drivers +L_0x138f400 .part L_0x138fe90, 0, 1; +L_0x138f560 .part L_0x138fe90, 1, 1; +L_0x138f6a0 .concat8 [ 1 1 0 0], L_0x138f340, L_0x138f790; +L_0x138f8a0 .part L_0x138fe90, 2, 1; +L_0x138fa00 .part L_0x138fe90, 3, 1; +L_0x138fbf0 .part L_0x138f6a0, 0, 1; +L_0x138fda0 .part L_0x138f6a0, 1, 1; +S_0x11f1770 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11f08a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x138ffc0/d .functor OR 1, L_0x1390030, L_0x1390190, C4<0>, C4<0>; +L_0x138ffc0 .delay 1 (30000,30000,30000) L_0x138ffc0/d; +L_0x13903c0/d .functor OR 1, L_0x13904d0, L_0x1390630, C4<0>, C4<0>; +L_0x13903c0 .delay 1 (30000,30000,30000) L_0x13903c0/d; +L_0x13907b0/d .functor OR 1, L_0x1390820, L_0x13909d0, C4<0>, C4<0>; +L_0x13907b0 .delay 1 (30000,30000,30000) L_0x13907b0/d; +v0x11f1930_0 .net *"_s0", 0 0, L_0x138ffc0; 1 drivers +v0x11f1a30_0 .net *"_s10", 0 0, L_0x13904d0; 1 drivers +v0x11f1b10_0 .net *"_s12", 0 0, L_0x1390630; 1 drivers +v0x11f1bd0_0 .net *"_s14", 0 0, L_0x1390820; 1 drivers +v0x11f1cb0_0 .net *"_s16", 0 0, L_0x13909d0; 1 drivers +v0x11f1de0_0 .net *"_s3", 0 0, L_0x1390030; 1 drivers +v0x11f1ec0_0 .net *"_s5", 0 0, L_0x1390190; 1 drivers +v0x11f1fa0_0 .net *"_s6", 0 0, L_0x13903c0; 1 drivers +v0x11f2080_0 .net "in", 3 0, L_0x1390c00; 1 drivers +v0x11f21f0_0 .net "ors", 1 0, L_0x13902d0; 1 drivers +v0x11f22d0_0 .net "out", 0 0, L_0x13907b0; 1 drivers +L_0x1390030 .part L_0x1390c00, 0, 1; +L_0x1390190 .part L_0x1390c00, 1, 1; +L_0x13902d0 .concat8 [ 1 1 0 0], L_0x138ffc0, L_0x13903c0; +L_0x13904d0 .part L_0x1390c00, 2, 1; +L_0x1390630 .part L_0x1390c00, 3, 1; +L_0x1390820 .part L_0x13902d0, 0, 1; +L_0x13909d0 .part L_0x13902d0, 1, 1; +S_0x11f2be0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11ebd10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x11f8010_0 .net "ands", 7 0, L_0x138b260; 1 drivers +v0x11f8120_0 .net "in", 7 0, L_0x13891d0; alias, 1 drivers +v0x11f81e0_0 .net "out", 0 0, L_0x138d260; alias, 1 drivers +v0x11f82b0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11f2e30 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11f2be0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x11f5570_0 .net "A", 7 0, L_0x13891d0; alias, 1 drivers +v0x11f5670_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x11f5730_0 .net *"_s0", 0 0, L_0x1389a50; 1 drivers +v0x11f57f0_0 .net *"_s12", 0 0, L_0x138a410; 1 drivers +v0x11f58d0_0 .net *"_s16", 0 0, L_0x138a770; 1 drivers +v0x11f5a00_0 .net *"_s20", 0 0, L_0x138aba0; 1 drivers +v0x11f5ae0_0 .net *"_s24", 0 0, L_0x138aed0; 1 drivers +v0x11f5bc0_0 .net *"_s28", 0 0, L_0x138ae60; 1 drivers +v0x11f5ca0_0 .net *"_s4", 0 0, L_0x1389df0; 1 drivers +v0x11f5e10_0 .net *"_s8", 0 0, L_0x138a100; 1 drivers +v0x11f5ef0_0 .net "out", 7 0, L_0x138b260; alias, 1 drivers +L_0x1389b60 .part L_0x13891d0, 0, 1; +L_0x1389d50 .part v0x127a150_0, 0, 1; +L_0x1389eb0 .part L_0x13891d0, 1, 1; +L_0x138a010 .part v0x127a150_0, 1, 1; +L_0x138a1c0 .part L_0x13891d0, 2, 1; +L_0x138a320 .part v0x127a150_0, 2, 1; +L_0x138a4d0 .part L_0x13891d0, 3, 1; +L_0x138a630 .part v0x127a150_0, 3, 1; +L_0x138a830 .part L_0x13891d0, 4, 1; +L_0x138aaa0 .part v0x127a150_0, 4, 1; +L_0x138ac10 .part L_0x13891d0, 5, 1; +L_0x138ad70 .part v0x127a150_0, 5, 1; +L_0x138af90 .part L_0x13891d0, 6, 1; +L_0x138b0f0 .part v0x127a150_0, 6, 1; +LS_0x138b260_0_0 .concat8 [ 1 1 1 1], L_0x1389a50, L_0x1389df0, L_0x138a100, L_0x138a410; +LS_0x138b260_0_4 .concat8 [ 1 1 1 1], L_0x138a770, L_0x138aba0, L_0x138aed0, L_0x138ae60; +L_0x138b260 .concat8 [ 4 4 0 0], LS_0x138b260_0_0, LS_0x138b260_0_4; +L_0x138b620 .part L_0x13891d0, 7, 1; +L_0x138b810 .part v0x127a150_0, 7, 1; +S_0x11f3070 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f3280 .param/l "i" 0 4 54, +C4<00>; +L_0x1389a50/d .functor AND 1, L_0x1389b60, L_0x1389d50, C4<1>, C4<1>; +L_0x1389a50 .delay 1 (30000,30000,30000) L_0x1389a50/d; +v0x11f3360_0 .net *"_s0", 0 0, L_0x1389b60; 1 drivers +v0x11f3440_0 .net *"_s1", 0 0, L_0x1389d50; 1 drivers +S_0x11f3520 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f3730 .param/l "i" 0 4 54, +C4<01>; +L_0x1389df0/d .functor AND 1, L_0x1389eb0, L_0x138a010, C4<1>, C4<1>; +L_0x1389df0 .delay 1 (30000,30000,30000) L_0x1389df0/d; +v0x11f37f0_0 .net *"_s0", 0 0, L_0x1389eb0; 1 drivers +v0x11f38d0_0 .net *"_s1", 0 0, L_0x138a010; 1 drivers +S_0x11f39b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f3bf0 .param/l "i" 0 4 54, +C4<010>; +L_0x138a100/d .functor AND 1, L_0x138a1c0, L_0x138a320, C4<1>, C4<1>; +L_0x138a100 .delay 1 (30000,30000,30000) L_0x138a100/d; +v0x11f3c90_0 .net *"_s0", 0 0, L_0x138a1c0; 1 drivers +v0x11f3d70_0 .net *"_s1", 0 0, L_0x138a320; 1 drivers +S_0x11f3e50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f4060 .param/l "i" 0 4 54, +C4<011>; +L_0x138a410/d .functor AND 1, L_0x138a4d0, L_0x138a630, C4<1>, C4<1>; +L_0x138a410 .delay 1 (30000,30000,30000) L_0x138a410/d; +v0x11f4120_0 .net *"_s0", 0 0, L_0x138a4d0; 1 drivers +v0x11f4200_0 .net *"_s1", 0 0, L_0x138a630; 1 drivers +S_0x11f42e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f4540 .param/l "i" 0 4 54, +C4<0100>; +L_0x138a770/d .functor AND 1, L_0x138a830, L_0x138aaa0, C4<1>, C4<1>; +L_0x138a770 .delay 1 (30000,30000,30000) L_0x138a770/d; +v0x11f4600_0 .net *"_s0", 0 0, L_0x138a830; 1 drivers +v0x11f46e0_0 .net *"_s1", 0 0, L_0x138aaa0; 1 drivers +S_0x11f47c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f49d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x138aba0/d .functor AND 1, L_0x138ac10, L_0x138ad70, C4<1>, C4<1>; +L_0x138aba0 .delay 1 (30000,30000,30000) L_0x138aba0/d; +v0x11f4a90_0 .net *"_s0", 0 0, L_0x138ac10; 1 drivers +v0x11f4b70_0 .net *"_s1", 0 0, L_0x138ad70; 1 drivers +S_0x11f4c50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f4e60 .param/l "i" 0 4 54, +C4<0110>; +L_0x138aed0/d .functor AND 1, L_0x138af90, L_0x138b0f0, C4<1>, C4<1>; +L_0x138aed0 .delay 1 (30000,30000,30000) L_0x138aed0/d; +v0x11f4f20_0 .net *"_s0", 0 0, L_0x138af90; 1 drivers +v0x11f5000_0 .net *"_s1", 0 0, L_0x138b0f0; 1 drivers +S_0x11f50e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11f2e30; + .timescale -9 -12; +P_0x11f52f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x138ae60/d .functor AND 1, L_0x138b620, L_0x138b810, C4<1>, C4<1>; +L_0x138ae60 .delay 1 (30000,30000,30000) L_0x138ae60/d; +v0x11f53b0_0 .net *"_s0", 0 0, L_0x138b620; 1 drivers +v0x11f5490_0 .net *"_s1", 0 0, L_0x138b810; 1 drivers +S_0x11f6050 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11f2be0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x138d260/d .functor OR 1, L_0x138d320, L_0x138d4d0, C4<0>, C4<0>; +L_0x138d260 .delay 1 (30000,30000,30000) L_0x138d260/d; +v0x11f7ba0_0 .net *"_s10", 0 0, L_0x138d320; 1 drivers +v0x11f7c80_0 .net *"_s12", 0 0, L_0x138d4d0; 1 drivers +v0x11f7d60_0 .net "in", 7 0, L_0x138b260; alias, 1 drivers +v0x11f7e30_0 .net "ors", 1 0, L_0x138d080; 1 drivers +v0x11f7ef0_0 .net "out", 0 0, L_0x138d260; alias, 1 drivers +L_0x138c450 .part L_0x138b260, 0, 4; +L_0x138d080 .concat8 [ 1 1 0 0], L_0x138c140, L_0x138cd70; +L_0x138d1c0 .part L_0x138b260, 4, 4; +L_0x138d320 .part L_0x138d080, 0, 1; +L_0x138d4d0 .part L_0x138d080, 1, 1; +S_0x11f6210 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11f6050; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x138b900/d .functor OR 1, L_0x138b9c0, L_0x138bb20, C4<0>, C4<0>; +L_0x138b900 .delay 1 (30000,30000,30000) L_0x138b900/d; +L_0x138bd50/d .functor OR 1, L_0x138be60, L_0x138bfc0, C4<0>, C4<0>; +L_0x138bd50 .delay 1 (30000,30000,30000) L_0x138bd50/d; +L_0x138c140/d .functor OR 1, L_0x138c1b0, L_0x138c360, C4<0>, C4<0>; +L_0x138c140 .delay 1 (30000,30000,30000) L_0x138c140/d; +v0x11f6460_0 .net *"_s0", 0 0, L_0x138b900; 1 drivers +v0x11f6560_0 .net *"_s10", 0 0, L_0x138be60; 1 drivers +v0x11f6640_0 .net *"_s12", 0 0, L_0x138bfc0; 1 drivers +v0x11f6700_0 .net *"_s14", 0 0, L_0x138c1b0; 1 drivers +v0x11f67e0_0 .net *"_s16", 0 0, L_0x138c360; 1 drivers +v0x11f6910_0 .net *"_s3", 0 0, L_0x138b9c0; 1 drivers +v0x11f69f0_0 .net *"_s5", 0 0, L_0x138bb20; 1 drivers +v0x11f6ad0_0 .net *"_s6", 0 0, L_0x138bd50; 1 drivers +v0x11f6bb0_0 .net "in", 3 0, L_0x138c450; 1 drivers +v0x11f6d20_0 .net "ors", 1 0, L_0x138bc60; 1 drivers +v0x11f6e00_0 .net "out", 0 0, L_0x138c140; 1 drivers +L_0x138b9c0 .part L_0x138c450, 0, 1; +L_0x138bb20 .part L_0x138c450, 1, 1; +L_0x138bc60 .concat8 [ 1 1 0 0], L_0x138b900, L_0x138bd50; +L_0x138be60 .part L_0x138c450, 2, 1; +L_0x138bfc0 .part L_0x138c450, 3, 1; +L_0x138c1b0 .part L_0x138bc60, 0, 1; +L_0x138c360 .part L_0x138bc60, 1, 1; +S_0x11f6f20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11f6050; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x138c580/d .functor OR 1, L_0x138c5f0, L_0x138c750, C4<0>, C4<0>; +L_0x138c580 .delay 1 (30000,30000,30000) L_0x138c580/d; +L_0x138c980/d .functor OR 1, L_0x138ca90, L_0x138cbf0, C4<0>, C4<0>; +L_0x138c980 .delay 1 (30000,30000,30000) L_0x138c980/d; +L_0x138cd70/d .functor OR 1, L_0x138cde0, L_0x138cf90, C4<0>, C4<0>; +L_0x138cd70 .delay 1 (30000,30000,30000) L_0x138cd70/d; +v0x11f70e0_0 .net *"_s0", 0 0, L_0x138c580; 1 drivers +v0x11f71e0_0 .net *"_s10", 0 0, L_0x138ca90; 1 drivers +v0x11f72c0_0 .net *"_s12", 0 0, L_0x138cbf0; 1 drivers +v0x11f7380_0 .net *"_s14", 0 0, L_0x138cde0; 1 drivers +v0x11f7460_0 .net *"_s16", 0 0, L_0x138cf90; 1 drivers +v0x11f7590_0 .net *"_s3", 0 0, L_0x138c5f0; 1 drivers +v0x11f7670_0 .net *"_s5", 0 0, L_0x138c750; 1 drivers +v0x11f7750_0 .net *"_s6", 0 0, L_0x138c980; 1 drivers +v0x11f7830_0 .net "in", 3 0, L_0x138d1c0; 1 drivers +v0x11f79a0_0 .net "ors", 1 0, L_0x138c890; 1 drivers +v0x11f7a80_0 .net "out", 0 0, L_0x138cd70; 1 drivers +L_0x138c5f0 .part L_0x138d1c0, 0, 1; +L_0x138c750 .part L_0x138d1c0, 1, 1; +L_0x138c890 .concat8 [ 1 1 0 0], L_0x138c580, L_0x138c980; +L_0x138ca90 .part L_0x138d1c0, 2, 1; +L_0x138cbf0 .part L_0x138d1c0, 3, 1; +L_0x138cde0 .part L_0x138c890, 0, 1; +L_0x138cf90 .part L_0x138c890, 1, 1; +S_0x1100b50 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11ebd10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1388010/d .functor XNOR 1, L_0x1391100, L_0x1386aa0, C4<0>, C4<0>; +L_0x1388010 .delay 1 (20000,20000,20000) L_0x1388010/d; +L_0x1388190/d .functor AND 1, L_0x1391100, L_0x1386d50, C4<1>, C4<1>; +L_0x1388190 .delay 1 (30000,30000,30000) L_0x1388190/d; +L_0x13882f0/d .functor AND 1, L_0x1388010, L_0x1386b40, C4<1>, C4<1>; +L_0x13882f0 .delay 1 (30000,30000,30000) L_0x13882f0/d; +L_0x1388400/d .functor OR 1, L_0x13882f0, L_0x1388190, C4<0>, C4<0>; +L_0x1388400 .delay 1 (30000,30000,30000) L_0x1388400/d; +v0x1100e00_0 .net "a", 0 0, L_0x1391100; alias, 1 drivers +v0x1100ef0_0 .net "a_", 0 0, L_0x137c300; alias, 1 drivers +v0x1100fb0_0 .net "b", 0 0, L_0x1386aa0; alias, 1 drivers +v0x11010a0_0 .net "b_", 0 0, L_0x1386d50; alias, 1 drivers +v0x1101140_0 .net "carryin", 0 0, L_0x1386b40; alias, 1 drivers +v0x1101280_0 .net "eq", 0 0, L_0x1388010; 1 drivers +v0x11f9380_0 .net "lt", 0 0, L_0x1388190; 1 drivers +v0x11f9440_0 .net "out", 0 0, L_0x1388400; 1 drivers +v0x11f9500_0 .net "w0", 0 0, L_0x13882f0; 1 drivers +S_0x11f9750 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11ebd10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1387c40/d .functor OR 1, L_0x1387740, L_0x11fa9b0, C4<0>, C4<0>; +L_0x1387c40 .delay 1 (30000,30000,30000) L_0x1387c40/d; +v0x11fa540_0 .net "a", 0 0, L_0x1391100; alias, 1 drivers +v0x11fa690_0 .net "b", 0 0, L_0x1386d50; alias, 1 drivers +v0x11fa750_0 .net "c1", 0 0, L_0x1387740; 1 drivers +v0x11fa7f0_0 .net "c2", 0 0, L_0x11fa9b0; 1 drivers +v0x11fa8c0_0 .net "carryin", 0 0, L_0x1386b40; alias, 1 drivers +v0x11faa40_0 .net "carryout", 0 0, L_0x1387c40; 1 drivers +v0x11faae0_0 .net "s1", 0 0, L_0x1387680; 1 drivers +v0x11fab80_0 .net "sum", 0 0, L_0x13878a0; 1 drivers +S_0x11f99a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11f9750; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1387680/d .functor XOR 1, L_0x1391100, L_0x1386d50, C4<0>, C4<0>; +L_0x1387680 .delay 1 (30000,30000,30000) L_0x1387680/d; +L_0x1387740/d .functor AND 1, L_0x1391100, L_0x1386d50, C4<1>, C4<1>; +L_0x1387740 .delay 1 (30000,30000,30000) L_0x1387740/d; +v0x11f9c00_0 .net "a", 0 0, L_0x1391100; alias, 1 drivers +v0x11f9cc0_0 .net "b", 0 0, L_0x1386d50; alias, 1 drivers +v0x11f9d80_0 .net "carryout", 0 0, L_0x1387740; alias, 1 drivers +v0x11f9e20_0 .net "sum", 0 0, L_0x1387680; alias, 1 drivers +S_0x11f9f50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11f9750; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13878a0/d .functor XOR 1, L_0x1387680, L_0x1386b40, C4<0>, C4<0>; +L_0x13878a0 .delay 1 (30000,30000,30000) L_0x13878a0/d; +L_0x11fa9b0/d .functor AND 1, L_0x1387680, L_0x1386b40, C4<1>, C4<1>; +L_0x11fa9b0 .delay 1 (30000,30000,30000) L_0x11fa9b0/d; +v0x11fa1b0_0 .net "a", 0 0, L_0x1387680; alias, 1 drivers +v0x11fa280_0 .net "b", 0 0, L_0x1386b40; alias, 1 drivers +v0x11fa320_0 .net "carryout", 0 0, L_0x11fa9b0; alias, 1 drivers +v0x11fa3f0_0 .net "sum", 0 0, L_0x13878a0; alias, 1 drivers +S_0x11fcc10 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11eba40; + .timescale -9 -12; +L_0x2ac432889558 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328895a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1387200/d .functor OR 1, L_0x2ac432889558, L_0x2ac4328895a0, C4<0>, C4<0>; +L_0x1387200 .delay 1 (30000,30000,30000) L_0x1387200/d; +v0x11fce00_0 .net/2u *"_s0", 0 0, L_0x2ac432889558; 1 drivers +v0x11fcee0_0 .net/2u *"_s2", 0 0, L_0x2ac4328895a0; 1 drivers +S_0x11fcfc0 .scope generate, "alu_slices[26]" "alu_slices[26]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x11fd1d0 .param/l "i" 0 3 39, +C4<011010>; +S_0x11fd290 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x11fcfc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1386c80/d .functor NOT 1, L_0x139b930, C4<0>, C4<0>, C4<0>; +L_0x1386c80 .delay 1 (10000,10000,10000) L_0x1386c80/d; +L_0x1391580/d .functor NOT 1, L_0x139ba90, C4<0>, C4<0>, C4<0>; +L_0x1391580 .delay 1 (10000,10000,10000) L_0x1391580/d; +L_0x1392580/d .functor XOR 1, L_0x139b930, L_0x139ba90, C4<0>, C4<0>; +L_0x1392580 .delay 1 (30000,30000,30000) L_0x1392580/d; +L_0x2ac4328895e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889630 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1392640/d .functor OR 1, L_0x2ac4328895e8, L_0x2ac432889630, C4<0>, C4<0>; +L_0x1392640 .delay 1 (30000,30000,30000) L_0x1392640/d; +L_0x2ac432889678 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328896c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1392de0/d .functor OR 1, L_0x2ac432889678, L_0x2ac4328896c0, C4<0>, C4<0>; +L_0x1392de0 .delay 1 (30000,30000,30000) L_0x1392de0/d; +L_0x1392fe0/d .functor AND 1, L_0x139b930, L_0x139ba90, C4<1>, C4<1>; +L_0x1392fe0 .delay 1 (30000,30000,30000) L_0x1392fe0/d; +L_0x2ac432889708 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889750 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13930a0/d .functor OR 1, L_0x2ac432889708, L_0x2ac432889750, C4<0>, C4<0>; +L_0x13930a0 .delay 1 (30000,30000,30000) L_0x13930a0/d; +L_0x13932a0/d .functor NAND 1, L_0x139b930, L_0x139ba90, C4<1>, C4<1>; +L_0x13932a0 .delay 1 (20000,20000,20000) L_0x13932a0/d; +L_0x2ac432889798 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac4328897e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13933b0/d .functor OR 1, L_0x2ac432889798, L_0x2ac4328897e0, C4<0>, C4<0>; +L_0x13933b0 .delay 1 (30000,30000,30000) L_0x13933b0/d; +L_0x1393560/d .functor NOR 1, L_0x139b930, L_0x139ba90, C4<0>, C4<0>; +L_0x1393560 .delay 1 (20000,20000,20000) L_0x1393560/d; +L_0x2ac432889828 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889870 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1393830/d .functor OR 1, L_0x2ac432889828, L_0x2ac432889870, C4<0>, C4<0>; +L_0x1393830 .delay 1 (30000,30000,30000) L_0x1393830/d; +L_0x1393c30/d .functor OR 1, L_0x139b930, L_0x139ba90, C4<0>, C4<0>; +L_0x1393c30 .delay 1 (30000,30000,30000) L_0x1393c30/d; +L_0x2ac4328898b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889900 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13940d0/d .functor OR 1, L_0x2ac4328898b8, L_0x2ac432889900, C4<0>, C4<0>; +L_0x13940d0 .delay 1 (30000,30000,30000) L_0x13940d0/d; +L_0x139b830/d .functor NOT 1, L_0x1397a90, C4<0>, C4<0>, C4<0>; +L_0x139b830 .delay 1 (10000,10000,10000) L_0x139b830/d; +v0x120b9c0_0 .net "A", 0 0, L_0x139b930; 1 drivers +v0x120ba80_0 .net "A_", 0 0, L_0x1386c80; 1 drivers +v0x120bb40_0 .net "B", 0 0, L_0x139ba90; 1 drivers +v0x120bc10_0 .net "B_", 0 0, L_0x1391580; 1 drivers +v0x120bcb0_0 .net *"_s11", 0 0, L_0x1392640; 1 drivers +v0x120bda0_0 .net/2s *"_s13", 0 0, L_0x2ac4328895e8; 1 drivers +v0x120be60_0 .net/2s *"_s15", 0 0, L_0x2ac432889630; 1 drivers +v0x120bf40_0 .net *"_s19", 0 0, L_0x1392de0; 1 drivers +v0x120c020_0 .net/2s *"_s21", 0 0, L_0x2ac432889678; 1 drivers +v0x120c190_0 .net/2s *"_s23", 0 0, L_0x2ac4328896c0; 1 drivers +v0x120c270_0 .net *"_s25", 0 0, L_0x1392fe0; 1 drivers +v0x120c350_0 .net *"_s28", 0 0, L_0x13930a0; 1 drivers +v0x120c430_0 .net/2s *"_s30", 0 0, L_0x2ac432889708; 1 drivers +v0x120c510_0 .net/2s *"_s32", 0 0, L_0x2ac432889750; 1 drivers +v0x120c5f0_0 .net *"_s34", 0 0, L_0x13932a0; 1 drivers +v0x120c6d0_0 .net *"_s37", 0 0, L_0x13933b0; 1 drivers +v0x120c7b0_0 .net/2s *"_s39", 0 0, L_0x2ac432889798; 1 drivers +v0x120c960_0 .net/2s *"_s41", 0 0, L_0x2ac4328897e0; 1 drivers +v0x120ca00_0 .net *"_s43", 0 0, L_0x1393560; 1 drivers +v0x120cae0_0 .net *"_s46", 0 0, L_0x1393830; 1 drivers +v0x120cbc0_0 .net/2s *"_s48", 0 0, L_0x2ac432889828; 1 drivers +v0x120cca0_0 .net/2s *"_s50", 0 0, L_0x2ac432889870; 1 drivers +v0x120cd80_0 .net *"_s52", 0 0, L_0x1393c30; 1 drivers +v0x120ce60_0 .net *"_s56", 0 0, L_0x13940d0; 1 drivers +v0x120cf40_0 .net/2s *"_s59", 0 0, L_0x2ac4328898b8; 1 drivers +v0x120d020_0 .net/2s *"_s61", 0 0, L_0x2ac432889900; 1 drivers +v0x120d100_0 .net *"_s8", 0 0, L_0x1392580; 1 drivers +v0x120d1e0_0 .net "carryin", 0 0, L_0x1391260; 1 drivers +v0x120d280_0 .net "carryout", 0 0, L_0x139b4d0; 1 drivers +v0x120d320_0 .net "carryouts", 7 0, L_0x1393d40; 1 drivers +v0x120d430_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x120d4f0_0 .net "result", 0 0, L_0x1397a90; 1 drivers +v0x120d5e0_0 .net "results", 7 0, L_0x1393a00; 1 drivers +v0x120c8c0_0 .net "zero", 0 0, L_0x139b830; 1 drivers +LS_0x1393a00_0_0 .concat8 [ 1 1 1 1], L_0x1391aa0, L_0x13920d0, L_0x1392580, L_0x1392de0; +LS_0x1393a00_0_4 .concat8 [ 1 1 1 1], L_0x1392fe0, L_0x13932a0, L_0x1393560, L_0x1393c30; +L_0x1393a00 .concat8 [ 4 4 0 0], LS_0x1393a00_0_0, LS_0x1393a00_0_4; +LS_0x1393d40_0_0 .concat8 [ 1 1 1 1], L_0x1391d50, L_0x1392420, L_0x1392640, L_0x1392c30; +LS_0x1393d40_0_4 .concat8 [ 1 1 1 1], L_0x13930a0, L_0x13933b0, L_0x1393830, L_0x13940d0; +L_0x1393d40 .concat8 [ 4 4 0 0], LS_0x1393d40_0_0, LS_0x1393d40_0_4; +S_0x11fd510 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11fd290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1391d50/d .functor OR 1, L_0x1391830, L_0x1391bf0, C4<0>, C4<0>; +L_0x1391d50 .delay 1 (30000,30000,30000) L_0x1391d50/d; +v0x11fe340_0 .net "a", 0 0, L_0x139b930; alias, 1 drivers +v0x11fe400_0 .net "b", 0 0, L_0x139ba90; alias, 1 drivers +v0x11fe4d0_0 .net "c1", 0 0, L_0x1391830; 1 drivers +v0x11fe5d0_0 .net "c2", 0 0, L_0x1391bf0; 1 drivers +v0x11fe6a0_0 .net "carryin", 0 0, L_0x1391260; alias, 1 drivers +v0x11fe790_0 .net "carryout", 0 0, L_0x1391d50; 1 drivers +v0x11fe830_0 .net "s1", 0 0, L_0x1391770; 1 drivers +v0x11fe920_0 .net "sum", 0 0, L_0x1391aa0; 1 drivers +S_0x11fd780 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11fd510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1391770/d .functor XOR 1, L_0x139b930, L_0x139ba90, C4<0>, C4<0>; +L_0x1391770 .delay 1 (30000,30000,30000) L_0x1391770/d; +L_0x1391830/d .functor AND 1, L_0x139b930, L_0x139ba90, C4<1>, C4<1>; +L_0x1391830 .delay 1 (30000,30000,30000) L_0x1391830/d; +v0x11fd9e0_0 .net "a", 0 0, L_0x139b930; alias, 1 drivers +v0x11fdac0_0 .net "b", 0 0, L_0x139ba90; alias, 1 drivers +v0x11fdb80_0 .net "carryout", 0 0, L_0x1391830; alias, 1 drivers +v0x11fdc20_0 .net "sum", 0 0, L_0x1391770; alias, 1 drivers +S_0x11fdd60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11fd510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1391aa0/d .functor XOR 1, L_0x1391770, L_0x1391260, C4<0>, C4<0>; +L_0x1391aa0 .delay 1 (30000,30000,30000) L_0x1391aa0/d; +L_0x1391bf0/d .functor AND 1, L_0x1391770, L_0x1391260, C4<1>, C4<1>; +L_0x1391bf0 .delay 1 (30000,30000,30000) L_0x1391bf0/d; +v0x11fdfc0_0 .net "a", 0 0, L_0x1391770; alias, 1 drivers +v0x11fe060_0 .net "b", 0 0, L_0x1391260; alias, 1 drivers +v0x11fe100_0 .net "carryout", 0 0, L_0x1391bf0; alias, 1 drivers +v0x11fe1d0_0 .net "sum", 0 0, L_0x1391aa0; alias, 1 drivers +S_0x11fe9f0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x11fd290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1203de0_0 .net "ands", 7 0, L_0x13994d0; 1 drivers +v0x1203ef0_0 .net "in", 7 0, L_0x1393d40; alias, 1 drivers +v0x1203fb0_0 .net "out", 0 0, L_0x139b4d0; alias, 1 drivers +v0x1204080_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x11fec10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11fe9f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1201340_0 .net "A", 7 0, L_0x1393d40; alias, 1 drivers +v0x1201440_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1201500_0 .net *"_s0", 0 0, L_0x1397df0; 1 drivers +v0x12015c0_0 .net *"_s12", 0 0, L_0x1398760; 1 drivers +v0x12016a0_0 .net *"_s16", 0 0, L_0x1398ac0; 1 drivers +v0x12017d0_0 .net *"_s20", 0 0, L_0x1398e90; 1 drivers +v0x12018b0_0 .net *"_s24", 0 0, L_0x13991c0; 1 drivers +v0x1201990_0 .net *"_s28", 0 0, L_0x1399150; 1 drivers +v0x1201a70_0 .net *"_s4", 0 0, L_0x1398140; 1 drivers +v0x1201be0_0 .net *"_s8", 0 0, L_0x1398450; 1 drivers +v0x1201cc0_0 .net "out", 7 0, L_0x13994d0; alias, 1 drivers +L_0x1397eb0 .part L_0x1393d40, 0, 1; +L_0x13980a0 .part v0x127a150_0, 0, 1; +L_0x1398200 .part L_0x1393d40, 1, 1; +L_0x1398360 .part v0x127a150_0, 1, 1; +L_0x1398510 .part L_0x1393d40, 2, 1; +L_0x1398670 .part v0x127a150_0, 2, 1; +L_0x1398820 .part L_0x1393d40, 3, 1; +L_0x1398980 .part v0x127a150_0, 3, 1; +L_0x1398b80 .part L_0x1393d40, 4, 1; +L_0x1398df0 .part v0x127a150_0, 4, 1; +L_0x1398f00 .part L_0x1393d40, 5, 1; +L_0x1399060 .part v0x127a150_0, 5, 1; +L_0x1399280 .part L_0x1393d40, 6, 1; +L_0x13993e0 .part v0x127a150_0, 6, 1; +LS_0x13994d0_0_0 .concat8 [ 1 1 1 1], L_0x1397df0, L_0x1398140, L_0x1398450, L_0x1398760; +LS_0x13994d0_0_4 .concat8 [ 1 1 1 1], L_0x1398ac0, L_0x1398e90, L_0x13991c0, L_0x1399150; +L_0x13994d0 .concat8 [ 4 4 0 0], LS_0x13994d0_0_0, LS_0x13994d0_0_4; +L_0x1399890 .part L_0x1393d40, 7, 1; +L_0x1399a80 .part v0x127a150_0, 7, 1; +S_0x11fee70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x11ff080 .param/l "i" 0 4 54, +C4<00>; +L_0x1397df0/d .functor AND 1, L_0x1397eb0, L_0x13980a0, C4<1>, C4<1>; +L_0x1397df0 .delay 1 (30000,30000,30000) L_0x1397df0/d; +v0x11ff160_0 .net *"_s0", 0 0, L_0x1397eb0; 1 drivers +v0x11ff240_0 .net *"_s1", 0 0, L_0x13980a0; 1 drivers +S_0x11ff320 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x11ff530 .param/l "i" 0 4 54, +C4<01>; +L_0x1398140/d .functor AND 1, L_0x1398200, L_0x1398360, C4<1>, C4<1>; +L_0x1398140 .delay 1 (30000,30000,30000) L_0x1398140/d; +v0x11ff5f0_0 .net *"_s0", 0 0, L_0x1398200; 1 drivers +v0x11ff6d0_0 .net *"_s1", 0 0, L_0x1398360; 1 drivers +S_0x11ff7b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x11ff9c0 .param/l "i" 0 4 54, +C4<010>; +L_0x1398450/d .functor AND 1, L_0x1398510, L_0x1398670, C4<1>, C4<1>; +L_0x1398450 .delay 1 (30000,30000,30000) L_0x1398450/d; +v0x11ffa60_0 .net *"_s0", 0 0, L_0x1398510; 1 drivers +v0x11ffb40_0 .net *"_s1", 0 0, L_0x1398670; 1 drivers +S_0x11ffc20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x11ffe30 .param/l "i" 0 4 54, +C4<011>; +L_0x1398760/d .functor AND 1, L_0x1398820, L_0x1398980, C4<1>, C4<1>; +L_0x1398760 .delay 1 (30000,30000,30000) L_0x1398760/d; +v0x11ffef0_0 .net *"_s0", 0 0, L_0x1398820; 1 drivers +v0x11fffd0_0 .net *"_s1", 0 0, L_0x1398980; 1 drivers +S_0x12000b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x1200310 .param/l "i" 0 4 54, +C4<0100>; +L_0x1398ac0/d .functor AND 1, L_0x1398b80, L_0x1398df0, C4<1>, C4<1>; +L_0x1398ac0 .delay 1 (30000,30000,30000) L_0x1398ac0/d; +v0x12003d0_0 .net *"_s0", 0 0, L_0x1398b80; 1 drivers +v0x12004b0_0 .net *"_s1", 0 0, L_0x1398df0; 1 drivers +S_0x1200590 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x12007a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1398e90/d .functor AND 1, L_0x1398f00, L_0x1399060, C4<1>, C4<1>; +L_0x1398e90 .delay 1 (30000,30000,30000) L_0x1398e90/d; +v0x1200860_0 .net *"_s0", 0 0, L_0x1398f00; 1 drivers +v0x1200940_0 .net *"_s1", 0 0, L_0x1399060; 1 drivers +S_0x1200a20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x1200c30 .param/l "i" 0 4 54, +C4<0110>; +L_0x13991c0/d .functor AND 1, L_0x1399280, L_0x13993e0, C4<1>, C4<1>; +L_0x13991c0 .delay 1 (30000,30000,30000) L_0x13991c0/d; +v0x1200cf0_0 .net *"_s0", 0 0, L_0x1399280; 1 drivers +v0x1200dd0_0 .net *"_s1", 0 0, L_0x13993e0; 1 drivers +S_0x1200eb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11fec10; + .timescale -9 -12; +P_0x12010c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1399150/d .functor AND 1, L_0x1399890, L_0x1399a80, C4<1>, C4<1>; +L_0x1399150 .delay 1 (30000,30000,30000) L_0x1399150/d; +v0x1201180_0 .net *"_s0", 0 0, L_0x1399890; 1 drivers +v0x1201260_0 .net *"_s1", 0 0, L_0x1399a80; 1 drivers +S_0x1201e20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11fe9f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x139b4d0/d .functor OR 1, L_0x139b590, L_0x139b740, C4<0>, C4<0>; +L_0x139b4d0 .delay 1 (30000,30000,30000) L_0x139b4d0/d; +v0x12039a0_0 .net *"_s10", 0 0, L_0x139b590; 1 drivers +v0x1203a80_0 .net *"_s12", 0 0, L_0x139b740; 1 drivers +v0x1203b60_0 .net "in", 7 0, L_0x13994d0; alias, 1 drivers +v0x1203c00_0 .net "ors", 1 0, L_0x139b2f0; 1 drivers +v0x1203cc0_0 .net "out", 0 0, L_0x139b4d0; alias, 1 drivers +L_0x139a6c0 .part L_0x13994d0, 0, 4; +L_0x139b2f0 .concat8 [ 1 1 0 0], L_0x139a3b0, L_0x139afe0; +L_0x139b430 .part L_0x13994d0, 4, 4; +L_0x139b590 .part L_0x139b2f0, 0, 1; +L_0x139b740 .part L_0x139b2f0, 1, 1; +S_0x1201fe0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1201e20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1399b70/d .functor OR 1, L_0x1399c30, L_0x1399d90, C4<0>, C4<0>; +L_0x1399b70 .delay 1 (30000,30000,30000) L_0x1399b70/d; +L_0x1399fc0/d .functor OR 1, L_0x139a0d0, L_0x139a230, C4<0>, C4<0>; +L_0x1399fc0 .delay 1 (30000,30000,30000) L_0x1399fc0/d; +L_0x139a3b0/d .functor OR 1, L_0x139a420, L_0x139a5d0, C4<0>, C4<0>; +L_0x139a3b0 .delay 1 (30000,30000,30000) L_0x139a3b0/d; +v0x1202210_0 .net *"_s0", 0 0, L_0x1399b70; 1 drivers +v0x1202310_0 .net *"_s10", 0 0, L_0x139a0d0; 1 drivers +v0x12023f0_0 .net *"_s12", 0 0, L_0x139a230; 1 drivers +v0x12024e0_0 .net *"_s14", 0 0, L_0x139a420; 1 drivers +v0x12025c0_0 .net *"_s16", 0 0, L_0x139a5d0; 1 drivers +v0x12026f0_0 .net *"_s3", 0 0, L_0x1399c30; 1 drivers +v0x12027d0_0 .net *"_s5", 0 0, L_0x1399d90; 1 drivers +v0x12028b0_0 .net *"_s6", 0 0, L_0x1399fc0; 1 drivers +v0x1202990_0 .net "in", 3 0, L_0x139a6c0; 1 drivers +v0x1202b00_0 .net "ors", 1 0, L_0x1399ed0; 1 drivers +v0x1202be0_0 .net "out", 0 0, L_0x139a3b0; 1 drivers +L_0x1399c30 .part L_0x139a6c0, 0, 1; +L_0x1399d90 .part L_0x139a6c0, 1, 1; +L_0x1399ed0 .concat8 [ 1 1 0 0], L_0x1399b70, L_0x1399fc0; +L_0x139a0d0 .part L_0x139a6c0, 2, 1; +L_0x139a230 .part L_0x139a6c0, 3, 1; +L_0x139a420 .part L_0x1399ed0, 0, 1; +L_0x139a5d0 .part L_0x1399ed0, 1, 1; +S_0x1202d00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1201e20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x139a7f0/d .functor OR 1, L_0x139a860, L_0x139a9c0, C4<0>, C4<0>; +L_0x139a7f0 .delay 1 (30000,30000,30000) L_0x139a7f0/d; +L_0x139abf0/d .functor OR 1, L_0x139ad00, L_0x139ae60, C4<0>, C4<0>; +L_0x139abf0 .delay 1 (30000,30000,30000) L_0x139abf0/d; +L_0x139afe0/d .functor OR 1, L_0x139b050, L_0x139b200, C4<0>, C4<0>; +L_0x139afe0 .delay 1 (30000,30000,30000) L_0x139afe0/d; +v0x1202ee0_0 .net *"_s0", 0 0, L_0x139a7f0; 1 drivers +v0x1202fe0_0 .net *"_s10", 0 0, L_0x139ad00; 1 drivers +v0x12030c0_0 .net *"_s12", 0 0, L_0x139ae60; 1 drivers +v0x1203180_0 .net *"_s14", 0 0, L_0x139b050; 1 drivers +v0x1203260_0 .net *"_s16", 0 0, L_0x139b200; 1 drivers +v0x1203390_0 .net *"_s3", 0 0, L_0x139a860; 1 drivers +v0x1203470_0 .net *"_s5", 0 0, L_0x139a9c0; 1 drivers +v0x1203550_0 .net *"_s6", 0 0, L_0x139abf0; 1 drivers +v0x1203630_0 .net "in", 3 0, L_0x139b430; 1 drivers +v0x12037a0_0 .net "ors", 1 0, L_0x139ab00; 1 drivers +v0x1203880_0 .net "out", 0 0, L_0x139afe0; 1 drivers +L_0x139a860 .part L_0x139b430, 0, 1; +L_0x139a9c0 .part L_0x139b430, 1, 1; +L_0x139ab00 .concat8 [ 1 1 0 0], L_0x139a7f0, L_0x139abf0; +L_0x139ad00 .part L_0x139b430, 2, 1; +L_0x139ae60 .part L_0x139b430, 3, 1; +L_0x139b050 .part L_0x139ab00, 0, 1; +L_0x139b200 .part L_0x139ab00, 1, 1; +S_0x1204160 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x11fd290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1209590_0 .net "ands", 7 0, L_0x1395a90; 1 drivers +v0x12096a0_0 .net "in", 7 0, L_0x1393a00; alias, 1 drivers +v0x1209760_0 .net "out", 0 0, L_0x1397a90; alias, 1 drivers +v0x1209830_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x12043b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1204160; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1206af0_0 .net "A", 7 0, L_0x1393a00; alias, 1 drivers +v0x1206bf0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1206cb0_0 .net *"_s0", 0 0, L_0x1394280; 1 drivers +v0x1206d70_0 .net *"_s12", 0 0, L_0x1394c40; 1 drivers +v0x1206e50_0 .net *"_s16", 0 0, L_0x1394fa0; 1 drivers +v0x1206f80_0 .net *"_s20", 0 0, L_0x13953d0; 1 drivers +v0x1207060_0 .net *"_s24", 0 0, L_0x1395700; 1 drivers +v0x1207140_0 .net *"_s28", 0 0, L_0x1395690; 1 drivers +v0x1207220_0 .net *"_s4", 0 0, L_0x1394620; 1 drivers +v0x1207390_0 .net *"_s8", 0 0, L_0x1394930; 1 drivers +v0x1207470_0 .net "out", 7 0, L_0x1395a90; alias, 1 drivers +L_0x1394390 .part L_0x1393a00, 0, 1; +L_0x1394580 .part v0x127a150_0, 0, 1; +L_0x13946e0 .part L_0x1393a00, 1, 1; +L_0x1394840 .part v0x127a150_0, 1, 1; +L_0x13949f0 .part L_0x1393a00, 2, 1; +L_0x1394b50 .part v0x127a150_0, 2, 1; +L_0x1394d00 .part L_0x1393a00, 3, 1; +L_0x1394e60 .part v0x127a150_0, 3, 1; +L_0x1395060 .part L_0x1393a00, 4, 1; +L_0x13952d0 .part v0x127a150_0, 4, 1; +L_0x1395440 .part L_0x1393a00, 5, 1; +L_0x13955a0 .part v0x127a150_0, 5, 1; +L_0x13957c0 .part L_0x1393a00, 6, 1; +L_0x1395920 .part v0x127a150_0, 6, 1; +LS_0x1395a90_0_0 .concat8 [ 1 1 1 1], L_0x1394280, L_0x1394620, L_0x1394930, L_0x1394c40; +LS_0x1395a90_0_4 .concat8 [ 1 1 1 1], L_0x1394fa0, L_0x13953d0, L_0x1395700, L_0x1395690; +L_0x1395a90 .concat8 [ 4 4 0 0], LS_0x1395a90_0_0, LS_0x1395a90_0_4; +L_0x1395e50 .part L_0x1393a00, 7, 1; +L_0x1396040 .part v0x127a150_0, 7, 1; +S_0x12045f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x1204800 .param/l "i" 0 4 54, +C4<00>; +L_0x1394280/d .functor AND 1, L_0x1394390, L_0x1394580, C4<1>, C4<1>; +L_0x1394280 .delay 1 (30000,30000,30000) L_0x1394280/d; +v0x12048e0_0 .net *"_s0", 0 0, L_0x1394390; 1 drivers +v0x12049c0_0 .net *"_s1", 0 0, L_0x1394580; 1 drivers +S_0x1204aa0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x1204cb0 .param/l "i" 0 4 54, +C4<01>; +L_0x1394620/d .functor AND 1, L_0x13946e0, L_0x1394840, C4<1>, C4<1>; +L_0x1394620 .delay 1 (30000,30000,30000) L_0x1394620/d; +v0x1204d70_0 .net *"_s0", 0 0, L_0x13946e0; 1 drivers +v0x1204e50_0 .net *"_s1", 0 0, L_0x1394840; 1 drivers +S_0x1204f30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x1205170 .param/l "i" 0 4 54, +C4<010>; +L_0x1394930/d .functor AND 1, L_0x13949f0, L_0x1394b50, C4<1>, C4<1>; +L_0x1394930 .delay 1 (30000,30000,30000) L_0x1394930/d; +v0x1205210_0 .net *"_s0", 0 0, L_0x13949f0; 1 drivers +v0x12052f0_0 .net *"_s1", 0 0, L_0x1394b50; 1 drivers +S_0x12053d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x12055e0 .param/l "i" 0 4 54, +C4<011>; +L_0x1394c40/d .functor AND 1, L_0x1394d00, L_0x1394e60, C4<1>, C4<1>; +L_0x1394c40 .delay 1 (30000,30000,30000) L_0x1394c40/d; +v0x12056a0_0 .net *"_s0", 0 0, L_0x1394d00; 1 drivers +v0x1205780_0 .net *"_s1", 0 0, L_0x1394e60; 1 drivers +S_0x1205860 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x1205ac0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1394fa0/d .functor AND 1, L_0x1395060, L_0x13952d0, C4<1>, C4<1>; +L_0x1394fa0 .delay 1 (30000,30000,30000) L_0x1394fa0/d; +v0x1205b80_0 .net *"_s0", 0 0, L_0x1395060; 1 drivers +v0x1205c60_0 .net *"_s1", 0 0, L_0x13952d0; 1 drivers +S_0x1205d40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x1205f50 .param/l "i" 0 4 54, +C4<0101>; +L_0x13953d0/d .functor AND 1, L_0x1395440, L_0x13955a0, C4<1>, C4<1>; +L_0x13953d0 .delay 1 (30000,30000,30000) L_0x13953d0/d; +v0x1206010_0 .net *"_s0", 0 0, L_0x1395440; 1 drivers +v0x12060f0_0 .net *"_s1", 0 0, L_0x13955a0; 1 drivers +S_0x12061d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x12063e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1395700/d .functor AND 1, L_0x13957c0, L_0x1395920, C4<1>, C4<1>; +L_0x1395700 .delay 1 (30000,30000,30000) L_0x1395700/d; +v0x12064a0_0 .net *"_s0", 0 0, L_0x13957c0; 1 drivers +v0x1206580_0 .net *"_s1", 0 0, L_0x1395920; 1 drivers +S_0x1206660 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x12043b0; + .timescale -9 -12; +P_0x1206870 .param/l "i" 0 4 54, +C4<0111>; +L_0x1395690/d .functor AND 1, L_0x1395e50, L_0x1396040, C4<1>, C4<1>; +L_0x1395690 .delay 1 (30000,30000,30000) L_0x1395690/d; +v0x1206930_0 .net *"_s0", 0 0, L_0x1395e50; 1 drivers +v0x1206a10_0 .net *"_s1", 0 0, L_0x1396040; 1 drivers +S_0x12075d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1204160; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1397a90/d .functor OR 1, L_0x1397b50, L_0x1397d00, C4<0>, C4<0>; +L_0x1397a90 .delay 1 (30000,30000,30000) L_0x1397a90/d; +v0x1209120_0 .net *"_s10", 0 0, L_0x1397b50; 1 drivers +v0x1209200_0 .net *"_s12", 0 0, L_0x1397d00; 1 drivers +v0x12092e0_0 .net "in", 7 0, L_0x1395a90; alias, 1 drivers +v0x12093b0_0 .net "ors", 1 0, L_0x13978b0; 1 drivers +v0x1209470_0 .net "out", 0 0, L_0x1397a90; alias, 1 drivers +L_0x1396c80 .part L_0x1395a90, 0, 4; +L_0x13978b0 .concat8 [ 1 1 0 0], L_0x1396970, L_0x13975a0; +L_0x13979f0 .part L_0x1395a90, 4, 4; +L_0x1397b50 .part L_0x13978b0, 0, 1; +L_0x1397d00 .part L_0x13978b0, 1, 1; +S_0x1207790 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x12075d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1396130/d .functor OR 1, L_0x13961f0, L_0x1396350, C4<0>, C4<0>; +L_0x1396130 .delay 1 (30000,30000,30000) L_0x1396130/d; +L_0x1396580/d .functor OR 1, L_0x1396690, L_0x13967f0, C4<0>, C4<0>; +L_0x1396580 .delay 1 (30000,30000,30000) L_0x1396580/d; +L_0x1396970/d .functor OR 1, L_0x13969e0, L_0x1396b90, C4<0>, C4<0>; +L_0x1396970 .delay 1 (30000,30000,30000) L_0x1396970/d; +v0x12079e0_0 .net *"_s0", 0 0, L_0x1396130; 1 drivers +v0x1207ae0_0 .net *"_s10", 0 0, L_0x1396690; 1 drivers +v0x1207bc0_0 .net *"_s12", 0 0, L_0x13967f0; 1 drivers +v0x1207c80_0 .net *"_s14", 0 0, L_0x13969e0; 1 drivers +v0x1207d60_0 .net *"_s16", 0 0, L_0x1396b90; 1 drivers +v0x1207e90_0 .net *"_s3", 0 0, L_0x13961f0; 1 drivers +v0x1207f70_0 .net *"_s5", 0 0, L_0x1396350; 1 drivers +v0x1208050_0 .net *"_s6", 0 0, L_0x1396580; 1 drivers +v0x1208130_0 .net "in", 3 0, L_0x1396c80; 1 drivers +v0x12082a0_0 .net "ors", 1 0, L_0x1396490; 1 drivers +v0x1208380_0 .net "out", 0 0, L_0x1396970; 1 drivers +L_0x13961f0 .part L_0x1396c80, 0, 1; +L_0x1396350 .part L_0x1396c80, 1, 1; +L_0x1396490 .concat8 [ 1 1 0 0], L_0x1396130, L_0x1396580; +L_0x1396690 .part L_0x1396c80, 2, 1; +L_0x13967f0 .part L_0x1396c80, 3, 1; +L_0x13969e0 .part L_0x1396490, 0, 1; +L_0x1396b90 .part L_0x1396490, 1, 1; +S_0x12084a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x12075d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1396db0/d .functor OR 1, L_0x1396e20, L_0x1396f80, C4<0>, C4<0>; +L_0x1396db0 .delay 1 (30000,30000,30000) L_0x1396db0/d; +L_0x13971b0/d .functor OR 1, L_0x13972c0, L_0x1397420, C4<0>, C4<0>; +L_0x13971b0 .delay 1 (30000,30000,30000) L_0x13971b0/d; +L_0x13975a0/d .functor OR 1, L_0x1397610, L_0x13977c0, C4<0>, C4<0>; +L_0x13975a0 .delay 1 (30000,30000,30000) L_0x13975a0/d; +v0x1208660_0 .net *"_s0", 0 0, L_0x1396db0; 1 drivers +v0x1208760_0 .net *"_s10", 0 0, L_0x13972c0; 1 drivers +v0x1208840_0 .net *"_s12", 0 0, L_0x1397420; 1 drivers +v0x1208900_0 .net *"_s14", 0 0, L_0x1397610; 1 drivers +v0x12089e0_0 .net *"_s16", 0 0, L_0x13977c0; 1 drivers +v0x1208b10_0 .net *"_s3", 0 0, L_0x1396e20; 1 drivers +v0x1208bf0_0 .net *"_s5", 0 0, L_0x1396f80; 1 drivers +v0x1208cd0_0 .net *"_s6", 0 0, L_0x13971b0; 1 drivers +v0x1208db0_0 .net "in", 3 0, L_0x13979f0; 1 drivers +v0x1208f20_0 .net "ors", 1 0, L_0x13970c0; 1 drivers +v0x1209000_0 .net "out", 0 0, L_0x13975a0; 1 drivers +L_0x1396e20 .part L_0x13979f0, 0, 1; +L_0x1396f80 .part L_0x13979f0, 1, 1; +L_0x13970c0 .concat8 [ 1 1 0 0], L_0x1396db0, L_0x13971b0; +L_0x13972c0 .part L_0x13979f0, 2, 1; +L_0x1397420 .part L_0x13979f0, 3, 1; +L_0x1397610 .part L_0x13970c0, 0, 1; +L_0x13977c0 .part L_0x13970c0, 1, 1; +S_0x1209910 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x11fd290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1392840/d .functor XNOR 1, L_0x139b930, L_0x139ba90, C4<0>, C4<0>; +L_0x1392840 .delay 1 (20000,20000,20000) L_0x1392840/d; +L_0x13929c0/d .functor AND 1, L_0x139b930, L_0x1391580, C4<1>, C4<1>; +L_0x13929c0 .delay 1 (30000,30000,30000) L_0x13929c0/d; +L_0x1392b20/d .functor AND 1, L_0x1392840, L_0x1391260, C4<1>, C4<1>; +L_0x1392b20 .delay 1 (30000,30000,30000) L_0x1392b20/d; +L_0x1392c30/d .functor OR 1, L_0x1392b20, L_0x13929c0, C4<0>, C4<0>; +L_0x1392c30 .delay 1 (30000,30000,30000) L_0x1392c30/d; +v0x1209bc0_0 .net "a", 0 0, L_0x139b930; alias, 1 drivers +v0x1209cb0_0 .net "a_", 0 0, L_0x1386c80; alias, 1 drivers +v0x1209d70_0 .net "b", 0 0, L_0x139ba90; alias, 1 drivers +v0x1209e60_0 .net "b_", 0 0, L_0x1391580; alias, 1 drivers +v0x1209f00_0 .net "carryin", 0 0, L_0x1391260; alias, 1 drivers +v0x120a040_0 .net "eq", 0 0, L_0x1392840; 1 drivers +v0x120a100_0 .net "lt", 0 0, L_0x13929c0; 1 drivers +v0x120a1c0_0 .net "out", 0 0, L_0x1392c30; 1 drivers +v0x120a280_0 .net "w0", 0 0, L_0x1392b20; 1 drivers +S_0x120a4d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11fd290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1392420/d .functor OR 1, L_0x1391f70, L_0x120b730, C4<0>, C4<0>; +L_0x1392420 .delay 1 (30000,30000,30000) L_0x1392420/d; +v0x120b2c0_0 .net "a", 0 0, L_0x139b930; alias, 1 drivers +v0x120b410_0 .net "b", 0 0, L_0x1391580; alias, 1 drivers +v0x120b4d0_0 .net "c1", 0 0, L_0x1391f70; 1 drivers +v0x120b570_0 .net "c2", 0 0, L_0x120b730; 1 drivers +v0x120b640_0 .net "carryin", 0 0, L_0x1391260; alias, 1 drivers +v0x120b7c0_0 .net "carryout", 0 0, L_0x1392420; 1 drivers +v0x120b860_0 .net "s1", 0 0, L_0x1391eb0; 1 drivers +v0x120b900_0 .net "sum", 0 0, L_0x13920d0; 1 drivers +S_0x120a720 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x120a4d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1391eb0/d .functor XOR 1, L_0x139b930, L_0x1391580, C4<0>, C4<0>; +L_0x1391eb0 .delay 1 (30000,30000,30000) L_0x1391eb0/d; +L_0x1391f70/d .functor AND 1, L_0x139b930, L_0x1391580, C4<1>, C4<1>; +L_0x1391f70 .delay 1 (30000,30000,30000) L_0x1391f70/d; +v0x120a980_0 .net "a", 0 0, L_0x139b930; alias, 1 drivers +v0x120aa40_0 .net "b", 0 0, L_0x1391580; alias, 1 drivers +v0x120ab00_0 .net "carryout", 0 0, L_0x1391f70; alias, 1 drivers +v0x120aba0_0 .net "sum", 0 0, L_0x1391eb0; alias, 1 drivers +S_0x120acd0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x120a4d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13920d0/d .functor XOR 1, L_0x1391eb0, L_0x1391260, C4<0>, C4<0>; +L_0x13920d0 .delay 1 (30000,30000,30000) L_0x13920d0/d; +L_0x120b730/d .functor AND 1, L_0x1391eb0, L_0x1391260, C4<1>, C4<1>; +L_0x120b730 .delay 1 (30000,30000,30000) L_0x120b730/d; +v0x120af30_0 .net "a", 0 0, L_0x1391eb0; alias, 1 drivers +v0x120b000_0 .net "b", 0 0, L_0x1391260; alias, 1 drivers +v0x120b0a0_0 .net "carryout", 0 0, L_0x120b730; alias, 1 drivers +v0x120b170_0 .net "sum", 0 0, L_0x13920d0; alias, 1 drivers +S_0x120d990 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x11fcfc0; + .timescale -9 -12; +L_0x2ac432889948 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889990 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1391a30/d .functor OR 1, L_0x2ac432889948, L_0x2ac432889990, C4<0>, C4<0>; +L_0x1391a30 .delay 1 (30000,30000,30000) L_0x1391a30/d; +v0x120db80_0 .net/2u *"_s0", 0 0, L_0x2ac432889948; 1 drivers +v0x120dc60_0 .net/2u *"_s2", 0 0, L_0x2ac432889990; 1 drivers +S_0x120dd40 .scope generate, "alu_slices[27]" "alu_slices[27]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x120df50 .param/l "i" 0 3 39, +C4<011011>; +S_0x120e010 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x120dd40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13913a0/d .functor NOT 1, L_0x13a6190, C4<0>, C4<0>, C4<0>; +L_0x13913a0 .delay 1 (10000,10000,10000) L_0x13913a0/d; +L_0x139be10/d .functor NOT 1, L_0x139bb30, C4<0>, C4<0>, C4<0>; +L_0x139be10 .delay 1 (10000,10000,10000) L_0x139be10/d; +L_0x139ce60/d .functor XOR 1, L_0x13a6190, L_0x139bb30, C4<0>, C4<0>; +L_0x139ce60 .delay 1 (30000,30000,30000) L_0x139ce60/d; +L_0x2ac4328899d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889a20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139cf20/d .functor OR 1, L_0x2ac4328899d8, L_0x2ac432889a20, C4<0>, C4<0>; +L_0x139cf20 .delay 1 (30000,30000,30000) L_0x139cf20/d; +L_0x2ac432889a68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889ab0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139d6c0/d .functor OR 1, L_0x2ac432889a68, L_0x2ac432889ab0, C4<0>, C4<0>; +L_0x139d6c0 .delay 1 (30000,30000,30000) L_0x139d6c0/d; +L_0x139d8c0/d .functor AND 1, L_0x13a6190, L_0x139bb30, C4<1>, C4<1>; +L_0x139d8c0 .delay 1 (30000,30000,30000) L_0x139d8c0/d; +L_0x2ac432889af8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889b40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139d980/d .functor OR 1, L_0x2ac432889af8, L_0x2ac432889b40, C4<0>, C4<0>; +L_0x139d980 .delay 1 (30000,30000,30000) L_0x139d980/d; +L_0x139db80/d .functor NAND 1, L_0x13a6190, L_0x139bb30, C4<1>, C4<1>; +L_0x139db80 .delay 1 (20000,20000,20000) L_0x139db80/d; +L_0x2ac432889b88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889bd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139dc90/d .functor OR 1, L_0x2ac432889b88, L_0x2ac432889bd0, C4<0>, C4<0>; +L_0x139dc90 .delay 1 (30000,30000,30000) L_0x139dc90/d; +L_0x139de40/d .functor NOR 1, L_0x13a6190, L_0x139bb30, C4<0>, C4<0>; +L_0x139de40 .delay 1 (20000,20000,20000) L_0x139de40/d; +L_0x2ac432889c18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889c60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139c2c0/d .functor OR 1, L_0x2ac432889c18, L_0x2ac432889c60, C4<0>, C4<0>; +L_0x139c2c0 .delay 1 (30000,30000,30000) L_0x139c2c0/d; +L_0x139e4a0/d .functor OR 1, L_0x13a6190, L_0x139bb30, C4<0>, C4<0>; +L_0x139e4a0 .delay 1 (30000,30000,30000) L_0x139e4a0/d; +L_0x2ac432889ca8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889cf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139e990/d .functor OR 1, L_0x2ac432889ca8, L_0x2ac432889cf0, C4<0>, C4<0>; +L_0x139e990 .delay 1 (30000,30000,30000) L_0x139e990/d; +L_0x13a6090/d .functor NOT 1, L_0x13a22f0, C4<0>, C4<0>, C4<0>; +L_0x13a6090 .delay 1 (10000,10000,10000) L_0x13a6090/d; +v0x121c740_0 .net "A", 0 0, L_0x13a6190; 1 drivers +v0x121c800_0 .net "A_", 0 0, L_0x13913a0; 1 drivers +v0x121c8c0_0 .net "B", 0 0, L_0x139bb30; 1 drivers +v0x121c990_0 .net "B_", 0 0, L_0x139be10; 1 drivers +v0x121ca30_0 .net *"_s11", 0 0, L_0x139cf20; 1 drivers +v0x121cb20_0 .net/2s *"_s13", 0 0, L_0x2ac4328899d8; 1 drivers +v0x121cbe0_0 .net/2s *"_s15", 0 0, L_0x2ac432889a20; 1 drivers +v0x121ccc0_0 .net *"_s19", 0 0, L_0x139d6c0; 1 drivers +v0x121cda0_0 .net/2s *"_s21", 0 0, L_0x2ac432889a68; 1 drivers +v0x121cf10_0 .net/2s *"_s23", 0 0, L_0x2ac432889ab0; 1 drivers +v0x121cff0_0 .net *"_s25", 0 0, L_0x139d8c0; 1 drivers +v0x121d0d0_0 .net *"_s28", 0 0, L_0x139d980; 1 drivers +v0x121d1b0_0 .net/2s *"_s30", 0 0, L_0x2ac432889af8; 1 drivers +v0x121d290_0 .net/2s *"_s32", 0 0, L_0x2ac432889b40; 1 drivers +v0x121d370_0 .net *"_s34", 0 0, L_0x139db80; 1 drivers +v0x121d450_0 .net *"_s37", 0 0, L_0x139dc90; 1 drivers +v0x121d530_0 .net/2s *"_s39", 0 0, L_0x2ac432889b88; 1 drivers +v0x121d6e0_0 .net/2s *"_s41", 0 0, L_0x2ac432889bd0; 1 drivers +v0x121d780_0 .net *"_s43", 0 0, L_0x139de40; 1 drivers +v0x121d860_0 .net *"_s46", 0 0, L_0x139c2c0; 1 drivers +v0x121d940_0 .net/2s *"_s48", 0 0, L_0x2ac432889c18; 1 drivers +v0x121da20_0 .net/2s *"_s50", 0 0, L_0x2ac432889c60; 1 drivers +v0x121db00_0 .net *"_s52", 0 0, L_0x139e4a0; 1 drivers +v0x121dbe0_0 .net *"_s56", 0 0, L_0x139e990; 1 drivers +v0x121dcc0_0 .net/2s *"_s59", 0 0, L_0x2ac432889ca8; 1 drivers +v0x121dda0_0 .net/2s *"_s61", 0 0, L_0x2ac432889cf0; 1 drivers +v0x121de80_0 .net *"_s8", 0 0, L_0x139ce60; 1 drivers +v0x121df60_0 .net "carryin", 0 0, L_0x139bbd0; 1 drivers +v0x121e000_0 .net "carryout", 0 0, L_0x13a5d30; 1 drivers +v0x121e0a0_0 .net "carryouts", 7 0, L_0x139e620; 1 drivers +v0x121e1b0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x121e270_0 .net "result", 0 0, L_0x13a22f0; 1 drivers +v0x121e360_0 .net "results", 7 0, L_0x139e270; 1 drivers +v0x121d640_0 .net "zero", 0 0, L_0x13a6090; 1 drivers +LS_0x139e270_0_0 .concat8 [ 1 1 1 1], L_0x139c330, L_0x139c960, L_0x139ce60, L_0x139d6c0; +LS_0x139e270_0_4 .concat8 [ 1 1 1 1], L_0x139d8c0, L_0x139db80, L_0x139de40, L_0x139e4a0; +L_0x139e270 .concat8 [ 4 4 0 0], LS_0x139e270_0_0, LS_0x139e270_0_4; +LS_0x139e620_0_0 .concat8 [ 1 1 1 1], L_0x139c5e0, L_0x139cd00, L_0x139cf20, L_0x139d510; +LS_0x139e620_0_4 .concat8 [ 1 1 1 1], L_0x139d980, L_0x139dc90, L_0x139c2c0, L_0x139e990; +L_0x139e620 .concat8 [ 4 4 0 0], LS_0x139e620_0_0, LS_0x139e620_0_4; +S_0x120e290 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x120e010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x139c5e0/d .functor OR 1, L_0x139c0c0, L_0x139c480, C4<0>, C4<0>; +L_0x139c5e0 .delay 1 (30000,30000,30000) L_0x139c5e0/d; +v0x120f0c0_0 .net "a", 0 0, L_0x13a6190; alias, 1 drivers +v0x120f180_0 .net "b", 0 0, L_0x139bb30; alias, 1 drivers +v0x120f250_0 .net "c1", 0 0, L_0x139c0c0; 1 drivers +v0x120f350_0 .net "c2", 0 0, L_0x139c480; 1 drivers +v0x120f420_0 .net "carryin", 0 0, L_0x139bbd0; alias, 1 drivers +v0x120f510_0 .net "carryout", 0 0, L_0x139c5e0; 1 drivers +v0x120f5b0_0 .net "s1", 0 0, L_0x139c000; 1 drivers +v0x120f6a0_0 .net "sum", 0 0, L_0x139c330; 1 drivers +S_0x120e500 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x120e290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x139c000/d .functor XOR 1, L_0x13a6190, L_0x139bb30, C4<0>, C4<0>; +L_0x139c000 .delay 1 (30000,30000,30000) L_0x139c000/d; +L_0x139c0c0/d .functor AND 1, L_0x13a6190, L_0x139bb30, C4<1>, C4<1>; +L_0x139c0c0 .delay 1 (30000,30000,30000) L_0x139c0c0/d; +v0x120e760_0 .net "a", 0 0, L_0x13a6190; alias, 1 drivers +v0x120e840_0 .net "b", 0 0, L_0x139bb30; alias, 1 drivers +v0x120e900_0 .net "carryout", 0 0, L_0x139c0c0; alias, 1 drivers +v0x120e9a0_0 .net "sum", 0 0, L_0x139c000; alias, 1 drivers +S_0x120eae0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x120e290; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x139c330/d .functor XOR 1, L_0x139c000, L_0x139bbd0, C4<0>, C4<0>; +L_0x139c330 .delay 1 (30000,30000,30000) L_0x139c330/d; +L_0x139c480/d .functor AND 1, L_0x139c000, L_0x139bbd0, C4<1>, C4<1>; +L_0x139c480 .delay 1 (30000,30000,30000) L_0x139c480/d; +v0x120ed40_0 .net "a", 0 0, L_0x139c000; alias, 1 drivers +v0x120ede0_0 .net "b", 0 0, L_0x139bbd0; alias, 1 drivers +v0x120ee80_0 .net "carryout", 0 0, L_0x139c480; alias, 1 drivers +v0x120ef50_0 .net "sum", 0 0, L_0x139c330; alias, 1 drivers +S_0x120f770 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x120e010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1214b60_0 .net "ands", 7 0, L_0x13a3d30; 1 drivers +v0x1214c70_0 .net "in", 7 0, L_0x139e620; alias, 1 drivers +v0x1214d30_0 .net "out", 0 0, L_0x13a5d30; alias, 1 drivers +v0x1214e00_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x120f990 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x120f770; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x12120c0_0 .net "A", 7 0, L_0x139e620; alias, 1 drivers +v0x12121c0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1212280_0 .net *"_s0", 0 0, L_0x13a2650; 1 drivers +v0x1212340_0 .net *"_s12", 0 0, L_0x13a2fc0; 1 drivers +v0x1212420_0 .net *"_s16", 0 0, L_0x13a3320; 1 drivers +v0x1212550_0 .net *"_s20", 0 0, L_0x13a36f0; 1 drivers +v0x1212630_0 .net *"_s24", 0 0, L_0x13a3a20; 1 drivers +v0x1212710_0 .net *"_s28", 0 0, L_0x13a39b0; 1 drivers +v0x12127f0_0 .net *"_s4", 0 0, L_0x13a29a0; 1 drivers +v0x1212960_0 .net *"_s8", 0 0, L_0x13a2cb0; 1 drivers +v0x1212a40_0 .net "out", 7 0, L_0x13a3d30; alias, 1 drivers +L_0x13a2710 .part L_0x139e620, 0, 1; +L_0x13a2900 .part v0x127a150_0, 0, 1; +L_0x13a2a60 .part L_0x139e620, 1, 1; +L_0x13a2bc0 .part v0x127a150_0, 1, 1; +L_0x13a2d70 .part L_0x139e620, 2, 1; +L_0x13a2ed0 .part v0x127a150_0, 2, 1; +L_0x13a3080 .part L_0x139e620, 3, 1; +L_0x13a31e0 .part v0x127a150_0, 3, 1; +L_0x13a33e0 .part L_0x139e620, 4, 1; +L_0x13a3650 .part v0x127a150_0, 4, 1; +L_0x13a3760 .part L_0x139e620, 5, 1; +L_0x13a38c0 .part v0x127a150_0, 5, 1; +L_0x13a3ae0 .part L_0x139e620, 6, 1; +L_0x13a3c40 .part v0x127a150_0, 6, 1; +LS_0x13a3d30_0_0 .concat8 [ 1 1 1 1], L_0x13a2650, L_0x13a29a0, L_0x13a2cb0, L_0x13a2fc0; +LS_0x13a3d30_0_4 .concat8 [ 1 1 1 1], L_0x13a3320, L_0x13a36f0, L_0x13a3a20, L_0x13a39b0; +L_0x13a3d30 .concat8 [ 4 4 0 0], LS_0x13a3d30_0_0, LS_0x13a3d30_0_4; +L_0x13a40f0 .part L_0x139e620, 7, 1; +L_0x13a42e0 .part v0x127a150_0, 7, 1; +S_0x120fbf0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x120fe00 .param/l "i" 0 4 54, +C4<00>; +L_0x13a2650/d .functor AND 1, L_0x13a2710, L_0x13a2900, C4<1>, C4<1>; +L_0x13a2650 .delay 1 (30000,30000,30000) L_0x13a2650/d; +v0x120fee0_0 .net *"_s0", 0 0, L_0x13a2710; 1 drivers +v0x120ffc0_0 .net *"_s1", 0 0, L_0x13a2900; 1 drivers +S_0x12100a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x12102b0 .param/l "i" 0 4 54, +C4<01>; +L_0x13a29a0/d .functor AND 1, L_0x13a2a60, L_0x13a2bc0, C4<1>, C4<1>; +L_0x13a29a0 .delay 1 (30000,30000,30000) L_0x13a29a0/d; +v0x1210370_0 .net *"_s0", 0 0, L_0x13a2a60; 1 drivers +v0x1210450_0 .net *"_s1", 0 0, L_0x13a2bc0; 1 drivers +S_0x1210530 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x1210740 .param/l "i" 0 4 54, +C4<010>; +L_0x13a2cb0/d .functor AND 1, L_0x13a2d70, L_0x13a2ed0, C4<1>, C4<1>; +L_0x13a2cb0 .delay 1 (30000,30000,30000) L_0x13a2cb0/d; +v0x12107e0_0 .net *"_s0", 0 0, L_0x13a2d70; 1 drivers +v0x12108c0_0 .net *"_s1", 0 0, L_0x13a2ed0; 1 drivers +S_0x12109a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x1210bb0 .param/l "i" 0 4 54, +C4<011>; +L_0x13a2fc0/d .functor AND 1, L_0x13a3080, L_0x13a31e0, C4<1>, C4<1>; +L_0x13a2fc0 .delay 1 (30000,30000,30000) L_0x13a2fc0/d; +v0x1210c70_0 .net *"_s0", 0 0, L_0x13a3080; 1 drivers +v0x1210d50_0 .net *"_s1", 0 0, L_0x13a31e0; 1 drivers +S_0x1210e30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x1211090 .param/l "i" 0 4 54, +C4<0100>; +L_0x13a3320/d .functor AND 1, L_0x13a33e0, L_0x13a3650, C4<1>, C4<1>; +L_0x13a3320 .delay 1 (30000,30000,30000) L_0x13a3320/d; +v0x1211150_0 .net *"_s0", 0 0, L_0x13a33e0; 1 drivers +v0x1211230_0 .net *"_s1", 0 0, L_0x13a3650; 1 drivers +S_0x1211310 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x1211520 .param/l "i" 0 4 54, +C4<0101>; +L_0x13a36f0/d .functor AND 1, L_0x13a3760, L_0x13a38c0, C4<1>, C4<1>; +L_0x13a36f0 .delay 1 (30000,30000,30000) L_0x13a36f0/d; +v0x12115e0_0 .net *"_s0", 0 0, L_0x13a3760; 1 drivers +v0x12116c0_0 .net *"_s1", 0 0, L_0x13a38c0; 1 drivers +S_0x12117a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x12119b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x13a3a20/d .functor AND 1, L_0x13a3ae0, L_0x13a3c40, C4<1>, C4<1>; +L_0x13a3a20 .delay 1 (30000,30000,30000) L_0x13a3a20/d; +v0x1211a70_0 .net *"_s0", 0 0, L_0x13a3ae0; 1 drivers +v0x1211b50_0 .net *"_s1", 0 0, L_0x13a3c40; 1 drivers +S_0x1211c30 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x120f990; + .timescale -9 -12; +P_0x1211e40 .param/l "i" 0 4 54, +C4<0111>; +L_0x13a39b0/d .functor AND 1, L_0x13a40f0, L_0x13a42e0, C4<1>, C4<1>; +L_0x13a39b0 .delay 1 (30000,30000,30000) L_0x13a39b0/d; +v0x1211f00_0 .net *"_s0", 0 0, L_0x13a40f0; 1 drivers +v0x1211fe0_0 .net *"_s1", 0 0, L_0x13a42e0; 1 drivers +S_0x1212ba0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x120f770; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13a5d30/d .functor OR 1, L_0x13a5df0, L_0x13a5fa0, C4<0>, C4<0>; +L_0x13a5d30 .delay 1 (30000,30000,30000) L_0x13a5d30/d; +v0x12146f0_0 .net *"_s10", 0 0, L_0x13a5df0; 1 drivers +v0x12147d0_0 .net *"_s12", 0 0, L_0x13a5fa0; 1 drivers +v0x12148b0_0 .net "in", 7 0, L_0x13a3d30; alias, 1 drivers +v0x1214980_0 .net "ors", 1 0, L_0x13a5b50; 1 drivers +v0x1214a40_0 .net "out", 0 0, L_0x13a5d30; alias, 1 drivers +L_0x13a4f20 .part L_0x13a3d30, 0, 4; +L_0x13a5b50 .concat8 [ 1 1 0 0], L_0x13a4c10, L_0x13a5840; +L_0x13a5c90 .part L_0x13a3d30, 4, 4; +L_0x13a5df0 .part L_0x13a5b50, 0, 1; +L_0x13a5fa0 .part L_0x13a5b50, 1, 1; +S_0x1212d60 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1212ba0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13a43d0/d .functor OR 1, L_0x13a4490, L_0x13a45f0, C4<0>, C4<0>; +L_0x13a43d0 .delay 1 (30000,30000,30000) L_0x13a43d0/d; +L_0x13a4820/d .functor OR 1, L_0x13a4930, L_0x13a4a90, C4<0>, C4<0>; +L_0x13a4820 .delay 1 (30000,30000,30000) L_0x13a4820/d; +L_0x13a4c10/d .functor OR 1, L_0x13a4c80, L_0x13a4e30, C4<0>, C4<0>; +L_0x13a4c10 .delay 1 (30000,30000,30000) L_0x13a4c10/d; +v0x1212fb0_0 .net *"_s0", 0 0, L_0x13a43d0; 1 drivers +v0x12130b0_0 .net *"_s10", 0 0, L_0x13a4930; 1 drivers +v0x1213190_0 .net *"_s12", 0 0, L_0x13a4a90; 1 drivers +v0x1213250_0 .net *"_s14", 0 0, L_0x13a4c80; 1 drivers +v0x1213330_0 .net *"_s16", 0 0, L_0x13a4e30; 1 drivers +v0x1213460_0 .net *"_s3", 0 0, L_0x13a4490; 1 drivers +v0x1213540_0 .net *"_s5", 0 0, L_0x13a45f0; 1 drivers +v0x1213620_0 .net *"_s6", 0 0, L_0x13a4820; 1 drivers +v0x1213700_0 .net "in", 3 0, L_0x13a4f20; 1 drivers +v0x1213870_0 .net "ors", 1 0, L_0x13a4730; 1 drivers +v0x1213950_0 .net "out", 0 0, L_0x13a4c10; 1 drivers +L_0x13a4490 .part L_0x13a4f20, 0, 1; +L_0x13a45f0 .part L_0x13a4f20, 1, 1; +L_0x13a4730 .concat8 [ 1 1 0 0], L_0x13a43d0, L_0x13a4820; +L_0x13a4930 .part L_0x13a4f20, 2, 1; +L_0x13a4a90 .part L_0x13a4f20, 3, 1; +L_0x13a4c80 .part L_0x13a4730, 0, 1; +L_0x13a4e30 .part L_0x13a4730, 1, 1; +S_0x1213a70 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1212ba0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13a5050/d .functor OR 1, L_0x13a50c0, L_0x13a5220, C4<0>, C4<0>; +L_0x13a5050 .delay 1 (30000,30000,30000) L_0x13a5050/d; +L_0x13a5450/d .functor OR 1, L_0x13a5560, L_0x13a56c0, C4<0>, C4<0>; +L_0x13a5450 .delay 1 (30000,30000,30000) L_0x13a5450/d; +L_0x13a5840/d .functor OR 1, L_0x13a58b0, L_0x13a5a60, C4<0>, C4<0>; +L_0x13a5840 .delay 1 (30000,30000,30000) L_0x13a5840/d; +v0x1213c30_0 .net *"_s0", 0 0, L_0x13a5050; 1 drivers +v0x1213d30_0 .net *"_s10", 0 0, L_0x13a5560; 1 drivers +v0x1213e10_0 .net *"_s12", 0 0, L_0x13a56c0; 1 drivers +v0x1213ed0_0 .net *"_s14", 0 0, L_0x13a58b0; 1 drivers +v0x1213fb0_0 .net *"_s16", 0 0, L_0x13a5a60; 1 drivers +v0x12140e0_0 .net *"_s3", 0 0, L_0x13a50c0; 1 drivers +v0x12141c0_0 .net *"_s5", 0 0, L_0x13a5220; 1 drivers +v0x12142a0_0 .net *"_s6", 0 0, L_0x13a5450; 1 drivers +v0x1214380_0 .net "in", 3 0, L_0x13a5c90; 1 drivers +v0x12144f0_0 .net "ors", 1 0, L_0x13a5360; 1 drivers +v0x12145d0_0 .net "out", 0 0, L_0x13a5840; 1 drivers +L_0x13a50c0 .part L_0x13a5c90, 0, 1; +L_0x13a5220 .part L_0x13a5c90, 1, 1; +L_0x13a5360 .concat8 [ 1 1 0 0], L_0x13a5050, L_0x13a5450; +L_0x13a5560 .part L_0x13a5c90, 2, 1; +L_0x13a56c0 .part L_0x13a5c90, 3, 1; +L_0x13a58b0 .part L_0x13a5360, 0, 1; +L_0x13a5a60 .part L_0x13a5360, 1, 1; +S_0x1214ee0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x120e010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x121a310_0 .net "ands", 7 0, L_0x13a02f0; 1 drivers +v0x121a420_0 .net "in", 7 0, L_0x139e270; alias, 1 drivers +v0x121a4e0_0 .net "out", 0 0, L_0x13a22f0; alias, 1 drivers +v0x121a5b0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1215130 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1214ee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1217870_0 .net "A", 7 0, L_0x139e270; alias, 1 drivers +v0x1217970_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1217a30_0 .net *"_s0", 0 0, L_0x139eb40; 1 drivers +v0x1217af0_0 .net *"_s12", 0 0, L_0x139f500; 1 drivers +v0x1217bd0_0 .net *"_s16", 0 0, L_0x139f860; 1 drivers +v0x1217d00_0 .net *"_s20", 0 0, L_0x139fc30; 1 drivers +v0x1217de0_0 .net *"_s24", 0 0, L_0x139ff60; 1 drivers +v0x1217ec0_0 .net *"_s28", 0 0, L_0x139fef0; 1 drivers +v0x1217fa0_0 .net *"_s4", 0 0, L_0x139eee0; 1 drivers +v0x1218110_0 .net *"_s8", 0 0, L_0x139f1f0; 1 drivers +v0x12181f0_0 .net "out", 7 0, L_0x13a02f0; alias, 1 drivers +L_0x139ec50 .part L_0x139e270, 0, 1; +L_0x139ee40 .part v0x127a150_0, 0, 1; +L_0x139efa0 .part L_0x139e270, 1, 1; +L_0x139f100 .part v0x127a150_0, 1, 1; +L_0x139f2b0 .part L_0x139e270, 2, 1; +L_0x139f410 .part v0x127a150_0, 2, 1; +L_0x139f5c0 .part L_0x139e270, 3, 1; +L_0x139f720 .part v0x127a150_0, 3, 1; +L_0x139f920 .part L_0x139e270, 4, 1; +L_0x139fb90 .part v0x127a150_0, 4, 1; +L_0x139fca0 .part L_0x139e270, 5, 1; +L_0x139fe00 .part v0x127a150_0, 5, 1; +L_0x13a0020 .part L_0x139e270, 6, 1; +L_0x13a0180 .part v0x127a150_0, 6, 1; +LS_0x13a02f0_0_0 .concat8 [ 1 1 1 1], L_0x139eb40, L_0x139eee0, L_0x139f1f0, L_0x139f500; +LS_0x13a02f0_0_4 .concat8 [ 1 1 1 1], L_0x139f860, L_0x139fc30, L_0x139ff60, L_0x139fef0; +L_0x13a02f0 .concat8 [ 4 4 0 0], LS_0x13a02f0_0_0, LS_0x13a02f0_0_4; +L_0x13a06b0 .part L_0x139e270, 7, 1; +L_0x13a08a0 .part v0x127a150_0, 7, 1; +S_0x1215370 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1215580 .param/l "i" 0 4 54, +C4<00>; +L_0x139eb40/d .functor AND 1, L_0x139ec50, L_0x139ee40, C4<1>, C4<1>; +L_0x139eb40 .delay 1 (30000,30000,30000) L_0x139eb40/d; +v0x1215660_0 .net *"_s0", 0 0, L_0x139ec50; 1 drivers +v0x1215740_0 .net *"_s1", 0 0, L_0x139ee40; 1 drivers +S_0x1215820 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1215a30 .param/l "i" 0 4 54, +C4<01>; +L_0x139eee0/d .functor AND 1, L_0x139efa0, L_0x139f100, C4<1>, C4<1>; +L_0x139eee0 .delay 1 (30000,30000,30000) L_0x139eee0/d; +v0x1215af0_0 .net *"_s0", 0 0, L_0x139efa0; 1 drivers +v0x1215bd0_0 .net *"_s1", 0 0, L_0x139f100; 1 drivers +S_0x1215cb0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1215ef0 .param/l "i" 0 4 54, +C4<010>; +L_0x139f1f0/d .functor AND 1, L_0x139f2b0, L_0x139f410, C4<1>, C4<1>; +L_0x139f1f0 .delay 1 (30000,30000,30000) L_0x139f1f0/d; +v0x1215f90_0 .net *"_s0", 0 0, L_0x139f2b0; 1 drivers +v0x1216070_0 .net *"_s1", 0 0, L_0x139f410; 1 drivers +S_0x1216150 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1216360 .param/l "i" 0 4 54, +C4<011>; +L_0x139f500/d .functor AND 1, L_0x139f5c0, L_0x139f720, C4<1>, C4<1>; +L_0x139f500 .delay 1 (30000,30000,30000) L_0x139f500/d; +v0x1216420_0 .net *"_s0", 0 0, L_0x139f5c0; 1 drivers +v0x1216500_0 .net *"_s1", 0 0, L_0x139f720; 1 drivers +S_0x12165e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1216840 .param/l "i" 0 4 54, +C4<0100>; +L_0x139f860/d .functor AND 1, L_0x139f920, L_0x139fb90, C4<1>, C4<1>; +L_0x139f860 .delay 1 (30000,30000,30000) L_0x139f860/d; +v0x1216900_0 .net *"_s0", 0 0, L_0x139f920; 1 drivers +v0x12169e0_0 .net *"_s1", 0 0, L_0x139fb90; 1 drivers +S_0x1216ac0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1216cd0 .param/l "i" 0 4 54, +C4<0101>; +L_0x139fc30/d .functor AND 1, L_0x139fca0, L_0x139fe00, C4<1>, C4<1>; +L_0x139fc30 .delay 1 (30000,30000,30000) L_0x139fc30/d; +v0x1216d90_0 .net *"_s0", 0 0, L_0x139fca0; 1 drivers +v0x1216e70_0 .net *"_s1", 0 0, L_0x139fe00; 1 drivers +S_0x1216f50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x1217160 .param/l "i" 0 4 54, +C4<0110>; +L_0x139ff60/d .functor AND 1, L_0x13a0020, L_0x13a0180, C4<1>, C4<1>; +L_0x139ff60 .delay 1 (30000,30000,30000) L_0x139ff60/d; +v0x1217220_0 .net *"_s0", 0 0, L_0x13a0020; 1 drivers +v0x1217300_0 .net *"_s1", 0 0, L_0x13a0180; 1 drivers +S_0x12173e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1215130; + .timescale -9 -12; +P_0x12175f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x139fef0/d .functor AND 1, L_0x13a06b0, L_0x13a08a0, C4<1>, C4<1>; +L_0x139fef0 .delay 1 (30000,30000,30000) L_0x139fef0/d; +v0x12176b0_0 .net *"_s0", 0 0, L_0x13a06b0; 1 drivers +v0x1217790_0 .net *"_s1", 0 0, L_0x13a08a0; 1 drivers +S_0x1218350 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1214ee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13a22f0/d .functor OR 1, L_0x13a23b0, L_0x13a2560, C4<0>, C4<0>; +L_0x13a22f0 .delay 1 (30000,30000,30000) L_0x13a22f0/d; +v0x1219ea0_0 .net *"_s10", 0 0, L_0x13a23b0; 1 drivers +v0x1219f80_0 .net *"_s12", 0 0, L_0x13a2560; 1 drivers +v0x121a060_0 .net "in", 7 0, L_0x13a02f0; alias, 1 drivers +v0x121a130_0 .net "ors", 1 0, L_0x13a2110; 1 drivers +v0x121a1f0_0 .net "out", 0 0, L_0x13a22f0; alias, 1 drivers +L_0x13a14e0 .part L_0x13a02f0, 0, 4; +L_0x13a2110 .concat8 [ 1 1 0 0], L_0x13a11d0, L_0x13a1e00; +L_0x13a2250 .part L_0x13a02f0, 4, 4; +L_0x13a23b0 .part L_0x13a2110, 0, 1; +L_0x13a2560 .part L_0x13a2110, 1, 1; +S_0x1218510 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1218350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13a0990/d .functor OR 1, L_0x13a0a50, L_0x13a0bb0, C4<0>, C4<0>; +L_0x13a0990 .delay 1 (30000,30000,30000) L_0x13a0990/d; +L_0x13a0de0/d .functor OR 1, L_0x13a0ef0, L_0x13a1050, C4<0>, C4<0>; +L_0x13a0de0 .delay 1 (30000,30000,30000) L_0x13a0de0/d; +L_0x13a11d0/d .functor OR 1, L_0x13a1240, L_0x13a13f0, C4<0>, C4<0>; +L_0x13a11d0 .delay 1 (30000,30000,30000) L_0x13a11d0/d; +v0x1218760_0 .net *"_s0", 0 0, L_0x13a0990; 1 drivers +v0x1218860_0 .net *"_s10", 0 0, L_0x13a0ef0; 1 drivers +v0x1218940_0 .net *"_s12", 0 0, L_0x13a1050; 1 drivers +v0x1218a00_0 .net *"_s14", 0 0, L_0x13a1240; 1 drivers +v0x1218ae0_0 .net *"_s16", 0 0, L_0x13a13f0; 1 drivers +v0x1218c10_0 .net *"_s3", 0 0, L_0x13a0a50; 1 drivers +v0x1218cf0_0 .net *"_s5", 0 0, L_0x13a0bb0; 1 drivers +v0x1218dd0_0 .net *"_s6", 0 0, L_0x13a0de0; 1 drivers +v0x1218eb0_0 .net "in", 3 0, L_0x13a14e0; 1 drivers +v0x1219020_0 .net "ors", 1 0, L_0x13a0cf0; 1 drivers +v0x1219100_0 .net "out", 0 0, L_0x13a11d0; 1 drivers +L_0x13a0a50 .part L_0x13a14e0, 0, 1; +L_0x13a0bb0 .part L_0x13a14e0, 1, 1; +L_0x13a0cf0 .concat8 [ 1 1 0 0], L_0x13a0990, L_0x13a0de0; +L_0x13a0ef0 .part L_0x13a14e0, 2, 1; +L_0x13a1050 .part L_0x13a14e0, 3, 1; +L_0x13a1240 .part L_0x13a0cf0, 0, 1; +L_0x13a13f0 .part L_0x13a0cf0, 1, 1; +S_0x1219220 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1218350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13a1610/d .functor OR 1, L_0x13a1680, L_0x13a17e0, C4<0>, C4<0>; +L_0x13a1610 .delay 1 (30000,30000,30000) L_0x13a1610/d; +L_0x13a1a10/d .functor OR 1, L_0x13a1b20, L_0x13a1c80, C4<0>, C4<0>; +L_0x13a1a10 .delay 1 (30000,30000,30000) L_0x13a1a10/d; +L_0x13a1e00/d .functor OR 1, L_0x13a1e70, L_0x13a2020, C4<0>, C4<0>; +L_0x13a1e00 .delay 1 (30000,30000,30000) L_0x13a1e00/d; +v0x12193e0_0 .net *"_s0", 0 0, L_0x13a1610; 1 drivers +v0x12194e0_0 .net *"_s10", 0 0, L_0x13a1b20; 1 drivers +v0x12195c0_0 .net *"_s12", 0 0, L_0x13a1c80; 1 drivers +v0x1219680_0 .net *"_s14", 0 0, L_0x13a1e70; 1 drivers +v0x1219760_0 .net *"_s16", 0 0, L_0x13a2020; 1 drivers +v0x1219890_0 .net *"_s3", 0 0, L_0x13a1680; 1 drivers +v0x1219970_0 .net *"_s5", 0 0, L_0x13a17e0; 1 drivers +v0x1219a50_0 .net *"_s6", 0 0, L_0x13a1a10; 1 drivers +v0x1219b30_0 .net "in", 3 0, L_0x13a2250; 1 drivers +v0x1219ca0_0 .net "ors", 1 0, L_0x13a1920; 1 drivers +v0x1219d80_0 .net "out", 0 0, L_0x13a1e00; 1 drivers +L_0x13a1680 .part L_0x13a2250, 0, 1; +L_0x13a17e0 .part L_0x13a2250, 1, 1; +L_0x13a1920 .concat8 [ 1 1 0 0], L_0x13a1610, L_0x13a1a10; +L_0x13a1b20 .part L_0x13a2250, 2, 1; +L_0x13a1c80 .part L_0x13a2250, 3, 1; +L_0x13a1e70 .part L_0x13a1920, 0, 1; +L_0x13a2020 .part L_0x13a1920, 1, 1; +S_0x121a690 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x120e010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x139d120/d .functor XNOR 1, L_0x13a6190, L_0x139bb30, C4<0>, C4<0>; +L_0x139d120 .delay 1 (20000,20000,20000) L_0x139d120/d; +L_0x139d2a0/d .functor AND 1, L_0x13a6190, L_0x139be10, C4<1>, C4<1>; +L_0x139d2a0 .delay 1 (30000,30000,30000) L_0x139d2a0/d; +L_0x139d400/d .functor AND 1, L_0x139d120, L_0x139bbd0, C4<1>, C4<1>; +L_0x139d400 .delay 1 (30000,30000,30000) L_0x139d400/d; +L_0x139d510/d .functor OR 1, L_0x139d400, L_0x139d2a0, C4<0>, C4<0>; +L_0x139d510 .delay 1 (30000,30000,30000) L_0x139d510/d; +v0x121a940_0 .net "a", 0 0, L_0x13a6190; alias, 1 drivers +v0x121aa30_0 .net "a_", 0 0, L_0x13913a0; alias, 1 drivers +v0x121aaf0_0 .net "b", 0 0, L_0x139bb30; alias, 1 drivers +v0x121abe0_0 .net "b_", 0 0, L_0x139be10; alias, 1 drivers +v0x121ac80_0 .net "carryin", 0 0, L_0x139bbd0; alias, 1 drivers +v0x121adc0_0 .net "eq", 0 0, L_0x139d120; 1 drivers +v0x121ae80_0 .net "lt", 0 0, L_0x139d2a0; 1 drivers +v0x121af40_0 .net "out", 0 0, L_0x139d510; 1 drivers +v0x121b000_0 .net "w0", 0 0, L_0x139d400; 1 drivers +S_0x121b250 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x120e010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x139cd00/d .functor OR 1, L_0x139c800, L_0x121c4b0, C4<0>, C4<0>; +L_0x139cd00 .delay 1 (30000,30000,30000) L_0x139cd00/d; +v0x121c040_0 .net "a", 0 0, L_0x13a6190; alias, 1 drivers +v0x121c190_0 .net "b", 0 0, L_0x139be10; alias, 1 drivers +v0x121c250_0 .net "c1", 0 0, L_0x139c800; 1 drivers +v0x121c2f0_0 .net "c2", 0 0, L_0x121c4b0; 1 drivers +v0x121c3c0_0 .net "carryin", 0 0, L_0x139bbd0; alias, 1 drivers +v0x121c540_0 .net "carryout", 0 0, L_0x139cd00; 1 drivers +v0x121c5e0_0 .net "s1", 0 0, L_0x139c740; 1 drivers +v0x121c680_0 .net "sum", 0 0, L_0x139c960; 1 drivers +S_0x121b4a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x121b250; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x139c740/d .functor XOR 1, L_0x13a6190, L_0x139be10, C4<0>, C4<0>; +L_0x139c740 .delay 1 (30000,30000,30000) L_0x139c740/d; +L_0x139c800/d .functor AND 1, L_0x13a6190, L_0x139be10, C4<1>, C4<1>; +L_0x139c800 .delay 1 (30000,30000,30000) L_0x139c800/d; +v0x121b700_0 .net "a", 0 0, L_0x13a6190; alias, 1 drivers +v0x121b7c0_0 .net "b", 0 0, L_0x139be10; alias, 1 drivers +v0x121b880_0 .net "carryout", 0 0, L_0x139c800; alias, 1 drivers +v0x121b920_0 .net "sum", 0 0, L_0x139c740; alias, 1 drivers +S_0x121ba50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x121b250; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x139c960/d .functor XOR 1, L_0x139c740, L_0x139bbd0, C4<0>, C4<0>; +L_0x139c960 .delay 1 (30000,30000,30000) L_0x139c960/d; +L_0x121c4b0/d .functor AND 1, L_0x139c740, L_0x139bbd0, C4<1>, C4<1>; +L_0x121c4b0 .delay 1 (30000,30000,30000) L_0x121c4b0/d; +v0x121bcb0_0 .net "a", 0 0, L_0x139c740; alias, 1 drivers +v0x121bd80_0 .net "b", 0 0, L_0x139bbd0; alias, 1 drivers +v0x121be20_0 .net "carryout", 0 0, L_0x121c4b0; alias, 1 drivers +v0x121bef0_0 .net "sum", 0 0, L_0x139c960; alias, 1 drivers +S_0x121e710 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x120dd40; + .timescale -9 -12; +L_0x2ac432889d38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889d80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x139e5b0/d .functor OR 1, L_0x2ac432889d38, L_0x2ac432889d80, C4<0>, C4<0>; +L_0x139e5b0 .delay 1 (30000,30000,30000) L_0x139e5b0/d; +v0x121e900_0 .net/2u *"_s0", 0 0, L_0x2ac432889d38; 1 drivers +v0x121e9e0_0 .net/2u *"_s2", 0 0, L_0x2ac432889d80; 1 drivers +S_0x121eac0 .scope generate, "alu_slices[28]" "alu_slices[28]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x121ecd0 .param/l "i" 0 3 39, +C4<011100>; +S_0x121ed90 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x121eac0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13a65a0/d .functor NOT 1, L_0x13b0a10, C4<0>, C4<0>, C4<0>; +L_0x13a65a0 .delay 1 (10000,10000,10000) L_0x13a65a0/d; +L_0x13a6660/d .functor NOT 1, L_0x13b0b70, C4<0>, C4<0>, C4<0>; +L_0x13a6660 .delay 1 (10000,10000,10000) L_0x13a6660/d; +L_0x13a76b0/d .functor XOR 1, L_0x13b0a10, L_0x13b0b70, C4<0>, C4<0>; +L_0x13a76b0 .delay 1 (30000,30000,30000) L_0x13a76b0/d; +L_0x2ac432889dc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889e10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a7770/d .functor OR 1, L_0x2ac432889dc8, L_0x2ac432889e10, C4<0>, C4<0>; +L_0x13a7770 .delay 1 (30000,30000,30000) L_0x13a7770/d; +L_0x2ac432889e58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889ea0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a7f10/d .functor OR 1, L_0x2ac432889e58, L_0x2ac432889ea0, C4<0>, C4<0>; +L_0x13a7f10 .delay 1 (30000,30000,30000) L_0x13a7f10/d; +L_0x13a8070/d .functor AND 1, L_0x13b0a10, L_0x13b0b70, C4<1>, C4<1>; +L_0x13a8070 .delay 1 (30000,30000,30000) L_0x13a8070/d; +L_0x2ac432889ee8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889f30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a8180/d .functor OR 1, L_0x2ac432889ee8, L_0x2ac432889f30, C4<0>, C4<0>; +L_0x13a8180 .delay 1 (30000,30000,30000) L_0x13a8180/d; +L_0x13a8380/d .functor NAND 1, L_0x13b0a10, L_0x13b0b70, C4<1>, C4<1>; +L_0x13a8380 .delay 1 (20000,20000,20000) L_0x13a8380/d; +L_0x2ac432889f78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac432889fc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a8490/d .functor OR 1, L_0x2ac432889f78, L_0x2ac432889fc0, C4<0>, C4<0>; +L_0x13a8490 .delay 1 (30000,30000,30000) L_0x13a8490/d; +L_0x13a8640/d .functor NOR 1, L_0x13b0a10, L_0x13b0b70, C4<0>, C4<0>; +L_0x13a8640 .delay 1 (20000,20000,20000) L_0x13a8640/d; +L_0x2ac43288a008 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a050 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a8910/d .functor OR 1, L_0x2ac43288a008, L_0x2ac43288a050, C4<0>, C4<0>; +L_0x13a8910 .delay 1 (30000,30000,30000) L_0x13a8910/d; +L_0x13a8d10/d .functor OR 1, L_0x13b0a10, L_0x13b0b70, C4<0>, C4<0>; +L_0x13a8d10 .delay 1 (30000,30000,30000) L_0x13a8d10/d; +L_0x2ac43288a098 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a0e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a91b0/d .functor OR 1, L_0x2ac43288a098, L_0x2ac43288a0e0, C4<0>, C4<0>; +L_0x13a91b0 .delay 1 (30000,30000,30000) L_0x13a91b0/d; +L_0x13b0910/d .functor NOT 1, L_0x13acb70, C4<0>, C4<0>, C4<0>; +L_0x13b0910 .delay 1 (10000,10000,10000) L_0x13b0910/d; +v0x122d4c0_0 .net "A", 0 0, L_0x13b0a10; 1 drivers +v0x122d580_0 .net "A_", 0 0, L_0x13a65a0; 1 drivers +v0x122d640_0 .net "B", 0 0, L_0x13b0b70; 1 drivers +v0x122d710_0 .net "B_", 0 0, L_0x13a6660; 1 drivers +v0x122d7b0_0 .net *"_s11", 0 0, L_0x13a7770; 1 drivers +v0x122d8a0_0 .net/2s *"_s13", 0 0, L_0x2ac432889dc8; 1 drivers +v0x122d960_0 .net/2s *"_s15", 0 0, L_0x2ac432889e10; 1 drivers +v0x122da40_0 .net *"_s19", 0 0, L_0x13a7f10; 1 drivers +v0x122db20_0 .net/2s *"_s21", 0 0, L_0x2ac432889e58; 1 drivers +v0x122dc90_0 .net/2s *"_s23", 0 0, L_0x2ac432889ea0; 1 drivers +v0x122dd70_0 .net *"_s25", 0 0, L_0x13a8070; 1 drivers +v0x122de50_0 .net *"_s28", 0 0, L_0x13a8180; 1 drivers +v0x122df30_0 .net/2s *"_s30", 0 0, L_0x2ac432889ee8; 1 drivers +v0x122e010_0 .net/2s *"_s32", 0 0, L_0x2ac432889f30; 1 drivers +v0x122e0f0_0 .net *"_s34", 0 0, L_0x13a8380; 1 drivers +v0x122e1d0_0 .net *"_s37", 0 0, L_0x13a8490; 1 drivers +v0x122e2b0_0 .net/2s *"_s39", 0 0, L_0x2ac432889f78; 1 drivers +v0x122e460_0 .net/2s *"_s41", 0 0, L_0x2ac432889fc0; 1 drivers +v0x122e500_0 .net *"_s43", 0 0, L_0x13a8640; 1 drivers +v0x122e5e0_0 .net *"_s46", 0 0, L_0x13a8910; 1 drivers +v0x122e6c0_0 .net/2s *"_s48", 0 0, L_0x2ac43288a008; 1 drivers +v0x122e7a0_0 .net/2s *"_s50", 0 0, L_0x2ac43288a050; 1 drivers +v0x122e880_0 .net *"_s52", 0 0, L_0x13a8d10; 1 drivers +v0x122e960_0 .net *"_s56", 0 0, L_0x13a91b0; 1 drivers +v0x122ea40_0 .net/2s *"_s59", 0 0, L_0x2ac43288a098; 1 drivers +v0x122eb20_0 .net/2s *"_s61", 0 0, L_0x2ac43288a0e0; 1 drivers +v0x122ec00_0 .net *"_s8", 0 0, L_0x13a76b0; 1 drivers +v0x122ece0_0 .net "carryin", 0 0, L_0x13a62f0; 1 drivers +v0x122ed80_0 .net "carryout", 0 0, L_0x13b05b0; 1 drivers +v0x122ee20_0 .net "carryouts", 7 0, L_0x13a8e20; 1 drivers +v0x122ef30_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x122eff0_0 .net "result", 0 0, L_0x13acb70; 1 drivers +v0x122f0e0_0 .net "results", 7 0, L_0x13a8ae0; 1 drivers +v0x122e3c0_0 .net "zero", 0 0, L_0x13b0910; 1 drivers +LS_0x13a8ae0_0_0 .concat8 [ 1 1 1 1], L_0x13a6b80, L_0x13a71b0, L_0x13a76b0, L_0x13a7f10; +LS_0x13a8ae0_0_4 .concat8 [ 1 1 1 1], L_0x13a8070, L_0x13a8380, L_0x13a8640, L_0x13a8d10; +L_0x13a8ae0 .concat8 [ 4 4 0 0], LS_0x13a8ae0_0_0, LS_0x13a8ae0_0_4; +LS_0x13a8e20_0_0 .concat8 [ 1 1 1 1], L_0x13a6e30, L_0x13a7550, L_0x13a7770, L_0x13a7d60; +LS_0x13a8e20_0_4 .concat8 [ 1 1 1 1], L_0x13a8180, L_0x13a8490, L_0x13a8910, L_0x13a91b0; +L_0x13a8e20 .concat8 [ 4 4 0 0], LS_0x13a8e20_0_0, LS_0x13a8e20_0_4; +S_0x121f010 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x121ed90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13a6e30/d .functor OR 1, L_0x13a6910, L_0x13a6cd0, C4<0>, C4<0>; +L_0x13a6e30 .delay 1 (30000,30000,30000) L_0x13a6e30/d; +v0x121fe40_0 .net "a", 0 0, L_0x13b0a10; alias, 1 drivers +v0x121ff00_0 .net "b", 0 0, L_0x13b0b70; alias, 1 drivers +v0x121ffd0_0 .net "c1", 0 0, L_0x13a6910; 1 drivers +v0x12200d0_0 .net "c2", 0 0, L_0x13a6cd0; 1 drivers +v0x12201a0_0 .net "carryin", 0 0, L_0x13a62f0; alias, 1 drivers +v0x1220290_0 .net "carryout", 0 0, L_0x13a6e30; 1 drivers +v0x1220330_0 .net "s1", 0 0, L_0x13a6850; 1 drivers +v0x1220420_0 .net "sum", 0 0, L_0x13a6b80; 1 drivers +S_0x121f280 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x121f010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13a6850/d .functor XOR 1, L_0x13b0a10, L_0x13b0b70, C4<0>, C4<0>; +L_0x13a6850 .delay 1 (30000,30000,30000) L_0x13a6850/d; +L_0x13a6910/d .functor AND 1, L_0x13b0a10, L_0x13b0b70, C4<1>, C4<1>; +L_0x13a6910 .delay 1 (30000,30000,30000) L_0x13a6910/d; +v0x121f4e0_0 .net "a", 0 0, L_0x13b0a10; alias, 1 drivers +v0x121f5c0_0 .net "b", 0 0, L_0x13b0b70; alias, 1 drivers +v0x121f680_0 .net "carryout", 0 0, L_0x13a6910; alias, 1 drivers +v0x121f720_0 .net "sum", 0 0, L_0x13a6850; alias, 1 drivers +S_0x121f860 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x121f010; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13a6b80/d .functor XOR 1, L_0x13a6850, L_0x13a62f0, C4<0>, C4<0>; +L_0x13a6b80 .delay 1 (30000,30000,30000) L_0x13a6b80/d; +L_0x13a6cd0/d .functor AND 1, L_0x13a6850, L_0x13a62f0, C4<1>, C4<1>; +L_0x13a6cd0 .delay 1 (30000,30000,30000) L_0x13a6cd0/d; +v0x121fac0_0 .net "a", 0 0, L_0x13a6850; alias, 1 drivers +v0x121fb60_0 .net "b", 0 0, L_0x13a62f0; alias, 1 drivers +v0x121fc00_0 .net "carryout", 0 0, L_0x13a6cd0; alias, 1 drivers +v0x121fcd0_0 .net "sum", 0 0, L_0x13a6b80; alias, 1 drivers +S_0x12204f0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x121ed90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x12258e0_0 .net "ands", 7 0, L_0x13ae5b0; 1 drivers +v0x12259f0_0 .net "in", 7 0, L_0x13a8e20; alias, 1 drivers +v0x1225ab0_0 .net "out", 0 0, L_0x13b05b0; alias, 1 drivers +v0x1225b80_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1220710 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x12204f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1222e40_0 .net "A", 7 0, L_0x13a8e20; alias, 1 drivers +v0x1222f40_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1222fe0_0 .net *"_s0", 0 0, L_0x13aced0; 1 drivers +v0x12230f0_0 .net *"_s12", 0 0, L_0x13ad840; 1 drivers +v0x12231d0_0 .net *"_s16", 0 0, L_0x13adba0; 1 drivers +v0x1223300_0 .net *"_s20", 0 0, L_0x13adf70; 1 drivers +v0x12233e0_0 .net *"_s24", 0 0, L_0x13ae2a0; 1 drivers +v0x12234c0_0 .net *"_s28", 0 0, L_0x13ae230; 1 drivers +v0x12235a0_0 .net *"_s4", 0 0, L_0x13ad220; 1 drivers +v0x1223710_0 .net *"_s8", 0 0, L_0x13ad530; 1 drivers +v0x12237f0_0 .net "out", 7 0, L_0x13ae5b0; alias, 1 drivers +L_0x13acf90 .part L_0x13a8e20, 0, 1; +L_0x13ad180 .part v0x127a150_0, 0, 1; +L_0x13ad2e0 .part L_0x13a8e20, 1, 1; +L_0x13ad440 .part v0x127a150_0, 1, 1; +L_0x13ad5f0 .part L_0x13a8e20, 2, 1; +L_0x13ad750 .part v0x127a150_0, 2, 1; +L_0x13ad900 .part L_0x13a8e20, 3, 1; +L_0x13ada60 .part v0x127a150_0, 3, 1; +L_0x13adc60 .part L_0x13a8e20, 4, 1; +L_0x13aded0 .part v0x127a150_0, 4, 1; +L_0x13adfe0 .part L_0x13a8e20, 5, 1; +L_0x13ae140 .part v0x127a150_0, 5, 1; +L_0x13ae360 .part L_0x13a8e20, 6, 1; +L_0x13ae4c0 .part v0x127a150_0, 6, 1; +LS_0x13ae5b0_0_0 .concat8 [ 1 1 1 1], L_0x13aced0, L_0x13ad220, L_0x13ad530, L_0x13ad840; +LS_0x13ae5b0_0_4 .concat8 [ 1 1 1 1], L_0x13adba0, L_0x13adf70, L_0x13ae2a0, L_0x13ae230; +L_0x13ae5b0 .concat8 [ 4 4 0 0], LS_0x13ae5b0_0_0, LS_0x13ae5b0_0_4; +L_0x13ae970 .part L_0x13a8e20, 7, 1; +L_0x13aeb60 .part v0x127a150_0, 7, 1; +S_0x1220970 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x1220b80 .param/l "i" 0 4 54, +C4<00>; +L_0x13aced0/d .functor AND 1, L_0x13acf90, L_0x13ad180, C4<1>, C4<1>; +L_0x13aced0 .delay 1 (30000,30000,30000) L_0x13aced0/d; +v0x1220c60_0 .net *"_s0", 0 0, L_0x13acf90; 1 drivers +v0x1220d40_0 .net *"_s1", 0 0, L_0x13ad180; 1 drivers +S_0x1220e20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x1221030 .param/l "i" 0 4 54, +C4<01>; +L_0x13ad220/d .functor AND 1, L_0x13ad2e0, L_0x13ad440, C4<1>, C4<1>; +L_0x13ad220 .delay 1 (30000,30000,30000) L_0x13ad220/d; +v0x12210f0_0 .net *"_s0", 0 0, L_0x13ad2e0; 1 drivers +v0x12211d0_0 .net *"_s1", 0 0, L_0x13ad440; 1 drivers +S_0x12212b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x12214c0 .param/l "i" 0 4 54, +C4<010>; +L_0x13ad530/d .functor AND 1, L_0x13ad5f0, L_0x13ad750, C4<1>, C4<1>; +L_0x13ad530 .delay 1 (30000,30000,30000) L_0x13ad530/d; +v0x1221560_0 .net *"_s0", 0 0, L_0x13ad5f0; 1 drivers +v0x1221640_0 .net *"_s1", 0 0, L_0x13ad750; 1 drivers +S_0x1221720 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x1221930 .param/l "i" 0 4 54, +C4<011>; +L_0x13ad840/d .functor AND 1, L_0x13ad900, L_0x13ada60, C4<1>, C4<1>; +L_0x13ad840 .delay 1 (30000,30000,30000) L_0x13ad840/d; +v0x12219f0_0 .net *"_s0", 0 0, L_0x13ad900; 1 drivers +v0x1221ad0_0 .net *"_s1", 0 0, L_0x13ada60; 1 drivers +S_0x1221bb0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x1221e10 .param/l "i" 0 4 54, +C4<0100>; +L_0x13adba0/d .functor AND 1, L_0x13adc60, L_0x13aded0, C4<1>, C4<1>; +L_0x13adba0 .delay 1 (30000,30000,30000) L_0x13adba0/d; +v0x1221ed0_0 .net *"_s0", 0 0, L_0x13adc60; 1 drivers +v0x1221fb0_0 .net *"_s1", 0 0, L_0x13aded0; 1 drivers +S_0x1222090 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x12222a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13adf70/d .functor AND 1, L_0x13adfe0, L_0x13ae140, C4<1>, C4<1>; +L_0x13adf70 .delay 1 (30000,30000,30000) L_0x13adf70/d; +v0x1222360_0 .net *"_s0", 0 0, L_0x13adfe0; 1 drivers +v0x1222440_0 .net *"_s1", 0 0, L_0x13ae140; 1 drivers +S_0x1222520 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x1222730 .param/l "i" 0 4 54, +C4<0110>; +L_0x13ae2a0/d .functor AND 1, L_0x13ae360, L_0x13ae4c0, C4<1>, C4<1>; +L_0x13ae2a0 .delay 1 (30000,30000,30000) L_0x13ae2a0/d; +v0x12227f0_0 .net *"_s0", 0 0, L_0x13ae360; 1 drivers +v0x12228d0_0 .net *"_s1", 0 0, L_0x13ae4c0; 1 drivers +S_0x12229b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1220710; + .timescale -9 -12; +P_0x1222bc0 .param/l "i" 0 4 54, +C4<0111>; +L_0x13ae230/d .functor AND 1, L_0x13ae970, L_0x13aeb60, C4<1>, C4<1>; +L_0x13ae230 .delay 1 (30000,30000,30000) L_0x13ae230/d; +v0x1222c80_0 .net *"_s0", 0 0, L_0x13ae970; 1 drivers +v0x1222d60_0 .net *"_s1", 0 0, L_0x13aeb60; 1 drivers +S_0x1223950 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x12204f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13b05b0/d .functor OR 1, L_0x13b0670, L_0x13b0820, C4<0>, C4<0>; +L_0x13b05b0 .delay 1 (30000,30000,30000) L_0x13b05b0/d; +v0x12254a0_0 .net *"_s10", 0 0, L_0x13b0670; 1 drivers +v0x1225580_0 .net *"_s12", 0 0, L_0x13b0820; 1 drivers +v0x1225660_0 .net "in", 7 0, L_0x13ae5b0; alias, 1 drivers +v0x1225700_0 .net "ors", 1 0, L_0x13b03d0; 1 drivers +v0x12257c0_0 .net "out", 0 0, L_0x13b05b0; alias, 1 drivers +L_0x13af7a0 .part L_0x13ae5b0, 0, 4; +L_0x13b03d0 .concat8 [ 1 1 0 0], L_0x13af490, L_0x13b00c0; +L_0x13b0510 .part L_0x13ae5b0, 4, 4; +L_0x13b0670 .part L_0x13b03d0, 0, 1; +L_0x13b0820 .part L_0x13b03d0, 1, 1; +S_0x1223b10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1223950; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13aec50/d .functor OR 1, L_0x13aed10, L_0x13aee70, C4<0>, C4<0>; +L_0x13aec50 .delay 1 (30000,30000,30000) L_0x13aec50/d; +L_0x13af0a0/d .functor OR 1, L_0x13af1b0, L_0x13af310, C4<0>, C4<0>; +L_0x13af0a0 .delay 1 (30000,30000,30000) L_0x13af0a0/d; +L_0x13af490/d .functor OR 1, L_0x13af500, L_0x13af6b0, C4<0>, C4<0>; +L_0x13af490 .delay 1 (30000,30000,30000) L_0x13af490/d; +v0x1223d60_0 .net *"_s0", 0 0, L_0x13aec50; 1 drivers +v0x1223e60_0 .net *"_s10", 0 0, L_0x13af1b0; 1 drivers +v0x1223f40_0 .net *"_s12", 0 0, L_0x13af310; 1 drivers +v0x1224000_0 .net *"_s14", 0 0, L_0x13af500; 1 drivers +v0x12240e0_0 .net *"_s16", 0 0, L_0x13af6b0; 1 drivers +v0x1224210_0 .net *"_s3", 0 0, L_0x13aed10; 1 drivers +v0x12242f0_0 .net *"_s5", 0 0, L_0x13aee70; 1 drivers +v0x12243d0_0 .net *"_s6", 0 0, L_0x13af0a0; 1 drivers +v0x12244b0_0 .net "in", 3 0, L_0x13af7a0; 1 drivers +v0x1224620_0 .net "ors", 1 0, L_0x13aefb0; 1 drivers +v0x1224700_0 .net "out", 0 0, L_0x13af490; 1 drivers +L_0x13aed10 .part L_0x13af7a0, 0, 1; +L_0x13aee70 .part L_0x13af7a0, 1, 1; +L_0x13aefb0 .concat8 [ 1 1 0 0], L_0x13aec50, L_0x13af0a0; +L_0x13af1b0 .part L_0x13af7a0, 2, 1; +L_0x13af310 .part L_0x13af7a0, 3, 1; +L_0x13af500 .part L_0x13aefb0, 0, 1; +L_0x13af6b0 .part L_0x13aefb0, 1, 1; +S_0x1224820 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1223950; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13af8d0/d .functor OR 1, L_0x13af940, L_0x13afaa0, C4<0>, C4<0>; +L_0x13af8d0 .delay 1 (30000,30000,30000) L_0x13af8d0/d; +L_0x13afcd0/d .functor OR 1, L_0x13afde0, L_0x13aff40, C4<0>, C4<0>; +L_0x13afcd0 .delay 1 (30000,30000,30000) L_0x13afcd0/d; +L_0x13b00c0/d .functor OR 1, L_0x13b0130, L_0x13b02e0, C4<0>, C4<0>; +L_0x13b00c0 .delay 1 (30000,30000,30000) L_0x13b00c0/d; +v0x12249e0_0 .net *"_s0", 0 0, L_0x13af8d0; 1 drivers +v0x1224ae0_0 .net *"_s10", 0 0, L_0x13afde0; 1 drivers +v0x1224bc0_0 .net *"_s12", 0 0, L_0x13aff40; 1 drivers +v0x1224c80_0 .net *"_s14", 0 0, L_0x13b0130; 1 drivers +v0x1224d60_0 .net *"_s16", 0 0, L_0x13b02e0; 1 drivers +v0x1224e90_0 .net *"_s3", 0 0, L_0x13af940; 1 drivers +v0x1224f70_0 .net *"_s5", 0 0, L_0x13afaa0; 1 drivers +v0x1225050_0 .net *"_s6", 0 0, L_0x13afcd0; 1 drivers +v0x1225130_0 .net "in", 3 0, L_0x13b0510; 1 drivers +v0x12252a0_0 .net "ors", 1 0, L_0x13afbe0; 1 drivers +v0x1225380_0 .net "out", 0 0, L_0x13b00c0; 1 drivers +L_0x13af940 .part L_0x13b0510, 0, 1; +L_0x13afaa0 .part L_0x13b0510, 1, 1; +L_0x13afbe0 .concat8 [ 1 1 0 0], L_0x13af8d0, L_0x13afcd0; +L_0x13afde0 .part L_0x13b0510, 2, 1; +L_0x13aff40 .part L_0x13b0510, 3, 1; +L_0x13b0130 .part L_0x13afbe0, 0, 1; +L_0x13b02e0 .part L_0x13afbe0, 1, 1; +S_0x1225c60 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x121ed90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x122b090_0 .net "ands", 7 0, L_0x13aab70; 1 drivers +v0x122b1a0_0 .net "in", 7 0, L_0x13a8ae0; alias, 1 drivers +v0x122b260_0 .net "out", 0 0, L_0x13acb70; alias, 1 drivers +v0x122b330_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1225eb0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1225c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x12285f0_0 .net "A", 7 0, L_0x13a8ae0; alias, 1 drivers +v0x12286f0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x12287b0_0 .net *"_s0", 0 0, L_0x13a9360; 1 drivers +v0x1228870_0 .net *"_s12", 0 0, L_0x13a9d20; 1 drivers +v0x1228950_0 .net *"_s16", 0 0, L_0x13aa080; 1 drivers +v0x1228a80_0 .net *"_s20", 0 0, L_0x13aa4b0; 1 drivers +v0x1228b60_0 .net *"_s24", 0 0, L_0x13aa7e0; 1 drivers +v0x1228c40_0 .net *"_s28", 0 0, L_0x13aa770; 1 drivers +v0x1228d20_0 .net *"_s4", 0 0, L_0x13a9700; 1 drivers +v0x1228e90_0 .net *"_s8", 0 0, L_0x13a9a10; 1 drivers +v0x1228f70_0 .net "out", 7 0, L_0x13aab70; alias, 1 drivers +L_0x13a9470 .part L_0x13a8ae0, 0, 1; +L_0x13a9660 .part v0x127a150_0, 0, 1; +L_0x13a97c0 .part L_0x13a8ae0, 1, 1; +L_0x13a9920 .part v0x127a150_0, 1, 1; +L_0x13a9ad0 .part L_0x13a8ae0, 2, 1; +L_0x13a9c30 .part v0x127a150_0, 2, 1; +L_0x13a9de0 .part L_0x13a8ae0, 3, 1; +L_0x13a9f40 .part v0x127a150_0, 3, 1; +L_0x13aa140 .part L_0x13a8ae0, 4, 1; +L_0x13aa3b0 .part v0x127a150_0, 4, 1; +L_0x13aa520 .part L_0x13a8ae0, 5, 1; +L_0x13aa680 .part v0x127a150_0, 5, 1; +L_0x13aa8a0 .part L_0x13a8ae0, 6, 1; +L_0x13aaa00 .part v0x127a150_0, 6, 1; +LS_0x13aab70_0_0 .concat8 [ 1 1 1 1], L_0x13a9360, L_0x13a9700, L_0x13a9a10, L_0x13a9d20; +LS_0x13aab70_0_4 .concat8 [ 1 1 1 1], L_0x13aa080, L_0x13aa4b0, L_0x13aa7e0, L_0x13aa770; +L_0x13aab70 .concat8 [ 4 4 0 0], LS_0x13aab70_0_0, LS_0x13aab70_0_4; +L_0x13aaf30 .part L_0x13a8ae0, 7, 1; +L_0x13ab120 .part v0x127a150_0, 7, 1; +S_0x12260f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x1226300 .param/l "i" 0 4 54, +C4<00>; +L_0x13a9360/d .functor AND 1, L_0x13a9470, L_0x13a9660, C4<1>, C4<1>; +L_0x13a9360 .delay 1 (30000,30000,30000) L_0x13a9360/d; +v0x12263e0_0 .net *"_s0", 0 0, L_0x13a9470; 1 drivers +v0x12264c0_0 .net *"_s1", 0 0, L_0x13a9660; 1 drivers +S_0x12265a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x12267b0 .param/l "i" 0 4 54, +C4<01>; +L_0x13a9700/d .functor AND 1, L_0x13a97c0, L_0x13a9920, C4<1>, C4<1>; +L_0x13a9700 .delay 1 (30000,30000,30000) L_0x13a9700/d; +v0x1226870_0 .net *"_s0", 0 0, L_0x13a97c0; 1 drivers +v0x1226950_0 .net *"_s1", 0 0, L_0x13a9920; 1 drivers +S_0x1226a30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x1226c70 .param/l "i" 0 4 54, +C4<010>; +L_0x13a9a10/d .functor AND 1, L_0x13a9ad0, L_0x13a9c30, C4<1>, C4<1>; +L_0x13a9a10 .delay 1 (30000,30000,30000) L_0x13a9a10/d; +v0x1226d10_0 .net *"_s0", 0 0, L_0x13a9ad0; 1 drivers +v0x1226df0_0 .net *"_s1", 0 0, L_0x13a9c30; 1 drivers +S_0x1226ed0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x12270e0 .param/l "i" 0 4 54, +C4<011>; +L_0x13a9d20/d .functor AND 1, L_0x13a9de0, L_0x13a9f40, C4<1>, C4<1>; +L_0x13a9d20 .delay 1 (30000,30000,30000) L_0x13a9d20/d; +v0x12271a0_0 .net *"_s0", 0 0, L_0x13a9de0; 1 drivers +v0x1227280_0 .net *"_s1", 0 0, L_0x13a9f40; 1 drivers +S_0x1227360 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x12275c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x13aa080/d .functor AND 1, L_0x13aa140, L_0x13aa3b0, C4<1>, C4<1>; +L_0x13aa080 .delay 1 (30000,30000,30000) L_0x13aa080/d; +v0x1227680_0 .net *"_s0", 0 0, L_0x13aa140; 1 drivers +v0x1227760_0 .net *"_s1", 0 0, L_0x13aa3b0; 1 drivers +S_0x1227840 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x1227a50 .param/l "i" 0 4 54, +C4<0101>; +L_0x13aa4b0/d .functor AND 1, L_0x13aa520, L_0x13aa680, C4<1>, C4<1>; +L_0x13aa4b0 .delay 1 (30000,30000,30000) L_0x13aa4b0/d; +v0x1227b10_0 .net *"_s0", 0 0, L_0x13aa520; 1 drivers +v0x1227bf0_0 .net *"_s1", 0 0, L_0x13aa680; 1 drivers +S_0x1227cd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x1227ee0 .param/l "i" 0 4 54, +C4<0110>; +L_0x13aa7e0/d .functor AND 1, L_0x13aa8a0, L_0x13aaa00, C4<1>, C4<1>; +L_0x13aa7e0 .delay 1 (30000,30000,30000) L_0x13aa7e0/d; +v0x1227fa0_0 .net *"_s0", 0 0, L_0x13aa8a0; 1 drivers +v0x1228080_0 .net *"_s1", 0 0, L_0x13aaa00; 1 drivers +S_0x1228160 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1225eb0; + .timescale -9 -12; +P_0x1228370 .param/l "i" 0 4 54, +C4<0111>; +L_0x13aa770/d .functor AND 1, L_0x13aaf30, L_0x13ab120, C4<1>, C4<1>; +L_0x13aa770 .delay 1 (30000,30000,30000) L_0x13aa770/d; +v0x1228430_0 .net *"_s0", 0 0, L_0x13aaf30; 1 drivers +v0x1228510_0 .net *"_s1", 0 0, L_0x13ab120; 1 drivers +S_0x12290d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1225c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13acb70/d .functor OR 1, L_0x13acc30, L_0x13acde0, C4<0>, C4<0>; +L_0x13acb70 .delay 1 (30000,30000,30000) L_0x13acb70/d; +v0x122ac20_0 .net *"_s10", 0 0, L_0x13acc30; 1 drivers +v0x122ad00_0 .net *"_s12", 0 0, L_0x13acde0; 1 drivers +v0x122ade0_0 .net "in", 7 0, L_0x13aab70; alias, 1 drivers +v0x122aeb0_0 .net "ors", 1 0, L_0x13ac990; 1 drivers +v0x122af70_0 .net "out", 0 0, L_0x13acb70; alias, 1 drivers +L_0x13abd60 .part L_0x13aab70, 0, 4; +L_0x13ac990 .concat8 [ 1 1 0 0], L_0x13aba50, L_0x13ac680; +L_0x13acad0 .part L_0x13aab70, 4, 4; +L_0x13acc30 .part L_0x13ac990, 0, 1; +L_0x13acde0 .part L_0x13ac990, 1, 1; +S_0x1229290 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x12290d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13ab210/d .functor OR 1, L_0x13ab2d0, L_0x13ab430, C4<0>, C4<0>; +L_0x13ab210 .delay 1 (30000,30000,30000) L_0x13ab210/d; +L_0x13ab660/d .functor OR 1, L_0x13ab770, L_0x13ab8d0, C4<0>, C4<0>; +L_0x13ab660 .delay 1 (30000,30000,30000) L_0x13ab660/d; +L_0x13aba50/d .functor OR 1, L_0x13abac0, L_0x13abc70, C4<0>, C4<0>; +L_0x13aba50 .delay 1 (30000,30000,30000) L_0x13aba50/d; +v0x12294e0_0 .net *"_s0", 0 0, L_0x13ab210; 1 drivers +v0x12295e0_0 .net *"_s10", 0 0, L_0x13ab770; 1 drivers +v0x12296c0_0 .net *"_s12", 0 0, L_0x13ab8d0; 1 drivers +v0x1229780_0 .net *"_s14", 0 0, L_0x13abac0; 1 drivers +v0x1229860_0 .net *"_s16", 0 0, L_0x13abc70; 1 drivers +v0x1229990_0 .net *"_s3", 0 0, L_0x13ab2d0; 1 drivers +v0x1229a70_0 .net *"_s5", 0 0, L_0x13ab430; 1 drivers +v0x1229b50_0 .net *"_s6", 0 0, L_0x13ab660; 1 drivers +v0x1229c30_0 .net "in", 3 0, L_0x13abd60; 1 drivers +v0x1229da0_0 .net "ors", 1 0, L_0x13ab570; 1 drivers +v0x1229e80_0 .net "out", 0 0, L_0x13aba50; 1 drivers +L_0x13ab2d0 .part L_0x13abd60, 0, 1; +L_0x13ab430 .part L_0x13abd60, 1, 1; +L_0x13ab570 .concat8 [ 1 1 0 0], L_0x13ab210, L_0x13ab660; +L_0x13ab770 .part L_0x13abd60, 2, 1; +L_0x13ab8d0 .part L_0x13abd60, 3, 1; +L_0x13abac0 .part L_0x13ab570, 0, 1; +L_0x13abc70 .part L_0x13ab570, 1, 1; +S_0x1229fa0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x12290d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13abe90/d .functor OR 1, L_0x13abf00, L_0x13ac060, C4<0>, C4<0>; +L_0x13abe90 .delay 1 (30000,30000,30000) L_0x13abe90/d; +L_0x13ac290/d .functor OR 1, L_0x13ac3a0, L_0x13ac500, C4<0>, C4<0>; +L_0x13ac290 .delay 1 (30000,30000,30000) L_0x13ac290/d; +L_0x13ac680/d .functor OR 1, L_0x13ac6f0, L_0x13ac8a0, C4<0>, C4<0>; +L_0x13ac680 .delay 1 (30000,30000,30000) L_0x13ac680/d; +v0x122a160_0 .net *"_s0", 0 0, L_0x13abe90; 1 drivers +v0x122a260_0 .net *"_s10", 0 0, L_0x13ac3a0; 1 drivers +v0x122a340_0 .net *"_s12", 0 0, L_0x13ac500; 1 drivers +v0x122a400_0 .net *"_s14", 0 0, L_0x13ac6f0; 1 drivers +v0x122a4e0_0 .net *"_s16", 0 0, L_0x13ac8a0; 1 drivers +v0x122a610_0 .net *"_s3", 0 0, L_0x13abf00; 1 drivers +v0x122a6f0_0 .net *"_s5", 0 0, L_0x13ac060; 1 drivers +v0x122a7d0_0 .net *"_s6", 0 0, L_0x13ac290; 1 drivers +v0x122a8b0_0 .net "in", 3 0, L_0x13acad0; 1 drivers +v0x122aa20_0 .net "ors", 1 0, L_0x13ac1a0; 1 drivers +v0x122ab00_0 .net "out", 0 0, L_0x13ac680; 1 drivers +L_0x13abf00 .part L_0x13acad0, 0, 1; +L_0x13ac060 .part L_0x13acad0, 1, 1; +L_0x13ac1a0 .concat8 [ 1 1 0 0], L_0x13abe90, L_0x13ac290; +L_0x13ac3a0 .part L_0x13acad0, 2, 1; +L_0x13ac500 .part L_0x13acad0, 3, 1; +L_0x13ac6f0 .part L_0x13ac1a0, 0, 1; +L_0x13ac8a0 .part L_0x13ac1a0, 1, 1; +S_0x122b410 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x121ed90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x13a7970/d .functor XNOR 1, L_0x13b0a10, L_0x13b0b70, C4<0>, C4<0>; +L_0x13a7970 .delay 1 (20000,20000,20000) L_0x13a7970/d; +L_0x13a7af0/d .functor AND 1, L_0x13b0a10, L_0x13a6660, C4<1>, C4<1>; +L_0x13a7af0 .delay 1 (30000,30000,30000) L_0x13a7af0/d; +L_0x13a7c50/d .functor AND 1, L_0x13a7970, L_0x13a62f0, C4<1>, C4<1>; +L_0x13a7c50 .delay 1 (30000,30000,30000) L_0x13a7c50/d; +L_0x13a7d60/d .functor OR 1, L_0x13a7c50, L_0x13a7af0, C4<0>, C4<0>; +L_0x13a7d60 .delay 1 (30000,30000,30000) L_0x13a7d60/d; +v0x122b6c0_0 .net "a", 0 0, L_0x13b0a10; alias, 1 drivers +v0x122b7b0_0 .net "a_", 0 0, L_0x13a65a0; alias, 1 drivers +v0x122b870_0 .net "b", 0 0, L_0x13b0b70; alias, 1 drivers +v0x122b960_0 .net "b_", 0 0, L_0x13a6660; alias, 1 drivers +v0x122ba00_0 .net "carryin", 0 0, L_0x13a62f0; alias, 1 drivers +v0x122bb40_0 .net "eq", 0 0, L_0x13a7970; 1 drivers +v0x122bc00_0 .net "lt", 0 0, L_0x13a7af0; 1 drivers +v0x122bcc0_0 .net "out", 0 0, L_0x13a7d60; 1 drivers +v0x122bd80_0 .net "w0", 0 0, L_0x13a7c50; 1 drivers +S_0x122bfd0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x121ed90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13a7550/d .functor OR 1, L_0x13a7050, L_0x122d230, C4<0>, C4<0>; +L_0x13a7550 .delay 1 (30000,30000,30000) L_0x13a7550/d; +v0x122cdc0_0 .net "a", 0 0, L_0x13b0a10; alias, 1 drivers +v0x122cf10_0 .net "b", 0 0, L_0x13a6660; alias, 1 drivers +v0x122cfd0_0 .net "c1", 0 0, L_0x13a7050; 1 drivers +v0x122d070_0 .net "c2", 0 0, L_0x122d230; 1 drivers +v0x122d140_0 .net "carryin", 0 0, L_0x13a62f0; alias, 1 drivers +v0x122d2c0_0 .net "carryout", 0 0, L_0x13a7550; 1 drivers +v0x122d360_0 .net "s1", 0 0, L_0x13a6f90; 1 drivers +v0x122d400_0 .net "sum", 0 0, L_0x13a71b0; 1 drivers +S_0x122c220 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x122bfd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13a6f90/d .functor XOR 1, L_0x13b0a10, L_0x13a6660, C4<0>, C4<0>; +L_0x13a6f90 .delay 1 (30000,30000,30000) L_0x13a6f90/d; +L_0x13a7050/d .functor AND 1, L_0x13b0a10, L_0x13a6660, C4<1>, C4<1>; +L_0x13a7050 .delay 1 (30000,30000,30000) L_0x13a7050/d; +v0x122c480_0 .net "a", 0 0, L_0x13b0a10; alias, 1 drivers +v0x122c540_0 .net "b", 0 0, L_0x13a6660; alias, 1 drivers +v0x122c600_0 .net "carryout", 0 0, L_0x13a7050; alias, 1 drivers +v0x122c6a0_0 .net "sum", 0 0, L_0x13a6f90; alias, 1 drivers +S_0x122c7d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x122bfd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13a71b0/d .functor XOR 1, L_0x13a6f90, L_0x13a62f0, C4<0>, C4<0>; +L_0x13a71b0 .delay 1 (30000,30000,30000) L_0x13a71b0/d; +L_0x122d230/d .functor AND 1, L_0x13a6f90, L_0x13a62f0, C4<1>, C4<1>; +L_0x122d230 .delay 1 (30000,30000,30000) L_0x122d230/d; +v0x122ca30_0 .net "a", 0 0, L_0x13a6f90; alias, 1 drivers +v0x122cb00_0 .net "b", 0 0, L_0x13a62f0; alias, 1 drivers +v0x122cba0_0 .net "carryout", 0 0, L_0x122d230; alias, 1 drivers +v0x122cc70_0 .net "sum", 0 0, L_0x13a71b0; alias, 1 drivers +S_0x122f490 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x121eac0; + .timescale -9 -12; +L_0x2ac43288a128 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a170 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13a6b10/d .functor OR 1, L_0x2ac43288a128, L_0x2ac43288a170, C4<0>, C4<0>; +L_0x13a6b10 .delay 1 (30000,30000,30000) L_0x13a6b10/d; +v0x122f680_0 .net/2u *"_s0", 0 0, L_0x2ac43288a128; 1 drivers +v0x122f760_0 .net/2u *"_s2", 0 0, L_0x2ac43288a170; 1 drivers +S_0x122f840 .scope generate, "alu_slices[29]" "alu_slices[29]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x122fa50 .param/l "i" 0 3 39, +C4<011101>; +S_0x122fb10 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x122f840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13a63e0/d .functor NOT 1, L_0x13bb230, C4<0>, C4<0>, C4<0>; +L_0x13a63e0 .delay 1 (10000,10000,10000) L_0x13a63e0/d; +L_0x13b0ed0/d .functor NOT 1, L_0x13b0c10, C4<0>, C4<0>, C4<0>; +L_0x13b0ed0 .delay 1 (10000,10000,10000) L_0x13b0ed0/d; +L_0x13b1e80/d .functor XOR 1, L_0x13bb230, L_0x13b0c10, C4<0>, C4<0>; +L_0x13b1e80 .delay 1 (30000,30000,30000) L_0x13b1e80/d; +L_0x2ac43288a1b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a200 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b1f40/d .functor OR 1, L_0x2ac43288a1b8, L_0x2ac43288a200, C4<0>, C4<0>; +L_0x13b1f40 .delay 1 (30000,30000,30000) L_0x13b1f40/d; +L_0x2ac43288a248 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a290 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b26e0/d .functor OR 1, L_0x2ac43288a248, L_0x2ac43288a290, C4<0>, C4<0>; +L_0x13b26e0 .delay 1 (30000,30000,30000) L_0x13b26e0/d; +L_0x13b28e0/d .functor AND 1, L_0x13bb230, L_0x13b0c10, C4<1>, C4<1>; +L_0x13b28e0 .delay 1 (30000,30000,30000) L_0x13b28e0/d; +L_0x2ac43288a2d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a320 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b29a0/d .functor OR 1, L_0x2ac43288a2d8, L_0x2ac43288a320, C4<0>, C4<0>; +L_0x13b29a0 .delay 1 (30000,30000,30000) L_0x13b29a0/d; +L_0x13b2ba0/d .functor NAND 1, L_0x13bb230, L_0x13b0c10, C4<1>, C4<1>; +L_0x13b2ba0 .delay 1 (20000,20000,20000) L_0x13b2ba0/d; +L_0x2ac43288a368 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a3b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b2cb0/d .functor OR 1, L_0x2ac43288a368, L_0x2ac43288a3b0, C4<0>, C4<0>; +L_0x13b2cb0 .delay 1 (30000,30000,30000) L_0x13b2cb0/d; +L_0x13b2e60/d .functor NOR 1, L_0x13bb230, L_0x13b0c10, C4<0>, C4<0>; +L_0x13b2e60 .delay 1 (20000,20000,20000) L_0x13b2e60/d; +L_0x2ac43288a3f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a440 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b3130/d .functor OR 1, L_0x2ac43288a3f8, L_0x2ac43288a440, C4<0>, C4<0>; +L_0x13b3130 .delay 1 (30000,30000,30000) L_0x13b3130/d; +L_0x13b3530/d .functor OR 1, L_0x13bb230, L_0x13b0c10, C4<0>, C4<0>; +L_0x13b3530 .delay 1 (30000,30000,30000) L_0x13b3530/d; +L_0x2ac43288a488 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a4d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b39d0/d .functor OR 1, L_0x2ac43288a488, L_0x2ac43288a4d0, C4<0>, C4<0>; +L_0x13b39d0 .delay 1 (30000,30000,30000) L_0x13b39d0/d; +L_0x13bb130/d .functor NOT 1, L_0x13b7390, C4<0>, C4<0>, C4<0>; +L_0x13bb130 .delay 1 (10000,10000,10000) L_0x13bb130/d; +v0x123e240_0 .net "A", 0 0, L_0x13bb230; 1 drivers +v0x123e300_0 .net "A_", 0 0, L_0x13a63e0; 1 drivers +v0x123e3c0_0 .net "B", 0 0, L_0x13b0c10; 1 drivers +v0x123e490_0 .net "B_", 0 0, L_0x13b0ed0; 1 drivers +v0x123e530_0 .net *"_s11", 0 0, L_0x13b1f40; 1 drivers +v0x123e620_0 .net/2s *"_s13", 0 0, L_0x2ac43288a1b8; 1 drivers +v0x123e6e0_0 .net/2s *"_s15", 0 0, L_0x2ac43288a200; 1 drivers +v0x123e7c0_0 .net *"_s19", 0 0, L_0x13b26e0; 1 drivers +v0x123e8a0_0 .net/2s *"_s21", 0 0, L_0x2ac43288a248; 1 drivers +v0x123ea10_0 .net/2s *"_s23", 0 0, L_0x2ac43288a290; 1 drivers +v0x123eaf0_0 .net *"_s25", 0 0, L_0x13b28e0; 1 drivers +v0x123ebd0_0 .net *"_s28", 0 0, L_0x13b29a0; 1 drivers +v0x123ecb0_0 .net/2s *"_s30", 0 0, L_0x2ac43288a2d8; 1 drivers +v0x123ed90_0 .net/2s *"_s32", 0 0, L_0x2ac43288a320; 1 drivers +v0x123ee70_0 .net *"_s34", 0 0, L_0x13b2ba0; 1 drivers +v0x123ef50_0 .net *"_s37", 0 0, L_0x13b2cb0; 1 drivers +v0x123f030_0 .net/2s *"_s39", 0 0, L_0x2ac43288a368; 1 drivers +v0x123f1e0_0 .net/2s *"_s41", 0 0, L_0x2ac43288a3b0; 1 drivers +v0x123f280_0 .net *"_s43", 0 0, L_0x13b2e60; 1 drivers +v0x123f360_0 .net *"_s46", 0 0, L_0x13b3130; 1 drivers +v0x123f440_0 .net/2s *"_s48", 0 0, L_0x2ac43288a3f8; 1 drivers +v0x123f520_0 .net/2s *"_s50", 0 0, L_0x2ac43288a440; 1 drivers +v0x123f600_0 .net *"_s52", 0 0, L_0x13b3530; 1 drivers +v0x123f6e0_0 .net *"_s56", 0 0, L_0x13b39d0; 1 drivers +v0x123f7c0_0 .net/2s *"_s59", 0 0, L_0x2ac43288a488; 1 drivers +v0x123f8a0_0 .net/2s *"_s61", 0 0, L_0x2ac43288a4d0; 1 drivers +v0x123f980_0 .net *"_s8", 0 0, L_0x13b1e80; 1 drivers +v0x123fa60_0 .net "carryin", 0 0, L_0x13b0cb0; 1 drivers +v0x123fb00_0 .net "carryout", 0 0, L_0x13badd0; 1 drivers +v0x123fba0_0 .net "carryouts", 7 0, L_0x13b3640; 1 drivers +v0x123fcb0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x123fd70_0 .net "result", 0 0, L_0x13b7390; 1 drivers +v0x123fe60_0 .net "results", 7 0, L_0x13b3300; 1 drivers +v0x123f140_0 .net "zero", 0 0, L_0x13bb130; 1 drivers +LS_0x13b3300_0_0 .concat8 [ 1 1 1 1], L_0x13b13a0, L_0x13b19d0, L_0x13b1e80, L_0x13b26e0; +LS_0x13b3300_0_4 .concat8 [ 1 1 1 1], L_0x13b28e0, L_0x13b2ba0, L_0x13b2e60, L_0x13b3530; +L_0x13b3300 .concat8 [ 4 4 0 0], LS_0x13b3300_0_0, LS_0x13b3300_0_4; +LS_0x13b3640_0_0 .concat8 [ 1 1 1 1], L_0x13b1650, L_0x13b1d20, L_0x13b1f40, L_0x13b2530; +LS_0x13b3640_0_4 .concat8 [ 1 1 1 1], L_0x13b29a0, L_0x13b2cb0, L_0x13b3130, L_0x13b39d0; +L_0x13b3640 .concat8 [ 4 4 0 0], LS_0x13b3640_0_0, LS_0x13b3640_0_4; +S_0x122fd90 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x122fb10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13b1650/d .functor OR 1, L_0x13b1130, L_0x13b14f0, C4<0>, C4<0>; +L_0x13b1650 .delay 1 (30000,30000,30000) L_0x13b1650/d; +v0x1230bc0_0 .net "a", 0 0, L_0x13bb230; alias, 1 drivers +v0x1230c80_0 .net "b", 0 0, L_0x13b0c10; alias, 1 drivers +v0x1230d50_0 .net "c1", 0 0, L_0x13b1130; 1 drivers +v0x1230e50_0 .net "c2", 0 0, L_0x13b14f0; 1 drivers +v0x1230f20_0 .net "carryin", 0 0, L_0x13b0cb0; alias, 1 drivers +v0x1231010_0 .net "carryout", 0 0, L_0x13b1650; 1 drivers +v0x12310b0_0 .net "s1", 0 0, L_0x13b10c0; 1 drivers +v0x12311a0_0 .net "sum", 0 0, L_0x13b13a0; 1 drivers +S_0x1230000 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x122fd90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13b10c0/d .functor XOR 1, L_0x13bb230, L_0x13b0c10, C4<0>, C4<0>; +L_0x13b10c0 .delay 1 (30000,30000,30000) L_0x13b10c0/d; +L_0x13b1130/d .functor AND 1, L_0x13bb230, L_0x13b0c10, C4<1>, C4<1>; +L_0x13b1130 .delay 1 (30000,30000,30000) L_0x13b1130/d; +v0x1230260_0 .net "a", 0 0, L_0x13bb230; alias, 1 drivers +v0x1230340_0 .net "b", 0 0, L_0x13b0c10; alias, 1 drivers +v0x1230400_0 .net "carryout", 0 0, L_0x13b1130; alias, 1 drivers +v0x12304a0_0 .net "sum", 0 0, L_0x13b10c0; alias, 1 drivers +S_0x12305e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x122fd90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13b13a0/d .functor XOR 1, L_0x13b10c0, L_0x13b0cb0, C4<0>, C4<0>; +L_0x13b13a0 .delay 1 (30000,30000,30000) L_0x13b13a0/d; +L_0x13b14f0/d .functor AND 1, L_0x13b10c0, L_0x13b0cb0, C4<1>, C4<1>; +L_0x13b14f0 .delay 1 (30000,30000,30000) L_0x13b14f0/d; +v0x1230840_0 .net "a", 0 0, L_0x13b10c0; alias, 1 drivers +v0x12308e0_0 .net "b", 0 0, L_0x13b0cb0; alias, 1 drivers +v0x1230980_0 .net "carryout", 0 0, L_0x13b14f0; alias, 1 drivers +v0x1230a50_0 .net "sum", 0 0, L_0x13b13a0; alias, 1 drivers +S_0x1231270 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x122fb10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1236660_0 .net "ands", 7 0, L_0x13b8dd0; 1 drivers +v0x1236770_0 .net "in", 7 0, L_0x13b3640; alias, 1 drivers +v0x1236830_0 .net "out", 0 0, L_0x13badd0; alias, 1 drivers +v0x1236900_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1231490 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1231270; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1233bc0_0 .net "A", 7 0, L_0x13b3640; alias, 1 drivers +v0x1233cc0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1233d80_0 .net *"_s0", 0 0, L_0x13b76f0; 1 drivers +v0x1233e40_0 .net *"_s12", 0 0, L_0x13b8060; 1 drivers +v0x1233f20_0 .net *"_s16", 0 0, L_0x13b83c0; 1 drivers +v0x1234050_0 .net *"_s20", 0 0, L_0x13b8790; 1 drivers +v0x1234130_0 .net *"_s24", 0 0, L_0x13b8ac0; 1 drivers +v0x1234210_0 .net *"_s28", 0 0, L_0x13b8a50; 1 drivers +v0x12342f0_0 .net *"_s4", 0 0, L_0x13b7a40; 1 drivers +v0x1234460_0 .net *"_s8", 0 0, L_0x13b7d50; 1 drivers +v0x1234540_0 .net "out", 7 0, L_0x13b8dd0; alias, 1 drivers +L_0x13b77b0 .part L_0x13b3640, 0, 1; +L_0x13b79a0 .part v0x127a150_0, 0, 1; +L_0x13b7b00 .part L_0x13b3640, 1, 1; +L_0x13b7c60 .part v0x127a150_0, 1, 1; +L_0x13b7e10 .part L_0x13b3640, 2, 1; +L_0x13b7f70 .part v0x127a150_0, 2, 1; +L_0x13b8120 .part L_0x13b3640, 3, 1; +L_0x13b8280 .part v0x127a150_0, 3, 1; +L_0x13b8480 .part L_0x13b3640, 4, 1; +L_0x13b86f0 .part v0x127a150_0, 4, 1; +L_0x13b8800 .part L_0x13b3640, 5, 1; +L_0x13b8960 .part v0x127a150_0, 5, 1; +L_0x13b8b80 .part L_0x13b3640, 6, 1; +L_0x13b8ce0 .part v0x127a150_0, 6, 1; +LS_0x13b8dd0_0_0 .concat8 [ 1 1 1 1], L_0x13b76f0, L_0x13b7a40, L_0x13b7d50, L_0x13b8060; +LS_0x13b8dd0_0_4 .concat8 [ 1 1 1 1], L_0x13b83c0, L_0x13b8790, L_0x13b8ac0, L_0x13b8a50; +L_0x13b8dd0 .concat8 [ 4 4 0 0], LS_0x13b8dd0_0_0, LS_0x13b8dd0_0_4; +L_0x13b9190 .part L_0x13b3640, 7, 1; +L_0x13b9380 .part v0x127a150_0, 7, 1; +S_0x12316f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x1231900 .param/l "i" 0 4 54, +C4<00>; +L_0x13b76f0/d .functor AND 1, L_0x13b77b0, L_0x13b79a0, C4<1>, C4<1>; +L_0x13b76f0 .delay 1 (30000,30000,30000) L_0x13b76f0/d; +v0x12319e0_0 .net *"_s0", 0 0, L_0x13b77b0; 1 drivers +v0x1231ac0_0 .net *"_s1", 0 0, L_0x13b79a0; 1 drivers +S_0x1231ba0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x1231db0 .param/l "i" 0 4 54, +C4<01>; +L_0x13b7a40/d .functor AND 1, L_0x13b7b00, L_0x13b7c60, C4<1>, C4<1>; +L_0x13b7a40 .delay 1 (30000,30000,30000) L_0x13b7a40/d; +v0x1231e70_0 .net *"_s0", 0 0, L_0x13b7b00; 1 drivers +v0x1231f50_0 .net *"_s1", 0 0, L_0x13b7c60; 1 drivers +S_0x1232030 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x1232240 .param/l "i" 0 4 54, +C4<010>; +L_0x13b7d50/d .functor AND 1, L_0x13b7e10, L_0x13b7f70, C4<1>, C4<1>; +L_0x13b7d50 .delay 1 (30000,30000,30000) L_0x13b7d50/d; +v0x12322e0_0 .net *"_s0", 0 0, L_0x13b7e10; 1 drivers +v0x12323c0_0 .net *"_s1", 0 0, L_0x13b7f70; 1 drivers +S_0x12324a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x12326b0 .param/l "i" 0 4 54, +C4<011>; +L_0x13b8060/d .functor AND 1, L_0x13b8120, L_0x13b8280, C4<1>, C4<1>; +L_0x13b8060 .delay 1 (30000,30000,30000) L_0x13b8060/d; +v0x1232770_0 .net *"_s0", 0 0, L_0x13b8120; 1 drivers +v0x1232850_0 .net *"_s1", 0 0, L_0x13b8280; 1 drivers +S_0x1232930 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x1232b90 .param/l "i" 0 4 54, +C4<0100>; +L_0x13b83c0/d .functor AND 1, L_0x13b8480, L_0x13b86f0, C4<1>, C4<1>; +L_0x13b83c0 .delay 1 (30000,30000,30000) L_0x13b83c0/d; +v0x1232c50_0 .net *"_s0", 0 0, L_0x13b8480; 1 drivers +v0x1232d30_0 .net *"_s1", 0 0, L_0x13b86f0; 1 drivers +S_0x1232e10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x1233020 .param/l "i" 0 4 54, +C4<0101>; +L_0x13b8790/d .functor AND 1, L_0x13b8800, L_0x13b8960, C4<1>, C4<1>; +L_0x13b8790 .delay 1 (30000,30000,30000) L_0x13b8790/d; +v0x12330e0_0 .net *"_s0", 0 0, L_0x13b8800; 1 drivers +v0x12331c0_0 .net *"_s1", 0 0, L_0x13b8960; 1 drivers +S_0x12332a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x12334b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x13b8ac0/d .functor AND 1, L_0x13b8b80, L_0x13b8ce0, C4<1>, C4<1>; +L_0x13b8ac0 .delay 1 (30000,30000,30000) L_0x13b8ac0/d; +v0x1233570_0 .net *"_s0", 0 0, L_0x13b8b80; 1 drivers +v0x1233650_0 .net *"_s1", 0 0, L_0x13b8ce0; 1 drivers +S_0x1233730 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1231490; + .timescale -9 -12; +P_0x1233940 .param/l "i" 0 4 54, +C4<0111>; +L_0x13b8a50/d .functor AND 1, L_0x13b9190, L_0x13b9380, C4<1>, C4<1>; +L_0x13b8a50 .delay 1 (30000,30000,30000) L_0x13b8a50/d; +v0x1233a00_0 .net *"_s0", 0 0, L_0x13b9190; 1 drivers +v0x1233ae0_0 .net *"_s1", 0 0, L_0x13b9380; 1 drivers +S_0x12346a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1231270; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13badd0/d .functor OR 1, L_0x13bae90, L_0x13bb040, C4<0>, C4<0>; +L_0x13badd0 .delay 1 (30000,30000,30000) L_0x13badd0/d; +v0x12361f0_0 .net *"_s10", 0 0, L_0x13bae90; 1 drivers +v0x12362d0_0 .net *"_s12", 0 0, L_0x13bb040; 1 drivers +v0x12363b0_0 .net "in", 7 0, L_0x13b8dd0; alias, 1 drivers +v0x1236480_0 .net "ors", 1 0, L_0x13babf0; 1 drivers +v0x1236540_0 .net "out", 0 0, L_0x13badd0; alias, 1 drivers +L_0x13b9fc0 .part L_0x13b8dd0, 0, 4; +L_0x13babf0 .concat8 [ 1 1 0 0], L_0x13b9cb0, L_0x13ba8e0; +L_0x13bad30 .part L_0x13b8dd0, 4, 4; +L_0x13bae90 .part L_0x13babf0, 0, 1; +L_0x13bb040 .part L_0x13babf0, 1, 1; +S_0x1234860 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x12346a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13b9470/d .functor OR 1, L_0x13b9530, L_0x13b9690, C4<0>, C4<0>; +L_0x13b9470 .delay 1 (30000,30000,30000) L_0x13b9470/d; +L_0x13b98c0/d .functor OR 1, L_0x13b99d0, L_0x13b9b30, C4<0>, C4<0>; +L_0x13b98c0 .delay 1 (30000,30000,30000) L_0x13b98c0/d; +L_0x13b9cb0/d .functor OR 1, L_0x13b9d20, L_0x13b9ed0, C4<0>, C4<0>; +L_0x13b9cb0 .delay 1 (30000,30000,30000) L_0x13b9cb0/d; +v0x1234ab0_0 .net *"_s0", 0 0, L_0x13b9470; 1 drivers +v0x1234bb0_0 .net *"_s10", 0 0, L_0x13b99d0; 1 drivers +v0x1234c90_0 .net *"_s12", 0 0, L_0x13b9b30; 1 drivers +v0x1234d50_0 .net *"_s14", 0 0, L_0x13b9d20; 1 drivers +v0x1234e30_0 .net *"_s16", 0 0, L_0x13b9ed0; 1 drivers +v0x1234f60_0 .net *"_s3", 0 0, L_0x13b9530; 1 drivers +v0x1235040_0 .net *"_s5", 0 0, L_0x13b9690; 1 drivers +v0x1235120_0 .net *"_s6", 0 0, L_0x13b98c0; 1 drivers +v0x1235200_0 .net "in", 3 0, L_0x13b9fc0; 1 drivers +v0x1235370_0 .net "ors", 1 0, L_0x13b97d0; 1 drivers +v0x1235450_0 .net "out", 0 0, L_0x13b9cb0; 1 drivers +L_0x13b9530 .part L_0x13b9fc0, 0, 1; +L_0x13b9690 .part L_0x13b9fc0, 1, 1; +L_0x13b97d0 .concat8 [ 1 1 0 0], L_0x13b9470, L_0x13b98c0; +L_0x13b99d0 .part L_0x13b9fc0, 2, 1; +L_0x13b9b30 .part L_0x13b9fc0, 3, 1; +L_0x13b9d20 .part L_0x13b97d0, 0, 1; +L_0x13b9ed0 .part L_0x13b97d0, 1, 1; +S_0x1235570 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x12346a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13ba0f0/d .functor OR 1, L_0x13ba160, L_0x13ba2c0, C4<0>, C4<0>; +L_0x13ba0f0 .delay 1 (30000,30000,30000) L_0x13ba0f0/d; +L_0x13ba4f0/d .functor OR 1, L_0x13ba600, L_0x13ba760, C4<0>, C4<0>; +L_0x13ba4f0 .delay 1 (30000,30000,30000) L_0x13ba4f0/d; +L_0x13ba8e0/d .functor OR 1, L_0x13ba950, L_0x13bab00, C4<0>, C4<0>; +L_0x13ba8e0 .delay 1 (30000,30000,30000) L_0x13ba8e0/d; +v0x1235730_0 .net *"_s0", 0 0, L_0x13ba0f0; 1 drivers +v0x1235830_0 .net *"_s10", 0 0, L_0x13ba600; 1 drivers +v0x1235910_0 .net *"_s12", 0 0, L_0x13ba760; 1 drivers +v0x12359d0_0 .net *"_s14", 0 0, L_0x13ba950; 1 drivers +v0x1235ab0_0 .net *"_s16", 0 0, L_0x13bab00; 1 drivers +v0x1235be0_0 .net *"_s3", 0 0, L_0x13ba160; 1 drivers +v0x1235cc0_0 .net *"_s5", 0 0, L_0x13ba2c0; 1 drivers +v0x1235da0_0 .net *"_s6", 0 0, L_0x13ba4f0; 1 drivers +v0x1235e80_0 .net "in", 3 0, L_0x13bad30; 1 drivers +v0x1235ff0_0 .net "ors", 1 0, L_0x13ba400; 1 drivers +v0x12360d0_0 .net "out", 0 0, L_0x13ba8e0; 1 drivers +L_0x13ba160 .part L_0x13bad30, 0, 1; +L_0x13ba2c0 .part L_0x13bad30, 1, 1; +L_0x13ba400 .concat8 [ 1 1 0 0], L_0x13ba0f0, L_0x13ba4f0; +L_0x13ba600 .part L_0x13bad30, 2, 1; +L_0x13ba760 .part L_0x13bad30, 3, 1; +L_0x13ba950 .part L_0x13ba400, 0, 1; +L_0x13bab00 .part L_0x13ba400, 1, 1; +S_0x12369e0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x122fb10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x123be10_0 .net "ands", 7 0, L_0x13b5390; 1 drivers +v0x123bf20_0 .net "in", 7 0, L_0x13b3300; alias, 1 drivers +v0x123bfe0_0 .net "out", 0 0, L_0x13b7390; alias, 1 drivers +v0x123c0b0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1236c30 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x12369e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1239370_0 .net "A", 7 0, L_0x13b3300; alias, 1 drivers +v0x1239470_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1239530_0 .net *"_s0", 0 0, L_0x13b3b80; 1 drivers +v0x12395f0_0 .net *"_s12", 0 0, L_0x13b4540; 1 drivers +v0x12396d0_0 .net *"_s16", 0 0, L_0x13b48a0; 1 drivers +v0x1239800_0 .net *"_s20", 0 0, L_0x13b4cd0; 1 drivers +v0x12398e0_0 .net *"_s24", 0 0, L_0x13b5000; 1 drivers +v0x12399c0_0 .net *"_s28", 0 0, L_0x13b4f90; 1 drivers +v0x1239aa0_0 .net *"_s4", 0 0, L_0x13b3f20; 1 drivers +v0x1239c10_0 .net *"_s8", 0 0, L_0x13b4230; 1 drivers +v0x1239cf0_0 .net "out", 7 0, L_0x13b5390; alias, 1 drivers +L_0x13b3c90 .part L_0x13b3300, 0, 1; +L_0x13b3e80 .part v0x127a150_0, 0, 1; +L_0x13b3fe0 .part L_0x13b3300, 1, 1; +L_0x13b4140 .part v0x127a150_0, 1, 1; +L_0x13b42f0 .part L_0x13b3300, 2, 1; +L_0x13b4450 .part v0x127a150_0, 2, 1; +L_0x13b4600 .part L_0x13b3300, 3, 1; +L_0x13b4760 .part v0x127a150_0, 3, 1; +L_0x13b4960 .part L_0x13b3300, 4, 1; +L_0x13b4bd0 .part v0x127a150_0, 4, 1; +L_0x13b4d40 .part L_0x13b3300, 5, 1; +L_0x13b4ea0 .part v0x127a150_0, 5, 1; +L_0x13b50c0 .part L_0x13b3300, 6, 1; +L_0x13b5220 .part v0x127a150_0, 6, 1; +LS_0x13b5390_0_0 .concat8 [ 1 1 1 1], L_0x13b3b80, L_0x13b3f20, L_0x13b4230, L_0x13b4540; +LS_0x13b5390_0_4 .concat8 [ 1 1 1 1], L_0x13b48a0, L_0x13b4cd0, L_0x13b5000, L_0x13b4f90; +L_0x13b5390 .concat8 [ 4 4 0 0], LS_0x13b5390_0_0, LS_0x13b5390_0_4; +L_0x13b5750 .part L_0x13b3300, 7, 1; +L_0x13b5940 .part v0x127a150_0, 7, 1; +S_0x1236e70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x1237080 .param/l "i" 0 4 54, +C4<00>; +L_0x13b3b80/d .functor AND 1, L_0x13b3c90, L_0x13b3e80, C4<1>, C4<1>; +L_0x13b3b80 .delay 1 (30000,30000,30000) L_0x13b3b80/d; +v0x1237160_0 .net *"_s0", 0 0, L_0x13b3c90; 1 drivers +v0x1237240_0 .net *"_s1", 0 0, L_0x13b3e80; 1 drivers +S_0x1237320 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x1237530 .param/l "i" 0 4 54, +C4<01>; +L_0x13b3f20/d .functor AND 1, L_0x13b3fe0, L_0x13b4140, C4<1>, C4<1>; +L_0x13b3f20 .delay 1 (30000,30000,30000) L_0x13b3f20/d; +v0x12375f0_0 .net *"_s0", 0 0, L_0x13b3fe0; 1 drivers +v0x12376d0_0 .net *"_s1", 0 0, L_0x13b4140; 1 drivers +S_0x12377b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x12379f0 .param/l "i" 0 4 54, +C4<010>; +L_0x13b4230/d .functor AND 1, L_0x13b42f0, L_0x13b4450, C4<1>, C4<1>; +L_0x13b4230 .delay 1 (30000,30000,30000) L_0x13b4230/d; +v0x1237a90_0 .net *"_s0", 0 0, L_0x13b42f0; 1 drivers +v0x1237b70_0 .net *"_s1", 0 0, L_0x13b4450; 1 drivers +S_0x1237c50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x1237e60 .param/l "i" 0 4 54, +C4<011>; +L_0x13b4540/d .functor AND 1, L_0x13b4600, L_0x13b4760, C4<1>, C4<1>; +L_0x13b4540 .delay 1 (30000,30000,30000) L_0x13b4540/d; +v0x1237f20_0 .net *"_s0", 0 0, L_0x13b4600; 1 drivers +v0x1238000_0 .net *"_s1", 0 0, L_0x13b4760; 1 drivers +S_0x12380e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x1238340 .param/l "i" 0 4 54, +C4<0100>; +L_0x13b48a0/d .functor AND 1, L_0x13b4960, L_0x13b4bd0, C4<1>, C4<1>; +L_0x13b48a0 .delay 1 (30000,30000,30000) L_0x13b48a0/d; +v0x1238400_0 .net *"_s0", 0 0, L_0x13b4960; 1 drivers +v0x12384e0_0 .net *"_s1", 0 0, L_0x13b4bd0; 1 drivers +S_0x12385c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x12387d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13b4cd0/d .functor AND 1, L_0x13b4d40, L_0x13b4ea0, C4<1>, C4<1>; +L_0x13b4cd0 .delay 1 (30000,30000,30000) L_0x13b4cd0/d; +v0x1238890_0 .net *"_s0", 0 0, L_0x13b4d40; 1 drivers +v0x1238970_0 .net *"_s1", 0 0, L_0x13b4ea0; 1 drivers +S_0x1238a50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x1238c60 .param/l "i" 0 4 54, +C4<0110>; +L_0x13b5000/d .functor AND 1, L_0x13b50c0, L_0x13b5220, C4<1>, C4<1>; +L_0x13b5000 .delay 1 (30000,30000,30000) L_0x13b5000/d; +v0x1238d20_0 .net *"_s0", 0 0, L_0x13b50c0; 1 drivers +v0x1238e00_0 .net *"_s1", 0 0, L_0x13b5220; 1 drivers +S_0x1238ee0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1236c30; + .timescale -9 -12; +P_0x12390f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x13b4f90/d .functor AND 1, L_0x13b5750, L_0x13b5940, C4<1>, C4<1>; +L_0x13b4f90 .delay 1 (30000,30000,30000) L_0x13b4f90/d; +v0x12391b0_0 .net *"_s0", 0 0, L_0x13b5750; 1 drivers +v0x1239290_0 .net *"_s1", 0 0, L_0x13b5940; 1 drivers +S_0x1239e50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x12369e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13b7390/d .functor OR 1, L_0x13b7450, L_0x13b7600, C4<0>, C4<0>; +L_0x13b7390 .delay 1 (30000,30000,30000) L_0x13b7390/d; +v0x123b9a0_0 .net *"_s10", 0 0, L_0x13b7450; 1 drivers +v0x123ba80_0 .net *"_s12", 0 0, L_0x13b7600; 1 drivers +v0x123bb60_0 .net "in", 7 0, L_0x13b5390; alias, 1 drivers +v0x123bc30_0 .net "ors", 1 0, L_0x13b71b0; 1 drivers +v0x123bcf0_0 .net "out", 0 0, L_0x13b7390; alias, 1 drivers +L_0x13b6580 .part L_0x13b5390, 0, 4; +L_0x13b71b0 .concat8 [ 1 1 0 0], L_0x13b6270, L_0x13b6ea0; +L_0x13b72f0 .part L_0x13b5390, 4, 4; +L_0x13b7450 .part L_0x13b71b0, 0, 1; +L_0x13b7600 .part L_0x13b71b0, 1, 1; +S_0x123a010 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1239e50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13b5a30/d .functor OR 1, L_0x13b5af0, L_0x13b5c50, C4<0>, C4<0>; +L_0x13b5a30 .delay 1 (30000,30000,30000) L_0x13b5a30/d; +L_0x13b5e80/d .functor OR 1, L_0x13b5f90, L_0x13b60f0, C4<0>, C4<0>; +L_0x13b5e80 .delay 1 (30000,30000,30000) L_0x13b5e80/d; +L_0x13b6270/d .functor OR 1, L_0x13b62e0, L_0x13b6490, C4<0>, C4<0>; +L_0x13b6270 .delay 1 (30000,30000,30000) L_0x13b6270/d; +v0x123a260_0 .net *"_s0", 0 0, L_0x13b5a30; 1 drivers +v0x123a360_0 .net *"_s10", 0 0, L_0x13b5f90; 1 drivers +v0x123a440_0 .net *"_s12", 0 0, L_0x13b60f0; 1 drivers +v0x123a500_0 .net *"_s14", 0 0, L_0x13b62e0; 1 drivers +v0x123a5e0_0 .net *"_s16", 0 0, L_0x13b6490; 1 drivers +v0x123a710_0 .net *"_s3", 0 0, L_0x13b5af0; 1 drivers +v0x123a7f0_0 .net *"_s5", 0 0, L_0x13b5c50; 1 drivers +v0x123a8d0_0 .net *"_s6", 0 0, L_0x13b5e80; 1 drivers +v0x123a9b0_0 .net "in", 3 0, L_0x13b6580; 1 drivers +v0x123ab20_0 .net "ors", 1 0, L_0x13b5d90; 1 drivers +v0x123ac00_0 .net "out", 0 0, L_0x13b6270; 1 drivers +L_0x13b5af0 .part L_0x13b6580, 0, 1; +L_0x13b5c50 .part L_0x13b6580, 1, 1; +L_0x13b5d90 .concat8 [ 1 1 0 0], L_0x13b5a30, L_0x13b5e80; +L_0x13b5f90 .part L_0x13b6580, 2, 1; +L_0x13b60f0 .part L_0x13b6580, 3, 1; +L_0x13b62e0 .part L_0x13b5d90, 0, 1; +L_0x13b6490 .part L_0x13b5d90, 1, 1; +S_0x123ad20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1239e50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13b66b0/d .functor OR 1, L_0x13b6720, L_0x13b6880, C4<0>, C4<0>; +L_0x13b66b0 .delay 1 (30000,30000,30000) L_0x13b66b0/d; +L_0x13b6ab0/d .functor OR 1, L_0x13b6bc0, L_0x13b6d20, C4<0>, C4<0>; +L_0x13b6ab0 .delay 1 (30000,30000,30000) L_0x13b6ab0/d; +L_0x13b6ea0/d .functor OR 1, L_0x13b6f10, L_0x13b70c0, C4<0>, C4<0>; +L_0x13b6ea0 .delay 1 (30000,30000,30000) L_0x13b6ea0/d; +v0x123aee0_0 .net *"_s0", 0 0, L_0x13b66b0; 1 drivers +v0x123afe0_0 .net *"_s10", 0 0, L_0x13b6bc0; 1 drivers +v0x123b0c0_0 .net *"_s12", 0 0, L_0x13b6d20; 1 drivers +v0x123b180_0 .net *"_s14", 0 0, L_0x13b6f10; 1 drivers +v0x123b260_0 .net *"_s16", 0 0, L_0x13b70c0; 1 drivers +v0x123b390_0 .net *"_s3", 0 0, L_0x13b6720; 1 drivers +v0x123b470_0 .net *"_s5", 0 0, L_0x13b6880; 1 drivers +v0x123b550_0 .net *"_s6", 0 0, L_0x13b6ab0; 1 drivers +v0x123b630_0 .net "in", 3 0, L_0x13b72f0; 1 drivers +v0x123b7a0_0 .net "ors", 1 0, L_0x13b69c0; 1 drivers +v0x123b880_0 .net "out", 0 0, L_0x13b6ea0; 1 drivers +L_0x13b6720 .part L_0x13b72f0, 0, 1; +L_0x13b6880 .part L_0x13b72f0, 1, 1; +L_0x13b69c0 .concat8 [ 1 1 0 0], L_0x13b66b0, L_0x13b6ab0; +L_0x13b6bc0 .part L_0x13b72f0, 2, 1; +L_0x13b6d20 .part L_0x13b72f0, 3, 1; +L_0x13b6f10 .part L_0x13b69c0, 0, 1; +L_0x13b70c0 .part L_0x13b69c0, 1, 1; +S_0x123c190 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x122fb10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x13b2140/d .functor XNOR 1, L_0x13bb230, L_0x13b0c10, C4<0>, C4<0>; +L_0x13b2140 .delay 1 (20000,20000,20000) L_0x13b2140/d; +L_0x13b22c0/d .functor AND 1, L_0x13bb230, L_0x13b0ed0, C4<1>, C4<1>; +L_0x13b22c0 .delay 1 (30000,30000,30000) L_0x13b22c0/d; +L_0x13b2420/d .functor AND 1, L_0x13b2140, L_0x13b0cb0, C4<1>, C4<1>; +L_0x13b2420 .delay 1 (30000,30000,30000) L_0x13b2420/d; +L_0x13b2530/d .functor OR 1, L_0x13b2420, L_0x13b22c0, C4<0>, C4<0>; +L_0x13b2530 .delay 1 (30000,30000,30000) L_0x13b2530/d; +v0x123c440_0 .net "a", 0 0, L_0x13bb230; alias, 1 drivers +v0x123c530_0 .net "a_", 0 0, L_0x13a63e0; alias, 1 drivers +v0x123c5f0_0 .net "b", 0 0, L_0x13b0c10; alias, 1 drivers +v0x123c6e0_0 .net "b_", 0 0, L_0x13b0ed0; alias, 1 drivers +v0x123c780_0 .net "carryin", 0 0, L_0x13b0cb0; alias, 1 drivers +v0x123c8c0_0 .net "eq", 0 0, L_0x13b2140; 1 drivers +v0x123c980_0 .net "lt", 0 0, L_0x13b22c0; 1 drivers +v0x123ca40_0 .net "out", 0 0, L_0x13b2530; 1 drivers +v0x123cb00_0 .net "w0", 0 0, L_0x13b2420; 1 drivers +S_0x123cd50 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x122fb10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13b1d20/d .functor OR 1, L_0x13b1870, L_0x123dfb0, C4<0>, C4<0>; +L_0x13b1d20 .delay 1 (30000,30000,30000) L_0x13b1d20/d; +v0x123db40_0 .net "a", 0 0, L_0x13bb230; alias, 1 drivers +v0x123dc90_0 .net "b", 0 0, L_0x13b0ed0; alias, 1 drivers +v0x123dd50_0 .net "c1", 0 0, L_0x13b1870; 1 drivers +v0x123ddf0_0 .net "c2", 0 0, L_0x123dfb0; 1 drivers +v0x123dec0_0 .net "carryin", 0 0, L_0x13b0cb0; alias, 1 drivers +v0x123e040_0 .net "carryout", 0 0, L_0x13b1d20; 1 drivers +v0x123e0e0_0 .net "s1", 0 0, L_0x13b17b0; 1 drivers +v0x123e180_0 .net "sum", 0 0, L_0x13b19d0; 1 drivers +S_0x123cfa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x123cd50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13b17b0/d .functor XOR 1, L_0x13bb230, L_0x13b0ed0, C4<0>, C4<0>; +L_0x13b17b0 .delay 1 (30000,30000,30000) L_0x13b17b0/d; +L_0x13b1870/d .functor AND 1, L_0x13bb230, L_0x13b0ed0, C4<1>, C4<1>; +L_0x13b1870 .delay 1 (30000,30000,30000) L_0x13b1870/d; +v0x123d200_0 .net "a", 0 0, L_0x13bb230; alias, 1 drivers +v0x123d2c0_0 .net "b", 0 0, L_0x13b0ed0; alias, 1 drivers +v0x123d380_0 .net "carryout", 0 0, L_0x13b1870; alias, 1 drivers +v0x123d420_0 .net "sum", 0 0, L_0x13b17b0; alias, 1 drivers +S_0x123d550 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x123cd50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13b19d0/d .functor XOR 1, L_0x13b17b0, L_0x13b0cb0, C4<0>, C4<0>; +L_0x13b19d0 .delay 1 (30000,30000,30000) L_0x13b19d0/d; +L_0x123dfb0/d .functor AND 1, L_0x13b17b0, L_0x13b0cb0, C4<1>, C4<1>; +L_0x123dfb0 .delay 1 (30000,30000,30000) L_0x123dfb0/d; +v0x123d7b0_0 .net "a", 0 0, L_0x13b17b0; alias, 1 drivers +v0x123d880_0 .net "b", 0 0, L_0x13b0cb0; alias, 1 drivers +v0x123d920_0 .net "carryout", 0 0, L_0x123dfb0; alias, 1 drivers +v0x123d9f0_0 .net "sum", 0 0, L_0x13b19d0; alias, 1 drivers +S_0x1240210 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x122f840; + .timescale -9 -12; +L_0x2ac43288a518 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a560 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13b1330/d .functor OR 1, L_0x2ac43288a518, L_0x2ac43288a560, C4<0>, C4<0>; +L_0x13b1330 .delay 1 (30000,30000,30000) L_0x13b1330/d; +v0x1240400_0 .net/2u *"_s0", 0 0, L_0x2ac43288a518; 1 drivers +v0x12404e0_0 .net/2u *"_s2", 0 0, L_0x2ac43288a560; 1 drivers +S_0x12405c0 .scope generate, "alu_slices[30]" "alu_slices[30]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x12407d0 .param/l "i" 0 3 39, +C4<011110>; +S_0x1240890 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x12405c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x13b0e40/d .functor NOT 1, L_0x13c5a90, C4<0>, C4<0>, C4<0>; +L_0x13b0e40 .delay 1 (10000,10000,10000) L_0x13b0e40/d; +L_0x13bb710/d .functor NOT 1, L_0x131ab30, C4<0>, C4<0>, C4<0>; +L_0x13bb710 .delay 1 (10000,10000,10000) L_0x13bb710/d; +L_0x13bc760/d .functor XOR 1, L_0x13c5a90, L_0x131ab30, C4<0>, C4<0>; +L_0x13bc760 .delay 1 (30000,30000,30000) L_0x13bc760/d; +L_0x2ac43288a5a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a5f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13bc820/d .functor OR 1, L_0x2ac43288a5a8, L_0x2ac43288a5f0, C4<0>, C4<0>; +L_0x13bc820 .delay 1 (30000,30000,30000) L_0x13bc820/d; +L_0x2ac43288a638 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a680 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13bcfc0/d .functor OR 1, L_0x2ac43288a638, L_0x2ac43288a680, C4<0>, C4<0>; +L_0x13bcfc0 .delay 1 (30000,30000,30000) L_0x13bcfc0/d; +L_0x13bd1c0/d .functor AND 1, L_0x13c5a90, L_0x131ab30, C4<1>, C4<1>; +L_0x13bd1c0 .delay 1 (30000,30000,30000) L_0x13bd1c0/d; +L_0x2ac43288a6c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a710 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13bd280/d .functor OR 1, L_0x2ac43288a6c8, L_0x2ac43288a710, C4<0>, C4<0>; +L_0x13bd280 .delay 1 (30000,30000,30000) L_0x13bd280/d; +L_0x13bd480/d .functor NAND 1, L_0x13c5a90, L_0x131ab30, C4<1>, C4<1>; +L_0x13bd480 .delay 1 (20000,20000,20000) L_0x13bd480/d; +L_0x2ac43288a758 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a7a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13bd590/d .functor OR 1, L_0x2ac43288a758, L_0x2ac43288a7a0, C4<0>, C4<0>; +L_0x13bd590 .delay 1 (30000,30000,30000) L_0x13bd590/d; +L_0x13bd740/d .functor NOR 1, L_0x13c5a90, L_0x131ab30, C4<0>, C4<0>; +L_0x13bd740 .delay 1 (20000,20000,20000) L_0x13bd740/d; +L_0x2ac43288a7e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a830 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13bbbc0/d .functor OR 1, L_0x2ac43288a7e8, L_0x2ac43288a830, C4<0>, C4<0>; +L_0x13bbbc0 .delay 1 (30000,30000,30000) L_0x13bbbc0/d; +L_0x13bdda0/d .functor OR 1, L_0x13c5a90, L_0x131ab30, C4<0>, C4<0>; +L_0x13bdda0 .delay 1 (30000,30000,30000) L_0x13bdda0/d; +L_0x2ac43288a878 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a8c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13be290/d .functor OR 1, L_0x2ac43288a878, L_0x2ac43288a8c0, C4<0>, C4<0>; +L_0x13be290 .delay 1 (30000,30000,30000) L_0x13be290/d; +L_0x13c5990/d .functor NOT 1, L_0x13c1bf0, C4<0>, C4<0>, C4<0>; +L_0x13c5990 .delay 1 (10000,10000,10000) L_0x13c5990/d; +v0x124efd0_0 .net "A", 0 0, L_0x13c5a90; 1 drivers +v0x124f090_0 .net "A_", 0 0, L_0x13b0e40; 1 drivers +v0x124f150_0 .net "B", 0 0, L_0x131ab30; 1 drivers +v0x124f220_0 .net "B_", 0 0, L_0x13bb710; 1 drivers +v0x124f2c0_0 .net *"_s11", 0 0, L_0x13bc820; 1 drivers +v0x124f3b0_0 .net/2s *"_s13", 0 0, L_0x2ac43288a5a8; 1 drivers +v0x124f470_0 .net/2s *"_s15", 0 0, L_0x2ac43288a5f0; 1 drivers +v0x124f550_0 .net *"_s19", 0 0, L_0x13bcfc0; 1 drivers +v0x124f630_0 .net/2s *"_s21", 0 0, L_0x2ac43288a638; 1 drivers +v0x124f7a0_0 .net/2s *"_s23", 0 0, L_0x2ac43288a680; 1 drivers +v0x124f880_0 .net *"_s25", 0 0, L_0x13bd1c0; 1 drivers +v0x124f960_0 .net *"_s28", 0 0, L_0x13bd280; 1 drivers +v0x124fa40_0 .net/2s *"_s30", 0 0, L_0x2ac43288a6c8; 1 drivers +v0x124fb20_0 .net/2s *"_s32", 0 0, L_0x2ac43288a710; 1 drivers +v0x124fc00_0 .net *"_s34", 0 0, L_0x13bd480; 1 drivers +v0x124fce0_0 .net *"_s37", 0 0, L_0x13bd590; 1 drivers +v0x124fdc0_0 .net/2s *"_s39", 0 0, L_0x2ac43288a758; 1 drivers +v0x124ff70_0 .net/2s *"_s41", 0 0, L_0x2ac43288a7a0; 1 drivers +v0x1250010_0 .net *"_s43", 0 0, L_0x13bd740; 1 drivers +v0x12500f0_0 .net *"_s46", 0 0, L_0x13bbbc0; 1 drivers +v0x12501d0_0 .net/2s *"_s48", 0 0, L_0x2ac43288a7e8; 1 drivers +v0x12502b0_0 .net/2s *"_s50", 0 0, L_0x2ac43288a830; 1 drivers +v0x1250390_0 .net *"_s52", 0 0, L_0x13bdda0; 1 drivers +v0x1250470_0 .net *"_s56", 0 0, L_0x13be290; 1 drivers +v0x1250550_0 .net/2s *"_s59", 0 0, L_0x2ac43288a878; 1 drivers +v0x1250630_0 .net/2s *"_s61", 0 0, L_0x2ac43288a8c0; 1 drivers +v0x1250710_0 .net *"_s8", 0 0, L_0x13bc760; 1 drivers +v0x12507f0_0 .net "carryin", 0 0, L_0x13bb390; 1 drivers +v0x1250890_0 .net "carryout", 0 0, L_0x13c5630; 1 drivers +v0x1250930_0 .net "carryouts", 7 0, L_0x13bdf20; 1 drivers +v0x1250a40_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1250b00_0 .net "result", 0 0, L_0x13c1bf0; 1 drivers +v0x1250bf0_0 .net "results", 7 0, L_0x13bdb70; 1 drivers +v0x124fed0_0 .net "zero", 0 0, L_0x13c5990; 1 drivers +LS_0x13bdb70_0_0 .concat8 [ 1 1 1 1], L_0x13bbc30, L_0x13bc260, L_0x13bc760, L_0x13bcfc0; +LS_0x13bdb70_0_4 .concat8 [ 1 1 1 1], L_0x13bd1c0, L_0x13bd480, L_0x13bd740, L_0x13bdda0; +L_0x13bdb70 .concat8 [ 4 4 0 0], LS_0x13bdb70_0_0, LS_0x13bdb70_0_4; +LS_0x13bdf20_0_0 .concat8 [ 1 1 1 1], L_0x13bbee0, L_0x13bc600, L_0x13bc820, L_0x13bce10; +LS_0x13bdf20_0_4 .concat8 [ 1 1 1 1], L_0x13bd280, L_0x13bd590, L_0x13bbbc0, L_0x13be290; +L_0x13bdf20 .concat8 [ 4 4 0 0], LS_0x13bdf20_0_0, LS_0x13bdf20_0_4; +S_0x1240b10 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1240890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13bbee0/d .functor OR 1, L_0x13bb9c0, L_0x13bbd80, C4<0>, C4<0>; +L_0x13bbee0 .delay 1 (30000,30000,30000) L_0x13bbee0/d; +v0x1241940_0 .net "a", 0 0, L_0x13c5a90; alias, 1 drivers +v0x1241a00_0 .net "b", 0 0, L_0x131ab30; alias, 1 drivers +v0x1241ad0_0 .net "c1", 0 0, L_0x13bb9c0; 1 drivers +v0x1241bd0_0 .net "c2", 0 0, L_0x13bbd80; 1 drivers +v0x1241ca0_0 .net "carryin", 0 0, L_0x13bb390; alias, 1 drivers +v0x1241d90_0 .net "carryout", 0 0, L_0x13bbee0; 1 drivers +v0x1241e30_0 .net "s1", 0 0, L_0x13bb900; 1 drivers +v0x1241f20_0 .net "sum", 0 0, L_0x13bbc30; 1 drivers +S_0x1240d80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1240b10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13bb900/d .functor XOR 1, L_0x13c5a90, L_0x131ab30, C4<0>, C4<0>; +L_0x13bb900 .delay 1 (30000,30000,30000) L_0x13bb900/d; +L_0x13bb9c0/d .functor AND 1, L_0x13c5a90, L_0x131ab30, C4<1>, C4<1>; +L_0x13bb9c0 .delay 1 (30000,30000,30000) L_0x13bb9c0/d; +v0x1240fe0_0 .net "a", 0 0, L_0x13c5a90; alias, 1 drivers +v0x12410c0_0 .net "b", 0 0, L_0x131ab30; alias, 1 drivers +v0x1241180_0 .net "carryout", 0 0, L_0x13bb9c0; alias, 1 drivers +v0x1241220_0 .net "sum", 0 0, L_0x13bb900; alias, 1 drivers +S_0x1241360 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1240b10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13bbc30/d .functor XOR 1, L_0x13bb900, L_0x13bb390, C4<0>, C4<0>; +L_0x13bbc30 .delay 1 (30000,30000,30000) L_0x13bbc30/d; +L_0x13bbd80/d .functor AND 1, L_0x13bb900, L_0x13bb390, C4<1>, C4<1>; +L_0x13bbd80 .delay 1 (30000,30000,30000) L_0x13bbd80/d; +v0x12415c0_0 .net "a", 0 0, L_0x13bb900; alias, 1 drivers +v0x1241660_0 .net "b", 0 0, L_0x13bb390; alias, 1 drivers +v0x1241700_0 .net "carryout", 0 0, L_0x13bbd80; alias, 1 drivers +v0x12417d0_0 .net "sum", 0 0, L_0x13bbc30; alias, 1 drivers +S_0x1241ff0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1240890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x12473f0_0 .net "ands", 7 0, L_0x13c3630; 1 drivers +v0x1247500_0 .net "in", 7 0, L_0x13bdf20; alias, 1 drivers +v0x12475c0_0 .net "out", 0 0, L_0x13c5630; alias, 1 drivers +v0x1247690_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1242210 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1241ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1244920_0 .net "A", 7 0, L_0x13bdf20; alias, 1 drivers +v0x1244a20_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1244ae0_0 .net *"_s0", 0 0, L_0x13c1f50; 1 drivers +v0x1244bd0_0 .net *"_s12", 0 0, L_0x13c28c0; 1 drivers +v0x1244cb0_0 .net *"_s16", 0 0, L_0x13c2c20; 1 drivers +v0x1244de0_0 .net *"_s20", 0 0, L_0x13c2ff0; 1 drivers +v0x1244ec0_0 .net *"_s24", 0 0, L_0x13c3320; 1 drivers +v0x1244fa0_0 .net *"_s28", 0 0, L_0x13c32b0; 1 drivers +v0x1245080_0 .net *"_s4", 0 0, L_0x13c22a0; 1 drivers +v0x12451f0_0 .net *"_s8", 0 0, L_0x13c25b0; 1 drivers +v0x12452d0_0 .net "out", 7 0, L_0x13c3630; alias, 1 drivers +L_0x13c2010 .part L_0x13bdf20, 0, 1; +L_0x13c2200 .part v0x127a150_0, 0, 1; +L_0x13c2360 .part L_0x13bdf20, 1, 1; +L_0x13c24c0 .part v0x127a150_0, 1, 1; +L_0x13c2670 .part L_0x13bdf20, 2, 1; +L_0x13c27d0 .part v0x127a150_0, 2, 1; +L_0x13c2980 .part L_0x13bdf20, 3, 1; +L_0x13c2ae0 .part v0x127a150_0, 3, 1; +L_0x13c2ce0 .part L_0x13bdf20, 4, 1; +L_0x13c2f50 .part v0x127a150_0, 4, 1; +L_0x13c3060 .part L_0x13bdf20, 5, 1; +L_0x13c31c0 .part v0x127a150_0, 5, 1; +L_0x13c33e0 .part L_0x13bdf20, 6, 1; +L_0x13c3540 .part v0x127a150_0, 6, 1; +LS_0x13c3630_0_0 .concat8 [ 1 1 1 1], L_0x13c1f50, L_0x13c22a0, L_0x13c25b0, L_0x13c28c0; +LS_0x13c3630_0_4 .concat8 [ 1 1 1 1], L_0x13c2c20, L_0x13c2ff0, L_0x13c3320, L_0x13c32b0; +L_0x13c3630 .concat8 [ 4 4 0 0], LS_0x13c3630_0_0, LS_0x13c3630_0_4; +L_0x13c39f0 .part L_0x13bdf20, 7, 1; +L_0x13c3be0 .part v0x127a150_0, 7, 1; +S_0x1242470 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1242680 .param/l "i" 0 4 54, +C4<00>; +L_0x13c1f50/d .functor AND 1, L_0x13c2010, L_0x13c2200, C4<1>, C4<1>; +L_0x13c1f50 .delay 1 (30000,30000,30000) L_0x13c1f50/d; +v0x1242760_0 .net *"_s0", 0 0, L_0x13c2010; 1 drivers +v0x1242840_0 .net *"_s1", 0 0, L_0x13c2200; 1 drivers +S_0x1242920 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1242b30 .param/l "i" 0 4 54, +C4<01>; +L_0x13c22a0/d .functor AND 1, L_0x13c2360, L_0x13c24c0, C4<1>, C4<1>; +L_0x13c22a0 .delay 1 (30000,30000,30000) L_0x13c22a0/d; +v0x1242bf0_0 .net *"_s0", 0 0, L_0x13c2360; 1 drivers +v0x1242cd0_0 .net *"_s1", 0 0, L_0x13c24c0; 1 drivers +S_0x1242db0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1242fc0 .param/l "i" 0 4 54, +C4<010>; +L_0x13c25b0/d .functor AND 1, L_0x13c2670, L_0x13c27d0, C4<1>, C4<1>; +L_0x13c25b0 .delay 1 (30000,30000,30000) L_0x13c25b0/d; +v0x1243060_0 .net *"_s0", 0 0, L_0x13c2670; 1 drivers +v0x1243140_0 .net *"_s1", 0 0, L_0x13c27d0; 1 drivers +S_0x1243220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1243430 .param/l "i" 0 4 54, +C4<011>; +L_0x13c28c0/d .functor AND 1, L_0x13c2980, L_0x13c2ae0, C4<1>, C4<1>; +L_0x13c28c0 .delay 1 (30000,30000,30000) L_0x13c28c0/d; +v0x12434f0_0 .net *"_s0", 0 0, L_0x13c2980; 1 drivers +v0x12435d0_0 .net *"_s1", 0 0, L_0x13c2ae0; 1 drivers +S_0x12436b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1243910 .param/l "i" 0 4 54, +C4<0100>; +L_0x13c2c20/d .functor AND 1, L_0x13c2ce0, L_0x13c2f50, C4<1>, C4<1>; +L_0x13c2c20 .delay 1 (30000,30000,30000) L_0x13c2c20/d; +v0x12439d0_0 .net *"_s0", 0 0, L_0x13c2ce0; 1 drivers +v0x1243ab0_0 .net *"_s1", 0 0, L_0x13c2f50; 1 drivers +S_0x1243b90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1243da0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13c2ff0/d .functor AND 1, L_0x13c3060, L_0x13c31c0, C4<1>, C4<1>; +L_0x13c2ff0 .delay 1 (30000,30000,30000) L_0x13c2ff0/d; +v0x1243e60_0 .net *"_s0", 0 0, L_0x13c3060; 1 drivers +v0x1243f40_0 .net *"_s1", 0 0, L_0x13c31c0; 1 drivers +S_0x1244000 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x1244210 .param/l "i" 0 4 54, +C4<0110>; +L_0x13c3320/d .functor AND 1, L_0x13c33e0, L_0x13c3540, C4<1>, C4<1>; +L_0x13c3320 .delay 1 (30000,30000,30000) L_0x13c3320/d; +v0x12442d0_0 .net *"_s0", 0 0, L_0x13c33e0; 1 drivers +v0x12443b0_0 .net *"_s1", 0 0, L_0x13c3540; 1 drivers +S_0x1244490 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1242210; + .timescale -9 -12; +P_0x12446a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x13c32b0/d .functor AND 1, L_0x13c39f0, L_0x13c3be0, C4<1>, C4<1>; +L_0x13c32b0 .delay 1 (30000,30000,30000) L_0x13c32b0/d; +v0x1244760_0 .net *"_s0", 0 0, L_0x13c39f0; 1 drivers +v0x1244840_0 .net *"_s1", 0 0, L_0x13c3be0; 1 drivers +S_0x1245430 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1241ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13c5630/d .functor OR 1, L_0x13c56f0, L_0x13c58a0, C4<0>, C4<0>; +L_0x13c5630 .delay 1 (30000,30000,30000) L_0x13c5630/d; +v0x1246f80_0 .net *"_s10", 0 0, L_0x13c56f0; 1 drivers +v0x1247060_0 .net *"_s12", 0 0, L_0x13c58a0; 1 drivers +v0x1247140_0 .net "in", 7 0, L_0x13c3630; alias, 1 drivers +v0x1247210_0 .net "ors", 1 0, L_0x13c5450; 1 drivers +v0x12472d0_0 .net "out", 0 0, L_0x13c5630; alias, 1 drivers +L_0x13c4820 .part L_0x13c3630, 0, 4; +L_0x13c5450 .concat8 [ 1 1 0 0], L_0x13c4510, L_0x13c5140; +L_0x13c5590 .part L_0x13c3630, 4, 4; +L_0x13c56f0 .part L_0x13c5450, 0, 1; +L_0x13c58a0 .part L_0x13c5450, 1, 1; +S_0x12455f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1245430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13c3cd0/d .functor OR 1, L_0x13c3d90, L_0x13c3ef0, C4<0>, C4<0>; +L_0x13c3cd0 .delay 1 (30000,30000,30000) L_0x13c3cd0/d; +L_0x13c4120/d .functor OR 1, L_0x13c4230, L_0x13c4390, C4<0>, C4<0>; +L_0x13c4120 .delay 1 (30000,30000,30000) L_0x13c4120/d; +L_0x13c4510/d .functor OR 1, L_0x13c4580, L_0x13c4730, C4<0>, C4<0>; +L_0x13c4510 .delay 1 (30000,30000,30000) L_0x13c4510/d; +v0x1245840_0 .net *"_s0", 0 0, L_0x13c3cd0; 1 drivers +v0x1245940_0 .net *"_s10", 0 0, L_0x13c4230; 1 drivers +v0x1245a20_0 .net *"_s12", 0 0, L_0x13c4390; 1 drivers +v0x1245ae0_0 .net *"_s14", 0 0, L_0x13c4580; 1 drivers +v0x1245bc0_0 .net *"_s16", 0 0, L_0x13c4730; 1 drivers +v0x1245cf0_0 .net *"_s3", 0 0, L_0x13c3d90; 1 drivers +v0x1245dd0_0 .net *"_s5", 0 0, L_0x13c3ef0; 1 drivers +v0x1245eb0_0 .net *"_s6", 0 0, L_0x13c4120; 1 drivers +v0x1245f90_0 .net "in", 3 0, L_0x13c4820; 1 drivers +v0x1246100_0 .net "ors", 1 0, L_0x13c4030; 1 drivers +v0x12461e0_0 .net "out", 0 0, L_0x13c4510; 1 drivers +L_0x13c3d90 .part L_0x13c4820, 0, 1; +L_0x13c3ef0 .part L_0x13c4820, 1, 1; +L_0x13c4030 .concat8 [ 1 1 0 0], L_0x13c3cd0, L_0x13c4120; +L_0x13c4230 .part L_0x13c4820, 2, 1; +L_0x13c4390 .part L_0x13c4820, 3, 1; +L_0x13c4580 .part L_0x13c4030, 0, 1; +L_0x13c4730 .part L_0x13c4030, 1, 1; +S_0x1246300 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1245430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13c4950/d .functor OR 1, L_0x13c49c0, L_0x13c4b20, C4<0>, C4<0>; +L_0x13c4950 .delay 1 (30000,30000,30000) L_0x13c4950/d; +L_0x13c4d50/d .functor OR 1, L_0x13c4e60, L_0x13c4fc0, C4<0>, C4<0>; +L_0x13c4d50 .delay 1 (30000,30000,30000) L_0x13c4d50/d; +L_0x13c5140/d .functor OR 1, L_0x13c51b0, L_0x13c5360, C4<0>, C4<0>; +L_0x13c5140 .delay 1 (30000,30000,30000) L_0x13c5140/d; +v0x12464c0_0 .net *"_s0", 0 0, L_0x13c4950; 1 drivers +v0x12465c0_0 .net *"_s10", 0 0, L_0x13c4e60; 1 drivers +v0x12466a0_0 .net *"_s12", 0 0, L_0x13c4fc0; 1 drivers +v0x1246760_0 .net *"_s14", 0 0, L_0x13c51b0; 1 drivers +v0x1246840_0 .net *"_s16", 0 0, L_0x13c5360; 1 drivers +v0x1246970_0 .net *"_s3", 0 0, L_0x13c49c0; 1 drivers +v0x1246a50_0 .net *"_s5", 0 0, L_0x13c4b20; 1 drivers +v0x1246b30_0 .net *"_s6", 0 0, L_0x13c4d50; 1 drivers +v0x1246c10_0 .net "in", 3 0, L_0x13c5590; 1 drivers +v0x1246d80_0 .net "ors", 1 0, L_0x13c4c60; 1 drivers +v0x1246e60_0 .net "out", 0 0, L_0x13c5140; 1 drivers +L_0x13c49c0 .part L_0x13c5590, 0, 1; +L_0x13c4b20 .part L_0x13c5590, 1, 1; +L_0x13c4c60 .concat8 [ 1 1 0 0], L_0x13c4950, L_0x13c4d50; +L_0x13c4e60 .part L_0x13c5590, 2, 1; +L_0x13c4fc0 .part L_0x13c5590, 3, 1; +L_0x13c51b0 .part L_0x13c4c60, 0, 1; +L_0x13c5360 .part L_0x13c4c60, 1, 1; +S_0x1247770 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1240890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x124cba0_0 .net "ands", 7 0, L_0x13bfbf0; 1 drivers +v0x124ccb0_0 .net "in", 7 0, L_0x13bdb70; alias, 1 drivers +v0x124cd70_0 .net "out", 0 0, L_0x13c1bf0; alias, 1 drivers +v0x124ce40_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x12479c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1247770; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x124a100_0 .net "A", 7 0, L_0x13bdb70; alias, 1 drivers +v0x124a200_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x124a2c0_0 .net *"_s0", 0 0, L_0x13be440; 1 drivers +v0x124a380_0 .net *"_s12", 0 0, L_0x13bee00; 1 drivers +v0x124a460_0 .net *"_s16", 0 0, L_0x13bf160; 1 drivers +v0x124a590_0 .net *"_s20", 0 0, L_0x13bf530; 1 drivers +v0x124a670_0 .net *"_s24", 0 0, L_0x13bf860; 1 drivers +v0x124a750_0 .net *"_s28", 0 0, L_0x13bf7f0; 1 drivers +v0x124a830_0 .net *"_s4", 0 0, L_0x13be7e0; 1 drivers +v0x124a9a0_0 .net *"_s8", 0 0, L_0x13beaf0; 1 drivers +v0x124aa80_0 .net "out", 7 0, L_0x13bfbf0; alias, 1 drivers +L_0x13be550 .part L_0x13bdb70, 0, 1; +L_0x13be740 .part v0x127a150_0, 0, 1; +L_0x13be8a0 .part L_0x13bdb70, 1, 1; +L_0x13bea00 .part v0x127a150_0, 1, 1; +L_0x13bebb0 .part L_0x13bdb70, 2, 1; +L_0x13bed10 .part v0x127a150_0, 2, 1; +L_0x13beec0 .part L_0x13bdb70, 3, 1; +L_0x13bf020 .part v0x127a150_0, 3, 1; +L_0x13bf220 .part L_0x13bdb70, 4, 1; +L_0x13bf490 .part v0x127a150_0, 4, 1; +L_0x13bf5a0 .part L_0x13bdb70, 5, 1; +L_0x13bf700 .part v0x127a150_0, 5, 1; +L_0x13bf920 .part L_0x13bdb70, 6, 1; +L_0x13bfa80 .part v0x127a150_0, 6, 1; +LS_0x13bfbf0_0_0 .concat8 [ 1 1 1 1], L_0x13be440, L_0x13be7e0, L_0x13beaf0, L_0x13bee00; +LS_0x13bfbf0_0_4 .concat8 [ 1 1 1 1], L_0x13bf160, L_0x13bf530, L_0x13bf860, L_0x13bf7f0; +L_0x13bfbf0 .concat8 [ 4 4 0 0], LS_0x13bfbf0_0_0, LS_0x13bfbf0_0_4; +L_0x13bffb0 .part L_0x13bdb70, 7, 1; +L_0x13c01a0 .part v0x127a150_0, 7, 1; +S_0x1247c00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x1247e10 .param/l "i" 0 4 54, +C4<00>; +L_0x13be440/d .functor AND 1, L_0x13be550, L_0x13be740, C4<1>, C4<1>; +L_0x13be440 .delay 1 (30000,30000,30000) L_0x13be440/d; +v0x1247ef0_0 .net *"_s0", 0 0, L_0x13be550; 1 drivers +v0x1247fd0_0 .net *"_s1", 0 0, L_0x13be740; 1 drivers +S_0x12480b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x12482c0 .param/l "i" 0 4 54, +C4<01>; +L_0x13be7e0/d .functor AND 1, L_0x13be8a0, L_0x13bea00, C4<1>, C4<1>; +L_0x13be7e0 .delay 1 (30000,30000,30000) L_0x13be7e0/d; +v0x1248380_0 .net *"_s0", 0 0, L_0x13be8a0; 1 drivers +v0x1248460_0 .net *"_s1", 0 0, L_0x13bea00; 1 drivers +S_0x1248540 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x1248780 .param/l "i" 0 4 54, +C4<010>; +L_0x13beaf0/d .functor AND 1, L_0x13bebb0, L_0x13bed10, C4<1>, C4<1>; +L_0x13beaf0 .delay 1 (30000,30000,30000) L_0x13beaf0/d; +v0x1248820_0 .net *"_s0", 0 0, L_0x13bebb0; 1 drivers +v0x1248900_0 .net *"_s1", 0 0, L_0x13bed10; 1 drivers +S_0x12489e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x1248bf0 .param/l "i" 0 4 54, +C4<011>; +L_0x13bee00/d .functor AND 1, L_0x13beec0, L_0x13bf020, C4<1>, C4<1>; +L_0x13bee00 .delay 1 (30000,30000,30000) L_0x13bee00/d; +v0x1248cb0_0 .net *"_s0", 0 0, L_0x13beec0; 1 drivers +v0x1248d90_0 .net *"_s1", 0 0, L_0x13bf020; 1 drivers +S_0x1248e70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x12490d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x13bf160/d .functor AND 1, L_0x13bf220, L_0x13bf490, C4<1>, C4<1>; +L_0x13bf160 .delay 1 (30000,30000,30000) L_0x13bf160/d; +v0x1249190_0 .net *"_s0", 0 0, L_0x13bf220; 1 drivers +v0x1249270_0 .net *"_s1", 0 0, L_0x13bf490; 1 drivers +S_0x1249350 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x1249560 .param/l "i" 0 4 54, +C4<0101>; +L_0x13bf530/d .functor AND 1, L_0x13bf5a0, L_0x13bf700, C4<1>, C4<1>; +L_0x13bf530 .delay 1 (30000,30000,30000) L_0x13bf530/d; +v0x1249620_0 .net *"_s0", 0 0, L_0x13bf5a0; 1 drivers +v0x1249700_0 .net *"_s1", 0 0, L_0x13bf700; 1 drivers +S_0x12497e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x12499f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x13bf860/d .functor AND 1, L_0x13bf920, L_0x13bfa80, C4<1>, C4<1>; +L_0x13bf860 .delay 1 (30000,30000,30000) L_0x13bf860/d; +v0x1249ab0_0 .net *"_s0", 0 0, L_0x13bf920; 1 drivers +v0x1249b90_0 .net *"_s1", 0 0, L_0x13bfa80; 1 drivers +S_0x1249c70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x12479c0; + .timescale -9 -12; +P_0x1249e80 .param/l "i" 0 4 54, +C4<0111>; +L_0x13bf7f0/d .functor AND 1, L_0x13bffb0, L_0x13c01a0, C4<1>, C4<1>; +L_0x13bf7f0 .delay 1 (30000,30000,30000) L_0x13bf7f0/d; +v0x1249f40_0 .net *"_s0", 0 0, L_0x13bffb0; 1 drivers +v0x124a020_0 .net *"_s1", 0 0, L_0x13c01a0; 1 drivers +S_0x124abe0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1247770; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13c1bf0/d .functor OR 1, L_0x13c1cb0, L_0x13c1e60, C4<0>, C4<0>; +L_0x13c1bf0 .delay 1 (30000,30000,30000) L_0x13c1bf0/d; +v0x124c730_0 .net *"_s10", 0 0, L_0x13c1cb0; 1 drivers +v0x124c810_0 .net *"_s12", 0 0, L_0x13c1e60; 1 drivers +v0x124c8f0_0 .net "in", 7 0, L_0x13bfbf0; alias, 1 drivers +v0x124c9c0_0 .net "ors", 1 0, L_0x13c1a10; 1 drivers +v0x124ca80_0 .net "out", 0 0, L_0x13c1bf0; alias, 1 drivers +L_0x13c0de0 .part L_0x13bfbf0, 0, 4; +L_0x13c1a10 .concat8 [ 1 1 0 0], L_0x13c0ad0, L_0x13c1700; +L_0x13c1b50 .part L_0x13bfbf0, 4, 4; +L_0x13c1cb0 .part L_0x13c1a10, 0, 1; +L_0x13c1e60 .part L_0x13c1a10, 1, 1; +S_0x124ada0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x124abe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13c0290/d .functor OR 1, L_0x13c0350, L_0x13c04b0, C4<0>, C4<0>; +L_0x13c0290 .delay 1 (30000,30000,30000) L_0x13c0290/d; +L_0x13c06e0/d .functor OR 1, L_0x13c07f0, L_0x13c0950, C4<0>, C4<0>; +L_0x13c06e0 .delay 1 (30000,30000,30000) L_0x13c06e0/d; +L_0x13c0ad0/d .functor OR 1, L_0x13c0b40, L_0x13c0cf0, C4<0>, C4<0>; +L_0x13c0ad0 .delay 1 (30000,30000,30000) L_0x13c0ad0/d; +v0x124aff0_0 .net *"_s0", 0 0, L_0x13c0290; 1 drivers +v0x124b0f0_0 .net *"_s10", 0 0, L_0x13c07f0; 1 drivers +v0x124b1d0_0 .net *"_s12", 0 0, L_0x13c0950; 1 drivers +v0x124b290_0 .net *"_s14", 0 0, L_0x13c0b40; 1 drivers +v0x124b370_0 .net *"_s16", 0 0, L_0x13c0cf0; 1 drivers +v0x124b4a0_0 .net *"_s3", 0 0, L_0x13c0350; 1 drivers +v0x124b580_0 .net *"_s5", 0 0, L_0x13c04b0; 1 drivers +v0x124b660_0 .net *"_s6", 0 0, L_0x13c06e0; 1 drivers +v0x124b740_0 .net "in", 3 0, L_0x13c0de0; 1 drivers +v0x124b8b0_0 .net "ors", 1 0, L_0x13c05f0; 1 drivers +v0x124b990_0 .net "out", 0 0, L_0x13c0ad0; 1 drivers +L_0x13c0350 .part L_0x13c0de0, 0, 1; +L_0x13c04b0 .part L_0x13c0de0, 1, 1; +L_0x13c05f0 .concat8 [ 1 1 0 0], L_0x13c0290, L_0x13c06e0; +L_0x13c07f0 .part L_0x13c0de0, 2, 1; +L_0x13c0950 .part L_0x13c0de0, 3, 1; +L_0x13c0b40 .part L_0x13c05f0, 0, 1; +L_0x13c0cf0 .part L_0x13c05f0, 1, 1; +S_0x124bab0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x124abe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13c0f10/d .functor OR 1, L_0x13c0f80, L_0x13c10e0, C4<0>, C4<0>; +L_0x13c0f10 .delay 1 (30000,30000,30000) L_0x13c0f10/d; +L_0x13c1310/d .functor OR 1, L_0x13c1420, L_0x13c1580, C4<0>, C4<0>; +L_0x13c1310 .delay 1 (30000,30000,30000) L_0x13c1310/d; +L_0x13c1700/d .functor OR 1, L_0x13c1770, L_0x13c1920, C4<0>, C4<0>; +L_0x13c1700 .delay 1 (30000,30000,30000) L_0x13c1700/d; +v0x124bc70_0 .net *"_s0", 0 0, L_0x13c0f10; 1 drivers +v0x124bd70_0 .net *"_s10", 0 0, L_0x13c1420; 1 drivers +v0x124be50_0 .net *"_s12", 0 0, L_0x13c1580; 1 drivers +v0x124bf10_0 .net *"_s14", 0 0, L_0x13c1770; 1 drivers +v0x124bff0_0 .net *"_s16", 0 0, L_0x13c1920; 1 drivers +v0x124c120_0 .net *"_s3", 0 0, L_0x13c0f80; 1 drivers +v0x124c200_0 .net *"_s5", 0 0, L_0x13c10e0; 1 drivers +v0x124c2e0_0 .net *"_s6", 0 0, L_0x13c1310; 1 drivers +v0x124c3c0_0 .net "in", 3 0, L_0x13c1b50; 1 drivers +v0x124c530_0 .net "ors", 1 0, L_0x13c1220; 1 drivers +v0x124c610_0 .net "out", 0 0, L_0x13c1700; 1 drivers +L_0x13c0f80 .part L_0x13c1b50, 0, 1; +L_0x13c10e0 .part L_0x13c1b50, 1, 1; +L_0x13c1220 .concat8 [ 1 1 0 0], L_0x13c0f10, L_0x13c1310; +L_0x13c1420 .part L_0x13c1b50, 2, 1; +L_0x13c1580 .part L_0x13c1b50, 3, 1; +L_0x13c1770 .part L_0x13c1220, 0, 1; +L_0x13c1920 .part L_0x13c1220, 1, 1; +S_0x124cf20 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1240890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x13bca20/d .functor XNOR 1, L_0x13c5a90, L_0x131ab30, C4<0>, C4<0>; +L_0x13bca20 .delay 1 (20000,20000,20000) L_0x13bca20/d; +L_0x13bcba0/d .functor AND 1, L_0x13c5a90, L_0x13bb710, C4<1>, C4<1>; +L_0x13bcba0 .delay 1 (30000,30000,30000) L_0x13bcba0/d; +L_0x13bcd00/d .functor AND 1, L_0x13bca20, L_0x13bb390, C4<1>, C4<1>; +L_0x13bcd00 .delay 1 (30000,30000,30000) L_0x13bcd00/d; +L_0x13bce10/d .functor OR 1, L_0x13bcd00, L_0x13bcba0, C4<0>, C4<0>; +L_0x13bce10 .delay 1 (30000,30000,30000) L_0x13bce10/d; +v0x124d1d0_0 .net "a", 0 0, L_0x13c5a90; alias, 1 drivers +v0x124d2c0_0 .net "a_", 0 0, L_0x13b0e40; alias, 1 drivers +v0x124d380_0 .net "b", 0 0, L_0x131ab30; alias, 1 drivers +v0x124d470_0 .net "b_", 0 0, L_0x13bb710; alias, 1 drivers +v0x124d510_0 .net "carryin", 0 0, L_0x13bb390; alias, 1 drivers +v0x124d650_0 .net "eq", 0 0, L_0x13bca20; 1 drivers +v0x124d710_0 .net "lt", 0 0, L_0x13bcba0; 1 drivers +v0x124d7d0_0 .net "out", 0 0, L_0x13bce10; 1 drivers +v0x124d890_0 .net "w0", 0 0, L_0x13bcd00; 1 drivers +S_0x124dae0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1240890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13bc600/d .functor OR 1, L_0x13bc100, L_0x124ed40, C4<0>, C4<0>; +L_0x13bc600 .delay 1 (30000,30000,30000) L_0x13bc600/d; +v0x124e8d0_0 .net "a", 0 0, L_0x13c5a90; alias, 1 drivers +v0x124ea20_0 .net "b", 0 0, L_0x13bb710; alias, 1 drivers +v0x124eae0_0 .net "c1", 0 0, L_0x13bc100; 1 drivers +v0x124eb80_0 .net "c2", 0 0, L_0x124ed40; 1 drivers +v0x124ec50_0 .net "carryin", 0 0, L_0x13bb390; alias, 1 drivers +v0x124edd0_0 .net "carryout", 0 0, L_0x13bc600; 1 drivers +v0x124ee70_0 .net "s1", 0 0, L_0x13bc040; 1 drivers +v0x124ef10_0 .net "sum", 0 0, L_0x13bc260; 1 drivers +S_0x124dd30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x124dae0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13bc040/d .functor XOR 1, L_0x13c5a90, L_0x13bb710, C4<0>, C4<0>; +L_0x13bc040 .delay 1 (30000,30000,30000) L_0x13bc040/d; +L_0x13bc100/d .functor AND 1, L_0x13c5a90, L_0x13bb710, C4<1>, C4<1>; +L_0x13bc100 .delay 1 (30000,30000,30000) L_0x13bc100/d; +v0x124df90_0 .net "a", 0 0, L_0x13c5a90; alias, 1 drivers +v0x124e050_0 .net "b", 0 0, L_0x13bb710; alias, 1 drivers +v0x124e110_0 .net "carryout", 0 0, L_0x13bc100; alias, 1 drivers +v0x124e1b0_0 .net "sum", 0 0, L_0x13bc040; alias, 1 drivers +S_0x124e2e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x124dae0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13bc260/d .functor XOR 1, L_0x13bc040, L_0x13bb390, C4<0>, C4<0>; +L_0x13bc260 .delay 1 (30000,30000,30000) L_0x13bc260/d; +L_0x124ed40/d .functor AND 1, L_0x13bc040, L_0x13bb390, C4<1>, C4<1>; +L_0x124ed40 .delay 1 (30000,30000,30000) L_0x124ed40/d; +v0x124e540_0 .net "a", 0 0, L_0x13bc040; alias, 1 drivers +v0x124e610_0 .net "b", 0 0, L_0x13bb390; alias, 1 drivers +v0x124e6b0_0 .net "carryout", 0 0, L_0x124ed40; alias, 1 drivers +v0x124e780_0 .net "sum", 0 0, L_0x13bc260; alias, 1 drivers +S_0x1250fa0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x12405c0; + .timescale -9 -12; +L_0x2ac43288a908 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a950 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c5b30/d .functor OR 1, L_0x2ac43288a908, L_0x2ac43288a950, C4<0>, C4<0>; +L_0x13c5b30 .delay 1 (30000,30000,30000) L_0x13c5b30/d; +v0x1251190_0 .net/2u *"_s0", 0 0, L_0x2ac43288a908; 1 drivers +v0x1251270_0 .net/2u *"_s2", 0 0, L_0x2ac43288a950; 1 drivers +S_0x1251350 .scope generate, "alu_slices[31]" "alu_slices[31]" 3 39, 3 39 0, S_0xc4eec0; + .timescale -9 -12; +P_0x1251560 .param/l "i" 0 3 39, +C4<011111>; +S_0x1251620 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x1251350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x131aec0/d .functor NOT 1, L_0x13d15c0, C4<0>, C4<0>, C4<0>; +L_0x131aec0 .delay 1 (10000,10000,10000) L_0x131aec0/d; +L_0x13bb520/d .functor NOT 1, L_0x13d09b0, C4<0>, C4<0>, C4<0>; +L_0x13bb520 .delay 1 (10000,10000,10000) L_0x13bb520/d; +L_0x13c7390/d .functor XOR 1, L_0x13d15c0, L_0x13d09b0, C4<0>, C4<0>; +L_0x13c7390 .delay 1 (30000,30000,30000) L_0x13c7390/d; +L_0x2ac43288a998 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288a9e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c7450/d .functor OR 1, L_0x2ac43288a998, L_0x2ac43288a9e0, C4<0>, C4<0>; +L_0x13c7450 .delay 1 (30000,30000,30000) L_0x13c7450/d; +L_0x2ac43288aa28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288aa70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c7bf0/d .functor OR 1, L_0x2ac43288aa28, L_0x2ac43288aa70, C4<0>, C4<0>; +L_0x13c7bf0 .delay 1 (30000,30000,30000) L_0x13c7bf0/d; +L_0x13c7df0/d .functor AND 1, L_0x13d15c0, L_0x13d09b0, C4<1>, C4<1>; +L_0x13c7df0 .delay 1 (30000,30000,30000) L_0x13c7df0/d; +L_0x2ac43288aab8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288ab00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c7eb0/d .functor OR 1, L_0x2ac43288aab8, L_0x2ac43288ab00, C4<0>, C4<0>; +L_0x13c7eb0 .delay 1 (30000,30000,30000) L_0x13c7eb0/d; +L_0x13c80b0/d .functor NAND 1, L_0x13d15c0, L_0x13d09b0, C4<1>, C4<1>; +L_0x13c80b0 .delay 1 (20000,20000,20000) L_0x13c80b0/d; +L_0x2ac43288ab48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288ab90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c81c0/d .functor OR 1, L_0x2ac43288ab48, L_0x2ac43288ab90, C4<0>, C4<0>; +L_0x13c81c0 .delay 1 (30000,30000,30000) L_0x13c81c0/d; +L_0x13c8370/d .functor NOR 1, L_0x13d15c0, L_0x13d09b0, C4<0>, C4<0>; +L_0x13c8370 .delay 1 (20000,20000,20000) L_0x13c8370/d; +L_0x2ac43288abd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288ac20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c8640/d .functor OR 1, L_0x2ac43288abd8, L_0x2ac43288ac20, C4<0>, C4<0>; +L_0x13c8640 .delay 1 (30000,30000,30000) L_0x13c8640/d; +L_0x13c8a40/d .functor OR 1, L_0x13d15c0, L_0x13d09b0, C4<0>, C4<0>; +L_0x13c8a40 .delay 1 (30000,30000,30000) L_0x13c8a40/d; +L_0x2ac43288ac68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288acb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c8ee0/d .functor OR 1, L_0x2ac43288ac68, L_0x2ac43288acb0, C4<0>, C4<0>; +L_0x13c8ee0 .delay 1 (30000,30000,30000) L_0x13c8ee0/d; +L_0x13d0640/d .functor NOT 1, L_0x13cc8a0, C4<0>, C4<0>, C4<0>; +L_0x13d0640 .delay 1 (10000,10000,10000) L_0x13d0640/d; +v0x125fd50_0 .net "A", 0 0, L_0x13d15c0; 1 drivers +v0x125fe10_0 .net "A_", 0 0, L_0x131aec0; 1 drivers +v0x125fed0_0 .net "B", 0 0, L_0x13d09b0; 1 drivers +v0x125ffa0_0 .net "B_", 0 0, L_0x13bb520; 1 drivers +v0x1260040_0 .net *"_s11", 0 0, L_0x13c7450; 1 drivers +v0x1260130_0 .net/2s *"_s13", 0 0, L_0x2ac43288a998; 1 drivers +v0x12601f0_0 .net/2s *"_s15", 0 0, L_0x2ac43288a9e0; 1 drivers +v0x12602d0_0 .net *"_s19", 0 0, L_0x13c7bf0; 1 drivers +v0x12603b0_0 .net/2s *"_s21", 0 0, L_0x2ac43288aa28; 1 drivers +v0x1260520_0 .net/2s *"_s23", 0 0, L_0x2ac43288aa70; 1 drivers +v0x1260600_0 .net *"_s25", 0 0, L_0x13c7df0; 1 drivers +v0x12606e0_0 .net *"_s28", 0 0, L_0x13c7eb0; 1 drivers +v0x12607c0_0 .net/2s *"_s30", 0 0, L_0x2ac43288aab8; 1 drivers +v0x12608a0_0 .net/2s *"_s32", 0 0, L_0x2ac43288ab00; 1 drivers +v0x1260980_0 .net *"_s34", 0 0, L_0x13c80b0; 1 drivers +v0x1260a60_0 .net *"_s37", 0 0, L_0x13c81c0; 1 drivers +v0x1260b40_0 .net/2s *"_s39", 0 0, L_0x2ac43288ab48; 1 drivers +v0x1260cf0_0 .net/2s *"_s41", 0 0, L_0x2ac43288ab90; 1 drivers +v0x1260d90_0 .net *"_s43", 0 0, L_0x13c8370; 1 drivers +v0x1260e70_0 .net *"_s46", 0 0, L_0x13c8640; 1 drivers +v0x1260f50_0 .net/2s *"_s48", 0 0, L_0x2ac43288abd8; 1 drivers +v0x1261030_0 .net/2s *"_s50", 0 0, L_0x2ac43288ac20; 1 drivers +v0x1261110_0 .net *"_s52", 0 0, L_0x13c8a40; 1 drivers +v0x12611f0_0 .net *"_s56", 0 0, L_0x13c8ee0; 1 drivers +v0x12612d0_0 .net/2s *"_s59", 0 0, L_0x2ac43288ac68; 1 drivers +v0x12613b0_0 .net/2s *"_s61", 0 0, L_0x2ac43288acb0; 1 drivers +v0x1261490_0 .net *"_s8", 0 0, L_0x13c7390; 1 drivers +v0x1261570_0 .net "carryin", 0 0, L_0x13d0a50; 1 drivers +v0x1261610_0 .net "carryout", 0 0, L_0x13d02e0; 1 drivers +v0x12616b0_0 .net "carryouts", 7 0, L_0x13c8b50; 1 drivers +v0x12617c0_0 .net "command", 7 0, v0x127a150_0; alias, 1 drivers +v0x1261880_0 .net "result", 0 0, L_0x13cc8a0; 1 drivers +v0x1261970_0 .net "results", 7 0, L_0x13c8810; 1 drivers +v0x1260c50_0 .net "zero", 0 0, L_0x13d0640; 1 drivers +LS_0x13c8810_0_0 .concat8 [ 1 1 1 1], L_0x13c6860, L_0x13c6e90, L_0x13c7390, L_0x13c7bf0; +LS_0x13c8810_0_4 .concat8 [ 1 1 1 1], L_0x13c7df0, L_0x13c80b0, L_0x13c8370, L_0x13c8a40; +L_0x13c8810 .concat8 [ 4 4 0 0], LS_0x13c8810_0_0, LS_0x13c8810_0_4; +LS_0x13c8b50_0_0 .concat8 [ 1 1 1 1], L_0x13c6b10, L_0x13c7230, L_0x13c7450, L_0x13c7a40; +LS_0x13c8b50_0_4 .concat8 [ 1 1 1 1], L_0x13c7eb0, L_0x13c81c0, L_0x13c8640, L_0x13c8ee0; +L_0x13c8b50 .concat8 [ 4 4 0 0], LS_0x13c8b50_0_0, LS_0x13c8b50_0_4; +S_0x12518a0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1251620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13c6b10/d .functor OR 1, L_0x13c65f0, L_0x13c69b0, C4<0>, C4<0>; +L_0x13c6b10 .delay 1 (30000,30000,30000) L_0x13c6b10/d; +v0x12526d0_0 .net "a", 0 0, L_0x13d15c0; alias, 1 drivers +v0x1252790_0 .net "b", 0 0, L_0x13d09b0; alias, 1 drivers +v0x1252860_0 .net "c1", 0 0, L_0x13c65f0; 1 drivers +v0x1252960_0 .net "c2", 0 0, L_0x13c69b0; 1 drivers +v0x1252a30_0 .net "carryin", 0 0, L_0x13d0a50; alias, 1 drivers +v0x1252b20_0 .net "carryout", 0 0, L_0x13c6b10; 1 drivers +v0x1252bc0_0 .net "s1", 0 0, L_0x13c6530; 1 drivers +v0x1252cb0_0 .net "sum", 0 0, L_0x13c6860; 1 drivers +S_0x1251b10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x12518a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13c6530/d .functor XOR 1, L_0x13d15c0, L_0x13d09b0, C4<0>, C4<0>; +L_0x13c6530 .delay 1 (30000,30000,30000) L_0x13c6530/d; +L_0x13c65f0/d .functor AND 1, L_0x13d15c0, L_0x13d09b0, C4<1>, C4<1>; +L_0x13c65f0 .delay 1 (30000,30000,30000) L_0x13c65f0/d; +v0x1251d70_0 .net "a", 0 0, L_0x13d15c0; alias, 1 drivers +v0x1251e50_0 .net "b", 0 0, L_0x13d09b0; alias, 1 drivers +v0x1251f10_0 .net "carryout", 0 0, L_0x13c65f0; alias, 1 drivers +v0x1251fb0_0 .net "sum", 0 0, L_0x13c6530; alias, 1 drivers +S_0x12520f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x12518a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13c6860/d .functor XOR 1, L_0x13c6530, L_0x13d0a50, C4<0>, C4<0>; +L_0x13c6860 .delay 1 (30000,30000,30000) L_0x13c6860/d; +L_0x13c69b0/d .functor AND 1, L_0x13c6530, L_0x13d0a50, C4<1>, C4<1>; +L_0x13c69b0 .delay 1 (30000,30000,30000) L_0x13c69b0/d; +v0x1252350_0 .net "a", 0 0, L_0x13c6530; alias, 1 drivers +v0x12523f0_0 .net "b", 0 0, L_0x13d0a50; alias, 1 drivers +v0x1252490_0 .net "carryout", 0 0, L_0x13c69b0; alias, 1 drivers +v0x1252560_0 .net "sum", 0 0, L_0x13c6860; alias, 1 drivers +S_0x1252d80 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x1251620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1258170_0 .net "ands", 7 0, L_0x13ce2e0; 1 drivers +v0x1258280_0 .net "in", 7 0, L_0x13c8b50; alias, 1 drivers +v0x1258340_0 .net "out", 0 0, L_0x13d02e0; alias, 1 drivers +v0x1258410_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1252fa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1252d80; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x12556d0_0 .net "A", 7 0, L_0x13c8b50; alias, 1 drivers +v0x12557d0_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x1255890_0 .net *"_s0", 0 0, L_0x13ccc00; 1 drivers +v0x1255950_0 .net *"_s12", 0 0, L_0x13cd570; 1 drivers +v0x1255a30_0 .net *"_s16", 0 0, L_0x13cd8d0; 1 drivers +v0x1255b60_0 .net *"_s20", 0 0, L_0x13cdca0; 1 drivers +v0x1255c40_0 .net *"_s24", 0 0, L_0x13cdfd0; 1 drivers +v0x1255d20_0 .net *"_s28", 0 0, L_0x13cdf60; 1 drivers +v0x1255e00_0 .net *"_s4", 0 0, L_0x13ccf50; 1 drivers +v0x1255f70_0 .net *"_s8", 0 0, L_0x13cd260; 1 drivers +v0x1256050_0 .net "out", 7 0, L_0x13ce2e0; alias, 1 drivers +L_0x13cccc0 .part L_0x13c8b50, 0, 1; +L_0x13cceb0 .part v0x127a150_0, 0, 1; +L_0x13cd010 .part L_0x13c8b50, 1, 1; +L_0x13cd170 .part v0x127a150_0, 1, 1; +L_0x13cd320 .part L_0x13c8b50, 2, 1; +L_0x13cd480 .part v0x127a150_0, 2, 1; +L_0x13cd630 .part L_0x13c8b50, 3, 1; +L_0x13cd790 .part v0x127a150_0, 3, 1; +L_0x13cd990 .part L_0x13c8b50, 4, 1; +L_0x13cdc00 .part v0x127a150_0, 4, 1; +L_0x13cdd10 .part L_0x13c8b50, 5, 1; +L_0x13cde70 .part v0x127a150_0, 5, 1; +L_0x13ce090 .part L_0x13c8b50, 6, 1; +L_0x13ce1f0 .part v0x127a150_0, 6, 1; +LS_0x13ce2e0_0_0 .concat8 [ 1 1 1 1], L_0x13ccc00, L_0x13ccf50, L_0x13cd260, L_0x13cd570; +LS_0x13ce2e0_0_4 .concat8 [ 1 1 1 1], L_0x13cd8d0, L_0x13cdca0, L_0x13cdfd0, L_0x13cdf60; +L_0x13ce2e0 .concat8 [ 4 4 0 0], LS_0x13ce2e0_0_0, LS_0x13ce2e0_0_4; +L_0x13ce6a0 .part L_0x13c8b50, 7, 1; +L_0x13ce890 .part v0x127a150_0, 7, 1; +S_0x1253200 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x1253410 .param/l "i" 0 4 54, +C4<00>; +L_0x13ccc00/d .functor AND 1, L_0x13cccc0, L_0x13cceb0, C4<1>, C4<1>; +L_0x13ccc00 .delay 1 (30000,30000,30000) L_0x13ccc00/d; +v0x12534f0_0 .net *"_s0", 0 0, L_0x13cccc0; 1 drivers +v0x12535d0_0 .net *"_s1", 0 0, L_0x13cceb0; 1 drivers +S_0x12536b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x12538c0 .param/l "i" 0 4 54, +C4<01>; +L_0x13ccf50/d .functor AND 1, L_0x13cd010, L_0x13cd170, C4<1>, C4<1>; +L_0x13ccf50 .delay 1 (30000,30000,30000) L_0x13ccf50/d; +v0x1253980_0 .net *"_s0", 0 0, L_0x13cd010; 1 drivers +v0x1253a60_0 .net *"_s1", 0 0, L_0x13cd170; 1 drivers +S_0x1253b40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x1253d50 .param/l "i" 0 4 54, +C4<010>; +L_0x13cd260/d .functor AND 1, L_0x13cd320, L_0x13cd480, C4<1>, C4<1>; +L_0x13cd260 .delay 1 (30000,30000,30000) L_0x13cd260/d; +v0x1253df0_0 .net *"_s0", 0 0, L_0x13cd320; 1 drivers +v0x1253ed0_0 .net *"_s1", 0 0, L_0x13cd480; 1 drivers +S_0x1253fb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x12541c0 .param/l "i" 0 4 54, +C4<011>; +L_0x13cd570/d .functor AND 1, L_0x13cd630, L_0x13cd790, C4<1>, C4<1>; +L_0x13cd570 .delay 1 (30000,30000,30000) L_0x13cd570/d; +v0x1254280_0 .net *"_s0", 0 0, L_0x13cd630; 1 drivers +v0x1254360_0 .net *"_s1", 0 0, L_0x13cd790; 1 drivers +S_0x1254440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x12546a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x13cd8d0/d .functor AND 1, L_0x13cd990, L_0x13cdc00, C4<1>, C4<1>; +L_0x13cd8d0 .delay 1 (30000,30000,30000) L_0x13cd8d0/d; +v0x1254760_0 .net *"_s0", 0 0, L_0x13cd990; 1 drivers +v0x1254840_0 .net *"_s1", 0 0, L_0x13cdc00; 1 drivers +S_0x1254920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x1254b30 .param/l "i" 0 4 54, +C4<0101>; +L_0x13cdca0/d .functor AND 1, L_0x13cdd10, L_0x13cde70, C4<1>, C4<1>; +L_0x13cdca0 .delay 1 (30000,30000,30000) L_0x13cdca0/d; +v0x1254bf0_0 .net *"_s0", 0 0, L_0x13cdd10; 1 drivers +v0x1254cd0_0 .net *"_s1", 0 0, L_0x13cde70; 1 drivers +S_0x1254db0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x1254fc0 .param/l "i" 0 4 54, +C4<0110>; +L_0x13cdfd0/d .functor AND 1, L_0x13ce090, L_0x13ce1f0, C4<1>, C4<1>; +L_0x13cdfd0 .delay 1 (30000,30000,30000) L_0x13cdfd0/d; +v0x1255080_0 .net *"_s0", 0 0, L_0x13ce090; 1 drivers +v0x1255160_0 .net *"_s1", 0 0, L_0x13ce1f0; 1 drivers +S_0x1255240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1252fa0; + .timescale -9 -12; +P_0x1255450 .param/l "i" 0 4 54, +C4<0111>; +L_0x13cdf60/d .functor AND 1, L_0x13ce6a0, L_0x13ce890, C4<1>, C4<1>; +L_0x13cdf60 .delay 1 (30000,30000,30000) L_0x13cdf60/d; +v0x1255510_0 .net *"_s0", 0 0, L_0x13ce6a0; 1 drivers +v0x12555f0_0 .net *"_s1", 0 0, L_0x13ce890; 1 drivers +S_0x12561b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1252d80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13d02e0/d .functor OR 1, L_0x13d03a0, L_0x13d0550, C4<0>, C4<0>; +L_0x13d02e0 .delay 1 (30000,30000,30000) L_0x13d02e0/d; +v0x1257d00_0 .net *"_s10", 0 0, L_0x13d03a0; 1 drivers +v0x1257de0_0 .net *"_s12", 0 0, L_0x13d0550; 1 drivers +v0x1257ec0_0 .net "in", 7 0, L_0x13ce2e0; alias, 1 drivers +v0x1257f90_0 .net "ors", 1 0, L_0x13d0100; 1 drivers +v0x1258050_0 .net "out", 0 0, L_0x13d02e0; alias, 1 drivers +L_0x13cf4d0 .part L_0x13ce2e0, 0, 4; +L_0x13d0100 .concat8 [ 1 1 0 0], L_0x13cf1c0, L_0x13cfdf0; +L_0x13d0240 .part L_0x13ce2e0, 4, 4; +L_0x13d03a0 .part L_0x13d0100, 0, 1; +L_0x13d0550 .part L_0x13d0100, 1, 1; +S_0x1256370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x12561b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13ce980/d .functor OR 1, L_0x13cea40, L_0x13ceba0, C4<0>, C4<0>; +L_0x13ce980 .delay 1 (30000,30000,30000) L_0x13ce980/d; +L_0x13cedd0/d .functor OR 1, L_0x13ceee0, L_0x13cf040, C4<0>, C4<0>; +L_0x13cedd0 .delay 1 (30000,30000,30000) L_0x13cedd0/d; +L_0x13cf1c0/d .functor OR 1, L_0x13cf230, L_0x13cf3e0, C4<0>, C4<0>; +L_0x13cf1c0 .delay 1 (30000,30000,30000) L_0x13cf1c0/d; +v0x12565c0_0 .net *"_s0", 0 0, L_0x13ce980; 1 drivers +v0x12566c0_0 .net *"_s10", 0 0, L_0x13ceee0; 1 drivers +v0x12567a0_0 .net *"_s12", 0 0, L_0x13cf040; 1 drivers +v0x1256860_0 .net *"_s14", 0 0, L_0x13cf230; 1 drivers +v0x1256940_0 .net *"_s16", 0 0, L_0x13cf3e0; 1 drivers +v0x1256a70_0 .net *"_s3", 0 0, L_0x13cea40; 1 drivers +v0x1256b50_0 .net *"_s5", 0 0, L_0x13ceba0; 1 drivers +v0x1256c30_0 .net *"_s6", 0 0, L_0x13cedd0; 1 drivers +v0x1256d10_0 .net "in", 3 0, L_0x13cf4d0; 1 drivers +v0x1256e80_0 .net "ors", 1 0, L_0x13cece0; 1 drivers +v0x1256f60_0 .net "out", 0 0, L_0x13cf1c0; 1 drivers +L_0x13cea40 .part L_0x13cf4d0, 0, 1; +L_0x13ceba0 .part L_0x13cf4d0, 1, 1; +L_0x13cece0 .concat8 [ 1 1 0 0], L_0x13ce980, L_0x13cedd0; +L_0x13ceee0 .part L_0x13cf4d0, 2, 1; +L_0x13cf040 .part L_0x13cf4d0, 3, 1; +L_0x13cf230 .part L_0x13cece0, 0, 1; +L_0x13cf3e0 .part L_0x13cece0, 1, 1; +S_0x1257080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x12561b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13cf600/d .functor OR 1, L_0x13cf670, L_0x13cf7d0, C4<0>, C4<0>; +L_0x13cf600 .delay 1 (30000,30000,30000) L_0x13cf600/d; +L_0x13cfa00/d .functor OR 1, L_0x13cfb10, L_0x13cfc70, C4<0>, C4<0>; +L_0x13cfa00 .delay 1 (30000,30000,30000) L_0x13cfa00/d; +L_0x13cfdf0/d .functor OR 1, L_0x13cfe60, L_0x13d0010, C4<0>, C4<0>; +L_0x13cfdf0 .delay 1 (30000,30000,30000) L_0x13cfdf0/d; +v0x1257240_0 .net *"_s0", 0 0, L_0x13cf600; 1 drivers +v0x1257340_0 .net *"_s10", 0 0, L_0x13cfb10; 1 drivers +v0x1257420_0 .net *"_s12", 0 0, L_0x13cfc70; 1 drivers +v0x12574e0_0 .net *"_s14", 0 0, L_0x13cfe60; 1 drivers +v0x12575c0_0 .net *"_s16", 0 0, L_0x13d0010; 1 drivers +v0x12576f0_0 .net *"_s3", 0 0, L_0x13cf670; 1 drivers +v0x12577d0_0 .net *"_s5", 0 0, L_0x13cf7d0; 1 drivers +v0x12578b0_0 .net *"_s6", 0 0, L_0x13cfa00; 1 drivers +v0x1257990_0 .net "in", 3 0, L_0x13d0240; 1 drivers +v0x1257b00_0 .net "ors", 1 0, L_0x13cf910; 1 drivers +v0x1257be0_0 .net "out", 0 0, L_0x13cfdf0; 1 drivers +L_0x13cf670 .part L_0x13d0240, 0, 1; +L_0x13cf7d0 .part L_0x13d0240, 1, 1; +L_0x13cf910 .concat8 [ 1 1 0 0], L_0x13cf600, L_0x13cfa00; +L_0x13cfb10 .part L_0x13d0240, 2, 1; +L_0x13cfc70 .part L_0x13d0240, 3, 1; +L_0x13cfe60 .part L_0x13cf910, 0, 1; +L_0x13d0010 .part L_0x13cf910, 1, 1; +S_0x12584f0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x1251620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x125d920_0 .net "ands", 7 0, L_0x13ca8a0; 1 drivers +v0x125da30_0 .net "in", 7 0, L_0x13c8810; alias, 1 drivers +v0x125daf0_0 .net "out", 0 0, L_0x13cc8a0; alias, 1 drivers +v0x125dbc0_0 .net "sel", 7 0, v0x127a150_0; alias, 1 drivers +S_0x1258740 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x12584f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x125ae80_0 .net "A", 7 0, L_0x13c8810; alias, 1 drivers +v0x125af80_0 .net "B", 7 0, v0x127a150_0; alias, 1 drivers +v0x125b040_0 .net *"_s0", 0 0, L_0x13c9090; 1 drivers +v0x125b100_0 .net *"_s12", 0 0, L_0x13c9a50; 1 drivers +v0x125b1e0_0 .net *"_s16", 0 0, L_0x13c9db0; 1 drivers +v0x125b310_0 .net *"_s20", 0 0, L_0x13ca1e0; 1 drivers +v0x125b3f0_0 .net *"_s24", 0 0, L_0x13ca510; 1 drivers +v0x125b4d0_0 .net *"_s28", 0 0, L_0x13ca4a0; 1 drivers +v0x125b5b0_0 .net *"_s4", 0 0, L_0x13c9430; 1 drivers +v0x125b720_0 .net *"_s8", 0 0, L_0x13c9740; 1 drivers +v0x125b800_0 .net "out", 7 0, L_0x13ca8a0; alias, 1 drivers +L_0x13c91a0 .part L_0x13c8810, 0, 1; +L_0x13c9390 .part v0x127a150_0, 0, 1; +L_0x13c94f0 .part L_0x13c8810, 1, 1; +L_0x13c9650 .part v0x127a150_0, 1, 1; +L_0x13c9800 .part L_0x13c8810, 2, 1; +L_0x13c9960 .part v0x127a150_0, 2, 1; +L_0x13c9b10 .part L_0x13c8810, 3, 1; +L_0x13c9c70 .part v0x127a150_0, 3, 1; +L_0x13c9e70 .part L_0x13c8810, 4, 1; +L_0x13ca0e0 .part v0x127a150_0, 4, 1; +L_0x13ca250 .part L_0x13c8810, 5, 1; +L_0x13ca3b0 .part v0x127a150_0, 5, 1; +L_0x13ca5d0 .part L_0x13c8810, 6, 1; +L_0x13ca730 .part v0x127a150_0, 6, 1; +LS_0x13ca8a0_0_0 .concat8 [ 1 1 1 1], L_0x13c9090, L_0x13c9430, L_0x13c9740, L_0x13c9a50; +LS_0x13ca8a0_0_4 .concat8 [ 1 1 1 1], L_0x13c9db0, L_0x13ca1e0, L_0x13ca510, L_0x13ca4a0; +L_0x13ca8a0 .concat8 [ 4 4 0 0], LS_0x13ca8a0_0_0, LS_0x13ca8a0_0_4; +L_0x13cac60 .part L_0x13c8810, 7, 1; +L_0x13cae50 .part v0x127a150_0, 7, 1; +S_0x1258980 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x1258b90 .param/l "i" 0 4 54, +C4<00>; +L_0x13c9090/d .functor AND 1, L_0x13c91a0, L_0x13c9390, C4<1>, C4<1>; +L_0x13c9090 .delay 1 (30000,30000,30000) L_0x13c9090/d; +v0x1258c70_0 .net *"_s0", 0 0, L_0x13c91a0; 1 drivers +v0x1258d50_0 .net *"_s1", 0 0, L_0x13c9390; 1 drivers +S_0x1258e30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x1259040 .param/l "i" 0 4 54, +C4<01>; +L_0x13c9430/d .functor AND 1, L_0x13c94f0, L_0x13c9650, C4<1>, C4<1>; +L_0x13c9430 .delay 1 (30000,30000,30000) L_0x13c9430/d; +v0x1259100_0 .net *"_s0", 0 0, L_0x13c94f0; 1 drivers +v0x12591e0_0 .net *"_s1", 0 0, L_0x13c9650; 1 drivers +S_0x12592c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x1259500 .param/l "i" 0 4 54, +C4<010>; +L_0x13c9740/d .functor AND 1, L_0x13c9800, L_0x13c9960, C4<1>, C4<1>; +L_0x13c9740 .delay 1 (30000,30000,30000) L_0x13c9740/d; +v0x12595a0_0 .net *"_s0", 0 0, L_0x13c9800; 1 drivers +v0x1259680_0 .net *"_s1", 0 0, L_0x13c9960; 1 drivers +S_0x1259760 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x1259970 .param/l "i" 0 4 54, +C4<011>; +L_0x13c9a50/d .functor AND 1, L_0x13c9b10, L_0x13c9c70, C4<1>, C4<1>; +L_0x13c9a50 .delay 1 (30000,30000,30000) L_0x13c9a50/d; +v0x1259a30_0 .net *"_s0", 0 0, L_0x13c9b10; 1 drivers +v0x1259b10_0 .net *"_s1", 0 0, L_0x13c9c70; 1 drivers +S_0x1259bf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x1259e50 .param/l "i" 0 4 54, +C4<0100>; +L_0x13c9db0/d .functor AND 1, L_0x13c9e70, L_0x13ca0e0, C4<1>, C4<1>; +L_0x13c9db0 .delay 1 (30000,30000,30000) L_0x13c9db0/d; +v0x1259f10_0 .net *"_s0", 0 0, L_0x13c9e70; 1 drivers +v0x1259ff0_0 .net *"_s1", 0 0, L_0x13ca0e0; 1 drivers +S_0x125a0d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x125a2e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13ca1e0/d .functor AND 1, L_0x13ca250, L_0x13ca3b0, C4<1>, C4<1>; +L_0x13ca1e0 .delay 1 (30000,30000,30000) L_0x13ca1e0/d; +v0x125a3a0_0 .net *"_s0", 0 0, L_0x13ca250; 1 drivers +v0x125a480_0 .net *"_s1", 0 0, L_0x13ca3b0; 1 drivers +S_0x125a560 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x125a770 .param/l "i" 0 4 54, +C4<0110>; +L_0x13ca510/d .functor AND 1, L_0x13ca5d0, L_0x13ca730, C4<1>, C4<1>; +L_0x13ca510 .delay 1 (30000,30000,30000) L_0x13ca510/d; +v0x125a830_0 .net *"_s0", 0 0, L_0x13ca5d0; 1 drivers +v0x125a910_0 .net *"_s1", 0 0, L_0x13ca730; 1 drivers +S_0x125a9f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1258740; + .timescale -9 -12; +P_0x125ac00 .param/l "i" 0 4 54, +C4<0111>; +L_0x13ca4a0/d .functor AND 1, L_0x13cac60, L_0x13cae50, C4<1>, C4<1>; +L_0x13ca4a0 .delay 1 (30000,30000,30000) L_0x13ca4a0/d; +v0x125acc0_0 .net *"_s0", 0 0, L_0x13cac60; 1 drivers +v0x125ada0_0 .net *"_s1", 0 0, L_0x13cae50; 1 drivers +S_0x125b960 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x12584f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13cc8a0/d .functor OR 1, L_0x13cc960, L_0x13ccb10, C4<0>, C4<0>; +L_0x13cc8a0 .delay 1 (30000,30000,30000) L_0x13cc8a0/d; +v0x125d4b0_0 .net *"_s10", 0 0, L_0x13cc960; 1 drivers +v0x125d590_0 .net *"_s12", 0 0, L_0x13ccb10; 1 drivers +v0x125d670_0 .net "in", 7 0, L_0x13ca8a0; alias, 1 drivers +v0x125d740_0 .net "ors", 1 0, L_0x13cc6c0; 1 drivers +v0x125d800_0 .net "out", 0 0, L_0x13cc8a0; alias, 1 drivers +L_0x13cba90 .part L_0x13ca8a0, 0, 4; +L_0x13cc6c0 .concat8 [ 1 1 0 0], L_0x13cb780, L_0x13cc3b0; +L_0x13cc800 .part L_0x13ca8a0, 4, 4; +L_0x13cc960 .part L_0x13cc6c0, 0, 1; +L_0x13ccb10 .part L_0x13cc6c0, 1, 1; +S_0x125bb20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x125b960; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13caf40/d .functor OR 1, L_0x13cb000, L_0x13cb160, C4<0>, C4<0>; +L_0x13caf40 .delay 1 (30000,30000,30000) L_0x13caf40/d; +L_0x13cb390/d .functor OR 1, L_0x13cb4a0, L_0x13cb600, C4<0>, C4<0>; +L_0x13cb390 .delay 1 (30000,30000,30000) L_0x13cb390/d; +L_0x13cb780/d .functor OR 1, L_0x13cb7f0, L_0x13cb9a0, C4<0>, C4<0>; +L_0x13cb780 .delay 1 (30000,30000,30000) L_0x13cb780/d; +v0x125bd70_0 .net *"_s0", 0 0, L_0x13caf40; 1 drivers +v0x125be70_0 .net *"_s10", 0 0, L_0x13cb4a0; 1 drivers +v0x125bf50_0 .net *"_s12", 0 0, L_0x13cb600; 1 drivers +v0x125c010_0 .net *"_s14", 0 0, L_0x13cb7f0; 1 drivers +v0x125c0f0_0 .net *"_s16", 0 0, L_0x13cb9a0; 1 drivers +v0x125c220_0 .net *"_s3", 0 0, L_0x13cb000; 1 drivers +v0x125c300_0 .net *"_s5", 0 0, L_0x13cb160; 1 drivers +v0x125c3e0_0 .net *"_s6", 0 0, L_0x13cb390; 1 drivers +v0x125c4c0_0 .net "in", 3 0, L_0x13cba90; 1 drivers +v0x125c630_0 .net "ors", 1 0, L_0x13cb2a0; 1 drivers +v0x125c710_0 .net "out", 0 0, L_0x13cb780; 1 drivers +L_0x13cb000 .part L_0x13cba90, 0, 1; +L_0x13cb160 .part L_0x13cba90, 1, 1; +L_0x13cb2a0 .concat8 [ 1 1 0 0], L_0x13caf40, L_0x13cb390; +L_0x13cb4a0 .part L_0x13cba90, 2, 1; +L_0x13cb600 .part L_0x13cba90, 3, 1; +L_0x13cb7f0 .part L_0x13cb2a0, 0, 1; +L_0x13cb9a0 .part L_0x13cb2a0, 1, 1; +S_0x125c830 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x125b960; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13cbbc0/d .functor OR 1, L_0x13cbc30, L_0x13cbd90, C4<0>, C4<0>; +L_0x13cbbc0 .delay 1 (30000,30000,30000) L_0x13cbbc0/d; +L_0x13cbfc0/d .functor OR 1, L_0x13cc0d0, L_0x13cc230, C4<0>, C4<0>; +L_0x13cbfc0 .delay 1 (30000,30000,30000) L_0x13cbfc0/d; +L_0x13cc3b0/d .functor OR 1, L_0x13cc420, L_0x13cc5d0, C4<0>, C4<0>; +L_0x13cc3b0 .delay 1 (30000,30000,30000) L_0x13cc3b0/d; +v0x125c9f0_0 .net *"_s0", 0 0, L_0x13cbbc0; 1 drivers +v0x125caf0_0 .net *"_s10", 0 0, L_0x13cc0d0; 1 drivers +v0x125cbd0_0 .net *"_s12", 0 0, L_0x13cc230; 1 drivers +v0x125cc90_0 .net *"_s14", 0 0, L_0x13cc420; 1 drivers +v0x125cd70_0 .net *"_s16", 0 0, L_0x13cc5d0; 1 drivers +v0x125cea0_0 .net *"_s3", 0 0, L_0x13cbc30; 1 drivers +v0x125cf80_0 .net *"_s5", 0 0, L_0x13cbd90; 1 drivers +v0x125d060_0 .net *"_s6", 0 0, L_0x13cbfc0; 1 drivers +v0x125d140_0 .net "in", 3 0, L_0x13cc800; 1 drivers +v0x125d2b0_0 .net "ors", 1 0, L_0x13cbed0; 1 drivers +v0x125d390_0 .net "out", 0 0, L_0x13cc3b0; 1 drivers +L_0x13cbc30 .part L_0x13cc800, 0, 1; +L_0x13cbd90 .part L_0x13cc800, 1, 1; +L_0x13cbed0 .concat8 [ 1 1 0 0], L_0x13cbbc0, L_0x13cbfc0; +L_0x13cc0d0 .part L_0x13cc800, 2, 1; +L_0x13cc230 .part L_0x13cc800, 3, 1; +L_0x13cc420 .part L_0x13cbed0, 0, 1; +L_0x13cc5d0 .part L_0x13cbed0, 1, 1; +S_0x125dca0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x1251620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x13c7650/d .functor XNOR 1, L_0x13d15c0, L_0x13d09b0, C4<0>, C4<0>; +L_0x13c7650 .delay 1 (20000,20000,20000) L_0x13c7650/d; +L_0x13c77d0/d .functor AND 1, L_0x13d15c0, L_0x13bb520, C4<1>, C4<1>; +L_0x13c77d0 .delay 1 (30000,30000,30000) L_0x13c77d0/d; +L_0x13c7930/d .functor AND 1, L_0x13c7650, L_0x13d0a50, C4<1>, C4<1>; +L_0x13c7930 .delay 1 (30000,30000,30000) L_0x13c7930/d; +L_0x13c7a40/d .functor OR 1, L_0x13c7930, L_0x13c77d0, C4<0>, C4<0>; +L_0x13c7a40 .delay 1 (30000,30000,30000) L_0x13c7a40/d; +v0x125df50_0 .net "a", 0 0, L_0x13d15c0; alias, 1 drivers +v0x125e040_0 .net "a_", 0 0, L_0x131aec0; alias, 1 drivers +v0x125e100_0 .net "b", 0 0, L_0x13d09b0; alias, 1 drivers +v0x125e1f0_0 .net "b_", 0 0, L_0x13bb520; alias, 1 drivers +v0x125e290_0 .net "carryin", 0 0, L_0x13d0a50; alias, 1 drivers +v0x125e3d0_0 .net "eq", 0 0, L_0x13c7650; 1 drivers +v0x125e490_0 .net "lt", 0 0, L_0x13c77d0; 1 drivers +v0x125e550_0 .net "out", 0 0, L_0x13c7a40; 1 drivers +v0x125e610_0 .net "w0", 0 0, L_0x13c7930; 1 drivers +S_0x125e860 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1251620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x13c7230/d .functor OR 1, L_0x13c6d30, L_0x125fac0, C4<0>, C4<0>; +L_0x13c7230 .delay 1 (30000,30000,30000) L_0x13c7230/d; +v0x125f650_0 .net "a", 0 0, L_0x13d15c0; alias, 1 drivers +v0x125f7a0_0 .net "b", 0 0, L_0x13bb520; alias, 1 drivers +v0x125f860_0 .net "c1", 0 0, L_0x13c6d30; 1 drivers +v0x125f900_0 .net "c2", 0 0, L_0x125fac0; 1 drivers +v0x125f9d0_0 .net "carryin", 0 0, L_0x13d0a50; alias, 1 drivers +v0x125fb50_0 .net "carryout", 0 0, L_0x13c7230; 1 drivers +v0x125fbf0_0 .net "s1", 0 0, L_0x13c6c70; 1 drivers +v0x125fc90_0 .net "sum", 0 0, L_0x13c6e90; 1 drivers +S_0x125eab0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x125e860; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13c6c70/d .functor XOR 1, L_0x13d15c0, L_0x13bb520, C4<0>, C4<0>; +L_0x13c6c70 .delay 1 (30000,30000,30000) L_0x13c6c70/d; +L_0x13c6d30/d .functor AND 1, L_0x13d15c0, L_0x13bb520, C4<1>, C4<1>; +L_0x13c6d30 .delay 1 (30000,30000,30000) L_0x13c6d30/d; +v0x125ed10_0 .net "a", 0 0, L_0x13d15c0; alias, 1 drivers +v0x125edd0_0 .net "b", 0 0, L_0x13bb520; alias, 1 drivers +v0x125ee90_0 .net "carryout", 0 0, L_0x13c6d30; alias, 1 drivers +v0x125ef30_0 .net "sum", 0 0, L_0x13c6c70; alias, 1 drivers +S_0x125f060 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x125e860; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x13c6e90/d .functor XOR 1, L_0x13c6c70, L_0x13d0a50, C4<0>, C4<0>; +L_0x13c6e90 .delay 1 (30000,30000,30000) L_0x13c6e90/d; +L_0x125fac0/d .functor AND 1, L_0x13c6c70, L_0x13d0a50, C4<1>, C4<1>; +L_0x125fac0 .delay 1 (30000,30000,30000) L_0x125fac0/d; +v0x125f2c0_0 .net "a", 0 0, L_0x13c6c70; alias, 1 drivers +v0x125f390_0 .net "b", 0 0, L_0x13d0a50; alias, 1 drivers +v0x125f430_0 .net "carryout", 0 0, L_0x125fac0; alias, 1 drivers +v0x125f500_0 .net "sum", 0 0, L_0x13c6e90; alias, 1 drivers +S_0x1261d20 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x1251350; + .timescale -9 -12; +L_0x2ac43288acf8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac43288ad40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13c67f0/d .functor OR 1, L_0x2ac43288acf8, L_0x2ac43288ad40, C4<0>, C4<0>; +L_0x13c67f0 .delay 1 (30000,30000,30000) L_0x13c67f0/d; +v0x1261f10_0 .net/2u *"_s0", 0 0, L_0x2ac43288acf8; 1 drivers +v0x1261ff0_0 .net/2u *"_s2", 0 0, L_0x2ac43288ad40; 1 drivers +S_0x12620d0 .scope module, "overflowMux" "mux1" 3 67, 4 122 0, S_0xc4eec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "s" +L_0x13daf10/d .functor NOT 1, L_0x13db9a0, C4<0>, C4<0>, C4<0>; +L_0x13daf10 .delay 1 (10000,10000,10000) L_0x13daf10/d; +L_0x13dafd0/d .functor AND 1, L_0x13d30d0, L_0x13daf10, C4<1>, C4<1>; +L_0x13dafd0 .delay 1 (30000,30000,30000) L_0x13dafd0/d; +L_0x13db130/d .functor AND 1, L_0x13daca0, L_0x13db9a0, C4<1>, C4<1>; +L_0x13db130 .delay 1 (30000,30000,30000) L_0x13db130/d; +L_0x13db7a0/d .functor OR 1, L_0x13dafd0, L_0x13db130, C4<0>, C4<0>; +L_0x13db7a0 .delay 1 (30000,30000,30000) L_0x13db7a0/d; +v0x11342a0_0 .net "a", 0 0, L_0x13d30d0; alias, 1 drivers +v0x12624f0_0 .net "b", 0 0, L_0x13daca0; alias, 1 drivers +v0x12625b0_0 .net "out", 0 0, L_0x13db7a0; alias, 1 drivers +v0x1262650_0 .net "s", 0 0, L_0x13db9a0; 1 drivers +v0x1262710_0 .net "s_", 0 0, L_0x13daf10; 1 drivers +v0x1262820_0 .net "w0", 0 0, L_0x13dafd0; 1 drivers +v0x12628e0_0 .net "w1", 0 0, L_0x13db130; 1 drivers +S_0x1262a20 .scope module, "resultOr" "or32P" 3 76, 4 60 0, S_0xc4eec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 32 "out" + .port_info 1 /INPUT 32 "A" + .port_info 2 /INPUT 32 "B" +v0x126beb0_0 .net "A", 31 0, L_0x13d0740; alias, 1 drivers +v0x126bfb0_0 .net "B", 31 0, L_0x13dc340; alias, 1 drivers +v0x126c090_0 .net *"_s0", 0 0, L_0x13dbeb0; 1 drivers +v0x126c180_0 .net *"_s100", 0 0, L_0x13e2130; 1 drivers +v0x126c260_0 .net *"_s104", 0 0, L_0x13e2450; 1 drivers +v0x126c390_0 .net *"_s108", 0 0, L_0x13e2780; 1 drivers +v0x126c470_0 .net *"_s112", 0 0, L_0x13e2ac0; 1 drivers +v0x126c550_0 .net *"_s116", 0 0, L_0x13e2dc0; 1 drivers +v0x126c630_0 .net *"_s12", 0 0, L_0x13ddb10; 1 drivers +v0x126c7a0_0 .net *"_s120", 0 0, L_0x13e01d0; 1 drivers +v0x126c880_0 .net *"_s124", 0 0, L_0x13e46c0; 1 drivers +v0x126c960_0 .net *"_s16", 0 0, L_0x13dde70; 1 drivers +v0x126ca40_0 .net *"_s20", 0 0, L_0x13de1e0; 1 drivers +v0x126cb20_0 .net *"_s24", 0 0, L_0x13de670; 1 drivers +v0x126cc00_0 .net *"_s28", 0 0, L_0x13de980; 1 drivers +v0x126cce0_0 .net *"_s32", 0 0, L_0x13dec90; 1 drivers +v0x126cdc0_0 .net *"_s36", 0 0, L_0x13dd7c0; 1 drivers +v0x126cf70_0 .net *"_s4", 0 0, L_0x13dd470; 1 drivers +v0x126d010_0 .net *"_s40", 0 0, L_0x13defa0; 1 drivers +v0x126d0f0_0 .net *"_s44", 0 0, L_0x13df2e0; 1 drivers +v0x126d1d0_0 .net *"_s48", 0 0, L_0x13df630; 1 drivers +v0x126d2b0_0 .net *"_s52", 0 0, L_0x13df990; 1 drivers +v0x126d390_0 .net *"_s56", 0 0, L_0x13dfcb0; 1 drivers +v0x126d470_0 .net *"_s60", 0 0, L_0x13e0560; 1 drivers +v0x126d550_0 .net *"_s64", 0 0, L_0x13e0870; 1 drivers +v0x126d630_0 .net *"_s68", 0 0, L_0x13de560; 1 drivers +v0x126d710_0 .net *"_s72", 0 0, L_0x13e0b80; 1 drivers +v0x126d7f0_0 .net *"_s76", 0 0, L_0x13e0e80; 1 drivers +v0x126d8d0_0 .net *"_s8", 0 0, L_0x13dd850; 1 drivers +v0x126d9b0_0 .net *"_s80", 0 0, L_0x13e1190; 1 drivers +v0x126da90_0 .net *"_s84", 0 0, L_0x13e14b0; 1 drivers +v0x126db70_0 .net *"_s88", 0 0, L_0x13e17e0; 1 drivers +v0x126dc50_0 .net *"_s92", 0 0, L_0x13e1b20; 1 drivers +v0x126cea0_0 .net *"_s96", 0 0, L_0x13e1e20; 1 drivers +v0x126df20_0 .net "out", 31 0, L_0x13dffe0; alias, 1 drivers +L_0x13dd220 .part L_0x13d0740, 0, 1; +L_0x13dd380 .part L_0x13dc340, 0, 1; +L_0x13dd530 .part L_0x13d0740, 1, 1; +L_0x13dd720 .part L_0x13dc340, 1, 1; +L_0x13dd8c0 .part L_0x13d0740, 2, 1; +L_0x13dda20 .part L_0x13dc340, 2, 1; +L_0x13ddbd0 .part L_0x13d0740, 3, 1; +L_0x13ddd30 .part L_0x13dc340, 3, 1; +L_0x13ddf30 .part L_0x13d0740, 4, 1; +L_0x13de090 .part L_0x13dc340, 4, 1; +L_0x13de250 .part L_0x13d0740, 5, 1; +L_0x13de4c0 .part L_0x13dc340, 5, 1; +L_0x13de730 .part L_0x13d0740, 6, 1; +L_0x13de890 .part L_0x13dc340, 6, 1; +L_0x13dea40 .part L_0x13d0740, 7, 1; +L_0x13deba0 .part L_0x13dc340, 7, 1; +L_0x13ded50 .part L_0x13d0740, 8, 1; +L_0x13deeb0 .part L_0x13dc340, 8, 1; +L_0x13df090 .part L_0x13d0740, 9, 1; +L_0x13df1f0 .part L_0x13dc340, 9, 1; +L_0x13df3e0 .part L_0x13d0740, 10, 1; +L_0x13df540 .part L_0x13dc340, 10, 1; +L_0x13df740 .part L_0x13d0740, 11, 1; +L_0x13df8a0 .part L_0x13dc340, 11, 1; +L_0x13dfa60 .part L_0x13d0740, 12, 1; +L_0x13dfbc0 .part L_0x13dc340, 12, 1; +L_0x13dfd90 .part L_0x13d0740, 13, 1; +L_0x13de3b0 .part L_0x13dc340, 13, 1; +L_0x13e0310 .part L_0x13d0740, 14, 1; +L_0x13e0470 .part L_0x13dc340, 14, 1; +L_0x13e0620 .part L_0x13d0740, 15, 1; +L_0x13e0780 .part L_0x13dc340, 15, 1; +L_0x13e0930 .part L_0x13d0740, 16, 1; +L_0x13e0a90 .part L_0x13dc340, 16, 1; +L_0x13e0ca0 .part L_0x13d0740, 17, 1; +L_0x13e0d90 .part L_0x13dc340, 17, 1; +L_0x13e0fb0 .part L_0x13d0740, 18, 1; +L_0x13e10a0 .part L_0x13dc340, 18, 1; +L_0x13e12d0 .part L_0x13d0740, 19, 1; +L_0x13e13c0 .part L_0x13dc340, 19, 1; +L_0x13e1600 .part L_0x13d0740, 20, 1; +L_0x13e16f0 .part L_0x13dc340, 20, 1; +L_0x13e1940 .part L_0x13d0740, 21, 1; +L_0x13e1a30 .part L_0x13dc340, 21, 1; +L_0x13e1c90 .part L_0x13d0740, 22, 1; +L_0x13e1d30 .part L_0x13dc340, 22, 1; +L_0x13e1fa0 .part L_0x13d0740, 23, 1; +L_0x13e2040 .part L_0x13dc340, 23, 1; +L_0x13e22c0 .part L_0x13d0740, 24, 1; +L_0x13e2360 .part L_0x13dc340, 24, 1; +L_0x13e25f0 .part L_0x13d0740, 25, 1; +L_0x13e2690 .part L_0x13dc340, 25, 1; +L_0x13e2930 .part L_0x13d0740, 26, 1; +L_0x13e29d0 .part L_0x13dc340, 26, 1; +L_0x13e2890 .part L_0x13d0740, 27, 1; +L_0x13e2cd0 .part L_0x13dc340, 27, 1; +L_0x13e2bd0 .part L_0x13d0740, 28, 1; +L_0x13e2fe0 .part L_0x13dc340, 28, 1; +L_0x13e2e80 .part L_0x13d0740, 29, 1; +L_0x13dfef0 .part L_0x13dc340, 29, 1; +L_0x13e30d0 .part L_0x13d0740, 30, 1; +L_0x13e3b20 .part L_0x13dc340, 30, 1; +LS_0x13dffe0_0_0 .concat8 [ 1 1 1 1], L_0x13dbeb0, L_0x13dd470, L_0x13dd850, L_0x13ddb10; +LS_0x13dffe0_0_4 .concat8 [ 1 1 1 1], L_0x13dde70, L_0x13de1e0, L_0x13de670, L_0x13de980; +LS_0x13dffe0_0_8 .concat8 [ 1 1 1 1], L_0x13dec90, L_0x13dd7c0, L_0x13defa0, L_0x13df2e0; +LS_0x13dffe0_0_12 .concat8 [ 1 1 1 1], L_0x13df630, L_0x13df990, L_0x13dfcb0, L_0x13e0560; +LS_0x13dffe0_0_16 .concat8 [ 1 1 1 1], L_0x13e0870, L_0x13de560, L_0x13e0b80, L_0x13e0e80; +LS_0x13dffe0_0_20 .concat8 [ 1 1 1 1], L_0x13e1190, L_0x13e14b0, L_0x13e17e0, L_0x13e1b20; +LS_0x13dffe0_0_24 .concat8 [ 1 1 1 1], L_0x13e1e20, L_0x13e2130, L_0x13e2450, L_0x13e2780; +LS_0x13dffe0_0_28 .concat8 [ 1 1 1 1], L_0x13e2ac0, L_0x13e2dc0, L_0x13e01d0, L_0x13e46c0; +LS_0x13dffe0_1_0 .concat8 [ 4 4 4 4], LS_0x13dffe0_0_0, LS_0x13dffe0_0_4, LS_0x13dffe0_0_8, LS_0x13dffe0_0_12; +LS_0x13dffe0_1_4 .concat8 [ 4 4 4 4], LS_0x13dffe0_0_16, LS_0x13dffe0_0_20, LS_0x13dffe0_0_24, LS_0x13dffe0_0_28; +L_0x13dffe0 .concat8 [ 16 16 0 0], LS_0x13dffe0_1_0, LS_0x13dffe0_1_4; +L_0x13e47d0 .part L_0x13d0740, 31, 1; +L_0x13e3bc0 .part L_0x13dc340, 31, 1; +S_0x1262c60 .scope generate, "or_slces[0]" "or_slces[0]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1262e70 .param/l "i" 0 4 63, +C4<00>; +L_0x13dbeb0/d .functor OR 1, L_0x13dd220, L_0x13dd380, C4<0>, C4<0>; +L_0x13dbeb0 .delay 1 (30000,30000,30000) L_0x13dbeb0/d; +v0x1262f50_0 .net *"_s0", 0 0, L_0x13dd220; 1 drivers +v0x1263030_0 .net *"_s1", 0 0, L_0x13dd380; 1 drivers +S_0x1263110 .scope generate, "or_slces[1]" "or_slces[1]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1263320 .param/l "i" 0 4 63, +C4<01>; +L_0x13dd470/d .functor OR 1, L_0x13dd530, L_0x13dd720, C4<0>, C4<0>; +L_0x13dd470 .delay 1 (30000,30000,30000) L_0x13dd470/d; +v0x12633e0_0 .net *"_s0", 0 0, L_0x13dd530; 1 drivers +v0x12634c0_0 .net *"_s1", 0 0, L_0x13dd720; 1 drivers +S_0x12635a0 .scope generate, "or_slces[2]" "or_slces[2]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x12637b0 .param/l "i" 0 4 63, +C4<010>; +L_0x13dd850/d .functor OR 1, L_0x13dd8c0, L_0x13dda20, C4<0>, C4<0>; +L_0x13dd850 .delay 1 (30000,30000,30000) L_0x13dd850/d; +v0x1263850_0 .net *"_s0", 0 0, L_0x13dd8c0; 1 drivers +v0x1263930_0 .net *"_s1", 0 0, L_0x13dda20; 1 drivers +S_0x1263a10 .scope generate, "or_slces[3]" "or_slces[3]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1263c20 .param/l "i" 0 4 63, +C4<011>; +L_0x13ddb10/d .functor OR 1, L_0x13ddbd0, L_0x13ddd30, C4<0>, C4<0>; +L_0x13ddb10 .delay 1 (30000,30000,30000) L_0x13ddb10/d; +v0x1263ce0_0 .net *"_s0", 0 0, L_0x13ddbd0; 1 drivers +v0x1263dc0_0 .net *"_s1", 0 0, L_0x13ddd30; 1 drivers +S_0x1263ea0 .scope generate, "or_slces[4]" "or_slces[4]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1264100 .param/l "i" 0 4 63, +C4<0100>; +L_0x13dde70/d .functor OR 1, L_0x13ddf30, L_0x13de090, C4<0>, C4<0>; +L_0x13dde70 .delay 1 (30000,30000,30000) L_0x13dde70/d; +v0x12641c0_0 .net *"_s0", 0 0, L_0x13ddf30; 1 drivers +v0x12642a0_0 .net *"_s1", 0 0, L_0x13de090; 1 drivers +S_0x1264380 .scope generate, "or_slces[5]" "or_slces[5]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1264590 .param/l "i" 0 4 63, +C4<0101>; +L_0x13de1e0/d .functor OR 1, L_0x13de250, L_0x13de4c0, C4<0>, C4<0>; +L_0x13de1e0 .delay 1 (30000,30000,30000) L_0x13de1e0/d; +v0x1264650_0 .net *"_s0", 0 0, L_0x13de250; 1 drivers +v0x1264730_0 .net *"_s1", 0 0, L_0x13de4c0; 1 drivers +S_0x1264810 .scope generate, "or_slces[6]" "or_slces[6]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1264a20 .param/l "i" 0 4 63, +C4<0110>; +L_0x13de670/d .functor OR 1, L_0x13de730, L_0x13de890, C4<0>, C4<0>; +L_0x13de670 .delay 1 (30000,30000,30000) L_0x13de670/d; +v0x1264ae0_0 .net *"_s0", 0 0, L_0x13de730; 1 drivers +v0x1264bc0_0 .net *"_s1", 0 0, L_0x13de890; 1 drivers +S_0x1264ca0 .scope generate, "or_slces[7]" "or_slces[7]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1264eb0 .param/l "i" 0 4 63, +C4<0111>; +L_0x13de980/d .functor OR 1, L_0x13dea40, L_0x13deba0, C4<0>, C4<0>; +L_0x13de980 .delay 1 (30000,30000,30000) L_0x13de980/d; +v0x1264f70_0 .net *"_s0", 0 0, L_0x13dea40; 1 drivers +v0x1265010_0 .net *"_s1", 0 0, L_0x13deba0; 1 drivers +S_0x12650b0 .scope generate, "or_slces[8]" "or_slces[8]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x12640b0 .param/l "i" 0 4 63, +C4<01000>; +L_0x13dec90/d .functor OR 1, L_0x13ded50, L_0x13deeb0, C4<0>, C4<0>; +L_0x13dec90 .delay 1 (30000,30000,30000) L_0x13dec90/d; +v0x1265380_0 .net *"_s0", 0 0, L_0x13ded50; 1 drivers +v0x1265460_0 .net *"_s1", 0 0, L_0x13deeb0; 1 drivers +S_0x1265540 .scope generate, "or_slces[9]" "or_slces[9]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1265750 .param/l "i" 0 4 63, +C4<01001>; +L_0x13dd7c0/d .functor OR 1, L_0x13df090, L_0x13df1f0, C4<0>, C4<0>; +L_0x13dd7c0 .delay 1 (30000,30000,30000) L_0x13dd7c0/d; +v0x1265810_0 .net *"_s0", 0 0, L_0x13df090; 1 drivers +v0x12658f0_0 .net *"_s1", 0 0, L_0x13df1f0; 1 drivers +S_0x12659d0 .scope generate, "or_slces[10]" "or_slces[10]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1265be0 .param/l "i" 0 4 63, +C4<01010>; +L_0x13defa0/d .functor OR 1, L_0x13df3e0, L_0x13df540, C4<0>, C4<0>; +L_0x13defa0 .delay 1 (30000,30000,30000) L_0x13defa0/d; +v0x1265ca0_0 .net *"_s0", 0 0, L_0x13df3e0; 1 drivers +v0x1265d80_0 .net *"_s1", 0 0, L_0x13df540; 1 drivers +S_0x1265e60 .scope generate, "or_slces[11]" "or_slces[11]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1266070 .param/l "i" 0 4 63, +C4<01011>; +L_0x13df2e0/d .functor OR 1, L_0x13df740, L_0x13df8a0, C4<0>, C4<0>; +L_0x13df2e0 .delay 1 (30000,30000,30000) L_0x13df2e0/d; +v0x1266130_0 .net *"_s0", 0 0, L_0x13df740; 1 drivers +v0x1266210_0 .net *"_s1", 0 0, L_0x13df8a0; 1 drivers +S_0x12662f0 .scope generate, "or_slces[12]" "or_slces[12]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1266500 .param/l "i" 0 4 63, +C4<01100>; +L_0x13df630/d .functor OR 1, L_0x13dfa60, L_0x13dfbc0, C4<0>, C4<0>; +L_0x13df630 .delay 1 (30000,30000,30000) L_0x13df630/d; +v0x12665c0_0 .net *"_s0", 0 0, L_0x13dfa60; 1 drivers +v0x12666a0_0 .net *"_s1", 0 0, L_0x13dfbc0; 1 drivers +S_0x1266780 .scope generate, "or_slces[13]" "or_slces[13]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1266990 .param/l "i" 0 4 63, +C4<01101>; +L_0x13df990/d .functor OR 1, L_0x13dfd90, L_0x13de3b0, C4<0>, C4<0>; +L_0x13df990 .delay 1 (30000,30000,30000) L_0x13df990/d; +v0x1266a50_0 .net *"_s0", 0 0, L_0x13dfd90; 1 drivers +v0x1266b30_0 .net *"_s1", 0 0, L_0x13de3b0; 1 drivers +S_0x1266c10 .scope generate, "or_slces[14]" "or_slces[14]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1266e20 .param/l "i" 0 4 63, +C4<01110>; +L_0x13dfcb0/d .functor OR 1, L_0x13e0310, L_0x13e0470, C4<0>, C4<0>; +L_0x13dfcb0 .delay 1 (30000,30000,30000) L_0x13dfcb0/d; +v0x1266ee0_0 .net *"_s0", 0 0, L_0x13e0310; 1 drivers +v0x1266fc0_0 .net *"_s1", 0 0, L_0x13e0470; 1 drivers +S_0x12670a0 .scope generate, "or_slces[15]" "or_slces[15]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x12672b0 .param/l "i" 0 4 63, +C4<01111>; +L_0x13e0560/d .functor OR 1, L_0x13e0620, L_0x13e0780, C4<0>, C4<0>; +L_0x13e0560 .delay 1 (30000,30000,30000) L_0x13e0560/d; +v0x1267370_0 .net *"_s0", 0 0, L_0x13e0620; 1 drivers +v0x1267450_0 .net *"_s1", 0 0, L_0x13e0780; 1 drivers +S_0x1267530 .scope generate, "or_slces[16]" "or_slces[16]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1265280 .param/l "i" 0 4 63, +C4<010000>; +L_0x13e0870/d .functor OR 1, L_0x13e0930, L_0x13e0a90, C4<0>, C4<0>; +L_0x13e0870 .delay 1 (30000,30000,30000) L_0x13e0870/d; +v0x12678a0_0 .net *"_s0", 0 0, L_0x13e0930; 1 drivers +v0x1267960_0 .net *"_s1", 0 0, L_0x13e0a90; 1 drivers +S_0x1267a40 .scope generate, "or_slces[17]" "or_slces[17]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1267c50 .param/l "i" 0 4 63, +C4<010001>; +L_0x13de560/d .functor OR 1, L_0x13e0ca0, L_0x13e0d90, C4<0>, C4<0>; +L_0x13de560 .delay 1 (30000,30000,30000) L_0x13de560/d; +v0x1267d10_0 .net *"_s0", 0 0, L_0x13e0ca0; 1 drivers +v0x1267df0_0 .net *"_s1", 0 0, L_0x13e0d90; 1 drivers +S_0x1267ed0 .scope generate, "or_slces[18]" "or_slces[18]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x12680e0 .param/l "i" 0 4 63, +C4<010010>; +L_0x13e0b80/d .functor OR 1, L_0x13e0fb0, L_0x13e10a0, C4<0>, C4<0>; +L_0x13e0b80 .delay 1 (30000,30000,30000) L_0x13e0b80/d; +v0x12681a0_0 .net *"_s0", 0 0, L_0x13e0fb0; 1 drivers +v0x1268280_0 .net *"_s1", 0 0, L_0x13e10a0; 1 drivers +S_0x1268360 .scope generate, "or_slces[19]" "or_slces[19]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1268570 .param/l "i" 0 4 63, +C4<010011>; +L_0x13e0e80/d .functor OR 1, L_0x13e12d0, L_0x13e13c0, C4<0>, C4<0>; +L_0x13e0e80 .delay 1 (30000,30000,30000) L_0x13e0e80/d; +v0x1268630_0 .net *"_s0", 0 0, L_0x13e12d0; 1 drivers +v0x1268710_0 .net *"_s1", 0 0, L_0x13e13c0; 1 drivers +S_0x12687f0 .scope generate, "or_slces[20]" "or_slces[20]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1268a00 .param/l "i" 0 4 63, +C4<010100>; +L_0x13e1190/d .functor OR 1, L_0x13e1600, L_0x13e16f0, C4<0>, C4<0>; +L_0x13e1190 .delay 1 (30000,30000,30000) L_0x13e1190/d; +v0x1268ac0_0 .net *"_s0", 0 0, L_0x13e1600; 1 drivers +v0x1268ba0_0 .net *"_s1", 0 0, L_0x13e16f0; 1 drivers +S_0x1268c80 .scope generate, "or_slces[21]" "or_slces[21]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1268e90 .param/l "i" 0 4 63, +C4<010101>; +L_0x13e14b0/d .functor OR 1, L_0x13e1940, L_0x13e1a30, C4<0>, C4<0>; +L_0x13e14b0 .delay 1 (30000,30000,30000) L_0x13e14b0/d; +v0x1268f50_0 .net *"_s0", 0 0, L_0x13e1940; 1 drivers +v0x1269030_0 .net *"_s1", 0 0, L_0x13e1a30; 1 drivers +S_0x1269110 .scope generate, "or_slces[22]" "or_slces[22]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1269320 .param/l "i" 0 4 63, +C4<010110>; +L_0x13e17e0/d .functor OR 1, L_0x13e1c90, L_0x13e1d30, C4<0>, C4<0>; +L_0x13e17e0 .delay 1 (30000,30000,30000) L_0x13e17e0/d; +v0x12693e0_0 .net *"_s0", 0 0, L_0x13e1c90; 1 drivers +v0x12694c0_0 .net *"_s1", 0 0, L_0x13e1d30; 1 drivers +S_0x12695a0 .scope generate, "or_slces[23]" "or_slces[23]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x12697b0 .param/l "i" 0 4 63, +C4<010111>; +L_0x13e1b20/d .functor OR 1, L_0x13e1fa0, L_0x13e2040, C4<0>, C4<0>; +L_0x13e1b20 .delay 1 (30000,30000,30000) L_0x13e1b20/d; +v0x1269870_0 .net *"_s0", 0 0, L_0x13e1fa0; 1 drivers +v0x1269950_0 .net *"_s1", 0 0, L_0x13e2040; 1 drivers +S_0x1269a30 .scope generate, "or_slces[24]" "or_slces[24]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x1269c40 .param/l "i" 0 4 63, +C4<011000>; +L_0x13e1e20/d .functor OR 1, L_0x13e22c0, L_0x13e2360, C4<0>, C4<0>; +L_0x13e1e20 .delay 1 (30000,30000,30000) L_0x13e1e20/d; +v0x1269d00_0 .net *"_s0", 0 0, L_0x13e22c0; 1 drivers +v0x1269de0_0 .net *"_s1", 0 0, L_0x13e2360; 1 drivers +S_0x1269ec0 .scope generate, "or_slces[25]" "or_slces[25]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126a0d0 .param/l "i" 0 4 63, +C4<011001>; +L_0x13e2130/d .functor OR 1, L_0x13e25f0, L_0x13e2690, C4<0>, C4<0>; +L_0x13e2130 .delay 1 (30000,30000,30000) L_0x13e2130/d; +v0x126a190_0 .net *"_s0", 0 0, L_0x13e25f0; 1 drivers +v0x126a270_0 .net *"_s1", 0 0, L_0x13e2690; 1 drivers +S_0x126a350 .scope generate, "or_slces[26]" "or_slces[26]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126a560 .param/l "i" 0 4 63, +C4<011010>; +L_0x13e2450/d .functor OR 1, L_0x13e2930, L_0x13e29d0, C4<0>, C4<0>; +L_0x13e2450 .delay 1 (30000,30000,30000) L_0x13e2450/d; +v0x126a620_0 .net *"_s0", 0 0, L_0x13e2930; 1 drivers +v0x126a700_0 .net *"_s1", 0 0, L_0x13e29d0; 1 drivers +S_0x126a7e0 .scope generate, "or_slces[27]" "or_slces[27]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126a9f0 .param/l "i" 0 4 63, +C4<011011>; +L_0x13e2780/d .functor OR 1, L_0x13e2890, L_0x13e2cd0, C4<0>, C4<0>; +L_0x13e2780 .delay 1 (30000,30000,30000) L_0x13e2780/d; +v0x126aab0_0 .net *"_s0", 0 0, L_0x13e2890; 1 drivers +v0x126ab90_0 .net *"_s1", 0 0, L_0x13e2cd0; 1 drivers +S_0x126ac70 .scope generate, "or_slces[28]" "or_slces[28]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126ae80 .param/l "i" 0 4 63, +C4<011100>; +L_0x13e2ac0/d .functor OR 1, L_0x13e2bd0, L_0x13e2fe0, C4<0>, C4<0>; +L_0x13e2ac0 .delay 1 (30000,30000,30000) L_0x13e2ac0/d; +v0x126af40_0 .net *"_s0", 0 0, L_0x13e2bd0; 1 drivers +v0x126b020_0 .net *"_s1", 0 0, L_0x13e2fe0; 1 drivers +S_0x126b100 .scope generate, "or_slces[29]" "or_slces[29]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126b310 .param/l "i" 0 4 63, +C4<011101>; +L_0x13e2dc0/d .functor OR 1, L_0x13e2e80, L_0x13dfef0, C4<0>, C4<0>; +L_0x13e2dc0 .delay 1 (30000,30000,30000) L_0x13e2dc0/d; +v0x126b3d0_0 .net *"_s0", 0 0, L_0x13e2e80; 1 drivers +v0x126b4b0_0 .net *"_s1", 0 0, L_0x13dfef0; 1 drivers +S_0x126b590 .scope generate, "or_slces[30]" "or_slces[30]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126b7a0 .param/l "i" 0 4 63, +C4<011110>; +L_0x13e01d0/d .functor OR 1, L_0x13e30d0, L_0x13e3b20, C4<0>, C4<0>; +L_0x13e01d0 .delay 1 (30000,30000,30000) L_0x13e01d0/d; +v0x126b860_0 .net *"_s0", 0 0, L_0x13e30d0; 1 drivers +v0x126b940_0 .net *"_s1", 0 0, L_0x13e3b20; 1 drivers +S_0x126ba20 .scope generate, "or_slces[31]" "or_slces[31]" 4 63, 4 63 0, S_0x1262a20; + .timescale -9 -12; +P_0x126bc30 .param/l "i" 0 4 63, +C4<011111>; +L_0x13e46c0/d .functor OR 1, L_0x13e47d0, L_0x13e3bc0, C4<0>, C4<0>; +L_0x13e46c0 .delay 1 (30000,30000,30000) L_0x13e46c0/d; +v0x126bcf0_0 .net *"_s0", 0 0, L_0x13e47d0; 1 drivers +v0x126bdd0_0 .net *"_s1", 0 0, L_0x13e3bc0; 1 drivers +S_0x126e080 .scope module, "zeroout" "and32" 3 61, 4 44 0, S_0xc4eec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 32 "in" +L_0x13da990/d .functor AND 1, L_0x13daa00, L_0x13dabb0, C4<1>, C4<1>; +L_0x13da990 .delay 1 (30000,30000,30000) L_0x13da990/d; +v0x1277140_0 .net *"_s10", 0 0, L_0x13daa00; 1 drivers +v0x1277220_0 .net *"_s12", 0 0, L_0x13dabb0; 1 drivers +v0x1277300_0 .net "ands", 1 0, L_0x13da720; 1 drivers +v0x12773c0_0 .net "in", 31 0, L_0x131abd0; alias, 1 drivers +v0x12774a0_0 .net "out", 0 0, L_0x13da990; alias, 1 drivers +L_0x13d66b0 .part L_0x131abd0, 0, 16; +L_0x13da720 .concat8 [ 1 1 0 0], L_0x13d6350, L_0x13da3c0; +L_0x13da860 .part L_0x131abd0, 16, 16; +L_0x13daa00 .part L_0x13da720, 0, 1; +L_0x13dabb0 .part L_0x13da720, 1, 1; +S_0x126e240 .scope module, "and_1" "and16" 4 46, 4 37 0, S_0x126e080; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 16 "in" +L_0x13d6350/d .functor AND 1, L_0x13d6410, L_0x13d65c0, C4<1>, C4<1>; +L_0x13d6350 .delay 1 (30000,30000,30000) L_0x13d6350/d; +v0x1272510_0 .net *"_s10", 0 0, L_0x13d6410; 1 drivers +v0x12725f0_0 .net *"_s12", 0 0, L_0x13d65c0; 1 drivers +v0x12726d0_0 .net "ands", 1 0, L_0x13d6120; 1 drivers +v0x1272790_0 .net "in", 15 0, L_0x13d66b0; 1 drivers +v0x1272870_0 .net "out", 0 0, L_0x13d6350; 1 drivers +L_0x13d43b0 .part L_0x13d66b0, 0, 8; +L_0x13d6120 .concat8 [ 1 1 0 0], L_0x13d4110, L_0x13d5dc0; +L_0x13d6260 .part L_0x13d66b0, 8, 8; +L_0x13d6410 .part L_0x13d6120, 0, 1; +L_0x13d65c0 .part L_0x13d6120, 1, 1; +S_0x126e490 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x126e240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13d4110/d .functor AND 1, L_0x13d4180, L_0x13d42c0, C4<1>, C4<1>; +L_0x13d4110 .delay 1 (30000,30000,30000) L_0x13d4110/d; +v0x1270070_0 .net *"_s10", 0 0, L_0x13d4180; 1 drivers +v0x1270150_0 .net *"_s12", 0 0, L_0x13d42c0; 1 drivers +v0x1270230_0 .net "ands", 1 0, L_0x13d3fd0; 1 drivers +v0x12702f0_0 .net "in", 7 0, L_0x13d43b0; 1 drivers +v0x12703d0_0 .net "out", 0 0, L_0x13d4110; 1 drivers +L_0x13d38f0 .part L_0x13d43b0, 0, 4; +L_0x13d3fd0 .concat8 [ 1 1 0 0], L_0x13d3740, L_0x13d3e20; +L_0x13d4070 .part L_0x13d43b0, 4, 4; +L_0x13d4180 .part L_0x13d3fd0, 0, 1; +L_0x13d42c0 .part L_0x13d3fd0, 1, 1; +S_0x126e6e0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x126e490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d1fd0/d .functor AND 1, L_0x13d3320, L_0x13d33c0, C4<1>, C4<1>; +L_0x13d1fd0 .delay 1 (30000,30000,30000) L_0x13d1fd0/d; +L_0x13d3500/d .functor AND 1, L_0x13d3570, L_0x13d3610, C4<1>, C4<1>; +L_0x13d3500 .delay 1 (30000,30000,30000) L_0x13d3500/d; +L_0x13d3740/d .functor AND 1, L_0x13d37b0, L_0x13d3850, C4<1>, C4<1>; +L_0x13d3740 .delay 1 (30000,30000,30000) L_0x13d3740/d; +v0x126e930_0 .net *"_s0", 0 0, L_0x13d1fd0; 1 drivers +v0x126ea30_0 .net *"_s10", 0 0, L_0x13d3570; 1 drivers +v0x126eb10_0 .net *"_s12", 0 0, L_0x13d3610; 1 drivers +v0x126ebd0_0 .net *"_s14", 0 0, L_0x13d37b0; 1 drivers +v0x126ecb0_0 .net *"_s16", 0 0, L_0x13d3850; 1 drivers +v0x126ede0_0 .net *"_s3", 0 0, L_0x13d3320; 1 drivers +v0x126eec0_0 .net *"_s5", 0 0, L_0x13d33c0; 1 drivers +v0x126efa0_0 .net *"_s6", 0 0, L_0x13d3500; 1 drivers +v0x126f080_0 .net "ands", 1 0, L_0x13d3460; 1 drivers +v0x126f1f0_0 .net "in", 3 0, L_0x13d38f0; 1 drivers +v0x126f2d0_0 .net "out", 0 0, L_0x13d3740; 1 drivers +L_0x13d3320 .part L_0x13d38f0, 0, 1; +L_0x13d33c0 .part L_0x13d38f0, 1, 1; +L_0x13d3460 .concat8 [ 1 1 0 0], L_0x13d1fd0, L_0x13d3500; +L_0x13d3570 .part L_0x13d38f0, 2, 1; +L_0x13d3610 .part L_0x13d38f0, 3, 1; +L_0x13d37b0 .part L_0x13d3460, 0, 1; +L_0x13d3850 .part L_0x13d3460, 1, 1; +S_0x126f3f0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x126e490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d3990/d .functor AND 1, L_0x13d3a00, L_0x13d3aa0, C4<1>, C4<1>; +L_0x13d3990 .delay 1 (30000,30000,30000) L_0x13d3990/d; +L_0x13d3be0/d .functor AND 1, L_0x13d3c50, L_0x13d3cf0, C4<1>, C4<1>; +L_0x13d3be0 .delay 1 (30000,30000,30000) L_0x13d3be0/d; +L_0x13d3e20/d .functor AND 1, L_0x13d3e90, L_0x13d3f30, C4<1>, C4<1>; +L_0x13d3e20 .delay 1 (30000,30000,30000) L_0x13d3e20/d; +v0x126f5b0_0 .net *"_s0", 0 0, L_0x13d3990; 1 drivers +v0x126f6b0_0 .net *"_s10", 0 0, L_0x13d3c50; 1 drivers +v0x126f790_0 .net *"_s12", 0 0, L_0x13d3cf0; 1 drivers +v0x126f850_0 .net *"_s14", 0 0, L_0x13d3e90; 1 drivers +v0x126f930_0 .net *"_s16", 0 0, L_0x13d3f30; 1 drivers +v0x126fa60_0 .net *"_s3", 0 0, L_0x13d3a00; 1 drivers +v0x126fb40_0 .net *"_s5", 0 0, L_0x13d3aa0; 1 drivers +v0x126fc20_0 .net *"_s6", 0 0, L_0x13d3be0; 1 drivers +v0x126fd00_0 .net "ands", 1 0, L_0x13d3b40; 1 drivers +v0x126fe70_0 .net "in", 3 0, L_0x13d4070; 1 drivers +v0x126ff50_0 .net "out", 0 0, L_0x13d3e20; 1 drivers +L_0x13d3a00 .part L_0x13d4070, 0, 1; +L_0x13d3aa0 .part L_0x13d4070, 1, 1; +L_0x13d3b40 .concat8 [ 1 1 0 0], L_0x13d3990, L_0x13d3be0; +L_0x13d3c50 .part L_0x13d4070, 2, 1; +L_0x13d3cf0 .part L_0x13d4070, 3, 1; +L_0x13d3e90 .part L_0x13d3b40, 0, 1; +L_0x13d3f30 .part L_0x13d3b40, 1, 1; +S_0x12704f0 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x126e240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13d5dc0/d .functor AND 1, L_0x13d5e80, L_0x13d6030, C4<1>, C4<1>; +L_0x13d5dc0 .delay 1 (30000,30000,30000) L_0x13d5dc0/d; +v0x1272090_0 .net *"_s10", 0 0, L_0x13d5e80; 1 drivers +v0x1272170_0 .net *"_s12", 0 0, L_0x13d6030; 1 drivers +v0x1272250_0 .net "ands", 1 0, L_0x13d5b90; 1 drivers +v0x1272310_0 .net "in", 7 0, L_0x13d6260; 1 drivers +v0x12723f0_0 .net "out", 0 0, L_0x13d5dc0; 1 drivers +L_0x13d4fa0 .part L_0x13d6260, 0, 4; +L_0x13d5b90 .concat8 [ 1 1 0 0], L_0x13d4c90, L_0x13d5880; +L_0x13d5cd0 .part L_0x13d6260, 4, 4; +L_0x13d5e80 .part L_0x13d5b90, 0, 1; +L_0x13d6030 .part L_0x13d5b90, 1, 1; +S_0x1270700 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x12704f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d4450/d .functor AND 1, L_0x13d4510, L_0x13d4670, C4<1>, C4<1>; +L_0x13d4450 .delay 1 (30000,30000,30000) L_0x13d4450/d; +L_0x13d48a0/d .functor AND 1, L_0x13d49b0, L_0x13d4b10, C4<1>, C4<1>; +L_0x13d48a0 .delay 1 (30000,30000,30000) L_0x13d48a0/d; +L_0x13d4c90/d .functor AND 1, L_0x13d4d00, L_0x13d4eb0, C4<1>, C4<1>; +L_0x13d4c90 .delay 1 (30000,30000,30000) L_0x13d4c90/d; +v0x1270950_0 .net *"_s0", 0 0, L_0x13d4450; 1 drivers +v0x1270a50_0 .net *"_s10", 0 0, L_0x13d49b0; 1 drivers +v0x1270b30_0 .net *"_s12", 0 0, L_0x13d4b10; 1 drivers +v0x1270bf0_0 .net *"_s14", 0 0, L_0x13d4d00; 1 drivers +v0x1270cd0_0 .net *"_s16", 0 0, L_0x13d4eb0; 1 drivers +v0x1270e00_0 .net *"_s3", 0 0, L_0x13d4510; 1 drivers +v0x1270ee0_0 .net *"_s5", 0 0, L_0x13d4670; 1 drivers +v0x1270fc0_0 .net *"_s6", 0 0, L_0x13d48a0; 1 drivers +v0x12710a0_0 .net "ands", 1 0, L_0x13d47b0; 1 drivers +v0x1271210_0 .net "in", 3 0, L_0x13d4fa0; 1 drivers +v0x12712f0_0 .net "out", 0 0, L_0x13d4c90; 1 drivers +L_0x13d4510 .part L_0x13d4fa0, 0, 1; +L_0x13d4670 .part L_0x13d4fa0, 1, 1; +L_0x13d47b0 .concat8 [ 1 1 0 0], L_0x13d4450, L_0x13d48a0; +L_0x13d49b0 .part L_0x13d4fa0, 2, 1; +L_0x13d4b10 .part L_0x13d4fa0, 3, 1; +L_0x13d4d00 .part L_0x13d47b0, 0, 1; +L_0x13d4eb0 .part L_0x13d47b0, 1, 1; +S_0x1271410 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x12704f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d5040/d .functor AND 1, L_0x13d5100, L_0x13d5260, C4<1>, C4<1>; +L_0x13d5040 .delay 1 (30000,30000,30000) L_0x13d5040/d; +L_0x13d5490/d .functor AND 1, L_0x13d55a0, L_0x13d5700, C4<1>, C4<1>; +L_0x13d5490 .delay 1 (30000,30000,30000) L_0x13d5490/d; +L_0x13d5880/d .functor AND 1, L_0x13d58f0, L_0x13d5aa0, C4<1>, C4<1>; +L_0x13d5880 .delay 1 (30000,30000,30000) L_0x13d5880/d; +v0x12715d0_0 .net *"_s0", 0 0, L_0x13d5040; 1 drivers +v0x12716d0_0 .net *"_s10", 0 0, L_0x13d55a0; 1 drivers +v0x12717b0_0 .net *"_s12", 0 0, L_0x13d5700; 1 drivers +v0x1271870_0 .net *"_s14", 0 0, L_0x13d58f0; 1 drivers +v0x1271950_0 .net *"_s16", 0 0, L_0x13d5aa0; 1 drivers +v0x1271a80_0 .net *"_s3", 0 0, L_0x13d5100; 1 drivers +v0x1271b60_0 .net *"_s5", 0 0, L_0x13d5260; 1 drivers +v0x1271c40_0 .net *"_s6", 0 0, L_0x13d5490; 1 drivers +v0x1271d20_0 .net "ands", 1 0, L_0x13d53a0; 1 drivers +v0x1271e90_0 .net "in", 3 0, L_0x13d5cd0; 1 drivers +v0x1271f70_0 .net "out", 0 0, L_0x13d5880; 1 drivers +L_0x13d5100 .part L_0x13d5cd0, 0, 1; +L_0x13d5260 .part L_0x13d5cd0, 1, 1; +L_0x13d53a0 .concat8 [ 1 1 0 0], L_0x13d5040, L_0x13d5490; +L_0x13d55a0 .part L_0x13d5cd0, 2, 1; +L_0x13d5700 .part L_0x13d5cd0, 3, 1; +L_0x13d58f0 .part L_0x13d53a0, 0, 1; +L_0x13d5aa0 .part L_0x13d53a0, 1, 1; +S_0x12729e0 .scope module, "and_2" "and16" 4 47, 4 37 0, S_0x126e080; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 16 "in" +L_0x13da3c0/d .functor AND 1, L_0x13da480, L_0x13da630, C4<1>, C4<1>; +L_0x13da3c0 .delay 1 (30000,30000,30000) L_0x13da3c0/d; +v0x1276c70_0 .net *"_s10", 0 0, L_0x13da480; 1 drivers +v0x1276d50_0 .net *"_s12", 0 0, L_0x13da630; 1 drivers +v0x1276e30_0 .net "ands", 1 0, L_0x13da190; 1 drivers +v0x1276ef0_0 .net "in", 15 0, L_0x13da860; 1 drivers +v0x1276fd0_0 .net "out", 0 0, L_0x13da3c0; 1 drivers +L_0x13d8420 .part L_0x13da860, 0, 8; +L_0x13da190 .concat8 [ 1 1 0 0], L_0x13d80c0, L_0x13d9e30; +L_0x13da2d0 .part L_0x13da860, 8, 8; +L_0x13da480 .part L_0x13da190, 0, 1; +L_0x13da630 .part L_0x13da190, 1, 1; +S_0x1272bf0 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x12729e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13d80c0/d .functor AND 1, L_0x13d8180, L_0x13d8330, C4<1>, C4<1>; +L_0x13d80c0 .delay 1 (30000,30000,30000) L_0x13d80c0/d; +v0x12747d0_0 .net *"_s10", 0 0, L_0x13d8180; 1 drivers +v0x12748b0_0 .net *"_s12", 0 0, L_0x13d8330; 1 drivers +v0x1274990_0 .net "ands", 1 0, L_0x13d7e90; 1 drivers +v0x1274a50_0 .net "in", 7 0, L_0x13d8420; 1 drivers +v0x1274b30_0 .net "out", 0 0, L_0x13d80c0; 1 drivers +L_0x13d72a0 .part L_0x13d8420, 0, 4; +L_0x13d7e90 .concat8 [ 1 1 0 0], L_0x13d6f90, L_0x13d7b80; +L_0x13d7fd0 .part L_0x13d8420, 4, 4; +L_0x13d8180 .part L_0x13d7e90, 0, 1; +L_0x13d8330 .part L_0x13d7e90, 1, 1; +S_0x1272e40 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1272bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d6750/d .functor AND 1, L_0x13d6810, L_0x13d6970, C4<1>, C4<1>; +L_0x13d6750 .delay 1 (30000,30000,30000) L_0x13d6750/d; +L_0x13d6ba0/d .functor AND 1, L_0x13d6cb0, L_0x13d6e10, C4<1>, C4<1>; +L_0x13d6ba0 .delay 1 (30000,30000,30000) L_0x13d6ba0/d; +L_0x13d6f90/d .functor AND 1, L_0x13d7000, L_0x13d71b0, C4<1>, C4<1>; +L_0x13d6f90 .delay 1 (30000,30000,30000) L_0x13d6f90/d; +v0x1273090_0 .net *"_s0", 0 0, L_0x13d6750; 1 drivers +v0x1273190_0 .net *"_s10", 0 0, L_0x13d6cb0; 1 drivers +v0x1273270_0 .net *"_s12", 0 0, L_0x13d6e10; 1 drivers +v0x1273330_0 .net *"_s14", 0 0, L_0x13d7000; 1 drivers +v0x1273410_0 .net *"_s16", 0 0, L_0x13d71b0; 1 drivers +v0x1273540_0 .net *"_s3", 0 0, L_0x13d6810; 1 drivers +v0x1273620_0 .net *"_s5", 0 0, L_0x13d6970; 1 drivers +v0x1273700_0 .net *"_s6", 0 0, L_0x13d6ba0; 1 drivers +v0x12737e0_0 .net "ands", 1 0, L_0x13d6ab0; 1 drivers +v0x1273950_0 .net "in", 3 0, L_0x13d72a0; 1 drivers +v0x1273a30_0 .net "out", 0 0, L_0x13d6f90; 1 drivers +L_0x13d6810 .part L_0x13d72a0, 0, 1; +L_0x13d6970 .part L_0x13d72a0, 1, 1; +L_0x13d6ab0 .concat8 [ 1 1 0 0], L_0x13d6750, L_0x13d6ba0; +L_0x13d6cb0 .part L_0x13d72a0, 2, 1; +L_0x13d6e10 .part L_0x13d72a0, 3, 1; +L_0x13d7000 .part L_0x13d6ab0, 0, 1; +L_0x13d71b0 .part L_0x13d6ab0, 1, 1; +S_0x1273b50 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1272bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d7340/d .functor AND 1, L_0x13d7400, L_0x13d7560, C4<1>, C4<1>; +L_0x13d7340 .delay 1 (30000,30000,30000) L_0x13d7340/d; +L_0x13d7790/d .functor AND 1, L_0x13d78a0, L_0x13d7a00, C4<1>, C4<1>; +L_0x13d7790 .delay 1 (30000,30000,30000) L_0x13d7790/d; +L_0x13d7b80/d .functor AND 1, L_0x13d7bf0, L_0x13d7da0, C4<1>, C4<1>; +L_0x13d7b80 .delay 1 (30000,30000,30000) L_0x13d7b80/d; +v0x1273d10_0 .net *"_s0", 0 0, L_0x13d7340; 1 drivers +v0x1273e10_0 .net *"_s10", 0 0, L_0x13d78a0; 1 drivers +v0x1273ef0_0 .net *"_s12", 0 0, L_0x13d7a00; 1 drivers +v0x1273fb0_0 .net *"_s14", 0 0, L_0x13d7bf0; 1 drivers +v0x1274090_0 .net *"_s16", 0 0, L_0x13d7da0; 1 drivers +v0x12741c0_0 .net *"_s3", 0 0, L_0x13d7400; 1 drivers +v0x12742a0_0 .net *"_s5", 0 0, L_0x13d7560; 1 drivers +v0x1274380_0 .net *"_s6", 0 0, L_0x13d7790; 1 drivers +v0x1274460_0 .net "ands", 1 0, L_0x13d76a0; 1 drivers +v0x12745d0_0 .net "in", 3 0, L_0x13d7fd0; 1 drivers +v0x12746b0_0 .net "out", 0 0, L_0x13d7b80; 1 drivers +L_0x13d7400 .part L_0x13d7fd0, 0, 1; +L_0x13d7560 .part L_0x13d7fd0, 1, 1; +L_0x13d76a0 .concat8 [ 1 1 0 0], L_0x13d7340, L_0x13d7790; +L_0x13d78a0 .part L_0x13d7fd0, 2, 1; +L_0x13d7a00 .part L_0x13d7fd0, 3, 1; +L_0x13d7bf0 .part L_0x13d76a0, 0, 1; +L_0x13d7da0 .part L_0x13d76a0, 1, 1; +S_0x1274c50 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x12729e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x13d9e30/d .functor AND 1, L_0x13d9ef0, L_0x13da0a0, C4<1>, C4<1>; +L_0x13d9e30 .delay 1 (30000,30000,30000) L_0x13d9e30/d; +v0x12767f0_0 .net *"_s10", 0 0, L_0x13d9ef0; 1 drivers +v0x12768d0_0 .net *"_s12", 0 0, L_0x13da0a0; 1 drivers +v0x12769b0_0 .net "ands", 1 0, L_0x13d9c00; 1 drivers +v0x1276a70_0 .net "in", 7 0, L_0x13da2d0; 1 drivers +v0x1276b50_0 .net "out", 0 0, L_0x13d9e30; 1 drivers +L_0x13d9010 .part L_0x13da2d0, 0, 4; +L_0x13d9c00 .concat8 [ 1 1 0 0], L_0x13d8d00, L_0x13d98f0; +L_0x13d9d40 .part L_0x13da2d0, 4, 4; +L_0x13d9ef0 .part L_0x13d9c00, 0, 1; +L_0x13da0a0 .part L_0x13d9c00, 1, 1; +S_0x1274e60 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1274c50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d84c0/d .functor AND 1, L_0x13d8580, L_0x13d86e0, C4<1>, C4<1>; +L_0x13d84c0 .delay 1 (30000,30000,30000) L_0x13d84c0/d; +L_0x13d8910/d .functor AND 1, L_0x13d8a20, L_0x13d8b80, C4<1>, C4<1>; +L_0x13d8910 .delay 1 (30000,30000,30000) L_0x13d8910/d; +L_0x13d8d00/d .functor AND 1, L_0x13d8d70, L_0x13d8f20, C4<1>, C4<1>; +L_0x13d8d00 .delay 1 (30000,30000,30000) L_0x13d8d00/d; +v0x12750b0_0 .net *"_s0", 0 0, L_0x13d84c0; 1 drivers +v0x12751b0_0 .net *"_s10", 0 0, L_0x13d8a20; 1 drivers +v0x1275290_0 .net *"_s12", 0 0, L_0x13d8b80; 1 drivers +v0x1275350_0 .net *"_s14", 0 0, L_0x13d8d70; 1 drivers +v0x1275430_0 .net *"_s16", 0 0, L_0x13d8f20; 1 drivers +v0x1275560_0 .net *"_s3", 0 0, L_0x13d8580; 1 drivers +v0x1275640_0 .net *"_s5", 0 0, L_0x13d86e0; 1 drivers +v0x1275720_0 .net *"_s6", 0 0, L_0x13d8910; 1 drivers +v0x1275800_0 .net "ands", 1 0, L_0x13d8820; 1 drivers +v0x1275970_0 .net "in", 3 0, L_0x13d9010; 1 drivers +v0x1275a50_0 .net "out", 0 0, L_0x13d8d00; 1 drivers +L_0x13d8580 .part L_0x13d9010, 0, 1; +L_0x13d86e0 .part L_0x13d9010, 1, 1; +L_0x13d8820 .concat8 [ 1 1 0 0], L_0x13d84c0, L_0x13d8910; +L_0x13d8a20 .part L_0x13d9010, 2, 1; +L_0x13d8b80 .part L_0x13d9010, 3, 1; +L_0x13d8d70 .part L_0x13d8820, 0, 1; +L_0x13d8f20 .part L_0x13d8820, 1, 1; +S_0x1275b70 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1274c50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x13d90b0/d .functor AND 1, L_0x13d9170, L_0x13d92d0, C4<1>, C4<1>; +L_0x13d90b0 .delay 1 (30000,30000,30000) L_0x13d90b0/d; +L_0x13d9500/d .functor AND 1, L_0x13d9610, L_0x13d9770, C4<1>, C4<1>; +L_0x13d9500 .delay 1 (30000,30000,30000) L_0x13d9500/d; +L_0x13d98f0/d .functor AND 1, L_0x13d9960, L_0x13d9b10, C4<1>, C4<1>; +L_0x13d98f0 .delay 1 (30000,30000,30000) L_0x13d98f0/d; +v0x1275d30_0 .net *"_s0", 0 0, L_0x13d90b0; 1 drivers +v0x1275e30_0 .net *"_s10", 0 0, L_0x13d9610; 1 drivers +v0x1275f10_0 .net *"_s12", 0 0, L_0x13d9770; 1 drivers +v0x1275fd0_0 .net *"_s14", 0 0, L_0x13d9960; 1 drivers +v0x12760b0_0 .net *"_s16", 0 0, L_0x13d9b10; 1 drivers +v0x12761e0_0 .net *"_s3", 0 0, L_0x13d9170; 1 drivers +v0x12762c0_0 .net *"_s5", 0 0, L_0x13d92d0; 1 drivers +v0x12763a0_0 .net *"_s6", 0 0, L_0x13d9500; 1 drivers +v0x1276480_0 .net "ands", 1 0, L_0x13d9410; 1 drivers +v0x12765f0_0 .net "in", 3 0, L_0x13d9d40; 1 drivers +v0x12766d0_0 .net "out", 0 0, L_0x13d98f0; 1 drivers +L_0x13d9170 .part L_0x13d9d40, 0, 1; +L_0x13d92d0 .part L_0x13d9d40, 1, 1; +L_0x13d9410 .concat8 [ 1 1 0 0], L_0x13d90b0, L_0x13d9500; +L_0x13d9610 .part L_0x13d9d40, 2, 1; +L_0x13d9770 .part L_0x13d9d40, 3, 1; +L_0x13d9960 .part L_0x13d9410, 0, 1; +L_0x13d9b10 .part L_0x13d9410, 1, 1; + .scope S_0xc4eec0; +T_0 ; + %wait E_0x1020b00; + %load/vec4 v0x127a070_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_0.7, 6; + %jmp T_0.8; +T_0.0 ; + %pushi/vec4 1, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.1 ; + %pushi/vec4 2, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.2 ; + %pushi/vec4 4, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.3 ; + %pushi/vec4 8, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.4 ; + %pushi/vec4 16, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.5 ; + %pushi/vec4 32, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.6 ; + %pushi/vec4 64, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.7 ; + %pushi/vec4 128, 0, 8; + %store/vec4 v0x127a150_0, 0, 8; + %jmp T_0.8; +T_0.8 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0xc983a0; +T_1 ; + %vpi_call 2 17 "$dumpfile", "alu.vcd" {0 0 0}; + %vpi_call 2 18 "$dumpvars", 32'sb00000000000000000000000000000000, S_0xc983a0 {0 0 0}; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %cmpi/ne 0, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x127b170_0; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x127b300_0; + %nor/r; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.0, 8; + %vpi_call 2 24 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.0 ; + %pushi/vec4 2147483647, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %pad/s 33; + %pushi/vec4 3221225472, 0, 32; + %concati/vec4 0, 0, 1; + %cmp/ne; + %flag_mov 8, 4; + %load/vec4 v0x127b170_0; + %nor/r; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x127b300_0; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.2, 8; + %vpi_call 2 29 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb10000000000000000000000000000000 {0 0 0}; +T_1.2 ; + %pushi/vec4 1, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %cmpi/ne 0, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x127b170_0; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x127b300_0; + %nor/r; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.4, 8; + %vpi_call 2 37 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.4 ; + %pushi/vec4 2147483648, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %cmpi/ne 2147483647, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x127b170_0; + %nor/r; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x127b300_0; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.6, 8; + %vpi_call 2 42 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb01111111111111111111111111111111 {0 0 0}; +T_1.6 ; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %xor; + %cmp/ne; + %jmp/0xz T_1.8, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %xor; + %vpi_call 2 50 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.8 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %xor; + %cmp/ne; + %jmp/0xz T_1.10, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %xor; + %vpi_call 2 55 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.10 ; + %pushi/vec4 3, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 4294967288, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 4294967280, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.12, 8; + %vpi_call 2 63 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.12 ; + %pushi/vec4 8, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 16, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.14, 4; + %vpi_call 2 68 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb00000000000000000000000000000001 {0 0 0}; +T_1.14 ; + %pushi/vec4 8, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 4294967280, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.16, 8; + %vpi_call 2 73 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.16 ; + %pushi/vec4 4294967288, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 16, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.18, 4; + %vpi_call 2 78 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, 32'sb00000000000000000000000000000001 {0 0 0}; +T_1.18 ; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %cmp/e; + %flag_get/vec4 4; + %inv; + %pad/u 32; + %load/vec4 v0x127aed0_0; + %and; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.20, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %and; + %vpi_call 2 86 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.20 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %cmp/e; + %flag_get/vec4 4; + %inv; + %pad/u 32; + %load/vec4 v0x127aed0_0; + %and; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.22, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %and; + %vpi_call 2 91 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.22 ; + %pushi/vec4 5, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %and; + %inv; + %cmp/ne; + %jmp/0xz T_1.24, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %and; + %inv; + %vpi_call 2 99 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.24 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %and; + %inv; + %cmp/ne; + %jmp/0xz T_1.26, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %and; + %inv; + %vpi_call 2 104 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.26 ; + %pushi/vec4 6, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %inv; + %cmp/ne; + %jmp/0xz T_1.28, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %inv; + %vpi_call 2 112 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.28 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %inv; + %cmp/ne; + %jmp/0xz T_1.30, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %inv; + %vpi_call 2 117 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.30 ; + %pushi/vec4 7, 0, 3; + %store/vec4 v0x127b0a0_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %cmp/ne; + %jmp/0xz T_1.32, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %vpi_call 2 125 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.32 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x127adc0_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x127aed0_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x127b210_0; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %cmp/ne; + %jmp/0xz T_1.34, 4; + %load/vec4 v0x127adc0_0; + %load/vec4 v0x127aed0_0; + %or; + %vpi_call 2 130 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x127adc0_0, v0x127aed0_0, v0x127b210_0, v0x127b0a0_0, v0x127b170_0, v0x127b300_0, v0x127afa0_0, S<0,vec4,s32> {1 0 0}; +T_1.34 ; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 5; + "N/A"; + ""; + "alu.t.v"; + "./alu.v"; + "./alu1.v"; diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..b1c6859 --- /dev/null +++ b/alu.t.v @@ -0,0 +1,133 @@ +`timescale 1 ns / 1 ps +`include "alu.v" + +module testALU(); + reg signed[31:0] a; + reg signed[31:0] b; + reg[2:0] command; + wire carryout; + wire zero; + wire overflow; + wire signed[31:0] result; + + + ALU dut(result, carryout, zero, overflow, a, b, command); + + initial begin + $dumpfile("alu.vcd"); + $dumpvars(0, testALU); + //Addition tests + command = 3'd0; + a = -4; + b = 4; #1000000 + if (result != 0 || overflow || !zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); + end + a = 31'h7fffffff; + b = 1; #1000000 + if (result != -2147483648 || !overflow || zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, -2147483648); + end + + //Subtraction tests + command = 3'd1; + a = 4; + b = 4; #1000000 + if (result != 0 || overflow || !zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); + end + a = -2147483648; + b = 1; #1000000 + if (result != 2147483647 || !overflow || zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 2147483647); + end + + //XOR tests + command = 3'd2; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != (a^b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a^b); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != (a^b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a^b); + end + + //SLT tests + command = 3'd3; + a = -8; + b = -16; #1000000 + if (!result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); + end + a = 8; + b = 16; #1000000 + if (result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 1); + end + a = 8; + b = -16; #1000000 + if (!result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); + end + a = -8; + b = 16; #1000000 + if (result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 1); + end + + //AND tests + command = 3'd4; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != a&b) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a&b); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != a&b) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a&b); + end + + //AND tests + command = 3'd5; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != ~(a&b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a&b)); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != ~(a&b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a&b)); + end + + //NOR tests + command = 3'd6; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != ~(a|b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a|b)); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != ~(a|b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a|b)); + end + + //OR tests + command = 3'd7; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != (a|b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, (a|b)); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != (a|b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, (a|b)); + end + end +endmodule diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..05cc877 --- /dev/null +++ b/alu.v @@ -0,0 +1,78 @@ +`include "alu1.v" +module ALU( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input[2:0] command +); + wire[32:0] carryinbus; + wire[31:0] zerobus; + wire[31:0] overrideBus; + wire[31:0] resultBus; + wire mixedSigns; + wire sameSigns; + wire possibleOverflow; + wire overFlowPossible; + wire overflowPre; + wire addOrSub; + wire sltPre; + + reg[7:0] commandslice; + always @(command) begin + case (command) + 0: begin commandslice = 8'd1<<0; end + 1: begin commandslice = 8'd1<<1; end + 2: begin commandslice = 8'd1<<2; end + 3: begin commandslice = 8'd1<<3; end + 4: begin commandslice = 8'd1<<4; end + 5: begin commandslice = 8'd1<<5; end + 6: begin commandslice = 8'd1<<6; end + 7: begin commandslice = 8'd1<<7; end + endcase + end + + genvar i; + generate + for(i = 0; i < 32; i = i + 1) begin: alu_slices + alu1 alu1_inst(resultBus[i], + carryinbus[i+1], + zerobus[i], + operandA[i], + operandB[i], + carryinbus[i], + commandslice); + // we need to be able to force the first bit to be a 1 + // for SLT. Otherwise, we never use the override bus. + if (i != 0) begin + `OR false_inst(overrideBus[i], 1'b0, 1'b0); + end + end + endgenerate + //set the the first carry in only if we are subtracting + // this or gate is a wire + `OR subflag(carryinbus[0], commandslice[1], commandslice[1]); + //set carryout to the lest carry bit + //this or gate is also a wire + `OR carryor(carryout, carryinbus[32], carryinbus[32]); + //and all the zero outputs to get the zero output + and32 zeroout(zero, zerobus); + //it's nice to know these + `XNOR sameSignXNOR(sameSigns, operandA[31], operandB[31]); + `NOT differentSignNOT(mixedSigns, sameSigns); + //calculate overflow + `XOR overflowXor(possibleOverflow, result[31], carryout); + mux1 overflowMux(overFlowPossible, mixedSigns, sameSigns, commandslice[0]); + `OR addSubOr(addOrSub, commandslice[0], commandslice[1]); + `AND overflowAnd(overflowPre, possibleOverflow, overFlowPossible); + `AND overflowOut(overflow, overflowPre, addOrSub); + + //handle the slt stuff + `XOR sltOut(sltPre, carryout, mixedSigns); + `AND sltOut2(overrideBus[0], sltPre, commandslice[3]); + + or32P resultOr(result, resultBus, overrideBus); + +endmodule diff --git a/alu.vcd b/alu.vcd new file mode 100644 index 0000000..df6fec4 --- /dev/null +++ b/alu.vcd @@ -0,0 +1,58994 @@ +$date + Fri Oct 13 01:46:46 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testALU $end +$var wire 1 ! zero $end +$var wire 32 " result [31:0] $end +$var wire 1 # overflow $end +$var wire 1 $ carryout $end +$var reg 32 % a [31:0] $end +$var reg 32 & b [31:0] $end +$var reg 3 ' command [2:0] $end +$scope module dut $end +$var wire 1 ( addOrSub $end +$var wire 1 $ carryout $end +$var wire 3 ) command [2:0] $end +$var wire 1 * mixedSigns $end +$var wire 32 + operandA [31:0] $end +$var wire 32 , operandB [31:0] $end +$var wire 1 # overflow $end +$var wire 1 - overflowPre $end +$var wire 1 . possibleOverflow $end +$var wire 1 / sameSigns $end +$var wire 1 0 sltPre $end +$var wire 32 1 zerobus [31:0] $end +$var wire 1 ! zero $end +$var wire 32 2 resultBus [31:0] $end +$var wire 32 3 result [31:0] $end +$var wire 32 4 overrideBus [31:0] $end +$var wire 1 5 overFlowPossible $end +$var wire 33 6 carryinbus [32:0] $end +$var reg 8 7 commandslice [7:0] $end +$scope begin alu_slices[0] $end +$scope module alu1_inst $end +$var wire 1 8 A $end +$var wire 1 9 A_ $end +$var wire 1 : B $end +$var wire 1 ; B_ $end +$var wire 1 < carryin $end +$var wire 8 = command [7:0] $end +$var wire 1 > zero $end +$var wire 8 ? results [7:0] $end +$var wire 1 @ result $end +$var wire 8 A carryouts [7:0] $end +$var wire 1 B carryout $end +$scope module adder $end +$var wire 1 8 a $end +$var wire 1 : b $end +$var wire 1 < carryin $end +$var wire 1 C carryout $end +$var wire 1 D sum $end +$var wire 1 E s1 $end +$var wire 1 F c2 $end +$var wire 1 G c1 $end +$scope module a1 $end +$var wire 1 8 a $end +$var wire 1 : b $end +$var wire 1 G carryout $end +$var wire 1 E sum $end +$upscope $end +$scope module a2 $end +$var wire 1 E a $end +$var wire 1 < b $end +$var wire 1 F carryout $end +$var wire 1 D sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 H in [7:0] $end +$var wire 8 I sel [7:0] $end +$var wire 1 B out $end +$var wire 8 J ands [7:0] $end +$scope module andP $end +$var wire 8 K A [7:0] $end +$var wire 8 L B [7:0] $end +$var wire 8 M out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 N in [7:0] $end +$var wire 1 B out $end +$var wire 2 O ors [1:0] $end +$scope module or_1 $end +$var wire 4 P in [3:0] $end +$var wire 1 Q out $end +$var wire 2 R ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 S in [3:0] $end +$var wire 1 T out $end +$var wire 2 U ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 V in [7:0] $end +$var wire 8 W sel [7:0] $end +$var wire 1 @ out $end +$var wire 8 X ands [7:0] $end +$scope module andP $end +$var wire 8 Y A [7:0] $end +$var wire 8 Z B [7:0] $end +$var wire 8 [ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 \ in [7:0] $end +$var wire 1 @ out $end +$var wire 2 ] ors [1:0] $end +$scope module or_1 $end +$var wire 4 ^ in [3:0] $end +$var wire 1 _ out $end +$var wire 2 ` ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 a in [3:0] $end +$var wire 1 b out $end +$var wire 2 c ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 8 a $end +$var wire 1 9 a_ $end +$var wire 1 : b $end +$var wire 1 ; b_ $end +$var wire 1 < carryin $end +$var wire 1 d eq $end +$var wire 1 e lt $end +$var wire 1 f out $end +$var wire 1 g w0 $end +$upscope $end +$scope module sub $end +$var wire 1 8 a $end +$var wire 1 ; b $end +$var wire 1 < carryin $end +$var wire 1 h carryout $end +$var wire 1 i sum $end +$var wire 1 j s1 $end +$var wire 1 k c2 $end +$var wire 1 l c1 $end +$scope module a1 $end +$var wire 1 8 a $end +$var wire 1 ; b $end +$var wire 1 l carryout $end +$var wire 1 j sum $end +$upscope $end +$scope module a2 $end +$var wire 1 j a $end +$var wire 1 < b $end +$var wire 1 k carryout $end +$var wire 1 i sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[1] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 m A $end +$var wire 1 n A_ $end +$var wire 1 o B $end +$var wire 1 p B_ $end +$var wire 1 q carryin $end +$var wire 8 r command [7:0] $end +$var wire 1 s zero $end +$var wire 8 t results [7:0] $end +$var wire 1 u result $end +$var wire 8 v carryouts [7:0] $end +$var wire 1 w carryout $end +$scope module adder $end +$var wire 1 m a $end +$var wire 1 o b $end +$var wire 1 q carryin $end +$var wire 1 x carryout $end +$var wire 1 y sum $end +$var wire 1 z s1 $end +$var wire 1 { c2 $end +$var wire 1 | c1 $end +$scope module a1 $end +$var wire 1 m a $end +$var wire 1 o b $end +$var wire 1 | carryout $end +$var wire 1 z sum $end +$upscope $end +$scope module a2 $end +$var wire 1 z a $end +$var wire 1 q b $end +$var wire 1 { carryout $end +$var wire 1 y sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 } in [7:0] $end +$var wire 8 ~ sel [7:0] $end +$var wire 1 w out $end +$var wire 8 !" ands [7:0] $end +$scope module andP $end +$var wire 8 "" A [7:0] $end +$var wire 8 #" B [7:0] $end +$var wire 8 $" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 %" in [7:0] $end +$var wire 1 w out $end +$var wire 2 &" ors [1:0] $end +$scope module or_1 $end +$var wire 4 '" in [3:0] $end +$var wire 1 (" out $end +$var wire 2 )" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 *" in [3:0] $end +$var wire 1 +" out $end +$var wire 2 ," ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 -" in [7:0] $end +$var wire 8 ." sel [7:0] $end +$var wire 1 u out $end +$var wire 8 /" ands [7:0] $end +$scope module andP $end +$var wire 8 0" A [7:0] $end +$var wire 8 1" B [7:0] $end +$var wire 8 2" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 3" in [7:0] $end +$var wire 1 u out $end +$var wire 2 4" ors [1:0] $end +$scope module or_1 $end +$var wire 4 5" in [3:0] $end +$var wire 1 6" out $end +$var wire 2 7" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 8" in [3:0] $end +$var wire 1 9" out $end +$var wire 2 :" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 m a $end +$var wire 1 n a_ $end +$var wire 1 o b $end +$var wire 1 p b_ $end +$var wire 1 q carryin $end +$var wire 1 ;" eq $end +$var wire 1 <" lt $end +$var wire 1 =" out $end +$var wire 1 >" w0 $end +$upscope $end +$scope module sub $end +$var wire 1 m a $end +$var wire 1 p b $end +$var wire 1 q carryin $end +$var wire 1 ?" carryout $end +$var wire 1 @" sum $end +$var wire 1 A" s1 $end +$var wire 1 B" c2 $end +$var wire 1 C" c1 $end +$scope module a1 $end +$var wire 1 m a $end +$var wire 1 p b $end +$var wire 1 C" carryout $end +$var wire 1 A" sum $end +$upscope $end +$scope module a2 $end +$var wire 1 A" a $end +$var wire 1 q b $end +$var wire 1 B" carryout $end +$var wire 1 @" sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[2] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 D" A $end +$var wire 1 E" A_ $end +$var wire 1 F" B $end +$var wire 1 G" B_ $end +$var wire 1 H" carryin $end +$var wire 8 I" command [7:0] $end +$var wire 1 J" zero $end +$var wire 8 K" results [7:0] $end +$var wire 1 L" result $end +$var wire 8 M" carryouts [7:0] $end +$var wire 1 N" carryout $end +$scope module adder $end +$var wire 1 D" a $end +$var wire 1 F" b $end +$var wire 1 H" carryin $end +$var wire 1 O" carryout $end +$var wire 1 P" sum $end +$var wire 1 Q" s1 $end +$var wire 1 R" c2 $end +$var wire 1 S" c1 $end +$scope module a1 $end +$var wire 1 D" a $end +$var wire 1 F" b $end +$var wire 1 S" carryout $end +$var wire 1 Q" sum $end +$upscope $end +$scope module a2 $end +$var wire 1 Q" a $end +$var wire 1 H" b $end +$var wire 1 R" carryout $end +$var wire 1 P" sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 T" in [7:0] $end +$var wire 8 U" sel [7:0] $end +$var wire 1 N" out $end +$var wire 8 V" ands [7:0] $end +$scope module andP $end +$var wire 8 W" A [7:0] $end +$var wire 8 X" B [7:0] $end +$var wire 8 Y" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 Z" in [7:0] $end +$var wire 1 N" out $end +$var wire 2 [" ors [1:0] $end +$scope module or_1 $end +$var wire 4 \" in [3:0] $end +$var wire 1 ]" out $end +$var wire 2 ^" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 _" in [3:0] $end +$var wire 1 `" out $end +$var wire 2 a" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 b" in [7:0] $end +$var wire 8 c" sel [7:0] $end +$var wire 1 L" out $end +$var wire 8 d" ands [7:0] $end +$scope module andP $end +$var wire 8 e" A [7:0] $end +$var wire 8 f" B [7:0] $end +$var wire 8 g" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 h" in [7:0] $end +$var wire 1 L" out $end +$var wire 2 i" ors [1:0] $end +$scope module or_1 $end +$var wire 4 j" in [3:0] $end +$var wire 1 k" out $end +$var wire 2 l" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 m" in [3:0] $end +$var wire 1 n" out $end +$var wire 2 o" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 D" a $end +$var wire 1 E" a_ $end +$var wire 1 F" b $end +$var wire 1 G" b_ $end +$var wire 1 H" carryin $end +$var wire 1 p" eq $end +$var wire 1 q" lt $end +$var wire 1 r" out $end +$var wire 1 s" w0 $end +$upscope $end +$scope module sub $end +$var wire 1 D" a $end +$var wire 1 G" b $end +$var wire 1 H" carryin $end +$var wire 1 t" carryout $end +$var wire 1 u" sum $end +$var wire 1 v" s1 $end +$var wire 1 w" c2 $end +$var wire 1 x" c1 $end +$scope module a1 $end +$var wire 1 D" a $end +$var wire 1 G" b $end +$var wire 1 x" carryout $end +$var wire 1 v" sum $end +$upscope $end +$scope module a2 $end +$var wire 1 v" a $end +$var wire 1 H" b $end +$var wire 1 w" carryout $end +$var wire 1 u" sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[3] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 y" A $end +$var wire 1 z" A_ $end +$var wire 1 {" B $end +$var wire 1 |" B_ $end +$var wire 1 }" carryin $end +$var wire 8 ~" command [7:0] $end +$var wire 1 !# zero $end +$var wire 8 "# results [7:0] $end +$var wire 1 ## result $end +$var wire 8 $# carryouts [7:0] $end +$var wire 1 %# carryout $end +$scope module adder $end +$var wire 1 y" a $end +$var wire 1 {" b $end +$var wire 1 }" carryin $end +$var wire 1 &# carryout $end +$var wire 1 '# sum $end +$var wire 1 (# s1 $end +$var wire 1 )# c2 $end +$var wire 1 *# c1 $end +$scope module a1 $end +$var wire 1 y" a $end +$var wire 1 {" b $end +$var wire 1 *# carryout $end +$var wire 1 (# sum $end +$upscope $end +$scope module a2 $end +$var wire 1 (# a $end +$var wire 1 }" b $end +$var wire 1 )# carryout $end +$var wire 1 '# sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 +# in [7:0] $end +$var wire 8 ,# sel [7:0] $end +$var wire 1 %# out $end +$var wire 8 -# ands [7:0] $end +$scope module andP $end +$var wire 8 .# A [7:0] $end +$var wire 8 /# B [7:0] $end +$var wire 8 0# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 1# in [7:0] $end +$var wire 1 %# out $end +$var wire 2 2# ors [1:0] $end +$scope module or_1 $end +$var wire 4 3# in [3:0] $end +$var wire 1 4# out $end +$var wire 2 5# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 6# in [3:0] $end +$var wire 1 7# out $end +$var wire 2 8# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 9# in [7:0] $end +$var wire 8 :# sel [7:0] $end +$var wire 1 ## out $end +$var wire 8 ;# ands [7:0] $end +$scope module andP $end +$var wire 8 <# A [7:0] $end +$var wire 8 =# B [7:0] $end +$var wire 8 ># out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ?# in [7:0] $end +$var wire 1 ## out $end +$var wire 2 @# ors [1:0] $end +$scope module or_1 $end +$var wire 4 A# in [3:0] $end +$var wire 1 B# out $end +$var wire 2 C# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 D# in [3:0] $end +$var wire 1 E# out $end +$var wire 2 F# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 y" a $end +$var wire 1 z" a_ $end +$var wire 1 {" b $end +$var wire 1 |" b_ $end +$var wire 1 }" carryin $end +$var wire 1 G# eq $end +$var wire 1 H# lt $end +$var wire 1 I# out $end +$var wire 1 J# w0 $end +$upscope $end +$scope module sub $end +$var wire 1 y" a $end +$var wire 1 |" b $end +$var wire 1 }" carryin $end +$var wire 1 K# carryout $end +$var wire 1 L# sum $end +$var wire 1 M# s1 $end +$var wire 1 N# c2 $end +$var wire 1 O# c1 $end +$scope module a1 $end +$var wire 1 y" a $end +$var wire 1 |" b $end +$var wire 1 O# carryout $end +$var wire 1 M# sum $end +$upscope $end +$scope module a2 $end +$var wire 1 M# a $end +$var wire 1 }" b $end +$var wire 1 N# carryout $end +$var wire 1 L# sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[4] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 P# A $end +$var wire 1 Q# A_ $end +$var wire 1 R# B $end +$var wire 1 S# B_ $end +$var wire 1 T# carryin $end +$var wire 8 U# command [7:0] $end +$var wire 1 V# zero $end +$var wire 8 W# results [7:0] $end +$var wire 1 X# result $end +$var wire 8 Y# carryouts [7:0] $end +$var wire 1 Z# carryout $end +$scope module adder $end +$var wire 1 P# a $end +$var wire 1 R# b $end +$var wire 1 T# carryin $end +$var wire 1 [# carryout $end +$var wire 1 \# sum $end +$var wire 1 ]# s1 $end +$var wire 1 ^# c2 $end +$var wire 1 _# c1 $end +$scope module a1 $end +$var wire 1 P# a $end +$var wire 1 R# b $end +$var wire 1 _# carryout $end +$var wire 1 ]# sum $end +$upscope $end +$scope module a2 $end +$var wire 1 ]# a $end +$var wire 1 T# b $end +$var wire 1 ^# carryout $end +$var wire 1 \# sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 `# in [7:0] $end +$var wire 8 a# sel [7:0] $end +$var wire 1 Z# out $end +$var wire 8 b# ands [7:0] $end +$scope module andP $end +$var wire 8 c# A [7:0] $end +$var wire 8 d# B [7:0] $end +$var wire 8 e# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 f# in [7:0] $end +$var wire 1 Z# out $end +$var wire 2 g# ors [1:0] $end +$scope module or_1 $end +$var wire 4 h# in [3:0] $end +$var wire 1 i# out $end +$var wire 2 j# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 k# in [3:0] $end +$var wire 1 l# out $end +$var wire 2 m# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 n# in [7:0] $end +$var wire 8 o# sel [7:0] $end +$var wire 1 X# out $end +$var wire 8 p# ands [7:0] $end +$scope module andP $end +$var wire 8 q# A [7:0] $end +$var wire 8 r# B [7:0] $end +$var wire 8 s# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 t# in [7:0] $end +$var wire 1 X# out $end +$var wire 2 u# ors [1:0] $end +$scope module or_1 $end +$var wire 4 v# in [3:0] $end +$var wire 1 w# out $end +$var wire 2 x# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 y# in [3:0] $end +$var wire 1 z# out $end +$var wire 2 {# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 P# a $end +$var wire 1 Q# a_ $end +$var wire 1 R# b $end +$var wire 1 S# b_ $end +$var wire 1 T# carryin $end +$var wire 1 |# eq $end +$var wire 1 }# lt $end +$var wire 1 ~# out $end +$var wire 1 !$ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 P# a $end +$var wire 1 S# b $end +$var wire 1 T# carryin $end +$var wire 1 "$ carryout $end +$var wire 1 #$ sum $end +$var wire 1 $$ s1 $end +$var wire 1 %$ c2 $end +$var wire 1 &$ c1 $end +$scope module a1 $end +$var wire 1 P# a $end +$var wire 1 S# b $end +$var wire 1 &$ carryout $end +$var wire 1 $$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 $$ a $end +$var wire 1 T# b $end +$var wire 1 %$ carryout $end +$var wire 1 #$ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[5] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 '$ A $end +$var wire 1 ($ A_ $end +$var wire 1 )$ B $end +$var wire 1 *$ B_ $end +$var wire 1 +$ carryin $end +$var wire 8 ,$ command [7:0] $end +$var wire 1 -$ zero $end +$var wire 8 .$ results [7:0] $end +$var wire 1 /$ result $end +$var wire 8 0$ carryouts [7:0] $end +$var wire 1 1$ carryout $end +$scope module adder $end +$var wire 1 '$ a $end +$var wire 1 )$ b $end +$var wire 1 +$ carryin $end +$var wire 1 2$ carryout $end +$var wire 1 3$ sum $end +$var wire 1 4$ s1 $end +$var wire 1 5$ c2 $end +$var wire 1 6$ c1 $end +$scope module a1 $end +$var wire 1 '$ a $end +$var wire 1 )$ b $end +$var wire 1 6$ carryout $end +$var wire 1 4$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 4$ a $end +$var wire 1 +$ b $end +$var wire 1 5$ carryout $end +$var wire 1 3$ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 7$ in [7:0] $end +$var wire 8 8$ sel [7:0] $end +$var wire 1 1$ out $end +$var wire 8 9$ ands [7:0] $end +$scope module andP $end +$var wire 8 :$ A [7:0] $end +$var wire 8 ;$ B [7:0] $end +$var wire 8 <$ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 =$ in [7:0] $end +$var wire 1 1$ out $end +$var wire 2 >$ ors [1:0] $end +$scope module or_1 $end +$var wire 4 ?$ in [3:0] $end +$var wire 1 @$ out $end +$var wire 2 A$ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 B$ in [3:0] $end +$var wire 1 C$ out $end +$var wire 2 D$ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 E$ in [7:0] $end +$var wire 8 F$ sel [7:0] $end +$var wire 1 /$ out $end +$var wire 8 G$ ands [7:0] $end +$scope module andP $end +$var wire 8 H$ A [7:0] $end +$var wire 8 I$ B [7:0] $end +$var wire 8 J$ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 K$ in [7:0] $end +$var wire 1 /$ out $end +$var wire 2 L$ ors [1:0] $end +$scope module or_1 $end +$var wire 4 M$ in [3:0] $end +$var wire 1 N$ out $end +$var wire 2 O$ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 P$ in [3:0] $end +$var wire 1 Q$ out $end +$var wire 2 R$ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 '$ a $end +$var wire 1 ($ a_ $end +$var wire 1 )$ b $end +$var wire 1 *$ b_ $end +$var wire 1 +$ carryin $end +$var wire 1 S$ eq $end +$var wire 1 T$ lt $end +$var wire 1 U$ out $end +$var wire 1 V$ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 '$ a $end +$var wire 1 *$ b $end +$var wire 1 +$ carryin $end +$var wire 1 W$ carryout $end +$var wire 1 X$ sum $end +$var wire 1 Y$ s1 $end +$var wire 1 Z$ c2 $end +$var wire 1 [$ c1 $end +$scope module a1 $end +$var wire 1 '$ a $end +$var wire 1 *$ b $end +$var wire 1 [$ carryout $end +$var wire 1 Y$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 Y$ a $end +$var wire 1 +$ b $end +$var wire 1 Z$ carryout $end +$var wire 1 X$ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[6] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 \$ A $end +$var wire 1 ]$ A_ $end +$var wire 1 ^$ B $end +$var wire 1 _$ B_ $end +$var wire 1 `$ carryin $end +$var wire 8 a$ command [7:0] $end +$var wire 1 b$ zero $end +$var wire 8 c$ results [7:0] $end +$var wire 1 d$ result $end +$var wire 8 e$ carryouts [7:0] $end +$var wire 1 f$ carryout $end +$scope module adder $end +$var wire 1 \$ a $end +$var wire 1 ^$ b $end +$var wire 1 `$ carryin $end +$var wire 1 g$ carryout $end +$var wire 1 h$ sum $end +$var wire 1 i$ s1 $end +$var wire 1 j$ c2 $end +$var wire 1 k$ c1 $end +$scope module a1 $end +$var wire 1 \$ a $end +$var wire 1 ^$ b $end +$var wire 1 k$ carryout $end +$var wire 1 i$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 i$ a $end +$var wire 1 `$ b $end +$var wire 1 j$ carryout $end +$var wire 1 h$ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 l$ in [7:0] $end +$var wire 8 m$ sel [7:0] $end +$var wire 1 f$ out $end +$var wire 8 n$ ands [7:0] $end +$scope module andP $end +$var wire 8 o$ A [7:0] $end +$var wire 8 p$ B [7:0] $end +$var wire 8 q$ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 r$ in [7:0] $end +$var wire 1 f$ out $end +$var wire 2 s$ ors [1:0] $end +$scope module or_1 $end +$var wire 4 t$ in [3:0] $end +$var wire 1 u$ out $end +$var wire 2 v$ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 w$ in [3:0] $end +$var wire 1 x$ out $end +$var wire 2 y$ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 z$ in [7:0] $end +$var wire 8 {$ sel [7:0] $end +$var wire 1 d$ out $end +$var wire 8 |$ ands [7:0] $end +$scope module andP $end +$var wire 8 }$ A [7:0] $end +$var wire 8 ~$ B [7:0] $end +$var wire 8 !% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 "% in [7:0] $end +$var wire 1 d$ out $end +$var wire 2 #% ors [1:0] $end +$scope module or_1 $end +$var wire 4 $% in [3:0] $end +$var wire 1 %% out $end +$var wire 2 &% ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 '% in [3:0] $end +$var wire 1 (% out $end +$var wire 2 )% ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 \$ a $end +$var wire 1 ]$ a_ $end +$var wire 1 ^$ b $end +$var wire 1 _$ b_ $end +$var wire 1 `$ carryin $end +$var wire 1 *% eq $end +$var wire 1 +% lt $end +$var wire 1 ,% out $end +$var wire 1 -% w0 $end +$upscope $end +$scope module sub $end +$var wire 1 \$ a $end +$var wire 1 _$ b $end +$var wire 1 `$ carryin $end +$var wire 1 .% carryout $end +$var wire 1 /% sum $end +$var wire 1 0% s1 $end +$var wire 1 1% c2 $end +$var wire 1 2% c1 $end +$scope module a1 $end +$var wire 1 \$ a $end +$var wire 1 _$ b $end +$var wire 1 2% carryout $end +$var wire 1 0% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 0% a $end +$var wire 1 `$ b $end +$var wire 1 1% carryout $end +$var wire 1 /% sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[7] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 3% A $end +$var wire 1 4% A_ $end +$var wire 1 5% B $end +$var wire 1 6% B_ $end +$var wire 1 7% carryin $end +$var wire 8 8% command [7:0] $end +$var wire 1 9% zero $end +$var wire 8 :% results [7:0] $end +$var wire 1 ;% result $end +$var wire 8 <% carryouts [7:0] $end +$var wire 1 =% carryout $end +$scope module adder $end +$var wire 1 3% a $end +$var wire 1 5% b $end +$var wire 1 7% carryin $end +$var wire 1 >% carryout $end +$var wire 1 ?% sum $end +$var wire 1 @% s1 $end +$var wire 1 A% c2 $end +$var wire 1 B% c1 $end +$scope module a1 $end +$var wire 1 3% a $end +$var wire 1 5% b $end +$var wire 1 B% carryout $end +$var wire 1 @% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 @% a $end +$var wire 1 7% b $end +$var wire 1 A% carryout $end +$var wire 1 ?% sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 C% in [7:0] $end +$var wire 8 D% sel [7:0] $end +$var wire 1 =% out $end +$var wire 8 E% ands [7:0] $end +$scope module andP $end +$var wire 8 F% A [7:0] $end +$var wire 8 G% B [7:0] $end +$var wire 8 H% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 I% in [7:0] $end +$var wire 1 =% out $end +$var wire 2 J% ors [1:0] $end +$scope module or_1 $end +$var wire 4 K% in [3:0] $end +$var wire 1 L% out $end +$var wire 2 M% ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 N% in [3:0] $end +$var wire 1 O% out $end +$var wire 2 P% ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 Q% in [7:0] $end +$var wire 8 R% sel [7:0] $end +$var wire 1 ;% out $end +$var wire 8 S% ands [7:0] $end +$scope module andP $end +$var wire 8 T% A [7:0] $end +$var wire 8 U% B [7:0] $end +$var wire 8 V% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 W% in [7:0] $end +$var wire 1 ;% out $end +$var wire 2 X% ors [1:0] $end +$scope module or_1 $end +$var wire 4 Y% in [3:0] $end +$var wire 1 Z% out $end +$var wire 2 [% ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 \% in [3:0] $end +$var wire 1 ]% out $end +$var wire 2 ^% ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 3% a $end +$var wire 1 4% a_ $end +$var wire 1 5% b $end +$var wire 1 6% b_ $end +$var wire 1 7% carryin $end +$var wire 1 _% eq $end +$var wire 1 `% lt $end +$var wire 1 a% out $end +$var wire 1 b% w0 $end +$upscope $end +$scope module sub $end +$var wire 1 3% a $end +$var wire 1 6% b $end +$var wire 1 7% carryin $end +$var wire 1 c% carryout $end +$var wire 1 d% sum $end +$var wire 1 e% s1 $end +$var wire 1 f% c2 $end +$var wire 1 g% c1 $end +$scope module a1 $end +$var wire 1 3% a $end +$var wire 1 6% b $end +$var wire 1 g% carryout $end +$var wire 1 e% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 e% a $end +$var wire 1 7% b $end +$var wire 1 f% carryout $end +$var wire 1 d% sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[8] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 h% A $end +$var wire 1 i% A_ $end +$var wire 1 j% B $end +$var wire 1 k% B_ $end +$var wire 1 l% carryin $end +$var wire 8 m% command [7:0] $end +$var wire 1 n% zero $end +$var wire 8 o% results [7:0] $end +$var wire 1 p% result $end +$var wire 8 q% carryouts [7:0] $end +$var wire 1 r% carryout $end +$scope module adder $end +$var wire 1 h% a $end +$var wire 1 j% b $end +$var wire 1 l% carryin $end +$var wire 1 s% carryout $end +$var wire 1 t% sum $end +$var wire 1 u% s1 $end +$var wire 1 v% c2 $end +$var wire 1 w% c1 $end +$scope module a1 $end +$var wire 1 h% a $end +$var wire 1 j% b $end +$var wire 1 w% carryout $end +$var wire 1 u% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 u% a $end +$var wire 1 l% b $end +$var wire 1 v% carryout $end +$var wire 1 t% sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 x% in [7:0] $end +$var wire 8 y% sel [7:0] $end +$var wire 1 r% out $end +$var wire 8 z% ands [7:0] $end +$scope module andP $end +$var wire 8 {% A [7:0] $end +$var wire 8 |% B [7:0] $end +$var wire 8 }% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ~% in [7:0] $end +$var wire 1 r% out $end +$var wire 2 !& ors [1:0] $end +$scope module or_1 $end +$var wire 4 "& in [3:0] $end +$var wire 1 #& out $end +$var wire 2 $& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 %& in [3:0] $end +$var wire 1 && out $end +$var wire 2 '& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 (& in [7:0] $end +$var wire 8 )& sel [7:0] $end +$var wire 1 p% out $end +$var wire 8 *& ands [7:0] $end +$scope module andP $end +$var wire 8 +& A [7:0] $end +$var wire 8 ,& B [7:0] $end +$var wire 8 -& out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 .& in [7:0] $end +$var wire 1 p% out $end +$var wire 2 /& ors [1:0] $end +$scope module or_1 $end +$var wire 4 0& in [3:0] $end +$var wire 1 1& out $end +$var wire 2 2& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 3& in [3:0] $end +$var wire 1 4& out $end +$var wire 2 5& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 h% a $end +$var wire 1 i% a_ $end +$var wire 1 j% b $end +$var wire 1 k% b_ $end +$var wire 1 l% carryin $end +$var wire 1 6& eq $end +$var wire 1 7& lt $end +$var wire 1 8& out $end +$var wire 1 9& w0 $end +$upscope $end +$scope module sub $end +$var wire 1 h% a $end +$var wire 1 k% b $end +$var wire 1 l% carryin $end +$var wire 1 :& carryout $end +$var wire 1 ;& sum $end +$var wire 1 <& s1 $end +$var wire 1 =& c2 $end +$var wire 1 >& c1 $end +$scope module a1 $end +$var wire 1 h% a $end +$var wire 1 k% b $end +$var wire 1 >& carryout $end +$var wire 1 <& sum $end +$upscope $end +$scope module a2 $end +$var wire 1 <& a $end +$var wire 1 l% b $end +$var wire 1 =& carryout $end +$var wire 1 ;& sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[9] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 ?& A $end +$var wire 1 @& A_ $end +$var wire 1 A& B $end +$var wire 1 B& B_ $end +$var wire 1 C& carryin $end +$var wire 8 D& command [7:0] $end +$var wire 1 E& zero $end +$var wire 8 F& results [7:0] $end +$var wire 1 G& result $end +$var wire 8 H& carryouts [7:0] $end +$var wire 1 I& carryout $end +$scope module adder $end +$var wire 1 ?& a $end +$var wire 1 A& b $end +$var wire 1 C& carryin $end +$var wire 1 J& carryout $end +$var wire 1 K& sum $end +$var wire 1 L& s1 $end +$var wire 1 M& c2 $end +$var wire 1 N& c1 $end +$scope module a1 $end +$var wire 1 ?& a $end +$var wire 1 A& b $end +$var wire 1 N& carryout $end +$var wire 1 L& sum $end +$upscope $end +$scope module a2 $end +$var wire 1 L& a $end +$var wire 1 C& b $end +$var wire 1 M& carryout $end +$var wire 1 K& sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 O& in [7:0] $end +$var wire 8 P& sel [7:0] $end +$var wire 1 I& out $end +$var wire 8 Q& ands [7:0] $end +$scope module andP $end +$var wire 8 R& A [7:0] $end +$var wire 8 S& B [7:0] $end +$var wire 8 T& out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 U& in [7:0] $end +$var wire 1 I& out $end +$var wire 2 V& ors [1:0] $end +$scope module or_1 $end +$var wire 4 W& in [3:0] $end +$var wire 1 X& out $end +$var wire 2 Y& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 Z& in [3:0] $end +$var wire 1 [& out $end +$var wire 2 \& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 ]& in [7:0] $end +$var wire 8 ^& sel [7:0] $end +$var wire 1 G& out $end +$var wire 8 _& ands [7:0] $end +$scope module andP $end +$var wire 8 `& A [7:0] $end +$var wire 8 a& B [7:0] $end +$var wire 8 b& out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 c& in [7:0] $end +$var wire 1 G& out $end +$var wire 2 d& ors [1:0] $end +$scope module or_1 $end +$var wire 4 e& in [3:0] $end +$var wire 1 f& out $end +$var wire 2 g& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 h& in [3:0] $end +$var wire 1 i& out $end +$var wire 2 j& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 ?& a $end +$var wire 1 @& a_ $end +$var wire 1 A& b $end +$var wire 1 B& b_ $end +$var wire 1 C& carryin $end +$var wire 1 k& eq $end +$var wire 1 l& lt $end +$var wire 1 m& out $end +$var wire 1 n& w0 $end +$upscope $end +$scope module sub $end +$var wire 1 ?& a $end +$var wire 1 B& b $end +$var wire 1 C& carryin $end +$var wire 1 o& carryout $end +$var wire 1 p& sum $end +$var wire 1 q& s1 $end +$var wire 1 r& c2 $end +$var wire 1 s& c1 $end +$scope module a1 $end +$var wire 1 ?& a $end +$var wire 1 B& b $end +$var wire 1 s& carryout $end +$var wire 1 q& sum $end +$upscope $end +$scope module a2 $end +$var wire 1 q& a $end +$var wire 1 C& b $end +$var wire 1 r& carryout $end +$var wire 1 p& sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[10] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 t& A $end +$var wire 1 u& A_ $end +$var wire 1 v& B $end +$var wire 1 w& B_ $end +$var wire 1 x& carryin $end +$var wire 8 y& command [7:0] $end +$var wire 1 z& zero $end +$var wire 8 {& results [7:0] $end +$var wire 1 |& result $end +$var wire 8 }& carryouts [7:0] $end +$var wire 1 ~& carryout $end +$scope module adder $end +$var wire 1 t& a $end +$var wire 1 v& b $end +$var wire 1 x& carryin $end +$var wire 1 !' carryout $end +$var wire 1 "' sum $end +$var wire 1 #' s1 $end +$var wire 1 $' c2 $end +$var wire 1 %' c1 $end +$scope module a1 $end +$var wire 1 t& a $end +$var wire 1 v& b $end +$var wire 1 %' carryout $end +$var wire 1 #' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 #' a $end +$var wire 1 x& b $end +$var wire 1 $' carryout $end +$var wire 1 "' sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 &' in [7:0] $end +$var wire 8 '' sel [7:0] $end +$var wire 1 ~& out $end +$var wire 8 (' ands [7:0] $end +$scope module andP $end +$var wire 8 )' A [7:0] $end +$var wire 8 *' B [7:0] $end +$var wire 8 +' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ,' in [7:0] $end +$var wire 1 ~& out $end +$var wire 2 -' ors [1:0] $end +$scope module or_1 $end +$var wire 4 .' in [3:0] $end +$var wire 1 /' out $end +$var wire 2 0' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 1' in [3:0] $end +$var wire 1 2' out $end +$var wire 2 3' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 4' in [7:0] $end +$var wire 8 5' sel [7:0] $end +$var wire 1 |& out $end +$var wire 8 6' ands [7:0] $end +$scope module andP $end +$var wire 8 7' A [7:0] $end +$var wire 8 8' B [7:0] $end +$var wire 8 9' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 :' in [7:0] $end +$var wire 1 |& out $end +$var wire 2 ;' ors [1:0] $end +$scope module or_1 $end +$var wire 4 <' in [3:0] $end +$var wire 1 =' out $end +$var wire 2 >' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ?' in [3:0] $end +$var wire 1 @' out $end +$var wire 2 A' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 t& a $end +$var wire 1 u& a_ $end +$var wire 1 v& b $end +$var wire 1 w& b_ $end +$var wire 1 x& carryin $end +$var wire 1 B' eq $end +$var wire 1 C' lt $end +$var wire 1 D' out $end +$var wire 1 E' w0 $end +$upscope $end +$scope module sub $end +$var wire 1 t& a $end +$var wire 1 w& b $end +$var wire 1 x& carryin $end +$var wire 1 F' carryout $end +$var wire 1 G' sum $end +$var wire 1 H' s1 $end +$var wire 1 I' c2 $end +$var wire 1 J' c1 $end +$scope module a1 $end +$var wire 1 t& a $end +$var wire 1 w& b $end +$var wire 1 J' carryout $end +$var wire 1 H' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 H' a $end +$var wire 1 x& b $end +$var wire 1 I' carryout $end +$var wire 1 G' sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[11] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 K' A $end +$var wire 1 L' A_ $end +$var wire 1 M' B $end +$var wire 1 N' B_ $end +$var wire 1 O' carryin $end +$var wire 8 P' command [7:0] $end +$var wire 1 Q' zero $end +$var wire 8 R' results [7:0] $end +$var wire 1 S' result $end +$var wire 8 T' carryouts [7:0] $end +$var wire 1 U' carryout $end +$scope module adder $end +$var wire 1 K' a $end +$var wire 1 M' b $end +$var wire 1 O' carryin $end +$var wire 1 V' carryout $end +$var wire 1 W' sum $end +$var wire 1 X' s1 $end +$var wire 1 Y' c2 $end +$var wire 1 Z' c1 $end +$scope module a1 $end +$var wire 1 K' a $end +$var wire 1 M' b $end +$var wire 1 Z' carryout $end +$var wire 1 X' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 X' a $end +$var wire 1 O' b $end +$var wire 1 Y' carryout $end +$var wire 1 W' sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 [' in [7:0] $end +$var wire 8 \' sel [7:0] $end +$var wire 1 U' out $end +$var wire 8 ]' ands [7:0] $end +$scope module andP $end +$var wire 8 ^' A [7:0] $end +$var wire 8 _' B [7:0] $end +$var wire 8 `' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 a' in [7:0] $end +$var wire 1 U' out $end +$var wire 2 b' ors [1:0] $end +$scope module or_1 $end +$var wire 4 c' in [3:0] $end +$var wire 1 d' out $end +$var wire 2 e' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 f' in [3:0] $end +$var wire 1 g' out $end +$var wire 2 h' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 i' in [7:0] $end +$var wire 8 j' sel [7:0] $end +$var wire 1 S' out $end +$var wire 8 k' ands [7:0] $end +$scope module andP $end +$var wire 8 l' A [7:0] $end +$var wire 8 m' B [7:0] $end +$var wire 8 n' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 o' in [7:0] $end +$var wire 1 S' out $end +$var wire 2 p' ors [1:0] $end +$scope module or_1 $end +$var wire 4 q' in [3:0] $end +$var wire 1 r' out $end +$var wire 2 s' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 t' in [3:0] $end +$var wire 1 u' out $end +$var wire 2 v' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 K' a $end +$var wire 1 L' a_ $end +$var wire 1 M' b $end +$var wire 1 N' b_ $end +$var wire 1 O' carryin $end +$var wire 1 w' eq $end +$var wire 1 x' lt $end +$var wire 1 y' out $end +$var wire 1 z' w0 $end +$upscope $end +$scope module sub $end +$var wire 1 K' a $end +$var wire 1 N' b $end +$var wire 1 O' carryin $end +$var wire 1 {' carryout $end +$var wire 1 |' sum $end +$var wire 1 }' s1 $end +$var wire 1 ~' c2 $end +$var wire 1 !( c1 $end +$scope module a1 $end +$var wire 1 K' a $end +$var wire 1 N' b $end +$var wire 1 !( carryout $end +$var wire 1 }' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 }' a $end +$var wire 1 O' b $end +$var wire 1 ~' carryout $end +$var wire 1 |' sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[12] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 "( A $end +$var wire 1 #( A_ $end +$var wire 1 $( B $end +$var wire 1 %( B_ $end +$var wire 1 &( carryin $end +$var wire 8 '( command [7:0] $end +$var wire 1 (( zero $end +$var wire 8 )( results [7:0] $end +$var wire 1 *( result $end +$var wire 8 +( carryouts [7:0] $end +$var wire 1 ,( carryout $end +$scope module adder $end +$var wire 1 "( a $end +$var wire 1 $( b $end +$var wire 1 &( carryin $end +$var wire 1 -( carryout $end +$var wire 1 .( sum $end +$var wire 1 /( s1 $end +$var wire 1 0( c2 $end +$var wire 1 1( c1 $end +$scope module a1 $end +$var wire 1 "( a $end +$var wire 1 $( b $end +$var wire 1 1( carryout $end +$var wire 1 /( sum $end +$upscope $end +$scope module a2 $end +$var wire 1 /( a $end +$var wire 1 &( b $end +$var wire 1 0( carryout $end +$var wire 1 .( sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 2( in [7:0] $end +$var wire 8 3( sel [7:0] $end +$var wire 1 ,( out $end +$var wire 8 4( ands [7:0] $end +$scope module andP $end +$var wire 8 5( A [7:0] $end +$var wire 8 6( B [7:0] $end +$var wire 8 7( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 8( in [7:0] $end +$var wire 1 ,( out $end +$var wire 2 9( ors [1:0] $end +$scope module or_1 $end +$var wire 4 :( in [3:0] $end +$var wire 1 ;( out $end +$var wire 2 <( ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 =( in [3:0] $end +$var wire 1 >( out $end +$var wire 2 ?( ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 @( in [7:0] $end +$var wire 8 A( sel [7:0] $end +$var wire 1 *( out $end +$var wire 8 B( ands [7:0] $end +$scope module andP $end +$var wire 8 C( A [7:0] $end +$var wire 8 D( B [7:0] $end +$var wire 8 E( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 F( in [7:0] $end +$var wire 1 *( out $end +$var wire 2 G( ors [1:0] $end +$scope module or_1 $end +$var wire 4 H( in [3:0] $end +$var wire 1 I( out $end +$var wire 2 J( ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 K( in [3:0] $end +$var wire 1 L( out $end +$var wire 2 M( ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 "( a $end +$var wire 1 #( a_ $end +$var wire 1 $( b $end +$var wire 1 %( b_ $end +$var wire 1 &( carryin $end +$var wire 1 N( eq $end +$var wire 1 O( lt $end +$var wire 1 P( out $end +$var wire 1 Q( w0 $end +$upscope $end +$scope module sub $end +$var wire 1 "( a $end +$var wire 1 %( b $end +$var wire 1 &( carryin $end +$var wire 1 R( carryout $end +$var wire 1 S( sum $end +$var wire 1 T( s1 $end +$var wire 1 U( c2 $end +$var wire 1 V( c1 $end +$scope module a1 $end +$var wire 1 "( a $end +$var wire 1 %( b $end +$var wire 1 V( carryout $end +$var wire 1 T( sum $end +$upscope $end +$scope module a2 $end +$var wire 1 T( a $end +$var wire 1 &( b $end +$var wire 1 U( carryout $end +$var wire 1 S( sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[13] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 W( A $end +$var wire 1 X( A_ $end +$var wire 1 Y( B $end +$var wire 1 Z( B_ $end +$var wire 1 [( carryin $end +$var wire 8 \( command [7:0] $end +$var wire 1 ]( zero $end +$var wire 8 ^( results [7:0] $end +$var wire 1 _( result $end +$var wire 8 `( carryouts [7:0] $end +$var wire 1 a( carryout $end +$scope module adder $end +$var wire 1 W( a $end +$var wire 1 Y( b $end +$var wire 1 [( carryin $end +$var wire 1 b( carryout $end +$var wire 1 c( sum $end +$var wire 1 d( s1 $end +$var wire 1 e( c2 $end +$var wire 1 f( c1 $end +$scope module a1 $end +$var wire 1 W( a $end +$var wire 1 Y( b $end +$var wire 1 f( carryout $end +$var wire 1 d( sum $end +$upscope $end +$scope module a2 $end +$var wire 1 d( a $end +$var wire 1 [( b $end +$var wire 1 e( carryout $end +$var wire 1 c( sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 g( in [7:0] $end +$var wire 8 h( sel [7:0] $end +$var wire 1 a( out $end +$var wire 8 i( ands [7:0] $end +$scope module andP $end +$var wire 8 j( A [7:0] $end +$var wire 8 k( B [7:0] $end +$var wire 8 l( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 m( in [7:0] $end +$var wire 1 a( out $end +$var wire 2 n( ors [1:0] $end +$scope module or_1 $end +$var wire 4 o( in [3:0] $end +$var wire 1 p( out $end +$var wire 2 q( ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 r( in [3:0] $end +$var wire 1 s( out $end +$var wire 2 t( ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 u( in [7:0] $end +$var wire 8 v( sel [7:0] $end +$var wire 1 _( out $end +$var wire 8 w( ands [7:0] $end +$scope module andP $end +$var wire 8 x( A [7:0] $end +$var wire 8 y( B [7:0] $end +$var wire 8 z( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 {( in [7:0] $end +$var wire 1 _( out $end +$var wire 2 |( ors [1:0] $end +$scope module or_1 $end +$var wire 4 }( in [3:0] $end +$var wire 1 ~( out $end +$var wire 2 !) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ") in [3:0] $end +$var wire 1 #) out $end +$var wire 2 $) ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 W( a $end +$var wire 1 X( a_ $end +$var wire 1 Y( b $end +$var wire 1 Z( b_ $end +$var wire 1 [( carryin $end +$var wire 1 %) eq $end +$var wire 1 &) lt $end +$var wire 1 ') out $end +$var wire 1 () w0 $end +$upscope $end +$scope module sub $end +$var wire 1 W( a $end +$var wire 1 Z( b $end +$var wire 1 [( carryin $end +$var wire 1 )) carryout $end +$var wire 1 *) sum $end +$var wire 1 +) s1 $end +$var wire 1 ,) c2 $end +$var wire 1 -) c1 $end +$scope module a1 $end +$var wire 1 W( a $end +$var wire 1 Z( b $end +$var wire 1 -) carryout $end +$var wire 1 +) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 +) a $end +$var wire 1 [( b $end +$var wire 1 ,) carryout $end +$var wire 1 *) sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[14] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 .) A $end +$var wire 1 /) A_ $end +$var wire 1 0) B $end +$var wire 1 1) B_ $end +$var wire 1 2) carryin $end +$var wire 8 3) command [7:0] $end +$var wire 1 4) zero $end +$var wire 8 5) results [7:0] $end +$var wire 1 6) result $end +$var wire 8 7) carryouts [7:0] $end +$var wire 1 8) carryout $end +$scope module adder $end +$var wire 1 .) a $end +$var wire 1 0) b $end +$var wire 1 2) carryin $end +$var wire 1 9) carryout $end +$var wire 1 :) sum $end +$var wire 1 ;) s1 $end +$var wire 1 <) c2 $end +$var wire 1 =) c1 $end +$scope module a1 $end +$var wire 1 .) a $end +$var wire 1 0) b $end +$var wire 1 =) carryout $end +$var wire 1 ;) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 ;) a $end +$var wire 1 2) b $end +$var wire 1 <) carryout $end +$var wire 1 :) sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 >) in [7:0] $end +$var wire 8 ?) sel [7:0] $end +$var wire 1 8) out $end +$var wire 8 @) ands [7:0] $end +$scope module andP $end +$var wire 8 A) A [7:0] $end +$var wire 8 B) B [7:0] $end +$var wire 8 C) out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 D) in [7:0] $end +$var wire 1 8) out $end +$var wire 2 E) ors [1:0] $end +$scope module or_1 $end +$var wire 4 F) in [3:0] $end +$var wire 1 G) out $end +$var wire 2 H) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 I) in [3:0] $end +$var wire 1 J) out $end +$var wire 2 K) ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 L) in [7:0] $end +$var wire 8 M) sel [7:0] $end +$var wire 1 6) out $end +$var wire 8 N) ands [7:0] $end +$scope module andP $end +$var wire 8 O) A [7:0] $end +$var wire 8 P) B [7:0] $end +$var wire 8 Q) out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 R) in [7:0] $end +$var wire 1 6) out $end +$var wire 2 S) ors [1:0] $end +$scope module or_1 $end +$var wire 4 T) in [3:0] $end +$var wire 1 U) out $end +$var wire 2 V) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 W) in [3:0] $end +$var wire 1 X) out $end +$var wire 2 Y) ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 .) a $end +$var wire 1 /) a_ $end +$var wire 1 0) b $end +$var wire 1 1) b_ $end +$var wire 1 2) carryin $end +$var wire 1 Z) eq $end +$var wire 1 [) lt $end +$var wire 1 \) out $end +$var wire 1 ]) w0 $end +$upscope $end +$scope module sub $end +$var wire 1 .) a $end +$var wire 1 1) b $end +$var wire 1 2) carryin $end +$var wire 1 ^) carryout $end +$var wire 1 _) sum $end +$var wire 1 `) s1 $end +$var wire 1 a) c2 $end +$var wire 1 b) c1 $end +$scope module a1 $end +$var wire 1 .) a $end +$var wire 1 1) b $end +$var wire 1 b) carryout $end +$var wire 1 `) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 `) a $end +$var wire 1 2) b $end +$var wire 1 a) carryout $end +$var wire 1 _) sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[15] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 c) A $end +$var wire 1 d) A_ $end +$var wire 1 e) B $end +$var wire 1 f) B_ $end +$var wire 1 g) carryin $end +$var wire 8 h) command [7:0] $end +$var wire 1 i) zero $end +$var wire 8 j) results [7:0] $end +$var wire 1 k) result $end +$var wire 8 l) carryouts [7:0] $end +$var wire 1 m) carryout $end +$scope module adder $end +$var wire 1 c) a $end +$var wire 1 e) b $end +$var wire 1 g) carryin $end +$var wire 1 n) carryout $end +$var wire 1 o) sum $end +$var wire 1 p) s1 $end +$var wire 1 q) c2 $end +$var wire 1 r) c1 $end +$scope module a1 $end +$var wire 1 c) a $end +$var wire 1 e) b $end +$var wire 1 r) carryout $end +$var wire 1 p) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 p) a $end +$var wire 1 g) b $end +$var wire 1 q) carryout $end +$var wire 1 o) sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 s) in [7:0] $end +$var wire 8 t) sel [7:0] $end +$var wire 1 m) out $end +$var wire 8 u) ands [7:0] $end +$scope module andP $end +$var wire 8 v) A [7:0] $end +$var wire 8 w) B [7:0] $end +$var wire 8 x) out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 y) in [7:0] $end +$var wire 1 m) out $end +$var wire 2 z) ors [1:0] $end +$scope module or_1 $end +$var wire 4 {) in [3:0] $end +$var wire 1 |) out $end +$var wire 2 }) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ~) in [3:0] $end +$var wire 1 !* out $end +$var wire 2 "* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 #* in [7:0] $end +$var wire 8 $* sel [7:0] $end +$var wire 1 k) out $end +$var wire 8 %* ands [7:0] $end +$scope module andP $end +$var wire 8 &* A [7:0] $end +$var wire 8 '* B [7:0] $end +$var wire 8 (* out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 )* in [7:0] $end +$var wire 1 k) out $end +$var wire 2 ** ors [1:0] $end +$scope module or_1 $end +$var wire 4 +* in [3:0] $end +$var wire 1 ,* out $end +$var wire 2 -* ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 .* in [3:0] $end +$var wire 1 /* out $end +$var wire 2 0* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 c) a $end +$var wire 1 d) a_ $end +$var wire 1 e) b $end +$var wire 1 f) b_ $end +$var wire 1 g) carryin $end +$var wire 1 1* eq $end +$var wire 1 2* lt $end +$var wire 1 3* out $end +$var wire 1 4* w0 $end +$upscope $end +$scope module sub $end +$var wire 1 c) a $end +$var wire 1 f) b $end +$var wire 1 g) carryin $end +$var wire 1 5* carryout $end +$var wire 1 6* sum $end +$var wire 1 7* s1 $end +$var wire 1 8* c2 $end +$var wire 1 9* c1 $end +$scope module a1 $end +$var wire 1 c) a $end +$var wire 1 f) b $end +$var wire 1 9* carryout $end +$var wire 1 7* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 7* a $end +$var wire 1 g) b $end +$var wire 1 8* carryout $end +$var wire 1 6* sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[16] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 :* A $end +$var wire 1 ;* A_ $end +$var wire 1 <* B $end +$var wire 1 =* B_ $end +$var wire 1 >* carryin $end +$var wire 8 ?* command [7:0] $end +$var wire 1 @* zero $end +$var wire 8 A* results [7:0] $end +$var wire 1 B* result $end +$var wire 8 C* carryouts [7:0] $end +$var wire 1 D* carryout $end +$scope module adder $end +$var wire 1 :* a $end +$var wire 1 <* b $end +$var wire 1 >* carryin $end +$var wire 1 E* carryout $end +$var wire 1 F* sum $end +$var wire 1 G* s1 $end +$var wire 1 H* c2 $end +$var wire 1 I* c1 $end +$scope module a1 $end +$var wire 1 :* a $end +$var wire 1 <* b $end +$var wire 1 I* carryout $end +$var wire 1 G* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 G* a $end +$var wire 1 >* b $end +$var wire 1 H* carryout $end +$var wire 1 F* sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 J* in [7:0] $end +$var wire 8 K* sel [7:0] $end +$var wire 1 D* out $end +$var wire 8 L* ands [7:0] $end +$scope module andP $end +$var wire 8 M* A [7:0] $end +$var wire 8 N* B [7:0] $end +$var wire 8 O* out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 P* in [7:0] $end +$var wire 1 D* out $end +$var wire 2 Q* ors [1:0] $end +$scope module or_1 $end +$var wire 4 R* in [3:0] $end +$var wire 1 S* out $end +$var wire 2 T* ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 U* in [3:0] $end +$var wire 1 V* out $end +$var wire 2 W* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 X* in [7:0] $end +$var wire 8 Y* sel [7:0] $end +$var wire 1 B* out $end +$var wire 8 Z* ands [7:0] $end +$scope module andP $end +$var wire 8 [* A [7:0] $end +$var wire 8 \* B [7:0] $end +$var wire 8 ]* out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ^* in [7:0] $end +$var wire 1 B* out $end +$var wire 2 _* ors [1:0] $end +$scope module or_1 $end +$var wire 4 `* in [3:0] $end +$var wire 1 a* out $end +$var wire 2 b* ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 c* in [3:0] $end +$var wire 1 d* out $end +$var wire 2 e* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 :* a $end +$var wire 1 ;* a_ $end +$var wire 1 <* b $end +$var wire 1 =* b_ $end +$var wire 1 >* carryin $end +$var wire 1 f* eq $end +$var wire 1 g* lt $end +$var wire 1 h* out $end +$var wire 1 i* w0 $end +$upscope $end +$scope module sub $end +$var wire 1 :* a $end +$var wire 1 =* b $end +$var wire 1 >* carryin $end +$var wire 1 j* carryout $end +$var wire 1 k* sum $end +$var wire 1 l* s1 $end +$var wire 1 m* c2 $end +$var wire 1 n* c1 $end +$scope module a1 $end +$var wire 1 :* a $end +$var wire 1 =* b $end +$var wire 1 n* carryout $end +$var wire 1 l* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 l* a $end +$var wire 1 >* b $end +$var wire 1 m* carryout $end +$var wire 1 k* sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[17] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 o* A $end +$var wire 1 p* A_ $end +$var wire 1 q* B $end +$var wire 1 r* B_ $end +$var wire 1 s* carryin $end +$var wire 8 t* command [7:0] $end +$var wire 1 u* zero $end +$var wire 8 v* results [7:0] $end +$var wire 1 w* result $end +$var wire 8 x* carryouts [7:0] $end +$var wire 1 y* carryout $end +$scope module adder $end +$var wire 1 o* a $end +$var wire 1 q* b $end +$var wire 1 s* carryin $end +$var wire 1 z* carryout $end +$var wire 1 {* sum $end +$var wire 1 |* s1 $end +$var wire 1 }* c2 $end +$var wire 1 ~* c1 $end +$scope module a1 $end +$var wire 1 o* a $end +$var wire 1 q* b $end +$var wire 1 ~* carryout $end +$var wire 1 |* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 |* a $end +$var wire 1 s* b $end +$var wire 1 }* carryout $end +$var wire 1 {* sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 !+ in [7:0] $end +$var wire 8 "+ sel [7:0] $end +$var wire 1 y* out $end +$var wire 8 #+ ands [7:0] $end +$scope module andP $end +$var wire 8 $+ A [7:0] $end +$var wire 8 %+ B [7:0] $end +$var wire 8 &+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 '+ in [7:0] $end +$var wire 1 y* out $end +$var wire 2 (+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 )+ in [3:0] $end +$var wire 1 *+ out $end +$var wire 2 ++ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ,+ in [3:0] $end +$var wire 1 -+ out $end +$var wire 2 .+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 /+ in [7:0] $end +$var wire 8 0+ sel [7:0] $end +$var wire 1 w* out $end +$var wire 8 1+ ands [7:0] $end +$scope module andP $end +$var wire 8 2+ A [7:0] $end +$var wire 8 3+ B [7:0] $end +$var wire 8 4+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 5+ in [7:0] $end +$var wire 1 w* out $end +$var wire 2 6+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 7+ in [3:0] $end +$var wire 1 8+ out $end +$var wire 2 9+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 :+ in [3:0] $end +$var wire 1 ;+ out $end +$var wire 2 <+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 o* a $end +$var wire 1 p* a_ $end +$var wire 1 q* b $end +$var wire 1 r* b_ $end +$var wire 1 s* carryin $end +$var wire 1 =+ eq $end +$var wire 1 >+ lt $end +$var wire 1 ?+ out $end +$var wire 1 @+ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 o* a $end +$var wire 1 r* b $end +$var wire 1 s* carryin $end +$var wire 1 A+ carryout $end +$var wire 1 B+ sum $end +$var wire 1 C+ s1 $end +$var wire 1 D+ c2 $end +$var wire 1 E+ c1 $end +$scope module a1 $end +$var wire 1 o* a $end +$var wire 1 r* b $end +$var wire 1 E+ carryout $end +$var wire 1 C+ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 C+ a $end +$var wire 1 s* b $end +$var wire 1 D+ carryout $end +$var wire 1 B+ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[18] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 F+ A $end +$var wire 1 G+ A_ $end +$var wire 1 H+ B $end +$var wire 1 I+ B_ $end +$var wire 1 J+ carryin $end +$var wire 8 K+ command [7:0] $end +$var wire 1 L+ zero $end +$var wire 8 M+ results [7:0] $end +$var wire 1 N+ result $end +$var wire 8 O+ carryouts [7:0] $end +$var wire 1 P+ carryout $end +$scope module adder $end +$var wire 1 F+ a $end +$var wire 1 H+ b $end +$var wire 1 J+ carryin $end +$var wire 1 Q+ carryout $end +$var wire 1 R+ sum $end +$var wire 1 S+ s1 $end +$var wire 1 T+ c2 $end +$var wire 1 U+ c1 $end +$scope module a1 $end +$var wire 1 F+ a $end +$var wire 1 H+ b $end +$var wire 1 U+ carryout $end +$var wire 1 S+ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 S+ a $end +$var wire 1 J+ b $end +$var wire 1 T+ carryout $end +$var wire 1 R+ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 V+ in [7:0] $end +$var wire 8 W+ sel [7:0] $end +$var wire 1 P+ out $end +$var wire 8 X+ ands [7:0] $end +$scope module andP $end +$var wire 8 Y+ A [7:0] $end +$var wire 8 Z+ B [7:0] $end +$var wire 8 [+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 \+ in [7:0] $end +$var wire 1 P+ out $end +$var wire 2 ]+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 ^+ in [3:0] $end +$var wire 1 _+ out $end +$var wire 2 `+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 a+ in [3:0] $end +$var wire 1 b+ out $end +$var wire 2 c+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 d+ in [7:0] $end +$var wire 8 e+ sel [7:0] $end +$var wire 1 N+ out $end +$var wire 8 f+ ands [7:0] $end +$scope module andP $end +$var wire 8 g+ A [7:0] $end +$var wire 8 h+ B [7:0] $end +$var wire 8 i+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 j+ in [7:0] $end +$var wire 1 N+ out $end +$var wire 2 k+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 l+ in [3:0] $end +$var wire 1 m+ out $end +$var wire 2 n+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 o+ in [3:0] $end +$var wire 1 p+ out $end +$var wire 2 q+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 F+ a $end +$var wire 1 G+ a_ $end +$var wire 1 H+ b $end +$var wire 1 I+ b_ $end +$var wire 1 J+ carryin $end +$var wire 1 r+ eq $end +$var wire 1 s+ lt $end +$var wire 1 t+ out $end +$var wire 1 u+ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 F+ a $end +$var wire 1 I+ b $end +$var wire 1 J+ carryin $end +$var wire 1 v+ carryout $end +$var wire 1 w+ sum $end +$var wire 1 x+ s1 $end +$var wire 1 y+ c2 $end +$var wire 1 z+ c1 $end +$scope module a1 $end +$var wire 1 F+ a $end +$var wire 1 I+ b $end +$var wire 1 z+ carryout $end +$var wire 1 x+ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 x+ a $end +$var wire 1 J+ b $end +$var wire 1 y+ carryout $end +$var wire 1 w+ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[19] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 {+ A $end +$var wire 1 |+ A_ $end +$var wire 1 }+ B $end +$var wire 1 ~+ B_ $end +$var wire 1 !, carryin $end +$var wire 8 ", command [7:0] $end +$var wire 1 #, zero $end +$var wire 8 $, results [7:0] $end +$var wire 1 %, result $end +$var wire 8 &, carryouts [7:0] $end +$var wire 1 ', carryout $end +$scope module adder $end +$var wire 1 {+ a $end +$var wire 1 }+ b $end +$var wire 1 !, carryin $end +$var wire 1 (, carryout $end +$var wire 1 ), sum $end +$var wire 1 *, s1 $end +$var wire 1 +, c2 $end +$var wire 1 ,, c1 $end +$scope module a1 $end +$var wire 1 {+ a $end +$var wire 1 }+ b $end +$var wire 1 ,, carryout $end +$var wire 1 *, sum $end +$upscope $end +$scope module a2 $end +$var wire 1 *, a $end +$var wire 1 !, b $end +$var wire 1 +, carryout $end +$var wire 1 ), sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 -, in [7:0] $end +$var wire 8 ., sel [7:0] $end +$var wire 1 ', out $end +$var wire 8 /, ands [7:0] $end +$scope module andP $end +$var wire 8 0, A [7:0] $end +$var wire 8 1, B [7:0] $end +$var wire 8 2, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 3, in [7:0] $end +$var wire 1 ', out $end +$var wire 2 4, ors [1:0] $end +$scope module or_1 $end +$var wire 4 5, in [3:0] $end +$var wire 1 6, out $end +$var wire 2 7, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 8, in [3:0] $end +$var wire 1 9, out $end +$var wire 2 :, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 ;, in [7:0] $end +$var wire 8 <, sel [7:0] $end +$var wire 1 %, out $end +$var wire 8 =, ands [7:0] $end +$scope module andP $end +$var wire 8 >, A [7:0] $end +$var wire 8 ?, B [7:0] $end +$var wire 8 @, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 A, in [7:0] $end +$var wire 1 %, out $end +$var wire 2 B, ors [1:0] $end +$scope module or_1 $end +$var wire 4 C, in [3:0] $end +$var wire 1 D, out $end +$var wire 2 E, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 F, in [3:0] $end +$var wire 1 G, out $end +$var wire 2 H, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 {+ a $end +$var wire 1 |+ a_ $end +$var wire 1 }+ b $end +$var wire 1 ~+ b_ $end +$var wire 1 !, carryin $end +$var wire 1 I, eq $end +$var wire 1 J, lt $end +$var wire 1 K, out $end +$var wire 1 L, w0 $end +$upscope $end +$scope module sub $end +$var wire 1 {+ a $end +$var wire 1 ~+ b $end +$var wire 1 !, carryin $end +$var wire 1 M, carryout $end +$var wire 1 N, sum $end +$var wire 1 O, s1 $end +$var wire 1 P, c2 $end +$var wire 1 Q, c1 $end +$scope module a1 $end +$var wire 1 {+ a $end +$var wire 1 ~+ b $end +$var wire 1 Q, carryout $end +$var wire 1 O, sum $end +$upscope $end +$scope module a2 $end +$var wire 1 O, a $end +$var wire 1 !, b $end +$var wire 1 P, carryout $end +$var wire 1 N, sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[20] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 R, A $end +$var wire 1 S, A_ $end +$var wire 1 T, B $end +$var wire 1 U, B_ $end +$var wire 1 V, carryin $end +$var wire 8 W, command [7:0] $end +$var wire 1 X, zero $end +$var wire 8 Y, results [7:0] $end +$var wire 1 Z, result $end +$var wire 8 [, carryouts [7:0] $end +$var wire 1 \, carryout $end +$scope module adder $end +$var wire 1 R, a $end +$var wire 1 T, b $end +$var wire 1 V, carryin $end +$var wire 1 ], carryout $end +$var wire 1 ^, sum $end +$var wire 1 _, s1 $end +$var wire 1 `, c2 $end +$var wire 1 a, c1 $end +$scope module a1 $end +$var wire 1 R, a $end +$var wire 1 T, b $end +$var wire 1 a, carryout $end +$var wire 1 _, sum $end +$upscope $end +$scope module a2 $end +$var wire 1 _, a $end +$var wire 1 V, b $end +$var wire 1 `, carryout $end +$var wire 1 ^, sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 b, in [7:0] $end +$var wire 8 c, sel [7:0] $end +$var wire 1 \, out $end +$var wire 8 d, ands [7:0] $end +$scope module andP $end +$var wire 8 e, A [7:0] $end +$var wire 8 f, B [7:0] $end +$var wire 8 g, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 h, in [7:0] $end +$var wire 1 \, out $end +$var wire 2 i, ors [1:0] $end +$scope module or_1 $end +$var wire 4 j, in [3:0] $end +$var wire 1 k, out $end +$var wire 2 l, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 m, in [3:0] $end +$var wire 1 n, out $end +$var wire 2 o, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 p, in [7:0] $end +$var wire 8 q, sel [7:0] $end +$var wire 1 Z, out $end +$var wire 8 r, ands [7:0] $end +$scope module andP $end +$var wire 8 s, A [7:0] $end +$var wire 8 t, B [7:0] $end +$var wire 8 u, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 v, in [7:0] $end +$var wire 1 Z, out $end +$var wire 2 w, ors [1:0] $end +$scope module or_1 $end +$var wire 4 x, in [3:0] $end +$var wire 1 y, out $end +$var wire 2 z, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 {, in [3:0] $end +$var wire 1 |, out $end +$var wire 2 }, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 R, a $end +$var wire 1 S, a_ $end +$var wire 1 T, b $end +$var wire 1 U, b_ $end +$var wire 1 V, carryin $end +$var wire 1 ~, eq $end +$var wire 1 !- lt $end +$var wire 1 "- out $end +$var wire 1 #- w0 $end +$upscope $end +$scope module sub $end +$var wire 1 R, a $end +$var wire 1 U, b $end +$var wire 1 V, carryin $end +$var wire 1 $- carryout $end +$var wire 1 %- sum $end +$var wire 1 &- s1 $end +$var wire 1 '- c2 $end +$var wire 1 (- c1 $end +$scope module a1 $end +$var wire 1 R, a $end +$var wire 1 U, b $end +$var wire 1 (- carryout $end +$var wire 1 &- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 &- a $end +$var wire 1 V, b $end +$var wire 1 '- carryout $end +$var wire 1 %- sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[21] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 )- A $end +$var wire 1 *- A_ $end +$var wire 1 +- B $end +$var wire 1 ,- B_ $end +$var wire 1 -- carryin $end +$var wire 8 .- command [7:0] $end +$var wire 1 /- zero $end +$var wire 8 0- results [7:0] $end +$var wire 1 1- result $end +$var wire 8 2- carryouts [7:0] $end +$var wire 1 3- carryout $end +$scope module adder $end +$var wire 1 )- a $end +$var wire 1 +- b $end +$var wire 1 -- carryin $end +$var wire 1 4- carryout $end +$var wire 1 5- sum $end +$var wire 1 6- s1 $end +$var wire 1 7- c2 $end +$var wire 1 8- c1 $end +$scope module a1 $end +$var wire 1 )- a $end +$var wire 1 +- b $end +$var wire 1 8- carryout $end +$var wire 1 6- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 6- a $end +$var wire 1 -- b $end +$var wire 1 7- carryout $end +$var wire 1 5- sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 9- in [7:0] $end +$var wire 8 :- sel [7:0] $end +$var wire 1 3- out $end +$var wire 8 ;- ands [7:0] $end +$scope module andP $end +$var wire 8 <- A [7:0] $end +$var wire 8 =- B [7:0] $end +$var wire 8 >- out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ?- in [7:0] $end +$var wire 1 3- out $end +$var wire 2 @- ors [1:0] $end +$scope module or_1 $end +$var wire 4 A- in [3:0] $end +$var wire 1 B- out $end +$var wire 2 C- ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 D- in [3:0] $end +$var wire 1 E- out $end +$var wire 2 F- ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 G- in [7:0] $end +$var wire 8 H- sel [7:0] $end +$var wire 1 1- out $end +$var wire 8 I- ands [7:0] $end +$scope module andP $end +$var wire 8 J- A [7:0] $end +$var wire 8 K- B [7:0] $end +$var wire 8 L- out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 M- in [7:0] $end +$var wire 1 1- out $end +$var wire 2 N- ors [1:0] $end +$scope module or_1 $end +$var wire 4 O- in [3:0] $end +$var wire 1 P- out $end +$var wire 2 Q- ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 R- in [3:0] $end +$var wire 1 S- out $end +$var wire 2 T- ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 )- a $end +$var wire 1 *- a_ $end +$var wire 1 +- b $end +$var wire 1 ,- b_ $end +$var wire 1 -- carryin $end +$var wire 1 U- eq $end +$var wire 1 V- lt $end +$var wire 1 W- out $end +$var wire 1 X- w0 $end +$upscope $end +$scope module sub $end +$var wire 1 )- a $end +$var wire 1 ,- b $end +$var wire 1 -- carryin $end +$var wire 1 Y- carryout $end +$var wire 1 Z- sum $end +$var wire 1 [- s1 $end +$var wire 1 \- c2 $end +$var wire 1 ]- c1 $end +$scope module a1 $end +$var wire 1 )- a $end +$var wire 1 ,- b $end +$var wire 1 ]- carryout $end +$var wire 1 [- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 [- a $end +$var wire 1 -- b $end +$var wire 1 \- carryout $end +$var wire 1 Z- sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[22] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 ^- A $end +$var wire 1 _- A_ $end +$var wire 1 `- B $end +$var wire 1 a- B_ $end +$var wire 1 b- carryin $end +$var wire 8 c- command [7:0] $end +$var wire 1 d- zero $end +$var wire 8 e- results [7:0] $end +$var wire 1 f- result $end +$var wire 8 g- carryouts [7:0] $end +$var wire 1 h- carryout $end +$scope module adder $end +$var wire 1 ^- a $end +$var wire 1 `- b $end +$var wire 1 b- carryin $end +$var wire 1 i- carryout $end +$var wire 1 j- sum $end +$var wire 1 k- s1 $end +$var wire 1 l- c2 $end +$var wire 1 m- c1 $end +$scope module a1 $end +$var wire 1 ^- a $end +$var wire 1 `- b $end +$var wire 1 m- carryout $end +$var wire 1 k- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 k- a $end +$var wire 1 b- b $end +$var wire 1 l- carryout $end +$var wire 1 j- sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 n- in [7:0] $end +$var wire 8 o- sel [7:0] $end +$var wire 1 h- out $end +$var wire 8 p- ands [7:0] $end +$scope module andP $end +$var wire 8 q- A [7:0] $end +$var wire 8 r- B [7:0] $end +$var wire 8 s- out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 t- in [7:0] $end +$var wire 1 h- out $end +$var wire 2 u- ors [1:0] $end +$scope module or_1 $end +$var wire 4 v- in [3:0] $end +$var wire 1 w- out $end +$var wire 2 x- ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 y- in [3:0] $end +$var wire 1 z- out $end +$var wire 2 {- ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 |- in [7:0] $end +$var wire 8 }- sel [7:0] $end +$var wire 1 f- out $end +$var wire 8 ~- ands [7:0] $end +$scope module andP $end +$var wire 8 !. A [7:0] $end +$var wire 8 ". B [7:0] $end +$var wire 8 #. out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 $. in [7:0] $end +$var wire 1 f- out $end +$var wire 2 %. ors [1:0] $end +$scope module or_1 $end +$var wire 4 &. in [3:0] $end +$var wire 1 '. out $end +$var wire 2 (. ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ). in [3:0] $end +$var wire 1 *. out $end +$var wire 2 +. ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 ^- a $end +$var wire 1 _- a_ $end +$var wire 1 `- b $end +$var wire 1 a- b_ $end +$var wire 1 b- carryin $end +$var wire 1 ,. eq $end +$var wire 1 -. lt $end +$var wire 1 .. out $end +$var wire 1 /. w0 $end +$upscope $end +$scope module sub $end +$var wire 1 ^- a $end +$var wire 1 a- b $end +$var wire 1 b- carryin $end +$var wire 1 0. carryout $end +$var wire 1 1. sum $end +$var wire 1 2. s1 $end +$var wire 1 3. c2 $end +$var wire 1 4. c1 $end +$scope module a1 $end +$var wire 1 ^- a $end +$var wire 1 a- b $end +$var wire 1 4. carryout $end +$var wire 1 2. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 2. a $end +$var wire 1 b- b $end +$var wire 1 3. carryout $end +$var wire 1 1. sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[23] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 5. A $end +$var wire 1 6. A_ $end +$var wire 1 7. B $end +$var wire 1 8. B_ $end +$var wire 1 9. carryin $end +$var wire 8 :. command [7:0] $end +$var wire 1 ;. zero $end +$var wire 8 <. results [7:0] $end +$var wire 1 =. result $end +$var wire 8 >. carryouts [7:0] $end +$var wire 1 ?. carryout $end +$scope module adder $end +$var wire 1 5. a $end +$var wire 1 7. b $end +$var wire 1 9. carryin $end +$var wire 1 @. carryout $end +$var wire 1 A. sum $end +$var wire 1 B. s1 $end +$var wire 1 C. c2 $end +$var wire 1 D. c1 $end +$scope module a1 $end +$var wire 1 5. a $end +$var wire 1 7. b $end +$var wire 1 D. carryout $end +$var wire 1 B. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 B. a $end +$var wire 1 9. b $end +$var wire 1 C. carryout $end +$var wire 1 A. sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 E. in [7:0] $end +$var wire 8 F. sel [7:0] $end +$var wire 1 ?. out $end +$var wire 8 G. ands [7:0] $end +$scope module andP $end +$var wire 8 H. A [7:0] $end +$var wire 8 I. B [7:0] $end +$var wire 8 J. out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 K. in [7:0] $end +$var wire 1 ?. out $end +$var wire 2 L. ors [1:0] $end +$scope module or_1 $end +$var wire 4 M. in [3:0] $end +$var wire 1 N. out $end +$var wire 2 O. ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 P. in [3:0] $end +$var wire 1 Q. out $end +$var wire 2 R. ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 S. in [7:0] $end +$var wire 8 T. sel [7:0] $end +$var wire 1 =. out $end +$var wire 8 U. ands [7:0] $end +$scope module andP $end +$var wire 8 V. A [7:0] $end +$var wire 8 W. B [7:0] $end +$var wire 8 X. out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 Y. in [7:0] $end +$var wire 1 =. out $end +$var wire 2 Z. ors [1:0] $end +$scope module or_1 $end +$var wire 4 [. in [3:0] $end +$var wire 1 \. out $end +$var wire 2 ]. ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ^. in [3:0] $end +$var wire 1 _. out $end +$var wire 2 `. ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 5. a $end +$var wire 1 6. a_ $end +$var wire 1 7. b $end +$var wire 1 8. b_ $end +$var wire 1 9. carryin $end +$var wire 1 a. eq $end +$var wire 1 b. lt $end +$var wire 1 c. out $end +$var wire 1 d. w0 $end +$upscope $end +$scope module sub $end +$var wire 1 5. a $end +$var wire 1 8. b $end +$var wire 1 9. carryin $end +$var wire 1 e. carryout $end +$var wire 1 f. sum $end +$var wire 1 g. s1 $end +$var wire 1 h. c2 $end +$var wire 1 i. c1 $end +$scope module a1 $end +$var wire 1 5. a $end +$var wire 1 8. b $end +$var wire 1 i. carryout $end +$var wire 1 g. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 g. a $end +$var wire 1 9. b $end +$var wire 1 h. carryout $end +$var wire 1 f. sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[24] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 j. A $end +$var wire 1 k. A_ $end +$var wire 1 l. B $end +$var wire 1 m. B_ $end +$var wire 1 n. carryin $end +$var wire 8 o. command [7:0] $end +$var wire 1 p. zero $end +$var wire 8 q. results [7:0] $end +$var wire 1 r. result $end +$var wire 8 s. carryouts [7:0] $end +$var wire 1 t. carryout $end +$scope module adder $end +$var wire 1 j. a $end +$var wire 1 l. b $end +$var wire 1 n. carryin $end +$var wire 1 u. carryout $end +$var wire 1 v. sum $end +$var wire 1 w. s1 $end +$var wire 1 x. c2 $end +$var wire 1 y. c1 $end +$scope module a1 $end +$var wire 1 j. a $end +$var wire 1 l. b $end +$var wire 1 y. carryout $end +$var wire 1 w. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 w. a $end +$var wire 1 n. b $end +$var wire 1 x. carryout $end +$var wire 1 v. sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 z. in [7:0] $end +$var wire 8 {. sel [7:0] $end +$var wire 1 t. out $end +$var wire 8 |. ands [7:0] $end +$scope module andP $end +$var wire 8 }. A [7:0] $end +$var wire 8 ~. B [7:0] $end +$var wire 8 !/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 "/ in [7:0] $end +$var wire 1 t. out $end +$var wire 2 #/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 $/ in [3:0] $end +$var wire 1 %/ out $end +$var wire 2 &/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 '/ in [3:0] $end +$var wire 1 (/ out $end +$var wire 2 )/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 */ in [7:0] $end +$var wire 8 +/ sel [7:0] $end +$var wire 1 r. out $end +$var wire 8 ,/ ands [7:0] $end +$scope module andP $end +$var wire 8 -/ A [7:0] $end +$var wire 8 ./ B [7:0] $end +$var wire 8 // out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 0/ in [7:0] $end +$var wire 1 r. out $end +$var wire 2 1/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 2/ in [3:0] $end +$var wire 1 3/ out $end +$var wire 2 4/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 5/ in [3:0] $end +$var wire 1 6/ out $end +$var wire 2 7/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 j. a $end +$var wire 1 k. a_ $end +$var wire 1 l. b $end +$var wire 1 m. b_ $end +$var wire 1 n. carryin $end +$var wire 1 8/ eq $end +$var wire 1 9/ lt $end +$var wire 1 :/ out $end +$var wire 1 ;/ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 j. a $end +$var wire 1 m. b $end +$var wire 1 n. carryin $end +$var wire 1 / s1 $end +$var wire 1 ?/ c2 $end +$var wire 1 @/ c1 $end +$scope module a1 $end +$var wire 1 j. a $end +$var wire 1 m. b $end +$var wire 1 @/ carryout $end +$var wire 1 >/ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 >/ a $end +$var wire 1 n. b $end +$var wire 1 ?/ carryout $end +$var wire 1 =/ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[25] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 A/ A $end +$var wire 1 B/ A_ $end +$var wire 1 C/ B $end +$var wire 1 D/ B_ $end +$var wire 1 E/ carryin $end +$var wire 8 F/ command [7:0] $end +$var wire 1 G/ zero $end +$var wire 8 H/ results [7:0] $end +$var wire 1 I/ result $end +$var wire 8 J/ carryouts [7:0] $end +$var wire 1 K/ carryout $end +$scope module adder $end +$var wire 1 A/ a $end +$var wire 1 C/ b $end +$var wire 1 E/ carryin $end +$var wire 1 L/ carryout $end +$var wire 1 M/ sum $end +$var wire 1 N/ s1 $end +$var wire 1 O/ c2 $end +$var wire 1 P/ c1 $end +$scope module a1 $end +$var wire 1 A/ a $end +$var wire 1 C/ b $end +$var wire 1 P/ carryout $end +$var wire 1 N/ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 N/ a $end +$var wire 1 E/ b $end +$var wire 1 O/ carryout $end +$var wire 1 M/ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 Q/ in [7:0] $end +$var wire 8 R/ sel [7:0] $end +$var wire 1 K/ out $end +$var wire 8 S/ ands [7:0] $end +$scope module andP $end +$var wire 8 T/ A [7:0] $end +$var wire 8 U/ B [7:0] $end +$var wire 8 V/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 W/ in [7:0] $end +$var wire 1 K/ out $end +$var wire 2 X/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 Y/ in [3:0] $end +$var wire 1 Z/ out $end +$var wire 2 [/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 \/ in [3:0] $end +$var wire 1 ]/ out $end +$var wire 2 ^/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 _/ in [7:0] $end +$var wire 8 `/ sel [7:0] $end +$var wire 1 I/ out $end +$var wire 8 a/ ands [7:0] $end +$scope module andP $end +$var wire 8 b/ A [7:0] $end +$var wire 8 c/ B [7:0] $end +$var wire 8 d/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 e/ in [7:0] $end +$var wire 1 I/ out $end +$var wire 2 f/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 g/ in [3:0] $end +$var wire 1 h/ out $end +$var wire 2 i/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 j/ in [3:0] $end +$var wire 1 k/ out $end +$var wire 2 l/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 A/ a $end +$var wire 1 B/ a_ $end +$var wire 1 C/ b $end +$var wire 1 D/ b_ $end +$var wire 1 E/ carryin $end +$var wire 1 m/ eq $end +$var wire 1 n/ lt $end +$var wire 1 o/ out $end +$var wire 1 p/ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 A/ a $end +$var wire 1 D/ b $end +$var wire 1 E/ carryin $end +$var wire 1 q/ carryout $end +$var wire 1 r/ sum $end +$var wire 1 s/ s1 $end +$var wire 1 t/ c2 $end +$var wire 1 u/ c1 $end +$scope module a1 $end +$var wire 1 A/ a $end +$var wire 1 D/ b $end +$var wire 1 u/ carryout $end +$var wire 1 s/ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 s/ a $end +$var wire 1 E/ b $end +$var wire 1 t/ carryout $end +$var wire 1 r/ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[26] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 v/ A $end +$var wire 1 w/ A_ $end +$var wire 1 x/ B $end +$var wire 1 y/ B_ $end +$var wire 1 z/ carryin $end +$var wire 8 {/ command [7:0] $end +$var wire 1 |/ zero $end +$var wire 8 }/ results [7:0] $end +$var wire 1 ~/ result $end +$var wire 8 !0 carryouts [7:0] $end +$var wire 1 "0 carryout $end +$scope module adder $end +$var wire 1 v/ a $end +$var wire 1 x/ b $end +$var wire 1 z/ carryin $end +$var wire 1 #0 carryout $end +$var wire 1 $0 sum $end +$var wire 1 %0 s1 $end +$var wire 1 &0 c2 $end +$var wire 1 '0 c1 $end +$scope module a1 $end +$var wire 1 v/ a $end +$var wire 1 x/ b $end +$var wire 1 '0 carryout $end +$var wire 1 %0 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 %0 a $end +$var wire 1 z/ b $end +$var wire 1 &0 carryout $end +$var wire 1 $0 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 (0 in [7:0] $end +$var wire 8 )0 sel [7:0] $end +$var wire 1 "0 out $end +$var wire 8 *0 ands [7:0] $end +$scope module andP $end +$var wire 8 +0 A [7:0] $end +$var wire 8 ,0 B [7:0] $end +$var wire 8 -0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 .0 in [7:0] $end +$var wire 1 "0 out $end +$var wire 2 /0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 00 in [3:0] $end +$var wire 1 10 out $end +$var wire 2 20 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 30 in [3:0] $end +$var wire 1 40 out $end +$var wire 2 50 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 60 in [7:0] $end +$var wire 8 70 sel [7:0] $end +$var wire 1 ~/ out $end +$var wire 8 80 ands [7:0] $end +$scope module andP $end +$var wire 8 90 A [7:0] $end +$var wire 8 :0 B [7:0] $end +$var wire 8 ;0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 <0 in [7:0] $end +$var wire 1 ~/ out $end +$var wire 2 =0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 >0 in [3:0] $end +$var wire 1 ?0 out $end +$var wire 2 @0 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 A0 in [3:0] $end +$var wire 1 B0 out $end +$var wire 2 C0 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 v/ a $end +$var wire 1 w/ a_ $end +$var wire 1 x/ b $end +$var wire 1 y/ b_ $end +$var wire 1 z/ carryin $end +$var wire 1 D0 eq $end +$var wire 1 E0 lt $end +$var wire 1 F0 out $end +$var wire 1 G0 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 v/ a $end +$var wire 1 y/ b $end +$var wire 1 z/ carryin $end +$var wire 1 H0 carryout $end +$var wire 1 I0 sum $end +$var wire 1 J0 s1 $end +$var wire 1 K0 c2 $end +$var wire 1 L0 c1 $end +$scope module a1 $end +$var wire 1 v/ a $end +$var wire 1 y/ b $end +$var wire 1 L0 carryout $end +$var wire 1 J0 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 J0 a $end +$var wire 1 z/ b $end +$var wire 1 K0 carryout $end +$var wire 1 I0 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[27] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 M0 A $end +$var wire 1 N0 A_ $end +$var wire 1 O0 B $end +$var wire 1 P0 B_ $end +$var wire 1 Q0 carryin $end +$var wire 8 R0 command [7:0] $end +$var wire 1 S0 zero $end +$var wire 8 T0 results [7:0] $end +$var wire 1 U0 result $end +$var wire 8 V0 carryouts [7:0] $end +$var wire 1 W0 carryout $end +$scope module adder $end +$var wire 1 M0 a $end +$var wire 1 O0 b $end +$var wire 1 Q0 carryin $end +$var wire 1 X0 carryout $end +$var wire 1 Y0 sum $end +$var wire 1 Z0 s1 $end +$var wire 1 [0 c2 $end +$var wire 1 \0 c1 $end +$scope module a1 $end +$var wire 1 M0 a $end +$var wire 1 O0 b $end +$var wire 1 \0 carryout $end +$var wire 1 Z0 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 Z0 a $end +$var wire 1 Q0 b $end +$var wire 1 [0 carryout $end +$var wire 1 Y0 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 ]0 in [7:0] $end +$var wire 8 ^0 sel [7:0] $end +$var wire 1 W0 out $end +$var wire 8 _0 ands [7:0] $end +$scope module andP $end +$var wire 8 `0 A [7:0] $end +$var wire 8 a0 B [7:0] $end +$var wire 8 b0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 c0 in [7:0] $end +$var wire 1 W0 out $end +$var wire 2 d0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 e0 in [3:0] $end +$var wire 1 f0 out $end +$var wire 2 g0 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 h0 in [3:0] $end +$var wire 1 i0 out $end +$var wire 2 j0 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 k0 in [7:0] $end +$var wire 8 l0 sel [7:0] $end +$var wire 1 U0 out $end +$var wire 8 m0 ands [7:0] $end +$scope module andP $end +$var wire 8 n0 A [7:0] $end +$var wire 8 o0 B [7:0] $end +$var wire 8 p0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 q0 in [7:0] $end +$var wire 1 U0 out $end +$var wire 2 r0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 s0 in [3:0] $end +$var wire 1 t0 out $end +$var wire 2 u0 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 v0 in [3:0] $end +$var wire 1 w0 out $end +$var wire 2 x0 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 M0 a $end +$var wire 1 N0 a_ $end +$var wire 1 O0 b $end +$var wire 1 P0 b_ $end +$var wire 1 Q0 carryin $end +$var wire 1 y0 eq $end +$var wire 1 z0 lt $end +$var wire 1 {0 out $end +$var wire 1 |0 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 M0 a $end +$var wire 1 P0 b $end +$var wire 1 Q0 carryin $end +$var wire 1 }0 carryout $end +$var wire 1 ~0 sum $end +$var wire 1 !1 s1 $end +$var wire 1 "1 c2 $end +$var wire 1 #1 c1 $end +$scope module a1 $end +$var wire 1 M0 a $end +$var wire 1 P0 b $end +$var wire 1 #1 carryout $end +$var wire 1 !1 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 !1 a $end +$var wire 1 Q0 b $end +$var wire 1 "1 carryout $end +$var wire 1 ~0 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[28] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 $1 A $end +$var wire 1 %1 A_ $end +$var wire 1 &1 B $end +$var wire 1 '1 B_ $end +$var wire 1 (1 carryin $end +$var wire 8 )1 command [7:0] $end +$var wire 1 *1 zero $end +$var wire 8 +1 results [7:0] $end +$var wire 1 ,1 result $end +$var wire 8 -1 carryouts [7:0] $end +$var wire 1 .1 carryout $end +$scope module adder $end +$var wire 1 $1 a $end +$var wire 1 &1 b $end +$var wire 1 (1 carryin $end +$var wire 1 /1 carryout $end +$var wire 1 01 sum $end +$var wire 1 11 s1 $end +$var wire 1 21 c2 $end +$var wire 1 31 c1 $end +$scope module a1 $end +$var wire 1 $1 a $end +$var wire 1 &1 b $end +$var wire 1 31 carryout $end +$var wire 1 11 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 11 a $end +$var wire 1 (1 b $end +$var wire 1 21 carryout $end +$var wire 1 01 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 41 in [7:0] $end +$var wire 8 51 sel [7:0] $end +$var wire 1 .1 out $end +$var wire 8 61 ands [7:0] $end +$scope module andP $end +$var wire 8 71 A [7:0] $end +$var wire 8 81 B [7:0] $end +$var wire 8 91 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 :1 in [7:0] $end +$var wire 1 .1 out $end +$var wire 2 ;1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 <1 in [3:0] $end +$var wire 1 =1 out $end +$var wire 2 >1 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ?1 in [3:0] $end +$var wire 1 @1 out $end +$var wire 2 A1 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 B1 in [7:0] $end +$var wire 8 C1 sel [7:0] $end +$var wire 1 ,1 out $end +$var wire 8 D1 ands [7:0] $end +$scope module andP $end +$var wire 8 E1 A [7:0] $end +$var wire 8 F1 B [7:0] $end +$var wire 8 G1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 H1 in [7:0] $end +$var wire 1 ,1 out $end +$var wire 2 I1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 J1 in [3:0] $end +$var wire 1 K1 out $end +$var wire 2 L1 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 M1 in [3:0] $end +$var wire 1 N1 out $end +$var wire 2 O1 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 $1 a $end +$var wire 1 %1 a_ $end +$var wire 1 &1 b $end +$var wire 1 '1 b_ $end +$var wire 1 (1 carryin $end +$var wire 1 P1 eq $end +$var wire 1 Q1 lt $end +$var wire 1 R1 out $end +$var wire 1 S1 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 $1 a $end +$var wire 1 '1 b $end +$var wire 1 (1 carryin $end +$var wire 1 T1 carryout $end +$var wire 1 U1 sum $end +$var wire 1 V1 s1 $end +$var wire 1 W1 c2 $end +$var wire 1 X1 c1 $end +$scope module a1 $end +$var wire 1 $1 a $end +$var wire 1 '1 b $end +$var wire 1 X1 carryout $end +$var wire 1 V1 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 V1 a $end +$var wire 1 (1 b $end +$var wire 1 W1 carryout $end +$var wire 1 U1 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[29] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 Y1 A $end +$var wire 1 Z1 A_ $end +$var wire 1 [1 B $end +$var wire 1 \1 B_ $end +$var wire 1 ]1 carryin $end +$var wire 8 ^1 command [7:0] $end +$var wire 1 _1 zero $end +$var wire 8 `1 results [7:0] $end +$var wire 1 a1 result $end +$var wire 8 b1 carryouts [7:0] $end +$var wire 1 c1 carryout $end +$scope module adder $end +$var wire 1 Y1 a $end +$var wire 1 [1 b $end +$var wire 1 ]1 carryin $end +$var wire 1 d1 carryout $end +$var wire 1 e1 sum $end +$var wire 1 f1 s1 $end +$var wire 1 g1 c2 $end +$var wire 1 h1 c1 $end +$scope module a1 $end +$var wire 1 Y1 a $end +$var wire 1 [1 b $end +$var wire 1 h1 carryout $end +$var wire 1 f1 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 f1 a $end +$var wire 1 ]1 b $end +$var wire 1 g1 carryout $end +$var wire 1 e1 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 i1 in [7:0] $end +$var wire 8 j1 sel [7:0] $end +$var wire 1 c1 out $end +$var wire 8 k1 ands [7:0] $end +$scope module andP $end +$var wire 8 l1 A [7:0] $end +$var wire 8 m1 B [7:0] $end +$var wire 8 n1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 o1 in [7:0] $end +$var wire 1 c1 out $end +$var wire 2 p1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 q1 in [3:0] $end +$var wire 1 r1 out $end +$var wire 2 s1 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 t1 in [3:0] $end +$var wire 1 u1 out $end +$var wire 2 v1 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 w1 in [7:0] $end +$var wire 8 x1 sel [7:0] $end +$var wire 1 a1 out $end +$var wire 8 y1 ands [7:0] $end +$scope module andP $end +$var wire 8 z1 A [7:0] $end +$var wire 8 {1 B [7:0] $end +$var wire 8 |1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 }1 in [7:0] $end +$var wire 1 a1 out $end +$var wire 2 ~1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 !2 in [3:0] $end +$var wire 1 "2 out $end +$var wire 2 #2 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 $2 in [3:0] $end +$var wire 1 %2 out $end +$var wire 2 &2 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 Y1 a $end +$var wire 1 Z1 a_ $end +$var wire 1 [1 b $end +$var wire 1 \1 b_ $end +$var wire 1 ]1 carryin $end +$var wire 1 '2 eq $end +$var wire 1 (2 lt $end +$var wire 1 )2 out $end +$var wire 1 *2 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 Y1 a $end +$var wire 1 \1 b $end +$var wire 1 ]1 carryin $end +$var wire 1 +2 carryout $end +$var wire 1 ,2 sum $end +$var wire 1 -2 s1 $end +$var wire 1 .2 c2 $end +$var wire 1 /2 c1 $end +$scope module a1 $end +$var wire 1 Y1 a $end +$var wire 1 \1 b $end +$var wire 1 /2 carryout $end +$var wire 1 -2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 -2 a $end +$var wire 1 ]1 b $end +$var wire 1 .2 carryout $end +$var wire 1 ,2 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[30] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 02 A $end +$var wire 1 12 A_ $end +$var wire 1 22 B $end +$var wire 1 32 B_ $end +$var wire 1 42 carryin $end +$var wire 8 52 command [7:0] $end +$var wire 1 62 zero $end +$var wire 8 72 results [7:0] $end +$var wire 1 82 result $end +$var wire 8 92 carryouts [7:0] $end +$var wire 1 :2 carryout $end +$scope module adder $end +$var wire 1 02 a $end +$var wire 1 22 b $end +$var wire 1 42 carryin $end +$var wire 1 ;2 carryout $end +$var wire 1 <2 sum $end +$var wire 1 =2 s1 $end +$var wire 1 >2 c2 $end +$var wire 1 ?2 c1 $end +$scope module a1 $end +$var wire 1 02 a $end +$var wire 1 22 b $end +$var wire 1 ?2 carryout $end +$var wire 1 =2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 =2 a $end +$var wire 1 42 b $end +$var wire 1 >2 carryout $end +$var wire 1 <2 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 @2 in [7:0] $end +$var wire 8 A2 sel [7:0] $end +$var wire 1 :2 out $end +$var wire 8 B2 ands [7:0] $end +$scope module andP $end +$var wire 8 C2 A [7:0] $end +$var wire 8 D2 B [7:0] $end +$var wire 8 E2 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 F2 in [7:0] $end +$var wire 1 :2 out $end +$var wire 2 G2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 H2 in [3:0] $end +$var wire 1 I2 out $end +$var wire 2 J2 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 K2 in [3:0] $end +$var wire 1 L2 out $end +$var wire 2 M2 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 N2 in [7:0] $end +$var wire 8 O2 sel [7:0] $end +$var wire 1 82 out $end +$var wire 8 P2 ands [7:0] $end +$scope module andP $end +$var wire 8 Q2 A [7:0] $end +$var wire 8 R2 B [7:0] $end +$var wire 8 S2 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 T2 in [7:0] $end +$var wire 1 82 out $end +$var wire 2 U2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 V2 in [3:0] $end +$var wire 1 W2 out $end +$var wire 2 X2 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 Y2 in [3:0] $end +$var wire 1 Z2 out $end +$var wire 2 [2 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 02 a $end +$var wire 1 12 a_ $end +$var wire 1 22 b $end +$var wire 1 32 b_ $end +$var wire 1 42 carryin $end +$var wire 1 \2 eq $end +$var wire 1 ]2 lt $end +$var wire 1 ^2 out $end +$var wire 1 _2 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 02 a $end +$var wire 1 32 b $end +$var wire 1 42 carryin $end +$var wire 1 `2 carryout $end +$var wire 1 a2 sum $end +$var wire 1 b2 s1 $end +$var wire 1 c2 c2 $end +$var wire 1 d2 c1 $end +$scope module a1 $end +$var wire 1 02 a $end +$var wire 1 32 b $end +$var wire 1 d2 carryout $end +$var wire 1 b2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 b2 a $end +$var wire 1 42 b $end +$var wire 1 c2 carryout $end +$var wire 1 a2 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[31] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 e2 A $end +$var wire 1 f2 A_ $end +$var wire 1 g2 B $end +$var wire 1 h2 B_ $end +$var wire 1 i2 carryin $end +$var wire 8 j2 command [7:0] $end +$var wire 1 k2 zero $end +$var wire 8 l2 results [7:0] $end +$var wire 1 m2 result $end +$var wire 8 n2 carryouts [7:0] $end +$var wire 1 o2 carryout $end +$scope module adder $end +$var wire 1 e2 a $end +$var wire 1 g2 b $end +$var wire 1 i2 carryin $end +$var wire 1 p2 carryout $end +$var wire 1 q2 sum $end +$var wire 1 r2 s1 $end +$var wire 1 s2 c2 $end +$var wire 1 t2 c1 $end +$scope module a1 $end +$var wire 1 e2 a $end +$var wire 1 g2 b $end +$var wire 1 t2 carryout $end +$var wire 1 r2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 r2 a $end +$var wire 1 i2 b $end +$var wire 1 s2 carryout $end +$var wire 1 q2 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 u2 in [7:0] $end +$var wire 8 v2 sel [7:0] $end +$var wire 1 o2 out $end +$var wire 8 w2 ands [7:0] $end +$scope module andP $end +$var wire 8 x2 A [7:0] $end +$var wire 8 y2 B [7:0] $end +$var wire 8 z2 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 {2 in [7:0] $end +$var wire 1 o2 out $end +$var wire 2 |2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 }2 in [3:0] $end +$var wire 1 ~2 out $end +$var wire 2 !3 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 "3 in [3:0] $end +$var wire 1 #3 out $end +$var wire 2 $3 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 %3 in [7:0] $end +$var wire 8 &3 sel [7:0] $end +$var wire 1 m2 out $end +$var wire 8 '3 ands [7:0] $end +$scope module andP $end +$var wire 8 (3 A [7:0] $end +$var wire 8 )3 B [7:0] $end +$var wire 8 *3 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 +3 in [7:0] $end +$var wire 1 m2 out $end +$var wire 2 ,3 ors [1:0] $end +$scope module or_1 $end +$var wire 4 -3 in [3:0] $end +$var wire 1 .3 out $end +$var wire 2 /3 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 03 in [3:0] $end +$var wire 1 13 out $end +$var wire 2 23 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 e2 a $end +$var wire 1 f2 a_ $end +$var wire 1 g2 b $end +$var wire 1 h2 b_ $end +$var wire 1 i2 carryin $end +$var wire 1 33 eq $end +$var wire 1 43 lt $end +$var wire 1 53 out $end +$var wire 1 63 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 e2 a $end +$var wire 1 h2 b $end +$var wire 1 i2 carryin $end +$var wire 1 73 carryout $end +$var wire 1 83 sum $end +$var wire 1 93 s1 $end +$var wire 1 :3 c2 $end +$var wire 1 ;3 c1 $end +$scope module a1 $end +$var wire 1 e2 a $end +$var wire 1 h2 b $end +$var wire 1 ;3 carryout $end +$var wire 1 93 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 93 a $end +$var wire 1 i2 b $end +$var wire 1 :3 carryout $end +$var wire 1 83 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module overflowMux $end +$var wire 1 * a $end +$var wire 1 / b $end +$var wire 1 5 out $end +$var wire 1 <3 s $end +$var wire 1 =3 s_ $end +$var wire 1 >3 w0 $end +$var wire 1 ?3 w1 $end +$upscope $end +$scope module resultOr $end +$var wire 32 @3 A [31:0] $end +$var wire 32 A3 B [31:0] $end +$var wire 32 B3 out [31:0] $end +$scope begin or_slces[0] $end +$upscope $end +$scope begin or_slces[1] $end +$upscope $end +$scope begin or_slces[2] $end +$upscope $end +$scope begin or_slces[3] $end +$upscope $end +$scope begin or_slces[4] $end +$upscope $end +$scope begin or_slces[5] $end +$upscope $end +$scope begin or_slces[6] $end +$upscope $end +$scope begin or_slces[7] $end +$upscope $end +$scope begin or_slces[8] $end +$upscope $end +$scope begin or_slces[9] $end +$upscope $end +$scope begin or_slces[10] $end +$upscope $end +$scope begin or_slces[11] $end +$upscope $end +$scope begin or_slces[12] $end +$upscope $end +$scope begin or_slces[13] $end +$upscope $end +$scope begin or_slces[14] $end +$upscope $end +$scope begin or_slces[15] $end +$upscope $end +$scope begin or_slces[16] $end +$upscope $end +$scope begin or_slces[17] $end +$upscope $end +$scope begin or_slces[18] $end +$upscope $end +$scope begin or_slces[19] $end +$upscope $end +$scope begin or_slces[20] $end +$upscope $end +$scope begin or_slces[21] $end +$upscope $end +$scope begin or_slces[22] $end +$upscope $end +$scope begin or_slces[23] $end +$upscope $end +$scope begin or_slces[24] $end +$upscope $end +$scope begin or_slces[25] $end +$upscope $end +$scope begin or_slces[26] $end +$upscope $end +$scope begin or_slces[27] $end +$upscope $end +$scope begin or_slces[28] $end +$upscope $end +$scope begin or_slces[29] $end +$upscope $end +$scope begin or_slces[30] $end +$upscope $end +$scope begin or_slces[31] $end +$upscope $end +$upscope $end +$scope module zeroout $end +$var wire 32 C3 in [31:0] $end +$var wire 1 ! out $end +$var wire 2 D3 ands [1:0] $end +$scope module and_1 $end +$var wire 16 E3 in [15:0] $end +$var wire 1 F3 out $end +$var wire 2 G3 ands [1:0] $end +$scope module and_1 $end +$var wire 8 H3 in [7:0] $end +$var wire 1 I3 out $end +$var wire 2 J3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 K3 in [3:0] $end +$var wire 1 L3 out $end +$var wire 2 M3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 N3 in [3:0] $end +$var wire 1 O3 out $end +$var wire 2 P3 ands [1:0] $end +$upscope $end +$upscope $end +$scope module and_2 $end +$var wire 8 Q3 in [7:0] $end +$var wire 1 R3 out $end +$var wire 2 S3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 T3 in [3:0] $end +$var wire 1 U3 out $end +$var wire 2 V3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 W3 in [3:0] $end +$var wire 1 X3 out $end +$var wire 2 Y3 ands [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module and_2 $end +$var wire 16 Z3 in [15:0] $end +$var wire 1 [3 out $end +$var wire 2 \3 ands [1:0] $end +$scope module and_1 $end +$var wire 8 ]3 in [7:0] $end +$var wire 1 ^3 out $end +$var wire 2 _3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 `3 in [3:0] $end +$var wire 1 a3 out $end +$var wire 2 b3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 c3 in [3:0] $end +$var wire 1 d3 out $end +$var wire 2 e3 ands [1:0] $end +$upscope $end +$upscope $end +$scope module and_2 $end +$var wire 8 f3 in [7:0] $end +$var wire 1 g3 out $end +$var wire 2 h3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 i3 in [3:0] $end +$var wire 1 j3 out $end +$var wire 2 k3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 l3 in [3:0] $end +$var wire 1 m3 out $end +$var wire 2 n3 ands [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx n3 +xm3 +bx l3 +bx k3 +xj3 +bx i3 +bx h3 +xg3 +bx f3 +bx e3 +xd3 +bx c3 +bx b3 +xa3 +bx `3 +bx _3 +x^3 +bx ]3 +bx \3 +x[3 +bx Z3 +bx Y3 +xX3 +bx W3 +bx V3 +xU3 +bx T3 +bx S3 +xR3 +bx Q3 +bx P3 +xO3 +bx N3 +bx M3 +xL3 +bx K3 +bx J3 +xI3 +bx H3 +bx G3 +xF3 +bx E3 +bx D3 +bx C3 +bx B3 +bx A3 +bx @3 +x?3 +x>3 +x=3 +1<3 +x;3 +x:3 +x93 +x83 +x73 +x63 +x53 +x43 +x33 +bx 23 +x13 +bx 03 +bx /3 +x.3 +bx -3 +bx ,3 +bx +3 +bx *3 +b1 )3 +bx (3 +bx '3 +b1 &3 +bx %3 +bx $3 +x#3 +bx "3 +bx !3 +x~2 +bx }2 +bx |2 +bx {2 +bx z2 +b1 y2 +bx x2 +bx w2 +b1 v2 +bx u2 +xt2 +xs2 +xr2 +xq2 +xp2 +xo2 +bx n2 +xm2 +bx l2 +xk2 +b1 j2 +xi2 +xh2 +0g2 +xf2 +1e2 +xd2 +xc2 +xb2 +xa2 +x`2 +x_2 +x^2 +x]2 +x\2 +bx [2 +xZ2 +bx Y2 +bx X2 +xW2 +bx V2 +bx U2 +bx T2 +bx S2 +b1 R2 +bx Q2 +bx P2 +b1 O2 +bx N2 +bx M2 +xL2 +bx K2 +bx J2 +xI2 +bx H2 +bx G2 +bx F2 +bx E2 +b1 D2 +bx C2 +bx B2 +b1 A2 +bx @2 +x?2 +x>2 +x=2 +x<2 +x;2 +x:2 +bx 92 +x82 +bx 72 +x62 +b1 52 +x42 +x32 +022 +x12 +102 +x/2 +x.2 +x-2 +x,2 +x+2 +x*2 +x)2 +x(2 +x'2 +bx &2 +x%2 +bx $2 +bx #2 +x"2 +bx !2 +bx ~1 +bx }1 +bx |1 +b1 {1 +bx z1 +bx y1 +b1 x1 +bx w1 +bx v1 +xu1 +bx t1 +bx s1 +xr1 +bx q1 +bx p1 +bx o1 +bx n1 +b1 m1 +bx l1 +bx k1 +b1 j1 +bx i1 +xh1 +xg1 +xf1 +xe1 +xd1 +xc1 +bx b1 +xa1 +bx `1 +x_1 +b1 ^1 +x]1 +x\1 +0[1 +xZ1 +1Y1 +xX1 +xW1 +xV1 +xU1 +xT1 +xS1 +xR1 +xQ1 +xP1 +bx O1 +xN1 +bx M1 +bx L1 +xK1 +bx J1 +bx I1 +bx H1 +bx G1 +b1 F1 +bx E1 +bx D1 +b1 C1 +bx B1 +bx A1 +x@1 +bx ?1 +bx >1 +x=1 +bx <1 +bx ;1 +bx :1 +bx 91 +b1 81 +bx 71 +bx 61 +b1 51 +bx 41 +x31 +x21 +x11 +x01 +x/1 +x.1 +bx -1 +x,1 +bx +1 +x*1 +b1 )1 +x(1 +x'1 +0&1 +x%1 +1$1 +x#1 +x"1 +x!1 +x~0 +x}0 +x|0 +x{0 +xz0 +xy0 +bx x0 +xw0 +bx v0 +bx u0 +xt0 +bx s0 +bx r0 +bx q0 +bx p0 +b1 o0 +bx n0 +bx m0 +b1 l0 +bx k0 +bx j0 +xi0 +bx h0 +bx g0 +xf0 +bx e0 +bx d0 +bx c0 +bx b0 +b1 a0 +bx `0 +bx _0 +b1 ^0 +bx ]0 +x\0 +x[0 +xZ0 +xY0 +xX0 +xW0 +bx V0 +xU0 +bx T0 +xS0 +b1 R0 +xQ0 +xP0 +0O0 +xN0 +1M0 +xL0 +xK0 +xJ0 +xI0 +xH0 +xG0 +xF0 +xE0 +xD0 +bx C0 +xB0 +bx A0 +bx @0 +x?0 +bx >0 +bx =0 +bx <0 +bx ;0 +b1 :0 +bx 90 +bx 80 +b1 70 +bx 60 +bx 50 +x40 +bx 30 +bx 20 +x10 +bx 00 +bx /0 +bx .0 +bx -0 +b1 ,0 +bx +0 +bx *0 +b1 )0 +bx (0 +x'0 +x&0 +x%0 +x$0 +x#0 +x"0 +bx !0 +x~/ +bx }/ +x|/ +b1 {/ +xz/ +xy/ +0x/ +xw/ +1v/ +xu/ +xt/ +xs/ +xr/ +xq/ +xp/ +xo/ +xn/ +xm/ +bx l/ +xk/ +bx j/ +bx i/ +xh/ +bx g/ +bx f/ +bx e/ +bx d/ +b1 c/ +bx b/ +bx a/ +b1 `/ +bx _/ +bx ^/ +x]/ +bx \/ +bx [/ +xZ/ +bx Y/ +bx X/ +bx W/ +bx V/ +b1 U/ +bx T/ +bx S/ +b1 R/ +bx Q/ +xP/ +xO/ +xN/ +xM/ +xL/ +xK/ +bx J/ +xI/ +bx H/ +xG/ +b1 F/ +xE/ +xD/ +0C/ +xB/ +1A/ +x@/ +x?/ +x>/ +x=/ +x. +x=. +bx <. +x;. +b1 :. +x9. +x8. +07. +x6. +15. +x4. +x3. +x2. +x1. +x0. +x/. +x.. +x-. +x,. +bx +. +x*. +bx ). +bx (. +x'. +bx &. +bx %. +bx $. +bx #. +b1 ". +bx !. +bx ~- +b1 }- +bx |- +bx {- +xz- +bx y- +bx x- +xw- +bx v- +bx u- +bx t- +bx s- +b1 r- +bx q- +bx p- +b1 o- +bx n- +xm- +xl- +xk- +xj- +xi- +xh- +bx g- +xf- +bx e- +xd- +b1 c- +xb- +xa- +0`- +x_- +1^- +x]- +x\- +x[- +xZ- +xY- +xX- +xW- +xV- +xU- +bx T- +xS- +bx R- +bx Q- +xP- +bx O- +bx N- +bx M- +bx L- +b1 K- +bx J- +bx I- +b1 H- +bx G- +bx F- +xE- +bx D- +bx C- +xB- +bx A- +bx @- +bx ?- +bx >- +b1 =- +bx <- +bx ;- +b1 :- +bx 9- +x8- +x7- +x6- +x5- +x4- +x3- +bx 2- +x1- +bx 0- +x/- +b1 .- +x-- +x,- +0+- +x*- +1)- +x(- +x'- +x&- +x%- +x$- +x#- +x"- +x!- +x~, +bx }, +x|, +bx {, +bx z, +xy, +bx x, +bx w, +bx v, +bx u, +b1 t, +bx s, +bx r, +b1 q, +bx p, +bx o, +xn, +bx m, +bx l, +xk, +bx j, +bx i, +bx h, +bx g, +b1 f, +bx e, +bx d, +b1 c, +bx b, +xa, +x`, +x_, +x^, +x], +x\, +bx [, +xZ, +bx Y, +xX, +b1 W, +xV, +xU, +0T, +xS, +1R, +xQ, +xP, +xO, +xN, +xM, +xL, +xK, +xJ, +xI, +bx H, +xG, +bx F, +bx E, +xD, +bx C, +bx B, +bx A, +bx @, +b1 ?, +bx >, +bx =, +b1 <, +bx ;, +bx :, +x9, +bx 8, +bx 7, +x6, +bx 5, +bx 4, +bx 3, +bx 2, +b1 1, +bx 0, +bx /, +b1 ., +bx -, +x,, +x+, +x*, +x), +x(, +x', +bx &, +x%, +bx $, +x#, +b1 ", +x!, +x~+ +0}+ +x|+ +1{+ +xz+ +xy+ +xx+ +xw+ +xv+ +xu+ +xt+ +xs+ +xr+ +bx q+ +xp+ +bx o+ +bx n+ +xm+ +bx l+ +bx k+ +bx j+ +bx i+ +b1 h+ +bx g+ +bx f+ +b1 e+ +bx d+ +bx c+ +xb+ +bx a+ +bx `+ +x_+ +bx ^+ +bx ]+ +bx \+ +bx [+ +b1 Z+ +bx Y+ +bx X+ +b1 W+ +bx V+ +xU+ +xT+ +xS+ +xR+ +xQ+ +xP+ +bx O+ +xN+ +bx M+ +xL+ +b1 K+ +xJ+ +xI+ +0H+ +xG+ +1F+ +xE+ +xD+ +xC+ +xB+ +xA+ +x@+ +x?+ +x>+ +x=+ +bx <+ +x;+ +bx :+ +bx 9+ +x8+ +bx 7+ +bx 6+ +bx 5+ +bx 4+ +b1 3+ +bx 2+ +bx 1+ +b1 0+ +bx /+ +bx .+ +x-+ +bx ,+ +bx ++ +x*+ +bx )+ +bx (+ +bx '+ +bx &+ +b1 %+ +bx $+ +bx #+ +b1 "+ +bx !+ +x~* +x}* +x|* +x{* +xz* +xy* +bx x* +xw* +bx v* +xu* +b1 t* +xs* +xr* +0q* +xp* +1o* +xn* +xm* +xl* +xk* +xj* +xi* +xh* +xg* +xf* +bx e* +xd* +bx c* +bx b* +xa* +bx `* +bx _* +bx ^* +bx ]* +b1 \* +bx [* +bx Z* +b1 Y* +bx X* +bx W* +xV* +bx U* +bx T* +xS* +bx R* +bx Q* +bx P* +bx O* +b1 N* +bx M* +bx L* +b1 K* +bx J* +xI* +xH* +xG* +xF* +xE* +xD* +bx C* +xB* +bx A* +x@* +b1 ?* +x>* +x=* +0<* +x;* +1:* +x9* +x8* +x7* +x6* +x5* +x4* +x3* +x2* +x1* +bx 0* +x/* +bx .* +bx -* +x,* +bx +* +bx ** +bx )* +bx (* +b1 '* +bx &* +bx %* +b1 $* +bx #* +bx "* +x!* +bx ~) +bx }) +x|) +bx {) +bx z) +bx y) +bx x) +b1 w) +bx v) +bx u) +b1 t) +bx s) +xr) +xq) +xp) +xo) +xn) +xm) +bx l) +xk) +bx j) +xi) +b1 h) +xg) +xf) +0e) +xd) +1c) +xb) +xa) +x`) +x_) +x^) +x]) +x\) +x[) +xZ) +bx Y) +xX) +bx W) +bx V) +xU) +bx T) +bx S) +bx R) +bx Q) +b1 P) +bx O) +bx N) +b1 M) +bx L) +bx K) +xJ) +bx I) +bx H) +xG) +bx F) +bx E) +bx D) +bx C) +b1 B) +bx A) +bx @) +b1 ?) +bx >) +x=) +x<) +x;) +x:) +x9) +x8) +bx 7) +x6) +bx 5) +x4) +b1 3) +x2) +x1) +00) +x/) +1.) +x-) +x,) +x+) +x*) +x)) +x() +x') +x&) +x%) +bx $) +x#) +bx ") +bx !) +x~( +bx }( +bx |( +bx {( +bx z( +b1 y( +bx x( +bx w( +b1 v( +bx u( +bx t( +xs( +bx r( +bx q( +xp( +bx o( +bx n( +bx m( +bx l( +b1 k( +bx j( +bx i( +b1 h( +bx g( +xf( +xe( +xd( +xc( +xb( +xa( +bx `( +x_( +bx ^( +x]( +b1 \( +x[( +xZ( +0Y( +xX( +1W( +xV( +xU( +xT( +xS( +xR( +xQ( +xP( +xO( +xN( +bx M( +xL( +bx K( +bx J( +xI( +bx H( +bx G( +bx F( +bx E( +b1 D( +bx C( +bx B( +b1 A( +bx @( +bx ?( +x>( +bx =( +bx <( +x;( +bx :( +bx 9( +bx 8( +bx 7( +b1 6( +bx 5( +bx 4( +b1 3( +bx 2( +x1( +x0( +x/( +x.( +x-( +x,( +bx +( +x*( +bx )( +x(( +b1 '( +x&( +x%( +0$( +x#( +1"( +x!( +x~' +x}' +x|' +x{' +xz' +xy' +xx' +xw' +bx v' +xu' +bx t' +bx s' +xr' +bx q' +bx p' +bx o' +bx n' +b1 m' +bx l' +bx k' +b1 j' +bx i' +bx h' +xg' +bx f' +bx e' +xd' +bx c' +bx b' +bx a' +bx `' +b1 _' +bx ^' +bx ]' +b1 \' +bx [' +xZ' +xY' +xX' +xW' +xV' +xU' +bx T' +xS' +bx R' +xQ' +b1 P' +xO' +xN' +0M' +xL' +1K' +xJ' +xI' +xH' +xG' +xF' +xE' +xD' +xC' +xB' +bx A' +x@' +bx ?' +bx >' +x=' +bx <' +bx ;' +bx :' +bx 9' +b1 8' +bx 7' +bx 6' +b1 5' +bx 4' +bx 3' +x2' +bx 1' +bx 0' +x/' +bx .' +bx -' +bx ,' +bx +' +b1 *' +bx )' +bx (' +b1 '' +bx &' +x%' +x$' +x#' +x"' +x!' +x~& +bx }& +x|& +bx {& +xz& +b1 y& +xx& +xw& +0v& +xu& +1t& +xs& +xr& +xq& +xp& +xo& +xn& +xm& +xl& +xk& +bx j& +xi& +bx h& +bx g& +xf& +bx e& +bx d& +bx c& +bx b& +b1 a& +bx `& +bx _& +b1 ^& +bx ]& +bx \& +x[& +bx Z& +bx Y& +xX& +bx W& +bx V& +bx U& +bx T& +b1 S& +bx R& +bx Q& +b1 P& +bx O& +xN& +xM& +xL& +xK& +xJ& +xI& +bx H& +xG& +bx F& +xE& +b1 D& +xC& +xB& +0A& +x@& +1?& +x>& +x=& +x<& +x;& +x:& +x9& +x8& +x7& +x6& +bx 5& +x4& +bx 3& +bx 2& +x1& +bx 0& +bx /& +bx .& +bx -& +b1 ,& +bx +& +bx *& +b1 )& +bx (& +bx '& +x&& +bx %& +bx $& +x#& +bx "& +bx !& +bx ~% +bx }% +b1 |% +bx {% +bx z% +b1 y% +bx x% +xw% +xv% +xu% +xt% +xs% +xr% +bx q% +xp% +bx o% +xn% +b1 m% +xl% +xk% +0j% +xi% +1h% +xg% +xf% +xe% +xd% +xc% +xb% +xa% +x`% +x_% +bx ^% +x]% +bx \% +bx [% +xZ% +bx Y% +bx X% +bx W% +bx V% +b1 U% +bx T% +bx S% +b1 R% +bx Q% +bx P% +xO% +bx N% +bx M% +xL% +bx K% +bx J% +bx I% +bx H% +b1 G% +bx F% +bx E% +b1 D% +bx C% +xB% +xA% +x@% +x?% +x>% +x=% +bx <% +x;% +bx :% +x9% +b1 8% +x7% +x6% +05% +x4% +13% +x2% +x1% +x0% +x/% +x.% +x-% +x,% +x+% +x*% +bx )% +x(% +bx '% +bx &% +x%% +bx $% +bx #% +bx "% +bx !% +b1 ~$ +bx }$ +bx |$ +b1 {$ +bx z$ +bx y$ +xx$ +bx w$ +bx v$ +xu$ +bx t$ +bx s$ +bx r$ +bx q$ +b1 p$ +bx o$ +bx n$ +b1 m$ +bx l$ +xk$ +xj$ +xi$ +xh$ +xg$ +xf$ +bx e$ +xd$ +bx c$ +xb$ +b1 a$ +x`$ +x_$ +0^$ +x]$ +1\$ +x[$ +xZ$ +xY$ +xX$ +xW$ +xV$ +xU$ +xT$ +xS$ +bx R$ +xQ$ +bx P$ +bx O$ +xN$ +bx M$ +bx L$ +bx K$ +bx J$ +b1 I$ +bx H$ +bx G$ +b1 F$ +bx E$ +bx D$ +xC$ +bx B$ +bx A$ +x@$ +bx ?$ +bx >$ +bx =$ +bx <$ +b1 ;$ +bx :$ +bx 9$ +b1 8$ +bx 7$ +x6$ +x5$ +x4$ +x3$ +x2$ +x1$ +bx 0$ +x/$ +bx .$ +x-$ +b1 ,$ +x+$ +x*$ +0)$ +x($ +1'$ +x&$ +x%$ +x$$ +x#$ +x"$ +x!$ +x~# +x}# +x|# +bx {# +xz# +bx y# +bx x# +xw# +bx v# +bx u# +bx t# +bx s# +b1 r# +bx q# +bx p# +b1 o# +bx n# +bx m# +xl# +bx k# +bx j# +xi# +bx h# +bx g# +bx f# +bx e# +b1 d# +bx c# +bx b# +b1 a# +bx `# +x_# +x^# +x]# +x\# +x[# +xZ# +bx Y# +xX# +bx W# +xV# +b1 U# +xT# +xS# +0R# +xQ# +1P# +xO# +xN# +xM# +xL# +xK# +xJ# +xI# +xH# +xG# +bx F# +xE# +bx D# +bx C# +xB# +bx A# +bx @# +bx ?# +bx ># +b1 =# +bx <# +bx ;# +b1 :# +bx 9# +bx 8# +x7# +bx 6# +bx 5# +x4# +bx 3# +bx 2# +bx 1# +bx 0# +b1 /# +bx .# +bx -# +b1 ,# +bx +# +x*# +x)# +x(# +x'# +x&# +x%# +bx $# +x## +bx "# +x!# +b1 ~" +x}" +x|" +0{" +xz" +1y" +xx" +xw" +xv" +xu" +xt" +xs" +xr" +xq" +xp" +bx o" +xn" +bx m" +bx l" +xk" +bx j" +bx i" +bx h" +bx g" +b1 f" +bx e" +bx d" +b1 c" +bx b" +bx a" +x`" +bx _" +bx ^" +x]" +bx \" +bx [" +bx Z" +bx Y" +b1 X" +bx W" +bx V" +b1 U" +bx T" +xS" +xR" +xQ" +xP" +xO" +xN" +bx M" +xL" +bx K" +xJ" +b1 I" +xH" +xG" +1F" +xE" +1D" +xC" +xB" +xA" +x@" +x?" +x>" +x=" +x<" +x;" +bx :" +x9" +bx 8" +bx 7" +x6" +bx 5" +bx 4" +bx 3" +bx 2" +b1 1" +bx 0" +bx /" +b1 ." +bx -" +bx ," +x+" +bx *" +bx )" +x(" +bx '" +bx &" +bx %" +bx $" +b1 #" +bx "" +bx !" +b1 ~ +bx } +x| +x{ +xz +xy +xx +xw +bx v +xu +bx t +xs +b1 r +xq +xp +0o +xn +0m +xl +xk +xj +xi +xh +xg +xf +xe +xd +bx c +xb +bx a +bx ` +x_ +bx ^ +bx ] +bx \ +bx [ +b1 Z +bx Y +bx X +b1 W +bx V +bx U +xT +bx S +bx R +xQ +bx P +bx O +bx N +bx M +b1 L +bx K +bx J +b1 I +bx H +xG +xF +xE +xD +xC +xB +bx A +x@ +bx ? +x> +b1 = +x< +x; +0: +x9 +08 +b1 7 +bx 6 +x5 +bx 4 +bx 3 +bx 2 +bx 1 +x0 +x/ +x. +x- +b100 , +b11111111111111111111111111111100 + +x* +b0 ) +x( +b0 ' +b100 & +b11111111111111111111111111111100 % +x$ +x# +bx " +x! +$end +#10000 +0=3 +1; +1p +0G" +1|" +1S# +1*$ +1_$ +16% +1k% +1B& +1w& +1N' +1%( +1Z( +11) +1f) +1=* +1r* +1I+ +1~+ +1U, +1,- +1a- +18. +1m. +1D/ +1y/ +1P0 +1'1 +1\1 +132 +1h2 +19 +1n +0E" +0z" +0Q# +0($ +0]$ +04% +0i% +0@& +0u& +0L' +0#( +0X( +0/) +0d) +0;* +0p* +0G+ +0|+ +0S, +0*- +0_- +06. +0k. +0B/ +0w/ +0N0 +0%1 +0Z1 +012 +0f2 +#20000 +bx11xxxxx ? +bx11xxxxx V +bx11xxxxx Y +1d +bx11xxxxx t +bx11xxxxx -" +bx11xxxxx 0" +1;" +bx00xxxxx K" +bx00xxxxx b" +bx00xxxxx e" +1p" +bx01xxxxx "# +bx01xxxxx 9# +bx01xxxxx <# +0G# +bx01xxxxx W# +bx01xxxxx n# +bx01xxxxx q# +0|# +bx01xxxxx .$ +bx01xxxxx E$ +bx01xxxxx H$ +0S$ +bx01xxxxx c$ +bx01xxxxx z$ +bx01xxxxx }$ +0*% +bx01xxxxx :% +bx01xxxxx Q% +bx01xxxxx T% +0_% +bx01xxxxx o% +bx01xxxxx (& +bx01xxxxx +& +06& +bx01xxxxx F& +bx01xxxxx ]& +bx01xxxxx `& +0k& +bx01xxxxx {& +bx01xxxxx 4' +bx01xxxxx 7' +0B' +bx01xxxxx R' +bx01xxxxx i' +bx01xxxxx l' +0w' +bx01xxxxx )( +bx01xxxxx @( +bx01xxxxx C( +0N( +bx01xxxxx ^( +bx01xxxxx u( +bx01xxxxx x( +0%) +bx01xxxxx 5) +bx01xxxxx L) +bx01xxxxx O) +0Z) +bx01xxxxx j) +bx01xxxxx #* +bx01xxxxx &* +01* +bx01xxxxx A* +bx01xxxxx X* +bx01xxxxx [* +0f* +bx01xxxxx v* +bx01xxxxx /+ +bx01xxxxx 2+ +0=+ +bx01xxxxx M+ +bx01xxxxx d+ +bx01xxxxx g+ +0r+ +bx01xxxxx $, +bx01xxxxx ;, +bx01xxxxx >, +0I, +bx01xxxxx Y, +bx01xxxxx p, +bx01xxxxx s, +0~, +bx01xxxxx 0- +bx01xxxxx G- +bx01xxxxx J- +0U- +bx01xxxxx e- +bx01xxxxx |- +bx01xxxxx !. +0,. +bx01xxxxx <. +bx01xxxxx S. +bx01xxxxx V. +0a. +bx01xxxxx q. +bx01xxxxx */ +bx01xxxxx -/ +08/ +bx01xxxxx H/ +bx01xxxxx _/ +bx01xxxxx b/ +0m/ +bx01xxxxx }/ +bx01xxxxx 60 +bx01xxxxx 90 +0D0 +bx01xxxxx T0 +bx01xxxxx k0 +bx01xxxxx n0 +0y0 +bx01xxxxx +1 +bx01xxxxx B1 +bx01xxxxx E1 +0P1 +bx01xxxxx `1 +bx01xxxxx w1 +bx01xxxxx z1 +0'2 +bx01xxxxx 72 +bx01xxxxx N2 +bx01xxxxx Q2 +0\2 +bx01xxxxx l2 +bx01xxxxx %3 +bx01xxxxx (3 +033 +0/ +#30000 +0< +b0x P +b0 S +b0x ^ +b0 a +b0x '" +b0 *" +b0x 5" +b0 8" +b0x \" +b0 _" +b0x j" +b0 m" +b0x 3# +b0 6# +b0x A# +b0 D# +b0x h# +b0 k# +b0x v# +b0 y# +b0x ?$ +b0 B$ +b0x M$ +b0 P$ +b0x t$ +b0 w$ +b0x $% +b0 '% +b0x K% +b0 N% +b0x Y% +b0 \% +b0x "& +b0 %& +b0x 0& +b0 3& +b0x W& +b0 Z& +b0x e& +b0 h& +b0x .' +b0 1' +b0x <' +b0 ?' +b0x c' +b0 f' +b0x q' +b0 t' +b0x :( +b0 =( +b0x H( +b0 K( +b0x o( +b0 r( +b0x }( +b0 ") +b0x F) +b0 I) +b0x T) +b0 W) +b0x {) +b0 ~) +b0x +* +b0 .* +b0x R* +b0 U* +b0x `* +b0 c* +b0x )+ +b0 ,+ +b0x 7+ +b0 :+ +b0x ^+ +b0 a+ +b0x l+ +b0 o+ +b0x 5, +b0 8, +b0x C, +b0 F, +b0x j, +b0 m, +b0x x, +b0 {, +b0x A- +b0 D- +b0x O- +b0 R- +b0x v- +b0 y- +b0x &. +b0 ). +b0x M. +b0 P. +b0x [. +b0 ^. +b0x $/ +b0 '/ +b0x 2/ +b0 5/ +b0x Y/ +b0 \/ +b0x g/ +b0 j/ +b0x 00 +b0 30 +b0x >0 +b0 A0 +b0x e0 +b0 h0 +b0x s0 +b0 v0 +b0x <1 +b0 ?1 +b0x J1 +b0 M1 +b0x q1 +b0 t1 +b0x !2 +b0 $2 +b0x H2 +b0 K2 +b0x V2 +b0 Y2 +b0x }2 +b0 "3 +b0x -3 +b0 03 +1* +bx0 6 +1( +b0x J +b0x M +b0x N +b0x X +b0x [ +b0x \ +b0x !" +b0x $" +b0x %" +b0x /" +b0x 2" +b0x 3" +b0x V" +b0x Y" +b0x Z" +b0x d" +b0x g" +b0x h" +b0x -# +b0x 0# +b0x 1# +b0x ;# +b0x ># +b0x ?# +b0x b# +b0x e# +b0x f# +b0x p# +b0x s# +b0x t# +b0x 9$ +b0x <$ +b0x =$ +b0x G$ +b0x J$ +b0x K$ +b0x n$ +b0x q$ +b0x r$ +b0x |$ +b0x !% +b0x "% +b0x E% +b0x H% +b0x I% +b0x S% +b0x V% +b0x W% +b0x z% +b0x }% +b0x ~% +b0x *& +b0x -& +b0x .& +b0x Q& +b0x T& +b0x U& +b0x _& +b0x b& +b0x c& +b0x (' +b0x +' +b0x ,' +b0x 6' +b0x 9' +b0x :' +b0x ]' +b0x `' +b0x a' +b0x k' +b0x n' +b0x o' +b0x 4( +b0x 7( +b0x 8( +b0x B( +b0x E( +b0x F( +b0x i( +b0x l( +b0x m( +b0x w( +b0x z( +b0x {( +b0x @) +b0x C) +b0x D) +b0x N) +b0x Q) +b0x R) +b0x u) +b0x x) +b0x y) +b0x %* +b0x (* +b0x )* +b0x L* +b0x O* +b0x P* +b0x Z* +b0x ]* +b0x ^* +b0x #+ +b0x &+ +b0x '+ +b0x 1+ +b0x 4+ +b0x 5+ +b0x X+ +b0x [+ +b0x \+ +b0x f+ +b0x i+ +b0x j+ +b0x /, +b0x 2, +b0x 3, +b0x =, +b0x @, +b0x A, +b0x d, +b0x g, +b0x h, +b0x r, +b0x u, +b0x v, +b0x ;- +b0x >- +b0x ?- +b0x I- +b0x L- +b0x M- +b0x p- +b0x s- +b0x t- +b0x ~- +b0x #. +b0x $. +b0x G. +b0x J. +b0x K. +b0x U. +b0x X. +b0x Y. +b0x |. +b0x !/ +b0x "/ +b0x ,/ +b0x // +b0x 0/ +b0x S/ +b0x V/ +b0x W/ +b0x a/ +b0x d/ +b0x e/ +b0x *0 +b0x -0 +b0x .0 +b0x 80 +b0x ;0 +b0x <0 +b0x _0 +b0x b0 +b0x c0 +b0x m0 +b0x p0 +b0x q0 +b0x 61 +b0x 91 +b0x :1 +b0x D1 +b0x G1 +b0x H1 +b0x k1 +b0x n1 +b0x o1 +b0x y1 +b0x |1 +b0x }1 +b0x B2 +b0x E2 +b0x F2 +b0x P2 +b0x S2 +b0x T2 +b0x w2 +b0x z2 +b0x {2 +b0x '3 +b0x *3 +b0x +3 +0E +0G +0e +0l +0z +0| +0<" +0C" +0Q" +1S" +1(# +0*# +1]# +0_# +14$ +06$ +1i$ +0k$ +1@% +0B% +1u% +0w% +1L& +0N& +1#' +0%' +1X' +0Z' +1/( +01( +1d( +0f( +1;) +0=) +1p) +0r) +1G* +0I* +1|* +0~* +1S+ +0U+ +1*, +0,, +1_, +0a, +16- +08- +1k- +0m- +1B. +0D. +1w. +0y. +1N/ +0P/ +1%0 +0'0 +1Z0 +0\0 +111 +031 +1f1 +0h1 +1=2 +0?2 +1r2 +0t2 +b101001xx l2 +b101001xx %3 +b101001xx (3 +b0x0xx n2 +b0x0xx u2 +b0x0xx x2 +b101001xx 72 +b101001xx N2 +b101001xx Q2 +b0x0xx 92 +b0x0xx @2 +b0x0xx C2 +b101001xx `1 +b101001xx w1 +b101001xx z1 +b0x0xx b1 +b0x0xx i1 +b0x0xx l1 +b101001xx +1 +b101001xx B1 +b101001xx E1 +b0x0xx -1 +b0x0xx 41 +b0x0xx 71 +b101001xx T0 +b101001xx k0 +b101001xx n0 +b0x0xx V0 +b0x0xx ]0 +b0x0xx `0 +b101001xx }/ +b101001xx 60 +b101001xx 90 +b0x0xx !0 +b0x0xx (0 +b0x0xx +0 +b101001xx H/ +b101001xx _/ +b101001xx b/ +b0x0xx J/ +b0x0xx Q/ +b0x0xx T/ +b101001xx q. +b101001xx */ +b101001xx -/ +b0x0xx s. +b0x0xx z. +b0x0xx }. +b101001xx <. +b101001xx S. +b101001xx V. +b0x0xx >. +b0x0xx E. +b0x0xx H. +b101001xx e- +b101001xx |- +b101001xx !. +b0x0xx g- +b0x0xx n- +b0x0xx q- +b101001xx 0- +b101001xx G- +b101001xx J- +b0x0xx 2- +b0x0xx 9- +b0x0xx <- +b101001xx Y, +b101001xx p, +b101001xx s, +b0x0xx [, +b0x0xx b, +b0x0xx e, +b101001xx $, +b101001xx ;, +b101001xx >, +b0x0xx &, +b0x0xx -, +b0x0xx 0, +b101001xx M+ +b101001xx d+ +b101001xx g+ +b0x0xx O+ +b0x0xx V+ +b0x0xx Y+ +b101001xx v* +b101001xx /+ +b101001xx 2+ +b0x0xx x* +b0x0xx !+ +b0x0xx $+ +b101001xx A* +b101001xx X* +b101001xx [* +b0x0xx C* +b0x0xx J* +b0x0xx M* +b101001xx j) +b101001xx #* +b101001xx &* +b0x0xx l) +b0x0xx s) +b0x0xx v) +b101001xx 5) +b101001xx L) +b101001xx O) +b0x0xx 7) +b0x0xx >) +b0x0xx A) +b101001xx ^( +b101001xx u( +b101001xx x( +b0x0xx `( +b0x0xx g( +b0x0xx j( +b101001xx )( +b101001xx @( +b101001xx C( +b0x0xx +( +b0x0xx 2( +b0x0xx 5( +b101001xx R' +b101001xx i' +b101001xx l' +b0x0xx T' +b0x0xx [' +b0x0xx ^' +b101001xx {& +b101001xx 4' +b101001xx 7' +b0x0xx }& +b0x0xx &' +b0x0xx )' +b101001xx F& +b101001xx ]& +b101001xx `& +b0x0xx H& +b0x0xx O& +b0x0xx R& +b101001xx o% +b101001xx (& +b101001xx +& +b0x0xx q% +b0x0xx x% +b0x0xx {% +b101001xx :% +b101001xx Q% +b101001xx T% +b0x0xx <% +b0x0xx C% +b0x0xx F% +b101001xx c$ +b101001xx z$ +b101001xx }$ +b0x0xx e$ +b0x0xx l$ +b0x0xx o$ +b101001xx .$ +b101001xx E$ +b101001xx H$ +b0x0xx 0$ +b0x0xx 7$ +b0x0xx :$ +b101001xx W# +b101001xx n# +b101001xx q# +b0x0xx Y# +b0x0xx `# +b0x0xx c# +b101001xx "# +b101001xx 9# +b101001xx <# +b0x0xx $# +b0x0xx +# +b0x0xx .# +b100100xx K" +b100100xx b" +b100100xx e" +b0x0xx M" +b0x0xx T" +b0x0xx W" +b0 4 +b0 A3 +b11000xx t +b11000xx -" +b11000xx 0" +b0x0xx v +b0x0xx } +b0x0xx "" +b11000xx ? +b11000xx V +b11000xx Y +b0x0xx A +b0x0xx H +b0x0xx K +#40000 +0>3 +1j +1A" +0q" +1v" +0x" +1H# +0M# +1O# +1}# +0$$ +1&$ +1T$ +0Y$ +1[$ +1+% +00% +12% +1`% +0e% +1g% +17& +0<& +1>& +1l& +0q& +1s& +1C' +0H' +1J' +1x' +0}' +1!( +1O( +0T( +1V( +1&) +0+) +1-) +1[) +0`) +1b) +12* +07* +19* +1g* +0l* +1n* +1>+ +0C+ +1E+ +1s+ +0x+ +1z+ +1J, +0O, +1Q, +1!- +0&- +1(- +1V- +0[- +1]- +1-. +02. +14. +1b. +0g. +1i. +19/ +0>/ +1@/ +1n/ +0s/ +1u/ +1E0 +0J0 +1L0 +1z0 +0!1 +1#1 +1Q1 +0V1 +1X1 +1(2 +0-2 +1/2 +1]2 +0b2 +1d2 +143 +093 +1;3 +#50000 +0J# +0!$ +0V$ +0-% +0b% +09& +0n& +0E' +0z' +0Q( +0() +0]) +04* +0i* +0@+ +0u+ +0L, +0#- +0X- +0/. +0d. +0;/ +0p/ +0G0 +0|0 +0S1 +0*2 +0_2 +063 +0?3 +#60000 +b0x R +b0 U +b0x ` +b0 c +b0x )" +b0 ," +b0x 7" +b0 :" +b0x ^" +b0 a" +b0x l" +b0 o" +b0x 5# +b0 8# +b0x C# +b0 F# +b0x j# +b0 m# +b0x x# +b0 {# +b0x A$ +b0 D$ +b0x O$ +b0 R$ +b0x v$ +b0 y$ +b0x &% +b0 )% +b0x M% +b0 P% +b0x [% +b0 ^% +b0x $& +b0 '& +b0x 2& +b0 5& +b0x Y& +b0 \& +b0x g& +b0 j& +b0x 0' +b0 3' +b0x >' +b0 A' +b0x e' +b0 h' +b0x s' +b0 v' +b0x <( +b0 ?( +b0x J( +b0 M( +b0x q( +b0 t( +b0x !) +b0 $) +b0x H) +b0 K) +b0x V) +b0 Y) +b0x }) +b0 "* +b0x -* +b0 0* +b0x T* +b0 W* +b0x b* +b0 e* +b0x ++ +b0 .+ +b0x 9+ +b0 <+ +b0x `+ +b0 c+ +b0x n+ +b0 q+ +b0x 7, +b0 :, +b0x E, +b0 H, +b0x l, +b0 o, +b0x z, +b0 }, +b0x C- +b0 F- +b0x Q- +b0 T- +b0x x- +b0 {- +b0x (. +b0 +. +b0x O. +b0 R. +b0x ]. +b0 `. +b0x &/ +b0 )/ +b0x 4/ +b0 7/ +b0x [/ +b0 ^/ +b0x i/ +b0 l/ +b0x 20 +b0 50 +b0x @0 +b0 C0 +b0x g0 +b0 j0 +b0x u0 +b0 x0 +b0x >1 +b0 A1 +b0x L1 +b0 O1 +b0x s1 +b0 v1 +b0x #2 +b0 &2 +b0x J2 +b0 M2 +b0x X2 +b0 [2 +b0x !3 +b0 $3 +b0x /3 +b0 23 +b11000x0 ? +b11000x0 V +b11000x0 Y +0D +0g +0k +0F +0{ +0R" +b0x0x1 M" +b0x0x1 T" +b0x0x1 W" +1O" +#70000 +b1100010 ? +b1100010 V +b1100010 Y +1i +1I# +0N# +b101x $# +b101x +# +b101x .# +1K# +1~# +0%$ +b101x Y# +b101x `# +b101x c# +1"$ +1U$ +0Z$ +b101x 0$ +b101x 7$ +b101x :$ +1W$ +1,% +01% +b101x e$ +b101x l$ +b101x o$ +1.% +1a% +0f% +b101x <% +b101x C% +b101x F% +1c% +18& +0=& +b101x q% +b101x x% +b101x {% +1:& +1m& +0r& +b101x H& +b101x O& +b101x R& +1o& +1D' +0I' +b101x }& +b101x &' +b101x )' +1F' +1y' +0~' +b101x T' +b101x [' +b101x ^' +1{' +1P( +0U( +b101x +( +b101x 2( +b101x 5( +1R( +1') +0,) +b101x `( +b101x g( +b101x j( +1)) +1\) +0a) +b101x 7) +b101x >) +b101x A) +1^) +13* +08* +b101x l) +b101x s) +b101x v) +15* +1h* +0m* +b101x C* +b101x J* +b101x M* +1j* +1?+ +0D+ +b101x x* +b101x !+ +b101x $+ +1A+ +1t+ +0y+ +b101x O+ +b101x V+ +b101x Y+ +1v+ +1K, +0P, +b101x &, +b101x -, +b101x 0, +1M, +1"- +0'- +b101x [, +b101x b, +b101x e, +1$- +1W- +0\- +b101x 2- +b101x 9- +b101x <- +1Y- +1.. +03. +b101x g- +b101x n- +b101x q- +10. +1c. +0h. +b101x >. +b101x E. +b101x H. +1e. +1:/ +0?/ +b101x s. +b101x z. +b101x }. +1$ +0C$ +b0x L$ +0Q$ +b0x s$ +0x$ +b0x #% +0(% +b0x J% +0O% +b0x X% +0]% +b0x !& +0&& +b0x /& +04& +b0x V& +0[& +b0x d& +0i& +b0x -' +02' +b0x ;' +0@' +b0x b' +0g' +b0x p' +0u' +b0x 9( +0>( +b0x G( +0L( +b0x n( +0s( +b0x |( +0#) +b0x E) +0J) +b0x S) +0X) +b0x z) +0!* +b0x ** +0/* +b0x Q* +0V* +b0x _* +0d* +b0x (+ +0-+ +b0x 6+ +0;+ +b0x ]+ +0b+ +b0x k+ +0p+ +b0x 4, +09, +b0x B, +0G, +b0x i, +0n, +b0x w, +0|, +b0x @- +0E- +b0x N- +0S- +b0x u- +0z- +b0x %. +0*. +b0x L. +0Q. +b0x Z. +0_. +b0x #/ +0(/ +b0x 1/ +06/ +b0x X/ +0]/ +b0x f/ +0k/ +b0x /0 +040 +b0x =0 +0B0 +b0x d0 +0i0 +b0x r0 +0w0 +b0x ;1 +0@1 +b0x I1 +0N1 +b0x p1 +0u1 +b0x ~1 +0%2 +b0x G2 +0L2 +b0x U2 +0Z2 +b0x |2 +0#3 +b0x ,3 +013 +b0 X +b0 [ +b0 \ +b1 V" +b1 Y" +b1 Z" +0f +0h +b0 A +b0 H +b0 K +0C +b0x0x0 v +b0x0x0 } +b0x0x0 "" +0x +#110000 +0- +#120000 +b0 P +b0 '" +b0 ` +b1 ^" +b0 J +b0 M +b0 N +b0 !" +b0 $" +b0 %" +#140000 +0# +#150000 +b0 R +b0 )" +b0 ] +0_ +b1 [" +1]" +#180000 +1}" +b0 O +0Q +b0 &" +0(" +bx0 2 +bx0 @3 +0@ +bx1xx0 6 +1N" +#190000 +bx1 K3 +bx1 H3 +bx1 E3 +bx1 1 +bx1 C3 +1> +#210000 +0q +0H" +0B +bx1000 6 +0w +bx0 " +bx0 3 +bx0 B3 +0'# +1)# +b10100110 "# +b10100110 9# +b10100110 <# +1L# +#240000 +b0 A# +0y +0>" +b1100010 t +b1100010 -" +b1100010 0" +1@" +0B" +0P" +0s" +b10010010 K" +b10010010 b" +b10010010 e" +1u" +0w" +b0 ;# +b0 ># +b0 ?# +b1011 $# +b1011 +# +b1011 .# +1&# +#270000 +b0 5" +b0 j" +b1 3# +b0 C# +b0 /" +b0 2" +b0 3" +b0 d" +b0 g" +b0 h" +b1 -# +b1 0# +b1 1# +0=" +b0 v +b0 } +b0 "" +0?" +0r" +b1 M" +b1 T" +b1 W" +0t" +#300000 +b0 7" +b0 l" +b1 5# +b0 @# +0B# +#330000 +b0 4" +06" +b0 i" +0k" +b1 2# +14# +bx0xx0 2 +bx0xx0 @3 +0## +#340000 +b1xx1 K3 +bx1xx1 H3 +bx1xx1 E3 +bx1xx1 1 +bx1xx1 C3 +1!# +#360000 +1T# +0u +bx0000 2 +bx0000 @3 +0L" +bx11000 6 +1%# +bx0xx0 " +bx0xx0 3 +bx0xx0 B3 +#370000 +b1111 K3 +bx1111 H3 +bx1111 E3 +1s +bx1111 1 +bx1111 C3 +1J" +#390000 +bx0000 " +bx0000 3 +bx0000 B3 +0\# +1^# +b10100110 W# +b10100110 n# +b10100110 q# +1#$ +#400000 +b11 M3 +#420000 +b0 v# +b0 p# +b0 s# +b0 t# +b1011 Y# +b1011 `# +b1011 c# +1[# +#430000 +bx1 J3 +1L3 +#450000 +b1 h# +b0 x# +b1 b# +b1 e# +b1 f# +#480000 +b1 j# +b0 u# +0w# +#510000 +b1 g# +1i# +bx00000 2 +bx00000 @3 +0X# +#520000 +bx1 N3 +bx11111 H3 +bx11111 E3 +bx11111 1 +bx11111 C3 +1V# +#540000 +1+$ +bx111000 6 +1Z# +bx00000 " +bx00000 3 +bx00000 B3 +#570000 +03$ +15$ +b10100110 .$ +b10100110 E$ +b10100110 H$ +1X$ +#600000 +b0 M$ +b0 G$ +b0 J$ +b0 K$ +b1011 0$ +b1011 7$ +b1011 :$ +12$ +#630000 +b1 ?$ +b0 O$ +b1 9$ +b1 <$ +b1 =$ +#660000 +b1 A$ +b0 L$ +0N$ +#690000 +b1 >$ +1@$ +bx000000 2 +bx000000 @3 +0/$ +#700000 +bx11 N3 +bx111111 H3 +bx111111 E3 +bx111111 1 +bx111111 C3 +1-$ +#720000 +1`$ +bx1111000 6 +11$ +bx000000 " +bx000000 3 +bx000000 B3 +#730000 +bx1 P3 +#750000 +0h$ +1j$ +b10100110 c$ +b10100110 z$ +b10100110 }$ +1/% +#780000 +b0 $% +b0 |$ +b0 !% +b0 "% +b1011 e$ +b1011 l$ +b1011 o$ +1g$ +#810000 +b1 t$ +b0 &% +b1 n$ +b1 q$ +b1 r$ +#840000 +b1 v$ +b0 #% +0%% +#870000 +b1 s$ +1u$ +bx0000000 2 +bx0000000 @3 +0d$ +#880000 +bx111 N3 +bx1111111 H3 +bx1111111 E3 +bx1111111 1 +bx1111111 C3 +1b$ +#900000 +17% +bx11111000 6 +1f$ +bx0000000 " +bx0000000 3 +bx0000000 B3 +#930000 +0?% +1A% +b10100110 :% +b10100110 Q% +b10100110 T% +1d% +#960000 +b0 Y% +b0 S% +b0 V% +b0 W% +b1011 <% +b1011 C% +b1011 F% +1>% +#990000 +b1 K% +b0 [% +b1 E% +b1 H% +b1 I% +#1020000 +b1 M% +b0 X% +0Z% +#1050000 +b1 J% +1L% +bx00000000 2 +bx00000000 @3 +0;% +#1060000 +b1111 N3 +b11111111 H3 +bx11111111 E3 +bx11111111 1 +bx11111111 C3 +19% +#1080000 +1l% +bx111111000 6 +1=% +bx00000000 " +bx00000000 3 +bx00000000 B3 +#1090000 +b11 P3 +#1110000 +0t% +1v% +b10100110 o% +b10100110 (& +b10100110 +& +1;& +#1120000 +b11 J3 +1O3 +#1140000 +b0 0& +b0 *& +b0 -& +b0 .& +b1011 q% +b1011 x% +b1011 {% +1s% +#1150000 +bx1 G3 +1I3 +#1170000 +b1 "& +b0 2& +b1 z% +b1 }% +b1 ~% +#1200000 +b1 $& +b0 /& +01& +#1230000 +b1 !& +1#& +bx000000000 2 +bx000000000 @3 +0p% +#1240000 +bx1 T3 +bx1 Q3 +bx111111111 E3 +bx111111111 1 +bx111111111 C3 +1n% +#1260000 +1C& +bx1111111000 6 +1r% +bx000000000 " +bx000000000 3 +bx000000000 B3 +#1290000 +0K& +1M& +b10100110 F& +b10100110 ]& +b10100110 `& +1p& +#1320000 +b0 e& +b0 _& +b0 b& +b0 c& +b1011 H& +b1011 O& +b1011 R& +1J& +#1350000 +b1 W& +b0 g& +b1 Q& +b1 T& +b1 U& +#1380000 +b1 Y& +b0 d& +0f& +#1410000 +b1 V& +1X& +bx0000000000 2 +bx0000000000 @3 +0G& +#1420000 +bx11 T3 +bx11 Q3 +bx1111111111 E3 +bx1111111111 1 +bx1111111111 C3 +1E& +#1440000 +1x& +bx11111111000 6 +1I& +bx0000000000 " +bx0000000000 3 +bx0000000000 B3 +#1450000 +bx1 V3 +#1470000 +0"' +1$' +b10100110 {& +b10100110 4' +b10100110 7' +1G' +#1500000 +b0 <' +b0 6' +b0 9' +b0 :' +b1011 }& +b1011 &' +b1011 )' +1!' +#1530000 +b1 .' +b0 >' +b1 (' +b1 +' +b1 ,' +#1560000 +b1 0' +b0 ;' +0=' +#1590000 +b1 -' +1/' +bx00000000000 2 +bx00000000000 @3 +0|& +#1600000 +bx111 T3 +bx111 Q3 +bx11111111111 E3 +bx11111111111 1 +bx11111111111 C3 +1z& +#1620000 +1O' +bx111111111000 6 +1~& +bx00000000000 " +bx00000000000 3 +bx00000000000 B3 +#1650000 +0W' +1Y' +b10100110 R' +b10100110 i' +b10100110 l' +1|' +#1680000 +b0 q' +b0 k' +b0 n' +b0 o' +b1011 T' +b1011 [' +b1011 ^' +1V' +#1710000 +b1 c' +b0 s' +b1 ]' +b1 `' +b1 a' +#1740000 +b1 e' +b0 p' +0r' +#1770000 +b1 b' +1d' +bx000000000000 2 +bx000000000000 @3 +0S' +#1780000 +b1111 T3 +bx1111 Q3 +bx111111111111 E3 +bx111111111111 1 +bx111111111111 C3 +1Q' +#1800000 +1&( +bx1111111111000 6 +1U' +bx000000000000 " +bx000000000000 3 +bx000000000000 B3 +#1810000 +b11 V3 +#1830000 +0.( +10( +b10100110 )( +b10100110 @( +b10100110 C( +1S( +#1840000 +bx1 S3 +1U3 +#1860000 +b0 H( +b0 B( +b0 E( +b0 F( +b1011 +( +b1011 2( +b1011 5( +1-( +#1890000 +b1 :( +b0 J( +b1 4( +b1 7( +b1 8( +#1920000 +b1 <( +b0 G( +0I( +#1950000 +b1 9( +1;( +bx0000000000000 2 +bx0000000000000 @3 +0*( +#1960000 +bx1 W3 +bx11111 Q3 +bx1111111111111 E3 +bx1111111111111 1 +bx1111111111111 C3 +1(( +#1980000 +1[( +bx11111111111000 6 +1,( +bx0000000000000 " +bx0000000000000 3 +bx0000000000000 B3 +#2010000 +0c( +1e( +b10100110 ^( +b10100110 u( +b10100110 x( +1*) +#2040000 +b0 }( +b0 w( +b0 z( +b0 {( +b1011 `( +b1011 g( +b1011 j( +1b( +#2070000 +b1 o( +b0 !) +b1 i( +b1 l( +b1 m( +#2100000 +b1 q( +b0 |( +0~( +#2130000 +b1 n( +1p( +bx00000000000000 2 +bx00000000000000 @3 +0_( +#2140000 +bx11 W3 +bx111111 Q3 +bx11111111111111 E3 +bx11111111111111 1 +bx11111111111111 C3 +1]( +#2160000 +12) +bx111111111111000 6 +1a( +bx00000000000000 " +bx00000000000000 3 +bx00000000000000 B3 +#2170000 +bx1 Y3 +#2190000 +0:) +1<) +b10100110 5) +b10100110 L) +b10100110 O) +1_) +#2220000 +b0 T) +b0 N) +b0 Q) +b0 R) +b1011 7) +b1011 >) +b1011 A) +19) +#2250000 +b1 F) +b0 V) +b1 @) +b1 C) +b1 D) +#2280000 +b1 H) +b0 S) +0U) +#2310000 +b1 E) +1G) +bx000000000000000 2 +bx000000000000000 @3 +06) +#2320000 +bx111 W3 +bx1111111 Q3 +bx111111111111111 E3 +bx111111111111111 1 +bx111111111111111 C3 +14) +#2340000 +1g) +bx1111111111111000 6 +18) +bx000000000000000 " +bx000000000000000 3 +bx000000000000000 B3 +#2370000 +0o) +1q) +b10100110 j) +b10100110 #* +b10100110 &* +16* +#2400000 +b0 +* +b0 %* +b0 (* +b0 )* +b1011 l) +b1011 s) +b1011 v) +1n) +#2430000 +b1 {) +b0 -* +b1 u) +b1 x) +b1 y) +#2460000 +b1 }) +b0 ** +0,* +#2490000 +b1 z) +1|) +bx0000000000000000 2 +bx0000000000000000 @3 +0k) +#2500000 +b1111 W3 +b11111111 Q3 +b1111111111111111 E3 +bx1111111111111111 1 +bx1111111111111111 C3 +1i) +#2520000 +1>* +bx11111111111111000 6 +1m) +bx0000000000000000 " +bx0000000000000000 3 +bx0000000000000000 B3 +#2530000 +b11 Y3 +#2550000 +0F* +1H* +b10100110 A* +b10100110 X* +b10100110 [* +1k* +#2560000 +b11 S3 +1X3 +#2580000 +b0 `* +b0 Z* +b0 ]* +b0 ^* +b1011 C* +b1011 J* +b1011 M* +1E* +#2590000 +b11 G3 +1R3 +#2610000 +b1 R* +b0 b* +b1 L* +b1 O* +b1 P* +#2620000 +bx1 D3 +1F3 +#2640000 +b1 T* +b0 _* +0a* +#2670000 +b1 Q* +1S* +bx00000000000000000 2 +bx00000000000000000 @3 +0B* +#2680000 +bx1 `3 +bx1 ]3 +bx1 Z3 +bx11111111111111111 1 +bx11111111111111111 C3 +1@* +#2700000 +1s* +bx111111111111111000 6 +1D* +bx00000000000000000 " +bx00000000000000000 3 +bx00000000000000000 B3 +#2730000 +0{* +1}* +b10100110 v* +b10100110 /+ +b10100110 2+ +1B+ +#2760000 +b0 7+ +b0 1+ +b0 4+ +b0 5+ +b1011 x* +b1011 !+ +b1011 $+ +1z* +#2790000 +b1 )+ +b0 9+ +b1 #+ +b1 &+ +b1 '+ +#2820000 +b1 ++ +b0 6+ +08+ +#2850000 +b1 (+ +1*+ +bx000000000000000000 2 +bx000000000000000000 @3 +0w* +#2860000 +bx11 `3 +bx11 ]3 +bx11 Z3 +bx111111111111111111 1 +bx111111111111111111 C3 +1u* +#2880000 +1J+ +bx1111111111111111000 6 +1y* +bx000000000000000000 " +bx000000000000000000 3 +bx000000000000000000 B3 +#2890000 +bx1 b3 +#2910000 +0R+ +1T+ +b10100110 M+ +b10100110 d+ +b10100110 g+ +1w+ +#2940000 +b0 l+ +b0 f+ +b0 i+ +b0 j+ +b1011 O+ +b1011 V+ +b1011 Y+ +1Q+ +#2970000 +b1 ^+ +b0 n+ +b1 X+ +b1 [+ +b1 \+ +#3000000 +b1 `+ +b0 k+ +0m+ +#3030000 +b1 ]+ +1_+ +bx0000000000000000000 2 +bx0000000000000000000 @3 +0N+ +#3040000 +bx111 `3 +bx111 ]3 +bx111 Z3 +bx1111111111111111111 1 +bx1111111111111111111 C3 +1L+ +#3060000 +1!, +bx11111111111111111000 6 +1P+ +bx0000000000000000000 " +bx0000000000000000000 3 +bx0000000000000000000 B3 +#3090000 +0), +1+, +b10100110 $, +b10100110 ;, +b10100110 >, +1N, +#3120000 +b0 C, +b0 =, +b0 @, +b0 A, +b1011 &, +b1011 -, +b1011 0, +1(, +#3150000 +b1 5, +b0 E, +b1 /, +b1 2, +b1 3, +#3180000 +b1 7, +b0 B, +0D, +#3210000 +b1 4, +16, +bx00000000000000000000 2 +bx00000000000000000000 @3 +0%, +#3220000 +b1111 `3 +bx1111 ]3 +bx1111 Z3 +bx11111111111111111111 1 +bx11111111111111111111 C3 +1#, +#3240000 +1V, +bx111111111111111111000 6 +1', +bx00000000000000000000 " +bx00000000000000000000 3 +bx00000000000000000000 B3 +#3250000 +b11 b3 +#3270000 +0^, +1`, +b10100110 Y, +b10100110 p, +b10100110 s, +1%- +#3280000 +bx1 _3 +1a3 +#3300000 +b0 x, +b0 r, +b0 u, +b0 v, +b1011 [, +b1011 b, +b1011 e, +1], +#3330000 +b1 j, +b0 z, +b1 d, +b1 g, +b1 h, +#3360000 +b1 l, +b0 w, +0y, +#3390000 +b1 i, +1k, +bx000000000000000000000 2 +bx000000000000000000000 @3 +0Z, +#3400000 +bx1 c3 +bx11111 ]3 +bx11111 Z3 +bx111111111111111111111 1 +bx111111111111111111111 C3 +1X, +#3420000 +1-- +bx1111111111111111111000 6 +1\, +bx000000000000000000000 " +bx000000000000000000000 3 +bx000000000000000000000 B3 +#3450000 +05- +17- +b10100110 0- +b10100110 G- +b10100110 J- +1Z- +#3480000 +b0 O- +b0 I- +b0 L- +b0 M- +b1011 2- +b1011 9- +b1011 <- +14- +#3510000 +b1 A- +b0 Q- +b1 ;- +b1 >- +b1 ?- +#3540000 +b1 C- +b0 N- +0P- +#3570000 +b1 @- +1B- +bx0000000000000000000000 2 +bx0000000000000000000000 @3 +01- +#3580000 +bx11 c3 +bx111111 ]3 +bx111111 Z3 +bx1111111111111111111111 1 +bx1111111111111111111111 C3 +1/- +#3600000 +1b- +bx11111111111111111111000 6 +13- +bx0000000000000000000000 " +bx0000000000000000000000 3 +bx0000000000000000000000 B3 +#3610000 +bx1 e3 +#3630000 +0j- +1l- +b10100110 e- +b10100110 |- +b10100110 !. +11. +#3660000 +b0 &. +b0 ~- +b0 #. +b0 $. +b1011 g- +b1011 n- +b1011 q- +1i- +#3690000 +b1 v- +b0 (. +b1 p- +b1 s- +b1 t- +#3720000 +b1 x- +b0 %. +0'. +#3750000 +b1 u- +1w- +bx00000000000000000000000 2 +bx00000000000000000000000 @3 +0f- +#3760000 +bx111 c3 +bx1111111 ]3 +bx1111111 Z3 +bx11111111111111111111111 1 +bx11111111111111111111111 C3 +1d- +#3780000 +19. +bx111111111111111111111000 6 +1h- +bx00000000000000000000000 " +bx00000000000000000000000 3 +bx00000000000000000000000 B3 +#3810000 +0A. +1C. +b10100110 <. +b10100110 S. +b10100110 V. +1f. +#3840000 +b0 [. +b0 U. +b0 X. +b0 Y. +b1011 >. +b1011 E. +b1011 H. +1@. +#3870000 +b1 M. +b0 ]. +b1 G. +b1 J. +b1 K. +#3900000 +b1 O. +b0 Z. +0\. +#3930000 +b1 L. +1N. +bx000000000000000000000000 2 +bx000000000000000000000000 @3 +0=. +#3940000 +b1111 c3 +b11111111 ]3 +bx11111111 Z3 +bx111111111111111111111111 1 +bx111111111111111111111111 C3 +1;. +#3960000 +1n. +bx1111111111111111111111000 6 +1?. +bx000000000000000000000000 " +bx000000000000000000000000 3 +bx000000000000000000000000 B3 +#3970000 +b11 e3 +#3990000 +0v. +1x. +b10100110 q. +b10100110 */ +b10100110 -/ +1=/ +#4000000 +b11 _3 +1d3 +#4020000 +b0 2/ +b0 ,/ +b0 // +b0 0/ +b1011 s. +b1011 z. +b1011 }. +1u. +#4030000 +bx1 \3 +1^3 +#4050000 +b1 $/ +b0 4/ +b1 |. +b1 !/ +b1 "/ +#4080000 +b1 &/ +b0 1/ +03/ +#4110000 +b1 #/ +1%/ +bx0000000000000000000000000 2 +bx0000000000000000000000000 @3 +0r. +#4120000 +bx1 i3 +bx1 f3 +bx111111111 Z3 +bx1111111111111111111111111 1 +bx1111111111111111111111111 C3 +1p. +#4140000 +1E/ +bx11111111111111111111111000 6 +1t. +bx0000000000000000000000000 " +bx0000000000000000000000000 3 +bx0000000000000000000000000 B3 +#4170000 +0M/ +1O/ +b10100110 H/ +b10100110 _/ +b10100110 b/ +1r/ +#4200000 +b0 g/ +b0 a/ +b0 d/ +b0 e/ +b1011 J/ +b1011 Q/ +b1011 T/ +1L/ +#4230000 +b1 Y/ +b0 i/ +b1 S/ +b1 V/ +b1 W/ +#4260000 +b1 [/ +b0 f/ +0h/ +#4290000 +b1 X/ +1Z/ +bx00000000000000000000000000 2 +bx00000000000000000000000000 @3 +0I/ +#4300000 +bx11 i3 +bx11 f3 +bx1111111111 Z3 +bx11111111111111111111111111 1 +bx11111111111111111111111111 C3 +1G/ +#4320000 +1z/ +bx111111111111111111111111000 6 +1K/ +bx00000000000000000000000000 " +bx00000000000000000000000000 3 +bx00000000000000000000000000 B3 +#4330000 +bx1 k3 +#4350000 +0$0 +1&0 +b10100110 }/ +b10100110 60 +b10100110 90 +1I0 +#4380000 +b0 >0 +b0 80 +b0 ;0 +b0 <0 +b1011 !0 +b1011 (0 +b1011 +0 +1#0 +#4410000 +b1 00 +b0 @0 +b1 *0 +b1 -0 +b1 .0 +#4440000 +b1 20 +b0 =0 +0?0 +#4470000 +b1 /0 +110 +bx000000000000000000000000000 2 +bx000000000000000000000000000 @3 +0~/ +#4480000 +bx111 i3 +bx111 f3 +bx11111111111 Z3 +bx111111111111111111111111111 1 +bx111111111111111111111111111 C3 +1|/ +#4500000 +1Q0 +bx1111111111111111111111111000 6 +1"0 +bx000000000000000000000000000 " +bx000000000000000000000000000 3 +bx000000000000000000000000000 B3 +#4530000 +0Y0 +1[0 +b10100110 T0 +b10100110 k0 +b10100110 n0 +1~0 +#4560000 +b0 s0 +b0 m0 +b0 p0 +b0 q0 +b1011 V0 +b1011 ]0 +b1011 `0 +1X0 +#4590000 +b1 e0 +b0 u0 +b1 _0 +b1 b0 +b1 c0 +#4620000 +b1 g0 +b0 r0 +0t0 +#4650000 +b1 d0 +1f0 +bx0000000000000000000000000000 2 +bx0000000000000000000000000000 @3 +0U0 +#4660000 +b1111 i3 +bx1111 f3 +bx111111111111 Z3 +bx1111111111111111111111111111 1 +bx1111111111111111111111111111 C3 +1S0 +#4680000 +1(1 +bx11111111111111111111111111000 6 +1W0 +bx0000000000000000000000000000 " +bx0000000000000000000000000000 3 +bx0000000000000000000000000000 B3 +#4690000 +b11 k3 +#4710000 +001 +121 +b10100110 +1 +b10100110 B1 +b10100110 E1 +1U1 +#4720000 +bx1 h3 +1j3 +#4740000 +b0 J1 +b0 D1 +b0 G1 +b0 H1 +b1011 -1 +b1011 41 +b1011 71 +1/1 +#4770000 +b1 <1 +b0 L1 +b1 61 +b1 91 +b1 :1 +#4800000 +b1 >1 +b0 I1 +0K1 +#4830000 +b1 ;1 +1=1 +bx00000000000000000000000000000 2 +bx00000000000000000000000000000 @3 +0,1 +#4840000 +bx1 l3 +bx11111 f3 +bx1111111111111 Z3 +bx11111111111111111111111111111 1 +bx11111111111111111111111111111 C3 +1*1 +#4860000 +1]1 +bx111111111111111111111111111000 6 +1.1 +bx00000000000000000000000000000 " +bx00000000000000000000000000000 3 +bx00000000000000000000000000000 B3 +#4890000 +0e1 +1g1 +b10100110 `1 +b10100110 w1 +b10100110 z1 +1,2 +#4920000 +b0 !2 +b0 y1 +b0 |1 +b0 }1 +b1011 b1 +b1011 i1 +b1011 l1 +1d1 +#4950000 +b1 q1 +b0 #2 +b1 k1 +b1 n1 +b1 o1 +#4980000 +b1 s1 +b0 ~1 +0"2 +#5010000 +b1 p1 +1r1 +bx000000000000000000000000000000 2 +bx000000000000000000000000000000 @3 +0a1 +#5020000 +bx11 l3 +bx111111 f3 +bx11111111111111 Z3 +bx111111111111111111111111111111 1 +bx111111111111111111111111111111 C3 +1_1 +#5040000 +142 +bx1111111111111111111111111111000 6 +1c1 +bx000000000000000000000000000000 " +bx000000000000000000000000000000 3 +bx000000000000000000000000000000 B3 +#5050000 +bx1 n3 +#5070000 +0<2 +1>2 +b10100110 72 +b10100110 N2 +b10100110 Q2 +1a2 +#5100000 +b0 V2 +b0 P2 +b0 S2 +b0 T2 +b1011 92 +b1011 @2 +b1011 C2 +1;2 +#5130000 +b1 H2 +b0 X2 +b1 B2 +b1 E2 +b1 F2 +#5160000 +b1 J2 +b0 U2 +0W2 +#5190000 +b1 G2 +1I2 +bx0000000000000000000000000000000 2 +bx0000000000000000000000000000000 @3 +082 +#5200000 +bx111 l3 +bx1111111 f3 +bx111111111111111 Z3 +bx1111111111111111111111111111111 1 +bx1111111111111111111111111111111 C3 +162 +#5220000 +1i2 +bx11111111111111111111111111111000 6 +1:2 +bx0000000000000000000000000000000 " +bx0000000000000000000000000000000 3 +bx0000000000000000000000000000000 B3 +#5250000 +0q2 +1s2 +b10100110 l2 +b10100110 %3 +b10100110 (3 +183 +#5280000 +b0 -3 +b0 '3 +b0 *3 +b0 +3 +b1011 n2 +b1011 u2 +b1011 x2 +1p2 +#5310000 +b1 }2 +b0 /3 +b1 w2 +b1 z2 +b1 {2 +#5340000 +b1 !3 +b0 ,3 +0.3 +#5370000 +b1 |2 +1~2 +b0 2 +b0 @3 +0m2 +#5380000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1k2 +#5400000 +b111111111111111111111111111111000 6 +1o2 +b0 " +b0 3 +b0 B3 +#5410000 +b11 n3 +#5430000 +1$ +#5440000 +b11 h3 +1m3 +#5460000 +1. +00 +#5470000 +b11 \3 +1g3 +#5500000 +b11 D3 +1[3 +#5530000 +1! +#1000000000 +1: +0F" +18 +1m +0e2 +b1 & +b1 , +b1111111111111111111111111111111 % +b1111111111111111111111111111111 + +#1000010000 +0; +1G" +09 +0n +1f2 +#1000020000 +b10110010 K" +b10110010 b" +b10110010 e" +0p" +b10 ? +b10 V +b10 Y +b100010 t +b100010 -" +b100010 0" +0;" +b11100110 l2 +b11100110 %3 +b11100110 (3 +133 +1/ +#1000030000 +0* +b10100110 K" +b10100110 b" +b10100110 e" +1Q" +0S" +b10010010 ? +b10010010 V +b10010010 Y +1G +b10100110 t +b10100110 -" +b10100110 0" +1z +1<" +0A" +1C" +b1100010 l2 +b1100010 %3 +b1100010 (3 +0r2 +043 +193 +0;3 +#1000040000 +1q" +0v" +1x" +#1000050000 +163 +1?3 +#1000060000 +10 +b10100111 K" +b10100111 b" +b10100111 e" +1P" +b0 M" +b0 T" +b0 W" +0O" +b1 A +b1 H +b1 K +1C +1y +1=" +b10100101 t +b10100101 -" +b10100101 0" +0@" +b1010 v +b1010 } +b1010 "" +1?" +1q2 +0s2 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +b1001 n2 +b1001 u2 +b1001 x2 +073 +#1000070000 +1r" +b10100101 K" +b10100101 b" +b10100101 e" +0u" +b1010 M" +b1010 T" +b1010 W" +1t" +#1000080000 +15 +#1000090000 +b1 j" +b0 \" +b1 P +b1 5" +b1 -3 +b1 d" +b1 g" +b1 h" +b0 V" +b0 Y" +b0 Z" +b1 J +b1 M +b1 N +b1 /" +b1 2" +b1 3" +b1 '3 +b1 *3 +b1 +3 +0p2 +b1010 n2 +b1010 u2 +b1010 x2 +173 +#1000110000 +1- +#1000120000 +b0 }2 +b1 l" +b0 ^" +b1 R +b1 7" +b1 /3 +b0 w2 +b0 z2 +b0 {2 +#1000140000 +1# +#1000150000 +b0 !3 +b1 i" +1k" +b0 [" +0]" +b1 O +1Q +b1 4" +16" +b1 ,3 +1.3 +#1000180000 +0}" +1q +b0 |2 +0~2 +1L" +0N" +b111111111111111111111111111110010 6 +1B +1u +b10000000000000000000000000000110 2 +b10000000000000000000000000000110 @3 +1m2 +#1000190000 +b1001 K3 +b111 l3 +b11111001 H3 +b1111111 f3 +b1111111111111001 E3 +b111111111111111 Z3 +0J" +0s +b1111111111111111111111111111001 1 +b1111111111111111111111111111001 C3 +0k2 +#1000210000 +b11111111111111111111111111110010 6 +0o2 +1'# +0)# +b10100101 "# +b10100101 9# +b10100101 <# +0L# +0y +1{ +b10100110 t +b10100110 -" +b10100110 0" +1@" +b10000000000000000000000000000110 " +b10000000000000000000000000000110 3 +b10000000000000000000000000000110 B3 +#1000220000 +b0 M3 +b1 n3 +#1000240000 +b1 A# +b0 5" +0$ +b1 ;# +b1 ># +b1 ?# +b0 /" +b0 2" +b0 3" +0. +b1010 $# +b1010 +# +b1010 .# +0&# +b1011 v +b1011 } +b1011 "" +1x +#1000250000 +b10 J3 +0L3 +b1 h3 +0m3 +#1000270000 +b0 3# +b1 '" +b1 C# +b0 7" +b0 -# +b0 0# +b0 1# +b1 !" +b1 $" +b1 %" +1. +00 +0- +#1000280000 +b10 G3 +0I3 +b1 \3 +0g3 +#1000300000 +b0 5# +b1 )" +b1 @# +1B# +b0 4" +06" +1- +0# +#1000310000 +0F3 +b0 D3 +0[3 +#1000330000 +b0 2# +04# +b1 &" +1(" +1## +b10000000000000000000000000001100 2 +b10000000000000000000000000001100 @3 +0u +1# +#1000340000 +b11 K3 +b11110011 H3 +b1111111111110011 E3 +0!# +b1111111111111111111111111110011 1 +b1111111111111111111111111110011 C3 +1s +0! +#1000360000 +0T# +1H" +0%# +b11111111111111111111111111100110 6 +1w +b10000000000000000000000000001100 " +b10000000000000000000000000001100 3 +b10000000000000000000000000001100 B3 +#1000370000 +b1 M3 +#1000390000 +1\# +0^# +b10100101 W# +b10100101 n# +b10100101 q# +0#$ +0P" +1R" +b10100110 K" +b10100110 b" +b10100110 e" +1u" +#1000420000 +b1 v# +b0 j" +b1 p# +b1 s# +b1 t# +b0 d" +b0 g" +b0 h" +b1010 Y# +b1010 `# +b1010 c# +0[# +b1011 M" +b1011 T" +b1011 W" +1O" +#1000450000 +b0 h# +b1 \" +b1 x# +b0 l" +b0 b# +b0 e# +b0 f# +b1 V" +b1 Y" +b1 Z" +#1000480000 +b0 j# +b1 ^" +b1 u# +1w# +b0 i" +0k" +#1000510000 +b0 g# +0i# +b1 [" +1]" +1X# +b10000000000000000000000000011000 2 +b10000000000000000000000000011000 @3 +0L" +#1000520000 +b111 K3 +b1110 N3 +b11100111 H3 +b1111111111100111 E3 +0V# +b1111111111111111111111111100111 1 +b1111111111111111111111111100111 C3 +1J" +#1000540000 +0+$ +1}" +0Z# +b11111111111111111111111111001110 6 +1N" +b10000000000000000000000000011000 " +b10000000000000000000000000011000 3 +b10000000000000000000000000011000 B3 +#1000550000 +b10 P3 +#1000570000 +13$ +05$ +b10100101 .$ +b10100101 E$ +b10100101 H$ +0X$ +0'# +1)# +b10100110 "# +b10100110 9# +b10100110 <# +1L# +#1000580000 +b0 J3 +0O3 +#1000600000 +b1 M$ +b0 A# +b1 G$ +b1 J$ +b1 K$ +b0 ;# +b0 ># +b0 ?# +b1010 0$ +b1010 7$ +b1010 :$ +02$ +b1011 $# +b1011 +# +b1011 .# +1&# +#1000630000 +b0 ?$ +b1 3# +b1 O$ +b0 C# +b0 9$ +b0 <$ +b0 =$ +b1 -# +b1 0# +b1 1# +#1000660000 +b0 A$ +b1 5# +b1 L$ +1N$ +b0 @# +0B# +#1000690000 +b0 >$ +0@$ +b1 2# +14# +1/$ +b10000000000000000000000000110000 2 +b10000000000000000000000000110000 @3 +0## +#1000700000 +b1111 K3 +b1100 N3 +b11001111 H3 +b1111111111001111 E3 +0-$ +b1111111111111111111111111001111 1 +b1111111111111111111111111001111 C3 +1!# +#1000720000 +0`$ +1T# +01$ +b11111111111111111111111110011110 6 +1%# +b10000000000000000000000000110000 " +b10000000000000000000000000110000 3 +b10000000000000000000000000110000 B3 +#1000730000 +b11 M3 +#1000750000 +1h$ +0j$ +b10100101 c$ +b10100101 z$ +b10100101 }$ +0/% +0\# +1^# +b10100110 W# +b10100110 n# +b10100110 q# +1#$ +#1000760000 +b1 J3 +1L3 +#1000780000 +b1 $% +b0 v# +b1 |$ +b1 !% +b1 "% +b0 p# +b0 s# +b0 t# +b1010 e$ +b1010 l$ +b1010 o$ +0g$ +b1011 Y# +b1011 `# +b1011 c# +1[# +#1000810000 +b0 t$ +b1 h# +b1 &% +b0 x# +b0 n$ +b0 q$ +b0 r$ +b1 b# +b1 e# +b1 f# +#1000840000 +b0 v$ +b1 j# +b1 #% +1%% +b0 u# +0w# +#1000870000 +b0 s$ +0u$ +b1 g# +1i# +1d$ +b10000000000000000000000001100000 2 +b10000000000000000000000001100000 @3 +0X# +#1000880000 +b1001 N3 +b10011111 H3 +b1111111110011111 E3 +0b$ +b1111111111111111111111110011111 1 +b1111111111111111111111110011111 C3 +1V# +#1000900000 +07% +1+$ +0f$ +b11111111111111111111111100111110 6 +1Z# +b10000000000000000000000001100000 " +b10000000000000000000000001100000 3 +b10000000000000000000000001100000 B3 +#1000910000 +b0 P3 +#1000930000 +1?% +0A% +b10100101 :% +b10100101 Q% +b10100101 T% +0d% +03$ +15$ +b10100110 .$ +b10100110 E$ +b10100110 H$ +1X$ +#1000960000 +b1 Y% +b0 M$ +b1 S% +b1 V% +b1 W% +b0 G$ +b0 J$ +b0 K$ +b1010 <% +b1010 C% +b1010 F% +0>% +b1011 0$ +b1011 7$ +b1011 :$ +12$ +#1000990000 +b0 K% +b1 ?$ +b1 [% +b0 O$ +b0 E% +b0 H% +b0 I% +b1 9$ +b1 <$ +b1 =$ +#1001020000 +b0 M% +b1 A$ +b1 X% +1Z% +b0 L$ +0N$ +#1001050000 +b0 J% +0L% +b1 >$ +1@$ +1;% +b10000000000000000000000011000000 2 +b10000000000000000000000011000000 @3 +0/$ +#1001060000 +b11 N3 +b111111 H3 +b1111111100111111 E3 +09% +b1111111111111111111111100111111 1 +b1111111111111111111111100111111 C3 +1-$ +#1001080000 +0l% +1`$ +0=% +b11111111111111111111111001111110 6 +11$ +b10000000000000000000000011000000 " +b10000000000000000000000011000000 3 +b10000000000000000000000011000000 B3 +#1001090000 +b1 P3 +#1001110000 +1t% +0v% +b10100101 o% +b10100101 (& +b10100101 +& +0;& +0h$ +1j$ +b10100110 c$ +b10100110 z$ +b10100110 }$ +1/% +#1001140000 +b1 0& +b0 $% +b1 *& +b1 -& +b1 .& +b0 |$ +b0 !% +b0 "% +b1010 q% +b1010 x% +b1010 {% +0s% +b1011 e$ +b1011 l$ +b1011 o$ +1g$ +#1001170000 +b0 "& +b1 t$ +b1 2& +b0 &% +b0 z% +b0 }% +b0 ~% +b1 n$ +b1 q$ +b1 r$ +#1001200000 +b0 $& +b1 v$ +b1 /& +11& +b0 #% +0%% +#1001230000 +b0 !& +0#& +b1 s$ +1u$ +1p% +b10000000000000000000000110000000 2 +b10000000000000000000000110000000 @3 +0d$ +#1001240000 +b111 N3 +b1110 T3 +b1111111 H3 +b11111110 Q3 +b1111111001111111 E3 +0n% +b1111111111111111111111001111111 1 +b1111111111111111111111001111111 C3 +1b$ +#1001260000 +0C& +17% +0r% +b11111111111111111111110011111110 6 +1f$ +b10000000000000000000000110000000 " +b10000000000000000000000110000000 3 +b10000000000000000000000110000000 B3 +#1001270000 +b10 V3 +#1001290000 +1K& +0M& +b10100101 F& +b10100101 ]& +b10100101 `& +0p& +0?% +1A% +b10100110 :% +b10100110 Q% +b10100110 T% +1d% +#1001300000 +b10 S3 +0U3 +#1001320000 +b1 e& +b0 Y% +b1 _& +b1 b& +b1 c& +b0 S% +b0 V% +b0 W% +b1010 H& +b1010 O& +b1010 R& +0J& +b1011 <% +b1011 C% +b1011 F% +1>% +#1001330000 +b0 G3 +0R3 +#1001350000 +b0 W& +b1 K% +b1 g& +b0 [% +b0 Q& +b0 T& +b0 U& +b1 E% +b1 H% +b1 I% +#1001380000 +b0 Y& +b1 M% +b1 d& +1f& +b0 X% +0Z% +#1001410000 +b0 V& +0X& +b1 J% +1L% +1G& +b10000000000000000000001100000000 2 +b10000000000000000000001100000000 @3 +0;% +#1001420000 +b1111 N3 +b1100 T3 +b11111111 H3 +b11111100 Q3 +b1111110011111111 E3 +0E& +b1111111111111111111110011111111 1 +b1111111111111111111110011111111 C3 +19% +#1001440000 +0x& +1l% +0I& +b11111111111111111111100111111110 6 +1=% +b10000000000000000000001100000000 " +b10000000000000000000001100000000 3 +b10000000000000000000001100000000 B3 +#1001450000 +b11 P3 +#1001470000 +1"' +0$' +b10100101 {& +b10100101 4' +b10100101 7' +0G' +0t% +1v% +b10100110 o% +b10100110 (& +b10100110 +& +1;& +#1001480000 +b11 J3 +1O3 +#1001500000 +b1 <' +b0 0& +b1 6' +b1 9' +b1 :' +b0 *& +b0 -& +b0 .& +b1010 }& +b1010 &' +b1010 )' +0!' +b1011 q% +b1011 x% +b1011 {% +1s% +#1001510000 +b1 G3 +1I3 +#1001530000 +b0 .' +b1 "& +b1 >' +b0 2& +b0 (' +b0 +' +b0 ,' +b1 z% +b1 }% +b1 ~% +#1001560000 +b0 0' +b1 $& +b1 ;' +1=' +b0 /& +01& +#1001590000 +b0 -' +0/' +b1 !& +1#& +1|& +b10000000000000000000011000000000 2 +b10000000000000000000011000000000 @3 +0p% +#1001600000 +b1001 T3 +b11111001 Q3 +b1111100111111111 E3 +0z& +b1111111111111111111100111111111 1 +b1111111111111111111100111111111 C3 +1n% +#1001620000 +0O' +1C& +0~& +b11111111111111111111001111111110 6 +1r% +b10000000000000000000011000000000 " +b10000000000000000000011000000000 3 +b10000000000000000000011000000000 B3 +#1001630000 +b0 V3 +#1001650000 +1W' +0Y' +b10100101 R' +b10100101 i' +b10100101 l' +0|' +0K& +1M& +b10100110 F& +b10100110 ]& +b10100110 `& +1p& +#1001680000 +b1 q' +b0 e& +b1 k' +b1 n' +b1 o' +b0 _& +b0 b& +b0 c& +b1010 T' +b1010 [' +b1010 ^' +0V' +b1011 H& +b1011 O& +b1011 R& +1J& +#1001710000 +b0 c' +b1 W& +b1 s' +b0 g& +b0 ]' +b0 `' +b0 a' +b1 Q& +b1 T& +b1 U& +#1001740000 +b0 e' +b1 Y& +b1 p' +1r' +b0 d& +0f& +#1001770000 +b0 b' +0d' +b1 V& +1X& +1S' +b10000000000000000000110000000000 2 +b10000000000000000000110000000000 @3 +0G& +#1001780000 +b11 T3 +b11110011 Q3 +b1111001111111111 E3 +0Q' +b1111111111111111111001111111111 1 +b1111111111111111111001111111111 C3 +1E& +#1001800000 +0&( +1x& +0U' +b11111111111111111110011111111110 6 +1I& +b10000000000000000000110000000000 " +b10000000000000000000110000000000 3 +b10000000000000000000110000000000 B3 +#1001810000 +b1 V3 +#1001830000 +1.( +00( +b10100101 )( +b10100101 @( +b10100101 C( +0S( +0"' +1$' +b10100110 {& +b10100110 4' +b10100110 7' +1G' +#1001860000 +b1 H( +b0 <' +b1 B( +b1 E( +b1 F( +b0 6' +b0 9' +b0 :' +b1010 +( +b1010 2( +b1010 5( +0-( +b1011 }& +b1011 &' +b1011 )' +1!' +#1001890000 +b0 :( +b1 .' +b1 J( +b0 >' +b0 4( +b0 7( +b0 8( +b1 (' +b1 +' +b1 ,' +#1001920000 +b0 <( +b1 0' +b1 G( +1I( +b0 ;' +0=' +#1001950000 +b0 9( +0;( +b1 -' +1/' +1*( +b10000000000000000001100000000000 2 +b10000000000000000001100000000000 @3 +0|& +#1001960000 +b111 T3 +b1110 W3 +b11100111 Q3 +b1110011111111111 E3 +0(( +b1111111111111111110011111111111 1 +b1111111111111111110011111111111 C3 +1z& +#1001980000 +0[( +1O' +0,( +b11111111111111111100111111111110 6 +1~& +b10000000000000000001100000000000 " +b10000000000000000001100000000000 3 +b10000000000000000001100000000000 B3 +#1001990000 +b10 Y3 +#1002010000 +1c( +0e( +b10100101 ^( +b10100101 u( +b10100101 x( +0*) +0W' +1Y' +b10100110 R' +b10100110 i' +b10100110 l' +1|' +#1002020000 +b0 S3 +0X3 +#1002040000 +b1 }( +b0 q' +b1 w( +b1 z( +b1 {( +b0 k' +b0 n' +b0 o' +b1010 `( +b1010 g( +b1010 j( +0b( +b1011 T' +b1011 [' +b1011 ^' +1V' +#1002070000 +b0 o( +b1 c' +b1 !) +b0 s' +b0 i( +b0 l( +b0 m( +b1 ]' +b1 `' +b1 a' +#1002100000 +b0 q( +b1 e' +b1 |( +1~( +b0 p' +0r' +#1002130000 +b0 n( +0p( +b1 b' +1d' +1_( +b10000000000000000011000000000000 2 +b10000000000000000011000000000000 @3 +0S' +#1002140000 +b1111 T3 +b1100 W3 +b11001111 Q3 +b1100111111111111 E3 +0]( +b1111111111111111100111111111111 1 +b1111111111111111100111111111111 C3 +1Q' +#1002160000 +02) +1&( +0a( +b11111111111111111001111111111110 6 +1U' +b10000000000000000011000000000000 " +b10000000000000000011000000000000 3 +b10000000000000000011000000000000 B3 +#1002170000 +b11 V3 +#1002190000 +1:) +0<) +b10100101 5) +b10100101 L) +b10100101 O) +0_) +0.( +10( +b10100110 )( +b10100110 @( +b10100110 C( +1S( +#1002200000 +b1 S3 +1U3 +#1002220000 +b1 T) +b0 H( +b1 N) +b1 Q) +b1 R) +b0 B( +b0 E( +b0 F( +b1010 7) +b1010 >) +b1010 A) +09) +b1011 +( +b1011 2( +b1011 5( +1-( +#1002250000 +b0 F) +b1 :( +b1 V) +b0 J( +b0 @) +b0 C) +b0 D) +b1 4( +b1 7( +b1 8( +#1002280000 +b0 H) +b1 <( +b1 S) +1U) +b0 G( +0I( +#1002310000 +b0 E) +0G) +b1 9( +1;( +16) +b10000000000000000110000000000000 2 +b10000000000000000110000000000000 @3 +0*( +#1002320000 +b1001 W3 +b10011111 Q3 +b1001111111111111 E3 +04) +b1111111111111111001111111111111 1 +b1111111111111111001111111111111 C3 +1(( +#1002340000 +0g) +1[( +08) +b11111111111111110011111111111110 6 +1,( +b10000000000000000110000000000000 " +b10000000000000000110000000000000 3 +b10000000000000000110000000000000 B3 +#1002350000 +b0 Y3 +#1002370000 +1o) +0q) +b10100101 j) +b10100101 #* +b10100101 &* +06* +0c( +1e( +b10100110 ^( +b10100110 u( +b10100110 x( +1*) +#1002400000 +b1 +* +b0 }( +b1 %* +b1 (* +b1 )* +b0 w( +b0 z( +b0 {( +b1010 l) +b1010 s) +b1010 v) +0n) +b1011 `( +b1011 g( +b1011 j( +1b( +#1002430000 +b0 {) +b1 o( +b1 -* +b0 !) +b0 u) +b0 x) +b0 y) +b1 i( +b1 l( +b1 m( +#1002460000 +b0 }) +b1 q( +b1 ** +1,* +b0 |( +0~( +#1002490000 +b0 z) +0|) +b1 n( +1p( +1k) +b10000000000000001100000000000000 2 +b10000000000000001100000000000000 @3 +0_( +#1002500000 +b11 W3 +b111111 Q3 +b11111111111111 E3 +0i) +b1111111111111110011111111111111 1 +b1111111111111110011111111111111 C3 +1]( +#1002520000 +0>* +12) +0m) +b11111111111111100111111111111110 6 +1a( +b10000000000000001100000000000000 " +b10000000000000001100000000000000 3 +b10000000000000001100000000000000 B3 +#1002530000 +b1 Y3 +#1002550000 +1F* +0H* +b10100101 A* +b10100101 X* +b10100101 [* +0k* +0:) +1<) +b10100110 5) +b10100110 L) +b10100110 O) +1_) +#1002580000 +b1 `* +b0 T) +b1 Z* +b1 ]* +b1 ^* +b0 N) +b0 Q) +b0 R) +b1010 C* +b1010 J* +b1010 M* +0E* +b1011 7) +b1011 >) +b1011 A) +19) +#1002610000 +b0 R* +b1 F) +b1 b* +b0 V) +b0 L* +b0 O* +b0 P* +b1 @) +b1 C) +b1 D) +#1002640000 +b0 T* +b1 H) +b1 _* +1a* +b0 S) +0U) +#1002670000 +b0 Q* +0S* +b1 E) +1G) +1B* +b10000000000000011000000000000000 2 +b10000000000000011000000000000000 @3 +06) +#1002680000 +b1110 `3 +b111 W3 +b11111110 ]3 +b1111111 Q3 +b111111111111110 Z3 +b111111111111111 E3 +0@* +b1111111111111100111111111111111 1 +b1111111111111100111111111111111 C3 +14) +#1002700000 +0s* +1g) +0D* +b11111111111111001111111111111110 6 +18) +b10000000000000011000000000000000 " +b10000000000000011000000000000000 3 +b10000000000000011000000000000000 B3 +#1002710000 +b10 b3 +#1002730000 +1{* +0}* +b10100101 v* +b10100101 /+ +b10100101 2+ +0B+ +0o) +1q) +b10100110 j) +b10100110 #* +b10100110 &* +16* +#1002740000 +b10 _3 +0a3 +#1002760000 +b1 7+ +b0 +* +b1 1+ +b1 4+ +b1 5+ +b0 %* +b0 (* +b0 )* +b1010 x* +b1010 !+ +b1010 $+ +0z* +b1011 l) +b1011 s) +b1011 v) +1n) +#1002770000 +b0 \3 +0^3 +#1002790000 +b0 )+ +b1 {) +b1 9+ +b0 -* +b0 #+ +b0 &+ +b0 '+ +b1 u) +b1 x) +b1 y) +#1002820000 +b0 ++ +b1 }) +b1 6+ +18+ +b0 ** +0,* +#1002850000 +b0 (+ +0*+ +b1 z) +1|) +1w* +b10000000000000110000000000000000 2 +b10000000000000110000000000000000 @3 +0k) +#1002860000 +b1100 `3 +b1111 W3 +b11111100 ]3 +b11111111 Q3 +b111111111111100 Z3 +b1111111111111111 E3 +0u* +b1111111111111001111111111111111 1 +b1111111111111001111111111111111 C3 +1i) +#1002880000 +0J+ +1>* +0y* +b11111111111110011111111111111110 6 +1m) +b10000000000000110000000000000000 " +b10000000000000110000000000000000 3 +b10000000000000110000000000000000 B3 +#1002890000 +b11 Y3 +#1002910000 +1R+ +0T+ +b10100101 M+ +b10100101 d+ +b10100101 g+ +0w+ +0F* +1H* +b10100110 A* +b10100110 X* +b10100110 [* +1k* +#1002920000 +b11 S3 +1X3 +#1002940000 +b1 l+ +b0 `* +b1 f+ +b1 i+ +b1 j+ +b0 Z* +b0 ]* +b0 ^* +b1010 O+ +b1010 V+ +b1010 Y+ +0Q+ +b1011 C* +b1011 J* +b1011 M* +1E* +#1002950000 +b11 G3 +1R3 +#1002970000 +b0 ^+ +b1 R* +b1 n+ +b0 b* +b0 X+ +b0 [+ +b0 \+ +b1 L* +b1 O* +b1 P* +#1002980000 +b1 D3 +1F3 +#1003000000 +b0 `+ +b1 T* +b1 k+ +1m+ +b0 _* +0a* +#1003030000 +b0 ]+ +0_+ +b1 Q* +1S* +1N+ +b10000000000001100000000000000000 2 +b10000000000001100000000000000000 @3 +0B* +#1003040000 +b1001 `3 +b11111001 ]3 +b111111111111001 Z3 +0L+ +b1111111111110011111111111111111 1 +b1111111111110011111111111111111 C3 +1@* +#1003060000 +0!, +1s* +0P+ +b11111111111100111111111111111110 6 +1D* +b10000000000001100000000000000000 " +b10000000000001100000000000000000 3 +b10000000000001100000000000000000 B3 +#1003070000 +b0 b3 +#1003090000 +1), +0+, +b10100101 $, +b10100101 ;, +b10100101 >, +0N, +0{* +1}* +b10100110 v* +b10100110 /+ +b10100110 2+ +1B+ +#1003120000 +b1 C, +b0 7+ +b1 =, +b1 @, +b1 A, +b0 1+ +b0 4+ +b0 5+ +b1010 &, +b1010 -, +b1010 0, +0(, +b1011 x* +b1011 !+ +b1011 $+ +1z* +#1003150000 +b0 5, +b1 )+ +b1 E, +b0 9+ +b0 /, +b0 2, +b0 3, +b1 #+ +b1 &+ +b1 '+ +#1003180000 +b0 7, +b1 ++ +b1 B, +1D, +b0 6+ +08+ +#1003210000 +b0 4, +06, +b1 (+ +1*+ +1%, +b10000000000011000000000000000000 2 +b10000000000011000000000000000000 @3 +0w* +#1003220000 +b11 `3 +b11110011 ]3 +b111111111110011 Z3 +0#, +b1111111111100111111111111111111 1 +b1111111111100111111111111111111 C3 +1u* +#1003240000 +0V, +1J+ +0', +b11111111111001111111111111111110 6 +1y* +b10000000000011000000000000000000 " +b10000000000011000000000000000000 3 +b10000000000011000000000000000000 B3 +#1003250000 +b1 b3 +#1003270000 +1^, +0`, +b10100101 Y, +b10100101 p, +b10100101 s, +0%- +0R+ +1T+ +b10100110 M+ +b10100110 d+ +b10100110 g+ +1w+ +#1003300000 +b1 x, +b0 l+ +b1 r, +b1 u, +b1 v, +b0 f+ +b0 i+ +b0 j+ +b1010 [, +b1010 b, +b1010 e, +0], +b1011 O+ +b1011 V+ +b1011 Y+ +1Q+ +#1003330000 +b0 j, +b1 ^+ +b1 z, +b0 n+ +b0 d, +b0 g, +b0 h, +b1 X+ +b1 [+ +b1 \+ +#1003360000 +b0 l, +b1 `+ +b1 w, +1y, +b0 k+ +0m+ +#1003390000 +b0 i, +0k, +b1 ]+ +1_+ +1Z, +b10000000000110000000000000000000 2 +b10000000000110000000000000000000 @3 +0N+ +#1003400000 +b111 `3 +b1110 c3 +b11100111 ]3 +b111111111100111 Z3 +0X, +b1111111111001111111111111111111 1 +b1111111111001111111111111111111 C3 +1L+ +#1003420000 +0-- +1!, +0\, +b11111111110011111111111111111110 6 +1P+ +b10000000000110000000000000000000 " +b10000000000110000000000000000000 3 +b10000000000110000000000000000000 B3 +#1003430000 +b10 e3 +#1003450000 +15- +07- +b10100101 0- +b10100101 G- +b10100101 J- +0Z- +0), +1+, +b10100110 $, +b10100110 ;, +b10100110 >, +1N, +#1003460000 +b0 _3 +0d3 +#1003480000 +b1 O- +b0 C, +b1 I- +b1 L- +b1 M- +b0 =, +b0 @, +b0 A, +b1010 2- +b1010 9- +b1010 <- +04- +b1011 &, +b1011 -, +b1011 0, +1(, +#1003510000 +b0 A- +b1 5, +b1 Q- +b0 E, +b0 ;- +b0 >- +b0 ?- +b1 /, +b1 2, +b1 3, +#1003540000 +b0 C- +b1 7, +b1 N- +1P- +b0 B, +0D, +#1003570000 +b0 @- +0B- +b1 4, +16, +11- +b10000000001100000000000000000000 2 +b10000000001100000000000000000000 @3 +0%, +#1003580000 +b1111 `3 +b1100 c3 +b11001111 ]3 +b111111111001111 Z3 +0/- +b1111111110011111111111111111111 1 +b1111111110011111111111111111111 C3 +1#, +#1003600000 +0b- +1V, +03- +b11111111100111111111111111111110 6 +1', +b10000000001100000000000000000000 " +b10000000001100000000000000000000 3 +b10000000001100000000000000000000 B3 +#1003610000 +b11 b3 +#1003630000 +1j- +0l- +b10100101 e- +b10100101 |- +b10100101 !. +01. +0^, +1`, +b10100110 Y, +b10100110 p, +b10100110 s, +1%- +#1003640000 +b1 _3 +1a3 +#1003660000 +b1 &. +b0 x, +b1 ~- +b1 #. +b1 $. +b0 r, +b0 u, +b0 v, +b1010 g- +b1010 n- +b1010 q- +0i- +b1011 [, +b1011 b, +b1011 e, +1], +#1003690000 +b0 v- +b1 j, +b1 (. +b0 z, +b0 p- +b0 s- +b0 t- +b1 d, +b1 g, +b1 h, +#1003720000 +b0 x- +b1 l, +b1 %. +1'. +b0 w, +0y, +#1003750000 +b0 u- +0w- +b1 i, +1k, +1f- +b10000000011000000000000000000000 2 +b10000000011000000000000000000000 @3 +0Z, +#1003760000 +b1001 c3 +b10011111 ]3 +b111111110011111 Z3 +0d- +b1111111100111111111111111111111 1 +b1111111100111111111111111111111 C3 +1X, +#1003780000 +09. +1-- +0h- +b11111111001111111111111111111110 6 +1\, +b10000000011000000000000000000000 " +b10000000011000000000000000000000 3 +b10000000011000000000000000000000 B3 +#1003790000 +b0 e3 +#1003810000 +1A. +0C. +b10100101 <. +b10100101 S. +b10100101 V. +0f. +05- +17- +b10100110 0- +b10100110 G- +b10100110 J- +1Z- +#1003840000 +b1 [. +b0 O- +b1 U. +b1 X. +b1 Y. +b0 I- +b0 L- +b0 M- +b1010 >. +b1010 E. +b1010 H. +0@. +b1011 2- +b1011 9- +b1011 <- +14- +#1003870000 +b0 M. +b1 A- +b1 ]. +b0 Q- +b0 G. +b0 J. +b0 K. +b1 ;- +b1 >- +b1 ?- +#1003900000 +b0 O. +b1 C- +b1 Z. +1\. +b0 N- +0P- +#1003930000 +b0 L. +0N. +b1 @- +1B- +1=. +b10000000110000000000000000000000 2 +b10000000110000000000000000000000 @3 +01- +#1003940000 +b11 c3 +b111111 ]3 +b111111100111111 Z3 +0;. +b1111111001111111111111111111111 1 +b1111111001111111111111111111111 C3 +1/- +#1003960000 +0n. +1b- +0?. +b11111110011111111111111111111110 6 +13- +b10000000110000000000000000000000 " +b10000000110000000000000000000000 3 +b10000000110000000000000000000000 B3 +#1003970000 +b1 e3 +#1003990000 +1v. +0x. +b10100101 q. +b10100101 */ +b10100101 -/ +0=/ +0j- +1l- +b10100110 e- +b10100110 |- +b10100110 !. +11. +#1004020000 +b1 2/ +b0 &. +b1 ,/ +b1 // +b1 0/ +b0 ~- +b0 #. +b0 $. +b1010 s. +b1010 z. +b1010 }. +0u. +b1011 g- +b1011 n- +b1011 q- +1i- +#1004050000 +b0 $/ +b1 v- +b1 4/ +b0 (. +b0 |. +b0 !/ +b0 "/ +b1 p- +b1 s- +b1 t- +#1004080000 +b0 &/ +b1 x- +b1 1/ +13/ +b0 %. +0'. +#1004110000 +b0 #/ +0%/ +b1 u- +1w- +1r. +b10000001100000000000000000000000 2 +b10000001100000000000000000000000 @3 +0f- +#1004120000 +b111 c3 +b1110 i3 +b1111111 ]3 +b1111110 f3 +b111111001111111 Z3 +0p. +b1111110011111111111111111111111 1 +b1111110011111111111111111111111 C3 +1d- +#1004140000 +0E/ +19. +0t. +b11111100111111111111111111111110 6 +1h- +b10000001100000000000000000000000 " +b10000001100000000000000000000000 3 +b10000001100000000000000000000000 B3 +#1004150000 +b10 k3 +#1004170000 +1M/ +0O/ +b10100101 H/ +b10100101 _/ +b10100101 b/ +0r/ +0A. +1C. +b10100110 <. +b10100110 S. +b10100110 V. +1f. +#1004180000 +b0 h3 +0j3 +#1004200000 +b1 g/ +b0 [. +b1 a/ +b1 d/ +b1 e/ +b0 U. +b0 X. +b0 Y. +b1010 J/ +b1010 Q/ +b1010 T/ +0L/ +b1011 >. +b1011 E. +b1011 H. +1@. +#1004230000 +b0 Y/ +b1 M. +b1 i/ +b0 ]. +b0 S/ +b0 V/ +b0 W/ +b1 G. +b1 J. +b1 K. +#1004260000 +b0 [/ +b1 O. +b1 f/ +1h/ +b0 Z. +0\. +#1004290000 +b0 X/ +0Z/ +b1 L. +1N. +1I/ +b10000011000000000000000000000000 2 +b10000011000000000000000000000000 @3 +0=. +#1004300000 +b1111 c3 +b1100 i3 +b11111111 ]3 +b1111100 f3 +b111110011111111 Z3 +0G/ +b1111100111111111111111111111111 1 +b1111100111111111111111111111111 C3 +1;. +#1004320000 +0z/ +1n. +0K/ +b11111001111111111111111111111110 6 +1?. +b10000011000000000000000000000000 " +b10000011000000000000000000000000 3 +b10000011000000000000000000000000 B3 +#1004330000 +b11 e3 +#1004350000 +1$0 +0&0 +b10100101 }/ +b10100101 60 +b10100101 90 +0I0 +0v. +1x. +b10100110 q. +b10100110 */ +b10100110 -/ +1=/ +#1004360000 +b11 _3 +1d3 +#1004380000 +b1 >0 +b0 2/ +b1 80 +b1 ;0 +b1 <0 +b0 ,/ +b0 // +b0 0/ +b1010 !0 +b1010 (0 +b1010 +0 +0#0 +b1011 s. +b1011 z. +b1011 }. +1u. +#1004390000 +b1 \3 +1^3 +#1004410000 +b0 00 +b1 $/ +b1 @0 +b0 4/ +b0 *0 +b0 -0 +b0 .0 +b1 |. +b1 !/ +b1 "/ +#1004440000 +b0 20 +b1 &/ +b1 =0 +1?0 +b0 1/ +03/ +#1004470000 +b0 /0 +010 +b1 #/ +1%/ +1~/ +b10000110000000000000000000000000 2 +b10000110000000000000000000000000 @3 +0r. +#1004480000 +b1001 i3 +b1111001 f3 +b111100111111111 Z3 +0|/ +b1111001111111111111111111111111 1 +b1111001111111111111111111111111 C3 +1p. +#1004500000 +0Q0 +1E/ +0"0 +b11110011111111111111111111111110 6 +1t. +b10000110000000000000000000000000 " +b10000110000000000000000000000000 3 +b10000110000000000000000000000000 B3 +#1004510000 +b0 k3 +#1004530000 +1Y0 +0[0 +b10100101 T0 +b10100101 k0 +b10100101 n0 +0~0 +0M/ +1O/ +b10100110 H/ +b10100110 _/ +b10100110 b/ +1r/ +#1004560000 +b1 s0 +b0 g/ +b1 m0 +b1 p0 +b1 q0 +b0 a/ +b0 d/ +b0 e/ +b1010 V0 +b1010 ]0 +b1010 `0 +0X0 +b1011 J/ +b1011 Q/ +b1011 T/ +1L/ +#1004590000 +b0 e0 +b1 Y/ +b1 u0 +b0 i/ +b0 _0 +b0 b0 +b0 c0 +b1 S/ +b1 V/ +b1 W/ +#1004620000 +b0 g0 +b1 [/ +b1 r0 +1t0 +b0 f/ +0h/ +#1004650000 +b0 d0 +0f0 +b1 X/ +1Z/ +1U0 +b10001100000000000000000000000000 2 +b10001100000000000000000000000000 @3 +0I/ +#1004660000 +b11 i3 +b1110011 f3 +b111001111111111 Z3 +0S0 +b1110011111111111111111111111111 1 +b1110011111111111111111111111111 C3 +1G/ +#1004680000 +0(1 +1z/ +0W0 +b11100111111111111111111111111110 6 +1K/ +b10001100000000000000000000000000 " +b10001100000000000000000000000000 3 +b10001100000000000000000000000000 B3 +#1004690000 +b1 k3 +#1004710000 +101 +021 +b10100101 +1 +b10100101 B1 +b10100101 E1 +0U1 +0$0 +1&0 +b10100110 }/ +b10100110 60 +b10100110 90 +1I0 +#1004740000 +b1 J1 +b0 >0 +b1 D1 +b1 G1 +b1 H1 +b0 80 +b0 ;0 +b0 <0 +b1010 -1 +b1010 41 +b1010 71 +0/1 +b1011 !0 +b1011 (0 +b1011 +0 +1#0 +#1004770000 +b0 <1 +b1 00 +b1 L1 +b0 @0 +b0 61 +b0 91 +b0 :1 +b1 *0 +b1 -0 +b1 .0 +#1004800000 +b0 >1 +b1 20 +b1 I1 +1K1 +b0 =0 +0?0 +#1004830000 +b0 ;1 +0=1 +b1 /0 +110 +1,1 +b10011000000000000000000000000000 2 +b10011000000000000000000000000000 @3 +0~/ +#1004840000 +b111 i3 +b110 l3 +b1100111 f3 +b110011111111111 Z3 +0*1 +b1100111111111111111111111111111 1 +b1100111111111111111111111111111 C3 +1|/ +#1004860000 +0]1 +1Q0 +0.1 +b11001111111111111111111111111110 6 +1"0 +b10011000000000000000000000000000 " +b10011000000000000000000000000000 3 +b10011000000000000000000000000000 B3 +#1004870000 +b0 n3 +#1004890000 +1e1 +0g1 +b10100101 `1 +b10100101 w1 +b10100101 z1 +0,2 +0Y0 +1[0 +b10100110 T0 +b10100110 k0 +b10100110 n0 +1~0 +#1004920000 +b1 !2 +b0 s0 +b1 y1 +b1 |1 +b1 }1 +b0 m0 +b0 p0 +b0 q0 +b1010 b1 +b1010 i1 +b1010 l1 +0d1 +b1011 V0 +b1011 ]0 +b1011 `0 +1X0 +#1004950000 +b0 q1 +b1 e0 +b1 #2 +b0 u0 +b0 k1 +b0 n1 +b0 o1 +b1 _0 +b1 b0 +b1 c0 +#1004980000 +b0 s1 +b1 g0 +b1 ~1 +1"2 +b0 r0 +0t0 +#1005010000 +b0 p1 +0r1 +b1 d0 +1f0 +1a1 +b10110000000000000000000000000000 2 +b10110000000000000000000000000000 @3 +0U0 +#1005020000 +b1111 i3 +b100 l3 +b1001111 f3 +b100111111111111 Z3 +0_1 +b1001111111111111111111111111111 1 +b1001111111111111111111111111111 C3 +1S0 +#1005040000 +042 +1(1 +0c1 +b10011111111111111111111111111110 6 +1W0 +b10110000000000000000000000000000 " +b10110000000000000000000000000000 3 +b10110000000000000000000000000000 B3 +#1005050000 +b11 k3 +#1005070000 +1<2 +0>2 +b10100101 72 +b10100101 N2 +b10100101 Q2 +0a2 +001 +121 +b10100110 +1 +b10100110 B1 +b10100110 E1 +1U1 +#1005080000 +b1 h3 +1j3 +#1005100000 +b1 V2 +b0 J1 +b1 P2 +b1 S2 +b1 T2 +b0 D1 +b0 G1 +b0 H1 +b1010 92 +b1010 @2 +b1010 C2 +0;2 +b1011 -1 +b1011 41 +b1011 71 +1/1 +#1005130000 +b0 H2 +b1 <1 +b1 X2 +b0 L1 +b0 B2 +b0 E2 +b0 F2 +b1 61 +b1 91 +b1 :1 +#1005160000 +b0 J2 +b1 >1 +b1 U2 +1W2 +b0 I1 +0K1 +#1005190000 +b0 G2 +0I2 +b1 ;1 +1=1 +182 +b11100000000000000000000000000000 2 +b11100000000000000000000000000000 @3 +0,1 +#1005200000 +b1 l3 +b11111 f3 +b1111111111111 Z3 +062 +b11111111111111111111111111111 1 +b11111111111111111111111111111 C3 +1*1 +#1005220000 +0i2 +1]1 +0:2 +b111111111111111111111111111110 6 +1.1 +b11100000000000000000000000000000 " +b11100000000000000000000000000000 3 +b11100000000000000000000000000000 B3 +#1005250000 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0e1 +1g1 +b10100110 `1 +b10100110 w1 +b10100110 z1 +1,2 +#1005280000 +b0 -3 +b0 !2 +b0 '3 +b0 *3 +b0 +3 +b0 y1 +b0 |1 +b0 }1 +053 +b0 n2 +b0 u2 +b0 x2 +073 +b1011 b1 +b1011 i1 +b1011 l1 +1d1 +#1005310000 +b1 q1 +b0 /3 +b0 #2 +b1 k1 +b1 n1 +b1 o1 +#1005340000 +b1 s1 +b0 ,3 +0.3 +b0 ~1 +0"2 +#1005370000 +b1 p1 +1r1 +0m2 +b1000000000000000000000000000000 2 +b1000000000000000000000000000000 @3 +0a1 +#1005380000 +b1011 l3 +b10111111 f3 +b1011111111111111 Z3 +1k2 +b10111111111111111111111111111111 1 +b10111111111111111111111111111111 C3 +1_1 +#1005400000 +142 +b1111111111111111111111111111110 6 +1c1 +b1000000000000000000000000000000 " +b1000000000000000000000000000000 3 +b1000000000000000000000000000000 B3 +#1005410000 +b1 n3 +#1005430000 +0<2 +1>2 +b10100110 72 +b10100110 N2 +b10100110 Q2 +1a2 +0. +#1005460000 +b0 V2 +b0 P2 +b0 S2 +b0 T2 +b1011 92 +b1011 @2 +b1011 C2 +1;2 +0- +#1005490000 +b1 H2 +b0 X2 +b1 B2 +b1 E2 +b1 F2 +0# +#1005520000 +b1 J2 +b0 U2 +0W2 +#1005550000 +b1 G2 +1I2 +b0 2 +b0 @3 +082 +#1005560000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +162 +#1005580000 +1i2 +b11111111111111111111111111111110 6 +1:2 +b0 " +b0 3 +b0 B3 +#1005590000 +b11 n3 +#1005610000 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +#1005620000 +b11 h3 +1m3 +#1005640000 +b1 -3 +b1 '3 +b1 *3 +b1 +3 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +#1005650000 +b11 \3 +1g3 +#1005670000 +b1 /3 +#1005680000 +b11 D3 +1[3 +#1005700000 +b1 ,3 +1.3 +#1005710000 +1! +#1005730000 +b10000000000000000000000000000000 2 +b10000000000000000000000000000000 @3 +1m2 +#1005740000 +b111 l3 +b1111111 f3 +b111111111111111 Z3 +b1111111111111111111111111111111 1 +b1111111111111111111111111111111 C3 +0k2 +#1005760000 +b10000000000000000000000000000000 " +b10000000000000000000000000000000 3 +b10000000000000000000000000000000 B3 +#1005770000 +b1 n3 +#1005790000 +1. +#1005800000 +b1 h3 +0m3 +#1005820000 +1- +#1005830000 +b1 \3 +0g3 +#1005850000 +1# +#1005860000 +b1 D3 +0[3 +#1005890000 +0! +#2000000000 +0<3 +0: +1F" +08 +0m +0y" +0P# +0'$ +0\$ +03% +0h% +0?& +0t& +0K' +0"( +0W( +0.) +0c) +0:* +0o* +0F+ +0{+ +0R, +0)- +0^- +05. +0j. +0A/ +0v/ +0M0 +0$1 +0Y1 +002 +b10 7 +b10 = +b10 I +b10 L +b10 W +b10 Z +b10 r +b10 ~ +b10 #" +b10 ." +b10 1" +b10 I" +b10 U" +b10 X" +b10 c" +b10 f" +b10 ~" +b10 ,# +b10 /# +b10 :# +b10 =# +b10 U# +b10 a# +b10 d# +b10 o# +b10 r# +b10 ,$ +b10 8$ +b10 ;$ +b10 F$ +b10 I$ +b10 a$ +b10 m$ +b10 p$ +b10 {$ +b10 ~$ +b10 8% +b10 D% +b10 G% +b10 R% +b10 U% +b10 m% +b10 y% +b10 |% +b10 )& +b10 ,& +b10 D& +b10 P& +b10 S& +b10 ^& +b10 a& +b10 y& +b10 '' +b10 *' +b10 5' +b10 8' +b10 P' +b10 \' +b10 _' +b10 j' +b10 m' +b10 '( +b10 3( +b10 6( +b10 A( +b10 D( +b10 \( +b10 h( +b10 k( +b10 v( +b10 y( +b10 3) +b10 ?) +b10 B) +b10 M) +b10 P) +b10 h) +b10 t) +b10 w) +b10 $* +b10 '* +b10 ?* +b10 K* +b10 N* +b10 Y* +b10 \* +b10 t* +b10 "+ +b10 %+ +b10 0+ +b10 3+ +b10 K+ +b10 W+ +b10 Z+ +b10 e+ +b10 h+ +b10 ", +b10 ., +b10 1, +b10 <, +b10 ?, +b10 W, +b10 c, +b10 f, +b10 q, +b10 t, +b10 .- +b10 :- +b10 =- +b10 H- +b10 K- +b10 c- +b10 o- +b10 r- +b10 }- +b10 ". +b10 :. +b10 F. +b10 I. +b10 T. +b10 W. +b10 o. +b10 {. +b10 ~. +b10 +/ +b10 ./ +b10 F/ +b10 R/ +b10 U/ +b10 `/ +b10 c/ +b10 {/ +b10 )0 +b10 ,0 +b10 70 +b10 :0 +b10 R0 +b10 ^0 +b10 a0 +b10 l0 +b10 o0 +b10 )1 +b10 51 +b10 81 +b10 C1 +b10 F1 +b10 ^1 +b10 j1 +b10 m1 +b10 x1 +b10 {1 +b10 52 +b10 A2 +b10 D2 +b10 O2 +b10 R2 +b10 j2 +b10 v2 +b10 y2 +b10 &3 +b10 )3 +b100 & +b100 , +b100 % +b100 + +b1 ' +b1 ) +#2000010000 +1=3 +1; +0G" +19 +1n +1z" +1Q# +1($ +1]$ +14% +1i% +1@& +1u& +1L' +1#( +1X( +1/) +1d) +1;* +1p* +1G+ +1|+ +1S, +1*- +1_- +16. +1k. +1B/ +1w/ +1N0 +1%1 +1Z1 +112 +#2000020000 +b10000110 K" +b10000110 b" +b10000110 e" +1p" +b11110010 ? +b11110010 V +b11110010 Y +b11100110 t +b11100110 -" +b11100110 0" +1;" +b11100110 "# +b11100110 9# +b11100110 <# +1G# +b11100110 W# +b11100110 n# +b11100110 q# +1|# +b11100110 .$ +b11100110 E$ +b11100110 H$ +1S$ +b11100110 c$ +b11100110 z$ +b11100110 }$ +1*% +b11100110 :% +b11100110 Q% +b11100110 T% +1_% +b11100110 o% +b11100110 (& +b11100110 +& +16& +b11100110 F& +b11100110 ]& +b11100110 `& +1k& +b11100110 {& +b11100110 4' +b11100110 7' +1B' +b11100110 R' +b11100110 i' +b11100110 l' +1w' +b11100110 )( +b11100110 @( +b11100110 C( +1N( +b11100110 ^( +b11100110 u( +b11100110 x( +1%) +b11100110 5) +b11100110 L) +b11100110 O) +1Z) +b11100110 j) +b11100110 #* +b11100110 &* +11* +b11100110 A* +b11100110 X* +b11100110 [* +1f* +b11100110 v* +b11100110 /+ +b11100110 2+ +1=+ +b11100110 M+ +b11100110 d+ +b11100110 g+ +1r+ +b11100110 $, +b11100110 ;, +b11100110 >, +1I, +b11100110 Y, +b11100110 p, +b11100110 s, +1~, +b11100110 0- +b11100110 G- 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+b1001 v +b1001 } +b1001 "" +0?" +1'# +0)# +b1100001 "# +b1100001 9# +b1100001 <# +0L# +1N# +b1001 $# +b1001 +# +b1001 .# +0K# +1\# +0^# +b1100001 W# +b1100001 n# +b1100001 q# +0#$ +1%$ +b1001 Y# +b1001 `# +b1001 c# +0"$ +13$ +05$ +b1100001 .$ +b1100001 E$ +b1100001 H$ +0X$ +1Z$ +b1001 0$ +b1001 7$ +b1001 :$ +0W$ +1h$ +0j$ +b1100001 c$ +b1100001 z$ +b1100001 }$ +0/% +11% +b1001 e$ +b1001 l$ +b1001 o$ +0.% +1?% +0A% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +b1001 <% +b1001 C% +b1001 F% +0c% +1t% +0v% +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +b1001 q% +b1001 x% +b1001 {% +0:& +1K& +0M& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +b1001 H& +b1001 O& +b1001 R& +0o& +1"' +0$' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +b1001 }& +b1001 &' +b1001 )' +0F' +1W' +0Y' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +b1001 T' +b1001 [' +b1001 ^' +0{' +1.( +00( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +b1001 +( +b1001 2( +b1001 5( +0R( +1c( +0e( +b1100001 ^( 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+b0 p- +b0 s- +b0 t- +b0 U. +b0 X. +b0 Y. +b0 G. +b0 J. +b0 K. +b0 ,/ +b0 // +b0 0/ +b0 |. +b0 !/ +b0 "/ +b0 a/ +b0 d/ +b0 e/ +b0 S/ +b0 V/ +b0 W/ +b0 80 +b0 ;0 +b0 <0 +b0 *0 +b0 -0 +b0 .0 +b0 m0 +b0 p0 +b0 q0 +b0 _0 +b0 b0 +b0 c0 +b0 D1 +b0 G1 +b0 H1 +b0 61 +b0 91 +b0 :1 +b0 y1 +b0 |1 +b0 }1 +b0 k1 +b0 n1 +b0 o1 +b0 P2 +b0 S2 +b0 T2 +b0 B2 +b0 E2 +b0 F2 +1f +b1010 A +b1010 H +b1010 K +1h +0- +0x +b1010 v +b1010 } +b1010 "" +1?" +0&# +b1010 $# +b1010 +# +b1010 .# +1K# +0[# +b1010 Y# +b1010 `# +b1010 c# +1"$ +02$ +b1010 0$ +b1010 7$ +b1010 :$ +1W$ +0g$ +b1010 e$ +b1010 l$ +b1010 o$ +1.% +0>% +b1010 <% +b1010 C% +b1010 F% +1c% +0s% +b1010 q% +b1010 x% +b1010 {% +1:& +0J& +b1010 H& +b1010 O& +b1010 R& +1o& +0!' +b1010 }& +b1010 &' +b1010 )' +1F' +0V' +b1010 T' +b1010 [' +b1010 ^' +1{' +0-( +b1010 +( +b1010 2( +b1010 5( +1R( +0b( +b1010 `( +b1010 g( +b1010 j( +1)) +09) +b1010 7) +b1010 >) +b1010 A) +1^) +0n) +b1010 l) +b1010 s) +b1010 v) +15* +0E* +b1010 C* +b1010 J* +b1010 M* +1j* +0z* +b1010 x* +b1010 !+ +b1010 $+ +1A+ +0Q+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +0(, +b1010 &, +b1010 -, +b1010 0, +1M, +0], +b1010 [, +b1010 b, +b1010 e, +1$- +04- +b1010 2- +b1010 9- +b1010 <- +1Y- +0i- +b1010 g- +b1010 n- +b1010 q- +10. +0@. +b1010 >. +b1010 E. +b1010 H. +1e. +0u. +b1010 s. +b1010 z. +b1010 }. +1' +b0 0' +b0 s' +b0 e' +b0 J( +b0 <( +b0 !) +b0 q( +b0 V) +b0 H) +b0 -* +b0 }) +b0 b* +b0 T* +b0 9+ +b0 ++ +b0 n+ +b0 `+ +b0 E, +b0 7, +b0 z, +b0 l, +b0 Q- +b0 C- +b0 (. +b0 x- +b0 ]. +b0 O. +b0 4/ +b0 &/ +b0 i/ +b0 [/ +b0 @0 +b0 20 +b0 u0 +b0 g0 +b0 L1 +b0 >1 +b0 #2 +b0 s1 +b0 X2 +b0 J2 +0B +1@ +1u +1L" +1## +1X# +1/$ +1d$ +1;% +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b111111111111111111111111111111101 6 +1o2 +b1111111111111111111111111111111 2 +b1111111111111111111111111111111 @3 +0m2 +b10 J +b10 M +b10 N +b10 !" +b10 $" +b10 %" +b10 -# +b10 0# +b10 1# +b10 b# +b10 e# +b10 f# +b10 9$ +b10 <$ +b10 =$ +b10 n$ +b10 q$ +b10 r$ +b10 E% +b10 H% +b10 I% +b10 z% +b10 }% +b10 ~% +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +0# +#2000130000 +b0 K3 +b0 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b1000 l3 +b0 H3 +b0 Q3 +b0 ]3 +b10000000 f3 +b0 E3 +b1000000000000000 Z3 +b10 \" +0> +0s +0J" +0!# +0V# +0-$ +0b$ +09% +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10000000000000000000000000000000 1 +b10000000000000000000000000000000 C3 +1k2 +b0 l" +b0 ^" +b10 V" +b10 Y" +b10 Z" +#2000150000 +b1 R +b1 )" +b1 5# +b1 j# +b1 A$ +b1 v$ +b1 M% +b1 $& +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b0 ] +0_ +b0 4" +06" +b0 &" +0(" +b0 @# +0B# +b0 2# +04# +b0 u# +0w# +b0 g# +0i# +b0 L$ +0N$ +b0 >$ +0@$ +b0 #% +0%% +b0 s$ +0u$ +b0 X% +0Z% +b0 J% +0L% +b0 /& +01& +b0 !& +0#& +b0 d& +0f& +b0 V& +0X& +b0 ;' +0=' +b0 -' +0/' +b0 p' +0r' +b0 b' +0d' +b0 G( +0I( +b0 9( +0;( +b0 |( +0~( +b0 n( +0p( +b0 S) +0U) +b0 E) +0G) +b0 ** +0,* +b0 z) +0|) +b0 _* +0a* +b0 Q* +0S* +b0 6+ +08+ +b0 (+ +0*+ +b0 k+ +0m+ +b0 ]+ +0_+ +b0 B, +0D, +b0 4, +06, +b0 w, +0y, +b0 i, +0k, +b0 N- +0P- +b0 @- +0B- +b0 %. +0'. +b0 u- +0w- +b0 Z. +0\. +b0 L. +0N. +b0 1/ +03/ +b0 #/ +0%/ +b0 f/ +0h/ +b0 X/ +0Z/ +b0 =0 +0?0 +b0 /0 +010 +b0 r0 +0t0 +b0 d0 +0f0 +b0 I1 +0K1 +b0 ;1 +0=1 +b0 ~1 +0"2 +b0 p1 +0r1 +b0 U2 +0W2 +b0 G2 +0I2 +0y +0>" +b1100010 t +b1100010 -" +b1100010 0" +1@" +0B" +1$ +b1111111111111111111111111111111 " +b1111111111111111111111111111111 3 +b1111111111111111111111111111111 B3 +#2000160000 +b0 M3 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 ^" +b0 i" +0k" +b0 [" +0]" +#2000180000 +0H" +0T# +0+$ +0`$ +07% +0l% +0C& +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 5" +b1 O +1Q +b1 &" +1(" +b1 2# +14# +b1 g# +1i# +b1 >$ +1@$ +b1 s$ +1u$ +b1 J% +1L% +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +0@ +0u +0w +0## +0%# +0X# +0Z# +0/$ +01$ +0d$ +0f$ +0;% +0=% +0p% +0r% +0G& +0I& +0|& +0~& +0S' +0U' +0*( +0,( +0_( +0a( +06) +08) +0k) +0m) +0B* +0D* +0w* +0y* +0N+ +0P+ +0%, +0', +0Z, +0\, +01- +03- +0f- +0h- +0=. +0?. +0r. +0t. +0I/ +0K/ +0~/ +0"0 +0U0 +0W0 +0,1 +0.1 +0a1 +0c1 +b100 2 +b100 @3 +082 +b100000000000000000000000000001001 6 +0:2 +b10 /" +b10 2" +b10 3" +0=" +b0 v +b0 } +b0 "" +0?" +10 +#2000190000 +b1011 K3 +b1111 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111011 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111111111011 E3 +b1111111111111111 Z3 +0}" +1> +1s +1!# +1V# +1-$ +1b$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +b11111111111111111111111111111011 1 +b11111111111111111111111111111011 C3 +162 +0L3 +b0 J3 +0O3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +b0 h3 +0j3 +b1 [" +1]" +b0 2 +b0 @3 +0L" +b100000000000000000000000000000001 6 +0N" +#2000200000 +b1111 K3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1J" +#2000210000 +1q +1H" +1T# +1+$ +1`$ +17% +1l% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 '" +b1 7" +1B +1w +1%# +1Z# +11$ +1f$ +1=% +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +b111111111111111111111111111110111 6 +1:2 +0P" +0s" +b10010010 K" +b10010010 b" +b10010010 e" +1u" +0w" +0\# +0!$ +b1100010 W# +b1100010 n# +b1100010 q# +1#$ +0%$ +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +b100 " +b100 3 +b100 B3 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +b0 !" +b0 $" +b0 %" +#2000220000 +1}" +b1 M3 +b11 P3 +b11 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +0I3 +b0 G3 +0R3 +b0 \3 +0^3 +b111111111111111111111111111111111 6 +1N" +b0 " +b0 3 +b0 B3 +0'# +0J# +b1100010 "# +b1100010 9# +b1100010 <# +1L# +0N# +#2000230000 +b11 M3 +#2000240000 +b10 j" +b10 v# +b10 M$ +b10 $% +b10 Y% +b10 0& +b10 e& +b10 <' +b10 q' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 )" +b1 4" +16" +1y +1>" +b1100001 t +b1100001 -" +b1100001 0" +0@" +1B" +1P" +1s" +b10010001 K" +b10010001 b" +b10010001 e" +0u" +1w" +1\# +1!$ +b1100001 W# +b1100001 n# +b1100001 q# +0#$ +1%$ +13$ +1V$ +b1100001 .$ +b1100001 E$ +b1100001 H$ +0X$ +1Z$ +1h$ +1-% +b1100001 c$ +b1100001 z$ +b1100001 }$ +0/% +11% +1?% +1b% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +1t% +19& +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +1K& +1n& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +b10 d" +b10 g" +b10 h" +b10 p# +b10 s# +b10 t# +b10 G$ +b10 J$ +b10 K$ +b10 |$ +b10 !% +b10 "% +b10 S% +b10 V% +b10 W% +b10 *& +b10 -& +b10 .& +b10 _& +b10 b& +b10 c& +b10 6' +b10 9' +b10 :' +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0r" +b1 M" +b1 T" +b1 W" +0t" +0~# +b0 Y# +b0 `# +b0 c# +0"$ +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +0a% +b0 <% +b0 C% +b0 F% +0c% +08& +b0 q% +b0 x% +b0 {% +0:& +0m& +b0 H& +b0 O& +b0 R& +0o& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +0# +b10 ?# +0I# +b0 $# +b0 +# +b0 .# +0K# +#2000260000 +b11 J3 +1L3 +#2000270000 +b0 5" +b0 j" +b0 v# +b0 M$ +b0 $% +b0 Y% +b0 0& +b0 e& +b0 <' +b0 q' +b0 H( +b0 }( +b0 T) +b0 +* +b0 `* +b0 7+ +b0 l+ +b0 C, +b0 x, +b0 O- +b0 &. +b0 [. +b0 2/ +b0 g/ +b0 >0 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 \" +b0 h# +b0 ?$ +b0 t$ +b0 K% +b0 "& +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 l" +b1 x# +b1 O$ +b1 &% +b1 [% +b1 2& +b1 g& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 &" +0(" +b10 2 +b10 @3 +1u +b0 /" +b0 2" +b0 3" +b0 d" +b0 g" +b0 h" +b0 p# +b0 s# +b0 t# +b0 G$ +b0 J$ +b0 K$ +b0 |$ +b0 !% +b0 "% +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 V" +b0 Y" +b0 Z" +b0 b# +b0 e# +b0 f# +b0 9$ +b0 <$ +b0 =$ +b0 n$ +b0 q$ +b0 r$ +b0 E% +b0 H% +b0 I% +b0 z% +b0 }% +b0 ~% +b0 Q& +b0 T& +b0 U& +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1=" +b1010 v +b1010 } +b1010 "" +1?" +1r" +b1011 M" +b1011 T" +b1011 W" +1t" +1~# +b1010 Y# +b1010 `# +b1010 c# +1"$ +1U$ +b1010 0$ +b1010 7$ +b1010 :$ +1W$ +1,% +b1010 e$ +b1010 l$ +b1010 o$ +1.% +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1# +b0 ?# +b0 -# +b0 0# +b0 1# +1I# +b1010 $# +b1010 +# +b1010 .# +1K# +#2000290000 +b11 G3 +1I3 +#2000300000 +0H" +b10 '" +b10 \" +b10 h# +b10 ?$ +b10 t$ +b10 K% +b10 "& +b10 W& +b10 .' +b10 c' +b10 :( +b10 o( +b10 F) +b10 {) +b10 R* +b10 )+ +b10 ^+ +b10 5, +b10 j, +b10 A- +b10 v- +b10 M. +b10 $/ +b10 Y/ +b10 00 +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 7" +b0 l" +b0 x# +b0 O$ +b0 &% +b0 [% +b0 2& +b0 g& +b0 >' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 ^" +b0 j# +b0 A$ +b0 v$ +b0 M% +b0 $& +b0 Y& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 i" +1k" +b1 u# +1w# +b1 L$ +1N$ +b1 #% +1%% +b1 X% +1Z% +b1 /& +11& +b1 d& +1f& +b1 ;' +1=' +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111111111111011 6 +0w +b10 " +b10 3 +b10 B3 +b10 !" +b10 $" +b10 %" +b10 V" +b10 Y" +b10 Z" +b10 b# +b10 e# +b10 f# +b10 9$ +b10 <$ +b10 =$ +b10 n$ +b10 q$ +b10 r$ +b10 E% +b10 H% +b10 I% +b10 z% +b10 }% +b10 ~% +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2000310000 +b10 3# +b10 M3 +b0 C# +b0 5# +b1 @# +1B# +b10 D3 +1[3 +b10 -# +b10 0# +b10 1# +#2000320000 +b11 D3 +1F3 +#2000330000 +b1 )" +b1 ^" +b1 j# +b1 A$ +b1 v$ +b1 M% +b1 $& +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 4" +06" +b0 i" +0k" +b0 u# +0w# +b0 L$ +0N$ +b0 #% +0%% +b0 X% +0Z% +b0 /& +01& +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 [" +0]" +b0 g# +0i# +b0 >$ +0@$ +b0 s$ +0u$ +b0 J% +0L% +b0 !& +0#& +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1L" +1X# +1/$ +1d$ +1;% +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111111110110 2 +b11111111111111111111111111110110 @3 +1m2 +0P" +0s" +b10010010 K" +b10010010 b" +b10010010 e" +1u" +0w" +#2000340000 +b1001 K3 +b0 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b1001 H3 +b0 Q3 +b0 ]3 +b0 f3 +b1001 E3 +b0 Z3 +0J" +0V# +0-$ +0b$ +09% +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001 1 +b1001 C3 +0k2 +b1 5# +b10 J3 +0L3 +b0 @# +0B# +b0 2# +04# +b11111111111111111111111111111110 2 +b11111111111111111111111111111110 @3 +1## +#2000350000 +b1 K3 +b1 H3 +b1 E3 +b1 1 +b1 C3 +0!# +1! +#2000360000 +0}" +0+$ +0`$ +07% +0l% +0C& +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 j" +b1 &" +1(" +b1 [" +1]" +b1 g# +1i# +b1 >$ +1@$ +b1 s$ +1u$ +b1 J% +1L% +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0u +0L" +0X# +0/$ +0d$ +0;% +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000 2 +b1000 @3 +0m2 +0N" +0Z# +01$ +0f$ +0=% +0r% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011 6 +0o2 +b11111111111111111111111111110110 " +b11111111111111111111111111110110 3 +b11111111111111111111111111110110 B3 +b10 d" +b10 g" +b10 h" +0r" +b1 M" +b1 T" +b1 W" +0t" +#2000370000 +b111 K3 +b1111 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11110111 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111111110111 E3 +b1111111111111111 Z3 +0T# +1s +1J" +1V# +1-$ +1b$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111111110111 1 +b11111111111111111111111111110111 C3 +1k2 +b0 M3 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 2# +14# +b10 G3 +0I3 +b0 2 +b0 @3 +0## +b11 6 +0%# +b11111111111111111111111111111110 " +b11111111111111111111111111111110 3 +b11111111111111111111111111111110 B3 +#2000380000 +b1111 K3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1!# +#2000390000 +1H" +1}" +1+$ +1`$ +17% +1l% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 \" +b1 l" +1w +1N" +1Z# +11$ +1f$ +1=% +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111111111101111 6 +1o2 +b1000 " +b1000 3 +b1000 B3 +0'# +0J# +b1100010 "# +b1100010 9# +b1100010 <# +1L# +0N# +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 V" +b0 Y" +b0 Z" +#2000400000 +1T# +b1 M3 +b11 P3 +b11 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 J3 +0O3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1%# +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0\# +0!$ +b1100010 W# +b1100010 n# +b1100010 q# +1#$ +0%$ +#2000410000 +b11 M3 +#2000420000 +b10 A# +b10 M$ +b10 $% +b10 Y% +b10 0& +b10 e& +b10 <' +b10 q' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 ^" +b1 i" +1k" +1P" +1s" +b10010001 K" +b10010001 b" +b10010001 e" +0u" +1w" +1'# +1J# +b1100001 "# +b1100001 9# +b1100001 <# +0L# +1N# +13$ +1V$ +b1100001 .$ +b1100001 E$ +b1100001 H$ +0X$ +1Z$ +1h$ +1-% +b1100001 c$ +b1100001 z$ +b1100001 }$ +0/% +11% +1?% +1b% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +1t% +19& +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +1K& +1n& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 ;# +b10 ># +b10 ?# +b10 G$ +b10 J$ +b10 K$ +b10 |$ +b10 !% +b10 "% +b10 S% +b10 V% +b10 W% +b10 *& +b10 -& +b10 .& +b10 _& +b10 b& +b10 c& +b10 6' +b10 9' +b10 :' +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0I# +b0 $# +b0 +# +b0 .# +0K# +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +0a% +b0 <% +b0 C% +b0 F% +0c% +08& +b0 q% +b0 x% +b0 {% +0:& +0m& +b0 H& +b0 O& +b0 R& +0o& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 3# +b0 ?$ +b0 t$ +b0 K% +b0 "& +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 C# +b1 O$ +b1 &% +b1 [% +b1 2& +b1 g& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 [" +0]" +b100 2 +b100 @3 +1L" +b0 d" +b0 g" +b0 h" +b0 ;# +b0 ># +b0 ?# +b0 G$ +b0 J$ +b0 K$ +b0 |$ +b0 !% +b0 "% +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 -# +b0 0# +b0 1# +b0 9$ +b0 <$ +b0 =$ +b0 n$ +b0 q$ +b0 r$ +b0 E% +b0 H% +b0 I% +b0 z% +b0 }% +b0 ~% +b0 Q& +b0 T& +b0 U& +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1r" +b1011 M" +b1011 T" +b1011 W" +1t" +1I# +b1010 $# +b1010 +# +b1010 .# +1K# +1U$ +b1010 0$ +b1010 7$ +b1010 :$ +1W$ +1,% +b1010 e$ +b1010 l$ +b1010 o$ +1.% +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 5# +b0 A$ +b0 v$ +b0 M% +b0 $& +b0 Y& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 @# +1B# +b1 L$ +1N$ +b1 #% +1%% +b1 X% +1Z% +b1 /& +11& +b1 d& +1f& +b1 ;' +1=' +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111111111110111 6 +0N" +b100 " +b100 3 +b100 B3 +b10 V" +b10 Y" +b10 Z" +b10 -# +b10 0# +b10 1# +b10 9$ +b10 <$ +b10 =$ +b10 n$ +b10 q$ +b10 r$ +b10 E% +b10 H% +b10 I% +b10 z% +b10 }% +b10 ~% +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2000490000 +b10 h# +b1 M3 +b0 x# +b0 j# +b1 u# +1w# +b10 D3 +1[3 +b10 b# +b10 e# +b10 f# +#2000500000 +b11 D3 +1F3 +#2000510000 +b1 ^" +b1 5# +b1 A$ +b1 v$ +b1 M% +b1 $& +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 i" +0k" +b0 @# +0B# +b0 L$ +0N$ +b0 #% +0%% +b0 X% +0Z% +b0 /& +01& +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 2# +04# +b0 >$ +0@$ +b0 s$ +0u$ +b0 J% +0L% +b0 !& +0#& +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1## +1/$ +1d$ +1;% +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111111101100 2 +b11111111111111111111111111101100 @3 +1m2 +0'# +0J# +b1100010 "# +b1100010 9# +b1100010 <# +1L# +0N# +#2000520000 +b11 K3 +b1 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b10011 H3 +b0 Q3 +b0 ]3 +b0 f3 +b10011 E3 +b0 Z3 +0!# +0-$ +0b$ +09% +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011 1 +b10011 C3 +0k2 +b1 j# +b10 J3 +0L3 +b0 u# +0w# +b0 g# +0i# +b11111111111111111111111111111100 2 +b11111111111111111111111111111100 @3 +1X# +#2000530000 +b0 N3 +b11 H3 +b11 E3 +b11 1 +b11 C3 +0V# +1! +#2000540000 +0T# +0`$ +07% +0l% +0C& +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 A# +b1 [" +1]" +b1 2# +14# +b1 >$ +1@$ +b1 s$ +1u$ +b1 J% +1L% +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0L" +0## +0/$ +0d$ +0;% +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000 2 +b10000 @3 +0m2 +0%# +01$ +0f$ +0=% +0r% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111 6 +0o2 +b11111111111111111111111111101100 " +b11111111111111111111111111101100 3 +b11111111111111111111111111101100 B3 +b10 ;# +b10 ># +b10 ?# +0I# +b0 $# +b0 +# +b0 .# +0K# +#2000550000 +b1111 K3 +b1110 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11101111 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111111101111 E3 +b1111111111111111 Z3 +0+$ +1J" +1!# +1-$ +1b$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111111101111 1 +b11111111111111111111111111101111 C3 +1k2 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 g# +1i# +b10 G3 +0I3 +b0 2 +b0 @3 +0X# +b111 6 +0Z# +b11111111111111111111111111111100 " +b11111111111111111111111111111100 3 +b11111111111111111111111111111100 B3 +#2000560000 +b1111 N3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1V# +#2000570000 +1}" +1T# +1`$ +17% +1l% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 3# +b1 C# +1N" +1%# +11$ +1f$ +1=% +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111111111011111 6 +1o2 +b10000 " +b10000 3 +b10000 B3 +0\# +0!$ +b1100010 W# +b1100010 n# +b1100010 q# +1#$ +0%$ +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 -# +b0 0# +b0 1# +#2000580000 +1+$ +b11 M3 +b10 P3 +b11 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 J3 +0O3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1Z# +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +#2000590000 +b11 P3 +#2000600000 +b10 v# +b10 $% +b10 Y% +b10 0& +b10 e& +b10 <' +b10 q' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 5# +b1 @# +1B# +1'# +1J# +b1100001 "# +b1100001 9# +b1100001 <# +0L# +1N# +1\# +1!$ +b1100001 W# +b1100001 n# +b1100001 q# +0#$ +1%$ +1h$ +1-% +b1100001 c$ +b1100001 z$ +b1100001 }$ +0/% +11% +1?% +1b% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +1t% +19& +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +1K& +1n& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 p# +b10 s# +b10 t# +b10 |$ +b10 !% +b10 "% +b10 S% +b10 V% +b10 W% +b10 *& +b10 -& +b10 .& +b10 _& +b10 b& +b10 c& +b10 6' +b10 9' +b10 :' +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0~# +b0 Y# +b0 `# +b0 c# +0"$ +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +0a% +b0 <% +b0 C% +b0 F% +0c% +08& +b0 q% +b0 x% +b0 {% +0:& +0m& +b0 H& +b0 O& +b0 R& +0o& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 h# +b0 t$ +b0 K% +b0 "& +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 x# +b1 &% +b1 [% +b1 2& +b1 g& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 2# +04# +b1000 2 +b1000 @3 +1## +b0 ;# +b0 ># +b0 ?# +b0 p# +b0 s# +b0 t# +b0 |$ +b0 !% +b0 "% +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 b# +b0 e# +b0 f# +b0 n$ +b0 q$ +b0 r$ +b0 E% +b0 H% +b0 I% +b0 z% +b0 }% +b0 ~% +b0 Q& +b0 T& +b0 U& +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1I# +b1010 $# +b1010 +# +b1010 .# +1K# +1~# +b1010 Y# +b1010 `# +b1010 c# +1"$ +1,% +b1010 e$ +b1010 l$ +b1010 o$ +1.% +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 j# +b0 v$ +b0 M% +b0 $& +b0 Y& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 u# +1w# +b1 #% +1%% +b1 X% +1Z% +b1 /& +11& +b1 d& +1f& +b1 ;' +1=' +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111111111101111 6 +0%# +b1000 " +b1000 3 +b1000 B3 +b10 -# +b10 0# +b10 1# +b10 b# +b10 e# +b10 f# +b10 n$ +b10 q$ +b10 r$ +b10 E% +b10 H% +b10 I% +b10 z% +b10 }% +b10 ~% +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2000670000 +b10 ?$ +b1 M3 +b0 O$ +b0 A$ +b1 L$ +1N$ +b10 D3 +1[3 +b10 9$ +b10 <$ +b10 =$ +#2000680000 +b11 D3 +1F3 +#2000690000 +b1 5# +b1 j# +b1 v$ +b1 M% +b1 $& +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 @# +0B# +b0 u# +0w# +b0 #% +0%% +b0 X% +0Z% +b0 /& +01& +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 g# +0i# +b0 s$ +0u$ +b0 J% +0L% +b0 !& +0#& +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1X# +1d$ +1;% +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111111011000 2 +b11111111111111111111111111011000 @3 +1m2 +0\# +0!$ +b1100010 W# +b1100010 n# +b1100010 q# +1#$ +0%$ +#2000700000 +b10 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b100111 H3 +b0 Q3 +b0 ]3 +b0 f3 +b100111 E3 +b0 Z3 +0V# +0b$ +09% +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111 1 +b100111 C3 +0k2 +b1 A$ +b10 J3 +0L3 +b0 L$ +0N$ +b0 >$ +0@$ +b11111111111111111111111111111000 2 +b11111111111111111111111111111000 @3 +1/$ +#2000710000 +b0 N3 +b111 H3 +b111 E3 +b111 1 +b111 C3 +0-$ +1! +#2000720000 +0+$ +07% +0l% +0C& +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 v# +b1 2# +14# +b1 g# +1i# +b1 s$ +1u$ +b1 J% +1L% +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0## +0X# +0d$ +0;% +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000 2 +b100000 @3 +0m2 +0Z# +0f$ +0=% +0r% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111 6 +0o2 +b11111111111111111111111111011000 " +b11111111111111111111111111011000 3 +b11111111111111111111111111011000 B3 +b10 p# +b10 s# +b10 t# +0~# +b0 Y# +b0 `# +b0 c# +0"$ +#2000730000 +b1111 K3 +b1101 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11011111 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111111011111 E3 +b1111111111111111 Z3 +0`$ +1!# +1V# +1b$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111111011111 1 +b11111111111111111111111111011111 C3 +1k2 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 >$ +1@$ +b10 G3 +0I3 +b0 2 +b0 @3 +0/$ +b1111 6 +01$ +b11111111111111111111111111111000 " +b11111111111111111111111111111000 3 +b11111111111111111111111111111000 B3 +#2000740000 +b1111 N3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1-$ +#2000750000 +1T# +1+$ +17% +1l% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 h# +b1 x# +1%# +1Z# +1f$ +1=% +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111111110111111 6 +1o2 +b100000 " +b100000 3 +b100000 B3 +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 b# +b0 e# +b0 f# +#2000760000 +1`$ +b11 M3 +b10 P3 +b11 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 J3 +0O3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +11$ +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +#2000770000 +b11 P3 +#2000780000 +b10 M$ +b10 Y% +b10 0& +b10 e& +b10 <' +b10 q' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 j# +b1 u# +1w# +1\# +1!$ +b1100001 W# +b1100001 n# +b1100001 q# +0#$ +1%$ +13$ +1V$ +b1100001 .$ +b1100001 E$ +b1100001 H$ +0X$ +1Z$ +1?% +1b% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +1t% +19& +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +1K& +1n& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 G$ +b10 J$ +b10 K$ +b10 S% +b10 V% +b10 W% +b10 *& +b10 -& +b10 .& +b10 _& +b10 b& +b10 c& +b10 6' +b10 9' +b10 :' +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +0a% +b0 <% +b0 C% +b0 F% +0c% +08& +b0 q% +b0 x% +b0 {% +0:& +0m& +b0 H& +b0 O& +b0 R& +0o& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 ?$ +b0 K% +b0 "& +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 O$ +b1 [% +b1 2& +b1 g& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 g# +0i# +b10000 2 +b10000 @3 +1X# +b0 p# +b0 s# +b0 t# +b0 G$ +b0 J$ +b0 K$ +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 9$ +b0 <$ +b0 =$ +b0 E% +b0 H% +b0 I% +b0 z% +b0 }% +b0 ~% +b0 Q& +b0 T& +b0 U& +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1~# +b1010 Y# +b1010 `# +b1010 c# +1"$ +1U$ +b1010 0$ +b1010 7$ +b1010 :$ +1W$ +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 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+b10 P3 +b0 &% +b0 v$ +b1 #% +1%% +b10 D3 +1[3 +b10 n$ +b10 q$ +b10 r$ +#2000860000 +b11 D3 +1F3 +#2000870000 +b1 j# +b1 A$ +b1 M% +b1 $& +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 u# +0w# +b0 L$ +0N$ +b0 X% +0Z% +b0 /& +01& +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 >$ +0@$ +b0 J% +0L% +b0 !& +0#& +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1/$ +1;% +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111110110000 2 +b11111111111111111111111110110000 @3 +1m2 +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +#2000880000 +b100 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b1001111 H3 +b0 Q3 +b0 ]3 +b0 f3 +b1001111 E3 +b0 Z3 +0-$ +09% +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111 1 +b1001111 C3 +0k2 +b1 v$ +b1 J3 +0O3 +b0 #% +0%% +b0 s$ +0u$ +b11111111111111111111111111110000 2 +b11111111111111111111111111110000 @3 +1d$ +#2000890000 +b0 N3 +b1111 H3 +b1111 E3 +b1111 1 +b1111 C3 +0b$ +1! +#2000900000 +0`$ +0l% +0C& +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 M$ +b1 g# +1i# +b1 >$ +1@$ +b1 J% +1L% +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0X# +0/$ +0;% +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000 2 +b1000000 @3 +0m2 +01$ +0=% +0r% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111 6 +0o2 +b11111111111111111111111110110000 " +b11111111111111111111111110110000 3 +b11111111111111111111111110110000 B3 +b10 G$ +b10 J$ +b10 K$ +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +#2000910000 +b1011 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b10111111 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111110111111 E3 +b1111111111111111 Z3 +07% +1V# +1-$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111110111111 1 +b11111111111111111111111110111111 C3 +1k2 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 s$ +1u$ +b10 G3 +0I3 +b0 2 +b0 @3 +0d$ +b11111 6 +0f$ +b11111111111111111111111111110000 " +b11111111111111111111111111110000 3 +b11111111111111111111111111110000 B3 +#2000920000 +b1111 N3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1b$ +#2000930000 +1+$ +1`$ +1l% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 ?$ +b1 O$ +1Z# +11$ +1=% +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111111101111111 6 +1o2 +b1000000 " +b1000000 3 +b1000000 B3 +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' 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+b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 |$ +b10 !% +b10 "% +b10 *& +b10 -& +b10 .& +b10 _& +b10 b& +b10 c& +b10 6' +b10 9' +b10 :' +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +08& +b0 q% +b0 x% +b0 {% +0:& +0m& +b0 H& +b0 O& +b0 R& +0o& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 t$ +b0 "& +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 &% +b1 2& +b1 g& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 >$ +0@$ +b100000 2 +b100000 @3 +1/$ +b0 G$ +b0 J$ +b0 K$ +b0 |$ +b0 !% +b0 "% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 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+b1010 l$ +b1010 o$ +1.% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 v$ +b0 $& +b0 Y& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 #% +1%% +b1 /& +11& +b1 d& +1f& +b1 ;' +1=' +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111111110111111 6 +01$ +b100000 " +b100000 3 +b100000 B3 +b10 9$ +b10 <$ +b10 =$ +b10 n$ +b10 q$ +b10 r$ +b10 z% +b10 }% +b10 ~% +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2001030000 +b10 K% +b10 P3 +b0 [% +b0 M% +b1 X% +1Z% +b10 D3 +1[3 +b10 E% +b10 H% +b10 I% +#2001040000 +b11 D3 +1F3 +#2001050000 +b1 A$ +b1 v$ +b1 $& +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 L$ +0N$ +b0 #% +0%% +b0 /& +01& +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 s$ +0u$ +b0 !& +0#& +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1d$ +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111101100000 2 +b11111111111111111111111101100000 @3 +1m2 +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +#2001060000 +b1001 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b10011111 H3 +b0 Q3 +b0 ]3 +b0 f3 +b10011111 E3 +b0 Z3 +0b$ +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011111 1 +b10011111 C3 +0k2 +b1 M% +b1 J3 +0O3 +b0 X% +0Z% +b0 J% +0L% +b11111111111111111111111111100000 2 +b11111111111111111111111111100000 @3 +1;% +#2001070000 +b1 N3 +b11111 H3 +b11111 E3 +b11111 1 +b11111 C3 +09% +1! +#2001080000 +07% +0C& +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 $% +b1 >$ +1@$ +b1 s$ +1u$ +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0/$ +0d$ +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000000 2 +b10000000 @3 +0m2 +0f$ +0r% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111 6 +0o2 +b11111111111111111111111101100000 " +b11111111111111111111111101100000 3 +b11111111111111111111111101100000 B3 +b10 |$ +b10 !% +b10 "% +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +#2001090000 +b111 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b1111111 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111101111111 E3 +b1111111111111111 Z3 +0l% +1-$ +1b$ +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111101111111 1 +b11111111111111111111111101111111 C3 +1k2 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 J% +1L% +b10 G3 +0I3 +b0 2 +b0 @3 +0;% +b111111 6 +0=% +b11111111111111111111111111100000 " +b11111111111111111111111111100000 3 +b11111111111111111111111111100000 B3 +#2001100000 +b1111 N3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +19% +#2001110000 +1`$ +17% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 t$ +b1 &% +11$ +1f$ +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111111011111111 6 +1o2 +b10000000 " +b10000000 3 +b10000000 B3 +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( 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+0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 K% +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 [% +b1 g& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 s$ +0u$ +b1000000 2 +b1000000 @3 +1d$ +b0 |$ +b0 !% +b0 "% +b0 S% +b0 V% +b0 W% +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 E% +b0 H% +b0 I% +b0 Q& +b0 T& +b0 U& +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1,% +b1010 e$ +b1010 l$ +b1010 o$ +1.% +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 M% +b0 Y& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 X% +1Z% +b1 d& +1f& +b1 ;' +1=' +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111111101111111 6 +0f$ +b1000000 " +b1000000 3 +b1000000 B3 +b10 n$ +b10 q$ +b10 r$ +b10 E% +b10 H% +b10 I% +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2001210000 +b10 "& +b1 P3 +b0 2& +b0 $& +b1 /& +11& +b10 D3 +1[3 +b10 z% +b10 }% +b10 ~% +#2001220000 +b11 D3 +1F3 +#2001230000 +b1 v$ +b1 M% +b1 Y& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 #% +0%% +b0 X% +0Z% +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 J% +0L% +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1;% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111011000000 2 +b11111111111111111111111011000000 @3 +1m2 +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +#2001240000 +b11 N3 +b1 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b111111 H3 +b1 Q3 +b0 ]3 +b0 f3 +b100111111 E3 +b0 Z3 +09% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111111 1 +b100111111 C3 +0k2 +b1 $& +b1 J3 +0O3 +b0 /& +01& +b0 !& +0#& +b11111111111111111111111111000000 2 +b11111111111111111111111111000000 @3 +1p% +#2001250000 +b0 T3 +b0 Q3 +b111111 E3 +b111111 1 +b111111 C3 +0n% +1! +#2001260000 +0l% +0x& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 Y% +b1 s$ +1u$ +b1 J% +1L% +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0d$ +0;% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000000 2 +b100000000 @3 +0m2 +0=% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111111 6 +0o2 +b11111111111111111111111011000000 " +b11111111111111111111111011000000 3 +b11111111111111111111111011000000 B3 +b10 S% +b10 V% +b10 W% +0a% +b0 <% +b0 C% +b0 F% +0c% +#2001270000 +b1111 N3 +b1110 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111111 H3 +b11111110 Q3 +b11111111 ]3 +b11111111 f3 +b1111111011111111 E3 +b1111111111111111 Z3 +0C& +1b$ +19% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111011111111 1 +b11111111111111111111111011111111 C3 +1k2 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 !& +1#& +b10 G3 +0I3 +b0 2 +b0 @3 +0p% +b1111111 6 +0r% +b11111111111111111111111111000000 " +b11111111111111111111111111000000 3 +b11111111111111111111111111000000 B3 +#2001280000 +b1111 T3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1n% +#2001290000 +17% +1l% +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 K% +b1 [% +1f$ +1=% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111110111111111 6 +1o2 +b100000000 " +b100000000 3 +b100000000 B3 +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 E% +b0 H% +b0 I% +#2001300000 +1C& +b11 P3 +b10 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1r% +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +#2001310000 +b11 V3 +#2001320000 +b10 0& +b10 <' +b10 q' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 M% +b1 X% +1Z% +1?% +1b% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +1t% +19& +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 *& +b10 -& +b10 .& +b10 6' +b10 9' +b10 :' +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +08& +b0 q% +b0 x% +b0 {% +0:& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 "& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 2& +b1 >' +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 J% +0L% +b10000000 2 +b10000000 @3 +1;% +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 z% +b0 }% +b0 ~% +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 $& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 /& +11& +b1 ;' +1=' +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111111011111111 6 +0=% +b10000000 " +b10000000 3 +b10000000 B3 +b10 E% +b10 H% +b10 I% +b10 z% +b10 }% +b10 ~% +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2001390000 +b10 W& +b1 P3 +b0 g& +b0 Y& +b1 d& +1f& +b10 D3 +1[3 +b10 Q& +b10 T& +b10 U& +#2001400000 +b11 D3 +1F3 +#2001410000 +b1 M% +b1 $& +b1 0' +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 X% +0Z% +b0 /& +01& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 !& +0#& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1p% +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111110110000000 2 +b11111111111111111111110110000000 @3 +1m2 +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +#2001420000 +b10 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b10 Q3 +b0 ]3 +b0 f3 +b1001111111 E3 +b0 Z3 +0n% +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111111 1 +b1001111111 C3 +0k2 +b1 Y& +b1 J3 +0O3 +b0 d& +0f& +b0 V& +0X& +b11111111111111111111111110000000 2 +b11111111111111111111111110000000 @3 +1G& +#2001430000 +b0 T3 +b0 Q3 +b1111111 E3 +b1111111 1 +b1111111 C3 +0E& +1! +#2001440000 +0C& +0O' +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 0& +b1 J% +1L% +b1 !& +1#& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0;% +0p% +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000000 2 +b1000000000 @3 +0m2 +0r% +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111111 6 +0o2 +b11111111111111111111110110000000 " +b11111111111111111111110110000000 3 +b11111111111111111111110110000000 B3 +b10 *& +b10 -& +b10 .& +08& +b0 q% +b0 x% +b0 {% +0:& +#2001450000 +b1111 N3 +b1101 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111111 H3 +b11111101 Q3 +b11111111 ]3 +b11111111 f3 +b1111110111111111 E3 +b1111111111111111 Z3 +0x& +19% +1n% +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111110111111111 1 +b11111111111111111111110111111111 C3 +1k2 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 V& +1X& +b10 G3 +0I3 +b0 2 +b0 @3 +0G& +b11111111 6 +0I& +b11111111111111111111111110000000 " +b11111111111111111111111110000000 3 +b11111111111111111111111110000000 B3 +#2001460000 +b1111 T3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1E& +#2001470000 +1l% +1C& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 "& +b1 2& +1=% +1r% +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111101111111111 6 +1o2 +b1000000000 " +b1000000000 3 +b1000000000 B3 +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 z% +b0 }% +b0 ~% +#2001480000 +1x& +b11 P3 +b10 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1I& +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +#2001490000 +b11 V3 +#2001500000 +b10 e& +b10 q' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 $& +b1 /& +11& +1t% +19& +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +1K& +1n& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 _& +b10 b& +b10 c& +b10 k' +b10 n' +b10 o' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0m& +b0 H& +b0 O& +b0 R& +0o& +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 W& +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 g& +b1 s' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 !& +0#& +b100000000 2 +b100000000 @3 +1p% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 Q& +b0 T& +b0 U& +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b1 G3 +1I3 +1^3 +b11 \3 +1g3 +b0 D3 +0[3 +b0 6' +b0 9' +b0 :' +b0 (' +b0 +' +b0 ,' +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +#2001550000 +b11 G3 +1R3 +#2001560000 +0C& +b10 "& +b10 W& +b10 c' +b10 :( +b10 o( +b10 F) +b10 {) +b10 R* +b10 )+ +b10 ^+ +b10 5, +b10 j, +b10 A- +b10 v- +b10 M. +b10 $/ +b10 Y/ +b10 00 +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 2& +b0 g& +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 Y& +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 d& +1f& +b1 p' +1r' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111110111111111 6 +0r% +b100000000 " +b100000000 3 +b100000000 B3 +b10 z% +b10 }% +b10 ~% +b10 Q& +b10 T& +b10 U& +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2001570000 +b10 .' +b10 V3 +b0 >' +b0 0' +b1 ;' +1=' +b10 D3 +1[3 +b10 (' +b10 +' +b10 ,' +#2001580000 +b11 D3 +1F3 +#2001590000 +b1 $& +b1 Y& +b1 e' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 /& +01& +b0 d& +0f& +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 V& +0X& +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1G& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111101100000000 2 +b11111111111111111111101100000000 @3 +1m2 +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +#2001600000 +b100 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b100 Q3 +b0 ]3 +b0 f3 +b10011111111 E3 +b0 Z3 +0E& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011111111 1 +b10011111111 C3 +0k2 +b1 0' +b10 S3 +0U3 +b0 ;' +0=' +b0 -' +0/' +b11111111111111111111111100000000 2 +b11111111111111111111111100000000 @3 +1|& +#2001610000 +b0 T3 +b0 Q3 +b11111111 E3 +b11111111 1 +b11111111 C3 +0z& +1! +#2001620000 +0x& +0&( +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 e& +b1 !& +1#& +b1 V& +1X& +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0p% +0G& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000000000 2 +b10000000000 @3 +0m2 +0I& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111111 6 +0o2 +b11111111111111111111101100000000 " +b11111111111111111111101100000000 3 +b11111111111111111111101100000000 B3 +b10 _& +b10 b& +b10 c& +0m& +b0 H& +b0 O& +b0 R& +0o& +#2001630000 +b1011 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111011 Q3 +b11111111 ]3 +b11111111 f3 +b1111101111111111 E3 +b1111111111111111 Z3 +0O' +1n% +1E& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111101111111111 1 +b11111111111111111111101111111111 C3 +1k2 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 -' +1/' +b1 G3 +0R3 +b0 2 +b0 @3 +0|& +b111111111 6 +0~& +b11111111111111111111111100000000 " +b11111111111111111111111100000000 3 +b11111111111111111111111100000000 B3 +#2001640000 +b1111 T3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1z& +#2001650000 +1C& +1x& +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 W& +b1 g& +1r% +1I& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111011111111111 6 +1o2 +b10000000000 " +b10000000000 3 +b10000000000 B3 +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 Q& +b0 T& +b0 U& +#2001660000 +1O' +b1 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1~& +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +#2001670000 +b11 V3 +#2001680000 +b10 <' +b10 H( +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 Y& +b1 d& +1f& +1K& +1n& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 6' +b10 9' +b10 :' +b10 B( +b10 E( +b10 F( +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0D' +b0 }& +b0 &' +b0 )' +0F' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 .' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 >' +b1 J( +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 V& +0X& +b1000000000 2 +b1000000000 @3 +1G& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 (' +b0 +' +b0 ,' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 0' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 ;' +1=' +b1 G( +1I( +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111101111111111 6 +0I& +b1000000000 " +b1000000000 3 +b1000000000 B3 +b10 Q& +b10 T& +b10 U& +b10 (' +b10 +' +b10 ,' +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2001750000 +b10 c' +b10 V3 +b0 s' +b0 e' +b1 p' +1r' +b10 D3 +1[3 +b10 ]' +b10 `' +b10 a' +#2001760000 +b11 D3 +1F3 +#2001770000 +b1 Y& +b1 0' +b1 <( +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 d& +0f& +b0 ;' +0=' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 -' +0/' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1|& +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111011000000000 2 +b11111111111111111111011000000000 @3 +1m2 +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +#2001780000 +b1001 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b1001 Q3 +b0 ]3 +b0 f3 +b100111111111 E3 +b0 Z3 +0z& +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111111111 1 +b100111111111 C3 +0k2 +b1 e' +b10 S3 +0U3 +b0 p' +0r' +b0 b' +0d' +b11111111111111111111111000000000 2 +b11111111111111111111111000000000 @3 +1S' +#2001790000 +b1 T3 +b1 Q3 +b111111111 E3 +b111111111 1 +b111111111 C3 +0Q' +1! +#2001800000 +0O' +0[( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 <' +b1 V& +1X& +b1 -' +1/' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0G& +0|& +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000000000 2 +b100000000000 @3 +0m2 +0~& +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111111111 6 +0o2 +b11111111111111111111011000000000 " +b11111111111111111111011000000000 3 +b11111111111111111111011000000000 B3 +b10 6' +b10 9' +b10 :' +0D' +b0 }& +b0 &' +b0 )' +0F' +#2001810000 +b111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11110111 Q3 +b11111111 ]3 +b11111111 f3 +b1111011111111111 E3 +b1111111111111111 Z3 +0&( +1E& +1z& +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111011111111111 1 +b11111111111111111111011111111111 C3 +1k2 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 b' +1d' +b1 G3 +0R3 +b0 2 +b0 @3 +0S' +b1111111111 6 +0U' +b11111111111111111111111000000000 " +b11111111111111111111111000000000 3 +b11111111111111111111111000000000 B3 +#2001820000 +b1111 T3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1Q' +#2001830000 +1x& +1O' +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 .' +b1 >' +1I& +1~& +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111110111111111111 6 +1o2 +b100000000000 " +b100000000000 3 +b100000000000 B3 +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 (' +b0 +' +b0 ,' +#2001840000 +1&( +b1 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1U' +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +#2001850000 +b11 V3 +#2001860000 +b10 q' +b10 }( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 0' +b1 ;' +1=' +1"' +1E' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 k' +b10 n' +b10 o' +b10 w( +b10 z( +b10 {( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0y' +b0 T' +b0 [' +b0 ^' +0{' +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 c' +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 s' +b1 !) +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 -' +0/' +b10000000000 2 +b10000000000 @3 +1|& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 ]' +b0 `' +b0 a' +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1' +b0 s' +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 e' +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 p' +1r' +b1 |( +1~( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111111011111111111 6 +0~& +b10000000000 " +b10000000000 3 +b10000000000 B3 +b10 (' +b10 +' +b10 ,' +b10 ]' +b10 `' +b10 a' +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2001930000 +b10 :( +b1 V3 +b0 J( +b0 <( +b1 G( +1I( +b10 D3 +1[3 +b10 4( +b10 7( +b10 8( +#2001940000 +b11 D3 +1F3 +#2001950000 +b1 0' +b1 e' +b1 q( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 ;' +0=' +b0 p' +0r' +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 b' +0d' +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1S' +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111110110000000000 2 +b11111111111111111110110000000000 @3 +1m2 +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +#2001960000 +b11 T3 +b1 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b10011 Q3 +b0 ]3 +b0 f3 +b1001111111111 E3 +b0 Z3 +0Q' +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111111111 1 +b1001111111111 C3 +0k2 +b1 <( +b10 S3 +0U3 +b0 G( +0I( +b0 9( +0;( +b11111111111111111111110000000000 2 +b11111111111111111111110000000000 @3 +1*( +#2001970000 +b0 W3 +b11 Q3 +b1111111111 E3 +b1111111111 1 +b1111111111 C3 +0(( +1! +#2001980000 +0&( +02) +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 q' +b1 -' +1/' +b1 b' +1d' +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0|& +0S' +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000000000 2 +b1000000000000 @3 +0m2 +0U' +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111111111 6 +0o2 +b11111111111111111110110000000000 " +b11111111111111111110110000000000 3 +b11111111111111111110110000000000 B3 +b10 k' +b10 n' +b10 o' +0y' +b0 T' +b0 [' +b0 ^' +0{' +#2001990000 +b1111 T3 +b1110 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11101111 Q3 +b11111111 ]3 +b11111111 f3 +b1110111111111111 E3 +b1111111111111111 Z3 +0[( +1z& +1Q' +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111110111111111111 1 +b11111111111111111110111111111111 C3 +1k2 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 9( +1;( +b1 G3 +0R3 +b0 2 +b0 @3 +0*( +b11111111111 6 +0,( +b11111111111111111111110000000000 " +b11111111111111111111110000000000 3 +b11111111111111111111110000000000 B3 +#2002000000 +b1111 W3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1(( +#2002010000 +1O' +1&( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 c' +b1 s' +1~& +1U' +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111101111111111111 6 +1o2 +b1000000000000 " +b1000000000000 3 +b1000000000000 B3 +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 ]' +b0 `' +b0 a' +#2002020000 +1[( +b11 V3 +b10 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1,( +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +#2002030000 +b11 Y3 +#2002040000 +b10 H( +b10 T) +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 e' +b1 p' +1r' +1W' +1z' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 B( +b10 E( +b10 F( +b10 N) +b10 Q) +b10 R) +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0P( +b0 +( +b0 2( +b0 5( +0R( +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 :( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 J( +b1 V) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 b' +0d' +b100000000000 2 +b100000000000 @3 +1S' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 4( +b0 7( +b0 8( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 G( +1I( +b1 S) +1U) +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111110111111111111 6 +0U' +b100000000000 " +b100000000000 3 +b100000000000 B3 +b10 ]' +b10 `' +b10 a' +b10 4( +b10 7( +b10 8( +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2002110000 +b10 o( +b1 V3 +b0 !) +b0 q( +b1 |( +1~( +b10 D3 +1[3 +b10 i( +b10 l( +b10 m( +#2002120000 +b11 D3 +1F3 +#2002130000 +b1 e' +b1 <( +b1 H) +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 p' +0r' +b0 G( +0I( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 9( +0;( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1*( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111101100000000000 2 +b11111111111111111101100000000000 @3 +1m2 +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +#2002140000 +b10 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b100111 Q3 +b0 ]3 +b0 f3 +b10011111111111 E3 +b0 Z3 +0(( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011111111111 1 +b10011111111111 C3 +0k2 +b1 q( +b10 S3 +0U3 +b0 |( +0~( +b0 n( +0p( +b11111111111111111111100000000000 2 +b11111111111111111111100000000000 @3 +1_( +#2002150000 +b0 W3 +b111 Q3 +b11111111111 E3 +b11111111111 1 +b11111111111 C3 +0]( +1! +#2002160000 +0[( +0g) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 H( +b1 b' +1d' +b1 9( +1;( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0S' +0*( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000000000000 2 +b10000000000000 @3 +0m2 +0,( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111111111 6 +0o2 +b11111111111111111101100000000000 " +b11111111111111111101100000000000 3 +b11111111111111111101100000000000 B3 +b10 B( +b10 E( +b10 F( +0P( +b0 +( +b0 2( +b0 5( +0R( +#2002170000 +b1111 T3 +b1101 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11011111 Q3 +b11111111 ]3 +b11111111 f3 +b1101111111111111 E3 +b1111111111111111 Z3 +02) +1Q' +1(( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111101111111111111 1 +b11111111111111111101111111111111 C3 +1k2 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 n( +1p( +b1 G3 +0R3 +b0 2 +b0 @3 +0_( +b111111111111 6 +0a( +b11111111111111111111100000000000 " +b11111111111111111111100000000000 3 +b11111111111111111111100000000000 B3 +#2002180000 +b1111 W3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1]( +#2002190000 +1&( +1[( +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 :( +b1 J( +1U' +1,( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111011111111111111 6 +1o2 +b10000000000000 " +b10000000000000 3 +b10000000000000 B3 +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 4( +b0 7( +b0 8( +#2002200000 +12) +b11 V3 +b10 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1a( +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +#2002210000 +b11 Y3 +#2002220000 +b10 }( +b10 +* +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 <( +b1 G( +1I( +1.( +1Q( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 w( +b10 z( +b10 {( +b10 %* +b10 (* +b10 )* +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0') +b0 `( +b0 g( +b0 j( +0)) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +0) +b0 A) +0^) +#2002240000 +b11 S3 +1X3 +#2002250000 +b0 H( +b0 }( +b0 +* +b0 `* +b0 7+ +b0 l+ +b0 C, +b0 x, +b0 O- +b0 &. +b0 [. +b0 2/ +b0 g/ +b0 >0 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 o( +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 !) +b1 -* +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 9( +0;( +b1000000000000 2 +b1000000000000 @3 +1*( +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 i( +b0 l( +b0 m( +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1) +b1010 A) +1^) +#2002270000 +b11 G3 +1R3 +#2002280000 +0[( +b10 :( +b10 o( +b10 {) +b10 R* +b10 )+ +b10 ^+ +b10 5, +b10 j, +b10 A- +b10 v- +b10 M. +b10 $/ +b10 Y/ +b10 00 +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 J( +b0 !) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 q( +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 |( +1~( +b1 ** +1,* +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111101111111111111 6 +0,( +b1000000000000 " +b1000000000000 3 +b1000000000000 B3 +b10 4( +b10 7( +b10 8( +b10 i( +b10 l( +b10 m( +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2002290000 +b10 F) +b10 Y3 +b0 V) +b0 H) +b1 S) +1U) +b10 D3 +1[3 +b10 @) +b10 C) +b10 D) +#2002300000 +b11 D3 +1F3 +#2002310000 +b1 <( +b1 q( +b1 }) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 G( +0I( +b0 |( +0~( +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 n( +0p( +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1_( +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111011000000000000 2 +b11111111111111111011000000000000 @3 +1m2 +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +#2002320000 +b100 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b1001111 Q3 +b0 ]3 +b0 f3 +b100111111111111 E3 +b0 Z3 +0]( +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111111111111 1 +b100111111111111 C3 +0k2 +b1 H) +b1 S3 +0X3 +b0 S) +0U) +b0 E) +0G) +b11111111111111111111000000000000 2 +b11111111111111111111000000000000 @3 +16) +#2002330000 +b0 W3 +b1111 Q3 +b111111111111 E3 +b111111111111 1 +b111111111111 C3 +04) +1! +#2002340000 +02) +0>* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 }( +b1 9( +1;( +b1 n( +1p( +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0*( +0_( +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000000000000 2 +b100000000000000 @3 +0m2 +0a( +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111111111111 6 +0o2 +b11111111111111111011000000000000 " +b11111111111111111011000000000000 3 +b11111111111111111011000000000000 B3 +b10 w( +b10 z( +b10 {( +0') +b0 `( +b0 g( +b0 j( +0)) +#2002350000 +b1011 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b10111111 Q3 +b11111111 ]3 +b11111111 f3 +b1011111111111111 E3 +b1111111111111111 Z3 +0g) +1(( +1]( +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111011111111111111 1 +b11111111111111111011111111111111 C3 +1k2 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 E) +1G) +b1 G3 +0R3 +b0 2 +b0 @3 +06) +b1111111111111 6 +08) +b11111111111111111111000000000000 " +b11111111111111111111000000000000 3 +b11111111111111111111000000000000 B3 +#2002360000 +b1111 W3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +14) +#2002370000 +1[( +12) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 o( +b1 !) +1,( +1a( +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111110111111111111111 6 +1o2 +b100000000000000 " +b100000000000000 3 +b100000000000000 B3 +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 i( +b0 l( +b0 m( +#2002380000 +1g) +b1 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +18) +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +#2002390000 +b11 Y3 +#2002400000 +b10 T) +b10 `* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 q( +b1 |( +1~( +1c( +1() +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 N) +b10 Q) +b10 R) +b10 Z* +b10 ]* +b10 ^* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0\) +b0 7) +b0 >) +b0 A) +0^) +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 F) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 V) +b1 b* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 n( +0p( +b10000000000000 2 +b10000000000000 @3 +1_( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 @) +b0 C) +b0 D) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 S) +1U) +b1 _* +1a* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111111011111111111111 6 +0a( +b10000000000000 " +b10000000000000 3 +b10000000000000 B3 +b10 i( +b10 l( +b10 m( +b10 @) +b10 C) +b10 D) +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2002470000 +b10 {) +b10 Y3 +b0 -* +b0 }) +b1 ** +1,* +b10 D3 +1[3 +b10 u) +b10 x) +b10 y) +#2002480000 +b11 D3 +1F3 +#2002490000 +b1 q( +b1 H) +b1 T* +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 |( +0~( +b0 S) +0U) +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 E) +0G) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +16) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111110110000000000000 2 +b11111111111111110110000000000000 @3 +1m2 +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +#2002500000 +b1001 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b10011111 Q3 +b0 ]3 +b0 f3 +b1001111111111111 E3 +b0 Z3 +04) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111111111111 1 +b1001111111111111 C3 +0k2 +b1 }) +b1 S3 +0X3 +b0 ** +0,* +b0 z) +0|) +b11111111111111111110000000000000 2 +b11111111111111111110000000000000 @3 +1k) +#2002510000 +b1 W3 +b11111 Q3 +b1111111111111 E3 +b1111111111111 1 +b1111111111111 C3 +0i) +1! +#2002520000 +0g) +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 T) +b1 n( +1p( +b1 E) +1G) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0_( +06) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000000000000 2 +b1000000000000000 @3 +0m2 +08) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111111111111 6 +0o2 +b11111111111111110110000000000000 " +b11111111111111110110000000000000 3 +b11111111111111110110000000000000 B3 +b10 N) +b10 Q) +b10 R) +0\) +b0 7) +b0 >) +b0 A) +0^) +#2002530000 +b111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b1111111 Q3 +b11111111 ]3 +b11111111 f3 +b111111111111111 E3 +b1111111111111111 Z3 +0>* +1]( +14) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111110111111111111111 1 +b11111111111111110111111111111111 C3 +1k2 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 z) +1|) +b1 G3 +0R3 +b0 2 +b0 @3 +0k) +b11111111111111 6 +0m) +b11111111111111111110000000000000 " +b11111111111111111110000000000000 3 +b11111111111111111110000000000000 B3 +#2002540000 +b1111 W3 +b11111111 Q3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1i) +#2002550000 +12) +1g) +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 F) +b1 V) +1a( +18) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111101111111111111111 6 +1o2 +b1000000000000000 " +b1000000000000000 3 +b1000000000000000 B3 +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 @) +b0 C) +b0 D) +#2002560000 +1>* +b1 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1m) +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +#2002570000 +b11 Y3 +#2002580000 +b10 +* +b10 7+ +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 H) +b1 S) +1U) +1:) +1]) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 %* +b10 (* +b10 )* +b10 1+ +b10 4+ +b10 5+ +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +03* +b0 l) +b0 s) +b0 v) +05* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 {) +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 -* +b1 9+ +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 E) +0G) +b100000000000000 2 +b100000000000000 @3 +16) +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 u) +b0 x) +b0 y) +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 ** +1,* +b1 6+ +18+ +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111110111111111111111 6 +08) +b100000000000000 " +b100000000000000 3 +b100000000000000 B3 +b10 @) +b10 C) +b10 D) +b10 u) +b10 x) +b10 y) +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2002650000 +b10 R* +b1 Y3 +b0 b* +b0 T* +b1 _* +1a* +b10 D3 +1[3 +b10 L* +b10 O* +b10 P* +#2002660000 +b11 D3 +1F3 +#2002670000 +b1 H) +b1 }) +b1 ++ +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 S) +0U) +b0 ** +0,* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 z) +0|) +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1k) +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111101100000000000000 2 +b11111111111111101100000000000000 @3 +1m2 +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +#2002680000 +b11 W3 +b1 `3 +b0 c3 +b0 i3 +b0 l3 +b111111 Q3 +b1 ]3 +b0 f3 +b11111111111111 E3 +b1 Z3 +0i) +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011111111111111 1 +b10011111111111111 C3 +0k2 +b1 T* +b1 S3 +0X3 +b0 _* +0a* +b0 Q* +0S* +b11111111111111111100000000000000 2 +b11111111111111111100000000000000 @3 +1B* +#2002690000 +b0 `3 +b0 ]3 +b0 Z3 +b11111111111111 1 +b11111111111111 C3 +0@* +1! +#2002700000 +0>* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 +* +b1 E) +1G) +b1 z) +1|) +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +06) +0k) +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000000000000000 2 +b10000000000000000 @3 +0m2 +0m) +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111111111111 6 +0o2 +b11111111111111101100000000000000 " +b11111111111111101100000000000000 3 +b11111111111111101100000000000000 B3 +b10 %* +b10 (* +b10 )* +03* +b0 l) +b0 s) +b0 v) +05* +#2002710000 +b1111 W3 +b1110 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111111 Q3 +b11111110 ]3 +b11111111 f3 +b1111111111111111 E3 +b1111111111111110 Z3 +0s* +14) +1i) +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111101111111111111111 1 +b11111111111111101111111111111111 C3 +1k2 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 Q* +1S* +b1 G3 +0R3 +b0 2 +b0 @3 +0B* +b111111111111111 6 +0D* +b11111111111111111100000000000000 " +b11111111111111111100000000000000 3 +b11111111111111111100000000000000 B3 +#2002720000 +b1111 `3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1@* +#2002730000 +1g) +1>* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 {) +b1 -* +18) +1m) +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111011111111111111111 6 +1o2 +b10000000000000000 " +b10000000000000000 3 +b10000000000000000 B3 +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 u) +b0 x) +b0 y) +#2002740000 +1s* +b11 Y3 +b10 b3 +b11 e3 +b11 k3 +b11 n3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1D* +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +#2002750000 +b11 b3 +#2002760000 +b10 `* +b10 l+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 }) +b1 ** +1,* +1o) +14* +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 Z* +b10 ]* +b10 ^* +b10 f+ +b10 i+ +b10 j+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0h* +b0 C* +b0 J* +b0 M* +0j* +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 R* +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 b* +b1 n+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 z) +0|) +b1000000000000000 2 +b1000000000000000 @3 +1k) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 L* +b0 O* +b0 P* +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1* +b10 {) +b10 R* +b10 ^+ +b10 5, +b10 j, +b10 A- +b10 v- +b10 M. +b10 $/ +b10 Y/ +b10 00 +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 -* +b0 b* +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 T* +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 _* +1a* +b1 k+ +1m+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111101111111111111111 6 +0m) +b1000000000000000 " +b1000000000000000 3 +b1000000000000000 B3 +b10 u) +b10 x) +b10 y) +b10 L* +b10 O* +b10 P* +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2002830000 +b10 )+ +b1 Y3 +b0 9+ +b0 ++ +b1 6+ +18+ +b1 D3 +1F3 +b10 #+ +b10 &+ +b10 '+ +#2002840000 +b11 D3 +1[3 +#2002850000 +b1 }) +b1 T* +b1 `+ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 ** +0,* +b0 _* +0a* +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 Q* +0S* +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1B* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111011000000000000000 2 +b11111111111111011000000000000000 @3 +1m2 +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +#2002860000 +b10 `3 +b0 c3 +b0 i3 +b0 l3 +b10 ]3 +b0 f3 +b10 Z3 +0@* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111111111111111 1 +b100111111111111111 C3 +0k2 +b1 ++ +b1 S3 +0X3 +b0 6+ +08+ +b0 (+ +0*+ +b11111111111111111000000000000000 2 +b11111111111111111000000000000000 @3 +1w* +#2002870000 +b0 `3 +b0 ]3 +b0 Z3 +b111111111111111 1 +b111111111111111 C3 +0u* +1! +#2002880000 +0s* +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 `* +b1 z) +1|) +b1 Q* +1S* +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0k) +0B* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000000000000000 2 +b100000000000000000 @3 +0m2 +0D* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111111111111111 6 +0o2 +b11111111111111011000000000000000 " +b11111111111111011000000000000000 3 +b11111111111111011000000000000000 B3 +b10 Z* +b10 ]* +b10 ^* +0h* +b0 C* +b0 J* +b0 M* +0j* +#2002890000 +b1111 W3 +b1101 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111111 Q3 +b11111101 ]3 +b11111111 f3 +b1111111111111111 E3 +b1111111111111101 Z3 +0J+ +1i) +1@* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111011111111111111111 1 +b11111111111111011111111111111111 C3 +1k2 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 (+ +1*+ +b1 G3 +0R3 +b0 2 +b0 @3 +0w* +b1111111111111111 6 +0y* +b11111111111111111000000000000000 " +b11111111111111111000000000000000 3 +b11111111111111111000000000000000 B3 +#2002900000 +b1111 `3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1u* +#2002910000 +1>* +1s* +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 R* +b1 b* +1m) +1D* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111110111111111111111111 6 +1o2 +b100000000000000000 " +b100000000000000000 3 +b100000000000000000 B3 +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 L* +b0 O* +b0 P* +#2002920000 +1J+ +b11 Y3 +b10 b3 +b11 e3 +b11 k3 +b11 n3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1y* +b10 D3 +0F3 +b0 " +b0 3 +b0 B3 +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +#2002930000 +b11 b3 +#2002940000 +b10 7+ +b10 C, +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 T* +b1 _* +1a* +1F* +1i* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 1+ +b10 4+ +b10 5+ +b10 =, +b10 @, +b10 A, +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 )+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 9+ +b1 E, +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 Q* +0S* +b10000000000000000 2 +b10000000000000000 @3 +1B* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 #+ +b0 &+ +b0 '+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 6+ +18+ +b1 B, +1D, +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111111011111111111111111 6 +0D* +b10000000000000000 " +b10000000000000000 3 +b10000000000000000 B3 +b10 L* +b10 O* +b10 P* +b10 #+ +b10 &+ +b10 '+ +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2003010000 +b10 ^+ +b10 b3 +b0 n+ +b0 `+ +b1 k+ +1m+ +b1 D3 +1F3 +b10 X+ +b10 [+ +b10 \+ +#2003020000 +b11 D3 +1[3 +#2003030000 +b1 T* +b1 ++ +b1 7, +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 _* +0a* +b0 6+ +08+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 (+ +0*+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1w* +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111110110000000000000000 2 +b11111111111110110000000000000000 @3 +1m2 +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +#2003040000 +b100 `3 +b0 c3 +b0 i3 +b0 l3 +b100 ]3 +b0 f3 +b100 Z3 +0u* +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111111111111111 1 +b1001111111111111111 C3 +0k2 +b1 `+ +b10 _3 +0a3 +b0 k+ +0m+ +b0 ]+ +0_+ +b11111111111111110000000000000000 2 +b11111111111111110000000000000000 @3 +1N+ +#2003050000 +b0 `3 +b0 ]3 +b0 Z3 +b1111111111111111 1 +b1111111111111111 C3 +0L+ +1! +#2003060000 +0J+ +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 7+ +b1 Q* +1S* +b1 (+ +1*+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0B* +0w* +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000000000000000 2 +b1000000000000000000 @3 +0m2 +0y* +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111111111111111 6 +0o2 +b11111111111110110000000000000000 " +b11111111111110110000000000000000 3 +b11111111111110110000000000000000 B3 +b10 1+ +b10 4+ +b10 5+ +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +#2003070000 +b1011 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11111011 ]3 +b11111111 f3 +b1111111111111011 Z3 +0!, +1@* +1u* +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111110111111111111111111 1 +b11111111111110111111111111111111 C3 +1k2 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 ]+ +1_+ +b10 \3 +0^3 +b0 2 +b0 @3 +0N+ +b11111111111111111 6 +0P+ +b11111111111111110000000000000000 " +b11111111111111110000000000000000 3 +b11111111111111110000000000000000 B3 +#2003080000 +b1111 `3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1L+ +#2003090000 +1s* +1J+ +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 )+ +b1 9+ +1D* +1y* +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111101111111111111111111 6 +1o2 +b1000000000000000000 " +b1000000000000000000 3 +b1000000000000000000 B3 +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 #+ +b0 &+ +b0 '+ +#2003100000 +1!, +b1 b3 +b11 e3 +b11 k3 +b11 n3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1P+ +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +#2003110000 +b11 b3 +#2003120000 +b10 l+ +b10 x, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 ++ +b1 6+ +18+ +1{* +1@+ +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 f+ +b10 i+ +b10 j+ +b10 r, +b10 u, +b10 v, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +0, +0N, +1P, +0! +b10 =, +b10 @, +b10 A, +0K, +b0 &, +b0 -, +b0 0, +0M, +#2003140000 +b11 _3 +1a3 +#2003150000 +b0 7+ +b0 l+ +b0 x, +b0 O- +b0 &. +b0 [. +b0 2/ +b0 g/ +b0 >0 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 ^+ +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 n+ +b1 z, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 (+ +0*+ +b100000000000000000 2 +b100000000000000000 @3 +1w* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 X+ +b0 [+ +b0 \+ +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 k+ +1m+ +b1 w, +1y, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111110111111111111111111 6 +0y* +b100000000000000000 " +b100000000000000000 3 +b100000000000000000 B3 +b10 #+ +b10 &+ +b10 '+ +b10 X+ +b10 [+ +b10 \+ +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2003190000 +b10 5, +b10 b3 +b0 E, +b0 7, +b1 B, +1D, +b10 /, +b10 2, +b10 3, +#2003200000 +b11 D3 +1[3 +#2003210000 +b1 ++ +b1 `+ +b1 l, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 6+ +08+ +b0 k+ +0m+ +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 ]+ +0_+ +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1N+ +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111101100000000000000000 2 +b11111111111101100000000000000000 @3 +1m2 +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +#2003220000 +b1001 `3 +b0 c3 +b0 i3 +b0 l3 +b1001 ]3 +b0 f3 +b1001 Z3 +0L+ +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011111111111111111 1 +b10011111111111111111 C3 +0k2 +b1 7, +b10 _3 +0a3 +b0 B, +0D, +b0 4, +06, +b11111111111111100000000000000000 2 +b11111111111111100000000000000000 @3 +1%, +#2003230000 +b1 `3 +b1 ]3 +b1 Z3 +b11111111111111111 1 +b11111111111111111 C3 +0#, +1! +#2003240000 +0!, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 l+ +b1 (+ +1*+ +b1 ]+ +1_+ +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0w* +0N+ +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000000000000000000 2 +b10000000000000000000 @3 +0m2 +0P+ +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111111111111111 6 +0o2 +b11111111111101100000000000000000 " +b11111111111101100000000000000000 3 +b11111111111101100000000000000000 B3 +b10 f+ +b10 i+ +b10 j+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +#2003250000 +b111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11110111 ]3 +b11111111 f3 +b1111111111110111 Z3 +0V, +1u* +1L+ +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111101111111111111111111 1 +b11111111111101111111111111111111 C3 +1k2 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +b1 4, +16, +b10 \3 +0^3 +b0 2 +b0 @3 +0%, +b111111111111111111 6 +0', +b11111111111111100000000000000000 " +b11111111111111100000000000000000 3 +b11111111111111100000000000000000 B3 +#2003260000 +b1111 `3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1#, +#2003270000 +1J+ +1!, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 ^+ +b1 n+ +1y* +1P+ +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111011111111111111111111 6 +1o2 +b10000000000000000000 " +b10000000000000000000 3 +b10000000000000000000 B3 +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 X+ +b0 [+ +b0 \+ +#2003280000 +1V, +b1 b3 +b11 e3 +b11 k3 +b11 n3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1', +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +#2003290000 +b11 b3 +#2003300000 +b10 C, +b10 O- +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 `+ +b1 k+ +1m+ +1R+ +1u+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 =, +b10 @, +b10 A, +b10 I- +b10 L- +b10 M- +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0K, +b0 &, +b0 -, +b0 0, +0M, +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 5, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 E, +b1 Q- +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 ]+ +0_+ +b1000000000000000000 2 +b1000000000000000000 @3 +1N+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 /, +b0 2, +b0 3, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 B, +1D, +b1 N- +1P- +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111101111111111111111111 6 +0P+ +b1000000000000000000 " +b1000000000000000000 3 +b1000000000000000000 B3 +b10 X+ +b10 [+ +b10 \+ +b10 /, +b10 2, +b10 3, +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2003370000 +b10 j, +b1 b3 +b0 z, +b0 l, +b1 w, +1y, +b10 d, +b10 g, +b10 h, +#2003380000 +b11 D3 +1[3 +#2003390000 +b1 `+ +b1 7, +b1 C- +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 k+ +0m+ +b0 B, +0D, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 4, +06, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1%, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111011000000000000000000 2 +b11111111111011000000000000000000 @3 +1m2 +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +#2003400000 +b11 `3 +b1 c3 +b0 i3 +b0 l3 +b10011 ]3 +b0 f3 +b10011 Z3 +0#, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111111111111111111 1 +b100111111111111111111 C3 +0k2 +b1 l, +b10 _3 +0a3 +b0 w, +0y, +b0 i, +0k, +b11111111111111000000000000000000 2 +b11111111111111000000000000000000 @3 +1Z, +#2003410000 +b0 c3 +b11 ]3 +b11 Z3 +b111111111111111111 1 +b111111111111111111 C3 +0X, +1! +#2003420000 +0V, +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 C, +b1 ]+ +1_+ +b1 4, +16, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0N+ +0%, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000000000000000000 2 +b100000000000000000000 @3 +0m2 +0', +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111111111111111111 6 +0o2 +b11111111111011000000000000000000 " +b11111111111011000000000000000000 3 +b11111111111011000000000000000000 B3 +b10 =, +b10 @, +b10 A, +0K, +b0 &, +b0 -, +b0 0, +0M, +#2003430000 +b1111 `3 +b1110 c3 +b1111 i3 +b1111 l3 +b11101111 ]3 +b11111111 f3 +b1111111111101111 Z3 +0-- +1L+ +1#, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111011111111111111111111 1 +b11111111111011111111111111111111 C3 +1k2 +b0 e3 +b0 k3 +b0 n3 +b1 i, +1k, +b10 \3 +0^3 +b0 2 +b0 @3 +0Z, +b1111111111111111111 6 +0\, +b11111111111111000000000000000000 " +b11111111111111000000000000000000 3 +b11111111111111000000000000000000 B3 +#2003440000 +b1111 c3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1X, +#2003450000 +1!, +1V, +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 5, +b1 E, +1P+ +1', +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111110111111111111111111111 6 +1o2 +b100000000000000000000 " +b100000000000000000000 3 +b100000000000000000000 B3 +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 /, +b0 2, +b0 3, +#2003460000 +1-- +b11 b3 +b10 e3 +b11 k3 +b11 n3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1\, +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +#2003470000 +b11 e3 +#2003480000 +b10 x, +b10 &. +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 7, +b1 B, +1D, +1), +1L, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 r, +b10 u, +b10 v, +b10 ~- +b10 #. +b10 $. +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0"- +b0 [, +b0 b, +b0 e, +0$- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 j, +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 z, +b1 (. +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 4, +06, +b10000000000000000000 2 +b10000000000000000000 @3 +1%, +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 d, +b0 g, +b0 h, +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1- +b0 ?- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +#2003530000 +b11 \3 +1^3 +#2003540000 +0V, +b10 5, +b10 j, +b10 v- +b10 M. +b10 $/ +b10 Y/ +b10 00 +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 E, +b0 z, +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 l, +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 w, +1y, +b1 %. +1'. +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111111011111111111111111111 6 +0', +b10000000000000000000 " +b10000000000000000000 3 +b10000000000000000000 B3 +b10 /, +b10 2, +b10 3, +b10 d, +b10 g, +b10 h, +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2003550000 +b10 A- +b1 b3 +b0 Q- +b0 C- +b1 N- +1P- +b10 ;- +b10 >- +b10 ?- +#2003560000 +b11 D3 +1[3 +#2003570000 +b1 7, +b1 l, +b1 x- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 B, +0D, +b0 w, +0y, +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 i, +0k, +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1Z, +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111110110000000000000000000 2 +b11111111110110000000000000000000 @3 +1m2 +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +#2003580000 +b10 c3 +b0 i3 +b0 l3 +b100111 ]3 +b0 f3 +b100111 Z3 +0X, +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111111111111111111 1 +b1001111111111111111111 C3 +0k2 +b1 C- +b10 _3 +0a3 +b0 N- +0P- +b0 @- +0B- +b11111111111110000000000000000000 2 +b11111111111110000000000000000000 @3 +11- +#2003590000 +b0 c3 +b111 ]3 +b111 Z3 +b1111111111111111111 1 +b1111111111111111111 C3 +0/- +1! +#2003600000 +0-- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 x, +b1 4, +16, +b1 i, +1k, +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0%, +0Z, +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000000000000000000 2 +b1000000000000000000000 @3 +0m2 +0\, +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111111111111111111 6 +0o2 +b11111111110110000000000000000000 " +b11111111110110000000000000000000 3 +b11111111110110000000000000000000 B3 +b10 r, +b10 u, +b10 v, +0"- +b0 [, +b0 b, +b0 e, +0$- +#2003610000 +b1111 `3 +b1101 c3 +b1111 i3 +b1111 l3 +b11011111 ]3 +b11111111 f3 +b1111111111011111 Z3 +0b- +1#, +1X, +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111110111111111111111111111 1 +b11111111110111111111111111111111 C3 +1k2 +b0 e3 +b0 k3 +b0 n3 +b1 @- +1B- +b10 \3 +0^3 +b0 2 +b0 @3 +01- +b11111111111111111111 6 +03- +b11111111111110000000000000000000 " +b11111111111110000000000000000000 3 +b11111111111110000000000000000000 B3 +#2003620000 +b1111 c3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1/- +#2003630000 +1V, +1-- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 j, +b1 z, +1', +1\, +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111101111111111111111111111 6 +1o2 +b1000000000000000000000 " +b1000000000000000000000 3 +b1000000000000000000000 B3 +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 d, +b0 g, +b0 h, +#2003640000 +1b- +b11 b3 +b10 e3 +b11 k3 +b11 n3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +13- +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +#2003650000 +b11 e3 +#2003660000 +b10 O- +b10 [. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 l, +b1 w, +1y, +1^, +1#- +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 I- +b10 L- +b10 M- +b10 U. +b10 X. +b10 Y. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0W- +b0 2- +b0 9- +b0 <- +0Y- +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 A- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 Q- +b1 ]. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 i, +0k, +b100000000000000000000 2 +b100000000000000000000 @3 +1Z, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 ;- +b0 >- +b0 ?- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 N- +1P- +b1 Z. +1\. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111110111111111111111111111 6 +0\, +b100000000000000000000 " +b100000000000000000000 3 +b100000000000000000000 B3 +b10 d, +b10 g, +b10 h, +b10 ;- +b10 >- +b10 ?- +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2003730000 +b10 v- +b10 e3 +b0 (. +b0 x- +b1 %. +1'. +b10 p- +b10 s- +b10 t- +#2003740000 +b11 D3 +1[3 +#2003750000 +b1 l, +b1 C- +b1 O. +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 w, +0y, +b0 N- +0P- +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 @- +0B- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +11- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111101100000000000000000000 2 +b11111111101100000000000000000000 @3 +1m2 +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +#2003760000 +b100 c3 +b0 i3 +b0 l3 +b1001111 ]3 +b0 f3 +b1001111 Z3 +0/- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b10011111111111111111111 1 +b10011111111111111111111 C3 +0k2 +b1 x- +b1 _3 +0d3 +b0 %. +0'. +b0 u- +0w- +b11111111111100000000000000000000 2 +b11111111111100000000000000000000 @3 +1f- +#2003770000 +b0 c3 +b1111 ]3 +b1111 Z3 +b11111111111111111111 1 +b11111111111111111111 C3 +0d- +1! +#2003780000 +0b- +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 O- +b1 i, +1k, +b1 @- +1B- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0Z, +01- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b10000000000000000000000 2 +b10000000000000000000000 @3 +0m2 +03- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111111111111111111 6 +0o2 +b11111111101100000000000000000000 " +b11111111101100000000000000000000 3 +b11111111101100000000000000000000 B3 +b10 I- +b10 L- +b10 M- +0W- +b0 2- +b0 9- +b0 <- +0Y- +#2003790000 +b1011 c3 +b1111 i3 +b1111 l3 +b10111111 ]3 +b11111111 f3 +b1111111110111111 Z3 +09. +1X, +1/- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111101111111111111111111111 1 +b11111111101111111111111111111111 C3 +1k2 +b0 e3 +b0 k3 +b0 n3 +b1 u- +1w- +b10 \3 +0^3 +b0 2 +b0 @3 +0f- +b111111111111111111111 6 +0h- +b11111111111100000000000000000000 " +b11111111111100000000000000000000 3 +b11111111111100000000000000000000 B3 +#2003800000 +b1111 c3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1d- +#2003810000 +1-- +1b- +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 A- +b1 Q- +1\, +13- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111011111111111111111111111 6 +1o2 +b10000000000000000000000 " +b10000000000000000000000 3 +b10000000000000000000000 B3 +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 ;- +b0 >- +b0 ?- +#2003820000 +19. +b1 e3 +b11 k3 +b11 n3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1h- +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +#2003830000 +b11 e3 +#2003840000 +b10 &. +b10 2/ +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 C- +b1 N- +1P- +15- +1X- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 ~- +b10 #. +b10 $. +b10 ,/ +b10 // +b10 0/ +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0.. +b0 g- +b0 n- +b0 q- +00. +0:/ +b0 s. +b0 z. +b0 }. +0. +b0 E. +b0 H. +0e. +#2003860000 +b11 _3 +1d3 +#2003870000 +b0 O- +b0 &. +b0 2/ +b0 g/ +b0 >0 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 v- +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 (. +b1 4/ +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 @- +0B- +b1000000000000000000000 2 +b1000000000000000000000 @3 +11- +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 p- +b0 s- +b0 t- +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1:/ +b1010 s. +b1010 z. +b1010 }. +1. +b1010 E. +b1010 H. +1e. +#2003890000 +b11 \3 +1^3 +#2003900000 +0b- +b10 A- +b10 v- +b10 $/ +b10 Y/ +b10 00 +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 Q- +b0 (. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 x- +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 %. +1'. +b1 1/ +13/ +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111101111111111111111111111 6 +03- +b1000000000000000000000 " +b1000000000000000000000 3 +b1000000000000000000000 B3 +b10 ;- +b10 >- +b10 ?- +b10 p- +b10 s- +b10 t- +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2003910000 +b10 M. +b10 e3 +b0 ]. +b0 O. +b1 Z. +1\. +b10 G. +b10 J. +b10 K. +#2003920000 +b11 D3 +1[3 +#2003930000 +b1 C- +b1 x- +b1 &/ +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 N- +0P- +b0 %. +0'. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 u- +0w- +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1f- +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111011000000000000000000000 2 +b11111111011000000000000000000000 @3 +1m2 +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +#2003940000 +b1001 c3 +b0 i3 +b0 l3 +b10011111 ]3 +b0 f3 +b10011111 Z3 +0d- +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b100111111111111111111111 1 +b100111111111111111111111 C3 +0k2 +b1 O. +b1 _3 +0d3 +b0 Z. +0\. +b0 L. +0N. +b11111111111000000000000000000000 2 +b11111111111000000000000000000000 @3 +1=. +#2003950000 +b1 c3 +b11111 ]3 +b11111 Z3 +b111111111111111111111 1 +b111111111111111111111 C3 +0;. +1! +#2003960000 +09. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 &. +b1 @- +1B- +b1 u- +1w- +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +01- +0f- +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b100000000000000000000000 2 +b100000000000000000000000 @3 +0m2 +0h- +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b1001111111111111111111111 6 +0o2 +b11111111011000000000000000000000 " +b11111111011000000000000000000000 3 +b11111111011000000000000000000000 B3 +b10 ~- +b10 #. +b10 $. +0.. +b0 g- +b0 n- +b0 q- +00. +#2003970000 +b111 c3 +b1111 i3 +b1111 l3 +b1111111 ]3 +b11111111 f3 +b1111111101111111 Z3 +0n. +1/- +1d- +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111011111111111111111111111 1 +b11111111011111111111111111111111 C3 +1k2 +b0 e3 +b0 k3 +b0 n3 +b1 L. +1N. +b10 \3 +0^3 +b0 2 +b0 @3 +0=. +b1111111111111111111111 6 +0?. +b11111111111000000000000000000000 " +b11111111111000000000000000000000 3 +b11111111111000000000000000000000 B3 +#2003980000 +b1111 c3 +b11111111 ]3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1;. +#2003990000 +1b- +19. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 v- +b1 (. +13- +1h- +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111110111111111111111111111111 6 +1o2 +b100000000000000000000000 " +b100000000000000000000000 3 +b100000000000000000000000 B3 +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 p- +b0 s- +b0 t- +#2004000000 +1n. +b1 e3 +b11 k3 +b11 n3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1?. +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +#2004010000 +b11 e3 +#2004020000 +b10 [. +b10 g/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 x- +b1 %. +1'. +1j- +1/. +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 U. +b10 X. +b10 Y. +b10 a/ +b10 d/ +b10 e/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0c. +b0 >. +b0 E. +b0 H. +0e. +0o/ +b0 J/ +b0 Q/ +b0 T/ +0q/ +0F0 +b0 !0 +b0 (0 +b0 +0 +0H0 +0{0 +b0 V0 +b0 ]0 +b0 `0 +0}0 +0R1 +b0 -1 +b0 41 +b0 71 +0T1 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +053 +b0 n2 +b0 u2 +b0 x2 +073 +00 +#2004030000 +b10 2/ +1j3 +b11 h3 +1m3 +b0 \3 +0g3 +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +0! +b10 ,/ +b10 // +b10 0/ +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 M. +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 ]. +b1 i/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 u- +0w- +b10000000000000000000000 2 +b10000000000000000000000 @3 +1f- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 G. +b0 J. +b0 K. +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1o/ +b1010 J/ +b1010 Q/ +b1010 T/ +1q/ +1F0 +b1010 !0 +b1010 (0 +b1010 +0 +1H0 +1{0 +b1010 V0 +b1010 ]0 +b1010 `0 +1}0 +1R1 +b1010 -1 +b1010 41 +b1010 71 +1T1 +1)2 +b1010 b1 +b1010 i1 +b1010 l1 +1+2 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +1. +10 +#2004060000 +b1011 c3 +b10111111 ]3 +b1111111110111111 Z3 +b0 2/ +b0 $/ +b11111111101111111111111111111111 1 +b11111111101111111111111111111111 C3 +0d- +b1 4/ +b10 \3 +1g3 +b0 ,/ +b0 // +b0 0/ +b0 |. +b0 !/ +b0 "/ +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 Z. +1\. +b1 f/ +1h/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111111011111111111111111111111 6 +0h- +b10000000000000000000000 " +b10000000000000000000000 3 +b10000000000000000000000 B3 +b10 p- +b10 s- +b10 t- +b10 G. +b10 J. +b10 K. +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2004090000 +b10 $/ +b1 e3 +b0 4/ +b0 &/ +b1 1/ +13/ +b10 |. +b10 !/ +b10 "/ +#2004100000 +b11 D3 +1[3 +#2004110000 +b1 x- +b1 O. +b1 [/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 %. +0'. +b0 Z. +0\. +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 L. +0N. +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1=. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111110110000000000000000000000 2 +b11111110110000000000000000000000 @3 +1m2 +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +#2004120000 +b11 c3 +b1 i3 +b0 l3 +b111111 ]3 +b1 f3 +b100111111 Z3 +0;. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1001111111111111111111111 1 +b1001111111111111111111111 C3 +0k2 +b1 &/ +b1 _3 +0d3 +b0 1/ +03/ +b0 #/ +0%/ +b11111111110000000000000000000000 2 +b11111111110000000000000000000000 @3 +1r. +#2004130000 +b0 i3 +b0 f3 +b111111 Z3 +b1111111111111111111111 1 +b1111111111111111111111 C3 +0p. +1! +#2004140000 +0n. +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 [. +b1 u- +1w- +b1 L. +1N. +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0f- +0=. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1000000000000000000000000 2 +b1000000000000000000000000 @3 +0m2 +0?. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b10011111111111111111111111 6 +0o2 +b11111110110000000000000000000000 " +b11111110110000000000000000000000 3 +b11111110110000000000000000000000 B3 +b10 U. +b10 X. +b10 Y. +0c. +b0 >. +b0 E. +b0 H. +0e. +#2004150000 +b1111 c3 +b1110 i3 +b1111 l3 +b11111111 ]3 +b11111110 f3 +b1111111011111111 Z3 +0E/ +1d- +1;. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111110111111111111111111111111 1 +b11111110111111111111111111111111 C3 +1k2 +b0 k3 +b0 n3 +b1 #/ +1%/ +b10 \3 +0^3 +b0 2 +b0 @3 +0r. +b11111111111111111111111 6 +0t. +b11111111110000000000000000000000 " +b11111111110000000000000000000000 3 +b11111111110000000000000000000000 B3 +#2004160000 +b1111 i3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1p. +#2004170000 +19. +1n. +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +b0 M. +b1 ]. +1h- +1?. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111101111111111111111111111111 6 +1o2 +b1000000000000000000000000 " +b1000000000000000000000000 3 +b1000000000000000000000000 B3 +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 G. +b0 J. +b0 K. +#2004180000 +1E/ +b11 e3 +b10 k3 +b11 n3 +0j3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1t. +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +#2004190000 +b11 k3 +#2004200000 +b10 2/ +b10 >0 +b10 s0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 O. +b1 Z. +1\. +1A. +1d. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +1v. +1;/ +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 ,/ +b10 // +b10 0/ +b10 80 +b10 ;0 +b10 <0 +b10 m0 +b10 p0 +b10 q0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0:/ +b0 s. +b0 z. +b0 }. +00 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 $/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 4/ +b1 @0 +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 L. +0N. +b100000000000000000000000 2 +b100000000000000000000000 @3 +1=. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 |. +b0 !/ +b0 "/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +11 +b0 s1 +b0 J2 +b0 !3 +b1 1/ +13/ +b1 =0 +1?0 +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111110111111111111111111111111 6 +0?. +b100000000000000000000000 " +b100000000000000000000000 3 +b100000000000000000000000 B3 +b10 G. +b10 J. +b10 K. +b10 |. +b10 !/ +b10 "/ +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2004270000 +b10 Y/ +b1 e3 +b0 i/ +b0 [/ +b1 f/ +1h/ +b10 S/ +b10 V/ +b10 W/ +#2004280000 +b11 D3 +1[3 +#2004290000 +b1 O. +b1 &/ +b1 20 +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 Z. +0\. +b0 1/ +03/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 #/ +0%/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1r. +1~/ +1U0 +1,1 +1a1 +182 +b11111101100000000000000000000000 2 +b11111101100000000000000000000000 @3 +1m2 +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +#2004300000 +b10 i3 +b0 l3 +b10 f3 +b1001111111 Z3 +0p. +0|/ +0S0 +0*1 +0_1 +062 +b10011111111111111111111111 1 +b10011111111111111111111111 C3 +0k2 +b1 [/ +b1 _3 +0d3 +b0 f/ +0h/ +b0 X/ +0Z/ +b11111111100000000000000000000000 2 +b11111111100000000000000000000000 @3 +1I/ +#2004310000 +b0 i3 +b0 f3 +b1111111 Z3 +b11111111111111111111111 1 +b11111111111111111111111 C3 +0G/ +1! +#2004320000 +0E/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 2/ +b1 L. +1N. +b1 #/ +1%/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0=. +0r. +0~/ +0U0 +0,1 +0a1 +082 +b10000000000000000000000000 2 +b10000000000000000000000000 @3 +0m2 +0t. +0"0 +0W0 +0.1 +0c1 +0:2 +b100111111111111111111111111 6 +0o2 +b11111101100000000000000000000000 " +b11111101100000000000000000000000 3 +b11111101100000000000000000000000 B3 +b10 ,/ +b10 // +b10 0/ +0:/ +b0 s. +b0 z. +b0 }. +00 +b11 _3 +1d3 +b10 h3 +1m3 +b0 \3 +0g3 +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +0! +b10 80 +b10 ;0 +b10 <0 +0F0 +b0 !0 +b0 (0 +b0 +0 +0H0 +#2004400000 +b11 h3 +1j3 +#2004410000 +b0 2/ +b0 g/ +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 Y/ +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 i/ +b1 u0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 #/ +0%/ +b1000000000000000000000000 2 +b1000000000000000000000000 @3 +1r. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 S/ +b0 V/ +b0 W/ +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1:/ +b1010 s. +b1010 z. +b1010 }. +10 +b0 00 +b11111110111111111111111111111111 1 +b11111110111111111111111111111111 C3 +0p. +b1 @0 +b1 \3 +1^3 +b0 80 +b0 ;0 +b0 <0 +b0 *0 +b0 -0 +b0 .0 +1F0 +b1010 !0 +b1010 (0 +b1010 +0 +1H0 +#2004430000 +b11 \3 +1g3 +#2004440000 +0E/ +b10 $/ +b10 Y/ +b10 e0 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 4/ +b0 i/ +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 [/ +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 f/ +1h/ +b1 r0 +1t0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111101111111111111111111111111 6 +0t. +b1000000000000000000000000 " +b1000000000000000000000000 3 +b1000000000000000000000000 B3 +b10 |. +b10 !/ +b10 "/ +b10 S/ +b10 V/ +b10 W/ +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2004450000 +b10 00 +b10 k3 +b0 @0 +b0 20 +b1 =0 +1?0 +b10 *0 +b10 -0 +b10 .0 +#2004460000 +b11 D3 +1[3 +#2004470000 +b1 &/ +b1 [/ +b1 g0 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 1/ +03/ +b0 f/ +0h/ +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 X/ +0Z/ +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1I/ +1U0 +1,1 +1a1 +182 +b11111011000000000000000000000000 2 +b11111011000000000000000000000000 @3 +1m2 +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +#2004480000 +b100 i3 +b0 l3 +b100 f3 +b10011111111 Z3 +0G/ +0S0 +0*1 +0_1 +062 +b100111111111111111111111111 1 +b100111111111111111111111111 C3 +0k2 +b1 20 +b10 h3 +0j3 +b0 =0 +0?0 +b0 /0 +010 +b11111111000000000000000000000000 2 +b11111111000000000000000000000000 @3 +1~/ +#2004490000 +b0 i3 +b0 f3 +b11111111 Z3 +b111111111111111111111111 1 +b111111111111111111111111 C3 +0|/ +1! +#2004500000 +0z/ +0(1 +0]1 +042 +0i2 +b10 g/ +b1 #/ +1%/ +b1 X/ +1Z/ +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0r. +0I/ +0U0 +0,1 +0a1 +082 +b100000000000000000000000000 2 +b100000000000000000000000000 @3 +0m2 +0K/ +0W0 +0.1 +0c1 +0:2 +b1001111111111111111111111111 6 +0o2 +b11111011000000000000000000000000 " +b11111011000000000000000000000000 3 +b11111011000000000000000000000000 B3 +b10 a/ +b10 d/ +b10 e/ +0o/ +b0 J/ +b0 Q/ +b0 T/ +0q/ +#2004510000 +b1011 i3 +b1111 l3 +b11111011 f3 +b1111101111111111 Z3 +0Q0 +1p. +1G/ +1S0 +1*1 +1_1 +162 +b11111011111111111111111111111111 1 +b11111011111111111111111111111111 C3 +1k2 +b0 k3 +b0 n3 +b1 /0 +110 +b1 \3 +0g3 +b0 2 +b0 @3 +0~/ +b1111111111111111111111111 6 +0"0 +b11111111000000000000000000000000 " +b11111111000000000000000000000000 3 +b11111111000000000000000000000000 B3 +#2004520000 +b1111 i3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1|/ +#2004530000 +1E/ +1z/ +1(1 +1]1 +142 +1i2 +b0 Y/ +b1 i/ +1t. +1K/ +1W0 +1.1 +1c1 +1:2 +b111110111111111111111111111111111 6 +1o2 +b100000000000000000000000000 " +b100000000000000000000000000 3 +b100000000000000000000000000 B3 +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 S/ +b0 V/ +b0 W/ +#2004540000 +1Q0 +b1 k3 +b11 n3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1"0 +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +#2004550000 +b11 k3 +#2004560000 +b10 >0 +b10 J1 +b10 !2 +b10 V2 +b10 -3 +b0 [/ +b1 f/ +1h/ +1M/ +1p/ +b1100001 H/ +b1100001 _/ +b1100001 b/ +0r/ +1t/ +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 80 +b10 ;0 +b10 <0 +b10 D1 +b10 G1 +b10 H1 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0F0 +b0 !0 +b0 (0 +b0 +0 +0H0 +0R1 +b0 -1 +b0 41 +b0 71 +0T1 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +053 +b0 n2 +b0 u2 +b0 x2 +073 +00 +#2004570000 +b10 s0 +b10 h3 +1m3 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +0! +b10 m0 +b10 p0 +b10 q0 +0{0 +b0 V0 +b0 ]0 +b0 `0 +0}0 +#2004580000 +b11 h3 +1j3 +#2004590000 +b0 g/ +b0 >0 +b0 J1 +b0 !2 +b0 V2 +b0 -3 +b0 00 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +b1 @0 +b1 L1 +b1 #2 +b1 X2 +b1 /3 +b0 X/ +0Z/ +b10000000000000000000000000 2 +b10000000000000000000000000 @3 +1I/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 *0 +b0 -0 +b0 .0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1o/ +b1010 J/ +b1010 Q/ +b1010 T/ +1q/ +1F0 +b1010 !0 +b1010 (0 +b1010 +0 +1H0 +1R1 +b1010 -1 +b1010 41 +b1010 71 +1T1 +1)2 +b1010 b1 +b1010 i1 +b1010 l1 +1+2 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +1. +10 +#2004600000 +b1101 i3 +b11111101 f3 +b1111110111111111 Z3 +b0 s0 +b0 e0 +b11111101111111111111111111111111 1 +b11111101111111111111111111111111 C3 +0G/ +b1 u0 +b0 m0 +b0 p0 +b0 q0 +b0 _0 +b0 b0 +b0 c0 +1{0 +b1010 V0 +b1010 ]0 +b1010 `0 +1}0 +#2004610000 +b11 \3 +1g3 +#2004620000 +0z/ +b10 Y/ +b10 00 +b10 <1 +b10 q1 +b10 H2 +b10 }2 +b0 i/ +b0 @0 +b0 L1 +b0 #2 +b0 X2 +b0 /3 +b0 20 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b1 =0 +1?0 +b1 I1 +1K1 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111111011111111111111111111111111 6 +0K/ +b10000000000000000000000000 " +b10000000000000000000000000 3 +b10000000000000000000000000 B3 +b10 S/ +b10 V/ +b10 W/ +b10 *0 +b10 -0 +b10 .0 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2004630000 +b10 e0 +b10 k3 +b0 u0 +b0 g0 +b1 r0 +1t0 +b10 _0 +b10 b0 +b10 c0 +#2004640000 +b11 D3 +1[3 +#2004650000 +b1 [/ +b1 20 +b1 >1 +b1 s1 +b1 J2 +b1 !3 +b0 f/ +0h/ +b0 =0 +0?0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 /0 +010 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1~/ +1,1 +1a1 +182 +b11110110000000000000000000000000 2 +b11110110000000000000000000000000 @3 +1m2 +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +#2004660000 +b1001 i3 +b0 l3 +b1001 f3 +b100111111111 Z3 +0|/ +0*1 +0_1 +062 +b1001111111111111111111111111 1 +b1001111111111111111111111111 C3 +0k2 +b1 g0 +b10 h3 +0j3 +b0 r0 +0t0 +b0 d0 +0f0 +b11111110000000000000000000000000 2 +b11111110000000000000000000000000 @3 +1U0 +#2004670000 +b1 i3 +b1 f3 +b111111111 Z3 +b1111111111111111111111111 1 +b1111111111111111111111111 C3 +0S0 +1! +#2004680000 +0Q0 +0]1 +042 +0i2 +b10 >0 +b1 X/ +1Z/ +b1 /0 +110 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0I/ +0~/ +0,1 +0a1 +082 +b1000000000000000000000000000 2 +b1000000000000000000000000000 @3 +0m2 +0"0 +0.1 +0c1 +0:2 +b10011111111111111111111111111 6 +0o2 +b11110110000000000000000000000000 " +b11110110000000000000000000000000 3 +b11110110000000000000000000000000 B3 +b10 80 +b10 ;0 +b10 <0 +0F0 +b0 !0 +b0 (0 +b0 +0 +0H0 +#2004690000 +b111 i3 +b1111 l3 +b11110111 f3 +b1111011111111111 Z3 +0(1 +1G/ +1|/ +1*1 +1_1 +162 +b11110111111111111111111111111111 1 +b11110111111111111111111111111111 C3 +1k2 +b0 k3 +b0 n3 +b1 d0 +1f0 +b1 \3 +0g3 +b0 2 +b0 @3 +0U0 +b11111111111111111111111111 6 +0W0 +b11111110000000000000000000000000 " +b11111110000000000000000000000000 3 +b11111110000000000000000000000000 B3 +#2004700000 +b1111 i3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1S0 +#2004710000 +1z/ +1Q0 +1]1 +142 +1i2 +b0 00 +b1 @0 +1K/ +1"0 +1.1 +1c1 +1:2 +b111101111111111111111111111111111 6 +1o2 +b1000000000000000000000000000 " +b1000000000000000000000000000 3 +b1000000000000000000000000000 B3 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 *0 +b0 -0 +b0 .0 +#2004720000 +1(1 +b1 k3 +b11 n3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1W0 +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +#2004730000 +b11 k3 +#2004740000 +b10 s0 +b10 !2 +b10 V2 +b10 -3 +b0 20 +b1 =0 +1?0 +1$0 +1G0 +b1100001 }/ +b1100001 60 +b1100001 90 +0I0 +1K0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 m0 +b10 p0 +b10 q0 +b10 y1 +b10 |1 +b10 }1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0{0 +b0 V0 +b0 ]0 +b0 `0 +0}0 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +053 +b0 n2 +b0 u2 +b0 x2 +073 +00 +#2004750000 +b10 J1 +b10 h3 +1m3 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +0! +b10 D1 +b10 G1 +b10 H1 +0R1 +b0 -1 +b0 41 +b0 71 +0T1 +#2004760000 +b11 h3 +1j3 +#2004770000 +b0 >0 +b0 s0 +b0 !2 +b0 V2 +b0 -3 +b0 e0 +b0 q1 +b0 H2 +b0 }2 +b1 u0 +b1 #2 +b1 X2 +b1 /3 +b0 /0 +010 +b100000000000000000000000000 2 +b100000000000000000000000000 @3 +1~/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 _0 +b0 b0 +b0 c0 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1F0 +b1010 !0 +b1010 (0 +b1010 +0 +1H0 +1{0 +b1010 V0 +b1010 ]0 +b1010 `0 +1}0 +1)2 +b1010 b1 +b1010 i1 +b1010 l1 +1+2 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +1. +10 +#2004780000 +b1011 i3 +b11111011 f3 +b1111101111111111 Z3 +b0 J1 +b0 <1 +b11111011111111111111111111111111 1 +b11111011111111111111111111111111 C3 +0|/ +b1 L1 +b0 D1 +b0 G1 +b0 H1 +b0 61 +b0 91 +b0 :1 +1R1 +b1010 -1 +b1010 41 +b1010 71 +1T1 +#2004790000 +b11 \3 +1g3 +#2004800000 +0Q0 +b10 00 +b10 e0 +b10 q1 +b10 H2 +b10 }2 +b0 @0 +b0 u0 +b0 #2 +b0 X2 +b0 /3 +b0 g0 +b0 s1 +b0 J2 +b0 !3 +b1 r0 +1t0 +b1 ~1 +1"2 +b1 U2 +1W2 +b1 ,3 +1.3 +b111110111111111111111111111111111 6 +0"0 +b100000000000000000000000000 " +b100000000000000000000000000 3 +b100000000000000000000000000 B3 +b10 *0 +b10 -0 +b10 .0 +b10 _0 +b10 b0 +b10 c0 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2004810000 +b10 <1 +b1 k3 +b0 L1 +b0 >1 +b1 I1 +1K1 +b10 61 +b10 91 +b10 :1 +#2004820000 +b11 D3 +1[3 +#2004830000 +b1 20 +b1 g0 +b1 s1 +b1 J2 +b1 !3 +b0 =0 +0?0 +b0 r0 +0t0 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 d0 +0f0 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +1U0 +1a1 +182 +b11101100000000000000000000000000 2 +b11101100000000000000000000000000 @3 +1m2 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +#2004840000 +b11 i3 +b1 l3 +b10011 f3 +b1001111111111 Z3 +0S0 +0_1 +062 +b10011111111111111111111111111 1 +b10011111111111111111111111111 C3 +0k2 +b1 >1 +b10 h3 +0j3 +b0 I1 +0K1 +b0 ;1 +0=1 +b11111100000000000000000000000000 2 +b11111100000000000000000000000000 @3 +1,1 +#2004850000 +b0 l3 +b11 f3 +b1111111111 Z3 +b11111111111111111111111111 1 +b11111111111111111111111111 C3 +0*1 +1! +#2004860000 +0(1 +042 +0i2 +b10 s0 +b1 /0 +110 +b1 d0 +1f0 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +0~/ +0U0 +0a1 +082 +b10000000000000000000000000000 2 +b10000000000000000000000000000 @3 +0m2 +0W0 +0c1 +0:2 +b100111111111111111111111111111 6 +0o2 +b11101100000000000000000000000000 " +b11101100000000000000000000000000 3 +b11101100000000000000000000000000 B3 +b10 m0 +b10 p0 +b10 q0 +0{0 +b0 V0 +b0 ]0 +b0 `0 +0}0 +#2004870000 +b1111 i3 +b1110 l3 +b11101111 f3 +b1110111111111111 Z3 +0]1 +1|/ +1S0 +1_1 +162 +b11101111111111111111111111111111 1 +b11101111111111111111111111111111 C3 +1k2 +b0 n3 +b1 ;1 +1=1 +b1 \3 +0g3 +b0 2 +b0 @3 +0,1 +b111111111111111111111111111 6 +0.1 +b11111100000000000000000000000000 " +b11111100000000000000000000000000 3 +b11111100000000000000000000000000 B3 +#2004880000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1*1 +#2004890000 +1Q0 +1(1 +142 +1i2 +b0 e0 +b1 u0 +1"0 +1W0 +1c1 +1:2 +b111011111111111111111111111111111 6 +1o2 +b10000000000000000000000000000 " +b10000000000000000000000000000 3 +b10000000000000000000000000000 B3 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 _0 +b0 b0 +b0 c0 +#2004900000 +1]1 +b11 k3 +b10 n3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1.1 +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +#2004910000 +b11 n3 +#2004920000 +b10 J1 +b10 V2 +b10 -3 +b0 g0 +b1 r0 +1t0 +1Y0 +1|0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0~0 +1"1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 D1 +b10 G1 +b10 H1 +b10 P2 +b10 S2 +b10 T2 +b10 '3 +b10 *3 +b10 +3 +0R1 +b0 -1 +b0 41 +b0 71 +0T1 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +053 +b0 n2 +b0 u2 +b0 x2 +073 +00 +#2004930000 +b10 !2 +b1 h3 +1j3 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +0! +b10 y1 +b10 |1 +b10 }1 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +#2004940000 +b11 h3 +1m3 +#2004950000 +b0 s0 +b0 J1 +b0 V2 +b0 -3 +b0 <1 +b0 H2 +b0 }2 +b1 L1 +b1 X2 +b1 /3 +b0 d0 +0f0 +b1000000000000000000000000000 2 +b1000000000000000000000000000 @3 +1U0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 61 +b0 91 +b0 :1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +1{0 +b1010 V0 +b1010 ]0 +b1010 `0 +1}0 +1R1 +b1010 -1 +b1010 41 +b1010 71 +1T1 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +1. +10 +#2004960000 +b111 i3 +b11110111 f3 +b1111011111111111 Z3 +b0 !2 +b0 q1 +b11110111111111111111111111111111 1 +b11110111111111111111111111111111 C3 +0S0 +b1 #2 +b0 y1 +b0 |1 +b0 }1 +b0 k1 +b0 n1 +b0 o1 +1)2 +b1010 b1 +b1010 i1 +b1010 l1 +1+2 +#2004970000 +b11 \3 +1g3 +#2004980000 +0(1 +b10 e0 +b10 <1 +b10 H2 +b10 }2 +b0 u0 +b0 L1 +b0 X2 +b0 /3 +b0 >1 +b0 J2 +b0 !3 +b1 I1 +1K1 +b1 U2 +1W2 +b1 ,3 +1.3 +b111101111111111111111111111111111 6 +0W0 +b1000000000000000000000000000 " +b1000000000000000000000000000 3 +b1000000000000000000000000000 B3 +b10 _0 +b10 b0 +b10 c0 +b10 61 +b10 91 +b10 :1 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2004990000 +b10 q1 +b1 k3 +b0 #2 +b0 s1 +b1 ~1 +1"2 +b10 k1 +b10 n1 +b10 o1 +#2005000000 +b11 D3 +1[3 +#2005010000 +b1 g0 +b1 >1 +b1 J2 +b1 !3 +b0 r0 +0t0 +b0 I1 +0K1 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 ;1 +0=1 +b0 G2 +0I2 +b0 |2 +0~2 +1,1 +182 +b11011000000000000000000000000000 2 +b11011000000000000000000000000000 @3 +1m2 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +#2005020000 +b10 l3 +b100111 f3 +b10011111111111 Z3 +0*1 +062 +b100111111111111111111111111111 1 +b100111111111111111111111111111 C3 +0k2 +b1 s1 +b10 h3 +0j3 +b0 ~1 +0"2 +b0 p1 +0r1 +b11111000000000000000000000000000 2 +b11111000000000000000000000000000 @3 +1a1 +#2005030000 +b0 l3 +b111 f3 +b11111111111 Z3 +b111111111111111111111111111 1 +b111111111111111111111111111 C3 +0_1 +1! +#2005040000 +0]1 +0i2 +b10 J1 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 G2 +1I2 +b1 |2 +1~2 +0U0 +0,1 +082 +b100000000000000000000000000000 2 +b100000000000000000000000000000 @3 +0m2 +0.1 +0:2 +b1001111111111111111111111111111 6 +0o2 +b11011000000000000000000000000000 " +b11011000000000000000000000000000 3 +b11011000000000000000000000000000 B3 +b10 D1 +b10 G1 +b10 H1 +0R1 +b0 -1 +b0 41 +b0 71 +0T1 +#2005050000 +b1111 i3 +b1101 l3 +b11011111 f3 +b1101111111111111 Z3 +042 +1S0 +1*1 +162 +b11011111111111111111111111111111 1 +b11011111111111111111111111111111 C3 +1k2 +b0 n3 +b1 p1 +1r1 +b1 \3 +0g3 +b0 2 +b0 @3 +0a1 +b1111111111111111111111111111 6 +0c1 +b11111000000000000000000000000000 " +b11111000000000000000000000000000 3 +b11111000000000000000000000000000 B3 +#2005060000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1_1 +#2005070000 +1(1 +1]1 +1i2 +b0 <1 +b1 L1 +1W0 +1.1 +1:2 +b110111111111111111111111111111111 6 +1o2 +b100000000000000000000000000000 " +b100000000000000000000000000000 3 +b100000000000000000000000000000 B3 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +0. +b0 61 +b0 91 +b0 :1 +#2005080000 +142 +b11 k3 +b10 n3 +b0 h3 +0m3 +b111111111111111111111111111111111 6 +1c1 +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +#2005090000 +b11 n3 +#2005100000 +b10 !2 +b10 -3 +b0 >1 +b1 I1 +1K1 +101 +1S1 +b1100001 +1 +b1100001 B1 +b1100001 E1 +0U1 +1W1 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +b10 y1 +b10 |1 +b10 }1 +b10 '3 +b10 *3 +b10 +3 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +053 +b0 n2 +b0 u2 +b0 x2 +073 +00 +#2005110000 +b10 V2 +b1 h3 +1j3 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +0! +b10 P2 +b10 S2 +b10 T2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +#2005120000 +b11 h3 +1m3 +#2005130000 +b0 J1 +b0 !2 +b0 -3 +b0 q1 +b0 }2 +b1 #2 +b1 /3 +b0 ;1 +0=1 +b10000000000000000000000000000 2 +b10000000000000000000000000000 @3 +1,1 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 '3 +b0 *3 +b0 +3 +b0 k1 +b0 n1 +b0 o1 +b0 w2 +b0 z2 +b0 {2 +1R1 +b1010 -1 +b1010 41 +b1010 71 +1T1 +1)2 +b1010 b1 +b1010 i1 +b1010 l1 +1+2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +1. +10 +#2005140000 +b1110 l3 +b11101111 f3 +b1110111111111111 Z3 +b0 V2 +b0 H2 +b11101111111111111111111111111111 1 +b11101111111111111111111111111111 C3 +0*1 +b1 X2 +b0 P2 +b0 S2 +b0 T2 +b0 B2 +b0 E2 +b0 F2 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +#2005150000 +b11 \3 +1g3 +#2005160000 +0]1 +b10 <1 +b10 q1 +b10 }2 +b0 L1 +b0 #2 +b0 /3 +b0 s1 +b0 !3 +b1 ~1 +1"2 +b1 ,3 +1.3 +b111011111111111111111111111111111 6 +0.1 +b10000000000000000000000000000 " +b10000000000000000000000000000 3 +b10000000000000000000000000000 B3 +b10 61 +b10 91 +b10 :1 +b10 k1 +b10 n1 +b10 o1 +b10 w2 +b10 z2 +b10 {2 +#2005170000 +b10 H2 +b10 n3 +b0 X2 +b0 J2 +b1 U2 +1W2 +b10 B2 +b10 E2 +b10 F2 +#2005180000 +b11 D3 +1[3 +#2005190000 +b1 >1 +b1 s1 +b1 !3 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 ,3 +0.3 +b0 p1 +0r1 +b0 |2 +0~2 +1a1 +b10110000000000000000000000000000 2 +b10110000000000000000000000000000 @3 +1m2 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +#2005200000 +b100 l3 +b1001111 f3 +b100111111111111 Z3 +0_1 +b1001111111111111111111111111111 1 +b1001111111111111111111111111111 C3 +0k2 +b1 J2 +b1 h3 +0m3 +b0 U2 +0W2 +b0 G2 +0I2 +b11110000000000000000000000000000 2 +b11110000000000000000000000000000 @3 +182 +#2005210000 +b0 l3 +b1111 f3 +b111111111111 Z3 +b1111111111111111111111111111 1 +b1111111111111111111111111111 C3 +062 +1! +#2005220000 +042 +b10 !2 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 |2 +1~2 +0,1 +0a1 +b1000000000000000000000000000000 2 +b1000000000000000000000000000000 @3 +0m2 +0c1 +b10011111111111111111111111111111 6 +0o2 +b10110000000000000000000000000000 " +b10110000000000000000000000000000 3 +b10110000000000000000000000000000 B3 +b10 y1 +b10 |1 +b10 }1 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +#2005230000 +b1011 l3 +b10111111 f3 +b1011111111111111 Z3 +0i2 +1*1 +1_1 +b10111111111111111111111111111111 1 +b10111111111111111111111111111111 C3 +1k2 +b0 n3 +b1 G2 +1I2 +b1 \3 +0g3 +b0 2 +b0 @3 +082 +b11111111111111111111111111111 6 +0:2 +b11110000000000000000000000000000 " +b11110000000000000000000000000000 3 +b11110000000000000000000000000000 B3 +#2005240000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +162 +#2005250000 +1]1 +142 +b0 q1 +b1 #2 +1.1 +1c1 +b101111111111111111111111111111111 6 +1o2 +b1000000000000000000000000000000 " +b1000000000000000000000000000000 3 +b1000000000000000000000000000000 B3 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0$ +0. +b0 k1 +b0 n1 +b0 o1 +#2005260000 +1i2 +b1 n3 +b111111111111111111111111111111111 6 +1:2 +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +#2005270000 +b11 n3 +#2005280000 +b10 V2 +b0 s1 +b1 ~1 +1"2 +1e1 +1*2 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0,2 +1.2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1$ +b10 P2 +b10 S2 +b10 T2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +00 +#2005290000 +b10 -3 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +0! +b10 '3 +b10 *3 +b10 +3 +053 +b0 n2 +b0 u2 +b0 x2 +073 +#2005300000 +b11 h3 +1m3 +#2005310000 +b0 !2 +b0 V2 +b0 H2 +b1 X2 +b0 p1 +0r1 +b100000000000000000000000000000 2 +b100000000000000000000000000000 @3 +1a1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 B2 +b0 E2 +b0 F2 +1)2 +b1010 b1 +b1010 i1 +b1010 l1 +1+2 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +1. +10 +#2005320000 +b1101 l3 +b11011111 f3 +b1101111111111111 Z3 +b0 -3 +b0 }2 +b11011111111111111111111111111111 1 +b11011111111111111111111111111111 C3 +0_1 +b1 /3 +b0 '3 +b0 *3 +b0 +3 +b0 w2 +b0 z2 +b0 {2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +#2005330000 +b11 \3 +1g3 +#2005340000 +042 +b10 q1 +b10 H2 +b0 #2 +b0 X2 +b0 J2 +b1 U2 +1W2 +b110111111111111111111111111111111 6 +0c1 +b100000000000000000000000000000 " +b100000000000000000000000000000 3 +b100000000000000000000000000000 B3 +b10 k1 +b10 n1 +b10 o1 +b10 B2 +b10 E2 +b10 F2 +#2005350000 +b10 }2 +b10 n3 +b0 /3 +b0 !3 +b1 ,3 +1.3 +b10 w2 +b10 z2 +b10 {2 +#2005360000 +b11 D3 +1[3 +#2005370000 +b1 s1 +b1 J2 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 G2 +0I2 +b1100000000000000000000000000000 2 +b1100000000000000000000000000000 @3 +182 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +#2005380000 +b1001 l3 +b10011111 f3 +b1001111111111111 Z3 +b10011111111111111111111111111111 1 +b10011111111111111111111111111111 C3 +062 +b1 !3 +b1 h3 +0m3 +b0 ,3 +0.3 +b0 |2 +0~2 +b11100000000000000000000000000000 2 +b11100000000000000000000000000000 @3 +1m2 +#2005390000 +b1 l3 +b11111 f3 +b1111111111111 Z3 +b11111111111111111111111111111 1 +b11111111111111111111111111111 C3 +0k2 +1! +#2005400000 +0i2 +b10 V2 +b1 p1 +1r1 +b1 G2 +1I2 +0a1 +b10000000000000000000000000000000 2 +b10000000000000000000000000000000 @3 +082 +b100111111111111111111111111111111 6 +0:2 +b1100000000000000000000000000000 " +b1100000000000000000000000000000 3 +b1100000000000000000000000000000 B3 +b10 P2 +b10 S2 +b10 T2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +#2005410000 +b111 l3 +b1111111 f3 +b111111111111111 Z3 +1_1 +b1111111111111111111111111111111 1 +b1111111111111111111111111111111 C3 +162 +b0 n3 +b1 |2 +1~2 +b1 \3 +0g3 +b0 2 +b0 @3 +0m2 +b111111111111111111111111111111 6 +0o2 +b11100000000000000000000000000000 " +b11100000000000000000000000000000 3 +b11100000000000000000000000000000 B3 +#2005420000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1k2 +#2005430000 +142 +1i2 +b0 H2 +b1 X2 +1c1 +b11111111111111111111111111111111 6 +1:2 +b10000000000000000000000000000000 " +b10000000000000000000000000000000 3 +b10000000000000000000000000000000 B3 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +b0 B2 +b0 E2 +b0 F2 +#2005440000 +b1 n3 +b111111111111111111111111111111111 6 +1o2 +b1 D3 +0[3 +b0 " +b0 3 +b0 B3 +0$ +0. +#2005450000 +b11 n3 +#2005460000 +b10 -3 +b0 J2 +b1 U2 +1W2 +1<2 +1_2 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +b10 '3 +b10 *3 +b10 +3 +053 +b0 n2 +b0 u2 +b0 x2 +073 +#2005470000 +1$ +0! +00 +#2005480000 +b11 h3 +1m3 +#2005490000 +b0 V2 +b0 -3 +b0 }2 +b1 /3 +b0 G2 +0I2 +b1000000000000000000000000000000 2 +b1000000000000000000000000000000 @3 +182 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b0 w2 +b0 z2 +b0 {2 +1^2 +b1010 92 +b1010 @2 +b1010 C2 +1`2 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +#2005500000 +b1011 l3 +b10111111 f3 +b1011111111111111 Z3 +b10111111111111111111111111111111 1 +b10111111111111111111111111111111 C3 +062 +1. +10 +#2005510000 +b11 \3 +1g3 +#2005520000 +0i2 +b10 H2 +b10 }2 +b0 X2 +b0 /3 +b0 !3 +b1 ,3 +1.3 +b101111111111111111111111111111111 6 +0:2 +b1000000000000000000000000000000 " +b1000000000000000000000000000000 3 +b1000000000000000000000000000000 B3 +b10 B2 +b10 E2 +b10 F2 +b10 w2 +b10 z2 +b10 {2 +#2005530000 +b1 n3 +#2005540000 +b11 D3 +1[3 +#2005550000 +b1 J2 +b1 !3 +b0 U2 +0W2 +b0 ,3 +0.3 +b0 |2 +0~2 +b11000000000000000000000000000000 2 +b11000000000000000000000000000000 @3 +1m2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +#2005560000 +b11 l3 +b111111 f3 +b11111111111111 Z3 +b111111111111111111111111111111 1 +b111111111111111111111111111111 C3 +0k2 +b1 h3 +0m3 +#2005570000 +1! +#2005580000 +b10 -3 +b1 G2 +1I2 +b1 |2 +1~2 +082 +b0 2 +b0 @3 +0m2 +b1111111111111111111111111111111 6 +0o2 +b11000000000000000000000000000000 " +b11000000000000000000000000000000 3 +b11000000000000000000000000000000 B3 +b10 '3 +b10 *3 +b10 +3 +053 +b0 n2 +b0 u2 +b0 x2 +073 +#2005590000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +162 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1k2 +b1 \3 +0g3 +#2005610000 +1i2 +b0 }2 +b1 /3 +1:2 +b111111111111111111111111111111111 6 +1o2 +b0 " +b0 3 +b0 B3 +0$ +0. +b0 w2 +b0 z2 +b0 {2 +#2005620000 +b11 n3 +b1 D3 +0[3 +#2005640000 +b0 !3 +b1 ,3 +1.3 +1q2 +163 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +1$ +00 +#2005650000 +b11 h3 +1m3 +0! +#2005670000 +b0 -3 +b0 |2 +0~2 +b10000000000000000000000000000000 2 +b10000000000000000000000000000000 @3 +1m2 +b0 '3 +b0 *3 +b0 +3 +153 +b1010 n2 +b1010 u2 +b1010 x2 +173 +1. +10 +#2005680000 +b111 l3 +b1111111 f3 +b111111111111111 Z3 +b1111111111111111111111111111111 1 +b1111111111111111111111111111111 C3 +0k2 +b11 \3 +1g3 +#2005700000 +b10 }2 +b0 /3 +b11111111111111111111111111111111 6 +0o2 +b10000000000000000000000000000000 " +b10000000000000000000000000000000 3 +b10000000000000000000000000000000 B3 +b10 w2 +b10 z2 +b10 {2 +#2005710000 +b1 n3 +b11 D3 +1[3 +#2005730000 +b1 !3 +b0 ,3 +0.3 +0$ +0. +#2005740000 +b1 h3 +0m3 +1! +#2005760000 +b1 |2 +1~2 +b0 2 +b0 @3 +0m2 +1. +00 +#2005770000 +b1111 l3 +b11111111 f3 +b1111111111111111 Z3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1k2 +b1 \3 +0g3 +#2005790000 +b111111111111111111111111111111111 6 +1o2 +b0 " +b0 3 +b0 B3 +#2005800000 +b11 n3 +b1 D3 +0[3 +#2005820000 +1$ +0. +#2005830000 +b11 h3 +1m3 +0! +#2005850000 +1. +10 +#2005860000 +b11 \3 +1g3 +#2005890000 +b11 D3 +1[3 +#2005920000 +1! +#3000000000 +1: +0F" +0D" +1e2 +b1 & +b1 , +b10000000000000000000000000000000 % +b10000000000000000000000000000000 + +#3000010000 +0; +1G" +1E" +0f2 +#3000020000 +b100001 ? +b100001 V +b100001 Y +0d +b11110001 K" +b11110001 b" +b11110001 e" +b100001 l2 +b100001 %3 +b100001 (3 +033 +0/ +#3000030000 +1* +b10100101 ? +b10100101 V +b10100101 Y +1E +b1100001 K" +b1100001 b" +b1100001 e" +0S" +b10100101 l2 +b10100101 %3 +b10100101 (3 +1r2 +143 +093 +1;3 +#3000040000 +0j +#3000050000 +0g +063 +#3000060000 +00 +1>3 +b10100100 ? +b10100100 V +b10100100 Y +0D +1F +b1010 M" +b1010 T" +b1010 W" +0O" +0q2 +1s2 +b10100110 l2 +b10100110 %3 +b10100110 (3 +183 +0:3 +#3000070000 +b10100110 ? +b10100110 V +b10100110 Y +1i +0k +#3000080000 +b10 A +b10 H +b10 K +0f +#3000090000 +b10 -3 +b10 '3 +b10 *3 +b10 +3 +15 +b11 A +b11 H +b11 K +1C +b1011 n2 +b1011 u2 +b1011 x2 +1p2 +#3000100000 +b10 ^ +b10 X +b10 [ +b10 \ +b1 A +b1 H +b1 K +0h +#3000120000 +b1 /3 +1- +#3000130000 +b0 P +b1 ` +b0 J +b0 M +b0 N +#3000150000 +b1 ,3 +1.3 +1# +#3000160000 +b0 R +b1 ] +1_ +#3000180000 +b10000000000000000000000000000000 2 +b10000000000000000000000000000000 @3 +1m2 +#3000190000 +b111 l3 +b1111111 f3 +b111111111111111 Z3 +b1111111111111111111111111111111 1 +b1111111111111111111111111111111 C3 +0k2 +b0 O +0Q +b10000000000000000000000000000001 2 +b10000000000000000000000000000001 @3 +1@ +#3000200000 +b1110 K3 +b11111110 H3 +b1111111111111110 E3 +b1111111111111111111111111111110 1 +b1111111111111111111111111111110 C3 +0> +#3000210000 +b10000000000000000000000000000000 " +b10000000000000000000000000000000 3 +b10000000000000000000000000000000 B3 +#3000220000 +0q +b1 n3 +b111111111111111111111111111111101 6 +0B +b10000000000000000000000000000001 " +b10000000000000000000000000000001 3 +b10000000000000000000000000000001 B3 +#3000230000 +b10 M3 +#3000240000 +0. +#3000250000 +b1 h3 +0m3 +0y +0>" +b1100010 t +b1100010 -" +b1100010 0" +1@" +0B" +#3000260000 +b10 J3 +0L3 +#3000270000 +0- +#3000280000 +b10 5" +b1 \3 +0g3 +b10 /" +b10 2" +b10 3" +0=" +b0 v +b0 } +b0 "" +0?" +#3000290000 +b10 G3 +0I3 +#3000300000 +0# +#3000310000 +b0 '" +b1 7" +b1 D3 +0[3 +b0 !" +b0 $" +b0 %" +#3000320000 +b0 D3 +0F3 +#3000340000 +b0 )" +b1 4" +16" +0! +#3000370000 +b0 &" +0(" +b10000000000000000000000000000011 2 +b10000000000000000000000000000011 @3 +1u +#3000380000 +b1100 K3 +b11111100 H3 +b1111111111111100 E3 +b1111111111111111111111111111100 1 +b1111111111111111111111111111100 C3 +0s +#3000400000 +0H" +b111111111111111111111111111111001 6 +0w +b10000000000000000000000000000011 " +b10000000000000000000000000000011 3 +b10000000000000000000000000000011 B3 +#3000430000 +0P" +0s" +b1100010 K" +b1100010 b" +b1100010 e" +1u" +0w" +#3000460000 +b10 j" +b10 d" +b10 g" +b10 h" +0r" +b0 M" +b0 T" +b0 W" +0t" +#3000490000 +b0 \" +b1 l" +b0 V" +b0 Y" +b0 Z" +#3000520000 +b0 ^" +b1 i" +1k" +#3000550000 +b0 [" +0]" +b10000000000000000000000000000111 2 +b10000000000000000000000000000111 @3 +1L" +#3000560000 +b1000 K3 +b11111000 H3 +b1111111111111000 E3 +b1111111111111111111111111111000 1 +b1111111111111111111111111111000 C3 +0J" +#3000580000 +0}" +b111111111111111111111111111110001 6 +0N" +b10000000000000000000000000000111 " +b10000000000000000000000000000111 3 +b10000000000000000000000000000111 B3 +#3000590000 +b0 M3 +#3000610000 +0'# +0J# +b1100010 "# +b1100010 9# +b1100010 <# +1L# +0N# +#3000640000 +b10 A# +b10 ;# +b10 ># +b10 ?# +0I# +b0 $# +b0 +# +b0 .# +0K# +#3000670000 +b0 3# +b1 C# +b0 -# +b0 0# +b0 1# +#3000700000 +b0 5# +b1 @# +1B# +#3000730000 +b0 2# +04# +b10000000000000000000000000001111 2 +b10000000000000000000000000001111 @3 +1## +#3000740000 +b0 K3 +b11110000 H3 +b1111111111110000 E3 +b1111111111111111111111111110000 1 +b1111111111111111111111111110000 C3 +0!# +#3000760000 +0T# +b111111111111111111111111111100001 6 +0%# +b10000000000000000000000000001111 " +b10000000000000000000000000001111 3 +b10000000000000000000000000001111 B3 +#3000790000 +0\# +0!$ +b1100010 W# +b1100010 n# +b1100010 q# +1#$ +0%$ +#3000820000 +b10 v# +b10 p# +b10 s# +b10 t# +0~# +b0 Y# +b0 `# +b0 c# +0"$ +#3000850000 +b0 h# +b1 x# +b0 b# +b0 e# +b0 f# +#3000880000 +b0 j# +b1 u# +1w# +#3000910000 +b0 g# +0i# +b10000000000000000000000000011111 2 +b10000000000000000000000000011111 @3 +1X# +#3000920000 +b1110 N3 +b11100000 H3 +b1111111111100000 E3 +b1111111111111111111111111100000 1 +b1111111111111111111111111100000 C3 +0V# +#3000940000 +0+$ +b111111111111111111111111111000001 6 +0Z# +b10000000000000000000000000011111 " +b10000000000000000000000000011111 3 +b10000000000000000000000000011111 B3 +#3000950000 +b10 P3 +#3000970000 +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +#3000980000 +b0 J3 +0O3 +#3001000000 +b10 M$ +b10 G$ +b10 J$ +b10 K$ +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +#3001030000 +b0 ?$ +b1 O$ +b0 9$ +b0 <$ +b0 =$ +#3001060000 +b0 A$ +b1 L$ +1N$ +#3001090000 +b0 >$ +0@$ +b10000000000000000000000000111111 2 +b10000000000000000000000000111111 @3 +1/$ +#3001100000 +b1100 N3 +b11000000 H3 +b1111111111000000 E3 +b1111111111111111111111111000000 1 +b1111111111111111111111111000000 C3 +0-$ +#3001120000 +0`$ +b111111111111111111111111110000001 6 +01$ +b10000000000000000000000000111111 " +b10000000000000000000000000111111 3 +b10000000000000000000000000111111 B3 +#3001150000 +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +#3001180000 +b10 $% +b10 |$ +b10 !% +b10 "% +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +#3001210000 +b0 t$ +b1 &% +b0 n$ +b0 q$ +b0 r$ +#3001240000 +b0 v$ +b1 #% +1%% +#3001270000 +b0 s$ +0u$ +b10000000000000000000000001111111 2 +b10000000000000000000000001111111 @3 +1d$ +#3001280000 +b1000 N3 +b10000000 H3 +b1111111110000000 E3 +b1111111111111111111111110000000 1 +b1111111111111111111111110000000 C3 +0b$ +#3001300000 +07% +b111111111111111111111111100000001 6 +0f$ +b10000000000000000000000001111111 " +b10000000000000000000000001111111 3 +b10000000000000000000000001111111 B3 +#3001310000 +b0 P3 +#3001330000 +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +#3001360000 +b10 Y% +b10 S% +b10 V% +b10 W% +0a% +b0 <% +b0 C% +b0 F% +0c% +#3001390000 +b0 K% +b1 [% +b0 E% +b0 H% +b0 I% +#3001420000 +b0 M% +b1 X% +1Z% +#3001450000 +b0 J% +0L% +b10000000000000000000000011111111 2 +b10000000000000000000000011111111 @3 +1;% +#3001460000 +b0 N3 +b0 H3 +b1111111100000000 E3 +b1111111111111111111111100000000 1 +b1111111111111111111111100000000 C3 +09% +#3001480000 +0l% +b111111111111111111111111000000001 6 +0=% +b10000000000000000000000011111111 " +b10000000000000000000000011111111 3 +b10000000000000000000000011111111 B3 +#3001510000 +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +#3001540000 +b10 0& +b10 *& +b10 -& +b10 .& +08& +b0 q% +b0 x% +b0 {% +0:& +#3001570000 +b0 "& +b1 2& +b0 z% +b0 }% +b0 ~% +#3001600000 +b0 $& +b1 /& +11& +#3001630000 +b0 !& +0#& +b10000000000000000000000111111111 2 +b10000000000000000000000111111111 @3 +1p% +#3001640000 +b1110 T3 +b11111110 Q3 +b1111111000000000 E3 +b1111111111111111111111000000000 1 +b1111111111111111111111000000000 C3 +0n% +#3001660000 +0C& +b111111111111111111111110000000001 6 +0r% +b10000000000000000000000111111111 " +b10000000000000000000000111111111 3 +b10000000000000000000000111111111 B3 +#3001670000 +b10 V3 +#3001690000 +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +#3001700000 +b10 S3 +0U3 +#3001720000 +b10 e& +b10 _& +b10 b& +b10 c& +0m& +b0 H& +b0 O& +b0 R& +0o& +#3001730000 +b0 G3 +0R3 +#3001750000 +b0 W& +b1 g& +b0 Q& +b0 T& +b0 U& +#3001780000 +b0 Y& +b1 d& +1f& +#3001810000 +b0 V& +0X& +b10000000000000000000001111111111 2 +b10000000000000000000001111111111 @3 +1G& +#3001820000 +b1100 T3 +b11111100 Q3 +b1111110000000000 E3 +b1111111111111111111110000000000 1 +b1111111111111111111110000000000 C3 +0E& +#3001840000 +0x& +b111111111111111111111100000000001 6 +0I& +b10000000000000000000001111111111 " +b10000000000000000000001111111111 3 +b10000000000000000000001111111111 B3 +#3001870000 +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +#3001900000 +b10 <' +b10 6' +b10 9' +b10 :' +0D' +b0 }& +b0 &' +b0 )' +0F' +#3001930000 +b0 .' +b1 >' +b0 (' +b0 +' +b0 ,' +#3001960000 +b0 0' +b1 ;' +1=' +#3001990000 +b0 -' +0/' +b10000000000000000000011111111111 2 +b10000000000000000000011111111111 @3 +1|& +#3002000000 +b1000 T3 +b11111000 Q3 +b1111100000000000 E3 +b1111111111111111111100000000000 1 +b1111111111111111111100000000000 C3 +0z& +#3002020000 +0O' +b111111111111111111111000000000001 6 +0~& +b10000000000000000000011111111111 " +b10000000000000000000011111111111 3 +b10000000000000000000011111111111 B3 +#3002030000 +b0 V3 +#3002050000 +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +#3002080000 +b10 q' +b10 k' +b10 n' +b10 o' +0y' +b0 T' +b0 [' +b0 ^' +0{' +#3002110000 +b0 c' +b1 s' +b0 ]' +b0 `' +b0 a' +#3002140000 +b0 e' +b1 p' +1r' +#3002170000 +b0 b' +0d' +b10000000000000000000111111111111 2 +b10000000000000000000111111111111 @3 +1S' +#3002180000 +b0 T3 +b11110000 Q3 +b1111000000000000 E3 +b1111111111111111111000000000000 1 +b1111111111111111111000000000000 C3 +0Q' +#3002200000 +0&( +b111111111111111111110000000000001 6 +0U' +b10000000000000000000111111111111 " +b10000000000000000000111111111111 3 +b10000000000000000000111111111111 B3 +#3002230000 +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +#3002260000 +b10 H( +b10 B( +b10 E( +b10 F( +0P( +b0 +( +b0 2( +b0 5( +0R( +#3002290000 +b0 :( +b1 J( +b0 4( +b0 7( +b0 8( +#3002320000 +b0 <( +b1 G( +1I( +#3002350000 +b0 9( +0;( +b10000000000000000001111111111111 2 +b10000000000000000001111111111111 @3 +1*( +#3002360000 +b1110 W3 +b11100000 Q3 +b1110000000000000 E3 +b1111111111111111110000000000000 1 +b1111111111111111110000000000000 C3 +0(( +#3002380000 +0[( +b111111111111111111100000000000001 6 +0,( +b10000000000000000001111111111111 " +b10000000000000000001111111111111 3 +b10000000000000000001111111111111 B3 +#3002390000 +b10 Y3 +#3002410000 +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +#3002420000 +b0 S3 +0X3 +#3002440000 +b10 }( +b10 w( +b10 z( +b10 {( +0') +b0 `( +b0 g( +b0 j( +0)) +#3002470000 +b0 o( +b1 !) +b0 i( +b0 l( +b0 m( +#3002500000 +b0 q( +b1 |( +1~( +#3002530000 +b0 n( +0p( +b10000000000000000011111111111111 2 +b10000000000000000011111111111111 @3 +1_( +#3002540000 +b1100 W3 +b11000000 Q3 +b1100000000000000 E3 +b1111111111111111100000000000000 1 +b1111111111111111100000000000000 C3 +0]( +#3002560000 +02) +b111111111111111111000000000000001 6 +0a( +b10000000000000000011111111111111 " +b10000000000000000011111111111111 3 +b10000000000000000011111111111111 B3 +#3002590000 +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +#3002620000 +b10 T) +b10 N) +b10 Q) +b10 R) +0\) +b0 7) +b0 >) +b0 A) +0^) +#3002650000 +b0 F) +b1 V) +b0 @) +b0 C) +b0 D) +#3002680000 +b0 H) +b1 S) +1U) +#3002710000 +b0 E) +0G) +b10000000000000000111111111111111 2 +b10000000000000000111111111111111 @3 +16) +#3002720000 +b1000 W3 +b10000000 Q3 +b1000000000000000 E3 +b1111111111111111000000000000000 1 +b1111111111111111000000000000000 C3 +04) +#3002740000 +0g) +b111111111111111110000000000000001 6 +08) +b10000000000000000111111111111111 " +b10000000000000000111111111111111 3 +b10000000000000000111111111111111 B3 +#3002750000 +b0 Y3 +#3002770000 +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +#3002800000 +b10 +* +b10 %* +b10 (* +b10 )* +03* +b0 l) +b0 s) +b0 v) +05* +#3002830000 +b0 {) +b1 -* +b0 u) +b0 x) +b0 y) +#3002860000 +b0 }) +b1 ** +1,* +#3002890000 +b0 z) +0|) +b10000000000000001111111111111111 2 +b10000000000000001111111111111111 @3 +1k) +#3002900000 +b0 W3 +b0 Q3 +b0 E3 +b1111111111111110000000000000000 1 +b1111111111111110000000000000000 C3 +0i) +#3002920000 +0>* +b111111111111111100000000000000001 6 +0m) +b10000000000000001111111111111111 " +b10000000000000001111111111111111 3 +b10000000000000001111111111111111 B3 +#3002950000 +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +#3002980000 +b10 `* +b10 Z* +b10 ]* +b10 ^* +0h* +b0 C* +b0 J* +b0 M* +0j* +#3003010000 +b0 R* +b1 b* +b0 L* +b0 O* +b0 P* +#3003040000 +b0 T* +b1 _* +1a* +#3003070000 +b0 Q* +0S* +b10000000000000011111111111111111 2 +b10000000000000011111111111111111 @3 +1B* +#3003080000 +b1110 `3 +b11111110 ]3 +b111111111111110 Z3 +b1111111111111100000000000000000 1 +b1111111111111100000000000000000 C3 +0@* +#3003100000 +0s* +b111111111111111000000000000000001 6 +0D* +b10000000000000011111111111111111 " +b10000000000000011111111111111111 3 +b10000000000000011111111111111111 B3 +#3003110000 +b10 b3 +#3003130000 +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +#3003140000 +b10 _3 +0a3 +#3003160000 +b10 7+ +b10 1+ +b10 4+ +b10 5+ +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +#3003170000 +b0 \3 +0^3 +#3003190000 +b0 )+ +b1 9+ +b0 #+ +b0 &+ +b0 '+ +#3003220000 +b0 ++ +b1 6+ +18+ +#3003250000 +b0 (+ +0*+ +b10000000000000111111111111111111 2 +b10000000000000111111111111111111 @3 +1w* +#3003260000 +b1100 `3 +b11111100 ]3 +b111111111111100 Z3 +b1111111111111000000000000000000 1 +b1111111111111000000000000000000 C3 +0u* +#3003280000 +0J+ +b111111111111110000000000000000001 6 +0y* +b10000000000000111111111111111111 " +b10000000000000111111111111111111 3 +b10000000000000111111111111111111 B3 +#3003310000 +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +#3003340000 +b10 l+ +b10 f+ +b10 i+ +b10 j+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +#3003370000 +b0 ^+ +b1 n+ +b0 X+ +b0 [+ +b0 \+ +#3003400000 +b0 `+ +b1 k+ +1m+ +#3003430000 +b0 ]+ +0_+ +b10000000000001111111111111111111 2 +b10000000000001111111111111111111 @3 +1N+ +#3003440000 +b1000 `3 +b11111000 ]3 +b111111111111000 Z3 +b1111111111110000000000000000000 1 +b1111111111110000000000000000000 C3 +0L+ +#3003460000 +0!, +b111111111111100000000000000000001 6 +0P+ +b10000000000001111111111111111111 " +b10000000000001111111111111111111 3 +b10000000000001111111111111111111 B3 +#3003470000 +b0 b3 +#3003490000 +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +#3003520000 +b10 C, +b10 =, +b10 @, +b10 A, +0K, +b0 &, +b0 -, +b0 0, +0M, +#3003550000 +b0 5, +b1 E, +b0 /, +b0 2, +b0 3, +#3003580000 +b0 7, +b1 B, +1D, +#3003610000 +b0 4, +06, +b10000000000011111111111111111111 2 +b10000000000011111111111111111111 @3 +1%, +#3003620000 +b0 `3 +b11110000 ]3 +b111111111110000 Z3 +b1111111111100000000000000000000 1 +b1111111111100000000000000000000 C3 +0#, +#3003640000 +0V, +b111111111111000000000000000000001 6 +0', +b10000000000011111111111111111111 " +b10000000000011111111111111111111 3 +b10000000000011111111111111111111 B3 +#3003670000 +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +#3003700000 +b10 x, +b10 r, +b10 u, +b10 v, +0"- +b0 [, +b0 b, +b0 e, +0$- +#3003730000 +b0 j, +b1 z, +b0 d, +b0 g, +b0 h, +#3003760000 +b0 l, +b1 w, +1y, +#3003790000 +b0 i, +0k, +b10000000000111111111111111111111 2 +b10000000000111111111111111111111 @3 +1Z, +#3003800000 +b1110 c3 +b11100000 ]3 +b111111111100000 Z3 +b1111111111000000000000000000000 1 +b1111111111000000000000000000000 C3 +0X, +#3003820000 +0-- +b111111111110000000000000000000001 6 +0\, +b10000000000111111111111111111111 " +b10000000000111111111111111111111 3 +b10000000000111111111111111111111 B3 +#3003830000 +b10 e3 +#3003850000 +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +#3003860000 +b0 _3 +0d3 +#3003880000 +b10 O- +b10 I- +b10 L- +b10 M- +0W- +b0 2- +b0 9- +b0 <- +0Y- +#3003910000 +b0 A- +b1 Q- +b0 ;- +b0 >- +b0 ?- +#3003940000 +b0 C- +b1 N- +1P- +#3003970000 +b0 @- +0B- +b10000000001111111111111111111111 2 +b10000000001111111111111111111111 @3 +11- +#3003980000 +b1100 c3 +b11000000 ]3 +b111111111000000 Z3 +b1111111110000000000000000000000 1 +b1111111110000000000000000000000 C3 +0/- +#3004000000 +0b- +b111111111100000000000000000000001 6 +03- +b10000000001111111111111111111111 " +b10000000001111111111111111111111 3 +b10000000001111111111111111111111 B3 +#3004030000 +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +#3004060000 +b10 &. +b10 ~- +b10 #. +b10 $. +0.. +b0 g- +b0 n- +b0 q- +00. +#3004090000 +b0 v- +b1 (. +b0 p- +b0 s- +b0 t- +#3004120000 +b0 x- +b1 %. +1'. +#3004150000 +b0 u- +0w- +b10000000011111111111111111111111 2 +b10000000011111111111111111111111 @3 +1f- +#3004160000 +b1000 c3 +b10000000 ]3 +b111111110000000 Z3 +b1111111100000000000000000000000 1 +b1111111100000000000000000000000 C3 +0d- +#3004180000 +09. +b111111111000000000000000000000001 6 +0h- +b10000000011111111111111111111111 " +b10000000011111111111111111111111 3 +b10000000011111111111111111111111 B3 +#3004190000 +b0 e3 +#3004210000 +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +#3004240000 +b10 [. +b10 U. +b10 X. +b10 Y. +0c. +b0 >. +b0 E. +b0 H. +0e. +#3004270000 +b0 M. +b1 ]. +b0 G. +b0 J. +b0 K. +#3004300000 +b0 O. +b1 Z. +1\. +#3004330000 +b0 L. +0N. +b10000000111111111111111111111111 2 +b10000000111111111111111111111111 @3 +1=. +#3004340000 +b0 c3 +b0 ]3 +b111111100000000 Z3 +b1111111000000000000000000000000 1 +b1111111000000000000000000000000 C3 +0;. +#3004360000 +0n. +b111111110000000000000000000000001 6 +0?. +b10000000111111111111111111111111 " +b10000000111111111111111111111111 3 +b10000000111111111111111111111111 B3 +#3004390000 +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +#3004420000 +b10 2/ +b10 ,/ +b10 // +b10 0/ +0:/ +b0 s. +b0 z. +b0 }. +00 +b10 80 +b10 ;0 +b10 <0 +0F0 +b0 !0 +b0 (0 +b0 +0 +0H0 +#3004810000 +b0 00 +b1 @0 +b0 *0 +b0 -0 +b0 .0 +#3004840000 +b0 20 +b1 =0 +1?0 +#3004870000 +b0 /0 +010 +b10000111111111111111111111111111 2 +b10000111111111111111111111111111 @3 +1~/ +#3004880000 +b1000 i3 +b1111000 f3 +b111100000000000 Z3 +b1111000000000000000000000000000 1 +b1111000000000000000000000000000 C3 +0|/ +#3004900000 +0Q0 +b111110000000000000000000000000001 6 +0"0 +b10000111111111111111111111111111 " +b10000111111111111111111111111111 3 +b10000111111111111111111111111111 B3 +#3004910000 +b0 k3 +#3004930000 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +#3004960000 +b10 s0 +b10 m0 +b10 p0 +b10 q0 +0{0 +b0 V0 +b0 ]0 +b0 `0 +0}0 +#3004990000 +b0 e0 +b1 u0 +b0 _0 +b0 b0 +b0 c0 +#3005020000 +b0 g0 +b1 r0 +1t0 +#3005050000 +b0 d0 +0f0 +b10001111111111111111111111111111 2 +b10001111111111111111111111111111 @3 +1U0 +#3005060000 +b0 i3 +b1110000 f3 +b111000000000000 Z3 +b1110000000000000000000000000000 1 +b1110000000000000000000000000000 C3 +0S0 +#3005080000 +0(1 +b111100000000000000000000000000001 6 +0W0 +b10001111111111111111111111111111 " +b10001111111111111111111111111111 3 +b10001111111111111111111111111111 B3 +#3005110000 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +#3005140000 +b10 J1 +b10 D1 +b10 G1 +b10 H1 +0R1 +b0 -1 +b0 41 +b0 71 +0T1 +#3005170000 +b0 <1 +b1 L1 +b0 61 +b0 91 +b0 :1 +#3005200000 +b0 >1 +b1 I1 +1K1 +#3005230000 +b0 ;1 +0=1 +b10011111111111111111111111111111 2 +b10011111111111111111111111111111 @3 +1,1 +#3005240000 +b110 l3 +b1100000 f3 +b110000000000000 Z3 +b1100000000000000000000000000000 1 +b1100000000000000000000000000000 C3 +0*1 +#3005260000 +0]1 +b111000000000000000000000000000001 6 +0.1 +b10011111111111111111111111111111 " +b10011111111111111111111111111111 3 +b10011111111111111111111111111111 B3 +#3005270000 +b0 n3 +#3005290000 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +#3005320000 +b10 !2 +b10 y1 +b10 |1 +b10 }1 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +#3005350000 +b0 q1 +b1 #2 +b0 k1 +b0 n1 +b0 o1 +#3005380000 +b0 s1 +b1 ~1 +1"2 +#3005410000 +b0 p1 +0r1 +b10111111111111111111111111111111 2 +b10111111111111111111111111111111 @3 +1a1 +#3005420000 +b100 l3 +b1000000 f3 +b100000000000000 Z3 +b1000000000000000000000000000000 1 +b1000000000000000000000000000000 C3 +0_1 +#3005440000 +042 +b110000000000000000000000000000001 6 +0c1 +b10111111111111111111111111111111 " +b10111111111111111111111111111111 3 +b10111111111111111111111111111111 B3 +#3005470000 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +#3005500000 +b10 V2 +b10 P2 +b10 S2 +b10 T2 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +#3005530000 +b0 H2 +b1 X2 +b0 B2 +b0 E2 +b0 F2 +#3005560000 +b0 J2 +b1 U2 +1W2 +#3005590000 +b0 G2 +0I2 +b11111111111111111111111111111111 2 +b11111111111111111111111111111111 @3 +182 +#3005600000 +b0 l3 +b0 f3 +b0 Z3 +b0 1 +b0 C3 +062 +#3005620000 +0i2 +b100000000000000000000000000000001 6 +0:2 +b11111111111111111111111111111111 " +b11111111111111111111111111111111 3 +b11111111111111111111111111111111 B3 +#3005650000 +1q2 +0s2 +b10100101 l2 +b10100101 %3 +b10100101 (3 +083 +#3005680000 +b0 -3 +b0 '3 +b0 *3 +b0 +3 +b1010 n2 +b1010 u2 +b1010 x2 +0p2 +#3005710000 +b0 /3 +#3005740000 +b0 ,3 +0.3 +#3005770000 +b1111111111111111111111111111111 2 +b1111111111111111111111111111111 @3 +0m2 +#3005780000 +b1000 l3 +b10000000 f3 +b1000000000000000 Z3 +b10000000000000000000000000000000 1 +b10000000000000000000000000000000 C3 +1k2 +#3005800000 +b1111111111111111111111111111111 " +b1111111111111111111111111111111 3 +b1111111111111111111111111111111 B3 +#3005830000 +1. +#3005860000 +1- +#3005890000 +1# +#4000000000 +0: +1o +1{" +18 +1y" +0e2 +b100 7 +b100 = +b100 I +b100 L +b100 W +b100 Z +b100 r +b100 ~ +b100 #" +b100 ." +b100 1" +b100 I" +b100 U" +b100 X" +b100 c" +b100 f" +b100 ~" +b100 ,# +b100 /# +b100 :# +b100 =# +b100 U# +b100 a# +b100 d# +b100 o# +b100 r# +b100 ,$ +b100 8$ +b100 ;$ +b100 F$ +b100 I$ +b100 a$ +b100 m$ +b100 p$ +b100 {$ +b100 ~$ +b100 8% +b100 D% +b100 G% +b100 R% +b100 U% +b100 m% +b100 y% +b100 |% +b100 )& +b100 ,& +b100 D& +b100 P& +b100 S& +b100 ^& +b100 a& +b100 y& +b100 '' +b100 *' +b100 5' +b100 8' +b100 P' +b100 \' +b100 _' +b100 j' +b100 m' +b100 '( +b100 3( +b100 6( +b100 A( +b100 D( +b100 \( +b100 h( +b100 k( +b100 v( +b100 y( +b100 3) +b100 ?) +b100 B) +b100 M) +b100 P) +b100 h) +b100 t) +b100 w) +b100 $* +b100 '* +b100 ?* +b100 K* +b100 N* +b100 Y* +b100 \* +b100 t* +b100 "+ +b100 %+ +b100 0+ +b100 3+ +b100 K+ +b100 W+ +b100 Z+ +b100 e+ +b100 h+ +b100 ", +b100 ., +b100 1, +b100 <, +b100 ?, +b100 W, +b100 c, +b100 f, +b100 q, +b100 t, +b100 .- +b100 :- +b100 =- +b100 H- +b100 K- +b100 c- +b100 o- +b100 r- +b100 }- +b100 ". +b100 :. +b100 F. +b100 I. +b100 T. +b100 W. +b100 o. +b100 {. +b100 ~. +b100 +/ +b100 ./ +b100 F/ +b100 R/ +b100 U/ +b100 `/ +b100 c/ +b100 {/ +b100 )0 +b100 ,0 +b100 70 +b100 :0 +b100 R0 +b100 ^0 +b100 a0 +b100 l0 +b100 o0 +b100 )1 +b100 51 +b100 81 +b100 C1 +b100 F1 +b100 ^1 +b100 j1 +b100 m1 +b100 x1 +b100 {1 +b100 52 +b100 A2 +b100 D2 +b100 O2 +b100 R2 +b100 j2 +b100 v2 +b100 y2 +b100 &3 +b100 )3 +b1010 & +b1010 , +b1001 % +b1001 + +b10 ' +b10 ) +#4000010000 +1; +0p +0|" +09 +0z" +1f2 +#4000020000 +b100010 t +b100010 -" +b100010 0" +0;" +b10 "# +b10 9# +b10 <# +b11100101 l2 +b11100101 %3 +b11100101 (3 +133 +1/ +#4000030000 +0< +b100 ^ +b0 5" +b0 j" +b0 A# +b0 v# +b0 M$ +b0 $% +b0 Y% +b0 0& +b0 e& +b0 <' +b0 q' +b0 H( +b0 }( +b0 T) +b0 +* +b0 `* +b0 7+ +b0 l+ +b0 C, +b0 x, +b0 O- +b0 &. +b0 [. +b0 2/ +b0 g/ +b0 >0 +b0 s0 +b0 J1 +b0 !2 +b0 V2 +b0 }2 +b100 -3 +0* +b100000000000000000000000000000000 6 +0( +b100 X +b100 [ +b100 \ +b0 /" +b0 2" +b0 3" +b0 d" +b0 g" +b0 h" +b0 ;# +b0 ># +b0 ?# +b0 p# +b0 s# +b0 t# +b0 G$ +b0 J$ +b0 K$ +b0 |$ +b0 !% +b0 "% +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 w2 +b0 z2 +b0 {2 +b100 '3 +b100 *3 +b100 +3 +b10100110 t +b10100110 -" +b10100110 0" +1z +b10010010 "# +b10010010 9# +b10010010 <# +1*# +b1100001 l2 +b1100001 %3 +b1100001 (3 +0r2 +043 +193 +0;3 +#4000040000 +1e +1l +0A" +#4000060000 +b100 5" +b0 -3 +b10 ` +b0 7" +b0 l" +b0 C# +b0 x# +b0 O$ +b0 &% +b0 [% +b0 2& +b0 g& +b0 >' +b0 s' +b0 J( +b0 !) +b0 V) +b0 -* +b0 b* +b0 9+ +b0 n+ +b0 E, +b0 z, +b0 Q- +b0 (. +b0 ]. +b0 4/ +b0 i/ +b0 @0 +b0 u0 +b0 L1 +b0 #2 +b0 X2 +b0 !3 +b10 /3 +1D +0F +b10100101 ? +b10100101 V +b10100101 Y +0i +b100 /" +b100 2" +b100 3" +b0 '3 +b0 *3 +b0 +3 +10 +0>3 +0# +b10100111 t +b10100111 -" +b10100111 0" +1y +b1 $# +b1 +# +b1 .# +1&# +0q2 +053 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +b0 n2 +b0 u2 +b0 x2 +073 +#4000070000 +1f +b1011 A +b1011 H +b1011 K +1h +b10100101 t +b10100101 -" +b10100101 0" +0@" +#4000090000 +b10 7" +b0 /3 +b0 4" +06" +b0 i" +0k" +b0 @# +0B# +b0 u# +0w# +b0 L$ +0N$ +b0 #% +0%% +b0 X% +0Z% +b0 /& +01& +b0 d& +0f& +b0 ;' +0=' +b0 p' +0r' +b0 G( +0I( +b0 |( +0~( +b0 S) +0U) +b0 ** +0,* +b0 _* +0a* +b0 6+ +08+ +b0 k+ +0m+ +b0 B, +0D, +b0 w, +0y, +b0 N- +0P- +b0 %. +0'. +b0 Z. +0\. +b0 1/ +03/ +b0 f/ +0h/ +b0 =0 +0?0 +b0 r0 +0t0 +b0 I1 +0K1 +b0 ~1 +0"2 +b0 U2 +0W2 +b0 |2 +0~2 +b1 ,3 +1.3 +b1010 A +b1010 H +b1010 K +0C +05 +#4000120000 +b1 4" +16" +b0 ,3 +0.3 +0u +0L" +0## +0X# +0/$ +0d$ +0;% +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b0 6 +0o2 +b10000000000000000000000000000001 2 +b10000000000000000000000000000001 @3 +1m2 +0- +#4000130000 +b1110 K3 +b1111 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b111 l3 +b11111110 H3 +b11111111 Q3 +b11111111 ]3 +b1111111 f3 +b1111111111111110 E3 +b111111111111111 Z3 +1s +1J" +1!# +1V# +1-$ +1b$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b1111111111111111111111111111110 1 +b1111111111111111111111111111110 C3 +0k2 +#4000150000 +1u +b11 2 +b11 @3 +0m2 +0$ +b10000000000000000000000000000001 " +b10000000000000000000000000000001 3 +b10000000000000000000000000000001 B3 +#4000160000 +b1100 K3 +b1111 l3 +b11111100 H3 +b11111111 f3 +b1111111111111100 E3 +b1111111111111111 Z3 +0s +b11111111111111111111111111111100 1 +b11111111111111111111111111111100 C3 +1k2 +b10 M3 +b11 P3 +b11 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b1 n3 +#4000180000 +b11 " +b11 3 +b11 B3 +00 +#4000190000 +b11 n3 +b10 J3 +1O3 +1U3 +b11 S3 +1X3 +1a3 +b11 _3 +1d3 +b1 h3 +1j3 +#4000210000 +0. +#4000220000 +b11 h3 +1m3 +b10 G3 +1R3 +b1 \3 +1^3 +#4000250000 +b11 \3 +1g3 +#4000280000 +b10 D3 +1[3 +#5000000000 +1: +1F" +08 +0y" +b1111 & +b1111 , +b0 % +b0 + +#5000010000 +0; +0G" +19 +1z" +#5000020000 +b100010 K" +b100010 b" +b100010 e" +0p" +b10110010 "# +b10110010 9# +b10110010 <# +0G# +#5000030000 +b10100110 K" +b10100110 b" +b10100110 e" +1Q" +0e +0l +b10100110 "# +b10100110 9# +b10100110 <# +1(# +0*# +0M# +#5000040000 +0v" +#5000060000 +b100 j" +b100 A# +b100 d" +b100 g" +b100 h" +b100 ;# +b100 ># +b100 ?# +b10100111 K" +b10100111 b" +b10100111 e" +1P" +0f +b0 A +b0 H +b0 K +0h +1'# +b0 $# +b0 +# +b0 .# +0&# +b10100101 "# +b10100101 9# +b10100101 <# +0L# +#5000070000 +b10100101 K" +b10100101 b" +b10100101 e" +0u" +#5000090000 +b10 l" +b10 C# +#5000120000 +b1 i" +1k" +b1 @# +1B# +#5000150000 +1L" +b1111 2 +b1111 @3 +1## +#5000160000 +b0 K3 +b11110000 H3 +b1111111111110000 E3 +0J" +b11111111111111111111111111110000 1 +b11111111111111111111111111110000 C3 +0!# +#5000180000 +b1111 " +b1111 3 +b1111 B3 +#5000190000 +b0 M3 +#6000000000 +0: +0o +0F" +0{" +1R# +1)$ +1^$ +15% +1j% +1A& +1v& +1M' +1$( +1Y( +10) +1e) +1<* +1q* +1H+ +1}+ +1T, +1+- +1`- +17. +1l. +1C/ +1x/ +1O0 +1&1 +1[1 +122 +1g2 +1y" +1P# +1'$ +1\$ +13% +1h% +1?& +1t& +1K' +1"( +1W( +1.) +1c) +1:* +1o* +1F+ +1{+ +1R, +1)- +1^- +15. +1j. +1A/ +1v/ +1M0 +1$1 +1Y1 +102 +1e2 +b1000 7 +b1000 = +b1000 I +b1000 L +b1000 W +b1000 Z +b1000 r +b1000 ~ +b1000 #" +b1000 ." +b1000 1" +b1000 I" +b1000 U" +b1000 X" +b1000 c" +b1000 f" +b1000 ~" +b1000 ,# +b1000 /# +b1000 :# +b1000 =# +b1000 U# +b1000 a# +b1000 d# +b1000 o# +b1000 r# +b1000 ,$ +b1000 8$ +b1000 ;$ +b1000 F$ +b1000 I$ +b1000 a$ +b1000 m$ +b1000 p$ +b1000 {$ +b1000 ~$ +b1000 8% +b1000 D% +b1000 G% +b1000 R% +b1000 U% +b1000 m% +b1000 y% +b1000 |% +b1000 )& +b1000 ,& +b1000 D& +b1000 P& +b1000 S& +b1000 ^& +b1000 a& +b1000 y& +b1000 '' +b1000 *' +b1000 5' +b1000 8' +b1000 P' +b1000 \' +b1000 _' +b1000 j' +b1000 m' +b1000 '( +b1000 3( +b1000 6( +b1000 A( +b1000 D( +b1000 \( +b1000 h( +b1000 k( +b1000 v( +b1000 y( +b1000 3) +b1000 ?) +b1000 B) +b1000 M) +b1000 P) +b1000 h) +b1000 t) +b1000 w) +b1000 $* +b1000 '* +b1000 ?* +b1000 K* +b1000 N* +b1000 Y* +b1000 \* +b1000 t* +b1000 "+ +b1000 %+ +b1000 0+ +b1000 3+ +b1000 K+ +b1000 W+ +b1000 Z+ +b1000 e+ +b1000 h+ +b1000 ", +b1000 ., +b1000 1, +b1000 <, +b1000 ?, +b1000 W, +b1000 c, +b1000 f, +b1000 q, +b1000 t, +b1000 .- +b1000 :- +b1000 =- +b1000 H- +b1000 K- +b1000 c- +b1000 o- +b1000 r- +b1000 }- +b1000 ". +b1000 :. +b1000 F. +b1000 I. +b1000 T. +b1000 W. +b1000 o. +b1000 {. +b1000 ~. +b1000 +/ +b1000 ./ +b1000 F/ +b1000 R/ +b1000 U/ +b1000 `/ +b1000 c/ +b1000 {/ +b1000 )0 +b1000 ,0 +b1000 70 +b1000 :0 +b1000 R0 +b1000 ^0 +b1000 a0 +b1000 l0 +b1000 o0 +b1000 )1 +b1000 51 +b1000 81 +b1000 C1 +b1000 F1 +b1000 ^1 +b1000 j1 +b1000 m1 +b1000 x1 +b1000 {1 +b1000 52 +b1000 A2 +b1000 D2 +b1000 O2 +b1000 R2 +b1000 j2 +b1000 v2 +b1000 y2 +b1000 &3 +b1000 )3 +b11111111111111111111111111110000 & +b11111111111111111111111111110000 , +b11111111111111111111111111111000 % +b11111111111111111111111111111000 + +b11 ' +b11 ) +#6000010000 +1; +1p +1G" +1|" +0S# +0*$ +0_$ +06% +0k% +0B& +0w& +0N' +0%( +0Z( +01) +0f) +0=* +0r* +0I+ +0~+ +0U, +0,- +0a- +08. +0m. +0D/ +0y/ +0P0 +0'1 +0\1 +032 +0h2 +0z" +0Q# +0($ +0]$ +04% +0i% +0@& +0u& +0L' +0#( +0X( +0/) +0d) +0;* +0p* +0G+ +0|+ +0S, +0*- +0_- +06. +0k. +0B/ +0w/ +0N0 +0%1 +0Z1 +012 +0f2 +#6000020000 +b11100101 ? +b11100101 V +b11100101 Y +1d +b11100101 t +b11100101 -" +b11100101 0" +1;" +b11100101 K" +b11100101 b" +b11100101 e" +1p" +b10 W# +b10 n# +b10 q# +b10 .$ +b10 E$ +b10 H$ +b10 c$ +b10 z$ +b10 }$ +b10 :% +b10 Q% +b10 T% +b10 o% +b10 (& +b10 +& +b10 F& +b10 ]& +b10 `& +b10 {& +b10 4' +b10 7' +b10 R' +b10 i' +b10 l' +b10 )( +b10 @( +b10 C( +b10 ^( +b10 u( +b10 x( +b10 5) +b10 L) +b10 O) +b10 j) +b10 #* +b10 &* +b10 A* +b10 X* +b10 [* +b10 v* +b10 /+ +b10 2+ +b10 M+ +b10 d+ +b10 g+ +b10 $, +b10 ;, +b10 >, +b10 Y, +b10 p, +b10 s, +b10 0- +b10 G- +b10 J- +b10 e- +b10 |- +b10 !. +b10 <. +b10 S. +b10 V. +b10 q. +b10 */ +b10 -/ +b10 H/ +b10 _/ +b10 b/ +b10 }/ +b10 60 +b10 90 +b10 T0 +b10 k0 +b10 n0 +b10 +1 +b10 B1 +b10 E1 +b10 `1 +b10 w1 +b10 z1 +b10 72 +b10 N2 +b10 Q2 +b10 l2 +b10 %3 +b10 (3 +#6000030000 +b0 ^ +b0 5" +b0 j" +b0 A# +b0 X +b0 [ +b0 \ +b0 /" +b0 2" +b0 3" +b0 d" +b0 g" +b0 h" +b0 ;# +b0 ># +b0 ?# +b1100001 ? +b1100001 V +b1100001 Y +0E +b1100001 t +b1100001 -" +b1100001 0" +0z +b1100001 K" +b1100001 b" +b1100001 e" +0Q" +b10010010 W# +b10010010 n# +b10010010 q# +1_# +b10010010 .$ +b10010010 E$ +b10010010 H$ +16$ +b10010010 c$ +b10010010 z$ +b10010010 }$ +1k$ +b10010010 :% +b10010010 Q% +b10010010 T% +1B% +b10010010 o% +b10010010 (& +b10010010 +& +1w% +b10010010 F& +b10010010 ]& +b10010010 `& +1N& +b10010010 {& +b10010010 4' +b10010010 7' +1%' +b10010010 R' +b10010010 i' +b10010010 l' +1Z' +b10010010 )( +b10010010 @( +b10010010 C( +11( +b10010010 ^( +b10010010 u( +b10010010 x( +1f( +b10010010 5) +b10010010 L) +b10010010 O) +1=) +b10010010 j) +b10010010 #* +b10010010 &* +1r) +b10010010 A* +b10010010 X* +b10010010 [* +1I* +b10010010 v* +b10010010 /+ +b10010010 2+ +1~* +b10010010 M+ +b10010010 d+ +b10010010 g+ +1U+ +b10010010 $, +b10010010 ;, +b10010010 >, +1,, +b10010010 Y, +b10010010 p, +b10010010 s, +1a, +b10010010 0- +b10010010 G- +b10010010 J- +18- +b10010010 e- +b10010010 |- +b10010010 !. +1m- +b10010010 <. +b10010010 S. +b10010010 V. +1D. +b10010010 q. +b10010010 */ +b10010010 -/ +1y. +b10010010 H/ +b10010010 _/ +b10010010 b/ +1P/ +b10010010 }/ +b10010010 60 +b10010010 90 +1'0 +b10010010 T0 +b10010010 k0 +b10010010 n0 +1\0 +b10010010 +1 +b10010010 B1 +b10010010 E1 +131 +b10010010 `1 +b10010010 w1 +b10010010 z1 +1h1 +b10010010 72 +b10010010 N2 +b10010010 Q2 +1?2 +b10010010 l2 +b10010010 %3 +b10010010 (3 +1t2 +#6000040000 +1j +1A" +1v" +1H# +1O# +#6000060000 +b0 ` +b0 7" +b0 l" +b0 C# +b1100000 ? +b1100000 V +b1100000 Y +0D +b1100000 t +b1100000 -" +b1100000 0" +0y +b1100000 K" +b1100000 b" +b1100000 e" +0P" +b1 Y# +b1 `# +b1 c# +1[# +b1 0$ +b1 7$ +b1 :$ +12$ +b1 e$ +b1 l$ +b1 o$ +1g$ +b1 <% +b1 C% +b1 F% +1>% +b1 q% +b1 x% +b1 {% +1s% +b1 H& +b1 O& +b1 R& +1J& +b1 }& +b1 &' +b1 )' +1!' +b1 T' +b1 [' +b1 ^' +1V' +b1 +( +b1 2( +b1 5( +1-( +b1 `( +b1 g( +b1 j( +1b( +b1 7) +b1 >) +b1 A) +19) +b1 l) +b1 s) +b1 v) +1n) +b1 C* +b1 J* +b1 M* +1E* +b1 x* +b1 !+ +b1 $+ +1z* +b1 O+ +b1 V+ +b1 Y+ +1Q+ +b1 &, +b1 -, +b1 0, +1(, +b1 [, +b1 b, +b1 e, +1], +b1 2- +b1 9- +b1 <- +14- +b1 g- +b1 n- +b1 q- +1i- +b1 >. +b1 E. +b1 H. +1@. +b1 s. +b1 z. +b1 }. +1u. +b1 J/ +b1 Q/ +b1 T/ +1L/ +b1 !0 +b1 (0 +b1 +0 +1#0 +b1 V0 +b1 ]0 +b1 `0 +1X0 +b1 -1 +b1 41 +b1 71 +1/1 +b1 b1 +b1 i1 +b1 l1 +1d1 +b1 92 +b1 @2 +b1 C2 +1;2 +b1 n2 +b1 u2 +b1 x2 +1p2 +#6000070000 +b1100010 ? +b1100010 V +b1100010 Y +1i +b1100010 t +b1100010 -" +b1100010 0" +1@" +b1100010 K" +b1100010 b" +b1100010 e" +1u" +1I# +b1010 $# +b1010 +# +b1010 .# +1K# +#6000090000 +b0 ] +0_ +b0 4" +06" +b0 i" +0k" +b0 @# +0B# +#6000100000 +b1000 3# +b1000 -# +b1000 0# +b1000 1# +#6000120000 +0@ +0u +0L" +b0 2 +b0 @3 +0## +#6000130000 +b1111 K3 +b11111111 H3 +b1111111111111111 E3 +1> +1s +1J" +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1!# +b10 5# +#6000150000 +b0 " +b0 3 +b0 B3 +#6000160000 +b11 M3 +b1 2# +14# +#6000190000 +1T# +b11 J3 +1L3 +b10000 6 +1%# +#6000220000 +b11 G3 +1I3 +1\# +1!$ +b10010001 W# +b10010001 n# +b10010001 q# +0#$ +1%$ +#6000250000 +b11 D3 +1F3 +1~# +b1011 Y# +b1011 `# +b1011 c# +1"$ +#6000280000 +b1000 h# +1! +b1000 b# +b1000 e# +b1000 f# +#6000310000 +b10 j# +#6000340000 +b1 g# +1i# +#6000370000 +1+$ +b110000 6 +1Z# +#6000400000 +13$ +1V$ +b10010001 .$ +b10010001 E$ +b10010001 H$ +0X$ +1Z$ +#6000430000 +1U$ +b1011 0$ +b1011 7$ +b1011 :$ +1W$ +#6000460000 +b1000 ?$ +b1000 9$ +b1000 <$ +b1000 =$ +#6000490000 +b10 A$ +#6000520000 +b1 >$ +1@$ +#6000550000 +1`$ +b1110000 6 +11$ +#6000580000 +1h$ +1-% +b10010001 c$ +b10010001 z$ +b10010001 }$ +0/% +11% +#6000610000 +1,% +b1011 e$ +b1011 l$ +b1011 o$ +1.% +#6000640000 +b1000 t$ +b1000 n$ +b1000 q$ +b1000 r$ +#6000670000 +b10 v$ +#6000700000 +b1 s$ +1u$ +#6000730000 +17% +b11110000 6 +1f$ +#6000760000 +1?% +1b% +b10010001 :% +b10010001 Q% +b10010001 T% +0d% +1f% +#6000790000 +1a% +b1011 <% +b1011 C% +b1011 F% +1c% +#6000820000 +b1000 K% +b1000 E% +b1000 H% +b1000 I% +#6000850000 +b10 M% +#6000880000 +b1 J% +1L% +#6000910000 +1l% +b111110000 6 +1=% +#6000940000 +1t% +19& +b10010001 o% +b10010001 (& +b10010001 +& +0;& +1=& +#6000970000 +18& +b1011 q% +b1011 x% +b1011 {% +1:& +#6001000000 +b1000 "& +b1000 z% +b1000 }% +b1000 ~% +#6001030000 +b10 $& +#6001060000 +b1 !& +1#& +#6001090000 +1C& +b1111110000 6 +1r% +#6001120000 +1K& +1n& +b10010001 F& +b10010001 ]& +b10010001 `& +0p& +1r& +#6001150000 +1m& +b1011 H& +b1011 O& +b1011 R& +1o& +#6001180000 +b1000 W& +b1000 Q& +b1000 T& +b1000 U& +#6001210000 +b10 Y& +#6001240000 +b1 V& +1X& +#6001270000 +1x& +b11111110000 6 +1I& +#6001300000 +1"' +1E' +b10010001 {& +b10010001 4' +b10010001 7' +0G' +1I' +#6001330000 +1D' +b1011 }& +b1011 &' +b1011 )' +1F' +#6001360000 +b1000 .' +b1000 (' +b1000 +' +b1000 ,' +#6001390000 +b10 0' +#6001420000 +b1 -' +1/' +#6001450000 +1O' +b111111110000 6 +1~& +#6001480000 +1W' +1z' +b10010001 R' +b10010001 i' +b10010001 l' +0|' +1~' +#6001510000 +1y' +b1011 T' +b1011 [' +b1011 ^' +1{' +#6001540000 +b1000 c' +b1000 ]' +b1000 `' +b1000 a' +#6001570000 +b10 e' +#6001600000 +b1 b' +1d' +#6001630000 +1&( +b1111111110000 6 +1U' +#6001660000 +1.( +1Q( +b10010001 )( +b10010001 @( +b10010001 C( +0S( +1U( +#6001690000 +1P( +b1011 +( +b1011 2( +b1011 5( +1R( +#6001720000 +b1000 :( +b1000 4( +b1000 7( +b1000 8( +#6001750000 +b10 <( +#6001780000 +b1 9( +1;( +#6001810000 +1[( +b11111111110000 6 +1,( +#6001840000 +1c( +1() +b10010001 ^( +b10010001 u( +b10010001 x( +0*) +1,) +#6001870000 +1') +b1011 `( +b1011 g( +b1011 j( +1)) +#6001900000 +b1000 o( +b1000 i( +b1000 l( +b1000 m( +#6001930000 +b10 q( +#6001960000 +b1 n( +1p( +#6001990000 +12) +b111111111110000 6 +1a( +#6002020000 +1:) +1]) +b10010001 5) +b10010001 L) +b10010001 O) +0_) +1a) +#6002050000 +1\) +b1011 7) +b1011 >) +b1011 A) +1^) +#6002080000 +b1000 F) +b1000 @) +b1000 C) +b1000 D) +#6002110000 +b10 H) +#6002140000 +b1 E) +1G) +#6002170000 +1g) +b1111111111110000 6 +18) +#6002200000 +1o) +14* +b10010001 j) +b10010001 #* +b10010001 &* +06* +18* +#6002230000 +13* +b1011 l) +b1011 s) +b1011 v) +15* +#6002260000 +b1000 {) +b1000 u) +b1000 x) +b1000 y) +#6002290000 +b10 }) +#6002320000 +b1 z) +1|) +#6002350000 +1>* +b11111111111110000 6 +1m) +#6002380000 +1F* +1i* +b10010001 A* +b10010001 X* +b10010001 [* +0k* +1m* +#6002410000 +1h* +b1011 C* +b1011 J* +b1011 M* +1j* +#6002440000 +b1000 R* +b1000 L* +b1000 O* +b1000 P* +#6002470000 +b10 T* +#6002500000 +b1 Q* +1S* +#6002530000 +1s* +b111111111111110000 6 +1D* +#6002560000 +1{* +1@+ +b10010001 v* +b10010001 /+ +b10010001 2+ +0B+ +1D+ +#6002590000 +1?+ +b1011 x* +b1011 !+ +b1011 $+ +1A+ +#6002620000 +b1000 )+ +b1000 #+ +b1000 &+ +b1000 '+ +#6002650000 +b10 ++ +#6002680000 +b1 (+ +1*+ +#6002710000 +1J+ +b1111111111111110000 6 +1y* +#6002740000 +1R+ +1u+ +b10010001 M+ +b10010001 d+ +b10010001 g+ +0w+ +1y+ +#6002770000 +1t+ +b1011 O+ +b1011 V+ +b1011 Y+ +1v+ +#6002800000 +b1000 ^+ +b1000 X+ +b1000 [+ +b1000 \+ +#6002830000 +b10 `+ +#6002860000 +b1 ]+ +1_+ +#6002890000 +1!, +b11111111111111110000 6 +1P+ +#6002920000 +1), +1L, +b10010001 $, +b10010001 ;, +b10010001 >, +0N, +1P, +#6002950000 +1K, +b1011 &, +b1011 -, +b1011 0, +1M, +#6002980000 +b1000 5, +b1000 /, +b1000 2, +b1000 3, +#6003010000 +b10 7, +#6003040000 +b1 4, +16, +#6003070000 +1V, +b111111111111111110000 6 +1', +#6003100000 +1^, +1#- +b10010001 Y, +b10010001 p, +b10010001 s, +0%- +1'- +#6003130000 +1"- +b1011 [, +b1011 b, +b1011 e, +1$- +#6003160000 +b1000 j, +b1000 d, +b1000 g, +b1000 h, +#6003190000 +b10 l, +#6003220000 +b1 i, +1k, +#6003250000 +1-- +b1111111111111111110000 6 +1\, +#6003280000 +15- +1X- +b10010001 0- +b10010001 G- +b10010001 J- +0Z- +1\- +#6003310000 +1W- +b1011 2- +b1011 9- +b1011 <- +1Y- +#6003340000 +b1000 A- +b1000 ;- +b1000 >- +b1000 ?- +#6003370000 +b10 C- +#6003400000 +b1 @- +1B- +#6003430000 +1b- +b11111111111111111110000 6 +13- +#6003460000 +1j- +1/. +b10010001 e- +b10010001 |- +b10010001 !. +01. +13. +#6003490000 +1.. +b1011 g- +b1011 n- +b1011 q- +10. +#6003520000 +b1000 v- +b1000 p- +b1000 s- +b1000 t- +#6003550000 +b10 x- +#6003580000 +b1 u- +1w- +#6003610000 +19. +b111111111111111111110000 6 +1h- +#6003640000 +1A. +1d. +b10010001 <. +b10010001 S. +b10010001 V. +0f. +1h. +#6003670000 +1c. +b1011 >. +b1011 E. +b1011 H. +1e. +#6003700000 +b1000 M. +b1000 G. +b1000 J. +b1000 K. +#6003730000 +b10 O. +#6003760000 +b1 L. +1N. +#6003790000 +1n. +b1111111111111111111110000 6 +1?. +#6003820000 +1v. +1;/ +b10010001 q. +b10010001 */ +b10010001 -/ +0=/ +1?/ +#6003850000 +1:/ +b1011 s. +b1011 z. +b1011 }. +11 +#6004660000 +b1 ;1 +1=1 +#6004690000 +1]1 +b111111111111111111111111110000 6 +1.1 +#6004720000 +1e1 +1*2 +b10010001 `1 +b10010001 w1 +b10010001 z1 +0,2 +1.2 +#6004750000 +1)2 +b1011 b1 +b1011 i1 +b1011 l1 +1+2 +#6004780000 +b1000 q1 +b1000 k1 +b1000 n1 +b1000 o1 +#6004810000 +b10 s1 +#6004840000 +b1 p1 +1r1 +#6004870000 +142 +b1111111111111111111111111110000 6 +1c1 +#6004900000 +1<2 +1_2 +b10010001 72 +b10010001 N2 +b10010001 Q2 +0a2 +1c2 +#6004930000 +1^2 +b1011 92 +b1011 @2 +b1011 C2 +1`2 +#6004960000 +b1000 H2 +b1000 B2 +b1000 E2 +b1000 F2 +#6004990000 +b10 J2 +#6005020000 +b1 G2 +1I2 +#6005050000 +1i2 +b11111111111111111111111111110000 6 +1:2 +#6005080000 +1q2 +163 +b10010001 l2 +b10010001 %3 +b10010001 (3 +083 +1:3 +#6005110000 +153 +b1011 n2 +b1011 u2 +b1011 x2 +173 +#6005140000 +b1000 }2 +b1000 w2 +b1000 z2 +b1000 {2 +#6005170000 +b10 !3 +#6005200000 +b1 |2 +1~2 +#6005230000 +b111111111111111111111111111110000 6 +1o2 +#6005260000 +1$ +#6005290000 +1. +10 +#6005320000 +b1 4 +b1 A3 +#6005350000 +b1 " +b1 3 +b1 B3 +#7000000000 +0)$ +0^$ +05% +0j% +0A& +0v& +0M' +0$( +0Y( +00) +0e) +0<* +0q* +0H+ +0}+ +0T, +0+- +0`- +07. +0l. +0C/ +0x/ +0O0 +0&1 +0[1 +022 +0g2 +0P# +0'$ +0\$ +03% +0h% +0?& +0t& +0K' +0"( +0W( +0.) +0c) +0:* +0o* +0F+ +0{+ +0R, +0)- +0^- +05. +0j. +0A/ +0v/ +0M0 +0$1 +0Y1 +002 +0e2 +b10000 & +b10000 , +b1000 % +b1000 + +#7000010000 +1*$ +1_$ +16% +1k% +1B& +1w& +1N' +1%( +1Z( +11) +1f) +1=* +1r* +1I+ +1~+ +1U, +1,- +1a- +18. +1m. +1D/ +1y/ +1P0 +1'1 +1\1 +132 +1h2 +1Q# +1($ +1]$ +14% +1i% +1@& +1u& +1L' +1#( +1X( +1/) +1d) +1;* +1p* +1G+ +1|+ +1S, +1*- +1_- +16. +1k. +1B/ +1w/ +1N0 +1%1 +1Z1 +112 +1f2 +#7000020000 +b10110001 W# +b10110001 n# +b10110001 q# +0|# +b11110001 .$ +b11110001 E$ +b11110001 H$ +b11110001 c$ +b11110001 z$ +b11110001 }$ +b11110001 :% +b11110001 Q% +b11110001 T% +b11110001 o% +b11110001 (& +b11110001 +& +b11110001 F& +b11110001 ]& +b11110001 `& +b11110001 {& +b11110001 4' +b11110001 7' +b11110001 R' +b11110001 i' +b11110001 l' +b11110001 )( +b11110001 @( +b11110001 C( +b11110001 ^( +b11110001 u( +b11110001 x( +b11110001 5) +b11110001 L) +b11110001 O) +b11110001 j) +b11110001 #* +b11110001 &* +b11110001 A* +b11110001 X* +b11110001 [* +b11110001 v* +b11110001 /+ +b11110001 2+ +b11110001 M+ +b11110001 d+ +b11110001 g+ +b11110001 $, +b11110001 ;, +b11110001 >, +b11110001 Y, +b11110001 p, +b11110001 s, +b11110001 0- +b11110001 G- +b11110001 J- +b11110001 e- +b11110001 |- +b11110001 !. +b11110001 <. +b11110001 S. +b11110001 V. +b11110001 q. +b11110001 */ +b11110001 -/ +b11110001 H/ +b11110001 _/ +b11110001 b/ +b11110001 }/ +b11110001 60 +b11110001 90 +b11110001 T0 +b11110001 k0 +b11110001 n0 +b11110001 +1 +b11110001 B1 +b11110001 E1 +b11110001 `1 +b11110001 w1 +b11110001 z1 +b11110001 72 +b11110001 N2 +b11110001 Q2 +b11110001 l2 +b11110001 %3 +b11110001 (3 +#7000030000 +b10100101 W# +b10100101 n# +b10100101 q# +1]# +0_# +0$$ +b1100001 .$ +b1100001 E$ +b1100001 H$ +06$ +b1100001 c$ +b1100001 z$ +b1100001 }$ +0k$ +b1100001 :% +b1100001 Q% +b1100001 T% +0B% +b1100001 o% +b1100001 (& +b1100001 +& +0w% +b1100001 F& +b1100001 ]& +b1100001 `& +0N& +b1100001 {& +b1100001 4' +b1100001 7' +0%' +b1100001 R' +b1100001 i' +b1100001 l' +0Z' +b1100001 )( +b1100001 @( +b1100001 C( +01( +b1100001 ^( +b1100001 u( +b1100001 x( +0f( +b1100001 5) +b1100001 L) +b1100001 O) +0=) +b1100001 j) +b1100001 #* +b1100001 &* +0r) +b1100001 A* +b1100001 X* +b1100001 [* +0I* +b1100001 v* +b1100001 /+ +b1100001 2+ +0~* +b1100001 M+ +b1100001 d+ +b1100001 g+ +0U+ +b1100001 $, +b1100001 ;, +b1100001 >, +0,, +b1100001 Y, +b1100001 p, +b1100001 s, +0a, +b1100001 0- +b1100001 G- +b1100001 J- +08- +b1100001 e- +b1100001 |- +b1100001 !. +0m- +b1100001 <. +b1100001 S. +b1100001 V. +0D. +b1100001 q. +b1100001 */ +b1100001 -/ +0y. +b1100001 H/ +b1100001 _/ +b1100001 b/ +0P/ +b1100001 }/ +b1100001 60 +b1100001 90 +0'0 +b1100001 T0 +b1100001 k0 +b1100001 n0 +0\0 +b1100001 +1 +b1100001 B1 +b1100001 E1 +031 +b1100001 `1 +b1100001 w1 +b1100001 z1 +0h1 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0?2 +b1100001 l2 +b1100001 %3 +b1100001 (3 +0t2 +#7000050000 +0!$ +#7000060000 +0\# +1^# +b1010 Y# +b1010 `# +b1010 c# +0[# +b10100110 W# +b10100110 n# +b10100110 q# +1#$ +0%$ +b1010 0$ +b1010 7$ +b1010 :$ +02$ +b1010 e$ +b1010 l$ +b1010 o$ +0g$ +b1010 <% +b1010 C% +b1010 F% +0>% +b1010 q% +b1010 x% +b1010 {% +0s% +b1010 H& +b1010 O& +b1010 R& +0J& +b1010 }& +b1010 &' +b1010 )' +0!' +b1010 T' +b1010 [' +b1010 ^' +0V' +b1010 +( +b1010 2( +b1010 5( +0-( +b1010 `( +b1010 g( +b1010 j( +0b( +b1010 7) +b1010 >) +b1010 A) +09) +b1010 l) +b1010 s) +b1010 v) +0n) +b1010 C* +b1010 J* +b1010 M* +0E* +b1010 x* +b1010 !+ +b1010 $+ +0z* +b1010 O+ +b1010 V+ +b1010 Y+ +0Q+ +b1010 &, +b1010 -, +b1010 0, +0(, +b1010 [, +b1010 b, +b1010 e, +0], +b1010 2- +b1010 9- +b1010 <- +04- +b1010 g- +b1010 n- +b1010 q- +0i- +b1010 >. +b1010 E. +b1010 H. +0@. +b1010 s. +b1010 z. +b1010 }. +0u. +b1010 J/ +b1010 Q/ +b1010 T/ +0L/ +b1010 !0 +b1010 (0 +b1010 +0 +0#0 +b1010 V0 +b1010 ]0 +b1010 `0 +0X0 +b1010 -1 +b1010 41 +b1010 71 +0/1 +b1010 b1 +b1010 i1 +b1010 l1 +0d1 +b1010 92 +b1010 @2 +b1010 C2 +0;2 +b1010 n2 +b1010 u2 +b1010 x2 +0p2 +#7000080000 +b10 Y# +b10 `# +b10 c# +0~# +#7000090000 +1[# +b1 Y# +b1 `# +b1 c# +0"$ +#7000110000 +b0 h# +b0 b# +b0 e# +b0 f# +#7000140000 +b0 j# +#7000170000 +b0 g# +0i# +#7000200000 +0+$ +b111111111111111111111111111010000 6 +0Z# +#7000230000 +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +#7000260000 +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +#7000290000 +b0 ?$ +b0 9$ +b0 <$ +b0 =$ +#7000320000 +b0 A$ +#7000350000 +b0 >$ +0@$ +#7000380000 +0`$ +b111111111111111111111111110010000 6 +01$ +#7000410000 +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +#7000440000 +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +#7000470000 +b0 t$ +b0 n$ +b0 q$ +b0 r$ +#7000500000 +b0 v$ +#7000530000 +b0 s$ +0u$ +#7000560000 +07% +b111111111111111111111111100010000 6 +0f$ +#7000590000 +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +#7000620000 +0a% +b0 <% +b0 C% +b0 F% +0c% +#7000650000 +b0 K% +b0 E% +b0 H% +b0 I% +#7000680000 +b0 M% +#7000710000 +b0 J% +0L% +#7000740000 +0l% +b111111111111111111111111000010000 6 +0=% +#7000770000 +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +#7000800000 +08& +b0 q% +b0 x% +b0 {% +0:& +#7000830000 +b0 "& +b0 z% +b0 }% +b0 ~% +#7000860000 +b0 $& +#7000890000 +b0 !& +0#& +#7000920000 +0C& +b111111111111111111111110000010000 6 +0r% +#7000950000 +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +#7000980000 +0m& +b0 H& +b0 O& +b0 R& +0o& +#7001010000 +b0 W& +b0 Q& +b0 T& +b0 U& +#7001040000 +b0 Y& +#7001070000 +b0 V& +0X& +#7001100000 +0x& +b111111111111111111111100000010000 6 +0I& +#7001130000 +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +#7001160000 +0D' +b0 }& +b0 &' +b0 )' +0F' +#7001190000 +b0 .' +b0 (' +b0 +' +b0 ,' +#7001220000 +b0 0' +#7001250000 +b0 -' +0/' +#7001280000 +0O' +b111111111111111111111000000010000 6 +0~& +#7001310000 +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +#7001340000 +0y' +b0 T' +b0 [' +b0 ^' +0{' +#7001370000 +b0 c' +b0 ]' +b0 `' +b0 a' +#7001400000 +b0 e' +#7001430000 +b0 b' +0d' +#7001460000 +0&( +b111111111111111111110000000010000 6 +0U' +#7001490000 +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +#7001520000 +0P( +b0 +( +b0 2( +b0 5( +0R( +#7001550000 +b0 :( +b0 4( +b0 7( +b0 8( +#7001580000 +b0 <( +#7001610000 +b0 9( +0;( +#7001640000 +0[( +b111111111111111111100000000010000 6 +0,( +#7001670000 +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +#7001700000 +0') +b0 `( +b0 g( +b0 j( +0)) +#7001730000 +b0 o( +b0 i( +b0 l( +b0 m( +#7001760000 +b0 q( +#7001790000 +b0 n( +0p( +#7001820000 +02) +b111111111111111111000000000010000 6 +0a( +#7001850000 +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +#7001880000 +0\) +b0 7) +b0 >) +b0 A) +0^) +#7001910000 +b0 F) +b0 @) +b0 C) +b0 D) +#7001940000 +b0 H) +#7001970000 +b0 E) +0G) +#7002000000 +0g) +b111111111111111110000000000010000 6 +08) +#7002030000 +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +#7002060000 +03* +b0 l) +b0 s) +b0 v) +05* +#7002090000 +b0 {) +b0 u) +b0 x) +b0 y) +#7002120000 +b0 }) +#7002150000 +b0 z) +0|) +#7002180000 +0>* +b111111111111111100000000000010000 6 +0m) +#7002210000 +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +#7002240000 +0h* +b0 C* +b0 J* +b0 M* +0j* +#7002270000 +b0 R* +b0 L* +b0 O* +b0 P* +#7002300000 +b0 T* +#7002330000 +b0 Q* +0S* +#7002360000 +0s* +b111111111111111000000000000010000 6 +0D* +#7002390000 +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +#7002420000 +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +#7002450000 +b0 )+ +b0 #+ +b0 &+ +b0 '+ +#7002480000 +b0 ++ +#7002510000 +b0 (+ +0*+ +#7002540000 +0J+ +b111111111111110000000000000010000 6 +0y* +#7002570000 +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +#7002600000 +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +#7002630000 +b0 ^+ +b0 X+ +b0 [+ +b0 \+ +#7002660000 +b0 `+ +#7002690000 +b0 ]+ +0_+ +#7002720000 +0!, +b111111111111100000000000000010000 6 +0P+ +#7002750000 +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +#7002780000 +0K, +b0 &, +b0 -, +b0 0, +0M, +#7002810000 +b0 5, +b0 /, +b0 2, +b0 3, +#7002840000 +b0 7, +#7002870000 +b0 4, +06, +#7002900000 +0V, +b111111111111000000000000000010000 6 +0', +#7002930000 +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +#7002960000 +0"- +b0 [, +b0 b, +b0 e, +0$- +#7002990000 +b0 j, +b0 d, +b0 g, +b0 h, +#7003020000 +b0 l, +#7003050000 +b0 i, +0k, +#7003080000 +0-- +b111111111110000000000000000010000 6 +0\, +#7003110000 +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +#7003140000 +0W- +b0 2- +b0 9- +b0 <- +0Y- +#7003170000 +b0 A- +b0 ;- +b0 >- +b0 ?- +#7003200000 +b0 C- +#7003230000 +b0 @- +0B- +#7003260000 +0b- +b111111111100000000000000000010000 6 +03- +#7003290000 +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +#7003320000 +0.. +b0 g- +b0 n- +b0 q- +00. +#7003350000 +b0 v- +b0 p- +b0 s- +b0 t- +#7003380000 +b0 x- +#7003410000 +b0 u- +0w- +#7003440000 +09. +b111111111000000000000000000010000 6 +0h- +#7003470000 +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +#7003500000 +0c. +b0 >. +b0 E. +b0 H. +0e. +#7003530000 +b0 M. +b0 G. +b0 J. +b0 K. +#7003560000 +b0 O. +#7003590000 +b0 L. +0N. +#7003620000 +0n. +b111111110000000000000000000010000 6 +0?. +#7003650000 +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +#7003680000 +0:/ +b0 s. +b0 z. +b0 }. +01 +#7004490000 +b0 ;1 +0=1 +#7004520000 +0]1 +b111000000000000000000000000010000 6 +0.1 +#7004550000 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +#7004580000 +0)2 +b0 b1 +b0 i1 +b0 l1 +0+2 +#7004610000 +b0 q1 +b0 k1 +b0 n1 +b0 o1 +#7004640000 +b0 s1 +#7004670000 +b0 p1 +0r1 +#7004700000 +042 +b110000000000000000000000000010000 6 +0c1 +#7004730000 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +#7004760000 +0^2 +b0 92 +b0 @2 +b0 C2 +0`2 +#7004790000 +b0 H2 +b0 B2 +b0 E2 +b0 F2 +#7004820000 +b0 J2 +#7004850000 +b0 G2 +0I2 +#7004880000 +0i2 +b100000000000000000000000000010000 6 +0:2 +#7004910000 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +#7004940000 +053 +b0 n2 +b0 u2 +b0 x2 +073 +#7004970000 +b0 }2 +b0 w2 +b0 z2 +b0 {2 +#7005000000 +b0 !3 +#7005030000 +b0 |2 +0~2 +#7005060000 +b10000 6 +0o2 +#7005090000 +0$ +#7005120000 +0. +00 +#7005150000 +b0 4 +b0 A3 +#7005180000 +b0 " +b0 3 +b0 B3 +#8000000000 +1)$ +1^$ +15% +1j% +1A& +1v& +1M' +1$( +1Y( +10) +1e) +1<* +1q* +1H+ +1}+ +1T, +1+- +1`- +17. +1l. +1C/ +1x/ +1O0 +1&1 +1[1 +122 +1g2 +b11111111111111111111111111110000 & +b11111111111111111111111111110000 , +#8000010000 +0*$ +0_$ +06% +0k% +0B& +0w& +0N' +0%( +0Z( +01) +0f) +0=* +0r* +0I+ +0~+ +0U, +0,- +0a- +08. +0m. +0D/ +0y/ +0P0 +0'1 +0\1 +032 +0h2 +#8000020000 +b100010 .$ +b100010 E$ +b100010 H$ +0S$ +b100010 c$ +b100010 z$ +b100010 }$ +0*% +b100010 :% +b100010 Q% +b100010 T% +0_% +b100010 o% +b100010 (& +b100010 +& +06& +b100010 F& +b100010 ]& +b100010 `& +0k& +b100010 {& +b100010 4' +b100010 7' +0B' +b100010 R' +b100010 i' +b100010 l' +0w' +b100010 )( +b100010 @( +b100010 C( +0N( +b100010 ^( +b100010 u( +b100010 x( +0%) +b100010 5) +b100010 L) +b100010 O) +0Z) +b100010 j) +b100010 #* +b100010 &* +01* +b100010 A* +b100010 X* +b100010 [* +0f* +b100010 v* +b100010 /+ +b100010 2+ +0=+ +b100010 M+ +b100010 d+ +b100010 g+ +0r+ +b100010 $, +b100010 ;, +b100010 >, +0I, +b100010 Y, +b100010 p, +b100010 s, +0~, +b100010 0- +b100010 G- +b100010 J- +0U- +b100010 e- +b100010 |- +b100010 !. +0,. +b100010 <. +b100010 S. +b100010 V. +0a. +b100010 q. +b100010 */ +b100010 -/ +08/ +b100010 H/ +b100010 _/ +b100010 b/ +0m/ +b100010 }/ +b100010 60 +b100010 90 +0D0 +b100010 T0 +b100010 k0 +b100010 n0 +0y0 +b100010 +1 +b100010 B1 +b100010 E1 +0P1 +b100010 `1 +b100010 w1 +b100010 z1 +0'2 +b100010 72 +b100010 N2 +b100010 Q2 +0\2 +b100010 l2 +b100010 %3 +b100010 (3 +033 +0/ +#8000030000 +1* +b10100110 .$ +b10100110 E$ +b10100110 H$ +14$ +b10100110 c$ +b10100110 z$ +b10100110 }$ +1i$ +b10100110 :% +b10100110 Q% +b10100110 T% +1@% +b10100110 o% +b10100110 (& +b10100110 +& +1u% +b10100110 F& +b10100110 ]& +b10100110 `& +1L& +b10100110 {& +b10100110 4' +b10100110 7' +1#' +b10100110 R' +b10100110 i' +b10100110 l' +1X' +b10100110 )( +b10100110 @( +b10100110 C( +1/( +b10100110 ^( +b10100110 u( +b10100110 x( +1d( +b10100110 5) +b10100110 L) +b10100110 O) +1;) +b10100110 j) +b10100110 #* +b10100110 &* +1p) +b10100110 A* +b10100110 X* +b10100110 [* +1G* +b10100110 v* +b10100110 /+ +b10100110 2+ +1|* +b10100110 M+ +b10100110 d+ +b10100110 g+ +1S+ +b10100110 $, +b10100110 ;, +b10100110 >, +1*, +b10100110 Y, +b10100110 p, +b10100110 s, +1_, +b10100110 0- +b10100110 G- +b10100110 J- +16- +b10100110 e- +b10100110 |- +b10100110 !. +1k- +b10100110 <. +b10100110 S. +b10100110 V. +1B. +b10100110 q. +b10100110 */ +b10100110 -/ +1w. +b10100110 H/ +b10100110 _/ +b10100110 b/ +1N/ +b10100110 }/ +b10100110 60 +b10100110 90 +1%0 +b10100110 T0 +b10100110 k0 +b10100110 n0 +1Z0 +b10100110 +1 +b10100110 B1 +b10100110 E1 +111 +b10100110 `1 +b10100110 w1 +b10100110 z1 +1f1 +b10100110 72 +b10100110 N2 +b10100110 Q2 +1=2 +b10100110 l2 +b10100110 %3 +b10100110 (3 +1r2 +#8000040000 +0Y$ +00% +0e% +0<& +0q& +0H' +0}' +0T( +0+) +0`) +07* +0l* +0C+ +0x+ +0O, +0&- +0[- +02. +0g. +0>/ +0s/ +0J0 +0!1 +0V1 +0-2 +0b2 +093 +#8000060000 +10 +1>3 +b10100111 .$ +b10100111 E$ +b10100111 H$ +13$ +b10100111 c$ +b10100111 z$ +b10100111 }$ +1h$ +b10100111 :% +b10100111 Q% +b10100111 T% +1?% +b10100111 o% +b10100111 (& +b10100111 +& +1t% +b10100111 F& +b10100111 ]& +b10100111 `& +1K& +b10100111 {& +b10100111 4' +b10100111 7' +1"' +b10100111 R' +b10100111 i' +b10100111 l' +1W' +b10100111 )( +b10100111 @( +b10100111 C( +1.( +b10100111 ^( +b10100111 u( +b10100111 x( +1c( +b10100111 5) +b10100111 L) +b10100111 O) +1:) +b10100111 j) +b10100111 #* +b10100111 &* +1o) +b10100111 A* +b10100111 X* +b10100111 [* +1F* +b10100111 v* +b10100111 /+ +b10100111 2+ +1{* +b10100111 M+ +b10100111 d+ +b10100111 g+ +1R+ +b10100111 $, +b10100111 ;, +b10100111 >, +1), +b10100111 Y, +b10100111 p, +b10100111 s, +1^, +b10100111 0- +b10100111 G- +b10100111 J- +15- +b10100111 e- +b10100111 |- +b10100111 !. +1j- +b10100111 <. +b10100111 S. +b10100111 V. +1A. +b10100111 q. +b10100111 */ +b10100111 -/ +1v. +b10100111 H/ +b10100111 _/ +b10100111 b/ +1M/ +b10100111 }/ +b10100111 60 +b10100111 90 +1$0 +b10100111 T0 +b10100111 k0 +b10100111 n0 +1Y0 +b10100111 +1 +b10100111 B1 +b10100111 E1 +101 +b10100111 `1 +b10100111 w1 +b10100111 z1 +1e1 +b10100111 72 +b10100111 N2 +b10100111 Q2 +1<2 +b10100111 l2 +b10100111 %3 +b10100111 (3 +1q2 +#8000070000 +b10100101 .$ +b10100101 E$ +b10100101 H$ +0X$ +b10100101 c$ +b10100101 z$ +b10100101 }$ +0/% +b10100101 :% +b10100101 Q% +b10100101 T% +0d% +b10100101 o% +b10100101 (& +b10100101 +& +0;& +b10100101 F& +b10100101 ]& +b10100101 `& +0p& +b10100101 {& +b10100101 4' +b10100101 7' +0G' +b10100101 R' +b10100101 i' +b10100101 l' +0|' +b10100101 )( +b10100101 @( +b10100101 C( +0S( +b10100101 ^( +b10100101 u( +b10100101 x( +0*) +b10100101 5) +b10100101 L) +b10100101 O) +0_) +b10100101 j) +b10100101 #* +b10100101 &* +06* +b10100101 A* +b10100101 X* +b10100101 [* +0k* +b10100101 v* +b10100101 /+ +b10100101 2+ +0B+ +b10100101 M+ +b10100101 d+ +b10100101 g+ +0w+ +b10100101 $, +b10100101 ;, +b10100101 >, +0N, +b10100101 Y, +b10100101 p, +b10100101 s, +0%- +b10100101 0- +b10100101 G- +b10100101 J- +0Z- +b10100101 e- +b10100101 |- +b10100101 !. +01. +b10100101 <. +b10100101 S. +b10100101 V. +0f. +b10100101 q. +b10100101 */ +b10100101 -/ +0=/ +b10100101 H/ +b10100101 _/ +b10100101 b/ +0r/ +b10100101 }/ +b10100101 60 +b10100101 90 +0I0 +b10100101 T0 +b10100101 k0 +b10100101 n0 +0~0 +b10100101 +1 +b10100101 B1 +b10100101 E1 +0U1 +b10100101 `1 +b10100101 w1 +b10100101 z1 +0,2 +b10100101 72 +b10100101 N2 +b10100101 Q2 +0a2 +b10100101 l2 +b10100101 %3 +b10100101 (3 +083 +#8000090000 +b1 4 +b1 A3 +15 +#8000120000 +b1 " +b1 3 +b1 B3 +#9000000000 +0)$ +0^$ +05% +0j% +0A& +0v& +0M' +0$( +0Y( +00) +0e) +0<* +0q* +0H+ +0}+ +0T, +0+- +0`- +07. +0l. +0C/ +0x/ +0O0 +0&1 +0[1 +022 +0g2 +1P# +1'$ +1\$ +13% +1h% +1?& +1t& +1K' +1"( +1W( +1.) +1c) +1:* +1o* +1F+ +1{+ +1R, +1)- +1^- +15. +1j. +1A/ +1v/ +1M0 +1$1 +1Y1 +102 +1e2 +b10000 & +b10000 , +b11111111111111111111111111111000 % +b11111111111111111111111111111000 + +#9000010000 +1*$ +1_$ +16% +1k% +1B& +1w& +1N' +1%( +1Z( +11) +1f) +1=* +1r* +1I+ +1~+ +1U, +1,- +1a- +18. +1m. +1D/ +1y/ +1P0 +1'1 +1\1 +132 +1h2 +0Q# +0($ +0]$ +04% +0i% +0@& +0u& +0L' +0#( +0X( +0/) +0d) +0;* +0p* +0G+ +0|+ +0S, +0*- +0_- +06. +0k. +0B/ +0w/ +0N0 +0%1 +0Z1 +012 +0f2 +#9000020000 +b10000110 W# +b10000110 n# +b10000110 q# +1|# +#9000030000 +b10010010 W# +b10010010 n# +b10010010 q# +0]# +1_# +1$$ +#9000040000 +1T$ +1[$ +1+% +12% +1`% +1g% +17& +1>& +1l& +1s& +1C' +1J' +1x' +1!( +1O( +1V( +1&) +1-) +1[) +1b) +12* +19* +1g* +1n* +1>+ +1E+ +1s+ +1z+ +1J, +1Q, +1!- +1(- +1V- +1]- +1-. +14. +1b. +1i. +19/ +1@/ +1n/ +1u/ +1E0 +1L0 +1z0 +1#1 +1Q1 +1X1 +1(2 +1/2 +1]2 +1d2 +143 +1;3 +#9000050000 +1!$ +#9000060000 +1\# +0^# +b10010001 W# +b10010001 n# +b10010001 q# +0#$ +1%$ +#9000070000 +1U$ +b1010 0$ +b1010 7$ +b1010 :$ +1W$ +1,% +b1010 e$ +b1010 l$ +b1010 o$ +1.% +1a% +b1010 <% +b1010 C% +b1010 F% +1c% +18& +b1010 q% +b1010 x% +b1010 {% +1:& +1m& +b1010 H& +b1010 O& +b1010 R& +1o& +1D' +b1010 }& +b1010 &' +b1010 )' +1F' +1y' +b1010 T' +b1010 [' +b1010 ^' +1{' +1P( +b1010 +( +b1010 2( +b1010 5( +1R( +1') +b1010 `( +b1010 g( +b1010 j( +1)) +1\) +b1010 7) +b1010 >) +b1010 A) +1^) +13* +b1010 l) +b1010 s) +b1010 v) +15* +1h* +b1010 C* +b1010 J* +b1010 M* +1j* +1?+ +b1010 x* +b1010 !+ +b1010 $+ +1A+ +1t+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +1K, +b1010 &, +b1010 -, +b1010 0, +1M, +1"- +b1010 [, +b1010 b, +b1010 e, +1$- +1W- +b1010 2- +b1010 9- +b1010 <- +1Y- +1.. +b1010 g- +b1010 n- +b1010 q- +10. +1c. +b1010 >. +b1010 E. +b1010 H. +1e. +1:/ +b1010 s. +b1010 z. +b1010 }. +1- +b1000 ?- +b1000 p- +b1000 s- +b1000 t- +b1000 G. +b1000 J. +b1000 K. +b1000 |. +b1000 !/ +b1000 "/ +b1000 S/ +b1000 V/ +b1000 W/ +b1000 *0 +b1000 -0 +b1000 .0 +b1000 _0 +b1000 b0 +b1000 c0 +b1000 61 +b1000 91 +b1000 :1 +b1000 k1 +b1000 n1 +b1000 o1 +b1000 B2 +b1000 E2 +b1000 F2 +b1000 w2 +b1000 z2 +b1000 {2 +#9000110000 +b1000 h# +b1000 b# +b1000 e# +b1000 f# +#9000130000 +b10 A$ +b10 v$ +b10 M% +b10 $& +b10 Y& +b10 0' +b10 e' +b10 <( +b10 q( +b10 H) +b10 }) +b10 T* +b10 ++ +b10 `+ +b10 7, +b10 l, +b10 C- +b10 x- +b10 O. +b10 &/ +b10 [/ +b10 20 +b10 g0 +b10 >1 +b10 s1 +b10 J2 +b10 !3 +#9000140000 +b10 j# +#9000160000 +b1 >$ +1@$ +b1 s$ +1u$ +b1 J% +1L% +b1 !& +1#& +b1 V& +1X& +b1 -' +1/' +b1 b' +1d' +b1 9( +1;( +b1 n( +1p( +b1 E) +1G) +b1 z) +1|) +b1 Q* +1S* +b1 (+ +1*+ +b1 ]+ +1_+ +b1 4, +16, +b1 i, +1k, +b1 @- +1B- +b1 u- +1w- +b1 L. +1N. +b1 #/ +1%/ +b1 X/ +1Z/ +b1 /0 +110 +b1 d0 +1f0 +b1 ;1 +1=1 +b1 p1 +1r1 +b1 G2 +1I2 +b1 |2 +1~2 +#9000170000 +b1 g# +1i# +#9000190000 +1`$ +17% +1l% +1C& +1x& +1O' +1&( +1[( +12) +1g) +1>* +1s* +1J+ +1!, +1V, +1-- +1b- +19. +1n. +1E/ +1z/ +1Q0 +1(1 +1]1 +142 +1i2 +11$ +1f$ +1=% +1r% +1I& +1~& +1U' +1,( +1a( +18) +1m) +1D* +1y* +1P+ +1', +1\, +13- +1h- +1?. +1t. +1K/ +1"0 +1W0 +1.1 +1c1 +1:2 +b111111111111111111111111111010000 6 +1o2 +#9000200000 +1+$ +b111111111111111111111111111110000 6 +1Z# +#9000220000 +0h$ +1j$ +b10100110 c$ +b10100110 z$ +b10100110 }$ +1/% +0?% +1A% +b10100110 :% +b10100110 Q% +b10100110 T% +1d% +0t% +1v% +b10100110 o% +b10100110 (& +b10100110 +& +1;& +0K& +1M& +b10100110 F& +b10100110 ]& +b10100110 `& +1p& +0"' +1$' +b10100110 {& +b10100110 4' +b10100110 7' +1G' +0W' +1Y' +b10100110 R' +b10100110 i' +b10100110 l' +1|' +0.( +10( +b10100110 )( +b10100110 @( +b10100110 C( +1S( +0c( +1e( +b10100110 ^( +b10100110 u( +b10100110 x( +1*) +0:) +1<) +b10100110 5) +b10100110 L) +b10100110 O) +1_) +0o) +1q) +b10100110 j) +b10100110 #* +b10100110 &* +16* +0F* +1H* +b10100110 A* +b10100110 X* +b10100110 [* +1k* +0{* +1}* +b10100110 v* +b10100110 /+ +b10100110 2+ +1B+ +0R+ +1T+ +b10100110 M+ +b10100110 d+ +b10100110 g+ +1w+ +0), +1+, +b10100110 $, +b10100110 ;, +b10100110 >, +1N, +0^, +1`, +b10100110 Y, +b10100110 p, +b10100110 s, +1%- +05- +17- +b10100110 0- +b10100110 G- +b10100110 J- +1Z- +0j- +1l- +b10100110 e- +b10100110 |- +b10100110 !. +11. +0A. +1C. +b10100110 <. +b10100110 S. +b10100110 V. +1f. +0v. +1x. +b10100110 q. +b10100110 */ +b10100110 -/ +1=/ +0M/ +1O/ +b10100110 H/ +b10100110 _/ +b10100110 b/ +1r/ +0$0 +1&0 +b10100110 }/ +b10100110 60 +b10100110 90 +1I0 +0Y0 +1[0 +b10100110 T0 +b10100110 k0 +b10100110 n0 +1~0 +001 +121 +b10100110 +1 +b10100110 B1 +b10100110 E1 +1U1 +0e1 +1g1 +b10100110 `1 +b10100110 w1 +b10100110 z1 +1,2 +0<2 +1>2 +b10100110 72 +b10100110 N2 +b10100110 Q2 +1a2 +0q2 +1s2 +b10100110 l2 +b10100110 %3 +b10100110 (3 +183 +1$ +#9000230000 +03$ +15$ +b10100110 .$ +b10100110 E$ +b10100110 H$ +1X$ +#9000250000 +b1011 e$ +b1011 l$ +b1011 o$ +1g$ +b1011 <% +b1011 C% +b1011 F% +1>% +b1011 q% +b1011 x% +b1011 {% +1s% +b1011 H& +b1011 O& +b1011 R& +1J& +b1011 }& +b1011 &' +b1011 )' +1!' +b1011 T' +b1011 [' +b1011 ^' +1V' +b1011 +( +b1011 2( +b1011 5( +1-( +b1011 `( +b1011 g( +b1011 j( +1b( +b1011 7) +b1011 >) +b1011 A) +19) +b1011 l) +b1011 s) +b1011 v) +1n) +b1011 C* +b1011 J* +b1011 M* +1E* +b1011 x* +b1011 !+ +b1011 $+ +1z* +b1011 O+ +b1011 V+ +b1011 Y+ +1Q+ +b1011 &, +b1011 -, +b1011 0, +1(, +b1011 [, +b1011 b, +b1011 e, +1], +b1011 2- +b1011 9- +b1011 <- +14- +b1011 g- +b1011 n- +b1011 q- +1i- +b1011 >. +b1011 E. +b1011 H. +1@. +b1011 s. +b1011 z. +b1011 }. +1u. +b1011 J/ +b1011 Q/ +b1011 T/ +1L/ +b1011 !0 +b1011 (0 +b1011 +0 +1#0 +b1011 V0 +b1011 ]0 +b1011 `0 +1X0 +b1011 -1 +b1011 41 +b1011 71 +1/1 +b1011 b1 +b1011 i1 +b1011 l1 +1d1 +b1011 92 +b1011 @2 +b1011 C2 +1;2 +b1011 n2 +b1011 u2 +b1011 x2 +1p2 +1. +00 +#9000260000 +b1011 0$ +b1011 7$ +b1011 :$ +12$ +#9000280000 +1- +b0 4 +b0 A3 +#9000310000 +b0 " +b0 3 +b0 B3 +#10000000000 +1o +1{" +0R# +18 +0P# +0'$ +0\$ +03% +0h% +0?& +0t& +0K' +0"( +0W( +0.) +0c) +0:* +0o* +0F+ +0{+ +0R, +0)- +0^- +05. +0j. +0A/ +0v/ +0M0 +0$1 +0Y1 +002 +0e2 +b10000 7 +b10000 = +b10000 I +b10000 L +b10000 W +b10000 Z +b10000 r +b10000 ~ +b10000 #" +b10000 ." +b10000 1" +b10000 I" +b10000 U" +b10000 X" +b10000 c" +b10000 f" +b10000 ~" +b10000 ,# +b10000 /# +b10000 :# +b10000 =# +b10000 U# +b10000 a# +b10000 d# +b10000 o# +b10000 r# +b10000 ,$ +b10000 8$ +b10000 ;$ +b10000 F$ +b10000 I$ +b10000 a$ +b10000 m$ +b10000 p$ +b10000 {$ +b10000 ~$ +b10000 8% +b10000 D% +b10000 G% +b10000 R% +b10000 U% +b10000 m% +b10000 y% +b10000 |% +b10000 )& +b10000 ,& +b10000 D& +b10000 P& +b10000 S& +b10000 ^& +b10000 a& +b10000 y& +b10000 '' +b10000 *' +b10000 5' +b10000 8' +b10000 P' +b10000 \' +b10000 _' +b10000 j' +b10000 m' +b10000 '( +b10000 3( +b10000 6( +b10000 A( +b10000 D( +b10000 \( +b10000 h( +b10000 k( +b10000 v( +b10000 y( +b10000 3) +b10000 ?) +b10000 B) +b10000 M) +b10000 P) +b10000 h) +b10000 t) +b10000 w) +b10000 $* +b10000 '* +b10000 ?* +b10000 K* +b10000 N* +b10000 Y* +b10000 \* +b10000 t* +b10000 "+ +b10000 %+ +b10000 0+ +b10000 3+ +b10000 K+ +b10000 W+ +b10000 Z+ +b10000 e+ +b10000 h+ +b10000 ", +b10000 ., +b10000 1, +b10000 <, +b10000 ?, +b10000 W, +b10000 c, +b10000 f, +b10000 q, +b10000 t, +b10000 .- +b10000 :- +b10000 =- +b10000 H- +b10000 K- +b10000 c- +b10000 o- +b10000 r- +b10000 }- +b10000 ". +b10000 :. +b10000 F. +b10000 I. +b10000 T. +b10000 W. +b10000 o. +b10000 {. +b10000 ~. +b10000 +/ +b10000 ./ +b10000 F/ +b10000 R/ +b10000 U/ +b10000 `/ +b10000 c/ +b10000 {/ +b10000 )0 +b10000 ,0 +b10000 70 +b10000 :0 +b10000 R0 +b10000 ^0 +b10000 a0 +b10000 l0 +b10000 o0 +b10000 )1 +b10000 51 +b10000 81 +b10000 C1 +b10000 F1 +b10000 ^1 +b10000 j1 +b10000 m1 +b10000 x1 +b10000 {1 +b10000 52 +b10000 A2 +b10000 D2 +b10000 O2 +b10000 R2 +b10000 j2 +b10000 v2 +b10000 y2 +b10000 &3 +b10000 )3 +b1010 & +b1010 , +b1001 % +b1001 + +b100 ' +b100 ) +#10000010000 +0p +0|" +1S# +09 +1Q# +1($ +1]$ +14% +1i% +1@& +1u& +1L' +1#( +1X( +1/) +1d) +1;* +1p* +1G+ +1|+ +1S, +1*- +1_- +16. +1k. +1B/ +1w/ +1N0 +1%1 +1Z1 +112 +1f2 +#10000020000 +b100010 t +b100010 -" +b100010 0" +0;" +b10000101 "# +b10000101 9# +b10000101 <# +1G# +b100010 ? +b100010 V +b100010 Y +0d +b11110001 W# +b11110001 n# +b11110001 q# +b11100110 .$ +b11100110 E$ +b11100110 H$ +1S$ +b11100110 c$ +b11100110 z$ +b11100110 }$ +1*% +b11100110 :% +b11100110 Q% +b11100110 T% +1_% +b11100110 o% +b11100110 (& +b11100110 +& +16& +b11100110 F& +b11100110 ]& +b11100110 `& +1k& +b11100110 {& +b11100110 4' +b11100110 7' +1B' +b11100110 R' +b11100110 i' +b11100110 l' +1w' +b11100110 )( +b11100110 @( +b11100110 C( +1N( +b11100110 ^( +b11100110 u( +b11100110 x( +1%) +b11100110 5) +b11100110 L) +b11100110 O) +1Z) +b11100110 j) +b11100110 #* +b11100110 &* +11* +b11100110 A* +b11100110 X* +b11100110 [* +1f* +b11100110 v* +b11100110 /+ +b11100110 2+ +1=+ +b11100110 M+ +b11100110 d+ +b11100110 g+ +1r+ +b11100110 $, +b11100110 ;, +b11100110 >, +1I, +b11100110 Y, +b11100110 p, +b11100110 s, +1~, +b11100110 0- +b11100110 G- +b11100110 J- +1U- +b11100110 e- +b11100110 |- +b11100110 !. +1,. +b11100110 <. +b11100110 S. +b11100110 V. +1a. +b11100110 q. +b11100110 */ +b11100110 -/ +18/ +b11100110 H/ +b11100110 _/ +b11100110 b/ +1m/ +b11100110 }/ +b11100110 60 +b11100110 90 +1D0 +b11100110 T0 +b11100110 k0 +b11100110 n0 +1y0 +b11100110 +1 +b11100110 B1 +b11100110 E1 +1P1 +b11100110 `1 +b11100110 w1 +b11100110 z1 +1'2 +b11100110 72 +b11100110 N2 +b11100110 Q2 +1\2 +b11100110 l2 +b11100110 %3 +b11100110 (3 +133 +1/ +#10000030000 +b0 3# +b0 h# +b1 y# +b0 ?$ +b0 t$ +b0 K% +b0 "& +b0 W& +b0 .' +b0 c' +b0 :( +b0 o( +b0 F) +b0 {) +b0 R* +b0 )+ +b0 ^+ +b0 5, +b0 j, +b0 A- +b0 v- +b0 M. +b0 $/ +b0 Y/ +b0 00 +b0 e0 +b0 <1 +b0 q1 +b0 H2 +b0 }2 +0* +b0 -# +b0 0# +b0 1# +b0 b# +b0 e# +b0 f# +b10000 p# +b10000 s# +b10000 t# +b0 9$ +b0 <$ +b0 =$ +b0 n$ +b0 q$ +b0 r$ +b0 E% +b0 H% +b0 I% +b0 z% +b0 }% +b0 ~% +b0 Q& +b0 T& +b0 U& +b0 (' +b0 +' +b0 ,' +b0 ]' +b0 `' +b0 a' +b0 4( +b0 7( +b0 8( +b0 i( +b0 l( +b0 m( +b0 @) +b0 C) +b0 D) +b0 u) +b0 x) +b0 y) +b0 L* +b0 O* +b0 P* +b0 #+ +b0 &+ +b0 '+ +b0 X+ +b0 [+ +b0 \+ +b0 /, +b0 2, +b0 3, +b0 d, +b0 g, +b0 h, +b0 ;- +b0 >- +b0 ?- +b0 p- +b0 s- +b0 t- +b0 G. +b0 J. +b0 K. +b0 |. +b0 !/ +b0 "/ +b0 S/ +b0 V/ +b0 W/ +b0 *0 +b0 -0 +b0 .0 +b0 _0 +b0 b0 +b0 c0 +b0 61 +b0 91 +b0 :1 +b0 k1 +b0 n1 +b0 o1 +b0 B2 +b0 E2 +b0 F2 +b0 w2 +b0 z2 +b0 {2 +b10100110 t +b10100110 -" +b10100110 0" +1z +b10010001 "# +b10010001 9# +b10010001 <# +0(# +1*# +b10100110 ? +b10100110 V +b10100110 Y +1E +1e +0j +1l +b1100001 W# +b1100001 n# +b1100001 q# +0_# +b1100010 .$ +b1100010 E$ +b1100010 H$ +04$ +0T$ +1Y$ +0[$ +b1100010 c$ +b1100010 z$ +b1100010 }$ +0i$ +0+% +10% +02% +b1100010 :% +b1100010 Q% +b1100010 T% +0@% +0`% +1e% +0g% +b1100010 o% +b1100010 (& +b1100010 +& +0u% +07& +1<& +0>& +b1100010 F& +b1100010 ]& +b1100010 `& +0L& +0l& +1q& +0s& +b1100010 {& +b1100010 4' +b1100010 7' +0#' +0C' +1H' +0J' +b1100010 R' +b1100010 i' +b1100010 l' +0X' +0x' +1}' +0!( +b1100010 )( +b1100010 @( +b1100010 C( +0/( +0O( +1T( +0V( +b1100010 ^( +b1100010 u( +b1100010 x( +0d( +0&) +1+) +0-) +b1100010 5) +b1100010 L) +b1100010 O) +0;) +0[) +1`) +0b) +b1100010 j) +b1100010 #* +b1100010 &* +0p) +02* +17* +09* +b1100010 A* +b1100010 X* +b1100010 [* +0G* +0g* +1l* +0n* +b1100010 v* +b1100010 /+ +b1100010 2+ +0|* +0>+ +1C+ +0E+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +0S+ +0s+ +1x+ +0z+ +b1100010 $, +b1100010 ;, +b1100010 >, +0*, +0J, +1O, +0Q, +b1100010 Y, +b1100010 p, +b1100010 s, +0_, +0!- +1&- +0(- +b1100010 0- +b1100010 G- +b1100010 J- +06- +0V- +1[- +0]- +b1100010 e- +b1100010 |- +b1100010 !. +0k- +0-. +12. +04. +b1100010 <. +b1100010 S. +b1100010 V. +0B. +0b. +1g. +0i. +b1100010 q. +b1100010 */ +b1100010 -/ +0w. +09/ +1>/ +0@/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +0N/ +0n/ +1s/ +0u/ +b1100010 }/ +b1100010 60 +b1100010 90 +0%0 +0E0 +1J0 +0L0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +0Z0 +0z0 +1!1 +0#1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +011 +0Q1 +1V1 +0X1 +b1100010 `1 +b1100010 w1 +b1100010 z1 +0f1 +0(2 +1-2 +0/2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +0=2 +0]2 +1b2 +0d2 +b1100010 l2 +b1100010 %3 +b1100010 (3 +0r2 +043 +193 +0;3 +#10000040000 +0A" +0H# +1M# +0O# +#10000050000 +1V$ +1-% +1b% +19& +1n& +1E' +1z' +1Q( +1() +1]) +14* +1i* +1@+ +1u+ +1L, +1#- +1X- +1/. +1d. +1;/ +1p/ +1G0 +1|0 +1S1 +1*2 +1_2 +163 +#10000060000 +b1 D# +b0 y# +b0 5# +b0 j# +b1 {# +b0 A$ +b0 v$ +b0 M% +b0 $& +b0 Y& +b0 0' +b0 e' +b0 <( +b0 q( +b0 H) +b0 }) +b0 T* +b0 ++ +b0 `+ +b0 7, +b0 l, +b0 C- +b0 x- +b0 O. +b0 &/ +b0 [/ +b0 20 +b0 g0 +b0 >1 +b0 s1 +b0 J2 +b0 !3 +b10000 ;# +b10000 ># +b10000 ?# +b0 p# +b0 s# +b0 t# +10 +0>3 +b10100111 t +b10100111 -" +b10100111 0" +1y +b10010000 "# +b10010000 9# +b10010000 <# +0'# +b1011 $# +b1011 +# +b1011 .# +1&# +1D +1f +b10100101 ? +b10100101 V +b10100101 Y +0i +b1010 A +b1010 H +b1010 K +1h +b1010 Y# +b1010 `# +b1010 c# +0[# +13$ +05$ +b1100001 .$ +b1100001 E$ +b1100001 H$ +0X$ +1Z$ +b1001 0$ +b1001 7$ +b1001 :$ +0W$ +1h$ +0j$ +b1100001 c$ +b1100001 z$ +b1100001 }$ +0/% +11% +b1001 e$ +b1001 l$ +b1001 o$ +0.% +1?% +0A% +b1100001 :% +b1100001 Q% +b1100001 T% +0d% +1f% +b1001 <% +b1001 C% +b1001 F% +0c% +1t% +0v% +b1100001 o% +b1100001 (& +b1100001 +& +0;& +1=& +b1001 q% +b1001 x% +b1001 {% +0:& +1K& +0M& +b1100001 F& +b1100001 ]& +b1100001 `& +0p& +1r& +b1001 H& +b1001 O& +b1001 R& +0o& +1"' +0$' +b1100001 {& +b1100001 4' +b1100001 7' +0G' +1I' +b1001 }& +b1001 &' +b1001 )' +0F' +1W' +0Y' +b1100001 R' +b1100001 i' +b1100001 l' +0|' +1~' +b1001 T' +b1001 [' +b1001 ^' +0{' +1.( +00( +b1100001 )( +b1100001 @( +b1100001 C( +0S( +1U( +b1001 +( +b1001 2( +b1001 5( +0R( +1c( +0e( +b1100001 ^( +b1100001 u( +b1100001 x( +0*) +1,) +b1001 `( +b1001 g( +b1001 j( +0)) +1:) +0<) +b1100001 5) +b1100001 L) +b1100001 O) +0_) +1a) +b1001 7) +b1001 >) +b1001 A) +0^) +1o) +0q) +b1100001 j) +b1100001 #* +b1100001 &* +06* +18* +b1001 l) +b1001 s) +b1001 v) +05* +1F* +0H* +b1100001 A* +b1100001 X* +b1100001 [* +0k* +1m* +b1001 C* +b1001 J* +b1001 M* +0j* +1{* +0}* +b1100001 v* +b1100001 /+ +b1100001 2+ +0B+ +1D+ +b1001 x* +b1001 !+ +b1001 $+ +0A+ +1R+ +0T+ +b1100001 M+ +b1100001 d+ +b1100001 g+ +0w+ +1y+ +b1001 O+ +b1001 V+ +b1001 Y+ +0v+ +1), +0+, +b1100001 $, +b1100001 ;, +b1100001 >, +0N, +1P, +b1001 &, +b1001 -, +b1001 0, +0M, +1^, +0`, +b1100001 Y, +b1100001 p, +b1100001 s, +0%- +1'- +b1001 [, +b1001 b, +b1001 e, +0$- +15- +07- +b1100001 0- +b1100001 G- +b1100001 J- +0Z- +1\- +b1001 2- +b1001 9- +b1001 <- +0Y- +1j- +0l- +b1100001 e- +b1100001 |- +b1100001 !. +01. +13. +b1001 g- +b1001 n- +b1001 q- +00. +1A. +0C. +b1100001 <. +b1100001 S. +b1100001 V. +0f. +1h. +b1001 >. +b1001 E. +b1001 H. +0e. +1v. +0x. +b1100001 q. +b1100001 */ +b1100001 -/ +0=/ +1?/ +b1001 s. +b1001 z. +b1001 }. +02 +b1100001 72 +b1100001 N2 +b1100001 Q2 +0a2 +1c2 +b1001 92 +b1001 @2 +b1001 C2 +0`2 +1q2 +0s2 +b1100001 l2 +b1100001 %3 +b1100001 (3 +083 +1:3 +b1001 n2 +b1001 u2 +b1001 x2 +073 +#10000070000 +b10100101 t +b10100101 -" +b10100101 0" +0@" +0I# +b10010010 "# +b10010010 9# +b10010010 <# +1L# +b1 $# +b1 +# +b1 .# +0K# +#10000090000 +b1 F# +b0 {# +b0 2# +04# +b0 g# +0i# +b10 u# +1z# +b0 >$ +0@$ +b0 s$ +0u$ +b0 J% +0L% +b0 !& +0#& +b0 V& +0X& +b0 -' +0/' +b0 b' +0d' +b0 9( +0;( +b0 n( +0p( +b0 E) +0G) +b0 z) +0|) +b0 Q* +0S* +b0 (+ +0*+ +b0 ]+ +0_+ +b0 4, +06, +b0 i, +0k, +b0 @- +0B- +b0 u- +0w- +b0 L. +0N. +b0 #/ +0%/ +b0 X/ +0Z/ +b0 /0 +010 +b0 d0 +0f0 +b0 ;1 +0=1 +b0 p1 +0r1 +b0 G2 +0I2 +b0 |2 +0~2 +05 +02$ +b1010 0$ +b1010 7$ +b1010 :$ +1W$ +0g$ +b1010 e$ +b1010 l$ +b1010 o$ +1.% +0>% +b1010 <% +b1010 C% +b1010 F% +1c% +0s% +b1010 q% +b1010 x% +b1010 {% +1:& +0J& +b1010 H& +b1010 O& +b1010 R& +1o& +0!' +b1010 }& +b1010 &' +b1010 )' +1F' +0V' +b1010 T' +b1010 [' +b1010 ^' +1{' +0-( +b1010 +( +b1010 2( +b1010 5( +1R( +0b( +b1010 `( +b1010 g( +b1010 j( +1)) +09) +b1010 7) +b1010 >) +b1010 A) +1^) +0n) +b1010 l) +b1010 s) +b1010 v) +15* +0E* +b1010 C* +b1010 J* +b1010 M* +1j* +0z* +b1010 x* +b1010 !+ +b1010 $+ +1A+ +0Q+ +b1010 O+ +b1010 V+ +b1010 Y+ +1v+ +0(, +b1010 &, +b1010 -, +b1010 0, +1M, +0], +b1010 [, +b1010 b, +b1010 e, +1$- +04- +b1010 2- +b1010 9- +b1010 <- +1Y- +0i- +b1010 g- +b1010 n- +b1010 q- +10. +0@. +b1010 >. +b1010 E. +b1010 H. +1e. +0u. +b1010 s. +b1010 z. +b1010 }. +1* +0s* +0J+ +0!, +0V, +0-- +0b- +09. +0n. +0E/ +0z/ +0Q0 +0(1 +0]1 +042 +0i2 +b10 @# +1E# +b0 u# +0z# +0%# +0Z# +b10000 2 +b10000 @3 +1X# +01$ +0f$ +0=% +0r% +0I& +0~& +0U' +0,( +0a( +08) +0m) +0D* +0y* +0P+ +0', +0\, +03- +0h- +0?. +0t. +0K/ +0"0 +0W0 +0.1 +0c1 +0:2 +b0 6 +0o2 +0- +#10000130000 +b1110 N3 +b11101111 H3 +b1111111111101111 E3 +b11111111111111111111111111101111 1 +b11111111111111111111111111101111 C3 +0V# +#10000150000 +1## +b1000 2 +b1000 @3 +0X# +0\# +0!$ +b1100010 W# +b1100010 n# +b1100010 q# +1#$ +0%$ +03$ +0V$ +b1100010 .$ +b1100010 E$ +b1100010 H$ +1X$ +0Z$ +b10000 " +b10000 3 +b10000 B3 +0h$ +0-% +b1100010 c$ +b1100010 z$ +b1100010 }$ +1/% +01% +0?% +0b% +b1100010 :% +b1100010 Q% +b1100010 T% +1d% +0f% +0t% +09& +b1100010 o% +b1100010 (& +b1100010 +& +1;& +0=& +0K& +0n& +b1100010 F& +b1100010 ]& +b1100010 `& +1p& +0r& +0"' +0E' +b1100010 {& +b1100010 4' +b1100010 7' +1G' +0I' +0W' +0z' +b1100010 R' +b1100010 i' +b1100010 l' +1|' +0~' +0.( +0Q( +b1100010 )( +b1100010 @( +b1100010 C( +1S( +0U( +0c( +0() +b1100010 ^( +b1100010 u( +b1100010 x( +1*) +0,) +0:) +0]) +b1100010 5) +b1100010 L) +b1100010 O) +1_) +0a) +0o) +04* +b1100010 j) +b1100010 #* +b1100010 &* +16* +08* +0F* +0i* +b1100010 A* +b1100010 X* +b1100010 [* +1k* +0m* +0{* +0@+ +b1100010 v* +b1100010 /+ +b1100010 2+ +1B+ +0D+ +0R+ +0u+ +b1100010 M+ +b1100010 d+ +b1100010 g+ +1w+ +0y+ +0), +0L, +b1100010 $, +b1100010 ;, +b1100010 >, +1N, +0P, +0^, +0#- +b1100010 Y, +b1100010 p, +b1100010 s, +1%- +0'- +05- +0X- +b1100010 0- +b1100010 G- +b1100010 J- +1Z- +0\- +0j- +0/. +b1100010 e- +b1100010 |- +b1100010 !. +11. +03. +0A. +0d. +b1100010 <. +b1100010 S. +b1100010 V. +1f. +0h. +0v. +0;/ +b1100010 q. +b1100010 */ +b1100010 -/ +1=/ +0?/ +0M/ +0p/ +b1100010 H/ +b1100010 _/ +b1100010 b/ +1r/ +0t/ +0$0 +0G0 +b1100010 }/ +b1100010 60 +b1100010 90 +1I0 +0K0 +0Y0 +0|0 +b1100010 T0 +b1100010 k0 +b1100010 n0 +1~0 +0"1 +001 +0S1 +b1100010 +1 +b1100010 B1 +b1100010 E1 +1U1 +0W1 +0e1 +0*2 +b1100010 `1 +b1100010 w1 +b1100010 z1 +1,2 +0.2 +0<2 +0_2 +b1100010 72 +b1100010 N2 +b1100010 Q2 +1a2 +0c2 +0q2 +063 +b1100010 l2 +b1100010 %3 +b1100010 (3 +183 +0:3 +0$ +#10000160000 +b111 K3 +b1111 N3 +b11110111 H3 +b1111111111110111 E3 +0!# +b11111111111111111111111111110111 1 +b11111111111111111111111111110111 C3 +1V# +b10 P3 +#10000180000 +b1000 " +b1000 3 +b1000 B3 +0~# +b0 Y# +b0 `# +b0 c# +0"$ +0U$ +b0 0$ +b0 7$ +b0 :$ +0W$ +0,% +b0 e$ +b0 l$ +b0 o$ +0.% +0a% +b0 <% +b0 C% +b0 F% +0c% +08& +b0 q% +b0 x% +b0 {% +0:& +0m& +b0 H& +b0 O& +b0 R& +0o& +0D' +b0 }& +b0 &' +b0 )' +0F' +0y' +b0 T' +b0 [' +b0 ^' +0{' +0P( +b0 +( +b0 2( +b0 5( +0R( +0') +b0 `( +b0 g( +b0 j( +0)) +0\) +b0 7) +b0 >) +b0 A) +0^) +03* +b0 l) +b0 s) +b0 v) +05* +0h* +b0 C* +b0 J* +b0 M* +0j* +0?+ +b0 x* +b0 !+ +b0 $+ +0A+ +0t+ +b0 O+ +b0 V+ +b0 Y+ +0v+ +0K, +b0 &, +b0 -, +b0 0, +0M, +0"- +b0 [, +b0 b, +b0 e, +0$- +0W- +b0 2- +b0 9- +b0 <- +0Y- +0.. +b0 g- +b0 n- +b0 q- +00. +0c. +b0 >. +b0 E. +b0 H. +0e. +0:/ +b0 s. +b0 z. +b0 }. +0# +b0 ?# +b10100111 K" +b10100111 b" +b10100111 e" +1P" +0f +b0 A +b0 H +b0 K +0h +1'# +b0 $# +b0 +# +b0 .# +0&# +b10100101 "# +b10100101 9# +b10100101 <# +0L# +#11000070000 +b10100101 K" +b10100101 b" +b10100101 e" +0u" +#11000090000 +b0 F# +#11000120000 +b0 @# +0E# +#11000150000 +b0 2 +b0 @3 +0## +#11000160000 +b1111 K3 +b11111111 H3 +b1111111111111111 E3 +b11111111111111111111111111111111 1 +b11111111111111111111111111111111 C3 +1!# +#11000180000 +b0 " +b0 3 +b0 B3 +#11000190000 +b11 M3 +#11000220000 +b11 J3 +1L3 +#11000250000 +b11 G3 +1I3 +#11000280000 +b11 D3 +1F3 +#11000310000 +1! +#12000000000 +0: +0F" +18 +1y" +b100000 7 +b100000 = +b100000 I +b100000 L +b100000 W +b100000 Z +b100000 r +b100000 ~ +b100000 #" +b100000 ." +b100000 1" +b100000 I" +b100000 U" +b100000 X" +b100000 c" +b100000 f" +b100000 ~" +b100000 ,# +b100000 /# +b100000 :# +b100000 =# +b100000 U# +b100000 a# +b100000 d# +b100000 o# +b100000 r# +b100000 ,$ +b100000 8$ +b100000 ;$ +b100000 F$ +b100000 I$ +b100000 a$ +b100000 m$ +b100000 p$ +b100000 {$ +b100000 ~$ +b100000 8% +b100000 D% +b100000 G% +b100000 R% +b100000 U% +b100000 m% +b100000 y% +b100000 |% +b100000 )& +b100000 ,& +b100000 D& +b100000 P& +b100000 S& +b100000 ^& +b100000 a& +b100000 y& +b100000 '' +b100000 *' +b100000 5' +b100000 8' +b100000 P' +b100000 \' +b100000 _' +b100000 j' +b100000 m' +b100000 '( +b100000 3( +b100000 6( +b100000 A( +b100000 D( +b100000 \( +b100000 h( +b100000 k( +b100000 v( +b100000 y( +b100000 3) +b100000 ?) +b100000 B) +b100000 M) +b100000 P) +b100000 h) +b100000 t) +b100000 w) +b100000 $* +b100000 '* +b100000 ?* +b100000 K* +b100000 N* +b100000 Y* +b100000 \* +b100000 t* +b100000 "+ +b100000 %+ +b100000 0+ +b100000 3+ +b100000 K+ +b100000 W+ +b100000 Z+ +b100000 e+ +b100000 h+ +b100000 ", +b100000 ., +b100000 1, +b100000 <, +b100000 ?, +b100000 W, +b100000 c, +b100000 f, +b100000 q, +b100000 t, +b100000 .- +b100000 :- +b100000 =- +b100000 H- +b100000 K- +b100000 c- +b100000 o- +b100000 r- +b100000 }- +b100000 ". +b100000 :. +b100000 F. +b100000 I. +b100000 T. +b100000 W. +b100000 o. +b100000 {. +b100000 ~. +b100000 +/ +b100000 ./ +b100000 F/ +b100000 R/ +b100000 U/ +b100000 `/ +b100000 c/ +b100000 {/ +b100000 )0 +b100000 ,0 +b100000 70 +b100000 :0 +b100000 R0 +b100000 ^0 +b100000 a0 +b100000 l0 +b100000 o0 +b100000 )1 +b100000 51 +b100000 81 +b100000 C1 +b100000 F1 +b100000 ^1 +b100000 j1 +b100000 m1 +b100000 x1 +b100000 {1 +b100000 52 +b100000 A2 +b100000 D2 +b100000 O2 +b100000 R2 +b100000 j2 +b100000 v2 +b100000 y2 +b100000 &3 +b100000 )3 +b1010 & +b1010 , +b1001 % +b1001 + +b101 ' +b101 ) +#12000010000 +1; +1G" +09 +0z" +#12000020000 +b11100101 K" +b11100101 b" +b11100101 e" +1p" +b10000101 "# +b10000101 9# +b10000101 <# +1G# +#12000030000 +b10 a +b10 8" +b10 m" +b10 y# +b10 P$ +b10 '% +b10 \% +b10 3& +b10 h& +b10 ?' +b10 t' +b10 K( +b10 ") +b10 W) +b10 .* +b10 c* +b10 :+ +b10 o+ +b10 F, +b10 {, +b10 R- +b10 ). +b10 ^. +b10 5/ +b10 j/ +b10 A0 +b10 v0 +b10 M1 +b10 $2 +b10 Y2 +b10 03 +b100000 X +b100000 [ +b100000 \ +b100000 /" +b100000 2" +b100000 3" +b100000 d" +b100000 g" +b100000 h" +b100000 p# +b100000 s# +b100000 t# +b100000 G$ +b100000 J$ +b100000 K$ +b100000 |$ +b100000 !% +b100000 "% +b100000 S% +b100000 V% +b100000 W% +b100000 *& +b100000 -& +b100000 .& +b100000 _& +b100000 b& +b100000 c& +b100000 6' +b100000 9' +b100000 :' +b100000 k' +b100000 n' +b100000 o' +b100000 B( +b100000 E( +b100000 F( +b100000 w( +b100000 z( +b100000 {( +b100000 N) +b100000 Q) +b100000 R) +b100000 %* +b100000 (* +b100000 )* +b100000 Z* +b100000 ]* +b100000 ^* +b100000 1+ +b100000 4+ +b100000 5+ +b100000 f+ +b100000 i+ +b100000 j+ +b100000 =, +b100000 @, +b100000 A, +b100000 r, +b100000 u, +b100000 v, +b100000 I- +b100000 L- +b100000 M- +b100000 ~- +b100000 #. +b100000 $. +b100000 U. +b100000 X. +b100000 Y. +b100000 ,/ +b100000 // +b100000 0/ +b100000 a/ +b100000 d/ +b100000 e/ +b100000 80 +b100000 ;0 +b100000 <0 +b100000 m0 +b100000 p0 +b100000 q0 +b100000 D1 +b100000 G1 +b100000 H1 +b100000 y1 +b100000 |1 +b100000 }1 +b100000 P2 +b100000 S2 +b100000 T2 +b100000 '3 +b100000 *3 +b100000 +3 +b1100001 K" +b1100001 b" +b1100001 e" +0Q" +b10010001 "# +b10010001 9# +b10010001 <# +0(# +1*# +1M# +#12000040000 +1e +1l +1v" +#12000060000 +b1 c +b1 :" +b1 o" +b1 {# +b1 R$ +b1 )% +b1 ^% +b1 5& +b1 j& +b1 A' +b1 v' +b1 M( +b1 $) +b1 Y) +b1 0* +b1 e* +b1 <+ +b1 q+ +b1 H, +b1 }, +b1 T- +b1 +. +b1 `. +b1 7/ +b1 l/ +b1 C0 +b1 x0 +b1 O1 +b1 &2 +b1 [2 +b1 23 +b1100000 K" +b1100000 b" +b1100000 e" +0P" +0'# +b1 $# +b1 +# +b1 .# +1&# +b10010010 "# +b10010010 9# +b10010010 <# +1L# +#12000070000 +1f +b1010 A +b1010 H +b1010 K +1h +b1100010 K" +b1100010 b" +b1100010 e" +1u" +#12000090000 +b10 ] +1b +b10 4" +19" +b10 i" +1n" +b10 u# +1z# +b10 L$ +1Q$ +b10 #% +1(% +b10 X% +1]% +b10 /& +14& +b10 d& +1i& +b10 ;' +1@' +b10 p' +1u' +b10 G( +1L( +b10 |( +1#) +b10 S) +1X) +b10 ** +1/* +b10 _* +1d* +b10 6+ +1;+ +b10 k+ +1p+ +b10 B, +1G, +b10 w, +1|, +b10 N- +1S- +b10 %. +1*. +b10 Z. +1_. +b10 1/ +16/ +b10 f/ +1k/ +b10 =0 +1B0 +b10 r0 +1w0 +b10 I1 +1N1 +b10 ~1 +1%2 +b10 U2 +1Z2 +b10 ,3 +113 +#12000120000 +1@ +1u +1L" +1X# +1/$ +1d$ +1;% +1p% +1G& +1|& +1S' +1*( +1_( +16) +1k) +1B* +1w* +1N+ +1%, +1Z, +11- +1f- +1=. +1r. +1I/ +1~/ +1U0 +1,1 +1a1 +182 +b11111111111111111111111111110111 2 +b11111111111111111111111111110111 @3 +1m2 +#12000130000 +b1000 K3 +b0 N3 +b0 T3 +b0 W3 +b0 `3 +b0 c3 +b0 i3 +b0 l3 +b1000 H3 +b0 Q3 +b0 ]3 +b0 f3 +b1000 E3 +b0 Z3 +0> +0s +0J" +0V# +0-$ +0b$ +09% +0n% +0E& +0z& +0Q' +0(( +0]( +04) +0i) +0@* +0u* +0L+ +0#, +0X, +0/- +0d- +0;. +0p. +0G/ +0|/ +0S0 +0*1 +0_1 +062 +b1000 1 +b1000 C3 +0k2 +#12000150000 +b11111111111111111111111111110111 " +b11111111111111111111111111110111 3 +b11111111111111111111111111110111 B3 +#12000160000 +b0 M3 +b0 P3 +b0 V3 +b0 Y3 +b0 b3 +b0 e3 +b0 k3 +b0 n3 +#12000180000 +1. +#12000190000 +0L3 +b0 J3 +0O3 +0U3 +b0 S3 +0X3 +0a3 +b0 _3 +0d3 +0j3 +b0 h3 +0m3 +#12000220000 +0I3 +b0 G3 +0R3 +0^3 +b0 \3 +0g3 +#12000250000 +0F3 +b0 D3 +0[3 +#12000280000 +0! +#13000000000 +1: +1F" +08 +0y" +b1111 & +b1111 , +b0 % +b0 + +#13000010000 +0; +0G" +19 +1z" +#13000020000 +b100010 K" +b100010 b" +b100010 e" +0p" +b10110010 "# +b10110010 9# +b10110010 <# +0G# +#13000030000 +b10100110 K" +b10100110 b" +b10100110 e" +1Q" +0e +0l +b10100110 "# +b10100110 9# +b10100110 <# +1(# +0*# +0M# +#13000040000 +0v" +#13000050000 +b10 D# +b100000 ;# +b100000 ># +b100000 ?# +#13000060000 +b10100111 K" +b10100111 b" +b10100111 e" +1P" +0f +b0 A +b0 H +b0 K +0h +1'# +b0 $# +b0 +# +b0 .# +0&# +b10100101 "# +b10100101 9# +b10100101 <# +0L# +#13000070000 +b10100101 K" +b10100101 b" +b10100101 e" +0u" +#13000080000 +b1 F# +#13000110000 +b10 @# +1E# +#13000140000 +b11111111111111111111111111111111 2 +b11111111111111111111111111111111 @3 +1## +#13000150000 +b0 K3 +b0 H3 +b0 E3 +b0 1 +b0 C3 +0!# +#13000170000 +b11111111111111111111111111111111 " +b11111111111111111111111111111111 3 +b11111111111111111111111111111111 B3 +#14000000000 +0: +0F" +18 +1y" +b1000000 7 +b1000000 = +b1000000 I +b1000000 L +b1000000 W +b1000000 Z +b1000000 r +b1000000 ~ +b1000000 #" +b1000000 ." +b1000000 1" +b1000000 I" +b1000000 U" +b1000000 X" +b1000000 c" +b1000000 f" +b1000000 ~" +b1000000 ,# +b1000000 /# +b1000000 :# +b1000000 =# +b1000000 U# +b1000000 a# +b1000000 d# +b1000000 o# +b1000000 r# +b1000000 ,$ +b1000000 8$ +b1000000 ;$ +b1000000 F$ +b1000000 I$ +b1000000 a$ +b1000000 m$ +b1000000 p$ +b1000000 {$ +b1000000 ~$ +b1000000 8% +b1000000 D% +b1000000 G% +b1000000 R% +b1000000 U% +b1000000 m% +b1000000 y% +b1000000 |% +b1000000 )& +b1000000 ,& +b1000000 D& +b1000000 P& +b1000000 S& +b1000000 ^& +b1000000 a& +b1000000 y& +b1000000 '' +b1000000 *' +b1000000 5' +b1000000 8' +b1000000 P' +b1000000 \' +b1000000 _' +b1000000 j' +b1000000 m' +b1000000 '( +b1000000 3( +b1000000 6( +b1000000 A( +b1000000 D( +b1000000 \( +b1000000 h( +b1000000 k( +b1000000 v( +b1000000 y( +b1000000 3) +b1000000 ?) +b1000000 B) +b1000000 M) +b1000000 P) +b1000000 h) +b1000000 t) +b1000000 w) +b1000000 $* +b1000000 '* +b1000000 ?* +b1000000 K* +b1000000 N* +b1000000 Y* +b1000000 \* +b1000000 t* +b1000000 "+ +b1000000 %+ +b1000000 0+ +b1000000 3+ +b1000000 K+ +b1000000 W+ +b1000000 Z+ +b1000000 e+ +b1000000 h+ +b1000000 ", +b1000000 ., +b1000000 1, +b1000000 <, +b1000000 ?, +b1000000 W, +b1000000 c, +b1000000 f, +b1000000 q, +b1000000 t, +b1000000 .- +b1000000 :- +b1000000 =- +b1000000 H- +b1000000 K- +b1000000 c- +b1000000 o- +b1000000 r- +b1000000 }- +b1000000 ". +b1000000 :. +b1000000 F. +b1000000 I. +b1000000 T. +b1000000 W. +b1000000 o. +b1000000 {. +b1000000 ~. +b1000000 +/ +b1000000 ./ +b1000000 F/ +b1000000 R/ +b1000000 U/ +b1000000 `/ +b1000000 c/ +b1000000 {/ +b1000000 )0 +b1000000 ,0 +b1000000 70 +b1000000 :0 +b1000000 R0 +b1000000 ^0 +b1000000 a0 +b1000000 l0 +b1000000 o0 +b1000000 )1 +b1000000 51 +b1000000 81 +b1000000 C1 +b1000000 F1 +b1000000 ^1 +b1000000 j1 +b1000000 m1 +b1000000 x1 +b1000000 {1 +b1000000 52 +b1000000 A2 +b1000000 D2 +b1000000 O2 +b1000000 R2 +b1000000 j2 +b1000000 v2 +b1000000 y2 +b1000000 &3 +b1000000 )3 +b1010 & +b1010 , +b1001 % +b1001 + +b110 ' +b110 ) +#14000010000 +1; +1G" +09 +0z" +#14000020000 +b11100101 K" +b11100101 b" +b11100101 e" +1p" +b10000101 "# +b10000101 9# +b10000101 <# +1G# +#14000030000 +b0 a +b0 8" +b0 m" +b0 D# +b100 y# +b100 P$ +b100 '% +b100 \% +b100 3& +b100 h& +b100 ?' +b100 t' +b100 K( +b100 ") +b100 W) +b100 .* +b100 c* +b100 :+ +b100 o+ +b100 F, +b100 {, +b100 R- +b100 ). +b100 ^. +b100 5/ +b100 j/ +b100 A0 +b100 v0 +b100 M1 +b100 $2 +b100 Y2 +b100 03 +b0 X +b0 [ +b0 \ +b0 /" +b0 2" +b0 3" +b0 d" +b0 g" +b0 h" +b0 ;# +b0 ># +b0 ?# +b1000000 p# +b1000000 s# +b1000000 t# +b1000000 G$ +b1000000 J$ +b1000000 K$ +b1000000 |$ +b1000000 !% +b1000000 "% +b1000000 S% +b1000000 V% +b1000000 W% +b1000000 *& +b1000000 -& +b1000000 .& +b1000000 _& +b1000000 b& +b1000000 c& +b1000000 6' +b1000000 9' +b1000000 :' +b1000000 k' +b1000000 n' +b1000000 o' +b1000000 B( +b1000000 E( +b1000000 F( +b1000000 w( +b1000000 z( +b1000000 {( +b1000000 N) +b1000000 Q) +b1000000 R) +b1000000 %* +b1000000 (* +b1000000 )* +b1000000 Z* +b1000000 ]* +b1000000 ^* +b1000000 1+ +b1000000 4+ +b1000000 5+ +b1000000 f+ +b1000000 i+ +b1000000 j+ +b1000000 =, +b1000000 @, +b1000000 A, +b1000000 r, +b1000000 u, +b1000000 v, +b1000000 I- +b1000000 L- +b1000000 M- +b1000000 ~- +b1000000 #. +b1000000 $. +b1000000 U. +b1000000 X. +b1000000 Y. +b1000000 ,/ +b1000000 // +b1000000 0/ +b1000000 a/ +b1000000 d/ +b1000000 e/ +b1000000 80 +b1000000 ;0 +b1000000 <0 +b1000000 m0 +b1000000 p0 +b1000000 q0 +b1000000 D1 +b1000000 G1 +b1000000 H1 +b1000000 y1 +b1000000 |1 +b1000000 }1 +b1000000 P2 +b1000000 S2 +b1000000 T2 +b1000000 '3 +b1000000 *3 +b1000000 +3 +b1100001 K" +b1100001 b" +b1100001 e" +0Q" +b10010001 "# +b10010001 9# +b10010001 <# +0(# +1*# +1M# +#14000040000 +1e +1l +1v" +#14000050000 +b100 m" +b1000000 d" +b1000000 g" +b1000000 h" +#14000060000 +b0 c +b0 :" +b0 o" +b0 F# +b10 {# +b10 R$ +b10 )% +b10 ^% +b10 5& +b10 j& +b10 A' +b10 v' +b10 M( +b10 $) +b10 Y) +b10 0* +b10 e* +b10 <+ +b10 q+ +b10 H, +b10 }, +b10 T- +b10 +. +b10 `. +b10 7/ +b10 l/ +b10 C0 +b10 x0 +b10 O1 +b10 &2 +b10 [2 +b10 23 +b1100000 K" +b1100000 b" +b1100000 e" +0P" +0'# +b1 $# +b1 +# +b1 .# +1&# +b10010010 "# +b10010010 9# +b10010010 <# +1L# +#14000070000 +1f +b1010 A +b1010 H +b1010 K +1h +b1100010 K" +b1100010 b" +b1100010 e" +1u" +#14000080000 +b10 o" +#14000090000 +b0 ] +0b +b0 4" +09" +b0 @# +0E# +#14000120000 +0@ +0u +b11111111111111111111111111110100 2 +b11111111111111111111111111110100 @3 +0## +#14000130000 +b1011 K3 +b1011 H3 +b1011 E3 +1> +1s +b1011 1 +b1011 C3 +1!# +#14000150000 +b11111111111111111111111111110100 " +b11111111111111111111111111110100 3 +b11111111111111111111111111110100 B3 +#14000160000 +b1 M3 +#15000000000 +1: +1F" +08 +0y" +b1111 & +b1111 , +b0 % +b0 + +#15000010000 +0; +0G" +19 +1z" +#15000020000 +b100010 K" +b100010 b" +b100010 e" +0p" +b10110010 "# +b10110010 9# +b10110010 <# +0G# +#15000030000 +b10100110 K" +b10100110 b" +b10100110 e" +1Q" +0e +0l +b10100110 "# +b10100110 9# +b10100110 <# +1(# +0*# +0M# +#15000040000 +0v" +#15000050000 +b0 m" +b0 d" +b0 g" +b0 h" +#15000060000 +b10100111 K" +b10100111 b" +b10100111 e" +1P" +0f +b0 A +b0 H +b0 K +0h +1'# +b0 $# +b0 +# +b0 .# +0&# +b10100101 "# +b10100101 9# +b10100101 <# +0L# +#15000070000 +b10100101 K" +b10100101 b" +b10100101 e" +0u" +#15000080000 +b0 o" +#15000110000 +b0 i" +0n" +#15000140000 +b11111111111111111111111111110000 2 +b11111111111111111111111111110000 @3 +0L" +#15000150000 +b1111 K3 +b1111 H3 +b1111 E3 +b1111 1 +b1111 C3 +1J" +#15000170000 +b11111111111111111111111111110000 " +b11111111111111111111111111110000 3 +b11111111111111111111111111110000 B3 +#15000180000 +b11 M3 +#15000210000 +b1 J3 +1L3 +#16000000000 +0: +0F" +18 +1y" +b10000000 7 +b10000000 = +b10000000 I +b10000000 L +b10000000 W +b10000000 Z +b10000000 r +b10000000 ~ +b10000000 #" +b10000000 ." +b10000000 1" +b10000000 I" +b10000000 U" +b10000000 X" +b10000000 c" +b10000000 f" +b10000000 ~" +b10000000 ,# +b10000000 /# +b10000000 :# +b10000000 =# +b10000000 U# +b10000000 a# +b10000000 d# +b10000000 o# +b10000000 r# +b10000000 ,$ +b10000000 8$ +b10000000 ;$ +b10000000 F$ +b10000000 I$ +b10000000 a$ +b10000000 m$ +b10000000 p$ +b10000000 {$ +b10000000 ~$ +b10000000 8% +b10000000 D% +b10000000 G% +b10000000 R% +b10000000 U% +b10000000 m% +b10000000 y% +b10000000 |% +b10000000 )& +b10000000 ,& +b10000000 D& +b10000000 P& +b10000000 S& +b10000000 ^& +b10000000 a& +b10000000 y& +b10000000 '' +b10000000 *' +b10000000 5' +b10000000 8' +b10000000 P' +b10000000 \' +b10000000 _' +b10000000 j' +b10000000 m' +b10000000 '( +b10000000 3( +b10000000 6( +b10000000 A( +b10000000 D( +b10000000 \( +b10000000 h( +b10000000 k( +b10000000 v( +b10000000 y( +b10000000 3) +b10000000 ?) +b10000000 B) +b10000000 M) +b10000000 P) +b10000000 h) +b10000000 t) +b10000000 w) +b10000000 $* +b10000000 '* +b10000000 ?* +b10000000 K* +b10000000 N* +b10000000 Y* +b10000000 \* +b10000000 t* +b10000000 "+ +b10000000 %+ +b10000000 0+ +b10000000 3+ +b10000000 K+ +b10000000 W+ +b10000000 Z+ +b10000000 e+ +b10000000 h+ +b10000000 ", +b10000000 ., +b10000000 1, +b10000000 <, +b10000000 ?, +b10000000 W, +b10000000 c, +b10000000 f, +b10000000 q, +b10000000 t, +b10000000 .- +b10000000 :- +b10000000 =- +b10000000 H- +b10000000 K- +b10000000 c- +b10000000 o- +b10000000 r- +b10000000 }- +b10000000 ". +b10000000 :. +b10000000 F. +b10000000 I. +b10000000 T. +b10000000 W. +b10000000 o. +b10000000 {. +b10000000 ~. +b10000000 +/ +b10000000 ./ +b10000000 F/ +b10000000 R/ +b10000000 U/ +b10000000 `/ +b10000000 c/ +b10000000 {/ +b10000000 )0 +b10000000 ,0 +b10000000 70 +b10000000 :0 +b10000000 R0 +b10000000 ^0 +b10000000 a0 +b10000000 l0 +b10000000 o0 +b10000000 )1 +b10000000 51 +b10000000 81 +b10000000 C1 +b10000000 F1 +b10000000 ^1 +b10000000 j1 +b10000000 m1 +b10000000 x1 +b10000000 {1 +b10000000 52 +b10000000 A2 +b10000000 D2 +b10000000 O2 +b10000000 R2 +b10000000 j2 +b10000000 v2 +b10000000 y2 +b10000000 &3 +b10000000 )3 +b1010 & +b1010 , +b1001 % +b1001 + +b111 ' +b111 ) +#16000010000 +1; +1G" +09 +0z" +#16000020000 +b11100101 K" +b11100101 b" +b11100101 e" +1p" +b10000101 "# +b10000101 9# +b10000101 <# +1G# +#16000030000 +b1000 a +b1000 8" +b1000 m" +b1000 D# +b0 y# +b0 P$ +b0 '% +b0 \% +b0 3& +b0 h& +b0 ?' +b0 t' +b0 K( +b0 ") +b0 W) +b0 .* +b0 c* +b0 :+ +b0 o+ +b0 F, +b0 {, +b0 R- +b0 ). +b0 ^. +b0 5/ +b0 j/ +b0 A0 +b0 v0 +b0 M1 +b0 $2 +b0 Y2 +b0 03 +b10000000 X +b10000000 [ +b10000000 \ +b10000000 /" +b10000000 2" +b10000000 3" +b10000000 d" +b10000000 g" +b10000000 h" +b10000000 ;# +b10000000 ># +b10000000 ?# +b0 p# +b0 s# +b0 t# +b0 G$ +b0 J$ +b0 K$ +b0 |$ +b0 !% +b0 "% +b0 S% +b0 V% +b0 W% +b0 *& +b0 -& +b0 .& +b0 _& +b0 b& +b0 c& +b0 6' +b0 9' +b0 :' +b0 k' +b0 n' +b0 o' +b0 B( +b0 E( +b0 F( +b0 w( +b0 z( +b0 {( +b0 N) +b0 Q) +b0 R) +b0 %* +b0 (* +b0 )* +b0 Z* +b0 ]* +b0 ^* +b0 1+ +b0 4+ +b0 5+ +b0 f+ +b0 i+ +b0 j+ +b0 =, +b0 @, +b0 A, +b0 r, +b0 u, +b0 v, +b0 I- +b0 L- +b0 M- +b0 ~- +b0 #. +b0 $. +b0 U. +b0 X. +b0 Y. +b0 ,/ +b0 // +b0 0/ +b0 a/ +b0 d/ +b0 e/ +b0 80 +b0 ;0 +b0 <0 +b0 m0 +b0 p0 +b0 q0 +b0 D1 +b0 G1 +b0 H1 +b0 y1 +b0 |1 +b0 }1 +b0 P2 +b0 S2 +b0 T2 +b0 '3 +b0 *3 +b0 +3 +b1100001 K" +b1100001 b" +b1100001 e" +0Q" +b10010001 "# +b10010001 9# +b10010001 <# +0(# +1*# +1M# +#16000040000 +1e +1l +1v" +#16000060000 +b0 m" +b10 c +b10 :" +b10 o" +b10 F# +b0 {# +b0 R$ +b0 )% +b0 ^% +b0 5& +b0 j& +b0 A' +b0 v' +b0 M( +b0 $) +b0 Y) +b0 0* +b0 e* +b0 <+ +b0 q+ +b0 H, +b0 }, +b0 T- +b0 +. +b0 `. +b0 7/ +b0 l/ +b0 C0 +b0 x0 +b0 O1 +b0 &2 +b0 [2 +b0 23 +b0 d" +b0 g" +b0 h" +b1100000 K" +b1100000 b" +b1100000 e" +0P" +0'# +b1 $# +b1 +# +b1 .# +1&# +b10010010 "# +b10010010 9# +b10010010 <# +1L# +#16000070000 +1f +b1010 A +b1010 H +b1010 K +1h +b1100010 K" +b1100010 b" +b1100010 e" +1u" +#16000090000 +b0 o" +b10 ] +1b +b10 4" +19" +b10 i" +1n" +b10 @# +1E# +b0 u# +0z# +b0 L$ +0Q$ +b0 #% +0(% +b0 X% +0]% +b0 /& +04& +b0 d& +0i& +b0 ;' +0@' +b0 p' +0u' +b0 G( +0L( +b0 |( +0#) +b0 S) +0X) +b0 ** +0/* +b0 _* +0d* +b0 6+ +0;+ +b0 k+ +0p+ +b0 B, +0G, +b0 w, +0|, +b0 N- +0S- +b0 %. +0*. +b0 Z. +0_. +b0 1/ +06/ +b0 f/ +0k/ +b0 =0 +0B0 +b0 r0 +0w0 +b0 I1 +0N1 +b0 ~1 +0%2 +b0 U2 +0Z2 +b0 ,3 +013 +#16000120000 +b0 i" +0n" +1@ +1u +1L" +1## +0X# +0/$ +0d$ +0;% +0p% +0G& +0|& +0S' +0*( +0_( +06) +0k) +0B* +0w* +0N+ +0%, +0Z, +01- +0f- +0=. +0r. +0I/ +0~/ +0U0 +0,1 +0a1 +082 +b1111 2 +b1111 @3 +0m2 +#16000130000 +b0 K3 +b1111 N3 +b1111 T3 +b1111 W3 +b1111 `3 +b1111 c3 +b1111 i3 +b1111 l3 +b11110000 H3 +b11111111 Q3 +b11111111 ]3 +b11111111 f3 +b1111111111110000 E3 +b1111111111111111 Z3 +0> +0s +0J" +0!# +1V# +1-$ +1b$ +19% +1n% +1E& +1z& +1Q' +1(( +1]( +14) +1i) +1@* +1u* +1L+ +1#, +1X, +1/- +1d- +1;. +1p. +1G/ +1|/ +1S0 +1*1 +1_1 +162 +b11111111111111111111111111110000 1 +b11111111111111111111111111110000 C3 +1k2 +#16000150000 +b1011 2 +b1011 @3 +0L" +b1111 " +b1111 3 +b1111 B3 +#16000160000 +b100 K3 +b11110100 H3 +b1111111111110100 E3 +b11111111111111111111111111110100 1 +b11111111111111111111111111110100 C3 +1J" +b0 M3 +b11 P3 +b11 V3 +b11 Y3 +b11 b3 +b11 e3 +b11 k3 +b11 n3 +#16000180000 +b1011 " +b1011 3 +b1011 B3 +0. +#16000190000 +0L3 +b10 J3 +1O3 +1U3 +b11 S3 +1X3 +1a3 +b11 _3 +1d3 +1j3 +b11 h3 +1m3 +#16000220000 +b10 G3 +1R3 +1^3 +b11 \3 +1g3 +#16000250000 +b10 D3 +1[3 +#17000000000 +1: +1F" +08 +0y" +b1111 & +b1111 , +b0 % +b0 + +#17000010000 +0; +0G" +19 +1z" +#17000020000 +b100010 K" +b100010 b" +b100010 e" +0p" +b10110010 "# +b10110010 9# +b10110010 <# +0G# +#17000030000 +b10100110 K" +b10100110 b" +b10100110 e" +1Q" +0e +0l +b10100110 "# +b10100110 9# +b10100110 <# +1(# +0*# +0M# +#17000040000 +0v" +#17000060000 +b1000 m" +b10000000 d" +b10000000 g" +b10000000 h" +b10100111 K" +b10100111 b" +b10100111 e" +1P" +0f +b0 A +b0 H +b0 K +0h +1'# +b0 $# +b0 +# +b0 .# +0&# +b10100101 "# +b10100101 9# +b10100101 <# +0L# +#17000070000 +b10100101 K" +b10100101 b" +b10100101 e" +0u" +#17000090000 +b10 o" +#17000120000 +b10 i" +1n" +#17000150000 +b1111 2 +b1111 @3 +1L" +#17000160000 +b0 K3 +b11110000 H3 +b1111111111110000 E3 +b11111111111111111111111111110000 1 +b11111111111111111111111111110000 C3 +0J" +#17000180000 +b1111 " +b1111 3 +b1111 B3 +#18000000000 diff --git a/alu1.v b/alu1.v new file mode 100644 index 0000000..afab236 --- /dev/null +++ b/alu1.v @@ -0,0 +1,178 @@ +`define XOR xor #30 +`define OR or #30 +`define AND and #30 +`define NOT not #10 +`define XNOR xnor #20 +`define NOR nor #20 +`define NAND nand #20 + +module or4(output out, input[3:0] in); + wire[1:0] ors; + `OR or_1(ors[0], in[0], in[1]); + `OR or_2(ors[1], in[2], in[3]); + `OR or_3(out, ors[0], ors[1]); +endmodule + +module or8(output out, input[7:0] in); + wire[1:0] ors; + or4 or_1(ors[0], in[3:0]); + or4 or_2(ors[1], in[7:4]); + `OR or_3(out, ors[0], ors[1]); +endmodule + +module and4(output out, input[3:0] in); + wire[1:0] ands; + `AND and_1(ands[0], in[0], in[1]); + `AND and_2(ands[1], in[2], in[3]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and8(output out, input[7:0] in); + wire[1:0] ands; + and4 and_1(ands[0], in[3:0]); + and4 and_2(ands[1], in[7:4]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and16(output out, input[15:0] in); + wire[1:0] ands; + and8 and_1(ands[0], in[7:0]); + and8 and_2(ands[1], in[15:8]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and32(output out, input[31:0] in); + wire[1:0] ands; + and16 and_1(ands[0], in[15:0]); + and16 and_2(ands[1], in[31:16]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and8P(output[7:0] out, input[7:0] A, input[7:0] B); + genvar i; + generate + for(i = 0; i<8; i=i+1) begin: and_slces + `AND and_inst(out[i], A[i], B[i]); + end + endgenerate +endmodule + +module or32P(output[31:0] out, input[31:0] A, input[31:0] B); + genvar i; + generate + for(i = 0; i<32; i=i+1) begin: or_slces + `OR or_inst(out[i], A[i], B[i]); + end + endgenerate +endmodule + +module unaryMultiplexor(output out, input[7:0] in, input[7:0] sel); + wire[7:0] ands; + and8P andP(ands, in, sel); + or8 ors(out, ands); +endmodule + +module halfAdder( + output sum, + output carryout, + input a, + input b +); + `XOR axorb(sum,a,b); + `AND aandb(carryout,a,b); +endmodule + +module fullAdder +( + output sum, + output carryout, + input a, + input b, + input carryin +); + wire s1; + wire c1; + wire c2; + halfAdder a1(s1,c1,a,b); + halfAdder a2(sum, c2, s1, carryin); + `OR (carryout, c1, c2); +endmodule + +module slt(output out, + input carryin, + input a, input a_, + input b, input b_); + wire lt; + wire eq; + wire w0; + wire invertSLT; + // a bitwise SLT implementation + // if a==b, pass on carry in. + // if a>b, return 1 + // if a carryin[n+1] + // note that this will always be wrong if + // the signs of A and B are opposite. + `XNOR xnorGate(eq, a, b); + `AND ltAnd(lt, a, b_); + `AND and0(w0, eq, carryin); + `OR or1(out, w0, lt); +endmodule + +module mux1(output out, input a, input b, input s); + wire s_; + wire w0; + wire w1; + + `NOT sNot(s_,s); + `AND aAnd(w0, a, s_); + `AND bAnd(w1, b, s); + `OR(out,w0,w1); +endmodule + +`define ADDSig command[0] +`define SUBSig command[1] +`define XORSig command[2] +`define SLTSig command[3] +`define ANDSig command[4] +`define NANDSig command[5] +`define NORSig command[6] +`define ORSig command[7] + +module alu1( + output result, + output carryout, + output zero, + input A, + input B, + input carryin, + input[7:0] command +); +wire[7:0] results; +wire result; +wire[7:0] carryouts; +wire A_, B_; +`NOT an(A_, A); +`NOT bn(B_, B); +fullAdder adder(results[0], carryouts[0], A, B, carryin); +fullAdder sub(results[1], carryouts[1], A, B_, carryin); +`XOR xorGate(results[2], A, B); +`OR(carryouts[2], 0, 0); +//slt is odd. Only the first bit is ever set, but it depends +//on the lest bit. The actual result is handled later, +//in the full ALU +slt sltGate(carryouts[3], carryin, A, A_, B, B_); +`OR falseGate(results[3], 0, 0); + +`AND andGate(results[4], A, B); +`OR(carryouts[4], 0, 0); +`NAND nandGate(results[5], A, B); +`OR(carryouts[5], 0, 0); +`NOR norGate(results[6], A, B); +`OR(carryouts[6], 0, 0); +`OR orGate(results[7], A, B); +`OR(carryouts[7], 0, 0); +unaryMultiplexor resMux(result, results, command); +unaryMultiplexor cMux(carryout, carryouts, command); +`NOT(zero, result); +endmodule diff --git a/alu_wrapper.v b/alu_wrapper.v new file mode 100644 index 0000000..9971958 --- /dev/null +++ b/alu_wrapper.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps +`include "alu.v" + + +//-------------------------------------------------------------------------------- +// Basic building block modules +//-------------------------------------------------------------------------------- + +// D flip-flop with parameterized bit width (default: 1-bit) +// Parameters in Verilog: http://www.asic-world.com/verilog/para_modules1.html +module dff #( parameter W = 1 ) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @(posedge trigger) begin + if(enable) begin + q <= d; + end + end +endmodule + +// JK flip-flop +module jkff1 +( + input trigger, + input j, + input k, + output reg q +); + always @(posedge trigger) begin + if(j && ~k) begin + q <= 1'b1; + end + else if(k && ~j) begin + q <= 1'b0; + end + else if(k && j) begin + q <= ~q; + end + end +endmodule + +// Two-input MUX with parameterized bit width (default: 1-bit) +module mux2 #( parameter W = 1 ) +( + input[W-1:0] in0, + input[W-1:0] in1, + input sel, + output[W-1:0] out +); + // Conditional operator - http://www.verilog.renerta.com/source/vrg00010.htm + assign out = (sel) ? in1 : in0; +endmodule + + + +module alu_wrapper +( + input clk, + input [3:0] sw, + input [3:0] btn, + output [3:0] led +); + + wire[31:0] opA, opB; // Stored inputs to ALU + wire[2:0] command; + wire[31:0] res0; + wire[3:0] res1; // Output display options + wire res_sel; // Select between display options + wire cout; // Carry out from ALU + wire ovf; // Overflow from ALU + wire zero; // Zero flag from ALU + + + // Memory for stored operands (parametric width set to 4 bits) + dff #(4) opA_mem(.trigger(clk), .enable(btn[0]), .d(sw), .q(opA[0 +:4])); + dff #(4) opB_mem(.trigger(clk), .enable(btn[1]), .d(sw), .q(opB[0 +:4])); + dff #(3) cmd_mem(.trigger(clk), .enable(btn[2]), .d(sw[0+:3]), .q(command)); + + // Capture button input to switch which MUX input to LEDs + jkff1 src_sel(.trigger(clk), .j(btn[3]), .k(btn[2]), .q(res_sel)); + mux2 #(4) output_select(.in0(res0[0 +:4]), .in1(res1), .sel(res_sel), .out(led)); + + // TODO: You write this in your adder.v + ALU alu(.result(res0), .carryout(cout), .zero(zero), .overflow(ovf), .operandA(opA), .operandB(opB), .command(command)); + + // Assign bits of second display output to show carry out and overflow + assign res1[0] = cout; + assign res1[1] = ovf; + assign res1[2] = zero; + assign res1[3] = 1'b0; + +endmodule diff --git a/work_plan.txt b/work_plan.txt new file mode 100644 index 0000000..c477794 --- /dev/null +++ b/work_plan.txt @@ -0,0 +1,4 @@ +write tests (4 hrs) : 10/7 +write verilog (2 hrs) : 10/8 +fix tests (1 hr) : 10/8 +fpga integration (1 hr - ∞) : 10/11 - 10/13