From 0c9ea77fe8bccb802189986832d0f77976c86ffb Mon Sep 17 00:00:00 2001 From: TShapinsky Date: Wed, 4 Oct 2017 23:28:42 -0400 Subject: [PATCH 01/26] added work plan --- work_plan.txt | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 work_plan.txt diff --git a/work_plan.txt b/work_plan.txt new file mode 100644 index 0000000..c477794 --- /dev/null +++ b/work_plan.txt @@ -0,0 +1,4 @@ +write tests (4 hrs) : 10/7 +write verilog (2 hrs) : 10/8 +fix tests (1 hr) : 10/8 +fpga integration (1 hr - ∞) : 10/11 - 10/13 From 1833002c8fe397584df9a0c8f66cb22c55282f52 Mon Sep 17 00:00:00 2001 From: Henry Rachootin Date: Sun, 8 Oct 2017 17:02:52 -0400 Subject: [PATCH 02/26] added api for 1 bit alu --- alu1.v | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 alu1.v diff --git a/alu1.v b/alu1.v new file mode 100644 index 0000000..5b9a55f --- /dev/null +++ b/alu1.v @@ -0,0 +1,9 @@ +module alu1( + output result, + output carryout, + output zero, + input A, + input B, + input carryin, + input[7:0] command +) From d40d4a46d5a19fcfeff3496b86e69eebddd523bd Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Sun, 8 Oct 2017 17:30:29 -0400 Subject: [PATCH 03/26] implemented alu --- alu.v | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 alu.v diff --git a/alu.v b/alu.v new file mode 100644 index 0000000..880457c --- /dev/null +++ b/alu.v @@ -0,0 +1,34 @@ +`include alu1.v +module ALU +( +output[31:0] result, +output carryout, +output zero, +output overflow, +input[31:0] operandA, +input[31:0] operandB, +input[2:0] command + ); + + initial begin + wire carryinbus [32:0]; + wire zerobus [31:0]; + + wire commandslice [7:0]; + assign commandslice=1< Date: Sun, 8 Oct 2017 17:54:57 -0400 Subject: [PATCH 04/26] Made a bit slice. SLT needs to be implemented in the higher level code. --- alu1.v | 120 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 1 deletion(-) diff --git a/alu1.v b/alu1.v index 5b9a55f..44e855e 100644 --- a/alu1.v +++ b/alu1.v @@ -1,3 +1,103 @@ +`define XOR xor #30 +`define OR or #30 +`define AND and #30 +`define NOT not #10 +`define XNOR xnor #20 +`define NOR xor #20 +`define NAND nand #20 + +module or4(output out, input[3:0] in); + wire[1:0] ors; + `OR or_1(ors[0], in[0], in[1]); + `OR or_2(ors[1], in[2], in[3]); + `OR or_3(out, ors[0], ors[1]); +endmodule + +module or8(output out, input[7:0] in); + wire[1:0] ors; + or4 or_1(ors[0], in[3:0]); + or4 or_2(ors[1], in[7:4]); + `OR or_3(out, ors[0], ors[1]); +endmodule + +module and4(output out, input[3:0] in); + wire[1:0] ands; + `AND and_1(ands[0], in[0], in[1]); + `AND and_2(ands[1], in[2], in[3]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and8(output out, input[7:0] in); + wire[1:0] ands; + and4 and_1(ands[0], in[3:0]); + and4 and_2(ands[1], in[7:4]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and16(output out, input[15:0] in); + wire[1:0] ands; + and8 and_1(ands[0], in[7:0]); + and8 and_2(ands[1], in[15:8]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and32(output out, input[31:0] in); + wire[1:0] ands; + and16 and_1(ands[0], in[15:0]); + and16 and_2(ands[1], in[31:16]); + `AND and_3(out, ands[0], ands[1]); +endmodule + +module and8P(output[7:0] out, input[7:0] A, input[7:0] B); + genvar i; + generate + for(i = 0; i<8; i++) + `AND and_inst(out[i], A[i], B[i]); + end + endgenerate +endmodule + +module unaryMultiplexor(output out, input[7:0] in, input[7:0] sel); + wire[7:0] ands; + and8P andP(ands, in, sel); + or4 ors[out, ands]; +endmodule + +module halfAdder( + output sum, + output carryout, + input a, + input b +); + `XOR axorb(sum,a,b); + `AND aandb(carryout,a,b); +endmodule + +module fullAdder +( + output sum, + output carryout, + input a, + input b, + input carryin +); + wire s1; + wire c1; + wire c2; + halfAdder a1(s1,c1,a,b); + halfAdder a2(sum, c2, s1, carryin); + `OR (carryout, c1, c2); +endmodule + +`define ADDSig command[0] +`define SUBSig command[1] +`define XORSig command[2] +`define SLTSig command[3] +`define ANDSig command[4] +`define NANDSig command[5] +`define NORSig command[6] +`define ORSig command[7] + module alu1( output result, output carryout, @@ -6,4 +106,22 @@ module alu1( input B, input carryin, input[7:0] command -) +); +wire[7:0] results; +wire[7:0] caryouts; +wire A_, B_; +`NOT an(A_, A); +`NOT bn(B_, B); +fullAdder adder(results[0], carryouts[0], A, B, carryin); +fullAdder sub(results[1], carryouts[1], A, B_, carryin); +`XOR xor(results[2], A, B); +fullAdder slt(results[3], carryouts[3], A, B_, carryin); +`AND and(results[4], A, B); +`NAND nand(results[5], A, B); +`NOR nor(results[6], A, B); +`OR or(results[7], A, B); + +unaryMultiplexor resMux(result, results, command); +unaryMultiplexor cMux(carryout, carryouts, command); + +endmodule From eeb014c8a7a5f79d042bb597f0cd440b953d52d7 Mon Sep 17 00:00:00 2001 From: Henry Rachootin Date: Tue, 10 Oct 2017 01:22:30 -0400 Subject: [PATCH 05/26] made some changes. made a ALU --- alu | 17973 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ alu.t.v | 54 + alu.v | 85 +- alu1.v | 55 +- 4 files changed, 18132 insertions(+), 35 deletions(-) create mode 100755 alu create mode 100644 alu.t.v diff --git a/alu b/alu new file mode 100755 index 0000000..1510f9d --- /dev/null +++ b/alu @@ -0,0 +1,17973 @@ +#! /usr/local/bin/vvp +:ivl_version "0.10.0 (devel)" "(s20150513)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_0x17c4680 .scope module, "testALU" "testALU" 2 4; + .timescale -9 -12; +v0x1d6e5c0_0 .var/s "a", 31 0; +v0x1d6e6d0_0 .var/s "b", 31 0; +v0x1d6e7a0_0 .net "carryout", 0 0, L_0x1eac600; 1 drivers +v0x1d6e8a0_0 .var "command", 2 0; +v0x1d6e970_0 .net "overflow", 0 0, L_0x1eb5e20; 1 drivers +v0x1d6ea10_0 .net/s "result", 31 0, L_0x1eba0f0; 1 drivers +v0x1d6eb00_0 .net "zero", 0 0, L_0x1eb5590; 1 drivers +S_0x1a570b0 .scope module, "dut" "ALU" 2 13, 3 2 0, S_0x17c4680; + .timescale -9 -12; + .port_info 0 /OUTPUT 32 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /OUTPUT 1 "overflow" + .port_info 4 /INPUT 32 "operandA" + .port_info 5 /INPUT 32 "operandB" + .port_info 6 /INPUT 3 "command" +L_0x1e0c750/d .functor OR 1, L_0x1ead720, L_0x1eac560, C4<0>, C4<0>; +L_0x1e0c750 .delay 1 (30000,30000,30000) L_0x1e0c750/d; +L_0x1eac600/d .functor OR 1, L_0x1eac670, L_0x1eac710, C4<0>, C4<0>; +L_0x1eac600 .delay 1 (30000,30000,30000) L_0x1eac600/d; +L_0x1eb58a0/d .functor XOR 1, L_0x1eb5960, L_0x1eac600, C4<0>, C4<0>; +L_0x1eb58a0 .delay 1 (30000,30000,30000) L_0x1eb58a0/d; +L_0x1ead7c0/d .functor XNOR 1, L_0x1ead880, L_0x1ead9e0, C4<0>, C4<0>; +L_0x1ead7c0 .delay 1 (20000,20000,20000) L_0x1ead7c0/d; +L_0x1eb5e20/d .functor AND 1, L_0x1eb58a0, L_0x1ead7c0, C4<1>, C4<1>; +L_0x1eb5e20 .delay 1 (30000,30000,30000) L_0x1eb5e20/d; +L_0x1eb5fd0/d .functor NOT 1, L_0x1ead7c0, C4<0>, C4<0>, C4<0>; +L_0x1eb5fd0 .delay 1 (10000,10000,10000) L_0x1eb5fd0/d; +L_0x1eb6130/d .functor AND 1, L_0x1eb61f0, L_0x1eb6350, C4<1>, C4<1>; +L_0x1eb6130 .delay 1 (30000,30000,30000) L_0x1eb6130/d; +L_0x1eb7020/d .functor XOR 1, L_0x1eb6130, L_0x1eb5fd0, C4<0>, C4<0>; +L_0x1eb7020 .delay 1 (30000,30000,30000) L_0x1eb7020/d; +v0x1d6b100_0 .net *"_s106", 0 0, L_0x1dd18f0; 1 drivers +v0x1d6b1e0_0 .net *"_s117", 0 0, L_0x1ddb510; 1 drivers +v0x1d6b2c0_0 .net *"_s128", 0 0, L_0x1de5140; 1 drivers +v0x1d6b380_0 .net *"_s139", 0 0, L_0x1deed50; 1 drivers +v0x1d6b460_0 .net *"_s150", 0 0, L_0x1df8990; 1 drivers +v0x1d6b590_0 .net *"_s161", 0 0, L_0x1e02570; 1 drivers +v0x1d6b670_0 .net *"_s172", 0 0, L_0x1e0c380; 1 drivers +v0x1d6b750_0 .net *"_s18", 0 0, L_0x1d825d0; 1 drivers +v0x1d6b830_0 .net *"_s183", 0 0, L_0x1e16100; 1 drivers +v0x1d6b9a0_0 .net *"_s194", 0 0, L_0x1e1ff60; 1 drivers +v0x1d6ba80_0 .net *"_s205", 0 0, L_0x1e29b50; 1 drivers +v0x1d6bb60_0 .net *"_s216", 0 0, L_0x1e337b0; 1 drivers +v0x1d6bc40_0 .net *"_s227", 0 0, L_0x1e3d430; 1 drivers +v0x1d6bd20_0 .net *"_s238", 0 0, L_0x1da9440; 1 drivers +v0x1d6be00_0 .net *"_s249", 0 0, L_0x1e52d40; 1 drivers +v0x1d6bee0_0 .net *"_s260", 0 0, L_0x1e5c8a0; 1 drivers +v0x1d6bfc0_0 .net *"_s271", 0 0, L_0x1e665a0; 1 drivers +v0x1d6c170_0 .net *"_s282", 0 0, L_0x1e70230; 1 drivers +v0x1d6c210_0 .net *"_s29", 0 0, L_0x1d8bf80; 1 drivers +v0x1d6c2f0_0 .net *"_s293", 0 0, L_0x1e79e70; 1 drivers +v0x1d6c3d0_0 .net *"_s304", 0 0, L_0x1e83ae0; 1 drivers +v0x1d6c4b0_0 .net *"_s315", 0 0, L_0x1e8d720; 1 drivers +v0x1d6c590_0 .net *"_s326", 0 0, L_0x1e97330; 1 drivers +v0x1d6c670_0 .net *"_s337", 0 0, L_0x1ea0f80; 1 drivers +v0x1d6c750_0 .net *"_s350", 0 0, L_0x1ea5000; 1 drivers +v0x1d6c830_0 .net *"_s352", 0 0, L_0x1e0c750; 1 drivers +v0x1d6c910_0 .net *"_s356", 0 0, L_0x1ead720; 1 drivers +v0x1d6c9f0_0 .net *"_s358", 0 0, L_0x1eac560; 1 drivers +v0x1d6cad0_0 .net *"_s360", 0 0, L_0x1eac670; 1 drivers +v0x1d6cbb0_0 .net *"_s362", 0 0, L_0x1eac710; 1 drivers +v0x1d6cc90_0 .net *"_s364", 0 0, L_0x1eb5960; 1 drivers +v0x1d6cd70_0 .net *"_s366", 0 0, L_0x1ead880; 1 drivers +v0x1d6ce50_0 .net *"_s368", 0 0, L_0x1ead9e0; 1 drivers +v0x1d6c0a0_0 .net *"_s370", 0 0, L_0x1eb61f0; 1 drivers +v0x1d6d120_0 .net *"_s372", 0 0, L_0x1eb6350; 1 drivers +v0x1d6d200_0 .net *"_s373", 0 0, L_0x1eb7020; 1 drivers +v0x1d6d2e0_0 .net *"_s40", 0 0, L_0x1d95f40; 1 drivers +v0x1d6d3c0_0 .net *"_s51", 0 0, L_0x1d95cb0; 1 drivers +v0x1d6d4a0_0 .net *"_s62", 0 0, L_0x1daa440; 1 drivers +v0x1d6d580_0 .net *"_s73", 0 0, L_0x1db4170; 1 drivers +v0x1d6d660_0 .net *"_s84", 0 0, L_0x1dbdf10; 1 drivers +v0x1d6d740_0 .net *"_s95", 0 0, L_0x1dc7be0; 1 drivers +v0x1d6d820_0 .net "carryinbus", 32 0, L_0x1eab320; 1 drivers +v0x1d6d900_0 .net "carryout", 0 0, L_0x1eac600; alias, 1 drivers +v0x1d6d9c0_0 .net "command", 2 0, v0x1d6e8a0_0; 1 drivers +v0x1d6daa0_0 .var "commandslice", 7 0; +v0x1d6db60_0 .net "mixedSigns", 0 0, L_0x1eb5fd0; 1 drivers +v0x1d6dc20_0 .net "operandA", 31 0, v0x1d6e5c0_0; 1 drivers +v0x1d6dd00_0 .net "operandB", 31 0, v0x1d6e6d0_0; 1 drivers +v0x1d6dde0_0 .net "overflow", 0 0, L_0x1eb5e20; alias, 1 drivers +v0x1d6dea0_0 .net "overrideBus", 31 0, L_0x1eb5ac0; 1 drivers +v0x1d6df60_0 .net "possibleOverflow", 0 0, L_0x1eb58a0; 1 drivers +v0x1d6e000_0 .net "result", 31 0, L_0x1eba0f0; alias, 1 drivers +v0x1d6e0f0_0 .net "resultBus", 31 0, L_0x1eaaf20; 1 drivers +v0x1d6e1c0_0 .net "sameSigns", 0 0, L_0x1ead7c0; 1 drivers +v0x1d6e260_0 .net "sltPre", 0 0, L_0x1eb6130; 1 drivers +v0x1d6e320_0 .net "zero", 0 0, L_0x1eb5590; alias, 1 drivers +v0x1d6e3f0_0 .net "zerobus", 31 0, L_0x1e026d0; 1 drivers +E_0x1b385b0 .event edge, v0x1d6d9c0_0; +L_0x1d786d0 .part v0x1d6e5c0_0, 0, 1; +L_0x1d78830 .part v0x1d6e6d0_0, 0, 1; +L_0x1d78920 .part L_0x1eab320, 0, 1; +L_0x1d82330 .part v0x1d6e5c0_0, 1, 1; +L_0x1d82490 .part v0x1d6e6d0_0, 1, 1; +L_0x1d82530 .part L_0x1eab320, 1, 1; +L_0x1d8bee0 .part v0x1d6e5c0_0, 2, 1; +L_0x1d8c0d0 .part v0x1d6e6d0_0, 2, 1; +L_0x1d8c200 .part L_0x1eab320, 2, 1; +L_0x1d95c10 .part v0x1d6e5c0_0, 3, 1; +L_0x1d95d70 .part v0x1d6e6d0_0, 3, 1; +L_0x1d95e10 .part L_0x1eab320, 3, 1; +L_0x1d9f810 .part v0x1d6e5c0_0, 4, 1; +L_0x1d9f970 .part v0x1d6e6d0_0, 4, 1; +L_0x1d9fa10 .part L_0x1eab320, 4, 1; +L_0x1daa3a0 .part v0x1d6e5c0_0, 5, 1; +L_0x1daa590 .part v0x1d6e6d0_0, 5, 1; +L_0x1daa630 .part L_0x1eab320, 5, 1; +L_0x1db40d0 .part v0x1d6e5c0_0, 6, 1; +L_0x1db4340 .part v0x1d6e6d0_0, 6, 1; +L_0x1daa6d0 .part L_0x1eab320, 6, 1; +L_0x1dbde70 .part v0x1d6e5c0_0, 7, 1; +L_0x1db44f0 .part v0x1d6e6d0_0, 7, 1; +L_0x1dbe090 .part L_0x1eab320, 7, 1; +L_0x1dc7b40 .part v0x1d6e5c0_0, 8, 1; +L_0x1dc7ca0 .part v0x1d6e6d0_0, 8, 1; +L_0x1dbe240 .part L_0x1eab320, 8, 1; +L_0x1dd1850 .part v0x1d6e5c0_0, 9, 1; +L_0x1dc7d40 .part v0x1d6e6d0_0, 9, 1; +L_0x1dd1aa0 .part L_0x1eab320, 9, 1; +L_0x1ddb470 .part v0x1d6e5c0_0, 10, 1; +L_0x1ddb5d0 .part v0x1d6e6d0_0, 10, 1; +L_0x1dd1b40 .part L_0x1eab320, 10, 1; +L_0x1de50a0 .part v0x1d6e5c0_0, 11, 1; +L_0x1ddb670 .part v0x1d6e6d0_0, 11, 1; +L_0x1de5320 .part L_0x1eab320, 11, 1; +L_0x1deecb0 .part v0x1d6e5c0_0, 12, 1; +L_0x1deee10 .part v0x1d6e6d0_0, 12, 1; +L_0x1de53c0 .part L_0x1eab320, 12, 1; +L_0x1df88f0 .part v0x1d6e5c0_0, 13, 1; +L_0x1deeeb0 .part v0x1d6e6d0_0, 13, 1; +L_0x1deef50 .part L_0x1eab320, 13, 1; +L_0x1e024d0 .part v0x1d6e5c0_0, 14, 1; +L_0x1db4230 .part v0x1d6e6d0_0, 14, 1; +L_0x1db43e0 .part L_0x1eab320, 14, 1; +L_0x1e0c2e0 .part v0x1d6e5c0_0, 15, 1; +L_0x1e02a50 .part v0x1d6e6d0_0, 15, 1; +L_0x1e02af0 .part L_0x1eab320, 15, 1; +L_0x1e16060 .part v0x1d6e5c0_0, 16, 1; +L_0x1e161c0 .part v0x1d6e6d0_0, 16, 1; +L_0x1e0c7d0 .part L_0x1eab320, 16, 1; +L_0x1e1fec0 .part v0x1d6e5c0_0, 17, 1; +L_0x1e16260 .part v0x1d6e6d0_0, 17, 1; +L_0x1e16300 .part L_0x1eab320, 17, 1; +L_0x1e29ab0 .part v0x1d6e5c0_0, 18, 1; +L_0x1e29c10 .part v0x1d6e6d0_0, 18, 1; +L_0x1e20020 .part L_0x1eab320, 18, 1; +L_0x1e33710 .part v0x1d6e5c0_0, 19, 1; +L_0x1e29cb0 .part v0x1d6e6d0_0, 19, 1; +L_0x1e29d50 .part L_0x1eab320, 19, 1; +L_0x1e3d390 .part v0x1d6e5c0_0, 20, 1; +L_0x1e3d4f0 .part v0x1d6e6d0_0, 20, 1; +L_0x1e33870 .part L_0x1eab320, 20, 1; +L_0x1da93a0 .part v0x1d6e5c0_0, 21, 1; +L_0x1da9500 .part v0x1d6e6d0_0, 21, 1; +L_0x1da95a0 .part L_0x1eab320, 21, 1; +L_0x1e52ca0 .part v0x1d6e5c0_0, 22, 1; +L_0x1e52e00 .part v0x1d6e6d0_0, 22, 1; +L_0x1e49230 .part L_0x1eab320, 22, 1; +L_0x1e5c800 .part v0x1d6e5c0_0, 23, 1; +L_0x1e52ea0 .part v0x1d6e6d0_0, 23, 1; +L_0x1e52f40 .part L_0x1eab320, 23, 1; +L_0x1e66500 .part v0x1d6e5c0_0, 24, 1; +L_0x1e66660 .part v0x1d6e6d0_0, 24, 1; +L_0x1e5c960 .part L_0x1eab320, 24, 1; +L_0x1e70190 .part v0x1d6e5c0_0, 25, 1; +L_0x1e66700 .part v0x1d6e6d0_0, 25, 1; +L_0x1e667a0 .part L_0x1eab320, 25, 1; +L_0x1e79dd0 .part v0x1d6e5c0_0, 26, 1; +L_0x1e79f30 .part v0x1d6e6d0_0, 26, 1; +L_0x1e702f0 .part L_0x1eab320, 26, 1; +L_0x1e83a40 .part v0x1d6e5c0_0, 27, 1; +L_0x1e79fd0 .part v0x1d6e6d0_0, 27, 1; +L_0x1e7a070 .part L_0x1eab320, 27, 1; +L_0x1e8d680 .part v0x1d6e5c0_0, 28, 1; +L_0x1e8d7e0 .part v0x1d6e6d0_0, 28, 1; +L_0x1e83ba0 .part L_0x1eab320, 28, 1; +L_0x1e97290 .part v0x1d6e5c0_0, 29, 1; +L_0x1e8d880 .part v0x1d6e6d0_0, 29, 1; +L_0x1e8d920 .part L_0x1eab320, 29, 1; +L_0x1ea0ee0 .part v0x1d6e5c0_0, 30, 1; +L_0x1e02630 .part v0x1d6e6d0_0, 30, 1; +L_0x1e973f0 .part L_0x1eab320, 30, 1; +LS_0x1eaaf20_0_0 .concat8 [ 1 1 1 1], L_0x1d748d0, L_0x1d7e3f0, L_0x1d88040, L_0x1d91d70; +LS_0x1eaaf20_0_4 .concat8 [ 1 1 1 1], L_0x1d9b970, L_0x1da55c0, L_0x1db0230, L_0x1db9ef0; +LS_0x1eaaf20_0_8 .concat8 [ 1 1 1 1], L_0x1dc3ca0, L_0x1dcd9b0, L_0x1dd7600, L_0x1de1200; +LS_0x1eaaf20_0_12 .concat8 [ 1 1 1 1], L_0x1deae10, L_0x1df4a50, L_0x1dfe630, L_0x1e08440; +LS_0x1eaaf20_0_16 .concat8 [ 1 1 1 1], L_0x1e121c0, L_0x1e1bfc0, L_0x1e25c10, L_0x1e2f810; +LS_0x1eaaf20_0_20 .concat8 [ 1 1 1 1], L_0x1e394c0, L_0x1e43140, L_0x1e4ed40, L_0x1e58a20; +LS_0x1eaaf20_0_24 .concat8 [ 1 1 1 1], L_0x1e62600, L_0x1e6c230, L_0x1e75f30, L_0x1e7fba0; +LS_0x1eaaf20_0_28 .concat8 [ 1 1 1 1], L_0x1e897e0, L_0x1e933f0, L_0x1e87760, L_0x1ea7080; +LS_0x1eaaf20_1_0 .concat8 [ 4 4 4 4], LS_0x1eaaf20_0_0, LS_0x1eaaf20_0_4, LS_0x1eaaf20_0_8, LS_0x1eaaf20_0_12; +LS_0x1eaaf20_1_4 .concat8 [ 4 4 4 4], LS_0x1eaaf20_0_16, LS_0x1eaaf20_0_20, LS_0x1eaaf20_0_24, LS_0x1eaaf20_0_28; +L_0x1eaaf20 .concat8 [ 16 16 0 0], LS_0x1eaaf20_1_0, LS_0x1eaaf20_1_4; +LS_0x1e026d0_0_0 .concat8 [ 1 1 1 1], L_0x1d785d0, L_0x1d821e0, L_0x1d8bde0, L_0x1d95b10; +LS_0x1e026d0_0_4 .concat8 [ 1 1 1 1], L_0x1d9f710, L_0x1daa2a0, L_0x1db3fd0, L_0x1dbdd70; +LS_0x1e026d0_0_8 .concat8 [ 1 1 1 1], L_0x1dc7a40, L_0x1dd1750, L_0x1ddb370, L_0x1de4fa0; +LS_0x1e026d0_0_12 .concat8 [ 1 1 1 1], L_0x1deebb0, L_0x1df87f0, L_0x1e023d0, L_0x1e0c1e0; +LS_0x1e026d0_0_16 .concat8 [ 1 1 1 1], L_0x1e15f60, L_0x1e1fdc0, L_0x1e299b0, L_0x1e33610; +LS_0x1e026d0_0_20 .concat8 [ 1 1 1 1], L_0x1e3d290, L_0x1da92a0, L_0x1e52ba0, L_0x1e5c700; +LS_0x1e026d0_0_24 .concat8 [ 1 1 1 1], L_0x1e66400, L_0x1e70090, L_0x1e79cd0, L_0x1e83940; +LS_0x1e026d0_0_28 .concat8 [ 1 1 1 1], L_0x1e8d580, L_0x1e97190, L_0x1ea0de0, L_0x1eaae20; +LS_0x1e026d0_1_0 .concat8 [ 4 4 4 4], LS_0x1e026d0_0_0, LS_0x1e026d0_0_4, LS_0x1e026d0_0_8, LS_0x1e026d0_0_12; +LS_0x1e026d0_1_4 .concat8 [ 4 4 4 4], LS_0x1e026d0_0_16, LS_0x1e026d0_0_20, LS_0x1e026d0_0_24, LS_0x1e026d0_0_28; +L_0x1e026d0 .concat8 [ 16 16 0 0], LS_0x1e026d0_1_0, LS_0x1e026d0_1_4; +L_0x1eabda0 .part v0x1d6e5c0_0, 31, 1; +L_0x1eab190 .part v0x1d6e6d0_0, 31, 1; +L_0x1eab230 .part L_0x1eab320, 31, 1; +LS_0x1eab320_0_0 .concat8 [ 1 1 1 1], L_0x1e0c750, L_0x1d78270, L_0x1d81e80, L_0x1d8ba80; +LS_0x1eab320_0_4 .concat8 [ 1 1 1 1], L_0x1d957b0, L_0x1d9f3b0, L_0x1da9f40, L_0x1db3c70; +LS_0x1eab320_0_8 .concat8 [ 1 1 1 1], L_0x1dbda10, L_0x1dc76e0, L_0x1dd13f0, L_0x1ddb010; +LS_0x1eab320_0_12 .concat8 [ 1 1 1 1], L_0x1de4c40, L_0x1dee850, L_0x1df8490, L_0x1e02070; +LS_0x1eab320_0_16 .concat8 [ 1 1 1 1], L_0x1e0be80, L_0x1e15c00, L_0x1e1fa60, L_0x1e29650; +LS_0x1eab320_0_20 .concat8 [ 1 1 1 1], L_0x1e332b0, L_0x1e3cf30, L_0x1da8f40, L_0x1e52840; +LS_0x1eab320_0_24 .concat8 [ 1 1 1 1], L_0x1e5c3a0, L_0x1e660a0, L_0x1e6fd30, L_0x1e79970; +LS_0x1eab320_0_28 .concat8 [ 1 1 1 1], L_0x1e835e0, L_0x1e8d220, L_0x1e96e30, L_0x1ea0a80; +LS_0x1eab320_0_32 .concat8 [ 1 0 0 0], L_0x1eaaac0; +LS_0x1eab320_1_0 .concat8 [ 4 4 4 4], LS_0x1eab320_0_0, LS_0x1eab320_0_4, LS_0x1eab320_0_8, LS_0x1eab320_0_12; +LS_0x1eab320_1_4 .concat8 [ 4 4 4 4], LS_0x1eab320_0_16, LS_0x1eab320_0_20, LS_0x1eab320_0_24, LS_0x1eab320_0_28; +LS_0x1eab320_1_8 .concat8 [ 1 0 0 0], LS_0x1eab320_0_32; +L_0x1eab320 .concat8 [ 16 16 1 0], LS_0x1eab320_1_0, LS_0x1eab320_1_4, LS_0x1eab320_1_8; +L_0x1ead720 .part v0x1d6daa0_0, 1, 1; +L_0x1eac560 .part v0x1d6daa0_0, 1, 1; +L_0x1eac670 .part L_0x1eab320, 32, 1; +L_0x1eac710 .part L_0x1eab320, 32, 1; +L_0x1eb5960 .part L_0x1eba0f0, 31, 1; +L_0x1ead880 .part v0x1d6e5c0_0, 31, 1; +L_0x1ead9e0 .part v0x1d6e6d0_0, 31, 1; +L_0x1eb61f0 .part L_0x1eab320, 32, 1; +L_0x1eb6350 .part v0x1d6daa0_0, 3, 1; +LS_0x1eb5ac0_0_0 .concat8 [ 1 1 1 1], L_0x1eb7020, L_0x1d825d0, L_0x1d8bf80, L_0x1d95f40; +LS_0x1eb5ac0_0_4 .concat8 [ 1 1 1 1], L_0x1d95cb0, L_0x1daa440, L_0x1db4170, L_0x1dbdf10; +LS_0x1eb5ac0_0_8 .concat8 [ 1 1 1 1], L_0x1dc7be0, L_0x1dd18f0, L_0x1ddb510, L_0x1de5140; +LS_0x1eb5ac0_0_12 .concat8 [ 1 1 1 1], L_0x1deed50, L_0x1df8990, L_0x1e02570, L_0x1e0c380; +LS_0x1eb5ac0_0_16 .concat8 [ 1 1 1 1], L_0x1e16100, L_0x1e1ff60, L_0x1e29b50, L_0x1e337b0; +LS_0x1eb5ac0_0_20 .concat8 [ 1 1 1 1], L_0x1e3d430, L_0x1da9440, L_0x1e52d40, L_0x1e5c8a0; +LS_0x1eb5ac0_0_24 .concat8 [ 1 1 1 1], L_0x1e665a0, L_0x1e70230, L_0x1e79e70, L_0x1e83ae0; +LS_0x1eb5ac0_0_28 .concat8 [ 1 1 1 1], L_0x1e8d720, L_0x1e97330, L_0x1ea0f80, L_0x1ea5000; +LS_0x1eb5ac0_1_0 .concat8 [ 4 4 4 4], LS_0x1eb5ac0_0_0, LS_0x1eb5ac0_0_4, LS_0x1eb5ac0_0_8, LS_0x1eb5ac0_0_12; +LS_0x1eb5ac0_1_4 .concat8 [ 4 4 4 4], LS_0x1eb5ac0_0_16, LS_0x1eb5ac0_0_20, LS_0x1eb5ac0_0_24, LS_0x1eb5ac0_0_28; +L_0x1eb5ac0 .concat8 [ 16 16 0 0], LS_0x1eb5ac0_1_0, LS_0x1eb5ac0_1_4; +S_0x1a35c10 .scope generate, "alu_slices[0]" "alu_slices[0]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1b31360 .param/l "i" 0 3 37, +C4<00>; +S_0x1a14870 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1a35c10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1d6ebf0/d .functor NOT 1, L_0x1d786d0, C4<0>, C4<0>, C4<0>; +L_0x1d6ebf0 .delay 1 (10000,10000,10000) L_0x1d6ebf0/d; +L_0x1d6ed00/d .functor NOT 1, L_0x1d78830, C4<0>, C4<0>, C4<0>; +L_0x1d6ed00 .delay 1 (10000,10000,10000) L_0x1d6ed00/d; +L_0x1d6ff90/d .functor XOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; +L_0x1d6ff90 .delay 1 (30000,30000,30000) L_0x1d6ff90/d; +L_0x7f72592da018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d706e0/d .functor OR 1, L_0x7f72592da018, L_0x7f72592da060, C4<0>, C4<0>; +L_0x1d706e0 .delay 1 (30000,30000,30000) L_0x1d706e0/d; +L_0x1d70890/d .functor AND 1, L_0x1d786d0, L_0x1d78830, C4<1>, C4<1>; +L_0x1d70890 .delay 1 (30000,30000,30000) L_0x1d70890/d; +L_0x1d70950/d .functor NAND 1, L_0x1d786d0, L_0x1d78830, C4<1>, C4<1>; +L_0x1d70950 .delay 1 (20000,20000,20000) L_0x1d70950/d; +L_0x1d70ab0/d .functor XOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; +L_0x1d70ab0 .delay 1 (20000,20000,20000) L_0x1d70ab0/d; +L_0x1d70f60/d .functor OR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; +L_0x1d70f60 .delay 1 (30000,30000,30000) L_0x1d70f60/d; +L_0x1d785d0/d .functor NOT 1, L_0x1d748d0, C4<0>, C4<0>, C4<0>; +L_0x1d785d0 .delay 1 (10000,10000,10000) L_0x1d785d0/d; +v0x18995b0_0 .net "A", 0 0, L_0x1d786d0; 1 drivers +v0x1896860_0 .net "A_", 0 0, L_0x1d6ebf0; 1 drivers +v0x1896920_0 .net "B", 0 0, L_0x1d78830; 1 drivers +v0x18a5a80_0 .net "B_", 0 0, L_0x1d6ed00; 1 drivers +v0x18a5b20_0 .net *"_s12", 0 0, L_0x1d706e0; 1 drivers +v0x18a2f10_0 .net/2s *"_s14", 0 0, L_0x7f72592da018; 1 drivers +v0x18a2fb0_0 .net/2s *"_s16", 0 0, L_0x7f72592da060; 1 drivers +v0x1878550_0 .net *"_s18", 0 0, L_0x1d70890; 1 drivers +v0x18781c0_0 .net *"_s20", 0 0, L_0x1d70950; 1 drivers +v0x1875510_0 .net *"_s22", 0 0, L_0x1d70ab0; 1 drivers +v0x18755d0_0 .net *"_s24", 0 0, L_0x1d70f60; 1 drivers +o0x7f7259356328 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1881bc0_0 name=_s30 +o0x7f7259356358 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1857180_0 name=_s32 +v0x1856df0_0 .net *"_s8", 0 0, L_0x1d6ff90; 1 drivers +v0x1854140_0 .net "carryin", 0 0, L_0x1d78920; 1 drivers +v0x18541e0_0 .net "carryout", 0 0, L_0x1d78270; 1 drivers +v0x1863830_0 .net "carryouts", 7 0, L_0x1ebddc0; 1 drivers +v0x18638d0_0 .net "command", 7 0, v0x1d6daa0_0; 1 drivers +v0x18607f0_0 .net "result", 0 0, L_0x1d748d0; 1 drivers +v0x1860890_0 .net "results", 7 0, L_0x1d70d30; 1 drivers +v0x1835e00_0 .net "zero", 0 0, L_0x1d785d0; 1 drivers +LS_0x1d70d30_0_0 .concat8 [ 1 1 1 1], L_0x1d6f240, L_0x1d6fa20, L_0x1d6ff90, L_0x1d706e0; +LS_0x1d70d30_0_4 .concat8 [ 1 1 1 1], L_0x1d70890, L_0x1d70950, L_0x1d70ab0, L_0x1d70f60; +L_0x1d70d30 .concat8 [ 4 4 0 0], LS_0x1d70d30_0_0, LS_0x1d70d30_0_4; +LS_0x1ebddc0_0_0 .concat [ 1 1 1 1], L_0x1d6f5b0, L_0x1d6fe30, o0x7f7259356328, L_0x1d70530; +LS_0x1ebddc0_0_4 .concat [ 4 0 0 0], o0x7f7259356358; +L_0x1ebddc0 .concat [ 4 4 0 0], LS_0x1ebddc0_0_0, LS_0x1ebddc0_0_4; +S_0x19f34d0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1a14870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d6f5b0/d .functor OR 1, L_0x1d6eff0, L_0x1d6f420, C4<0>, C4<0>; +L_0x1d6f5b0 .delay 1 (30000,30000,30000) L_0x1d6f5b0/d; +v0x1b34410_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers +v0x1b344d0_0 .net "b", 0 0, L_0x1d78830; alias, 1 drivers +v0x1b30b00_0 .net "c1", 0 0, L_0x1d6eff0; 1 drivers +v0x1b306c0_0 .net "c2", 0 0, L_0x1d6f420; 1 drivers +v0x1b2d9d0_0 .net "carryin", 0 0, L_0x1d78920; alias, 1 drivers +v0x1b237b0_0 .net "carryout", 0 0, L_0x1d6f5b0; 1 drivers +v0x1b23850_0 .net "s1", 0 0, L_0x1d6eef0; 1 drivers +v0x1b26230_0 .net "sum", 0 0, L_0x1d6f240; 1 drivers +S_0x19d2120 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x19f34d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d6eef0/d .functor XOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; +L_0x1d6eef0 .delay 1 (30000,30000,30000) L_0x1d6eef0/d; +L_0x1d6eff0/d .functor AND 1, L_0x1d786d0, L_0x1d78830, C4<1>, C4<1>; +L_0x1d6eff0 .delay 1 (30000,30000,30000) L_0x1d6eff0/d; +v0x1473f50_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers +v0x1b39690_0 .net "b", 0 0, L_0x1d78830; alias, 1 drivers +v0x1b392a0_0 .net "carryout", 0 0, L_0x1d6eff0; alias, 1 drivers +v0x1b38620_0 .net "sum", 0 0, L_0x1d6eef0; alias, 1 drivers +S_0x19b0d90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x19f34d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d6f240/d .functor XOR 1, L_0x1d6eef0, L_0x1d78920, C4<0>, C4<0>; +L_0x1d6f240 .delay 1 (30000,30000,30000) L_0x1d6f240/d; +L_0x1d6f420/d .functor AND 1, L_0x1d6eef0, L_0x1d78920, C4<1>, C4<1>; +L_0x1d6f420 .delay 1 (30000,30000,30000) L_0x1d6f420/d; +v0x1b38300_0 .net "a", 0 0, L_0x1d6eef0; alias, 1 drivers +v0x1b37610_0 .net "b", 0 0, L_0x1d78920; alias, 1 drivers +v0x1b376b0_0 .net "carryout", 0 0, L_0x1d6f420; alias, 1 drivers +v0x1b37280_0 .net "sum", 0 0, L_0x1d6f240; alias, 1 drivers +S_0x198f9e0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1a14870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1a556f0_0 .net "ands", 7 0, L_0x1d76310; 1 drivers +v0x1a17c20_0 .net "in", 7 0, L_0x1ebddc0; alias, 1 drivers +v0x1a17ce0_0 .net "out", 0 0, L_0x1d78270; alias, 1 drivers +v0x1a1a590_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b01920 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x198f9e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1ac08f0_0 .net "A", 7 0, L_0x1ebddc0; alias, 1 drivers +v0x1ace200_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1acdd60_0 .net *"_s0", 0 0, L_0x1d74c30; 1 drivers +v0x1acde00_0 .net *"_s12", 0 0, L_0x1d755a0; 1 drivers +v0x1acb090_0 .net *"_s16", 0 0, L_0x1d75900; 1 drivers +v0x1adab00_0 .net *"_s20", 0 0, L_0x1d75c10; 1 drivers +v0x1ada770_0 .net *"_s24", 0 0, L_0x1d76000; 1 drivers +v0x1ad7ac0_0 .net *"_s28", 0 0, L_0x1d75f90; 1 drivers +v0x1a9caf0_0 .net *"_s4", 0 0, L_0x1d74f40; 1 drivers +v0x1a9f460_0 .net *"_s8", 0 0, L_0x1d75290; 1 drivers +v0x1aacd90_0 .net "out", 7 0, L_0x1d76310; alias, 1 drivers +L_0x1d74cf0 .part L_0x1ebddc0, 0, 1; +L_0x1d74e50 .part v0x1d6daa0_0, 0, 1; +L_0x1d75000 .part L_0x1ebddc0, 1, 1; +L_0x1d751f0 .part v0x1d6daa0_0, 1, 1; +L_0x1d75350 .part L_0x1ebddc0, 2, 1; +L_0x1d754b0 .part v0x1d6daa0_0, 2, 1; +L_0x1d75660 .part L_0x1ebddc0, 3, 1; +L_0x1d757c0 .part v0x1d6daa0_0, 3, 1; +L_0x1d759c0 .part L_0x1ebddc0, 4, 1; +L_0x1d75b20 .part v0x1d6daa0_0, 4, 1; +L_0x1d75c80 .part L_0x1ebddc0, 5, 1; +L_0x1d75ef0 .part v0x1d6daa0_0, 5, 1; +L_0x1d760c0 .part L_0x1ebddc0, 6, 1; +L_0x1d76220 .part v0x1d6daa0_0, 6, 1; +LS_0x1d76310_0_0 .concat8 [ 1 1 1 1], L_0x1d74c30, L_0x1d74f40, L_0x1d75290, L_0x1d755a0; +LS_0x1d76310_0_4 .concat8 [ 1 1 1 1], L_0x1d75900, L_0x1d75c10, L_0x1d76000, L_0x1d75f90; +L_0x1d76310 .concat8 [ 4 4 0 0], LS_0x1d76310_0_0, LS_0x1d76310_0_4; +L_0x1d766d0 .part L_0x1ebddc0, 7, 1; +L_0x1d768c0 .part v0x1d6daa0_0, 7, 1; +S_0x1b00380 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1b22cb0 .param/l "i" 0 4 54, +C4<00>; +L_0x1d74c30/d .functor AND 1, L_0x1d74cf0, L_0x1d74e50, C4<1>, C4<1>; +L_0x1d74c30 .delay 1 (30000,30000,30000) L_0x1d74c30/d; +v0x1b228d0_0 .net *"_s0", 0 0, L_0x1d74cf0; 1 drivers +v0x1b10a40_0 .net *"_s1", 0 0, L_0x1d74e50; 1 drivers +S_0x1ae0520 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1b10600 .param/l "i" 0 4 54, +C4<01>; +L_0x1d74f40/d .functor AND 1, L_0x1d75000, L_0x1d751f0, C4<1>, C4<1>; +L_0x1d74f40 .delay 1 (30000,30000,30000) L_0x1d74f40/d; +v0x1b106a0_0 .net *"_s0", 0 0, L_0x1d75000; 1 drivers +v0x1b0d930_0 .net *"_s1", 0 0, L_0x1d751f0; 1 drivers +S_0x1adef80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1b1d3f0 .param/l "i" 0 4 54, +C4<010>; +L_0x1d75290/d .functor AND 1, L_0x1d75350, L_0x1d754b0, C4<1>, C4<1>; +L_0x1d75290 .delay 1 (30000,30000,30000) L_0x1d75290/d; +v0x1b1cff0_0 .net *"_s0", 0 0, L_0x1d75350; 1 drivers +v0x1b1a340_0 .net *"_s1", 0 0, L_0x1d754b0; 1 drivers +S_0x1abf120 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1b1d0d0 .param/l "i" 0 4 54, +C4<011>; +L_0x1d755a0/d .functor AND 1, L_0x1d75660, L_0x1d757c0, C4<1>, C4<1>; +L_0x1d755a0 .delay 1 (30000,30000,30000) L_0x1d755a0/d; +v0x1ae08a0_0 .net *"_s0", 0 0, L_0x1d75660; 1 drivers +v0x1adf2c0_0 .net *"_s1", 0 0, L_0x1d757c0; 1 drivers +S_0x1abdb80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1ae1c80 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d75900/d .functor AND 1, L_0x1d759c0, L_0x1d75b20, C4<1>, C4<1>; +L_0x1d75900 .delay 1 (30000,30000,30000) L_0x1d75900/d; +v0x1aef5e0_0 .net *"_s0", 0 0, L_0x1d759c0; 1 drivers +v0x1aef1a0_0 .net *"_s1", 0 0, L_0x1d75b20; 1 drivers +S_0x1a9dd50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1aef6c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d75c10/d .functor AND 1, L_0x1d75c80, L_0x1d75ef0, C4<1>, C4<1>; +L_0x1d75c10 .delay 1 (30000,30000,30000) L_0x1d75c10/d; +v0x1aec520_0 .net *"_s0", 0 0, L_0x1d75c80; 1 drivers +v0x1afbf00_0 .net *"_s1", 0 0, L_0x1d75ef0; 1 drivers +S_0x1a9c7b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1afbb70 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d76000/d .functor AND 1, L_0x1d760c0, L_0x1d76220, C4<1>, C4<1>; +L_0x1d76000 .delay 1 (30000,30000,30000) L_0x1d76000/d; +v0x1afbc30_0 .net *"_s0", 0 0, L_0x1d760c0; 1 drivers +v0x1af8ec0_0 .net *"_s1", 0 0, L_0x1d76220; 1 drivers +S_0x1a7c9d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b01920; + .timescale -9 -12; +P_0x1abdec0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d75f90/d .functor AND 1, L_0x1d766d0, L_0x1d768c0, C4<1>, C4<1>; +L_0x1d75f90 .delay 1 (30000,30000,30000) L_0x1d75f90/d; +v0x1abdf60_0 .net *"_s0", 0 0, L_0x1d766d0; 1 drivers +v0x1ac0830_0 .net *"_s1", 0 0, L_0x1d768c0; 1 drivers +S_0x1a7b430 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x198f9e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d78270/d .functor OR 1, L_0x1d78330, L_0x1d784e0, C4<0>, C4<0>; +L_0x1d78270 .delay 1 (30000,30000,30000) L_0x1d78270/d; +v0x1a39050_0 .net *"_s10", 0 0, L_0x1d78330; 1 drivers +v0x1a3b9c0_0 .net *"_s12", 0 0, L_0x1d784e0; 1 drivers +v0x1a48e40_0 .net "in", 7 0, L_0x1d76310; alias, 1 drivers +v0x1a55b30_0 .net "ors", 1 0, L_0x1d78090; 1 drivers +v0x1a55bf0_0 .net "out", 0 0, L_0x1d78270; alias, 1 drivers +L_0x1d77500 .part L_0x1d76310, 0, 4; +L_0x1d78090 .concat8 [ 1 1 0 0], L_0x1d771f0, L_0x1d77e20; +L_0x1d781d0 .part L_0x1d76310, 4, 4; +L_0x1d78330 .part L_0x1d78090, 0, 1; +L_0x1d784e0 .part L_0x1d78090, 1, 1; +S_0x1a5b630 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1a7b430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d769b0/d .functor OR 1, L_0x1d76a70, L_0x1d76bd0, C4<0>, C4<0>; +L_0x1d769b0 .delay 1 (30000,30000,30000) L_0x1d769b0/d; +L_0x1d76e00/d .functor OR 1, L_0x1d76f10, L_0x1d77070, C4<0>, C4<0>; +L_0x1d76e00 .delay 1 (30000,30000,30000) L_0x1d76e00/d; +L_0x1d771f0/d .functor OR 1, L_0x1d77260, L_0x1d77410, C4<0>, C4<0>; +L_0x1d771f0 .delay 1 (30000,30000,30000) L_0x1d771f0/d; +v0x1aac950_0 .net *"_s0", 0 0, L_0x1d769b0; 1 drivers +v0x1aa9c60_0 .net *"_s10", 0 0, L_0x1d76f10; 1 drivers +v0x1ab9700_0 .net *"_s12", 0 0, L_0x1d77070; 1 drivers +v0x1ab97c0_0 .net *"_s14", 0 0, L_0x1d77260; 1 drivers +v0x1ab9370_0 .net *"_s16", 0 0, L_0x1d77410; 1 drivers +v0x1ab6540_0 .net *"_s3", 0 0, L_0x1d76a70; 1 drivers +v0x1a7b770_0 .net *"_s5", 0 0, L_0x1d76bd0; 1 drivers +v0x1a7e0e0_0 .net *"_s6", 0 0, L_0x1d76e00; 1 drivers +v0x1a8b9c0_0 .net "in", 3 0, L_0x1d77500; 1 drivers +v0x1a8b580_0 .net "ors", 1 0, L_0x1d76d10; 1 drivers +v0x1a88890_0 .net "out", 0 0, L_0x1d771f0; 1 drivers +L_0x1d76a70 .part L_0x1d77500, 0, 1; +L_0x1d76bd0 .part L_0x1d77500, 1, 1; +L_0x1d76d10 .concat8 [ 1 1 0 0], L_0x1d769b0, L_0x1d76e00; +L_0x1d76f10 .part L_0x1d77500, 2, 1; +L_0x1d77070 .part L_0x1d77500, 3, 1; +L_0x1d77260 .part L_0x1d76d10, 0, 1; +L_0x1d77410 .part L_0x1d76d10, 1, 1; +S_0x1a5a090 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1a7b430; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d77630/d .functor OR 1, L_0x1d776a0, L_0x1d77800, C4<0>, C4<0>; +L_0x1d77630 .delay 1 (30000,30000,30000) L_0x1d77630/d; +L_0x1d77a30/d .functor OR 1, L_0x1d77b40, L_0x1d77ca0, C4<0>, C4<0>; +L_0x1d77a30 .delay 1 (30000,30000,30000) L_0x1d77a30/d; +L_0x1d77e20/d .functor OR 1, L_0x1d77e90, L_0x1d77ff0, C4<0>, C4<0>; +L_0x1d77e20 .delay 1 (30000,30000,30000) L_0x1d77e20/d; +v0x1a98330_0 .net *"_s0", 0 0, L_0x1d77630; 1 drivers +v0x1a97fa0_0 .net *"_s10", 0 0, L_0x1d77b40; 1 drivers +v0x1a95170_0 .net *"_s12", 0 0, L_0x1d77ca0; 1 drivers +v0x1a95230_0 .net *"_s14", 0 0, L_0x1d77e90; 1 drivers +v0x1a5a3d0_0 .net *"_s16", 0 0, L_0x1d77ff0; 1 drivers +v0x1a5cd40_0 .net *"_s3", 0 0, L_0x1d776a0; 1 drivers +v0x1a6a600_0 .net *"_s5", 0 0, L_0x1d77800; 1 drivers +v0x1a6a1c0_0 .net *"_s6", 0 0, L_0x1d77a30; 1 drivers +v0x1a76ee0_0 .net "in", 3 0, L_0x1d781d0; 1 drivers +v0x1a76aa0_0 .net "ors", 1 0, L_0x1d77940; 1 drivers +v0x1a73db0_0 .net "out", 0 0, L_0x1d77e20; 1 drivers +L_0x1d776a0 .part L_0x1d781d0, 0, 1; +L_0x1d77800 .part L_0x1d781d0, 1, 1; +L_0x1d77940 .concat8 [ 1 1 0 0], L_0x1d77630, L_0x1d77a30; +L_0x1d77b40 .part L_0x1d781d0, 2, 1; +L_0x1d77ca0 .part L_0x1d781d0, 3, 1; +L_0x1d77e90 .part L_0x1d77940, 0, 1; +L_0x1d77ff0 .part L_0x1d77940, 1, 1; +S_0x1a3a2b0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1a14870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x191b590_0 .net "ands", 7 0, L_0x1d728d0; 1 drivers +v0x192ac40_0 .net "in", 7 0, L_0x1d70d30; alias, 1 drivers +v0x192ad00_0 .net "out", 0 0, L_0x1d748d0; alias, 1 drivers +v0x192a800_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1a38d10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1a3a2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x19f1c20_0 .net "A", 7 0, L_0x1d70d30; alias, 1 drivers +v0x19eef30_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x19c4530_0 .net *"_s0", 0 0, L_0x1d710c0; 1 drivers +v0x19c45f0_0 .net *"_s12", 0 0, L_0x1d71a80; 1 drivers +v0x19c41a0_0 .net *"_s16", 0 0, L_0x1d71de0; 1 drivers +v0x19c14f0_0 .net *"_s20", 0 0, L_0x1d72210; 1 drivers +v0x19d0cb0_0 .net *"_s24", 0 0, L_0x1d72540; 1 drivers +v0x19d0870_0 .net *"_s28", 0 0, L_0x1d724d0; 1 drivers +v0x19cdb80_0 .net *"_s4", 0 0, L_0x1d71460; 1 drivers +v0x19a31b0_0 .net *"_s8", 0 0, L_0x1d71770; 1 drivers +v0x19a2e20_0 .net "out", 7 0, L_0x1d728d0; alias, 1 drivers +L_0x1d711d0 .part L_0x1d70d30, 0, 1; +L_0x1d713c0 .part v0x1d6daa0_0, 0, 1; +L_0x1d71520 .part L_0x1d70d30, 1, 1; +L_0x1d71680 .part v0x1d6daa0_0, 1, 1; +L_0x1d71830 .part L_0x1d70d30, 2, 1; +L_0x1d71990 .part v0x1d6daa0_0, 2, 1; +L_0x1d71b40 .part L_0x1d70d30, 3, 1; +L_0x1d71ca0 .part v0x1d6daa0_0, 3, 1; +L_0x1d71ea0 .part L_0x1d70d30, 4, 1; +L_0x1d72110 .part v0x1d6daa0_0, 4, 1; +L_0x1d72280 .part L_0x1d70d30, 5, 1; +L_0x1d723e0 .part v0x1d6daa0_0, 5, 1; +L_0x1d72600 .part L_0x1d70d30, 6, 1; +L_0x1d72760 .part v0x1d6daa0_0, 6, 1; +LS_0x1d728d0_0_0 .concat8 [ 1 1 1 1], L_0x1d710c0, L_0x1d71460, L_0x1d71770, L_0x1d71a80; +LS_0x1d728d0_0_4 .concat8 [ 1 1 1 1], L_0x1d71de0, L_0x1d72210, L_0x1d72540, L_0x1d724d0; +L_0x1d728d0 .concat8 [ 4 4 0 0], LS_0x1d728d0_0_0, LS_0x1d728d0_0_4; +L_0x1d72c90 .part L_0x1d70d30, 7, 1; +L_0x1d72e80 .part v0x1d6daa0_0, 7, 1; +S_0x1a18e80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x1a7b850 .param/l "i" 0 4 54, +C4<00>; +L_0x1d710c0/d .functor AND 1, L_0x1d711d0, L_0x1d713c0, C4<1>, C4<1>; +L_0x1d710c0 .delay 1 (30000,30000,30000) L_0x1d710c0/d; +v0x1a27ab0_0 .net *"_s0", 0 0, L_0x1d711d0; 1 drivers +v0x1a24f40_0 .net *"_s1", 0 0, L_0x1d713c0; 1 drivers +S_0x1a178e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x1a8b660 .param/l "i" 0 4 54, +C4<01>; +L_0x1d71460/d .functor AND 1, L_0x1d71520, L_0x1d71680, C4<1>, C4<1>; +L_0x1d71460 .delay 1 (30000,30000,30000) L_0x1d71460/d; +v0x1a347a0_0 .net *"_s0", 0 0, L_0x1d71520; 1 drivers +v0x1a34360_0 .net *"_s1", 0 0, L_0x1d71680; 1 drivers +S_0x19f7ae0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x1a34460 .param/l "i" 0 4 54, +C4<010>; +L_0x1d71770/d .functor AND 1, L_0x1d71830, L_0x1d71990, C4<1>, C4<1>; +L_0x1d71770 .delay 1 (30000,30000,30000) L_0x1d71770/d; +v0x19f6880_0 .net *"_s0", 0 0, L_0x1d71830; 1 drivers +v0x19f6940_0 .net *"_s1", 0 0, L_0x1d71990; 1 drivers +S_0x19f6540 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x1a76b80 .param/l "i" 0 4 54, +C4<011>; +L_0x1d71a80/d .functor AND 1, L_0x1d71b40, L_0x1d71ca0, C4<1>, C4<1>; +L_0x1d71a80 .delay 1 (30000,30000,30000) L_0x1d71a80/d; +v0x19f91f0_0 .net *"_s0", 0 0, L_0x1d71b40; 1 drivers +v0x1a03ba0_0 .net *"_s1", 0 0, L_0x1d71ca0; 1 drivers +S_0x1a06ae0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x19f92d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d71de0/d .functor AND 1, L_0x1d71ea0, L_0x1d72110, C4<1>, C4<1>; +L_0x1d71de0 .delay 1 (30000,30000,30000) L_0x1d71de0/d; +v0x1a13400_0 .net *"_s0", 0 0, L_0x1d71ea0; 1 drivers +v0x1a12fc0_0 .net *"_s1", 0 0, L_0x1d72110; 1 drivers +S_0x1884ab0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x1a134e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d72210/d .functor AND 1, L_0x1d72280, L_0x1d723e0, C4<1>, C4<1>; +L_0x1d72210 .delay 1 (30000,30000,30000) L_0x1d72210/d; +v0x19d67b0_0 .net *"_s0", 0 0, L_0x1d72280; 1 drivers +v0x19d7ea0_0 .net *"_s1", 0 0, L_0x1d723e0; 1 drivers +S_0x17e3240 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x19e5840 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d72540/d .functor AND 1, L_0x1d72600, L_0x1d72760, C4<1>, C4<1>; +L_0x1d72540 .delay 1 (30000,30000,30000) L_0x1d72540/d; +v0x19e5900_0 .net *"_s0", 0 0, L_0x1d72600; 1 drivers +v0x19e54b0_0 .net *"_s1", 0 0, L_0x1d72760; 1 drivers +S_0x17e2f20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1a38d10; + .timescale -9 -12; +P_0x19e2800 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d724d0/d .functor AND 1, L_0x1d72c90, L_0x1d72e80, C4<1>, C4<1>; +L_0x1d724d0 .delay 1 (30000,30000,30000) L_0x1d724d0/d; +v0x19e28a0_0 .net *"_s0", 0 0, L_0x1d72c90; 1 drivers +v0x19f2080_0 .net *"_s1", 0 0, L_0x1d72e80; 1 drivers +S_0x17c3110 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1a3a2b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d748d0/d .functor OR 1, L_0x1d74990, L_0x1d74b40, C4<0>, C4<0>; +L_0x1d748d0 .delay 1 (30000,30000,30000) L_0x1d748d0/d; +v0x194baf0_0 .net *"_s10", 0 0, L_0x1d74990; 1 drivers +v0x1948e00_0 .net *"_s12", 0 0, L_0x1d74b40; 1 drivers +v0x191e5d0_0 .net "in", 7 0, L_0x1d728d0; alias, 1 drivers +v0x191e670_0 .net "ors", 1 0, L_0x1d746f0; 1 drivers +v0x191e240_0 .net "out", 0 0, L_0x1d748d0; alias, 1 drivers +L_0x1d73ac0 .part L_0x1d728d0, 0, 4; +L_0x1d746f0 .concat8 [ 1 1 0 0], L_0x1d737b0, L_0x1d743e0; +L_0x1d74830 .part L_0x1d728d0, 4, 4; +L_0x1d74990 .part L_0x1d746f0, 0, 1; +L_0x1d74b40 .part L_0x1d746f0, 1, 1; +S_0x17c1b70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x17c3110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d72f70/d .functor OR 1, L_0x1d73030, L_0x1d73190, C4<0>, C4<0>; +L_0x1d72f70 .delay 1 (30000,30000,30000) L_0x1d72f70/d; +L_0x1d733c0/d .functor OR 1, L_0x1d734d0, L_0x1d73630, C4<0>, C4<0>; +L_0x1d733c0 .delay 1 (30000,30000,30000) L_0x1d733c0/d; +L_0x1d737b0/d .functor OR 1, L_0x1d73820, L_0x1d739d0, C4<0>, C4<0>; +L_0x1d737b0 .delay 1 (30000,30000,30000) L_0x1d737b0/d; +v0x19a0170_0 .net *"_s0", 0 0, L_0x1d72f70; 1 drivers +v0x19af920_0 .net *"_s10", 0 0, L_0x1d734d0; 1 drivers +v0x19af4e0_0 .net *"_s12", 0 0, L_0x1d73630; 1 drivers +v0x19af5a0_0 .net *"_s14", 0 0, L_0x1d73820; 1 drivers +v0x19ac7f0_0 .net *"_s16", 0 0, L_0x1d739d0; 1 drivers +v0x1981e80_0 .net *"_s3", 0 0, L_0x1d73030; 1 drivers +v0x1981af0_0 .net *"_s5", 0 0, L_0x1d73190; 1 drivers +v0x197ee40_0 .net *"_s6", 0 0, L_0x1d733c0; 1 drivers +v0x198e570_0 .net "in", 3 0, L_0x1d73ac0; 1 drivers +v0x198e130_0 .net "ors", 1 0, L_0x1d732d0; 1 drivers +v0x198b440_0 .net "out", 0 0, L_0x1d737b0; 1 drivers +L_0x1d73030 .part L_0x1d73ac0, 0, 1; +L_0x1d73190 .part L_0x1d73ac0, 1, 1; +L_0x1d732d0 .concat8 [ 1 1 0 0], L_0x1d72f70, L_0x1d733c0; +L_0x1d734d0 .part L_0x1d73ac0, 2, 1; +L_0x1d73630 .part L_0x1d73ac0, 3, 1; +L_0x1d73820 .part L_0x1d732d0, 0, 1; +L_0x1d739d0 .part L_0x1d732d0, 1, 1; +S_0x17a1d30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x17c3110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d73bf0/d .functor OR 1, L_0x1d73c60, L_0x1d73dc0, C4<0>, C4<0>; +L_0x1d73bf0 .delay 1 (30000,30000,30000) L_0x1d73bf0/d; +L_0x1d73ff0/d .functor OR 1, L_0x1d74100, L_0x1d74260, C4<0>, C4<0>; +L_0x1d73ff0 .delay 1 (30000,30000,30000) L_0x1d73ff0/d; +L_0x1d743e0/d .functor OR 1, L_0x1d74450, L_0x1d74600, C4<0>, C4<0>; +L_0x1d743e0 .delay 1 (30000,30000,30000) L_0x1d743e0/d; +v0x1960b40_0 .net *"_s0", 0 0, L_0x1d73bf0; 1 drivers +v0x19607b0_0 .net *"_s10", 0 0, L_0x1d74100; 1 drivers +v0x195db00_0 .net *"_s12", 0 0, L_0x1d74260; 1 drivers +v0x195dbc0_0 .net *"_s14", 0 0, L_0x1d74450; 1 drivers +v0x196d240_0 .net *"_s16", 0 0, L_0x1d74600; 1 drivers +v0x196ce00_0 .net *"_s3", 0 0, L_0x1d73c60; 1 drivers +v0x196a110_0 .net *"_s5", 0 0, L_0x1d73dc0; 1 drivers +v0x193f850_0 .net *"_s6", 0 0, L_0x1d73ff0; 1 drivers +v0x193f4c0_0 .net "in", 3 0, L_0x1d74830; 1 drivers +v0x193c810_0 .net "ors", 1 0, L_0x1d73f00; 1 drivers +v0x194bf30_0 .net "out", 0 0, L_0x1d743e0; 1 drivers +L_0x1d73c60 .part L_0x1d74830, 0, 1; +L_0x1d73dc0 .part L_0x1d74830, 1, 1; +L_0x1d73f00 .concat8 [ 1 1 0 0], L_0x1d73bf0, L_0x1d73ff0; +L_0x1d74100 .part L_0x1d74830, 2, 1; +L_0x1d74260 .part L_0x1d74830, 3, 1; +L_0x1d74450 .part L_0x1d73f00, 0, 1; +L_0x1d74600 .part L_0x1d73f00, 1, 1; +S_0x17a0790 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1a14870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1d700f0/d .functor XNOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; +L_0x1d700f0 .delay 1 (20000,20000,20000) L_0x1d700f0/d; +L_0x1d70360/d .functor AND 1, L_0x1d786d0, L_0x1d6ed00, C4<1>, C4<1>; +L_0x1d70360 .delay 1 (30000,30000,30000) L_0x1d70360/d; +L_0x1d703d0/d .functor AND 1, L_0x1d700f0, L_0x1d78920, C4<1>, C4<1>; +L_0x1d703d0 .delay 1 (30000,30000,30000) L_0x1d703d0/d; +L_0x1d70530/d .functor OR 1, L_0x1d703d0, L_0x1d70360, C4<0>, C4<0>; +L_0x1d70530 .delay 1 (30000,30000,30000) L_0x1d70530/d; +v0x18fd380_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers +v0x18fcf50_0 .net "a_", 0 0, L_0x1d6ebf0; alias, 1 drivers +v0x18fcff0_0 .net "b", 0 0, L_0x1d78830; alias, 1 drivers +v0x18fa2a0_0 .net "b_", 0 0, L_0x1d6ed00; alias, 1 drivers +v0x18fa340_0 .net "carryin", 0 0, L_0x1d78920; alias, 1 drivers +v0x1909960_0 .net "eq", 0 0, L_0x1d700f0; 1 drivers +v0x1909a00_0 .net "lt", 0 0, L_0x1d70360; 1 drivers +v0x1909520_0 .net "out", 0 0, L_0x1d70530; 1 drivers +v0x19095c0_0 .net "w0", 0 0, L_0x1d703d0; 1 drivers +S_0x17808d0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1a14870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d6fe30/d .functor OR 1, L_0x1d6f870, L_0x1d6fd20, C4<0>, C4<0>; +L_0x1d6fe30 .delay 1 (30000,30000,30000) L_0x1d6fe30/d; +v0x18bac40_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers +v0x18ba8b0_0 .net "b", 0 0, L_0x1d6ed00; alias, 1 drivers +v0x18ba970_0 .net "c1", 0 0, L_0x1d6f870; 1 drivers +v0x18b7c00_0 .net "c2", 0 0, L_0x1d6fd20; 1 drivers +v0x18c42b0_0 .net "carryin", 0 0, L_0x1d78920; alias, 1 drivers +v0x18998a0_0 .net "carryout", 0 0, L_0x1d6fe30; 1 drivers +v0x1899940_0 .net "s1", 0 0, L_0x1d6f710; 1 drivers +v0x1899510_0 .net "sum", 0 0, L_0x1d6fa20; 1 drivers +S_0x177f330 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x17808d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d6f710/d .functor XOR 1, L_0x1d786d0, L_0x1d6ed00, C4<0>, C4<0>; +L_0x1d6f710 .delay 1 (30000,30000,30000) L_0x1d6f710/d; +L_0x1d6f870/d .functor AND 1, L_0x1d786d0, L_0x1d6ed00, C4<1>, C4<1>; +L_0x1d6f870 .delay 1 (30000,30000,30000) L_0x1d6f870/d; +v0x18dbfa0_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers +v0x18dc060_0 .net "b", 0 0, L_0x1d6ed00; alias, 1 drivers +v0x18dbc10_0 .net "carryout", 0 0, L_0x1d6f870; alias, 1 drivers +v0x18dbcb0_0 .net "sum", 0 0, L_0x1d6f710; alias, 1 drivers +S_0x175f440 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x17808d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d6fa20/d .functor XOR 1, L_0x1d6f710, L_0x1d78920, C4<0>, C4<0>; +L_0x1d6fa20 .delay 1 (30000,30000,30000) L_0x1d6fa20/d; +L_0x1d6fd20/d .functor AND 1, L_0x1d6f710, L_0x1d78920, C4<1>, C4<1>; +L_0x1d6fd20 .delay 1 (30000,30000,30000) L_0x1d6fd20/d; +v0x18d8f60_0 .net "a", 0 0, L_0x1d6f710; alias, 1 drivers +v0x18d9020_0 .net "b", 0 0, L_0x1d78920; alias, 1 drivers +v0x18e81b0_0 .net "carryout", 0 0, L_0x1d6fd20; alias, 1 drivers +v0x18e8250_0 .net "sum", 0 0, L_0x1d6fa20; alias, 1 drivers +S_0x175dea0 .scope generate, "alu_slices[1]" "alu_slices[1]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1948ee0 .param/l "i" 0 3 37, +C4<01>; +S_0x173dee0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x175dea0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1d789c0/d .functor NOT 1, L_0x1d82330, C4<0>, C4<0>, C4<0>; +L_0x1d789c0 .delay 1 (10000,10000,10000) L_0x1d789c0/d; +L_0x1d78ad0/d .functor NOT 1, L_0x1d82490, C4<0>, C4<0>, C4<0>; +L_0x1d78ad0 .delay 1 (10000,10000,10000) L_0x1d78ad0/d; +L_0x1d79b00/d .functor XOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; +L_0x1d79b00 .delay 1 (30000,30000,30000) L_0x1d79b00/d; +L_0x7f72592da0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d7a1b0/d .functor OR 1, L_0x7f72592da0a8, L_0x7f72592da0f0, C4<0>, C4<0>; +L_0x1d7a1b0 .delay 1 (30000,30000,30000) L_0x1d7a1b0/d; +L_0x1d7a3b0/d .functor AND 1, L_0x1d82330, L_0x1d82490, C4<1>, C4<1>; +L_0x1d7a3b0 .delay 1 (30000,30000,30000) L_0x1d7a3b0/d; +L_0x1d7a470/d .functor NAND 1, L_0x1d82330, L_0x1d82490, C4<1>, C4<1>; +L_0x1d7a470 .delay 1 (20000,20000,20000) L_0x1d7a470/d; +L_0x1d7a5d0/d .functor XOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; +L_0x1d7a5d0 .delay 1 (20000,20000,20000) L_0x1d7a5d0/d; +L_0x1d7aa80/d .functor OR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; +L_0x1d7aa80 .delay 1 (30000,30000,30000) L_0x1d7aa80/d; +L_0x1d821e0/d .functor NOT 1, L_0x1d7e3f0, C4<0>, C4<0>, C4<0>; +L_0x1d821e0 .delay 1 (10000,10000,10000) L_0x1d821e0/d; +v0x19ef450_0 .net "A", 0 0, L_0x1d82330; 1 drivers +v0x19ef510_0 .net "A_", 0 0, L_0x1d789c0; 1 drivers +v0x19ce0a0_0 .net "B", 0 0, L_0x1d82490; 1 drivers +v0x19ce170_0 .net "B_", 0 0, L_0x1d78ad0; 1 drivers +v0x19acd10_0 .net *"_s12", 0 0, L_0x1d7a1b0; 1 drivers +v0x19ace00_0 .net/2s *"_s14", 0 0, L_0x7f72592da0a8; 1 drivers +v0x198b960_0 .net/2s *"_s16", 0 0, L_0x7f72592da0f0; 1 drivers +v0x198ba20_0 .net *"_s18", 0 0, L_0x1d7a3b0; 1 drivers +v0x196a630_0 .net *"_s20", 0 0, L_0x1d7a470; 1 drivers +v0x1949320_0 .net *"_s22", 0 0, L_0x1d7a5d0; 1 drivers +v0x1949400_0 .net *"_s24", 0 0, L_0x1d7aa80; 1 drivers +o0x7f7259358818 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1928030_0 name=_s30 +o0x7f7259358848 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1928110_0 name=_s32 +v0x1906d50_0 .net *"_s8", 0 0, L_0x1d79b00; 1 drivers +v0x1906e10_0 .net "carryin", 0 0, L_0x1d82530; 1 drivers +v0x18e8580_0 .net "carryout", 0 0, L_0x1d81e80; 1 drivers +v0x18e8620_0 .net "carryouts", 7 0, L_0x1ebed40; 1 drivers +v0x18c7200_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x18c72a0_0 .net "result", 0 0, L_0x1d7e3f0; 1 drivers +v0x18a5e50_0 .net "results", 7 0, L_0x1d7a850; 1 drivers +v0x1826c60_0 .net "zero", 0 0, L_0x1d821e0; 1 drivers +LS_0x1d7a850_0_0 .concat8 [ 1 1 1 1], L_0x1d78fa0, L_0x1d79600, L_0x1d79b00, L_0x1d7a1b0; +LS_0x1d7a850_0_4 .concat8 [ 1 1 1 1], L_0x1d7a3b0, L_0x1d7a470, L_0x1d7a5d0, L_0x1d7aa80; +L_0x1d7a850 .concat8 [ 4 4 0 0], LS_0x1d7a850_0_0, LS_0x1d7a850_0_4; +LS_0x1ebed40_0_0 .concat [ 1 1 1 1], L_0x1d792f0, L_0x1d799a0, o0x7f7259358818, L_0x1d7a000; +LS_0x1ebed40_0_4 .concat [ 4 0 0 0], o0x7f7259358848; +L_0x1ebed40 .concat [ 4 4 0 0], LS_0x1ebed40_0_0, LS_0x1ebed40_0_4; +S_0x173c940 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x173dee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d792f0/d .functor OR 1, L_0x1d78e20, L_0x1d79190, C4<0>, C4<0>; +L_0x1d792f0 .delay 1 (30000,30000,30000) L_0x1d792f0/d; +v0x18118d0_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers +v0x1811990_0 .net "b", 0 0, L_0x1d82490; alias, 1 drivers +v0x1821170_0 .net "c1", 0 0, L_0x1d78e20; 1 drivers +v0x1820de0_0 .net "c2", 0 0, L_0x1d79190; 1 drivers +v0x181e130_0 .net "carryin", 0 0, L_0x1d82530; alias, 1 drivers +v0x17f3660_0 .net "carryout", 0 0, L_0x1d792f0; 1 drivers +v0x17f3700_0 .net "s1", 0 0, L_0x1d78cc0; 1 drivers +v0x17f3220_0 .net "sum", 0 0, L_0x1d78fa0; 1 drivers +S_0x171ca50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x173c940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d78cc0/d .functor XOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; +L_0x1d78cc0 .delay 1 (30000,30000,30000) L_0x1d78cc0/d; +L_0x1d78e20/d .functor AND 1, L_0x1d82330, L_0x1d82490, C4<1>, C4<1>; +L_0x1d78e20 .delay 1 (30000,30000,30000) L_0x1d78e20/d; +v0x1832c50_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers +v0x18424a0_0 .net "b", 0 0, L_0x1d82490; alias, 1 drivers +v0x1842560_0 .net "carryout", 0 0, L_0x1d78e20; alias, 1 drivers +v0x1842110_0 .net "sum", 0 0, L_0x1d78cc0; alias, 1 drivers +S_0x171b4b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x173c940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d78fa0/d .functor XOR 1, L_0x1d78cc0, L_0x1d82530, C4<0>, C4<0>; +L_0x1d78fa0 .delay 1 (30000,30000,30000) L_0x1d78fa0/d; +L_0x1d79190/d .functor AND 1, L_0x1d78cc0, L_0x1d82530, C4<1>, C4<1>; +L_0x1d79190 .delay 1 (30000,30000,30000) L_0x1d79190/d; +v0x183f4d0_0 .net "a", 0 0, L_0x1d78cc0; alias, 1 drivers +v0x1814ac0_0 .net "b", 0 0, L_0x1d82530; alias, 1 drivers +v0x1814b60_0 .net "carryout", 0 0, L_0x1d79190; alias, 1 drivers +v0x1814730_0 .net "sum", 0 0, L_0x1d78fa0; alias, 1 drivers +S_0x16fc260 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x173dee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1708180_0 .net "ands", 7 0, L_0x1d7fe80; 1 drivers +v0x1717bd0_0 .net "in", 7 0, L_0x1ebed40; alias, 1 drivers +v0x1717c90_0 .net "out", 0 0, L_0x1d81e80; alias, 1 drivers +v0x1717840_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x16facc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x16fc260; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1781fe0_0 .net "A", 7 0, L_0x1ebed40; alias, 1 drivers +v0x178fa50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x178fb10_0 .net *"_s0", 0 0, L_0x1d7e750; 1 drivers +v0x178f610_0 .net *"_s12", 0 0, L_0x1d7f110; 1 drivers +v0x178c920_0 .net *"_s16", 0 0, L_0x1d7f470; 1 drivers +v0x179c310_0 .net *"_s20", 0 0, L_0x1d7f780; 1 drivers +v0x179bf80_0 .net *"_s24", 0 0, L_0x1d7fb70; 1 drivers +v0x17992d0_0 .net *"_s28", 0 0, L_0x1d7fb00; 1 drivers +v0x175e1e0_0 .net *"_s4", 0 0, L_0x1d7ea60; 1 drivers +v0x1760b50_0 .net *"_s8", 0 0, L_0x1d7ee00; 1 drivers +v0x176e5a0_0 .net "out", 7 0, L_0x1d7fe80; alias, 1 drivers +L_0x1d7e810 .part L_0x1ebed40, 0, 1; +L_0x1d7e970 .part v0x1d6daa0_0, 0, 1; +L_0x1d7eb20 .part L_0x1ebed40, 1, 1; +L_0x1d7ed10 .part v0x1d6daa0_0, 1, 1; +L_0x1d7eec0 .part L_0x1ebed40, 2, 1; +L_0x1d7f020 .part v0x1d6daa0_0, 2, 1; +L_0x1d7f1d0 .part L_0x1ebed40, 3, 1; +L_0x1d7f330 .part v0x1d6daa0_0, 3, 1; +L_0x1d7f530 .part L_0x1ebed40, 4, 1; +L_0x1d7f690 .part v0x1d6daa0_0, 4, 1; +L_0x1d7f7f0 .part L_0x1ebed40, 5, 1; +L_0x1d7fa60 .part v0x1d6daa0_0, 5, 1; +L_0x1d7fc30 .part L_0x1ebed40, 6, 1; +L_0x1d7fd90 .part v0x1d6daa0_0, 6, 1; +LS_0x1d7fe80_0_0 .concat8 [ 1 1 1 1], L_0x1d7e750, L_0x1d7ea60, L_0x1d7ee00, L_0x1d7f110; +LS_0x1d7fe80_0_4 .concat8 [ 1 1 1 1], L_0x1d7f470, L_0x1d7f780, L_0x1d7fb70, L_0x1d7fb00; +L_0x1d7fe80 .concat8 [ 4 4 0 0], LS_0x1d7fe80_0_0, LS_0x1d7fe80_0_4; +L_0x1d80240 .part L_0x1ebed40, 7, 1; +L_0x1d80430 .part v0x1d6daa0_0, 7, 1; +S_0x1b2b170 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17f05d0 .param/l "i" 0 4 54, +C4<00>; +L_0x1d7e750/d .functor AND 1, L_0x1d7e810, L_0x1d7e970, C4<1>, C4<1>; +L_0x1d7e750 .delay 1 (30000,30000,30000) L_0x1d7e750/d; +v0x17ffdf0_0 .net *"_s0", 0 0, L_0x1d7e810; 1 drivers +v0x17ffeb0_0 .net *"_s1", 0 0, L_0x1d7e970; 1 drivers +S_0x1825700 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17ffab0 .param/l "i" 0 4 54, +C4<01>; +L_0x1d7ea60/d .functor AND 1, L_0x1d7eb20, L_0x1d7ed10, C4<1>, C4<1>; +L_0x1d7ea60 .delay 1 (30000,30000,30000) L_0x1d7ea60/d; +v0x17fcdb0_0 .net *"_s0", 0 0, L_0x1d7eb20; 1 drivers +v0x17c1eb0_0 .net *"_s1", 0 0, L_0x1d7ed10; 1 drivers +S_0x1a15580 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17fce90 .param/l "i" 0 4 54, +C4<010>; +L_0x1d7ee00/d .functor AND 1, L_0x1d7eec0, L_0x1d7f020, C4<1>, C4<1>; +L_0x1d7ee00 .delay 1 (30000,30000,30000) L_0x1d7ee00/d; +v0x17d2290_0 .net *"_s0", 0 0, L_0x1d7eec0; 1 drivers +v0x17d1e50_0 .net *"_s1", 0 0, L_0x1d7f020; 1 drivers +S_0x1a151f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17d1f30 .param/l "i" 0 4 54, +C4<011>; +L_0x1d7f110/d .functor AND 1, L_0x1d7f1d0, L_0x1d7f330, C4<1>, C4<1>; +L_0x1d7f110 .delay 1 (30000,30000,30000) L_0x1d7f110/d; +v0x17cf1f0_0 .net *"_s0", 0 0, L_0x1d7f1d0; 1 drivers +v0x17deaa0_0 .net *"_s1", 0 0, L_0x1d7f330; 1 drivers +S_0x1a14e40 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17de760 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d7f470/d .functor AND 1, L_0x1d7f530, L_0x1d7f690, C4<1>, C4<1>; +L_0x1d7f470 .delay 1 (30000,30000,30000) L_0x1d7f470/d; +v0x17dba60_0 .net *"_s0", 0 0, L_0x1d7f530; 1 drivers +v0x17a0ad0_0 .net *"_s1", 0 0, L_0x1d7f690; 1 drivers +S_0x19f41e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17a0bb0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d7f780/d .functor AND 1, L_0x1d7f7f0, L_0x1d7fa60, C4<1>, C4<1>; +L_0x1d7f780 .delay 1 (30000,30000,30000) L_0x1d7f780/d; +v0x17b0f20_0 .net *"_s0", 0 0, L_0x1d7f7f0; 1 drivers +v0x17b0a50_0 .net *"_s1", 0 0, L_0x1d7fa60; 1 drivers +S_0x19f3e50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17add80 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d7fb70/d .functor AND 1, L_0x1d7fc30, L_0x1d7fd90, C4<1>, C4<1>; +L_0x1d7fb70 .delay 1 (30000,30000,30000) L_0x1d7fb70/d; +v0x17bd6f0_0 .net *"_s0", 0 0, L_0x1d7fc30; 1 drivers +v0x17bd360_0 .net *"_s1", 0 0, L_0x1d7fd90; 1 drivers +S_0x19f3aa0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x16facc0; + .timescale -9 -12; +P_0x17bd7f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d7fb00/d .functor AND 1, L_0x1d80240, L_0x1d80430, C4<1>, C4<1>; +L_0x1d7fb00 .delay 1 (30000,30000,30000) L_0x1d7fb00/d; +v0x17ba6b0_0 .net *"_s0", 0 0, L_0x1d80240; 1 drivers +v0x177f670_0 .net *"_s1", 0 0, L_0x1d80430; 1 drivers +S_0x19d2e30 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x16fc260; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d81e80/d .functor OR 1, L_0x1d81f40, L_0x1d820f0, C4<0>, C4<0>; +L_0x1d81e80 .delay 1 (30000,30000,30000) L_0x1d81e80/d; +v0x16fb000_0 .net *"_s10", 0 0, L_0x1d81f40; 1 drivers +v0x16fd970_0 .net *"_s12", 0 0, L_0x1d820f0; 1 drivers +v0x170b2b0_0 .net "in", 7 0, L_0x1d7fe80; alias, 1 drivers +v0x170b350_0 .net "ors", 1 0, L_0x1d81ca0; 1 drivers +v0x170ae70_0 .net "out", 0 0, L_0x1d81e80; alias, 1 drivers +L_0x1d81070 .part L_0x1d7fe80, 0, 4; +L_0x1d81ca0 .concat8 [ 1 1 0 0], L_0x1d80d60, L_0x1d81990; +L_0x1d81de0 .part L_0x1d7fe80, 4, 4; +L_0x1d81f40 .part L_0x1d81ca0, 0, 1; +L_0x1d820f0 .part L_0x1d81ca0, 1, 1; +S_0x19d2aa0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x19d2e30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d80520/d .functor OR 1, L_0x1d805e0, L_0x1d80740, C4<0>, C4<0>; +L_0x1d80520 .delay 1 (30000,30000,30000) L_0x1d80520/d; +L_0x1d80970/d .functor OR 1, L_0x1d80a80, L_0x1d80be0, C4<0>, C4<0>; +L_0x1d80970 .delay 1 (30000,30000,30000) L_0x1d80970/d; +L_0x1d80d60/d .functor OR 1, L_0x1d80dd0, L_0x1d80f80, C4<0>, C4<0>; +L_0x1d80d60 .delay 1 (30000,30000,30000) L_0x1d80d60/d; +v0x176e160_0 .net *"_s0", 0 0, L_0x1d80520; 1 drivers +v0x176b470_0 .net *"_s10", 0 0, L_0x1d80a80; 1 drivers +v0x177aeb0_0 .net *"_s12", 0 0, L_0x1d80be0; 1 drivers +v0x177af70_0 .net *"_s14", 0 0, L_0x1d80dd0; 1 drivers +v0x177ab20_0 .net *"_s16", 0 0, L_0x1d80f80; 1 drivers +v0x1777e70_0 .net *"_s3", 0 0, L_0x1d805e0; 1 drivers +v0x173e1f0_0 .net *"_s5", 0 0, L_0x1d80740; 1 drivers +v0x174d0f0_0 .net *"_s6", 0 0, L_0x1d80970; 1 drivers +v0x174ccb0_0 .net "in", 3 0, L_0x1d81070; 1 drivers +v0x1749fc0_0 .net "ors", 1 0, L_0x1d80880; 1 drivers +v0x1759a20_0 .net "out", 0 0, L_0x1d80d60; 1 drivers +L_0x1d805e0 .part L_0x1d81070, 0, 1; +L_0x1d80740 .part L_0x1d81070, 1, 1; +L_0x1d80880 .concat8 [ 1 1 0 0], L_0x1d80520, L_0x1d80970; +L_0x1d80a80 .part L_0x1d81070, 2, 1; +L_0x1d80be0 .part L_0x1d81070, 3, 1; +L_0x1d80dd0 .part L_0x1d80880, 0, 1; +L_0x1d80f80 .part L_0x1d80880, 1, 1; +S_0x19d26f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x19d2e30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d811a0/d .functor OR 1, L_0x1d81210, L_0x1d81370, C4<0>, C4<0>; +L_0x1d811a0 .delay 1 (30000,30000,30000) L_0x1d811a0/d; +L_0x1d815a0/d .functor OR 1, L_0x1d816b0, L_0x1d81810, C4<0>, C4<0>; +L_0x1d815a0 .delay 1 (30000,30000,30000) L_0x1d815a0/d; +L_0x1d81990/d .functor OR 1, L_0x1d81a00, L_0x1d81bb0, C4<0>, C4<0>; +L_0x1d81990 .delay 1 (30000,30000,30000) L_0x1d81990/d; +v0x1759690_0 .net *"_s0", 0 0, L_0x1d811a0; 1 drivers +v0x17569e0_0 .net *"_s10", 0 0, L_0x1d816b0; 1 drivers +v0x171b7f0_0 .net *"_s12", 0 0, L_0x1d81810; 1 drivers +v0x171b8b0_0 .net *"_s14", 0 0, L_0x1d81a00; 1 drivers +v0x171e160_0 .net *"_s16", 0 0, L_0x1d81bb0; 1 drivers +v0x172bc10_0 .net *"_s3", 0 0, L_0x1d81210; 1 drivers +v0x172b7d0_0 .net *"_s5", 0 0, L_0x1d81370; 1 drivers +v0x1728ae0_0 .net *"_s6", 0 0, L_0x1d815a0; 1 drivers +v0x1738540_0 .net "in", 3 0, L_0x1d81de0; 1 drivers +v0x17381b0_0 .net "ors", 1 0, L_0x1d814b0; 1 drivers +v0x1735500_0 .net "out", 0 0, L_0x1d81990; 1 drivers +L_0x1d81210 .part L_0x1d81de0, 0, 1; +L_0x1d81370 .part L_0x1d81de0, 1, 1; +L_0x1d814b0 .concat8 [ 1 1 0 0], L_0x1d811a0, L_0x1d815a0; +L_0x1d816b0 .part L_0x1d81de0, 2, 1; +L_0x1d81810 .part L_0x1d81de0, 3, 1; +L_0x1d81a00 .part L_0x1d814b0, 0, 1; +L_0x1d81bb0 .part L_0x1d814b0, 1, 1; +S_0x19b1aa0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x173dee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1acb590_0 .net "ands", 7 0, L_0x1d7c3f0; 1 drivers +v0x1acb650_0 .net "in", 7 0, L_0x1d7a850; alias, 1 drivers +v0x1abb7e0_0 .net "out", 0 0, L_0x1d7e3f0; alias, 1 drivers +v0x1abb880_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x19b1710 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x19b1aa0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x18c9420_0 .net "A", 7 0, L_0x1d7a850; alias, 1 drivers +v0x18c9090_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x18c9150_0 .net *"_s0", 0 0, L_0x1d7abe0; 1 drivers +v0x18c8ce0_0 .net *"_s12", 0 0, L_0x1d7b5a0; 1 drivers +v0x18c8dc0_0 .net *"_s16", 0 0, L_0x1d7b900; 1 drivers +v0x18a8070_0 .net *"_s20", 0 0, L_0x1d7bd30; 1 drivers +v0x18a8150_0 .net *"_s24", 0 0, L_0x1d7c060; 1 drivers +v0x18a7ce0_0 .net *"_s28", 0 0, L_0x1d7bff0; 1 drivers +v0x18a7dc0_0 .net *"_s4", 0 0, L_0x1d7af80; 1 drivers +v0x18a7a00_0 .net *"_s8", 0 0, L_0x1d7b290; 1 drivers +v0x1886cd0_0 .net "out", 7 0, L_0x1d7c3f0; alias, 1 drivers +L_0x1d7acf0 .part L_0x1d7a850, 0, 1; +L_0x1d7aee0 .part v0x1d6daa0_0, 0, 1; +L_0x1d7b040 .part L_0x1d7a850, 1, 1; +L_0x1d7b1a0 .part v0x1d6daa0_0, 1, 1; +L_0x1d7b350 .part L_0x1d7a850, 2, 1; +L_0x1d7b4b0 .part v0x1d6daa0_0, 2, 1; +L_0x1d7b660 .part L_0x1d7a850, 3, 1; +L_0x1d7b7c0 .part v0x1d6daa0_0, 3, 1; +L_0x1d7b9c0 .part L_0x1d7a850, 4, 1; +L_0x1d7bc30 .part v0x1d6daa0_0, 4, 1; +L_0x1d7bda0 .part L_0x1d7a850, 5, 1; +L_0x1d7bf00 .part v0x1d6daa0_0, 5, 1; +L_0x1d7c120 .part L_0x1d7a850, 6, 1; +L_0x1d7c280 .part v0x1d6daa0_0, 6, 1; +LS_0x1d7c3f0_0_0 .concat8 [ 1 1 1 1], L_0x1d7abe0, L_0x1d7af80, L_0x1d7b290, L_0x1d7b5a0; +LS_0x1d7c3f0_0_4 .concat8 [ 1 1 1 1], L_0x1d7b900, L_0x1d7bd30, L_0x1d7c060, L_0x1d7bff0; +L_0x1d7c3f0 .concat8 [ 4 4 0 0], LS_0x1d7c3f0_0_0, LS_0x1d7c3f0_0_4; +L_0x1d7c7b0 .part L_0x1d7a850, 7, 1; +L_0x1d7c9a0 .part v0x1d6daa0_0, 7, 1; +S_0x19b1360 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x176e240 .param/l "i" 0 4 54, +C4<00>; +L_0x1d7abe0/d .functor AND 1, L_0x1d7acf0, L_0x1d7aee0, C4<1>, C4<1>; +L_0x1d7abe0 .delay 1 (30000,30000,30000) L_0x1d7abe0/d; +v0x1714b90_0 .net *"_s0", 0 0, L_0x1d7acf0; 1 drivers +v0x19906f0_0 .net *"_s1", 0 0, L_0x1d7aee0; 1 drivers +S_0x1990360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x1777f50 .param/l "i" 0 4 54, +C4<01>; +L_0x1d7af80/d .functor AND 1, L_0x1d7b040, L_0x1d7b1a0, C4<1>, C4<1>; +L_0x1d7af80 .delay 1 (30000,30000,30000) L_0x1d7af80/d; +v0x19907d0_0 .net *"_s0", 0 0, L_0x1d7b040; 1 drivers +v0x198ffb0_0 .net *"_s1", 0 0, L_0x1d7b1a0; 1 drivers +S_0x196f3c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x1759770 .param/l "i" 0 4 54, +C4<010>; +L_0x1d7b290/d .functor AND 1, L_0x1d7b350, L_0x1d7b4b0, C4<1>, C4<1>; +L_0x1d7b290 .delay 1 (30000,30000,30000) L_0x1d7b290/d; +v0x1990090_0 .net *"_s0", 0 0, L_0x1d7b350; 1 drivers +v0x196f030_0 .net *"_s1", 0 0, L_0x1d7b4b0; 1 drivers +S_0x196ec80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x172b8b0 .param/l "i" 0 4 54, +C4<011>; +L_0x1d7b5a0/d .functor AND 1, L_0x1d7b660, L_0x1d7b7c0, C4<1>, C4<1>; +L_0x1d7b5a0 .delay 1 (30000,30000,30000) L_0x1d7b5a0/d; +v0x196f110_0 .net *"_s0", 0 0, L_0x1d7b660; 1 drivers +v0x194e0b0_0 .net *"_s1", 0 0, L_0x1d7b7c0; 1 drivers +S_0x194dd20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x16fda50 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d7b900/d .functor AND 1, L_0x1d7b9c0, L_0x1d7bc30, C4<1>, C4<1>; +L_0x1d7b900 .delay 1 (30000,30000,30000) L_0x1d7b900/d; +v0x194e190_0 .net *"_s0", 0 0, L_0x1d7b9c0; 1 drivers +v0x194d990_0 .net *"_s1", 0 0, L_0x1d7bc30; 1 drivers +S_0x192cdc0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x192ca30 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d7bd30/d .functor AND 1, L_0x1d7bda0, L_0x1d7bf00, C4<1>, C4<1>; +L_0x1d7bd30 .delay 1 (30000,30000,30000) L_0x1d7bd30/d; +v0x192caf0_0 .net *"_s0", 0 0, L_0x1d7bda0; 1 drivers +v0x192c6a0_0 .net *"_s1", 0 0, L_0x1d7bf00; 1 drivers +S_0x190baf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x190b760 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d7c060/d .functor AND 1, L_0x1d7c120, L_0x1d7c280, C4<1>, C4<1>; +L_0x1d7c060 .delay 1 (30000,30000,30000) L_0x1d7c060/d; +v0x190b820_0 .net *"_s0", 0 0, L_0x1d7c120; 1 drivers +v0x190b3d0_0 .net *"_s1", 0 0, L_0x1d7c280; 1 drivers +S_0x18ea7a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x19b1710; + .timescale -9 -12; +P_0x18ea410 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d7bff0/d .functor AND 1, L_0x1d7c7b0, L_0x1d7c9a0, C4<1>, C4<1>; +L_0x1d7bff0 .delay 1 (30000,30000,30000) L_0x1d7bff0/d; +v0x18ea4d0_0 .net *"_s0", 0 0, L_0x1d7c7b0; 1 drivers +v0x18ea080_0 .net *"_s1", 0 0, L_0x1d7c9a0; 1 drivers +S_0x1886940 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x19b1aa0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d7e3f0/d .functor OR 1, L_0x1d7e4b0, L_0x1d7e660, C4<0>, C4<0>; +L_0x1d7e3f0 .delay 1 (30000,30000,30000) L_0x1d7e3f0/d; +v0x1aec9d0_0 .net *"_s10", 0 0, L_0x1d7e4b0; 1 drivers +v0x1aecab0_0 .net *"_s12", 0 0, L_0x1d7e660; 1 drivers +v0x1adcbe0_0 .net "in", 7 0, L_0x1d7c3f0; alias, 1 drivers +v0x1adcc80_0 .net "ors", 1 0, L_0x1d7e210; 1 drivers +v0x1adc860_0 .net "out", 0 0, L_0x1d7e3f0; alias, 1 drivers +L_0x1d7d5e0 .part L_0x1d7c3f0, 0, 4; +L_0x1d7e210 .concat8 [ 1 1 0 0], L_0x1d7d2d0, L_0x1d7df00; +L_0x1d7e350 .part L_0x1d7c3f0, 4, 4; +L_0x1d7e4b0 .part L_0x1d7e210, 0, 1; +L_0x1d7e660 .part L_0x1d7e210, 1, 1; +S_0x18658f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1886940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d7ca90/d .functor OR 1, L_0x1d7cb50, L_0x1d7ccb0, C4<0>, C4<0>; +L_0x1d7ca90 .delay 1 (30000,30000,30000) L_0x1d7ca90/d; +L_0x1d7cee0/d .functor OR 1, L_0x1d7cff0, L_0x1d7d150, C4<0>, C4<0>; +L_0x1d7cee0 .delay 1 (30000,30000,30000) L_0x1d7cee0/d; +L_0x1d7d2d0/d .functor OR 1, L_0x1d7d340, L_0x1d7d4f0, C4<0>, C4<0>; +L_0x1d7d2d0 .delay 1 (30000,30000,30000) L_0x1d7d2d0/d; +v0x1865560_0 .net *"_s0", 0 0, L_0x1d7ca90; 1 drivers +v0x18651b0_0 .net *"_s10", 0 0, L_0x1d7cff0; 1 drivers +v0x1865290_0 .net *"_s12", 0 0, L_0x1d7d150; 1 drivers +v0x1844530_0 .net *"_s14", 0 0, L_0x1d7d340; 1 drivers +v0x1844610_0 .net *"_s16", 0 0, L_0x1d7d4f0; 1 drivers +v0x18441a0_0 .net *"_s3", 0 0, L_0x1d7cb50; 1 drivers +v0x1844280_0 .net *"_s5", 0 0, L_0x1d7ccb0; 1 drivers +v0x1843df0_0 .net *"_s6", 0 0, L_0x1d7cee0; 1 drivers +v0x1843ed0_0 .net "in", 3 0, L_0x1d7d5e0; 1 drivers +v0x173cd50_0 .net "ors", 1 0, L_0x1d7cdf0; 1 drivers +v0x1b31c00_0 .net "out", 0 0, L_0x1d7d2d0; 1 drivers +L_0x1d7cb50 .part L_0x1d7d5e0, 0, 1; +L_0x1d7ccb0 .part L_0x1d7d5e0, 1, 1; +L_0x1d7cdf0 .concat8 [ 1 1 0 0], L_0x1d7ca90, L_0x1d7cee0; +L_0x1d7cff0 .part L_0x1d7d5e0, 2, 1; +L_0x1d7d150 .part L_0x1d7d5e0, 3, 1; +L_0x1d7d340 .part L_0x1d7cdf0, 0, 1; +L_0x1d7d4f0 .part L_0x1d7cdf0, 1, 1; +S_0x1b34930 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1886940; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d7d710/d .functor OR 1, L_0x1d7d780, L_0x1d7d8e0, C4<0>, C4<0>; +L_0x1d7d710 .delay 1 (30000,30000,30000) L_0x1d7d710/d; +L_0x1d7db10/d .functor OR 1, L_0x1d7dc20, L_0x1d7dd80, C4<0>, C4<0>; +L_0x1d7db10 .delay 1 (30000,30000,30000) L_0x1d7db10/d; +L_0x1d7df00/d .functor OR 1, L_0x1d7df70, L_0x1d7e120, C4<0>, C4<0>; +L_0x1d7df00 .delay 1 (30000,30000,30000) L_0x1d7df00/d; +v0x1b2def0_0 .net *"_s0", 0 0, L_0x1d7d710; 1 drivers +v0x1b2dfd0_0 .net *"_s10", 0 0, L_0x1d7dc20; 1 drivers +v0x1b29fd0_0 .net *"_s12", 0 0, L_0x1d7dd80; 1 drivers +v0x1b2a070_0 .net *"_s14", 0 0, L_0x1d7df70; 1 drivers +v0x1b28f90_0 .net *"_s16", 0 0, L_0x1d7e120; 1 drivers +v0x198f490_0 .net *"_s3", 0 0, L_0x1d7d780; 1 drivers +v0x198f570_0 .net *"_s5", 0 0, L_0x1d7d8e0; 1 drivers +v0x1b0de30_0 .net *"_s6", 0 0, L_0x1d7db10; 1 drivers +v0x1b0df10_0 .net "in", 3 0, L_0x1d7e350; 1 drivers +v0x1afe090_0 .net "ors", 1 0, L_0x1d7da20; 1 drivers +v0x1afdc60_0 .net "out", 0 0, L_0x1d7df00; 1 drivers +L_0x1d7d780 .part L_0x1d7e350, 0, 1; +L_0x1d7d8e0 .part L_0x1d7e350, 1, 1; +L_0x1d7da20 .concat8 [ 1 1 0 0], L_0x1d7d710, L_0x1d7db10; +L_0x1d7dc20 .part L_0x1d7e350, 2, 1; +L_0x1d7dd80 .part L_0x1d7e350, 3, 1; +L_0x1d7df70 .part L_0x1d7da20, 0, 1; +L_0x1d7e120 .part L_0x1d7da20, 1, 1; +S_0x1aaa180 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x173dee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1d79bc0/d .functor XNOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; +L_0x1d79bc0 .delay 1 (20000,20000,20000) L_0x1d79bc0/d; +L_0x1d79e30/d .functor AND 1, L_0x1d82330, L_0x1d78ad0, C4<1>, C4<1>; +L_0x1d79e30 .delay 1 (30000,30000,30000) L_0x1d79e30/d; +L_0x1d79ea0/d .functor AND 1, L_0x1d79bc0, L_0x1d82530, C4<1>, C4<1>; +L_0x1d79ea0 .delay 1 (30000,30000,30000) L_0x1d79ea0/d; +L_0x1d7a000/d .functor OR 1, L_0x1d79ea0, L_0x1d79e30, C4<0>, C4<0>; +L_0x1d7a000 .delay 1 (30000,30000,30000) L_0x1d7a000/d; +v0x1ab6b00_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers +v0x1a9a410_0 .net "a_", 0 0, L_0x1d789c0; alias, 1 drivers +v0x1a9a4b0_0 .net "b", 0 0, L_0x1d82490; alias, 1 drivers +v0x1a9a090_0 .net "b_", 0 0, L_0x1d78ad0; alias, 1 drivers +v0x1a9a130_0 .net "carryin", 0 0, L_0x1d82530; alias, 1 drivers +v0x1a88db0_0 .net "eq", 0 0, L_0x1d79bc0; 1 drivers +v0x1a88e50_0 .net "lt", 0 0, L_0x1d79e30; 1 drivers +v0x1a95690_0 .net "out", 0 0, L_0x1d7a000; 1 drivers +v0x1a95750_0 .net "w0", 0 0, L_0x1d79ea0; 1 drivers +S_0x1a79090 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x173dee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d799a0/d .functor OR 1, L_0x1d794a0, L_0x1a31b90, C4<0>, C4<0>; +L_0x1d799a0 .delay 1 (30000,30000,30000) L_0x1d799a0/d; +v0x1a36970_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers +v0x1a365f0_0 .net "b", 0 0, L_0x1d78ad0; alias, 1 drivers +v0x1a366b0_0 .net "c1", 0 0, L_0x1d794a0; 1 drivers +v0x1a27e80_0 .net "c2", 0 0, L_0x1a31b90; 1 drivers +v0x1a27f50_0 .net "carryin", 0 0, L_0x1d82530; alias, 1 drivers +v0x1a31c20_0 .net "carryout", 0 0, L_0x1d799a0; 1 drivers +v0x1a107f0_0 .net "s1", 0 0, L_0x1821240; 1 drivers +v0x1a10890_0 .net "sum", 0 0, L_0x1d79600; 1 drivers +S_0x1a679f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1a79090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1821240/d .functor XOR 1, L_0x1d82330, L_0x1d78ad0, C4<0>, C4<0>; +L_0x1821240 .delay 1 (30000,30000,30000) L_0x1821240/d; +L_0x1d794a0/d .functor AND 1, L_0x1d82330, L_0x1d78ad0, C4<1>, C4<1>; +L_0x1d794a0 .delay 1 (30000,30000,30000) L_0x1d794a0/d; +v0x1a742d0_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers +v0x1a74370_0 .net "b", 0 0, L_0x1d78ad0; alias, 1 drivers +v0x1a57cf0_0 .net "carryout", 0 0, L_0x1d794a0; alias, 1 drivers +v0x1a57d90_0 .net "sum", 0 0, L_0x1821240; alias, 1 drivers +S_0x1a57970 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1a79090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d79600/d .functor XOR 1, L_0x1821240, L_0x1d82530, C4<0>, C4<0>; +L_0x1d79600 .delay 1 (30000,30000,30000) L_0x1d79600/d; +L_0x1a31b90/d .functor AND 1, L_0x1821240, L_0x1d82530, C4<1>, C4<1>; +L_0x1a31b90 .delay 1 (30000,30000,30000) L_0x1a31b90/d; +v0x1a492d0_0 .net "a", 0 0, L_0x1821240; alias, 1 drivers +v0x1a46670_0 .net "b", 0 0, L_0x1d82530; alias, 1 drivers +v0x1a46710_0 .net "carryout", 0 0, L_0x1a31b90; alias, 1 drivers +v0x1a52f20_0 .net "sum", 0 0, L_0x1d79600; alias, 1 drivers +S_0x1833170 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x175dea0; + .timescale -9 -12; +L_0x7f72592da138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d825d0/d .functor OR 1, L_0x7f72592da138, L_0x7f72592da180, C4<0>, C4<0>; +L_0x1d825d0 .delay 1 (30000,30000,30000) L_0x1d825d0/d; +v0x1823250_0 .net/2u *"_s0", 0 0, L_0x7f72592da138; 1 drivers +v0x1823330_0 .net/2u *"_s2", 0 0, L_0x7f72592da180; 1 drivers +S_0x1822ed0 .scope generate, "alu_slices[2]" "alu_slices[2]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x18e5af0 .param/l "i" 0 3 37, +C4<010>; +S_0x1811df0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1822ed0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1d827f0/d .functor NOT 1, L_0x1d8bee0, C4<0>, C4<0>, C4<0>; +L_0x1d827f0 .delay 1 (10000,10000,10000) L_0x1d827f0/d; +L_0x1d82900/d .functor NOT 1, L_0x1d8c0d0, C4<0>, C4<0>, C4<0>; +L_0x1d82900 .delay 1 (10000,10000,10000) L_0x1d82900/d; +L_0x1d83750/d .functor XOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; +L_0x1d83750 .delay 1 (30000,30000,30000) L_0x1d83750/d; +L_0x7f72592da1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d83e00/d .functor OR 1, L_0x7f72592da1c8, L_0x7f72592da210, C4<0>, C4<0>; +L_0x1d83e00 .delay 1 (30000,30000,30000) L_0x1d83e00/d; +L_0x1d84000/d .functor AND 1, L_0x1d8bee0, L_0x1d8c0d0, C4<1>, C4<1>; +L_0x1d84000 .delay 1 (30000,30000,30000) L_0x1d84000/d; +L_0x1d840c0/d .functor NAND 1, L_0x1d8bee0, L_0x1d8c0d0, C4<1>, C4<1>; +L_0x1d840c0 .delay 1 (20000,20000,20000) L_0x1d840c0/d; +L_0x1d84220/d .functor XOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; +L_0x1d84220 .delay 1 (20000,20000,20000) L_0x1d84220/d; +L_0x1d846d0/d .functor OR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; +L_0x1d846d0 .delay 1 (30000,30000,30000) L_0x1d846d0/d; +L_0x1d8bde0/d .functor NOT 1, L_0x1d88040, C4<0>, C4<0>, C4<0>; +L_0x1d8bde0 .delay 1 (10000,10000,10000) L_0x1d8bde0/d; +v0x1b61ee0_0 .net "A", 0 0, L_0x1d8bee0; 1 drivers +v0x1b61fa0_0 .net "A_", 0 0, L_0x1d827f0; 1 drivers +v0x1b62060_0 .net "B", 0 0, L_0x1d8c0d0; 1 drivers +v0x1b62130_0 .net "B_", 0 0, L_0x1d82900; 1 drivers +v0x1b621d0_0 .net *"_s12", 0 0, L_0x1d83e00; 1 drivers +v0x1b622c0_0 .net/2s *"_s14", 0 0, L_0x7f72592da1c8; 1 drivers +v0x1b62380_0 .net/2s *"_s16", 0 0, L_0x7f72592da210; 1 drivers +v0x1b62460_0 .net *"_s18", 0 0, L_0x1d84000; 1 drivers +v0x1b62540_0 .net *"_s20", 0 0, L_0x1d840c0; 1 drivers +v0x1b626b0_0 .net *"_s22", 0 0, L_0x1d84220; 1 drivers +v0x1b62790_0 .net *"_s24", 0 0, L_0x1d846d0; 1 drivers +o0x7f725935ad68 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1b62870_0 name=_s30 +o0x7f725935ad98 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1b62950_0 name=_s32 +v0x1b62a30_0 .net *"_s8", 0 0, L_0x1d83750; 1 drivers +v0x1b62b10_0 .net "carryin", 0 0, L_0x1d8c200; 1 drivers +v0x1b62bb0_0 .net "carryout", 0 0, L_0x1d8ba80; 1 drivers +v0x1b62c50_0 .net "carryouts", 7 0, L_0x1ebeed0; 1 drivers +v0x1b62e00_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b62ea0_0 .net "result", 0 0, L_0x1d88040; 1 drivers +v0x1b62f90_0 .net "results", 7 0, L_0x1d844a0; 1 drivers +v0x1b630a0_0 .net "zero", 0 0, L_0x1d8bde0; 1 drivers +LS_0x1d844a0_0_0 .concat8 [ 1 1 1 1], L_0x1d82c70, L_0x1d832a0, L_0x1d83750, L_0x1d83e00; +LS_0x1d844a0_0_4 .concat8 [ 1 1 1 1], L_0x1d84000, L_0x1d840c0, L_0x1d84220, L_0x1d846d0; +L_0x1d844a0 .concat8 [ 4 4 0 0], LS_0x1d844a0_0_0, LS_0x1d844a0_0_4; +LS_0x1ebeed0_0_0 .concat [ 1 1 1 1], L_0x1d82f20, L_0x1d835f0, o0x7f725935ad68, L_0x1d83c50; +LS_0x1ebeed0_0_4 .concat [ 4 0 0 0], o0x7f725935ad98; +L_0x1ebeed0 .concat [ 4 4 0 0], LS_0x1ebeed0_0_0, LS_0x1ebeed0_0_4; +S_0x1801b50 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1811df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d82f20/d .functor OR 1, L_0x1d82af0, L_0x1d82dc0, C4<0>, C4<0>; +L_0x1d82f20 .delay 1 (30000,30000,30000) L_0x1d82f20/d; +v0x179e070_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers +v0x179e130_0 .net "b", 0 0, L_0x1d8c0d0; alias, 1 drivers +v0x178ce40_0 .net "c1", 0 0, L_0x1d82af0; 1 drivers +v0x178cf40_0 .net "c2", 0 0, L_0x1d82dc0; 1 drivers +v0x177cf90_0 .net "carryin", 0 0, L_0x1d8c200; alias, 1 drivers +v0x177d080_0 .net "carryout", 0 0, L_0x1d82f20; 1 drivers +v0x177cc10_0 .net "s1", 0 0, L_0x1d7c370; 1 drivers +v0x177cd00_0 .net "sum", 0 0, L_0x1d82c70; 1 drivers +S_0x17f0a50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1801b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d7c370/d .functor XOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; +L_0x1d7c370 .delay 1 (30000,30000,30000) L_0x1d7c370/d; +L_0x1d82af0/d .functor AND 1, L_0x1d8bee0, L_0x1d8c0d0, C4<1>, C4<1>; +L_0x1d82af0 .delay 1 (30000,30000,30000) L_0x1d82af0/d; +v0x17e0c40_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers +v0x17e0800_0 .net "b", 0 0, L_0x1d8c0d0; alias, 1 drivers +v0x17e08a0_0 .net "carryout", 0 0, L_0x1d82af0; alias, 1 drivers +v0x17cf680_0 .net "sum", 0 0, L_0x1d7c370; alias, 1 drivers +S_0x17bf7d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1801b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d82c70/d .functor XOR 1, L_0x1d7c370, L_0x1d8c200, C4<0>, C4<0>; +L_0x1d82c70 .delay 1 (30000,30000,30000) L_0x1d82c70/d; +L_0x1d82dc0/d .functor AND 1, L_0x1d7c370, L_0x1d8c200, C4<1>, C4<1>; +L_0x1d82dc0 .delay 1 (30000,30000,30000) L_0x1d82dc0/d; +v0x17bf4c0_0 .net "a", 0 0, L_0x1d7c370; alias, 1 drivers +v0x17ae280_0 .net "b", 0 0, L_0x1d8c200; alias, 1 drivers +v0x17ae320_0 .net "carryout", 0 0, L_0x1d82dc0; alias, 1 drivers +v0x179e3f0_0 .net "sum", 0 0, L_0x1d82c70; alias, 1 drivers +S_0x176b990 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1811df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1a99e10_0 .net "ands", 7 0, L_0x1d89a80; 1 drivers +v0x1a78970_0 .net "in", 7 0, L_0x1ebeed0; alias, 1 drivers +v0x1a78a10_0 .net "out", 0 0, L_0x1d8ba80; alias, 1 drivers +v0x1a575d0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x175bb00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x176b990; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x167c610_0 .net "A", 7 0, L_0x1ebeed0; alias, 1 drivers +v0x1671f10_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1671ff0_0 .net *"_s0", 0 0, L_0x1d883a0; 1 drivers +v0x16678f0_0 .net *"_s12", 0 0, L_0x1d88d10; 1 drivers +v0x16679d0_0 .net *"_s16", 0 0, L_0x1d89070; 1 drivers +v0x165d360_0 .net *"_s20", 0 0, L_0x1d89380; 1 drivers +v0x1652cb0_0 .net *"_s24", 0 0, L_0x1d89770; 1 drivers +v0x1652d90_0 .net *"_s28", 0 0, L_0x1d89700; 1 drivers +v0x1648690_0 .net *"_s4", 0 0, L_0x1d886b0; 1 drivers +v0x163e070_0 .net *"_s8", 0 0, L_0x1d88a00; 1 drivers +v0x163e150_0 .net "out", 7 0, L_0x1d89a80; alias, 1 drivers +L_0x1d88460 .part L_0x1ebeed0, 0, 1; +L_0x1d885c0 .part v0x1d6daa0_0, 0, 1; +L_0x1d88770 .part L_0x1ebeed0, 1, 1; +L_0x1d88960 .part v0x1d6daa0_0, 1, 1; +L_0x1d88ac0 .part L_0x1ebeed0, 2, 1; +L_0x1d88c20 .part v0x1d6daa0_0, 2, 1; +L_0x1d88dd0 .part L_0x1ebeed0, 3, 1; +L_0x1d88f30 .part v0x1d6daa0_0, 3, 1; +L_0x1d89130 .part L_0x1ebeed0, 4, 1; +L_0x1d89290 .part v0x1d6daa0_0, 4, 1; +L_0x1d893f0 .part L_0x1ebeed0, 5, 1; +L_0x1d89660 .part v0x1d6daa0_0, 5, 1; +L_0x1d89830 .part L_0x1ebeed0, 6, 1; +L_0x1d89990 .part v0x1d6daa0_0, 6, 1; +LS_0x1d89a80_0_0 .concat8 [ 1 1 1 1], L_0x1d883a0, L_0x1d886b0, L_0x1d88a00, L_0x1d88d10; +LS_0x1d89a80_0_4 .concat8 [ 1 1 1 1], L_0x1d89070, L_0x1d89380, L_0x1d89770, L_0x1d89700; +L_0x1d89a80 .concat8 [ 4 4 0 0], LS_0x1d89a80_0_0, LS_0x1d89a80_0_4; +L_0x1d89e40 .part L_0x1ebeed0, 7, 1; +L_0x1d8a030 .part v0x1d6daa0_0, 7, 1; +S_0x174a4e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x175b840 .param/l "i" 0 4 54, +C4<00>; +L_0x1d883a0/d .functor AND 1, L_0x1d88460, L_0x1d885c0, C4<1>, C4<1>; +L_0x1d883a0 .delay 1 (30000,30000,30000) L_0x1d883a0/d; +v0x173a620_0 .net *"_s0", 0 0, L_0x1d88460; 1 drivers +v0x173a700_0 .net *"_s1", 0 0, L_0x1d885c0; 1 drivers +S_0x173a2a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x1729050 .param/l "i" 0 4 54, +C4<01>; +L_0x1d886b0/d .functor AND 1, L_0x1d88770, L_0x1d88960, C4<1>, C4<1>; +L_0x1d886b0 .delay 1 (30000,30000,30000) L_0x1d886b0/d; +v0x1719da0_0 .net *"_s0", 0 0, L_0x1d88770; 1 drivers +v0x1719e80_0 .net *"_s1", 0 0, L_0x1d88960; 1 drivers +S_0x17199f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x17086a0 .param/l "i" 0 4 54, +C4<010>; +L_0x1d88a00/d .functor AND 1, L_0x1d88ac0, L_0x1d88c20, C4<1>, C4<1>; +L_0x1d88a00 .delay 1 (30000,30000,30000) L_0x1d88a00/d; +v0x1708740_0 .net *"_s0", 0 0, L_0x1d88ac0; 1 drivers +v0x1adbd30_0 .net *"_s1", 0 0, L_0x1d88c20; 1 drivers +S_0x1aba930 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x1adbe60 .param/l "i" 0 4 54, +C4<011>; +L_0x1d88d10/d .functor AND 1, L_0x1d88dd0, L_0x1d88f30, C4<1>, C4<1>; +L_0x1d88d10 .delay 1 (30000,30000,30000) L_0x1d88d10/d; +v0x1a995f0_0 .net *"_s0", 0 0, L_0x1d88dd0; 1 drivers +v0x1a781e0_0 .net *"_s1", 0 0, L_0x1d88f30; 1 drivers +S_0x16ee890 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x16e4270 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d89070/d .functor AND 1, L_0x1d89130, L_0x1d89290, C4<1>, C4<1>; +L_0x1d89070 .delay 1 (30000,30000,30000) L_0x1d89070/d; +v0x16e4350_0 .net *"_s0", 0 0, L_0x1d89130; 1 drivers +v0x16d9c50_0 .net *"_s1", 0 0, L_0x1d89290; 1 drivers +S_0x16cf630 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x16d9da0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d89380/d .functor AND 1, L_0x1d893f0, L_0x1d89660, C4<1>, C4<1>; +L_0x1d89380 .delay 1 (30000,30000,30000) L_0x1d89380/d; +v0x16c50a0_0 .net *"_s0", 0 0, L_0x1d893f0; 1 drivers +v0x16ba9f0_0 .net *"_s1", 0 0, L_0x1d89660; 1 drivers +S_0x16b03d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x16bab40 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d89770/d .functor AND 1, L_0x1d89830, L_0x1d89990, C4<1>, C4<1>; +L_0x1d89770 .delay 1 (30000,30000,30000) L_0x1d89770/d; +v0x16a5e40_0 .net *"_s0", 0 0, L_0x1d89830; 1 drivers +v0x169b790_0 .net *"_s1", 0 0, L_0x1d89990; 1 drivers +S_0x1691170 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x175bb00; + .timescale -9 -12; +P_0x169b8e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d89700/d .functor AND 1, L_0x1d89e40, L_0x1d8a030, C4<1>, C4<1>; +L_0x1d89700 .delay 1 (30000,30000,30000) L_0x1d89700/d; +v0x1686be0_0 .net *"_s0", 0 0, L_0x1d89e40; 1 drivers +v0x167c530_0 .net *"_s1", 0 0, L_0x1d8a030; 1 drivers +S_0x1633a50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x176b990; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d8ba80/d .functor OR 1, L_0x1d8bb40, L_0x1d8bcf0, C4<0>, C4<0>; +L_0x1d8ba80 .delay 1 (30000,30000,30000) L_0x1d8ba80/d; +v0x1adc4c0_0 .net *"_s10", 0 0, L_0x1d8bb40; 1 drivers +v0x1adc5a0_0 .net *"_s12", 0 0, L_0x1d8bcf0; 1 drivers +v0x1abb0c0_0 .net "in", 7 0, L_0x1d89a80; alias, 1 drivers +v0x1abb160_0 .net "ors", 1 0, L_0x1d8b8a0; 1 drivers +v0x1a99cf0_0 .net "out", 0 0, L_0x1d8ba80; alias, 1 drivers +L_0x1d8ac70 .part L_0x1d89a80, 0, 4; +L_0x1d8b8a0 .concat8 [ 1 1 0 0], L_0x1d8a960, L_0x1d8b590; +L_0x1d8b9e0 .part L_0x1d89a80, 4, 4; +L_0x1d8bb40 .part L_0x1d8b8a0, 0, 1; +L_0x1d8bcf0 .part L_0x1d8b8a0, 1, 1; +S_0x1629430 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1633a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d8a120/d .functor OR 1, L_0x1d8a1e0, L_0x1d8a340, C4<0>, C4<0>; +L_0x1d8a120 .delay 1 (30000,30000,30000) L_0x1d8a120/d; +L_0x1d8a570/d .functor OR 1, L_0x1d8a680, L_0x1d8a7e0, C4<0>, C4<0>; +L_0x1d8a570 .delay 1 (30000,30000,30000) L_0x1d8a570/d; +L_0x1d8a960/d .functor OR 1, L_0x1d8a9d0, L_0x1d8ab80, C4<0>, C4<0>; +L_0x1d8a960 .delay 1 (30000,30000,30000) L_0x1d8a960/d; +v0x161ee80_0 .net *"_s0", 0 0, L_0x1d8a120; 1 drivers +v0x16147f0_0 .net *"_s10", 0 0, L_0x1d8a680; 1 drivers +v0x16148d0_0 .net *"_s12", 0 0, L_0x1d8a7e0; 1 drivers +v0x160a1d0_0 .net *"_s14", 0 0, L_0x1d8a9d0; 1 drivers +v0x160a2b0_0 .net *"_s16", 0 0, L_0x1d8ab80; 1 drivers +v0x15ffc40_0 .net *"_s3", 0 0, L_0x1d8a1e0; 1 drivers +v0x15f55e0_0 .net *"_s5", 0 0, L_0x1d8a340; 1 drivers +v0x15f56c0_0 .net *"_s6", 0 0, L_0x1d8a570; 1 drivers +v0x15eaf70_0 .net "in", 3 0, L_0x1d8ac70; 1 drivers +v0x15e0950_0 .net "ors", 1 0, L_0x1d8a480; 1 drivers +v0x15e0a30_0 .net "out", 0 0, L_0x1d8a960; 1 drivers +L_0x1d8a1e0 .part L_0x1d8ac70, 0, 1; +L_0x1d8a340 .part L_0x1d8ac70, 1, 1; +L_0x1d8a480 .concat8 [ 1 1 0 0], L_0x1d8a120, L_0x1d8a570; +L_0x1d8a680 .part L_0x1d8ac70, 2, 1; +L_0x1d8a7e0 .part L_0x1d8ac70, 3, 1; +L_0x1d8a9d0 .part L_0x1d8a480, 0, 1; +L_0x1d8ab80 .part L_0x1d8a480, 1, 1; +S_0x15d6370 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1633a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d8ada0/d .functor OR 1, L_0x1d8ae10, L_0x1d8af70, C4<0>, C4<0>; +L_0x1d8ada0 .delay 1 (30000,30000,30000) L_0x1d8ada0/d; +L_0x1d8b1a0/d .functor OR 1, L_0x1d8b2b0, L_0x1d8b410, C4<0>, C4<0>; +L_0x1d8b1a0 .delay 1 (30000,30000,30000) L_0x1d8b1a0/d; +L_0x1d8b590/d .functor OR 1, L_0x1d8b600, L_0x1d8b7b0, C4<0>, C4<0>; +L_0x1d8b590 .delay 1 (30000,30000,30000) L_0x1d8b590/d; +v0x15cbd50_0 .net *"_s0", 0 0, L_0x1d8ada0; 1 drivers +v0x15cbe30_0 .net *"_s10", 0 0, L_0x1d8b2b0; 1 drivers +v0x15c1730_0 .net *"_s12", 0 0, L_0x1d8b410; 1 drivers +v0x15c1810_0 .net *"_s14", 0 0, L_0x1d8b600; 1 drivers +v0x15b7110_0 .net *"_s16", 0 0, L_0x1d8b7b0; 1 drivers +v0x15b7220_0 .net *"_s3", 0 0, L_0x1d8ae10; 1 drivers +v0x15acaf0_0 .net *"_s5", 0 0, L_0x1d8af70; 1 drivers +v0x15acbd0_0 .net *"_s6", 0 0, L_0x1d8b1a0; 1 drivers +v0x1739440_0 .net "in", 3 0, L_0x1d8b9e0; 1 drivers +v0x1afd8c0_0 .net "ors", 1 0, L_0x1d8b0b0; 1 drivers +v0x1afd9a0_0 .net "out", 0 0, L_0x1d8b590; 1 drivers +L_0x1d8ae10 .part L_0x1d8b9e0, 0, 1; +L_0x1d8af70 .part L_0x1d8b9e0, 1, 1; +L_0x1d8b0b0 .concat8 [ 1 1 0 0], L_0x1d8ada0, L_0x1d8b1a0; +L_0x1d8b2b0 .part L_0x1d8b9e0, 2, 1; +L_0x1d8b410 .part L_0x1d8b9e0, 3, 1; +L_0x1d8b600 .part L_0x1d8b0b0, 0, 1; +L_0x1d8b7b0 .part L_0x1d8b0b0, 1, 1; +S_0x1a36250 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1811df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1930850_0 .net "ands", 7 0, L_0x1d86040; 1 drivers +v0x1930960_0 .net "in", 7 0, L_0x1d844a0; alias, 1 drivers +v0x1930a20_0 .net "out", 0 0, L_0x1d88040; alias, 1 drivers +v0x190f580_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1847fc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1a36250; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1a3a6a0_0 .net "A", 7 0, L_0x1d844a0; alias, 1 drivers +v0x1a19190_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1a19230_0 .net *"_s0", 0 0, L_0x1d84830; 1 drivers +v0x1a192f0_0 .net *"_s12", 0 0, L_0x1d851f0; 1 drivers +v0x19f7df0_0 .net *"_s16", 0 0, L_0x1d85550; 1 drivers +v0x19f7f20_0 .net *"_s20", 0 0, L_0x1d85980; 1 drivers +v0x19d6a30_0 .net *"_s24", 0 0, L_0x1d85cb0; 1 drivers +v0x19d6af0_0 .net *"_s28", 0 0, L_0x1d85c40; 1 drivers +v0x17c3420_0 .net *"_s4", 0 0, L_0x1d84bd0; 1 drivers +v0x17a2040_0 .net *"_s8", 0 0, L_0x1d84ee0; 1 drivers +v0x17a2120_0 .net "out", 7 0, L_0x1d86040; alias, 1 drivers +L_0x1d84940 .part L_0x1d844a0, 0, 1; +L_0x1d84b30 .part v0x1d6daa0_0, 0, 1; +L_0x1d84c90 .part L_0x1d844a0, 1, 1; +L_0x1d84df0 .part v0x1d6daa0_0, 1, 1; +L_0x1d84fa0 .part L_0x1d844a0, 2, 1; +L_0x1d85100 .part v0x1d6daa0_0, 2, 1; +L_0x1d852b0 .part L_0x1d844a0, 3, 1; +L_0x1d85410 .part v0x1d6daa0_0, 3, 1; +L_0x1d85610 .part L_0x1d844a0, 4, 1; +L_0x1d85880 .part v0x1d6daa0_0, 4, 1; +L_0x1d859f0 .part L_0x1d844a0, 5, 1; +L_0x1d85b50 .part v0x1d6daa0_0, 5, 1; +L_0x1d85d70 .part L_0x1d844a0, 6, 1; +L_0x1d85ed0 .part v0x1d6daa0_0, 6, 1; +LS_0x1d86040_0_0 .concat8 [ 1 1 1 1], L_0x1d84830, L_0x1d84bd0, L_0x1d84ee0, L_0x1d851f0; +LS_0x1d86040_0_4 .concat8 [ 1 1 1 1], L_0x1d85550, L_0x1d85980, L_0x1d85cb0, L_0x1d85c40; +L_0x1d86040 .concat8 [ 4 4 0 0], LS_0x1d86040_0_0, LS_0x1d86040_0_4; +L_0x1d86400 .part L_0x1d844a0, 7, 1; +L_0x1d865f0 .part v0x1d6daa0_0, 7, 1; +S_0x1822b30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x1a57700 .param/l "i" 0 4 54, +C4<00>; +L_0x1d84830/d .functor AND 1, L_0x1d84940, L_0x1d84b30, C4<1>, C4<1>; +L_0x1d84830 .delay 1 (30000,30000,30000) L_0x1d84830/d; +v0x18017b0_0 .net *"_s0", 0 0, L_0x1d84940; 1 drivers +v0x1801890_0 .net *"_s1", 0 0, L_0x1d84b30; 1 drivers +S_0x17e0460 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x17bf120 .param/l "i" 0 4 54, +C4<01>; +L_0x1d84bd0/d .functor AND 1, L_0x1d84c90, L_0x1d84df0, C4<1>, C4<1>; +L_0x1d84bd0 .delay 1 (30000,30000,30000) L_0x1d84bd0/d; +v0x17bf1e0_0 .net *"_s0", 0 0, L_0x1d84c90; 1 drivers +v0x179dcf0_0 .net *"_s1", 0 0, L_0x1d84df0; 1 drivers +S_0x177c870 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x179de40 .param/l "i" 0 4 54, +C4<010>; +L_0x1d84ee0/d .functor AND 1, L_0x1d84fa0, L_0x1d85100, C4<1>, C4<1>; +L_0x1d84ee0 .delay 1 (30000,30000,30000) L_0x1d84ee0/d; +v0x175b430_0 .net *"_s0", 0 0, L_0x1d84fa0; 1 drivers +v0x175b510_0 .net *"_s1", 0 0, L_0x1d85100; 1 drivers +S_0x1739f20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x1719690 .param/l "i" 0 4 54, +C4<011>; +L_0x1d851f0/d .functor AND 1, L_0x1d852b0, L_0x1d85410, C4<1>, C4<1>; +L_0x1d851f0 .delay 1 (30000,30000,30000) L_0x1d851f0/d; +v0x18494c0_0 .net *"_s0", 0 0, L_0x1d852b0; 1 drivers +v0x18495a0_0 .net *"_s1", 0 0, L_0x1d85410; 1 drivers +S_0x1828160 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x17e5a00 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d85550/d .functor AND 1, L_0x1d85610, L_0x1d85880, C4<1>, C4<1>; +L_0x1d85550 .delay 1 (30000,30000,30000) L_0x1d85550/d; +v0x17e5ac0_0 .net *"_s0", 0 0, L_0x1d85610; 1 drivers +v0x1b01c30_0 .net *"_s1", 0 0, L_0x1d85880; 1 drivers +S_0x1b006c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x1b01d10 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d85980/d .functor AND 1, L_0x1d859f0, L_0x1d85b50, C4<1>, C4<1>; +L_0x1d85980 .delay 1 (30000,30000,30000) L_0x1d85980/d; +v0x1b03030_0 .net *"_s0", 0 0, L_0x1d859f0; 1 drivers +v0x1b03110_0 .net *"_s1", 0 0, L_0x1d85b50; 1 drivers +S_0x1abf430 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x1abf5d0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d85cb0/d .functor AND 1, L_0x1d85d70, L_0x1d85ed0, C4<1>, C4<1>; +L_0x1d85cb0 .delay 1 (30000,30000,30000) L_0x1d85cb0/d; +v0x1a9e0d0_0 .net *"_s0", 0 0, L_0x1d85d70; 1 drivers +v0x1a9e1b0_0 .net *"_s1", 0 0, L_0x1d85ed0; 1 drivers +S_0x1a7cce0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1847fc0; + .timescale -9 -12; +P_0x1a5b940 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d85c40/d .functor AND 1, L_0x1d86400, L_0x1d865f0, C4<1>, C4<1>; +L_0x1d85c40 .delay 1 (30000,30000,30000) L_0x1d85c40/d; +v0x1a5b9e0_0 .net *"_s0", 0 0, L_0x1d86400; 1 drivers +v0x1a3a5c0_0 .net *"_s1", 0 0, L_0x1d865f0; 1 drivers +S_0x17a3440 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1a36250; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d88040/d .functor OR 1, L_0x1d88100, L_0x1d882b0, C4<0>, C4<0>; +L_0x1d88040 .delay 1 (30000,30000,30000) L_0x1d88040/d; +v0x1972e50_0 .net *"_s10", 0 0, L_0x1d88100; 1 drivers +v0x1972f30_0 .net *"_s12", 0 0, L_0x1d882b0; 1 drivers +v0x1973010_0 .net "in", 7 0, L_0x1d86040; alias, 1 drivers +v0x1951b40_0 .net "ors", 1 0, L_0x1d87e60; 1 drivers +v0x1951c00_0 .net "out", 0 0, L_0x1d88040; alias, 1 drivers +L_0x1d87230 .part L_0x1d86040, 0, 4; +L_0x1d87e60 .concat8 [ 1 1 0 0], L_0x1d86f20, L_0x1d87b50; +L_0x1d87fa0 .part L_0x1d86040, 4, 4; +L_0x1d88100 .part L_0x1d87e60, 0, 1; +L_0x1d882b0 .part L_0x1d87e60, 1, 1; +S_0x1780be0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x17a3440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d866e0/d .functor OR 1, L_0x1d867a0, L_0x1d86900, C4<0>, C4<0>; +L_0x1d866e0 .delay 1 (30000,30000,30000) L_0x1d866e0/d; +L_0x1d86b30/d .functor OR 1, L_0x1d86c40, L_0x1d86da0, C4<0>, C4<0>; +L_0x1d86b30 .delay 1 (30000,30000,30000) L_0x1d86b30/d; +L_0x1d86f20/d .functor OR 1, L_0x1d86f90, L_0x1d87140, C4<0>, C4<0>; +L_0x1d86f20 .delay 1 (30000,30000,30000) L_0x1d86f20/d; +v0x175f750_0 .net *"_s0", 0 0, L_0x1d866e0; 1 drivers +v0x175f830_0 .net *"_s10", 0 0, L_0x1d86c40; 1 drivers +v0x173f5f0_0 .net *"_s12", 0 0, L_0x1d86da0; 1 drivers +v0x173f6b0_0 .net *"_s14", 0 0, L_0x1d86f90; 1 drivers +v0x171cd60_0 .net *"_s16", 0 0, L_0x1d87140; 1 drivers +v0x171ce40_0 .net *"_s3", 0 0, L_0x1d867a0; 1 drivers +v0x16fc570_0 .net *"_s5", 0 0, L_0x1d86900; 1 drivers +v0x16fc650_0 .net *"_s6", 0 0, L_0x1d86b30; 1 drivers +v0x1b210c0_0 .net "in", 3 0, L_0x1d87230; 1 drivers +v0x1b21230_0 .net "ors", 1 0, L_0x1d86a40; 1 drivers +v0x1afd130_0 .net "out", 0 0, L_0x1d86f20; 1 drivers +L_0x1d867a0 .part L_0x1d87230, 0, 1; +L_0x1d86900 .part L_0x1d87230, 1, 1; +L_0x1d86a40 .concat8 [ 1 1 0 0], L_0x1d866e0, L_0x1d86b30; +L_0x1d86c40 .part L_0x1d87230, 2, 1; +L_0x1d86da0 .part L_0x1d87230, 3, 1; +L_0x1d86f90 .part L_0x1d86a40, 0, 1; +L_0x1d87140 .part L_0x1d86a40, 1, 1; +S_0x1b1e280 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x17a3440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d87360/d .functor OR 1, L_0x1d873d0, L_0x1d87530, C4<0>, C4<0>; +L_0x1d87360 .delay 1 (30000,30000,30000) L_0x1d87360/d; +L_0x1d87760/d .functor OR 1, L_0x1d87870, L_0x1d879d0, C4<0>, C4<0>; +L_0x1d87760 .delay 1 (30000,30000,30000) L_0x1d87760/d; +L_0x1d87b50/d .functor OR 1, L_0x1d87bc0, L_0x1d87d70, C4<0>, C4<0>; +L_0x1d87b50 .delay 1 (30000,30000,30000) L_0x1d87b50/d; +v0x1b1e420_0 .net *"_s0", 0 0, L_0x1d87360; 1 drivers +v0x1afd230_0 .net *"_s10", 0 0, L_0x1d87870; 1 drivers +v0x17e4540_0 .net *"_s12", 0 0, L_0x1d879d0; 1 drivers +v0x17e4600_0 .net *"_s14", 0 0, L_0x1d87bc0; 1 drivers +v0x17e46e0_0 .net *"_s16", 0 0, L_0x1d87d70; 1 drivers +v0x19b5530_0 .net *"_s3", 0 0, L_0x1d873d0; 1 drivers +v0x19b5610_0 .net *"_s5", 0 0, L_0x1d87530; 1 drivers +v0x19b56f0_0 .net *"_s6", 0 0, L_0x1d87760; 1 drivers +v0x1994180_0 .net "in", 3 0, L_0x1d87fa0; 1 drivers +v0x1994240_0 .net "ors", 1 0, L_0x1d87670; 1 drivers +v0x1994320_0 .net "out", 0 0, L_0x1d87b50; 1 drivers +L_0x1d873d0 .part L_0x1d87fa0, 0, 1; +L_0x1d87530 .part L_0x1d87fa0, 1, 1; +L_0x1d87670 .concat8 [ 1 1 0 0], L_0x1d87360, L_0x1d87760; +L_0x1d87870 .part L_0x1d87fa0, 2, 1; +L_0x1d879d0 .part L_0x1d87fa0, 3, 1; +L_0x1d87bc0 .part L_0x1d87670, 0, 1; +L_0x1d87d70 .part L_0x1d87670, 1, 1; +S_0x190f660 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1811df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1d83810/d .functor XNOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; +L_0x1d83810 .delay 1 (20000,20000,20000) L_0x1d83810/d; +L_0x1d83a80/d .functor AND 1, L_0x1d8bee0, L_0x1d82900, C4<1>, C4<1>; +L_0x1d83a80 .delay 1 (30000,30000,30000) L_0x1d83a80/d; +L_0x1d83af0/d .functor AND 1, L_0x1d83810, L_0x1d8c200, C4<1>, C4<1>; +L_0x1d83af0 .delay 1 (30000,30000,30000) L_0x1d83af0/d; +L_0x1d83c50/d .functor OR 1, L_0x1d83af0, L_0x1d83a80, C4<0>, C4<0>; +L_0x1d83c50 .delay 1 (30000,30000,30000) L_0x1d83c50/d; +v0x18ee2d0_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers +v0x18ee3c0_0 .net "a_", 0 0, L_0x1d827f0; alias, 1 drivers +v0x18cceb0_0 .net "b", 0 0, L_0x1d8c0d0; alias, 1 drivers +v0x18ccfa0_0 .net "b_", 0 0, L_0x1d82900; alias, 1 drivers +v0x18cd040_0 .net "carryin", 0 0, L_0x1d8c200; alias, 1 drivers +v0x18abb00_0 .net "eq", 0 0, L_0x1d83810; 1 drivers +v0x18abbc0_0 .net "lt", 0 0, L_0x1d83a80; 1 drivers +v0x18abc80_0 .net "out", 0 0, L_0x1d83c50; 1 drivers +v0x188a760_0 .net "w0", 0 0, L_0x1d83af0; 1 drivers +S_0x1869380 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1811df0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d835f0/d .functor OR 1, L_0x1d83140, L_0x1b61c20, C4<0>, C4<0>; +L_0x1d835f0 .delay 1 (30000,30000,30000) L_0x1d835f0/d; +v0x1b61820_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers +v0x1b61950_0 .net "b", 0 0, L_0x1d82900; alias, 1 drivers +v0x1b619f0_0 .net "c1", 0 0, L_0x1d83140; 1 drivers +v0x1b61a90_0 .net "c2", 0 0, L_0x1b61c20; 1 drivers +v0x1b61b30_0 .net "carryin", 0 0, L_0x1d8c200; alias, 1 drivers +v0x1b61cb0_0 .net "carryout", 0 0, L_0x1d835f0; 1 drivers +v0x1b61d50_0 .net "s1", 0 0, L_0x1d83080; 1 drivers +v0x1b61e40_0 .net "sum", 0 0, L_0x1d832a0; 1 drivers +S_0x18058e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1869380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d83080/d .functor XOR 1, L_0x1d8bee0, L_0x1d82900, C4<0>, C4<0>; +L_0x1d83080 .delay 1 (30000,30000,30000) L_0x1d83080/d; +L_0x1d83140/d .functor AND 1, L_0x1d8bee0, L_0x1d82900, C4<1>, C4<1>; +L_0x1d83140 .delay 1 (30000,30000,30000) L_0x1d83140/d; +v0x1869550_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers +v0x188a8e0_0 .net "b", 0 0, L_0x1d82900; alias, 1 drivers +v0x1b1f0b0_0 .net "carryout", 0 0, L_0x1d83140; alias, 1 drivers +v0x1b1f150_0 .net "sum", 0 0, L_0x1d83080; alias, 1 drivers +S_0x1b1f250 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1869380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d832a0/d .functor XOR 1, L_0x1d83080, L_0x1d8c200, C4<0>, C4<0>; +L_0x1d832a0 .delay 1 (30000,30000,30000) L_0x1d832a0/d; +L_0x1b61c20/d .functor AND 1, L_0x1d83080, L_0x1d8c200, C4<1>, C4<1>; +L_0x1b61c20 .delay 1 (30000,30000,30000) L_0x1b61c20/d; +v0x1b615a0_0 .net "a", 0 0, L_0x1d83080; alias, 1 drivers +v0x1b61640_0 .net "b", 0 0, L_0x1d8c200; alias, 1 drivers +v0x1b616e0_0 .net "carryout", 0 0, L_0x1b61c20; alias, 1 drivers +v0x1b61780_0 .net "sum", 0 0, L_0x1d832a0; alias, 1 drivers +S_0x1b63240 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1822ed0; + .timescale -9 -12; +L_0x7f72592da258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d8bf80/d .functor OR 1, L_0x7f72592da258, L_0x7f72592da2a0, C4<0>, C4<0>; +L_0x1d8bf80 .delay 1 (30000,30000,30000) L_0x1d8bf80/d; +v0x1b63430_0 .net/2u *"_s0", 0 0, L_0x7f72592da258; 1 drivers +v0x1b63510_0 .net/2u *"_s2", 0 0, L_0x7f72592da2a0; 1 drivers +S_0x1b635f0 .scope generate, "alu_slices[3]" "alu_slices[3]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1b63800 .param/l "i" 0 3 37, +C4<011>; +S_0x1b638c0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b635f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1d8c400/d .functor NOT 1, L_0x1d95c10, C4<0>, C4<0>, C4<0>; +L_0x1d8c400 .delay 1 (10000,10000,10000) L_0x1d8c400/d; +L_0x1d8c510/d .functor NOT 1, L_0x1d95d70, C4<0>, C4<0>, C4<0>; +L_0x1d8c510 .delay 1 (10000,10000,10000) L_0x1d8c510/d; +L_0x1d8d560/d .functor XOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; +L_0x1d8d560 .delay 1 (30000,30000,30000) L_0x1d8d560/d; +L_0x7f72592da2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d8dc10/d .functor OR 1, L_0x7f72592da2e8, L_0x7f72592da330, C4<0>, C4<0>; +L_0x1d8dc10 .delay 1 (30000,30000,30000) L_0x1d8dc10/d; +L_0x1d8de10/d .functor AND 1, L_0x1d95c10, L_0x1d95d70, C4<1>, C4<1>; +L_0x1d8de10 .delay 1 (30000,30000,30000) L_0x1d8de10/d; +L_0x1d8ded0/d .functor NAND 1, L_0x1d95c10, L_0x1d95d70, C4<1>, C4<1>; +L_0x1d8ded0 .delay 1 (20000,20000,20000) L_0x1d8ded0/d; +L_0x1d8e030/d .functor XOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; +L_0x1d8e030 .delay 1 (20000,20000,20000) L_0x1d8e030/d; +L_0x1d8e4e0/d .functor OR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; +L_0x1d8e4e0 .delay 1 (30000,30000,30000) L_0x1d8e4e0/d; +L_0x1d95b10/d .functor NOT 1, L_0x1d91d70, C4<0>, C4<0>, C4<0>; +L_0x1d95b10 .delay 1 (10000,10000,10000) L_0x1d95b10/d; +v0x1b71f80_0 .net "A", 0 0, L_0x1d95c10; 1 drivers +v0x1b72040_0 .net "A_", 0 0, L_0x1d8c400; 1 drivers +v0x1b72100_0 .net "B", 0 0, L_0x1d95d70; 1 drivers +v0x1b721d0_0 .net "B_", 0 0, L_0x1d8c510; 1 drivers +v0x1b72270_0 .net *"_s12", 0 0, L_0x1d8dc10; 1 drivers +v0x1b72360_0 .net/2s *"_s14", 0 0, L_0x7f72592da2e8; 1 drivers +v0x1b72420_0 .net/2s *"_s16", 0 0, L_0x7f72592da330; 1 drivers +v0x1b72500_0 .net *"_s18", 0 0, L_0x1d8de10; 1 drivers +v0x1b725e0_0 .net *"_s20", 0 0, L_0x1d8ded0; 1 drivers +v0x1b72750_0 .net *"_s22", 0 0, L_0x1d8e030; 1 drivers +v0x1b72830_0 .net *"_s24", 0 0, L_0x1d8e4e0; 1 drivers +o0x7f725935d2b8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1b72910_0 name=_s30 +o0x7f725935d2e8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1b729f0_0 name=_s32 +v0x1b72ad0_0 .net *"_s8", 0 0, L_0x1d8d560; 1 drivers +v0x1b72bb0_0 .net "carryin", 0 0, L_0x1d95e10; 1 drivers +v0x1b72c50_0 .net "carryout", 0 0, L_0x1d957b0; 1 drivers +v0x1b72cf0_0 .net "carryouts", 7 0, L_0x1ebf060; 1 drivers +v0x1b72ea0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b72f40_0 .net "result", 0 0, L_0x1d91d70; 1 drivers +v0x1b73030_0 .net "results", 7 0, L_0x1d8e2b0; 1 drivers +v0x1b73140_0 .net "zero", 0 0, L_0x1d95b10; 1 drivers +LS_0x1d8e2b0_0_0 .concat8 [ 1 1 1 1], L_0x1d8ca30, L_0x1d8d060, L_0x1d8d560, L_0x1d8dc10; +LS_0x1d8e2b0_0_4 .concat8 [ 1 1 1 1], L_0x1d8de10, L_0x1d8ded0, L_0x1d8e030, L_0x1d8e4e0; +L_0x1d8e2b0 .concat8 [ 4 4 0 0], LS_0x1d8e2b0_0_0, LS_0x1d8e2b0_0_4; +LS_0x1ebf060_0_0 .concat [ 1 1 1 1], L_0x1d8cce0, L_0x1d8d400, o0x7f725935d2b8, L_0x1d8da60; +LS_0x1ebf060_0_4 .concat [ 4 0 0 0], o0x7f725935d2e8; +L_0x1ebf060 .concat [ 4 4 0 0], LS_0x1ebf060_0_0, LS_0x1ebf060_0_4; +S_0x1b63b40 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b638c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d8cce0/d .functor OR 1, L_0x1d8c7c0, L_0x1d8cb80, C4<0>, C4<0>; +L_0x1d8cce0 .delay 1 (30000,30000,30000) L_0x1d8cce0/d; +v0x1b64970_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers +v0x1b64a30_0 .net "b", 0 0, L_0x1d95d70; alias, 1 drivers +v0x1b64b00_0 .net "c1", 0 0, L_0x1d8c7c0; 1 drivers +v0x1b64c00_0 .net "c2", 0 0, L_0x1d8cb80; 1 drivers +v0x1b64cd0_0 .net "carryin", 0 0, L_0x1d95e10; alias, 1 drivers +v0x1b64dc0_0 .net "carryout", 0 0, L_0x1d8cce0; 1 drivers +v0x1b64e60_0 .net "s1", 0 0, L_0x1d8c700; 1 drivers +v0x1b64f50_0 .net "sum", 0 0, L_0x1d8ca30; 1 drivers +S_0x1b63db0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b63b40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d8c700/d .functor XOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; +L_0x1d8c700 .delay 1 (30000,30000,30000) L_0x1d8c700/d; +L_0x1d8c7c0/d .functor AND 1, L_0x1d95c10, L_0x1d95d70, C4<1>, C4<1>; +L_0x1d8c7c0 .delay 1 (30000,30000,30000) L_0x1d8c7c0/d; +v0x1b64010_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers +v0x1b640f0_0 .net "b", 0 0, L_0x1d95d70; alias, 1 drivers +v0x1b641b0_0 .net "carryout", 0 0, L_0x1d8c7c0; alias, 1 drivers +v0x1b64250_0 .net "sum", 0 0, L_0x1d8c700; alias, 1 drivers +S_0x1b64390 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b63b40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d8ca30/d .functor XOR 1, L_0x1d8c700, L_0x1d95e10, C4<0>, C4<0>; +L_0x1d8ca30 .delay 1 (30000,30000,30000) L_0x1d8ca30/d; +L_0x1d8cb80/d .functor AND 1, L_0x1d8c700, L_0x1d95e10, C4<1>, C4<1>; +L_0x1d8cb80 .delay 1 (30000,30000,30000) L_0x1d8cb80/d; +v0x1b645f0_0 .net "a", 0 0, L_0x1d8c700; alias, 1 drivers +v0x1b64690_0 .net "b", 0 0, L_0x1d95e10; alias, 1 drivers +v0x1b64730_0 .net "carryout", 0 0, L_0x1d8cb80; alias, 1 drivers +v0x1b64800_0 .net "sum", 0 0, L_0x1d8ca30; alias, 1 drivers +S_0x1b65020 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b638c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b6a2a0_0 .net "ands", 7 0, L_0x1d937b0; 1 drivers +v0x1b6a3b0_0 .net "in", 7 0, L_0x1ebf060; alias, 1 drivers +v0x1b6a470_0 .net "out", 0 0, L_0x1d957b0; alias, 1 drivers +v0x1b6a540_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b65240 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b65020; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b67970_0 .net "A", 7 0, L_0x1ebf060; alias, 1 drivers +v0x1b67a70_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b67b30_0 .net *"_s0", 0 0, L_0x1d920d0; 1 drivers +v0x1b67bf0_0 .net *"_s12", 0 0, L_0x1d92a40; 1 drivers +v0x1b67cd0_0 .net *"_s16", 0 0, L_0x1d92da0; 1 drivers +v0x1b67e00_0 .net *"_s20", 0 0, L_0x1d930b0; 1 drivers +v0x1b67ee0_0 .net *"_s24", 0 0, L_0x1d934a0; 1 drivers +v0x1b67fc0_0 .net *"_s28", 0 0, L_0x1d93430; 1 drivers +v0x1b68060_0 .net *"_s4", 0 0, L_0x1d923e0; 1 drivers +v0x1b68190_0 .net *"_s8", 0 0, L_0x1d92730; 1 drivers +v0x1b68230_0 .net "out", 7 0, L_0x1d937b0; alias, 1 drivers +L_0x1d92190 .part L_0x1ebf060, 0, 1; +L_0x1d922f0 .part v0x1d6daa0_0, 0, 1; +L_0x1d924a0 .part L_0x1ebf060, 1, 1; +L_0x1d92690 .part v0x1d6daa0_0, 1, 1; +L_0x1d927f0 .part L_0x1ebf060, 2, 1; +L_0x1d92950 .part v0x1d6daa0_0, 2, 1; +L_0x1d92b00 .part L_0x1ebf060, 3, 1; +L_0x1d92c60 .part v0x1d6daa0_0, 3, 1; +L_0x1d92e60 .part L_0x1ebf060, 4, 1; +L_0x1d92fc0 .part v0x1d6daa0_0, 4, 1; +L_0x1d93120 .part L_0x1ebf060, 5, 1; +L_0x1d93390 .part v0x1d6daa0_0, 5, 1; +L_0x1d93560 .part L_0x1ebf060, 6, 1; +L_0x1d936c0 .part v0x1d6daa0_0, 6, 1; +LS_0x1d937b0_0_0 .concat8 [ 1 1 1 1], L_0x1d920d0, L_0x1d923e0, L_0x1d92730, L_0x1d92a40; +LS_0x1d937b0_0_4 .concat8 [ 1 1 1 1], L_0x1d92da0, L_0x1d930b0, L_0x1d934a0, L_0x1d93430; +L_0x1d937b0 .concat8 [ 4 4 0 0], LS_0x1d937b0_0_0, LS_0x1d937b0_0_4; +L_0x1d93b70 .part L_0x1ebf060, 7, 1; +L_0x1d93d60 .part v0x1d6daa0_0, 7, 1; +S_0x1b654a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b656b0 .param/l "i" 0 4 54, +C4<00>; +L_0x1d920d0/d .functor AND 1, L_0x1d92190, L_0x1d922f0, C4<1>, C4<1>; +L_0x1d920d0 .delay 1 (30000,30000,30000) L_0x1d920d0/d; +v0x1b65790_0 .net *"_s0", 0 0, L_0x1d92190; 1 drivers +v0x1b65870_0 .net *"_s1", 0 0, L_0x1d922f0; 1 drivers +S_0x1b65950 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b65b60 .param/l "i" 0 4 54, +C4<01>; +L_0x1d923e0/d .functor AND 1, L_0x1d924a0, L_0x1d92690, C4<1>, C4<1>; +L_0x1d923e0 .delay 1 (30000,30000,30000) L_0x1d923e0/d; +v0x1b65c20_0 .net *"_s0", 0 0, L_0x1d924a0; 1 drivers +v0x1b65d00_0 .net *"_s1", 0 0, L_0x1d92690; 1 drivers +S_0x1b65de0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b65ff0 .param/l "i" 0 4 54, +C4<010>; +L_0x1d92730/d .functor AND 1, L_0x1d927f0, L_0x1d92950, C4<1>, C4<1>; +L_0x1d92730 .delay 1 (30000,30000,30000) L_0x1d92730/d; +v0x1b66090_0 .net *"_s0", 0 0, L_0x1d927f0; 1 drivers +v0x1b66170_0 .net *"_s1", 0 0, L_0x1d92950; 1 drivers +S_0x1b66250 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b66460 .param/l "i" 0 4 54, +C4<011>; +L_0x1d92a40/d .functor AND 1, L_0x1d92b00, L_0x1d92c60, C4<1>, C4<1>; +L_0x1d92a40 .delay 1 (30000,30000,30000) L_0x1d92a40/d; +v0x1b66520_0 .net *"_s0", 0 0, L_0x1d92b00; 1 drivers +v0x1b66600_0 .net *"_s1", 0 0, L_0x1d92c60; 1 drivers +S_0x1b666e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b66940 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d92da0/d .functor AND 1, L_0x1d92e60, L_0x1d92fc0, C4<1>, C4<1>; +L_0x1d92da0 .delay 1 (30000,30000,30000) L_0x1d92da0/d; +v0x1b66a00_0 .net *"_s0", 0 0, L_0x1d92e60; 1 drivers +v0x1b66ae0_0 .net *"_s1", 0 0, L_0x1d92fc0; 1 drivers +S_0x1b66bc0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b66dd0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d930b0/d .functor AND 1, L_0x1d93120, L_0x1d93390, C4<1>, C4<1>; +L_0x1d930b0 .delay 1 (30000,30000,30000) L_0x1d930b0/d; +v0x1b66e90_0 .net *"_s0", 0 0, L_0x1d93120; 1 drivers +v0x1b66f70_0 .net *"_s1", 0 0, L_0x1d93390; 1 drivers +S_0x1b67050 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b67260 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d934a0/d .functor AND 1, L_0x1d93560, L_0x1d936c0, C4<1>, C4<1>; +L_0x1d934a0 .delay 1 (30000,30000,30000) L_0x1d934a0/d; +v0x1b67320_0 .net *"_s0", 0 0, L_0x1d93560; 1 drivers +v0x1b67400_0 .net *"_s1", 0 0, L_0x1d936c0; 1 drivers +S_0x1b674e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b65240; + .timescale -9 -12; +P_0x1b676f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d93430/d .functor AND 1, L_0x1d93b70, L_0x1d93d60, C4<1>, C4<1>; +L_0x1d93430 .delay 1 (30000,30000,30000) L_0x1d93430/d; +v0x1b677b0_0 .net *"_s0", 0 0, L_0x1d93b70; 1 drivers +v0x1b67890_0 .net *"_s1", 0 0, L_0x1d93d60; 1 drivers +S_0x1b682d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b65020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d957b0/d .functor OR 1, L_0x1d95870, L_0x1d95a20, C4<0>, C4<0>; +L_0x1d957b0 .delay 1 (30000,30000,30000) L_0x1d957b0/d; +v0x1b69e30_0 .net *"_s10", 0 0, L_0x1d95870; 1 drivers +v0x1b69f10_0 .net *"_s12", 0 0, L_0x1d95a20; 1 drivers +v0x1b69ff0_0 .net "in", 7 0, L_0x1d937b0; alias, 1 drivers +v0x1b6a0c0_0 .net "ors", 1 0, L_0x1d955d0; 1 drivers +v0x1b6a180_0 .net "out", 0 0, L_0x1d957b0; alias, 1 drivers +L_0x1d949a0 .part L_0x1d937b0, 0, 4; +L_0x1d955d0 .concat8 [ 1 1 0 0], L_0x1d94690, L_0x1d952c0; +L_0x1d95710 .part L_0x1d937b0, 4, 4; +L_0x1d95870 .part L_0x1d955d0, 0, 1; +L_0x1d95a20 .part L_0x1d955d0, 1, 1; +S_0x1b68490 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b682d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d93e50/d .functor OR 1, L_0x1d93f10, L_0x1d94070, C4<0>, C4<0>; +L_0x1d93e50 .delay 1 (30000,30000,30000) L_0x1d93e50/d; +L_0x1d942a0/d .functor OR 1, L_0x1d943b0, L_0x1d94510, C4<0>, C4<0>; +L_0x1d942a0 .delay 1 (30000,30000,30000) L_0x1d942a0/d; +L_0x1d94690/d .functor OR 1, L_0x1d94700, L_0x1d948b0, C4<0>, C4<0>; +L_0x1d94690 .delay 1 (30000,30000,30000) L_0x1d94690/d; +v0x1b686c0_0 .net *"_s0", 0 0, L_0x1d93e50; 1 drivers +v0x1b687c0_0 .net *"_s10", 0 0, L_0x1d943b0; 1 drivers +v0x1b688a0_0 .net *"_s12", 0 0, L_0x1d94510; 1 drivers +v0x1b68990_0 .net *"_s14", 0 0, L_0x1d94700; 1 drivers +v0x1b68a70_0 .net *"_s16", 0 0, L_0x1d948b0; 1 drivers +v0x1b68ba0_0 .net *"_s3", 0 0, L_0x1d93f10; 1 drivers +v0x1b68c80_0 .net *"_s5", 0 0, L_0x1d94070; 1 drivers +v0x1b68d60_0 .net *"_s6", 0 0, L_0x1d942a0; 1 drivers +v0x1b68e40_0 .net "in", 3 0, L_0x1d949a0; 1 drivers +v0x1b68fb0_0 .net "ors", 1 0, L_0x1d941b0; 1 drivers +v0x1b69090_0 .net "out", 0 0, L_0x1d94690; 1 drivers +L_0x1d93f10 .part L_0x1d949a0, 0, 1; +L_0x1d94070 .part L_0x1d949a0, 1, 1; +L_0x1d941b0 .concat8 [ 1 1 0 0], L_0x1d93e50, L_0x1d942a0; +L_0x1d943b0 .part L_0x1d949a0, 2, 1; +L_0x1d94510 .part L_0x1d949a0, 3, 1; +L_0x1d94700 .part L_0x1d941b0, 0, 1; +L_0x1d948b0 .part L_0x1d941b0, 1, 1; +S_0x1b691b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b682d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d94ad0/d .functor OR 1, L_0x1d94b40, L_0x1d94ca0, C4<0>, C4<0>; +L_0x1d94ad0 .delay 1 (30000,30000,30000) L_0x1d94ad0/d; +L_0x1d94ed0/d .functor OR 1, L_0x1d94fe0, L_0x1d95140, C4<0>, C4<0>; +L_0x1d94ed0 .delay 1 (30000,30000,30000) L_0x1d94ed0/d; +L_0x1d952c0/d .functor OR 1, L_0x1d95330, L_0x1d954e0, C4<0>, C4<0>; +L_0x1d952c0 .delay 1 (30000,30000,30000) L_0x1d952c0/d; +v0x1b69370_0 .net *"_s0", 0 0, L_0x1d94ad0; 1 drivers +v0x1b69470_0 .net *"_s10", 0 0, L_0x1d94fe0; 1 drivers +v0x1b69550_0 .net *"_s12", 0 0, L_0x1d95140; 1 drivers +v0x1b69610_0 .net *"_s14", 0 0, L_0x1d95330; 1 drivers +v0x1b696f0_0 .net *"_s16", 0 0, L_0x1d954e0; 1 drivers +v0x1b69820_0 .net *"_s3", 0 0, L_0x1d94b40; 1 drivers +v0x1b69900_0 .net *"_s5", 0 0, L_0x1d94ca0; 1 drivers +v0x1b699e0_0 .net *"_s6", 0 0, L_0x1d94ed0; 1 drivers +v0x1b69ac0_0 .net "in", 3 0, L_0x1d95710; 1 drivers +v0x1b69c30_0 .net "ors", 1 0, L_0x1d94de0; 1 drivers +v0x1b69d10_0 .net "out", 0 0, L_0x1d952c0; 1 drivers +L_0x1d94b40 .part L_0x1d95710, 0, 1; +L_0x1d94ca0 .part L_0x1d95710, 1, 1; +L_0x1d94de0 .concat8 [ 1 1 0 0], L_0x1d94ad0, L_0x1d94ed0; +L_0x1d94fe0 .part L_0x1d95710, 2, 1; +L_0x1d95140 .part L_0x1d95710, 3, 1; +L_0x1d95330 .part L_0x1d94de0, 0, 1; +L_0x1d954e0 .part L_0x1d94de0, 1, 1; +S_0x1b6a7f0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b638c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b6fb50_0 .net "ands", 7 0, L_0x1d8fd70; 1 drivers +v0x1b6fc60_0 .net "in", 7 0, L_0x1d8e2b0; alias, 1 drivers +v0x1b6fd20_0 .net "out", 0 0, L_0x1d91d70; alias, 1 drivers +v0x1b6fdf0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b6a970 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b6a7f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b6d0b0_0 .net "A", 7 0, L_0x1d8e2b0; alias, 1 drivers +v0x1b6d1b0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b6d270_0 .net *"_s0", 0 0, L_0x1d8e640; 1 drivers +v0x1b6d330_0 .net *"_s12", 0 0, L_0x1d8f000; 1 drivers +v0x1b6d410_0 .net *"_s16", 0 0, L_0x1d8f360; 1 drivers +v0x1b6d540_0 .net *"_s20", 0 0, L_0x1d8f730; 1 drivers +v0x1b6d620_0 .net *"_s24", 0 0, L_0x1d8fa60; 1 drivers +v0x1b6d700_0 .net *"_s28", 0 0, L_0x1d8f9f0; 1 drivers +v0x1b6d7e0_0 .net *"_s4", 0 0, L_0x1d8e9e0; 1 drivers +v0x1b6d950_0 .net *"_s8", 0 0, L_0x1d8ecf0; 1 drivers +v0x1b6da30_0 .net "out", 7 0, L_0x1d8fd70; alias, 1 drivers +L_0x1d8e750 .part L_0x1d8e2b0, 0, 1; +L_0x1d8e940 .part v0x1d6daa0_0, 0, 1; +L_0x1d8eaa0 .part L_0x1d8e2b0, 1, 1; +L_0x1d8ec00 .part v0x1d6daa0_0, 1, 1; +L_0x1d8edb0 .part L_0x1d8e2b0, 2, 1; +L_0x1d8ef10 .part v0x1d6daa0_0, 2, 1; +L_0x1d8f0c0 .part L_0x1d8e2b0, 3, 1; +L_0x1d8f220 .part v0x1d6daa0_0, 3, 1; +L_0x1d8f420 .part L_0x1d8e2b0, 4, 1; +L_0x1d8f690 .part v0x1d6daa0_0, 4, 1; +L_0x1d8f7a0 .part L_0x1d8e2b0, 5, 1; +L_0x1d8f900 .part v0x1d6daa0_0, 5, 1; +L_0x1d8fb20 .part L_0x1d8e2b0, 6, 1; +L_0x1d8fc80 .part v0x1d6daa0_0, 6, 1; +LS_0x1d8fd70_0_0 .concat8 [ 1 1 1 1], L_0x1d8e640, L_0x1d8e9e0, L_0x1d8ecf0, L_0x1d8f000; +LS_0x1d8fd70_0_4 .concat8 [ 1 1 1 1], L_0x1d8f360, L_0x1d8f730, L_0x1d8fa60, L_0x1d8f9f0; +L_0x1d8fd70 .concat8 [ 4 4 0 0], LS_0x1d8fd70_0_0, LS_0x1d8fd70_0_4; +L_0x1d90130 .part L_0x1d8e2b0, 7, 1; +L_0x1d90320 .part v0x1d6daa0_0, 7, 1; +S_0x1b6abb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6adc0 .param/l "i" 0 4 54, +C4<00>; +L_0x1d8e640/d .functor AND 1, L_0x1d8e750, L_0x1d8e940, C4<1>, C4<1>; +L_0x1d8e640 .delay 1 (30000,30000,30000) L_0x1d8e640/d; +v0x1b6aea0_0 .net *"_s0", 0 0, L_0x1d8e750; 1 drivers +v0x1b6af80_0 .net *"_s1", 0 0, L_0x1d8e940; 1 drivers +S_0x1b6b060 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6b270 .param/l "i" 0 4 54, +C4<01>; +L_0x1d8e9e0/d .functor AND 1, L_0x1d8eaa0, L_0x1d8ec00, C4<1>, C4<1>; +L_0x1d8e9e0 .delay 1 (30000,30000,30000) L_0x1d8e9e0/d; +v0x1b6b330_0 .net *"_s0", 0 0, L_0x1d8eaa0; 1 drivers +v0x1b6b410_0 .net *"_s1", 0 0, L_0x1d8ec00; 1 drivers +S_0x1b6b4f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6b730 .param/l "i" 0 4 54, +C4<010>; +L_0x1d8ecf0/d .functor AND 1, L_0x1d8edb0, L_0x1d8ef10, C4<1>, C4<1>; +L_0x1d8ecf0 .delay 1 (30000,30000,30000) L_0x1d8ecf0/d; +v0x1b6b7d0_0 .net *"_s0", 0 0, L_0x1d8edb0; 1 drivers +v0x1b6b8b0_0 .net *"_s1", 0 0, L_0x1d8ef10; 1 drivers +S_0x1b6b990 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6bba0 .param/l "i" 0 4 54, +C4<011>; +L_0x1d8f000/d .functor AND 1, L_0x1d8f0c0, L_0x1d8f220, C4<1>, C4<1>; +L_0x1d8f000 .delay 1 (30000,30000,30000) L_0x1d8f000/d; +v0x1b6bc60_0 .net *"_s0", 0 0, L_0x1d8f0c0; 1 drivers +v0x1b6bd40_0 .net *"_s1", 0 0, L_0x1d8f220; 1 drivers +S_0x1b6be20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6c080 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d8f360/d .functor AND 1, L_0x1d8f420, L_0x1d8f690, C4<1>, C4<1>; +L_0x1d8f360 .delay 1 (30000,30000,30000) L_0x1d8f360/d; +v0x1b6c140_0 .net *"_s0", 0 0, L_0x1d8f420; 1 drivers +v0x1b6c220_0 .net *"_s1", 0 0, L_0x1d8f690; 1 drivers +S_0x1b6c300 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6c510 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d8f730/d .functor AND 1, L_0x1d8f7a0, L_0x1d8f900, C4<1>, C4<1>; +L_0x1d8f730 .delay 1 (30000,30000,30000) L_0x1d8f730/d; +v0x1b6c5d0_0 .net *"_s0", 0 0, L_0x1d8f7a0; 1 drivers +v0x1b6c6b0_0 .net *"_s1", 0 0, L_0x1d8f900; 1 drivers +S_0x1b6c790 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6c9a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d8fa60/d .functor AND 1, L_0x1d8fb20, L_0x1d8fc80, C4<1>, C4<1>; +L_0x1d8fa60 .delay 1 (30000,30000,30000) L_0x1d8fa60/d; +v0x1b6ca60_0 .net *"_s0", 0 0, L_0x1d8fb20; 1 drivers +v0x1b6cb40_0 .net *"_s1", 0 0, L_0x1d8fc80; 1 drivers +S_0x1b6cc20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b6a970; + .timescale -9 -12; +P_0x1b6ce30 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d8f9f0/d .functor AND 1, L_0x1d90130, L_0x1d90320, C4<1>, C4<1>; +L_0x1d8f9f0 .delay 1 (30000,30000,30000) L_0x1d8f9f0/d; +v0x1b6cef0_0 .net *"_s0", 0 0, L_0x1d90130; 1 drivers +v0x1b6cfd0_0 .net *"_s1", 0 0, L_0x1d90320; 1 drivers +S_0x1b6db90 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b6a7f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d91d70/d .functor OR 1, L_0x1d91e30, L_0x1d91fe0, C4<0>, C4<0>; +L_0x1d91d70 .delay 1 (30000,30000,30000) L_0x1d91d70/d; +v0x1b6f6e0_0 .net *"_s10", 0 0, L_0x1d91e30; 1 drivers +v0x1b6f7c0_0 .net *"_s12", 0 0, L_0x1d91fe0; 1 drivers +v0x1b6f8a0_0 .net "in", 7 0, L_0x1d8fd70; alias, 1 drivers +v0x1b6f970_0 .net "ors", 1 0, L_0x1d91b90; 1 drivers +v0x1b6fa30_0 .net "out", 0 0, L_0x1d91d70; alias, 1 drivers +L_0x1d90f60 .part L_0x1d8fd70, 0, 4; +L_0x1d91b90 .concat8 [ 1 1 0 0], L_0x1d90c50, L_0x1d91880; +L_0x1d91cd0 .part L_0x1d8fd70, 4, 4; +L_0x1d91e30 .part L_0x1d91b90, 0, 1; +L_0x1d91fe0 .part L_0x1d91b90, 1, 1; +S_0x1b6dd50 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b6db90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d90410/d .functor OR 1, L_0x1d904d0, L_0x1d90630, C4<0>, C4<0>; +L_0x1d90410 .delay 1 (30000,30000,30000) L_0x1d90410/d; +L_0x1d90860/d .functor OR 1, L_0x1d90970, L_0x1d90ad0, C4<0>, C4<0>; +L_0x1d90860 .delay 1 (30000,30000,30000) L_0x1d90860/d; +L_0x1d90c50/d .functor OR 1, L_0x1d90cc0, L_0x1d90e70, C4<0>, C4<0>; +L_0x1d90c50 .delay 1 (30000,30000,30000) L_0x1d90c50/d; +v0x1b6dfa0_0 .net *"_s0", 0 0, L_0x1d90410; 1 drivers +v0x1b6e0a0_0 .net *"_s10", 0 0, L_0x1d90970; 1 drivers +v0x1b6e180_0 .net *"_s12", 0 0, L_0x1d90ad0; 1 drivers +v0x1b6e240_0 .net *"_s14", 0 0, L_0x1d90cc0; 1 drivers +v0x1b6e320_0 .net *"_s16", 0 0, L_0x1d90e70; 1 drivers +v0x1b6e450_0 .net *"_s3", 0 0, L_0x1d904d0; 1 drivers +v0x1b6e530_0 .net *"_s5", 0 0, L_0x1d90630; 1 drivers +v0x1b6e610_0 .net *"_s6", 0 0, L_0x1d90860; 1 drivers +v0x1b6e6f0_0 .net "in", 3 0, L_0x1d90f60; 1 drivers +v0x1b6e860_0 .net "ors", 1 0, L_0x1d90770; 1 drivers +v0x1b6e940_0 .net "out", 0 0, L_0x1d90c50; 1 drivers +L_0x1d904d0 .part L_0x1d90f60, 0, 1; +L_0x1d90630 .part L_0x1d90f60, 1, 1; +L_0x1d90770 .concat8 [ 1 1 0 0], L_0x1d90410, L_0x1d90860; +L_0x1d90970 .part L_0x1d90f60, 2, 1; +L_0x1d90ad0 .part L_0x1d90f60, 3, 1; +L_0x1d90cc0 .part L_0x1d90770, 0, 1; +L_0x1d90e70 .part L_0x1d90770, 1, 1; +S_0x1b6ea60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b6db90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d91090/d .functor OR 1, L_0x1d91100, L_0x1d91260, C4<0>, C4<0>; +L_0x1d91090 .delay 1 (30000,30000,30000) L_0x1d91090/d; +L_0x1d91490/d .functor OR 1, L_0x1d915a0, L_0x1d91700, C4<0>, C4<0>; +L_0x1d91490 .delay 1 (30000,30000,30000) L_0x1d91490/d; +L_0x1d91880/d .functor OR 1, L_0x1d918f0, L_0x1d91aa0, C4<0>, C4<0>; +L_0x1d91880 .delay 1 (30000,30000,30000) L_0x1d91880/d; +v0x1b6ec20_0 .net *"_s0", 0 0, L_0x1d91090; 1 drivers +v0x1b6ed20_0 .net *"_s10", 0 0, L_0x1d915a0; 1 drivers +v0x1b6ee00_0 .net *"_s12", 0 0, L_0x1d91700; 1 drivers +v0x1b6eec0_0 .net *"_s14", 0 0, L_0x1d918f0; 1 drivers +v0x1b6efa0_0 .net *"_s16", 0 0, L_0x1d91aa0; 1 drivers +v0x1b6f0d0_0 .net *"_s3", 0 0, L_0x1d91100; 1 drivers +v0x1b6f1b0_0 .net *"_s5", 0 0, L_0x1d91260; 1 drivers +v0x1b6f290_0 .net *"_s6", 0 0, L_0x1d91490; 1 drivers +v0x1b6f370_0 .net "in", 3 0, L_0x1d91cd0; 1 drivers +v0x1b6f4e0_0 .net "ors", 1 0, L_0x1d913a0; 1 drivers +v0x1b6f5c0_0 .net "out", 0 0, L_0x1d91880; 1 drivers +L_0x1d91100 .part L_0x1d91cd0, 0, 1; +L_0x1d91260 .part L_0x1d91cd0, 1, 1; +L_0x1d913a0 .concat8 [ 1 1 0 0], L_0x1d91090, L_0x1d91490; +L_0x1d915a0 .part L_0x1d91cd0, 2, 1; +L_0x1d91700 .part L_0x1d91cd0, 3, 1; +L_0x1d918f0 .part L_0x1d913a0, 0, 1; +L_0x1d91aa0 .part L_0x1d913a0, 1, 1; +S_0x1b6fed0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b638c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1d8d620/d .functor XNOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; +L_0x1d8d620 .delay 1 (20000,20000,20000) L_0x1d8d620/d; +L_0x1d8d890/d .functor AND 1, L_0x1d95c10, L_0x1d8c510, C4<1>, C4<1>; +L_0x1d8d890 .delay 1 (30000,30000,30000) L_0x1d8d890/d; +L_0x1d8d900/d .functor AND 1, L_0x1d8d620, L_0x1d95e10, C4<1>, C4<1>; +L_0x1d8d900 .delay 1 (30000,30000,30000) L_0x1d8d900/d; +L_0x1d8da60/d .functor OR 1, L_0x1d8d900, L_0x1d8d890, C4<0>, C4<0>; +L_0x1d8da60 .delay 1 (30000,30000,30000) L_0x1d8da60/d; +v0x1b70180_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers +v0x1b70270_0 .net "a_", 0 0, L_0x1d8c400; alias, 1 drivers +v0x1b70330_0 .net "b", 0 0, L_0x1d95d70; alias, 1 drivers +v0x1b70420_0 .net "b_", 0 0, L_0x1d8c510; alias, 1 drivers +v0x1b704c0_0 .net "carryin", 0 0, L_0x1d95e10; alias, 1 drivers +v0x1b70600_0 .net "eq", 0 0, L_0x1d8d620; 1 drivers +v0x1b706c0_0 .net "lt", 0 0, L_0x1d8d890; 1 drivers +v0x1b70780_0 .net "out", 0 0, L_0x1d8da60; 1 drivers +v0x1b70840_0 .net "w0", 0 0, L_0x1d8d900; 1 drivers +S_0x1b70a90 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b638c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d8d400/d .functor OR 1, L_0x1d8cf00, L_0x1b71cf0, C4<0>, C4<0>; +L_0x1d8d400 .delay 1 (30000,30000,30000) L_0x1d8d400/d; +v0x1b71880_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers +v0x1b719d0_0 .net "b", 0 0, L_0x1d8c510; alias, 1 drivers +v0x1b71a90_0 .net "c1", 0 0, L_0x1d8cf00; 1 drivers +v0x1b71b30_0 .net "c2", 0 0, L_0x1b71cf0; 1 drivers +v0x1b71c00_0 .net "carryin", 0 0, L_0x1d95e10; alias, 1 drivers +v0x1b71d80_0 .net "carryout", 0 0, L_0x1d8d400; 1 drivers +v0x1b71e20_0 .net "s1", 0 0, L_0x1d8ce40; 1 drivers +v0x1b71ec0_0 .net "sum", 0 0, L_0x1d8d060; 1 drivers +S_0x1b70ce0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b70a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d8ce40/d .functor XOR 1, L_0x1d95c10, L_0x1d8c510, C4<0>, C4<0>; +L_0x1d8ce40 .delay 1 (30000,30000,30000) L_0x1d8ce40/d; +L_0x1d8cf00/d .functor AND 1, L_0x1d95c10, L_0x1d8c510, C4<1>, C4<1>; +L_0x1d8cf00 .delay 1 (30000,30000,30000) L_0x1d8cf00/d; +v0x1b70f40_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers +v0x1b71000_0 .net "b", 0 0, L_0x1d8c510; alias, 1 drivers +v0x1b710c0_0 .net "carryout", 0 0, L_0x1d8cf00; alias, 1 drivers +v0x1b71160_0 .net "sum", 0 0, L_0x1d8ce40; alias, 1 drivers +S_0x1b71290 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b70a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d8d060/d .functor XOR 1, L_0x1d8ce40, L_0x1d95e10, C4<0>, C4<0>; +L_0x1d8d060 .delay 1 (30000,30000,30000) L_0x1d8d060/d; +L_0x1b71cf0/d .functor AND 1, L_0x1d8ce40, L_0x1d95e10, C4<1>, C4<1>; +L_0x1b71cf0 .delay 1 (30000,30000,30000) L_0x1b71cf0/d; +v0x1b714f0_0 .net "a", 0 0, L_0x1d8ce40; alias, 1 drivers +v0x1b715c0_0 .net "b", 0 0, L_0x1d95e10; alias, 1 drivers +v0x1b71660_0 .net "carryout", 0 0, L_0x1b71cf0; alias, 1 drivers +v0x1b71730_0 .net "sum", 0 0, L_0x1d8d060; alias, 1 drivers +S_0x1b732e0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b635f0; + .timescale -9 -12; +L_0x7f72592da378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da3c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d95f40/d .functor OR 1, L_0x7f72592da378, L_0x7f72592da3c0, C4<0>, C4<0>; +L_0x1d95f40 .delay 1 (30000,30000,30000) L_0x1d95f40/d; +v0x1b734d0_0 .net/2u *"_s0", 0 0, L_0x7f72592da378; 1 drivers +v0x1b735b0_0 .net/2u *"_s2", 0 0, L_0x7f72592da3c0; 1 drivers +S_0x1b73690 .scope generate, "alu_slices[4]" "alu_slices[4]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1b738f0 .param/l "i" 0 3 37, +C4<0100>; +S_0x1b739b0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b73690; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1d96050/d .functor NOT 1, L_0x1d9f810, C4<0>, C4<0>, C4<0>; +L_0x1d96050 .delay 1 (10000,10000,10000) L_0x1d96050/d; +L_0x1d96160/d .functor NOT 1, L_0x1d9f970, C4<0>, C4<0>, C4<0>; +L_0x1d96160 .delay 1 (10000,10000,10000) L_0x1d96160/d; +L_0x1d971b0/d .functor XOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; +L_0x1d971b0 .delay 1 (30000,30000,30000) L_0x1d971b0/d; +L_0x7f72592da408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d97860/d .functor OR 1, L_0x7f72592da408, L_0x7f72592da450, C4<0>, C4<0>; +L_0x1d97860 .delay 1 (30000,30000,30000) L_0x1d97860/d; +L_0x1d97a60/d .functor AND 1, L_0x1d9f810, L_0x1d9f970, C4<1>, C4<1>; +L_0x1d97a60 .delay 1 (30000,30000,30000) L_0x1d97a60/d; +L_0x1d97b20/d .functor NAND 1, L_0x1d9f810, L_0x1d9f970, C4<1>, C4<1>; +L_0x1d97b20 .delay 1 (20000,20000,20000) L_0x1d97b20/d; +L_0x1d97c80/d .functor XOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; +L_0x1d97c80 .delay 1 (20000,20000,20000) L_0x1d97c80/d; +L_0x1d98130/d .functor OR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; +L_0x1d98130 .delay 1 (30000,30000,30000) L_0x1d98130/d; +L_0x1d9f710/d .functor NOT 1, L_0x1d9b970, C4<0>, C4<0>, C4<0>; +L_0x1d9f710 .delay 1 (10000,10000,10000) L_0x1d9f710/d; +v0x1b820b0_0 .net "A", 0 0, L_0x1d9f810; 1 drivers +v0x1b82170_0 .net "A_", 0 0, L_0x1d96050; 1 drivers +v0x1b82230_0 .net "B", 0 0, L_0x1d9f970; 1 drivers +v0x1b82300_0 .net "B_", 0 0, L_0x1d96160; 1 drivers +v0x1b823a0_0 .net *"_s12", 0 0, L_0x1d97860; 1 drivers +v0x1b82490_0 .net/2s *"_s14", 0 0, L_0x7f72592da408; 1 drivers +v0x1b82550_0 .net/2s *"_s16", 0 0, L_0x7f72592da450; 1 drivers +v0x1b82630_0 .net *"_s18", 0 0, L_0x1d97a60; 1 drivers +v0x1b82710_0 .net *"_s20", 0 0, L_0x1d97b20; 1 drivers +v0x1b82880_0 .net *"_s22", 0 0, L_0x1d97c80; 1 drivers +v0x1b82960_0 .net *"_s24", 0 0, L_0x1d98130; 1 drivers +o0x7f725935f808 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1b82a40_0 name=_s30 +o0x7f725935f838 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1b82b20_0 name=_s32 +v0x1b82c00_0 .net *"_s8", 0 0, L_0x1d971b0; 1 drivers +v0x1b82ce0_0 .net "carryin", 0 0, L_0x1d9fa10; 1 drivers +v0x1b82d80_0 .net "carryout", 0 0, L_0x1d9f3b0; 1 drivers +v0x1b82e20_0 .net "carryouts", 7 0, L_0x1ebf1f0; 1 drivers +v0x1b82fd0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b83070_0 .net "result", 0 0, L_0x1d9b970; 1 drivers +v0x1b83160_0 .net "results", 7 0, L_0x1d97f00; 1 drivers +v0x1b83270_0 .net "zero", 0 0, L_0x1d9f710; 1 drivers +LS_0x1d97f00_0_0 .concat8 [ 1 1 1 1], L_0x1d96680, L_0x1d96cb0, L_0x1d971b0, L_0x1d97860; +LS_0x1d97f00_0_4 .concat8 [ 1 1 1 1], L_0x1d97a60, L_0x1d97b20, L_0x1d97c80, L_0x1d98130; +L_0x1d97f00 .concat8 [ 4 4 0 0], LS_0x1d97f00_0_0, LS_0x1d97f00_0_4; +LS_0x1ebf1f0_0_0 .concat [ 1 1 1 1], L_0x1d96930, L_0x1d97050, o0x7f725935f808, L_0x1d976b0; +LS_0x1ebf1f0_0_4 .concat [ 4 0 0 0], o0x7f725935f838; +L_0x1ebf1f0 .concat [ 4 4 0 0], LS_0x1ebf1f0_0_0, LS_0x1ebf1f0_0_4; +S_0x1b73c30 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b739b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d96930/d .functor OR 1, L_0x1d96410, L_0x1d967d0, C4<0>, C4<0>; +L_0x1d96930 .delay 1 (30000,30000,30000) L_0x1d96930/d; +v0x1b74a30_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers +v0x1b74af0_0 .net "b", 0 0, L_0x1d9f970; alias, 1 drivers +v0x1b74bc0_0 .net "c1", 0 0, L_0x1d96410; 1 drivers +v0x1b74cc0_0 .net "c2", 0 0, L_0x1d967d0; 1 drivers +v0x1b74d90_0 .net "carryin", 0 0, L_0x1d9fa10; alias, 1 drivers +v0x1b74e80_0 .net "carryout", 0 0, L_0x1d96930; 1 drivers +v0x1b74f20_0 .net "s1", 0 0, L_0x1d96350; 1 drivers +v0x1b75010_0 .net "sum", 0 0, L_0x1d96680; 1 drivers +S_0x1b73ea0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b73c30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d96350/d .functor XOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; +L_0x1d96350 .delay 1 (30000,30000,30000) L_0x1d96350/d; +L_0x1d96410/d .functor AND 1, L_0x1d9f810, L_0x1d9f970, C4<1>, C4<1>; +L_0x1d96410 .delay 1 (30000,30000,30000) L_0x1d96410/d; +v0x1b74100_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers +v0x1b741e0_0 .net "b", 0 0, L_0x1d9f970; alias, 1 drivers +v0x1b742a0_0 .net "carryout", 0 0, L_0x1d96410; alias, 1 drivers +v0x1b74340_0 .net "sum", 0 0, L_0x1d96350; alias, 1 drivers +S_0x1b74480 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b73c30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d96680/d .functor XOR 1, L_0x1d96350, L_0x1d9fa10, C4<0>, C4<0>; +L_0x1d96680 .delay 1 (30000,30000,30000) L_0x1d96680/d; +L_0x1d967d0/d .functor AND 1, L_0x1d96350, L_0x1d9fa10, C4<1>, C4<1>; +L_0x1d967d0 .delay 1 (30000,30000,30000) L_0x1d967d0/d; +v0x1b746e0_0 .net "a", 0 0, L_0x1d96350; alias, 1 drivers +v0x1b74780_0 .net "b", 0 0, L_0x1d9fa10; alias, 1 drivers +v0x1b74820_0 .net "carryout", 0 0, L_0x1d967d0; alias, 1 drivers +v0x1b748c0_0 .net "sum", 0 0, L_0x1d96680; alias, 1 drivers +S_0x1b750e0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b739b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b7a4d0_0 .net "ands", 7 0, L_0x1d9d3b0; 1 drivers +v0x1b7a5e0_0 .net "in", 7 0, L_0x1ebf1f0; alias, 1 drivers +v0x1b7a6a0_0 .net "out", 0 0, L_0x1d9f3b0; alias, 1 drivers +v0x1b7a770_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b75300 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b750e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b77a30_0 .net "A", 7 0, L_0x1ebf1f0; alias, 1 drivers +v0x1b77b30_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b77bf0_0 .net *"_s0", 0 0, L_0x1d9bcd0; 1 drivers +v0x1b77cb0_0 .net *"_s12", 0 0, L_0x1d9c640; 1 drivers +v0x1b77d90_0 .net *"_s16", 0 0, L_0x1d9c9a0; 1 drivers +v0x1b77ec0_0 .net *"_s20", 0 0, L_0x1d9ccb0; 1 drivers +v0x1b77fa0_0 .net *"_s24", 0 0, L_0x1d9d0a0; 1 drivers +v0x1b78080_0 .net *"_s28", 0 0, L_0x1d9d030; 1 drivers +v0x1b78160_0 .net *"_s4", 0 0, L_0x1d9bfe0; 1 drivers +v0x1b782d0_0 .net *"_s8", 0 0, L_0x1d9c330; 1 drivers +v0x1b783b0_0 .net "out", 7 0, L_0x1d9d3b0; alias, 1 drivers +L_0x1d9bd90 .part L_0x1ebf1f0, 0, 1; +L_0x1d9bef0 .part v0x1d6daa0_0, 0, 1; +L_0x1d9c0a0 .part L_0x1ebf1f0, 1, 1; +L_0x1d9c290 .part v0x1d6daa0_0, 1, 1; +L_0x1d9c3f0 .part L_0x1ebf1f0, 2, 1; +L_0x1d9c550 .part v0x1d6daa0_0, 2, 1; +L_0x1d9c700 .part L_0x1ebf1f0, 3, 1; +L_0x1d9c860 .part v0x1d6daa0_0, 3, 1; +L_0x1d9ca60 .part L_0x1ebf1f0, 4, 1; +L_0x1d9cbc0 .part v0x1d6daa0_0, 4, 1; +L_0x1d9cd20 .part L_0x1ebf1f0, 5, 1; +L_0x1d9cf90 .part v0x1d6daa0_0, 5, 1; +L_0x1d9d160 .part L_0x1ebf1f0, 6, 1; +L_0x1d9d2c0 .part v0x1d6daa0_0, 6, 1; +LS_0x1d9d3b0_0_0 .concat8 [ 1 1 1 1], L_0x1d9bcd0, L_0x1d9bfe0, L_0x1d9c330, L_0x1d9c640; +LS_0x1d9d3b0_0_4 .concat8 [ 1 1 1 1], L_0x1d9c9a0, L_0x1d9ccb0, L_0x1d9d0a0, L_0x1d9d030; +L_0x1d9d3b0 .concat8 [ 4 4 0 0], LS_0x1d9d3b0_0_0, LS_0x1d9d3b0_0_4; +L_0x1d9d770 .part L_0x1ebf1f0, 7, 1; +L_0x1d9d960 .part v0x1d6daa0_0, 7, 1; +S_0x1b75560 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b75770 .param/l "i" 0 4 54, +C4<00>; +L_0x1d9bcd0/d .functor AND 1, L_0x1d9bd90, L_0x1d9bef0, C4<1>, C4<1>; +L_0x1d9bcd0 .delay 1 (30000,30000,30000) L_0x1d9bcd0/d; +v0x1b75850_0 .net *"_s0", 0 0, L_0x1d9bd90; 1 drivers +v0x1b75930_0 .net *"_s1", 0 0, L_0x1d9bef0; 1 drivers +S_0x1b75a10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b75c20 .param/l "i" 0 4 54, +C4<01>; +L_0x1d9bfe0/d .functor AND 1, L_0x1d9c0a0, L_0x1d9c290, C4<1>, C4<1>; +L_0x1d9bfe0 .delay 1 (30000,30000,30000) L_0x1d9bfe0/d; +v0x1b75ce0_0 .net *"_s0", 0 0, L_0x1d9c0a0; 1 drivers +v0x1b75dc0_0 .net *"_s1", 0 0, L_0x1d9c290; 1 drivers +S_0x1b75ea0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b760b0 .param/l "i" 0 4 54, +C4<010>; +L_0x1d9c330/d .functor AND 1, L_0x1d9c3f0, L_0x1d9c550, C4<1>, C4<1>; +L_0x1d9c330 .delay 1 (30000,30000,30000) L_0x1d9c330/d; +v0x1b76150_0 .net *"_s0", 0 0, L_0x1d9c3f0; 1 drivers +v0x1b76230_0 .net *"_s1", 0 0, L_0x1d9c550; 1 drivers +S_0x1b76310 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b76520 .param/l "i" 0 4 54, +C4<011>; +L_0x1d9c640/d .functor AND 1, L_0x1d9c700, L_0x1d9c860, C4<1>, C4<1>; +L_0x1d9c640 .delay 1 (30000,30000,30000) L_0x1d9c640/d; +v0x1b765e0_0 .net *"_s0", 0 0, L_0x1d9c700; 1 drivers +v0x1b766c0_0 .net *"_s1", 0 0, L_0x1d9c860; 1 drivers +S_0x1b767a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b76a00 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d9c9a0/d .functor AND 1, L_0x1d9ca60, L_0x1d9cbc0, C4<1>, C4<1>; +L_0x1d9c9a0 .delay 1 (30000,30000,30000) L_0x1d9c9a0/d; +v0x1b76ac0_0 .net *"_s0", 0 0, L_0x1d9ca60; 1 drivers +v0x1b76ba0_0 .net *"_s1", 0 0, L_0x1d9cbc0; 1 drivers +S_0x1b76c80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b76e90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d9ccb0/d .functor AND 1, L_0x1d9cd20, L_0x1d9cf90, C4<1>, C4<1>; +L_0x1d9ccb0 .delay 1 (30000,30000,30000) L_0x1d9ccb0/d; +v0x1b76f50_0 .net *"_s0", 0 0, L_0x1d9cd20; 1 drivers +v0x1b77030_0 .net *"_s1", 0 0, L_0x1d9cf90; 1 drivers +S_0x1b77110 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b77320 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d9d0a0/d .functor AND 1, L_0x1d9d160, L_0x1d9d2c0, C4<1>, C4<1>; +L_0x1d9d0a0 .delay 1 (30000,30000,30000) L_0x1d9d0a0/d; +v0x1b773e0_0 .net *"_s0", 0 0, L_0x1d9d160; 1 drivers +v0x1b774c0_0 .net *"_s1", 0 0, L_0x1d9d2c0; 1 drivers +S_0x1b775a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b75300; + .timescale -9 -12; +P_0x1b777b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d9d030/d .functor AND 1, L_0x1d9d770, L_0x1d9d960, C4<1>, C4<1>; +L_0x1d9d030 .delay 1 (30000,30000,30000) L_0x1d9d030/d; +v0x1b77870_0 .net *"_s0", 0 0, L_0x1d9d770; 1 drivers +v0x1b77950_0 .net *"_s1", 0 0, L_0x1d9d960; 1 drivers +S_0x1b78510 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b750e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d9f3b0/d .functor OR 1, L_0x1d9f470, L_0x1d9f620, C4<0>, C4<0>; +L_0x1d9f3b0 .delay 1 (30000,30000,30000) L_0x1d9f3b0/d; +v0x1b7a060_0 .net *"_s10", 0 0, L_0x1d9f470; 1 drivers +v0x1b7a140_0 .net *"_s12", 0 0, L_0x1d9f620; 1 drivers +v0x1b7a220_0 .net "in", 7 0, L_0x1d9d3b0; alias, 1 drivers +v0x1b7a2f0_0 .net "ors", 1 0, L_0x1d9f1d0; 1 drivers +v0x1b7a3b0_0 .net "out", 0 0, L_0x1d9f3b0; alias, 1 drivers +L_0x1d9e5a0 .part L_0x1d9d3b0, 0, 4; +L_0x1d9f1d0 .concat8 [ 1 1 0 0], L_0x1d9e290, L_0x1d9eec0; +L_0x1d9f310 .part L_0x1d9d3b0, 4, 4; +L_0x1d9f470 .part L_0x1d9f1d0, 0, 1; +L_0x1d9f620 .part L_0x1d9f1d0, 1, 1; +S_0x1b786d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b78510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d9da50/d .functor OR 1, L_0x1d9db10, L_0x1d9dc70, C4<0>, C4<0>; +L_0x1d9da50 .delay 1 (30000,30000,30000) L_0x1d9da50/d; +L_0x1d9dea0/d .functor OR 1, L_0x1d9dfb0, L_0x1d9e110, C4<0>, C4<0>; +L_0x1d9dea0 .delay 1 (30000,30000,30000) L_0x1d9dea0/d; +L_0x1d9e290/d .functor OR 1, L_0x1d9e300, L_0x1d9e4b0, C4<0>, C4<0>; +L_0x1d9e290 .delay 1 (30000,30000,30000) L_0x1d9e290/d; +v0x1b78920_0 .net *"_s0", 0 0, L_0x1d9da50; 1 drivers +v0x1b78a20_0 .net *"_s10", 0 0, L_0x1d9dfb0; 1 drivers +v0x1b78b00_0 .net *"_s12", 0 0, L_0x1d9e110; 1 drivers +v0x1b78bc0_0 .net *"_s14", 0 0, L_0x1d9e300; 1 drivers +v0x1b78ca0_0 .net *"_s16", 0 0, L_0x1d9e4b0; 1 drivers +v0x1b78dd0_0 .net *"_s3", 0 0, L_0x1d9db10; 1 drivers +v0x1b78eb0_0 .net *"_s5", 0 0, L_0x1d9dc70; 1 drivers +v0x1b78f90_0 .net *"_s6", 0 0, L_0x1d9dea0; 1 drivers +v0x1b79070_0 .net "in", 3 0, L_0x1d9e5a0; 1 drivers +v0x1b791e0_0 .net "ors", 1 0, L_0x1d9ddb0; 1 drivers +v0x1b792c0_0 .net "out", 0 0, L_0x1d9e290; 1 drivers +L_0x1d9db10 .part L_0x1d9e5a0, 0, 1; +L_0x1d9dc70 .part L_0x1d9e5a0, 1, 1; +L_0x1d9ddb0 .concat8 [ 1 1 0 0], L_0x1d9da50, L_0x1d9dea0; +L_0x1d9dfb0 .part L_0x1d9e5a0, 2, 1; +L_0x1d9e110 .part L_0x1d9e5a0, 3, 1; +L_0x1d9e300 .part L_0x1d9ddb0, 0, 1; +L_0x1d9e4b0 .part L_0x1d9ddb0, 1, 1; +S_0x1b793e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b78510; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d9e6d0/d .functor OR 1, L_0x1d9e740, L_0x1d9e8a0, C4<0>, C4<0>; +L_0x1d9e6d0 .delay 1 (30000,30000,30000) L_0x1d9e6d0/d; +L_0x1d9ead0/d .functor OR 1, L_0x1d9ebe0, L_0x1d9ed40, C4<0>, C4<0>; +L_0x1d9ead0 .delay 1 (30000,30000,30000) L_0x1d9ead0/d; +L_0x1d9eec0/d .functor OR 1, L_0x1d9ef30, L_0x1d9f0e0, C4<0>, C4<0>; +L_0x1d9eec0 .delay 1 (30000,30000,30000) L_0x1d9eec0/d; +v0x1b795a0_0 .net *"_s0", 0 0, L_0x1d9e6d0; 1 drivers +v0x1b796a0_0 .net *"_s10", 0 0, L_0x1d9ebe0; 1 drivers +v0x1b79780_0 .net *"_s12", 0 0, L_0x1d9ed40; 1 drivers +v0x1b79840_0 .net *"_s14", 0 0, L_0x1d9ef30; 1 drivers +v0x1b79920_0 .net *"_s16", 0 0, L_0x1d9f0e0; 1 drivers +v0x1b79a50_0 .net *"_s3", 0 0, L_0x1d9e740; 1 drivers +v0x1b79b30_0 .net *"_s5", 0 0, L_0x1d9e8a0; 1 drivers +v0x1b79c10_0 .net *"_s6", 0 0, L_0x1d9ead0; 1 drivers +v0x1b79cf0_0 .net "in", 3 0, L_0x1d9f310; 1 drivers +v0x1b79e60_0 .net "ors", 1 0, L_0x1d9e9e0; 1 drivers +v0x1b79f40_0 .net "out", 0 0, L_0x1d9eec0; 1 drivers +L_0x1d9e740 .part L_0x1d9f310, 0, 1; +L_0x1d9e8a0 .part L_0x1d9f310, 1, 1; +L_0x1d9e9e0 .concat8 [ 1 1 0 0], L_0x1d9e6d0, L_0x1d9ead0; +L_0x1d9ebe0 .part L_0x1d9f310, 2, 1; +L_0x1d9ed40 .part L_0x1d9f310, 3, 1; +L_0x1d9ef30 .part L_0x1d9e9e0, 0, 1; +L_0x1d9f0e0 .part L_0x1d9e9e0, 1, 1; +S_0x1b7a850 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b739b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b7fc80_0 .net "ands", 7 0, L_0x1d99970; 1 drivers +v0x1b7fd90_0 .net "in", 7 0, L_0x1d97f00; alias, 1 drivers +v0x1b7fe50_0 .net "out", 0 0, L_0x1d9b970; alias, 1 drivers +v0x1b7ff20_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b7aaa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b7a850; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b7d1e0_0 .net "A", 7 0, L_0x1d97f00; alias, 1 drivers +v0x1b7d2e0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b7d3a0_0 .net *"_s0", 0 0, L_0x1d98290; 1 drivers +v0x1b7d460_0 .net *"_s12", 0 0, L_0x1d98c50; 1 drivers +v0x1b7d540_0 .net *"_s16", 0 0, L_0x1d85fc0; 1 drivers +v0x1b7d670_0 .net *"_s20", 0 0, L_0x1d992b0; 1 drivers +v0x1b7d750_0 .net *"_s24", 0 0, L_0x1d995e0; 1 drivers +v0x1b7d830_0 .net *"_s28", 0 0, L_0x1d99570; 1 drivers +v0x1b7d910_0 .net *"_s4", 0 0, L_0x1d98630; 1 drivers +v0x1b7da80_0 .net *"_s8", 0 0, L_0x1d98940; 1 drivers +v0x1b7db60_0 .net "out", 7 0, L_0x1d99970; alias, 1 drivers +L_0x1d983a0 .part L_0x1d97f00, 0, 1; +L_0x1d98590 .part v0x1d6daa0_0, 0, 1; +L_0x1d986f0 .part L_0x1d97f00, 1, 1; +L_0x1d98850 .part v0x1d6daa0_0, 1, 1; +L_0x1d98a00 .part L_0x1d97f00, 2, 1; +L_0x1d98b60 .part v0x1d6daa0_0, 2, 1; +L_0x1d98d10 .part L_0x1d97f00, 3, 1; +L_0x1d98e70 .part v0x1d6daa0_0, 3, 1; +L_0x1d98fb0 .part L_0x1d97f00, 4, 1; +L_0x1d991b0 .part v0x1d6daa0_0, 4, 1; +L_0x1d99320 .part L_0x1d97f00, 5, 1; +L_0x1d99480 .part v0x1d6daa0_0, 5, 1; +L_0x1d996a0 .part L_0x1d97f00, 6, 1; +L_0x1d99800 .part v0x1d6daa0_0, 6, 1; +LS_0x1d99970_0_0 .concat8 [ 1 1 1 1], L_0x1d98290, L_0x1d98630, L_0x1d98940, L_0x1d98c50; +LS_0x1d99970_0_4 .concat8 [ 1 1 1 1], L_0x1d85fc0, L_0x1d992b0, L_0x1d995e0, L_0x1d99570; +L_0x1d99970 .concat8 [ 4 4 0 0], LS_0x1d99970_0_0, LS_0x1d99970_0_4; +L_0x1d99d30 .part L_0x1d97f00, 7, 1; +L_0x1d99f20 .part v0x1d6daa0_0, 7, 1; +S_0x1b7ace0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7aef0 .param/l "i" 0 4 54, +C4<00>; +L_0x1d98290/d .functor AND 1, L_0x1d983a0, L_0x1d98590, C4<1>, C4<1>; +L_0x1d98290 .delay 1 (30000,30000,30000) L_0x1d98290/d; +v0x1b7afd0_0 .net *"_s0", 0 0, L_0x1d983a0; 1 drivers +v0x1b7b0b0_0 .net *"_s1", 0 0, L_0x1d98590; 1 drivers +S_0x1b7b190 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7b3a0 .param/l "i" 0 4 54, +C4<01>; +L_0x1d98630/d .functor AND 1, L_0x1d986f0, L_0x1d98850, C4<1>, C4<1>; +L_0x1d98630 .delay 1 (30000,30000,30000) L_0x1d98630/d; +v0x1b7b460_0 .net *"_s0", 0 0, L_0x1d986f0; 1 drivers +v0x1b7b540_0 .net *"_s1", 0 0, L_0x1d98850; 1 drivers +S_0x1b7b620 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7b860 .param/l "i" 0 4 54, +C4<010>; +L_0x1d98940/d .functor AND 1, L_0x1d98a00, L_0x1d98b60, C4<1>, C4<1>; +L_0x1d98940 .delay 1 (30000,30000,30000) L_0x1d98940/d; +v0x1b7b900_0 .net *"_s0", 0 0, L_0x1d98a00; 1 drivers +v0x1b7b9e0_0 .net *"_s1", 0 0, L_0x1d98b60; 1 drivers +S_0x1b7bac0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7bcd0 .param/l "i" 0 4 54, +C4<011>; +L_0x1d98c50/d .functor AND 1, L_0x1d98d10, L_0x1d98e70, C4<1>, C4<1>; +L_0x1d98c50 .delay 1 (30000,30000,30000) L_0x1d98c50/d; +v0x1b7bd90_0 .net *"_s0", 0 0, L_0x1d98d10; 1 drivers +v0x1b7be70_0 .net *"_s1", 0 0, L_0x1d98e70; 1 drivers +S_0x1b7bf50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7c1b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1d85fc0/d .functor AND 1, L_0x1d98fb0, L_0x1d991b0, C4<1>, C4<1>; +L_0x1d85fc0 .delay 1 (30000,30000,30000) L_0x1d85fc0/d; +v0x1b7c270_0 .net *"_s0", 0 0, L_0x1d98fb0; 1 drivers +v0x1b7c350_0 .net *"_s1", 0 0, L_0x1d991b0; 1 drivers +S_0x1b7c430 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7c640 .param/l "i" 0 4 54, +C4<0101>; +L_0x1d992b0/d .functor AND 1, L_0x1d99320, L_0x1d99480, C4<1>, C4<1>; +L_0x1d992b0 .delay 1 (30000,30000,30000) L_0x1d992b0/d; +v0x1b7c700_0 .net *"_s0", 0 0, L_0x1d99320; 1 drivers +v0x1b7c7e0_0 .net *"_s1", 0 0, L_0x1d99480; 1 drivers +S_0x1b7c8c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7cad0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1d995e0/d .functor AND 1, L_0x1d996a0, L_0x1d99800, C4<1>, C4<1>; +L_0x1d995e0 .delay 1 (30000,30000,30000) L_0x1d995e0/d; +v0x1b7cb90_0 .net *"_s0", 0 0, L_0x1d996a0; 1 drivers +v0x1b7cc70_0 .net *"_s1", 0 0, L_0x1d99800; 1 drivers +S_0x1b7cd50 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b7aaa0; + .timescale -9 -12; +P_0x1b7cf60 .param/l "i" 0 4 54, +C4<0111>; +L_0x1d99570/d .functor AND 1, L_0x1d99d30, L_0x1d99f20, C4<1>, C4<1>; +L_0x1d99570 .delay 1 (30000,30000,30000) L_0x1d99570/d; +v0x1b7d020_0 .net *"_s0", 0 0, L_0x1d99d30; 1 drivers +v0x1b7d100_0 .net *"_s1", 0 0, L_0x1d99f20; 1 drivers +S_0x1b7dcc0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b7a850; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1d9b970/d .functor OR 1, L_0x1d9ba30, L_0x1d9bbe0, C4<0>, C4<0>; +L_0x1d9b970 .delay 1 (30000,30000,30000) L_0x1d9b970/d; +v0x1b7f810_0 .net *"_s10", 0 0, L_0x1d9ba30; 1 drivers +v0x1b7f8f0_0 .net *"_s12", 0 0, L_0x1d9bbe0; 1 drivers +v0x1b7f9d0_0 .net "in", 7 0, L_0x1d99970; alias, 1 drivers +v0x1b7faa0_0 .net "ors", 1 0, L_0x1d9b790; 1 drivers +v0x1b7fb60_0 .net "out", 0 0, L_0x1d9b970; alias, 1 drivers +L_0x1d9ab60 .part L_0x1d99970, 0, 4; +L_0x1d9b790 .concat8 [ 1 1 0 0], L_0x1d9a850, L_0x1d9b480; +L_0x1d9b8d0 .part L_0x1d99970, 4, 4; +L_0x1d9ba30 .part L_0x1d9b790, 0, 1; +L_0x1d9bbe0 .part L_0x1d9b790, 1, 1; +S_0x1b7de80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b7dcc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d9a010/d .functor OR 1, L_0x1d9a0d0, L_0x1d9a230, C4<0>, C4<0>; +L_0x1d9a010 .delay 1 (30000,30000,30000) L_0x1d9a010/d; +L_0x1d9a460/d .functor OR 1, L_0x1d9a570, L_0x1d9a6d0, C4<0>, C4<0>; +L_0x1d9a460 .delay 1 (30000,30000,30000) L_0x1d9a460/d; +L_0x1d9a850/d .functor OR 1, L_0x1d9a8c0, L_0x1d9aa70, C4<0>, C4<0>; +L_0x1d9a850 .delay 1 (30000,30000,30000) L_0x1d9a850/d; +v0x1b7e0d0_0 .net *"_s0", 0 0, L_0x1d9a010; 1 drivers +v0x1b7e1d0_0 .net *"_s10", 0 0, L_0x1d9a570; 1 drivers +v0x1b7e2b0_0 .net *"_s12", 0 0, L_0x1d9a6d0; 1 drivers +v0x1b7e370_0 .net *"_s14", 0 0, L_0x1d9a8c0; 1 drivers +v0x1b7e450_0 .net *"_s16", 0 0, L_0x1d9aa70; 1 drivers +v0x1b7e580_0 .net *"_s3", 0 0, L_0x1d9a0d0; 1 drivers +v0x1b7e660_0 .net *"_s5", 0 0, L_0x1d9a230; 1 drivers +v0x1b7e740_0 .net *"_s6", 0 0, L_0x1d9a460; 1 drivers +v0x1b7e820_0 .net "in", 3 0, L_0x1d9ab60; 1 drivers +v0x1b7e990_0 .net "ors", 1 0, L_0x1d9a370; 1 drivers +v0x1b7ea70_0 .net "out", 0 0, L_0x1d9a850; 1 drivers +L_0x1d9a0d0 .part L_0x1d9ab60, 0, 1; +L_0x1d9a230 .part L_0x1d9ab60, 1, 1; +L_0x1d9a370 .concat8 [ 1 1 0 0], L_0x1d9a010, L_0x1d9a460; +L_0x1d9a570 .part L_0x1d9ab60, 2, 1; +L_0x1d9a6d0 .part L_0x1d9ab60, 3, 1; +L_0x1d9a8c0 .part L_0x1d9a370, 0, 1; +L_0x1d9aa70 .part L_0x1d9a370, 1, 1; +S_0x1b7eb90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b7dcc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1d9ac90/d .functor OR 1, L_0x1d9ad00, L_0x1d9ae60, C4<0>, C4<0>; +L_0x1d9ac90 .delay 1 (30000,30000,30000) L_0x1d9ac90/d; +L_0x1d9b090/d .functor OR 1, L_0x1d9b1a0, L_0x1d9b300, C4<0>, C4<0>; +L_0x1d9b090 .delay 1 (30000,30000,30000) L_0x1d9b090/d; +L_0x1d9b480/d .functor OR 1, L_0x1d9b4f0, L_0x1d9b6a0, C4<0>, C4<0>; +L_0x1d9b480 .delay 1 (30000,30000,30000) L_0x1d9b480/d; +v0x1b7ed50_0 .net *"_s0", 0 0, L_0x1d9ac90; 1 drivers +v0x1b7ee50_0 .net *"_s10", 0 0, L_0x1d9b1a0; 1 drivers +v0x1b7ef30_0 .net *"_s12", 0 0, L_0x1d9b300; 1 drivers +v0x1b7eff0_0 .net *"_s14", 0 0, L_0x1d9b4f0; 1 drivers +v0x1b7f0d0_0 .net *"_s16", 0 0, L_0x1d9b6a0; 1 drivers +v0x1b7f200_0 .net *"_s3", 0 0, L_0x1d9ad00; 1 drivers +v0x1b7f2e0_0 .net *"_s5", 0 0, L_0x1d9ae60; 1 drivers +v0x1b7f3c0_0 .net *"_s6", 0 0, L_0x1d9b090; 1 drivers +v0x1b7f4a0_0 .net "in", 3 0, L_0x1d9b8d0; 1 drivers +v0x1b7f610_0 .net "ors", 1 0, L_0x1d9afa0; 1 drivers +v0x1b7f6f0_0 .net "out", 0 0, L_0x1d9b480; 1 drivers +L_0x1d9ad00 .part L_0x1d9b8d0, 0, 1; +L_0x1d9ae60 .part L_0x1d9b8d0, 1, 1; +L_0x1d9afa0 .concat8 [ 1 1 0 0], L_0x1d9ac90, L_0x1d9b090; +L_0x1d9b1a0 .part L_0x1d9b8d0, 2, 1; +L_0x1d9b300 .part L_0x1d9b8d0, 3, 1; +L_0x1d9b4f0 .part L_0x1d9afa0, 0, 1; +L_0x1d9b6a0 .part L_0x1d9afa0, 1, 1; +S_0x1b80000 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b739b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1d97270/d .functor XNOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; +L_0x1d97270 .delay 1 (20000,20000,20000) L_0x1d97270/d; +L_0x1d974e0/d .functor AND 1, L_0x1d9f810, L_0x1d96160, C4<1>, C4<1>; +L_0x1d974e0 .delay 1 (30000,30000,30000) L_0x1d974e0/d; +L_0x1d97550/d .functor AND 1, L_0x1d97270, L_0x1d9fa10, C4<1>, C4<1>; +L_0x1d97550 .delay 1 (30000,30000,30000) L_0x1d97550/d; +L_0x1d976b0/d .functor OR 1, L_0x1d97550, L_0x1d974e0, C4<0>, C4<0>; +L_0x1d976b0 .delay 1 (30000,30000,30000) L_0x1d976b0/d; +v0x1b802b0_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers +v0x1b803a0_0 .net "a_", 0 0, L_0x1d96050; alias, 1 drivers +v0x1b80460_0 .net "b", 0 0, L_0x1d9f970; alias, 1 drivers +v0x1b80550_0 .net "b_", 0 0, L_0x1d96160; alias, 1 drivers +v0x1b805f0_0 .net "carryin", 0 0, L_0x1d9fa10; alias, 1 drivers +v0x1b80730_0 .net "eq", 0 0, L_0x1d97270; 1 drivers +v0x1b807f0_0 .net "lt", 0 0, L_0x1d974e0; 1 drivers +v0x1b808b0_0 .net "out", 0 0, L_0x1d976b0; 1 drivers +v0x1b80970_0 .net "w0", 0 0, L_0x1d97550; 1 drivers +S_0x1b80bc0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b739b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1d97050/d .functor OR 1, L_0x1d96b50, L_0x1b81e20, C4<0>, C4<0>; +L_0x1d97050 .delay 1 (30000,30000,30000) L_0x1d97050/d; +v0x1b819b0_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers +v0x1b81b00_0 .net "b", 0 0, L_0x1d96160; alias, 1 drivers +v0x1b81bc0_0 .net "c1", 0 0, L_0x1d96b50; 1 drivers +v0x1b81c60_0 .net "c2", 0 0, L_0x1b81e20; 1 drivers +v0x1b81d30_0 .net "carryin", 0 0, L_0x1d9fa10; alias, 1 drivers +v0x1b81eb0_0 .net "carryout", 0 0, L_0x1d97050; 1 drivers +v0x1b81f50_0 .net "s1", 0 0, L_0x1d96a90; 1 drivers +v0x1b81ff0_0 .net "sum", 0 0, L_0x1d96cb0; 1 drivers +S_0x1b80e10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b80bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d96a90/d .functor XOR 1, L_0x1d9f810, L_0x1d96160, C4<0>, C4<0>; +L_0x1d96a90 .delay 1 (30000,30000,30000) L_0x1d96a90/d; +L_0x1d96b50/d .functor AND 1, L_0x1d9f810, L_0x1d96160, C4<1>, C4<1>; +L_0x1d96b50 .delay 1 (30000,30000,30000) L_0x1d96b50/d; +v0x1b81070_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers +v0x1b81130_0 .net "b", 0 0, L_0x1d96160; alias, 1 drivers +v0x1b811f0_0 .net "carryout", 0 0, L_0x1d96b50; alias, 1 drivers +v0x1b81290_0 .net "sum", 0 0, L_0x1d96a90; alias, 1 drivers +S_0x1b813c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b80bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d96cb0/d .functor XOR 1, L_0x1d96a90, L_0x1d9fa10, C4<0>, C4<0>; +L_0x1d96cb0 .delay 1 (30000,30000,30000) L_0x1d96cb0/d; +L_0x1b81e20/d .functor AND 1, L_0x1d96a90, L_0x1d9fa10, C4<1>, C4<1>; +L_0x1b81e20 .delay 1 (30000,30000,30000) L_0x1b81e20/d; +v0x1b81620_0 .net "a", 0 0, L_0x1d96a90; alias, 1 drivers +v0x1b816f0_0 .net "b", 0 0, L_0x1d9fa10; alias, 1 drivers +v0x1b81790_0 .net "carryout", 0 0, L_0x1b81e20; alias, 1 drivers +v0x1b81860_0 .net "sum", 0 0, L_0x1d96cb0; alias, 1 drivers +S_0x1b83410 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b73690; + .timescale -9 -12; +L_0x7f72592da498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da4e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1d95cb0/d .functor OR 1, L_0x7f72592da498, L_0x7f72592da4e0, C4<0>, C4<0>; +L_0x1d95cb0 .delay 1 (30000,30000,30000) L_0x1d95cb0/d; +v0x1b83600_0 .net/2u *"_s0", 0 0, L_0x7f72592da498; 1 drivers +v0x1b836e0_0 .net/2u *"_s2", 0 0, L_0x7f72592da4e0; 1 drivers +S_0x1b837c0 .scope generate, "alu_slices[5]" "alu_slices[5]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1b839d0 .param/l "i" 0 3 37, +C4<0101>; +S_0x1b83a90 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b837c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1d9fb50/d .functor NOT 1, L_0x1daa3a0, C4<0>, C4<0>, C4<0>; +L_0x1d9fb50 .delay 1 (10000,10000,10000) L_0x1d9fb50/d; +L_0x1d9fd20/d .functor NOT 1, L_0x1daa590, C4<0>, C4<0>, C4<0>; +L_0x1d9fd20 .delay 1 (10000,10000,10000) L_0x1d9fd20/d; +L_0x1da0cd0/d .functor XOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; +L_0x1da0cd0 .delay 1 (30000,30000,30000) L_0x1da0cd0/d; +L_0x7f72592da528 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da570 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1da1380/d .functor OR 1, L_0x7f72592da528, L_0x7f72592da570, C4<0>, C4<0>; +L_0x1da1380 .delay 1 (30000,30000,30000) L_0x1da1380/d; +L_0x1da1580/d .functor AND 1, L_0x1daa3a0, L_0x1daa590, C4<1>, C4<1>; +L_0x1da1580 .delay 1 (30000,30000,30000) L_0x1da1580/d; +L_0x1da1640/d .functor NAND 1, L_0x1daa3a0, L_0x1daa590, C4<1>, C4<1>; +L_0x1da1640 .delay 1 (20000,20000,20000) L_0x1da1640/d; +L_0x1da17a0/d .functor XOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; +L_0x1da17a0 .delay 1 (20000,20000,20000) L_0x1da17a0/d; +L_0x1da1c50/d .functor OR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; +L_0x1da1c50 .delay 1 (30000,30000,30000) L_0x1da1c50/d; +L_0x1daa2a0/d .functor NOT 1, L_0x1da55c0, C4<0>, C4<0>, C4<0>; +L_0x1daa2a0 .delay 1 (10000,10000,10000) L_0x1daa2a0/d; +v0x1b921d0_0 .net "A", 0 0, L_0x1daa3a0; 1 drivers +v0x1b92290_0 .net "A_", 0 0, L_0x1d9fb50; 1 drivers +v0x1b92350_0 .net "B", 0 0, L_0x1daa590; 1 drivers +v0x1b92420_0 .net "B_", 0 0, L_0x1d9fd20; 1 drivers +v0x1b924c0_0 .net *"_s12", 0 0, L_0x1da1380; 1 drivers +v0x1b925b0_0 .net/2s *"_s14", 0 0, L_0x7f72592da528; 1 drivers +v0x1b92670_0 .net/2s *"_s16", 0 0, L_0x7f72592da570; 1 drivers +v0x1b92750_0 .net *"_s18", 0 0, L_0x1da1580; 1 drivers +v0x1b92830_0 .net *"_s20", 0 0, L_0x1da1640; 1 drivers +v0x1b929a0_0 .net *"_s22", 0 0, L_0x1da17a0; 1 drivers +v0x1b92a80_0 .net *"_s24", 0 0, L_0x1da1c50; 1 drivers +o0x7f7259361d58 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1b92b60_0 name=_s30 +o0x7f7259361d88 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1b92c40_0 name=_s32 +v0x1b92d20_0 .net *"_s8", 0 0, L_0x1da0cd0; 1 drivers +v0x1b92e00_0 .net "carryin", 0 0, L_0x1daa630; 1 drivers +v0x1b92ea0_0 .net "carryout", 0 0, L_0x1da9f40; 1 drivers +v0x1b92f40_0 .net "carryouts", 7 0, L_0x1ebf380; 1 drivers +v0x1b930f0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b93190_0 .net "result", 0 0, L_0x1da55c0; 1 drivers +v0x1b93280_0 .net "results", 7 0, L_0x1da1a20; 1 drivers +v0x1b93390_0 .net "zero", 0 0, L_0x1daa2a0; 1 drivers +LS_0x1da1a20_0_0 .concat8 [ 1 1 1 1], L_0x1da01f0, L_0x1da0820, L_0x1da0cd0, L_0x1da1380; +LS_0x1da1a20_0_4 .concat8 [ 1 1 1 1], L_0x1da1580, L_0x1da1640, L_0x1da17a0, L_0x1da1c50; +L_0x1da1a20 .concat8 [ 4 4 0 0], LS_0x1da1a20_0_0, LS_0x1da1a20_0_4; +LS_0x1ebf380_0_0 .concat [ 1 1 1 1], L_0x1da04a0, L_0x1da0b70, o0x7f7259361d58, L_0x1da11d0; +LS_0x1ebf380_0_4 .concat [ 4 0 0 0], o0x7f7259361d88; +L_0x1ebf380 .concat [ 4 4 0 0], LS_0x1ebf380_0_0, LS_0x1ebf380_0_4; +S_0x1b83d10 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b83a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1da04a0/d .functor OR 1, L_0x1d9ff80, L_0x1da0340, C4<0>, C4<0>; +L_0x1da04a0 .delay 1 (30000,30000,30000) L_0x1da04a0/d; +v0x1b84b40_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers +v0x1b84c00_0 .net "b", 0 0, L_0x1daa590; alias, 1 drivers +v0x1b84cd0_0 .net "c1", 0 0, L_0x1d9ff80; 1 drivers +v0x1b84dd0_0 .net "c2", 0 0, L_0x1da0340; 1 drivers +v0x1b84ea0_0 .net "carryin", 0 0, L_0x1daa630; alias, 1 drivers +v0x1b84f90_0 .net "carryout", 0 0, L_0x1da04a0; 1 drivers +v0x1b85030_0 .net "s1", 0 0, L_0x1d9ff10; 1 drivers +v0x1b85120_0 .net "sum", 0 0, L_0x1da01f0; 1 drivers +S_0x1b83f80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b83d10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1d9ff10/d .functor XOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; +L_0x1d9ff10 .delay 1 (30000,30000,30000) L_0x1d9ff10/d; +L_0x1d9ff80/d .functor AND 1, L_0x1daa3a0, L_0x1daa590, C4<1>, C4<1>; +L_0x1d9ff80 .delay 1 (30000,30000,30000) L_0x1d9ff80/d; +v0x1b841e0_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers +v0x1b842c0_0 .net "b", 0 0, L_0x1daa590; alias, 1 drivers +v0x1b84380_0 .net "carryout", 0 0, L_0x1d9ff80; alias, 1 drivers +v0x1b84420_0 .net "sum", 0 0, L_0x1d9ff10; alias, 1 drivers +S_0x1b84560 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b83d10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1da01f0/d .functor XOR 1, L_0x1d9ff10, L_0x1daa630, C4<0>, C4<0>; +L_0x1da01f0 .delay 1 (30000,30000,30000) L_0x1da01f0/d; +L_0x1da0340/d .functor AND 1, L_0x1d9ff10, L_0x1daa630, C4<1>, C4<1>; +L_0x1da0340 .delay 1 (30000,30000,30000) L_0x1da0340/d; +v0x1b847c0_0 .net "a", 0 0, L_0x1d9ff10; alias, 1 drivers +v0x1b84860_0 .net "b", 0 0, L_0x1daa630; alias, 1 drivers +v0x1b84900_0 .net "carryout", 0 0, L_0x1da0340; alias, 1 drivers +v0x1b849d0_0 .net "sum", 0 0, L_0x1da01f0; alias, 1 drivers +S_0x1b851f0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b83a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b8a5f0_0 .net "ands", 7 0, L_0x1da7000; 1 drivers +v0x1b8a700_0 .net "in", 7 0, L_0x1ebf380; alias, 1 drivers +v0x1b8a7c0_0 .net "out", 0 0, L_0x1da9f40; alias, 1 drivers +v0x1b8a890_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b85410 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b851f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b87b40_0 .net "A", 7 0, L_0x1ebf380; alias, 1 drivers +v0x1b87c40_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b87d00_0 .net *"_s0", 0 0, L_0x1da5920; 1 drivers +v0x1b87dc0_0 .net *"_s12", 0 0, L_0x1da6290; 1 drivers +v0x1b87ea0_0 .net *"_s16", 0 0, L_0x1da65f0; 1 drivers +v0x1b87fd0_0 .net *"_s20", 0 0, L_0x1da6900; 1 drivers +v0x1b880b0_0 .net *"_s24", 0 0, L_0x1da6cf0; 1 drivers +v0x1b88190_0 .net *"_s28", 0 0, L_0x1da6c80; 1 drivers +v0x1b88270_0 .net *"_s4", 0 0, L_0x1da5c30; 1 drivers +v0x1b883e0_0 .net *"_s8", 0 0, L_0x1da5f80; 1 drivers +v0x1b884c0_0 .net "out", 7 0, L_0x1da7000; alias, 1 drivers +L_0x1da59e0 .part L_0x1ebf380, 0, 1; +L_0x1da5b40 .part v0x1d6daa0_0, 0, 1; +L_0x1da5cf0 .part L_0x1ebf380, 1, 1; +L_0x1da5ee0 .part v0x1d6daa0_0, 1, 1; +L_0x1da6040 .part L_0x1ebf380, 2, 1; +L_0x1da61a0 .part v0x1d6daa0_0, 2, 1; +L_0x1da6350 .part L_0x1ebf380, 3, 1; +L_0x1da64b0 .part v0x1d6daa0_0, 3, 1; +L_0x1da66b0 .part L_0x1ebf380, 4, 1; +L_0x1da6810 .part v0x1d6daa0_0, 4, 1; +L_0x1da6970 .part L_0x1ebf380, 5, 1; +L_0x1da6be0 .part v0x1d6daa0_0, 5, 1; +L_0x1da6db0 .part L_0x1ebf380, 6, 1; +L_0x1da6f10 .part v0x1d6daa0_0, 6, 1; +LS_0x1da7000_0_0 .concat8 [ 1 1 1 1], L_0x1da5920, L_0x1da5c30, L_0x1da5f80, L_0x1da6290; +LS_0x1da7000_0_4 .concat8 [ 1 1 1 1], L_0x1da65f0, L_0x1da6900, L_0x1da6cf0, L_0x1da6c80; +L_0x1da7000 .concat8 [ 4 4 0 0], LS_0x1da7000_0_0, LS_0x1da7000_0_4; +L_0x1da73c0 .part L_0x1ebf380, 7, 1; +L_0x1da75b0 .part v0x1d6daa0_0, 7, 1; +S_0x1b85670 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b85880 .param/l "i" 0 4 54, +C4<00>; +L_0x1da5920/d .functor AND 1, L_0x1da59e0, L_0x1da5b40, C4<1>, C4<1>; +L_0x1da5920 .delay 1 (30000,30000,30000) L_0x1da5920/d; +v0x1b85960_0 .net *"_s0", 0 0, L_0x1da59e0; 1 drivers +v0x1b85a40_0 .net *"_s1", 0 0, L_0x1da5b40; 1 drivers +S_0x1b85b20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b85d30 .param/l "i" 0 4 54, +C4<01>; +L_0x1da5c30/d .functor AND 1, L_0x1da5cf0, L_0x1da5ee0, C4<1>, C4<1>; +L_0x1da5c30 .delay 1 (30000,30000,30000) L_0x1da5c30/d; +v0x1b85df0_0 .net *"_s0", 0 0, L_0x1da5cf0; 1 drivers +v0x1b85ed0_0 .net *"_s1", 0 0, L_0x1da5ee0; 1 drivers +S_0x1b85fb0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b861c0 .param/l "i" 0 4 54, +C4<010>; +L_0x1da5f80/d .functor AND 1, L_0x1da6040, L_0x1da61a0, C4<1>, C4<1>; +L_0x1da5f80 .delay 1 (30000,30000,30000) L_0x1da5f80/d; +v0x1b86260_0 .net *"_s0", 0 0, L_0x1da6040; 1 drivers +v0x1b86340_0 .net *"_s1", 0 0, L_0x1da61a0; 1 drivers +S_0x1b86420 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b86630 .param/l "i" 0 4 54, +C4<011>; +L_0x1da6290/d .functor AND 1, L_0x1da6350, L_0x1da64b0, C4<1>, C4<1>; +L_0x1da6290 .delay 1 (30000,30000,30000) L_0x1da6290/d; +v0x1b866f0_0 .net *"_s0", 0 0, L_0x1da6350; 1 drivers +v0x1b867d0_0 .net *"_s1", 0 0, L_0x1da64b0; 1 drivers +S_0x1b868b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b86b10 .param/l "i" 0 4 54, +C4<0100>; +L_0x1da65f0/d .functor AND 1, L_0x1da66b0, L_0x1da6810, C4<1>, C4<1>; +L_0x1da65f0 .delay 1 (30000,30000,30000) L_0x1da65f0/d; +v0x1b86bd0_0 .net *"_s0", 0 0, L_0x1da66b0; 1 drivers +v0x1b86cb0_0 .net *"_s1", 0 0, L_0x1da6810; 1 drivers +S_0x1b86d90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b86fa0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1da6900/d .functor AND 1, L_0x1da6970, L_0x1da6be0, C4<1>, C4<1>; +L_0x1da6900 .delay 1 (30000,30000,30000) L_0x1da6900/d; +v0x1b87060_0 .net *"_s0", 0 0, L_0x1da6970; 1 drivers +v0x1b87140_0 .net *"_s1", 0 0, L_0x1da6be0; 1 drivers +S_0x1b87220 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b87430 .param/l "i" 0 4 54, +C4<0110>; +L_0x1da6cf0/d .functor AND 1, L_0x1da6db0, L_0x1da6f10, C4<1>, C4<1>; +L_0x1da6cf0 .delay 1 (30000,30000,30000) L_0x1da6cf0/d; +v0x1b874f0_0 .net *"_s0", 0 0, L_0x1da6db0; 1 drivers +v0x1b875d0_0 .net *"_s1", 0 0, L_0x1da6f10; 1 drivers +S_0x1b876b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b85410; + .timescale -9 -12; +P_0x1b878c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1da6c80/d .functor AND 1, L_0x1da73c0, L_0x1da75b0, C4<1>, C4<1>; +L_0x1da6c80 .delay 1 (30000,30000,30000) L_0x1da6c80/d; +v0x1b87980_0 .net *"_s0", 0 0, L_0x1da73c0; 1 drivers +v0x1b87a60_0 .net *"_s1", 0 0, L_0x1da75b0; 1 drivers +S_0x1b88620 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b851f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1da9f40/d .functor OR 1, L_0x1daa000, L_0x1daa1b0, C4<0>, C4<0>; +L_0x1da9f40 .delay 1 (30000,30000,30000) L_0x1da9f40/d; +v0x1b8a180_0 .net *"_s10", 0 0, L_0x1daa000; 1 drivers +v0x1b8a260_0 .net *"_s12", 0 0, L_0x1daa1b0; 1 drivers +v0x1b8a340_0 .net "in", 7 0, L_0x1da7000; alias, 1 drivers +v0x1b8a410_0 .net "ors", 1 0, L_0x1da9d60; 1 drivers +v0x1b8a4d0_0 .net "out", 0 0, L_0x1da9f40; alias, 1 drivers +L_0x1cf2800 .part L_0x1da7000, 0, 4; +L_0x1da9d60 .concat8 [ 1 1 0 0], L_0x1cf24f0, L_0x1da9a50; +L_0x1da9ea0 .part L_0x1da7000, 4, 4; +L_0x1daa000 .part L_0x1da9d60, 0, 1; +L_0x1daa1b0 .part L_0x1da9d60, 1, 1; +S_0x1b887e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b88620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1da3540/d .functor OR 1, L_0x1cf1d70, L_0x1cf1ed0, C4<0>, C4<0>; +L_0x1da3540 .delay 1 (30000,30000,30000) L_0x1da3540/d; +L_0x1cf2100/d .functor OR 1, L_0x1cf2210, L_0x1cf2370, C4<0>, C4<0>; +L_0x1cf2100 .delay 1 (30000,30000,30000) L_0x1cf2100/d; +L_0x1cf24f0/d .functor OR 1, L_0x1cf2560, L_0x1cf2710, C4<0>, C4<0>; +L_0x1cf24f0 .delay 1 (30000,30000,30000) L_0x1cf24f0/d; +v0x1b88a30_0 .net *"_s0", 0 0, L_0x1da3540; 1 drivers +v0x1b88b30_0 .net *"_s10", 0 0, L_0x1cf2210; 1 drivers +v0x1b88c10_0 .net *"_s12", 0 0, L_0x1cf2370; 1 drivers +v0x1b88cd0_0 .net *"_s14", 0 0, L_0x1cf2560; 1 drivers +v0x1b88db0_0 .net *"_s16", 0 0, L_0x1cf2710; 1 drivers +v0x1b88ee0_0 .net *"_s3", 0 0, L_0x1cf1d70; 1 drivers +v0x1b88fc0_0 .net *"_s5", 0 0, L_0x1cf1ed0; 1 drivers +v0x1b89080_0 .net *"_s6", 0 0, L_0x1cf2100; 1 drivers +v0x1b89160_0 .net "in", 3 0, L_0x1cf2800; 1 drivers +v0x1b892d0_0 .net "ors", 1 0, L_0x1cf2010; 1 drivers +v0x1b893b0_0 .net "out", 0 0, L_0x1cf24f0; 1 drivers +L_0x1cf1d70 .part L_0x1cf2800, 0, 1; +L_0x1cf1ed0 .part L_0x1cf2800, 1, 1; +L_0x1cf2010 .concat8 [ 1 1 0 0], L_0x1da3540, L_0x1cf2100; +L_0x1cf2210 .part L_0x1cf2800, 2, 1; +L_0x1cf2370 .part L_0x1cf2800, 3, 1; +L_0x1cf2560 .part L_0x1cf2010, 0, 1; +L_0x1cf2710 .part L_0x1cf2010, 1, 1; +S_0x1b894d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b88620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1cf2930/d .functor OR 1, L_0x1cf29a0, L_0x1cf2b00, C4<0>, C4<0>; +L_0x1cf2930 .delay 1 (30000,30000,30000) L_0x1cf2930/d; +L_0x1da96b0/d .functor OR 1, L_0x1da9770, L_0x1da98d0, C4<0>, C4<0>; +L_0x1da96b0 .delay 1 (30000,30000,30000) L_0x1da96b0/d; +L_0x1da9a50/d .functor OR 1, L_0x1da9ac0, L_0x1da9c70, C4<0>, C4<0>; +L_0x1da9a50 .delay 1 (30000,30000,30000) L_0x1da9a50/d; +v0x1b89690_0 .net *"_s0", 0 0, L_0x1cf2930; 1 drivers +v0x1b89790_0 .net *"_s10", 0 0, L_0x1da9770; 1 drivers +v0x1b89870_0 .net *"_s12", 0 0, L_0x1da98d0; 1 drivers +v0x1b89960_0 .net *"_s14", 0 0, L_0x1da9ac0; 1 drivers +v0x1b89a40_0 .net *"_s16", 0 0, L_0x1da9c70; 1 drivers +v0x1b89b70_0 .net *"_s3", 0 0, L_0x1cf29a0; 1 drivers +v0x1b89c50_0 .net *"_s5", 0 0, L_0x1cf2b00; 1 drivers +v0x1b89d30_0 .net *"_s6", 0 0, L_0x1da96b0; 1 drivers +v0x1b89e10_0 .net "in", 3 0, L_0x1da9ea0; 1 drivers +v0x1b89f80_0 .net "ors", 1 0, L_0x1cf2c40; 1 drivers +v0x1b8a060_0 .net "out", 0 0, L_0x1da9a50; 1 drivers +L_0x1cf29a0 .part L_0x1da9ea0, 0, 1; +L_0x1cf2b00 .part L_0x1da9ea0, 1, 1; +L_0x1cf2c40 .concat8 [ 1 1 0 0], L_0x1cf2930, L_0x1da96b0; +L_0x1da9770 .part L_0x1da9ea0, 2, 1; +L_0x1da98d0 .part L_0x1da9ea0, 3, 1; +L_0x1da9ac0 .part L_0x1cf2c40, 0, 1; +L_0x1da9c70 .part L_0x1cf2c40, 1, 1; +S_0x1b8a970 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b83a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b8fda0_0 .net "ands", 7 0, L_0x1da35c0; 1 drivers +v0x1b8feb0_0 .net "in", 7 0, L_0x1da1a20; alias, 1 drivers +v0x1b8ff70_0 .net "out", 0 0, L_0x1da55c0; alias, 1 drivers +v0x1b90040_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b8abc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b8a970; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b8d300_0 .net "A", 7 0, L_0x1da1a20; alias, 1 drivers +v0x1b8d400_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b8d4c0_0 .net *"_s0", 0 0, L_0x1da1db0; 1 drivers +v0x1b8d580_0 .net *"_s12", 0 0, L_0x1da2770; 1 drivers +v0x1b8d660_0 .net *"_s16", 0 0, L_0x1da2ad0; 1 drivers +v0x1b8d790_0 .net *"_s20", 0 0, L_0x1da2f00; 1 drivers +v0x1b8d870_0 .net *"_s24", 0 0, L_0x1da3230; 1 drivers +v0x1b8d950_0 .net *"_s28", 0 0, L_0x1da31c0; 1 drivers +v0x1b8da30_0 .net *"_s4", 0 0, L_0x1da2150; 1 drivers +v0x1b8dba0_0 .net *"_s8", 0 0, L_0x1da2460; 1 drivers +v0x1b8dc80_0 .net "out", 7 0, L_0x1da35c0; alias, 1 drivers +L_0x1da1ec0 .part L_0x1da1a20, 0, 1; +L_0x1da20b0 .part v0x1d6daa0_0, 0, 1; +L_0x1da2210 .part L_0x1da1a20, 1, 1; +L_0x1da2370 .part v0x1d6daa0_0, 1, 1; +L_0x1da2520 .part L_0x1da1a20, 2, 1; +L_0x1da2680 .part v0x1d6daa0_0, 2, 1; +L_0x1da2830 .part L_0x1da1a20, 3, 1; +L_0x1da2990 .part v0x1d6daa0_0, 3, 1; +L_0x1da2b90 .part L_0x1da1a20, 4, 1; +L_0x1da2e00 .part v0x1d6daa0_0, 4, 1; +L_0x1da2f70 .part L_0x1da1a20, 5, 1; +L_0x1da30d0 .part v0x1d6daa0_0, 5, 1; +L_0x1da32f0 .part L_0x1da1a20, 6, 1; +L_0x1da3450 .part v0x1d6daa0_0, 6, 1; +LS_0x1da35c0_0_0 .concat8 [ 1 1 1 1], L_0x1da1db0, L_0x1da2150, L_0x1da2460, L_0x1da2770; +LS_0x1da35c0_0_4 .concat8 [ 1 1 1 1], L_0x1da2ad0, L_0x1da2f00, L_0x1da3230, L_0x1da31c0; +L_0x1da35c0 .concat8 [ 4 4 0 0], LS_0x1da35c0_0_0, LS_0x1da35c0_0_4; +L_0x1da3980 .part L_0x1da1a20, 7, 1; +L_0x1da3b70 .part v0x1d6daa0_0, 7, 1; +S_0x1b8ae00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8b010 .param/l "i" 0 4 54, +C4<00>; +L_0x1da1db0/d .functor AND 1, L_0x1da1ec0, L_0x1da20b0, C4<1>, C4<1>; +L_0x1da1db0 .delay 1 (30000,30000,30000) L_0x1da1db0/d; +v0x1b8b0f0_0 .net *"_s0", 0 0, L_0x1da1ec0; 1 drivers +v0x1b8b1d0_0 .net *"_s1", 0 0, L_0x1da20b0; 1 drivers +S_0x1b8b2b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8b4c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1da2150/d .functor AND 1, L_0x1da2210, L_0x1da2370, C4<1>, C4<1>; +L_0x1da2150 .delay 1 (30000,30000,30000) L_0x1da2150/d; +v0x1b8b580_0 .net *"_s0", 0 0, L_0x1da2210; 1 drivers +v0x1b8b660_0 .net *"_s1", 0 0, L_0x1da2370; 1 drivers +S_0x1b8b740 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8b980 .param/l "i" 0 4 54, +C4<010>; +L_0x1da2460/d .functor AND 1, L_0x1da2520, L_0x1da2680, C4<1>, C4<1>; +L_0x1da2460 .delay 1 (30000,30000,30000) L_0x1da2460/d; +v0x1b8ba20_0 .net *"_s0", 0 0, L_0x1da2520; 1 drivers +v0x1b8bb00_0 .net *"_s1", 0 0, L_0x1da2680; 1 drivers +S_0x1b8bbe0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8bdf0 .param/l "i" 0 4 54, +C4<011>; +L_0x1da2770/d .functor AND 1, L_0x1da2830, L_0x1da2990, C4<1>, C4<1>; +L_0x1da2770 .delay 1 (30000,30000,30000) L_0x1da2770/d; +v0x1b8beb0_0 .net *"_s0", 0 0, L_0x1da2830; 1 drivers +v0x1b8bf90_0 .net *"_s1", 0 0, L_0x1da2990; 1 drivers +S_0x1b8c070 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8c2d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1da2ad0/d .functor AND 1, L_0x1da2b90, L_0x1da2e00, C4<1>, C4<1>; +L_0x1da2ad0 .delay 1 (30000,30000,30000) L_0x1da2ad0/d; +v0x1b8c390_0 .net *"_s0", 0 0, L_0x1da2b90; 1 drivers +v0x1b8c470_0 .net *"_s1", 0 0, L_0x1da2e00; 1 drivers +S_0x1b8c550 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8c760 .param/l "i" 0 4 54, +C4<0101>; +L_0x1da2f00/d .functor AND 1, L_0x1da2f70, L_0x1da30d0, C4<1>, C4<1>; +L_0x1da2f00 .delay 1 (30000,30000,30000) L_0x1da2f00/d; +v0x1b8c820_0 .net *"_s0", 0 0, L_0x1da2f70; 1 drivers +v0x1b8c900_0 .net *"_s1", 0 0, L_0x1da30d0; 1 drivers +S_0x1b8c9e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8cbf0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1da3230/d .functor AND 1, L_0x1da32f0, L_0x1da3450, C4<1>, C4<1>; +L_0x1da3230 .delay 1 (30000,30000,30000) L_0x1da3230/d; +v0x1b8ccb0_0 .net *"_s0", 0 0, L_0x1da32f0; 1 drivers +v0x1b8cd90_0 .net *"_s1", 0 0, L_0x1da3450; 1 drivers +S_0x1b8ce70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b8abc0; + .timescale -9 -12; +P_0x1b8d080 .param/l "i" 0 4 54, +C4<0111>; +L_0x1da31c0/d .functor AND 1, L_0x1da3980, L_0x1da3b70, C4<1>, C4<1>; +L_0x1da31c0 .delay 1 (30000,30000,30000) L_0x1da31c0/d; +v0x1b8d140_0 .net *"_s0", 0 0, L_0x1da3980; 1 drivers +v0x1b8d220_0 .net *"_s1", 0 0, L_0x1da3b70; 1 drivers +S_0x1b8dde0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b8a970; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1da55c0/d .functor OR 1, L_0x1da5680, L_0x1da5830, C4<0>, C4<0>; +L_0x1da55c0 .delay 1 (30000,30000,30000) L_0x1da55c0/d; +v0x1b8f930_0 .net *"_s10", 0 0, L_0x1da5680; 1 drivers +v0x1b8fa10_0 .net *"_s12", 0 0, L_0x1da5830; 1 drivers +v0x1b8faf0_0 .net "in", 7 0, L_0x1da35c0; alias, 1 drivers +v0x1b8fbc0_0 .net "ors", 1 0, L_0x1da53e0; 1 drivers +v0x1b8fc80_0 .net "out", 0 0, L_0x1da55c0; alias, 1 drivers +L_0x1da47b0 .part L_0x1da35c0, 0, 4; +L_0x1da53e0 .concat8 [ 1 1 0 0], L_0x1da44a0, L_0x1da50d0; +L_0x1da5520 .part L_0x1da35c0, 4, 4; +L_0x1da5680 .part L_0x1da53e0, 0, 1; +L_0x1da5830 .part L_0x1da53e0, 1, 1; +S_0x1b8dfa0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b8dde0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1da3c60/d .functor OR 1, L_0x1da3d20, L_0x1da3e80, C4<0>, C4<0>; +L_0x1da3c60 .delay 1 (30000,30000,30000) L_0x1da3c60/d; +L_0x1da40b0/d .functor OR 1, L_0x1da41c0, L_0x1da4320, C4<0>, C4<0>; +L_0x1da40b0 .delay 1 (30000,30000,30000) L_0x1da40b0/d; +L_0x1da44a0/d .functor OR 1, L_0x1da4510, L_0x1da46c0, C4<0>, C4<0>; +L_0x1da44a0 .delay 1 (30000,30000,30000) L_0x1da44a0/d; +v0x1b8e1f0_0 .net *"_s0", 0 0, L_0x1da3c60; 1 drivers +v0x1b8e2f0_0 .net *"_s10", 0 0, L_0x1da41c0; 1 drivers +v0x1b8e3d0_0 .net *"_s12", 0 0, L_0x1da4320; 1 drivers +v0x1b8e490_0 .net *"_s14", 0 0, L_0x1da4510; 1 drivers +v0x1b8e570_0 .net *"_s16", 0 0, L_0x1da46c0; 1 drivers +v0x1b8e6a0_0 .net *"_s3", 0 0, L_0x1da3d20; 1 drivers +v0x1b8e780_0 .net *"_s5", 0 0, L_0x1da3e80; 1 drivers +v0x1b8e860_0 .net *"_s6", 0 0, L_0x1da40b0; 1 drivers +v0x1b8e940_0 .net "in", 3 0, L_0x1da47b0; 1 drivers +v0x1b8eab0_0 .net "ors", 1 0, L_0x1da3fc0; 1 drivers +v0x1b8eb90_0 .net "out", 0 0, L_0x1da44a0; 1 drivers +L_0x1da3d20 .part L_0x1da47b0, 0, 1; +L_0x1da3e80 .part L_0x1da47b0, 1, 1; +L_0x1da3fc0 .concat8 [ 1 1 0 0], L_0x1da3c60, L_0x1da40b0; +L_0x1da41c0 .part L_0x1da47b0, 2, 1; +L_0x1da4320 .part L_0x1da47b0, 3, 1; +L_0x1da4510 .part L_0x1da3fc0, 0, 1; +L_0x1da46c0 .part L_0x1da3fc0, 1, 1; +S_0x1b8ecb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b8dde0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1da48e0/d .functor OR 1, L_0x1da4950, L_0x1da4ab0, C4<0>, C4<0>; +L_0x1da48e0 .delay 1 (30000,30000,30000) L_0x1da48e0/d; +L_0x1da4ce0/d .functor OR 1, L_0x1da4df0, L_0x1da4f50, C4<0>, C4<0>; +L_0x1da4ce0 .delay 1 (30000,30000,30000) L_0x1da4ce0/d; +L_0x1da50d0/d .functor OR 1, L_0x1da5140, L_0x1da52f0, C4<0>, C4<0>; +L_0x1da50d0 .delay 1 (30000,30000,30000) L_0x1da50d0/d; +v0x1b8ee70_0 .net *"_s0", 0 0, L_0x1da48e0; 1 drivers +v0x1b8ef70_0 .net *"_s10", 0 0, L_0x1da4df0; 1 drivers +v0x1b8f050_0 .net *"_s12", 0 0, L_0x1da4f50; 1 drivers +v0x1b8f110_0 .net *"_s14", 0 0, L_0x1da5140; 1 drivers +v0x1b8f1f0_0 .net *"_s16", 0 0, L_0x1da52f0; 1 drivers +v0x1b8f320_0 .net *"_s3", 0 0, L_0x1da4950; 1 drivers +v0x1b8f400_0 .net *"_s5", 0 0, L_0x1da4ab0; 1 drivers +v0x1b8f4e0_0 .net *"_s6", 0 0, L_0x1da4ce0; 1 drivers +v0x1b8f5c0_0 .net "in", 3 0, L_0x1da5520; 1 drivers +v0x1b8f730_0 .net "ors", 1 0, L_0x1da4bf0; 1 drivers +v0x1b8f810_0 .net "out", 0 0, L_0x1da50d0; 1 drivers +L_0x1da4950 .part L_0x1da5520, 0, 1; +L_0x1da4ab0 .part L_0x1da5520, 1, 1; +L_0x1da4bf0 .concat8 [ 1 1 0 0], L_0x1da48e0, L_0x1da4ce0; +L_0x1da4df0 .part L_0x1da5520, 2, 1; +L_0x1da4f50 .part L_0x1da5520, 3, 1; +L_0x1da5140 .part L_0x1da4bf0, 0, 1; +L_0x1da52f0 .part L_0x1da4bf0, 1, 1; +S_0x1b90120 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b83a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1da0d90/d .functor XNOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; +L_0x1da0d90 .delay 1 (20000,20000,20000) L_0x1da0d90/d; +L_0x1da1000/d .functor AND 1, L_0x1daa3a0, L_0x1d9fd20, C4<1>, C4<1>; +L_0x1da1000 .delay 1 (30000,30000,30000) L_0x1da1000/d; +L_0x1da1070/d .functor AND 1, L_0x1da0d90, L_0x1daa630, C4<1>, C4<1>; +L_0x1da1070 .delay 1 (30000,30000,30000) L_0x1da1070/d; +L_0x1da11d0/d .functor OR 1, L_0x1da1070, L_0x1da1000, C4<0>, C4<0>; +L_0x1da11d0 .delay 1 (30000,30000,30000) L_0x1da11d0/d; +v0x1b903d0_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers +v0x1b904c0_0 .net "a_", 0 0, L_0x1d9fb50; alias, 1 drivers +v0x1b90580_0 .net "b", 0 0, L_0x1daa590; alias, 1 drivers +v0x1b90670_0 .net "b_", 0 0, L_0x1d9fd20; alias, 1 drivers +v0x1b90710_0 .net "carryin", 0 0, L_0x1daa630; alias, 1 drivers +v0x1b90850_0 .net "eq", 0 0, L_0x1da0d90; 1 drivers +v0x1b90910_0 .net "lt", 0 0, L_0x1da1000; 1 drivers +v0x1b909d0_0 .net "out", 0 0, L_0x1da11d0; 1 drivers +v0x1b90a90_0 .net "w0", 0 0, L_0x1da1070; 1 drivers +S_0x1b90ce0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b83a90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1da0b70/d .functor OR 1, L_0x1da06c0, L_0x1b91f40, C4<0>, C4<0>; +L_0x1da0b70 .delay 1 (30000,30000,30000) L_0x1da0b70/d; +v0x1b91ad0_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers +v0x1b91c20_0 .net "b", 0 0, L_0x1d9fd20; alias, 1 drivers +v0x1b91ce0_0 .net "c1", 0 0, L_0x1da06c0; 1 drivers +v0x1b91d80_0 .net "c2", 0 0, L_0x1b91f40; 1 drivers +v0x1b91e50_0 .net "carryin", 0 0, L_0x1daa630; alias, 1 drivers +v0x1b91fd0_0 .net "carryout", 0 0, L_0x1da0b70; 1 drivers +v0x1b92070_0 .net "s1", 0 0, L_0x1da0600; 1 drivers +v0x1b92110_0 .net "sum", 0 0, L_0x1da0820; 1 drivers +S_0x1b90f30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b90ce0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1da0600/d .functor XOR 1, L_0x1daa3a0, L_0x1d9fd20, C4<0>, C4<0>; +L_0x1da0600 .delay 1 (30000,30000,30000) L_0x1da0600/d; +L_0x1da06c0/d .functor AND 1, L_0x1daa3a0, L_0x1d9fd20, C4<1>, C4<1>; +L_0x1da06c0 .delay 1 (30000,30000,30000) L_0x1da06c0/d; +v0x1b91190_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers +v0x1b91250_0 .net "b", 0 0, L_0x1d9fd20; alias, 1 drivers +v0x1b91310_0 .net "carryout", 0 0, L_0x1da06c0; alias, 1 drivers +v0x1b913b0_0 .net "sum", 0 0, L_0x1da0600; alias, 1 drivers +S_0x1b914e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b90ce0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1da0820/d .functor XOR 1, L_0x1da0600, L_0x1daa630, C4<0>, C4<0>; +L_0x1da0820 .delay 1 (30000,30000,30000) L_0x1da0820/d; +L_0x1b91f40/d .functor AND 1, L_0x1da0600, L_0x1daa630, C4<1>, C4<1>; +L_0x1b91f40 .delay 1 (30000,30000,30000) L_0x1b91f40/d; +v0x1b91740_0 .net "a", 0 0, L_0x1da0600; alias, 1 drivers +v0x1b91810_0 .net "b", 0 0, L_0x1daa630; alias, 1 drivers +v0x1b918b0_0 .net "carryout", 0 0, L_0x1b91f40; alias, 1 drivers +v0x1b91980_0 .net "sum", 0 0, L_0x1da0820; alias, 1 drivers +S_0x1b93530 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b837c0; + .timescale -9 -12; +L_0x7f72592da5b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1daa440/d .functor OR 1, L_0x7f72592da5b8, L_0x7f72592da600, C4<0>, C4<0>; +L_0x1daa440 .delay 1 (30000,30000,30000) L_0x1daa440/d; +v0x1b93720_0 .net/2u *"_s0", 0 0, L_0x7f72592da5b8; 1 drivers +v0x1b93800_0 .net/2u *"_s2", 0 0, L_0x7f72592da600; 1 drivers +S_0x1b938e0 .scope generate, "alu_slices[6]" "alu_slices[6]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1b93af0 .param/l "i" 0 3 37, +C4<0110>; +S_0x1b93bb0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b938e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1daa810/d .functor NOT 1, L_0x1db40d0, C4<0>, C4<0>, C4<0>; +L_0x1daa810 .delay 1 (10000,10000,10000) L_0x1daa810/d; +L_0x1daa970/d .functor NOT 1, L_0x1db4340, C4<0>, C4<0>, C4<0>; +L_0x1daa970 .delay 1 (10000,10000,10000) L_0x1daa970/d; +L_0x1dab9c0/d .functor XOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; +L_0x1dab9c0 .delay 1 (30000,30000,30000) L_0x1dab9c0/d; +L_0x7f72592da648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dac070/d .functor OR 1, L_0x7f72592da648, L_0x7f72592da690, C4<0>, C4<0>; +L_0x1dac070 .delay 1 (30000,30000,30000) L_0x1dac070/d; +L_0x1dac270/d .functor AND 1, L_0x1db40d0, L_0x1db4340, C4<1>, C4<1>; +L_0x1dac270 .delay 1 (30000,30000,30000) L_0x1dac270/d; +L_0x1dac330/d .functor NAND 1, L_0x1db40d0, L_0x1db4340, C4<1>, C4<1>; +L_0x1dac330 .delay 1 (20000,20000,20000) L_0x1dac330/d; +L_0x1dac490/d .functor XOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; +L_0x1dac490 .delay 1 (20000,20000,20000) L_0x1dac490/d; +L_0x1dac940/d .functor OR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; +L_0x1dac940 .delay 1 (30000,30000,30000) L_0x1dac940/d; +L_0x1db3fd0/d .functor NOT 1, L_0x1db0230, C4<0>, C4<0>, C4<0>; +L_0x1db3fd0 .delay 1 (10000,10000,10000) L_0x1db3fd0/d; +v0x1ba24e0_0 .net "A", 0 0, L_0x1db40d0; 1 drivers +v0x1ba25a0_0 .net "A_", 0 0, L_0x1daa810; 1 drivers +v0x1ba2660_0 .net "B", 0 0, L_0x1db4340; 1 drivers +v0x1ba2730_0 .net "B_", 0 0, L_0x1daa970; 1 drivers +v0x1ba27d0_0 .net *"_s12", 0 0, L_0x1dac070; 1 drivers +v0x1ba28c0_0 .net/2s *"_s14", 0 0, L_0x7f72592da648; 1 drivers +v0x1ba2980_0 .net/2s *"_s16", 0 0, L_0x7f72592da690; 1 drivers +v0x1ba2a60_0 .net *"_s18", 0 0, L_0x1dac270; 1 drivers +v0x1ba2b40_0 .net *"_s20", 0 0, L_0x1dac330; 1 drivers +v0x1ba2cb0_0 .net *"_s22", 0 0, L_0x1dac490; 1 drivers +v0x1ba2d90_0 .net *"_s24", 0 0, L_0x1dac940; 1 drivers +o0x7f72593642a8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1ba2e70_0 name=_s30 +o0x7f72593642d8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1ba2f50_0 name=_s32 +v0x1ba3030_0 .net *"_s8", 0 0, L_0x1dab9c0; 1 drivers +v0x1ba3110_0 .net "carryin", 0 0, L_0x1daa6d0; 1 drivers +v0x1ba31b0_0 .net "carryout", 0 0, L_0x1db3c70; 1 drivers +v0x1ba3250_0 .net "carryouts", 7 0, L_0x1ebf510; 1 drivers +v0x1ba3400_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ba34a0_0 .net "result", 0 0, L_0x1db0230; 1 drivers +v0x1ba3590_0 .net "results", 7 0, L_0x1dac710; 1 drivers +v0x1ba36a0_0 .net "zero", 0 0, L_0x1db3fd0; 1 drivers +LS_0x1dac710_0_0 .concat8 [ 1 1 1 1], L_0x1daae90, L_0x1dab4c0, L_0x1dab9c0, L_0x1dac070; +LS_0x1dac710_0_4 .concat8 [ 1 1 1 1], L_0x1dac270, L_0x1dac330, L_0x1dac490, L_0x1dac940; +L_0x1dac710 .concat8 [ 4 4 0 0], LS_0x1dac710_0_0, LS_0x1dac710_0_4; +LS_0x1ebf510_0_0 .concat [ 1 1 1 1], L_0x1dab140, L_0x1dab860, o0x7f72593642a8, L_0x1dabec0; +LS_0x1ebf510_0_4 .concat [ 4 0 0 0], o0x7f72593642d8; +L_0x1ebf510 .concat [ 4 4 0 0], LS_0x1ebf510_0_0, LS_0x1ebf510_0_4; +S_0x1b93e30 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b93bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dab140/d .functor OR 1, L_0x1daac20, L_0x1daafe0, C4<0>, C4<0>; +L_0x1dab140 .delay 1 (30000,30000,30000) L_0x1dab140/d; +v0x1b94c60_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers +v0x1b94d20_0 .net "b", 0 0, L_0x1db4340; alias, 1 drivers +v0x1b94df0_0 .net "c1", 0 0, L_0x1daac20; 1 drivers +v0x1b94ef0_0 .net "c2", 0 0, L_0x1daafe0; 1 drivers +v0x1b94fc0_0 .net "carryin", 0 0, L_0x1daa6d0; alias, 1 drivers +v0x1b950b0_0 .net "carryout", 0 0, L_0x1dab140; 1 drivers +v0x1b95150_0 .net "s1", 0 0, L_0x1daab60; 1 drivers +v0x1b95240_0 .net "sum", 0 0, L_0x1daae90; 1 drivers +S_0x1b940a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b93e30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1daab60/d .functor XOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; +L_0x1daab60 .delay 1 (30000,30000,30000) L_0x1daab60/d; +L_0x1daac20/d .functor AND 1, L_0x1db40d0, L_0x1db4340, C4<1>, C4<1>; +L_0x1daac20 .delay 1 (30000,30000,30000) L_0x1daac20/d; +v0x1b94300_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers +v0x1b943e0_0 .net "b", 0 0, L_0x1db4340; alias, 1 drivers +v0x1b944a0_0 .net "carryout", 0 0, L_0x1daac20; alias, 1 drivers +v0x1b94540_0 .net "sum", 0 0, L_0x1daab60; alias, 1 drivers +S_0x1b94680 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b93e30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1daae90/d .functor XOR 1, L_0x1daab60, L_0x1daa6d0, C4<0>, C4<0>; +L_0x1daae90 .delay 1 (30000,30000,30000) L_0x1daae90/d; +L_0x1daafe0/d .functor AND 1, L_0x1daab60, L_0x1daa6d0, C4<1>, C4<1>; +L_0x1daafe0 .delay 1 (30000,30000,30000) L_0x1daafe0/d; +v0x1b948e0_0 .net "a", 0 0, L_0x1daab60; alias, 1 drivers +v0x1b94980_0 .net "b", 0 0, L_0x1daa6d0; alias, 1 drivers +v0x1b94a20_0 .net "carryout", 0 0, L_0x1daafe0; alias, 1 drivers +v0x1b94af0_0 .net "sum", 0 0, L_0x1daae90; alias, 1 drivers +S_0x1b95310 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b93bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1b9a700_0 .net "ands", 7 0, L_0x1db1c70; 1 drivers +v0x1b9a810_0 .net "in", 7 0, L_0x1ebf510; alias, 1 drivers +v0x1b9a8d0_0 .net "out", 0 0, L_0x1db3c70; alias, 1 drivers +v0x1b9a9a0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b95530 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b95310; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b97c60_0 .net "A", 7 0, L_0x1ebf510; alias, 1 drivers +v0x1b97d60_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b97e20_0 .net *"_s0", 0 0, L_0x1db0590; 1 drivers +v0x1b97ee0_0 .net *"_s12", 0 0, L_0x1db0f00; 1 drivers +v0x1b97fc0_0 .net *"_s16", 0 0, L_0x1db1260; 1 drivers +v0x1b980f0_0 .net *"_s20", 0 0, L_0x1db1570; 1 drivers +v0x1b981d0_0 .net *"_s24", 0 0, L_0x1db1960; 1 drivers +v0x1b982b0_0 .net *"_s28", 0 0, L_0x1db18f0; 1 drivers +v0x1b98390_0 .net *"_s4", 0 0, L_0x1db08a0; 1 drivers +v0x1b98500_0 .net *"_s8", 0 0, L_0x1db0bf0; 1 drivers +v0x1b985e0_0 .net "out", 7 0, L_0x1db1c70; alias, 1 drivers +L_0x1db0650 .part L_0x1ebf510, 0, 1; +L_0x1db07b0 .part v0x1d6daa0_0, 0, 1; +L_0x1db0960 .part L_0x1ebf510, 1, 1; +L_0x1db0b50 .part v0x1d6daa0_0, 1, 1; +L_0x1db0cb0 .part L_0x1ebf510, 2, 1; +L_0x1db0e10 .part v0x1d6daa0_0, 2, 1; +L_0x1db0fc0 .part L_0x1ebf510, 3, 1; +L_0x1db1120 .part v0x1d6daa0_0, 3, 1; +L_0x1db1320 .part L_0x1ebf510, 4, 1; +L_0x1db1480 .part v0x1d6daa0_0, 4, 1; +L_0x1db15e0 .part L_0x1ebf510, 5, 1; +L_0x1db1850 .part v0x1d6daa0_0, 5, 1; +L_0x1db1a20 .part L_0x1ebf510, 6, 1; +L_0x1db1b80 .part v0x1d6daa0_0, 6, 1; +LS_0x1db1c70_0_0 .concat8 [ 1 1 1 1], L_0x1db0590, L_0x1db08a0, L_0x1db0bf0, L_0x1db0f00; +LS_0x1db1c70_0_4 .concat8 [ 1 1 1 1], L_0x1db1260, L_0x1db1570, L_0x1db1960, L_0x1db18f0; +L_0x1db1c70 .concat8 [ 4 4 0 0], LS_0x1db1c70_0_0, LS_0x1db1c70_0_4; +L_0x1db2030 .part L_0x1ebf510, 7, 1; +L_0x1db2220 .part v0x1d6daa0_0, 7, 1; +S_0x1b95790 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b959a0 .param/l "i" 0 4 54, +C4<00>; +L_0x1db0590/d .functor AND 1, L_0x1db0650, L_0x1db07b0, C4<1>, C4<1>; +L_0x1db0590 .delay 1 (30000,30000,30000) L_0x1db0590/d; +v0x1b95a80_0 .net *"_s0", 0 0, L_0x1db0650; 1 drivers +v0x1b95b60_0 .net *"_s1", 0 0, L_0x1db07b0; 1 drivers +S_0x1b95c40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b95e50 .param/l "i" 0 4 54, +C4<01>; +L_0x1db08a0/d .functor AND 1, L_0x1db0960, L_0x1db0b50, C4<1>, C4<1>; +L_0x1db08a0 .delay 1 (30000,30000,30000) L_0x1db08a0/d; +v0x1b95f10_0 .net *"_s0", 0 0, L_0x1db0960; 1 drivers +v0x1b95ff0_0 .net *"_s1", 0 0, L_0x1db0b50; 1 drivers +S_0x1b960d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b962e0 .param/l "i" 0 4 54, +C4<010>; +L_0x1db0bf0/d .functor AND 1, L_0x1db0cb0, L_0x1db0e10, C4<1>, C4<1>; +L_0x1db0bf0 .delay 1 (30000,30000,30000) L_0x1db0bf0/d; +v0x1b96380_0 .net *"_s0", 0 0, L_0x1db0cb0; 1 drivers +v0x1b96460_0 .net *"_s1", 0 0, L_0x1db0e10; 1 drivers +S_0x1b96540 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b96750 .param/l "i" 0 4 54, +C4<011>; +L_0x1db0f00/d .functor AND 1, L_0x1db0fc0, L_0x1db1120, C4<1>, C4<1>; +L_0x1db0f00 .delay 1 (30000,30000,30000) L_0x1db0f00/d; +v0x1b96810_0 .net *"_s0", 0 0, L_0x1db0fc0; 1 drivers +v0x1b968f0_0 .net *"_s1", 0 0, L_0x1db1120; 1 drivers +S_0x1b969d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b96c30 .param/l "i" 0 4 54, +C4<0100>; +L_0x1db1260/d .functor AND 1, L_0x1db1320, L_0x1db1480, C4<1>, C4<1>; +L_0x1db1260 .delay 1 (30000,30000,30000) L_0x1db1260/d; +v0x1b96cf0_0 .net *"_s0", 0 0, L_0x1db1320; 1 drivers +v0x1b96dd0_0 .net *"_s1", 0 0, L_0x1db1480; 1 drivers +S_0x1b96eb0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b970c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1db1570/d .functor AND 1, L_0x1db15e0, L_0x1db1850, C4<1>, C4<1>; +L_0x1db1570 .delay 1 (30000,30000,30000) L_0x1db1570/d; +v0x1b97180_0 .net *"_s0", 0 0, L_0x1db15e0; 1 drivers +v0x1b97260_0 .net *"_s1", 0 0, L_0x1db1850; 1 drivers +S_0x1b97340 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b97550 .param/l "i" 0 4 54, +C4<0110>; +L_0x1db1960/d .functor AND 1, L_0x1db1a20, L_0x1db1b80, C4<1>, C4<1>; +L_0x1db1960 .delay 1 (30000,30000,30000) L_0x1db1960/d; +v0x1b97610_0 .net *"_s0", 0 0, L_0x1db1a20; 1 drivers +v0x1b976f0_0 .net *"_s1", 0 0, L_0x1db1b80; 1 drivers +S_0x1b977d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b95530; + .timescale -9 -12; +P_0x1b979e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1db18f0/d .functor AND 1, L_0x1db2030, L_0x1db2220, C4<1>, C4<1>; +L_0x1db18f0 .delay 1 (30000,30000,30000) L_0x1db18f0/d; +v0x1b97aa0_0 .net *"_s0", 0 0, L_0x1db2030; 1 drivers +v0x1b97b80_0 .net *"_s1", 0 0, L_0x1db2220; 1 drivers +S_0x1b98740 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b95310; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1db3c70/d .functor OR 1, L_0x1db3d30, L_0x1db3ee0, C4<0>, C4<0>; +L_0x1db3c70 .delay 1 (30000,30000,30000) L_0x1db3c70/d; +v0x1b9a290_0 .net *"_s10", 0 0, L_0x1db3d30; 1 drivers +v0x1b9a370_0 .net *"_s12", 0 0, L_0x1db3ee0; 1 drivers +v0x1b9a450_0 .net "in", 7 0, L_0x1db1c70; alias, 1 drivers +v0x1b9a520_0 .net "ors", 1 0, L_0x1db3a90; 1 drivers +v0x1b9a5e0_0 .net "out", 0 0, L_0x1db3c70; alias, 1 drivers +L_0x1db2e60 .part L_0x1db1c70, 0, 4; +L_0x1db3a90 .concat8 [ 1 1 0 0], L_0x1db2b50, L_0x1db3780; +L_0x1db3bd0 .part L_0x1db1c70, 4, 4; +L_0x1db3d30 .part L_0x1db3a90, 0, 1; +L_0x1db3ee0 .part L_0x1db3a90, 1, 1; +S_0x1b98900 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b98740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1db2310/d .functor OR 1, L_0x1db23d0, L_0x1db2530, C4<0>, C4<0>; +L_0x1db2310 .delay 1 (30000,30000,30000) L_0x1db2310/d; +L_0x1db2760/d .functor OR 1, L_0x1db2870, L_0x1db29d0, C4<0>, C4<0>; +L_0x1db2760 .delay 1 (30000,30000,30000) L_0x1db2760/d; +L_0x1db2b50/d .functor OR 1, L_0x1db2bc0, L_0x1db2d70, C4<0>, C4<0>; +L_0x1db2b50 .delay 1 (30000,30000,30000) L_0x1db2b50/d; +v0x1b98b50_0 .net *"_s0", 0 0, L_0x1db2310; 1 drivers +v0x1b98c50_0 .net *"_s10", 0 0, L_0x1db2870; 1 drivers +v0x1b98d30_0 .net *"_s12", 0 0, L_0x1db29d0; 1 drivers +v0x1b98df0_0 .net *"_s14", 0 0, L_0x1db2bc0; 1 drivers +v0x1b98ed0_0 .net *"_s16", 0 0, L_0x1db2d70; 1 drivers +v0x1b99000_0 .net *"_s3", 0 0, L_0x1db23d0; 1 drivers +v0x1b990e0_0 .net *"_s5", 0 0, L_0x1db2530; 1 drivers +v0x1b991c0_0 .net *"_s6", 0 0, L_0x1db2760; 1 drivers +v0x1b992a0_0 .net "in", 3 0, L_0x1db2e60; 1 drivers +v0x1b99410_0 .net "ors", 1 0, L_0x1db2670; 1 drivers +v0x1b994f0_0 .net "out", 0 0, L_0x1db2b50; 1 drivers +L_0x1db23d0 .part L_0x1db2e60, 0, 1; +L_0x1db2530 .part L_0x1db2e60, 1, 1; +L_0x1db2670 .concat8 [ 1 1 0 0], L_0x1db2310, L_0x1db2760; +L_0x1db2870 .part L_0x1db2e60, 2, 1; +L_0x1db29d0 .part L_0x1db2e60, 3, 1; +L_0x1db2bc0 .part L_0x1db2670, 0, 1; +L_0x1db2d70 .part L_0x1db2670, 1, 1; +S_0x1b99610 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b98740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1db2f90/d .functor OR 1, L_0x1db3000, L_0x1db3160, C4<0>, C4<0>; +L_0x1db2f90 .delay 1 (30000,30000,30000) L_0x1db2f90/d; +L_0x1db3390/d .functor OR 1, L_0x1db34a0, L_0x1db3600, C4<0>, C4<0>; +L_0x1db3390 .delay 1 (30000,30000,30000) L_0x1db3390/d; +L_0x1db3780/d .functor OR 1, L_0x1db37f0, L_0x1db39a0, C4<0>, C4<0>; +L_0x1db3780 .delay 1 (30000,30000,30000) L_0x1db3780/d; +v0x1b997d0_0 .net *"_s0", 0 0, L_0x1db2f90; 1 drivers +v0x1b998d0_0 .net *"_s10", 0 0, L_0x1db34a0; 1 drivers +v0x1b999b0_0 .net *"_s12", 0 0, L_0x1db3600; 1 drivers +v0x1b99a70_0 .net *"_s14", 0 0, L_0x1db37f0; 1 drivers +v0x1b99b50_0 .net *"_s16", 0 0, L_0x1db39a0; 1 drivers +v0x1b99c80_0 .net *"_s3", 0 0, L_0x1db3000; 1 drivers +v0x1b99d60_0 .net *"_s5", 0 0, L_0x1db3160; 1 drivers +v0x1b99e40_0 .net *"_s6", 0 0, L_0x1db3390; 1 drivers +v0x1b99f20_0 .net "in", 3 0, L_0x1db3bd0; 1 drivers +v0x1b9a090_0 .net "ors", 1 0, L_0x1db32a0; 1 drivers +v0x1b9a170_0 .net "out", 0 0, L_0x1db3780; 1 drivers +L_0x1db3000 .part L_0x1db3bd0, 0, 1; +L_0x1db3160 .part L_0x1db3bd0, 1, 1; +L_0x1db32a0 .concat8 [ 1 1 0 0], L_0x1db2f90, L_0x1db3390; +L_0x1db34a0 .part L_0x1db3bd0, 2, 1; +L_0x1db3600 .part L_0x1db3bd0, 3, 1; +L_0x1db37f0 .part L_0x1db32a0, 0, 1; +L_0x1db39a0 .part L_0x1db32a0, 1, 1; +S_0x1b9aa80 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b93bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1ba00b0_0 .net "ands", 7 0, L_0x1dae230; 1 drivers +v0x1ba01c0_0 .net "in", 7 0, L_0x1dac710; alias, 1 drivers +v0x1ba0280_0 .net "out", 0 0, L_0x1db0230; alias, 1 drivers +v0x1ba0350_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1b9acd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b9aa80; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1b9d410_0 .net "A", 7 0, L_0x1dac710; alias, 1 drivers +v0x1b9d510_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b6a5e0_0 .net *"_s0", 0 0, L_0x1dacaa0; 1 drivers +v0x1b6a6a0_0 .net *"_s12", 0 0, L_0x1dad460; 1 drivers +v0x1b9d9e0_0 .net *"_s16", 0 0, L_0x1dad7c0; 1 drivers +v0x1b9daa0_0 .net *"_s20", 0 0, L_0x1dadbf0; 1 drivers +v0x1b9db80_0 .net *"_s24", 0 0, L_0x1dadf20; 1 drivers +v0x1b9dc60_0 .net *"_s28", 0 0, L_0x1dadeb0; 1 drivers +v0x1b9dd40_0 .net *"_s4", 0 0, L_0x1dace40; 1 drivers +v0x1b9deb0_0 .net *"_s8", 0 0, L_0x1dad150; 1 drivers +v0x1b9df90_0 .net "out", 7 0, L_0x1dae230; alias, 1 drivers +L_0x1dacbb0 .part L_0x1dac710, 0, 1; +L_0x1dacda0 .part v0x1d6daa0_0, 0, 1; +L_0x1dacf00 .part L_0x1dac710, 1, 1; +L_0x1dad060 .part v0x1d6daa0_0, 1, 1; +L_0x1dad210 .part L_0x1dac710, 2, 1; +L_0x1dad370 .part v0x1d6daa0_0, 2, 1; +L_0x1dad520 .part L_0x1dac710, 3, 1; +L_0x1dad680 .part v0x1d6daa0_0, 3, 1; +L_0x1dad880 .part L_0x1dac710, 4, 1; +L_0x1dadaf0 .part v0x1d6daa0_0, 4, 1; +L_0x1dadc60 .part L_0x1dac710, 5, 1; +L_0x1daddc0 .part v0x1d6daa0_0, 5, 1; +L_0x1dadfe0 .part L_0x1dac710, 6, 1; +L_0x1dae140 .part v0x1d6daa0_0, 6, 1; +LS_0x1dae230_0_0 .concat8 [ 1 1 1 1], L_0x1dacaa0, L_0x1dace40, L_0x1dad150, L_0x1dad460; +LS_0x1dae230_0_4 .concat8 [ 1 1 1 1], L_0x1dad7c0, L_0x1dadbf0, L_0x1dadf20, L_0x1dadeb0; +L_0x1dae230 .concat8 [ 4 4 0 0], LS_0x1dae230_0_0, LS_0x1dae230_0_4; +L_0x1dae5f0 .part L_0x1dac710, 7, 1; +L_0x1dae7e0 .part v0x1d6daa0_0, 7, 1; +S_0x1b9af10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9b120 .param/l "i" 0 4 54, +C4<00>; +L_0x1dacaa0/d .functor AND 1, L_0x1dacbb0, L_0x1dacda0, C4<1>, C4<1>; +L_0x1dacaa0 .delay 1 (30000,30000,30000) L_0x1dacaa0/d; +v0x1b9b200_0 .net *"_s0", 0 0, L_0x1dacbb0; 1 drivers +v0x1b9b2e0_0 .net *"_s1", 0 0, L_0x1dacda0; 1 drivers +S_0x1b9b3c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9b5d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1dace40/d .functor AND 1, L_0x1dacf00, L_0x1dad060, C4<1>, C4<1>; +L_0x1dace40 .delay 1 (30000,30000,30000) L_0x1dace40/d; +v0x1b9b690_0 .net *"_s0", 0 0, L_0x1dacf00; 1 drivers +v0x1b9b770_0 .net *"_s1", 0 0, L_0x1dad060; 1 drivers +S_0x1b9b850 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9ba90 .param/l "i" 0 4 54, +C4<010>; +L_0x1dad150/d .functor AND 1, L_0x1dad210, L_0x1dad370, C4<1>, C4<1>; +L_0x1dad150 .delay 1 (30000,30000,30000) L_0x1dad150/d; +v0x1b9bb30_0 .net *"_s0", 0 0, L_0x1dad210; 1 drivers +v0x1b9bc10_0 .net *"_s1", 0 0, L_0x1dad370; 1 drivers +S_0x1b9bcf0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9bf00 .param/l "i" 0 4 54, +C4<011>; +L_0x1dad460/d .functor AND 1, L_0x1dad520, L_0x1dad680, C4<1>, C4<1>; +L_0x1dad460 .delay 1 (30000,30000,30000) L_0x1dad460/d; +v0x1b9bfc0_0 .net *"_s0", 0 0, L_0x1dad520; 1 drivers +v0x1b9c0a0_0 .net *"_s1", 0 0, L_0x1dad680; 1 drivers +S_0x1b9c180 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9c3e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dad7c0/d .functor AND 1, L_0x1dad880, L_0x1dadaf0, C4<1>, C4<1>; +L_0x1dad7c0 .delay 1 (30000,30000,30000) L_0x1dad7c0/d; +v0x1b9c4a0_0 .net *"_s0", 0 0, L_0x1dad880; 1 drivers +v0x1b9c580_0 .net *"_s1", 0 0, L_0x1dadaf0; 1 drivers +S_0x1b9c660 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9c870 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dadbf0/d .functor AND 1, L_0x1dadc60, L_0x1daddc0, C4<1>, C4<1>; +L_0x1dadbf0 .delay 1 (30000,30000,30000) L_0x1dadbf0/d; +v0x1b9c930_0 .net *"_s0", 0 0, L_0x1dadc60; 1 drivers +v0x1b9ca10_0 .net *"_s1", 0 0, L_0x1daddc0; 1 drivers +S_0x1b9caf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9cd00 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dadf20/d .functor AND 1, L_0x1dadfe0, L_0x1dae140, C4<1>, C4<1>; +L_0x1dadf20 .delay 1 (30000,30000,30000) L_0x1dadf20/d; +v0x1b9cdc0_0 .net *"_s0", 0 0, L_0x1dadfe0; 1 drivers +v0x1b9cea0_0 .net *"_s1", 0 0, L_0x1dae140; 1 drivers +S_0x1b9cf80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b9acd0; + .timescale -9 -12; +P_0x1b9d190 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dadeb0/d .functor AND 1, L_0x1dae5f0, L_0x1dae7e0, C4<1>, C4<1>; +L_0x1dadeb0 .delay 1 (30000,30000,30000) L_0x1dadeb0/d; +v0x1b9d250_0 .net *"_s0", 0 0, L_0x1dae5f0; 1 drivers +v0x1b9d330_0 .net *"_s1", 0 0, L_0x1dae7e0; 1 drivers +S_0x1b9e0f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b9aa80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1db0230/d .functor OR 1, L_0x1db02f0, L_0x1db04a0, C4<0>, C4<0>; +L_0x1db0230 .delay 1 (30000,30000,30000) L_0x1db0230/d; +v0x1b9fc40_0 .net *"_s10", 0 0, L_0x1db02f0; 1 drivers +v0x1b9fd20_0 .net *"_s12", 0 0, L_0x1db04a0; 1 drivers +v0x1b9fe00_0 .net "in", 7 0, L_0x1dae230; alias, 1 drivers +v0x1b9fed0_0 .net "ors", 1 0, L_0x1db0050; 1 drivers +v0x1b9ff90_0 .net "out", 0 0, L_0x1db0230; alias, 1 drivers +L_0x1daf420 .part L_0x1dae230, 0, 4; +L_0x1db0050 .concat8 [ 1 1 0 0], L_0x1daf110, L_0x1dafd40; +L_0x1db0190 .part L_0x1dae230, 4, 4; +L_0x1db02f0 .part L_0x1db0050, 0, 1; +L_0x1db04a0 .part L_0x1db0050, 1, 1; +S_0x1b9e2b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b9e0f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dae8d0/d .functor OR 1, L_0x1dae990, L_0x1daeaf0, C4<0>, C4<0>; +L_0x1dae8d0 .delay 1 (30000,30000,30000) L_0x1dae8d0/d; +L_0x1daed20/d .functor OR 1, L_0x1daee30, L_0x1daef90, C4<0>, C4<0>; +L_0x1daed20 .delay 1 (30000,30000,30000) L_0x1daed20/d; +L_0x1daf110/d .functor OR 1, L_0x1daf180, L_0x1daf330, C4<0>, C4<0>; +L_0x1daf110 .delay 1 (30000,30000,30000) L_0x1daf110/d; +v0x1b9e500_0 .net *"_s0", 0 0, L_0x1dae8d0; 1 drivers +v0x1b9e600_0 .net *"_s10", 0 0, L_0x1daee30; 1 drivers +v0x1b9e6e0_0 .net *"_s12", 0 0, L_0x1daef90; 1 drivers +v0x1b9e7a0_0 .net *"_s14", 0 0, L_0x1daf180; 1 drivers +v0x1b9e880_0 .net *"_s16", 0 0, L_0x1daf330; 1 drivers +v0x1b9e9b0_0 .net *"_s3", 0 0, L_0x1dae990; 1 drivers +v0x1b9ea90_0 .net *"_s5", 0 0, L_0x1daeaf0; 1 drivers +v0x1b9eb70_0 .net *"_s6", 0 0, L_0x1daed20; 1 drivers +v0x1b9ec50_0 .net "in", 3 0, L_0x1daf420; 1 drivers +v0x1b9edc0_0 .net "ors", 1 0, L_0x1daec30; 1 drivers +v0x1b9eea0_0 .net "out", 0 0, L_0x1daf110; 1 drivers +L_0x1dae990 .part L_0x1daf420, 0, 1; +L_0x1daeaf0 .part L_0x1daf420, 1, 1; +L_0x1daec30 .concat8 [ 1 1 0 0], L_0x1dae8d0, L_0x1daed20; +L_0x1daee30 .part L_0x1daf420, 2, 1; +L_0x1daef90 .part L_0x1daf420, 3, 1; +L_0x1daf180 .part L_0x1daec30, 0, 1; +L_0x1daf330 .part L_0x1daec30, 1, 1; +S_0x1b9efc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b9e0f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1daf550/d .functor OR 1, L_0x1daf5c0, L_0x1daf720, C4<0>, C4<0>; +L_0x1daf550 .delay 1 (30000,30000,30000) L_0x1daf550/d; +L_0x1daf950/d .functor OR 1, L_0x1dafa60, L_0x1dafbc0, C4<0>, C4<0>; +L_0x1daf950 .delay 1 (30000,30000,30000) L_0x1daf950/d; +L_0x1dafd40/d .functor OR 1, L_0x1dafdb0, L_0x1daff60, C4<0>, C4<0>; +L_0x1dafd40 .delay 1 (30000,30000,30000) L_0x1dafd40/d; +v0x1b9f180_0 .net *"_s0", 0 0, L_0x1daf550; 1 drivers +v0x1b9f280_0 .net *"_s10", 0 0, L_0x1dafa60; 1 drivers +v0x1b9f360_0 .net *"_s12", 0 0, L_0x1dafbc0; 1 drivers +v0x1b9f420_0 .net *"_s14", 0 0, L_0x1dafdb0; 1 drivers +v0x1b9f500_0 .net *"_s16", 0 0, L_0x1daff60; 1 drivers +v0x1b9f630_0 .net *"_s3", 0 0, L_0x1daf5c0; 1 drivers +v0x1b9f710_0 .net *"_s5", 0 0, L_0x1daf720; 1 drivers +v0x1b9f7f0_0 .net *"_s6", 0 0, L_0x1daf950; 1 drivers +v0x1b9f8d0_0 .net "in", 3 0, L_0x1db0190; 1 drivers +v0x1b9fa40_0 .net "ors", 1 0, L_0x1daf860; 1 drivers +v0x1b9fb20_0 .net "out", 0 0, L_0x1dafd40; 1 drivers +L_0x1daf5c0 .part L_0x1db0190, 0, 1; +L_0x1daf720 .part L_0x1db0190, 1, 1; +L_0x1daf860 .concat8 [ 1 1 0 0], L_0x1daf550, L_0x1daf950; +L_0x1dafa60 .part L_0x1db0190, 2, 1; +L_0x1dafbc0 .part L_0x1db0190, 3, 1; +L_0x1dafdb0 .part L_0x1daf860, 0, 1; +L_0x1daff60 .part L_0x1daf860, 1, 1; +S_0x1ba0430 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b93bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1daba80/d .functor XNOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; +L_0x1daba80 .delay 1 (20000,20000,20000) L_0x1daba80/d; +L_0x1dabcf0/d .functor AND 1, L_0x1db40d0, L_0x1daa970, C4<1>, C4<1>; +L_0x1dabcf0 .delay 1 (30000,30000,30000) L_0x1dabcf0/d; +L_0x1dabd60/d .functor AND 1, L_0x1daba80, L_0x1daa6d0, C4<1>, C4<1>; +L_0x1dabd60 .delay 1 (30000,30000,30000) L_0x1dabd60/d; +L_0x1dabec0/d .functor OR 1, L_0x1dabd60, L_0x1dabcf0, C4<0>, C4<0>; +L_0x1dabec0 .delay 1 (30000,30000,30000) L_0x1dabec0/d; +v0x1ba06e0_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers +v0x1ba07d0_0 .net "a_", 0 0, L_0x1daa810; alias, 1 drivers +v0x1ba0890_0 .net "b", 0 0, L_0x1db4340; alias, 1 drivers +v0x1ba0980_0 .net "b_", 0 0, L_0x1daa970; alias, 1 drivers +v0x1ba0a20_0 .net "carryin", 0 0, L_0x1daa6d0; alias, 1 drivers +v0x1ba0b60_0 .net "eq", 0 0, L_0x1daba80; 1 drivers +v0x1ba0c20_0 .net "lt", 0 0, L_0x1dabcf0; 1 drivers +v0x1ba0ce0_0 .net "out", 0 0, L_0x1dabec0; 1 drivers +v0x1ba0da0_0 .net "w0", 0 0, L_0x1dabd60; 1 drivers +S_0x1ba0ff0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b93bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dab860/d .functor OR 1, L_0x1dab360, L_0x1ba2250, C4<0>, C4<0>; +L_0x1dab860 .delay 1 (30000,30000,30000) L_0x1dab860/d; +v0x1ba1de0_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers +v0x1ba1f30_0 .net "b", 0 0, L_0x1daa970; alias, 1 drivers +v0x1ba1ff0_0 .net "c1", 0 0, L_0x1dab360; 1 drivers +v0x1ba2090_0 .net "c2", 0 0, L_0x1ba2250; 1 drivers +v0x1ba2160_0 .net "carryin", 0 0, L_0x1daa6d0; alias, 1 drivers +v0x1ba22e0_0 .net "carryout", 0 0, L_0x1dab860; 1 drivers +v0x1ba2380_0 .net "s1", 0 0, L_0x1dab2a0; 1 drivers +v0x1ba2420_0 .net "sum", 0 0, L_0x1dab4c0; 1 drivers +S_0x1ba1240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ba0ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dab2a0/d .functor XOR 1, L_0x1db40d0, L_0x1daa970, C4<0>, C4<0>; +L_0x1dab2a0 .delay 1 (30000,30000,30000) L_0x1dab2a0/d; +L_0x1dab360/d .functor AND 1, L_0x1db40d0, L_0x1daa970, C4<1>, C4<1>; +L_0x1dab360 .delay 1 (30000,30000,30000) L_0x1dab360/d; +v0x1ba14a0_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers +v0x1ba1560_0 .net "b", 0 0, L_0x1daa970; alias, 1 drivers +v0x1ba1620_0 .net "carryout", 0 0, L_0x1dab360; alias, 1 drivers +v0x1ba16c0_0 .net "sum", 0 0, L_0x1dab2a0; alias, 1 drivers +S_0x1ba17f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ba0ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dab4c0/d .functor XOR 1, L_0x1dab2a0, L_0x1daa6d0, C4<0>, C4<0>; +L_0x1dab4c0 .delay 1 (30000,30000,30000) L_0x1dab4c0/d; +L_0x1ba2250/d .functor AND 1, L_0x1dab2a0, L_0x1daa6d0, C4<1>, C4<1>; +L_0x1ba2250 .delay 1 (30000,30000,30000) L_0x1ba2250/d; +v0x1ba1a50_0 .net "a", 0 0, L_0x1dab2a0; alias, 1 drivers +v0x1ba1b20_0 .net "b", 0 0, L_0x1daa6d0; alias, 1 drivers +v0x1ba1bc0_0 .net "carryout", 0 0, L_0x1ba2250; alias, 1 drivers +v0x1ba1c90_0 .net "sum", 0 0, L_0x1dab4c0; alias, 1 drivers +S_0x1ba3840 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b938e0; + .timescale -9 -12; +L_0x7f72592da6d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1db4170/d .functor OR 1, L_0x7f72592da6d8, L_0x7f72592da720, C4<0>, C4<0>; +L_0x1db4170 .delay 1 (30000,30000,30000) L_0x1db4170/d; +v0x1ba3a30_0 .net/2u *"_s0", 0 0, L_0x7f72592da6d8; 1 drivers +v0x1ba3b10_0 .net/2u *"_s2", 0 0, L_0x7f72592da720; 1 drivers +S_0x1ba3bf0 .scope generate, "alu_slices[7]" "alu_slices[7]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1ba3e00 .param/l "i" 0 3 37, +C4<0111>; +S_0x1ba3ec0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ba3bf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1db4640/d .functor NOT 1, L_0x1dbde70, C4<0>, C4<0>, C4<0>; +L_0x1db4640 .delay 1 (10000,10000,10000) L_0x1db4640/d; +L_0x1db4750/d .functor NOT 1, L_0x1db44f0, C4<0>, C4<0>, C4<0>; +L_0x1db4750 .delay 1 (10000,10000,10000) L_0x1db4750/d; +L_0x1db57a0/d .functor XOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; +L_0x1db57a0 .delay 1 (30000,30000,30000) L_0x1db57a0/d; +L_0x7f72592da768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da7b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1db5e50/d .functor OR 1, L_0x7f72592da768, L_0x7f72592da7b0, C4<0>, C4<0>; +L_0x1db5e50 .delay 1 (30000,30000,30000) L_0x1db5e50/d; +L_0x1db6050/d .functor AND 1, L_0x1dbde70, L_0x1db44f0, C4<1>, C4<1>; +L_0x1db6050 .delay 1 (30000,30000,30000) L_0x1db6050/d; +L_0x1db6110/d .functor NAND 1, L_0x1dbde70, L_0x1db44f0, C4<1>, C4<1>; +L_0x1db6110 .delay 1 (20000,20000,20000) L_0x1db6110/d; +L_0x1db6270/d .functor XOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; +L_0x1db6270 .delay 1 (20000,20000,20000) L_0x1db6270/d; +L_0x1db6720/d .functor OR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; +L_0x1db6720 .delay 1 (30000,30000,30000) L_0x1db6720/d; +L_0x1dbdd70/d .functor NOT 1, L_0x1db9ef0, C4<0>, C4<0>, C4<0>; +L_0x1dbdd70 .delay 1 (10000,10000,10000) L_0x1dbdd70/d; +v0x1bb2600_0 .net "A", 0 0, L_0x1dbde70; 1 drivers +v0x1bb26c0_0 .net "A_", 0 0, L_0x1db4640; 1 drivers +v0x1bb2780_0 .net "B", 0 0, L_0x1db44f0; 1 drivers +v0x1bb2850_0 .net "B_", 0 0, L_0x1db4750; 1 drivers +v0x1bb28f0_0 .net *"_s12", 0 0, L_0x1db5e50; 1 drivers +v0x1bb29e0_0 .net/2s *"_s14", 0 0, L_0x7f72592da768; 1 drivers +v0x1bb2aa0_0 .net/2s *"_s16", 0 0, L_0x7f72592da7b0; 1 drivers +v0x1bb2b80_0 .net *"_s18", 0 0, L_0x1db6050; 1 drivers +v0x1bb2c60_0 .net *"_s20", 0 0, L_0x1db6110; 1 drivers +v0x1bb2dd0_0 .net *"_s22", 0 0, L_0x1db6270; 1 drivers +v0x1bb2eb0_0 .net *"_s24", 0 0, L_0x1db6720; 1 drivers +o0x7f72593667f8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1bb2f90_0 name=_s30 +o0x7f7259366828 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1bb3070_0 name=_s32 +v0x1bb3150_0 .net *"_s8", 0 0, L_0x1db57a0; 1 drivers +v0x1bb3230_0 .net "carryin", 0 0, L_0x1dbe090; 1 drivers +v0x1bb32d0_0 .net "carryout", 0 0, L_0x1dbda10; 1 drivers +v0x1bb3370_0 .net "carryouts", 7 0, L_0x1ebf6a0; 1 drivers +v0x1bb3520_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bb35c0_0 .net "result", 0 0, L_0x1db9ef0; 1 drivers +v0x1bb36b0_0 .net "results", 7 0, L_0x1db64f0; 1 drivers +v0x1bb37c0_0 .net "zero", 0 0, L_0x1dbdd70; 1 drivers +LS_0x1db64f0_0_0 .concat8 [ 1 1 1 1], L_0x1db4c70, L_0x1db52a0, L_0x1db57a0, L_0x1db5e50; +LS_0x1db64f0_0_4 .concat8 [ 1 1 1 1], L_0x1db6050, L_0x1db6110, L_0x1db6270, L_0x1db6720; +L_0x1db64f0 .concat8 [ 4 4 0 0], LS_0x1db64f0_0_0, LS_0x1db64f0_0_4; +LS_0x1ebf6a0_0_0 .concat [ 1 1 1 1], L_0x1db4f20, L_0x1db5640, o0x7f72593667f8, L_0x1db5ca0; +LS_0x1ebf6a0_0_4 .concat [ 4 0 0 0], o0x7f7259366828; +L_0x1ebf6a0 .concat [ 4 4 0 0], LS_0x1ebf6a0_0_0, LS_0x1ebf6a0_0_4; +S_0x1ba4140 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1ba3ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1db4f20/d .functor OR 1, L_0x1db4a00, L_0x1db4dc0, C4<0>, C4<0>; +L_0x1db4f20 .delay 1 (30000,30000,30000) L_0x1db4f20/d; +v0x1ba4f70_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers +v0x1ba5030_0 .net "b", 0 0, L_0x1db44f0; alias, 1 drivers +v0x1ba5100_0 .net "c1", 0 0, L_0x1db4a00; 1 drivers +v0x1ba5200_0 .net "c2", 0 0, L_0x1db4dc0; 1 drivers +v0x1ba52d0_0 .net "carryin", 0 0, L_0x1dbe090; alias, 1 drivers +v0x1ba53c0_0 .net "carryout", 0 0, L_0x1db4f20; 1 drivers +v0x1ba5460_0 .net "s1", 0 0, L_0x1db4940; 1 drivers +v0x1ba5550_0 .net "sum", 0 0, L_0x1db4c70; 1 drivers +S_0x1ba43b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ba4140; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1db4940/d .functor XOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; +L_0x1db4940 .delay 1 (30000,30000,30000) L_0x1db4940/d; +L_0x1db4a00/d .functor AND 1, L_0x1dbde70, L_0x1db44f0, C4<1>, C4<1>; +L_0x1db4a00 .delay 1 (30000,30000,30000) L_0x1db4a00/d; +v0x1ba4610_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers +v0x1ba46f0_0 .net "b", 0 0, L_0x1db44f0; alias, 1 drivers +v0x1ba47b0_0 .net "carryout", 0 0, L_0x1db4a00; alias, 1 drivers +v0x1ba4850_0 .net "sum", 0 0, L_0x1db4940; alias, 1 drivers +S_0x1ba4990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ba4140; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1db4c70/d .functor XOR 1, L_0x1db4940, L_0x1dbe090, C4<0>, C4<0>; +L_0x1db4c70 .delay 1 (30000,30000,30000) L_0x1db4c70/d; +L_0x1db4dc0/d .functor AND 1, L_0x1db4940, L_0x1dbe090, C4<1>, C4<1>; +L_0x1db4dc0 .delay 1 (30000,30000,30000) L_0x1db4dc0/d; +v0x1ba4bf0_0 .net "a", 0 0, L_0x1db4940; alias, 1 drivers +v0x1ba4c90_0 .net "b", 0 0, L_0x1dbe090; alias, 1 drivers +v0x1ba4d30_0 .net "carryout", 0 0, L_0x1db4dc0; alias, 1 drivers +v0x1ba4e00_0 .net "sum", 0 0, L_0x1db4c70; alias, 1 drivers +S_0x1ba5620 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1ba3ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1baaa20_0 .net "ands", 7 0, L_0x1dbba10; 1 drivers +v0x1baab30_0 .net "in", 7 0, L_0x1ebf6a0; alias, 1 drivers +v0x1baabf0_0 .net "out", 0 0, L_0x1dbda10; alias, 1 drivers +v0x1baacc0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1ba5840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ba5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1ba7f70_0 .net "A", 7 0, L_0x1ebf6a0; alias, 1 drivers +v0x1ba8070_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ba8130_0 .net *"_s0", 0 0, L_0x1dba250; 1 drivers +v0x1ba81f0_0 .net *"_s12", 0 0, L_0x1dbabc0; 1 drivers +v0x1ba82d0_0 .net *"_s16", 0 0, L_0x1dbaf20; 1 drivers +v0x1ba8400_0 .net *"_s20", 0 0, L_0x1dbb290; 1 drivers +v0x1ba84e0_0 .net *"_s24", 0 0, L_0x1dbb680; 1 drivers +v0x1ba85c0_0 .net *"_s28", 0 0, L_0x1dbb610; 1 drivers +v0x1ba86a0_0 .net *"_s4", 0 0, L_0x1dba560; 1 drivers +v0x1ba8810_0 .net *"_s8", 0 0, L_0x1dba8b0; 1 drivers +v0x1ba88f0_0 .net "out", 7 0, L_0x1dbba10; alias, 1 drivers +L_0x1dba310 .part L_0x1ebf6a0, 0, 1; +L_0x1dba470 .part v0x1d6daa0_0, 0, 1; +L_0x1dba620 .part L_0x1ebf6a0, 1, 1; +L_0x1dba810 .part v0x1d6daa0_0, 1, 1; +L_0x1dba970 .part L_0x1ebf6a0, 2, 1; +L_0x1dbaad0 .part v0x1d6daa0_0, 2, 1; +L_0x1dbac80 .part L_0x1ebf6a0, 3, 1; +L_0x1dbade0 .part v0x1d6daa0_0, 3, 1; +L_0x1dbafe0 .part L_0x1ebf6a0, 4, 1; +L_0x1dbb140 .part v0x1d6daa0_0, 4, 1; +L_0x1dbb300 .part L_0x1ebf6a0, 5, 1; +L_0x1dbb570 .part v0x1d6daa0_0, 5, 1; +L_0x1dbb740 .part L_0x1ebf6a0, 6, 1; +L_0x1dbb8a0 .part v0x1d6daa0_0, 6, 1; +LS_0x1dbba10_0_0 .concat8 [ 1 1 1 1], L_0x1dba250, L_0x1dba560, L_0x1dba8b0, L_0x1dbabc0; +LS_0x1dbba10_0_4 .concat8 [ 1 1 1 1], L_0x1dbaf20, L_0x1dbb290, L_0x1dbb680, L_0x1dbb610; +L_0x1dbba10 .concat8 [ 4 4 0 0], LS_0x1dbba10_0_0, LS_0x1dbba10_0_4; +L_0x1dbbdd0 .part L_0x1ebf6a0, 7, 1; +L_0x1dbbfc0 .part v0x1d6daa0_0, 7, 1; +S_0x1ba5aa0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba5cb0 .param/l "i" 0 4 54, +C4<00>; +L_0x1dba250/d .functor AND 1, L_0x1dba310, L_0x1dba470, C4<1>, C4<1>; +L_0x1dba250 .delay 1 (30000,30000,30000) L_0x1dba250/d; +v0x1ba5d90_0 .net *"_s0", 0 0, L_0x1dba310; 1 drivers +v0x1ba5e70_0 .net *"_s1", 0 0, L_0x1dba470; 1 drivers +S_0x1ba5f50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba6160 .param/l "i" 0 4 54, +C4<01>; +L_0x1dba560/d .functor AND 1, L_0x1dba620, L_0x1dba810, C4<1>, C4<1>; +L_0x1dba560 .delay 1 (30000,30000,30000) L_0x1dba560/d; +v0x1ba6220_0 .net *"_s0", 0 0, L_0x1dba620; 1 drivers +v0x1ba6300_0 .net *"_s1", 0 0, L_0x1dba810; 1 drivers +S_0x1ba63e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba65f0 .param/l "i" 0 4 54, +C4<010>; +L_0x1dba8b0/d .functor AND 1, L_0x1dba970, L_0x1dbaad0, C4<1>, C4<1>; +L_0x1dba8b0 .delay 1 (30000,30000,30000) L_0x1dba8b0/d; +v0x1ba6690_0 .net *"_s0", 0 0, L_0x1dba970; 1 drivers +v0x1ba6770_0 .net *"_s1", 0 0, L_0x1dbaad0; 1 drivers +S_0x1ba6850 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba6a60 .param/l "i" 0 4 54, +C4<011>; +L_0x1dbabc0/d .functor AND 1, L_0x1dbac80, L_0x1dbade0, C4<1>, C4<1>; +L_0x1dbabc0 .delay 1 (30000,30000,30000) L_0x1dbabc0/d; +v0x1ba6b20_0 .net *"_s0", 0 0, L_0x1dbac80; 1 drivers +v0x1ba6c00_0 .net *"_s1", 0 0, L_0x1dbade0; 1 drivers +S_0x1ba6ce0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba6f40 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dbaf20/d .functor AND 1, L_0x1dbafe0, L_0x1dbb140, C4<1>, C4<1>; +L_0x1dbaf20 .delay 1 (30000,30000,30000) L_0x1dbaf20/d; +v0x1ba7000_0 .net *"_s0", 0 0, L_0x1dbafe0; 1 drivers +v0x1ba70e0_0 .net *"_s1", 0 0, L_0x1dbb140; 1 drivers +S_0x1ba71c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba73d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dbb290/d .functor AND 1, L_0x1dbb300, L_0x1dbb570, C4<1>, C4<1>; +L_0x1dbb290 .delay 1 (30000,30000,30000) L_0x1dbb290/d; +v0x1ba7490_0 .net *"_s0", 0 0, L_0x1dbb300; 1 drivers +v0x1ba7570_0 .net *"_s1", 0 0, L_0x1dbb570; 1 drivers +S_0x1ba7650 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba7860 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dbb680/d .functor AND 1, L_0x1dbb740, L_0x1dbb8a0, C4<1>, C4<1>; +L_0x1dbb680 .delay 1 (30000,30000,30000) L_0x1dbb680/d; +v0x1ba7920_0 .net *"_s0", 0 0, L_0x1dbb740; 1 drivers +v0x1ba7a00_0 .net *"_s1", 0 0, L_0x1dbb8a0; 1 drivers +S_0x1ba7ae0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ba5840; + .timescale -9 -12; +P_0x1ba7cf0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dbb610/d .functor AND 1, L_0x1dbbdd0, L_0x1dbbfc0, C4<1>, C4<1>; +L_0x1dbb610 .delay 1 (30000,30000,30000) L_0x1dbb610/d; +v0x1ba7db0_0 .net *"_s0", 0 0, L_0x1dbbdd0; 1 drivers +v0x1ba7e90_0 .net *"_s1", 0 0, L_0x1dbbfc0; 1 drivers +S_0x1ba8a50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ba5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dbda10/d .functor OR 1, L_0x1dbdad0, L_0x1dbdc80, C4<0>, C4<0>; +L_0x1dbda10 .delay 1 (30000,30000,30000) L_0x1dbda10/d; +v0x1baa580_0 .net *"_s10", 0 0, L_0x1dbdad0; 1 drivers +v0x1baa660_0 .net *"_s12", 0 0, L_0x1dbdc80; 1 drivers +v0x1baa740_0 .net "in", 7 0, L_0x1dbba10; alias, 1 drivers +v0x1baa840_0 .net "ors", 1 0, L_0x1dbd830; 1 drivers +v0x1baa900_0 .net "out", 0 0, L_0x1dbda10; alias, 1 drivers +L_0x1dbcc00 .part L_0x1dbba10, 0, 4; +L_0x1dbd830 .concat8 [ 1 1 0 0], L_0x1dbc8f0, L_0x1dbd520; +L_0x1dbd970 .part L_0x1dbba10, 4, 4; +L_0x1dbdad0 .part L_0x1dbd830, 0, 1; +L_0x1dbdc80 .part L_0x1dbd830, 1, 1; +S_0x1ba8c10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1ba8a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dbc0b0/d .functor OR 1, L_0x1dbc170, L_0x1dbc2d0, C4<0>, C4<0>; +L_0x1dbc0b0 .delay 1 (30000,30000,30000) L_0x1dbc0b0/d; +L_0x1dbc500/d .functor OR 1, L_0x1dbc610, L_0x1dbc770, C4<0>, C4<0>; +L_0x1dbc500 .delay 1 (30000,30000,30000) L_0x1dbc500/d; +L_0x1dbc8f0/d .functor OR 1, L_0x1dbc960, L_0x1dbcb10, C4<0>, C4<0>; +L_0x1dbc8f0 .delay 1 (30000,30000,30000) L_0x1dbc8f0/d; +v0x1ba8e60_0 .net *"_s0", 0 0, L_0x1dbc0b0; 1 drivers +v0x1ba8f60_0 .net *"_s10", 0 0, L_0x1dbc610; 1 drivers +v0x1ba9040_0 .net *"_s12", 0 0, L_0x1dbc770; 1 drivers +v0x1ba9100_0 .net *"_s14", 0 0, L_0x1dbc960; 1 drivers +v0x1ba91e0_0 .net *"_s16", 0 0, L_0x1dbcb10; 1 drivers +v0x1ba9310_0 .net *"_s3", 0 0, L_0x1dbc170; 1 drivers +v0x1ba93f0_0 .net *"_s5", 0 0, L_0x1dbc2d0; 1 drivers +v0x1ba94d0_0 .net *"_s6", 0 0, L_0x1dbc500; 1 drivers +v0x1ba95b0_0 .net "in", 3 0, L_0x1dbcc00; 1 drivers +v0x1ba9720_0 .net "ors", 1 0, L_0x1dbc410; 1 drivers +v0x1ba9800_0 .net "out", 0 0, L_0x1dbc8f0; 1 drivers +L_0x1dbc170 .part L_0x1dbcc00, 0, 1; +L_0x1dbc2d0 .part L_0x1dbcc00, 1, 1; +L_0x1dbc410 .concat8 [ 1 1 0 0], L_0x1dbc0b0, L_0x1dbc500; +L_0x1dbc610 .part L_0x1dbcc00, 2, 1; +L_0x1dbc770 .part L_0x1dbcc00, 3, 1; +L_0x1dbc960 .part L_0x1dbc410, 0, 1; +L_0x1dbcb10 .part L_0x1dbc410, 1, 1; +S_0x1ba9920 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1ba8a50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dbcd30/d .functor OR 1, L_0x1dbcda0, L_0x1dbcf00, C4<0>, C4<0>; +L_0x1dbcd30 .delay 1 (30000,30000,30000) L_0x1dbcd30/d; +L_0x1dbd130/d .functor OR 1, L_0x1dbd240, L_0x1dbd3a0, C4<0>, C4<0>; +L_0x1dbd130 .delay 1 (30000,30000,30000) L_0x1dbd130/d; +L_0x1dbd520/d .functor OR 1, L_0x1dbd590, L_0x1dbd740, C4<0>, C4<0>; +L_0x1dbd520 .delay 1 (30000,30000,30000) L_0x1dbd520/d; +v0x1ba9ae0_0 .net *"_s0", 0 0, L_0x1dbcd30; 1 drivers +v0x1ba9be0_0 .net *"_s10", 0 0, L_0x1dbd240; 1 drivers +v0x1ba9cc0_0 .net *"_s12", 0 0, L_0x1dbd3a0; 1 drivers +v0x1ba9d80_0 .net *"_s14", 0 0, L_0x1dbd590; 1 drivers +v0x1ba9e60_0 .net *"_s16", 0 0, L_0x1dbd740; 1 drivers +v0x1ba9f90_0 .net *"_s3", 0 0, L_0x1dbcda0; 1 drivers +v0x1baa050_0 .net *"_s5", 0 0, L_0x1dbcf00; 1 drivers +v0x1baa130_0 .net *"_s6", 0 0, L_0x1dbd130; 1 drivers +v0x1baa210_0 .net "in", 3 0, L_0x1dbd970; 1 drivers +v0x1baa380_0 .net "ors", 1 0, L_0x1dbd040; 1 drivers +v0x1baa460_0 .net "out", 0 0, L_0x1dbd520; 1 drivers +L_0x1dbcda0 .part L_0x1dbd970, 0, 1; +L_0x1dbcf00 .part L_0x1dbd970, 1, 1; +L_0x1dbd040 .concat8 [ 1 1 0 0], L_0x1dbcd30, L_0x1dbd130; +L_0x1dbd240 .part L_0x1dbd970, 2, 1; +L_0x1dbd3a0 .part L_0x1dbd970, 3, 1; +L_0x1dbd590 .part L_0x1dbd040, 0, 1; +L_0x1dbd740 .part L_0x1dbd040, 1, 1; +S_0x1baada0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1ba3ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bb01d0_0 .net "ands", 7 0, L_0x1db7fb0; 1 drivers +v0x1bb02e0_0 .net "in", 7 0, L_0x1db64f0; alias, 1 drivers +v0x1bb03a0_0 .net "out", 0 0, L_0x1db9ef0; alias, 1 drivers +v0x1bb0470_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1baaff0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1baada0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bad730_0 .net "A", 7 0, L_0x1db64f0; alias, 1 drivers +v0x1bad830_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bad8f0_0 .net *"_s0", 0 0, L_0x1db6880; 1 drivers +v0x1bad9b0_0 .net *"_s12", 0 0, L_0x1db7240; 1 drivers +v0x1bada90_0 .net *"_s16", 0 0, L_0x1db75a0; 1 drivers +v0x1badbc0_0 .net *"_s20", 0 0, L_0x1db7970; 1 drivers +v0x1badca0_0 .net *"_s24", 0 0, L_0x1db7ca0; 1 drivers +v0x1badd80_0 .net *"_s28", 0 0, L_0x1db7c30; 1 drivers +v0x1bade60_0 .net *"_s4", 0 0, L_0x1db6c20; 1 drivers +v0x1badfd0_0 .net *"_s8", 0 0, L_0x1db6f30; 1 drivers +v0x1bae0b0_0 .net "out", 7 0, L_0x1db7fb0; alias, 1 drivers +L_0x1db6990 .part L_0x1db64f0, 0, 1; +L_0x1db6b80 .part v0x1d6daa0_0, 0, 1; +L_0x1db6ce0 .part L_0x1db64f0, 1, 1; +L_0x1db6e40 .part v0x1d6daa0_0, 1, 1; +L_0x1db6ff0 .part L_0x1db64f0, 2, 1; +L_0x1db7150 .part v0x1d6daa0_0, 2, 1; +L_0x1db7300 .part L_0x1db64f0, 3, 1; +L_0x1db7460 .part v0x1d6daa0_0, 3, 1; +L_0x1db7660 .part L_0x1db64f0, 4, 1; +L_0x1db78d0 .part v0x1d6daa0_0, 4, 1; +L_0x1db79e0 .part L_0x1db64f0, 5, 1; +L_0x1db7b40 .part v0x1d6daa0_0, 5, 1; +L_0x1db7d60 .part L_0x1db64f0, 6, 1; +L_0x1db7ec0 .part v0x1d6daa0_0, 6, 1; +LS_0x1db7fb0_0_0 .concat8 [ 1 1 1 1], L_0x1db6880, L_0x1db6c20, L_0x1db6f30, L_0x1db7240; +LS_0x1db7fb0_0_4 .concat8 [ 1 1 1 1], L_0x1db75a0, L_0x1db7970, L_0x1db7ca0, L_0x1db7c30; +L_0x1db7fb0 .concat8 [ 4 4 0 0], LS_0x1db7fb0_0_0, LS_0x1db7fb0_0_4; +L_0x1db8370 .part L_0x1db64f0, 7, 1; +L_0x1db8560 .part v0x1d6daa0_0, 7, 1; +S_0x1bab230 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bab440 .param/l "i" 0 4 54, +C4<00>; +L_0x1db6880/d .functor AND 1, L_0x1db6990, L_0x1db6b80, C4<1>, C4<1>; +L_0x1db6880 .delay 1 (30000,30000,30000) L_0x1db6880/d; +v0x1bab520_0 .net *"_s0", 0 0, L_0x1db6990; 1 drivers +v0x1bab600_0 .net *"_s1", 0 0, L_0x1db6b80; 1 drivers +S_0x1bab6e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bab8f0 .param/l "i" 0 4 54, +C4<01>; +L_0x1db6c20/d .functor AND 1, L_0x1db6ce0, L_0x1db6e40, C4<1>, C4<1>; +L_0x1db6c20 .delay 1 (30000,30000,30000) L_0x1db6c20/d; +v0x1bab9b0_0 .net *"_s0", 0 0, L_0x1db6ce0; 1 drivers +v0x1baba90_0 .net *"_s1", 0 0, L_0x1db6e40; 1 drivers +S_0x1babb70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1babdb0 .param/l "i" 0 4 54, +C4<010>; +L_0x1db6f30/d .functor AND 1, L_0x1db6ff0, L_0x1db7150, C4<1>, C4<1>; +L_0x1db6f30 .delay 1 (30000,30000,30000) L_0x1db6f30/d; +v0x1babe50_0 .net *"_s0", 0 0, L_0x1db6ff0; 1 drivers +v0x1babf30_0 .net *"_s1", 0 0, L_0x1db7150; 1 drivers +S_0x1bac010 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bac220 .param/l "i" 0 4 54, +C4<011>; +L_0x1db7240/d .functor AND 1, L_0x1db7300, L_0x1db7460, C4<1>, C4<1>; +L_0x1db7240 .delay 1 (30000,30000,30000) L_0x1db7240/d; +v0x1bac2e0_0 .net *"_s0", 0 0, L_0x1db7300; 1 drivers +v0x1bac3c0_0 .net *"_s1", 0 0, L_0x1db7460; 1 drivers +S_0x1bac4a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bac700 .param/l "i" 0 4 54, +C4<0100>; +L_0x1db75a0/d .functor AND 1, L_0x1db7660, L_0x1db78d0, C4<1>, C4<1>; +L_0x1db75a0 .delay 1 (30000,30000,30000) L_0x1db75a0/d; +v0x1bac7c0_0 .net *"_s0", 0 0, L_0x1db7660; 1 drivers +v0x1bac8a0_0 .net *"_s1", 0 0, L_0x1db78d0; 1 drivers +S_0x1bac980 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bacb90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1db7970/d .functor AND 1, L_0x1db79e0, L_0x1db7b40, C4<1>, C4<1>; +L_0x1db7970 .delay 1 (30000,30000,30000) L_0x1db7970/d; +v0x1bacc50_0 .net *"_s0", 0 0, L_0x1db79e0; 1 drivers +v0x1bacd30_0 .net *"_s1", 0 0, L_0x1db7b40; 1 drivers +S_0x1bace10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bad020 .param/l "i" 0 4 54, +C4<0110>; +L_0x1db7ca0/d .functor AND 1, L_0x1db7d60, L_0x1db7ec0, C4<1>, C4<1>; +L_0x1db7ca0 .delay 1 (30000,30000,30000) L_0x1db7ca0/d; +v0x1bad0e0_0 .net *"_s0", 0 0, L_0x1db7d60; 1 drivers +v0x1bad1c0_0 .net *"_s1", 0 0, L_0x1db7ec0; 1 drivers +S_0x1bad2a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1baaff0; + .timescale -9 -12; +P_0x1bad4b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1db7c30/d .functor AND 1, L_0x1db8370, L_0x1db8560, C4<1>, C4<1>; +L_0x1db7c30 .delay 1 (30000,30000,30000) L_0x1db7c30/d; +v0x1bad570_0 .net *"_s0", 0 0, L_0x1db8370; 1 drivers +v0x1bad650_0 .net *"_s1", 0 0, L_0x1db8560; 1 drivers +S_0x1bae210 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1baada0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1db9ef0/d .functor OR 1, L_0x1db9fb0, L_0x1dba160, C4<0>, C4<0>; +L_0x1db9ef0 .delay 1 (30000,30000,30000) L_0x1db9ef0/d; +v0x1bafd60_0 .net *"_s10", 0 0, L_0x1db9fb0; 1 drivers +v0x1bafe40_0 .net *"_s12", 0 0, L_0x1dba160; 1 drivers +v0x1baff20_0 .net "in", 7 0, L_0x1db7fb0; alias, 1 drivers +v0x1bafff0_0 .net "ors", 1 0, L_0x1db9d10; 1 drivers +v0x1bb00b0_0 .net "out", 0 0, L_0x1db9ef0; alias, 1 drivers +L_0x1db90e0 .part L_0x1db7fb0, 0, 4; +L_0x1db9d10 .concat8 [ 1 1 0 0], L_0x1db8e90, L_0x1db9a00; +L_0x1db9e50 .part L_0x1db7fb0, 4, 4; +L_0x1db9fb0 .part L_0x1db9d10, 0, 1; +L_0x1dba160 .part L_0x1db9d10, 1, 1; +S_0x1bae3d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bae210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1db8650/d .functor OR 1, L_0x1db8710, L_0x1db8870, C4<0>, C4<0>; +L_0x1db8650 .delay 1 (30000,30000,30000) L_0x1db8650/d; +L_0x1db8aa0/d .functor OR 1, L_0x1db8bb0, L_0x1db8d10, C4<0>, C4<0>; +L_0x1db8aa0 .delay 1 (30000,30000,30000) L_0x1db8aa0/d; +L_0x1db8e90/d .functor OR 1, L_0x1db8f00, L_0x1db8ff0, C4<0>, C4<0>; +L_0x1db8e90 .delay 1 (30000,30000,30000) L_0x1db8e90/d; +v0x1bae620_0 .net *"_s0", 0 0, L_0x1db8650; 1 drivers +v0x1bae720_0 .net *"_s10", 0 0, L_0x1db8bb0; 1 drivers +v0x1bae800_0 .net *"_s12", 0 0, L_0x1db8d10; 1 drivers +v0x1bae8c0_0 .net *"_s14", 0 0, L_0x1db8f00; 1 drivers +v0x1bae9a0_0 .net *"_s16", 0 0, L_0x1db8ff0; 1 drivers +v0x1baead0_0 .net *"_s3", 0 0, L_0x1db8710; 1 drivers +v0x1baebb0_0 .net *"_s5", 0 0, L_0x1db8870; 1 drivers +v0x1baec90_0 .net *"_s6", 0 0, L_0x1db8aa0; 1 drivers +v0x1baed70_0 .net "in", 3 0, L_0x1db90e0; 1 drivers +v0x1baeee0_0 .net "ors", 1 0, L_0x1db89b0; 1 drivers +v0x1baefc0_0 .net "out", 0 0, L_0x1db8e90; 1 drivers +L_0x1db8710 .part L_0x1db90e0, 0, 1; +L_0x1db8870 .part L_0x1db90e0, 1, 1; +L_0x1db89b0 .concat8 [ 1 1 0 0], L_0x1db8650, L_0x1db8aa0; +L_0x1db8bb0 .part L_0x1db90e0, 2, 1; +L_0x1db8d10 .part L_0x1db90e0, 3, 1; +L_0x1db8f00 .part L_0x1db89b0, 0, 1; +L_0x1db8ff0 .part L_0x1db89b0, 1, 1; +S_0x1baf0e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bae210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1db9210/d .functor OR 1, L_0x1db9280, L_0x1db93e0, C4<0>, C4<0>; +L_0x1db9210 .delay 1 (30000,30000,30000) L_0x1db9210/d; +L_0x1db9610/d .functor OR 1, L_0x1db9720, L_0x1db9880, C4<0>, C4<0>; +L_0x1db9610 .delay 1 (30000,30000,30000) L_0x1db9610/d; +L_0x1db9a00/d .functor OR 1, L_0x1db9a70, L_0x1db9c20, C4<0>, C4<0>; +L_0x1db9a00 .delay 1 (30000,30000,30000) L_0x1db9a00/d; +v0x1baf2a0_0 .net *"_s0", 0 0, L_0x1db9210; 1 drivers +v0x1baf3a0_0 .net *"_s10", 0 0, L_0x1db9720; 1 drivers +v0x1baf480_0 .net *"_s12", 0 0, L_0x1db9880; 1 drivers +v0x1baf540_0 .net *"_s14", 0 0, L_0x1db9a70; 1 drivers +v0x1baf620_0 .net *"_s16", 0 0, L_0x1db9c20; 1 drivers +v0x1baf750_0 .net *"_s3", 0 0, L_0x1db9280; 1 drivers +v0x1baf830_0 .net *"_s5", 0 0, L_0x1db93e0; 1 drivers +v0x1baf910_0 .net *"_s6", 0 0, L_0x1db9610; 1 drivers +v0x1baf9f0_0 .net "in", 3 0, L_0x1db9e50; 1 drivers +v0x1bafb60_0 .net "ors", 1 0, L_0x1db9520; 1 drivers +v0x1bafc40_0 .net "out", 0 0, L_0x1db9a00; 1 drivers +L_0x1db9280 .part L_0x1db9e50, 0, 1; +L_0x1db93e0 .part L_0x1db9e50, 1, 1; +L_0x1db9520 .concat8 [ 1 1 0 0], L_0x1db9210, L_0x1db9610; +L_0x1db9720 .part L_0x1db9e50, 2, 1; +L_0x1db9880 .part L_0x1db9e50, 3, 1; +L_0x1db9a70 .part L_0x1db9520, 0, 1; +L_0x1db9c20 .part L_0x1db9520, 1, 1; +S_0x1bb0550 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ba3ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1db5860/d .functor XNOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; +L_0x1db5860 .delay 1 (20000,20000,20000) L_0x1db5860/d; +L_0x1db5ad0/d .functor AND 1, L_0x1dbde70, L_0x1db4750, C4<1>, C4<1>; +L_0x1db5ad0 .delay 1 (30000,30000,30000) L_0x1db5ad0/d; +L_0x1db5b40/d .functor AND 1, L_0x1db5860, L_0x1dbe090, C4<1>, C4<1>; +L_0x1db5b40 .delay 1 (30000,30000,30000) L_0x1db5b40/d; +L_0x1db5ca0/d .functor OR 1, L_0x1db5b40, L_0x1db5ad0, C4<0>, C4<0>; +L_0x1db5ca0 .delay 1 (30000,30000,30000) L_0x1db5ca0/d; +v0x1bb0800_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers +v0x1bb08f0_0 .net "a_", 0 0, L_0x1db4640; alias, 1 drivers +v0x1bb09b0_0 .net "b", 0 0, L_0x1db44f0; alias, 1 drivers +v0x1bb0aa0_0 .net "b_", 0 0, L_0x1db4750; alias, 1 drivers +v0x1bb0b40_0 .net "carryin", 0 0, L_0x1dbe090; alias, 1 drivers +v0x1bb0c80_0 .net "eq", 0 0, L_0x1db5860; 1 drivers +v0x1bb0d40_0 .net "lt", 0 0, L_0x1db5ad0; 1 drivers +v0x1bb0e00_0 .net "out", 0 0, L_0x1db5ca0; 1 drivers +v0x1bb0ec0_0 .net "w0", 0 0, L_0x1db5b40; 1 drivers +S_0x1bb1110 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1ba3ec0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1db5640/d .functor OR 1, L_0x1db5140, L_0x1bb2370, C4<0>, C4<0>; +L_0x1db5640 .delay 1 (30000,30000,30000) L_0x1db5640/d; +v0x1bb1f00_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers +v0x1bb2050_0 .net "b", 0 0, L_0x1db4750; alias, 1 drivers +v0x1bb2110_0 .net "c1", 0 0, L_0x1db5140; 1 drivers +v0x1bb21b0_0 .net "c2", 0 0, L_0x1bb2370; 1 drivers +v0x1bb2280_0 .net "carryin", 0 0, L_0x1dbe090; alias, 1 drivers +v0x1bb2400_0 .net "carryout", 0 0, L_0x1db5640; 1 drivers +v0x1bb24a0_0 .net "s1", 0 0, L_0x1db5080; 1 drivers +v0x1bb2540_0 .net "sum", 0 0, L_0x1db52a0; 1 drivers +S_0x1bb1360 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bb1110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1db5080/d .functor XOR 1, L_0x1dbde70, L_0x1db4750, C4<0>, C4<0>; +L_0x1db5080 .delay 1 (30000,30000,30000) L_0x1db5080/d; +L_0x1db5140/d .functor AND 1, L_0x1dbde70, L_0x1db4750, C4<1>, C4<1>; +L_0x1db5140 .delay 1 (30000,30000,30000) L_0x1db5140/d; +v0x1bb15c0_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers +v0x1bb1680_0 .net "b", 0 0, L_0x1db4750; alias, 1 drivers +v0x1bb1740_0 .net "carryout", 0 0, L_0x1db5140; alias, 1 drivers +v0x1bb17e0_0 .net "sum", 0 0, L_0x1db5080; alias, 1 drivers +S_0x1bb1910 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bb1110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1db52a0/d .functor XOR 1, L_0x1db5080, L_0x1dbe090, C4<0>, C4<0>; +L_0x1db52a0 .delay 1 (30000,30000,30000) L_0x1db52a0/d; +L_0x1bb2370/d .functor AND 1, L_0x1db5080, L_0x1dbe090, C4<1>, C4<1>; +L_0x1bb2370 .delay 1 (30000,30000,30000) L_0x1bb2370/d; +v0x1bb1b70_0 .net "a", 0 0, L_0x1db5080; alias, 1 drivers +v0x1bb1c40_0 .net "b", 0 0, L_0x1dbe090; alias, 1 drivers +v0x1bb1ce0_0 .net "carryout", 0 0, L_0x1bb2370; alias, 1 drivers +v0x1bb1db0_0 .net "sum", 0 0, L_0x1db52a0; alias, 1 drivers +S_0x1bb3960 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1ba3bf0; + .timescale -9 -12; +L_0x7f72592da7f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da840 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dbdf10/d .functor OR 1, L_0x7f72592da7f8, L_0x7f72592da840, C4<0>, C4<0>; +L_0x1dbdf10 .delay 1 (30000,30000,30000) L_0x1dbdf10/d; +v0x1bb3b50_0 .net/2u *"_s0", 0 0, L_0x7f72592da7f8; 1 drivers +v0x1bb3c30_0 .net/2u *"_s2", 0 0, L_0x7f72592da840; 1 drivers +S_0x1bb3d10 .scope generate, "alu_slices[8]" "alu_slices[8]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1b738a0 .param/l "i" 0 3 37, +C4<01000>; +S_0x1bb4020 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bb3d10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1dbb990/d .functor NOT 1, L_0x1dc7b40, C4<0>, C4<0>, C4<0>; +L_0x1dbb990 .delay 1 (10000,10000,10000) L_0x1dbb990/d; +L_0x1dbe3b0/d .functor NOT 1, L_0x1dc7ca0, C4<0>, C4<0>, C4<0>; +L_0x1dbe3b0 .delay 1 (10000,10000,10000) L_0x1dbe3b0/d; +L_0x1dbf3b0/d .functor XOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; +L_0x1dbf3b0 .delay 1 (30000,30000,30000) L_0x1dbf3b0/d; +L_0x7f72592da888 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da8d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dbfa60/d .functor OR 1, L_0x7f72592da888, L_0x7f72592da8d0, C4<0>, C4<0>; +L_0x1dbfa60 .delay 1 (30000,30000,30000) L_0x1dbfa60/d; +L_0x1dbfc60/d .functor AND 1, L_0x1dc7b40, L_0x1dc7ca0, C4<1>, C4<1>; +L_0x1dbfc60 .delay 1 (30000,30000,30000) L_0x1dbfc60/d; +L_0x1dbfd20/d .functor NAND 1, L_0x1dc7b40, L_0x1dc7ca0, C4<1>, C4<1>; +L_0x1dbfd20 .delay 1 (20000,20000,20000) L_0x1dbfd20/d; +L_0x1dbfe80/d .functor XOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; +L_0x1dbfe80 .delay 1 (20000,20000,20000) L_0x1dbfe80/d; +L_0x1dc0330/d .functor OR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; +L_0x1dc0330 .delay 1 (30000,30000,30000) L_0x1dc0330/d; +L_0x1dc7a40/d .functor NOT 1, L_0x1dc3ca0, C4<0>, C4<0>, C4<0>; +L_0x1dc7a40 .delay 1 (10000,10000,10000) L_0x1dc7a40/d; +v0x1bc2750_0 .net "A", 0 0, L_0x1dc7b40; 1 drivers +v0x1bc2810_0 .net "A_", 0 0, L_0x1dbb990; 1 drivers +v0x1bc28d0_0 .net "B", 0 0, L_0x1dc7ca0; 1 drivers +v0x1bc29a0_0 .net "B_", 0 0, L_0x1dbe3b0; 1 drivers +v0x1bc2a40_0 .net *"_s12", 0 0, L_0x1dbfa60; 1 drivers +v0x1bc2b30_0 .net/2s *"_s14", 0 0, L_0x7f72592da888; 1 drivers +v0x1bc2bf0_0 .net/2s *"_s16", 0 0, L_0x7f72592da8d0; 1 drivers +v0x1bc2cd0_0 .net *"_s18", 0 0, L_0x1dbfc60; 1 drivers +v0x1bc2db0_0 .net *"_s20", 0 0, L_0x1dbfd20; 1 drivers +v0x1bc2f20_0 .net *"_s22", 0 0, L_0x1dbfe80; 1 drivers +v0x1bc3000_0 .net *"_s24", 0 0, L_0x1dc0330; 1 drivers +o0x7f7259368d48 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1bc30e0_0 name=_s30 +o0x7f7259368d78 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1bc31c0_0 name=_s32 +v0x1bc32a0_0 .net *"_s8", 0 0, L_0x1dbf3b0; 1 drivers +v0x1bc3380_0 .net "carryin", 0 0, L_0x1dbe240; 1 drivers +v0x1bc3420_0 .net "carryout", 0 0, L_0x1dc76e0; 1 drivers +v0x1bc34c0_0 .net "carryouts", 7 0, L_0x1ebf830; 1 drivers +v0x1bc3670_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bc3710_0 .net "result", 0 0, L_0x1dc3ca0; 1 drivers +v0x1bc3800_0 .net "results", 7 0, L_0x1dc0100; 1 drivers +v0x1bc3910_0 .net "zero", 0 0, L_0x1dc7a40; 1 drivers +LS_0x1dc0100_0_0 .concat8 [ 1 1 1 1], L_0x1dbe8d0, L_0x1dbef00, L_0x1dbf3b0, L_0x1dbfa60; +LS_0x1dc0100_0_4 .concat8 [ 1 1 1 1], L_0x1dbfc60, L_0x1dbfd20, L_0x1dbfe80, L_0x1dc0330; +L_0x1dc0100 .concat8 [ 4 4 0 0], LS_0x1dc0100_0_0, LS_0x1dc0100_0_4; +LS_0x1ebf830_0_0 .concat [ 1 1 1 1], L_0x1dbeb80, L_0x1dbf250, o0x7f7259368d48, L_0x1dbf8b0; +LS_0x1ebf830_0_4 .concat [ 4 0 0 0], o0x7f7259368d78; +L_0x1ebf830 .concat [ 4 4 0 0], LS_0x1ebf830_0_0, LS_0x1ebf830_0_4; +S_0x1bb42a0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bb4020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dbeb80/d .functor OR 1, L_0x1dbe660, L_0x1dbea20, C4<0>, C4<0>; +L_0x1dbeb80 .delay 1 (30000,30000,30000) L_0x1dbeb80/d; +v0x1bb50d0_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers +v0x1bb5190_0 .net "b", 0 0, L_0x1dc7ca0; alias, 1 drivers +v0x1bb5260_0 .net "c1", 0 0, L_0x1dbe660; 1 drivers +v0x1bb5360_0 .net "c2", 0 0, L_0x1dbea20; 1 drivers +v0x1bb5430_0 .net "carryin", 0 0, L_0x1dbe240; alias, 1 drivers +v0x1bb5520_0 .net "carryout", 0 0, L_0x1dbeb80; 1 drivers +v0x1bb55c0_0 .net "s1", 0 0, L_0x1dbe5a0; 1 drivers +v0x1bb56b0_0 .net "sum", 0 0, L_0x1dbe8d0; 1 drivers +S_0x1bb4510 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bb42a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dbe5a0/d .functor XOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; +L_0x1dbe5a0 .delay 1 (30000,30000,30000) L_0x1dbe5a0/d; +L_0x1dbe660/d .functor AND 1, L_0x1dc7b40, L_0x1dc7ca0, C4<1>, C4<1>; +L_0x1dbe660 .delay 1 (30000,30000,30000) L_0x1dbe660/d; +v0x1bb4770_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers +v0x1bb4850_0 .net "b", 0 0, L_0x1dc7ca0; alias, 1 drivers +v0x1bb4910_0 .net "carryout", 0 0, L_0x1dbe660; alias, 1 drivers +v0x1bb49b0_0 .net "sum", 0 0, L_0x1dbe5a0; alias, 1 drivers +S_0x1bb4af0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bb42a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dbe8d0/d .functor XOR 1, L_0x1dbe5a0, L_0x1dbe240, C4<0>, C4<0>; +L_0x1dbe8d0 .delay 1 (30000,30000,30000) L_0x1dbe8d0/d; +L_0x1dbea20/d .functor AND 1, L_0x1dbe5a0, L_0x1dbe240, C4<1>, C4<1>; +L_0x1dbea20 .delay 1 (30000,30000,30000) L_0x1dbea20/d; +v0x1bb4d50_0 .net "a", 0 0, L_0x1dbe5a0; alias, 1 drivers +v0x1bb4df0_0 .net "b", 0 0, L_0x1dbe240; alias, 1 drivers +v0x1bb4e90_0 .net "carryout", 0 0, L_0x1dbea20; alias, 1 drivers +v0x1bb4f60_0 .net "sum", 0 0, L_0x1dbe8d0; alias, 1 drivers +S_0x1bb5780 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bb4020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bbab70_0 .net "ands", 7 0, L_0x1dc56e0; 1 drivers +v0x1bbac80_0 .net "in", 7 0, L_0x1ebf830; alias, 1 drivers +v0x1bbad40_0 .net "out", 0 0, L_0x1dc76e0; alias, 1 drivers +v0x1bbae10_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bb59a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bb5780; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bb80d0_0 .net "A", 7 0, L_0x1ebf830; alias, 1 drivers +v0x1bb81d0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bb8290_0 .net *"_s0", 0 0, L_0x1dc4000; 1 drivers +v0x1bb8350_0 .net *"_s12", 0 0, L_0x1dc4970; 1 drivers +v0x1bb8430_0 .net *"_s16", 0 0, L_0x1dc4cd0; 1 drivers +v0x1bb8560_0 .net *"_s20", 0 0, L_0x1dc4fe0; 1 drivers +v0x1bb8640_0 .net *"_s24", 0 0, L_0x1dc53d0; 1 drivers +v0x1bb8720_0 .net *"_s28", 0 0, L_0x1dc5360; 1 drivers +v0x1bb8800_0 .net *"_s4", 0 0, L_0x1dc4310; 1 drivers +v0x1bb8970_0 .net *"_s8", 0 0, L_0x1dc4660; 1 drivers +v0x1bb8a50_0 .net "out", 7 0, L_0x1dc56e0; alias, 1 drivers +L_0x1dc40c0 .part L_0x1ebf830, 0, 1; +L_0x1dc4220 .part v0x1d6daa0_0, 0, 1; +L_0x1dc43d0 .part L_0x1ebf830, 1, 1; +L_0x1dc45c0 .part v0x1d6daa0_0, 1, 1; +L_0x1dc4720 .part L_0x1ebf830, 2, 1; +L_0x1dc4880 .part v0x1d6daa0_0, 2, 1; +L_0x1dc4a30 .part L_0x1ebf830, 3, 1; +L_0x1dc4b90 .part v0x1d6daa0_0, 3, 1; +L_0x1dc4d90 .part L_0x1ebf830, 4, 1; +L_0x1dc4ef0 .part v0x1d6daa0_0, 4, 1; +L_0x1dc5050 .part L_0x1ebf830, 5, 1; +L_0x1dc52c0 .part v0x1d6daa0_0, 5, 1; +L_0x1dc5490 .part L_0x1ebf830, 6, 1; +L_0x1dc55f0 .part v0x1d6daa0_0, 6, 1; +LS_0x1dc56e0_0_0 .concat8 [ 1 1 1 1], L_0x1dc4000, L_0x1dc4310, L_0x1dc4660, L_0x1dc4970; +LS_0x1dc56e0_0_4 .concat8 [ 1 1 1 1], L_0x1dc4cd0, L_0x1dc4fe0, L_0x1dc53d0, L_0x1dc5360; +L_0x1dc56e0 .concat8 [ 4 4 0 0], LS_0x1dc56e0_0_0, LS_0x1dc56e0_0_4; +L_0x1dc5aa0 .part L_0x1ebf830, 7, 1; +L_0x1dc5c90 .part v0x1d6daa0_0, 7, 1; +S_0x1bb5c00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb5e10 .param/l "i" 0 4 54, +C4<00>; +L_0x1dc4000/d .functor AND 1, L_0x1dc40c0, L_0x1dc4220, C4<1>, C4<1>; +L_0x1dc4000 .delay 1 (30000,30000,30000) L_0x1dc4000/d; +v0x1bb5ef0_0 .net *"_s0", 0 0, L_0x1dc40c0; 1 drivers +v0x1bb5fd0_0 .net *"_s1", 0 0, L_0x1dc4220; 1 drivers +S_0x1bb60b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb62c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1dc4310/d .functor AND 1, L_0x1dc43d0, L_0x1dc45c0, C4<1>, C4<1>; +L_0x1dc4310 .delay 1 (30000,30000,30000) L_0x1dc4310/d; +v0x1bb6380_0 .net *"_s0", 0 0, L_0x1dc43d0; 1 drivers +v0x1bb6460_0 .net *"_s1", 0 0, L_0x1dc45c0; 1 drivers +S_0x1bb6540 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb6750 .param/l "i" 0 4 54, +C4<010>; +L_0x1dc4660/d .functor AND 1, L_0x1dc4720, L_0x1dc4880, C4<1>, C4<1>; +L_0x1dc4660 .delay 1 (30000,30000,30000) L_0x1dc4660/d; +v0x1bb67f0_0 .net *"_s0", 0 0, L_0x1dc4720; 1 drivers +v0x1bb68d0_0 .net *"_s1", 0 0, L_0x1dc4880; 1 drivers +S_0x1bb69b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb6bc0 .param/l "i" 0 4 54, +C4<011>; +L_0x1dc4970/d .functor AND 1, L_0x1dc4a30, L_0x1dc4b90, C4<1>, C4<1>; +L_0x1dc4970 .delay 1 (30000,30000,30000) L_0x1dc4970/d; +v0x1bb6c80_0 .net *"_s0", 0 0, L_0x1dc4a30; 1 drivers +v0x1bb6d60_0 .net *"_s1", 0 0, L_0x1dc4b90; 1 drivers +S_0x1bb6e40 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb70a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dc4cd0/d .functor AND 1, L_0x1dc4d90, L_0x1dc4ef0, C4<1>, C4<1>; +L_0x1dc4cd0 .delay 1 (30000,30000,30000) L_0x1dc4cd0/d; +v0x1bb7160_0 .net *"_s0", 0 0, L_0x1dc4d90; 1 drivers +v0x1bb7240_0 .net *"_s1", 0 0, L_0x1dc4ef0; 1 drivers +S_0x1bb7320 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb7530 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dc4fe0/d .functor AND 1, L_0x1dc5050, L_0x1dc52c0, C4<1>, C4<1>; +L_0x1dc4fe0 .delay 1 (30000,30000,30000) L_0x1dc4fe0/d; +v0x1bb75f0_0 .net *"_s0", 0 0, L_0x1dc5050; 1 drivers +v0x1bb76d0_0 .net *"_s1", 0 0, L_0x1dc52c0; 1 drivers +S_0x1bb77b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb79c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dc53d0/d .functor AND 1, L_0x1dc5490, L_0x1dc55f0, C4<1>, C4<1>; +L_0x1dc53d0 .delay 1 (30000,30000,30000) L_0x1dc53d0/d; +v0x1bb7a80_0 .net *"_s0", 0 0, L_0x1dc5490; 1 drivers +v0x1bb7b60_0 .net *"_s1", 0 0, L_0x1dc55f0; 1 drivers +S_0x1bb7c40 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bb59a0; + .timescale -9 -12; +P_0x1bb7e50 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dc5360/d .functor AND 1, L_0x1dc5aa0, L_0x1dc5c90, C4<1>, C4<1>; +L_0x1dc5360 .delay 1 (30000,30000,30000) L_0x1dc5360/d; +v0x1bb7f10_0 .net *"_s0", 0 0, L_0x1dc5aa0; 1 drivers +v0x1bb7ff0_0 .net *"_s1", 0 0, L_0x1dc5c90; 1 drivers +S_0x1bb8bb0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bb5780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dc76e0/d .functor OR 1, L_0x1dc77a0, L_0x1dc7950, C4<0>, C4<0>; +L_0x1dc76e0 .delay 1 (30000,30000,30000) L_0x1dc76e0/d; +v0x1bba700_0 .net *"_s10", 0 0, L_0x1dc77a0; 1 drivers +v0x1bba7e0_0 .net *"_s12", 0 0, L_0x1dc7950; 1 drivers +v0x1bba8c0_0 .net "in", 7 0, L_0x1dc56e0; alias, 1 drivers +v0x1bba990_0 .net "ors", 1 0, L_0x1dc7500; 1 drivers +v0x1bbaa50_0 .net "out", 0 0, L_0x1dc76e0; alias, 1 drivers +L_0x1dc68d0 .part L_0x1dc56e0, 0, 4; +L_0x1dc7500 .concat8 [ 1 1 0 0], L_0x1dc65c0, L_0x1dc71f0; +L_0x1dc7640 .part L_0x1dc56e0, 4, 4; +L_0x1dc77a0 .part L_0x1dc7500, 0, 1; +L_0x1dc7950 .part L_0x1dc7500, 1, 1; +S_0x1bb8d70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bb8bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dc5d80/d .functor OR 1, L_0x1dc5e40, L_0x1dc5fa0, C4<0>, C4<0>; +L_0x1dc5d80 .delay 1 (30000,30000,30000) L_0x1dc5d80/d; +L_0x1dc61d0/d .functor OR 1, L_0x1dc62e0, L_0x1dc6440, C4<0>, C4<0>; +L_0x1dc61d0 .delay 1 (30000,30000,30000) L_0x1dc61d0/d; +L_0x1dc65c0/d .functor OR 1, L_0x1dc6630, L_0x1dc67e0, C4<0>, C4<0>; +L_0x1dc65c0 .delay 1 (30000,30000,30000) L_0x1dc65c0/d; +v0x1bb8fc0_0 .net *"_s0", 0 0, L_0x1dc5d80; 1 drivers +v0x1bb90c0_0 .net *"_s10", 0 0, L_0x1dc62e0; 1 drivers +v0x1bb91a0_0 .net *"_s12", 0 0, L_0x1dc6440; 1 drivers +v0x1bb9260_0 .net *"_s14", 0 0, L_0x1dc6630; 1 drivers +v0x1bb9340_0 .net *"_s16", 0 0, L_0x1dc67e0; 1 drivers +v0x1bb9470_0 .net *"_s3", 0 0, L_0x1dc5e40; 1 drivers +v0x1bb9550_0 .net *"_s5", 0 0, L_0x1dc5fa0; 1 drivers +v0x1bb9630_0 .net *"_s6", 0 0, L_0x1dc61d0; 1 drivers +v0x1bb9710_0 .net "in", 3 0, L_0x1dc68d0; 1 drivers +v0x1bb9880_0 .net "ors", 1 0, L_0x1dc60e0; 1 drivers +v0x1bb9960_0 .net "out", 0 0, L_0x1dc65c0; 1 drivers +L_0x1dc5e40 .part L_0x1dc68d0, 0, 1; +L_0x1dc5fa0 .part L_0x1dc68d0, 1, 1; +L_0x1dc60e0 .concat8 [ 1 1 0 0], L_0x1dc5d80, L_0x1dc61d0; +L_0x1dc62e0 .part L_0x1dc68d0, 2, 1; +L_0x1dc6440 .part L_0x1dc68d0, 3, 1; +L_0x1dc6630 .part L_0x1dc60e0, 0, 1; +L_0x1dc67e0 .part L_0x1dc60e0, 1, 1; +S_0x1bb9a80 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bb8bb0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dc6a00/d .functor OR 1, L_0x1dc6a70, L_0x1dc6bd0, C4<0>, C4<0>; +L_0x1dc6a00 .delay 1 (30000,30000,30000) L_0x1dc6a00/d; +L_0x1dc6e00/d .functor OR 1, L_0x1dc6f10, L_0x1dc7070, C4<0>, C4<0>; +L_0x1dc6e00 .delay 1 (30000,30000,30000) L_0x1dc6e00/d; +L_0x1dc71f0/d .functor OR 1, L_0x1dc7260, L_0x1dc7410, C4<0>, C4<0>; +L_0x1dc71f0 .delay 1 (30000,30000,30000) L_0x1dc71f0/d; +v0x1bb9c40_0 .net *"_s0", 0 0, L_0x1dc6a00; 1 drivers +v0x1bb9d40_0 .net *"_s10", 0 0, L_0x1dc6f10; 1 drivers +v0x1bb9e20_0 .net *"_s12", 0 0, L_0x1dc7070; 1 drivers +v0x1bb9ee0_0 .net *"_s14", 0 0, L_0x1dc7260; 1 drivers +v0x1bb9fc0_0 .net *"_s16", 0 0, L_0x1dc7410; 1 drivers +v0x1bba0f0_0 .net *"_s3", 0 0, L_0x1dc6a70; 1 drivers +v0x1bba1d0_0 .net *"_s5", 0 0, L_0x1dc6bd0; 1 drivers +v0x1bba2b0_0 .net *"_s6", 0 0, L_0x1dc6e00; 1 drivers +v0x1bba390_0 .net "in", 3 0, L_0x1dc7640; 1 drivers +v0x1bba500_0 .net "ors", 1 0, L_0x1dc6d10; 1 drivers +v0x1bba5e0_0 .net "out", 0 0, L_0x1dc71f0; 1 drivers +L_0x1dc6a70 .part L_0x1dc7640, 0, 1; +L_0x1dc6bd0 .part L_0x1dc7640, 1, 1; +L_0x1dc6d10 .concat8 [ 1 1 0 0], L_0x1dc6a00, L_0x1dc6e00; +L_0x1dc6f10 .part L_0x1dc7640, 2, 1; +L_0x1dc7070 .part L_0x1dc7640, 3, 1; +L_0x1dc7260 .part L_0x1dc6d10, 0, 1; +L_0x1dc7410 .part L_0x1dc6d10, 1, 1; +S_0x1bbaef0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bb4020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bc0320_0 .net "ands", 7 0, L_0x1dc1ca0; 1 drivers +v0x1bc0430_0 .net "in", 7 0, L_0x1dc0100; alias, 1 drivers +v0x1bc04f0_0 .net "out", 0 0, L_0x1dc3ca0; alias, 1 drivers +v0x1bc05c0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bbb140 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bbaef0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bbd880_0 .net "A", 7 0, L_0x1dc0100; alias, 1 drivers +v0x1bbd980_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bbda40_0 .net *"_s0", 0 0, L_0x1dc0490; 1 drivers +v0x1bbdb00_0 .net *"_s12", 0 0, L_0x1dc0e50; 1 drivers +v0x1bbdbe0_0 .net *"_s16", 0 0, L_0x1dc11b0; 1 drivers +v0x1bbdd10_0 .net *"_s20", 0 0, L_0x1dc15e0; 1 drivers +v0x1bbddf0_0 .net *"_s24", 0 0, L_0x1dc1910; 1 drivers +v0x1bbded0_0 .net *"_s28", 0 0, L_0x1dc18a0; 1 drivers +v0x1bbdfb0_0 .net *"_s4", 0 0, L_0x1dc0830; 1 drivers +v0x1bbe120_0 .net *"_s8", 0 0, L_0x1dc0b40; 1 drivers +v0x1bbe200_0 .net "out", 7 0, L_0x1dc1ca0; alias, 1 drivers +L_0x1dc05a0 .part L_0x1dc0100, 0, 1; +L_0x1dc0790 .part v0x1d6daa0_0, 0, 1; +L_0x1dc08f0 .part L_0x1dc0100, 1, 1; +L_0x1dc0a50 .part v0x1d6daa0_0, 1, 1; +L_0x1dc0c00 .part L_0x1dc0100, 2, 1; +L_0x1dc0d60 .part v0x1d6daa0_0, 2, 1; +L_0x1dc0f10 .part L_0x1dc0100, 3, 1; +L_0x1dc1070 .part v0x1d6daa0_0, 3, 1; +L_0x1dc1270 .part L_0x1dc0100, 4, 1; +L_0x1dc14e0 .part v0x1d6daa0_0, 4, 1; +L_0x1dc1650 .part L_0x1dc0100, 5, 1; +L_0x1dc17b0 .part v0x1d6daa0_0, 5, 1; +L_0x1dc19d0 .part L_0x1dc0100, 6, 1; +L_0x1dc1b30 .part v0x1d6daa0_0, 6, 1; +LS_0x1dc1ca0_0_0 .concat8 [ 1 1 1 1], L_0x1dc0490, L_0x1dc0830, L_0x1dc0b40, L_0x1dc0e50; +LS_0x1dc1ca0_0_4 .concat8 [ 1 1 1 1], L_0x1dc11b0, L_0x1dc15e0, L_0x1dc1910, L_0x1dc18a0; +L_0x1dc1ca0 .concat8 [ 4 4 0 0], LS_0x1dc1ca0_0_0, LS_0x1dc1ca0_0_4; +L_0x1dc2060 .part L_0x1dc0100, 7, 1; +L_0x1dc2250 .part v0x1d6daa0_0, 7, 1; +S_0x1bbb380 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbb590 .param/l "i" 0 4 54, +C4<00>; +L_0x1dc0490/d .functor AND 1, L_0x1dc05a0, L_0x1dc0790, C4<1>, C4<1>; +L_0x1dc0490 .delay 1 (30000,30000,30000) L_0x1dc0490/d; +v0x1bbb670_0 .net *"_s0", 0 0, L_0x1dc05a0; 1 drivers +v0x1bbb750_0 .net *"_s1", 0 0, L_0x1dc0790; 1 drivers +S_0x1bbb830 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbba40 .param/l "i" 0 4 54, +C4<01>; +L_0x1dc0830/d .functor AND 1, L_0x1dc08f0, L_0x1dc0a50, C4<1>, C4<1>; +L_0x1dc0830 .delay 1 (30000,30000,30000) L_0x1dc0830/d; +v0x1bbbb00_0 .net *"_s0", 0 0, L_0x1dc08f0; 1 drivers +v0x1bbbbe0_0 .net *"_s1", 0 0, L_0x1dc0a50; 1 drivers +S_0x1bbbcc0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbbf00 .param/l "i" 0 4 54, +C4<010>; +L_0x1dc0b40/d .functor AND 1, L_0x1dc0c00, L_0x1dc0d60, C4<1>, C4<1>; +L_0x1dc0b40 .delay 1 (30000,30000,30000) L_0x1dc0b40/d; +v0x1bbbfa0_0 .net *"_s0", 0 0, L_0x1dc0c00; 1 drivers +v0x1bbc080_0 .net *"_s1", 0 0, L_0x1dc0d60; 1 drivers +S_0x1bbc160 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbc370 .param/l "i" 0 4 54, +C4<011>; +L_0x1dc0e50/d .functor AND 1, L_0x1dc0f10, L_0x1dc1070, C4<1>, C4<1>; +L_0x1dc0e50 .delay 1 (30000,30000,30000) L_0x1dc0e50/d; +v0x1bbc430_0 .net *"_s0", 0 0, L_0x1dc0f10; 1 drivers +v0x1bbc510_0 .net *"_s1", 0 0, L_0x1dc1070; 1 drivers +S_0x1bbc5f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbc850 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dc11b0/d .functor AND 1, L_0x1dc1270, L_0x1dc14e0, C4<1>, C4<1>; +L_0x1dc11b0 .delay 1 (30000,30000,30000) L_0x1dc11b0/d; +v0x1bbc910_0 .net *"_s0", 0 0, L_0x1dc1270; 1 drivers +v0x1bbc9f0_0 .net *"_s1", 0 0, L_0x1dc14e0; 1 drivers +S_0x1bbcad0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbcce0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dc15e0/d .functor AND 1, L_0x1dc1650, L_0x1dc17b0, C4<1>, C4<1>; +L_0x1dc15e0 .delay 1 (30000,30000,30000) L_0x1dc15e0/d; +v0x1bbcda0_0 .net *"_s0", 0 0, L_0x1dc1650; 1 drivers +v0x1bbce80_0 .net *"_s1", 0 0, L_0x1dc17b0; 1 drivers +S_0x1bbcf60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbd170 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dc1910/d .functor AND 1, L_0x1dc19d0, L_0x1dc1b30, C4<1>, C4<1>; +L_0x1dc1910 .delay 1 (30000,30000,30000) L_0x1dc1910/d; +v0x1bbd230_0 .net *"_s0", 0 0, L_0x1dc19d0; 1 drivers +v0x1bbd310_0 .net *"_s1", 0 0, L_0x1dc1b30; 1 drivers +S_0x1bbd3f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bbb140; + .timescale -9 -12; +P_0x1bbd600 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dc18a0/d .functor AND 1, L_0x1dc2060, L_0x1dc2250, C4<1>, C4<1>; +L_0x1dc18a0 .delay 1 (30000,30000,30000) L_0x1dc18a0/d; +v0x1bbd6c0_0 .net *"_s0", 0 0, L_0x1dc2060; 1 drivers +v0x1bbd7a0_0 .net *"_s1", 0 0, L_0x1dc2250; 1 drivers +S_0x1bbe360 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bbaef0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dc3ca0/d .functor OR 1, L_0x1dc3d60, L_0x1dc3f10, C4<0>, C4<0>; +L_0x1dc3ca0 .delay 1 (30000,30000,30000) L_0x1dc3ca0/d; +v0x1bbfeb0_0 .net *"_s10", 0 0, L_0x1dc3d60; 1 drivers +v0x1bbff90_0 .net *"_s12", 0 0, L_0x1dc3f10; 1 drivers +v0x1bc0070_0 .net "in", 7 0, L_0x1dc1ca0; alias, 1 drivers +v0x1bc0140_0 .net "ors", 1 0, L_0x1dc3ac0; 1 drivers +v0x1bc0200_0 .net "out", 0 0, L_0x1dc3ca0; alias, 1 drivers +L_0x1dc2e90 .part L_0x1dc1ca0, 0, 4; +L_0x1dc3ac0 .concat8 [ 1 1 0 0], L_0x1dc2b80, L_0x1dc37b0; +L_0x1dc3c00 .part L_0x1dc1ca0, 4, 4; +L_0x1dc3d60 .part L_0x1dc3ac0, 0, 1; +L_0x1dc3f10 .part L_0x1dc3ac0, 1, 1; +S_0x1bbe520 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bbe360; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dc2340/d .functor OR 1, L_0x1dc2400, L_0x1dc2560, C4<0>, C4<0>; +L_0x1dc2340 .delay 1 (30000,30000,30000) L_0x1dc2340/d; +L_0x1dc2790/d .functor OR 1, L_0x1dc28a0, L_0x1dc2a00, C4<0>, C4<0>; +L_0x1dc2790 .delay 1 (30000,30000,30000) L_0x1dc2790/d; +L_0x1dc2b80/d .functor OR 1, L_0x1dc2bf0, L_0x1dc2da0, C4<0>, C4<0>; +L_0x1dc2b80 .delay 1 (30000,30000,30000) L_0x1dc2b80/d; +v0x1bbe770_0 .net *"_s0", 0 0, L_0x1dc2340; 1 drivers +v0x1bbe870_0 .net *"_s10", 0 0, L_0x1dc28a0; 1 drivers +v0x1bbe950_0 .net *"_s12", 0 0, L_0x1dc2a00; 1 drivers +v0x1bbea10_0 .net *"_s14", 0 0, L_0x1dc2bf0; 1 drivers +v0x1bbeaf0_0 .net *"_s16", 0 0, L_0x1dc2da0; 1 drivers +v0x1bbec20_0 .net *"_s3", 0 0, L_0x1dc2400; 1 drivers +v0x1bbed00_0 .net *"_s5", 0 0, L_0x1dc2560; 1 drivers +v0x1bbede0_0 .net *"_s6", 0 0, L_0x1dc2790; 1 drivers +v0x1bbeec0_0 .net "in", 3 0, L_0x1dc2e90; 1 drivers +v0x1bbf030_0 .net "ors", 1 0, L_0x1dc26a0; 1 drivers +v0x1bbf110_0 .net "out", 0 0, L_0x1dc2b80; 1 drivers +L_0x1dc2400 .part L_0x1dc2e90, 0, 1; +L_0x1dc2560 .part L_0x1dc2e90, 1, 1; +L_0x1dc26a0 .concat8 [ 1 1 0 0], L_0x1dc2340, L_0x1dc2790; +L_0x1dc28a0 .part L_0x1dc2e90, 2, 1; +L_0x1dc2a00 .part L_0x1dc2e90, 3, 1; +L_0x1dc2bf0 .part L_0x1dc26a0, 0, 1; +L_0x1dc2da0 .part L_0x1dc26a0, 1, 1; +S_0x1bbf230 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bbe360; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dc2fc0/d .functor OR 1, L_0x1dc3030, L_0x1dc3190, C4<0>, C4<0>; +L_0x1dc2fc0 .delay 1 (30000,30000,30000) L_0x1dc2fc0/d; +L_0x1dc33c0/d .functor OR 1, L_0x1dc34d0, L_0x1dc3630, C4<0>, C4<0>; +L_0x1dc33c0 .delay 1 (30000,30000,30000) L_0x1dc33c0/d; +L_0x1dc37b0/d .functor OR 1, L_0x1dc3820, L_0x1dc39d0, C4<0>, C4<0>; +L_0x1dc37b0 .delay 1 (30000,30000,30000) L_0x1dc37b0/d; +v0x1bbf3f0_0 .net *"_s0", 0 0, L_0x1dc2fc0; 1 drivers +v0x1bbf4f0_0 .net *"_s10", 0 0, L_0x1dc34d0; 1 drivers +v0x1bbf5d0_0 .net *"_s12", 0 0, L_0x1dc3630; 1 drivers +v0x1bbf690_0 .net *"_s14", 0 0, L_0x1dc3820; 1 drivers +v0x1bbf770_0 .net *"_s16", 0 0, L_0x1dc39d0; 1 drivers +v0x1bbf8a0_0 .net *"_s3", 0 0, L_0x1dc3030; 1 drivers +v0x1bbf980_0 .net *"_s5", 0 0, L_0x1dc3190; 1 drivers +v0x1bbfa60_0 .net *"_s6", 0 0, L_0x1dc33c0; 1 drivers +v0x1bbfb40_0 .net "in", 3 0, L_0x1dc3c00; 1 drivers +v0x1bbfcb0_0 .net "ors", 1 0, L_0x1dc32d0; 1 drivers +v0x1bbfd90_0 .net "out", 0 0, L_0x1dc37b0; 1 drivers +L_0x1dc3030 .part L_0x1dc3c00, 0, 1; +L_0x1dc3190 .part L_0x1dc3c00, 1, 1; +L_0x1dc32d0 .concat8 [ 1 1 0 0], L_0x1dc2fc0, L_0x1dc33c0; +L_0x1dc34d0 .part L_0x1dc3c00, 2, 1; +L_0x1dc3630 .part L_0x1dc3c00, 3, 1; +L_0x1dc3820 .part L_0x1dc32d0, 0, 1; +L_0x1dc39d0 .part L_0x1dc32d0, 1, 1; +S_0x1bc06a0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bb4020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1dbf470/d .functor XNOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; +L_0x1dbf470 .delay 1 (20000,20000,20000) L_0x1dbf470/d; +L_0x1dbf6e0/d .functor AND 1, L_0x1dc7b40, L_0x1dbe3b0, C4<1>, C4<1>; +L_0x1dbf6e0 .delay 1 (30000,30000,30000) L_0x1dbf6e0/d; +L_0x1dbf750/d .functor AND 1, L_0x1dbf470, L_0x1dbe240, C4<1>, C4<1>; +L_0x1dbf750 .delay 1 (30000,30000,30000) L_0x1dbf750/d; +L_0x1dbf8b0/d .functor OR 1, L_0x1dbf750, L_0x1dbf6e0, C4<0>, C4<0>; +L_0x1dbf8b0 .delay 1 (30000,30000,30000) L_0x1dbf8b0/d; +v0x1bc0950_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers +v0x1bc0a40_0 .net "a_", 0 0, L_0x1dbb990; alias, 1 drivers +v0x1bc0b00_0 .net "b", 0 0, L_0x1dc7ca0; alias, 1 drivers +v0x1bc0bf0_0 .net "b_", 0 0, L_0x1dbe3b0; alias, 1 drivers +v0x1bc0c90_0 .net "carryin", 0 0, L_0x1dbe240; alias, 1 drivers +v0x1bc0dd0_0 .net "eq", 0 0, L_0x1dbf470; 1 drivers +v0x1bc0e90_0 .net "lt", 0 0, L_0x1dbf6e0; 1 drivers +v0x1bc0f50_0 .net "out", 0 0, L_0x1dbf8b0; 1 drivers +v0x1bc1010_0 .net "w0", 0 0, L_0x1dbf750; 1 drivers +S_0x1bc1260 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bb4020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dbf250/d .functor OR 1, L_0x1dbeda0, L_0x1bc24c0, C4<0>, C4<0>; +L_0x1dbf250 .delay 1 (30000,30000,30000) L_0x1dbf250/d; +v0x1bc2050_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers +v0x1bc21a0_0 .net "b", 0 0, L_0x1dbe3b0; alias, 1 drivers +v0x1bc2260_0 .net "c1", 0 0, L_0x1dbeda0; 1 drivers +v0x1bc2300_0 .net "c2", 0 0, L_0x1bc24c0; 1 drivers +v0x1bc23d0_0 .net "carryin", 0 0, L_0x1dbe240; alias, 1 drivers +v0x1bc2550_0 .net "carryout", 0 0, L_0x1dbf250; 1 drivers +v0x1bc25f0_0 .net "s1", 0 0, L_0x1dbece0; 1 drivers +v0x1bc2690_0 .net "sum", 0 0, L_0x1dbef00; 1 drivers +S_0x1bc14b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bc1260; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dbece0/d .functor XOR 1, L_0x1dc7b40, L_0x1dbe3b0, C4<0>, C4<0>; +L_0x1dbece0 .delay 1 (30000,30000,30000) L_0x1dbece0/d; +L_0x1dbeda0/d .functor AND 1, L_0x1dc7b40, L_0x1dbe3b0, C4<1>, C4<1>; +L_0x1dbeda0 .delay 1 (30000,30000,30000) L_0x1dbeda0/d; +v0x1bc1710_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers +v0x1bc17d0_0 .net "b", 0 0, L_0x1dbe3b0; alias, 1 drivers +v0x1bc1890_0 .net "carryout", 0 0, L_0x1dbeda0; alias, 1 drivers +v0x1bc1930_0 .net "sum", 0 0, L_0x1dbece0; alias, 1 drivers +S_0x1bc1a60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bc1260; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dbef00/d .functor XOR 1, L_0x1dbece0, L_0x1dbe240, C4<0>, C4<0>; +L_0x1dbef00 .delay 1 (30000,30000,30000) L_0x1dbef00/d; +L_0x1bc24c0/d .functor AND 1, L_0x1dbece0, L_0x1dbe240, C4<1>, C4<1>; +L_0x1bc24c0 .delay 1 (30000,30000,30000) L_0x1bc24c0/d; +v0x1bc1cc0_0 .net "a", 0 0, L_0x1dbece0; alias, 1 drivers +v0x1bc1d90_0 .net "b", 0 0, L_0x1dbe240; alias, 1 drivers +v0x1bc1e30_0 .net "carryout", 0 0, L_0x1bc24c0; alias, 1 drivers +v0x1bc1f00_0 .net "sum", 0 0, L_0x1dbef00; alias, 1 drivers +S_0x1bc3ab0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bb3d10; + .timescale -9 -12; +L_0x7f72592da918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dc7be0/d .functor OR 1, L_0x7f72592da918, L_0x7f72592da960, C4<0>, C4<0>; +L_0x1dc7be0 .delay 1 (30000,30000,30000) L_0x1dc7be0/d; +v0x1bc3ca0_0 .net/2u *"_s0", 0 0, L_0x7f72592da918; 1 drivers +v0x1bc3d80_0 .net/2u *"_s2", 0 0, L_0x7f72592da960; 1 drivers +S_0x1bc3e60 .scope generate, "alu_slices[9]" "alu_slices[9]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1bc4070 .param/l "i" 0 3 37, +C4<01001>; +S_0x1bc4130 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bc3e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1dc7f10/d .functor NOT 1, L_0x1dd1850, C4<0>, C4<0>, C4<0>; +L_0x1dc7f10 .delay 1 (10000,10000,10000) L_0x1dc7f10/d; +L_0x1dc1c20/d .functor NOT 1, L_0x1dc7d40, C4<0>, C4<0>, C4<0>; +L_0x1dc1c20 .delay 1 (10000,10000,10000) L_0x1dc1c20/d; +L_0x1dc90c0/d .functor XOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; +L_0x1dc90c0 .delay 1 (30000,30000,30000) L_0x1dc90c0/d; +L_0x7f72592da9a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592da9f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dc9770/d .functor OR 1, L_0x7f72592da9a8, L_0x7f72592da9f0, C4<0>, C4<0>; +L_0x1dc9770 .delay 1 (30000,30000,30000) L_0x1dc9770/d; +L_0x1dc9970/d .functor AND 1, L_0x1dd1850, L_0x1dc7d40, C4<1>, C4<1>; +L_0x1dc9970 .delay 1 (30000,30000,30000) L_0x1dc9970/d; +L_0x1dc9a30/d .functor NAND 1, L_0x1dd1850, L_0x1dc7d40, C4<1>, C4<1>; +L_0x1dc9a30 .delay 1 (20000,20000,20000) L_0x1dc9a30/d; +L_0x1dc9b90/d .functor XOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; +L_0x1dc9b90 .delay 1 (20000,20000,20000) L_0x1dc9b90/d; +L_0x1dca040/d .functor OR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; +L_0x1dca040 .delay 1 (30000,30000,30000) L_0x1dca040/d; +L_0x1dd1750/d .functor NOT 1, L_0x1dcd9b0, C4<0>, C4<0>, C4<0>; +L_0x1dd1750 .delay 1 (10000,10000,10000) L_0x1dd1750/d; +v0x1bd2860_0 .net "A", 0 0, L_0x1dd1850; 1 drivers +v0x1bd2920_0 .net "A_", 0 0, L_0x1dc7f10; 1 drivers +v0x1bd29e0_0 .net "B", 0 0, L_0x1dc7d40; 1 drivers +v0x1bd2ab0_0 .net "B_", 0 0, L_0x1dc1c20; 1 drivers +v0x1bd2b50_0 .net *"_s12", 0 0, L_0x1dc9770; 1 drivers +v0x1bd2c40_0 .net/2s *"_s14", 0 0, L_0x7f72592da9a8; 1 drivers +v0x1bd2d00_0 .net/2s *"_s16", 0 0, L_0x7f72592da9f0; 1 drivers +v0x1bd2de0_0 .net *"_s18", 0 0, L_0x1dc9970; 1 drivers +v0x1bd2ec0_0 .net *"_s20", 0 0, L_0x1dc9a30; 1 drivers +v0x1bd3030_0 .net *"_s22", 0 0, L_0x1dc9b90; 1 drivers +v0x1bd3110_0 .net *"_s24", 0 0, L_0x1dca040; 1 drivers +o0x7f725936b298 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1bd31f0_0 name=_s30 +o0x7f725936b2c8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1bd32d0_0 name=_s32 +v0x1bd33b0_0 .net *"_s8", 0 0, L_0x1dc90c0; 1 drivers +v0x1bd3490_0 .net "carryin", 0 0, L_0x1dd1aa0; 1 drivers +v0x1bd3530_0 .net "carryout", 0 0, L_0x1dd13f0; 1 drivers +v0x1bd35d0_0 .net "carryouts", 7 0, L_0x1ebf9c0; 1 drivers +v0x1bd3780_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bd3820_0 .net "result", 0 0, L_0x1dcd9b0; 1 drivers +v0x1bd3910_0 .net "results", 7 0, L_0x1dc9e10; 1 drivers +v0x1bd3a20_0 .net "zero", 0 0, L_0x1dd1750; 1 drivers +LS_0x1dc9e10_0_0 .concat8 [ 1 1 1 1], L_0x1dc85e0, L_0x1dc8c10, L_0x1dc90c0, L_0x1dc9770; +LS_0x1dc9e10_0_4 .concat8 [ 1 1 1 1], L_0x1dc9970, L_0x1dc9a30, L_0x1dc9b90, L_0x1dca040; +L_0x1dc9e10 .concat8 [ 4 4 0 0], LS_0x1dc9e10_0_0, LS_0x1dc9e10_0_4; +LS_0x1ebf9c0_0_0 .concat [ 1 1 1 1], L_0x1dc8890, L_0x1dc8f60, o0x7f725936b298, L_0x1dc95c0; +LS_0x1ebf9c0_0_4 .concat [ 4 0 0 0], o0x7f725936b2c8; +L_0x1ebf9c0 .concat [ 4 4 0 0], LS_0x1ebf9c0_0_0, LS_0x1ebf9c0_0_4; +S_0x1bc43b0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bc4130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dc8890/d .functor OR 1, L_0x1dc8370, L_0x1dc8730, C4<0>, C4<0>; +L_0x1dc8890 .delay 1 (30000,30000,30000) L_0x1dc8890/d; +v0x1bc51e0_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers +v0x1bc52a0_0 .net "b", 0 0, L_0x1dc7d40; alias, 1 drivers +v0x1bc5370_0 .net "c1", 0 0, L_0x1dc8370; 1 drivers +v0x1bc5470_0 .net "c2", 0 0, L_0x1dc8730; 1 drivers +v0x1bc5540_0 .net "carryin", 0 0, L_0x1dd1aa0; alias, 1 drivers +v0x1bc5630_0 .net "carryout", 0 0, L_0x1dc8890; 1 drivers +v0x1bc56d0_0 .net "s1", 0 0, L_0x1dc8300; 1 drivers +v0x1bc57c0_0 .net "sum", 0 0, L_0x1dc85e0; 1 drivers +S_0x1bc4620 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bc43b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dc8300/d .functor XOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; +L_0x1dc8300 .delay 1 (30000,30000,30000) L_0x1dc8300/d; +L_0x1dc8370/d .functor AND 1, L_0x1dd1850, L_0x1dc7d40, C4<1>, C4<1>; +L_0x1dc8370 .delay 1 (30000,30000,30000) L_0x1dc8370/d; +v0x1bc4880_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers +v0x1bc4960_0 .net "b", 0 0, L_0x1dc7d40; alias, 1 drivers +v0x1bc4a20_0 .net "carryout", 0 0, L_0x1dc8370; alias, 1 drivers +v0x1bc4ac0_0 .net "sum", 0 0, L_0x1dc8300; alias, 1 drivers +S_0x1bc4c00 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bc43b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dc85e0/d .functor XOR 1, L_0x1dc8300, L_0x1dd1aa0, C4<0>, C4<0>; +L_0x1dc85e0 .delay 1 (30000,30000,30000) L_0x1dc85e0/d; +L_0x1dc8730/d .functor AND 1, L_0x1dc8300, L_0x1dd1aa0, C4<1>, C4<1>; +L_0x1dc8730 .delay 1 (30000,30000,30000) L_0x1dc8730/d; +v0x1bc4e60_0 .net "a", 0 0, L_0x1dc8300; alias, 1 drivers +v0x1bc4f00_0 .net "b", 0 0, L_0x1dd1aa0; alias, 1 drivers +v0x1bc4fa0_0 .net "carryout", 0 0, L_0x1dc8730; alias, 1 drivers +v0x1bc5070_0 .net "sum", 0 0, L_0x1dc85e0; alias, 1 drivers +S_0x1bc5890 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bc4130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bcac80_0 .net "ands", 7 0, L_0x1dcf3f0; 1 drivers +v0x1bcad90_0 .net "in", 7 0, L_0x1ebf9c0; alias, 1 drivers +v0x1bcae50_0 .net "out", 0 0, L_0x1dd13f0; alias, 1 drivers +v0x1bcaf20_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bc5ab0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bc5890; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bc81e0_0 .net "A", 7 0, L_0x1ebf9c0; alias, 1 drivers +v0x1bc82e0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bc83a0_0 .net *"_s0", 0 0, L_0x1dcdd10; 1 drivers +v0x1bc8460_0 .net *"_s12", 0 0, L_0x1dce680; 1 drivers +v0x1bc8540_0 .net *"_s16", 0 0, L_0x1dce9e0; 1 drivers +v0x1bc8670_0 .net *"_s20", 0 0, L_0x1dcecf0; 1 drivers +v0x1bc8750_0 .net *"_s24", 0 0, L_0x1dcf0e0; 1 drivers +v0x1bc8830_0 .net *"_s28", 0 0, L_0x1dcf070; 1 drivers +v0x1bc8910_0 .net *"_s4", 0 0, L_0x1dce020; 1 drivers +v0x1bc8a80_0 .net *"_s8", 0 0, L_0x1dce370; 1 drivers +v0x1bc8b60_0 .net "out", 7 0, L_0x1dcf3f0; alias, 1 drivers +L_0x1dcddd0 .part L_0x1ebf9c0, 0, 1; +L_0x1dcdf30 .part v0x1d6daa0_0, 0, 1; +L_0x1dce0e0 .part L_0x1ebf9c0, 1, 1; +L_0x1dce2d0 .part v0x1d6daa0_0, 1, 1; +L_0x1dce430 .part L_0x1ebf9c0, 2, 1; +L_0x1dce590 .part v0x1d6daa0_0, 2, 1; +L_0x1dce740 .part L_0x1ebf9c0, 3, 1; +L_0x1dce8a0 .part v0x1d6daa0_0, 3, 1; +L_0x1dceaa0 .part L_0x1ebf9c0, 4, 1; +L_0x1dcec00 .part v0x1d6daa0_0, 4, 1; +L_0x1dced60 .part L_0x1ebf9c0, 5, 1; +L_0x1dcefd0 .part v0x1d6daa0_0, 5, 1; +L_0x1dcf1a0 .part L_0x1ebf9c0, 6, 1; +L_0x1dcf300 .part v0x1d6daa0_0, 6, 1; +LS_0x1dcf3f0_0_0 .concat8 [ 1 1 1 1], L_0x1dcdd10, L_0x1dce020, L_0x1dce370, L_0x1dce680; +LS_0x1dcf3f0_0_4 .concat8 [ 1 1 1 1], L_0x1dce9e0, L_0x1dcecf0, L_0x1dcf0e0, L_0x1dcf070; +L_0x1dcf3f0 .concat8 [ 4 4 0 0], LS_0x1dcf3f0_0_0, LS_0x1dcf3f0_0_4; +L_0x1dcf7b0 .part L_0x1ebf9c0, 7, 1; +L_0x1dcf9a0 .part v0x1d6daa0_0, 7, 1; +S_0x1bc5d10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc5f20 .param/l "i" 0 4 54, +C4<00>; +L_0x1dcdd10/d .functor AND 1, L_0x1dcddd0, L_0x1dcdf30, C4<1>, C4<1>; +L_0x1dcdd10 .delay 1 (30000,30000,30000) L_0x1dcdd10/d; +v0x1bc6000_0 .net *"_s0", 0 0, L_0x1dcddd0; 1 drivers +v0x1bc60e0_0 .net *"_s1", 0 0, L_0x1dcdf30; 1 drivers +S_0x1bc61c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc63d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1dce020/d .functor AND 1, L_0x1dce0e0, L_0x1dce2d0, C4<1>, C4<1>; +L_0x1dce020 .delay 1 (30000,30000,30000) L_0x1dce020/d; +v0x1bc6490_0 .net *"_s0", 0 0, L_0x1dce0e0; 1 drivers +v0x1bc6570_0 .net *"_s1", 0 0, L_0x1dce2d0; 1 drivers +S_0x1bc6650 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc6860 .param/l "i" 0 4 54, +C4<010>; +L_0x1dce370/d .functor AND 1, L_0x1dce430, L_0x1dce590, C4<1>, C4<1>; +L_0x1dce370 .delay 1 (30000,30000,30000) L_0x1dce370/d; +v0x1bc6900_0 .net *"_s0", 0 0, L_0x1dce430; 1 drivers +v0x1bc69e0_0 .net *"_s1", 0 0, L_0x1dce590; 1 drivers +S_0x1bc6ac0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc6cd0 .param/l "i" 0 4 54, +C4<011>; +L_0x1dce680/d .functor AND 1, L_0x1dce740, L_0x1dce8a0, C4<1>, C4<1>; +L_0x1dce680 .delay 1 (30000,30000,30000) L_0x1dce680/d; +v0x1bc6d90_0 .net *"_s0", 0 0, L_0x1dce740; 1 drivers +v0x1bc6e70_0 .net *"_s1", 0 0, L_0x1dce8a0; 1 drivers +S_0x1bc6f50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc71b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dce9e0/d .functor AND 1, L_0x1dceaa0, L_0x1dcec00, C4<1>, C4<1>; +L_0x1dce9e0 .delay 1 (30000,30000,30000) L_0x1dce9e0/d; +v0x1bc7270_0 .net *"_s0", 0 0, L_0x1dceaa0; 1 drivers +v0x1bc7350_0 .net *"_s1", 0 0, L_0x1dcec00; 1 drivers +S_0x1bc7430 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc7640 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dcecf0/d .functor AND 1, L_0x1dced60, L_0x1dcefd0, C4<1>, C4<1>; +L_0x1dcecf0 .delay 1 (30000,30000,30000) L_0x1dcecf0/d; +v0x1bc7700_0 .net *"_s0", 0 0, L_0x1dced60; 1 drivers +v0x1bc77e0_0 .net *"_s1", 0 0, L_0x1dcefd0; 1 drivers +S_0x1bc78c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc7ad0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dcf0e0/d .functor AND 1, L_0x1dcf1a0, L_0x1dcf300, C4<1>, C4<1>; +L_0x1dcf0e0 .delay 1 (30000,30000,30000) L_0x1dcf0e0/d; +v0x1bc7b90_0 .net *"_s0", 0 0, L_0x1dcf1a0; 1 drivers +v0x1bc7c70_0 .net *"_s1", 0 0, L_0x1dcf300; 1 drivers +S_0x1bc7d50 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bc5ab0; + .timescale -9 -12; +P_0x1bc7f60 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dcf070/d .functor AND 1, L_0x1dcf7b0, L_0x1dcf9a0, C4<1>, C4<1>; +L_0x1dcf070 .delay 1 (30000,30000,30000) L_0x1dcf070/d; +v0x1bc8020_0 .net *"_s0", 0 0, L_0x1dcf7b0; 1 drivers +v0x1bc8100_0 .net *"_s1", 0 0, L_0x1dcf9a0; 1 drivers +S_0x1bc8cc0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bc5890; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dd13f0/d .functor OR 1, L_0x1dd14b0, L_0x1dd1660, C4<0>, C4<0>; +L_0x1dd13f0 .delay 1 (30000,30000,30000) L_0x1dd13f0/d; +v0x1bca810_0 .net *"_s10", 0 0, L_0x1dd14b0; 1 drivers +v0x1bca8f0_0 .net *"_s12", 0 0, L_0x1dd1660; 1 drivers +v0x1bca9d0_0 .net "in", 7 0, L_0x1dcf3f0; alias, 1 drivers +v0x1bcaaa0_0 .net "ors", 1 0, L_0x1dd1210; 1 drivers +v0x1bcab60_0 .net "out", 0 0, L_0x1dd13f0; alias, 1 drivers +L_0x1dd05e0 .part L_0x1dcf3f0, 0, 4; +L_0x1dd1210 .concat8 [ 1 1 0 0], L_0x1dd02d0, L_0x1dd0f00; +L_0x1dd1350 .part L_0x1dcf3f0, 4, 4; +L_0x1dd14b0 .part L_0x1dd1210, 0, 1; +L_0x1dd1660 .part L_0x1dd1210, 1, 1; +S_0x1bc8e80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bc8cc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dcfa90/d .functor OR 1, L_0x1dcfb50, L_0x1dcfcb0, C4<0>, C4<0>; +L_0x1dcfa90 .delay 1 (30000,30000,30000) L_0x1dcfa90/d; +L_0x1dcfee0/d .functor OR 1, L_0x1dcfff0, L_0x1dd0150, C4<0>, C4<0>; +L_0x1dcfee0 .delay 1 (30000,30000,30000) L_0x1dcfee0/d; +L_0x1dd02d0/d .functor OR 1, L_0x1dd0340, L_0x1dd04f0, C4<0>, C4<0>; +L_0x1dd02d0 .delay 1 (30000,30000,30000) L_0x1dd02d0/d; +v0x1bc90d0_0 .net *"_s0", 0 0, L_0x1dcfa90; 1 drivers +v0x1bc91d0_0 .net *"_s10", 0 0, L_0x1dcfff0; 1 drivers +v0x1bc92b0_0 .net *"_s12", 0 0, L_0x1dd0150; 1 drivers +v0x1bc9370_0 .net *"_s14", 0 0, L_0x1dd0340; 1 drivers +v0x1bc9450_0 .net *"_s16", 0 0, L_0x1dd04f0; 1 drivers +v0x1bc9580_0 .net *"_s3", 0 0, L_0x1dcfb50; 1 drivers +v0x1bc9660_0 .net *"_s5", 0 0, L_0x1dcfcb0; 1 drivers +v0x1bc9740_0 .net *"_s6", 0 0, L_0x1dcfee0; 1 drivers +v0x1bc9820_0 .net "in", 3 0, L_0x1dd05e0; 1 drivers +v0x1bc9990_0 .net "ors", 1 0, L_0x1dcfdf0; 1 drivers +v0x1bc9a70_0 .net "out", 0 0, L_0x1dd02d0; 1 drivers +L_0x1dcfb50 .part L_0x1dd05e0, 0, 1; +L_0x1dcfcb0 .part L_0x1dd05e0, 1, 1; +L_0x1dcfdf0 .concat8 [ 1 1 0 0], L_0x1dcfa90, L_0x1dcfee0; +L_0x1dcfff0 .part L_0x1dd05e0, 2, 1; +L_0x1dd0150 .part L_0x1dd05e0, 3, 1; +L_0x1dd0340 .part L_0x1dcfdf0, 0, 1; +L_0x1dd04f0 .part L_0x1dcfdf0, 1, 1; +S_0x1bc9b90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bc8cc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dd0710/d .functor OR 1, L_0x1dd0780, L_0x1dd08e0, C4<0>, C4<0>; +L_0x1dd0710 .delay 1 (30000,30000,30000) L_0x1dd0710/d; +L_0x1dd0b10/d .functor OR 1, L_0x1dd0c20, L_0x1dd0d80, C4<0>, C4<0>; +L_0x1dd0b10 .delay 1 (30000,30000,30000) L_0x1dd0b10/d; +L_0x1dd0f00/d .functor OR 1, L_0x1dd0f70, L_0x1dd1120, C4<0>, C4<0>; +L_0x1dd0f00 .delay 1 (30000,30000,30000) L_0x1dd0f00/d; +v0x1bc9d50_0 .net *"_s0", 0 0, L_0x1dd0710; 1 drivers +v0x1bc9e50_0 .net *"_s10", 0 0, L_0x1dd0c20; 1 drivers +v0x1bc9f30_0 .net *"_s12", 0 0, L_0x1dd0d80; 1 drivers +v0x1bc9ff0_0 .net *"_s14", 0 0, L_0x1dd0f70; 1 drivers +v0x1bca0d0_0 .net *"_s16", 0 0, L_0x1dd1120; 1 drivers +v0x1bca200_0 .net *"_s3", 0 0, L_0x1dd0780; 1 drivers +v0x1bca2e0_0 .net *"_s5", 0 0, L_0x1dd08e0; 1 drivers +v0x1bca3c0_0 .net *"_s6", 0 0, L_0x1dd0b10; 1 drivers +v0x1bca4a0_0 .net "in", 3 0, L_0x1dd1350; 1 drivers +v0x1bca610_0 .net "ors", 1 0, L_0x1dd0a20; 1 drivers +v0x1bca6f0_0 .net "out", 0 0, L_0x1dd0f00; 1 drivers +L_0x1dd0780 .part L_0x1dd1350, 0, 1; +L_0x1dd08e0 .part L_0x1dd1350, 1, 1; +L_0x1dd0a20 .concat8 [ 1 1 0 0], L_0x1dd0710, L_0x1dd0b10; +L_0x1dd0c20 .part L_0x1dd1350, 2, 1; +L_0x1dd0d80 .part L_0x1dd1350, 3, 1; +L_0x1dd0f70 .part L_0x1dd0a20, 0, 1; +L_0x1dd1120 .part L_0x1dd0a20, 1, 1; +S_0x1bcb000 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bc4130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bd0430_0 .net "ands", 7 0, L_0x1dcb9b0; 1 drivers +v0x1bd0540_0 .net "in", 7 0, L_0x1dc9e10; alias, 1 drivers +v0x1bd0600_0 .net "out", 0 0, L_0x1dcd9b0; alias, 1 drivers +v0x1bd06d0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bcb250 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bcb000; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bcd990_0 .net "A", 7 0, L_0x1dc9e10; alias, 1 drivers +v0x1bcda90_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bcdb50_0 .net *"_s0", 0 0, L_0x1dca1a0; 1 drivers +v0x1bcdc10_0 .net *"_s12", 0 0, L_0x1dcab60; 1 drivers +v0x1bcdcf0_0 .net *"_s16", 0 0, L_0x1dcaec0; 1 drivers +v0x1bcde20_0 .net *"_s20", 0 0, L_0x1dcb2f0; 1 drivers +v0x1bcdf00_0 .net *"_s24", 0 0, L_0x1dcb620; 1 drivers +v0x1bcdfe0_0 .net *"_s28", 0 0, L_0x1dcb5b0; 1 drivers +v0x1bce0c0_0 .net *"_s4", 0 0, L_0x1dca540; 1 drivers +v0x1bce230_0 .net *"_s8", 0 0, L_0x1dca850; 1 drivers +v0x1bce310_0 .net "out", 7 0, L_0x1dcb9b0; alias, 1 drivers +L_0x1dca2b0 .part L_0x1dc9e10, 0, 1; +L_0x1dca4a0 .part v0x1d6daa0_0, 0, 1; +L_0x1dca600 .part L_0x1dc9e10, 1, 1; +L_0x1dca760 .part v0x1d6daa0_0, 1, 1; +L_0x1dca910 .part L_0x1dc9e10, 2, 1; +L_0x1dcaa70 .part v0x1d6daa0_0, 2, 1; +L_0x1dcac20 .part L_0x1dc9e10, 3, 1; +L_0x1dcad80 .part v0x1d6daa0_0, 3, 1; +L_0x1dcaf80 .part L_0x1dc9e10, 4, 1; +L_0x1dcb1f0 .part v0x1d6daa0_0, 4, 1; +L_0x1dcb360 .part L_0x1dc9e10, 5, 1; +L_0x1dcb4c0 .part v0x1d6daa0_0, 5, 1; +L_0x1dcb6e0 .part L_0x1dc9e10, 6, 1; +L_0x1dcb840 .part v0x1d6daa0_0, 6, 1; +LS_0x1dcb9b0_0_0 .concat8 [ 1 1 1 1], L_0x1dca1a0, L_0x1dca540, L_0x1dca850, L_0x1dcab60; +LS_0x1dcb9b0_0_4 .concat8 [ 1 1 1 1], L_0x1dcaec0, L_0x1dcb2f0, L_0x1dcb620, L_0x1dcb5b0; +L_0x1dcb9b0 .concat8 [ 4 4 0 0], LS_0x1dcb9b0_0_0, LS_0x1dcb9b0_0_4; +L_0x1dcbd70 .part L_0x1dc9e10, 7, 1; +L_0x1dcbf60 .part v0x1d6daa0_0, 7, 1; +S_0x1bcb490 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcb6a0 .param/l "i" 0 4 54, +C4<00>; +L_0x1dca1a0/d .functor AND 1, L_0x1dca2b0, L_0x1dca4a0, C4<1>, C4<1>; +L_0x1dca1a0 .delay 1 (30000,30000,30000) L_0x1dca1a0/d; +v0x1bcb780_0 .net *"_s0", 0 0, L_0x1dca2b0; 1 drivers +v0x1bcb860_0 .net *"_s1", 0 0, L_0x1dca4a0; 1 drivers +S_0x1bcb940 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcbb50 .param/l "i" 0 4 54, +C4<01>; +L_0x1dca540/d .functor AND 1, L_0x1dca600, L_0x1dca760, C4<1>, C4<1>; +L_0x1dca540 .delay 1 (30000,30000,30000) L_0x1dca540/d; +v0x1bcbc10_0 .net *"_s0", 0 0, L_0x1dca600; 1 drivers +v0x1bcbcf0_0 .net *"_s1", 0 0, L_0x1dca760; 1 drivers +S_0x1bcbdd0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcc010 .param/l "i" 0 4 54, +C4<010>; +L_0x1dca850/d .functor AND 1, L_0x1dca910, L_0x1dcaa70, C4<1>, C4<1>; +L_0x1dca850 .delay 1 (30000,30000,30000) L_0x1dca850/d; +v0x1bcc0b0_0 .net *"_s0", 0 0, L_0x1dca910; 1 drivers +v0x1bcc190_0 .net *"_s1", 0 0, L_0x1dcaa70; 1 drivers +S_0x1bcc270 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcc480 .param/l "i" 0 4 54, +C4<011>; +L_0x1dcab60/d .functor AND 1, L_0x1dcac20, L_0x1dcad80, C4<1>, C4<1>; +L_0x1dcab60 .delay 1 (30000,30000,30000) L_0x1dcab60/d; +v0x1bcc540_0 .net *"_s0", 0 0, L_0x1dcac20; 1 drivers +v0x1bcc620_0 .net *"_s1", 0 0, L_0x1dcad80; 1 drivers +S_0x1bcc700 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcc960 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dcaec0/d .functor AND 1, L_0x1dcaf80, L_0x1dcb1f0, C4<1>, C4<1>; +L_0x1dcaec0 .delay 1 (30000,30000,30000) L_0x1dcaec0/d; +v0x1bcca20_0 .net *"_s0", 0 0, L_0x1dcaf80; 1 drivers +v0x1bccb00_0 .net *"_s1", 0 0, L_0x1dcb1f0; 1 drivers +S_0x1bccbe0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bccdf0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dcb2f0/d .functor AND 1, L_0x1dcb360, L_0x1dcb4c0, C4<1>, C4<1>; +L_0x1dcb2f0 .delay 1 (30000,30000,30000) L_0x1dcb2f0/d; +v0x1bcceb0_0 .net *"_s0", 0 0, L_0x1dcb360; 1 drivers +v0x1bccf90_0 .net *"_s1", 0 0, L_0x1dcb4c0; 1 drivers +S_0x1bcd070 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcd280 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dcb620/d .functor AND 1, L_0x1dcb6e0, L_0x1dcb840, C4<1>, C4<1>; +L_0x1dcb620 .delay 1 (30000,30000,30000) L_0x1dcb620/d; +v0x1bcd340_0 .net *"_s0", 0 0, L_0x1dcb6e0; 1 drivers +v0x1bcd420_0 .net *"_s1", 0 0, L_0x1dcb840; 1 drivers +S_0x1bcd500 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bcb250; + .timescale -9 -12; +P_0x1bcd710 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dcb5b0/d .functor AND 1, L_0x1dcbd70, L_0x1dcbf60, C4<1>, C4<1>; +L_0x1dcb5b0 .delay 1 (30000,30000,30000) L_0x1dcb5b0/d; +v0x1bcd7d0_0 .net *"_s0", 0 0, L_0x1dcbd70; 1 drivers +v0x1bcd8b0_0 .net *"_s1", 0 0, L_0x1dcbf60; 1 drivers +S_0x1bce470 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bcb000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dcd9b0/d .functor OR 1, L_0x1dcda70, L_0x1dcdc20, C4<0>, C4<0>; +L_0x1dcd9b0 .delay 1 (30000,30000,30000) L_0x1dcd9b0/d; +v0x1bcffc0_0 .net *"_s10", 0 0, L_0x1dcda70; 1 drivers +v0x1bd00a0_0 .net *"_s12", 0 0, L_0x1dcdc20; 1 drivers +v0x1bd0180_0 .net "in", 7 0, L_0x1dcb9b0; alias, 1 drivers +v0x1bd0250_0 .net "ors", 1 0, L_0x1dcd7d0; 1 drivers +v0x1bd0310_0 .net "out", 0 0, L_0x1dcd9b0; alias, 1 drivers +L_0x1dccba0 .part L_0x1dcb9b0, 0, 4; +L_0x1dcd7d0 .concat8 [ 1 1 0 0], L_0x1dcc890, L_0x1dcd4c0; +L_0x1dcd910 .part L_0x1dcb9b0, 4, 4; +L_0x1dcda70 .part L_0x1dcd7d0, 0, 1; +L_0x1dcdc20 .part L_0x1dcd7d0, 1, 1; +S_0x1bce630 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bce470; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dcc050/d .functor OR 1, L_0x1dcc110, L_0x1dcc270, C4<0>, C4<0>; +L_0x1dcc050 .delay 1 (30000,30000,30000) L_0x1dcc050/d; +L_0x1dcc4a0/d .functor OR 1, L_0x1dcc5b0, L_0x1dcc710, C4<0>, C4<0>; +L_0x1dcc4a0 .delay 1 (30000,30000,30000) L_0x1dcc4a0/d; +L_0x1dcc890/d .functor OR 1, L_0x1dcc900, L_0x1dccab0, C4<0>, C4<0>; +L_0x1dcc890 .delay 1 (30000,30000,30000) L_0x1dcc890/d; +v0x1bce880_0 .net *"_s0", 0 0, L_0x1dcc050; 1 drivers +v0x1bce980_0 .net *"_s10", 0 0, L_0x1dcc5b0; 1 drivers +v0x1bcea60_0 .net *"_s12", 0 0, L_0x1dcc710; 1 drivers +v0x1bceb20_0 .net *"_s14", 0 0, L_0x1dcc900; 1 drivers +v0x1bcec00_0 .net *"_s16", 0 0, L_0x1dccab0; 1 drivers +v0x1bced30_0 .net *"_s3", 0 0, L_0x1dcc110; 1 drivers +v0x1bcee10_0 .net *"_s5", 0 0, L_0x1dcc270; 1 drivers +v0x1bceef0_0 .net *"_s6", 0 0, L_0x1dcc4a0; 1 drivers +v0x1bcefd0_0 .net "in", 3 0, L_0x1dccba0; 1 drivers +v0x1bcf140_0 .net "ors", 1 0, L_0x1dcc3b0; 1 drivers +v0x1bcf220_0 .net "out", 0 0, L_0x1dcc890; 1 drivers +L_0x1dcc110 .part L_0x1dccba0, 0, 1; +L_0x1dcc270 .part L_0x1dccba0, 1, 1; +L_0x1dcc3b0 .concat8 [ 1 1 0 0], L_0x1dcc050, L_0x1dcc4a0; +L_0x1dcc5b0 .part L_0x1dccba0, 2, 1; +L_0x1dcc710 .part L_0x1dccba0, 3, 1; +L_0x1dcc900 .part L_0x1dcc3b0, 0, 1; +L_0x1dccab0 .part L_0x1dcc3b0, 1, 1; +S_0x1bcf340 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bce470; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dcccd0/d .functor OR 1, L_0x1dccd40, L_0x1dccea0, C4<0>, C4<0>; +L_0x1dcccd0 .delay 1 (30000,30000,30000) L_0x1dcccd0/d; +L_0x1dcd0d0/d .functor OR 1, L_0x1dcd1e0, L_0x1dcd340, C4<0>, C4<0>; +L_0x1dcd0d0 .delay 1 (30000,30000,30000) L_0x1dcd0d0/d; +L_0x1dcd4c0/d .functor OR 1, L_0x1dcd530, L_0x1dcd6e0, C4<0>, C4<0>; +L_0x1dcd4c0 .delay 1 (30000,30000,30000) L_0x1dcd4c0/d; +v0x1bcf500_0 .net *"_s0", 0 0, L_0x1dcccd0; 1 drivers +v0x1bcf600_0 .net *"_s10", 0 0, L_0x1dcd1e0; 1 drivers +v0x1bcf6e0_0 .net *"_s12", 0 0, L_0x1dcd340; 1 drivers +v0x1bcf7a0_0 .net *"_s14", 0 0, L_0x1dcd530; 1 drivers +v0x1bcf880_0 .net *"_s16", 0 0, L_0x1dcd6e0; 1 drivers +v0x1bcf9b0_0 .net *"_s3", 0 0, L_0x1dccd40; 1 drivers +v0x1bcfa90_0 .net *"_s5", 0 0, L_0x1dccea0; 1 drivers +v0x1bcfb70_0 .net *"_s6", 0 0, L_0x1dcd0d0; 1 drivers +v0x1bcfc50_0 .net "in", 3 0, L_0x1dcd910; 1 drivers +v0x1bcfdc0_0 .net "ors", 1 0, L_0x1dccfe0; 1 drivers +v0x1bcfea0_0 .net "out", 0 0, L_0x1dcd4c0; 1 drivers +L_0x1dccd40 .part L_0x1dcd910, 0, 1; +L_0x1dccea0 .part L_0x1dcd910, 1, 1; +L_0x1dccfe0 .concat8 [ 1 1 0 0], L_0x1dcccd0, L_0x1dcd0d0; +L_0x1dcd1e0 .part L_0x1dcd910, 2, 1; +L_0x1dcd340 .part L_0x1dcd910, 3, 1; +L_0x1dcd530 .part L_0x1dccfe0, 0, 1; +L_0x1dcd6e0 .part L_0x1dccfe0, 1, 1; +S_0x1bd07b0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bc4130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1dc9180/d .functor XNOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; +L_0x1dc9180 .delay 1 (20000,20000,20000) L_0x1dc9180/d; +L_0x1dc93f0/d .functor AND 1, L_0x1dd1850, L_0x1dc1c20, C4<1>, C4<1>; +L_0x1dc93f0 .delay 1 (30000,30000,30000) L_0x1dc93f0/d; +L_0x1dc9460/d .functor AND 1, L_0x1dc9180, L_0x1dd1aa0, C4<1>, C4<1>; +L_0x1dc9460 .delay 1 (30000,30000,30000) L_0x1dc9460/d; +L_0x1dc95c0/d .functor OR 1, L_0x1dc9460, L_0x1dc93f0, C4<0>, C4<0>; +L_0x1dc95c0 .delay 1 (30000,30000,30000) L_0x1dc95c0/d; +v0x1bd0a60_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers +v0x1bd0b50_0 .net "a_", 0 0, L_0x1dc7f10; alias, 1 drivers +v0x1bd0c10_0 .net "b", 0 0, L_0x1dc7d40; alias, 1 drivers +v0x1bd0d00_0 .net "b_", 0 0, L_0x1dc1c20; alias, 1 drivers +v0x1bd0da0_0 .net "carryin", 0 0, L_0x1dd1aa0; alias, 1 drivers +v0x1bd0ee0_0 .net "eq", 0 0, L_0x1dc9180; 1 drivers +v0x1bd0fa0_0 .net "lt", 0 0, L_0x1dc93f0; 1 drivers +v0x1bd1060_0 .net "out", 0 0, L_0x1dc95c0; 1 drivers +v0x1bd1120_0 .net "w0", 0 0, L_0x1dc9460; 1 drivers +S_0x1bd1370 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bc4130; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dc8f60/d .functor OR 1, L_0x1dc8ab0, L_0x1bd25d0, C4<0>, C4<0>; +L_0x1dc8f60 .delay 1 (30000,30000,30000) L_0x1dc8f60/d; +v0x1bd2160_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers +v0x1bd22b0_0 .net "b", 0 0, L_0x1dc1c20; alias, 1 drivers +v0x1bd2370_0 .net "c1", 0 0, L_0x1dc8ab0; 1 drivers +v0x1bd2410_0 .net "c2", 0 0, L_0x1bd25d0; 1 drivers +v0x1bd24e0_0 .net "carryin", 0 0, L_0x1dd1aa0; alias, 1 drivers +v0x1bd2660_0 .net "carryout", 0 0, L_0x1dc8f60; 1 drivers +v0x1bd2700_0 .net "s1", 0 0, L_0x1dc89f0; 1 drivers +v0x1bd27a0_0 .net "sum", 0 0, L_0x1dc8c10; 1 drivers +S_0x1bd15c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bd1370; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dc89f0/d .functor XOR 1, L_0x1dd1850, L_0x1dc1c20, C4<0>, C4<0>; +L_0x1dc89f0 .delay 1 (30000,30000,30000) L_0x1dc89f0/d; +L_0x1dc8ab0/d .functor AND 1, L_0x1dd1850, L_0x1dc1c20, C4<1>, C4<1>; +L_0x1dc8ab0 .delay 1 (30000,30000,30000) L_0x1dc8ab0/d; +v0x1bd1820_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers +v0x1bd18e0_0 .net "b", 0 0, L_0x1dc1c20; alias, 1 drivers +v0x1bd19a0_0 .net "carryout", 0 0, L_0x1dc8ab0; alias, 1 drivers +v0x1bd1a40_0 .net "sum", 0 0, L_0x1dc89f0; alias, 1 drivers +S_0x1bd1b70 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bd1370; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dc8c10/d .functor XOR 1, L_0x1dc89f0, L_0x1dd1aa0, C4<0>, C4<0>; +L_0x1dc8c10 .delay 1 (30000,30000,30000) L_0x1dc8c10/d; +L_0x1bd25d0/d .functor AND 1, L_0x1dc89f0, L_0x1dd1aa0, C4<1>, C4<1>; +L_0x1bd25d0 .delay 1 (30000,30000,30000) L_0x1bd25d0/d; +v0x1bd1dd0_0 .net "a", 0 0, L_0x1dc89f0; alias, 1 drivers +v0x1bd1ea0_0 .net "b", 0 0, L_0x1dd1aa0; alias, 1 drivers +v0x1bd1f40_0 .net "carryout", 0 0, L_0x1bd25d0; alias, 1 drivers +v0x1bd2010_0 .net "sum", 0 0, L_0x1dc8c10; alias, 1 drivers +S_0x1bd3bc0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bc3e60; + .timescale -9 -12; +L_0x7f72592daa38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592daa80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dd18f0/d .functor OR 1, L_0x7f72592daa38, L_0x7f72592daa80, C4<0>, C4<0>; +L_0x1dd18f0 .delay 1 (30000,30000,30000) L_0x1dd18f0/d; +v0x1bd3db0_0 .net/2u *"_s0", 0 0, L_0x7f72592daa38; 1 drivers +v0x1bd3e90_0 .net/2u *"_s2", 0 0, L_0x7f72592daa80; 1 drivers +S_0x1bd3f70 .scope generate, "alu_slices[10]" "alu_slices[10]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1bd4180 .param/l "i" 0 3 37, +C4<01010>; +S_0x1bd4240 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bd3f70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1dd1c90/d .functor NOT 1, L_0x1ddb470, C4<0>, C4<0>, C4<0>; +L_0x1dd1c90 .delay 1 (10000,10000,10000) L_0x1dd1c90/d; +L_0x1dd1da0/d .functor NOT 1, L_0x1ddb5d0, C4<0>, C4<0>, C4<0>; +L_0x1dd1da0 .delay 1 (10000,10000,10000) L_0x1dd1da0/d; +L_0x1dd2df0/d .functor XOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; +L_0x1dd2df0 .delay 1 (30000,30000,30000) L_0x1dd2df0/d; +L_0x7f72592daac8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dab10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dd34a0/d .functor OR 1, L_0x7f72592daac8, L_0x7f72592dab10, C4<0>, C4<0>; +L_0x1dd34a0 .delay 1 (30000,30000,30000) L_0x1dd34a0/d; +L_0x1dd36a0/d .functor AND 1, L_0x1ddb470, L_0x1ddb5d0, C4<1>, C4<1>; +L_0x1dd36a0 .delay 1 (30000,30000,30000) L_0x1dd36a0/d; +L_0x1dd3760/d .functor NAND 1, L_0x1ddb470, L_0x1ddb5d0, C4<1>, C4<1>; +L_0x1dd3760 .delay 1 (20000,20000,20000) L_0x1dd3760/d; +L_0x1dd38c0/d .functor XOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; +L_0x1dd38c0 .delay 1 (20000,20000,20000) L_0x1dd38c0/d; +L_0x1dd3d70/d .functor OR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; +L_0x1dd3d70 .delay 1 (30000,30000,30000) L_0x1dd3d70/d; +L_0x1ddb370/d .functor NOT 1, L_0x1dd7600, C4<0>, C4<0>, C4<0>; +L_0x1ddb370 .delay 1 (10000,10000,10000) L_0x1ddb370/d; +v0x1be2970_0 .net "A", 0 0, L_0x1ddb470; 1 drivers +v0x1be2a30_0 .net "A_", 0 0, L_0x1dd1c90; 1 drivers +v0x1be2af0_0 .net "B", 0 0, L_0x1ddb5d0; 1 drivers +v0x1be2bc0_0 .net "B_", 0 0, L_0x1dd1da0; 1 drivers +v0x1be2c60_0 .net *"_s12", 0 0, L_0x1dd34a0; 1 drivers +v0x1be2d50_0 .net/2s *"_s14", 0 0, L_0x7f72592daac8; 1 drivers +v0x1be2e10_0 .net/2s *"_s16", 0 0, L_0x7f72592dab10; 1 drivers +v0x1be2ef0_0 .net *"_s18", 0 0, L_0x1dd36a0; 1 drivers +v0x1be2fd0_0 .net *"_s20", 0 0, L_0x1dd3760; 1 drivers +v0x1be3140_0 .net *"_s22", 0 0, L_0x1dd38c0; 1 drivers +v0x1be3220_0 .net *"_s24", 0 0, L_0x1dd3d70; 1 drivers +o0x7f725936d7e8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1be3300_0 name=_s30 +o0x7f725936d818 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1be33e0_0 name=_s32 +v0x1be34c0_0 .net *"_s8", 0 0, L_0x1dd2df0; 1 drivers +v0x1be35a0_0 .net "carryin", 0 0, L_0x1dd1b40; 1 drivers +v0x1be3640_0 .net "carryout", 0 0, L_0x1ddb010; 1 drivers +v0x1be36e0_0 .net "carryouts", 7 0, L_0x1ebfb50; 1 drivers +v0x1be3890_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1be3930_0 .net "result", 0 0, L_0x1dd7600; 1 drivers +v0x1be3a20_0 .net "results", 7 0, L_0x1dd3b40; 1 drivers +v0x1be3b30_0 .net "zero", 0 0, L_0x1ddb370; 1 drivers +LS_0x1dd3b40_0_0 .concat8 [ 1 1 1 1], L_0x1dd22c0, L_0x1dd28f0, L_0x1dd2df0, L_0x1dd34a0; +LS_0x1dd3b40_0_4 .concat8 [ 1 1 1 1], L_0x1dd36a0, L_0x1dd3760, L_0x1dd38c0, L_0x1dd3d70; +L_0x1dd3b40 .concat8 [ 4 4 0 0], LS_0x1dd3b40_0_0, LS_0x1dd3b40_0_4; +LS_0x1ebfb50_0_0 .concat [ 1 1 1 1], L_0x1dd2570, L_0x1dd2c90, o0x7f725936d7e8, L_0x1dd32f0; +LS_0x1ebfb50_0_4 .concat [ 4 0 0 0], o0x7f725936d818; +L_0x1ebfb50 .concat [ 4 4 0 0], LS_0x1ebfb50_0_0, LS_0x1ebfb50_0_4; +S_0x1bd44c0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bd4240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dd2570/d .functor OR 1, L_0x1dd2050, L_0x1dd2410, C4<0>, C4<0>; +L_0x1dd2570 .delay 1 (30000,30000,30000) L_0x1dd2570/d; +v0x1bd52f0_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers +v0x1bd53b0_0 .net "b", 0 0, L_0x1ddb5d0; alias, 1 drivers +v0x1bd5480_0 .net "c1", 0 0, L_0x1dd2050; 1 drivers +v0x1bd5580_0 .net "c2", 0 0, L_0x1dd2410; 1 drivers +v0x1bd5650_0 .net "carryin", 0 0, L_0x1dd1b40; alias, 1 drivers +v0x1bd5740_0 .net "carryout", 0 0, L_0x1dd2570; 1 drivers +v0x1bd57e0_0 .net "s1", 0 0, L_0x1dd1f90; 1 drivers +v0x1bd58d0_0 .net "sum", 0 0, L_0x1dd22c0; 1 drivers +S_0x1bd4730 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bd44c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dd1f90/d .functor XOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; +L_0x1dd1f90 .delay 1 (30000,30000,30000) L_0x1dd1f90/d; +L_0x1dd2050/d .functor AND 1, L_0x1ddb470, L_0x1ddb5d0, C4<1>, C4<1>; +L_0x1dd2050 .delay 1 (30000,30000,30000) L_0x1dd2050/d; +v0x1bd4990_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers +v0x1bd4a70_0 .net "b", 0 0, L_0x1ddb5d0; alias, 1 drivers +v0x1bd4b30_0 .net "carryout", 0 0, L_0x1dd2050; alias, 1 drivers +v0x1bd4bd0_0 .net "sum", 0 0, L_0x1dd1f90; alias, 1 drivers +S_0x1bd4d10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bd44c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dd22c0/d .functor XOR 1, L_0x1dd1f90, L_0x1dd1b40, C4<0>, C4<0>; +L_0x1dd22c0 .delay 1 (30000,30000,30000) L_0x1dd22c0/d; +L_0x1dd2410/d .functor AND 1, L_0x1dd1f90, L_0x1dd1b40, C4<1>, C4<1>; +L_0x1dd2410 .delay 1 (30000,30000,30000) L_0x1dd2410/d; +v0x1bd4f70_0 .net "a", 0 0, L_0x1dd1f90; alias, 1 drivers +v0x1bd5010_0 .net "b", 0 0, L_0x1dd1b40; alias, 1 drivers +v0x1bd50b0_0 .net "carryout", 0 0, L_0x1dd2410; alias, 1 drivers +v0x1bd5180_0 .net "sum", 0 0, L_0x1dd22c0; alias, 1 drivers +S_0x1bd59a0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bd4240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bdad90_0 .net "ands", 7 0, L_0x1dd8ff0; 1 drivers +v0x1bdaea0_0 .net "in", 7 0, L_0x1ebfb50; alias, 1 drivers +v0x1bdaf60_0 .net "out", 0 0, L_0x1ddb010; alias, 1 drivers +v0x1bdb030_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bd5bc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bd59a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bd82f0_0 .net "A", 7 0, L_0x1ebfb50; alias, 1 drivers +v0x1bd83f0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bd84b0_0 .net *"_s0", 0 0, L_0x1dd7960; 1 drivers +v0x1bd8570_0 .net *"_s12", 0 0, L_0x1dd82d0; 1 drivers +v0x1bd8650_0 .net *"_s16", 0 0, L_0x1dd8630; 1 drivers +v0x1bd8780_0 .net *"_s20", 0 0, L_0x1dd8940; 1 drivers +v0x1bd8860_0 .net *"_s24", 0 0, L_0x1dd8d30; 1 drivers +v0x1bd8940_0 .net *"_s28", 0 0, L_0x1dd92c0; 1 drivers +v0x1bd8a20_0 .net *"_s4", 0 0, L_0x1dd7c70; 1 drivers +v0x1bd8b90_0 .net *"_s8", 0 0, L_0x1dd7fc0; 1 drivers +v0x1bd8c70_0 .net "out", 7 0, L_0x1dd8ff0; alias, 1 drivers +L_0x1dd7a20 .part L_0x1ebfb50, 0, 1; +L_0x1dd7b80 .part v0x1d6daa0_0, 0, 1; +L_0x1dd7d30 .part L_0x1ebfb50, 1, 1; +L_0x1dd7f20 .part v0x1d6daa0_0, 1, 1; +L_0x1dd8080 .part L_0x1ebfb50, 2, 1; +L_0x1dd81e0 .part v0x1d6daa0_0, 2, 1; +L_0x1dd8390 .part L_0x1ebfb50, 3, 1; +L_0x1dd84f0 .part v0x1d6daa0_0, 3, 1; +L_0x1dd86f0 .part L_0x1ebfb50, 4, 1; +L_0x1dd8850 .part v0x1d6daa0_0, 4, 1; +L_0x1dd89b0 .part L_0x1ebfb50, 5, 1; +L_0x1dd8c20 .part v0x1d6daa0_0, 5, 1; +L_0x1dd8df0 .part L_0x1ebfb50, 6, 1; +L_0x1dd8f50 .part v0x1d6daa0_0, 6, 1; +LS_0x1dd8ff0_0_0 .concat8 [ 1 1 1 1], L_0x1dd7960, L_0x1dd7c70, L_0x1dd7fc0, L_0x1dd82d0; +LS_0x1dd8ff0_0_4 .concat8 [ 1 1 1 1], L_0x1dd8630, L_0x1dd8940, L_0x1dd8d30, L_0x1dd92c0; +L_0x1dd8ff0 .concat8 [ 4 4 0 0], LS_0x1dd8ff0_0_0, LS_0x1dd8ff0_0_4; +L_0x1dd93d0 .part L_0x1ebfb50, 7, 1; +L_0x1dd95c0 .part v0x1d6daa0_0, 7, 1; +S_0x1bd5e20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd6030 .param/l "i" 0 4 54, +C4<00>; +L_0x1dd7960/d .functor AND 1, L_0x1dd7a20, L_0x1dd7b80, C4<1>, C4<1>; +L_0x1dd7960 .delay 1 (30000,30000,30000) L_0x1dd7960/d; +v0x1bd6110_0 .net *"_s0", 0 0, L_0x1dd7a20; 1 drivers +v0x1bd61f0_0 .net *"_s1", 0 0, L_0x1dd7b80; 1 drivers +S_0x1bd62d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd64e0 .param/l "i" 0 4 54, +C4<01>; +L_0x1dd7c70/d .functor AND 1, L_0x1dd7d30, L_0x1dd7f20, C4<1>, C4<1>; +L_0x1dd7c70 .delay 1 (30000,30000,30000) L_0x1dd7c70/d; +v0x1bd65a0_0 .net *"_s0", 0 0, L_0x1dd7d30; 1 drivers +v0x1bd6680_0 .net *"_s1", 0 0, L_0x1dd7f20; 1 drivers +S_0x1bd6760 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd6970 .param/l "i" 0 4 54, +C4<010>; +L_0x1dd7fc0/d .functor AND 1, L_0x1dd8080, L_0x1dd81e0, C4<1>, C4<1>; +L_0x1dd7fc0 .delay 1 (30000,30000,30000) L_0x1dd7fc0/d; +v0x1bd6a10_0 .net *"_s0", 0 0, L_0x1dd8080; 1 drivers +v0x1bd6af0_0 .net *"_s1", 0 0, L_0x1dd81e0; 1 drivers +S_0x1bd6bd0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd6de0 .param/l "i" 0 4 54, +C4<011>; +L_0x1dd82d0/d .functor AND 1, L_0x1dd8390, L_0x1dd84f0, C4<1>, C4<1>; +L_0x1dd82d0 .delay 1 (30000,30000,30000) L_0x1dd82d0/d; +v0x1bd6ea0_0 .net *"_s0", 0 0, L_0x1dd8390; 1 drivers +v0x1bd6f80_0 .net *"_s1", 0 0, L_0x1dd84f0; 1 drivers +S_0x1bd7060 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd72c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dd8630/d .functor AND 1, L_0x1dd86f0, L_0x1dd8850, C4<1>, C4<1>; +L_0x1dd8630 .delay 1 (30000,30000,30000) L_0x1dd8630/d; +v0x1bd7380_0 .net *"_s0", 0 0, L_0x1dd86f0; 1 drivers +v0x1bd7460_0 .net *"_s1", 0 0, L_0x1dd8850; 1 drivers +S_0x1bd7540 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd7750 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dd8940/d .functor AND 1, L_0x1dd89b0, L_0x1dd8c20, C4<1>, C4<1>; +L_0x1dd8940 .delay 1 (30000,30000,30000) L_0x1dd8940/d; +v0x1bd7810_0 .net *"_s0", 0 0, L_0x1dd89b0; 1 drivers +v0x1bd78f0_0 .net *"_s1", 0 0, L_0x1dd8c20; 1 drivers +S_0x1bd79d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd7be0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dd8d30/d .functor AND 1, L_0x1dd8df0, L_0x1dd8f50, C4<1>, C4<1>; +L_0x1dd8d30 .delay 1 (30000,30000,30000) L_0x1dd8d30/d; +v0x1bd7ca0_0 .net *"_s0", 0 0, L_0x1dd8df0; 1 drivers +v0x1bd7d80_0 .net *"_s1", 0 0, L_0x1dd8f50; 1 drivers +S_0x1bd7e60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bd5bc0; + .timescale -9 -12; +P_0x1bd8070 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dd92c0/d .functor AND 1, L_0x1dd93d0, L_0x1dd95c0, C4<1>, C4<1>; +L_0x1dd92c0 .delay 1 (30000,30000,30000) L_0x1dd92c0/d; +v0x1bd8130_0 .net *"_s0", 0 0, L_0x1dd93d0; 1 drivers +v0x1bd8210_0 .net *"_s1", 0 0, L_0x1dd95c0; 1 drivers +S_0x1bd8dd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bd59a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1ddb010/d .functor OR 1, L_0x1ddb0d0, L_0x1ddb280, C4<0>, C4<0>; +L_0x1ddb010 .delay 1 (30000,30000,30000) L_0x1ddb010/d; +v0x1bda920_0 .net *"_s10", 0 0, L_0x1ddb0d0; 1 drivers +v0x1bdaa00_0 .net *"_s12", 0 0, L_0x1ddb280; 1 drivers +v0x1bdaae0_0 .net "in", 7 0, L_0x1dd8ff0; alias, 1 drivers +v0x1bdabb0_0 .net "ors", 1 0, L_0x1ddae30; 1 drivers +v0x1bdac70_0 .net "out", 0 0, L_0x1ddb010; alias, 1 drivers +L_0x1dda200 .part L_0x1dd8ff0, 0, 4; +L_0x1ddae30 .concat8 [ 1 1 0 0], L_0x1dd9ef0, L_0x1ddab20; +L_0x1ddaf70 .part L_0x1dd8ff0, 4, 4; +L_0x1ddb0d0 .part L_0x1ddae30, 0, 1; +L_0x1ddb280 .part L_0x1ddae30, 1, 1; +S_0x1bd8f90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bd8dd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dd96b0/d .functor OR 1, L_0x1dd9770, L_0x1dd98d0, C4<0>, C4<0>; +L_0x1dd96b0 .delay 1 (30000,30000,30000) L_0x1dd96b0/d; +L_0x1dd9b00/d .functor OR 1, L_0x1dd9c10, L_0x1dd9d70, C4<0>, C4<0>; +L_0x1dd9b00 .delay 1 (30000,30000,30000) L_0x1dd9b00/d; +L_0x1dd9ef0/d .functor OR 1, L_0x1dd9f60, L_0x1dda110, C4<0>, C4<0>; +L_0x1dd9ef0 .delay 1 (30000,30000,30000) L_0x1dd9ef0/d; +v0x1bd91e0_0 .net *"_s0", 0 0, L_0x1dd96b0; 1 drivers +v0x1bd92e0_0 .net *"_s10", 0 0, L_0x1dd9c10; 1 drivers +v0x1bd93c0_0 .net *"_s12", 0 0, L_0x1dd9d70; 1 drivers +v0x1bd9480_0 .net *"_s14", 0 0, L_0x1dd9f60; 1 drivers +v0x1bd9560_0 .net *"_s16", 0 0, L_0x1dda110; 1 drivers +v0x1bd9690_0 .net *"_s3", 0 0, L_0x1dd9770; 1 drivers +v0x1bd9770_0 .net *"_s5", 0 0, L_0x1dd98d0; 1 drivers +v0x1bd9850_0 .net *"_s6", 0 0, L_0x1dd9b00; 1 drivers +v0x1bd9930_0 .net "in", 3 0, L_0x1dda200; 1 drivers +v0x1bd9aa0_0 .net "ors", 1 0, L_0x1dd9a10; 1 drivers +v0x1bd9b80_0 .net "out", 0 0, L_0x1dd9ef0; 1 drivers +L_0x1dd9770 .part L_0x1dda200, 0, 1; +L_0x1dd98d0 .part L_0x1dda200, 1, 1; +L_0x1dd9a10 .concat8 [ 1 1 0 0], L_0x1dd96b0, L_0x1dd9b00; +L_0x1dd9c10 .part L_0x1dda200, 2, 1; +L_0x1dd9d70 .part L_0x1dda200, 3, 1; +L_0x1dd9f60 .part L_0x1dd9a10, 0, 1; +L_0x1dda110 .part L_0x1dd9a10, 1, 1; +S_0x1bd9ca0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bd8dd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dda330/d .functor OR 1, L_0x1dda3a0, L_0x1dda500, C4<0>, C4<0>; +L_0x1dda330 .delay 1 (30000,30000,30000) L_0x1dda330/d; +L_0x1dda730/d .functor OR 1, L_0x1dda840, L_0x1dda9a0, C4<0>, C4<0>; +L_0x1dda730 .delay 1 (30000,30000,30000) L_0x1dda730/d; +L_0x1ddab20/d .functor OR 1, L_0x1ddab90, L_0x1ddad40, C4<0>, C4<0>; +L_0x1ddab20 .delay 1 (30000,30000,30000) L_0x1ddab20/d; +v0x1bd9e60_0 .net *"_s0", 0 0, L_0x1dda330; 1 drivers +v0x1bd9f60_0 .net *"_s10", 0 0, L_0x1dda840; 1 drivers +v0x1bda040_0 .net *"_s12", 0 0, L_0x1dda9a0; 1 drivers +v0x1bda100_0 .net *"_s14", 0 0, L_0x1ddab90; 1 drivers +v0x1bda1e0_0 .net *"_s16", 0 0, L_0x1ddad40; 1 drivers +v0x1bda310_0 .net *"_s3", 0 0, L_0x1dda3a0; 1 drivers +v0x1bda3f0_0 .net *"_s5", 0 0, L_0x1dda500; 1 drivers +v0x1bda4d0_0 .net *"_s6", 0 0, L_0x1dda730; 1 drivers +v0x1bda5b0_0 .net "in", 3 0, L_0x1ddaf70; 1 drivers +v0x1bda720_0 .net "ors", 1 0, L_0x1dda640; 1 drivers +v0x1bda800_0 .net "out", 0 0, L_0x1ddab20; 1 drivers +L_0x1dda3a0 .part L_0x1ddaf70, 0, 1; +L_0x1dda500 .part L_0x1ddaf70, 1, 1; +L_0x1dda640 .concat8 [ 1 1 0 0], L_0x1dda330, L_0x1dda730; +L_0x1dda840 .part L_0x1ddaf70, 2, 1; +L_0x1dda9a0 .part L_0x1ddaf70, 3, 1; +L_0x1ddab90 .part L_0x1dda640, 0, 1; +L_0x1ddad40 .part L_0x1dda640, 1, 1; +S_0x1bdb110 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bd4240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1be0540_0 .net "ands", 7 0, L_0x1dd5600; 1 drivers +v0x1be0650_0 .net "in", 7 0, L_0x1dd3b40; alias, 1 drivers +v0x1be0710_0 .net "out", 0 0, L_0x1dd7600; alias, 1 drivers +v0x1be07e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bdb360 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bdb110; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bddaa0_0 .net "A", 7 0, L_0x1dd3b40; alias, 1 drivers +v0x1bddba0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bddc60_0 .net *"_s0", 0 0, L_0x1dd3ed0; 1 drivers +v0x1bddd20_0 .net *"_s12", 0 0, L_0x1dd4890; 1 drivers +v0x1bdde00_0 .net *"_s16", 0 0, L_0x1dd4bf0; 1 drivers +v0x1bddf30_0 .net *"_s20", 0 0, L_0x1dd4fc0; 1 drivers +v0x1bde010_0 .net *"_s24", 0 0, L_0x1dd52f0; 1 drivers +v0x1bde0f0_0 .net *"_s28", 0 0, L_0x1dd5280; 1 drivers +v0x1bde1d0_0 .net *"_s4", 0 0, L_0x1dd4270; 1 drivers +v0x1bde340_0 .net *"_s8", 0 0, L_0x1dd4580; 1 drivers +v0x1bde420_0 .net "out", 7 0, L_0x1dd5600; alias, 1 drivers +L_0x1dd3fe0 .part L_0x1dd3b40, 0, 1; +L_0x1dd41d0 .part v0x1d6daa0_0, 0, 1; +L_0x1dd4330 .part L_0x1dd3b40, 1, 1; +L_0x1dd4490 .part v0x1d6daa0_0, 1, 1; +L_0x1dd4640 .part L_0x1dd3b40, 2, 1; +L_0x1dd47a0 .part v0x1d6daa0_0, 2, 1; +L_0x1dd4950 .part L_0x1dd3b40, 3, 1; +L_0x1dd4ab0 .part v0x1d6daa0_0, 3, 1; +L_0x1dd4cb0 .part L_0x1dd3b40, 4, 1; +L_0x1dd4f20 .part v0x1d6daa0_0, 4, 1; +L_0x1dd5030 .part L_0x1dd3b40, 5, 1; +L_0x1dd5190 .part v0x1d6daa0_0, 5, 1; +L_0x1dd53b0 .part L_0x1dd3b40, 6, 1; +L_0x1dd5510 .part v0x1d6daa0_0, 6, 1; +LS_0x1dd5600_0_0 .concat8 [ 1 1 1 1], L_0x1dd3ed0, L_0x1dd4270, L_0x1dd4580, L_0x1dd4890; +LS_0x1dd5600_0_4 .concat8 [ 1 1 1 1], L_0x1dd4bf0, L_0x1dd4fc0, L_0x1dd52f0, L_0x1dd5280; +L_0x1dd5600 .concat8 [ 4 4 0 0], LS_0x1dd5600_0_0, LS_0x1dd5600_0_4; +L_0x1dd59c0 .part L_0x1dd3b40, 7, 1; +L_0x1dd5bb0 .part v0x1d6daa0_0, 7, 1; +S_0x1bdb5a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdb7b0 .param/l "i" 0 4 54, +C4<00>; +L_0x1dd3ed0/d .functor AND 1, L_0x1dd3fe0, L_0x1dd41d0, C4<1>, C4<1>; +L_0x1dd3ed0 .delay 1 (30000,30000,30000) L_0x1dd3ed0/d; +v0x1bdb890_0 .net *"_s0", 0 0, L_0x1dd3fe0; 1 drivers +v0x1bdb970_0 .net *"_s1", 0 0, L_0x1dd41d0; 1 drivers +S_0x1bdba50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdbc60 .param/l "i" 0 4 54, +C4<01>; +L_0x1dd4270/d .functor AND 1, L_0x1dd4330, L_0x1dd4490, C4<1>, C4<1>; +L_0x1dd4270 .delay 1 (30000,30000,30000) L_0x1dd4270/d; +v0x1bdbd20_0 .net *"_s0", 0 0, L_0x1dd4330; 1 drivers +v0x1bdbe00_0 .net *"_s1", 0 0, L_0x1dd4490; 1 drivers +S_0x1bdbee0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdc120 .param/l "i" 0 4 54, +C4<010>; +L_0x1dd4580/d .functor AND 1, L_0x1dd4640, L_0x1dd47a0, C4<1>, C4<1>; +L_0x1dd4580 .delay 1 (30000,30000,30000) L_0x1dd4580/d; +v0x1bdc1c0_0 .net *"_s0", 0 0, L_0x1dd4640; 1 drivers +v0x1bdc2a0_0 .net *"_s1", 0 0, L_0x1dd47a0; 1 drivers +S_0x1bdc380 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdc590 .param/l "i" 0 4 54, +C4<011>; +L_0x1dd4890/d .functor AND 1, L_0x1dd4950, L_0x1dd4ab0, C4<1>, C4<1>; +L_0x1dd4890 .delay 1 (30000,30000,30000) L_0x1dd4890/d; +v0x1bdc650_0 .net *"_s0", 0 0, L_0x1dd4950; 1 drivers +v0x1bdc730_0 .net *"_s1", 0 0, L_0x1dd4ab0; 1 drivers +S_0x1bdc810 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdca70 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dd4bf0/d .functor AND 1, L_0x1dd4cb0, L_0x1dd4f20, C4<1>, C4<1>; +L_0x1dd4bf0 .delay 1 (30000,30000,30000) L_0x1dd4bf0/d; +v0x1bdcb30_0 .net *"_s0", 0 0, L_0x1dd4cb0; 1 drivers +v0x1bdcc10_0 .net *"_s1", 0 0, L_0x1dd4f20; 1 drivers +S_0x1bdccf0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdcf00 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dd4fc0/d .functor AND 1, L_0x1dd5030, L_0x1dd5190, C4<1>, C4<1>; +L_0x1dd4fc0 .delay 1 (30000,30000,30000) L_0x1dd4fc0/d; +v0x1bdcfc0_0 .net *"_s0", 0 0, L_0x1dd5030; 1 drivers +v0x1bdd0a0_0 .net *"_s1", 0 0, L_0x1dd5190; 1 drivers +S_0x1bdd180 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdd390 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dd52f0/d .functor AND 1, L_0x1dd53b0, L_0x1dd5510, C4<1>, C4<1>; +L_0x1dd52f0 .delay 1 (30000,30000,30000) L_0x1dd52f0/d; +v0x1bdd450_0 .net *"_s0", 0 0, L_0x1dd53b0; 1 drivers +v0x1bdd530_0 .net *"_s1", 0 0, L_0x1dd5510; 1 drivers +S_0x1bdd610 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bdb360; + .timescale -9 -12; +P_0x1bdd820 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dd5280/d .functor AND 1, L_0x1dd59c0, L_0x1dd5bb0, C4<1>, C4<1>; +L_0x1dd5280 .delay 1 (30000,30000,30000) L_0x1dd5280/d; +v0x1bdd8e0_0 .net *"_s0", 0 0, L_0x1dd59c0; 1 drivers +v0x1bdd9c0_0 .net *"_s1", 0 0, L_0x1dd5bb0; 1 drivers +S_0x1bde580 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bdb110; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dd7600/d .functor OR 1, L_0x1dd76c0, L_0x1dd7870, C4<0>, C4<0>; +L_0x1dd7600 .delay 1 (30000,30000,30000) L_0x1dd7600/d; +v0x1be00d0_0 .net *"_s10", 0 0, L_0x1dd76c0; 1 drivers +v0x1be01b0_0 .net *"_s12", 0 0, L_0x1dd7870; 1 drivers +v0x1be0290_0 .net "in", 7 0, L_0x1dd5600; alias, 1 drivers +v0x1be0360_0 .net "ors", 1 0, L_0x1dd7420; 1 drivers +v0x1be0420_0 .net "out", 0 0, L_0x1dd7600; alias, 1 drivers +L_0x1dd67f0 .part L_0x1dd5600, 0, 4; +L_0x1dd7420 .concat8 [ 1 1 0 0], L_0x1dd64e0, L_0x1dd7110; +L_0x1dd7560 .part L_0x1dd5600, 4, 4; +L_0x1dd76c0 .part L_0x1dd7420, 0, 1; +L_0x1dd7870 .part L_0x1dd7420, 1, 1; +S_0x1bde740 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bde580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dd5ca0/d .functor OR 1, L_0x1dd5d60, L_0x1dd5ec0, C4<0>, C4<0>; +L_0x1dd5ca0 .delay 1 (30000,30000,30000) L_0x1dd5ca0/d; +L_0x1dd60f0/d .functor OR 1, L_0x1dd6200, L_0x1dd6360, C4<0>, C4<0>; +L_0x1dd60f0 .delay 1 (30000,30000,30000) L_0x1dd60f0/d; +L_0x1dd64e0/d .functor OR 1, L_0x1dd6550, L_0x1dd6700, C4<0>, C4<0>; +L_0x1dd64e0 .delay 1 (30000,30000,30000) L_0x1dd64e0/d; +v0x1bde990_0 .net *"_s0", 0 0, L_0x1dd5ca0; 1 drivers +v0x1bdea90_0 .net *"_s10", 0 0, L_0x1dd6200; 1 drivers +v0x1bdeb70_0 .net *"_s12", 0 0, L_0x1dd6360; 1 drivers +v0x1bdec30_0 .net *"_s14", 0 0, L_0x1dd6550; 1 drivers +v0x1bded10_0 .net *"_s16", 0 0, L_0x1dd6700; 1 drivers +v0x1bdee40_0 .net *"_s3", 0 0, L_0x1dd5d60; 1 drivers +v0x1bdef20_0 .net *"_s5", 0 0, L_0x1dd5ec0; 1 drivers +v0x1bdf000_0 .net *"_s6", 0 0, L_0x1dd60f0; 1 drivers +v0x1bdf0e0_0 .net "in", 3 0, L_0x1dd67f0; 1 drivers +v0x1bdf250_0 .net "ors", 1 0, L_0x1dd6000; 1 drivers +v0x1bdf330_0 .net "out", 0 0, L_0x1dd64e0; 1 drivers +L_0x1dd5d60 .part L_0x1dd67f0, 0, 1; +L_0x1dd5ec0 .part L_0x1dd67f0, 1, 1; +L_0x1dd6000 .concat8 [ 1 1 0 0], L_0x1dd5ca0, L_0x1dd60f0; +L_0x1dd6200 .part L_0x1dd67f0, 2, 1; +L_0x1dd6360 .part L_0x1dd67f0, 3, 1; +L_0x1dd6550 .part L_0x1dd6000, 0, 1; +L_0x1dd6700 .part L_0x1dd6000, 1, 1; +S_0x1bdf450 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bde580; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dd6920/d .functor OR 1, L_0x1dd6990, L_0x1dd6af0, C4<0>, C4<0>; +L_0x1dd6920 .delay 1 (30000,30000,30000) L_0x1dd6920/d; +L_0x1dd6d20/d .functor OR 1, L_0x1dd6e30, L_0x1dd6f90, C4<0>, C4<0>; +L_0x1dd6d20 .delay 1 (30000,30000,30000) L_0x1dd6d20/d; +L_0x1dd7110/d .functor OR 1, L_0x1dd7180, L_0x1dd7330, C4<0>, C4<0>; +L_0x1dd7110 .delay 1 (30000,30000,30000) L_0x1dd7110/d; +v0x1bdf610_0 .net *"_s0", 0 0, L_0x1dd6920; 1 drivers +v0x1bdf710_0 .net *"_s10", 0 0, L_0x1dd6e30; 1 drivers +v0x1bdf7f0_0 .net *"_s12", 0 0, L_0x1dd6f90; 1 drivers +v0x1bdf8b0_0 .net *"_s14", 0 0, L_0x1dd7180; 1 drivers +v0x1bdf990_0 .net *"_s16", 0 0, L_0x1dd7330; 1 drivers +v0x1bdfac0_0 .net *"_s3", 0 0, L_0x1dd6990; 1 drivers +v0x1bdfba0_0 .net *"_s5", 0 0, L_0x1dd6af0; 1 drivers +v0x1bdfc80_0 .net *"_s6", 0 0, L_0x1dd6d20; 1 drivers +v0x1bdfd60_0 .net "in", 3 0, L_0x1dd7560; 1 drivers +v0x1bdfed0_0 .net "ors", 1 0, L_0x1dd6c30; 1 drivers +v0x1bdffb0_0 .net "out", 0 0, L_0x1dd7110; 1 drivers +L_0x1dd6990 .part L_0x1dd7560, 0, 1; +L_0x1dd6af0 .part L_0x1dd7560, 1, 1; +L_0x1dd6c30 .concat8 [ 1 1 0 0], L_0x1dd6920, L_0x1dd6d20; +L_0x1dd6e30 .part L_0x1dd7560, 2, 1; +L_0x1dd6f90 .part L_0x1dd7560, 3, 1; +L_0x1dd7180 .part L_0x1dd6c30, 0, 1; +L_0x1dd7330 .part L_0x1dd6c30, 1, 1; +S_0x1be08c0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bd4240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1dd2eb0/d .functor XNOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; +L_0x1dd2eb0 .delay 1 (20000,20000,20000) L_0x1dd2eb0/d; +L_0x1dd3120/d .functor AND 1, L_0x1ddb470, L_0x1dd1da0, C4<1>, C4<1>; +L_0x1dd3120 .delay 1 (30000,30000,30000) L_0x1dd3120/d; +L_0x1dd3190/d .functor AND 1, L_0x1dd2eb0, L_0x1dd1b40, C4<1>, C4<1>; +L_0x1dd3190 .delay 1 (30000,30000,30000) L_0x1dd3190/d; +L_0x1dd32f0/d .functor OR 1, L_0x1dd3190, L_0x1dd3120, C4<0>, C4<0>; +L_0x1dd32f0 .delay 1 (30000,30000,30000) L_0x1dd32f0/d; +v0x1be0b70_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers +v0x1be0c60_0 .net "a_", 0 0, L_0x1dd1c90; alias, 1 drivers +v0x1be0d20_0 .net "b", 0 0, L_0x1ddb5d0; alias, 1 drivers +v0x1be0e10_0 .net "b_", 0 0, L_0x1dd1da0; alias, 1 drivers +v0x1be0eb0_0 .net "carryin", 0 0, L_0x1dd1b40; alias, 1 drivers +v0x1be0ff0_0 .net "eq", 0 0, L_0x1dd2eb0; 1 drivers +v0x1be10b0_0 .net "lt", 0 0, L_0x1dd3120; 1 drivers +v0x1be1170_0 .net "out", 0 0, L_0x1dd32f0; 1 drivers +v0x1be1230_0 .net "w0", 0 0, L_0x1dd3190; 1 drivers +S_0x1be1480 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bd4240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1dd2c90/d .functor OR 1, L_0x1dd2790, L_0x1be26e0, C4<0>, C4<0>; +L_0x1dd2c90 .delay 1 (30000,30000,30000) L_0x1dd2c90/d; +v0x1be2270_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers +v0x1be23c0_0 .net "b", 0 0, L_0x1dd1da0; alias, 1 drivers +v0x1be2480_0 .net "c1", 0 0, L_0x1dd2790; 1 drivers +v0x1be2520_0 .net "c2", 0 0, L_0x1be26e0; 1 drivers +v0x1be25f0_0 .net "carryin", 0 0, L_0x1dd1b40; alias, 1 drivers +v0x1be2770_0 .net "carryout", 0 0, L_0x1dd2c90; 1 drivers +v0x1be2810_0 .net "s1", 0 0, L_0x1dd26d0; 1 drivers +v0x1be28b0_0 .net "sum", 0 0, L_0x1dd28f0; 1 drivers +S_0x1be16d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1be1480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dd26d0/d .functor XOR 1, L_0x1ddb470, L_0x1dd1da0, C4<0>, C4<0>; +L_0x1dd26d0 .delay 1 (30000,30000,30000) L_0x1dd26d0/d; +L_0x1dd2790/d .functor AND 1, L_0x1ddb470, L_0x1dd1da0, C4<1>, C4<1>; +L_0x1dd2790 .delay 1 (30000,30000,30000) L_0x1dd2790/d; +v0x1be1930_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers +v0x1be19f0_0 .net "b", 0 0, L_0x1dd1da0; alias, 1 drivers +v0x1be1ab0_0 .net "carryout", 0 0, L_0x1dd2790; alias, 1 drivers +v0x1be1b50_0 .net "sum", 0 0, L_0x1dd26d0; alias, 1 drivers +S_0x1be1c80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1be1480; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dd28f0/d .functor XOR 1, L_0x1dd26d0, L_0x1dd1b40, C4<0>, C4<0>; +L_0x1dd28f0 .delay 1 (30000,30000,30000) L_0x1dd28f0/d; +L_0x1be26e0/d .functor AND 1, L_0x1dd26d0, L_0x1dd1b40, C4<1>, C4<1>; +L_0x1be26e0 .delay 1 (30000,30000,30000) L_0x1be26e0/d; +v0x1be1ee0_0 .net "a", 0 0, L_0x1dd26d0; alias, 1 drivers +v0x1be1fb0_0 .net "b", 0 0, L_0x1dd1b40; alias, 1 drivers +v0x1be2050_0 .net "carryout", 0 0, L_0x1be26e0; alias, 1 drivers +v0x1be2120_0 .net "sum", 0 0, L_0x1dd28f0; alias, 1 drivers +S_0x1be3cd0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bd3f70; + .timescale -9 -12; +L_0x7f72592dab58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592daba0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1ddb510/d .functor OR 1, L_0x7f72592dab58, L_0x7f72592daba0, C4<0>, C4<0>; +L_0x1ddb510 .delay 1 (30000,30000,30000) L_0x1ddb510/d; +v0x1be3ec0_0 .net/2u *"_s0", 0 0, L_0x7f72592dab58; 1 drivers +v0x1be3fa0_0 .net/2u *"_s2", 0 0, L_0x7f72592daba0; 1 drivers +S_0x1be4080 .scope generate, "alu_slices[11]" "alu_slices[11]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1be4290 .param/l "i" 0 3 37, +C4<01011>; +S_0x1be4350 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1be4080; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1ddb820/d .functor NOT 1, L_0x1de50a0, C4<0>, C4<0>, C4<0>; +L_0x1ddb820 .delay 1 (10000,10000,10000) L_0x1ddb820/d; +L_0x1ddb980/d .functor NOT 1, L_0x1ddb670, C4<0>, C4<0>, C4<0>; +L_0x1ddb980 .delay 1 (10000,10000,10000) L_0x1ddb980/d; +L_0x1ddc910/d .functor XOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; +L_0x1ddc910 .delay 1 (30000,30000,30000) L_0x1ddc910/d; +L_0x7f72592dabe8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dac30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1ddcfc0/d .functor OR 1, L_0x7f72592dabe8, L_0x7f72592dac30, C4<0>, C4<0>; +L_0x1ddcfc0 .delay 1 (30000,30000,30000) L_0x1ddcfc0/d; +L_0x1ddd1c0/d .functor AND 1, L_0x1de50a0, L_0x1ddb670, C4<1>, C4<1>; +L_0x1ddd1c0 .delay 1 (30000,30000,30000) L_0x1ddd1c0/d; +L_0x1ddd280/d .functor NAND 1, L_0x1de50a0, L_0x1ddb670, C4<1>, C4<1>; +L_0x1ddd280 .delay 1 (20000,20000,20000) L_0x1ddd280/d; +L_0x1ddd3e0/d .functor XOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; +L_0x1ddd3e0 .delay 1 (20000,20000,20000) L_0x1ddd3e0/d; +L_0x1ddd890/d .functor OR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; +L_0x1ddd890 .delay 1 (30000,30000,30000) L_0x1ddd890/d; +L_0x1de4fa0/d .functor NOT 1, L_0x1de1200, C4<0>, C4<0>, C4<0>; +L_0x1de4fa0 .delay 1 (10000,10000,10000) L_0x1de4fa0/d; +v0x1bf2a80_0 .net "A", 0 0, L_0x1de50a0; 1 drivers +v0x1bf2b40_0 .net "A_", 0 0, L_0x1ddb820; 1 drivers +v0x1bf2c00_0 .net "B", 0 0, L_0x1ddb670; 1 drivers +v0x1bf2cd0_0 .net "B_", 0 0, L_0x1ddb980; 1 drivers +v0x1bf2d70_0 .net *"_s12", 0 0, L_0x1ddcfc0; 1 drivers +v0x1bf2e60_0 .net/2s *"_s14", 0 0, L_0x7f72592dabe8; 1 drivers +v0x1bf2f20_0 .net/2s *"_s16", 0 0, L_0x7f72592dac30; 1 drivers +v0x1bf3000_0 .net *"_s18", 0 0, L_0x1ddd1c0; 1 drivers +v0x1bf30e0_0 .net *"_s20", 0 0, L_0x1ddd280; 1 drivers +v0x1bf3250_0 .net *"_s22", 0 0, L_0x1ddd3e0; 1 drivers +v0x1bf3330_0 .net *"_s24", 0 0, L_0x1ddd890; 1 drivers +o0x7f725936fd38 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1bf3410_0 name=_s30 +o0x7f725936fd68 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1bf34f0_0 name=_s32 +v0x1bf35d0_0 .net *"_s8", 0 0, L_0x1ddc910; 1 drivers +v0x1bf36b0_0 .net "carryin", 0 0, L_0x1de5320; 1 drivers +v0x1bf3750_0 .net "carryout", 0 0, L_0x1de4c40; 1 drivers +v0x1bf37f0_0 .net "carryouts", 7 0, L_0x1ebfce0; 1 drivers +v0x1bf39a0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bf3a40_0 .net "result", 0 0, L_0x1de1200; 1 drivers +v0x1bf3b30_0 .net "results", 7 0, L_0x1ddd660; 1 drivers +v0x1bf3c40_0 .net "zero", 0 0, L_0x1de4fa0; 1 drivers +LS_0x1ddd660_0_0 .concat8 [ 1 1 1 1], L_0x1ddbe30, L_0x1ddc460, L_0x1ddc910, L_0x1ddcfc0; +LS_0x1ddd660_0_4 .concat8 [ 1 1 1 1], L_0x1ddd1c0, L_0x1ddd280, L_0x1ddd3e0, L_0x1ddd890; +L_0x1ddd660 .concat8 [ 4 4 0 0], LS_0x1ddd660_0_0, LS_0x1ddd660_0_4; +LS_0x1ebfce0_0_0 .concat [ 1 1 1 1], L_0x1ddc0e0, L_0x1ddc7b0, o0x7f725936fd38, L_0x1ddce10; +LS_0x1ebfce0_0_4 .concat [ 4 0 0 0], o0x7f725936fd68; +L_0x1ebfce0 .concat [ 4 4 0 0], LS_0x1ebfce0_0_0, LS_0x1ebfce0_0_4; +S_0x1be45d0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1be4350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1ddc0e0/d .functor OR 1, L_0x1ddbbc0, L_0x1ddbf80, C4<0>, C4<0>; +L_0x1ddc0e0 .delay 1 (30000,30000,30000) L_0x1ddc0e0/d; +v0x1be5400_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers +v0x1be54c0_0 .net "b", 0 0, L_0x1ddb670; alias, 1 drivers +v0x1be5590_0 .net "c1", 0 0, L_0x1ddbbc0; 1 drivers +v0x1be5690_0 .net "c2", 0 0, L_0x1ddbf80; 1 drivers +v0x1be5760_0 .net "carryin", 0 0, L_0x1de5320; alias, 1 drivers +v0x1be5850_0 .net "carryout", 0 0, L_0x1ddc0e0; 1 drivers +v0x1be58f0_0 .net "s1", 0 0, L_0x1dcb930; 1 drivers +v0x1be59e0_0 .net "sum", 0 0, L_0x1ddbe30; 1 drivers +S_0x1be4840 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1be45d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dcb930/d .functor XOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; +L_0x1dcb930 .delay 1 (30000,30000,30000) L_0x1dcb930/d; +L_0x1ddbbc0/d .functor AND 1, L_0x1de50a0, L_0x1ddb670, C4<1>, C4<1>; +L_0x1ddbbc0 .delay 1 (30000,30000,30000) L_0x1ddbbc0/d; +v0x1be4aa0_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers +v0x1be4b80_0 .net "b", 0 0, L_0x1ddb670; alias, 1 drivers +v0x1be4c40_0 .net "carryout", 0 0, L_0x1ddbbc0; alias, 1 drivers +v0x1be4ce0_0 .net "sum", 0 0, L_0x1dcb930; alias, 1 drivers +S_0x1be4e20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1be45d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ddbe30/d .functor XOR 1, L_0x1dcb930, L_0x1de5320, C4<0>, C4<0>; +L_0x1ddbe30 .delay 1 (30000,30000,30000) L_0x1ddbe30/d; +L_0x1ddbf80/d .functor AND 1, L_0x1dcb930, L_0x1de5320, C4<1>, C4<1>; +L_0x1ddbf80 .delay 1 (30000,30000,30000) L_0x1ddbf80/d; +v0x1be5080_0 .net "a", 0 0, L_0x1dcb930; alias, 1 drivers +v0x1be5120_0 .net "b", 0 0, L_0x1de5320; alias, 1 drivers +v0x1be51c0_0 .net "carryout", 0 0, L_0x1ddbf80; alias, 1 drivers +v0x1be5290_0 .net "sum", 0 0, L_0x1ddbe30; alias, 1 drivers +S_0x1be5ab0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1be4350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1beaea0_0 .net "ands", 7 0, L_0x1de2c40; 1 drivers +v0x1beafb0_0 .net "in", 7 0, L_0x1ebfce0; alias, 1 drivers +v0x1beb070_0 .net "out", 0 0, L_0x1de4c40; alias, 1 drivers +v0x1beb140_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1be5cd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1be5ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1be8400_0 .net "A", 7 0, L_0x1ebfce0; alias, 1 drivers +v0x1be8500_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1be85c0_0 .net *"_s0", 0 0, L_0x1de1560; 1 drivers +v0x1be8680_0 .net *"_s12", 0 0, L_0x1de1ed0; 1 drivers +v0x1be8760_0 .net *"_s16", 0 0, L_0x1de2230; 1 drivers +v0x1be8890_0 .net *"_s20", 0 0, L_0x1de2540; 1 drivers +v0x1be8970_0 .net *"_s24", 0 0, L_0x1de2930; 1 drivers +v0x1be8a50_0 .net *"_s28", 0 0, L_0x1de28c0; 1 drivers +v0x1be8b30_0 .net *"_s4", 0 0, L_0x1de1870; 1 drivers +v0x1be8ca0_0 .net *"_s8", 0 0, L_0x1de1bc0; 1 drivers +v0x1be8d80_0 .net "out", 7 0, L_0x1de2c40; alias, 1 drivers +L_0x1de1620 .part L_0x1ebfce0, 0, 1; +L_0x1de1780 .part v0x1d6daa0_0, 0, 1; +L_0x1de1930 .part L_0x1ebfce0, 1, 1; +L_0x1de1b20 .part v0x1d6daa0_0, 1, 1; +L_0x1de1c80 .part L_0x1ebfce0, 2, 1; +L_0x1de1de0 .part v0x1d6daa0_0, 2, 1; +L_0x1de1f90 .part L_0x1ebfce0, 3, 1; +L_0x1de20f0 .part v0x1d6daa0_0, 3, 1; +L_0x1de22f0 .part L_0x1ebfce0, 4, 1; +L_0x1de2450 .part v0x1d6daa0_0, 4, 1; +L_0x1de25b0 .part L_0x1ebfce0, 5, 1; +L_0x1de2820 .part v0x1d6daa0_0, 5, 1; +L_0x1de29f0 .part L_0x1ebfce0, 6, 1; +L_0x1de2b50 .part v0x1d6daa0_0, 6, 1; +LS_0x1de2c40_0_0 .concat8 [ 1 1 1 1], L_0x1de1560, L_0x1de1870, L_0x1de1bc0, L_0x1de1ed0; +LS_0x1de2c40_0_4 .concat8 [ 1 1 1 1], L_0x1de2230, L_0x1de2540, L_0x1de2930, L_0x1de28c0; +L_0x1de2c40 .concat8 [ 4 4 0 0], LS_0x1de2c40_0_0, LS_0x1de2c40_0_4; +L_0x1de3000 .part L_0x1ebfce0, 7, 1; +L_0x1de31f0 .part v0x1d6daa0_0, 7, 1; +S_0x1be5f30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be6140 .param/l "i" 0 4 54, +C4<00>; +L_0x1de1560/d .functor AND 1, L_0x1de1620, L_0x1de1780, C4<1>, C4<1>; +L_0x1de1560 .delay 1 (30000,30000,30000) L_0x1de1560/d; +v0x1be6220_0 .net *"_s0", 0 0, L_0x1de1620; 1 drivers +v0x1be6300_0 .net *"_s1", 0 0, L_0x1de1780; 1 drivers +S_0x1be63e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be65f0 .param/l "i" 0 4 54, +C4<01>; +L_0x1de1870/d .functor AND 1, L_0x1de1930, L_0x1de1b20, C4<1>, C4<1>; +L_0x1de1870 .delay 1 (30000,30000,30000) L_0x1de1870/d; +v0x1be66b0_0 .net *"_s0", 0 0, L_0x1de1930; 1 drivers +v0x1be6790_0 .net *"_s1", 0 0, L_0x1de1b20; 1 drivers +S_0x1be6870 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be6a80 .param/l "i" 0 4 54, +C4<010>; +L_0x1de1bc0/d .functor AND 1, L_0x1de1c80, L_0x1de1de0, C4<1>, C4<1>; +L_0x1de1bc0 .delay 1 (30000,30000,30000) L_0x1de1bc0/d; +v0x1be6b20_0 .net *"_s0", 0 0, L_0x1de1c80; 1 drivers +v0x1be6c00_0 .net *"_s1", 0 0, L_0x1de1de0; 1 drivers +S_0x1be6ce0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be6ef0 .param/l "i" 0 4 54, +C4<011>; +L_0x1de1ed0/d .functor AND 1, L_0x1de1f90, L_0x1de20f0, C4<1>, C4<1>; +L_0x1de1ed0 .delay 1 (30000,30000,30000) L_0x1de1ed0/d; +v0x1be6fb0_0 .net *"_s0", 0 0, L_0x1de1f90; 1 drivers +v0x1be7090_0 .net *"_s1", 0 0, L_0x1de20f0; 1 drivers +S_0x1be7170 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be73d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1de2230/d .functor AND 1, L_0x1de22f0, L_0x1de2450, C4<1>, C4<1>; +L_0x1de2230 .delay 1 (30000,30000,30000) L_0x1de2230/d; +v0x1be7490_0 .net *"_s0", 0 0, L_0x1de22f0; 1 drivers +v0x1be7570_0 .net *"_s1", 0 0, L_0x1de2450; 1 drivers +S_0x1be7650 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be7860 .param/l "i" 0 4 54, +C4<0101>; +L_0x1de2540/d .functor AND 1, L_0x1de25b0, L_0x1de2820, C4<1>, C4<1>; +L_0x1de2540 .delay 1 (30000,30000,30000) L_0x1de2540/d; +v0x1be7920_0 .net *"_s0", 0 0, L_0x1de25b0; 1 drivers +v0x1be7a00_0 .net *"_s1", 0 0, L_0x1de2820; 1 drivers +S_0x1be7ae0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be7cf0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1de2930/d .functor AND 1, L_0x1de29f0, L_0x1de2b50, C4<1>, C4<1>; +L_0x1de2930 .delay 1 (30000,30000,30000) L_0x1de2930/d; +v0x1be7db0_0 .net *"_s0", 0 0, L_0x1de29f0; 1 drivers +v0x1be7e90_0 .net *"_s1", 0 0, L_0x1de2b50; 1 drivers +S_0x1be7f70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1be5cd0; + .timescale -9 -12; +P_0x1be8180 .param/l "i" 0 4 54, +C4<0111>; +L_0x1de28c0/d .functor AND 1, L_0x1de3000, L_0x1de31f0, C4<1>, C4<1>; +L_0x1de28c0 .delay 1 (30000,30000,30000) L_0x1de28c0/d; +v0x1be8240_0 .net *"_s0", 0 0, L_0x1de3000; 1 drivers +v0x1be8320_0 .net *"_s1", 0 0, L_0x1de31f0; 1 drivers +S_0x1be8ee0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1be5ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1de4c40/d .functor OR 1, L_0x1de4d00, L_0x1de4eb0, C4<0>, C4<0>; +L_0x1de4c40 .delay 1 (30000,30000,30000) L_0x1de4c40/d; +v0x1beaa30_0 .net *"_s10", 0 0, L_0x1de4d00; 1 drivers +v0x1beab10_0 .net *"_s12", 0 0, L_0x1de4eb0; 1 drivers +v0x1beabf0_0 .net "in", 7 0, L_0x1de2c40; alias, 1 drivers +v0x1beacc0_0 .net "ors", 1 0, L_0x1de4a60; 1 drivers +v0x1bead80_0 .net "out", 0 0, L_0x1de4c40; alias, 1 drivers +L_0x1de3e30 .part L_0x1de2c40, 0, 4; +L_0x1de4a60 .concat8 [ 1 1 0 0], L_0x1de3b20, L_0x1de4750; +L_0x1de4ba0 .part L_0x1de2c40, 4, 4; +L_0x1de4d00 .part L_0x1de4a60, 0, 1; +L_0x1de4eb0 .part L_0x1de4a60, 1, 1; +S_0x1be90a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1be8ee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1de32e0/d .functor OR 1, L_0x1de33a0, L_0x1de3500, C4<0>, C4<0>; +L_0x1de32e0 .delay 1 (30000,30000,30000) L_0x1de32e0/d; +L_0x1de3730/d .functor OR 1, L_0x1de3840, L_0x1de39a0, C4<0>, C4<0>; +L_0x1de3730 .delay 1 (30000,30000,30000) L_0x1de3730/d; +L_0x1de3b20/d .functor OR 1, L_0x1de3b90, L_0x1de3d40, C4<0>, C4<0>; +L_0x1de3b20 .delay 1 (30000,30000,30000) L_0x1de3b20/d; +v0x1be92f0_0 .net *"_s0", 0 0, L_0x1de32e0; 1 drivers +v0x1be93f0_0 .net *"_s10", 0 0, L_0x1de3840; 1 drivers +v0x1be94d0_0 .net *"_s12", 0 0, L_0x1de39a0; 1 drivers +v0x1be9590_0 .net *"_s14", 0 0, L_0x1de3b90; 1 drivers +v0x1be9670_0 .net *"_s16", 0 0, L_0x1de3d40; 1 drivers +v0x1be97a0_0 .net *"_s3", 0 0, L_0x1de33a0; 1 drivers +v0x1be9880_0 .net *"_s5", 0 0, L_0x1de3500; 1 drivers +v0x1be9960_0 .net *"_s6", 0 0, L_0x1de3730; 1 drivers +v0x1be9a40_0 .net "in", 3 0, L_0x1de3e30; 1 drivers +v0x1be9bb0_0 .net "ors", 1 0, L_0x1de3640; 1 drivers +v0x1be9c90_0 .net "out", 0 0, L_0x1de3b20; 1 drivers +L_0x1de33a0 .part L_0x1de3e30, 0, 1; +L_0x1de3500 .part L_0x1de3e30, 1, 1; +L_0x1de3640 .concat8 [ 1 1 0 0], L_0x1de32e0, L_0x1de3730; +L_0x1de3840 .part L_0x1de3e30, 2, 1; +L_0x1de39a0 .part L_0x1de3e30, 3, 1; +L_0x1de3b90 .part L_0x1de3640, 0, 1; +L_0x1de3d40 .part L_0x1de3640, 1, 1; +S_0x1be9db0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1be8ee0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1de3f60/d .functor OR 1, L_0x1de3fd0, L_0x1de4130, C4<0>, C4<0>; +L_0x1de3f60 .delay 1 (30000,30000,30000) L_0x1de3f60/d; +L_0x1de4360/d .functor OR 1, L_0x1de4470, L_0x1de45d0, C4<0>, C4<0>; +L_0x1de4360 .delay 1 (30000,30000,30000) L_0x1de4360/d; +L_0x1de4750/d .functor OR 1, L_0x1de47c0, L_0x1de4970, C4<0>, C4<0>; +L_0x1de4750 .delay 1 (30000,30000,30000) L_0x1de4750/d; +v0x1be9f70_0 .net *"_s0", 0 0, L_0x1de3f60; 1 drivers +v0x1bea070_0 .net *"_s10", 0 0, L_0x1de4470; 1 drivers +v0x1bea150_0 .net *"_s12", 0 0, L_0x1de45d0; 1 drivers +v0x1bea210_0 .net *"_s14", 0 0, L_0x1de47c0; 1 drivers +v0x1bea2f0_0 .net *"_s16", 0 0, L_0x1de4970; 1 drivers +v0x1bea420_0 .net *"_s3", 0 0, L_0x1de3fd0; 1 drivers +v0x1bea500_0 .net *"_s5", 0 0, L_0x1de4130; 1 drivers +v0x1bea5e0_0 .net *"_s6", 0 0, L_0x1de4360; 1 drivers +v0x1bea6c0_0 .net "in", 3 0, L_0x1de4ba0; 1 drivers +v0x1bea830_0 .net "ors", 1 0, L_0x1de4270; 1 drivers +v0x1bea910_0 .net "out", 0 0, L_0x1de4750; 1 drivers +L_0x1de3fd0 .part L_0x1de4ba0, 0, 1; +L_0x1de4130 .part L_0x1de4ba0, 1, 1; +L_0x1de4270 .concat8 [ 1 1 0 0], L_0x1de3f60, L_0x1de4360; +L_0x1de4470 .part L_0x1de4ba0, 2, 1; +L_0x1de45d0 .part L_0x1de4ba0, 3, 1; +L_0x1de47c0 .part L_0x1de4270, 0, 1; +L_0x1de4970 .part L_0x1de4270, 1, 1; +S_0x1beb220 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1be4350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bf0650_0 .net "ands", 7 0, L_0x1ddf200; 1 drivers +v0x1bf0760_0 .net "in", 7 0, L_0x1ddd660; alias, 1 drivers +v0x1bf0820_0 .net "out", 0 0, L_0x1de1200; alias, 1 drivers +v0x1bf08f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1beb470 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1beb220; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bedbb0_0 .net "A", 7 0, L_0x1ddd660; alias, 1 drivers +v0x1bedcb0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bedd70_0 .net *"_s0", 0 0, L_0x1ddd9f0; 1 drivers +v0x1bede30_0 .net *"_s12", 0 0, L_0x1dde3b0; 1 drivers +v0x1bedf10_0 .net *"_s16", 0 0, L_0x1dde710; 1 drivers +v0x1bee040_0 .net *"_s20", 0 0, L_0x1ddeb40; 1 drivers +v0x1bee120_0 .net *"_s24", 0 0, L_0x1ddee70; 1 drivers +v0x1bee200_0 .net *"_s28", 0 0, L_0x1ddee00; 1 drivers +v0x1bee2e0_0 .net *"_s4", 0 0, L_0x1dddd90; 1 drivers +v0x1bee450_0 .net *"_s8", 0 0, L_0x1dde0a0; 1 drivers +v0x1bee530_0 .net "out", 7 0, L_0x1ddf200; alias, 1 drivers +L_0x1dddb00 .part L_0x1ddd660, 0, 1; +L_0x1dddcf0 .part v0x1d6daa0_0, 0, 1; +L_0x1ddde50 .part L_0x1ddd660, 1, 1; +L_0x1dddfb0 .part v0x1d6daa0_0, 1, 1; +L_0x1dde160 .part L_0x1ddd660, 2, 1; +L_0x1dde2c0 .part v0x1d6daa0_0, 2, 1; +L_0x1dde470 .part L_0x1ddd660, 3, 1; +L_0x1dde5d0 .part v0x1d6daa0_0, 3, 1; +L_0x1dde7d0 .part L_0x1ddd660, 4, 1; +L_0x1ddea40 .part v0x1d6daa0_0, 4, 1; +L_0x1ddebb0 .part L_0x1ddd660, 5, 1; +L_0x1dded10 .part v0x1d6daa0_0, 5, 1; +L_0x1ddef30 .part L_0x1ddd660, 6, 1; +L_0x1ddf090 .part v0x1d6daa0_0, 6, 1; +LS_0x1ddf200_0_0 .concat8 [ 1 1 1 1], L_0x1ddd9f0, L_0x1dddd90, L_0x1dde0a0, L_0x1dde3b0; +LS_0x1ddf200_0_4 .concat8 [ 1 1 1 1], L_0x1dde710, L_0x1ddeb40, L_0x1ddee70, L_0x1ddee00; +L_0x1ddf200 .concat8 [ 4 4 0 0], LS_0x1ddf200_0_0, LS_0x1ddf200_0_4; +L_0x1ddf5c0 .part L_0x1ddd660, 7, 1; +L_0x1ddf7b0 .part v0x1d6daa0_0, 7, 1; +S_0x1beb6b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1beb8c0 .param/l "i" 0 4 54, +C4<00>; +L_0x1ddd9f0/d .functor AND 1, L_0x1dddb00, L_0x1dddcf0, C4<1>, C4<1>; +L_0x1ddd9f0 .delay 1 (30000,30000,30000) L_0x1ddd9f0/d; +v0x1beb9a0_0 .net *"_s0", 0 0, L_0x1dddb00; 1 drivers +v0x1beba80_0 .net *"_s1", 0 0, L_0x1dddcf0; 1 drivers +S_0x1bebb60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1bebd70 .param/l "i" 0 4 54, +C4<01>; +L_0x1dddd90/d .functor AND 1, L_0x1ddde50, L_0x1dddfb0, C4<1>, C4<1>; +L_0x1dddd90 .delay 1 (30000,30000,30000) L_0x1dddd90/d; +v0x1bebe30_0 .net *"_s0", 0 0, L_0x1ddde50; 1 drivers +v0x1bebf10_0 .net *"_s1", 0 0, L_0x1dddfb0; 1 drivers +S_0x1bebff0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1bec230 .param/l "i" 0 4 54, +C4<010>; +L_0x1dde0a0/d .functor AND 1, L_0x1dde160, L_0x1dde2c0, C4<1>, C4<1>; +L_0x1dde0a0 .delay 1 (30000,30000,30000) L_0x1dde0a0/d; +v0x1bec2d0_0 .net *"_s0", 0 0, L_0x1dde160; 1 drivers +v0x1bec3b0_0 .net *"_s1", 0 0, L_0x1dde2c0; 1 drivers +S_0x1bec490 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1bec6a0 .param/l "i" 0 4 54, +C4<011>; +L_0x1dde3b0/d .functor AND 1, L_0x1dde470, L_0x1dde5d0, C4<1>, C4<1>; +L_0x1dde3b0 .delay 1 (30000,30000,30000) L_0x1dde3b0/d; +v0x1bec760_0 .net *"_s0", 0 0, L_0x1dde470; 1 drivers +v0x1bec840_0 .net *"_s1", 0 0, L_0x1dde5d0; 1 drivers +S_0x1bec920 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1becb80 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dde710/d .functor AND 1, L_0x1dde7d0, L_0x1ddea40, C4<1>, C4<1>; +L_0x1dde710 .delay 1 (30000,30000,30000) L_0x1dde710/d; +v0x1becc40_0 .net *"_s0", 0 0, L_0x1dde7d0; 1 drivers +v0x1becd20_0 .net *"_s1", 0 0, L_0x1ddea40; 1 drivers +S_0x1bece00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1bed010 .param/l "i" 0 4 54, +C4<0101>; +L_0x1ddeb40/d .functor AND 1, L_0x1ddebb0, L_0x1dded10, C4<1>, C4<1>; +L_0x1ddeb40 .delay 1 (30000,30000,30000) L_0x1ddeb40/d; +v0x1bed0d0_0 .net *"_s0", 0 0, L_0x1ddebb0; 1 drivers +v0x1bed1b0_0 .net *"_s1", 0 0, L_0x1dded10; 1 drivers +S_0x1bed290 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1bed4a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1ddee70/d .functor AND 1, L_0x1ddef30, L_0x1ddf090, C4<1>, C4<1>; +L_0x1ddee70 .delay 1 (30000,30000,30000) L_0x1ddee70/d; +v0x1bed560_0 .net *"_s0", 0 0, L_0x1ddef30; 1 drivers +v0x1bed640_0 .net *"_s1", 0 0, L_0x1ddf090; 1 drivers +S_0x1bed720 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1beb470; + .timescale -9 -12; +P_0x1bed930 .param/l "i" 0 4 54, +C4<0111>; +L_0x1ddee00/d .functor AND 1, L_0x1ddf5c0, L_0x1ddf7b0, C4<1>, C4<1>; +L_0x1ddee00 .delay 1 (30000,30000,30000) L_0x1ddee00/d; +v0x1bed9f0_0 .net *"_s0", 0 0, L_0x1ddf5c0; 1 drivers +v0x1bedad0_0 .net *"_s1", 0 0, L_0x1ddf7b0; 1 drivers +S_0x1bee690 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1beb220; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1de1200/d .functor OR 1, L_0x1de12c0, L_0x1de1470, C4<0>, C4<0>; +L_0x1de1200 .delay 1 (30000,30000,30000) L_0x1de1200/d; +v0x1bf01e0_0 .net *"_s10", 0 0, L_0x1de12c0; 1 drivers +v0x1bf02c0_0 .net *"_s12", 0 0, L_0x1de1470; 1 drivers +v0x1bf03a0_0 .net "in", 7 0, L_0x1ddf200; alias, 1 drivers +v0x1bf0470_0 .net "ors", 1 0, L_0x1de1020; 1 drivers +v0x1bf0530_0 .net "out", 0 0, L_0x1de1200; alias, 1 drivers +L_0x1de03f0 .part L_0x1ddf200, 0, 4; +L_0x1de1020 .concat8 [ 1 1 0 0], L_0x1de00e0, L_0x1de0d10; +L_0x1de1160 .part L_0x1ddf200, 4, 4; +L_0x1de12c0 .part L_0x1de1020, 0, 1; +L_0x1de1470 .part L_0x1de1020, 1, 1; +S_0x1bee850 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bee690; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1ddf8a0/d .functor OR 1, L_0x1ddf960, L_0x1ddfac0, C4<0>, C4<0>; +L_0x1ddf8a0 .delay 1 (30000,30000,30000) L_0x1ddf8a0/d; +L_0x1ddfcf0/d .functor OR 1, L_0x1ddfe00, L_0x1ddff60, C4<0>, C4<0>; +L_0x1ddfcf0 .delay 1 (30000,30000,30000) L_0x1ddfcf0/d; +L_0x1de00e0/d .functor OR 1, L_0x1de0150, L_0x1de0300, C4<0>, C4<0>; +L_0x1de00e0 .delay 1 (30000,30000,30000) L_0x1de00e0/d; +v0x1beeaa0_0 .net *"_s0", 0 0, L_0x1ddf8a0; 1 drivers +v0x1beeba0_0 .net *"_s10", 0 0, L_0x1ddfe00; 1 drivers +v0x1beec80_0 .net *"_s12", 0 0, L_0x1ddff60; 1 drivers +v0x1beed40_0 .net *"_s14", 0 0, L_0x1de0150; 1 drivers +v0x1beee20_0 .net *"_s16", 0 0, L_0x1de0300; 1 drivers +v0x1beef50_0 .net *"_s3", 0 0, L_0x1ddf960; 1 drivers +v0x1bef030_0 .net *"_s5", 0 0, L_0x1ddfac0; 1 drivers +v0x1bef110_0 .net *"_s6", 0 0, L_0x1ddfcf0; 1 drivers +v0x1bef1f0_0 .net "in", 3 0, L_0x1de03f0; 1 drivers +v0x1bef360_0 .net "ors", 1 0, L_0x1ddfc00; 1 drivers +v0x1bef440_0 .net "out", 0 0, L_0x1de00e0; 1 drivers +L_0x1ddf960 .part L_0x1de03f0, 0, 1; +L_0x1ddfac0 .part L_0x1de03f0, 1, 1; +L_0x1ddfc00 .concat8 [ 1 1 0 0], L_0x1ddf8a0, L_0x1ddfcf0; +L_0x1ddfe00 .part L_0x1de03f0, 2, 1; +L_0x1ddff60 .part L_0x1de03f0, 3, 1; +L_0x1de0150 .part L_0x1ddfc00, 0, 1; +L_0x1de0300 .part L_0x1ddfc00, 1, 1; +S_0x1bef560 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bee690; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1de0520/d .functor OR 1, L_0x1de0590, L_0x1de06f0, C4<0>, C4<0>; +L_0x1de0520 .delay 1 (30000,30000,30000) L_0x1de0520/d; +L_0x1de0920/d .functor OR 1, L_0x1de0a30, L_0x1de0b90, C4<0>, C4<0>; +L_0x1de0920 .delay 1 (30000,30000,30000) L_0x1de0920/d; +L_0x1de0d10/d .functor OR 1, L_0x1de0d80, L_0x1de0f30, C4<0>, C4<0>; +L_0x1de0d10 .delay 1 (30000,30000,30000) L_0x1de0d10/d; +v0x1bef720_0 .net *"_s0", 0 0, L_0x1de0520; 1 drivers +v0x1bef820_0 .net *"_s10", 0 0, L_0x1de0a30; 1 drivers +v0x1bef900_0 .net *"_s12", 0 0, L_0x1de0b90; 1 drivers +v0x1bef9c0_0 .net *"_s14", 0 0, L_0x1de0d80; 1 drivers +v0x1befaa0_0 .net *"_s16", 0 0, L_0x1de0f30; 1 drivers +v0x1befbd0_0 .net *"_s3", 0 0, L_0x1de0590; 1 drivers +v0x1befcb0_0 .net *"_s5", 0 0, L_0x1de06f0; 1 drivers +v0x1befd90_0 .net *"_s6", 0 0, L_0x1de0920; 1 drivers +v0x1befe70_0 .net "in", 3 0, L_0x1de1160; 1 drivers +v0x1beffe0_0 .net "ors", 1 0, L_0x1de0830; 1 drivers +v0x1bf00c0_0 .net "out", 0 0, L_0x1de0d10; 1 drivers +L_0x1de0590 .part L_0x1de1160, 0, 1; +L_0x1de06f0 .part L_0x1de1160, 1, 1; +L_0x1de0830 .concat8 [ 1 1 0 0], L_0x1de0520, L_0x1de0920; +L_0x1de0a30 .part L_0x1de1160, 2, 1; +L_0x1de0b90 .part L_0x1de1160, 3, 1; +L_0x1de0d80 .part L_0x1de0830, 0, 1; +L_0x1de0f30 .part L_0x1de0830, 1, 1; +S_0x1bf09d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1be4350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1ddc9d0/d .functor XNOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; +L_0x1ddc9d0 .delay 1 (20000,20000,20000) L_0x1ddc9d0/d; +L_0x1ddcc40/d .functor AND 1, L_0x1de50a0, L_0x1ddb980, C4<1>, C4<1>; +L_0x1ddcc40 .delay 1 (30000,30000,30000) L_0x1ddcc40/d; +L_0x1ddccb0/d .functor AND 1, L_0x1ddc9d0, L_0x1de5320, C4<1>, C4<1>; +L_0x1ddccb0 .delay 1 (30000,30000,30000) L_0x1ddccb0/d; +L_0x1ddce10/d .functor OR 1, L_0x1ddccb0, L_0x1ddcc40, C4<0>, C4<0>; +L_0x1ddce10 .delay 1 (30000,30000,30000) L_0x1ddce10/d; +v0x1bf0c80_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers +v0x1bf0d70_0 .net "a_", 0 0, L_0x1ddb820; alias, 1 drivers +v0x1bf0e30_0 .net "b", 0 0, L_0x1ddb670; alias, 1 drivers +v0x1bf0f20_0 .net "b_", 0 0, L_0x1ddb980; alias, 1 drivers +v0x1bf0fc0_0 .net "carryin", 0 0, L_0x1de5320; alias, 1 drivers +v0x1bf1100_0 .net "eq", 0 0, L_0x1ddc9d0; 1 drivers +v0x1bf11c0_0 .net "lt", 0 0, L_0x1ddcc40; 1 drivers +v0x1bf1280_0 .net "out", 0 0, L_0x1ddce10; 1 drivers +v0x1bf1340_0 .net "w0", 0 0, L_0x1ddccb0; 1 drivers +S_0x1bf1590 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1be4350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1ddc7b0/d .functor OR 1, L_0x1ddc300, L_0x1bf27f0, C4<0>, C4<0>; +L_0x1ddc7b0 .delay 1 (30000,30000,30000) L_0x1ddc7b0/d; +v0x1bf2380_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers +v0x1bf24d0_0 .net "b", 0 0, L_0x1ddb980; alias, 1 drivers +v0x1bf2590_0 .net "c1", 0 0, L_0x1ddc300; 1 drivers +v0x1bf2630_0 .net "c2", 0 0, L_0x1bf27f0; 1 drivers +v0x1bf2700_0 .net "carryin", 0 0, L_0x1de5320; alias, 1 drivers +v0x1bf2880_0 .net "carryout", 0 0, L_0x1ddc7b0; 1 drivers +v0x1bf2920_0 .net "s1", 0 0, L_0x1ddc240; 1 drivers +v0x1bf29c0_0 .net "sum", 0 0, L_0x1ddc460; 1 drivers +S_0x1bf17e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bf1590; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ddc240/d .functor XOR 1, L_0x1de50a0, L_0x1ddb980, C4<0>, C4<0>; +L_0x1ddc240 .delay 1 (30000,30000,30000) L_0x1ddc240/d; +L_0x1ddc300/d .functor AND 1, L_0x1de50a0, L_0x1ddb980, C4<1>, C4<1>; +L_0x1ddc300 .delay 1 (30000,30000,30000) L_0x1ddc300/d; +v0x1bf1a40_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers +v0x1bf1b00_0 .net "b", 0 0, L_0x1ddb980; alias, 1 drivers +v0x1bf1bc0_0 .net "carryout", 0 0, L_0x1ddc300; alias, 1 drivers +v0x1bf1c60_0 .net "sum", 0 0, L_0x1ddc240; alias, 1 drivers +S_0x1bf1d90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bf1590; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ddc460/d .functor XOR 1, L_0x1ddc240, L_0x1de5320, C4<0>, C4<0>; +L_0x1ddc460 .delay 1 (30000,30000,30000) L_0x1ddc460/d; +L_0x1bf27f0/d .functor AND 1, L_0x1ddc240, L_0x1de5320, C4<1>, C4<1>; +L_0x1bf27f0 .delay 1 (30000,30000,30000) L_0x1bf27f0/d; +v0x1bf1ff0_0 .net "a", 0 0, L_0x1ddc240; alias, 1 drivers +v0x1bf20c0_0 .net "b", 0 0, L_0x1de5320; alias, 1 drivers +v0x1bf2160_0 .net "carryout", 0 0, L_0x1bf27f0; alias, 1 drivers +v0x1bf2230_0 .net "sum", 0 0, L_0x1ddc460; alias, 1 drivers +S_0x1bf3de0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1be4080; + .timescale -9 -12; +L_0x7f72592dac78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dacc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1de5140/d .functor OR 1, L_0x7f72592dac78, L_0x7f72592dacc0, C4<0>, C4<0>; +L_0x1de5140 .delay 1 (30000,30000,30000) L_0x1de5140/d; +v0x1bf3fd0_0 .net/2u *"_s0", 0 0, L_0x7f72592dac78; 1 drivers +v0x1bf40b0_0 .net/2u *"_s2", 0 0, L_0x7f72592dacc0; 1 drivers +S_0x1bf4190 .scope generate, "alu_slices[12]" "alu_slices[12]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1bf43a0 .param/l "i" 0 3 37, +C4<01100>; +S_0x1bf4460 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bf4190; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1de52a0/d .functor NOT 1, L_0x1deecb0, C4<0>, C4<0>, C4<0>; +L_0x1de52a0 .delay 1 (10000,10000,10000) L_0x1de52a0/d; +L_0x1de55e0/d .functor NOT 1, L_0x1deee10, C4<0>, C4<0>, C4<0>; +L_0x1de55e0 .delay 1 (10000,10000,10000) L_0x1de55e0/d; +L_0x1de6520/d .functor XOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; +L_0x1de6520 .delay 1 (30000,30000,30000) L_0x1de6520/d; +L_0x7f72592dad08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dad50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1de6bd0/d .functor OR 1, L_0x7f72592dad08, L_0x7f72592dad50, C4<0>, C4<0>; +L_0x1de6bd0 .delay 1 (30000,30000,30000) L_0x1de6bd0/d; +L_0x1de6dd0/d .functor AND 1, L_0x1deecb0, L_0x1deee10, C4<1>, C4<1>; +L_0x1de6dd0 .delay 1 (30000,30000,30000) L_0x1de6dd0/d; +L_0x1de6e90/d .functor NAND 1, L_0x1deecb0, L_0x1deee10, C4<1>, C4<1>; +L_0x1de6e90 .delay 1 (20000,20000,20000) L_0x1de6e90/d; +L_0x1de6ff0/d .functor XOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; +L_0x1de6ff0 .delay 1 (20000,20000,20000) L_0x1de6ff0/d; +L_0x1de74a0/d .functor OR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; +L_0x1de74a0 .delay 1 (30000,30000,30000) L_0x1de74a0/d; +L_0x1deebb0/d .functor NOT 1, L_0x1deae10, C4<0>, C4<0>, C4<0>; +L_0x1deebb0 .delay 1 (10000,10000,10000) L_0x1deebb0/d; +v0x1c02b90_0 .net "A", 0 0, L_0x1deecb0; 1 drivers +v0x1c02c50_0 .net "A_", 0 0, L_0x1de52a0; 1 drivers +v0x1c02d10_0 .net "B", 0 0, L_0x1deee10; 1 drivers +v0x1c02de0_0 .net "B_", 0 0, L_0x1de55e0; 1 drivers +v0x1c02e80_0 .net *"_s12", 0 0, L_0x1de6bd0; 1 drivers +v0x1c02f70_0 .net/2s *"_s14", 0 0, L_0x7f72592dad08; 1 drivers +v0x1c03030_0 .net/2s *"_s16", 0 0, L_0x7f72592dad50; 1 drivers +v0x1c03110_0 .net *"_s18", 0 0, L_0x1de6dd0; 1 drivers +v0x1c031f0_0 .net *"_s20", 0 0, L_0x1de6e90; 1 drivers +v0x1c03360_0 .net *"_s22", 0 0, L_0x1de6ff0; 1 drivers +v0x1c03440_0 .net *"_s24", 0 0, L_0x1de74a0; 1 drivers +o0x7f7259372288 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c03520_0 name=_s30 +o0x7f72593722b8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c03600_0 name=_s32 +v0x1c036e0_0 .net *"_s8", 0 0, L_0x1de6520; 1 drivers +v0x1c037c0_0 .net "carryin", 0 0, L_0x1de53c0; 1 drivers +v0x1c03860_0 .net "carryout", 0 0, L_0x1dee850; 1 drivers +v0x1c03900_0 .net "carryouts", 7 0, L_0x1ebfeb0; 1 drivers +v0x1c03ab0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1b9d5d0_0 .net "result", 0 0, L_0x1deae10; 1 drivers +v0x1b9d6c0_0 .net "results", 7 0, L_0x1de7270; 1 drivers +v0x1b9d7d0_0 .net "zero", 0 0, L_0x1deebb0; 1 drivers +LS_0x1de7270_0_0 .concat8 [ 1 1 1 1], L_0x1de5a40, L_0x1de6070, L_0x1de6520, L_0x1de6bd0; +LS_0x1de7270_0_4 .concat8 [ 1 1 1 1], L_0x1de6dd0, L_0x1de6e90, L_0x1de6ff0, L_0x1de74a0; +L_0x1de7270 .concat8 [ 4 4 0 0], LS_0x1de7270_0_0, LS_0x1de7270_0_4; +LS_0x1ebfeb0_0_0 .concat [ 1 1 1 1], L_0x1de5cf0, L_0x1de63c0, o0x7f7259372288, L_0x1de6a20; +LS_0x1ebfeb0_0_4 .concat [ 4 0 0 0], o0x7f72593722b8; +L_0x1ebfeb0 .concat [ 4 4 0 0], LS_0x1ebfeb0_0_0, LS_0x1ebfeb0_0_4; +S_0x1bf46e0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bf4460; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1de5cf0/d .functor OR 1, L_0x1de57d0, L_0x1de5b90, C4<0>, C4<0>; +L_0x1de5cf0 .delay 1 (30000,30000,30000) L_0x1de5cf0/d; +v0x1bf5510_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers +v0x1bf55d0_0 .net "b", 0 0, L_0x1deee10; alias, 1 drivers +v0x1bf56a0_0 .net "c1", 0 0, L_0x1de57d0; 1 drivers +v0x1bf57a0_0 .net "c2", 0 0, L_0x1de5b90; 1 drivers +v0x1bf5870_0 .net "carryin", 0 0, L_0x1de53c0; alias, 1 drivers +v0x1bf5960_0 .net "carryout", 0 0, L_0x1de5cf0; 1 drivers +v0x1bf5a00_0 .net "s1", 0 0, L_0x1ddf180; 1 drivers +v0x1bf5af0_0 .net "sum", 0 0, L_0x1de5a40; 1 drivers +S_0x1bf4950 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bf46e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ddf180/d .functor XOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; +L_0x1ddf180 .delay 1 (30000,30000,30000) L_0x1ddf180/d; +L_0x1de57d0/d .functor AND 1, L_0x1deecb0, L_0x1deee10, C4<1>, C4<1>; +L_0x1de57d0 .delay 1 (30000,30000,30000) L_0x1de57d0/d; +v0x1bf4bb0_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers +v0x1bf4c90_0 .net "b", 0 0, L_0x1deee10; alias, 1 drivers +v0x1bf4d50_0 .net "carryout", 0 0, L_0x1de57d0; alias, 1 drivers +v0x1bf4df0_0 .net "sum", 0 0, L_0x1ddf180; alias, 1 drivers +S_0x1bf4f30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bf46e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1de5a40/d .functor XOR 1, L_0x1ddf180, L_0x1de53c0, C4<0>, C4<0>; +L_0x1de5a40 .delay 1 (30000,30000,30000) L_0x1de5a40/d; +L_0x1de5b90/d .functor AND 1, L_0x1ddf180, L_0x1de53c0, C4<1>, C4<1>; +L_0x1de5b90 .delay 1 (30000,30000,30000) L_0x1de5b90/d; +v0x1bf5190_0 .net "a", 0 0, L_0x1ddf180; alias, 1 drivers +v0x1bf5230_0 .net "b", 0 0, L_0x1de53c0; alias, 1 drivers +v0x1bf52d0_0 .net "carryout", 0 0, L_0x1de5b90; alias, 1 drivers +v0x1bf53a0_0 .net "sum", 0 0, L_0x1de5a40; alias, 1 drivers +S_0x1bf5bc0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bf4460; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1bfafb0_0 .net "ands", 7 0, L_0x1dec850; 1 drivers +v0x1bfb0c0_0 .net "in", 7 0, L_0x1ebfeb0; alias, 1 drivers +v0x1bfb180_0 .net "out", 0 0, L_0x1dee850; alias, 1 drivers +v0x1bfb250_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bf5de0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bf5bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bf8510_0 .net "A", 7 0, L_0x1ebfeb0; alias, 1 drivers +v0x1bf8610_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bf86d0_0 .net *"_s0", 0 0, L_0x1deb170; 1 drivers +v0x1bf8790_0 .net *"_s12", 0 0, L_0x1debae0; 1 drivers +v0x1bf8870_0 .net *"_s16", 0 0, L_0x1debe40; 1 drivers +v0x1bf89a0_0 .net *"_s20", 0 0, L_0x1dec150; 1 drivers +v0x1bf8a80_0 .net *"_s24", 0 0, L_0x1dec540; 1 drivers +v0x1bf8b60_0 .net *"_s28", 0 0, L_0x1dec4d0; 1 drivers +v0x1bf8c40_0 .net *"_s4", 0 0, L_0x1deb480; 1 drivers +v0x1bf8db0_0 .net *"_s8", 0 0, L_0x1deb7d0; 1 drivers +v0x1bf8e90_0 .net "out", 7 0, L_0x1dec850; alias, 1 drivers +L_0x1deb230 .part L_0x1ebfeb0, 0, 1; +L_0x1deb390 .part v0x1d6daa0_0, 0, 1; +L_0x1deb540 .part L_0x1ebfeb0, 1, 1; +L_0x1deb730 .part v0x1d6daa0_0, 1, 1; +L_0x1deb890 .part L_0x1ebfeb0, 2, 1; +L_0x1deb9f0 .part v0x1d6daa0_0, 2, 1; +L_0x1debba0 .part L_0x1ebfeb0, 3, 1; +L_0x1debd00 .part v0x1d6daa0_0, 3, 1; +L_0x1debf00 .part L_0x1ebfeb0, 4, 1; +L_0x1dec060 .part v0x1d6daa0_0, 4, 1; +L_0x1dec1c0 .part L_0x1ebfeb0, 5, 1; +L_0x1dec430 .part v0x1d6daa0_0, 5, 1; +L_0x1dec600 .part L_0x1ebfeb0, 6, 1; +L_0x1dec760 .part v0x1d6daa0_0, 6, 1; +LS_0x1dec850_0_0 .concat8 [ 1 1 1 1], L_0x1deb170, L_0x1deb480, L_0x1deb7d0, L_0x1debae0; +LS_0x1dec850_0_4 .concat8 [ 1 1 1 1], L_0x1debe40, L_0x1dec150, L_0x1dec540, L_0x1dec4d0; +L_0x1dec850 .concat8 [ 4 4 0 0], LS_0x1dec850_0_0, LS_0x1dec850_0_4; +L_0x1decc10 .part L_0x1ebfeb0, 7, 1; +L_0x1dece00 .part v0x1d6daa0_0, 7, 1; +S_0x1bf6040 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf6250 .param/l "i" 0 4 54, +C4<00>; +L_0x1deb170/d .functor AND 1, L_0x1deb230, L_0x1deb390, C4<1>, C4<1>; +L_0x1deb170 .delay 1 (30000,30000,30000) L_0x1deb170/d; +v0x1bf6330_0 .net *"_s0", 0 0, L_0x1deb230; 1 drivers +v0x1bf6410_0 .net *"_s1", 0 0, L_0x1deb390; 1 drivers +S_0x1bf64f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf6700 .param/l "i" 0 4 54, +C4<01>; +L_0x1deb480/d .functor AND 1, L_0x1deb540, L_0x1deb730, C4<1>, C4<1>; +L_0x1deb480 .delay 1 (30000,30000,30000) L_0x1deb480/d; +v0x1bf67c0_0 .net *"_s0", 0 0, L_0x1deb540; 1 drivers +v0x1bf68a0_0 .net *"_s1", 0 0, L_0x1deb730; 1 drivers +S_0x1bf6980 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf6b90 .param/l "i" 0 4 54, +C4<010>; +L_0x1deb7d0/d .functor AND 1, L_0x1deb890, L_0x1deb9f0, C4<1>, C4<1>; +L_0x1deb7d0 .delay 1 (30000,30000,30000) L_0x1deb7d0/d; +v0x1bf6c30_0 .net *"_s0", 0 0, L_0x1deb890; 1 drivers +v0x1bf6d10_0 .net *"_s1", 0 0, L_0x1deb9f0; 1 drivers +S_0x1bf6df0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf7000 .param/l "i" 0 4 54, +C4<011>; +L_0x1debae0/d .functor AND 1, L_0x1debba0, L_0x1debd00, C4<1>, C4<1>; +L_0x1debae0 .delay 1 (30000,30000,30000) L_0x1debae0/d; +v0x1bf70c0_0 .net *"_s0", 0 0, L_0x1debba0; 1 drivers +v0x1bf71a0_0 .net *"_s1", 0 0, L_0x1debd00; 1 drivers +S_0x1bf7280 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf74e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1debe40/d .functor AND 1, L_0x1debf00, L_0x1dec060, C4<1>, C4<1>; +L_0x1debe40 .delay 1 (30000,30000,30000) L_0x1debe40/d; +v0x1bf75a0_0 .net *"_s0", 0 0, L_0x1debf00; 1 drivers +v0x1bf7680_0 .net *"_s1", 0 0, L_0x1dec060; 1 drivers +S_0x1bf7760 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf7970 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dec150/d .functor AND 1, L_0x1dec1c0, L_0x1dec430, C4<1>, C4<1>; +L_0x1dec150 .delay 1 (30000,30000,30000) L_0x1dec150/d; +v0x1bf7a30_0 .net *"_s0", 0 0, L_0x1dec1c0; 1 drivers +v0x1bf7b10_0 .net *"_s1", 0 0, L_0x1dec430; 1 drivers +S_0x1bf7bf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf7e00 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dec540/d .functor AND 1, L_0x1dec600, L_0x1dec760, C4<1>, C4<1>; +L_0x1dec540 .delay 1 (30000,30000,30000) L_0x1dec540/d; +v0x1bf7ec0_0 .net *"_s0", 0 0, L_0x1dec600; 1 drivers +v0x1bf7fa0_0 .net *"_s1", 0 0, L_0x1dec760; 1 drivers +S_0x1bf8080 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bf5de0; + .timescale -9 -12; +P_0x1bf8290 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dec4d0/d .functor AND 1, L_0x1decc10, L_0x1dece00, C4<1>, C4<1>; +L_0x1dec4d0 .delay 1 (30000,30000,30000) L_0x1dec4d0/d; +v0x1bf8350_0 .net *"_s0", 0 0, L_0x1decc10; 1 drivers +v0x1bf8430_0 .net *"_s1", 0 0, L_0x1dece00; 1 drivers +S_0x1bf8ff0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bf5bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dee850/d .functor OR 1, L_0x1dee910, L_0x1deeac0, C4<0>, C4<0>; +L_0x1dee850 .delay 1 (30000,30000,30000) L_0x1dee850/d; +v0x1bfab40_0 .net *"_s10", 0 0, L_0x1dee910; 1 drivers +v0x1bfac20_0 .net *"_s12", 0 0, L_0x1deeac0; 1 drivers +v0x1bfad00_0 .net "in", 7 0, L_0x1dec850; alias, 1 drivers +v0x1bfadd0_0 .net "ors", 1 0, L_0x1dee670; 1 drivers +v0x1bfae90_0 .net "out", 0 0, L_0x1dee850; alias, 1 drivers +L_0x1deda40 .part L_0x1dec850, 0, 4; +L_0x1dee670 .concat8 [ 1 1 0 0], L_0x1ded730, L_0x1dee360; +L_0x1dee7b0 .part L_0x1dec850, 4, 4; +L_0x1dee910 .part L_0x1dee670, 0, 1; +L_0x1deeac0 .part L_0x1dee670, 1, 1; +S_0x1bf91b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bf8ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1decef0/d .functor OR 1, L_0x1decfb0, L_0x1ded110, C4<0>, C4<0>; +L_0x1decef0 .delay 1 (30000,30000,30000) L_0x1decef0/d; +L_0x1ded340/d .functor OR 1, L_0x1ded450, L_0x1ded5b0, C4<0>, C4<0>; +L_0x1ded340 .delay 1 (30000,30000,30000) L_0x1ded340/d; +L_0x1ded730/d .functor OR 1, L_0x1ded7a0, L_0x1ded950, C4<0>, C4<0>; +L_0x1ded730 .delay 1 (30000,30000,30000) L_0x1ded730/d; +v0x1bf9400_0 .net *"_s0", 0 0, L_0x1decef0; 1 drivers +v0x1bf9500_0 .net *"_s10", 0 0, L_0x1ded450; 1 drivers +v0x1bf95e0_0 .net *"_s12", 0 0, L_0x1ded5b0; 1 drivers +v0x1bf96a0_0 .net *"_s14", 0 0, L_0x1ded7a0; 1 drivers +v0x1bf9780_0 .net *"_s16", 0 0, L_0x1ded950; 1 drivers +v0x1bf98b0_0 .net *"_s3", 0 0, L_0x1decfb0; 1 drivers +v0x1bf9990_0 .net *"_s5", 0 0, L_0x1ded110; 1 drivers +v0x1bf9a70_0 .net *"_s6", 0 0, L_0x1ded340; 1 drivers +v0x1bf9b50_0 .net "in", 3 0, L_0x1deda40; 1 drivers +v0x1bf9cc0_0 .net "ors", 1 0, L_0x1ded250; 1 drivers +v0x1bf9da0_0 .net "out", 0 0, L_0x1ded730; 1 drivers +L_0x1decfb0 .part L_0x1deda40, 0, 1; +L_0x1ded110 .part L_0x1deda40, 1, 1; +L_0x1ded250 .concat8 [ 1 1 0 0], L_0x1decef0, L_0x1ded340; +L_0x1ded450 .part L_0x1deda40, 2, 1; +L_0x1ded5b0 .part L_0x1deda40, 3, 1; +L_0x1ded7a0 .part L_0x1ded250, 0, 1; +L_0x1ded950 .part L_0x1ded250, 1, 1; +S_0x1bf9ec0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bf8ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dedb70/d .functor OR 1, L_0x1dedbe0, L_0x1dedd40, C4<0>, C4<0>; +L_0x1dedb70 .delay 1 (30000,30000,30000) L_0x1dedb70/d; +L_0x1dedf70/d .functor OR 1, L_0x1dee080, L_0x1dee1e0, C4<0>, C4<0>; +L_0x1dedf70 .delay 1 (30000,30000,30000) L_0x1dedf70/d; +L_0x1dee360/d .functor OR 1, L_0x1dee3d0, L_0x1dee580, C4<0>, C4<0>; +L_0x1dee360 .delay 1 (30000,30000,30000) L_0x1dee360/d; +v0x1bfa080_0 .net *"_s0", 0 0, L_0x1dedb70; 1 drivers +v0x1bfa180_0 .net *"_s10", 0 0, L_0x1dee080; 1 drivers +v0x1bfa260_0 .net *"_s12", 0 0, L_0x1dee1e0; 1 drivers +v0x1bfa320_0 .net *"_s14", 0 0, L_0x1dee3d0; 1 drivers +v0x1bfa400_0 .net *"_s16", 0 0, L_0x1dee580; 1 drivers +v0x1bfa530_0 .net *"_s3", 0 0, L_0x1dedbe0; 1 drivers +v0x1bfa610_0 .net *"_s5", 0 0, L_0x1dedd40; 1 drivers +v0x1bfa6f0_0 .net *"_s6", 0 0, L_0x1dedf70; 1 drivers +v0x1bfa7d0_0 .net "in", 3 0, L_0x1dee7b0; 1 drivers +v0x1bfa940_0 .net "ors", 1 0, L_0x1dede80; 1 drivers +v0x1bfaa20_0 .net "out", 0 0, L_0x1dee360; 1 drivers +L_0x1dedbe0 .part L_0x1dee7b0, 0, 1; +L_0x1dedd40 .part L_0x1dee7b0, 1, 1; +L_0x1dede80 .concat8 [ 1 1 0 0], L_0x1dedb70, L_0x1dedf70; +L_0x1dee080 .part L_0x1dee7b0, 2, 1; +L_0x1dee1e0 .part L_0x1dee7b0, 3, 1; +L_0x1dee3d0 .part L_0x1dede80, 0, 1; +L_0x1dee580 .part L_0x1dede80, 1, 1; +S_0x1bfb330 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bf4460; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c00760_0 .net "ands", 7 0, L_0x1de8e10; 1 drivers +v0x1c00870_0 .net "in", 7 0, L_0x1de7270; alias, 1 drivers +v0x1c00930_0 .net "out", 0 0, L_0x1deae10; alias, 1 drivers +v0x1c00a00_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1bfb580 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bfb330; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1bfdcc0_0 .net "A", 7 0, L_0x1de7270; alias, 1 drivers +v0x1bfddc0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1bfde80_0 .net *"_s0", 0 0, L_0x1de7600; 1 drivers +v0x1bfdf40_0 .net *"_s12", 0 0, L_0x1de7fc0; 1 drivers +v0x1bfe020_0 .net *"_s16", 0 0, L_0x1de8320; 1 drivers +v0x1bfe150_0 .net *"_s20", 0 0, L_0x1de8750; 1 drivers +v0x1bfe230_0 .net *"_s24", 0 0, L_0x1de8a80; 1 drivers +v0x1bfe310_0 .net *"_s28", 0 0, L_0x1de8a10; 1 drivers +v0x1bfe3f0_0 .net *"_s4", 0 0, L_0x1de79a0; 1 drivers +v0x1bfe560_0 .net *"_s8", 0 0, L_0x1de7cb0; 1 drivers +v0x1bfe640_0 .net "out", 7 0, L_0x1de8e10; alias, 1 drivers +L_0x1de7710 .part L_0x1de7270, 0, 1; +L_0x1de7900 .part v0x1d6daa0_0, 0, 1; +L_0x1de7a60 .part L_0x1de7270, 1, 1; +L_0x1de7bc0 .part v0x1d6daa0_0, 1, 1; +L_0x1de7d70 .part L_0x1de7270, 2, 1; +L_0x1de7ed0 .part v0x1d6daa0_0, 2, 1; +L_0x1de8080 .part L_0x1de7270, 3, 1; +L_0x1de81e0 .part v0x1d6daa0_0, 3, 1; +L_0x1de83e0 .part L_0x1de7270, 4, 1; +L_0x1de8650 .part v0x1d6daa0_0, 4, 1; +L_0x1de87c0 .part L_0x1de7270, 5, 1; +L_0x1de8920 .part v0x1d6daa0_0, 5, 1; +L_0x1de8b40 .part L_0x1de7270, 6, 1; +L_0x1de8ca0 .part v0x1d6daa0_0, 6, 1; +LS_0x1de8e10_0_0 .concat8 [ 1 1 1 1], L_0x1de7600, L_0x1de79a0, L_0x1de7cb0, L_0x1de7fc0; +LS_0x1de8e10_0_4 .concat8 [ 1 1 1 1], L_0x1de8320, L_0x1de8750, L_0x1de8a80, L_0x1de8a10; +L_0x1de8e10 .concat8 [ 4 4 0 0], LS_0x1de8e10_0_0, LS_0x1de8e10_0_4; +L_0x1de91d0 .part L_0x1de7270, 7, 1; +L_0x1de93c0 .part v0x1d6daa0_0, 7, 1; +S_0x1bfb7c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfb9d0 .param/l "i" 0 4 54, +C4<00>; +L_0x1de7600/d .functor AND 1, L_0x1de7710, L_0x1de7900, C4<1>, C4<1>; +L_0x1de7600 .delay 1 (30000,30000,30000) L_0x1de7600/d; +v0x1bfbab0_0 .net *"_s0", 0 0, L_0x1de7710; 1 drivers +v0x1bfbb90_0 .net *"_s1", 0 0, L_0x1de7900; 1 drivers +S_0x1bfbc70 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfbe80 .param/l "i" 0 4 54, +C4<01>; +L_0x1de79a0/d .functor AND 1, L_0x1de7a60, L_0x1de7bc0, C4<1>, C4<1>; +L_0x1de79a0 .delay 1 (30000,30000,30000) L_0x1de79a0/d; +v0x1bfbf40_0 .net *"_s0", 0 0, L_0x1de7a60; 1 drivers +v0x1bfc020_0 .net *"_s1", 0 0, L_0x1de7bc0; 1 drivers +S_0x1bfc100 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfc340 .param/l "i" 0 4 54, +C4<010>; +L_0x1de7cb0/d .functor AND 1, L_0x1de7d70, L_0x1de7ed0, C4<1>, C4<1>; +L_0x1de7cb0 .delay 1 (30000,30000,30000) L_0x1de7cb0/d; +v0x1bfc3e0_0 .net *"_s0", 0 0, L_0x1de7d70; 1 drivers +v0x1bfc4c0_0 .net *"_s1", 0 0, L_0x1de7ed0; 1 drivers +S_0x1bfc5a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfc7b0 .param/l "i" 0 4 54, +C4<011>; +L_0x1de7fc0/d .functor AND 1, L_0x1de8080, L_0x1de81e0, C4<1>, C4<1>; +L_0x1de7fc0 .delay 1 (30000,30000,30000) L_0x1de7fc0/d; +v0x1bfc870_0 .net *"_s0", 0 0, L_0x1de8080; 1 drivers +v0x1bfc950_0 .net *"_s1", 0 0, L_0x1de81e0; 1 drivers +S_0x1bfca30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfcc90 .param/l "i" 0 4 54, +C4<0100>; +L_0x1de8320/d .functor AND 1, L_0x1de83e0, L_0x1de8650, C4<1>, C4<1>; +L_0x1de8320 .delay 1 (30000,30000,30000) L_0x1de8320/d; +v0x1bfcd50_0 .net *"_s0", 0 0, L_0x1de83e0; 1 drivers +v0x1bfce30_0 .net *"_s1", 0 0, L_0x1de8650; 1 drivers +S_0x1bfcf10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfd120 .param/l "i" 0 4 54, +C4<0101>; +L_0x1de8750/d .functor AND 1, L_0x1de87c0, L_0x1de8920, C4<1>, C4<1>; +L_0x1de8750 .delay 1 (30000,30000,30000) L_0x1de8750/d; +v0x1bfd1e0_0 .net *"_s0", 0 0, L_0x1de87c0; 1 drivers +v0x1bfd2c0_0 .net *"_s1", 0 0, L_0x1de8920; 1 drivers +S_0x1bfd3a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfd5b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1de8a80/d .functor AND 1, L_0x1de8b40, L_0x1de8ca0, C4<1>, C4<1>; +L_0x1de8a80 .delay 1 (30000,30000,30000) L_0x1de8a80/d; +v0x1bfd670_0 .net *"_s0", 0 0, L_0x1de8b40; 1 drivers +v0x1bfd750_0 .net *"_s1", 0 0, L_0x1de8ca0; 1 drivers +S_0x1bfd830 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bfb580; + .timescale -9 -12; +P_0x1bfda40 .param/l "i" 0 4 54, +C4<0111>; +L_0x1de8a10/d .functor AND 1, L_0x1de91d0, L_0x1de93c0, C4<1>, C4<1>; +L_0x1de8a10 .delay 1 (30000,30000,30000) L_0x1de8a10/d; +v0x1bfdb00_0 .net *"_s0", 0 0, L_0x1de91d0; 1 drivers +v0x1bfdbe0_0 .net *"_s1", 0 0, L_0x1de93c0; 1 drivers +S_0x1bfe7a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bfb330; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1deae10/d .functor OR 1, L_0x1deaed0, L_0x1deb080, C4<0>, C4<0>; +L_0x1deae10 .delay 1 (30000,30000,30000) L_0x1deae10/d; +v0x1c002f0_0 .net *"_s10", 0 0, L_0x1deaed0; 1 drivers +v0x1c003d0_0 .net *"_s12", 0 0, L_0x1deb080; 1 drivers +v0x1c004b0_0 .net "in", 7 0, L_0x1de8e10; alias, 1 drivers +v0x1c00580_0 .net "ors", 1 0, L_0x1deac30; 1 drivers +v0x1c00640_0 .net "out", 0 0, L_0x1deae10; alias, 1 drivers +L_0x1dea000 .part L_0x1de8e10, 0, 4; +L_0x1deac30 .concat8 [ 1 1 0 0], L_0x1de9cf0, L_0x1dea920; +L_0x1dead70 .part L_0x1de8e10, 4, 4; +L_0x1deaed0 .part L_0x1deac30, 0, 1; +L_0x1deb080 .part L_0x1deac30, 1, 1; +S_0x1bfe960 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bfe7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1de94b0/d .functor OR 1, L_0x1de9570, L_0x1de96d0, C4<0>, C4<0>; +L_0x1de94b0 .delay 1 (30000,30000,30000) L_0x1de94b0/d; +L_0x1de9900/d .functor OR 1, L_0x1de9a10, L_0x1de9b70, C4<0>, C4<0>; +L_0x1de9900 .delay 1 (30000,30000,30000) L_0x1de9900/d; +L_0x1de9cf0/d .functor OR 1, L_0x1de9d60, L_0x1de9f10, C4<0>, C4<0>; +L_0x1de9cf0 .delay 1 (30000,30000,30000) L_0x1de9cf0/d; +v0x1bfebb0_0 .net *"_s0", 0 0, L_0x1de94b0; 1 drivers +v0x1bfecb0_0 .net *"_s10", 0 0, L_0x1de9a10; 1 drivers +v0x1bfed90_0 .net *"_s12", 0 0, L_0x1de9b70; 1 drivers +v0x1bfee50_0 .net *"_s14", 0 0, L_0x1de9d60; 1 drivers +v0x1bfef30_0 .net *"_s16", 0 0, L_0x1de9f10; 1 drivers +v0x1bff060_0 .net *"_s3", 0 0, L_0x1de9570; 1 drivers +v0x1bff140_0 .net *"_s5", 0 0, L_0x1de96d0; 1 drivers +v0x1bff220_0 .net *"_s6", 0 0, L_0x1de9900; 1 drivers +v0x1bff300_0 .net "in", 3 0, L_0x1dea000; 1 drivers +v0x1bff470_0 .net "ors", 1 0, L_0x1de9810; 1 drivers +v0x1bff550_0 .net "out", 0 0, L_0x1de9cf0; 1 drivers +L_0x1de9570 .part L_0x1dea000, 0, 1; +L_0x1de96d0 .part L_0x1dea000, 1, 1; +L_0x1de9810 .concat8 [ 1 1 0 0], L_0x1de94b0, L_0x1de9900; +L_0x1de9a10 .part L_0x1dea000, 2, 1; +L_0x1de9b70 .part L_0x1dea000, 3, 1; +L_0x1de9d60 .part L_0x1de9810, 0, 1; +L_0x1de9f10 .part L_0x1de9810, 1, 1; +S_0x1bff670 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bfe7a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dea130/d .functor OR 1, L_0x1dea1a0, L_0x1dea300, C4<0>, C4<0>; +L_0x1dea130 .delay 1 (30000,30000,30000) L_0x1dea130/d; +L_0x1dea530/d .functor OR 1, L_0x1dea640, L_0x1dea7a0, C4<0>, C4<0>; +L_0x1dea530 .delay 1 (30000,30000,30000) L_0x1dea530/d; +L_0x1dea920/d .functor OR 1, L_0x1dea990, L_0x1deab40, C4<0>, C4<0>; +L_0x1dea920 .delay 1 (30000,30000,30000) L_0x1dea920/d; +v0x1bff830_0 .net *"_s0", 0 0, L_0x1dea130; 1 drivers +v0x1bff930_0 .net *"_s10", 0 0, L_0x1dea640; 1 drivers +v0x1bffa10_0 .net *"_s12", 0 0, L_0x1dea7a0; 1 drivers +v0x1bffad0_0 .net *"_s14", 0 0, L_0x1dea990; 1 drivers +v0x1bffbb0_0 .net *"_s16", 0 0, L_0x1deab40; 1 drivers +v0x1bffce0_0 .net *"_s3", 0 0, L_0x1dea1a0; 1 drivers +v0x1bffdc0_0 .net *"_s5", 0 0, L_0x1dea300; 1 drivers +v0x1bffea0_0 .net *"_s6", 0 0, L_0x1dea530; 1 drivers +v0x1bfff80_0 .net "in", 3 0, L_0x1dead70; 1 drivers +v0x1c000f0_0 .net "ors", 1 0, L_0x1dea440; 1 drivers +v0x1c001d0_0 .net "out", 0 0, L_0x1dea920; 1 drivers +L_0x1dea1a0 .part L_0x1dead70, 0, 1; +L_0x1dea300 .part L_0x1dead70, 1, 1; +L_0x1dea440 .concat8 [ 1 1 0 0], L_0x1dea130, L_0x1dea530; +L_0x1dea640 .part L_0x1dead70, 2, 1; +L_0x1dea7a0 .part L_0x1dead70, 3, 1; +L_0x1dea990 .part L_0x1dea440, 0, 1; +L_0x1deab40 .part L_0x1dea440, 1, 1; +S_0x1c00ae0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bf4460; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1de65e0/d .functor XNOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; +L_0x1de65e0 .delay 1 (20000,20000,20000) L_0x1de65e0/d; +L_0x1de6850/d .functor AND 1, L_0x1deecb0, L_0x1de55e0, C4<1>, C4<1>; +L_0x1de6850 .delay 1 (30000,30000,30000) L_0x1de6850/d; +L_0x1de68c0/d .functor AND 1, L_0x1de65e0, L_0x1de53c0, C4<1>, C4<1>; +L_0x1de68c0 .delay 1 (30000,30000,30000) L_0x1de68c0/d; +L_0x1de6a20/d .functor OR 1, L_0x1de68c0, L_0x1de6850, C4<0>, C4<0>; +L_0x1de6a20 .delay 1 (30000,30000,30000) L_0x1de6a20/d; +v0x1c00d90_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers +v0x1c00e80_0 .net "a_", 0 0, L_0x1de52a0; alias, 1 drivers +v0x1c00f40_0 .net "b", 0 0, L_0x1deee10; alias, 1 drivers +v0x1c01030_0 .net "b_", 0 0, L_0x1de55e0; alias, 1 drivers +v0x1c010d0_0 .net "carryin", 0 0, L_0x1de53c0; alias, 1 drivers +v0x1c01210_0 .net "eq", 0 0, L_0x1de65e0; 1 drivers +v0x1c012d0_0 .net "lt", 0 0, L_0x1de6850; 1 drivers +v0x1c01390_0 .net "out", 0 0, L_0x1de6a20; 1 drivers +v0x1c01450_0 .net "w0", 0 0, L_0x1de68c0; 1 drivers +S_0x1c016a0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bf4460; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1de63c0/d .functor OR 1, L_0x1de5f10, L_0x1c02900, C4<0>, C4<0>; +L_0x1de63c0 .delay 1 (30000,30000,30000) L_0x1de63c0/d; +v0x1c02490_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers +v0x1c025e0_0 .net "b", 0 0, L_0x1de55e0; alias, 1 drivers +v0x1c026a0_0 .net "c1", 0 0, L_0x1de5f10; 1 drivers +v0x1c02740_0 .net "c2", 0 0, L_0x1c02900; 1 drivers +v0x1c02810_0 .net "carryin", 0 0, L_0x1de53c0; alias, 1 drivers +v0x1c02990_0 .net "carryout", 0 0, L_0x1de63c0; 1 drivers +v0x1c02a30_0 .net "s1", 0 0, L_0x1de5e50; 1 drivers +v0x1c02ad0_0 .net "sum", 0 0, L_0x1de6070; 1 drivers +S_0x1c018f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c016a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1de5e50/d .functor XOR 1, L_0x1deecb0, L_0x1de55e0, C4<0>, C4<0>; +L_0x1de5e50 .delay 1 (30000,30000,30000) L_0x1de5e50/d; +L_0x1de5f10/d .functor AND 1, L_0x1deecb0, L_0x1de55e0, C4<1>, C4<1>; +L_0x1de5f10 .delay 1 (30000,30000,30000) L_0x1de5f10/d; +v0x1c01b50_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers +v0x1c01c10_0 .net "b", 0 0, L_0x1de55e0; alias, 1 drivers +v0x1c01cd0_0 .net "carryout", 0 0, L_0x1de5f10; alias, 1 drivers +v0x1c01d70_0 .net "sum", 0 0, L_0x1de5e50; alias, 1 drivers +S_0x1c01ea0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c016a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1de6070/d .functor XOR 1, L_0x1de5e50, L_0x1de53c0, C4<0>, C4<0>; +L_0x1de6070 .delay 1 (30000,30000,30000) L_0x1de6070/d; +L_0x1c02900/d .functor AND 1, L_0x1de5e50, L_0x1de53c0, C4<1>, C4<1>; +L_0x1c02900 .delay 1 (30000,30000,30000) L_0x1c02900/d; +v0x1c02100_0 .net "a", 0 0, L_0x1de5e50; alias, 1 drivers +v0x1c021d0_0 .net "b", 0 0, L_0x1de53c0; alias, 1 drivers +v0x1c02270_0 .net "carryout", 0 0, L_0x1c02900; alias, 1 drivers +v0x1c02340_0 .net "sum", 0 0, L_0x1de6070; alias, 1 drivers +S_0x1c04360 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bf4190; + .timescale -9 -12; +L_0x7f72592dad98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dade0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1deed50/d .functor OR 1, L_0x7f72592dad98, L_0x7f72592dade0, C4<0>, C4<0>; +L_0x1deed50 .delay 1 (30000,30000,30000) L_0x1deed50/d; +v0x1c044e0_0 .net/2u *"_s0", 0 0, L_0x7f72592dad98; 1 drivers +v0x1c04580_0 .net/2u *"_s2", 0 0, L_0x7f72592dade0; 1 drivers +S_0x1c04640 .scope generate, "alu_slices[13]" "alu_slices[13]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c04850 .param/l "i" 0 3 37, +C4<01101>; +S_0x1c04910 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c04640; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1def090/d .functor NOT 1, L_0x1df88f0, C4<0>, C4<0>, C4<0>; +L_0x1def090 .delay 1 (10000,10000,10000) L_0x1def090/d; +L_0x1def1f0/d .functor NOT 1, L_0x1deeeb0, C4<0>, C4<0>, C4<0>; +L_0x1def1f0 .delay 1 (10000,10000,10000) L_0x1def1f0/d; +L_0x1df0240/d .functor XOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; +L_0x1df0240 .delay 1 (30000,30000,30000) L_0x1df0240/d; +L_0x7f72592dae28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dae70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1df08f0/d .functor OR 1, L_0x7f72592dae28, L_0x7f72592dae70, C4<0>, C4<0>; +L_0x1df08f0 .delay 1 (30000,30000,30000) L_0x1df08f0/d; +L_0x1df0af0/d .functor AND 1, L_0x1df88f0, L_0x1deeeb0, C4<1>, C4<1>; +L_0x1df0af0 .delay 1 (30000,30000,30000) L_0x1df0af0/d; +L_0x1df0bb0/d .functor NAND 1, L_0x1df88f0, L_0x1deeeb0, C4<1>, C4<1>; +L_0x1df0bb0 .delay 1 (20000,20000,20000) L_0x1df0bb0/d; +L_0x1df0d10/d .functor XOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; +L_0x1df0d10 .delay 1 (20000,20000,20000) L_0x1df0d10/d; +L_0x1df11c0/d .functor OR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; +L_0x1df11c0 .delay 1 (30000,30000,30000) L_0x1df11c0/d; +L_0x1df87f0/d .functor NOT 1, L_0x1df4a50, C4<0>, C4<0>, C4<0>; +L_0x1df87f0 .delay 1 (10000,10000,10000) L_0x1df87f0/d; +v0x1c130d0_0 .net "A", 0 0, L_0x1df88f0; 1 drivers +v0x1c13190_0 .net "A_", 0 0, L_0x1def090; 1 drivers +v0x1c13250_0 .net "B", 0 0, L_0x1deeeb0; 1 drivers +v0x1c13320_0 .net "B_", 0 0, L_0x1def1f0; 1 drivers +v0x1c133c0_0 .net *"_s12", 0 0, L_0x1df08f0; 1 drivers +v0x1c134b0_0 .net/2s *"_s14", 0 0, L_0x7f72592dae28; 1 drivers +v0x1c13570_0 .net/2s *"_s16", 0 0, L_0x7f72592dae70; 1 drivers +v0x1c13650_0 .net *"_s18", 0 0, L_0x1df0af0; 1 drivers +v0x1c13730_0 .net *"_s20", 0 0, L_0x1df0bb0; 1 drivers +v0x1c138a0_0 .net *"_s22", 0 0, L_0x1df0d10; 1 drivers +v0x1c13980_0 .net *"_s24", 0 0, L_0x1df11c0; 1 drivers +o0x7f72593747d8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c13a60_0 name=_s30 +o0x7f7259374808 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c13b40_0 name=_s32 +v0x1c13c20_0 .net *"_s8", 0 0, L_0x1df0240; 1 drivers +v0x1c13d00_0 .net "carryin", 0 0, L_0x1deef50; 1 drivers +v0x1c13da0_0 .net "carryout", 0 0, L_0x1df8490; 1 drivers +v0x1c13e40_0 .net "carryouts", 7 0, L_0x1ec0080; 1 drivers +v0x1c13ff0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c14090_0 .net "result", 0 0, L_0x1df4a50; 1 drivers +v0x1c14180_0 .net "results", 7 0, L_0x1df0f90; 1 drivers +v0x1c14290_0 .net "zero", 0 0, L_0x1df87f0; 1 drivers +LS_0x1df0f90_0_0 .concat8 [ 1 1 1 1], L_0x1def710, L_0x1defd40, L_0x1df0240, L_0x1df08f0; +LS_0x1df0f90_0_4 .concat8 [ 1 1 1 1], L_0x1df0af0, L_0x1df0bb0, L_0x1df0d10, L_0x1df11c0; +L_0x1df0f90 .concat8 [ 4 4 0 0], LS_0x1df0f90_0_0, LS_0x1df0f90_0_4; +LS_0x1ec0080_0_0 .concat [ 1 1 1 1], L_0x1def9c0, L_0x1df00e0, o0x7f72593747d8, L_0x1df0740; +LS_0x1ec0080_0_4 .concat [ 4 0 0 0], o0x7f7259374808; +L_0x1ec0080 .concat [ 4 4 0 0], LS_0x1ec0080_0_0, LS_0x1ec0080_0_4; +S_0x1c04b90 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c04910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1def9c0/d .functor OR 1, L_0x1def4a0, L_0x1def860, C4<0>, C4<0>; +L_0x1def9c0 .delay 1 (30000,30000,30000) L_0x1def9c0/d; +v0x1c05a50_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers +v0x1c05b10_0 .net "b", 0 0, L_0x1deeeb0; alias, 1 drivers +v0x1c05be0_0 .net "c1", 0 0, L_0x1def4a0; 1 drivers +v0x1c05ce0_0 .net "c2", 0 0, L_0x1def860; 1 drivers +v0x1c05db0_0 .net "carryin", 0 0, L_0x1deef50; alias, 1 drivers +v0x1c05ea0_0 .net "carryout", 0 0, L_0x1def9c0; 1 drivers +v0x1c05f40_0 .net "s1", 0 0, L_0x1def3e0; 1 drivers +v0x1c06030_0 .net "sum", 0 0, L_0x1def710; 1 drivers +S_0x1c04e00 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c04b90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1def3e0/d .functor XOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; +L_0x1def3e0 .delay 1 (30000,30000,30000) L_0x1def3e0/d; +L_0x1def4a0/d .functor AND 1, L_0x1df88f0, L_0x1deeeb0, C4<1>, C4<1>; +L_0x1def4a0 .delay 1 (30000,30000,30000) L_0x1def4a0/d; +v0x1c05060_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers +v0x1c05140_0 .net "b", 0 0, L_0x1deeeb0; alias, 1 drivers +v0x1c05200_0 .net "carryout", 0 0, L_0x1def4a0; alias, 1 drivers +v0x1c052d0_0 .net "sum", 0 0, L_0x1def3e0; alias, 1 drivers +S_0x1c05440 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c04b90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1def710/d .functor XOR 1, L_0x1def3e0, L_0x1deef50, C4<0>, C4<0>; +L_0x1def710 .delay 1 (30000,30000,30000) L_0x1def710/d; +L_0x1def860/d .functor AND 1, L_0x1def3e0, L_0x1deef50, C4<1>, C4<1>; +L_0x1def860 .delay 1 (30000,30000,30000) L_0x1def860/d; +v0x1c056a0_0 .net "a", 0 0, L_0x1def3e0; alias, 1 drivers +v0x1c05770_0 .net "b", 0 0, L_0x1deef50; alias, 1 drivers +v0x1c05810_0 .net "carryout", 0 0, L_0x1def860; alias, 1 drivers +v0x1c058e0_0 .net "sum", 0 0, L_0x1def710; alias, 1 drivers +S_0x1c06100 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c04910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c0b4f0_0 .net "ands", 7 0, L_0x1df6490; 1 drivers +v0x1c0b600_0 .net "in", 7 0, L_0x1ec0080; alias, 1 drivers +v0x1c0b6c0_0 .net "out", 0 0, L_0x1df8490; alias, 1 drivers +v0x1c0b790_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c06320 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c06100; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c08a50_0 .net "A", 7 0, L_0x1ec0080; alias, 1 drivers +v0x1c08b50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c08c10_0 .net *"_s0", 0 0, L_0x1df4db0; 1 drivers +v0x1c08cd0_0 .net *"_s12", 0 0, L_0x1df5720; 1 drivers +v0x1c08db0_0 .net *"_s16", 0 0, L_0x1df5a80; 1 drivers +v0x1c08ee0_0 .net *"_s20", 0 0, L_0x1df5d90; 1 drivers +v0x1c08fc0_0 .net *"_s24", 0 0, L_0x1df6180; 1 drivers +v0x1c090a0_0 .net *"_s28", 0 0, L_0x1df6110; 1 drivers +v0x1c09180_0 .net *"_s4", 0 0, L_0x1df50c0; 1 drivers +v0x1c092f0_0 .net *"_s8", 0 0, L_0x1df5410; 1 drivers +v0x1c093d0_0 .net "out", 7 0, L_0x1df6490; alias, 1 drivers +L_0x1df4e70 .part L_0x1ec0080, 0, 1; +L_0x1df4fd0 .part v0x1d6daa0_0, 0, 1; +L_0x1df5180 .part L_0x1ec0080, 1, 1; +L_0x1df5370 .part v0x1d6daa0_0, 1, 1; +L_0x1df54d0 .part L_0x1ec0080, 2, 1; +L_0x1df5630 .part v0x1d6daa0_0, 2, 1; +L_0x1df57e0 .part L_0x1ec0080, 3, 1; +L_0x1df5940 .part v0x1d6daa0_0, 3, 1; +L_0x1df5b40 .part L_0x1ec0080, 4, 1; +L_0x1df5ca0 .part v0x1d6daa0_0, 4, 1; +L_0x1df5e00 .part L_0x1ec0080, 5, 1; +L_0x1df6070 .part v0x1d6daa0_0, 5, 1; +L_0x1df6240 .part L_0x1ec0080, 6, 1; +L_0x1df63a0 .part v0x1d6daa0_0, 6, 1; +LS_0x1df6490_0_0 .concat8 [ 1 1 1 1], L_0x1df4db0, L_0x1df50c0, L_0x1df5410, L_0x1df5720; +LS_0x1df6490_0_4 .concat8 [ 1 1 1 1], L_0x1df5a80, L_0x1df5d90, L_0x1df6180, L_0x1df6110; +L_0x1df6490 .concat8 [ 4 4 0 0], LS_0x1df6490_0_0, LS_0x1df6490_0_4; +L_0x1df6850 .part L_0x1ec0080, 7, 1; +L_0x1df6a40 .part v0x1d6daa0_0, 7, 1; +S_0x1c06580 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c06790 .param/l "i" 0 4 54, +C4<00>; +L_0x1df4db0/d .functor AND 1, L_0x1df4e70, L_0x1df4fd0, C4<1>, C4<1>; +L_0x1df4db0 .delay 1 (30000,30000,30000) L_0x1df4db0/d; +v0x1c06870_0 .net *"_s0", 0 0, L_0x1df4e70; 1 drivers +v0x1c06950_0 .net *"_s1", 0 0, L_0x1df4fd0; 1 drivers +S_0x1c06a30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c06c40 .param/l "i" 0 4 54, +C4<01>; +L_0x1df50c0/d .functor AND 1, L_0x1df5180, L_0x1df5370, C4<1>, C4<1>; +L_0x1df50c0 .delay 1 (30000,30000,30000) L_0x1df50c0/d; +v0x1c06d00_0 .net *"_s0", 0 0, L_0x1df5180; 1 drivers +v0x1c06de0_0 .net *"_s1", 0 0, L_0x1df5370; 1 drivers +S_0x1c06ec0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c070d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1df5410/d .functor AND 1, L_0x1df54d0, L_0x1df5630, C4<1>, C4<1>; +L_0x1df5410 .delay 1 (30000,30000,30000) L_0x1df5410/d; +v0x1c07170_0 .net *"_s0", 0 0, L_0x1df54d0; 1 drivers +v0x1c07250_0 .net *"_s1", 0 0, L_0x1df5630; 1 drivers +S_0x1c07330 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c07540 .param/l "i" 0 4 54, +C4<011>; +L_0x1df5720/d .functor AND 1, L_0x1df57e0, L_0x1df5940, C4<1>, C4<1>; +L_0x1df5720 .delay 1 (30000,30000,30000) L_0x1df5720/d; +v0x1c07600_0 .net *"_s0", 0 0, L_0x1df57e0; 1 drivers +v0x1c076e0_0 .net *"_s1", 0 0, L_0x1df5940; 1 drivers +S_0x1c077c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c07a20 .param/l "i" 0 4 54, +C4<0100>; +L_0x1df5a80/d .functor AND 1, L_0x1df5b40, L_0x1df5ca0, C4<1>, C4<1>; +L_0x1df5a80 .delay 1 (30000,30000,30000) L_0x1df5a80/d; +v0x1c07ae0_0 .net *"_s0", 0 0, L_0x1df5b40; 1 drivers +v0x1c07bc0_0 .net *"_s1", 0 0, L_0x1df5ca0; 1 drivers +S_0x1c07ca0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c07eb0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1df5d90/d .functor AND 1, L_0x1df5e00, L_0x1df6070, C4<1>, C4<1>; +L_0x1df5d90 .delay 1 (30000,30000,30000) L_0x1df5d90/d; +v0x1c07f70_0 .net *"_s0", 0 0, L_0x1df5e00; 1 drivers +v0x1c08050_0 .net *"_s1", 0 0, L_0x1df6070; 1 drivers +S_0x1c08130 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c08340 .param/l "i" 0 4 54, +C4<0110>; +L_0x1df6180/d .functor AND 1, L_0x1df6240, L_0x1df63a0, C4<1>, C4<1>; +L_0x1df6180 .delay 1 (30000,30000,30000) L_0x1df6180/d; +v0x1c08400_0 .net *"_s0", 0 0, L_0x1df6240; 1 drivers +v0x1c084e0_0 .net *"_s1", 0 0, L_0x1df63a0; 1 drivers +S_0x1c085c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c06320; + .timescale -9 -12; +P_0x1c087d0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1df6110/d .functor AND 1, L_0x1df6850, L_0x1df6a40, C4<1>, C4<1>; +L_0x1df6110 .delay 1 (30000,30000,30000) L_0x1df6110/d; +v0x1c08890_0 .net *"_s0", 0 0, L_0x1df6850; 1 drivers +v0x1c08970_0 .net *"_s1", 0 0, L_0x1df6a40; 1 drivers +S_0x1c09530 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c06100; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1df8490/d .functor OR 1, L_0x1df8550, L_0x1df8700, C4<0>, C4<0>; +L_0x1df8490 .delay 1 (30000,30000,30000) L_0x1df8490/d; +v0x1c0b080_0 .net *"_s10", 0 0, L_0x1df8550; 1 drivers +v0x1c0b160_0 .net *"_s12", 0 0, L_0x1df8700; 1 drivers +v0x1c0b240_0 .net "in", 7 0, L_0x1df6490; alias, 1 drivers +v0x1c0b310_0 .net "ors", 1 0, L_0x1df82b0; 1 drivers +v0x1c0b3d0_0 .net "out", 0 0, L_0x1df8490; alias, 1 drivers +L_0x1df7680 .part L_0x1df6490, 0, 4; +L_0x1df82b0 .concat8 [ 1 1 0 0], L_0x1df7370, L_0x1df7fa0; +L_0x1df83f0 .part L_0x1df6490, 4, 4; +L_0x1df8550 .part L_0x1df82b0, 0, 1; +L_0x1df8700 .part L_0x1df82b0, 1, 1; +S_0x1c096f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c09530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1df6b30/d .functor OR 1, L_0x1df6bf0, L_0x1df6d50, C4<0>, C4<0>; +L_0x1df6b30 .delay 1 (30000,30000,30000) L_0x1df6b30/d; +L_0x1df6f80/d .functor OR 1, L_0x1df7090, L_0x1df71f0, C4<0>, C4<0>; +L_0x1df6f80 .delay 1 (30000,30000,30000) L_0x1df6f80/d; +L_0x1df7370/d .functor OR 1, L_0x1df73e0, L_0x1df7590, C4<0>, C4<0>; +L_0x1df7370 .delay 1 (30000,30000,30000) L_0x1df7370/d; +v0x1c09940_0 .net *"_s0", 0 0, L_0x1df6b30; 1 drivers +v0x1c09a40_0 .net *"_s10", 0 0, L_0x1df7090; 1 drivers +v0x1c09b20_0 .net *"_s12", 0 0, L_0x1df71f0; 1 drivers +v0x1c09be0_0 .net *"_s14", 0 0, L_0x1df73e0; 1 drivers +v0x1c09cc0_0 .net *"_s16", 0 0, L_0x1df7590; 1 drivers +v0x1c09df0_0 .net *"_s3", 0 0, L_0x1df6bf0; 1 drivers +v0x1c09ed0_0 .net *"_s5", 0 0, L_0x1df6d50; 1 drivers +v0x1c09fb0_0 .net *"_s6", 0 0, L_0x1df6f80; 1 drivers +v0x1c0a090_0 .net "in", 3 0, L_0x1df7680; 1 drivers +v0x1c0a200_0 .net "ors", 1 0, L_0x1df6e90; 1 drivers +v0x1c0a2e0_0 .net "out", 0 0, L_0x1df7370; 1 drivers +L_0x1df6bf0 .part L_0x1df7680, 0, 1; +L_0x1df6d50 .part L_0x1df7680, 1, 1; +L_0x1df6e90 .concat8 [ 1 1 0 0], L_0x1df6b30, L_0x1df6f80; +L_0x1df7090 .part L_0x1df7680, 2, 1; +L_0x1df71f0 .part L_0x1df7680, 3, 1; +L_0x1df73e0 .part L_0x1df6e90, 0, 1; +L_0x1df7590 .part L_0x1df6e90, 1, 1; +S_0x1c0a400 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c09530; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1df77b0/d .functor OR 1, L_0x1df7820, L_0x1df7980, C4<0>, C4<0>; +L_0x1df77b0 .delay 1 (30000,30000,30000) L_0x1df77b0/d; +L_0x1df7bb0/d .functor OR 1, L_0x1df7cc0, L_0x1df7e20, C4<0>, C4<0>; +L_0x1df7bb0 .delay 1 (30000,30000,30000) L_0x1df7bb0/d; +L_0x1df7fa0/d .functor OR 1, L_0x1df8010, L_0x1df81c0, C4<0>, C4<0>; +L_0x1df7fa0 .delay 1 (30000,30000,30000) L_0x1df7fa0/d; +v0x1c0a5c0_0 .net *"_s0", 0 0, L_0x1df77b0; 1 drivers +v0x1c0a6c0_0 .net *"_s10", 0 0, L_0x1df7cc0; 1 drivers +v0x1c0a7a0_0 .net *"_s12", 0 0, L_0x1df7e20; 1 drivers +v0x1c0a860_0 .net *"_s14", 0 0, L_0x1df8010; 1 drivers +v0x1c0a940_0 .net *"_s16", 0 0, L_0x1df81c0; 1 drivers +v0x1c0aa70_0 .net *"_s3", 0 0, L_0x1df7820; 1 drivers +v0x1c0ab50_0 .net *"_s5", 0 0, L_0x1df7980; 1 drivers +v0x1c0ac30_0 .net *"_s6", 0 0, L_0x1df7bb0; 1 drivers +v0x1c0ad10_0 .net "in", 3 0, L_0x1df83f0; 1 drivers +v0x1c0ae80_0 .net "ors", 1 0, L_0x1df7ac0; 1 drivers +v0x1c0af60_0 .net "out", 0 0, L_0x1df7fa0; 1 drivers +L_0x1df7820 .part L_0x1df83f0, 0, 1; +L_0x1df7980 .part L_0x1df83f0, 1, 1; +L_0x1df7ac0 .concat8 [ 1 1 0 0], L_0x1df77b0, L_0x1df7bb0; +L_0x1df7cc0 .part L_0x1df83f0, 2, 1; +L_0x1df7e20 .part L_0x1df83f0, 3, 1; +L_0x1df8010 .part L_0x1df7ac0, 0, 1; +L_0x1df81c0 .part L_0x1df7ac0, 1, 1; +S_0x1c0b870 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c04910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c10ca0_0 .net "ands", 7 0, L_0x1df2a50; 1 drivers +v0x1c10db0_0 .net "in", 7 0, L_0x1df0f90; alias, 1 drivers +v0x1c10e70_0 .net "out", 0 0, L_0x1df4a50; alias, 1 drivers +v0x1c10f40_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c0bac0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c0b870; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c0e200_0 .net "A", 7 0, L_0x1df0f90; alias, 1 drivers +v0x1c0e300_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c0e3c0_0 .net *"_s0", 0 0, L_0x1df1320; 1 drivers +v0x1c0e480_0 .net *"_s12", 0 0, L_0x1df1ce0; 1 drivers +v0x1c0e560_0 .net *"_s16", 0 0, L_0x1df2040; 1 drivers +v0x1c0e690_0 .net *"_s20", 0 0, L_0x1df2410; 1 drivers +v0x1c0e770_0 .net *"_s24", 0 0, L_0x1df2740; 1 drivers +v0x1c0e850_0 .net *"_s28", 0 0, L_0x1df26d0; 1 drivers +v0x1c0e930_0 .net *"_s4", 0 0, L_0x1df16c0; 1 drivers +v0x1c0eaa0_0 .net *"_s8", 0 0, L_0x1df19d0; 1 drivers +v0x1c0eb80_0 .net "out", 7 0, L_0x1df2a50; alias, 1 drivers +L_0x1df1430 .part L_0x1df0f90, 0, 1; +L_0x1df1620 .part v0x1d6daa0_0, 0, 1; +L_0x1df1780 .part L_0x1df0f90, 1, 1; +L_0x1df18e0 .part v0x1d6daa0_0, 1, 1; +L_0x1df1a90 .part L_0x1df0f90, 2, 1; +L_0x1df1bf0 .part v0x1d6daa0_0, 2, 1; +L_0x1df1da0 .part L_0x1df0f90, 3, 1; +L_0x1df1f00 .part v0x1d6daa0_0, 3, 1; +L_0x1df2100 .part L_0x1df0f90, 4, 1; +L_0x1df2370 .part v0x1d6daa0_0, 4, 1; +L_0x1df2480 .part L_0x1df0f90, 5, 1; +L_0x1df25e0 .part v0x1d6daa0_0, 5, 1; +L_0x1df2800 .part L_0x1df0f90, 6, 1; +L_0x1df2960 .part v0x1d6daa0_0, 6, 1; +LS_0x1df2a50_0_0 .concat8 [ 1 1 1 1], L_0x1df1320, L_0x1df16c0, L_0x1df19d0, L_0x1df1ce0; +LS_0x1df2a50_0_4 .concat8 [ 1 1 1 1], L_0x1df2040, L_0x1df2410, L_0x1df2740, L_0x1df26d0; +L_0x1df2a50 .concat8 [ 4 4 0 0], LS_0x1df2a50_0_0, LS_0x1df2a50_0_4; +L_0x1df2e10 .part L_0x1df0f90, 7, 1; +L_0x1df3000 .part v0x1d6daa0_0, 7, 1; +S_0x1c0bd00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0bf10 .param/l "i" 0 4 54, +C4<00>; +L_0x1df1320/d .functor AND 1, L_0x1df1430, L_0x1df1620, C4<1>, C4<1>; +L_0x1df1320 .delay 1 (30000,30000,30000) L_0x1df1320/d; +v0x1c0bff0_0 .net *"_s0", 0 0, L_0x1df1430; 1 drivers +v0x1c0c0d0_0 .net *"_s1", 0 0, L_0x1df1620; 1 drivers +S_0x1c0c1b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0c3c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1df16c0/d .functor AND 1, L_0x1df1780, L_0x1df18e0, C4<1>, C4<1>; +L_0x1df16c0 .delay 1 (30000,30000,30000) L_0x1df16c0/d; +v0x1c0c480_0 .net *"_s0", 0 0, L_0x1df1780; 1 drivers +v0x1c0c560_0 .net *"_s1", 0 0, L_0x1df18e0; 1 drivers +S_0x1c0c640 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0c880 .param/l "i" 0 4 54, +C4<010>; +L_0x1df19d0/d .functor AND 1, L_0x1df1a90, L_0x1df1bf0, C4<1>, C4<1>; +L_0x1df19d0 .delay 1 (30000,30000,30000) L_0x1df19d0/d; +v0x1c0c920_0 .net *"_s0", 0 0, L_0x1df1a90; 1 drivers +v0x1c0ca00_0 .net *"_s1", 0 0, L_0x1df1bf0; 1 drivers +S_0x1c0cae0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0ccf0 .param/l "i" 0 4 54, +C4<011>; +L_0x1df1ce0/d .functor AND 1, L_0x1df1da0, L_0x1df1f00, C4<1>, C4<1>; +L_0x1df1ce0 .delay 1 (30000,30000,30000) L_0x1df1ce0/d; +v0x1c0cdb0_0 .net *"_s0", 0 0, L_0x1df1da0; 1 drivers +v0x1c0ce90_0 .net *"_s1", 0 0, L_0x1df1f00; 1 drivers +S_0x1c0cf70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0d1d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1df2040/d .functor AND 1, L_0x1df2100, L_0x1df2370, C4<1>, C4<1>; +L_0x1df2040 .delay 1 (30000,30000,30000) L_0x1df2040/d; +v0x1c0d290_0 .net *"_s0", 0 0, L_0x1df2100; 1 drivers +v0x1c0d370_0 .net *"_s1", 0 0, L_0x1df2370; 1 drivers +S_0x1c0d450 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0d660 .param/l "i" 0 4 54, +C4<0101>; +L_0x1df2410/d .functor AND 1, L_0x1df2480, L_0x1df25e0, C4<1>, C4<1>; +L_0x1df2410 .delay 1 (30000,30000,30000) L_0x1df2410/d; +v0x1c0d720_0 .net *"_s0", 0 0, L_0x1df2480; 1 drivers +v0x1c0d800_0 .net *"_s1", 0 0, L_0x1df25e0; 1 drivers +S_0x1c0d8e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0daf0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1df2740/d .functor AND 1, L_0x1df2800, L_0x1df2960, C4<1>, C4<1>; +L_0x1df2740 .delay 1 (30000,30000,30000) L_0x1df2740/d; +v0x1c0dbb0_0 .net *"_s0", 0 0, L_0x1df2800; 1 drivers +v0x1c0dc90_0 .net *"_s1", 0 0, L_0x1df2960; 1 drivers +S_0x1c0dd70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c0bac0; + .timescale -9 -12; +P_0x1c0df80 .param/l "i" 0 4 54, +C4<0111>; +L_0x1df26d0/d .functor AND 1, L_0x1df2e10, L_0x1df3000, C4<1>, C4<1>; +L_0x1df26d0 .delay 1 (30000,30000,30000) L_0x1df26d0/d; +v0x1c0e040_0 .net *"_s0", 0 0, L_0x1df2e10; 1 drivers +v0x1c0e120_0 .net *"_s1", 0 0, L_0x1df3000; 1 drivers +S_0x1c0ece0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c0b870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1df4a50/d .functor OR 1, L_0x1df4b10, L_0x1df4cc0, C4<0>, C4<0>; +L_0x1df4a50 .delay 1 (30000,30000,30000) L_0x1df4a50/d; +v0x1c10830_0 .net *"_s10", 0 0, L_0x1df4b10; 1 drivers +v0x1c10910_0 .net *"_s12", 0 0, L_0x1df4cc0; 1 drivers +v0x1c109f0_0 .net "in", 7 0, L_0x1df2a50; alias, 1 drivers +v0x1c10ac0_0 .net "ors", 1 0, L_0x1df4870; 1 drivers +v0x1c10b80_0 .net "out", 0 0, L_0x1df4a50; alias, 1 drivers +L_0x1df3c40 .part L_0x1df2a50, 0, 4; +L_0x1df4870 .concat8 [ 1 1 0 0], L_0x1df3930, L_0x1df4560; +L_0x1df49b0 .part L_0x1df2a50, 4, 4; +L_0x1df4b10 .part L_0x1df4870, 0, 1; +L_0x1df4cc0 .part L_0x1df4870, 1, 1; +S_0x1c0eea0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c0ece0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1df30f0/d .functor OR 1, L_0x1df31b0, L_0x1df3310, C4<0>, C4<0>; +L_0x1df30f0 .delay 1 (30000,30000,30000) L_0x1df30f0/d; +L_0x1df3540/d .functor OR 1, L_0x1df3650, L_0x1df37b0, C4<0>, C4<0>; +L_0x1df3540 .delay 1 (30000,30000,30000) L_0x1df3540/d; +L_0x1df3930/d .functor OR 1, L_0x1df39a0, L_0x1df3b50, C4<0>, C4<0>; +L_0x1df3930 .delay 1 (30000,30000,30000) L_0x1df3930/d; +v0x1c0f0f0_0 .net *"_s0", 0 0, L_0x1df30f0; 1 drivers +v0x1c0f1f0_0 .net *"_s10", 0 0, L_0x1df3650; 1 drivers +v0x1c0f2d0_0 .net *"_s12", 0 0, L_0x1df37b0; 1 drivers +v0x1c0f390_0 .net *"_s14", 0 0, L_0x1df39a0; 1 drivers +v0x1c0f470_0 .net *"_s16", 0 0, L_0x1df3b50; 1 drivers +v0x1c0f5a0_0 .net *"_s3", 0 0, L_0x1df31b0; 1 drivers +v0x1c0f680_0 .net *"_s5", 0 0, L_0x1df3310; 1 drivers +v0x1c0f760_0 .net *"_s6", 0 0, L_0x1df3540; 1 drivers +v0x1c0f840_0 .net "in", 3 0, L_0x1df3c40; 1 drivers +v0x1c0f9b0_0 .net "ors", 1 0, L_0x1df3450; 1 drivers +v0x1c0fa90_0 .net "out", 0 0, L_0x1df3930; 1 drivers +L_0x1df31b0 .part L_0x1df3c40, 0, 1; +L_0x1df3310 .part L_0x1df3c40, 1, 1; +L_0x1df3450 .concat8 [ 1 1 0 0], L_0x1df30f0, L_0x1df3540; +L_0x1df3650 .part L_0x1df3c40, 2, 1; +L_0x1df37b0 .part L_0x1df3c40, 3, 1; +L_0x1df39a0 .part L_0x1df3450, 0, 1; +L_0x1df3b50 .part L_0x1df3450, 1, 1; +S_0x1c0fbb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c0ece0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1df3d70/d .functor OR 1, L_0x1df3de0, L_0x1df3f40, C4<0>, C4<0>; +L_0x1df3d70 .delay 1 (30000,30000,30000) L_0x1df3d70/d; +L_0x1df4170/d .functor OR 1, L_0x1df4280, L_0x1df43e0, C4<0>, C4<0>; +L_0x1df4170 .delay 1 (30000,30000,30000) L_0x1df4170/d; +L_0x1df4560/d .functor OR 1, L_0x1df45d0, L_0x1df4780, C4<0>, C4<0>; +L_0x1df4560 .delay 1 (30000,30000,30000) L_0x1df4560/d; +v0x1c0fd70_0 .net *"_s0", 0 0, L_0x1df3d70; 1 drivers +v0x1c0fe70_0 .net *"_s10", 0 0, L_0x1df4280; 1 drivers +v0x1c0ff50_0 .net *"_s12", 0 0, L_0x1df43e0; 1 drivers +v0x1c10010_0 .net *"_s14", 0 0, L_0x1df45d0; 1 drivers +v0x1c100f0_0 .net *"_s16", 0 0, L_0x1df4780; 1 drivers +v0x1c10220_0 .net *"_s3", 0 0, L_0x1df3de0; 1 drivers +v0x1c10300_0 .net *"_s5", 0 0, L_0x1df3f40; 1 drivers +v0x1c103e0_0 .net *"_s6", 0 0, L_0x1df4170; 1 drivers +v0x1c104c0_0 .net "in", 3 0, L_0x1df49b0; 1 drivers +v0x1c10630_0 .net "ors", 1 0, L_0x1df4080; 1 drivers +v0x1c10710_0 .net "out", 0 0, L_0x1df4560; 1 drivers +L_0x1df3de0 .part L_0x1df49b0, 0, 1; +L_0x1df3f40 .part L_0x1df49b0, 1, 1; +L_0x1df4080 .concat8 [ 1 1 0 0], L_0x1df3d70, L_0x1df4170; +L_0x1df4280 .part L_0x1df49b0, 2, 1; +L_0x1df43e0 .part L_0x1df49b0, 3, 1; +L_0x1df45d0 .part L_0x1df4080, 0, 1; +L_0x1df4780 .part L_0x1df4080, 1, 1; +S_0x1c11020 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c04910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1df0300/d .functor XNOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; +L_0x1df0300 .delay 1 (20000,20000,20000) L_0x1df0300/d; +L_0x1df0570/d .functor AND 1, L_0x1df88f0, L_0x1def1f0, C4<1>, C4<1>; +L_0x1df0570 .delay 1 (30000,30000,30000) L_0x1df0570/d; +L_0x1df05e0/d .functor AND 1, L_0x1df0300, L_0x1deef50, C4<1>, C4<1>; +L_0x1df05e0 .delay 1 (30000,30000,30000) L_0x1df05e0/d; +L_0x1df0740/d .functor OR 1, L_0x1df05e0, L_0x1df0570, C4<0>, C4<0>; +L_0x1df0740 .delay 1 (30000,30000,30000) L_0x1df0740/d; +v0x1c112d0_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers +v0x1c113c0_0 .net "a_", 0 0, L_0x1def090; alias, 1 drivers +v0x1c11480_0 .net "b", 0 0, L_0x1deeeb0; alias, 1 drivers +v0x1c11570_0 .net "b_", 0 0, L_0x1def1f0; alias, 1 drivers +v0x1c11610_0 .net "carryin", 0 0, L_0x1deef50; alias, 1 drivers +v0x1c11750_0 .net "eq", 0 0, L_0x1df0300; 1 drivers +v0x1c11810_0 .net "lt", 0 0, L_0x1df0570; 1 drivers +v0x1c118d0_0 .net "out", 0 0, L_0x1df0740; 1 drivers +v0x1c11990_0 .net "w0", 0 0, L_0x1df05e0; 1 drivers +S_0x1c11be0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c04910; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1df00e0/d .functor OR 1, L_0x1defbe0, L_0x1c12e40, C4<0>, C4<0>; +L_0x1df00e0 .delay 1 (30000,30000,30000) L_0x1df00e0/d; +v0x1c129d0_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers +v0x1c12b20_0 .net "b", 0 0, L_0x1def1f0; alias, 1 drivers +v0x1c12be0_0 .net "c1", 0 0, L_0x1defbe0; 1 drivers +v0x1c12c80_0 .net "c2", 0 0, L_0x1c12e40; 1 drivers +v0x1c12d50_0 .net "carryin", 0 0, L_0x1deef50; alias, 1 drivers +v0x1c12ed0_0 .net "carryout", 0 0, L_0x1df00e0; 1 drivers +v0x1c12f70_0 .net "s1", 0 0, L_0x1defb20; 1 drivers +v0x1c13010_0 .net "sum", 0 0, L_0x1defd40; 1 drivers +S_0x1c11e30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c11be0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1defb20/d .functor XOR 1, L_0x1df88f0, L_0x1def1f0, C4<0>, C4<0>; +L_0x1defb20 .delay 1 (30000,30000,30000) L_0x1defb20/d; +L_0x1defbe0/d .functor AND 1, L_0x1df88f0, L_0x1def1f0, C4<1>, C4<1>; +L_0x1defbe0 .delay 1 (30000,30000,30000) L_0x1defbe0/d; +v0x1c12090_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers +v0x1c12150_0 .net "b", 0 0, L_0x1def1f0; alias, 1 drivers +v0x1c12210_0 .net "carryout", 0 0, L_0x1defbe0; alias, 1 drivers +v0x1c122b0_0 .net "sum", 0 0, L_0x1defb20; alias, 1 drivers +S_0x1c123e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c11be0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1defd40/d .functor XOR 1, L_0x1defb20, L_0x1deef50, C4<0>, C4<0>; +L_0x1defd40 .delay 1 (30000,30000,30000) L_0x1defd40/d; +L_0x1c12e40/d .functor AND 1, L_0x1defb20, L_0x1deef50, C4<1>, C4<1>; +L_0x1c12e40 .delay 1 (30000,30000,30000) L_0x1c12e40/d; +v0x1c12640_0 .net "a", 0 0, L_0x1defb20; alias, 1 drivers +v0x1c12710_0 .net "b", 0 0, L_0x1deef50; alias, 1 drivers +v0x1c127b0_0 .net "carryout", 0 0, L_0x1c12e40; alias, 1 drivers +v0x1c12880_0 .net "sum", 0 0, L_0x1defd40; alias, 1 drivers +S_0x1c14430 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c04640; + .timescale -9 -12; +L_0x7f72592daeb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592daf00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1df8990/d .functor OR 1, L_0x7f72592daeb8, L_0x7f72592daf00, C4<0>, C4<0>; +L_0x1df8990 .delay 1 (30000,30000,30000) L_0x1df8990/d; +v0x1c14620_0 .net/2u *"_s0", 0 0, L_0x7f72592daeb8; 1 drivers +v0x1c14700_0 .net/2u *"_s2", 0 0, L_0x7f72592daf00; 1 drivers +S_0x1c147e0 .scope generate, "alu_slices[14]" "alu_slices[14]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c149f0 .param/l "i" 0 3 37, +C4<01110>; +S_0x1c14ab0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c147e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1df8ca0/d .functor NOT 1, L_0x1e024d0, C4<0>, C4<0>, C4<0>; +L_0x1df8ca0 .delay 1 (10000,10000,10000) L_0x1df8ca0/d; +L_0x1df8e00/d .functor NOT 1, L_0x1db4230, C4<0>, C4<0>, C4<0>; +L_0x1df8e00 .delay 1 (10000,10000,10000) L_0x1df8e00/d; +L_0x1df9e50/d .functor XOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; +L_0x1df9e50 .delay 1 (30000,30000,30000) L_0x1df9e50/d; +L_0x7f72592daf48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592daf90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1dfa3f0/d .functor OR 1, L_0x7f72592daf48, L_0x7f72592daf90, C4<0>, C4<0>; +L_0x1dfa3f0 .delay 1 (30000,30000,30000) L_0x1dfa3f0/d; +L_0x1dfa5f0/d .functor AND 1, L_0x1e024d0, L_0x1db4230, C4<1>, C4<1>; +L_0x1dfa5f0 .delay 1 (30000,30000,30000) L_0x1dfa5f0/d; +L_0x1dfa6b0/d .functor NAND 1, L_0x1e024d0, L_0x1db4230, C4<1>, C4<1>; +L_0x1dfa6b0 .delay 1 (20000,20000,20000) L_0x1dfa6b0/d; +L_0x1dfa810/d .functor XOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; +L_0x1dfa810 .delay 1 (20000,20000,20000) L_0x1dfa810/d; +L_0x1dfacc0/d .functor OR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; +L_0x1dfacc0 .delay 1 (30000,30000,30000) L_0x1dfacc0/d; +L_0x1e023d0/d .functor NOT 1, L_0x1dfe630, C4<0>, C4<0>, C4<0>; +L_0x1e023d0 .delay 1 (10000,10000,10000) L_0x1e023d0/d; +v0x1c231e0_0 .net "A", 0 0, L_0x1e024d0; 1 drivers +v0x1c232a0_0 .net "A_", 0 0, L_0x1df8ca0; 1 drivers +v0x1c23360_0 .net "B", 0 0, L_0x1db4230; 1 drivers +v0x1c23430_0 .net "B_", 0 0, L_0x1df8e00; 1 drivers +v0x1c234d0_0 .net *"_s12", 0 0, L_0x1dfa3f0; 1 drivers +v0x1c235c0_0 .net/2s *"_s14", 0 0, L_0x7f72592daf48; 1 drivers +v0x1c23680_0 .net/2s *"_s16", 0 0, L_0x7f72592daf90; 1 drivers +v0x1c23760_0 .net *"_s18", 0 0, L_0x1dfa5f0; 1 drivers +v0x1c23840_0 .net *"_s20", 0 0, L_0x1dfa6b0; 1 drivers +v0x1c239b0_0 .net *"_s22", 0 0, L_0x1dfa810; 1 drivers +v0x1c23a90_0 .net *"_s24", 0 0, L_0x1dfacc0; 1 drivers +o0x7f7259376d28 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c23b70_0 name=_s30 +o0x7f7259376d58 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c23c50_0 name=_s32 +v0x1c23d30_0 .net *"_s8", 0 0, L_0x1df9e50; 1 drivers +v0x1c23e10_0 .net "carryin", 0 0, L_0x1db43e0; 1 drivers +v0x1c23eb0_0 .net "carryout", 0 0, L_0x1e02070; 1 drivers +v0x1c23f50_0 .net "carryouts", 7 0, L_0x1ec0250; 1 drivers +v0x1c24100_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c241a0_0 .net "result", 0 0, L_0x1dfe630; 1 drivers +v0x1c24290_0 .net "results", 7 0, L_0x1dfaa90; 1 drivers +v0x1c243a0_0 .net "zero", 0 0, L_0x1e023d0; 1 drivers +LS_0x1dfaa90_0_0 .concat8 [ 1 1 1 1], L_0x1df9320, L_0x1df9950, L_0x1df9e50, L_0x1dfa3f0; +LS_0x1dfaa90_0_4 .concat8 [ 1 1 1 1], L_0x1dfa5f0, L_0x1dfa6b0, L_0x1dfa810, L_0x1dfacc0; +L_0x1dfaa90 .concat8 [ 4 4 0 0], LS_0x1dfaa90_0_0, LS_0x1dfaa90_0_4; +LS_0x1ec0250_0_0 .concat [ 1 1 1 1], L_0x1df95d0, L_0x1df9cf0, o0x7f7259376d28, L_0x1dfa240; +LS_0x1ec0250_0_4 .concat [ 4 0 0 0], o0x7f7259376d58; +L_0x1ec0250 .concat [ 4 4 0 0], LS_0x1ec0250_0_0, LS_0x1ec0250_0_4; +S_0x1c14d30 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c14ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1df95d0/d .functor OR 1, L_0x1df90b0, L_0x1df9470, C4<0>, C4<0>; +L_0x1df95d0 .delay 1 (30000,30000,30000) L_0x1df95d0/d; +v0x1c15b60_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers +v0x1c15c20_0 .net "b", 0 0, L_0x1db4230; alias, 1 drivers +v0x1c15cf0_0 .net "c1", 0 0, L_0x1df90b0; 1 drivers +v0x1c15df0_0 .net "c2", 0 0, L_0x1df9470; 1 drivers +v0x1c15ec0_0 .net "carryin", 0 0, L_0x1db43e0; alias, 1 drivers +v0x1c15fb0_0 .net "carryout", 0 0, L_0x1df95d0; 1 drivers +v0x1c16050_0 .net "s1", 0 0, L_0x1df8ff0; 1 drivers +v0x1c16140_0 .net "sum", 0 0, L_0x1df9320; 1 drivers +S_0x1c14fa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c14d30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1df8ff0/d .functor XOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; +L_0x1df8ff0 .delay 1 (30000,30000,30000) L_0x1df8ff0/d; +L_0x1df90b0/d .functor AND 1, L_0x1e024d0, L_0x1db4230, C4<1>, C4<1>; +L_0x1df90b0 .delay 1 (30000,30000,30000) L_0x1df90b0/d; +v0x1c15200_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers +v0x1c152e0_0 .net "b", 0 0, L_0x1db4230; alias, 1 drivers +v0x1c153a0_0 .net "carryout", 0 0, L_0x1df90b0; alias, 1 drivers +v0x1c15440_0 .net "sum", 0 0, L_0x1df8ff0; alias, 1 drivers +S_0x1c15580 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c14d30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1df9320/d .functor XOR 1, L_0x1df8ff0, L_0x1db43e0, C4<0>, C4<0>; +L_0x1df9320 .delay 1 (30000,30000,30000) L_0x1df9320/d; +L_0x1df9470/d .functor AND 1, L_0x1df8ff0, L_0x1db43e0, C4<1>, C4<1>; +L_0x1df9470 .delay 1 (30000,30000,30000) L_0x1df9470/d; +v0x1c157e0_0 .net "a", 0 0, L_0x1df8ff0; alias, 1 drivers +v0x1c15880_0 .net "b", 0 0, L_0x1db43e0; alias, 1 drivers +v0x1c15920_0 .net "carryout", 0 0, L_0x1df9470; alias, 1 drivers +v0x1c159f0_0 .net "sum", 0 0, L_0x1df9320; alias, 1 drivers +S_0x1c16210 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c14ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c1b600_0 .net "ands", 7 0, L_0x1e00070; 1 drivers +v0x1c1b710_0 .net "in", 7 0, L_0x1ec0250; alias, 1 drivers +v0x1c1b7d0_0 .net "out", 0 0, L_0x1e02070; alias, 1 drivers +v0x1c1b8a0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c16430 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c16210; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c18b60_0 .net "A", 7 0, L_0x1ec0250; alias, 1 drivers +v0x1c18c60_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c18d20_0 .net *"_s0", 0 0, L_0x1dfe990; 1 drivers +v0x1c18de0_0 .net *"_s12", 0 0, L_0x1dff300; 1 drivers +v0x1c18ec0_0 .net *"_s16", 0 0, L_0x1dff660; 1 drivers +v0x1c18ff0_0 .net *"_s20", 0 0, L_0x1dff970; 1 drivers +v0x1c190d0_0 .net *"_s24", 0 0, L_0x1dffd60; 1 drivers +v0x1c191b0_0 .net *"_s28", 0 0, L_0x1dffcf0; 1 drivers +v0x1c19290_0 .net *"_s4", 0 0, L_0x1dfeca0; 1 drivers +v0x1c19400_0 .net *"_s8", 0 0, L_0x1dfeff0; 1 drivers +v0x1c194e0_0 .net "out", 7 0, L_0x1e00070; alias, 1 drivers +L_0x1dfea50 .part L_0x1ec0250, 0, 1; +L_0x1dfebb0 .part v0x1d6daa0_0, 0, 1; +L_0x1dfed60 .part L_0x1ec0250, 1, 1; +L_0x1dfef50 .part v0x1d6daa0_0, 1, 1; +L_0x1dff0b0 .part L_0x1ec0250, 2, 1; +L_0x1dff210 .part v0x1d6daa0_0, 2, 1; +L_0x1dff3c0 .part L_0x1ec0250, 3, 1; +L_0x1dff520 .part v0x1d6daa0_0, 3, 1; +L_0x1dff720 .part L_0x1ec0250, 4, 1; +L_0x1dff880 .part v0x1d6daa0_0, 4, 1; +L_0x1dff9e0 .part L_0x1ec0250, 5, 1; +L_0x1dffc50 .part v0x1d6daa0_0, 5, 1; +L_0x1dffe20 .part L_0x1ec0250, 6, 1; +L_0x1dfff80 .part v0x1d6daa0_0, 6, 1; +LS_0x1e00070_0_0 .concat8 [ 1 1 1 1], L_0x1dfe990, L_0x1dfeca0, L_0x1dfeff0, L_0x1dff300; +LS_0x1e00070_0_4 .concat8 [ 1 1 1 1], L_0x1dff660, L_0x1dff970, L_0x1dffd60, L_0x1dffcf0; +L_0x1e00070 .concat8 [ 4 4 0 0], LS_0x1e00070_0_0, LS_0x1e00070_0_4; +L_0x1e00430 .part L_0x1ec0250, 7, 1; +L_0x1e00620 .part v0x1d6daa0_0, 7, 1; +S_0x1c16690 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c168a0 .param/l "i" 0 4 54, +C4<00>; +L_0x1dfe990/d .functor AND 1, L_0x1dfea50, L_0x1dfebb0, C4<1>, C4<1>; +L_0x1dfe990 .delay 1 (30000,30000,30000) L_0x1dfe990/d; +v0x1c16980_0 .net *"_s0", 0 0, L_0x1dfea50; 1 drivers +v0x1c16a60_0 .net *"_s1", 0 0, L_0x1dfebb0; 1 drivers +S_0x1c16b40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c16d50 .param/l "i" 0 4 54, +C4<01>; +L_0x1dfeca0/d .functor AND 1, L_0x1dfed60, L_0x1dfef50, C4<1>, C4<1>; +L_0x1dfeca0 .delay 1 (30000,30000,30000) L_0x1dfeca0/d; +v0x1c16e10_0 .net *"_s0", 0 0, L_0x1dfed60; 1 drivers +v0x1c16ef0_0 .net *"_s1", 0 0, L_0x1dfef50; 1 drivers +S_0x1c16fd0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c171e0 .param/l "i" 0 4 54, +C4<010>; +L_0x1dfeff0/d .functor AND 1, L_0x1dff0b0, L_0x1dff210, C4<1>, C4<1>; +L_0x1dfeff0 .delay 1 (30000,30000,30000) L_0x1dfeff0/d; +v0x1c17280_0 .net *"_s0", 0 0, L_0x1dff0b0; 1 drivers +v0x1c17360_0 .net *"_s1", 0 0, L_0x1dff210; 1 drivers +S_0x1c17440 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c17650 .param/l "i" 0 4 54, +C4<011>; +L_0x1dff300/d .functor AND 1, L_0x1dff3c0, L_0x1dff520, C4<1>, C4<1>; +L_0x1dff300 .delay 1 (30000,30000,30000) L_0x1dff300/d; +v0x1c17710_0 .net *"_s0", 0 0, L_0x1dff3c0; 1 drivers +v0x1c177f0_0 .net *"_s1", 0 0, L_0x1dff520; 1 drivers +S_0x1c178d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c17b30 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dff660/d .functor AND 1, L_0x1dff720, L_0x1dff880, C4<1>, C4<1>; +L_0x1dff660 .delay 1 (30000,30000,30000) L_0x1dff660/d; +v0x1c17bf0_0 .net *"_s0", 0 0, L_0x1dff720; 1 drivers +v0x1c17cd0_0 .net *"_s1", 0 0, L_0x1dff880; 1 drivers +S_0x1c17db0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c17fc0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dff970/d .functor AND 1, L_0x1dff9e0, L_0x1dffc50, C4<1>, C4<1>; +L_0x1dff970 .delay 1 (30000,30000,30000) L_0x1dff970/d; +v0x1c18080_0 .net *"_s0", 0 0, L_0x1dff9e0; 1 drivers +v0x1c18160_0 .net *"_s1", 0 0, L_0x1dffc50; 1 drivers +S_0x1c18240 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c18450 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dffd60/d .functor AND 1, L_0x1dffe20, L_0x1dfff80, C4<1>, C4<1>; +L_0x1dffd60 .delay 1 (30000,30000,30000) L_0x1dffd60/d; +v0x1c18510_0 .net *"_s0", 0 0, L_0x1dffe20; 1 drivers +v0x1c185f0_0 .net *"_s1", 0 0, L_0x1dfff80; 1 drivers +S_0x1c186d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c16430; + .timescale -9 -12; +P_0x1c188e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dffcf0/d .functor AND 1, L_0x1e00430, L_0x1e00620, C4<1>, C4<1>; +L_0x1dffcf0 .delay 1 (30000,30000,30000) L_0x1dffcf0/d; +v0x1c189a0_0 .net *"_s0", 0 0, L_0x1e00430; 1 drivers +v0x1c18a80_0 .net *"_s1", 0 0, L_0x1e00620; 1 drivers +S_0x1c19640 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c16210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e02070/d .functor OR 1, L_0x1e02130, L_0x1e022e0, C4<0>, C4<0>; +L_0x1e02070 .delay 1 (30000,30000,30000) L_0x1e02070/d; +v0x1c1b190_0 .net *"_s10", 0 0, L_0x1e02130; 1 drivers +v0x1c1b270_0 .net *"_s12", 0 0, L_0x1e022e0; 1 drivers +v0x1c1b350_0 .net "in", 7 0, L_0x1e00070; alias, 1 drivers +v0x1c1b420_0 .net "ors", 1 0, L_0x1e01e90; 1 drivers +v0x1c1b4e0_0 .net "out", 0 0, L_0x1e02070; alias, 1 drivers +L_0x1e01260 .part L_0x1e00070, 0, 4; +L_0x1e01e90 .concat8 [ 1 1 0 0], L_0x1e00f50, L_0x1e01b80; +L_0x1e01fd0 .part L_0x1e00070, 4, 4; +L_0x1e02130 .part L_0x1e01e90, 0, 1; +L_0x1e022e0 .part L_0x1e01e90, 1, 1; +S_0x1c19800 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c19640; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e00710/d .functor OR 1, L_0x1e007d0, L_0x1e00930, C4<0>, C4<0>; +L_0x1e00710 .delay 1 (30000,30000,30000) L_0x1e00710/d; +L_0x1e00b60/d .functor OR 1, L_0x1e00c70, L_0x1e00dd0, C4<0>, C4<0>; +L_0x1e00b60 .delay 1 (30000,30000,30000) L_0x1e00b60/d; +L_0x1e00f50/d .functor OR 1, L_0x1e00fc0, L_0x1e01170, C4<0>, C4<0>; +L_0x1e00f50 .delay 1 (30000,30000,30000) L_0x1e00f50/d; +v0x1c19a50_0 .net *"_s0", 0 0, L_0x1e00710; 1 drivers +v0x1c19b50_0 .net *"_s10", 0 0, L_0x1e00c70; 1 drivers +v0x1c19c30_0 .net *"_s12", 0 0, L_0x1e00dd0; 1 drivers +v0x1c19cf0_0 .net *"_s14", 0 0, L_0x1e00fc0; 1 drivers +v0x1c19dd0_0 .net *"_s16", 0 0, L_0x1e01170; 1 drivers +v0x1c19f00_0 .net *"_s3", 0 0, L_0x1e007d0; 1 drivers +v0x1c19fe0_0 .net *"_s5", 0 0, L_0x1e00930; 1 drivers +v0x1c1a0c0_0 .net *"_s6", 0 0, L_0x1e00b60; 1 drivers +v0x1c1a1a0_0 .net "in", 3 0, L_0x1e01260; 1 drivers +v0x1c1a310_0 .net "ors", 1 0, L_0x1e00a70; 1 drivers +v0x1c1a3f0_0 .net "out", 0 0, L_0x1e00f50; 1 drivers +L_0x1e007d0 .part L_0x1e01260, 0, 1; +L_0x1e00930 .part L_0x1e01260, 1, 1; +L_0x1e00a70 .concat8 [ 1 1 0 0], L_0x1e00710, L_0x1e00b60; +L_0x1e00c70 .part L_0x1e01260, 2, 1; +L_0x1e00dd0 .part L_0x1e01260, 3, 1; +L_0x1e00fc0 .part L_0x1e00a70, 0, 1; +L_0x1e01170 .part L_0x1e00a70, 1, 1; +S_0x1c1a510 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c19640; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e01390/d .functor OR 1, L_0x1e01400, L_0x1e01560, C4<0>, C4<0>; +L_0x1e01390 .delay 1 (30000,30000,30000) L_0x1e01390/d; +L_0x1e01790/d .functor OR 1, L_0x1e018a0, L_0x1e01a00, C4<0>, C4<0>; +L_0x1e01790 .delay 1 (30000,30000,30000) L_0x1e01790/d; +L_0x1e01b80/d .functor OR 1, L_0x1e01bf0, L_0x1e01da0, C4<0>, C4<0>; +L_0x1e01b80 .delay 1 (30000,30000,30000) L_0x1e01b80/d; +v0x1c1a6d0_0 .net *"_s0", 0 0, L_0x1e01390; 1 drivers +v0x1c1a7d0_0 .net *"_s10", 0 0, L_0x1e018a0; 1 drivers +v0x1c1a8b0_0 .net *"_s12", 0 0, L_0x1e01a00; 1 drivers +v0x1c1a970_0 .net *"_s14", 0 0, L_0x1e01bf0; 1 drivers +v0x1c1aa50_0 .net *"_s16", 0 0, L_0x1e01da0; 1 drivers +v0x1c1ab80_0 .net *"_s3", 0 0, L_0x1e01400; 1 drivers +v0x1c1ac60_0 .net *"_s5", 0 0, L_0x1e01560; 1 drivers +v0x1c1ad40_0 .net *"_s6", 0 0, L_0x1e01790; 1 drivers +v0x1c1ae20_0 .net "in", 3 0, L_0x1e01fd0; 1 drivers +v0x1c1af90_0 .net "ors", 1 0, L_0x1e016a0; 1 drivers +v0x1c1b070_0 .net "out", 0 0, L_0x1e01b80; 1 drivers +L_0x1e01400 .part L_0x1e01fd0, 0, 1; +L_0x1e01560 .part L_0x1e01fd0, 1, 1; +L_0x1e016a0 .concat8 [ 1 1 0 0], L_0x1e01390, L_0x1e01790; +L_0x1e018a0 .part L_0x1e01fd0, 2, 1; +L_0x1e01a00 .part L_0x1e01fd0, 3, 1; +L_0x1e01bf0 .part L_0x1e016a0, 0, 1; +L_0x1e01da0 .part L_0x1e016a0, 1, 1; +S_0x1c1b980 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c14ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c20db0_0 .net "ands", 7 0, L_0x1dfc630; 1 drivers +v0x1c20ec0_0 .net "in", 7 0, L_0x1dfaa90; alias, 1 drivers +v0x1c20f80_0 .net "out", 0 0, L_0x1dfe630; alias, 1 drivers +v0x1c21050_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c1bbd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c1b980; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c1e310_0 .net "A", 7 0, L_0x1dfaa90; alias, 1 drivers +v0x1c1e410_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c1e4d0_0 .net *"_s0", 0 0, L_0x1dfae20; 1 drivers +v0x1c1e590_0 .net *"_s12", 0 0, L_0x1dfb7e0; 1 drivers +v0x1c1e670_0 .net *"_s16", 0 0, L_0x1dfbb40; 1 drivers +v0x1c1e7a0_0 .net *"_s20", 0 0, L_0x1dfbf70; 1 drivers +v0x1c1e880_0 .net *"_s24", 0 0, L_0x1dfc2a0; 1 drivers +v0x1c1e960_0 .net *"_s28", 0 0, L_0x1dfc230; 1 drivers +v0x1c1ea40_0 .net *"_s4", 0 0, L_0x1dfb1c0; 1 drivers +v0x1c1ebb0_0 .net *"_s8", 0 0, L_0x1dfb4d0; 1 drivers +v0x1c1ec90_0 .net "out", 7 0, L_0x1dfc630; alias, 1 drivers +L_0x1dfaf30 .part L_0x1dfaa90, 0, 1; +L_0x1dfb120 .part v0x1d6daa0_0, 0, 1; +L_0x1dfb280 .part L_0x1dfaa90, 1, 1; +L_0x1dfb3e0 .part v0x1d6daa0_0, 1, 1; +L_0x1dfb590 .part L_0x1dfaa90, 2, 1; +L_0x1dfb6f0 .part v0x1d6daa0_0, 2, 1; +L_0x1dfb8a0 .part L_0x1dfaa90, 3, 1; +L_0x1dfba00 .part v0x1d6daa0_0, 3, 1; +L_0x1dfbc00 .part L_0x1dfaa90, 4, 1; +L_0x1dfbe70 .part v0x1d6daa0_0, 4, 1; +L_0x1dfbfe0 .part L_0x1dfaa90, 5, 1; +L_0x1dfc140 .part v0x1d6daa0_0, 5, 1; +L_0x1dfc360 .part L_0x1dfaa90, 6, 1; +L_0x1dfc4c0 .part v0x1d6daa0_0, 6, 1; +LS_0x1dfc630_0_0 .concat8 [ 1 1 1 1], L_0x1dfae20, L_0x1dfb1c0, L_0x1dfb4d0, L_0x1dfb7e0; +LS_0x1dfc630_0_4 .concat8 [ 1 1 1 1], L_0x1dfbb40, L_0x1dfbf70, L_0x1dfc2a0, L_0x1dfc230; +L_0x1dfc630 .concat8 [ 4 4 0 0], LS_0x1dfc630_0_0, LS_0x1dfc630_0_4; +L_0x1dfc9f0 .part L_0x1dfaa90, 7, 1; +L_0x1dfcbe0 .part v0x1d6daa0_0, 7, 1; +S_0x1c1be10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1c020 .param/l "i" 0 4 54, +C4<00>; +L_0x1dfae20/d .functor AND 1, L_0x1dfaf30, L_0x1dfb120, C4<1>, C4<1>; +L_0x1dfae20 .delay 1 (30000,30000,30000) L_0x1dfae20/d; +v0x1c1c100_0 .net *"_s0", 0 0, L_0x1dfaf30; 1 drivers +v0x1c1c1e0_0 .net *"_s1", 0 0, L_0x1dfb120; 1 drivers +S_0x1c1c2c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1c4d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1dfb1c0/d .functor AND 1, L_0x1dfb280, L_0x1dfb3e0, C4<1>, C4<1>; +L_0x1dfb1c0 .delay 1 (30000,30000,30000) L_0x1dfb1c0/d; +v0x1c1c590_0 .net *"_s0", 0 0, L_0x1dfb280; 1 drivers +v0x1c1c670_0 .net *"_s1", 0 0, L_0x1dfb3e0; 1 drivers +S_0x1c1c750 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1c990 .param/l "i" 0 4 54, +C4<010>; +L_0x1dfb4d0/d .functor AND 1, L_0x1dfb590, L_0x1dfb6f0, C4<1>, C4<1>; +L_0x1dfb4d0 .delay 1 (30000,30000,30000) L_0x1dfb4d0/d; +v0x1c1ca30_0 .net *"_s0", 0 0, L_0x1dfb590; 1 drivers +v0x1c1cb10_0 .net *"_s1", 0 0, L_0x1dfb6f0; 1 drivers +S_0x1c1cbf0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1ce00 .param/l "i" 0 4 54, +C4<011>; +L_0x1dfb7e0/d .functor AND 1, L_0x1dfb8a0, L_0x1dfba00, C4<1>, C4<1>; +L_0x1dfb7e0 .delay 1 (30000,30000,30000) L_0x1dfb7e0/d; +v0x1c1cec0_0 .net *"_s0", 0 0, L_0x1dfb8a0; 1 drivers +v0x1c1cfa0_0 .net *"_s1", 0 0, L_0x1dfba00; 1 drivers +S_0x1c1d080 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1d2e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1dfbb40/d .functor AND 1, L_0x1dfbc00, L_0x1dfbe70, C4<1>, C4<1>; +L_0x1dfbb40 .delay 1 (30000,30000,30000) L_0x1dfbb40/d; +v0x1c1d3a0_0 .net *"_s0", 0 0, L_0x1dfbc00; 1 drivers +v0x1c1d480_0 .net *"_s1", 0 0, L_0x1dfbe70; 1 drivers +S_0x1c1d560 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1d770 .param/l "i" 0 4 54, +C4<0101>; +L_0x1dfbf70/d .functor AND 1, L_0x1dfbfe0, L_0x1dfc140, C4<1>, C4<1>; +L_0x1dfbf70 .delay 1 (30000,30000,30000) L_0x1dfbf70/d; +v0x1c1d830_0 .net *"_s0", 0 0, L_0x1dfbfe0; 1 drivers +v0x1c1d910_0 .net *"_s1", 0 0, L_0x1dfc140; 1 drivers +S_0x1c1d9f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1dc00 .param/l "i" 0 4 54, +C4<0110>; +L_0x1dfc2a0/d .functor AND 1, L_0x1dfc360, L_0x1dfc4c0, C4<1>, C4<1>; +L_0x1dfc2a0 .delay 1 (30000,30000,30000) L_0x1dfc2a0/d; +v0x1c1dcc0_0 .net *"_s0", 0 0, L_0x1dfc360; 1 drivers +v0x1c1dda0_0 .net *"_s1", 0 0, L_0x1dfc4c0; 1 drivers +S_0x1c1de80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c1bbd0; + .timescale -9 -12; +P_0x1c1e090 .param/l "i" 0 4 54, +C4<0111>; +L_0x1dfc230/d .functor AND 1, L_0x1dfc9f0, L_0x1dfcbe0, C4<1>, C4<1>; +L_0x1dfc230 .delay 1 (30000,30000,30000) L_0x1dfc230/d; +v0x1c1e150_0 .net *"_s0", 0 0, L_0x1dfc9f0; 1 drivers +v0x1c1e230_0 .net *"_s1", 0 0, L_0x1dfcbe0; 1 drivers +S_0x1c1edf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c1b980; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1dfe630/d .functor OR 1, L_0x1dfe6f0, L_0x1dfe8a0, C4<0>, C4<0>; +L_0x1dfe630 .delay 1 (30000,30000,30000) L_0x1dfe630/d; +v0x1c20940_0 .net *"_s10", 0 0, L_0x1dfe6f0; 1 drivers +v0x1c20a20_0 .net *"_s12", 0 0, L_0x1dfe8a0; 1 drivers +v0x1c20b00_0 .net "in", 7 0, L_0x1dfc630; alias, 1 drivers +v0x1c20bd0_0 .net "ors", 1 0, L_0x1dfe450; 1 drivers +v0x1c20c90_0 .net "out", 0 0, L_0x1dfe630; alias, 1 drivers +L_0x1dfd820 .part L_0x1dfc630, 0, 4; +L_0x1dfe450 .concat8 [ 1 1 0 0], L_0x1dfd510, L_0x1dfe140; +L_0x1dfe590 .part L_0x1dfc630, 4, 4; +L_0x1dfe6f0 .part L_0x1dfe450, 0, 1; +L_0x1dfe8a0 .part L_0x1dfe450, 1, 1; +S_0x1c1efb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c1edf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dfccd0/d .functor OR 1, L_0x1dfcd90, L_0x1dfcef0, C4<0>, C4<0>; +L_0x1dfccd0 .delay 1 (30000,30000,30000) L_0x1dfccd0/d; +L_0x1dfd120/d .functor OR 1, L_0x1dfd230, L_0x1dfd390, C4<0>, C4<0>; +L_0x1dfd120 .delay 1 (30000,30000,30000) L_0x1dfd120/d; +L_0x1dfd510/d .functor OR 1, L_0x1dfd580, L_0x1dfd730, C4<0>, C4<0>; +L_0x1dfd510 .delay 1 (30000,30000,30000) L_0x1dfd510/d; +v0x1c1f200_0 .net *"_s0", 0 0, L_0x1dfccd0; 1 drivers +v0x1c1f300_0 .net *"_s10", 0 0, L_0x1dfd230; 1 drivers +v0x1c1f3e0_0 .net *"_s12", 0 0, L_0x1dfd390; 1 drivers +v0x1c1f4a0_0 .net *"_s14", 0 0, L_0x1dfd580; 1 drivers +v0x1c1f580_0 .net *"_s16", 0 0, L_0x1dfd730; 1 drivers +v0x1c1f6b0_0 .net *"_s3", 0 0, L_0x1dfcd90; 1 drivers +v0x1c1f790_0 .net *"_s5", 0 0, L_0x1dfcef0; 1 drivers +v0x1c1f870_0 .net *"_s6", 0 0, L_0x1dfd120; 1 drivers +v0x1c1f950_0 .net "in", 3 0, L_0x1dfd820; 1 drivers +v0x1c1fac0_0 .net "ors", 1 0, L_0x1dfd030; 1 drivers +v0x1c1fba0_0 .net "out", 0 0, L_0x1dfd510; 1 drivers +L_0x1dfcd90 .part L_0x1dfd820, 0, 1; +L_0x1dfcef0 .part L_0x1dfd820, 1, 1; +L_0x1dfd030 .concat8 [ 1 1 0 0], L_0x1dfccd0, L_0x1dfd120; +L_0x1dfd230 .part L_0x1dfd820, 2, 1; +L_0x1dfd390 .part L_0x1dfd820, 3, 1; +L_0x1dfd580 .part L_0x1dfd030, 0, 1; +L_0x1dfd730 .part L_0x1dfd030, 1, 1; +S_0x1c1fcc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c1edf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1dfd950/d .functor OR 1, L_0x1dfd9c0, L_0x1dfdb20, C4<0>, C4<0>; +L_0x1dfd950 .delay 1 (30000,30000,30000) L_0x1dfd950/d; +L_0x1dfdd50/d .functor OR 1, L_0x1dfde60, L_0x1dfdfc0, C4<0>, C4<0>; +L_0x1dfdd50 .delay 1 (30000,30000,30000) L_0x1dfdd50/d; +L_0x1dfe140/d .functor OR 1, L_0x1dfe1b0, L_0x1dfe360, C4<0>, C4<0>; +L_0x1dfe140 .delay 1 (30000,30000,30000) L_0x1dfe140/d; +v0x1c1fe80_0 .net *"_s0", 0 0, L_0x1dfd950; 1 drivers +v0x1c1ff80_0 .net *"_s10", 0 0, L_0x1dfde60; 1 drivers +v0x1c20060_0 .net *"_s12", 0 0, L_0x1dfdfc0; 1 drivers +v0x1c20120_0 .net *"_s14", 0 0, L_0x1dfe1b0; 1 drivers +v0x1c20200_0 .net *"_s16", 0 0, L_0x1dfe360; 1 drivers +v0x1c20330_0 .net *"_s3", 0 0, L_0x1dfd9c0; 1 drivers +v0x1c20410_0 .net *"_s5", 0 0, L_0x1dfdb20; 1 drivers +v0x1c204f0_0 .net *"_s6", 0 0, L_0x1dfdd50; 1 drivers +v0x1c205d0_0 .net "in", 3 0, L_0x1dfe590; 1 drivers +v0x1c20740_0 .net "ors", 1 0, L_0x1dfdc60; 1 drivers +v0x1c20820_0 .net "out", 0 0, L_0x1dfe140; 1 drivers +L_0x1dfd9c0 .part L_0x1dfe590, 0, 1; +L_0x1dfdb20 .part L_0x1dfe590, 1, 1; +L_0x1dfdc60 .concat8 [ 1 1 0 0], L_0x1dfd950, L_0x1dfdd50; +L_0x1dfde60 .part L_0x1dfe590, 2, 1; +L_0x1dfdfc0 .part L_0x1dfe590, 3, 1; +L_0x1dfe1b0 .part L_0x1dfdc60, 0, 1; +L_0x1dfe360 .part L_0x1dfdc60, 1, 1; +S_0x1c21130 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c14ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1de8d90/d .functor XNOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; +L_0x1de8d90 .delay 1 (20000,20000,20000) L_0x1de8d90/d; +L_0x1dfa020/d .functor AND 1, L_0x1e024d0, L_0x1df8e00, C4<1>, C4<1>; +L_0x1dfa020 .delay 1 (30000,30000,30000) L_0x1dfa020/d; +L_0x1dfa0e0/d .functor AND 1, L_0x1de8d90, L_0x1db43e0, C4<1>, C4<1>; +L_0x1dfa0e0 .delay 1 (30000,30000,30000) L_0x1dfa0e0/d; +L_0x1dfa240/d .functor OR 1, L_0x1dfa0e0, L_0x1dfa020, C4<0>, C4<0>; +L_0x1dfa240 .delay 1 (30000,30000,30000) L_0x1dfa240/d; +v0x1c213e0_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers +v0x1c214d0_0 .net "a_", 0 0, L_0x1df8ca0; alias, 1 drivers +v0x1c21590_0 .net "b", 0 0, L_0x1db4230; alias, 1 drivers +v0x1c21680_0 .net "b_", 0 0, L_0x1df8e00; alias, 1 drivers +v0x1c21720_0 .net "carryin", 0 0, L_0x1db43e0; alias, 1 drivers +v0x1c21860_0 .net "eq", 0 0, L_0x1de8d90; 1 drivers +v0x1c21920_0 .net "lt", 0 0, L_0x1dfa020; 1 drivers +v0x1c219e0_0 .net "out", 0 0, L_0x1dfa240; 1 drivers +v0x1c21aa0_0 .net "w0", 0 0, L_0x1dfa0e0; 1 drivers +S_0x1c21cf0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c14ab0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1df9cf0/d .functor OR 1, L_0x1df97f0, L_0x1c22f50, C4<0>, C4<0>; +L_0x1df9cf0 .delay 1 (30000,30000,30000) L_0x1df9cf0/d; +v0x1c22ae0_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers +v0x1c22c30_0 .net "b", 0 0, L_0x1df8e00; alias, 1 drivers +v0x1c22cf0_0 .net "c1", 0 0, L_0x1df97f0; 1 drivers +v0x1c22d90_0 .net "c2", 0 0, L_0x1c22f50; 1 drivers +v0x1c22e60_0 .net "carryin", 0 0, L_0x1db43e0; alias, 1 drivers +v0x1c22fe0_0 .net "carryout", 0 0, L_0x1df9cf0; 1 drivers +v0x1c23080_0 .net "s1", 0 0, L_0x1df9730; 1 drivers +v0x1c23120_0 .net "sum", 0 0, L_0x1df9950; 1 drivers +S_0x1c21f40 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c21cf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1df9730/d .functor XOR 1, L_0x1e024d0, L_0x1df8e00, C4<0>, C4<0>; +L_0x1df9730 .delay 1 (30000,30000,30000) L_0x1df9730/d; +L_0x1df97f0/d .functor AND 1, L_0x1e024d0, L_0x1df8e00, C4<1>, C4<1>; +L_0x1df97f0 .delay 1 (30000,30000,30000) L_0x1df97f0/d; +v0x1c221a0_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers +v0x1c22260_0 .net "b", 0 0, L_0x1df8e00; alias, 1 drivers +v0x1c22320_0 .net "carryout", 0 0, L_0x1df97f0; alias, 1 drivers +v0x1c223c0_0 .net "sum", 0 0, L_0x1df9730; alias, 1 drivers +S_0x1c224f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c21cf0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1df9950/d .functor XOR 1, L_0x1df9730, L_0x1db43e0, C4<0>, C4<0>; +L_0x1df9950 .delay 1 (30000,30000,30000) L_0x1df9950/d; +L_0x1c22f50/d .functor AND 1, L_0x1df9730, L_0x1db43e0, C4<1>, C4<1>; +L_0x1c22f50 .delay 1 (30000,30000,30000) L_0x1c22f50/d; +v0x1c22750_0 .net "a", 0 0, L_0x1df9730; alias, 1 drivers +v0x1c22820_0 .net "b", 0 0, L_0x1db43e0; alias, 1 drivers +v0x1c228c0_0 .net "carryout", 0 0, L_0x1c22f50; alias, 1 drivers +v0x1c22990_0 .net "sum", 0 0, L_0x1df9950; alias, 1 drivers +S_0x1c24540 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c147e0; + .timescale -9 -12; +L_0x7f72592dafd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db020 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e02570/d .functor OR 1, L_0x7f72592dafd8, L_0x7f72592db020, C4<0>, C4<0>; +L_0x1e02570 .delay 1 (30000,30000,30000) L_0x1e02570/d; +v0x1c24730_0 .net/2u *"_s0", 0 0, L_0x7f72592dafd8; 1 drivers +v0x1c24810_0 .net/2u *"_s2", 0 0, L_0x7f72592db020; 1 drivers +S_0x1c248f0 .scope generate, "alu_slices[15]" "alu_slices[15]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c24b00 .param/l "i" 0 3 37, +C4<01111>; +S_0x1c24bc0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c248f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1df8aa0/d .functor NOT 1, L_0x1e0c2e0, C4<0>, C4<0>, C4<0>; +L_0x1df8aa0 .delay 1 (10000,10000,10000) L_0x1df8aa0/d; +L_0x1e02c10/d .functor NOT 1, L_0x1e02a50, C4<0>, C4<0>, C4<0>; +L_0x1e02c10 .delay 1 (10000,10000,10000) L_0x1e02c10/d; +L_0x1e03b50/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; +L_0x1e03b50 .delay 1 (30000,30000,30000) L_0x1e03b50/d; +L_0x7f72592db068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db0b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e04200/d .functor OR 1, L_0x7f72592db068, L_0x7f72592db0b0, C4<0>, C4<0>; +L_0x1e04200 .delay 1 (30000,30000,30000) L_0x1e04200/d; +L_0x1e04400/d .functor AND 1, L_0x1e0c2e0, L_0x1e02a50, C4<1>, C4<1>; +L_0x1e04400 .delay 1 (30000,30000,30000) L_0x1e04400/d; +L_0x1e044c0/d .functor NAND 1, L_0x1e0c2e0, L_0x1e02a50, C4<1>, C4<1>; +L_0x1e044c0 .delay 1 (20000,20000,20000) L_0x1e044c0/d; +L_0x1e04620/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; +L_0x1e04620 .delay 1 (20000,20000,20000) L_0x1e04620/d; +L_0x1e04ad0/d .functor OR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; +L_0x1e04ad0 .delay 1 (30000,30000,30000) L_0x1e04ad0/d; +L_0x1e0c1e0/d .functor NOT 1, L_0x1e08440, C4<0>, C4<0>, C4<0>; +L_0x1e0c1e0 .delay 1 (10000,10000,10000) L_0x1e0c1e0/d; +v0x1c332f0_0 .net "A", 0 0, L_0x1e0c2e0; 1 drivers +v0x1c333b0_0 .net "A_", 0 0, L_0x1df8aa0; 1 drivers +v0x1c33470_0 .net "B", 0 0, L_0x1e02a50; 1 drivers +v0x1c33540_0 .net "B_", 0 0, L_0x1e02c10; 1 drivers +v0x1c335e0_0 .net *"_s12", 0 0, L_0x1e04200; 1 drivers +v0x1c336d0_0 .net/2s *"_s14", 0 0, L_0x7f72592db068; 1 drivers +v0x1c33790_0 .net/2s *"_s16", 0 0, L_0x7f72592db0b0; 1 drivers +v0x1c33870_0 .net *"_s18", 0 0, L_0x1e04400; 1 drivers +v0x1c33950_0 .net *"_s20", 0 0, L_0x1e044c0; 1 drivers +v0x1c33ac0_0 .net *"_s22", 0 0, L_0x1e04620; 1 drivers +v0x1c33ba0_0 .net *"_s24", 0 0, L_0x1e04ad0; 1 drivers +o0x7f7259379278 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c33c80_0 name=_s30 +o0x7f72593792a8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c33d60_0 name=_s32 +v0x1c33e40_0 .net *"_s8", 0 0, L_0x1e03b50; 1 drivers +v0x1c33f20_0 .net "carryin", 0 0, L_0x1e02af0; 1 drivers +v0x1c33fc0_0 .net "carryout", 0 0, L_0x1e0be80; 1 drivers +v0x1c34060_0 .net "carryouts", 7 0, L_0x1ec0420; 1 drivers +v0x1c34210_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c342b0_0 .net "result", 0 0, L_0x1e08440; 1 drivers +v0x1c343a0_0 .net "results", 7 0, L_0x1e048a0; 1 drivers +v0x1c344b0_0 .net "zero", 0 0, L_0x1e0c1e0; 1 drivers +LS_0x1e048a0_0_0 .concat8 [ 1 1 1 1], L_0x1e03070, L_0x1e036a0, L_0x1e03b50, L_0x1e04200; +LS_0x1e048a0_0_4 .concat8 [ 1 1 1 1], L_0x1e04400, L_0x1e044c0, L_0x1e04620, L_0x1e04ad0; +L_0x1e048a0 .concat8 [ 4 4 0 0], LS_0x1e048a0_0_0, LS_0x1e048a0_0_4; +LS_0x1ec0420_0_0 .concat [ 1 1 1 1], L_0x1e03320, L_0x1e039f0, o0x7f7259379278, L_0x1e04050; +LS_0x1ec0420_0_4 .concat [ 4 0 0 0], o0x7f72593792a8; +L_0x1ec0420 .concat [ 4 4 0 0], LS_0x1ec0420_0_0, LS_0x1ec0420_0_4; +S_0x1c24e40 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c24bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e03320/d .functor OR 1, L_0x1e02e00, L_0x1e031c0, C4<0>, C4<0>; +L_0x1e03320 .delay 1 (30000,30000,30000) L_0x1e03320/d; +v0x1c25c70_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers +v0x1c25d30_0 .net "b", 0 0, L_0x1e02a50; alias, 1 drivers +v0x1c25e00_0 .net "c1", 0 0, L_0x1e02e00; 1 drivers +v0x1c25f00_0 .net "c2", 0 0, L_0x1e031c0; 1 drivers +v0x1c25fd0_0 .net "carryin", 0 0, L_0x1e02af0; alias, 1 drivers +v0x1c260c0_0 .net "carryout", 0 0, L_0x1e03320; 1 drivers +v0x1c26160_0 .net "s1", 0 0, L_0x1dfc5b0; 1 drivers +v0x1c26250_0 .net "sum", 0 0, L_0x1e03070; 1 drivers +S_0x1c250b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c24e40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1dfc5b0/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; +L_0x1dfc5b0 .delay 1 (30000,30000,30000) L_0x1dfc5b0/d; +L_0x1e02e00/d .functor AND 1, L_0x1e0c2e0, L_0x1e02a50, C4<1>, C4<1>; +L_0x1e02e00 .delay 1 (30000,30000,30000) L_0x1e02e00/d; +v0x1c25310_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers +v0x1c253f0_0 .net "b", 0 0, L_0x1e02a50; alias, 1 drivers +v0x1c254b0_0 .net "carryout", 0 0, L_0x1e02e00; alias, 1 drivers +v0x1c25550_0 .net "sum", 0 0, L_0x1dfc5b0; alias, 1 drivers +S_0x1c25690 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c24e40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e03070/d .functor XOR 1, L_0x1dfc5b0, L_0x1e02af0, C4<0>, C4<0>; +L_0x1e03070 .delay 1 (30000,30000,30000) L_0x1e03070/d; +L_0x1e031c0/d .functor AND 1, L_0x1dfc5b0, L_0x1e02af0, C4<1>, C4<1>; +L_0x1e031c0 .delay 1 (30000,30000,30000) L_0x1e031c0/d; +v0x1c258f0_0 .net "a", 0 0, L_0x1dfc5b0; alias, 1 drivers +v0x1c25990_0 .net "b", 0 0, L_0x1e02af0; alias, 1 drivers +v0x1c25a30_0 .net "carryout", 0 0, L_0x1e031c0; alias, 1 drivers +v0x1c25b00_0 .net "sum", 0 0, L_0x1e03070; alias, 1 drivers +S_0x1c26320 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c24bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c2b710_0 .net "ands", 7 0, L_0x1e09e80; 1 drivers +v0x1c2b820_0 .net "in", 7 0, L_0x1ec0420; alias, 1 drivers +v0x1c2b8e0_0 .net "out", 0 0, L_0x1e0be80; alias, 1 drivers +v0x1c2b9b0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c26540 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c26320; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c28c70_0 .net "A", 7 0, L_0x1ec0420; alias, 1 drivers +v0x1c28d70_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c28e30_0 .net *"_s0", 0 0, L_0x1e087a0; 1 drivers +v0x1c28ef0_0 .net *"_s12", 0 0, L_0x1e09110; 1 drivers +v0x1c28fd0_0 .net *"_s16", 0 0, L_0x1e09470; 1 drivers +v0x1c29100_0 .net *"_s20", 0 0, L_0x1e09780; 1 drivers +v0x1c291e0_0 .net *"_s24", 0 0, L_0x1e09b70; 1 drivers +v0x1c292c0_0 .net *"_s28", 0 0, L_0x1e09b00; 1 drivers +v0x1c293a0_0 .net *"_s4", 0 0, L_0x1e08ab0; 1 drivers +v0x1c29510_0 .net *"_s8", 0 0, L_0x1e08e00; 1 drivers +v0x1c295f0_0 .net "out", 7 0, L_0x1e09e80; alias, 1 drivers +L_0x1e08860 .part L_0x1ec0420, 0, 1; +L_0x1e089c0 .part v0x1d6daa0_0, 0, 1; +L_0x1e08b70 .part L_0x1ec0420, 1, 1; +L_0x1e08d60 .part v0x1d6daa0_0, 1, 1; +L_0x1e08ec0 .part L_0x1ec0420, 2, 1; +L_0x1e09020 .part v0x1d6daa0_0, 2, 1; +L_0x1e091d0 .part L_0x1ec0420, 3, 1; +L_0x1e09330 .part v0x1d6daa0_0, 3, 1; +L_0x1e09530 .part L_0x1ec0420, 4, 1; +L_0x1e09690 .part v0x1d6daa0_0, 4, 1; +L_0x1e097f0 .part L_0x1ec0420, 5, 1; +L_0x1e09a60 .part v0x1d6daa0_0, 5, 1; +L_0x1e09c30 .part L_0x1ec0420, 6, 1; +L_0x1e09d90 .part v0x1d6daa0_0, 6, 1; +LS_0x1e09e80_0_0 .concat8 [ 1 1 1 1], L_0x1e087a0, L_0x1e08ab0, L_0x1e08e00, L_0x1e09110; +LS_0x1e09e80_0_4 .concat8 [ 1 1 1 1], L_0x1e09470, L_0x1e09780, L_0x1e09b70, L_0x1e09b00; +L_0x1e09e80 .concat8 [ 4 4 0 0], LS_0x1e09e80_0_0, LS_0x1e09e80_0_4; +L_0x1e0a240 .part L_0x1ec0420, 7, 1; +L_0x1e0a430 .part v0x1d6daa0_0, 7, 1; +S_0x1c267a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c269b0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e087a0/d .functor AND 1, L_0x1e08860, L_0x1e089c0, C4<1>, C4<1>; +L_0x1e087a0 .delay 1 (30000,30000,30000) L_0x1e087a0/d; +v0x1c26a90_0 .net *"_s0", 0 0, L_0x1e08860; 1 drivers +v0x1c26b70_0 .net *"_s1", 0 0, L_0x1e089c0; 1 drivers +S_0x1c26c50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c26e60 .param/l "i" 0 4 54, +C4<01>; +L_0x1e08ab0/d .functor AND 1, L_0x1e08b70, L_0x1e08d60, C4<1>, C4<1>; +L_0x1e08ab0 .delay 1 (30000,30000,30000) L_0x1e08ab0/d; +v0x1c26f20_0 .net *"_s0", 0 0, L_0x1e08b70; 1 drivers +v0x1c27000_0 .net *"_s1", 0 0, L_0x1e08d60; 1 drivers +S_0x1c270e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c272f0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e08e00/d .functor AND 1, L_0x1e08ec0, L_0x1e09020, C4<1>, C4<1>; +L_0x1e08e00 .delay 1 (30000,30000,30000) L_0x1e08e00/d; +v0x1c27390_0 .net *"_s0", 0 0, L_0x1e08ec0; 1 drivers +v0x1c27470_0 .net *"_s1", 0 0, L_0x1e09020; 1 drivers +S_0x1c27550 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c27760 .param/l "i" 0 4 54, +C4<011>; +L_0x1e09110/d .functor AND 1, L_0x1e091d0, L_0x1e09330, C4<1>, C4<1>; +L_0x1e09110 .delay 1 (30000,30000,30000) L_0x1e09110/d; +v0x1c27820_0 .net *"_s0", 0 0, L_0x1e091d0; 1 drivers +v0x1c27900_0 .net *"_s1", 0 0, L_0x1e09330; 1 drivers +S_0x1c279e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c27c40 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e09470/d .functor AND 1, L_0x1e09530, L_0x1e09690, C4<1>, C4<1>; +L_0x1e09470 .delay 1 (30000,30000,30000) L_0x1e09470/d; +v0x1c27d00_0 .net *"_s0", 0 0, L_0x1e09530; 1 drivers +v0x1c27de0_0 .net *"_s1", 0 0, L_0x1e09690; 1 drivers +S_0x1c27ec0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c280d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e09780/d .functor AND 1, L_0x1e097f0, L_0x1e09a60, C4<1>, C4<1>; +L_0x1e09780 .delay 1 (30000,30000,30000) L_0x1e09780/d; +v0x1c28190_0 .net *"_s0", 0 0, L_0x1e097f0; 1 drivers +v0x1c28270_0 .net *"_s1", 0 0, L_0x1e09a60; 1 drivers +S_0x1c28350 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c28560 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e09b70/d .functor AND 1, L_0x1e09c30, L_0x1e09d90, C4<1>, C4<1>; +L_0x1e09b70 .delay 1 (30000,30000,30000) L_0x1e09b70/d; +v0x1c28620_0 .net *"_s0", 0 0, L_0x1e09c30; 1 drivers +v0x1c28700_0 .net *"_s1", 0 0, L_0x1e09d90; 1 drivers +S_0x1c287e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c26540; + .timescale -9 -12; +P_0x1c289f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e09b00/d .functor AND 1, L_0x1e0a240, L_0x1e0a430, C4<1>, C4<1>; +L_0x1e09b00 .delay 1 (30000,30000,30000) L_0x1e09b00/d; +v0x1c28ab0_0 .net *"_s0", 0 0, L_0x1e0a240; 1 drivers +v0x1c28b90_0 .net *"_s1", 0 0, L_0x1e0a430; 1 drivers +S_0x1c29750 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c26320; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e0be80/d .functor OR 1, L_0x1e0bf40, L_0x1e0c0f0, C4<0>, C4<0>; +L_0x1e0be80 .delay 1 (30000,30000,30000) L_0x1e0be80/d; +v0x1c2b2a0_0 .net *"_s10", 0 0, L_0x1e0bf40; 1 drivers +v0x1c2b380_0 .net *"_s12", 0 0, L_0x1e0c0f0; 1 drivers +v0x1c2b460_0 .net "in", 7 0, L_0x1e09e80; alias, 1 drivers +v0x1c2b530_0 .net "ors", 1 0, L_0x1e0bca0; 1 drivers +v0x1c2b5f0_0 .net "out", 0 0, L_0x1e0be80; alias, 1 drivers +L_0x1e0b070 .part L_0x1e09e80, 0, 4; +L_0x1e0bca0 .concat8 [ 1 1 0 0], L_0x1e0ad60, L_0x1e0b990; +L_0x1e0bde0 .part L_0x1e09e80, 4, 4; +L_0x1e0bf40 .part L_0x1e0bca0, 0, 1; +L_0x1e0c0f0 .part L_0x1e0bca0, 1, 1; +S_0x1c29910 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c29750; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e0a520/d .functor OR 1, L_0x1e0a5e0, L_0x1e0a740, C4<0>, C4<0>; +L_0x1e0a520 .delay 1 (30000,30000,30000) L_0x1e0a520/d; +L_0x1e0a970/d .functor OR 1, L_0x1e0aa80, L_0x1e0abe0, C4<0>, C4<0>; +L_0x1e0a970 .delay 1 (30000,30000,30000) L_0x1e0a970/d; +L_0x1e0ad60/d .functor OR 1, L_0x1e0add0, L_0x1e0af80, C4<0>, C4<0>; +L_0x1e0ad60 .delay 1 (30000,30000,30000) L_0x1e0ad60/d; +v0x1c29b60_0 .net *"_s0", 0 0, L_0x1e0a520; 1 drivers +v0x1c29c60_0 .net *"_s10", 0 0, L_0x1e0aa80; 1 drivers +v0x1c29d40_0 .net *"_s12", 0 0, L_0x1e0abe0; 1 drivers +v0x1c29e00_0 .net *"_s14", 0 0, L_0x1e0add0; 1 drivers +v0x1c29ee0_0 .net *"_s16", 0 0, L_0x1e0af80; 1 drivers +v0x1c2a010_0 .net *"_s3", 0 0, L_0x1e0a5e0; 1 drivers +v0x1c2a0f0_0 .net *"_s5", 0 0, L_0x1e0a740; 1 drivers +v0x1c2a1d0_0 .net *"_s6", 0 0, L_0x1e0a970; 1 drivers +v0x1c2a2b0_0 .net "in", 3 0, L_0x1e0b070; 1 drivers +v0x1c2a420_0 .net "ors", 1 0, L_0x1e0a880; 1 drivers +v0x1c2a500_0 .net "out", 0 0, L_0x1e0ad60; 1 drivers +L_0x1e0a5e0 .part L_0x1e0b070, 0, 1; +L_0x1e0a740 .part L_0x1e0b070, 1, 1; +L_0x1e0a880 .concat8 [ 1 1 0 0], L_0x1e0a520, L_0x1e0a970; +L_0x1e0aa80 .part L_0x1e0b070, 2, 1; +L_0x1e0abe0 .part L_0x1e0b070, 3, 1; +L_0x1e0add0 .part L_0x1e0a880, 0, 1; +L_0x1e0af80 .part L_0x1e0a880, 1, 1; +S_0x1c2a620 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c29750; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e0b1a0/d .functor OR 1, L_0x1e0b210, L_0x1e0b370, C4<0>, C4<0>; +L_0x1e0b1a0 .delay 1 (30000,30000,30000) L_0x1e0b1a0/d; +L_0x1e0b5a0/d .functor OR 1, L_0x1e0b6b0, L_0x1e0b810, C4<0>, C4<0>; +L_0x1e0b5a0 .delay 1 (30000,30000,30000) L_0x1e0b5a0/d; +L_0x1e0b990/d .functor OR 1, L_0x1e0ba00, L_0x1e0bbb0, C4<0>, C4<0>; +L_0x1e0b990 .delay 1 (30000,30000,30000) L_0x1e0b990/d; +v0x1c2a7e0_0 .net *"_s0", 0 0, L_0x1e0b1a0; 1 drivers +v0x1c2a8e0_0 .net *"_s10", 0 0, L_0x1e0b6b0; 1 drivers +v0x1c2a9c0_0 .net *"_s12", 0 0, L_0x1e0b810; 1 drivers +v0x1c2aa80_0 .net *"_s14", 0 0, L_0x1e0ba00; 1 drivers +v0x1c2ab60_0 .net *"_s16", 0 0, L_0x1e0bbb0; 1 drivers +v0x1c2ac90_0 .net *"_s3", 0 0, L_0x1e0b210; 1 drivers +v0x1c2ad70_0 .net *"_s5", 0 0, L_0x1e0b370; 1 drivers +v0x1c2ae50_0 .net *"_s6", 0 0, L_0x1e0b5a0; 1 drivers +v0x1c2af30_0 .net "in", 3 0, L_0x1e0bde0; 1 drivers +v0x1c2b0a0_0 .net "ors", 1 0, L_0x1e0b4b0; 1 drivers +v0x1c2b180_0 .net "out", 0 0, L_0x1e0b990; 1 drivers +L_0x1e0b210 .part L_0x1e0bde0, 0, 1; +L_0x1e0b370 .part L_0x1e0bde0, 1, 1; +L_0x1e0b4b0 .concat8 [ 1 1 0 0], L_0x1e0b1a0, L_0x1e0b5a0; +L_0x1e0b6b0 .part L_0x1e0bde0, 2, 1; +L_0x1e0b810 .part L_0x1e0bde0, 3, 1; +L_0x1e0ba00 .part L_0x1e0b4b0, 0, 1; +L_0x1e0bbb0 .part L_0x1e0b4b0, 1, 1; +S_0x1c2ba90 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c24bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c30ec0_0 .net "ands", 7 0, L_0x1e06440; 1 drivers +v0x1c30fd0_0 .net "in", 7 0, L_0x1e048a0; alias, 1 drivers +v0x1c31090_0 .net "out", 0 0, L_0x1e08440; alias, 1 drivers +v0x1c31160_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c2bce0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c2ba90; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c2e420_0 .net "A", 7 0, L_0x1e048a0; alias, 1 drivers +v0x1c2e520_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c2e5e0_0 .net *"_s0", 0 0, L_0x1e04c30; 1 drivers +v0x1c2e6a0_0 .net *"_s12", 0 0, L_0x1e055f0; 1 drivers +v0x1c2e780_0 .net *"_s16", 0 0, L_0x1e05950; 1 drivers +v0x1c2e8b0_0 .net *"_s20", 0 0, L_0x1e05d80; 1 drivers +v0x1c2e990_0 .net *"_s24", 0 0, L_0x1e060b0; 1 drivers +v0x1c2ea70_0 .net *"_s28", 0 0, L_0x1e06040; 1 drivers +v0x1c2eb50_0 .net *"_s4", 0 0, L_0x1e04fd0; 1 drivers +v0x1c2ecc0_0 .net *"_s8", 0 0, L_0x1e052e0; 1 drivers +v0x1c2eda0_0 .net "out", 7 0, L_0x1e06440; alias, 1 drivers +L_0x1e04d40 .part L_0x1e048a0, 0, 1; +L_0x1e04f30 .part v0x1d6daa0_0, 0, 1; +L_0x1e05090 .part L_0x1e048a0, 1, 1; +L_0x1e051f0 .part v0x1d6daa0_0, 1, 1; +L_0x1e053a0 .part L_0x1e048a0, 2, 1; +L_0x1e05500 .part v0x1d6daa0_0, 2, 1; +L_0x1e056b0 .part L_0x1e048a0, 3, 1; +L_0x1e05810 .part v0x1d6daa0_0, 3, 1; +L_0x1e05a10 .part L_0x1e048a0, 4, 1; +L_0x1e05c80 .part v0x1d6daa0_0, 4, 1; +L_0x1e05df0 .part L_0x1e048a0, 5, 1; +L_0x1e05f50 .part v0x1d6daa0_0, 5, 1; +L_0x1e06170 .part L_0x1e048a0, 6, 1; +L_0x1e062d0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e06440_0_0 .concat8 [ 1 1 1 1], L_0x1e04c30, L_0x1e04fd0, L_0x1e052e0, L_0x1e055f0; +LS_0x1e06440_0_4 .concat8 [ 1 1 1 1], L_0x1e05950, L_0x1e05d80, L_0x1e060b0, L_0x1e06040; +L_0x1e06440 .concat8 [ 4 4 0 0], LS_0x1e06440_0_0, LS_0x1e06440_0_4; +L_0x1e06800 .part L_0x1e048a0, 7, 1; +L_0x1e069f0 .part v0x1d6daa0_0, 7, 1; +S_0x1c2bf20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2c130 .param/l "i" 0 4 54, +C4<00>; +L_0x1e04c30/d .functor AND 1, L_0x1e04d40, L_0x1e04f30, C4<1>, C4<1>; +L_0x1e04c30 .delay 1 (30000,30000,30000) L_0x1e04c30/d; +v0x1c2c210_0 .net *"_s0", 0 0, L_0x1e04d40; 1 drivers +v0x1c2c2f0_0 .net *"_s1", 0 0, L_0x1e04f30; 1 drivers +S_0x1c2c3d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2c5e0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e04fd0/d .functor AND 1, L_0x1e05090, L_0x1e051f0, C4<1>, C4<1>; +L_0x1e04fd0 .delay 1 (30000,30000,30000) L_0x1e04fd0/d; +v0x1c2c6a0_0 .net *"_s0", 0 0, L_0x1e05090; 1 drivers +v0x1c2c780_0 .net *"_s1", 0 0, L_0x1e051f0; 1 drivers +S_0x1c2c860 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2caa0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e052e0/d .functor AND 1, L_0x1e053a0, L_0x1e05500, C4<1>, C4<1>; +L_0x1e052e0 .delay 1 (30000,30000,30000) L_0x1e052e0/d; +v0x1c2cb40_0 .net *"_s0", 0 0, L_0x1e053a0; 1 drivers +v0x1c2cc20_0 .net *"_s1", 0 0, L_0x1e05500; 1 drivers +S_0x1c2cd00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2cf10 .param/l "i" 0 4 54, +C4<011>; +L_0x1e055f0/d .functor AND 1, L_0x1e056b0, L_0x1e05810, C4<1>, C4<1>; +L_0x1e055f0 .delay 1 (30000,30000,30000) L_0x1e055f0/d; +v0x1c2cfd0_0 .net *"_s0", 0 0, L_0x1e056b0; 1 drivers +v0x1c2d0b0_0 .net *"_s1", 0 0, L_0x1e05810; 1 drivers +S_0x1c2d190 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2d3f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e05950/d .functor AND 1, L_0x1e05a10, L_0x1e05c80, C4<1>, C4<1>; +L_0x1e05950 .delay 1 (30000,30000,30000) L_0x1e05950/d; +v0x1c2d4b0_0 .net *"_s0", 0 0, L_0x1e05a10; 1 drivers +v0x1c2d590_0 .net *"_s1", 0 0, L_0x1e05c80; 1 drivers +S_0x1c2d670 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2d880 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e05d80/d .functor AND 1, L_0x1e05df0, L_0x1e05f50, C4<1>, C4<1>; +L_0x1e05d80 .delay 1 (30000,30000,30000) L_0x1e05d80/d; +v0x1c2d940_0 .net *"_s0", 0 0, L_0x1e05df0; 1 drivers +v0x1c2da20_0 .net *"_s1", 0 0, L_0x1e05f50; 1 drivers +S_0x1c2db00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2dd10 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e060b0/d .functor AND 1, L_0x1e06170, L_0x1e062d0, C4<1>, C4<1>; +L_0x1e060b0 .delay 1 (30000,30000,30000) L_0x1e060b0/d; +v0x1c2ddd0_0 .net *"_s0", 0 0, L_0x1e06170; 1 drivers +v0x1c2deb0_0 .net *"_s1", 0 0, L_0x1e062d0; 1 drivers +S_0x1c2df90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c2bce0; + .timescale -9 -12; +P_0x1c2e180 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e06040/d .functor AND 1, L_0x1e06800, L_0x1e069f0, C4<1>, C4<1>; +L_0x1e06040 .delay 1 (30000,30000,30000) L_0x1e06040/d; +v0x1c2e260_0 .net *"_s0", 0 0, L_0x1e06800; 1 drivers +v0x1c2e340_0 .net *"_s1", 0 0, L_0x1e069f0; 1 drivers +S_0x1c2ef00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c2ba90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e08440/d .functor OR 1, L_0x1e08500, L_0x1e086b0, C4<0>, C4<0>; +L_0x1e08440 .delay 1 (30000,30000,30000) L_0x1e08440/d; +v0x1c30a50_0 .net *"_s10", 0 0, L_0x1e08500; 1 drivers +v0x1c30b30_0 .net *"_s12", 0 0, L_0x1e086b0; 1 drivers +v0x1c30c10_0 .net "in", 7 0, L_0x1e06440; alias, 1 drivers +v0x1c30ce0_0 .net "ors", 1 0, L_0x1e08260; 1 drivers +v0x1c30da0_0 .net "out", 0 0, L_0x1e08440; alias, 1 drivers +L_0x1e07630 .part L_0x1e06440, 0, 4; +L_0x1e08260 .concat8 [ 1 1 0 0], L_0x1e07320, L_0x1e07f50; +L_0x1e083a0 .part L_0x1e06440, 4, 4; +L_0x1e08500 .part L_0x1e08260, 0, 1; +L_0x1e086b0 .part L_0x1e08260, 1, 1; +S_0x1c2f0c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c2ef00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e06ae0/d .functor OR 1, L_0x1e06ba0, L_0x1e06d00, C4<0>, C4<0>; +L_0x1e06ae0 .delay 1 (30000,30000,30000) L_0x1e06ae0/d; +L_0x1e06f30/d .functor OR 1, L_0x1e07040, L_0x1e071a0, C4<0>, C4<0>; +L_0x1e06f30 .delay 1 (30000,30000,30000) L_0x1e06f30/d; +L_0x1e07320/d .functor OR 1, L_0x1e07390, L_0x1e07540, C4<0>, C4<0>; +L_0x1e07320 .delay 1 (30000,30000,30000) L_0x1e07320/d; +v0x1c2f310_0 .net *"_s0", 0 0, L_0x1e06ae0; 1 drivers +v0x1c2f410_0 .net *"_s10", 0 0, L_0x1e07040; 1 drivers +v0x1c2f4f0_0 .net *"_s12", 0 0, L_0x1e071a0; 1 drivers +v0x1c2f5b0_0 .net *"_s14", 0 0, L_0x1e07390; 1 drivers +v0x1c2f690_0 .net *"_s16", 0 0, L_0x1e07540; 1 drivers +v0x1c2f7c0_0 .net *"_s3", 0 0, L_0x1e06ba0; 1 drivers +v0x1c2f8a0_0 .net *"_s5", 0 0, L_0x1e06d00; 1 drivers +v0x1c2f980_0 .net *"_s6", 0 0, L_0x1e06f30; 1 drivers +v0x1c2fa60_0 .net "in", 3 0, L_0x1e07630; 1 drivers +v0x1c2fbd0_0 .net "ors", 1 0, L_0x1e06e40; 1 drivers +v0x1c2fcb0_0 .net "out", 0 0, L_0x1e07320; 1 drivers +L_0x1e06ba0 .part L_0x1e07630, 0, 1; +L_0x1e06d00 .part L_0x1e07630, 1, 1; +L_0x1e06e40 .concat8 [ 1 1 0 0], L_0x1e06ae0, L_0x1e06f30; +L_0x1e07040 .part L_0x1e07630, 2, 1; +L_0x1e071a0 .part L_0x1e07630, 3, 1; +L_0x1e07390 .part L_0x1e06e40, 0, 1; +L_0x1e07540 .part L_0x1e06e40, 1, 1; +S_0x1c2fdd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c2ef00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e07760/d .functor OR 1, L_0x1e077d0, L_0x1e07930, C4<0>, C4<0>; +L_0x1e07760 .delay 1 (30000,30000,30000) L_0x1e07760/d; +L_0x1e07b60/d .functor OR 1, L_0x1e07c70, L_0x1e07dd0, C4<0>, C4<0>; +L_0x1e07b60 .delay 1 (30000,30000,30000) L_0x1e07b60/d; +L_0x1e07f50/d .functor OR 1, L_0x1e07fc0, L_0x1e08170, C4<0>, C4<0>; +L_0x1e07f50 .delay 1 (30000,30000,30000) L_0x1e07f50/d; +v0x1c2ff90_0 .net *"_s0", 0 0, L_0x1e07760; 1 drivers +v0x1c30090_0 .net *"_s10", 0 0, L_0x1e07c70; 1 drivers +v0x1c30170_0 .net *"_s12", 0 0, L_0x1e07dd0; 1 drivers +v0x1c30230_0 .net *"_s14", 0 0, L_0x1e07fc0; 1 drivers +v0x1c30310_0 .net *"_s16", 0 0, L_0x1e08170; 1 drivers +v0x1c30440_0 .net *"_s3", 0 0, L_0x1e077d0; 1 drivers +v0x1c30520_0 .net *"_s5", 0 0, L_0x1e07930; 1 drivers +v0x1c30600_0 .net *"_s6", 0 0, L_0x1e07b60; 1 drivers +v0x1c306e0_0 .net "in", 3 0, L_0x1e083a0; 1 drivers +v0x1c30850_0 .net "ors", 1 0, L_0x1e07a70; 1 drivers +v0x1c30930_0 .net "out", 0 0, L_0x1e07f50; 1 drivers +L_0x1e077d0 .part L_0x1e083a0, 0, 1; +L_0x1e07930 .part L_0x1e083a0, 1, 1; +L_0x1e07a70 .concat8 [ 1 1 0 0], L_0x1e07760, L_0x1e07b60; +L_0x1e07c70 .part L_0x1e083a0, 2, 1; +L_0x1e07dd0 .part L_0x1e083a0, 3, 1; +L_0x1e07fc0 .part L_0x1e07a70, 0, 1; +L_0x1e08170 .part L_0x1e07a70, 1, 1; +S_0x1c31240 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c24bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e03c10/d .functor XNOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; +L_0x1e03c10 .delay 1 (20000,20000,20000) L_0x1e03c10/d; +L_0x1e03e80/d .functor AND 1, L_0x1e0c2e0, L_0x1e02c10, C4<1>, C4<1>; +L_0x1e03e80 .delay 1 (30000,30000,30000) L_0x1e03e80/d; +L_0x1e03ef0/d .functor AND 1, L_0x1e03c10, L_0x1e02af0, C4<1>, C4<1>; +L_0x1e03ef0 .delay 1 (30000,30000,30000) L_0x1e03ef0/d; +L_0x1e04050/d .functor OR 1, L_0x1e03ef0, L_0x1e03e80, C4<0>, C4<0>; +L_0x1e04050 .delay 1 (30000,30000,30000) L_0x1e04050/d; +v0x1c314f0_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers +v0x1c315e0_0 .net "a_", 0 0, L_0x1df8aa0; alias, 1 drivers +v0x1c316a0_0 .net "b", 0 0, L_0x1e02a50; alias, 1 drivers +v0x1c31790_0 .net "b_", 0 0, L_0x1e02c10; alias, 1 drivers +v0x1c31830_0 .net "carryin", 0 0, L_0x1e02af0; alias, 1 drivers +v0x1c31970_0 .net "eq", 0 0, L_0x1e03c10; 1 drivers +v0x1c31a30_0 .net "lt", 0 0, L_0x1e03e80; 1 drivers +v0x1c31af0_0 .net "out", 0 0, L_0x1e04050; 1 drivers +v0x1c31bb0_0 .net "w0", 0 0, L_0x1e03ef0; 1 drivers +S_0x1c31e00 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c24bc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e039f0/d .functor OR 1, L_0x1e03540, L_0x1c33060, C4<0>, C4<0>; +L_0x1e039f0 .delay 1 (30000,30000,30000) L_0x1e039f0/d; +v0x1c32bf0_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers +v0x1c32d40_0 .net "b", 0 0, L_0x1e02c10; alias, 1 drivers +v0x1c32e00_0 .net "c1", 0 0, L_0x1e03540; 1 drivers +v0x1c32ea0_0 .net "c2", 0 0, L_0x1c33060; 1 drivers +v0x1c32f70_0 .net "carryin", 0 0, L_0x1e02af0; alias, 1 drivers +v0x1c330f0_0 .net "carryout", 0 0, L_0x1e039f0; 1 drivers +v0x1c33190_0 .net "s1", 0 0, L_0x1e03480; 1 drivers +v0x1c33230_0 .net "sum", 0 0, L_0x1e036a0; 1 drivers +S_0x1c32050 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c31e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e03480/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02c10, C4<0>, C4<0>; +L_0x1e03480 .delay 1 (30000,30000,30000) L_0x1e03480/d; +L_0x1e03540/d .functor AND 1, L_0x1e0c2e0, L_0x1e02c10, C4<1>, C4<1>; +L_0x1e03540 .delay 1 (30000,30000,30000) L_0x1e03540/d; +v0x1c322b0_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers +v0x1c32370_0 .net "b", 0 0, L_0x1e02c10; alias, 1 drivers +v0x1c32430_0 .net "carryout", 0 0, L_0x1e03540; alias, 1 drivers +v0x1c324d0_0 .net "sum", 0 0, L_0x1e03480; alias, 1 drivers +S_0x1c32600 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c31e00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e036a0/d .functor XOR 1, L_0x1e03480, L_0x1e02af0, C4<0>, C4<0>; +L_0x1e036a0 .delay 1 (30000,30000,30000) L_0x1e036a0/d; +L_0x1c33060/d .functor AND 1, L_0x1e03480, L_0x1e02af0, C4<1>, C4<1>; +L_0x1c33060 .delay 1 (30000,30000,30000) L_0x1c33060/d; +v0x1c32860_0 .net "a", 0 0, L_0x1e03480; alias, 1 drivers +v0x1c32930_0 .net "b", 0 0, L_0x1e02af0; alias, 1 drivers +v0x1c329d0_0 .net "carryout", 0 0, L_0x1c33060; alias, 1 drivers +v0x1c32aa0_0 .net "sum", 0 0, L_0x1e036a0; alias, 1 drivers +S_0x1c34650 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c248f0; + .timescale -9 -12; +L_0x7f72592db0f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e0c380/d .functor OR 1, L_0x7f72592db0f8, L_0x7f72592db140, C4<0>, C4<0>; +L_0x1e0c380 .delay 1 (30000,30000,30000) L_0x1e0c380/d; +v0x1c34840_0 .net/2u *"_s0", 0 0, L_0x7f72592db0f8; 1 drivers +v0x1c34920_0 .net/2u *"_s2", 0 0, L_0x7f72592db140; 1 drivers +S_0x1c34a00 .scope generate, "alu_slices[16]" "alu_slices[16]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1bb3f20 .param/l "i" 0 3 37, +C4<010000>; +S_0x1c34d70 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c34a00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e0c440/d .functor NOT 1, L_0x1e16060, C4<0>, C4<0>, C4<0>; +L_0x1e0c440 .delay 1 (10000,10000,10000) L_0x1e0c440/d; +L_0x1e0c960/d .functor NOT 1, L_0x1e161c0, C4<0>, C4<0>, C4<0>; +L_0x1e0c960 .delay 1 (10000,10000,10000) L_0x1e0c960/d; +L_0x1e0d9b0/d .functor XOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; +L_0x1e0d9b0 .delay 1 (30000,30000,30000) L_0x1e0d9b0/d; +L_0x7f72592db188 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db1d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e0e060/d .functor OR 1, L_0x7f72592db188, L_0x7f72592db1d0, C4<0>, C4<0>; +L_0x1e0e060 .delay 1 (30000,30000,30000) L_0x1e0e060/d; +L_0x1e0e260/d .functor AND 1, L_0x1e16060, L_0x1e161c0, C4<1>, C4<1>; +L_0x1e0e260 .delay 1 (30000,30000,30000) L_0x1e0e260/d; +L_0x1e0e320/d .functor NAND 1, L_0x1e16060, L_0x1e161c0, C4<1>, C4<1>; +L_0x1e0e320 .delay 1 (20000,20000,20000) L_0x1e0e320/d; +L_0x1e0e480/d .functor XOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; +L_0x1e0e480 .delay 1 (20000,20000,20000) L_0x1e0e480/d; +L_0x1e0e930/d .functor OR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; +L_0x1e0e930 .delay 1 (30000,30000,30000) L_0x1e0e930/d; +L_0x1e15f60/d .functor NOT 1, L_0x1e121c0, C4<0>, C4<0>, C4<0>; +L_0x1e15f60 .delay 1 (10000,10000,10000) L_0x1e15f60/d; +v0x1c43480_0 .net "A", 0 0, L_0x1e16060; 1 drivers +v0x1c43540_0 .net "A_", 0 0, L_0x1e0c440; 1 drivers +v0x1c43600_0 .net "B", 0 0, L_0x1e161c0; 1 drivers +v0x1c436d0_0 .net "B_", 0 0, L_0x1e0c960; 1 drivers +v0x1c43770_0 .net *"_s12", 0 0, L_0x1e0e060; 1 drivers +v0x1c43860_0 .net/2s *"_s14", 0 0, L_0x7f72592db188; 1 drivers +v0x1c43920_0 .net/2s *"_s16", 0 0, L_0x7f72592db1d0; 1 drivers +v0x1c43a00_0 .net *"_s18", 0 0, L_0x1e0e260; 1 drivers +v0x1c43ae0_0 .net *"_s20", 0 0, L_0x1e0e320; 1 drivers +v0x1c43c50_0 .net *"_s22", 0 0, L_0x1e0e480; 1 drivers +v0x1c43d30_0 .net *"_s24", 0 0, L_0x1e0e930; 1 drivers +o0x7f725937b7c8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c43e10_0 name=_s30 +o0x7f725937b7f8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c43ef0_0 name=_s32 +v0x1c43fd0_0 .net *"_s8", 0 0, L_0x1e0d9b0; 1 drivers +v0x1c440b0_0 .net "carryin", 0 0, L_0x1e0c7d0; 1 drivers +v0x1c44150_0 .net "carryout", 0 0, L_0x1e15c00; 1 drivers +v0x1c441f0_0 .net "carryouts", 7 0, L_0x1ec05f0; 1 drivers +v0x1c443a0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c44440_0 .net "result", 0 0, L_0x1e121c0; 1 drivers +v0x1c44530_0 .net "results", 7 0, L_0x1e0e700; 1 drivers +v0x1c44640_0 .net "zero", 0 0, L_0x1e15f60; 1 drivers +LS_0x1e0e700_0_0 .concat8 [ 1 1 1 1], L_0x1e0ce80, L_0x1e0d4b0, L_0x1e0d9b0, L_0x1e0e060; +LS_0x1e0e700_0_4 .concat8 [ 1 1 1 1], L_0x1e0e260, L_0x1e0e320, L_0x1e0e480, L_0x1e0e930; +L_0x1e0e700 .concat8 [ 4 4 0 0], LS_0x1e0e700_0_0, LS_0x1e0e700_0_4; +LS_0x1ec05f0_0_0 .concat [ 1 1 1 1], L_0x1e0d130, L_0x1e0d850, o0x7f725937b7c8, L_0x1e0deb0; +LS_0x1ec05f0_0_4 .concat [ 4 0 0 0], o0x7f725937b7f8; +L_0x1ec05f0 .concat [ 4 4 0 0], LS_0x1ec05f0_0_0, LS_0x1ec05f0_0_4; +S_0x1c34ff0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c34d70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e0d130/d .functor OR 1, L_0x1e0cc10, L_0x1e0cfd0, C4<0>, C4<0>; +L_0x1e0d130 .delay 1 (30000,30000,30000) L_0x1e0d130/d; +v0x1c35e00_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers +v0x1c35ec0_0 .net "b", 0 0, L_0x1e161c0; alias, 1 drivers +v0x1c35f90_0 .net "c1", 0 0, L_0x1e0cc10; 1 drivers +v0x1c36090_0 .net "c2", 0 0, L_0x1e0cfd0; 1 drivers +v0x1c36160_0 .net "carryin", 0 0, L_0x1e0c7d0; alias, 1 drivers +v0x1c36250_0 .net "carryout", 0 0, L_0x1e0d130; 1 drivers +v0x1c362f0_0 .net "s1", 0 0, L_0x1e0cb50; 1 drivers +v0x1c363e0_0 .net "sum", 0 0, L_0x1e0ce80; 1 drivers +S_0x1c35240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c34ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e0cb50/d .functor XOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; +L_0x1e0cb50 .delay 1 (30000,30000,30000) L_0x1e0cb50/d; +L_0x1e0cc10/d .functor AND 1, L_0x1e16060, L_0x1e161c0, C4<1>, C4<1>; +L_0x1e0cc10 .delay 1 (30000,30000,30000) L_0x1e0cc10/d; +v0x1c354a0_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers +v0x1c35580_0 .net "b", 0 0, L_0x1e161c0; alias, 1 drivers +v0x1c35640_0 .net "carryout", 0 0, L_0x1e0cc10; alias, 1 drivers +v0x1c356e0_0 .net "sum", 0 0, L_0x1e0cb50; alias, 1 drivers +S_0x1c35820 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c34ff0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e0ce80/d .functor XOR 1, L_0x1e0cb50, L_0x1e0c7d0, C4<0>, C4<0>; +L_0x1e0ce80 .delay 1 (30000,30000,30000) L_0x1e0ce80/d; +L_0x1e0cfd0/d .functor AND 1, L_0x1e0cb50, L_0x1e0c7d0, C4<1>, C4<1>; +L_0x1e0cfd0 .delay 1 (30000,30000,30000) L_0x1e0cfd0/d; +v0x1c35a80_0 .net "a", 0 0, L_0x1e0cb50; alias, 1 drivers +v0x1c35b20_0 .net "b", 0 0, L_0x1e0c7d0; alias, 1 drivers +v0x1c35bc0_0 .net "carryout", 0 0, L_0x1e0cfd0; alias, 1 drivers +v0x1c35c90_0 .net "sum", 0 0, L_0x1e0ce80; alias, 1 drivers +S_0x1c364b0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c34d70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c3b8a0_0 .net "ands", 7 0, L_0x1e13c00; 1 drivers +v0x1c3b9b0_0 .net "in", 7 0, L_0x1ec05f0; alias, 1 drivers +v0x1c3ba70_0 .net "out", 0 0, L_0x1e15c00; alias, 1 drivers +v0x1c3bb40_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c366d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c364b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c38e00_0 .net "A", 7 0, L_0x1ec05f0; alias, 1 drivers +v0x1c38f00_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c38fc0_0 .net *"_s0", 0 0, L_0x1e12520; 1 drivers +v0x1c39080_0 .net *"_s12", 0 0, L_0x1e12e90; 1 drivers +v0x1c39160_0 .net *"_s16", 0 0, L_0x1e131f0; 1 drivers +v0x1c39290_0 .net *"_s20", 0 0, L_0x1e13500; 1 drivers +v0x1c39370_0 .net *"_s24", 0 0, L_0x1e138f0; 1 drivers +v0x1c39450_0 .net *"_s28", 0 0, L_0x1e13880; 1 drivers +v0x1c39530_0 .net *"_s4", 0 0, L_0x1e12830; 1 drivers +v0x1c396a0_0 .net *"_s8", 0 0, L_0x1e12b80; 1 drivers +v0x1c39780_0 .net "out", 7 0, L_0x1e13c00; alias, 1 drivers +L_0x1e125e0 .part L_0x1ec05f0, 0, 1; +L_0x1e12740 .part v0x1d6daa0_0, 0, 1; +L_0x1e128f0 .part L_0x1ec05f0, 1, 1; +L_0x1e12ae0 .part v0x1d6daa0_0, 1, 1; +L_0x1e12c40 .part L_0x1ec05f0, 2, 1; +L_0x1e12da0 .part v0x1d6daa0_0, 2, 1; +L_0x1e12f50 .part L_0x1ec05f0, 3, 1; +L_0x1e130b0 .part v0x1d6daa0_0, 3, 1; +L_0x1e132b0 .part L_0x1ec05f0, 4, 1; +L_0x1e13410 .part v0x1d6daa0_0, 4, 1; +L_0x1e13570 .part L_0x1ec05f0, 5, 1; +L_0x1e137e0 .part v0x1d6daa0_0, 5, 1; +L_0x1e139b0 .part L_0x1ec05f0, 6, 1; +L_0x1e13b10 .part v0x1d6daa0_0, 6, 1; +LS_0x1e13c00_0_0 .concat8 [ 1 1 1 1], L_0x1e12520, L_0x1e12830, L_0x1e12b80, L_0x1e12e90; +LS_0x1e13c00_0_4 .concat8 [ 1 1 1 1], L_0x1e131f0, L_0x1e13500, L_0x1e138f0, L_0x1e13880; +L_0x1e13c00 .concat8 [ 4 4 0 0], LS_0x1e13c00_0_0, LS_0x1e13c00_0_4; +L_0x1e13fc0 .part L_0x1ec05f0, 7, 1; +L_0x1e141b0 .part v0x1d6daa0_0, 7, 1; +S_0x1c36930 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c36b40 .param/l "i" 0 4 54, +C4<00>; +L_0x1e12520/d .functor AND 1, L_0x1e125e0, L_0x1e12740, C4<1>, C4<1>; +L_0x1e12520 .delay 1 (30000,30000,30000) L_0x1e12520/d; +v0x1c36c20_0 .net *"_s0", 0 0, L_0x1e125e0; 1 drivers +v0x1c36d00_0 .net *"_s1", 0 0, L_0x1e12740; 1 drivers +S_0x1c36de0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c36ff0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e12830/d .functor AND 1, L_0x1e128f0, L_0x1e12ae0, C4<1>, C4<1>; +L_0x1e12830 .delay 1 (30000,30000,30000) L_0x1e12830/d; +v0x1c370b0_0 .net *"_s0", 0 0, L_0x1e128f0; 1 drivers +v0x1c37190_0 .net *"_s1", 0 0, L_0x1e12ae0; 1 drivers +S_0x1c37270 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c37480 .param/l "i" 0 4 54, +C4<010>; +L_0x1e12b80/d .functor AND 1, L_0x1e12c40, L_0x1e12da0, C4<1>, C4<1>; +L_0x1e12b80 .delay 1 (30000,30000,30000) L_0x1e12b80/d; +v0x1c37520_0 .net *"_s0", 0 0, L_0x1e12c40; 1 drivers +v0x1c37600_0 .net *"_s1", 0 0, L_0x1e12da0; 1 drivers +S_0x1c376e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c378f0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e12e90/d .functor AND 1, L_0x1e12f50, L_0x1e130b0, C4<1>, C4<1>; +L_0x1e12e90 .delay 1 (30000,30000,30000) L_0x1e12e90/d; +v0x1c379b0_0 .net *"_s0", 0 0, L_0x1e12f50; 1 drivers +v0x1c37a90_0 .net *"_s1", 0 0, L_0x1e130b0; 1 drivers +S_0x1c37b70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c37dd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e131f0/d .functor AND 1, L_0x1e132b0, L_0x1e13410, C4<1>, C4<1>; +L_0x1e131f0 .delay 1 (30000,30000,30000) L_0x1e131f0/d; +v0x1c37e90_0 .net *"_s0", 0 0, L_0x1e132b0; 1 drivers +v0x1c37f70_0 .net *"_s1", 0 0, L_0x1e13410; 1 drivers +S_0x1c38050 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c38260 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e13500/d .functor AND 1, L_0x1e13570, L_0x1e137e0, C4<1>, C4<1>; +L_0x1e13500 .delay 1 (30000,30000,30000) L_0x1e13500/d; +v0x1c38320_0 .net *"_s0", 0 0, L_0x1e13570; 1 drivers +v0x1c38400_0 .net *"_s1", 0 0, L_0x1e137e0; 1 drivers +S_0x1c384e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c386f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e138f0/d .functor AND 1, L_0x1e139b0, L_0x1e13b10, C4<1>, C4<1>; +L_0x1e138f0 .delay 1 (30000,30000,30000) L_0x1e138f0/d; +v0x1c387b0_0 .net *"_s0", 0 0, L_0x1e139b0; 1 drivers +v0x1c38890_0 .net *"_s1", 0 0, L_0x1e13b10; 1 drivers +S_0x1c38970 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c366d0; + .timescale -9 -12; +P_0x1c38b80 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e13880/d .functor AND 1, L_0x1e13fc0, L_0x1e141b0, C4<1>, C4<1>; +L_0x1e13880 .delay 1 (30000,30000,30000) L_0x1e13880/d; +v0x1c38c40_0 .net *"_s0", 0 0, L_0x1e13fc0; 1 drivers +v0x1c38d20_0 .net *"_s1", 0 0, L_0x1e141b0; 1 drivers +S_0x1c398e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c364b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e15c00/d .functor OR 1, L_0x1e15cc0, L_0x1e15e70, C4<0>, C4<0>; +L_0x1e15c00 .delay 1 (30000,30000,30000) L_0x1e15c00/d; +v0x1c3b430_0 .net *"_s10", 0 0, L_0x1e15cc0; 1 drivers +v0x1c3b510_0 .net *"_s12", 0 0, L_0x1e15e70; 1 drivers +v0x1c3b5f0_0 .net "in", 7 0, L_0x1e13c00; alias, 1 drivers +v0x1c3b6c0_0 .net "ors", 1 0, L_0x1e15a20; 1 drivers +v0x1c3b780_0 .net "out", 0 0, L_0x1e15c00; alias, 1 drivers +L_0x1e14df0 .part L_0x1e13c00, 0, 4; +L_0x1e15a20 .concat8 [ 1 1 0 0], L_0x1e14ae0, L_0x1e15710; +L_0x1e15b60 .part L_0x1e13c00, 4, 4; +L_0x1e15cc0 .part L_0x1e15a20, 0, 1; +L_0x1e15e70 .part L_0x1e15a20, 1, 1; +S_0x1c39aa0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c398e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e142a0/d .functor OR 1, L_0x1e14360, L_0x1e144c0, C4<0>, C4<0>; +L_0x1e142a0 .delay 1 (30000,30000,30000) L_0x1e142a0/d; +L_0x1e146f0/d .functor OR 1, L_0x1e14800, L_0x1e14960, C4<0>, C4<0>; +L_0x1e146f0 .delay 1 (30000,30000,30000) L_0x1e146f0/d; +L_0x1e14ae0/d .functor OR 1, L_0x1e14b50, L_0x1e14d00, C4<0>, C4<0>; +L_0x1e14ae0 .delay 1 (30000,30000,30000) L_0x1e14ae0/d; +v0x1c39cf0_0 .net *"_s0", 0 0, L_0x1e142a0; 1 drivers +v0x1c39df0_0 .net *"_s10", 0 0, L_0x1e14800; 1 drivers +v0x1c39ed0_0 .net *"_s12", 0 0, L_0x1e14960; 1 drivers +v0x1c39f90_0 .net *"_s14", 0 0, L_0x1e14b50; 1 drivers +v0x1c3a070_0 .net *"_s16", 0 0, L_0x1e14d00; 1 drivers +v0x1c3a1a0_0 .net *"_s3", 0 0, L_0x1e14360; 1 drivers +v0x1c3a280_0 .net *"_s5", 0 0, L_0x1e144c0; 1 drivers +v0x1c3a360_0 .net *"_s6", 0 0, L_0x1e146f0; 1 drivers +v0x1c3a440_0 .net "in", 3 0, L_0x1e14df0; 1 drivers +v0x1c3a5b0_0 .net "ors", 1 0, L_0x1e14600; 1 drivers +v0x1c3a690_0 .net "out", 0 0, L_0x1e14ae0; 1 drivers +L_0x1e14360 .part L_0x1e14df0, 0, 1; +L_0x1e144c0 .part L_0x1e14df0, 1, 1; +L_0x1e14600 .concat8 [ 1 1 0 0], L_0x1e142a0, L_0x1e146f0; +L_0x1e14800 .part L_0x1e14df0, 2, 1; +L_0x1e14960 .part L_0x1e14df0, 3, 1; +L_0x1e14b50 .part L_0x1e14600, 0, 1; +L_0x1e14d00 .part L_0x1e14600, 1, 1; +S_0x1c3a7b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c398e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e14f20/d .functor OR 1, L_0x1e14f90, L_0x1e150f0, C4<0>, C4<0>; +L_0x1e14f20 .delay 1 (30000,30000,30000) L_0x1e14f20/d; +L_0x1e15320/d .functor OR 1, L_0x1e15430, L_0x1e15590, C4<0>, C4<0>; +L_0x1e15320 .delay 1 (30000,30000,30000) L_0x1e15320/d; +L_0x1e15710/d .functor OR 1, L_0x1e15780, L_0x1e15930, C4<0>, C4<0>; +L_0x1e15710 .delay 1 (30000,30000,30000) L_0x1e15710/d; +v0x1c3a970_0 .net *"_s0", 0 0, L_0x1e14f20; 1 drivers +v0x1c3aa70_0 .net *"_s10", 0 0, L_0x1e15430; 1 drivers +v0x1c3ab50_0 .net *"_s12", 0 0, L_0x1e15590; 1 drivers +v0x1c3ac10_0 .net *"_s14", 0 0, L_0x1e15780; 1 drivers +v0x1c3acf0_0 .net *"_s16", 0 0, L_0x1e15930; 1 drivers +v0x1c3ae20_0 .net *"_s3", 0 0, L_0x1e14f90; 1 drivers +v0x1c3af00_0 .net *"_s5", 0 0, L_0x1e150f0; 1 drivers +v0x1c3afe0_0 .net *"_s6", 0 0, L_0x1e15320; 1 drivers +v0x1c3b0c0_0 .net "in", 3 0, L_0x1e15b60; 1 drivers +v0x1c3b230_0 .net "ors", 1 0, L_0x1e15230; 1 drivers +v0x1c3b310_0 .net "out", 0 0, L_0x1e15710; 1 drivers +L_0x1e14f90 .part L_0x1e15b60, 0, 1; +L_0x1e150f0 .part L_0x1e15b60, 1, 1; +L_0x1e15230 .concat8 [ 1 1 0 0], L_0x1e14f20, L_0x1e15320; +L_0x1e15430 .part L_0x1e15b60, 2, 1; +L_0x1e15590 .part L_0x1e15b60, 3, 1; +L_0x1e15780 .part L_0x1e15230, 0, 1; +L_0x1e15930 .part L_0x1e15230, 1, 1; +S_0x1c3bc20 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c34d70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c41050_0 .net "ands", 7 0, L_0x1e101c0; 1 drivers +v0x1c41160_0 .net "in", 7 0, L_0x1e0e700; alias, 1 drivers +v0x1c41220_0 .net "out", 0 0, L_0x1e121c0; alias, 1 drivers +v0x1c412f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c3be70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c3bc20; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c3e5b0_0 .net "A", 7 0, L_0x1e0e700; alias, 1 drivers +v0x1c3e6b0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c3e770_0 .net *"_s0", 0 0, L_0x1e0ea90; 1 drivers +v0x1c3e830_0 .net *"_s12", 0 0, L_0x1e0f450; 1 drivers +v0x1c3e910_0 .net *"_s16", 0 0, L_0x1e0f7b0; 1 drivers +v0x1c3ea40_0 .net *"_s20", 0 0, L_0x1e0fb80; 1 drivers +v0x1c3eb20_0 .net *"_s24", 0 0, L_0x1e0feb0; 1 drivers +v0x1c3ec00_0 .net *"_s28", 0 0, L_0x1e0fe40; 1 drivers +v0x1c3ece0_0 .net *"_s4", 0 0, L_0x1e0ee30; 1 drivers +v0x1c3ee50_0 .net *"_s8", 0 0, L_0x1e0f140; 1 drivers +v0x1c3ef30_0 .net "out", 7 0, L_0x1e101c0; alias, 1 drivers +L_0x1e0eba0 .part L_0x1e0e700, 0, 1; +L_0x1e0ed90 .part v0x1d6daa0_0, 0, 1; +L_0x1e0eef0 .part L_0x1e0e700, 1, 1; +L_0x1e0f050 .part v0x1d6daa0_0, 1, 1; +L_0x1e0f200 .part L_0x1e0e700, 2, 1; +L_0x1e0f360 .part v0x1d6daa0_0, 2, 1; +L_0x1e0f510 .part L_0x1e0e700, 3, 1; +L_0x1e0f670 .part v0x1d6daa0_0, 3, 1; +L_0x1e0f870 .part L_0x1e0e700, 4, 1; +L_0x1e0fae0 .part v0x1d6daa0_0, 4, 1; +L_0x1e0fbf0 .part L_0x1e0e700, 5, 1; +L_0x1e0fd50 .part v0x1d6daa0_0, 5, 1; +L_0x1e0ff70 .part L_0x1e0e700, 6, 1; +L_0x1e100d0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e101c0_0_0 .concat8 [ 1 1 1 1], L_0x1e0ea90, L_0x1e0ee30, L_0x1e0f140, L_0x1e0f450; +LS_0x1e101c0_0_4 .concat8 [ 1 1 1 1], L_0x1e0f7b0, L_0x1e0fb80, L_0x1e0feb0, L_0x1e0fe40; +L_0x1e101c0 .concat8 [ 4 4 0 0], LS_0x1e101c0_0_0, LS_0x1e101c0_0_4; +L_0x1e10580 .part L_0x1e0e700, 7, 1; +L_0x1e10770 .part v0x1d6daa0_0, 7, 1; +S_0x1c3c0b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3c2c0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e0ea90/d .functor AND 1, L_0x1e0eba0, L_0x1e0ed90, C4<1>, C4<1>; +L_0x1e0ea90 .delay 1 (30000,30000,30000) L_0x1e0ea90/d; +v0x1c3c3a0_0 .net *"_s0", 0 0, L_0x1e0eba0; 1 drivers +v0x1c3c480_0 .net *"_s1", 0 0, L_0x1e0ed90; 1 drivers +S_0x1c3c560 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3c770 .param/l "i" 0 4 54, +C4<01>; +L_0x1e0ee30/d .functor AND 1, L_0x1e0eef0, L_0x1e0f050, C4<1>, C4<1>; +L_0x1e0ee30 .delay 1 (30000,30000,30000) L_0x1e0ee30/d; +v0x1c3c830_0 .net *"_s0", 0 0, L_0x1e0eef0; 1 drivers +v0x1c3c910_0 .net *"_s1", 0 0, L_0x1e0f050; 1 drivers +S_0x1c3c9f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3cc30 .param/l "i" 0 4 54, +C4<010>; +L_0x1e0f140/d .functor AND 1, L_0x1e0f200, L_0x1e0f360, C4<1>, C4<1>; +L_0x1e0f140 .delay 1 (30000,30000,30000) L_0x1e0f140/d; +v0x1c3ccd0_0 .net *"_s0", 0 0, L_0x1e0f200; 1 drivers +v0x1c3cdb0_0 .net *"_s1", 0 0, L_0x1e0f360; 1 drivers +S_0x1c3ce90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3d0a0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e0f450/d .functor AND 1, L_0x1e0f510, L_0x1e0f670, C4<1>, C4<1>; +L_0x1e0f450 .delay 1 (30000,30000,30000) L_0x1e0f450/d; +v0x1c3d160_0 .net *"_s0", 0 0, L_0x1e0f510; 1 drivers +v0x1c3d240_0 .net *"_s1", 0 0, L_0x1e0f670; 1 drivers +S_0x1c3d320 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3d580 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e0f7b0/d .functor AND 1, L_0x1e0f870, L_0x1e0fae0, C4<1>, C4<1>; +L_0x1e0f7b0 .delay 1 (30000,30000,30000) L_0x1e0f7b0/d; +v0x1c3d640_0 .net *"_s0", 0 0, L_0x1e0f870; 1 drivers +v0x1c3d720_0 .net *"_s1", 0 0, L_0x1e0fae0; 1 drivers +S_0x1c3d800 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3da10 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e0fb80/d .functor AND 1, L_0x1e0fbf0, L_0x1e0fd50, C4<1>, C4<1>; +L_0x1e0fb80 .delay 1 (30000,30000,30000) L_0x1e0fb80/d; +v0x1c3dad0_0 .net *"_s0", 0 0, L_0x1e0fbf0; 1 drivers +v0x1c3dbb0_0 .net *"_s1", 0 0, L_0x1e0fd50; 1 drivers +S_0x1c3dc90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3dea0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e0feb0/d .functor AND 1, L_0x1e0ff70, L_0x1e100d0, C4<1>, C4<1>; +L_0x1e0feb0 .delay 1 (30000,30000,30000) L_0x1e0feb0/d; +v0x1c3df60_0 .net *"_s0", 0 0, L_0x1e0ff70; 1 drivers +v0x1c3e040_0 .net *"_s1", 0 0, L_0x1e100d0; 1 drivers +S_0x1c3e120 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c3be70; + .timescale -9 -12; +P_0x1c3e330 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e0fe40/d .functor AND 1, L_0x1e10580, L_0x1e10770, C4<1>, C4<1>; +L_0x1e0fe40 .delay 1 (30000,30000,30000) L_0x1e0fe40/d; +v0x1c3e3f0_0 .net *"_s0", 0 0, L_0x1e10580; 1 drivers +v0x1c3e4d0_0 .net *"_s1", 0 0, L_0x1e10770; 1 drivers +S_0x1c3f090 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c3bc20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e121c0/d .functor OR 1, L_0x1e12280, L_0x1e12430, C4<0>, C4<0>; +L_0x1e121c0 .delay 1 (30000,30000,30000) L_0x1e121c0/d; +v0x1c40be0_0 .net *"_s10", 0 0, L_0x1e12280; 1 drivers +v0x1c40cc0_0 .net *"_s12", 0 0, L_0x1e12430; 1 drivers +v0x1c40da0_0 .net "in", 7 0, L_0x1e101c0; alias, 1 drivers +v0x1c40e70_0 .net "ors", 1 0, L_0x1e11fe0; 1 drivers +v0x1c40f30_0 .net "out", 0 0, L_0x1e121c0; alias, 1 drivers +L_0x1e113b0 .part L_0x1e101c0, 0, 4; +L_0x1e11fe0 .concat8 [ 1 1 0 0], L_0x1e110a0, L_0x1e11cd0; +L_0x1e12120 .part L_0x1e101c0, 4, 4; +L_0x1e12280 .part L_0x1e11fe0, 0, 1; +L_0x1e12430 .part L_0x1e11fe0, 1, 1; +S_0x1c3f250 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c3f090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e10860/d .functor OR 1, L_0x1e10920, L_0x1e10a80, C4<0>, C4<0>; +L_0x1e10860 .delay 1 (30000,30000,30000) L_0x1e10860/d; +L_0x1e10cb0/d .functor OR 1, L_0x1e10dc0, L_0x1e10f20, C4<0>, C4<0>; +L_0x1e10cb0 .delay 1 (30000,30000,30000) L_0x1e10cb0/d; +L_0x1e110a0/d .functor OR 1, L_0x1e11110, L_0x1e112c0, C4<0>, C4<0>; +L_0x1e110a0 .delay 1 (30000,30000,30000) L_0x1e110a0/d; +v0x1c3f4a0_0 .net *"_s0", 0 0, L_0x1e10860; 1 drivers +v0x1c3f5a0_0 .net *"_s10", 0 0, L_0x1e10dc0; 1 drivers +v0x1c3f680_0 .net *"_s12", 0 0, L_0x1e10f20; 1 drivers +v0x1c3f740_0 .net *"_s14", 0 0, L_0x1e11110; 1 drivers +v0x1c3f820_0 .net *"_s16", 0 0, L_0x1e112c0; 1 drivers +v0x1c3f950_0 .net *"_s3", 0 0, L_0x1e10920; 1 drivers +v0x1c3fa30_0 .net *"_s5", 0 0, L_0x1e10a80; 1 drivers +v0x1c3fb10_0 .net *"_s6", 0 0, L_0x1e10cb0; 1 drivers +v0x1c3fbf0_0 .net "in", 3 0, L_0x1e113b0; 1 drivers +v0x1c3fd60_0 .net "ors", 1 0, L_0x1e10bc0; 1 drivers +v0x1c3fe40_0 .net "out", 0 0, L_0x1e110a0; 1 drivers +L_0x1e10920 .part L_0x1e113b0, 0, 1; +L_0x1e10a80 .part L_0x1e113b0, 1, 1; +L_0x1e10bc0 .concat8 [ 1 1 0 0], L_0x1e10860, L_0x1e10cb0; +L_0x1e10dc0 .part L_0x1e113b0, 2, 1; +L_0x1e10f20 .part L_0x1e113b0, 3, 1; +L_0x1e11110 .part L_0x1e10bc0, 0, 1; +L_0x1e112c0 .part L_0x1e10bc0, 1, 1; +S_0x1c3ff60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c3f090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e114e0/d .functor OR 1, L_0x1e11550, L_0x1e116b0, C4<0>, C4<0>; +L_0x1e114e0 .delay 1 (30000,30000,30000) L_0x1e114e0/d; +L_0x1e118e0/d .functor OR 1, L_0x1e119f0, L_0x1e11b50, C4<0>, C4<0>; +L_0x1e118e0 .delay 1 (30000,30000,30000) L_0x1e118e0/d; +L_0x1e11cd0/d .functor OR 1, L_0x1e11d40, L_0x1e11ef0, C4<0>, C4<0>; +L_0x1e11cd0 .delay 1 (30000,30000,30000) L_0x1e11cd0/d; +v0x1c40120_0 .net *"_s0", 0 0, L_0x1e114e0; 1 drivers +v0x1c40220_0 .net *"_s10", 0 0, L_0x1e119f0; 1 drivers +v0x1c40300_0 .net *"_s12", 0 0, L_0x1e11b50; 1 drivers +v0x1c403c0_0 .net *"_s14", 0 0, L_0x1e11d40; 1 drivers +v0x1c404a0_0 .net *"_s16", 0 0, L_0x1e11ef0; 1 drivers +v0x1c405d0_0 .net *"_s3", 0 0, L_0x1e11550; 1 drivers +v0x1c406b0_0 .net *"_s5", 0 0, L_0x1e116b0; 1 drivers +v0x1c40790_0 .net *"_s6", 0 0, L_0x1e118e0; 1 drivers +v0x1c40870_0 .net "in", 3 0, L_0x1e12120; 1 drivers +v0x1c409e0_0 .net "ors", 1 0, L_0x1e117f0; 1 drivers +v0x1c40ac0_0 .net "out", 0 0, L_0x1e11cd0; 1 drivers +L_0x1e11550 .part L_0x1e12120, 0, 1; +L_0x1e116b0 .part L_0x1e12120, 1, 1; +L_0x1e117f0 .concat8 [ 1 1 0 0], L_0x1e114e0, L_0x1e118e0; +L_0x1e119f0 .part L_0x1e12120, 2, 1; +L_0x1e11b50 .part L_0x1e12120, 3, 1; +L_0x1e11d40 .part L_0x1e117f0, 0, 1; +L_0x1e11ef0 .part L_0x1e117f0, 1, 1; +S_0x1c413d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c34d70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e0da70/d .functor XNOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; +L_0x1e0da70 .delay 1 (20000,20000,20000) L_0x1e0da70/d; +L_0x1e0dce0/d .functor AND 1, L_0x1e16060, L_0x1e0c960, C4<1>, C4<1>; +L_0x1e0dce0 .delay 1 (30000,30000,30000) L_0x1e0dce0/d; +L_0x1e0dd50/d .functor AND 1, L_0x1e0da70, L_0x1e0c7d0, C4<1>, C4<1>; +L_0x1e0dd50 .delay 1 (30000,30000,30000) L_0x1e0dd50/d; +L_0x1e0deb0/d .functor OR 1, L_0x1e0dd50, L_0x1e0dce0, C4<0>, C4<0>; +L_0x1e0deb0 .delay 1 (30000,30000,30000) L_0x1e0deb0/d; +v0x1c41680_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers +v0x1c41770_0 .net "a_", 0 0, L_0x1e0c440; alias, 1 drivers +v0x1c41830_0 .net "b", 0 0, L_0x1e161c0; alias, 1 drivers +v0x1c41920_0 .net "b_", 0 0, L_0x1e0c960; alias, 1 drivers +v0x1c419c0_0 .net "carryin", 0 0, L_0x1e0c7d0; alias, 1 drivers +v0x1c41b00_0 .net "eq", 0 0, L_0x1e0da70; 1 drivers +v0x1c41bc0_0 .net "lt", 0 0, L_0x1e0dce0; 1 drivers +v0x1c41c80_0 .net "out", 0 0, L_0x1e0deb0; 1 drivers +v0x1c41d40_0 .net "w0", 0 0, L_0x1e0dd50; 1 drivers +S_0x1c41f90 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c34d70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e0d850/d .functor OR 1, L_0x1e0d350, L_0x1c431f0, C4<0>, C4<0>; +L_0x1e0d850 .delay 1 (30000,30000,30000) L_0x1e0d850/d; +v0x1c42d80_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers +v0x1c42ed0_0 .net "b", 0 0, L_0x1e0c960; alias, 1 drivers +v0x1c42f90_0 .net "c1", 0 0, L_0x1e0d350; 1 drivers +v0x1c43030_0 .net "c2", 0 0, L_0x1c431f0; 1 drivers +v0x1c43100_0 .net "carryin", 0 0, L_0x1e0c7d0; alias, 1 drivers +v0x1c43280_0 .net "carryout", 0 0, L_0x1e0d850; 1 drivers +v0x1c43320_0 .net "s1", 0 0, L_0x1e0d290; 1 drivers +v0x1c433c0_0 .net "sum", 0 0, L_0x1e0d4b0; 1 drivers +S_0x1c421e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c41f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e0d290/d .functor XOR 1, L_0x1e16060, L_0x1e0c960, C4<0>, C4<0>; +L_0x1e0d290 .delay 1 (30000,30000,30000) L_0x1e0d290/d; +L_0x1e0d350/d .functor AND 1, L_0x1e16060, L_0x1e0c960, C4<1>, C4<1>; +L_0x1e0d350 .delay 1 (30000,30000,30000) L_0x1e0d350/d; +v0x1c42440_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers +v0x1c42500_0 .net "b", 0 0, L_0x1e0c960; alias, 1 drivers +v0x1c425c0_0 .net "carryout", 0 0, L_0x1e0d350; alias, 1 drivers +v0x1c42660_0 .net "sum", 0 0, L_0x1e0d290; alias, 1 drivers +S_0x1c42790 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c41f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e0d4b0/d .functor XOR 1, L_0x1e0d290, L_0x1e0c7d0, C4<0>, C4<0>; +L_0x1e0d4b0 .delay 1 (30000,30000,30000) L_0x1e0d4b0/d; +L_0x1c431f0/d .functor AND 1, L_0x1e0d290, L_0x1e0c7d0, C4<1>, C4<1>; +L_0x1c431f0 .delay 1 (30000,30000,30000) L_0x1c431f0/d; +v0x1c429f0_0 .net "a", 0 0, L_0x1e0d290; alias, 1 drivers +v0x1c42ac0_0 .net "b", 0 0, L_0x1e0c7d0; alias, 1 drivers +v0x1c42b60_0 .net "carryout", 0 0, L_0x1c431f0; alias, 1 drivers +v0x1c42c30_0 .net "sum", 0 0, L_0x1e0d4b0; alias, 1 drivers +S_0x1c447e0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c34a00; + .timescale -9 -12; +L_0x7f72592db218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db260 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e16100/d .functor OR 1, L_0x7f72592db218, L_0x7f72592db260, C4<0>, C4<0>; +L_0x1e16100 .delay 1 (30000,30000,30000) L_0x1e16100/d; +v0x1c449d0_0 .net/2u *"_s0", 0 0, L_0x7f72592db218; 1 drivers +v0x1c44ab0_0 .net/2u *"_s2", 0 0, L_0x7f72592db260; 1 drivers +S_0x1c44b90 .scope generate, "alu_slices[17]" "alu_slices[17]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c44da0 .param/l "i" 0 3 37, +C4<010001>; +S_0x1c44e60 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c44b90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e063c0/d .functor NOT 1, L_0x1e1fec0, C4<0>, C4<0>, C4<0>; +L_0x1e063c0 .delay 1 (10000,10000,10000) L_0x1e063c0/d; +L_0x1dc8070/d .functor NOT 1, L_0x1e16260, C4<0>, C4<0>, C4<0>; +L_0x1dc8070 .delay 1 (10000,10000,10000) L_0x1dc8070/d; +L_0x1e17700/d .functor XOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; +L_0x1e17700 .delay 1 (30000,30000,30000) L_0x1e17700/d; +L_0x7f72592db2a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db2f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e17db0/d .functor OR 1, L_0x7f72592db2a8, L_0x7f72592db2f0, C4<0>, C4<0>; +L_0x1e17db0 .delay 1 (30000,30000,30000) L_0x1e17db0/d; +L_0x1e17fb0/d .functor AND 1, L_0x1e1fec0, L_0x1e16260, C4<1>, C4<1>; +L_0x1e17fb0 .delay 1 (30000,30000,30000) L_0x1e17fb0/d; +L_0x1e18070/d .functor NAND 1, L_0x1e1fec0, L_0x1e16260, C4<1>, C4<1>; +L_0x1e18070 .delay 1 (20000,20000,20000) L_0x1e18070/d; +L_0x1e181d0/d .functor XOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; +L_0x1e181d0 .delay 1 (20000,20000,20000) L_0x1e181d0/d; +L_0x1e18680/d .functor OR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; +L_0x1e18680 .delay 1 (30000,30000,30000) L_0x1e18680/d; +L_0x1e1fdc0/d .functor NOT 1, L_0x1e1bfc0, C4<0>, C4<0>, C4<0>; +L_0x1e1fdc0 .delay 1 (10000,10000,10000) L_0x1e1fdc0/d; +v0x1c535b0_0 .net "A", 0 0, L_0x1e1fec0; 1 drivers +v0x1c53670_0 .net "A_", 0 0, L_0x1e063c0; 1 drivers +v0x1c53730_0 .net "B", 0 0, L_0x1e16260; 1 drivers +v0x1c53800_0 .net "B_", 0 0, L_0x1dc8070; 1 drivers +v0x1c538a0_0 .net *"_s12", 0 0, L_0x1e17db0; 1 drivers +v0x1c53990_0 .net/2s *"_s14", 0 0, L_0x7f72592db2a8; 1 drivers +v0x1c53a50_0 .net/2s *"_s16", 0 0, L_0x7f72592db2f0; 1 drivers +v0x1c53b30_0 .net *"_s18", 0 0, L_0x1e17fb0; 1 drivers +v0x1c53c10_0 .net *"_s20", 0 0, L_0x1e18070; 1 drivers +v0x1c53d80_0 .net *"_s22", 0 0, L_0x1e181d0; 1 drivers +v0x1c53e60_0 .net *"_s24", 0 0, L_0x1e18680; 1 drivers +o0x7f725937dd18 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c53f40_0 name=_s30 +o0x7f725937dd48 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c54020_0 name=_s32 +v0x1c54100_0 .net *"_s8", 0 0, L_0x1e17700; 1 drivers +v0x1c541e0_0 .net "carryin", 0 0, L_0x1e16300; 1 drivers +v0x1c54280_0 .net "carryout", 0 0, L_0x1e1fa60; 1 drivers +v0x1c54320_0 .net "carryouts", 7 0, L_0x1ec07c0; 1 drivers +v0x1c544d0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c54570_0 .net "result", 0 0, L_0x1e1bfc0; 1 drivers +v0x1c54660_0 .net "results", 7 0, L_0x1e18450; 1 drivers +v0x1c54770_0 .net "zero", 0 0, L_0x1e1fdc0; 1 drivers +LS_0x1e18450_0_0 .concat8 [ 1 1 1 1], L_0x1e16bd0, L_0x1e17200, L_0x1e17700, L_0x1e17db0; +LS_0x1e18450_0_4 .concat8 [ 1 1 1 1], L_0x1e17fb0, L_0x1e18070, L_0x1e181d0, L_0x1e18680; +L_0x1e18450 .concat8 [ 4 4 0 0], LS_0x1e18450_0_0, LS_0x1e18450_0_4; +LS_0x1ec07c0_0_0 .concat [ 1 1 1 1], L_0x1e16e80, L_0x1e175a0, o0x7f725937dd18, L_0x1e17c00; +LS_0x1ec07c0_0_4 .concat [ 4 0 0 0], o0x7f725937dd48; +L_0x1ec07c0 .concat [ 4 4 0 0], LS_0x1ec07c0_0_0, LS_0x1ec07c0_0_4; +S_0x1c450e0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c44e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e16e80/d .functor OR 1, L_0x1e16960, L_0x1e16d20, C4<0>, C4<0>; +L_0x1e16e80 .delay 1 (30000,30000,30000) L_0x1e16e80/d; +v0x1c45f10_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers +v0x1c45fd0_0 .net "b", 0 0, L_0x1e16260; alias, 1 drivers +v0x1c460a0_0 .net "c1", 0 0, L_0x1e16960; 1 drivers +v0x1c461a0_0 .net "c2", 0 0, L_0x1e16d20; 1 drivers +v0x1c46270_0 .net "carryin", 0 0, L_0x1e16300; alias, 1 drivers +v0x1c46360_0 .net "carryout", 0 0, L_0x1e16e80; 1 drivers +v0x1c46400_0 .net "s1", 0 0, L_0x1e168a0; 1 drivers +v0x1c464f0_0 .net "sum", 0 0, L_0x1e16bd0; 1 drivers +S_0x1c45350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c450e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e168a0/d .functor XOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; +L_0x1e168a0 .delay 1 (30000,30000,30000) L_0x1e168a0/d; +L_0x1e16960/d .functor AND 1, L_0x1e1fec0, L_0x1e16260, C4<1>, C4<1>; +L_0x1e16960 .delay 1 (30000,30000,30000) L_0x1e16960/d; +v0x1c455b0_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers +v0x1c45690_0 .net "b", 0 0, L_0x1e16260; alias, 1 drivers +v0x1c45750_0 .net "carryout", 0 0, L_0x1e16960; alias, 1 drivers +v0x1c457f0_0 .net "sum", 0 0, L_0x1e168a0; alias, 1 drivers +S_0x1c45930 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c450e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e16bd0/d .functor XOR 1, L_0x1e168a0, L_0x1e16300, C4<0>, C4<0>; +L_0x1e16bd0 .delay 1 (30000,30000,30000) L_0x1e16bd0/d; +L_0x1e16d20/d .functor AND 1, L_0x1e168a0, L_0x1e16300, C4<1>, C4<1>; +L_0x1e16d20 .delay 1 (30000,30000,30000) L_0x1e16d20/d; +v0x1c45b90_0 .net "a", 0 0, L_0x1e168a0; alias, 1 drivers +v0x1c45c30_0 .net "b", 0 0, L_0x1e16300; alias, 1 drivers +v0x1c45cd0_0 .net "carryout", 0 0, L_0x1e16d20; alias, 1 drivers +v0x1c45da0_0 .net "sum", 0 0, L_0x1e16bd0; alias, 1 drivers +S_0x1c465c0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c44e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c4b9b0_0 .net "ands", 7 0, L_0x1e1da60; 1 drivers +v0x1c4bac0_0 .net "in", 7 0, L_0x1ec07c0; alias, 1 drivers +v0x1c4bb80_0 .net "out", 0 0, L_0x1e1fa60; alias, 1 drivers +v0x1c4bc50_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c467e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c465c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c48f10_0 .net "A", 7 0, L_0x1ec07c0; alias, 1 drivers +v0x1c49010_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c490d0_0 .net *"_s0", 0 0, L_0x1e1c320; 1 drivers +v0x1c49190_0 .net *"_s12", 0 0, L_0x1e1cc90; 1 drivers +v0x1c49270_0 .net *"_s16", 0 0, L_0x1e1cff0; 1 drivers +v0x1c493a0_0 .net *"_s20", 0 0, L_0x1e1d360; 1 drivers +v0x1c49480_0 .net *"_s24", 0 0, L_0x1e1d750; 1 drivers +v0x1c49560_0 .net *"_s28", 0 0, L_0x1e1d6e0; 1 drivers +v0x1c49640_0 .net *"_s4", 0 0, L_0x1e1c630; 1 drivers +v0x1c497b0_0 .net *"_s8", 0 0, L_0x1e1c980; 1 drivers +v0x1c49890_0 .net "out", 7 0, L_0x1e1da60; alias, 1 drivers +L_0x1e1c3e0 .part L_0x1ec07c0, 0, 1; +L_0x1e1c540 .part v0x1d6daa0_0, 0, 1; +L_0x1e1c6f0 .part L_0x1ec07c0, 1, 1; +L_0x1e1c8e0 .part v0x1d6daa0_0, 1, 1; +L_0x1e1ca40 .part L_0x1ec07c0, 2, 1; +L_0x1e1cba0 .part v0x1d6daa0_0, 2, 1; +L_0x1e1cd50 .part L_0x1ec07c0, 3, 1; +L_0x1e1ceb0 .part v0x1d6daa0_0, 3, 1; +L_0x1e1d0b0 .part L_0x1ec07c0, 4, 1; +L_0x1e1d210 .part v0x1d6daa0_0, 4, 1; +L_0x1e1d3d0 .part L_0x1ec07c0, 5, 1; +L_0x1e1d640 .part v0x1d6daa0_0, 5, 1; +L_0x1e1d810 .part L_0x1ec07c0, 6, 1; +L_0x1e1d970 .part v0x1d6daa0_0, 6, 1; +LS_0x1e1da60_0_0 .concat8 [ 1 1 1 1], L_0x1e1c320, L_0x1e1c630, L_0x1e1c980, L_0x1e1cc90; +LS_0x1e1da60_0_4 .concat8 [ 1 1 1 1], L_0x1e1cff0, L_0x1e1d360, L_0x1e1d750, L_0x1e1d6e0; +L_0x1e1da60 .concat8 [ 4 4 0 0], LS_0x1e1da60_0_0, LS_0x1e1da60_0_4; +L_0x1e1de20 .part L_0x1ec07c0, 7, 1; +L_0x1e1e010 .part v0x1d6daa0_0, 7, 1; +S_0x1c46a40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c46c50 .param/l "i" 0 4 54, +C4<00>; +L_0x1e1c320/d .functor AND 1, L_0x1e1c3e0, L_0x1e1c540, C4<1>, C4<1>; +L_0x1e1c320 .delay 1 (30000,30000,30000) L_0x1e1c320/d; +v0x1c46d30_0 .net *"_s0", 0 0, L_0x1e1c3e0; 1 drivers +v0x1c46e10_0 .net *"_s1", 0 0, L_0x1e1c540; 1 drivers +S_0x1c46ef0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c47100 .param/l "i" 0 4 54, +C4<01>; +L_0x1e1c630/d .functor AND 1, L_0x1e1c6f0, L_0x1e1c8e0, C4<1>, C4<1>; +L_0x1e1c630 .delay 1 (30000,30000,30000) L_0x1e1c630/d; +v0x1c471c0_0 .net *"_s0", 0 0, L_0x1e1c6f0; 1 drivers +v0x1c472a0_0 .net *"_s1", 0 0, L_0x1e1c8e0; 1 drivers +S_0x1c47380 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c47590 .param/l "i" 0 4 54, +C4<010>; +L_0x1e1c980/d .functor AND 1, L_0x1e1ca40, L_0x1e1cba0, C4<1>, C4<1>; +L_0x1e1c980 .delay 1 (30000,30000,30000) L_0x1e1c980/d; +v0x1c47630_0 .net *"_s0", 0 0, L_0x1e1ca40; 1 drivers +v0x1c47710_0 .net *"_s1", 0 0, L_0x1e1cba0; 1 drivers +S_0x1c477f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c47a00 .param/l "i" 0 4 54, +C4<011>; +L_0x1e1cc90/d .functor AND 1, L_0x1e1cd50, L_0x1e1ceb0, C4<1>, C4<1>; +L_0x1e1cc90 .delay 1 (30000,30000,30000) L_0x1e1cc90/d; +v0x1c47ac0_0 .net *"_s0", 0 0, L_0x1e1cd50; 1 drivers +v0x1c47ba0_0 .net *"_s1", 0 0, L_0x1e1ceb0; 1 drivers +S_0x1c47c80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c47ee0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e1cff0/d .functor AND 1, L_0x1e1d0b0, L_0x1e1d210, C4<1>, C4<1>; +L_0x1e1cff0 .delay 1 (30000,30000,30000) L_0x1e1cff0/d; +v0x1c47fa0_0 .net *"_s0", 0 0, L_0x1e1d0b0; 1 drivers +v0x1c48080_0 .net *"_s1", 0 0, L_0x1e1d210; 1 drivers +S_0x1c48160 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c48370 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e1d360/d .functor AND 1, L_0x1e1d3d0, L_0x1e1d640, C4<1>, C4<1>; +L_0x1e1d360 .delay 1 (30000,30000,30000) L_0x1e1d360/d; +v0x1c48430_0 .net *"_s0", 0 0, L_0x1e1d3d0; 1 drivers +v0x1c48510_0 .net *"_s1", 0 0, L_0x1e1d640; 1 drivers +S_0x1c485f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c48800 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e1d750/d .functor AND 1, L_0x1e1d810, L_0x1e1d970, C4<1>, C4<1>; +L_0x1e1d750 .delay 1 (30000,30000,30000) L_0x1e1d750/d; +v0x1c488c0_0 .net *"_s0", 0 0, L_0x1e1d810; 1 drivers +v0x1c489a0_0 .net *"_s1", 0 0, L_0x1e1d970; 1 drivers +S_0x1c48a80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c467e0; + .timescale -9 -12; +P_0x1c48c90 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e1d6e0/d .functor AND 1, L_0x1e1de20, L_0x1e1e010, C4<1>, C4<1>; +L_0x1e1d6e0 .delay 1 (30000,30000,30000) L_0x1e1d6e0/d; +v0x1c48d50_0 .net *"_s0", 0 0, L_0x1e1de20; 1 drivers +v0x1c48e30_0 .net *"_s1", 0 0, L_0x1e1e010; 1 drivers +S_0x1c499f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c465c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e1fa60/d .functor OR 1, L_0x1e1fb20, L_0x1e1fcd0, C4<0>, C4<0>; +L_0x1e1fa60 .delay 1 (30000,30000,30000) L_0x1e1fa60/d; +v0x1c4b540_0 .net *"_s10", 0 0, L_0x1e1fb20; 1 drivers +v0x1c4b620_0 .net *"_s12", 0 0, L_0x1e1fcd0; 1 drivers +v0x1c4b700_0 .net "in", 7 0, L_0x1e1da60; alias, 1 drivers +v0x1c4b7d0_0 .net "ors", 1 0, L_0x1e1f880; 1 drivers +v0x1c4b890_0 .net "out", 0 0, L_0x1e1fa60; alias, 1 drivers +L_0x1e1ec50 .part L_0x1e1da60, 0, 4; +L_0x1e1f880 .concat8 [ 1 1 0 0], L_0x1e1e940, L_0x1e1f570; +L_0x1e1f9c0 .part L_0x1e1da60, 4, 4; +L_0x1e1fb20 .part L_0x1e1f880, 0, 1; +L_0x1e1fcd0 .part L_0x1e1f880, 1, 1; +S_0x1c49bb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c499f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e1e100/d .functor OR 1, L_0x1e1e1c0, L_0x1e1e320, C4<0>, C4<0>; +L_0x1e1e100 .delay 1 (30000,30000,30000) L_0x1e1e100/d; +L_0x1e1e550/d .functor OR 1, L_0x1e1e660, L_0x1e1e7c0, C4<0>, C4<0>; +L_0x1e1e550 .delay 1 (30000,30000,30000) L_0x1e1e550/d; +L_0x1e1e940/d .functor OR 1, L_0x1e1e9b0, L_0x1e1eb60, C4<0>, C4<0>; +L_0x1e1e940 .delay 1 (30000,30000,30000) L_0x1e1e940/d; +v0x1c49e00_0 .net *"_s0", 0 0, L_0x1e1e100; 1 drivers +v0x1c49f00_0 .net *"_s10", 0 0, L_0x1e1e660; 1 drivers +v0x1c49fe0_0 .net *"_s12", 0 0, L_0x1e1e7c0; 1 drivers +v0x1c4a0a0_0 .net *"_s14", 0 0, L_0x1e1e9b0; 1 drivers +v0x1c4a180_0 .net *"_s16", 0 0, L_0x1e1eb60; 1 drivers +v0x1c4a2b0_0 .net *"_s3", 0 0, L_0x1e1e1c0; 1 drivers +v0x1c4a390_0 .net *"_s5", 0 0, L_0x1e1e320; 1 drivers +v0x1c4a470_0 .net *"_s6", 0 0, L_0x1e1e550; 1 drivers +v0x1c4a550_0 .net "in", 3 0, L_0x1e1ec50; 1 drivers +v0x1c4a6c0_0 .net "ors", 1 0, L_0x1e1e460; 1 drivers +v0x1c4a7a0_0 .net "out", 0 0, L_0x1e1e940; 1 drivers +L_0x1e1e1c0 .part L_0x1e1ec50, 0, 1; +L_0x1e1e320 .part L_0x1e1ec50, 1, 1; +L_0x1e1e460 .concat8 [ 1 1 0 0], L_0x1e1e100, L_0x1e1e550; +L_0x1e1e660 .part L_0x1e1ec50, 2, 1; +L_0x1e1e7c0 .part L_0x1e1ec50, 3, 1; +L_0x1e1e9b0 .part L_0x1e1e460, 0, 1; +L_0x1e1eb60 .part L_0x1e1e460, 1, 1; +S_0x1c4a8c0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c499f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e1ed80/d .functor OR 1, L_0x1e1edf0, L_0x1e1ef50, C4<0>, C4<0>; +L_0x1e1ed80 .delay 1 (30000,30000,30000) L_0x1e1ed80/d; +L_0x1e1f180/d .functor OR 1, L_0x1e1f290, L_0x1e1f3f0, C4<0>, C4<0>; +L_0x1e1f180 .delay 1 (30000,30000,30000) L_0x1e1f180/d; +L_0x1e1f570/d .functor OR 1, L_0x1e1f5e0, L_0x1e1f790, C4<0>, C4<0>; +L_0x1e1f570 .delay 1 (30000,30000,30000) L_0x1e1f570/d; +v0x1c4aa80_0 .net *"_s0", 0 0, L_0x1e1ed80; 1 drivers +v0x1c4ab80_0 .net *"_s10", 0 0, L_0x1e1f290; 1 drivers +v0x1c4ac60_0 .net *"_s12", 0 0, L_0x1e1f3f0; 1 drivers +v0x1c4ad20_0 .net *"_s14", 0 0, L_0x1e1f5e0; 1 drivers +v0x1c4ae00_0 .net *"_s16", 0 0, L_0x1e1f790; 1 drivers +v0x1c4af30_0 .net *"_s3", 0 0, L_0x1e1edf0; 1 drivers +v0x1c4b010_0 .net *"_s5", 0 0, L_0x1e1ef50; 1 drivers +v0x1c4b0f0_0 .net *"_s6", 0 0, L_0x1e1f180; 1 drivers +v0x1c4b1d0_0 .net "in", 3 0, L_0x1e1f9c0; 1 drivers +v0x1c4b340_0 .net "ors", 1 0, L_0x1e1f090; 1 drivers +v0x1c4b420_0 .net "out", 0 0, L_0x1e1f570; 1 drivers +L_0x1e1edf0 .part L_0x1e1f9c0, 0, 1; +L_0x1e1ef50 .part L_0x1e1f9c0, 1, 1; +L_0x1e1f090 .concat8 [ 1 1 0 0], L_0x1e1ed80, L_0x1e1f180; +L_0x1e1f290 .part L_0x1e1f9c0, 2, 1; +L_0x1e1f3f0 .part L_0x1e1f9c0, 3, 1; +L_0x1e1f5e0 .part L_0x1e1f090, 0, 1; +L_0x1e1f790 .part L_0x1e1f090, 1, 1; +S_0x1c4bd30 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c44e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c51180_0 .net "ands", 7 0, L_0x1e19ff0; 1 drivers +v0x1c51290_0 .net "in", 7 0, L_0x1e18450; alias, 1 drivers +v0x1c51350_0 .net "out", 0 0, L_0x1e1bfc0; alias, 1 drivers +v0x1c51420_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c4bf80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c4bd30; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c4e6c0_0 .net "A", 7 0, L_0x1e18450; alias, 1 drivers +v0x1c4e7c0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c4e880_0 .net *"_s0", 0 0, L_0x1e187e0; 1 drivers +v0x1c4e940_0 .net *"_s12", 0 0, L_0x1e191a0; 1 drivers +v0x1c4ea20_0 .net *"_s16", 0 0, L_0x1e19500; 1 drivers +v0x1c4eb50_0 .net *"_s20", 0 0, L_0x1e19930; 1 drivers +v0x1c4ec30_0 .net *"_s24", 0 0, L_0x1e19c60; 1 drivers +v0x1c4ed10_0 .net *"_s28", 0 0, L_0x1e1a270; 1 drivers +v0x1c4edf0_0 .net *"_s4", 0 0, L_0x1e18b80; 1 drivers +v0x1c4ef60_0 .net *"_s8", 0 0, L_0x1e18e90; 1 drivers +v0x1c4f000_0 .net "out", 7 0, L_0x1e19ff0; alias, 1 drivers +L_0x1e188f0 .part L_0x1e18450, 0, 1; +L_0x1e18ae0 .part v0x1d6daa0_0, 0, 1; +L_0x1e18c40 .part L_0x1e18450, 1, 1; +L_0x1e18da0 .part v0x1d6daa0_0, 1, 1; +L_0x1e18f50 .part L_0x1e18450, 2, 1; +L_0x1e190b0 .part v0x1d6daa0_0, 2, 1; +L_0x1e19260 .part L_0x1e18450, 3, 1; +L_0x1e193c0 .part v0x1d6daa0_0, 3, 1; +L_0x1e195c0 .part L_0x1e18450, 4, 1; +L_0x1e19830 .part v0x1d6daa0_0, 4, 1; +L_0x1e199a0 .part L_0x1e18450, 5, 1; +L_0x1e19b00 .part v0x1d6daa0_0, 5, 1; +L_0x1e19d20 .part L_0x1e18450, 6, 1; +L_0x1e19e80 .part v0x1d6daa0_0, 6, 1; +LS_0x1e19ff0_0_0 .concat8 [ 1 1 1 1], L_0x1e187e0, L_0x1e18b80, L_0x1e18e90, L_0x1e191a0; +LS_0x1e19ff0_0_4 .concat8 [ 1 1 1 1], L_0x1e19500, L_0x1e19930, L_0x1e19c60, L_0x1e1a270; +L_0x1e19ff0 .concat8 [ 4 4 0 0], LS_0x1e19ff0_0_0, LS_0x1e19ff0_0_4; +L_0x1e1a380 .part L_0x1e18450, 7, 1; +L_0x1e1a570 .part v0x1d6daa0_0, 7, 1; +S_0x1c4c1c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4c3d0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e187e0/d .functor AND 1, L_0x1e188f0, L_0x1e18ae0, C4<1>, C4<1>; +L_0x1e187e0 .delay 1 (30000,30000,30000) L_0x1e187e0/d; +v0x1c4c4b0_0 .net *"_s0", 0 0, L_0x1e188f0; 1 drivers +v0x1c4c590_0 .net *"_s1", 0 0, L_0x1e18ae0; 1 drivers +S_0x1c4c670 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4c880 .param/l "i" 0 4 54, +C4<01>; +L_0x1e18b80/d .functor AND 1, L_0x1e18c40, L_0x1e18da0, C4<1>, C4<1>; +L_0x1e18b80 .delay 1 (30000,30000,30000) L_0x1e18b80/d; +v0x1c4c940_0 .net *"_s0", 0 0, L_0x1e18c40; 1 drivers +v0x1c4ca20_0 .net *"_s1", 0 0, L_0x1e18da0; 1 drivers +S_0x1c4cb00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4cd40 .param/l "i" 0 4 54, +C4<010>; +L_0x1e18e90/d .functor AND 1, L_0x1e18f50, L_0x1e190b0, C4<1>, C4<1>; +L_0x1e18e90 .delay 1 (30000,30000,30000) L_0x1e18e90/d; +v0x1c4cde0_0 .net *"_s0", 0 0, L_0x1e18f50; 1 drivers +v0x1c4cec0_0 .net *"_s1", 0 0, L_0x1e190b0; 1 drivers +S_0x1c4cfa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4d1b0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e191a0/d .functor AND 1, L_0x1e19260, L_0x1e193c0, C4<1>, C4<1>; +L_0x1e191a0 .delay 1 (30000,30000,30000) L_0x1e191a0/d; +v0x1c4d270_0 .net *"_s0", 0 0, L_0x1e19260; 1 drivers +v0x1c4d350_0 .net *"_s1", 0 0, L_0x1e193c0; 1 drivers +S_0x1c4d430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4d690 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e19500/d .functor AND 1, L_0x1e195c0, L_0x1e19830, C4<1>, C4<1>; +L_0x1e19500 .delay 1 (30000,30000,30000) L_0x1e19500/d; +v0x1c4d750_0 .net *"_s0", 0 0, L_0x1e195c0; 1 drivers +v0x1c4d830_0 .net *"_s1", 0 0, L_0x1e19830; 1 drivers +S_0x1c4d910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4db20 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e19930/d .functor AND 1, L_0x1e199a0, L_0x1e19b00, C4<1>, C4<1>; +L_0x1e19930 .delay 1 (30000,30000,30000) L_0x1e19930/d; +v0x1c4dbe0_0 .net *"_s0", 0 0, L_0x1e199a0; 1 drivers +v0x1c4dcc0_0 .net *"_s1", 0 0, L_0x1e19b00; 1 drivers +S_0x1c4dda0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4dfb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e19c60/d .functor AND 1, L_0x1e19d20, L_0x1e19e80, C4<1>, C4<1>; +L_0x1e19c60 .delay 1 (30000,30000,30000) L_0x1e19c60/d; +v0x1c4e070_0 .net *"_s0", 0 0, L_0x1e19d20; 1 drivers +v0x1c4e150_0 .net *"_s1", 0 0, L_0x1e19e80; 1 drivers +S_0x1c4e230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c4bf80; + .timescale -9 -12; +P_0x1c4e440 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e1a270/d .functor AND 1, L_0x1e1a380, L_0x1e1a570, C4<1>, C4<1>; +L_0x1e1a270 .delay 1 (30000,30000,30000) L_0x1e1a270/d; +v0x1c4e500_0 .net *"_s0", 0 0, L_0x1e1a380; 1 drivers +v0x1c4e5e0_0 .net *"_s1", 0 0, L_0x1e1a570; 1 drivers +S_0x1c4f140 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c4bd30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e1bfc0/d .functor OR 1, L_0x1e1c080, L_0x1e1c230, C4<0>, C4<0>; +L_0x1e1bfc0 .delay 1 (30000,30000,30000) L_0x1e1bfc0/d; +v0x1c50d10_0 .net *"_s10", 0 0, L_0x1e1c080; 1 drivers +v0x1c50df0_0 .net *"_s12", 0 0, L_0x1e1c230; 1 drivers +v0x1c50ed0_0 .net "in", 7 0, L_0x1e19ff0; alias, 1 drivers +v0x1c50fa0_0 .net "ors", 1 0, L_0x1e1bde0; 1 drivers +v0x1c51060_0 .net "out", 0 0, L_0x1e1bfc0; alias, 1 drivers +L_0x1e1b1b0 .part L_0x1e19ff0, 0, 4; +L_0x1e1bde0 .concat8 [ 1 1 0 0], L_0x1e1aea0, L_0x1e1bad0; +L_0x1e1bf20 .part L_0x1e19ff0, 4, 4; +L_0x1e1c080 .part L_0x1e1bde0, 0, 1; +L_0x1e1c230 .part L_0x1e1bde0, 1, 1; +S_0x1c4f350 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c4f140; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e1a660/d .functor OR 1, L_0x1e1a720, L_0x1e1a880, C4<0>, C4<0>; +L_0x1e1a660 .delay 1 (30000,30000,30000) L_0x1e1a660/d; +L_0x1e1aab0/d .functor OR 1, L_0x1e1abc0, L_0x1e1ad20, C4<0>, C4<0>; +L_0x1e1aab0 .delay 1 (30000,30000,30000) L_0x1e1aab0/d; +L_0x1e1aea0/d .functor OR 1, L_0x1e1af10, L_0x1e1b0c0, C4<0>, C4<0>; +L_0x1e1aea0 .delay 1 (30000,30000,30000) L_0x1e1aea0/d; +v0x1c4f5a0_0 .net *"_s0", 0 0, L_0x1e1a660; 1 drivers +v0x1c4f6a0_0 .net *"_s10", 0 0, L_0x1e1abc0; 1 drivers +v0x1c4f780_0 .net *"_s12", 0 0, L_0x1e1ad20; 1 drivers +v0x1c4f870_0 .net *"_s14", 0 0, L_0x1e1af10; 1 drivers +v0x1c4f950_0 .net *"_s16", 0 0, L_0x1e1b0c0; 1 drivers +v0x1c4fa80_0 .net *"_s3", 0 0, L_0x1e1a720; 1 drivers +v0x1c4fb60_0 .net *"_s5", 0 0, L_0x1e1a880; 1 drivers +v0x1c4fc40_0 .net *"_s6", 0 0, L_0x1e1aab0; 1 drivers +v0x1c4fd20_0 .net "in", 3 0, L_0x1e1b1b0; 1 drivers +v0x1c4fe90_0 .net "ors", 1 0, L_0x1e1a9c0; 1 drivers +v0x1c4ff70_0 .net "out", 0 0, L_0x1e1aea0; 1 drivers +L_0x1e1a720 .part L_0x1e1b1b0, 0, 1; +L_0x1e1a880 .part L_0x1e1b1b0, 1, 1; +L_0x1e1a9c0 .concat8 [ 1 1 0 0], L_0x1e1a660, L_0x1e1aab0; +L_0x1e1abc0 .part L_0x1e1b1b0, 2, 1; +L_0x1e1ad20 .part L_0x1e1b1b0, 3, 1; +L_0x1e1af10 .part L_0x1e1a9c0, 0, 1; +L_0x1e1b0c0 .part L_0x1e1a9c0, 1, 1; +S_0x1c50090 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c4f140; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e1b2e0/d .functor OR 1, L_0x1e1b350, L_0x1e1b4b0, C4<0>, C4<0>; +L_0x1e1b2e0 .delay 1 (30000,30000,30000) L_0x1e1b2e0/d; +L_0x1e1b6e0/d .functor OR 1, L_0x1e1b7f0, L_0x1e1b950, C4<0>, C4<0>; +L_0x1e1b6e0 .delay 1 (30000,30000,30000) L_0x1e1b6e0/d; +L_0x1e1bad0/d .functor OR 1, L_0x1e1bb40, L_0x1e1bcf0, C4<0>, C4<0>; +L_0x1e1bad0 .delay 1 (30000,30000,30000) L_0x1e1bad0/d; +v0x1c50250_0 .net *"_s0", 0 0, L_0x1e1b2e0; 1 drivers +v0x1c50350_0 .net *"_s10", 0 0, L_0x1e1b7f0; 1 drivers +v0x1c50430_0 .net *"_s12", 0 0, L_0x1e1b950; 1 drivers +v0x1c504f0_0 .net *"_s14", 0 0, L_0x1e1bb40; 1 drivers +v0x1c505d0_0 .net *"_s16", 0 0, L_0x1e1bcf0; 1 drivers +v0x1c50700_0 .net *"_s3", 0 0, L_0x1e1b350; 1 drivers +v0x1c507e0_0 .net *"_s5", 0 0, L_0x1e1b4b0; 1 drivers +v0x1c508c0_0 .net *"_s6", 0 0, L_0x1e1b6e0; 1 drivers +v0x1c509a0_0 .net "in", 3 0, L_0x1e1bf20; 1 drivers +v0x1c50b10_0 .net "ors", 1 0, L_0x1e1b5f0; 1 drivers +v0x1c50bf0_0 .net "out", 0 0, L_0x1e1bad0; 1 drivers +L_0x1e1b350 .part L_0x1e1bf20, 0, 1; +L_0x1e1b4b0 .part L_0x1e1bf20, 1, 1; +L_0x1e1b5f0 .concat8 [ 1 1 0 0], L_0x1e1b2e0, L_0x1e1b6e0; +L_0x1e1b7f0 .part L_0x1e1bf20, 2, 1; +L_0x1e1b950 .part L_0x1e1bf20, 3, 1; +L_0x1e1bb40 .part L_0x1e1b5f0, 0, 1; +L_0x1e1bcf0 .part L_0x1e1b5f0, 1, 1; +S_0x1c51500 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c44e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e177c0/d .functor XNOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; +L_0x1e177c0 .delay 1 (20000,20000,20000) L_0x1e177c0/d; +L_0x1e17a30/d .functor AND 1, L_0x1e1fec0, L_0x1dc8070, C4<1>, C4<1>; +L_0x1e17a30 .delay 1 (30000,30000,30000) L_0x1e17a30/d; +L_0x1e17aa0/d .functor AND 1, L_0x1e177c0, L_0x1e16300, C4<1>, C4<1>; +L_0x1e17aa0 .delay 1 (30000,30000,30000) L_0x1e17aa0/d; +L_0x1e17c00/d .functor OR 1, L_0x1e17aa0, L_0x1e17a30, C4<0>, C4<0>; +L_0x1e17c00 .delay 1 (30000,30000,30000) L_0x1e17c00/d; +v0x1c517b0_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers +v0x1c518a0_0 .net "a_", 0 0, L_0x1e063c0; alias, 1 drivers +v0x1c51960_0 .net "b", 0 0, L_0x1e16260; alias, 1 drivers +v0x1c51a50_0 .net "b_", 0 0, L_0x1dc8070; alias, 1 drivers +v0x1c51af0_0 .net "carryin", 0 0, L_0x1e16300; alias, 1 drivers +v0x1c51c30_0 .net "eq", 0 0, L_0x1e177c0; 1 drivers +v0x1c51cf0_0 .net "lt", 0 0, L_0x1e17a30; 1 drivers +v0x1c51db0_0 .net "out", 0 0, L_0x1e17c00; 1 drivers +v0x1c51e70_0 .net "w0", 0 0, L_0x1e17aa0; 1 drivers +S_0x1c520c0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c44e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e175a0/d .functor OR 1, L_0x1e170a0, L_0x1c53320, C4<0>, C4<0>; +L_0x1e175a0 .delay 1 (30000,30000,30000) L_0x1e175a0/d; +v0x1c52eb0_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers +v0x1c53000_0 .net "b", 0 0, L_0x1dc8070; alias, 1 drivers +v0x1c530c0_0 .net "c1", 0 0, L_0x1e170a0; 1 drivers +v0x1c53160_0 .net "c2", 0 0, L_0x1c53320; 1 drivers +v0x1c53230_0 .net "carryin", 0 0, L_0x1e16300; alias, 1 drivers +v0x1c533b0_0 .net "carryout", 0 0, L_0x1e175a0; 1 drivers +v0x1c53450_0 .net "s1", 0 0, L_0x1e16fe0; 1 drivers +v0x1c534f0_0 .net "sum", 0 0, L_0x1e17200; 1 drivers +S_0x1c52310 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c520c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e16fe0/d .functor XOR 1, L_0x1e1fec0, L_0x1dc8070, C4<0>, C4<0>; +L_0x1e16fe0 .delay 1 (30000,30000,30000) L_0x1e16fe0/d; +L_0x1e170a0/d .functor AND 1, L_0x1e1fec0, L_0x1dc8070, C4<1>, C4<1>; +L_0x1e170a0 .delay 1 (30000,30000,30000) L_0x1e170a0/d; +v0x1c52570_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers +v0x1c52630_0 .net "b", 0 0, L_0x1dc8070; alias, 1 drivers +v0x1c526f0_0 .net "carryout", 0 0, L_0x1e170a0; alias, 1 drivers +v0x1c52790_0 .net "sum", 0 0, L_0x1e16fe0; alias, 1 drivers +S_0x1c528c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c520c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e17200/d .functor XOR 1, L_0x1e16fe0, L_0x1e16300, C4<0>, C4<0>; +L_0x1e17200 .delay 1 (30000,30000,30000) L_0x1e17200/d; +L_0x1c53320/d .functor AND 1, L_0x1e16fe0, L_0x1e16300, C4<1>, C4<1>; +L_0x1c53320 .delay 1 (30000,30000,30000) L_0x1c53320/d; +v0x1c52b20_0 .net "a", 0 0, L_0x1e16fe0; alias, 1 drivers +v0x1c52bf0_0 .net "b", 0 0, L_0x1e16300; alias, 1 drivers +v0x1c52c90_0 .net "carryout", 0 0, L_0x1c53320; alias, 1 drivers +v0x1c52d60_0 .net "sum", 0 0, L_0x1e17200; alias, 1 drivers +S_0x1c54910 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c44b90; + .timescale -9 -12; +L_0x7f72592db338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db380 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e1ff60/d .functor OR 1, L_0x7f72592db338, L_0x7f72592db380, C4<0>, C4<0>; +L_0x1e1ff60 .delay 1 (30000,30000,30000) L_0x1e1ff60/d; +v0x1c54b00_0 .net/2u *"_s0", 0 0, L_0x7f72592db338; 1 drivers +v0x1c54be0_0 .net/2u *"_s2", 0 0, L_0x7f72592db380; 1 drivers +S_0x1c54cc0 .scope generate, "alu_slices[18]" "alu_slices[18]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c54ed0 .param/l "i" 0 3 37, +C4<010010>; +S_0x1c54f90 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c54cc0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e20280/d .functor NOT 1, L_0x1e29ab0, C4<0>, C4<0>, C4<0>; +L_0x1e20280 .delay 1 (10000,10000,10000) L_0x1e20280/d; +L_0x1e203e0/d .functor NOT 1, L_0x1e29c10, C4<0>, C4<0>, C4<0>; +L_0x1e203e0 .delay 1 (10000,10000,10000) L_0x1e203e0/d; +L_0x1e21320/d .functor XOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; +L_0x1e21320 .delay 1 (30000,30000,30000) L_0x1e21320/d; +L_0x7f72592db3c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db410 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e219d0/d .functor OR 1, L_0x7f72592db3c8, L_0x7f72592db410, C4<0>, C4<0>; +L_0x1e219d0 .delay 1 (30000,30000,30000) L_0x1e219d0/d; +L_0x1e21bd0/d .functor AND 1, L_0x1e29ab0, L_0x1e29c10, C4<1>, C4<1>; +L_0x1e21bd0 .delay 1 (30000,30000,30000) L_0x1e21bd0/d; +L_0x1e21c90/d .functor NAND 1, L_0x1e29ab0, L_0x1e29c10, C4<1>, C4<1>; +L_0x1e21c90 .delay 1 (20000,20000,20000) L_0x1e21c90/d; +L_0x1e21df0/d .functor XOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; +L_0x1e21df0 .delay 1 (20000,20000,20000) L_0x1e21df0/d; +L_0x1e222a0/d .functor OR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; +L_0x1e222a0 .delay 1 (30000,30000,30000) L_0x1e222a0/d; +L_0x1e299b0/d .functor NOT 1, L_0x1e25c10, C4<0>, C4<0>, C4<0>; +L_0x1e299b0 .delay 1 (10000,10000,10000) L_0x1e299b0/d; +v0x1c636c0_0 .net "A", 0 0, L_0x1e29ab0; 1 drivers +v0x1c63780_0 .net "A_", 0 0, L_0x1e20280; 1 drivers +v0x1c63840_0 .net "B", 0 0, L_0x1e29c10; 1 drivers +v0x1c63910_0 .net "B_", 0 0, L_0x1e203e0; 1 drivers +v0x1c639b0_0 .net *"_s12", 0 0, L_0x1e219d0; 1 drivers +v0x1c63aa0_0 .net/2s *"_s14", 0 0, L_0x7f72592db3c8; 1 drivers +v0x1c63b60_0 .net/2s *"_s16", 0 0, L_0x7f72592db410; 1 drivers +v0x1c63c40_0 .net *"_s18", 0 0, L_0x1e21bd0; 1 drivers +v0x1c63d20_0 .net *"_s20", 0 0, L_0x1e21c90; 1 drivers +v0x1c63e90_0 .net *"_s22", 0 0, L_0x1e21df0; 1 drivers +v0x1c63f70_0 .net *"_s24", 0 0, L_0x1e222a0; 1 drivers +o0x7f7259380268 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c64050_0 name=_s30 +o0x7f7259380298 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c64130_0 name=_s32 +v0x1c64210_0 .net *"_s8", 0 0, L_0x1e21320; 1 drivers +v0x1c642f0_0 .net "carryin", 0 0, L_0x1e20020; 1 drivers +v0x1c64390_0 .net "carryout", 0 0, L_0x1e29650; 1 drivers +v0x1c64430_0 .net "carryouts", 7 0, L_0x1ec0990; 1 drivers +v0x1c645e0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c64680_0 .net "result", 0 0, L_0x1e25c10; 1 drivers +v0x1c64770_0 .net "results", 7 0, L_0x1e22070; 1 drivers +v0x1c64880_0 .net "zero", 0 0, L_0x1e299b0; 1 drivers +LS_0x1e22070_0_0 .concat8 [ 1 1 1 1], L_0x1e20840, L_0x1e20e70, L_0x1e21320, L_0x1e219d0; +LS_0x1e22070_0_4 .concat8 [ 1 1 1 1], L_0x1e21bd0, L_0x1e21c90, L_0x1e21df0, L_0x1e222a0; +L_0x1e22070 .concat8 [ 4 4 0 0], LS_0x1e22070_0_0, LS_0x1e22070_0_4; +LS_0x1ec0990_0_0 .concat [ 1 1 1 1], L_0x1e20af0, L_0x1e211c0, o0x7f7259380268, L_0x1e21820; +LS_0x1ec0990_0_4 .concat [ 4 0 0 0], o0x7f7259380298; +L_0x1ec0990 .concat [ 4 4 0 0], LS_0x1ec0990_0_0, LS_0x1ec0990_0_4; +S_0x1c55210 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c54f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e20af0/d .functor OR 1, L_0x1e205d0, L_0x1e20990, C4<0>, C4<0>; +L_0x1e20af0 .delay 1 (30000,30000,30000) L_0x1e20af0/d; +v0x1c56040_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers +v0x1c56100_0 .net "b", 0 0, L_0x1e29c10; alias, 1 drivers +v0x1c561d0_0 .net "c1", 0 0, L_0x1e205d0; 1 drivers +v0x1c562d0_0 .net "c2", 0 0, L_0x1e20990; 1 drivers +v0x1c563a0_0 .net "carryin", 0 0, L_0x1e20020; alias, 1 drivers +v0x1c56490_0 .net "carryout", 0 0, L_0x1e20af0; 1 drivers +v0x1c56530_0 .net "s1", 0 0, L_0x1e19f70; 1 drivers +v0x1c56620_0 .net "sum", 0 0, L_0x1e20840; 1 drivers +S_0x1c55480 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c55210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e19f70/d .functor XOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; +L_0x1e19f70 .delay 1 (30000,30000,30000) L_0x1e19f70/d; +L_0x1e205d0/d .functor AND 1, L_0x1e29ab0, L_0x1e29c10, C4<1>, C4<1>; +L_0x1e205d0 .delay 1 (30000,30000,30000) L_0x1e205d0/d; +v0x1c556e0_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers +v0x1c557c0_0 .net "b", 0 0, L_0x1e29c10; alias, 1 drivers +v0x1c55880_0 .net "carryout", 0 0, L_0x1e205d0; alias, 1 drivers +v0x1c55920_0 .net "sum", 0 0, L_0x1e19f70; alias, 1 drivers +S_0x1c55a60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c55210; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e20840/d .functor XOR 1, L_0x1e19f70, L_0x1e20020, C4<0>, C4<0>; +L_0x1e20840 .delay 1 (30000,30000,30000) L_0x1e20840/d; +L_0x1e20990/d .functor AND 1, L_0x1e19f70, L_0x1e20020, C4<1>, C4<1>; +L_0x1e20990 .delay 1 (30000,30000,30000) L_0x1e20990/d; +v0x1c55cc0_0 .net "a", 0 0, L_0x1e19f70; alias, 1 drivers +v0x1c55d60_0 .net "b", 0 0, L_0x1e20020; alias, 1 drivers +v0x1c55e00_0 .net "carryout", 0 0, L_0x1e20990; alias, 1 drivers +v0x1c55ed0_0 .net "sum", 0 0, L_0x1e20840; alias, 1 drivers +S_0x1c566f0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c54f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c5bae0_0 .net "ands", 7 0, L_0x1e27650; 1 drivers +v0x1c5bbf0_0 .net "in", 7 0, L_0x1ec0990; alias, 1 drivers +v0x1c5bcb0_0 .net "out", 0 0, L_0x1e29650; alias, 1 drivers +v0x1c5bd80_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c56910 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c566f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c59040_0 .net "A", 7 0, L_0x1ec0990; alias, 1 drivers +v0x1c59140_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c59200_0 .net *"_s0", 0 0, L_0x1e25f70; 1 drivers +v0x1c592c0_0 .net *"_s12", 0 0, L_0x1e268e0; 1 drivers +v0x1c593a0_0 .net *"_s16", 0 0, L_0x1e26c40; 1 drivers +v0x1c594d0_0 .net *"_s20", 0 0, L_0x1e26f50; 1 drivers +v0x1c595b0_0 .net *"_s24", 0 0, L_0x1e27340; 1 drivers +v0x1c59690_0 .net *"_s28", 0 0, L_0x1e272d0; 1 drivers +v0x1c59770_0 .net *"_s4", 0 0, L_0x1e26280; 1 drivers +v0x1c598e0_0 .net *"_s8", 0 0, L_0x1e265d0; 1 drivers +v0x1c599c0_0 .net "out", 7 0, L_0x1e27650; alias, 1 drivers +L_0x1e26030 .part L_0x1ec0990, 0, 1; +L_0x1e26190 .part v0x1d6daa0_0, 0, 1; +L_0x1e26340 .part L_0x1ec0990, 1, 1; +L_0x1e26530 .part v0x1d6daa0_0, 1, 1; +L_0x1e26690 .part L_0x1ec0990, 2, 1; +L_0x1e267f0 .part v0x1d6daa0_0, 2, 1; +L_0x1e269a0 .part L_0x1ec0990, 3, 1; +L_0x1e26b00 .part v0x1d6daa0_0, 3, 1; +L_0x1e26d00 .part L_0x1ec0990, 4, 1; +L_0x1e26e60 .part v0x1d6daa0_0, 4, 1; +L_0x1e26fc0 .part L_0x1ec0990, 5, 1; +L_0x1e27230 .part v0x1d6daa0_0, 5, 1; +L_0x1e27400 .part L_0x1ec0990, 6, 1; +L_0x1e27560 .part v0x1d6daa0_0, 6, 1; +LS_0x1e27650_0_0 .concat8 [ 1 1 1 1], L_0x1e25f70, L_0x1e26280, L_0x1e265d0, L_0x1e268e0; +LS_0x1e27650_0_4 .concat8 [ 1 1 1 1], L_0x1e26c40, L_0x1e26f50, L_0x1e27340, L_0x1e272d0; +L_0x1e27650 .concat8 [ 4 4 0 0], LS_0x1e27650_0_0, LS_0x1e27650_0_4; +L_0x1e27a10 .part L_0x1ec0990, 7, 1; +L_0x1e27c00 .part v0x1d6daa0_0, 7, 1; +S_0x1c56b70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c56d80 .param/l "i" 0 4 54, +C4<00>; +L_0x1e25f70/d .functor AND 1, L_0x1e26030, L_0x1e26190, C4<1>, C4<1>; +L_0x1e25f70 .delay 1 (30000,30000,30000) L_0x1e25f70/d; +v0x1c56e60_0 .net *"_s0", 0 0, L_0x1e26030; 1 drivers +v0x1c56f40_0 .net *"_s1", 0 0, L_0x1e26190; 1 drivers +S_0x1c57020 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c57230 .param/l "i" 0 4 54, +C4<01>; +L_0x1e26280/d .functor AND 1, L_0x1e26340, L_0x1e26530, C4<1>, C4<1>; +L_0x1e26280 .delay 1 (30000,30000,30000) L_0x1e26280/d; +v0x1c572f0_0 .net *"_s0", 0 0, L_0x1e26340; 1 drivers +v0x1c573d0_0 .net *"_s1", 0 0, L_0x1e26530; 1 drivers +S_0x1c574b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c576c0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e265d0/d .functor AND 1, L_0x1e26690, L_0x1e267f0, C4<1>, C4<1>; +L_0x1e265d0 .delay 1 (30000,30000,30000) L_0x1e265d0/d; +v0x1c57760_0 .net *"_s0", 0 0, L_0x1e26690; 1 drivers +v0x1c57840_0 .net *"_s1", 0 0, L_0x1e267f0; 1 drivers +S_0x1c57920 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c57b30 .param/l "i" 0 4 54, +C4<011>; +L_0x1e268e0/d .functor AND 1, L_0x1e269a0, L_0x1e26b00, C4<1>, C4<1>; +L_0x1e268e0 .delay 1 (30000,30000,30000) L_0x1e268e0/d; +v0x1c57bf0_0 .net *"_s0", 0 0, L_0x1e269a0; 1 drivers +v0x1c57cd0_0 .net *"_s1", 0 0, L_0x1e26b00; 1 drivers +S_0x1c57db0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c58010 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e26c40/d .functor AND 1, L_0x1e26d00, L_0x1e26e60, C4<1>, C4<1>; +L_0x1e26c40 .delay 1 (30000,30000,30000) L_0x1e26c40/d; +v0x1c580d0_0 .net *"_s0", 0 0, L_0x1e26d00; 1 drivers +v0x1c581b0_0 .net *"_s1", 0 0, L_0x1e26e60; 1 drivers +S_0x1c58290 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c584a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e26f50/d .functor AND 1, L_0x1e26fc0, L_0x1e27230, C4<1>, C4<1>; +L_0x1e26f50 .delay 1 (30000,30000,30000) L_0x1e26f50/d; +v0x1c58560_0 .net *"_s0", 0 0, L_0x1e26fc0; 1 drivers +v0x1c58640_0 .net *"_s1", 0 0, L_0x1e27230; 1 drivers +S_0x1c58720 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c58930 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e27340/d .functor AND 1, L_0x1e27400, L_0x1e27560, C4<1>, C4<1>; +L_0x1e27340 .delay 1 (30000,30000,30000) L_0x1e27340/d; +v0x1c589f0_0 .net *"_s0", 0 0, L_0x1e27400; 1 drivers +v0x1c58ad0_0 .net *"_s1", 0 0, L_0x1e27560; 1 drivers +S_0x1c58bb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c56910; + .timescale -9 -12; +P_0x1c58dc0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e272d0/d .functor AND 1, L_0x1e27a10, L_0x1e27c00, C4<1>, C4<1>; +L_0x1e272d0 .delay 1 (30000,30000,30000) L_0x1e272d0/d; +v0x1c58e80_0 .net *"_s0", 0 0, L_0x1e27a10; 1 drivers +v0x1c58f60_0 .net *"_s1", 0 0, L_0x1e27c00; 1 drivers +S_0x1c59b20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c566f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e29650/d .functor OR 1, L_0x1e29710, L_0x1e298c0, C4<0>, C4<0>; +L_0x1e29650 .delay 1 (30000,30000,30000) L_0x1e29650/d; +v0x1c5b670_0 .net *"_s10", 0 0, L_0x1e29710; 1 drivers +v0x1c5b750_0 .net *"_s12", 0 0, L_0x1e298c0; 1 drivers +v0x1c5b830_0 .net "in", 7 0, L_0x1e27650; alias, 1 drivers +v0x1c5b900_0 .net "ors", 1 0, L_0x1e29470; 1 drivers +v0x1c5b9c0_0 .net "out", 0 0, L_0x1e29650; alias, 1 drivers +L_0x1e28840 .part L_0x1e27650, 0, 4; +L_0x1e29470 .concat8 [ 1 1 0 0], L_0x1e28530, L_0x1e29160; +L_0x1e295b0 .part L_0x1e27650, 4, 4; +L_0x1e29710 .part L_0x1e29470, 0, 1; +L_0x1e298c0 .part L_0x1e29470, 1, 1; +S_0x1c59ce0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c59b20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e27cf0/d .functor OR 1, L_0x1e27db0, L_0x1e27f10, C4<0>, C4<0>; +L_0x1e27cf0 .delay 1 (30000,30000,30000) L_0x1e27cf0/d; +L_0x1e28140/d .functor OR 1, L_0x1e28250, L_0x1e283b0, C4<0>, C4<0>; +L_0x1e28140 .delay 1 (30000,30000,30000) L_0x1e28140/d; +L_0x1e28530/d .functor OR 1, L_0x1e285a0, L_0x1e28750, C4<0>, C4<0>; +L_0x1e28530 .delay 1 (30000,30000,30000) L_0x1e28530/d; +v0x1c59f30_0 .net *"_s0", 0 0, L_0x1e27cf0; 1 drivers +v0x1c5a030_0 .net *"_s10", 0 0, L_0x1e28250; 1 drivers +v0x1c5a110_0 .net *"_s12", 0 0, L_0x1e283b0; 1 drivers +v0x1c5a1d0_0 .net *"_s14", 0 0, L_0x1e285a0; 1 drivers +v0x1c5a2b0_0 .net *"_s16", 0 0, L_0x1e28750; 1 drivers +v0x1c5a3e0_0 .net *"_s3", 0 0, L_0x1e27db0; 1 drivers +v0x1c5a4c0_0 .net *"_s5", 0 0, L_0x1e27f10; 1 drivers +v0x1c5a5a0_0 .net *"_s6", 0 0, L_0x1e28140; 1 drivers +v0x1c5a680_0 .net "in", 3 0, L_0x1e28840; 1 drivers +v0x1c5a7f0_0 .net "ors", 1 0, L_0x1e28050; 1 drivers +v0x1c5a8d0_0 .net "out", 0 0, L_0x1e28530; 1 drivers +L_0x1e27db0 .part L_0x1e28840, 0, 1; +L_0x1e27f10 .part L_0x1e28840, 1, 1; +L_0x1e28050 .concat8 [ 1 1 0 0], L_0x1e27cf0, L_0x1e28140; +L_0x1e28250 .part L_0x1e28840, 2, 1; +L_0x1e283b0 .part L_0x1e28840, 3, 1; +L_0x1e285a0 .part L_0x1e28050, 0, 1; +L_0x1e28750 .part L_0x1e28050, 1, 1; +S_0x1c5a9f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c59b20; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e28970/d .functor OR 1, L_0x1e289e0, L_0x1e28b40, C4<0>, C4<0>; +L_0x1e28970 .delay 1 (30000,30000,30000) L_0x1e28970/d; +L_0x1e28d70/d .functor OR 1, L_0x1e28e80, L_0x1e28fe0, C4<0>, C4<0>; +L_0x1e28d70 .delay 1 (30000,30000,30000) L_0x1e28d70/d; +L_0x1e29160/d .functor OR 1, L_0x1e291d0, L_0x1e29380, C4<0>, C4<0>; +L_0x1e29160 .delay 1 (30000,30000,30000) L_0x1e29160/d; +v0x1c5abb0_0 .net *"_s0", 0 0, L_0x1e28970; 1 drivers +v0x1c5acb0_0 .net *"_s10", 0 0, L_0x1e28e80; 1 drivers +v0x1c5ad90_0 .net *"_s12", 0 0, L_0x1e28fe0; 1 drivers +v0x1c5ae50_0 .net *"_s14", 0 0, L_0x1e291d0; 1 drivers +v0x1c5af30_0 .net *"_s16", 0 0, L_0x1e29380; 1 drivers +v0x1c5b060_0 .net *"_s3", 0 0, L_0x1e289e0; 1 drivers +v0x1c5b140_0 .net *"_s5", 0 0, L_0x1e28b40; 1 drivers +v0x1c5b220_0 .net *"_s6", 0 0, L_0x1e28d70; 1 drivers +v0x1c5b300_0 .net "in", 3 0, L_0x1e295b0; 1 drivers +v0x1c5b470_0 .net "ors", 1 0, L_0x1e28c80; 1 drivers +v0x1c5b550_0 .net "out", 0 0, L_0x1e29160; 1 drivers +L_0x1e289e0 .part L_0x1e295b0, 0, 1; +L_0x1e28b40 .part L_0x1e295b0, 1, 1; +L_0x1e28c80 .concat8 [ 1 1 0 0], L_0x1e28970, L_0x1e28d70; +L_0x1e28e80 .part L_0x1e295b0, 2, 1; +L_0x1e28fe0 .part L_0x1e295b0, 3, 1; +L_0x1e291d0 .part L_0x1e28c80, 0, 1; +L_0x1e29380 .part L_0x1e28c80, 1, 1; +S_0x1c5be60 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c54f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c61290_0 .net "ands", 7 0, L_0x1e23c10; 1 drivers +v0x1c613a0_0 .net "in", 7 0, L_0x1e22070; alias, 1 drivers +v0x1c61460_0 .net "out", 0 0, L_0x1e25c10; alias, 1 drivers +v0x1c61530_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c5c0b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c5be60; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c5e7f0_0 .net "A", 7 0, L_0x1e22070; alias, 1 drivers +v0x1c5e8f0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c5e9b0_0 .net *"_s0", 0 0, L_0x1e22400; 1 drivers +v0x1c5ea70_0 .net *"_s12", 0 0, L_0x1e22dc0; 1 drivers +v0x1c5eb50_0 .net *"_s16", 0 0, L_0x1e23120; 1 drivers +v0x1c5ec80_0 .net *"_s20", 0 0, L_0x1e23550; 1 drivers +v0x1c5ed60_0 .net *"_s24", 0 0, L_0x1e23880; 1 drivers +v0x1c5ee40_0 .net *"_s28", 0 0, L_0x1e23810; 1 drivers +v0x1c5ef20_0 .net *"_s4", 0 0, L_0x1e227a0; 1 drivers +v0x1c5f090_0 .net *"_s8", 0 0, L_0x1e22ab0; 1 drivers +v0x1c5f170_0 .net "out", 7 0, L_0x1e23c10; alias, 1 drivers +L_0x1e22510 .part L_0x1e22070, 0, 1; +L_0x1e22700 .part v0x1d6daa0_0, 0, 1; +L_0x1e22860 .part L_0x1e22070, 1, 1; +L_0x1e229c0 .part v0x1d6daa0_0, 1, 1; +L_0x1e22b70 .part L_0x1e22070, 2, 1; +L_0x1e22cd0 .part v0x1d6daa0_0, 2, 1; +L_0x1e22e80 .part L_0x1e22070, 3, 1; +L_0x1e22fe0 .part v0x1d6daa0_0, 3, 1; +L_0x1e231e0 .part L_0x1e22070, 4, 1; +L_0x1e23450 .part v0x1d6daa0_0, 4, 1; +L_0x1e235c0 .part L_0x1e22070, 5, 1; +L_0x1e23720 .part v0x1d6daa0_0, 5, 1; +L_0x1e23940 .part L_0x1e22070, 6, 1; +L_0x1e23aa0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e23c10_0_0 .concat8 [ 1 1 1 1], L_0x1e22400, L_0x1e227a0, L_0x1e22ab0, L_0x1e22dc0; +LS_0x1e23c10_0_4 .concat8 [ 1 1 1 1], L_0x1e23120, L_0x1e23550, L_0x1e23880, L_0x1e23810; +L_0x1e23c10 .concat8 [ 4 4 0 0], LS_0x1e23c10_0_0, LS_0x1e23c10_0_4; +L_0x1e23fd0 .part L_0x1e22070, 7, 1; +L_0x1e241c0 .part v0x1d6daa0_0, 7, 1; +S_0x1c5c2f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5c500 .param/l "i" 0 4 54, +C4<00>; +L_0x1e22400/d .functor AND 1, L_0x1e22510, L_0x1e22700, C4<1>, C4<1>; +L_0x1e22400 .delay 1 (30000,30000,30000) L_0x1e22400/d; +v0x1c5c5e0_0 .net *"_s0", 0 0, L_0x1e22510; 1 drivers +v0x1c5c6c0_0 .net *"_s1", 0 0, L_0x1e22700; 1 drivers +S_0x1c5c7a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5c9b0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e227a0/d .functor AND 1, L_0x1e22860, L_0x1e229c0, C4<1>, C4<1>; +L_0x1e227a0 .delay 1 (30000,30000,30000) L_0x1e227a0/d; +v0x1c5ca70_0 .net *"_s0", 0 0, L_0x1e22860; 1 drivers +v0x1c5cb50_0 .net *"_s1", 0 0, L_0x1e229c0; 1 drivers +S_0x1c5cc30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5ce70 .param/l "i" 0 4 54, +C4<010>; +L_0x1e22ab0/d .functor AND 1, L_0x1e22b70, L_0x1e22cd0, C4<1>, C4<1>; +L_0x1e22ab0 .delay 1 (30000,30000,30000) L_0x1e22ab0/d; +v0x1c5cf10_0 .net *"_s0", 0 0, L_0x1e22b70; 1 drivers +v0x1c5cff0_0 .net *"_s1", 0 0, L_0x1e22cd0; 1 drivers +S_0x1c5d0d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5d2e0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e22dc0/d .functor AND 1, L_0x1e22e80, L_0x1e22fe0, C4<1>, C4<1>; +L_0x1e22dc0 .delay 1 (30000,30000,30000) L_0x1e22dc0/d; +v0x1c5d3a0_0 .net *"_s0", 0 0, L_0x1e22e80; 1 drivers +v0x1c5d480_0 .net *"_s1", 0 0, L_0x1e22fe0; 1 drivers +S_0x1c5d560 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5d7c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e23120/d .functor AND 1, L_0x1e231e0, L_0x1e23450, C4<1>, C4<1>; +L_0x1e23120 .delay 1 (30000,30000,30000) L_0x1e23120/d; +v0x1c5d880_0 .net *"_s0", 0 0, L_0x1e231e0; 1 drivers +v0x1c5d960_0 .net *"_s1", 0 0, L_0x1e23450; 1 drivers +S_0x1c5da40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5dc50 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e23550/d .functor AND 1, L_0x1e235c0, L_0x1e23720, C4<1>, C4<1>; +L_0x1e23550 .delay 1 (30000,30000,30000) L_0x1e23550/d; +v0x1c5dd10_0 .net *"_s0", 0 0, L_0x1e235c0; 1 drivers +v0x1c5ddf0_0 .net *"_s1", 0 0, L_0x1e23720; 1 drivers +S_0x1c5ded0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5e0e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e23880/d .functor AND 1, L_0x1e23940, L_0x1e23aa0, C4<1>, C4<1>; +L_0x1e23880 .delay 1 (30000,30000,30000) L_0x1e23880/d; +v0x1c5e1a0_0 .net *"_s0", 0 0, L_0x1e23940; 1 drivers +v0x1c5e280_0 .net *"_s1", 0 0, L_0x1e23aa0; 1 drivers +S_0x1c5e360 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c5c0b0; + .timescale -9 -12; +P_0x1c5e570 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e23810/d .functor AND 1, L_0x1e23fd0, L_0x1e241c0, C4<1>, C4<1>; +L_0x1e23810 .delay 1 (30000,30000,30000) L_0x1e23810/d; +v0x1c5e630_0 .net *"_s0", 0 0, L_0x1e23fd0; 1 drivers +v0x1c5e710_0 .net *"_s1", 0 0, L_0x1e241c0; 1 drivers +S_0x1c5f2d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c5be60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e25c10/d .functor OR 1, L_0x1e25cd0, L_0x1e25e80, C4<0>, C4<0>; +L_0x1e25c10 .delay 1 (30000,30000,30000) L_0x1e25c10/d; +v0x1c60e20_0 .net *"_s10", 0 0, L_0x1e25cd0; 1 drivers +v0x1c60f00_0 .net *"_s12", 0 0, L_0x1e25e80; 1 drivers +v0x1c60fe0_0 .net "in", 7 0, L_0x1e23c10; alias, 1 drivers +v0x1c610b0_0 .net "ors", 1 0, L_0x1e25a30; 1 drivers +v0x1c61170_0 .net "out", 0 0, L_0x1e25c10; alias, 1 drivers +L_0x1e24e00 .part L_0x1e23c10, 0, 4; +L_0x1e25a30 .concat8 [ 1 1 0 0], L_0x1e24af0, L_0x1e25720; +L_0x1e25b70 .part L_0x1e23c10, 4, 4; +L_0x1e25cd0 .part L_0x1e25a30, 0, 1; +L_0x1e25e80 .part L_0x1e25a30, 1, 1; +S_0x1c5f490 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c5f2d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e242b0/d .functor OR 1, L_0x1e24370, L_0x1e244d0, C4<0>, C4<0>; +L_0x1e242b0 .delay 1 (30000,30000,30000) L_0x1e242b0/d; +L_0x1e24700/d .functor OR 1, L_0x1e24810, L_0x1e24970, C4<0>, C4<0>; +L_0x1e24700 .delay 1 (30000,30000,30000) L_0x1e24700/d; +L_0x1e24af0/d .functor OR 1, L_0x1e24b60, L_0x1e24d10, C4<0>, C4<0>; +L_0x1e24af0 .delay 1 (30000,30000,30000) L_0x1e24af0/d; +v0x1c5f6e0_0 .net *"_s0", 0 0, L_0x1e242b0; 1 drivers +v0x1c5f7e0_0 .net *"_s10", 0 0, L_0x1e24810; 1 drivers +v0x1c5f8c0_0 .net *"_s12", 0 0, L_0x1e24970; 1 drivers +v0x1c5f980_0 .net *"_s14", 0 0, L_0x1e24b60; 1 drivers +v0x1c5fa60_0 .net *"_s16", 0 0, L_0x1e24d10; 1 drivers +v0x1c5fb90_0 .net *"_s3", 0 0, L_0x1e24370; 1 drivers +v0x1c5fc70_0 .net *"_s5", 0 0, L_0x1e244d0; 1 drivers +v0x1c5fd50_0 .net *"_s6", 0 0, L_0x1e24700; 1 drivers +v0x1c5fe30_0 .net "in", 3 0, L_0x1e24e00; 1 drivers +v0x1c5ffa0_0 .net "ors", 1 0, L_0x1e24610; 1 drivers +v0x1c60080_0 .net "out", 0 0, L_0x1e24af0; 1 drivers +L_0x1e24370 .part L_0x1e24e00, 0, 1; +L_0x1e244d0 .part L_0x1e24e00, 1, 1; +L_0x1e24610 .concat8 [ 1 1 0 0], L_0x1e242b0, L_0x1e24700; +L_0x1e24810 .part L_0x1e24e00, 2, 1; +L_0x1e24970 .part L_0x1e24e00, 3, 1; +L_0x1e24b60 .part L_0x1e24610, 0, 1; +L_0x1e24d10 .part L_0x1e24610, 1, 1; +S_0x1c601a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c5f2d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e24f30/d .functor OR 1, L_0x1e24fa0, L_0x1e25100, C4<0>, C4<0>; +L_0x1e24f30 .delay 1 (30000,30000,30000) L_0x1e24f30/d; +L_0x1e25330/d .functor OR 1, L_0x1e25440, L_0x1e255a0, C4<0>, C4<0>; +L_0x1e25330 .delay 1 (30000,30000,30000) L_0x1e25330/d; +L_0x1e25720/d .functor OR 1, L_0x1e25790, L_0x1e25940, C4<0>, C4<0>; +L_0x1e25720 .delay 1 (30000,30000,30000) L_0x1e25720/d; +v0x1c60360_0 .net *"_s0", 0 0, L_0x1e24f30; 1 drivers +v0x1c60460_0 .net *"_s10", 0 0, L_0x1e25440; 1 drivers +v0x1c60540_0 .net *"_s12", 0 0, L_0x1e255a0; 1 drivers +v0x1c60600_0 .net *"_s14", 0 0, L_0x1e25790; 1 drivers +v0x1c606e0_0 .net *"_s16", 0 0, L_0x1e25940; 1 drivers +v0x1c60810_0 .net *"_s3", 0 0, L_0x1e24fa0; 1 drivers +v0x1c608f0_0 .net *"_s5", 0 0, L_0x1e25100; 1 drivers +v0x1c609d0_0 .net *"_s6", 0 0, L_0x1e25330; 1 drivers +v0x1c60ab0_0 .net "in", 3 0, L_0x1e25b70; 1 drivers +v0x1c60c20_0 .net "ors", 1 0, L_0x1e25240; 1 drivers +v0x1c60d00_0 .net "out", 0 0, L_0x1e25720; 1 drivers +L_0x1e24fa0 .part L_0x1e25b70, 0, 1; +L_0x1e25100 .part L_0x1e25b70, 1, 1; +L_0x1e25240 .concat8 [ 1 1 0 0], L_0x1e24f30, L_0x1e25330; +L_0x1e25440 .part L_0x1e25b70, 2, 1; +L_0x1e255a0 .part L_0x1e25b70, 3, 1; +L_0x1e25790 .part L_0x1e25240, 0, 1; +L_0x1e25940 .part L_0x1e25240, 1, 1; +S_0x1c61610 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c54f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e213e0/d .functor XNOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; +L_0x1e213e0 .delay 1 (20000,20000,20000) L_0x1e213e0/d; +L_0x1e21650/d .functor AND 1, L_0x1e29ab0, L_0x1e203e0, C4<1>, C4<1>; +L_0x1e21650 .delay 1 (30000,30000,30000) L_0x1e21650/d; +L_0x1e216c0/d .functor AND 1, L_0x1e213e0, L_0x1e20020, C4<1>, C4<1>; +L_0x1e216c0 .delay 1 (30000,30000,30000) L_0x1e216c0/d; +L_0x1e21820/d .functor OR 1, L_0x1e216c0, L_0x1e21650, C4<0>, C4<0>; +L_0x1e21820 .delay 1 (30000,30000,30000) L_0x1e21820/d; +v0x1c618c0_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers +v0x1c619b0_0 .net "a_", 0 0, L_0x1e20280; alias, 1 drivers +v0x1c61a70_0 .net "b", 0 0, L_0x1e29c10; alias, 1 drivers +v0x1c61b60_0 .net "b_", 0 0, L_0x1e203e0; alias, 1 drivers +v0x1c61c00_0 .net "carryin", 0 0, L_0x1e20020; alias, 1 drivers +v0x1c61d40_0 .net "eq", 0 0, L_0x1e213e0; 1 drivers +v0x1c61e00_0 .net "lt", 0 0, L_0x1e21650; 1 drivers +v0x1c61ec0_0 .net "out", 0 0, L_0x1e21820; 1 drivers +v0x1c61f80_0 .net "w0", 0 0, L_0x1e216c0; 1 drivers +S_0x1c621d0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c54f90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e211c0/d .functor OR 1, L_0x1e20d10, L_0x1c63430, C4<0>, C4<0>; +L_0x1e211c0 .delay 1 (30000,30000,30000) L_0x1e211c0/d; +v0x1c62fc0_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers +v0x1c63110_0 .net "b", 0 0, L_0x1e203e0; alias, 1 drivers +v0x1c631d0_0 .net "c1", 0 0, L_0x1e20d10; 1 drivers +v0x1c63270_0 .net "c2", 0 0, L_0x1c63430; 1 drivers +v0x1c63340_0 .net "carryin", 0 0, L_0x1e20020; alias, 1 drivers +v0x1c634c0_0 .net "carryout", 0 0, L_0x1e211c0; 1 drivers +v0x1c63560_0 .net "s1", 0 0, L_0x1e20c50; 1 drivers +v0x1c63600_0 .net "sum", 0 0, L_0x1e20e70; 1 drivers +S_0x1c62420 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c621d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e20c50/d .functor XOR 1, L_0x1e29ab0, L_0x1e203e0, C4<0>, C4<0>; +L_0x1e20c50 .delay 1 (30000,30000,30000) L_0x1e20c50/d; +L_0x1e20d10/d .functor AND 1, L_0x1e29ab0, L_0x1e203e0, C4<1>, C4<1>; +L_0x1e20d10 .delay 1 (30000,30000,30000) L_0x1e20d10/d; +v0x1c62680_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers +v0x1c62740_0 .net "b", 0 0, L_0x1e203e0; alias, 1 drivers +v0x1c62800_0 .net "carryout", 0 0, L_0x1e20d10; alias, 1 drivers +v0x1c628a0_0 .net "sum", 0 0, L_0x1e20c50; alias, 1 drivers +S_0x1c629d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c621d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e20e70/d .functor XOR 1, L_0x1e20c50, L_0x1e20020, C4<0>, C4<0>; +L_0x1e20e70 .delay 1 (30000,30000,30000) L_0x1e20e70/d; +L_0x1c63430/d .functor AND 1, L_0x1e20c50, L_0x1e20020, C4<1>, C4<1>; +L_0x1c63430 .delay 1 (30000,30000,30000) L_0x1c63430/d; +v0x1c62c30_0 .net "a", 0 0, L_0x1e20c50; alias, 1 drivers +v0x1c62d00_0 .net "b", 0 0, L_0x1e20020; alias, 1 drivers +v0x1c62da0_0 .net "carryout", 0 0, L_0x1c63430; alias, 1 drivers +v0x1c62e70_0 .net "sum", 0 0, L_0x1e20e70; alias, 1 drivers +S_0x1c64a20 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c54cc0; + .timescale -9 -12; +L_0x7f72592db458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db4a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e29b50/d .functor OR 1, L_0x7f72592db458, L_0x7f72592db4a0, C4<0>, C4<0>; +L_0x1e29b50 .delay 1 (30000,30000,30000) L_0x1e29b50/d; +v0x1c64c10_0 .net/2u *"_s0", 0 0, L_0x7f72592db458; 1 drivers +v0x1c64cf0_0 .net/2u *"_s2", 0 0, L_0x7f72592db4a0; 1 drivers +S_0x1c64dd0 .scope generate, "alu_slices[19]" "alu_slices[19]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c64fe0 .param/l "i" 0 3 37, +C4<010011>; +S_0x1c650a0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c64dd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e23b90/d .functor NOT 1, L_0x1e33710, C4<0>, C4<0>, C4<0>; +L_0x1e23b90 .delay 1 (10000,10000,10000) L_0x1e23b90/d; +L_0x1e29f20/d .functor NOT 1, L_0x1e29cb0, C4<0>, C4<0>, C4<0>; +L_0x1e29f20 .delay 1 (10000,10000,10000) L_0x1e29f20/d; +L_0x1e2af20/d .functor XOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; +L_0x1e2af20 .delay 1 (30000,30000,30000) L_0x1e2af20/d; +L_0x7f72592db4e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db530 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e2b5d0/d .functor OR 1, L_0x7f72592db4e8, L_0x7f72592db530, C4<0>, C4<0>; +L_0x1e2b5d0 .delay 1 (30000,30000,30000) L_0x1e2b5d0/d; +L_0x1e2b7d0/d .functor AND 1, L_0x1e33710, L_0x1e29cb0, C4<1>, C4<1>; +L_0x1e2b7d0 .delay 1 (30000,30000,30000) L_0x1e2b7d0/d; +L_0x1e2b890/d .functor NAND 1, L_0x1e33710, L_0x1e29cb0, C4<1>, C4<1>; +L_0x1e2b890 .delay 1 (20000,20000,20000) L_0x1e2b890/d; +L_0x1e2b9f0/d .functor XOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; +L_0x1e2b9f0 .delay 1 (20000,20000,20000) L_0x1e2b9f0/d; +L_0x1e2bea0/d .functor OR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; +L_0x1e2bea0 .delay 1 (30000,30000,30000) L_0x1e2bea0/d; +L_0x1e33610/d .functor NOT 1, L_0x1e2f810, C4<0>, C4<0>, C4<0>; +L_0x1e33610 .delay 1 (10000,10000,10000) L_0x1e33610/d; +v0x1c737e0_0 .net "A", 0 0, L_0x1e33710; 1 drivers +v0x1c738a0_0 .net "A_", 0 0, L_0x1e23b90; 1 drivers +v0x1c73960_0 .net "B", 0 0, L_0x1e29cb0; 1 drivers +v0x1c73a30_0 .net "B_", 0 0, L_0x1e29f20; 1 drivers +v0x1c73ad0_0 .net *"_s12", 0 0, L_0x1e2b5d0; 1 drivers +v0x1c73bc0_0 .net/2s *"_s14", 0 0, L_0x7f72592db4e8; 1 drivers +v0x1c73c80_0 .net/2s *"_s16", 0 0, L_0x7f72592db530; 1 drivers +v0x1c73d60_0 .net *"_s18", 0 0, L_0x1e2b7d0; 1 drivers +v0x1c73e40_0 .net *"_s20", 0 0, L_0x1e2b890; 1 drivers +v0x1c73fb0_0 .net *"_s22", 0 0, L_0x1e2b9f0; 1 drivers +v0x1c74090_0 .net *"_s24", 0 0, L_0x1e2bea0; 1 drivers +o0x7f72593827b8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1c74170_0 name=_s30 +o0x7f72593827e8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1c74250_0 name=_s32 +v0x1c74330_0 .net *"_s8", 0 0, L_0x1e2af20; 1 drivers +v0x1c74410_0 .net "carryin", 0 0, L_0x1e29d50; 1 drivers +v0x1c744b0_0 .net "carryout", 0 0, L_0x1e332b0; 1 drivers +v0x1c74550_0 .net "carryouts", 7 0, L_0x1ec0b60; 1 drivers +v0x1c74700_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c747a0_0 .net "result", 0 0, L_0x1e2f810; 1 drivers +v0x1c74890_0 .net "results", 7 0, L_0x1e2bc70; 1 drivers +v0x1c749a0_0 .net "zero", 0 0, L_0x1e33610; 1 drivers +LS_0x1e2bc70_0_0 .concat8 [ 1 1 1 1], L_0x1e2a440, L_0x1e2aa70, L_0x1e2af20, L_0x1e2b5d0; +LS_0x1e2bc70_0_4 .concat8 [ 1 1 1 1], L_0x1e2b7d0, L_0x1e2b890, L_0x1e2b9f0, L_0x1e2bea0; +L_0x1e2bc70 .concat8 [ 4 4 0 0], LS_0x1e2bc70_0_0, LS_0x1e2bc70_0_4; +LS_0x1ec0b60_0_0 .concat [ 1 1 1 1], L_0x1e2a6f0, L_0x1e2adc0, o0x7f72593827b8, L_0x1e2b420; +LS_0x1ec0b60_0_4 .concat [ 4 0 0 0], o0x7f72593827e8; +L_0x1ec0b60 .concat [ 4 4 0 0], LS_0x1ec0b60_0_0, LS_0x1ec0b60_0_4; +S_0x1c65320 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c650a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e2a6f0/d .functor OR 1, L_0x1e2a1d0, L_0x1e2a590, C4<0>, C4<0>; +L_0x1e2a6f0 .delay 1 (30000,30000,30000) L_0x1e2a6f0/d; +v0x1c66150_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers +v0x1c66210_0 .net "b", 0 0, L_0x1e29cb0; alias, 1 drivers +v0x1c662e0_0 .net "c1", 0 0, L_0x1e2a1d0; 1 drivers +v0x1c663e0_0 .net "c2", 0 0, L_0x1e2a590; 1 drivers +v0x1c664b0_0 .net "carryin", 0 0, L_0x1e29d50; alias, 1 drivers +v0x1c665a0_0 .net "carryout", 0 0, L_0x1e2a6f0; 1 drivers +v0x1c66640_0 .net "s1", 0 0, L_0x1e2a110; 1 drivers +v0x1c66730_0 .net "sum", 0 0, L_0x1e2a440; 1 drivers +S_0x1c65590 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c65320; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e2a110/d .functor XOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; +L_0x1e2a110 .delay 1 (30000,30000,30000) L_0x1e2a110/d; +L_0x1e2a1d0/d .functor AND 1, L_0x1e33710, L_0x1e29cb0, C4<1>, C4<1>; +L_0x1e2a1d0 .delay 1 (30000,30000,30000) L_0x1e2a1d0/d; +v0x1c657f0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers +v0x1c658d0_0 .net "b", 0 0, L_0x1e29cb0; alias, 1 drivers +v0x1c65990_0 .net "carryout", 0 0, L_0x1e2a1d0; alias, 1 drivers +v0x1c65a30_0 .net "sum", 0 0, L_0x1e2a110; alias, 1 drivers +S_0x1c65b70 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c65320; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e2a440/d .functor XOR 1, L_0x1e2a110, L_0x1e29d50, C4<0>, C4<0>; +L_0x1e2a440 .delay 1 (30000,30000,30000) L_0x1e2a440/d; +L_0x1e2a590/d .functor AND 1, L_0x1e2a110, L_0x1e29d50, C4<1>, C4<1>; +L_0x1e2a590 .delay 1 (30000,30000,30000) L_0x1e2a590/d; +v0x1c65dd0_0 .net "a", 0 0, L_0x1e2a110; alias, 1 drivers +v0x1c65e70_0 .net "b", 0 0, L_0x1e29d50; alias, 1 drivers +v0x1c65f10_0 .net "carryout", 0 0, L_0x1e2a590; alias, 1 drivers +v0x1c65fe0_0 .net "sum", 0 0, L_0x1e2a440; alias, 1 drivers +S_0x1c66800 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c650a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c6bbf0_0 .net "ands", 7 0, L_0x1e312b0; 1 drivers +v0x1c6bd00_0 .net "in", 7 0, L_0x1ec0b60; alias, 1 drivers +v0x1c6bdc0_0 .net "out", 0 0, L_0x1e332b0; alias, 1 drivers +v0x1c6be90_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c66a20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c66800; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c69150_0 .net "A", 7 0, L_0x1ec0b60; alias, 1 drivers +v0x1c69250_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c69310_0 .net *"_s0", 0 0, L_0x1e2fb70; 1 drivers +v0x1c693d0_0 .net *"_s12", 0 0, L_0x1e304e0; 1 drivers +v0x1c694b0_0 .net *"_s16", 0 0, L_0x1e30840; 1 drivers +v0x1c695e0_0 .net *"_s20", 0 0, L_0x1e30b50; 1 drivers +v0x1c696c0_0 .net *"_s24", 0 0, L_0x1e30f70; 1 drivers +v0x1c697a0_0 .net *"_s28", 0 0, L_0x1e30f00; 1 drivers +v0x1c69880_0 .net *"_s4", 0 0, L_0x1e2fe80; 1 drivers +v0x1c699f0_0 .net *"_s8", 0 0, L_0x1e301d0; 1 drivers +v0x1c69ad0_0 .net "out", 7 0, L_0x1e312b0; alias, 1 drivers +L_0x1e2fc30 .part L_0x1ec0b60, 0, 1; +L_0x1e2fd90 .part v0x1d6daa0_0, 0, 1; +L_0x1e2ff40 .part L_0x1ec0b60, 1, 1; +L_0x1e30130 .part v0x1d6daa0_0, 1, 1; +L_0x1e30290 .part L_0x1ec0b60, 2, 1; +L_0x1e303f0 .part v0x1d6daa0_0, 2, 1; +L_0x1e305a0 .part L_0x1ec0b60, 3, 1; +L_0x1e30700 .part v0x1d6daa0_0, 3, 1; +L_0x1e30900 .part L_0x1ec0b60, 4, 1; +L_0x1e30a60 .part v0x1d6daa0_0, 4, 1; +L_0x1e30bf0 .part L_0x1ec0b60, 5, 1; +L_0x1e30e60 .part v0x1d6daa0_0, 5, 1; +L_0x1e31060 .part L_0x1ec0b60, 6, 1; +L_0x1e311c0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e312b0_0_0 .concat8 [ 1 1 1 1], L_0x1e2fb70, L_0x1e2fe80, L_0x1e301d0, L_0x1e304e0; +LS_0x1e312b0_0_4 .concat8 [ 1 1 1 1], L_0x1e30840, L_0x1e30b50, L_0x1e30f70, L_0x1e30f00; +L_0x1e312b0 .concat8 [ 4 4 0 0], LS_0x1e312b0_0_0, LS_0x1e312b0_0_4; +L_0x1e31670 .part L_0x1ec0b60, 7, 1; +L_0x1e31860 .part v0x1d6daa0_0, 7, 1; +S_0x1c66c80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c66e90 .param/l "i" 0 4 54, +C4<00>; +L_0x1e2fb70/d .functor AND 1, L_0x1e2fc30, L_0x1e2fd90, C4<1>, C4<1>; +L_0x1e2fb70 .delay 1 (30000,30000,30000) L_0x1e2fb70/d; +v0x1c66f70_0 .net *"_s0", 0 0, L_0x1e2fc30; 1 drivers +v0x1c67050_0 .net *"_s1", 0 0, L_0x1e2fd90; 1 drivers +S_0x1c67130 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c67340 .param/l "i" 0 4 54, +C4<01>; +L_0x1e2fe80/d .functor AND 1, L_0x1e2ff40, L_0x1e30130, C4<1>, C4<1>; +L_0x1e2fe80 .delay 1 (30000,30000,30000) L_0x1e2fe80/d; +v0x1c67400_0 .net *"_s0", 0 0, L_0x1e2ff40; 1 drivers +v0x1c674e0_0 .net *"_s1", 0 0, L_0x1e30130; 1 drivers +S_0x1c675c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c677d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e301d0/d .functor AND 1, L_0x1e30290, L_0x1e303f0, C4<1>, C4<1>; +L_0x1e301d0 .delay 1 (30000,30000,30000) L_0x1e301d0/d; +v0x1c67870_0 .net *"_s0", 0 0, L_0x1e30290; 1 drivers +v0x1c67950_0 .net *"_s1", 0 0, L_0x1e303f0; 1 drivers +S_0x1c67a30 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c67c40 .param/l "i" 0 4 54, +C4<011>; +L_0x1e304e0/d .functor AND 1, L_0x1e305a0, L_0x1e30700, C4<1>, C4<1>; +L_0x1e304e0 .delay 1 (30000,30000,30000) L_0x1e304e0/d; +v0x1c67d00_0 .net *"_s0", 0 0, L_0x1e305a0; 1 drivers +v0x1c67de0_0 .net *"_s1", 0 0, L_0x1e30700; 1 drivers +S_0x1c67ec0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c68120 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e30840/d .functor AND 1, L_0x1e30900, L_0x1e30a60, C4<1>, C4<1>; +L_0x1e30840 .delay 1 (30000,30000,30000) L_0x1e30840/d; +v0x1c681e0_0 .net *"_s0", 0 0, L_0x1e30900; 1 drivers +v0x1c682c0_0 .net *"_s1", 0 0, L_0x1e30a60; 1 drivers +S_0x1c683a0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c685b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e30b50/d .functor AND 1, L_0x1e30bf0, L_0x1e30e60, C4<1>, C4<1>; +L_0x1e30b50 .delay 1 (30000,30000,30000) L_0x1e30b50/d; +v0x1c68670_0 .net *"_s0", 0 0, L_0x1e30bf0; 1 drivers +v0x1c68750_0 .net *"_s1", 0 0, L_0x1e30e60; 1 drivers +S_0x1c68830 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c68a40 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e30f70/d .functor AND 1, L_0x1e31060, L_0x1e311c0, C4<1>, C4<1>; +L_0x1e30f70 .delay 1 (30000,30000,30000) L_0x1e30f70/d; +v0x1c68b00_0 .net *"_s0", 0 0, L_0x1e31060; 1 drivers +v0x1c68be0_0 .net *"_s1", 0 0, L_0x1e311c0; 1 drivers +S_0x1c68cc0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c66a20; + .timescale -9 -12; +P_0x1c68ed0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e30f00/d .functor AND 1, L_0x1e31670, L_0x1e31860, C4<1>, C4<1>; +L_0x1e30f00 .delay 1 (30000,30000,30000) L_0x1e30f00/d; +v0x1c68f90_0 .net *"_s0", 0 0, L_0x1e31670; 1 drivers +v0x1c69070_0 .net *"_s1", 0 0, L_0x1e31860; 1 drivers +S_0x1c69c30 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c66800; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e332b0/d .functor OR 1, L_0x1e33370, L_0x1e33520, C4<0>, C4<0>; +L_0x1e332b0 .delay 1 (30000,30000,30000) L_0x1e332b0/d; +v0x1c6b780_0 .net *"_s10", 0 0, L_0x1e33370; 1 drivers +v0x1c6b860_0 .net *"_s12", 0 0, L_0x1e33520; 1 drivers +v0x1c6b940_0 .net "in", 7 0, L_0x1e312b0; alias, 1 drivers +v0x1c6ba10_0 .net "ors", 1 0, L_0x1e330d0; 1 drivers +v0x1c6bad0_0 .net "out", 0 0, L_0x1e332b0; alias, 1 drivers +L_0x1e324a0 .part L_0x1e312b0, 0, 4; +L_0x1e330d0 .concat8 [ 1 1 0 0], L_0x1e32190, L_0x1e32dc0; +L_0x1e33210 .part L_0x1e312b0, 4, 4; +L_0x1e33370 .part L_0x1e330d0, 0, 1; +L_0x1e33520 .part L_0x1e330d0, 1, 1; +S_0x1c69df0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c69c30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e31950/d .functor OR 1, L_0x1e31a10, L_0x1e31b70, C4<0>, C4<0>; +L_0x1e31950 .delay 1 (30000,30000,30000) L_0x1e31950/d; +L_0x1e31da0/d .functor OR 1, L_0x1e31eb0, L_0x1e32010, C4<0>, C4<0>; +L_0x1e31da0 .delay 1 (30000,30000,30000) L_0x1e31da0/d; +L_0x1e32190/d .functor OR 1, L_0x1e32200, L_0x1e323b0, C4<0>, C4<0>; +L_0x1e32190 .delay 1 (30000,30000,30000) L_0x1e32190/d; +v0x1c6a040_0 .net *"_s0", 0 0, L_0x1e31950; 1 drivers +v0x1c6a140_0 .net *"_s10", 0 0, L_0x1e31eb0; 1 drivers +v0x1c6a220_0 .net *"_s12", 0 0, L_0x1e32010; 1 drivers +v0x1c6a2e0_0 .net *"_s14", 0 0, L_0x1e32200; 1 drivers +v0x1c6a3c0_0 .net *"_s16", 0 0, L_0x1e323b0; 1 drivers +v0x1c6a4f0_0 .net *"_s3", 0 0, L_0x1e31a10; 1 drivers +v0x1c6a5d0_0 .net *"_s5", 0 0, L_0x1e31b70; 1 drivers +v0x1c6a6b0_0 .net *"_s6", 0 0, L_0x1e31da0; 1 drivers +v0x1c6a790_0 .net "in", 3 0, L_0x1e324a0; 1 drivers +v0x1c6a900_0 .net "ors", 1 0, L_0x1e31cb0; 1 drivers +v0x1c6a9e0_0 .net "out", 0 0, L_0x1e32190; 1 drivers +L_0x1e31a10 .part L_0x1e324a0, 0, 1; +L_0x1e31b70 .part L_0x1e324a0, 1, 1; +L_0x1e31cb0 .concat8 [ 1 1 0 0], L_0x1e31950, L_0x1e31da0; +L_0x1e31eb0 .part L_0x1e324a0, 2, 1; +L_0x1e32010 .part L_0x1e324a0, 3, 1; +L_0x1e32200 .part L_0x1e31cb0, 0, 1; +L_0x1e323b0 .part L_0x1e31cb0, 1, 1; +S_0x1c6ab00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c69c30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e325d0/d .functor OR 1, L_0x1e32640, L_0x1e327a0, C4<0>, C4<0>; +L_0x1e325d0 .delay 1 (30000,30000,30000) L_0x1e325d0/d; +L_0x1e329d0/d .functor OR 1, L_0x1e32ae0, L_0x1e32c40, C4<0>, C4<0>; +L_0x1e329d0 .delay 1 (30000,30000,30000) L_0x1e329d0/d; +L_0x1e32dc0/d .functor OR 1, L_0x1e32e30, L_0x1e32fe0, C4<0>, C4<0>; +L_0x1e32dc0 .delay 1 (30000,30000,30000) L_0x1e32dc0/d; +v0x1c6acc0_0 .net *"_s0", 0 0, L_0x1e325d0; 1 drivers +v0x1c6adc0_0 .net *"_s10", 0 0, L_0x1e32ae0; 1 drivers +v0x1c6aea0_0 .net *"_s12", 0 0, L_0x1e32c40; 1 drivers +v0x1c6af60_0 .net *"_s14", 0 0, L_0x1e32e30; 1 drivers +v0x1c6b040_0 .net *"_s16", 0 0, L_0x1e32fe0; 1 drivers +v0x1c6b170_0 .net *"_s3", 0 0, L_0x1e32640; 1 drivers +v0x1c6b250_0 .net *"_s5", 0 0, L_0x1e327a0; 1 drivers +v0x1c6b330_0 .net *"_s6", 0 0, L_0x1e329d0; 1 drivers +v0x1c6b410_0 .net "in", 3 0, L_0x1e33210; 1 drivers +v0x1c6b580_0 .net "ors", 1 0, L_0x1e328e0; 1 drivers +v0x1c6b660_0 .net "out", 0 0, L_0x1e32dc0; 1 drivers +L_0x1e32640 .part L_0x1e33210, 0, 1; +L_0x1e327a0 .part L_0x1e33210, 1, 1; +L_0x1e328e0 .concat8 [ 1 1 0 0], L_0x1e325d0, L_0x1e329d0; +L_0x1e32ae0 .part L_0x1e33210, 2, 1; +L_0x1e32c40 .part L_0x1e33210, 3, 1; +L_0x1e32e30 .part L_0x1e328e0, 0, 1; +L_0x1e32fe0 .part L_0x1e328e0, 1, 1; +S_0x1c6bf70 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c650a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c713b0_0 .net "ands", 7 0, L_0x1e2d810; 1 drivers +v0x1c714c0_0 .net "in", 7 0, L_0x1e2bc70; alias, 1 drivers +v0x1c71580_0 .net "out", 0 0, L_0x1e2f810; alias, 1 drivers +v0x1c71650_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c6c1c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c6bf70; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c6e900_0 .net "A", 7 0, L_0x1e2bc70; alias, 1 drivers +v0x1c6ea00_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c6eac0_0 .net *"_s0", 0 0, L_0x1e2c000; 1 drivers +v0x1c6eb80_0 .net *"_s12", 0 0, L_0x1e2c9c0; 1 drivers +v0x1c6ec60_0 .net *"_s16", 0 0, L_0x1e2cd20; 1 drivers +v0x1c6ed90_0 .net *"_s20", 0 0, L_0x1e2d150; 1 drivers +v0x1c6ee70_0 .net *"_s24", 0 0, L_0x1e2d480; 1 drivers +v0x1c6ef50_0 .net *"_s28", 0 0, L_0x1e2d410; 1 drivers +v0x1c6f030_0 .net *"_s4", 0 0, L_0x1e2c3a0; 1 drivers +v0x1c6f1a0_0 .net *"_s8", 0 0, L_0x1e2c6b0; 1 drivers +v0x1c6f280_0 .net "out", 7 0, L_0x1e2d810; alias, 1 drivers +L_0x1e2c110 .part L_0x1e2bc70, 0, 1; +L_0x1e2c300 .part v0x1d6daa0_0, 0, 1; +L_0x1e2c460 .part L_0x1e2bc70, 1, 1; +L_0x1e2c5c0 .part v0x1d6daa0_0, 1, 1; +L_0x1e2c770 .part L_0x1e2bc70, 2, 1; +L_0x1e2c8d0 .part v0x1d6daa0_0, 2, 1; +L_0x1e2ca80 .part L_0x1e2bc70, 3, 1; +L_0x1e2cbe0 .part v0x1d6daa0_0, 3, 1; +L_0x1e2cde0 .part L_0x1e2bc70, 4, 1; +L_0x1e2d050 .part v0x1d6daa0_0, 4, 1; +L_0x1e2d1c0 .part L_0x1e2bc70, 5, 1; +L_0x1e2d320 .part v0x1d6daa0_0, 5, 1; +L_0x1e2d540 .part L_0x1e2bc70, 6, 1; +L_0x1e2d6a0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e2d810_0_0 .concat8 [ 1 1 1 1], L_0x1e2c000, L_0x1e2c3a0, L_0x1e2c6b0, L_0x1e2c9c0; +LS_0x1e2d810_0_4 .concat8 [ 1 1 1 1], L_0x1e2cd20, L_0x1e2d150, L_0x1e2d480, L_0x1e2d410; +L_0x1e2d810 .concat8 [ 4 4 0 0], LS_0x1e2d810_0_0, LS_0x1e2d810_0_4; +L_0x1e2dbd0 .part L_0x1e2bc70, 7, 1; +L_0x1e2ddc0 .part v0x1d6daa0_0, 7, 1; +S_0x1c6c400 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6c610 .param/l "i" 0 4 54, +C4<00>; +L_0x1e2c000/d .functor AND 1, L_0x1e2c110, L_0x1e2c300, C4<1>, C4<1>; +L_0x1e2c000 .delay 1 (30000,30000,30000) L_0x1e2c000/d; +v0x1c6c6f0_0 .net *"_s0", 0 0, L_0x1e2c110; 1 drivers +v0x1c6c7d0_0 .net *"_s1", 0 0, L_0x1e2c300; 1 drivers +S_0x1c6c8b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6cac0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e2c3a0/d .functor AND 1, L_0x1e2c460, L_0x1e2c5c0, C4<1>, C4<1>; +L_0x1e2c3a0 .delay 1 (30000,30000,30000) L_0x1e2c3a0/d; +v0x1c6cb80_0 .net *"_s0", 0 0, L_0x1e2c460; 1 drivers +v0x1c6cc60_0 .net *"_s1", 0 0, L_0x1e2c5c0; 1 drivers +S_0x1c6cd40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6cf80 .param/l "i" 0 4 54, +C4<010>; +L_0x1e2c6b0/d .functor AND 1, L_0x1e2c770, L_0x1e2c8d0, C4<1>, C4<1>; +L_0x1e2c6b0 .delay 1 (30000,30000,30000) L_0x1e2c6b0/d; +v0x1c6d020_0 .net *"_s0", 0 0, L_0x1e2c770; 1 drivers +v0x1c6d100_0 .net *"_s1", 0 0, L_0x1e2c8d0; 1 drivers +S_0x1c6d1e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6d3f0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e2c9c0/d .functor AND 1, L_0x1e2ca80, L_0x1e2cbe0, C4<1>, C4<1>; +L_0x1e2c9c0 .delay 1 (30000,30000,30000) L_0x1e2c9c0/d; +v0x1c6d4b0_0 .net *"_s0", 0 0, L_0x1e2ca80; 1 drivers +v0x1c6d590_0 .net *"_s1", 0 0, L_0x1e2cbe0; 1 drivers +S_0x1c6d670 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6d8d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e2cd20/d .functor AND 1, L_0x1e2cde0, L_0x1e2d050, C4<1>, C4<1>; +L_0x1e2cd20 .delay 1 (30000,30000,30000) L_0x1e2cd20/d; +v0x1c6d990_0 .net *"_s0", 0 0, L_0x1e2cde0; 1 drivers +v0x1c6da70_0 .net *"_s1", 0 0, L_0x1e2d050; 1 drivers +S_0x1c6db50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6dd60 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e2d150/d .functor AND 1, L_0x1e2d1c0, L_0x1e2d320, C4<1>, C4<1>; +L_0x1e2d150 .delay 1 (30000,30000,30000) L_0x1e2d150/d; +v0x1c6de20_0 .net *"_s0", 0 0, L_0x1e2d1c0; 1 drivers +v0x1c6df00_0 .net *"_s1", 0 0, L_0x1e2d320; 1 drivers +S_0x1c6dfe0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6e1f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e2d480/d .functor AND 1, L_0x1e2d540, L_0x1e2d6a0, C4<1>, C4<1>; +L_0x1e2d480 .delay 1 (30000,30000,30000) L_0x1e2d480/d; +v0x1c6e2b0_0 .net *"_s0", 0 0, L_0x1e2d540; 1 drivers +v0x1c6e390_0 .net *"_s1", 0 0, L_0x1e2d6a0; 1 drivers +S_0x1c6e470 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c6c1c0; + .timescale -9 -12; +P_0x1c6e680 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e2d410/d .functor AND 1, L_0x1e2dbd0, L_0x1e2ddc0, C4<1>, C4<1>; +L_0x1e2d410 .delay 1 (30000,30000,30000) L_0x1e2d410/d; +v0x1c6e740_0 .net *"_s0", 0 0, L_0x1e2dbd0; 1 drivers +v0x1c6e820_0 .net *"_s1", 0 0, L_0x1e2ddc0; 1 drivers +S_0x1c6f3e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c6bf70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e2f810/d .functor OR 1, L_0x1e2f8d0, L_0x1e2fa80, C4<0>, C4<0>; +L_0x1e2f810 .delay 1 (30000,30000,30000) L_0x1e2f810/d; +v0x1c70f40_0 .net *"_s10", 0 0, L_0x1e2f8d0; 1 drivers +v0x1c71020_0 .net *"_s12", 0 0, L_0x1e2fa80; 1 drivers +v0x1c71100_0 .net "in", 7 0, L_0x1e2d810; alias, 1 drivers +v0x1c711d0_0 .net "ors", 1 0, L_0x1e2f630; 1 drivers +v0x1c71290_0 .net "out", 0 0, L_0x1e2f810; alias, 1 drivers +L_0x1e2ea00 .part L_0x1e2d810, 0, 4; +L_0x1e2f630 .concat8 [ 1 1 0 0], L_0x1e2e6f0, L_0x1e2f320; +L_0x1e2f770 .part L_0x1e2d810, 4, 4; +L_0x1e2f8d0 .part L_0x1e2f630, 0, 1; +L_0x1e2fa80 .part L_0x1e2f630, 1, 1; +S_0x1c6f5a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c6f3e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e2deb0/d .functor OR 1, L_0x1e2df70, L_0x1e2e0d0, C4<0>, C4<0>; +L_0x1e2deb0 .delay 1 (30000,30000,30000) L_0x1e2deb0/d; +L_0x1e2e300/d .functor OR 1, L_0x1e2e410, L_0x1e2e570, C4<0>, C4<0>; +L_0x1e2e300 .delay 1 (30000,30000,30000) L_0x1e2e300/d; +L_0x1e2e6f0/d .functor OR 1, L_0x1e2e760, L_0x1e2e910, C4<0>, C4<0>; +L_0x1e2e6f0 .delay 1 (30000,30000,30000) L_0x1e2e6f0/d; +v0x1c6f7f0_0 .net *"_s0", 0 0, L_0x1e2deb0; 1 drivers +v0x1c6f8f0_0 .net *"_s10", 0 0, L_0x1e2e410; 1 drivers +v0x1c6f9d0_0 .net *"_s12", 0 0, L_0x1e2e570; 1 drivers +v0x1c6fa90_0 .net *"_s14", 0 0, L_0x1e2e760; 1 drivers +v0x1c6fb70_0 .net *"_s16", 0 0, L_0x1e2e910; 1 drivers +v0x1c6fca0_0 .net *"_s3", 0 0, L_0x1e2df70; 1 drivers +v0x1c6fd80_0 .net *"_s5", 0 0, L_0x1e2e0d0; 1 drivers +v0x1c6fe60_0 .net *"_s6", 0 0, L_0x1e2e300; 1 drivers +v0x1c6ff40_0 .net "in", 3 0, L_0x1e2ea00; 1 drivers +v0x1c70090_0 .net "ors", 1 0, L_0x1e2e210; 1 drivers +v0x1c70170_0 .net "out", 0 0, L_0x1e2e6f0; 1 drivers +L_0x1e2df70 .part L_0x1e2ea00, 0, 1; +L_0x1e2e0d0 .part L_0x1e2ea00, 1, 1; +L_0x1e2e210 .concat8 [ 1 1 0 0], L_0x1e2deb0, L_0x1e2e300; +L_0x1e2e410 .part L_0x1e2ea00, 2, 1; +L_0x1e2e570 .part L_0x1e2ea00, 3, 1; +L_0x1e2e760 .part L_0x1e2e210, 0, 1; +L_0x1e2e910 .part L_0x1e2e210, 1, 1; +S_0x1c70290 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c6f3e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e2eb30/d .functor OR 1, L_0x1e2eba0, L_0x1e2ed00, C4<0>, C4<0>; +L_0x1e2eb30 .delay 1 (30000,30000,30000) L_0x1e2eb30/d; +L_0x1e2ef30/d .functor OR 1, L_0x1e2f040, L_0x1e2f1a0, C4<0>, C4<0>; +L_0x1e2ef30 .delay 1 (30000,30000,30000) L_0x1e2ef30/d; +L_0x1e2f320/d .functor OR 1, L_0x1e2f390, L_0x1e2f540, C4<0>, C4<0>; +L_0x1e2f320 .delay 1 (30000,30000,30000) L_0x1e2f320/d; +v0x1c70450_0 .net *"_s0", 0 0, L_0x1e2eb30; 1 drivers +v0x1c70550_0 .net *"_s10", 0 0, L_0x1e2f040; 1 drivers +v0x1c70630_0 .net *"_s12", 0 0, L_0x1e2f1a0; 1 drivers +v0x1c70720_0 .net *"_s14", 0 0, L_0x1e2f390; 1 drivers +v0x1c70800_0 .net *"_s16", 0 0, L_0x1e2f540; 1 drivers +v0x1c70930_0 .net *"_s3", 0 0, L_0x1e2eba0; 1 drivers +v0x1c70a10_0 .net *"_s5", 0 0, L_0x1e2ed00; 1 drivers +v0x1c70af0_0 .net *"_s6", 0 0, L_0x1e2ef30; 1 drivers +v0x1c70bd0_0 .net "in", 3 0, L_0x1e2f770; 1 drivers +v0x1c70d40_0 .net "ors", 1 0, L_0x1e2ee40; 1 drivers +v0x1c70e20_0 .net "out", 0 0, L_0x1e2f320; 1 drivers +L_0x1e2eba0 .part L_0x1e2f770, 0, 1; +L_0x1e2ed00 .part L_0x1e2f770, 1, 1; +L_0x1e2ee40 .concat8 [ 1 1 0 0], L_0x1e2eb30, L_0x1e2ef30; +L_0x1e2f040 .part L_0x1e2f770, 2, 1; +L_0x1e2f1a0 .part L_0x1e2f770, 3, 1; +L_0x1e2f390 .part L_0x1e2ee40, 0, 1; +L_0x1e2f540 .part L_0x1e2ee40, 1, 1; +S_0x1c71730 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c650a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e2afe0/d .functor XNOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; +L_0x1e2afe0 .delay 1 (20000,20000,20000) L_0x1e2afe0/d; +L_0x1e2b250/d .functor AND 1, L_0x1e33710, L_0x1e29f20, C4<1>, C4<1>; +L_0x1e2b250 .delay 1 (30000,30000,30000) L_0x1e2b250/d; +L_0x1e2b2c0/d .functor AND 1, L_0x1e2afe0, L_0x1e29d50, C4<1>, C4<1>; +L_0x1e2b2c0 .delay 1 (30000,30000,30000) L_0x1e2b2c0/d; +L_0x1e2b420/d .functor OR 1, L_0x1e2b2c0, L_0x1e2b250, C4<0>, C4<0>; +L_0x1e2b420 .delay 1 (30000,30000,30000) L_0x1e2b420/d; +v0x1c719e0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers +v0x1c71ad0_0 .net "a_", 0 0, L_0x1e23b90; alias, 1 drivers +v0x1c71b90_0 .net "b", 0 0, L_0x1e29cb0; alias, 1 drivers +v0x1c71c80_0 .net "b_", 0 0, L_0x1e29f20; alias, 1 drivers +v0x1c71d20_0 .net "carryin", 0 0, L_0x1e29d50; alias, 1 drivers +v0x1c71e60_0 .net "eq", 0 0, L_0x1e2afe0; 1 drivers +v0x1c71f20_0 .net "lt", 0 0, L_0x1e2b250; 1 drivers +v0x1c71fe0_0 .net "out", 0 0, L_0x1e2b420; 1 drivers +v0x1c720a0_0 .net "w0", 0 0, L_0x1e2b2c0; 1 drivers +S_0x1c722f0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c650a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e2adc0/d .functor OR 1, L_0x1e2a910, L_0x1c73550, C4<0>, C4<0>; +L_0x1e2adc0 .delay 1 (30000,30000,30000) L_0x1e2adc0/d; +v0x1c730e0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers +v0x1c73230_0 .net "b", 0 0, L_0x1e29f20; alias, 1 drivers +v0x1c732f0_0 .net "c1", 0 0, L_0x1e2a910; 1 drivers +v0x1c73390_0 .net "c2", 0 0, L_0x1c73550; 1 drivers +v0x1c73460_0 .net "carryin", 0 0, L_0x1e29d50; alias, 1 drivers +v0x1c735e0_0 .net "carryout", 0 0, L_0x1e2adc0; 1 drivers +v0x1c73680_0 .net "s1", 0 0, L_0x1e2a850; 1 drivers +v0x1c73720_0 .net "sum", 0 0, L_0x1e2aa70; 1 drivers +S_0x1c72540 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c722f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e2a850/d .functor XOR 1, L_0x1e33710, L_0x1e29f20, C4<0>, C4<0>; +L_0x1e2a850 .delay 1 (30000,30000,30000) L_0x1e2a850/d; +L_0x1e2a910/d .functor AND 1, L_0x1e33710, L_0x1e29f20, C4<1>, C4<1>; +L_0x1e2a910 .delay 1 (30000,30000,30000) L_0x1e2a910/d; +v0x1c727a0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers +v0x1c72860_0 .net "b", 0 0, L_0x1e29f20; alias, 1 drivers +v0x1c72920_0 .net "carryout", 0 0, L_0x1e2a910; alias, 1 drivers +v0x1c729c0_0 .net "sum", 0 0, L_0x1e2a850; alias, 1 drivers +S_0x1c72af0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c722f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e2aa70/d .functor XOR 1, L_0x1e2a850, L_0x1e29d50, C4<0>, C4<0>; +L_0x1e2aa70 .delay 1 (30000,30000,30000) L_0x1e2aa70/d; +L_0x1c73550/d .functor AND 1, L_0x1e2a850, L_0x1e29d50, C4<1>, C4<1>; +L_0x1c73550 .delay 1 (30000,30000,30000) L_0x1c73550/d; +v0x1c72d50_0 .net "a", 0 0, L_0x1e2a850; alias, 1 drivers +v0x1c72e20_0 .net "b", 0 0, L_0x1e29d50; alias, 1 drivers +v0x1c72ec0_0 .net "carryout", 0 0, L_0x1c73550; alias, 1 drivers +v0x1c72f90_0 .net "sum", 0 0, L_0x1e2aa70; alias, 1 drivers +S_0x1c74b40 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c64dd0; + .timescale -9 -12; +L_0x7f72592db578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db5c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e337b0/d .functor OR 1, L_0x7f72592db578, L_0x7f72592db5c0, C4<0>, C4<0>; +L_0x1e337b0 .delay 1 (30000,30000,30000) L_0x1e337b0/d; +v0x1c74d30_0 .net/2u *"_s0", 0 0, L_0x7f72592db578; 1 drivers +v0x1c74e10_0 .net/2u *"_s2", 0 0, L_0x7f72592db5c0; 1 drivers +S_0x1c74ef0 .scope generate, "alu_slices[20]" "alu_slices[20]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1c75100 .param/l "i" 0 3 37, +C4<010100>; +S_0x1c751c0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c74ef0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e33b00/d .functor NOT 1, L_0x1e3d390, C4<0>, C4<0>, C4<0>; +L_0x1e33b00 .delay 1 (10000,10000,10000) L_0x1e33b00/d; +L_0x1e33c60/d .functor NOT 1, L_0x1e3d4f0, C4<0>, C4<0>, C4<0>; +L_0x1e33c60 .delay 1 (10000,10000,10000) L_0x1e33c60/d; +L_0x1e34cb0/d .functor XOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; +L_0x1e34cb0 .delay 1 (30000,30000,30000) L_0x1e34cb0/d; +L_0x7f72592db608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e35360/d .functor OR 1, L_0x7f72592db608, L_0x7f72592db650, C4<0>, C4<0>; +L_0x1e35360 .delay 1 (30000,30000,30000) L_0x1e35360/d; +L_0x1e35560/d .functor AND 1, L_0x1e3d390, L_0x1e3d4f0, C4<1>, C4<1>; +L_0x1e35560 .delay 1 (30000,30000,30000) L_0x1e35560/d; +L_0x1e35620/d .functor NAND 1, L_0x1e3d390, L_0x1e3d4f0, C4<1>, C4<1>; +L_0x1e35620 .delay 1 (20000,20000,20000) L_0x1e35620/d; +L_0x1e35780/d .functor XOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; +L_0x1e35780 .delay 1 (20000,20000,20000) L_0x1e35780/d; +L_0x1e35c30/d .functor OR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; +L_0x1e35c30 .delay 1 (30000,30000,30000) L_0x1e35c30/d; +L_0x1e3d290/d .functor NOT 1, L_0x1e394c0, C4<0>, C4<0>, C4<0>; +L_0x1e3d290 .delay 1 (10000,10000,10000) L_0x1e3d290/d; +v0x1ca38f0_0 .net "A", 0 0, L_0x1e3d390; 1 drivers +v0x1ca39b0_0 .net "A_", 0 0, L_0x1e33b00; 1 drivers +v0x1ca3a70_0 .net "B", 0 0, L_0x1e3d4f0; 1 drivers +v0x1ca3b40_0 .net "B_", 0 0, L_0x1e33c60; 1 drivers +v0x1ca3be0_0 .net *"_s12", 0 0, L_0x1e35360; 1 drivers +v0x1ca3cd0_0 .net/2s *"_s14", 0 0, L_0x7f72592db608; 1 drivers +v0x1ca3d90_0 .net/2s *"_s16", 0 0, L_0x7f72592db650; 1 drivers +v0x1ca3e70_0 .net *"_s18", 0 0, L_0x1e35560; 1 drivers +v0x1ca3f50_0 .net *"_s20", 0 0, L_0x1e35620; 1 drivers +v0x1ca40c0_0 .net *"_s22", 0 0, L_0x1e35780; 1 drivers +v0x1ca41a0_0 .net *"_s24", 0 0, L_0x1e35c30; 1 drivers +o0x7f7259323d08 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1ca4280_0 name=_s30 +o0x7f7259323d38 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1ca4360_0 name=_s32 +v0x1ca4440_0 .net *"_s8", 0 0, L_0x1e34cb0; 1 drivers +v0x1ca4520_0 .net "carryin", 0 0, L_0x1e33870; 1 drivers +v0x1ca45c0_0 .net "carryout", 0 0, L_0x1e3cf30; 1 drivers +v0x1ca4660_0 .net "carryouts", 7 0, L_0x1ec0d30; 1 drivers +v0x1ca4810_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ca48b0_0 .net "result", 0 0, L_0x1e394c0; 1 drivers +v0x1ca49a0_0 .net "results", 7 0, L_0x1e35a00; 1 drivers +v0x1ca4ab0_0 .net "zero", 0 0, L_0x1e3d290; 1 drivers +LS_0x1e35a00_0_0 .concat8 [ 1 1 1 1], L_0x1e34180, L_0x1e347b0, L_0x1e34cb0, L_0x1e35360; +LS_0x1e35a00_0_4 .concat8 [ 1 1 1 1], L_0x1e35560, L_0x1e35620, L_0x1e35780, L_0x1e35c30; +L_0x1e35a00 .concat8 [ 4 4 0 0], LS_0x1e35a00_0_0, LS_0x1e35a00_0_4; +LS_0x1ec0d30_0_0 .concat [ 1 1 1 1], L_0x1e34430, L_0x1e34b50, o0x7f7259323d08, L_0x1e351b0; +LS_0x1ec0d30_0_4 .concat [ 4 0 0 0], o0x7f7259323d38; +L_0x1ec0d30 .concat [ 4 4 0 0], LS_0x1ec0d30_0_0, LS_0x1ec0d30_0_4; +S_0x1c75440 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c751c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e34430/d .functor OR 1, L_0x1e33f10, L_0x1e342d0, C4<0>, C4<0>; +L_0x1e34430 .delay 1 (30000,30000,30000) L_0x1e34430/d; +v0x1c76270_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers +v0x1c76330_0 .net "b", 0 0, L_0x1e3d4f0; alias, 1 drivers +v0x1c76400_0 .net "c1", 0 0, L_0x1e33f10; 1 drivers +v0x1c76500_0 .net "c2", 0 0, L_0x1e342d0; 1 drivers +v0x1c765d0_0 .net "carryin", 0 0, L_0x1e33870; alias, 1 drivers +v0x1c766c0_0 .net "carryout", 0 0, L_0x1e34430; 1 drivers +v0x1c76760_0 .net "s1", 0 0, L_0x1e33e50; 1 drivers +v0x1c76850_0 .net "sum", 0 0, L_0x1e34180; 1 drivers +S_0x1c756b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c75440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e33e50/d .functor XOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; +L_0x1e33e50 .delay 1 (30000,30000,30000) L_0x1e33e50/d; +L_0x1e33f10/d .functor AND 1, L_0x1e3d390, L_0x1e3d4f0, C4<1>, C4<1>; +L_0x1e33f10 .delay 1 (30000,30000,30000) L_0x1e33f10/d; +v0x1c75910_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers +v0x1c759f0_0 .net "b", 0 0, L_0x1e3d4f0; alias, 1 drivers +v0x1c75ab0_0 .net "carryout", 0 0, L_0x1e33f10; alias, 1 drivers +v0x1c75b50_0 .net "sum", 0 0, L_0x1e33e50; alias, 1 drivers +S_0x1c75c90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c75440; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e34180/d .functor XOR 1, L_0x1e33e50, L_0x1e33870, C4<0>, C4<0>; +L_0x1e34180 .delay 1 (30000,30000,30000) L_0x1e34180/d; +L_0x1e342d0/d .functor AND 1, L_0x1e33e50, L_0x1e33870, C4<1>, C4<1>; +L_0x1e342d0 .delay 1 (30000,30000,30000) L_0x1e342d0/d; +v0x1c75ef0_0 .net "a", 0 0, L_0x1e33e50; alias, 1 drivers +v0x1c75f90_0 .net "b", 0 0, L_0x1e33870; alias, 1 drivers +v0x1c76030_0 .net "carryout", 0 0, L_0x1e342d0; alias, 1 drivers +v0x1c76100_0 .net "sum", 0 0, L_0x1e34180; alias, 1 drivers +S_0x1c76920 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c751c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1c7bd10_0 .net "ands", 7 0, L_0x1e3af60; 1 drivers +v0x1c7be20_0 .net "in", 7 0, L_0x1ec0d30; alias, 1 drivers +v0x1c7bee0_0 .net "out", 0 0, L_0x1e3cf30; alias, 1 drivers +v0x1c7bfb0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c76b40 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c76920; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c79270_0 .net "A", 7 0, L_0x1ec0d30; alias, 1 drivers +v0x1c79370_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c79430_0 .net *"_s0", 0 0, L_0x1e39820; 1 drivers +v0x1c794f0_0 .net *"_s12", 0 0, L_0x1e3a190; 1 drivers +v0x1c795d0_0 .net *"_s16", 0 0, L_0x1e3a4f0; 1 drivers +v0x1c79700_0 .net *"_s20", 0 0, L_0x1e3a800; 1 drivers +v0x1c797e0_0 .net *"_s24", 0 0, L_0x1e3ac50; 1 drivers +v0x1c798c0_0 .net *"_s28", 0 0, L_0x1e3b1e0; 1 drivers +v0x1c799a0_0 .net *"_s4", 0 0, L_0x1e39b30; 1 drivers +v0x1c79b10_0 .net *"_s8", 0 0, L_0x1e39e80; 1 drivers +v0x1c79bf0_0 .net "out", 7 0, L_0x1e3af60; alias, 1 drivers +L_0x1e398e0 .part L_0x1ec0d30, 0, 1; +L_0x1e39a40 .part v0x1d6daa0_0, 0, 1; +L_0x1e39bf0 .part L_0x1ec0d30, 1, 1; +L_0x1e39de0 .part v0x1d6daa0_0, 1, 1; +L_0x1e39f40 .part L_0x1ec0d30, 2, 1; +L_0x1e3a0a0 .part v0x1d6daa0_0, 2, 1; +L_0x1e3a250 .part L_0x1ec0d30, 3, 1; +L_0x1e3a3b0 .part v0x1d6daa0_0, 3, 1; +L_0x1e3a5b0 .part L_0x1ec0d30, 4, 1; +L_0x1e3a710 .part v0x1d6daa0_0, 4, 1; +L_0x1e3a8d0 .part L_0x1ec0d30, 5, 1; +L_0x1e3ab40 .part v0x1d6daa0_0, 5, 1; +L_0x1e3ad10 .part L_0x1ec0d30, 6, 1; +L_0x1e3ae70 .part v0x1d6daa0_0, 6, 1; +LS_0x1e3af60_0_0 .concat8 [ 1 1 1 1], L_0x1e39820, L_0x1e39b30, L_0x1e39e80, L_0x1e3a190; +LS_0x1e3af60_0_4 .concat8 [ 1 1 1 1], L_0x1e3a4f0, L_0x1e3a800, L_0x1e3ac50, L_0x1e3b1e0; +L_0x1e3af60 .concat8 [ 4 4 0 0], LS_0x1e3af60_0_0, LS_0x1e3af60_0_4; +L_0x1e3b2f0 .part L_0x1ec0d30, 7, 1; +L_0x1e3b4e0 .part v0x1d6daa0_0, 7, 1; +S_0x1c76da0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c76fb0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e39820/d .functor AND 1, L_0x1e398e0, L_0x1e39a40, C4<1>, C4<1>; +L_0x1e39820 .delay 1 (30000,30000,30000) L_0x1e39820/d; +v0x1c77090_0 .net *"_s0", 0 0, L_0x1e398e0; 1 drivers +v0x1c77170_0 .net *"_s1", 0 0, L_0x1e39a40; 1 drivers +S_0x1c77250 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c77460 .param/l "i" 0 4 54, +C4<01>; +L_0x1e39b30/d .functor AND 1, L_0x1e39bf0, L_0x1e39de0, C4<1>, C4<1>; +L_0x1e39b30 .delay 1 (30000,30000,30000) L_0x1e39b30/d; +v0x1c77520_0 .net *"_s0", 0 0, L_0x1e39bf0; 1 drivers +v0x1c77600_0 .net *"_s1", 0 0, L_0x1e39de0; 1 drivers +S_0x1c776e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c778f0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e39e80/d .functor AND 1, L_0x1e39f40, L_0x1e3a0a0, C4<1>, C4<1>; +L_0x1e39e80 .delay 1 (30000,30000,30000) L_0x1e39e80/d; +v0x1c77990_0 .net *"_s0", 0 0, L_0x1e39f40; 1 drivers +v0x1c77a70_0 .net *"_s1", 0 0, L_0x1e3a0a0; 1 drivers +S_0x1c77b50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c77d60 .param/l "i" 0 4 54, +C4<011>; +L_0x1e3a190/d .functor AND 1, L_0x1e3a250, L_0x1e3a3b0, C4<1>, C4<1>; +L_0x1e3a190 .delay 1 (30000,30000,30000) L_0x1e3a190/d; +v0x1c77e20_0 .net *"_s0", 0 0, L_0x1e3a250; 1 drivers +v0x1c77f00_0 .net *"_s1", 0 0, L_0x1e3a3b0; 1 drivers +S_0x1c77fe0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c78240 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e3a4f0/d .functor AND 1, L_0x1e3a5b0, L_0x1e3a710, C4<1>, C4<1>; +L_0x1e3a4f0 .delay 1 (30000,30000,30000) L_0x1e3a4f0/d; +v0x1c78300_0 .net *"_s0", 0 0, L_0x1e3a5b0; 1 drivers +v0x1c783e0_0 .net *"_s1", 0 0, L_0x1e3a710; 1 drivers +S_0x1c784c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c786d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e3a800/d .functor AND 1, L_0x1e3a8d0, L_0x1e3ab40, C4<1>, C4<1>; +L_0x1e3a800 .delay 1 (30000,30000,30000) L_0x1e3a800/d; +v0x1c78790_0 .net *"_s0", 0 0, L_0x1e3a8d0; 1 drivers +v0x1c78870_0 .net *"_s1", 0 0, L_0x1e3ab40; 1 drivers +S_0x1c78950 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c78b60 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e3ac50/d .functor AND 1, L_0x1e3ad10, L_0x1e3ae70, C4<1>, C4<1>; +L_0x1e3ac50 .delay 1 (30000,30000,30000) L_0x1e3ac50/d; +v0x1c78c20_0 .net *"_s0", 0 0, L_0x1e3ad10; 1 drivers +v0x1c78d00_0 .net *"_s1", 0 0, L_0x1e3ae70; 1 drivers +S_0x1c78de0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c76b40; + .timescale -9 -12; +P_0x1c78ff0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e3b1e0/d .functor AND 1, L_0x1e3b2f0, L_0x1e3b4e0, C4<1>, C4<1>; +L_0x1e3b1e0 .delay 1 (30000,30000,30000) L_0x1e3b1e0/d; +v0x1c790b0_0 .net *"_s0", 0 0, L_0x1e3b2f0; 1 drivers +v0x1c79190_0 .net *"_s1", 0 0, L_0x1e3b4e0; 1 drivers +S_0x1c79d50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c76920; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e3cf30/d .functor OR 1, L_0x1e3cff0, L_0x1e3d1a0, C4<0>, C4<0>; +L_0x1e3cf30 .delay 1 (30000,30000,30000) L_0x1e3cf30/d; +v0x1c7b8a0_0 .net *"_s10", 0 0, L_0x1e3cff0; 1 drivers +v0x1c7b980_0 .net *"_s12", 0 0, L_0x1e3d1a0; 1 drivers +v0x1c7ba60_0 .net "in", 7 0, L_0x1e3af60; alias, 1 drivers +v0x1c7bb30_0 .net "ors", 1 0, L_0x1e3cd50; 1 drivers +v0x1c7bbf0_0 .net "out", 0 0, L_0x1e3cf30; alias, 1 drivers +L_0x1e3c120 .part L_0x1e3af60, 0, 4; +L_0x1e3cd50 .concat8 [ 1 1 0 0], L_0x1e3be10, L_0x1e3ca40; +L_0x1e3ce90 .part L_0x1e3af60, 4, 4; +L_0x1e3cff0 .part L_0x1e3cd50, 0, 1; +L_0x1e3d1a0 .part L_0x1e3cd50, 1, 1; +S_0x1c79f10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c79d50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e3b5d0/d .functor OR 1, L_0x1e3b690, L_0x1e3b7f0, C4<0>, C4<0>; +L_0x1e3b5d0 .delay 1 (30000,30000,30000) L_0x1e3b5d0/d; +L_0x1e3ba20/d .functor OR 1, L_0x1e3bb30, L_0x1e3bc90, C4<0>, C4<0>; +L_0x1e3ba20 .delay 1 (30000,30000,30000) L_0x1e3ba20/d; +L_0x1e3be10/d .functor OR 1, L_0x1e3be80, L_0x1e3c030, C4<0>, C4<0>; +L_0x1e3be10 .delay 1 (30000,30000,30000) L_0x1e3be10/d; +v0x1c7a160_0 .net *"_s0", 0 0, L_0x1e3b5d0; 1 drivers +v0x1c7a260_0 .net *"_s10", 0 0, L_0x1e3bb30; 1 drivers +v0x1c7a340_0 .net *"_s12", 0 0, L_0x1e3bc90; 1 drivers +v0x1c7a400_0 .net *"_s14", 0 0, L_0x1e3be80; 1 drivers +v0x1c7a4e0_0 .net *"_s16", 0 0, L_0x1e3c030; 1 drivers +v0x1c7a610_0 .net *"_s3", 0 0, L_0x1e3b690; 1 drivers +v0x1c7a6f0_0 .net *"_s5", 0 0, L_0x1e3b7f0; 1 drivers +v0x1c7a7d0_0 .net *"_s6", 0 0, L_0x1e3ba20; 1 drivers +v0x1c7a8b0_0 .net "in", 3 0, L_0x1e3c120; 1 drivers +v0x1c7aa20_0 .net "ors", 1 0, L_0x1e3b930; 1 drivers +v0x1c7ab00_0 .net "out", 0 0, L_0x1e3be10; 1 drivers +L_0x1e3b690 .part L_0x1e3c120, 0, 1; +L_0x1e3b7f0 .part L_0x1e3c120, 1, 1; +L_0x1e3b930 .concat8 [ 1 1 0 0], L_0x1e3b5d0, L_0x1e3ba20; +L_0x1e3bb30 .part L_0x1e3c120, 2, 1; +L_0x1e3bc90 .part L_0x1e3c120, 3, 1; +L_0x1e3be80 .part L_0x1e3b930, 0, 1; +L_0x1e3c030 .part L_0x1e3b930, 1, 1; +S_0x1c7ac20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c79d50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e3c250/d .functor OR 1, L_0x1e3c2c0, L_0x1e3c420, C4<0>, C4<0>; +L_0x1e3c250 .delay 1 (30000,30000,30000) L_0x1e3c250/d; +L_0x1e3c650/d .functor OR 1, L_0x1e3c760, L_0x1e3c8c0, C4<0>, C4<0>; +L_0x1e3c650 .delay 1 (30000,30000,30000) L_0x1e3c650/d; +L_0x1e3ca40/d .functor OR 1, L_0x1e3cab0, L_0x1e3cc60, C4<0>, C4<0>; +L_0x1e3ca40 .delay 1 (30000,30000,30000) L_0x1e3ca40/d; +v0x1c7ade0_0 .net *"_s0", 0 0, L_0x1e3c250; 1 drivers +v0x1c7aee0_0 .net *"_s10", 0 0, L_0x1e3c760; 1 drivers +v0x1c7afc0_0 .net *"_s12", 0 0, L_0x1e3c8c0; 1 drivers +v0x1c7b080_0 .net *"_s14", 0 0, L_0x1e3cab0; 1 drivers +v0x1c7b160_0 .net *"_s16", 0 0, L_0x1e3cc60; 1 drivers +v0x1c7b290_0 .net *"_s3", 0 0, L_0x1e3c2c0; 1 drivers +v0x1c7b370_0 .net *"_s5", 0 0, L_0x1e3c420; 1 drivers +v0x1c7b450_0 .net *"_s6", 0 0, L_0x1e3c650; 1 drivers +v0x1c7b530_0 .net "in", 3 0, L_0x1e3ce90; 1 drivers +v0x1c7b6a0_0 .net "ors", 1 0, L_0x1e3c560; 1 drivers +v0x1c7b780_0 .net "out", 0 0, L_0x1e3ca40; 1 drivers +L_0x1e3c2c0 .part L_0x1e3ce90, 0, 1; +L_0x1e3c420 .part L_0x1e3ce90, 1, 1; +L_0x1e3c560 .concat8 [ 1 1 0 0], L_0x1e3c250, L_0x1e3c650; +L_0x1e3c760 .part L_0x1e3ce90, 2, 1; +L_0x1e3c8c0 .part L_0x1e3ce90, 3, 1; +L_0x1e3cab0 .part L_0x1e3c560, 0, 1; +L_0x1e3cc60 .part L_0x1e3c560, 1, 1; +S_0x1c7c090 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c751c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1ca14c0_0 .net "ands", 7 0, L_0x1e374c0; 1 drivers +v0x1ca15d0_0 .net "in", 7 0, L_0x1e35a00; alias, 1 drivers +v0x1ca1690_0 .net "out", 0 0, L_0x1e394c0; alias, 1 drivers +v0x1ca1760_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1c7c2e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c7c090; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1c7ea20_0 .net "A", 7 0, L_0x1e35a00; alias, 1 drivers +v0x1c7eb20_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1c7ebe0_0 .net *"_s0", 0 0, L_0x1e35d90; 1 drivers +v0x1c7eca0_0 .net *"_s12", 0 0, L_0x1e36750; 1 drivers +v0x1c7ed80_0 .net *"_s16", 0 0, L_0x1e36ab0; 1 drivers +v0x1c7eeb0_0 .net *"_s20", 0 0, L_0x1e36e80; 1 drivers +v0x1c7ef90_0 .net *"_s24", 0 0, L_0x1e371b0; 1 drivers +v0x1c7f070_0 .net *"_s28", 0 0, L_0x1e37140; 1 drivers +v0x1c7f150_0 .net *"_s4", 0 0, L_0x1e36130; 1 drivers +v0x1c7f2c0_0 .net *"_s8", 0 0, L_0x1e36440; 1 drivers +v0x1c7f3a0_0 .net "out", 7 0, L_0x1e374c0; alias, 1 drivers +L_0x1e35ea0 .part L_0x1e35a00, 0, 1; +L_0x1e36090 .part v0x1d6daa0_0, 0, 1; +L_0x1e361f0 .part L_0x1e35a00, 1, 1; +L_0x1e36350 .part v0x1d6daa0_0, 1, 1; +L_0x1e36500 .part L_0x1e35a00, 2, 1; +L_0x1e36660 .part v0x1d6daa0_0, 2, 1; +L_0x1e36810 .part L_0x1e35a00, 3, 1; +L_0x1e36970 .part v0x1d6daa0_0, 3, 1; +L_0x1e36b70 .part L_0x1e35a00, 4, 1; +L_0x1e36de0 .part v0x1d6daa0_0, 4, 1; +L_0x1e36ef0 .part L_0x1e35a00, 5, 1; +L_0x1e37050 .part v0x1d6daa0_0, 5, 1; +L_0x1e37270 .part L_0x1e35a00, 6, 1; +L_0x1e373d0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e374c0_0_0 .concat8 [ 1 1 1 1], L_0x1e35d90, L_0x1e36130, L_0x1e36440, L_0x1e36750; +LS_0x1e374c0_0_4 .concat8 [ 1 1 1 1], L_0x1e36ab0, L_0x1e36e80, L_0x1e371b0, L_0x1e37140; +L_0x1e374c0 .concat8 [ 4 4 0 0], LS_0x1e374c0_0_0, LS_0x1e374c0_0_4; +L_0x1e37880 .part L_0x1e35a00, 7, 1; +L_0x1e37a70 .part v0x1d6daa0_0, 7, 1; +S_0x1c7c520 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7c730 .param/l "i" 0 4 54, +C4<00>; +L_0x1e35d90/d .functor AND 1, L_0x1e35ea0, L_0x1e36090, C4<1>, C4<1>; +L_0x1e35d90 .delay 1 (30000,30000,30000) L_0x1e35d90/d; +v0x1c7c810_0 .net *"_s0", 0 0, L_0x1e35ea0; 1 drivers +v0x1c7c8f0_0 .net *"_s1", 0 0, L_0x1e36090; 1 drivers +S_0x1c7c9d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7cbe0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e36130/d .functor AND 1, L_0x1e361f0, L_0x1e36350, C4<1>, C4<1>; +L_0x1e36130 .delay 1 (30000,30000,30000) L_0x1e36130/d; +v0x1c7cca0_0 .net *"_s0", 0 0, L_0x1e361f0; 1 drivers +v0x1c7cd80_0 .net *"_s1", 0 0, L_0x1e36350; 1 drivers +S_0x1c7ce60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7d0a0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e36440/d .functor AND 1, L_0x1e36500, L_0x1e36660, C4<1>, C4<1>; +L_0x1e36440 .delay 1 (30000,30000,30000) L_0x1e36440/d; +v0x1c7d140_0 .net *"_s0", 0 0, L_0x1e36500; 1 drivers +v0x1c7d220_0 .net *"_s1", 0 0, L_0x1e36660; 1 drivers +S_0x1c7d300 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7d510 .param/l "i" 0 4 54, +C4<011>; +L_0x1e36750/d .functor AND 1, L_0x1e36810, L_0x1e36970, C4<1>, C4<1>; +L_0x1e36750 .delay 1 (30000,30000,30000) L_0x1e36750/d; +v0x1c7d5d0_0 .net *"_s0", 0 0, L_0x1e36810; 1 drivers +v0x1c7d6b0_0 .net *"_s1", 0 0, L_0x1e36970; 1 drivers +S_0x1c7d790 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7d9f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e36ab0/d .functor AND 1, L_0x1e36b70, L_0x1e36de0, C4<1>, C4<1>; +L_0x1e36ab0 .delay 1 (30000,30000,30000) L_0x1e36ab0/d; +v0x1c7dab0_0 .net *"_s0", 0 0, L_0x1e36b70; 1 drivers +v0x1c7db90_0 .net *"_s1", 0 0, L_0x1e36de0; 1 drivers +S_0x1c7dc70 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7de80 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e36e80/d .functor AND 1, L_0x1e36ef0, L_0x1e37050, C4<1>, C4<1>; +L_0x1e36e80 .delay 1 (30000,30000,30000) L_0x1e36e80/d; +v0x1c7df40_0 .net *"_s0", 0 0, L_0x1e36ef0; 1 drivers +v0x1c7e020_0 .net *"_s1", 0 0, L_0x1e37050; 1 drivers +S_0x1c7e100 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7e310 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e371b0/d .functor AND 1, L_0x1e37270, L_0x1e373d0, C4<1>, C4<1>; +L_0x1e371b0 .delay 1 (30000,30000,30000) L_0x1e371b0/d; +v0x1c7e3d0_0 .net *"_s0", 0 0, L_0x1e37270; 1 drivers +v0x1c7e4b0_0 .net *"_s1", 0 0, L_0x1e373d0; 1 drivers +S_0x1c7e590 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c7c2e0; + .timescale -9 -12; +P_0x1c7e7a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e37140/d .functor AND 1, L_0x1e37880, L_0x1e37a70, C4<1>, C4<1>; +L_0x1e37140 .delay 1 (30000,30000,30000) L_0x1e37140/d; +v0x1c7e860_0 .net *"_s0", 0 0, L_0x1e37880; 1 drivers +v0x1c7e940_0 .net *"_s1", 0 0, L_0x1e37a70; 1 drivers +S_0x1c7f500 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c7c090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e394c0/d .functor OR 1, L_0x1e39580, L_0x1e39730, C4<0>, C4<0>; +L_0x1e394c0 .delay 1 (30000,30000,30000) L_0x1e394c0/d; +v0x1ca1050_0 .net *"_s10", 0 0, L_0x1e39580; 1 drivers +v0x1ca1130_0 .net *"_s12", 0 0, L_0x1e39730; 1 drivers +v0x1ca1210_0 .net "in", 7 0, L_0x1e374c0; alias, 1 drivers +v0x1ca12e0_0 .net "ors", 1 0, L_0x1e392e0; 1 drivers +v0x1ca13a0_0 .net "out", 0 0, L_0x1e394c0; alias, 1 drivers +L_0x1e386b0 .part L_0x1e374c0, 0, 4; +L_0x1e392e0 .concat8 [ 1 1 0 0], L_0x1e383a0, L_0x1e38fd0; +L_0x1e39420 .part L_0x1e374c0, 4, 4; +L_0x1e39580 .part L_0x1e392e0, 0, 1; +L_0x1e39730 .part L_0x1e392e0, 1, 1; +S_0x1c7f6c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c7f500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e37b60/d .functor OR 1, L_0x1e37c20, L_0x1e37d80, C4<0>, C4<0>; +L_0x1e37b60 .delay 1 (30000,30000,30000) L_0x1e37b60/d; +L_0x1e37fb0/d .functor OR 1, L_0x1e380c0, L_0x1e38220, C4<0>, C4<0>; +L_0x1e37fb0 .delay 1 (30000,30000,30000) L_0x1e37fb0/d; +L_0x1e383a0/d .functor OR 1, L_0x1e38410, L_0x1e385c0, C4<0>, C4<0>; +L_0x1e383a0 .delay 1 (30000,30000,30000) L_0x1e383a0/d; +v0x1c7f910_0 .net *"_s0", 0 0, L_0x1e37b60; 1 drivers +v0x1c7fa10_0 .net *"_s10", 0 0, L_0x1e380c0; 1 drivers +v0x1c7faf0_0 .net *"_s12", 0 0, L_0x1e38220; 1 drivers +v0x1c7fbb0_0 .net *"_s14", 0 0, L_0x1e38410; 1 drivers +v0x1c9fc90_0 .net *"_s16", 0 0, L_0x1e385c0; 1 drivers +v0x1c9fdc0_0 .net *"_s3", 0 0, L_0x1e37c20; 1 drivers +v0x1c9fea0_0 .net *"_s5", 0 0, L_0x1e37d80; 1 drivers +v0x1c9ff80_0 .net *"_s6", 0 0, L_0x1e37fb0; 1 drivers +v0x1ca0060_0 .net "in", 3 0, L_0x1e386b0; 1 drivers +v0x1ca01d0_0 .net "ors", 1 0, L_0x1e37ec0; 1 drivers +v0x1ca02b0_0 .net "out", 0 0, L_0x1e383a0; 1 drivers +L_0x1e37c20 .part L_0x1e386b0, 0, 1; +L_0x1e37d80 .part L_0x1e386b0, 1, 1; +L_0x1e37ec0 .concat8 [ 1 1 0 0], L_0x1e37b60, L_0x1e37fb0; +L_0x1e380c0 .part L_0x1e386b0, 2, 1; +L_0x1e38220 .part L_0x1e386b0, 3, 1; +L_0x1e38410 .part L_0x1e37ec0, 0, 1; +L_0x1e385c0 .part L_0x1e37ec0, 1, 1; +S_0x1ca03d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c7f500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e387e0/d .functor OR 1, L_0x1e38850, L_0x1e389b0, C4<0>, C4<0>; +L_0x1e387e0 .delay 1 (30000,30000,30000) L_0x1e387e0/d; +L_0x1e38be0/d .functor OR 1, L_0x1e38cf0, L_0x1e38e50, C4<0>, C4<0>; +L_0x1e38be0 .delay 1 (30000,30000,30000) L_0x1e38be0/d; +L_0x1e38fd0/d .functor OR 1, L_0x1e39040, L_0x1e391f0, C4<0>, C4<0>; +L_0x1e38fd0 .delay 1 (30000,30000,30000) L_0x1e38fd0/d; +v0x1ca0590_0 .net *"_s0", 0 0, L_0x1e387e0; 1 drivers +v0x1ca0690_0 .net *"_s10", 0 0, L_0x1e38cf0; 1 drivers +v0x1ca0770_0 .net *"_s12", 0 0, L_0x1e38e50; 1 drivers +v0x1ca0830_0 .net *"_s14", 0 0, L_0x1e39040; 1 drivers +v0x1ca0910_0 .net *"_s16", 0 0, L_0x1e391f0; 1 drivers +v0x1ca0a40_0 .net *"_s3", 0 0, L_0x1e38850; 1 drivers +v0x1ca0b20_0 .net *"_s5", 0 0, L_0x1e389b0; 1 drivers +v0x1ca0c00_0 .net *"_s6", 0 0, L_0x1e38be0; 1 drivers +v0x1ca0ce0_0 .net "in", 3 0, L_0x1e39420; 1 drivers +v0x1ca0e50_0 .net "ors", 1 0, L_0x1e38af0; 1 drivers +v0x1ca0f30_0 .net "out", 0 0, L_0x1e38fd0; 1 drivers +L_0x1e38850 .part L_0x1e39420, 0, 1; +L_0x1e389b0 .part L_0x1e39420, 1, 1; +L_0x1e38af0 .concat8 [ 1 1 0 0], L_0x1e387e0, L_0x1e38be0; +L_0x1e38cf0 .part L_0x1e39420, 2, 1; +L_0x1e38e50 .part L_0x1e39420, 3, 1; +L_0x1e39040 .part L_0x1e38af0, 0, 1; +L_0x1e391f0 .part L_0x1e38af0, 1, 1; +S_0x1ca1840 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c751c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e34d70/d .functor XNOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; +L_0x1e34d70 .delay 1 (20000,20000,20000) L_0x1e34d70/d; +L_0x1e34fe0/d .functor AND 1, L_0x1e3d390, L_0x1e33c60, C4<1>, C4<1>; +L_0x1e34fe0 .delay 1 (30000,30000,30000) L_0x1e34fe0/d; +L_0x1e35050/d .functor AND 1, L_0x1e34d70, L_0x1e33870, C4<1>, C4<1>; +L_0x1e35050 .delay 1 (30000,30000,30000) L_0x1e35050/d; +L_0x1e351b0/d .functor OR 1, L_0x1e35050, L_0x1e34fe0, C4<0>, C4<0>; +L_0x1e351b0 .delay 1 (30000,30000,30000) L_0x1e351b0/d; +v0x1ca1af0_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers +v0x1ca1be0_0 .net "a_", 0 0, L_0x1e33b00; alias, 1 drivers +v0x1ca1ca0_0 .net "b", 0 0, L_0x1e3d4f0; alias, 1 drivers +v0x1ca1d90_0 .net "b_", 0 0, L_0x1e33c60; alias, 1 drivers +v0x1ca1e30_0 .net "carryin", 0 0, L_0x1e33870; alias, 1 drivers +v0x1ca1f70_0 .net "eq", 0 0, L_0x1e34d70; 1 drivers +v0x1ca2030_0 .net "lt", 0 0, L_0x1e34fe0; 1 drivers +v0x1ca20f0_0 .net "out", 0 0, L_0x1e351b0; 1 drivers +v0x1ca21b0_0 .net "w0", 0 0, L_0x1e35050; 1 drivers +S_0x1ca2400 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c751c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e34b50/d .functor OR 1, L_0x1e34650, L_0x1ca3660, C4<0>, C4<0>; +L_0x1e34b50 .delay 1 (30000,30000,30000) L_0x1e34b50/d; +v0x1ca31f0_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers +v0x1ca3340_0 .net "b", 0 0, L_0x1e33c60; alias, 1 drivers +v0x1ca3400_0 .net "c1", 0 0, L_0x1e34650; 1 drivers +v0x1ca34a0_0 .net "c2", 0 0, L_0x1ca3660; 1 drivers +v0x1ca3570_0 .net "carryin", 0 0, L_0x1e33870; alias, 1 drivers +v0x1ca36f0_0 .net "carryout", 0 0, L_0x1e34b50; 1 drivers +v0x1ca3790_0 .net "s1", 0 0, L_0x1e34590; 1 drivers +v0x1ca3830_0 .net "sum", 0 0, L_0x1e347b0; 1 drivers +S_0x1ca2650 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ca2400; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e34590/d .functor XOR 1, L_0x1e3d390, L_0x1e33c60, C4<0>, C4<0>; +L_0x1e34590 .delay 1 (30000,30000,30000) L_0x1e34590/d; +L_0x1e34650/d .functor AND 1, L_0x1e3d390, L_0x1e33c60, C4<1>, C4<1>; +L_0x1e34650 .delay 1 (30000,30000,30000) L_0x1e34650/d; +v0x1ca28b0_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers +v0x1ca2970_0 .net "b", 0 0, L_0x1e33c60; alias, 1 drivers +v0x1ca2a30_0 .net "carryout", 0 0, L_0x1e34650; alias, 1 drivers +v0x1ca2ad0_0 .net "sum", 0 0, L_0x1e34590; alias, 1 drivers +S_0x1ca2c00 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ca2400; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e347b0/d .functor XOR 1, L_0x1e34590, L_0x1e33870, C4<0>, C4<0>; +L_0x1e347b0 .delay 1 (30000,30000,30000) L_0x1e347b0/d; +L_0x1ca3660/d .functor AND 1, L_0x1e34590, L_0x1e33870, C4<1>, C4<1>; +L_0x1ca3660 .delay 1 (30000,30000,30000) L_0x1ca3660/d; +v0x1ca2e60_0 .net "a", 0 0, L_0x1e34590; alias, 1 drivers +v0x1ca2f30_0 .net "b", 0 0, L_0x1e33870; alias, 1 drivers +v0x1ca2fd0_0 .net "carryout", 0 0, L_0x1ca3660; alias, 1 drivers +v0x1ca30a0_0 .net "sum", 0 0, L_0x1e347b0; alias, 1 drivers +S_0x1ca4c50 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c74ef0; + .timescale -9 -12; +L_0x7f72592db698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db6e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e3d430/d .functor OR 1, L_0x7f72592db698, L_0x7f72592db6e0, C4<0>, C4<0>; +L_0x1e3d430 .delay 1 (30000,30000,30000) L_0x1e3d430/d; +v0x1ca4e40_0 .net/2u *"_s0", 0 0, L_0x7f72592db698; 1 drivers +v0x1ca4f20_0 .net/2u *"_s2", 0 0, L_0x7f72592db6e0; 1 drivers +S_0x1ca5000 .scope generate, "alu_slices[21]" "alu_slices[21]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1ca5210 .param/l "i" 0 3 37, +C4<010101>; +S_0x1ca52d0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ca5000; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e3d790/d .functor NOT 1, L_0x1da93a0, C4<0>, C4<0>, C4<0>; +L_0x1e3d790 .delay 1 (10000,10000,10000) L_0x1e3d790/d; +L_0x1e3d850/d .functor NOT 1, L_0x1da9500, C4<0>, C4<0>, C4<0>; +L_0x1e3d850 .delay 1 (10000,10000,10000) L_0x1e3d850/d; +L_0x1e3e850/d .functor XOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; +L_0x1e3e850 .delay 1 (30000,30000,30000) L_0x1e3e850/d; +L_0x7f72592db728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e3ef00/d .functor OR 1, L_0x7f72592db728, L_0x7f72592db770, C4<0>, C4<0>; +L_0x1e3ef00 .delay 1 (30000,30000,30000) L_0x1e3ef00/d; +L_0x1e3f100/d .functor AND 1, L_0x1da93a0, L_0x1da9500, C4<1>, C4<1>; +L_0x1e3f100 .delay 1 (30000,30000,30000) L_0x1e3f100/d; +L_0x1e3f1c0/d .functor NAND 1, L_0x1da93a0, L_0x1da9500, C4<1>, C4<1>; +L_0x1e3f1c0 .delay 1 (20000,20000,20000) L_0x1e3f1c0/d; +L_0x1e3f320/d .functor XOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; +L_0x1e3f320 .delay 1 (20000,20000,20000) L_0x1e3f320/d; +L_0x1e3f7d0/d .functor OR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; +L_0x1e3f7d0 .delay 1 (30000,30000,30000) L_0x1e3f7d0/d; +L_0x1da92a0/d .functor NOT 1, L_0x1e43140, C4<0>, C4<0>, C4<0>; +L_0x1da92a0 .delay 1 (10000,10000,10000) L_0x1da92a0/d; +v0x1cb3a10_0 .net "A", 0 0, L_0x1da93a0; 1 drivers +v0x1cb3ad0_0 .net "A_", 0 0, L_0x1e3d790; 1 drivers +v0x1cb3b90_0 .net "B", 0 0, L_0x1da9500; 1 drivers +v0x1cb3c60_0 .net "B_", 0 0, L_0x1e3d850; 1 drivers +v0x1cb3d00_0 .net *"_s12", 0 0, L_0x1e3ef00; 1 drivers +v0x1cb3df0_0 .net/2s *"_s14", 0 0, L_0x7f72592db728; 1 drivers +v0x1cb3eb0_0 .net/2s *"_s16", 0 0, L_0x7f72592db770; 1 drivers +v0x1cb3f90_0 .net *"_s18", 0 0, L_0x1e3f100; 1 drivers +v0x1cb4070_0 .net *"_s20", 0 0, L_0x1e3f1c0; 1 drivers +v0x1cb41e0_0 .net *"_s22", 0 0, L_0x1e3f320; 1 drivers +v0x1cb42c0_0 .net *"_s24", 0 0, L_0x1e3f7d0; 1 drivers +o0x7f7259326258 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1cb43a0_0 name=_s30 +o0x7f7259326288 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1cb4480_0 name=_s32 +v0x1cb4560_0 .net *"_s8", 0 0, L_0x1e3e850; 1 drivers +v0x1cb4640_0 .net "carryin", 0 0, L_0x1da95a0; 1 drivers +v0x1cb46e0_0 .net "carryout", 0 0, L_0x1da8f40; 1 drivers +v0x1cb4780_0 .net "carryouts", 7 0, L_0x1ec0f00; 1 drivers +v0x1cb4930_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cb49d0_0 .net "result", 0 0, L_0x1e43140; 1 drivers +v0x1cb4ac0_0 .net "results", 7 0, L_0x1e3f5a0; 1 drivers +v0x1cb4bd0_0 .net "zero", 0 0, L_0x1da92a0; 1 drivers +LS_0x1e3f5a0_0_0 .concat8 [ 1 1 1 1], L_0x1e3dd70, L_0x1e3e3a0, L_0x1e3e850, L_0x1e3ef00; +LS_0x1e3f5a0_0_4 .concat8 [ 1 1 1 1], L_0x1e3f100, L_0x1e3f1c0, L_0x1e3f320, L_0x1e3f7d0; +L_0x1e3f5a0 .concat8 [ 4 4 0 0], LS_0x1e3f5a0_0_0, LS_0x1e3f5a0_0_4; +LS_0x1ec0f00_0_0 .concat [ 1 1 1 1], L_0x1e3e020, L_0x1e3e6f0, o0x7f7259326258, L_0x1e3ed50; +LS_0x1ec0f00_0_4 .concat [ 4 0 0 0], o0x7f7259326288; +L_0x1ec0f00 .concat [ 4 4 0 0], LS_0x1ec0f00_0_0, LS_0x1ec0f00_0_4; +S_0x1ca5550 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1ca52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e3e020/d .functor OR 1, L_0x1e3db00, L_0x1e3dec0, C4<0>, C4<0>; +L_0x1e3e020 .delay 1 (30000,30000,30000) L_0x1e3e020/d; +v0x1ca6380_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers +v0x1ca6440_0 .net "b", 0 0, L_0x1da9500; alias, 1 drivers +v0x1ca6510_0 .net "c1", 0 0, L_0x1e3db00; 1 drivers +v0x1ca6610_0 .net "c2", 0 0, L_0x1e3dec0; 1 drivers +v0x1ca66e0_0 .net "carryin", 0 0, L_0x1da95a0; alias, 1 drivers +v0x1ca67d0_0 .net "carryout", 0 0, L_0x1e3e020; 1 drivers +v0x1ca6870_0 .net "s1", 0 0, L_0x1e3da40; 1 drivers +v0x1ca6960_0 .net "sum", 0 0, L_0x1e3dd70; 1 drivers +S_0x1ca57c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ca5550; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e3da40/d .functor XOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; +L_0x1e3da40 .delay 1 (30000,30000,30000) L_0x1e3da40/d; +L_0x1e3db00/d .functor AND 1, L_0x1da93a0, L_0x1da9500, C4<1>, C4<1>; +L_0x1e3db00 .delay 1 (30000,30000,30000) L_0x1e3db00/d; +v0x1ca5a20_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers +v0x1ca5b00_0 .net "b", 0 0, L_0x1da9500; alias, 1 drivers +v0x1ca5bc0_0 .net "carryout", 0 0, L_0x1e3db00; alias, 1 drivers +v0x1ca5c60_0 .net "sum", 0 0, L_0x1e3da40; alias, 1 drivers +S_0x1ca5da0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ca5550; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e3dd70/d .functor XOR 1, L_0x1e3da40, L_0x1da95a0, C4<0>, C4<0>; +L_0x1e3dd70 .delay 1 (30000,30000,30000) L_0x1e3dd70/d; +L_0x1e3dec0/d .functor AND 1, L_0x1e3da40, L_0x1da95a0, C4<1>, C4<1>; +L_0x1e3dec0 .delay 1 (30000,30000,30000) L_0x1e3dec0/d; +v0x1ca6000_0 .net "a", 0 0, L_0x1e3da40; alias, 1 drivers +v0x1ca60a0_0 .net "b", 0 0, L_0x1da95a0; alias, 1 drivers +v0x1ca6140_0 .net "carryout", 0 0, L_0x1e3dec0; alias, 1 drivers +v0x1ca6210_0 .net "sum", 0 0, L_0x1e3dd70; alias, 1 drivers +S_0x1ca6a30 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1ca52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cabe20_0 .net "ands", 7 0, L_0x1e44b80; 1 drivers +v0x1cabf30_0 .net "in", 7 0, L_0x1ec0f00; alias, 1 drivers +v0x1cabff0_0 .net "out", 0 0, L_0x1da8f40; alias, 1 drivers +v0x1cac0c0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1ca6c50 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ca6a30; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1ca9380_0 .net "A", 7 0, L_0x1ec0f00; alias, 1 drivers +v0x1ca9480_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ca9540_0 .net *"_s0", 0 0, L_0x1e434a0; 1 drivers +v0x1ca9600_0 .net *"_s12", 0 0, L_0x1e43e10; 1 drivers +v0x1ca96e0_0 .net *"_s16", 0 0, L_0x1e44170; 1 drivers +v0x1ca9810_0 .net *"_s20", 0 0, L_0x1e44480; 1 drivers +v0x1ca98f0_0 .net *"_s24", 0 0, L_0x1e44870; 1 drivers +v0x1ca99d0_0 .net *"_s28", 0 0, L_0x1e44800; 1 drivers +v0x1ca9ab0_0 .net *"_s4", 0 0, L_0x1e437b0; 1 drivers +v0x1ca9c20_0 .net *"_s8", 0 0, L_0x1e43b00; 1 drivers +v0x1ca9d00_0 .net "out", 7 0, L_0x1e44b80; alias, 1 drivers +L_0x1e43560 .part L_0x1ec0f00, 0, 1; +L_0x1e436c0 .part v0x1d6daa0_0, 0, 1; +L_0x1e43870 .part L_0x1ec0f00, 1, 1; +L_0x1e43a60 .part v0x1d6daa0_0, 1, 1; +L_0x1e43bc0 .part L_0x1ec0f00, 2, 1; +L_0x1e43d20 .part v0x1d6daa0_0, 2, 1; +L_0x1e43ed0 .part L_0x1ec0f00, 3, 1; +L_0x1e44030 .part v0x1d6daa0_0, 3, 1; +L_0x1e44230 .part L_0x1ec0f00, 4, 1; +L_0x1e44390 .part v0x1d6daa0_0, 4, 1; +L_0x1e444f0 .part L_0x1ec0f00, 5, 1; +L_0x1e44760 .part v0x1d6daa0_0, 5, 1; +L_0x1e44930 .part L_0x1ec0f00, 6, 1; +L_0x1e44a90 .part v0x1d6daa0_0, 6, 1; +LS_0x1e44b80_0_0 .concat8 [ 1 1 1 1], L_0x1e434a0, L_0x1e437b0, L_0x1e43b00, L_0x1e43e10; +LS_0x1e44b80_0_4 .concat8 [ 1 1 1 1], L_0x1e44170, L_0x1e44480, L_0x1e44870, L_0x1e44800; +L_0x1e44b80 .concat8 [ 4 4 0 0], LS_0x1e44b80_0_0, LS_0x1e44b80_0_4; +L_0x1e44f40 .part L_0x1ec0f00, 7, 1; +L_0x1e45130 .part v0x1d6daa0_0, 7, 1; +S_0x1ca6eb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca70c0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e434a0/d .functor AND 1, L_0x1e43560, L_0x1e436c0, C4<1>, C4<1>; +L_0x1e434a0 .delay 1 (30000,30000,30000) L_0x1e434a0/d; +v0x1ca71a0_0 .net *"_s0", 0 0, L_0x1e43560; 1 drivers +v0x1ca7280_0 .net *"_s1", 0 0, L_0x1e436c0; 1 drivers +S_0x1ca7360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca7570 .param/l "i" 0 4 54, +C4<01>; +L_0x1e437b0/d .functor AND 1, L_0x1e43870, L_0x1e43a60, C4<1>, C4<1>; +L_0x1e437b0 .delay 1 (30000,30000,30000) L_0x1e437b0/d; +v0x1ca7630_0 .net *"_s0", 0 0, L_0x1e43870; 1 drivers +v0x1ca7710_0 .net *"_s1", 0 0, L_0x1e43a60; 1 drivers +S_0x1ca77f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca7a00 .param/l "i" 0 4 54, +C4<010>; +L_0x1e43b00/d .functor AND 1, L_0x1e43bc0, L_0x1e43d20, C4<1>, C4<1>; +L_0x1e43b00 .delay 1 (30000,30000,30000) L_0x1e43b00/d; +v0x1ca7aa0_0 .net *"_s0", 0 0, L_0x1e43bc0; 1 drivers +v0x1ca7b80_0 .net *"_s1", 0 0, L_0x1e43d20; 1 drivers +S_0x1ca7c60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca7e70 .param/l "i" 0 4 54, +C4<011>; +L_0x1e43e10/d .functor AND 1, L_0x1e43ed0, L_0x1e44030, C4<1>, C4<1>; +L_0x1e43e10 .delay 1 (30000,30000,30000) L_0x1e43e10/d; +v0x1ca7f30_0 .net *"_s0", 0 0, L_0x1e43ed0; 1 drivers +v0x1ca8010_0 .net *"_s1", 0 0, L_0x1e44030; 1 drivers +S_0x1ca80f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca8350 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e44170/d .functor AND 1, L_0x1e44230, L_0x1e44390, C4<1>, C4<1>; +L_0x1e44170 .delay 1 (30000,30000,30000) L_0x1e44170/d; +v0x1ca8410_0 .net *"_s0", 0 0, L_0x1e44230; 1 drivers +v0x1ca84f0_0 .net *"_s1", 0 0, L_0x1e44390; 1 drivers +S_0x1ca85d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca87e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e44480/d .functor AND 1, L_0x1e444f0, L_0x1e44760, C4<1>, C4<1>; +L_0x1e44480 .delay 1 (30000,30000,30000) L_0x1e44480/d; +v0x1ca88a0_0 .net *"_s0", 0 0, L_0x1e444f0; 1 drivers +v0x1ca8980_0 .net *"_s1", 0 0, L_0x1e44760; 1 drivers +S_0x1ca8a60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca8c70 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e44870/d .functor AND 1, L_0x1e44930, L_0x1e44a90, C4<1>, C4<1>; +L_0x1e44870 .delay 1 (30000,30000,30000) L_0x1e44870/d; +v0x1ca8d30_0 .net *"_s0", 0 0, L_0x1e44930; 1 drivers +v0x1ca8e10_0 .net *"_s1", 0 0, L_0x1e44a90; 1 drivers +S_0x1ca8ef0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ca6c50; + .timescale -9 -12; +P_0x1ca9100 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e44800/d .functor AND 1, L_0x1e44f40, L_0x1e45130, C4<1>, C4<1>; +L_0x1e44800 .delay 1 (30000,30000,30000) L_0x1e44800/d; +v0x1ca91c0_0 .net *"_s0", 0 0, L_0x1e44f40; 1 drivers +v0x1ca92a0_0 .net *"_s1", 0 0, L_0x1e45130; 1 drivers +S_0x1ca9e60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ca6a30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1da8f40/d .functor OR 1, L_0x1da9000, L_0x1da91b0, C4<0>, C4<0>; +L_0x1da8f40 .delay 1 (30000,30000,30000) L_0x1da8f40/d; +v0x1cab9b0_0 .net *"_s10", 0 0, L_0x1da9000; 1 drivers +v0x1caba90_0 .net *"_s12", 0 0, L_0x1da91b0; 1 drivers +v0x1cabb70_0 .net "in", 7 0, L_0x1e44b80; alias, 1 drivers +v0x1cabc40_0 .net "ors", 1 0, L_0x1da8d60; 1 drivers +v0x1cabd00_0 .net "out", 0 0, L_0x1da8f40; alias, 1 drivers +L_0x1da8130 .part L_0x1e44b80, 0, 4; +L_0x1da8d60 .concat8 [ 1 1 0 0], L_0x1da7e20, L_0x1da8a50; +L_0x1da8ea0 .part L_0x1e44b80, 4, 4; +L_0x1da9000 .part L_0x1da8d60, 0, 1; +L_0x1da91b0 .part L_0x1da8d60, 1, 1; +S_0x1caa020 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1ca9e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e410c0/d .functor OR 1, L_0x1da76a0, L_0x1da7800, C4<0>, C4<0>; +L_0x1e410c0 .delay 1 (30000,30000,30000) L_0x1e410c0/d; +L_0x1da7a30/d .functor OR 1, L_0x1da7b40, L_0x1da7ca0, C4<0>, C4<0>; +L_0x1da7a30 .delay 1 (30000,30000,30000) L_0x1da7a30/d; +L_0x1da7e20/d .functor OR 1, L_0x1da7e90, L_0x1da8040, C4<0>, C4<0>; +L_0x1da7e20 .delay 1 (30000,30000,30000) L_0x1da7e20/d; +v0x1caa270_0 .net *"_s0", 0 0, L_0x1e410c0; 1 drivers +v0x1caa370_0 .net *"_s10", 0 0, L_0x1da7b40; 1 drivers +v0x1caa450_0 .net *"_s12", 0 0, L_0x1da7ca0; 1 drivers +v0x1caa510_0 .net *"_s14", 0 0, L_0x1da7e90; 1 drivers +v0x1caa5f0_0 .net *"_s16", 0 0, L_0x1da8040; 1 drivers +v0x1caa720_0 .net *"_s3", 0 0, L_0x1da76a0; 1 drivers +v0x1caa800_0 .net *"_s5", 0 0, L_0x1da7800; 1 drivers +v0x1caa8e0_0 .net *"_s6", 0 0, L_0x1da7a30; 1 drivers +v0x1caa9c0_0 .net "in", 3 0, L_0x1da8130; 1 drivers +v0x1caab30_0 .net "ors", 1 0, L_0x1da7940; 1 drivers +v0x1caac10_0 .net "out", 0 0, L_0x1da7e20; 1 drivers +L_0x1da76a0 .part L_0x1da8130, 0, 1; +L_0x1da7800 .part L_0x1da8130, 1, 1; +L_0x1da7940 .concat8 [ 1 1 0 0], L_0x1e410c0, L_0x1da7a30; +L_0x1da7b40 .part L_0x1da8130, 2, 1; +L_0x1da7ca0 .part L_0x1da8130, 3, 1; +L_0x1da7e90 .part L_0x1da7940, 0, 1; +L_0x1da8040 .part L_0x1da7940, 1, 1; +S_0x1caad30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1ca9e60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1da8260/d .functor OR 1, L_0x1da82d0, L_0x1da8430, C4<0>, C4<0>; +L_0x1da8260 .delay 1 (30000,30000,30000) L_0x1da8260/d; +L_0x1da8660/d .functor OR 1, L_0x1da8770, L_0x1da88d0, C4<0>, C4<0>; +L_0x1da8660 .delay 1 (30000,30000,30000) L_0x1da8660/d; +L_0x1da8a50/d .functor OR 1, L_0x1da8ac0, L_0x1da8c70, C4<0>, C4<0>; +L_0x1da8a50 .delay 1 (30000,30000,30000) L_0x1da8a50/d; +v0x1caaef0_0 .net *"_s0", 0 0, L_0x1da8260; 1 drivers +v0x1caaff0_0 .net *"_s10", 0 0, L_0x1da8770; 1 drivers +v0x1cab0d0_0 .net *"_s12", 0 0, L_0x1da88d0; 1 drivers +v0x1cab190_0 .net *"_s14", 0 0, L_0x1da8ac0; 1 drivers +v0x1cab270_0 .net *"_s16", 0 0, L_0x1da8c70; 1 drivers +v0x1cab3a0_0 .net *"_s3", 0 0, L_0x1da82d0; 1 drivers +v0x1cab480_0 .net *"_s5", 0 0, L_0x1da8430; 1 drivers +v0x1cab560_0 .net *"_s6", 0 0, L_0x1da8660; 1 drivers +v0x1cab640_0 .net "in", 3 0, L_0x1da8ea0; 1 drivers +v0x1cab7b0_0 .net "ors", 1 0, L_0x1da8570; 1 drivers +v0x1cab890_0 .net "out", 0 0, L_0x1da8a50; 1 drivers +L_0x1da82d0 .part L_0x1da8ea0, 0, 1; +L_0x1da8430 .part L_0x1da8ea0, 1, 1; +L_0x1da8570 .concat8 [ 1 1 0 0], L_0x1da8260, L_0x1da8660; +L_0x1da8770 .part L_0x1da8ea0, 2, 1; +L_0x1da88d0 .part L_0x1da8ea0, 3, 1; +L_0x1da8ac0 .part L_0x1da8570, 0, 1; +L_0x1da8c70 .part L_0x1da8570, 1, 1; +S_0x1cac1a0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1ca52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cb15d0_0 .net "ands", 7 0, L_0x1e41140; 1 drivers +v0x1cb16e0_0 .net "in", 7 0, L_0x1e3f5a0; alias, 1 drivers +v0x1cb17a0_0 .net "out", 0 0, L_0x1e43140; alias, 1 drivers +v0x1cb1870_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cac3f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cac1a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1caeb30_0 .net "A", 7 0, L_0x1e3f5a0; alias, 1 drivers +v0x1caec30_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1caecf0_0 .net *"_s0", 0 0, L_0x1e3f930; 1 drivers +v0x1caedb0_0 .net *"_s12", 0 0, L_0x1e402f0; 1 drivers +v0x1caee90_0 .net *"_s16", 0 0, L_0x1e40650; 1 drivers +v0x1caefc0_0 .net *"_s20", 0 0, L_0x1e40a80; 1 drivers +v0x1caf0a0_0 .net *"_s24", 0 0, L_0x1e40db0; 1 drivers +v0x1caf180_0 .net *"_s28", 0 0, L_0x1e40d40; 1 drivers +v0x1caf260_0 .net *"_s4", 0 0, L_0x1e3fcd0; 1 drivers +v0x1caf3d0_0 .net *"_s8", 0 0, L_0x1e3ffe0; 1 drivers +v0x1caf4b0_0 .net "out", 7 0, L_0x1e41140; alias, 1 drivers +L_0x1e3fa40 .part L_0x1e3f5a0, 0, 1; +L_0x1e3fc30 .part v0x1d6daa0_0, 0, 1; +L_0x1e3fd90 .part L_0x1e3f5a0, 1, 1; +L_0x1e3fef0 .part v0x1d6daa0_0, 1, 1; +L_0x1e400a0 .part L_0x1e3f5a0, 2, 1; +L_0x1e40200 .part v0x1d6daa0_0, 2, 1; +L_0x1e403b0 .part L_0x1e3f5a0, 3, 1; +L_0x1e40510 .part v0x1d6daa0_0, 3, 1; +L_0x1e40710 .part L_0x1e3f5a0, 4, 1; +L_0x1e40980 .part v0x1d6daa0_0, 4, 1; +L_0x1e40af0 .part L_0x1e3f5a0, 5, 1; +L_0x1e40c50 .part v0x1d6daa0_0, 5, 1; +L_0x1e40e70 .part L_0x1e3f5a0, 6, 1; +L_0x1e40fd0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e41140_0_0 .concat8 [ 1 1 1 1], L_0x1e3f930, L_0x1e3fcd0, L_0x1e3ffe0, L_0x1e402f0; +LS_0x1e41140_0_4 .concat8 [ 1 1 1 1], L_0x1e40650, L_0x1e40a80, L_0x1e40db0, L_0x1e40d40; +L_0x1e41140 .concat8 [ 4 4 0 0], LS_0x1e41140_0_0, LS_0x1e41140_0_4; +L_0x1e41500 .part L_0x1e3f5a0, 7, 1; +L_0x1e416f0 .part v0x1d6daa0_0, 7, 1; +S_0x1cac630 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cac840 .param/l "i" 0 4 54, +C4<00>; +L_0x1e3f930/d .functor AND 1, L_0x1e3fa40, L_0x1e3fc30, C4<1>, C4<1>; +L_0x1e3f930 .delay 1 (30000,30000,30000) L_0x1e3f930/d; +v0x1cac920_0 .net *"_s0", 0 0, L_0x1e3fa40; 1 drivers +v0x1caca00_0 .net *"_s1", 0 0, L_0x1e3fc30; 1 drivers +S_0x1cacae0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1caccf0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e3fcd0/d .functor AND 1, L_0x1e3fd90, L_0x1e3fef0, C4<1>, C4<1>; +L_0x1e3fcd0 .delay 1 (30000,30000,30000) L_0x1e3fcd0/d; +v0x1cacdb0_0 .net *"_s0", 0 0, L_0x1e3fd90; 1 drivers +v0x1cace90_0 .net *"_s1", 0 0, L_0x1e3fef0; 1 drivers +S_0x1cacf70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cad1b0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e3ffe0/d .functor AND 1, L_0x1e400a0, L_0x1e40200, C4<1>, C4<1>; +L_0x1e3ffe0 .delay 1 (30000,30000,30000) L_0x1e3ffe0/d; +v0x1cad250_0 .net *"_s0", 0 0, L_0x1e400a0; 1 drivers +v0x1cad330_0 .net *"_s1", 0 0, L_0x1e40200; 1 drivers +S_0x1cad410 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cad620 .param/l "i" 0 4 54, +C4<011>; +L_0x1e402f0/d .functor AND 1, L_0x1e403b0, L_0x1e40510, C4<1>, C4<1>; +L_0x1e402f0 .delay 1 (30000,30000,30000) L_0x1e402f0/d; +v0x1cad6e0_0 .net *"_s0", 0 0, L_0x1e403b0; 1 drivers +v0x1cad7c0_0 .net *"_s1", 0 0, L_0x1e40510; 1 drivers +S_0x1cad8a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cadb00 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e40650/d .functor AND 1, L_0x1e40710, L_0x1e40980, C4<1>, C4<1>; +L_0x1e40650 .delay 1 (30000,30000,30000) L_0x1e40650/d; +v0x1cadbc0_0 .net *"_s0", 0 0, L_0x1e40710; 1 drivers +v0x1cadca0_0 .net *"_s1", 0 0, L_0x1e40980; 1 drivers +S_0x1cadd80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cadf90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e40a80/d .functor AND 1, L_0x1e40af0, L_0x1e40c50, C4<1>, C4<1>; +L_0x1e40a80 .delay 1 (30000,30000,30000) L_0x1e40a80/d; +v0x1cae050_0 .net *"_s0", 0 0, L_0x1e40af0; 1 drivers +v0x1cae130_0 .net *"_s1", 0 0, L_0x1e40c50; 1 drivers +S_0x1cae210 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cae420 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e40db0/d .functor AND 1, L_0x1e40e70, L_0x1e40fd0, C4<1>, C4<1>; +L_0x1e40db0 .delay 1 (30000,30000,30000) L_0x1e40db0/d; +v0x1cae4e0_0 .net *"_s0", 0 0, L_0x1e40e70; 1 drivers +v0x1cae5c0_0 .net *"_s1", 0 0, L_0x1e40fd0; 1 drivers +S_0x1cae6a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cac3f0; + .timescale -9 -12; +P_0x1cae8b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e40d40/d .functor AND 1, L_0x1e41500, L_0x1e416f0, C4<1>, C4<1>; +L_0x1e40d40 .delay 1 (30000,30000,30000) L_0x1e40d40/d; +v0x1cae970_0 .net *"_s0", 0 0, L_0x1e41500; 1 drivers +v0x1caea50_0 .net *"_s1", 0 0, L_0x1e416f0; 1 drivers +S_0x1caf610 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cac1a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e43140/d .functor OR 1, L_0x1e43200, L_0x1e433b0, C4<0>, C4<0>; +L_0x1e43140 .delay 1 (30000,30000,30000) L_0x1e43140/d; +v0x1cb1160_0 .net *"_s10", 0 0, L_0x1e43200; 1 drivers +v0x1cb1240_0 .net *"_s12", 0 0, L_0x1e433b0; 1 drivers +v0x1cb1320_0 .net "in", 7 0, L_0x1e41140; alias, 1 drivers +v0x1cb13f0_0 .net "ors", 1 0, L_0x1e42f60; 1 drivers +v0x1cb14b0_0 .net "out", 0 0, L_0x1e43140; alias, 1 drivers +L_0x1e42330 .part L_0x1e41140, 0, 4; +L_0x1e42f60 .concat8 [ 1 1 0 0], L_0x1e42020, L_0x1e42c50; +L_0x1e430a0 .part L_0x1e41140, 4, 4; +L_0x1e43200 .part L_0x1e42f60, 0, 1; +L_0x1e433b0 .part L_0x1e42f60, 1, 1; +S_0x1caf7d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1caf610; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e417e0/d .functor OR 1, L_0x1e418a0, L_0x1e41a00, C4<0>, C4<0>; +L_0x1e417e0 .delay 1 (30000,30000,30000) L_0x1e417e0/d; +L_0x1e41c30/d .functor OR 1, L_0x1e41d40, L_0x1e41ea0, C4<0>, C4<0>; +L_0x1e41c30 .delay 1 (30000,30000,30000) L_0x1e41c30/d; +L_0x1e42020/d .functor OR 1, L_0x1e42090, L_0x1e42240, C4<0>, C4<0>; +L_0x1e42020 .delay 1 (30000,30000,30000) L_0x1e42020/d; +v0x1cafa20_0 .net *"_s0", 0 0, L_0x1e417e0; 1 drivers +v0x1cafb20_0 .net *"_s10", 0 0, L_0x1e41d40; 1 drivers +v0x1cafc00_0 .net *"_s12", 0 0, L_0x1e41ea0; 1 drivers +v0x1cafcc0_0 .net *"_s14", 0 0, L_0x1e42090; 1 drivers +v0x1cafda0_0 .net *"_s16", 0 0, L_0x1e42240; 1 drivers +v0x1cafed0_0 .net *"_s3", 0 0, L_0x1e418a0; 1 drivers +v0x1caffb0_0 .net *"_s5", 0 0, L_0x1e41a00; 1 drivers +v0x1cb0090_0 .net *"_s6", 0 0, L_0x1e41c30; 1 drivers +v0x1cb0170_0 .net "in", 3 0, L_0x1e42330; 1 drivers +v0x1cb02e0_0 .net "ors", 1 0, L_0x1e41b40; 1 drivers +v0x1cb03c0_0 .net "out", 0 0, L_0x1e42020; 1 drivers +L_0x1e418a0 .part L_0x1e42330, 0, 1; +L_0x1e41a00 .part L_0x1e42330, 1, 1; +L_0x1e41b40 .concat8 [ 1 1 0 0], L_0x1e417e0, L_0x1e41c30; +L_0x1e41d40 .part L_0x1e42330, 2, 1; +L_0x1e41ea0 .part L_0x1e42330, 3, 1; +L_0x1e42090 .part L_0x1e41b40, 0, 1; +L_0x1e42240 .part L_0x1e41b40, 1, 1; +S_0x1cb04e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1caf610; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e42460/d .functor OR 1, L_0x1e424d0, L_0x1e42630, C4<0>, C4<0>; +L_0x1e42460 .delay 1 (30000,30000,30000) L_0x1e42460/d; +L_0x1e42860/d .functor OR 1, L_0x1e42970, L_0x1e42ad0, C4<0>, C4<0>; +L_0x1e42860 .delay 1 (30000,30000,30000) L_0x1e42860/d; +L_0x1e42c50/d .functor OR 1, L_0x1e42cc0, L_0x1e42e70, C4<0>, C4<0>; +L_0x1e42c50 .delay 1 (30000,30000,30000) L_0x1e42c50/d; +v0x1cb06a0_0 .net *"_s0", 0 0, L_0x1e42460; 1 drivers +v0x1cb07a0_0 .net *"_s10", 0 0, L_0x1e42970; 1 drivers +v0x1cb0880_0 .net *"_s12", 0 0, L_0x1e42ad0; 1 drivers +v0x1cb0940_0 .net *"_s14", 0 0, L_0x1e42cc0; 1 drivers +v0x1cb0a20_0 .net *"_s16", 0 0, L_0x1e42e70; 1 drivers +v0x1cb0b50_0 .net *"_s3", 0 0, L_0x1e424d0; 1 drivers +v0x1cb0c30_0 .net *"_s5", 0 0, L_0x1e42630; 1 drivers +v0x1cb0d10_0 .net *"_s6", 0 0, L_0x1e42860; 1 drivers +v0x1cb0df0_0 .net "in", 3 0, L_0x1e430a0; 1 drivers +v0x1cb0f60_0 .net "ors", 1 0, L_0x1e42770; 1 drivers +v0x1cb1040_0 .net "out", 0 0, L_0x1e42c50; 1 drivers +L_0x1e424d0 .part L_0x1e430a0, 0, 1; +L_0x1e42630 .part L_0x1e430a0, 1, 1; +L_0x1e42770 .concat8 [ 1 1 0 0], L_0x1e42460, L_0x1e42860; +L_0x1e42970 .part L_0x1e430a0, 2, 1; +L_0x1e42ad0 .part L_0x1e430a0, 3, 1; +L_0x1e42cc0 .part L_0x1e42770, 0, 1; +L_0x1e42e70 .part L_0x1e42770, 1, 1; +S_0x1cb1950 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ca52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e3e910/d .functor XNOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; +L_0x1e3e910 .delay 1 (20000,20000,20000) L_0x1e3e910/d; +L_0x1e3eb80/d .functor AND 1, L_0x1da93a0, L_0x1e3d850, C4<1>, C4<1>; +L_0x1e3eb80 .delay 1 (30000,30000,30000) L_0x1e3eb80/d; +L_0x1e3ebf0/d .functor AND 1, L_0x1e3e910, L_0x1da95a0, C4<1>, C4<1>; +L_0x1e3ebf0 .delay 1 (30000,30000,30000) L_0x1e3ebf0/d; +L_0x1e3ed50/d .functor OR 1, L_0x1e3ebf0, L_0x1e3eb80, C4<0>, C4<0>; +L_0x1e3ed50 .delay 1 (30000,30000,30000) L_0x1e3ed50/d; +v0x1cb1c00_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers +v0x1cb1cf0_0 .net "a_", 0 0, L_0x1e3d790; alias, 1 drivers +v0x1cb1db0_0 .net "b", 0 0, L_0x1da9500; alias, 1 drivers +v0x1cb1ea0_0 .net "b_", 0 0, L_0x1e3d850; alias, 1 drivers +v0x1cb1f40_0 .net "carryin", 0 0, L_0x1da95a0; alias, 1 drivers +v0x1cb2080_0 .net "eq", 0 0, L_0x1e3e910; 1 drivers +v0x1cb2120_0 .net "lt", 0 0, L_0x1e3eb80; 1 drivers +v0x1cb21e0_0 .net "out", 0 0, L_0x1e3ed50; 1 drivers +v0x1cb22a0_0 .net "w0", 0 0, L_0x1e3ebf0; 1 drivers +S_0x1cb24f0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1ca52d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e3e6f0/d .functor OR 1, L_0x1e3e240, L_0x1cb3780, C4<0>, C4<0>; +L_0x1e3e6f0 .delay 1 (30000,30000,30000) L_0x1e3e6f0/d; +v0x1cb3310_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers +v0x1cb3460_0 .net "b", 0 0, L_0x1e3d850; alias, 1 drivers +v0x1cb3520_0 .net "c1", 0 0, L_0x1e3e240; 1 drivers +v0x1cb35c0_0 .net "c2", 0 0, L_0x1cb3780; 1 drivers +v0x1cb3690_0 .net "carryin", 0 0, L_0x1da95a0; alias, 1 drivers +v0x1cb3810_0 .net "carryout", 0 0, L_0x1e3e6f0; 1 drivers +v0x1cb38b0_0 .net "s1", 0 0, L_0x1e3e180; 1 drivers +v0x1cb3950_0 .net "sum", 0 0, L_0x1e3e3a0; 1 drivers +S_0x1cb2740 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cb24f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e3e180/d .functor XOR 1, L_0x1da93a0, L_0x1e3d850, C4<0>, C4<0>; +L_0x1e3e180 .delay 1 (30000,30000,30000) L_0x1e3e180/d; +L_0x1e3e240/d .functor AND 1, L_0x1da93a0, L_0x1e3d850, C4<1>, C4<1>; +L_0x1e3e240 .delay 1 (30000,30000,30000) L_0x1e3e240/d; +v0x1cb29a0_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers +v0x1cb2a60_0 .net "b", 0 0, L_0x1e3d850; alias, 1 drivers +v0x1cb2b20_0 .net "carryout", 0 0, L_0x1e3e240; alias, 1 drivers +v0x1cb2bf0_0 .net "sum", 0 0, L_0x1e3e180; alias, 1 drivers +S_0x1cb2d20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cb24f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e3e3a0/d .functor XOR 1, L_0x1e3e180, L_0x1da95a0, C4<0>, C4<0>; +L_0x1e3e3a0 .delay 1 (30000,30000,30000) L_0x1e3e3a0/d; +L_0x1cb3780/d .functor AND 1, L_0x1e3e180, L_0x1da95a0, C4<1>, C4<1>; +L_0x1cb3780 .delay 1 (30000,30000,30000) L_0x1cb3780/d; +v0x1cb2f80_0 .net "a", 0 0, L_0x1e3e180; alias, 1 drivers +v0x1cb3050_0 .net "b", 0 0, L_0x1da95a0; alias, 1 drivers +v0x1cb30f0_0 .net "carryout", 0 0, L_0x1cb3780; alias, 1 drivers +v0x1cb31c0_0 .net "sum", 0 0, L_0x1e3e3a0; alias, 1 drivers +S_0x1cb4d70 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1ca5000; + .timescale -9 -12; +L_0x7f72592db7b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1da9440/d .functor OR 1, L_0x7f72592db7b8, L_0x7f72592db800, C4<0>, C4<0>; +L_0x1da9440 .delay 1 (30000,30000,30000) L_0x1da9440/d; +v0x1cb4f60_0 .net/2u *"_s0", 0 0, L_0x7f72592db7b8; 1 drivers +v0x1cb5040_0 .net/2u *"_s2", 0 0, L_0x7f72592db800; 1 drivers +S_0x1cb5120 .scope generate, "alu_slices[22]" "alu_slices[22]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1cb5330 .param/l "i" 0 3 37, +C4<010110>; +S_0x1cb53f0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cb5120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e3d590/d .functor NOT 1, L_0x1e52ca0, C4<0>, C4<0>, C4<0>; +L_0x1e3d590 .delay 1 (10000,10000,10000) L_0x1e3d590/d; +L_0x1e49450/d .functor NOT 1, L_0x1e52e00, C4<0>, C4<0>, C4<0>; +L_0x1e49450 .delay 1 (10000,10000,10000) L_0x1e49450/d; +L_0x1e4a450/d .functor XOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; +L_0x1e4a450 .delay 1 (30000,30000,30000) L_0x1e4a450/d; +L_0x7f72592db848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e4ab00/d .functor OR 1, L_0x7f72592db848, L_0x7f72592db890, C4<0>, C4<0>; +L_0x1e4ab00 .delay 1 (30000,30000,30000) L_0x1e4ab00/d; +L_0x1e4ad00/d .functor AND 1, L_0x1e52ca0, L_0x1e52e00, C4<1>, C4<1>; +L_0x1e4ad00 .delay 1 (30000,30000,30000) L_0x1e4ad00/d; +L_0x1e4adc0/d .functor NAND 1, L_0x1e52ca0, L_0x1e52e00, C4<1>, C4<1>; +L_0x1e4adc0 .delay 1 (20000,20000,20000) L_0x1e4adc0/d; +L_0x1e4af20/d .functor XOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; +L_0x1e4af20 .delay 1 (20000,20000,20000) L_0x1e4af20/d; +L_0x1e4b3d0/d .functor OR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; +L_0x1e4b3d0 .delay 1 (30000,30000,30000) L_0x1e4b3d0/d; +L_0x1e52ba0/d .functor NOT 1, L_0x1e4ed40, C4<0>, C4<0>, C4<0>; +L_0x1e52ba0 .delay 1 (10000,10000,10000) L_0x1e52ba0/d; +v0x1cc3b20_0 .net "A", 0 0, L_0x1e52ca0; 1 drivers +v0x1cc3be0_0 .net "A_", 0 0, L_0x1e3d590; 1 drivers +v0x1cc3ca0_0 .net "B", 0 0, L_0x1e52e00; 1 drivers +v0x1cc3d70_0 .net "B_", 0 0, L_0x1e49450; 1 drivers +v0x1cc3e10_0 .net *"_s12", 0 0, L_0x1e4ab00; 1 drivers +v0x1cc3f00_0 .net/2s *"_s14", 0 0, L_0x7f72592db848; 1 drivers +v0x1cc3fc0_0 .net/2s *"_s16", 0 0, L_0x7f72592db890; 1 drivers +v0x1cc40a0_0 .net *"_s18", 0 0, L_0x1e4ad00; 1 drivers +v0x1cc4180_0 .net *"_s20", 0 0, L_0x1e4adc0; 1 drivers +v0x1cc42f0_0 .net *"_s22", 0 0, L_0x1e4af20; 1 drivers +v0x1cc43d0_0 .net *"_s24", 0 0, L_0x1e4b3d0; 1 drivers +o0x7f72593287a8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1cc44b0_0 name=_s30 +o0x7f72593287d8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1cc4590_0 name=_s32 +v0x1cc4670_0 .net *"_s8", 0 0, L_0x1e4a450; 1 drivers +v0x1cc4750_0 .net "carryin", 0 0, L_0x1e49230; 1 drivers +v0x1cc47f0_0 .net "carryout", 0 0, L_0x1e52840; 1 drivers +v0x1cc4890_0 .net "carryouts", 7 0, L_0x1ec10d0; 1 drivers +v0x1cc4a40_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cc4ae0_0 .net "result", 0 0, L_0x1e4ed40; 1 drivers +v0x1cc4bd0_0 .net "results", 7 0, L_0x1e4b1a0; 1 drivers +v0x1cc4ce0_0 .net "zero", 0 0, L_0x1e52ba0; 1 drivers +LS_0x1e4b1a0_0_0 .concat8 [ 1 1 1 1], L_0x1e49970, L_0x1e49fa0, L_0x1e4a450, L_0x1e4ab00; +LS_0x1e4b1a0_0_4 .concat8 [ 1 1 1 1], L_0x1e4ad00, L_0x1e4adc0, L_0x1e4af20, L_0x1e4b3d0; +L_0x1e4b1a0 .concat8 [ 4 4 0 0], LS_0x1e4b1a0_0_0, LS_0x1e4b1a0_0_4; +LS_0x1ec10d0_0_0 .concat [ 1 1 1 1], L_0x1e49c20, L_0x1e4a2f0, o0x7f72593287a8, L_0x1e4a950; +LS_0x1ec10d0_0_4 .concat [ 4 0 0 0], o0x7f72593287d8; +L_0x1ec10d0 .concat [ 4 4 0 0], LS_0x1ec10d0_0_0, LS_0x1ec10d0_0_4; +S_0x1cb5670 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cb53f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e49c20/d .functor OR 1, L_0x1e49700, L_0x1e49ac0, C4<0>, C4<0>; +L_0x1e49c20 .delay 1 (30000,30000,30000) L_0x1e49c20/d; +v0x1cb64a0_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers +v0x1cb6560_0 .net "b", 0 0, L_0x1e52e00; alias, 1 drivers +v0x1cb6630_0 .net "c1", 0 0, L_0x1e49700; 1 drivers +v0x1cb6730_0 .net "c2", 0 0, L_0x1e49ac0; 1 drivers +v0x1cb6800_0 .net "carryin", 0 0, L_0x1e49230; alias, 1 drivers +v0x1cb68f0_0 .net "carryout", 0 0, L_0x1e49c20; 1 drivers +v0x1cb6990_0 .net "s1", 0 0, L_0x1e49640; 1 drivers +v0x1cb6a80_0 .net "sum", 0 0, L_0x1e49970; 1 drivers +S_0x1cb58e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cb5670; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e49640/d .functor XOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; +L_0x1e49640 .delay 1 (30000,30000,30000) L_0x1e49640/d; +L_0x1e49700/d .functor AND 1, L_0x1e52ca0, L_0x1e52e00, C4<1>, C4<1>; +L_0x1e49700 .delay 1 (30000,30000,30000) L_0x1e49700/d; +v0x1cb5b40_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers +v0x1cb5c20_0 .net "b", 0 0, L_0x1e52e00; alias, 1 drivers +v0x1cb5ce0_0 .net "carryout", 0 0, L_0x1e49700; alias, 1 drivers +v0x1cb5d80_0 .net "sum", 0 0, L_0x1e49640; alias, 1 drivers +S_0x1cb5ec0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cb5670; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e49970/d .functor XOR 1, L_0x1e49640, L_0x1e49230, C4<0>, C4<0>; +L_0x1e49970 .delay 1 (30000,30000,30000) L_0x1e49970/d; +L_0x1e49ac0/d .functor AND 1, L_0x1e49640, L_0x1e49230, C4<1>, C4<1>; +L_0x1e49ac0 .delay 1 (30000,30000,30000) L_0x1e49ac0/d; +v0x1cb6120_0 .net "a", 0 0, L_0x1e49640; alias, 1 drivers +v0x1cb61c0_0 .net "b", 0 0, L_0x1e49230; alias, 1 drivers +v0x1cb6260_0 .net "carryout", 0 0, L_0x1e49ac0; alias, 1 drivers +v0x1cb6330_0 .net "sum", 0 0, L_0x1e49970; alias, 1 drivers +S_0x1cb6b50 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cb53f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cbbf40_0 .net "ands", 7 0, L_0x1e50840; 1 drivers +v0x1cbc050_0 .net "in", 7 0, L_0x1ec10d0; alias, 1 drivers +v0x1cbc110_0 .net "out", 0 0, L_0x1e52840; alias, 1 drivers +v0x1cbc1e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cb6d70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cb6b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cb94a0_0 .net "A", 7 0, L_0x1ec10d0; alias, 1 drivers +v0x1cb95a0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cb9660_0 .net *"_s0", 0 0, L_0x1e4f0a0; 1 drivers +v0x1cb9720_0 .net *"_s12", 0 0, L_0x1e4fa10; 1 drivers +v0x1cb9800_0 .net *"_s16", 0 0, L_0x1e4fdd0; 1 drivers +v0x1cb9930_0 .net *"_s20", 0 0, L_0x1e50110; 1 drivers +v0x1cb9a10_0 .net *"_s24", 0 0, L_0x1e50530; 1 drivers +v0x1cb9af0_0 .net *"_s28", 0 0, L_0x1e504c0; 1 drivers +v0x1cb9bd0_0 .net *"_s4", 0 0, L_0x1e4f3b0; 1 drivers +v0x1cb9d40_0 .net *"_s8", 0 0, L_0x1e4f700; 1 drivers +v0x1cb9e20_0 .net "out", 7 0, L_0x1e50840; alias, 1 drivers +L_0x1e4f160 .part L_0x1ec10d0, 0, 1; +L_0x1e4f2c0 .part v0x1d6daa0_0, 0, 1; +L_0x1e4f470 .part L_0x1ec10d0, 1, 1; +L_0x1e4f660 .part v0x1d6daa0_0, 1, 1; +L_0x1e4f7c0 .part L_0x1ec10d0, 2, 1; +L_0x1e4f920 .part v0x1d6daa0_0, 2, 1; +L_0x1e4fb30 .part L_0x1ec10d0, 3, 1; +L_0x1e4fc90 .part v0x1d6daa0_0, 3, 1; +L_0x1e4fec0 .part L_0x1ec10d0, 4, 1; +L_0x1e50020 .part v0x1d6daa0_0, 4, 1; +L_0x1e501b0 .part L_0x1ec10d0, 5, 1; +L_0x1e50420 .part v0x1d6daa0_0, 5, 1; +L_0x1e505f0 .part L_0x1ec10d0, 6, 1; +L_0x1e50750 .part v0x1d6daa0_0, 6, 1; +LS_0x1e50840_0_0 .concat8 [ 1 1 1 1], L_0x1e4f0a0, L_0x1e4f3b0, L_0x1e4f700, L_0x1e4fa10; +LS_0x1e50840_0_4 .concat8 [ 1 1 1 1], L_0x1e4fdd0, L_0x1e50110, L_0x1e50530, L_0x1e504c0; +L_0x1e50840 .concat8 [ 4 4 0 0], LS_0x1e50840_0_0, LS_0x1e50840_0_4; +L_0x1e50c00 .part L_0x1ec10d0, 7, 1; +L_0x1e50df0 .part v0x1d6daa0_0, 7, 1; +S_0x1cb6fd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb71e0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e4f0a0/d .functor AND 1, L_0x1e4f160, L_0x1e4f2c0, C4<1>, C4<1>; +L_0x1e4f0a0 .delay 1 (30000,30000,30000) L_0x1e4f0a0/d; +v0x1cb72c0_0 .net *"_s0", 0 0, L_0x1e4f160; 1 drivers +v0x1cb73a0_0 .net *"_s1", 0 0, L_0x1e4f2c0; 1 drivers +S_0x1cb7480 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb7690 .param/l "i" 0 4 54, +C4<01>; +L_0x1e4f3b0/d .functor AND 1, L_0x1e4f470, L_0x1e4f660, C4<1>, C4<1>; +L_0x1e4f3b0 .delay 1 (30000,30000,30000) L_0x1e4f3b0/d; +v0x1cb7750_0 .net *"_s0", 0 0, L_0x1e4f470; 1 drivers +v0x1cb7830_0 .net *"_s1", 0 0, L_0x1e4f660; 1 drivers +S_0x1cb7910 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb7b20 .param/l "i" 0 4 54, +C4<010>; +L_0x1e4f700/d .functor AND 1, L_0x1e4f7c0, L_0x1e4f920, C4<1>, C4<1>; +L_0x1e4f700 .delay 1 (30000,30000,30000) L_0x1e4f700/d; +v0x1cb7bc0_0 .net *"_s0", 0 0, L_0x1e4f7c0; 1 drivers +v0x1cb7ca0_0 .net *"_s1", 0 0, L_0x1e4f920; 1 drivers +S_0x1cb7d80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb7f90 .param/l "i" 0 4 54, +C4<011>; +L_0x1e4fa10/d .functor AND 1, L_0x1e4fb30, L_0x1e4fc90, C4<1>, C4<1>; +L_0x1e4fa10 .delay 1 (30000,30000,30000) L_0x1e4fa10/d; +v0x1cb8050_0 .net *"_s0", 0 0, L_0x1e4fb30; 1 drivers +v0x1cb8130_0 .net *"_s1", 0 0, L_0x1e4fc90; 1 drivers +S_0x1cb8210 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb8470 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e4fdd0/d .functor AND 1, L_0x1e4fec0, L_0x1e50020, C4<1>, C4<1>; +L_0x1e4fdd0 .delay 1 (30000,30000,30000) L_0x1e4fdd0/d; +v0x1cb8530_0 .net *"_s0", 0 0, L_0x1e4fec0; 1 drivers +v0x1cb8610_0 .net *"_s1", 0 0, L_0x1e50020; 1 drivers +S_0x1cb86f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb8900 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e50110/d .functor AND 1, L_0x1e501b0, L_0x1e50420, C4<1>, C4<1>; +L_0x1e50110 .delay 1 (30000,30000,30000) L_0x1e50110/d; +v0x1cb89c0_0 .net *"_s0", 0 0, L_0x1e501b0; 1 drivers +v0x1cb8aa0_0 .net *"_s1", 0 0, L_0x1e50420; 1 drivers +S_0x1cb8b80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb8d90 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e50530/d .functor AND 1, L_0x1e505f0, L_0x1e50750, C4<1>, C4<1>; +L_0x1e50530 .delay 1 (30000,30000,30000) L_0x1e50530/d; +v0x1cb8e50_0 .net *"_s0", 0 0, L_0x1e505f0; 1 drivers +v0x1cb8f30_0 .net *"_s1", 0 0, L_0x1e50750; 1 drivers +S_0x1cb9010 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cb6d70; + .timescale -9 -12; +P_0x1cb9220 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e504c0/d .functor AND 1, L_0x1e50c00, L_0x1e50df0, C4<1>, C4<1>; +L_0x1e504c0 .delay 1 (30000,30000,30000) L_0x1e504c0/d; +v0x1cb92e0_0 .net *"_s0", 0 0, L_0x1e50c00; 1 drivers +v0x1cb93c0_0 .net *"_s1", 0 0, L_0x1e50df0; 1 drivers +S_0x1cb9f80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cb6b50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e52840/d .functor OR 1, L_0x1e52900, L_0x1e52ab0, C4<0>, C4<0>; +L_0x1e52840 .delay 1 (30000,30000,30000) L_0x1e52840/d; +v0x1cbbad0_0 .net *"_s10", 0 0, L_0x1e52900; 1 drivers +v0x1cbbbb0_0 .net *"_s12", 0 0, L_0x1e52ab0; 1 drivers +v0x1cbbc90_0 .net "in", 7 0, L_0x1e50840; alias, 1 drivers +v0x1cbbd60_0 .net "ors", 1 0, L_0x1e52660; 1 drivers +v0x1cbbe20_0 .net "out", 0 0, L_0x1e52840; alias, 1 drivers +L_0x1e51a30 .part L_0x1e50840, 0, 4; +L_0x1e52660 .concat8 [ 1 1 0 0], L_0x1e51720, L_0x1e52350; +L_0x1e527a0 .part L_0x1e50840, 4, 4; +L_0x1e52900 .part L_0x1e52660, 0, 1; +L_0x1e52ab0 .part L_0x1e52660, 1, 1; +S_0x1cba140 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cb9f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e50ee0/d .functor OR 1, L_0x1e50fa0, L_0x1e51100, C4<0>, C4<0>; +L_0x1e50ee0 .delay 1 (30000,30000,30000) L_0x1e50ee0/d; +L_0x1e51330/d .functor OR 1, L_0x1e51440, L_0x1e515a0, C4<0>, C4<0>; +L_0x1e51330 .delay 1 (30000,30000,30000) L_0x1e51330/d; +L_0x1e51720/d .functor OR 1, L_0x1e51790, L_0x1e51940, C4<0>, C4<0>; +L_0x1e51720 .delay 1 (30000,30000,30000) L_0x1e51720/d; +v0x1cba390_0 .net *"_s0", 0 0, L_0x1e50ee0; 1 drivers +v0x1cba490_0 .net *"_s10", 0 0, L_0x1e51440; 1 drivers +v0x1cba570_0 .net *"_s12", 0 0, L_0x1e515a0; 1 drivers +v0x1cba630_0 .net *"_s14", 0 0, L_0x1e51790; 1 drivers +v0x1cba710_0 .net *"_s16", 0 0, L_0x1e51940; 1 drivers +v0x1cba840_0 .net *"_s3", 0 0, L_0x1e50fa0; 1 drivers +v0x1cba920_0 .net *"_s5", 0 0, L_0x1e51100; 1 drivers +v0x1cbaa00_0 .net *"_s6", 0 0, L_0x1e51330; 1 drivers +v0x1cbaae0_0 .net "in", 3 0, L_0x1e51a30; 1 drivers +v0x1cbac50_0 .net "ors", 1 0, L_0x1e51240; 1 drivers +v0x1cbad30_0 .net "out", 0 0, L_0x1e51720; 1 drivers +L_0x1e50fa0 .part L_0x1e51a30, 0, 1; +L_0x1e51100 .part L_0x1e51a30, 1, 1; +L_0x1e51240 .concat8 [ 1 1 0 0], L_0x1e50ee0, L_0x1e51330; +L_0x1e51440 .part L_0x1e51a30, 2, 1; +L_0x1e515a0 .part L_0x1e51a30, 3, 1; +L_0x1e51790 .part L_0x1e51240, 0, 1; +L_0x1e51940 .part L_0x1e51240, 1, 1; +S_0x1cbae50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cb9f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e51b60/d .functor OR 1, L_0x1e51bd0, L_0x1e51d30, C4<0>, C4<0>; +L_0x1e51b60 .delay 1 (30000,30000,30000) L_0x1e51b60/d; +L_0x1e51f60/d .functor OR 1, L_0x1e52070, L_0x1e521d0, C4<0>, C4<0>; +L_0x1e51f60 .delay 1 (30000,30000,30000) L_0x1e51f60/d; +L_0x1e52350/d .functor OR 1, L_0x1e523c0, L_0x1e52570, C4<0>, C4<0>; +L_0x1e52350 .delay 1 (30000,30000,30000) L_0x1e52350/d; +v0x1cbb010_0 .net *"_s0", 0 0, L_0x1e51b60; 1 drivers +v0x1cbb110_0 .net *"_s10", 0 0, L_0x1e52070; 1 drivers +v0x1cbb1f0_0 .net *"_s12", 0 0, L_0x1e521d0; 1 drivers +v0x1cbb2b0_0 .net *"_s14", 0 0, L_0x1e523c0; 1 drivers +v0x1cbb390_0 .net *"_s16", 0 0, L_0x1e52570; 1 drivers +v0x1cbb4c0_0 .net *"_s3", 0 0, L_0x1e51bd0; 1 drivers +v0x1cbb5a0_0 .net *"_s5", 0 0, L_0x1e51d30; 1 drivers +v0x1cbb680_0 .net *"_s6", 0 0, L_0x1e51f60; 1 drivers +v0x1cbb760_0 .net "in", 3 0, L_0x1e527a0; 1 drivers +v0x1cbb8d0_0 .net "ors", 1 0, L_0x1e51e70; 1 drivers +v0x1cbb9b0_0 .net "out", 0 0, L_0x1e52350; 1 drivers +L_0x1e51bd0 .part L_0x1e527a0, 0, 1; +L_0x1e51d30 .part L_0x1e527a0, 1, 1; +L_0x1e51e70 .concat8 [ 1 1 0 0], L_0x1e51b60, L_0x1e51f60; +L_0x1e52070 .part L_0x1e527a0, 2, 1; +L_0x1e521d0 .part L_0x1e527a0, 3, 1; +L_0x1e523c0 .part L_0x1e51e70, 0, 1; +L_0x1e52570 .part L_0x1e51e70, 1, 1; +S_0x1cbc2c0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cb53f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cc16f0_0 .net "ands", 7 0, L_0x1e4cd40; 1 drivers +v0x1cc1800_0 .net "in", 7 0, L_0x1e4b1a0; alias, 1 drivers +v0x1cc18c0_0 .net "out", 0 0, L_0x1e4ed40; alias, 1 drivers +v0x1cc1990_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cbc510 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cbc2c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cbec50_0 .net "A", 7 0, L_0x1e4b1a0; alias, 1 drivers +v0x1cbed50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cbee10_0 .net *"_s0", 0 0, L_0x1e4b530; 1 drivers +v0x1cbeed0_0 .net *"_s12", 0 0, L_0x1e4bef0; 1 drivers +v0x1cbefb0_0 .net *"_s16", 0 0, L_0x1e4c250; 1 drivers +v0x1cbf0e0_0 .net *"_s20", 0 0, L_0x1e4c680; 1 drivers +v0x1cbf1c0_0 .net *"_s24", 0 0, L_0x1e4c9b0; 1 drivers +v0x1cbf2a0_0 .net *"_s28", 0 0, L_0x1e4c940; 1 drivers +v0x1cbf380_0 .net *"_s4", 0 0, L_0x1e4b8d0; 1 drivers +v0x1cbf4f0_0 .net *"_s8", 0 0, L_0x1e4bbe0; 1 drivers +v0x1cbf5d0_0 .net "out", 7 0, L_0x1e4cd40; alias, 1 drivers +L_0x1e4b640 .part L_0x1e4b1a0, 0, 1; +L_0x1e4b830 .part v0x1d6daa0_0, 0, 1; +L_0x1e4b990 .part L_0x1e4b1a0, 1, 1; +L_0x1e4baf0 .part v0x1d6daa0_0, 1, 1; +L_0x1e4bca0 .part L_0x1e4b1a0, 2, 1; +L_0x1e4be00 .part v0x1d6daa0_0, 2, 1; +L_0x1e4bfb0 .part L_0x1e4b1a0, 3, 1; +L_0x1e4c110 .part v0x1d6daa0_0, 3, 1; +L_0x1e4c310 .part L_0x1e4b1a0, 4, 1; +L_0x1e4c580 .part v0x1d6daa0_0, 4, 1; +L_0x1e4c6f0 .part L_0x1e4b1a0, 5, 1; +L_0x1e4c850 .part v0x1d6daa0_0, 5, 1; +L_0x1e4ca70 .part L_0x1e4b1a0, 6, 1; +L_0x1e4cbd0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e4cd40_0_0 .concat8 [ 1 1 1 1], L_0x1e4b530, L_0x1e4b8d0, L_0x1e4bbe0, L_0x1e4bef0; +LS_0x1e4cd40_0_4 .concat8 [ 1 1 1 1], L_0x1e4c250, L_0x1e4c680, L_0x1e4c9b0, L_0x1e4c940; +L_0x1e4cd40 .concat8 [ 4 4 0 0], LS_0x1e4cd40_0_0, LS_0x1e4cd40_0_4; +L_0x1e4d100 .part L_0x1e4b1a0, 7, 1; +L_0x1e4d2f0 .part v0x1d6daa0_0, 7, 1; +S_0x1cbc750 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbc960 .param/l "i" 0 4 54, +C4<00>; +L_0x1e4b530/d .functor AND 1, L_0x1e4b640, L_0x1e4b830, C4<1>, C4<1>; +L_0x1e4b530 .delay 1 (30000,30000,30000) L_0x1e4b530/d; +v0x1cbca40_0 .net *"_s0", 0 0, L_0x1e4b640; 1 drivers +v0x1cbcb20_0 .net *"_s1", 0 0, L_0x1e4b830; 1 drivers +S_0x1cbcc00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbce10 .param/l "i" 0 4 54, +C4<01>; +L_0x1e4b8d0/d .functor AND 1, L_0x1e4b990, L_0x1e4baf0, C4<1>, C4<1>; +L_0x1e4b8d0 .delay 1 (30000,30000,30000) L_0x1e4b8d0/d; +v0x1cbced0_0 .net *"_s0", 0 0, L_0x1e4b990; 1 drivers +v0x1cbcfb0_0 .net *"_s1", 0 0, L_0x1e4baf0; 1 drivers +S_0x1cbd090 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbd2d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e4bbe0/d .functor AND 1, L_0x1e4bca0, L_0x1e4be00, C4<1>, C4<1>; +L_0x1e4bbe0 .delay 1 (30000,30000,30000) L_0x1e4bbe0/d; +v0x1cbd370_0 .net *"_s0", 0 0, L_0x1e4bca0; 1 drivers +v0x1cbd450_0 .net *"_s1", 0 0, L_0x1e4be00; 1 drivers +S_0x1cbd530 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbd740 .param/l "i" 0 4 54, +C4<011>; +L_0x1e4bef0/d .functor AND 1, L_0x1e4bfb0, L_0x1e4c110, C4<1>, C4<1>; +L_0x1e4bef0 .delay 1 (30000,30000,30000) L_0x1e4bef0/d; +v0x1cbd800_0 .net *"_s0", 0 0, L_0x1e4bfb0; 1 drivers +v0x1cbd8e0_0 .net *"_s1", 0 0, L_0x1e4c110; 1 drivers +S_0x1cbd9c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbdc20 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e4c250/d .functor AND 1, L_0x1e4c310, L_0x1e4c580, C4<1>, C4<1>; +L_0x1e4c250 .delay 1 (30000,30000,30000) L_0x1e4c250/d; +v0x1cbdce0_0 .net *"_s0", 0 0, L_0x1e4c310; 1 drivers +v0x1cbddc0_0 .net *"_s1", 0 0, L_0x1e4c580; 1 drivers +S_0x1cbdea0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbe0b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e4c680/d .functor AND 1, L_0x1e4c6f0, L_0x1e4c850, C4<1>, C4<1>; +L_0x1e4c680 .delay 1 (30000,30000,30000) L_0x1e4c680/d; +v0x1cbe170_0 .net *"_s0", 0 0, L_0x1e4c6f0; 1 drivers +v0x1cbe250_0 .net *"_s1", 0 0, L_0x1e4c850; 1 drivers +S_0x1cbe330 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbe540 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e4c9b0/d .functor AND 1, L_0x1e4ca70, L_0x1e4cbd0, C4<1>, C4<1>; +L_0x1e4c9b0 .delay 1 (30000,30000,30000) L_0x1e4c9b0/d; +v0x1cbe600_0 .net *"_s0", 0 0, L_0x1e4ca70; 1 drivers +v0x1cbe6e0_0 .net *"_s1", 0 0, L_0x1e4cbd0; 1 drivers +S_0x1cbe7c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cbc510; + .timescale -9 -12; +P_0x1cbe9d0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e4c940/d .functor AND 1, L_0x1e4d100, L_0x1e4d2f0, C4<1>, C4<1>; +L_0x1e4c940 .delay 1 (30000,30000,30000) L_0x1e4c940/d; +v0x1cbea90_0 .net *"_s0", 0 0, L_0x1e4d100; 1 drivers +v0x1cbeb70_0 .net *"_s1", 0 0, L_0x1e4d2f0; 1 drivers +S_0x1cbf730 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cbc2c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e4ed40/d .functor OR 1, L_0x1e4ee00, L_0x1e4efb0, C4<0>, C4<0>; +L_0x1e4ed40 .delay 1 (30000,30000,30000) L_0x1e4ed40/d; +v0x1cc1280_0 .net *"_s10", 0 0, L_0x1e4ee00; 1 drivers +v0x1cc1360_0 .net *"_s12", 0 0, L_0x1e4efb0; 1 drivers +v0x1cc1440_0 .net "in", 7 0, L_0x1e4cd40; alias, 1 drivers +v0x1cc1510_0 .net "ors", 1 0, L_0x1e4eb60; 1 drivers +v0x1cc15d0_0 .net "out", 0 0, L_0x1e4ed40; alias, 1 drivers +L_0x1e4df30 .part L_0x1e4cd40, 0, 4; +L_0x1e4eb60 .concat8 [ 1 1 0 0], L_0x1e4dc20, L_0x1e4e850; +L_0x1e4eca0 .part L_0x1e4cd40, 4, 4; +L_0x1e4ee00 .part L_0x1e4eb60, 0, 1; +L_0x1e4efb0 .part L_0x1e4eb60, 1, 1; +S_0x1cbf8f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cbf730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e4d3e0/d .functor OR 1, L_0x1e4d4a0, L_0x1e4d600, C4<0>, C4<0>; +L_0x1e4d3e0 .delay 1 (30000,30000,30000) L_0x1e4d3e0/d; +L_0x1e4d830/d .functor OR 1, L_0x1e4d940, L_0x1e4daa0, C4<0>, C4<0>; +L_0x1e4d830 .delay 1 (30000,30000,30000) L_0x1e4d830/d; +L_0x1e4dc20/d .functor OR 1, L_0x1e4dc90, L_0x1e4de40, C4<0>, C4<0>; +L_0x1e4dc20 .delay 1 (30000,30000,30000) L_0x1e4dc20/d; +v0x1cbfb40_0 .net *"_s0", 0 0, L_0x1e4d3e0; 1 drivers +v0x1cbfc40_0 .net *"_s10", 0 0, L_0x1e4d940; 1 drivers +v0x1cbfd20_0 .net *"_s12", 0 0, L_0x1e4daa0; 1 drivers +v0x1cbfde0_0 .net *"_s14", 0 0, L_0x1e4dc90; 1 drivers +v0x1cbfec0_0 .net *"_s16", 0 0, L_0x1e4de40; 1 drivers +v0x1cbfff0_0 .net *"_s3", 0 0, L_0x1e4d4a0; 1 drivers +v0x1cc00d0_0 .net *"_s5", 0 0, L_0x1e4d600; 1 drivers +v0x1cc01b0_0 .net *"_s6", 0 0, L_0x1e4d830; 1 drivers +v0x1cc0290_0 .net "in", 3 0, L_0x1e4df30; 1 drivers +v0x1cc0400_0 .net "ors", 1 0, L_0x1e4d740; 1 drivers +v0x1cc04e0_0 .net "out", 0 0, L_0x1e4dc20; 1 drivers +L_0x1e4d4a0 .part L_0x1e4df30, 0, 1; +L_0x1e4d600 .part L_0x1e4df30, 1, 1; +L_0x1e4d740 .concat8 [ 1 1 0 0], L_0x1e4d3e0, L_0x1e4d830; +L_0x1e4d940 .part L_0x1e4df30, 2, 1; +L_0x1e4daa0 .part L_0x1e4df30, 3, 1; +L_0x1e4dc90 .part L_0x1e4d740, 0, 1; +L_0x1e4de40 .part L_0x1e4d740, 1, 1; +S_0x1cc0600 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cbf730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e4e060/d .functor OR 1, L_0x1e4e0d0, L_0x1e4e230, C4<0>, C4<0>; +L_0x1e4e060 .delay 1 (30000,30000,30000) L_0x1e4e060/d; +L_0x1e4e460/d .functor OR 1, L_0x1e4e570, L_0x1e4e6d0, C4<0>, C4<0>; +L_0x1e4e460 .delay 1 (30000,30000,30000) L_0x1e4e460/d; +L_0x1e4e850/d .functor OR 1, L_0x1e4e8c0, L_0x1e4ea70, C4<0>, C4<0>; +L_0x1e4e850 .delay 1 (30000,30000,30000) L_0x1e4e850/d; +v0x1cc07c0_0 .net *"_s0", 0 0, L_0x1e4e060; 1 drivers +v0x1cc08c0_0 .net *"_s10", 0 0, L_0x1e4e570; 1 drivers +v0x1cc09a0_0 .net *"_s12", 0 0, L_0x1e4e6d0; 1 drivers +v0x1cc0a60_0 .net *"_s14", 0 0, L_0x1e4e8c0; 1 drivers +v0x1cc0b40_0 .net *"_s16", 0 0, L_0x1e4ea70; 1 drivers +v0x1cc0c70_0 .net *"_s3", 0 0, L_0x1e4e0d0; 1 drivers +v0x1cc0d50_0 .net *"_s5", 0 0, L_0x1e4e230; 1 drivers +v0x1cc0e30_0 .net *"_s6", 0 0, L_0x1e4e460; 1 drivers +v0x1cc0f10_0 .net "in", 3 0, L_0x1e4eca0; 1 drivers +v0x1cc1080_0 .net "ors", 1 0, L_0x1e4e370; 1 drivers +v0x1cc1160_0 .net "out", 0 0, L_0x1e4e850; 1 drivers +L_0x1e4e0d0 .part L_0x1e4eca0, 0, 1; +L_0x1e4e230 .part L_0x1e4eca0, 1, 1; +L_0x1e4e370 .concat8 [ 1 1 0 0], L_0x1e4e060, L_0x1e4e460; +L_0x1e4e570 .part L_0x1e4eca0, 2, 1; +L_0x1e4e6d0 .part L_0x1e4eca0, 3, 1; +L_0x1e4e8c0 .part L_0x1e4e370, 0, 1; +L_0x1e4ea70 .part L_0x1e4e370, 1, 1; +S_0x1cc1a70 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cb53f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e4a510/d .functor XNOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; +L_0x1e4a510 .delay 1 (20000,20000,20000) L_0x1e4a510/d; +L_0x1e4a780/d .functor AND 1, L_0x1e52ca0, L_0x1e49450, C4<1>, C4<1>; +L_0x1e4a780 .delay 1 (30000,30000,30000) L_0x1e4a780/d; +L_0x1e4a7f0/d .functor AND 1, L_0x1e4a510, L_0x1e49230, C4<1>, C4<1>; +L_0x1e4a7f0 .delay 1 (30000,30000,30000) L_0x1e4a7f0/d; +L_0x1e4a950/d .functor OR 1, L_0x1e4a7f0, L_0x1e4a780, C4<0>, C4<0>; +L_0x1e4a950 .delay 1 (30000,30000,30000) L_0x1e4a950/d; +v0x1cc1d20_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers +v0x1cc1e10_0 .net "a_", 0 0, L_0x1e3d590; alias, 1 drivers +v0x1cc1ed0_0 .net "b", 0 0, L_0x1e52e00; alias, 1 drivers +v0x1cc1fc0_0 .net "b_", 0 0, L_0x1e49450; alias, 1 drivers +v0x1cc2060_0 .net "carryin", 0 0, L_0x1e49230; alias, 1 drivers +v0x1cc21a0_0 .net "eq", 0 0, L_0x1e4a510; 1 drivers +v0x1cc2260_0 .net "lt", 0 0, L_0x1e4a780; 1 drivers +v0x1cc2320_0 .net "out", 0 0, L_0x1e4a950; 1 drivers +v0x1cc23e0_0 .net "w0", 0 0, L_0x1e4a7f0; 1 drivers +S_0x1cc2630 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cb53f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e4a2f0/d .functor OR 1, L_0x1e49e40, L_0x1cc3890, C4<0>, C4<0>; +L_0x1e4a2f0 .delay 1 (30000,30000,30000) L_0x1e4a2f0/d; +v0x1cc3420_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers +v0x1cc3570_0 .net "b", 0 0, L_0x1e49450; alias, 1 drivers +v0x1cc3630_0 .net "c1", 0 0, L_0x1e49e40; 1 drivers +v0x1cc36d0_0 .net "c2", 0 0, L_0x1cc3890; 1 drivers +v0x1cc37a0_0 .net "carryin", 0 0, L_0x1e49230; alias, 1 drivers +v0x1cc3920_0 .net "carryout", 0 0, L_0x1e4a2f0; 1 drivers +v0x1cc39c0_0 .net "s1", 0 0, L_0x1e49d80; 1 drivers +v0x1cc3a60_0 .net "sum", 0 0, L_0x1e49fa0; 1 drivers +S_0x1cc2880 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cc2630; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e49d80/d .functor XOR 1, L_0x1e52ca0, L_0x1e49450, C4<0>, C4<0>; +L_0x1e49d80 .delay 1 (30000,30000,30000) L_0x1e49d80/d; +L_0x1e49e40/d .functor AND 1, L_0x1e52ca0, L_0x1e49450, C4<1>, C4<1>; +L_0x1e49e40 .delay 1 (30000,30000,30000) L_0x1e49e40/d; +v0x1cc2ae0_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers +v0x1cc2ba0_0 .net "b", 0 0, L_0x1e49450; alias, 1 drivers +v0x1cc2c60_0 .net "carryout", 0 0, L_0x1e49e40; alias, 1 drivers +v0x1cc2d00_0 .net "sum", 0 0, L_0x1e49d80; alias, 1 drivers +S_0x1cc2e30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cc2630; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e49fa0/d .functor XOR 1, L_0x1e49d80, L_0x1e49230, C4<0>, C4<0>; +L_0x1e49fa0 .delay 1 (30000,30000,30000) L_0x1e49fa0/d; +L_0x1cc3890/d .functor AND 1, L_0x1e49d80, L_0x1e49230, C4<1>, C4<1>; +L_0x1cc3890 .delay 1 (30000,30000,30000) L_0x1cc3890/d; +v0x1cc3090_0 .net "a", 0 0, L_0x1e49d80; alias, 1 drivers +v0x1cc3160_0 .net "b", 0 0, L_0x1e49230; alias, 1 drivers +v0x1cc3200_0 .net "carryout", 0 0, L_0x1cc3890; alias, 1 drivers +v0x1cc32d0_0 .net "sum", 0 0, L_0x1e49fa0; alias, 1 drivers +S_0x1cc4e80 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cb5120; + .timescale -9 -12; +L_0x7f72592db8d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db920 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e52d40/d .functor OR 1, L_0x7f72592db8d8, L_0x7f72592db920, C4<0>, C4<0>; +L_0x1e52d40 .delay 1 (30000,30000,30000) L_0x1e52d40/d; +v0x1cc5070_0 .net/2u *"_s0", 0 0, L_0x7f72592db8d8; 1 drivers +v0x1cc5150_0 .net/2u *"_s2", 0 0, L_0x7f72592db920; 1 drivers +S_0x1cc5230 .scope generate, "alu_slices[23]" "alu_slices[23]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1cc5440 .param/l "i" 0 3 37, +C4<010111>; +S_0x1cc5500 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cc5230; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e493c0/d .functor NOT 1, L_0x1e5c800, C4<0>, C4<0>, C4<0>; +L_0x1e493c0 .delay 1 (10000,10000,10000) L_0x1e493c0/d; +L_0x1e531c0/d .functor NOT 1, L_0x1e52ea0, C4<0>, C4<0>, C4<0>; +L_0x1e531c0 .delay 1 (10000,10000,10000) L_0x1e531c0/d; +L_0x1e54210/d .functor XOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; +L_0x1e54210 .delay 1 (30000,30000,30000) L_0x1e54210/d; +L_0x7f72592db968 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592db9b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e548c0/d .functor OR 1, L_0x7f72592db968, L_0x7f72592db9b0, C4<0>, C4<0>; +L_0x1e548c0 .delay 1 (30000,30000,30000) L_0x1e548c0/d; +L_0x1e54ac0/d .functor AND 1, L_0x1e5c800, L_0x1e52ea0, C4<1>, C4<1>; +L_0x1e54ac0 .delay 1 (30000,30000,30000) L_0x1e54ac0/d; +L_0x1e54b80/d .functor NAND 1, L_0x1e5c800, L_0x1e52ea0, C4<1>, C4<1>; +L_0x1e54b80 .delay 1 (20000,20000,20000) L_0x1e54b80/d; +L_0x1e54ce0/d .functor XOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; +L_0x1e54ce0 .delay 1 (20000,20000,20000) L_0x1e54ce0/d; +L_0x1e55190/d .functor OR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; +L_0x1e55190 .delay 1 (30000,30000,30000) L_0x1e55190/d; +L_0x1e5c700/d .functor NOT 1, L_0x1e58a20, C4<0>, C4<0>, C4<0>; +L_0x1e5c700 .delay 1 (10000,10000,10000) L_0x1e5c700/d; +v0x1cd3c40_0 .net "A", 0 0, L_0x1e5c800; 1 drivers +v0x1cd3d00_0 .net "A_", 0 0, L_0x1e493c0; 1 drivers +v0x1cd3dc0_0 .net "B", 0 0, L_0x1e52ea0; 1 drivers +v0x1cd3e90_0 .net "B_", 0 0, L_0x1e531c0; 1 drivers +v0x1cd3f30_0 .net *"_s12", 0 0, L_0x1e548c0; 1 drivers +v0x1cd4020_0 .net/2s *"_s14", 0 0, L_0x7f72592db968; 1 drivers +v0x1cd40e0_0 .net/2s *"_s16", 0 0, L_0x7f72592db9b0; 1 drivers +v0x1cd41c0_0 .net *"_s18", 0 0, L_0x1e54ac0; 1 drivers +v0x1cd42a0_0 .net *"_s20", 0 0, L_0x1e54b80; 1 drivers +v0x1cd4410_0 .net *"_s22", 0 0, L_0x1e54ce0; 1 drivers +v0x1cd44f0_0 .net *"_s24", 0 0, L_0x1e55190; 1 drivers +o0x7f725932acf8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1cd45d0_0 name=_s30 +o0x7f725932ad28 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1cd46b0_0 name=_s32 +v0x1cd4790_0 .net *"_s8", 0 0, L_0x1e54210; 1 drivers +v0x1cd4870_0 .net "carryin", 0 0, L_0x1e52f40; 1 drivers +v0x1cd4910_0 .net "carryout", 0 0, L_0x1e5c3a0; 1 drivers +v0x1cd49b0_0 .net "carryouts", 7 0, L_0x1ec12a0; 1 drivers +v0x1cd4b60_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cd4c00_0 .net "result", 0 0, L_0x1e58a20; 1 drivers +v0x1cd4cf0_0 .net "results", 7 0, L_0x1e54f60; 1 drivers +v0x1cd4e00_0 .net "zero", 0 0, L_0x1e5c700; 1 drivers +LS_0x1e54f60_0_0 .concat8 [ 1 1 1 1], L_0x1e536e0, L_0x1e53d10, L_0x1e54210, L_0x1e548c0; +LS_0x1e54f60_0_4 .concat8 [ 1 1 1 1], L_0x1e54ac0, L_0x1e54b80, L_0x1e54ce0, L_0x1e55190; +L_0x1e54f60 .concat8 [ 4 4 0 0], LS_0x1e54f60_0_0, LS_0x1e54f60_0_4; +LS_0x1ec12a0_0_0 .concat [ 1 1 1 1], L_0x1e53990, L_0x1e540b0, o0x7f725932acf8, L_0x1e54710; +LS_0x1ec12a0_0_4 .concat [ 4 0 0 0], o0x7f725932ad28; +L_0x1ec12a0 .concat [ 4 4 0 0], LS_0x1ec12a0_0_0, LS_0x1ec12a0_0_4; +S_0x1cc5780 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cc5500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e53990/d .functor OR 1, L_0x1e53470, L_0x1e53830, C4<0>, C4<0>; +L_0x1e53990 .delay 1 (30000,30000,30000) L_0x1e53990/d; +v0x1cc65b0_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers +v0x1cc6670_0 .net "b", 0 0, L_0x1e52ea0; alias, 1 drivers +v0x1cc6740_0 .net "c1", 0 0, L_0x1e53470; 1 drivers +v0x1cc6840_0 .net "c2", 0 0, L_0x1e53830; 1 drivers +v0x1cc6910_0 .net "carryin", 0 0, L_0x1e52f40; alias, 1 drivers +v0x1cc6a00_0 .net "carryout", 0 0, L_0x1e53990; 1 drivers +v0x1cc6aa0_0 .net "s1", 0 0, L_0x1e533b0; 1 drivers +v0x1cc6b90_0 .net "sum", 0 0, L_0x1e536e0; 1 drivers +S_0x1cc59f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cc5780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e533b0/d .functor XOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; +L_0x1e533b0 .delay 1 (30000,30000,30000) L_0x1e533b0/d; +L_0x1e53470/d .functor AND 1, L_0x1e5c800, L_0x1e52ea0, C4<1>, C4<1>; +L_0x1e53470 .delay 1 (30000,30000,30000) L_0x1e53470/d; +v0x1cc5c50_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers +v0x1cc5d30_0 .net "b", 0 0, L_0x1e52ea0; alias, 1 drivers +v0x1cc5df0_0 .net "carryout", 0 0, L_0x1e53470; alias, 1 drivers +v0x1cc5e90_0 .net "sum", 0 0, L_0x1e533b0; alias, 1 drivers +S_0x1cc5fd0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cc5780; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e536e0/d .functor XOR 1, L_0x1e533b0, L_0x1e52f40, C4<0>, C4<0>; +L_0x1e536e0 .delay 1 (30000,30000,30000) L_0x1e536e0/d; +L_0x1e53830/d .functor AND 1, L_0x1e533b0, L_0x1e52f40, C4<1>, C4<1>; +L_0x1e53830 .delay 1 (30000,30000,30000) L_0x1e53830/d; +v0x1cc6230_0 .net "a", 0 0, L_0x1e533b0; alias, 1 drivers +v0x1cc62d0_0 .net "b", 0 0, L_0x1e52f40; alias, 1 drivers +v0x1cc6370_0 .net "carryout", 0 0, L_0x1e53830; alias, 1 drivers +v0x1cc6440_0 .net "sum", 0 0, L_0x1e536e0; alias, 1 drivers +S_0x1cc6c60 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cc5500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1ccc050_0 .net "ands", 7 0, L_0x1e5a460; 1 drivers +v0x1ccc160_0 .net "in", 7 0, L_0x1ec12a0; alias, 1 drivers +v0x1ccc220_0 .net "out", 0 0, L_0x1e5c3a0; alias, 1 drivers +v0x1ccc2f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cc6e80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cc6c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cc95b0_0 .net "A", 7 0, L_0x1ec12a0; alias, 1 drivers +v0x1cc96b0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cc9770_0 .net *"_s0", 0 0, L_0x1e58d80; 1 drivers +v0x1cc9830_0 .net *"_s12", 0 0, L_0x1e596f0; 1 drivers +v0x1cc9910_0 .net *"_s16", 0 0, L_0x1e59a50; 1 drivers +v0x1cc9a40_0 .net *"_s20", 0 0, L_0x1e59d60; 1 drivers +v0x1cc9b20_0 .net *"_s24", 0 0, L_0x1e5a150; 1 drivers +v0x1cc9c00_0 .net *"_s28", 0 0, L_0x1e5a0e0; 1 drivers +v0x1cc9ce0_0 .net *"_s4", 0 0, L_0x1e59090; 1 drivers +v0x1cc9e50_0 .net *"_s8", 0 0, L_0x1e593e0; 1 drivers +v0x1cc9f30_0 .net "out", 7 0, L_0x1e5a460; alias, 1 drivers +L_0x1e58e40 .part L_0x1ec12a0, 0, 1; +L_0x1e58fa0 .part v0x1d6daa0_0, 0, 1; +L_0x1e59150 .part L_0x1ec12a0, 1, 1; +L_0x1e59340 .part v0x1d6daa0_0, 1, 1; +L_0x1e594a0 .part L_0x1ec12a0, 2, 1; +L_0x1e59600 .part v0x1d6daa0_0, 2, 1; +L_0x1e597b0 .part L_0x1ec12a0, 3, 1; +L_0x1e59910 .part v0x1d6daa0_0, 3, 1; +L_0x1e59b10 .part L_0x1ec12a0, 4, 1; +L_0x1e59c70 .part v0x1d6daa0_0, 4, 1; +L_0x1e59dd0 .part L_0x1ec12a0, 5, 1; +L_0x1e5a040 .part v0x1d6daa0_0, 5, 1; +L_0x1e5a210 .part L_0x1ec12a0, 6, 1; +L_0x1e5a370 .part v0x1d6daa0_0, 6, 1; +LS_0x1e5a460_0_0 .concat8 [ 1 1 1 1], L_0x1e58d80, L_0x1e59090, L_0x1e593e0, L_0x1e596f0; +LS_0x1e5a460_0_4 .concat8 [ 1 1 1 1], L_0x1e59a50, L_0x1e59d60, L_0x1e5a150, L_0x1e5a0e0; +L_0x1e5a460 .concat8 [ 4 4 0 0], LS_0x1e5a460_0_0, LS_0x1e5a460_0_4; +L_0x1e5a820 .part L_0x1ec12a0, 7, 1; +L_0x1e5aa10 .part v0x1d6daa0_0, 7, 1; +S_0x1cc70e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc72f0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e58d80/d .functor AND 1, L_0x1e58e40, L_0x1e58fa0, C4<1>, C4<1>; +L_0x1e58d80 .delay 1 (30000,30000,30000) L_0x1e58d80/d; +v0x1cc73d0_0 .net *"_s0", 0 0, L_0x1e58e40; 1 drivers +v0x1cc74b0_0 .net *"_s1", 0 0, L_0x1e58fa0; 1 drivers +S_0x1cc7590 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc77a0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e59090/d .functor AND 1, L_0x1e59150, L_0x1e59340, C4<1>, C4<1>; +L_0x1e59090 .delay 1 (30000,30000,30000) L_0x1e59090/d; +v0x1cc7860_0 .net *"_s0", 0 0, L_0x1e59150; 1 drivers +v0x1cc7940_0 .net *"_s1", 0 0, L_0x1e59340; 1 drivers +S_0x1cc7a20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc7c30 .param/l "i" 0 4 54, +C4<010>; +L_0x1e593e0/d .functor AND 1, L_0x1e594a0, L_0x1e59600, C4<1>, C4<1>; +L_0x1e593e0 .delay 1 (30000,30000,30000) L_0x1e593e0/d; +v0x1cc7cd0_0 .net *"_s0", 0 0, L_0x1e594a0; 1 drivers +v0x1cc7db0_0 .net *"_s1", 0 0, L_0x1e59600; 1 drivers +S_0x1cc7e90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc80a0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e596f0/d .functor AND 1, L_0x1e597b0, L_0x1e59910, C4<1>, C4<1>; +L_0x1e596f0 .delay 1 (30000,30000,30000) L_0x1e596f0/d; +v0x1cc8160_0 .net *"_s0", 0 0, L_0x1e597b0; 1 drivers +v0x1cc8240_0 .net *"_s1", 0 0, L_0x1e59910; 1 drivers +S_0x1cc8320 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc8580 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e59a50/d .functor AND 1, L_0x1e59b10, L_0x1e59c70, C4<1>, C4<1>; +L_0x1e59a50 .delay 1 (30000,30000,30000) L_0x1e59a50/d; +v0x1cc8640_0 .net *"_s0", 0 0, L_0x1e59b10; 1 drivers +v0x1cc8720_0 .net *"_s1", 0 0, L_0x1e59c70; 1 drivers +S_0x1cc8800 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc8a10 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e59d60/d .functor AND 1, L_0x1e59dd0, L_0x1e5a040, C4<1>, C4<1>; +L_0x1e59d60 .delay 1 (30000,30000,30000) L_0x1e59d60/d; +v0x1cc8ad0_0 .net *"_s0", 0 0, L_0x1e59dd0; 1 drivers +v0x1cc8bb0_0 .net *"_s1", 0 0, L_0x1e5a040; 1 drivers +S_0x1cc8c90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc8ea0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e5a150/d .functor AND 1, L_0x1e5a210, L_0x1e5a370, C4<1>, C4<1>; +L_0x1e5a150 .delay 1 (30000,30000,30000) L_0x1e5a150/d; +v0x1cc8f60_0 .net *"_s0", 0 0, L_0x1e5a210; 1 drivers +v0x1cc9040_0 .net *"_s1", 0 0, L_0x1e5a370; 1 drivers +S_0x1cc9120 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cc6e80; + .timescale -9 -12; +P_0x1cc9330 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e5a0e0/d .functor AND 1, L_0x1e5a820, L_0x1e5aa10, C4<1>, C4<1>; +L_0x1e5a0e0 .delay 1 (30000,30000,30000) L_0x1e5a0e0/d; +v0x1cc93f0_0 .net *"_s0", 0 0, L_0x1e5a820; 1 drivers +v0x1cc94d0_0 .net *"_s1", 0 0, L_0x1e5aa10; 1 drivers +S_0x1cca090 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cc6c60; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e5c3a0/d .functor OR 1, L_0x1e5c460, L_0x1e5c610, C4<0>, C4<0>; +L_0x1e5c3a0 .delay 1 (30000,30000,30000) L_0x1e5c3a0/d; +v0x1ccbbe0_0 .net *"_s10", 0 0, L_0x1e5c460; 1 drivers +v0x1ccbcc0_0 .net *"_s12", 0 0, L_0x1e5c610; 1 drivers +v0x1ccbda0_0 .net "in", 7 0, L_0x1e5a460; alias, 1 drivers +v0x1ccbe70_0 .net "ors", 1 0, L_0x1e5c1c0; 1 drivers +v0x1ccbf30_0 .net "out", 0 0, L_0x1e5c3a0; alias, 1 drivers +L_0x1e5b650 .part L_0x1e5a460, 0, 4; +L_0x1e5c1c0 .concat8 [ 1 1 0 0], L_0x1e5b340, L_0x1e5bf70; +L_0x1e5c300 .part L_0x1e5a460, 4, 4; +L_0x1e5c460 .part L_0x1e5c1c0, 0, 1; +L_0x1e5c610 .part L_0x1e5c1c0, 1, 1; +S_0x1cca250 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cca090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e5ab00/d .functor OR 1, L_0x1e5abc0, L_0x1e5ad20, C4<0>, C4<0>; +L_0x1e5ab00 .delay 1 (30000,30000,30000) L_0x1e5ab00/d; +L_0x1e5af50/d .functor OR 1, L_0x1e5b060, L_0x1e5b1c0, C4<0>, C4<0>; +L_0x1e5af50 .delay 1 (30000,30000,30000) L_0x1e5af50/d; +L_0x1e5b340/d .functor OR 1, L_0x1e5b3b0, L_0x1e5b560, C4<0>, C4<0>; +L_0x1e5b340 .delay 1 (30000,30000,30000) L_0x1e5b340/d; +v0x1cca4a0_0 .net *"_s0", 0 0, L_0x1e5ab00; 1 drivers +v0x1cca5a0_0 .net *"_s10", 0 0, L_0x1e5b060; 1 drivers +v0x1cca680_0 .net *"_s12", 0 0, L_0x1e5b1c0; 1 drivers +v0x1cca740_0 .net *"_s14", 0 0, L_0x1e5b3b0; 1 drivers +v0x1cca820_0 .net *"_s16", 0 0, L_0x1e5b560; 1 drivers +v0x1cca950_0 .net *"_s3", 0 0, L_0x1e5abc0; 1 drivers +v0x1ccaa30_0 .net *"_s5", 0 0, L_0x1e5ad20; 1 drivers +v0x1ccab10_0 .net *"_s6", 0 0, L_0x1e5af50; 1 drivers +v0x1ccabf0_0 .net "in", 3 0, L_0x1e5b650; 1 drivers +v0x1ccad60_0 .net "ors", 1 0, L_0x1e5ae60; 1 drivers +v0x1ccae40_0 .net "out", 0 0, L_0x1e5b340; 1 drivers +L_0x1e5abc0 .part L_0x1e5b650, 0, 1; +L_0x1e5ad20 .part L_0x1e5b650, 1, 1; +L_0x1e5ae60 .concat8 [ 1 1 0 0], L_0x1e5ab00, L_0x1e5af50; +L_0x1e5b060 .part L_0x1e5b650, 2, 1; +L_0x1e5b1c0 .part L_0x1e5b650, 3, 1; +L_0x1e5b3b0 .part L_0x1e5ae60, 0, 1; +L_0x1e5b560 .part L_0x1e5ae60, 1, 1; +S_0x1ccaf60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cca090; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e5b780/d .functor OR 1, L_0x1e5b7f0, L_0x1e5b950, C4<0>, C4<0>; +L_0x1e5b780 .delay 1 (30000,30000,30000) L_0x1e5b780/d; +L_0x1e5bb80/d .functor OR 1, L_0x1e5bc90, L_0x1e5bdf0, C4<0>, C4<0>; +L_0x1e5bb80 .delay 1 (30000,30000,30000) L_0x1e5bb80/d; +L_0x1e5bf70/d .functor OR 1, L_0x1e5bfe0, L_0x1e5c0d0, C4<0>, C4<0>; +L_0x1e5bf70 .delay 1 (30000,30000,30000) L_0x1e5bf70/d; +v0x1ccb120_0 .net *"_s0", 0 0, L_0x1e5b780; 1 drivers +v0x1ccb220_0 .net *"_s10", 0 0, L_0x1e5bc90; 1 drivers +v0x1ccb300_0 .net *"_s12", 0 0, L_0x1e5bdf0; 1 drivers +v0x1ccb3c0_0 .net *"_s14", 0 0, L_0x1e5bfe0; 1 drivers +v0x1ccb4a0_0 .net *"_s16", 0 0, L_0x1e5c0d0; 1 drivers +v0x1ccb5d0_0 .net *"_s3", 0 0, L_0x1e5b7f0; 1 drivers +v0x1ccb6b0_0 .net *"_s5", 0 0, L_0x1e5b950; 1 drivers +v0x1ccb790_0 .net *"_s6", 0 0, L_0x1e5bb80; 1 drivers +v0x1ccb870_0 .net "in", 3 0, L_0x1e5c300; 1 drivers +v0x1ccb9e0_0 .net "ors", 1 0, L_0x1e5ba90; 1 drivers +v0x1ccbac0_0 .net "out", 0 0, L_0x1e5bf70; 1 drivers +L_0x1e5b7f0 .part L_0x1e5c300, 0, 1; +L_0x1e5b950 .part L_0x1e5c300, 1, 1; +L_0x1e5ba90 .concat8 [ 1 1 0 0], L_0x1e5b780, L_0x1e5bb80; +L_0x1e5bc90 .part L_0x1e5c300, 2, 1; +L_0x1e5bdf0 .part L_0x1e5c300, 3, 1; +L_0x1e5bfe0 .part L_0x1e5ba90, 0, 1; +L_0x1e5c0d0 .part L_0x1e5ba90, 1, 1; +S_0x1ccc3d0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cc5500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cd1800_0 .net "ands", 7 0, L_0x1e56a20; 1 drivers +v0x1cd1910_0 .net "in", 7 0, L_0x1e54f60; alias, 1 drivers +v0x1cd19d0_0 .net "out", 0 0, L_0x1e58a20; alias, 1 drivers +v0x1cd1aa0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1ccc620 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ccc3d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cced60_0 .net "A", 7 0, L_0x1e54f60; alias, 1 drivers +v0x1ccee60_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ccef20_0 .net *"_s0", 0 0, L_0x1e552f0; 1 drivers +v0x1ccefe0_0 .net *"_s12", 0 0, L_0x1e55cb0; 1 drivers +v0x1ccf0c0_0 .net *"_s16", 0 0, L_0x1e56010; 1 drivers +v0x1ccf1f0_0 .net *"_s20", 0 0, L_0x1e563e0; 1 drivers +v0x1ccf2d0_0 .net *"_s24", 0 0, L_0x1e56710; 1 drivers +v0x1ccf3b0_0 .net *"_s28", 0 0, L_0x1e566a0; 1 drivers +v0x1ccf490_0 .net *"_s4", 0 0, L_0x1e55690; 1 drivers +v0x1ccf600_0 .net *"_s8", 0 0, L_0x1e559a0; 1 drivers +v0x1ccf6e0_0 .net "out", 7 0, L_0x1e56a20; alias, 1 drivers +L_0x1e55400 .part L_0x1e54f60, 0, 1; +L_0x1e555f0 .part v0x1d6daa0_0, 0, 1; +L_0x1e55750 .part L_0x1e54f60, 1, 1; +L_0x1e558b0 .part v0x1d6daa0_0, 1, 1; +L_0x1e55a60 .part L_0x1e54f60, 2, 1; +L_0x1e55bc0 .part v0x1d6daa0_0, 2, 1; +L_0x1e55d70 .part L_0x1e54f60, 3, 1; +L_0x1e55ed0 .part v0x1d6daa0_0, 3, 1; +L_0x1e560d0 .part L_0x1e54f60, 4, 1; +L_0x1e56340 .part v0x1d6daa0_0, 4, 1; +L_0x1e56450 .part L_0x1e54f60, 5, 1; +L_0x1e565b0 .part v0x1d6daa0_0, 5, 1; +L_0x1e567d0 .part L_0x1e54f60, 6, 1; +L_0x1e56930 .part v0x1d6daa0_0, 6, 1; +LS_0x1e56a20_0_0 .concat8 [ 1 1 1 1], L_0x1e552f0, L_0x1e55690, L_0x1e559a0, L_0x1e55cb0; +LS_0x1e56a20_0_4 .concat8 [ 1 1 1 1], L_0x1e56010, L_0x1e563e0, L_0x1e56710, L_0x1e566a0; +L_0x1e56a20 .concat8 [ 4 4 0 0], LS_0x1e56a20_0_0, LS_0x1e56a20_0_4; +L_0x1e56de0 .part L_0x1e54f60, 7, 1; +L_0x1e56fd0 .part v0x1d6daa0_0, 7, 1; +S_0x1ccc860 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1ccca70 .param/l "i" 0 4 54, +C4<00>; +L_0x1e552f0/d .functor AND 1, L_0x1e55400, L_0x1e555f0, C4<1>, C4<1>; +L_0x1e552f0 .delay 1 (30000,30000,30000) L_0x1e552f0/d; +v0x1cccb50_0 .net *"_s0", 0 0, L_0x1e55400; 1 drivers +v0x1cccc30_0 .net *"_s1", 0 0, L_0x1e555f0; 1 drivers +S_0x1cccd10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1cccf20 .param/l "i" 0 4 54, +C4<01>; +L_0x1e55690/d .functor AND 1, L_0x1e55750, L_0x1e558b0, C4<1>, C4<1>; +L_0x1e55690 .delay 1 (30000,30000,30000) L_0x1e55690/d; +v0x1cccfe0_0 .net *"_s0", 0 0, L_0x1e55750; 1 drivers +v0x1ccd0c0_0 .net *"_s1", 0 0, L_0x1e558b0; 1 drivers +S_0x1ccd1a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1ccd3e0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e559a0/d .functor AND 1, L_0x1e55a60, L_0x1e55bc0, C4<1>, C4<1>; +L_0x1e559a0 .delay 1 (30000,30000,30000) L_0x1e559a0/d; +v0x1ccd480_0 .net *"_s0", 0 0, L_0x1e55a60; 1 drivers +v0x1ccd560_0 .net *"_s1", 0 0, L_0x1e55bc0; 1 drivers +S_0x1ccd640 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1ccd850 .param/l "i" 0 4 54, +C4<011>; +L_0x1e55cb0/d .functor AND 1, L_0x1e55d70, L_0x1e55ed0, C4<1>, C4<1>; +L_0x1e55cb0 .delay 1 (30000,30000,30000) L_0x1e55cb0/d; +v0x1ccd910_0 .net *"_s0", 0 0, L_0x1e55d70; 1 drivers +v0x1ccd9f0_0 .net *"_s1", 0 0, L_0x1e55ed0; 1 drivers +S_0x1ccdad0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1ccdd30 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e56010/d .functor AND 1, L_0x1e560d0, L_0x1e56340, C4<1>, C4<1>; +L_0x1e56010 .delay 1 (30000,30000,30000) L_0x1e56010/d; +v0x1ccddf0_0 .net *"_s0", 0 0, L_0x1e560d0; 1 drivers +v0x1ccded0_0 .net *"_s1", 0 0, L_0x1e56340; 1 drivers +S_0x1ccdfb0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1cce1c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e563e0/d .functor AND 1, L_0x1e56450, L_0x1e565b0, C4<1>, C4<1>; +L_0x1e563e0 .delay 1 (30000,30000,30000) L_0x1e563e0/d; +v0x1cce280_0 .net *"_s0", 0 0, L_0x1e56450; 1 drivers +v0x1cce360_0 .net *"_s1", 0 0, L_0x1e565b0; 1 drivers +S_0x1cce440 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1cce650 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e56710/d .functor AND 1, L_0x1e567d0, L_0x1e56930, C4<1>, C4<1>; +L_0x1e56710 .delay 1 (30000,30000,30000) L_0x1e56710/d; +v0x1cce710_0 .net *"_s0", 0 0, L_0x1e567d0; 1 drivers +v0x1cce7f0_0 .net *"_s1", 0 0, L_0x1e56930; 1 drivers +S_0x1cce8d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ccc620; + .timescale -9 -12; +P_0x1cceae0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e566a0/d .functor AND 1, L_0x1e56de0, L_0x1e56fd0, C4<1>, C4<1>; +L_0x1e566a0 .delay 1 (30000,30000,30000) L_0x1e566a0/d; +v0x1cceba0_0 .net *"_s0", 0 0, L_0x1e56de0; 1 drivers +v0x1ccec80_0 .net *"_s1", 0 0, L_0x1e56fd0; 1 drivers +S_0x1ccf840 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ccc3d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e58a20/d .functor OR 1, L_0x1e58ae0, L_0x1e58c90, C4<0>, C4<0>; +L_0x1e58a20 .delay 1 (30000,30000,30000) L_0x1e58a20/d; +v0x1cd1390_0 .net *"_s10", 0 0, L_0x1e58ae0; 1 drivers +v0x1cd1470_0 .net *"_s12", 0 0, L_0x1e58c90; 1 drivers +v0x1cd1550_0 .net "in", 7 0, L_0x1e56a20; alias, 1 drivers +v0x1cd1620_0 .net "ors", 1 0, L_0x1e58840; 1 drivers +v0x1cd16e0_0 .net "out", 0 0, L_0x1e58a20; alias, 1 drivers +L_0x1e57c10 .part L_0x1e56a20, 0, 4; +L_0x1e58840 .concat8 [ 1 1 0 0], L_0x1e57900, L_0x1e58530; +L_0x1e58980 .part L_0x1e56a20, 4, 4; +L_0x1e58ae0 .part L_0x1e58840, 0, 1; +L_0x1e58c90 .part L_0x1e58840, 1, 1; +S_0x1ccfa00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1ccf840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e570c0/d .functor OR 1, L_0x1e57180, L_0x1e572e0, C4<0>, C4<0>; +L_0x1e570c0 .delay 1 (30000,30000,30000) L_0x1e570c0/d; +L_0x1e57510/d .functor OR 1, L_0x1e57620, L_0x1e57780, C4<0>, C4<0>; +L_0x1e57510 .delay 1 (30000,30000,30000) L_0x1e57510/d; +L_0x1e57900/d .functor OR 1, L_0x1e57970, L_0x1e57b20, C4<0>, C4<0>; +L_0x1e57900 .delay 1 (30000,30000,30000) L_0x1e57900/d; +v0x1ccfc50_0 .net *"_s0", 0 0, L_0x1e570c0; 1 drivers +v0x1ccfd50_0 .net *"_s10", 0 0, L_0x1e57620; 1 drivers +v0x1ccfe30_0 .net *"_s12", 0 0, L_0x1e57780; 1 drivers +v0x1ccfef0_0 .net *"_s14", 0 0, L_0x1e57970; 1 drivers +v0x1ccffd0_0 .net *"_s16", 0 0, L_0x1e57b20; 1 drivers +v0x1cd0100_0 .net *"_s3", 0 0, L_0x1e57180; 1 drivers +v0x1cd01e0_0 .net *"_s5", 0 0, L_0x1e572e0; 1 drivers +v0x1cd02c0_0 .net *"_s6", 0 0, L_0x1e57510; 1 drivers +v0x1cd03a0_0 .net "in", 3 0, L_0x1e57c10; 1 drivers +v0x1cd0510_0 .net "ors", 1 0, L_0x1e57420; 1 drivers +v0x1cd05f0_0 .net "out", 0 0, L_0x1e57900; 1 drivers +L_0x1e57180 .part L_0x1e57c10, 0, 1; +L_0x1e572e0 .part L_0x1e57c10, 1, 1; +L_0x1e57420 .concat8 [ 1 1 0 0], L_0x1e570c0, L_0x1e57510; +L_0x1e57620 .part L_0x1e57c10, 2, 1; +L_0x1e57780 .part L_0x1e57c10, 3, 1; +L_0x1e57970 .part L_0x1e57420, 0, 1; +L_0x1e57b20 .part L_0x1e57420, 1, 1; +S_0x1cd0710 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1ccf840; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e57d40/d .functor OR 1, L_0x1e57db0, L_0x1e57f10, C4<0>, C4<0>; +L_0x1e57d40 .delay 1 (30000,30000,30000) L_0x1e57d40/d; +L_0x1e58140/d .functor OR 1, L_0x1e58250, L_0x1e583b0, C4<0>, C4<0>; +L_0x1e58140 .delay 1 (30000,30000,30000) L_0x1e58140/d; +L_0x1e58530/d .functor OR 1, L_0x1e585a0, L_0x1e58750, C4<0>, C4<0>; +L_0x1e58530 .delay 1 (30000,30000,30000) L_0x1e58530/d; +v0x1cd08d0_0 .net *"_s0", 0 0, L_0x1e57d40; 1 drivers +v0x1cd09d0_0 .net *"_s10", 0 0, L_0x1e58250; 1 drivers +v0x1cd0ab0_0 .net *"_s12", 0 0, L_0x1e583b0; 1 drivers +v0x1cd0b70_0 .net *"_s14", 0 0, L_0x1e585a0; 1 drivers +v0x1cd0c50_0 .net *"_s16", 0 0, L_0x1e58750; 1 drivers +v0x1cd0d80_0 .net *"_s3", 0 0, L_0x1e57db0; 1 drivers +v0x1cd0e60_0 .net *"_s5", 0 0, L_0x1e57f10; 1 drivers +v0x1cd0f40_0 .net *"_s6", 0 0, L_0x1e58140; 1 drivers +v0x1cd1020_0 .net "in", 3 0, L_0x1e58980; 1 drivers +v0x1cd1190_0 .net "ors", 1 0, L_0x1e58050; 1 drivers +v0x1cd1270_0 .net "out", 0 0, L_0x1e58530; 1 drivers +L_0x1e57db0 .part L_0x1e58980, 0, 1; +L_0x1e57f10 .part L_0x1e58980, 1, 1; +L_0x1e58050 .concat8 [ 1 1 0 0], L_0x1e57d40, L_0x1e58140; +L_0x1e58250 .part L_0x1e58980, 2, 1; +L_0x1e583b0 .part L_0x1e58980, 3, 1; +L_0x1e585a0 .part L_0x1e58050, 0, 1; +L_0x1e58750 .part L_0x1e58050, 1, 1; +S_0x1cd1b80 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cc5500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e542d0/d .functor XNOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; +L_0x1e542d0 .delay 1 (20000,20000,20000) L_0x1e542d0/d; +L_0x1e54540/d .functor AND 1, L_0x1e5c800, L_0x1e531c0, C4<1>, C4<1>; +L_0x1e54540 .delay 1 (30000,30000,30000) L_0x1e54540/d; +L_0x1e545b0/d .functor AND 1, L_0x1e542d0, L_0x1e52f40, C4<1>, C4<1>; +L_0x1e545b0 .delay 1 (30000,30000,30000) L_0x1e545b0/d; +L_0x1e54710/d .functor OR 1, L_0x1e545b0, L_0x1e54540, C4<0>, C4<0>; +L_0x1e54710 .delay 1 (30000,30000,30000) L_0x1e54710/d; +v0x1cd1e30_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers +v0x1cd1f20_0 .net "a_", 0 0, L_0x1e493c0; alias, 1 drivers +v0x1cd1fe0_0 .net "b", 0 0, L_0x1e52ea0; alias, 1 drivers +v0x1cd20d0_0 .net "b_", 0 0, L_0x1e531c0; alias, 1 drivers +v0x1cd2170_0 .net "carryin", 0 0, L_0x1e52f40; alias, 1 drivers +v0x1cd22b0_0 .net "eq", 0 0, L_0x1e542d0; 1 drivers +v0x1cd2370_0 .net "lt", 0 0, L_0x1e54540; 1 drivers +v0x1cd2430_0 .net "out", 0 0, L_0x1e54710; 1 drivers +v0x1cd24f0_0 .net "w0", 0 0, L_0x1e545b0; 1 drivers +S_0x1cd2740 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cc5500; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e540b0/d .functor OR 1, L_0x1e53bb0, L_0x1cd39b0, C4<0>, C4<0>; +L_0x1e540b0 .delay 1 (30000,30000,30000) L_0x1e540b0/d; +v0x1cd3510_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers +v0x1cd3660_0 .net "b", 0 0, L_0x1e531c0; alias, 1 drivers +v0x1cd3720_0 .net "c1", 0 0, L_0x1e53bb0; 1 drivers +v0x1cd37f0_0 .net "c2", 0 0, L_0x1cd39b0; 1 drivers +v0x1cd38c0_0 .net "carryin", 0 0, L_0x1e52f40; alias, 1 drivers +v0x1cd3a40_0 .net "carryout", 0 0, L_0x1e540b0; 1 drivers +v0x1cd3ae0_0 .net "s1", 0 0, L_0x1e53af0; 1 drivers +v0x1cd3b80_0 .net "sum", 0 0, L_0x1e53d10; 1 drivers +S_0x1cd2990 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cd2740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e53af0/d .functor XOR 1, L_0x1e5c800, L_0x1e531c0, C4<0>, C4<0>; +L_0x1e53af0 .delay 1 (30000,30000,30000) L_0x1e53af0/d; +L_0x1e53bb0/d .functor AND 1, L_0x1e5c800, L_0x1e531c0, C4<1>, C4<1>; +L_0x1e53bb0 .delay 1 (30000,30000,30000) L_0x1e53bb0/d; +v0x1cd2bf0_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers +v0x1cd2cb0_0 .net "b", 0 0, L_0x1e531c0; alias, 1 drivers +v0x1cd2d70_0 .net "carryout", 0 0, L_0x1e53bb0; alias, 1 drivers +v0x1cd2e10_0 .net "sum", 0 0, L_0x1e53af0; alias, 1 drivers +S_0x1cd2f40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cd2740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e53d10/d .functor XOR 1, L_0x1e53af0, L_0x1e52f40, C4<0>, C4<0>; +L_0x1e53d10 .delay 1 (30000,30000,30000) L_0x1e53d10/d; +L_0x1cd39b0/d .functor AND 1, L_0x1e53af0, L_0x1e52f40, C4<1>, C4<1>; +L_0x1cd39b0 .delay 1 (30000,30000,30000) L_0x1cd39b0/d; +v0x1cd3180_0 .net "a", 0 0, L_0x1e53af0; alias, 1 drivers +v0x1cd3250_0 .net "b", 0 0, L_0x1e52f40; alias, 1 drivers +v0x1cd32f0_0 .net "carryout", 0 0, L_0x1cd39b0; alias, 1 drivers +v0x1cd33c0_0 .net "sum", 0 0, L_0x1e53d10; alias, 1 drivers +S_0x1cd4fa0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cc5230; + .timescale -9 -12; +L_0x7f72592db9f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dba40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e5c8a0/d .functor OR 1, L_0x7f72592db9f8, L_0x7f72592dba40, C4<0>, C4<0>; +L_0x1e5c8a0 .delay 1 (30000,30000,30000) L_0x1e5c8a0/d; +v0x1cd5190_0 .net/2u *"_s0", 0 0, L_0x7f72592db9f8; 1 drivers +v0x1cd5270_0 .net/2u *"_s2", 0 0, L_0x7f72592dba40; 1 drivers +S_0x1cd5350 .scope generate, "alu_slices[24]" "alu_slices[24]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1cd5560 .param/l "i" 0 3 37, +C4<011000>; +S_0x1cd5620 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cd5350; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e5cc00/d .functor NOT 1, L_0x1e66500, C4<0>, C4<0>, C4<0>; +L_0x1e5cc00 .delay 1 (10000,10000,10000) L_0x1e5cc00/d; +L_0x1e5cd10/d .functor NOT 1, L_0x1e66660, C4<0>, C4<0>, C4<0>; +L_0x1e5cd10 .delay 1 (10000,10000,10000) L_0x1e5cd10/d; +L_0x1e5dd10/d .functor XOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; +L_0x1e5dd10 .delay 1 (30000,30000,30000) L_0x1e5dd10/d; +L_0x7f72592dba88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbad0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e5e3c0/d .functor OR 1, L_0x7f72592dba88, L_0x7f72592dbad0, C4<0>, C4<0>; +L_0x1e5e3c0 .delay 1 (30000,30000,30000) L_0x1e5e3c0/d; +L_0x1e5e5c0/d .functor AND 1, L_0x1e66500, L_0x1e66660, C4<1>, C4<1>; +L_0x1e5e5c0 .delay 1 (30000,30000,30000) L_0x1e5e5c0/d; +L_0x1e5e680/d .functor NAND 1, L_0x1e66500, L_0x1e66660, C4<1>, C4<1>; +L_0x1e5e680 .delay 1 (20000,20000,20000) L_0x1e5e680/d; +L_0x1e5e7e0/d .functor XOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; +L_0x1e5e7e0 .delay 1 (20000,20000,20000) L_0x1e5e7e0/d; +L_0x1e5ec90/d .functor OR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; +L_0x1e5ec90 .delay 1 (30000,30000,30000) L_0x1e5ec90/d; +L_0x1e66400/d .functor NOT 1, L_0x1e62600, C4<0>, C4<0>, C4<0>; +L_0x1e66400 .delay 1 (10000,10000,10000) L_0x1e66400/d; +v0x1ce3d50_0 .net "A", 0 0, L_0x1e66500; 1 drivers +v0x1ce3e10_0 .net "A_", 0 0, L_0x1e5cc00; 1 drivers +v0x1ce3ed0_0 .net "B", 0 0, L_0x1e66660; 1 drivers +v0x1ce3fa0_0 .net "B_", 0 0, L_0x1e5cd10; 1 drivers +v0x1ce4040_0 .net *"_s12", 0 0, L_0x1e5e3c0; 1 drivers +v0x1ce4130_0 .net/2s *"_s14", 0 0, L_0x7f72592dba88; 1 drivers +v0x1ce41f0_0 .net/2s *"_s16", 0 0, L_0x7f72592dbad0; 1 drivers +v0x1ce42d0_0 .net *"_s18", 0 0, L_0x1e5e5c0; 1 drivers +v0x1ce43b0_0 .net *"_s20", 0 0, L_0x1e5e680; 1 drivers +v0x1ce4520_0 .net *"_s22", 0 0, L_0x1e5e7e0; 1 drivers +v0x1ce4600_0 .net *"_s24", 0 0, L_0x1e5ec90; 1 drivers +o0x7f725932d248 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1ce46e0_0 name=_s30 +o0x7f725932d278 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1ce47c0_0 name=_s32 +v0x1ce48a0_0 .net *"_s8", 0 0, L_0x1e5dd10; 1 drivers +v0x1ce4980_0 .net "carryin", 0 0, L_0x1e5c960; 1 drivers +v0x1ce4a20_0 .net "carryout", 0 0, L_0x1e660a0; 1 drivers +v0x1ce4ac0_0 .net "carryouts", 7 0, L_0x1ec1470; 1 drivers +v0x1ce4c70_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ce4d10_0 .net "result", 0 0, L_0x1e62600; 1 drivers +v0x1ce4e00_0 .net "results", 7 0, L_0x1e5ea60; 1 drivers +v0x1ce4f10_0 .net "zero", 0 0, L_0x1e66400; 1 drivers +LS_0x1e5ea60_0_0 .concat8 [ 1 1 1 1], L_0x1e5d230, L_0x1e5d860, L_0x1e5dd10, L_0x1e5e3c0; +LS_0x1e5ea60_0_4 .concat8 [ 1 1 1 1], L_0x1e5e5c0, L_0x1e5e680, L_0x1e5e7e0, L_0x1e5ec90; +L_0x1e5ea60 .concat8 [ 4 4 0 0], LS_0x1e5ea60_0_0, LS_0x1e5ea60_0_4; +LS_0x1ec1470_0_0 .concat [ 1 1 1 1], L_0x1e5d4e0, L_0x1e5dbb0, o0x7f725932d248, L_0x1e5e210; +LS_0x1ec1470_0_4 .concat [ 4 0 0 0], o0x7f725932d278; +L_0x1ec1470 .concat [ 4 4 0 0], LS_0x1ec1470_0_0, LS_0x1ec1470_0_4; +S_0x1cd58a0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cd5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e5d4e0/d .functor OR 1, L_0x1e5cfc0, L_0x1e5d380, C4<0>, C4<0>; +L_0x1e5d4e0 .delay 1 (30000,30000,30000) L_0x1e5d4e0/d; +v0x1cd66d0_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers +v0x1cd6790_0 .net "b", 0 0, L_0x1e66660; alias, 1 drivers +v0x1cd6860_0 .net "c1", 0 0, L_0x1e5cfc0; 1 drivers +v0x1cd6960_0 .net "c2", 0 0, L_0x1e5d380; 1 drivers +v0x1cd6a30_0 .net "carryin", 0 0, L_0x1e5c960; alias, 1 drivers +v0x1cd6b20_0 .net "carryout", 0 0, L_0x1e5d4e0; 1 drivers +v0x1cd6bc0_0 .net "s1", 0 0, L_0x1e5cf00; 1 drivers +v0x1cd6cb0_0 .net "sum", 0 0, L_0x1e5d230; 1 drivers +S_0x1cd5b10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cd58a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e5cf00/d .functor XOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; +L_0x1e5cf00 .delay 1 (30000,30000,30000) L_0x1e5cf00/d; +L_0x1e5cfc0/d .functor AND 1, L_0x1e66500, L_0x1e66660, C4<1>, C4<1>; +L_0x1e5cfc0 .delay 1 (30000,30000,30000) L_0x1e5cfc0/d; +v0x1cd5d70_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers +v0x1cd5e50_0 .net "b", 0 0, L_0x1e66660; alias, 1 drivers +v0x1cd5f10_0 .net "carryout", 0 0, L_0x1e5cfc0; alias, 1 drivers +v0x1cd5fb0_0 .net "sum", 0 0, L_0x1e5cf00; alias, 1 drivers +S_0x1cd60f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cd58a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e5d230/d .functor XOR 1, L_0x1e5cf00, L_0x1e5c960, C4<0>, C4<0>; +L_0x1e5d230 .delay 1 (30000,30000,30000) L_0x1e5d230/d; +L_0x1e5d380/d .functor AND 1, L_0x1e5cf00, L_0x1e5c960, C4<1>, C4<1>; +L_0x1e5d380 .delay 1 (30000,30000,30000) L_0x1e5d380/d; +v0x1cd6350_0 .net "a", 0 0, L_0x1e5cf00; alias, 1 drivers +v0x1cd63f0_0 .net "b", 0 0, L_0x1e5c960; alias, 1 drivers +v0x1cd6490_0 .net "carryout", 0 0, L_0x1e5d380; alias, 1 drivers +v0x1cd6560_0 .net "sum", 0 0, L_0x1e5d230; alias, 1 drivers +S_0x1cd6d80 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cd5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cdc170_0 .net "ands", 7 0, L_0x1e640a0; 1 drivers +v0x1cdc280_0 .net "in", 7 0, L_0x1ec1470; alias, 1 drivers +v0x1cdc340_0 .net "out", 0 0, L_0x1e660a0; alias, 1 drivers +v0x1cdc410_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cd6fa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cd6d80; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cd96d0_0 .net "A", 7 0, L_0x1ec1470; alias, 1 drivers +v0x1cd97d0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cd9890_0 .net *"_s0", 0 0, L_0x1e62960; 1 drivers +v0x1cd9950_0 .net *"_s12", 0 0, L_0x1e632d0; 1 drivers +v0x1cd9a30_0 .net *"_s16", 0 0, L_0x1e63630; 1 drivers +v0x1cd9b60_0 .net *"_s20", 0 0, L_0x1e63940; 1 drivers +v0x1cd9c40_0 .net *"_s24", 0 0, L_0x1e63d30; 1 drivers +v0x1cd9d20_0 .net *"_s28", 0 0, L_0x1e63cc0; 1 drivers +v0x1cd9e00_0 .net *"_s4", 0 0, L_0x1e62c70; 1 drivers +v0x1cd9f70_0 .net *"_s8", 0 0, L_0x1e62fc0; 1 drivers +v0x1cda050_0 .net "out", 7 0, L_0x1e640a0; alias, 1 drivers +L_0x1e62a20 .part L_0x1ec1470, 0, 1; +L_0x1e62b80 .part v0x1d6daa0_0, 0, 1; +L_0x1e62d30 .part L_0x1ec1470, 1, 1; +L_0x1e62f20 .part v0x1d6daa0_0, 1, 1; +L_0x1e63080 .part L_0x1ec1470, 2, 1; +L_0x1e631e0 .part v0x1d6daa0_0, 2, 1; +L_0x1e63390 .part L_0x1ec1470, 3, 1; +L_0x1e634f0 .part v0x1d6daa0_0, 3, 1; +L_0x1e636f0 .part L_0x1ec1470, 4, 1; +L_0x1e63850 .part v0x1d6daa0_0, 4, 1; +L_0x1e639b0 .part L_0x1ec1470, 5, 1; +L_0x1e63c20 .part v0x1d6daa0_0, 5, 1; +L_0x1e63e50 .part L_0x1ec1470, 6, 1; +L_0x1e63fb0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e640a0_0_0 .concat8 [ 1 1 1 1], L_0x1e62960, L_0x1e62c70, L_0x1e62fc0, L_0x1e632d0; +LS_0x1e640a0_0_4 .concat8 [ 1 1 1 1], L_0x1e63630, L_0x1e63940, L_0x1e63d30, L_0x1e63cc0; +L_0x1e640a0 .concat8 [ 4 4 0 0], LS_0x1e640a0_0_0, LS_0x1e640a0_0_4; +L_0x1e64460 .part L_0x1ec1470, 7, 1; +L_0x1e64650 .part v0x1d6daa0_0, 7, 1; +S_0x1cd7200 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd7410 .param/l "i" 0 4 54, +C4<00>; +L_0x1e62960/d .functor AND 1, L_0x1e62a20, L_0x1e62b80, C4<1>, C4<1>; +L_0x1e62960 .delay 1 (30000,30000,30000) L_0x1e62960/d; +v0x1cd74f0_0 .net *"_s0", 0 0, L_0x1e62a20; 1 drivers +v0x1cd75d0_0 .net *"_s1", 0 0, L_0x1e62b80; 1 drivers +S_0x1cd76b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd78c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e62c70/d .functor AND 1, L_0x1e62d30, L_0x1e62f20, C4<1>, C4<1>; +L_0x1e62c70 .delay 1 (30000,30000,30000) L_0x1e62c70/d; +v0x1cd7980_0 .net *"_s0", 0 0, L_0x1e62d30; 1 drivers +v0x1cd7a60_0 .net *"_s1", 0 0, L_0x1e62f20; 1 drivers +S_0x1cd7b40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd7d50 .param/l "i" 0 4 54, +C4<010>; +L_0x1e62fc0/d .functor AND 1, L_0x1e63080, L_0x1e631e0, C4<1>, C4<1>; +L_0x1e62fc0 .delay 1 (30000,30000,30000) L_0x1e62fc0/d; +v0x1cd7df0_0 .net *"_s0", 0 0, L_0x1e63080; 1 drivers +v0x1cd7ed0_0 .net *"_s1", 0 0, L_0x1e631e0; 1 drivers +S_0x1cd7fb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd81c0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e632d0/d .functor AND 1, L_0x1e63390, L_0x1e634f0, C4<1>, C4<1>; +L_0x1e632d0 .delay 1 (30000,30000,30000) L_0x1e632d0/d; +v0x1cd8280_0 .net *"_s0", 0 0, L_0x1e63390; 1 drivers +v0x1cd8360_0 .net *"_s1", 0 0, L_0x1e634f0; 1 drivers +S_0x1cd8440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd86a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e63630/d .functor AND 1, L_0x1e636f0, L_0x1e63850, C4<1>, C4<1>; +L_0x1e63630 .delay 1 (30000,30000,30000) L_0x1e63630/d; +v0x1cd8760_0 .net *"_s0", 0 0, L_0x1e636f0; 1 drivers +v0x1cd8840_0 .net *"_s1", 0 0, L_0x1e63850; 1 drivers +S_0x1cd8920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd8b30 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e63940/d .functor AND 1, L_0x1e639b0, L_0x1e63c20, C4<1>, C4<1>; +L_0x1e63940 .delay 1 (30000,30000,30000) L_0x1e63940/d; +v0x1cd8bf0_0 .net *"_s0", 0 0, L_0x1e639b0; 1 drivers +v0x1cd8cd0_0 .net *"_s1", 0 0, L_0x1e63c20; 1 drivers +S_0x1cd8db0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd8fc0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e63d30/d .functor AND 1, L_0x1e63e50, L_0x1e63fb0, C4<1>, C4<1>; +L_0x1e63d30 .delay 1 (30000,30000,30000) L_0x1e63d30/d; +v0x1cd9080_0 .net *"_s0", 0 0, L_0x1e63e50; 1 drivers +v0x1cd9160_0 .net *"_s1", 0 0, L_0x1e63fb0; 1 drivers +S_0x1cd9240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cd6fa0; + .timescale -9 -12; +P_0x1cd9450 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e63cc0/d .functor AND 1, L_0x1e64460, L_0x1e64650, C4<1>, C4<1>; +L_0x1e63cc0 .delay 1 (30000,30000,30000) L_0x1e63cc0/d; +v0x1cd9510_0 .net *"_s0", 0 0, L_0x1e64460; 1 drivers +v0x1cd95f0_0 .net *"_s1", 0 0, L_0x1e64650; 1 drivers +S_0x1cda1b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cd6d80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e660a0/d .functor OR 1, L_0x1e66160, L_0x1e66310, C4<0>, C4<0>; +L_0x1e660a0 .delay 1 (30000,30000,30000) L_0x1e660a0/d; +v0x1cdbd00_0 .net *"_s10", 0 0, L_0x1e66160; 1 drivers +v0x1cdbde0_0 .net *"_s12", 0 0, L_0x1e66310; 1 drivers +v0x1cdbec0_0 .net "in", 7 0, L_0x1e640a0; alias, 1 drivers +v0x1cdbf90_0 .net "ors", 1 0, L_0x1e65ec0; 1 drivers +v0x1cdc050_0 .net "out", 0 0, L_0x1e660a0; alias, 1 drivers +L_0x1e65290 .part L_0x1e640a0, 0, 4; +L_0x1e65ec0 .concat8 [ 1 1 0 0], L_0x1e64f80, L_0x1e65bb0; +L_0x1e66000 .part L_0x1e640a0, 4, 4; +L_0x1e66160 .part L_0x1e65ec0, 0, 1; +L_0x1e66310 .part L_0x1e65ec0, 1, 1; +S_0x1cda370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cda1b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e64740/d .functor OR 1, L_0x1e64800, L_0x1e64960, C4<0>, C4<0>; +L_0x1e64740 .delay 1 (30000,30000,30000) L_0x1e64740/d; +L_0x1e64b90/d .functor OR 1, L_0x1e64ca0, L_0x1e64e00, C4<0>, C4<0>; +L_0x1e64b90 .delay 1 (30000,30000,30000) L_0x1e64b90/d; +L_0x1e64f80/d .functor OR 1, L_0x1e64ff0, L_0x1e651a0, C4<0>, C4<0>; +L_0x1e64f80 .delay 1 (30000,30000,30000) L_0x1e64f80/d; +v0x1cda5c0_0 .net *"_s0", 0 0, L_0x1e64740; 1 drivers +v0x1cda6c0_0 .net *"_s10", 0 0, L_0x1e64ca0; 1 drivers +v0x1cda7a0_0 .net *"_s12", 0 0, L_0x1e64e00; 1 drivers +v0x1cda860_0 .net *"_s14", 0 0, L_0x1e64ff0; 1 drivers +v0x1cda940_0 .net *"_s16", 0 0, L_0x1e651a0; 1 drivers +v0x1cdaa70_0 .net *"_s3", 0 0, L_0x1e64800; 1 drivers +v0x1cdab50_0 .net *"_s5", 0 0, L_0x1e64960; 1 drivers +v0x1cdac30_0 .net *"_s6", 0 0, L_0x1e64b90; 1 drivers +v0x1cdad10_0 .net "in", 3 0, L_0x1e65290; 1 drivers +v0x1cdae80_0 .net "ors", 1 0, L_0x1e64aa0; 1 drivers +v0x1cdaf60_0 .net "out", 0 0, L_0x1e64f80; 1 drivers +L_0x1e64800 .part L_0x1e65290, 0, 1; +L_0x1e64960 .part L_0x1e65290, 1, 1; +L_0x1e64aa0 .concat8 [ 1 1 0 0], L_0x1e64740, L_0x1e64b90; +L_0x1e64ca0 .part L_0x1e65290, 2, 1; +L_0x1e64e00 .part L_0x1e65290, 3, 1; +L_0x1e64ff0 .part L_0x1e64aa0, 0, 1; +L_0x1e651a0 .part L_0x1e64aa0, 1, 1; +S_0x1cdb080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cda1b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e653c0/d .functor OR 1, L_0x1e65430, L_0x1e65590, C4<0>, C4<0>; +L_0x1e653c0 .delay 1 (30000,30000,30000) L_0x1e653c0/d; +L_0x1e657c0/d .functor OR 1, L_0x1e658d0, L_0x1e65a30, C4<0>, C4<0>; +L_0x1e657c0 .delay 1 (30000,30000,30000) L_0x1e657c0/d; +L_0x1e65bb0/d .functor OR 1, L_0x1e65c20, L_0x1e65dd0, C4<0>, C4<0>; +L_0x1e65bb0 .delay 1 (30000,30000,30000) L_0x1e65bb0/d; +v0x1cdb240_0 .net *"_s0", 0 0, L_0x1e653c0; 1 drivers +v0x1cdb340_0 .net *"_s10", 0 0, L_0x1e658d0; 1 drivers +v0x1cdb420_0 .net *"_s12", 0 0, L_0x1e65a30; 1 drivers +v0x1cdb4e0_0 .net *"_s14", 0 0, L_0x1e65c20; 1 drivers +v0x1cdb5c0_0 .net *"_s16", 0 0, L_0x1e65dd0; 1 drivers +v0x1cdb6f0_0 .net *"_s3", 0 0, L_0x1e65430; 1 drivers +v0x1cdb7d0_0 .net *"_s5", 0 0, L_0x1e65590; 1 drivers +v0x1cdb8b0_0 .net *"_s6", 0 0, L_0x1e657c0; 1 drivers +v0x1cdb990_0 .net "in", 3 0, L_0x1e66000; 1 drivers +v0x1cdbb00_0 .net "ors", 1 0, L_0x1e656d0; 1 drivers +v0x1cdbbe0_0 .net "out", 0 0, L_0x1e65bb0; 1 drivers +L_0x1e65430 .part L_0x1e66000, 0, 1; +L_0x1e65590 .part L_0x1e66000, 1, 1; +L_0x1e656d0 .concat8 [ 1 1 0 0], L_0x1e653c0, L_0x1e657c0; +L_0x1e658d0 .part L_0x1e66000, 2, 1; +L_0x1e65a30 .part L_0x1e66000, 3, 1; +L_0x1e65c20 .part L_0x1e656d0, 0, 1; +L_0x1e65dd0 .part L_0x1e656d0, 1, 1; +S_0x1cdc4f0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cd5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1ce1920_0 .net "ands", 7 0, L_0x1e60600; 1 drivers +v0x1ce1a30_0 .net "in", 7 0, L_0x1e5ea60; alias, 1 drivers +v0x1ce1af0_0 .net "out", 0 0, L_0x1e62600; alias, 1 drivers +v0x1ce1bc0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cdc740 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cdc4f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cdee80_0 .net "A", 7 0, L_0x1e5ea60; alias, 1 drivers +v0x1cdef80_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cdf040_0 .net *"_s0", 0 0, L_0x1e5edf0; 1 drivers +v0x1cdf100_0 .net *"_s12", 0 0, L_0x1e5f7b0; 1 drivers +v0x1cdf1e0_0 .net *"_s16", 0 0, L_0x1e5fb10; 1 drivers +v0x1cdf310_0 .net *"_s20", 0 0, L_0x1e5ff40; 1 drivers +v0x1cdf3f0_0 .net *"_s24", 0 0, L_0x1e60270; 1 drivers +v0x1cdf4d0_0 .net *"_s28", 0 0, L_0x1e60200; 1 drivers +v0x1cdf5b0_0 .net *"_s4", 0 0, L_0x1e5f190; 1 drivers +v0x1cdf720_0 .net *"_s8", 0 0, L_0x1e5f4a0; 1 drivers +v0x1cdf800_0 .net "out", 7 0, L_0x1e60600; alias, 1 drivers +L_0x1e5ef00 .part L_0x1e5ea60, 0, 1; +L_0x1e5f0f0 .part v0x1d6daa0_0, 0, 1; +L_0x1e5f250 .part L_0x1e5ea60, 1, 1; +L_0x1e5f3b0 .part v0x1d6daa0_0, 1, 1; +L_0x1e5f560 .part L_0x1e5ea60, 2, 1; +L_0x1e5f6c0 .part v0x1d6daa0_0, 2, 1; +L_0x1e5f870 .part L_0x1e5ea60, 3, 1; +L_0x1e5f9d0 .part v0x1d6daa0_0, 3, 1; +L_0x1e5fbd0 .part L_0x1e5ea60, 4, 1; +L_0x1e5fe40 .part v0x1d6daa0_0, 4, 1; +L_0x1e5ffb0 .part L_0x1e5ea60, 5, 1; +L_0x1e60110 .part v0x1d6daa0_0, 5, 1; +L_0x1e60330 .part L_0x1e5ea60, 6, 1; +L_0x1e60490 .part v0x1d6daa0_0, 6, 1; +LS_0x1e60600_0_0 .concat8 [ 1 1 1 1], L_0x1e5edf0, L_0x1e5f190, L_0x1e5f4a0, L_0x1e5f7b0; +LS_0x1e60600_0_4 .concat8 [ 1 1 1 1], L_0x1e5fb10, L_0x1e5ff40, L_0x1e60270, L_0x1e60200; +L_0x1e60600 .concat8 [ 4 4 0 0], LS_0x1e60600_0_0, LS_0x1e60600_0_4; +L_0x1e609c0 .part L_0x1e5ea60, 7, 1; +L_0x1e60bb0 .part v0x1d6daa0_0, 7, 1; +S_0x1cdc980 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cdcb90 .param/l "i" 0 4 54, +C4<00>; +L_0x1e5edf0/d .functor AND 1, L_0x1e5ef00, L_0x1e5f0f0, C4<1>, C4<1>; +L_0x1e5edf0 .delay 1 (30000,30000,30000) L_0x1e5edf0/d; +v0x1cdcc70_0 .net *"_s0", 0 0, L_0x1e5ef00; 1 drivers +v0x1cdcd50_0 .net *"_s1", 0 0, L_0x1e5f0f0; 1 drivers +S_0x1cdce30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cdd040 .param/l "i" 0 4 54, +C4<01>; +L_0x1e5f190/d .functor AND 1, L_0x1e5f250, L_0x1e5f3b0, C4<1>, C4<1>; +L_0x1e5f190 .delay 1 (30000,30000,30000) L_0x1e5f190/d; +v0x1cdd100_0 .net *"_s0", 0 0, L_0x1e5f250; 1 drivers +v0x1cdd1e0_0 .net *"_s1", 0 0, L_0x1e5f3b0; 1 drivers +S_0x1cdd2c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cdd500 .param/l "i" 0 4 54, +C4<010>; +L_0x1e5f4a0/d .functor AND 1, L_0x1e5f560, L_0x1e5f6c0, C4<1>, C4<1>; +L_0x1e5f4a0 .delay 1 (30000,30000,30000) L_0x1e5f4a0/d; +v0x1cdd5a0_0 .net *"_s0", 0 0, L_0x1e5f560; 1 drivers +v0x1cdd680_0 .net *"_s1", 0 0, L_0x1e5f6c0; 1 drivers +S_0x1cdd760 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cdd970 .param/l "i" 0 4 54, +C4<011>; +L_0x1e5f7b0/d .functor AND 1, L_0x1e5f870, L_0x1e5f9d0, C4<1>, C4<1>; +L_0x1e5f7b0 .delay 1 (30000,30000,30000) L_0x1e5f7b0/d; +v0x1cdda30_0 .net *"_s0", 0 0, L_0x1e5f870; 1 drivers +v0x1cddb10_0 .net *"_s1", 0 0, L_0x1e5f9d0; 1 drivers +S_0x1cddbf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cdde50 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e5fb10/d .functor AND 1, L_0x1e5fbd0, L_0x1e5fe40, C4<1>, C4<1>; +L_0x1e5fb10 .delay 1 (30000,30000,30000) L_0x1e5fb10/d; +v0x1cddf10_0 .net *"_s0", 0 0, L_0x1e5fbd0; 1 drivers +v0x1cddff0_0 .net *"_s1", 0 0, L_0x1e5fe40; 1 drivers +S_0x1cde0d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cde2e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e5ff40/d .functor AND 1, L_0x1e5ffb0, L_0x1e60110, C4<1>, C4<1>; +L_0x1e5ff40 .delay 1 (30000,30000,30000) L_0x1e5ff40/d; +v0x1cde3a0_0 .net *"_s0", 0 0, L_0x1e5ffb0; 1 drivers +v0x1cde480_0 .net *"_s1", 0 0, L_0x1e60110; 1 drivers +S_0x1cde560 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cde770 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e60270/d .functor AND 1, L_0x1e60330, L_0x1e60490, C4<1>, C4<1>; +L_0x1e60270 .delay 1 (30000,30000,30000) L_0x1e60270/d; +v0x1cde830_0 .net *"_s0", 0 0, L_0x1e60330; 1 drivers +v0x1cde910_0 .net *"_s1", 0 0, L_0x1e60490; 1 drivers +S_0x1cde9f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cdc740; + .timescale -9 -12; +P_0x1cdec00 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e60200/d .functor AND 1, L_0x1e609c0, L_0x1e60bb0, C4<1>, C4<1>; +L_0x1e60200 .delay 1 (30000,30000,30000) L_0x1e60200/d; +v0x1cdecc0_0 .net *"_s0", 0 0, L_0x1e609c0; 1 drivers +v0x1cdeda0_0 .net *"_s1", 0 0, L_0x1e60bb0; 1 drivers +S_0x1cdf960 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cdc4f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e62600/d .functor OR 1, L_0x1e626c0, L_0x1e62870, C4<0>, C4<0>; +L_0x1e62600 .delay 1 (30000,30000,30000) L_0x1e62600/d; +v0x1ce14b0_0 .net *"_s10", 0 0, L_0x1e626c0; 1 drivers +v0x1ce1590_0 .net *"_s12", 0 0, L_0x1e62870; 1 drivers +v0x1ce1670_0 .net "in", 7 0, L_0x1e60600; alias, 1 drivers +v0x1ce1740_0 .net "ors", 1 0, L_0x1e62420; 1 drivers +v0x1ce1800_0 .net "out", 0 0, L_0x1e62600; alias, 1 drivers +L_0x1e617f0 .part L_0x1e60600, 0, 4; +L_0x1e62420 .concat8 [ 1 1 0 0], L_0x1e614e0, L_0x1e62110; +L_0x1e62560 .part L_0x1e60600, 4, 4; +L_0x1e626c0 .part L_0x1e62420, 0, 1; +L_0x1e62870 .part L_0x1e62420, 1, 1; +S_0x1cdfb20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cdf960; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e60ca0/d .functor OR 1, L_0x1e60d60, L_0x1e60ec0, C4<0>, C4<0>; +L_0x1e60ca0 .delay 1 (30000,30000,30000) L_0x1e60ca0/d; +L_0x1e610f0/d .functor OR 1, L_0x1e61200, L_0x1e61360, C4<0>, C4<0>; +L_0x1e610f0 .delay 1 (30000,30000,30000) L_0x1e610f0/d; +L_0x1e614e0/d .functor OR 1, L_0x1e61550, L_0x1e61700, C4<0>, C4<0>; +L_0x1e614e0 .delay 1 (30000,30000,30000) L_0x1e614e0/d; +v0x1cdfd70_0 .net *"_s0", 0 0, L_0x1e60ca0; 1 drivers +v0x1cdfe70_0 .net *"_s10", 0 0, L_0x1e61200; 1 drivers +v0x1cdff50_0 .net *"_s12", 0 0, L_0x1e61360; 1 drivers +v0x1ce0010_0 .net *"_s14", 0 0, L_0x1e61550; 1 drivers +v0x1ce00f0_0 .net *"_s16", 0 0, L_0x1e61700; 1 drivers +v0x1ce0220_0 .net *"_s3", 0 0, L_0x1e60d60; 1 drivers +v0x1ce0300_0 .net *"_s5", 0 0, L_0x1e60ec0; 1 drivers +v0x1ce03e0_0 .net *"_s6", 0 0, L_0x1e610f0; 1 drivers +v0x1ce04c0_0 .net "in", 3 0, L_0x1e617f0; 1 drivers +v0x1ce0630_0 .net "ors", 1 0, L_0x1e61000; 1 drivers +v0x1ce0710_0 .net "out", 0 0, L_0x1e614e0; 1 drivers +L_0x1e60d60 .part L_0x1e617f0, 0, 1; +L_0x1e60ec0 .part L_0x1e617f0, 1, 1; +L_0x1e61000 .concat8 [ 1 1 0 0], L_0x1e60ca0, L_0x1e610f0; +L_0x1e61200 .part L_0x1e617f0, 2, 1; +L_0x1e61360 .part L_0x1e617f0, 3, 1; +L_0x1e61550 .part L_0x1e61000, 0, 1; +L_0x1e61700 .part L_0x1e61000, 1, 1; +S_0x1ce0830 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cdf960; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e61920/d .functor OR 1, L_0x1e61990, L_0x1e61af0, C4<0>, C4<0>; +L_0x1e61920 .delay 1 (30000,30000,30000) L_0x1e61920/d; +L_0x1e61d20/d .functor OR 1, L_0x1e61e30, L_0x1e61f90, C4<0>, C4<0>; +L_0x1e61d20 .delay 1 (30000,30000,30000) L_0x1e61d20/d; +L_0x1e62110/d .functor OR 1, L_0x1e62180, L_0x1e62330, C4<0>, C4<0>; +L_0x1e62110 .delay 1 (30000,30000,30000) L_0x1e62110/d; +v0x1ce09f0_0 .net *"_s0", 0 0, L_0x1e61920; 1 drivers +v0x1ce0af0_0 .net *"_s10", 0 0, L_0x1e61e30; 1 drivers +v0x1ce0bd0_0 .net *"_s12", 0 0, L_0x1e61f90; 1 drivers +v0x1ce0c90_0 .net *"_s14", 0 0, L_0x1e62180; 1 drivers +v0x1ce0d70_0 .net *"_s16", 0 0, L_0x1e62330; 1 drivers +v0x1ce0ea0_0 .net *"_s3", 0 0, L_0x1e61990; 1 drivers +v0x1ce0f80_0 .net *"_s5", 0 0, L_0x1e61af0; 1 drivers +v0x1ce1060_0 .net *"_s6", 0 0, L_0x1e61d20; 1 drivers +v0x1ce1140_0 .net "in", 3 0, L_0x1e62560; 1 drivers +v0x1ce12b0_0 .net "ors", 1 0, L_0x1e61c30; 1 drivers +v0x1ce1390_0 .net "out", 0 0, L_0x1e62110; 1 drivers +L_0x1e61990 .part L_0x1e62560, 0, 1; +L_0x1e61af0 .part L_0x1e62560, 1, 1; +L_0x1e61c30 .concat8 [ 1 1 0 0], L_0x1e61920, L_0x1e61d20; +L_0x1e61e30 .part L_0x1e62560, 2, 1; +L_0x1e61f90 .part L_0x1e62560, 3, 1; +L_0x1e62180 .part L_0x1e61c30, 0, 1; +L_0x1e62330 .part L_0x1e61c30, 1, 1; +S_0x1ce1ca0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cd5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e5ddd0/d .functor XNOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; +L_0x1e5ddd0 .delay 1 (20000,20000,20000) L_0x1e5ddd0/d; +L_0x1e5e040/d .functor AND 1, L_0x1e66500, L_0x1e5cd10, C4<1>, C4<1>; +L_0x1e5e040 .delay 1 (30000,30000,30000) L_0x1e5e040/d; +L_0x1e5e0b0/d .functor AND 1, L_0x1e5ddd0, L_0x1e5c960, C4<1>, C4<1>; +L_0x1e5e0b0 .delay 1 (30000,30000,30000) L_0x1e5e0b0/d; +L_0x1e5e210/d .functor OR 1, L_0x1e5e0b0, L_0x1e5e040, C4<0>, C4<0>; +L_0x1e5e210 .delay 1 (30000,30000,30000) L_0x1e5e210/d; +v0x1ce1f50_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers +v0x1ce2040_0 .net "a_", 0 0, L_0x1e5cc00; alias, 1 drivers +v0x1ce2100_0 .net "b", 0 0, L_0x1e66660; alias, 1 drivers +v0x1ce21f0_0 .net "b_", 0 0, L_0x1e5cd10; alias, 1 drivers +v0x1ce2290_0 .net "carryin", 0 0, L_0x1e5c960; alias, 1 drivers +v0x1ce23d0_0 .net "eq", 0 0, L_0x1e5ddd0; 1 drivers +v0x1ce2490_0 .net "lt", 0 0, L_0x1e5e040; 1 drivers +v0x1ce2550_0 .net "out", 0 0, L_0x1e5e210; 1 drivers +v0x1ce2610_0 .net "w0", 0 0, L_0x1e5e0b0; 1 drivers +S_0x1ce2860 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cd5620; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e5dbb0/d .functor OR 1, L_0x1e5d700, L_0x1ce3ac0, C4<0>, C4<0>; +L_0x1e5dbb0 .delay 1 (30000,30000,30000) L_0x1e5dbb0/d; +v0x1ce3650_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers +v0x1ce37a0_0 .net "b", 0 0, L_0x1e5cd10; alias, 1 drivers +v0x1ce3860_0 .net "c1", 0 0, L_0x1e5d700; 1 drivers +v0x1ce3900_0 .net "c2", 0 0, L_0x1ce3ac0; 1 drivers +v0x1ce39d0_0 .net "carryin", 0 0, L_0x1e5c960; alias, 1 drivers +v0x1ce3b50_0 .net "carryout", 0 0, L_0x1e5dbb0; 1 drivers +v0x1ce3bf0_0 .net "s1", 0 0, L_0x1e5d640; 1 drivers +v0x1ce3c90_0 .net "sum", 0 0, L_0x1e5d860; 1 drivers +S_0x1ce2ab0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ce2860; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e5d640/d .functor XOR 1, L_0x1e66500, L_0x1e5cd10, C4<0>, C4<0>; +L_0x1e5d640 .delay 1 (30000,30000,30000) L_0x1e5d640/d; +L_0x1e5d700/d .functor AND 1, L_0x1e66500, L_0x1e5cd10, C4<1>, C4<1>; +L_0x1e5d700 .delay 1 (30000,30000,30000) L_0x1e5d700/d; +v0x1ce2d10_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers +v0x1ce2dd0_0 .net "b", 0 0, L_0x1e5cd10; alias, 1 drivers +v0x1ce2e90_0 .net "carryout", 0 0, L_0x1e5d700; alias, 1 drivers +v0x1ce2f30_0 .net "sum", 0 0, L_0x1e5d640; alias, 1 drivers +S_0x1ce3060 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ce2860; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e5d860/d .functor XOR 1, L_0x1e5d640, L_0x1e5c960, C4<0>, C4<0>; +L_0x1e5d860 .delay 1 (30000,30000,30000) L_0x1e5d860/d; +L_0x1ce3ac0/d .functor AND 1, L_0x1e5d640, L_0x1e5c960, C4<1>, C4<1>; +L_0x1ce3ac0 .delay 1 (30000,30000,30000) L_0x1ce3ac0/d; +v0x1ce32c0_0 .net "a", 0 0, L_0x1e5d640; alias, 1 drivers +v0x1ce3390_0 .net "b", 0 0, L_0x1e5c960; alias, 1 drivers +v0x1ce3430_0 .net "carryout", 0 0, L_0x1ce3ac0; alias, 1 drivers +v0x1ce3500_0 .net "sum", 0 0, L_0x1e5d860; alias, 1 drivers +S_0x1ce50b0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cd5350; + .timescale -9 -12; +L_0x7f72592dbb18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbb60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e665a0/d .functor OR 1, L_0x7f72592dbb18, L_0x7f72592dbb60, C4<0>, C4<0>; +L_0x1e665a0 .delay 1 (30000,30000,30000) L_0x1e665a0/d; +v0x1ce52a0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbb18; 1 drivers +v0x1ce5380_0 .net/2u *"_s2", 0 0, L_0x7f72592dbb60; 1 drivers +S_0x1ce5460 .scope generate, "alu_slices[25]" "alu_slices[25]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1ce5670 .param/l "i" 0 3 37, +C4<011001>; +S_0x1ce5730 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ce5460; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e5caf0/d .functor NOT 1, L_0x1e70190, C4<0>, C4<0>, C4<0>; +L_0x1e5caf0 .delay 1 (10000,10000,10000) L_0x1e5caf0/d; +L_0x1e66a00/d .functor NOT 1, L_0x1e66700, C4<0>, C4<0>, C4<0>; +L_0x1e66a00 .delay 1 (10000,10000,10000) L_0x1e66a00/d; +L_0x1e67940/d .functor XOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; +L_0x1e67940 .delay 1 (30000,30000,30000) L_0x1e67940/d; +L_0x7f72592dbba8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbbf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e67ff0/d .functor OR 1, L_0x7f72592dbba8, L_0x7f72592dbbf0, C4<0>, C4<0>; +L_0x1e67ff0 .delay 1 (30000,30000,30000) L_0x1e67ff0/d; +L_0x1e681f0/d .functor AND 1, L_0x1e70190, L_0x1e66700, C4<1>, C4<1>; +L_0x1e681f0 .delay 1 (30000,30000,30000) L_0x1e681f0/d; +L_0x1e682b0/d .functor NAND 1, L_0x1e70190, L_0x1e66700, C4<1>, C4<1>; +L_0x1e682b0 .delay 1 (20000,20000,20000) L_0x1e682b0/d; +L_0x1e68410/d .functor XOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; +L_0x1e68410 .delay 1 (20000,20000,20000) L_0x1e68410/d; +L_0x1e688c0/d .functor OR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; +L_0x1e688c0 .delay 1 (30000,30000,30000) L_0x1e688c0/d; +L_0x1e70090/d .functor NOT 1, L_0x1e6c230, C4<0>, C4<0>, C4<0>; +L_0x1e70090 .delay 1 (10000,10000,10000) L_0x1e70090/d; +v0x1cf4620_0 .net "A", 0 0, L_0x1e70190; 1 drivers +v0x1cf46e0_0 .net "A_", 0 0, L_0x1e5caf0; 1 drivers +v0x1cf47a0_0 .net "B", 0 0, L_0x1e66700; 1 drivers +v0x1cf4870_0 .net "B_", 0 0, L_0x1e66a00; 1 drivers +v0x1cf4910_0 .net *"_s12", 0 0, L_0x1e67ff0; 1 drivers +v0x1cf4a00_0 .net/2s *"_s14", 0 0, L_0x7f72592dbba8; 1 drivers +v0x1cf4ac0_0 .net/2s *"_s16", 0 0, L_0x7f72592dbbf0; 1 drivers +v0x1cf4ba0_0 .net *"_s18", 0 0, L_0x1e681f0; 1 drivers +v0x1cf4c80_0 .net *"_s20", 0 0, L_0x1e682b0; 1 drivers +v0x1cf4df0_0 .net *"_s22", 0 0, L_0x1e68410; 1 drivers +v0x1cf4ed0_0 .net *"_s24", 0 0, L_0x1e688c0; 1 drivers +o0x7f725932f798 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1cf4fb0_0 name=_s30 +o0x7f725932f7c8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1cf5090_0 name=_s32 +v0x1cf5170_0 .net *"_s8", 0 0, L_0x1e67940; 1 drivers +v0x1cf5250_0 .net "carryin", 0 0, L_0x1e667a0; 1 drivers +v0x1cf52f0_0 .net "carryout", 0 0, L_0x1e6fd30; 1 drivers +v0x1cf5390_0 .net "carryouts", 7 0, L_0x1ec1640; 1 drivers +v0x1cf5540_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cf55e0_0 .net "result", 0 0, L_0x1e6c230; 1 drivers +v0x1cf56d0_0 .net "results", 7 0, L_0x1e68690; 1 drivers +v0x1cf57e0_0 .net "zero", 0 0, L_0x1e70090; 1 drivers +LS_0x1e68690_0_0 .concat8 [ 1 1 1 1], L_0x1e66e60, L_0x1e67490, L_0x1e67940, L_0x1e67ff0; +LS_0x1e68690_0_4 .concat8 [ 1 1 1 1], L_0x1e681f0, L_0x1e682b0, L_0x1e68410, L_0x1e688c0; +L_0x1e68690 .concat8 [ 4 4 0 0], LS_0x1e68690_0_0, LS_0x1e68690_0_4; +LS_0x1ec1640_0_0 .concat [ 1 1 1 1], L_0x1e67110, L_0x1e677e0, o0x7f725932f798, L_0x1e67e40; +LS_0x1ec1640_0_4 .concat [ 4 0 0 0], o0x7f725932f7c8; +L_0x1ec1640 .concat [ 4 4 0 0], LS_0x1ec1640_0_0, LS_0x1ec1640_0_4; +S_0x1ce59b0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1ce5730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e67110/d .functor OR 1, L_0x1e66bf0, L_0x1e66fb0, C4<0>, C4<0>; +L_0x1e67110 .delay 1 (30000,30000,30000) L_0x1e67110/d; +v0x1ce67e0_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers +v0x1ce68a0_0 .net "b", 0 0, L_0x1e66700; alias, 1 drivers +v0x1ce6970_0 .net "c1", 0 0, L_0x1e66bf0; 1 drivers +v0x1ce6a70_0 .net "c2", 0 0, L_0x1e66fb0; 1 drivers +v0x1ce6b40_0 .net "carryin", 0 0, L_0x1e667a0; alias, 1 drivers +v0x1ce6c30_0 .net "carryout", 0 0, L_0x1e67110; 1 drivers +v0x1ce6cd0_0 .net "s1", 0 0, L_0x1e60580; 1 drivers +v0x1ce6dc0_0 .net "sum", 0 0, L_0x1e66e60; 1 drivers +S_0x1ce5c20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ce59b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e60580/d .functor XOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; +L_0x1e60580 .delay 1 (30000,30000,30000) L_0x1e60580/d; +L_0x1e66bf0/d .functor AND 1, L_0x1e70190, L_0x1e66700, C4<1>, C4<1>; +L_0x1e66bf0 .delay 1 (30000,30000,30000) L_0x1e66bf0/d; +v0x1ce5e80_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers +v0x1ce5f60_0 .net "b", 0 0, L_0x1e66700; alias, 1 drivers +v0x1ce6020_0 .net "carryout", 0 0, L_0x1e66bf0; alias, 1 drivers +v0x1ce60c0_0 .net "sum", 0 0, L_0x1e60580; alias, 1 drivers +S_0x1ce6200 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ce59b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e66e60/d .functor XOR 1, L_0x1e60580, L_0x1e667a0, C4<0>, C4<0>; +L_0x1e66e60 .delay 1 (30000,30000,30000) L_0x1e66e60/d; +L_0x1e66fb0/d .functor AND 1, L_0x1e60580, L_0x1e667a0, C4<1>, C4<1>; +L_0x1e66fb0 .delay 1 (30000,30000,30000) L_0x1e66fb0/d; +v0x1ce6460_0 .net "a", 0 0, L_0x1e60580; alias, 1 drivers +v0x1ce6500_0 .net "b", 0 0, L_0x1e667a0; alias, 1 drivers +v0x1ce65a0_0 .net "carryout", 0 0, L_0x1e66fb0; alias, 1 drivers +v0x1ce6670_0 .net "sum", 0 0, L_0x1e66e60; alias, 1 drivers +S_0x1ce6e90 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1ce5730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cec280_0 .net "ands", 7 0, L_0x1e6dd30; 1 drivers +v0x1cec390_0 .net "in", 7 0, L_0x1ec1640; alias, 1 drivers +v0x1cec450_0 .net "out", 0 0, L_0x1e6fd30; alias, 1 drivers +v0x1cec520_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1ce70b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ce6e90; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1ce97e0_0 .net "A", 7 0, L_0x1ec1640; alias, 1 drivers +v0x1ce98e0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1ce99a0_0 .net *"_s0", 0 0, L_0x1e6c590; 1 drivers +v0x1ce9a60_0 .net *"_s12", 0 0, L_0x1e6cf00; 1 drivers +v0x1ce9b40_0 .net *"_s16", 0 0, L_0x1e6d2c0; 1 drivers +v0x1ce9c70_0 .net *"_s20", 0 0, L_0x1e6d600; 1 drivers +v0x1ce9d50_0 .net *"_s24", 0 0, L_0x1e6da20; 1 drivers +v0x1ce9e30_0 .net *"_s28", 0 0, L_0x1e6d9b0; 1 drivers +v0x1ce9f10_0 .net *"_s4", 0 0, L_0x1e6c8a0; 1 drivers +v0x1cea080_0 .net *"_s8", 0 0, L_0x1e6cbf0; 1 drivers +v0x1cea160_0 .net "out", 7 0, L_0x1e6dd30; alias, 1 drivers +L_0x1e6c650 .part L_0x1ec1640, 0, 1; +L_0x1e6c7b0 .part v0x1d6daa0_0, 0, 1; +L_0x1e6c960 .part L_0x1ec1640, 1, 1; +L_0x1e6cb50 .part v0x1d6daa0_0, 1, 1; +L_0x1e6ccb0 .part L_0x1ec1640, 2, 1; +L_0x1e6ce10 .part v0x1d6daa0_0, 2, 1; +L_0x1e6d020 .part L_0x1ec1640, 3, 1; +L_0x1e6d180 .part v0x1d6daa0_0, 3, 1; +L_0x1e6d3b0 .part L_0x1ec1640, 4, 1; +L_0x1e6d510 .part v0x1d6daa0_0, 4, 1; +L_0x1e6d6a0 .part L_0x1ec1640, 5, 1; +L_0x1e6d910 .part v0x1d6daa0_0, 5, 1; +L_0x1e6dae0 .part L_0x1ec1640, 6, 1; +L_0x1e6dc40 .part v0x1d6daa0_0, 6, 1; +LS_0x1e6dd30_0_0 .concat8 [ 1 1 1 1], L_0x1e6c590, L_0x1e6c8a0, L_0x1e6cbf0, L_0x1e6cf00; +LS_0x1e6dd30_0_4 .concat8 [ 1 1 1 1], L_0x1e6d2c0, L_0x1e6d600, L_0x1e6da20, L_0x1e6d9b0; +L_0x1e6dd30 .concat8 [ 4 4 0 0], LS_0x1e6dd30_0_0, LS_0x1e6dd30_0_4; +L_0x1e6e0f0 .part L_0x1ec1640, 7, 1; +L_0x1e6e2e0 .part v0x1d6daa0_0, 7, 1; +S_0x1ce7310 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce7520 .param/l "i" 0 4 54, +C4<00>; +L_0x1e6c590/d .functor AND 1, L_0x1e6c650, L_0x1e6c7b0, C4<1>, C4<1>; +L_0x1e6c590 .delay 1 (30000,30000,30000) L_0x1e6c590/d; +v0x1ce7600_0 .net *"_s0", 0 0, L_0x1e6c650; 1 drivers +v0x1ce76e0_0 .net *"_s1", 0 0, L_0x1e6c7b0; 1 drivers +S_0x1ce77c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce79d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e6c8a0/d .functor AND 1, L_0x1e6c960, L_0x1e6cb50, C4<1>, C4<1>; +L_0x1e6c8a0 .delay 1 (30000,30000,30000) L_0x1e6c8a0/d; +v0x1ce7a90_0 .net *"_s0", 0 0, L_0x1e6c960; 1 drivers +v0x1ce7b70_0 .net *"_s1", 0 0, L_0x1e6cb50; 1 drivers +S_0x1ce7c50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce7e60 .param/l "i" 0 4 54, +C4<010>; +L_0x1e6cbf0/d .functor AND 1, L_0x1e6ccb0, L_0x1e6ce10, C4<1>, C4<1>; +L_0x1e6cbf0 .delay 1 (30000,30000,30000) L_0x1e6cbf0/d; +v0x1ce7f00_0 .net *"_s0", 0 0, L_0x1e6ccb0; 1 drivers +v0x1ce7fe0_0 .net *"_s1", 0 0, L_0x1e6ce10; 1 drivers +S_0x1ce80c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce82d0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e6cf00/d .functor AND 1, L_0x1e6d020, L_0x1e6d180, C4<1>, C4<1>; +L_0x1e6cf00 .delay 1 (30000,30000,30000) L_0x1e6cf00/d; +v0x1ce8390_0 .net *"_s0", 0 0, L_0x1e6d020; 1 drivers +v0x1ce8470_0 .net *"_s1", 0 0, L_0x1e6d180; 1 drivers +S_0x1ce8550 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce87b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e6d2c0/d .functor AND 1, L_0x1e6d3b0, L_0x1e6d510, C4<1>, C4<1>; +L_0x1e6d2c0 .delay 1 (30000,30000,30000) L_0x1e6d2c0/d; +v0x1ce8870_0 .net *"_s0", 0 0, L_0x1e6d3b0; 1 drivers +v0x1ce8950_0 .net *"_s1", 0 0, L_0x1e6d510; 1 drivers +S_0x1ce8a30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce8c40 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e6d600/d .functor AND 1, L_0x1e6d6a0, L_0x1e6d910, C4<1>, C4<1>; +L_0x1e6d600 .delay 1 (30000,30000,30000) L_0x1e6d600/d; +v0x1ce8d00_0 .net *"_s0", 0 0, L_0x1e6d6a0; 1 drivers +v0x1ce8de0_0 .net *"_s1", 0 0, L_0x1e6d910; 1 drivers +S_0x1ce8ec0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce90d0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e6da20/d .functor AND 1, L_0x1e6dae0, L_0x1e6dc40, C4<1>, C4<1>; +L_0x1e6da20 .delay 1 (30000,30000,30000) L_0x1e6da20/d; +v0x1ce9190_0 .net *"_s0", 0 0, L_0x1e6dae0; 1 drivers +v0x1ce9270_0 .net *"_s1", 0 0, L_0x1e6dc40; 1 drivers +S_0x1ce9350 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ce70b0; + .timescale -9 -12; +P_0x1ce9560 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e6d9b0/d .functor AND 1, L_0x1e6e0f0, L_0x1e6e2e0, C4<1>, C4<1>; +L_0x1e6d9b0 .delay 1 (30000,30000,30000) L_0x1e6d9b0/d; +v0x1ce9620_0 .net *"_s0", 0 0, L_0x1e6e0f0; 1 drivers +v0x1ce9700_0 .net *"_s1", 0 0, L_0x1e6e2e0; 1 drivers +S_0x1cea2c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ce6e90; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e6fd30/d .functor OR 1, L_0x1e6fdf0, L_0x1e6ffa0, C4<0>, C4<0>; +L_0x1e6fd30 .delay 1 (30000,30000,30000) L_0x1e6fd30/d; +v0x1cebe10_0 .net *"_s10", 0 0, L_0x1e6fdf0; 1 drivers +v0x1cebef0_0 .net *"_s12", 0 0, L_0x1e6ffa0; 1 drivers +v0x1cebfd0_0 .net "in", 7 0, L_0x1e6dd30; alias, 1 drivers +v0x1cec0a0_0 .net "ors", 1 0, L_0x1e6fb50; 1 drivers +v0x1cec160_0 .net "out", 0 0, L_0x1e6fd30; alias, 1 drivers +L_0x1e6ef20 .part L_0x1e6dd30, 0, 4; +L_0x1e6fb50 .concat8 [ 1 1 0 0], L_0x1e6ec10, L_0x1e6f840; +L_0x1e6fc90 .part L_0x1e6dd30, 4, 4; +L_0x1e6fdf0 .part L_0x1e6fb50, 0, 1; +L_0x1e6ffa0 .part L_0x1e6fb50, 1, 1; +S_0x1cea480 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cea2c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e6e3d0/d .functor OR 1, L_0x1e6e490, L_0x1e6e5f0, C4<0>, C4<0>; +L_0x1e6e3d0 .delay 1 (30000,30000,30000) L_0x1e6e3d0/d; +L_0x1e6e820/d .functor OR 1, L_0x1e6e930, L_0x1e6ea90, C4<0>, C4<0>; +L_0x1e6e820 .delay 1 (30000,30000,30000) L_0x1e6e820/d; +L_0x1e6ec10/d .functor OR 1, L_0x1e6ec80, L_0x1e6ee30, C4<0>, C4<0>; +L_0x1e6ec10 .delay 1 (30000,30000,30000) L_0x1e6ec10/d; +v0x1cea6d0_0 .net *"_s0", 0 0, L_0x1e6e3d0; 1 drivers +v0x1cea7d0_0 .net *"_s10", 0 0, L_0x1e6e930; 1 drivers +v0x1cea8b0_0 .net *"_s12", 0 0, L_0x1e6ea90; 1 drivers +v0x1cea970_0 .net *"_s14", 0 0, L_0x1e6ec80; 1 drivers +v0x1ceaa50_0 .net *"_s16", 0 0, L_0x1e6ee30; 1 drivers +v0x1ceab80_0 .net *"_s3", 0 0, L_0x1e6e490; 1 drivers +v0x1ceac60_0 .net *"_s5", 0 0, L_0x1e6e5f0; 1 drivers +v0x1cead40_0 .net *"_s6", 0 0, L_0x1e6e820; 1 drivers +v0x1ceae20_0 .net "in", 3 0, L_0x1e6ef20; 1 drivers +v0x1ceaf90_0 .net "ors", 1 0, L_0x1e6e730; 1 drivers +v0x1ceb070_0 .net "out", 0 0, L_0x1e6ec10; 1 drivers +L_0x1e6e490 .part L_0x1e6ef20, 0, 1; +L_0x1e6e5f0 .part L_0x1e6ef20, 1, 1; +L_0x1e6e730 .concat8 [ 1 1 0 0], L_0x1e6e3d0, L_0x1e6e820; +L_0x1e6e930 .part L_0x1e6ef20, 2, 1; +L_0x1e6ea90 .part L_0x1e6ef20, 3, 1; +L_0x1e6ec80 .part L_0x1e6e730, 0, 1; +L_0x1e6ee30 .part L_0x1e6e730, 1, 1; +S_0x1ceb190 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cea2c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e6f050/d .functor OR 1, L_0x1e6f0c0, L_0x1e6f220, C4<0>, C4<0>; +L_0x1e6f050 .delay 1 (30000,30000,30000) L_0x1e6f050/d; +L_0x1e6f450/d .functor OR 1, L_0x1e6f560, L_0x1e6f6c0, C4<0>, C4<0>; +L_0x1e6f450 .delay 1 (30000,30000,30000) L_0x1e6f450/d; +L_0x1e6f840/d .functor OR 1, L_0x1e6f8b0, L_0x1e6fa60, C4<0>, C4<0>; +L_0x1e6f840 .delay 1 (30000,30000,30000) L_0x1e6f840/d; +v0x1ceb350_0 .net *"_s0", 0 0, L_0x1e6f050; 1 drivers +v0x1ceb450_0 .net *"_s10", 0 0, L_0x1e6f560; 1 drivers +v0x1ceb530_0 .net *"_s12", 0 0, L_0x1e6f6c0; 1 drivers +v0x1ceb5f0_0 .net *"_s14", 0 0, L_0x1e6f8b0; 1 drivers +v0x1ceb6d0_0 .net *"_s16", 0 0, L_0x1e6fa60; 1 drivers +v0x1ceb800_0 .net *"_s3", 0 0, L_0x1e6f0c0; 1 drivers +v0x1ceb8e0_0 .net *"_s5", 0 0, L_0x1e6f220; 1 drivers +v0x1ceb9c0_0 .net *"_s6", 0 0, L_0x1e6f450; 1 drivers +v0x1cebaa0_0 .net "in", 3 0, L_0x1e6fc90; 1 drivers +v0x1cebc10_0 .net "ors", 1 0, L_0x1e6f360; 1 drivers +v0x1cebcf0_0 .net "out", 0 0, L_0x1e6f840; 1 drivers +L_0x1e6f0c0 .part L_0x1e6fc90, 0, 1; +L_0x1e6f220 .part L_0x1e6fc90, 1, 1; +L_0x1e6f360 .concat8 [ 1 1 0 0], L_0x1e6f050, L_0x1e6f450; +L_0x1e6f560 .part L_0x1e6fc90, 2, 1; +L_0x1e6f6c0 .part L_0x1e6fc90, 3, 1; +L_0x1e6f8b0 .part L_0x1e6f360, 0, 1; +L_0x1e6fa60 .part L_0x1e6f360, 1, 1; +S_0x1cec600 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1ce5730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cf1a30_0 .net "ands", 7 0, L_0x1e6a230; 1 drivers +v0x1cf1b40_0 .net "in", 7 0, L_0x1e68690; alias, 1 drivers +v0x1cf1c00_0 .net "out", 0 0, L_0x1e6c230; alias, 1 drivers +v0x1cf1cd0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cec850 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cec600; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1ceef90_0 .net "A", 7 0, L_0x1e68690; alias, 1 drivers +v0x1cef090_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cef150_0 .net *"_s0", 0 0, L_0x1e68a20; 1 drivers +v0x1cef210_0 .net *"_s12", 0 0, L_0x1e693e0; 1 drivers +v0x1cef2f0_0 .net *"_s16", 0 0, L_0x1e69740; 1 drivers +v0x1cef420_0 .net *"_s20", 0 0, L_0x1e69b70; 1 drivers +v0x1cef500_0 .net *"_s24", 0 0, L_0x1e69ea0; 1 drivers +v0x1cef5e0_0 .net *"_s28", 0 0, L_0x1e69e30; 1 drivers +v0x1cef6c0_0 .net *"_s4", 0 0, L_0x1e68dc0; 1 drivers +v0x1cef830_0 .net *"_s8", 0 0, L_0x1e690d0; 1 drivers +v0x1cef910_0 .net "out", 7 0, L_0x1e6a230; alias, 1 drivers +L_0x1e68b30 .part L_0x1e68690, 0, 1; +L_0x1e68d20 .part v0x1d6daa0_0, 0, 1; +L_0x1e68e80 .part L_0x1e68690, 1, 1; +L_0x1e68fe0 .part v0x1d6daa0_0, 1, 1; +L_0x1e69190 .part L_0x1e68690, 2, 1; +L_0x1e692f0 .part v0x1d6daa0_0, 2, 1; +L_0x1e694a0 .part L_0x1e68690, 3, 1; +L_0x1e69600 .part v0x1d6daa0_0, 3, 1; +L_0x1e69800 .part L_0x1e68690, 4, 1; +L_0x1e69a70 .part v0x1d6daa0_0, 4, 1; +L_0x1e69be0 .part L_0x1e68690, 5, 1; +L_0x1e69d40 .part v0x1d6daa0_0, 5, 1; +L_0x1e69f60 .part L_0x1e68690, 6, 1; +L_0x1e6a0c0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e6a230_0_0 .concat8 [ 1 1 1 1], L_0x1e68a20, L_0x1e68dc0, L_0x1e690d0, L_0x1e693e0; +LS_0x1e6a230_0_4 .concat8 [ 1 1 1 1], L_0x1e69740, L_0x1e69b70, L_0x1e69ea0, L_0x1e69e30; +L_0x1e6a230 .concat8 [ 4 4 0 0], LS_0x1e6a230_0_0, LS_0x1e6a230_0_4; +L_0x1e6a5f0 .part L_0x1e68690, 7, 1; +L_0x1e6a7e0 .part v0x1d6daa0_0, 7, 1; +S_0x1ceca90 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1cecca0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e68a20/d .functor AND 1, L_0x1e68b30, L_0x1e68d20, C4<1>, C4<1>; +L_0x1e68a20 .delay 1 (30000,30000,30000) L_0x1e68a20/d; +v0x1cecd80_0 .net *"_s0", 0 0, L_0x1e68b30; 1 drivers +v0x1cece60_0 .net *"_s1", 0 0, L_0x1e68d20; 1 drivers +S_0x1cecf40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1ced150 .param/l "i" 0 4 54, +C4<01>; +L_0x1e68dc0/d .functor AND 1, L_0x1e68e80, L_0x1e68fe0, C4<1>, C4<1>; +L_0x1e68dc0 .delay 1 (30000,30000,30000) L_0x1e68dc0/d; +v0x1ced210_0 .net *"_s0", 0 0, L_0x1e68e80; 1 drivers +v0x1ced2f0_0 .net *"_s1", 0 0, L_0x1e68fe0; 1 drivers +S_0x1ced3d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1ced610 .param/l "i" 0 4 54, +C4<010>; +L_0x1e690d0/d .functor AND 1, L_0x1e69190, L_0x1e692f0, C4<1>, C4<1>; +L_0x1e690d0 .delay 1 (30000,30000,30000) L_0x1e690d0/d; +v0x1ced6b0_0 .net *"_s0", 0 0, L_0x1e69190; 1 drivers +v0x1ced790_0 .net *"_s1", 0 0, L_0x1e692f0; 1 drivers +S_0x1ced870 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1ceda80 .param/l "i" 0 4 54, +C4<011>; +L_0x1e693e0/d .functor AND 1, L_0x1e694a0, L_0x1e69600, C4<1>, C4<1>; +L_0x1e693e0 .delay 1 (30000,30000,30000) L_0x1e693e0/d; +v0x1cedb40_0 .net *"_s0", 0 0, L_0x1e694a0; 1 drivers +v0x1cedc20_0 .net *"_s1", 0 0, L_0x1e69600; 1 drivers +S_0x1cedd00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1cedf60 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e69740/d .functor AND 1, L_0x1e69800, L_0x1e69a70, C4<1>, C4<1>; +L_0x1e69740 .delay 1 (30000,30000,30000) L_0x1e69740/d; +v0x1cee020_0 .net *"_s0", 0 0, L_0x1e69800; 1 drivers +v0x1cee100_0 .net *"_s1", 0 0, L_0x1e69a70; 1 drivers +S_0x1cee1e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1cee3f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e69b70/d .functor AND 1, L_0x1e69be0, L_0x1e69d40, C4<1>, C4<1>; +L_0x1e69b70 .delay 1 (30000,30000,30000) L_0x1e69b70/d; +v0x1cee4b0_0 .net *"_s0", 0 0, L_0x1e69be0; 1 drivers +v0x1cee590_0 .net *"_s1", 0 0, L_0x1e69d40; 1 drivers +S_0x1cee670 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1cee880 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e69ea0/d .functor AND 1, L_0x1e69f60, L_0x1e6a0c0, C4<1>, C4<1>; +L_0x1e69ea0 .delay 1 (30000,30000,30000) L_0x1e69ea0/d; +v0x1cee940_0 .net *"_s0", 0 0, L_0x1e69f60; 1 drivers +v0x1ceea20_0 .net *"_s1", 0 0, L_0x1e6a0c0; 1 drivers +S_0x1ceeb00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cec850; + .timescale -9 -12; +P_0x1ceed10 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e69e30/d .functor AND 1, L_0x1e6a5f0, L_0x1e6a7e0, C4<1>, C4<1>; +L_0x1e69e30 .delay 1 (30000,30000,30000) L_0x1e69e30/d; +v0x1ceedd0_0 .net *"_s0", 0 0, L_0x1e6a5f0; 1 drivers +v0x1ceeeb0_0 .net *"_s1", 0 0, L_0x1e6a7e0; 1 drivers +S_0x1cefa70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cec600; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e6c230/d .functor OR 1, L_0x1e6c2f0, L_0x1e6c4a0, C4<0>, C4<0>; +L_0x1e6c230 .delay 1 (30000,30000,30000) L_0x1e6c230/d; +v0x1cf15c0_0 .net *"_s10", 0 0, L_0x1e6c2f0; 1 drivers +v0x1cf16a0_0 .net *"_s12", 0 0, L_0x1e6c4a0; 1 drivers +v0x1cf1780_0 .net "in", 7 0, L_0x1e6a230; alias, 1 drivers +v0x1cf1850_0 .net "ors", 1 0, L_0x1e6c050; 1 drivers +v0x1cf1910_0 .net "out", 0 0, L_0x1e6c230; alias, 1 drivers +L_0x1e6b420 .part L_0x1e6a230, 0, 4; +L_0x1e6c050 .concat8 [ 1 1 0 0], L_0x1e6b110, L_0x1e6bd40; +L_0x1e6c190 .part L_0x1e6a230, 4, 4; +L_0x1e6c2f0 .part L_0x1e6c050, 0, 1; +L_0x1e6c4a0 .part L_0x1e6c050, 1, 1; +S_0x1cefc30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cefa70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e6a8d0/d .functor OR 1, L_0x1e6a990, L_0x1e6aaf0, C4<0>, C4<0>; +L_0x1e6a8d0 .delay 1 (30000,30000,30000) L_0x1e6a8d0/d; +L_0x1e6ad20/d .functor OR 1, L_0x1e6ae30, L_0x1e6af90, C4<0>, C4<0>; +L_0x1e6ad20 .delay 1 (30000,30000,30000) L_0x1e6ad20/d; +L_0x1e6b110/d .functor OR 1, L_0x1e6b180, L_0x1e6b330, C4<0>, C4<0>; +L_0x1e6b110 .delay 1 (30000,30000,30000) L_0x1e6b110/d; +v0x1cefe80_0 .net *"_s0", 0 0, L_0x1e6a8d0; 1 drivers +v0x1ceff80_0 .net *"_s10", 0 0, L_0x1e6ae30; 1 drivers +v0x1cf0060_0 .net *"_s12", 0 0, L_0x1e6af90; 1 drivers +v0x1cf0120_0 .net *"_s14", 0 0, L_0x1e6b180; 1 drivers +v0x1cf0200_0 .net *"_s16", 0 0, L_0x1e6b330; 1 drivers +v0x1cf0330_0 .net *"_s3", 0 0, L_0x1e6a990; 1 drivers +v0x1cf0410_0 .net *"_s5", 0 0, L_0x1e6aaf0; 1 drivers +v0x1cf04f0_0 .net *"_s6", 0 0, L_0x1e6ad20; 1 drivers +v0x1cf05d0_0 .net "in", 3 0, L_0x1e6b420; 1 drivers +v0x1cf0740_0 .net "ors", 1 0, L_0x1e6ac30; 1 drivers +v0x1cf0820_0 .net "out", 0 0, L_0x1e6b110; 1 drivers +L_0x1e6a990 .part L_0x1e6b420, 0, 1; +L_0x1e6aaf0 .part L_0x1e6b420, 1, 1; +L_0x1e6ac30 .concat8 [ 1 1 0 0], L_0x1e6a8d0, L_0x1e6ad20; +L_0x1e6ae30 .part L_0x1e6b420, 2, 1; +L_0x1e6af90 .part L_0x1e6b420, 3, 1; +L_0x1e6b180 .part L_0x1e6ac30, 0, 1; +L_0x1e6b330 .part L_0x1e6ac30, 1, 1; +S_0x1cf0940 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cefa70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e6b550/d .functor OR 1, L_0x1e6b5c0, L_0x1e6b720, C4<0>, C4<0>; +L_0x1e6b550 .delay 1 (30000,30000,30000) L_0x1e6b550/d; +L_0x1e6b950/d .functor OR 1, L_0x1e6ba60, L_0x1e6bbc0, C4<0>, C4<0>; +L_0x1e6b950 .delay 1 (30000,30000,30000) L_0x1e6b950/d; +L_0x1e6bd40/d .functor OR 1, L_0x1e6bdb0, L_0x1e6bf60, C4<0>, C4<0>; +L_0x1e6bd40 .delay 1 (30000,30000,30000) L_0x1e6bd40/d; +v0x1cf0b00_0 .net *"_s0", 0 0, L_0x1e6b550; 1 drivers +v0x1cf0c00_0 .net *"_s10", 0 0, L_0x1e6ba60; 1 drivers +v0x1cf0ce0_0 .net *"_s12", 0 0, L_0x1e6bbc0; 1 drivers +v0x1cf0da0_0 .net *"_s14", 0 0, L_0x1e6bdb0; 1 drivers +v0x1cf0e80_0 .net *"_s16", 0 0, L_0x1e6bf60; 1 drivers +v0x1cf0fb0_0 .net *"_s3", 0 0, L_0x1e6b5c0; 1 drivers +v0x1cf1090_0 .net *"_s5", 0 0, L_0x1e6b720; 1 drivers +v0x1cf1170_0 .net *"_s6", 0 0, L_0x1e6b950; 1 drivers +v0x1cf1250_0 .net "in", 3 0, L_0x1e6c190; 1 drivers +v0x1cf13c0_0 .net "ors", 1 0, L_0x1e6b860; 1 drivers +v0x1cf14a0_0 .net "out", 0 0, L_0x1e6bd40; 1 drivers +L_0x1e6b5c0 .part L_0x1e6c190, 0, 1; +L_0x1e6b720 .part L_0x1e6c190, 1, 1; +L_0x1e6b860 .concat8 [ 1 1 0 0], L_0x1e6b550, L_0x1e6b950; +L_0x1e6ba60 .part L_0x1e6c190, 2, 1; +L_0x1e6bbc0 .part L_0x1e6c190, 3, 1; +L_0x1e6bdb0 .part L_0x1e6b860, 0, 1; +L_0x1e6bf60 .part L_0x1e6b860, 1, 1; +S_0x1c03b90 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ce5730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e67a00/d .functor XNOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; +L_0x1e67a00 .delay 1 (20000,20000,20000) L_0x1e67a00/d; +L_0x1e67c70/d .functor AND 1, L_0x1e70190, L_0x1e66a00, C4<1>, C4<1>; +L_0x1e67c70 .delay 1 (30000,30000,30000) L_0x1e67c70/d; +L_0x1e67ce0/d .functor AND 1, L_0x1e67a00, L_0x1e667a0, C4<1>, C4<1>; +L_0x1e67ce0 .delay 1 (30000,30000,30000) L_0x1e67ce0/d; +L_0x1e67e40/d .functor OR 1, L_0x1e67ce0, L_0x1e67c70, C4<0>, C4<0>; +L_0x1e67e40 .delay 1 (30000,30000,30000) L_0x1e67e40/d; +v0x1c03e40_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers +v0x1c03f30_0 .net "a_", 0 0, L_0x1e5caf0; alias, 1 drivers +v0x1c03ff0_0 .net "b", 0 0, L_0x1e66700; alias, 1 drivers +v0x1c040e0_0 .net "b_", 0 0, L_0x1e66a00; alias, 1 drivers +v0x1c04180_0 .net "carryin", 0 0, L_0x1e667a0; alias, 1 drivers +v0x1c042c0_0 .net "eq", 0 0, L_0x1e67a00; 1 drivers +v0x1cf2da0_0 .net "lt", 0 0, L_0x1e67c70; 1 drivers +v0x1cf2e60_0 .net "out", 0 0, L_0x1e67e40; 1 drivers +v0x1cf2f20_0 .net "w0", 0 0, L_0x1e67ce0; 1 drivers +S_0x1cf3170 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1ce5730; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e677e0/d .functor OR 1, L_0x1e67330, L_0x1cf4390, C4<0>, C4<0>; +L_0x1e677e0 .delay 1 (30000,30000,30000) L_0x1e677e0/d; +v0x1cf3f60_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers +v0x1cf4090_0 .net "b", 0 0, L_0x1e66a00; alias, 1 drivers +v0x1cf4130_0 .net "c1", 0 0, L_0x1e67330; 1 drivers +v0x1cf41d0_0 .net "c2", 0 0, L_0x1cf4390; 1 drivers +v0x1cf42a0_0 .net "carryin", 0 0, L_0x1e667a0; alias, 1 drivers +v0x1cf4420_0 .net "carryout", 0 0, L_0x1e677e0; 1 drivers +v0x1cf44c0_0 .net "s1", 0 0, L_0x1e67270; 1 drivers +v0x1cf4560_0 .net "sum", 0 0, L_0x1e67490; 1 drivers +S_0x1cf33c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cf3170; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e67270/d .functor XOR 1, L_0x1e70190, L_0x1e66a00, C4<0>, C4<0>; +L_0x1e67270 .delay 1 (30000,30000,30000) L_0x1e67270/d; +L_0x1e67330/d .functor AND 1, L_0x1e70190, L_0x1e66a00, C4<1>, C4<1>; +L_0x1e67330 .delay 1 (30000,30000,30000) L_0x1e67330/d; +v0x1cf3620_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers +v0x1cf36e0_0 .net "b", 0 0, L_0x1e66a00; alias, 1 drivers +v0x1cf37a0_0 .net "carryout", 0 0, L_0x1e67330; alias, 1 drivers +v0x1cf3840_0 .net "sum", 0 0, L_0x1e67270; alias, 1 drivers +S_0x1cf3970 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cf3170; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e67490/d .functor XOR 1, L_0x1e67270, L_0x1e667a0, C4<0>, C4<0>; +L_0x1e67490 .delay 1 (30000,30000,30000) L_0x1e67490/d; +L_0x1cf4390/d .functor AND 1, L_0x1e67270, L_0x1e667a0, C4<1>, C4<1>; +L_0x1cf4390 .delay 1 (30000,30000,30000) L_0x1cf4390/d; +v0x1cf3bd0_0 .net "a", 0 0, L_0x1e67270; alias, 1 drivers +v0x1cf3ca0_0 .net "b", 0 0, L_0x1e667a0; alias, 1 drivers +v0x1cf3d40_0 .net "carryout", 0 0, L_0x1cf4390; alias, 1 drivers +v0x1cf3e10_0 .net "sum", 0 0, L_0x1e67490; alias, 1 drivers +S_0x1cf59c0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1ce5460; + .timescale -9 -12; +L_0x7f72592dbc38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbc80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e70230/d .functor OR 1, L_0x7f72592dbc38, L_0x7f72592dbc80, C4<0>, C4<0>; +L_0x1e70230 .delay 1 (30000,30000,30000) L_0x1e70230/d; +v0x1cf5bb0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbc38; 1 drivers +v0x1cf5c90_0 .net/2u *"_s2", 0 0, L_0x7f72592dbc80; 1 drivers +S_0x1cf5d70 .scope generate, "alu_slices[26]" "alu_slices[26]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1cf5f80 .param/l "i" 0 3 37, +C4<011010>; +S_0x1cf6040 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cf5d70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e705c0/d .functor NOT 1, L_0x1e79dd0, C4<0>, C4<0>, C4<0>; +L_0x1e705c0 .delay 1 (10000,10000,10000) L_0x1e705c0/d; +L_0x1e706d0/d .functor NOT 1, L_0x1e79f30, C4<0>, C4<0>, C4<0>; +L_0x1e706d0 .delay 1 (10000,10000,10000) L_0x1e706d0/d; +L_0x1e71720/d .functor XOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; +L_0x1e71720 .delay 1 (30000,30000,30000) L_0x1e71720/d; +L_0x7f72592dbcc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbd10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e71dd0/d .functor OR 1, L_0x7f72592dbcc8, L_0x7f72592dbd10, C4<0>, C4<0>; +L_0x1e71dd0 .delay 1 (30000,30000,30000) L_0x1e71dd0/d; +L_0x1e71fd0/d .functor AND 1, L_0x1e79dd0, L_0x1e79f30, C4<1>, C4<1>; +L_0x1e71fd0 .delay 1 (30000,30000,30000) L_0x1e71fd0/d; +L_0x1e72090/d .functor NAND 1, L_0x1e79dd0, L_0x1e79f30, C4<1>, C4<1>; +L_0x1e72090 .delay 1 (20000,20000,20000) L_0x1e72090/d; +L_0x1e721f0/d .functor XOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; +L_0x1e721f0 .delay 1 (20000,20000,20000) L_0x1e721f0/d; +L_0x1e726a0/d .functor OR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; +L_0x1e726a0 .delay 1 (30000,30000,30000) L_0x1e726a0/d; +L_0x1e79cd0/d .functor NOT 1, L_0x1e75f30, C4<0>, C4<0>, C4<0>; +L_0x1e79cd0 .delay 1 (10000,10000,10000) L_0x1e79cd0/d; +v0x1d04770_0 .net "A", 0 0, L_0x1e79dd0; 1 drivers +v0x1d04830_0 .net "A_", 0 0, L_0x1e705c0; 1 drivers +v0x1d048f0_0 .net "B", 0 0, L_0x1e79f30; 1 drivers +v0x1d049c0_0 .net "B_", 0 0, L_0x1e706d0; 1 drivers +v0x1d04a60_0 .net *"_s12", 0 0, L_0x1e71dd0; 1 drivers +v0x1d04b50_0 .net/2s *"_s14", 0 0, L_0x7f72592dbcc8; 1 drivers +v0x1d04c10_0 .net/2s *"_s16", 0 0, L_0x7f72592dbd10; 1 drivers +v0x1d04cf0_0 .net *"_s18", 0 0, L_0x1e71fd0; 1 drivers +v0x1d04dd0_0 .net *"_s20", 0 0, L_0x1e72090; 1 drivers +v0x1d04f40_0 .net *"_s22", 0 0, L_0x1e721f0; 1 drivers +v0x1d05020_0 .net *"_s24", 0 0, L_0x1e726a0; 1 drivers +o0x7f7259331ce8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1d05100_0 name=_s30 +o0x7f7259331d18 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1d051e0_0 name=_s32 +v0x1d052c0_0 .net *"_s8", 0 0, L_0x1e71720; 1 drivers +v0x1d053a0_0 .net "carryin", 0 0, L_0x1e702f0; 1 drivers +v0x1d05440_0 .net "carryout", 0 0, L_0x1e79970; 1 drivers +v0x1d054e0_0 .net "carryouts", 7 0, L_0x1ec1810; 1 drivers +v0x1d05690_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d05730_0 .net "result", 0 0, L_0x1e75f30; 1 drivers +v0x1d05820_0 .net "results", 7 0, L_0x1e72470; 1 drivers +v0x1d05930_0 .net "zero", 0 0, L_0x1e79cd0; 1 drivers +LS_0x1e72470_0_0 .concat8 [ 1 1 1 1], L_0x1e70bf0, L_0x1e71220, L_0x1e71720, L_0x1e71dd0; +LS_0x1e72470_0_4 .concat8 [ 1 1 1 1], L_0x1e71fd0, L_0x1e72090, L_0x1e721f0, L_0x1e726a0; +L_0x1e72470 .concat8 [ 4 4 0 0], LS_0x1e72470_0_0, LS_0x1e72470_0_4; +LS_0x1ec1810_0_0 .concat [ 1 1 1 1], L_0x1e70ea0, L_0x1e715c0, o0x7f7259331ce8, L_0x1e71c20; +LS_0x1ec1810_0_4 .concat [ 4 0 0 0], o0x7f7259331d18; +L_0x1ec1810 .concat [ 4 4 0 0], LS_0x1ec1810_0_0, LS_0x1ec1810_0_4; +S_0x1cf62c0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cf6040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e70ea0/d .functor OR 1, L_0x1e70980, L_0x1e70d40, C4<0>, C4<0>; +L_0x1e70ea0 .delay 1 (30000,30000,30000) L_0x1e70ea0/d; +v0x1cf70f0_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers +v0x1cf71b0_0 .net "b", 0 0, L_0x1e79f30; alias, 1 drivers +v0x1cf7280_0 .net "c1", 0 0, L_0x1e70980; 1 drivers +v0x1cf7380_0 .net "c2", 0 0, L_0x1e70d40; 1 drivers +v0x1cf7450_0 .net "carryin", 0 0, L_0x1e702f0; alias, 1 drivers +v0x1cf7540_0 .net "carryout", 0 0, L_0x1e70ea0; 1 drivers +v0x1cf75e0_0 .net "s1", 0 0, L_0x1e708c0; 1 drivers +v0x1cf76d0_0 .net "sum", 0 0, L_0x1e70bf0; 1 drivers +S_0x1cf6530 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cf62c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e708c0/d .functor XOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; +L_0x1e708c0 .delay 1 (30000,30000,30000) L_0x1e708c0/d; +L_0x1e70980/d .functor AND 1, L_0x1e79dd0, L_0x1e79f30, C4<1>, C4<1>; +L_0x1e70980 .delay 1 (30000,30000,30000) L_0x1e70980/d; +v0x1cf6790_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers +v0x1cf6870_0 .net "b", 0 0, L_0x1e79f30; alias, 1 drivers +v0x1cf6930_0 .net "carryout", 0 0, L_0x1e70980; alias, 1 drivers +v0x1cf69d0_0 .net "sum", 0 0, L_0x1e708c0; alias, 1 drivers +S_0x1cf6b10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cf62c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e70bf0/d .functor XOR 1, L_0x1e708c0, L_0x1e702f0, C4<0>, C4<0>; +L_0x1e70bf0 .delay 1 (30000,30000,30000) L_0x1e70bf0/d; +L_0x1e70d40/d .functor AND 1, L_0x1e708c0, L_0x1e702f0, C4<1>, C4<1>; +L_0x1e70d40 .delay 1 (30000,30000,30000) L_0x1e70d40/d; +v0x1cf6d70_0 .net "a", 0 0, L_0x1e708c0; alias, 1 drivers +v0x1cf6e10_0 .net "b", 0 0, L_0x1e702f0; alias, 1 drivers +v0x1cf6eb0_0 .net "carryout", 0 0, L_0x1e70d40; alias, 1 drivers +v0x1cf6f80_0 .net "sum", 0 0, L_0x1e70bf0; alias, 1 drivers +S_0x1cf77a0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cf6040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1cfcb90_0 .net "ands", 7 0, L_0x1e77970; 1 drivers +v0x1cfcca0_0 .net "in", 7 0, L_0x1ec1810; alias, 1 drivers +v0x1cfcd60_0 .net "out", 0 0, L_0x1e79970; alias, 1 drivers +v0x1cfce30_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cf79c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cf77a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cfa0f0_0 .net "A", 7 0, L_0x1ec1810; alias, 1 drivers +v0x1cfa1f0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cfa2b0_0 .net *"_s0", 0 0, L_0x1e76290; 1 drivers +v0x1cfa370_0 .net *"_s12", 0 0, L_0x1e76c00; 1 drivers +v0x1cfa450_0 .net *"_s16", 0 0, L_0x1e76f60; 1 drivers +v0x1cfa580_0 .net *"_s20", 0 0, L_0x1e77270; 1 drivers +v0x1cfa660_0 .net *"_s24", 0 0, L_0x1e77660; 1 drivers +v0x1cfa740_0 .net *"_s28", 0 0, L_0x1e775f0; 1 drivers +v0x1cfa820_0 .net *"_s4", 0 0, L_0x1e765a0; 1 drivers +v0x1cfa990_0 .net *"_s8", 0 0, L_0x1e768f0; 1 drivers +v0x1cfaa70_0 .net "out", 7 0, L_0x1e77970; alias, 1 drivers +L_0x1e76350 .part L_0x1ec1810, 0, 1; +L_0x1e764b0 .part v0x1d6daa0_0, 0, 1; +L_0x1e76660 .part L_0x1ec1810, 1, 1; +L_0x1e76850 .part v0x1d6daa0_0, 1, 1; +L_0x1e769b0 .part L_0x1ec1810, 2, 1; +L_0x1e76b10 .part v0x1d6daa0_0, 2, 1; +L_0x1e76cc0 .part L_0x1ec1810, 3, 1; +L_0x1e76e20 .part v0x1d6daa0_0, 3, 1; +L_0x1e77020 .part L_0x1ec1810, 4, 1; +L_0x1e77180 .part v0x1d6daa0_0, 4, 1; +L_0x1e772e0 .part L_0x1ec1810, 5, 1; +L_0x1e77550 .part v0x1d6daa0_0, 5, 1; +L_0x1e77720 .part L_0x1ec1810, 6, 1; +L_0x1e77880 .part v0x1d6daa0_0, 6, 1; +LS_0x1e77970_0_0 .concat8 [ 1 1 1 1], L_0x1e76290, L_0x1e765a0, L_0x1e768f0, L_0x1e76c00; +LS_0x1e77970_0_4 .concat8 [ 1 1 1 1], L_0x1e76f60, L_0x1e77270, L_0x1e77660, L_0x1e775f0; +L_0x1e77970 .concat8 [ 4 4 0 0], LS_0x1e77970_0_0, LS_0x1e77970_0_4; +L_0x1e77d30 .part L_0x1ec1810, 7, 1; +L_0x1e77f20 .part v0x1d6daa0_0, 7, 1; +S_0x1cf7c20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf7e30 .param/l "i" 0 4 54, +C4<00>; +L_0x1e76290/d .functor AND 1, L_0x1e76350, L_0x1e764b0, C4<1>, C4<1>; +L_0x1e76290 .delay 1 (30000,30000,30000) L_0x1e76290/d; +v0x1cf7f10_0 .net *"_s0", 0 0, L_0x1e76350; 1 drivers +v0x1cf7ff0_0 .net *"_s1", 0 0, L_0x1e764b0; 1 drivers +S_0x1cf80d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf82e0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e765a0/d .functor AND 1, L_0x1e76660, L_0x1e76850, C4<1>, C4<1>; +L_0x1e765a0 .delay 1 (30000,30000,30000) L_0x1e765a0/d; +v0x1cf83a0_0 .net *"_s0", 0 0, L_0x1e76660; 1 drivers +v0x1cf8480_0 .net *"_s1", 0 0, L_0x1e76850; 1 drivers +S_0x1cf8560 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf8770 .param/l "i" 0 4 54, +C4<010>; +L_0x1e768f0/d .functor AND 1, L_0x1e769b0, L_0x1e76b10, C4<1>, C4<1>; +L_0x1e768f0 .delay 1 (30000,30000,30000) L_0x1e768f0/d; +v0x1cf8810_0 .net *"_s0", 0 0, L_0x1e769b0; 1 drivers +v0x1cf88f0_0 .net *"_s1", 0 0, L_0x1e76b10; 1 drivers +S_0x1cf89d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf8be0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e76c00/d .functor AND 1, L_0x1e76cc0, L_0x1e76e20, C4<1>, C4<1>; +L_0x1e76c00 .delay 1 (30000,30000,30000) L_0x1e76c00/d; +v0x1cf8ca0_0 .net *"_s0", 0 0, L_0x1e76cc0; 1 drivers +v0x1cf8d80_0 .net *"_s1", 0 0, L_0x1e76e20; 1 drivers +S_0x1cf8e60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf90c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e76f60/d .functor AND 1, L_0x1e77020, L_0x1e77180, C4<1>, C4<1>; +L_0x1e76f60 .delay 1 (30000,30000,30000) L_0x1e76f60/d; +v0x1cf9180_0 .net *"_s0", 0 0, L_0x1e77020; 1 drivers +v0x1cf9260_0 .net *"_s1", 0 0, L_0x1e77180; 1 drivers +S_0x1cf9340 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf9550 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e77270/d .functor AND 1, L_0x1e772e0, L_0x1e77550, C4<1>, C4<1>; +L_0x1e77270 .delay 1 (30000,30000,30000) L_0x1e77270/d; +v0x1cf9610_0 .net *"_s0", 0 0, L_0x1e772e0; 1 drivers +v0x1cf96f0_0 .net *"_s1", 0 0, L_0x1e77550; 1 drivers +S_0x1cf97d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf99e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e77660/d .functor AND 1, L_0x1e77720, L_0x1e77880, C4<1>, C4<1>; +L_0x1e77660 .delay 1 (30000,30000,30000) L_0x1e77660/d; +v0x1cf9aa0_0 .net *"_s0", 0 0, L_0x1e77720; 1 drivers +v0x1cf9b80_0 .net *"_s1", 0 0, L_0x1e77880; 1 drivers +S_0x1cf9c60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cf79c0; + .timescale -9 -12; +P_0x1cf9e70 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e775f0/d .functor AND 1, L_0x1e77d30, L_0x1e77f20, C4<1>, C4<1>; +L_0x1e775f0 .delay 1 (30000,30000,30000) L_0x1e775f0/d; +v0x1cf9f30_0 .net *"_s0", 0 0, L_0x1e77d30; 1 drivers +v0x1cfa010_0 .net *"_s1", 0 0, L_0x1e77f20; 1 drivers +S_0x1cfabd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cf77a0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e79970/d .functor OR 1, L_0x1e79a30, L_0x1e79be0, C4<0>, C4<0>; +L_0x1e79970 .delay 1 (30000,30000,30000) L_0x1e79970/d; +v0x1cfc720_0 .net *"_s10", 0 0, L_0x1e79a30; 1 drivers +v0x1cfc800_0 .net *"_s12", 0 0, L_0x1e79be0; 1 drivers +v0x1cfc8e0_0 .net "in", 7 0, L_0x1e77970; alias, 1 drivers +v0x1cfc9b0_0 .net "ors", 1 0, L_0x1e79790; 1 drivers +v0x1cfca70_0 .net "out", 0 0, L_0x1e79970; alias, 1 drivers +L_0x1e78b60 .part L_0x1e77970, 0, 4; +L_0x1e79790 .concat8 [ 1 1 0 0], L_0x1e78850, L_0x1e79480; +L_0x1e798d0 .part L_0x1e77970, 4, 4; +L_0x1e79a30 .part L_0x1e79790, 0, 1; +L_0x1e79be0 .part L_0x1e79790, 1, 1; +S_0x1cfad90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cfabd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e78010/d .functor OR 1, L_0x1e780d0, L_0x1e78230, C4<0>, C4<0>; +L_0x1e78010 .delay 1 (30000,30000,30000) L_0x1e78010/d; +L_0x1e78460/d .functor OR 1, L_0x1e78570, L_0x1e786d0, C4<0>, C4<0>; +L_0x1e78460 .delay 1 (30000,30000,30000) L_0x1e78460/d; +L_0x1e78850/d .functor OR 1, L_0x1e788c0, L_0x1e78a70, C4<0>, C4<0>; +L_0x1e78850 .delay 1 (30000,30000,30000) L_0x1e78850/d; +v0x1cfafe0_0 .net *"_s0", 0 0, L_0x1e78010; 1 drivers +v0x1cfb0e0_0 .net *"_s10", 0 0, L_0x1e78570; 1 drivers +v0x1cfb1c0_0 .net *"_s12", 0 0, L_0x1e786d0; 1 drivers +v0x1cfb280_0 .net *"_s14", 0 0, L_0x1e788c0; 1 drivers +v0x1cfb360_0 .net *"_s16", 0 0, L_0x1e78a70; 1 drivers +v0x1cfb490_0 .net *"_s3", 0 0, L_0x1e780d0; 1 drivers +v0x1cfb570_0 .net *"_s5", 0 0, L_0x1e78230; 1 drivers +v0x1cfb650_0 .net *"_s6", 0 0, L_0x1e78460; 1 drivers +v0x1cfb730_0 .net "in", 3 0, L_0x1e78b60; 1 drivers +v0x1cfb8a0_0 .net "ors", 1 0, L_0x1e78370; 1 drivers +v0x1cfb980_0 .net "out", 0 0, L_0x1e78850; 1 drivers +L_0x1e780d0 .part L_0x1e78b60, 0, 1; +L_0x1e78230 .part L_0x1e78b60, 1, 1; +L_0x1e78370 .concat8 [ 1 1 0 0], L_0x1e78010, L_0x1e78460; +L_0x1e78570 .part L_0x1e78b60, 2, 1; +L_0x1e786d0 .part L_0x1e78b60, 3, 1; +L_0x1e788c0 .part L_0x1e78370, 0, 1; +L_0x1e78a70 .part L_0x1e78370, 1, 1; +S_0x1cfbaa0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cfabd0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e78c90/d .functor OR 1, L_0x1e78d00, L_0x1e78e60, C4<0>, C4<0>; +L_0x1e78c90 .delay 1 (30000,30000,30000) L_0x1e78c90/d; +L_0x1e79090/d .functor OR 1, L_0x1e791a0, L_0x1e79300, C4<0>, C4<0>; +L_0x1e79090 .delay 1 (30000,30000,30000) L_0x1e79090/d; +L_0x1e79480/d .functor OR 1, L_0x1e794f0, L_0x1e796a0, C4<0>, C4<0>; +L_0x1e79480 .delay 1 (30000,30000,30000) L_0x1e79480/d; +v0x1cfbc60_0 .net *"_s0", 0 0, L_0x1e78c90; 1 drivers +v0x1cfbd60_0 .net *"_s10", 0 0, L_0x1e791a0; 1 drivers +v0x1cfbe40_0 .net *"_s12", 0 0, L_0x1e79300; 1 drivers +v0x1cfbf00_0 .net *"_s14", 0 0, L_0x1e794f0; 1 drivers +v0x1cfbfe0_0 .net *"_s16", 0 0, L_0x1e796a0; 1 drivers +v0x1cfc110_0 .net *"_s3", 0 0, L_0x1e78d00; 1 drivers +v0x1cfc1f0_0 .net *"_s5", 0 0, L_0x1e78e60; 1 drivers +v0x1cfc2d0_0 .net *"_s6", 0 0, L_0x1e79090; 1 drivers +v0x1cfc3b0_0 .net "in", 3 0, L_0x1e798d0; 1 drivers +v0x1cfc520_0 .net "ors", 1 0, L_0x1e78fa0; 1 drivers +v0x1cfc600_0 .net "out", 0 0, L_0x1e79480; 1 drivers +L_0x1e78d00 .part L_0x1e798d0, 0, 1; +L_0x1e78e60 .part L_0x1e798d0, 1, 1; +L_0x1e78fa0 .concat8 [ 1 1 0 0], L_0x1e78c90, L_0x1e79090; +L_0x1e791a0 .part L_0x1e798d0, 2, 1; +L_0x1e79300 .part L_0x1e798d0, 3, 1; +L_0x1e794f0 .part L_0x1e78fa0, 0, 1; +L_0x1e796a0 .part L_0x1e78fa0, 1, 1; +S_0x1cfcf10 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cf6040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d02340_0 .net "ands", 7 0, L_0x1e73f30; 1 drivers +v0x1d02450_0 .net "in", 7 0, L_0x1e72470; alias, 1 drivers +v0x1d02510_0 .net "out", 0 0, L_0x1e75f30; alias, 1 drivers +v0x1d025e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1cfd160 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cfcf10; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1cff8a0_0 .net "A", 7 0, L_0x1e72470; alias, 1 drivers +v0x1cff9a0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1cffa60_0 .net *"_s0", 0 0, L_0x1e72800; 1 drivers +v0x1cffb20_0 .net *"_s12", 0 0, L_0x1e731c0; 1 drivers +v0x1cffc00_0 .net *"_s16", 0 0, L_0x1e73520; 1 drivers +v0x1cffd30_0 .net *"_s20", 0 0, L_0x1e738f0; 1 drivers +v0x1cffe10_0 .net *"_s24", 0 0, L_0x1e73c20; 1 drivers +v0x1cffef0_0 .net *"_s28", 0 0, L_0x1e73bb0; 1 drivers +v0x1cfffd0_0 .net *"_s4", 0 0, L_0x1e72ba0; 1 drivers +v0x1d00140_0 .net *"_s8", 0 0, L_0x1e72eb0; 1 drivers +v0x1d00220_0 .net "out", 7 0, L_0x1e73f30; alias, 1 drivers +L_0x1e72910 .part L_0x1e72470, 0, 1; +L_0x1e72b00 .part v0x1d6daa0_0, 0, 1; +L_0x1e72c60 .part L_0x1e72470, 1, 1; +L_0x1e72dc0 .part v0x1d6daa0_0, 1, 1; +L_0x1e72f70 .part L_0x1e72470, 2, 1; +L_0x1e730d0 .part v0x1d6daa0_0, 2, 1; +L_0x1e73280 .part L_0x1e72470, 3, 1; +L_0x1e733e0 .part v0x1d6daa0_0, 3, 1; +L_0x1e735e0 .part L_0x1e72470, 4, 1; +L_0x1e73850 .part v0x1d6daa0_0, 4, 1; +L_0x1e73960 .part L_0x1e72470, 5, 1; +L_0x1e73ac0 .part v0x1d6daa0_0, 5, 1; +L_0x1e73ce0 .part L_0x1e72470, 6, 1; +L_0x1e73e40 .part v0x1d6daa0_0, 6, 1; +LS_0x1e73f30_0_0 .concat8 [ 1 1 1 1], L_0x1e72800, L_0x1e72ba0, L_0x1e72eb0, L_0x1e731c0; +LS_0x1e73f30_0_4 .concat8 [ 1 1 1 1], L_0x1e73520, L_0x1e738f0, L_0x1e73c20, L_0x1e73bb0; +L_0x1e73f30 .concat8 [ 4 4 0 0], LS_0x1e73f30_0_0, LS_0x1e73f30_0_4; +L_0x1e742f0 .part L_0x1e72470, 7, 1; +L_0x1e744e0 .part v0x1d6daa0_0, 7, 1; +S_0x1cfd3a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cfd5b0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e72800/d .functor AND 1, L_0x1e72910, L_0x1e72b00, C4<1>, C4<1>; +L_0x1e72800 .delay 1 (30000,30000,30000) L_0x1e72800/d; +v0x1cfd690_0 .net *"_s0", 0 0, L_0x1e72910; 1 drivers +v0x1cfd770_0 .net *"_s1", 0 0, L_0x1e72b00; 1 drivers +S_0x1cfd850 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cfda60 .param/l "i" 0 4 54, +C4<01>; +L_0x1e72ba0/d .functor AND 1, L_0x1e72c60, L_0x1e72dc0, C4<1>, C4<1>; +L_0x1e72ba0 .delay 1 (30000,30000,30000) L_0x1e72ba0/d; +v0x1cfdb20_0 .net *"_s0", 0 0, L_0x1e72c60; 1 drivers +v0x1cfdc00_0 .net *"_s1", 0 0, L_0x1e72dc0; 1 drivers +S_0x1cfdce0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cfdf20 .param/l "i" 0 4 54, +C4<010>; +L_0x1e72eb0/d .functor AND 1, L_0x1e72f70, L_0x1e730d0, C4<1>, C4<1>; +L_0x1e72eb0 .delay 1 (30000,30000,30000) L_0x1e72eb0/d; +v0x1cfdfc0_0 .net *"_s0", 0 0, L_0x1e72f70; 1 drivers +v0x1cfe0a0_0 .net *"_s1", 0 0, L_0x1e730d0; 1 drivers +S_0x1cfe180 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cfe390 .param/l "i" 0 4 54, +C4<011>; +L_0x1e731c0/d .functor AND 1, L_0x1e73280, L_0x1e733e0, C4<1>, C4<1>; +L_0x1e731c0 .delay 1 (30000,30000,30000) L_0x1e731c0/d; +v0x1cfe450_0 .net *"_s0", 0 0, L_0x1e73280; 1 drivers +v0x1cfe530_0 .net *"_s1", 0 0, L_0x1e733e0; 1 drivers +S_0x1cfe610 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cfe870 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e73520/d .functor AND 1, L_0x1e735e0, L_0x1e73850, C4<1>, C4<1>; +L_0x1e73520 .delay 1 (30000,30000,30000) L_0x1e73520/d; +v0x1cfe930_0 .net *"_s0", 0 0, L_0x1e735e0; 1 drivers +v0x1cfea10_0 .net *"_s1", 0 0, L_0x1e73850; 1 drivers +S_0x1cfeaf0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cfed00 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e738f0/d .functor AND 1, L_0x1e73960, L_0x1e73ac0, C4<1>, C4<1>; +L_0x1e738f0 .delay 1 (30000,30000,30000) L_0x1e738f0/d; +v0x1cfedc0_0 .net *"_s0", 0 0, L_0x1e73960; 1 drivers +v0x1cfeea0_0 .net *"_s1", 0 0, L_0x1e73ac0; 1 drivers +S_0x1cfef80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cff190 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e73c20/d .functor AND 1, L_0x1e73ce0, L_0x1e73e40, C4<1>, C4<1>; +L_0x1e73c20 .delay 1 (30000,30000,30000) L_0x1e73c20/d; +v0x1cff250_0 .net *"_s0", 0 0, L_0x1e73ce0; 1 drivers +v0x1cff330_0 .net *"_s1", 0 0, L_0x1e73e40; 1 drivers +S_0x1cff410 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cfd160; + .timescale -9 -12; +P_0x1cff620 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e73bb0/d .functor AND 1, L_0x1e742f0, L_0x1e744e0, C4<1>, C4<1>; +L_0x1e73bb0 .delay 1 (30000,30000,30000) L_0x1e73bb0/d; +v0x1cff6e0_0 .net *"_s0", 0 0, L_0x1e742f0; 1 drivers +v0x1cff7c0_0 .net *"_s1", 0 0, L_0x1e744e0; 1 drivers +S_0x1d00380 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cfcf10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e75f30/d .functor OR 1, L_0x1e75ff0, L_0x1e761a0, C4<0>, C4<0>; +L_0x1e75f30 .delay 1 (30000,30000,30000) L_0x1e75f30/d; +v0x1d01ed0_0 .net *"_s10", 0 0, L_0x1e75ff0; 1 drivers +v0x1d01fb0_0 .net *"_s12", 0 0, L_0x1e761a0; 1 drivers +v0x1d02090_0 .net "in", 7 0, L_0x1e73f30; alias, 1 drivers +v0x1d02160_0 .net "ors", 1 0, L_0x1e75d50; 1 drivers +v0x1d02220_0 .net "out", 0 0, L_0x1e75f30; alias, 1 drivers +L_0x1e75120 .part L_0x1e73f30, 0, 4; +L_0x1e75d50 .concat8 [ 1 1 0 0], L_0x1e74e10, L_0x1e75a40; +L_0x1e75e90 .part L_0x1e73f30, 4, 4; +L_0x1e75ff0 .part L_0x1e75d50, 0, 1; +L_0x1e761a0 .part L_0x1e75d50, 1, 1; +S_0x1d00540 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d00380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e745d0/d .functor OR 1, L_0x1e74690, L_0x1e747f0, C4<0>, C4<0>; +L_0x1e745d0 .delay 1 (30000,30000,30000) L_0x1e745d0/d; +L_0x1e74a20/d .functor OR 1, L_0x1e74b30, L_0x1e74c90, C4<0>, C4<0>; +L_0x1e74a20 .delay 1 (30000,30000,30000) L_0x1e74a20/d; +L_0x1e74e10/d .functor OR 1, L_0x1e74e80, L_0x1e75030, C4<0>, C4<0>; +L_0x1e74e10 .delay 1 (30000,30000,30000) L_0x1e74e10/d; +v0x1d00790_0 .net *"_s0", 0 0, L_0x1e745d0; 1 drivers +v0x1d00890_0 .net *"_s10", 0 0, L_0x1e74b30; 1 drivers +v0x1d00970_0 .net *"_s12", 0 0, L_0x1e74c90; 1 drivers +v0x1d00a30_0 .net *"_s14", 0 0, L_0x1e74e80; 1 drivers +v0x1d00b10_0 .net *"_s16", 0 0, L_0x1e75030; 1 drivers +v0x1d00c40_0 .net *"_s3", 0 0, L_0x1e74690; 1 drivers +v0x1d00d20_0 .net *"_s5", 0 0, L_0x1e747f0; 1 drivers +v0x1d00e00_0 .net *"_s6", 0 0, L_0x1e74a20; 1 drivers +v0x1d00ee0_0 .net "in", 3 0, L_0x1e75120; 1 drivers +v0x1d01050_0 .net "ors", 1 0, L_0x1e74930; 1 drivers +v0x1d01130_0 .net "out", 0 0, L_0x1e74e10; 1 drivers +L_0x1e74690 .part L_0x1e75120, 0, 1; +L_0x1e747f0 .part L_0x1e75120, 1, 1; +L_0x1e74930 .concat8 [ 1 1 0 0], L_0x1e745d0, L_0x1e74a20; +L_0x1e74b30 .part L_0x1e75120, 2, 1; +L_0x1e74c90 .part L_0x1e75120, 3, 1; +L_0x1e74e80 .part L_0x1e74930, 0, 1; +L_0x1e75030 .part L_0x1e74930, 1, 1; +S_0x1d01250 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d00380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e75250/d .functor OR 1, L_0x1e752c0, L_0x1e75420, C4<0>, C4<0>; +L_0x1e75250 .delay 1 (30000,30000,30000) L_0x1e75250/d; +L_0x1e75650/d .functor OR 1, L_0x1e75760, L_0x1e758c0, C4<0>, C4<0>; +L_0x1e75650 .delay 1 (30000,30000,30000) L_0x1e75650/d; +L_0x1e75a40/d .functor OR 1, L_0x1e75ab0, L_0x1e75c60, C4<0>, C4<0>; +L_0x1e75a40 .delay 1 (30000,30000,30000) L_0x1e75a40/d; +v0x1d01410_0 .net *"_s0", 0 0, L_0x1e75250; 1 drivers +v0x1d01510_0 .net *"_s10", 0 0, L_0x1e75760; 1 drivers +v0x1d015f0_0 .net *"_s12", 0 0, L_0x1e758c0; 1 drivers +v0x1d016b0_0 .net *"_s14", 0 0, L_0x1e75ab0; 1 drivers +v0x1d01790_0 .net *"_s16", 0 0, L_0x1e75c60; 1 drivers +v0x1d018c0_0 .net *"_s3", 0 0, L_0x1e752c0; 1 drivers +v0x1d019a0_0 .net *"_s5", 0 0, L_0x1e75420; 1 drivers +v0x1d01a80_0 .net *"_s6", 0 0, L_0x1e75650; 1 drivers +v0x1d01b60_0 .net "in", 3 0, L_0x1e75e90; 1 drivers +v0x1d01cd0_0 .net "ors", 1 0, L_0x1e75560; 1 drivers +v0x1d01db0_0 .net "out", 0 0, L_0x1e75a40; 1 drivers +L_0x1e752c0 .part L_0x1e75e90, 0, 1; +L_0x1e75420 .part L_0x1e75e90, 1, 1; +L_0x1e75560 .concat8 [ 1 1 0 0], L_0x1e75250, L_0x1e75650; +L_0x1e75760 .part L_0x1e75e90, 2, 1; +L_0x1e758c0 .part L_0x1e75e90, 3, 1; +L_0x1e75ab0 .part L_0x1e75560, 0, 1; +L_0x1e75c60 .part L_0x1e75560, 1, 1; +S_0x1d026c0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cf6040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e717e0/d .functor XNOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; +L_0x1e717e0 .delay 1 (20000,20000,20000) L_0x1e717e0/d; +L_0x1e71a50/d .functor AND 1, L_0x1e79dd0, L_0x1e706d0, C4<1>, C4<1>; +L_0x1e71a50 .delay 1 (30000,30000,30000) L_0x1e71a50/d; +L_0x1e71ac0/d .functor AND 1, L_0x1e717e0, L_0x1e702f0, C4<1>, C4<1>; +L_0x1e71ac0 .delay 1 (30000,30000,30000) L_0x1e71ac0/d; +L_0x1e71c20/d .functor OR 1, L_0x1e71ac0, L_0x1e71a50, C4<0>, C4<0>; +L_0x1e71c20 .delay 1 (30000,30000,30000) L_0x1e71c20/d; +v0x1d02970_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers +v0x1d02a60_0 .net "a_", 0 0, L_0x1e705c0; alias, 1 drivers +v0x1d02b20_0 .net "b", 0 0, L_0x1e79f30; alias, 1 drivers +v0x1d02c10_0 .net "b_", 0 0, L_0x1e706d0; alias, 1 drivers +v0x1d02cb0_0 .net "carryin", 0 0, L_0x1e702f0; alias, 1 drivers +v0x1d02df0_0 .net "eq", 0 0, L_0x1e717e0; 1 drivers +v0x1d02eb0_0 .net "lt", 0 0, L_0x1e71a50; 1 drivers +v0x1d02f70_0 .net "out", 0 0, L_0x1e71c20; 1 drivers +v0x1d03030_0 .net "w0", 0 0, L_0x1e71ac0; 1 drivers +S_0x1d03280 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cf6040; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e715c0/d .functor OR 1, L_0x1e710c0, L_0x1d044e0, C4<0>, C4<0>; +L_0x1e715c0 .delay 1 (30000,30000,30000) L_0x1e715c0/d; +v0x1d04070_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers +v0x1d041c0_0 .net "b", 0 0, L_0x1e706d0; alias, 1 drivers +v0x1d04280_0 .net "c1", 0 0, L_0x1e710c0; 1 drivers +v0x1d04320_0 .net "c2", 0 0, L_0x1d044e0; 1 drivers +v0x1d043f0_0 .net "carryin", 0 0, L_0x1e702f0; alias, 1 drivers +v0x1d04570_0 .net "carryout", 0 0, L_0x1e715c0; 1 drivers +v0x1d04610_0 .net "s1", 0 0, L_0x1e71000; 1 drivers +v0x1d046b0_0 .net "sum", 0 0, L_0x1e71220; 1 drivers +S_0x1d034d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d03280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e71000/d .functor XOR 1, L_0x1e79dd0, L_0x1e706d0, C4<0>, C4<0>; +L_0x1e71000 .delay 1 (30000,30000,30000) L_0x1e71000/d; +L_0x1e710c0/d .functor AND 1, L_0x1e79dd0, L_0x1e706d0, C4<1>, C4<1>; +L_0x1e710c0 .delay 1 (30000,30000,30000) L_0x1e710c0/d; +v0x1d03730_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers +v0x1d037f0_0 .net "b", 0 0, L_0x1e706d0; alias, 1 drivers +v0x1d038b0_0 .net "carryout", 0 0, L_0x1e710c0; alias, 1 drivers +v0x1d03950_0 .net "sum", 0 0, L_0x1e71000; alias, 1 drivers +S_0x1d03a80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d03280; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e71220/d .functor XOR 1, L_0x1e71000, L_0x1e702f0, C4<0>, C4<0>; +L_0x1e71220 .delay 1 (30000,30000,30000) L_0x1e71220/d; +L_0x1d044e0/d .functor AND 1, L_0x1e71000, L_0x1e702f0, C4<1>, C4<1>; +L_0x1d044e0 .delay 1 (30000,30000,30000) L_0x1d044e0/d; +v0x1d03ce0_0 .net "a", 0 0, L_0x1e71000; alias, 1 drivers +v0x1d03db0_0 .net "b", 0 0, L_0x1e702f0; alias, 1 drivers +v0x1d03e50_0 .net "carryout", 0 0, L_0x1d044e0; alias, 1 drivers +v0x1d03f20_0 .net "sum", 0 0, L_0x1e71220; alias, 1 drivers +S_0x1d05ad0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cf5d70; + .timescale -9 -12; +L_0x7f72592dbd58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbda0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e79e70/d .functor OR 1, L_0x7f72592dbd58, L_0x7f72592dbda0, C4<0>, C4<0>; +L_0x1e79e70 .delay 1 (30000,30000,30000) L_0x1e79e70/d; +v0x1d05cc0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbd58; 1 drivers +v0x1d05da0_0 .net/2u *"_s2", 0 0, L_0x7f72592dbda0; 1 drivers +S_0x1d05e80 .scope generate, "alu_slices[27]" "alu_slices[27]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1d06090 .param/l "i" 0 3 37, +C4<011011>; +S_0x1d06150 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d05e80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e70480/d .functor NOT 1, L_0x1e83a40, C4<0>, C4<0>, C4<0>; +L_0x1e70480 .delay 1 (10000,10000,10000) L_0x1e70480/d; +L_0x1e7a300/d .functor NOT 1, L_0x1e79fd0, C4<0>, C4<0>, C4<0>; +L_0x1e7a300 .delay 1 (10000,10000,10000) L_0x1e7a300/d; +L_0x1e7b350/d .functor XOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; +L_0x1e7b350 .delay 1 (30000,30000,30000) L_0x1e7b350/d; +L_0x7f72592dbde8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbe30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e7ba00/d .functor OR 1, L_0x7f72592dbde8, L_0x7f72592dbe30, C4<0>, C4<0>; +L_0x1e7ba00 .delay 1 (30000,30000,30000) L_0x1e7ba00/d; +L_0x1e7bc00/d .functor AND 1, L_0x1e83a40, L_0x1e79fd0, C4<1>, C4<1>; +L_0x1e7bc00 .delay 1 (30000,30000,30000) L_0x1e7bc00/d; +L_0x1e7bcc0/d .functor NAND 1, L_0x1e83a40, L_0x1e79fd0, C4<1>, C4<1>; +L_0x1e7bcc0 .delay 1 (20000,20000,20000) L_0x1e7bcc0/d; +L_0x1e7be20/d .functor XOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; +L_0x1e7be20 .delay 1 (20000,20000,20000) L_0x1e7be20/d; +L_0x1e7c230/d .functor OR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; +L_0x1e7c230 .delay 1 (30000,30000,30000) L_0x1e7c230/d; +L_0x1e83940/d .functor NOT 1, L_0x1e7fba0, C4<0>, C4<0>, C4<0>; +L_0x1e83940 .delay 1 (10000,10000,10000) L_0x1e83940/d; +v0x1d14880_0 .net "A", 0 0, L_0x1e83a40; 1 drivers +v0x1d14940_0 .net "A_", 0 0, L_0x1e70480; 1 drivers +v0x1d14a00_0 .net "B", 0 0, L_0x1e79fd0; 1 drivers +v0x1d14ad0_0 .net "B_", 0 0, L_0x1e7a300; 1 drivers +v0x1d14b70_0 .net *"_s12", 0 0, L_0x1e7ba00; 1 drivers +v0x1d14c60_0 .net/2s *"_s14", 0 0, L_0x7f72592dbde8; 1 drivers +v0x1d14d20_0 .net/2s *"_s16", 0 0, L_0x7f72592dbe30; 1 drivers +v0x1d14e00_0 .net *"_s18", 0 0, L_0x1e7bc00; 1 drivers +v0x1d14ee0_0 .net *"_s20", 0 0, L_0x1e7bcc0; 1 drivers +v0x1d15010_0 .net *"_s22", 0 0, L_0x1e7be20; 1 drivers +v0x1d150d0_0 .net *"_s24", 0 0, L_0x1e7c230; 1 drivers +o0x7f7259334238 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1d151b0_0 name=_s30 +o0x7f7259334268 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1d15290_0 name=_s32 +v0x1d15370_0 .net *"_s8", 0 0, L_0x1e7b350; 1 drivers +v0x1d15450_0 .net "carryin", 0 0, L_0x1e7a070; 1 drivers +v0x1d154f0_0 .net "carryout", 0 0, L_0x1e835e0; 1 drivers +v0x1d15590_0 .net "carryouts", 7 0, L_0x1ec19e0; 1 drivers +v0x1d15740_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d157e0_0 .net "result", 0 0, L_0x1e7fba0; 1 drivers +v0x1d158d0_0 .net "results", 7 0, L_0x1e7a710; 1 drivers +v0x1d159e0_0 .net "zero", 0 0, L_0x1e83940; 1 drivers +LS_0x1e7a710_0_0 .concat8 [ 1 1 1 1], L_0x1e7a820, L_0x1e7ae50, L_0x1e7b350, L_0x1e7ba00; +LS_0x1e7a710_0_4 .concat8 [ 1 1 1 1], L_0x1e7bc00, L_0x1e7bcc0, L_0x1e7be20, L_0x1e7c230; +L_0x1e7a710 .concat8 [ 4 4 0 0], LS_0x1e7a710_0_0, LS_0x1e7a710_0_4; +LS_0x1ec19e0_0_0 .concat [ 1 1 1 1], L_0x1e7aad0, L_0x1e7b1f0, o0x7f7259334238, L_0x1e7b850; +LS_0x1ec19e0_0_4 .concat [ 4 0 0 0], o0x7f7259334268; +L_0x1ec19e0 .concat [ 4 4 0 0], LS_0x1ec19e0_0_0, LS_0x1ec19e0_0_4; +S_0x1d063d0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d06150; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e7aad0/d .functor OR 1, L_0x1e7a5b0, L_0x1e7a970, C4<0>, C4<0>; +L_0x1e7aad0 .delay 1 (30000,30000,30000) L_0x1e7aad0/d; +v0x1d07200_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers +v0x1d072c0_0 .net "b", 0 0, L_0x1e79fd0; alias, 1 drivers +v0x1d07390_0 .net "c1", 0 0, L_0x1e7a5b0; 1 drivers +v0x1d07490_0 .net "c2", 0 0, L_0x1e7a970; 1 drivers +v0x1d07560_0 .net "carryin", 0 0, L_0x1e7a070; alias, 1 drivers +v0x1d07650_0 .net "carryout", 0 0, L_0x1e7aad0; 1 drivers +v0x1d076f0_0 .net "s1", 0 0, L_0x1e7a4f0; 1 drivers +v0x1d077e0_0 .net "sum", 0 0, L_0x1e7a820; 1 drivers +S_0x1d06640 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d063d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e7a4f0/d .functor XOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; +L_0x1e7a4f0 .delay 1 (30000,30000,30000) L_0x1e7a4f0/d; +L_0x1e7a5b0/d .functor AND 1, L_0x1e83a40, L_0x1e79fd0, C4<1>, C4<1>; +L_0x1e7a5b0 .delay 1 (30000,30000,30000) L_0x1e7a5b0/d; +v0x1d068a0_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers +v0x1d06980_0 .net "b", 0 0, L_0x1e79fd0; alias, 1 drivers +v0x1d06a40_0 .net "carryout", 0 0, L_0x1e7a5b0; alias, 1 drivers +v0x1d06ae0_0 .net "sum", 0 0, L_0x1e7a4f0; alias, 1 drivers +S_0x1d06c20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d063d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e7a820/d .functor XOR 1, L_0x1e7a4f0, L_0x1e7a070, C4<0>, C4<0>; +L_0x1e7a820 .delay 1 (30000,30000,30000) L_0x1e7a820/d; +L_0x1e7a970/d .functor AND 1, L_0x1e7a4f0, L_0x1e7a070, C4<1>, C4<1>; +L_0x1e7a970 .delay 1 (30000,30000,30000) L_0x1e7a970/d; +v0x1d06e80_0 .net "a", 0 0, L_0x1e7a4f0; alias, 1 drivers +v0x1d06f20_0 .net "b", 0 0, L_0x1e7a070; alias, 1 drivers +v0x1d06fc0_0 .net "carryout", 0 0, L_0x1e7a970; alias, 1 drivers +v0x1d07090_0 .net "sum", 0 0, L_0x1e7a820; alias, 1 drivers +S_0x1d078b0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d06150; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d0cca0_0 .net "ands", 7 0, L_0x1e815e0; 1 drivers +v0x1d0cdb0_0 .net "in", 7 0, L_0x1ec19e0; alias, 1 drivers +v0x1d0ce70_0 .net "out", 0 0, L_0x1e835e0; alias, 1 drivers +v0x1d0cf40_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d07ad0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d078b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d0a200_0 .net "A", 7 0, L_0x1ec19e0; alias, 1 drivers +v0x1d0a300_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d0a3c0_0 .net *"_s0", 0 0, L_0x1e7ff00; 1 drivers +v0x1d0a480_0 .net *"_s12", 0 0, L_0x1e80870; 1 drivers +v0x1d0a560_0 .net *"_s16", 0 0, L_0x1e80bd0; 1 drivers +v0x1d0a690_0 .net *"_s20", 0 0, L_0x1e80ee0; 1 drivers +v0x1d0a770_0 .net *"_s24", 0 0, L_0x1e812d0; 1 drivers +v0x1d0a850_0 .net *"_s28", 0 0, L_0x1e81260; 1 drivers +v0x1d0a930_0 .net *"_s4", 0 0, L_0x1e80210; 1 drivers +v0x1d0aaa0_0 .net *"_s8", 0 0, L_0x1e80560; 1 drivers +v0x1d0ab80_0 .net "out", 7 0, L_0x1e815e0; alias, 1 drivers +L_0x1e7ffc0 .part L_0x1ec19e0, 0, 1; +L_0x1e80120 .part v0x1d6daa0_0, 0, 1; +L_0x1e802d0 .part L_0x1ec19e0, 1, 1; +L_0x1e804c0 .part v0x1d6daa0_0, 1, 1; +L_0x1e80620 .part L_0x1ec19e0, 2, 1; +L_0x1e80780 .part v0x1d6daa0_0, 2, 1; +L_0x1e80930 .part L_0x1ec19e0, 3, 1; +L_0x1e80a90 .part v0x1d6daa0_0, 3, 1; +L_0x1e80c90 .part L_0x1ec19e0, 4, 1; +L_0x1e80df0 .part v0x1d6daa0_0, 4, 1; +L_0x1e80f50 .part L_0x1ec19e0, 5, 1; +L_0x1e811c0 .part v0x1d6daa0_0, 5, 1; +L_0x1e81390 .part L_0x1ec19e0, 6, 1; +L_0x1e814f0 .part v0x1d6daa0_0, 6, 1; +LS_0x1e815e0_0_0 .concat8 [ 1 1 1 1], L_0x1e7ff00, L_0x1e80210, L_0x1e80560, L_0x1e80870; +LS_0x1e815e0_0_4 .concat8 [ 1 1 1 1], L_0x1e80bd0, L_0x1e80ee0, L_0x1e812d0, L_0x1e81260; +L_0x1e815e0 .concat8 [ 4 4 0 0], LS_0x1e815e0_0_0, LS_0x1e815e0_0_4; +L_0x1e819a0 .part L_0x1ec19e0, 7, 1; +L_0x1e81b90 .part v0x1d6daa0_0, 7, 1; +S_0x1d07d30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d07f40 .param/l "i" 0 4 54, +C4<00>; +L_0x1e7ff00/d .functor AND 1, L_0x1e7ffc0, L_0x1e80120, C4<1>, C4<1>; +L_0x1e7ff00 .delay 1 (30000,30000,30000) L_0x1e7ff00/d; +v0x1d08020_0 .net *"_s0", 0 0, L_0x1e7ffc0; 1 drivers +v0x1d08100_0 .net *"_s1", 0 0, L_0x1e80120; 1 drivers +S_0x1d081e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d083f0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e80210/d .functor AND 1, L_0x1e802d0, L_0x1e804c0, C4<1>, C4<1>; +L_0x1e80210 .delay 1 (30000,30000,30000) L_0x1e80210/d; +v0x1d084b0_0 .net *"_s0", 0 0, L_0x1e802d0; 1 drivers +v0x1d08590_0 .net *"_s1", 0 0, L_0x1e804c0; 1 drivers +S_0x1d08670 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d08880 .param/l "i" 0 4 54, +C4<010>; +L_0x1e80560/d .functor AND 1, L_0x1e80620, L_0x1e80780, C4<1>, C4<1>; +L_0x1e80560 .delay 1 (30000,30000,30000) L_0x1e80560/d; +v0x1d08920_0 .net *"_s0", 0 0, L_0x1e80620; 1 drivers +v0x1d08a00_0 .net *"_s1", 0 0, L_0x1e80780; 1 drivers +S_0x1d08ae0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d08cf0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e80870/d .functor AND 1, L_0x1e80930, L_0x1e80a90, C4<1>, C4<1>; +L_0x1e80870 .delay 1 (30000,30000,30000) L_0x1e80870/d; +v0x1d08db0_0 .net *"_s0", 0 0, L_0x1e80930; 1 drivers +v0x1d08e90_0 .net *"_s1", 0 0, L_0x1e80a90; 1 drivers +S_0x1d08f70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d091d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e80bd0/d .functor AND 1, L_0x1e80c90, L_0x1e80df0, C4<1>, C4<1>; +L_0x1e80bd0 .delay 1 (30000,30000,30000) L_0x1e80bd0/d; +v0x1d09290_0 .net *"_s0", 0 0, L_0x1e80c90; 1 drivers +v0x1d09370_0 .net *"_s1", 0 0, L_0x1e80df0; 1 drivers +S_0x1d09450 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d09660 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e80ee0/d .functor AND 1, L_0x1e80f50, L_0x1e811c0, C4<1>, C4<1>; +L_0x1e80ee0 .delay 1 (30000,30000,30000) L_0x1e80ee0/d; +v0x1d09720_0 .net *"_s0", 0 0, L_0x1e80f50; 1 drivers +v0x1d09800_0 .net *"_s1", 0 0, L_0x1e811c0; 1 drivers +S_0x1d098e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d09af0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e812d0/d .functor AND 1, L_0x1e81390, L_0x1e814f0, C4<1>, C4<1>; +L_0x1e812d0 .delay 1 (30000,30000,30000) L_0x1e812d0/d; +v0x1d09bb0_0 .net *"_s0", 0 0, L_0x1e81390; 1 drivers +v0x1d09c90_0 .net *"_s1", 0 0, L_0x1e814f0; 1 drivers +S_0x1d09d70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d07ad0; + .timescale -9 -12; +P_0x1d09f80 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e81260/d .functor AND 1, L_0x1e819a0, L_0x1e81b90, C4<1>, C4<1>; +L_0x1e81260 .delay 1 (30000,30000,30000) L_0x1e81260/d; +v0x1d0a040_0 .net *"_s0", 0 0, L_0x1e819a0; 1 drivers +v0x1d0a120_0 .net *"_s1", 0 0, L_0x1e81b90; 1 drivers +S_0x1d0ace0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d078b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e835e0/d .functor OR 1, L_0x1e836a0, L_0x1e83850, C4<0>, C4<0>; +L_0x1e835e0 .delay 1 (30000,30000,30000) L_0x1e835e0/d; +v0x1d0c830_0 .net *"_s10", 0 0, L_0x1e836a0; 1 drivers +v0x1d0c910_0 .net *"_s12", 0 0, L_0x1e83850; 1 drivers +v0x1d0c9f0_0 .net "in", 7 0, L_0x1e815e0; alias, 1 drivers +v0x1d0cac0_0 .net "ors", 1 0, L_0x1e83400; 1 drivers +v0x1d0cb80_0 .net "out", 0 0, L_0x1e835e0; alias, 1 drivers +L_0x1e827d0 .part L_0x1e815e0, 0, 4; +L_0x1e83400 .concat8 [ 1 1 0 0], L_0x1e824c0, L_0x1e830f0; +L_0x1e83540 .part L_0x1e815e0, 4, 4; +L_0x1e836a0 .part L_0x1e83400, 0, 1; +L_0x1e83850 .part L_0x1e83400, 1, 1; +S_0x1d0aea0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d0ace0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e81c80/d .functor OR 1, L_0x1e81d40, L_0x1e81ea0, C4<0>, C4<0>; +L_0x1e81c80 .delay 1 (30000,30000,30000) L_0x1e81c80/d; +L_0x1e820d0/d .functor OR 1, L_0x1e821e0, L_0x1e82340, C4<0>, C4<0>; +L_0x1e820d0 .delay 1 (30000,30000,30000) L_0x1e820d0/d; +L_0x1e824c0/d .functor OR 1, L_0x1e82530, L_0x1e826e0, C4<0>, C4<0>; +L_0x1e824c0 .delay 1 (30000,30000,30000) L_0x1e824c0/d; +v0x1d0b0f0_0 .net *"_s0", 0 0, L_0x1e81c80; 1 drivers +v0x1d0b1f0_0 .net *"_s10", 0 0, L_0x1e821e0; 1 drivers +v0x1d0b2d0_0 .net *"_s12", 0 0, L_0x1e82340; 1 drivers +v0x1d0b390_0 .net *"_s14", 0 0, L_0x1e82530; 1 drivers +v0x1d0b470_0 .net *"_s16", 0 0, L_0x1e826e0; 1 drivers +v0x1d0b5a0_0 .net *"_s3", 0 0, L_0x1e81d40; 1 drivers +v0x1d0b680_0 .net *"_s5", 0 0, L_0x1e81ea0; 1 drivers +v0x1d0b760_0 .net *"_s6", 0 0, L_0x1e820d0; 1 drivers +v0x1d0b840_0 .net "in", 3 0, L_0x1e827d0; 1 drivers +v0x1d0b9b0_0 .net "ors", 1 0, L_0x1e81fe0; 1 drivers +v0x1d0ba90_0 .net "out", 0 0, L_0x1e824c0; 1 drivers +L_0x1e81d40 .part L_0x1e827d0, 0, 1; +L_0x1e81ea0 .part L_0x1e827d0, 1, 1; +L_0x1e81fe0 .concat8 [ 1 1 0 0], L_0x1e81c80, L_0x1e820d0; +L_0x1e821e0 .part L_0x1e827d0, 2, 1; +L_0x1e82340 .part L_0x1e827d0, 3, 1; +L_0x1e82530 .part L_0x1e81fe0, 0, 1; +L_0x1e826e0 .part L_0x1e81fe0, 1, 1; +S_0x1d0bbb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d0ace0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e82900/d .functor OR 1, L_0x1e82970, L_0x1e82ad0, C4<0>, C4<0>; +L_0x1e82900 .delay 1 (30000,30000,30000) L_0x1e82900/d; +L_0x1e82d00/d .functor OR 1, L_0x1e82e10, L_0x1e82f70, C4<0>, C4<0>; +L_0x1e82d00 .delay 1 (30000,30000,30000) L_0x1e82d00/d; +L_0x1e830f0/d .functor OR 1, L_0x1e83160, L_0x1e83310, C4<0>, C4<0>; +L_0x1e830f0 .delay 1 (30000,30000,30000) L_0x1e830f0/d; +v0x1d0bd70_0 .net *"_s0", 0 0, L_0x1e82900; 1 drivers +v0x1d0be70_0 .net *"_s10", 0 0, L_0x1e82e10; 1 drivers +v0x1d0bf50_0 .net *"_s12", 0 0, L_0x1e82f70; 1 drivers +v0x1d0c010_0 .net *"_s14", 0 0, L_0x1e83160; 1 drivers +v0x1d0c0f0_0 .net *"_s16", 0 0, L_0x1e83310; 1 drivers +v0x1d0c220_0 .net *"_s3", 0 0, L_0x1e82970; 1 drivers +v0x1d0c300_0 .net *"_s5", 0 0, L_0x1e82ad0; 1 drivers +v0x1d0c3e0_0 .net *"_s6", 0 0, L_0x1e82d00; 1 drivers +v0x1d0c4c0_0 .net "in", 3 0, L_0x1e83540; 1 drivers +v0x1d0c630_0 .net "ors", 1 0, L_0x1e82c10; 1 drivers +v0x1d0c710_0 .net "out", 0 0, L_0x1e830f0; 1 drivers +L_0x1e82970 .part L_0x1e83540, 0, 1; +L_0x1e82ad0 .part L_0x1e83540, 1, 1; +L_0x1e82c10 .concat8 [ 1 1 0 0], L_0x1e82900, L_0x1e82d00; +L_0x1e82e10 .part L_0x1e83540, 2, 1; +L_0x1e82f70 .part L_0x1e83540, 3, 1; +L_0x1e83160 .part L_0x1e82c10, 0, 1; +L_0x1e83310 .part L_0x1e82c10, 1, 1; +S_0x1d0d020 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d06150; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d12450_0 .net "ands", 7 0, L_0x1e7dba0; 1 drivers +v0x1d12560_0 .net "in", 7 0, L_0x1e7a710; alias, 1 drivers +v0x1d12620_0 .net "out", 0 0, L_0x1e7fba0; alias, 1 drivers +v0x1d126f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d0d270 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d0d020; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d0f9b0_0 .net "A", 7 0, L_0x1e7a710; alias, 1 drivers +v0x1d0fab0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d0fb70_0 .net *"_s0", 0 0, L_0x1e7c390; 1 drivers +v0x1d0fc30_0 .net *"_s12", 0 0, L_0x1e7cd50; 1 drivers +v0x1d0fd10_0 .net *"_s16", 0 0, L_0x1e7d0b0; 1 drivers +v0x1d0fe40_0 .net *"_s20", 0 0, L_0x1e7d4e0; 1 drivers +v0x1d0ff20_0 .net *"_s24", 0 0, L_0x1e7d810; 1 drivers +v0x1d10000_0 .net *"_s28", 0 0, L_0x1e7d7a0; 1 drivers +v0x1d100e0_0 .net *"_s4", 0 0, L_0x1e7c730; 1 drivers +v0x1d10250_0 .net *"_s8", 0 0, L_0x1e7ca40; 1 drivers +v0x1d10330_0 .net "out", 7 0, L_0x1e7dba0; alias, 1 drivers +L_0x1e7c4a0 .part L_0x1e7a710, 0, 1; +L_0x1e7c690 .part v0x1d6daa0_0, 0, 1; +L_0x1e7c7f0 .part L_0x1e7a710, 1, 1; +L_0x1e7c950 .part v0x1d6daa0_0, 1, 1; +L_0x1e7cb00 .part L_0x1e7a710, 2, 1; +L_0x1e7cc60 .part v0x1d6daa0_0, 2, 1; +L_0x1e7ce10 .part L_0x1e7a710, 3, 1; +L_0x1e7cf70 .part v0x1d6daa0_0, 3, 1; +L_0x1e7d170 .part L_0x1e7a710, 4, 1; +L_0x1e7d3e0 .part v0x1d6daa0_0, 4, 1; +L_0x1e7d550 .part L_0x1e7a710, 5, 1; +L_0x1e7d6b0 .part v0x1d6daa0_0, 5, 1; +L_0x1e7d8d0 .part L_0x1e7a710, 6, 1; +L_0x1e7da30 .part v0x1d6daa0_0, 6, 1; +LS_0x1e7dba0_0_0 .concat8 [ 1 1 1 1], L_0x1e7c390, L_0x1e7c730, L_0x1e7ca40, L_0x1e7cd50; +LS_0x1e7dba0_0_4 .concat8 [ 1 1 1 1], L_0x1e7d0b0, L_0x1e7d4e0, L_0x1e7d810, L_0x1e7d7a0; +L_0x1e7dba0 .concat8 [ 4 4 0 0], LS_0x1e7dba0_0_0, LS_0x1e7dba0_0_4; +L_0x1e7df60 .part L_0x1e7a710, 7, 1; +L_0x1e7e150 .part v0x1d6daa0_0, 7, 1; +S_0x1d0d4b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0d6c0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e7c390/d .functor AND 1, L_0x1e7c4a0, L_0x1e7c690, C4<1>, C4<1>; +L_0x1e7c390 .delay 1 (30000,30000,30000) L_0x1e7c390/d; +v0x1d0d7a0_0 .net *"_s0", 0 0, L_0x1e7c4a0; 1 drivers +v0x1d0d880_0 .net *"_s1", 0 0, L_0x1e7c690; 1 drivers +S_0x1d0d960 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0db70 .param/l "i" 0 4 54, +C4<01>; +L_0x1e7c730/d .functor AND 1, L_0x1e7c7f0, L_0x1e7c950, C4<1>, C4<1>; +L_0x1e7c730 .delay 1 (30000,30000,30000) L_0x1e7c730/d; +v0x1d0dc30_0 .net *"_s0", 0 0, L_0x1e7c7f0; 1 drivers +v0x1d0dd10_0 .net *"_s1", 0 0, L_0x1e7c950; 1 drivers +S_0x1d0ddf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0e030 .param/l "i" 0 4 54, +C4<010>; +L_0x1e7ca40/d .functor AND 1, L_0x1e7cb00, L_0x1e7cc60, C4<1>, C4<1>; +L_0x1e7ca40 .delay 1 (30000,30000,30000) L_0x1e7ca40/d; +v0x1d0e0d0_0 .net *"_s0", 0 0, L_0x1e7cb00; 1 drivers +v0x1d0e1b0_0 .net *"_s1", 0 0, L_0x1e7cc60; 1 drivers +S_0x1d0e290 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0e4a0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e7cd50/d .functor AND 1, L_0x1e7ce10, L_0x1e7cf70, C4<1>, C4<1>; +L_0x1e7cd50 .delay 1 (30000,30000,30000) L_0x1e7cd50/d; +v0x1d0e560_0 .net *"_s0", 0 0, L_0x1e7ce10; 1 drivers +v0x1d0e640_0 .net *"_s1", 0 0, L_0x1e7cf70; 1 drivers +S_0x1d0e720 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0e980 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e7d0b0/d .functor AND 1, L_0x1e7d170, L_0x1e7d3e0, C4<1>, C4<1>; +L_0x1e7d0b0 .delay 1 (30000,30000,30000) L_0x1e7d0b0/d; +v0x1d0ea40_0 .net *"_s0", 0 0, L_0x1e7d170; 1 drivers +v0x1d0eb20_0 .net *"_s1", 0 0, L_0x1e7d3e0; 1 drivers +S_0x1d0ec00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0ee10 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e7d4e0/d .functor AND 1, L_0x1e7d550, L_0x1e7d6b0, C4<1>, C4<1>; +L_0x1e7d4e0 .delay 1 (30000,30000,30000) L_0x1e7d4e0/d; +v0x1d0eed0_0 .net *"_s0", 0 0, L_0x1e7d550; 1 drivers +v0x1d0efb0_0 .net *"_s1", 0 0, L_0x1e7d6b0; 1 drivers +S_0x1d0f090 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0f2a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e7d810/d .functor AND 1, L_0x1e7d8d0, L_0x1e7da30, C4<1>, C4<1>; +L_0x1e7d810 .delay 1 (30000,30000,30000) L_0x1e7d810/d; +v0x1d0f360_0 .net *"_s0", 0 0, L_0x1e7d8d0; 1 drivers +v0x1d0f440_0 .net *"_s1", 0 0, L_0x1e7da30; 1 drivers +S_0x1d0f520 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d0d270; + .timescale -9 -12; +P_0x1d0f730 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e7d7a0/d .functor AND 1, L_0x1e7df60, L_0x1e7e150, C4<1>, C4<1>; +L_0x1e7d7a0 .delay 1 (30000,30000,30000) L_0x1e7d7a0/d; +v0x1d0f7f0_0 .net *"_s0", 0 0, L_0x1e7df60; 1 drivers +v0x1d0f8d0_0 .net *"_s1", 0 0, L_0x1e7e150; 1 drivers +S_0x1d10490 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d0d020; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e7fba0/d .functor OR 1, L_0x1e7fc60, L_0x1e7fe10, C4<0>, C4<0>; +L_0x1e7fba0 .delay 1 (30000,30000,30000) L_0x1e7fba0/d; +v0x1d11fe0_0 .net *"_s10", 0 0, L_0x1e7fc60; 1 drivers +v0x1d120c0_0 .net *"_s12", 0 0, L_0x1e7fe10; 1 drivers +v0x1d121a0_0 .net "in", 7 0, L_0x1e7dba0; alias, 1 drivers +v0x1d12270_0 .net "ors", 1 0, L_0x1e7f9c0; 1 drivers +v0x1d12330_0 .net "out", 0 0, L_0x1e7fba0; alias, 1 drivers +L_0x1e7ed90 .part L_0x1e7dba0, 0, 4; +L_0x1e7f9c0 .concat8 [ 1 1 0 0], L_0x1e7ea80, L_0x1e7f6b0; +L_0x1e7fb00 .part L_0x1e7dba0, 4, 4; +L_0x1e7fc60 .part L_0x1e7f9c0, 0, 1; +L_0x1e7fe10 .part L_0x1e7f9c0, 1, 1; +S_0x1d10650 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d10490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e7e240/d .functor OR 1, L_0x1e7e300, L_0x1e7e460, C4<0>, C4<0>; +L_0x1e7e240 .delay 1 (30000,30000,30000) L_0x1e7e240/d; +L_0x1e7e690/d .functor OR 1, L_0x1e7e7a0, L_0x1e7e900, C4<0>, C4<0>; +L_0x1e7e690 .delay 1 (30000,30000,30000) L_0x1e7e690/d; +L_0x1e7ea80/d .functor OR 1, L_0x1e7eaf0, L_0x1e7eca0, C4<0>, C4<0>; +L_0x1e7ea80 .delay 1 (30000,30000,30000) L_0x1e7ea80/d; +v0x1d108a0_0 .net *"_s0", 0 0, L_0x1e7e240; 1 drivers +v0x1d109a0_0 .net *"_s10", 0 0, L_0x1e7e7a0; 1 drivers +v0x1d10a80_0 .net *"_s12", 0 0, L_0x1e7e900; 1 drivers +v0x1d10b40_0 .net *"_s14", 0 0, L_0x1e7eaf0; 1 drivers +v0x1d10c20_0 .net *"_s16", 0 0, L_0x1e7eca0; 1 drivers +v0x1d10d50_0 .net *"_s3", 0 0, L_0x1e7e300; 1 drivers +v0x1d10e30_0 .net *"_s5", 0 0, L_0x1e7e460; 1 drivers +v0x1d10f10_0 .net *"_s6", 0 0, L_0x1e7e690; 1 drivers +v0x1d10ff0_0 .net "in", 3 0, L_0x1e7ed90; 1 drivers +v0x1d11160_0 .net "ors", 1 0, L_0x1e7e5a0; 1 drivers +v0x1d11240_0 .net "out", 0 0, L_0x1e7ea80; 1 drivers +L_0x1e7e300 .part L_0x1e7ed90, 0, 1; +L_0x1e7e460 .part L_0x1e7ed90, 1, 1; +L_0x1e7e5a0 .concat8 [ 1 1 0 0], L_0x1e7e240, L_0x1e7e690; +L_0x1e7e7a0 .part L_0x1e7ed90, 2, 1; +L_0x1e7e900 .part L_0x1e7ed90, 3, 1; +L_0x1e7eaf0 .part L_0x1e7e5a0, 0, 1; +L_0x1e7eca0 .part L_0x1e7e5a0, 1, 1; +S_0x1d11360 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d10490; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e7eec0/d .functor OR 1, L_0x1e7ef30, L_0x1e7f090, C4<0>, C4<0>; +L_0x1e7eec0 .delay 1 (30000,30000,30000) L_0x1e7eec0/d; +L_0x1e7f2c0/d .functor OR 1, L_0x1e7f3d0, L_0x1e7f530, C4<0>, C4<0>; +L_0x1e7f2c0 .delay 1 (30000,30000,30000) L_0x1e7f2c0/d; +L_0x1e7f6b0/d .functor OR 1, L_0x1e7f720, L_0x1e7f8d0, C4<0>, C4<0>; +L_0x1e7f6b0 .delay 1 (30000,30000,30000) L_0x1e7f6b0/d; +v0x1d11520_0 .net *"_s0", 0 0, L_0x1e7eec0; 1 drivers +v0x1d11620_0 .net *"_s10", 0 0, L_0x1e7f3d0; 1 drivers +v0x1d11700_0 .net *"_s12", 0 0, L_0x1e7f530; 1 drivers +v0x1d117c0_0 .net *"_s14", 0 0, L_0x1e7f720; 1 drivers +v0x1d118a0_0 .net *"_s16", 0 0, L_0x1e7f8d0; 1 drivers +v0x1d119d0_0 .net *"_s3", 0 0, L_0x1e7ef30; 1 drivers +v0x1d11ab0_0 .net *"_s5", 0 0, L_0x1e7f090; 1 drivers +v0x1d11b90_0 .net *"_s6", 0 0, L_0x1e7f2c0; 1 drivers +v0x1d11c70_0 .net "in", 3 0, L_0x1e7fb00; 1 drivers +v0x1d11de0_0 .net "ors", 1 0, L_0x1e7f1d0; 1 drivers +v0x1d11ec0_0 .net "out", 0 0, L_0x1e7f6b0; 1 drivers +L_0x1e7ef30 .part L_0x1e7fb00, 0, 1; +L_0x1e7f090 .part L_0x1e7fb00, 1, 1; +L_0x1e7f1d0 .concat8 [ 1 1 0 0], L_0x1e7eec0, L_0x1e7f2c0; +L_0x1e7f3d0 .part L_0x1e7fb00, 2, 1; +L_0x1e7f530 .part L_0x1e7fb00, 3, 1; +L_0x1e7f720 .part L_0x1e7f1d0, 0, 1; +L_0x1e7f8d0 .part L_0x1e7f1d0, 1, 1; +S_0x1d127d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d06150; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e7b410/d .functor XNOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; +L_0x1e7b410 .delay 1 (20000,20000,20000) L_0x1e7b410/d; +L_0x1e7b680/d .functor AND 1, L_0x1e83a40, L_0x1e7a300, C4<1>, C4<1>; +L_0x1e7b680 .delay 1 (30000,30000,30000) L_0x1e7b680/d; +L_0x1e7b6f0/d .functor AND 1, L_0x1e7b410, L_0x1e7a070, C4<1>, C4<1>; +L_0x1e7b6f0 .delay 1 (30000,30000,30000) L_0x1e7b6f0/d; +L_0x1e7b850/d .functor OR 1, L_0x1e7b6f0, L_0x1e7b680, C4<0>, C4<0>; +L_0x1e7b850 .delay 1 (30000,30000,30000) L_0x1e7b850/d; +v0x1d12a80_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers +v0x1d12b70_0 .net "a_", 0 0, L_0x1e70480; alias, 1 drivers +v0x1d12c30_0 .net "b", 0 0, L_0x1e79fd0; alias, 1 drivers +v0x1d12d20_0 .net "b_", 0 0, L_0x1e7a300; alias, 1 drivers +v0x1d12dc0_0 .net "carryin", 0 0, L_0x1e7a070; alias, 1 drivers +v0x1d12f00_0 .net "eq", 0 0, L_0x1e7b410; 1 drivers +v0x1d12fc0_0 .net "lt", 0 0, L_0x1e7b680; 1 drivers +v0x1d13080_0 .net "out", 0 0, L_0x1e7b850; 1 drivers +v0x1d13140_0 .net "w0", 0 0, L_0x1e7b6f0; 1 drivers +S_0x1d13390 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d06150; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e7b1f0/d .functor OR 1, L_0x1e7acf0, L_0x1d145f0, C4<0>, C4<0>; +L_0x1e7b1f0 .delay 1 (30000,30000,30000) L_0x1e7b1f0/d; +v0x1d14180_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers +v0x1d142d0_0 .net "b", 0 0, L_0x1e7a300; alias, 1 drivers +v0x1d14390_0 .net "c1", 0 0, L_0x1e7acf0; 1 drivers +v0x1d14430_0 .net "c2", 0 0, L_0x1d145f0; 1 drivers +v0x1d14500_0 .net "carryin", 0 0, L_0x1e7a070; alias, 1 drivers +v0x1d14680_0 .net "carryout", 0 0, L_0x1e7b1f0; 1 drivers +v0x1d14720_0 .net "s1", 0 0, L_0x1e7ac30; 1 drivers +v0x1d147c0_0 .net "sum", 0 0, L_0x1e7ae50; 1 drivers +S_0x1d135e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d13390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e7ac30/d .functor XOR 1, L_0x1e83a40, L_0x1e7a300, C4<0>, C4<0>; +L_0x1e7ac30 .delay 1 (30000,30000,30000) L_0x1e7ac30/d; +L_0x1e7acf0/d .functor AND 1, L_0x1e83a40, L_0x1e7a300, C4<1>, C4<1>; +L_0x1e7acf0 .delay 1 (30000,30000,30000) L_0x1e7acf0/d; +v0x1d13840_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers +v0x1d13900_0 .net "b", 0 0, L_0x1e7a300; alias, 1 drivers +v0x1d139c0_0 .net "carryout", 0 0, L_0x1e7acf0; alias, 1 drivers +v0x1d13a60_0 .net "sum", 0 0, L_0x1e7ac30; alias, 1 drivers +S_0x1d13b90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d13390; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e7ae50/d .functor XOR 1, L_0x1e7ac30, L_0x1e7a070, C4<0>, C4<0>; +L_0x1e7ae50 .delay 1 (30000,30000,30000) L_0x1e7ae50/d; +L_0x1d145f0/d .functor AND 1, L_0x1e7ac30, L_0x1e7a070, C4<1>, C4<1>; +L_0x1d145f0 .delay 1 (30000,30000,30000) L_0x1d145f0/d; +v0x1d13df0_0 .net "a", 0 0, L_0x1e7ac30; alias, 1 drivers +v0x1d13ec0_0 .net "b", 0 0, L_0x1e7a070; alias, 1 drivers +v0x1d13f60_0 .net "carryout", 0 0, L_0x1d145f0; alias, 1 drivers +v0x1d14030_0 .net "sum", 0 0, L_0x1e7ae50; alias, 1 drivers +S_0x1d15bc0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d05e80; + .timescale -9 -12; +L_0x7f72592dbe78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbec0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e83ae0/d .functor OR 1, L_0x7f72592dbe78, L_0x7f72592dbec0, C4<0>, C4<0>; +L_0x1e83ae0 .delay 1 (30000,30000,30000) L_0x1e83ae0/d; +v0x1d15db0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbe78; 1 drivers +v0x1d15e90_0 .net/2u *"_s2", 0 0, L_0x7f72592dbec0; 1 drivers +S_0x1d15f70 .scope generate, "alu_slices[28]" "alu_slices[28]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1d16180 .param/l "i" 0 3 37, +C4<011100>; +S_0x1d16240 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d15f70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e7a1b0/d .functor NOT 1, L_0x1e8d680, C4<0>, C4<0>, C4<0>; +L_0x1e7a1b0 .delay 1 (10000,10000,10000) L_0x1e7a1b0/d; +L_0x1e83ef0/d .functor NOT 1, L_0x1e8d7e0, C4<0>, C4<0>, C4<0>; +L_0x1e83ef0 .delay 1 (10000,10000,10000) L_0x1e83ef0/d; +L_0x1e84ef0/d .functor XOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; +L_0x1e84ef0 .delay 1 (30000,30000,30000) L_0x1e84ef0/d; +L_0x7f72592dbf08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbf50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e855a0/d .functor OR 1, L_0x7f72592dbf08, L_0x7f72592dbf50, C4<0>, C4<0>; +L_0x1e855a0 .delay 1 (30000,30000,30000) L_0x1e855a0/d; +L_0x1e857a0/d .functor AND 1, L_0x1e8d680, L_0x1e8d7e0, C4<1>, C4<1>; +L_0x1e857a0 .delay 1 (30000,30000,30000) L_0x1e857a0/d; +L_0x1e85860/d .functor NAND 1, L_0x1e8d680, L_0x1e8d7e0, C4<1>, C4<1>; +L_0x1e85860 .delay 1 (20000,20000,20000) L_0x1e85860/d; +L_0x1e859c0/d .functor XOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; +L_0x1e859c0 .delay 1 (20000,20000,20000) L_0x1e859c0/d; +L_0x1e85e70/d .functor OR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; +L_0x1e85e70 .delay 1 (30000,30000,30000) L_0x1e85e70/d; +L_0x1e8d580/d .functor NOT 1, L_0x1e897e0, C4<0>, C4<0>, C4<0>; +L_0x1e8d580 .delay 1 (10000,10000,10000) L_0x1e8d580/d; +v0x1d249a0_0 .net "A", 0 0, L_0x1e8d680; 1 drivers +v0x1d24a60_0 .net "A_", 0 0, L_0x1e7a1b0; 1 drivers +v0x1d24b20_0 .net "B", 0 0, L_0x1e8d7e0; 1 drivers +v0x1d24bf0_0 .net "B_", 0 0, L_0x1e83ef0; 1 drivers +v0x1d24c90_0 .net *"_s12", 0 0, L_0x1e855a0; 1 drivers +v0x1d24d80_0 .net/2s *"_s14", 0 0, L_0x7f72592dbf08; 1 drivers +v0x1d24e40_0 .net/2s *"_s16", 0 0, L_0x7f72592dbf50; 1 drivers +v0x1d24f20_0 .net *"_s18", 0 0, L_0x1e857a0; 1 drivers +v0x1d25000_0 .net *"_s20", 0 0, L_0x1e85860; 1 drivers +v0x1d25170_0 .net *"_s22", 0 0, L_0x1e859c0; 1 drivers +v0x1d25250_0 .net *"_s24", 0 0, L_0x1e85e70; 1 drivers +o0x7f7259336788 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1d25330_0 name=_s30 +o0x7f72593367b8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1d25410_0 name=_s32 +v0x1d254f0_0 .net *"_s8", 0 0, L_0x1e84ef0; 1 drivers +v0x1d255d0_0 .net "carryin", 0 0, L_0x1e83ba0; 1 drivers +v0x1d25670_0 .net "carryout", 0 0, L_0x1e8d220; 1 drivers +v0x1d25710_0 .net "carryouts", 7 0, L_0x1ec1bb0; 1 drivers +v0x1d258c0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d25960_0 .net "result", 0 0, L_0x1e897e0; 1 drivers +v0x1d25a50_0 .net "results", 7 0, L_0x1e85c40; 1 drivers +v0x1d25b60_0 .net "zero", 0 0, L_0x1e8d580; 1 drivers +LS_0x1e85c40_0_0 .concat8 [ 1 1 1 1], L_0x1e84410, L_0x1e84a40, L_0x1e84ef0, L_0x1e855a0; +LS_0x1e85c40_0_4 .concat8 [ 1 1 1 1], L_0x1e857a0, L_0x1e85860, L_0x1e859c0, L_0x1e85e70; +L_0x1e85c40 .concat8 [ 4 4 0 0], LS_0x1e85c40_0_0, LS_0x1e85c40_0_4; +LS_0x1ec1bb0_0_0 .concat [ 1 1 1 1], L_0x1e846c0, L_0x1e84d90, o0x7f7259336788, L_0x1e853f0; +LS_0x1ec1bb0_0_4 .concat [ 4 0 0 0], o0x7f72593367b8; +L_0x1ec1bb0 .concat [ 4 4 0 0], LS_0x1ec1bb0_0_0, LS_0x1ec1bb0_0_4; +S_0x1d164c0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d16240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e846c0/d .functor OR 1, L_0x1e841a0, L_0x1e84560, C4<0>, C4<0>; +L_0x1e846c0 .delay 1 (30000,30000,30000) L_0x1e846c0/d; +v0x1d17320_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers +v0x1d173e0_0 .net "b", 0 0, L_0x1e8d7e0; alias, 1 drivers +v0x1d174b0_0 .net "c1", 0 0, L_0x1e841a0; 1 drivers +v0x1d175b0_0 .net "c2", 0 0, L_0x1e84560; 1 drivers +v0x1d17680_0 .net "carryin", 0 0, L_0x1e83ba0; alias, 1 drivers +v0x1d17770_0 .net "carryout", 0 0, L_0x1e846c0; 1 drivers +v0x1d17810_0 .net "s1", 0 0, L_0x1e840e0; 1 drivers +v0x1d17900_0 .net "sum", 0 0, L_0x1e84410; 1 drivers +S_0x1d16730 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d164c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e840e0/d .functor XOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; +L_0x1e840e0 .delay 1 (30000,30000,30000) L_0x1e840e0/d; +L_0x1e841a0/d .functor AND 1, L_0x1e8d680, L_0x1e8d7e0, C4<1>, C4<1>; +L_0x1e841a0 .delay 1 (30000,30000,30000) L_0x1e841a0/d; +v0x1d16990_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers +v0x1d16a70_0 .net "b", 0 0, L_0x1e8d7e0; alias, 1 drivers +v0x1d16b30_0 .net "carryout", 0 0, L_0x1e841a0; alias, 1 drivers +v0x1d16bd0_0 .net "sum", 0 0, L_0x1e840e0; alias, 1 drivers +S_0x1d16d10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d164c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e84410/d .functor XOR 1, L_0x1e840e0, L_0x1e83ba0, C4<0>, C4<0>; +L_0x1e84410 .delay 1 (30000,30000,30000) L_0x1e84410/d; +L_0x1e84560/d .functor AND 1, L_0x1e840e0, L_0x1e83ba0, C4<1>, C4<1>; +L_0x1e84560 .delay 1 (30000,30000,30000) L_0x1e84560/d; +v0x1d16f70_0 .net "a", 0 0, L_0x1e840e0; alias, 1 drivers +v0x1d17040_0 .net "b", 0 0, L_0x1e83ba0; alias, 1 drivers +v0x1d170e0_0 .net "carryout", 0 0, L_0x1e84560; alias, 1 drivers +v0x1d171b0_0 .net "sum", 0 0, L_0x1e84410; alias, 1 drivers +S_0x1d179d0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d16240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d1cdc0_0 .net "ands", 7 0, L_0x1e8b220; 1 drivers +v0x1d1ced0_0 .net "in", 7 0, L_0x1ec1bb0; alias, 1 drivers +v0x1d1cf90_0 .net "out", 0 0, L_0x1e8d220; alias, 1 drivers +v0x1d1d060_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d17bf0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d179d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d1a320_0 .net "A", 7 0, L_0x1ec1bb0; alias, 1 drivers +v0x1d1a420_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d1a4e0_0 .net *"_s0", 0 0, L_0x1e89b40; 1 drivers +v0x1d1a5a0_0 .net *"_s12", 0 0, L_0x1e8a4b0; 1 drivers +v0x1d1a680_0 .net *"_s16", 0 0, L_0x1e8a810; 1 drivers +v0x1d1a7b0_0 .net *"_s20", 0 0, L_0x1e8ab20; 1 drivers +v0x1d1a890_0 .net *"_s24", 0 0, L_0x1e8af10; 1 drivers +v0x1d1a970_0 .net *"_s28", 0 0, L_0x1e8aea0; 1 drivers +v0x1d1aa50_0 .net *"_s4", 0 0, L_0x1e89e50; 1 drivers +v0x1d1abc0_0 .net *"_s8", 0 0, L_0x1e8a1a0; 1 drivers +v0x1d1aca0_0 .net "out", 7 0, L_0x1e8b220; alias, 1 drivers +L_0x1e89c00 .part L_0x1ec1bb0, 0, 1; +L_0x1e89d60 .part v0x1d6daa0_0, 0, 1; +L_0x1e89f10 .part L_0x1ec1bb0, 1, 1; +L_0x1e8a100 .part v0x1d6daa0_0, 1, 1; +L_0x1e8a260 .part L_0x1ec1bb0, 2, 1; +L_0x1e8a3c0 .part v0x1d6daa0_0, 2, 1; +L_0x1e8a570 .part L_0x1ec1bb0, 3, 1; +L_0x1e8a6d0 .part v0x1d6daa0_0, 3, 1; +L_0x1e8a8d0 .part L_0x1ec1bb0, 4, 1; +L_0x1e8aa30 .part v0x1d6daa0_0, 4, 1; +L_0x1e8ab90 .part L_0x1ec1bb0, 5, 1; +L_0x1e8ae00 .part v0x1d6daa0_0, 5, 1; +L_0x1e8afd0 .part L_0x1ec1bb0, 6, 1; +L_0x1e8b130 .part v0x1d6daa0_0, 6, 1; +LS_0x1e8b220_0_0 .concat8 [ 1 1 1 1], L_0x1e89b40, L_0x1e89e50, L_0x1e8a1a0, L_0x1e8a4b0; +LS_0x1e8b220_0_4 .concat8 [ 1 1 1 1], L_0x1e8a810, L_0x1e8ab20, L_0x1e8af10, L_0x1e8aea0; +L_0x1e8b220 .concat8 [ 4 4 0 0], LS_0x1e8b220_0_0, LS_0x1e8b220_0_4; +L_0x1e8b5e0 .part L_0x1ec1bb0, 7, 1; +L_0x1e8b7d0 .part v0x1d6daa0_0, 7, 1; +S_0x1d17e50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d18060 .param/l "i" 0 4 54, +C4<00>; +L_0x1e89b40/d .functor AND 1, L_0x1e89c00, L_0x1e89d60, C4<1>, C4<1>; +L_0x1e89b40 .delay 1 (30000,30000,30000) L_0x1e89b40/d; +v0x1d18140_0 .net *"_s0", 0 0, L_0x1e89c00; 1 drivers +v0x1d18220_0 .net *"_s1", 0 0, L_0x1e89d60; 1 drivers +S_0x1d18300 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d18510 .param/l "i" 0 4 54, +C4<01>; +L_0x1e89e50/d .functor AND 1, L_0x1e89f10, L_0x1e8a100, C4<1>, C4<1>; +L_0x1e89e50 .delay 1 (30000,30000,30000) L_0x1e89e50/d; +v0x1d185d0_0 .net *"_s0", 0 0, L_0x1e89f10; 1 drivers +v0x1d186b0_0 .net *"_s1", 0 0, L_0x1e8a100; 1 drivers +S_0x1d18790 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d189a0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e8a1a0/d .functor AND 1, L_0x1e8a260, L_0x1e8a3c0, C4<1>, C4<1>; +L_0x1e8a1a0 .delay 1 (30000,30000,30000) L_0x1e8a1a0/d; +v0x1d18a40_0 .net *"_s0", 0 0, L_0x1e8a260; 1 drivers +v0x1d18b20_0 .net *"_s1", 0 0, L_0x1e8a3c0; 1 drivers +S_0x1d18c00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d18e10 .param/l "i" 0 4 54, +C4<011>; +L_0x1e8a4b0/d .functor AND 1, L_0x1e8a570, L_0x1e8a6d0, C4<1>, C4<1>; +L_0x1e8a4b0 .delay 1 (30000,30000,30000) L_0x1e8a4b0/d; +v0x1d18ed0_0 .net *"_s0", 0 0, L_0x1e8a570; 1 drivers +v0x1d18fb0_0 .net *"_s1", 0 0, L_0x1e8a6d0; 1 drivers +S_0x1d19090 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d192f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e8a810/d .functor AND 1, L_0x1e8a8d0, L_0x1e8aa30, C4<1>, C4<1>; +L_0x1e8a810 .delay 1 (30000,30000,30000) L_0x1e8a810/d; +v0x1d193b0_0 .net *"_s0", 0 0, L_0x1e8a8d0; 1 drivers +v0x1d19490_0 .net *"_s1", 0 0, L_0x1e8aa30; 1 drivers +S_0x1d19570 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d19780 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e8ab20/d .functor AND 1, L_0x1e8ab90, L_0x1e8ae00, C4<1>, C4<1>; +L_0x1e8ab20 .delay 1 (30000,30000,30000) L_0x1e8ab20/d; +v0x1d19840_0 .net *"_s0", 0 0, L_0x1e8ab90; 1 drivers +v0x1d19920_0 .net *"_s1", 0 0, L_0x1e8ae00; 1 drivers +S_0x1d19a00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d19c10 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e8af10/d .functor AND 1, L_0x1e8afd0, L_0x1e8b130, C4<1>, C4<1>; +L_0x1e8af10 .delay 1 (30000,30000,30000) L_0x1e8af10/d; +v0x1d19cd0_0 .net *"_s0", 0 0, L_0x1e8afd0; 1 drivers +v0x1d19db0_0 .net *"_s1", 0 0, L_0x1e8b130; 1 drivers +S_0x1d19e90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d17bf0; + .timescale -9 -12; +P_0x1d1a0a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e8aea0/d .functor AND 1, L_0x1e8b5e0, L_0x1e8b7d0, C4<1>, C4<1>; +L_0x1e8aea0 .delay 1 (30000,30000,30000) L_0x1e8aea0/d; +v0x1d1a160_0 .net *"_s0", 0 0, L_0x1e8b5e0; 1 drivers +v0x1d1a240_0 .net *"_s1", 0 0, L_0x1e8b7d0; 1 drivers +S_0x1d1ae00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d179d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e8d220/d .functor OR 1, L_0x1e8d2e0, L_0x1e8d490, C4<0>, C4<0>; +L_0x1e8d220 .delay 1 (30000,30000,30000) L_0x1e8d220/d; +v0x1d1c950_0 .net *"_s10", 0 0, L_0x1e8d2e0; 1 drivers +v0x1d1ca30_0 .net *"_s12", 0 0, L_0x1e8d490; 1 drivers +v0x1d1cb10_0 .net "in", 7 0, L_0x1e8b220; alias, 1 drivers +v0x1d1cbe0_0 .net "ors", 1 0, L_0x1e8d040; 1 drivers +v0x1d1cca0_0 .net "out", 0 0, L_0x1e8d220; alias, 1 drivers +L_0x1e8c410 .part L_0x1e8b220, 0, 4; +L_0x1e8d040 .concat8 [ 1 1 0 0], L_0x1e8c100, L_0x1e8cd30; +L_0x1e8d180 .part L_0x1e8b220, 4, 4; +L_0x1e8d2e0 .part L_0x1e8d040, 0, 1; +L_0x1e8d490 .part L_0x1e8d040, 1, 1; +S_0x1d1afc0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d1ae00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e8b8c0/d .functor OR 1, L_0x1e8b980, L_0x1e8bae0, C4<0>, C4<0>; +L_0x1e8b8c0 .delay 1 (30000,30000,30000) L_0x1e8b8c0/d; +L_0x1e8bd10/d .functor OR 1, L_0x1e8be20, L_0x1e8bf80, C4<0>, C4<0>; +L_0x1e8bd10 .delay 1 (30000,30000,30000) L_0x1e8bd10/d; +L_0x1e8c100/d .functor OR 1, L_0x1e8c170, L_0x1e8c320, C4<0>, C4<0>; +L_0x1e8c100 .delay 1 (30000,30000,30000) L_0x1e8c100/d; +v0x1d1b210_0 .net *"_s0", 0 0, L_0x1e8b8c0; 1 drivers +v0x1d1b310_0 .net *"_s10", 0 0, L_0x1e8be20; 1 drivers +v0x1d1b3f0_0 .net *"_s12", 0 0, L_0x1e8bf80; 1 drivers +v0x1d1b4b0_0 .net *"_s14", 0 0, L_0x1e8c170; 1 drivers +v0x1d1b590_0 .net *"_s16", 0 0, L_0x1e8c320; 1 drivers +v0x1d1b6c0_0 .net *"_s3", 0 0, L_0x1e8b980; 1 drivers +v0x1d1b7a0_0 .net *"_s5", 0 0, L_0x1e8bae0; 1 drivers +v0x1d1b880_0 .net *"_s6", 0 0, L_0x1e8bd10; 1 drivers +v0x1d1b960_0 .net "in", 3 0, L_0x1e8c410; 1 drivers +v0x1d1bad0_0 .net "ors", 1 0, L_0x1e8bc20; 1 drivers +v0x1d1bbb0_0 .net "out", 0 0, L_0x1e8c100; 1 drivers +L_0x1e8b980 .part L_0x1e8c410, 0, 1; +L_0x1e8bae0 .part L_0x1e8c410, 1, 1; +L_0x1e8bc20 .concat8 [ 1 1 0 0], L_0x1e8b8c0, L_0x1e8bd10; +L_0x1e8be20 .part L_0x1e8c410, 2, 1; +L_0x1e8bf80 .part L_0x1e8c410, 3, 1; +L_0x1e8c170 .part L_0x1e8bc20, 0, 1; +L_0x1e8c320 .part L_0x1e8bc20, 1, 1; +S_0x1d1bcd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d1ae00; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e8c540/d .functor OR 1, L_0x1e8c5b0, L_0x1e8c710, C4<0>, C4<0>; +L_0x1e8c540 .delay 1 (30000,30000,30000) L_0x1e8c540/d; +L_0x1e8c940/d .functor OR 1, L_0x1e8ca50, L_0x1e8cbb0, C4<0>, C4<0>; +L_0x1e8c940 .delay 1 (30000,30000,30000) L_0x1e8c940/d; +L_0x1e8cd30/d .functor OR 1, L_0x1e8cda0, L_0x1e8cf50, C4<0>, C4<0>; +L_0x1e8cd30 .delay 1 (30000,30000,30000) L_0x1e8cd30/d; +v0x1d1be90_0 .net *"_s0", 0 0, L_0x1e8c540; 1 drivers +v0x1d1bf90_0 .net *"_s10", 0 0, L_0x1e8ca50; 1 drivers +v0x1d1c070_0 .net *"_s12", 0 0, L_0x1e8cbb0; 1 drivers +v0x1d1c130_0 .net *"_s14", 0 0, L_0x1e8cda0; 1 drivers +v0x1d1c210_0 .net *"_s16", 0 0, L_0x1e8cf50; 1 drivers +v0x1d1c340_0 .net *"_s3", 0 0, L_0x1e8c5b0; 1 drivers +v0x1d1c420_0 .net *"_s5", 0 0, L_0x1e8c710; 1 drivers +v0x1d1c500_0 .net *"_s6", 0 0, L_0x1e8c940; 1 drivers +v0x1d1c5e0_0 .net "in", 3 0, L_0x1e8d180; 1 drivers +v0x1d1c750_0 .net "ors", 1 0, L_0x1e8c850; 1 drivers +v0x1d1c830_0 .net "out", 0 0, L_0x1e8cd30; 1 drivers +L_0x1e8c5b0 .part L_0x1e8d180, 0, 1; +L_0x1e8c710 .part L_0x1e8d180, 1, 1; +L_0x1e8c850 .concat8 [ 1 1 0 0], L_0x1e8c540, L_0x1e8c940; +L_0x1e8ca50 .part L_0x1e8d180, 2, 1; +L_0x1e8cbb0 .part L_0x1e8d180, 3, 1; +L_0x1e8cda0 .part L_0x1e8c850, 0, 1; +L_0x1e8cf50 .part L_0x1e8c850, 1, 1; +S_0x1d1d140 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d16240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d22570_0 .net "ands", 7 0, L_0x1e877e0; 1 drivers +v0x1d22680_0 .net "in", 7 0, L_0x1e85c40; alias, 1 drivers +v0x1d22740_0 .net "out", 0 0, L_0x1e897e0; alias, 1 drivers +v0x1d22810_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d1d390 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d1d140; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d1fad0_0 .net "A", 7 0, L_0x1e85c40; alias, 1 drivers +v0x1d1fbd0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d1fc90_0 .net *"_s0", 0 0, L_0x1e85fd0; 1 drivers +v0x1d1fd50_0 .net *"_s12", 0 0, L_0x1e86990; 1 drivers +v0x1d1fe30_0 .net *"_s16", 0 0, L_0x1e86cf0; 1 drivers +v0x1d1ff60_0 .net *"_s20", 0 0, L_0x1e87120; 1 drivers +v0x1d20040_0 .net *"_s24", 0 0, L_0x1e87450; 1 drivers +v0x1d20120_0 .net *"_s28", 0 0, L_0x1e873e0; 1 drivers +v0x1d20200_0 .net *"_s4", 0 0, L_0x1e86370; 1 drivers +v0x1d20370_0 .net *"_s8", 0 0, L_0x1e86680; 1 drivers +v0x1d20450_0 .net "out", 7 0, L_0x1e877e0; alias, 1 drivers +L_0x1e860e0 .part L_0x1e85c40, 0, 1; +L_0x1e862d0 .part v0x1d6daa0_0, 0, 1; +L_0x1e86430 .part L_0x1e85c40, 1, 1; +L_0x1e86590 .part v0x1d6daa0_0, 1, 1; +L_0x1e86740 .part L_0x1e85c40, 2, 1; +L_0x1e868a0 .part v0x1d6daa0_0, 2, 1; +L_0x1e86a50 .part L_0x1e85c40, 3, 1; +L_0x1e86bb0 .part v0x1d6daa0_0, 3, 1; +L_0x1e86db0 .part L_0x1e85c40, 4, 1; +L_0x1e87020 .part v0x1d6daa0_0, 4, 1; +L_0x1e87190 .part L_0x1e85c40, 5, 1; +L_0x1e872f0 .part v0x1d6daa0_0, 5, 1; +L_0x1e87510 .part L_0x1e85c40, 6, 1; +L_0x1e87670 .part v0x1d6daa0_0, 6, 1; +LS_0x1e877e0_0_0 .concat8 [ 1 1 1 1], L_0x1e85fd0, L_0x1e86370, L_0x1e86680, L_0x1e86990; +LS_0x1e877e0_0_4 .concat8 [ 1 1 1 1], L_0x1e86cf0, L_0x1e87120, L_0x1e87450, L_0x1e873e0; +L_0x1e877e0 .concat8 [ 4 4 0 0], LS_0x1e877e0_0_0, LS_0x1e877e0_0_4; +L_0x1e87ba0 .part L_0x1e85c40, 7, 1; +L_0x1e87d90 .part v0x1d6daa0_0, 7, 1; +S_0x1d1d5d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1d7e0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e85fd0/d .functor AND 1, L_0x1e860e0, L_0x1e862d0, C4<1>, C4<1>; +L_0x1e85fd0 .delay 1 (30000,30000,30000) L_0x1e85fd0/d; +v0x1d1d8c0_0 .net *"_s0", 0 0, L_0x1e860e0; 1 drivers +v0x1d1d9a0_0 .net *"_s1", 0 0, L_0x1e862d0; 1 drivers +S_0x1d1da80 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1dc90 .param/l "i" 0 4 54, +C4<01>; +L_0x1e86370/d .functor AND 1, L_0x1e86430, L_0x1e86590, C4<1>, C4<1>; +L_0x1e86370 .delay 1 (30000,30000,30000) L_0x1e86370/d; +v0x1d1dd50_0 .net *"_s0", 0 0, L_0x1e86430; 1 drivers +v0x1d1de30_0 .net *"_s1", 0 0, L_0x1e86590; 1 drivers +S_0x1d1df10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1e150 .param/l "i" 0 4 54, +C4<010>; +L_0x1e86680/d .functor AND 1, L_0x1e86740, L_0x1e868a0, C4<1>, C4<1>; +L_0x1e86680 .delay 1 (30000,30000,30000) L_0x1e86680/d; +v0x1d1e1f0_0 .net *"_s0", 0 0, L_0x1e86740; 1 drivers +v0x1d1e2d0_0 .net *"_s1", 0 0, L_0x1e868a0; 1 drivers +S_0x1d1e3b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1e5c0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e86990/d .functor AND 1, L_0x1e86a50, L_0x1e86bb0, C4<1>, C4<1>; +L_0x1e86990 .delay 1 (30000,30000,30000) L_0x1e86990/d; +v0x1d1e680_0 .net *"_s0", 0 0, L_0x1e86a50; 1 drivers +v0x1d1e760_0 .net *"_s1", 0 0, L_0x1e86bb0; 1 drivers +S_0x1d1e840 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1eaa0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e86cf0/d .functor AND 1, L_0x1e86db0, L_0x1e87020, C4<1>, C4<1>; +L_0x1e86cf0 .delay 1 (30000,30000,30000) L_0x1e86cf0/d; +v0x1d1eb60_0 .net *"_s0", 0 0, L_0x1e86db0; 1 drivers +v0x1d1ec40_0 .net *"_s1", 0 0, L_0x1e87020; 1 drivers +S_0x1d1ed20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1ef30 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e87120/d .functor AND 1, L_0x1e87190, L_0x1e872f0, C4<1>, C4<1>; +L_0x1e87120 .delay 1 (30000,30000,30000) L_0x1e87120/d; +v0x1d1eff0_0 .net *"_s0", 0 0, L_0x1e87190; 1 drivers +v0x1d1f0d0_0 .net *"_s1", 0 0, L_0x1e872f0; 1 drivers +S_0x1d1f1b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1f3c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e87450/d .functor AND 1, L_0x1e87510, L_0x1e87670, C4<1>, C4<1>; +L_0x1e87450 .delay 1 (30000,30000,30000) L_0x1e87450/d; +v0x1d1f480_0 .net *"_s0", 0 0, L_0x1e87510; 1 drivers +v0x1d1f560_0 .net *"_s1", 0 0, L_0x1e87670; 1 drivers +S_0x1d1f640 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d1d390; + .timescale -9 -12; +P_0x1d1f850 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e873e0/d .functor AND 1, L_0x1e87ba0, L_0x1e87d90, C4<1>, C4<1>; +L_0x1e873e0 .delay 1 (30000,30000,30000) L_0x1e873e0/d; +v0x1d1f910_0 .net *"_s0", 0 0, L_0x1e87ba0; 1 drivers +v0x1d1f9f0_0 .net *"_s1", 0 0, L_0x1e87d90; 1 drivers +S_0x1d205b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d1d140; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e897e0/d .functor OR 1, L_0x1e898a0, L_0x1e89a50, C4<0>, C4<0>; +L_0x1e897e0 .delay 1 (30000,30000,30000) L_0x1e897e0/d; +v0x1d22100_0 .net *"_s10", 0 0, L_0x1e898a0; 1 drivers +v0x1d221e0_0 .net *"_s12", 0 0, L_0x1e89a50; 1 drivers +v0x1d222c0_0 .net "in", 7 0, L_0x1e877e0; alias, 1 drivers +v0x1d22390_0 .net "ors", 1 0, L_0x1e89600; 1 drivers +v0x1d22450_0 .net "out", 0 0, L_0x1e897e0; alias, 1 drivers +L_0x1e889d0 .part L_0x1e877e0, 0, 4; +L_0x1e89600 .concat8 [ 1 1 0 0], L_0x1e886c0, L_0x1e892f0; +L_0x1e89740 .part L_0x1e877e0, 4, 4; +L_0x1e898a0 .part L_0x1e89600, 0, 1; +L_0x1e89a50 .part L_0x1e89600, 1, 1; +S_0x1d20770 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d205b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e87e80/d .functor OR 1, L_0x1e87f40, L_0x1e880a0, C4<0>, C4<0>; +L_0x1e87e80 .delay 1 (30000,30000,30000) L_0x1e87e80/d; +L_0x1e882d0/d .functor OR 1, L_0x1e883e0, L_0x1e88540, C4<0>, C4<0>; +L_0x1e882d0 .delay 1 (30000,30000,30000) L_0x1e882d0/d; +L_0x1e886c0/d .functor OR 1, L_0x1e88730, L_0x1e888e0, C4<0>, C4<0>; +L_0x1e886c0 .delay 1 (30000,30000,30000) L_0x1e886c0/d; +v0x1d209c0_0 .net *"_s0", 0 0, L_0x1e87e80; 1 drivers +v0x1d20ac0_0 .net *"_s10", 0 0, L_0x1e883e0; 1 drivers +v0x1d20ba0_0 .net *"_s12", 0 0, L_0x1e88540; 1 drivers +v0x1d20c60_0 .net *"_s14", 0 0, L_0x1e88730; 1 drivers +v0x1d20d40_0 .net *"_s16", 0 0, L_0x1e888e0; 1 drivers +v0x1d20e70_0 .net *"_s3", 0 0, L_0x1e87f40; 1 drivers +v0x1d20f50_0 .net *"_s5", 0 0, L_0x1e880a0; 1 drivers +v0x1d21030_0 .net *"_s6", 0 0, L_0x1e882d0; 1 drivers +v0x1d21110_0 .net "in", 3 0, L_0x1e889d0; 1 drivers +v0x1d21280_0 .net "ors", 1 0, L_0x1e881e0; 1 drivers +v0x1d21360_0 .net "out", 0 0, L_0x1e886c0; 1 drivers +L_0x1e87f40 .part L_0x1e889d0, 0, 1; +L_0x1e880a0 .part L_0x1e889d0, 1, 1; +L_0x1e881e0 .concat8 [ 1 1 0 0], L_0x1e87e80, L_0x1e882d0; +L_0x1e883e0 .part L_0x1e889d0, 2, 1; +L_0x1e88540 .part L_0x1e889d0, 3, 1; +L_0x1e88730 .part L_0x1e881e0, 0, 1; +L_0x1e888e0 .part L_0x1e881e0, 1, 1; +S_0x1d21480 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d205b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e88b00/d .functor OR 1, L_0x1e88b70, L_0x1e88cd0, C4<0>, C4<0>; +L_0x1e88b00 .delay 1 (30000,30000,30000) L_0x1e88b00/d; +L_0x1e88f00/d .functor OR 1, L_0x1e89010, L_0x1e89170, C4<0>, C4<0>; +L_0x1e88f00 .delay 1 (30000,30000,30000) L_0x1e88f00/d; +L_0x1e892f0/d .functor OR 1, L_0x1e89360, L_0x1e89510, C4<0>, C4<0>; +L_0x1e892f0 .delay 1 (30000,30000,30000) L_0x1e892f0/d; +v0x1d21640_0 .net *"_s0", 0 0, L_0x1e88b00; 1 drivers +v0x1d21740_0 .net *"_s10", 0 0, L_0x1e89010; 1 drivers +v0x1d21820_0 .net *"_s12", 0 0, L_0x1e89170; 1 drivers +v0x1d218e0_0 .net *"_s14", 0 0, L_0x1e89360; 1 drivers +v0x1d219c0_0 .net *"_s16", 0 0, L_0x1e89510; 1 drivers +v0x1d21af0_0 .net *"_s3", 0 0, L_0x1e88b70; 1 drivers +v0x1d21bd0_0 .net *"_s5", 0 0, L_0x1e88cd0; 1 drivers +v0x1d21cb0_0 .net *"_s6", 0 0, L_0x1e88f00; 1 drivers +v0x1d21d90_0 .net "in", 3 0, L_0x1e89740; 1 drivers +v0x1d21f00_0 .net "ors", 1 0, L_0x1e88e10; 1 drivers +v0x1d21fe0_0 .net "out", 0 0, L_0x1e892f0; 1 drivers +L_0x1e88b70 .part L_0x1e89740, 0, 1; +L_0x1e88cd0 .part L_0x1e89740, 1, 1; +L_0x1e88e10 .concat8 [ 1 1 0 0], L_0x1e88b00, L_0x1e88f00; +L_0x1e89010 .part L_0x1e89740, 2, 1; +L_0x1e89170 .part L_0x1e89740, 3, 1; +L_0x1e89360 .part L_0x1e88e10, 0, 1; +L_0x1e89510 .part L_0x1e88e10, 1, 1; +S_0x1d228f0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d16240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e84fb0/d .functor XNOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; +L_0x1e84fb0 .delay 1 (20000,20000,20000) L_0x1e84fb0/d; +L_0x1e85220/d .functor AND 1, L_0x1e8d680, L_0x1e83ef0, C4<1>, C4<1>; +L_0x1e85220 .delay 1 (30000,30000,30000) L_0x1e85220/d; +L_0x1e85290/d .functor AND 1, L_0x1e84fb0, L_0x1e83ba0, C4<1>, C4<1>; +L_0x1e85290 .delay 1 (30000,30000,30000) L_0x1e85290/d; +L_0x1e853f0/d .functor OR 1, L_0x1e85290, L_0x1e85220, C4<0>, C4<0>; +L_0x1e853f0 .delay 1 (30000,30000,30000) L_0x1e853f0/d; +v0x1d22ba0_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers +v0x1d22c90_0 .net "a_", 0 0, L_0x1e7a1b0; alias, 1 drivers +v0x1d22d50_0 .net "b", 0 0, L_0x1e8d7e0; alias, 1 drivers +v0x1d22e40_0 .net "b_", 0 0, L_0x1e83ef0; alias, 1 drivers +v0x1d22ee0_0 .net "carryin", 0 0, L_0x1e83ba0; alias, 1 drivers +v0x1d23020_0 .net "eq", 0 0, L_0x1e84fb0; 1 drivers +v0x1d230e0_0 .net "lt", 0 0, L_0x1e85220; 1 drivers +v0x1d231a0_0 .net "out", 0 0, L_0x1e853f0; 1 drivers +v0x1d23260_0 .net "w0", 0 0, L_0x1e85290; 1 drivers +S_0x1d234b0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d16240; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e84d90/d .functor OR 1, L_0x1e848e0, L_0x1d24710, C4<0>, C4<0>; +L_0x1e84d90 .delay 1 (30000,30000,30000) L_0x1e84d90/d; +v0x1d242a0_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers +v0x1d243f0_0 .net "b", 0 0, L_0x1e83ef0; alias, 1 drivers +v0x1d244b0_0 .net "c1", 0 0, L_0x1e848e0; 1 drivers +v0x1d24550_0 .net "c2", 0 0, L_0x1d24710; 1 drivers +v0x1d24620_0 .net "carryin", 0 0, L_0x1e83ba0; alias, 1 drivers +v0x1d247a0_0 .net "carryout", 0 0, L_0x1e84d90; 1 drivers +v0x1d24840_0 .net "s1", 0 0, L_0x1e84820; 1 drivers +v0x1d248e0_0 .net "sum", 0 0, L_0x1e84a40; 1 drivers +S_0x1d23700 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d234b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e84820/d .functor XOR 1, L_0x1e8d680, L_0x1e83ef0, C4<0>, C4<0>; +L_0x1e84820 .delay 1 (30000,30000,30000) L_0x1e84820/d; +L_0x1e848e0/d .functor AND 1, L_0x1e8d680, L_0x1e83ef0, C4<1>, C4<1>; +L_0x1e848e0 .delay 1 (30000,30000,30000) L_0x1e848e0/d; +v0x1d23960_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers +v0x1d23a20_0 .net "b", 0 0, L_0x1e83ef0; alias, 1 drivers +v0x1d23ae0_0 .net "carryout", 0 0, L_0x1e848e0; alias, 1 drivers +v0x1d23b80_0 .net "sum", 0 0, L_0x1e84820; alias, 1 drivers +S_0x1d23cb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d234b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e84a40/d .functor XOR 1, L_0x1e84820, L_0x1e83ba0, C4<0>, C4<0>; +L_0x1e84a40 .delay 1 (30000,30000,30000) L_0x1e84a40/d; +L_0x1d24710/d .functor AND 1, L_0x1e84820, L_0x1e83ba0, C4<1>, C4<1>; +L_0x1d24710 .delay 1 (30000,30000,30000) L_0x1d24710/d; +v0x1d23f10_0 .net "a", 0 0, L_0x1e84820; alias, 1 drivers +v0x1d23fe0_0 .net "b", 0 0, L_0x1e83ba0; alias, 1 drivers +v0x1d24080_0 .net "carryout", 0 0, L_0x1d24710; alias, 1 drivers +v0x1d24150_0 .net "sum", 0 0, L_0x1e84a40; alias, 1 drivers +S_0x1d25d00 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d15f70; + .timescale -9 -12; +L_0x7f72592dbf98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dbfe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e8d720/d .functor OR 1, L_0x7f72592dbf98, L_0x7f72592dbfe0, C4<0>, C4<0>; +L_0x1e8d720 .delay 1 (30000,30000,30000) L_0x1e8d720/d; +v0x1d25ef0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbf98; 1 drivers +v0x1d25fd0_0 .net/2u *"_s2", 0 0, L_0x7f72592dbfe0; 1 drivers +S_0x1d260b0 .scope generate, "alu_slices[29]" "alu_slices[29]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1d262c0 .param/l "i" 0 3 37, +C4<011101>; +S_0x1d26380 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d260b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e83ce0/d .functor NOT 1, L_0x1e97290, C4<0>, C4<0>, C4<0>; +L_0x1e83ce0 .delay 1 (10000,10000,10000) L_0x1e83ce0/d; +L_0x1e8db90/d .functor NOT 1, L_0x1e8d880, C4<0>, C4<0>, C4<0>; +L_0x1e8db90 .delay 1 (10000,10000,10000) L_0x1e8db90/d; +L_0x1e8ebe0/d .functor XOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; +L_0x1e8ebe0 .delay 1 (30000,30000,30000) L_0x1e8ebe0/d; +L_0x7f72592dc028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dc070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e8f290/d .functor OR 1, L_0x7f72592dc028, L_0x7f72592dc070, C4<0>, C4<0>; +L_0x1e8f290 .delay 1 (30000,30000,30000) L_0x1e8f290/d; +L_0x1e8f490/d .functor AND 1, L_0x1e97290, L_0x1e8d880, C4<1>, C4<1>; +L_0x1e8f490 .delay 1 (30000,30000,30000) L_0x1e8f490/d; +L_0x1e8f550/d .functor NAND 1, L_0x1e97290, L_0x1e8d880, C4<1>, C4<1>; +L_0x1e8f550 .delay 1 (20000,20000,20000) L_0x1e8f550/d; +L_0x1e8f6b0/d .functor XOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; +L_0x1e8f6b0 .delay 1 (20000,20000,20000) L_0x1e8f6b0/d; +L_0x1e8fb60/d .functor OR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; +L_0x1e8fb60 .delay 1 (30000,30000,30000) L_0x1e8fb60/d; +L_0x1e97190/d .functor NOT 1, L_0x1e933f0, C4<0>, C4<0>, C4<0>; +L_0x1e97190 .delay 1 (10000,10000,10000) L_0x1e97190/d; +v0x1d34ab0_0 .net "A", 0 0, L_0x1e97290; 1 drivers +v0x1d34b70_0 .net "A_", 0 0, L_0x1e83ce0; 1 drivers +v0x1d34c30_0 .net "B", 0 0, L_0x1e8d880; 1 drivers +v0x1d34d00_0 .net "B_", 0 0, L_0x1e8db90; 1 drivers +v0x1d34da0_0 .net *"_s12", 0 0, L_0x1e8f290; 1 drivers +v0x1d34e90_0 .net/2s *"_s14", 0 0, L_0x7f72592dc028; 1 drivers +v0x1d34f50_0 .net/2s *"_s16", 0 0, L_0x7f72592dc070; 1 drivers +v0x1d35030_0 .net *"_s18", 0 0, L_0x1e8f490; 1 drivers +v0x1d35110_0 .net *"_s20", 0 0, L_0x1e8f550; 1 drivers +v0x1d35280_0 .net *"_s22", 0 0, L_0x1e8f6b0; 1 drivers +v0x1d35360_0 .net *"_s24", 0 0, L_0x1e8fb60; 1 drivers +o0x7f7259338cd8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1d35440_0 name=_s30 +o0x7f7259338d08 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1d35520_0 name=_s32 +v0x1d35600_0 .net *"_s8", 0 0, L_0x1e8ebe0; 1 drivers +v0x1d356e0_0 .net "carryin", 0 0, L_0x1e8d920; 1 drivers +v0x1d35780_0 .net "carryout", 0 0, L_0x1e96e30; 1 drivers +v0x1d35820_0 .net "carryouts", 7 0, L_0x1ec1d80; 1 drivers +v0x1d359d0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d35a70_0 .net "result", 0 0, L_0x1e933f0; 1 drivers +v0x1d35b60_0 .net "results", 7 0, L_0x1e8f930; 1 drivers +v0x1d35c70_0 .net "zero", 0 0, L_0x1e97190; 1 drivers +LS_0x1e8f930_0_0 .concat8 [ 1 1 1 1], L_0x1e8e0b0, L_0x1e8e6e0, L_0x1e8ebe0, L_0x1e8f290; +LS_0x1e8f930_0_4 .concat8 [ 1 1 1 1], L_0x1e8f490, L_0x1e8f550, L_0x1e8f6b0, L_0x1e8fb60; +L_0x1e8f930 .concat8 [ 4 4 0 0], LS_0x1e8f930_0_0, LS_0x1e8f930_0_4; +LS_0x1ec1d80_0_0 .concat [ 1 1 1 1], L_0x1e8e360, L_0x1e8ea80, o0x7f7259338cd8, L_0x1e8f0e0; +LS_0x1ec1d80_0_4 .concat [ 4 0 0 0], o0x7f7259338d08; +L_0x1ec1d80 .concat [ 4 4 0 0], LS_0x1ec1d80_0_0, LS_0x1ec1d80_0_4; +S_0x1d26600 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d26380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e8e360/d .functor OR 1, L_0x1e8de40, L_0x1e8e200, C4<0>, C4<0>; +L_0x1e8e360 .delay 1 (30000,30000,30000) L_0x1e8e360/d; +v0x1d27430_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers +v0x1d274f0_0 .net "b", 0 0, L_0x1e8d880; alias, 1 drivers +v0x1d275c0_0 .net "c1", 0 0, L_0x1e8de40; 1 drivers +v0x1d276c0_0 .net "c2", 0 0, L_0x1e8e200; 1 drivers +v0x1d27790_0 .net "carryin", 0 0, L_0x1e8d920; alias, 1 drivers +v0x1d27880_0 .net "carryout", 0 0, L_0x1e8e360; 1 drivers +v0x1d27920_0 .net "s1", 0 0, L_0x1e8dd80; 1 drivers +v0x1d27a10_0 .net "sum", 0 0, L_0x1e8e0b0; 1 drivers +S_0x1d26870 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d26600; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e8dd80/d .functor XOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; +L_0x1e8dd80 .delay 1 (30000,30000,30000) L_0x1e8dd80/d; +L_0x1e8de40/d .functor AND 1, L_0x1e97290, L_0x1e8d880, C4<1>, C4<1>; +L_0x1e8de40 .delay 1 (30000,30000,30000) L_0x1e8de40/d; +v0x1d26ad0_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers +v0x1d26bb0_0 .net "b", 0 0, L_0x1e8d880; alias, 1 drivers +v0x1d26c70_0 .net "carryout", 0 0, L_0x1e8de40; alias, 1 drivers +v0x1d26d10_0 .net "sum", 0 0, L_0x1e8dd80; alias, 1 drivers +S_0x1d26e50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d26600; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e8e0b0/d .functor XOR 1, L_0x1e8dd80, L_0x1e8d920, C4<0>, C4<0>; +L_0x1e8e0b0 .delay 1 (30000,30000,30000) L_0x1e8e0b0/d; +L_0x1e8e200/d .functor AND 1, L_0x1e8dd80, L_0x1e8d920, C4<1>, C4<1>; +L_0x1e8e200 .delay 1 (30000,30000,30000) L_0x1e8e200/d; +v0x1d270b0_0 .net "a", 0 0, L_0x1e8dd80; alias, 1 drivers +v0x1d27150_0 .net "b", 0 0, L_0x1e8d920; alias, 1 drivers +v0x1d271f0_0 .net "carryout", 0 0, L_0x1e8e200; alias, 1 drivers +v0x1d272c0_0 .net "sum", 0 0, L_0x1e8e0b0; alias, 1 drivers +S_0x1d27ae0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d26380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d2ced0_0 .net "ands", 7 0, L_0x1e94e30; 1 drivers +v0x1d2cfe0_0 .net "in", 7 0, L_0x1ec1d80; alias, 1 drivers +v0x1d2d0a0_0 .net "out", 0 0, L_0x1e96e30; alias, 1 drivers +v0x1d2d170_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d27d00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d27ae0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d2a430_0 .net "A", 7 0, L_0x1ec1d80; alias, 1 drivers +v0x1d2a530_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d2a5f0_0 .net *"_s0", 0 0, L_0x1e93750; 1 drivers +v0x1d2a6b0_0 .net *"_s12", 0 0, L_0x1e940c0; 1 drivers +v0x1d2a790_0 .net *"_s16", 0 0, L_0x1e94420; 1 drivers +v0x1d2a8c0_0 .net *"_s20", 0 0, L_0x1e94730; 1 drivers +v0x1d2a9a0_0 .net *"_s24", 0 0, L_0x1e94b20; 1 drivers +v0x1d2aa80_0 .net *"_s28", 0 0, L_0x1e94ab0; 1 drivers +v0x1d2ab60_0 .net *"_s4", 0 0, L_0x1e93a60; 1 drivers +v0x1d2acd0_0 .net *"_s8", 0 0, L_0x1e93db0; 1 drivers +v0x1d2adb0_0 .net "out", 7 0, L_0x1e94e30; alias, 1 drivers +L_0x1e93810 .part L_0x1ec1d80, 0, 1; +L_0x1e93970 .part v0x1d6daa0_0, 0, 1; +L_0x1e93b20 .part L_0x1ec1d80, 1, 1; +L_0x1e93d10 .part v0x1d6daa0_0, 1, 1; +L_0x1e93e70 .part L_0x1ec1d80, 2, 1; +L_0x1e93fd0 .part v0x1d6daa0_0, 2, 1; +L_0x1e94180 .part L_0x1ec1d80, 3, 1; +L_0x1e942e0 .part v0x1d6daa0_0, 3, 1; +L_0x1e944e0 .part L_0x1ec1d80, 4, 1; +L_0x1e94640 .part v0x1d6daa0_0, 4, 1; +L_0x1e947a0 .part L_0x1ec1d80, 5, 1; +L_0x1e94a10 .part v0x1d6daa0_0, 5, 1; +L_0x1e94be0 .part L_0x1ec1d80, 6, 1; +L_0x1e94d40 .part v0x1d6daa0_0, 6, 1; +LS_0x1e94e30_0_0 .concat8 [ 1 1 1 1], L_0x1e93750, L_0x1e93a60, L_0x1e93db0, L_0x1e940c0; +LS_0x1e94e30_0_4 .concat8 [ 1 1 1 1], L_0x1e94420, L_0x1e94730, L_0x1e94b20, L_0x1e94ab0; +L_0x1e94e30 .concat8 [ 4 4 0 0], LS_0x1e94e30_0_0, LS_0x1e94e30_0_4; +L_0x1e951f0 .part L_0x1ec1d80, 7, 1; +L_0x1e953e0 .part v0x1d6daa0_0, 7, 1; +S_0x1d27f60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d28170 .param/l "i" 0 4 54, +C4<00>; +L_0x1e93750/d .functor AND 1, L_0x1e93810, L_0x1e93970, C4<1>, C4<1>; +L_0x1e93750 .delay 1 (30000,30000,30000) L_0x1e93750/d; +v0x1d28250_0 .net *"_s0", 0 0, L_0x1e93810; 1 drivers +v0x1d28330_0 .net *"_s1", 0 0, L_0x1e93970; 1 drivers +S_0x1d28410 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d28620 .param/l "i" 0 4 54, +C4<01>; +L_0x1e93a60/d .functor AND 1, L_0x1e93b20, L_0x1e93d10, C4<1>, C4<1>; +L_0x1e93a60 .delay 1 (30000,30000,30000) L_0x1e93a60/d; +v0x1d286e0_0 .net *"_s0", 0 0, L_0x1e93b20; 1 drivers +v0x1d287c0_0 .net *"_s1", 0 0, L_0x1e93d10; 1 drivers +S_0x1d288a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d28ab0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e93db0/d .functor AND 1, L_0x1e93e70, L_0x1e93fd0, C4<1>, C4<1>; +L_0x1e93db0 .delay 1 (30000,30000,30000) L_0x1e93db0/d; +v0x1d28b50_0 .net *"_s0", 0 0, L_0x1e93e70; 1 drivers +v0x1d28c30_0 .net *"_s1", 0 0, L_0x1e93fd0; 1 drivers +S_0x1d28d10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d28f20 .param/l "i" 0 4 54, +C4<011>; +L_0x1e940c0/d .functor AND 1, L_0x1e94180, L_0x1e942e0, C4<1>, C4<1>; +L_0x1e940c0 .delay 1 (30000,30000,30000) L_0x1e940c0/d; +v0x1d28fe0_0 .net *"_s0", 0 0, L_0x1e94180; 1 drivers +v0x1d290c0_0 .net *"_s1", 0 0, L_0x1e942e0; 1 drivers +S_0x1d291a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d29400 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e94420/d .functor AND 1, L_0x1e944e0, L_0x1e94640, C4<1>, C4<1>; +L_0x1e94420 .delay 1 (30000,30000,30000) L_0x1e94420/d; +v0x1d294c0_0 .net *"_s0", 0 0, L_0x1e944e0; 1 drivers +v0x1d295a0_0 .net *"_s1", 0 0, L_0x1e94640; 1 drivers +S_0x1d29680 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d29890 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e94730/d .functor AND 1, L_0x1e947a0, L_0x1e94a10, C4<1>, C4<1>; +L_0x1e94730 .delay 1 (30000,30000,30000) L_0x1e94730/d; +v0x1d29950_0 .net *"_s0", 0 0, L_0x1e947a0; 1 drivers +v0x1d29a30_0 .net *"_s1", 0 0, L_0x1e94a10; 1 drivers +S_0x1d29b10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d29d20 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e94b20/d .functor AND 1, L_0x1e94be0, L_0x1e94d40, C4<1>, C4<1>; +L_0x1e94b20 .delay 1 (30000,30000,30000) L_0x1e94b20/d; +v0x1d29de0_0 .net *"_s0", 0 0, L_0x1e94be0; 1 drivers +v0x1d29ec0_0 .net *"_s1", 0 0, L_0x1e94d40; 1 drivers +S_0x1d29fa0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d27d00; + .timescale -9 -12; +P_0x1d2a1b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e94ab0/d .functor AND 1, L_0x1e951f0, L_0x1e953e0, C4<1>, C4<1>; +L_0x1e94ab0 .delay 1 (30000,30000,30000) L_0x1e94ab0/d; +v0x1d2a270_0 .net *"_s0", 0 0, L_0x1e951f0; 1 drivers +v0x1d2a350_0 .net *"_s1", 0 0, L_0x1e953e0; 1 drivers +S_0x1d2af10 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d27ae0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e96e30/d .functor OR 1, L_0x1e96ef0, L_0x1e970a0, C4<0>, C4<0>; +L_0x1e96e30 .delay 1 (30000,30000,30000) L_0x1e96e30/d; +v0x1d2ca60_0 .net *"_s10", 0 0, L_0x1e96ef0; 1 drivers +v0x1d2cb40_0 .net *"_s12", 0 0, L_0x1e970a0; 1 drivers +v0x1d2cc20_0 .net "in", 7 0, L_0x1e94e30; alias, 1 drivers +v0x1d2ccf0_0 .net "ors", 1 0, L_0x1e96c50; 1 drivers +v0x1d2cdb0_0 .net "out", 0 0, L_0x1e96e30; alias, 1 drivers +L_0x1e96020 .part L_0x1e94e30, 0, 4; +L_0x1e96c50 .concat8 [ 1 1 0 0], L_0x1e95d10, L_0x1e96940; +L_0x1e96d90 .part L_0x1e94e30, 4, 4; +L_0x1e96ef0 .part L_0x1e96c50, 0, 1; +L_0x1e970a0 .part L_0x1e96c50, 1, 1; +S_0x1d2b0d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d2af10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e954d0/d .functor OR 1, L_0x1e95590, L_0x1e956f0, C4<0>, C4<0>; +L_0x1e954d0 .delay 1 (30000,30000,30000) L_0x1e954d0/d; +L_0x1e95920/d .functor OR 1, L_0x1e95a30, L_0x1e95b90, C4<0>, C4<0>; +L_0x1e95920 .delay 1 (30000,30000,30000) L_0x1e95920/d; +L_0x1e95d10/d .functor OR 1, L_0x1e95d80, L_0x1e95f30, C4<0>, C4<0>; +L_0x1e95d10 .delay 1 (30000,30000,30000) L_0x1e95d10/d; +v0x1d2b320_0 .net *"_s0", 0 0, L_0x1e954d0; 1 drivers +v0x1d2b420_0 .net *"_s10", 0 0, L_0x1e95a30; 1 drivers +v0x1d2b500_0 .net *"_s12", 0 0, L_0x1e95b90; 1 drivers +v0x1d2b5c0_0 .net *"_s14", 0 0, L_0x1e95d80; 1 drivers +v0x1d2b6a0_0 .net *"_s16", 0 0, L_0x1e95f30; 1 drivers +v0x1d2b7d0_0 .net *"_s3", 0 0, L_0x1e95590; 1 drivers +v0x1d2b8b0_0 .net *"_s5", 0 0, L_0x1e956f0; 1 drivers +v0x1d2b990_0 .net *"_s6", 0 0, L_0x1e95920; 1 drivers +v0x1d2ba70_0 .net "in", 3 0, L_0x1e96020; 1 drivers +v0x1d2bbe0_0 .net "ors", 1 0, L_0x1e95830; 1 drivers +v0x1d2bcc0_0 .net "out", 0 0, L_0x1e95d10; 1 drivers +L_0x1e95590 .part L_0x1e96020, 0, 1; +L_0x1e956f0 .part L_0x1e96020, 1, 1; +L_0x1e95830 .concat8 [ 1 1 0 0], L_0x1e954d0, L_0x1e95920; +L_0x1e95a30 .part L_0x1e96020, 2, 1; +L_0x1e95b90 .part L_0x1e96020, 3, 1; +L_0x1e95d80 .part L_0x1e95830, 0, 1; +L_0x1e95f30 .part L_0x1e95830, 1, 1; +S_0x1d2bde0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d2af10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e96150/d .functor OR 1, L_0x1e961c0, L_0x1e96320, C4<0>, C4<0>; +L_0x1e96150 .delay 1 (30000,30000,30000) L_0x1e96150/d; +L_0x1e96550/d .functor OR 1, L_0x1e96660, L_0x1e967c0, C4<0>, C4<0>; +L_0x1e96550 .delay 1 (30000,30000,30000) L_0x1e96550/d; +L_0x1e96940/d .functor OR 1, L_0x1e969b0, L_0x1e96b60, C4<0>, C4<0>; +L_0x1e96940 .delay 1 (30000,30000,30000) L_0x1e96940/d; +v0x1d2bfa0_0 .net *"_s0", 0 0, L_0x1e96150; 1 drivers +v0x1d2c0a0_0 .net *"_s10", 0 0, L_0x1e96660; 1 drivers +v0x1d2c180_0 .net *"_s12", 0 0, L_0x1e967c0; 1 drivers +v0x1d2c240_0 .net *"_s14", 0 0, L_0x1e969b0; 1 drivers +v0x1d2c320_0 .net *"_s16", 0 0, L_0x1e96b60; 1 drivers +v0x1d2c450_0 .net *"_s3", 0 0, L_0x1e961c0; 1 drivers +v0x1d2c530_0 .net *"_s5", 0 0, L_0x1e96320; 1 drivers +v0x1d2c610_0 .net *"_s6", 0 0, L_0x1e96550; 1 drivers +v0x1d2c6f0_0 .net "in", 3 0, L_0x1e96d90; 1 drivers +v0x1d2c860_0 .net "ors", 1 0, L_0x1e96460; 1 drivers +v0x1d2c940_0 .net "out", 0 0, L_0x1e96940; 1 drivers +L_0x1e961c0 .part L_0x1e96d90, 0, 1; +L_0x1e96320 .part L_0x1e96d90, 1, 1; +L_0x1e96460 .concat8 [ 1 1 0 0], L_0x1e96150, L_0x1e96550; +L_0x1e96660 .part L_0x1e96d90, 2, 1; +L_0x1e967c0 .part L_0x1e96d90, 3, 1; +L_0x1e969b0 .part L_0x1e96460, 0, 1; +L_0x1e96b60 .part L_0x1e96460, 1, 1; +S_0x1d2d250 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d26380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d32680_0 .net "ands", 7 0, L_0x1e913f0; 1 drivers +v0x1d32790_0 .net "in", 7 0, L_0x1e8f930; alias, 1 drivers +v0x1d32850_0 .net "out", 0 0, L_0x1e933f0; alias, 1 drivers +v0x1d32920_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d2d4a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d2d250; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d2fbe0_0 .net "A", 7 0, L_0x1e8f930; alias, 1 drivers +v0x1d2fce0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d2fda0_0 .net *"_s0", 0 0, L_0x1e8fcc0; 1 drivers +v0x1d2fe60_0 .net *"_s12", 0 0, L_0x1e90680; 1 drivers +v0x1d2ff40_0 .net *"_s16", 0 0, L_0x1e909e0; 1 drivers +v0x1d30070_0 .net *"_s20", 0 0, L_0x1e90db0; 1 drivers +v0x1d30150_0 .net *"_s24", 0 0, L_0x1e910e0; 1 drivers +v0x1d30230_0 .net *"_s28", 0 0, L_0x1e91070; 1 drivers +v0x1d30310_0 .net *"_s4", 0 0, L_0x1e90060; 1 drivers +v0x1d30480_0 .net *"_s8", 0 0, L_0x1e90370; 1 drivers +v0x1d30560_0 .net "out", 7 0, L_0x1e913f0; alias, 1 drivers +L_0x1e8fdd0 .part L_0x1e8f930, 0, 1; +L_0x1e8ffc0 .part v0x1d6daa0_0, 0, 1; +L_0x1e90120 .part L_0x1e8f930, 1, 1; +L_0x1e90280 .part v0x1d6daa0_0, 1, 1; +L_0x1e90430 .part L_0x1e8f930, 2, 1; +L_0x1e90590 .part v0x1d6daa0_0, 2, 1; +L_0x1e90740 .part L_0x1e8f930, 3, 1; +L_0x1e908a0 .part v0x1d6daa0_0, 3, 1; +L_0x1e90aa0 .part L_0x1e8f930, 4, 1; +L_0x1e90d10 .part v0x1d6daa0_0, 4, 1; +L_0x1e90e20 .part L_0x1e8f930, 5, 1; +L_0x1e90f80 .part v0x1d6daa0_0, 5, 1; +L_0x1e911a0 .part L_0x1e8f930, 6, 1; +L_0x1e91300 .part v0x1d6daa0_0, 6, 1; +LS_0x1e913f0_0_0 .concat8 [ 1 1 1 1], L_0x1e8fcc0, L_0x1e90060, L_0x1e90370, L_0x1e90680; +LS_0x1e913f0_0_4 .concat8 [ 1 1 1 1], L_0x1e909e0, L_0x1e90db0, L_0x1e910e0, L_0x1e91070; +L_0x1e913f0 .concat8 [ 4 4 0 0], LS_0x1e913f0_0_0, LS_0x1e913f0_0_4; +L_0x1e917b0 .part L_0x1e8f930, 7, 1; +L_0x1e919a0 .part v0x1d6daa0_0, 7, 1; +S_0x1d2d6e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2d8f0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e8fcc0/d .functor AND 1, L_0x1e8fdd0, L_0x1e8ffc0, C4<1>, C4<1>; +L_0x1e8fcc0 .delay 1 (30000,30000,30000) L_0x1e8fcc0/d; +v0x1d2d9d0_0 .net *"_s0", 0 0, L_0x1e8fdd0; 1 drivers +v0x1d2dab0_0 .net *"_s1", 0 0, L_0x1e8ffc0; 1 drivers +S_0x1d2db90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2dda0 .param/l "i" 0 4 54, +C4<01>; +L_0x1e90060/d .functor AND 1, L_0x1e90120, L_0x1e90280, C4<1>, C4<1>; +L_0x1e90060 .delay 1 (30000,30000,30000) L_0x1e90060/d; +v0x1d2de60_0 .net *"_s0", 0 0, L_0x1e90120; 1 drivers +v0x1d2df40_0 .net *"_s1", 0 0, L_0x1e90280; 1 drivers +S_0x1d2e020 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2e260 .param/l "i" 0 4 54, +C4<010>; +L_0x1e90370/d .functor AND 1, L_0x1e90430, L_0x1e90590, C4<1>, C4<1>; +L_0x1e90370 .delay 1 (30000,30000,30000) L_0x1e90370/d; +v0x1d2e300_0 .net *"_s0", 0 0, L_0x1e90430; 1 drivers +v0x1d2e3e0_0 .net *"_s1", 0 0, L_0x1e90590; 1 drivers +S_0x1d2e4c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2e6d0 .param/l "i" 0 4 54, +C4<011>; +L_0x1e90680/d .functor AND 1, L_0x1e90740, L_0x1e908a0, C4<1>, C4<1>; +L_0x1e90680 .delay 1 (30000,30000,30000) L_0x1e90680/d; +v0x1d2e790_0 .net *"_s0", 0 0, L_0x1e90740; 1 drivers +v0x1d2e870_0 .net *"_s1", 0 0, L_0x1e908a0; 1 drivers +S_0x1d2e950 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2ebb0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e909e0/d .functor AND 1, L_0x1e90aa0, L_0x1e90d10, C4<1>, C4<1>; +L_0x1e909e0 .delay 1 (30000,30000,30000) L_0x1e909e0/d; +v0x1d2ec70_0 .net *"_s0", 0 0, L_0x1e90aa0; 1 drivers +v0x1d2ed50_0 .net *"_s1", 0 0, L_0x1e90d10; 1 drivers +S_0x1d2ee30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2f040 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e90db0/d .functor AND 1, L_0x1e90e20, L_0x1e90f80, C4<1>, C4<1>; +L_0x1e90db0 .delay 1 (30000,30000,30000) L_0x1e90db0/d; +v0x1d2f100_0 .net *"_s0", 0 0, L_0x1e90e20; 1 drivers +v0x1d2f1e0_0 .net *"_s1", 0 0, L_0x1e90f80; 1 drivers +S_0x1d2f2c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2f4d0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e910e0/d .functor AND 1, L_0x1e911a0, L_0x1e91300, C4<1>, C4<1>; +L_0x1e910e0 .delay 1 (30000,30000,30000) L_0x1e910e0/d; +v0x1d2f590_0 .net *"_s0", 0 0, L_0x1e911a0; 1 drivers +v0x1d2f670_0 .net *"_s1", 0 0, L_0x1e91300; 1 drivers +S_0x1d2f750 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d2d4a0; + .timescale -9 -12; +P_0x1d2f960 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e91070/d .functor AND 1, L_0x1e917b0, L_0x1e919a0, C4<1>, C4<1>; +L_0x1e91070 .delay 1 (30000,30000,30000) L_0x1e91070/d; +v0x1d2fa20_0 .net *"_s0", 0 0, L_0x1e917b0; 1 drivers +v0x1d2fb00_0 .net *"_s1", 0 0, L_0x1e919a0; 1 drivers +S_0x1d306c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d2d250; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e933f0/d .functor OR 1, L_0x1e934b0, L_0x1e93660, C4<0>, C4<0>; +L_0x1e933f0 .delay 1 (30000,30000,30000) L_0x1e933f0/d; +v0x1d32210_0 .net *"_s10", 0 0, L_0x1e934b0; 1 drivers +v0x1d322f0_0 .net *"_s12", 0 0, L_0x1e93660; 1 drivers +v0x1d323d0_0 .net "in", 7 0, L_0x1e913f0; alias, 1 drivers +v0x1d324a0_0 .net "ors", 1 0, L_0x1e93210; 1 drivers +v0x1d32560_0 .net "out", 0 0, L_0x1e933f0; alias, 1 drivers +L_0x1e925e0 .part L_0x1e913f0, 0, 4; +L_0x1e93210 .concat8 [ 1 1 0 0], L_0x1e922d0, L_0x1e92f00; +L_0x1e93350 .part L_0x1e913f0, 4, 4; +L_0x1e934b0 .part L_0x1e93210, 0, 1; +L_0x1e93660 .part L_0x1e93210, 1, 1; +S_0x1d30880 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d306c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e91a90/d .functor OR 1, L_0x1e91b50, L_0x1e91cb0, C4<0>, C4<0>; +L_0x1e91a90 .delay 1 (30000,30000,30000) L_0x1e91a90/d; +L_0x1e91ee0/d .functor OR 1, L_0x1e91ff0, L_0x1e92150, C4<0>, C4<0>; +L_0x1e91ee0 .delay 1 (30000,30000,30000) L_0x1e91ee0/d; +L_0x1e922d0/d .functor OR 1, L_0x1e92340, L_0x1e924f0, C4<0>, C4<0>; +L_0x1e922d0 .delay 1 (30000,30000,30000) L_0x1e922d0/d; +v0x1d30ad0_0 .net *"_s0", 0 0, L_0x1e91a90; 1 drivers +v0x1d30bd0_0 .net *"_s10", 0 0, L_0x1e91ff0; 1 drivers +v0x1d30cb0_0 .net *"_s12", 0 0, L_0x1e92150; 1 drivers +v0x1d30d70_0 .net *"_s14", 0 0, L_0x1e92340; 1 drivers +v0x1d30e50_0 .net *"_s16", 0 0, L_0x1e924f0; 1 drivers +v0x1d30f80_0 .net *"_s3", 0 0, L_0x1e91b50; 1 drivers +v0x1d31060_0 .net *"_s5", 0 0, L_0x1e91cb0; 1 drivers +v0x1d31140_0 .net *"_s6", 0 0, L_0x1e91ee0; 1 drivers +v0x1d31220_0 .net "in", 3 0, L_0x1e925e0; 1 drivers +v0x1d31390_0 .net "ors", 1 0, L_0x1e91df0; 1 drivers +v0x1d31470_0 .net "out", 0 0, L_0x1e922d0; 1 drivers +L_0x1e91b50 .part L_0x1e925e0, 0, 1; +L_0x1e91cb0 .part L_0x1e925e0, 1, 1; +L_0x1e91df0 .concat8 [ 1 1 0 0], L_0x1e91a90, L_0x1e91ee0; +L_0x1e91ff0 .part L_0x1e925e0, 2, 1; +L_0x1e92150 .part L_0x1e925e0, 3, 1; +L_0x1e92340 .part L_0x1e91df0, 0, 1; +L_0x1e924f0 .part L_0x1e91df0, 1, 1; +S_0x1d31590 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d306c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e92710/d .functor OR 1, L_0x1e92780, L_0x1e928e0, C4<0>, C4<0>; +L_0x1e92710 .delay 1 (30000,30000,30000) L_0x1e92710/d; +L_0x1e92b10/d .functor OR 1, L_0x1e92c20, L_0x1e92d80, C4<0>, C4<0>; +L_0x1e92b10 .delay 1 (30000,30000,30000) L_0x1e92b10/d; +L_0x1e92f00/d .functor OR 1, L_0x1e92f70, L_0x1e93120, C4<0>, C4<0>; +L_0x1e92f00 .delay 1 (30000,30000,30000) L_0x1e92f00/d; +v0x1d31750_0 .net *"_s0", 0 0, L_0x1e92710; 1 drivers +v0x1d31850_0 .net *"_s10", 0 0, L_0x1e92c20; 1 drivers +v0x1d31930_0 .net *"_s12", 0 0, L_0x1e92d80; 1 drivers +v0x1d319f0_0 .net *"_s14", 0 0, L_0x1e92f70; 1 drivers +v0x1d31ad0_0 .net *"_s16", 0 0, L_0x1e93120; 1 drivers +v0x1d31c00_0 .net *"_s3", 0 0, L_0x1e92780; 1 drivers +v0x1d31ce0_0 .net *"_s5", 0 0, L_0x1e928e0; 1 drivers +v0x1d31dc0_0 .net *"_s6", 0 0, L_0x1e92b10; 1 drivers +v0x1d31ea0_0 .net "in", 3 0, L_0x1e93350; 1 drivers +v0x1d32010_0 .net "ors", 1 0, L_0x1e92a20; 1 drivers +v0x1d320f0_0 .net "out", 0 0, L_0x1e92f00; 1 drivers +L_0x1e92780 .part L_0x1e93350, 0, 1; +L_0x1e928e0 .part L_0x1e93350, 1, 1; +L_0x1e92a20 .concat8 [ 1 1 0 0], L_0x1e92710, L_0x1e92b10; +L_0x1e92c20 .part L_0x1e93350, 2, 1; +L_0x1e92d80 .part L_0x1e93350, 3, 1; +L_0x1e92f70 .part L_0x1e92a20, 0, 1; +L_0x1e93120 .part L_0x1e92a20, 1, 1; +S_0x1d32a00 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d26380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e8eca0/d .functor XNOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; +L_0x1e8eca0 .delay 1 (20000,20000,20000) L_0x1e8eca0/d; +L_0x1e8ef10/d .functor AND 1, L_0x1e97290, L_0x1e8db90, C4<1>, C4<1>; +L_0x1e8ef10 .delay 1 (30000,30000,30000) L_0x1e8ef10/d; +L_0x1e8ef80/d .functor AND 1, L_0x1e8eca0, L_0x1e8d920, C4<1>, C4<1>; +L_0x1e8ef80 .delay 1 (30000,30000,30000) L_0x1e8ef80/d; +L_0x1e8f0e0/d .functor OR 1, L_0x1e8ef80, L_0x1e8ef10, C4<0>, C4<0>; +L_0x1e8f0e0 .delay 1 (30000,30000,30000) L_0x1e8f0e0/d; +v0x1d32cb0_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers +v0x1d32da0_0 .net "a_", 0 0, L_0x1e83ce0; alias, 1 drivers +v0x1d32e60_0 .net "b", 0 0, L_0x1e8d880; alias, 1 drivers +v0x1d32f50_0 .net "b_", 0 0, L_0x1e8db90; alias, 1 drivers +v0x1d32ff0_0 .net "carryin", 0 0, L_0x1e8d920; alias, 1 drivers +v0x1d33130_0 .net "eq", 0 0, L_0x1e8eca0; 1 drivers +v0x1d331f0_0 .net "lt", 0 0, L_0x1e8ef10; 1 drivers +v0x1d332b0_0 .net "out", 0 0, L_0x1e8f0e0; 1 drivers +v0x1d33370_0 .net "w0", 0 0, L_0x1e8ef80; 1 drivers +S_0x1d335c0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d26380; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e8ea80/d .functor OR 1, L_0x1e8e580, L_0x1d34820, C4<0>, C4<0>; +L_0x1e8ea80 .delay 1 (30000,30000,30000) L_0x1e8ea80/d; +v0x1d343b0_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers +v0x1d34500_0 .net "b", 0 0, L_0x1e8db90; alias, 1 drivers +v0x1d345c0_0 .net "c1", 0 0, L_0x1e8e580; 1 drivers +v0x1d34660_0 .net "c2", 0 0, L_0x1d34820; 1 drivers +v0x1d34730_0 .net "carryin", 0 0, L_0x1e8d920; alias, 1 drivers +v0x1d348b0_0 .net "carryout", 0 0, L_0x1e8ea80; 1 drivers +v0x1d34950_0 .net "s1", 0 0, L_0x1e8e4c0; 1 drivers +v0x1d349f0_0 .net "sum", 0 0, L_0x1e8e6e0; 1 drivers +S_0x1d33810 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d335c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e8e4c0/d .functor XOR 1, L_0x1e97290, L_0x1e8db90, C4<0>, C4<0>; +L_0x1e8e4c0 .delay 1 (30000,30000,30000) L_0x1e8e4c0/d; +L_0x1e8e580/d .functor AND 1, L_0x1e97290, L_0x1e8db90, C4<1>, C4<1>; +L_0x1e8e580 .delay 1 (30000,30000,30000) L_0x1e8e580/d; +v0x1d33a70_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers +v0x1d33b30_0 .net "b", 0 0, L_0x1e8db90; alias, 1 drivers +v0x1d33bf0_0 .net "carryout", 0 0, L_0x1e8e580; alias, 1 drivers +v0x1d33c90_0 .net "sum", 0 0, L_0x1e8e4c0; alias, 1 drivers +S_0x1d33dc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d335c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e8e6e0/d .functor XOR 1, L_0x1e8e4c0, L_0x1e8d920, C4<0>, C4<0>; +L_0x1e8e6e0 .delay 1 (30000,30000,30000) L_0x1e8e6e0/d; +L_0x1d34820/d .functor AND 1, L_0x1e8e4c0, L_0x1e8d920, C4<1>, C4<1>; +L_0x1d34820 .delay 1 (30000,30000,30000) L_0x1d34820/d; +v0x1d34020_0 .net "a", 0 0, L_0x1e8e4c0; alias, 1 drivers +v0x1d340f0_0 .net "b", 0 0, L_0x1e8d920; alias, 1 drivers +v0x1d34190_0 .net "carryout", 0 0, L_0x1d34820; alias, 1 drivers +v0x1d34260_0 .net "sum", 0 0, L_0x1e8e6e0; alias, 1 drivers +S_0x1d35e10 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d260b0; + .timescale -9 -12; +L_0x7f72592dc0b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dc100 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e97330/d .functor OR 1, L_0x7f72592dc0b8, L_0x7f72592dc100, C4<0>, C4<0>; +L_0x1e97330 .delay 1 (30000,30000,30000) L_0x1e97330/d; +v0x1d35fe0_0 .net/2u *"_s0", 0 0, L_0x7f72592dc0b8; 1 drivers +v0x1d36080_0 .net/2u *"_s2", 0 0, L_0x7f72592dc100; 1 drivers +S_0x1d36120 .scope generate, "alu_slices[30]" "alu_slices[30]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1d362f0 .param/l "i" 0 3 37, +C4<011110>; +S_0x1d363b0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d36120; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e8dab0/d .functor NOT 1, L_0x1ea0ee0, C4<0>, C4<0>, C4<0>; +L_0x1e8dab0 .delay 1 (10000,10000,10000) L_0x1e8dab0/d; +L_0x1e977c0/d .functor NOT 1, L_0x1e02630, C4<0>, C4<0>, C4<0>; +L_0x1e977c0 .delay 1 (10000,10000,10000) L_0x1e977c0/d; +L_0x1e98810/d .functor XOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; +L_0x1e98810 .delay 1 (30000,30000,30000) L_0x1e98810/d; +L_0x7f72592dc148 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dc190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1e98ec0/d .functor OR 1, L_0x7f72592dc148, L_0x7f72592dc190, C4<0>, C4<0>; +L_0x1e98ec0 .delay 1 (30000,30000,30000) L_0x1e98ec0/d; +L_0x1e990c0/d .functor AND 1, L_0x1ea0ee0, L_0x1e02630, C4<1>, C4<1>; +L_0x1e990c0 .delay 1 (30000,30000,30000) L_0x1e990c0/d; +L_0x1e99180/d .functor NAND 1, L_0x1ea0ee0, L_0x1e02630, C4<1>, C4<1>; +L_0x1e99180 .delay 1 (20000,20000,20000) L_0x1e99180/d; +L_0x1e992e0/d .functor XOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; +L_0x1e992e0 .delay 1 (20000,20000,20000) L_0x1e992e0/d; +L_0x1e99790/d .functor OR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; +L_0x1e99790 .delay 1 (30000,30000,30000) L_0x1e99790/d; +L_0x1ea0de0/d .functor NOT 1, L_0x1e87760, C4<0>, C4<0>, C4<0>; +L_0x1ea0de0 .delay 1 (10000,10000,10000) L_0x1ea0de0/d; +v0x1d44c10_0 .net "A", 0 0, L_0x1ea0ee0; 1 drivers +v0x1d44cd0_0 .net "A_", 0 0, L_0x1e8dab0; 1 drivers +v0x1d44d90_0 .net "B", 0 0, L_0x1e02630; 1 drivers +v0x1d44e60_0 .net "B_", 0 0, L_0x1e977c0; 1 drivers +v0x1d44f00_0 .net *"_s12", 0 0, L_0x1e98ec0; 1 drivers +v0x1d44ff0_0 .net/2s *"_s14", 0 0, L_0x7f72592dc148; 1 drivers +v0x1d450b0_0 .net/2s *"_s16", 0 0, L_0x7f72592dc190; 1 drivers +v0x1d45190_0 .net *"_s18", 0 0, L_0x1e990c0; 1 drivers +v0x1d45270_0 .net *"_s20", 0 0, L_0x1e99180; 1 drivers +v0x1d453e0_0 .net *"_s22", 0 0, L_0x1e992e0; 1 drivers +v0x1d454c0_0 .net *"_s24", 0 0, L_0x1e99790; 1 drivers +o0x7f725933b228 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1d455a0_0 name=_s30 +o0x7f725933b258 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1d45680_0 name=_s32 +v0x1d45760_0 .net *"_s8", 0 0, L_0x1e98810; 1 drivers +v0x1d45840_0 .net "carryin", 0 0, L_0x1e973f0; 1 drivers +v0x1d458e0_0 .net "carryout", 0 0, L_0x1ea0a80; 1 drivers +v0x1d45980_0 .net "carryouts", 7 0, L_0x1ec1f50; 1 drivers +v0x1d45b30_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d45bd0_0 .net "result", 0 0, L_0x1e87760; 1 drivers +v0x1d45cc0_0 .net "results", 7 0, L_0x1e99560; 1 drivers +v0x1d45dd0_0 .net "zero", 0 0, L_0x1ea0de0; 1 drivers +LS_0x1e99560_0_0 .concat8 [ 1 1 1 1], L_0x1e97ce0, L_0x1e98310, L_0x1e98810, L_0x1e98ec0; +LS_0x1e99560_0_4 .concat8 [ 1 1 1 1], L_0x1e990c0, L_0x1e99180, L_0x1e992e0, L_0x1e99790; +L_0x1e99560 .concat8 [ 4 4 0 0], LS_0x1e99560_0_0, LS_0x1e99560_0_4; +LS_0x1ec1f50_0_0 .concat [ 1 1 1 1], L_0x1e97f90, L_0x1e986b0, o0x7f725933b228, L_0x1e98d10; +LS_0x1ec1f50_0_4 .concat [ 4 0 0 0], o0x7f725933b258; +L_0x1ec1f50 .concat [ 4 4 0 0], LS_0x1ec1f50_0_0, LS_0x1ec1f50_0_4; +S_0x1d36670 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d363b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e97f90/d .functor OR 1, L_0x1e97a70, L_0x1e97e30, C4<0>, C4<0>; +L_0x1e97f90 .delay 1 (30000,30000,30000) L_0x1e97f90/d; +v0x1d37590_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers +v0x1d37650_0 .net "b", 0 0, L_0x1e02630; alias, 1 drivers +v0x1d37720_0 .net "c1", 0 0, L_0x1e97a70; 1 drivers +v0x1d37820_0 .net "c2", 0 0, L_0x1e97e30; 1 drivers +v0x1d378f0_0 .net "carryin", 0 0, L_0x1e973f0; alias, 1 drivers +v0x1d379e0_0 .net "carryout", 0 0, L_0x1e97f90; 1 drivers +v0x1d37a80_0 .net "s1", 0 0, L_0x1e979b0; 1 drivers +v0x1d37b70_0 .net "sum", 0 0, L_0x1e97ce0; 1 drivers +S_0x1d36910 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d36670; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e979b0/d .functor XOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; +L_0x1e979b0 .delay 1 (30000,30000,30000) L_0x1e979b0/d; +L_0x1e97a70/d .functor AND 1, L_0x1ea0ee0, L_0x1e02630, C4<1>, C4<1>; +L_0x1e97a70 .delay 1 (30000,30000,30000) L_0x1e97a70/d; +v0x1d36ba0_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers +v0x1d36c80_0 .net "b", 0 0, L_0x1e02630; alias, 1 drivers +v0x1d36d40_0 .net "carryout", 0 0, L_0x1e97a70; alias, 1 drivers +v0x1d36e10_0 .net "sum", 0 0, L_0x1e979b0; alias, 1 drivers +S_0x1d36f80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d36670; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e97ce0/d .functor XOR 1, L_0x1e979b0, L_0x1e973f0, C4<0>, C4<0>; +L_0x1e97ce0 .delay 1 (30000,30000,30000) L_0x1e97ce0/d; +L_0x1e97e30/d .functor AND 1, L_0x1e979b0, L_0x1e973f0, C4<1>, C4<1>; +L_0x1e97e30 .delay 1 (30000,30000,30000) L_0x1e97e30/d; +v0x1d371e0_0 .net "a", 0 0, L_0x1e979b0; alias, 1 drivers +v0x1d372b0_0 .net "b", 0 0, L_0x1e973f0; alias, 1 drivers +v0x1d37350_0 .net "carryout", 0 0, L_0x1e97e30; alias, 1 drivers +v0x1d37420_0 .net "sum", 0 0, L_0x1e97ce0; alias, 1 drivers +S_0x1d37c40 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d363b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d3d030_0 .net "ands", 7 0, L_0x1e9ea80; 1 drivers +v0x1d3d140_0 .net "in", 7 0, L_0x1ec1f50; alias, 1 drivers +v0x1d3d200_0 .net "out", 0 0, L_0x1ea0a80; alias, 1 drivers +v0x1d3d2d0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d37e60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d37c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d3a590_0 .net "A", 7 0, L_0x1ec1f50; alias, 1 drivers +v0x1d3a690_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d3a750_0 .net *"_s0", 0 0, L_0x1e9d2c0; 1 drivers +v0x1d3a810_0 .net *"_s12", 0 0, L_0x1e9dc30; 1 drivers +v0x1d3a8f0_0 .net *"_s16", 0 0, L_0x1e9df90; 1 drivers +v0x1d3aa20_0 .net *"_s20", 0 0, L_0x1e9e300; 1 drivers +v0x1d3ab00_0 .net *"_s24", 0 0, L_0x1e9e6f0; 1 drivers +v0x1d3abe0_0 .net *"_s28", 0 0, L_0x1e9e680; 1 drivers +v0x1d3acc0_0 .net *"_s4", 0 0, L_0x1e9d5d0; 1 drivers +v0x1d3ae30_0 .net *"_s8", 0 0, L_0x1e9d920; 1 drivers +v0x1d3af10_0 .net "out", 7 0, L_0x1e9ea80; alias, 1 drivers +L_0x1e9d380 .part L_0x1ec1f50, 0, 1; +L_0x1e9d4e0 .part v0x1d6daa0_0, 0, 1; +L_0x1e9d690 .part L_0x1ec1f50, 1, 1; +L_0x1e9d880 .part v0x1d6daa0_0, 1, 1; +L_0x1e9d9e0 .part L_0x1ec1f50, 2, 1; +L_0x1e9db40 .part v0x1d6daa0_0, 2, 1; +L_0x1e9dcf0 .part L_0x1ec1f50, 3, 1; +L_0x1e9de50 .part v0x1d6daa0_0, 3, 1; +L_0x1e9e050 .part L_0x1ec1f50, 4, 1; +L_0x1e9e1b0 .part v0x1d6daa0_0, 4, 1; +L_0x1e9e370 .part L_0x1ec1f50, 5, 1; +L_0x1e9e5e0 .part v0x1d6daa0_0, 5, 1; +L_0x1e9e7b0 .part L_0x1ec1f50, 6, 1; +L_0x1e9e910 .part v0x1d6daa0_0, 6, 1; +LS_0x1e9ea80_0_0 .concat8 [ 1 1 1 1], L_0x1e9d2c0, L_0x1e9d5d0, L_0x1e9d920, L_0x1e9dc30; +LS_0x1e9ea80_0_4 .concat8 [ 1 1 1 1], L_0x1e9df90, L_0x1e9e300, L_0x1e9e6f0, L_0x1e9e680; +L_0x1e9ea80 .concat8 [ 4 4 0 0], LS_0x1e9ea80_0_0, LS_0x1e9ea80_0_4; +L_0x1e9ee40 .part L_0x1ec1f50, 7, 1; +L_0x1e9f030 .part v0x1d6daa0_0, 7, 1; +S_0x1d380c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d382d0 .param/l "i" 0 4 54, +C4<00>; +L_0x1e9d2c0/d .functor AND 1, L_0x1e9d380, L_0x1e9d4e0, C4<1>, C4<1>; +L_0x1e9d2c0 .delay 1 (30000,30000,30000) L_0x1e9d2c0/d; +v0x1d383b0_0 .net *"_s0", 0 0, L_0x1e9d380; 1 drivers +v0x1d38490_0 .net *"_s1", 0 0, L_0x1e9d4e0; 1 drivers +S_0x1d38570 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d38780 .param/l "i" 0 4 54, +C4<01>; +L_0x1e9d5d0/d .functor AND 1, L_0x1e9d690, L_0x1e9d880, C4<1>, C4<1>; +L_0x1e9d5d0 .delay 1 (30000,30000,30000) L_0x1e9d5d0/d; +v0x1d38840_0 .net *"_s0", 0 0, L_0x1e9d690; 1 drivers +v0x1d38920_0 .net *"_s1", 0 0, L_0x1e9d880; 1 drivers +S_0x1d38a00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d38c10 .param/l "i" 0 4 54, +C4<010>; +L_0x1e9d920/d .functor AND 1, L_0x1e9d9e0, L_0x1e9db40, C4<1>, C4<1>; +L_0x1e9d920 .delay 1 (30000,30000,30000) L_0x1e9d920/d; +v0x1d38cb0_0 .net *"_s0", 0 0, L_0x1e9d9e0; 1 drivers +v0x1d38d90_0 .net *"_s1", 0 0, L_0x1e9db40; 1 drivers +S_0x1d38e70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d39080 .param/l "i" 0 4 54, +C4<011>; +L_0x1e9dc30/d .functor AND 1, L_0x1e9dcf0, L_0x1e9de50, C4<1>, C4<1>; +L_0x1e9dc30 .delay 1 (30000,30000,30000) L_0x1e9dc30/d; +v0x1d39140_0 .net *"_s0", 0 0, L_0x1e9dcf0; 1 drivers +v0x1d39220_0 .net *"_s1", 0 0, L_0x1e9de50; 1 drivers +S_0x1d39300 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d39560 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e9df90/d .functor AND 1, L_0x1e9e050, L_0x1e9e1b0, C4<1>, C4<1>; +L_0x1e9df90 .delay 1 (30000,30000,30000) L_0x1e9df90/d; +v0x1d39620_0 .net *"_s0", 0 0, L_0x1e9e050; 1 drivers +v0x1d39700_0 .net *"_s1", 0 0, L_0x1e9e1b0; 1 drivers +S_0x1d397e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d399f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e9e300/d .functor AND 1, L_0x1e9e370, L_0x1e9e5e0, C4<1>, C4<1>; +L_0x1e9e300 .delay 1 (30000,30000,30000) L_0x1e9e300/d; +v0x1d39ab0_0 .net *"_s0", 0 0, L_0x1e9e370; 1 drivers +v0x1d39b90_0 .net *"_s1", 0 0, L_0x1e9e5e0; 1 drivers +S_0x1d39c70 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d39e80 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e9e6f0/d .functor AND 1, L_0x1e9e7b0, L_0x1e9e910, C4<1>, C4<1>; +L_0x1e9e6f0 .delay 1 (30000,30000,30000) L_0x1e9e6f0/d; +v0x1d39f40_0 .net *"_s0", 0 0, L_0x1e9e7b0; 1 drivers +v0x1d3a020_0 .net *"_s1", 0 0, L_0x1e9e910; 1 drivers +S_0x1d3a100 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d37e60; + .timescale -9 -12; +P_0x1d3a310 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e9e680/d .functor AND 1, L_0x1e9ee40, L_0x1e9f030, C4<1>, C4<1>; +L_0x1e9e680 .delay 1 (30000,30000,30000) L_0x1e9e680/d; +v0x1d3a3d0_0 .net *"_s0", 0 0, L_0x1e9ee40; 1 drivers +v0x1d3a4b0_0 .net *"_s1", 0 0, L_0x1e9f030; 1 drivers +S_0x1d3b070 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d37c40; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1ea0a80/d .functor OR 1, L_0x1ea0b40, L_0x1ea0cf0, C4<0>, C4<0>; +L_0x1ea0a80 .delay 1 (30000,30000,30000) L_0x1ea0a80/d; +v0x1d3cbc0_0 .net *"_s10", 0 0, L_0x1ea0b40; 1 drivers +v0x1d3cca0_0 .net *"_s12", 0 0, L_0x1ea0cf0; 1 drivers +v0x1d3cd80_0 .net "in", 7 0, L_0x1e9ea80; alias, 1 drivers +v0x1d3ce50_0 .net "ors", 1 0, L_0x1ea08a0; 1 drivers +v0x1d3cf10_0 .net "out", 0 0, L_0x1ea0a80; alias, 1 drivers +L_0x1e9fc70 .part L_0x1e9ea80, 0, 4; +L_0x1ea08a0 .concat8 [ 1 1 0 0], L_0x1e9f960, L_0x1ea0590; +L_0x1ea09e0 .part L_0x1e9ea80, 4, 4; +L_0x1ea0b40 .part L_0x1ea08a0, 0, 1; +L_0x1ea0cf0 .part L_0x1ea08a0, 1, 1; +S_0x1d3b230 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d3b070; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e9f120/d .functor OR 1, L_0x1e9f1e0, L_0x1e9f340, C4<0>, C4<0>; +L_0x1e9f120 .delay 1 (30000,30000,30000) L_0x1e9f120/d; +L_0x1e9f570/d .functor OR 1, L_0x1e9f680, L_0x1e9f7e0, C4<0>, C4<0>; +L_0x1e9f570 .delay 1 (30000,30000,30000) L_0x1e9f570/d; +L_0x1e9f960/d .functor OR 1, L_0x1e9f9d0, L_0x1e9fb80, C4<0>, C4<0>; +L_0x1e9f960 .delay 1 (30000,30000,30000) L_0x1e9f960/d; +v0x1d3b480_0 .net *"_s0", 0 0, L_0x1e9f120; 1 drivers +v0x1d3b580_0 .net *"_s10", 0 0, L_0x1e9f680; 1 drivers +v0x1d3b660_0 .net *"_s12", 0 0, L_0x1e9f7e0; 1 drivers +v0x1d3b720_0 .net *"_s14", 0 0, L_0x1e9f9d0; 1 drivers +v0x1d3b800_0 .net *"_s16", 0 0, L_0x1e9fb80; 1 drivers +v0x1d3b930_0 .net *"_s3", 0 0, L_0x1e9f1e0; 1 drivers +v0x1d3ba10_0 .net *"_s5", 0 0, L_0x1e9f340; 1 drivers +v0x1d3baf0_0 .net *"_s6", 0 0, L_0x1e9f570; 1 drivers +v0x1d3bbd0_0 .net "in", 3 0, L_0x1e9fc70; 1 drivers +v0x1d3bd40_0 .net "ors", 1 0, L_0x1e9f480; 1 drivers +v0x1d3be20_0 .net "out", 0 0, L_0x1e9f960; 1 drivers +L_0x1e9f1e0 .part L_0x1e9fc70, 0, 1; +L_0x1e9f340 .part L_0x1e9fc70, 1, 1; +L_0x1e9f480 .concat8 [ 1 1 0 0], L_0x1e9f120, L_0x1e9f570; +L_0x1e9f680 .part L_0x1e9fc70, 2, 1; +L_0x1e9f7e0 .part L_0x1e9fc70, 3, 1; +L_0x1e9f9d0 .part L_0x1e9f480, 0, 1; +L_0x1e9fb80 .part L_0x1e9f480, 1, 1; +S_0x1d3bf40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d3b070; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e9fda0/d .functor OR 1, L_0x1e9fe10, L_0x1e9ff70, C4<0>, C4<0>; +L_0x1e9fda0 .delay 1 (30000,30000,30000) L_0x1e9fda0/d; +L_0x1ea01a0/d .functor OR 1, L_0x1ea02b0, L_0x1ea0410, C4<0>, C4<0>; +L_0x1ea01a0 .delay 1 (30000,30000,30000) L_0x1ea01a0/d; +L_0x1ea0590/d .functor OR 1, L_0x1ea0600, L_0x1ea07b0, C4<0>, C4<0>; +L_0x1ea0590 .delay 1 (30000,30000,30000) L_0x1ea0590/d; +v0x1d3c100_0 .net *"_s0", 0 0, L_0x1e9fda0; 1 drivers +v0x1d3c200_0 .net *"_s10", 0 0, L_0x1ea02b0; 1 drivers +v0x1d3c2e0_0 .net *"_s12", 0 0, L_0x1ea0410; 1 drivers +v0x1d3c3a0_0 .net *"_s14", 0 0, L_0x1ea0600; 1 drivers +v0x1d3c480_0 .net *"_s16", 0 0, L_0x1ea07b0; 1 drivers +v0x1d3c5b0_0 .net *"_s3", 0 0, L_0x1e9fe10; 1 drivers +v0x1d3c690_0 .net *"_s5", 0 0, L_0x1e9ff70; 1 drivers +v0x1d3c770_0 .net *"_s6", 0 0, L_0x1ea01a0; 1 drivers +v0x1d3c850_0 .net "in", 3 0, L_0x1ea09e0; 1 drivers +v0x1d3c9c0_0 .net "ors", 1 0, L_0x1ea00b0; 1 drivers +v0x1d3caa0_0 .net "out", 0 0, L_0x1ea0590; 1 drivers +L_0x1e9fe10 .part L_0x1ea09e0, 0, 1; +L_0x1e9ff70 .part L_0x1ea09e0, 1, 1; +L_0x1ea00b0 .concat8 [ 1 1 0 0], L_0x1e9fda0, L_0x1ea01a0; +L_0x1ea02b0 .part L_0x1ea09e0, 2, 1; +L_0x1ea0410 .part L_0x1ea09e0, 3, 1; +L_0x1ea0600 .part L_0x1ea00b0, 0, 1; +L_0x1ea07b0 .part L_0x1ea00b0, 1, 1; +S_0x1d3d3b0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d363b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d427e0_0 .net "ands", 7 0, L_0x1e9b020; 1 drivers +v0x1d428f0_0 .net "in", 7 0, L_0x1e99560; alias, 1 drivers +v0x1d429b0_0 .net "out", 0 0, L_0x1e87760; alias, 1 drivers +v0x1d42a80_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d3d600 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d3d3b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d3fd40_0 .net "A", 7 0, L_0x1e99560; alias, 1 drivers +v0x1d3fe40_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d3ff00_0 .net *"_s0", 0 0, L_0x1e998f0; 1 drivers +v0x1d3ffc0_0 .net *"_s12", 0 0, L_0x1e9a2b0; 1 drivers +v0x1d400a0_0 .net *"_s16", 0 0, L_0x1e9a610; 1 drivers +v0x1d401d0_0 .net *"_s20", 0 0, L_0x1e9a9e0; 1 drivers +v0x1d402b0_0 .net *"_s24", 0 0, L_0x1e9ad10; 1 drivers +v0x1d40390_0 .net *"_s28", 0 0, L_0x1e9aca0; 1 drivers +v0x1d40470_0 .net *"_s4", 0 0, L_0x1e99c90; 1 drivers +v0x1d405e0_0 .net *"_s8", 0 0, L_0x1e99fa0; 1 drivers +v0x1d406c0_0 .net "out", 7 0, L_0x1e9b020; alias, 1 drivers +L_0x1e99a00 .part L_0x1e99560, 0, 1; +L_0x1e99bf0 .part v0x1d6daa0_0, 0, 1; +L_0x1e99d50 .part L_0x1e99560, 1, 1; +L_0x1e99eb0 .part v0x1d6daa0_0, 1, 1; +L_0x1e9a060 .part L_0x1e99560, 2, 1; +L_0x1e9a1c0 .part v0x1d6daa0_0, 2, 1; +L_0x1e9a370 .part L_0x1e99560, 3, 1; +L_0x1e9a4d0 .part v0x1d6daa0_0, 3, 1; +L_0x1e9a6d0 .part L_0x1e99560, 4, 1; +L_0x1e9a940 .part v0x1d6daa0_0, 4, 1; +L_0x1e9aa50 .part L_0x1e99560, 5, 1; +L_0x1e9abb0 .part v0x1d6daa0_0, 5, 1; +L_0x1e9add0 .part L_0x1e99560, 6, 1; +L_0x1e9af30 .part v0x1d6daa0_0, 6, 1; +LS_0x1e9b020_0_0 .concat8 [ 1 1 1 1], L_0x1e998f0, L_0x1e99c90, L_0x1e99fa0, L_0x1e9a2b0; +LS_0x1e9b020_0_4 .concat8 [ 1 1 1 1], L_0x1e9a610, L_0x1e9a9e0, L_0x1e9ad10, L_0x1e9aca0; +L_0x1e9b020 .concat8 [ 4 4 0 0], LS_0x1e9b020_0_0, LS_0x1e9b020_0_4; +L_0x1e9b3e0 .part L_0x1e99560, 7, 1; +L_0x1e9b5d0 .part v0x1d6daa0_0, 7, 1; +S_0x1d3d840 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3da50 .param/l "i" 0 4 54, +C4<00>; +L_0x1e998f0/d .functor AND 1, L_0x1e99a00, L_0x1e99bf0, C4<1>, C4<1>; +L_0x1e998f0 .delay 1 (30000,30000,30000) L_0x1e998f0/d; +v0x1d3db30_0 .net *"_s0", 0 0, L_0x1e99a00; 1 drivers +v0x1d3dc10_0 .net *"_s1", 0 0, L_0x1e99bf0; 1 drivers +S_0x1d3dcf0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3df00 .param/l "i" 0 4 54, +C4<01>; +L_0x1e99c90/d .functor AND 1, L_0x1e99d50, L_0x1e99eb0, C4<1>, C4<1>; +L_0x1e99c90 .delay 1 (30000,30000,30000) L_0x1e99c90/d; +v0x1d3dfc0_0 .net *"_s0", 0 0, L_0x1e99d50; 1 drivers +v0x1d3e0a0_0 .net *"_s1", 0 0, L_0x1e99eb0; 1 drivers +S_0x1d3e180 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3e3c0 .param/l "i" 0 4 54, +C4<010>; +L_0x1e99fa0/d .functor AND 1, L_0x1e9a060, L_0x1e9a1c0, C4<1>, C4<1>; +L_0x1e99fa0 .delay 1 (30000,30000,30000) L_0x1e99fa0/d; +v0x1d3e460_0 .net *"_s0", 0 0, L_0x1e9a060; 1 drivers +v0x1d3e540_0 .net *"_s1", 0 0, L_0x1e9a1c0; 1 drivers +S_0x1d3e620 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3e830 .param/l "i" 0 4 54, +C4<011>; +L_0x1e9a2b0/d .functor AND 1, L_0x1e9a370, L_0x1e9a4d0, C4<1>, C4<1>; +L_0x1e9a2b0 .delay 1 (30000,30000,30000) L_0x1e9a2b0/d; +v0x1d3e8f0_0 .net *"_s0", 0 0, L_0x1e9a370; 1 drivers +v0x1d3e9d0_0 .net *"_s1", 0 0, L_0x1e9a4d0; 1 drivers +S_0x1d3eab0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3ed10 .param/l "i" 0 4 54, +C4<0100>; +L_0x1e9a610/d .functor AND 1, L_0x1e9a6d0, L_0x1e9a940, C4<1>, C4<1>; +L_0x1e9a610 .delay 1 (30000,30000,30000) L_0x1e9a610/d; +v0x1d3edd0_0 .net *"_s0", 0 0, L_0x1e9a6d0; 1 drivers +v0x1d3eeb0_0 .net *"_s1", 0 0, L_0x1e9a940; 1 drivers +S_0x1d3ef90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3f1a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1e9a9e0/d .functor AND 1, L_0x1e9aa50, L_0x1e9abb0, C4<1>, C4<1>; +L_0x1e9a9e0 .delay 1 (30000,30000,30000) L_0x1e9a9e0/d; +v0x1d3f260_0 .net *"_s0", 0 0, L_0x1e9aa50; 1 drivers +v0x1d3f340_0 .net *"_s1", 0 0, L_0x1e9abb0; 1 drivers +S_0x1d3f420 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3f630 .param/l "i" 0 4 54, +C4<0110>; +L_0x1e9ad10/d .functor AND 1, L_0x1e9add0, L_0x1e9af30, C4<1>, C4<1>; +L_0x1e9ad10 .delay 1 (30000,30000,30000) L_0x1e9ad10/d; +v0x1d3f6f0_0 .net *"_s0", 0 0, L_0x1e9add0; 1 drivers +v0x1d3f7d0_0 .net *"_s1", 0 0, L_0x1e9af30; 1 drivers +S_0x1d3f8b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d3d600; + .timescale -9 -12; +P_0x1d3fac0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1e9aca0/d .functor AND 1, L_0x1e9b3e0, L_0x1e9b5d0, C4<1>, C4<1>; +L_0x1e9aca0 .delay 1 (30000,30000,30000) L_0x1e9aca0/d; +v0x1d3fb80_0 .net *"_s0", 0 0, L_0x1e9b3e0; 1 drivers +v0x1d3fc60_0 .net *"_s1", 0 0, L_0x1e9b5d0; 1 drivers +S_0x1d40820 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d3d3b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1e87760/d .functor OR 1, L_0x1e9d020, L_0x1e9d1d0, C4<0>, C4<0>; +L_0x1e87760 .delay 1 (30000,30000,30000) L_0x1e87760/d; +v0x1d42370_0 .net *"_s10", 0 0, L_0x1e9d020; 1 drivers +v0x1d42450_0 .net *"_s12", 0 0, L_0x1e9d1d0; 1 drivers +v0x1d42530_0 .net "in", 7 0, L_0x1e9b020; alias, 1 drivers +v0x1d42600_0 .net "ors", 1 0, L_0x1e9ce40; 1 drivers +v0x1d426c0_0 .net "out", 0 0, L_0x1e87760; alias, 1 drivers +L_0x1e9c210 .part L_0x1e9b020, 0, 4; +L_0x1e9ce40 .concat8 [ 1 1 0 0], L_0x1e9bf00, L_0x1e9cb30; +L_0x1e9cf80 .part L_0x1e9b020, 4, 4; +L_0x1e9d020 .part L_0x1e9ce40, 0, 1; +L_0x1e9d1d0 .part L_0x1e9ce40, 1, 1; +S_0x1d409e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d40820; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e9b6c0/d .functor OR 1, L_0x1e9b780, L_0x1e9b8e0, C4<0>, C4<0>; +L_0x1e9b6c0 .delay 1 (30000,30000,30000) L_0x1e9b6c0/d; +L_0x1e9bb10/d .functor OR 1, L_0x1e9bc20, L_0x1e9bd80, C4<0>, C4<0>; +L_0x1e9bb10 .delay 1 (30000,30000,30000) L_0x1e9bb10/d; +L_0x1e9bf00/d .functor OR 1, L_0x1e9bf70, L_0x1e9c120, C4<0>, C4<0>; +L_0x1e9bf00 .delay 1 (30000,30000,30000) L_0x1e9bf00/d; +v0x1d40c30_0 .net *"_s0", 0 0, L_0x1e9b6c0; 1 drivers +v0x1d40d30_0 .net *"_s10", 0 0, L_0x1e9bc20; 1 drivers +v0x1d40e10_0 .net *"_s12", 0 0, L_0x1e9bd80; 1 drivers +v0x1d40ed0_0 .net *"_s14", 0 0, L_0x1e9bf70; 1 drivers +v0x1d40fb0_0 .net *"_s16", 0 0, L_0x1e9c120; 1 drivers +v0x1d410e0_0 .net *"_s3", 0 0, L_0x1e9b780; 1 drivers +v0x1d411c0_0 .net *"_s5", 0 0, L_0x1e9b8e0; 1 drivers +v0x1d412a0_0 .net *"_s6", 0 0, L_0x1e9bb10; 1 drivers +v0x1d41380_0 .net "in", 3 0, L_0x1e9c210; 1 drivers +v0x1d414f0_0 .net "ors", 1 0, L_0x1e9ba20; 1 drivers +v0x1d415d0_0 .net "out", 0 0, L_0x1e9bf00; 1 drivers +L_0x1e9b780 .part L_0x1e9c210, 0, 1; +L_0x1e9b8e0 .part L_0x1e9c210, 1, 1; +L_0x1e9ba20 .concat8 [ 1 1 0 0], L_0x1e9b6c0, L_0x1e9bb10; +L_0x1e9bc20 .part L_0x1e9c210, 2, 1; +L_0x1e9bd80 .part L_0x1e9c210, 3, 1; +L_0x1e9bf70 .part L_0x1e9ba20, 0, 1; +L_0x1e9c120 .part L_0x1e9ba20, 1, 1; +S_0x1d416f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d40820; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1e9c340/d .functor OR 1, L_0x1e9c3b0, L_0x1e9c510, C4<0>, C4<0>; +L_0x1e9c340 .delay 1 (30000,30000,30000) L_0x1e9c340/d; +L_0x1e9c740/d .functor OR 1, L_0x1e9c850, L_0x1e9c9b0, C4<0>, C4<0>; +L_0x1e9c740 .delay 1 (30000,30000,30000) L_0x1e9c740/d; +L_0x1e9cb30/d .functor OR 1, L_0x1e9cba0, L_0x1e9cd50, C4<0>, C4<0>; +L_0x1e9cb30 .delay 1 (30000,30000,30000) L_0x1e9cb30/d; +v0x1d418b0_0 .net *"_s0", 0 0, L_0x1e9c340; 1 drivers +v0x1d419b0_0 .net *"_s10", 0 0, L_0x1e9c850; 1 drivers +v0x1d41a90_0 .net *"_s12", 0 0, L_0x1e9c9b0; 1 drivers +v0x1d41b50_0 .net *"_s14", 0 0, L_0x1e9cba0; 1 drivers +v0x1d41c30_0 .net *"_s16", 0 0, L_0x1e9cd50; 1 drivers +v0x1d41d60_0 .net *"_s3", 0 0, L_0x1e9c3b0; 1 drivers +v0x1d41e40_0 .net *"_s5", 0 0, L_0x1e9c510; 1 drivers +v0x1d41f20_0 .net *"_s6", 0 0, L_0x1e9c740; 1 drivers +v0x1d42000_0 .net "in", 3 0, L_0x1e9cf80; 1 drivers +v0x1d42170_0 .net "ors", 1 0, L_0x1e9c650; 1 drivers +v0x1d42250_0 .net "out", 0 0, L_0x1e9cb30; 1 drivers +L_0x1e9c3b0 .part L_0x1e9cf80, 0, 1; +L_0x1e9c510 .part L_0x1e9cf80, 1, 1; +L_0x1e9c650 .concat8 [ 1 1 0 0], L_0x1e9c340, L_0x1e9c740; +L_0x1e9c850 .part L_0x1e9cf80, 2, 1; +L_0x1e9c9b0 .part L_0x1e9cf80, 3, 1; +L_0x1e9cba0 .part L_0x1e9c650, 0, 1; +L_0x1e9cd50 .part L_0x1e9c650, 1, 1; +S_0x1d42b60 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d363b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1e988d0/d .functor XNOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; +L_0x1e988d0 .delay 1 (20000,20000,20000) L_0x1e988d0/d; +L_0x1e98b40/d .functor AND 1, L_0x1ea0ee0, L_0x1e977c0, C4<1>, C4<1>; +L_0x1e98b40 .delay 1 (30000,30000,30000) L_0x1e98b40/d; +L_0x1e98bb0/d .functor AND 1, L_0x1e988d0, L_0x1e973f0, C4<1>, C4<1>; +L_0x1e98bb0 .delay 1 (30000,30000,30000) L_0x1e98bb0/d; +L_0x1e98d10/d .functor OR 1, L_0x1e98bb0, L_0x1e98b40, C4<0>, C4<0>; +L_0x1e98d10 .delay 1 (30000,30000,30000) L_0x1e98d10/d; +v0x1d42e10_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers +v0x1d42f00_0 .net "a_", 0 0, L_0x1e8dab0; alias, 1 drivers +v0x1d42fc0_0 .net "b", 0 0, L_0x1e02630; alias, 1 drivers +v0x1d430b0_0 .net "b_", 0 0, L_0x1e977c0; alias, 1 drivers +v0x1d43150_0 .net "carryin", 0 0, L_0x1e973f0; alias, 1 drivers +v0x1d43290_0 .net "eq", 0 0, L_0x1e988d0; 1 drivers +v0x1d43350_0 .net "lt", 0 0, L_0x1e98b40; 1 drivers +v0x1d43410_0 .net "out", 0 0, L_0x1e98d10; 1 drivers +v0x1d434d0_0 .net "w0", 0 0, L_0x1e98bb0; 1 drivers +S_0x1d43720 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d363b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1e986b0/d .functor OR 1, L_0x1e981b0, L_0x1d44980, C4<0>, C4<0>; +L_0x1e986b0 .delay 1 (30000,30000,30000) L_0x1e986b0/d; +v0x1d44510_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers +v0x1d44660_0 .net "b", 0 0, L_0x1e977c0; alias, 1 drivers +v0x1d44720_0 .net "c1", 0 0, L_0x1e981b0; 1 drivers +v0x1d447c0_0 .net "c2", 0 0, L_0x1d44980; 1 drivers +v0x1d44890_0 .net "carryin", 0 0, L_0x1e973f0; alias, 1 drivers +v0x1d44a10_0 .net "carryout", 0 0, L_0x1e986b0; 1 drivers +v0x1d44ab0_0 .net "s1", 0 0, L_0x1e980f0; 1 drivers +v0x1d44b50_0 .net "sum", 0 0, L_0x1e98310; 1 drivers +S_0x1d43970 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d43720; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e980f0/d .functor XOR 1, L_0x1ea0ee0, L_0x1e977c0, C4<0>, C4<0>; +L_0x1e980f0 .delay 1 (30000,30000,30000) L_0x1e980f0/d; +L_0x1e981b0/d .functor AND 1, L_0x1ea0ee0, L_0x1e977c0, C4<1>, C4<1>; +L_0x1e981b0 .delay 1 (30000,30000,30000) L_0x1e981b0/d; +v0x1d43bd0_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers +v0x1d43c90_0 .net "b", 0 0, L_0x1e977c0; alias, 1 drivers +v0x1d43d50_0 .net "carryout", 0 0, L_0x1e981b0; alias, 1 drivers +v0x1d43df0_0 .net "sum", 0 0, L_0x1e980f0; alias, 1 drivers +S_0x1d43f20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d43720; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1e98310/d .functor XOR 1, L_0x1e980f0, L_0x1e973f0, C4<0>, C4<0>; +L_0x1e98310 .delay 1 (30000,30000,30000) L_0x1e98310/d; +L_0x1d44980/d .functor AND 1, L_0x1e980f0, L_0x1e973f0, C4<1>, C4<1>; +L_0x1d44980 .delay 1 (30000,30000,30000) L_0x1d44980/d; +v0x1d44180_0 .net "a", 0 0, L_0x1e980f0; alias, 1 drivers +v0x1d44250_0 .net "b", 0 0, L_0x1e973f0; alias, 1 drivers +v0x1d442f0_0 .net "carryout", 0 0, L_0x1d44980; alias, 1 drivers +v0x1d443c0_0 .net "sum", 0 0, L_0x1e98310; alias, 1 drivers +S_0x1d45f70 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d36120; + .timescale -9 -12; +L_0x7f72592dc1d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dc220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1ea0f80/d .functor OR 1, L_0x7f72592dc1d8, L_0x7f72592dc220, C4<0>, C4<0>; +L_0x1ea0f80 .delay 1 (30000,30000,30000) L_0x1ea0f80/d; +v0x1d46160_0 .net/2u *"_s0", 0 0, L_0x7f72592dc1d8; 1 drivers +v0x1d46240_0 .net/2u *"_s2", 0 0, L_0x7f72592dc220; 1 drivers +S_0x1d46320 .scope generate, "alu_slices[31]" "alu_slices[31]" 3 37, 3 37 0, S_0x1a570b0; + .timescale -9 -12; +P_0x1d46530 .param/l "i" 0 3 37, +C4<011111>; +S_0x1d465f0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d46320; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "result" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /OUTPUT 1 "zero" + .port_info 3 /INPUT 1 "A" + .port_info 4 /INPUT 1 "B" + .port_info 5 /INPUT 1 "carryin" + .port_info 6 /INPUT 8 "command" +L_0x1e029c0/d .functor NOT 1, L_0x1eabda0, C4<0>, C4<0>, C4<0>; +L_0x1e029c0 .delay 1 (10000,10000,10000) L_0x1e029c0/d; +L_0x1e97580/d .functor NOT 1, L_0x1eab190, C4<0>, C4<0>, C4<0>; +L_0x1e97580 .delay 1 (10000,10000,10000) L_0x1e97580/d; +L_0x1ea2790/d .functor XOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; +L_0x1ea2790 .delay 1 (30000,30000,30000) L_0x1ea2790/d; +L_0x7f72592dc268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dc2b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1ea2e40/d .functor OR 1, L_0x7f72592dc268, L_0x7f72592dc2b0, C4<0>, C4<0>; +L_0x1ea2e40 .delay 1 (30000,30000,30000) L_0x1ea2e40/d; +L_0x1ea3040/d .functor AND 1, L_0x1eabda0, L_0x1eab190, C4<1>, C4<1>; +L_0x1ea3040 .delay 1 (30000,30000,30000) L_0x1ea3040/d; +L_0x1ea3100/d .functor NAND 1, L_0x1eabda0, L_0x1eab190, C4<1>, C4<1>; +L_0x1ea3100 .delay 1 (20000,20000,20000) L_0x1ea3100/d; +L_0x1ea3260/d .functor XOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; +L_0x1ea3260 .delay 1 (20000,20000,20000) L_0x1ea3260/d; +L_0x1ea3710/d .functor OR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; +L_0x1ea3710 .delay 1 (30000,30000,30000) L_0x1ea3710/d; +L_0x1eaae20/d .functor NOT 1, L_0x1ea7080, C4<0>, C4<0>, C4<0>; +L_0x1eaae20 .delay 1 (10000,10000,10000) L_0x1eaae20/d; +v0x1d54d20_0 .net "A", 0 0, L_0x1eabda0; 1 drivers +v0x1d54de0_0 .net "A_", 0 0, L_0x1e029c0; 1 drivers +v0x1d54ea0_0 .net "B", 0 0, L_0x1eab190; 1 drivers +v0x1d54f70_0 .net "B_", 0 0, L_0x1e97580; 1 drivers +v0x1d55010_0 .net *"_s12", 0 0, L_0x1ea2e40; 1 drivers +v0x1d55100_0 .net/2s *"_s14", 0 0, L_0x7f72592dc268; 1 drivers +v0x1d551c0_0 .net/2s *"_s16", 0 0, L_0x7f72592dc2b0; 1 drivers +v0x1d552a0_0 .net *"_s18", 0 0, L_0x1ea3040; 1 drivers +v0x1d55380_0 .net *"_s20", 0 0, L_0x1ea3100; 1 drivers +v0x1d554f0_0 .net *"_s22", 0 0, L_0x1ea3260; 1 drivers +v0x1d555d0_0 .net *"_s24", 0 0, L_0x1ea3710; 1 drivers +L_0x7f72592dc388 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; +v0x1d556b0_0 .net *"_s30", 0 0, L_0x7f72592dc388; 1 drivers +o0x7f725933d7a8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1d55790_0 name=_s32 +v0x1d55870_0 .net *"_s8", 0 0, L_0x1ea2790; 1 drivers +v0x1d55950_0 .net "carryin", 0 0, L_0x1eab230; 1 drivers +v0x1d559f0_0 .net "carryout", 0 0, L_0x1eaaac0; 1 drivers +v0x1d55a90_0 .net "carryouts", 7 0, L_0x1ec2120; 1 drivers +v0x1d55c40_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d55ce0_0 .net "result", 0 0, L_0x1ea7080; 1 drivers +v0x1d55dd0_0 .net "results", 7 0, L_0x1ea34e0; 1 drivers +v0x1d55ee0_0 .net "zero", 0 0, L_0x1eaae20; 1 drivers +LS_0x1ea34e0_0_0 .concat8 [ 1 1 1 1], L_0x1ea1cb0, L_0x1ea22e0, L_0x1ea2790, L_0x1ea2e40; +LS_0x1ea34e0_0_4 .concat8 [ 1 1 1 1], L_0x1ea3040, L_0x1ea3100, L_0x1ea3260, L_0x1ea3710; +L_0x1ea34e0 .concat8 [ 4 4 0 0], LS_0x1ea34e0_0_0, LS_0x1ea34e0_0_4; +LS_0x1ec2120_0_0 .concat [ 1 1 1 1], L_0x1ea1f60, L_0x1ea2630, L_0x7f72592dc388, L_0x1ea2c90; +LS_0x1ec2120_0_4 .concat [ 4 0 0 0], o0x7f725933d7a8; +L_0x1ec2120 .concat [ 4 4 0 0], LS_0x1ec2120_0_0, LS_0x1ec2120_0_4; +S_0x1d46870 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d465f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1ea1f60/d .functor OR 1, L_0x1ea1a40, L_0x1ea1e00, C4<0>, C4<0>; +L_0x1ea1f60 .delay 1 (30000,30000,30000) L_0x1ea1f60/d; +v0x1d476a0_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers +v0x1d47760_0 .net "b", 0 0, L_0x1eab190; alias, 1 drivers +v0x1d47830_0 .net "c1", 0 0, L_0x1ea1a40; 1 drivers +v0x1d47930_0 .net "c2", 0 0, L_0x1ea1e00; 1 drivers +v0x1d47a00_0 .net "carryin", 0 0, L_0x1eab230; alias, 1 drivers +v0x1d47af0_0 .net "carryout", 0 0, L_0x1ea1f60; 1 drivers +v0x1d47b90_0 .net "s1", 0 0, L_0x1ea1980; 1 drivers +v0x1d47c80_0 .net "sum", 0 0, L_0x1ea1cb0; 1 drivers +S_0x1d46ae0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d46870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ea1980/d .functor XOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; +L_0x1ea1980 .delay 1 (30000,30000,30000) L_0x1ea1980/d; +L_0x1ea1a40/d .functor AND 1, L_0x1eabda0, L_0x1eab190, C4<1>, C4<1>; +L_0x1ea1a40 .delay 1 (30000,30000,30000) L_0x1ea1a40/d; +v0x1d46d40_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers +v0x1d46e20_0 .net "b", 0 0, L_0x1eab190; alias, 1 drivers +v0x1d46ee0_0 .net "carryout", 0 0, L_0x1ea1a40; alias, 1 drivers +v0x1d46f80_0 .net "sum", 0 0, L_0x1ea1980; alias, 1 drivers +S_0x1d470c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d46870; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ea1cb0/d .functor XOR 1, L_0x1ea1980, L_0x1eab230, C4<0>, C4<0>; +L_0x1ea1cb0 .delay 1 (30000,30000,30000) L_0x1ea1cb0/d; +L_0x1ea1e00/d .functor AND 1, L_0x1ea1980, L_0x1eab230, C4<1>, C4<1>; +L_0x1ea1e00 .delay 1 (30000,30000,30000) L_0x1ea1e00/d; +v0x1d47320_0 .net "a", 0 0, L_0x1ea1980; alias, 1 drivers +v0x1d473c0_0 .net "b", 0 0, L_0x1eab230; alias, 1 drivers +v0x1d47460_0 .net "carryout", 0 0, L_0x1ea1e00; alias, 1 drivers +v0x1d47530_0 .net "sum", 0 0, L_0x1ea1cb0; alias, 1 drivers +S_0x1d47d50 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d465f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d4d140_0 .net "ands", 7 0, L_0x1ea8ac0; 1 drivers +v0x1d4d250_0 .net "in", 7 0, L_0x1ec2120; alias, 1 drivers +v0x1d4d310_0 .net "out", 0 0, L_0x1eaaac0; alias, 1 drivers +v0x1d4d3e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d47f70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d47d50; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d4a6a0_0 .net "A", 7 0, L_0x1ec2120; alias, 1 drivers +v0x1d4a7a0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d4a860_0 .net *"_s0", 0 0, L_0x1ea73e0; 1 drivers +v0x1d4a920_0 .net *"_s12", 0 0, L_0x1ea7d50; 1 drivers +v0x1d4aa00_0 .net *"_s16", 0 0, L_0x1ea80b0; 1 drivers +v0x1d4ab30_0 .net *"_s20", 0 0, L_0x1ea83c0; 1 drivers +v0x1d4ac10_0 .net *"_s24", 0 0, L_0x1ea87b0; 1 drivers +v0x1d4acf0_0 .net *"_s28", 0 0, L_0x1ea8740; 1 drivers +v0x1d4add0_0 .net *"_s4", 0 0, L_0x1ea76f0; 1 drivers +v0x1d4af40_0 .net *"_s8", 0 0, L_0x1ea7a40; 1 drivers +v0x1d4b020_0 .net "out", 7 0, L_0x1ea8ac0; alias, 1 drivers +L_0x1ea74a0 .part L_0x1ec2120, 0, 1; +L_0x1ea7600 .part v0x1d6daa0_0, 0, 1; +L_0x1ea77b0 .part L_0x1ec2120, 1, 1; +L_0x1ea79a0 .part v0x1d6daa0_0, 1, 1; +L_0x1ea7b00 .part L_0x1ec2120, 2, 1; +L_0x1ea7c60 .part v0x1d6daa0_0, 2, 1; +L_0x1ea7e10 .part L_0x1ec2120, 3, 1; +L_0x1ea7f70 .part v0x1d6daa0_0, 3, 1; +L_0x1ea8170 .part L_0x1ec2120, 4, 1; +L_0x1ea82d0 .part v0x1d6daa0_0, 4, 1; +L_0x1ea8430 .part L_0x1ec2120, 5, 1; +L_0x1ea86a0 .part v0x1d6daa0_0, 5, 1; +L_0x1ea8870 .part L_0x1ec2120, 6, 1; +L_0x1ea89d0 .part v0x1d6daa0_0, 6, 1; +LS_0x1ea8ac0_0_0 .concat8 [ 1 1 1 1], L_0x1ea73e0, L_0x1ea76f0, L_0x1ea7a40, L_0x1ea7d50; +LS_0x1ea8ac0_0_4 .concat8 [ 1 1 1 1], L_0x1ea80b0, L_0x1ea83c0, L_0x1ea87b0, L_0x1ea8740; +L_0x1ea8ac0 .concat8 [ 4 4 0 0], LS_0x1ea8ac0_0_0, LS_0x1ea8ac0_0_4; +L_0x1ea8e80 .part L_0x1ec2120, 7, 1; +L_0x1ea9070 .part v0x1d6daa0_0, 7, 1; +S_0x1d481d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d483e0 .param/l "i" 0 4 54, +C4<00>; +L_0x1ea73e0/d .functor AND 1, L_0x1ea74a0, L_0x1ea7600, C4<1>, C4<1>; +L_0x1ea73e0 .delay 1 (30000,30000,30000) L_0x1ea73e0/d; +v0x1d484c0_0 .net *"_s0", 0 0, L_0x1ea74a0; 1 drivers +v0x1d485a0_0 .net *"_s1", 0 0, L_0x1ea7600; 1 drivers +S_0x1d48680 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d48890 .param/l "i" 0 4 54, +C4<01>; +L_0x1ea76f0/d .functor AND 1, L_0x1ea77b0, L_0x1ea79a0, C4<1>, C4<1>; +L_0x1ea76f0 .delay 1 (30000,30000,30000) L_0x1ea76f0/d; +v0x1d48950_0 .net *"_s0", 0 0, L_0x1ea77b0; 1 drivers +v0x1d48a30_0 .net *"_s1", 0 0, L_0x1ea79a0; 1 drivers +S_0x1d48b10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d48d20 .param/l "i" 0 4 54, +C4<010>; +L_0x1ea7a40/d .functor AND 1, L_0x1ea7b00, L_0x1ea7c60, C4<1>, C4<1>; +L_0x1ea7a40 .delay 1 (30000,30000,30000) L_0x1ea7a40/d; +v0x1d48dc0_0 .net *"_s0", 0 0, L_0x1ea7b00; 1 drivers +v0x1d48ea0_0 .net *"_s1", 0 0, L_0x1ea7c60; 1 drivers +S_0x1d48f80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d49190 .param/l "i" 0 4 54, +C4<011>; +L_0x1ea7d50/d .functor AND 1, L_0x1ea7e10, L_0x1ea7f70, C4<1>, C4<1>; +L_0x1ea7d50 .delay 1 (30000,30000,30000) L_0x1ea7d50/d; +v0x1d49250_0 .net *"_s0", 0 0, L_0x1ea7e10; 1 drivers +v0x1d49330_0 .net *"_s1", 0 0, L_0x1ea7f70; 1 drivers +S_0x1d49410 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d49670 .param/l "i" 0 4 54, +C4<0100>; +L_0x1ea80b0/d .functor AND 1, L_0x1ea8170, L_0x1ea82d0, C4<1>, C4<1>; +L_0x1ea80b0 .delay 1 (30000,30000,30000) L_0x1ea80b0/d; +v0x1d49730_0 .net *"_s0", 0 0, L_0x1ea8170; 1 drivers +v0x1d49810_0 .net *"_s1", 0 0, L_0x1ea82d0; 1 drivers +S_0x1d498f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d49b00 .param/l "i" 0 4 54, +C4<0101>; +L_0x1ea83c0/d .functor AND 1, L_0x1ea8430, L_0x1ea86a0, C4<1>, C4<1>; +L_0x1ea83c0 .delay 1 (30000,30000,30000) L_0x1ea83c0/d; +v0x1d49bc0_0 .net *"_s0", 0 0, L_0x1ea8430; 1 drivers +v0x1d49ca0_0 .net *"_s1", 0 0, L_0x1ea86a0; 1 drivers +S_0x1d49d80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d49f90 .param/l "i" 0 4 54, +C4<0110>; +L_0x1ea87b0/d .functor AND 1, L_0x1ea8870, L_0x1ea89d0, C4<1>, C4<1>; +L_0x1ea87b0 .delay 1 (30000,30000,30000) L_0x1ea87b0/d; +v0x1d4a050_0 .net *"_s0", 0 0, L_0x1ea8870; 1 drivers +v0x1d4a130_0 .net *"_s1", 0 0, L_0x1ea89d0; 1 drivers +S_0x1d4a210 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d47f70; + .timescale -9 -12; +P_0x1d4a420 .param/l "i" 0 4 54, +C4<0111>; +L_0x1ea8740/d .functor AND 1, L_0x1ea8e80, L_0x1ea9070, C4<1>, C4<1>; +L_0x1ea8740 .delay 1 (30000,30000,30000) L_0x1ea8740/d; +v0x1d4a4e0_0 .net *"_s0", 0 0, L_0x1ea8e80; 1 drivers +v0x1d4a5c0_0 .net *"_s1", 0 0, L_0x1ea9070; 1 drivers +S_0x1d4b180 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d47d50; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1eaaac0/d .functor OR 1, L_0x1eaab80, L_0x1eaad30, C4<0>, C4<0>; +L_0x1eaaac0 .delay 1 (30000,30000,30000) L_0x1eaaac0/d; +v0x1d4ccd0_0 .net *"_s10", 0 0, L_0x1eaab80; 1 drivers +v0x1d4cdb0_0 .net *"_s12", 0 0, L_0x1eaad30; 1 drivers +v0x1d4ce90_0 .net "in", 7 0, L_0x1ea8ac0; alias, 1 drivers +v0x1d4cf60_0 .net "ors", 1 0, L_0x1eaa8e0; 1 drivers +v0x1d4d020_0 .net "out", 0 0, L_0x1eaaac0; alias, 1 drivers +L_0x1ea9cb0 .part L_0x1ea8ac0, 0, 4; +L_0x1eaa8e0 .concat8 [ 1 1 0 0], L_0x1ea99a0, L_0x1eaa5d0; +L_0x1eaaa20 .part L_0x1ea8ac0, 4, 4; +L_0x1eaab80 .part L_0x1eaa8e0, 0, 1; +L_0x1eaad30 .part L_0x1eaa8e0, 1, 1; +S_0x1d4b340 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d4b180; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1ea9160/d .functor OR 1, L_0x1ea9220, L_0x1ea9380, C4<0>, C4<0>; +L_0x1ea9160 .delay 1 (30000,30000,30000) L_0x1ea9160/d; +L_0x1ea95b0/d .functor OR 1, L_0x1ea96c0, L_0x1ea9820, C4<0>, C4<0>; +L_0x1ea95b0 .delay 1 (30000,30000,30000) L_0x1ea95b0/d; +L_0x1ea99a0/d .functor OR 1, L_0x1ea9a10, L_0x1ea9bc0, C4<0>, C4<0>; +L_0x1ea99a0 .delay 1 (30000,30000,30000) L_0x1ea99a0/d; +v0x1d4b590_0 .net *"_s0", 0 0, L_0x1ea9160; 1 drivers +v0x1d4b690_0 .net *"_s10", 0 0, L_0x1ea96c0; 1 drivers +v0x1d4b770_0 .net *"_s12", 0 0, L_0x1ea9820; 1 drivers +v0x1d4b830_0 .net *"_s14", 0 0, L_0x1ea9a10; 1 drivers +v0x1d4b910_0 .net *"_s16", 0 0, L_0x1ea9bc0; 1 drivers +v0x1d4ba40_0 .net *"_s3", 0 0, L_0x1ea9220; 1 drivers +v0x1d4bb20_0 .net *"_s5", 0 0, L_0x1ea9380; 1 drivers +v0x1d4bc00_0 .net *"_s6", 0 0, L_0x1ea95b0; 1 drivers +v0x1d4bce0_0 .net "in", 3 0, L_0x1ea9cb0; 1 drivers +v0x1d4be50_0 .net "ors", 1 0, L_0x1ea94c0; 1 drivers +v0x1d4bf30_0 .net "out", 0 0, L_0x1ea99a0; 1 drivers +L_0x1ea9220 .part L_0x1ea9cb0, 0, 1; +L_0x1ea9380 .part L_0x1ea9cb0, 1, 1; +L_0x1ea94c0 .concat8 [ 1 1 0 0], L_0x1ea9160, L_0x1ea95b0; +L_0x1ea96c0 .part L_0x1ea9cb0, 2, 1; +L_0x1ea9820 .part L_0x1ea9cb0, 3, 1; +L_0x1ea9a10 .part L_0x1ea94c0, 0, 1; +L_0x1ea9bc0 .part L_0x1ea94c0, 1, 1; +S_0x1d4c050 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d4b180; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1ea9de0/d .functor OR 1, L_0x1ea9e50, L_0x1ea9fb0, C4<0>, C4<0>; +L_0x1ea9de0 .delay 1 (30000,30000,30000) L_0x1ea9de0/d; +L_0x1eaa1e0/d .functor OR 1, L_0x1eaa2f0, L_0x1eaa450, C4<0>, C4<0>; +L_0x1eaa1e0 .delay 1 (30000,30000,30000) L_0x1eaa1e0/d; +L_0x1eaa5d0/d .functor OR 1, L_0x1eaa640, L_0x1eaa7f0, C4<0>, C4<0>; +L_0x1eaa5d0 .delay 1 (30000,30000,30000) L_0x1eaa5d0/d; +v0x1d4c210_0 .net *"_s0", 0 0, L_0x1ea9de0; 1 drivers +v0x1d4c310_0 .net *"_s10", 0 0, L_0x1eaa2f0; 1 drivers +v0x1d4c3f0_0 .net *"_s12", 0 0, L_0x1eaa450; 1 drivers +v0x1d4c4b0_0 .net *"_s14", 0 0, L_0x1eaa640; 1 drivers +v0x1d4c590_0 .net *"_s16", 0 0, L_0x1eaa7f0; 1 drivers +v0x1d4c6c0_0 .net *"_s3", 0 0, L_0x1ea9e50; 1 drivers +v0x1d4c7a0_0 .net *"_s5", 0 0, L_0x1ea9fb0; 1 drivers +v0x1d4c880_0 .net *"_s6", 0 0, L_0x1eaa1e0; 1 drivers +v0x1d4c960_0 .net "in", 3 0, L_0x1eaaa20; 1 drivers +v0x1d4cad0_0 .net "ors", 1 0, L_0x1eaa0f0; 1 drivers +v0x1d4cbb0_0 .net "out", 0 0, L_0x1eaa5d0; 1 drivers +L_0x1ea9e50 .part L_0x1eaaa20, 0, 1; +L_0x1ea9fb0 .part L_0x1eaaa20, 1, 1; +L_0x1eaa0f0 .concat8 [ 1 1 0 0], L_0x1ea9de0, L_0x1eaa1e0; +L_0x1eaa2f0 .part L_0x1eaaa20, 2, 1; +L_0x1eaa450 .part L_0x1eaaa20, 3, 1; +L_0x1eaa640 .part L_0x1eaa0f0, 0, 1; +L_0x1eaa7f0 .part L_0x1eaa0f0, 1, 1; +S_0x1d4d4c0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d465f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" + .port_info 2 /INPUT 8 "sel" +v0x1d528f0_0 .net "ands", 7 0, L_0x1ea5080; 1 drivers +v0x1d52a00_0 .net "in", 7 0, L_0x1ea34e0; alias, 1 drivers +v0x1d52ac0_0 .net "out", 0 0, L_0x1ea7080; alias, 1 drivers +v0x1d52b90_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers +S_0x1d4d710 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d4d4c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 8 "out" + .port_info 1 /INPUT 8 "A" + .port_info 2 /INPUT 8 "B" +v0x1d4fe50_0 .net "A", 7 0, L_0x1ea34e0; alias, 1 drivers +v0x1d4ff50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers +v0x1d50010_0 .net *"_s0", 0 0, L_0x1ea3870; 1 drivers +v0x1d500d0_0 .net *"_s12", 0 0, L_0x1ea4230; 1 drivers +v0x1d501b0_0 .net *"_s16", 0 0, L_0x1ea4590; 1 drivers +v0x1d502e0_0 .net *"_s20", 0 0, L_0x1ea49c0; 1 drivers +v0x1d503c0_0 .net *"_s24", 0 0, L_0x1ea4cf0; 1 drivers +v0x1d504a0_0 .net *"_s28", 0 0, L_0x1ea4c80; 1 drivers +v0x1d50580_0 .net *"_s4", 0 0, L_0x1ea3c10; 1 drivers +v0x1d506f0_0 .net *"_s8", 0 0, L_0x1ea3f20; 1 drivers +v0x1d507d0_0 .net "out", 7 0, L_0x1ea5080; alias, 1 drivers +L_0x1ea3980 .part L_0x1ea34e0, 0, 1; +L_0x1ea3b70 .part v0x1d6daa0_0, 0, 1; +L_0x1ea3cd0 .part L_0x1ea34e0, 1, 1; +L_0x1ea3e30 .part v0x1d6daa0_0, 1, 1; +L_0x1ea3fe0 .part L_0x1ea34e0, 2, 1; +L_0x1ea4140 .part v0x1d6daa0_0, 2, 1; +L_0x1ea42f0 .part L_0x1ea34e0, 3, 1; +L_0x1ea4450 .part v0x1d6daa0_0, 3, 1; +L_0x1ea4650 .part L_0x1ea34e0, 4, 1; +L_0x1ea48c0 .part v0x1d6daa0_0, 4, 1; +L_0x1ea4a30 .part L_0x1ea34e0, 5, 1; +L_0x1ea4b90 .part v0x1d6daa0_0, 5, 1; +L_0x1ea4db0 .part L_0x1ea34e0, 6, 1; +L_0x1ea4f10 .part v0x1d6daa0_0, 6, 1; +LS_0x1ea5080_0_0 .concat8 [ 1 1 1 1], L_0x1ea3870, L_0x1ea3c10, L_0x1ea3f20, L_0x1ea4230; +LS_0x1ea5080_0_4 .concat8 [ 1 1 1 1], L_0x1ea4590, L_0x1ea49c0, L_0x1ea4cf0, L_0x1ea4c80; +L_0x1ea5080 .concat8 [ 4 4 0 0], LS_0x1ea5080_0_0, LS_0x1ea5080_0_4; +L_0x1ea5440 .part L_0x1ea34e0, 7, 1; +L_0x1ea5630 .part v0x1d6daa0_0, 7, 1; +S_0x1d4d950 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4db60 .param/l "i" 0 4 54, +C4<00>; +L_0x1ea3870/d .functor AND 1, L_0x1ea3980, L_0x1ea3b70, C4<1>, C4<1>; +L_0x1ea3870 .delay 1 (30000,30000,30000) L_0x1ea3870/d; +v0x1d4dc40_0 .net *"_s0", 0 0, L_0x1ea3980; 1 drivers +v0x1d4dd20_0 .net *"_s1", 0 0, L_0x1ea3b70; 1 drivers +S_0x1d4de00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4e010 .param/l "i" 0 4 54, +C4<01>; +L_0x1ea3c10/d .functor AND 1, L_0x1ea3cd0, L_0x1ea3e30, C4<1>, C4<1>; +L_0x1ea3c10 .delay 1 (30000,30000,30000) L_0x1ea3c10/d; +v0x1d4e0d0_0 .net *"_s0", 0 0, L_0x1ea3cd0; 1 drivers +v0x1d4e1b0_0 .net *"_s1", 0 0, L_0x1ea3e30; 1 drivers +S_0x1d4e290 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4e4d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1ea3f20/d .functor AND 1, L_0x1ea3fe0, L_0x1ea4140, C4<1>, C4<1>; +L_0x1ea3f20 .delay 1 (30000,30000,30000) L_0x1ea3f20/d; +v0x1d4e570_0 .net *"_s0", 0 0, L_0x1ea3fe0; 1 drivers +v0x1d4e650_0 .net *"_s1", 0 0, L_0x1ea4140; 1 drivers +S_0x1d4e730 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4e940 .param/l "i" 0 4 54, +C4<011>; +L_0x1ea4230/d .functor AND 1, L_0x1ea42f0, L_0x1ea4450, C4<1>, C4<1>; +L_0x1ea4230 .delay 1 (30000,30000,30000) L_0x1ea4230/d; +v0x1d4ea00_0 .net *"_s0", 0 0, L_0x1ea42f0; 1 drivers +v0x1d4eae0_0 .net *"_s1", 0 0, L_0x1ea4450; 1 drivers +S_0x1d4ebc0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4ee20 .param/l "i" 0 4 54, +C4<0100>; +L_0x1ea4590/d .functor AND 1, L_0x1ea4650, L_0x1ea48c0, C4<1>, C4<1>; +L_0x1ea4590 .delay 1 (30000,30000,30000) L_0x1ea4590/d; +v0x1d4eee0_0 .net *"_s0", 0 0, L_0x1ea4650; 1 drivers +v0x1d4efc0_0 .net *"_s1", 0 0, L_0x1ea48c0; 1 drivers +S_0x1d4f0a0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4f2b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1ea49c0/d .functor AND 1, L_0x1ea4a30, L_0x1ea4b90, C4<1>, C4<1>; +L_0x1ea49c0 .delay 1 (30000,30000,30000) L_0x1ea49c0/d; +v0x1d4f370_0 .net *"_s0", 0 0, L_0x1ea4a30; 1 drivers +v0x1d4f450_0 .net *"_s1", 0 0, L_0x1ea4b90; 1 drivers +S_0x1d4f530 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4f740 .param/l "i" 0 4 54, +C4<0110>; +L_0x1ea4cf0/d .functor AND 1, L_0x1ea4db0, L_0x1ea4f10, C4<1>, C4<1>; +L_0x1ea4cf0 .delay 1 (30000,30000,30000) L_0x1ea4cf0/d; +v0x1d4f800_0 .net *"_s0", 0 0, L_0x1ea4db0; 1 drivers +v0x1d4f8e0_0 .net *"_s1", 0 0, L_0x1ea4f10; 1 drivers +S_0x1d4f9c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d4d710; + .timescale -9 -12; +P_0x1d4fbd0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1ea4c80/d .functor AND 1, L_0x1ea5440, L_0x1ea5630, C4<1>, C4<1>; +L_0x1ea4c80 .delay 1 (30000,30000,30000) L_0x1ea4c80/d; +v0x1d4fc90_0 .net *"_s0", 0 0, L_0x1ea5440; 1 drivers +v0x1d4fd70_0 .net *"_s1", 0 0, L_0x1ea5630; 1 drivers +S_0x1d50930 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d4d4c0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1ea7080/d .functor OR 1, L_0x1ea7140, L_0x1ea72f0, C4<0>, C4<0>; +L_0x1ea7080 .delay 1 (30000,30000,30000) L_0x1ea7080/d; +v0x1d52480_0 .net *"_s10", 0 0, L_0x1ea7140; 1 drivers +v0x1d52560_0 .net *"_s12", 0 0, L_0x1ea72f0; 1 drivers +v0x1d52640_0 .net "in", 7 0, L_0x1ea5080; alias, 1 drivers +v0x1d52710_0 .net "ors", 1 0, L_0x1ea6ea0; 1 drivers +v0x1d527d0_0 .net "out", 0 0, L_0x1ea7080; alias, 1 drivers +L_0x1ea6270 .part L_0x1ea5080, 0, 4; +L_0x1ea6ea0 .concat8 [ 1 1 0 0], L_0x1ea5f60, L_0x1ea6b90; +L_0x1ea6fe0 .part L_0x1ea5080, 4, 4; +L_0x1ea7140 .part L_0x1ea6ea0, 0, 1; +L_0x1ea72f0 .part L_0x1ea6ea0, 1, 1; +S_0x1d50af0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d50930; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1ea5720/d .functor OR 1, L_0x1ea57e0, L_0x1ea5940, C4<0>, C4<0>; +L_0x1ea5720 .delay 1 (30000,30000,30000) L_0x1ea5720/d; +L_0x1ea5b70/d .functor OR 1, L_0x1ea5c80, L_0x1ea5de0, C4<0>, C4<0>; +L_0x1ea5b70 .delay 1 (30000,30000,30000) L_0x1ea5b70/d; +L_0x1ea5f60/d .functor OR 1, L_0x1ea5fd0, L_0x1ea6180, C4<0>, C4<0>; +L_0x1ea5f60 .delay 1 (30000,30000,30000) L_0x1ea5f60/d; +v0x1d50d40_0 .net *"_s0", 0 0, L_0x1ea5720; 1 drivers +v0x1d50e40_0 .net *"_s10", 0 0, L_0x1ea5c80; 1 drivers +v0x1d50f20_0 .net *"_s12", 0 0, L_0x1ea5de0; 1 drivers +v0x1d50fe0_0 .net *"_s14", 0 0, L_0x1ea5fd0; 1 drivers +v0x1d510c0_0 .net *"_s16", 0 0, L_0x1ea6180; 1 drivers +v0x1d511f0_0 .net *"_s3", 0 0, L_0x1ea57e0; 1 drivers +v0x1d512d0_0 .net *"_s5", 0 0, L_0x1ea5940; 1 drivers +v0x1d513b0_0 .net *"_s6", 0 0, L_0x1ea5b70; 1 drivers +v0x1d51490_0 .net "in", 3 0, L_0x1ea6270; 1 drivers +v0x1d51600_0 .net "ors", 1 0, L_0x1ea5a80; 1 drivers +v0x1d516e0_0 .net "out", 0 0, L_0x1ea5f60; 1 drivers +L_0x1ea57e0 .part L_0x1ea6270, 0, 1; +L_0x1ea5940 .part L_0x1ea6270, 1, 1; +L_0x1ea5a80 .concat8 [ 1 1 0 0], L_0x1ea5720, L_0x1ea5b70; +L_0x1ea5c80 .part L_0x1ea6270, 2, 1; +L_0x1ea5de0 .part L_0x1ea6270, 3, 1; +L_0x1ea5fd0 .part L_0x1ea5a80, 0, 1; +L_0x1ea6180 .part L_0x1ea5a80, 1, 1; +S_0x1d51800 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d50930; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1ea63a0/d .functor OR 1, L_0x1ea6410, L_0x1ea6570, C4<0>, C4<0>; +L_0x1ea63a0 .delay 1 (30000,30000,30000) L_0x1ea63a0/d; +L_0x1ea67a0/d .functor OR 1, L_0x1ea68b0, L_0x1ea6a10, C4<0>, C4<0>; +L_0x1ea67a0 .delay 1 (30000,30000,30000) L_0x1ea67a0/d; +L_0x1ea6b90/d .functor OR 1, L_0x1ea6c00, L_0x1ea6db0, C4<0>, C4<0>; +L_0x1ea6b90 .delay 1 (30000,30000,30000) L_0x1ea6b90/d; +v0x1d519c0_0 .net *"_s0", 0 0, L_0x1ea63a0; 1 drivers +v0x1d51ac0_0 .net *"_s10", 0 0, L_0x1ea68b0; 1 drivers +v0x1d51ba0_0 .net *"_s12", 0 0, L_0x1ea6a10; 1 drivers +v0x1d51c60_0 .net *"_s14", 0 0, L_0x1ea6c00; 1 drivers +v0x1d51d40_0 .net *"_s16", 0 0, L_0x1ea6db0; 1 drivers +v0x1d51e70_0 .net *"_s3", 0 0, L_0x1ea6410; 1 drivers +v0x1d51f50_0 .net *"_s5", 0 0, L_0x1ea6570; 1 drivers +v0x1d52030_0 .net *"_s6", 0 0, L_0x1ea67a0; 1 drivers +v0x1d52110_0 .net "in", 3 0, L_0x1ea6fe0; 1 drivers +v0x1d52280_0 .net "ors", 1 0, L_0x1ea66b0; 1 drivers +v0x1d52360_0 .net "out", 0 0, L_0x1ea6b90; 1 drivers +L_0x1ea6410 .part L_0x1ea6fe0, 0, 1; +L_0x1ea6570 .part L_0x1ea6fe0, 1, 1; +L_0x1ea66b0 .concat8 [ 1 1 0 0], L_0x1ea63a0, L_0x1ea67a0; +L_0x1ea68b0 .part L_0x1ea6fe0, 2, 1; +L_0x1ea6a10 .part L_0x1ea6fe0, 3, 1; +L_0x1ea6c00 .part L_0x1ea66b0, 0, 1; +L_0x1ea6db0 .part L_0x1ea66b0, 1, 1; +S_0x1d52c70 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d465f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "carryin" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "a_" + .port_info 4 /INPUT 1 "b" + .port_info 5 /INPUT 1 "b_" +L_0x1ea2850/d .functor XNOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; +L_0x1ea2850 .delay 1 (20000,20000,20000) L_0x1ea2850/d; +L_0x1ea2ac0/d .functor AND 1, L_0x1eabda0, L_0x1e97580, C4<1>, C4<1>; +L_0x1ea2ac0 .delay 1 (30000,30000,30000) L_0x1ea2ac0/d; +L_0x1ea2b30/d .functor AND 1, L_0x1ea2850, L_0x1eab230, C4<1>, C4<1>; +L_0x1ea2b30 .delay 1 (30000,30000,30000) L_0x1ea2b30/d; +L_0x1ea2c90/d .functor OR 1, L_0x1ea2b30, L_0x1ea2ac0, C4<0>, C4<0>; +L_0x1ea2c90 .delay 1 (30000,30000,30000) L_0x1ea2c90/d; +v0x1d52f20_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers +v0x1d53010_0 .net "a_", 0 0, L_0x1e029c0; alias, 1 drivers +v0x1d530d0_0 .net "b", 0 0, L_0x1eab190; alias, 1 drivers +v0x1d531c0_0 .net "b_", 0 0, L_0x1e97580; alias, 1 drivers +v0x1d53260_0 .net "carryin", 0 0, L_0x1eab230; alias, 1 drivers +v0x1d533a0_0 .net "eq", 0 0, L_0x1ea2850; 1 drivers +v0x1d53460_0 .net "lt", 0 0, L_0x1ea2ac0; 1 drivers +v0x1d53520_0 .net "out", 0 0, L_0x1ea2c90; 1 drivers +v0x1d535e0_0 .net "w0", 0 0, L_0x1ea2b30; 1 drivers +S_0x1d53830 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d465f0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" + .port_info 4 /INPUT 1 "carryin" +L_0x1ea2630/d .functor OR 1, L_0x1ea2180, L_0x1d54a90, C4<0>, C4<0>; +L_0x1ea2630 .delay 1 (30000,30000,30000) L_0x1ea2630/d; +v0x1d54620_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers +v0x1d54770_0 .net "b", 0 0, L_0x1e97580; alias, 1 drivers +v0x1d54830_0 .net "c1", 0 0, L_0x1ea2180; 1 drivers +v0x1d548d0_0 .net "c2", 0 0, L_0x1d54a90; 1 drivers +v0x1d549a0_0 .net "carryin", 0 0, L_0x1eab230; alias, 1 drivers +v0x1d54b20_0 .net "carryout", 0 0, L_0x1ea2630; 1 drivers +v0x1d54bc0_0 .net "s1", 0 0, L_0x1ea20c0; 1 drivers +v0x1d54c60_0 .net "sum", 0 0, L_0x1ea22e0; 1 drivers +S_0x1d53a80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d53830; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ea20c0/d .functor XOR 1, L_0x1eabda0, L_0x1e97580, C4<0>, C4<0>; +L_0x1ea20c0 .delay 1 (30000,30000,30000) L_0x1ea20c0/d; +L_0x1ea2180/d .functor AND 1, L_0x1eabda0, L_0x1e97580, C4<1>, C4<1>; +L_0x1ea2180 .delay 1 (30000,30000,30000) L_0x1ea2180/d; +v0x1d53ce0_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers +v0x1d53da0_0 .net "b", 0 0, L_0x1e97580; alias, 1 drivers +v0x1d53e60_0 .net "carryout", 0 0, L_0x1ea2180; alias, 1 drivers +v0x1d53f00_0 .net "sum", 0 0, L_0x1ea20c0; alias, 1 drivers +S_0x1d54030 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d53830; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "sum" + .port_info 1 /OUTPUT 1 "carryout" + .port_info 2 /INPUT 1 "a" + .port_info 3 /INPUT 1 "b" +L_0x1ea22e0/d .functor XOR 1, L_0x1ea20c0, L_0x1eab230, C4<0>, C4<0>; +L_0x1ea22e0 .delay 1 (30000,30000,30000) L_0x1ea22e0/d; +L_0x1d54a90/d .functor AND 1, L_0x1ea20c0, L_0x1eab230, C4<1>, C4<1>; +L_0x1d54a90 .delay 1 (30000,30000,30000) L_0x1d54a90/d; +v0x1d54290_0 .net "a", 0 0, L_0x1ea20c0; alias, 1 drivers +v0x1d54360_0 .net "b", 0 0, L_0x1eab230; alias, 1 drivers +v0x1d54400_0 .net "carryout", 0 0, L_0x1d54a90; alias, 1 drivers +v0x1d544d0_0 .net "sum", 0 0, L_0x1ea22e0; alias, 1 drivers +S_0x1d56080 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d46320; + .timescale -9 -12; +L_0x7f72592dc2f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x7f72592dc340 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1ea5000/d .functor OR 1, L_0x7f72592dc2f8, L_0x7f72592dc340, C4<0>, C4<0>; +L_0x1ea5000 .delay 1 (30000,30000,30000) L_0x1ea5000/d; +v0x1d56270_0 .net/2u *"_s0", 0 0, L_0x7f72592dc2f8; 1 drivers +v0x1d56350_0 .net/2u *"_s2", 0 0, L_0x7f72592dc340; 1 drivers +S_0x1d56430 .scope module, "resultOr" "or32P" 3 64, 4 60 0, S_0x1a570b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 32 "out" + .port_info 1 /INPUT 32 "A" + .port_info 2 /INPUT 32 "B" +v0x1d5f9d0_0 .net "A", 31 0, L_0x1eaaf20; alias, 1 drivers +v0x1d5fad0_0 .net "B", 31 0, L_0x1eb5ac0; alias, 1 drivers +v0x1d5fbb0_0 .net *"_s0", 0 0, L_0x1eb7220; 1 drivers +v0x1d5fc70_0 .net *"_s100", 0 0, L_0x1ebc240; 1 drivers +v0x1d5fd50_0 .net *"_s104", 0 0, L_0x1ebc560; 1 drivers +v0x1d5fe80_0 .net *"_s108", 0 0, L_0x1ebc890; 1 drivers +v0x1d5ff60_0 .net *"_s112", 0 0, L_0x1ebcbd0; 1 drivers +v0x1d60040_0 .net *"_s116", 0 0, L_0x1ebced0; 1 drivers +v0x1d60120_0 .net *"_s12", 0 0, L_0x1eb7c20; 1 drivers +v0x1d60290_0 .net *"_s120", 0 0, L_0x1eba2e0; 1 drivers +v0x1d60370_0 .net *"_s124", 0 0, L_0x1ebe820; 1 drivers +v0x1d60450_0 .net *"_s16", 0 0, L_0x1eb7f80; 1 drivers +v0x1d60530_0 .net *"_s20", 0 0, L_0x1eb82f0; 1 drivers +v0x1d60610_0 .net *"_s24", 0 0, L_0x1eb8780; 1 drivers +v0x1d606f0_0 .net *"_s28", 0 0, L_0x1eb8a90; 1 drivers +v0x1d607d0_0 .net *"_s32", 0 0, L_0x1eb8da0; 1 drivers +v0x1d608b0_0 .net *"_s36", 0 0, L_0x1eb78d0; 1 drivers +v0x1d60a60_0 .net *"_s4", 0 0, L_0x1eb7580; 1 drivers +v0x1d60b00_0 .net *"_s40", 0 0, L_0x1eb90b0; 1 drivers +v0x1d60be0_0 .net *"_s44", 0 0, L_0x1eb93f0; 1 drivers +v0x1d60cc0_0 .net *"_s48", 0 0, L_0x1eb9740; 1 drivers +v0x1d60da0_0 .net *"_s52", 0 0, L_0x1eb9aa0; 1 drivers +v0x1d60e80_0 .net *"_s56", 0 0, L_0x1eb9dc0; 1 drivers +v0x1d60f60_0 .net *"_s60", 0 0, L_0x1eba670; 1 drivers +v0x1d61040_0 .net *"_s64", 0 0, L_0x1eba980; 1 drivers +v0x1d61120_0 .net *"_s68", 0 0, L_0x1eb8670; 1 drivers +v0x1d61200_0 .net *"_s72", 0 0, L_0x1ebac90; 1 drivers +v0x1d612e0_0 .net *"_s76", 0 0, L_0x1ebaf90; 1 drivers +v0x1d613c0_0 .net *"_s8", 0 0, L_0x1eb7960; 1 drivers +v0x1d614a0_0 .net *"_s80", 0 0, L_0x1ebb2a0; 1 drivers +v0x1d61580_0 .net *"_s84", 0 0, L_0x1ebb5c0; 1 drivers +v0x1d61660_0 .net *"_s88", 0 0, L_0x1ebb8f0; 1 drivers +v0x1d61740_0 .net *"_s92", 0 0, L_0x1ebbc30; 1 drivers +v0x1d60990_0 .net *"_s96", 0 0, L_0x1ebbf30; 1 drivers +v0x1d61a10_0 .net "out", 31 0, L_0x1eba0f0; alias, 1 drivers +L_0x1eb7330 .part L_0x1eaaf20, 0, 1; +L_0x1eb7490 .part L_0x1eb5ac0, 0, 1; +L_0x1eb7640 .part L_0x1eaaf20, 1, 1; +L_0x1eb7830 .part L_0x1eb5ac0, 1, 1; +L_0x1eb79d0 .part L_0x1eaaf20, 2, 1; +L_0x1eb7b30 .part L_0x1eb5ac0, 2, 1; +L_0x1eb7ce0 .part L_0x1eaaf20, 3, 1; +L_0x1eb7e40 .part L_0x1eb5ac0, 3, 1; +L_0x1eb8040 .part L_0x1eaaf20, 4, 1; +L_0x1eb81a0 .part L_0x1eb5ac0, 4, 1; +L_0x1eb8360 .part L_0x1eaaf20, 5, 1; +L_0x1eb85d0 .part L_0x1eb5ac0, 5, 1; +L_0x1eb8840 .part L_0x1eaaf20, 6, 1; +L_0x1eb89a0 .part L_0x1eb5ac0, 6, 1; +L_0x1eb8b50 .part L_0x1eaaf20, 7, 1; +L_0x1eb8cb0 .part L_0x1eb5ac0, 7, 1; +L_0x1eb8e60 .part L_0x1eaaf20, 8, 1; +L_0x1eb8fc0 .part L_0x1eb5ac0, 8, 1; +L_0x1eb91a0 .part L_0x1eaaf20, 9, 1; +L_0x1eb9300 .part L_0x1eb5ac0, 9, 1; +L_0x1eb94f0 .part L_0x1eaaf20, 10, 1; +L_0x1eb9650 .part L_0x1eb5ac0, 10, 1; +L_0x1eb9850 .part L_0x1eaaf20, 11, 1; +L_0x1eb99b0 .part L_0x1eb5ac0, 11, 1; +L_0x1eb9b70 .part L_0x1eaaf20, 12, 1; +L_0x1eb9cd0 .part L_0x1eb5ac0, 12, 1; +L_0x1eb9ea0 .part L_0x1eaaf20, 13, 1; +L_0x1eb84c0 .part L_0x1eb5ac0, 13, 1; +L_0x1eba420 .part L_0x1eaaf20, 14, 1; +L_0x1eba580 .part L_0x1eb5ac0, 14, 1; +L_0x1eba730 .part L_0x1eaaf20, 15, 1; +L_0x1eba890 .part L_0x1eb5ac0, 15, 1; +L_0x1ebaa40 .part L_0x1eaaf20, 16, 1; +L_0x1ebaba0 .part L_0x1eb5ac0, 16, 1; +L_0x1ebadb0 .part L_0x1eaaf20, 17, 1; +L_0x1ebaea0 .part L_0x1eb5ac0, 17, 1; +L_0x1ebb0c0 .part L_0x1eaaf20, 18, 1; +L_0x1ebb1b0 .part L_0x1eb5ac0, 18, 1; +L_0x1ebb3e0 .part L_0x1eaaf20, 19, 1; +L_0x1ebb4d0 .part L_0x1eb5ac0, 19, 1; +L_0x1ebb710 .part L_0x1eaaf20, 20, 1; +L_0x1ebb800 .part L_0x1eb5ac0, 20, 1; +L_0x1ebba50 .part L_0x1eaaf20, 21, 1; +L_0x1ebbb40 .part L_0x1eb5ac0, 21, 1; +L_0x1ebbda0 .part L_0x1eaaf20, 22, 1; +L_0x1ebbe40 .part L_0x1eb5ac0, 22, 1; +L_0x1ebc0b0 .part L_0x1eaaf20, 23, 1; +L_0x1ebc150 .part L_0x1eb5ac0, 23, 1; +L_0x1ebc3d0 .part L_0x1eaaf20, 24, 1; +L_0x1ebc470 .part L_0x1eb5ac0, 24, 1; +L_0x1ebc700 .part L_0x1eaaf20, 25, 1; +L_0x1ebc7a0 .part L_0x1eb5ac0, 25, 1; +L_0x1ebca40 .part L_0x1eaaf20, 26, 1; +L_0x1ebcae0 .part L_0x1eb5ac0, 26, 1; +L_0x1ebc9a0 .part L_0x1eaaf20, 27, 1; +L_0x1ebcde0 .part L_0x1eb5ac0, 27, 1; +L_0x1ebcce0 .part L_0x1eaaf20, 28, 1; +L_0x1ebd0f0 .part L_0x1eb5ac0, 28, 1; +L_0x1ebcf90 .part L_0x1eaaf20, 29, 1; +L_0x1eba000 .part L_0x1eb5ac0, 29, 1; +L_0x1ebd1e0 .part L_0x1eaaf20, 30, 1; +L_0x1ebdc30 .part L_0x1eb5ac0, 30, 1; +LS_0x1eba0f0_0_0 .concat8 [ 1 1 1 1], L_0x1eb7220, L_0x1eb7580, L_0x1eb7960, L_0x1eb7c20; +LS_0x1eba0f0_0_4 .concat8 [ 1 1 1 1], L_0x1eb7f80, L_0x1eb82f0, L_0x1eb8780, L_0x1eb8a90; +LS_0x1eba0f0_0_8 .concat8 [ 1 1 1 1], L_0x1eb8da0, L_0x1eb78d0, L_0x1eb90b0, L_0x1eb93f0; +LS_0x1eba0f0_0_12 .concat8 [ 1 1 1 1], L_0x1eb9740, L_0x1eb9aa0, L_0x1eb9dc0, L_0x1eba670; +LS_0x1eba0f0_0_16 .concat8 [ 1 1 1 1], L_0x1eba980, L_0x1eb8670, L_0x1ebac90, L_0x1ebaf90; +LS_0x1eba0f0_0_20 .concat8 [ 1 1 1 1], L_0x1ebb2a0, L_0x1ebb5c0, L_0x1ebb8f0, L_0x1ebbc30; +LS_0x1eba0f0_0_24 .concat8 [ 1 1 1 1], L_0x1ebbf30, L_0x1ebc240, L_0x1ebc560, L_0x1ebc890; +LS_0x1eba0f0_0_28 .concat8 [ 1 1 1 1], L_0x1ebcbd0, L_0x1ebced0, L_0x1eba2e0, L_0x1ebe820; +LS_0x1eba0f0_1_0 .concat8 [ 4 4 4 4], LS_0x1eba0f0_0_0, LS_0x1eba0f0_0_4, LS_0x1eba0f0_0_8, LS_0x1eba0f0_0_12; +LS_0x1eba0f0_1_4 .concat8 [ 4 4 4 4], LS_0x1eba0f0_0_16, LS_0x1eba0f0_0_20, LS_0x1eba0f0_0_24, LS_0x1eba0f0_0_28; +L_0x1eba0f0 .concat8 [ 16 16 0 0], LS_0x1eba0f0_1_0, LS_0x1eba0f0_1_4; +L_0x1ebe930 .part L_0x1eaaf20, 31, 1; +L_0x1ebdcd0 .part L_0x1eb5ac0, 31, 1; +S_0x1d56810 .scope generate, "or_slces[0]" "or_slces[0]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d56990 .param/l "i" 0 4 63, +C4<00>; +L_0x1eb7220/d .functor OR 1, L_0x1eb7330, L_0x1eb7490, C4<0>, C4<0>; +L_0x1eb7220 .delay 1 (30000,30000,30000) L_0x1eb7220/d; +v0x1d56a70_0 .net *"_s0", 0 0, L_0x1eb7330; 1 drivers +v0x1d56b50_0 .net *"_s1", 0 0, L_0x1eb7490; 1 drivers +S_0x1d56c30 .scope generate, "or_slces[1]" "or_slces[1]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d56e40 .param/l "i" 0 4 63, +C4<01>; +L_0x1eb7580/d .functor OR 1, L_0x1eb7640, L_0x1eb7830, C4<0>, C4<0>; +L_0x1eb7580 .delay 1 (30000,30000,30000) L_0x1eb7580/d; +v0x1d56f00_0 .net *"_s0", 0 0, L_0x1eb7640; 1 drivers +v0x1d56fe0_0 .net *"_s1", 0 0, L_0x1eb7830; 1 drivers +S_0x1d57080 .scope generate, "or_slces[2]" "or_slces[2]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d57250 .param/l "i" 0 4 63, +C4<010>; +L_0x1eb7960/d .functor OR 1, L_0x1eb79d0, L_0x1eb7b30, C4<0>, C4<0>; +L_0x1eb7960 .delay 1 (30000,30000,30000) L_0x1eb7960/d; +v0x1d572f0_0 .net *"_s0", 0 0, L_0x1eb79d0; 1 drivers +v0x1d57390_0 .net *"_s1", 0 0, L_0x1eb7b30; 1 drivers +S_0x1d57470 .scope generate, "or_slces[3]" "or_slces[3]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d57680 .param/l "i" 0 4 63, +C4<011>; +L_0x1eb7c20/d .functor OR 1, L_0x1eb7ce0, L_0x1eb7e40, C4<0>, C4<0>; +L_0x1eb7c20 .delay 1 (30000,30000,30000) L_0x1eb7c20/d; +v0x1d57740_0 .net *"_s0", 0 0, L_0x1eb7ce0; 1 drivers +v0x1d57820_0 .net *"_s1", 0 0, L_0x1eb7e40; 1 drivers +S_0x1d57900 .scope generate, "or_slces[4]" "or_slces[4]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d57b60 .param/l "i" 0 4 63, +C4<0100>; +L_0x1eb7f80/d .functor OR 1, L_0x1eb8040, L_0x1eb81a0, C4<0>, C4<0>; +L_0x1eb7f80 .delay 1 (30000,30000,30000) L_0x1eb7f80/d; +v0x1d57c20_0 .net *"_s0", 0 0, L_0x1eb8040; 1 drivers +v0x1d57d00_0 .net *"_s1", 0 0, L_0x1eb81a0; 1 drivers +S_0x1d57de0 .scope generate, "or_slces[5]" "or_slces[5]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d57ff0 .param/l "i" 0 4 63, +C4<0101>; +L_0x1eb82f0/d .functor OR 1, L_0x1eb8360, L_0x1eb85d0, C4<0>, C4<0>; +L_0x1eb82f0 .delay 1 (30000,30000,30000) L_0x1eb82f0/d; +v0x1d580b0_0 .net *"_s0", 0 0, L_0x1eb8360; 1 drivers +v0x1d58190_0 .net *"_s1", 0 0, L_0x1eb85d0; 1 drivers +S_0x1d58270 .scope generate, "or_slces[6]" "or_slces[6]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d58480 .param/l "i" 0 4 63, +C4<0110>; +L_0x1eb8780/d .functor OR 1, L_0x1eb8840, L_0x1eb89a0, C4<0>, C4<0>; +L_0x1eb8780 .delay 1 (30000,30000,30000) L_0x1eb8780/d; +v0x1d58540_0 .net *"_s0", 0 0, L_0x1eb8840; 1 drivers +v0x1d58620_0 .net *"_s1", 0 0, L_0x1eb89a0; 1 drivers +S_0x1d58700 .scope generate, "or_slces[7]" "or_slces[7]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d58910 .param/l "i" 0 4 63, +C4<0111>; +L_0x1eb8a90/d .functor OR 1, L_0x1eb8b50, L_0x1eb8cb0, C4<0>, C4<0>; +L_0x1eb8a90 .delay 1 (30000,30000,30000) L_0x1eb8a90/d; +v0x1d589d0_0 .net *"_s0", 0 0, L_0x1eb8b50; 1 drivers +v0x1d58ab0_0 .net *"_s1", 0 0, L_0x1eb8cb0; 1 drivers +S_0x1d58b90 .scope generate, "or_slces[8]" "or_slces[8]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d57b10 .param/l "i" 0 4 63, +C4<01000>; +L_0x1eb8da0/d .functor OR 1, L_0x1eb8e60, L_0x1eb8fc0, C4<0>, C4<0>; +L_0x1eb8da0 .delay 1 (30000,30000,30000) L_0x1eb8da0/d; +v0x1d58ea0_0 .net *"_s0", 0 0, L_0x1eb8e60; 1 drivers +v0x1d58f80_0 .net *"_s1", 0 0, L_0x1eb8fc0; 1 drivers +S_0x1d59060 .scope generate, "or_slces[9]" "or_slces[9]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d59270 .param/l "i" 0 4 63, +C4<01001>; +L_0x1eb78d0/d .functor OR 1, L_0x1eb91a0, L_0x1eb9300, C4<0>, C4<0>; +L_0x1eb78d0 .delay 1 (30000,30000,30000) L_0x1eb78d0/d; +v0x1d59330_0 .net *"_s0", 0 0, L_0x1eb91a0; 1 drivers +v0x1d59410_0 .net *"_s1", 0 0, L_0x1eb9300; 1 drivers +S_0x1d594f0 .scope generate, "or_slces[10]" "or_slces[10]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d59700 .param/l "i" 0 4 63, +C4<01010>; +L_0x1eb90b0/d .functor OR 1, L_0x1eb94f0, L_0x1eb9650, C4<0>, C4<0>; +L_0x1eb90b0 .delay 1 (30000,30000,30000) L_0x1eb90b0/d; +v0x1d597c0_0 .net *"_s0", 0 0, L_0x1eb94f0; 1 drivers +v0x1d598a0_0 .net *"_s1", 0 0, L_0x1eb9650; 1 drivers +S_0x1d59980 .scope generate, "or_slces[11]" "or_slces[11]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d59b90 .param/l "i" 0 4 63, +C4<01011>; +L_0x1eb93f0/d .functor OR 1, L_0x1eb9850, L_0x1eb99b0, C4<0>, C4<0>; +L_0x1eb93f0 .delay 1 (30000,30000,30000) L_0x1eb93f0/d; +v0x1d59c50_0 .net *"_s0", 0 0, L_0x1eb9850; 1 drivers +v0x1d59d30_0 .net *"_s1", 0 0, L_0x1eb99b0; 1 drivers +S_0x1d59e10 .scope generate, "or_slces[12]" "or_slces[12]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5a020 .param/l "i" 0 4 63, +C4<01100>; +L_0x1eb9740/d .functor OR 1, L_0x1eb9b70, L_0x1eb9cd0, C4<0>, C4<0>; +L_0x1eb9740 .delay 1 (30000,30000,30000) L_0x1eb9740/d; +v0x1d5a0e0_0 .net *"_s0", 0 0, L_0x1eb9b70; 1 drivers +v0x1d5a1c0_0 .net *"_s1", 0 0, L_0x1eb9cd0; 1 drivers +S_0x1d5a2a0 .scope generate, "or_slces[13]" "or_slces[13]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5a4b0 .param/l "i" 0 4 63, +C4<01101>; +L_0x1eb9aa0/d .functor OR 1, L_0x1eb9ea0, L_0x1eb84c0, C4<0>, C4<0>; +L_0x1eb9aa0 .delay 1 (30000,30000,30000) L_0x1eb9aa0/d; +v0x1d5a570_0 .net *"_s0", 0 0, L_0x1eb9ea0; 1 drivers +v0x1d5a650_0 .net *"_s1", 0 0, L_0x1eb84c0; 1 drivers +S_0x1d5a730 .scope generate, "or_slces[14]" "or_slces[14]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5a940 .param/l "i" 0 4 63, +C4<01110>; +L_0x1eb9dc0/d .functor OR 1, L_0x1eba420, L_0x1eba580, C4<0>, C4<0>; +L_0x1eb9dc0 .delay 1 (30000,30000,30000) L_0x1eb9dc0/d; +v0x1d5aa00_0 .net *"_s0", 0 0, L_0x1eba420; 1 drivers +v0x1d5aae0_0 .net *"_s1", 0 0, L_0x1eba580; 1 drivers +S_0x1d5abc0 .scope generate, "or_slces[15]" "or_slces[15]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5add0 .param/l "i" 0 4 63, +C4<01111>; +L_0x1eba670/d .functor OR 1, L_0x1eba730, L_0x1eba890, C4<0>, C4<0>; +L_0x1eba670 .delay 1 (30000,30000,30000) L_0x1eba670/d; +v0x1d5ae90_0 .net *"_s0", 0 0, L_0x1eba730; 1 drivers +v0x1d5af70_0 .net *"_s1", 0 0, L_0x1eba890; 1 drivers +S_0x1d5b050 .scope generate, "or_slces[16]" "or_slces[16]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d58da0 .param/l "i" 0 4 63, +C4<010000>; +L_0x1eba980/d .functor OR 1, L_0x1ebaa40, L_0x1ebaba0, C4<0>, C4<0>; +L_0x1eba980 .delay 1 (30000,30000,30000) L_0x1eba980/d; +v0x1d5b3c0_0 .net *"_s0", 0 0, L_0x1ebaa40; 1 drivers +v0x1d5b480_0 .net *"_s1", 0 0, L_0x1ebaba0; 1 drivers +S_0x1d5b560 .scope generate, "or_slces[17]" "or_slces[17]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5b770 .param/l "i" 0 4 63, +C4<010001>; +L_0x1eb8670/d .functor OR 1, L_0x1ebadb0, L_0x1ebaea0, C4<0>, C4<0>; +L_0x1eb8670 .delay 1 (30000,30000,30000) L_0x1eb8670/d; +v0x1d5b830_0 .net *"_s0", 0 0, L_0x1ebadb0; 1 drivers +v0x1d5b910_0 .net *"_s1", 0 0, L_0x1ebaea0; 1 drivers +S_0x1d5b9f0 .scope generate, "or_slces[18]" "or_slces[18]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5bc00 .param/l "i" 0 4 63, +C4<010010>; +L_0x1ebac90/d .functor OR 1, L_0x1ebb0c0, L_0x1ebb1b0, C4<0>, C4<0>; +L_0x1ebac90 .delay 1 (30000,30000,30000) L_0x1ebac90/d; +v0x1d5bcc0_0 .net *"_s0", 0 0, L_0x1ebb0c0; 1 drivers +v0x1d5bda0_0 .net *"_s1", 0 0, L_0x1ebb1b0; 1 drivers +S_0x1d5be80 .scope generate, "or_slces[19]" "or_slces[19]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5c090 .param/l "i" 0 4 63, +C4<010011>; +L_0x1ebaf90/d .functor OR 1, L_0x1ebb3e0, L_0x1ebb4d0, C4<0>, C4<0>; +L_0x1ebaf90 .delay 1 (30000,30000,30000) L_0x1ebaf90/d; +v0x1d5c150_0 .net *"_s0", 0 0, L_0x1ebb3e0; 1 drivers +v0x1d5c230_0 .net *"_s1", 0 0, L_0x1ebb4d0; 1 drivers +S_0x1d5c310 .scope generate, "or_slces[20]" "or_slces[20]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5c520 .param/l "i" 0 4 63, +C4<010100>; +L_0x1ebb2a0/d .functor OR 1, L_0x1ebb710, L_0x1ebb800, C4<0>, C4<0>; +L_0x1ebb2a0 .delay 1 (30000,30000,30000) L_0x1ebb2a0/d; +v0x1d5c5e0_0 .net *"_s0", 0 0, L_0x1ebb710; 1 drivers +v0x1d5c6c0_0 .net *"_s1", 0 0, L_0x1ebb800; 1 drivers +S_0x1d5c7a0 .scope generate, "or_slces[21]" "or_slces[21]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5c9b0 .param/l "i" 0 4 63, +C4<010101>; +L_0x1ebb5c0/d .functor OR 1, L_0x1ebba50, L_0x1ebbb40, C4<0>, C4<0>; +L_0x1ebb5c0 .delay 1 (30000,30000,30000) L_0x1ebb5c0/d; +v0x1d5ca70_0 .net *"_s0", 0 0, L_0x1ebba50; 1 drivers +v0x1d5cb50_0 .net *"_s1", 0 0, L_0x1ebbb40; 1 drivers +S_0x1d5cc30 .scope generate, "or_slces[22]" "or_slces[22]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5ce40 .param/l "i" 0 4 63, +C4<010110>; +L_0x1ebb8f0/d .functor OR 1, L_0x1ebbda0, L_0x1ebbe40, C4<0>, C4<0>; +L_0x1ebb8f0 .delay 1 (30000,30000,30000) L_0x1ebb8f0/d; +v0x1d5cf00_0 .net *"_s0", 0 0, L_0x1ebbda0; 1 drivers +v0x1d5cfe0_0 .net *"_s1", 0 0, L_0x1ebbe40; 1 drivers +S_0x1d5d0c0 .scope generate, "or_slces[23]" "or_slces[23]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5d2d0 .param/l "i" 0 4 63, +C4<010111>; +L_0x1ebbc30/d .functor OR 1, L_0x1ebc0b0, L_0x1ebc150, C4<0>, C4<0>; +L_0x1ebbc30 .delay 1 (30000,30000,30000) L_0x1ebbc30/d; +v0x1d5d390_0 .net *"_s0", 0 0, L_0x1ebc0b0; 1 drivers +v0x1d5d470_0 .net *"_s1", 0 0, L_0x1ebc150; 1 drivers +S_0x1d5d550 .scope generate, "or_slces[24]" "or_slces[24]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5d760 .param/l "i" 0 4 63, +C4<011000>; +L_0x1ebbf30/d .functor OR 1, L_0x1ebc3d0, L_0x1ebc470, C4<0>, C4<0>; +L_0x1ebbf30 .delay 1 (30000,30000,30000) L_0x1ebbf30/d; +v0x1d5d820_0 .net *"_s0", 0 0, L_0x1ebc3d0; 1 drivers +v0x1d5d900_0 .net *"_s1", 0 0, L_0x1ebc470; 1 drivers +S_0x1d5d9e0 .scope generate, "or_slces[25]" "or_slces[25]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5dbf0 .param/l "i" 0 4 63, +C4<011001>; +L_0x1ebc240/d .functor OR 1, L_0x1ebc700, L_0x1ebc7a0, C4<0>, C4<0>; +L_0x1ebc240 .delay 1 (30000,30000,30000) L_0x1ebc240/d; +v0x1d5dcb0_0 .net *"_s0", 0 0, L_0x1ebc700; 1 drivers +v0x1d5dd90_0 .net *"_s1", 0 0, L_0x1ebc7a0; 1 drivers +S_0x1d5de70 .scope generate, "or_slces[26]" "or_slces[26]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5e080 .param/l "i" 0 4 63, +C4<011010>; +L_0x1ebc560/d .functor OR 1, L_0x1ebca40, L_0x1ebcae0, C4<0>, C4<0>; +L_0x1ebc560 .delay 1 (30000,30000,30000) L_0x1ebc560/d; +v0x1d5e140_0 .net *"_s0", 0 0, L_0x1ebca40; 1 drivers +v0x1d5e220_0 .net *"_s1", 0 0, L_0x1ebcae0; 1 drivers +S_0x1d5e300 .scope generate, "or_slces[27]" "or_slces[27]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5e510 .param/l "i" 0 4 63, +C4<011011>; +L_0x1ebc890/d .functor OR 1, L_0x1ebc9a0, L_0x1ebcde0, C4<0>, C4<0>; +L_0x1ebc890 .delay 1 (30000,30000,30000) L_0x1ebc890/d; +v0x1d5e5d0_0 .net *"_s0", 0 0, L_0x1ebc9a0; 1 drivers +v0x1d5e6b0_0 .net *"_s1", 0 0, L_0x1ebcde0; 1 drivers +S_0x1d5e790 .scope generate, "or_slces[28]" "or_slces[28]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5e9a0 .param/l "i" 0 4 63, +C4<011100>; +L_0x1ebcbd0/d .functor OR 1, L_0x1ebcce0, L_0x1ebd0f0, C4<0>, C4<0>; +L_0x1ebcbd0 .delay 1 (30000,30000,30000) L_0x1ebcbd0/d; +v0x1d5ea60_0 .net *"_s0", 0 0, L_0x1ebcce0; 1 drivers +v0x1d5eb40_0 .net *"_s1", 0 0, L_0x1ebd0f0; 1 drivers +S_0x1d5ec20 .scope generate, "or_slces[29]" "or_slces[29]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5ee30 .param/l "i" 0 4 63, +C4<011101>; +L_0x1ebced0/d .functor OR 1, L_0x1ebcf90, L_0x1eba000, C4<0>, C4<0>; +L_0x1ebced0 .delay 1 (30000,30000,30000) L_0x1ebced0/d; +v0x1d5eef0_0 .net *"_s0", 0 0, L_0x1ebcf90; 1 drivers +v0x1d5efd0_0 .net *"_s1", 0 0, L_0x1eba000; 1 drivers +S_0x1d5f0b0 .scope generate, "or_slces[30]" "or_slces[30]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5f2c0 .param/l "i" 0 4 63, +C4<011110>; +L_0x1eba2e0/d .functor OR 1, L_0x1ebd1e0, L_0x1ebdc30, C4<0>, C4<0>; +L_0x1eba2e0 .delay 1 (30000,30000,30000) L_0x1eba2e0/d; +v0x1d5f380_0 .net *"_s0", 0 0, L_0x1ebd1e0; 1 drivers +v0x1d5f460_0 .net *"_s1", 0 0, L_0x1ebdc30; 1 drivers +S_0x1d5f540 .scope generate, "or_slces[31]" "or_slces[31]" 4 63, 4 63 0, S_0x1d56430; + .timescale -9 -12; +P_0x1d5f750 .param/l "i" 0 4 63, +C4<011111>; +L_0x1ebe820/d .functor OR 1, L_0x1ebe930, L_0x1ebdcd0, C4<0>, C4<0>; +L_0x1ebe820 .delay 1 (30000,30000,30000) L_0x1ebe820/d; +v0x1d5f810_0 .net *"_s0", 0 0, L_0x1ebe930; 1 drivers +v0x1d5f8f0_0 .net *"_s1", 0 0, L_0x1ebdcd0; 1 drivers +S_0x1d61b70 .scope module, "zeroout" "and32" 3 55, 4 44 0, S_0x1a570b0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 32 "in" +L_0x1eb5590/d .functor AND 1, L_0x1eb5600, L_0x1eb57b0, C4<1>, C4<1>; +L_0x1eb5590 .delay 1 (30000,30000,30000) L_0x1eb5590/d; +v0x1d6ac30_0 .net *"_s10", 0 0, L_0x1eb5600; 1 drivers +v0x1d6ad10_0 .net *"_s12", 0 0, L_0x1eb57b0; 1 drivers +v0x1d6adf0_0 .net "ands", 1 0, L_0x1eb5320; 1 drivers +v0x1d6aeb0_0 .net "in", 31 0, L_0x1e026d0; alias, 1 drivers +v0x1d6af90_0 .net "out", 0 0, L_0x1eb5590; alias, 1 drivers +L_0x1eb12b0 .part L_0x1e026d0, 0, 16; +L_0x1eb5320 .concat8 [ 1 1 0 0], L_0x1eb0f50, L_0x1eb4fc0; +L_0x1eb5460 .part L_0x1e026d0, 16, 16; +L_0x1eb5600 .part L_0x1eb5320, 0, 1; +L_0x1eb57b0 .part L_0x1eb5320, 1, 1; +S_0x1d61d30 .scope module, "and_1" "and16" 4 46, 4 37 0, S_0x1d61b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 16 "in" +L_0x1eb0f50/d .functor AND 1, L_0x1eb1010, L_0x1eb11c0, C4<1>, C4<1>; +L_0x1eb0f50 .delay 1 (30000,30000,30000) L_0x1eb0f50/d; +v0x1d66000_0 .net *"_s10", 0 0, L_0x1eb1010; 1 drivers +v0x1d660e0_0 .net *"_s12", 0 0, L_0x1eb11c0; 1 drivers +v0x1d661c0_0 .net "ands", 1 0, L_0x1eb0d20; 1 drivers +v0x1d66280_0 .net "in", 15 0, L_0x1eb12b0; 1 drivers +v0x1d66360_0 .net "out", 0 0, L_0x1eb0f50; 1 drivers +L_0x1eaefb0 .part L_0x1eb12b0, 0, 8; +L_0x1eb0d20 .concat8 [ 1 1 0 0], L_0x1eaec50, L_0x1eb09c0; +L_0x1eb0e60 .part L_0x1eb12b0, 8, 8; +L_0x1eb1010 .part L_0x1eb0d20, 0, 1; +L_0x1eb11c0 .part L_0x1eb0d20, 1, 1; +S_0x1d61f80 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x1d61d30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1eaec50/d .functor AND 1, L_0x1eaed10, L_0x1eaeec0, C4<1>, C4<1>; +L_0x1eaec50 .delay 1 (30000,30000,30000) L_0x1eaec50/d; +v0x1d63b60_0 .net *"_s10", 0 0, L_0x1eaed10; 1 drivers +v0x1d63c40_0 .net *"_s12", 0 0, L_0x1eaeec0; 1 drivers +v0x1d63d20_0 .net "ands", 1 0, L_0x1eaea20; 1 drivers +v0x1d63de0_0 .net "in", 7 0, L_0x1eaefb0; 1 drivers +v0x1d63ec0_0 .net "out", 0 0, L_0x1eaec50; 1 drivers +L_0x1eae0d0 .part L_0x1eaefb0, 0, 4; +L_0x1eaea20 .concat8 [ 1 1 0 0], L_0x1eadf20, L_0x1eae710; +L_0x1eaeb60 .part L_0x1eaefb0, 4, 4; +L_0x1eaed10 .part L_0x1eaea20, 0, 1; +L_0x1eaeec0 .part L_0x1eaea20, 1, 1; +S_0x1d621d0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d61f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eac7b0/d .functor AND 1, L_0x1eadb00, L_0x1eadba0, C4<1>, C4<1>; +L_0x1eac7b0 .delay 1 (30000,30000,30000) L_0x1eac7b0/d; +L_0x1eadce0/d .functor AND 1, L_0x1eadd50, L_0x1eaddf0, C4<1>, C4<1>; +L_0x1eadce0 .delay 1 (30000,30000,30000) L_0x1eadce0/d; +L_0x1eadf20/d .functor AND 1, L_0x1eadf90, L_0x1eae030, C4<1>, C4<1>; +L_0x1eadf20 .delay 1 (30000,30000,30000) L_0x1eadf20/d; +v0x1d62420_0 .net *"_s0", 0 0, L_0x1eac7b0; 1 drivers +v0x1d62520_0 .net *"_s10", 0 0, L_0x1eadd50; 1 drivers +v0x1d62600_0 .net *"_s12", 0 0, L_0x1eaddf0; 1 drivers +v0x1d626c0_0 .net *"_s14", 0 0, L_0x1eadf90; 1 drivers +v0x1d627a0_0 .net *"_s16", 0 0, L_0x1eae030; 1 drivers +v0x1d628d0_0 .net *"_s3", 0 0, L_0x1eadb00; 1 drivers +v0x1d629b0_0 .net *"_s5", 0 0, L_0x1eadba0; 1 drivers +v0x1d62a90_0 .net *"_s6", 0 0, L_0x1eadce0; 1 drivers +v0x1d62b70_0 .net "ands", 1 0, L_0x1eadc40; 1 drivers +v0x1d62ce0_0 .net "in", 3 0, L_0x1eae0d0; 1 drivers +v0x1d62dc0_0 .net "out", 0 0, L_0x1eadf20; 1 drivers +L_0x1eadb00 .part L_0x1eae0d0, 0, 1; +L_0x1eadba0 .part L_0x1eae0d0, 1, 1; +L_0x1eadc40 .concat8 [ 1 1 0 0], L_0x1eac7b0, L_0x1eadce0; +L_0x1eadd50 .part L_0x1eae0d0, 2, 1; +L_0x1eaddf0 .part L_0x1eae0d0, 3, 1; +L_0x1eadf90 .part L_0x1eadc40, 0, 1; +L_0x1eae030 .part L_0x1eadc40, 1, 1; +S_0x1d62ee0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d61f80; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eae170/d .functor AND 1, L_0x1eae1e0, L_0x1eae280, C4<1>, C4<1>; +L_0x1eae170 .delay 1 (30000,30000,30000) L_0x1eae170/d; +L_0x1eae3c0/d .functor AND 1, L_0x1eae430, L_0x1eae590, C4<1>, C4<1>; +L_0x1eae3c0 .delay 1 (30000,30000,30000) L_0x1eae3c0/d; +L_0x1eae710/d .functor AND 1, L_0x1eae780, L_0x1eae930, C4<1>, C4<1>; +L_0x1eae710 .delay 1 (30000,30000,30000) L_0x1eae710/d; +v0x1d630a0_0 .net *"_s0", 0 0, L_0x1eae170; 1 drivers +v0x1d631a0_0 .net *"_s10", 0 0, L_0x1eae430; 1 drivers +v0x1d63280_0 .net *"_s12", 0 0, L_0x1eae590; 1 drivers +v0x1d63340_0 .net *"_s14", 0 0, L_0x1eae780; 1 drivers +v0x1d63420_0 .net *"_s16", 0 0, L_0x1eae930; 1 drivers +v0x1d63550_0 .net *"_s3", 0 0, L_0x1eae1e0; 1 drivers +v0x1d63630_0 .net *"_s5", 0 0, L_0x1eae280; 1 drivers +v0x1d63710_0 .net *"_s6", 0 0, L_0x1eae3c0; 1 drivers +v0x1d637f0_0 .net "ands", 1 0, L_0x1eae320; 1 drivers +v0x1d63960_0 .net "in", 3 0, L_0x1eaeb60; 1 drivers +v0x1d63a40_0 .net "out", 0 0, L_0x1eae710; 1 drivers +L_0x1eae1e0 .part L_0x1eaeb60, 0, 1; +L_0x1eae280 .part L_0x1eaeb60, 1, 1; +L_0x1eae320 .concat8 [ 1 1 0 0], L_0x1eae170, L_0x1eae3c0; +L_0x1eae430 .part L_0x1eaeb60, 2, 1; +L_0x1eae590 .part L_0x1eaeb60, 3, 1; +L_0x1eae780 .part L_0x1eae320, 0, 1; +L_0x1eae930 .part L_0x1eae320, 1, 1; +S_0x1d63fe0 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x1d61d30; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1eb09c0/d .functor AND 1, L_0x1eb0a80, L_0x1eb0c30, C4<1>, C4<1>; +L_0x1eb09c0 .delay 1 (30000,30000,30000) L_0x1eb09c0/d; +v0x1d65b80_0 .net *"_s10", 0 0, L_0x1eb0a80; 1 drivers +v0x1d65c60_0 .net *"_s12", 0 0, L_0x1eb0c30; 1 drivers +v0x1d65d40_0 .net "ands", 1 0, L_0x1eb0790; 1 drivers +v0x1d65e00_0 .net "in", 7 0, L_0x1eb0e60; 1 drivers +v0x1d65ee0_0 .net "out", 0 0, L_0x1eb09c0; 1 drivers +L_0x1eafba0 .part L_0x1eb0e60, 0, 4; +L_0x1eb0790 .concat8 [ 1 1 0 0], L_0x1eaf890, L_0x1eb0480; +L_0x1eb08d0 .part L_0x1eb0e60, 4, 4; +L_0x1eb0a80 .part L_0x1eb0790, 0, 1; +L_0x1eb0c30 .part L_0x1eb0790, 1, 1; +S_0x1d641f0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d63fe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eaf050/d .functor AND 1, L_0x1eaf110, L_0x1eaf270, C4<1>, C4<1>; +L_0x1eaf050 .delay 1 (30000,30000,30000) L_0x1eaf050/d; +L_0x1eaf4a0/d .functor AND 1, L_0x1eaf5b0, L_0x1eaf710, C4<1>, C4<1>; +L_0x1eaf4a0 .delay 1 (30000,30000,30000) L_0x1eaf4a0/d; +L_0x1eaf890/d .functor AND 1, L_0x1eaf900, L_0x1eafab0, C4<1>, C4<1>; +L_0x1eaf890 .delay 1 (30000,30000,30000) L_0x1eaf890/d; +v0x1d64440_0 .net *"_s0", 0 0, L_0x1eaf050; 1 drivers +v0x1d64540_0 .net *"_s10", 0 0, L_0x1eaf5b0; 1 drivers +v0x1d64620_0 .net *"_s12", 0 0, L_0x1eaf710; 1 drivers +v0x1d646e0_0 .net *"_s14", 0 0, L_0x1eaf900; 1 drivers +v0x1d647c0_0 .net *"_s16", 0 0, L_0x1eafab0; 1 drivers +v0x1d648f0_0 .net *"_s3", 0 0, L_0x1eaf110; 1 drivers +v0x1d649d0_0 .net *"_s5", 0 0, L_0x1eaf270; 1 drivers +v0x1d64ab0_0 .net *"_s6", 0 0, L_0x1eaf4a0; 1 drivers +v0x1d64b90_0 .net "ands", 1 0, L_0x1eaf3b0; 1 drivers +v0x1d64d00_0 .net "in", 3 0, L_0x1eafba0; 1 drivers +v0x1d64de0_0 .net "out", 0 0, L_0x1eaf890; 1 drivers +L_0x1eaf110 .part L_0x1eafba0, 0, 1; +L_0x1eaf270 .part L_0x1eafba0, 1, 1; +L_0x1eaf3b0 .concat8 [ 1 1 0 0], L_0x1eaf050, L_0x1eaf4a0; +L_0x1eaf5b0 .part L_0x1eafba0, 2, 1; +L_0x1eaf710 .part L_0x1eafba0, 3, 1; +L_0x1eaf900 .part L_0x1eaf3b0, 0, 1; +L_0x1eafab0 .part L_0x1eaf3b0, 1, 1; +S_0x1d64f00 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d63fe0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eafc40/d .functor AND 1, L_0x1eafd00, L_0x1eafe60, C4<1>, C4<1>; +L_0x1eafc40 .delay 1 (30000,30000,30000) L_0x1eafc40/d; +L_0x1eb0090/d .functor AND 1, L_0x1eb01a0, L_0x1eb0300, C4<1>, C4<1>; +L_0x1eb0090 .delay 1 (30000,30000,30000) L_0x1eb0090/d; +L_0x1eb0480/d .functor AND 1, L_0x1eb04f0, L_0x1eb06a0, C4<1>, C4<1>; +L_0x1eb0480 .delay 1 (30000,30000,30000) L_0x1eb0480/d; +v0x1d650c0_0 .net *"_s0", 0 0, L_0x1eafc40; 1 drivers +v0x1d651c0_0 .net *"_s10", 0 0, L_0x1eb01a0; 1 drivers +v0x1d652a0_0 .net *"_s12", 0 0, L_0x1eb0300; 1 drivers +v0x1d65360_0 .net *"_s14", 0 0, L_0x1eb04f0; 1 drivers +v0x1d65440_0 .net *"_s16", 0 0, L_0x1eb06a0; 1 drivers +v0x1d65570_0 .net *"_s3", 0 0, L_0x1eafd00; 1 drivers +v0x1d65650_0 .net *"_s5", 0 0, L_0x1eafe60; 1 drivers +v0x1d65730_0 .net *"_s6", 0 0, L_0x1eb0090; 1 drivers +v0x1d65810_0 .net "ands", 1 0, L_0x1eaffa0; 1 drivers +v0x1d65980_0 .net "in", 3 0, L_0x1eb08d0; 1 drivers +v0x1d65a60_0 .net "out", 0 0, L_0x1eb0480; 1 drivers +L_0x1eafd00 .part L_0x1eb08d0, 0, 1; +L_0x1eafe60 .part L_0x1eb08d0, 1, 1; +L_0x1eaffa0 .concat8 [ 1 1 0 0], L_0x1eafc40, L_0x1eb0090; +L_0x1eb01a0 .part L_0x1eb08d0, 2, 1; +L_0x1eb0300 .part L_0x1eb08d0, 3, 1; +L_0x1eb04f0 .part L_0x1eaffa0, 0, 1; +L_0x1eb06a0 .part L_0x1eaffa0, 1, 1; +S_0x1d664d0 .scope module, "and_2" "and16" 4 47, 4 37 0, S_0x1d61b70; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 16 "in" +L_0x1eb4fc0/d .functor AND 1, L_0x1eb5080, L_0x1eb5230, C4<1>, C4<1>; +L_0x1eb4fc0 .delay 1 (30000,30000,30000) L_0x1eb4fc0/d; +v0x1d6a760_0 .net *"_s10", 0 0, L_0x1eb5080; 1 drivers +v0x1d6a840_0 .net *"_s12", 0 0, L_0x1eb5230; 1 drivers +v0x1d6a920_0 .net "ands", 1 0, L_0x1eb4d90; 1 drivers +v0x1d6a9e0_0 .net "in", 15 0, L_0x1eb5460; 1 drivers +v0x1d6aac0_0 .net "out", 0 0, L_0x1eb4fc0; 1 drivers +L_0x1eb3020 .part L_0x1eb5460, 0, 8; +L_0x1eb4d90 .concat8 [ 1 1 0 0], L_0x1eb2cc0, L_0x1eb4a30; +L_0x1eb4ed0 .part L_0x1eb5460, 8, 8; +L_0x1eb5080 .part L_0x1eb4d90, 0, 1; +L_0x1eb5230 .part L_0x1eb4d90, 1, 1; +S_0x1d666e0 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x1d664d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1eb2cc0/d .functor AND 1, L_0x1eb2d80, L_0x1eb2f30, C4<1>, C4<1>; +L_0x1eb2cc0 .delay 1 (30000,30000,30000) L_0x1eb2cc0/d; +v0x1d682c0_0 .net *"_s10", 0 0, L_0x1eb2d80; 1 drivers +v0x1d683a0_0 .net *"_s12", 0 0, L_0x1eb2f30; 1 drivers +v0x1d68480_0 .net "ands", 1 0, L_0x1eb2a90; 1 drivers +v0x1d68540_0 .net "in", 7 0, L_0x1eb3020; 1 drivers +v0x1d68620_0 .net "out", 0 0, L_0x1eb2cc0; 1 drivers +L_0x1eb1ea0 .part L_0x1eb3020, 0, 4; +L_0x1eb2a90 .concat8 [ 1 1 0 0], L_0x1eb1b90, L_0x1eb2780; +L_0x1eb2bd0 .part L_0x1eb3020, 4, 4; +L_0x1eb2d80 .part L_0x1eb2a90, 0, 1; +L_0x1eb2f30 .part L_0x1eb2a90, 1, 1; +S_0x1d66930 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d666e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eb1350/d .functor AND 1, L_0x1eb1410, L_0x1eb1570, C4<1>, C4<1>; +L_0x1eb1350 .delay 1 (30000,30000,30000) L_0x1eb1350/d; +L_0x1eb17a0/d .functor AND 1, L_0x1eb18b0, L_0x1eb1a10, C4<1>, C4<1>; +L_0x1eb17a0 .delay 1 (30000,30000,30000) L_0x1eb17a0/d; +L_0x1eb1b90/d .functor AND 1, L_0x1eb1c00, L_0x1eb1db0, C4<1>, C4<1>; +L_0x1eb1b90 .delay 1 (30000,30000,30000) L_0x1eb1b90/d; +v0x1d66b80_0 .net *"_s0", 0 0, L_0x1eb1350; 1 drivers +v0x1d66c80_0 .net *"_s10", 0 0, L_0x1eb18b0; 1 drivers +v0x1d66d60_0 .net *"_s12", 0 0, L_0x1eb1a10; 1 drivers +v0x1d66e20_0 .net *"_s14", 0 0, L_0x1eb1c00; 1 drivers +v0x1d66f00_0 .net *"_s16", 0 0, L_0x1eb1db0; 1 drivers +v0x1d67030_0 .net *"_s3", 0 0, L_0x1eb1410; 1 drivers +v0x1d67110_0 .net *"_s5", 0 0, L_0x1eb1570; 1 drivers +v0x1d671f0_0 .net *"_s6", 0 0, L_0x1eb17a0; 1 drivers +v0x1d672d0_0 .net "ands", 1 0, L_0x1eb16b0; 1 drivers +v0x1d67440_0 .net "in", 3 0, L_0x1eb1ea0; 1 drivers +v0x1d67520_0 .net "out", 0 0, L_0x1eb1b90; 1 drivers +L_0x1eb1410 .part L_0x1eb1ea0, 0, 1; +L_0x1eb1570 .part L_0x1eb1ea0, 1, 1; +L_0x1eb16b0 .concat8 [ 1 1 0 0], L_0x1eb1350, L_0x1eb17a0; +L_0x1eb18b0 .part L_0x1eb1ea0, 2, 1; +L_0x1eb1a10 .part L_0x1eb1ea0, 3, 1; +L_0x1eb1c00 .part L_0x1eb16b0, 0, 1; +L_0x1eb1db0 .part L_0x1eb16b0, 1, 1; +S_0x1d67640 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d666e0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eb1f40/d .functor AND 1, L_0x1eb2000, L_0x1eb2160, C4<1>, C4<1>; +L_0x1eb1f40 .delay 1 (30000,30000,30000) L_0x1eb1f40/d; +L_0x1eb2390/d .functor AND 1, L_0x1eb24a0, L_0x1eb2600, C4<1>, C4<1>; +L_0x1eb2390 .delay 1 (30000,30000,30000) L_0x1eb2390/d; +L_0x1eb2780/d .functor AND 1, L_0x1eb27f0, L_0x1eb29a0, C4<1>, C4<1>; +L_0x1eb2780 .delay 1 (30000,30000,30000) L_0x1eb2780/d; +v0x1d67800_0 .net *"_s0", 0 0, L_0x1eb1f40; 1 drivers +v0x1d67900_0 .net *"_s10", 0 0, L_0x1eb24a0; 1 drivers +v0x1d679e0_0 .net *"_s12", 0 0, L_0x1eb2600; 1 drivers +v0x1d67aa0_0 .net *"_s14", 0 0, L_0x1eb27f0; 1 drivers +v0x1d67b80_0 .net *"_s16", 0 0, L_0x1eb29a0; 1 drivers +v0x1d67cb0_0 .net *"_s3", 0 0, L_0x1eb2000; 1 drivers +v0x1d67d90_0 .net *"_s5", 0 0, L_0x1eb2160; 1 drivers +v0x1d67e70_0 .net *"_s6", 0 0, L_0x1eb2390; 1 drivers +v0x1d67f50_0 .net "ands", 1 0, L_0x1eb22a0; 1 drivers +v0x1d680c0_0 .net "in", 3 0, L_0x1eb2bd0; 1 drivers +v0x1d681a0_0 .net "out", 0 0, L_0x1eb2780; 1 drivers +L_0x1eb2000 .part L_0x1eb2bd0, 0, 1; +L_0x1eb2160 .part L_0x1eb2bd0, 1, 1; +L_0x1eb22a0 .concat8 [ 1 1 0 0], L_0x1eb1f40, L_0x1eb2390; +L_0x1eb24a0 .part L_0x1eb2bd0, 2, 1; +L_0x1eb2600 .part L_0x1eb2bd0, 3, 1; +L_0x1eb27f0 .part L_0x1eb22a0, 0, 1; +L_0x1eb29a0 .part L_0x1eb22a0, 1, 1; +S_0x1d68740 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x1d664d0; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 8 "in" +L_0x1eb4a30/d .functor AND 1, L_0x1eb4af0, L_0x1eb4ca0, C4<1>, C4<1>; +L_0x1eb4a30 .delay 1 (30000,30000,30000) L_0x1eb4a30/d; +v0x1d6a2e0_0 .net *"_s10", 0 0, L_0x1eb4af0; 1 drivers +v0x1d6a3c0_0 .net *"_s12", 0 0, L_0x1eb4ca0; 1 drivers +v0x1d6a4a0_0 .net "ands", 1 0, L_0x1eb4800; 1 drivers +v0x1d6a560_0 .net "in", 7 0, L_0x1eb4ed0; 1 drivers +v0x1d6a640_0 .net "out", 0 0, L_0x1eb4a30; 1 drivers +L_0x1eb3c10 .part L_0x1eb4ed0, 0, 4; +L_0x1eb4800 .concat8 [ 1 1 0 0], L_0x1eb3900, L_0x1eb44f0; +L_0x1eb4940 .part L_0x1eb4ed0, 4, 4; +L_0x1eb4af0 .part L_0x1eb4800, 0, 1; +L_0x1eb4ca0 .part L_0x1eb4800, 1, 1; +S_0x1d68950 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d68740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eb30c0/d .functor AND 1, L_0x1eb3180, L_0x1eb32e0, C4<1>, C4<1>; +L_0x1eb30c0 .delay 1 (30000,30000,30000) L_0x1eb30c0/d; +L_0x1eb3510/d .functor AND 1, L_0x1eb3620, L_0x1eb3780, C4<1>, C4<1>; +L_0x1eb3510 .delay 1 (30000,30000,30000) L_0x1eb3510/d; +L_0x1eb3900/d .functor AND 1, L_0x1eb3970, L_0x1eb3b20, C4<1>, C4<1>; +L_0x1eb3900 .delay 1 (30000,30000,30000) L_0x1eb3900/d; +v0x1d68ba0_0 .net *"_s0", 0 0, L_0x1eb30c0; 1 drivers +v0x1d68ca0_0 .net *"_s10", 0 0, L_0x1eb3620; 1 drivers +v0x1d68d80_0 .net *"_s12", 0 0, L_0x1eb3780; 1 drivers +v0x1d68e40_0 .net *"_s14", 0 0, L_0x1eb3970; 1 drivers +v0x1d68f20_0 .net *"_s16", 0 0, L_0x1eb3b20; 1 drivers +v0x1d69050_0 .net *"_s3", 0 0, L_0x1eb3180; 1 drivers +v0x1d69130_0 .net *"_s5", 0 0, L_0x1eb32e0; 1 drivers +v0x1d69210_0 .net *"_s6", 0 0, L_0x1eb3510; 1 drivers +v0x1d692f0_0 .net "ands", 1 0, L_0x1eb3420; 1 drivers +v0x1d69460_0 .net "in", 3 0, L_0x1eb3c10; 1 drivers +v0x1d69540_0 .net "out", 0 0, L_0x1eb3900; 1 drivers +L_0x1eb3180 .part L_0x1eb3c10, 0, 1; +L_0x1eb32e0 .part L_0x1eb3c10, 1, 1; +L_0x1eb3420 .concat8 [ 1 1 0 0], L_0x1eb30c0, L_0x1eb3510; +L_0x1eb3620 .part L_0x1eb3c10, 2, 1; +L_0x1eb3780 .part L_0x1eb3c10, 3, 1; +L_0x1eb3970 .part L_0x1eb3420, 0, 1; +L_0x1eb3b20 .part L_0x1eb3420, 1, 1; +S_0x1d69660 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d68740; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 4 "in" +L_0x1eb3cb0/d .functor AND 1, L_0x1eb3d70, L_0x1eb3ed0, C4<1>, C4<1>; +L_0x1eb3cb0 .delay 1 (30000,30000,30000) L_0x1eb3cb0/d; +L_0x1eb4100/d .functor AND 1, L_0x1eb4210, L_0x1eb4370, C4<1>, C4<1>; +L_0x1eb4100 .delay 1 (30000,30000,30000) L_0x1eb4100/d; +L_0x1eb44f0/d .functor AND 1, L_0x1eb4560, L_0x1eb4710, C4<1>, C4<1>; +L_0x1eb44f0 .delay 1 (30000,30000,30000) L_0x1eb44f0/d; +v0x1d69820_0 .net *"_s0", 0 0, L_0x1eb3cb0; 1 drivers +v0x1d69920_0 .net *"_s10", 0 0, L_0x1eb4210; 1 drivers +v0x1d69a00_0 .net *"_s12", 0 0, L_0x1eb4370; 1 drivers +v0x1d69ac0_0 .net *"_s14", 0 0, L_0x1eb4560; 1 drivers +v0x1d69ba0_0 .net *"_s16", 0 0, L_0x1eb4710; 1 drivers +v0x1d69cd0_0 .net *"_s3", 0 0, L_0x1eb3d70; 1 drivers +v0x1d69db0_0 .net *"_s5", 0 0, L_0x1eb3ed0; 1 drivers +v0x1d69e90_0 .net *"_s6", 0 0, L_0x1eb4100; 1 drivers +v0x1d69f70_0 .net "ands", 1 0, L_0x1eb4010; 1 drivers +v0x1d6a0e0_0 .net "in", 3 0, L_0x1eb4940; 1 drivers +v0x1d6a1c0_0 .net "out", 0 0, L_0x1eb44f0; 1 drivers +L_0x1eb3d70 .part L_0x1eb4940, 0, 1; +L_0x1eb3ed0 .part L_0x1eb4940, 1, 1; +L_0x1eb4010 .concat8 [ 1 1 0 0], L_0x1eb3cb0, L_0x1eb4100; +L_0x1eb4210 .part L_0x1eb4940, 2, 1; +L_0x1eb4370 .part L_0x1eb4940, 3, 1; +L_0x1eb4560 .part L_0x1eb4010, 0, 1; +L_0x1eb4710 .part L_0x1eb4010, 1, 1; + .scope S_0x1a570b0; +T_0 ; + %wait E_0x1b385b0; + %load/vec4 v0x1d6d9c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_0.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_0.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_0.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_0.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_0.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_0.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_0.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_0.7, 6; + %jmp T_0.8; +T_0.0 ; + %pushi/vec4 1, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.1 ; + %pushi/vec4 2, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.2 ; + %pushi/vec4 4, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.3 ; + %pushi/vec4 8, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.4 ; + %pushi/vec4 16, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.5 ; + %pushi/vec4 32, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.6 ; + %pushi/vec4 64, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.7 ; + %pushi/vec4 128, 0, 8; + %store/vec4 v0x1d6daa0_0, 0, 8; + %jmp T_0.8; +T_0.8 ; + %pop/vec4 1; + %jmp T_0; + .thread T_0, $push; + .scope S_0x17c4680; +T_1 ; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x1d6e8a0_0, 0, 3; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 19 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4294967293, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 22 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4294967293, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 25 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 28 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 3, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 31 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 3, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 34 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 3, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 37 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 3, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 40 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4294967293, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 43 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4294967293, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 46 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 4294967293, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 49 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x1d6e5c0_0, 0, 32; + %pushi/vec4 3, 0, 32; + %store/vec4 v0x1d6e6d0_0, 0, 32; + %delay 1410065408, 2; + %vpi_call 2 52 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %end; + .thread T_1; +# The file index is used to find the file name in the following table. +:file_names 5; + "N/A"; + ""; + "alu.t.v"; + "./alu.v"; + "./alu1.v"; diff --git a/alu.t.v b/alu.t.v new file mode 100644 index 0000000..409c4b5 --- /dev/null +++ b/alu.t.v @@ -0,0 +1,54 @@ +`timescale 1 ns / 1 ps +`include "alu.v" + +module testALU(); + reg signed[31:0] a; + reg signed[31:0] b; + reg[2:0] command; + wire carryout; + wire zero; + wire overflow; + wire signed[31:0] result; + + ALU dut(result, carryout, zero, overflow, a, b, command); + + initial begin + command = 3'd2; + a = -4; + b = -4; #10000000 + $display("%d %d %d", a, b, result); + a = -3; + b = -4; #10000000 + $display("%d %d %d", a, b, result); + a = -4; + b = -3; #10000000 + $display("%d %d %d", a, b, result); + a = 4; + b = 4; #10000000 + $display("%d %d %d", a, b, result); + a = 3; + b = 4; #10000000 + $display("%d %d %d", a, b, result); + a = 4; + b = 3; #10000000 + $display("%d %d %d", a, b, result); + a = 3; + b = 0; #10000000 + $display("%d %d %d", a, b, result); + a = 0; + b = 3; #10000000 + $display("%d %d %d", a, b, result); + a = -3; + b = 0; #10000000 + $display("%d %d %d", a, b, result); + a = 0; + b = -3; #10000000 + $display("%d %d %d", a, b, result); + a = 4; + b = -3; #10000000 + $display("%d %d %d", a, b, result); + a = -4; + b = 3; #10000000 + $display("%d %d %d", a, b, result); + end +endmodule diff --git a/alu.v b/alu.v index 880457c..eb4ec75 100644 --- a/alu.v +++ b/alu.v @@ -1,6 +1,5 @@ -`include alu1.v -module ALU -( +`include "alu1.v" +module ALU( output[31:0] result, output carryout, output zero, @@ -8,27 +7,63 @@ output overflow, input[31:0] operandA, input[31:0] operandB, input[2:0] command - ); +); + wire[32:0] carryinbus; + wire[31:0] zerobus; + wire[31:0] overrideBus; + wire[31:0] resultBus; + wire carryout; + wire mixedSigns; + wire sameSigns; + wire possibleOverflow; + wire sltPre; - initial begin - wire carryinbus [32:0]; - wire zerobus [31:0]; - - wire commandslice [7:0]; - assign commandslice=1<b, return 1 + // if a carryin[n+1] + // note that this will always be wrong if + // the signs of A and B are opposite. + `XNOR xnorGate(eq, a, b); + `AND ltAnd(lt, a, b_); + `AND and0(w0, eq, carryin); + `OR or1(out, w0, lt); +endmodule + `define ADDSig command[0] `define SUBSig command[1] `define XORSig command[2] @@ -108,20 +138,25 @@ module alu1( input[7:0] command ); wire[7:0] results; -wire[7:0] caryouts; +wire result; +wire[7:0] carryouts; wire A_, B_; `NOT an(A_, A); `NOT bn(B_, B); fullAdder adder(results[0], carryouts[0], A, B, carryin); fullAdder sub(results[1], carryouts[1], A, B_, carryin); -`XOR xor(results[2], A, B); -fullAdder slt(results[3], carryouts[3], A, B_, carryin); -`AND and(results[4], A, B); -`NAND nand(results[5], A, B); -`NOR nor(results[6], A, B); -`OR or(results[7], A, B); +`XOR xorGate(results[2], A, B); +//slt is odd. Only the first bit is ever set, but it depends +//on the lest bit. The actual result is handled later, +//in the full ALU +slt sltGate(carryouts[3], carryin, A, A_, B, B_); +`OR falseGate(results[3], 0, 0); +`AND andGate(results[4], A, B); +`NAND nandGate(results[5], A, B); +`NOR norGate(results[6], A, B); +`OR orGate(results[7], A, B); unaryMultiplexor resMux(result, results, command); unaryMultiplexor cMux(carryout, carryouts, command); - +`NOT(zero, result); endmodule From 0f14f99c40fc8ed3ce3e8d8de9da392f3a216b89 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Tue, 10 Oct 2017 11:14:24 -0400 Subject: [PATCH 06/26] added Makefile --- Makefile | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Makefile diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..447df6d --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +test: build + ./alu + +build: alu.t.v alu.v alu1.v + iverilog alu.t.v -o alu + +clean: + rm alu + From 77e09e43b2f794d3d7f863df66f8655d1130c535 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Thu, 12 Oct 2017 13:49:52 -0400 Subject: [PATCH 07/26] added fpga wrapper for alu --- alu_wrapper.v | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 alu_wrapper.v diff --git a/alu_wrapper.v b/alu_wrapper.v new file mode 100644 index 0000000..92112a9 --- /dev/null +++ b/alu_wrapper.v @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +`include "alu.v" + + +//-------------------------------------------------------------------------------- +// Basic building block modules +//-------------------------------------------------------------------------------- + +// D flip-flop with parameterized bit width (default: 1-bit) +// Parameters in Verilog: http://www.asic-world.com/verilog/para_modules1.html +module dff #( parameter W = 1 ) +( + input trigger, + input enable, + input [W-1:0] d, + output reg [W-1:0] q +); + always @(posedge trigger) begin + if(enable) begin + q <= d; + end + end +endmodule + +// JK flip-flop +module jkff1 +( + input trigger, + input j, + input k, + output reg q +); + always @(posedge trigger) begin + if(j && ~k) begin + q <= 1'b1; + end + else if(k && ~j) begin + q <= 1'b0; + end + else if(k && j) begin + q <= ~q; + end + end +endmodule + +// Two-input MUX with parameterized bit width (default: 1-bit) +module mux2 #( parameter W = 1 ) +( + input[W-1:0] in0, + input[W-1:0] in1, + input sel, + output[W-1:0] out +); + // Conditional operator - http://www.verilog.renerta.com/source/vrg00010.htm + assign out = (sel) ? in1 : in0; +endmodule + + + +module alu_wrapper +( + input clk, + input [3:0] sw, + input [3:0] btn, + output [3:0] led +); + + wire[31:0] opA, opB; // Stored inputs to ALU + wire[3:0] res0; + wire[31:0] res1; // Output display options + wire res_sel; // Select between display options + wire cout; // Carry out from ALU + wire ovf; // Overflow from ALU + wire zero; // Zero flag from ALU + + + // Memory for stored operands (parametric width set to 4 bits) + dff #(4) opA_mem(.trigger(clk), .enable(btn[0]), .d(sw), .q(opA[0 +:4)); + dff #(4) opB_mem(.trigger(clk), .enable(btn[1]), .d(sw), .q(opB[0 +:4)); + + // Capture button input to switch which MUX input to LEDs + jkff1 src_sel(.trigger(clk), .j(btn[3]), .k(btn[2]), .q(res_sel)); + mux2 #(4) output_select(.in0(res0[0 +:4]), .in1(res1), .sel(res_sel), .out(led)); + + // TODO: You write this in your adder.v + ALU32Bit alu(.result(res0), .carryout(cout), .zero(zero), .overflow(ovf), .operandA(opA), .operandB(opB)); + + // Assign bits of second display output to show carry out and overflow + assign res1[0] = cout; + assign res1[1] = ovf; + assign res1[2] = zero; + assign res1[3] = 1'b0; + +endmodule From 75c1e54412c9fdc70781018b8c684f54cb8f89dd Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Thu, 12 Oct 2017 14:44:28 -0400 Subject: [PATCH 08/26] fixed fpga wrapper --- alu_wrapper.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/alu_wrapper.v b/alu_wrapper.v index 92112a9..f6b160a 100644 --- a/alu_wrapper.v +++ b/alu_wrapper.v @@ -66,8 +66,8 @@ module alu_wrapper ); wire[31:0] opA, opB; // Stored inputs to ALU - wire[3:0] res0; - wire[31:0] res1; // Output display options + wire[31:0] res0; + wire[3:0] res1; // Output display options wire res_sel; // Select between display options wire cout; // Carry out from ALU wire ovf; // Overflow from ALU @@ -75,15 +75,15 @@ module alu_wrapper // Memory for stored operands (parametric width set to 4 bits) - dff #(4) opA_mem(.trigger(clk), .enable(btn[0]), .d(sw), .q(opA[0 +:4)); - dff #(4) opB_mem(.trigger(clk), .enable(btn[1]), .d(sw), .q(opB[0 +:4)); + dff #(4) opA_mem(.trigger(clk), .enable(btn[0]), .d(sw), .q(opA[0 +:4])); + dff #(4) opB_mem(.trigger(clk), .enable(btn[1]), .d(sw), .q(opB[0 +:4])); // Capture button input to switch which MUX input to LEDs jkff1 src_sel(.trigger(clk), .j(btn[3]), .k(btn[2]), .q(res_sel)); mux2 #(4) output_select(.in0(res0[0 +:4]), .in1(res1), .sel(res_sel), .out(led)); // TODO: You write this in your adder.v - ALU32Bit alu(.result(res0), .carryout(cout), .zero(zero), .overflow(ovf), .operandA(opA), .operandB(opB)); + ALU alu(.result(res0), .carryout(cout), .zero(zero), .overflow(ovf), .operandA(opA), .operandB(opB)); // Assign bits of second display output to show carry out and overflow assign res1[0] = cout; From 18ec17012e253a306a858543a4448648d88c5922 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Thu, 12 Oct 2017 16:02:37 -0400 Subject: [PATCH 09/26] ready for fpga push --- ZYBO_Master.xdc | 146 ++++++++++++++++++++++++++++++++++++++++++++++++ alu_wrapper.v | 4 +- 2 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 ZYBO_Master.xdc diff --git a/ZYBO_Master.xdc b/ZYBO_Master.xdc new file mode 100644 index 0000000..f3dbb71 --- /dev/null +++ b/ZYBO_Master.xdc @@ -0,0 +1,146 @@ +## This file is a general .xdc for the ZYBO Rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used signals according to the project + + +##Clock signal +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk +#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }]; + + +##Switches +set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0 +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1 +set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2 +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3 + + +##Buttons +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0 +set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1 +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2 +set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3 + + +##LEDs +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0 +set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1 +set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2 +set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3 + + +##I2S Audio Codec +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK +#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT +#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC + + +##Audio Codec/external EEPROM IIC bus +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA + + +##Additional Ethernet signals +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B + + +##HDMI Signals +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P +#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P +#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N +#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P +#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N +#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P +#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD +#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA + + +##Pmod Header JA (XADC) +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P +#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N +#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N +#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N + + +##Pmod Header JB +#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p +#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N +#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P +#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N +#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P +#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N + + +##Pmod Header JC +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P +#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N +#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P +#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N + + +##Pmod Header JD +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P +#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P +#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N + + +##Pmod Header JE +#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1 +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2 +#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3 +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4 +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7 +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8 +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9 +#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10 + + +##USB-OTG overcurrent detect pin +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC + + +##VGA Connector +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1 +#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2 +#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3 +#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4 +#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5 +#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0 +#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1 +#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2 +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3 +#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4 +#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5 +#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1 +#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2 +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3 +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4 +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5 +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS diff --git a/alu_wrapper.v b/alu_wrapper.v index f6b160a..9971958 100644 --- a/alu_wrapper.v +++ b/alu_wrapper.v @@ -66,6 +66,7 @@ module alu_wrapper ); wire[31:0] opA, opB; // Stored inputs to ALU + wire[2:0] command; wire[31:0] res0; wire[3:0] res1; // Output display options wire res_sel; // Select between display options @@ -77,13 +78,14 @@ module alu_wrapper // Memory for stored operands (parametric width set to 4 bits) dff #(4) opA_mem(.trigger(clk), .enable(btn[0]), .d(sw), .q(opA[0 +:4])); dff #(4) opB_mem(.trigger(clk), .enable(btn[1]), .d(sw), .q(opB[0 +:4])); + dff #(3) cmd_mem(.trigger(clk), .enable(btn[2]), .d(sw[0+:3]), .q(command)); // Capture button input to switch which MUX input to LEDs jkff1 src_sel(.trigger(clk), .j(btn[3]), .k(btn[2]), .q(res_sel)); mux2 #(4) output_select(.in0(res0[0 +:4]), .in1(res1), .sel(res_sel), .out(led)); // TODO: You write this in your adder.v - ALU alu(.result(res0), .carryout(cout), .zero(zero), .overflow(ovf), .operandA(opA), .operandB(opB)); + ALU alu(.result(res0), .carryout(cout), .zero(zero), .overflow(ovf), .operandA(opA), .operandB(opB), .command(command)); // Assign bits of second display output to show carry out and overflow assign res1[0] = cout; From 452b277661fb95acb26135583112e6829945ea76 Mon Sep 17 00:00:00 2001 From: TShapinsky Date: Thu, 12 Oct 2017 23:13:14 -0400 Subject: [PATCH 10/26] Create Writeup.md --- Writeup.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Writeup.md diff --git a/Writeup.md b/Writeup.md new file mode 100644 index 0000000..147d192 --- /dev/null +++ b/Writeup.md @@ -0,0 +1,18 @@ +## Implementation +Going into this lab we knew the bigget decision to be made for the ALU would be whether to implement it through a bit slice method or individualy via several independent logic circuits through a decoder. In the end we decided to use a bit slice because it is much easier to define dynamically and in the end should result in a more compact design. + +### Bit Slice + +### SLT + +### ALU +The first thing that the ALU does when it recieves information (op A, op B, command) is expand the command from a 3 bit binary bus to a 7 bit one-hot bus. This operation if not implemented in the top level of the ALU would be required in each ALU sliced bit individually, so in this case implementing it once for the top level gives a 32 fold gate reduction. + +## Test Results +### Test Choice +### Test Driven Development Catches Bugs +### Discovered Tests + +## Timing + +## Work Plan Reflection From 437adce06be1b209822f8e25ea4c69bf1cf7f92e Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Thu, 12 Oct 2017 23:59:23 -0400 Subject: [PATCH 11/26] added flag enable --- alu.v | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/alu.v b/alu.v index eb4ec75..c783eec 100644 --- a/alu.v +++ b/alu.v @@ -12,11 +12,13 @@ input[2:0] command wire[31:0] zerobus; wire[31:0] overrideBus; wire[31:0] resultBus; - wire carryout; wire mixedSigns; wire sameSigns; wire possibleOverflow; wire sltPre; + wire flagsEnable; + wire carryoutint, overflowint; + reg[7:0] commandslice; always @(command) begin @@ -54,16 +56,21 @@ input[2:0] command `OR subflag(carryinbus[0], commandslice[1], commandslice[1]); //set carryout to the lest carry bit //this or gate is also a wire - `OR carryor(carryout, carryinbus[32], carryinbus[32]); + `OR carryor(carryoutint, carryinbus[32], carryinbus[32]); //and all the zero outputs to get the zero output and32 zeroout(zero, zerobus); //calculate overflow `XOR overflowXor(possibleOverflow, result[31], carryout); `XNOR overflowXnor(sameSigns, operandA[31], operandB[31]); - `AND overflowAnd(overflow, possibleOverflow, sameSigns); + `AND overflowAnd(overflowint, possibleOverflow, sameSigns); //handle the slt stuff `NOT sltNot(mixedSigns, sameSigns); `AND sltOut(sltPre, carryinbus[32], commandslice[3]); `XOR sltOut2(overrideBus[0], sltPre, mixedSigns); or32P resultOr(result, resultBus, overrideBus); + //flag enabling + `OR addorsub(flagsEnable, commandslice[0], commandslice[1]); + `AND overflowand(overflow, overflowint, flagsEnable); + `AND carryoutand(carryout, carryoutint, flagsEnable); + endmodule From 02e4b8a2ed698084ae0ae90d09df12c4cb46b60e Mon Sep 17 00:00:00 2001 From: TShapinsky Date: Fri, 13 Oct 2017 00:15:32 -0400 Subject: [PATCH 12/26] Update Writeup.md --- Writeup.md | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Writeup.md b/Writeup.md index 147d192..f369dea 100644 --- a/Writeup.md +++ b/Writeup.md @@ -6,7 +6,13 @@ Going into this lab we knew the bigget decision to be made for the ALU would be ### SLT ### ALU -The first thing that the ALU does when it recieves information (op A, op B, command) is expand the command from a 3 bit binary bus to a 7 bit one-hot bus. This operation if not implemented in the top level of the ALU would be required in each ALU sliced bit individually, so in this case implementing it once for the top level gives a 32 fold gate reduction. +The first thing that the ALU does when it recieves information (op A, op B, command) is expand the command from a 3 bit binary bus to a 7 bit one-hot bus. This operation if not implemented in the top level of the ALU would be required in each ALU sliced bit individually, so in this case implementing it once for the top level gives a 32 fold gate reduction. + +#### Subtraction +In the case of subtraction the LSB of the carryin bus is flipped to a 1 and each individual bit of the B operand is flipped by the 1 bit ALU slices which then do single bit addition, resulting in a subtraction action. + +#### Addition +In the case of addition each the LSB of the carryin bus is left empty and the carryout of each 1 bit ALU slice is connected to the carryin of the next bit, with the final connected to an AND gate to enable the carryout flag. ## Test Results ### Test Choice @@ -16,3 +22,4 @@ The first thing that the ALU does when it recieves information (op A, op B, comm ## Timing ## Work Plan Reflection +Writing the implementation happened fairly quickly in about the time we predicted, however the act of gathering information and creating visuals for the From ad380b6dc7da2d1671af4244c62ea6605384131b Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Fri, 13 Oct 2017 00:34:48 -0400 Subject: [PATCH 13/26] added tests --- alu.t.v | 53 ++++++++++++++++------------------------------------- 1 file changed, 16 insertions(+), 37 deletions(-) diff --git a/alu.t.v b/alu.t.v index 409c4b5..bbbf196 100644 --- a/alu.t.v +++ b/alu.t.v @@ -10,45 +10,24 @@ module testALU(); wire overflow; wire signed[31:0] result; + ALU dut(result, carryout, zero, overflow, a, b, command); initial begin - command = 3'd2; - a = -4; - b = -4; #10000000 - $display("%d %d %d", a, b, result); - a = -3; - b = -4; #10000000 - $display("%d %d %d", a, b, result); - a = -4; - b = -3; #10000000 - $display("%d %d %d", a, b, result); - a = 4; - b = 4; #10000000 - $display("%d %d %d", a, b, result); - a = 3; - b = 4; #10000000 - $display("%d %d %d", a, b, result); - a = 4; - b = 3; #10000000 - $display("%d %d %d", a, b, result); - a = 3; - b = 0; #10000000 - $display("%d %d %d", a, b, result); - a = 0; - b = 3; #10000000 - $display("%d %d %d", a, b, result); - a = -3; - b = 0; #10000000 - $display("%d %d %d", a, b, result); - a = 0; - b = -3; #10000000 - $display("%d %d %d", a, b, result); - a = 4; - b = -3; #10000000 - $display("%d %d %d", a, b, result); - a = -4; - b = 3; #10000000 - $display("%d %d %d", a, b, result); + $dumpfile("alu.vcd"); + $dumpvars(0, testALU); + command = 3'd0; + a = -4; + b = 4; #1000000 + if (result != 0 || overflow || !zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + + command = 3'd1; + a = 4; + b = 4; #1000000 + if (result != 0 || overflow || !zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end end endmodule From 01e44d4a2603a90d54d9733c1c5803503d771d61 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Fri, 13 Oct 2017 00:50:21 -0400 Subject: [PATCH 14/26] added two more test cases --- alu.t.v | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/alu.t.v b/alu.t.v index bbbf196..e23e6bd 100644 --- a/alu.t.v +++ b/alu.t.v @@ -22,6 +22,11 @@ module testALU(); if (result != 0 || overflow || !zero) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); end + a = 31'h7fffffff; + b = 1; #1000000 + if (result != 31'h80000000 || !overflow || zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end command = 3'd1; a = 4; @@ -29,5 +34,10 @@ module testALU(); if (result != 0 || overflow || !zero) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); end + a = 31'h80000000; + b = 1; #1000000 + if (result != 31'h7fffffff || !overflow || zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end end endmodule From f0f5cca17752369bdab280d444cffcd8a4b7f3ef Mon Sep 17 00:00:00 2001 From: Henry Rachootin Date: Fri, 13 Oct 2017 01:03:23 -0400 Subject: [PATCH 15/26] fixed some bugs --- alu | 30449 +++++++++++++++++++++++++++--------------------------- alu.t.v | 41 +- alu.v | 18 +- alu1.v | 11 + 4 files changed, 15235 insertions(+), 15284 deletions(-) diff --git a/alu b/alu index 1510f9d..6b00501 100755 --- a/alu +++ b/alu @@ -6,16 +6,16 @@ :vpi_module "vhdl_sys"; :vpi_module "v2005_math"; :vpi_module "va_math"; -S_0x17c4680 .scope module, "testALU" "testALU" 2 4; +S_0xf510b0 .scope module, "testALU" "testALU" 2 4; .timescale -9 -12; -v0x1d6e5c0_0 .var/s "a", 31 0; -v0x1d6e6d0_0 .var/s "b", 31 0; -v0x1d6e7a0_0 .net "carryout", 0 0, L_0x1eac600; 1 drivers -v0x1d6e8a0_0 .var "command", 2 0; -v0x1d6e970_0 .net "overflow", 0 0, L_0x1eb5e20; 1 drivers -v0x1d6ea10_0 .net/s "result", 31 0, L_0x1eba0f0; 1 drivers -v0x1d6eb00_0 .net "zero", 0 0, L_0x1eb5590; 1 drivers -S_0x1a570b0 .scope module, "dut" "ALU" 2 13, 3 2 0, S_0x17c4680; +v0x1201d20_0 .var/s "a", 31 0; +v0x1201e30_0 .var/s "b", 31 0; +v0x1201f00_0 .net "carryout", 0 0, L_0x133ff10; 1 drivers +v0x1202000_0 .var "command", 2 0; +v0x12020d0_0 .net "overflow", 0 0, L_0x1349900; 1 drivers +v0x1202170_0 .net/s "result", 31 0, L_0x134e4a0; 1 drivers +v0x1202260_0 .net "zero", 0 0, L_0x1348e30; 1 drivers +S_0xf2fc10 .scope module, "dut" "ALU" 2 13, 3 2 0, S_0xf510b0; .timescale -9 -12; .port_info 0 /OUTPUT 32 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -24,236 +24,246 @@ S_0x1a570b0 .scope module, "dut" "ALU" 2 13, 3 2 0, S_0x17c4680; .port_info 4 /INPUT 32 "operandA" .port_info 5 /INPUT 32 "operandB" .port_info 6 /INPUT 3 "command" -L_0x1e0c750/d .functor OR 1, L_0x1ead720, L_0x1eac560, C4<0>, C4<0>; -L_0x1e0c750 .delay 1 (30000,30000,30000) L_0x1e0c750/d; -L_0x1eac600/d .functor OR 1, L_0x1eac670, L_0x1eac710, C4<0>, C4<0>; -L_0x1eac600 .delay 1 (30000,30000,30000) L_0x1eac600/d; -L_0x1eb58a0/d .functor XOR 1, L_0x1eb5960, L_0x1eac600, C4<0>, C4<0>; -L_0x1eb58a0 .delay 1 (30000,30000,30000) L_0x1eb58a0/d; -L_0x1ead7c0/d .functor XNOR 1, L_0x1ead880, L_0x1ead9e0, C4<0>, C4<0>; -L_0x1ead7c0 .delay 1 (20000,20000,20000) L_0x1ead7c0/d; -L_0x1eb5e20/d .functor AND 1, L_0x1eb58a0, L_0x1ead7c0, C4<1>, C4<1>; -L_0x1eb5e20 .delay 1 (30000,30000,30000) L_0x1eb5e20/d; -L_0x1eb5fd0/d .functor NOT 1, L_0x1ead7c0, C4<0>, C4<0>, C4<0>; -L_0x1eb5fd0 .delay 1 (10000,10000,10000) L_0x1eb5fd0/d; -L_0x1eb6130/d .functor AND 1, L_0x1eb61f0, L_0x1eb6350, C4<1>, C4<1>; -L_0x1eb6130 .delay 1 (30000,30000,30000) L_0x1eb6130/d; -L_0x1eb7020/d .functor XOR 1, L_0x1eb6130, L_0x1eb5fd0, C4<0>, C4<0>; -L_0x1eb7020 .delay 1 (30000,30000,30000) L_0x1eb7020/d; -v0x1d6b100_0 .net *"_s106", 0 0, L_0x1dd18f0; 1 drivers -v0x1d6b1e0_0 .net *"_s117", 0 0, L_0x1ddb510; 1 drivers -v0x1d6b2c0_0 .net *"_s128", 0 0, L_0x1de5140; 1 drivers -v0x1d6b380_0 .net *"_s139", 0 0, L_0x1deed50; 1 drivers -v0x1d6b460_0 .net *"_s150", 0 0, L_0x1df8990; 1 drivers -v0x1d6b590_0 .net *"_s161", 0 0, L_0x1e02570; 1 drivers -v0x1d6b670_0 .net *"_s172", 0 0, L_0x1e0c380; 1 drivers -v0x1d6b750_0 .net *"_s18", 0 0, L_0x1d825d0; 1 drivers -v0x1d6b830_0 .net *"_s183", 0 0, L_0x1e16100; 1 drivers -v0x1d6b9a0_0 .net *"_s194", 0 0, L_0x1e1ff60; 1 drivers -v0x1d6ba80_0 .net *"_s205", 0 0, L_0x1e29b50; 1 drivers -v0x1d6bb60_0 .net *"_s216", 0 0, L_0x1e337b0; 1 drivers -v0x1d6bc40_0 .net *"_s227", 0 0, L_0x1e3d430; 1 drivers -v0x1d6bd20_0 .net *"_s238", 0 0, L_0x1da9440; 1 drivers -v0x1d6be00_0 .net *"_s249", 0 0, L_0x1e52d40; 1 drivers -v0x1d6bee0_0 .net *"_s260", 0 0, L_0x1e5c8a0; 1 drivers -v0x1d6bfc0_0 .net *"_s271", 0 0, L_0x1e665a0; 1 drivers -v0x1d6c170_0 .net *"_s282", 0 0, L_0x1e70230; 1 drivers -v0x1d6c210_0 .net *"_s29", 0 0, L_0x1d8bf80; 1 drivers -v0x1d6c2f0_0 .net *"_s293", 0 0, L_0x1e79e70; 1 drivers -v0x1d6c3d0_0 .net *"_s304", 0 0, L_0x1e83ae0; 1 drivers -v0x1d6c4b0_0 .net *"_s315", 0 0, L_0x1e8d720; 1 drivers -v0x1d6c590_0 .net *"_s326", 0 0, L_0x1e97330; 1 drivers -v0x1d6c670_0 .net *"_s337", 0 0, L_0x1ea0f80; 1 drivers -v0x1d6c750_0 .net *"_s350", 0 0, L_0x1ea5000; 1 drivers -v0x1d6c830_0 .net *"_s352", 0 0, L_0x1e0c750; 1 drivers -v0x1d6c910_0 .net *"_s356", 0 0, L_0x1ead720; 1 drivers -v0x1d6c9f0_0 .net *"_s358", 0 0, L_0x1eac560; 1 drivers -v0x1d6cad0_0 .net *"_s360", 0 0, L_0x1eac670; 1 drivers -v0x1d6cbb0_0 .net *"_s362", 0 0, L_0x1eac710; 1 drivers -v0x1d6cc90_0 .net *"_s364", 0 0, L_0x1eb5960; 1 drivers -v0x1d6cd70_0 .net *"_s366", 0 0, L_0x1ead880; 1 drivers -v0x1d6ce50_0 .net *"_s368", 0 0, L_0x1ead9e0; 1 drivers -v0x1d6c0a0_0 .net *"_s370", 0 0, L_0x1eb61f0; 1 drivers -v0x1d6d120_0 .net *"_s372", 0 0, L_0x1eb6350; 1 drivers -v0x1d6d200_0 .net *"_s373", 0 0, L_0x1eb7020; 1 drivers -v0x1d6d2e0_0 .net *"_s40", 0 0, L_0x1d95f40; 1 drivers -v0x1d6d3c0_0 .net *"_s51", 0 0, L_0x1d95cb0; 1 drivers -v0x1d6d4a0_0 .net *"_s62", 0 0, L_0x1daa440; 1 drivers -v0x1d6d580_0 .net *"_s73", 0 0, L_0x1db4170; 1 drivers -v0x1d6d660_0 .net *"_s84", 0 0, L_0x1dbdf10; 1 drivers -v0x1d6d740_0 .net *"_s95", 0 0, L_0x1dc7be0; 1 drivers -v0x1d6d820_0 .net "carryinbus", 32 0, L_0x1eab320; 1 drivers -v0x1d6d900_0 .net "carryout", 0 0, L_0x1eac600; alias, 1 drivers -v0x1d6d9c0_0 .net "command", 2 0, v0x1d6e8a0_0; 1 drivers -v0x1d6daa0_0 .var "commandslice", 7 0; -v0x1d6db60_0 .net "mixedSigns", 0 0, L_0x1eb5fd0; 1 drivers -v0x1d6dc20_0 .net "operandA", 31 0, v0x1d6e5c0_0; 1 drivers -v0x1d6dd00_0 .net "operandB", 31 0, v0x1d6e6d0_0; 1 drivers -v0x1d6dde0_0 .net "overflow", 0 0, L_0x1eb5e20; alias, 1 drivers -v0x1d6dea0_0 .net "overrideBus", 31 0, L_0x1eb5ac0; 1 drivers -v0x1d6df60_0 .net "possibleOverflow", 0 0, L_0x1eb58a0; 1 drivers -v0x1d6e000_0 .net "result", 31 0, L_0x1eba0f0; alias, 1 drivers -v0x1d6e0f0_0 .net "resultBus", 31 0, L_0x1eaaf20; 1 drivers -v0x1d6e1c0_0 .net "sameSigns", 0 0, L_0x1ead7c0; 1 drivers -v0x1d6e260_0 .net "sltPre", 0 0, L_0x1eb6130; 1 drivers -v0x1d6e320_0 .net "zero", 0 0, L_0x1eb5590; alias, 1 drivers -v0x1d6e3f0_0 .net "zerobus", 31 0, L_0x1e026d0; 1 drivers -E_0x1b385b0 .event edge, v0x1d6d9c0_0; -L_0x1d786d0 .part v0x1d6e5c0_0, 0, 1; -L_0x1d78830 .part v0x1d6e6d0_0, 0, 1; -L_0x1d78920 .part L_0x1eab320, 0, 1; -L_0x1d82330 .part v0x1d6e5c0_0, 1, 1; -L_0x1d82490 .part v0x1d6e6d0_0, 1, 1; -L_0x1d82530 .part L_0x1eab320, 1, 1; -L_0x1d8bee0 .part v0x1d6e5c0_0, 2, 1; -L_0x1d8c0d0 .part v0x1d6e6d0_0, 2, 1; -L_0x1d8c200 .part L_0x1eab320, 2, 1; -L_0x1d95c10 .part v0x1d6e5c0_0, 3, 1; -L_0x1d95d70 .part v0x1d6e6d0_0, 3, 1; -L_0x1d95e10 .part L_0x1eab320, 3, 1; -L_0x1d9f810 .part v0x1d6e5c0_0, 4, 1; -L_0x1d9f970 .part v0x1d6e6d0_0, 4, 1; -L_0x1d9fa10 .part L_0x1eab320, 4, 1; -L_0x1daa3a0 .part v0x1d6e5c0_0, 5, 1; -L_0x1daa590 .part v0x1d6e6d0_0, 5, 1; -L_0x1daa630 .part L_0x1eab320, 5, 1; -L_0x1db40d0 .part v0x1d6e5c0_0, 6, 1; -L_0x1db4340 .part v0x1d6e6d0_0, 6, 1; -L_0x1daa6d0 .part L_0x1eab320, 6, 1; -L_0x1dbde70 .part v0x1d6e5c0_0, 7, 1; -L_0x1db44f0 .part v0x1d6e6d0_0, 7, 1; -L_0x1dbe090 .part L_0x1eab320, 7, 1; -L_0x1dc7b40 .part v0x1d6e5c0_0, 8, 1; -L_0x1dc7ca0 .part v0x1d6e6d0_0, 8, 1; -L_0x1dbe240 .part L_0x1eab320, 8, 1; -L_0x1dd1850 .part v0x1d6e5c0_0, 9, 1; -L_0x1dc7d40 .part v0x1d6e6d0_0, 9, 1; -L_0x1dd1aa0 .part L_0x1eab320, 9, 1; -L_0x1ddb470 .part v0x1d6e5c0_0, 10, 1; -L_0x1ddb5d0 .part v0x1d6e6d0_0, 10, 1; -L_0x1dd1b40 .part L_0x1eab320, 10, 1; -L_0x1de50a0 .part v0x1d6e5c0_0, 11, 1; -L_0x1ddb670 .part v0x1d6e6d0_0, 11, 1; -L_0x1de5320 .part L_0x1eab320, 11, 1; -L_0x1deecb0 .part v0x1d6e5c0_0, 12, 1; -L_0x1deee10 .part v0x1d6e6d0_0, 12, 1; -L_0x1de53c0 .part L_0x1eab320, 12, 1; -L_0x1df88f0 .part v0x1d6e5c0_0, 13, 1; -L_0x1deeeb0 .part v0x1d6e6d0_0, 13, 1; -L_0x1deef50 .part L_0x1eab320, 13, 1; -L_0x1e024d0 .part v0x1d6e5c0_0, 14, 1; -L_0x1db4230 .part v0x1d6e6d0_0, 14, 1; -L_0x1db43e0 .part L_0x1eab320, 14, 1; -L_0x1e0c2e0 .part v0x1d6e5c0_0, 15, 1; -L_0x1e02a50 .part v0x1d6e6d0_0, 15, 1; -L_0x1e02af0 .part L_0x1eab320, 15, 1; -L_0x1e16060 .part v0x1d6e5c0_0, 16, 1; -L_0x1e161c0 .part v0x1d6e6d0_0, 16, 1; -L_0x1e0c7d0 .part L_0x1eab320, 16, 1; -L_0x1e1fec0 .part v0x1d6e5c0_0, 17, 1; -L_0x1e16260 .part v0x1d6e6d0_0, 17, 1; -L_0x1e16300 .part L_0x1eab320, 17, 1; -L_0x1e29ab0 .part v0x1d6e5c0_0, 18, 1; -L_0x1e29c10 .part v0x1d6e6d0_0, 18, 1; -L_0x1e20020 .part L_0x1eab320, 18, 1; -L_0x1e33710 .part v0x1d6e5c0_0, 19, 1; -L_0x1e29cb0 .part v0x1d6e6d0_0, 19, 1; -L_0x1e29d50 .part L_0x1eab320, 19, 1; -L_0x1e3d390 .part v0x1d6e5c0_0, 20, 1; -L_0x1e3d4f0 .part v0x1d6e6d0_0, 20, 1; -L_0x1e33870 .part L_0x1eab320, 20, 1; -L_0x1da93a0 .part v0x1d6e5c0_0, 21, 1; -L_0x1da9500 .part v0x1d6e6d0_0, 21, 1; -L_0x1da95a0 .part L_0x1eab320, 21, 1; -L_0x1e52ca0 .part v0x1d6e5c0_0, 22, 1; -L_0x1e52e00 .part v0x1d6e6d0_0, 22, 1; -L_0x1e49230 .part L_0x1eab320, 22, 1; -L_0x1e5c800 .part v0x1d6e5c0_0, 23, 1; -L_0x1e52ea0 .part v0x1d6e6d0_0, 23, 1; -L_0x1e52f40 .part L_0x1eab320, 23, 1; -L_0x1e66500 .part v0x1d6e5c0_0, 24, 1; -L_0x1e66660 .part v0x1d6e6d0_0, 24, 1; -L_0x1e5c960 .part L_0x1eab320, 24, 1; -L_0x1e70190 .part v0x1d6e5c0_0, 25, 1; -L_0x1e66700 .part v0x1d6e6d0_0, 25, 1; -L_0x1e667a0 .part L_0x1eab320, 25, 1; -L_0x1e79dd0 .part v0x1d6e5c0_0, 26, 1; -L_0x1e79f30 .part v0x1d6e6d0_0, 26, 1; -L_0x1e702f0 .part L_0x1eab320, 26, 1; -L_0x1e83a40 .part v0x1d6e5c0_0, 27, 1; -L_0x1e79fd0 .part v0x1d6e6d0_0, 27, 1; -L_0x1e7a070 .part L_0x1eab320, 27, 1; -L_0x1e8d680 .part v0x1d6e5c0_0, 28, 1; -L_0x1e8d7e0 .part v0x1d6e6d0_0, 28, 1; -L_0x1e83ba0 .part L_0x1eab320, 28, 1; -L_0x1e97290 .part v0x1d6e5c0_0, 29, 1; -L_0x1e8d880 .part v0x1d6e6d0_0, 29, 1; -L_0x1e8d920 .part L_0x1eab320, 29, 1; -L_0x1ea0ee0 .part v0x1d6e5c0_0, 30, 1; -L_0x1e02630 .part v0x1d6e6d0_0, 30, 1; -L_0x1e973f0 .part L_0x1eab320, 30, 1; -LS_0x1eaaf20_0_0 .concat8 [ 1 1 1 1], L_0x1d748d0, L_0x1d7e3f0, L_0x1d88040, L_0x1d91d70; -LS_0x1eaaf20_0_4 .concat8 [ 1 1 1 1], L_0x1d9b970, L_0x1da55c0, L_0x1db0230, L_0x1db9ef0; -LS_0x1eaaf20_0_8 .concat8 [ 1 1 1 1], L_0x1dc3ca0, L_0x1dcd9b0, L_0x1dd7600, L_0x1de1200; -LS_0x1eaaf20_0_12 .concat8 [ 1 1 1 1], L_0x1deae10, L_0x1df4a50, L_0x1dfe630, L_0x1e08440; -LS_0x1eaaf20_0_16 .concat8 [ 1 1 1 1], L_0x1e121c0, L_0x1e1bfc0, L_0x1e25c10, L_0x1e2f810; -LS_0x1eaaf20_0_20 .concat8 [ 1 1 1 1], L_0x1e394c0, L_0x1e43140, L_0x1e4ed40, L_0x1e58a20; -LS_0x1eaaf20_0_24 .concat8 [ 1 1 1 1], L_0x1e62600, L_0x1e6c230, L_0x1e75f30, L_0x1e7fba0; -LS_0x1eaaf20_0_28 .concat8 [ 1 1 1 1], L_0x1e897e0, L_0x1e933f0, L_0x1e87760, L_0x1ea7080; -LS_0x1eaaf20_1_0 .concat8 [ 4 4 4 4], LS_0x1eaaf20_0_0, LS_0x1eaaf20_0_4, LS_0x1eaaf20_0_8, LS_0x1eaaf20_0_12; -LS_0x1eaaf20_1_4 .concat8 [ 4 4 4 4], LS_0x1eaaf20_0_16, LS_0x1eaaf20_0_20, LS_0x1eaaf20_0_24, LS_0x1eaaf20_0_28; -L_0x1eaaf20 .concat8 [ 16 16 0 0], LS_0x1eaaf20_1_0, LS_0x1eaaf20_1_4; -LS_0x1e026d0_0_0 .concat8 [ 1 1 1 1], L_0x1d785d0, L_0x1d821e0, L_0x1d8bde0, L_0x1d95b10; -LS_0x1e026d0_0_4 .concat8 [ 1 1 1 1], L_0x1d9f710, L_0x1daa2a0, L_0x1db3fd0, L_0x1dbdd70; -LS_0x1e026d0_0_8 .concat8 [ 1 1 1 1], L_0x1dc7a40, L_0x1dd1750, L_0x1ddb370, L_0x1de4fa0; -LS_0x1e026d0_0_12 .concat8 [ 1 1 1 1], L_0x1deebb0, L_0x1df87f0, L_0x1e023d0, L_0x1e0c1e0; -LS_0x1e026d0_0_16 .concat8 [ 1 1 1 1], L_0x1e15f60, L_0x1e1fdc0, L_0x1e299b0, L_0x1e33610; -LS_0x1e026d0_0_20 .concat8 [ 1 1 1 1], L_0x1e3d290, L_0x1da92a0, L_0x1e52ba0, L_0x1e5c700; -LS_0x1e026d0_0_24 .concat8 [ 1 1 1 1], L_0x1e66400, L_0x1e70090, L_0x1e79cd0, L_0x1e83940; -LS_0x1e026d0_0_28 .concat8 [ 1 1 1 1], L_0x1e8d580, L_0x1e97190, L_0x1ea0de0, L_0x1eaae20; -LS_0x1e026d0_1_0 .concat8 [ 4 4 4 4], LS_0x1e026d0_0_0, LS_0x1e026d0_0_4, LS_0x1e026d0_0_8, LS_0x1e026d0_0_12; -LS_0x1e026d0_1_4 .concat8 [ 4 4 4 4], LS_0x1e026d0_0_16, LS_0x1e026d0_0_20, LS_0x1e026d0_0_24, LS_0x1e026d0_0_28; -L_0x1e026d0 .concat8 [ 16 16 0 0], LS_0x1e026d0_1_0, LS_0x1e026d0_1_4; -L_0x1eabda0 .part v0x1d6e5c0_0, 31, 1; -L_0x1eab190 .part v0x1d6e6d0_0, 31, 1; -L_0x1eab230 .part L_0x1eab320, 31, 1; -LS_0x1eab320_0_0 .concat8 [ 1 1 1 1], L_0x1e0c750, L_0x1d78270, L_0x1d81e80, L_0x1d8ba80; -LS_0x1eab320_0_4 .concat8 [ 1 1 1 1], L_0x1d957b0, L_0x1d9f3b0, L_0x1da9f40, L_0x1db3c70; -LS_0x1eab320_0_8 .concat8 [ 1 1 1 1], L_0x1dbda10, L_0x1dc76e0, L_0x1dd13f0, L_0x1ddb010; -LS_0x1eab320_0_12 .concat8 [ 1 1 1 1], L_0x1de4c40, L_0x1dee850, L_0x1df8490, L_0x1e02070; -LS_0x1eab320_0_16 .concat8 [ 1 1 1 1], L_0x1e0be80, L_0x1e15c00, L_0x1e1fa60, L_0x1e29650; -LS_0x1eab320_0_20 .concat8 [ 1 1 1 1], L_0x1e332b0, L_0x1e3cf30, L_0x1da8f40, L_0x1e52840; -LS_0x1eab320_0_24 .concat8 [ 1 1 1 1], L_0x1e5c3a0, L_0x1e660a0, L_0x1e6fd30, L_0x1e79970; -LS_0x1eab320_0_28 .concat8 [ 1 1 1 1], L_0x1e835e0, L_0x1e8d220, L_0x1e96e30, L_0x1ea0a80; -LS_0x1eab320_0_32 .concat8 [ 1 0 0 0], L_0x1eaaac0; -LS_0x1eab320_1_0 .concat8 [ 4 4 4 4], LS_0x1eab320_0_0, LS_0x1eab320_0_4, LS_0x1eab320_0_8, LS_0x1eab320_0_12; -LS_0x1eab320_1_4 .concat8 [ 4 4 4 4], LS_0x1eab320_0_16, LS_0x1eab320_0_20, LS_0x1eab320_0_24, LS_0x1eab320_0_28; -LS_0x1eab320_1_8 .concat8 [ 1 0 0 0], LS_0x1eab320_0_32; -L_0x1eab320 .concat8 [ 16 16 1 0], LS_0x1eab320_1_0, LS_0x1eab320_1_4, LS_0x1eab320_1_8; -L_0x1ead720 .part v0x1d6daa0_0, 1, 1; -L_0x1eac560 .part v0x1d6daa0_0, 1, 1; -L_0x1eac670 .part L_0x1eab320, 32, 1; -L_0x1eac710 .part L_0x1eab320, 32, 1; -L_0x1eb5960 .part L_0x1eba0f0, 31, 1; -L_0x1ead880 .part v0x1d6e5c0_0, 31, 1; -L_0x1ead9e0 .part v0x1d6e6d0_0, 31, 1; -L_0x1eb61f0 .part L_0x1eab320, 32, 1; -L_0x1eb6350 .part v0x1d6daa0_0, 3, 1; -LS_0x1eb5ac0_0_0 .concat8 [ 1 1 1 1], L_0x1eb7020, L_0x1d825d0, L_0x1d8bf80, L_0x1d95f40; -LS_0x1eb5ac0_0_4 .concat8 [ 1 1 1 1], L_0x1d95cb0, L_0x1daa440, L_0x1db4170, L_0x1dbdf10; -LS_0x1eb5ac0_0_8 .concat8 [ 1 1 1 1], L_0x1dc7be0, L_0x1dd18f0, L_0x1ddb510, L_0x1de5140; -LS_0x1eb5ac0_0_12 .concat8 [ 1 1 1 1], L_0x1deed50, L_0x1df8990, L_0x1e02570, L_0x1e0c380; -LS_0x1eb5ac0_0_16 .concat8 [ 1 1 1 1], L_0x1e16100, L_0x1e1ff60, L_0x1e29b50, L_0x1e337b0; -LS_0x1eb5ac0_0_20 .concat8 [ 1 1 1 1], L_0x1e3d430, L_0x1da9440, L_0x1e52d40, L_0x1e5c8a0; -LS_0x1eb5ac0_0_24 .concat8 [ 1 1 1 1], L_0x1e665a0, L_0x1e70230, L_0x1e79e70, L_0x1e83ae0; -LS_0x1eb5ac0_0_28 .concat8 [ 1 1 1 1], L_0x1e8d720, L_0x1e97330, L_0x1ea0f80, L_0x1ea5000; -LS_0x1eb5ac0_1_0 .concat8 [ 4 4 4 4], LS_0x1eb5ac0_0_0, LS_0x1eb5ac0_0_4, LS_0x1eb5ac0_0_8, LS_0x1eb5ac0_0_12; -LS_0x1eb5ac0_1_4 .concat8 [ 4 4 4 4], LS_0x1eb5ac0_0_16, LS_0x1eb5ac0_0_20, LS_0x1eb5ac0_0_24, LS_0x1eb5ac0_0_28; -L_0x1eb5ac0 .concat8 [ 16 16 0 0], LS_0x1eb5ac0_1_0, LS_0x1eb5ac0_1_4; -S_0x1a35c10 .scope generate, "alu_slices[0]" "alu_slices[0]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1b31360 .param/l "i" 0 3 37, +C4<00>; -S_0x1a14870 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1a35c10; +L_0x133ec80/d .functor OR 1, L_0x1341030, L_0x133fe70, C4<0>, C4<0>; +L_0x133ec80 .delay 1 (30000,30000,30000) L_0x133ec80/d; +L_0x133ff10/d .functor OR 1, L_0x133ff80, L_0x1340020, C4<0>, C4<0>; +L_0x133ff10 .delay 1 (30000,30000,30000) L_0x133ff10/d; +L_0x1349140/d .functor XOR 1, L_0x1349200, L_0x133ff10, C4<0>, C4<0>; +L_0x1349140 .delay 1 (30000,30000,30000) L_0x1349140/d; +L_0x13410d0/d .functor XNOR 1, L_0x1341340, L_0x1341230, C4<0>, C4<0>; +L_0x13410d0 .delay 1 (20000,20000,20000) L_0x13410d0/d; +L_0x1349360/d .functor NOT 1, L_0x13410d0, C4<0>, C4<0>, C4<0>; +L_0x1349360 .delay 1 (10000,10000,10000) L_0x1349360/d; +L_0x1349f00/d .functor OR 1, L_0x134a010, L_0x1349700, C4<0>, C4<0>; +L_0x1349f00 .delay 1 (30000,30000,30000) L_0x1349f00/d; +L_0x13497f0/d .functor AND 1, L_0x1349140, L_0x1349c60, C4<1>, C4<1>; +L_0x13497f0 .delay 1 (30000,30000,30000) L_0x13497f0/d; +L_0x1349900/d .functor AND 1, L_0x13497f0, L_0x1349f00, C4<1>, C4<1>; +L_0x1349900 .delay 1 (30000,30000,30000) L_0x1349900/d; +L_0x134a5d0/d .functor XOR 1, L_0x133ff10, L_0x1349360, C4<0>, C4<0>; +L_0x134a5d0 .delay 1 (30000,30000,30000) L_0x134a5d0/d; +L_0x134a170/d .functor AND 1, L_0x134a5d0, L_0x134a2d0, C4<1>, C4<1>; +L_0x134a170 .delay 1 (30000,30000,30000) L_0x134a170/d; +v0x11fe570_0 .net *"_s106", 0 0, L_0x1265030; 1 drivers +v0x11fe650_0 .net *"_s117", 0 0, L_0x126ec80; 1 drivers +v0x11fe730_0 .net *"_s128", 0 0, L_0x12788b0; 1 drivers +v0x11fe7f0_0 .net *"_s139", 0 0, L_0x12824c0; 1 drivers +v0x11fe8d0_0 .net *"_s150", 0 0, L_0x128c0d0; 1 drivers +v0x11fea00_0 .net *"_s161", 0 0, L_0x1295c20; 1 drivers +v0x11feae0_0 .net *"_s172", 0 0, L_0x129faf0; 1 drivers +v0x11febc0_0 .net *"_s18", 0 0, L_0x1215c80; 1 drivers +v0x11feca0_0 .net *"_s183", 0 0, L_0x12a9870; 1 drivers +v0x11fee10_0 .net *"_s194", 0 0, L_0x12b36d0; 1 drivers +v0x11feef0_0 .net *"_s205", 0 0, L_0x12bd3b0; 1 drivers +v0x11fefd0_0 .net *"_s216", 0 0, L_0x12c6fb0; 1 drivers +v0x11ff0b0_0 .net *"_s227", 0 0, L_0x12d0c90; 1 drivers +v0x11ff190_0 .net *"_s238", 0 0, L_0x123cc10; 1 drivers +v0x11ff270_0 .net *"_s249", 0 0, L_0x12e65b0; 1 drivers +v0x11ff350_0 .net *"_s260", 0 0, L_0x12f01d0; 1 drivers +v0x11ff430_0 .net *"_s271", 0 0, L_0x12f9e00; 1 drivers +v0x11ff5e0_0 .net *"_s282", 0 0, L_0x1303a60; 1 drivers +v0x11ff680_0 .net *"_s29", 0 0, L_0x121f720; 1 drivers +v0x11ff760_0 .net *"_s293", 0 0, L_0x130d6b0; 1 drivers +v0x11ff840_0 .net *"_s304", 0 0, L_0x1317200; 1 drivers +v0x11ff920_0 .net *"_s315", 0 0, L_0x1320f40; 1 drivers +v0x11ffa00_0 .net *"_s326", 0 0, L_0x132ac10; 1 drivers +v0x11ffae0_0 .net *"_s337", 0 0, L_0x1334840; 1 drivers +v0x11ffbc0_0 .net *"_s350", 0 0, L_0x1338910; 1 drivers +v0x11ffca0_0 .net *"_s352", 0 0, L_0x133ec80; 1 drivers +v0x11ffd80_0 .net *"_s356", 0 0, L_0x1341030; 1 drivers +v0x11ffe60_0 .net *"_s358", 0 0, L_0x133fe70; 1 drivers +v0x11fff40_0 .net *"_s360", 0 0, L_0x133ff80; 1 drivers +v0x1200020_0 .net *"_s362", 0 0, L_0x1340020; 1 drivers +v0x1200100_0 .net *"_s364", 0 0, L_0x1349200; 1 drivers +v0x12001e0_0 .net *"_s366", 0 0, L_0x1341340; 1 drivers +v0x12002c0_0 .net *"_s368", 0 0, L_0x1341230; 1 drivers +v0x11ff510_0 .net *"_s372", 0 0, L_0x134a010; 1 drivers +v0x1200590_0 .net *"_s374", 0 0, L_0x1349700; 1 drivers +v0x1200670_0 .net *"_s375", 0 0, L_0x134a170; 1 drivers +v0x1200750_0 .net *"_s379", 0 0, L_0x134a2d0; 1 drivers +v0x1200830_0 .net *"_s40", 0 0, L_0x1229660; 1 drivers +v0x1200910_0 .net *"_s51", 0 0, L_0x12293d0; 1 drivers +v0x12009f0_0 .net *"_s62", 0 0, L_0x123dbe0; 1 drivers +v0x1200ad0_0 .net *"_s73", 0 0, L_0x12478d0; 1 drivers +v0x1200bb0_0 .net *"_s84", 0 0, L_0x1251650; 1 drivers +v0x1200c90_0 .net *"_s95", 0 0, L_0x125b320; 1 drivers +v0x1200d70_0 .net "addOrSub", 0 0, L_0x1349f00; 1 drivers +v0x1200e30_0 .net "carryinbus", 32 0, L_0x133ebe0; 1 drivers +v0x1200f10_0 .net "carryout", 0 0, L_0x133ff10; alias, 1 drivers +v0x1200fd0_0 .net "command", 2 0, v0x1202000_0; 1 drivers +v0x12010b0_0 .var "commandslice", 7 0; +v0x1201170_0 .net "mixedSigns", 0 0, L_0x1349360; 1 drivers +v0x1201210_0 .net "operandA", 31 0, v0x1201d20_0; 1 drivers +v0x12012d0_0 .net "operandB", 31 0, v0x1201e30_0; 1 drivers +v0x12013b0_0 .net "overFlowPossible", 0 0, L_0x1349c60; 1 drivers +v0x1201480_0 .net "overflow", 0 0, L_0x1349900; alias, 1 drivers +v0x1201520_0 .net "overflowPre", 0 0, L_0x13497f0; 1 drivers +v0x12015e0_0 .net "overrideBus", 31 0, L_0x134a800; 1 drivers +v0x12016d0_0 .net "possibleOverflow", 0 0, L_0x1349140; 1 drivers +v0x1201770_0 .net "result", 31 0, L_0x134e4a0; alias, 1 drivers +v0x1201860_0 .net "resultBus", 31 0, L_0x133e830; 1 drivers +v0x1201930_0 .net "sameSigns", 0 0, L_0x13410d0; 1 drivers +v0x1201a00_0 .net "sltPre", 0 0, L_0x134a5d0; 1 drivers +v0x1201aa0_0 .net "zero", 0 0, L_0x1348e30; alias, 1 drivers +v0x1201b70_0 .net "zerobus", 31 0, L_0x1295d80; 1 drivers +E_0xfc9f50 .event edge, v0x1200fd0_0; +L_0x120bed0 .part v0x1201d20_0, 0, 1; +L_0x120c030 .part v0x1201e30_0, 0, 1; +L_0x120c120 .part L_0x133ebe0, 0, 1; +L_0x12159e0 .part v0x1201d20_0, 1, 1; +L_0x1215b40 .part v0x1201e30_0, 1, 1; +L_0x1215be0 .part L_0x133ebe0, 1, 1; +L_0x121f680 .part v0x1201d20_0, 2, 1; +L_0x121f870 .part v0x1201e30_0, 2, 1; +L_0x121f9a0 .part L_0x133ebe0, 2, 1; +L_0x1229330 .part v0x1201d20_0, 3, 1; +L_0x1229490 .part v0x1201e30_0, 3, 1; +L_0x1229530 .part L_0x133ebe0, 3, 1; +L_0x1232f10 .part v0x1201d20_0, 4, 1; +L_0x1233070 .part v0x1201e30_0, 4, 1; +L_0x1233110 .part L_0x133ebe0, 4, 1; +L_0x123db40 .part v0x1201d20_0, 5, 1; +L_0x123dd30 .part v0x1201e30_0, 5, 1; +L_0x123ddd0 .part L_0x133ebe0, 5, 1; +L_0x1247830 .part v0x1201d20_0, 6, 1; +L_0x1247aa0 .part v0x1201e30_0, 6, 1; +L_0x123de70 .part L_0x133ebe0, 6, 1; +L_0x12515b0 .part v0x1201d20_0, 7, 1; +L_0x1247c50 .part v0x1201e30_0, 7, 1; +L_0x12517d0 .part L_0x133ebe0, 7, 1; +L_0x125b280 .part v0x1201d20_0, 8, 1; +L_0x125b3e0 .part v0x1201e30_0, 8, 1; +L_0x1251980 .part L_0x133ebe0, 8, 1; +L_0x1264f90 .part v0x1201d20_0, 9, 1; +L_0x125b480 .part v0x1201e30_0, 9, 1; +L_0x12651e0 .part L_0x133ebe0, 9, 1; +L_0x126ebe0 .part v0x1201d20_0, 10, 1; +L_0x126ed40 .part v0x1201e30_0, 10, 1; +L_0x1265280 .part L_0x133ebe0, 10, 1; +L_0x1278810 .part v0x1201d20_0, 11, 1; +L_0x126ede0 .part v0x1201e30_0, 11, 1; +L_0x1278a90 .part L_0x133ebe0, 11, 1; +L_0x1282420 .part v0x1201d20_0, 12, 1; +L_0x1282580 .part v0x1201e30_0, 12, 1; +L_0x1278b30 .part L_0x133ebe0, 12, 1; +L_0x128c030 .part v0x1201d20_0, 13, 1; +L_0x1282620 .part v0x1201e30_0, 13, 1; +L_0x12826c0 .part L_0x133ebe0, 13, 1; +L_0x1295b80 .part v0x1201d20_0, 14, 1; +L_0x1247990 .part v0x1201e30_0, 14, 1; +L_0x1247b40 .part L_0x133ebe0, 14, 1; +L_0x129fa50 .part v0x1201d20_0, 15, 1; +L_0x1296100 .part v0x1201e30_0, 15, 1; +L_0x12961a0 .part L_0x133ebe0, 15, 1; +L_0x12a97d0 .part v0x1201d20_0, 16, 1; +L_0x12a9930 .part v0x1201e30_0, 16, 1; +L_0x129ff40 .part L_0x133ebe0, 16, 1; +L_0x12b3630 .part v0x1201d20_0, 17, 1; +L_0x12a99d0 .part v0x1201e30_0, 17, 1; +L_0x12a9a70 .part L_0x133ebe0, 17, 1; +L_0x12bd310 .part v0x1201d20_0, 18, 1; +L_0x12bd470 .part v0x1201e30_0, 18, 1; +L_0x12b3790 .part L_0x133ebe0, 18, 1; +L_0x12c6f10 .part v0x1201d20_0, 19, 1; +L_0x12bd510 .part v0x1201e30_0, 19, 1; +L_0x12bd5b0 .part L_0x133ebe0, 19, 1; +L_0x12d0bf0 .part v0x1201d20_0, 20, 1; +L_0x12d0d50 .part v0x1201e30_0, 20, 1; +L_0x12c7070 .part L_0x133ebe0, 20, 1; +L_0x123cb70 .part v0x1201d20_0, 21, 1; +L_0x123ccd0 .part v0x1201e30_0, 21, 1; +L_0x123cd70 .part L_0x133ebe0, 21, 1; +L_0x12e6510 .part v0x1201d20_0, 22, 1; +L_0x12e6670 .part v0x1201e30_0, 22, 1; +L_0x12dca20 .part L_0x133ebe0, 22, 1; +L_0x12f0130 .part v0x1201d20_0, 23, 1; +L_0x12e6710 .part v0x1201e30_0, 23, 1; +L_0x12e67b0 .part L_0x133ebe0, 23, 1; +L_0x12f9d60 .part v0x1201d20_0, 24, 1; +L_0x12f9ec0 .part v0x1201e30_0, 24, 1; +L_0x12f0290 .part L_0x133ebe0, 24, 1; +L_0x13039c0 .part v0x1201d20_0, 25, 1; +L_0x12f9f60 .part v0x1201e30_0, 25, 1; +L_0x12fa000 .part L_0x133ebe0, 25, 1; +L_0x130d610 .part v0x1201d20_0, 26, 1; +L_0x130d770 .part v0x1201e30_0, 26, 1; +L_0x1303b20 .part L_0x133ebe0, 26, 1; +L_0x1317160 .part v0x1201d20_0, 27, 1; +L_0x130d810 .part v0x1201e30_0, 27, 1; +L_0x130d8b0 .part L_0x133ebe0, 27, 1; +L_0x1320ea0 .part v0x1201d20_0, 28, 1; +L_0x1321000 .part v0x1201e30_0, 28, 1; +L_0x13172c0 .part L_0x133ebe0, 28, 1; +L_0x132ab70 .part v0x1201d20_0, 29, 1; +L_0x13210a0 .part v0x1201e30_0, 29, 1; +L_0x1321140 .part L_0x133ebe0, 29, 1; +L_0x13347a0 .part v0x1201d20_0, 30, 1; +L_0x1295ce0 .part v0x1201e30_0, 30, 1; +L_0x132acd0 .part L_0x133ebe0, 30, 1; +LS_0x133e830_0_0 .concat8 [ 1 1 1 1], L_0x1208030, L_0x1211a70, L_0x121b7e0, L_0x1225490; +LS_0x133e830_0_4 .concat8 [ 1 1 1 1], L_0x122f0e0, L_0x1238d60, L_0x1243990, L_0x124d710; +LS_0x133e830_0_8 .concat8 [ 1 1 1 1], L_0x12573e0, L_0x12610f0, L_0x126ad40, L_0x1274890; +LS_0x133e830_0_12 .concat8 [ 1 1 1 1], L_0x127e580, L_0x1288190, L_0x1291da0, L_0x129bbb0; +LS_0x133e830_0_16 .concat8 [ 1 1 1 1], L_0x12a5900, L_0x12af760, L_0x12b93e0, L_0x12c3070; +LS_0x133e830_0_20 .concat8 [ 1 1 1 1], L_0x12cccc0, L_0x12d6850, L_0x12e25b0, L_0x12ec290; +LS_0x133e830_0_24 .concat8 [ 1 1 1 1], L_0x12f5ea0, L_0x12ffa90, L_0x13096e0, L_0x13133a0; +LS_0x133e830_0_28 .concat8 [ 1 1 1 1], L_0x131cf70, L_0x1326c10, L_0x1330900, L_0x133a990; +LS_0x133e830_1_0 .concat8 [ 4 4 4 4], LS_0x133e830_0_0, LS_0x133e830_0_4, LS_0x133e830_0_8, LS_0x133e830_0_12; +LS_0x133e830_1_4 .concat8 [ 4 4 4 4], LS_0x133e830_0_16, LS_0x133e830_0_20, LS_0x133e830_0_24, LS_0x133e830_0_28; +L_0x133e830 .concat8 [ 16 16 0 0], LS_0x133e830_1_0, LS_0x133e830_1_4; +LS_0x1295d80_0_0 .concat8 [ 1 1 1 1], L_0x120bdd0, L_0x12158e0, L_0x121f580, L_0x1229230; +LS_0x1295d80_0_4 .concat8 [ 1 1 1 1], L_0x1232e10, L_0x123da40, L_0x1247730, L_0x12514b0; +LS_0x1295d80_0_8 .concat8 [ 1 1 1 1], L_0x125b180, L_0x1264e90, L_0x126eae0, L_0x1278710; +LS_0x1295d80_0_12 .concat8 [ 1 1 1 1], L_0x1282320, L_0x128bf30, L_0x1295a80, L_0x129f950; +LS_0x1295d80_0_16 .concat8 [ 1 1 1 1], L_0x12a96d0, L_0x12b3530, L_0x12bd210, L_0x12c6e10; +LS_0x1295d80_0_20 .concat8 [ 1 1 1 1], L_0x12d0af0, L_0x123ca70, L_0x12e6410, L_0x12f0030; +LS_0x1295d80_0_24 .concat8 [ 1 1 1 1], L_0x12f9c60, L_0x13038c0, L_0x130d510, L_0x1317060; +LS_0x1295d80_0_28 .concat8 [ 1 1 1 1], L_0x1320da0, L_0x132aa70, L_0x13346a0, L_0x133e730; +LS_0x1295d80_1_0 .concat8 [ 4 4 4 4], LS_0x1295d80_0_0, LS_0x1295d80_0_4, LS_0x1295d80_0_8, LS_0x1295d80_0_12; +LS_0x1295d80_1_4 .concat8 [ 4 4 4 4], LS_0x1295d80_0_16, LS_0x1295d80_0_20, LS_0x1295d80_0_24, LS_0x1295d80_0_28; +L_0x1295d80 .concat8 [ 16 16 0 0], LS_0x1295d80_1_0, LS_0x1295d80_1_4; +L_0x133f6b0 .part v0x1201d20_0, 31, 1; +L_0x133eaa0 .part v0x1201e30_0, 31, 1; +L_0x133eb40 .part L_0x133ebe0, 31, 1; +LS_0x133ebe0_0_0 .concat8 [ 1 1 1 1], L_0x133ec80, L_0x120ba70, L_0x1215580, L_0x121f220; +LS_0x133ebe0_0_4 .concat8 [ 1 1 1 1], L_0x1228ed0, L_0x1232ab0, L_0x123d6e0, L_0x12473d0; +LS_0x133ebe0_0_8 .concat8 [ 1 1 1 1], L_0x1251150, L_0x125ae20, L_0x1264b30, L_0x126e780; +LS_0x133ebe0_0_12 .concat8 [ 1 1 1 1], L_0x12783b0, L_0x1281fc0, L_0x128bbd0, L_0x1295720; +LS_0x133ebe0_0_16 .concat8 [ 1 1 1 1], L_0x129f5f0, L_0x12a9370, L_0x12b31d0, L_0x12bceb0; +LS_0x133ebe0_0_20 .concat8 [ 1 1 1 1], L_0x12c6ab0, L_0x12d0790, L_0x123c710, L_0x12e60b0; +LS_0x133ebe0_0_24 .concat8 [ 1 1 1 1], L_0x12efcd0, L_0x12f9900, L_0x1303560, L_0x130d1b0; +LS_0x133ebe0_0_28 .concat8 [ 1 1 1 1], L_0x1316d00, L_0x1320a40, L_0x132a710, L_0x1334340; +LS_0x133ebe0_0_32 .concat8 [ 1 0 0 0], L_0x133e3d0; +LS_0x133ebe0_1_0 .concat8 [ 4 4 4 4], LS_0x133ebe0_0_0, LS_0x133ebe0_0_4, LS_0x133ebe0_0_8, LS_0x133ebe0_0_12; +LS_0x133ebe0_1_4 .concat8 [ 4 4 4 4], LS_0x133ebe0_0_16, LS_0x133ebe0_0_20, LS_0x133ebe0_0_24, LS_0x133ebe0_0_28; +LS_0x133ebe0_1_8 .concat8 [ 1 0 0 0], LS_0x133ebe0_0_32; +L_0x133ebe0 .concat8 [ 16 16 1 0], LS_0x133ebe0_1_0, LS_0x133ebe0_1_4, LS_0x133ebe0_1_8; +L_0x1341030 .part v0x12010b0_0, 1, 1; +L_0x133fe70 .part v0x12010b0_0, 1, 1; +L_0x133ff80 .part L_0x133ebe0, 32, 1; +L_0x1340020 .part L_0x133ebe0, 32, 1; +L_0x1349200 .part L_0x134e4a0, 31, 1; +L_0x1341340 .part v0x1201d20_0, 31, 1; +L_0x1341230 .part v0x1201e30_0, 31, 1; +L_0x1349e60 .part v0x12010b0_0, 0, 1; +L_0x134a010 .part v0x12010b0_0, 0, 1; +L_0x1349700 .part v0x12010b0_0, 1, 1; +LS_0x134a800_0_0 .concat8 [ 1 1 1 1], L_0x134a170, L_0x1215c80, L_0x121f720, L_0x1229660; +LS_0x134a800_0_4 .concat8 [ 1 1 1 1], L_0x12293d0, L_0x123dbe0, L_0x12478d0, L_0x1251650; +LS_0x134a800_0_8 .concat8 [ 1 1 1 1], L_0x125b320, L_0x1265030, L_0x126ec80, L_0x12788b0; +LS_0x134a800_0_12 .concat8 [ 1 1 1 1], L_0x12824c0, L_0x128c0d0, L_0x1295c20, L_0x129faf0; +LS_0x134a800_0_16 .concat8 [ 1 1 1 1], L_0x12a9870, L_0x12b36d0, L_0x12bd3b0, L_0x12c6fb0; +LS_0x134a800_0_20 .concat8 [ 1 1 1 1], L_0x12d0c90, L_0x123cc10, L_0x12e65b0, L_0x12f01d0; +LS_0x134a800_0_24 .concat8 [ 1 1 1 1], L_0x12f9e00, L_0x1303a60, L_0x130d6b0, L_0x1317200; +LS_0x134a800_0_28 .concat8 [ 1 1 1 1], L_0x1320f40, L_0x132ac10, L_0x1334840, L_0x1338910; +LS_0x134a800_1_0 .concat8 [ 4 4 4 4], LS_0x134a800_0_0, LS_0x134a800_0_4, LS_0x134a800_0_8, LS_0x134a800_0_12; +LS_0x134a800_1_4 .concat8 [ 4 4 4 4], LS_0x134a800_0_16, LS_0x134a800_0_20, LS_0x134a800_0_24, LS_0x134a800_0_28; +L_0x134a800 .concat8 [ 16 16 0 0], LS_0x134a800_1_0, LS_0x134a800_1_4; +L_0x134a2d0 .part v0x12010b0_0, 3, 1; +S_0xf0e870 .scope generate, "alu_slices[0]" "alu_slices[0]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0xfcf020 .param/l "i" 0 3 41, +C4<00>; +S_0xeed4d0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xf0e870; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -262,445 +272,445 @@ S_0x1a14870 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1a35c10; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1d6ebf0/d .functor NOT 1, L_0x1d786d0, C4<0>, C4<0>, C4<0>; -L_0x1d6ebf0 .delay 1 (10000,10000,10000) L_0x1d6ebf0/d; -L_0x1d6ed00/d .functor NOT 1, L_0x1d78830, C4<0>, C4<0>, C4<0>; -L_0x1d6ed00 .delay 1 (10000,10000,10000) L_0x1d6ed00/d; -L_0x1d6ff90/d .functor XOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; -L_0x1d6ff90 .delay 1 (30000,30000,30000) L_0x1d6ff90/d; -L_0x7f72592da018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d706e0/d .functor OR 1, L_0x7f72592da018, L_0x7f72592da060, C4<0>, C4<0>; -L_0x1d706e0 .delay 1 (30000,30000,30000) L_0x1d706e0/d; -L_0x1d70890/d .functor AND 1, L_0x1d786d0, L_0x1d78830, C4<1>, C4<1>; -L_0x1d70890 .delay 1 (30000,30000,30000) L_0x1d70890/d; -L_0x1d70950/d .functor NAND 1, L_0x1d786d0, L_0x1d78830, C4<1>, C4<1>; -L_0x1d70950 .delay 1 (20000,20000,20000) L_0x1d70950/d; -L_0x1d70ab0/d .functor XOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; -L_0x1d70ab0 .delay 1 (20000,20000,20000) L_0x1d70ab0/d; -L_0x1d70f60/d .functor OR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; -L_0x1d70f60 .delay 1 (30000,30000,30000) L_0x1d70f60/d; -L_0x1d785d0/d .functor NOT 1, L_0x1d748d0, C4<0>, C4<0>, C4<0>; -L_0x1d785d0 .delay 1 (10000,10000,10000) L_0x1d785d0/d; -v0x18995b0_0 .net "A", 0 0, L_0x1d786d0; 1 drivers -v0x1896860_0 .net "A_", 0 0, L_0x1d6ebf0; 1 drivers -v0x1896920_0 .net "B", 0 0, L_0x1d78830; 1 drivers -v0x18a5a80_0 .net "B_", 0 0, L_0x1d6ed00; 1 drivers -v0x18a5b20_0 .net *"_s12", 0 0, L_0x1d706e0; 1 drivers -v0x18a2f10_0 .net/2s *"_s14", 0 0, L_0x7f72592da018; 1 drivers -v0x18a2fb0_0 .net/2s *"_s16", 0 0, L_0x7f72592da060; 1 drivers -v0x1878550_0 .net *"_s18", 0 0, L_0x1d70890; 1 drivers -v0x18781c0_0 .net *"_s20", 0 0, L_0x1d70950; 1 drivers -v0x1875510_0 .net *"_s22", 0 0, L_0x1d70ab0; 1 drivers -v0x18755d0_0 .net *"_s24", 0 0, L_0x1d70f60; 1 drivers -o0x7f7259356328 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1881bc0_0 name=_s30 -o0x7f7259356358 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1857180_0 name=_s32 -v0x1856df0_0 .net *"_s8", 0 0, L_0x1d6ff90; 1 drivers -v0x1854140_0 .net "carryin", 0 0, L_0x1d78920; 1 drivers -v0x18541e0_0 .net "carryout", 0 0, L_0x1d78270; 1 drivers -v0x1863830_0 .net "carryouts", 7 0, L_0x1ebddc0; 1 drivers -v0x18638d0_0 .net "command", 7 0, v0x1d6daa0_0; 1 drivers -v0x18607f0_0 .net "result", 0 0, L_0x1d748d0; 1 drivers -v0x1860890_0 .net "results", 7 0, L_0x1d70d30; 1 drivers -v0x1835e00_0 .net "zero", 0 0, L_0x1d785d0; 1 drivers -LS_0x1d70d30_0_0 .concat8 [ 1 1 1 1], L_0x1d6f240, L_0x1d6fa20, L_0x1d6ff90, L_0x1d706e0; -LS_0x1d70d30_0_4 .concat8 [ 1 1 1 1], L_0x1d70890, L_0x1d70950, L_0x1d70ab0, L_0x1d70f60; -L_0x1d70d30 .concat8 [ 4 4 0 0], LS_0x1d70d30_0_0, LS_0x1d70d30_0_4; -LS_0x1ebddc0_0_0 .concat [ 1 1 1 1], L_0x1d6f5b0, L_0x1d6fe30, o0x7f7259356328, L_0x1d70530; -LS_0x1ebddc0_0_4 .concat [ 4 0 0 0], o0x7f7259356358; -L_0x1ebddc0 .concat [ 4 4 0 0], LS_0x1ebddc0_0_0, LS_0x1ebddc0_0_4; -S_0x19f34d0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1a14870; +L_0x1202350/d .functor NOT 1, L_0x120bed0, C4<0>, C4<0>, C4<0>; +L_0x1202350 .delay 1 (10000,10000,10000) L_0x1202350/d; +L_0x1202460/d .functor NOT 1, L_0x120c030, C4<0>, C4<0>, C4<0>; +L_0x1202460 .delay 1 (10000,10000,10000) L_0x1202460/d; +L_0x12036a0/d .functor XOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; +L_0x12036a0 .delay 1 (30000,30000,30000) L_0x12036a0/d; +L_0x2b0ab3d05018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1203df0/d .functor OR 1, L_0x2b0ab3d05018, L_0x2b0ab3d05060, C4<0>, C4<0>; +L_0x1203df0 .delay 1 (30000,30000,30000) L_0x1203df0/d; +L_0x1203ff0/d .functor AND 1, L_0x120bed0, L_0x120c030, C4<1>, C4<1>; +L_0x1203ff0 .delay 1 (30000,30000,30000) L_0x1203ff0/d; +L_0x12040b0/d .functor NAND 1, L_0x120bed0, L_0x120c030, C4<1>, C4<1>; +L_0x12040b0 .delay 1 (20000,20000,20000) L_0x12040b0/d; +L_0x1204210/d .functor XOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; +L_0x1204210 .delay 1 (20000,20000,20000) L_0x1204210/d; +L_0x12046c0/d .functor OR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; +L_0x12046c0 .delay 1 (30000,30000,30000) L_0x12046c0/d; +L_0x120bdd0/d .functor NOT 1, L_0x1208030, C4<0>, C4<0>, C4<0>; +L_0x120bdd0 .delay 1 (10000,10000,10000) L_0x120bdd0/d; +v0xc655e0_0 .net "A", 0 0, L_0x120bed0; 1 drivers +v0xc65680_0 .net "A_", 0 0, L_0x1202350; 1 drivers +v0xc74f90_0 .net "B", 0 0, L_0x120c030; 1 drivers +v0xc75030_0 .net "B_", 0 0, L_0x1202460; 1 drivers +v0xc74c00_0 .net *"_s12", 0 0, L_0x1203df0; 1 drivers +v0xc71f50_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05018; 1 drivers +v0xc71ff0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05060; 1 drivers +v0xc36e40_0 .net *"_s18", 0 0, L_0x1203ff0; 1 drivers +v0xc397b0_0 .net *"_s20", 0 0, L_0x12040b0; 1 drivers +v0xc47270_0 .net *"_s22", 0 0, L_0x1204210; 1 drivers +v0xc46e30_0 .net *"_s24", 0 0, L_0x12046c0; 1 drivers +o0x2b0ab3ca5328 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0xc44140_0 name=_s30 +o0x2b0ab3ca5358 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0xc53b50_0 name=_s32 +v0xc537c0_0 .net *"_s8", 0 0, L_0x12036a0; 1 drivers +v0xc50b10_0 .net "carryin", 0 0, L_0x120c120; 1 drivers +v0xc50bb0_0 .net "carryout", 0 0, L_0x120ba70; 1 drivers +v0xc15a10_0 .net "carryouts", 7 0, L_0x1352170; 1 drivers +v0xc15ab0_0 .net "command", 7 0, v0x12010b0_0; 1 drivers +v0xc25950_0 .net "result", 0 0, L_0x1208030; 1 drivers +v0xc259f0_0 .net "results", 7 0, L_0x1204490; 1 drivers +v0xc22c60_0 .net "zero", 0 0, L_0x120bdd0; 1 drivers +LS_0x1204490_0_0 .concat8 [ 1 1 1 1], L_0x12029a0, L_0x1203130, L_0x12036a0, L_0x1203df0; +LS_0x1204490_0_4 .concat8 [ 1 1 1 1], L_0x1203ff0, L_0x12040b0, L_0x1204210, L_0x12046c0; +L_0x1204490 .concat8 [ 4 4 0 0], LS_0x1204490_0_0, LS_0x1204490_0_4; +LS_0x1352170_0_0 .concat [ 1 1 1 1], L_0x1202cc0, L_0x1203540, o0x2b0ab3ca5328, L_0x1203c40; +LS_0x1352170_0_4 .concat [ 4 0 0 0], o0x2b0ab3ca5358; +L_0x1352170 .concat [ 4 4 0 0], LS_0x1352170_0_0, LS_0x1352170_0_4; +S_0xecc120 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xeed4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d6f5b0/d .functor OR 1, L_0x1d6eff0, L_0x1d6f420, C4<0>, C4<0>; -L_0x1d6f5b0 .delay 1 (30000,30000,30000) L_0x1d6f5b0/d; -v0x1b34410_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers -v0x1b344d0_0 .net "b", 0 0, L_0x1d78830; alias, 1 drivers -v0x1b30b00_0 .net "c1", 0 0, L_0x1d6eff0; 1 drivers -v0x1b306c0_0 .net "c2", 0 0, L_0x1d6f420; 1 drivers -v0x1b2d9d0_0 .net "carryin", 0 0, L_0x1d78920; alias, 1 drivers -v0x1b237b0_0 .net "carryout", 0 0, L_0x1d6f5b0; 1 drivers -v0x1b23850_0 .net "s1", 0 0, L_0x1d6eef0; 1 drivers -v0x1b26230_0 .net "sum", 0 0, L_0x1d6f240; 1 drivers -S_0x19d2120 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x19f34d0; +L_0x1202cc0/d .functor OR 1, L_0x1202750, L_0x1202b30, C4<0>, C4<0>; +L_0x1202cc0 .delay 1 (30000,30000,30000) L_0x1202cc0/d; +v0xf70aa0_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers +v0xf70b60_0 .net "b", 0 0, L_0x120c030; alias, 1 drivers +v0xf6ddb0_0 .net "c1", 0 0, L_0x1202750; 1 drivers +v0xf345c0_0 .net "c2", 0 0, L_0x1202b30; 1 drivers +v0xf33050_0 .net "carryin", 0 0, L_0x120c120; alias, 1 drivers +v0xf42e40_0 .net "carryout", 0 0, L_0x1202cc0; 1 drivers +v0xf42ee0_0 .net "s1", 0 0, L_0x1202650; 1 drivers +v0xf4fb30_0 .net "sum", 0 0, L_0x12029a0; 1 drivers +S_0xeaad90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xecc120; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d6eef0/d .functor XOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; -L_0x1d6eef0 .delay 1 (30000,30000,30000) L_0x1d6eef0/d; -L_0x1d6eff0/d .functor AND 1, L_0x1d786d0, L_0x1d78830, C4<1>, C4<1>; -L_0x1d6eff0 .delay 1 (30000,30000,30000) L_0x1d6eff0/d; -v0x1473f50_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers -v0x1b39690_0 .net "b", 0 0, L_0x1d78830; alias, 1 drivers -v0x1b392a0_0 .net "carryout", 0 0, L_0x1d6eff0; alias, 1 drivers -v0x1b38620_0 .net "sum", 0 0, L_0x1d6eef0; alias, 1 drivers -S_0x19b0d90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x19f34d0; +L_0x1202650/d .functor XOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; +L_0x1202650 .delay 1 (30000,30000,30000) L_0x1202650/d; +L_0x1202750/d .functor AND 1, L_0x120bed0, L_0x120c030, C4<1>, C4<1>; +L_0x1202750 .delay 1 (30000,30000,30000) L_0x1202750/d; +v0x90cb20_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers +v0xf91fc0_0 .net "b", 0 0, L_0x120c030; alias, 1 drivers +v0xf8f170_0 .net "carryout", 0 0, L_0x1202750; alias, 1 drivers +v0xf55940_0 .net "sum", 0 0, L_0x1202650; alias, 1 drivers +S_0xe899e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xecc120; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d6f240/d .functor XOR 1, L_0x1d6eef0, L_0x1d78920, C4<0>, C4<0>; -L_0x1d6f240 .delay 1 (30000,30000,30000) L_0x1d6f240/d; -L_0x1d6f420/d .functor AND 1, L_0x1d6eef0, L_0x1d78920, C4<1>, C4<1>; -L_0x1d6f420 .delay 1 (30000,30000,30000) L_0x1d6f420/d; -v0x1b38300_0 .net "a", 0 0, L_0x1d6eef0; alias, 1 drivers -v0x1b37610_0 .net "b", 0 0, L_0x1d78920; alias, 1 drivers -v0x1b376b0_0 .net "carryout", 0 0, L_0x1d6f420; alias, 1 drivers -v0x1b37280_0 .net "sum", 0 0, L_0x1d6f240; alias, 1 drivers -S_0x198f9e0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1a14870; +L_0x12029a0/d .functor XOR 1, L_0x1202650, L_0x120c120, C4<0>, C4<0>; +L_0x12029a0 .delay 1 (30000,30000,30000) L_0x12029a0/d; +L_0x1202b30/d .functor AND 1, L_0x1202650, L_0x120c120, C4<1>, C4<1>; +L_0x1202b30 .delay 1 (30000,30000,30000) L_0x1202b30/d; +v0xf64600_0 .net "a", 0 0, L_0x1202650; alias, 1 drivers +v0xf641c0_0 .net "b", 0 0, L_0x120c120; alias, 1 drivers +v0xf64260_0 .net "carryout", 0 0, L_0x1202b30; alias, 1 drivers +v0xf70ee0_0 .net "sum", 0 0, L_0x12029a0; alias, 1 drivers +S_0xd5e8d0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xeed4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1a556f0_0 .net "ands", 7 0, L_0x1d76310; 1 drivers -v0x1a17c20_0 .net "in", 7 0, L_0x1ebddc0; alias, 1 drivers -v0x1a17ce0_0 .net "out", 0 0, L_0x1d78270; alias, 1 drivers -v0x1a1a590_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b01920 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x198f9e0; +v0xe24c40_0 .net "ands", 7 0, L_0x1209a70; 1 drivers +v0xe24800_0 .net "in", 7 0, L_0x1352170; alias, 1 drivers +v0xe248c0_0 .net "out", 0 0, L_0x120ba70; alias, 1 drivers +v0xdf72b0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xfc0f60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xd5e8d0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1ac08f0_0 .net "A", 7 0, L_0x1ebddc0; alias, 1 drivers -v0x1ace200_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1acdd60_0 .net *"_s0", 0 0, L_0x1d74c30; 1 drivers -v0x1acde00_0 .net *"_s12", 0 0, L_0x1d755a0; 1 drivers -v0x1acb090_0 .net *"_s16", 0 0, L_0x1d75900; 1 drivers -v0x1adab00_0 .net *"_s20", 0 0, L_0x1d75c10; 1 drivers -v0x1ada770_0 .net *"_s24", 0 0, L_0x1d76000; 1 drivers -v0x1ad7ac0_0 .net *"_s28", 0 0, L_0x1d75f90; 1 drivers -v0x1a9caf0_0 .net *"_s4", 0 0, L_0x1d74f40; 1 drivers -v0x1a9f460_0 .net *"_s8", 0 0, L_0x1d75290; 1 drivers -v0x1aacd90_0 .net "out", 7 0, L_0x1d76310; alias, 1 drivers -L_0x1d74cf0 .part L_0x1ebddc0, 0, 1; -L_0x1d74e50 .part v0x1d6daa0_0, 0, 1; -L_0x1d75000 .part L_0x1ebddc0, 1, 1; -L_0x1d751f0 .part v0x1d6daa0_0, 1, 1; -L_0x1d75350 .part L_0x1ebddc0, 2, 1; -L_0x1d754b0 .part v0x1d6daa0_0, 2, 1; -L_0x1d75660 .part L_0x1ebddc0, 3, 1; -L_0x1d757c0 .part v0x1d6daa0_0, 3, 1; -L_0x1d759c0 .part L_0x1ebddc0, 4, 1; -L_0x1d75b20 .part v0x1d6daa0_0, 4, 1; -L_0x1d75c80 .part L_0x1ebddc0, 5, 1; -L_0x1d75ef0 .part v0x1d6daa0_0, 5, 1; -L_0x1d760c0 .part L_0x1ebddc0, 6, 1; -L_0x1d76220 .part v0x1d6daa0_0, 6, 1; -LS_0x1d76310_0_0 .concat8 [ 1 1 1 1], L_0x1d74c30, L_0x1d74f40, L_0x1d75290, L_0x1d755a0; -LS_0x1d76310_0_4 .concat8 [ 1 1 1 1], L_0x1d75900, L_0x1d75c10, L_0x1d76000, L_0x1d75f90; -L_0x1d76310 .concat8 [ 4 4 0 0], LS_0x1d76310_0_0, LS_0x1d76310_0_4; -L_0x1d766d0 .part L_0x1ebddc0, 7, 1; -L_0x1d768c0 .part v0x1d6daa0_0, 7, 1; -S_0x1b00380 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1b22cb0 .param/l "i" 0 4 54, +C4<00>; -L_0x1d74c30/d .functor AND 1, L_0x1d74cf0, L_0x1d74e50, C4<1>, C4<1>; -L_0x1d74c30 .delay 1 (30000,30000,30000) L_0x1d74c30/d; -v0x1b228d0_0 .net *"_s0", 0 0, L_0x1d74cf0; 1 drivers -v0x1b10a40_0 .net *"_s1", 0 0, L_0x1d74e50; 1 drivers -S_0x1ae0520 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1b10600 .param/l "i" 0 4 54, +C4<01>; -L_0x1d74f40/d .functor AND 1, L_0x1d75000, L_0x1d751f0, C4<1>, C4<1>; -L_0x1d74f40 .delay 1 (30000,30000,30000) L_0x1d74f40/d; -v0x1b106a0_0 .net *"_s0", 0 0, L_0x1d75000; 1 drivers -v0x1b0d930_0 .net *"_s1", 0 0, L_0x1d751f0; 1 drivers -S_0x1adef80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1b1d3f0 .param/l "i" 0 4 54, +C4<010>; -L_0x1d75290/d .functor AND 1, L_0x1d75350, L_0x1d754b0, C4<1>, C4<1>; -L_0x1d75290 .delay 1 (30000,30000,30000) L_0x1d75290/d; -v0x1b1cff0_0 .net *"_s0", 0 0, L_0x1d75350; 1 drivers -v0x1b1a340_0 .net *"_s1", 0 0, L_0x1d754b0; 1 drivers -S_0x1abf120 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1b1d0d0 .param/l "i" 0 4 54, +C4<011>; -L_0x1d755a0/d .functor AND 1, L_0x1d75660, L_0x1d757c0, C4<1>, C4<1>; -L_0x1d755a0 .delay 1 (30000,30000,30000) L_0x1d755a0/d; -v0x1ae08a0_0 .net *"_s0", 0 0, L_0x1d75660; 1 drivers -v0x1adf2c0_0 .net *"_s1", 0 0, L_0x1d757c0; 1 drivers -S_0x1abdb80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1ae1c80 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d75900/d .functor AND 1, L_0x1d759c0, L_0x1d75b20, C4<1>, C4<1>; -L_0x1d75900 .delay 1 (30000,30000,30000) L_0x1d75900/d; -v0x1aef5e0_0 .net *"_s0", 0 0, L_0x1d759c0; 1 drivers -v0x1aef1a0_0 .net *"_s1", 0 0, L_0x1d75b20; 1 drivers -S_0x1a9dd50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1aef6c0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d75c10/d .functor AND 1, L_0x1d75c80, L_0x1d75ef0, C4<1>, C4<1>; -L_0x1d75c10 .delay 1 (30000,30000,30000) L_0x1d75c10/d; -v0x1aec520_0 .net *"_s0", 0 0, L_0x1d75c80; 1 drivers -v0x1afbf00_0 .net *"_s1", 0 0, L_0x1d75ef0; 1 drivers -S_0x1a9c7b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1afbb70 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d76000/d .functor AND 1, L_0x1d760c0, L_0x1d76220, C4<1>, C4<1>; -L_0x1d76000 .delay 1 (30000,30000,30000) L_0x1d76000/d; -v0x1afbc30_0 .net *"_s0", 0 0, L_0x1d760c0; 1 drivers -v0x1af8ec0_0 .net *"_s1", 0 0, L_0x1d76220; 1 drivers -S_0x1a7c9d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b01920; - .timescale -9 -12; -P_0x1abdec0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d75f90/d .functor AND 1, L_0x1d766d0, L_0x1d768c0, C4<1>, C4<1>; -L_0x1d75f90 .delay 1 (30000,30000,30000) L_0x1d75f90/d; -v0x1abdf60_0 .net *"_s0", 0 0, L_0x1d766d0; 1 drivers -v0x1ac0830_0 .net *"_s1", 0 0, L_0x1d768c0; 1 drivers -S_0x1a7b430 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x198f9e0; +v0xee8f30_0 .net "A", 7 0, L_0x1352170; alias, 1 drivers +v0xebe530_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xebe1a0_0 .net *"_s0", 0 0, L_0x1208390; 1 drivers +v0xebe260_0 .net *"_s12", 0 0, L_0x1208d00; 1 drivers +v0xebb4f0_0 .net *"_s16", 0 0, L_0x1209060; 1 drivers +v0xecacb0_0 .net *"_s20", 0 0, L_0x1209370; 1 drivers +v0xeca870_0 .net *"_s24", 0 0, L_0x1209760; 1 drivers +v0xec7b80_0 .net *"_s28", 0 0, L_0x12096f0; 1 drivers +v0xe9d1b0_0 .net *"_s4", 0 0, L_0x12086a0; 1 drivers +v0xe9ce20_0 .net *"_s8", 0 0, L_0x12089f0; 1 drivers +v0xe9a170_0 .net "out", 7 0, L_0x1209a70; alias, 1 drivers +L_0x1208450 .part L_0x1352170, 0, 1; +L_0x12085b0 .part v0x12010b0_0, 0, 1; +L_0x1208760 .part L_0x1352170, 1, 1; +L_0x1208950 .part v0x12010b0_0, 1, 1; +L_0x1208ab0 .part L_0x1352170, 2, 1; +L_0x1208c10 .part v0x12010b0_0, 2, 1; +L_0x1208dc0 .part L_0x1352170, 3, 1; +L_0x1208f20 .part v0x12010b0_0, 3, 1; +L_0x1209120 .part L_0x1352170, 4, 1; +L_0x1209280 .part v0x12010b0_0, 4, 1; +L_0x12093e0 .part L_0x1352170, 5, 1; +L_0x1209650 .part v0x12010b0_0, 5, 1; +L_0x1209820 .part L_0x1352170, 6, 1; +L_0x1209980 .part v0x12010b0_0, 6, 1; +LS_0x1209a70_0_0 .concat8 [ 1 1 1 1], L_0x1208390, L_0x12086a0, L_0x12089f0, L_0x1208d00; +LS_0x1209a70_0_4 .concat8 [ 1 1 1 1], L_0x1209060, L_0x1209370, L_0x1209760, L_0x12096f0; +L_0x1209a70 .concat8 [ 4 4 0 0], LS_0x1209a70_0_0, LS_0x1209a70_0_4; +L_0x1209e30 .part L_0x1352170, 7, 1; +L_0x120a020 .part v0x12010b0_0, 7, 1; +S_0xf97d50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xf4f7d0 .param/l "i" 0 4 54, +C4<00>; +L_0x1208390/d .functor AND 1, L_0x1208450, L_0x12085b0, C4<1>, C4<1>; +L_0x1208390 .delay 1 (30000,30000,30000) L_0x1208390/d; +v0xf13220_0 .net *"_s0", 0 0, L_0x1208450; 1 drivers +v0xf11c20_0 .net *"_s1", 0 0, L_0x12085b0; 1 drivers +S_0xf967b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xf21ab0 .param/l "i" 0 4 54, +C4<01>; +L_0x12086a0/d .functor AND 1, L_0x1208760, L_0x1208950, C4<1>, C4<1>; +L_0x12086a0 .delay 1 (30000,30000,30000) L_0x12086a0/d; +v0xf21b50_0 .net *"_s0", 0 0, L_0x1208760; 1 drivers +v0xf1ef40_0 .net *"_s1", 0 0, L_0x1208950; 1 drivers +S_0xf769d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xf2e7a0 .param/l "i" 0 4 54, +C4<010>; +L_0x12089f0/d .functor AND 1, L_0x1208ab0, L_0x1208c10, C4<1>, C4<1>; +L_0x12089f0 .delay 1 (30000,30000,30000) L_0x12089f0/d; +v0xf2e840_0 .net *"_s0", 0 0, L_0x1208ab0; 1 drivers +v0xf2e360_0 .net *"_s1", 0 0, L_0x1208c10; 1 drivers +S_0xf75430 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xef1df0 .param/l "i" 0 4 54, +C4<011>; +L_0x1208d00/d .functor AND 1, L_0x1208dc0, L_0x1208f20, C4<1>, C4<1>; +L_0x1208d00 .delay 1 (30000,30000,30000) L_0x1208d00/d; +v0xef1eb0_0 .net *"_s0", 0 0, L_0x1208dc0; 1 drivers +v0xef08c0_0 .net *"_s1", 0 0, L_0x1208f20; 1 drivers +S_0xf55630 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xefdc40 .param/l "i" 0 4 54, +C4<0100>; +L_0x1209060/d .functor AND 1, L_0x1209120, L_0x1209280, C4<1>, C4<1>; +L_0x1209060 .delay 1 (30000,30000,30000) L_0x1209060/d; +v0xf0d400_0 .net *"_s0", 0 0, L_0x1209120; 1 drivers +v0xf0cfc0_0 .net *"_s1", 0 0, L_0x1209280; 1 drivers +S_0xf54090 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xf0d500 .param/l "i" 0 4 54, +C4<0101>; +L_0x1209370/d .functor AND 1, L_0x12093e0, L_0x1209650, C4<1>, C4<1>; +L_0x1209370 .delay 1 (30000,30000,30000) L_0x1209370/d; +v0xed0aa0_0 .net *"_s0", 0 0, L_0x12093e0; 1 drivers +v0xed0740_0 .net *"_s1", 0 0, L_0x1209650; 1 drivers +S_0xf342b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xedf860 .param/l "i" 0 4 54, +C4<0110>; +L_0x1209760/d .functor AND 1, L_0x1209820, L_0x1209980, C4<1>, C4<1>; +L_0x1209760 .delay 1 (30000,30000,30000) L_0x1209760/d; +v0xedf4b0_0 .net *"_s0", 0 0, L_0x1209820; 1 drivers +v0xedc800_0 .net *"_s1", 0 0, L_0x1209980; 1 drivers +S_0xf32d10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xfc0f60; + .timescale -9 -12; +P_0xedf940 .param/l "i" 0 4 54, +C4<0111>; +L_0x12096f0/d .functor AND 1, L_0x1209e30, L_0x120a020, C4<1>, C4<1>; +L_0x12096f0 .delay 1 (30000,30000,30000) L_0x12096f0/d; +v0xeec060_0 .net *"_s0", 0 0, L_0x1209e30; 1 drivers +v0xeebc20_0 .net *"_s1", 0 0, L_0x120a020; 1 drivers +S_0xf12e80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xd5e8d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d78270/d .functor OR 1, L_0x1d78330, L_0x1d784e0, C4<0>, C4<0>; -L_0x1d78270 .delay 1 (30000,30000,30000) L_0x1d78270/d; -v0x1a39050_0 .net *"_s10", 0 0, L_0x1d78330; 1 drivers -v0x1a3b9c0_0 .net *"_s12", 0 0, L_0x1d784e0; 1 drivers -v0x1a48e40_0 .net "in", 7 0, L_0x1d76310; alias, 1 drivers -v0x1a55b30_0 .net "ors", 1 0, L_0x1d78090; 1 drivers -v0x1a55bf0_0 .net "out", 0 0, L_0x1d78270; alias, 1 drivers -L_0x1d77500 .part L_0x1d76310, 0, 4; -L_0x1d78090 .concat8 [ 1 1 0 0], L_0x1d771f0, L_0x1d77e20; -L_0x1d781d0 .part L_0x1d76310, 4, 4; -L_0x1d78330 .part L_0x1d78090, 0, 1; -L_0x1d784e0 .part L_0x1d78090, 1, 1; -S_0x1a5b630 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1a7b430; +L_0x120ba70/d .functor OR 1, L_0x120bb30, L_0x120bce0, C4<0>, C4<0>; +L_0x120ba70 .delay 1 (30000,30000,30000) L_0x120ba70/d; +v0xe42e00_0 .net *"_s10", 0 0, L_0x120bb30; 1 drivers +v0xe185d0_0 .net *"_s12", 0 0, L_0x120bce0; 1 drivers +v0xe18240_0 .net "in", 7 0, L_0x1209a70; alias, 1 drivers +v0xe182e0_0 .net "ors", 1 0, L_0x120b890; 1 drivers +v0xe15590_0 .net "out", 0 0, L_0x120ba70; alias, 1 drivers +L_0x120ac60 .part L_0x1209a70, 0, 4; +L_0x120b890 .concat8 [ 1 1 0 0], L_0x120a950, L_0x120b580; +L_0x120b9d0 .part L_0x1209a70, 4, 4; +L_0x120bb30 .part L_0x120b890, 0, 1; +L_0x120bce0 .part L_0x120b890, 1, 1; +S_0xf118e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xf12e80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d769b0/d .functor OR 1, L_0x1d76a70, L_0x1d76bd0, C4<0>, C4<0>; -L_0x1d769b0 .delay 1 (30000,30000,30000) L_0x1d769b0/d; -L_0x1d76e00/d .functor OR 1, L_0x1d76f10, L_0x1d77070, C4<0>, C4<0>; -L_0x1d76e00 .delay 1 (30000,30000,30000) L_0x1d76e00/d; -L_0x1d771f0/d .functor OR 1, L_0x1d77260, L_0x1d77410, C4<0>, C4<0>; -L_0x1d771f0 .delay 1 (30000,30000,30000) L_0x1d771f0/d; -v0x1aac950_0 .net *"_s0", 0 0, L_0x1d769b0; 1 drivers -v0x1aa9c60_0 .net *"_s10", 0 0, L_0x1d76f10; 1 drivers -v0x1ab9700_0 .net *"_s12", 0 0, L_0x1d77070; 1 drivers -v0x1ab97c0_0 .net *"_s14", 0 0, L_0x1d77260; 1 drivers -v0x1ab9370_0 .net *"_s16", 0 0, L_0x1d77410; 1 drivers -v0x1ab6540_0 .net *"_s3", 0 0, L_0x1d76a70; 1 drivers -v0x1a7b770_0 .net *"_s5", 0 0, L_0x1d76bd0; 1 drivers -v0x1a7e0e0_0 .net *"_s6", 0 0, L_0x1d76e00; 1 drivers -v0x1a8b9c0_0 .net "in", 3 0, L_0x1d77500; 1 drivers -v0x1a8b580_0 .net "ors", 1 0, L_0x1d76d10; 1 drivers -v0x1a88890_0 .net "out", 0 0, L_0x1d771f0; 1 drivers -L_0x1d76a70 .part L_0x1d77500, 0, 1; -L_0x1d76bd0 .part L_0x1d77500, 1, 1; -L_0x1d76d10 .concat8 [ 1 1 0 0], L_0x1d769b0, L_0x1d76e00; -L_0x1d76f10 .part L_0x1d77500, 2, 1; -L_0x1d77070 .part L_0x1d77500, 3, 1; -L_0x1d77260 .part L_0x1d76d10, 0, 1; -L_0x1d77410 .part L_0x1d76d10, 1, 1; -S_0x1a5a090 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1a7b430; +L_0x120a110/d .functor OR 1, L_0x120a1d0, L_0x120a330, C4<0>, C4<0>; +L_0x120a110 .delay 1 (30000,30000,30000) L_0x120a110/d; +L_0x120a560/d .functor OR 1, L_0x120a670, L_0x120a7d0, C4<0>, C4<0>; +L_0x120a560 .delay 1 (30000,30000,30000) L_0x120a560/d; +L_0x120a950/d .functor OR 1, L_0x120a9c0, L_0x120ab70, C4<0>, C4<0>; +L_0x120a950 .delay 1 (30000,30000,30000) L_0x120a950/d; +v0xea9920_0 .net *"_s0", 0 0, L_0x120a110; 1 drivers +v0xea94e0_0 .net *"_s10", 0 0, L_0x120a670; 1 drivers +v0xea67f0_0 .net *"_s12", 0 0, L_0x120a7d0; 1 drivers +v0xea68b0_0 .net *"_s14", 0 0, L_0x120a9c0; 1 drivers +v0xe7be80_0 .net *"_s16", 0 0, L_0x120ab70; 1 drivers +v0xe7baf0_0 .net *"_s3", 0 0, L_0x120a1d0; 1 drivers +v0xe78e40_0 .net *"_s5", 0 0, L_0x120a330; 1 drivers +v0xe88570_0 .net *"_s6", 0 0, L_0x120a560; 1 drivers +v0xe88130_0 .net "in", 3 0, L_0x120ac60; 1 drivers +v0xe85440_0 .net "ors", 1 0, L_0x120a470; 1 drivers +v0xe5ab40_0 .net "out", 0 0, L_0x120a950; 1 drivers +L_0x120a1d0 .part L_0x120ac60, 0, 1; +L_0x120a330 .part L_0x120ac60, 1, 1; +L_0x120a470 .concat8 [ 1 1 0 0], L_0x120a110, L_0x120a560; +L_0x120a670 .part L_0x120ac60, 2, 1; +L_0x120a7d0 .part L_0x120ac60, 3, 1; +L_0x120a9c0 .part L_0x120a470, 0, 1; +L_0x120ab70 .part L_0x120a470, 1, 1; +S_0xef1ae0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xf12e80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d77630/d .functor OR 1, L_0x1d776a0, L_0x1d77800, C4<0>, C4<0>; -L_0x1d77630 .delay 1 (30000,30000,30000) L_0x1d77630/d; -L_0x1d77a30/d .functor OR 1, L_0x1d77b40, L_0x1d77ca0, C4<0>, C4<0>; -L_0x1d77a30 .delay 1 (30000,30000,30000) L_0x1d77a30/d; -L_0x1d77e20/d .functor OR 1, L_0x1d77e90, L_0x1d77ff0, C4<0>, C4<0>; -L_0x1d77e20 .delay 1 (30000,30000,30000) L_0x1d77e20/d; -v0x1a98330_0 .net *"_s0", 0 0, L_0x1d77630; 1 drivers -v0x1a97fa0_0 .net *"_s10", 0 0, L_0x1d77b40; 1 drivers -v0x1a95170_0 .net *"_s12", 0 0, L_0x1d77ca0; 1 drivers -v0x1a95230_0 .net *"_s14", 0 0, L_0x1d77e90; 1 drivers -v0x1a5a3d0_0 .net *"_s16", 0 0, L_0x1d77ff0; 1 drivers -v0x1a5cd40_0 .net *"_s3", 0 0, L_0x1d776a0; 1 drivers -v0x1a6a600_0 .net *"_s5", 0 0, L_0x1d77800; 1 drivers -v0x1a6a1c0_0 .net *"_s6", 0 0, L_0x1d77a30; 1 drivers -v0x1a76ee0_0 .net "in", 3 0, L_0x1d781d0; 1 drivers -v0x1a76aa0_0 .net "ors", 1 0, L_0x1d77940; 1 drivers -v0x1a73db0_0 .net "out", 0 0, L_0x1d77e20; 1 drivers -L_0x1d776a0 .part L_0x1d781d0, 0, 1; -L_0x1d77800 .part L_0x1d781d0, 1, 1; -L_0x1d77940 .concat8 [ 1 1 0 0], L_0x1d77630, L_0x1d77a30; -L_0x1d77b40 .part L_0x1d781d0, 2, 1; -L_0x1d77ca0 .part L_0x1d781d0, 3, 1; -L_0x1d77e90 .part L_0x1d77940, 0, 1; -L_0x1d77ff0 .part L_0x1d77940, 1, 1; -S_0x1a3a2b0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1a14870; +L_0x120ad90/d .functor OR 1, L_0x120ae00, L_0x120af60, C4<0>, C4<0>; +L_0x120ad90 .delay 1 (30000,30000,30000) L_0x120ad90/d; +L_0x120b190/d .functor OR 1, L_0x120b2a0, L_0x120b400, C4<0>, C4<0>; +L_0x120b190 .delay 1 (30000,30000,30000) L_0x120b190/d; +L_0x120b580/d .functor OR 1, L_0x120b5f0, L_0x120b7a0, C4<0>, C4<0>; +L_0x120b580 .delay 1 (30000,30000,30000) L_0x120b580/d; +v0xe5a7b0_0 .net *"_s0", 0 0, L_0x120ad90; 1 drivers +v0xe57b00_0 .net *"_s10", 0 0, L_0x120b2a0; 1 drivers +v0xe67240_0 .net *"_s12", 0 0, L_0x120b400; 1 drivers +v0xe67300_0 .net *"_s14", 0 0, L_0x120b5f0; 1 drivers +v0xe66e00_0 .net *"_s16", 0 0, L_0x120b7a0; 1 drivers +v0xe64110_0 .net *"_s3", 0 0, L_0x120ae00; 1 drivers +v0xe39850_0 .net *"_s5", 0 0, L_0x120af60; 1 drivers +v0xe394c0_0 .net *"_s6", 0 0, L_0x120b190; 1 drivers +v0xe36810_0 .net "in", 3 0, L_0x120b9d0; 1 drivers +v0xe45f30_0 .net "ors", 1 0, L_0x120b0a0; 1 drivers +v0xe45af0_0 .net "out", 0 0, L_0x120b580; 1 drivers +L_0x120ae00 .part L_0x120b9d0, 0, 1; +L_0x120af60 .part L_0x120b9d0, 1, 1; +L_0x120b0a0 .concat8 [ 1 1 0 0], L_0x120ad90, L_0x120b190; +L_0x120b2a0 .part L_0x120b9d0, 2, 1; +L_0x120b400 .part L_0x120b9d0, 3, 1; +L_0x120b5f0 .part L_0x120b0a0, 0, 1; +L_0x120b7a0 .part L_0x120b0a0, 1, 1; +S_0xef0540 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xeed4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x191b590_0 .net "ands", 7 0, L_0x1d728d0; 1 drivers -v0x192ac40_0 .net "in", 7 0, L_0x1d70d30; alias, 1 drivers -v0x192ad00_0 .net "out", 0 0, L_0x1d748d0; alias, 1 drivers -v0x192a800_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1a38d10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1a3a2b0; +v0xcd5a00_0 .net "ands", 7 0, L_0x1206030; 1 drivers +v0xc9ab10_0 .net "in", 7 0, L_0x1204490; alias, 1 drivers +v0xc9abd0_0 .net "out", 0 0, L_0x1208030; alias, 1 drivers +v0xcaaf00_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xf00ae0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xef0540; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x19f1c20_0 .net "A", 7 0, L_0x1d70d30; alias, 1 drivers -v0x19eef30_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x19c4530_0 .net *"_s0", 0 0, L_0x1d710c0; 1 drivers -v0x19c45f0_0 .net *"_s12", 0 0, L_0x1d71a80; 1 drivers -v0x19c41a0_0 .net *"_s16", 0 0, L_0x1d71de0; 1 drivers -v0x19c14f0_0 .net *"_s20", 0 0, L_0x1d72210; 1 drivers -v0x19d0cb0_0 .net *"_s24", 0 0, L_0x1d72540; 1 drivers -v0x19d0870_0 .net *"_s28", 0 0, L_0x1d724d0; 1 drivers -v0x19cdb80_0 .net *"_s4", 0 0, L_0x1d71460; 1 drivers -v0x19a31b0_0 .net *"_s8", 0 0, L_0x1d71770; 1 drivers -v0x19a2e20_0 .net "out", 7 0, L_0x1d728d0; alias, 1 drivers -L_0x1d711d0 .part L_0x1d70d30, 0, 1; -L_0x1d713c0 .part v0x1d6daa0_0, 0, 1; -L_0x1d71520 .part L_0x1d70d30, 1, 1; -L_0x1d71680 .part v0x1d6daa0_0, 1, 1; -L_0x1d71830 .part L_0x1d70d30, 2, 1; -L_0x1d71990 .part v0x1d6daa0_0, 2, 1; -L_0x1d71b40 .part L_0x1d70d30, 3, 1; -L_0x1d71ca0 .part v0x1d6daa0_0, 3, 1; -L_0x1d71ea0 .part L_0x1d70d30, 4, 1; -L_0x1d72110 .part v0x1d6daa0_0, 4, 1; -L_0x1d72280 .part L_0x1d70d30, 5, 1; -L_0x1d723e0 .part v0x1d6daa0_0, 5, 1; -L_0x1d72600 .part L_0x1d70d30, 6, 1; -L_0x1d72760 .part v0x1d6daa0_0, 6, 1; -LS_0x1d728d0_0_0 .concat8 [ 1 1 1 1], L_0x1d710c0, L_0x1d71460, L_0x1d71770, L_0x1d71a80; -LS_0x1d728d0_0_4 .concat8 [ 1 1 1 1], L_0x1d71de0, L_0x1d72210, L_0x1d72540, L_0x1d724d0; -L_0x1d728d0 .concat8 [ 4 4 0 0], LS_0x1d728d0_0_0, LS_0x1d728d0_0_4; -L_0x1d72c90 .part L_0x1d70d30, 7, 1; -L_0x1d72e80 .part v0x1d6daa0_0, 7, 1; -S_0x1a18e80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x1a7b850 .param/l "i" 0 4 54, +C4<00>; -L_0x1d710c0/d .functor AND 1, L_0x1d711d0, L_0x1d713c0, C4<1>, C4<1>; -L_0x1d710c0 .delay 1 (30000,30000,30000) L_0x1d710c0/d; -v0x1a27ab0_0 .net *"_s0", 0 0, L_0x1d711d0; 1 drivers -v0x1a24f40_0 .net *"_s1", 0 0, L_0x1d713c0; 1 drivers -S_0x1a178e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x1a8b660 .param/l "i" 0 4 54, +C4<01>; -L_0x1d71460/d .functor AND 1, L_0x1d71520, L_0x1d71680, C4<1>, C4<1>; -L_0x1d71460 .delay 1 (30000,30000,30000) L_0x1d71460/d; -v0x1a347a0_0 .net *"_s0", 0 0, L_0x1d71520; 1 drivers -v0x1a34360_0 .net *"_s1", 0 0, L_0x1d71680; 1 drivers -S_0x19f7ae0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x1a34460 .param/l "i" 0 4 54, +C4<010>; -L_0x1d71770/d .functor AND 1, L_0x1d71830, L_0x1d71990, C4<1>, C4<1>; -L_0x1d71770 .delay 1 (30000,30000,30000) L_0x1d71770/d; -v0x19f6880_0 .net *"_s0", 0 0, L_0x1d71830; 1 drivers -v0x19f6940_0 .net *"_s1", 0 0, L_0x1d71990; 1 drivers -S_0x19f6540 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x1a76b80 .param/l "i" 0 4 54, +C4<011>; -L_0x1d71a80/d .functor AND 1, L_0x1d71b40, L_0x1d71ca0, C4<1>, C4<1>; -L_0x1d71a80 .delay 1 (30000,30000,30000) L_0x1d71a80/d; -v0x19f91f0_0 .net *"_s0", 0 0, L_0x1d71b40; 1 drivers -v0x1a03ba0_0 .net *"_s1", 0 0, L_0x1d71ca0; 1 drivers -S_0x1a06ae0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x19f92d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d71de0/d .functor AND 1, L_0x1d71ea0, L_0x1d72110, C4<1>, C4<1>; -L_0x1d71de0 .delay 1 (30000,30000,30000) L_0x1d71de0/d; -v0x1a13400_0 .net *"_s0", 0 0, L_0x1d71ea0; 1 drivers -v0x1a12fc0_0 .net *"_s1", 0 0, L_0x1d72110; 1 drivers -S_0x1884ab0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x1a134e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d72210/d .functor AND 1, L_0x1d72280, L_0x1d723e0, C4<1>, C4<1>; -L_0x1d72210 .delay 1 (30000,30000,30000) L_0x1d72210/d; -v0x19d67b0_0 .net *"_s0", 0 0, L_0x1d72280; 1 drivers -v0x19d7ea0_0 .net *"_s1", 0 0, L_0x1d723e0; 1 drivers -S_0x17e3240 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x19e5840 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d72540/d .functor AND 1, L_0x1d72600, L_0x1d72760, C4<1>, C4<1>; -L_0x1d72540 .delay 1 (30000,30000,30000) L_0x1d72540/d; -v0x19e5900_0 .net *"_s0", 0 0, L_0x1d72600; 1 drivers -v0x19e54b0_0 .net *"_s1", 0 0, L_0x1d72760; 1 drivers -S_0x17e2f20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1a38d10; - .timescale -9 -12; -P_0x19e2800 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d724d0/d .functor AND 1, L_0x1d72c90, L_0x1d72e80, C4<1>, C4<1>; -L_0x1d724d0 .delay 1 (30000,30000,30000) L_0x1d724d0/d; -v0x19e28a0_0 .net *"_s0", 0 0, L_0x1d72c90; 1 drivers -v0x19f2080_0 .net *"_s1", 0 0, L_0x1d72e80; 1 drivers -S_0x17c3110 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1a3a2b0; +v0xd908a0_0 .net "A", 7 0, L_0x1204490; alias, 1 drivers +v0xd9fac0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xd9cf50_0 .net *"_s0", 0 0, L_0x1204820; 1 drivers +v0xd9d010_0 .net *"_s12", 0 0, L_0x12051e0; 1 drivers +v0xd72590_0 .net *"_s16", 0 0, L_0x1205540; 1 drivers +v0xd72200_0 .net *"_s20", 0 0, L_0x1205970; 1 drivers +v0xd6f550_0 .net *"_s24", 0 0, L_0x1205ca0; 1 drivers +v0xd7bc00_0 .net *"_s28", 0 0, L_0x1205c30; 1 drivers +v0xd51170_0 .net *"_s4", 0 0, L_0x1204bc0; 1 drivers +v0xd50de0_0 .net *"_s8", 0 0, L_0x1204ed0; 1 drivers +v0xd4e130_0 .net "out", 7 0, L_0x1206030; alias, 1 drivers +L_0x1204930 .part L_0x1204490, 0, 1; +L_0x1204b20 .part v0x12010b0_0, 0, 1; +L_0x1204c80 .part L_0x1204490, 1, 1; +L_0x1204de0 .part v0x12010b0_0, 1, 1; +L_0x1204f90 .part L_0x1204490, 2, 1; +L_0x12050f0 .part v0x12010b0_0, 2, 1; +L_0x12052a0 .part L_0x1204490, 3, 1; +L_0x1205400 .part v0x12010b0_0, 3, 1; +L_0x1205600 .part L_0x1204490, 4, 1; +L_0x1205870 .part v0x12010b0_0, 4, 1; +L_0x12059e0 .part L_0x1204490, 5, 1; +L_0x1205b40 .part v0x12010b0_0, 5, 1; +L_0x1205d60 .part L_0x1204490, 6, 1; +L_0x1205ec0 .part v0x12010b0_0, 6, 1; +LS_0x1206030_0_0 .concat8 [ 1 1 1 1], L_0x1204820, L_0x1204bc0, L_0x1204ed0, L_0x12051e0; +LS_0x1206030_0_4 .concat8 [ 1 1 1 1], L_0x1205540, L_0x1205970, L_0x1205ca0, L_0x1205c30; +L_0x1206030 .concat8 [ 4 4 0 0], LS_0x1206030_0_0, LS_0x1206030_0_4; +L_0x12063f0 .part L_0x1204490, 7, 1; +L_0x12065e0 .part v0x12010b0_0, 7, 1; +S_0xddf4b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xe9cf00 .param/l "i" 0 4 54, +C4<00>; +L_0x1204820/d .functor AND 1, L_0x1204930, L_0x1204b20, C4<1>, C4<1>; +L_0x1204820 .delay 1 (30000,30000,30000) L_0x1204820/d; +v0xdf6f20_0 .net *"_s0", 0 0, L_0x1204930; 1 drivers +v0xdf4270_0 .net *"_s1", 0 0, L_0x1204b20; 1 drivers +S_0xdbe150 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xdf4370 .param/l "i" 0 4 54, +C4<01>; +L_0x1204bc0/d .functor AND 1, L_0x1204c80, L_0x1204de0, C4<1>, C4<1>; +L_0x1204bc0 .delay 1 (30000,30000,30000) L_0x1204bc0/d; +v0xe03970_0 .net *"_s0", 0 0, L_0x1204c80; 1 drivers +v0xe03530_0 .net *"_s1", 0 0, L_0x1204de0; 1 drivers +S_0xd7eaf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xe78f20 .param/l "i" 0 4 54, +C4<010>; +L_0x1204ed0/d .functor AND 1, L_0x1204f90, L_0x12050f0, C4<1>, C4<1>; +L_0x1204ed0 .delay 1 (30000,30000,30000) L_0x1204ed0/d; +v0xe00840_0 .net *"_s0", 0 0, L_0x1204f90; 1 drivers +v0xe00900_0 .net *"_s1", 0 0, L_0x12050f0; 1 drivers +S_0xd5d330 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xe57be0 .param/l "i" 0 4 54, +C4<011>; +L_0x12051e0/d .functor AND 1, L_0x12052a0, L_0x1205400, C4<1>, C4<1>; +L_0x12051e0 .delay 1 (30000,30000,30000) L_0x12051e0/d; +v0xdd5f80_0 .net *"_s0", 0 0, L_0x12052a0; 1 drivers +v0xdd5bf0_0 .net *"_s1", 0 0, L_0x1205400; 1 drivers +S_0xc9a7d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xe395a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1205540/d .functor AND 1, L_0x1205600, L_0x1205870, C4<1>, C4<1>; +L_0x1205540 .delay 1 (30000,30000,30000) L_0x1205540/d; +v0xdd2f40_0 .net *"_s0", 0 0, L_0x1205600; 1 drivers +v0xde21b0_0 .net *"_s1", 0 0, L_0x1205870; 1 drivers +S_0xc7a9b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xe42ee0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1205970/d .functor AND 1, L_0x12059e0, L_0x1205b40, C4<1>, C4<1>; +L_0x1205970 .delay 1 (30000,30000,30000) L_0x1205970/d; +v0xdb4c40_0 .net *"_s0", 0 0, L_0x12059e0; 1 drivers +v0xdb48b0_0 .net *"_s1", 0 0, L_0x1205b40; 1 drivers +S_0xc79410 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xe03a50 .param/l "i" 0 4 54, +C4<0110>; +L_0x1205ca0/d .functor AND 1, L_0x1205d60, L_0x1205ec0, C4<1>, C4<1>; +L_0x1205ca0 .delay 1 (30000,30000,30000) L_0x1205ca0/d; +v0xdb1c00_0 .net *"_s0", 0 0, L_0x1205d60; 1 drivers +v0xdc0e50_0 .net *"_s1", 0 0, L_0x1205ec0; 1 drivers +S_0xc59570 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xf00ae0; + .timescale -9 -12; +P_0xdd3020 .param/l "i" 0 4 54, +C4<0111>; +L_0x1205c30/d .functor AND 1, L_0x12063f0, L_0x12065e0, C4<1>, C4<1>; +L_0x1205c30 .delay 1 (30000,30000,30000) L_0x1205c30/d; +v0xd938e0_0 .net *"_s0", 0 0, L_0x12063f0; 1 drivers +v0xd93550_0 .net *"_s1", 0 0, L_0x12065e0; 1 drivers +S_0xc57fd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xef0540; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d748d0/d .functor OR 1, L_0x1d74990, L_0x1d74b40, C4<0>, C4<0>; -L_0x1d748d0 .delay 1 (30000,30000,30000) L_0x1d748d0/d; -v0x194baf0_0 .net *"_s10", 0 0, L_0x1d74990; 1 drivers -v0x1948e00_0 .net *"_s12", 0 0, L_0x1d74b40; 1 drivers -v0x191e5d0_0 .net "in", 7 0, L_0x1d728d0; alias, 1 drivers -v0x191e670_0 .net "ors", 1 0, L_0x1d746f0; 1 drivers -v0x191e240_0 .net "out", 0 0, L_0x1d748d0; alias, 1 drivers -L_0x1d73ac0 .part L_0x1d728d0, 0, 4; -L_0x1d746f0 .concat8 [ 1 1 0 0], L_0x1d737b0, L_0x1d743e0; -L_0x1d74830 .part L_0x1d728d0, 4, 4; -L_0x1d74990 .part L_0x1d746f0, 0, 1; -L_0x1d74b40 .part L_0x1d746f0, 1, 1; -S_0x17c1b70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x17c3110; +L_0x1208030/d .functor OR 1, L_0x12080f0, L_0x12082a0, C4<0>, C4<0>; +L_0x1208030 .delay 1 (30000,30000,30000) L_0x1208030/d; +v0xccbe80_0 .net *"_s10", 0 0, L_0x12080f0; 1 drivers +v0xcc9190_0 .net *"_s12", 0 0, L_0x12082a0; 1 drivers +v0xcd8a40_0 .net "in", 7 0, L_0x1206030; alias, 1 drivers +v0xcd8ae0_0 .net "ors", 1 0, L_0x1207e50; 1 drivers +v0xcd86b0_0 .net "out", 0 0, L_0x1208030; alias, 1 drivers +L_0x1207220 .part L_0x1206030, 0, 4; +L_0x1207e50 .concat8 [ 1 1 0 0], L_0x1206f10, L_0x1207b40; +L_0x1207f90 .part L_0x1206030, 4, 4; +L_0x12080f0 .part L_0x1207e50, 0, 1; +L_0x12082a0 .part L_0x1207e50, 1, 1; +S_0xc380a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xc57fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d72f70/d .functor OR 1, L_0x1d73030, L_0x1d73190, C4<0>, C4<0>; -L_0x1d72f70 .delay 1 (30000,30000,30000) L_0x1d72f70/d; -L_0x1d733c0/d .functor OR 1, L_0x1d734d0, L_0x1d73630, C4<0>, C4<0>; -L_0x1d733c0 .delay 1 (30000,30000,30000) L_0x1d733c0/d; -L_0x1d737b0/d .functor OR 1, L_0x1d73820, L_0x1d739d0, C4<0>, C4<0>; -L_0x1d737b0 .delay 1 (30000,30000,30000) L_0x1d737b0/d; -v0x19a0170_0 .net *"_s0", 0 0, L_0x1d72f70; 1 drivers -v0x19af920_0 .net *"_s10", 0 0, L_0x1d734d0; 1 drivers -v0x19af4e0_0 .net *"_s12", 0 0, L_0x1d73630; 1 drivers -v0x19af5a0_0 .net *"_s14", 0 0, L_0x1d73820; 1 drivers -v0x19ac7f0_0 .net *"_s16", 0 0, L_0x1d739d0; 1 drivers -v0x1981e80_0 .net *"_s3", 0 0, L_0x1d73030; 1 drivers -v0x1981af0_0 .net *"_s5", 0 0, L_0x1d73190; 1 drivers -v0x197ee40_0 .net *"_s6", 0 0, L_0x1d733c0; 1 drivers -v0x198e570_0 .net "in", 3 0, L_0x1d73ac0; 1 drivers -v0x198e130_0 .net "ors", 1 0, L_0x1d732d0; 1 drivers -v0x198b440_0 .net "out", 0 0, L_0x1d737b0; 1 drivers -L_0x1d73030 .part L_0x1d73ac0, 0, 1; -L_0x1d73190 .part L_0x1d73ac0, 1, 1; -L_0x1d732d0 .concat8 [ 1 1 0 0], L_0x1d72f70, L_0x1d733c0; -L_0x1d734d0 .part L_0x1d73ac0, 2, 1; -L_0x1d73630 .part L_0x1d73ac0, 3, 1; -L_0x1d73820 .part L_0x1d732d0, 0, 1; -L_0x1d739d0 .part L_0x1d732d0, 1, 1; -S_0x17a1d30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x17c3110; +L_0x12066d0/d .functor OR 1, L_0x1206790, L_0x12068f0, C4<0>, C4<0>; +L_0x12066d0 .delay 1 (30000,30000,30000) L_0x12066d0/d; +L_0x1206b20/d .functor OR 1, L_0x1206c30, L_0x1206d90, C4<0>, C4<0>; +L_0x1206b20 .delay 1 (30000,30000,30000) L_0x1206b20/d; +L_0x1206f10/d .functor OR 1, L_0x1206f80, L_0x1207130, C4<0>, C4<0>; +L_0x1206f10 .delay 1 (30000,30000,30000) L_0x1206f10/d; +v0xd5a7e0_0 .net *"_s0", 0 0, L_0x12066d0; 1 drivers +v0xd2fde0_0 .net *"_s10", 0 0, L_0x1206c30; 1 drivers +v0xd2fa50_0 .net *"_s12", 0 0, L_0x1206d90; 1 drivers +v0xd2fb10_0 .net *"_s14", 0 0, L_0x1206f80; 1 drivers +v0xd2cc20_0 .net *"_s16", 0 0, L_0x1207130; 1 drivers +v0xd3c490_0 .net *"_s3", 0 0, L_0x1206790; 1 drivers +v0xd3c100_0 .net *"_s5", 0 0, L_0x12068f0; 1 drivers +v0xd39450_0 .net *"_s6", 0 0, L_0x1206b20; 1 drivers +v0xd1ce50_0 .net "in", 3 0, L_0x1207220; 1 drivers +v0xd0eab0_0 .net "ors", 1 0, L_0x1206a30; 1 drivers +v0xd0e720_0 .net "out", 0 0, L_0x1206f10; 1 drivers +L_0x1206790 .part L_0x1207220, 0, 1; +L_0x12068f0 .part L_0x1207220, 1, 1; +L_0x1206a30 .concat8 [ 1 1 0 0], L_0x12066d0, L_0x1206b20; +L_0x1206c30 .part L_0x1207220, 2, 1; +L_0x1206d90 .part L_0x1207220, 3, 1; +L_0x1206f80 .part L_0x1206a30, 0, 1; +L_0x1207130 .part L_0x1206a30, 1, 1; +S_0xc36b00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xc57fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d73bf0/d .functor OR 1, L_0x1d73c60, L_0x1d73dc0, C4<0>, C4<0>; -L_0x1d73bf0 .delay 1 (30000,30000,30000) L_0x1d73bf0/d; -L_0x1d73ff0/d .functor OR 1, L_0x1d74100, L_0x1d74260, C4<0>, C4<0>; -L_0x1d73ff0 .delay 1 (30000,30000,30000) L_0x1d73ff0/d; -L_0x1d743e0/d .functor OR 1, L_0x1d74450, L_0x1d74600, C4<0>, C4<0>; -L_0x1d743e0 .delay 1 (30000,30000,30000) L_0x1d743e0/d; -v0x1960b40_0 .net *"_s0", 0 0, L_0x1d73bf0; 1 drivers -v0x19607b0_0 .net *"_s10", 0 0, L_0x1d74100; 1 drivers -v0x195db00_0 .net *"_s12", 0 0, L_0x1d74260; 1 drivers -v0x195dbc0_0 .net *"_s14", 0 0, L_0x1d74450; 1 drivers -v0x196d240_0 .net *"_s16", 0 0, L_0x1d74600; 1 drivers -v0x196ce00_0 .net *"_s3", 0 0, L_0x1d73c60; 1 drivers -v0x196a110_0 .net *"_s5", 0 0, L_0x1d73dc0; 1 drivers -v0x193f850_0 .net *"_s6", 0 0, L_0x1d73ff0; 1 drivers -v0x193f4c0_0 .net "in", 3 0, L_0x1d74830; 1 drivers -v0x193c810_0 .net "ors", 1 0, L_0x1d73f00; 1 drivers -v0x194bf30_0 .net "out", 0 0, L_0x1d743e0; 1 drivers -L_0x1d73c60 .part L_0x1d74830, 0, 1; -L_0x1d73dc0 .part L_0x1d74830, 1, 1; -L_0x1d73f00 .concat8 [ 1 1 0 0], L_0x1d73bf0, L_0x1d73ff0; -L_0x1d74100 .part L_0x1d74830, 2, 1; -L_0x1d74260 .part L_0x1d74830, 3, 1; -L_0x1d74450 .part L_0x1d73f00, 0, 1; -L_0x1d74600 .part L_0x1d73f00, 1, 1; -S_0x17a0790 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1a14870; +L_0x1207350/d .functor OR 1, L_0x12073c0, L_0x1207520, C4<0>, C4<0>; +L_0x1207350 .delay 1 (30000,30000,30000) L_0x1207350/d; +L_0x1207750/d .functor OR 1, L_0x1207860, L_0x12079c0, C4<0>, C4<0>; +L_0x1207750 .delay 1 (30000,30000,30000) L_0x1207750/d; +L_0x1207b40/d .functor OR 1, L_0x1207bb0, L_0x1207d60, C4<0>, C4<0>; +L_0x1207b40 .delay 1 (30000,30000,30000) L_0x1207b40/d; +v0xd0b8a0_0 .net *"_s0", 0 0, L_0x1207350; 1 drivers +v0xd1b160_0 .net *"_s10", 0 0, L_0x1207860; 1 drivers +v0xd1add0_0 .net *"_s12", 0 0, L_0x12079c0; 1 drivers +v0xd1ae90_0 .net *"_s14", 0 0, L_0x1207bb0; 1 drivers +v0xd18120_0 .net *"_s16", 0 0, L_0x1207d60; 1 drivers +v0xced720_0 .net *"_s3", 0 0, L_0x12073c0; 1 drivers +v0xced390_0 .net *"_s5", 0 0, L_0x1207520; 1 drivers +v0xcea520_0 .net *"_s6", 0 0, L_0x1207750; 1 drivers +v0xcf9dd0_0 .net "in", 3 0, L_0x1207f90; 1 drivers +v0xcf9a40_0 .net "ors", 1 0, L_0x1207660; 1 drivers +v0xcf6d90_0 .net "out", 0 0, L_0x1207b40; 1 drivers +L_0x12073c0 .part L_0x1207f90, 0, 1; +L_0x1207520 .part L_0x1207f90, 1, 1; +L_0x1207660 .concat8 [ 1 1 0 0], L_0x1207350, L_0x1207750; +L_0x1207860 .part L_0x1207f90, 2, 1; +L_0x12079c0 .part L_0x1207f90, 3, 1; +L_0x1207bb0 .part L_0x1207660, 0, 1; +L_0x1207d60 .part L_0x1207660, 1, 1; +S_0xc16c70 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xeed4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -708,72 +718,72 @@ S_0x17a0790 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1a14870; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1d700f0/d .functor XNOR 1, L_0x1d786d0, L_0x1d78830, C4<0>, C4<0>; -L_0x1d700f0 .delay 1 (20000,20000,20000) L_0x1d700f0/d; -L_0x1d70360/d .functor AND 1, L_0x1d786d0, L_0x1d6ed00, C4<1>, C4<1>; -L_0x1d70360 .delay 1 (30000,30000,30000) L_0x1d70360/d; -L_0x1d703d0/d .functor AND 1, L_0x1d700f0, L_0x1d78920, C4<1>, C4<1>; -L_0x1d703d0 .delay 1 (30000,30000,30000) L_0x1d703d0/d; -L_0x1d70530/d .functor OR 1, L_0x1d703d0, L_0x1d70360, C4<0>, C4<0>; -L_0x1d70530 .delay 1 (30000,30000,30000) L_0x1d70530/d; -v0x18fd380_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers -v0x18fcf50_0 .net "a_", 0 0, L_0x1d6ebf0; alias, 1 drivers -v0x18fcff0_0 .net "b", 0 0, L_0x1d78830; alias, 1 drivers -v0x18fa2a0_0 .net "b_", 0 0, L_0x1d6ed00; alias, 1 drivers -v0x18fa340_0 .net "carryin", 0 0, L_0x1d78920; alias, 1 drivers -v0x1909960_0 .net "eq", 0 0, L_0x1d700f0; 1 drivers -v0x1909a00_0 .net "lt", 0 0, L_0x1d70360; 1 drivers -v0x1909520_0 .net "out", 0 0, L_0x1d70530; 1 drivers -v0x19095c0_0 .net "w0", 0 0, L_0x1d703d0; 1 drivers -S_0x17808d0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1a14870; +L_0x1203800/d .functor XNOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; +L_0x1203800 .delay 1 (20000,20000,20000) L_0x1203800/d; +L_0x1203a70/d .functor AND 1, L_0x120bed0, L_0x1202460, C4<1>, C4<1>; +L_0x1203a70 .delay 1 (30000,30000,30000) L_0x1203a70/d; +L_0x1203ae0/d .functor AND 1, L_0x1203800, L_0x120c120, C4<1>, C4<1>; +L_0x1203ae0 .delay 1 (30000,30000,30000) L_0x1203ae0/d; +L_0x1203c40/d .functor OR 1, L_0x1203ae0, L_0x1203a70, C4<0>, C4<0>; +L_0x1203c40 .delay 1 (30000,30000,30000) L_0x1203c40/d; +v0xcaab60_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers +v0xca7dd0_0 .net "a_", 0 0, L_0x1202350; alias, 1 drivers +v0xca7e70_0 .net "b", 0 0, L_0x120c030; alias, 1 drivers +v0xcb76f0_0 .net "b_", 0 0, L_0x1202460; alias, 1 drivers +v0xcb7790_0 .net "carryin", 0 0, L_0x120c120; alias, 1 drivers +v0xcb7360_0 .net "eq", 0 0, L_0x1203800; 1 drivers +v0xcb7400_0 .net "lt", 0 0, L_0x1203a70; 1 drivers +v0xcb46b0_0 .net "out", 0 0, L_0x1203c40; 1 drivers +v0xcb4750_0 .net "w0", 0 0, L_0x1203ae0; 1 drivers +S_0xc156d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xeed4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d6fe30/d .functor OR 1, L_0x1d6f870, L_0x1d6fd20, C4<0>, C4<0>; -L_0x1d6fe30 .delay 1 (30000,30000,30000) L_0x1d6fe30/d; -v0x18bac40_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers -v0x18ba8b0_0 .net "b", 0 0, L_0x1d6ed00; alias, 1 drivers -v0x18ba970_0 .net "c1", 0 0, L_0x1d6f870; 1 drivers -v0x18b7c00_0 .net "c2", 0 0, L_0x1d6fd20; 1 drivers -v0x18c42b0_0 .net "carryin", 0 0, L_0x1d78920; alias, 1 drivers -v0x18998a0_0 .net "carryout", 0 0, L_0x1d6fe30; 1 drivers -v0x1899940_0 .net "s1", 0 0, L_0x1d6f710; 1 drivers -v0x1899510_0 .net "sum", 0 0, L_0x1d6fa20; 1 drivers -S_0x177f330 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x17808d0; +L_0x1203540/d .functor OR 1, L_0x1202f80, L_0x1203430, C4<0>, C4<0>; +L_0x1203540 .delay 1 (30000,30000,30000) L_0x1203540/d; +v0xc95fc0_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers +v0xc93310_0 .net "b", 0 0, L_0x1202460; alias, 1 drivers +v0xc933d0_0 .net "c1", 0 0, L_0x1202f80; 1 drivers +v0xc59880_0 .net "c2", 0 0, L_0x1203430; 1 drivers +v0xc59920_0 .net "carryin", 0 0, L_0x120c120; alias, 1 drivers +v0xc687a0_0 .net "carryout", 0 0, L_0x1203540; 1 drivers +v0xc682d0_0 .net "s1", 0 0, L_0x1202e20; 1 drivers +v0xc68370_0 .net "sum", 0 0, L_0x1203130; 1 drivers +S_0xbf57f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xc156d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d6f710/d .functor XOR 1, L_0x1d786d0, L_0x1d6ed00, C4<0>, C4<0>; -L_0x1d6f710 .delay 1 (30000,30000,30000) L_0x1d6f710/d; -L_0x1d6f870/d .functor AND 1, L_0x1d786d0, L_0x1d6ed00, C4<1>, C4<1>; -L_0x1d6f870 .delay 1 (30000,30000,30000) L_0x1d6f870/d; -v0x18dbfa0_0 .net "a", 0 0, L_0x1d786d0; alias, 1 drivers -v0x18dc060_0 .net "b", 0 0, L_0x1d6ed00; alias, 1 drivers -v0x18dbc10_0 .net "carryout", 0 0, L_0x1d6f870; alias, 1 drivers -v0x18dbcb0_0 .net "sum", 0 0, L_0x1d6f710; alias, 1 drivers -S_0x175f440 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x17808d0; +L_0x1202e20/d .functor XOR 1, L_0x120bed0, L_0x1202460, C4<0>, C4<0>; +L_0x1202e20 .delay 1 (30000,30000,30000) L_0x1202e20/d; +L_0x1202f80/d .functor AND 1, L_0x120bed0, L_0x1202460, C4<1>, C4<1>; +L_0x1202f80 .delay 1 (30000,30000,30000) L_0x1202f80/d; +v0xc89b30_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers +v0xc89bf0_0 .net "b", 0 0, L_0x1202460; alias, 1 drivers +v0xc896f0_0 .net "carryout", 0 0, L_0x1202f80; alias, 1 drivers +v0xc89790_0 .net "sum", 0 0, L_0x1202e20; alias, 1 drivers +S_0xbf4250 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xc156d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d6fa20/d .functor XOR 1, L_0x1d6f710, L_0x1d78920, C4<0>, C4<0>; -L_0x1d6fa20 .delay 1 (30000,30000,30000) L_0x1d6fa20/d; -L_0x1d6fd20/d .functor AND 1, L_0x1d6f710, L_0x1d78920, C4<1>, C4<1>; -L_0x1d6fd20 .delay 1 (30000,30000,30000) L_0x1d6fd20/d; -v0x18d8f60_0 .net "a", 0 0, L_0x1d6f710; alias, 1 drivers -v0x18d9020_0 .net "b", 0 0, L_0x1d78920; alias, 1 drivers -v0x18e81b0_0 .net "carryout", 0 0, L_0x1d6fd20; alias, 1 drivers -v0x18e8250_0 .net "sum", 0 0, L_0x1d6fa20; alias, 1 drivers -S_0x175dea0 .scope generate, "alu_slices[1]" "alu_slices[1]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1948ee0 .param/l "i" 0 3 37, +C4<01>; -S_0x173dee0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x175dea0; +L_0x1203130/d .functor XOR 1, L_0x1202e20, L_0x120c120, C4<0>, C4<0>; +L_0x1203130 .delay 1 (30000,30000,30000) L_0x1203130/d; +L_0x1203430/d .functor AND 1, L_0x1202e20, L_0x120c120, C4<1>, C4<1>; +L_0x1203430 .delay 1 (30000,30000,30000) L_0x1203430/d; +v0xc86a00_0 .net "a", 0 0, L_0x1202e20; alias, 1 drivers +v0xc86ac0_0 .net "b", 0 0, L_0x120c120; alias, 1 drivers +v0xc96350_0 .net "carryout", 0 0, L_0x1203430; alias, 1 drivers +v0xc963f0_0 .net "sum", 0 0, L_0x1203130; alias, 1 drivers +S_0xbd4310 .scope generate, "alu_slices[1]" "alu_slices[1]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0xced470 .param/l "i" 0 3 41, +C4<01>; +S_0xbd2d70 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xbd4310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -782,445 +792,445 @@ S_0x173dee0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x175dea0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1d789c0/d .functor NOT 1, L_0x1d82330, C4<0>, C4<0>, C4<0>; -L_0x1d789c0 .delay 1 (10000,10000,10000) L_0x1d789c0/d; -L_0x1d78ad0/d .functor NOT 1, L_0x1d82490, C4<0>, C4<0>, C4<0>; -L_0x1d78ad0 .delay 1 (10000,10000,10000) L_0x1d78ad0/d; -L_0x1d79b00/d .functor XOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; -L_0x1d79b00 .delay 1 (30000,30000,30000) L_0x1d79b00/d; -L_0x7f72592da0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d7a1b0/d .functor OR 1, L_0x7f72592da0a8, L_0x7f72592da0f0, C4<0>, C4<0>; -L_0x1d7a1b0 .delay 1 (30000,30000,30000) L_0x1d7a1b0/d; -L_0x1d7a3b0/d .functor AND 1, L_0x1d82330, L_0x1d82490, C4<1>, C4<1>; -L_0x1d7a3b0 .delay 1 (30000,30000,30000) L_0x1d7a3b0/d; -L_0x1d7a470/d .functor NAND 1, L_0x1d82330, L_0x1d82490, C4<1>, C4<1>; -L_0x1d7a470 .delay 1 (20000,20000,20000) L_0x1d7a470/d; -L_0x1d7a5d0/d .functor XOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; -L_0x1d7a5d0 .delay 1 (20000,20000,20000) L_0x1d7a5d0/d; -L_0x1d7aa80/d .functor OR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; -L_0x1d7aa80 .delay 1 (30000,30000,30000) L_0x1d7aa80/d; -L_0x1d821e0/d .functor NOT 1, L_0x1d7e3f0, C4<0>, C4<0>, C4<0>; -L_0x1d821e0 .delay 1 (10000,10000,10000) L_0x1d821e0/d; -v0x19ef450_0 .net "A", 0 0, L_0x1d82330; 1 drivers -v0x19ef510_0 .net "A_", 0 0, L_0x1d789c0; 1 drivers -v0x19ce0a0_0 .net "B", 0 0, L_0x1d82490; 1 drivers -v0x19ce170_0 .net "B_", 0 0, L_0x1d78ad0; 1 drivers -v0x19acd10_0 .net *"_s12", 0 0, L_0x1d7a1b0; 1 drivers -v0x19ace00_0 .net/2s *"_s14", 0 0, L_0x7f72592da0a8; 1 drivers -v0x198b960_0 .net/2s *"_s16", 0 0, L_0x7f72592da0f0; 1 drivers -v0x198ba20_0 .net *"_s18", 0 0, L_0x1d7a3b0; 1 drivers -v0x196a630_0 .net *"_s20", 0 0, L_0x1d7a470; 1 drivers -v0x1949320_0 .net *"_s22", 0 0, L_0x1d7a5d0; 1 drivers -v0x1949400_0 .net *"_s24", 0 0, L_0x1d7aa80; 1 drivers -o0x7f7259358818 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1928030_0 name=_s30 -o0x7f7259358848 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1928110_0 name=_s32 -v0x1906d50_0 .net *"_s8", 0 0, L_0x1d79b00; 1 drivers -v0x1906e10_0 .net "carryin", 0 0, L_0x1d82530; 1 drivers -v0x18e8580_0 .net "carryout", 0 0, L_0x1d81e80; 1 drivers -v0x18e8620_0 .net "carryouts", 7 0, L_0x1ebed40; 1 drivers -v0x18c7200_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x18c72a0_0 .net "result", 0 0, L_0x1d7e3f0; 1 drivers -v0x18a5e50_0 .net "results", 7 0, L_0x1d7a850; 1 drivers -v0x1826c60_0 .net "zero", 0 0, L_0x1d821e0; 1 drivers -LS_0x1d7a850_0_0 .concat8 [ 1 1 1 1], L_0x1d78fa0, L_0x1d79600, L_0x1d79b00, L_0x1d7a1b0; -LS_0x1d7a850_0_4 .concat8 [ 1 1 1 1], L_0x1d7a3b0, L_0x1d7a470, L_0x1d7a5d0, L_0x1d7aa80; -L_0x1d7a850 .concat8 [ 4 4 0 0], LS_0x1d7a850_0_0, LS_0x1d7a850_0_4; -LS_0x1ebed40_0_0 .concat [ 1 1 1 1], L_0x1d792f0, L_0x1d799a0, o0x7f7259358818, L_0x1d7a000; -LS_0x1ebed40_0_4 .concat [ 4 0 0 0], o0x7f7259358848; -L_0x1ebed40 .concat [ 4 4 0 0], LS_0x1ebed40_0_0, LS_0x1ebed40_0_4; -S_0x173c940 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x173dee0; +L_0x120c1c0/d .functor NOT 1, L_0x12159e0, C4<0>, C4<0>, C4<0>; +L_0x120c1c0 .delay 1 (10000,10000,10000) L_0x120c1c0/d; +L_0x120c2d0/d .functor NOT 1, L_0x1215b40, C4<0>, C4<0>, C4<0>; +L_0x120c2d0 .delay 1 (10000,10000,10000) L_0x120c2d0/d; +L_0x120d320/d .functor XOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; +L_0x120d320 .delay 1 (30000,30000,30000) L_0x120d320/d; +L_0x2b0ab3d050a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d050f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x120d9d0/d .functor OR 1, L_0x2b0ab3d050a8, L_0x2b0ab3d050f0, C4<0>, C4<0>; +L_0x120d9d0 .delay 1 (30000,30000,30000) L_0x120d9d0/d; +L_0x120dbd0/d .functor AND 1, L_0x12159e0, L_0x1215b40, C4<1>, C4<1>; +L_0x120dbd0 .delay 1 (30000,30000,30000) L_0x120dbd0/d; +L_0x120dc90/d .functor NAND 1, L_0x12159e0, L_0x1215b40, C4<1>, C4<1>; +L_0x120dc90 .delay 1 (20000,20000,20000) L_0x120dc90/d; +L_0x120ddf0/d .functor XOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; +L_0x120ddf0 .delay 1 (20000,20000,20000) L_0x120ddf0/d; +L_0x120e2a0/d .functor OR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; +L_0x120e2a0 .delay 1 (30000,30000,30000) L_0x120e2a0/d; +L_0x12158e0/d .functor NOT 1, L_0x1211a70, C4<0>, C4<0>, C4<0>; +L_0x12158e0 .delay 1 (10000,10000,10000) L_0x12158e0/d; +v0xcc9750_0 .net "A", 0 0, L_0x12159e0; 1 drivers +v0xcb97d0_0 .net "A_", 0 0, L_0x120c1c0; 1 drivers +v0xcb9890_0 .net "B", 0 0, L_0x1215b40; 1 drivers +v0xcb9450_0 .net "B_", 0 0, L_0x120c2d0; 1 drivers +v0xcb94f0_0 .net *"_s12", 0 0, L_0x120d9d0; 1 drivers +v0xca82f0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d050a8; 1 drivers +v0xca83b0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d050f0; 1 drivers +v0xc98430_0 .net *"_s18", 0 0, L_0x120dbd0; 1 drivers +v0xc98510_0 .net *"_s20", 0 0, L_0x120dc90; 1 drivers +v0xc98160_0 .net *"_s22", 0 0, L_0x120ddf0; 1 drivers +v0xc86f20_0 .net *"_s24", 0 0, L_0x120e2a0; 1 drivers +o0x2b0ab3ca7818 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0xc87000_0 name=_s30 +o0x2b0ab3ca7848 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0xc77070_0 name=_s32 +v0xc77130_0 .net *"_s8", 0 0, L_0x120d320; 1 drivers +v0xc76cf0_0 .net "carryin", 0 0, L_0x1215be0; 1 drivers +v0xc76d90_0 .net "carryout", 0 0, L_0x1215580; 1 drivers +v0xc65b00_0 .net "carryouts", 7 0, L_0x13530f0; 1 drivers +v0xc65ba0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0xc558b0_0 .net "result", 0 0, L_0x1211a70; 1 drivers +v0xc559a0_0 .net "results", 7 0, L_0x120e070; 1 drivers +v0xc44660_0 .net "zero", 0 0, L_0x12158e0; 1 drivers +LS_0x120e070_0_0 .concat8 [ 1 1 1 1], L_0x120c7f0, L_0x120ce20, L_0x120d320, L_0x120d9d0; +LS_0x120e070_0_4 .concat8 [ 1 1 1 1], L_0x120dbd0, L_0x120dc90, L_0x120ddf0, L_0x120e2a0; +L_0x120e070 .concat8 [ 4 4 0 0], LS_0x120e070_0_0, LS_0x120e070_0_4; +LS_0x13530f0_0_0 .concat [ 1 1 1 1], L_0x120caa0, L_0x120d1c0, o0x2b0ab3ca7818, L_0x120d820; +LS_0x13530f0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ca7848; +L_0x13530f0 .concat [ 4 4 0 0], LS_0x13530f0_0_0, LS_0x13530f0_0_4; +S_0xbb2ed0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xbd2d70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d792f0/d .functor OR 1, L_0x1d78e20, L_0x1d79190, C4<0>, C4<0>; -L_0x1d792f0 .delay 1 (30000,30000,30000) L_0x1d792f0/d; -v0x18118d0_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers -v0x1811990_0 .net "b", 0 0, L_0x1d82490; alias, 1 drivers -v0x1821170_0 .net "c1", 0 0, L_0x1d78e20; 1 drivers -v0x1820de0_0 .net "c2", 0 0, L_0x1d79190; 1 drivers -v0x181e130_0 .net "carryin", 0 0, L_0x1d82530; alias, 1 drivers -v0x17f3660_0 .net "carryout", 0 0, L_0x1d792f0; 1 drivers -v0x17f3700_0 .net "s1", 0 0, L_0x1d78cc0; 1 drivers -v0x17f3220_0 .net "sum", 0 0, L_0x1d78fa0; 1 drivers -S_0x171ca50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x173c940; +L_0x120caa0/d .functor OR 1, L_0x120c580, L_0x120c940, C4<0>, C4<0>; +L_0x120caa0 .delay 1 (30000,30000,30000) L_0x120caa0/d; +v0xc017e0_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers +v0xc01880_0 .net "b", 0 0, L_0x1215b40; alias, 1 drivers +v0xc11250_0 .net "c1", 0 0, L_0x120c580; 1 drivers +v0xc10ec0_0 .net "c2", 0 0, L_0x120c940; 1 drivers +v0xc0e210_0 .net "carryin", 0 0, L_0x1215be0; alias, 1 drivers +v0xc0e2b0_0 .net "carryout", 0 0, L_0x120caa0; 1 drivers +v0xbd30b0_0 .net "s1", 0 0, L_0x120c4c0; 1 drivers +v0xbe34b0_0 .net "sum", 0 0, L_0x120c7f0; 1 drivers +S_0xbb1930 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xbb2ed0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d78cc0/d .functor XOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; -L_0x1d78cc0 .delay 1 (30000,30000,30000) L_0x1d78cc0/d; -L_0x1d78e20/d .functor AND 1, L_0x1d82330, L_0x1d82490, C4<1>, C4<1>; -L_0x1d78e20 .delay 1 (30000,30000,30000) L_0x1d78e20/d; -v0x1832c50_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers -v0x18424a0_0 .net "b", 0 0, L_0x1d82490; alias, 1 drivers -v0x1842560_0 .net "carryout", 0 0, L_0x1d78e20; alias, 1 drivers -v0x1842110_0 .net "sum", 0 0, L_0x1d78cc0; alias, 1 drivers -S_0x171b4b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x173c940; +L_0x120c4c0/d .functor XOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; +L_0x120c4c0 .delay 1 (30000,30000,30000) L_0x120c4c0/d; +L_0x120c580/d .functor AND 1, L_0x12159e0, L_0x1215b40, C4<1>, C4<1>; +L_0x120c580 .delay 1 (30000,30000,30000) L_0x120c580/d; +v0xc322f0_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers +v0xc2f640_0 .net "b", 0 0, L_0x1215b40; alias, 1 drivers +v0xc2f700_0 .net "carryout", 0 0, L_0x120c580; alias, 1 drivers +v0xbf4590_0 .net "sum", 0 0, L_0x120c4c0; alias, 1 drivers +S_0xb92720 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xbb2ed0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d78fa0/d .functor XOR 1, L_0x1d78cc0, L_0x1d82530, C4<0>, C4<0>; -L_0x1d78fa0 .delay 1 (30000,30000,30000) L_0x1d78fa0/d; -L_0x1d79190/d .functor AND 1, L_0x1d78cc0, L_0x1d82530, C4<1>, C4<1>; -L_0x1d79190 .delay 1 (30000,30000,30000) L_0x1d79190/d; -v0x183f4d0_0 .net "a", 0 0, L_0x1d78cc0; alias, 1 drivers -v0x1814ac0_0 .net "b", 0 0, L_0x1d82530; alias, 1 drivers -v0x1814b60_0 .net "carryout", 0 0, L_0x1d79190; alias, 1 drivers -v0x1814730_0 .net "sum", 0 0, L_0x1d78fa0; alias, 1 drivers -S_0x16fc260 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x173dee0; +L_0x120c7f0/d .functor XOR 1, L_0x120c4c0, L_0x1215be0, C4<0>, C4<0>; +L_0x120c7f0 .delay 1 (30000,30000,30000) L_0x120c7f0/d; +L_0x120c940/d .functor AND 1, L_0x120c4c0, L_0x1215be0, C4<1>, C4<1>; +L_0x120c940 .delay 1 (30000,30000,30000) L_0x120c940/d; +v0xc04910_0 .net "a", 0 0, L_0x120c4c0; alias, 1 drivers +v0xc049d0_0 .net "b", 0 0, L_0x1215be0; alias, 1 drivers +v0xc044d0_0 .net "carryout", 0 0, L_0x120c940; alias, 1 drivers +v0xc04570_0 .net "sum", 0 0, L_0x120c7f0; alias, 1 drivers +S_0xb91180 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xbd2d70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1708180_0 .net "ands", 7 0, L_0x1d7fe80; 1 drivers -v0x1717bd0_0 .net "in", 7 0, L_0x1ebed40; alias, 1 drivers -v0x1717c90_0 .net "out", 0 0, L_0x1d81e80; alias, 1 drivers -v0x1717840_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x16facc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x16fc260; +v0xdc2d00_0 .net "ands", 7 0, L_0x1213580; 1 drivers +v0xda20b0_0 .net "in", 7 0, L_0x13530f0; alias, 1 drivers +v0xda2170_0 .net "out", 0 0, L_0x1215580; alias, 1 drivers +v0xda1d20_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xf543d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xb91180; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1781fe0_0 .net "A", 7 0, L_0x1ebed40; alias, 1 drivers -v0x178fa50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x178fb10_0 .net *"_s0", 0 0, L_0x1d7e750; 1 drivers -v0x178f610_0 .net *"_s12", 0 0, L_0x1d7f110; 1 drivers -v0x178c920_0 .net *"_s16", 0 0, L_0x1d7f470; 1 drivers -v0x179c310_0 .net *"_s20", 0 0, L_0x1d7f780; 1 drivers -v0x179bf80_0 .net *"_s24", 0 0, L_0x1d7fb70; 1 drivers -v0x17992d0_0 .net *"_s28", 0 0, L_0x1d7fb00; 1 drivers -v0x175e1e0_0 .net *"_s4", 0 0, L_0x1d7ea60; 1 drivers -v0x1760b50_0 .net *"_s8", 0 0, L_0x1d7ee00; 1 drivers -v0x176e5a0_0 .net "out", 7 0, L_0x1d7fe80; alias, 1 drivers -L_0x1d7e810 .part L_0x1ebed40, 0, 1; -L_0x1d7e970 .part v0x1d6daa0_0, 0, 1; -L_0x1d7eb20 .part L_0x1ebed40, 1, 1; -L_0x1d7ed10 .part v0x1d6daa0_0, 1, 1; -L_0x1d7eec0 .part L_0x1ebed40, 2, 1; -L_0x1d7f020 .part v0x1d6daa0_0, 2, 1; -L_0x1d7f1d0 .part L_0x1ebed40, 3, 1; -L_0x1d7f330 .part v0x1d6daa0_0, 3, 1; -L_0x1d7f530 .part L_0x1ebed40, 4, 1; -L_0x1d7f690 .part v0x1d6daa0_0, 4, 1; -L_0x1d7f7f0 .part L_0x1ebed40, 5, 1; -L_0x1d7fa60 .part v0x1d6daa0_0, 5, 1; -L_0x1d7fc30 .part L_0x1ebed40, 6, 1; -L_0x1d7fd90 .part v0x1d6daa0_0, 6, 1; -LS_0x1d7fe80_0_0 .concat8 [ 1 1 1 1], L_0x1d7e750, L_0x1d7ea60, L_0x1d7ee00, L_0x1d7f110; -LS_0x1d7fe80_0_4 .concat8 [ 1 1 1 1], L_0x1d7f470, L_0x1d7f780, L_0x1d7fb70, L_0x1d7fb00; -L_0x1d7fe80 .concat8 [ 4 4 0 0], LS_0x1d7fe80_0_0, LS_0x1d7fe80_0_4; -L_0x1d80240 .part L_0x1ebed40, 7, 1; -L_0x1d80430 .part v0x1d6daa0_0, 7, 1; -S_0x1b2b170 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17f05d0 .param/l "i" 0 4 54, +C4<00>; -L_0x1d7e750/d .functor AND 1, L_0x1d7e810, L_0x1d7e970, C4<1>, C4<1>; -L_0x1d7e750 .delay 1 (30000,30000,30000) L_0x1d7e750/d; -v0x17ffdf0_0 .net *"_s0", 0 0, L_0x1d7e810; 1 drivers -v0x17ffeb0_0 .net *"_s1", 0 0, L_0x1d7e970; 1 drivers -S_0x1825700 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17ffab0 .param/l "i" 0 4 54, +C4<01>; -L_0x1d7ea60/d .functor AND 1, L_0x1d7eb20, L_0x1d7ed10, C4<1>, C4<1>; -L_0x1d7ea60 .delay 1 (30000,30000,30000) L_0x1d7ea60/d; -v0x17fcdb0_0 .net *"_s0", 0 0, L_0x1d7eb20; 1 drivers -v0x17c1eb0_0 .net *"_s1", 0 0, L_0x1d7ed10; 1 drivers -S_0x1a15580 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17fce90 .param/l "i" 0 4 54, +C4<010>; -L_0x1d7ee00/d .functor AND 1, L_0x1d7eec0, L_0x1d7f020, C4<1>, C4<1>; -L_0x1d7ee00 .delay 1 (30000,30000,30000) L_0x1d7ee00/d; -v0x17d2290_0 .net *"_s0", 0 0, L_0x1d7eec0; 1 drivers -v0x17d1e50_0 .net *"_s1", 0 0, L_0x1d7f020; 1 drivers -S_0x1a151f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17d1f30 .param/l "i" 0 4 54, +C4<011>; -L_0x1d7f110/d .functor AND 1, L_0x1d7f1d0, L_0x1d7f330, C4<1>, C4<1>; -L_0x1d7f110 .delay 1 (30000,30000,30000) L_0x1d7f110/d; -v0x17cf1f0_0 .net *"_s0", 0 0, L_0x1d7f1d0; 1 drivers -v0x17deaa0_0 .net *"_s1", 0 0, L_0x1d7f330; 1 drivers -S_0x1a14e40 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17de760 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d7f470/d .functor AND 1, L_0x1d7f530, L_0x1d7f690, C4<1>, C4<1>; -L_0x1d7f470 .delay 1 (30000,30000,30000) L_0x1d7f470/d; -v0x17dba60_0 .net *"_s0", 0 0, L_0x1d7f530; 1 drivers -v0x17a0ad0_0 .net *"_s1", 0 0, L_0x1d7f690; 1 drivers -S_0x19f41e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17a0bb0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d7f780/d .functor AND 1, L_0x1d7f7f0, L_0x1d7fa60, C4<1>, C4<1>; -L_0x1d7f780 .delay 1 (30000,30000,30000) L_0x1d7f780/d; -v0x17b0f20_0 .net *"_s0", 0 0, L_0x1d7f7f0; 1 drivers -v0x17b0a50_0 .net *"_s1", 0 0, L_0x1d7fa60; 1 drivers -S_0x19f3e50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17add80 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d7fb70/d .functor AND 1, L_0x1d7fc30, L_0x1d7fd90, C4<1>, C4<1>; -L_0x1d7fb70 .delay 1 (30000,30000,30000) L_0x1d7fb70/d; -v0x17bd6f0_0 .net *"_s0", 0 0, L_0x1d7fc30; 1 drivers -v0x17bd360_0 .net *"_s1", 0 0, L_0x1d7fd90; 1 drivers -S_0x19f3aa0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x16facc0; - .timescale -9 -12; -P_0x17bd7f0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d7fb00/d .functor AND 1, L_0x1d80240, L_0x1d80430, C4<1>, C4<1>; -L_0x1d7fb00 .delay 1 (30000,30000,30000) L_0x1d7fb00/d; -v0x17ba6b0_0 .net *"_s0", 0 0, L_0x1d80240; 1 drivers -v0x177f670_0 .net *"_s1", 0 0, L_0x1d80430; 1 drivers -S_0x19d2e30 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x16fc260; +v0xbaae90_0 .net "A", 7 0, L_0x13530f0; alias, 1 drivers +v0xda0ea0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xda0f60_0 .net *"_s0", 0 0, L_0x1211dd0; 1 drivers +v0xccc350_0 .net *"_s12", 0 0, L_0x1212790; 1 drivers +v0xd7fb00_0 .net *"_s16", 0 0, L_0x1212af0; 1 drivers +v0xecc6f0_0 .net *"_s20", 0 0, L_0x1212e00; 1 drivers +v0xecc7d0_0 .net *"_s24", 0 0, L_0x12131f0; 1 drivers +v0xeabaa0_0 .net *"_s28", 0 0, L_0x1213180; 1 drivers +v0xeabb80_0 .net *"_s4", 0 0, L_0x12120e0; 1 drivers +v0xeab710_0 .net *"_s8", 0 0, L_0x1212480; 1 drivers +v0xeab7f0_0 .net "out", 7 0, L_0x1213580; alias, 1 drivers +L_0x1211e90 .part L_0x13530f0, 0, 1; +L_0x1211ff0 .part v0x12010b0_0, 0, 1; +L_0x12121a0 .part L_0x13530f0, 1, 1; +L_0x1212390 .part v0x12010b0_0, 1, 1; +L_0x1212540 .part L_0x13530f0, 2, 1; +L_0x12126a0 .part v0x12010b0_0, 2, 1; +L_0x1212850 .part L_0x13530f0, 3, 1; +L_0x12129b0 .part v0x12010b0_0, 3, 1; +L_0x1212bb0 .part L_0x13530f0, 4, 1; +L_0x1212d10 .part v0x12010b0_0, 4, 1; +L_0x1212e70 .part L_0x13530f0, 5, 1; +L_0x12130e0 .part v0x12010b0_0, 5, 1; +L_0x12132b0 .part L_0x13530f0, 6, 1; +L_0x1213410 .part v0x12010b0_0, 6, 1; +LS_0x1213580_0_0 .concat8 [ 1 1 1 1], L_0x1211dd0, L_0x12120e0, L_0x1212480, L_0x1212790; +LS_0x1213580_0_4 .concat8 [ 1 1 1 1], L_0x1212af0, L_0x1212e00, L_0x12131f0, L_0x1213180; +L_0x1213580 .concat8 [ 4 4 0 0], LS_0x1213580_0_0, LS_0x1213580_0_4; +L_0x1213940 .part L_0x13530f0, 7, 1; +L_0x1213b30 .part v0x12010b0_0, 7, 1; +S_0xf0f580 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xc538a0 .param/l "i" 0 4 54, +C4<00>; +L_0x1211dd0/d .functor AND 1, L_0x1211e90, L_0x1211ff0, C4<1>, C4<1>; +L_0x1211dd0 .delay 1 (30000,30000,30000) L_0x1211dd0/d; +v0xbe3070_0 .net *"_s0", 0 0, L_0x1211e90; 1 drivers +v0xbe0380_0 .net *"_s1", 0 0, L_0x1211ff0; 1 drivers +S_0xf0f1f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbe0460 .param/l "i" 0 4 54, +C4<01>; +L_0x12120e0/d .functor AND 1, L_0x12121a0, L_0x1212390, C4<1>, C4<1>; +L_0x12120e0 .delay 1 (30000,30000,30000) L_0x12120e0/d; +v0xbefdd0_0 .net *"_s0", 0 0, L_0x12121a0; 1 drivers +v0xbefa40_0 .net *"_s1", 0 0, L_0x1212390; 1 drivers +S_0xf0ee40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbefb20 .param/l "i" 0 4 54, +C4<010>; +L_0x1212480/d .functor AND 1, L_0x1212540, L_0x12126a0, C4<1>, C4<1>; +L_0x1212480 .delay 1 (30000,30000,30000) L_0x1212480/d; +v0xbecde0_0 .net *"_s0", 0 0, L_0x1212540; 1 drivers +v0xbb1c70_0 .net *"_s1", 0 0, L_0x12126a0; 1 drivers +S_0xeee1e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbb45e0 .param/l "i" 0 4 54, +C4<011>; +L_0x1212790/d .functor AND 1, L_0x1212850, L_0x12129b0, C4<1>, C4<1>; +L_0x1212790 .delay 1 (30000,30000,30000) L_0x1212790/d; +v0xbc2020_0 .net *"_s0", 0 0, L_0x1212850; 1 drivers +v0xbc1be0_0 .net *"_s1", 0 0, L_0x12129b0; 1 drivers +S_0xeede50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbc1cc0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1212af0/d .functor AND 1, L_0x1212bb0, L_0x1212d10, C4<1>, C4<1>; +L_0x1212af0 .delay 1 (30000,30000,30000) L_0x1212af0/d; +v0xbbef80_0 .net *"_s0", 0 0, L_0x1212bb0; 1 drivers +v0xbce970_0 .net *"_s1", 0 0, L_0x1212d10; 1 drivers +S_0xeedaa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbce5e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1212e00/d .functor AND 1, L_0x1212e70, L_0x12130e0, C4<1>, C4<1>; +L_0x1212e00 .delay 1 (30000,30000,30000) L_0x1212e00/d; +v0xbcb930_0 .net *"_s0", 0 0, L_0x1212e70; 1 drivers +v0xb914c0_0 .net *"_s1", 0 0, L_0x12130e0; 1 drivers +S_0xecce30 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbcba10 .param/l "i" 0 4 54, +C4<0110>; +L_0x12131f0/d .functor AND 1, L_0x12132b0, L_0x1213410, C4<1>, C4<1>; +L_0x12131f0 .delay 1 (30000,30000,30000) L_0x12131f0/d; +v0xba16e0_0 .net *"_s0", 0 0, L_0x12132b0; 1 drivers +v0xba12a0_0 .net *"_s1", 0 0, L_0x1213410; 1 drivers +S_0xeccaa0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xf543d0; + .timescale -9 -12; +P_0xbae050 .param/l "i" 0 4 54, +C4<0111>; +L_0x1213180/d .functor AND 1, L_0x1213940, L_0x1213b30, C4<1>, C4<1>; +L_0x1213180 .delay 1 (30000,30000,30000) L_0x1213180/d; +v0xbae110_0 .net *"_s0", 0 0, L_0x1213940; 1 drivers +v0xbadcc0_0 .net *"_s1", 0 0, L_0x1213b30; 1 drivers +S_0xe8a6f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xb91180; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d81e80/d .functor OR 1, L_0x1d81f40, L_0x1d820f0, C4<0>, C4<0>; -L_0x1d81e80 .delay 1 (30000,30000,30000) L_0x1d81e80/d; -v0x16fb000_0 .net *"_s10", 0 0, L_0x1d81f40; 1 drivers -v0x16fd970_0 .net *"_s12", 0 0, L_0x1d820f0; 1 drivers -v0x170b2b0_0 .net "in", 7 0, L_0x1d7fe80; alias, 1 drivers -v0x170b350_0 .net "ors", 1 0, L_0x1d81ca0; 1 drivers -v0x170ae70_0 .net "out", 0 0, L_0x1d81e80; alias, 1 drivers -L_0x1d81070 .part L_0x1d7fe80, 0, 4; -L_0x1d81ca0 .concat8 [ 1 1 0 0], L_0x1d80d60, L_0x1d81990; -L_0x1d81de0 .part L_0x1d7fe80, 4, 4; -L_0x1d81f40 .part L_0x1d81ca0, 0, 1; -L_0x1d820f0 .part L_0x1d81ca0, 1, 1; -S_0x19d2aa0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x19d2e30; +L_0x1215580/d .functor OR 1, L_0x1215640, L_0x12157f0, C4<0>, C4<0>; +L_0x1215580 .delay 1 (30000,30000,30000) L_0x1215580/d; +v0xde40a0_0 .net *"_s10", 0 0, L_0x1215640; 1 drivers +v0xdc3440_0 .net *"_s12", 0 0, L_0x12157f0; 1 drivers +v0xdc3520_0 .net "in", 7 0, L_0x1213580; alias, 1 drivers +v0xdc30b0_0 .net "ors", 1 0, L_0x12153a0; 1 drivers +v0xdc3170_0 .net "out", 0 0, L_0x1215580; alias, 1 drivers +L_0x1214770 .part L_0x1213580, 0, 4; +L_0x12153a0 .concat8 [ 1 1 0 0], L_0x1214460, L_0x1215090; +L_0x12154e0 .part L_0x1213580, 4, 4; +L_0x1215640 .part L_0x12153a0, 0, 1; +L_0x12157f0 .part L_0x12153a0, 1, 1; +S_0xe8a360 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xe8a6f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d80520/d .functor OR 1, L_0x1d805e0, L_0x1d80740, C4<0>, C4<0>; -L_0x1d80520 .delay 1 (30000,30000,30000) L_0x1d80520/d; -L_0x1d80970/d .functor OR 1, L_0x1d80a80, L_0x1d80be0, C4<0>, C4<0>; -L_0x1d80970 .delay 1 (30000,30000,30000) L_0x1d80970/d; -L_0x1d80d60/d .functor OR 1, L_0x1d80dd0, L_0x1d80f80, C4<0>, C4<0>; -L_0x1d80d60 .delay 1 (30000,30000,30000) L_0x1d80d60/d; -v0x176e160_0 .net *"_s0", 0 0, L_0x1d80520; 1 drivers -v0x176b470_0 .net *"_s10", 0 0, L_0x1d80a80; 1 drivers -v0x177aeb0_0 .net *"_s12", 0 0, L_0x1d80be0; 1 drivers -v0x177af70_0 .net *"_s14", 0 0, L_0x1d80dd0; 1 drivers -v0x177ab20_0 .net *"_s16", 0 0, L_0x1d80f80; 1 drivers -v0x1777e70_0 .net *"_s3", 0 0, L_0x1d805e0; 1 drivers -v0x173e1f0_0 .net *"_s5", 0 0, L_0x1d80740; 1 drivers -v0x174d0f0_0 .net *"_s6", 0 0, L_0x1d80970; 1 drivers -v0x174ccb0_0 .net "in", 3 0, L_0x1d81070; 1 drivers -v0x1749fc0_0 .net "ors", 1 0, L_0x1d80880; 1 drivers -v0x1759a20_0 .net "out", 0 0, L_0x1d80d60; 1 drivers -L_0x1d805e0 .part L_0x1d81070, 0, 1; -L_0x1d80740 .part L_0x1d81070, 1, 1; -L_0x1d80880 .concat8 [ 1 1 0 0], L_0x1d80520, L_0x1d80970; -L_0x1d80a80 .part L_0x1d81070, 2, 1; -L_0x1d80be0 .part L_0x1d81070, 3, 1; -L_0x1d80dd0 .part L_0x1d80880, 0, 1; -L_0x1d80f80 .part L_0x1d80880, 1, 1; -S_0x19d26f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x19d2e30; +L_0x1213c20/d .functor OR 1, L_0x1213ce0, L_0x1213e40, C4<0>, C4<0>; +L_0x1213c20 .delay 1 (30000,30000,30000) L_0x1213c20/d; +L_0x1214070/d .functor OR 1, L_0x1214180, L_0x12142e0, C4<0>, C4<0>; +L_0x1214070 .delay 1 (30000,30000,30000) L_0x1214070/d; +L_0x1214460/d .functor OR 1, L_0x12144d0, L_0x1214680, C4<0>, C4<0>; +L_0x1214460 .delay 1 (30000,30000,30000) L_0x1214460/d; +v0xe89fb0_0 .net *"_s0", 0 0, L_0x1213c20; 1 drivers +v0xe693c0_0 .net *"_s10", 0 0, L_0x1214180; 1 drivers +v0xe694a0_0 .net *"_s12", 0 0, L_0x12142e0; 1 drivers +v0xe69030_0 .net *"_s14", 0 0, L_0x12144d0; 1 drivers +v0xe690f0_0 .net *"_s16", 0 0, L_0x1214680; 1 drivers +v0xe68c80_0 .net *"_s3", 0 0, L_0x1213ce0; 1 drivers +v0xe68d40_0 .net *"_s5", 0 0, L_0x1213e40; 1 drivers +v0xe480d0_0 .net *"_s6", 0 0, L_0x1214070; 1 drivers +v0xe47d20_0 .net "in", 3 0, L_0x1214770; 1 drivers +v0xe47e00_0 .net "ors", 1 0, L_0x1213f80; 1 drivers +v0xe479b0_0 .net "out", 0 0, L_0x1214460; 1 drivers +L_0x1213ce0 .part L_0x1214770, 0, 1; +L_0x1213e40 .part L_0x1214770, 1, 1; +L_0x1213f80 .concat8 [ 1 1 0 0], L_0x1213c20, L_0x1214070; +L_0x1214180 .part L_0x1214770, 2, 1; +L_0x12142e0 .part L_0x1214770, 3, 1; +L_0x12144d0 .part L_0x1213f80, 0, 1; +L_0x1214680 .part L_0x1213f80, 1, 1; +S_0xe26dc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xe8a6f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d811a0/d .functor OR 1, L_0x1d81210, L_0x1d81370, C4<0>, C4<0>; -L_0x1d811a0 .delay 1 (30000,30000,30000) L_0x1d811a0/d; -L_0x1d815a0/d .functor OR 1, L_0x1d816b0, L_0x1d81810, C4<0>, C4<0>; -L_0x1d815a0 .delay 1 (30000,30000,30000) L_0x1d815a0/d; -L_0x1d81990/d .functor OR 1, L_0x1d81a00, L_0x1d81bb0, C4<0>, C4<0>; -L_0x1d81990 .delay 1 (30000,30000,30000) L_0x1d81990/d; -v0x1759690_0 .net *"_s0", 0 0, L_0x1d811a0; 1 drivers -v0x17569e0_0 .net *"_s10", 0 0, L_0x1d816b0; 1 drivers -v0x171b7f0_0 .net *"_s12", 0 0, L_0x1d81810; 1 drivers -v0x171b8b0_0 .net *"_s14", 0 0, L_0x1d81a00; 1 drivers -v0x171e160_0 .net *"_s16", 0 0, L_0x1d81bb0; 1 drivers -v0x172bc10_0 .net *"_s3", 0 0, L_0x1d81210; 1 drivers -v0x172b7d0_0 .net *"_s5", 0 0, L_0x1d81370; 1 drivers -v0x1728ae0_0 .net *"_s6", 0 0, L_0x1d815a0; 1 drivers -v0x1738540_0 .net "in", 3 0, L_0x1d81de0; 1 drivers -v0x17381b0_0 .net "ors", 1 0, L_0x1d814b0; 1 drivers -v0x1735500_0 .net "out", 0 0, L_0x1d81990; 1 drivers -L_0x1d81210 .part L_0x1d81de0, 0, 1; -L_0x1d81370 .part L_0x1d81de0, 1, 1; -L_0x1d814b0 .concat8 [ 1 1 0 0], L_0x1d811a0, L_0x1d815a0; -L_0x1d816b0 .part L_0x1d81de0, 2, 1; -L_0x1d81810 .part L_0x1d81de0, 3, 1; -L_0x1d81a00 .part L_0x1d814b0, 0, 1; -L_0x1d81bb0 .part L_0x1d814b0, 1, 1; -S_0x19b1aa0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x173dee0; +L_0x12148a0/d .functor OR 1, L_0x1214910, L_0x1214a70, C4<0>, C4<0>; +L_0x12148a0 .delay 1 (30000,30000,30000) L_0x12148a0/d; +L_0x1214ca0/d .functor OR 1, L_0x1214db0, L_0x1214f10, C4<0>, C4<0>; +L_0x1214ca0 .delay 1 (30000,30000,30000) L_0x1214ca0/d; +L_0x1215090/d .functor OR 1, L_0x1215100, L_0x12152b0, C4<0>, C4<0>; +L_0x1215090 .delay 1 (30000,30000,30000) L_0x1215090/d; +v0xe26a70_0 .net *"_s0", 0 0, L_0x12148a0; 1 drivers +v0xe26680_0 .net *"_s10", 0 0, L_0x1214db0; 1 drivers +v0xe26760_0 .net *"_s12", 0 0, L_0x1214f10; 1 drivers +v0xe05af0_0 .net *"_s14", 0 0, L_0x1215100; 1 drivers +v0xe05bd0_0 .net *"_s16", 0 0, L_0x12152b0; 1 drivers +v0xe057a0_0 .net *"_s3", 0 0, L_0x1214910; 1 drivers +v0xe053b0_0 .net *"_s5", 0 0, L_0x1214a70; 1 drivers +v0xe05490_0 .net *"_s6", 0 0, L_0x1214ca0; 1 drivers +v0xde47a0_0 .net "in", 3 0, L_0x12154e0; 1 drivers +v0xde4410_0 .net "ors", 1 0, L_0x1214bb0; 1 drivers +v0xde44f0_0 .net "out", 0 0, L_0x1215090; 1 drivers +L_0x1214910 .part L_0x12154e0, 0, 1; +L_0x1214a70 .part L_0x12154e0, 1, 1; +L_0x1214bb0 .concat8 [ 1 1 0 0], L_0x12148a0, L_0x1214ca0; +L_0x1214db0 .part L_0x12154e0, 2, 1; +L_0x1214f10 .part L_0x12154e0, 3, 1; +L_0x1215100 .part L_0x1214bb0, 0, 1; +L_0x12152b0 .part L_0x1214bb0, 1, 1; +S_0xda1970 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xbd2d70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1acb590_0 .net "ands", 7 0, L_0x1d7c3f0; 1 drivers -v0x1acb650_0 .net "in", 7 0, L_0x1d7a850; alias, 1 drivers -v0x1abb7e0_0 .net "out", 0 0, L_0x1d7e3f0; alias, 1 drivers -v0x1abb880_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x19b1710 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x19b1aa0; +v0xe00d60_0 .net "ands", 7 0, L_0x120fb80; 1 drivers +v0xdc6ed0_0 .net "in", 7 0, L_0x120e070; alias, 1 drivers +v0xdc6f90_0 .net "out", 0 0, L_0x1211a70; alias, 1 drivers +v0xde2570_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xd80d10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xda1970; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x18c9420_0 .net "A", 7 0, L_0x1d7a850; alias, 1 drivers -v0x18c9090_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x18c9150_0 .net *"_s0", 0 0, L_0x1d7abe0; 1 drivers -v0x18c8ce0_0 .net *"_s12", 0 0, L_0x1d7b5a0; 1 drivers -v0x18c8dc0_0 .net *"_s16", 0 0, L_0x1d7b900; 1 drivers -v0x18a8070_0 .net *"_s20", 0 0, L_0x1d7bd30; 1 drivers -v0x18a8150_0 .net *"_s24", 0 0, L_0x1d7c060; 1 drivers -v0x18a7ce0_0 .net *"_s28", 0 0, L_0x1d7bff0; 1 drivers -v0x18a7dc0_0 .net *"_s4", 0 0, L_0x1d7af80; 1 drivers -v0x18a7a00_0 .net *"_s8", 0 0, L_0x1d7b290; 1 drivers -v0x1886cd0_0 .net "out", 7 0, L_0x1d7c3f0; alias, 1 drivers -L_0x1d7acf0 .part L_0x1d7a850, 0, 1; -L_0x1d7aee0 .part v0x1d6daa0_0, 0, 1; -L_0x1d7b040 .part L_0x1d7a850, 1, 1; -L_0x1d7b1a0 .part v0x1d6daa0_0, 1, 1; -L_0x1d7b350 .part L_0x1d7a850, 2, 1; -L_0x1d7b4b0 .part v0x1d6daa0_0, 2, 1; -L_0x1d7b660 .part L_0x1d7a850, 3, 1; -L_0x1d7b7c0 .part v0x1d6daa0_0, 3, 1; -L_0x1d7b9c0 .part L_0x1d7a850, 4, 1; -L_0x1d7bc30 .part v0x1d6daa0_0, 4, 1; -L_0x1d7bda0 .part L_0x1d7a850, 5, 1; -L_0x1d7bf00 .part v0x1d6daa0_0, 5, 1; -L_0x1d7c120 .part L_0x1d7a850, 6, 1; -L_0x1d7c280 .part v0x1d6daa0_0, 6, 1; -LS_0x1d7c3f0_0_0 .concat8 [ 1 1 1 1], L_0x1d7abe0, L_0x1d7af80, L_0x1d7b290, L_0x1d7b5a0; -LS_0x1d7c3f0_0_4 .concat8 [ 1 1 1 1], L_0x1d7b900, L_0x1d7bd30, L_0x1d7c060, L_0x1d7bff0; -L_0x1d7c3f0 .concat8 [ 4 4 0 0], LS_0x1d7c3f0_0_0, LS_0x1d7c3f0_0_4; -L_0x1d7c7b0 .part L_0x1d7a850, 7, 1; -L_0x1d7c9a0 .part v0x1d6daa0_0, 7, 1; -S_0x19b1360 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x176e240 .param/l "i" 0 4 54, +C4<00>; -L_0x1d7abe0/d .functor AND 1, L_0x1d7acf0, L_0x1d7aee0, C4<1>, C4<1>; -L_0x1d7abe0 .delay 1 (30000,30000,30000) L_0x1d7abe0/d; -v0x1714b90_0 .net *"_s0", 0 0, L_0x1d7acf0; 1 drivers -v0x19906f0_0 .net *"_s1", 0 0, L_0x1d7aee0; 1 drivers -S_0x1990360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x1777f50 .param/l "i" 0 4 54, +C4<01>; -L_0x1d7af80/d .functor AND 1, L_0x1d7b040, L_0x1d7b1a0, C4<1>, C4<1>; -L_0x1d7af80 .delay 1 (30000,30000,30000) L_0x1d7af80/d; -v0x19907d0_0 .net *"_s0", 0 0, L_0x1d7b040; 1 drivers -v0x198ffb0_0 .net *"_s1", 0 0, L_0x1d7b1a0; 1 drivers -S_0x196f3c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x1759770 .param/l "i" 0 4 54, +C4<010>; -L_0x1d7b290/d .functor AND 1, L_0x1d7b350, L_0x1d7b4b0, C4<1>, C4<1>; -L_0x1d7b290 .delay 1 (30000,30000,30000) L_0x1d7b290/d; -v0x1990090_0 .net *"_s0", 0 0, L_0x1d7b350; 1 drivers -v0x196f030_0 .net *"_s1", 0 0, L_0x1d7b4b0; 1 drivers -S_0x196ec80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x172b8b0 .param/l "i" 0 4 54, +C4<011>; -L_0x1d7b5a0/d .functor AND 1, L_0x1d7b660, L_0x1d7b7c0, C4<1>, C4<1>; -L_0x1d7b5a0 .delay 1 (30000,30000,30000) L_0x1d7b5a0/d; -v0x196f110_0 .net *"_s0", 0 0, L_0x1d7b660; 1 drivers -v0x194e0b0_0 .net *"_s1", 0 0, L_0x1d7b7c0; 1 drivers -S_0x194dd20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x16fda50 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d7b900/d .functor AND 1, L_0x1d7b9c0, L_0x1d7bc30, C4<1>, C4<1>; -L_0x1d7b900 .delay 1 (30000,30000,30000) L_0x1d7b900/d; -v0x194e190_0 .net *"_s0", 0 0, L_0x1d7b9c0; 1 drivers -v0x194d990_0 .net *"_s1", 0 0, L_0x1d7bc30; 1 drivers -S_0x192cdc0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x192ca30 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d7bd30/d .functor AND 1, L_0x1d7bda0, L_0x1d7bf00, C4<1>, C4<1>; -L_0x1d7bd30 .delay 1 (30000,30000,30000) L_0x1d7bd30/d; -v0x192caf0_0 .net *"_s0", 0 0, L_0x1d7bda0; 1 drivers -v0x192c6a0_0 .net *"_s1", 0 0, L_0x1d7bf00; 1 drivers -S_0x190baf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x190b760 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d7c060/d .functor AND 1, L_0x1d7c120, L_0x1d7c280, C4<1>, C4<1>; -L_0x1d7c060 .delay 1 (30000,30000,30000) L_0x1d7c060/d; -v0x190b820_0 .net *"_s0", 0 0, L_0x1d7c120; 1 drivers -v0x190b3d0_0 .net *"_s1", 0 0, L_0x1d7c280; 1 drivers -S_0x18ea7a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x19b1710; - .timescale -9 -12; -P_0x18ea410 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d7bff0/d .functor AND 1, L_0x1d7c7b0, L_0x1d7c9a0, C4<1>, C4<1>; -L_0x1d7bff0 .delay 1 (30000,30000,30000) L_0x1d7bff0/d; -v0x18ea4d0_0 .net *"_s0", 0 0, L_0x1d7c7b0; 1 drivers -v0x18ea080_0 .net *"_s1", 0 0, L_0x1d7c9a0; 1 drivers -S_0x1886940 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x19b1aa0; +v0xf73190_0 .net "A", 7 0, L_0x120e070; alias, 1 drivers +v0xf72d70_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xf619f0_0 .net *"_s0", 0 0, L_0x120e400; 1 drivers +v0xf61ab0_0 .net *"_s12", 0 0, L_0x120ee10; 1 drivers +v0xf6e2d0_0 .net *"_s16", 0 0, L_0x120f170; 1 drivers +v0xf51cf0_0 .net *"_s20", 0 0, L_0x120f540; 1 drivers +v0xf51dd0_0 .net *"_s24", 0 0, L_0x120f870; 1 drivers +v0xf51970_0 .net *"_s28", 0 0, L_0x120f800; 1 drivers +v0xf51a50_0 .net *"_s4", 0 0, L_0x120e7f0; 1 drivers +v0xf432c0_0 .net *"_s8", 0 0, L_0x120eb00; 1 drivers +v0xf40670_0 .net "out", 7 0, L_0x120fb80; alias, 1 drivers +L_0x120e510 .part L_0x120e070, 0, 1; +L_0x120e700 .part v0x12010b0_0, 0, 1; +L_0x120e8b0 .part L_0x120e070, 1, 1; +L_0x120ea10 .part v0x12010b0_0, 1, 1; +L_0x120ebc0 .part L_0x120e070, 2, 1; +L_0x120ed20 .part v0x12010b0_0, 2, 1; +L_0x120eed0 .part L_0x120e070, 3, 1; +L_0x120f030 .part v0x12010b0_0, 3, 1; +L_0x120f230 .part L_0x120e070, 4, 1; +L_0x120f4a0 .part v0x12010b0_0, 4, 1; +L_0x120f5b0 .part L_0x120e070, 5, 1; +L_0x120f710 .part v0x12010b0_0, 5, 1; +L_0x120f930 .part L_0x120e070, 6, 1; +L_0x120fa90 .part v0x12010b0_0, 6, 1; +LS_0x120fb80_0_0 .concat8 [ 1 1 1 1], L_0x120e400, L_0x120e7f0, L_0x120eb00, L_0x120ee10; +LS_0x120fb80_0_4 .concat8 [ 1 1 1 1], L_0x120f170, L_0x120f540, L_0x120f870, L_0x120f800; +L_0x120fb80 .concat8 [ 4 4 0 0], LS_0x120fb80_0_0, LS_0x120fb80_0_4; +L_0x120ff40 .part L_0x120e070, 7, 1; +L_0x1210130 .part v0x12010b0_0, 7, 1; +S_0xd805d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xd5f930 .param/l "i" 0 4 54, +C4<00>; +L_0x120e400/d .functor AND 1, L_0x120e510, L_0x120e700, C4<1>, C4<1>; +L_0x120e400 .delay 1 (30000,30000,30000) L_0x120e400/d; +v0xd5fa10_0 .net *"_s0", 0 0, L_0x120e510; 1 drivers +v0xd5f5a0_0 .net *"_s1", 0 0, L_0x120e700; 1 drivers +S_0xd5f1f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xd5f6b0 .param/l "i" 0 4 54, +C4<01>; +L_0x120e7f0/d .functor AND 1, L_0x120e8b0, L_0x120ea10, C4<1>, C4<1>; +L_0x120e7f0 .delay 1 (30000,30000,30000) L_0x120e7f0/d; +v0xd3e5d0_0 .net *"_s0", 0 0, L_0x120e8b0; 1 drivers +v0xd3e1d0_0 .net *"_s1", 0 0, L_0x120ea10; 1 drivers +S_0xd3de20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xd1d190 .param/l "i" 0 4 54, +C4<010>; +L_0x120eb00/d .functor AND 1, L_0x120ebc0, L_0x120ed20, C4<1>, C4<1>; +L_0x120eb00 .delay 1 (30000,30000,30000) L_0x120eb00/d; +v0xd1d250_0 .net *"_s0", 0 0, L_0x120ebc0; 1 drivers +v0xc58310_0 .net *"_s1", 0 0, L_0x120ed20; 1 drivers +S_0xfd2680 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xc58440 .param/l "i" 0 4 54, +C4<011>; +L_0x120ee10/d .functor AND 1, L_0x120eed0, L_0x120f030, C4<1>, C4<1>; +L_0x120ee10 .delay 1 (30000,30000,30000) L_0x120ee10/d; +v0xbf0d40_0 .net *"_s0", 0 0, L_0x120eed0; 1 drivers +v0xfcf810_0 .net *"_s1", 0 0, L_0x120f030; 1 drivers +S_0xfc1490 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xfcf940 .param/l "i" 0 4 54, +C4<0100>; +L_0x120f170/d .functor AND 1, L_0x120f230, L_0x120f4a0, C4<1>, C4<1>; +L_0x120f170 .delay 1 (30000,30000,30000) L_0x120f170/d; +v0xfc7f40_0 .net *"_s0", 0 0, L_0x120f230; 1 drivers +v0xfcac20_0 .net *"_s1", 0 0, L_0x120f4a0; 1 drivers +S_0xfc41d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xfcad00 .param/l "i" 0 4 54, +C4<0101>; +L_0x120f540/d .functor AND 1, L_0x120f5b0, L_0x120f710, C4<1>, C4<1>; +L_0x120f540 .delay 1 (30000,30000,30000) L_0x120f540/d; +v0xfa4180_0 .net *"_s0", 0 0, L_0x120f5b0; 1 drivers +v0xfa4240_0 .net *"_s1", 0 0, L_0x120f710; 1 drivers +S_0xfb0a60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xf94480 .param/l "i" 0 4 54, +C4<0110>; +L_0x120f870/d .functor AND 1, L_0x120f930, L_0x120fa90, C4<1>, C4<1>; +L_0x120f870 .delay 1 (30000,30000,30000) L_0x120f870/d; +v0xf94090_0 .net *"_s0", 0 0, L_0x120f930; 1 drivers +v0xf94170_0 .net *"_s1", 0 0, L_0x120fa90; 1 drivers +S_0xf82db0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xd80d10; + .timescale -9 -12; +P_0xf8f6b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x120f800/d .functor AND 1, L_0x120ff40, L_0x1210130, C4<1>, C4<1>; +L_0x120f800 .delay 1 (30000,30000,30000) L_0x120f800/d; +v0xf8f770_0 .net *"_s0", 0 0, L_0x120ff40; 1 drivers +v0xf730b0_0 .net *"_s1", 0 0, L_0x1210130; 1 drivers +S_0xf4cf20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xda1970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d7e3f0/d .functor OR 1, L_0x1d7e4b0, L_0x1d7e660, C4<0>, C4<0>; -L_0x1d7e3f0 .delay 1 (30000,30000,30000) L_0x1d7e3f0/d; -v0x1aec9d0_0 .net *"_s10", 0 0, L_0x1d7e4b0; 1 drivers -v0x1aecab0_0 .net *"_s12", 0 0, L_0x1d7e660; 1 drivers -v0x1adcbe0_0 .net "in", 7 0, L_0x1d7c3f0; alias, 1 drivers -v0x1adcc80_0 .net "ors", 1 0, L_0x1d7e210; 1 drivers -v0x1adc860_0 .net "out", 0 0, L_0x1d7e3f0; alias, 1 drivers -L_0x1d7d5e0 .part L_0x1d7c3f0, 0, 4; -L_0x1d7e210 .concat8 [ 1 1 0 0], L_0x1d7d2d0, L_0x1d7df00; -L_0x1d7e350 .part L_0x1d7c3f0, 4, 4; -L_0x1d7e4b0 .part L_0x1d7e210, 0, 1; -L_0x1d7e660 .part L_0x1d7e210, 1, 1; -S_0x18658f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1886940; +L_0x1211a70/d .functor OR 1, L_0x1211b30, L_0x1211ce0, C4<0>, C4<0>; +L_0x1211a70 .delay 1 (30000,30000,30000) L_0x1211a70/d; +v0xe09580_0 .net *"_s10", 0 0, L_0x1211b30; 1 drivers +v0xe09660_0 .net *"_s12", 0 0, L_0x1211ce0; 1 drivers +v0xe22030_0 .net "in", 7 0, L_0x120fb80; alias, 1 drivers +v0xe220d0_0 .net "ors", 1 0, L_0x1211890; 1 drivers +v0xde8230_0 .net "out", 0 0, L_0x1211a70; alias, 1 drivers +L_0x1210d70 .part L_0x120fb80, 0, 4; +L_0x1211890 .concat8 [ 1 1 0 0], L_0x1210a60, L_0x1211580; +L_0x12119d0 .part L_0x120fb80, 4, 4; +L_0x1211b30 .part L_0x1211890, 0, 1; +L_0x1211ce0 .part L_0x1211890, 1, 1; +S_0xf30970 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xf4cf20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d7ca90/d .functor OR 1, L_0x1d7cb50, L_0x1d7ccb0, C4<0>, C4<0>; -L_0x1d7ca90 .delay 1 (30000,30000,30000) L_0x1d7ca90/d; -L_0x1d7cee0/d .functor OR 1, L_0x1d7cff0, L_0x1d7d150, C4<0>, C4<0>; -L_0x1d7cee0 .delay 1 (30000,30000,30000) L_0x1d7cee0/d; -L_0x1d7d2d0/d .functor OR 1, L_0x1d7d340, L_0x1d7d4f0, C4<0>, C4<0>; -L_0x1d7d2d0 .delay 1 (30000,30000,30000) L_0x1d7d2d0/d; -v0x1865560_0 .net *"_s0", 0 0, L_0x1d7ca90; 1 drivers -v0x18651b0_0 .net *"_s10", 0 0, L_0x1d7cff0; 1 drivers -v0x1865290_0 .net *"_s12", 0 0, L_0x1d7d150; 1 drivers -v0x1844530_0 .net *"_s14", 0 0, L_0x1d7d340; 1 drivers -v0x1844610_0 .net *"_s16", 0 0, L_0x1d7d4f0; 1 drivers -v0x18441a0_0 .net *"_s3", 0 0, L_0x1d7cb50; 1 drivers -v0x1844280_0 .net *"_s5", 0 0, L_0x1d7ccb0; 1 drivers -v0x1843df0_0 .net *"_s6", 0 0, L_0x1d7cee0; 1 drivers -v0x1843ed0_0 .net "in", 3 0, L_0x1d7d5e0; 1 drivers -v0x173cd50_0 .net "ors", 1 0, L_0x1d7cdf0; 1 drivers -v0x1b31c00_0 .net "out", 0 0, L_0x1d7d2d0; 1 drivers -L_0x1d7cb50 .part L_0x1d7d5e0, 0, 1; -L_0x1d7ccb0 .part L_0x1d7d5e0, 1, 1; -L_0x1d7cdf0 .concat8 [ 1 1 0 0], L_0x1d7ca90, L_0x1d7cee0; -L_0x1d7cff0 .part L_0x1d7d5e0, 2, 1; -L_0x1d7d150 .part L_0x1d7d5e0, 3, 1; -L_0x1d7d340 .part L_0x1d7cdf0, 0, 1; -L_0x1d7d4f0 .part L_0x1d7cdf0, 1, 1; -S_0x1b34930 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1886940; +L_0x1210220/d .functor OR 1, L_0x12102e0, L_0x1210440, C4<0>, C4<0>; +L_0x1210220 .delay 1 (30000,30000,30000) L_0x1210220/d; +L_0x1210670/d .functor OR 1, L_0x1210780, L_0x12108e0, C4<0>, C4<0>; +L_0x1210670 .delay 1 (30000,30000,30000) L_0x1210670/d; +L_0x1210a60/d .functor OR 1, L_0x1210ad0, L_0x1210c80, C4<0>, C4<0>; +L_0x1210a60 .delay 1 (30000,30000,30000) L_0x1210a60/d; +v0xf305f0_0 .net *"_s0", 0 0, L_0x1210220; 1 drivers +v0xf306f0_0 .net *"_s10", 0 0, L_0x1210780; 1 drivers +v0xf21e80_0 .net *"_s12", 0 0, L_0x12108e0; 1 drivers +v0xf21f40_0 .net *"_s14", 0 0, L_0x1210ad0; 1 drivers +v0xf2bb90_0 .net *"_s16", 0 0, L_0x1210c80; 1 drivers +v0xf0a7f0_0 .net *"_s3", 0 0, L_0x12102e0; 1 drivers +v0xf0a8d0_0 .net *"_s5", 0 0, L_0x1210440; 1 drivers +v0xee9450_0 .net *"_s6", 0 0, L_0x1210670; 1 drivers +v0xee9530_0 .net "in", 3 0, L_0x1210d70; 1 drivers +v0xeaf5e0_0 .net "ors", 1 0, L_0x1210580; 1 drivers +v0xec80a0_0 .net "out", 0 0, L_0x1210a60; 1 drivers +L_0x12102e0 .part L_0x1210d70, 0, 1; +L_0x1210440 .part L_0x1210d70, 1, 1; +L_0x1210580 .concat8 [ 1 1 0 0], L_0x1210220, L_0x1210670; +L_0x1210780 .part L_0x1210d70, 2, 1; +L_0x12108e0 .part L_0x1210d70, 3, 1; +L_0x1210ad0 .part L_0x1210580, 0, 1; +L_0x1210c80 .part L_0x1210580, 1, 1; +S_0xe8e180 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xf4cf20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d7d710/d .functor OR 1, L_0x1d7d780, L_0x1d7d8e0, C4<0>, C4<0>; -L_0x1d7d710 .delay 1 (30000,30000,30000) L_0x1d7d710/d; -L_0x1d7db10/d .functor OR 1, L_0x1d7dc20, L_0x1d7dd80, C4<0>, C4<0>; -L_0x1d7db10 .delay 1 (30000,30000,30000) L_0x1d7db10/d; -L_0x1d7df00/d .functor OR 1, L_0x1d7df70, L_0x1d7e120, C4<0>, C4<0>; -L_0x1d7df00 .delay 1 (30000,30000,30000) L_0x1d7df00/d; -v0x1b2def0_0 .net *"_s0", 0 0, L_0x1d7d710; 1 drivers -v0x1b2dfd0_0 .net *"_s10", 0 0, L_0x1d7dc20; 1 drivers -v0x1b29fd0_0 .net *"_s12", 0 0, L_0x1d7dd80; 1 drivers -v0x1b2a070_0 .net *"_s14", 0 0, L_0x1d7df70; 1 drivers -v0x1b28f90_0 .net *"_s16", 0 0, L_0x1d7e120; 1 drivers -v0x198f490_0 .net *"_s3", 0 0, L_0x1d7d780; 1 drivers -v0x198f570_0 .net *"_s5", 0 0, L_0x1d7d8e0; 1 drivers -v0x1b0de30_0 .net *"_s6", 0 0, L_0x1d7db10; 1 drivers -v0x1b0df10_0 .net "in", 3 0, L_0x1d7e350; 1 drivers -v0x1afe090_0 .net "ors", 1 0, L_0x1d7da20; 1 drivers -v0x1afdc60_0 .net "out", 0 0, L_0x1d7df00; 1 drivers -L_0x1d7d780 .part L_0x1d7e350, 0, 1; -L_0x1d7d8e0 .part L_0x1d7e350, 1, 1; -L_0x1d7da20 .concat8 [ 1 1 0 0], L_0x1d7d710, L_0x1d7db10; -L_0x1d7dc20 .part L_0x1d7e350, 2, 1; -L_0x1d7dd80 .part L_0x1d7e350, 3, 1; -L_0x1d7df70 .part L_0x1d7da20, 0, 1; -L_0x1d7e120 .part L_0x1d7da20, 1, 1; -S_0x1aaa180 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x173dee0; +L_0x1210ea0/d .functor OR 1, L_0x1210f10, L_0x1210fb0, C4<0>, C4<0>; +L_0x1210ea0 .delay 1 (30000,30000,30000) L_0x1210ea0/d; +L_0x1211190/d .functor OR 1, L_0x12112a0, L_0x1211400, C4<0>, C4<0>; +L_0x1211190 .delay 1 (30000,30000,30000) L_0x1211190/d; +L_0x1211580/d .functor OR 1, L_0x12115f0, L_0x12117a0, C4<0>, C4<0>; +L_0x1211580 .delay 1 (30000,30000,30000) L_0x1211580/d; +v0xea6d10_0 .net *"_s0", 0 0, L_0x1210ea0; 1 drivers +v0xea6df0_0 .net *"_s10", 0 0, L_0x12112a0; 1 drivers +v0xe6ce50_0 .net *"_s12", 0 0, L_0x1211400; 1 drivers +v0xe6cf10_0 .net *"_s14", 0 0, L_0x12115f0; 1 drivers +v0xe85960_0 .net *"_s16", 0 0, L_0x12117a0; 1 drivers +v0xe4bb40_0 .net *"_s3", 0 0, L_0x1210f10; 1 drivers +v0xe4bc20_0 .net *"_s5", 0 0, L_0x1210fb0; 1 drivers +v0xe64630_0 .net *"_s6", 0 0, L_0x1211190; 1 drivers +v0xe64710_0 .net "in", 3 0, L_0x12119d0; 1 drivers +v0xe2a900_0 .net "ors", 1 0, L_0x12110a0; 1 drivers +v0xe43320_0 .net "out", 0 0, L_0x1211580; 1 drivers +L_0x1210f10 .part L_0x12119d0, 0, 1; +L_0x1210fb0 .part L_0x12119d0, 1, 1; +L_0x12110a0 .concat8 [ 1 1 0 0], L_0x1210ea0, L_0x1211190; +L_0x12112a0 .part L_0x12119d0, 2, 1; +L_0x1211400 .part L_0x12119d0, 3, 1; +L_0x12115f0 .part L_0x12110a0, 0, 1; +L_0x12117a0 .part L_0x12110a0, 1, 1; +S_0xda5b40 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xbd2d70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -1228,80 +1238,80 @@ S_0x1aaa180 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x173dee0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1d79bc0/d .functor XNOR 1, L_0x1d82330, L_0x1d82490, C4<0>, C4<0>; -L_0x1d79bc0 .delay 1 (20000,20000,20000) L_0x1d79bc0/d; -L_0x1d79e30/d .functor AND 1, L_0x1d82330, L_0x1d78ad0, C4<1>, C4<1>; -L_0x1d79e30 .delay 1 (30000,30000,30000) L_0x1d79e30/d; -L_0x1d79ea0/d .functor AND 1, L_0x1d79bc0, L_0x1d82530, C4<1>, C4<1>; -L_0x1d79ea0 .delay 1 (30000,30000,30000) L_0x1d79ea0/d; -L_0x1d7a000/d .functor OR 1, L_0x1d79ea0, L_0x1d79e30, C4<0>, C4<0>; -L_0x1d7a000 .delay 1 (30000,30000,30000) L_0x1d7a000/d; -v0x1ab6b00_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers -v0x1a9a410_0 .net "a_", 0 0, L_0x1d789c0; alias, 1 drivers -v0x1a9a4b0_0 .net "b", 0 0, L_0x1d82490; alias, 1 drivers -v0x1a9a090_0 .net "b_", 0 0, L_0x1d78ad0; alias, 1 drivers -v0x1a9a130_0 .net "carryin", 0 0, L_0x1d82530; alias, 1 drivers -v0x1a88db0_0 .net "eq", 0 0, L_0x1d79bc0; 1 drivers -v0x1a88e50_0 .net "lt", 0 0, L_0x1d79e30; 1 drivers -v0x1a95690_0 .net "out", 0 0, L_0x1d7a000; 1 drivers -v0x1a95750_0 .net "w0", 0 0, L_0x1d79ea0; 1 drivers -S_0x1a79090 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x173dee0; +L_0x120d3e0/d .functor XNOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; +L_0x120d3e0 .delay 1 (20000,20000,20000) L_0x120d3e0/d; +L_0x120d650/d .functor AND 1, L_0x12159e0, L_0x120c2d0, C4<1>, C4<1>; +L_0x120d650 .delay 1 (30000,30000,30000) L_0x120d650/d; +L_0x120d6c0/d .functor AND 1, L_0x120d3e0, L_0x1215be0, C4<1>, C4<1>; +L_0x120d6c0 .delay 1 (30000,30000,30000) L_0x120d6c0/d; +L_0x120d820/d .functor OR 1, L_0x120d6c0, L_0x120d650, C4<0>, C4<0>; +L_0x120d820 .delay 1 (30000,30000,30000) L_0x120d820/d; +v0xdc1210_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers +v0xdc1300_0 .net "a_", 0 0, L_0x120c1c0; alias, 1 drivers +v0xdbe680_0 .net "b", 0 0, L_0x1215b40; alias, 1 drivers +v0xdbe770_0 .net "b_", 0 0, L_0x120c2d0; alias, 1 drivers +v0xd847a0_0 .net "carryin", 0 0, L_0x1215be0; alias, 1 drivers +v0xd9fe90_0 .net "eq", 0 0, L_0x120d3e0; 1 drivers +v0xd9ff50_0 .net "lt", 0 0, L_0x120d650; 1 drivers +v0xd633c0_0 .net "out", 0 0, L_0x120d820; 1 drivers +v0xd63480_0 .net "w0", 0 0, L_0x120d6c0; 1 drivers +S_0xd41ff0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xbd2d70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d799a0/d .functor OR 1, L_0x1d794a0, L_0x1a31b90, C4<0>, C4<0>; -L_0x1d799a0 .delay 1 (30000,30000,30000) L_0x1d799a0/d; -v0x1a36970_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers -v0x1a365f0_0 .net "b", 0 0, L_0x1d78ad0; alias, 1 drivers -v0x1a366b0_0 .net "c1", 0 0, L_0x1d794a0; 1 drivers -v0x1a27e80_0 .net "c2", 0 0, L_0x1a31b90; 1 drivers -v0x1a27f50_0 .net "carryin", 0 0, L_0x1d82530; alias, 1 drivers -v0x1a31c20_0 .net "carryout", 0 0, L_0x1d799a0; 1 drivers -v0x1a107f0_0 .net "s1", 0 0, L_0x1821240; 1 drivers -v0x1a10890_0 .net "sum", 0 0, L_0x1d79600; 1 drivers -S_0x1a679f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1a79090; +L_0x120d1c0/d .functor OR 1, L_0x120ccc0, L_0xcdac10, C4<0>, C4<0>; +L_0x120d1c0 .delay 1 (30000,30000,30000) L_0x120d1c0/d; +v0xcde530_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers +v0xcde5f0_0 .net "b", 0 0, L_0x120c2d0; alias, 1 drivers +v0xceaa40_0 .net "c1", 0 0, L_0x120ccc0; 1 drivers +v0xceaae0_0 .net "c2", 0 0, L_0xcdac10; 1 drivers +v0xcdab20_0 .net "carryin", 0 0, L_0x1215be0; alias, 1 drivers +v0xcda7a0_0 .net "carryout", 0 0, L_0x120d1c0; 1 drivers +v0xcda840_0 .net "s1", 0 0, L_0x120cc00; 1 drivers +v0xcc96b0_0 .net "sum", 0 0, L_0x120ce20; 1 drivers +S_0xd5d700 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xd41ff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1821240/d .functor XOR 1, L_0x1d82330, L_0x1d78ad0, C4<0>, C4<0>; -L_0x1821240 .delay 1 (30000,30000,30000) L_0x1821240/d; -L_0x1d794a0/d .functor AND 1, L_0x1d82330, L_0x1d78ad0, C4<1>, C4<1>; -L_0x1d794a0 .delay 1 (30000,30000,30000) L_0x1d794a0/d; -v0x1a742d0_0 .net "a", 0 0, L_0x1d82330; alias, 1 drivers -v0x1a74370_0 .net "b", 0 0, L_0x1d78ad0; alias, 1 drivers -v0x1a57cf0_0 .net "carryout", 0 0, L_0x1d794a0; alias, 1 drivers -v0x1a57d90_0 .net "sum", 0 0, L_0x1821240; alias, 1 drivers -S_0x1a57970 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1a79090; +L_0x120cc00/d .functor XOR 1, L_0x12159e0, L_0x120c2d0, C4<0>, C4<0>; +L_0x120cc00 .delay 1 (30000,30000,30000) L_0x120cc00/d; +L_0x120ccc0/d .functor AND 1, L_0x12159e0, L_0x120c2d0, C4<1>, C4<1>; +L_0x120ccc0 .delay 1 (30000,30000,30000) L_0x120ccc0/d; +v0xd20c20_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers +v0xd20cc0_0 .net "b", 0 0, L_0x120c2d0; alias, 1 drivers +v0xd1cb20_0 .net "carryout", 0 0, L_0x120ccc0; alias, 1 drivers +v0xd1cbc0_0 .net "sum", 0 0, L_0x120cc00; alias, 1 drivers +S_0xcff8c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xd41ff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d79600/d .functor XOR 1, L_0x1821240, L_0x1d82530, C4<0>, C4<0>; -L_0x1d79600 .delay 1 (30000,30000,30000) L_0x1d79600/d; -L_0x1a31b90/d .functor AND 1, L_0x1821240, L_0x1d82530, C4<1>, C4<1>; -L_0x1a31b90 .delay 1 (30000,30000,30000) L_0x1a31b90/d; -v0x1a492d0_0 .net "a", 0 0, L_0x1821240; alias, 1 drivers -v0x1a46670_0 .net "b", 0 0, L_0x1d82530; alias, 1 drivers -v0x1a46710_0 .net "carryout", 0 0, L_0x1a31b90; alias, 1 drivers -v0x1a52f20_0 .net "sum", 0 0, L_0x1d79600; alias, 1 drivers -S_0x1833170 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x175dea0; - .timescale -9 -12; -L_0x7f72592da138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d825d0/d .functor OR 1, L_0x7f72592da138, L_0x7f72592da180, C4<0>, C4<0>; -L_0x1d825d0 .delay 1 (30000,30000,30000) L_0x1d825d0/d; -v0x1823250_0 .net/2u *"_s0", 0 0, L_0x7f72592da138; 1 drivers -v0x1823330_0 .net/2u *"_s2", 0 0, L_0x7f72592da180; 1 drivers -S_0x1822ed0 .scope generate, "alu_slices[2]" "alu_slices[2]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x18e5af0 .param/l "i" 0 3 37, +C4<010>; -S_0x1811df0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1822ed0; +L_0x120ce20/d .functor XOR 1, L_0x120cc00, L_0x1215be0, C4<0>, C4<0>; +L_0x120ce20 .delay 1 (30000,30000,30000) L_0x120ce20/d; +L_0xcdac10/d .functor AND 1, L_0x120cc00, L_0x1215be0, C4<1>, C4<1>; +L_0xcdac10 .delay 1 (30000,30000,30000) L_0xcdac10/d; +v0xd0be30_0 .net "a", 0 0, L_0x120cc00; alias, 1 drivers +v0xcfbeb0_0 .net "b", 0 0, L_0x1215be0; alias, 1 drivers +v0xcfbf50_0 .net "carryout", 0 0, L_0xcdac10; alias, 1 drivers +v0xcfbb30_0 .net "sum", 0 0, L_0x120ce20; alias, 1 drivers +S_0xc34760 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0xbd4310; + .timescale -9 -12; +L_0x2b0ab3d05138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1215c80/d .functor OR 1, L_0x2b0ab3d05138, L_0x2b0ab3d05180, C4<0>, C4<0>; +L_0x1215c80 .delay 1 (30000,30000,30000) L_0x1215c80/d; +v0xc343e0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05138; 1 drivers +v0xc344a0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05180; 1 drivers +S_0xc23180 .scope generate, "alu_slices[2]" "alu_slices[2]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0xcfbc70 .param/l "i" 0 3 41, +C4<010>; +S_0xc13330 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xc23180; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -1310,445 +1320,445 @@ S_0x1811df0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1822ed0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1d827f0/d .functor NOT 1, L_0x1d8bee0, C4<0>, C4<0>, C4<0>; -L_0x1d827f0 .delay 1 (10000,10000,10000) L_0x1d827f0/d; -L_0x1d82900/d .functor NOT 1, L_0x1d8c0d0, C4<0>, C4<0>, C4<0>; -L_0x1d82900 .delay 1 (10000,10000,10000) L_0x1d82900/d; -L_0x1d83750/d .functor XOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; -L_0x1d83750 .delay 1 (30000,30000,30000) L_0x1d83750/d; -L_0x7f72592da1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d83e00/d .functor OR 1, L_0x7f72592da1c8, L_0x7f72592da210, C4<0>, C4<0>; -L_0x1d83e00 .delay 1 (30000,30000,30000) L_0x1d83e00/d; -L_0x1d84000/d .functor AND 1, L_0x1d8bee0, L_0x1d8c0d0, C4<1>, C4<1>; -L_0x1d84000 .delay 1 (30000,30000,30000) L_0x1d84000/d; -L_0x1d840c0/d .functor NAND 1, L_0x1d8bee0, L_0x1d8c0d0, C4<1>, C4<1>; -L_0x1d840c0 .delay 1 (20000,20000,20000) L_0x1d840c0/d; -L_0x1d84220/d .functor XOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; -L_0x1d84220 .delay 1 (20000,20000,20000) L_0x1d84220/d; -L_0x1d846d0/d .functor OR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; -L_0x1d846d0 .delay 1 (30000,30000,30000) L_0x1d846d0/d; -L_0x1d8bde0/d .functor NOT 1, L_0x1d88040, C4<0>, C4<0>, C4<0>; -L_0x1d8bde0 .delay 1 (10000,10000,10000) L_0x1d8bde0/d; -v0x1b61ee0_0 .net "A", 0 0, L_0x1d8bee0; 1 drivers -v0x1b61fa0_0 .net "A_", 0 0, L_0x1d827f0; 1 drivers -v0x1b62060_0 .net "B", 0 0, L_0x1d8c0d0; 1 drivers -v0x1b62130_0 .net "B_", 0 0, L_0x1d82900; 1 drivers -v0x1b621d0_0 .net *"_s12", 0 0, L_0x1d83e00; 1 drivers -v0x1b622c0_0 .net/2s *"_s14", 0 0, L_0x7f72592da1c8; 1 drivers -v0x1b62380_0 .net/2s *"_s16", 0 0, L_0x7f72592da210; 1 drivers -v0x1b62460_0 .net *"_s18", 0 0, L_0x1d84000; 1 drivers -v0x1b62540_0 .net *"_s20", 0 0, L_0x1d840c0; 1 drivers -v0x1b626b0_0 .net *"_s22", 0 0, L_0x1d84220; 1 drivers -v0x1b62790_0 .net *"_s24", 0 0, L_0x1d846d0; 1 drivers -o0x7f725935ad68 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1b62870_0 name=_s30 -o0x7f725935ad98 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1b62950_0 name=_s32 -v0x1b62a30_0 .net *"_s8", 0 0, L_0x1d83750; 1 drivers -v0x1b62b10_0 .net "carryin", 0 0, L_0x1d8c200; 1 drivers -v0x1b62bb0_0 .net "carryout", 0 0, L_0x1d8ba80; 1 drivers -v0x1b62c50_0 .net "carryouts", 7 0, L_0x1ebeed0; 1 drivers -v0x1b62e00_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b62ea0_0 .net "result", 0 0, L_0x1d88040; 1 drivers -v0x1b62f90_0 .net "results", 7 0, L_0x1d844a0; 1 drivers -v0x1b630a0_0 .net "zero", 0 0, L_0x1d8bde0; 1 drivers -LS_0x1d844a0_0_0 .concat8 [ 1 1 1 1], L_0x1d82c70, L_0x1d832a0, L_0x1d83750, L_0x1d83e00; -LS_0x1d844a0_0_4 .concat8 [ 1 1 1 1], L_0x1d84000, L_0x1d840c0, L_0x1d84220, L_0x1d846d0; -L_0x1d844a0 .concat8 [ 4 4 0 0], LS_0x1d844a0_0_0, LS_0x1d844a0_0_4; -LS_0x1ebeed0_0_0 .concat [ 1 1 1 1], L_0x1d82f20, L_0x1d835f0, o0x7f725935ad68, L_0x1d83c50; -LS_0x1ebeed0_0_4 .concat [ 4 0 0 0], o0x7f725935ad98; -L_0x1ebeed0 .concat [ 4 4 0 0], LS_0x1ebeed0_0_0, LS_0x1ebeed0_0_4; -S_0x1801b50 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1811df0; +L_0x1215ea0/d .functor NOT 1, L_0x121f680, C4<0>, C4<0>, C4<0>; +L_0x1215ea0 .delay 1 (10000,10000,10000) L_0x1215ea0/d; +L_0x1215fb0/d .functor NOT 1, L_0x121f870, C4<0>, C4<0>, C4<0>; +L_0x1215fb0 .delay 1 (10000,10000,10000) L_0x1215fb0/d; +L_0x1216ef0/d .functor XOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; +L_0x1216ef0 .delay 1 (30000,30000,30000) L_0x1216ef0/d; +L_0x2b0ab3d051c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12175a0/d .functor OR 1, L_0x2b0ab3d051c8, L_0x2b0ab3d05210, C4<0>, C4<0>; +L_0x12175a0 .delay 1 (30000,30000,30000) L_0x12175a0/d; +L_0x12177a0/d .functor AND 1, L_0x121f680, L_0x121f870, C4<1>, C4<1>; +L_0x12177a0 .delay 1 (30000,30000,30000) L_0x12177a0/d; +L_0x1217860/d .functor NAND 1, L_0x121f680, L_0x121f870, C4<1>, C4<1>; +L_0x1217860 .delay 1 (20000,20000,20000) L_0x1217860/d; +L_0x12179c0/d .functor XOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; +L_0x12179c0 .delay 1 (20000,20000,20000) L_0x12179c0/d; +L_0x1217e70/d .functor OR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; +L_0x1217e70 .delay 1 (30000,30000,30000) L_0x1217e70/d; +L_0x121f580/d .functor NOT 1, L_0x121b7e0, C4<0>, C4<0>, C4<0>; +L_0x121f580 .delay 1 (10000,10000,10000) L_0x121f580/d; +v0xff4a60_0 .net "A", 0 0, L_0x121f680; 1 drivers +v0xff4b20_0 .net "A_", 0 0, L_0x1215ea0; 1 drivers +v0xff4be0_0 .net "B", 0 0, L_0x121f870; 1 drivers +v0xff4cb0_0 .net "B_", 0 0, L_0x1215fb0; 1 drivers +v0xff4d50_0 .net *"_s12", 0 0, L_0x12175a0; 1 drivers +v0xff4e40_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d051c8; 1 drivers +v0xff4f00_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05210; 1 drivers +v0xff4fe0_0 .net *"_s18", 0 0, L_0x12177a0; 1 drivers +v0xff50c0_0 .net *"_s20", 0 0, L_0x1217860; 1 drivers +v0xff5230_0 .net *"_s22", 0 0, L_0x12179c0; 1 drivers +v0xff5310_0 .net *"_s24", 0 0, L_0x1217e70; 1 drivers +o0x2b0ab3ca9d68 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0xff53f0_0 name=_s30 +o0x2b0ab3ca9d98 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0xff54d0_0 name=_s32 +v0xff55b0_0 .net *"_s8", 0 0, L_0x1216ef0; 1 drivers +v0xff5690_0 .net "carryin", 0 0, L_0x121f9a0; 1 drivers +v0xff5730_0 .net "carryout", 0 0, L_0x121f220; 1 drivers +v0xff57d0_0 .net "carryouts", 7 0, L_0x1353280; 1 drivers +v0xff5980_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0xff5a20_0 .net "result", 0 0, L_0x121b7e0; 1 drivers +v0xff5b10_0 .net "results", 7 0, L_0x1217c40; 1 drivers +v0xff5c20_0 .net "zero", 0 0, L_0x121f580; 1 drivers +LS_0x1217c40_0_0 .concat8 [ 1 1 1 1], L_0x1216410, L_0x1216a40, L_0x1216ef0, L_0x12175a0; +LS_0x1217c40_0_4 .concat8 [ 1 1 1 1], L_0x12177a0, L_0x1217860, L_0x12179c0, L_0x1217e70; +L_0x1217c40 .concat8 [ 4 4 0 0], LS_0x1217c40_0_0, LS_0x1217c40_0_4; +LS_0x1353280_0_0 .concat [ 1 1 1 1], L_0x12166c0, L_0x1216d90, o0x2b0ab3ca9d68, L_0x12173f0; +LS_0x1353280_0_4 .concat [ 4 0 0 0], o0x2b0ab3ca9d98; +L_0x1353280 .concat [ 4 4 0 0], LS_0x1353280_0_0, LS_0x1353280_0_4; +S_0xc01d00 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xc13330; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d82f20/d .functor OR 1, L_0x1d82af0, L_0x1d82dc0, C4<0>, C4<0>; -L_0x1d82f20 .delay 1 (30000,30000,30000) L_0x1d82f20/d; -v0x179e070_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers -v0x179e130_0 .net "b", 0 0, L_0x1d8c0d0; alias, 1 drivers -v0x178ce40_0 .net "c1", 0 0, L_0x1d82af0; 1 drivers -v0x178cf40_0 .net "c2", 0 0, L_0x1d82dc0; 1 drivers -v0x177cf90_0 .net "carryin", 0 0, L_0x1d8c200; alias, 1 drivers -v0x177d080_0 .net "carryout", 0 0, L_0x1d82f20; 1 drivers -v0x177cc10_0 .net "s1", 0 0, L_0x1d7c370; 1 drivers -v0x177cd00_0 .net "sum", 0 0, L_0x1d82c70; 1 drivers -S_0x17f0a50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1801b50; +L_0x12166c0/d .functor OR 1, L_0x12161a0, L_0x1216560, C4<0>, C4<0>; +L_0x12166c0 .delay 1 (30000,30000,30000) L_0x12166c0/d; +v0xb9ead0_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers +v0xb9eb90_0 .net "b", 0 0, L_0x121f870; alias, 1 drivers +v0xcdcfd0_0 .net "c1", 0 0, L_0x12161a0; 1 drivers +v0xcdd0d0_0 .net "c2", 0 0, L_0x1216560; 1 drivers +v0xf93560_0 .net "carryin", 0 0, L_0x121f9a0; alias, 1 drivers +v0xf93650_0 .net "carryout", 0 0, L_0x12166c0; 1 drivers +v0xf721e0_0 .net "s1", 0 0, L_0x1213500; 1 drivers +v0xf722d0_0 .net "sum", 0 0, L_0x1216410; 1 drivers +S_0xbf1eb0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xc01d00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d7c370/d .functor XOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; -L_0x1d7c370 .delay 1 (30000,30000,30000) L_0x1d7c370/d; -L_0x1d82af0/d .functor AND 1, L_0x1d8bee0, L_0x1d8c0d0, C4<1>, C4<1>; -L_0x1d82af0 .delay 1 (30000,30000,30000) L_0x1d82af0/d; -v0x17e0c40_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers -v0x17e0800_0 .net "b", 0 0, L_0x1d8c0d0; alias, 1 drivers -v0x17e08a0_0 .net "carryout", 0 0, L_0x1d82af0; alias, 1 drivers -v0x17cf680_0 .net "sum", 0 0, L_0x1d7c370; alias, 1 drivers -S_0x17bf7d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1801b50; +L_0x1213500/d .functor XOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; +L_0x1213500 .delay 1 (30000,30000,30000) L_0x1213500/d; +L_0x12161a0/d .functor AND 1, L_0x121f680, L_0x121f870, C4<1>, C4<1>; +L_0x12161a0 .delay 1 (30000,30000,30000) L_0x12161a0/d; +v0xbf1bf0_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers +v0xbe08a0_0 .net "b", 0 0, L_0x121f870; alias, 1 drivers +v0xbe0960_0 .net "carryout", 0 0, L_0x12161a0; alias, 1 drivers +v0xbd0a50_0 .net "sum", 0 0, L_0x1213500; alias, 1 drivers +S_0xbd06d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xc01d00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d82c70/d .functor XOR 1, L_0x1d7c370, L_0x1d8c200, C4<0>, C4<0>; -L_0x1d82c70 .delay 1 (30000,30000,30000) L_0x1d82c70/d; -L_0x1d82dc0/d .functor AND 1, L_0x1d7c370, L_0x1d8c200, C4<1>, C4<1>; -L_0x1d82dc0 .delay 1 (30000,30000,30000) L_0x1d82dc0/d; -v0x17bf4c0_0 .net "a", 0 0, L_0x1d7c370; alias, 1 drivers -v0x17ae280_0 .net "b", 0 0, L_0x1d8c200; alias, 1 drivers -v0x17ae320_0 .net "carryout", 0 0, L_0x1d82dc0; alias, 1 drivers -v0x179e3f0_0 .net "sum", 0 0, L_0x1d82c70; alias, 1 drivers -S_0x176b990 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1811df0; +L_0x1216410/d .functor XOR 1, L_0x1213500, L_0x121f9a0, C4<0>, C4<0>; +L_0x1216410 .delay 1 (30000,30000,30000) L_0x1216410/d; +L_0x1216560/d .functor AND 1, L_0x1213500, L_0x121f9a0, C4<1>, C4<1>; +L_0x1216560 .delay 1 (30000,30000,30000) L_0x1216560/d; +v0xbbf480_0 .net "a", 0 0, L_0x1213500; alias, 1 drivers +v0xbb0220_0 .net "b", 0 0, L_0x121f9a0; alias, 1 drivers +v0xbb02c0_0 .net "carryout", 0 0, L_0x1216560; alias, 1 drivers +v0xbafe70_0 .net "sum", 0 0, L_0x1216410; alias, 1 drivers +S_0xb84020 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xc13330; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1a99e10_0 .net "ands", 7 0, L_0x1d89a80; 1 drivers -v0x1a78970_0 .net "in", 7 0, L_0x1ebeed0; alias, 1 drivers -v0x1a78a10_0 .net "out", 0 0, L_0x1d8ba80; alias, 1 drivers -v0x1a575d0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x175bb00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x176b990; +v0xcdfa30_0 .net "ands", 7 0, L_0x121d220; 1 drivers +v0xcdfaf0_0 .net "in", 7 0, L_0x1353280; alias, 1 drivers +v0xcbe660_0 .net "out", 0 0, L_0x121f220; alias, 1 drivers +v0xcbe700_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xb79a00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xb84020; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x167c610_0 .net "A", 7 0, L_0x1ebeed0; alias, 1 drivers -v0x1671f10_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1671ff0_0 .net *"_s0", 0 0, L_0x1d883a0; 1 drivers -v0x16678f0_0 .net *"_s12", 0 0, L_0x1d88d10; 1 drivers -v0x16679d0_0 .net *"_s16", 0 0, L_0x1d89070; 1 drivers -v0x165d360_0 .net *"_s20", 0 0, L_0x1d89380; 1 drivers -v0x1652cb0_0 .net *"_s24", 0 0, L_0x1d89770; 1 drivers -v0x1652d90_0 .net *"_s28", 0 0, L_0x1d89700; 1 drivers -v0x1648690_0 .net *"_s4", 0 0, L_0x1d886b0; 1 drivers -v0x163e070_0 .net *"_s8", 0 0, L_0x1d88a00; 1 drivers -v0x163e150_0 .net "out", 7 0, L_0x1d89a80; alias, 1 drivers -L_0x1d88460 .part L_0x1ebeed0, 0, 1; -L_0x1d885c0 .part v0x1d6daa0_0, 0, 1; -L_0x1d88770 .part L_0x1ebeed0, 1, 1; -L_0x1d88960 .part v0x1d6daa0_0, 1, 1; -L_0x1d88ac0 .part L_0x1ebeed0, 2, 1; -L_0x1d88c20 .part v0x1d6daa0_0, 2, 1; -L_0x1d88dd0 .part L_0x1ebeed0, 3, 1; -L_0x1d88f30 .part v0x1d6daa0_0, 3, 1; -L_0x1d89130 .part L_0x1ebeed0, 4, 1; -L_0x1d89290 .part v0x1d6daa0_0, 4, 1; -L_0x1d893f0 .part L_0x1ebeed0, 5, 1; -L_0x1d89660 .part v0x1d6daa0_0, 5, 1; -L_0x1d89830 .part L_0x1ebeed0, 6, 1; -L_0x1d89990 .part v0x1d6daa0_0, 6, 1; -LS_0x1d89a80_0_0 .concat8 [ 1 1 1 1], L_0x1d883a0, L_0x1d886b0, L_0x1d88a00, L_0x1d88d10; -LS_0x1d89a80_0_4 .concat8 [ 1 1 1 1], L_0x1d89070, L_0x1d89380, L_0x1d89770, L_0x1d89700; -L_0x1d89a80 .concat8 [ 4 4 0 0], LS_0x1d89a80_0_0, LS_0x1d89a80_0_4; -L_0x1d89e40 .part L_0x1ebeed0, 7, 1; -L_0x1d8a030 .part v0x1d6daa0_0, 7, 1; -S_0x174a4e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x175b840 .param/l "i" 0 4 54, +C4<00>; -L_0x1d883a0/d .functor AND 1, L_0x1d88460, L_0x1d885c0, C4<1>, C4<1>; -L_0x1d883a0 .delay 1 (30000,30000,30000) L_0x1d883a0/d; -v0x173a620_0 .net *"_s0", 0 0, L_0x1d88460; 1 drivers -v0x173a700_0 .net *"_s1", 0 0, L_0x1d885c0; 1 drivers -S_0x173a2a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x1729050 .param/l "i" 0 4 54, +C4<01>; -L_0x1d886b0/d .functor AND 1, L_0x1d88770, L_0x1d88960, C4<1>, C4<1>; -L_0x1d886b0 .delay 1 (30000,30000,30000) L_0x1d886b0/d; -v0x1719da0_0 .net *"_s0", 0 0, L_0x1d88770; 1 drivers -v0x1719e80_0 .net *"_s1", 0 0, L_0x1d88960; 1 drivers -S_0x17199f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x17086a0 .param/l "i" 0 4 54, +C4<010>; -L_0x1d88a00/d .functor AND 1, L_0x1d88ac0, L_0x1d88c20, C4<1>, C4<1>; -L_0x1d88a00 .delay 1 (30000,30000,30000) L_0x1d88a00/d; -v0x1708740_0 .net *"_s0", 0 0, L_0x1d88ac0; 1 drivers -v0x1adbd30_0 .net *"_s1", 0 0, L_0x1d88c20; 1 drivers -S_0x1aba930 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x1adbe60 .param/l "i" 0 4 54, +C4<011>; -L_0x1d88d10/d .functor AND 1, L_0x1d88dd0, L_0x1d88f30, C4<1>, C4<1>; -L_0x1d88d10 .delay 1 (30000,30000,30000) L_0x1d88d10/d; -v0x1a995f0_0 .net *"_s0", 0 0, L_0x1d88dd0; 1 drivers -v0x1a781e0_0 .net *"_s1", 0 0, L_0x1d88f30; 1 drivers -S_0x16ee890 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x16e4270 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d89070/d .functor AND 1, L_0x1d89130, L_0x1d89290, C4<1>, C4<1>; -L_0x1d89070 .delay 1 (30000,30000,30000) L_0x1d89070/d; -v0x16e4350_0 .net *"_s0", 0 0, L_0x1d89130; 1 drivers -v0x16d9c50_0 .net *"_s1", 0 0, L_0x1d89290; 1 drivers -S_0x16cf630 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x16d9da0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d89380/d .functor AND 1, L_0x1d893f0, L_0x1d89660, C4<1>, C4<1>; -L_0x1d89380 .delay 1 (30000,30000,30000) L_0x1d89380/d; -v0x16c50a0_0 .net *"_s0", 0 0, L_0x1d893f0; 1 drivers -v0x16ba9f0_0 .net *"_s1", 0 0, L_0x1d89660; 1 drivers -S_0x16b03d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x16bab40 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d89770/d .functor AND 1, L_0x1d89830, L_0x1d89990, C4<1>, C4<1>; -L_0x1d89770 .delay 1 (30000,30000,30000) L_0x1d89770/d; -v0x16a5e40_0 .net *"_s0", 0 0, L_0x1d89830; 1 drivers -v0x169b790_0 .net *"_s1", 0 0, L_0x1d89990; 1 drivers -S_0x1691170 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x175bb00; - .timescale -9 -12; -P_0x169b8e0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d89700/d .functor AND 1, L_0x1d89e40, L_0x1d8a030, C4<1>, C4<1>; -L_0x1d89700 .delay 1 (30000,30000,30000) L_0x1d89700/d; -v0x1686be0_0 .net *"_s0", 0 0, L_0x1d89e40; 1 drivers -v0x167c530_0 .net *"_s1", 0 0, L_0x1d8a030; 1 drivers -S_0x1633a50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x176b990; +v0xa807e0_0 .net "A", 7 0, L_0x1353280; alias, 1 drivers +v0xa760e0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xa761c0_0 .net *"_s0", 0 0, L_0x121bb40; 1 drivers +v0xa6bb10_0 .net *"_s12", 0 0, L_0x121c4b0; 1 drivers +v0xa6bbf0_0 .net *"_s16", 0 0, L_0x121c810; 1 drivers +v0xa61580_0 .net *"_s20", 0 0, L_0x121cb20; 1 drivers +v0xa56ed0_0 .net *"_s24", 0 0, L_0x121cf10; 1 drivers +v0xa56fb0_0 .net *"_s28", 0 0, L_0x121cea0; 1 drivers +v0xa4c8b0_0 .net *"_s4", 0 0, L_0x121be50; 1 drivers +v0xa42290_0 .net *"_s8", 0 0, L_0x121c1a0; 1 drivers +v0xa42370_0 .net "out", 7 0, L_0x121d220; alias, 1 drivers +L_0x121bc00 .part L_0x1353280, 0, 1; +L_0x121bd60 .part v0x12010b0_0, 0, 1; +L_0x121bf10 .part L_0x1353280, 1, 1; +L_0x121c100 .part v0x12010b0_0, 1, 1; +L_0x121c260 .part L_0x1353280, 2, 1; +L_0x121c3c0 .part v0x12010b0_0, 2, 1; +L_0x121c570 .part L_0x1353280, 3, 1; +L_0x121c6d0 .part v0x12010b0_0, 3, 1; +L_0x121c8d0 .part L_0x1353280, 4, 1; +L_0x121ca30 .part v0x12010b0_0, 4, 1; +L_0x121cb90 .part L_0x1353280, 5, 1; +L_0x121ce00 .part v0x12010b0_0, 5, 1; +L_0x121cfd0 .part L_0x1353280, 6, 1; +L_0x121d130 .part v0x12010b0_0, 6, 1; +LS_0x121d220_0_0 .concat8 [ 1 1 1 1], L_0x121bb40, L_0x121be50, L_0x121c1a0, L_0x121c4b0; +LS_0x121d220_0_4 .concat8 [ 1 1 1 1], L_0x121c810, L_0x121cb20, L_0x121cf10, L_0x121cea0; +L_0x121d220 .concat8 [ 4 4 0 0], LS_0x121d220_0_0, LS_0x121d220_0_4; +L_0x121d5e0 .part L_0x1353280, 7, 1; +L_0x121d7d0 .part v0x12010b0_0, 7, 1; +S_0xb64dc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xb6f510 .param/l "i" 0 4 54, +C4<00>; +L_0x121bb40/d .functor AND 1, L_0x121bc00, L_0x121bd60, C4<1>, C4<1>; +L_0x121bb40 .delay 1 (30000,30000,30000) L_0x121bb40/d; +v0xb5a830_0 .net *"_s0", 0 0, L_0x121bc00; 1 drivers +v0xb50180_0 .net *"_s1", 0 0, L_0x121bd60; 1 drivers +S_0xb45b60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xb3b540 .param/l "i" 0 4 54, +C4<01>; +L_0x121be50/d .functor AND 1, L_0x121bf10, L_0x121c100, C4<1>, C4<1>; +L_0x121be50 .delay 1 (30000,30000,30000) L_0x121be50/d; +v0xb3b600_0 .net *"_s0", 0 0, L_0x121bf10; 1 drivers +v0xb30f20_0 .net *"_s1", 0 0, L_0x121c100; 1 drivers +S_0xb26900 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xb31070 .param/l "i" 0 4 54, +C4<010>; +L_0x121c1a0/d .functor AND 1, L_0x121c260, L_0x121c3c0, C4<1>, C4<1>; +L_0x121c1a0 .delay 1 (30000,30000,30000) L_0x121c1a0/d; +v0xb1c350_0 .net *"_s0", 0 0, L_0x121c260; 1 drivers +v0xb11cc0_0 .net *"_s1", 0 0, L_0x121c3c0; 1 drivers +S_0xb076a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xb11da0 .param/l "i" 0 4 54, +C4<011>; +L_0x121c4b0/d .functor AND 1, L_0x121c570, L_0x121c6d0, C4<1>, C4<1>; +L_0x121c4b0 .delay 1 (30000,30000,30000) L_0x121c4b0/d; +v0xafd080_0 .net *"_s0", 0 0, L_0x121c570; 1 drivers +v0xafd180_0 .net *"_s1", 0 0, L_0x121c6d0; 1 drivers +S_0xaf2a60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xae8500 .param/l "i" 0 4 54, +C4<0100>; +L_0x121c810/d .functor AND 1, L_0x121c8d0, L_0x121ca30, C4<1>, C4<1>; +L_0x121c810 .delay 1 (30000,30000,30000) L_0x121c810/d; +v0xadde20_0 .net *"_s0", 0 0, L_0x121c8d0; 1 drivers +v0xaddf00_0 .net *"_s1", 0 0, L_0x121ca30; 1 drivers +S_0xad3800 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xac9250 .param/l "i" 0 4 54, +C4<0101>; +L_0x121cb20/d .functor AND 1, L_0x121cb90, L_0x121ce00, C4<1>, C4<1>; +L_0x121cb20 .delay 1 (30000,30000,30000) L_0x121cb20/d; +v0xabebc0_0 .net *"_s0", 0 0, L_0x121cb90; 1 drivers +v0xabeca0_0 .net *"_s1", 0 0, L_0x121ce00; 1 drivers +S_0xab45a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xaa9f80 .param/l "i" 0 4 54, +C4<0110>; +L_0x121cf10/d .functor AND 1, L_0x121cfd0, L_0x121d130, C4<1>, C4<1>; +L_0x121cf10 .delay 1 (30000,30000,30000) L_0x121cf10/d; +v0xaaa040_0 .net *"_s0", 0 0, L_0x121cfd0; 1 drivers +v0xa9f960_0 .net *"_s1", 0 0, L_0x121d130; 1 drivers +S_0xa95340 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xb79a00; + .timescale -9 -12; +P_0xa9fab0 .param/l "i" 0 4 54, +C4<0111>; +L_0x121cea0/d .functor AND 1, L_0x121d5e0, L_0x121d7d0, C4<1>, C4<1>; +L_0x121cea0 .delay 1 (30000,30000,30000) L_0x121cea0/d; +v0xa8adb0_0 .net *"_s0", 0 0, L_0x121d5e0; 1 drivers +v0xa80700_0 .net *"_s1", 0 0, L_0x121d7d0; 1 drivers +S_0xc9be60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xb84020; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d8ba80/d .functor OR 1, L_0x1d8bb40, L_0x1d8bcf0, C4<0>, C4<0>; -L_0x1d8ba80 .delay 1 (30000,30000,30000) L_0x1d8ba80/d; -v0x1adc4c0_0 .net *"_s10", 0 0, L_0x1d8bb40; 1 drivers -v0x1adc5a0_0 .net *"_s12", 0 0, L_0x1d8bcf0; 1 drivers -v0x1abb0c0_0 .net "in", 7 0, L_0x1d89a80; alias, 1 drivers -v0x1abb160_0 .net "ors", 1 0, L_0x1d8b8a0; 1 drivers -v0x1a99cf0_0 .net "out", 0 0, L_0x1d8ba80; alias, 1 drivers -L_0x1d8ac70 .part L_0x1d89a80, 0, 4; -L_0x1d8b8a0 .concat8 [ 1 1 0 0], L_0x1d8a960, L_0x1d8b590; -L_0x1d8b9e0 .part L_0x1d89a80, 4, 4; -L_0x1d8bb40 .part L_0x1d8b8a0, 0, 1; -L_0x1d8bcf0 .part L_0x1d8b8a0, 1, 1; -S_0x1629430 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1633a50; +L_0x121f220/d .functor OR 1, L_0x121f2e0, L_0x121f490, C4<0>, C4<0>; +L_0x121f220 .delay 1 (30000,30000,30000) L_0x121f220/d; +v0xbf1890_0 .net *"_s10", 0 0, L_0x121f2e0; 1 drivers +v0xbd0330_0 .net *"_s12", 0 0, L_0x121f490; 1 drivers +v0xbd0410_0 .net "in", 7 0, L_0x121d220; alias, 1 drivers +v0xbafaa0_0 .net "ors", 1 0, L_0x121f040; 1 drivers +v0xbafb60_0 .net "out", 0 0, L_0x121f220; alias, 1 drivers +L_0x121e410 .part L_0x121d220, 0, 4; +L_0x121f040 .concat8 [ 1 1 0 0], L_0x121e100, L_0x121ed30; +L_0x121f180 .part L_0x121d220, 4, 4; +L_0x121f2e0 .part L_0x121f040, 0, 1; +L_0x121f490 .part L_0x121f040, 1, 1; +S_0xbf6f00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xc9be60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d8a120/d .functor OR 1, L_0x1d8a1e0, L_0x1d8a340, C4<0>, C4<0>; -L_0x1d8a120 .delay 1 (30000,30000,30000) L_0x1d8a120/d; -L_0x1d8a570/d .functor OR 1, L_0x1d8a680, L_0x1d8a7e0, C4<0>, C4<0>; -L_0x1d8a570 .delay 1 (30000,30000,30000) L_0x1d8a570/d; -L_0x1d8a960/d .functor OR 1, L_0x1d8a9d0, L_0x1d8ab80, C4<0>, C4<0>; -L_0x1d8a960 .delay 1 (30000,30000,30000) L_0x1d8a960/d; -v0x161ee80_0 .net *"_s0", 0 0, L_0x1d8a120; 1 drivers -v0x16147f0_0 .net *"_s10", 0 0, L_0x1d8a680; 1 drivers -v0x16148d0_0 .net *"_s12", 0 0, L_0x1d8a7e0; 1 drivers -v0x160a1d0_0 .net *"_s14", 0 0, L_0x1d8a9d0; 1 drivers -v0x160a2b0_0 .net *"_s16", 0 0, L_0x1d8ab80; 1 drivers -v0x15ffc40_0 .net *"_s3", 0 0, L_0x1d8a1e0; 1 drivers -v0x15f55e0_0 .net *"_s5", 0 0, L_0x1d8a340; 1 drivers -v0x15f56c0_0 .net *"_s6", 0 0, L_0x1d8a570; 1 drivers -v0x15eaf70_0 .net "in", 3 0, L_0x1d8ac70; 1 drivers -v0x15e0950_0 .net "ors", 1 0, L_0x1d8a480; 1 drivers -v0x15e0a30_0 .net "out", 0 0, L_0x1d8a960; 1 drivers -L_0x1d8a1e0 .part L_0x1d8ac70, 0, 1; -L_0x1d8a340 .part L_0x1d8ac70, 1, 1; -L_0x1d8a480 .concat8 [ 1 1 0 0], L_0x1d8a120, L_0x1d8a570; -L_0x1d8a680 .part L_0x1d8ac70, 2, 1; -L_0x1d8a7e0 .part L_0x1d8ac70, 3, 1; -L_0x1d8a9d0 .part L_0x1d8a480, 0, 1; -L_0x1d8ab80 .part L_0x1d8a480, 1, 1; -S_0x15d6370 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1633a50; +L_0x121d8c0/d .functor OR 1, L_0x121d980, L_0x121dae0, C4<0>, C4<0>; +L_0x121d8c0 .delay 1 (30000,30000,30000) L_0x121d8c0/d; +L_0x121dd10/d .functor OR 1, L_0x121de20, L_0x121df80, C4<0>, C4<0>; +L_0x121dd10 .delay 1 (30000,30000,30000) L_0x121dd10/d; +L_0x121e100/d .functor OR 1, L_0x121e170, L_0x121e320, C4<0>, C4<0>; +L_0x121e100 .delay 1 (30000,30000,30000) L_0x121e100/d; +v0xbcf8e0_0 .net *"_s0", 0 0, L_0x121d8c0; 1 drivers +v0xf93cf0_0 .net *"_s10", 0 0, L_0x121de20; 1 drivers +v0xf93dd0_0 .net *"_s12", 0 0, L_0x121df80; 1 drivers +v0xf72970_0 .net *"_s14", 0 0, L_0x121e170; 1 drivers +v0xf72a50_0 .net *"_s16", 0 0, L_0x121e320; 1 drivers +v0xf515d0_0 .net *"_s3", 0 0, L_0x121d980; 1 drivers +v0xf51690_0 .net *"_s5", 0 0, L_0x121dae0; 1 drivers +v0xf30250_0 .net *"_s6", 0 0, L_0x121dd10; 1 drivers +v0xf30330_0 .net "in", 3 0, L_0x121e410; 1 drivers +v0xcfb860_0 .net "ors", 1 0, L_0x121dc20; 1 drivers +v0xcda400_0 .net "out", 0 0, L_0x121e100; 1 drivers +L_0x121d980 .part L_0x121e410, 0, 1; +L_0x121dae0 .part L_0x121e410, 1, 1; +L_0x121dc20 .concat8 [ 1 1 0 0], L_0x121d8c0, L_0x121dd10; +L_0x121de20 .part L_0x121e410, 2, 1; +L_0x121df80 .part L_0x121e410, 3, 1; +L_0x121e170 .part L_0x121dc20, 0, 1; +L_0x121e320 .part L_0x121dc20, 1, 1; +S_0xcb90b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xc9be60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d8ada0/d .functor OR 1, L_0x1d8ae10, L_0x1d8af70, C4<0>, C4<0>; -L_0x1d8ada0 .delay 1 (30000,30000,30000) L_0x1d8ada0/d; -L_0x1d8b1a0/d .functor OR 1, L_0x1d8b2b0, L_0x1d8b410, C4<0>, C4<0>; -L_0x1d8b1a0 .delay 1 (30000,30000,30000) L_0x1d8b1a0/d; -L_0x1d8b590/d .functor OR 1, L_0x1d8b600, L_0x1d8b7b0, C4<0>, C4<0>; -L_0x1d8b590 .delay 1 (30000,30000,30000) L_0x1d8b590/d; -v0x15cbd50_0 .net *"_s0", 0 0, L_0x1d8ada0; 1 drivers -v0x15cbe30_0 .net *"_s10", 0 0, L_0x1d8b2b0; 1 drivers -v0x15c1730_0 .net *"_s12", 0 0, L_0x1d8b410; 1 drivers -v0x15c1810_0 .net *"_s14", 0 0, L_0x1d8b600; 1 drivers -v0x15b7110_0 .net *"_s16", 0 0, L_0x1d8b7b0; 1 drivers -v0x15b7220_0 .net *"_s3", 0 0, L_0x1d8ae10; 1 drivers -v0x15acaf0_0 .net *"_s5", 0 0, L_0x1d8af70; 1 drivers -v0x15acbd0_0 .net *"_s6", 0 0, L_0x1d8b1a0; 1 drivers -v0x1739440_0 .net "in", 3 0, L_0x1d8b9e0; 1 drivers -v0x1afd8c0_0 .net "ors", 1 0, L_0x1d8b0b0; 1 drivers -v0x1afd9a0_0 .net "out", 0 0, L_0x1d8b590; 1 drivers -L_0x1d8ae10 .part L_0x1d8b9e0, 0, 1; -L_0x1d8af70 .part L_0x1d8b9e0, 1, 1; -L_0x1d8b0b0 .concat8 [ 1 1 0 0], L_0x1d8ada0, L_0x1d8b1a0; -L_0x1d8b2b0 .part L_0x1d8b9e0, 2, 1; -L_0x1d8b410 .part L_0x1d8b9e0, 3, 1; -L_0x1d8b600 .part L_0x1d8b0b0, 0, 1; -L_0x1d8b7b0 .part L_0x1d8b0b0, 1, 1; -S_0x1a36250 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1811df0; +L_0x121e540/d .functor OR 1, L_0x121e5b0, L_0x121e710, C4<0>, C4<0>; +L_0x121e540 .delay 1 (30000,30000,30000) L_0x121e540/d; +L_0x121e940/d .functor OR 1, L_0x121ea50, L_0x121ebb0, C4<0>, C4<0>; +L_0x121e940 .delay 1 (30000,30000,30000) L_0x121e940/d; +L_0x121ed30/d .functor OR 1, L_0x121eda0, L_0x121ef50, C4<0>, C4<0>; +L_0x121ed30 .delay 1 (30000,30000,30000) L_0x121ed30/d; +v0xcda520_0 .net *"_s0", 0 0, L_0x121e540; 1 drivers +v0xc97d10_0 .net *"_s10", 0 0, L_0x121ea50; 1 drivers +v0xc97df0_0 .net *"_s12", 0 0, L_0x121ebb0; 1 drivers +v0xc76950_0 .net *"_s14", 0 0, L_0x121eda0; 1 drivers +v0xc76a30_0 .net *"_s16", 0 0, L_0x121ef50; 1 drivers +v0xc55510_0 .net *"_s3", 0 0, L_0x121e5b0; 1 drivers +v0xc555f0_0 .net *"_s5", 0 0, L_0x121e710; 1 drivers +v0xc34040_0 .net *"_s6", 0 0, L_0x121e940; 1 drivers +v0xc34120_0 .net "in", 3 0, L_0x121f180; 1 drivers +v0xc12ce0_0 .net "ors", 1 0, L_0x121e850; 1 drivers +v0xbf1790_0 .net "out", 0 0, L_0x121ed30; 1 drivers +L_0x121e5b0 .part L_0x121f180, 0, 1; +L_0x121e710 .part L_0x121f180, 1, 1; +L_0x121e850 .concat8 [ 1 1 0 0], L_0x121e540, L_0x121e940; +L_0x121ea50 .part L_0x121f180, 2, 1; +L_0x121ebb0 .part L_0x121f180, 3, 1; +L_0x121eda0 .part L_0x121e850, 0, 1; +L_0x121ef50 .part L_0x121e850, 1, 1; +S_0xde3b20 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xc13330; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1930850_0 .net "ands", 7 0, L_0x1d86040; 1 drivers -v0x1930960_0 .net "in", 7 0, L_0x1d844a0; alias, 1 drivers -v0x1930a20_0 .net "out", 0 0, L_0x1d88040; alias, 1 drivers -v0x190f580_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1847fc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1a36250; +v0xff28b0_0 .net "ands", 7 0, L_0x12197e0; 1 drivers +v0xff2950_0 .net "in", 7 0, L_0x1217c40; alias, 1 drivers +v0xff29f0_0 .net "out", 0 0, L_0x121b7e0; alias, 1 drivers +v0xff2a90_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xdc27c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xde3b20; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1a3a6a0_0 .net "A", 7 0, L_0x1d844a0; alias, 1 drivers -v0x1a19190_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1a19230_0 .net *"_s0", 0 0, L_0x1d84830; 1 drivers -v0x1a192f0_0 .net *"_s12", 0 0, L_0x1d851f0; 1 drivers -v0x19f7df0_0 .net *"_s16", 0 0, L_0x1d85550; 1 drivers -v0x19f7f20_0 .net *"_s20", 0 0, L_0x1d85980; 1 drivers -v0x19d6a30_0 .net *"_s24", 0 0, L_0x1d85cb0; 1 drivers -v0x19d6af0_0 .net *"_s28", 0 0, L_0x1d85c40; 1 drivers -v0x17c3420_0 .net *"_s4", 0 0, L_0x1d84bd0; 1 drivers -v0x17a2040_0 .net *"_s8", 0 0, L_0x1d84ee0; 1 drivers -v0x17a2120_0 .net "out", 7 0, L_0x1d86040; alias, 1 drivers -L_0x1d84940 .part L_0x1d844a0, 0, 1; -L_0x1d84b30 .part v0x1d6daa0_0, 0, 1; -L_0x1d84c90 .part L_0x1d844a0, 1, 1; -L_0x1d84df0 .part v0x1d6daa0_0, 1, 1; -L_0x1d84fa0 .part L_0x1d844a0, 2, 1; -L_0x1d85100 .part v0x1d6daa0_0, 2, 1; -L_0x1d852b0 .part L_0x1d844a0, 3, 1; -L_0x1d85410 .part v0x1d6daa0_0, 3, 1; -L_0x1d85610 .part L_0x1d844a0, 4, 1; -L_0x1d85880 .part v0x1d6daa0_0, 4, 1; -L_0x1d859f0 .part L_0x1d844a0, 5, 1; -L_0x1d85b50 .part v0x1d6daa0_0, 5, 1; -L_0x1d85d70 .part L_0x1d844a0, 6, 1; -L_0x1d85ed0 .part v0x1d6daa0_0, 6, 1; -LS_0x1d86040_0_0 .concat8 [ 1 1 1 1], L_0x1d84830, L_0x1d84bd0, L_0x1d84ee0, L_0x1d851f0; -LS_0x1d86040_0_4 .concat8 [ 1 1 1 1], L_0x1d85550, L_0x1d85980, L_0x1d85cb0, L_0x1d85c40; -L_0x1d86040 .concat8 [ 4 4 0 0], LS_0x1d86040_0_0, LS_0x1d86040_0_4; -L_0x1d86400 .part L_0x1d844a0, 7, 1; -L_0x1d865f0 .part v0x1d6daa0_0, 7, 1; -S_0x1822b30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x1a57700 .param/l "i" 0 4 54, +C4<00>; -L_0x1d84830/d .functor AND 1, L_0x1d84940, L_0x1d84b30, C4<1>, C4<1>; -L_0x1d84830 .delay 1 (30000,30000,30000) L_0x1d84830/d; -v0x18017b0_0 .net *"_s0", 0 0, L_0x1d84940; 1 drivers -v0x1801890_0 .net *"_s1", 0 0, L_0x1d84b30; 1 drivers -S_0x17e0460 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x17bf120 .param/l "i" 0 4 54, +C4<01>; -L_0x1d84bd0/d .functor AND 1, L_0x1d84c90, L_0x1d84df0, C4<1>, C4<1>; -L_0x1d84bd0 .delay 1 (30000,30000,30000) L_0x1d84bd0/d; -v0x17bf1e0_0 .net *"_s0", 0 0, L_0x1d84c90; 1 drivers -v0x179dcf0_0 .net *"_s1", 0 0, L_0x1d84df0; 1 drivers -S_0x177c870 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x179de40 .param/l "i" 0 4 54, +C4<010>; -L_0x1d84ee0/d .functor AND 1, L_0x1d84fa0, L_0x1d85100, C4<1>, C4<1>; -L_0x1d84ee0 .delay 1 (30000,30000,30000) L_0x1d84ee0/d; -v0x175b430_0 .net *"_s0", 0 0, L_0x1d84fa0; 1 drivers -v0x175b510_0 .net *"_s1", 0 0, L_0x1d85100; 1 drivers -S_0x1739f20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x1719690 .param/l "i" 0 4 54, +C4<011>; -L_0x1d851f0/d .functor AND 1, L_0x1d852b0, L_0x1d85410, C4<1>, C4<1>; -L_0x1d851f0 .delay 1 (30000,30000,30000) L_0x1d851f0/d; -v0x18494c0_0 .net *"_s0", 0 0, L_0x1d852b0; 1 drivers -v0x18495a0_0 .net *"_s1", 0 0, L_0x1d85410; 1 drivers -S_0x1828160 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x17e5a00 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d85550/d .functor AND 1, L_0x1d85610, L_0x1d85880, C4<1>, C4<1>; -L_0x1d85550 .delay 1 (30000,30000,30000) L_0x1d85550/d; -v0x17e5ac0_0 .net *"_s0", 0 0, L_0x1d85610; 1 drivers -v0x1b01c30_0 .net *"_s1", 0 0, L_0x1d85880; 1 drivers -S_0x1b006c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x1b01d10 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d85980/d .functor AND 1, L_0x1d859f0, L_0x1d85b50, C4<1>, C4<1>; -L_0x1d85980 .delay 1 (30000,30000,30000) L_0x1d85980/d; -v0x1b03030_0 .net *"_s0", 0 0, L_0x1d859f0; 1 drivers -v0x1b03110_0 .net *"_s1", 0 0, L_0x1d85b50; 1 drivers -S_0x1abf430 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x1abf5d0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d85cb0/d .functor AND 1, L_0x1d85d70, L_0x1d85ed0, C4<1>, C4<1>; -L_0x1d85cb0 .delay 1 (30000,30000,30000) L_0x1d85cb0/d; -v0x1a9e0d0_0 .net *"_s0", 0 0, L_0x1d85d70; 1 drivers -v0x1a9e1b0_0 .net *"_s1", 0 0, L_0x1d85ed0; 1 drivers -S_0x1a7cce0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1847fc0; - .timescale -9 -12; -P_0x1a5b940 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d85c40/d .functor AND 1, L_0x1d86400, L_0x1d865f0, C4<1>, C4<1>; -L_0x1d85c40 .delay 1 (30000,30000,30000) L_0x1d85c40/d; -v0x1a5b9e0_0 .net *"_s0", 0 0, L_0x1d86400; 1 drivers -v0x1a3a5c0_0 .net *"_s1", 0 0, L_0x1d865f0; 1 drivers -S_0x17a3440 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1a36250; +v0xf56e40_0 .net "A", 7 0, L_0x1217c40; alias, 1 drivers +v0xf359c0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xf35a80_0 .net *"_s0", 0 0, L_0x1217fd0; 1 drivers +v0xf14590_0 .net *"_s12", 0 0, L_0x1218990; 1 drivers +v0xf14670_0 .net *"_s16", 0 0, L_0x1218cf0; 1 drivers +v0xef31f0_0 .net *"_s20", 0 0, L_0x1219120; 1 drivers +v0xef32d0_0 .net *"_s24", 0 0, L_0x1219450; 1 drivers +v0xed1ea0_0 .net *"_s28", 0 0, L_0x12193e0; 1 drivers +v0xed1f80_0 .net *"_s4", 0 0, L_0x1218370; 1 drivers +v0xc7ad90_0 .net *"_s8", 0 0, L_0x1218680; 1 drivers +v0xc5ac80_0 .net "out", 7 0, L_0x12197e0; alias, 1 drivers +L_0x12180e0 .part L_0x1217c40, 0, 1; +L_0x12182d0 .part v0x12010b0_0, 0, 1; +L_0x1218430 .part L_0x1217c40, 1, 1; +L_0x1218590 .part v0x12010b0_0, 1, 1; +L_0x1218740 .part L_0x1217c40, 2, 1; +L_0x12188a0 .part v0x12010b0_0, 2, 1; +L_0x1218a50 .part L_0x1217c40, 3, 1; +L_0x1218bb0 .part v0x12010b0_0, 3, 1; +L_0x1218db0 .part L_0x1217c40, 4, 1; +L_0x1219020 .part v0x12010b0_0, 4, 1; +L_0x1219190 .part L_0x1217c40, 5, 1; +L_0x12192f0 .part v0x12010b0_0, 5, 1; +L_0x1219510 .part L_0x1217c40, 6, 1; +L_0x1219670 .part v0x12010b0_0, 6, 1; +LS_0x12197e0_0_0 .concat8 [ 1 1 1 1], L_0x1217fd0, L_0x1218370, L_0x1218680, L_0x1218990; +LS_0x12197e0_0_4 .concat8 [ 1 1 1 1], L_0x1218cf0, L_0x1219120, L_0x1219450, L_0x12193e0; +L_0x12197e0 .concat8 [ 4 4 0 0], LS_0x12197e0_0_0, LS_0x12197e0_0_4; +L_0x1219ba0 .part L_0x1217c40, 7, 1; +L_0x1219d90 .part v0x12010b0_0, 7, 1; +S_0xeadfd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xdc2940 .param/l "i" 0 4 54, +C4<00>; +L_0x1217fd0/d .functor AND 1, L_0x12180e0, L_0x12182d0, C4<1>, C4<1>; +L_0x1217fd0 .delay 1 (30000,30000,30000) L_0x1217fd0/d; +v0xe8cc90_0 .net *"_s0", 0 0, L_0x12180e0; 1 drivers +v0xe8cd70_0 .net *"_s1", 0 0, L_0x12182d0; 1 drivers +S_0xe6b910 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xe4a650 .param/l "i" 0 4 54, +C4<01>; +L_0x1218370/d .functor AND 1, L_0x1218430, L_0x1218590, C4<1>, C4<1>; +L_0x1218370 .delay 1 (30000,30000,30000) L_0x1218370/d; +v0xe4a710_0 .net *"_s0", 0 0, L_0x1218430; 1 drivers +v0xe292f0_0 .net *"_s1", 0 0, L_0x1218590; 1 drivers +S_0xe08020 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xe293d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1218680/d .functor AND 1, L_0x1218740, L_0x12188a0, C4<1>, C4<1>; +L_0x1218680 .delay 1 (30000,30000,30000) L_0x1218680/d; +v0xde6cd0_0 .net *"_s0", 0 0, L_0x1218740; 1 drivers +v0xde6db0_0 .net *"_s1", 0 0, L_0x12188a0; 1 drivers +S_0xdc5970 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xe29470 .param/l "i" 0 4 54, +C4<011>; +L_0x1218990/d .functor AND 1, L_0x1218a50, L_0x1218bb0, C4<1>, C4<1>; +L_0x1218990 .delay 1 (30000,30000,30000) L_0x1218990/d; +v0xda4630_0 .net *"_s0", 0 0, L_0x1218a50; 1 drivers +v0xda4710_0 .net *"_s1", 0 0, L_0x1218bb0; 1 drivers +S_0xd83240 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xd61ed0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1218cf0/d .functor AND 1, L_0x1218db0, L_0x1219020, C4<1>, C4<1>; +L_0x1218cf0 .delay 1 (30000,30000,30000) L_0x1218cf0/d; +v0xd61f90_0 .net *"_s0", 0 0, L_0x1218db0; 1 drivers +v0xd40ab0_0 .net *"_s1", 0 0, L_0x1219020; 1 drivers +S_0xd1f6c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xd40bb0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1219120/d .functor AND 1, L_0x1219190, L_0x12192f0, C4<1>, C4<1>; +L_0x1219120 .delay 1 (30000,30000,30000) L_0x1219120/d; +v0xcfe360_0 .net *"_s0", 0 0, L_0x1219190; 1 drivers +v0xcfe420_0 .net *"_s1", 0 0, L_0x12192f0; 1 drivers +S_0xcbd1a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xf98060 .param/l "i" 0 4 54, +C4<0110>; +L_0x1219450/d .functor AND 1, L_0x1219510, L_0x1219670, C4<1>, C4<1>; +L_0x1219450 .delay 1 (30000,30000,30000) L_0x1219450/d; +v0xf98120_0 .net *"_s0", 0 0, L_0x1219510; 1 drivers +v0xf96af0_0 .net *"_s1", 0 0, L_0x1219670; 1 drivers +S_0xf99460 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xdc27c0; + .timescale -9 -12; +P_0xf99600 .param/l "i" 0 4 54, +C4<0111>; +L_0x12193e0/d .functor AND 1, L_0x1219ba0, L_0x1219d90, C4<1>, C4<1>; +L_0x12193e0 .delay 1 (30000,30000,30000) L_0x12193e0/d; +v0xf96c20_0 .net *"_s0", 0 0, L_0x1219ba0; 1 drivers +v0xf56d60_0 .net *"_s1", 0 0, L_0x1219d90; 1 drivers +S_0xc383b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xde3b20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d88040/d .functor OR 1, L_0x1d88100, L_0x1d882b0, C4<0>, C4<0>; -L_0x1d88040 .delay 1 (30000,30000,30000) L_0x1d88040/d; -v0x1972e50_0 .net *"_s10", 0 0, L_0x1d88100; 1 drivers -v0x1972f30_0 .net *"_s12", 0 0, L_0x1d882b0; 1 drivers -v0x1973010_0 .net "in", 7 0, L_0x1d86040; alias, 1 drivers -v0x1951b40_0 .net "ors", 1 0, L_0x1d87e60; 1 drivers -v0x1951c00_0 .net "out", 0 0, L_0x1d88040; alias, 1 drivers -L_0x1d87230 .part L_0x1d86040, 0, 4; -L_0x1d87e60 .concat8 [ 1 1 0 0], L_0x1d86f20, L_0x1d87b50; -L_0x1d87fa0 .part L_0x1d86040, 4, 4; -L_0x1d88100 .part L_0x1d87e60, 0, 1; -L_0x1d882b0 .part L_0x1d87e60, 1, 1; -S_0x1780be0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x17a3440; +L_0x121b7e0/d .functor OR 1, L_0x121b8a0, L_0x121ba50, C4<0>, C4<0>; +L_0x121b7e0 .delay 1 (30000,30000,30000) L_0x121b7e0/d; +v0xff2590_0 .net *"_s10", 0 0, L_0x121b8a0; 1 drivers +v0xff2630_0 .net *"_s12", 0 0, L_0x121ba50; 1 drivers +v0xff26d0_0 .net "in", 7 0, L_0x12197e0; alias, 1 drivers +v0xff2770_0 .net "ors", 1 0, L_0x121b600; 1 drivers +v0xff2810_0 .net "out", 0 0, L_0x121b7e0; alias, 1 drivers +L_0x121a9d0 .part L_0x12197e0, 0, 4; +L_0x121b600 .concat8 [ 1 1 0 0], L_0x121a6c0, L_0x121b2f0; +L_0x121b740 .part L_0x12197e0, 4, 4; +L_0x121b8a0 .part L_0x121b600, 0, 1; +L_0x121ba50 .part L_0x121b600, 1, 1; +S_0xc16f80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xc383b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d866e0/d .functor OR 1, L_0x1d867a0, L_0x1d86900, C4<0>, C4<0>; -L_0x1d866e0 .delay 1 (30000,30000,30000) L_0x1d866e0/d; -L_0x1d86b30/d .functor OR 1, L_0x1d86c40, L_0x1d86da0, C4<0>, C4<0>; -L_0x1d86b30 .delay 1 (30000,30000,30000) L_0x1d86b30/d; -L_0x1d86f20/d .functor OR 1, L_0x1d86f90, L_0x1d87140, C4<0>, C4<0>; -L_0x1d86f20 .delay 1 (30000,30000,30000) L_0x1d86f20/d; -v0x175f750_0 .net *"_s0", 0 0, L_0x1d866e0; 1 drivers -v0x175f830_0 .net *"_s10", 0 0, L_0x1d86c40; 1 drivers -v0x173f5f0_0 .net *"_s12", 0 0, L_0x1d86da0; 1 drivers -v0x173f6b0_0 .net *"_s14", 0 0, L_0x1d86f90; 1 drivers -v0x171cd60_0 .net *"_s16", 0 0, L_0x1d87140; 1 drivers -v0x171ce40_0 .net *"_s3", 0 0, L_0x1d867a0; 1 drivers -v0x16fc570_0 .net *"_s5", 0 0, L_0x1d86900; 1 drivers -v0x16fc650_0 .net *"_s6", 0 0, L_0x1d86b30; 1 drivers -v0x1b210c0_0 .net "in", 3 0, L_0x1d87230; 1 drivers -v0x1b21230_0 .net "ors", 1 0, L_0x1d86a40; 1 drivers -v0x1afd130_0 .net "out", 0 0, L_0x1d86f20; 1 drivers -L_0x1d867a0 .part L_0x1d87230, 0, 1; -L_0x1d86900 .part L_0x1d87230, 1, 1; -L_0x1d86a40 .concat8 [ 1 1 0 0], L_0x1d866e0, L_0x1d86b30; -L_0x1d86c40 .part L_0x1d87230, 2, 1; -L_0x1d86da0 .part L_0x1d87230, 3, 1; -L_0x1d86f90 .part L_0x1d86a40, 0, 1; -L_0x1d87140 .part L_0x1d86a40, 1, 1; -S_0x1b1e280 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x17a3440; +L_0x1219e80/d .functor OR 1, L_0x1219f40, L_0x121a0a0, C4<0>, C4<0>; +L_0x1219e80 .delay 1 (30000,30000,30000) L_0x1219e80/d; +L_0x121a2d0/d .functor OR 1, L_0x121a3e0, L_0x121a540, C4<0>, C4<0>; +L_0x121a2d0 .delay 1 (30000,30000,30000) L_0x121a2d0/d; +L_0x121a6c0/d .functor OR 1, L_0x121a730, L_0x121a8e0, C4<0>, C4<0>; +L_0x121a6c0 .delay 1 (30000,30000,30000) L_0x121a6c0/d; +v0xc5ade0_0 .net *"_s0", 0 0, L_0x1219e80; 1 drivers +v0xc18380_0 .net *"_s10", 0 0, L_0x121a3e0; 1 drivers +v0xc18460_0 .net *"_s12", 0 0, L_0x121a540; 1 drivers +v0xbf5b00_0 .net *"_s14", 0 0, L_0x121a730; 1 drivers +v0xbf5be0_0 .net *"_s16", 0 0, L_0x121a8e0; 1 drivers +v0xbd4620_0 .net *"_s3", 0 0, L_0x1219f40; 1 drivers +v0xbd4700_0 .net *"_s5", 0 0, L_0x121a0a0; 1 drivers +v0xbd5a20_0 .net *"_s6", 0 0, L_0x121a2d0; 1 drivers +v0xbd5b00_0 .net "in", 3 0, L_0x121a9d0; 1 drivers +v0xbb32b0_0 .net "ors", 1 0, L_0x121a1e0; 1 drivers +v0xb92a30_0 .net "out", 0 0, L_0x121a6c0; 1 drivers +L_0x1219f40 .part L_0x121a9d0, 0, 1; +L_0x121a0a0 .part L_0x121a9d0, 1, 1; +L_0x121a1e0 .concat8 [ 1 1 0 0], L_0x1219e80, L_0x121a2d0; +L_0x121a3e0 .part L_0x121a9d0, 2, 1; +L_0x121a540 .part L_0x121a9d0, 3, 1; +L_0x121a730 .part L_0x121a1e0, 0, 1; +L_0x121a8e0 .part L_0x121a1e0, 1, 1; +S_0xb93e30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xc383b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d87360/d .functor OR 1, L_0x1d873d0, L_0x1d87530, C4<0>, C4<0>; -L_0x1d87360 .delay 1 (30000,30000,30000) L_0x1d87360/d; -L_0x1d87760/d .functor OR 1, L_0x1d87870, L_0x1d879d0, C4<0>, C4<0>; -L_0x1d87760 .delay 1 (30000,30000,30000) L_0x1d87760/d; -L_0x1d87b50/d .functor OR 1, L_0x1d87bc0, L_0x1d87d70, C4<0>, C4<0>; -L_0x1d87b50 .delay 1 (30000,30000,30000) L_0x1d87b50/d; -v0x1b1e420_0 .net *"_s0", 0 0, L_0x1d87360; 1 drivers -v0x1afd230_0 .net *"_s10", 0 0, L_0x1d87870; 1 drivers -v0x17e4540_0 .net *"_s12", 0 0, L_0x1d879d0; 1 drivers -v0x17e4600_0 .net *"_s14", 0 0, L_0x1d87bc0; 1 drivers -v0x17e46e0_0 .net *"_s16", 0 0, L_0x1d87d70; 1 drivers -v0x19b5530_0 .net *"_s3", 0 0, L_0x1d873d0; 1 drivers -v0x19b5610_0 .net *"_s5", 0 0, L_0x1d87530; 1 drivers -v0x19b56f0_0 .net *"_s6", 0 0, L_0x1d87760; 1 drivers -v0x1994180_0 .net "in", 3 0, L_0x1d87fa0; 1 drivers -v0x1994240_0 .net "ors", 1 0, L_0x1d87670; 1 drivers -v0x1994320_0 .net "out", 0 0, L_0x1d87b50; 1 drivers -L_0x1d873d0 .part L_0x1d87fa0, 0, 1; -L_0x1d87530 .part L_0x1d87fa0, 1, 1; -L_0x1d87670 .concat8 [ 1 1 0 0], L_0x1d87360, L_0x1d87760; -L_0x1d87870 .part L_0x1d87fa0, 2, 1; -L_0x1d879d0 .part L_0x1d87fa0, 3, 1; -L_0x1d87bc0 .part L_0x1d87670, 0, 1; -L_0x1d87d70 .part L_0x1d87670, 1, 1; -S_0x190f660 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1811df0; +L_0x121ab00/d .functor OR 1, L_0x121ab70, L_0x121acd0, C4<0>, C4<0>; +L_0x121ab00 .delay 1 (30000,30000,30000) L_0x121ab00/d; +L_0x121af00/d .functor OR 1, L_0x121b010, L_0x121b170, C4<0>, C4<0>; +L_0x121af00 .delay 1 (30000,30000,30000) L_0x121af00/d; +L_0x121b2f0/d .functor OR 1, L_0x121b360, L_0x121b510, C4<0>, C4<0>; +L_0x121b2f0 .delay 1 (30000,30000,30000) L_0x121b2f0/d; +v0xb92b50_0 .net *"_s0", 0 0, L_0x121ab00; 1 drivers +v0xcbbad0_0 .net *"_s10", 0 0, L_0x121b010; 1 drivers +v0xcbbb90_0 .net *"_s12", 0 0, L_0x121b170; 1 drivers +v0xcbbc50_0 .net *"_s14", 0 0, L_0x121b360; 1 drivers +v0xfb7440_0 .net *"_s16", 0 0, L_0x121b510; 1 drivers +v0xfb7570_0 .net *"_s3", 0 0, L_0x121ab70; 1 drivers +v0xfb4600_0 .net *"_s5", 0 0, L_0x121acd0; 1 drivers +v0xfb46e0_0 .net *"_s6", 0 0, L_0x121af00; 1 drivers +v0xfb47c0_0 .net "in", 3 0, L_0x121b740; 1 drivers +v0xfb5500_0 .net "ors", 1 0, L_0x121ae10; 1 drivers +v0xfb55e0_0 .net "out", 0 0, L_0x121b2f0; 1 drivers +L_0x121ab70 .part L_0x121b740, 0, 1; +L_0x121acd0 .part L_0x121b740, 1, 1; +L_0x121ae10 .concat8 [ 1 1 0 0], L_0x121ab00, L_0x121af00; +L_0x121b010 .part L_0x121b740, 2, 1; +L_0x121b170 .part L_0x121b740, 3, 1; +L_0x121b360 .part L_0x121ae10, 0, 1; +L_0x121b510 .part L_0x121ae10, 1, 1; +S_0xff2b30 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xc13330; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -1756,80 +1766,80 @@ S_0x190f660 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1811df0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1d83810/d .functor XNOR 1, L_0x1d8bee0, L_0x1d8c0d0, C4<0>, C4<0>; -L_0x1d83810 .delay 1 (20000,20000,20000) L_0x1d83810/d; -L_0x1d83a80/d .functor AND 1, L_0x1d8bee0, L_0x1d82900, C4<1>, C4<1>; -L_0x1d83a80 .delay 1 (30000,30000,30000) L_0x1d83a80/d; -L_0x1d83af0/d .functor AND 1, L_0x1d83810, L_0x1d8c200, C4<1>, C4<1>; -L_0x1d83af0 .delay 1 (30000,30000,30000) L_0x1d83af0/d; -L_0x1d83c50/d .functor OR 1, L_0x1d83af0, L_0x1d83a80, C4<0>, C4<0>; -L_0x1d83c50 .delay 1 (30000,30000,30000) L_0x1d83c50/d; -v0x18ee2d0_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers -v0x18ee3c0_0 .net "a_", 0 0, L_0x1d827f0; alias, 1 drivers -v0x18cceb0_0 .net "b", 0 0, L_0x1d8c0d0; alias, 1 drivers -v0x18ccfa0_0 .net "b_", 0 0, L_0x1d82900; alias, 1 drivers -v0x18cd040_0 .net "carryin", 0 0, L_0x1d8c200; alias, 1 drivers -v0x18abb00_0 .net "eq", 0 0, L_0x1d83810; 1 drivers -v0x18abbc0_0 .net "lt", 0 0, L_0x1d83a80; 1 drivers -v0x18abc80_0 .net "out", 0 0, L_0x1d83c50; 1 drivers -v0x188a760_0 .net "w0", 0 0, L_0x1d83af0; 1 drivers -S_0x1869380 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1811df0; +L_0x1216fb0/d .functor XNOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; +L_0x1216fb0 .delay 1 (20000,20000,20000) L_0x1216fb0/d; +L_0x1217220/d .functor AND 1, L_0x121f680, L_0x1215fb0, C4<1>, C4<1>; +L_0x1217220 .delay 1 (30000,30000,30000) L_0x1217220/d; +L_0x1217290/d .functor AND 1, L_0x1216fb0, L_0x121f9a0, C4<1>, C4<1>; +L_0x1217290 .delay 1 (30000,30000,30000) L_0x1217290/d; +L_0x12173f0/d .functor OR 1, L_0x1217290, L_0x1217220, C4<0>, C4<0>; +L_0x12173f0 .delay 1 (30000,30000,30000) L_0x12173f0/d; +v0xff2d50_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers +v0xff2df0_0 .net "a_", 0 0, L_0x1215ea0; alias, 1 drivers +v0xff2eb0_0 .net "b", 0 0, L_0x121f870; alias, 1 drivers +v0xff2fa0_0 .net "b_", 0 0, L_0x1215fb0; alias, 1 drivers +v0xff3040_0 .net "carryin", 0 0, L_0x121f9a0; alias, 1 drivers +v0xff3180_0 .net "eq", 0 0, L_0x1216fb0; 1 drivers +v0xff3240_0 .net "lt", 0 0, L_0x1217220; 1 drivers +v0xff3300_0 .net "out", 0 0, L_0x12173f0; 1 drivers +v0xff33c0_0 .net "w0", 0 0, L_0x1217290; 1 drivers +S_0xff35d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xc13330; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d835f0/d .functor OR 1, L_0x1d83140, L_0x1b61c20, C4<0>, C4<0>; -L_0x1d835f0 .delay 1 (30000,30000,30000) L_0x1d835f0/d; -v0x1b61820_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers -v0x1b61950_0 .net "b", 0 0, L_0x1d82900; alias, 1 drivers -v0x1b619f0_0 .net "c1", 0 0, L_0x1d83140; 1 drivers -v0x1b61a90_0 .net "c2", 0 0, L_0x1b61c20; 1 drivers -v0x1b61b30_0 .net "carryin", 0 0, L_0x1d8c200; alias, 1 drivers -v0x1b61cb0_0 .net "carryout", 0 0, L_0x1d835f0; 1 drivers -v0x1b61d50_0 .net "s1", 0 0, L_0x1d83080; 1 drivers -v0x1b61e40_0 .net "sum", 0 0, L_0x1d832a0; 1 drivers -S_0x18058e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1869380; +L_0x1216d90/d .functor OR 1, L_0x12168e0, L_0xff47d0, C4<0>, C4<0>; +L_0x1216d90 .delay 1 (30000,30000,30000) L_0x1216d90/d; +v0xff4360_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers +v0xff44b0_0 .net "b", 0 0, L_0x1215fb0; alias, 1 drivers +v0xff4570_0 .net "c1", 0 0, L_0x12168e0; 1 drivers +v0xff4610_0 .net "c2", 0 0, L_0xff47d0; 1 drivers +v0xff46e0_0 .net "carryin", 0 0, L_0x121f9a0; alias, 1 drivers +v0xff4860_0 .net "carryout", 0 0, L_0x1216d90; 1 drivers +v0xff4900_0 .net "s1", 0 0, L_0x1216820; 1 drivers +v0xff49a0_0 .net "sum", 0 0, L_0x1216a40; 1 drivers +S_0xff3820 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xff35d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d83080/d .functor XOR 1, L_0x1d8bee0, L_0x1d82900, C4<0>, C4<0>; -L_0x1d83080 .delay 1 (30000,30000,30000) L_0x1d83080/d; -L_0x1d83140/d .functor AND 1, L_0x1d8bee0, L_0x1d82900, C4<1>, C4<1>; -L_0x1d83140 .delay 1 (30000,30000,30000) L_0x1d83140/d; -v0x1869550_0 .net "a", 0 0, L_0x1d8bee0; alias, 1 drivers -v0x188a8e0_0 .net "b", 0 0, L_0x1d82900; alias, 1 drivers -v0x1b1f0b0_0 .net "carryout", 0 0, L_0x1d83140; alias, 1 drivers -v0x1b1f150_0 .net "sum", 0 0, L_0x1d83080; alias, 1 drivers -S_0x1b1f250 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1869380; +L_0x1216820/d .functor XOR 1, L_0x121f680, L_0x1215fb0, C4<0>, C4<0>; +L_0x1216820 .delay 1 (30000,30000,30000) L_0x1216820/d; +L_0x12168e0/d .functor AND 1, L_0x121f680, L_0x1215fb0, C4<1>, C4<1>; +L_0x12168e0 .delay 1 (30000,30000,30000) L_0x12168e0/d; +v0xff3a80_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers +v0xff3b40_0 .net "b", 0 0, L_0x1215fb0; alias, 1 drivers +v0xff3c00_0 .net "carryout", 0 0, L_0x12168e0; alias, 1 drivers +v0xff3ca0_0 .net "sum", 0 0, L_0x1216820; alias, 1 drivers +S_0xff3da0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xff35d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d832a0/d .functor XOR 1, L_0x1d83080, L_0x1d8c200, C4<0>, C4<0>; -L_0x1d832a0 .delay 1 (30000,30000,30000) L_0x1d832a0/d; -L_0x1b61c20/d .functor AND 1, L_0x1d83080, L_0x1d8c200, C4<1>, C4<1>; -L_0x1b61c20 .delay 1 (30000,30000,30000) L_0x1b61c20/d; -v0x1b615a0_0 .net "a", 0 0, L_0x1d83080; alias, 1 drivers -v0x1b61640_0 .net "b", 0 0, L_0x1d8c200; alias, 1 drivers -v0x1b616e0_0 .net "carryout", 0 0, L_0x1b61c20; alias, 1 drivers -v0x1b61780_0 .net "sum", 0 0, L_0x1d832a0; alias, 1 drivers -S_0x1b63240 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1822ed0; - .timescale -9 -12; -L_0x7f72592da258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d8bf80/d .functor OR 1, L_0x7f72592da258, L_0x7f72592da2a0, C4<0>, C4<0>; -L_0x1d8bf80 .delay 1 (30000,30000,30000) L_0x1d8bf80/d; -v0x1b63430_0 .net/2u *"_s0", 0 0, L_0x7f72592da258; 1 drivers -v0x1b63510_0 .net/2u *"_s2", 0 0, L_0x7f72592da2a0; 1 drivers -S_0x1b635f0 .scope generate, "alu_slices[3]" "alu_slices[3]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1b63800 .param/l "i" 0 3 37, +C4<011>; -S_0x1b638c0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b635f0; +L_0x1216a40/d .functor XOR 1, L_0x1216820, L_0x121f9a0, C4<0>, C4<0>; +L_0x1216a40 .delay 1 (30000,30000,30000) L_0x1216a40/d; +L_0xff47d0/d .functor AND 1, L_0x1216820, L_0x121f9a0, C4<1>, C4<1>; +L_0xff47d0 .delay 1 (30000,30000,30000) L_0xff47d0/d; +v0xff4000_0 .net "a", 0 0, L_0x1216820; alias, 1 drivers +v0xff40a0_0 .net "b", 0 0, L_0x121f9a0; alias, 1 drivers +v0xff4140_0 .net "carryout", 0 0, L_0xff47d0; alias, 1 drivers +v0xff4210_0 .net "sum", 0 0, L_0x1216a40; alias, 1 drivers +S_0xff5dc0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0xc23180; + .timescale -9 -12; +L_0x2b0ab3d05258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d052a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x121f720/d .functor OR 1, L_0x2b0ab3d05258, L_0x2b0ab3d052a0, C4<0>, C4<0>; +L_0x121f720 .delay 1 (30000,30000,30000) L_0x121f720/d; +v0xff5fb0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05258; 1 drivers +v0xff6090_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d052a0; 1 drivers +S_0xff6170 .scope generate, "alu_slices[3]" "alu_slices[3]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0xff6380 .param/l "i" 0 3 41, +C4<011>; +S_0xff6440 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xff6170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -1838,445 +1848,445 @@ S_0x1b638c0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b635f0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1d8c400/d .functor NOT 1, L_0x1d95c10, C4<0>, C4<0>, C4<0>; -L_0x1d8c400 .delay 1 (10000,10000,10000) L_0x1d8c400/d; -L_0x1d8c510/d .functor NOT 1, L_0x1d95d70, C4<0>, C4<0>, C4<0>; -L_0x1d8c510 .delay 1 (10000,10000,10000) L_0x1d8c510/d; -L_0x1d8d560/d .functor XOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; -L_0x1d8d560 .delay 1 (30000,30000,30000) L_0x1d8d560/d; -L_0x7f72592da2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d8dc10/d .functor OR 1, L_0x7f72592da2e8, L_0x7f72592da330, C4<0>, C4<0>; -L_0x1d8dc10 .delay 1 (30000,30000,30000) L_0x1d8dc10/d; -L_0x1d8de10/d .functor AND 1, L_0x1d95c10, L_0x1d95d70, C4<1>, C4<1>; -L_0x1d8de10 .delay 1 (30000,30000,30000) L_0x1d8de10/d; -L_0x1d8ded0/d .functor NAND 1, L_0x1d95c10, L_0x1d95d70, C4<1>, C4<1>; -L_0x1d8ded0 .delay 1 (20000,20000,20000) L_0x1d8ded0/d; -L_0x1d8e030/d .functor XOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; -L_0x1d8e030 .delay 1 (20000,20000,20000) L_0x1d8e030/d; -L_0x1d8e4e0/d .functor OR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; -L_0x1d8e4e0 .delay 1 (30000,30000,30000) L_0x1d8e4e0/d; -L_0x1d95b10/d .functor NOT 1, L_0x1d91d70, C4<0>, C4<0>, C4<0>; -L_0x1d95b10 .delay 1 (10000,10000,10000) L_0x1d95b10/d; -v0x1b71f80_0 .net "A", 0 0, L_0x1d95c10; 1 drivers -v0x1b72040_0 .net "A_", 0 0, L_0x1d8c400; 1 drivers -v0x1b72100_0 .net "B", 0 0, L_0x1d95d70; 1 drivers -v0x1b721d0_0 .net "B_", 0 0, L_0x1d8c510; 1 drivers -v0x1b72270_0 .net *"_s12", 0 0, L_0x1d8dc10; 1 drivers -v0x1b72360_0 .net/2s *"_s14", 0 0, L_0x7f72592da2e8; 1 drivers -v0x1b72420_0 .net/2s *"_s16", 0 0, L_0x7f72592da330; 1 drivers -v0x1b72500_0 .net *"_s18", 0 0, L_0x1d8de10; 1 drivers -v0x1b725e0_0 .net *"_s20", 0 0, L_0x1d8ded0; 1 drivers -v0x1b72750_0 .net *"_s22", 0 0, L_0x1d8e030; 1 drivers -v0x1b72830_0 .net *"_s24", 0 0, L_0x1d8e4e0; 1 drivers -o0x7f725935d2b8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1b72910_0 name=_s30 -o0x7f725935d2e8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1b729f0_0 name=_s32 -v0x1b72ad0_0 .net *"_s8", 0 0, L_0x1d8d560; 1 drivers -v0x1b72bb0_0 .net "carryin", 0 0, L_0x1d95e10; 1 drivers -v0x1b72c50_0 .net "carryout", 0 0, L_0x1d957b0; 1 drivers -v0x1b72cf0_0 .net "carryouts", 7 0, L_0x1ebf060; 1 drivers -v0x1b72ea0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b72f40_0 .net "result", 0 0, L_0x1d91d70; 1 drivers -v0x1b73030_0 .net "results", 7 0, L_0x1d8e2b0; 1 drivers -v0x1b73140_0 .net "zero", 0 0, L_0x1d95b10; 1 drivers -LS_0x1d8e2b0_0_0 .concat8 [ 1 1 1 1], L_0x1d8ca30, L_0x1d8d060, L_0x1d8d560, L_0x1d8dc10; -LS_0x1d8e2b0_0_4 .concat8 [ 1 1 1 1], L_0x1d8de10, L_0x1d8ded0, L_0x1d8e030, L_0x1d8e4e0; -L_0x1d8e2b0 .concat8 [ 4 4 0 0], LS_0x1d8e2b0_0_0, LS_0x1d8e2b0_0_4; -LS_0x1ebf060_0_0 .concat [ 1 1 1 1], L_0x1d8cce0, L_0x1d8d400, o0x7f725935d2b8, L_0x1d8da60; -LS_0x1ebf060_0_4 .concat [ 4 0 0 0], o0x7f725935d2e8; -L_0x1ebf060 .concat [ 4 4 0 0], LS_0x1ebf060_0_0, LS_0x1ebf060_0_4; -S_0x1b63b40 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b638c0; +L_0x121fba0/d .functor NOT 1, L_0x1229330, C4<0>, C4<0>, C4<0>; +L_0x121fba0 .delay 1 (10000,10000,10000) L_0x121fba0/d; +L_0x121fcb0/d .functor NOT 1, L_0x1229490, C4<0>, C4<0>, C4<0>; +L_0x121fcb0 .delay 1 (10000,10000,10000) L_0x121fcb0/d; +L_0x1220ba0/d .functor XOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; +L_0x1220ba0 .delay 1 (30000,30000,30000) L_0x1220ba0/d; +L_0x2b0ab3d052e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1221250/d .functor OR 1, L_0x2b0ab3d052e8, L_0x2b0ab3d05330, C4<0>, C4<0>; +L_0x1221250 .delay 1 (30000,30000,30000) L_0x1221250/d; +L_0x1221450/d .functor AND 1, L_0x1229330, L_0x1229490, C4<1>, C4<1>; +L_0x1221450 .delay 1 (30000,30000,30000) L_0x1221450/d; +L_0x1221510/d .functor NAND 1, L_0x1229330, L_0x1229490, C4<1>, C4<1>; +L_0x1221510 .delay 1 (20000,20000,20000) L_0x1221510/d; +L_0x1221670/d .functor XOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; +L_0x1221670 .delay 1 (20000,20000,20000) L_0x1221670/d; +L_0x1221b20/d .functor OR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; +L_0x1221b20 .delay 1 (30000,30000,30000) L_0x1221b20/d; +L_0x1229230/d .functor NOT 1, L_0x1225490, C4<0>, C4<0>, C4<0>; +L_0x1229230 .delay 1 (10000,10000,10000) L_0x1229230/d; +v0x1004c10_0 .net "A", 0 0, L_0x1229330; 1 drivers +v0x1004cd0_0 .net "A_", 0 0, L_0x121fba0; 1 drivers +v0x1004d90_0 .net "B", 0 0, L_0x1229490; 1 drivers +v0x1004e60_0 .net "B_", 0 0, L_0x121fcb0; 1 drivers +v0x1004f00_0 .net *"_s12", 0 0, L_0x1221250; 1 drivers +v0x1004ff0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d052e8; 1 drivers +v0x10050b0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05330; 1 drivers +v0x1005190_0 .net *"_s18", 0 0, L_0x1221450; 1 drivers +v0x1005270_0 .net *"_s20", 0 0, L_0x1221510; 1 drivers +v0x10053e0_0 .net *"_s22", 0 0, L_0x1221670; 1 drivers +v0x10054c0_0 .net *"_s24", 0 0, L_0x1221b20; 1 drivers +o0x2b0ab3cac2b8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10055a0_0 name=_s30 +o0x2b0ab3cac2e8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1005680_0 name=_s32 +v0x1005760_0 .net *"_s8", 0 0, L_0x1220ba0; 1 drivers +v0x1005840_0 .net "carryin", 0 0, L_0x1229530; 1 drivers +v0x10058e0_0 .net "carryout", 0 0, L_0x1228ed0; 1 drivers +v0x1005980_0 .net "carryouts", 7 0, L_0x1353410; 1 drivers +v0x1005b30_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1005bd0_0 .net "result", 0 0, L_0x1225490; 1 drivers +v0x1005cc0_0 .net "results", 7 0, L_0x12218f0; 1 drivers +v0x1005dd0_0 .net "zero", 0 0, L_0x1229230; 1 drivers +LS_0x12218f0_0_0 .concat8 [ 1 1 1 1], L_0x1220070, L_0x12206f0, L_0x1220ba0, L_0x1221250; +LS_0x12218f0_0_4 .concat8 [ 1 1 1 1], L_0x1221450, L_0x1221510, L_0x1221670, L_0x1221b20; +L_0x12218f0 .concat8 [ 4 4 0 0], LS_0x12218f0_0_0, LS_0x12218f0_0_4; +LS_0x1353410_0_0 .concat [ 1 1 1 1], L_0x1220370, L_0x1220a40, o0x2b0ab3cac2b8, L_0x12210a0; +LS_0x1353410_0_4 .concat [ 4 0 0 0], o0x2b0ab3cac2e8; +L_0x1353410 .concat [ 4 4 0 0], LS_0x1353410_0_0, LS_0x1353410_0_4; +S_0xff66c0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xff6440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d8cce0/d .functor OR 1, L_0x1d8c7c0, L_0x1d8cb80, C4<0>, C4<0>; -L_0x1d8cce0 .delay 1 (30000,30000,30000) L_0x1d8cce0/d; -v0x1b64970_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers -v0x1b64a30_0 .net "b", 0 0, L_0x1d95d70; alias, 1 drivers -v0x1b64b00_0 .net "c1", 0 0, L_0x1d8c7c0; 1 drivers -v0x1b64c00_0 .net "c2", 0 0, L_0x1d8cb80; 1 drivers -v0x1b64cd0_0 .net "carryin", 0 0, L_0x1d95e10; alias, 1 drivers -v0x1b64dc0_0 .net "carryout", 0 0, L_0x1d8cce0; 1 drivers -v0x1b64e60_0 .net "s1", 0 0, L_0x1d8c700; 1 drivers -v0x1b64f50_0 .net "sum", 0 0, L_0x1d8ca30; 1 drivers -S_0x1b63db0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b63b40; +L_0x1220370/d .functor OR 1, L_0x121fea0, L_0x1220260, C4<0>, C4<0>; +L_0x1220370 .delay 1 (30000,30000,30000) L_0x1220370/d; +v0xff74f0_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers +v0xff75b0_0 .net "b", 0 0, L_0x1229490; alias, 1 drivers +v0xff7680_0 .net "c1", 0 0, L_0x121fea0; 1 drivers +v0xff7780_0 .net "c2", 0 0, L_0x1220260; 1 drivers +v0xff7850_0 .net "carryin", 0 0, L_0x1229530; alias, 1 drivers +v0xff7940_0 .net "carryout", 0 0, L_0x1220370; 1 drivers +v0xff79e0_0 .net "s1", 0 0, L_0x1219760; 1 drivers +v0xff7ad0_0 .net "sum", 0 0, L_0x1220070; 1 drivers +S_0xff6930 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xff66c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d8c700/d .functor XOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; -L_0x1d8c700 .delay 1 (30000,30000,30000) L_0x1d8c700/d; -L_0x1d8c7c0/d .functor AND 1, L_0x1d95c10, L_0x1d95d70, C4<1>, C4<1>; -L_0x1d8c7c0 .delay 1 (30000,30000,30000) L_0x1d8c7c0/d; -v0x1b64010_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers -v0x1b640f0_0 .net "b", 0 0, L_0x1d95d70; alias, 1 drivers -v0x1b641b0_0 .net "carryout", 0 0, L_0x1d8c7c0; alias, 1 drivers -v0x1b64250_0 .net "sum", 0 0, L_0x1d8c700; alias, 1 drivers -S_0x1b64390 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b63b40; +L_0x1219760/d .functor XOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; +L_0x1219760 .delay 1 (30000,30000,30000) L_0x1219760/d; +L_0x121fea0/d .functor AND 1, L_0x1229330, L_0x1229490, C4<1>, C4<1>; +L_0x121fea0 .delay 1 (30000,30000,30000) L_0x121fea0/d; +v0xff6b90_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers +v0xff6c70_0 .net "b", 0 0, L_0x1229490; alias, 1 drivers +v0xff6d30_0 .net "carryout", 0 0, L_0x121fea0; alias, 1 drivers +v0xff6dd0_0 .net "sum", 0 0, L_0x1219760; alias, 1 drivers +S_0xff6f10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xff66c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d8ca30/d .functor XOR 1, L_0x1d8c700, L_0x1d95e10, C4<0>, C4<0>; -L_0x1d8ca30 .delay 1 (30000,30000,30000) L_0x1d8ca30/d; -L_0x1d8cb80/d .functor AND 1, L_0x1d8c700, L_0x1d95e10, C4<1>, C4<1>; -L_0x1d8cb80 .delay 1 (30000,30000,30000) L_0x1d8cb80/d; -v0x1b645f0_0 .net "a", 0 0, L_0x1d8c700; alias, 1 drivers -v0x1b64690_0 .net "b", 0 0, L_0x1d95e10; alias, 1 drivers -v0x1b64730_0 .net "carryout", 0 0, L_0x1d8cb80; alias, 1 drivers -v0x1b64800_0 .net "sum", 0 0, L_0x1d8ca30; alias, 1 drivers -S_0x1b65020 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b638c0; +L_0x1220070/d .functor XOR 1, L_0x1219760, L_0x1229530, C4<0>, C4<0>; +L_0x1220070 .delay 1 (30000,30000,30000) L_0x1220070/d; +L_0x1220260/d .functor AND 1, L_0x1219760, L_0x1229530, C4<1>, C4<1>; +L_0x1220260 .delay 1 (30000,30000,30000) L_0x1220260/d; +v0xff7170_0 .net "a", 0 0, L_0x1219760; alias, 1 drivers +v0xff7210_0 .net "b", 0 0, L_0x1229530; alias, 1 drivers +v0xff72b0_0 .net "carryout", 0 0, L_0x1220260; alias, 1 drivers +v0xff7380_0 .net "sum", 0 0, L_0x1220070; alias, 1 drivers +S_0xff7ba0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xff6440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b6a2a0_0 .net "ands", 7 0, L_0x1d937b0; 1 drivers -v0x1b6a3b0_0 .net "in", 7 0, L_0x1ebf060; alias, 1 drivers -v0x1b6a470_0 .net "out", 0 0, L_0x1d957b0; alias, 1 drivers -v0x1b6a540_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b65240 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b65020; +v0xffcf90_0 .net "ands", 7 0, L_0x1226ed0; 1 drivers +v0xffd0a0_0 .net "in", 7 0, L_0x1353410; alias, 1 drivers +v0xffd160_0 .net "out", 0 0, L_0x1228ed0; alias, 1 drivers +v0xffd230_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xff7dc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xff7ba0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b67970_0 .net "A", 7 0, L_0x1ebf060; alias, 1 drivers -v0x1b67a70_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b67b30_0 .net *"_s0", 0 0, L_0x1d920d0; 1 drivers -v0x1b67bf0_0 .net *"_s12", 0 0, L_0x1d92a40; 1 drivers -v0x1b67cd0_0 .net *"_s16", 0 0, L_0x1d92da0; 1 drivers -v0x1b67e00_0 .net *"_s20", 0 0, L_0x1d930b0; 1 drivers -v0x1b67ee0_0 .net *"_s24", 0 0, L_0x1d934a0; 1 drivers -v0x1b67fc0_0 .net *"_s28", 0 0, L_0x1d93430; 1 drivers -v0x1b68060_0 .net *"_s4", 0 0, L_0x1d923e0; 1 drivers -v0x1b68190_0 .net *"_s8", 0 0, L_0x1d92730; 1 drivers -v0x1b68230_0 .net "out", 7 0, L_0x1d937b0; alias, 1 drivers -L_0x1d92190 .part L_0x1ebf060, 0, 1; -L_0x1d922f0 .part v0x1d6daa0_0, 0, 1; -L_0x1d924a0 .part L_0x1ebf060, 1, 1; -L_0x1d92690 .part v0x1d6daa0_0, 1, 1; -L_0x1d927f0 .part L_0x1ebf060, 2, 1; -L_0x1d92950 .part v0x1d6daa0_0, 2, 1; -L_0x1d92b00 .part L_0x1ebf060, 3, 1; -L_0x1d92c60 .part v0x1d6daa0_0, 3, 1; -L_0x1d92e60 .part L_0x1ebf060, 4, 1; -L_0x1d92fc0 .part v0x1d6daa0_0, 4, 1; -L_0x1d93120 .part L_0x1ebf060, 5, 1; -L_0x1d93390 .part v0x1d6daa0_0, 5, 1; -L_0x1d93560 .part L_0x1ebf060, 6, 1; -L_0x1d936c0 .part v0x1d6daa0_0, 6, 1; -LS_0x1d937b0_0_0 .concat8 [ 1 1 1 1], L_0x1d920d0, L_0x1d923e0, L_0x1d92730, L_0x1d92a40; -LS_0x1d937b0_0_4 .concat8 [ 1 1 1 1], L_0x1d92da0, L_0x1d930b0, L_0x1d934a0, L_0x1d93430; -L_0x1d937b0 .concat8 [ 4 4 0 0], LS_0x1d937b0_0_0, LS_0x1d937b0_0_4; -L_0x1d93b70 .part L_0x1ebf060, 7, 1; -L_0x1d93d60 .part v0x1d6daa0_0, 7, 1; -S_0x1b654a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b656b0 .param/l "i" 0 4 54, +C4<00>; -L_0x1d920d0/d .functor AND 1, L_0x1d92190, L_0x1d922f0, C4<1>, C4<1>; -L_0x1d920d0 .delay 1 (30000,30000,30000) L_0x1d920d0/d; -v0x1b65790_0 .net *"_s0", 0 0, L_0x1d92190; 1 drivers -v0x1b65870_0 .net *"_s1", 0 0, L_0x1d922f0; 1 drivers -S_0x1b65950 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b65b60 .param/l "i" 0 4 54, +C4<01>; -L_0x1d923e0/d .functor AND 1, L_0x1d924a0, L_0x1d92690, C4<1>, C4<1>; -L_0x1d923e0 .delay 1 (30000,30000,30000) L_0x1d923e0/d; -v0x1b65c20_0 .net *"_s0", 0 0, L_0x1d924a0; 1 drivers -v0x1b65d00_0 .net *"_s1", 0 0, L_0x1d92690; 1 drivers -S_0x1b65de0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b65ff0 .param/l "i" 0 4 54, +C4<010>; -L_0x1d92730/d .functor AND 1, L_0x1d927f0, L_0x1d92950, C4<1>, C4<1>; -L_0x1d92730 .delay 1 (30000,30000,30000) L_0x1d92730/d; -v0x1b66090_0 .net *"_s0", 0 0, L_0x1d927f0; 1 drivers -v0x1b66170_0 .net *"_s1", 0 0, L_0x1d92950; 1 drivers -S_0x1b66250 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b66460 .param/l "i" 0 4 54, +C4<011>; -L_0x1d92a40/d .functor AND 1, L_0x1d92b00, L_0x1d92c60, C4<1>, C4<1>; -L_0x1d92a40 .delay 1 (30000,30000,30000) L_0x1d92a40/d; -v0x1b66520_0 .net *"_s0", 0 0, L_0x1d92b00; 1 drivers -v0x1b66600_0 .net *"_s1", 0 0, L_0x1d92c60; 1 drivers -S_0x1b666e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b66940 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d92da0/d .functor AND 1, L_0x1d92e60, L_0x1d92fc0, C4<1>, C4<1>; -L_0x1d92da0 .delay 1 (30000,30000,30000) L_0x1d92da0/d; -v0x1b66a00_0 .net *"_s0", 0 0, L_0x1d92e60; 1 drivers -v0x1b66ae0_0 .net *"_s1", 0 0, L_0x1d92fc0; 1 drivers -S_0x1b66bc0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b66dd0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d930b0/d .functor AND 1, L_0x1d93120, L_0x1d93390, C4<1>, C4<1>; -L_0x1d930b0 .delay 1 (30000,30000,30000) L_0x1d930b0/d; -v0x1b66e90_0 .net *"_s0", 0 0, L_0x1d93120; 1 drivers -v0x1b66f70_0 .net *"_s1", 0 0, L_0x1d93390; 1 drivers -S_0x1b67050 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b67260 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d934a0/d .functor AND 1, L_0x1d93560, L_0x1d936c0, C4<1>, C4<1>; -L_0x1d934a0 .delay 1 (30000,30000,30000) L_0x1d934a0/d; -v0x1b67320_0 .net *"_s0", 0 0, L_0x1d93560; 1 drivers -v0x1b67400_0 .net *"_s1", 0 0, L_0x1d936c0; 1 drivers -S_0x1b674e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b65240; - .timescale -9 -12; -P_0x1b676f0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d93430/d .functor AND 1, L_0x1d93b70, L_0x1d93d60, C4<1>, C4<1>; -L_0x1d93430 .delay 1 (30000,30000,30000) L_0x1d93430/d; -v0x1b677b0_0 .net *"_s0", 0 0, L_0x1d93b70; 1 drivers -v0x1b67890_0 .net *"_s1", 0 0, L_0x1d93d60; 1 drivers -S_0x1b682d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b65020; +v0xffa4f0_0 .net "A", 7 0, L_0x1353410; alias, 1 drivers +v0xffa5f0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xffa6b0_0 .net *"_s0", 0 0, L_0x12257f0; 1 drivers +v0xffa770_0 .net *"_s12", 0 0, L_0x1226160; 1 drivers +v0xffa850_0 .net *"_s16", 0 0, L_0x12264c0; 1 drivers +v0xffa980_0 .net *"_s20", 0 0, L_0x12267d0; 1 drivers +v0xffaa60_0 .net *"_s24", 0 0, L_0x1226bc0; 1 drivers +v0xffab40_0 .net *"_s28", 0 0, L_0x1226b50; 1 drivers +v0xffac20_0 .net *"_s4", 0 0, L_0x1225b00; 1 drivers +v0xffad90_0 .net *"_s8", 0 0, L_0x1225e50; 1 drivers +v0xffae70_0 .net "out", 7 0, L_0x1226ed0; alias, 1 drivers +L_0x12258b0 .part L_0x1353410, 0, 1; +L_0x1225a10 .part v0x12010b0_0, 0, 1; +L_0x1225bc0 .part L_0x1353410, 1, 1; +L_0x1225db0 .part v0x12010b0_0, 1, 1; +L_0x1225f10 .part L_0x1353410, 2, 1; +L_0x1226070 .part v0x12010b0_0, 2, 1; +L_0x1226220 .part L_0x1353410, 3, 1; +L_0x1226380 .part v0x12010b0_0, 3, 1; +L_0x1226580 .part L_0x1353410, 4, 1; +L_0x12266e0 .part v0x12010b0_0, 4, 1; +L_0x1226840 .part L_0x1353410, 5, 1; +L_0x1226ab0 .part v0x12010b0_0, 5, 1; +L_0x1226c80 .part L_0x1353410, 6, 1; +L_0x1226de0 .part v0x12010b0_0, 6, 1; +LS_0x1226ed0_0_0 .concat8 [ 1 1 1 1], L_0x12257f0, L_0x1225b00, L_0x1225e50, L_0x1226160; +LS_0x1226ed0_0_4 .concat8 [ 1 1 1 1], L_0x12264c0, L_0x12267d0, L_0x1226bc0, L_0x1226b50; +L_0x1226ed0 .concat8 [ 4 4 0 0], LS_0x1226ed0_0_0, LS_0x1226ed0_0_4; +L_0x1227290 .part L_0x1353410, 7, 1; +L_0x1227480 .part v0x12010b0_0, 7, 1; +S_0xff8020 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff8230 .param/l "i" 0 4 54, +C4<00>; +L_0x12257f0/d .functor AND 1, L_0x12258b0, L_0x1225a10, C4<1>, C4<1>; +L_0x12257f0 .delay 1 (30000,30000,30000) L_0x12257f0/d; +v0xff8310_0 .net *"_s0", 0 0, L_0x12258b0; 1 drivers +v0xff83f0_0 .net *"_s1", 0 0, L_0x1225a10; 1 drivers +S_0xff84d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff86e0 .param/l "i" 0 4 54, +C4<01>; +L_0x1225b00/d .functor AND 1, L_0x1225bc0, L_0x1225db0, C4<1>, C4<1>; +L_0x1225b00 .delay 1 (30000,30000,30000) L_0x1225b00/d; +v0xff87a0_0 .net *"_s0", 0 0, L_0x1225bc0; 1 drivers +v0xff8880_0 .net *"_s1", 0 0, L_0x1225db0; 1 drivers +S_0xff8960 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff8b70 .param/l "i" 0 4 54, +C4<010>; +L_0x1225e50/d .functor AND 1, L_0x1225f10, L_0x1226070, C4<1>, C4<1>; +L_0x1225e50 .delay 1 (30000,30000,30000) L_0x1225e50/d; +v0xff8c10_0 .net *"_s0", 0 0, L_0x1225f10; 1 drivers +v0xff8cf0_0 .net *"_s1", 0 0, L_0x1226070; 1 drivers +S_0xff8dd0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff8fe0 .param/l "i" 0 4 54, +C4<011>; +L_0x1226160/d .functor AND 1, L_0x1226220, L_0x1226380, C4<1>, C4<1>; +L_0x1226160 .delay 1 (30000,30000,30000) L_0x1226160/d; +v0xff90a0_0 .net *"_s0", 0 0, L_0x1226220; 1 drivers +v0xff9180_0 .net *"_s1", 0 0, L_0x1226380; 1 drivers +S_0xff9260 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff94c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12264c0/d .functor AND 1, L_0x1226580, L_0x12266e0, C4<1>, C4<1>; +L_0x12264c0 .delay 1 (30000,30000,30000) L_0x12264c0/d; +v0xff9580_0 .net *"_s0", 0 0, L_0x1226580; 1 drivers +v0xff9660_0 .net *"_s1", 0 0, L_0x12266e0; 1 drivers +S_0xff9740 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff9950 .param/l "i" 0 4 54, +C4<0101>; +L_0x12267d0/d .functor AND 1, L_0x1226840, L_0x1226ab0, C4<1>, C4<1>; +L_0x12267d0 .delay 1 (30000,30000,30000) L_0x12267d0/d; +v0xff9a10_0 .net *"_s0", 0 0, L_0x1226840; 1 drivers +v0xff9af0_0 .net *"_s1", 0 0, L_0x1226ab0; 1 drivers +S_0xff9bd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xff9de0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1226bc0/d .functor AND 1, L_0x1226c80, L_0x1226de0, C4<1>, C4<1>; +L_0x1226bc0 .delay 1 (30000,30000,30000) L_0x1226bc0/d; +v0xff9ea0_0 .net *"_s0", 0 0, L_0x1226c80; 1 drivers +v0xff9f80_0 .net *"_s1", 0 0, L_0x1226de0; 1 drivers +S_0xffa060 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xff7dc0; + .timescale -9 -12; +P_0xffa270 .param/l "i" 0 4 54, +C4<0111>; +L_0x1226b50/d .functor AND 1, L_0x1227290, L_0x1227480, C4<1>, C4<1>; +L_0x1226b50 .delay 1 (30000,30000,30000) L_0x1226b50/d; +v0xffa330_0 .net *"_s0", 0 0, L_0x1227290; 1 drivers +v0xffa410_0 .net *"_s1", 0 0, L_0x1227480; 1 drivers +S_0xffafd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xff7ba0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d957b0/d .functor OR 1, L_0x1d95870, L_0x1d95a20, C4<0>, C4<0>; -L_0x1d957b0 .delay 1 (30000,30000,30000) L_0x1d957b0/d; -v0x1b69e30_0 .net *"_s10", 0 0, L_0x1d95870; 1 drivers -v0x1b69f10_0 .net *"_s12", 0 0, L_0x1d95a20; 1 drivers -v0x1b69ff0_0 .net "in", 7 0, L_0x1d937b0; alias, 1 drivers -v0x1b6a0c0_0 .net "ors", 1 0, L_0x1d955d0; 1 drivers -v0x1b6a180_0 .net "out", 0 0, L_0x1d957b0; alias, 1 drivers -L_0x1d949a0 .part L_0x1d937b0, 0, 4; -L_0x1d955d0 .concat8 [ 1 1 0 0], L_0x1d94690, L_0x1d952c0; -L_0x1d95710 .part L_0x1d937b0, 4, 4; -L_0x1d95870 .part L_0x1d955d0, 0, 1; -L_0x1d95a20 .part L_0x1d955d0, 1, 1; -S_0x1b68490 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b682d0; +L_0x1228ed0/d .functor OR 1, L_0x1228f90, L_0x1229140, C4<0>, C4<0>; +L_0x1228ed0 .delay 1 (30000,30000,30000) L_0x1228ed0/d; +v0xffcb20_0 .net *"_s10", 0 0, L_0x1228f90; 1 drivers +v0xffcc00_0 .net *"_s12", 0 0, L_0x1229140; 1 drivers +v0xffcce0_0 .net "in", 7 0, L_0x1226ed0; alias, 1 drivers +v0xffcdb0_0 .net "ors", 1 0, L_0x1228cf0; 1 drivers +v0xffce70_0 .net "out", 0 0, L_0x1228ed0; alias, 1 drivers +L_0x12280c0 .part L_0x1226ed0, 0, 4; +L_0x1228cf0 .concat8 [ 1 1 0 0], L_0x1227db0, L_0x12289e0; +L_0x1228e30 .part L_0x1226ed0, 4, 4; +L_0x1228f90 .part L_0x1228cf0, 0, 1; +L_0x1229140 .part L_0x1228cf0, 1, 1; +S_0xffb190 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xffafd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d93e50/d .functor OR 1, L_0x1d93f10, L_0x1d94070, C4<0>, C4<0>; -L_0x1d93e50 .delay 1 (30000,30000,30000) L_0x1d93e50/d; -L_0x1d942a0/d .functor OR 1, L_0x1d943b0, L_0x1d94510, C4<0>, C4<0>; -L_0x1d942a0 .delay 1 (30000,30000,30000) L_0x1d942a0/d; -L_0x1d94690/d .functor OR 1, L_0x1d94700, L_0x1d948b0, C4<0>, C4<0>; -L_0x1d94690 .delay 1 (30000,30000,30000) L_0x1d94690/d; -v0x1b686c0_0 .net *"_s0", 0 0, L_0x1d93e50; 1 drivers -v0x1b687c0_0 .net *"_s10", 0 0, L_0x1d943b0; 1 drivers -v0x1b688a0_0 .net *"_s12", 0 0, L_0x1d94510; 1 drivers -v0x1b68990_0 .net *"_s14", 0 0, L_0x1d94700; 1 drivers -v0x1b68a70_0 .net *"_s16", 0 0, L_0x1d948b0; 1 drivers -v0x1b68ba0_0 .net *"_s3", 0 0, L_0x1d93f10; 1 drivers -v0x1b68c80_0 .net *"_s5", 0 0, L_0x1d94070; 1 drivers -v0x1b68d60_0 .net *"_s6", 0 0, L_0x1d942a0; 1 drivers -v0x1b68e40_0 .net "in", 3 0, L_0x1d949a0; 1 drivers -v0x1b68fb0_0 .net "ors", 1 0, L_0x1d941b0; 1 drivers -v0x1b69090_0 .net "out", 0 0, L_0x1d94690; 1 drivers -L_0x1d93f10 .part L_0x1d949a0, 0, 1; -L_0x1d94070 .part L_0x1d949a0, 1, 1; -L_0x1d941b0 .concat8 [ 1 1 0 0], L_0x1d93e50, L_0x1d942a0; -L_0x1d943b0 .part L_0x1d949a0, 2, 1; -L_0x1d94510 .part L_0x1d949a0, 3, 1; -L_0x1d94700 .part L_0x1d941b0, 0, 1; -L_0x1d948b0 .part L_0x1d941b0, 1, 1; -S_0x1b691b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b682d0; +L_0x1227570/d .functor OR 1, L_0x1227630, L_0x1227790, C4<0>, C4<0>; +L_0x1227570 .delay 1 (30000,30000,30000) L_0x1227570/d; +L_0x12279c0/d .functor OR 1, L_0x1227ad0, L_0x1227c30, C4<0>, C4<0>; +L_0x12279c0 .delay 1 (30000,30000,30000) L_0x12279c0/d; +L_0x1227db0/d .functor OR 1, L_0x1227e20, L_0x1227fd0, C4<0>, C4<0>; +L_0x1227db0 .delay 1 (30000,30000,30000) L_0x1227db0/d; +v0xffb3e0_0 .net *"_s0", 0 0, L_0x1227570; 1 drivers +v0xffb4e0_0 .net *"_s10", 0 0, L_0x1227ad0; 1 drivers +v0xffb5c0_0 .net *"_s12", 0 0, L_0x1227c30; 1 drivers +v0xffb680_0 .net *"_s14", 0 0, L_0x1227e20; 1 drivers +v0xffb760_0 .net *"_s16", 0 0, L_0x1227fd0; 1 drivers +v0xffb890_0 .net *"_s3", 0 0, L_0x1227630; 1 drivers +v0xffb970_0 .net *"_s5", 0 0, L_0x1227790; 1 drivers +v0xffba50_0 .net *"_s6", 0 0, L_0x12279c0; 1 drivers +v0xffbb30_0 .net "in", 3 0, L_0x12280c0; 1 drivers +v0xffbca0_0 .net "ors", 1 0, L_0x12278d0; 1 drivers +v0xffbd80_0 .net "out", 0 0, L_0x1227db0; 1 drivers +L_0x1227630 .part L_0x12280c0, 0, 1; +L_0x1227790 .part L_0x12280c0, 1, 1; +L_0x12278d0 .concat8 [ 1 1 0 0], L_0x1227570, L_0x12279c0; +L_0x1227ad0 .part L_0x12280c0, 2, 1; +L_0x1227c30 .part L_0x12280c0, 3, 1; +L_0x1227e20 .part L_0x12278d0, 0, 1; +L_0x1227fd0 .part L_0x12278d0, 1, 1; +S_0xffbea0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xffafd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d94ad0/d .functor OR 1, L_0x1d94b40, L_0x1d94ca0, C4<0>, C4<0>; -L_0x1d94ad0 .delay 1 (30000,30000,30000) L_0x1d94ad0/d; -L_0x1d94ed0/d .functor OR 1, L_0x1d94fe0, L_0x1d95140, C4<0>, C4<0>; -L_0x1d94ed0 .delay 1 (30000,30000,30000) L_0x1d94ed0/d; -L_0x1d952c0/d .functor OR 1, L_0x1d95330, L_0x1d954e0, C4<0>, C4<0>; -L_0x1d952c0 .delay 1 (30000,30000,30000) L_0x1d952c0/d; -v0x1b69370_0 .net *"_s0", 0 0, L_0x1d94ad0; 1 drivers -v0x1b69470_0 .net *"_s10", 0 0, L_0x1d94fe0; 1 drivers -v0x1b69550_0 .net *"_s12", 0 0, L_0x1d95140; 1 drivers -v0x1b69610_0 .net *"_s14", 0 0, L_0x1d95330; 1 drivers -v0x1b696f0_0 .net *"_s16", 0 0, L_0x1d954e0; 1 drivers -v0x1b69820_0 .net *"_s3", 0 0, L_0x1d94b40; 1 drivers -v0x1b69900_0 .net *"_s5", 0 0, L_0x1d94ca0; 1 drivers -v0x1b699e0_0 .net *"_s6", 0 0, L_0x1d94ed0; 1 drivers -v0x1b69ac0_0 .net "in", 3 0, L_0x1d95710; 1 drivers -v0x1b69c30_0 .net "ors", 1 0, L_0x1d94de0; 1 drivers -v0x1b69d10_0 .net "out", 0 0, L_0x1d952c0; 1 drivers -L_0x1d94b40 .part L_0x1d95710, 0, 1; -L_0x1d94ca0 .part L_0x1d95710, 1, 1; -L_0x1d94de0 .concat8 [ 1 1 0 0], L_0x1d94ad0, L_0x1d94ed0; -L_0x1d94fe0 .part L_0x1d95710, 2, 1; -L_0x1d95140 .part L_0x1d95710, 3, 1; -L_0x1d95330 .part L_0x1d94de0, 0, 1; -L_0x1d954e0 .part L_0x1d94de0, 1, 1; -S_0x1b6a7f0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b638c0; +L_0x12281f0/d .functor OR 1, L_0x1228260, L_0x12283c0, C4<0>, C4<0>; +L_0x12281f0 .delay 1 (30000,30000,30000) L_0x12281f0/d; +L_0x12285f0/d .functor OR 1, L_0x1228700, L_0x1228860, C4<0>, C4<0>; +L_0x12285f0 .delay 1 (30000,30000,30000) L_0x12285f0/d; +L_0x12289e0/d .functor OR 1, L_0x1228a50, L_0x1228c00, C4<0>, C4<0>; +L_0x12289e0 .delay 1 (30000,30000,30000) L_0x12289e0/d; +v0xffc060_0 .net *"_s0", 0 0, L_0x12281f0; 1 drivers +v0xffc160_0 .net *"_s10", 0 0, L_0x1228700; 1 drivers +v0xffc240_0 .net *"_s12", 0 0, L_0x1228860; 1 drivers +v0xffc300_0 .net *"_s14", 0 0, L_0x1228a50; 1 drivers +v0xffc3e0_0 .net *"_s16", 0 0, L_0x1228c00; 1 drivers +v0xffc510_0 .net *"_s3", 0 0, L_0x1228260; 1 drivers +v0xffc5f0_0 .net *"_s5", 0 0, L_0x12283c0; 1 drivers +v0xffc6d0_0 .net *"_s6", 0 0, L_0x12285f0; 1 drivers +v0xffc7b0_0 .net "in", 3 0, L_0x1228e30; 1 drivers +v0xffc920_0 .net "ors", 1 0, L_0x1228500; 1 drivers +v0xffca00_0 .net "out", 0 0, L_0x12289e0; 1 drivers +L_0x1228260 .part L_0x1228e30, 0, 1; +L_0x12283c0 .part L_0x1228e30, 1, 1; +L_0x1228500 .concat8 [ 1 1 0 0], L_0x12281f0, L_0x12285f0; +L_0x1228700 .part L_0x1228e30, 2, 1; +L_0x1228860 .part L_0x1228e30, 3, 1; +L_0x1228a50 .part L_0x1228500, 0, 1; +L_0x1228c00 .part L_0x1228500, 1, 1; +S_0xffd4e0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xff6440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b6fb50_0 .net "ands", 7 0, L_0x1d8fd70; 1 drivers -v0x1b6fc60_0 .net "in", 7 0, L_0x1d8e2b0; alias, 1 drivers -v0x1b6fd20_0 .net "out", 0 0, L_0x1d91d70; alias, 1 drivers -v0x1b6fdf0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b6a970 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b6a7f0; +v0x10027e0_0 .net "ands", 7 0, L_0x1223490; 1 drivers +v0x10028f0_0 .net "in", 7 0, L_0x12218f0; alias, 1 drivers +v0x10029b0_0 .net "out", 0 0, L_0x1225490; alias, 1 drivers +v0x1002a80_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0xffd660 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xffd4e0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b6d0b0_0 .net "A", 7 0, L_0x1d8e2b0; alias, 1 drivers -v0x1b6d1b0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b6d270_0 .net *"_s0", 0 0, L_0x1d8e640; 1 drivers -v0x1b6d330_0 .net *"_s12", 0 0, L_0x1d8f000; 1 drivers -v0x1b6d410_0 .net *"_s16", 0 0, L_0x1d8f360; 1 drivers -v0x1b6d540_0 .net *"_s20", 0 0, L_0x1d8f730; 1 drivers -v0x1b6d620_0 .net *"_s24", 0 0, L_0x1d8fa60; 1 drivers -v0x1b6d700_0 .net *"_s28", 0 0, L_0x1d8f9f0; 1 drivers -v0x1b6d7e0_0 .net *"_s4", 0 0, L_0x1d8e9e0; 1 drivers -v0x1b6d950_0 .net *"_s8", 0 0, L_0x1d8ecf0; 1 drivers -v0x1b6da30_0 .net "out", 7 0, L_0x1d8fd70; alias, 1 drivers -L_0x1d8e750 .part L_0x1d8e2b0, 0, 1; -L_0x1d8e940 .part v0x1d6daa0_0, 0, 1; -L_0x1d8eaa0 .part L_0x1d8e2b0, 1, 1; -L_0x1d8ec00 .part v0x1d6daa0_0, 1, 1; -L_0x1d8edb0 .part L_0x1d8e2b0, 2, 1; -L_0x1d8ef10 .part v0x1d6daa0_0, 2, 1; -L_0x1d8f0c0 .part L_0x1d8e2b0, 3, 1; -L_0x1d8f220 .part v0x1d6daa0_0, 3, 1; -L_0x1d8f420 .part L_0x1d8e2b0, 4, 1; -L_0x1d8f690 .part v0x1d6daa0_0, 4, 1; -L_0x1d8f7a0 .part L_0x1d8e2b0, 5, 1; -L_0x1d8f900 .part v0x1d6daa0_0, 5, 1; -L_0x1d8fb20 .part L_0x1d8e2b0, 6, 1; -L_0x1d8fc80 .part v0x1d6daa0_0, 6, 1; -LS_0x1d8fd70_0_0 .concat8 [ 1 1 1 1], L_0x1d8e640, L_0x1d8e9e0, L_0x1d8ecf0, L_0x1d8f000; -LS_0x1d8fd70_0_4 .concat8 [ 1 1 1 1], L_0x1d8f360, L_0x1d8f730, L_0x1d8fa60, L_0x1d8f9f0; -L_0x1d8fd70 .concat8 [ 4 4 0 0], LS_0x1d8fd70_0_0, LS_0x1d8fd70_0_4; -L_0x1d90130 .part L_0x1d8e2b0, 7, 1; -L_0x1d90320 .part v0x1d6daa0_0, 7, 1; -S_0x1b6abb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6adc0 .param/l "i" 0 4 54, +C4<00>; -L_0x1d8e640/d .functor AND 1, L_0x1d8e750, L_0x1d8e940, C4<1>, C4<1>; -L_0x1d8e640 .delay 1 (30000,30000,30000) L_0x1d8e640/d; -v0x1b6aea0_0 .net *"_s0", 0 0, L_0x1d8e750; 1 drivers -v0x1b6af80_0 .net *"_s1", 0 0, L_0x1d8e940; 1 drivers -S_0x1b6b060 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6b270 .param/l "i" 0 4 54, +C4<01>; -L_0x1d8e9e0/d .functor AND 1, L_0x1d8eaa0, L_0x1d8ec00, C4<1>, C4<1>; -L_0x1d8e9e0 .delay 1 (30000,30000,30000) L_0x1d8e9e0/d; -v0x1b6b330_0 .net *"_s0", 0 0, L_0x1d8eaa0; 1 drivers -v0x1b6b410_0 .net *"_s1", 0 0, L_0x1d8ec00; 1 drivers -S_0x1b6b4f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6b730 .param/l "i" 0 4 54, +C4<010>; -L_0x1d8ecf0/d .functor AND 1, L_0x1d8edb0, L_0x1d8ef10, C4<1>, C4<1>; -L_0x1d8ecf0 .delay 1 (30000,30000,30000) L_0x1d8ecf0/d; -v0x1b6b7d0_0 .net *"_s0", 0 0, L_0x1d8edb0; 1 drivers -v0x1b6b8b0_0 .net *"_s1", 0 0, L_0x1d8ef10; 1 drivers -S_0x1b6b990 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6bba0 .param/l "i" 0 4 54, +C4<011>; -L_0x1d8f000/d .functor AND 1, L_0x1d8f0c0, L_0x1d8f220, C4<1>, C4<1>; -L_0x1d8f000 .delay 1 (30000,30000,30000) L_0x1d8f000/d; -v0x1b6bc60_0 .net *"_s0", 0 0, L_0x1d8f0c0; 1 drivers -v0x1b6bd40_0 .net *"_s1", 0 0, L_0x1d8f220; 1 drivers -S_0x1b6be20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6c080 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d8f360/d .functor AND 1, L_0x1d8f420, L_0x1d8f690, C4<1>, C4<1>; -L_0x1d8f360 .delay 1 (30000,30000,30000) L_0x1d8f360/d; -v0x1b6c140_0 .net *"_s0", 0 0, L_0x1d8f420; 1 drivers -v0x1b6c220_0 .net *"_s1", 0 0, L_0x1d8f690; 1 drivers -S_0x1b6c300 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6c510 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d8f730/d .functor AND 1, L_0x1d8f7a0, L_0x1d8f900, C4<1>, C4<1>; -L_0x1d8f730 .delay 1 (30000,30000,30000) L_0x1d8f730/d; -v0x1b6c5d0_0 .net *"_s0", 0 0, L_0x1d8f7a0; 1 drivers -v0x1b6c6b0_0 .net *"_s1", 0 0, L_0x1d8f900; 1 drivers -S_0x1b6c790 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6c9a0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d8fa60/d .functor AND 1, L_0x1d8fb20, L_0x1d8fc80, C4<1>, C4<1>; -L_0x1d8fa60 .delay 1 (30000,30000,30000) L_0x1d8fa60/d; -v0x1b6ca60_0 .net *"_s0", 0 0, L_0x1d8fb20; 1 drivers -v0x1b6cb40_0 .net *"_s1", 0 0, L_0x1d8fc80; 1 drivers -S_0x1b6cc20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b6a970; - .timescale -9 -12; -P_0x1b6ce30 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d8f9f0/d .functor AND 1, L_0x1d90130, L_0x1d90320, C4<1>, C4<1>; -L_0x1d8f9f0 .delay 1 (30000,30000,30000) L_0x1d8f9f0/d; -v0x1b6cef0_0 .net *"_s0", 0 0, L_0x1d90130; 1 drivers -v0x1b6cfd0_0 .net *"_s1", 0 0, L_0x1d90320; 1 drivers -S_0x1b6db90 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b6a7f0; +v0xfffda0_0 .net "A", 7 0, L_0x12218f0; alias, 1 drivers +v0xfffea0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xffff60_0 .net *"_s0", 0 0, L_0x1221c80; 1 drivers +v0x1000020_0 .net *"_s12", 0 0, L_0x1222640; 1 drivers +v0x1000100_0 .net *"_s16", 0 0, L_0x12229a0; 1 drivers +v0x1000230_0 .net *"_s20", 0 0, L_0x1222dd0; 1 drivers +v0x1000310_0 .net *"_s24", 0 0, L_0x1223100; 1 drivers +v0x10003f0_0 .net *"_s28", 0 0, L_0x1223090; 1 drivers +v0x10004d0_0 .net *"_s4", 0 0, L_0x1222020; 1 drivers +v0x1000640_0 .net *"_s8", 0 0, L_0x1222330; 1 drivers +v0x1000720_0 .net "out", 7 0, L_0x1223490; alias, 1 drivers +L_0x1221d90 .part L_0x12218f0, 0, 1; +L_0x1221f80 .part v0x12010b0_0, 0, 1; +L_0x12220e0 .part L_0x12218f0, 1, 1; +L_0x1222240 .part v0x12010b0_0, 1, 1; +L_0x12223f0 .part L_0x12218f0, 2, 1; +L_0x1222550 .part v0x12010b0_0, 2, 1; +L_0x1222700 .part L_0x12218f0, 3, 1; +L_0x1222860 .part v0x12010b0_0, 3, 1; +L_0x1222a60 .part L_0x12218f0, 4, 1; +L_0x1222cd0 .part v0x12010b0_0, 4, 1; +L_0x1222e40 .part L_0x12218f0, 5, 1; +L_0x1222fa0 .part v0x12010b0_0, 5, 1; +L_0x12231c0 .part L_0x12218f0, 6, 1; +L_0x1223320 .part v0x12010b0_0, 6, 1; +LS_0x1223490_0_0 .concat8 [ 1 1 1 1], L_0x1221c80, L_0x1222020, L_0x1222330, L_0x1222640; +LS_0x1223490_0_4 .concat8 [ 1 1 1 1], L_0x12229a0, L_0x1222dd0, L_0x1223100, L_0x1223090; +L_0x1223490 .concat8 [ 4 4 0 0], LS_0x1223490_0_0, LS_0x1223490_0_4; +L_0x1223850 .part L_0x12218f0, 7, 1; +L_0x1223a40 .part v0x12010b0_0, 7, 1; +S_0xffd8a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xffdab0 .param/l "i" 0 4 54, +C4<00>; +L_0x1221c80/d .functor AND 1, L_0x1221d90, L_0x1221f80, C4<1>, C4<1>; +L_0x1221c80 .delay 1 (30000,30000,30000) L_0x1221c80/d; +v0xffdb90_0 .net *"_s0", 0 0, L_0x1221d90; 1 drivers +v0xffdc70_0 .net *"_s1", 0 0, L_0x1221f80; 1 drivers +S_0xffdd50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xffdf60 .param/l "i" 0 4 54, +C4<01>; +L_0x1222020/d .functor AND 1, L_0x12220e0, L_0x1222240, C4<1>, C4<1>; +L_0x1222020 .delay 1 (30000,30000,30000) L_0x1222020/d; +v0xffe020_0 .net *"_s0", 0 0, L_0x12220e0; 1 drivers +v0xffe100_0 .net *"_s1", 0 0, L_0x1222240; 1 drivers +S_0xffe1e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xffe420 .param/l "i" 0 4 54, +C4<010>; +L_0x1222330/d .functor AND 1, L_0x12223f0, L_0x1222550, C4<1>, C4<1>; +L_0x1222330 .delay 1 (30000,30000,30000) L_0x1222330/d; +v0xffe4c0_0 .net *"_s0", 0 0, L_0x12223f0; 1 drivers +v0xffe5a0_0 .net *"_s1", 0 0, L_0x1222550; 1 drivers +S_0xffe680 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xffe890 .param/l "i" 0 4 54, +C4<011>; +L_0x1222640/d .functor AND 1, L_0x1222700, L_0x1222860, C4<1>, C4<1>; +L_0x1222640 .delay 1 (30000,30000,30000) L_0x1222640/d; +v0xffe950_0 .net *"_s0", 0 0, L_0x1222700; 1 drivers +v0xffea30_0 .net *"_s1", 0 0, L_0x1222860; 1 drivers +S_0xffeb10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xffed70 .param/l "i" 0 4 54, +C4<0100>; +L_0x12229a0/d .functor AND 1, L_0x1222a60, L_0x1222cd0, C4<1>, C4<1>; +L_0x12229a0 .delay 1 (30000,30000,30000) L_0x12229a0/d; +v0xffee30_0 .net *"_s0", 0 0, L_0x1222a60; 1 drivers +v0xffef10_0 .net *"_s1", 0 0, L_0x1222cd0; 1 drivers +S_0xffeff0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xfff200 .param/l "i" 0 4 54, +C4<0101>; +L_0x1222dd0/d .functor AND 1, L_0x1222e40, L_0x1222fa0, C4<1>, C4<1>; +L_0x1222dd0 .delay 1 (30000,30000,30000) L_0x1222dd0/d; +v0xfff2c0_0 .net *"_s0", 0 0, L_0x1222e40; 1 drivers +v0xfff3a0_0 .net *"_s1", 0 0, L_0x1222fa0; 1 drivers +S_0xfff480 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xfff690 .param/l "i" 0 4 54, +C4<0110>; +L_0x1223100/d .functor AND 1, L_0x12231c0, L_0x1223320, C4<1>, C4<1>; +L_0x1223100 .delay 1 (30000,30000,30000) L_0x1223100/d; +v0xfff750_0 .net *"_s0", 0 0, L_0x12231c0; 1 drivers +v0xfff830_0 .net *"_s1", 0 0, L_0x1223320; 1 drivers +S_0xfff910 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xffd660; + .timescale -9 -12; +P_0xfffb20 .param/l "i" 0 4 54, +C4<0111>; +L_0x1223090/d .functor AND 1, L_0x1223850, L_0x1223a40, C4<1>, C4<1>; +L_0x1223090 .delay 1 (30000,30000,30000) L_0x1223090/d; +v0xfffbe0_0 .net *"_s0", 0 0, L_0x1223850; 1 drivers +v0xfffcc0_0 .net *"_s1", 0 0, L_0x1223a40; 1 drivers +S_0x1000880 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xffd4e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d91d70/d .functor OR 1, L_0x1d91e30, L_0x1d91fe0, C4<0>, C4<0>; -L_0x1d91d70 .delay 1 (30000,30000,30000) L_0x1d91d70/d; -v0x1b6f6e0_0 .net *"_s10", 0 0, L_0x1d91e30; 1 drivers -v0x1b6f7c0_0 .net *"_s12", 0 0, L_0x1d91fe0; 1 drivers -v0x1b6f8a0_0 .net "in", 7 0, L_0x1d8fd70; alias, 1 drivers -v0x1b6f970_0 .net "ors", 1 0, L_0x1d91b90; 1 drivers -v0x1b6fa30_0 .net "out", 0 0, L_0x1d91d70; alias, 1 drivers -L_0x1d90f60 .part L_0x1d8fd70, 0, 4; -L_0x1d91b90 .concat8 [ 1 1 0 0], L_0x1d90c50, L_0x1d91880; -L_0x1d91cd0 .part L_0x1d8fd70, 4, 4; -L_0x1d91e30 .part L_0x1d91b90, 0, 1; -L_0x1d91fe0 .part L_0x1d91b90, 1, 1; -S_0x1b6dd50 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b6db90; +L_0x1225490/d .functor OR 1, L_0x1225550, L_0x1225700, C4<0>, C4<0>; +L_0x1225490 .delay 1 (30000,30000,30000) L_0x1225490/d; +v0x1002370_0 .net *"_s10", 0 0, L_0x1225550; 1 drivers +v0x1002450_0 .net *"_s12", 0 0, L_0x1225700; 1 drivers +v0x1002530_0 .net "in", 7 0, L_0x1223490; alias, 1 drivers +v0x1002600_0 .net "ors", 1 0, L_0x12252b0; 1 drivers +v0x10026c0_0 .net "out", 0 0, L_0x1225490; alias, 1 drivers +L_0x1224680 .part L_0x1223490, 0, 4; +L_0x12252b0 .concat8 [ 1 1 0 0], L_0x1224370, L_0x1224fa0; +L_0x12253f0 .part L_0x1223490, 4, 4; +L_0x1225550 .part L_0x12252b0, 0, 1; +L_0x1225700 .part L_0x12252b0, 1, 1; +S_0x1000a40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1000880; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d90410/d .functor OR 1, L_0x1d904d0, L_0x1d90630, C4<0>, C4<0>; -L_0x1d90410 .delay 1 (30000,30000,30000) L_0x1d90410/d; -L_0x1d90860/d .functor OR 1, L_0x1d90970, L_0x1d90ad0, C4<0>, C4<0>; -L_0x1d90860 .delay 1 (30000,30000,30000) L_0x1d90860/d; -L_0x1d90c50/d .functor OR 1, L_0x1d90cc0, L_0x1d90e70, C4<0>, C4<0>; -L_0x1d90c50 .delay 1 (30000,30000,30000) L_0x1d90c50/d; -v0x1b6dfa0_0 .net *"_s0", 0 0, L_0x1d90410; 1 drivers -v0x1b6e0a0_0 .net *"_s10", 0 0, L_0x1d90970; 1 drivers -v0x1b6e180_0 .net *"_s12", 0 0, L_0x1d90ad0; 1 drivers -v0x1b6e240_0 .net *"_s14", 0 0, L_0x1d90cc0; 1 drivers -v0x1b6e320_0 .net *"_s16", 0 0, L_0x1d90e70; 1 drivers -v0x1b6e450_0 .net *"_s3", 0 0, L_0x1d904d0; 1 drivers -v0x1b6e530_0 .net *"_s5", 0 0, L_0x1d90630; 1 drivers -v0x1b6e610_0 .net *"_s6", 0 0, L_0x1d90860; 1 drivers -v0x1b6e6f0_0 .net "in", 3 0, L_0x1d90f60; 1 drivers -v0x1b6e860_0 .net "ors", 1 0, L_0x1d90770; 1 drivers -v0x1b6e940_0 .net "out", 0 0, L_0x1d90c50; 1 drivers -L_0x1d904d0 .part L_0x1d90f60, 0, 1; -L_0x1d90630 .part L_0x1d90f60, 1, 1; -L_0x1d90770 .concat8 [ 1 1 0 0], L_0x1d90410, L_0x1d90860; -L_0x1d90970 .part L_0x1d90f60, 2, 1; -L_0x1d90ad0 .part L_0x1d90f60, 3, 1; -L_0x1d90cc0 .part L_0x1d90770, 0, 1; -L_0x1d90e70 .part L_0x1d90770, 1, 1; -S_0x1b6ea60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b6db90; +L_0x1223b30/d .functor OR 1, L_0x1223bf0, L_0x1223d50, C4<0>, C4<0>; +L_0x1223b30 .delay 1 (30000,30000,30000) L_0x1223b30/d; +L_0x1223f80/d .functor OR 1, L_0x1224090, L_0x12241f0, C4<0>, C4<0>; +L_0x1223f80 .delay 1 (30000,30000,30000) L_0x1223f80/d; +L_0x1224370/d .functor OR 1, L_0x12243e0, L_0x1224590, C4<0>, C4<0>; +L_0x1224370 .delay 1 (30000,30000,30000) L_0x1224370/d; +v0x1000c90_0 .net *"_s0", 0 0, L_0x1223b30; 1 drivers +v0x1000d90_0 .net *"_s10", 0 0, L_0x1224090; 1 drivers +v0x1000e70_0 .net *"_s12", 0 0, L_0x12241f0; 1 drivers +v0x1000f30_0 .net *"_s14", 0 0, L_0x12243e0; 1 drivers +v0x1000ff0_0 .net *"_s16", 0 0, L_0x1224590; 1 drivers +v0x10010e0_0 .net *"_s3", 0 0, L_0x1223bf0; 1 drivers +v0x10011c0_0 .net *"_s5", 0 0, L_0x1223d50; 1 drivers +v0x10012a0_0 .net *"_s6", 0 0, L_0x1223f80; 1 drivers +v0x1001380_0 .net "in", 3 0, L_0x1224680; 1 drivers +v0x10014f0_0 .net "ors", 1 0, L_0x1223e90; 1 drivers +v0x10015d0_0 .net "out", 0 0, L_0x1224370; 1 drivers +L_0x1223bf0 .part L_0x1224680, 0, 1; +L_0x1223d50 .part L_0x1224680, 1, 1; +L_0x1223e90 .concat8 [ 1 1 0 0], L_0x1223b30, L_0x1223f80; +L_0x1224090 .part L_0x1224680, 2, 1; +L_0x12241f0 .part L_0x1224680, 3, 1; +L_0x12243e0 .part L_0x1223e90, 0, 1; +L_0x1224590 .part L_0x1223e90, 1, 1; +S_0x10016f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1000880; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d91090/d .functor OR 1, L_0x1d91100, L_0x1d91260, C4<0>, C4<0>; -L_0x1d91090 .delay 1 (30000,30000,30000) L_0x1d91090/d; -L_0x1d91490/d .functor OR 1, L_0x1d915a0, L_0x1d91700, C4<0>, C4<0>; -L_0x1d91490 .delay 1 (30000,30000,30000) L_0x1d91490/d; -L_0x1d91880/d .functor OR 1, L_0x1d918f0, L_0x1d91aa0, C4<0>, C4<0>; -L_0x1d91880 .delay 1 (30000,30000,30000) L_0x1d91880/d; -v0x1b6ec20_0 .net *"_s0", 0 0, L_0x1d91090; 1 drivers -v0x1b6ed20_0 .net *"_s10", 0 0, L_0x1d915a0; 1 drivers -v0x1b6ee00_0 .net *"_s12", 0 0, L_0x1d91700; 1 drivers -v0x1b6eec0_0 .net *"_s14", 0 0, L_0x1d918f0; 1 drivers -v0x1b6efa0_0 .net *"_s16", 0 0, L_0x1d91aa0; 1 drivers -v0x1b6f0d0_0 .net *"_s3", 0 0, L_0x1d91100; 1 drivers -v0x1b6f1b0_0 .net *"_s5", 0 0, L_0x1d91260; 1 drivers -v0x1b6f290_0 .net *"_s6", 0 0, L_0x1d91490; 1 drivers -v0x1b6f370_0 .net "in", 3 0, L_0x1d91cd0; 1 drivers -v0x1b6f4e0_0 .net "ors", 1 0, L_0x1d913a0; 1 drivers -v0x1b6f5c0_0 .net "out", 0 0, L_0x1d91880; 1 drivers -L_0x1d91100 .part L_0x1d91cd0, 0, 1; -L_0x1d91260 .part L_0x1d91cd0, 1, 1; -L_0x1d913a0 .concat8 [ 1 1 0 0], L_0x1d91090, L_0x1d91490; -L_0x1d915a0 .part L_0x1d91cd0, 2, 1; -L_0x1d91700 .part L_0x1d91cd0, 3, 1; -L_0x1d918f0 .part L_0x1d913a0, 0, 1; -L_0x1d91aa0 .part L_0x1d913a0, 1, 1; -S_0x1b6fed0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b638c0; +L_0x12247b0/d .functor OR 1, L_0x1224820, L_0x1224980, C4<0>, C4<0>; +L_0x12247b0 .delay 1 (30000,30000,30000) L_0x12247b0/d; +L_0x1224bb0/d .functor OR 1, L_0x1224cc0, L_0x1224e20, C4<0>, C4<0>; +L_0x1224bb0 .delay 1 (30000,30000,30000) L_0x1224bb0/d; +L_0x1224fa0/d .functor OR 1, L_0x1225010, L_0x12251c0, C4<0>, C4<0>; +L_0x1224fa0 .delay 1 (30000,30000,30000) L_0x1224fa0/d; +v0x10018b0_0 .net *"_s0", 0 0, L_0x12247b0; 1 drivers +v0x10019b0_0 .net *"_s10", 0 0, L_0x1224cc0; 1 drivers +v0x1001a90_0 .net *"_s12", 0 0, L_0x1224e20; 1 drivers +v0x1001b50_0 .net *"_s14", 0 0, L_0x1225010; 1 drivers +v0x1001c30_0 .net *"_s16", 0 0, L_0x12251c0; 1 drivers +v0x1001d60_0 .net *"_s3", 0 0, L_0x1224820; 1 drivers +v0x1001e40_0 .net *"_s5", 0 0, L_0x1224980; 1 drivers +v0x1001f20_0 .net *"_s6", 0 0, L_0x1224bb0; 1 drivers +v0x1002000_0 .net "in", 3 0, L_0x12253f0; 1 drivers +v0x1002170_0 .net "ors", 1 0, L_0x1224ac0; 1 drivers +v0x1002250_0 .net "out", 0 0, L_0x1224fa0; 1 drivers +L_0x1224820 .part L_0x12253f0, 0, 1; +L_0x1224980 .part L_0x12253f0, 1, 1; +L_0x1224ac0 .concat8 [ 1 1 0 0], L_0x12247b0, L_0x1224bb0; +L_0x1224cc0 .part L_0x12253f0, 2, 1; +L_0x1224e20 .part L_0x12253f0, 3, 1; +L_0x1225010 .part L_0x1224ac0, 0, 1; +L_0x12251c0 .part L_0x1224ac0, 1, 1; +S_0x1002b60 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xff6440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -2284,80 +2294,80 @@ S_0x1b6fed0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b638c0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1d8d620/d .functor XNOR 1, L_0x1d95c10, L_0x1d95d70, C4<0>, C4<0>; -L_0x1d8d620 .delay 1 (20000,20000,20000) L_0x1d8d620/d; -L_0x1d8d890/d .functor AND 1, L_0x1d95c10, L_0x1d8c510, C4<1>, C4<1>; -L_0x1d8d890 .delay 1 (30000,30000,30000) L_0x1d8d890/d; -L_0x1d8d900/d .functor AND 1, L_0x1d8d620, L_0x1d95e10, C4<1>, C4<1>; -L_0x1d8d900 .delay 1 (30000,30000,30000) L_0x1d8d900/d; -L_0x1d8da60/d .functor OR 1, L_0x1d8d900, L_0x1d8d890, C4<0>, C4<0>; -L_0x1d8da60 .delay 1 (30000,30000,30000) L_0x1d8da60/d; -v0x1b70180_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers -v0x1b70270_0 .net "a_", 0 0, L_0x1d8c400; alias, 1 drivers -v0x1b70330_0 .net "b", 0 0, L_0x1d95d70; alias, 1 drivers -v0x1b70420_0 .net "b_", 0 0, L_0x1d8c510; alias, 1 drivers -v0x1b704c0_0 .net "carryin", 0 0, L_0x1d95e10; alias, 1 drivers -v0x1b70600_0 .net "eq", 0 0, L_0x1d8d620; 1 drivers -v0x1b706c0_0 .net "lt", 0 0, L_0x1d8d890; 1 drivers -v0x1b70780_0 .net "out", 0 0, L_0x1d8da60; 1 drivers -v0x1b70840_0 .net "w0", 0 0, L_0x1d8d900; 1 drivers -S_0x1b70a90 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b638c0; +L_0x1220c60/d .functor XNOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; +L_0x1220c60 .delay 1 (20000,20000,20000) L_0x1220c60/d; +L_0x1220ed0/d .functor AND 1, L_0x1229330, L_0x121fcb0, C4<1>, C4<1>; +L_0x1220ed0 .delay 1 (30000,30000,30000) L_0x1220ed0/d; +L_0x1220f40/d .functor AND 1, L_0x1220c60, L_0x1229530, C4<1>, C4<1>; +L_0x1220f40 .delay 1 (30000,30000,30000) L_0x1220f40/d; +L_0x12210a0/d .functor OR 1, L_0x1220f40, L_0x1220ed0, C4<0>, C4<0>; +L_0x12210a0 .delay 1 (30000,30000,30000) L_0x12210a0/d; +v0x1002e10_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers +v0x1002f00_0 .net "a_", 0 0, L_0x121fba0; alias, 1 drivers +v0x1002fc0_0 .net "b", 0 0, L_0x1229490; alias, 1 drivers +v0x10030b0_0 .net "b_", 0 0, L_0x121fcb0; alias, 1 drivers +v0x1003150_0 .net "carryin", 0 0, L_0x1229530; alias, 1 drivers +v0x1003290_0 .net "eq", 0 0, L_0x1220c60; 1 drivers +v0x1003350_0 .net "lt", 0 0, L_0x1220ed0; 1 drivers +v0x1003410_0 .net "out", 0 0, L_0x12210a0; 1 drivers +v0x10034d0_0 .net "w0", 0 0, L_0x1220f40; 1 drivers +S_0x1003720 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xff6440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d8d400/d .functor OR 1, L_0x1d8cf00, L_0x1b71cf0, C4<0>, C4<0>; -L_0x1d8d400 .delay 1 (30000,30000,30000) L_0x1d8d400/d; -v0x1b71880_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers -v0x1b719d0_0 .net "b", 0 0, L_0x1d8c510; alias, 1 drivers -v0x1b71a90_0 .net "c1", 0 0, L_0x1d8cf00; 1 drivers -v0x1b71b30_0 .net "c2", 0 0, L_0x1b71cf0; 1 drivers -v0x1b71c00_0 .net "carryin", 0 0, L_0x1d95e10; alias, 1 drivers -v0x1b71d80_0 .net "carryout", 0 0, L_0x1d8d400; 1 drivers -v0x1b71e20_0 .net "s1", 0 0, L_0x1d8ce40; 1 drivers -v0x1b71ec0_0 .net "sum", 0 0, L_0x1d8d060; 1 drivers -S_0x1b70ce0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b70a90; +L_0x1220a40/d .functor OR 1, L_0x1220590, L_0x1004980, C4<0>, C4<0>; +L_0x1220a40 .delay 1 (30000,30000,30000) L_0x1220a40/d; +v0x1004510_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers +v0x1004660_0 .net "b", 0 0, L_0x121fcb0; alias, 1 drivers +v0x1004720_0 .net "c1", 0 0, L_0x1220590; 1 drivers +v0x10047c0_0 .net "c2", 0 0, L_0x1004980; 1 drivers +v0x1004890_0 .net "carryin", 0 0, L_0x1229530; alias, 1 drivers +v0x1004a10_0 .net "carryout", 0 0, L_0x1220a40; 1 drivers +v0x1004ab0_0 .net "s1", 0 0, L_0x12204d0; 1 drivers +v0x1004b50_0 .net "sum", 0 0, L_0x12206f0; 1 drivers +S_0x1003970 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1003720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d8ce40/d .functor XOR 1, L_0x1d95c10, L_0x1d8c510, C4<0>, C4<0>; -L_0x1d8ce40 .delay 1 (30000,30000,30000) L_0x1d8ce40/d; -L_0x1d8cf00/d .functor AND 1, L_0x1d95c10, L_0x1d8c510, C4<1>, C4<1>; -L_0x1d8cf00 .delay 1 (30000,30000,30000) L_0x1d8cf00/d; -v0x1b70f40_0 .net "a", 0 0, L_0x1d95c10; alias, 1 drivers -v0x1b71000_0 .net "b", 0 0, L_0x1d8c510; alias, 1 drivers -v0x1b710c0_0 .net "carryout", 0 0, L_0x1d8cf00; alias, 1 drivers -v0x1b71160_0 .net "sum", 0 0, L_0x1d8ce40; alias, 1 drivers -S_0x1b71290 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b70a90; +L_0x12204d0/d .functor XOR 1, L_0x1229330, L_0x121fcb0, C4<0>, C4<0>; +L_0x12204d0 .delay 1 (30000,30000,30000) L_0x12204d0/d; +L_0x1220590/d .functor AND 1, L_0x1229330, L_0x121fcb0, C4<1>, C4<1>; +L_0x1220590 .delay 1 (30000,30000,30000) L_0x1220590/d; +v0x1003bd0_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers +v0x1003c90_0 .net "b", 0 0, L_0x121fcb0; alias, 1 drivers +v0x1003d50_0 .net "carryout", 0 0, L_0x1220590; alias, 1 drivers +v0x1003df0_0 .net "sum", 0 0, L_0x12204d0; alias, 1 drivers +S_0x1003f20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1003720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d8d060/d .functor XOR 1, L_0x1d8ce40, L_0x1d95e10, C4<0>, C4<0>; -L_0x1d8d060 .delay 1 (30000,30000,30000) L_0x1d8d060/d; -L_0x1b71cf0/d .functor AND 1, L_0x1d8ce40, L_0x1d95e10, C4<1>, C4<1>; -L_0x1b71cf0 .delay 1 (30000,30000,30000) L_0x1b71cf0/d; -v0x1b714f0_0 .net "a", 0 0, L_0x1d8ce40; alias, 1 drivers -v0x1b715c0_0 .net "b", 0 0, L_0x1d95e10; alias, 1 drivers -v0x1b71660_0 .net "carryout", 0 0, L_0x1b71cf0; alias, 1 drivers -v0x1b71730_0 .net "sum", 0 0, L_0x1d8d060; alias, 1 drivers -S_0x1b732e0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b635f0; - .timescale -9 -12; -L_0x7f72592da378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da3c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d95f40/d .functor OR 1, L_0x7f72592da378, L_0x7f72592da3c0, C4<0>, C4<0>; -L_0x1d95f40 .delay 1 (30000,30000,30000) L_0x1d95f40/d; -v0x1b734d0_0 .net/2u *"_s0", 0 0, L_0x7f72592da378; 1 drivers -v0x1b735b0_0 .net/2u *"_s2", 0 0, L_0x7f72592da3c0; 1 drivers -S_0x1b73690 .scope generate, "alu_slices[4]" "alu_slices[4]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1b738f0 .param/l "i" 0 3 37, +C4<0100>; -S_0x1b739b0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b73690; +L_0x12206f0/d .functor XOR 1, L_0x12204d0, L_0x1229530, C4<0>, C4<0>; +L_0x12206f0 .delay 1 (30000,30000,30000) L_0x12206f0/d; +L_0x1004980/d .functor AND 1, L_0x12204d0, L_0x1229530, C4<1>, C4<1>; +L_0x1004980 .delay 1 (30000,30000,30000) L_0x1004980/d; +v0x1004180_0 .net "a", 0 0, L_0x12204d0; alias, 1 drivers +v0x1004250_0 .net "b", 0 0, L_0x1229530; alias, 1 drivers +v0x10042f0_0 .net "carryout", 0 0, L_0x1004980; alias, 1 drivers +v0x10043c0_0 .net "sum", 0 0, L_0x12206f0; alias, 1 drivers +S_0x1005f70 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0xff6170; + .timescale -9 -12; +L_0x2b0ab3d05378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d053c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1229660/d .functor OR 1, L_0x2b0ab3d05378, L_0x2b0ab3d053c0, C4<0>, C4<0>; +L_0x1229660 .delay 1 (30000,30000,30000) L_0x1229660/d; +v0x1006160_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05378; 1 drivers +v0x1006240_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d053c0; 1 drivers +S_0x1006320 .scope generate, "alu_slices[4]" "alu_slices[4]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1006580 .param/l "i" 0 3 41, +C4<0100>; +S_0x1006640 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1006320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -2366,445 +2376,445 @@ S_0x1b739b0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b73690; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1d96050/d .functor NOT 1, L_0x1d9f810, C4<0>, C4<0>, C4<0>; -L_0x1d96050 .delay 1 (10000,10000,10000) L_0x1d96050/d; -L_0x1d96160/d .functor NOT 1, L_0x1d9f970, C4<0>, C4<0>, C4<0>; -L_0x1d96160 .delay 1 (10000,10000,10000) L_0x1d96160/d; -L_0x1d971b0/d .functor XOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; -L_0x1d971b0 .delay 1 (30000,30000,30000) L_0x1d971b0/d; -L_0x7f72592da408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d97860/d .functor OR 1, L_0x7f72592da408, L_0x7f72592da450, C4<0>, C4<0>; -L_0x1d97860 .delay 1 (30000,30000,30000) L_0x1d97860/d; -L_0x1d97a60/d .functor AND 1, L_0x1d9f810, L_0x1d9f970, C4<1>, C4<1>; -L_0x1d97a60 .delay 1 (30000,30000,30000) L_0x1d97a60/d; -L_0x1d97b20/d .functor NAND 1, L_0x1d9f810, L_0x1d9f970, C4<1>, C4<1>; -L_0x1d97b20 .delay 1 (20000,20000,20000) L_0x1d97b20/d; -L_0x1d97c80/d .functor XOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; -L_0x1d97c80 .delay 1 (20000,20000,20000) L_0x1d97c80/d; -L_0x1d98130/d .functor OR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; -L_0x1d98130 .delay 1 (30000,30000,30000) L_0x1d98130/d; -L_0x1d9f710/d .functor NOT 1, L_0x1d9b970, C4<0>, C4<0>, C4<0>; -L_0x1d9f710 .delay 1 (10000,10000,10000) L_0x1d9f710/d; -v0x1b820b0_0 .net "A", 0 0, L_0x1d9f810; 1 drivers -v0x1b82170_0 .net "A_", 0 0, L_0x1d96050; 1 drivers -v0x1b82230_0 .net "B", 0 0, L_0x1d9f970; 1 drivers -v0x1b82300_0 .net "B_", 0 0, L_0x1d96160; 1 drivers -v0x1b823a0_0 .net *"_s12", 0 0, L_0x1d97860; 1 drivers -v0x1b82490_0 .net/2s *"_s14", 0 0, L_0x7f72592da408; 1 drivers -v0x1b82550_0 .net/2s *"_s16", 0 0, L_0x7f72592da450; 1 drivers -v0x1b82630_0 .net *"_s18", 0 0, L_0x1d97a60; 1 drivers -v0x1b82710_0 .net *"_s20", 0 0, L_0x1d97b20; 1 drivers -v0x1b82880_0 .net *"_s22", 0 0, L_0x1d97c80; 1 drivers -v0x1b82960_0 .net *"_s24", 0 0, L_0x1d98130; 1 drivers -o0x7f725935f808 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1b82a40_0 name=_s30 -o0x7f725935f838 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1b82b20_0 name=_s32 -v0x1b82c00_0 .net *"_s8", 0 0, L_0x1d971b0; 1 drivers -v0x1b82ce0_0 .net "carryin", 0 0, L_0x1d9fa10; 1 drivers -v0x1b82d80_0 .net "carryout", 0 0, L_0x1d9f3b0; 1 drivers -v0x1b82e20_0 .net "carryouts", 7 0, L_0x1ebf1f0; 1 drivers -v0x1b82fd0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b83070_0 .net "result", 0 0, L_0x1d9b970; 1 drivers -v0x1b83160_0 .net "results", 7 0, L_0x1d97f00; 1 drivers -v0x1b83270_0 .net "zero", 0 0, L_0x1d9f710; 1 drivers -LS_0x1d97f00_0_0 .concat8 [ 1 1 1 1], L_0x1d96680, L_0x1d96cb0, L_0x1d971b0, L_0x1d97860; -LS_0x1d97f00_0_4 .concat8 [ 1 1 1 1], L_0x1d97a60, L_0x1d97b20, L_0x1d97c80, L_0x1d98130; -L_0x1d97f00 .concat8 [ 4 4 0 0], LS_0x1d97f00_0_0, LS_0x1d97f00_0_4; -LS_0x1ebf1f0_0_0 .concat [ 1 1 1 1], L_0x1d96930, L_0x1d97050, o0x7f725935f808, L_0x1d976b0; -LS_0x1ebf1f0_0_4 .concat [ 4 0 0 0], o0x7f725935f838; -L_0x1ebf1f0 .concat [ 4 4 0 0], LS_0x1ebf1f0_0_0, LS_0x1ebf1f0_0_4; -S_0x1b73c30 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b739b0; +L_0x1229770/d .functor NOT 1, L_0x1232f10, C4<0>, C4<0>, C4<0>; +L_0x1229770 .delay 1 (10000,10000,10000) L_0x1229770/d; +L_0x1229880/d .functor NOT 1, L_0x1233070, C4<0>, C4<0>, C4<0>; +L_0x1229880 .delay 1 (10000,10000,10000) L_0x1229880/d; +L_0x122a8d0/d .functor XOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; +L_0x122a8d0 .delay 1 (30000,30000,30000) L_0x122a8d0/d; +L_0x2b0ab3d05408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x122af80/d .functor OR 1, L_0x2b0ab3d05408, L_0x2b0ab3d05450, C4<0>, C4<0>; +L_0x122af80 .delay 1 (30000,30000,30000) L_0x122af80/d; +L_0x122b180/d .functor AND 1, L_0x1232f10, L_0x1233070, C4<1>, C4<1>; +L_0x122b180 .delay 1 (30000,30000,30000) L_0x122b180/d; +L_0x122b240/d .functor NAND 1, L_0x1232f10, L_0x1233070, C4<1>, C4<1>; +L_0x122b240 .delay 1 (20000,20000,20000) L_0x122b240/d; +L_0x122b3a0/d .functor XOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; +L_0x122b3a0 .delay 1 (20000,20000,20000) L_0x122b3a0/d; +L_0x122b850/d .functor OR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; +L_0x122b850 .delay 1 (30000,30000,30000) L_0x122b850/d; +L_0x1232e10/d .functor NOT 1, L_0x122f0e0, C4<0>, C4<0>, C4<0>; +L_0x1232e10 .delay 1 (10000,10000,10000) L_0x1232e10/d; +v0x1014d40_0 .net "A", 0 0, L_0x1232f10; 1 drivers +v0x1014e00_0 .net "A_", 0 0, L_0x1229770; 1 drivers +v0x1014ec0_0 .net "B", 0 0, L_0x1233070; 1 drivers +v0x1014f90_0 .net "B_", 0 0, L_0x1229880; 1 drivers +v0x1015030_0 .net *"_s12", 0 0, L_0x122af80; 1 drivers +v0x1015120_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05408; 1 drivers +v0x10151e0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05450; 1 drivers +v0x10152c0_0 .net *"_s18", 0 0, L_0x122b180; 1 drivers +v0x10153a0_0 .net *"_s20", 0 0, L_0x122b240; 1 drivers +v0x1015510_0 .net *"_s22", 0 0, L_0x122b3a0; 1 drivers +v0x10155f0_0 .net *"_s24", 0 0, L_0x122b850; 1 drivers +o0x2b0ab3cae808 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10156d0_0 name=_s30 +o0x2b0ab3cae838 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10157b0_0 name=_s32 +v0x1015890_0 .net *"_s8", 0 0, L_0x122a8d0; 1 drivers +v0x1015970_0 .net "carryin", 0 0, L_0x1233110; 1 drivers +v0x1015a10_0 .net "carryout", 0 0, L_0x1232ab0; 1 drivers +v0x1015ab0_0 .net "carryouts", 7 0, L_0x13535a0; 1 drivers +v0x1015c60_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1015d00_0 .net "result", 0 0, L_0x122f0e0; 1 drivers +v0x1015df0_0 .net "results", 7 0, L_0x122b620; 1 drivers +v0x1015f00_0 .net "zero", 0 0, L_0x1232e10; 1 drivers +LS_0x122b620_0_0 .concat8 [ 1 1 1 1], L_0x1229da0, L_0x122a3d0, L_0x122a8d0, L_0x122af80; +LS_0x122b620_0_4 .concat8 [ 1 1 1 1], L_0x122b180, L_0x122b240, L_0x122b3a0, L_0x122b850; +L_0x122b620 .concat8 [ 4 4 0 0], LS_0x122b620_0_0, LS_0x122b620_0_4; +LS_0x13535a0_0_0 .concat [ 1 1 1 1], L_0x122a050, L_0x122a770, o0x2b0ab3cae808, L_0x122add0; +LS_0x13535a0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cae838; +L_0x13535a0 .concat [ 4 4 0 0], LS_0x13535a0_0_0, LS_0x13535a0_0_4; +S_0x10068c0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1006640; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d96930/d .functor OR 1, L_0x1d96410, L_0x1d967d0, C4<0>, C4<0>; -L_0x1d96930 .delay 1 (30000,30000,30000) L_0x1d96930/d; -v0x1b74a30_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers -v0x1b74af0_0 .net "b", 0 0, L_0x1d9f970; alias, 1 drivers -v0x1b74bc0_0 .net "c1", 0 0, L_0x1d96410; 1 drivers -v0x1b74cc0_0 .net "c2", 0 0, L_0x1d967d0; 1 drivers -v0x1b74d90_0 .net "carryin", 0 0, L_0x1d9fa10; alias, 1 drivers -v0x1b74e80_0 .net "carryout", 0 0, L_0x1d96930; 1 drivers -v0x1b74f20_0 .net "s1", 0 0, L_0x1d96350; 1 drivers -v0x1b75010_0 .net "sum", 0 0, L_0x1d96680; 1 drivers -S_0x1b73ea0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b73c30; +L_0x122a050/d .functor OR 1, L_0x1229b30, L_0x1229ef0, C4<0>, C4<0>; +L_0x122a050 .delay 1 (30000,30000,30000) L_0x122a050/d; +v0x10076c0_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers +v0x1007780_0 .net "b", 0 0, L_0x1233070; alias, 1 drivers +v0x1007850_0 .net "c1", 0 0, L_0x1229b30; 1 drivers +v0x1007950_0 .net "c2", 0 0, L_0x1229ef0; 1 drivers +v0x1007a20_0 .net "carryin", 0 0, L_0x1233110; alias, 1 drivers +v0x1007b10_0 .net "carryout", 0 0, L_0x122a050; 1 drivers +v0x1007bb0_0 .net "s1", 0 0, L_0x1229a70; 1 drivers +v0x1007ca0_0 .net "sum", 0 0, L_0x1229da0; 1 drivers +S_0x1006b30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10068c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d96350/d .functor XOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; -L_0x1d96350 .delay 1 (30000,30000,30000) L_0x1d96350/d; -L_0x1d96410/d .functor AND 1, L_0x1d9f810, L_0x1d9f970, C4<1>, C4<1>; -L_0x1d96410 .delay 1 (30000,30000,30000) L_0x1d96410/d; -v0x1b74100_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers -v0x1b741e0_0 .net "b", 0 0, L_0x1d9f970; alias, 1 drivers -v0x1b742a0_0 .net "carryout", 0 0, L_0x1d96410; alias, 1 drivers -v0x1b74340_0 .net "sum", 0 0, L_0x1d96350; alias, 1 drivers -S_0x1b74480 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b73c30; +L_0x1229a70/d .functor XOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; +L_0x1229a70 .delay 1 (30000,30000,30000) L_0x1229a70/d; +L_0x1229b30/d .functor AND 1, L_0x1232f10, L_0x1233070, C4<1>, C4<1>; +L_0x1229b30 .delay 1 (30000,30000,30000) L_0x1229b30/d; +v0x1006d90_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers +v0x1006e70_0 .net "b", 0 0, L_0x1233070; alias, 1 drivers +v0x1006f30_0 .net "carryout", 0 0, L_0x1229b30; alias, 1 drivers +v0x1006fd0_0 .net "sum", 0 0, L_0x1229a70; alias, 1 drivers +S_0x1007110 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10068c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d96680/d .functor XOR 1, L_0x1d96350, L_0x1d9fa10, C4<0>, C4<0>; -L_0x1d96680 .delay 1 (30000,30000,30000) L_0x1d96680/d; -L_0x1d967d0/d .functor AND 1, L_0x1d96350, L_0x1d9fa10, C4<1>, C4<1>; -L_0x1d967d0 .delay 1 (30000,30000,30000) L_0x1d967d0/d; -v0x1b746e0_0 .net "a", 0 0, L_0x1d96350; alias, 1 drivers -v0x1b74780_0 .net "b", 0 0, L_0x1d9fa10; alias, 1 drivers -v0x1b74820_0 .net "carryout", 0 0, L_0x1d967d0; alias, 1 drivers -v0x1b748c0_0 .net "sum", 0 0, L_0x1d96680; alias, 1 drivers -S_0x1b750e0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b739b0; +L_0x1229da0/d .functor XOR 1, L_0x1229a70, L_0x1233110, C4<0>, C4<0>; +L_0x1229da0 .delay 1 (30000,30000,30000) L_0x1229da0/d; +L_0x1229ef0/d .functor AND 1, L_0x1229a70, L_0x1233110, C4<1>, C4<1>; +L_0x1229ef0 .delay 1 (30000,30000,30000) L_0x1229ef0/d; +v0x1007370_0 .net "a", 0 0, L_0x1229a70; alias, 1 drivers +v0x1007410_0 .net "b", 0 0, L_0x1233110; alias, 1 drivers +v0x10074b0_0 .net "carryout", 0 0, L_0x1229ef0; alias, 1 drivers +v0x1007550_0 .net "sum", 0 0, L_0x1229da0; alias, 1 drivers +S_0x1007d70 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1006640; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b7a4d0_0 .net "ands", 7 0, L_0x1d9d3b0; 1 drivers -v0x1b7a5e0_0 .net "in", 7 0, L_0x1ebf1f0; alias, 1 drivers -v0x1b7a6a0_0 .net "out", 0 0, L_0x1d9f3b0; alias, 1 drivers -v0x1b7a770_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b75300 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b750e0; +v0x100d160_0 .net "ands", 7 0, L_0x1230b20; 1 drivers +v0x100d270_0 .net "in", 7 0, L_0x13535a0; alias, 1 drivers +v0x100d330_0 .net "out", 0 0, L_0x1232ab0; alias, 1 drivers +v0x100d400_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1007f90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1007d70; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b77a30_0 .net "A", 7 0, L_0x1ebf1f0; alias, 1 drivers -v0x1b77b30_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b77bf0_0 .net *"_s0", 0 0, L_0x1d9bcd0; 1 drivers -v0x1b77cb0_0 .net *"_s12", 0 0, L_0x1d9c640; 1 drivers -v0x1b77d90_0 .net *"_s16", 0 0, L_0x1d9c9a0; 1 drivers -v0x1b77ec0_0 .net *"_s20", 0 0, L_0x1d9ccb0; 1 drivers -v0x1b77fa0_0 .net *"_s24", 0 0, L_0x1d9d0a0; 1 drivers -v0x1b78080_0 .net *"_s28", 0 0, L_0x1d9d030; 1 drivers -v0x1b78160_0 .net *"_s4", 0 0, L_0x1d9bfe0; 1 drivers -v0x1b782d0_0 .net *"_s8", 0 0, L_0x1d9c330; 1 drivers -v0x1b783b0_0 .net "out", 7 0, L_0x1d9d3b0; alias, 1 drivers -L_0x1d9bd90 .part L_0x1ebf1f0, 0, 1; -L_0x1d9bef0 .part v0x1d6daa0_0, 0, 1; -L_0x1d9c0a0 .part L_0x1ebf1f0, 1, 1; -L_0x1d9c290 .part v0x1d6daa0_0, 1, 1; -L_0x1d9c3f0 .part L_0x1ebf1f0, 2, 1; -L_0x1d9c550 .part v0x1d6daa0_0, 2, 1; -L_0x1d9c700 .part L_0x1ebf1f0, 3, 1; -L_0x1d9c860 .part v0x1d6daa0_0, 3, 1; -L_0x1d9ca60 .part L_0x1ebf1f0, 4, 1; -L_0x1d9cbc0 .part v0x1d6daa0_0, 4, 1; -L_0x1d9cd20 .part L_0x1ebf1f0, 5, 1; -L_0x1d9cf90 .part v0x1d6daa0_0, 5, 1; -L_0x1d9d160 .part L_0x1ebf1f0, 6, 1; -L_0x1d9d2c0 .part v0x1d6daa0_0, 6, 1; -LS_0x1d9d3b0_0_0 .concat8 [ 1 1 1 1], L_0x1d9bcd0, L_0x1d9bfe0, L_0x1d9c330, L_0x1d9c640; -LS_0x1d9d3b0_0_4 .concat8 [ 1 1 1 1], L_0x1d9c9a0, L_0x1d9ccb0, L_0x1d9d0a0, L_0x1d9d030; -L_0x1d9d3b0 .concat8 [ 4 4 0 0], LS_0x1d9d3b0_0_0, LS_0x1d9d3b0_0_4; -L_0x1d9d770 .part L_0x1ebf1f0, 7, 1; -L_0x1d9d960 .part v0x1d6daa0_0, 7, 1; -S_0x1b75560 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b75770 .param/l "i" 0 4 54, +C4<00>; -L_0x1d9bcd0/d .functor AND 1, L_0x1d9bd90, L_0x1d9bef0, C4<1>, C4<1>; -L_0x1d9bcd0 .delay 1 (30000,30000,30000) L_0x1d9bcd0/d; -v0x1b75850_0 .net *"_s0", 0 0, L_0x1d9bd90; 1 drivers -v0x1b75930_0 .net *"_s1", 0 0, L_0x1d9bef0; 1 drivers -S_0x1b75a10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b75c20 .param/l "i" 0 4 54, +C4<01>; -L_0x1d9bfe0/d .functor AND 1, L_0x1d9c0a0, L_0x1d9c290, C4<1>, C4<1>; -L_0x1d9bfe0 .delay 1 (30000,30000,30000) L_0x1d9bfe0/d; -v0x1b75ce0_0 .net *"_s0", 0 0, L_0x1d9c0a0; 1 drivers -v0x1b75dc0_0 .net *"_s1", 0 0, L_0x1d9c290; 1 drivers -S_0x1b75ea0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b760b0 .param/l "i" 0 4 54, +C4<010>; -L_0x1d9c330/d .functor AND 1, L_0x1d9c3f0, L_0x1d9c550, C4<1>, C4<1>; -L_0x1d9c330 .delay 1 (30000,30000,30000) L_0x1d9c330/d; -v0x1b76150_0 .net *"_s0", 0 0, L_0x1d9c3f0; 1 drivers -v0x1b76230_0 .net *"_s1", 0 0, L_0x1d9c550; 1 drivers -S_0x1b76310 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b76520 .param/l "i" 0 4 54, +C4<011>; -L_0x1d9c640/d .functor AND 1, L_0x1d9c700, L_0x1d9c860, C4<1>, C4<1>; -L_0x1d9c640 .delay 1 (30000,30000,30000) L_0x1d9c640/d; -v0x1b765e0_0 .net *"_s0", 0 0, L_0x1d9c700; 1 drivers -v0x1b766c0_0 .net *"_s1", 0 0, L_0x1d9c860; 1 drivers -S_0x1b767a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b76a00 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d9c9a0/d .functor AND 1, L_0x1d9ca60, L_0x1d9cbc0, C4<1>, C4<1>; -L_0x1d9c9a0 .delay 1 (30000,30000,30000) L_0x1d9c9a0/d; -v0x1b76ac0_0 .net *"_s0", 0 0, L_0x1d9ca60; 1 drivers -v0x1b76ba0_0 .net *"_s1", 0 0, L_0x1d9cbc0; 1 drivers -S_0x1b76c80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b76e90 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d9ccb0/d .functor AND 1, L_0x1d9cd20, L_0x1d9cf90, C4<1>, C4<1>; -L_0x1d9ccb0 .delay 1 (30000,30000,30000) L_0x1d9ccb0/d; -v0x1b76f50_0 .net *"_s0", 0 0, L_0x1d9cd20; 1 drivers -v0x1b77030_0 .net *"_s1", 0 0, L_0x1d9cf90; 1 drivers -S_0x1b77110 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b77320 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d9d0a0/d .functor AND 1, L_0x1d9d160, L_0x1d9d2c0, C4<1>, C4<1>; -L_0x1d9d0a0 .delay 1 (30000,30000,30000) L_0x1d9d0a0/d; -v0x1b773e0_0 .net *"_s0", 0 0, L_0x1d9d160; 1 drivers -v0x1b774c0_0 .net *"_s1", 0 0, L_0x1d9d2c0; 1 drivers -S_0x1b775a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b75300; - .timescale -9 -12; -P_0x1b777b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d9d030/d .functor AND 1, L_0x1d9d770, L_0x1d9d960, C4<1>, C4<1>; -L_0x1d9d030 .delay 1 (30000,30000,30000) L_0x1d9d030/d; -v0x1b77870_0 .net *"_s0", 0 0, L_0x1d9d770; 1 drivers -v0x1b77950_0 .net *"_s1", 0 0, L_0x1d9d960; 1 drivers -S_0x1b78510 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b750e0; +v0x100a6c0_0 .net "A", 7 0, L_0x13535a0; alias, 1 drivers +v0x100a7c0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x100a880_0 .net *"_s0", 0 0, L_0x122f440; 1 drivers +v0x100a940_0 .net *"_s12", 0 0, L_0x122fdb0; 1 drivers +v0x100aa20_0 .net *"_s16", 0 0, L_0x1230110; 1 drivers +v0x100ab50_0 .net *"_s20", 0 0, L_0x1230420; 1 drivers +v0x100ac30_0 .net *"_s24", 0 0, L_0x1230810; 1 drivers +v0x100ad10_0 .net *"_s28", 0 0, L_0x12307a0; 1 drivers +v0x100adf0_0 .net *"_s4", 0 0, L_0x122f750; 1 drivers +v0x100af60_0 .net *"_s8", 0 0, L_0x122faa0; 1 drivers +v0x100b040_0 .net "out", 7 0, L_0x1230b20; alias, 1 drivers +L_0x122f500 .part L_0x13535a0, 0, 1; +L_0x122f660 .part v0x12010b0_0, 0, 1; +L_0x122f810 .part L_0x13535a0, 1, 1; +L_0x122fa00 .part v0x12010b0_0, 1, 1; +L_0x122fb60 .part L_0x13535a0, 2, 1; +L_0x122fcc0 .part v0x12010b0_0, 2, 1; +L_0x122fe70 .part L_0x13535a0, 3, 1; +L_0x122ffd0 .part v0x12010b0_0, 3, 1; +L_0x12301d0 .part L_0x13535a0, 4, 1; +L_0x1230330 .part v0x12010b0_0, 4, 1; +L_0x1230490 .part L_0x13535a0, 5, 1; +L_0x1230700 .part v0x12010b0_0, 5, 1; +L_0x12308d0 .part L_0x13535a0, 6, 1; +L_0x1230a30 .part v0x12010b0_0, 6, 1; +LS_0x1230b20_0_0 .concat8 [ 1 1 1 1], L_0x122f440, L_0x122f750, L_0x122faa0, L_0x122fdb0; +LS_0x1230b20_0_4 .concat8 [ 1 1 1 1], L_0x1230110, L_0x1230420, L_0x1230810, L_0x12307a0; +L_0x1230b20 .concat8 [ 4 4 0 0], LS_0x1230b20_0_0, LS_0x1230b20_0_4; +L_0x1230ee0 .part L_0x13535a0, 7, 1; +L_0x1231060 .part v0x12010b0_0, 7, 1; +S_0x10081f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x1008400 .param/l "i" 0 4 54, +C4<00>; +L_0x122f440/d .functor AND 1, L_0x122f500, L_0x122f660, C4<1>, C4<1>; +L_0x122f440 .delay 1 (30000,30000,30000) L_0x122f440/d; +v0x10084e0_0 .net *"_s0", 0 0, L_0x122f500; 1 drivers +v0x10085c0_0 .net *"_s1", 0 0, L_0x122f660; 1 drivers +S_0x10086a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x10088b0 .param/l "i" 0 4 54, +C4<01>; +L_0x122f750/d .functor AND 1, L_0x122f810, L_0x122fa00, C4<1>, C4<1>; +L_0x122f750 .delay 1 (30000,30000,30000) L_0x122f750/d; +v0x1008970_0 .net *"_s0", 0 0, L_0x122f810; 1 drivers +v0x1008a50_0 .net *"_s1", 0 0, L_0x122fa00; 1 drivers +S_0x1008b30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x1008d40 .param/l "i" 0 4 54, +C4<010>; +L_0x122faa0/d .functor AND 1, L_0x122fb60, L_0x122fcc0, C4<1>, C4<1>; +L_0x122faa0 .delay 1 (30000,30000,30000) L_0x122faa0/d; +v0x1008de0_0 .net *"_s0", 0 0, L_0x122fb60; 1 drivers +v0x1008ec0_0 .net *"_s1", 0 0, L_0x122fcc0; 1 drivers +S_0x1008fa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x10091b0 .param/l "i" 0 4 54, +C4<011>; +L_0x122fdb0/d .functor AND 1, L_0x122fe70, L_0x122ffd0, C4<1>, C4<1>; +L_0x122fdb0 .delay 1 (30000,30000,30000) L_0x122fdb0/d; +v0x1009270_0 .net *"_s0", 0 0, L_0x122fe70; 1 drivers +v0x1009350_0 .net *"_s1", 0 0, L_0x122ffd0; 1 drivers +S_0x1009430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x1009690 .param/l "i" 0 4 54, +C4<0100>; +L_0x1230110/d .functor AND 1, L_0x12301d0, L_0x1230330, C4<1>, C4<1>; +L_0x1230110 .delay 1 (30000,30000,30000) L_0x1230110/d; +v0x1009750_0 .net *"_s0", 0 0, L_0x12301d0; 1 drivers +v0x1009830_0 .net *"_s1", 0 0, L_0x1230330; 1 drivers +S_0x1009910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x1009b20 .param/l "i" 0 4 54, +C4<0101>; +L_0x1230420/d .functor AND 1, L_0x1230490, L_0x1230700, C4<1>, C4<1>; +L_0x1230420 .delay 1 (30000,30000,30000) L_0x1230420/d; +v0x1009be0_0 .net *"_s0", 0 0, L_0x1230490; 1 drivers +v0x1009cc0_0 .net *"_s1", 0 0, L_0x1230700; 1 drivers +S_0x1009da0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x1009fb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1230810/d .functor AND 1, L_0x12308d0, L_0x1230a30, C4<1>, C4<1>; +L_0x1230810 .delay 1 (30000,30000,30000) L_0x1230810/d; +v0x100a070_0 .net *"_s0", 0 0, L_0x12308d0; 1 drivers +v0x100a150_0 .net *"_s1", 0 0, L_0x1230a30; 1 drivers +S_0x100a230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1007f90; + .timescale -9 -12; +P_0x100a440 .param/l "i" 0 4 54, +C4<0111>; +L_0x12307a0/d .functor AND 1, L_0x1230ee0, L_0x1231060, C4<1>, C4<1>; +L_0x12307a0 .delay 1 (30000,30000,30000) L_0x12307a0/d; +v0x100a500_0 .net *"_s0", 0 0, L_0x1230ee0; 1 drivers +v0x100a5e0_0 .net *"_s1", 0 0, L_0x1231060; 1 drivers +S_0x100b1a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1007d70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d9f3b0/d .functor OR 1, L_0x1d9f470, L_0x1d9f620, C4<0>, C4<0>; -L_0x1d9f3b0 .delay 1 (30000,30000,30000) L_0x1d9f3b0/d; -v0x1b7a060_0 .net *"_s10", 0 0, L_0x1d9f470; 1 drivers -v0x1b7a140_0 .net *"_s12", 0 0, L_0x1d9f620; 1 drivers -v0x1b7a220_0 .net "in", 7 0, L_0x1d9d3b0; alias, 1 drivers -v0x1b7a2f0_0 .net "ors", 1 0, L_0x1d9f1d0; 1 drivers -v0x1b7a3b0_0 .net "out", 0 0, L_0x1d9f3b0; alias, 1 drivers -L_0x1d9e5a0 .part L_0x1d9d3b0, 0, 4; -L_0x1d9f1d0 .concat8 [ 1 1 0 0], L_0x1d9e290, L_0x1d9eec0; -L_0x1d9f310 .part L_0x1d9d3b0, 4, 4; -L_0x1d9f470 .part L_0x1d9f1d0, 0, 1; -L_0x1d9f620 .part L_0x1d9f1d0, 1, 1; -S_0x1b786d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b78510; +L_0x1232ab0/d .functor OR 1, L_0x1232b70, L_0x1232d20, C4<0>, C4<0>; +L_0x1232ab0 .delay 1 (30000,30000,30000) L_0x1232ab0/d; +v0x100ccf0_0 .net *"_s10", 0 0, L_0x1232b70; 1 drivers +v0x100cdd0_0 .net *"_s12", 0 0, L_0x1232d20; 1 drivers +v0x100ceb0_0 .net "in", 7 0, L_0x1230b20; alias, 1 drivers +v0x100cf80_0 .net "ors", 1 0, L_0x12328d0; 1 drivers +v0x100d040_0 .net "out", 0 0, L_0x1232ab0; alias, 1 drivers +L_0x1231ca0 .part L_0x1230b20, 0, 4; +L_0x12328d0 .concat8 [ 1 1 0 0], L_0x1231990, L_0x12325c0; +L_0x1232a10 .part L_0x1230b20, 4, 4; +L_0x1232b70 .part L_0x12328d0, 0, 1; +L_0x1232d20 .part L_0x12328d0, 1, 1; +S_0x100b360 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x100b1a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d9da50/d .functor OR 1, L_0x1d9db10, L_0x1d9dc70, C4<0>, C4<0>; -L_0x1d9da50 .delay 1 (30000,30000,30000) L_0x1d9da50/d; -L_0x1d9dea0/d .functor OR 1, L_0x1d9dfb0, L_0x1d9e110, C4<0>, C4<0>; -L_0x1d9dea0 .delay 1 (30000,30000,30000) L_0x1d9dea0/d; -L_0x1d9e290/d .functor OR 1, L_0x1d9e300, L_0x1d9e4b0, C4<0>, C4<0>; -L_0x1d9e290 .delay 1 (30000,30000,30000) L_0x1d9e290/d; -v0x1b78920_0 .net *"_s0", 0 0, L_0x1d9da50; 1 drivers -v0x1b78a20_0 .net *"_s10", 0 0, L_0x1d9dfb0; 1 drivers -v0x1b78b00_0 .net *"_s12", 0 0, L_0x1d9e110; 1 drivers -v0x1b78bc0_0 .net *"_s14", 0 0, L_0x1d9e300; 1 drivers -v0x1b78ca0_0 .net *"_s16", 0 0, L_0x1d9e4b0; 1 drivers -v0x1b78dd0_0 .net *"_s3", 0 0, L_0x1d9db10; 1 drivers -v0x1b78eb0_0 .net *"_s5", 0 0, L_0x1d9dc70; 1 drivers -v0x1b78f90_0 .net *"_s6", 0 0, L_0x1d9dea0; 1 drivers -v0x1b79070_0 .net "in", 3 0, L_0x1d9e5a0; 1 drivers -v0x1b791e0_0 .net "ors", 1 0, L_0x1d9ddb0; 1 drivers -v0x1b792c0_0 .net "out", 0 0, L_0x1d9e290; 1 drivers -L_0x1d9db10 .part L_0x1d9e5a0, 0, 1; -L_0x1d9dc70 .part L_0x1d9e5a0, 1, 1; -L_0x1d9ddb0 .concat8 [ 1 1 0 0], L_0x1d9da50, L_0x1d9dea0; -L_0x1d9dfb0 .part L_0x1d9e5a0, 2, 1; -L_0x1d9e110 .part L_0x1d9e5a0, 3, 1; -L_0x1d9e300 .part L_0x1d9ddb0, 0, 1; -L_0x1d9e4b0 .part L_0x1d9ddb0, 1, 1; -S_0x1b793e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b78510; +L_0x1231150/d .functor OR 1, L_0x1231210, L_0x1231370, C4<0>, C4<0>; +L_0x1231150 .delay 1 (30000,30000,30000) L_0x1231150/d; +L_0x12315a0/d .functor OR 1, L_0x12316b0, L_0x1231810, C4<0>, C4<0>; +L_0x12315a0 .delay 1 (30000,30000,30000) L_0x12315a0/d; +L_0x1231990/d .functor OR 1, L_0x1231a00, L_0x1231bb0, C4<0>, C4<0>; +L_0x1231990 .delay 1 (30000,30000,30000) L_0x1231990/d; +v0x100b5b0_0 .net *"_s0", 0 0, L_0x1231150; 1 drivers +v0x100b6b0_0 .net *"_s10", 0 0, L_0x12316b0; 1 drivers +v0x100b790_0 .net *"_s12", 0 0, L_0x1231810; 1 drivers +v0x100b850_0 .net *"_s14", 0 0, L_0x1231a00; 1 drivers +v0x100b930_0 .net *"_s16", 0 0, L_0x1231bb0; 1 drivers +v0x100ba60_0 .net *"_s3", 0 0, L_0x1231210; 1 drivers +v0x100bb40_0 .net *"_s5", 0 0, L_0x1231370; 1 drivers +v0x100bc20_0 .net *"_s6", 0 0, L_0x12315a0; 1 drivers +v0x100bd00_0 .net "in", 3 0, L_0x1231ca0; 1 drivers +v0x100be70_0 .net "ors", 1 0, L_0x12314b0; 1 drivers +v0x100bf50_0 .net "out", 0 0, L_0x1231990; 1 drivers +L_0x1231210 .part L_0x1231ca0, 0, 1; +L_0x1231370 .part L_0x1231ca0, 1, 1; +L_0x12314b0 .concat8 [ 1 1 0 0], L_0x1231150, L_0x12315a0; +L_0x12316b0 .part L_0x1231ca0, 2, 1; +L_0x1231810 .part L_0x1231ca0, 3, 1; +L_0x1231a00 .part L_0x12314b0, 0, 1; +L_0x1231bb0 .part L_0x12314b0, 1, 1; +S_0x100c070 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x100b1a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d9e6d0/d .functor OR 1, L_0x1d9e740, L_0x1d9e8a0, C4<0>, C4<0>; -L_0x1d9e6d0 .delay 1 (30000,30000,30000) L_0x1d9e6d0/d; -L_0x1d9ead0/d .functor OR 1, L_0x1d9ebe0, L_0x1d9ed40, C4<0>, C4<0>; -L_0x1d9ead0 .delay 1 (30000,30000,30000) L_0x1d9ead0/d; -L_0x1d9eec0/d .functor OR 1, L_0x1d9ef30, L_0x1d9f0e0, C4<0>, C4<0>; -L_0x1d9eec0 .delay 1 (30000,30000,30000) L_0x1d9eec0/d; -v0x1b795a0_0 .net *"_s0", 0 0, L_0x1d9e6d0; 1 drivers -v0x1b796a0_0 .net *"_s10", 0 0, L_0x1d9ebe0; 1 drivers -v0x1b79780_0 .net *"_s12", 0 0, L_0x1d9ed40; 1 drivers -v0x1b79840_0 .net *"_s14", 0 0, L_0x1d9ef30; 1 drivers -v0x1b79920_0 .net *"_s16", 0 0, L_0x1d9f0e0; 1 drivers -v0x1b79a50_0 .net *"_s3", 0 0, L_0x1d9e740; 1 drivers -v0x1b79b30_0 .net *"_s5", 0 0, L_0x1d9e8a0; 1 drivers -v0x1b79c10_0 .net *"_s6", 0 0, L_0x1d9ead0; 1 drivers -v0x1b79cf0_0 .net "in", 3 0, L_0x1d9f310; 1 drivers -v0x1b79e60_0 .net "ors", 1 0, L_0x1d9e9e0; 1 drivers -v0x1b79f40_0 .net "out", 0 0, L_0x1d9eec0; 1 drivers -L_0x1d9e740 .part L_0x1d9f310, 0, 1; -L_0x1d9e8a0 .part L_0x1d9f310, 1, 1; -L_0x1d9e9e0 .concat8 [ 1 1 0 0], L_0x1d9e6d0, L_0x1d9ead0; -L_0x1d9ebe0 .part L_0x1d9f310, 2, 1; -L_0x1d9ed40 .part L_0x1d9f310, 3, 1; -L_0x1d9ef30 .part L_0x1d9e9e0, 0, 1; -L_0x1d9f0e0 .part L_0x1d9e9e0, 1, 1; -S_0x1b7a850 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b739b0; +L_0x1231dd0/d .functor OR 1, L_0x1231e40, L_0x1231fa0, C4<0>, C4<0>; +L_0x1231dd0 .delay 1 (30000,30000,30000) L_0x1231dd0/d; +L_0x12321d0/d .functor OR 1, L_0x12322e0, L_0x1232440, C4<0>, C4<0>; +L_0x12321d0 .delay 1 (30000,30000,30000) L_0x12321d0/d; +L_0x12325c0/d .functor OR 1, L_0x1232630, L_0x12327e0, C4<0>, C4<0>; +L_0x12325c0 .delay 1 (30000,30000,30000) L_0x12325c0/d; +v0x100c230_0 .net *"_s0", 0 0, L_0x1231dd0; 1 drivers +v0x100c330_0 .net *"_s10", 0 0, L_0x12322e0; 1 drivers +v0x100c410_0 .net *"_s12", 0 0, L_0x1232440; 1 drivers +v0x100c4d0_0 .net *"_s14", 0 0, L_0x1232630; 1 drivers +v0x100c5b0_0 .net *"_s16", 0 0, L_0x12327e0; 1 drivers +v0x100c6e0_0 .net *"_s3", 0 0, L_0x1231e40; 1 drivers +v0x100c7c0_0 .net *"_s5", 0 0, L_0x1231fa0; 1 drivers +v0x100c8a0_0 .net *"_s6", 0 0, L_0x12321d0; 1 drivers +v0x100c980_0 .net "in", 3 0, L_0x1232a10; 1 drivers +v0x100caf0_0 .net "ors", 1 0, L_0x12320e0; 1 drivers +v0x100cbd0_0 .net "out", 0 0, L_0x12325c0; 1 drivers +L_0x1231e40 .part L_0x1232a10, 0, 1; +L_0x1231fa0 .part L_0x1232a10, 1, 1; +L_0x12320e0 .concat8 [ 1 1 0 0], L_0x1231dd0, L_0x12321d0; +L_0x12322e0 .part L_0x1232a10, 2, 1; +L_0x1232440 .part L_0x1232a10, 3, 1; +L_0x1232630 .part L_0x12320e0, 0, 1; +L_0x12327e0 .part L_0x12320e0, 1, 1; +S_0x100d4e0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1006640; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b7fc80_0 .net "ands", 7 0, L_0x1d99970; 1 drivers -v0x1b7fd90_0 .net "in", 7 0, L_0x1d97f00; alias, 1 drivers -v0x1b7fe50_0 .net "out", 0 0, L_0x1d9b970; alias, 1 drivers -v0x1b7ff20_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b7aaa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b7a850; +v0x1012910_0 .net "ands", 7 0, L_0x122d0e0; 1 drivers +v0x1012a20_0 .net "in", 7 0, L_0x122b620; alias, 1 drivers +v0x1012ae0_0 .net "out", 0 0, L_0x122f0e0; alias, 1 drivers +v0x1012bb0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x100d730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x100d4e0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b7d1e0_0 .net "A", 7 0, L_0x1d97f00; alias, 1 drivers -v0x1b7d2e0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b7d3a0_0 .net *"_s0", 0 0, L_0x1d98290; 1 drivers -v0x1b7d460_0 .net *"_s12", 0 0, L_0x1d98c50; 1 drivers -v0x1b7d540_0 .net *"_s16", 0 0, L_0x1d85fc0; 1 drivers -v0x1b7d670_0 .net *"_s20", 0 0, L_0x1d992b0; 1 drivers -v0x1b7d750_0 .net *"_s24", 0 0, L_0x1d995e0; 1 drivers -v0x1b7d830_0 .net *"_s28", 0 0, L_0x1d99570; 1 drivers -v0x1b7d910_0 .net *"_s4", 0 0, L_0x1d98630; 1 drivers -v0x1b7da80_0 .net *"_s8", 0 0, L_0x1d98940; 1 drivers -v0x1b7db60_0 .net "out", 7 0, L_0x1d99970; alias, 1 drivers -L_0x1d983a0 .part L_0x1d97f00, 0, 1; -L_0x1d98590 .part v0x1d6daa0_0, 0, 1; -L_0x1d986f0 .part L_0x1d97f00, 1, 1; -L_0x1d98850 .part v0x1d6daa0_0, 1, 1; -L_0x1d98a00 .part L_0x1d97f00, 2, 1; -L_0x1d98b60 .part v0x1d6daa0_0, 2, 1; -L_0x1d98d10 .part L_0x1d97f00, 3, 1; -L_0x1d98e70 .part v0x1d6daa0_0, 3, 1; -L_0x1d98fb0 .part L_0x1d97f00, 4, 1; -L_0x1d991b0 .part v0x1d6daa0_0, 4, 1; -L_0x1d99320 .part L_0x1d97f00, 5, 1; -L_0x1d99480 .part v0x1d6daa0_0, 5, 1; -L_0x1d996a0 .part L_0x1d97f00, 6, 1; -L_0x1d99800 .part v0x1d6daa0_0, 6, 1; -LS_0x1d99970_0_0 .concat8 [ 1 1 1 1], L_0x1d98290, L_0x1d98630, L_0x1d98940, L_0x1d98c50; -LS_0x1d99970_0_4 .concat8 [ 1 1 1 1], L_0x1d85fc0, L_0x1d992b0, L_0x1d995e0, L_0x1d99570; -L_0x1d99970 .concat8 [ 4 4 0 0], LS_0x1d99970_0_0, LS_0x1d99970_0_4; -L_0x1d99d30 .part L_0x1d97f00, 7, 1; -L_0x1d99f20 .part v0x1d6daa0_0, 7, 1; -S_0x1b7ace0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7aef0 .param/l "i" 0 4 54, +C4<00>; -L_0x1d98290/d .functor AND 1, L_0x1d983a0, L_0x1d98590, C4<1>, C4<1>; -L_0x1d98290 .delay 1 (30000,30000,30000) L_0x1d98290/d; -v0x1b7afd0_0 .net *"_s0", 0 0, L_0x1d983a0; 1 drivers -v0x1b7b0b0_0 .net *"_s1", 0 0, L_0x1d98590; 1 drivers -S_0x1b7b190 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7b3a0 .param/l "i" 0 4 54, +C4<01>; -L_0x1d98630/d .functor AND 1, L_0x1d986f0, L_0x1d98850, C4<1>, C4<1>; -L_0x1d98630 .delay 1 (30000,30000,30000) L_0x1d98630/d; -v0x1b7b460_0 .net *"_s0", 0 0, L_0x1d986f0; 1 drivers -v0x1b7b540_0 .net *"_s1", 0 0, L_0x1d98850; 1 drivers -S_0x1b7b620 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7b860 .param/l "i" 0 4 54, +C4<010>; -L_0x1d98940/d .functor AND 1, L_0x1d98a00, L_0x1d98b60, C4<1>, C4<1>; -L_0x1d98940 .delay 1 (30000,30000,30000) L_0x1d98940/d; -v0x1b7b900_0 .net *"_s0", 0 0, L_0x1d98a00; 1 drivers -v0x1b7b9e0_0 .net *"_s1", 0 0, L_0x1d98b60; 1 drivers -S_0x1b7bac0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7bcd0 .param/l "i" 0 4 54, +C4<011>; -L_0x1d98c50/d .functor AND 1, L_0x1d98d10, L_0x1d98e70, C4<1>, C4<1>; -L_0x1d98c50 .delay 1 (30000,30000,30000) L_0x1d98c50/d; -v0x1b7bd90_0 .net *"_s0", 0 0, L_0x1d98d10; 1 drivers -v0x1b7be70_0 .net *"_s1", 0 0, L_0x1d98e70; 1 drivers -S_0x1b7bf50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7c1b0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1d85fc0/d .functor AND 1, L_0x1d98fb0, L_0x1d991b0, C4<1>, C4<1>; -L_0x1d85fc0 .delay 1 (30000,30000,30000) L_0x1d85fc0/d; -v0x1b7c270_0 .net *"_s0", 0 0, L_0x1d98fb0; 1 drivers -v0x1b7c350_0 .net *"_s1", 0 0, L_0x1d991b0; 1 drivers -S_0x1b7c430 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7c640 .param/l "i" 0 4 54, +C4<0101>; -L_0x1d992b0/d .functor AND 1, L_0x1d99320, L_0x1d99480, C4<1>, C4<1>; -L_0x1d992b0 .delay 1 (30000,30000,30000) L_0x1d992b0/d; -v0x1b7c700_0 .net *"_s0", 0 0, L_0x1d99320; 1 drivers -v0x1b7c7e0_0 .net *"_s1", 0 0, L_0x1d99480; 1 drivers -S_0x1b7c8c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7cad0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1d995e0/d .functor AND 1, L_0x1d996a0, L_0x1d99800, C4<1>, C4<1>; -L_0x1d995e0 .delay 1 (30000,30000,30000) L_0x1d995e0/d; -v0x1b7cb90_0 .net *"_s0", 0 0, L_0x1d996a0; 1 drivers -v0x1b7cc70_0 .net *"_s1", 0 0, L_0x1d99800; 1 drivers -S_0x1b7cd50 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b7aaa0; - .timescale -9 -12; -P_0x1b7cf60 .param/l "i" 0 4 54, +C4<0111>; -L_0x1d99570/d .functor AND 1, L_0x1d99d30, L_0x1d99f20, C4<1>, C4<1>; -L_0x1d99570 .delay 1 (30000,30000,30000) L_0x1d99570/d; -v0x1b7d020_0 .net *"_s0", 0 0, L_0x1d99d30; 1 drivers -v0x1b7d100_0 .net *"_s1", 0 0, L_0x1d99f20; 1 drivers -S_0x1b7dcc0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b7a850; +v0x100fe70_0 .net "A", 7 0, L_0x122b620; alias, 1 drivers +v0x100ff70_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1010030_0 .net *"_s0", 0 0, L_0x122b9b0; 1 drivers +v0x10100f0_0 .net *"_s12", 0 0, L_0x122c370; 1 drivers +v0x10101d0_0 .net *"_s16", 0 0, L_0x122c6d0; 1 drivers +v0x1010300_0 .net *"_s20", 0 0, L_0x122caa0; 1 drivers +v0x10103e0_0 .net *"_s24", 0 0, L_0x122cdd0; 1 drivers +v0x10104c0_0 .net *"_s28", 0 0, L_0x122cd60; 1 drivers +v0x10105a0_0 .net *"_s4", 0 0, L_0x122bd50; 1 drivers +v0x1010710_0 .net *"_s8", 0 0, L_0x122c060; 1 drivers +v0x10107f0_0 .net "out", 7 0, L_0x122d0e0; alias, 1 drivers +L_0x122bac0 .part L_0x122b620, 0, 1; +L_0x122bcb0 .part v0x12010b0_0, 0, 1; +L_0x122be10 .part L_0x122b620, 1, 1; +L_0x122bf70 .part v0x12010b0_0, 1, 1; +L_0x122c120 .part L_0x122b620, 2, 1; +L_0x122c280 .part v0x12010b0_0, 2, 1; +L_0x122c430 .part L_0x122b620, 3, 1; +L_0x122c590 .part v0x12010b0_0, 3, 1; +L_0x122c790 .part L_0x122b620, 4, 1; +L_0x122ca00 .part v0x12010b0_0, 4, 1; +L_0x122cb10 .part L_0x122b620, 5, 1; +L_0x122cc70 .part v0x12010b0_0, 5, 1; +L_0x122ce90 .part L_0x122b620, 6, 1; +L_0x122cff0 .part v0x12010b0_0, 6, 1; +LS_0x122d0e0_0_0 .concat8 [ 1 1 1 1], L_0x122b9b0, L_0x122bd50, L_0x122c060, L_0x122c370; +LS_0x122d0e0_0_4 .concat8 [ 1 1 1 1], L_0x122c6d0, L_0x122caa0, L_0x122cdd0, L_0x122cd60; +L_0x122d0e0 .concat8 [ 4 4 0 0], LS_0x122d0e0_0_0, LS_0x122d0e0_0_4; +L_0x122d4a0 .part L_0x122b620, 7, 1; +L_0x122d690 .part v0x12010b0_0, 7, 1; +S_0x100d970 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100db80 .param/l "i" 0 4 54, +C4<00>; +L_0x122b9b0/d .functor AND 1, L_0x122bac0, L_0x122bcb0, C4<1>, C4<1>; +L_0x122b9b0 .delay 1 (30000,30000,30000) L_0x122b9b0/d; +v0x100dc60_0 .net *"_s0", 0 0, L_0x122bac0; 1 drivers +v0x100dd40_0 .net *"_s1", 0 0, L_0x122bcb0; 1 drivers +S_0x100de20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100e030 .param/l "i" 0 4 54, +C4<01>; +L_0x122bd50/d .functor AND 1, L_0x122be10, L_0x122bf70, C4<1>, C4<1>; +L_0x122bd50 .delay 1 (30000,30000,30000) L_0x122bd50/d; +v0x100e0f0_0 .net *"_s0", 0 0, L_0x122be10; 1 drivers +v0x100e1d0_0 .net *"_s1", 0 0, L_0x122bf70; 1 drivers +S_0x100e2b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100e4f0 .param/l "i" 0 4 54, +C4<010>; +L_0x122c060/d .functor AND 1, L_0x122c120, L_0x122c280, C4<1>, C4<1>; +L_0x122c060 .delay 1 (30000,30000,30000) L_0x122c060/d; +v0x100e590_0 .net *"_s0", 0 0, L_0x122c120; 1 drivers +v0x100e670_0 .net *"_s1", 0 0, L_0x122c280; 1 drivers +S_0x100e750 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100e960 .param/l "i" 0 4 54, +C4<011>; +L_0x122c370/d .functor AND 1, L_0x122c430, L_0x122c590, C4<1>, C4<1>; +L_0x122c370 .delay 1 (30000,30000,30000) L_0x122c370/d; +v0x100ea20_0 .net *"_s0", 0 0, L_0x122c430; 1 drivers +v0x100eb00_0 .net *"_s1", 0 0, L_0x122c590; 1 drivers +S_0x100ebe0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100ee40 .param/l "i" 0 4 54, +C4<0100>; +L_0x122c6d0/d .functor AND 1, L_0x122c790, L_0x122ca00, C4<1>, C4<1>; +L_0x122c6d0 .delay 1 (30000,30000,30000) L_0x122c6d0/d; +v0x100ef00_0 .net *"_s0", 0 0, L_0x122c790; 1 drivers +v0x100efe0_0 .net *"_s1", 0 0, L_0x122ca00; 1 drivers +S_0x100f0c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100f2d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x122caa0/d .functor AND 1, L_0x122cb10, L_0x122cc70, C4<1>, C4<1>; +L_0x122caa0 .delay 1 (30000,30000,30000) L_0x122caa0/d; +v0x100f390_0 .net *"_s0", 0 0, L_0x122cb10; 1 drivers +v0x100f470_0 .net *"_s1", 0 0, L_0x122cc70; 1 drivers +S_0x100f550 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100f760 .param/l "i" 0 4 54, +C4<0110>; +L_0x122cdd0/d .functor AND 1, L_0x122ce90, L_0x122cff0, C4<1>, C4<1>; +L_0x122cdd0 .delay 1 (30000,30000,30000) L_0x122cdd0/d; +v0x100f820_0 .net *"_s0", 0 0, L_0x122ce90; 1 drivers +v0x100f900_0 .net *"_s1", 0 0, L_0x122cff0; 1 drivers +S_0x100f9e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x100d730; + .timescale -9 -12; +P_0x100fbf0 .param/l "i" 0 4 54, +C4<0111>; +L_0x122cd60/d .functor AND 1, L_0x122d4a0, L_0x122d690, C4<1>, C4<1>; +L_0x122cd60 .delay 1 (30000,30000,30000) L_0x122cd60/d; +v0x100fcb0_0 .net *"_s0", 0 0, L_0x122d4a0; 1 drivers +v0x100fd90_0 .net *"_s1", 0 0, L_0x122d690; 1 drivers +S_0x1010950 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x100d4e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1d9b970/d .functor OR 1, L_0x1d9ba30, L_0x1d9bbe0, C4<0>, C4<0>; -L_0x1d9b970 .delay 1 (30000,30000,30000) L_0x1d9b970/d; -v0x1b7f810_0 .net *"_s10", 0 0, L_0x1d9ba30; 1 drivers -v0x1b7f8f0_0 .net *"_s12", 0 0, L_0x1d9bbe0; 1 drivers -v0x1b7f9d0_0 .net "in", 7 0, L_0x1d99970; alias, 1 drivers -v0x1b7faa0_0 .net "ors", 1 0, L_0x1d9b790; 1 drivers -v0x1b7fb60_0 .net "out", 0 0, L_0x1d9b970; alias, 1 drivers -L_0x1d9ab60 .part L_0x1d99970, 0, 4; -L_0x1d9b790 .concat8 [ 1 1 0 0], L_0x1d9a850, L_0x1d9b480; -L_0x1d9b8d0 .part L_0x1d99970, 4, 4; -L_0x1d9ba30 .part L_0x1d9b790, 0, 1; -L_0x1d9bbe0 .part L_0x1d9b790, 1, 1; -S_0x1b7de80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b7dcc0; +L_0x122f0e0/d .functor OR 1, L_0x122f1a0, L_0x122f350, C4<0>, C4<0>; +L_0x122f0e0 .delay 1 (30000,30000,30000) L_0x122f0e0/d; +v0x10124a0_0 .net *"_s10", 0 0, L_0x122f1a0; 1 drivers +v0x1012580_0 .net *"_s12", 0 0, L_0x122f350; 1 drivers +v0x1012660_0 .net "in", 7 0, L_0x122d0e0; alias, 1 drivers +v0x1012730_0 .net "ors", 1 0, L_0x122ef00; 1 drivers +v0x10127f0_0 .net "out", 0 0, L_0x122f0e0; alias, 1 drivers +L_0x122e2d0 .part L_0x122d0e0, 0, 4; +L_0x122ef00 .concat8 [ 1 1 0 0], L_0x122dfc0, L_0x122ebf0; +L_0x122f040 .part L_0x122d0e0, 4, 4; +L_0x122f1a0 .part L_0x122ef00, 0, 1; +L_0x122f350 .part L_0x122ef00, 1, 1; +S_0x1010b10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1010950; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d9a010/d .functor OR 1, L_0x1d9a0d0, L_0x1d9a230, C4<0>, C4<0>; -L_0x1d9a010 .delay 1 (30000,30000,30000) L_0x1d9a010/d; -L_0x1d9a460/d .functor OR 1, L_0x1d9a570, L_0x1d9a6d0, C4<0>, C4<0>; -L_0x1d9a460 .delay 1 (30000,30000,30000) L_0x1d9a460/d; -L_0x1d9a850/d .functor OR 1, L_0x1d9a8c0, L_0x1d9aa70, C4<0>, C4<0>; -L_0x1d9a850 .delay 1 (30000,30000,30000) L_0x1d9a850/d; -v0x1b7e0d0_0 .net *"_s0", 0 0, L_0x1d9a010; 1 drivers -v0x1b7e1d0_0 .net *"_s10", 0 0, L_0x1d9a570; 1 drivers -v0x1b7e2b0_0 .net *"_s12", 0 0, L_0x1d9a6d0; 1 drivers -v0x1b7e370_0 .net *"_s14", 0 0, L_0x1d9a8c0; 1 drivers -v0x1b7e450_0 .net *"_s16", 0 0, L_0x1d9aa70; 1 drivers -v0x1b7e580_0 .net *"_s3", 0 0, L_0x1d9a0d0; 1 drivers -v0x1b7e660_0 .net *"_s5", 0 0, L_0x1d9a230; 1 drivers -v0x1b7e740_0 .net *"_s6", 0 0, L_0x1d9a460; 1 drivers -v0x1b7e820_0 .net "in", 3 0, L_0x1d9ab60; 1 drivers -v0x1b7e990_0 .net "ors", 1 0, L_0x1d9a370; 1 drivers -v0x1b7ea70_0 .net "out", 0 0, L_0x1d9a850; 1 drivers -L_0x1d9a0d0 .part L_0x1d9ab60, 0, 1; -L_0x1d9a230 .part L_0x1d9ab60, 1, 1; -L_0x1d9a370 .concat8 [ 1 1 0 0], L_0x1d9a010, L_0x1d9a460; -L_0x1d9a570 .part L_0x1d9ab60, 2, 1; -L_0x1d9a6d0 .part L_0x1d9ab60, 3, 1; -L_0x1d9a8c0 .part L_0x1d9a370, 0, 1; -L_0x1d9aa70 .part L_0x1d9a370, 1, 1; -S_0x1b7eb90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b7dcc0; +L_0x122d780/d .functor OR 1, L_0x122d840, L_0x122d9a0, C4<0>, C4<0>; +L_0x122d780 .delay 1 (30000,30000,30000) L_0x122d780/d; +L_0x122dbd0/d .functor OR 1, L_0x122dce0, L_0x122de40, C4<0>, C4<0>; +L_0x122dbd0 .delay 1 (30000,30000,30000) L_0x122dbd0/d; +L_0x122dfc0/d .functor OR 1, L_0x122e030, L_0x122e1e0, C4<0>, C4<0>; +L_0x122dfc0 .delay 1 (30000,30000,30000) L_0x122dfc0/d; +v0x1010d60_0 .net *"_s0", 0 0, L_0x122d780; 1 drivers +v0x1010e60_0 .net *"_s10", 0 0, L_0x122dce0; 1 drivers +v0x1010f40_0 .net *"_s12", 0 0, L_0x122de40; 1 drivers +v0x1011000_0 .net *"_s14", 0 0, L_0x122e030; 1 drivers +v0x10110e0_0 .net *"_s16", 0 0, L_0x122e1e0; 1 drivers +v0x1011210_0 .net *"_s3", 0 0, L_0x122d840; 1 drivers +v0x10112f0_0 .net *"_s5", 0 0, L_0x122d9a0; 1 drivers +v0x10113d0_0 .net *"_s6", 0 0, L_0x122dbd0; 1 drivers +v0x10114b0_0 .net "in", 3 0, L_0x122e2d0; 1 drivers +v0x1011620_0 .net "ors", 1 0, L_0x122dae0; 1 drivers +v0x1011700_0 .net "out", 0 0, L_0x122dfc0; 1 drivers +L_0x122d840 .part L_0x122e2d0, 0, 1; +L_0x122d9a0 .part L_0x122e2d0, 1, 1; +L_0x122dae0 .concat8 [ 1 1 0 0], L_0x122d780, L_0x122dbd0; +L_0x122dce0 .part L_0x122e2d0, 2, 1; +L_0x122de40 .part L_0x122e2d0, 3, 1; +L_0x122e030 .part L_0x122dae0, 0, 1; +L_0x122e1e0 .part L_0x122dae0, 1, 1; +S_0x1011820 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1010950; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1d9ac90/d .functor OR 1, L_0x1d9ad00, L_0x1d9ae60, C4<0>, C4<0>; -L_0x1d9ac90 .delay 1 (30000,30000,30000) L_0x1d9ac90/d; -L_0x1d9b090/d .functor OR 1, L_0x1d9b1a0, L_0x1d9b300, C4<0>, C4<0>; -L_0x1d9b090 .delay 1 (30000,30000,30000) L_0x1d9b090/d; -L_0x1d9b480/d .functor OR 1, L_0x1d9b4f0, L_0x1d9b6a0, C4<0>, C4<0>; -L_0x1d9b480 .delay 1 (30000,30000,30000) L_0x1d9b480/d; -v0x1b7ed50_0 .net *"_s0", 0 0, L_0x1d9ac90; 1 drivers -v0x1b7ee50_0 .net *"_s10", 0 0, L_0x1d9b1a0; 1 drivers -v0x1b7ef30_0 .net *"_s12", 0 0, L_0x1d9b300; 1 drivers -v0x1b7eff0_0 .net *"_s14", 0 0, L_0x1d9b4f0; 1 drivers -v0x1b7f0d0_0 .net *"_s16", 0 0, L_0x1d9b6a0; 1 drivers -v0x1b7f200_0 .net *"_s3", 0 0, L_0x1d9ad00; 1 drivers -v0x1b7f2e0_0 .net *"_s5", 0 0, L_0x1d9ae60; 1 drivers -v0x1b7f3c0_0 .net *"_s6", 0 0, L_0x1d9b090; 1 drivers -v0x1b7f4a0_0 .net "in", 3 0, L_0x1d9b8d0; 1 drivers -v0x1b7f610_0 .net "ors", 1 0, L_0x1d9afa0; 1 drivers -v0x1b7f6f0_0 .net "out", 0 0, L_0x1d9b480; 1 drivers -L_0x1d9ad00 .part L_0x1d9b8d0, 0, 1; -L_0x1d9ae60 .part L_0x1d9b8d0, 1, 1; -L_0x1d9afa0 .concat8 [ 1 1 0 0], L_0x1d9ac90, L_0x1d9b090; -L_0x1d9b1a0 .part L_0x1d9b8d0, 2, 1; -L_0x1d9b300 .part L_0x1d9b8d0, 3, 1; -L_0x1d9b4f0 .part L_0x1d9afa0, 0, 1; -L_0x1d9b6a0 .part L_0x1d9afa0, 1, 1; -S_0x1b80000 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b739b0; +L_0x122e400/d .functor OR 1, L_0x122e470, L_0x122e5d0, C4<0>, C4<0>; +L_0x122e400 .delay 1 (30000,30000,30000) L_0x122e400/d; +L_0x122e800/d .functor OR 1, L_0x122e910, L_0x122ea70, C4<0>, C4<0>; +L_0x122e800 .delay 1 (30000,30000,30000) L_0x122e800/d; +L_0x122ebf0/d .functor OR 1, L_0x122ec60, L_0x122ee10, C4<0>, C4<0>; +L_0x122ebf0 .delay 1 (30000,30000,30000) L_0x122ebf0/d; +v0x10119e0_0 .net *"_s0", 0 0, L_0x122e400; 1 drivers +v0x1011ae0_0 .net *"_s10", 0 0, L_0x122e910; 1 drivers +v0x1011bc0_0 .net *"_s12", 0 0, L_0x122ea70; 1 drivers +v0x1011c80_0 .net *"_s14", 0 0, L_0x122ec60; 1 drivers +v0x1011d60_0 .net *"_s16", 0 0, L_0x122ee10; 1 drivers +v0x1011e90_0 .net *"_s3", 0 0, L_0x122e470; 1 drivers +v0x1011f70_0 .net *"_s5", 0 0, L_0x122e5d0; 1 drivers +v0x1012050_0 .net *"_s6", 0 0, L_0x122e800; 1 drivers +v0x1012130_0 .net "in", 3 0, L_0x122f040; 1 drivers +v0x10122a0_0 .net "ors", 1 0, L_0x122e710; 1 drivers +v0x1012380_0 .net "out", 0 0, L_0x122ebf0; 1 drivers +L_0x122e470 .part L_0x122f040, 0, 1; +L_0x122e5d0 .part L_0x122f040, 1, 1; +L_0x122e710 .concat8 [ 1 1 0 0], L_0x122e400, L_0x122e800; +L_0x122e910 .part L_0x122f040, 2, 1; +L_0x122ea70 .part L_0x122f040, 3, 1; +L_0x122ec60 .part L_0x122e710, 0, 1; +L_0x122ee10 .part L_0x122e710, 1, 1; +S_0x1012c90 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1006640; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -2812,80 +2822,80 @@ S_0x1b80000 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b739b0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1d97270/d .functor XNOR 1, L_0x1d9f810, L_0x1d9f970, C4<0>, C4<0>; -L_0x1d97270 .delay 1 (20000,20000,20000) L_0x1d97270/d; -L_0x1d974e0/d .functor AND 1, L_0x1d9f810, L_0x1d96160, C4<1>, C4<1>; -L_0x1d974e0 .delay 1 (30000,30000,30000) L_0x1d974e0/d; -L_0x1d97550/d .functor AND 1, L_0x1d97270, L_0x1d9fa10, C4<1>, C4<1>; -L_0x1d97550 .delay 1 (30000,30000,30000) L_0x1d97550/d; -L_0x1d976b0/d .functor OR 1, L_0x1d97550, L_0x1d974e0, C4<0>, C4<0>; -L_0x1d976b0 .delay 1 (30000,30000,30000) L_0x1d976b0/d; -v0x1b802b0_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers -v0x1b803a0_0 .net "a_", 0 0, L_0x1d96050; alias, 1 drivers -v0x1b80460_0 .net "b", 0 0, L_0x1d9f970; alias, 1 drivers -v0x1b80550_0 .net "b_", 0 0, L_0x1d96160; alias, 1 drivers -v0x1b805f0_0 .net "carryin", 0 0, L_0x1d9fa10; alias, 1 drivers -v0x1b80730_0 .net "eq", 0 0, L_0x1d97270; 1 drivers -v0x1b807f0_0 .net "lt", 0 0, L_0x1d974e0; 1 drivers -v0x1b808b0_0 .net "out", 0 0, L_0x1d976b0; 1 drivers -v0x1b80970_0 .net "w0", 0 0, L_0x1d97550; 1 drivers -S_0x1b80bc0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b739b0; +L_0x122a990/d .functor XNOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; +L_0x122a990 .delay 1 (20000,20000,20000) L_0x122a990/d; +L_0x122ac00/d .functor AND 1, L_0x1232f10, L_0x1229880, C4<1>, C4<1>; +L_0x122ac00 .delay 1 (30000,30000,30000) L_0x122ac00/d; +L_0x122ac70/d .functor AND 1, L_0x122a990, L_0x1233110, C4<1>, C4<1>; +L_0x122ac70 .delay 1 (30000,30000,30000) L_0x122ac70/d; +L_0x122add0/d .functor OR 1, L_0x122ac70, L_0x122ac00, C4<0>, C4<0>; +L_0x122add0 .delay 1 (30000,30000,30000) L_0x122add0/d; +v0x1012f40_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers +v0x1013030_0 .net "a_", 0 0, L_0x1229770; alias, 1 drivers +v0x10130f0_0 .net "b", 0 0, L_0x1233070; alias, 1 drivers +v0x10131e0_0 .net "b_", 0 0, L_0x1229880; alias, 1 drivers +v0x1013280_0 .net "carryin", 0 0, L_0x1233110; alias, 1 drivers +v0x10133c0_0 .net "eq", 0 0, L_0x122a990; 1 drivers +v0x1013480_0 .net "lt", 0 0, L_0x122ac00; 1 drivers +v0x1013540_0 .net "out", 0 0, L_0x122add0; 1 drivers +v0x1013600_0 .net "w0", 0 0, L_0x122ac70; 1 drivers +S_0x1013850 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1006640; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1d97050/d .functor OR 1, L_0x1d96b50, L_0x1b81e20, C4<0>, C4<0>; -L_0x1d97050 .delay 1 (30000,30000,30000) L_0x1d97050/d; -v0x1b819b0_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers -v0x1b81b00_0 .net "b", 0 0, L_0x1d96160; alias, 1 drivers -v0x1b81bc0_0 .net "c1", 0 0, L_0x1d96b50; 1 drivers -v0x1b81c60_0 .net "c2", 0 0, L_0x1b81e20; 1 drivers -v0x1b81d30_0 .net "carryin", 0 0, L_0x1d9fa10; alias, 1 drivers -v0x1b81eb0_0 .net "carryout", 0 0, L_0x1d97050; 1 drivers -v0x1b81f50_0 .net "s1", 0 0, L_0x1d96a90; 1 drivers -v0x1b81ff0_0 .net "sum", 0 0, L_0x1d96cb0; 1 drivers -S_0x1b80e10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b80bc0; +L_0x122a770/d .functor OR 1, L_0x122a270, L_0x1014ab0, C4<0>, C4<0>; +L_0x122a770 .delay 1 (30000,30000,30000) L_0x122a770/d; +v0x1014640_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers +v0x1014790_0 .net "b", 0 0, L_0x1229880; alias, 1 drivers +v0x1014850_0 .net "c1", 0 0, L_0x122a270; 1 drivers +v0x10148f0_0 .net "c2", 0 0, L_0x1014ab0; 1 drivers +v0x10149c0_0 .net "carryin", 0 0, L_0x1233110; alias, 1 drivers +v0x1014b40_0 .net "carryout", 0 0, L_0x122a770; 1 drivers +v0x1014be0_0 .net "s1", 0 0, L_0x122a1b0; 1 drivers +v0x1014c80_0 .net "sum", 0 0, L_0x122a3d0; 1 drivers +S_0x1013aa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1013850; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d96a90/d .functor XOR 1, L_0x1d9f810, L_0x1d96160, C4<0>, C4<0>; -L_0x1d96a90 .delay 1 (30000,30000,30000) L_0x1d96a90/d; -L_0x1d96b50/d .functor AND 1, L_0x1d9f810, L_0x1d96160, C4<1>, C4<1>; -L_0x1d96b50 .delay 1 (30000,30000,30000) L_0x1d96b50/d; -v0x1b81070_0 .net "a", 0 0, L_0x1d9f810; alias, 1 drivers -v0x1b81130_0 .net "b", 0 0, L_0x1d96160; alias, 1 drivers -v0x1b811f0_0 .net "carryout", 0 0, L_0x1d96b50; alias, 1 drivers -v0x1b81290_0 .net "sum", 0 0, L_0x1d96a90; alias, 1 drivers -S_0x1b813c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b80bc0; +L_0x122a1b0/d .functor XOR 1, L_0x1232f10, L_0x1229880, C4<0>, C4<0>; +L_0x122a1b0 .delay 1 (30000,30000,30000) L_0x122a1b0/d; +L_0x122a270/d .functor AND 1, L_0x1232f10, L_0x1229880, C4<1>, C4<1>; +L_0x122a270 .delay 1 (30000,30000,30000) L_0x122a270/d; +v0x1013d00_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers +v0x1013dc0_0 .net "b", 0 0, L_0x1229880; alias, 1 drivers +v0x1013e80_0 .net "carryout", 0 0, L_0x122a270; alias, 1 drivers +v0x1013f20_0 .net "sum", 0 0, L_0x122a1b0; alias, 1 drivers +S_0x1014050 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1013850; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d96cb0/d .functor XOR 1, L_0x1d96a90, L_0x1d9fa10, C4<0>, C4<0>; -L_0x1d96cb0 .delay 1 (30000,30000,30000) L_0x1d96cb0/d; -L_0x1b81e20/d .functor AND 1, L_0x1d96a90, L_0x1d9fa10, C4<1>, C4<1>; -L_0x1b81e20 .delay 1 (30000,30000,30000) L_0x1b81e20/d; -v0x1b81620_0 .net "a", 0 0, L_0x1d96a90; alias, 1 drivers -v0x1b816f0_0 .net "b", 0 0, L_0x1d9fa10; alias, 1 drivers -v0x1b81790_0 .net "carryout", 0 0, L_0x1b81e20; alias, 1 drivers -v0x1b81860_0 .net "sum", 0 0, L_0x1d96cb0; alias, 1 drivers -S_0x1b83410 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b73690; - .timescale -9 -12; -L_0x7f72592da498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da4e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1d95cb0/d .functor OR 1, L_0x7f72592da498, L_0x7f72592da4e0, C4<0>, C4<0>; -L_0x1d95cb0 .delay 1 (30000,30000,30000) L_0x1d95cb0/d; -v0x1b83600_0 .net/2u *"_s0", 0 0, L_0x7f72592da498; 1 drivers -v0x1b836e0_0 .net/2u *"_s2", 0 0, L_0x7f72592da4e0; 1 drivers -S_0x1b837c0 .scope generate, "alu_slices[5]" "alu_slices[5]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1b839d0 .param/l "i" 0 3 37, +C4<0101>; -S_0x1b83a90 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b837c0; +L_0x122a3d0/d .functor XOR 1, L_0x122a1b0, L_0x1233110, C4<0>, C4<0>; +L_0x122a3d0 .delay 1 (30000,30000,30000) L_0x122a3d0/d; +L_0x1014ab0/d .functor AND 1, L_0x122a1b0, L_0x1233110, C4<1>, C4<1>; +L_0x1014ab0 .delay 1 (30000,30000,30000) L_0x1014ab0/d; +v0x10142b0_0 .net "a", 0 0, L_0x122a1b0; alias, 1 drivers +v0x1014380_0 .net "b", 0 0, L_0x1233110; alias, 1 drivers +v0x1014420_0 .net "carryout", 0 0, L_0x1014ab0; alias, 1 drivers +v0x10144f0_0 .net "sum", 0 0, L_0x122a3d0; alias, 1 drivers +S_0x10160a0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1006320; + .timescale -9 -12; +L_0x2b0ab3d05498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d054e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12293d0/d .functor OR 1, L_0x2b0ab3d05498, L_0x2b0ab3d054e0, C4<0>, C4<0>; +L_0x12293d0 .delay 1 (30000,30000,30000) L_0x12293d0/d; +v0x1016290_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05498; 1 drivers +v0x1016370_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d054e0; 1 drivers +S_0x1016450 .scope generate, "alu_slices[5]" "alu_slices[5]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1016660 .param/l "i" 0 3 41, +C4<0101>; +S_0x1016720 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1016450; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -2894,445 +2904,445 @@ S_0x1b83a90 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b837c0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1d9fb50/d .functor NOT 1, L_0x1daa3a0, C4<0>, C4<0>, C4<0>; -L_0x1d9fb50 .delay 1 (10000,10000,10000) L_0x1d9fb50/d; -L_0x1d9fd20/d .functor NOT 1, L_0x1daa590, C4<0>, C4<0>, C4<0>; -L_0x1d9fd20 .delay 1 (10000,10000,10000) L_0x1d9fd20/d; -L_0x1da0cd0/d .functor XOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; -L_0x1da0cd0 .delay 1 (30000,30000,30000) L_0x1da0cd0/d; -L_0x7f72592da528 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da570 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1da1380/d .functor OR 1, L_0x7f72592da528, L_0x7f72592da570, C4<0>, C4<0>; -L_0x1da1380 .delay 1 (30000,30000,30000) L_0x1da1380/d; -L_0x1da1580/d .functor AND 1, L_0x1daa3a0, L_0x1daa590, C4<1>, C4<1>; -L_0x1da1580 .delay 1 (30000,30000,30000) L_0x1da1580/d; -L_0x1da1640/d .functor NAND 1, L_0x1daa3a0, L_0x1daa590, C4<1>, C4<1>; -L_0x1da1640 .delay 1 (20000,20000,20000) L_0x1da1640/d; -L_0x1da17a0/d .functor XOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; -L_0x1da17a0 .delay 1 (20000,20000,20000) L_0x1da17a0/d; -L_0x1da1c50/d .functor OR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; -L_0x1da1c50 .delay 1 (30000,30000,30000) L_0x1da1c50/d; -L_0x1daa2a0/d .functor NOT 1, L_0x1da55c0, C4<0>, C4<0>, C4<0>; -L_0x1daa2a0 .delay 1 (10000,10000,10000) L_0x1daa2a0/d; -v0x1b921d0_0 .net "A", 0 0, L_0x1daa3a0; 1 drivers -v0x1b92290_0 .net "A_", 0 0, L_0x1d9fb50; 1 drivers -v0x1b92350_0 .net "B", 0 0, L_0x1daa590; 1 drivers -v0x1b92420_0 .net "B_", 0 0, L_0x1d9fd20; 1 drivers -v0x1b924c0_0 .net *"_s12", 0 0, L_0x1da1380; 1 drivers -v0x1b925b0_0 .net/2s *"_s14", 0 0, L_0x7f72592da528; 1 drivers -v0x1b92670_0 .net/2s *"_s16", 0 0, L_0x7f72592da570; 1 drivers -v0x1b92750_0 .net *"_s18", 0 0, L_0x1da1580; 1 drivers -v0x1b92830_0 .net *"_s20", 0 0, L_0x1da1640; 1 drivers -v0x1b929a0_0 .net *"_s22", 0 0, L_0x1da17a0; 1 drivers -v0x1b92a80_0 .net *"_s24", 0 0, L_0x1da1c50; 1 drivers -o0x7f7259361d58 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1b92b60_0 name=_s30 -o0x7f7259361d88 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1b92c40_0 name=_s32 -v0x1b92d20_0 .net *"_s8", 0 0, L_0x1da0cd0; 1 drivers -v0x1b92e00_0 .net "carryin", 0 0, L_0x1daa630; 1 drivers -v0x1b92ea0_0 .net "carryout", 0 0, L_0x1da9f40; 1 drivers -v0x1b92f40_0 .net "carryouts", 7 0, L_0x1ebf380; 1 drivers -v0x1b930f0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b93190_0 .net "result", 0 0, L_0x1da55c0; 1 drivers -v0x1b93280_0 .net "results", 7 0, L_0x1da1a20; 1 drivers -v0x1b93390_0 .net "zero", 0 0, L_0x1daa2a0; 1 drivers -LS_0x1da1a20_0_0 .concat8 [ 1 1 1 1], L_0x1da01f0, L_0x1da0820, L_0x1da0cd0, L_0x1da1380; -LS_0x1da1a20_0_4 .concat8 [ 1 1 1 1], L_0x1da1580, L_0x1da1640, L_0x1da17a0, L_0x1da1c50; -L_0x1da1a20 .concat8 [ 4 4 0 0], LS_0x1da1a20_0_0, LS_0x1da1a20_0_4; -LS_0x1ebf380_0_0 .concat [ 1 1 1 1], L_0x1da04a0, L_0x1da0b70, o0x7f7259361d58, L_0x1da11d0; -LS_0x1ebf380_0_4 .concat [ 4 0 0 0], o0x7f7259361d88; -L_0x1ebf380 .concat [ 4 4 0 0], LS_0x1ebf380_0_0, LS_0x1ebf380_0_4; -S_0x1b83d10 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b83a90; +L_0x1233200/d .functor NOT 1, L_0x123db40, C4<0>, C4<0>, C4<0>; +L_0x1233200 .delay 1 (10000,10000,10000) L_0x1233200/d; +L_0x1233470/d .functor NOT 1, L_0x123dd30, C4<0>, C4<0>, C4<0>; +L_0x1233470 .delay 1 (10000,10000,10000) L_0x1233470/d; +L_0x1234470/d .functor XOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; +L_0x1234470 .delay 1 (30000,30000,30000) L_0x1234470/d; +L_0x2b0ab3d05528 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05570 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1234b20/d .functor OR 1, L_0x2b0ab3d05528, L_0x2b0ab3d05570, C4<0>, C4<0>; +L_0x1234b20 .delay 1 (30000,30000,30000) L_0x1234b20/d; +L_0x1234d20/d .functor AND 1, L_0x123db40, L_0x123dd30, C4<1>, C4<1>; +L_0x1234d20 .delay 1 (30000,30000,30000) L_0x1234d20/d; +L_0x1234de0/d .functor NAND 1, L_0x123db40, L_0x123dd30, C4<1>, C4<1>; +L_0x1234de0 .delay 1 (20000,20000,20000) L_0x1234de0/d; +L_0x1234f40/d .functor XOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; +L_0x1234f40 .delay 1 (20000,20000,20000) L_0x1234f40/d; +L_0x12353f0/d .functor OR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; +L_0x12353f0 .delay 1 (30000,30000,30000) L_0x12353f0/d; +L_0x123da40/d .functor NOT 1, L_0x1238d60, C4<0>, C4<0>, C4<0>; +L_0x123da40 .delay 1 (10000,10000,10000) L_0x123da40/d; +v0x1024e60_0 .net "A", 0 0, L_0x123db40; 1 drivers +v0x1024f20_0 .net "A_", 0 0, L_0x1233200; 1 drivers +v0x1024fe0_0 .net "B", 0 0, L_0x123dd30; 1 drivers +v0x10250b0_0 .net "B_", 0 0, L_0x1233470; 1 drivers +v0x1025150_0 .net *"_s12", 0 0, L_0x1234b20; 1 drivers +v0x1025240_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05528; 1 drivers +v0x1025300_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05570; 1 drivers +v0x10253e0_0 .net *"_s18", 0 0, L_0x1234d20; 1 drivers +v0x10254c0_0 .net *"_s20", 0 0, L_0x1234de0; 1 drivers +v0x1025630_0 .net *"_s22", 0 0, L_0x1234f40; 1 drivers +v0x1025710_0 .net *"_s24", 0 0, L_0x12353f0; 1 drivers +o0x2b0ab3cb0d58 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10257f0_0 name=_s30 +o0x2b0ab3cb0d88 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10258d0_0 name=_s32 +v0x10259b0_0 .net *"_s8", 0 0, L_0x1234470; 1 drivers +v0x1025a90_0 .net "carryin", 0 0, L_0x123ddd0; 1 drivers +v0x1025b30_0 .net "carryout", 0 0, L_0x123d6e0; 1 drivers +v0x1025bd0_0 .net "carryouts", 7 0, L_0x1353730; 1 drivers +v0x1025d80_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1025e20_0 .net "result", 0 0, L_0x1238d60; 1 drivers +v0x1025f10_0 .net "results", 7 0, L_0x12351c0; 1 drivers +v0x1026020_0 .net "zero", 0 0, L_0x123da40; 1 drivers +LS_0x12351c0_0_0 .concat8 [ 1 1 1 1], L_0x1233990, L_0x1233fc0, L_0x1234470, L_0x1234b20; +LS_0x12351c0_0_4 .concat8 [ 1 1 1 1], L_0x1234d20, L_0x1234de0, L_0x1234f40, L_0x12353f0; +L_0x12351c0 .concat8 [ 4 4 0 0], LS_0x12351c0_0_0, LS_0x12351c0_0_4; +LS_0x1353730_0_0 .concat [ 1 1 1 1], L_0x1233c40, L_0x1234310, o0x2b0ab3cb0d58, L_0x1234970; +LS_0x1353730_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb0d88; +L_0x1353730 .concat [ 4 4 0 0], LS_0x1353730_0_0, LS_0x1353730_0_4; +S_0x10169a0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1016720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1da04a0/d .functor OR 1, L_0x1d9ff80, L_0x1da0340, C4<0>, C4<0>; -L_0x1da04a0 .delay 1 (30000,30000,30000) L_0x1da04a0/d; -v0x1b84b40_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers -v0x1b84c00_0 .net "b", 0 0, L_0x1daa590; alias, 1 drivers -v0x1b84cd0_0 .net "c1", 0 0, L_0x1d9ff80; 1 drivers -v0x1b84dd0_0 .net "c2", 0 0, L_0x1da0340; 1 drivers -v0x1b84ea0_0 .net "carryin", 0 0, L_0x1daa630; alias, 1 drivers -v0x1b84f90_0 .net "carryout", 0 0, L_0x1da04a0; 1 drivers -v0x1b85030_0 .net "s1", 0 0, L_0x1d9ff10; 1 drivers -v0x1b85120_0 .net "sum", 0 0, L_0x1da01f0; 1 drivers -S_0x1b83f80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b83d10; +L_0x1233c40/d .functor OR 1, L_0x1233720, L_0x1233ae0, C4<0>, C4<0>; +L_0x1233c40 .delay 1 (30000,30000,30000) L_0x1233c40/d; +v0x10177d0_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers +v0x1017890_0 .net "b", 0 0, L_0x123dd30; alias, 1 drivers +v0x1017960_0 .net "c1", 0 0, L_0x1233720; 1 drivers +v0x1017a60_0 .net "c2", 0 0, L_0x1233ae0; 1 drivers +v0x1017b30_0 .net "carryin", 0 0, L_0x123ddd0; alias, 1 drivers +v0x1017c20_0 .net "carryout", 0 0, L_0x1233c40; 1 drivers +v0x1017cc0_0 .net "s1", 0 0, L_0x1233660; 1 drivers +v0x1017db0_0 .net "sum", 0 0, L_0x1233990; 1 drivers +S_0x1016c10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10169a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1d9ff10/d .functor XOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; -L_0x1d9ff10 .delay 1 (30000,30000,30000) L_0x1d9ff10/d; -L_0x1d9ff80/d .functor AND 1, L_0x1daa3a0, L_0x1daa590, C4<1>, C4<1>; -L_0x1d9ff80 .delay 1 (30000,30000,30000) L_0x1d9ff80/d; -v0x1b841e0_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers -v0x1b842c0_0 .net "b", 0 0, L_0x1daa590; alias, 1 drivers -v0x1b84380_0 .net "carryout", 0 0, L_0x1d9ff80; alias, 1 drivers -v0x1b84420_0 .net "sum", 0 0, L_0x1d9ff10; alias, 1 drivers -S_0x1b84560 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b83d10; +L_0x1233660/d .functor XOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; +L_0x1233660 .delay 1 (30000,30000,30000) L_0x1233660/d; +L_0x1233720/d .functor AND 1, L_0x123db40, L_0x123dd30, C4<1>, C4<1>; +L_0x1233720 .delay 1 (30000,30000,30000) L_0x1233720/d; +v0x1016e70_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers +v0x1016f50_0 .net "b", 0 0, L_0x123dd30; alias, 1 drivers +v0x1017010_0 .net "carryout", 0 0, L_0x1233720; alias, 1 drivers +v0x10170b0_0 .net "sum", 0 0, L_0x1233660; alias, 1 drivers +S_0x10171f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10169a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1da01f0/d .functor XOR 1, L_0x1d9ff10, L_0x1daa630, C4<0>, C4<0>; -L_0x1da01f0 .delay 1 (30000,30000,30000) L_0x1da01f0/d; -L_0x1da0340/d .functor AND 1, L_0x1d9ff10, L_0x1daa630, C4<1>, C4<1>; -L_0x1da0340 .delay 1 (30000,30000,30000) L_0x1da0340/d; -v0x1b847c0_0 .net "a", 0 0, L_0x1d9ff10; alias, 1 drivers -v0x1b84860_0 .net "b", 0 0, L_0x1daa630; alias, 1 drivers -v0x1b84900_0 .net "carryout", 0 0, L_0x1da0340; alias, 1 drivers -v0x1b849d0_0 .net "sum", 0 0, L_0x1da01f0; alias, 1 drivers -S_0x1b851f0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b83a90; +L_0x1233990/d .functor XOR 1, L_0x1233660, L_0x123ddd0, C4<0>, C4<0>; +L_0x1233990 .delay 1 (30000,30000,30000) L_0x1233990/d; +L_0x1233ae0/d .functor AND 1, L_0x1233660, L_0x123ddd0, C4<1>, C4<1>; +L_0x1233ae0 .delay 1 (30000,30000,30000) L_0x1233ae0/d; +v0x1017450_0 .net "a", 0 0, L_0x1233660; alias, 1 drivers +v0x10174f0_0 .net "b", 0 0, L_0x123ddd0; alias, 1 drivers +v0x1017590_0 .net "carryout", 0 0, L_0x1233ae0; alias, 1 drivers +v0x1017660_0 .net "sum", 0 0, L_0x1233990; alias, 1 drivers +S_0x1017e80 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1016720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b8a5f0_0 .net "ands", 7 0, L_0x1da7000; 1 drivers -v0x1b8a700_0 .net "in", 7 0, L_0x1ebf380; alias, 1 drivers -v0x1b8a7c0_0 .net "out", 0 0, L_0x1da9f40; alias, 1 drivers -v0x1b8a890_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b85410 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b851f0; +v0x101d270_0 .net "ands", 7 0, L_0x123a7a0; 1 drivers +v0x101d380_0 .net "in", 7 0, L_0x1353730; alias, 1 drivers +v0x101d440_0 .net "out", 0 0, L_0x123d6e0; alias, 1 drivers +v0x101d510_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10180a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1017e80; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b87b40_0 .net "A", 7 0, L_0x1ebf380; alias, 1 drivers -v0x1b87c40_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b87d00_0 .net *"_s0", 0 0, L_0x1da5920; 1 drivers -v0x1b87dc0_0 .net *"_s12", 0 0, L_0x1da6290; 1 drivers -v0x1b87ea0_0 .net *"_s16", 0 0, L_0x1da65f0; 1 drivers -v0x1b87fd0_0 .net *"_s20", 0 0, L_0x1da6900; 1 drivers -v0x1b880b0_0 .net *"_s24", 0 0, L_0x1da6cf0; 1 drivers -v0x1b88190_0 .net *"_s28", 0 0, L_0x1da6c80; 1 drivers -v0x1b88270_0 .net *"_s4", 0 0, L_0x1da5c30; 1 drivers -v0x1b883e0_0 .net *"_s8", 0 0, L_0x1da5f80; 1 drivers -v0x1b884c0_0 .net "out", 7 0, L_0x1da7000; alias, 1 drivers -L_0x1da59e0 .part L_0x1ebf380, 0, 1; -L_0x1da5b40 .part v0x1d6daa0_0, 0, 1; -L_0x1da5cf0 .part L_0x1ebf380, 1, 1; -L_0x1da5ee0 .part v0x1d6daa0_0, 1, 1; -L_0x1da6040 .part L_0x1ebf380, 2, 1; -L_0x1da61a0 .part v0x1d6daa0_0, 2, 1; -L_0x1da6350 .part L_0x1ebf380, 3, 1; -L_0x1da64b0 .part v0x1d6daa0_0, 3, 1; -L_0x1da66b0 .part L_0x1ebf380, 4, 1; -L_0x1da6810 .part v0x1d6daa0_0, 4, 1; -L_0x1da6970 .part L_0x1ebf380, 5, 1; -L_0x1da6be0 .part v0x1d6daa0_0, 5, 1; -L_0x1da6db0 .part L_0x1ebf380, 6, 1; -L_0x1da6f10 .part v0x1d6daa0_0, 6, 1; -LS_0x1da7000_0_0 .concat8 [ 1 1 1 1], L_0x1da5920, L_0x1da5c30, L_0x1da5f80, L_0x1da6290; -LS_0x1da7000_0_4 .concat8 [ 1 1 1 1], L_0x1da65f0, L_0x1da6900, L_0x1da6cf0, L_0x1da6c80; -L_0x1da7000 .concat8 [ 4 4 0 0], LS_0x1da7000_0_0, LS_0x1da7000_0_4; -L_0x1da73c0 .part L_0x1ebf380, 7, 1; -L_0x1da75b0 .part v0x1d6daa0_0, 7, 1; -S_0x1b85670 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b85880 .param/l "i" 0 4 54, +C4<00>; -L_0x1da5920/d .functor AND 1, L_0x1da59e0, L_0x1da5b40, C4<1>, C4<1>; -L_0x1da5920 .delay 1 (30000,30000,30000) L_0x1da5920/d; -v0x1b85960_0 .net *"_s0", 0 0, L_0x1da59e0; 1 drivers -v0x1b85a40_0 .net *"_s1", 0 0, L_0x1da5b40; 1 drivers -S_0x1b85b20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b85d30 .param/l "i" 0 4 54, +C4<01>; -L_0x1da5c30/d .functor AND 1, L_0x1da5cf0, L_0x1da5ee0, C4<1>, C4<1>; -L_0x1da5c30 .delay 1 (30000,30000,30000) L_0x1da5c30/d; -v0x1b85df0_0 .net *"_s0", 0 0, L_0x1da5cf0; 1 drivers -v0x1b85ed0_0 .net *"_s1", 0 0, L_0x1da5ee0; 1 drivers -S_0x1b85fb0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b861c0 .param/l "i" 0 4 54, +C4<010>; -L_0x1da5f80/d .functor AND 1, L_0x1da6040, L_0x1da61a0, C4<1>, C4<1>; -L_0x1da5f80 .delay 1 (30000,30000,30000) L_0x1da5f80/d; -v0x1b86260_0 .net *"_s0", 0 0, L_0x1da6040; 1 drivers -v0x1b86340_0 .net *"_s1", 0 0, L_0x1da61a0; 1 drivers -S_0x1b86420 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b86630 .param/l "i" 0 4 54, +C4<011>; -L_0x1da6290/d .functor AND 1, L_0x1da6350, L_0x1da64b0, C4<1>, C4<1>; -L_0x1da6290 .delay 1 (30000,30000,30000) L_0x1da6290/d; -v0x1b866f0_0 .net *"_s0", 0 0, L_0x1da6350; 1 drivers -v0x1b867d0_0 .net *"_s1", 0 0, L_0x1da64b0; 1 drivers -S_0x1b868b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b86b10 .param/l "i" 0 4 54, +C4<0100>; -L_0x1da65f0/d .functor AND 1, L_0x1da66b0, L_0x1da6810, C4<1>, C4<1>; -L_0x1da65f0 .delay 1 (30000,30000,30000) L_0x1da65f0/d; -v0x1b86bd0_0 .net *"_s0", 0 0, L_0x1da66b0; 1 drivers -v0x1b86cb0_0 .net *"_s1", 0 0, L_0x1da6810; 1 drivers -S_0x1b86d90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b86fa0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1da6900/d .functor AND 1, L_0x1da6970, L_0x1da6be0, C4<1>, C4<1>; -L_0x1da6900 .delay 1 (30000,30000,30000) L_0x1da6900/d; -v0x1b87060_0 .net *"_s0", 0 0, L_0x1da6970; 1 drivers -v0x1b87140_0 .net *"_s1", 0 0, L_0x1da6be0; 1 drivers -S_0x1b87220 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b87430 .param/l "i" 0 4 54, +C4<0110>; -L_0x1da6cf0/d .functor AND 1, L_0x1da6db0, L_0x1da6f10, C4<1>, C4<1>; -L_0x1da6cf0 .delay 1 (30000,30000,30000) L_0x1da6cf0/d; -v0x1b874f0_0 .net *"_s0", 0 0, L_0x1da6db0; 1 drivers -v0x1b875d0_0 .net *"_s1", 0 0, L_0x1da6f10; 1 drivers -S_0x1b876b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b85410; - .timescale -9 -12; -P_0x1b878c0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1da6c80/d .functor AND 1, L_0x1da73c0, L_0x1da75b0, C4<1>, C4<1>; -L_0x1da6c80 .delay 1 (30000,30000,30000) L_0x1da6c80/d; -v0x1b87980_0 .net *"_s0", 0 0, L_0x1da73c0; 1 drivers -v0x1b87a60_0 .net *"_s1", 0 0, L_0x1da75b0; 1 drivers -S_0x1b88620 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b851f0; +v0x101a7d0_0 .net "A", 7 0, L_0x1353730; alias, 1 drivers +v0x101a8d0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x101a990_0 .net *"_s0", 0 0, L_0x12390c0; 1 drivers +v0x101aa50_0 .net *"_s12", 0 0, L_0x1239a30; 1 drivers +v0x101ab30_0 .net *"_s16", 0 0, L_0x1239d90; 1 drivers +v0x101ac60_0 .net *"_s20", 0 0, L_0x123a0a0; 1 drivers +v0x101ad40_0 .net *"_s24", 0 0, L_0x123a490; 1 drivers +v0x101ae20_0 .net *"_s28", 0 0, L_0x123a420; 1 drivers +v0x101af00_0 .net *"_s4", 0 0, L_0x12393d0; 1 drivers +v0x101b070_0 .net *"_s8", 0 0, L_0x1239720; 1 drivers +v0x101b150_0 .net "out", 7 0, L_0x123a7a0; alias, 1 drivers +L_0x1239180 .part L_0x1353730, 0, 1; +L_0x12392e0 .part v0x12010b0_0, 0, 1; +L_0x1239490 .part L_0x1353730, 1, 1; +L_0x1239680 .part v0x12010b0_0, 1, 1; +L_0x12397e0 .part L_0x1353730, 2, 1; +L_0x1239940 .part v0x12010b0_0, 2, 1; +L_0x1239af0 .part L_0x1353730, 3, 1; +L_0x1239c50 .part v0x12010b0_0, 3, 1; +L_0x1239e50 .part L_0x1353730, 4, 1; +L_0x1239fb0 .part v0x12010b0_0, 4, 1; +L_0x123a110 .part L_0x1353730, 5, 1; +L_0x123a380 .part v0x12010b0_0, 5, 1; +L_0x123a550 .part L_0x1353730, 6, 1; +L_0x123a6b0 .part v0x12010b0_0, 6, 1; +LS_0x123a7a0_0_0 .concat8 [ 1 1 1 1], L_0x12390c0, L_0x12393d0, L_0x1239720, L_0x1239a30; +LS_0x123a7a0_0_4 .concat8 [ 1 1 1 1], L_0x1239d90, L_0x123a0a0, L_0x123a490, L_0x123a420; +L_0x123a7a0 .concat8 [ 4 4 0 0], LS_0x123a7a0_0_0, LS_0x123a7a0_0_4; +L_0x123ab60 .part L_0x1353730, 7, 1; +L_0x123ad50 .part v0x12010b0_0, 7, 1; +S_0x1018300 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x1018510 .param/l "i" 0 4 54, +C4<00>; +L_0x12390c0/d .functor AND 1, L_0x1239180, L_0x12392e0, C4<1>, C4<1>; +L_0x12390c0 .delay 1 (30000,30000,30000) L_0x12390c0/d; +v0x10185f0_0 .net *"_s0", 0 0, L_0x1239180; 1 drivers +v0x10186d0_0 .net *"_s1", 0 0, L_0x12392e0; 1 drivers +S_0x10187b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x10189c0 .param/l "i" 0 4 54, +C4<01>; +L_0x12393d0/d .functor AND 1, L_0x1239490, L_0x1239680, C4<1>, C4<1>; +L_0x12393d0 .delay 1 (30000,30000,30000) L_0x12393d0/d; +v0x1018a80_0 .net *"_s0", 0 0, L_0x1239490; 1 drivers +v0x1018b60_0 .net *"_s1", 0 0, L_0x1239680; 1 drivers +S_0x1018c40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x1018e50 .param/l "i" 0 4 54, +C4<010>; +L_0x1239720/d .functor AND 1, L_0x12397e0, L_0x1239940, C4<1>, C4<1>; +L_0x1239720 .delay 1 (30000,30000,30000) L_0x1239720/d; +v0x1018ef0_0 .net *"_s0", 0 0, L_0x12397e0; 1 drivers +v0x1018fd0_0 .net *"_s1", 0 0, L_0x1239940; 1 drivers +S_0x10190b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x10192c0 .param/l "i" 0 4 54, +C4<011>; +L_0x1239a30/d .functor AND 1, L_0x1239af0, L_0x1239c50, C4<1>, C4<1>; +L_0x1239a30 .delay 1 (30000,30000,30000) L_0x1239a30/d; +v0x1019380_0 .net *"_s0", 0 0, L_0x1239af0; 1 drivers +v0x1019460_0 .net *"_s1", 0 0, L_0x1239c50; 1 drivers +S_0x1019540 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x10197a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1239d90/d .functor AND 1, L_0x1239e50, L_0x1239fb0, C4<1>, C4<1>; +L_0x1239d90 .delay 1 (30000,30000,30000) L_0x1239d90/d; +v0x1019860_0 .net *"_s0", 0 0, L_0x1239e50; 1 drivers +v0x1019940_0 .net *"_s1", 0 0, L_0x1239fb0; 1 drivers +S_0x1019a20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x1019c30 .param/l "i" 0 4 54, +C4<0101>; +L_0x123a0a0/d .functor AND 1, L_0x123a110, L_0x123a380, C4<1>, C4<1>; +L_0x123a0a0 .delay 1 (30000,30000,30000) L_0x123a0a0/d; +v0x1019cf0_0 .net *"_s0", 0 0, L_0x123a110; 1 drivers +v0x1019dd0_0 .net *"_s1", 0 0, L_0x123a380; 1 drivers +S_0x1019eb0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x101a0c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x123a490/d .functor AND 1, L_0x123a550, L_0x123a6b0, C4<1>, C4<1>; +L_0x123a490 .delay 1 (30000,30000,30000) L_0x123a490/d; +v0x101a180_0 .net *"_s0", 0 0, L_0x123a550; 1 drivers +v0x101a260_0 .net *"_s1", 0 0, L_0x123a6b0; 1 drivers +S_0x101a340 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10180a0; + .timescale -9 -12; +P_0x101a550 .param/l "i" 0 4 54, +C4<0111>; +L_0x123a420/d .functor AND 1, L_0x123ab60, L_0x123ad50, C4<1>, C4<1>; +L_0x123a420 .delay 1 (30000,30000,30000) L_0x123a420/d; +v0x101a610_0 .net *"_s0", 0 0, L_0x123ab60; 1 drivers +v0x101a6f0_0 .net *"_s1", 0 0, L_0x123ad50; 1 drivers +S_0x101b2b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1017e80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1da9f40/d .functor OR 1, L_0x1daa000, L_0x1daa1b0, C4<0>, C4<0>; -L_0x1da9f40 .delay 1 (30000,30000,30000) L_0x1da9f40/d; -v0x1b8a180_0 .net *"_s10", 0 0, L_0x1daa000; 1 drivers -v0x1b8a260_0 .net *"_s12", 0 0, L_0x1daa1b0; 1 drivers -v0x1b8a340_0 .net "in", 7 0, L_0x1da7000; alias, 1 drivers -v0x1b8a410_0 .net "ors", 1 0, L_0x1da9d60; 1 drivers -v0x1b8a4d0_0 .net "out", 0 0, L_0x1da9f40; alias, 1 drivers -L_0x1cf2800 .part L_0x1da7000, 0, 4; -L_0x1da9d60 .concat8 [ 1 1 0 0], L_0x1cf24f0, L_0x1da9a50; -L_0x1da9ea0 .part L_0x1da7000, 4, 4; -L_0x1daa000 .part L_0x1da9d60, 0, 1; -L_0x1daa1b0 .part L_0x1da9d60, 1, 1; -S_0x1b887e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b88620; +L_0x123d6e0/d .functor OR 1, L_0x123d7a0, L_0x123d950, C4<0>, C4<0>; +L_0x123d6e0 .delay 1 (30000,30000,30000) L_0x123d6e0/d; +v0x101ce00_0 .net *"_s10", 0 0, L_0x123d7a0; 1 drivers +v0x101cee0_0 .net *"_s12", 0 0, L_0x123d950; 1 drivers +v0x101cfc0_0 .net "in", 7 0, L_0x123a7a0; alias, 1 drivers +v0x101d090_0 .net "ors", 1 0, L_0x123d500; 1 drivers +v0x101d150_0 .net "out", 0 0, L_0x123d6e0; alias, 1 drivers +L_0x1185460 .part L_0x123a7a0, 0, 4; +L_0x123d500 .concat8 [ 1 1 0 0], L_0x1185150, L_0x123d1f0; +L_0x123d640 .part L_0x123a7a0, 4, 4; +L_0x123d7a0 .part L_0x123d500, 0, 1; +L_0x123d950 .part L_0x123d500, 1, 1; +S_0x101b470 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x101b2b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1da3540/d .functor OR 1, L_0x1cf1d70, L_0x1cf1ed0, C4<0>, C4<0>; -L_0x1da3540 .delay 1 (30000,30000,30000) L_0x1da3540/d; -L_0x1cf2100/d .functor OR 1, L_0x1cf2210, L_0x1cf2370, C4<0>, C4<0>; -L_0x1cf2100 .delay 1 (30000,30000,30000) L_0x1cf2100/d; -L_0x1cf24f0/d .functor OR 1, L_0x1cf2560, L_0x1cf2710, C4<0>, C4<0>; -L_0x1cf24f0 .delay 1 (30000,30000,30000) L_0x1cf24f0/d; -v0x1b88a30_0 .net *"_s0", 0 0, L_0x1da3540; 1 drivers -v0x1b88b30_0 .net *"_s10", 0 0, L_0x1cf2210; 1 drivers -v0x1b88c10_0 .net *"_s12", 0 0, L_0x1cf2370; 1 drivers -v0x1b88cd0_0 .net *"_s14", 0 0, L_0x1cf2560; 1 drivers -v0x1b88db0_0 .net *"_s16", 0 0, L_0x1cf2710; 1 drivers -v0x1b88ee0_0 .net *"_s3", 0 0, L_0x1cf1d70; 1 drivers -v0x1b88fc0_0 .net *"_s5", 0 0, L_0x1cf1ed0; 1 drivers -v0x1b89080_0 .net *"_s6", 0 0, L_0x1cf2100; 1 drivers -v0x1b89160_0 .net "in", 3 0, L_0x1cf2800; 1 drivers -v0x1b892d0_0 .net "ors", 1 0, L_0x1cf2010; 1 drivers -v0x1b893b0_0 .net "out", 0 0, L_0x1cf24f0; 1 drivers -L_0x1cf1d70 .part L_0x1cf2800, 0, 1; -L_0x1cf1ed0 .part L_0x1cf2800, 1, 1; -L_0x1cf2010 .concat8 [ 1 1 0 0], L_0x1da3540, L_0x1cf2100; -L_0x1cf2210 .part L_0x1cf2800, 2, 1; -L_0x1cf2370 .part L_0x1cf2800, 3, 1; -L_0x1cf2560 .part L_0x1cf2010, 0, 1; -L_0x1cf2710 .part L_0x1cf2010, 1, 1; -S_0x1b894d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b88620; +L_0x1236ce0/d .functor OR 1, L_0x11849d0, L_0x1184b30, C4<0>, C4<0>; +L_0x1236ce0 .delay 1 (30000,30000,30000) L_0x1236ce0/d; +L_0x1184d60/d .functor OR 1, L_0x1184e70, L_0x1184fd0, C4<0>, C4<0>; +L_0x1184d60 .delay 1 (30000,30000,30000) L_0x1184d60/d; +L_0x1185150/d .functor OR 1, L_0x11851c0, L_0x1185370, C4<0>, C4<0>; +L_0x1185150 .delay 1 (30000,30000,30000) L_0x1185150/d; +v0x101b6c0_0 .net *"_s0", 0 0, L_0x1236ce0; 1 drivers +v0x101b7c0_0 .net *"_s10", 0 0, L_0x1184e70; 1 drivers +v0x101b8a0_0 .net *"_s12", 0 0, L_0x1184fd0; 1 drivers +v0x101b960_0 .net *"_s14", 0 0, L_0x11851c0; 1 drivers +v0x101ba40_0 .net *"_s16", 0 0, L_0x1185370; 1 drivers +v0x101bb70_0 .net *"_s3", 0 0, L_0x11849d0; 1 drivers +v0x101bc50_0 .net *"_s5", 0 0, L_0x1184b30; 1 drivers +v0x101bd30_0 .net *"_s6", 0 0, L_0x1184d60; 1 drivers +v0x101be10_0 .net "in", 3 0, L_0x1185460; 1 drivers +v0x101bf80_0 .net "ors", 1 0, L_0x1184c70; 1 drivers +v0x101c060_0 .net "out", 0 0, L_0x1185150; 1 drivers +L_0x11849d0 .part L_0x1185460, 0, 1; +L_0x1184b30 .part L_0x1185460, 1, 1; +L_0x1184c70 .concat8 [ 1 1 0 0], L_0x1236ce0, L_0x1184d60; +L_0x1184e70 .part L_0x1185460, 2, 1; +L_0x1184fd0 .part L_0x1185460, 3, 1; +L_0x11851c0 .part L_0x1184c70, 0, 1; +L_0x1185370 .part L_0x1184c70, 1, 1; +S_0x101c180 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x101b2b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1cf2930/d .functor OR 1, L_0x1cf29a0, L_0x1cf2b00, C4<0>, C4<0>; -L_0x1cf2930 .delay 1 (30000,30000,30000) L_0x1cf2930/d; -L_0x1da96b0/d .functor OR 1, L_0x1da9770, L_0x1da98d0, C4<0>, C4<0>; -L_0x1da96b0 .delay 1 (30000,30000,30000) L_0x1da96b0/d; -L_0x1da9a50/d .functor OR 1, L_0x1da9ac0, L_0x1da9c70, C4<0>, C4<0>; -L_0x1da9a50 .delay 1 (30000,30000,30000) L_0x1da9a50/d; -v0x1b89690_0 .net *"_s0", 0 0, L_0x1cf2930; 1 drivers -v0x1b89790_0 .net *"_s10", 0 0, L_0x1da9770; 1 drivers -v0x1b89870_0 .net *"_s12", 0 0, L_0x1da98d0; 1 drivers -v0x1b89960_0 .net *"_s14", 0 0, L_0x1da9ac0; 1 drivers -v0x1b89a40_0 .net *"_s16", 0 0, L_0x1da9c70; 1 drivers -v0x1b89b70_0 .net *"_s3", 0 0, L_0x1cf29a0; 1 drivers -v0x1b89c50_0 .net *"_s5", 0 0, L_0x1cf2b00; 1 drivers -v0x1b89d30_0 .net *"_s6", 0 0, L_0x1da96b0; 1 drivers -v0x1b89e10_0 .net "in", 3 0, L_0x1da9ea0; 1 drivers -v0x1b89f80_0 .net "ors", 1 0, L_0x1cf2c40; 1 drivers -v0x1b8a060_0 .net "out", 0 0, L_0x1da9a50; 1 drivers -L_0x1cf29a0 .part L_0x1da9ea0, 0, 1; -L_0x1cf2b00 .part L_0x1da9ea0, 1, 1; -L_0x1cf2c40 .concat8 [ 1 1 0 0], L_0x1cf2930, L_0x1da96b0; -L_0x1da9770 .part L_0x1da9ea0, 2, 1; -L_0x1da98d0 .part L_0x1da9ea0, 3, 1; -L_0x1da9ac0 .part L_0x1cf2c40, 0, 1; -L_0x1da9c70 .part L_0x1cf2c40, 1, 1; -S_0x1b8a970 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b83a90; +L_0x1185590/d .functor OR 1, L_0x1185600, L_0x1185760, C4<0>, C4<0>; +L_0x1185590 .delay 1 (30000,30000,30000) L_0x1185590/d; +L_0x123ce50/d .functor OR 1, L_0x123cf10, L_0x123d070, C4<0>, C4<0>; +L_0x123ce50 .delay 1 (30000,30000,30000) L_0x123ce50/d; +L_0x123d1f0/d .functor OR 1, L_0x123d260, L_0x123d410, C4<0>, C4<0>; +L_0x123d1f0 .delay 1 (30000,30000,30000) L_0x123d1f0/d; +v0x101c340_0 .net *"_s0", 0 0, L_0x1185590; 1 drivers +v0x101c440_0 .net *"_s10", 0 0, L_0x123cf10; 1 drivers +v0x101c520_0 .net *"_s12", 0 0, L_0x123d070; 1 drivers +v0x101c5e0_0 .net *"_s14", 0 0, L_0x123d260; 1 drivers +v0x101c6c0_0 .net *"_s16", 0 0, L_0x123d410; 1 drivers +v0x101c7f0_0 .net *"_s3", 0 0, L_0x1185600; 1 drivers +v0x101c8d0_0 .net *"_s5", 0 0, L_0x1185760; 1 drivers +v0x101c9b0_0 .net *"_s6", 0 0, L_0x123ce50; 1 drivers +v0x101ca90_0 .net "in", 3 0, L_0x123d640; 1 drivers +v0x101cc00_0 .net "ors", 1 0, L_0x11858a0; 1 drivers +v0x101cce0_0 .net "out", 0 0, L_0x123d1f0; 1 drivers +L_0x1185600 .part L_0x123d640, 0, 1; +L_0x1185760 .part L_0x123d640, 1, 1; +L_0x11858a0 .concat8 [ 1 1 0 0], L_0x1185590, L_0x123ce50; +L_0x123cf10 .part L_0x123d640, 2, 1; +L_0x123d070 .part L_0x123d640, 3, 1; +L_0x123d260 .part L_0x11858a0, 0, 1; +L_0x123d410 .part L_0x11858a0, 1, 1; +S_0x101d5f0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1016720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b8fda0_0 .net "ands", 7 0, L_0x1da35c0; 1 drivers -v0x1b8feb0_0 .net "in", 7 0, L_0x1da1a20; alias, 1 drivers -v0x1b8ff70_0 .net "out", 0 0, L_0x1da55c0; alias, 1 drivers -v0x1b90040_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b8abc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b8a970; +v0x1022a30_0 .net "ands", 7 0, L_0x1236d60; 1 drivers +v0x1022b40_0 .net "in", 7 0, L_0x12351c0; alias, 1 drivers +v0x1022c00_0 .net "out", 0 0, L_0x1238d60; alias, 1 drivers +v0x1022cd0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x101d840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x101d5f0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b8d300_0 .net "A", 7 0, L_0x1da1a20; alias, 1 drivers -v0x1b8d400_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b8d4c0_0 .net *"_s0", 0 0, L_0x1da1db0; 1 drivers -v0x1b8d580_0 .net *"_s12", 0 0, L_0x1da2770; 1 drivers -v0x1b8d660_0 .net *"_s16", 0 0, L_0x1da2ad0; 1 drivers -v0x1b8d790_0 .net *"_s20", 0 0, L_0x1da2f00; 1 drivers -v0x1b8d870_0 .net *"_s24", 0 0, L_0x1da3230; 1 drivers -v0x1b8d950_0 .net *"_s28", 0 0, L_0x1da31c0; 1 drivers -v0x1b8da30_0 .net *"_s4", 0 0, L_0x1da2150; 1 drivers -v0x1b8dba0_0 .net *"_s8", 0 0, L_0x1da2460; 1 drivers -v0x1b8dc80_0 .net "out", 7 0, L_0x1da35c0; alias, 1 drivers -L_0x1da1ec0 .part L_0x1da1a20, 0, 1; -L_0x1da20b0 .part v0x1d6daa0_0, 0, 1; -L_0x1da2210 .part L_0x1da1a20, 1, 1; -L_0x1da2370 .part v0x1d6daa0_0, 1, 1; -L_0x1da2520 .part L_0x1da1a20, 2, 1; -L_0x1da2680 .part v0x1d6daa0_0, 2, 1; -L_0x1da2830 .part L_0x1da1a20, 3, 1; -L_0x1da2990 .part v0x1d6daa0_0, 3, 1; -L_0x1da2b90 .part L_0x1da1a20, 4, 1; -L_0x1da2e00 .part v0x1d6daa0_0, 4, 1; -L_0x1da2f70 .part L_0x1da1a20, 5, 1; -L_0x1da30d0 .part v0x1d6daa0_0, 5, 1; -L_0x1da32f0 .part L_0x1da1a20, 6, 1; -L_0x1da3450 .part v0x1d6daa0_0, 6, 1; -LS_0x1da35c0_0_0 .concat8 [ 1 1 1 1], L_0x1da1db0, L_0x1da2150, L_0x1da2460, L_0x1da2770; -LS_0x1da35c0_0_4 .concat8 [ 1 1 1 1], L_0x1da2ad0, L_0x1da2f00, L_0x1da3230, L_0x1da31c0; -L_0x1da35c0 .concat8 [ 4 4 0 0], LS_0x1da35c0_0_0, LS_0x1da35c0_0_4; -L_0x1da3980 .part L_0x1da1a20, 7, 1; -L_0x1da3b70 .part v0x1d6daa0_0, 7, 1; -S_0x1b8ae00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8b010 .param/l "i" 0 4 54, +C4<00>; -L_0x1da1db0/d .functor AND 1, L_0x1da1ec0, L_0x1da20b0, C4<1>, C4<1>; -L_0x1da1db0 .delay 1 (30000,30000,30000) L_0x1da1db0/d; -v0x1b8b0f0_0 .net *"_s0", 0 0, L_0x1da1ec0; 1 drivers -v0x1b8b1d0_0 .net *"_s1", 0 0, L_0x1da20b0; 1 drivers -S_0x1b8b2b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8b4c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1da2150/d .functor AND 1, L_0x1da2210, L_0x1da2370, C4<1>, C4<1>; -L_0x1da2150 .delay 1 (30000,30000,30000) L_0x1da2150/d; -v0x1b8b580_0 .net *"_s0", 0 0, L_0x1da2210; 1 drivers -v0x1b8b660_0 .net *"_s1", 0 0, L_0x1da2370; 1 drivers -S_0x1b8b740 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8b980 .param/l "i" 0 4 54, +C4<010>; -L_0x1da2460/d .functor AND 1, L_0x1da2520, L_0x1da2680, C4<1>, C4<1>; -L_0x1da2460 .delay 1 (30000,30000,30000) L_0x1da2460/d; -v0x1b8ba20_0 .net *"_s0", 0 0, L_0x1da2520; 1 drivers -v0x1b8bb00_0 .net *"_s1", 0 0, L_0x1da2680; 1 drivers -S_0x1b8bbe0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8bdf0 .param/l "i" 0 4 54, +C4<011>; -L_0x1da2770/d .functor AND 1, L_0x1da2830, L_0x1da2990, C4<1>, C4<1>; -L_0x1da2770 .delay 1 (30000,30000,30000) L_0x1da2770/d; -v0x1b8beb0_0 .net *"_s0", 0 0, L_0x1da2830; 1 drivers -v0x1b8bf90_0 .net *"_s1", 0 0, L_0x1da2990; 1 drivers -S_0x1b8c070 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8c2d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1da2ad0/d .functor AND 1, L_0x1da2b90, L_0x1da2e00, C4<1>, C4<1>; -L_0x1da2ad0 .delay 1 (30000,30000,30000) L_0x1da2ad0/d; -v0x1b8c390_0 .net *"_s0", 0 0, L_0x1da2b90; 1 drivers -v0x1b8c470_0 .net *"_s1", 0 0, L_0x1da2e00; 1 drivers -S_0x1b8c550 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8c760 .param/l "i" 0 4 54, +C4<0101>; -L_0x1da2f00/d .functor AND 1, L_0x1da2f70, L_0x1da30d0, C4<1>, C4<1>; -L_0x1da2f00 .delay 1 (30000,30000,30000) L_0x1da2f00/d; -v0x1b8c820_0 .net *"_s0", 0 0, L_0x1da2f70; 1 drivers -v0x1b8c900_0 .net *"_s1", 0 0, L_0x1da30d0; 1 drivers -S_0x1b8c9e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8cbf0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1da3230/d .functor AND 1, L_0x1da32f0, L_0x1da3450, C4<1>, C4<1>; -L_0x1da3230 .delay 1 (30000,30000,30000) L_0x1da3230/d; -v0x1b8ccb0_0 .net *"_s0", 0 0, L_0x1da32f0; 1 drivers -v0x1b8cd90_0 .net *"_s1", 0 0, L_0x1da3450; 1 drivers -S_0x1b8ce70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b8abc0; - .timescale -9 -12; -P_0x1b8d080 .param/l "i" 0 4 54, +C4<0111>; -L_0x1da31c0/d .functor AND 1, L_0x1da3980, L_0x1da3b70, C4<1>, C4<1>; -L_0x1da31c0 .delay 1 (30000,30000,30000) L_0x1da31c0/d; -v0x1b8d140_0 .net *"_s0", 0 0, L_0x1da3980; 1 drivers -v0x1b8d220_0 .net *"_s1", 0 0, L_0x1da3b70; 1 drivers -S_0x1b8dde0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b8a970; +v0x101ff80_0 .net "A", 7 0, L_0x12351c0; alias, 1 drivers +v0x1020080_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1020140_0 .net *"_s0", 0 0, L_0x1235550; 1 drivers +v0x1020200_0 .net *"_s12", 0 0, L_0x1235f10; 1 drivers +v0x10202e0_0 .net *"_s16", 0 0, L_0x1236270; 1 drivers +v0x1020410_0 .net *"_s20", 0 0, L_0x12366a0; 1 drivers +v0x10204f0_0 .net *"_s24", 0 0, L_0x12369d0; 1 drivers +v0x10205d0_0 .net *"_s28", 0 0, L_0x1236960; 1 drivers +v0x10206b0_0 .net *"_s4", 0 0, L_0x12358f0; 1 drivers +v0x1020820_0 .net *"_s8", 0 0, L_0x1235c00; 1 drivers +v0x1020900_0 .net "out", 7 0, L_0x1236d60; alias, 1 drivers +L_0x1235660 .part L_0x12351c0, 0, 1; +L_0x1235850 .part v0x12010b0_0, 0, 1; +L_0x12359b0 .part L_0x12351c0, 1, 1; +L_0x1235b10 .part v0x12010b0_0, 1, 1; +L_0x1235cc0 .part L_0x12351c0, 2, 1; +L_0x1235e20 .part v0x12010b0_0, 2, 1; +L_0x1235fd0 .part L_0x12351c0, 3, 1; +L_0x1236130 .part v0x12010b0_0, 3, 1; +L_0x1236330 .part L_0x12351c0, 4, 1; +L_0x12365a0 .part v0x12010b0_0, 4, 1; +L_0x1236710 .part L_0x12351c0, 5, 1; +L_0x1236870 .part v0x12010b0_0, 5, 1; +L_0x1236a90 .part L_0x12351c0, 6, 1; +L_0x1236bf0 .part v0x12010b0_0, 6, 1; +LS_0x1236d60_0_0 .concat8 [ 1 1 1 1], L_0x1235550, L_0x12358f0, L_0x1235c00, L_0x1235f10; +LS_0x1236d60_0_4 .concat8 [ 1 1 1 1], L_0x1236270, L_0x12366a0, L_0x12369d0, L_0x1236960; +L_0x1236d60 .concat8 [ 4 4 0 0], LS_0x1236d60_0_0, LS_0x1236d60_0_4; +L_0x1237120 .part L_0x12351c0, 7, 1; +L_0x1237310 .part v0x12010b0_0, 7, 1; +S_0x101da80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101dc90 .param/l "i" 0 4 54, +C4<00>; +L_0x1235550/d .functor AND 1, L_0x1235660, L_0x1235850, C4<1>, C4<1>; +L_0x1235550 .delay 1 (30000,30000,30000) L_0x1235550/d; +v0x101dd70_0 .net *"_s0", 0 0, L_0x1235660; 1 drivers +v0x101de50_0 .net *"_s1", 0 0, L_0x1235850; 1 drivers +S_0x101df30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101e140 .param/l "i" 0 4 54, +C4<01>; +L_0x12358f0/d .functor AND 1, L_0x12359b0, L_0x1235b10, C4<1>, C4<1>; +L_0x12358f0 .delay 1 (30000,30000,30000) L_0x12358f0/d; +v0x101e200_0 .net *"_s0", 0 0, L_0x12359b0; 1 drivers +v0x101e2e0_0 .net *"_s1", 0 0, L_0x1235b10; 1 drivers +S_0x101e3c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101e600 .param/l "i" 0 4 54, +C4<010>; +L_0x1235c00/d .functor AND 1, L_0x1235cc0, L_0x1235e20, C4<1>, C4<1>; +L_0x1235c00 .delay 1 (30000,30000,30000) L_0x1235c00/d; +v0x101e6a0_0 .net *"_s0", 0 0, L_0x1235cc0; 1 drivers +v0x101e780_0 .net *"_s1", 0 0, L_0x1235e20; 1 drivers +S_0x101e860 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101ea70 .param/l "i" 0 4 54, +C4<011>; +L_0x1235f10/d .functor AND 1, L_0x1235fd0, L_0x1236130, C4<1>, C4<1>; +L_0x1235f10 .delay 1 (30000,30000,30000) L_0x1235f10/d; +v0x101eb30_0 .net *"_s0", 0 0, L_0x1235fd0; 1 drivers +v0x101ec10_0 .net *"_s1", 0 0, L_0x1236130; 1 drivers +S_0x101ecf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101ef50 .param/l "i" 0 4 54, +C4<0100>; +L_0x1236270/d .functor AND 1, L_0x1236330, L_0x12365a0, C4<1>, C4<1>; +L_0x1236270 .delay 1 (30000,30000,30000) L_0x1236270/d; +v0x101f010_0 .net *"_s0", 0 0, L_0x1236330; 1 drivers +v0x101f0f0_0 .net *"_s1", 0 0, L_0x12365a0; 1 drivers +S_0x101f1d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101f3e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12366a0/d .functor AND 1, L_0x1236710, L_0x1236870, C4<1>, C4<1>; +L_0x12366a0 .delay 1 (30000,30000,30000) L_0x12366a0/d; +v0x101f4a0_0 .net *"_s0", 0 0, L_0x1236710; 1 drivers +v0x101f580_0 .net *"_s1", 0 0, L_0x1236870; 1 drivers +S_0x101f660 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101f870 .param/l "i" 0 4 54, +C4<0110>; +L_0x12369d0/d .functor AND 1, L_0x1236a90, L_0x1236bf0, C4<1>, C4<1>; +L_0x12369d0 .delay 1 (30000,30000,30000) L_0x12369d0/d; +v0x101f930_0 .net *"_s0", 0 0, L_0x1236a90; 1 drivers +v0x101fa10_0 .net *"_s1", 0 0, L_0x1236bf0; 1 drivers +S_0x101faf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x101d840; + .timescale -9 -12; +P_0x101fd00 .param/l "i" 0 4 54, +C4<0111>; +L_0x1236960/d .functor AND 1, L_0x1237120, L_0x1237310, C4<1>, C4<1>; +L_0x1236960 .delay 1 (30000,30000,30000) L_0x1236960/d; +v0x101fdc0_0 .net *"_s0", 0 0, L_0x1237120; 1 drivers +v0x101fea0_0 .net *"_s1", 0 0, L_0x1237310; 1 drivers +S_0x1020a60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x101d5f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1da55c0/d .functor OR 1, L_0x1da5680, L_0x1da5830, C4<0>, C4<0>; -L_0x1da55c0 .delay 1 (30000,30000,30000) L_0x1da55c0/d; -v0x1b8f930_0 .net *"_s10", 0 0, L_0x1da5680; 1 drivers -v0x1b8fa10_0 .net *"_s12", 0 0, L_0x1da5830; 1 drivers -v0x1b8faf0_0 .net "in", 7 0, L_0x1da35c0; alias, 1 drivers -v0x1b8fbc0_0 .net "ors", 1 0, L_0x1da53e0; 1 drivers -v0x1b8fc80_0 .net "out", 0 0, L_0x1da55c0; alias, 1 drivers -L_0x1da47b0 .part L_0x1da35c0, 0, 4; -L_0x1da53e0 .concat8 [ 1 1 0 0], L_0x1da44a0, L_0x1da50d0; -L_0x1da5520 .part L_0x1da35c0, 4, 4; -L_0x1da5680 .part L_0x1da53e0, 0, 1; -L_0x1da5830 .part L_0x1da53e0, 1, 1; -S_0x1b8dfa0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b8dde0; +L_0x1238d60/d .functor OR 1, L_0x1238e20, L_0x1238fd0, C4<0>, C4<0>; +L_0x1238d60 .delay 1 (30000,30000,30000) L_0x1238d60/d; +v0x1022590_0 .net *"_s10", 0 0, L_0x1238e20; 1 drivers +v0x1022670_0 .net *"_s12", 0 0, L_0x1238fd0; 1 drivers +v0x1022750_0 .net "in", 7 0, L_0x1236d60; alias, 1 drivers +v0x1022850_0 .net "ors", 1 0, L_0x1238b80; 1 drivers +v0x1022910_0 .net "out", 0 0, L_0x1238d60; alias, 1 drivers +L_0x1237f50 .part L_0x1236d60, 0, 4; +L_0x1238b80 .concat8 [ 1 1 0 0], L_0x1237c40, L_0x1238870; +L_0x1238cc0 .part L_0x1236d60, 4, 4; +L_0x1238e20 .part L_0x1238b80, 0, 1; +L_0x1238fd0 .part L_0x1238b80, 1, 1; +S_0x1020c20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1020a60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1da3c60/d .functor OR 1, L_0x1da3d20, L_0x1da3e80, C4<0>, C4<0>; -L_0x1da3c60 .delay 1 (30000,30000,30000) L_0x1da3c60/d; -L_0x1da40b0/d .functor OR 1, L_0x1da41c0, L_0x1da4320, C4<0>, C4<0>; -L_0x1da40b0 .delay 1 (30000,30000,30000) L_0x1da40b0/d; -L_0x1da44a0/d .functor OR 1, L_0x1da4510, L_0x1da46c0, C4<0>, C4<0>; -L_0x1da44a0 .delay 1 (30000,30000,30000) L_0x1da44a0/d; -v0x1b8e1f0_0 .net *"_s0", 0 0, L_0x1da3c60; 1 drivers -v0x1b8e2f0_0 .net *"_s10", 0 0, L_0x1da41c0; 1 drivers -v0x1b8e3d0_0 .net *"_s12", 0 0, L_0x1da4320; 1 drivers -v0x1b8e490_0 .net *"_s14", 0 0, L_0x1da4510; 1 drivers -v0x1b8e570_0 .net *"_s16", 0 0, L_0x1da46c0; 1 drivers -v0x1b8e6a0_0 .net *"_s3", 0 0, L_0x1da3d20; 1 drivers -v0x1b8e780_0 .net *"_s5", 0 0, L_0x1da3e80; 1 drivers -v0x1b8e860_0 .net *"_s6", 0 0, L_0x1da40b0; 1 drivers -v0x1b8e940_0 .net "in", 3 0, L_0x1da47b0; 1 drivers -v0x1b8eab0_0 .net "ors", 1 0, L_0x1da3fc0; 1 drivers -v0x1b8eb90_0 .net "out", 0 0, L_0x1da44a0; 1 drivers -L_0x1da3d20 .part L_0x1da47b0, 0, 1; -L_0x1da3e80 .part L_0x1da47b0, 1, 1; -L_0x1da3fc0 .concat8 [ 1 1 0 0], L_0x1da3c60, L_0x1da40b0; -L_0x1da41c0 .part L_0x1da47b0, 2, 1; -L_0x1da4320 .part L_0x1da47b0, 3, 1; -L_0x1da4510 .part L_0x1da3fc0, 0, 1; -L_0x1da46c0 .part L_0x1da3fc0, 1, 1; -S_0x1b8ecb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b8dde0; +L_0x1237400/d .functor OR 1, L_0x12374c0, L_0x1237620, C4<0>, C4<0>; +L_0x1237400 .delay 1 (30000,30000,30000) L_0x1237400/d; +L_0x1237850/d .functor OR 1, L_0x1237960, L_0x1237ac0, C4<0>, C4<0>; +L_0x1237850 .delay 1 (30000,30000,30000) L_0x1237850/d; +L_0x1237c40/d .functor OR 1, L_0x1237cb0, L_0x1237e60, C4<0>, C4<0>; +L_0x1237c40 .delay 1 (30000,30000,30000) L_0x1237c40/d; +v0x1020e70_0 .net *"_s0", 0 0, L_0x1237400; 1 drivers +v0x1020f70_0 .net *"_s10", 0 0, L_0x1237960; 1 drivers +v0x1021050_0 .net *"_s12", 0 0, L_0x1237ac0; 1 drivers +v0x1021110_0 .net *"_s14", 0 0, L_0x1237cb0; 1 drivers +v0x10211f0_0 .net *"_s16", 0 0, L_0x1237e60; 1 drivers +v0x1021320_0 .net *"_s3", 0 0, L_0x12374c0; 1 drivers +v0x1021400_0 .net *"_s5", 0 0, L_0x1237620; 1 drivers +v0x10214e0_0 .net *"_s6", 0 0, L_0x1237850; 1 drivers +v0x10215c0_0 .net "in", 3 0, L_0x1237f50; 1 drivers +v0x1021730_0 .net "ors", 1 0, L_0x1237760; 1 drivers +v0x1021810_0 .net "out", 0 0, L_0x1237c40; 1 drivers +L_0x12374c0 .part L_0x1237f50, 0, 1; +L_0x1237620 .part L_0x1237f50, 1, 1; +L_0x1237760 .concat8 [ 1 1 0 0], L_0x1237400, L_0x1237850; +L_0x1237960 .part L_0x1237f50, 2, 1; +L_0x1237ac0 .part L_0x1237f50, 3, 1; +L_0x1237cb0 .part L_0x1237760, 0, 1; +L_0x1237e60 .part L_0x1237760, 1, 1; +S_0x1021930 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1020a60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1da48e0/d .functor OR 1, L_0x1da4950, L_0x1da4ab0, C4<0>, C4<0>; -L_0x1da48e0 .delay 1 (30000,30000,30000) L_0x1da48e0/d; -L_0x1da4ce0/d .functor OR 1, L_0x1da4df0, L_0x1da4f50, C4<0>, C4<0>; -L_0x1da4ce0 .delay 1 (30000,30000,30000) L_0x1da4ce0/d; -L_0x1da50d0/d .functor OR 1, L_0x1da5140, L_0x1da52f0, C4<0>, C4<0>; -L_0x1da50d0 .delay 1 (30000,30000,30000) L_0x1da50d0/d; -v0x1b8ee70_0 .net *"_s0", 0 0, L_0x1da48e0; 1 drivers -v0x1b8ef70_0 .net *"_s10", 0 0, L_0x1da4df0; 1 drivers -v0x1b8f050_0 .net *"_s12", 0 0, L_0x1da4f50; 1 drivers -v0x1b8f110_0 .net *"_s14", 0 0, L_0x1da5140; 1 drivers -v0x1b8f1f0_0 .net *"_s16", 0 0, L_0x1da52f0; 1 drivers -v0x1b8f320_0 .net *"_s3", 0 0, L_0x1da4950; 1 drivers -v0x1b8f400_0 .net *"_s5", 0 0, L_0x1da4ab0; 1 drivers -v0x1b8f4e0_0 .net *"_s6", 0 0, L_0x1da4ce0; 1 drivers -v0x1b8f5c0_0 .net "in", 3 0, L_0x1da5520; 1 drivers -v0x1b8f730_0 .net "ors", 1 0, L_0x1da4bf0; 1 drivers -v0x1b8f810_0 .net "out", 0 0, L_0x1da50d0; 1 drivers -L_0x1da4950 .part L_0x1da5520, 0, 1; -L_0x1da4ab0 .part L_0x1da5520, 1, 1; -L_0x1da4bf0 .concat8 [ 1 1 0 0], L_0x1da48e0, L_0x1da4ce0; -L_0x1da4df0 .part L_0x1da5520, 2, 1; -L_0x1da4f50 .part L_0x1da5520, 3, 1; -L_0x1da5140 .part L_0x1da4bf0, 0, 1; -L_0x1da52f0 .part L_0x1da4bf0, 1, 1; -S_0x1b90120 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b83a90; +L_0x1238080/d .functor OR 1, L_0x12380f0, L_0x1238250, C4<0>, C4<0>; +L_0x1238080 .delay 1 (30000,30000,30000) L_0x1238080/d; +L_0x1238480/d .functor OR 1, L_0x1238590, L_0x12386f0, C4<0>, C4<0>; +L_0x1238480 .delay 1 (30000,30000,30000) L_0x1238480/d; +L_0x1238870/d .functor OR 1, L_0x12388e0, L_0x1238a90, C4<0>, C4<0>; +L_0x1238870 .delay 1 (30000,30000,30000) L_0x1238870/d; +v0x1021af0_0 .net *"_s0", 0 0, L_0x1238080; 1 drivers +v0x1021bf0_0 .net *"_s10", 0 0, L_0x1238590; 1 drivers +v0x1021cd0_0 .net *"_s12", 0 0, L_0x12386f0; 1 drivers +v0x1021d90_0 .net *"_s14", 0 0, L_0x12388e0; 1 drivers +v0x1021e70_0 .net *"_s16", 0 0, L_0x1238a90; 1 drivers +v0x1021fa0_0 .net *"_s3", 0 0, L_0x12380f0; 1 drivers +v0x1022060_0 .net *"_s5", 0 0, L_0x1238250; 1 drivers +v0x1022140_0 .net *"_s6", 0 0, L_0x1238480; 1 drivers +v0x1022220_0 .net "in", 3 0, L_0x1238cc0; 1 drivers +v0x1022390_0 .net "ors", 1 0, L_0x1238390; 1 drivers +v0x1022470_0 .net "out", 0 0, L_0x1238870; 1 drivers +L_0x12380f0 .part L_0x1238cc0, 0, 1; +L_0x1238250 .part L_0x1238cc0, 1, 1; +L_0x1238390 .concat8 [ 1 1 0 0], L_0x1238080, L_0x1238480; +L_0x1238590 .part L_0x1238cc0, 2, 1; +L_0x12386f0 .part L_0x1238cc0, 3, 1; +L_0x12388e0 .part L_0x1238390, 0, 1; +L_0x1238a90 .part L_0x1238390, 1, 1; +S_0x1022db0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1016720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -3340,80 +3350,80 @@ S_0x1b90120 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b83a90; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1da0d90/d .functor XNOR 1, L_0x1daa3a0, L_0x1daa590, C4<0>, C4<0>; -L_0x1da0d90 .delay 1 (20000,20000,20000) L_0x1da0d90/d; -L_0x1da1000/d .functor AND 1, L_0x1daa3a0, L_0x1d9fd20, C4<1>, C4<1>; -L_0x1da1000 .delay 1 (30000,30000,30000) L_0x1da1000/d; -L_0x1da1070/d .functor AND 1, L_0x1da0d90, L_0x1daa630, C4<1>, C4<1>; -L_0x1da1070 .delay 1 (30000,30000,30000) L_0x1da1070/d; -L_0x1da11d0/d .functor OR 1, L_0x1da1070, L_0x1da1000, C4<0>, C4<0>; -L_0x1da11d0 .delay 1 (30000,30000,30000) L_0x1da11d0/d; -v0x1b903d0_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers -v0x1b904c0_0 .net "a_", 0 0, L_0x1d9fb50; alias, 1 drivers -v0x1b90580_0 .net "b", 0 0, L_0x1daa590; alias, 1 drivers -v0x1b90670_0 .net "b_", 0 0, L_0x1d9fd20; alias, 1 drivers -v0x1b90710_0 .net "carryin", 0 0, L_0x1daa630; alias, 1 drivers -v0x1b90850_0 .net "eq", 0 0, L_0x1da0d90; 1 drivers -v0x1b90910_0 .net "lt", 0 0, L_0x1da1000; 1 drivers -v0x1b909d0_0 .net "out", 0 0, L_0x1da11d0; 1 drivers -v0x1b90a90_0 .net "w0", 0 0, L_0x1da1070; 1 drivers -S_0x1b90ce0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b83a90; +L_0x1234530/d .functor XNOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; +L_0x1234530 .delay 1 (20000,20000,20000) L_0x1234530/d; +L_0x12347a0/d .functor AND 1, L_0x123db40, L_0x1233470, C4<1>, C4<1>; +L_0x12347a0 .delay 1 (30000,30000,30000) L_0x12347a0/d; +L_0x1234810/d .functor AND 1, L_0x1234530, L_0x123ddd0, C4<1>, C4<1>; +L_0x1234810 .delay 1 (30000,30000,30000) L_0x1234810/d; +L_0x1234970/d .functor OR 1, L_0x1234810, L_0x12347a0, C4<0>, C4<0>; +L_0x1234970 .delay 1 (30000,30000,30000) L_0x1234970/d; +v0x1023060_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers +v0x1023150_0 .net "a_", 0 0, L_0x1233200; alias, 1 drivers +v0x1023210_0 .net "b", 0 0, L_0x123dd30; alias, 1 drivers +v0x1023300_0 .net "b_", 0 0, L_0x1233470; alias, 1 drivers +v0x10233a0_0 .net "carryin", 0 0, L_0x123ddd0; alias, 1 drivers +v0x10234e0_0 .net "eq", 0 0, L_0x1234530; 1 drivers +v0x10235a0_0 .net "lt", 0 0, L_0x12347a0; 1 drivers +v0x1023660_0 .net "out", 0 0, L_0x1234970; 1 drivers +v0x1023720_0 .net "w0", 0 0, L_0x1234810; 1 drivers +S_0x1023970 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1016720; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1da0b70/d .functor OR 1, L_0x1da06c0, L_0x1b91f40, C4<0>, C4<0>; -L_0x1da0b70 .delay 1 (30000,30000,30000) L_0x1da0b70/d; -v0x1b91ad0_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers -v0x1b91c20_0 .net "b", 0 0, L_0x1d9fd20; alias, 1 drivers -v0x1b91ce0_0 .net "c1", 0 0, L_0x1da06c0; 1 drivers -v0x1b91d80_0 .net "c2", 0 0, L_0x1b91f40; 1 drivers -v0x1b91e50_0 .net "carryin", 0 0, L_0x1daa630; alias, 1 drivers -v0x1b91fd0_0 .net "carryout", 0 0, L_0x1da0b70; 1 drivers -v0x1b92070_0 .net "s1", 0 0, L_0x1da0600; 1 drivers -v0x1b92110_0 .net "sum", 0 0, L_0x1da0820; 1 drivers -S_0x1b90f30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b90ce0; +L_0x1234310/d .functor OR 1, L_0x1233e60, L_0x1024bd0, C4<0>, C4<0>; +L_0x1234310 .delay 1 (30000,30000,30000) L_0x1234310/d; +v0x1024760_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers +v0x10248b0_0 .net "b", 0 0, L_0x1233470; alias, 1 drivers +v0x1024970_0 .net "c1", 0 0, L_0x1233e60; 1 drivers +v0x1024a10_0 .net "c2", 0 0, L_0x1024bd0; 1 drivers +v0x1024ae0_0 .net "carryin", 0 0, L_0x123ddd0; alias, 1 drivers +v0x1024c60_0 .net "carryout", 0 0, L_0x1234310; 1 drivers +v0x1024d00_0 .net "s1", 0 0, L_0x1233da0; 1 drivers +v0x1024da0_0 .net "sum", 0 0, L_0x1233fc0; 1 drivers +S_0x1023bc0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1023970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1da0600/d .functor XOR 1, L_0x1daa3a0, L_0x1d9fd20, C4<0>, C4<0>; -L_0x1da0600 .delay 1 (30000,30000,30000) L_0x1da0600/d; -L_0x1da06c0/d .functor AND 1, L_0x1daa3a0, L_0x1d9fd20, C4<1>, C4<1>; -L_0x1da06c0 .delay 1 (30000,30000,30000) L_0x1da06c0/d; -v0x1b91190_0 .net "a", 0 0, L_0x1daa3a0; alias, 1 drivers -v0x1b91250_0 .net "b", 0 0, L_0x1d9fd20; alias, 1 drivers -v0x1b91310_0 .net "carryout", 0 0, L_0x1da06c0; alias, 1 drivers -v0x1b913b0_0 .net "sum", 0 0, L_0x1da0600; alias, 1 drivers -S_0x1b914e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b90ce0; +L_0x1233da0/d .functor XOR 1, L_0x123db40, L_0x1233470, C4<0>, C4<0>; +L_0x1233da0 .delay 1 (30000,30000,30000) L_0x1233da0/d; +L_0x1233e60/d .functor AND 1, L_0x123db40, L_0x1233470, C4<1>, C4<1>; +L_0x1233e60 .delay 1 (30000,30000,30000) L_0x1233e60/d; +v0x1023e20_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers +v0x1023ee0_0 .net "b", 0 0, L_0x1233470; alias, 1 drivers +v0x1023fa0_0 .net "carryout", 0 0, L_0x1233e60; alias, 1 drivers +v0x1024040_0 .net "sum", 0 0, L_0x1233da0; alias, 1 drivers +S_0x1024170 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1023970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1da0820/d .functor XOR 1, L_0x1da0600, L_0x1daa630, C4<0>, C4<0>; -L_0x1da0820 .delay 1 (30000,30000,30000) L_0x1da0820/d; -L_0x1b91f40/d .functor AND 1, L_0x1da0600, L_0x1daa630, C4<1>, C4<1>; -L_0x1b91f40 .delay 1 (30000,30000,30000) L_0x1b91f40/d; -v0x1b91740_0 .net "a", 0 0, L_0x1da0600; alias, 1 drivers -v0x1b91810_0 .net "b", 0 0, L_0x1daa630; alias, 1 drivers -v0x1b918b0_0 .net "carryout", 0 0, L_0x1b91f40; alias, 1 drivers -v0x1b91980_0 .net "sum", 0 0, L_0x1da0820; alias, 1 drivers -S_0x1b93530 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b837c0; - .timescale -9 -12; -L_0x7f72592da5b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1daa440/d .functor OR 1, L_0x7f72592da5b8, L_0x7f72592da600, C4<0>, C4<0>; -L_0x1daa440 .delay 1 (30000,30000,30000) L_0x1daa440/d; -v0x1b93720_0 .net/2u *"_s0", 0 0, L_0x7f72592da5b8; 1 drivers -v0x1b93800_0 .net/2u *"_s2", 0 0, L_0x7f72592da600; 1 drivers -S_0x1b938e0 .scope generate, "alu_slices[6]" "alu_slices[6]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1b93af0 .param/l "i" 0 3 37, +C4<0110>; -S_0x1b93bb0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b938e0; +L_0x1233fc0/d .functor XOR 1, L_0x1233da0, L_0x123ddd0, C4<0>, C4<0>; +L_0x1233fc0 .delay 1 (30000,30000,30000) L_0x1233fc0/d; +L_0x1024bd0/d .functor AND 1, L_0x1233da0, L_0x123ddd0, C4<1>, C4<1>; +L_0x1024bd0 .delay 1 (30000,30000,30000) L_0x1024bd0/d; +v0x10243d0_0 .net "a", 0 0, L_0x1233da0; alias, 1 drivers +v0x10244a0_0 .net "b", 0 0, L_0x123ddd0; alias, 1 drivers +v0x1024540_0 .net "carryout", 0 0, L_0x1024bd0; alias, 1 drivers +v0x1024610_0 .net "sum", 0 0, L_0x1233fc0; alias, 1 drivers +S_0x10261c0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1016450; + .timescale -9 -12; +L_0x2b0ab3d055b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x123dbe0/d .functor OR 1, L_0x2b0ab3d055b8, L_0x2b0ab3d05600, C4<0>, C4<0>; +L_0x123dbe0 .delay 1 (30000,30000,30000) L_0x123dbe0/d; +v0x10263b0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d055b8; 1 drivers +v0x1026490_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05600; 1 drivers +S_0x1026570 .scope generate, "alu_slices[6]" "alu_slices[6]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1026780 .param/l "i" 0 3 41, +C4<0110>; +S_0x1026840 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1026570; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -3422,445 +3432,445 @@ S_0x1b93bb0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1b938e0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1daa810/d .functor NOT 1, L_0x1db40d0, C4<0>, C4<0>, C4<0>; -L_0x1daa810 .delay 1 (10000,10000,10000) L_0x1daa810/d; -L_0x1daa970/d .functor NOT 1, L_0x1db4340, C4<0>, C4<0>, C4<0>; -L_0x1daa970 .delay 1 (10000,10000,10000) L_0x1daa970/d; -L_0x1dab9c0/d .functor XOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; -L_0x1dab9c0 .delay 1 (30000,30000,30000) L_0x1dab9c0/d; -L_0x7f72592da648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dac070/d .functor OR 1, L_0x7f72592da648, L_0x7f72592da690, C4<0>, C4<0>; -L_0x1dac070 .delay 1 (30000,30000,30000) L_0x1dac070/d; -L_0x1dac270/d .functor AND 1, L_0x1db40d0, L_0x1db4340, C4<1>, C4<1>; -L_0x1dac270 .delay 1 (30000,30000,30000) L_0x1dac270/d; -L_0x1dac330/d .functor NAND 1, L_0x1db40d0, L_0x1db4340, C4<1>, C4<1>; -L_0x1dac330 .delay 1 (20000,20000,20000) L_0x1dac330/d; -L_0x1dac490/d .functor XOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; -L_0x1dac490 .delay 1 (20000,20000,20000) L_0x1dac490/d; -L_0x1dac940/d .functor OR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; -L_0x1dac940 .delay 1 (30000,30000,30000) L_0x1dac940/d; -L_0x1db3fd0/d .functor NOT 1, L_0x1db0230, C4<0>, C4<0>, C4<0>; -L_0x1db3fd0 .delay 1 (10000,10000,10000) L_0x1db3fd0/d; -v0x1ba24e0_0 .net "A", 0 0, L_0x1db40d0; 1 drivers -v0x1ba25a0_0 .net "A_", 0 0, L_0x1daa810; 1 drivers -v0x1ba2660_0 .net "B", 0 0, L_0x1db4340; 1 drivers -v0x1ba2730_0 .net "B_", 0 0, L_0x1daa970; 1 drivers -v0x1ba27d0_0 .net *"_s12", 0 0, L_0x1dac070; 1 drivers -v0x1ba28c0_0 .net/2s *"_s14", 0 0, L_0x7f72592da648; 1 drivers -v0x1ba2980_0 .net/2s *"_s16", 0 0, L_0x7f72592da690; 1 drivers -v0x1ba2a60_0 .net *"_s18", 0 0, L_0x1dac270; 1 drivers -v0x1ba2b40_0 .net *"_s20", 0 0, L_0x1dac330; 1 drivers -v0x1ba2cb0_0 .net *"_s22", 0 0, L_0x1dac490; 1 drivers -v0x1ba2d90_0 .net *"_s24", 0 0, L_0x1dac940; 1 drivers -o0x7f72593642a8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1ba2e70_0 name=_s30 -o0x7f72593642d8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1ba2f50_0 name=_s32 -v0x1ba3030_0 .net *"_s8", 0 0, L_0x1dab9c0; 1 drivers -v0x1ba3110_0 .net "carryin", 0 0, L_0x1daa6d0; 1 drivers -v0x1ba31b0_0 .net "carryout", 0 0, L_0x1db3c70; 1 drivers -v0x1ba3250_0 .net "carryouts", 7 0, L_0x1ebf510; 1 drivers -v0x1ba3400_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ba34a0_0 .net "result", 0 0, L_0x1db0230; 1 drivers -v0x1ba3590_0 .net "results", 7 0, L_0x1dac710; 1 drivers -v0x1ba36a0_0 .net "zero", 0 0, L_0x1db3fd0; 1 drivers -LS_0x1dac710_0_0 .concat8 [ 1 1 1 1], L_0x1daae90, L_0x1dab4c0, L_0x1dab9c0, L_0x1dac070; -LS_0x1dac710_0_4 .concat8 [ 1 1 1 1], L_0x1dac270, L_0x1dac330, L_0x1dac490, L_0x1dac940; -L_0x1dac710 .concat8 [ 4 4 0 0], LS_0x1dac710_0_0, LS_0x1dac710_0_4; -LS_0x1ebf510_0_0 .concat [ 1 1 1 1], L_0x1dab140, L_0x1dab860, o0x7f72593642a8, L_0x1dabec0; -LS_0x1ebf510_0_4 .concat [ 4 0 0 0], o0x7f72593642d8; -L_0x1ebf510 .concat [ 4 4 0 0], LS_0x1ebf510_0_0, LS_0x1ebf510_0_4; -S_0x1b93e30 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1b93bb0; +L_0x123dfb0/d .functor NOT 1, L_0x1247830, C4<0>, C4<0>, C4<0>; +L_0x123dfb0 .delay 1 (10000,10000,10000) L_0x123dfb0/d; +L_0x123e110/d .functor NOT 1, L_0x1247aa0, C4<0>, C4<0>, C4<0>; +L_0x123e110 .delay 1 (10000,10000,10000) L_0x123e110/d; +L_0x123f0a0/d .functor XOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; +L_0x123f0a0 .delay 1 (30000,30000,30000) L_0x123f0a0/d; +L_0x2b0ab3d05648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x123f750/d .functor OR 1, L_0x2b0ab3d05648, L_0x2b0ab3d05690, C4<0>, C4<0>; +L_0x123f750 .delay 1 (30000,30000,30000) L_0x123f750/d; +L_0x123f950/d .functor AND 1, L_0x1247830, L_0x1247aa0, C4<1>, C4<1>; +L_0x123f950 .delay 1 (30000,30000,30000) L_0x123f950/d; +L_0x123fa10/d .functor NAND 1, L_0x1247830, L_0x1247aa0, C4<1>, C4<1>; +L_0x123fa10 .delay 1 (20000,20000,20000) L_0x123fa10/d; +L_0x123fb70/d .functor XOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; +L_0x123fb70 .delay 1 (20000,20000,20000) L_0x123fb70/d; +L_0x1240020/d .functor OR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; +L_0x1240020 .delay 1 (30000,30000,30000) L_0x1240020/d; +L_0x1247730/d .functor NOT 1, L_0x1243990, C4<0>, C4<0>, C4<0>; +L_0x1247730 .delay 1 (10000,10000,10000) L_0x1247730/d; +v0x1035170_0 .net "A", 0 0, L_0x1247830; 1 drivers +v0x1035230_0 .net "A_", 0 0, L_0x123dfb0; 1 drivers +v0x10352f0_0 .net "B", 0 0, L_0x1247aa0; 1 drivers +v0x10353c0_0 .net "B_", 0 0, L_0x123e110; 1 drivers +v0x1035460_0 .net *"_s12", 0 0, L_0x123f750; 1 drivers +v0x1035550_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05648; 1 drivers +v0x1035610_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05690; 1 drivers +v0x10356f0_0 .net *"_s18", 0 0, L_0x123f950; 1 drivers +v0x10357d0_0 .net *"_s20", 0 0, L_0x123fa10; 1 drivers +v0x1035940_0 .net *"_s22", 0 0, L_0x123fb70; 1 drivers +v0x1035a20_0 .net *"_s24", 0 0, L_0x1240020; 1 drivers +o0x2b0ab3cb32a8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1035b00_0 name=_s30 +o0x2b0ab3cb32d8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1035be0_0 name=_s32 +v0x1035cc0_0 .net *"_s8", 0 0, L_0x123f0a0; 1 drivers +v0x1035da0_0 .net "carryin", 0 0, L_0x123de70; 1 drivers +v0x1035e40_0 .net "carryout", 0 0, L_0x12473d0; 1 drivers +v0x1035ee0_0 .net "carryouts", 7 0, L_0x13538c0; 1 drivers +v0x1036090_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1036130_0 .net "result", 0 0, L_0x1243990; 1 drivers +v0x1036220_0 .net "results", 7 0, L_0x123fdf0; 1 drivers +v0x1036330_0 .net "zero", 0 0, L_0x1247730; 1 drivers +LS_0x123fdf0_0_0 .concat8 [ 1 1 1 1], L_0x123e5c0, L_0x123ebf0, L_0x123f0a0, L_0x123f750; +LS_0x123fdf0_0_4 .concat8 [ 1 1 1 1], L_0x123f950, L_0x123fa10, L_0x123fb70, L_0x1240020; +L_0x123fdf0 .concat8 [ 4 4 0 0], LS_0x123fdf0_0_0, LS_0x123fdf0_0_4; +LS_0x13538c0_0_0 .concat [ 1 1 1 1], L_0x123e870, L_0x123ef40, o0x2b0ab3cb32a8, L_0x123f5a0; +LS_0x13538c0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb32d8; +L_0x13538c0 .concat [ 4 4 0 0], LS_0x13538c0_0_0, LS_0x13538c0_0_4; +S_0x1026ac0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1026840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dab140/d .functor OR 1, L_0x1daac20, L_0x1daafe0, C4<0>, C4<0>; -L_0x1dab140 .delay 1 (30000,30000,30000) L_0x1dab140/d; -v0x1b94c60_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers -v0x1b94d20_0 .net "b", 0 0, L_0x1db4340; alias, 1 drivers -v0x1b94df0_0 .net "c1", 0 0, L_0x1daac20; 1 drivers -v0x1b94ef0_0 .net "c2", 0 0, L_0x1daafe0; 1 drivers -v0x1b94fc0_0 .net "carryin", 0 0, L_0x1daa6d0; alias, 1 drivers -v0x1b950b0_0 .net "carryout", 0 0, L_0x1dab140; 1 drivers -v0x1b95150_0 .net "s1", 0 0, L_0x1daab60; 1 drivers -v0x1b95240_0 .net "sum", 0 0, L_0x1daae90; 1 drivers -S_0x1b940a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1b93e30; +L_0x123e870/d .functor OR 1, L_0x123e350, L_0x123e710, C4<0>, C4<0>; +L_0x123e870 .delay 1 (30000,30000,30000) L_0x123e870/d; +v0x10278f0_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers +v0x10279b0_0 .net "b", 0 0, L_0x1247aa0; alias, 1 drivers +v0x1027a80_0 .net "c1", 0 0, L_0x123e350; 1 drivers +v0x1027b80_0 .net "c2", 0 0, L_0x123e710; 1 drivers +v0x1027c50_0 .net "carryin", 0 0, L_0x123de70; alias, 1 drivers +v0x1027d40_0 .net "carryout", 0 0, L_0x123e870; 1 drivers +v0x1027de0_0 .net "s1", 0 0, L_0x1223410; 1 drivers +v0x1027ed0_0 .net "sum", 0 0, L_0x123e5c0; 1 drivers +S_0x1026d30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1026ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1daab60/d .functor XOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; -L_0x1daab60 .delay 1 (30000,30000,30000) L_0x1daab60/d; -L_0x1daac20/d .functor AND 1, L_0x1db40d0, L_0x1db4340, C4<1>, C4<1>; -L_0x1daac20 .delay 1 (30000,30000,30000) L_0x1daac20/d; -v0x1b94300_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers -v0x1b943e0_0 .net "b", 0 0, L_0x1db4340; alias, 1 drivers -v0x1b944a0_0 .net "carryout", 0 0, L_0x1daac20; alias, 1 drivers -v0x1b94540_0 .net "sum", 0 0, L_0x1daab60; alias, 1 drivers -S_0x1b94680 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1b93e30; +L_0x1223410/d .functor XOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; +L_0x1223410 .delay 1 (30000,30000,30000) L_0x1223410/d; +L_0x123e350/d .functor AND 1, L_0x1247830, L_0x1247aa0, C4<1>, C4<1>; +L_0x123e350 .delay 1 (30000,30000,30000) L_0x123e350/d; +v0x1026f90_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers +v0x1027070_0 .net "b", 0 0, L_0x1247aa0; alias, 1 drivers +v0x1027130_0 .net "carryout", 0 0, L_0x123e350; alias, 1 drivers +v0x10271d0_0 .net "sum", 0 0, L_0x1223410; alias, 1 drivers +S_0x1027310 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1026ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1daae90/d .functor XOR 1, L_0x1daab60, L_0x1daa6d0, C4<0>, C4<0>; -L_0x1daae90 .delay 1 (30000,30000,30000) L_0x1daae90/d; -L_0x1daafe0/d .functor AND 1, L_0x1daab60, L_0x1daa6d0, C4<1>, C4<1>; -L_0x1daafe0 .delay 1 (30000,30000,30000) L_0x1daafe0/d; -v0x1b948e0_0 .net "a", 0 0, L_0x1daab60; alias, 1 drivers -v0x1b94980_0 .net "b", 0 0, L_0x1daa6d0; alias, 1 drivers -v0x1b94a20_0 .net "carryout", 0 0, L_0x1daafe0; alias, 1 drivers -v0x1b94af0_0 .net "sum", 0 0, L_0x1daae90; alias, 1 drivers -S_0x1b95310 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1b93bb0; +L_0x123e5c0/d .functor XOR 1, L_0x1223410, L_0x123de70, C4<0>, C4<0>; +L_0x123e5c0 .delay 1 (30000,30000,30000) L_0x123e5c0/d; +L_0x123e710/d .functor AND 1, L_0x1223410, L_0x123de70, C4<1>, C4<1>; +L_0x123e710 .delay 1 (30000,30000,30000) L_0x123e710/d; +v0x1027570_0 .net "a", 0 0, L_0x1223410; alias, 1 drivers +v0x1027610_0 .net "b", 0 0, L_0x123de70; alias, 1 drivers +v0x10276b0_0 .net "carryout", 0 0, L_0x123e710; alias, 1 drivers +v0x1027780_0 .net "sum", 0 0, L_0x123e5c0; alias, 1 drivers +S_0x1027fa0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1026840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1b9a700_0 .net "ands", 7 0, L_0x1db1c70; 1 drivers -v0x1b9a810_0 .net "in", 7 0, L_0x1ebf510; alias, 1 drivers -v0x1b9a8d0_0 .net "out", 0 0, L_0x1db3c70; alias, 1 drivers -v0x1b9a9a0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b95530 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b95310; +v0x102d390_0 .net "ands", 7 0, L_0x12453d0; 1 drivers +v0x102d4a0_0 .net "in", 7 0, L_0x13538c0; alias, 1 drivers +v0x102d560_0 .net "out", 0 0, L_0x12473d0; alias, 1 drivers +v0x102d630_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10281c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1027fa0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b97c60_0 .net "A", 7 0, L_0x1ebf510; alias, 1 drivers -v0x1b97d60_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b97e20_0 .net *"_s0", 0 0, L_0x1db0590; 1 drivers -v0x1b97ee0_0 .net *"_s12", 0 0, L_0x1db0f00; 1 drivers -v0x1b97fc0_0 .net *"_s16", 0 0, L_0x1db1260; 1 drivers -v0x1b980f0_0 .net *"_s20", 0 0, L_0x1db1570; 1 drivers -v0x1b981d0_0 .net *"_s24", 0 0, L_0x1db1960; 1 drivers -v0x1b982b0_0 .net *"_s28", 0 0, L_0x1db18f0; 1 drivers -v0x1b98390_0 .net *"_s4", 0 0, L_0x1db08a0; 1 drivers -v0x1b98500_0 .net *"_s8", 0 0, L_0x1db0bf0; 1 drivers -v0x1b985e0_0 .net "out", 7 0, L_0x1db1c70; alias, 1 drivers -L_0x1db0650 .part L_0x1ebf510, 0, 1; -L_0x1db07b0 .part v0x1d6daa0_0, 0, 1; -L_0x1db0960 .part L_0x1ebf510, 1, 1; -L_0x1db0b50 .part v0x1d6daa0_0, 1, 1; -L_0x1db0cb0 .part L_0x1ebf510, 2, 1; -L_0x1db0e10 .part v0x1d6daa0_0, 2, 1; -L_0x1db0fc0 .part L_0x1ebf510, 3, 1; -L_0x1db1120 .part v0x1d6daa0_0, 3, 1; -L_0x1db1320 .part L_0x1ebf510, 4, 1; -L_0x1db1480 .part v0x1d6daa0_0, 4, 1; -L_0x1db15e0 .part L_0x1ebf510, 5, 1; -L_0x1db1850 .part v0x1d6daa0_0, 5, 1; -L_0x1db1a20 .part L_0x1ebf510, 6, 1; -L_0x1db1b80 .part v0x1d6daa0_0, 6, 1; -LS_0x1db1c70_0_0 .concat8 [ 1 1 1 1], L_0x1db0590, L_0x1db08a0, L_0x1db0bf0, L_0x1db0f00; -LS_0x1db1c70_0_4 .concat8 [ 1 1 1 1], L_0x1db1260, L_0x1db1570, L_0x1db1960, L_0x1db18f0; -L_0x1db1c70 .concat8 [ 4 4 0 0], LS_0x1db1c70_0_0, LS_0x1db1c70_0_4; -L_0x1db2030 .part L_0x1ebf510, 7, 1; -L_0x1db2220 .part v0x1d6daa0_0, 7, 1; -S_0x1b95790 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b959a0 .param/l "i" 0 4 54, +C4<00>; -L_0x1db0590/d .functor AND 1, L_0x1db0650, L_0x1db07b0, C4<1>, C4<1>; -L_0x1db0590 .delay 1 (30000,30000,30000) L_0x1db0590/d; -v0x1b95a80_0 .net *"_s0", 0 0, L_0x1db0650; 1 drivers -v0x1b95b60_0 .net *"_s1", 0 0, L_0x1db07b0; 1 drivers -S_0x1b95c40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b95e50 .param/l "i" 0 4 54, +C4<01>; -L_0x1db08a0/d .functor AND 1, L_0x1db0960, L_0x1db0b50, C4<1>, C4<1>; -L_0x1db08a0 .delay 1 (30000,30000,30000) L_0x1db08a0/d; -v0x1b95f10_0 .net *"_s0", 0 0, L_0x1db0960; 1 drivers -v0x1b95ff0_0 .net *"_s1", 0 0, L_0x1db0b50; 1 drivers -S_0x1b960d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b962e0 .param/l "i" 0 4 54, +C4<010>; -L_0x1db0bf0/d .functor AND 1, L_0x1db0cb0, L_0x1db0e10, C4<1>, C4<1>; -L_0x1db0bf0 .delay 1 (30000,30000,30000) L_0x1db0bf0/d; -v0x1b96380_0 .net *"_s0", 0 0, L_0x1db0cb0; 1 drivers -v0x1b96460_0 .net *"_s1", 0 0, L_0x1db0e10; 1 drivers -S_0x1b96540 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b96750 .param/l "i" 0 4 54, +C4<011>; -L_0x1db0f00/d .functor AND 1, L_0x1db0fc0, L_0x1db1120, C4<1>, C4<1>; -L_0x1db0f00 .delay 1 (30000,30000,30000) L_0x1db0f00/d; -v0x1b96810_0 .net *"_s0", 0 0, L_0x1db0fc0; 1 drivers -v0x1b968f0_0 .net *"_s1", 0 0, L_0x1db1120; 1 drivers -S_0x1b969d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b96c30 .param/l "i" 0 4 54, +C4<0100>; -L_0x1db1260/d .functor AND 1, L_0x1db1320, L_0x1db1480, C4<1>, C4<1>; -L_0x1db1260 .delay 1 (30000,30000,30000) L_0x1db1260/d; -v0x1b96cf0_0 .net *"_s0", 0 0, L_0x1db1320; 1 drivers -v0x1b96dd0_0 .net *"_s1", 0 0, L_0x1db1480; 1 drivers -S_0x1b96eb0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b970c0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1db1570/d .functor AND 1, L_0x1db15e0, L_0x1db1850, C4<1>, C4<1>; -L_0x1db1570 .delay 1 (30000,30000,30000) L_0x1db1570/d; -v0x1b97180_0 .net *"_s0", 0 0, L_0x1db15e0; 1 drivers -v0x1b97260_0 .net *"_s1", 0 0, L_0x1db1850; 1 drivers -S_0x1b97340 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b97550 .param/l "i" 0 4 54, +C4<0110>; -L_0x1db1960/d .functor AND 1, L_0x1db1a20, L_0x1db1b80, C4<1>, C4<1>; -L_0x1db1960 .delay 1 (30000,30000,30000) L_0x1db1960/d; -v0x1b97610_0 .net *"_s0", 0 0, L_0x1db1a20; 1 drivers -v0x1b976f0_0 .net *"_s1", 0 0, L_0x1db1b80; 1 drivers -S_0x1b977d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b95530; - .timescale -9 -12; -P_0x1b979e0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1db18f0/d .functor AND 1, L_0x1db2030, L_0x1db2220, C4<1>, C4<1>; -L_0x1db18f0 .delay 1 (30000,30000,30000) L_0x1db18f0/d; -v0x1b97aa0_0 .net *"_s0", 0 0, L_0x1db2030; 1 drivers -v0x1b97b80_0 .net *"_s1", 0 0, L_0x1db2220; 1 drivers -S_0x1b98740 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b95310; +v0x102a8f0_0 .net "A", 7 0, L_0x13538c0; alias, 1 drivers +v0x102a9f0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x102aab0_0 .net *"_s0", 0 0, L_0x1243cf0; 1 drivers +v0x102ab70_0 .net *"_s12", 0 0, L_0x1244660; 1 drivers +v0x102ac50_0 .net *"_s16", 0 0, L_0x12449c0; 1 drivers +v0x102ad80_0 .net *"_s20", 0 0, L_0x1244cd0; 1 drivers +v0x102ae60_0 .net *"_s24", 0 0, L_0x12450c0; 1 drivers +v0x102af40_0 .net *"_s28", 0 0, L_0x1245050; 1 drivers +v0x102b020_0 .net *"_s4", 0 0, L_0x1244000; 1 drivers +v0x102b190_0 .net *"_s8", 0 0, L_0x1244350; 1 drivers +v0x102b270_0 .net "out", 7 0, L_0x12453d0; alias, 1 drivers +L_0x1243db0 .part L_0x13538c0, 0, 1; +L_0x1243f10 .part v0x12010b0_0, 0, 1; +L_0x12440c0 .part L_0x13538c0, 1, 1; +L_0x12442b0 .part v0x12010b0_0, 1, 1; +L_0x1244410 .part L_0x13538c0, 2, 1; +L_0x1244570 .part v0x12010b0_0, 2, 1; +L_0x1244720 .part L_0x13538c0, 3, 1; +L_0x1244880 .part v0x12010b0_0, 3, 1; +L_0x1244a80 .part L_0x13538c0, 4, 1; +L_0x1244be0 .part v0x12010b0_0, 4, 1; +L_0x1244d40 .part L_0x13538c0, 5, 1; +L_0x1244fb0 .part v0x12010b0_0, 5, 1; +L_0x1245180 .part L_0x13538c0, 6, 1; +L_0x12452e0 .part v0x12010b0_0, 6, 1; +LS_0x12453d0_0_0 .concat8 [ 1 1 1 1], L_0x1243cf0, L_0x1244000, L_0x1244350, L_0x1244660; +LS_0x12453d0_0_4 .concat8 [ 1 1 1 1], L_0x12449c0, L_0x1244cd0, L_0x12450c0, L_0x1245050; +L_0x12453d0 .concat8 [ 4 4 0 0], LS_0x12453d0_0_0, LS_0x12453d0_0_4; +L_0x1245790 .part L_0x13538c0, 7, 1; +L_0x1245980 .part v0x12010b0_0, 7, 1; +S_0x1028420 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x1028630 .param/l "i" 0 4 54, +C4<00>; +L_0x1243cf0/d .functor AND 1, L_0x1243db0, L_0x1243f10, C4<1>, C4<1>; +L_0x1243cf0 .delay 1 (30000,30000,30000) L_0x1243cf0/d; +v0x1028710_0 .net *"_s0", 0 0, L_0x1243db0; 1 drivers +v0x10287f0_0 .net *"_s1", 0 0, L_0x1243f10; 1 drivers +S_0x10288d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x1028ae0 .param/l "i" 0 4 54, +C4<01>; +L_0x1244000/d .functor AND 1, L_0x12440c0, L_0x12442b0, C4<1>, C4<1>; +L_0x1244000 .delay 1 (30000,30000,30000) L_0x1244000/d; +v0x1028ba0_0 .net *"_s0", 0 0, L_0x12440c0; 1 drivers +v0x1028c80_0 .net *"_s1", 0 0, L_0x12442b0; 1 drivers +S_0x1028d60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x1028f70 .param/l "i" 0 4 54, +C4<010>; +L_0x1244350/d .functor AND 1, L_0x1244410, L_0x1244570, C4<1>, C4<1>; +L_0x1244350 .delay 1 (30000,30000,30000) L_0x1244350/d; +v0x1029010_0 .net *"_s0", 0 0, L_0x1244410; 1 drivers +v0x10290f0_0 .net *"_s1", 0 0, L_0x1244570; 1 drivers +S_0x10291d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x10293e0 .param/l "i" 0 4 54, +C4<011>; +L_0x1244660/d .functor AND 1, L_0x1244720, L_0x1244880, C4<1>, C4<1>; +L_0x1244660 .delay 1 (30000,30000,30000) L_0x1244660/d; +v0x10294a0_0 .net *"_s0", 0 0, L_0x1244720; 1 drivers +v0x1029580_0 .net *"_s1", 0 0, L_0x1244880; 1 drivers +S_0x1029660 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x10298c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12449c0/d .functor AND 1, L_0x1244a80, L_0x1244be0, C4<1>, C4<1>; +L_0x12449c0 .delay 1 (30000,30000,30000) L_0x12449c0/d; +v0x1029980_0 .net *"_s0", 0 0, L_0x1244a80; 1 drivers +v0x1029a60_0 .net *"_s1", 0 0, L_0x1244be0; 1 drivers +S_0x1029b40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x1029d50 .param/l "i" 0 4 54, +C4<0101>; +L_0x1244cd0/d .functor AND 1, L_0x1244d40, L_0x1244fb0, C4<1>, C4<1>; +L_0x1244cd0 .delay 1 (30000,30000,30000) L_0x1244cd0/d; +v0x1029e10_0 .net *"_s0", 0 0, L_0x1244d40; 1 drivers +v0x1029ef0_0 .net *"_s1", 0 0, L_0x1244fb0; 1 drivers +S_0x1029fd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x102a1e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12450c0/d .functor AND 1, L_0x1245180, L_0x12452e0, C4<1>, C4<1>; +L_0x12450c0 .delay 1 (30000,30000,30000) L_0x12450c0/d; +v0x102a2a0_0 .net *"_s0", 0 0, L_0x1245180; 1 drivers +v0x102a380_0 .net *"_s1", 0 0, L_0x12452e0; 1 drivers +S_0x102a460 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10281c0; + .timescale -9 -12; +P_0x102a670 .param/l "i" 0 4 54, +C4<0111>; +L_0x1245050/d .functor AND 1, L_0x1245790, L_0x1245980, C4<1>, C4<1>; +L_0x1245050 .delay 1 (30000,30000,30000) L_0x1245050/d; +v0x102a730_0 .net *"_s0", 0 0, L_0x1245790; 1 drivers +v0x102a810_0 .net *"_s1", 0 0, L_0x1245980; 1 drivers +S_0x102b3d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1027fa0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1db3c70/d .functor OR 1, L_0x1db3d30, L_0x1db3ee0, C4<0>, C4<0>; -L_0x1db3c70 .delay 1 (30000,30000,30000) L_0x1db3c70/d; -v0x1b9a290_0 .net *"_s10", 0 0, L_0x1db3d30; 1 drivers -v0x1b9a370_0 .net *"_s12", 0 0, L_0x1db3ee0; 1 drivers -v0x1b9a450_0 .net "in", 7 0, L_0x1db1c70; alias, 1 drivers -v0x1b9a520_0 .net "ors", 1 0, L_0x1db3a90; 1 drivers -v0x1b9a5e0_0 .net "out", 0 0, L_0x1db3c70; alias, 1 drivers -L_0x1db2e60 .part L_0x1db1c70, 0, 4; -L_0x1db3a90 .concat8 [ 1 1 0 0], L_0x1db2b50, L_0x1db3780; -L_0x1db3bd0 .part L_0x1db1c70, 4, 4; -L_0x1db3d30 .part L_0x1db3a90, 0, 1; -L_0x1db3ee0 .part L_0x1db3a90, 1, 1; -S_0x1b98900 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b98740; +L_0x12473d0/d .functor OR 1, L_0x1247490, L_0x1247640, C4<0>, C4<0>; +L_0x12473d0 .delay 1 (30000,30000,30000) L_0x12473d0/d; +v0x102cf20_0 .net *"_s10", 0 0, L_0x1247490; 1 drivers +v0x102d000_0 .net *"_s12", 0 0, L_0x1247640; 1 drivers +v0x102d0e0_0 .net "in", 7 0, L_0x12453d0; alias, 1 drivers +v0x102d1b0_0 .net "ors", 1 0, L_0x12471f0; 1 drivers +v0x102d270_0 .net "out", 0 0, L_0x12473d0; alias, 1 drivers +L_0x12465c0 .part L_0x12453d0, 0, 4; +L_0x12471f0 .concat8 [ 1 1 0 0], L_0x12462b0, L_0x1246ee0; +L_0x1247330 .part L_0x12453d0, 4, 4; +L_0x1247490 .part L_0x12471f0, 0, 1; +L_0x1247640 .part L_0x12471f0, 1, 1; +S_0x102b590 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x102b3d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1db2310/d .functor OR 1, L_0x1db23d0, L_0x1db2530, C4<0>, C4<0>; -L_0x1db2310 .delay 1 (30000,30000,30000) L_0x1db2310/d; -L_0x1db2760/d .functor OR 1, L_0x1db2870, L_0x1db29d0, C4<0>, C4<0>; -L_0x1db2760 .delay 1 (30000,30000,30000) L_0x1db2760/d; -L_0x1db2b50/d .functor OR 1, L_0x1db2bc0, L_0x1db2d70, C4<0>, C4<0>; -L_0x1db2b50 .delay 1 (30000,30000,30000) L_0x1db2b50/d; -v0x1b98b50_0 .net *"_s0", 0 0, L_0x1db2310; 1 drivers -v0x1b98c50_0 .net *"_s10", 0 0, L_0x1db2870; 1 drivers -v0x1b98d30_0 .net *"_s12", 0 0, L_0x1db29d0; 1 drivers -v0x1b98df0_0 .net *"_s14", 0 0, L_0x1db2bc0; 1 drivers -v0x1b98ed0_0 .net *"_s16", 0 0, L_0x1db2d70; 1 drivers -v0x1b99000_0 .net *"_s3", 0 0, L_0x1db23d0; 1 drivers -v0x1b990e0_0 .net *"_s5", 0 0, L_0x1db2530; 1 drivers -v0x1b991c0_0 .net *"_s6", 0 0, L_0x1db2760; 1 drivers -v0x1b992a0_0 .net "in", 3 0, L_0x1db2e60; 1 drivers -v0x1b99410_0 .net "ors", 1 0, L_0x1db2670; 1 drivers -v0x1b994f0_0 .net "out", 0 0, L_0x1db2b50; 1 drivers -L_0x1db23d0 .part L_0x1db2e60, 0, 1; -L_0x1db2530 .part L_0x1db2e60, 1, 1; -L_0x1db2670 .concat8 [ 1 1 0 0], L_0x1db2310, L_0x1db2760; -L_0x1db2870 .part L_0x1db2e60, 2, 1; -L_0x1db29d0 .part L_0x1db2e60, 3, 1; -L_0x1db2bc0 .part L_0x1db2670, 0, 1; -L_0x1db2d70 .part L_0x1db2670, 1, 1; -S_0x1b99610 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b98740; +L_0x1245a70/d .functor OR 1, L_0x1245b30, L_0x1245c90, C4<0>, C4<0>; +L_0x1245a70 .delay 1 (30000,30000,30000) L_0x1245a70/d; +L_0x1245ec0/d .functor OR 1, L_0x1245fd0, L_0x1246130, C4<0>, C4<0>; +L_0x1245ec0 .delay 1 (30000,30000,30000) L_0x1245ec0/d; +L_0x12462b0/d .functor OR 1, L_0x1246320, L_0x12464d0, C4<0>, C4<0>; +L_0x12462b0 .delay 1 (30000,30000,30000) L_0x12462b0/d; +v0x102b7e0_0 .net *"_s0", 0 0, L_0x1245a70; 1 drivers +v0x102b8e0_0 .net *"_s10", 0 0, L_0x1245fd0; 1 drivers +v0x102b9c0_0 .net *"_s12", 0 0, L_0x1246130; 1 drivers +v0x102ba80_0 .net *"_s14", 0 0, L_0x1246320; 1 drivers +v0x102bb60_0 .net *"_s16", 0 0, L_0x12464d0; 1 drivers +v0x102bc90_0 .net *"_s3", 0 0, L_0x1245b30; 1 drivers +v0x102bd70_0 .net *"_s5", 0 0, L_0x1245c90; 1 drivers +v0x102be50_0 .net *"_s6", 0 0, L_0x1245ec0; 1 drivers +v0x102bf30_0 .net "in", 3 0, L_0x12465c0; 1 drivers +v0x102c0a0_0 .net "ors", 1 0, L_0x1245dd0; 1 drivers +v0x102c180_0 .net "out", 0 0, L_0x12462b0; 1 drivers +L_0x1245b30 .part L_0x12465c0, 0, 1; +L_0x1245c90 .part L_0x12465c0, 1, 1; +L_0x1245dd0 .concat8 [ 1 1 0 0], L_0x1245a70, L_0x1245ec0; +L_0x1245fd0 .part L_0x12465c0, 2, 1; +L_0x1246130 .part L_0x12465c0, 3, 1; +L_0x1246320 .part L_0x1245dd0, 0, 1; +L_0x12464d0 .part L_0x1245dd0, 1, 1; +S_0x102c2a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x102b3d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1db2f90/d .functor OR 1, L_0x1db3000, L_0x1db3160, C4<0>, C4<0>; -L_0x1db2f90 .delay 1 (30000,30000,30000) L_0x1db2f90/d; -L_0x1db3390/d .functor OR 1, L_0x1db34a0, L_0x1db3600, C4<0>, C4<0>; -L_0x1db3390 .delay 1 (30000,30000,30000) L_0x1db3390/d; -L_0x1db3780/d .functor OR 1, L_0x1db37f0, L_0x1db39a0, C4<0>, C4<0>; -L_0x1db3780 .delay 1 (30000,30000,30000) L_0x1db3780/d; -v0x1b997d0_0 .net *"_s0", 0 0, L_0x1db2f90; 1 drivers -v0x1b998d0_0 .net *"_s10", 0 0, L_0x1db34a0; 1 drivers -v0x1b999b0_0 .net *"_s12", 0 0, L_0x1db3600; 1 drivers -v0x1b99a70_0 .net *"_s14", 0 0, L_0x1db37f0; 1 drivers -v0x1b99b50_0 .net *"_s16", 0 0, L_0x1db39a0; 1 drivers -v0x1b99c80_0 .net *"_s3", 0 0, L_0x1db3000; 1 drivers -v0x1b99d60_0 .net *"_s5", 0 0, L_0x1db3160; 1 drivers -v0x1b99e40_0 .net *"_s6", 0 0, L_0x1db3390; 1 drivers -v0x1b99f20_0 .net "in", 3 0, L_0x1db3bd0; 1 drivers -v0x1b9a090_0 .net "ors", 1 0, L_0x1db32a0; 1 drivers -v0x1b9a170_0 .net "out", 0 0, L_0x1db3780; 1 drivers -L_0x1db3000 .part L_0x1db3bd0, 0, 1; -L_0x1db3160 .part L_0x1db3bd0, 1, 1; -L_0x1db32a0 .concat8 [ 1 1 0 0], L_0x1db2f90, L_0x1db3390; -L_0x1db34a0 .part L_0x1db3bd0, 2, 1; -L_0x1db3600 .part L_0x1db3bd0, 3, 1; -L_0x1db37f0 .part L_0x1db32a0, 0, 1; -L_0x1db39a0 .part L_0x1db32a0, 1, 1; -S_0x1b9aa80 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1b93bb0; +L_0x12466f0/d .functor OR 1, L_0x1246760, L_0x12468c0, C4<0>, C4<0>; +L_0x12466f0 .delay 1 (30000,30000,30000) L_0x12466f0/d; +L_0x1246af0/d .functor OR 1, L_0x1246c00, L_0x1246d60, C4<0>, C4<0>; +L_0x1246af0 .delay 1 (30000,30000,30000) L_0x1246af0/d; +L_0x1246ee0/d .functor OR 1, L_0x1246f50, L_0x1247100, C4<0>, C4<0>; +L_0x1246ee0 .delay 1 (30000,30000,30000) L_0x1246ee0/d; +v0x102c460_0 .net *"_s0", 0 0, L_0x12466f0; 1 drivers +v0x102c560_0 .net *"_s10", 0 0, L_0x1246c00; 1 drivers +v0x102c640_0 .net *"_s12", 0 0, L_0x1246d60; 1 drivers +v0x102c700_0 .net *"_s14", 0 0, L_0x1246f50; 1 drivers +v0x102c7e0_0 .net *"_s16", 0 0, L_0x1247100; 1 drivers +v0x102c910_0 .net *"_s3", 0 0, L_0x1246760; 1 drivers +v0x102c9f0_0 .net *"_s5", 0 0, L_0x12468c0; 1 drivers +v0x102cad0_0 .net *"_s6", 0 0, L_0x1246af0; 1 drivers +v0x102cbb0_0 .net "in", 3 0, L_0x1247330; 1 drivers +v0x102cd20_0 .net "ors", 1 0, L_0x1246a00; 1 drivers +v0x102ce00_0 .net "out", 0 0, L_0x1246ee0; 1 drivers +L_0x1246760 .part L_0x1247330, 0, 1; +L_0x12468c0 .part L_0x1247330, 1, 1; +L_0x1246a00 .concat8 [ 1 1 0 0], L_0x12466f0, L_0x1246af0; +L_0x1246c00 .part L_0x1247330, 2, 1; +L_0x1246d60 .part L_0x1247330, 3, 1; +L_0x1246f50 .part L_0x1246a00, 0, 1; +L_0x1247100 .part L_0x1246a00, 1, 1; +S_0x102d710 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1026840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1ba00b0_0 .net "ands", 7 0, L_0x1dae230; 1 drivers -v0x1ba01c0_0 .net "in", 7 0, L_0x1dac710; alias, 1 drivers -v0x1ba0280_0 .net "out", 0 0, L_0x1db0230; alias, 1 drivers -v0x1ba0350_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1b9acd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1b9aa80; +v0x1032d40_0 .net "ands", 7 0, L_0x1241990; 1 drivers +v0x1032e50_0 .net "in", 7 0, L_0x123fdf0; alias, 1 drivers +v0x1032f10_0 .net "out", 0 0, L_0x1243990; alias, 1 drivers +v0x1032fe0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x102d960 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x102d710; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1b9d410_0 .net "A", 7 0, L_0x1dac710; alias, 1 drivers -v0x1b9d510_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b6a5e0_0 .net *"_s0", 0 0, L_0x1dacaa0; 1 drivers -v0x1b6a6a0_0 .net *"_s12", 0 0, L_0x1dad460; 1 drivers -v0x1b9d9e0_0 .net *"_s16", 0 0, L_0x1dad7c0; 1 drivers -v0x1b9daa0_0 .net *"_s20", 0 0, L_0x1dadbf0; 1 drivers -v0x1b9db80_0 .net *"_s24", 0 0, L_0x1dadf20; 1 drivers -v0x1b9dc60_0 .net *"_s28", 0 0, L_0x1dadeb0; 1 drivers -v0x1b9dd40_0 .net *"_s4", 0 0, L_0x1dace40; 1 drivers -v0x1b9deb0_0 .net *"_s8", 0 0, L_0x1dad150; 1 drivers -v0x1b9df90_0 .net "out", 7 0, L_0x1dae230; alias, 1 drivers -L_0x1dacbb0 .part L_0x1dac710, 0, 1; -L_0x1dacda0 .part v0x1d6daa0_0, 0, 1; -L_0x1dacf00 .part L_0x1dac710, 1, 1; -L_0x1dad060 .part v0x1d6daa0_0, 1, 1; -L_0x1dad210 .part L_0x1dac710, 2, 1; -L_0x1dad370 .part v0x1d6daa0_0, 2, 1; -L_0x1dad520 .part L_0x1dac710, 3, 1; -L_0x1dad680 .part v0x1d6daa0_0, 3, 1; -L_0x1dad880 .part L_0x1dac710, 4, 1; -L_0x1dadaf0 .part v0x1d6daa0_0, 4, 1; -L_0x1dadc60 .part L_0x1dac710, 5, 1; -L_0x1daddc0 .part v0x1d6daa0_0, 5, 1; -L_0x1dadfe0 .part L_0x1dac710, 6, 1; -L_0x1dae140 .part v0x1d6daa0_0, 6, 1; -LS_0x1dae230_0_0 .concat8 [ 1 1 1 1], L_0x1dacaa0, L_0x1dace40, L_0x1dad150, L_0x1dad460; -LS_0x1dae230_0_4 .concat8 [ 1 1 1 1], L_0x1dad7c0, L_0x1dadbf0, L_0x1dadf20, L_0x1dadeb0; -L_0x1dae230 .concat8 [ 4 4 0 0], LS_0x1dae230_0_0, LS_0x1dae230_0_4; -L_0x1dae5f0 .part L_0x1dac710, 7, 1; -L_0x1dae7e0 .part v0x1d6daa0_0, 7, 1; -S_0x1b9af10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9b120 .param/l "i" 0 4 54, +C4<00>; -L_0x1dacaa0/d .functor AND 1, L_0x1dacbb0, L_0x1dacda0, C4<1>, C4<1>; -L_0x1dacaa0 .delay 1 (30000,30000,30000) L_0x1dacaa0/d; -v0x1b9b200_0 .net *"_s0", 0 0, L_0x1dacbb0; 1 drivers -v0x1b9b2e0_0 .net *"_s1", 0 0, L_0x1dacda0; 1 drivers -S_0x1b9b3c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9b5d0 .param/l "i" 0 4 54, +C4<01>; -L_0x1dace40/d .functor AND 1, L_0x1dacf00, L_0x1dad060, C4<1>, C4<1>; -L_0x1dace40 .delay 1 (30000,30000,30000) L_0x1dace40/d; -v0x1b9b690_0 .net *"_s0", 0 0, L_0x1dacf00; 1 drivers -v0x1b9b770_0 .net *"_s1", 0 0, L_0x1dad060; 1 drivers -S_0x1b9b850 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9ba90 .param/l "i" 0 4 54, +C4<010>; -L_0x1dad150/d .functor AND 1, L_0x1dad210, L_0x1dad370, C4<1>, C4<1>; -L_0x1dad150 .delay 1 (30000,30000,30000) L_0x1dad150/d; -v0x1b9bb30_0 .net *"_s0", 0 0, L_0x1dad210; 1 drivers -v0x1b9bc10_0 .net *"_s1", 0 0, L_0x1dad370; 1 drivers -S_0x1b9bcf0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9bf00 .param/l "i" 0 4 54, +C4<011>; -L_0x1dad460/d .functor AND 1, L_0x1dad520, L_0x1dad680, C4<1>, C4<1>; -L_0x1dad460 .delay 1 (30000,30000,30000) L_0x1dad460/d; -v0x1b9bfc0_0 .net *"_s0", 0 0, L_0x1dad520; 1 drivers -v0x1b9c0a0_0 .net *"_s1", 0 0, L_0x1dad680; 1 drivers -S_0x1b9c180 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9c3e0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dad7c0/d .functor AND 1, L_0x1dad880, L_0x1dadaf0, C4<1>, C4<1>; -L_0x1dad7c0 .delay 1 (30000,30000,30000) L_0x1dad7c0/d; -v0x1b9c4a0_0 .net *"_s0", 0 0, L_0x1dad880; 1 drivers -v0x1b9c580_0 .net *"_s1", 0 0, L_0x1dadaf0; 1 drivers -S_0x1b9c660 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9c870 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dadbf0/d .functor AND 1, L_0x1dadc60, L_0x1daddc0, C4<1>, C4<1>; -L_0x1dadbf0 .delay 1 (30000,30000,30000) L_0x1dadbf0/d; -v0x1b9c930_0 .net *"_s0", 0 0, L_0x1dadc60; 1 drivers -v0x1b9ca10_0 .net *"_s1", 0 0, L_0x1daddc0; 1 drivers -S_0x1b9caf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9cd00 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dadf20/d .functor AND 1, L_0x1dadfe0, L_0x1dae140, C4<1>, C4<1>; -L_0x1dadf20 .delay 1 (30000,30000,30000) L_0x1dadf20/d; -v0x1b9cdc0_0 .net *"_s0", 0 0, L_0x1dadfe0; 1 drivers -v0x1b9cea0_0 .net *"_s1", 0 0, L_0x1dae140; 1 drivers -S_0x1b9cf80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1b9acd0; - .timescale -9 -12; -P_0x1b9d190 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dadeb0/d .functor AND 1, L_0x1dae5f0, L_0x1dae7e0, C4<1>, C4<1>; -L_0x1dadeb0 .delay 1 (30000,30000,30000) L_0x1dadeb0/d; -v0x1b9d250_0 .net *"_s0", 0 0, L_0x1dae5f0; 1 drivers -v0x1b9d330_0 .net *"_s1", 0 0, L_0x1dae7e0; 1 drivers -S_0x1b9e0f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1b9aa80; +v0x10300a0_0 .net "A", 7 0, L_0x123fdf0; alias, 1 drivers +v0x10301a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0xffd2d0_0 .net *"_s0", 0 0, L_0x1240180; 1 drivers +v0xffd390_0 .net *"_s12", 0 0, L_0x1240b40; 1 drivers +v0x1030670_0 .net *"_s16", 0 0, L_0x1240ea0; 1 drivers +v0x1030730_0 .net *"_s20", 0 0, L_0x12412d0; 1 drivers +v0x1030810_0 .net *"_s24", 0 0, L_0x1241600; 1 drivers +v0x10308f0_0 .net *"_s28", 0 0, L_0x1241590; 1 drivers +v0x10309d0_0 .net *"_s4", 0 0, L_0x1240520; 1 drivers +v0x1030b40_0 .net *"_s8", 0 0, L_0x1240830; 1 drivers +v0x1030c20_0 .net "out", 7 0, L_0x1241990; alias, 1 drivers +L_0x1240290 .part L_0x123fdf0, 0, 1; +L_0x1240480 .part v0x12010b0_0, 0, 1; +L_0x12405e0 .part L_0x123fdf0, 1, 1; +L_0x1240740 .part v0x12010b0_0, 1, 1; +L_0x12408f0 .part L_0x123fdf0, 2, 1; +L_0x1240a50 .part v0x12010b0_0, 2, 1; +L_0x1240c00 .part L_0x123fdf0, 3, 1; +L_0x1240d60 .part v0x12010b0_0, 3, 1; +L_0x1240f60 .part L_0x123fdf0, 4, 1; +L_0x12411d0 .part v0x12010b0_0, 4, 1; +L_0x1241340 .part L_0x123fdf0, 5, 1; +L_0x12414a0 .part v0x12010b0_0, 5, 1; +L_0x12416c0 .part L_0x123fdf0, 6, 1; +L_0x1241820 .part v0x12010b0_0, 6, 1; +LS_0x1241990_0_0 .concat8 [ 1 1 1 1], L_0x1240180, L_0x1240520, L_0x1240830, L_0x1240b40; +LS_0x1241990_0_4 .concat8 [ 1 1 1 1], L_0x1240ea0, L_0x12412d0, L_0x1241600, L_0x1241590; +L_0x1241990 .concat8 [ 4 4 0 0], LS_0x1241990_0_0, LS_0x1241990_0_4; +L_0x1241d50 .part L_0x123fdf0, 7, 1; +L_0x1241f40 .part v0x12010b0_0, 7, 1; +S_0x102dba0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102ddb0 .param/l "i" 0 4 54, +C4<00>; +L_0x1240180/d .functor AND 1, L_0x1240290, L_0x1240480, C4<1>, C4<1>; +L_0x1240180 .delay 1 (30000,30000,30000) L_0x1240180/d; +v0x102de90_0 .net *"_s0", 0 0, L_0x1240290; 1 drivers +v0x102df70_0 .net *"_s1", 0 0, L_0x1240480; 1 drivers +S_0x102e050 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102e260 .param/l "i" 0 4 54, +C4<01>; +L_0x1240520/d .functor AND 1, L_0x12405e0, L_0x1240740, C4<1>, C4<1>; +L_0x1240520 .delay 1 (30000,30000,30000) L_0x1240520/d; +v0x102e320_0 .net *"_s0", 0 0, L_0x12405e0; 1 drivers +v0x102e400_0 .net *"_s1", 0 0, L_0x1240740; 1 drivers +S_0x102e4e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102e720 .param/l "i" 0 4 54, +C4<010>; +L_0x1240830/d .functor AND 1, L_0x12408f0, L_0x1240a50, C4<1>, C4<1>; +L_0x1240830 .delay 1 (30000,30000,30000) L_0x1240830/d; +v0x102e7c0_0 .net *"_s0", 0 0, L_0x12408f0; 1 drivers +v0x102e8a0_0 .net *"_s1", 0 0, L_0x1240a50; 1 drivers +S_0x102e980 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102eb90 .param/l "i" 0 4 54, +C4<011>; +L_0x1240b40/d .functor AND 1, L_0x1240c00, L_0x1240d60, C4<1>, C4<1>; +L_0x1240b40 .delay 1 (30000,30000,30000) L_0x1240b40/d; +v0x102ec50_0 .net *"_s0", 0 0, L_0x1240c00; 1 drivers +v0x102ed30_0 .net *"_s1", 0 0, L_0x1240d60; 1 drivers +S_0x102ee10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102f070 .param/l "i" 0 4 54, +C4<0100>; +L_0x1240ea0/d .functor AND 1, L_0x1240f60, L_0x12411d0, C4<1>, C4<1>; +L_0x1240ea0 .delay 1 (30000,30000,30000) L_0x1240ea0/d; +v0x102f130_0 .net *"_s0", 0 0, L_0x1240f60; 1 drivers +v0x102f210_0 .net *"_s1", 0 0, L_0x12411d0; 1 drivers +S_0x102f2f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102f500 .param/l "i" 0 4 54, +C4<0101>; +L_0x12412d0/d .functor AND 1, L_0x1241340, L_0x12414a0, C4<1>, C4<1>; +L_0x12412d0 .delay 1 (30000,30000,30000) L_0x12412d0/d; +v0x102f5c0_0 .net *"_s0", 0 0, L_0x1241340; 1 drivers +v0x102f6a0_0 .net *"_s1", 0 0, L_0x12414a0; 1 drivers +S_0x102f780 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102f990 .param/l "i" 0 4 54, +C4<0110>; +L_0x1241600/d .functor AND 1, L_0x12416c0, L_0x1241820, C4<1>, C4<1>; +L_0x1241600 .delay 1 (30000,30000,30000) L_0x1241600/d; +v0x102fa50_0 .net *"_s0", 0 0, L_0x12416c0; 1 drivers +v0x102fb30_0 .net *"_s1", 0 0, L_0x1241820; 1 drivers +S_0x102fc10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x102d960; + .timescale -9 -12; +P_0x102fe20 .param/l "i" 0 4 54, +C4<0111>; +L_0x1241590/d .functor AND 1, L_0x1241d50, L_0x1241f40, C4<1>, C4<1>; +L_0x1241590 .delay 1 (30000,30000,30000) L_0x1241590/d; +v0x102fee0_0 .net *"_s0", 0 0, L_0x1241d50; 1 drivers +v0x102ffc0_0 .net *"_s1", 0 0, L_0x1241f40; 1 drivers +S_0x1030d80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x102d710; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1db0230/d .functor OR 1, L_0x1db02f0, L_0x1db04a0, C4<0>, C4<0>; -L_0x1db0230 .delay 1 (30000,30000,30000) L_0x1db0230/d; -v0x1b9fc40_0 .net *"_s10", 0 0, L_0x1db02f0; 1 drivers -v0x1b9fd20_0 .net *"_s12", 0 0, L_0x1db04a0; 1 drivers -v0x1b9fe00_0 .net "in", 7 0, L_0x1dae230; alias, 1 drivers -v0x1b9fed0_0 .net "ors", 1 0, L_0x1db0050; 1 drivers -v0x1b9ff90_0 .net "out", 0 0, L_0x1db0230; alias, 1 drivers -L_0x1daf420 .part L_0x1dae230, 0, 4; -L_0x1db0050 .concat8 [ 1 1 0 0], L_0x1daf110, L_0x1dafd40; -L_0x1db0190 .part L_0x1dae230, 4, 4; -L_0x1db02f0 .part L_0x1db0050, 0, 1; -L_0x1db04a0 .part L_0x1db0050, 1, 1; -S_0x1b9e2b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1b9e0f0; +L_0x1243990/d .functor OR 1, L_0x1243a50, L_0x1243c00, C4<0>, C4<0>; +L_0x1243990 .delay 1 (30000,30000,30000) L_0x1243990/d; +v0x10328d0_0 .net *"_s10", 0 0, L_0x1243a50; 1 drivers +v0x10329b0_0 .net *"_s12", 0 0, L_0x1243c00; 1 drivers +v0x1032a90_0 .net "in", 7 0, L_0x1241990; alias, 1 drivers +v0x1032b60_0 .net "ors", 1 0, L_0x12437b0; 1 drivers +v0x1032c20_0 .net "out", 0 0, L_0x1243990; alias, 1 drivers +L_0x1242b80 .part L_0x1241990, 0, 4; +L_0x12437b0 .concat8 [ 1 1 0 0], L_0x1242870, L_0x12434a0; +L_0x12438f0 .part L_0x1241990, 4, 4; +L_0x1243a50 .part L_0x12437b0, 0, 1; +L_0x1243c00 .part L_0x12437b0, 1, 1; +S_0x1030f40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1030d80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dae8d0/d .functor OR 1, L_0x1dae990, L_0x1daeaf0, C4<0>, C4<0>; -L_0x1dae8d0 .delay 1 (30000,30000,30000) L_0x1dae8d0/d; -L_0x1daed20/d .functor OR 1, L_0x1daee30, L_0x1daef90, C4<0>, C4<0>; -L_0x1daed20 .delay 1 (30000,30000,30000) L_0x1daed20/d; -L_0x1daf110/d .functor OR 1, L_0x1daf180, L_0x1daf330, C4<0>, C4<0>; -L_0x1daf110 .delay 1 (30000,30000,30000) L_0x1daf110/d; -v0x1b9e500_0 .net *"_s0", 0 0, L_0x1dae8d0; 1 drivers -v0x1b9e600_0 .net *"_s10", 0 0, L_0x1daee30; 1 drivers -v0x1b9e6e0_0 .net *"_s12", 0 0, L_0x1daef90; 1 drivers -v0x1b9e7a0_0 .net *"_s14", 0 0, L_0x1daf180; 1 drivers -v0x1b9e880_0 .net *"_s16", 0 0, L_0x1daf330; 1 drivers -v0x1b9e9b0_0 .net *"_s3", 0 0, L_0x1dae990; 1 drivers -v0x1b9ea90_0 .net *"_s5", 0 0, L_0x1daeaf0; 1 drivers -v0x1b9eb70_0 .net *"_s6", 0 0, L_0x1daed20; 1 drivers -v0x1b9ec50_0 .net "in", 3 0, L_0x1daf420; 1 drivers -v0x1b9edc0_0 .net "ors", 1 0, L_0x1daec30; 1 drivers -v0x1b9eea0_0 .net "out", 0 0, L_0x1daf110; 1 drivers -L_0x1dae990 .part L_0x1daf420, 0, 1; -L_0x1daeaf0 .part L_0x1daf420, 1, 1; -L_0x1daec30 .concat8 [ 1 1 0 0], L_0x1dae8d0, L_0x1daed20; -L_0x1daee30 .part L_0x1daf420, 2, 1; -L_0x1daef90 .part L_0x1daf420, 3, 1; -L_0x1daf180 .part L_0x1daec30, 0, 1; -L_0x1daf330 .part L_0x1daec30, 1, 1; -S_0x1b9efc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1b9e0f0; +L_0x1242030/d .functor OR 1, L_0x12420f0, L_0x1242250, C4<0>, C4<0>; +L_0x1242030 .delay 1 (30000,30000,30000) L_0x1242030/d; +L_0x1242480/d .functor OR 1, L_0x1242590, L_0x12426f0, C4<0>, C4<0>; +L_0x1242480 .delay 1 (30000,30000,30000) L_0x1242480/d; +L_0x1242870/d .functor OR 1, L_0x12428e0, L_0x1242a90, C4<0>, C4<0>; +L_0x1242870 .delay 1 (30000,30000,30000) L_0x1242870/d; +v0x1031190_0 .net *"_s0", 0 0, L_0x1242030; 1 drivers +v0x1031290_0 .net *"_s10", 0 0, L_0x1242590; 1 drivers +v0x1031370_0 .net *"_s12", 0 0, L_0x12426f0; 1 drivers +v0x1031430_0 .net *"_s14", 0 0, L_0x12428e0; 1 drivers +v0x1031510_0 .net *"_s16", 0 0, L_0x1242a90; 1 drivers +v0x1031640_0 .net *"_s3", 0 0, L_0x12420f0; 1 drivers +v0x1031720_0 .net *"_s5", 0 0, L_0x1242250; 1 drivers +v0x1031800_0 .net *"_s6", 0 0, L_0x1242480; 1 drivers +v0x10318e0_0 .net "in", 3 0, L_0x1242b80; 1 drivers +v0x1031a50_0 .net "ors", 1 0, L_0x1242390; 1 drivers +v0x1031b30_0 .net "out", 0 0, L_0x1242870; 1 drivers +L_0x12420f0 .part L_0x1242b80, 0, 1; +L_0x1242250 .part L_0x1242b80, 1, 1; +L_0x1242390 .concat8 [ 1 1 0 0], L_0x1242030, L_0x1242480; +L_0x1242590 .part L_0x1242b80, 2, 1; +L_0x12426f0 .part L_0x1242b80, 3, 1; +L_0x12428e0 .part L_0x1242390, 0, 1; +L_0x1242a90 .part L_0x1242390, 1, 1; +S_0x1031c50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1030d80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1daf550/d .functor OR 1, L_0x1daf5c0, L_0x1daf720, C4<0>, C4<0>; -L_0x1daf550 .delay 1 (30000,30000,30000) L_0x1daf550/d; -L_0x1daf950/d .functor OR 1, L_0x1dafa60, L_0x1dafbc0, C4<0>, C4<0>; -L_0x1daf950 .delay 1 (30000,30000,30000) L_0x1daf950/d; -L_0x1dafd40/d .functor OR 1, L_0x1dafdb0, L_0x1daff60, C4<0>, C4<0>; -L_0x1dafd40 .delay 1 (30000,30000,30000) L_0x1dafd40/d; -v0x1b9f180_0 .net *"_s0", 0 0, L_0x1daf550; 1 drivers -v0x1b9f280_0 .net *"_s10", 0 0, L_0x1dafa60; 1 drivers -v0x1b9f360_0 .net *"_s12", 0 0, L_0x1dafbc0; 1 drivers -v0x1b9f420_0 .net *"_s14", 0 0, L_0x1dafdb0; 1 drivers -v0x1b9f500_0 .net *"_s16", 0 0, L_0x1daff60; 1 drivers -v0x1b9f630_0 .net *"_s3", 0 0, L_0x1daf5c0; 1 drivers -v0x1b9f710_0 .net *"_s5", 0 0, L_0x1daf720; 1 drivers -v0x1b9f7f0_0 .net *"_s6", 0 0, L_0x1daf950; 1 drivers -v0x1b9f8d0_0 .net "in", 3 0, L_0x1db0190; 1 drivers -v0x1b9fa40_0 .net "ors", 1 0, L_0x1daf860; 1 drivers -v0x1b9fb20_0 .net "out", 0 0, L_0x1dafd40; 1 drivers -L_0x1daf5c0 .part L_0x1db0190, 0, 1; -L_0x1daf720 .part L_0x1db0190, 1, 1; -L_0x1daf860 .concat8 [ 1 1 0 0], L_0x1daf550, L_0x1daf950; -L_0x1dafa60 .part L_0x1db0190, 2, 1; -L_0x1dafbc0 .part L_0x1db0190, 3, 1; -L_0x1dafdb0 .part L_0x1daf860, 0, 1; -L_0x1daff60 .part L_0x1daf860, 1, 1; -S_0x1ba0430 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b93bb0; +L_0x1242cb0/d .functor OR 1, L_0x1242d20, L_0x1242e80, C4<0>, C4<0>; +L_0x1242cb0 .delay 1 (30000,30000,30000) L_0x1242cb0/d; +L_0x12430b0/d .functor OR 1, L_0x12431c0, L_0x1243320, C4<0>, C4<0>; +L_0x12430b0 .delay 1 (30000,30000,30000) L_0x12430b0/d; +L_0x12434a0/d .functor OR 1, L_0x1243510, L_0x12436c0, C4<0>, C4<0>; +L_0x12434a0 .delay 1 (30000,30000,30000) L_0x12434a0/d; +v0x1031e10_0 .net *"_s0", 0 0, L_0x1242cb0; 1 drivers +v0x1031f10_0 .net *"_s10", 0 0, L_0x12431c0; 1 drivers +v0x1031ff0_0 .net *"_s12", 0 0, L_0x1243320; 1 drivers +v0x10320b0_0 .net *"_s14", 0 0, L_0x1243510; 1 drivers +v0x1032190_0 .net *"_s16", 0 0, L_0x12436c0; 1 drivers +v0x10322c0_0 .net *"_s3", 0 0, L_0x1242d20; 1 drivers +v0x10323a0_0 .net *"_s5", 0 0, L_0x1242e80; 1 drivers +v0x1032480_0 .net *"_s6", 0 0, L_0x12430b0; 1 drivers +v0x1032560_0 .net "in", 3 0, L_0x12438f0; 1 drivers +v0x10326d0_0 .net "ors", 1 0, L_0x1242fc0; 1 drivers +v0x10327b0_0 .net "out", 0 0, L_0x12434a0; 1 drivers +L_0x1242d20 .part L_0x12438f0, 0, 1; +L_0x1242e80 .part L_0x12438f0, 1, 1; +L_0x1242fc0 .concat8 [ 1 1 0 0], L_0x1242cb0, L_0x12430b0; +L_0x12431c0 .part L_0x12438f0, 2, 1; +L_0x1243320 .part L_0x12438f0, 3, 1; +L_0x1243510 .part L_0x1242fc0, 0, 1; +L_0x12436c0 .part L_0x1242fc0, 1, 1; +S_0x10330c0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1026840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -3868,80 +3878,80 @@ S_0x1ba0430 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1b93bb0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1daba80/d .functor XNOR 1, L_0x1db40d0, L_0x1db4340, C4<0>, C4<0>; -L_0x1daba80 .delay 1 (20000,20000,20000) L_0x1daba80/d; -L_0x1dabcf0/d .functor AND 1, L_0x1db40d0, L_0x1daa970, C4<1>, C4<1>; -L_0x1dabcf0 .delay 1 (30000,30000,30000) L_0x1dabcf0/d; -L_0x1dabd60/d .functor AND 1, L_0x1daba80, L_0x1daa6d0, C4<1>, C4<1>; -L_0x1dabd60 .delay 1 (30000,30000,30000) L_0x1dabd60/d; -L_0x1dabec0/d .functor OR 1, L_0x1dabd60, L_0x1dabcf0, C4<0>, C4<0>; -L_0x1dabec0 .delay 1 (30000,30000,30000) L_0x1dabec0/d; -v0x1ba06e0_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers -v0x1ba07d0_0 .net "a_", 0 0, L_0x1daa810; alias, 1 drivers -v0x1ba0890_0 .net "b", 0 0, L_0x1db4340; alias, 1 drivers -v0x1ba0980_0 .net "b_", 0 0, L_0x1daa970; alias, 1 drivers -v0x1ba0a20_0 .net "carryin", 0 0, L_0x1daa6d0; alias, 1 drivers -v0x1ba0b60_0 .net "eq", 0 0, L_0x1daba80; 1 drivers -v0x1ba0c20_0 .net "lt", 0 0, L_0x1dabcf0; 1 drivers -v0x1ba0ce0_0 .net "out", 0 0, L_0x1dabec0; 1 drivers -v0x1ba0da0_0 .net "w0", 0 0, L_0x1dabd60; 1 drivers -S_0x1ba0ff0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1b93bb0; +L_0x123f160/d .functor XNOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; +L_0x123f160 .delay 1 (20000,20000,20000) L_0x123f160/d; +L_0x123f3d0/d .functor AND 1, L_0x1247830, L_0x123e110, C4<1>, C4<1>; +L_0x123f3d0 .delay 1 (30000,30000,30000) L_0x123f3d0/d; +L_0x123f440/d .functor AND 1, L_0x123f160, L_0x123de70, C4<1>, C4<1>; +L_0x123f440 .delay 1 (30000,30000,30000) L_0x123f440/d; +L_0x123f5a0/d .functor OR 1, L_0x123f440, L_0x123f3d0, C4<0>, C4<0>; +L_0x123f5a0 .delay 1 (30000,30000,30000) L_0x123f5a0/d; +v0x1033370_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers +v0x1033460_0 .net "a_", 0 0, L_0x123dfb0; alias, 1 drivers +v0x1033520_0 .net "b", 0 0, L_0x1247aa0; alias, 1 drivers +v0x1033610_0 .net "b_", 0 0, L_0x123e110; alias, 1 drivers +v0x10336b0_0 .net "carryin", 0 0, L_0x123de70; alias, 1 drivers +v0x10337f0_0 .net "eq", 0 0, L_0x123f160; 1 drivers +v0x10338b0_0 .net "lt", 0 0, L_0x123f3d0; 1 drivers +v0x1033970_0 .net "out", 0 0, L_0x123f5a0; 1 drivers +v0x1033a30_0 .net "w0", 0 0, L_0x123f440; 1 drivers +S_0x1033c80 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1026840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dab860/d .functor OR 1, L_0x1dab360, L_0x1ba2250, C4<0>, C4<0>; -L_0x1dab860 .delay 1 (30000,30000,30000) L_0x1dab860/d; -v0x1ba1de0_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers -v0x1ba1f30_0 .net "b", 0 0, L_0x1daa970; alias, 1 drivers -v0x1ba1ff0_0 .net "c1", 0 0, L_0x1dab360; 1 drivers -v0x1ba2090_0 .net "c2", 0 0, L_0x1ba2250; 1 drivers -v0x1ba2160_0 .net "carryin", 0 0, L_0x1daa6d0; alias, 1 drivers -v0x1ba22e0_0 .net "carryout", 0 0, L_0x1dab860; 1 drivers -v0x1ba2380_0 .net "s1", 0 0, L_0x1dab2a0; 1 drivers -v0x1ba2420_0 .net "sum", 0 0, L_0x1dab4c0; 1 drivers -S_0x1ba1240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ba0ff0; +L_0x123ef40/d .functor OR 1, L_0x123ea90, L_0x1034ee0, C4<0>, C4<0>; +L_0x123ef40 .delay 1 (30000,30000,30000) L_0x123ef40/d; +v0x1034a70_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers +v0x1034bc0_0 .net "b", 0 0, L_0x123e110; alias, 1 drivers +v0x1034c80_0 .net "c1", 0 0, L_0x123ea90; 1 drivers +v0x1034d20_0 .net "c2", 0 0, L_0x1034ee0; 1 drivers +v0x1034df0_0 .net "carryin", 0 0, L_0x123de70; alias, 1 drivers +v0x1034f70_0 .net "carryout", 0 0, L_0x123ef40; 1 drivers +v0x1035010_0 .net "s1", 0 0, L_0x123e9d0; 1 drivers +v0x10350b0_0 .net "sum", 0 0, L_0x123ebf0; 1 drivers +S_0x1033ed0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1033c80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dab2a0/d .functor XOR 1, L_0x1db40d0, L_0x1daa970, C4<0>, C4<0>; -L_0x1dab2a0 .delay 1 (30000,30000,30000) L_0x1dab2a0/d; -L_0x1dab360/d .functor AND 1, L_0x1db40d0, L_0x1daa970, C4<1>, C4<1>; -L_0x1dab360 .delay 1 (30000,30000,30000) L_0x1dab360/d; -v0x1ba14a0_0 .net "a", 0 0, L_0x1db40d0; alias, 1 drivers -v0x1ba1560_0 .net "b", 0 0, L_0x1daa970; alias, 1 drivers -v0x1ba1620_0 .net "carryout", 0 0, L_0x1dab360; alias, 1 drivers -v0x1ba16c0_0 .net "sum", 0 0, L_0x1dab2a0; alias, 1 drivers -S_0x1ba17f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ba0ff0; +L_0x123e9d0/d .functor XOR 1, L_0x1247830, L_0x123e110, C4<0>, C4<0>; +L_0x123e9d0 .delay 1 (30000,30000,30000) L_0x123e9d0/d; +L_0x123ea90/d .functor AND 1, L_0x1247830, L_0x123e110, C4<1>, C4<1>; +L_0x123ea90 .delay 1 (30000,30000,30000) L_0x123ea90/d; +v0x1034130_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers +v0x10341f0_0 .net "b", 0 0, L_0x123e110; alias, 1 drivers +v0x10342b0_0 .net "carryout", 0 0, L_0x123ea90; alias, 1 drivers +v0x1034350_0 .net "sum", 0 0, L_0x123e9d0; alias, 1 drivers +S_0x1034480 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1033c80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dab4c0/d .functor XOR 1, L_0x1dab2a0, L_0x1daa6d0, C4<0>, C4<0>; -L_0x1dab4c0 .delay 1 (30000,30000,30000) L_0x1dab4c0/d; -L_0x1ba2250/d .functor AND 1, L_0x1dab2a0, L_0x1daa6d0, C4<1>, C4<1>; -L_0x1ba2250 .delay 1 (30000,30000,30000) L_0x1ba2250/d; -v0x1ba1a50_0 .net "a", 0 0, L_0x1dab2a0; alias, 1 drivers -v0x1ba1b20_0 .net "b", 0 0, L_0x1daa6d0; alias, 1 drivers -v0x1ba1bc0_0 .net "carryout", 0 0, L_0x1ba2250; alias, 1 drivers -v0x1ba1c90_0 .net "sum", 0 0, L_0x1dab4c0; alias, 1 drivers -S_0x1ba3840 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1b938e0; - .timescale -9 -12; -L_0x7f72592da6d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1db4170/d .functor OR 1, L_0x7f72592da6d8, L_0x7f72592da720, C4<0>, C4<0>; -L_0x1db4170 .delay 1 (30000,30000,30000) L_0x1db4170/d; -v0x1ba3a30_0 .net/2u *"_s0", 0 0, L_0x7f72592da6d8; 1 drivers -v0x1ba3b10_0 .net/2u *"_s2", 0 0, L_0x7f72592da720; 1 drivers -S_0x1ba3bf0 .scope generate, "alu_slices[7]" "alu_slices[7]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1ba3e00 .param/l "i" 0 3 37, +C4<0111>; -S_0x1ba3ec0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ba3bf0; +L_0x123ebf0/d .functor XOR 1, L_0x123e9d0, L_0x123de70, C4<0>, C4<0>; +L_0x123ebf0 .delay 1 (30000,30000,30000) L_0x123ebf0/d; +L_0x1034ee0/d .functor AND 1, L_0x123e9d0, L_0x123de70, C4<1>, C4<1>; +L_0x1034ee0 .delay 1 (30000,30000,30000) L_0x1034ee0/d; +v0x10346e0_0 .net "a", 0 0, L_0x123e9d0; alias, 1 drivers +v0x10347b0_0 .net "b", 0 0, L_0x123de70; alias, 1 drivers +v0x1034850_0 .net "carryout", 0 0, L_0x1034ee0; alias, 1 drivers +v0x1034920_0 .net "sum", 0 0, L_0x123ebf0; alias, 1 drivers +S_0x10364d0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1026570; + .timescale -9 -12; +L_0x2b0ab3d056d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12478d0/d .functor OR 1, L_0x2b0ab3d056d8, L_0x2b0ab3d05720, C4<0>, C4<0>; +L_0x12478d0 .delay 1 (30000,30000,30000) L_0x12478d0/d; +v0x10366c0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d056d8; 1 drivers +v0x10367a0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05720; 1 drivers +S_0x1036880 .scope generate, "alu_slices[7]" "alu_slices[7]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1036a90 .param/l "i" 0 3 41, +C4<0111>; +S_0x1036b50 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1036880; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -3950,445 +3960,445 @@ S_0x1ba3ec0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ba3bf0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1db4640/d .functor NOT 1, L_0x1dbde70, C4<0>, C4<0>, C4<0>; -L_0x1db4640 .delay 1 (10000,10000,10000) L_0x1db4640/d; -L_0x1db4750/d .functor NOT 1, L_0x1db44f0, C4<0>, C4<0>, C4<0>; -L_0x1db4750 .delay 1 (10000,10000,10000) L_0x1db4750/d; -L_0x1db57a0/d .functor XOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; -L_0x1db57a0 .delay 1 (30000,30000,30000) L_0x1db57a0/d; -L_0x7f72592da768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da7b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1db5e50/d .functor OR 1, L_0x7f72592da768, L_0x7f72592da7b0, C4<0>, C4<0>; -L_0x1db5e50 .delay 1 (30000,30000,30000) L_0x1db5e50/d; -L_0x1db6050/d .functor AND 1, L_0x1dbde70, L_0x1db44f0, C4<1>, C4<1>; -L_0x1db6050 .delay 1 (30000,30000,30000) L_0x1db6050/d; -L_0x1db6110/d .functor NAND 1, L_0x1dbde70, L_0x1db44f0, C4<1>, C4<1>; -L_0x1db6110 .delay 1 (20000,20000,20000) L_0x1db6110/d; -L_0x1db6270/d .functor XOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; -L_0x1db6270 .delay 1 (20000,20000,20000) L_0x1db6270/d; -L_0x1db6720/d .functor OR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; -L_0x1db6720 .delay 1 (30000,30000,30000) L_0x1db6720/d; -L_0x1dbdd70/d .functor NOT 1, L_0x1db9ef0, C4<0>, C4<0>, C4<0>; -L_0x1dbdd70 .delay 1 (10000,10000,10000) L_0x1dbdd70/d; -v0x1bb2600_0 .net "A", 0 0, L_0x1dbde70; 1 drivers -v0x1bb26c0_0 .net "A_", 0 0, L_0x1db4640; 1 drivers -v0x1bb2780_0 .net "B", 0 0, L_0x1db44f0; 1 drivers -v0x1bb2850_0 .net "B_", 0 0, L_0x1db4750; 1 drivers -v0x1bb28f0_0 .net *"_s12", 0 0, L_0x1db5e50; 1 drivers -v0x1bb29e0_0 .net/2s *"_s14", 0 0, L_0x7f72592da768; 1 drivers -v0x1bb2aa0_0 .net/2s *"_s16", 0 0, L_0x7f72592da7b0; 1 drivers -v0x1bb2b80_0 .net *"_s18", 0 0, L_0x1db6050; 1 drivers -v0x1bb2c60_0 .net *"_s20", 0 0, L_0x1db6110; 1 drivers -v0x1bb2dd0_0 .net *"_s22", 0 0, L_0x1db6270; 1 drivers -v0x1bb2eb0_0 .net *"_s24", 0 0, L_0x1db6720; 1 drivers -o0x7f72593667f8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1bb2f90_0 name=_s30 -o0x7f7259366828 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1bb3070_0 name=_s32 -v0x1bb3150_0 .net *"_s8", 0 0, L_0x1db57a0; 1 drivers -v0x1bb3230_0 .net "carryin", 0 0, L_0x1dbe090; 1 drivers -v0x1bb32d0_0 .net "carryout", 0 0, L_0x1dbda10; 1 drivers -v0x1bb3370_0 .net "carryouts", 7 0, L_0x1ebf6a0; 1 drivers -v0x1bb3520_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bb35c0_0 .net "result", 0 0, L_0x1db9ef0; 1 drivers -v0x1bb36b0_0 .net "results", 7 0, L_0x1db64f0; 1 drivers -v0x1bb37c0_0 .net "zero", 0 0, L_0x1dbdd70; 1 drivers -LS_0x1db64f0_0_0 .concat8 [ 1 1 1 1], L_0x1db4c70, L_0x1db52a0, L_0x1db57a0, L_0x1db5e50; -LS_0x1db64f0_0_4 .concat8 [ 1 1 1 1], L_0x1db6050, L_0x1db6110, L_0x1db6270, L_0x1db6720; -L_0x1db64f0 .concat8 [ 4 4 0 0], LS_0x1db64f0_0_0, LS_0x1db64f0_0_4; -LS_0x1ebf6a0_0_0 .concat [ 1 1 1 1], L_0x1db4f20, L_0x1db5640, o0x7f72593667f8, L_0x1db5ca0; -LS_0x1ebf6a0_0_4 .concat [ 4 0 0 0], o0x7f7259366828; -L_0x1ebf6a0 .concat [ 4 4 0 0], LS_0x1ebf6a0_0_0, LS_0x1ebf6a0_0_4; -S_0x1ba4140 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1ba3ec0; +L_0x1247da0/d .functor NOT 1, L_0x12515b0, C4<0>, C4<0>, C4<0>; +L_0x1247da0 .delay 1 (10000,10000,10000) L_0x1247da0/d; +L_0x1247eb0/d .functor NOT 1, L_0x1247c50, C4<0>, C4<0>, C4<0>; +L_0x1247eb0 .delay 1 (10000,10000,10000) L_0x1247eb0/d; +L_0x1248f00/d .functor XOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; +L_0x1248f00 .delay 1 (30000,30000,30000) L_0x1248f00/d; +L_0x2b0ab3d05768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d057b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12495b0/d .functor OR 1, L_0x2b0ab3d05768, L_0x2b0ab3d057b0, C4<0>, C4<0>; +L_0x12495b0 .delay 1 (30000,30000,30000) L_0x12495b0/d; +L_0x12497b0/d .functor AND 1, L_0x12515b0, L_0x1247c50, C4<1>, C4<1>; +L_0x12497b0 .delay 1 (30000,30000,30000) L_0x12497b0/d; +L_0x1249870/d .functor NAND 1, L_0x12515b0, L_0x1247c50, C4<1>, C4<1>; +L_0x1249870 .delay 1 (20000,20000,20000) L_0x1249870/d; +L_0x12499d0/d .functor XOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; +L_0x12499d0 .delay 1 (20000,20000,20000) L_0x12499d0/d; +L_0x1249e80/d .functor OR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; +L_0x1249e80 .delay 1 (30000,30000,30000) L_0x1249e80/d; +L_0x12514b0/d .functor NOT 1, L_0x124d710, C4<0>, C4<0>, C4<0>; +L_0x12514b0 .delay 1 (10000,10000,10000) L_0x12514b0/d; +v0x1045280_0 .net "A", 0 0, L_0x12515b0; 1 drivers +v0x1045340_0 .net "A_", 0 0, L_0x1247da0; 1 drivers +v0x1045400_0 .net "B", 0 0, L_0x1247c50; 1 drivers +v0x10454d0_0 .net "B_", 0 0, L_0x1247eb0; 1 drivers +v0x1045570_0 .net *"_s12", 0 0, L_0x12495b0; 1 drivers +v0x1045660_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05768; 1 drivers +v0x1045720_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d057b0; 1 drivers +v0x1045800_0 .net *"_s18", 0 0, L_0x12497b0; 1 drivers +v0x10458e0_0 .net *"_s20", 0 0, L_0x1249870; 1 drivers +v0x1045a50_0 .net *"_s22", 0 0, L_0x12499d0; 1 drivers +v0x1045b30_0 .net *"_s24", 0 0, L_0x1249e80; 1 drivers +o0x2b0ab3cb57f8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1045c10_0 name=_s30 +o0x2b0ab3cb5828 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1045cf0_0 name=_s32 +v0x1045dd0_0 .net *"_s8", 0 0, L_0x1248f00; 1 drivers +v0x1045eb0_0 .net "carryin", 0 0, L_0x12517d0; 1 drivers +v0x1045f50_0 .net "carryout", 0 0, L_0x1251150; 1 drivers +v0x1045ff0_0 .net "carryouts", 7 0, L_0x1353a50; 1 drivers +v0x10461a0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1046240_0 .net "result", 0 0, L_0x124d710; 1 drivers +v0x1046330_0 .net "results", 7 0, L_0x1249c50; 1 drivers +v0x1046440_0 .net "zero", 0 0, L_0x12514b0; 1 drivers +LS_0x1249c50_0_0 .concat8 [ 1 1 1 1], L_0x12483d0, L_0x1248a00, L_0x1248f00, L_0x12495b0; +LS_0x1249c50_0_4 .concat8 [ 1 1 1 1], L_0x12497b0, L_0x1249870, L_0x12499d0, L_0x1249e80; +L_0x1249c50 .concat8 [ 4 4 0 0], LS_0x1249c50_0_0, LS_0x1249c50_0_4; +LS_0x1353a50_0_0 .concat [ 1 1 1 1], L_0x1248680, L_0x1248da0, o0x2b0ab3cb57f8, L_0x1249400; +LS_0x1353a50_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb5828; +L_0x1353a50 .concat [ 4 4 0 0], LS_0x1353a50_0_0, LS_0x1353a50_0_4; +S_0x1036dd0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1036b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1db4f20/d .functor OR 1, L_0x1db4a00, L_0x1db4dc0, C4<0>, C4<0>; -L_0x1db4f20 .delay 1 (30000,30000,30000) L_0x1db4f20/d; -v0x1ba4f70_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers -v0x1ba5030_0 .net "b", 0 0, L_0x1db44f0; alias, 1 drivers -v0x1ba5100_0 .net "c1", 0 0, L_0x1db4a00; 1 drivers -v0x1ba5200_0 .net "c2", 0 0, L_0x1db4dc0; 1 drivers -v0x1ba52d0_0 .net "carryin", 0 0, L_0x1dbe090; alias, 1 drivers -v0x1ba53c0_0 .net "carryout", 0 0, L_0x1db4f20; 1 drivers -v0x1ba5460_0 .net "s1", 0 0, L_0x1db4940; 1 drivers -v0x1ba5550_0 .net "sum", 0 0, L_0x1db4c70; 1 drivers -S_0x1ba43b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ba4140; +L_0x1248680/d .functor OR 1, L_0x1248160, L_0x1248520, C4<0>, C4<0>; +L_0x1248680 .delay 1 (30000,30000,30000) L_0x1248680/d; +v0x1037c00_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers +v0x1037cc0_0 .net "b", 0 0, L_0x1247c50; alias, 1 drivers +v0x1037d90_0 .net "c1", 0 0, L_0x1248160; 1 drivers +v0x1037e90_0 .net "c2", 0 0, L_0x1248520; 1 drivers +v0x1037f60_0 .net "carryin", 0 0, L_0x12517d0; alias, 1 drivers +v0x1038050_0 .net "carryout", 0 0, L_0x1248680; 1 drivers +v0x10380f0_0 .net "s1", 0 0, L_0x12480a0; 1 drivers +v0x10381e0_0 .net "sum", 0 0, L_0x12483d0; 1 drivers +S_0x1037040 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1036dd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1db4940/d .functor XOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; -L_0x1db4940 .delay 1 (30000,30000,30000) L_0x1db4940/d; -L_0x1db4a00/d .functor AND 1, L_0x1dbde70, L_0x1db44f0, C4<1>, C4<1>; -L_0x1db4a00 .delay 1 (30000,30000,30000) L_0x1db4a00/d; -v0x1ba4610_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers -v0x1ba46f0_0 .net "b", 0 0, L_0x1db44f0; alias, 1 drivers -v0x1ba47b0_0 .net "carryout", 0 0, L_0x1db4a00; alias, 1 drivers -v0x1ba4850_0 .net "sum", 0 0, L_0x1db4940; alias, 1 drivers -S_0x1ba4990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ba4140; +L_0x12480a0/d .functor XOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; +L_0x12480a0 .delay 1 (30000,30000,30000) L_0x12480a0/d; +L_0x1248160/d .functor AND 1, L_0x12515b0, L_0x1247c50, C4<1>, C4<1>; +L_0x1248160 .delay 1 (30000,30000,30000) L_0x1248160/d; +v0x10372a0_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers +v0x1037380_0 .net "b", 0 0, L_0x1247c50; alias, 1 drivers +v0x1037440_0 .net "carryout", 0 0, L_0x1248160; alias, 1 drivers +v0x10374e0_0 .net "sum", 0 0, L_0x12480a0; alias, 1 drivers +S_0x1037620 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1036dd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1db4c70/d .functor XOR 1, L_0x1db4940, L_0x1dbe090, C4<0>, C4<0>; -L_0x1db4c70 .delay 1 (30000,30000,30000) L_0x1db4c70/d; -L_0x1db4dc0/d .functor AND 1, L_0x1db4940, L_0x1dbe090, C4<1>, C4<1>; -L_0x1db4dc0 .delay 1 (30000,30000,30000) L_0x1db4dc0/d; -v0x1ba4bf0_0 .net "a", 0 0, L_0x1db4940; alias, 1 drivers -v0x1ba4c90_0 .net "b", 0 0, L_0x1dbe090; alias, 1 drivers -v0x1ba4d30_0 .net "carryout", 0 0, L_0x1db4dc0; alias, 1 drivers -v0x1ba4e00_0 .net "sum", 0 0, L_0x1db4c70; alias, 1 drivers -S_0x1ba5620 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1ba3ec0; +L_0x12483d0/d .functor XOR 1, L_0x12480a0, L_0x12517d0, C4<0>, C4<0>; +L_0x12483d0 .delay 1 (30000,30000,30000) L_0x12483d0/d; +L_0x1248520/d .functor AND 1, L_0x12480a0, L_0x12517d0, C4<1>, C4<1>; +L_0x1248520 .delay 1 (30000,30000,30000) L_0x1248520/d; +v0x1037880_0 .net "a", 0 0, L_0x12480a0; alias, 1 drivers +v0x1037920_0 .net "b", 0 0, L_0x12517d0; alias, 1 drivers +v0x10379c0_0 .net "carryout", 0 0, L_0x1248520; alias, 1 drivers +v0x1037a90_0 .net "sum", 0 0, L_0x12483d0; alias, 1 drivers +S_0x10382b0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1036b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1baaa20_0 .net "ands", 7 0, L_0x1dbba10; 1 drivers -v0x1baab30_0 .net "in", 7 0, L_0x1ebf6a0; alias, 1 drivers -v0x1baabf0_0 .net "out", 0 0, L_0x1dbda10; alias, 1 drivers -v0x1baacc0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1ba5840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ba5620; +v0x103d6a0_0 .net "ands", 7 0, L_0x124f150; 1 drivers +v0x103d7b0_0 .net "in", 7 0, L_0x1353a50; alias, 1 drivers +v0x103d870_0 .net "out", 0 0, L_0x1251150; alias, 1 drivers +v0x103d940_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10384d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10382b0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1ba7f70_0 .net "A", 7 0, L_0x1ebf6a0; alias, 1 drivers -v0x1ba8070_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ba8130_0 .net *"_s0", 0 0, L_0x1dba250; 1 drivers -v0x1ba81f0_0 .net *"_s12", 0 0, L_0x1dbabc0; 1 drivers -v0x1ba82d0_0 .net *"_s16", 0 0, L_0x1dbaf20; 1 drivers -v0x1ba8400_0 .net *"_s20", 0 0, L_0x1dbb290; 1 drivers -v0x1ba84e0_0 .net *"_s24", 0 0, L_0x1dbb680; 1 drivers -v0x1ba85c0_0 .net *"_s28", 0 0, L_0x1dbb610; 1 drivers -v0x1ba86a0_0 .net *"_s4", 0 0, L_0x1dba560; 1 drivers -v0x1ba8810_0 .net *"_s8", 0 0, L_0x1dba8b0; 1 drivers -v0x1ba88f0_0 .net "out", 7 0, L_0x1dbba10; alias, 1 drivers -L_0x1dba310 .part L_0x1ebf6a0, 0, 1; -L_0x1dba470 .part v0x1d6daa0_0, 0, 1; -L_0x1dba620 .part L_0x1ebf6a0, 1, 1; -L_0x1dba810 .part v0x1d6daa0_0, 1, 1; -L_0x1dba970 .part L_0x1ebf6a0, 2, 1; -L_0x1dbaad0 .part v0x1d6daa0_0, 2, 1; -L_0x1dbac80 .part L_0x1ebf6a0, 3, 1; -L_0x1dbade0 .part v0x1d6daa0_0, 3, 1; -L_0x1dbafe0 .part L_0x1ebf6a0, 4, 1; -L_0x1dbb140 .part v0x1d6daa0_0, 4, 1; -L_0x1dbb300 .part L_0x1ebf6a0, 5, 1; -L_0x1dbb570 .part v0x1d6daa0_0, 5, 1; -L_0x1dbb740 .part L_0x1ebf6a0, 6, 1; -L_0x1dbb8a0 .part v0x1d6daa0_0, 6, 1; -LS_0x1dbba10_0_0 .concat8 [ 1 1 1 1], L_0x1dba250, L_0x1dba560, L_0x1dba8b0, L_0x1dbabc0; -LS_0x1dbba10_0_4 .concat8 [ 1 1 1 1], L_0x1dbaf20, L_0x1dbb290, L_0x1dbb680, L_0x1dbb610; -L_0x1dbba10 .concat8 [ 4 4 0 0], LS_0x1dbba10_0_0, LS_0x1dbba10_0_4; -L_0x1dbbdd0 .part L_0x1ebf6a0, 7, 1; -L_0x1dbbfc0 .part v0x1d6daa0_0, 7, 1; -S_0x1ba5aa0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba5cb0 .param/l "i" 0 4 54, +C4<00>; -L_0x1dba250/d .functor AND 1, L_0x1dba310, L_0x1dba470, C4<1>, C4<1>; -L_0x1dba250 .delay 1 (30000,30000,30000) L_0x1dba250/d; -v0x1ba5d90_0 .net *"_s0", 0 0, L_0x1dba310; 1 drivers -v0x1ba5e70_0 .net *"_s1", 0 0, L_0x1dba470; 1 drivers -S_0x1ba5f50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba6160 .param/l "i" 0 4 54, +C4<01>; -L_0x1dba560/d .functor AND 1, L_0x1dba620, L_0x1dba810, C4<1>, C4<1>; -L_0x1dba560 .delay 1 (30000,30000,30000) L_0x1dba560/d; -v0x1ba6220_0 .net *"_s0", 0 0, L_0x1dba620; 1 drivers -v0x1ba6300_0 .net *"_s1", 0 0, L_0x1dba810; 1 drivers -S_0x1ba63e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba65f0 .param/l "i" 0 4 54, +C4<010>; -L_0x1dba8b0/d .functor AND 1, L_0x1dba970, L_0x1dbaad0, C4<1>, C4<1>; -L_0x1dba8b0 .delay 1 (30000,30000,30000) L_0x1dba8b0/d; -v0x1ba6690_0 .net *"_s0", 0 0, L_0x1dba970; 1 drivers -v0x1ba6770_0 .net *"_s1", 0 0, L_0x1dbaad0; 1 drivers -S_0x1ba6850 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba6a60 .param/l "i" 0 4 54, +C4<011>; -L_0x1dbabc0/d .functor AND 1, L_0x1dbac80, L_0x1dbade0, C4<1>, C4<1>; -L_0x1dbabc0 .delay 1 (30000,30000,30000) L_0x1dbabc0/d; -v0x1ba6b20_0 .net *"_s0", 0 0, L_0x1dbac80; 1 drivers -v0x1ba6c00_0 .net *"_s1", 0 0, L_0x1dbade0; 1 drivers -S_0x1ba6ce0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba6f40 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dbaf20/d .functor AND 1, L_0x1dbafe0, L_0x1dbb140, C4<1>, C4<1>; -L_0x1dbaf20 .delay 1 (30000,30000,30000) L_0x1dbaf20/d; -v0x1ba7000_0 .net *"_s0", 0 0, L_0x1dbafe0; 1 drivers -v0x1ba70e0_0 .net *"_s1", 0 0, L_0x1dbb140; 1 drivers -S_0x1ba71c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba73d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dbb290/d .functor AND 1, L_0x1dbb300, L_0x1dbb570, C4<1>, C4<1>; -L_0x1dbb290 .delay 1 (30000,30000,30000) L_0x1dbb290/d; -v0x1ba7490_0 .net *"_s0", 0 0, L_0x1dbb300; 1 drivers -v0x1ba7570_0 .net *"_s1", 0 0, L_0x1dbb570; 1 drivers -S_0x1ba7650 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba7860 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dbb680/d .functor AND 1, L_0x1dbb740, L_0x1dbb8a0, C4<1>, C4<1>; -L_0x1dbb680 .delay 1 (30000,30000,30000) L_0x1dbb680/d; -v0x1ba7920_0 .net *"_s0", 0 0, L_0x1dbb740; 1 drivers -v0x1ba7a00_0 .net *"_s1", 0 0, L_0x1dbb8a0; 1 drivers -S_0x1ba7ae0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ba5840; - .timescale -9 -12; -P_0x1ba7cf0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dbb610/d .functor AND 1, L_0x1dbbdd0, L_0x1dbbfc0, C4<1>, C4<1>; -L_0x1dbb610 .delay 1 (30000,30000,30000) L_0x1dbb610/d; -v0x1ba7db0_0 .net *"_s0", 0 0, L_0x1dbbdd0; 1 drivers -v0x1ba7e90_0 .net *"_s1", 0 0, L_0x1dbbfc0; 1 drivers -S_0x1ba8a50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ba5620; +v0x103ac00_0 .net "A", 7 0, L_0x1353a50; alias, 1 drivers +v0x103ad00_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x103adc0_0 .net *"_s0", 0 0, L_0x124da70; 1 drivers +v0x103ae80_0 .net *"_s12", 0 0, L_0x124e3e0; 1 drivers +v0x103af60_0 .net *"_s16", 0 0, L_0x124e740; 1 drivers +v0x103b090_0 .net *"_s20", 0 0, L_0x124ea50; 1 drivers +v0x103b170_0 .net *"_s24", 0 0, L_0x124ee40; 1 drivers +v0x103b250_0 .net *"_s28", 0 0, L_0x124edd0; 1 drivers +v0x103b330_0 .net *"_s4", 0 0, L_0x124dd80; 1 drivers +v0x103b4a0_0 .net *"_s8", 0 0, L_0x124e0d0; 1 drivers +v0x103b580_0 .net "out", 7 0, L_0x124f150; alias, 1 drivers +L_0x124db30 .part L_0x1353a50, 0, 1; +L_0x124dc90 .part v0x12010b0_0, 0, 1; +L_0x124de40 .part L_0x1353a50, 1, 1; +L_0x124e030 .part v0x12010b0_0, 1, 1; +L_0x124e190 .part L_0x1353a50, 2, 1; +L_0x124e2f0 .part v0x12010b0_0, 2, 1; +L_0x124e4a0 .part L_0x1353a50, 3, 1; +L_0x124e600 .part v0x12010b0_0, 3, 1; +L_0x124e800 .part L_0x1353a50, 4, 1; +L_0x124e960 .part v0x12010b0_0, 4, 1; +L_0x124eac0 .part L_0x1353a50, 5, 1; +L_0x124ed30 .part v0x12010b0_0, 5, 1; +L_0x124ef00 .part L_0x1353a50, 6, 1; +L_0x124f060 .part v0x12010b0_0, 6, 1; +LS_0x124f150_0_0 .concat8 [ 1 1 1 1], L_0x124da70, L_0x124dd80, L_0x124e0d0, L_0x124e3e0; +LS_0x124f150_0_4 .concat8 [ 1 1 1 1], L_0x124e740, L_0x124ea50, L_0x124ee40, L_0x124edd0; +L_0x124f150 .concat8 [ 4 4 0 0], LS_0x124f150_0_0, LS_0x124f150_0_4; +L_0x124f510 .part L_0x1353a50, 7, 1; +L_0x124f700 .part v0x12010b0_0, 7, 1; +S_0x1038730 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x1038940 .param/l "i" 0 4 54, +C4<00>; +L_0x124da70/d .functor AND 1, L_0x124db30, L_0x124dc90, C4<1>, C4<1>; +L_0x124da70 .delay 1 (30000,30000,30000) L_0x124da70/d; +v0x1038a20_0 .net *"_s0", 0 0, L_0x124db30; 1 drivers +v0x1038b00_0 .net *"_s1", 0 0, L_0x124dc90; 1 drivers +S_0x1038be0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x1038df0 .param/l "i" 0 4 54, +C4<01>; +L_0x124dd80/d .functor AND 1, L_0x124de40, L_0x124e030, C4<1>, C4<1>; +L_0x124dd80 .delay 1 (30000,30000,30000) L_0x124dd80/d; +v0x1038eb0_0 .net *"_s0", 0 0, L_0x124de40; 1 drivers +v0x1038f90_0 .net *"_s1", 0 0, L_0x124e030; 1 drivers +S_0x1039070 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x1039280 .param/l "i" 0 4 54, +C4<010>; +L_0x124e0d0/d .functor AND 1, L_0x124e190, L_0x124e2f0, C4<1>, C4<1>; +L_0x124e0d0 .delay 1 (30000,30000,30000) L_0x124e0d0/d; +v0x1039320_0 .net *"_s0", 0 0, L_0x124e190; 1 drivers +v0x1039400_0 .net *"_s1", 0 0, L_0x124e2f0; 1 drivers +S_0x10394e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x10396f0 .param/l "i" 0 4 54, +C4<011>; +L_0x124e3e0/d .functor AND 1, L_0x124e4a0, L_0x124e600, C4<1>, C4<1>; +L_0x124e3e0 .delay 1 (30000,30000,30000) L_0x124e3e0/d; +v0x10397b0_0 .net *"_s0", 0 0, L_0x124e4a0; 1 drivers +v0x1039890_0 .net *"_s1", 0 0, L_0x124e600; 1 drivers +S_0x1039970 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x1039bd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x124e740/d .functor AND 1, L_0x124e800, L_0x124e960, C4<1>, C4<1>; +L_0x124e740 .delay 1 (30000,30000,30000) L_0x124e740/d; +v0x1039c90_0 .net *"_s0", 0 0, L_0x124e800; 1 drivers +v0x1039d70_0 .net *"_s1", 0 0, L_0x124e960; 1 drivers +S_0x1039e50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x103a060 .param/l "i" 0 4 54, +C4<0101>; +L_0x124ea50/d .functor AND 1, L_0x124eac0, L_0x124ed30, C4<1>, C4<1>; +L_0x124ea50 .delay 1 (30000,30000,30000) L_0x124ea50/d; +v0x103a120_0 .net *"_s0", 0 0, L_0x124eac0; 1 drivers +v0x103a200_0 .net *"_s1", 0 0, L_0x124ed30; 1 drivers +S_0x103a2e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x103a4f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x124ee40/d .functor AND 1, L_0x124ef00, L_0x124f060, C4<1>, C4<1>; +L_0x124ee40 .delay 1 (30000,30000,30000) L_0x124ee40/d; +v0x103a5b0_0 .net *"_s0", 0 0, L_0x124ef00; 1 drivers +v0x103a690_0 .net *"_s1", 0 0, L_0x124f060; 1 drivers +S_0x103a770 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10384d0; + .timescale -9 -12; +P_0x103a980 .param/l "i" 0 4 54, +C4<0111>; +L_0x124edd0/d .functor AND 1, L_0x124f510, L_0x124f700, C4<1>, C4<1>; +L_0x124edd0 .delay 1 (30000,30000,30000) L_0x124edd0/d; +v0x103aa40_0 .net *"_s0", 0 0, L_0x124f510; 1 drivers +v0x103ab20_0 .net *"_s1", 0 0, L_0x124f700; 1 drivers +S_0x103b6e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10382b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dbda10/d .functor OR 1, L_0x1dbdad0, L_0x1dbdc80, C4<0>, C4<0>; -L_0x1dbda10 .delay 1 (30000,30000,30000) L_0x1dbda10/d; -v0x1baa580_0 .net *"_s10", 0 0, L_0x1dbdad0; 1 drivers -v0x1baa660_0 .net *"_s12", 0 0, L_0x1dbdc80; 1 drivers -v0x1baa740_0 .net "in", 7 0, L_0x1dbba10; alias, 1 drivers -v0x1baa840_0 .net "ors", 1 0, L_0x1dbd830; 1 drivers -v0x1baa900_0 .net "out", 0 0, L_0x1dbda10; alias, 1 drivers -L_0x1dbcc00 .part L_0x1dbba10, 0, 4; -L_0x1dbd830 .concat8 [ 1 1 0 0], L_0x1dbc8f0, L_0x1dbd520; -L_0x1dbd970 .part L_0x1dbba10, 4, 4; -L_0x1dbdad0 .part L_0x1dbd830, 0, 1; -L_0x1dbdc80 .part L_0x1dbd830, 1, 1; -S_0x1ba8c10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1ba8a50; +L_0x1251150/d .functor OR 1, L_0x1251210, L_0x12513c0, C4<0>, C4<0>; +L_0x1251150 .delay 1 (30000,30000,30000) L_0x1251150/d; +v0x103d230_0 .net *"_s10", 0 0, L_0x1251210; 1 drivers +v0x103d310_0 .net *"_s12", 0 0, L_0x12513c0; 1 drivers +v0x103d3f0_0 .net "in", 7 0, L_0x124f150; alias, 1 drivers +v0x103d4c0_0 .net "ors", 1 0, L_0x1250f70; 1 drivers +v0x103d580_0 .net "out", 0 0, L_0x1251150; alias, 1 drivers +L_0x1250340 .part L_0x124f150, 0, 4; +L_0x1250f70 .concat8 [ 1 1 0 0], L_0x1250030, L_0x1250c60; +L_0x12510b0 .part L_0x124f150, 4, 4; +L_0x1251210 .part L_0x1250f70, 0, 1; +L_0x12513c0 .part L_0x1250f70, 1, 1; +S_0x103b8a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x103b6e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dbc0b0/d .functor OR 1, L_0x1dbc170, L_0x1dbc2d0, C4<0>, C4<0>; -L_0x1dbc0b0 .delay 1 (30000,30000,30000) L_0x1dbc0b0/d; -L_0x1dbc500/d .functor OR 1, L_0x1dbc610, L_0x1dbc770, C4<0>, C4<0>; -L_0x1dbc500 .delay 1 (30000,30000,30000) L_0x1dbc500/d; -L_0x1dbc8f0/d .functor OR 1, L_0x1dbc960, L_0x1dbcb10, C4<0>, C4<0>; -L_0x1dbc8f0 .delay 1 (30000,30000,30000) L_0x1dbc8f0/d; -v0x1ba8e60_0 .net *"_s0", 0 0, L_0x1dbc0b0; 1 drivers -v0x1ba8f60_0 .net *"_s10", 0 0, L_0x1dbc610; 1 drivers -v0x1ba9040_0 .net *"_s12", 0 0, L_0x1dbc770; 1 drivers -v0x1ba9100_0 .net *"_s14", 0 0, L_0x1dbc960; 1 drivers -v0x1ba91e0_0 .net *"_s16", 0 0, L_0x1dbcb10; 1 drivers -v0x1ba9310_0 .net *"_s3", 0 0, L_0x1dbc170; 1 drivers -v0x1ba93f0_0 .net *"_s5", 0 0, L_0x1dbc2d0; 1 drivers -v0x1ba94d0_0 .net *"_s6", 0 0, L_0x1dbc500; 1 drivers -v0x1ba95b0_0 .net "in", 3 0, L_0x1dbcc00; 1 drivers -v0x1ba9720_0 .net "ors", 1 0, L_0x1dbc410; 1 drivers -v0x1ba9800_0 .net "out", 0 0, L_0x1dbc8f0; 1 drivers -L_0x1dbc170 .part L_0x1dbcc00, 0, 1; -L_0x1dbc2d0 .part L_0x1dbcc00, 1, 1; -L_0x1dbc410 .concat8 [ 1 1 0 0], L_0x1dbc0b0, L_0x1dbc500; -L_0x1dbc610 .part L_0x1dbcc00, 2, 1; -L_0x1dbc770 .part L_0x1dbcc00, 3, 1; -L_0x1dbc960 .part L_0x1dbc410, 0, 1; -L_0x1dbcb10 .part L_0x1dbc410, 1, 1; -S_0x1ba9920 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1ba8a50; +L_0x124f7f0/d .functor OR 1, L_0x124f8b0, L_0x124fa10, C4<0>, C4<0>; +L_0x124f7f0 .delay 1 (30000,30000,30000) L_0x124f7f0/d; +L_0x124fc40/d .functor OR 1, L_0x124fd50, L_0x124feb0, C4<0>, C4<0>; +L_0x124fc40 .delay 1 (30000,30000,30000) L_0x124fc40/d; +L_0x1250030/d .functor OR 1, L_0x12500a0, L_0x1250250, C4<0>, C4<0>; +L_0x1250030 .delay 1 (30000,30000,30000) L_0x1250030/d; +v0x103baf0_0 .net *"_s0", 0 0, L_0x124f7f0; 1 drivers +v0x103bbf0_0 .net *"_s10", 0 0, L_0x124fd50; 1 drivers +v0x103bcd0_0 .net *"_s12", 0 0, L_0x124feb0; 1 drivers +v0x103bd90_0 .net *"_s14", 0 0, L_0x12500a0; 1 drivers +v0x103be70_0 .net *"_s16", 0 0, L_0x1250250; 1 drivers +v0x103bfa0_0 .net *"_s3", 0 0, L_0x124f8b0; 1 drivers +v0x103c080_0 .net *"_s5", 0 0, L_0x124fa10; 1 drivers +v0x103c160_0 .net *"_s6", 0 0, L_0x124fc40; 1 drivers +v0x103c240_0 .net "in", 3 0, L_0x1250340; 1 drivers +v0x103c3b0_0 .net "ors", 1 0, L_0x124fb50; 1 drivers +v0x103c490_0 .net "out", 0 0, L_0x1250030; 1 drivers +L_0x124f8b0 .part L_0x1250340, 0, 1; +L_0x124fa10 .part L_0x1250340, 1, 1; +L_0x124fb50 .concat8 [ 1 1 0 0], L_0x124f7f0, L_0x124fc40; +L_0x124fd50 .part L_0x1250340, 2, 1; +L_0x124feb0 .part L_0x1250340, 3, 1; +L_0x12500a0 .part L_0x124fb50, 0, 1; +L_0x1250250 .part L_0x124fb50, 1, 1; +S_0x103c5b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x103b6e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dbcd30/d .functor OR 1, L_0x1dbcda0, L_0x1dbcf00, C4<0>, C4<0>; -L_0x1dbcd30 .delay 1 (30000,30000,30000) L_0x1dbcd30/d; -L_0x1dbd130/d .functor OR 1, L_0x1dbd240, L_0x1dbd3a0, C4<0>, C4<0>; -L_0x1dbd130 .delay 1 (30000,30000,30000) L_0x1dbd130/d; -L_0x1dbd520/d .functor OR 1, L_0x1dbd590, L_0x1dbd740, C4<0>, C4<0>; -L_0x1dbd520 .delay 1 (30000,30000,30000) L_0x1dbd520/d; -v0x1ba9ae0_0 .net *"_s0", 0 0, L_0x1dbcd30; 1 drivers -v0x1ba9be0_0 .net *"_s10", 0 0, L_0x1dbd240; 1 drivers -v0x1ba9cc0_0 .net *"_s12", 0 0, L_0x1dbd3a0; 1 drivers -v0x1ba9d80_0 .net *"_s14", 0 0, L_0x1dbd590; 1 drivers -v0x1ba9e60_0 .net *"_s16", 0 0, L_0x1dbd740; 1 drivers -v0x1ba9f90_0 .net *"_s3", 0 0, L_0x1dbcda0; 1 drivers -v0x1baa050_0 .net *"_s5", 0 0, L_0x1dbcf00; 1 drivers -v0x1baa130_0 .net *"_s6", 0 0, L_0x1dbd130; 1 drivers -v0x1baa210_0 .net "in", 3 0, L_0x1dbd970; 1 drivers -v0x1baa380_0 .net "ors", 1 0, L_0x1dbd040; 1 drivers -v0x1baa460_0 .net "out", 0 0, L_0x1dbd520; 1 drivers -L_0x1dbcda0 .part L_0x1dbd970, 0, 1; -L_0x1dbcf00 .part L_0x1dbd970, 1, 1; -L_0x1dbd040 .concat8 [ 1 1 0 0], L_0x1dbcd30, L_0x1dbd130; -L_0x1dbd240 .part L_0x1dbd970, 2, 1; -L_0x1dbd3a0 .part L_0x1dbd970, 3, 1; -L_0x1dbd590 .part L_0x1dbd040, 0, 1; -L_0x1dbd740 .part L_0x1dbd040, 1, 1; -S_0x1baada0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1ba3ec0; +L_0x1250470/d .functor OR 1, L_0x12504e0, L_0x1250640, C4<0>, C4<0>; +L_0x1250470 .delay 1 (30000,30000,30000) L_0x1250470/d; +L_0x1250870/d .functor OR 1, L_0x1250980, L_0x1250ae0, C4<0>, C4<0>; +L_0x1250870 .delay 1 (30000,30000,30000) L_0x1250870/d; +L_0x1250c60/d .functor OR 1, L_0x1250cd0, L_0x1250e80, C4<0>, C4<0>; +L_0x1250c60 .delay 1 (30000,30000,30000) L_0x1250c60/d; +v0x103c770_0 .net *"_s0", 0 0, L_0x1250470; 1 drivers +v0x103c870_0 .net *"_s10", 0 0, L_0x1250980; 1 drivers +v0x103c950_0 .net *"_s12", 0 0, L_0x1250ae0; 1 drivers +v0x103ca10_0 .net *"_s14", 0 0, L_0x1250cd0; 1 drivers +v0x103caf0_0 .net *"_s16", 0 0, L_0x1250e80; 1 drivers +v0x103cc20_0 .net *"_s3", 0 0, L_0x12504e0; 1 drivers +v0x103cd00_0 .net *"_s5", 0 0, L_0x1250640; 1 drivers +v0x103cde0_0 .net *"_s6", 0 0, L_0x1250870; 1 drivers +v0x103cec0_0 .net "in", 3 0, L_0x12510b0; 1 drivers +v0x103d030_0 .net "ors", 1 0, L_0x1250780; 1 drivers +v0x103d110_0 .net "out", 0 0, L_0x1250c60; 1 drivers +L_0x12504e0 .part L_0x12510b0, 0, 1; +L_0x1250640 .part L_0x12510b0, 1, 1; +L_0x1250780 .concat8 [ 1 1 0 0], L_0x1250470, L_0x1250870; +L_0x1250980 .part L_0x12510b0, 2, 1; +L_0x1250ae0 .part L_0x12510b0, 3, 1; +L_0x1250cd0 .part L_0x1250780, 0, 1; +L_0x1250e80 .part L_0x1250780, 1, 1; +S_0x103da20 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1036b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bb01d0_0 .net "ands", 7 0, L_0x1db7fb0; 1 drivers -v0x1bb02e0_0 .net "in", 7 0, L_0x1db64f0; alias, 1 drivers -v0x1bb03a0_0 .net "out", 0 0, L_0x1db9ef0; alias, 1 drivers -v0x1bb0470_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1baaff0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1baada0; +v0x1042e50_0 .net "ands", 7 0, L_0x124b710; 1 drivers +v0x1042f60_0 .net "in", 7 0, L_0x1249c50; alias, 1 drivers +v0x1043000_0 .net "out", 0 0, L_0x124d710; alias, 1 drivers +v0x10430d0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x103dc70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x103da20; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bad730_0 .net "A", 7 0, L_0x1db64f0; alias, 1 drivers -v0x1bad830_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bad8f0_0 .net *"_s0", 0 0, L_0x1db6880; 1 drivers -v0x1bad9b0_0 .net *"_s12", 0 0, L_0x1db7240; 1 drivers -v0x1bada90_0 .net *"_s16", 0 0, L_0x1db75a0; 1 drivers -v0x1badbc0_0 .net *"_s20", 0 0, L_0x1db7970; 1 drivers -v0x1badca0_0 .net *"_s24", 0 0, L_0x1db7ca0; 1 drivers -v0x1badd80_0 .net *"_s28", 0 0, L_0x1db7c30; 1 drivers -v0x1bade60_0 .net *"_s4", 0 0, L_0x1db6c20; 1 drivers -v0x1badfd0_0 .net *"_s8", 0 0, L_0x1db6f30; 1 drivers -v0x1bae0b0_0 .net "out", 7 0, L_0x1db7fb0; alias, 1 drivers -L_0x1db6990 .part L_0x1db64f0, 0, 1; -L_0x1db6b80 .part v0x1d6daa0_0, 0, 1; -L_0x1db6ce0 .part L_0x1db64f0, 1, 1; -L_0x1db6e40 .part v0x1d6daa0_0, 1, 1; -L_0x1db6ff0 .part L_0x1db64f0, 2, 1; -L_0x1db7150 .part v0x1d6daa0_0, 2, 1; -L_0x1db7300 .part L_0x1db64f0, 3, 1; -L_0x1db7460 .part v0x1d6daa0_0, 3, 1; -L_0x1db7660 .part L_0x1db64f0, 4, 1; -L_0x1db78d0 .part v0x1d6daa0_0, 4, 1; -L_0x1db79e0 .part L_0x1db64f0, 5, 1; -L_0x1db7b40 .part v0x1d6daa0_0, 5, 1; -L_0x1db7d60 .part L_0x1db64f0, 6, 1; -L_0x1db7ec0 .part v0x1d6daa0_0, 6, 1; -LS_0x1db7fb0_0_0 .concat8 [ 1 1 1 1], L_0x1db6880, L_0x1db6c20, L_0x1db6f30, L_0x1db7240; -LS_0x1db7fb0_0_4 .concat8 [ 1 1 1 1], L_0x1db75a0, L_0x1db7970, L_0x1db7ca0, L_0x1db7c30; -L_0x1db7fb0 .concat8 [ 4 4 0 0], LS_0x1db7fb0_0_0, LS_0x1db7fb0_0_4; -L_0x1db8370 .part L_0x1db64f0, 7, 1; -L_0x1db8560 .part v0x1d6daa0_0, 7, 1; -S_0x1bab230 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bab440 .param/l "i" 0 4 54, +C4<00>; -L_0x1db6880/d .functor AND 1, L_0x1db6990, L_0x1db6b80, C4<1>, C4<1>; -L_0x1db6880 .delay 1 (30000,30000,30000) L_0x1db6880/d; -v0x1bab520_0 .net *"_s0", 0 0, L_0x1db6990; 1 drivers -v0x1bab600_0 .net *"_s1", 0 0, L_0x1db6b80; 1 drivers -S_0x1bab6e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bab8f0 .param/l "i" 0 4 54, +C4<01>; -L_0x1db6c20/d .functor AND 1, L_0x1db6ce0, L_0x1db6e40, C4<1>, C4<1>; -L_0x1db6c20 .delay 1 (30000,30000,30000) L_0x1db6c20/d; -v0x1bab9b0_0 .net *"_s0", 0 0, L_0x1db6ce0; 1 drivers -v0x1baba90_0 .net *"_s1", 0 0, L_0x1db6e40; 1 drivers -S_0x1babb70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1babdb0 .param/l "i" 0 4 54, +C4<010>; -L_0x1db6f30/d .functor AND 1, L_0x1db6ff0, L_0x1db7150, C4<1>, C4<1>; -L_0x1db6f30 .delay 1 (30000,30000,30000) L_0x1db6f30/d; -v0x1babe50_0 .net *"_s0", 0 0, L_0x1db6ff0; 1 drivers -v0x1babf30_0 .net *"_s1", 0 0, L_0x1db7150; 1 drivers -S_0x1bac010 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bac220 .param/l "i" 0 4 54, +C4<011>; -L_0x1db7240/d .functor AND 1, L_0x1db7300, L_0x1db7460, C4<1>, C4<1>; -L_0x1db7240 .delay 1 (30000,30000,30000) L_0x1db7240/d; -v0x1bac2e0_0 .net *"_s0", 0 0, L_0x1db7300; 1 drivers -v0x1bac3c0_0 .net *"_s1", 0 0, L_0x1db7460; 1 drivers -S_0x1bac4a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bac700 .param/l "i" 0 4 54, +C4<0100>; -L_0x1db75a0/d .functor AND 1, L_0x1db7660, L_0x1db78d0, C4<1>, C4<1>; -L_0x1db75a0 .delay 1 (30000,30000,30000) L_0x1db75a0/d; -v0x1bac7c0_0 .net *"_s0", 0 0, L_0x1db7660; 1 drivers -v0x1bac8a0_0 .net *"_s1", 0 0, L_0x1db78d0; 1 drivers -S_0x1bac980 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bacb90 .param/l "i" 0 4 54, +C4<0101>; -L_0x1db7970/d .functor AND 1, L_0x1db79e0, L_0x1db7b40, C4<1>, C4<1>; -L_0x1db7970 .delay 1 (30000,30000,30000) L_0x1db7970/d; -v0x1bacc50_0 .net *"_s0", 0 0, L_0x1db79e0; 1 drivers -v0x1bacd30_0 .net *"_s1", 0 0, L_0x1db7b40; 1 drivers -S_0x1bace10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bad020 .param/l "i" 0 4 54, +C4<0110>; -L_0x1db7ca0/d .functor AND 1, L_0x1db7d60, L_0x1db7ec0, C4<1>, C4<1>; -L_0x1db7ca0 .delay 1 (30000,30000,30000) L_0x1db7ca0/d; -v0x1bad0e0_0 .net *"_s0", 0 0, L_0x1db7d60; 1 drivers -v0x1bad1c0_0 .net *"_s1", 0 0, L_0x1db7ec0; 1 drivers -S_0x1bad2a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1baaff0; - .timescale -9 -12; -P_0x1bad4b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1db7c30/d .functor AND 1, L_0x1db8370, L_0x1db8560, C4<1>, C4<1>; -L_0x1db7c30 .delay 1 (30000,30000,30000) L_0x1db7c30/d; -v0x1bad570_0 .net *"_s0", 0 0, L_0x1db8370; 1 drivers -v0x1bad650_0 .net *"_s1", 0 0, L_0x1db8560; 1 drivers -S_0x1bae210 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1baada0; +v0x10403b0_0 .net "A", 7 0, L_0x1249c50; alias, 1 drivers +v0x10404b0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1040570_0 .net *"_s0", 0 0, L_0x1249fe0; 1 drivers +v0x1040630_0 .net *"_s12", 0 0, L_0x124a9a0; 1 drivers +v0x1040710_0 .net *"_s16", 0 0, L_0x124ad00; 1 drivers +v0x1040840_0 .net *"_s20", 0 0, L_0x124b0d0; 1 drivers +v0x1040920_0 .net *"_s24", 0 0, L_0x124b400; 1 drivers +v0x1040a00_0 .net *"_s28", 0 0, L_0x124b390; 1 drivers +v0x1040ae0_0 .net *"_s4", 0 0, L_0x124a380; 1 drivers +v0x1040c50_0 .net *"_s8", 0 0, L_0x124a690; 1 drivers +v0x1040d30_0 .net "out", 7 0, L_0x124b710; alias, 1 drivers +L_0x124a0f0 .part L_0x1249c50, 0, 1; +L_0x124a2e0 .part v0x12010b0_0, 0, 1; +L_0x124a440 .part L_0x1249c50, 1, 1; +L_0x124a5a0 .part v0x12010b0_0, 1, 1; +L_0x124a750 .part L_0x1249c50, 2, 1; +L_0x124a8b0 .part v0x12010b0_0, 2, 1; +L_0x124aa60 .part L_0x1249c50, 3, 1; +L_0x124abc0 .part v0x12010b0_0, 3, 1; +L_0x124adc0 .part L_0x1249c50, 4, 1; +L_0x124b030 .part v0x12010b0_0, 4, 1; +L_0x124b140 .part L_0x1249c50, 5, 1; +L_0x124b2a0 .part v0x12010b0_0, 5, 1; +L_0x124b4c0 .part L_0x1249c50, 6, 1; +L_0x124b620 .part v0x12010b0_0, 6, 1; +LS_0x124b710_0_0 .concat8 [ 1 1 1 1], L_0x1249fe0, L_0x124a380, L_0x124a690, L_0x124a9a0; +LS_0x124b710_0_4 .concat8 [ 1 1 1 1], L_0x124ad00, L_0x124b0d0, L_0x124b400, L_0x124b390; +L_0x124b710 .concat8 [ 4 4 0 0], LS_0x124b710_0_0, LS_0x124b710_0_4; +L_0x124bad0 .part L_0x1249c50, 7, 1; +L_0x124bcc0 .part v0x12010b0_0, 7, 1; +S_0x103deb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103e0c0 .param/l "i" 0 4 54, +C4<00>; +L_0x1249fe0/d .functor AND 1, L_0x124a0f0, L_0x124a2e0, C4<1>, C4<1>; +L_0x1249fe0 .delay 1 (30000,30000,30000) L_0x1249fe0/d; +v0x103e1a0_0 .net *"_s0", 0 0, L_0x124a0f0; 1 drivers +v0x103e280_0 .net *"_s1", 0 0, L_0x124a2e0; 1 drivers +S_0x103e360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103e570 .param/l "i" 0 4 54, +C4<01>; +L_0x124a380/d .functor AND 1, L_0x124a440, L_0x124a5a0, C4<1>, C4<1>; +L_0x124a380 .delay 1 (30000,30000,30000) L_0x124a380/d; +v0x103e630_0 .net *"_s0", 0 0, L_0x124a440; 1 drivers +v0x103e710_0 .net *"_s1", 0 0, L_0x124a5a0; 1 drivers +S_0x103e7f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103ea30 .param/l "i" 0 4 54, +C4<010>; +L_0x124a690/d .functor AND 1, L_0x124a750, L_0x124a8b0, C4<1>, C4<1>; +L_0x124a690 .delay 1 (30000,30000,30000) L_0x124a690/d; +v0x103ead0_0 .net *"_s0", 0 0, L_0x124a750; 1 drivers +v0x103ebb0_0 .net *"_s1", 0 0, L_0x124a8b0; 1 drivers +S_0x103ec90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103eea0 .param/l "i" 0 4 54, +C4<011>; +L_0x124a9a0/d .functor AND 1, L_0x124aa60, L_0x124abc0, C4<1>, C4<1>; +L_0x124a9a0 .delay 1 (30000,30000,30000) L_0x124a9a0/d; +v0x103ef60_0 .net *"_s0", 0 0, L_0x124aa60; 1 drivers +v0x103f040_0 .net *"_s1", 0 0, L_0x124abc0; 1 drivers +S_0x103f120 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103f380 .param/l "i" 0 4 54, +C4<0100>; +L_0x124ad00/d .functor AND 1, L_0x124adc0, L_0x124b030, C4<1>, C4<1>; +L_0x124ad00 .delay 1 (30000,30000,30000) L_0x124ad00/d; +v0x103f440_0 .net *"_s0", 0 0, L_0x124adc0; 1 drivers +v0x103f520_0 .net *"_s1", 0 0, L_0x124b030; 1 drivers +S_0x103f600 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103f810 .param/l "i" 0 4 54, +C4<0101>; +L_0x124b0d0/d .functor AND 1, L_0x124b140, L_0x124b2a0, C4<1>, C4<1>; +L_0x124b0d0 .delay 1 (30000,30000,30000) L_0x124b0d0/d; +v0x103f8d0_0 .net *"_s0", 0 0, L_0x124b140; 1 drivers +v0x103f9b0_0 .net *"_s1", 0 0, L_0x124b2a0; 1 drivers +S_0x103fa90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x103fca0 .param/l "i" 0 4 54, +C4<0110>; +L_0x124b400/d .functor AND 1, L_0x124b4c0, L_0x124b620, C4<1>, C4<1>; +L_0x124b400 .delay 1 (30000,30000,30000) L_0x124b400/d; +v0x103fd60_0 .net *"_s0", 0 0, L_0x124b4c0; 1 drivers +v0x103fe40_0 .net *"_s1", 0 0, L_0x124b620; 1 drivers +S_0x103ff20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x103dc70; + .timescale -9 -12; +P_0x1040130 .param/l "i" 0 4 54, +C4<0111>; +L_0x124b390/d .functor AND 1, L_0x124bad0, L_0x124bcc0, C4<1>, C4<1>; +L_0x124b390 .delay 1 (30000,30000,30000) L_0x124b390/d; +v0x10401f0_0 .net *"_s0", 0 0, L_0x124bad0; 1 drivers +v0x10402d0_0 .net *"_s1", 0 0, L_0x124bcc0; 1 drivers +S_0x1040e90 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x103da20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1db9ef0/d .functor OR 1, L_0x1db9fb0, L_0x1dba160, C4<0>, C4<0>; -L_0x1db9ef0 .delay 1 (30000,30000,30000) L_0x1db9ef0/d; -v0x1bafd60_0 .net *"_s10", 0 0, L_0x1db9fb0; 1 drivers -v0x1bafe40_0 .net *"_s12", 0 0, L_0x1dba160; 1 drivers -v0x1baff20_0 .net "in", 7 0, L_0x1db7fb0; alias, 1 drivers -v0x1bafff0_0 .net "ors", 1 0, L_0x1db9d10; 1 drivers -v0x1bb00b0_0 .net "out", 0 0, L_0x1db9ef0; alias, 1 drivers -L_0x1db90e0 .part L_0x1db7fb0, 0, 4; -L_0x1db9d10 .concat8 [ 1 1 0 0], L_0x1db8e90, L_0x1db9a00; -L_0x1db9e50 .part L_0x1db7fb0, 4, 4; -L_0x1db9fb0 .part L_0x1db9d10, 0, 1; -L_0x1dba160 .part L_0x1db9d10, 1, 1; -S_0x1bae3d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bae210; +L_0x124d710/d .functor OR 1, L_0x124d7d0, L_0x124d980, C4<0>, C4<0>; +L_0x124d710 .delay 1 (30000,30000,30000) L_0x124d710/d; +v0x10429e0_0 .net *"_s10", 0 0, L_0x124d7d0; 1 drivers +v0x1042ac0_0 .net *"_s12", 0 0, L_0x124d980; 1 drivers +v0x1042ba0_0 .net "in", 7 0, L_0x124b710; alias, 1 drivers +v0x1042c70_0 .net "ors", 1 0, L_0x124d530; 1 drivers +v0x1042d30_0 .net "out", 0 0, L_0x124d710; alias, 1 drivers +L_0x124c900 .part L_0x124b710, 0, 4; +L_0x124d530 .concat8 [ 1 1 0 0], L_0x124c5f0, L_0x124d220; +L_0x124d670 .part L_0x124b710, 4, 4; +L_0x124d7d0 .part L_0x124d530, 0, 1; +L_0x124d980 .part L_0x124d530, 1, 1; +S_0x1041050 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1040e90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1db8650/d .functor OR 1, L_0x1db8710, L_0x1db8870, C4<0>, C4<0>; -L_0x1db8650 .delay 1 (30000,30000,30000) L_0x1db8650/d; -L_0x1db8aa0/d .functor OR 1, L_0x1db8bb0, L_0x1db8d10, C4<0>, C4<0>; -L_0x1db8aa0 .delay 1 (30000,30000,30000) L_0x1db8aa0/d; -L_0x1db8e90/d .functor OR 1, L_0x1db8f00, L_0x1db8ff0, C4<0>, C4<0>; -L_0x1db8e90 .delay 1 (30000,30000,30000) L_0x1db8e90/d; -v0x1bae620_0 .net *"_s0", 0 0, L_0x1db8650; 1 drivers -v0x1bae720_0 .net *"_s10", 0 0, L_0x1db8bb0; 1 drivers -v0x1bae800_0 .net *"_s12", 0 0, L_0x1db8d10; 1 drivers -v0x1bae8c0_0 .net *"_s14", 0 0, L_0x1db8f00; 1 drivers -v0x1bae9a0_0 .net *"_s16", 0 0, L_0x1db8ff0; 1 drivers -v0x1baead0_0 .net *"_s3", 0 0, L_0x1db8710; 1 drivers -v0x1baebb0_0 .net *"_s5", 0 0, L_0x1db8870; 1 drivers -v0x1baec90_0 .net *"_s6", 0 0, L_0x1db8aa0; 1 drivers -v0x1baed70_0 .net "in", 3 0, L_0x1db90e0; 1 drivers -v0x1baeee0_0 .net "ors", 1 0, L_0x1db89b0; 1 drivers -v0x1baefc0_0 .net "out", 0 0, L_0x1db8e90; 1 drivers -L_0x1db8710 .part L_0x1db90e0, 0, 1; -L_0x1db8870 .part L_0x1db90e0, 1, 1; -L_0x1db89b0 .concat8 [ 1 1 0 0], L_0x1db8650, L_0x1db8aa0; -L_0x1db8bb0 .part L_0x1db90e0, 2, 1; -L_0x1db8d10 .part L_0x1db90e0, 3, 1; -L_0x1db8f00 .part L_0x1db89b0, 0, 1; -L_0x1db8ff0 .part L_0x1db89b0, 1, 1; -S_0x1baf0e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bae210; +L_0x124bdb0/d .functor OR 1, L_0x124be70, L_0x124bfd0, C4<0>, C4<0>; +L_0x124bdb0 .delay 1 (30000,30000,30000) L_0x124bdb0/d; +L_0x124c200/d .functor OR 1, L_0x124c310, L_0x124c470, C4<0>, C4<0>; +L_0x124c200 .delay 1 (30000,30000,30000) L_0x124c200/d; +L_0x124c5f0/d .functor OR 1, L_0x124c660, L_0x124c810, C4<0>, C4<0>; +L_0x124c5f0 .delay 1 (30000,30000,30000) L_0x124c5f0/d; +v0x10412a0_0 .net *"_s0", 0 0, L_0x124bdb0; 1 drivers +v0x10413a0_0 .net *"_s10", 0 0, L_0x124c310; 1 drivers +v0x1041480_0 .net *"_s12", 0 0, L_0x124c470; 1 drivers +v0x1041540_0 .net *"_s14", 0 0, L_0x124c660; 1 drivers +v0x1041620_0 .net *"_s16", 0 0, L_0x124c810; 1 drivers +v0x1041750_0 .net *"_s3", 0 0, L_0x124be70; 1 drivers +v0x1041830_0 .net *"_s5", 0 0, L_0x124bfd0; 1 drivers +v0x1041910_0 .net *"_s6", 0 0, L_0x124c200; 1 drivers +v0x10419f0_0 .net "in", 3 0, L_0x124c900; 1 drivers +v0x1041b60_0 .net "ors", 1 0, L_0x124c110; 1 drivers +v0x1041c40_0 .net "out", 0 0, L_0x124c5f0; 1 drivers +L_0x124be70 .part L_0x124c900, 0, 1; +L_0x124bfd0 .part L_0x124c900, 1, 1; +L_0x124c110 .concat8 [ 1 1 0 0], L_0x124bdb0, L_0x124c200; +L_0x124c310 .part L_0x124c900, 2, 1; +L_0x124c470 .part L_0x124c900, 3, 1; +L_0x124c660 .part L_0x124c110, 0, 1; +L_0x124c810 .part L_0x124c110, 1, 1; +S_0x1041d60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1040e90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1db9210/d .functor OR 1, L_0x1db9280, L_0x1db93e0, C4<0>, C4<0>; -L_0x1db9210 .delay 1 (30000,30000,30000) L_0x1db9210/d; -L_0x1db9610/d .functor OR 1, L_0x1db9720, L_0x1db9880, C4<0>, C4<0>; -L_0x1db9610 .delay 1 (30000,30000,30000) L_0x1db9610/d; -L_0x1db9a00/d .functor OR 1, L_0x1db9a70, L_0x1db9c20, C4<0>, C4<0>; -L_0x1db9a00 .delay 1 (30000,30000,30000) L_0x1db9a00/d; -v0x1baf2a0_0 .net *"_s0", 0 0, L_0x1db9210; 1 drivers -v0x1baf3a0_0 .net *"_s10", 0 0, L_0x1db9720; 1 drivers -v0x1baf480_0 .net *"_s12", 0 0, L_0x1db9880; 1 drivers -v0x1baf540_0 .net *"_s14", 0 0, L_0x1db9a70; 1 drivers -v0x1baf620_0 .net *"_s16", 0 0, L_0x1db9c20; 1 drivers -v0x1baf750_0 .net *"_s3", 0 0, L_0x1db9280; 1 drivers -v0x1baf830_0 .net *"_s5", 0 0, L_0x1db93e0; 1 drivers -v0x1baf910_0 .net *"_s6", 0 0, L_0x1db9610; 1 drivers -v0x1baf9f0_0 .net "in", 3 0, L_0x1db9e50; 1 drivers -v0x1bafb60_0 .net "ors", 1 0, L_0x1db9520; 1 drivers -v0x1bafc40_0 .net "out", 0 0, L_0x1db9a00; 1 drivers -L_0x1db9280 .part L_0x1db9e50, 0, 1; -L_0x1db93e0 .part L_0x1db9e50, 1, 1; -L_0x1db9520 .concat8 [ 1 1 0 0], L_0x1db9210, L_0x1db9610; -L_0x1db9720 .part L_0x1db9e50, 2, 1; -L_0x1db9880 .part L_0x1db9e50, 3, 1; -L_0x1db9a70 .part L_0x1db9520, 0, 1; -L_0x1db9c20 .part L_0x1db9520, 1, 1; -S_0x1bb0550 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ba3ec0; +L_0x124ca30/d .functor OR 1, L_0x124caa0, L_0x124cc00, C4<0>, C4<0>; +L_0x124ca30 .delay 1 (30000,30000,30000) L_0x124ca30/d; +L_0x124ce30/d .functor OR 1, L_0x124cf40, L_0x124d0a0, C4<0>, C4<0>; +L_0x124ce30 .delay 1 (30000,30000,30000) L_0x124ce30/d; +L_0x124d220/d .functor OR 1, L_0x124d290, L_0x124d440, C4<0>, C4<0>; +L_0x124d220 .delay 1 (30000,30000,30000) L_0x124d220/d; +v0x1041f20_0 .net *"_s0", 0 0, L_0x124ca30; 1 drivers +v0x1042020_0 .net *"_s10", 0 0, L_0x124cf40; 1 drivers +v0x1042100_0 .net *"_s12", 0 0, L_0x124d0a0; 1 drivers +v0x10421c0_0 .net *"_s14", 0 0, L_0x124d290; 1 drivers +v0x10422a0_0 .net *"_s16", 0 0, L_0x124d440; 1 drivers +v0x10423d0_0 .net *"_s3", 0 0, L_0x124caa0; 1 drivers +v0x10424b0_0 .net *"_s5", 0 0, L_0x124cc00; 1 drivers +v0x1042590_0 .net *"_s6", 0 0, L_0x124ce30; 1 drivers +v0x1042670_0 .net "in", 3 0, L_0x124d670; 1 drivers +v0x10427e0_0 .net "ors", 1 0, L_0x124cd40; 1 drivers +v0x10428c0_0 .net "out", 0 0, L_0x124d220; 1 drivers +L_0x124caa0 .part L_0x124d670, 0, 1; +L_0x124cc00 .part L_0x124d670, 1, 1; +L_0x124cd40 .concat8 [ 1 1 0 0], L_0x124ca30, L_0x124ce30; +L_0x124cf40 .part L_0x124d670, 2, 1; +L_0x124d0a0 .part L_0x124d670, 3, 1; +L_0x124d290 .part L_0x124cd40, 0, 1; +L_0x124d440 .part L_0x124cd40, 1, 1; +S_0x10431d0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1036b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -4396,80 +4406,80 @@ S_0x1bb0550 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ba3ec0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1db5860/d .functor XNOR 1, L_0x1dbde70, L_0x1db44f0, C4<0>, C4<0>; -L_0x1db5860 .delay 1 (20000,20000,20000) L_0x1db5860/d; -L_0x1db5ad0/d .functor AND 1, L_0x1dbde70, L_0x1db4750, C4<1>, C4<1>; -L_0x1db5ad0 .delay 1 (30000,30000,30000) L_0x1db5ad0/d; -L_0x1db5b40/d .functor AND 1, L_0x1db5860, L_0x1dbe090, C4<1>, C4<1>; -L_0x1db5b40 .delay 1 (30000,30000,30000) L_0x1db5b40/d; -L_0x1db5ca0/d .functor OR 1, L_0x1db5b40, L_0x1db5ad0, C4<0>, C4<0>; -L_0x1db5ca0 .delay 1 (30000,30000,30000) L_0x1db5ca0/d; -v0x1bb0800_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers -v0x1bb08f0_0 .net "a_", 0 0, L_0x1db4640; alias, 1 drivers -v0x1bb09b0_0 .net "b", 0 0, L_0x1db44f0; alias, 1 drivers -v0x1bb0aa0_0 .net "b_", 0 0, L_0x1db4750; alias, 1 drivers -v0x1bb0b40_0 .net "carryin", 0 0, L_0x1dbe090; alias, 1 drivers -v0x1bb0c80_0 .net "eq", 0 0, L_0x1db5860; 1 drivers -v0x1bb0d40_0 .net "lt", 0 0, L_0x1db5ad0; 1 drivers -v0x1bb0e00_0 .net "out", 0 0, L_0x1db5ca0; 1 drivers -v0x1bb0ec0_0 .net "w0", 0 0, L_0x1db5b40; 1 drivers -S_0x1bb1110 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1ba3ec0; +L_0x1248fc0/d .functor XNOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; +L_0x1248fc0 .delay 1 (20000,20000,20000) L_0x1248fc0/d; +L_0x1249230/d .functor AND 1, L_0x12515b0, L_0x1247eb0, C4<1>, C4<1>; +L_0x1249230 .delay 1 (30000,30000,30000) L_0x1249230/d; +L_0x12492a0/d .functor AND 1, L_0x1248fc0, L_0x12517d0, C4<1>, C4<1>; +L_0x12492a0 .delay 1 (30000,30000,30000) L_0x12492a0/d; +L_0x1249400/d .functor OR 1, L_0x12492a0, L_0x1249230, C4<0>, C4<0>; +L_0x1249400 .delay 1 (30000,30000,30000) L_0x1249400/d; +v0x1043480_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers +v0x1043570_0 .net "a_", 0 0, L_0x1247da0; alias, 1 drivers +v0x1043630_0 .net "b", 0 0, L_0x1247c50; alias, 1 drivers +v0x1043720_0 .net "b_", 0 0, L_0x1247eb0; alias, 1 drivers +v0x10437c0_0 .net "carryin", 0 0, L_0x12517d0; alias, 1 drivers +v0x1043900_0 .net "eq", 0 0, L_0x1248fc0; 1 drivers +v0x10439c0_0 .net "lt", 0 0, L_0x1249230; 1 drivers +v0x1043a80_0 .net "out", 0 0, L_0x1249400; 1 drivers +v0x1043b40_0 .net "w0", 0 0, L_0x12492a0; 1 drivers +S_0x1043d90 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1036b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1db5640/d .functor OR 1, L_0x1db5140, L_0x1bb2370, C4<0>, C4<0>; -L_0x1db5640 .delay 1 (30000,30000,30000) L_0x1db5640/d; -v0x1bb1f00_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers -v0x1bb2050_0 .net "b", 0 0, L_0x1db4750; alias, 1 drivers -v0x1bb2110_0 .net "c1", 0 0, L_0x1db5140; 1 drivers -v0x1bb21b0_0 .net "c2", 0 0, L_0x1bb2370; 1 drivers -v0x1bb2280_0 .net "carryin", 0 0, L_0x1dbe090; alias, 1 drivers -v0x1bb2400_0 .net "carryout", 0 0, L_0x1db5640; 1 drivers -v0x1bb24a0_0 .net "s1", 0 0, L_0x1db5080; 1 drivers -v0x1bb2540_0 .net "sum", 0 0, L_0x1db52a0; 1 drivers -S_0x1bb1360 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bb1110; +L_0x1248da0/d .functor OR 1, L_0x12488a0, L_0x1044ff0, C4<0>, C4<0>; +L_0x1248da0 .delay 1 (30000,30000,30000) L_0x1248da0/d; +v0x1044b80_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers +v0x1044cd0_0 .net "b", 0 0, L_0x1247eb0; alias, 1 drivers +v0x1044d90_0 .net "c1", 0 0, L_0x12488a0; 1 drivers +v0x1044e30_0 .net "c2", 0 0, L_0x1044ff0; 1 drivers +v0x1044f00_0 .net "carryin", 0 0, L_0x12517d0; alias, 1 drivers +v0x1045080_0 .net "carryout", 0 0, L_0x1248da0; 1 drivers +v0x1045120_0 .net "s1", 0 0, L_0x12487e0; 1 drivers +v0x10451c0_0 .net "sum", 0 0, L_0x1248a00; 1 drivers +S_0x1043fe0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1043d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1db5080/d .functor XOR 1, L_0x1dbde70, L_0x1db4750, C4<0>, C4<0>; -L_0x1db5080 .delay 1 (30000,30000,30000) L_0x1db5080/d; -L_0x1db5140/d .functor AND 1, L_0x1dbde70, L_0x1db4750, C4<1>, C4<1>; -L_0x1db5140 .delay 1 (30000,30000,30000) L_0x1db5140/d; -v0x1bb15c0_0 .net "a", 0 0, L_0x1dbde70; alias, 1 drivers -v0x1bb1680_0 .net "b", 0 0, L_0x1db4750; alias, 1 drivers -v0x1bb1740_0 .net "carryout", 0 0, L_0x1db5140; alias, 1 drivers -v0x1bb17e0_0 .net "sum", 0 0, L_0x1db5080; alias, 1 drivers -S_0x1bb1910 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bb1110; +L_0x12487e0/d .functor XOR 1, L_0x12515b0, L_0x1247eb0, C4<0>, C4<0>; +L_0x12487e0 .delay 1 (30000,30000,30000) L_0x12487e0/d; +L_0x12488a0/d .functor AND 1, L_0x12515b0, L_0x1247eb0, C4<1>, C4<1>; +L_0x12488a0 .delay 1 (30000,30000,30000) L_0x12488a0/d; +v0x1044240_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers +v0x1044300_0 .net "b", 0 0, L_0x1247eb0; alias, 1 drivers +v0x10443c0_0 .net "carryout", 0 0, L_0x12488a0; alias, 1 drivers +v0x1044460_0 .net "sum", 0 0, L_0x12487e0; alias, 1 drivers +S_0x1044590 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1043d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1db52a0/d .functor XOR 1, L_0x1db5080, L_0x1dbe090, C4<0>, C4<0>; -L_0x1db52a0 .delay 1 (30000,30000,30000) L_0x1db52a0/d; -L_0x1bb2370/d .functor AND 1, L_0x1db5080, L_0x1dbe090, C4<1>, C4<1>; -L_0x1bb2370 .delay 1 (30000,30000,30000) L_0x1bb2370/d; -v0x1bb1b70_0 .net "a", 0 0, L_0x1db5080; alias, 1 drivers -v0x1bb1c40_0 .net "b", 0 0, L_0x1dbe090; alias, 1 drivers -v0x1bb1ce0_0 .net "carryout", 0 0, L_0x1bb2370; alias, 1 drivers -v0x1bb1db0_0 .net "sum", 0 0, L_0x1db52a0; alias, 1 drivers -S_0x1bb3960 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1ba3bf0; - .timescale -9 -12; -L_0x7f72592da7f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da840 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dbdf10/d .functor OR 1, L_0x7f72592da7f8, L_0x7f72592da840, C4<0>, C4<0>; -L_0x1dbdf10 .delay 1 (30000,30000,30000) L_0x1dbdf10/d; -v0x1bb3b50_0 .net/2u *"_s0", 0 0, L_0x7f72592da7f8; 1 drivers -v0x1bb3c30_0 .net/2u *"_s2", 0 0, L_0x7f72592da840; 1 drivers -S_0x1bb3d10 .scope generate, "alu_slices[8]" "alu_slices[8]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1b738a0 .param/l "i" 0 3 37, +C4<01000>; -S_0x1bb4020 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bb3d10; +L_0x1248a00/d .functor XOR 1, L_0x12487e0, L_0x12517d0, C4<0>, C4<0>; +L_0x1248a00 .delay 1 (30000,30000,30000) L_0x1248a00/d; +L_0x1044ff0/d .functor AND 1, L_0x12487e0, L_0x12517d0, C4<1>, C4<1>; +L_0x1044ff0 .delay 1 (30000,30000,30000) L_0x1044ff0/d; +v0x10447f0_0 .net "a", 0 0, L_0x12487e0; alias, 1 drivers +v0x10448c0_0 .net "b", 0 0, L_0x12517d0; alias, 1 drivers +v0x1044960_0 .net "carryout", 0 0, L_0x1044ff0; alias, 1 drivers +v0x1044a30_0 .net "sum", 0 0, L_0x1248a00; alias, 1 drivers +S_0x10465e0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1036880; + .timescale -9 -12; +L_0x2b0ab3d057f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05840 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1251650/d .functor OR 1, L_0x2b0ab3d057f8, L_0x2b0ab3d05840, C4<0>, C4<0>; +L_0x1251650 .delay 1 (30000,30000,30000) L_0x1251650/d; +v0x10467d0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d057f8; 1 drivers +v0x10468b0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05840; 1 drivers +S_0x1046990 .scope generate, "alu_slices[8]" "alu_slices[8]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1006530 .param/l "i" 0 3 41, +C4<01000>; +S_0x1046ca0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1046990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -4478,445 +4488,445 @@ S_0x1bb4020 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bb3d10; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1dbb990/d .functor NOT 1, L_0x1dc7b40, C4<0>, C4<0>, C4<0>; -L_0x1dbb990 .delay 1 (10000,10000,10000) L_0x1dbb990/d; -L_0x1dbe3b0/d .functor NOT 1, L_0x1dc7ca0, C4<0>, C4<0>, C4<0>; -L_0x1dbe3b0 .delay 1 (10000,10000,10000) L_0x1dbe3b0/d; -L_0x1dbf3b0/d .functor XOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; -L_0x1dbf3b0 .delay 1 (30000,30000,30000) L_0x1dbf3b0/d; -L_0x7f72592da888 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da8d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dbfa60/d .functor OR 1, L_0x7f72592da888, L_0x7f72592da8d0, C4<0>, C4<0>; -L_0x1dbfa60 .delay 1 (30000,30000,30000) L_0x1dbfa60/d; -L_0x1dbfc60/d .functor AND 1, L_0x1dc7b40, L_0x1dc7ca0, C4<1>, C4<1>; -L_0x1dbfc60 .delay 1 (30000,30000,30000) L_0x1dbfc60/d; -L_0x1dbfd20/d .functor NAND 1, L_0x1dc7b40, L_0x1dc7ca0, C4<1>, C4<1>; -L_0x1dbfd20 .delay 1 (20000,20000,20000) L_0x1dbfd20/d; -L_0x1dbfe80/d .functor XOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; -L_0x1dbfe80 .delay 1 (20000,20000,20000) L_0x1dbfe80/d; -L_0x1dc0330/d .functor OR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; -L_0x1dc0330 .delay 1 (30000,30000,30000) L_0x1dc0330/d; -L_0x1dc7a40/d .functor NOT 1, L_0x1dc3ca0, C4<0>, C4<0>, C4<0>; -L_0x1dc7a40 .delay 1 (10000,10000,10000) L_0x1dc7a40/d; -v0x1bc2750_0 .net "A", 0 0, L_0x1dc7b40; 1 drivers -v0x1bc2810_0 .net "A_", 0 0, L_0x1dbb990; 1 drivers -v0x1bc28d0_0 .net "B", 0 0, L_0x1dc7ca0; 1 drivers -v0x1bc29a0_0 .net "B_", 0 0, L_0x1dbe3b0; 1 drivers -v0x1bc2a40_0 .net *"_s12", 0 0, L_0x1dbfa60; 1 drivers -v0x1bc2b30_0 .net/2s *"_s14", 0 0, L_0x7f72592da888; 1 drivers -v0x1bc2bf0_0 .net/2s *"_s16", 0 0, L_0x7f72592da8d0; 1 drivers -v0x1bc2cd0_0 .net *"_s18", 0 0, L_0x1dbfc60; 1 drivers -v0x1bc2db0_0 .net *"_s20", 0 0, L_0x1dbfd20; 1 drivers -v0x1bc2f20_0 .net *"_s22", 0 0, L_0x1dbfe80; 1 drivers -v0x1bc3000_0 .net *"_s24", 0 0, L_0x1dc0330; 1 drivers -o0x7f7259368d48 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1bc30e0_0 name=_s30 -o0x7f7259368d78 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1bc31c0_0 name=_s32 -v0x1bc32a0_0 .net *"_s8", 0 0, L_0x1dbf3b0; 1 drivers -v0x1bc3380_0 .net "carryin", 0 0, L_0x1dbe240; 1 drivers -v0x1bc3420_0 .net "carryout", 0 0, L_0x1dc76e0; 1 drivers -v0x1bc34c0_0 .net "carryouts", 7 0, L_0x1ebf830; 1 drivers -v0x1bc3670_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bc3710_0 .net "result", 0 0, L_0x1dc3ca0; 1 drivers -v0x1bc3800_0 .net "results", 7 0, L_0x1dc0100; 1 drivers -v0x1bc3910_0 .net "zero", 0 0, L_0x1dc7a40; 1 drivers -LS_0x1dc0100_0_0 .concat8 [ 1 1 1 1], L_0x1dbe8d0, L_0x1dbef00, L_0x1dbf3b0, L_0x1dbfa60; -LS_0x1dc0100_0_4 .concat8 [ 1 1 1 1], L_0x1dbfc60, L_0x1dbfd20, L_0x1dbfe80, L_0x1dc0330; -L_0x1dc0100 .concat8 [ 4 4 0 0], LS_0x1dc0100_0_0, LS_0x1dc0100_0_4; -LS_0x1ebf830_0_0 .concat [ 1 1 1 1], L_0x1dbeb80, L_0x1dbf250, o0x7f7259368d48, L_0x1dbf8b0; -LS_0x1ebf830_0_4 .concat [ 4 0 0 0], o0x7f7259368d78; -L_0x1ebf830 .concat [ 4 4 0 0], LS_0x1ebf830_0_0, LS_0x1ebf830_0_4; -S_0x1bb42a0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bb4020; +L_0x1251aa0/d .functor NOT 1, L_0x125b280, C4<0>, C4<0>, C4<0>; +L_0x1251aa0 .delay 1 (10000,10000,10000) L_0x1251aa0/d; +L_0x1251bb0/d .functor NOT 1, L_0x125b3e0, C4<0>, C4<0>, C4<0>; +L_0x1251bb0 .delay 1 (10000,10000,10000) L_0x1251bb0/d; +L_0x1252af0/d .functor XOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; +L_0x1252af0 .delay 1 (30000,30000,30000) L_0x1252af0/d; +L_0x2b0ab3d05888 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d058d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12531a0/d .functor OR 1, L_0x2b0ab3d05888, L_0x2b0ab3d058d0, C4<0>, C4<0>; +L_0x12531a0 .delay 1 (30000,30000,30000) L_0x12531a0/d; +L_0x12533a0/d .functor AND 1, L_0x125b280, L_0x125b3e0, C4<1>, C4<1>; +L_0x12533a0 .delay 1 (30000,30000,30000) L_0x12533a0/d; +L_0x1253460/d .functor NAND 1, L_0x125b280, L_0x125b3e0, C4<1>, C4<1>; +L_0x1253460 .delay 1 (20000,20000,20000) L_0x1253460/d; +L_0x12535c0/d .functor XOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; +L_0x12535c0 .delay 1 (20000,20000,20000) L_0x12535c0/d; +L_0x1253a70/d .functor OR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; +L_0x1253a70 .delay 1 (30000,30000,30000) L_0x1253a70/d; +L_0x125b180/d .functor NOT 1, L_0x12573e0, C4<0>, C4<0>, C4<0>; +L_0x125b180 .delay 1 (10000,10000,10000) L_0x125b180/d; +v0x10553d0_0 .net "A", 0 0, L_0x125b280; 1 drivers +v0x1055490_0 .net "A_", 0 0, L_0x1251aa0; 1 drivers +v0x1055550_0 .net "B", 0 0, L_0x125b3e0; 1 drivers +v0x1055620_0 .net "B_", 0 0, L_0x1251bb0; 1 drivers +v0x10556c0_0 .net *"_s12", 0 0, L_0x12531a0; 1 drivers +v0x10557b0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05888; 1 drivers +v0x1055870_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d058d0; 1 drivers +v0x1055950_0 .net *"_s18", 0 0, L_0x12533a0; 1 drivers +v0x1055a30_0 .net *"_s20", 0 0, L_0x1253460; 1 drivers +v0x1055ba0_0 .net *"_s22", 0 0, L_0x12535c0; 1 drivers +v0x1055c80_0 .net *"_s24", 0 0, L_0x1253a70; 1 drivers +o0x2b0ab3cb7d48 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1055d60_0 name=_s30 +o0x2b0ab3cb7d78 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1055e40_0 name=_s32 +v0x1055f20_0 .net *"_s8", 0 0, L_0x1252af0; 1 drivers +v0x1056000_0 .net "carryin", 0 0, L_0x1251980; 1 drivers +v0x10560a0_0 .net "carryout", 0 0, L_0x125ae20; 1 drivers +v0x1056140_0 .net "carryouts", 7 0, L_0x1353be0; 1 drivers +v0x10562f0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1056390_0 .net "result", 0 0, L_0x12573e0; 1 drivers +v0x1056480_0 .net "results", 7 0, L_0x1253840; 1 drivers +v0x1056590_0 .net "zero", 0 0, L_0x125b180; 1 drivers +LS_0x1253840_0_0 .concat8 [ 1 1 1 1], L_0x1241910, L_0x1252640, L_0x1252af0, L_0x12531a0; +LS_0x1253840_0_4 .concat8 [ 1 1 1 1], L_0x12533a0, L_0x1253460, L_0x12535c0, L_0x1253a70; +L_0x1253840 .concat8 [ 4 4 0 0], LS_0x1253840_0_0, LS_0x1253840_0_4; +LS_0x1353be0_0_0 .concat [ 1 1 1 1], L_0x12522c0, L_0x1252990, o0x2b0ab3cb7d48, L_0x1252ff0; +LS_0x1353be0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb7d78; +L_0x1353be0 .concat [ 4 4 0 0], LS_0x1353be0_0_0, LS_0x1353be0_0_4; +S_0x1046f20 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1046ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dbeb80/d .functor OR 1, L_0x1dbe660, L_0x1dbea20, C4<0>, C4<0>; -L_0x1dbeb80 .delay 1 (30000,30000,30000) L_0x1dbeb80/d; -v0x1bb50d0_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers -v0x1bb5190_0 .net "b", 0 0, L_0x1dc7ca0; alias, 1 drivers -v0x1bb5260_0 .net "c1", 0 0, L_0x1dbe660; 1 drivers -v0x1bb5360_0 .net "c2", 0 0, L_0x1dbea20; 1 drivers -v0x1bb5430_0 .net "carryin", 0 0, L_0x1dbe240; alias, 1 drivers -v0x1bb5520_0 .net "carryout", 0 0, L_0x1dbeb80; 1 drivers -v0x1bb55c0_0 .net "s1", 0 0, L_0x1dbe5a0; 1 drivers -v0x1bb56b0_0 .net "sum", 0 0, L_0x1dbe8d0; 1 drivers -S_0x1bb4510 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bb42a0; +L_0x12522c0/d .functor OR 1, L_0x1251e60, L_0x1252160, C4<0>, C4<0>; +L_0x12522c0 .delay 1 (30000,30000,30000) L_0x12522c0/d; +v0x1047d50_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers +v0x1047e10_0 .net "b", 0 0, L_0x125b3e0; alias, 1 drivers +v0x1047ee0_0 .net "c1", 0 0, L_0x1251e60; 1 drivers +v0x1047fe0_0 .net "c2", 0 0, L_0x1252160; 1 drivers +v0x10480b0_0 .net "carryin", 0 0, L_0x1251980; alias, 1 drivers +v0x10481a0_0 .net "carryout", 0 0, L_0x12522c0; 1 drivers +v0x1048240_0 .net "s1", 0 0, L_0x1251da0; 1 drivers +v0x1048330_0 .net "sum", 0 0, L_0x1241910; 1 drivers +S_0x1047190 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1046f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dbe5a0/d .functor XOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; -L_0x1dbe5a0 .delay 1 (30000,30000,30000) L_0x1dbe5a0/d; -L_0x1dbe660/d .functor AND 1, L_0x1dc7b40, L_0x1dc7ca0, C4<1>, C4<1>; -L_0x1dbe660 .delay 1 (30000,30000,30000) L_0x1dbe660/d; -v0x1bb4770_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers -v0x1bb4850_0 .net "b", 0 0, L_0x1dc7ca0; alias, 1 drivers -v0x1bb4910_0 .net "carryout", 0 0, L_0x1dbe660; alias, 1 drivers -v0x1bb49b0_0 .net "sum", 0 0, L_0x1dbe5a0; alias, 1 drivers -S_0x1bb4af0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bb42a0; +L_0x1251da0/d .functor XOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; +L_0x1251da0 .delay 1 (30000,30000,30000) L_0x1251da0/d; +L_0x1251e60/d .functor AND 1, L_0x125b280, L_0x125b3e0, C4<1>, C4<1>; +L_0x1251e60 .delay 1 (30000,30000,30000) L_0x1251e60/d; +v0x10473f0_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers +v0x10474d0_0 .net "b", 0 0, L_0x125b3e0; alias, 1 drivers +v0x1047590_0 .net "carryout", 0 0, L_0x1251e60; alias, 1 drivers +v0x1047630_0 .net "sum", 0 0, L_0x1251da0; alias, 1 drivers +S_0x1047770 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1046f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dbe8d0/d .functor XOR 1, L_0x1dbe5a0, L_0x1dbe240, C4<0>, C4<0>; -L_0x1dbe8d0 .delay 1 (30000,30000,30000) L_0x1dbe8d0/d; -L_0x1dbea20/d .functor AND 1, L_0x1dbe5a0, L_0x1dbe240, C4<1>, C4<1>; -L_0x1dbea20 .delay 1 (30000,30000,30000) L_0x1dbea20/d; -v0x1bb4d50_0 .net "a", 0 0, L_0x1dbe5a0; alias, 1 drivers -v0x1bb4df0_0 .net "b", 0 0, L_0x1dbe240; alias, 1 drivers -v0x1bb4e90_0 .net "carryout", 0 0, L_0x1dbea20; alias, 1 drivers -v0x1bb4f60_0 .net "sum", 0 0, L_0x1dbe8d0; alias, 1 drivers -S_0x1bb5780 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bb4020; +L_0x1241910/d .functor XOR 1, L_0x1251da0, L_0x1251980, C4<0>, C4<0>; +L_0x1241910 .delay 1 (30000,30000,30000) L_0x1241910/d; +L_0x1252160/d .functor AND 1, L_0x1251da0, L_0x1251980, C4<1>, C4<1>; +L_0x1252160 .delay 1 (30000,30000,30000) L_0x1252160/d; +v0x10479d0_0 .net "a", 0 0, L_0x1251da0; alias, 1 drivers +v0x1047a70_0 .net "b", 0 0, L_0x1251980; alias, 1 drivers +v0x1047b10_0 .net "carryout", 0 0, L_0x1252160; alias, 1 drivers +v0x1047be0_0 .net "sum", 0 0, L_0x1241910; alias, 1 drivers +S_0x1048400 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1046ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bbab70_0 .net "ands", 7 0, L_0x1dc56e0; 1 drivers -v0x1bbac80_0 .net "in", 7 0, L_0x1ebf830; alias, 1 drivers -v0x1bbad40_0 .net "out", 0 0, L_0x1dc76e0; alias, 1 drivers -v0x1bbae10_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bb59a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bb5780; +v0x104d7f0_0 .net "ands", 7 0, L_0x1258e20; 1 drivers +v0x104d900_0 .net "in", 7 0, L_0x1353be0; alias, 1 drivers +v0x104d9c0_0 .net "out", 0 0, L_0x125ae20; alias, 1 drivers +v0x104da90_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1048620 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1048400; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bb80d0_0 .net "A", 7 0, L_0x1ebf830; alias, 1 drivers -v0x1bb81d0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bb8290_0 .net *"_s0", 0 0, L_0x1dc4000; 1 drivers -v0x1bb8350_0 .net *"_s12", 0 0, L_0x1dc4970; 1 drivers -v0x1bb8430_0 .net *"_s16", 0 0, L_0x1dc4cd0; 1 drivers -v0x1bb8560_0 .net *"_s20", 0 0, L_0x1dc4fe0; 1 drivers -v0x1bb8640_0 .net *"_s24", 0 0, L_0x1dc53d0; 1 drivers -v0x1bb8720_0 .net *"_s28", 0 0, L_0x1dc5360; 1 drivers -v0x1bb8800_0 .net *"_s4", 0 0, L_0x1dc4310; 1 drivers -v0x1bb8970_0 .net *"_s8", 0 0, L_0x1dc4660; 1 drivers -v0x1bb8a50_0 .net "out", 7 0, L_0x1dc56e0; alias, 1 drivers -L_0x1dc40c0 .part L_0x1ebf830, 0, 1; -L_0x1dc4220 .part v0x1d6daa0_0, 0, 1; -L_0x1dc43d0 .part L_0x1ebf830, 1, 1; -L_0x1dc45c0 .part v0x1d6daa0_0, 1, 1; -L_0x1dc4720 .part L_0x1ebf830, 2, 1; -L_0x1dc4880 .part v0x1d6daa0_0, 2, 1; -L_0x1dc4a30 .part L_0x1ebf830, 3, 1; -L_0x1dc4b90 .part v0x1d6daa0_0, 3, 1; -L_0x1dc4d90 .part L_0x1ebf830, 4, 1; -L_0x1dc4ef0 .part v0x1d6daa0_0, 4, 1; -L_0x1dc5050 .part L_0x1ebf830, 5, 1; -L_0x1dc52c0 .part v0x1d6daa0_0, 5, 1; -L_0x1dc5490 .part L_0x1ebf830, 6, 1; -L_0x1dc55f0 .part v0x1d6daa0_0, 6, 1; -LS_0x1dc56e0_0_0 .concat8 [ 1 1 1 1], L_0x1dc4000, L_0x1dc4310, L_0x1dc4660, L_0x1dc4970; -LS_0x1dc56e0_0_4 .concat8 [ 1 1 1 1], L_0x1dc4cd0, L_0x1dc4fe0, L_0x1dc53d0, L_0x1dc5360; -L_0x1dc56e0 .concat8 [ 4 4 0 0], LS_0x1dc56e0_0_0, LS_0x1dc56e0_0_4; -L_0x1dc5aa0 .part L_0x1ebf830, 7, 1; -L_0x1dc5c90 .part v0x1d6daa0_0, 7, 1; -S_0x1bb5c00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb5e10 .param/l "i" 0 4 54, +C4<00>; -L_0x1dc4000/d .functor AND 1, L_0x1dc40c0, L_0x1dc4220, C4<1>, C4<1>; -L_0x1dc4000 .delay 1 (30000,30000,30000) L_0x1dc4000/d; -v0x1bb5ef0_0 .net *"_s0", 0 0, L_0x1dc40c0; 1 drivers -v0x1bb5fd0_0 .net *"_s1", 0 0, L_0x1dc4220; 1 drivers -S_0x1bb60b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb62c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1dc4310/d .functor AND 1, L_0x1dc43d0, L_0x1dc45c0, C4<1>, C4<1>; -L_0x1dc4310 .delay 1 (30000,30000,30000) L_0x1dc4310/d; -v0x1bb6380_0 .net *"_s0", 0 0, L_0x1dc43d0; 1 drivers -v0x1bb6460_0 .net *"_s1", 0 0, L_0x1dc45c0; 1 drivers -S_0x1bb6540 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb6750 .param/l "i" 0 4 54, +C4<010>; -L_0x1dc4660/d .functor AND 1, L_0x1dc4720, L_0x1dc4880, C4<1>, C4<1>; -L_0x1dc4660 .delay 1 (30000,30000,30000) L_0x1dc4660/d; -v0x1bb67f0_0 .net *"_s0", 0 0, L_0x1dc4720; 1 drivers -v0x1bb68d0_0 .net *"_s1", 0 0, L_0x1dc4880; 1 drivers -S_0x1bb69b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb6bc0 .param/l "i" 0 4 54, +C4<011>; -L_0x1dc4970/d .functor AND 1, L_0x1dc4a30, L_0x1dc4b90, C4<1>, C4<1>; -L_0x1dc4970 .delay 1 (30000,30000,30000) L_0x1dc4970/d; -v0x1bb6c80_0 .net *"_s0", 0 0, L_0x1dc4a30; 1 drivers -v0x1bb6d60_0 .net *"_s1", 0 0, L_0x1dc4b90; 1 drivers -S_0x1bb6e40 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb70a0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dc4cd0/d .functor AND 1, L_0x1dc4d90, L_0x1dc4ef0, C4<1>, C4<1>; -L_0x1dc4cd0 .delay 1 (30000,30000,30000) L_0x1dc4cd0/d; -v0x1bb7160_0 .net *"_s0", 0 0, L_0x1dc4d90; 1 drivers -v0x1bb7240_0 .net *"_s1", 0 0, L_0x1dc4ef0; 1 drivers -S_0x1bb7320 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb7530 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dc4fe0/d .functor AND 1, L_0x1dc5050, L_0x1dc52c0, C4<1>, C4<1>; -L_0x1dc4fe0 .delay 1 (30000,30000,30000) L_0x1dc4fe0/d; -v0x1bb75f0_0 .net *"_s0", 0 0, L_0x1dc5050; 1 drivers -v0x1bb76d0_0 .net *"_s1", 0 0, L_0x1dc52c0; 1 drivers -S_0x1bb77b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb79c0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dc53d0/d .functor AND 1, L_0x1dc5490, L_0x1dc55f0, C4<1>, C4<1>; -L_0x1dc53d0 .delay 1 (30000,30000,30000) L_0x1dc53d0/d; -v0x1bb7a80_0 .net *"_s0", 0 0, L_0x1dc5490; 1 drivers -v0x1bb7b60_0 .net *"_s1", 0 0, L_0x1dc55f0; 1 drivers -S_0x1bb7c40 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bb59a0; - .timescale -9 -12; -P_0x1bb7e50 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dc5360/d .functor AND 1, L_0x1dc5aa0, L_0x1dc5c90, C4<1>, C4<1>; -L_0x1dc5360 .delay 1 (30000,30000,30000) L_0x1dc5360/d; -v0x1bb7f10_0 .net *"_s0", 0 0, L_0x1dc5aa0; 1 drivers -v0x1bb7ff0_0 .net *"_s1", 0 0, L_0x1dc5c90; 1 drivers -S_0x1bb8bb0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bb5780; +v0x104ad50_0 .net "A", 7 0, L_0x1353be0; alias, 1 drivers +v0x104ae50_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x104af10_0 .net *"_s0", 0 0, L_0x1257740; 1 drivers +v0x104afd0_0 .net *"_s12", 0 0, L_0x12580b0; 1 drivers +v0x104b0b0_0 .net *"_s16", 0 0, L_0x1258410; 1 drivers +v0x104b1e0_0 .net *"_s20", 0 0, L_0x1258720; 1 drivers +v0x104b2c0_0 .net *"_s24", 0 0, L_0x1258b10; 1 drivers +v0x104b3a0_0 .net *"_s28", 0 0, L_0x1258aa0; 1 drivers +v0x104b480_0 .net *"_s4", 0 0, L_0x1257a50; 1 drivers +v0x104b5f0_0 .net *"_s8", 0 0, L_0x1257da0; 1 drivers +v0x104b6d0_0 .net "out", 7 0, L_0x1258e20; alias, 1 drivers +L_0x1257800 .part L_0x1353be0, 0, 1; +L_0x1257960 .part v0x12010b0_0, 0, 1; +L_0x1257b10 .part L_0x1353be0, 1, 1; +L_0x1257d00 .part v0x12010b0_0, 1, 1; +L_0x1257e60 .part L_0x1353be0, 2, 1; +L_0x1257fc0 .part v0x12010b0_0, 2, 1; +L_0x1258170 .part L_0x1353be0, 3, 1; +L_0x12582d0 .part v0x12010b0_0, 3, 1; +L_0x12584d0 .part L_0x1353be0, 4, 1; +L_0x1258630 .part v0x12010b0_0, 4, 1; +L_0x1258790 .part L_0x1353be0, 5, 1; +L_0x1258a00 .part v0x12010b0_0, 5, 1; +L_0x1258bd0 .part L_0x1353be0, 6, 1; +L_0x1258d30 .part v0x12010b0_0, 6, 1; +LS_0x1258e20_0_0 .concat8 [ 1 1 1 1], L_0x1257740, L_0x1257a50, L_0x1257da0, L_0x12580b0; +LS_0x1258e20_0_4 .concat8 [ 1 1 1 1], L_0x1258410, L_0x1258720, L_0x1258b10, L_0x1258aa0; +L_0x1258e20 .concat8 [ 4 4 0 0], LS_0x1258e20_0_0, LS_0x1258e20_0_4; +L_0x12591e0 .part L_0x1353be0, 7, 1; +L_0x12593d0 .part v0x12010b0_0, 7, 1; +S_0x1048880 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x1048a90 .param/l "i" 0 4 54, +C4<00>; +L_0x1257740/d .functor AND 1, L_0x1257800, L_0x1257960, C4<1>, C4<1>; +L_0x1257740 .delay 1 (30000,30000,30000) L_0x1257740/d; +v0x1048b70_0 .net *"_s0", 0 0, L_0x1257800; 1 drivers +v0x1048c50_0 .net *"_s1", 0 0, L_0x1257960; 1 drivers +S_0x1048d30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x1048f40 .param/l "i" 0 4 54, +C4<01>; +L_0x1257a50/d .functor AND 1, L_0x1257b10, L_0x1257d00, C4<1>, C4<1>; +L_0x1257a50 .delay 1 (30000,30000,30000) L_0x1257a50/d; +v0x1049000_0 .net *"_s0", 0 0, L_0x1257b10; 1 drivers +v0x10490e0_0 .net *"_s1", 0 0, L_0x1257d00; 1 drivers +S_0x10491c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x10493d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1257da0/d .functor AND 1, L_0x1257e60, L_0x1257fc0, C4<1>, C4<1>; +L_0x1257da0 .delay 1 (30000,30000,30000) L_0x1257da0/d; +v0x1049470_0 .net *"_s0", 0 0, L_0x1257e60; 1 drivers +v0x1049550_0 .net *"_s1", 0 0, L_0x1257fc0; 1 drivers +S_0x1049630 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x1049840 .param/l "i" 0 4 54, +C4<011>; +L_0x12580b0/d .functor AND 1, L_0x1258170, L_0x12582d0, C4<1>, C4<1>; +L_0x12580b0 .delay 1 (30000,30000,30000) L_0x12580b0/d; +v0x1049900_0 .net *"_s0", 0 0, L_0x1258170; 1 drivers +v0x10499e0_0 .net *"_s1", 0 0, L_0x12582d0; 1 drivers +S_0x1049ac0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x1049d20 .param/l "i" 0 4 54, +C4<0100>; +L_0x1258410/d .functor AND 1, L_0x12584d0, L_0x1258630, C4<1>, C4<1>; +L_0x1258410 .delay 1 (30000,30000,30000) L_0x1258410/d; +v0x1049de0_0 .net *"_s0", 0 0, L_0x12584d0; 1 drivers +v0x1049ec0_0 .net *"_s1", 0 0, L_0x1258630; 1 drivers +S_0x1049fa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x104a1b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1258720/d .functor AND 1, L_0x1258790, L_0x1258a00, C4<1>, C4<1>; +L_0x1258720 .delay 1 (30000,30000,30000) L_0x1258720/d; +v0x104a270_0 .net *"_s0", 0 0, L_0x1258790; 1 drivers +v0x104a350_0 .net *"_s1", 0 0, L_0x1258a00; 1 drivers +S_0x104a430 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x104a640 .param/l "i" 0 4 54, +C4<0110>; +L_0x1258b10/d .functor AND 1, L_0x1258bd0, L_0x1258d30, C4<1>, C4<1>; +L_0x1258b10 .delay 1 (30000,30000,30000) L_0x1258b10/d; +v0x104a700_0 .net *"_s0", 0 0, L_0x1258bd0; 1 drivers +v0x104a7e0_0 .net *"_s1", 0 0, L_0x1258d30; 1 drivers +S_0x104a8c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1048620; + .timescale -9 -12; +P_0x104aad0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1258aa0/d .functor AND 1, L_0x12591e0, L_0x12593d0, C4<1>, C4<1>; +L_0x1258aa0 .delay 1 (30000,30000,30000) L_0x1258aa0/d; +v0x104ab90_0 .net *"_s0", 0 0, L_0x12591e0; 1 drivers +v0x104ac70_0 .net *"_s1", 0 0, L_0x12593d0; 1 drivers +S_0x104b830 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1048400; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dc76e0/d .functor OR 1, L_0x1dc77a0, L_0x1dc7950, C4<0>, C4<0>; -L_0x1dc76e0 .delay 1 (30000,30000,30000) L_0x1dc76e0/d; -v0x1bba700_0 .net *"_s10", 0 0, L_0x1dc77a0; 1 drivers -v0x1bba7e0_0 .net *"_s12", 0 0, L_0x1dc7950; 1 drivers -v0x1bba8c0_0 .net "in", 7 0, L_0x1dc56e0; alias, 1 drivers -v0x1bba990_0 .net "ors", 1 0, L_0x1dc7500; 1 drivers -v0x1bbaa50_0 .net "out", 0 0, L_0x1dc76e0; alias, 1 drivers -L_0x1dc68d0 .part L_0x1dc56e0, 0, 4; -L_0x1dc7500 .concat8 [ 1 1 0 0], L_0x1dc65c0, L_0x1dc71f0; -L_0x1dc7640 .part L_0x1dc56e0, 4, 4; -L_0x1dc77a0 .part L_0x1dc7500, 0, 1; -L_0x1dc7950 .part L_0x1dc7500, 1, 1; -S_0x1bb8d70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bb8bb0; +L_0x125ae20/d .functor OR 1, L_0x125aee0, L_0x125b090, C4<0>, C4<0>; +L_0x125ae20 .delay 1 (30000,30000,30000) L_0x125ae20/d; +v0x104d380_0 .net *"_s10", 0 0, L_0x125aee0; 1 drivers +v0x104d460_0 .net *"_s12", 0 0, L_0x125b090; 1 drivers +v0x104d540_0 .net "in", 7 0, L_0x1258e20; alias, 1 drivers +v0x104d610_0 .net "ors", 1 0, L_0x125ac40; 1 drivers +v0x104d6d0_0 .net "out", 0 0, L_0x125ae20; alias, 1 drivers +L_0x125a010 .part L_0x1258e20, 0, 4; +L_0x125ac40 .concat8 [ 1 1 0 0], L_0x1259d00, L_0x125a930; +L_0x125ad80 .part L_0x1258e20, 4, 4; +L_0x125aee0 .part L_0x125ac40, 0, 1; +L_0x125b090 .part L_0x125ac40, 1, 1; +S_0x104b9f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x104b830; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dc5d80/d .functor OR 1, L_0x1dc5e40, L_0x1dc5fa0, C4<0>, C4<0>; -L_0x1dc5d80 .delay 1 (30000,30000,30000) L_0x1dc5d80/d; -L_0x1dc61d0/d .functor OR 1, L_0x1dc62e0, L_0x1dc6440, C4<0>, C4<0>; -L_0x1dc61d0 .delay 1 (30000,30000,30000) L_0x1dc61d0/d; -L_0x1dc65c0/d .functor OR 1, L_0x1dc6630, L_0x1dc67e0, C4<0>, C4<0>; -L_0x1dc65c0 .delay 1 (30000,30000,30000) L_0x1dc65c0/d; -v0x1bb8fc0_0 .net *"_s0", 0 0, L_0x1dc5d80; 1 drivers -v0x1bb90c0_0 .net *"_s10", 0 0, L_0x1dc62e0; 1 drivers -v0x1bb91a0_0 .net *"_s12", 0 0, L_0x1dc6440; 1 drivers -v0x1bb9260_0 .net *"_s14", 0 0, L_0x1dc6630; 1 drivers -v0x1bb9340_0 .net *"_s16", 0 0, L_0x1dc67e0; 1 drivers -v0x1bb9470_0 .net *"_s3", 0 0, L_0x1dc5e40; 1 drivers -v0x1bb9550_0 .net *"_s5", 0 0, L_0x1dc5fa0; 1 drivers -v0x1bb9630_0 .net *"_s6", 0 0, L_0x1dc61d0; 1 drivers -v0x1bb9710_0 .net "in", 3 0, L_0x1dc68d0; 1 drivers -v0x1bb9880_0 .net "ors", 1 0, L_0x1dc60e0; 1 drivers -v0x1bb9960_0 .net "out", 0 0, L_0x1dc65c0; 1 drivers -L_0x1dc5e40 .part L_0x1dc68d0, 0, 1; -L_0x1dc5fa0 .part L_0x1dc68d0, 1, 1; -L_0x1dc60e0 .concat8 [ 1 1 0 0], L_0x1dc5d80, L_0x1dc61d0; -L_0x1dc62e0 .part L_0x1dc68d0, 2, 1; -L_0x1dc6440 .part L_0x1dc68d0, 3, 1; -L_0x1dc6630 .part L_0x1dc60e0, 0, 1; -L_0x1dc67e0 .part L_0x1dc60e0, 1, 1; -S_0x1bb9a80 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bb8bb0; +L_0x12594c0/d .functor OR 1, L_0x1259580, L_0x12596e0, C4<0>, C4<0>; +L_0x12594c0 .delay 1 (30000,30000,30000) L_0x12594c0/d; +L_0x1259910/d .functor OR 1, L_0x1259a20, L_0x1259b80, C4<0>, C4<0>; +L_0x1259910 .delay 1 (30000,30000,30000) L_0x1259910/d; +L_0x1259d00/d .functor OR 1, L_0x1259d70, L_0x1259f20, C4<0>, C4<0>; +L_0x1259d00 .delay 1 (30000,30000,30000) L_0x1259d00/d; +v0x104bc40_0 .net *"_s0", 0 0, L_0x12594c0; 1 drivers +v0x104bd40_0 .net *"_s10", 0 0, L_0x1259a20; 1 drivers +v0x104be20_0 .net *"_s12", 0 0, L_0x1259b80; 1 drivers +v0x104bee0_0 .net *"_s14", 0 0, L_0x1259d70; 1 drivers +v0x104bfc0_0 .net *"_s16", 0 0, L_0x1259f20; 1 drivers +v0x104c0f0_0 .net *"_s3", 0 0, L_0x1259580; 1 drivers +v0x104c1d0_0 .net *"_s5", 0 0, L_0x12596e0; 1 drivers +v0x104c2b0_0 .net *"_s6", 0 0, L_0x1259910; 1 drivers +v0x104c390_0 .net "in", 3 0, L_0x125a010; 1 drivers +v0x104c500_0 .net "ors", 1 0, L_0x1259820; 1 drivers +v0x104c5e0_0 .net "out", 0 0, L_0x1259d00; 1 drivers +L_0x1259580 .part L_0x125a010, 0, 1; +L_0x12596e0 .part L_0x125a010, 1, 1; +L_0x1259820 .concat8 [ 1 1 0 0], L_0x12594c0, L_0x1259910; +L_0x1259a20 .part L_0x125a010, 2, 1; +L_0x1259b80 .part L_0x125a010, 3, 1; +L_0x1259d70 .part L_0x1259820, 0, 1; +L_0x1259f20 .part L_0x1259820, 1, 1; +S_0x104c700 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x104b830; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dc6a00/d .functor OR 1, L_0x1dc6a70, L_0x1dc6bd0, C4<0>, C4<0>; -L_0x1dc6a00 .delay 1 (30000,30000,30000) L_0x1dc6a00/d; -L_0x1dc6e00/d .functor OR 1, L_0x1dc6f10, L_0x1dc7070, C4<0>, C4<0>; -L_0x1dc6e00 .delay 1 (30000,30000,30000) L_0x1dc6e00/d; -L_0x1dc71f0/d .functor OR 1, L_0x1dc7260, L_0x1dc7410, C4<0>, C4<0>; -L_0x1dc71f0 .delay 1 (30000,30000,30000) L_0x1dc71f0/d; -v0x1bb9c40_0 .net *"_s0", 0 0, L_0x1dc6a00; 1 drivers -v0x1bb9d40_0 .net *"_s10", 0 0, L_0x1dc6f10; 1 drivers -v0x1bb9e20_0 .net *"_s12", 0 0, L_0x1dc7070; 1 drivers -v0x1bb9ee0_0 .net *"_s14", 0 0, L_0x1dc7260; 1 drivers -v0x1bb9fc0_0 .net *"_s16", 0 0, L_0x1dc7410; 1 drivers -v0x1bba0f0_0 .net *"_s3", 0 0, L_0x1dc6a70; 1 drivers -v0x1bba1d0_0 .net *"_s5", 0 0, L_0x1dc6bd0; 1 drivers -v0x1bba2b0_0 .net *"_s6", 0 0, L_0x1dc6e00; 1 drivers -v0x1bba390_0 .net "in", 3 0, L_0x1dc7640; 1 drivers -v0x1bba500_0 .net "ors", 1 0, L_0x1dc6d10; 1 drivers -v0x1bba5e0_0 .net "out", 0 0, L_0x1dc71f0; 1 drivers -L_0x1dc6a70 .part L_0x1dc7640, 0, 1; -L_0x1dc6bd0 .part L_0x1dc7640, 1, 1; -L_0x1dc6d10 .concat8 [ 1 1 0 0], L_0x1dc6a00, L_0x1dc6e00; -L_0x1dc6f10 .part L_0x1dc7640, 2, 1; -L_0x1dc7070 .part L_0x1dc7640, 3, 1; -L_0x1dc7260 .part L_0x1dc6d10, 0, 1; -L_0x1dc7410 .part L_0x1dc6d10, 1, 1; -S_0x1bbaef0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bb4020; +L_0x125a140/d .functor OR 1, L_0x125a1b0, L_0x125a310, C4<0>, C4<0>; +L_0x125a140 .delay 1 (30000,30000,30000) L_0x125a140/d; +L_0x125a540/d .functor OR 1, L_0x125a650, L_0x125a7b0, C4<0>, C4<0>; +L_0x125a540 .delay 1 (30000,30000,30000) L_0x125a540/d; +L_0x125a930/d .functor OR 1, L_0x125a9a0, L_0x125ab50, C4<0>, C4<0>; +L_0x125a930 .delay 1 (30000,30000,30000) L_0x125a930/d; +v0x104c8c0_0 .net *"_s0", 0 0, L_0x125a140; 1 drivers +v0x104c9c0_0 .net *"_s10", 0 0, L_0x125a650; 1 drivers +v0x104caa0_0 .net *"_s12", 0 0, L_0x125a7b0; 1 drivers +v0x104cb60_0 .net *"_s14", 0 0, L_0x125a9a0; 1 drivers +v0x104cc40_0 .net *"_s16", 0 0, L_0x125ab50; 1 drivers +v0x104cd70_0 .net *"_s3", 0 0, L_0x125a1b0; 1 drivers +v0x104ce50_0 .net *"_s5", 0 0, L_0x125a310; 1 drivers +v0x104cf30_0 .net *"_s6", 0 0, L_0x125a540; 1 drivers +v0x104d010_0 .net "in", 3 0, L_0x125ad80; 1 drivers +v0x104d180_0 .net "ors", 1 0, L_0x125a450; 1 drivers +v0x104d260_0 .net "out", 0 0, L_0x125a930; 1 drivers +L_0x125a1b0 .part L_0x125ad80, 0, 1; +L_0x125a310 .part L_0x125ad80, 1, 1; +L_0x125a450 .concat8 [ 1 1 0 0], L_0x125a140, L_0x125a540; +L_0x125a650 .part L_0x125ad80, 2, 1; +L_0x125a7b0 .part L_0x125ad80, 3, 1; +L_0x125a9a0 .part L_0x125a450, 0, 1; +L_0x125ab50 .part L_0x125a450, 1, 1; +S_0x104db70 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1046ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bc0320_0 .net "ands", 7 0, L_0x1dc1ca0; 1 drivers -v0x1bc0430_0 .net "in", 7 0, L_0x1dc0100; alias, 1 drivers -v0x1bc04f0_0 .net "out", 0 0, L_0x1dc3ca0; alias, 1 drivers -v0x1bc05c0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bbb140 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bbaef0; +v0x1052fa0_0 .net "ands", 7 0, L_0x12553e0; 1 drivers +v0x10530b0_0 .net "in", 7 0, L_0x1253840; alias, 1 drivers +v0x1053170_0 .net "out", 0 0, L_0x12573e0; alias, 1 drivers +v0x1053240_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x104ddc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x104db70; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bbd880_0 .net "A", 7 0, L_0x1dc0100; alias, 1 drivers -v0x1bbd980_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bbda40_0 .net *"_s0", 0 0, L_0x1dc0490; 1 drivers -v0x1bbdb00_0 .net *"_s12", 0 0, L_0x1dc0e50; 1 drivers -v0x1bbdbe0_0 .net *"_s16", 0 0, L_0x1dc11b0; 1 drivers -v0x1bbdd10_0 .net *"_s20", 0 0, L_0x1dc15e0; 1 drivers -v0x1bbddf0_0 .net *"_s24", 0 0, L_0x1dc1910; 1 drivers -v0x1bbded0_0 .net *"_s28", 0 0, L_0x1dc18a0; 1 drivers -v0x1bbdfb0_0 .net *"_s4", 0 0, L_0x1dc0830; 1 drivers -v0x1bbe120_0 .net *"_s8", 0 0, L_0x1dc0b40; 1 drivers -v0x1bbe200_0 .net "out", 7 0, L_0x1dc1ca0; alias, 1 drivers -L_0x1dc05a0 .part L_0x1dc0100, 0, 1; -L_0x1dc0790 .part v0x1d6daa0_0, 0, 1; -L_0x1dc08f0 .part L_0x1dc0100, 1, 1; -L_0x1dc0a50 .part v0x1d6daa0_0, 1, 1; -L_0x1dc0c00 .part L_0x1dc0100, 2, 1; -L_0x1dc0d60 .part v0x1d6daa0_0, 2, 1; -L_0x1dc0f10 .part L_0x1dc0100, 3, 1; -L_0x1dc1070 .part v0x1d6daa0_0, 3, 1; -L_0x1dc1270 .part L_0x1dc0100, 4, 1; -L_0x1dc14e0 .part v0x1d6daa0_0, 4, 1; -L_0x1dc1650 .part L_0x1dc0100, 5, 1; -L_0x1dc17b0 .part v0x1d6daa0_0, 5, 1; -L_0x1dc19d0 .part L_0x1dc0100, 6, 1; -L_0x1dc1b30 .part v0x1d6daa0_0, 6, 1; -LS_0x1dc1ca0_0_0 .concat8 [ 1 1 1 1], L_0x1dc0490, L_0x1dc0830, L_0x1dc0b40, L_0x1dc0e50; -LS_0x1dc1ca0_0_4 .concat8 [ 1 1 1 1], L_0x1dc11b0, L_0x1dc15e0, L_0x1dc1910, L_0x1dc18a0; -L_0x1dc1ca0 .concat8 [ 4 4 0 0], LS_0x1dc1ca0_0_0, LS_0x1dc1ca0_0_4; -L_0x1dc2060 .part L_0x1dc0100, 7, 1; -L_0x1dc2250 .part v0x1d6daa0_0, 7, 1; -S_0x1bbb380 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbb590 .param/l "i" 0 4 54, +C4<00>; -L_0x1dc0490/d .functor AND 1, L_0x1dc05a0, L_0x1dc0790, C4<1>, C4<1>; -L_0x1dc0490 .delay 1 (30000,30000,30000) L_0x1dc0490/d; -v0x1bbb670_0 .net *"_s0", 0 0, L_0x1dc05a0; 1 drivers -v0x1bbb750_0 .net *"_s1", 0 0, L_0x1dc0790; 1 drivers -S_0x1bbb830 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbba40 .param/l "i" 0 4 54, +C4<01>; -L_0x1dc0830/d .functor AND 1, L_0x1dc08f0, L_0x1dc0a50, C4<1>, C4<1>; -L_0x1dc0830 .delay 1 (30000,30000,30000) L_0x1dc0830/d; -v0x1bbbb00_0 .net *"_s0", 0 0, L_0x1dc08f0; 1 drivers -v0x1bbbbe0_0 .net *"_s1", 0 0, L_0x1dc0a50; 1 drivers -S_0x1bbbcc0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbbf00 .param/l "i" 0 4 54, +C4<010>; -L_0x1dc0b40/d .functor AND 1, L_0x1dc0c00, L_0x1dc0d60, C4<1>, C4<1>; -L_0x1dc0b40 .delay 1 (30000,30000,30000) L_0x1dc0b40/d; -v0x1bbbfa0_0 .net *"_s0", 0 0, L_0x1dc0c00; 1 drivers -v0x1bbc080_0 .net *"_s1", 0 0, L_0x1dc0d60; 1 drivers -S_0x1bbc160 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbc370 .param/l "i" 0 4 54, +C4<011>; -L_0x1dc0e50/d .functor AND 1, L_0x1dc0f10, L_0x1dc1070, C4<1>, C4<1>; -L_0x1dc0e50 .delay 1 (30000,30000,30000) L_0x1dc0e50/d; -v0x1bbc430_0 .net *"_s0", 0 0, L_0x1dc0f10; 1 drivers -v0x1bbc510_0 .net *"_s1", 0 0, L_0x1dc1070; 1 drivers -S_0x1bbc5f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbc850 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dc11b0/d .functor AND 1, L_0x1dc1270, L_0x1dc14e0, C4<1>, C4<1>; -L_0x1dc11b0 .delay 1 (30000,30000,30000) L_0x1dc11b0/d; -v0x1bbc910_0 .net *"_s0", 0 0, L_0x1dc1270; 1 drivers -v0x1bbc9f0_0 .net *"_s1", 0 0, L_0x1dc14e0; 1 drivers -S_0x1bbcad0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbcce0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dc15e0/d .functor AND 1, L_0x1dc1650, L_0x1dc17b0, C4<1>, C4<1>; -L_0x1dc15e0 .delay 1 (30000,30000,30000) L_0x1dc15e0/d; -v0x1bbcda0_0 .net *"_s0", 0 0, L_0x1dc1650; 1 drivers -v0x1bbce80_0 .net *"_s1", 0 0, L_0x1dc17b0; 1 drivers -S_0x1bbcf60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbd170 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dc1910/d .functor AND 1, L_0x1dc19d0, L_0x1dc1b30, C4<1>, C4<1>; -L_0x1dc1910 .delay 1 (30000,30000,30000) L_0x1dc1910/d; -v0x1bbd230_0 .net *"_s0", 0 0, L_0x1dc19d0; 1 drivers -v0x1bbd310_0 .net *"_s1", 0 0, L_0x1dc1b30; 1 drivers -S_0x1bbd3f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bbb140; - .timescale -9 -12; -P_0x1bbd600 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dc18a0/d .functor AND 1, L_0x1dc2060, L_0x1dc2250, C4<1>, C4<1>; -L_0x1dc18a0 .delay 1 (30000,30000,30000) L_0x1dc18a0/d; -v0x1bbd6c0_0 .net *"_s0", 0 0, L_0x1dc2060; 1 drivers -v0x1bbd7a0_0 .net *"_s1", 0 0, L_0x1dc2250; 1 drivers -S_0x1bbe360 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bbaef0; +v0x1050500_0 .net "A", 7 0, L_0x1253840; alias, 1 drivers +v0x1050600_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10506c0_0 .net *"_s0", 0 0, L_0x1253bd0; 1 drivers +v0x1050780_0 .net *"_s12", 0 0, L_0x1254590; 1 drivers +v0x1050860_0 .net *"_s16", 0 0, L_0x12548f0; 1 drivers +v0x1050990_0 .net *"_s20", 0 0, L_0x1254d20; 1 drivers +v0x1050a70_0 .net *"_s24", 0 0, L_0x1255050; 1 drivers +v0x1050b50_0 .net *"_s28", 0 0, L_0x1254fe0; 1 drivers +v0x1050c30_0 .net *"_s4", 0 0, L_0x1253f70; 1 drivers +v0x1050da0_0 .net *"_s8", 0 0, L_0x1254280; 1 drivers +v0x1050e80_0 .net "out", 7 0, L_0x12553e0; alias, 1 drivers +L_0x1253ce0 .part L_0x1253840, 0, 1; +L_0x1253ed0 .part v0x12010b0_0, 0, 1; +L_0x1254030 .part L_0x1253840, 1, 1; +L_0x1254190 .part v0x12010b0_0, 1, 1; +L_0x1254340 .part L_0x1253840, 2, 1; +L_0x12544a0 .part v0x12010b0_0, 2, 1; +L_0x1254650 .part L_0x1253840, 3, 1; +L_0x12547b0 .part v0x12010b0_0, 3, 1; +L_0x12549b0 .part L_0x1253840, 4, 1; +L_0x1254c20 .part v0x12010b0_0, 4, 1; +L_0x1254d90 .part L_0x1253840, 5, 1; +L_0x1254ef0 .part v0x12010b0_0, 5, 1; +L_0x1255110 .part L_0x1253840, 6, 1; +L_0x1255270 .part v0x12010b0_0, 6, 1; +LS_0x12553e0_0_0 .concat8 [ 1 1 1 1], L_0x1253bd0, L_0x1253f70, L_0x1254280, L_0x1254590; +LS_0x12553e0_0_4 .concat8 [ 1 1 1 1], L_0x12548f0, L_0x1254d20, L_0x1255050, L_0x1254fe0; +L_0x12553e0 .concat8 [ 4 4 0 0], LS_0x12553e0_0_0, LS_0x12553e0_0_4; +L_0x12557a0 .part L_0x1253840, 7, 1; +L_0x1255990 .part v0x12010b0_0, 7, 1; +S_0x104e000 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104e210 .param/l "i" 0 4 54, +C4<00>; +L_0x1253bd0/d .functor AND 1, L_0x1253ce0, L_0x1253ed0, C4<1>, C4<1>; +L_0x1253bd0 .delay 1 (30000,30000,30000) L_0x1253bd0/d; +v0x104e2f0_0 .net *"_s0", 0 0, L_0x1253ce0; 1 drivers +v0x104e3d0_0 .net *"_s1", 0 0, L_0x1253ed0; 1 drivers +S_0x104e4b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104e6c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1253f70/d .functor AND 1, L_0x1254030, L_0x1254190, C4<1>, C4<1>; +L_0x1253f70 .delay 1 (30000,30000,30000) L_0x1253f70/d; +v0x104e780_0 .net *"_s0", 0 0, L_0x1254030; 1 drivers +v0x104e860_0 .net *"_s1", 0 0, L_0x1254190; 1 drivers +S_0x104e940 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104eb80 .param/l "i" 0 4 54, +C4<010>; +L_0x1254280/d .functor AND 1, L_0x1254340, L_0x12544a0, C4<1>, C4<1>; +L_0x1254280 .delay 1 (30000,30000,30000) L_0x1254280/d; +v0x104ec20_0 .net *"_s0", 0 0, L_0x1254340; 1 drivers +v0x104ed00_0 .net *"_s1", 0 0, L_0x12544a0; 1 drivers +S_0x104ede0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104eff0 .param/l "i" 0 4 54, +C4<011>; +L_0x1254590/d .functor AND 1, L_0x1254650, L_0x12547b0, C4<1>, C4<1>; +L_0x1254590 .delay 1 (30000,30000,30000) L_0x1254590/d; +v0x104f0b0_0 .net *"_s0", 0 0, L_0x1254650; 1 drivers +v0x104f190_0 .net *"_s1", 0 0, L_0x12547b0; 1 drivers +S_0x104f270 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104f4d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12548f0/d .functor AND 1, L_0x12549b0, L_0x1254c20, C4<1>, C4<1>; +L_0x12548f0 .delay 1 (30000,30000,30000) L_0x12548f0/d; +v0x104f590_0 .net *"_s0", 0 0, L_0x12549b0; 1 drivers +v0x104f670_0 .net *"_s1", 0 0, L_0x1254c20; 1 drivers +S_0x104f750 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104f960 .param/l "i" 0 4 54, +C4<0101>; +L_0x1254d20/d .functor AND 1, L_0x1254d90, L_0x1254ef0, C4<1>, C4<1>; +L_0x1254d20 .delay 1 (30000,30000,30000) L_0x1254d20/d; +v0x104fa20_0 .net *"_s0", 0 0, L_0x1254d90; 1 drivers +v0x104fb00_0 .net *"_s1", 0 0, L_0x1254ef0; 1 drivers +S_0x104fbe0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x104fdf0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1255050/d .functor AND 1, L_0x1255110, L_0x1255270, C4<1>, C4<1>; +L_0x1255050 .delay 1 (30000,30000,30000) L_0x1255050/d; +v0x104feb0_0 .net *"_s0", 0 0, L_0x1255110; 1 drivers +v0x104ff90_0 .net *"_s1", 0 0, L_0x1255270; 1 drivers +S_0x1050070 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x104ddc0; + .timescale -9 -12; +P_0x1050280 .param/l "i" 0 4 54, +C4<0111>; +L_0x1254fe0/d .functor AND 1, L_0x12557a0, L_0x1255990, C4<1>, C4<1>; +L_0x1254fe0 .delay 1 (30000,30000,30000) L_0x1254fe0/d; +v0x1050340_0 .net *"_s0", 0 0, L_0x12557a0; 1 drivers +v0x1050420_0 .net *"_s1", 0 0, L_0x1255990; 1 drivers +S_0x1050fe0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x104db70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dc3ca0/d .functor OR 1, L_0x1dc3d60, L_0x1dc3f10, C4<0>, C4<0>; -L_0x1dc3ca0 .delay 1 (30000,30000,30000) L_0x1dc3ca0/d; -v0x1bbfeb0_0 .net *"_s10", 0 0, L_0x1dc3d60; 1 drivers -v0x1bbff90_0 .net *"_s12", 0 0, L_0x1dc3f10; 1 drivers -v0x1bc0070_0 .net "in", 7 0, L_0x1dc1ca0; alias, 1 drivers -v0x1bc0140_0 .net "ors", 1 0, L_0x1dc3ac0; 1 drivers -v0x1bc0200_0 .net "out", 0 0, L_0x1dc3ca0; alias, 1 drivers -L_0x1dc2e90 .part L_0x1dc1ca0, 0, 4; -L_0x1dc3ac0 .concat8 [ 1 1 0 0], L_0x1dc2b80, L_0x1dc37b0; -L_0x1dc3c00 .part L_0x1dc1ca0, 4, 4; -L_0x1dc3d60 .part L_0x1dc3ac0, 0, 1; -L_0x1dc3f10 .part L_0x1dc3ac0, 1, 1; -S_0x1bbe520 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bbe360; +L_0x12573e0/d .functor OR 1, L_0x12574a0, L_0x1257650, C4<0>, C4<0>; +L_0x12573e0 .delay 1 (30000,30000,30000) L_0x12573e0/d; +v0x1052b30_0 .net *"_s10", 0 0, L_0x12574a0; 1 drivers +v0x1052c10_0 .net *"_s12", 0 0, L_0x1257650; 1 drivers +v0x1052cf0_0 .net "in", 7 0, L_0x12553e0; alias, 1 drivers +v0x1052dc0_0 .net "ors", 1 0, L_0x1257200; 1 drivers +v0x1052e80_0 .net "out", 0 0, L_0x12573e0; alias, 1 drivers +L_0x12565d0 .part L_0x12553e0, 0, 4; +L_0x1257200 .concat8 [ 1 1 0 0], L_0x12562c0, L_0x1256ef0; +L_0x1257340 .part L_0x12553e0, 4, 4; +L_0x12574a0 .part L_0x1257200, 0, 1; +L_0x1257650 .part L_0x1257200, 1, 1; +S_0x10511a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1050fe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dc2340/d .functor OR 1, L_0x1dc2400, L_0x1dc2560, C4<0>, C4<0>; -L_0x1dc2340 .delay 1 (30000,30000,30000) L_0x1dc2340/d; -L_0x1dc2790/d .functor OR 1, L_0x1dc28a0, L_0x1dc2a00, C4<0>, C4<0>; -L_0x1dc2790 .delay 1 (30000,30000,30000) L_0x1dc2790/d; -L_0x1dc2b80/d .functor OR 1, L_0x1dc2bf0, L_0x1dc2da0, C4<0>, C4<0>; -L_0x1dc2b80 .delay 1 (30000,30000,30000) L_0x1dc2b80/d; -v0x1bbe770_0 .net *"_s0", 0 0, L_0x1dc2340; 1 drivers -v0x1bbe870_0 .net *"_s10", 0 0, L_0x1dc28a0; 1 drivers -v0x1bbe950_0 .net *"_s12", 0 0, L_0x1dc2a00; 1 drivers -v0x1bbea10_0 .net *"_s14", 0 0, L_0x1dc2bf0; 1 drivers -v0x1bbeaf0_0 .net *"_s16", 0 0, L_0x1dc2da0; 1 drivers -v0x1bbec20_0 .net *"_s3", 0 0, L_0x1dc2400; 1 drivers -v0x1bbed00_0 .net *"_s5", 0 0, L_0x1dc2560; 1 drivers -v0x1bbede0_0 .net *"_s6", 0 0, L_0x1dc2790; 1 drivers -v0x1bbeec0_0 .net "in", 3 0, L_0x1dc2e90; 1 drivers -v0x1bbf030_0 .net "ors", 1 0, L_0x1dc26a0; 1 drivers -v0x1bbf110_0 .net "out", 0 0, L_0x1dc2b80; 1 drivers -L_0x1dc2400 .part L_0x1dc2e90, 0, 1; -L_0x1dc2560 .part L_0x1dc2e90, 1, 1; -L_0x1dc26a0 .concat8 [ 1 1 0 0], L_0x1dc2340, L_0x1dc2790; -L_0x1dc28a0 .part L_0x1dc2e90, 2, 1; -L_0x1dc2a00 .part L_0x1dc2e90, 3, 1; -L_0x1dc2bf0 .part L_0x1dc26a0, 0, 1; -L_0x1dc2da0 .part L_0x1dc26a0, 1, 1; -S_0x1bbf230 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bbe360; +L_0x1255a80/d .functor OR 1, L_0x1255b40, L_0x1255ca0, C4<0>, C4<0>; +L_0x1255a80 .delay 1 (30000,30000,30000) L_0x1255a80/d; +L_0x1255ed0/d .functor OR 1, L_0x1255fe0, L_0x1256140, C4<0>, C4<0>; +L_0x1255ed0 .delay 1 (30000,30000,30000) L_0x1255ed0/d; +L_0x12562c0/d .functor OR 1, L_0x1256330, L_0x12564e0, C4<0>, C4<0>; +L_0x12562c0 .delay 1 (30000,30000,30000) L_0x12562c0/d; +v0x10513f0_0 .net *"_s0", 0 0, L_0x1255a80; 1 drivers +v0x10514f0_0 .net *"_s10", 0 0, L_0x1255fe0; 1 drivers +v0x10515d0_0 .net *"_s12", 0 0, L_0x1256140; 1 drivers +v0x1051690_0 .net *"_s14", 0 0, L_0x1256330; 1 drivers +v0x1051770_0 .net *"_s16", 0 0, L_0x12564e0; 1 drivers +v0x10518a0_0 .net *"_s3", 0 0, L_0x1255b40; 1 drivers +v0x1051980_0 .net *"_s5", 0 0, L_0x1255ca0; 1 drivers +v0x1051a60_0 .net *"_s6", 0 0, L_0x1255ed0; 1 drivers +v0x1051b40_0 .net "in", 3 0, L_0x12565d0; 1 drivers +v0x1051cb0_0 .net "ors", 1 0, L_0x1255de0; 1 drivers +v0x1051d90_0 .net "out", 0 0, L_0x12562c0; 1 drivers +L_0x1255b40 .part L_0x12565d0, 0, 1; +L_0x1255ca0 .part L_0x12565d0, 1, 1; +L_0x1255de0 .concat8 [ 1 1 0 0], L_0x1255a80, L_0x1255ed0; +L_0x1255fe0 .part L_0x12565d0, 2, 1; +L_0x1256140 .part L_0x12565d0, 3, 1; +L_0x1256330 .part L_0x1255de0, 0, 1; +L_0x12564e0 .part L_0x1255de0, 1, 1; +S_0x1051eb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1050fe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dc2fc0/d .functor OR 1, L_0x1dc3030, L_0x1dc3190, C4<0>, C4<0>; -L_0x1dc2fc0 .delay 1 (30000,30000,30000) L_0x1dc2fc0/d; -L_0x1dc33c0/d .functor OR 1, L_0x1dc34d0, L_0x1dc3630, C4<0>, C4<0>; -L_0x1dc33c0 .delay 1 (30000,30000,30000) L_0x1dc33c0/d; -L_0x1dc37b0/d .functor OR 1, L_0x1dc3820, L_0x1dc39d0, C4<0>, C4<0>; -L_0x1dc37b0 .delay 1 (30000,30000,30000) L_0x1dc37b0/d; -v0x1bbf3f0_0 .net *"_s0", 0 0, L_0x1dc2fc0; 1 drivers -v0x1bbf4f0_0 .net *"_s10", 0 0, L_0x1dc34d0; 1 drivers -v0x1bbf5d0_0 .net *"_s12", 0 0, L_0x1dc3630; 1 drivers -v0x1bbf690_0 .net *"_s14", 0 0, L_0x1dc3820; 1 drivers -v0x1bbf770_0 .net *"_s16", 0 0, L_0x1dc39d0; 1 drivers -v0x1bbf8a0_0 .net *"_s3", 0 0, L_0x1dc3030; 1 drivers -v0x1bbf980_0 .net *"_s5", 0 0, L_0x1dc3190; 1 drivers -v0x1bbfa60_0 .net *"_s6", 0 0, L_0x1dc33c0; 1 drivers -v0x1bbfb40_0 .net "in", 3 0, L_0x1dc3c00; 1 drivers -v0x1bbfcb0_0 .net "ors", 1 0, L_0x1dc32d0; 1 drivers -v0x1bbfd90_0 .net "out", 0 0, L_0x1dc37b0; 1 drivers -L_0x1dc3030 .part L_0x1dc3c00, 0, 1; -L_0x1dc3190 .part L_0x1dc3c00, 1, 1; -L_0x1dc32d0 .concat8 [ 1 1 0 0], L_0x1dc2fc0, L_0x1dc33c0; -L_0x1dc34d0 .part L_0x1dc3c00, 2, 1; -L_0x1dc3630 .part L_0x1dc3c00, 3, 1; -L_0x1dc3820 .part L_0x1dc32d0, 0, 1; -L_0x1dc39d0 .part L_0x1dc32d0, 1, 1; -S_0x1bc06a0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bb4020; +L_0x1256700/d .functor OR 1, L_0x1256770, L_0x12568d0, C4<0>, C4<0>; +L_0x1256700 .delay 1 (30000,30000,30000) L_0x1256700/d; +L_0x1256b00/d .functor OR 1, L_0x1256c10, L_0x1256d70, C4<0>, C4<0>; +L_0x1256b00 .delay 1 (30000,30000,30000) L_0x1256b00/d; +L_0x1256ef0/d .functor OR 1, L_0x1256f60, L_0x1257110, C4<0>, C4<0>; +L_0x1256ef0 .delay 1 (30000,30000,30000) L_0x1256ef0/d; +v0x1052070_0 .net *"_s0", 0 0, L_0x1256700; 1 drivers +v0x1052170_0 .net *"_s10", 0 0, L_0x1256c10; 1 drivers +v0x1052250_0 .net *"_s12", 0 0, L_0x1256d70; 1 drivers +v0x1052310_0 .net *"_s14", 0 0, L_0x1256f60; 1 drivers +v0x10523f0_0 .net *"_s16", 0 0, L_0x1257110; 1 drivers +v0x1052520_0 .net *"_s3", 0 0, L_0x1256770; 1 drivers +v0x1052600_0 .net *"_s5", 0 0, L_0x12568d0; 1 drivers +v0x10526e0_0 .net *"_s6", 0 0, L_0x1256b00; 1 drivers +v0x10527c0_0 .net "in", 3 0, L_0x1257340; 1 drivers +v0x1052930_0 .net "ors", 1 0, L_0x1256a10; 1 drivers +v0x1052a10_0 .net "out", 0 0, L_0x1256ef0; 1 drivers +L_0x1256770 .part L_0x1257340, 0, 1; +L_0x12568d0 .part L_0x1257340, 1, 1; +L_0x1256a10 .concat8 [ 1 1 0 0], L_0x1256700, L_0x1256b00; +L_0x1256c10 .part L_0x1257340, 2, 1; +L_0x1256d70 .part L_0x1257340, 3, 1; +L_0x1256f60 .part L_0x1256a10, 0, 1; +L_0x1257110 .part L_0x1256a10, 1, 1; +S_0x1053320 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1046ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -4924,80 +4934,80 @@ S_0x1bc06a0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bb4020; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1dbf470/d .functor XNOR 1, L_0x1dc7b40, L_0x1dc7ca0, C4<0>, C4<0>; -L_0x1dbf470 .delay 1 (20000,20000,20000) L_0x1dbf470/d; -L_0x1dbf6e0/d .functor AND 1, L_0x1dc7b40, L_0x1dbe3b0, C4<1>, C4<1>; -L_0x1dbf6e0 .delay 1 (30000,30000,30000) L_0x1dbf6e0/d; -L_0x1dbf750/d .functor AND 1, L_0x1dbf470, L_0x1dbe240, C4<1>, C4<1>; -L_0x1dbf750 .delay 1 (30000,30000,30000) L_0x1dbf750/d; -L_0x1dbf8b0/d .functor OR 1, L_0x1dbf750, L_0x1dbf6e0, C4<0>, C4<0>; -L_0x1dbf8b0 .delay 1 (30000,30000,30000) L_0x1dbf8b0/d; -v0x1bc0950_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers -v0x1bc0a40_0 .net "a_", 0 0, L_0x1dbb990; alias, 1 drivers -v0x1bc0b00_0 .net "b", 0 0, L_0x1dc7ca0; alias, 1 drivers -v0x1bc0bf0_0 .net "b_", 0 0, L_0x1dbe3b0; alias, 1 drivers -v0x1bc0c90_0 .net "carryin", 0 0, L_0x1dbe240; alias, 1 drivers -v0x1bc0dd0_0 .net "eq", 0 0, L_0x1dbf470; 1 drivers -v0x1bc0e90_0 .net "lt", 0 0, L_0x1dbf6e0; 1 drivers -v0x1bc0f50_0 .net "out", 0 0, L_0x1dbf8b0; 1 drivers -v0x1bc1010_0 .net "w0", 0 0, L_0x1dbf750; 1 drivers -S_0x1bc1260 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bb4020; +L_0x1252bb0/d .functor XNOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; +L_0x1252bb0 .delay 1 (20000,20000,20000) L_0x1252bb0/d; +L_0x1252e20/d .functor AND 1, L_0x125b280, L_0x1251bb0, C4<1>, C4<1>; +L_0x1252e20 .delay 1 (30000,30000,30000) L_0x1252e20/d; +L_0x1252e90/d .functor AND 1, L_0x1252bb0, L_0x1251980, C4<1>, C4<1>; +L_0x1252e90 .delay 1 (30000,30000,30000) L_0x1252e90/d; +L_0x1252ff0/d .functor OR 1, L_0x1252e90, L_0x1252e20, C4<0>, C4<0>; +L_0x1252ff0 .delay 1 (30000,30000,30000) L_0x1252ff0/d; +v0x10535d0_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers +v0x10536c0_0 .net "a_", 0 0, L_0x1251aa0; alias, 1 drivers +v0x1053780_0 .net "b", 0 0, L_0x125b3e0; alias, 1 drivers +v0x1053870_0 .net "b_", 0 0, L_0x1251bb0; alias, 1 drivers +v0x1053910_0 .net "carryin", 0 0, L_0x1251980; alias, 1 drivers +v0x1053a50_0 .net "eq", 0 0, L_0x1252bb0; 1 drivers +v0x1053b10_0 .net "lt", 0 0, L_0x1252e20; 1 drivers +v0x1053bd0_0 .net "out", 0 0, L_0x1252ff0; 1 drivers +v0x1053c90_0 .net "w0", 0 0, L_0x1252e90; 1 drivers +S_0x1053ee0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1046ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dbf250/d .functor OR 1, L_0x1dbeda0, L_0x1bc24c0, C4<0>, C4<0>; -L_0x1dbf250 .delay 1 (30000,30000,30000) L_0x1dbf250/d; -v0x1bc2050_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers -v0x1bc21a0_0 .net "b", 0 0, L_0x1dbe3b0; alias, 1 drivers -v0x1bc2260_0 .net "c1", 0 0, L_0x1dbeda0; 1 drivers -v0x1bc2300_0 .net "c2", 0 0, L_0x1bc24c0; 1 drivers -v0x1bc23d0_0 .net "carryin", 0 0, L_0x1dbe240; alias, 1 drivers -v0x1bc2550_0 .net "carryout", 0 0, L_0x1dbf250; 1 drivers -v0x1bc25f0_0 .net "s1", 0 0, L_0x1dbece0; 1 drivers -v0x1bc2690_0 .net "sum", 0 0, L_0x1dbef00; 1 drivers -S_0x1bc14b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bc1260; +L_0x1252990/d .functor OR 1, L_0x12524e0, L_0x1055140, C4<0>, C4<0>; +L_0x1252990 .delay 1 (30000,30000,30000) L_0x1252990/d; +v0x1054cd0_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers +v0x1054e20_0 .net "b", 0 0, L_0x1251bb0; alias, 1 drivers +v0x1054ee0_0 .net "c1", 0 0, L_0x12524e0; 1 drivers +v0x1054f80_0 .net "c2", 0 0, L_0x1055140; 1 drivers +v0x1055050_0 .net "carryin", 0 0, L_0x1251980; alias, 1 drivers +v0x10551d0_0 .net "carryout", 0 0, L_0x1252990; 1 drivers +v0x1055270_0 .net "s1", 0 0, L_0x1252420; 1 drivers +v0x1055310_0 .net "sum", 0 0, L_0x1252640; 1 drivers +S_0x1054130 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1053ee0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dbece0/d .functor XOR 1, L_0x1dc7b40, L_0x1dbe3b0, C4<0>, C4<0>; -L_0x1dbece0 .delay 1 (30000,30000,30000) L_0x1dbece0/d; -L_0x1dbeda0/d .functor AND 1, L_0x1dc7b40, L_0x1dbe3b0, C4<1>, C4<1>; -L_0x1dbeda0 .delay 1 (30000,30000,30000) L_0x1dbeda0/d; -v0x1bc1710_0 .net "a", 0 0, L_0x1dc7b40; alias, 1 drivers -v0x1bc17d0_0 .net "b", 0 0, L_0x1dbe3b0; alias, 1 drivers -v0x1bc1890_0 .net "carryout", 0 0, L_0x1dbeda0; alias, 1 drivers -v0x1bc1930_0 .net "sum", 0 0, L_0x1dbece0; alias, 1 drivers -S_0x1bc1a60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bc1260; +L_0x1252420/d .functor XOR 1, L_0x125b280, L_0x1251bb0, C4<0>, C4<0>; +L_0x1252420 .delay 1 (30000,30000,30000) L_0x1252420/d; +L_0x12524e0/d .functor AND 1, L_0x125b280, L_0x1251bb0, C4<1>, C4<1>; +L_0x12524e0 .delay 1 (30000,30000,30000) L_0x12524e0/d; +v0x1054390_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers +v0x1054450_0 .net "b", 0 0, L_0x1251bb0; alias, 1 drivers +v0x1054510_0 .net "carryout", 0 0, L_0x12524e0; alias, 1 drivers +v0x10545b0_0 .net "sum", 0 0, L_0x1252420; alias, 1 drivers +S_0x10546e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1053ee0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dbef00/d .functor XOR 1, L_0x1dbece0, L_0x1dbe240, C4<0>, C4<0>; -L_0x1dbef00 .delay 1 (30000,30000,30000) L_0x1dbef00/d; -L_0x1bc24c0/d .functor AND 1, L_0x1dbece0, L_0x1dbe240, C4<1>, C4<1>; -L_0x1bc24c0 .delay 1 (30000,30000,30000) L_0x1bc24c0/d; -v0x1bc1cc0_0 .net "a", 0 0, L_0x1dbece0; alias, 1 drivers -v0x1bc1d90_0 .net "b", 0 0, L_0x1dbe240; alias, 1 drivers -v0x1bc1e30_0 .net "carryout", 0 0, L_0x1bc24c0; alias, 1 drivers -v0x1bc1f00_0 .net "sum", 0 0, L_0x1dbef00; alias, 1 drivers -S_0x1bc3ab0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bb3d10; - .timescale -9 -12; -L_0x7f72592da918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dc7be0/d .functor OR 1, L_0x7f72592da918, L_0x7f72592da960, C4<0>, C4<0>; -L_0x1dc7be0 .delay 1 (30000,30000,30000) L_0x1dc7be0/d; -v0x1bc3ca0_0 .net/2u *"_s0", 0 0, L_0x7f72592da918; 1 drivers -v0x1bc3d80_0 .net/2u *"_s2", 0 0, L_0x7f72592da960; 1 drivers -S_0x1bc3e60 .scope generate, "alu_slices[9]" "alu_slices[9]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1bc4070 .param/l "i" 0 3 37, +C4<01001>; -S_0x1bc4130 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bc3e60; +L_0x1252640/d .functor XOR 1, L_0x1252420, L_0x1251980, C4<0>, C4<0>; +L_0x1252640 .delay 1 (30000,30000,30000) L_0x1252640/d; +L_0x1055140/d .functor AND 1, L_0x1252420, L_0x1251980, C4<1>, C4<1>; +L_0x1055140 .delay 1 (30000,30000,30000) L_0x1055140/d; +v0x1054940_0 .net "a", 0 0, L_0x1252420; alias, 1 drivers +v0x1054a10_0 .net "b", 0 0, L_0x1251980; alias, 1 drivers +v0x1054ab0_0 .net "carryout", 0 0, L_0x1055140; alias, 1 drivers +v0x1054b80_0 .net "sum", 0 0, L_0x1252640; alias, 1 drivers +S_0x1056730 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1046990; + .timescale -9 -12; +L_0x2b0ab3d05918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x125b320/d .functor OR 1, L_0x2b0ab3d05918, L_0x2b0ab3d05960, C4<0>, C4<0>; +L_0x125b320 .delay 1 (30000,30000,30000) L_0x125b320/d; +v0x1056920_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05918; 1 drivers +v0x1056a00_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05960; 1 drivers +S_0x1056ae0 .scope generate, "alu_slices[9]" "alu_slices[9]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1056cf0 .param/l "i" 0 3 41, +C4<01001>; +S_0x1056db0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1056ae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -5006,445 +5016,445 @@ S_0x1bc4130 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bc3e60; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1dc7f10/d .functor NOT 1, L_0x1dd1850, C4<0>, C4<0>, C4<0>; -L_0x1dc7f10 .delay 1 (10000,10000,10000) L_0x1dc7f10/d; -L_0x1dc1c20/d .functor NOT 1, L_0x1dc7d40, C4<0>, C4<0>, C4<0>; -L_0x1dc1c20 .delay 1 (10000,10000,10000) L_0x1dc1c20/d; -L_0x1dc90c0/d .functor XOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; -L_0x1dc90c0 .delay 1 (30000,30000,30000) L_0x1dc90c0/d; -L_0x7f72592da9a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592da9f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dc9770/d .functor OR 1, L_0x7f72592da9a8, L_0x7f72592da9f0, C4<0>, C4<0>; -L_0x1dc9770 .delay 1 (30000,30000,30000) L_0x1dc9770/d; -L_0x1dc9970/d .functor AND 1, L_0x1dd1850, L_0x1dc7d40, C4<1>, C4<1>; -L_0x1dc9970 .delay 1 (30000,30000,30000) L_0x1dc9970/d; -L_0x1dc9a30/d .functor NAND 1, L_0x1dd1850, L_0x1dc7d40, C4<1>, C4<1>; -L_0x1dc9a30 .delay 1 (20000,20000,20000) L_0x1dc9a30/d; -L_0x1dc9b90/d .functor XOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; -L_0x1dc9b90 .delay 1 (20000,20000,20000) L_0x1dc9b90/d; -L_0x1dca040/d .functor OR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; -L_0x1dca040 .delay 1 (30000,30000,30000) L_0x1dca040/d; -L_0x1dd1750/d .functor NOT 1, L_0x1dcd9b0, C4<0>, C4<0>, C4<0>; -L_0x1dd1750 .delay 1 (10000,10000,10000) L_0x1dd1750/d; -v0x1bd2860_0 .net "A", 0 0, L_0x1dd1850; 1 drivers -v0x1bd2920_0 .net "A_", 0 0, L_0x1dc7f10; 1 drivers -v0x1bd29e0_0 .net "B", 0 0, L_0x1dc7d40; 1 drivers -v0x1bd2ab0_0 .net "B_", 0 0, L_0x1dc1c20; 1 drivers -v0x1bd2b50_0 .net *"_s12", 0 0, L_0x1dc9770; 1 drivers -v0x1bd2c40_0 .net/2s *"_s14", 0 0, L_0x7f72592da9a8; 1 drivers -v0x1bd2d00_0 .net/2s *"_s16", 0 0, L_0x7f72592da9f0; 1 drivers -v0x1bd2de0_0 .net *"_s18", 0 0, L_0x1dc9970; 1 drivers -v0x1bd2ec0_0 .net *"_s20", 0 0, L_0x1dc9a30; 1 drivers -v0x1bd3030_0 .net *"_s22", 0 0, L_0x1dc9b90; 1 drivers -v0x1bd3110_0 .net *"_s24", 0 0, L_0x1dca040; 1 drivers -o0x7f725936b298 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1bd31f0_0 name=_s30 -o0x7f725936b2c8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1bd32d0_0 name=_s32 -v0x1bd33b0_0 .net *"_s8", 0 0, L_0x1dc90c0; 1 drivers -v0x1bd3490_0 .net "carryin", 0 0, L_0x1dd1aa0; 1 drivers -v0x1bd3530_0 .net "carryout", 0 0, L_0x1dd13f0; 1 drivers -v0x1bd35d0_0 .net "carryouts", 7 0, L_0x1ebf9c0; 1 drivers -v0x1bd3780_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bd3820_0 .net "result", 0 0, L_0x1dcd9b0; 1 drivers -v0x1bd3910_0 .net "results", 7 0, L_0x1dc9e10; 1 drivers -v0x1bd3a20_0 .net "zero", 0 0, L_0x1dd1750; 1 drivers -LS_0x1dc9e10_0_0 .concat8 [ 1 1 1 1], L_0x1dc85e0, L_0x1dc8c10, L_0x1dc90c0, L_0x1dc9770; -LS_0x1dc9e10_0_4 .concat8 [ 1 1 1 1], L_0x1dc9970, L_0x1dc9a30, L_0x1dc9b90, L_0x1dca040; -L_0x1dc9e10 .concat8 [ 4 4 0 0], LS_0x1dc9e10_0_0, LS_0x1dc9e10_0_4; -LS_0x1ebf9c0_0_0 .concat [ 1 1 1 1], L_0x1dc8890, L_0x1dc8f60, o0x7f725936b298, L_0x1dc95c0; -LS_0x1ebf9c0_0_4 .concat [ 4 0 0 0], o0x7f725936b2c8; -L_0x1ebf9c0 .concat [ 4 4 0 0], LS_0x1ebf9c0_0_0, LS_0x1ebf9c0_0_4; -S_0x1bc43b0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bc4130; +L_0x125b650/d .functor NOT 1, L_0x1264f90, C4<0>, C4<0>, C4<0>; +L_0x125b650 .delay 1 (10000,10000,10000) L_0x125b650/d; +L_0x1255360/d .functor NOT 1, L_0x125b480, C4<0>, C4<0>, C4<0>; +L_0x1255360 .delay 1 (10000,10000,10000) L_0x1255360/d; +L_0x125c800/d .functor XOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; +L_0x125c800 .delay 1 (30000,30000,30000) L_0x125c800/d; +L_0x2b0ab3d059a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d059f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x125ceb0/d .functor OR 1, L_0x2b0ab3d059a8, L_0x2b0ab3d059f0, C4<0>, C4<0>; +L_0x125ceb0 .delay 1 (30000,30000,30000) L_0x125ceb0/d; +L_0x125d0b0/d .functor AND 1, L_0x1264f90, L_0x125b480, C4<1>, C4<1>; +L_0x125d0b0 .delay 1 (30000,30000,30000) L_0x125d0b0/d; +L_0x125d170/d .functor NAND 1, L_0x1264f90, L_0x125b480, C4<1>, C4<1>; +L_0x125d170 .delay 1 (20000,20000,20000) L_0x125d170/d; +L_0x125d2d0/d .functor XOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; +L_0x125d2d0 .delay 1 (20000,20000,20000) L_0x125d2d0/d; +L_0x125d780/d .functor OR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; +L_0x125d780 .delay 1 (30000,30000,30000) L_0x125d780/d; +L_0x1264e90/d .functor NOT 1, L_0x12610f0, C4<0>, C4<0>, C4<0>; +L_0x1264e90 .delay 1 (10000,10000,10000) L_0x1264e90/d; +v0x10654a0_0 .net "A", 0 0, L_0x1264f90; 1 drivers +v0x1065560_0 .net "A_", 0 0, L_0x125b650; 1 drivers +v0x1065620_0 .net "B", 0 0, L_0x125b480; 1 drivers +v0x10656f0_0 .net "B_", 0 0, L_0x1255360; 1 drivers +v0x1065790_0 .net *"_s12", 0 0, L_0x125ceb0; 1 drivers +v0x1065880_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d059a8; 1 drivers +v0x1065940_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d059f0; 1 drivers +v0x1065a20_0 .net *"_s18", 0 0, L_0x125d0b0; 1 drivers +v0x1065b00_0 .net *"_s20", 0 0, L_0x125d170; 1 drivers +v0x1065c70_0 .net *"_s22", 0 0, L_0x125d2d0; 1 drivers +v0x1065d50_0 .net *"_s24", 0 0, L_0x125d780; 1 drivers +o0x2b0ab3cba298 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1065e30_0 name=_s30 +o0x2b0ab3cba2c8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1065f10_0 name=_s32 +v0x1065ff0_0 .net *"_s8", 0 0, L_0x125c800; 1 drivers +v0x10660d0_0 .net "carryin", 0 0, L_0x12651e0; 1 drivers +v0x1066170_0 .net "carryout", 0 0, L_0x1264b30; 1 drivers +v0x1066210_0 .net "carryouts", 7 0, L_0x1353d70; 1 drivers +v0x10663c0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1066460_0 .net "result", 0 0, L_0x12610f0; 1 drivers +v0x1066550_0 .net "results", 7 0, L_0x125d550; 1 drivers +v0x1066660_0 .net "zero", 0 0, L_0x1264e90; 1 drivers +LS_0x125d550_0_0 .concat8 [ 1 1 1 1], L_0x125bd20, L_0x125c350, L_0x125c800, L_0x125ceb0; +LS_0x125d550_0_4 .concat8 [ 1 1 1 1], L_0x125d0b0, L_0x125d170, L_0x125d2d0, L_0x125d780; +L_0x125d550 .concat8 [ 4 4 0 0], LS_0x125d550_0_0, LS_0x125d550_0_4; +LS_0x1353d70_0_0 .concat [ 1 1 1 1], L_0x125bfd0, L_0x125c6a0, o0x2b0ab3cba298, L_0x125cd00; +LS_0x1353d70_0_4 .concat [ 4 0 0 0], o0x2b0ab3cba2c8; +L_0x1353d70 .concat [ 4 4 0 0], LS_0x1353d70_0_0, LS_0x1353d70_0_4; +S_0x1057030 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1056db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dc8890/d .functor OR 1, L_0x1dc8370, L_0x1dc8730, C4<0>, C4<0>; -L_0x1dc8890 .delay 1 (30000,30000,30000) L_0x1dc8890/d; -v0x1bc51e0_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers -v0x1bc52a0_0 .net "b", 0 0, L_0x1dc7d40; alias, 1 drivers -v0x1bc5370_0 .net "c1", 0 0, L_0x1dc8370; 1 drivers -v0x1bc5470_0 .net "c2", 0 0, L_0x1dc8730; 1 drivers -v0x1bc5540_0 .net "carryin", 0 0, L_0x1dd1aa0; alias, 1 drivers -v0x1bc5630_0 .net "carryout", 0 0, L_0x1dc8890; 1 drivers -v0x1bc56d0_0 .net "s1", 0 0, L_0x1dc8300; 1 drivers -v0x1bc57c0_0 .net "sum", 0 0, L_0x1dc85e0; 1 drivers -S_0x1bc4620 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bc43b0; +L_0x125bfd0/d .functor OR 1, L_0x125bab0, L_0x125be70, C4<0>, C4<0>; +L_0x125bfd0 .delay 1 (30000,30000,30000) L_0x125bfd0/d; +v0x1057e60_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers +v0x1057f20_0 .net "b", 0 0, L_0x125b480; alias, 1 drivers +v0x1057ff0_0 .net "c1", 0 0, L_0x125bab0; 1 drivers +v0x10580f0_0 .net "c2", 0 0, L_0x125be70; 1 drivers +v0x10581c0_0 .net "carryin", 0 0, L_0x12651e0; alias, 1 drivers +v0x10582b0_0 .net "carryout", 0 0, L_0x125bfd0; 1 drivers +v0x1058350_0 .net "s1", 0 0, L_0x125ba40; 1 drivers +v0x1058440_0 .net "sum", 0 0, L_0x125bd20; 1 drivers +S_0x10572a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1057030; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dc8300/d .functor XOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; -L_0x1dc8300 .delay 1 (30000,30000,30000) L_0x1dc8300/d; -L_0x1dc8370/d .functor AND 1, L_0x1dd1850, L_0x1dc7d40, C4<1>, C4<1>; -L_0x1dc8370 .delay 1 (30000,30000,30000) L_0x1dc8370/d; -v0x1bc4880_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers -v0x1bc4960_0 .net "b", 0 0, L_0x1dc7d40; alias, 1 drivers -v0x1bc4a20_0 .net "carryout", 0 0, L_0x1dc8370; alias, 1 drivers -v0x1bc4ac0_0 .net "sum", 0 0, L_0x1dc8300; alias, 1 drivers -S_0x1bc4c00 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bc43b0; +L_0x125ba40/d .functor XOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; +L_0x125ba40 .delay 1 (30000,30000,30000) L_0x125ba40/d; +L_0x125bab0/d .functor AND 1, L_0x1264f90, L_0x125b480, C4<1>, C4<1>; +L_0x125bab0 .delay 1 (30000,30000,30000) L_0x125bab0/d; +v0x1057500_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers +v0x10575e0_0 .net "b", 0 0, L_0x125b480; alias, 1 drivers +v0x10576a0_0 .net "carryout", 0 0, L_0x125bab0; alias, 1 drivers +v0x1057740_0 .net "sum", 0 0, L_0x125ba40; alias, 1 drivers +S_0x1057880 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1057030; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dc85e0/d .functor XOR 1, L_0x1dc8300, L_0x1dd1aa0, C4<0>, C4<0>; -L_0x1dc85e0 .delay 1 (30000,30000,30000) L_0x1dc85e0/d; -L_0x1dc8730/d .functor AND 1, L_0x1dc8300, L_0x1dd1aa0, C4<1>, C4<1>; -L_0x1dc8730 .delay 1 (30000,30000,30000) L_0x1dc8730/d; -v0x1bc4e60_0 .net "a", 0 0, L_0x1dc8300; alias, 1 drivers -v0x1bc4f00_0 .net "b", 0 0, L_0x1dd1aa0; alias, 1 drivers -v0x1bc4fa0_0 .net "carryout", 0 0, L_0x1dc8730; alias, 1 drivers -v0x1bc5070_0 .net "sum", 0 0, L_0x1dc85e0; alias, 1 drivers -S_0x1bc5890 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bc4130; +L_0x125bd20/d .functor XOR 1, L_0x125ba40, L_0x12651e0, C4<0>, C4<0>; +L_0x125bd20 .delay 1 (30000,30000,30000) L_0x125bd20/d; +L_0x125be70/d .functor AND 1, L_0x125ba40, L_0x12651e0, C4<1>, C4<1>; +L_0x125be70 .delay 1 (30000,30000,30000) L_0x125be70/d; +v0x1057ae0_0 .net "a", 0 0, L_0x125ba40; alias, 1 drivers +v0x1057b80_0 .net "b", 0 0, L_0x12651e0; alias, 1 drivers +v0x1057c20_0 .net "carryout", 0 0, L_0x125be70; alias, 1 drivers +v0x1057cf0_0 .net "sum", 0 0, L_0x125bd20; alias, 1 drivers +S_0x1058510 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1056db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bcac80_0 .net "ands", 7 0, L_0x1dcf3f0; 1 drivers -v0x1bcad90_0 .net "in", 7 0, L_0x1ebf9c0; alias, 1 drivers -v0x1bcae50_0 .net "out", 0 0, L_0x1dd13f0; alias, 1 drivers -v0x1bcaf20_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bc5ab0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bc5890; +v0x105d900_0 .net "ands", 7 0, L_0x1262b30; 1 drivers +v0x105da10_0 .net "in", 7 0, L_0x1353d70; alias, 1 drivers +v0x105dad0_0 .net "out", 0 0, L_0x1264b30; alias, 1 drivers +v0x105dba0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1058730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1058510; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bc81e0_0 .net "A", 7 0, L_0x1ebf9c0; alias, 1 drivers -v0x1bc82e0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bc83a0_0 .net *"_s0", 0 0, L_0x1dcdd10; 1 drivers -v0x1bc8460_0 .net *"_s12", 0 0, L_0x1dce680; 1 drivers -v0x1bc8540_0 .net *"_s16", 0 0, L_0x1dce9e0; 1 drivers -v0x1bc8670_0 .net *"_s20", 0 0, L_0x1dcecf0; 1 drivers -v0x1bc8750_0 .net *"_s24", 0 0, L_0x1dcf0e0; 1 drivers -v0x1bc8830_0 .net *"_s28", 0 0, L_0x1dcf070; 1 drivers -v0x1bc8910_0 .net *"_s4", 0 0, L_0x1dce020; 1 drivers -v0x1bc8a80_0 .net *"_s8", 0 0, L_0x1dce370; 1 drivers -v0x1bc8b60_0 .net "out", 7 0, L_0x1dcf3f0; alias, 1 drivers -L_0x1dcddd0 .part L_0x1ebf9c0, 0, 1; -L_0x1dcdf30 .part v0x1d6daa0_0, 0, 1; -L_0x1dce0e0 .part L_0x1ebf9c0, 1, 1; -L_0x1dce2d0 .part v0x1d6daa0_0, 1, 1; -L_0x1dce430 .part L_0x1ebf9c0, 2, 1; -L_0x1dce590 .part v0x1d6daa0_0, 2, 1; -L_0x1dce740 .part L_0x1ebf9c0, 3, 1; -L_0x1dce8a0 .part v0x1d6daa0_0, 3, 1; -L_0x1dceaa0 .part L_0x1ebf9c0, 4, 1; -L_0x1dcec00 .part v0x1d6daa0_0, 4, 1; -L_0x1dced60 .part L_0x1ebf9c0, 5, 1; -L_0x1dcefd0 .part v0x1d6daa0_0, 5, 1; -L_0x1dcf1a0 .part L_0x1ebf9c0, 6, 1; -L_0x1dcf300 .part v0x1d6daa0_0, 6, 1; -LS_0x1dcf3f0_0_0 .concat8 [ 1 1 1 1], L_0x1dcdd10, L_0x1dce020, L_0x1dce370, L_0x1dce680; -LS_0x1dcf3f0_0_4 .concat8 [ 1 1 1 1], L_0x1dce9e0, L_0x1dcecf0, L_0x1dcf0e0, L_0x1dcf070; -L_0x1dcf3f0 .concat8 [ 4 4 0 0], LS_0x1dcf3f0_0_0, LS_0x1dcf3f0_0_4; -L_0x1dcf7b0 .part L_0x1ebf9c0, 7, 1; -L_0x1dcf9a0 .part v0x1d6daa0_0, 7, 1; -S_0x1bc5d10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc5f20 .param/l "i" 0 4 54, +C4<00>; -L_0x1dcdd10/d .functor AND 1, L_0x1dcddd0, L_0x1dcdf30, C4<1>, C4<1>; -L_0x1dcdd10 .delay 1 (30000,30000,30000) L_0x1dcdd10/d; -v0x1bc6000_0 .net *"_s0", 0 0, L_0x1dcddd0; 1 drivers -v0x1bc60e0_0 .net *"_s1", 0 0, L_0x1dcdf30; 1 drivers -S_0x1bc61c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc63d0 .param/l "i" 0 4 54, +C4<01>; -L_0x1dce020/d .functor AND 1, L_0x1dce0e0, L_0x1dce2d0, C4<1>, C4<1>; -L_0x1dce020 .delay 1 (30000,30000,30000) L_0x1dce020/d; -v0x1bc6490_0 .net *"_s0", 0 0, L_0x1dce0e0; 1 drivers -v0x1bc6570_0 .net *"_s1", 0 0, L_0x1dce2d0; 1 drivers -S_0x1bc6650 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc6860 .param/l "i" 0 4 54, +C4<010>; -L_0x1dce370/d .functor AND 1, L_0x1dce430, L_0x1dce590, C4<1>, C4<1>; -L_0x1dce370 .delay 1 (30000,30000,30000) L_0x1dce370/d; -v0x1bc6900_0 .net *"_s0", 0 0, L_0x1dce430; 1 drivers -v0x1bc69e0_0 .net *"_s1", 0 0, L_0x1dce590; 1 drivers -S_0x1bc6ac0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc6cd0 .param/l "i" 0 4 54, +C4<011>; -L_0x1dce680/d .functor AND 1, L_0x1dce740, L_0x1dce8a0, C4<1>, C4<1>; -L_0x1dce680 .delay 1 (30000,30000,30000) L_0x1dce680/d; -v0x1bc6d90_0 .net *"_s0", 0 0, L_0x1dce740; 1 drivers -v0x1bc6e70_0 .net *"_s1", 0 0, L_0x1dce8a0; 1 drivers -S_0x1bc6f50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc71b0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dce9e0/d .functor AND 1, L_0x1dceaa0, L_0x1dcec00, C4<1>, C4<1>; -L_0x1dce9e0 .delay 1 (30000,30000,30000) L_0x1dce9e0/d; -v0x1bc7270_0 .net *"_s0", 0 0, L_0x1dceaa0; 1 drivers -v0x1bc7350_0 .net *"_s1", 0 0, L_0x1dcec00; 1 drivers -S_0x1bc7430 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc7640 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dcecf0/d .functor AND 1, L_0x1dced60, L_0x1dcefd0, C4<1>, C4<1>; -L_0x1dcecf0 .delay 1 (30000,30000,30000) L_0x1dcecf0/d; -v0x1bc7700_0 .net *"_s0", 0 0, L_0x1dced60; 1 drivers -v0x1bc77e0_0 .net *"_s1", 0 0, L_0x1dcefd0; 1 drivers -S_0x1bc78c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc7ad0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dcf0e0/d .functor AND 1, L_0x1dcf1a0, L_0x1dcf300, C4<1>, C4<1>; -L_0x1dcf0e0 .delay 1 (30000,30000,30000) L_0x1dcf0e0/d; -v0x1bc7b90_0 .net *"_s0", 0 0, L_0x1dcf1a0; 1 drivers -v0x1bc7c70_0 .net *"_s1", 0 0, L_0x1dcf300; 1 drivers -S_0x1bc7d50 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bc5ab0; - .timescale -9 -12; -P_0x1bc7f60 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dcf070/d .functor AND 1, L_0x1dcf7b0, L_0x1dcf9a0, C4<1>, C4<1>; -L_0x1dcf070 .delay 1 (30000,30000,30000) L_0x1dcf070/d; -v0x1bc8020_0 .net *"_s0", 0 0, L_0x1dcf7b0; 1 drivers -v0x1bc8100_0 .net *"_s1", 0 0, L_0x1dcf9a0; 1 drivers -S_0x1bc8cc0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bc5890; +v0x105ae60_0 .net "A", 7 0, L_0x1353d70; alias, 1 drivers +v0x105af60_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x105b020_0 .net *"_s0", 0 0, L_0x1261450; 1 drivers +v0x105b0e0_0 .net *"_s12", 0 0, L_0x1261dc0; 1 drivers +v0x105b1c0_0 .net *"_s16", 0 0, L_0x1262120; 1 drivers +v0x105b2f0_0 .net *"_s20", 0 0, L_0x1262430; 1 drivers +v0x105b3d0_0 .net *"_s24", 0 0, L_0x1262820; 1 drivers +v0x105b4b0_0 .net *"_s28", 0 0, L_0x12627b0; 1 drivers +v0x105b590_0 .net *"_s4", 0 0, L_0x1261760; 1 drivers +v0x105b700_0 .net *"_s8", 0 0, L_0x1261ab0; 1 drivers +v0x105b7e0_0 .net "out", 7 0, L_0x1262b30; alias, 1 drivers +L_0x1261510 .part L_0x1353d70, 0, 1; +L_0x1261670 .part v0x12010b0_0, 0, 1; +L_0x1261820 .part L_0x1353d70, 1, 1; +L_0x1261a10 .part v0x12010b0_0, 1, 1; +L_0x1261b70 .part L_0x1353d70, 2, 1; +L_0x1261cd0 .part v0x12010b0_0, 2, 1; +L_0x1261e80 .part L_0x1353d70, 3, 1; +L_0x1261fe0 .part v0x12010b0_0, 3, 1; +L_0x12621e0 .part L_0x1353d70, 4, 1; +L_0x1262340 .part v0x12010b0_0, 4, 1; +L_0x12624a0 .part L_0x1353d70, 5, 1; +L_0x1262710 .part v0x12010b0_0, 5, 1; +L_0x12628e0 .part L_0x1353d70, 6, 1; +L_0x1262a40 .part v0x12010b0_0, 6, 1; +LS_0x1262b30_0_0 .concat8 [ 1 1 1 1], L_0x1261450, L_0x1261760, L_0x1261ab0, L_0x1261dc0; +LS_0x1262b30_0_4 .concat8 [ 1 1 1 1], L_0x1262120, L_0x1262430, L_0x1262820, L_0x12627b0; +L_0x1262b30 .concat8 [ 4 4 0 0], LS_0x1262b30_0_0, LS_0x1262b30_0_4; +L_0x1262ef0 .part L_0x1353d70, 7, 1; +L_0x12630e0 .part v0x12010b0_0, 7, 1; +S_0x1058990 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x1058ba0 .param/l "i" 0 4 54, +C4<00>; +L_0x1261450/d .functor AND 1, L_0x1261510, L_0x1261670, C4<1>, C4<1>; +L_0x1261450 .delay 1 (30000,30000,30000) L_0x1261450/d; +v0x1058c80_0 .net *"_s0", 0 0, L_0x1261510; 1 drivers +v0x1058d60_0 .net *"_s1", 0 0, L_0x1261670; 1 drivers +S_0x1058e40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x1059050 .param/l "i" 0 4 54, +C4<01>; +L_0x1261760/d .functor AND 1, L_0x1261820, L_0x1261a10, C4<1>, C4<1>; +L_0x1261760 .delay 1 (30000,30000,30000) L_0x1261760/d; +v0x1059110_0 .net *"_s0", 0 0, L_0x1261820; 1 drivers +v0x10591f0_0 .net *"_s1", 0 0, L_0x1261a10; 1 drivers +S_0x10592d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x10594e0 .param/l "i" 0 4 54, +C4<010>; +L_0x1261ab0/d .functor AND 1, L_0x1261b70, L_0x1261cd0, C4<1>, C4<1>; +L_0x1261ab0 .delay 1 (30000,30000,30000) L_0x1261ab0/d; +v0x1059580_0 .net *"_s0", 0 0, L_0x1261b70; 1 drivers +v0x1059660_0 .net *"_s1", 0 0, L_0x1261cd0; 1 drivers +S_0x1059740 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x1059950 .param/l "i" 0 4 54, +C4<011>; +L_0x1261dc0/d .functor AND 1, L_0x1261e80, L_0x1261fe0, C4<1>, C4<1>; +L_0x1261dc0 .delay 1 (30000,30000,30000) L_0x1261dc0/d; +v0x1059a10_0 .net *"_s0", 0 0, L_0x1261e80; 1 drivers +v0x1059af0_0 .net *"_s1", 0 0, L_0x1261fe0; 1 drivers +S_0x1059bd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x1059e30 .param/l "i" 0 4 54, +C4<0100>; +L_0x1262120/d .functor AND 1, L_0x12621e0, L_0x1262340, C4<1>, C4<1>; +L_0x1262120 .delay 1 (30000,30000,30000) L_0x1262120/d; +v0x1059ef0_0 .net *"_s0", 0 0, L_0x12621e0; 1 drivers +v0x1059fd0_0 .net *"_s1", 0 0, L_0x1262340; 1 drivers +S_0x105a0b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x105a2c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1262430/d .functor AND 1, L_0x12624a0, L_0x1262710, C4<1>, C4<1>; +L_0x1262430 .delay 1 (30000,30000,30000) L_0x1262430/d; +v0x105a380_0 .net *"_s0", 0 0, L_0x12624a0; 1 drivers +v0x105a460_0 .net *"_s1", 0 0, L_0x1262710; 1 drivers +S_0x105a540 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x105a750 .param/l "i" 0 4 54, +C4<0110>; +L_0x1262820/d .functor AND 1, L_0x12628e0, L_0x1262a40, C4<1>, C4<1>; +L_0x1262820 .delay 1 (30000,30000,30000) L_0x1262820/d; +v0x105a810_0 .net *"_s0", 0 0, L_0x12628e0; 1 drivers +v0x105a8f0_0 .net *"_s1", 0 0, L_0x1262a40; 1 drivers +S_0x105a9d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1058730; + .timescale -9 -12; +P_0x105abe0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12627b0/d .functor AND 1, L_0x1262ef0, L_0x12630e0, C4<1>, C4<1>; +L_0x12627b0 .delay 1 (30000,30000,30000) L_0x12627b0/d; +v0x105aca0_0 .net *"_s0", 0 0, L_0x1262ef0; 1 drivers +v0x105ad80_0 .net *"_s1", 0 0, L_0x12630e0; 1 drivers +S_0x105b940 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1058510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dd13f0/d .functor OR 1, L_0x1dd14b0, L_0x1dd1660, C4<0>, C4<0>; -L_0x1dd13f0 .delay 1 (30000,30000,30000) L_0x1dd13f0/d; -v0x1bca810_0 .net *"_s10", 0 0, L_0x1dd14b0; 1 drivers -v0x1bca8f0_0 .net *"_s12", 0 0, L_0x1dd1660; 1 drivers -v0x1bca9d0_0 .net "in", 7 0, L_0x1dcf3f0; alias, 1 drivers -v0x1bcaaa0_0 .net "ors", 1 0, L_0x1dd1210; 1 drivers -v0x1bcab60_0 .net "out", 0 0, L_0x1dd13f0; alias, 1 drivers -L_0x1dd05e0 .part L_0x1dcf3f0, 0, 4; -L_0x1dd1210 .concat8 [ 1 1 0 0], L_0x1dd02d0, L_0x1dd0f00; -L_0x1dd1350 .part L_0x1dcf3f0, 4, 4; -L_0x1dd14b0 .part L_0x1dd1210, 0, 1; -L_0x1dd1660 .part L_0x1dd1210, 1, 1; -S_0x1bc8e80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bc8cc0; +L_0x1264b30/d .functor OR 1, L_0x1264bf0, L_0x1264da0, C4<0>, C4<0>; +L_0x1264b30 .delay 1 (30000,30000,30000) L_0x1264b30/d; +v0x105d490_0 .net *"_s10", 0 0, L_0x1264bf0; 1 drivers +v0x105d570_0 .net *"_s12", 0 0, L_0x1264da0; 1 drivers +v0x105d650_0 .net "in", 7 0, L_0x1262b30; alias, 1 drivers +v0x105d720_0 .net "ors", 1 0, L_0x1264950; 1 drivers +v0x105d7e0_0 .net "out", 0 0, L_0x1264b30; alias, 1 drivers +L_0x1263d20 .part L_0x1262b30, 0, 4; +L_0x1264950 .concat8 [ 1 1 0 0], L_0x1263a10, L_0x1264640; +L_0x1264a90 .part L_0x1262b30, 4, 4; +L_0x1264bf0 .part L_0x1264950, 0, 1; +L_0x1264da0 .part L_0x1264950, 1, 1; +S_0x105bb00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x105b940; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dcfa90/d .functor OR 1, L_0x1dcfb50, L_0x1dcfcb0, C4<0>, C4<0>; -L_0x1dcfa90 .delay 1 (30000,30000,30000) L_0x1dcfa90/d; -L_0x1dcfee0/d .functor OR 1, L_0x1dcfff0, L_0x1dd0150, C4<0>, C4<0>; -L_0x1dcfee0 .delay 1 (30000,30000,30000) L_0x1dcfee0/d; -L_0x1dd02d0/d .functor OR 1, L_0x1dd0340, L_0x1dd04f0, C4<0>, C4<0>; -L_0x1dd02d0 .delay 1 (30000,30000,30000) L_0x1dd02d0/d; -v0x1bc90d0_0 .net *"_s0", 0 0, L_0x1dcfa90; 1 drivers -v0x1bc91d0_0 .net *"_s10", 0 0, L_0x1dcfff0; 1 drivers -v0x1bc92b0_0 .net *"_s12", 0 0, L_0x1dd0150; 1 drivers -v0x1bc9370_0 .net *"_s14", 0 0, L_0x1dd0340; 1 drivers -v0x1bc9450_0 .net *"_s16", 0 0, L_0x1dd04f0; 1 drivers -v0x1bc9580_0 .net *"_s3", 0 0, L_0x1dcfb50; 1 drivers -v0x1bc9660_0 .net *"_s5", 0 0, L_0x1dcfcb0; 1 drivers -v0x1bc9740_0 .net *"_s6", 0 0, L_0x1dcfee0; 1 drivers -v0x1bc9820_0 .net "in", 3 0, L_0x1dd05e0; 1 drivers -v0x1bc9990_0 .net "ors", 1 0, L_0x1dcfdf0; 1 drivers -v0x1bc9a70_0 .net "out", 0 0, L_0x1dd02d0; 1 drivers -L_0x1dcfb50 .part L_0x1dd05e0, 0, 1; -L_0x1dcfcb0 .part L_0x1dd05e0, 1, 1; -L_0x1dcfdf0 .concat8 [ 1 1 0 0], L_0x1dcfa90, L_0x1dcfee0; -L_0x1dcfff0 .part L_0x1dd05e0, 2, 1; -L_0x1dd0150 .part L_0x1dd05e0, 3, 1; -L_0x1dd0340 .part L_0x1dcfdf0, 0, 1; -L_0x1dd04f0 .part L_0x1dcfdf0, 1, 1; -S_0x1bc9b90 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bc8cc0; +L_0x12631d0/d .functor OR 1, L_0x1263290, L_0x12633f0, C4<0>, C4<0>; +L_0x12631d0 .delay 1 (30000,30000,30000) L_0x12631d0/d; +L_0x1263620/d .functor OR 1, L_0x1263730, L_0x1263890, C4<0>, C4<0>; +L_0x1263620 .delay 1 (30000,30000,30000) L_0x1263620/d; +L_0x1263a10/d .functor OR 1, L_0x1263a80, L_0x1263c30, C4<0>, C4<0>; +L_0x1263a10 .delay 1 (30000,30000,30000) L_0x1263a10/d; +v0x105bd50_0 .net *"_s0", 0 0, L_0x12631d0; 1 drivers +v0x105be50_0 .net *"_s10", 0 0, L_0x1263730; 1 drivers +v0x105bf30_0 .net *"_s12", 0 0, L_0x1263890; 1 drivers +v0x105bff0_0 .net *"_s14", 0 0, L_0x1263a80; 1 drivers +v0x105c0d0_0 .net *"_s16", 0 0, L_0x1263c30; 1 drivers +v0x105c200_0 .net *"_s3", 0 0, L_0x1263290; 1 drivers +v0x105c2e0_0 .net *"_s5", 0 0, L_0x12633f0; 1 drivers +v0x105c3c0_0 .net *"_s6", 0 0, L_0x1263620; 1 drivers +v0x105c4a0_0 .net "in", 3 0, L_0x1263d20; 1 drivers +v0x105c610_0 .net "ors", 1 0, L_0x1263530; 1 drivers +v0x105c6f0_0 .net "out", 0 0, L_0x1263a10; 1 drivers +L_0x1263290 .part L_0x1263d20, 0, 1; +L_0x12633f0 .part L_0x1263d20, 1, 1; +L_0x1263530 .concat8 [ 1 1 0 0], L_0x12631d0, L_0x1263620; +L_0x1263730 .part L_0x1263d20, 2, 1; +L_0x1263890 .part L_0x1263d20, 3, 1; +L_0x1263a80 .part L_0x1263530, 0, 1; +L_0x1263c30 .part L_0x1263530, 1, 1; +S_0x105c810 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x105b940; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dd0710/d .functor OR 1, L_0x1dd0780, L_0x1dd08e0, C4<0>, C4<0>; -L_0x1dd0710 .delay 1 (30000,30000,30000) L_0x1dd0710/d; -L_0x1dd0b10/d .functor OR 1, L_0x1dd0c20, L_0x1dd0d80, C4<0>, C4<0>; -L_0x1dd0b10 .delay 1 (30000,30000,30000) L_0x1dd0b10/d; -L_0x1dd0f00/d .functor OR 1, L_0x1dd0f70, L_0x1dd1120, C4<0>, C4<0>; -L_0x1dd0f00 .delay 1 (30000,30000,30000) L_0x1dd0f00/d; -v0x1bc9d50_0 .net *"_s0", 0 0, L_0x1dd0710; 1 drivers -v0x1bc9e50_0 .net *"_s10", 0 0, L_0x1dd0c20; 1 drivers -v0x1bc9f30_0 .net *"_s12", 0 0, L_0x1dd0d80; 1 drivers -v0x1bc9ff0_0 .net *"_s14", 0 0, L_0x1dd0f70; 1 drivers -v0x1bca0d0_0 .net *"_s16", 0 0, L_0x1dd1120; 1 drivers -v0x1bca200_0 .net *"_s3", 0 0, L_0x1dd0780; 1 drivers -v0x1bca2e0_0 .net *"_s5", 0 0, L_0x1dd08e0; 1 drivers -v0x1bca3c0_0 .net *"_s6", 0 0, L_0x1dd0b10; 1 drivers -v0x1bca4a0_0 .net "in", 3 0, L_0x1dd1350; 1 drivers -v0x1bca610_0 .net "ors", 1 0, L_0x1dd0a20; 1 drivers -v0x1bca6f0_0 .net "out", 0 0, L_0x1dd0f00; 1 drivers -L_0x1dd0780 .part L_0x1dd1350, 0, 1; -L_0x1dd08e0 .part L_0x1dd1350, 1, 1; -L_0x1dd0a20 .concat8 [ 1 1 0 0], L_0x1dd0710, L_0x1dd0b10; -L_0x1dd0c20 .part L_0x1dd1350, 2, 1; -L_0x1dd0d80 .part L_0x1dd1350, 3, 1; -L_0x1dd0f70 .part L_0x1dd0a20, 0, 1; -L_0x1dd1120 .part L_0x1dd0a20, 1, 1; -S_0x1bcb000 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bc4130; +L_0x1263e50/d .functor OR 1, L_0x1263ec0, L_0x1264020, C4<0>, C4<0>; +L_0x1263e50 .delay 1 (30000,30000,30000) L_0x1263e50/d; +L_0x1264250/d .functor OR 1, L_0x1264360, L_0x12644c0, C4<0>, C4<0>; +L_0x1264250 .delay 1 (30000,30000,30000) L_0x1264250/d; +L_0x1264640/d .functor OR 1, L_0x12646b0, L_0x1264860, C4<0>, C4<0>; +L_0x1264640 .delay 1 (30000,30000,30000) L_0x1264640/d; +v0x105c9d0_0 .net *"_s0", 0 0, L_0x1263e50; 1 drivers +v0x105cad0_0 .net *"_s10", 0 0, L_0x1264360; 1 drivers +v0x105cbb0_0 .net *"_s12", 0 0, L_0x12644c0; 1 drivers +v0x105cc70_0 .net *"_s14", 0 0, L_0x12646b0; 1 drivers +v0x105cd50_0 .net *"_s16", 0 0, L_0x1264860; 1 drivers +v0x105ce80_0 .net *"_s3", 0 0, L_0x1263ec0; 1 drivers +v0x105cf60_0 .net *"_s5", 0 0, L_0x1264020; 1 drivers +v0x105d040_0 .net *"_s6", 0 0, L_0x1264250; 1 drivers +v0x105d120_0 .net "in", 3 0, L_0x1264a90; 1 drivers +v0x105d290_0 .net "ors", 1 0, L_0x1264160; 1 drivers +v0x105d370_0 .net "out", 0 0, L_0x1264640; 1 drivers +L_0x1263ec0 .part L_0x1264a90, 0, 1; +L_0x1264020 .part L_0x1264a90, 1, 1; +L_0x1264160 .concat8 [ 1 1 0 0], L_0x1263e50, L_0x1264250; +L_0x1264360 .part L_0x1264a90, 2, 1; +L_0x12644c0 .part L_0x1264a90, 3, 1; +L_0x12646b0 .part L_0x1264160, 0, 1; +L_0x1264860 .part L_0x1264160, 1, 1; +S_0x105dc80 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1056db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bd0430_0 .net "ands", 7 0, L_0x1dcb9b0; 1 drivers -v0x1bd0540_0 .net "in", 7 0, L_0x1dc9e10; alias, 1 drivers -v0x1bd0600_0 .net "out", 0 0, L_0x1dcd9b0; alias, 1 drivers -v0x1bd06d0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bcb250 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bcb000; +v0x10630b0_0 .net "ands", 7 0, L_0x125f0f0; 1 drivers +v0x10631c0_0 .net "in", 7 0, L_0x125d550; alias, 1 drivers +v0x1063280_0 .net "out", 0 0, L_0x12610f0; alias, 1 drivers +v0x1063350_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x105ded0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x105dc80; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bcd990_0 .net "A", 7 0, L_0x1dc9e10; alias, 1 drivers -v0x1bcda90_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bcdb50_0 .net *"_s0", 0 0, L_0x1dca1a0; 1 drivers -v0x1bcdc10_0 .net *"_s12", 0 0, L_0x1dcab60; 1 drivers -v0x1bcdcf0_0 .net *"_s16", 0 0, L_0x1dcaec0; 1 drivers -v0x1bcde20_0 .net *"_s20", 0 0, L_0x1dcb2f0; 1 drivers -v0x1bcdf00_0 .net *"_s24", 0 0, L_0x1dcb620; 1 drivers -v0x1bcdfe0_0 .net *"_s28", 0 0, L_0x1dcb5b0; 1 drivers -v0x1bce0c0_0 .net *"_s4", 0 0, L_0x1dca540; 1 drivers -v0x1bce230_0 .net *"_s8", 0 0, L_0x1dca850; 1 drivers -v0x1bce310_0 .net "out", 7 0, L_0x1dcb9b0; alias, 1 drivers -L_0x1dca2b0 .part L_0x1dc9e10, 0, 1; -L_0x1dca4a0 .part v0x1d6daa0_0, 0, 1; -L_0x1dca600 .part L_0x1dc9e10, 1, 1; -L_0x1dca760 .part v0x1d6daa0_0, 1, 1; -L_0x1dca910 .part L_0x1dc9e10, 2, 1; -L_0x1dcaa70 .part v0x1d6daa0_0, 2, 1; -L_0x1dcac20 .part L_0x1dc9e10, 3, 1; -L_0x1dcad80 .part v0x1d6daa0_0, 3, 1; -L_0x1dcaf80 .part L_0x1dc9e10, 4, 1; -L_0x1dcb1f0 .part v0x1d6daa0_0, 4, 1; -L_0x1dcb360 .part L_0x1dc9e10, 5, 1; -L_0x1dcb4c0 .part v0x1d6daa0_0, 5, 1; -L_0x1dcb6e0 .part L_0x1dc9e10, 6, 1; -L_0x1dcb840 .part v0x1d6daa0_0, 6, 1; -LS_0x1dcb9b0_0_0 .concat8 [ 1 1 1 1], L_0x1dca1a0, L_0x1dca540, L_0x1dca850, L_0x1dcab60; -LS_0x1dcb9b0_0_4 .concat8 [ 1 1 1 1], L_0x1dcaec0, L_0x1dcb2f0, L_0x1dcb620, L_0x1dcb5b0; -L_0x1dcb9b0 .concat8 [ 4 4 0 0], LS_0x1dcb9b0_0_0, LS_0x1dcb9b0_0_4; -L_0x1dcbd70 .part L_0x1dc9e10, 7, 1; -L_0x1dcbf60 .part v0x1d6daa0_0, 7, 1; -S_0x1bcb490 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcb6a0 .param/l "i" 0 4 54, +C4<00>; -L_0x1dca1a0/d .functor AND 1, L_0x1dca2b0, L_0x1dca4a0, C4<1>, C4<1>; -L_0x1dca1a0 .delay 1 (30000,30000,30000) L_0x1dca1a0/d; -v0x1bcb780_0 .net *"_s0", 0 0, L_0x1dca2b0; 1 drivers -v0x1bcb860_0 .net *"_s1", 0 0, L_0x1dca4a0; 1 drivers -S_0x1bcb940 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcbb50 .param/l "i" 0 4 54, +C4<01>; -L_0x1dca540/d .functor AND 1, L_0x1dca600, L_0x1dca760, C4<1>, C4<1>; -L_0x1dca540 .delay 1 (30000,30000,30000) L_0x1dca540/d; -v0x1bcbc10_0 .net *"_s0", 0 0, L_0x1dca600; 1 drivers -v0x1bcbcf0_0 .net *"_s1", 0 0, L_0x1dca760; 1 drivers -S_0x1bcbdd0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcc010 .param/l "i" 0 4 54, +C4<010>; -L_0x1dca850/d .functor AND 1, L_0x1dca910, L_0x1dcaa70, C4<1>, C4<1>; -L_0x1dca850 .delay 1 (30000,30000,30000) L_0x1dca850/d; -v0x1bcc0b0_0 .net *"_s0", 0 0, L_0x1dca910; 1 drivers -v0x1bcc190_0 .net *"_s1", 0 0, L_0x1dcaa70; 1 drivers -S_0x1bcc270 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcc480 .param/l "i" 0 4 54, +C4<011>; -L_0x1dcab60/d .functor AND 1, L_0x1dcac20, L_0x1dcad80, C4<1>, C4<1>; -L_0x1dcab60 .delay 1 (30000,30000,30000) L_0x1dcab60/d; -v0x1bcc540_0 .net *"_s0", 0 0, L_0x1dcac20; 1 drivers -v0x1bcc620_0 .net *"_s1", 0 0, L_0x1dcad80; 1 drivers -S_0x1bcc700 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcc960 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dcaec0/d .functor AND 1, L_0x1dcaf80, L_0x1dcb1f0, C4<1>, C4<1>; -L_0x1dcaec0 .delay 1 (30000,30000,30000) L_0x1dcaec0/d; -v0x1bcca20_0 .net *"_s0", 0 0, L_0x1dcaf80; 1 drivers -v0x1bccb00_0 .net *"_s1", 0 0, L_0x1dcb1f0; 1 drivers -S_0x1bccbe0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bccdf0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dcb2f0/d .functor AND 1, L_0x1dcb360, L_0x1dcb4c0, C4<1>, C4<1>; -L_0x1dcb2f0 .delay 1 (30000,30000,30000) L_0x1dcb2f0/d; -v0x1bcceb0_0 .net *"_s0", 0 0, L_0x1dcb360; 1 drivers -v0x1bccf90_0 .net *"_s1", 0 0, L_0x1dcb4c0; 1 drivers -S_0x1bcd070 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcd280 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dcb620/d .functor AND 1, L_0x1dcb6e0, L_0x1dcb840, C4<1>, C4<1>; -L_0x1dcb620 .delay 1 (30000,30000,30000) L_0x1dcb620/d; -v0x1bcd340_0 .net *"_s0", 0 0, L_0x1dcb6e0; 1 drivers -v0x1bcd420_0 .net *"_s1", 0 0, L_0x1dcb840; 1 drivers -S_0x1bcd500 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bcb250; - .timescale -9 -12; -P_0x1bcd710 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dcb5b0/d .functor AND 1, L_0x1dcbd70, L_0x1dcbf60, C4<1>, C4<1>; -L_0x1dcb5b0 .delay 1 (30000,30000,30000) L_0x1dcb5b0/d; -v0x1bcd7d0_0 .net *"_s0", 0 0, L_0x1dcbd70; 1 drivers -v0x1bcd8b0_0 .net *"_s1", 0 0, L_0x1dcbf60; 1 drivers -S_0x1bce470 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bcb000; +v0x1060610_0 .net "A", 7 0, L_0x125d550; alias, 1 drivers +v0x1060710_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10607d0_0 .net *"_s0", 0 0, L_0x125d8e0; 1 drivers +v0x1060890_0 .net *"_s12", 0 0, L_0x125e2a0; 1 drivers +v0x1060970_0 .net *"_s16", 0 0, L_0x125e600; 1 drivers +v0x1060aa0_0 .net *"_s20", 0 0, L_0x125ea30; 1 drivers +v0x1060b80_0 .net *"_s24", 0 0, L_0x125ed60; 1 drivers +v0x1060c60_0 .net *"_s28", 0 0, L_0x125ecf0; 1 drivers +v0x1060d40_0 .net *"_s4", 0 0, L_0x125dc80; 1 drivers +v0x1060eb0_0 .net *"_s8", 0 0, L_0x125df90; 1 drivers +v0x1060f90_0 .net "out", 7 0, L_0x125f0f0; alias, 1 drivers +L_0x125d9f0 .part L_0x125d550, 0, 1; +L_0x125dbe0 .part v0x12010b0_0, 0, 1; +L_0x125dd40 .part L_0x125d550, 1, 1; +L_0x125dea0 .part v0x12010b0_0, 1, 1; +L_0x125e050 .part L_0x125d550, 2, 1; +L_0x125e1b0 .part v0x12010b0_0, 2, 1; +L_0x125e360 .part L_0x125d550, 3, 1; +L_0x125e4c0 .part v0x12010b0_0, 3, 1; +L_0x125e6c0 .part L_0x125d550, 4, 1; +L_0x125e930 .part v0x12010b0_0, 4, 1; +L_0x125eaa0 .part L_0x125d550, 5, 1; +L_0x125ec00 .part v0x12010b0_0, 5, 1; +L_0x125ee20 .part L_0x125d550, 6, 1; +L_0x125ef80 .part v0x12010b0_0, 6, 1; +LS_0x125f0f0_0_0 .concat8 [ 1 1 1 1], L_0x125d8e0, L_0x125dc80, L_0x125df90, L_0x125e2a0; +LS_0x125f0f0_0_4 .concat8 [ 1 1 1 1], L_0x125e600, L_0x125ea30, L_0x125ed60, L_0x125ecf0; +L_0x125f0f0 .concat8 [ 4 4 0 0], LS_0x125f0f0_0_0, LS_0x125f0f0_0_4; +L_0x125f4b0 .part L_0x125d550, 7, 1; +L_0x125f6a0 .part v0x12010b0_0, 7, 1; +S_0x105e110 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105e320 .param/l "i" 0 4 54, +C4<00>; +L_0x125d8e0/d .functor AND 1, L_0x125d9f0, L_0x125dbe0, C4<1>, C4<1>; +L_0x125d8e0 .delay 1 (30000,30000,30000) L_0x125d8e0/d; +v0x105e400_0 .net *"_s0", 0 0, L_0x125d9f0; 1 drivers +v0x105e4e0_0 .net *"_s1", 0 0, L_0x125dbe0; 1 drivers +S_0x105e5c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105e7d0 .param/l "i" 0 4 54, +C4<01>; +L_0x125dc80/d .functor AND 1, L_0x125dd40, L_0x125dea0, C4<1>, C4<1>; +L_0x125dc80 .delay 1 (30000,30000,30000) L_0x125dc80/d; +v0x105e890_0 .net *"_s0", 0 0, L_0x125dd40; 1 drivers +v0x105e970_0 .net *"_s1", 0 0, L_0x125dea0; 1 drivers +S_0x105ea50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105ec90 .param/l "i" 0 4 54, +C4<010>; +L_0x125df90/d .functor AND 1, L_0x125e050, L_0x125e1b0, C4<1>, C4<1>; +L_0x125df90 .delay 1 (30000,30000,30000) L_0x125df90/d; +v0x105ed30_0 .net *"_s0", 0 0, L_0x125e050; 1 drivers +v0x105ee10_0 .net *"_s1", 0 0, L_0x125e1b0; 1 drivers +S_0x105eef0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105f100 .param/l "i" 0 4 54, +C4<011>; +L_0x125e2a0/d .functor AND 1, L_0x125e360, L_0x125e4c0, C4<1>, C4<1>; +L_0x125e2a0 .delay 1 (30000,30000,30000) L_0x125e2a0/d; +v0x105f1c0_0 .net *"_s0", 0 0, L_0x125e360; 1 drivers +v0x105f2a0_0 .net *"_s1", 0 0, L_0x125e4c0; 1 drivers +S_0x105f380 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105f5e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x125e600/d .functor AND 1, L_0x125e6c0, L_0x125e930, C4<1>, C4<1>; +L_0x125e600 .delay 1 (30000,30000,30000) L_0x125e600/d; +v0x105f6a0_0 .net *"_s0", 0 0, L_0x125e6c0; 1 drivers +v0x105f780_0 .net *"_s1", 0 0, L_0x125e930; 1 drivers +S_0x105f860 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105fa70 .param/l "i" 0 4 54, +C4<0101>; +L_0x125ea30/d .functor AND 1, L_0x125eaa0, L_0x125ec00, C4<1>, C4<1>; +L_0x125ea30 .delay 1 (30000,30000,30000) L_0x125ea30/d; +v0x105fb30_0 .net *"_s0", 0 0, L_0x125eaa0; 1 drivers +v0x105fc10_0 .net *"_s1", 0 0, L_0x125ec00; 1 drivers +S_0x105fcf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x105ff00 .param/l "i" 0 4 54, +C4<0110>; +L_0x125ed60/d .functor AND 1, L_0x125ee20, L_0x125ef80, C4<1>, C4<1>; +L_0x125ed60 .delay 1 (30000,30000,30000) L_0x125ed60/d; +v0x105ffc0_0 .net *"_s0", 0 0, L_0x125ee20; 1 drivers +v0x10600a0_0 .net *"_s1", 0 0, L_0x125ef80; 1 drivers +S_0x1060180 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x105ded0; + .timescale -9 -12; +P_0x1060390 .param/l "i" 0 4 54, +C4<0111>; +L_0x125ecf0/d .functor AND 1, L_0x125f4b0, L_0x125f6a0, C4<1>, C4<1>; +L_0x125ecf0 .delay 1 (30000,30000,30000) L_0x125ecf0/d; +v0x1060450_0 .net *"_s0", 0 0, L_0x125f4b0; 1 drivers +v0x1060530_0 .net *"_s1", 0 0, L_0x125f6a0; 1 drivers +S_0x10610f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x105dc80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dcd9b0/d .functor OR 1, L_0x1dcda70, L_0x1dcdc20, C4<0>, C4<0>; -L_0x1dcd9b0 .delay 1 (30000,30000,30000) L_0x1dcd9b0/d; -v0x1bcffc0_0 .net *"_s10", 0 0, L_0x1dcda70; 1 drivers -v0x1bd00a0_0 .net *"_s12", 0 0, L_0x1dcdc20; 1 drivers -v0x1bd0180_0 .net "in", 7 0, L_0x1dcb9b0; alias, 1 drivers -v0x1bd0250_0 .net "ors", 1 0, L_0x1dcd7d0; 1 drivers -v0x1bd0310_0 .net "out", 0 0, L_0x1dcd9b0; alias, 1 drivers -L_0x1dccba0 .part L_0x1dcb9b0, 0, 4; -L_0x1dcd7d0 .concat8 [ 1 1 0 0], L_0x1dcc890, L_0x1dcd4c0; -L_0x1dcd910 .part L_0x1dcb9b0, 4, 4; -L_0x1dcda70 .part L_0x1dcd7d0, 0, 1; -L_0x1dcdc20 .part L_0x1dcd7d0, 1, 1; -S_0x1bce630 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bce470; +L_0x12610f0/d .functor OR 1, L_0x12611b0, L_0x1261360, C4<0>, C4<0>; +L_0x12610f0 .delay 1 (30000,30000,30000) L_0x12610f0/d; +v0x1062c40_0 .net *"_s10", 0 0, L_0x12611b0; 1 drivers +v0x1062d20_0 .net *"_s12", 0 0, L_0x1261360; 1 drivers +v0x1062e00_0 .net "in", 7 0, L_0x125f0f0; alias, 1 drivers +v0x1062ed0_0 .net "ors", 1 0, L_0x1260f10; 1 drivers +v0x1062f90_0 .net "out", 0 0, L_0x12610f0; alias, 1 drivers +L_0x12602e0 .part L_0x125f0f0, 0, 4; +L_0x1260f10 .concat8 [ 1 1 0 0], L_0x125ffd0, L_0x1260c00; +L_0x1261050 .part L_0x125f0f0, 4, 4; +L_0x12611b0 .part L_0x1260f10, 0, 1; +L_0x1261360 .part L_0x1260f10, 1, 1; +S_0x10612b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10610f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dcc050/d .functor OR 1, L_0x1dcc110, L_0x1dcc270, C4<0>, C4<0>; -L_0x1dcc050 .delay 1 (30000,30000,30000) L_0x1dcc050/d; -L_0x1dcc4a0/d .functor OR 1, L_0x1dcc5b0, L_0x1dcc710, C4<0>, C4<0>; -L_0x1dcc4a0 .delay 1 (30000,30000,30000) L_0x1dcc4a0/d; -L_0x1dcc890/d .functor OR 1, L_0x1dcc900, L_0x1dccab0, C4<0>, C4<0>; -L_0x1dcc890 .delay 1 (30000,30000,30000) L_0x1dcc890/d; -v0x1bce880_0 .net *"_s0", 0 0, L_0x1dcc050; 1 drivers -v0x1bce980_0 .net *"_s10", 0 0, L_0x1dcc5b0; 1 drivers -v0x1bcea60_0 .net *"_s12", 0 0, L_0x1dcc710; 1 drivers -v0x1bceb20_0 .net *"_s14", 0 0, L_0x1dcc900; 1 drivers -v0x1bcec00_0 .net *"_s16", 0 0, L_0x1dccab0; 1 drivers -v0x1bced30_0 .net *"_s3", 0 0, L_0x1dcc110; 1 drivers -v0x1bcee10_0 .net *"_s5", 0 0, L_0x1dcc270; 1 drivers -v0x1bceef0_0 .net *"_s6", 0 0, L_0x1dcc4a0; 1 drivers -v0x1bcefd0_0 .net "in", 3 0, L_0x1dccba0; 1 drivers -v0x1bcf140_0 .net "ors", 1 0, L_0x1dcc3b0; 1 drivers -v0x1bcf220_0 .net "out", 0 0, L_0x1dcc890; 1 drivers -L_0x1dcc110 .part L_0x1dccba0, 0, 1; -L_0x1dcc270 .part L_0x1dccba0, 1, 1; -L_0x1dcc3b0 .concat8 [ 1 1 0 0], L_0x1dcc050, L_0x1dcc4a0; -L_0x1dcc5b0 .part L_0x1dccba0, 2, 1; -L_0x1dcc710 .part L_0x1dccba0, 3, 1; -L_0x1dcc900 .part L_0x1dcc3b0, 0, 1; -L_0x1dccab0 .part L_0x1dcc3b0, 1, 1; -S_0x1bcf340 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bce470; +L_0x125f790/d .functor OR 1, L_0x125f850, L_0x125f9b0, C4<0>, C4<0>; +L_0x125f790 .delay 1 (30000,30000,30000) L_0x125f790/d; +L_0x125fbe0/d .functor OR 1, L_0x125fcf0, L_0x125fe50, C4<0>, C4<0>; +L_0x125fbe0 .delay 1 (30000,30000,30000) L_0x125fbe0/d; +L_0x125ffd0/d .functor OR 1, L_0x1260040, L_0x12601f0, C4<0>, C4<0>; +L_0x125ffd0 .delay 1 (30000,30000,30000) L_0x125ffd0/d; +v0x1061500_0 .net *"_s0", 0 0, L_0x125f790; 1 drivers +v0x1061600_0 .net *"_s10", 0 0, L_0x125fcf0; 1 drivers +v0x10616e0_0 .net *"_s12", 0 0, L_0x125fe50; 1 drivers +v0x10617a0_0 .net *"_s14", 0 0, L_0x1260040; 1 drivers +v0x1061880_0 .net *"_s16", 0 0, L_0x12601f0; 1 drivers +v0x10619b0_0 .net *"_s3", 0 0, L_0x125f850; 1 drivers +v0x1061a90_0 .net *"_s5", 0 0, L_0x125f9b0; 1 drivers +v0x1061b70_0 .net *"_s6", 0 0, L_0x125fbe0; 1 drivers +v0x1061c50_0 .net "in", 3 0, L_0x12602e0; 1 drivers +v0x1061dc0_0 .net "ors", 1 0, L_0x125faf0; 1 drivers +v0x1061ea0_0 .net "out", 0 0, L_0x125ffd0; 1 drivers +L_0x125f850 .part L_0x12602e0, 0, 1; +L_0x125f9b0 .part L_0x12602e0, 1, 1; +L_0x125faf0 .concat8 [ 1 1 0 0], L_0x125f790, L_0x125fbe0; +L_0x125fcf0 .part L_0x12602e0, 2, 1; +L_0x125fe50 .part L_0x12602e0, 3, 1; +L_0x1260040 .part L_0x125faf0, 0, 1; +L_0x12601f0 .part L_0x125faf0, 1, 1; +S_0x1061fc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10610f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dcccd0/d .functor OR 1, L_0x1dccd40, L_0x1dccea0, C4<0>, C4<0>; -L_0x1dcccd0 .delay 1 (30000,30000,30000) L_0x1dcccd0/d; -L_0x1dcd0d0/d .functor OR 1, L_0x1dcd1e0, L_0x1dcd340, C4<0>, C4<0>; -L_0x1dcd0d0 .delay 1 (30000,30000,30000) L_0x1dcd0d0/d; -L_0x1dcd4c0/d .functor OR 1, L_0x1dcd530, L_0x1dcd6e0, C4<0>, C4<0>; -L_0x1dcd4c0 .delay 1 (30000,30000,30000) L_0x1dcd4c0/d; -v0x1bcf500_0 .net *"_s0", 0 0, L_0x1dcccd0; 1 drivers -v0x1bcf600_0 .net *"_s10", 0 0, L_0x1dcd1e0; 1 drivers -v0x1bcf6e0_0 .net *"_s12", 0 0, L_0x1dcd340; 1 drivers -v0x1bcf7a0_0 .net *"_s14", 0 0, L_0x1dcd530; 1 drivers -v0x1bcf880_0 .net *"_s16", 0 0, L_0x1dcd6e0; 1 drivers -v0x1bcf9b0_0 .net *"_s3", 0 0, L_0x1dccd40; 1 drivers -v0x1bcfa90_0 .net *"_s5", 0 0, L_0x1dccea0; 1 drivers -v0x1bcfb70_0 .net *"_s6", 0 0, L_0x1dcd0d0; 1 drivers -v0x1bcfc50_0 .net "in", 3 0, L_0x1dcd910; 1 drivers -v0x1bcfdc0_0 .net "ors", 1 0, L_0x1dccfe0; 1 drivers -v0x1bcfea0_0 .net "out", 0 0, L_0x1dcd4c0; 1 drivers -L_0x1dccd40 .part L_0x1dcd910, 0, 1; -L_0x1dccea0 .part L_0x1dcd910, 1, 1; -L_0x1dccfe0 .concat8 [ 1 1 0 0], L_0x1dcccd0, L_0x1dcd0d0; -L_0x1dcd1e0 .part L_0x1dcd910, 2, 1; -L_0x1dcd340 .part L_0x1dcd910, 3, 1; -L_0x1dcd530 .part L_0x1dccfe0, 0, 1; -L_0x1dcd6e0 .part L_0x1dccfe0, 1, 1; -S_0x1bd07b0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bc4130; +L_0x1260410/d .functor OR 1, L_0x1260480, L_0x12605e0, C4<0>, C4<0>; +L_0x1260410 .delay 1 (30000,30000,30000) L_0x1260410/d; +L_0x1260810/d .functor OR 1, L_0x1260920, L_0x1260a80, C4<0>, C4<0>; +L_0x1260810 .delay 1 (30000,30000,30000) L_0x1260810/d; +L_0x1260c00/d .functor OR 1, L_0x1260c70, L_0x1260e20, C4<0>, C4<0>; +L_0x1260c00 .delay 1 (30000,30000,30000) L_0x1260c00/d; +v0x1062180_0 .net *"_s0", 0 0, L_0x1260410; 1 drivers +v0x1062280_0 .net *"_s10", 0 0, L_0x1260920; 1 drivers +v0x1062360_0 .net *"_s12", 0 0, L_0x1260a80; 1 drivers +v0x1062420_0 .net *"_s14", 0 0, L_0x1260c70; 1 drivers +v0x1062500_0 .net *"_s16", 0 0, L_0x1260e20; 1 drivers +v0x1062630_0 .net *"_s3", 0 0, L_0x1260480; 1 drivers +v0x1062710_0 .net *"_s5", 0 0, L_0x12605e0; 1 drivers +v0x10627f0_0 .net *"_s6", 0 0, L_0x1260810; 1 drivers +v0x10628d0_0 .net "in", 3 0, L_0x1261050; 1 drivers +v0x1062a40_0 .net "ors", 1 0, L_0x1260720; 1 drivers +v0x1062b20_0 .net "out", 0 0, L_0x1260c00; 1 drivers +L_0x1260480 .part L_0x1261050, 0, 1; +L_0x12605e0 .part L_0x1261050, 1, 1; +L_0x1260720 .concat8 [ 1 1 0 0], L_0x1260410, L_0x1260810; +L_0x1260920 .part L_0x1261050, 2, 1; +L_0x1260a80 .part L_0x1261050, 3, 1; +L_0x1260c70 .part L_0x1260720, 0, 1; +L_0x1260e20 .part L_0x1260720, 1, 1; +S_0x1063430 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1056db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -5452,80 +5462,80 @@ S_0x1bd07b0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bc4130; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1dc9180/d .functor XNOR 1, L_0x1dd1850, L_0x1dc7d40, C4<0>, C4<0>; -L_0x1dc9180 .delay 1 (20000,20000,20000) L_0x1dc9180/d; -L_0x1dc93f0/d .functor AND 1, L_0x1dd1850, L_0x1dc1c20, C4<1>, C4<1>; -L_0x1dc93f0 .delay 1 (30000,30000,30000) L_0x1dc93f0/d; -L_0x1dc9460/d .functor AND 1, L_0x1dc9180, L_0x1dd1aa0, C4<1>, C4<1>; -L_0x1dc9460 .delay 1 (30000,30000,30000) L_0x1dc9460/d; -L_0x1dc95c0/d .functor OR 1, L_0x1dc9460, L_0x1dc93f0, C4<0>, C4<0>; -L_0x1dc95c0 .delay 1 (30000,30000,30000) L_0x1dc95c0/d; -v0x1bd0a60_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers -v0x1bd0b50_0 .net "a_", 0 0, L_0x1dc7f10; alias, 1 drivers -v0x1bd0c10_0 .net "b", 0 0, L_0x1dc7d40; alias, 1 drivers -v0x1bd0d00_0 .net "b_", 0 0, L_0x1dc1c20; alias, 1 drivers -v0x1bd0da0_0 .net "carryin", 0 0, L_0x1dd1aa0; alias, 1 drivers -v0x1bd0ee0_0 .net "eq", 0 0, L_0x1dc9180; 1 drivers -v0x1bd0fa0_0 .net "lt", 0 0, L_0x1dc93f0; 1 drivers -v0x1bd1060_0 .net "out", 0 0, L_0x1dc95c0; 1 drivers -v0x1bd1120_0 .net "w0", 0 0, L_0x1dc9460; 1 drivers -S_0x1bd1370 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bc4130; +L_0x125c8c0/d .functor XNOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; +L_0x125c8c0 .delay 1 (20000,20000,20000) L_0x125c8c0/d; +L_0x125cb30/d .functor AND 1, L_0x1264f90, L_0x1255360, C4<1>, C4<1>; +L_0x125cb30 .delay 1 (30000,30000,30000) L_0x125cb30/d; +L_0x125cba0/d .functor AND 1, L_0x125c8c0, L_0x12651e0, C4<1>, C4<1>; +L_0x125cba0 .delay 1 (30000,30000,30000) L_0x125cba0/d; +L_0x125cd00/d .functor OR 1, L_0x125cba0, L_0x125cb30, C4<0>, C4<0>; +L_0x125cd00 .delay 1 (30000,30000,30000) L_0x125cd00/d; +v0x10636e0_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers +v0x10637d0_0 .net "a_", 0 0, L_0x125b650; alias, 1 drivers +v0x1063890_0 .net "b", 0 0, L_0x125b480; alias, 1 drivers +v0x1063980_0 .net "b_", 0 0, L_0x1255360; alias, 1 drivers +v0x1063a20_0 .net "carryin", 0 0, L_0x12651e0; alias, 1 drivers +v0x1063b60_0 .net "eq", 0 0, L_0x125c8c0; 1 drivers +v0x1063c20_0 .net "lt", 0 0, L_0x125cb30; 1 drivers +v0x1063ce0_0 .net "out", 0 0, L_0x125cd00; 1 drivers +v0x1063da0_0 .net "w0", 0 0, L_0x125cba0; 1 drivers +S_0x1063ff0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1056db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dc8f60/d .functor OR 1, L_0x1dc8ab0, L_0x1bd25d0, C4<0>, C4<0>; -L_0x1dc8f60 .delay 1 (30000,30000,30000) L_0x1dc8f60/d; -v0x1bd2160_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers -v0x1bd22b0_0 .net "b", 0 0, L_0x1dc1c20; alias, 1 drivers -v0x1bd2370_0 .net "c1", 0 0, L_0x1dc8ab0; 1 drivers -v0x1bd2410_0 .net "c2", 0 0, L_0x1bd25d0; 1 drivers -v0x1bd24e0_0 .net "carryin", 0 0, L_0x1dd1aa0; alias, 1 drivers -v0x1bd2660_0 .net "carryout", 0 0, L_0x1dc8f60; 1 drivers -v0x1bd2700_0 .net "s1", 0 0, L_0x1dc89f0; 1 drivers -v0x1bd27a0_0 .net "sum", 0 0, L_0x1dc8c10; 1 drivers -S_0x1bd15c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bd1370; +L_0x125c6a0/d .functor OR 1, L_0x125c1f0, L_0x1065210, C4<0>, C4<0>; +L_0x125c6a0 .delay 1 (30000,30000,30000) L_0x125c6a0/d; +v0x1064da0_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers +v0x1064ef0_0 .net "b", 0 0, L_0x1255360; alias, 1 drivers +v0x1064fb0_0 .net "c1", 0 0, L_0x125c1f0; 1 drivers +v0x1065050_0 .net "c2", 0 0, L_0x1065210; 1 drivers +v0x1065120_0 .net "carryin", 0 0, L_0x12651e0; alias, 1 drivers +v0x10652a0_0 .net "carryout", 0 0, L_0x125c6a0; 1 drivers +v0x1065340_0 .net "s1", 0 0, L_0x125c130; 1 drivers +v0x10653e0_0 .net "sum", 0 0, L_0x125c350; 1 drivers +S_0x1064240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1063ff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dc89f0/d .functor XOR 1, L_0x1dd1850, L_0x1dc1c20, C4<0>, C4<0>; -L_0x1dc89f0 .delay 1 (30000,30000,30000) L_0x1dc89f0/d; -L_0x1dc8ab0/d .functor AND 1, L_0x1dd1850, L_0x1dc1c20, C4<1>, C4<1>; -L_0x1dc8ab0 .delay 1 (30000,30000,30000) L_0x1dc8ab0/d; -v0x1bd1820_0 .net "a", 0 0, L_0x1dd1850; alias, 1 drivers -v0x1bd18e0_0 .net "b", 0 0, L_0x1dc1c20; alias, 1 drivers -v0x1bd19a0_0 .net "carryout", 0 0, L_0x1dc8ab0; alias, 1 drivers -v0x1bd1a40_0 .net "sum", 0 0, L_0x1dc89f0; alias, 1 drivers -S_0x1bd1b70 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bd1370; +L_0x125c130/d .functor XOR 1, L_0x1264f90, L_0x1255360, C4<0>, C4<0>; +L_0x125c130 .delay 1 (30000,30000,30000) L_0x125c130/d; +L_0x125c1f0/d .functor AND 1, L_0x1264f90, L_0x1255360, C4<1>, C4<1>; +L_0x125c1f0 .delay 1 (30000,30000,30000) L_0x125c1f0/d; +v0x1064480_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers +v0x1064520_0 .net "b", 0 0, L_0x1255360; alias, 1 drivers +v0x10645c0_0 .net "carryout", 0 0, L_0x125c1f0; alias, 1 drivers +v0x1064690_0 .net "sum", 0 0, L_0x125c130; alias, 1 drivers +S_0x10647c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1063ff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dc8c10/d .functor XOR 1, L_0x1dc89f0, L_0x1dd1aa0, C4<0>, C4<0>; -L_0x1dc8c10 .delay 1 (30000,30000,30000) L_0x1dc8c10/d; -L_0x1bd25d0/d .functor AND 1, L_0x1dc89f0, L_0x1dd1aa0, C4<1>, C4<1>; -L_0x1bd25d0 .delay 1 (30000,30000,30000) L_0x1bd25d0/d; -v0x1bd1dd0_0 .net "a", 0 0, L_0x1dc89f0; alias, 1 drivers -v0x1bd1ea0_0 .net "b", 0 0, L_0x1dd1aa0; alias, 1 drivers -v0x1bd1f40_0 .net "carryout", 0 0, L_0x1bd25d0; alias, 1 drivers -v0x1bd2010_0 .net "sum", 0 0, L_0x1dc8c10; alias, 1 drivers -S_0x1bd3bc0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bc3e60; - .timescale -9 -12; -L_0x7f72592daa38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592daa80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dd18f0/d .functor OR 1, L_0x7f72592daa38, L_0x7f72592daa80, C4<0>, C4<0>; -L_0x1dd18f0 .delay 1 (30000,30000,30000) L_0x1dd18f0/d; -v0x1bd3db0_0 .net/2u *"_s0", 0 0, L_0x7f72592daa38; 1 drivers -v0x1bd3e90_0 .net/2u *"_s2", 0 0, L_0x7f72592daa80; 1 drivers -S_0x1bd3f70 .scope generate, "alu_slices[10]" "alu_slices[10]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1bd4180 .param/l "i" 0 3 37, +C4<01010>; -S_0x1bd4240 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bd3f70; +L_0x125c350/d .functor XOR 1, L_0x125c130, L_0x12651e0, C4<0>, C4<0>; +L_0x125c350 .delay 1 (30000,30000,30000) L_0x125c350/d; +L_0x1065210/d .functor AND 1, L_0x125c130, L_0x12651e0, C4<1>, C4<1>; +L_0x1065210 .delay 1 (30000,30000,30000) L_0x1065210/d; +v0x1064a20_0 .net "a", 0 0, L_0x125c130; alias, 1 drivers +v0x1064ae0_0 .net "b", 0 0, L_0x12651e0; alias, 1 drivers +v0x1064b80_0 .net "carryout", 0 0, L_0x1065210; alias, 1 drivers +v0x1064c50_0 .net "sum", 0 0, L_0x125c350; alias, 1 drivers +S_0x1066840 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1056ae0; + .timescale -9 -12; +L_0x2b0ab3d05a38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05a80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1265030/d .functor OR 1, L_0x2b0ab3d05a38, L_0x2b0ab3d05a80, C4<0>, C4<0>; +L_0x1265030 .delay 1 (30000,30000,30000) L_0x1265030/d; +v0x1066a30_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05a38; 1 drivers +v0x1066b10_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05a80; 1 drivers +S_0x1066bf0 .scope generate, "alu_slices[10]" "alu_slices[10]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1066e00 .param/l "i" 0 3 41, +C4<01010>; +S_0x1066ec0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1066bf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -5534,445 +5544,445 @@ S_0x1bd4240 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bd3f70; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1dd1c90/d .functor NOT 1, L_0x1ddb470, C4<0>, C4<0>, C4<0>; -L_0x1dd1c90 .delay 1 (10000,10000,10000) L_0x1dd1c90/d; -L_0x1dd1da0/d .functor NOT 1, L_0x1ddb5d0, C4<0>, C4<0>, C4<0>; -L_0x1dd1da0 .delay 1 (10000,10000,10000) L_0x1dd1da0/d; -L_0x1dd2df0/d .functor XOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; -L_0x1dd2df0 .delay 1 (30000,30000,30000) L_0x1dd2df0/d; -L_0x7f72592daac8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dab10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dd34a0/d .functor OR 1, L_0x7f72592daac8, L_0x7f72592dab10, C4<0>, C4<0>; -L_0x1dd34a0 .delay 1 (30000,30000,30000) L_0x1dd34a0/d; -L_0x1dd36a0/d .functor AND 1, L_0x1ddb470, L_0x1ddb5d0, C4<1>, C4<1>; -L_0x1dd36a0 .delay 1 (30000,30000,30000) L_0x1dd36a0/d; -L_0x1dd3760/d .functor NAND 1, L_0x1ddb470, L_0x1ddb5d0, C4<1>, C4<1>; -L_0x1dd3760 .delay 1 (20000,20000,20000) L_0x1dd3760/d; -L_0x1dd38c0/d .functor XOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; -L_0x1dd38c0 .delay 1 (20000,20000,20000) L_0x1dd38c0/d; -L_0x1dd3d70/d .functor OR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; -L_0x1dd3d70 .delay 1 (30000,30000,30000) L_0x1dd3d70/d; -L_0x1ddb370/d .functor NOT 1, L_0x1dd7600, C4<0>, C4<0>, C4<0>; -L_0x1ddb370 .delay 1 (10000,10000,10000) L_0x1ddb370/d; -v0x1be2970_0 .net "A", 0 0, L_0x1ddb470; 1 drivers -v0x1be2a30_0 .net "A_", 0 0, L_0x1dd1c90; 1 drivers -v0x1be2af0_0 .net "B", 0 0, L_0x1ddb5d0; 1 drivers -v0x1be2bc0_0 .net "B_", 0 0, L_0x1dd1da0; 1 drivers -v0x1be2c60_0 .net *"_s12", 0 0, L_0x1dd34a0; 1 drivers -v0x1be2d50_0 .net/2s *"_s14", 0 0, L_0x7f72592daac8; 1 drivers -v0x1be2e10_0 .net/2s *"_s16", 0 0, L_0x7f72592dab10; 1 drivers -v0x1be2ef0_0 .net *"_s18", 0 0, L_0x1dd36a0; 1 drivers -v0x1be2fd0_0 .net *"_s20", 0 0, L_0x1dd3760; 1 drivers -v0x1be3140_0 .net *"_s22", 0 0, L_0x1dd38c0; 1 drivers -v0x1be3220_0 .net *"_s24", 0 0, L_0x1dd3d70; 1 drivers -o0x7f725936d7e8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1be3300_0 name=_s30 -o0x7f725936d818 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1be33e0_0 name=_s32 -v0x1be34c0_0 .net *"_s8", 0 0, L_0x1dd2df0; 1 drivers -v0x1be35a0_0 .net "carryin", 0 0, L_0x1dd1b40; 1 drivers -v0x1be3640_0 .net "carryout", 0 0, L_0x1ddb010; 1 drivers -v0x1be36e0_0 .net "carryouts", 7 0, L_0x1ebfb50; 1 drivers -v0x1be3890_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1be3930_0 .net "result", 0 0, L_0x1dd7600; 1 drivers -v0x1be3a20_0 .net "results", 7 0, L_0x1dd3b40; 1 drivers -v0x1be3b30_0 .net "zero", 0 0, L_0x1ddb370; 1 drivers -LS_0x1dd3b40_0_0 .concat8 [ 1 1 1 1], L_0x1dd22c0, L_0x1dd28f0, L_0x1dd2df0, L_0x1dd34a0; -LS_0x1dd3b40_0_4 .concat8 [ 1 1 1 1], L_0x1dd36a0, L_0x1dd3760, L_0x1dd38c0, L_0x1dd3d70; -L_0x1dd3b40 .concat8 [ 4 4 0 0], LS_0x1dd3b40_0_0, LS_0x1dd3b40_0_4; -LS_0x1ebfb50_0_0 .concat [ 1 1 1 1], L_0x1dd2570, L_0x1dd2c90, o0x7f725936d7e8, L_0x1dd32f0; -LS_0x1ebfb50_0_4 .concat [ 4 0 0 0], o0x7f725936d818; -L_0x1ebfb50 .concat [ 4 4 0 0], LS_0x1ebfb50_0_0, LS_0x1ebfb50_0_4; -S_0x1bd44c0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bd4240; +L_0x12653d0/d .functor NOT 1, L_0x126ebe0, C4<0>, C4<0>, C4<0>; +L_0x12653d0 .delay 1 (10000,10000,10000) L_0x12653d0/d; +L_0x12654e0/d .functor NOT 1, L_0x126ed40, C4<0>, C4<0>, C4<0>; +L_0x12654e0 .delay 1 (10000,10000,10000) L_0x12654e0/d; +L_0x1266530/d .functor XOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; +L_0x1266530 .delay 1 (30000,30000,30000) L_0x1266530/d; +L_0x2b0ab3d05ac8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05b10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1266be0/d .functor OR 1, L_0x2b0ab3d05ac8, L_0x2b0ab3d05b10, C4<0>, C4<0>; +L_0x1266be0 .delay 1 (30000,30000,30000) L_0x1266be0/d; +L_0x1266de0/d .functor AND 1, L_0x126ebe0, L_0x126ed40, C4<1>, C4<1>; +L_0x1266de0 .delay 1 (30000,30000,30000) L_0x1266de0/d; +L_0x1266ea0/d .functor NAND 1, L_0x126ebe0, L_0x126ed40, C4<1>, C4<1>; +L_0x1266ea0 .delay 1 (20000,20000,20000) L_0x1266ea0/d; +L_0x1267000/d .functor XOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; +L_0x1267000 .delay 1 (20000,20000,20000) L_0x1267000/d; +L_0x12674b0/d .functor OR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; +L_0x12674b0 .delay 1 (30000,30000,30000) L_0x12674b0/d; +L_0x126eae0/d .functor NOT 1, L_0x126ad40, C4<0>, C4<0>, C4<0>; +L_0x126eae0 .delay 1 (10000,10000,10000) L_0x126eae0/d; +v0x10755f0_0 .net "A", 0 0, L_0x126ebe0; 1 drivers +v0x10756b0_0 .net "A_", 0 0, L_0x12653d0; 1 drivers +v0x1075770_0 .net "B", 0 0, L_0x126ed40; 1 drivers +v0x1075840_0 .net "B_", 0 0, L_0x12654e0; 1 drivers +v0x10758e0_0 .net *"_s12", 0 0, L_0x1266be0; 1 drivers +v0x10759d0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05ac8; 1 drivers +v0x1075a90_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05b10; 1 drivers +v0x1075b70_0 .net *"_s18", 0 0, L_0x1266de0; 1 drivers +v0x1075c50_0 .net *"_s20", 0 0, L_0x1266ea0; 1 drivers +v0x1075dc0_0 .net *"_s22", 0 0, L_0x1267000; 1 drivers +v0x1075ea0_0 .net *"_s24", 0 0, L_0x12674b0; 1 drivers +o0x2b0ab3cbc7e8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1075f80_0 name=_s30 +o0x2b0ab3cbc818 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1076060_0 name=_s32 +v0x1076140_0 .net *"_s8", 0 0, L_0x1266530; 1 drivers +v0x1076220_0 .net "carryin", 0 0, L_0x1265280; 1 drivers +v0x10762c0_0 .net "carryout", 0 0, L_0x126e780; 1 drivers +v0x1076360_0 .net "carryouts", 7 0, L_0x1353f00; 1 drivers +v0x1076510_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10765b0_0 .net "result", 0 0, L_0x126ad40; 1 drivers +v0x10766a0_0 .net "results", 7 0, L_0x1267280; 1 drivers +v0x10767b0_0 .net "zero", 0 0, L_0x126eae0; 1 drivers +LS_0x1267280_0_0 .concat8 [ 1 1 1 1], L_0x1265a00, L_0x1266030, L_0x1266530, L_0x1266be0; +LS_0x1267280_0_4 .concat8 [ 1 1 1 1], L_0x1266de0, L_0x1266ea0, L_0x1267000, L_0x12674b0; +L_0x1267280 .concat8 [ 4 4 0 0], LS_0x1267280_0_0, LS_0x1267280_0_4; +LS_0x1353f00_0_0 .concat [ 1 1 1 1], L_0x1265cb0, L_0x12663d0, o0x2b0ab3cbc7e8, L_0x1266a30; +LS_0x1353f00_0_4 .concat [ 4 0 0 0], o0x2b0ab3cbc818; +L_0x1353f00 .concat [ 4 4 0 0], LS_0x1353f00_0_0, LS_0x1353f00_0_4; +S_0x1067140 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1066ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dd2570/d .functor OR 1, L_0x1dd2050, L_0x1dd2410, C4<0>, C4<0>; -L_0x1dd2570 .delay 1 (30000,30000,30000) L_0x1dd2570/d; -v0x1bd52f0_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers -v0x1bd53b0_0 .net "b", 0 0, L_0x1ddb5d0; alias, 1 drivers -v0x1bd5480_0 .net "c1", 0 0, L_0x1dd2050; 1 drivers -v0x1bd5580_0 .net "c2", 0 0, L_0x1dd2410; 1 drivers -v0x1bd5650_0 .net "carryin", 0 0, L_0x1dd1b40; alias, 1 drivers -v0x1bd5740_0 .net "carryout", 0 0, L_0x1dd2570; 1 drivers -v0x1bd57e0_0 .net "s1", 0 0, L_0x1dd1f90; 1 drivers -v0x1bd58d0_0 .net "sum", 0 0, L_0x1dd22c0; 1 drivers -S_0x1bd4730 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bd44c0; +L_0x1265cb0/d .functor OR 1, L_0x1265790, L_0x1265b50, C4<0>, C4<0>; +L_0x1265cb0 .delay 1 (30000,30000,30000) L_0x1265cb0/d; +v0x1067f70_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers +v0x1068030_0 .net "b", 0 0, L_0x126ed40; alias, 1 drivers +v0x1068100_0 .net "c1", 0 0, L_0x1265790; 1 drivers +v0x1068200_0 .net "c2", 0 0, L_0x1265b50; 1 drivers +v0x10682d0_0 .net "carryin", 0 0, L_0x1265280; alias, 1 drivers +v0x10683c0_0 .net "carryout", 0 0, L_0x1265cb0; 1 drivers +v0x1068460_0 .net "s1", 0 0, L_0x12656d0; 1 drivers +v0x1068550_0 .net "sum", 0 0, L_0x1265a00; 1 drivers +S_0x10673b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1067140; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dd1f90/d .functor XOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; -L_0x1dd1f90 .delay 1 (30000,30000,30000) L_0x1dd1f90/d; -L_0x1dd2050/d .functor AND 1, L_0x1ddb470, L_0x1ddb5d0, C4<1>, C4<1>; -L_0x1dd2050 .delay 1 (30000,30000,30000) L_0x1dd2050/d; -v0x1bd4990_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers -v0x1bd4a70_0 .net "b", 0 0, L_0x1ddb5d0; alias, 1 drivers -v0x1bd4b30_0 .net "carryout", 0 0, L_0x1dd2050; alias, 1 drivers -v0x1bd4bd0_0 .net "sum", 0 0, L_0x1dd1f90; alias, 1 drivers -S_0x1bd4d10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bd44c0; +L_0x12656d0/d .functor XOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; +L_0x12656d0 .delay 1 (30000,30000,30000) L_0x12656d0/d; +L_0x1265790/d .functor AND 1, L_0x126ebe0, L_0x126ed40, C4<1>, C4<1>; +L_0x1265790 .delay 1 (30000,30000,30000) L_0x1265790/d; +v0x1067610_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers +v0x10676f0_0 .net "b", 0 0, L_0x126ed40; alias, 1 drivers +v0x10677b0_0 .net "carryout", 0 0, L_0x1265790; alias, 1 drivers +v0x1067850_0 .net "sum", 0 0, L_0x12656d0; alias, 1 drivers +S_0x1067990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1067140; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dd22c0/d .functor XOR 1, L_0x1dd1f90, L_0x1dd1b40, C4<0>, C4<0>; -L_0x1dd22c0 .delay 1 (30000,30000,30000) L_0x1dd22c0/d; -L_0x1dd2410/d .functor AND 1, L_0x1dd1f90, L_0x1dd1b40, C4<1>, C4<1>; -L_0x1dd2410 .delay 1 (30000,30000,30000) L_0x1dd2410/d; -v0x1bd4f70_0 .net "a", 0 0, L_0x1dd1f90; alias, 1 drivers -v0x1bd5010_0 .net "b", 0 0, L_0x1dd1b40; alias, 1 drivers -v0x1bd50b0_0 .net "carryout", 0 0, L_0x1dd2410; alias, 1 drivers -v0x1bd5180_0 .net "sum", 0 0, L_0x1dd22c0; alias, 1 drivers -S_0x1bd59a0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bd4240; +L_0x1265a00/d .functor XOR 1, L_0x12656d0, L_0x1265280, C4<0>, C4<0>; +L_0x1265a00 .delay 1 (30000,30000,30000) L_0x1265a00/d; +L_0x1265b50/d .functor AND 1, L_0x12656d0, L_0x1265280, C4<1>, C4<1>; +L_0x1265b50 .delay 1 (30000,30000,30000) L_0x1265b50/d; +v0x1067bf0_0 .net "a", 0 0, L_0x12656d0; alias, 1 drivers +v0x1067c90_0 .net "b", 0 0, L_0x1265280; alias, 1 drivers +v0x1067d30_0 .net "carryout", 0 0, L_0x1265b50; alias, 1 drivers +v0x1067e00_0 .net "sum", 0 0, L_0x1265a00; alias, 1 drivers +S_0x1068620 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1066ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bdad90_0 .net "ands", 7 0, L_0x1dd8ff0; 1 drivers -v0x1bdaea0_0 .net "in", 7 0, L_0x1ebfb50; alias, 1 drivers -v0x1bdaf60_0 .net "out", 0 0, L_0x1ddb010; alias, 1 drivers -v0x1bdb030_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bd5bc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bd59a0; +v0x106da10_0 .net "ands", 7 0, L_0x126c780; 1 drivers +v0x106db20_0 .net "in", 7 0, L_0x1353f00; alias, 1 drivers +v0x106dbe0_0 .net "out", 0 0, L_0x126e780; alias, 1 drivers +v0x106dcb0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1068840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1068620; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bd82f0_0 .net "A", 7 0, L_0x1ebfb50; alias, 1 drivers -v0x1bd83f0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bd84b0_0 .net *"_s0", 0 0, L_0x1dd7960; 1 drivers -v0x1bd8570_0 .net *"_s12", 0 0, L_0x1dd82d0; 1 drivers -v0x1bd8650_0 .net *"_s16", 0 0, L_0x1dd8630; 1 drivers -v0x1bd8780_0 .net *"_s20", 0 0, L_0x1dd8940; 1 drivers -v0x1bd8860_0 .net *"_s24", 0 0, L_0x1dd8d30; 1 drivers -v0x1bd8940_0 .net *"_s28", 0 0, L_0x1dd92c0; 1 drivers -v0x1bd8a20_0 .net *"_s4", 0 0, L_0x1dd7c70; 1 drivers -v0x1bd8b90_0 .net *"_s8", 0 0, L_0x1dd7fc0; 1 drivers -v0x1bd8c70_0 .net "out", 7 0, L_0x1dd8ff0; alias, 1 drivers -L_0x1dd7a20 .part L_0x1ebfb50, 0, 1; -L_0x1dd7b80 .part v0x1d6daa0_0, 0, 1; -L_0x1dd7d30 .part L_0x1ebfb50, 1, 1; -L_0x1dd7f20 .part v0x1d6daa0_0, 1, 1; -L_0x1dd8080 .part L_0x1ebfb50, 2, 1; -L_0x1dd81e0 .part v0x1d6daa0_0, 2, 1; -L_0x1dd8390 .part L_0x1ebfb50, 3, 1; -L_0x1dd84f0 .part v0x1d6daa0_0, 3, 1; -L_0x1dd86f0 .part L_0x1ebfb50, 4, 1; -L_0x1dd8850 .part v0x1d6daa0_0, 4, 1; -L_0x1dd89b0 .part L_0x1ebfb50, 5, 1; -L_0x1dd8c20 .part v0x1d6daa0_0, 5, 1; -L_0x1dd8df0 .part L_0x1ebfb50, 6, 1; -L_0x1dd8f50 .part v0x1d6daa0_0, 6, 1; -LS_0x1dd8ff0_0_0 .concat8 [ 1 1 1 1], L_0x1dd7960, L_0x1dd7c70, L_0x1dd7fc0, L_0x1dd82d0; -LS_0x1dd8ff0_0_4 .concat8 [ 1 1 1 1], L_0x1dd8630, L_0x1dd8940, L_0x1dd8d30, L_0x1dd92c0; -L_0x1dd8ff0 .concat8 [ 4 4 0 0], LS_0x1dd8ff0_0_0, LS_0x1dd8ff0_0_4; -L_0x1dd93d0 .part L_0x1ebfb50, 7, 1; -L_0x1dd95c0 .part v0x1d6daa0_0, 7, 1; -S_0x1bd5e20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd6030 .param/l "i" 0 4 54, +C4<00>; -L_0x1dd7960/d .functor AND 1, L_0x1dd7a20, L_0x1dd7b80, C4<1>, C4<1>; -L_0x1dd7960 .delay 1 (30000,30000,30000) L_0x1dd7960/d; -v0x1bd6110_0 .net *"_s0", 0 0, L_0x1dd7a20; 1 drivers -v0x1bd61f0_0 .net *"_s1", 0 0, L_0x1dd7b80; 1 drivers -S_0x1bd62d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd64e0 .param/l "i" 0 4 54, +C4<01>; -L_0x1dd7c70/d .functor AND 1, L_0x1dd7d30, L_0x1dd7f20, C4<1>, C4<1>; -L_0x1dd7c70 .delay 1 (30000,30000,30000) L_0x1dd7c70/d; -v0x1bd65a0_0 .net *"_s0", 0 0, L_0x1dd7d30; 1 drivers -v0x1bd6680_0 .net *"_s1", 0 0, L_0x1dd7f20; 1 drivers -S_0x1bd6760 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd6970 .param/l "i" 0 4 54, +C4<010>; -L_0x1dd7fc0/d .functor AND 1, L_0x1dd8080, L_0x1dd81e0, C4<1>, C4<1>; -L_0x1dd7fc0 .delay 1 (30000,30000,30000) L_0x1dd7fc0/d; -v0x1bd6a10_0 .net *"_s0", 0 0, L_0x1dd8080; 1 drivers -v0x1bd6af0_0 .net *"_s1", 0 0, L_0x1dd81e0; 1 drivers -S_0x1bd6bd0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd6de0 .param/l "i" 0 4 54, +C4<011>; -L_0x1dd82d0/d .functor AND 1, L_0x1dd8390, L_0x1dd84f0, C4<1>, C4<1>; -L_0x1dd82d0 .delay 1 (30000,30000,30000) L_0x1dd82d0/d; -v0x1bd6ea0_0 .net *"_s0", 0 0, L_0x1dd8390; 1 drivers -v0x1bd6f80_0 .net *"_s1", 0 0, L_0x1dd84f0; 1 drivers -S_0x1bd7060 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd72c0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dd8630/d .functor AND 1, L_0x1dd86f0, L_0x1dd8850, C4<1>, C4<1>; -L_0x1dd8630 .delay 1 (30000,30000,30000) L_0x1dd8630/d; -v0x1bd7380_0 .net *"_s0", 0 0, L_0x1dd86f0; 1 drivers -v0x1bd7460_0 .net *"_s1", 0 0, L_0x1dd8850; 1 drivers -S_0x1bd7540 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd7750 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dd8940/d .functor AND 1, L_0x1dd89b0, L_0x1dd8c20, C4<1>, C4<1>; -L_0x1dd8940 .delay 1 (30000,30000,30000) L_0x1dd8940/d; -v0x1bd7810_0 .net *"_s0", 0 0, L_0x1dd89b0; 1 drivers -v0x1bd78f0_0 .net *"_s1", 0 0, L_0x1dd8c20; 1 drivers -S_0x1bd79d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd7be0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dd8d30/d .functor AND 1, L_0x1dd8df0, L_0x1dd8f50, C4<1>, C4<1>; -L_0x1dd8d30 .delay 1 (30000,30000,30000) L_0x1dd8d30/d; -v0x1bd7ca0_0 .net *"_s0", 0 0, L_0x1dd8df0; 1 drivers -v0x1bd7d80_0 .net *"_s1", 0 0, L_0x1dd8f50; 1 drivers -S_0x1bd7e60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bd5bc0; - .timescale -9 -12; -P_0x1bd8070 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dd92c0/d .functor AND 1, L_0x1dd93d0, L_0x1dd95c0, C4<1>, C4<1>; -L_0x1dd92c0 .delay 1 (30000,30000,30000) L_0x1dd92c0/d; -v0x1bd8130_0 .net *"_s0", 0 0, L_0x1dd93d0; 1 drivers -v0x1bd8210_0 .net *"_s1", 0 0, L_0x1dd95c0; 1 drivers -S_0x1bd8dd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bd59a0; +v0x106af70_0 .net "A", 7 0, L_0x1353f00; alias, 1 drivers +v0x106b070_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x106b130_0 .net *"_s0", 0 0, L_0x126b0a0; 1 drivers +v0x106b1f0_0 .net *"_s12", 0 0, L_0x126ba10; 1 drivers +v0x106b2d0_0 .net *"_s16", 0 0, L_0x126bd70; 1 drivers +v0x106b400_0 .net *"_s20", 0 0, L_0x126c080; 1 drivers +v0x106b4e0_0 .net *"_s24", 0 0, L_0x126c470; 1 drivers +v0x106b5c0_0 .net *"_s28", 0 0, L_0x126c400; 1 drivers +v0x106b6a0_0 .net *"_s4", 0 0, L_0x126b3b0; 1 drivers +v0x106b810_0 .net *"_s8", 0 0, L_0x126b700; 1 drivers +v0x106b8f0_0 .net "out", 7 0, L_0x126c780; alias, 1 drivers +L_0x126b160 .part L_0x1353f00, 0, 1; +L_0x126b2c0 .part v0x12010b0_0, 0, 1; +L_0x126b470 .part L_0x1353f00, 1, 1; +L_0x126b660 .part v0x12010b0_0, 1, 1; +L_0x126b7c0 .part L_0x1353f00, 2, 1; +L_0x126b920 .part v0x12010b0_0, 2, 1; +L_0x126bad0 .part L_0x1353f00, 3, 1; +L_0x126bc30 .part v0x12010b0_0, 3, 1; +L_0x126be30 .part L_0x1353f00, 4, 1; +L_0x126bf90 .part v0x12010b0_0, 4, 1; +L_0x126c0f0 .part L_0x1353f00, 5, 1; +L_0x126c360 .part v0x12010b0_0, 5, 1; +L_0x126c530 .part L_0x1353f00, 6, 1; +L_0x126c690 .part v0x12010b0_0, 6, 1; +LS_0x126c780_0_0 .concat8 [ 1 1 1 1], L_0x126b0a0, L_0x126b3b0, L_0x126b700, L_0x126ba10; +LS_0x126c780_0_4 .concat8 [ 1 1 1 1], L_0x126bd70, L_0x126c080, L_0x126c470, L_0x126c400; +L_0x126c780 .concat8 [ 4 4 0 0], LS_0x126c780_0_0, LS_0x126c780_0_4; +L_0x126cb40 .part L_0x1353f00, 7, 1; +L_0x126cd30 .part v0x12010b0_0, 7, 1; +S_0x1068aa0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x1068cb0 .param/l "i" 0 4 54, +C4<00>; +L_0x126b0a0/d .functor AND 1, L_0x126b160, L_0x126b2c0, C4<1>, C4<1>; +L_0x126b0a0 .delay 1 (30000,30000,30000) L_0x126b0a0/d; +v0x1068d90_0 .net *"_s0", 0 0, L_0x126b160; 1 drivers +v0x1068e70_0 .net *"_s1", 0 0, L_0x126b2c0; 1 drivers +S_0x1068f50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x1069160 .param/l "i" 0 4 54, +C4<01>; +L_0x126b3b0/d .functor AND 1, L_0x126b470, L_0x126b660, C4<1>, C4<1>; +L_0x126b3b0 .delay 1 (30000,30000,30000) L_0x126b3b0/d; +v0x1069220_0 .net *"_s0", 0 0, L_0x126b470; 1 drivers +v0x1069300_0 .net *"_s1", 0 0, L_0x126b660; 1 drivers +S_0x10693e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x10695f0 .param/l "i" 0 4 54, +C4<010>; +L_0x126b700/d .functor AND 1, L_0x126b7c0, L_0x126b920, C4<1>, C4<1>; +L_0x126b700 .delay 1 (30000,30000,30000) L_0x126b700/d; +v0x1069690_0 .net *"_s0", 0 0, L_0x126b7c0; 1 drivers +v0x1069770_0 .net *"_s1", 0 0, L_0x126b920; 1 drivers +S_0x1069850 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x1069a60 .param/l "i" 0 4 54, +C4<011>; +L_0x126ba10/d .functor AND 1, L_0x126bad0, L_0x126bc30, C4<1>, C4<1>; +L_0x126ba10 .delay 1 (30000,30000,30000) L_0x126ba10/d; +v0x1069b20_0 .net *"_s0", 0 0, L_0x126bad0; 1 drivers +v0x1069c00_0 .net *"_s1", 0 0, L_0x126bc30; 1 drivers +S_0x1069ce0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x1069f40 .param/l "i" 0 4 54, +C4<0100>; +L_0x126bd70/d .functor AND 1, L_0x126be30, L_0x126bf90, C4<1>, C4<1>; +L_0x126bd70 .delay 1 (30000,30000,30000) L_0x126bd70/d; +v0x106a000_0 .net *"_s0", 0 0, L_0x126be30; 1 drivers +v0x106a0e0_0 .net *"_s1", 0 0, L_0x126bf90; 1 drivers +S_0x106a1c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x106a3d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x126c080/d .functor AND 1, L_0x126c0f0, L_0x126c360, C4<1>, C4<1>; +L_0x126c080 .delay 1 (30000,30000,30000) L_0x126c080/d; +v0x106a490_0 .net *"_s0", 0 0, L_0x126c0f0; 1 drivers +v0x106a570_0 .net *"_s1", 0 0, L_0x126c360; 1 drivers +S_0x106a650 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x106a860 .param/l "i" 0 4 54, +C4<0110>; +L_0x126c470/d .functor AND 1, L_0x126c530, L_0x126c690, C4<1>, C4<1>; +L_0x126c470 .delay 1 (30000,30000,30000) L_0x126c470/d; +v0x106a920_0 .net *"_s0", 0 0, L_0x126c530; 1 drivers +v0x106aa00_0 .net *"_s1", 0 0, L_0x126c690; 1 drivers +S_0x106aae0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1068840; + .timescale -9 -12; +P_0x106acf0 .param/l "i" 0 4 54, +C4<0111>; +L_0x126c400/d .functor AND 1, L_0x126cb40, L_0x126cd30, C4<1>, C4<1>; +L_0x126c400 .delay 1 (30000,30000,30000) L_0x126c400/d; +v0x106adb0_0 .net *"_s0", 0 0, L_0x126cb40; 1 drivers +v0x106ae90_0 .net *"_s1", 0 0, L_0x126cd30; 1 drivers +S_0x106ba50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1068620; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1ddb010/d .functor OR 1, L_0x1ddb0d0, L_0x1ddb280, C4<0>, C4<0>; -L_0x1ddb010 .delay 1 (30000,30000,30000) L_0x1ddb010/d; -v0x1bda920_0 .net *"_s10", 0 0, L_0x1ddb0d0; 1 drivers -v0x1bdaa00_0 .net *"_s12", 0 0, L_0x1ddb280; 1 drivers -v0x1bdaae0_0 .net "in", 7 0, L_0x1dd8ff0; alias, 1 drivers -v0x1bdabb0_0 .net "ors", 1 0, L_0x1ddae30; 1 drivers -v0x1bdac70_0 .net "out", 0 0, L_0x1ddb010; alias, 1 drivers -L_0x1dda200 .part L_0x1dd8ff0, 0, 4; -L_0x1ddae30 .concat8 [ 1 1 0 0], L_0x1dd9ef0, L_0x1ddab20; -L_0x1ddaf70 .part L_0x1dd8ff0, 4, 4; -L_0x1ddb0d0 .part L_0x1ddae30, 0, 1; -L_0x1ddb280 .part L_0x1ddae30, 1, 1; -S_0x1bd8f90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bd8dd0; +L_0x126e780/d .functor OR 1, L_0x126e840, L_0x126e9f0, C4<0>, C4<0>; +L_0x126e780 .delay 1 (30000,30000,30000) L_0x126e780/d; +v0x106d5a0_0 .net *"_s10", 0 0, L_0x126e840; 1 drivers +v0x106d680_0 .net *"_s12", 0 0, L_0x126e9f0; 1 drivers +v0x106d760_0 .net "in", 7 0, L_0x126c780; alias, 1 drivers +v0x106d830_0 .net "ors", 1 0, L_0x126e5a0; 1 drivers +v0x106d8f0_0 .net "out", 0 0, L_0x126e780; alias, 1 drivers +L_0x126d970 .part L_0x126c780, 0, 4; +L_0x126e5a0 .concat8 [ 1 1 0 0], L_0x126d660, L_0x126e290; +L_0x126e6e0 .part L_0x126c780, 4, 4; +L_0x126e840 .part L_0x126e5a0, 0, 1; +L_0x126e9f0 .part L_0x126e5a0, 1, 1; +S_0x106bc10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x106ba50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dd96b0/d .functor OR 1, L_0x1dd9770, L_0x1dd98d0, C4<0>, C4<0>; -L_0x1dd96b0 .delay 1 (30000,30000,30000) L_0x1dd96b0/d; -L_0x1dd9b00/d .functor OR 1, L_0x1dd9c10, L_0x1dd9d70, C4<0>, C4<0>; -L_0x1dd9b00 .delay 1 (30000,30000,30000) L_0x1dd9b00/d; -L_0x1dd9ef0/d .functor OR 1, L_0x1dd9f60, L_0x1dda110, C4<0>, C4<0>; -L_0x1dd9ef0 .delay 1 (30000,30000,30000) L_0x1dd9ef0/d; -v0x1bd91e0_0 .net *"_s0", 0 0, L_0x1dd96b0; 1 drivers -v0x1bd92e0_0 .net *"_s10", 0 0, L_0x1dd9c10; 1 drivers -v0x1bd93c0_0 .net *"_s12", 0 0, L_0x1dd9d70; 1 drivers -v0x1bd9480_0 .net *"_s14", 0 0, L_0x1dd9f60; 1 drivers -v0x1bd9560_0 .net *"_s16", 0 0, L_0x1dda110; 1 drivers -v0x1bd9690_0 .net *"_s3", 0 0, L_0x1dd9770; 1 drivers -v0x1bd9770_0 .net *"_s5", 0 0, L_0x1dd98d0; 1 drivers -v0x1bd9850_0 .net *"_s6", 0 0, L_0x1dd9b00; 1 drivers -v0x1bd9930_0 .net "in", 3 0, L_0x1dda200; 1 drivers -v0x1bd9aa0_0 .net "ors", 1 0, L_0x1dd9a10; 1 drivers -v0x1bd9b80_0 .net "out", 0 0, L_0x1dd9ef0; 1 drivers -L_0x1dd9770 .part L_0x1dda200, 0, 1; -L_0x1dd98d0 .part L_0x1dda200, 1, 1; -L_0x1dd9a10 .concat8 [ 1 1 0 0], L_0x1dd96b0, L_0x1dd9b00; -L_0x1dd9c10 .part L_0x1dda200, 2, 1; -L_0x1dd9d70 .part L_0x1dda200, 3, 1; -L_0x1dd9f60 .part L_0x1dd9a10, 0, 1; -L_0x1dda110 .part L_0x1dd9a10, 1, 1; -S_0x1bd9ca0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bd8dd0; +L_0x126ce20/d .functor OR 1, L_0x126cee0, L_0x126d040, C4<0>, C4<0>; +L_0x126ce20 .delay 1 (30000,30000,30000) L_0x126ce20/d; +L_0x126d270/d .functor OR 1, L_0x126d380, L_0x126d4e0, C4<0>, C4<0>; +L_0x126d270 .delay 1 (30000,30000,30000) L_0x126d270/d; +L_0x126d660/d .functor OR 1, L_0x126d6d0, L_0x126d880, C4<0>, C4<0>; +L_0x126d660 .delay 1 (30000,30000,30000) L_0x126d660/d; +v0x106be60_0 .net *"_s0", 0 0, L_0x126ce20; 1 drivers +v0x106bf60_0 .net *"_s10", 0 0, L_0x126d380; 1 drivers +v0x106c040_0 .net *"_s12", 0 0, L_0x126d4e0; 1 drivers +v0x106c100_0 .net *"_s14", 0 0, L_0x126d6d0; 1 drivers +v0x106c1e0_0 .net *"_s16", 0 0, L_0x126d880; 1 drivers +v0x106c310_0 .net *"_s3", 0 0, L_0x126cee0; 1 drivers +v0x106c3f0_0 .net *"_s5", 0 0, L_0x126d040; 1 drivers +v0x106c4d0_0 .net *"_s6", 0 0, L_0x126d270; 1 drivers +v0x106c5b0_0 .net "in", 3 0, L_0x126d970; 1 drivers +v0x106c720_0 .net "ors", 1 0, L_0x126d180; 1 drivers +v0x106c800_0 .net "out", 0 0, L_0x126d660; 1 drivers +L_0x126cee0 .part L_0x126d970, 0, 1; +L_0x126d040 .part L_0x126d970, 1, 1; +L_0x126d180 .concat8 [ 1 1 0 0], L_0x126ce20, L_0x126d270; +L_0x126d380 .part L_0x126d970, 2, 1; +L_0x126d4e0 .part L_0x126d970, 3, 1; +L_0x126d6d0 .part L_0x126d180, 0, 1; +L_0x126d880 .part L_0x126d180, 1, 1; +S_0x106c920 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x106ba50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dda330/d .functor OR 1, L_0x1dda3a0, L_0x1dda500, C4<0>, C4<0>; -L_0x1dda330 .delay 1 (30000,30000,30000) L_0x1dda330/d; -L_0x1dda730/d .functor OR 1, L_0x1dda840, L_0x1dda9a0, C4<0>, C4<0>; -L_0x1dda730 .delay 1 (30000,30000,30000) L_0x1dda730/d; -L_0x1ddab20/d .functor OR 1, L_0x1ddab90, L_0x1ddad40, C4<0>, C4<0>; -L_0x1ddab20 .delay 1 (30000,30000,30000) L_0x1ddab20/d; -v0x1bd9e60_0 .net *"_s0", 0 0, L_0x1dda330; 1 drivers -v0x1bd9f60_0 .net *"_s10", 0 0, L_0x1dda840; 1 drivers -v0x1bda040_0 .net *"_s12", 0 0, L_0x1dda9a0; 1 drivers -v0x1bda100_0 .net *"_s14", 0 0, L_0x1ddab90; 1 drivers -v0x1bda1e0_0 .net *"_s16", 0 0, L_0x1ddad40; 1 drivers -v0x1bda310_0 .net *"_s3", 0 0, L_0x1dda3a0; 1 drivers -v0x1bda3f0_0 .net *"_s5", 0 0, L_0x1dda500; 1 drivers -v0x1bda4d0_0 .net *"_s6", 0 0, L_0x1dda730; 1 drivers -v0x1bda5b0_0 .net "in", 3 0, L_0x1ddaf70; 1 drivers -v0x1bda720_0 .net "ors", 1 0, L_0x1dda640; 1 drivers -v0x1bda800_0 .net "out", 0 0, L_0x1ddab20; 1 drivers -L_0x1dda3a0 .part L_0x1ddaf70, 0, 1; -L_0x1dda500 .part L_0x1ddaf70, 1, 1; -L_0x1dda640 .concat8 [ 1 1 0 0], L_0x1dda330, L_0x1dda730; -L_0x1dda840 .part L_0x1ddaf70, 2, 1; -L_0x1dda9a0 .part L_0x1ddaf70, 3, 1; -L_0x1ddab90 .part L_0x1dda640, 0, 1; -L_0x1ddad40 .part L_0x1dda640, 1, 1; -S_0x1bdb110 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bd4240; +L_0x126daa0/d .functor OR 1, L_0x126db10, L_0x126dc70, C4<0>, C4<0>; +L_0x126daa0 .delay 1 (30000,30000,30000) L_0x126daa0/d; +L_0x126dea0/d .functor OR 1, L_0x126dfb0, L_0x126e110, C4<0>, C4<0>; +L_0x126dea0 .delay 1 (30000,30000,30000) L_0x126dea0/d; +L_0x126e290/d .functor OR 1, L_0x126e300, L_0x126e4b0, C4<0>, C4<0>; +L_0x126e290 .delay 1 (30000,30000,30000) L_0x126e290/d; +v0x106cae0_0 .net *"_s0", 0 0, L_0x126daa0; 1 drivers +v0x106cbe0_0 .net *"_s10", 0 0, L_0x126dfb0; 1 drivers +v0x106ccc0_0 .net *"_s12", 0 0, L_0x126e110; 1 drivers +v0x106cd80_0 .net *"_s14", 0 0, L_0x126e300; 1 drivers +v0x106ce60_0 .net *"_s16", 0 0, L_0x126e4b0; 1 drivers +v0x106cf90_0 .net *"_s3", 0 0, L_0x126db10; 1 drivers +v0x106d070_0 .net *"_s5", 0 0, L_0x126dc70; 1 drivers +v0x106d150_0 .net *"_s6", 0 0, L_0x126dea0; 1 drivers +v0x106d230_0 .net "in", 3 0, L_0x126e6e0; 1 drivers +v0x106d3a0_0 .net "ors", 1 0, L_0x126ddb0; 1 drivers +v0x106d480_0 .net "out", 0 0, L_0x126e290; 1 drivers +L_0x126db10 .part L_0x126e6e0, 0, 1; +L_0x126dc70 .part L_0x126e6e0, 1, 1; +L_0x126ddb0 .concat8 [ 1 1 0 0], L_0x126daa0, L_0x126dea0; +L_0x126dfb0 .part L_0x126e6e0, 2, 1; +L_0x126e110 .part L_0x126e6e0, 3, 1; +L_0x126e300 .part L_0x126ddb0, 0, 1; +L_0x126e4b0 .part L_0x126ddb0, 1, 1; +S_0x106dd90 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1066ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1be0540_0 .net "ands", 7 0, L_0x1dd5600; 1 drivers -v0x1be0650_0 .net "in", 7 0, L_0x1dd3b40; alias, 1 drivers -v0x1be0710_0 .net "out", 0 0, L_0x1dd7600; alias, 1 drivers -v0x1be07e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bdb360 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bdb110; +v0x10731c0_0 .net "ands", 7 0, L_0x1268d40; 1 drivers +v0x10732d0_0 .net "in", 7 0, L_0x1267280; alias, 1 drivers +v0x1073390_0 .net "out", 0 0, L_0x126ad40; alias, 1 drivers +v0x1073460_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x106dfe0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x106dd90; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bddaa0_0 .net "A", 7 0, L_0x1dd3b40; alias, 1 drivers -v0x1bddba0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bddc60_0 .net *"_s0", 0 0, L_0x1dd3ed0; 1 drivers -v0x1bddd20_0 .net *"_s12", 0 0, L_0x1dd4890; 1 drivers -v0x1bdde00_0 .net *"_s16", 0 0, L_0x1dd4bf0; 1 drivers -v0x1bddf30_0 .net *"_s20", 0 0, L_0x1dd4fc0; 1 drivers -v0x1bde010_0 .net *"_s24", 0 0, L_0x1dd52f0; 1 drivers -v0x1bde0f0_0 .net *"_s28", 0 0, L_0x1dd5280; 1 drivers -v0x1bde1d0_0 .net *"_s4", 0 0, L_0x1dd4270; 1 drivers -v0x1bde340_0 .net *"_s8", 0 0, L_0x1dd4580; 1 drivers -v0x1bde420_0 .net "out", 7 0, L_0x1dd5600; alias, 1 drivers -L_0x1dd3fe0 .part L_0x1dd3b40, 0, 1; -L_0x1dd41d0 .part v0x1d6daa0_0, 0, 1; -L_0x1dd4330 .part L_0x1dd3b40, 1, 1; -L_0x1dd4490 .part v0x1d6daa0_0, 1, 1; -L_0x1dd4640 .part L_0x1dd3b40, 2, 1; -L_0x1dd47a0 .part v0x1d6daa0_0, 2, 1; -L_0x1dd4950 .part L_0x1dd3b40, 3, 1; -L_0x1dd4ab0 .part v0x1d6daa0_0, 3, 1; -L_0x1dd4cb0 .part L_0x1dd3b40, 4, 1; -L_0x1dd4f20 .part v0x1d6daa0_0, 4, 1; -L_0x1dd5030 .part L_0x1dd3b40, 5, 1; -L_0x1dd5190 .part v0x1d6daa0_0, 5, 1; -L_0x1dd53b0 .part L_0x1dd3b40, 6, 1; -L_0x1dd5510 .part v0x1d6daa0_0, 6, 1; -LS_0x1dd5600_0_0 .concat8 [ 1 1 1 1], L_0x1dd3ed0, L_0x1dd4270, L_0x1dd4580, L_0x1dd4890; -LS_0x1dd5600_0_4 .concat8 [ 1 1 1 1], L_0x1dd4bf0, L_0x1dd4fc0, L_0x1dd52f0, L_0x1dd5280; -L_0x1dd5600 .concat8 [ 4 4 0 0], LS_0x1dd5600_0_0, LS_0x1dd5600_0_4; -L_0x1dd59c0 .part L_0x1dd3b40, 7, 1; -L_0x1dd5bb0 .part v0x1d6daa0_0, 7, 1; -S_0x1bdb5a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdb7b0 .param/l "i" 0 4 54, +C4<00>; -L_0x1dd3ed0/d .functor AND 1, L_0x1dd3fe0, L_0x1dd41d0, C4<1>, C4<1>; -L_0x1dd3ed0 .delay 1 (30000,30000,30000) L_0x1dd3ed0/d; -v0x1bdb890_0 .net *"_s0", 0 0, L_0x1dd3fe0; 1 drivers -v0x1bdb970_0 .net *"_s1", 0 0, L_0x1dd41d0; 1 drivers -S_0x1bdba50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdbc60 .param/l "i" 0 4 54, +C4<01>; -L_0x1dd4270/d .functor AND 1, L_0x1dd4330, L_0x1dd4490, C4<1>, C4<1>; -L_0x1dd4270 .delay 1 (30000,30000,30000) L_0x1dd4270/d; -v0x1bdbd20_0 .net *"_s0", 0 0, L_0x1dd4330; 1 drivers -v0x1bdbe00_0 .net *"_s1", 0 0, L_0x1dd4490; 1 drivers -S_0x1bdbee0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdc120 .param/l "i" 0 4 54, +C4<010>; -L_0x1dd4580/d .functor AND 1, L_0x1dd4640, L_0x1dd47a0, C4<1>, C4<1>; -L_0x1dd4580 .delay 1 (30000,30000,30000) L_0x1dd4580/d; -v0x1bdc1c0_0 .net *"_s0", 0 0, L_0x1dd4640; 1 drivers -v0x1bdc2a0_0 .net *"_s1", 0 0, L_0x1dd47a0; 1 drivers -S_0x1bdc380 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdc590 .param/l "i" 0 4 54, +C4<011>; -L_0x1dd4890/d .functor AND 1, L_0x1dd4950, L_0x1dd4ab0, C4<1>, C4<1>; -L_0x1dd4890 .delay 1 (30000,30000,30000) L_0x1dd4890/d; -v0x1bdc650_0 .net *"_s0", 0 0, L_0x1dd4950; 1 drivers -v0x1bdc730_0 .net *"_s1", 0 0, L_0x1dd4ab0; 1 drivers -S_0x1bdc810 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdca70 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dd4bf0/d .functor AND 1, L_0x1dd4cb0, L_0x1dd4f20, C4<1>, C4<1>; -L_0x1dd4bf0 .delay 1 (30000,30000,30000) L_0x1dd4bf0/d; -v0x1bdcb30_0 .net *"_s0", 0 0, L_0x1dd4cb0; 1 drivers -v0x1bdcc10_0 .net *"_s1", 0 0, L_0x1dd4f20; 1 drivers -S_0x1bdccf0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdcf00 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dd4fc0/d .functor AND 1, L_0x1dd5030, L_0x1dd5190, C4<1>, C4<1>; -L_0x1dd4fc0 .delay 1 (30000,30000,30000) L_0x1dd4fc0/d; -v0x1bdcfc0_0 .net *"_s0", 0 0, L_0x1dd5030; 1 drivers -v0x1bdd0a0_0 .net *"_s1", 0 0, L_0x1dd5190; 1 drivers -S_0x1bdd180 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdd390 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dd52f0/d .functor AND 1, L_0x1dd53b0, L_0x1dd5510, C4<1>, C4<1>; -L_0x1dd52f0 .delay 1 (30000,30000,30000) L_0x1dd52f0/d; -v0x1bdd450_0 .net *"_s0", 0 0, L_0x1dd53b0; 1 drivers -v0x1bdd530_0 .net *"_s1", 0 0, L_0x1dd5510; 1 drivers -S_0x1bdd610 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bdb360; - .timescale -9 -12; -P_0x1bdd820 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dd5280/d .functor AND 1, L_0x1dd59c0, L_0x1dd5bb0, C4<1>, C4<1>; -L_0x1dd5280 .delay 1 (30000,30000,30000) L_0x1dd5280/d; -v0x1bdd8e0_0 .net *"_s0", 0 0, L_0x1dd59c0; 1 drivers -v0x1bdd9c0_0 .net *"_s1", 0 0, L_0x1dd5bb0; 1 drivers -S_0x1bde580 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bdb110; +v0x1070720_0 .net "A", 7 0, L_0x1267280; alias, 1 drivers +v0x1070820_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10708e0_0 .net *"_s0", 0 0, L_0x1267610; 1 drivers +v0x10709a0_0 .net *"_s12", 0 0, L_0x1267fd0; 1 drivers +v0x1070a80_0 .net *"_s16", 0 0, L_0x1268330; 1 drivers +v0x1070bb0_0 .net *"_s20", 0 0, L_0x1268700; 1 drivers +v0x1070c90_0 .net *"_s24", 0 0, L_0x1268a30; 1 drivers +v0x1070d70_0 .net *"_s28", 0 0, L_0x12689c0; 1 drivers +v0x1070e50_0 .net *"_s4", 0 0, L_0x12679b0; 1 drivers +v0x1070fc0_0 .net *"_s8", 0 0, L_0x1267cc0; 1 drivers +v0x10710a0_0 .net "out", 7 0, L_0x1268d40; alias, 1 drivers +L_0x1267720 .part L_0x1267280, 0, 1; +L_0x1267910 .part v0x12010b0_0, 0, 1; +L_0x1267a70 .part L_0x1267280, 1, 1; +L_0x1267bd0 .part v0x12010b0_0, 1, 1; +L_0x1267d80 .part L_0x1267280, 2, 1; +L_0x1267ee0 .part v0x12010b0_0, 2, 1; +L_0x1268090 .part L_0x1267280, 3, 1; +L_0x12681f0 .part v0x12010b0_0, 3, 1; +L_0x12683f0 .part L_0x1267280, 4, 1; +L_0x1268660 .part v0x12010b0_0, 4, 1; +L_0x1268770 .part L_0x1267280, 5, 1; +L_0x12688d0 .part v0x12010b0_0, 5, 1; +L_0x1268af0 .part L_0x1267280, 6, 1; +L_0x1268c50 .part v0x12010b0_0, 6, 1; +LS_0x1268d40_0_0 .concat8 [ 1 1 1 1], L_0x1267610, L_0x12679b0, L_0x1267cc0, L_0x1267fd0; +LS_0x1268d40_0_4 .concat8 [ 1 1 1 1], L_0x1268330, L_0x1268700, L_0x1268a30, L_0x12689c0; +L_0x1268d40 .concat8 [ 4 4 0 0], LS_0x1268d40_0_0, LS_0x1268d40_0_4; +L_0x1269100 .part L_0x1267280, 7, 1; +L_0x12692f0 .part v0x12010b0_0, 7, 1; +S_0x106e220 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x106e430 .param/l "i" 0 4 54, +C4<00>; +L_0x1267610/d .functor AND 1, L_0x1267720, L_0x1267910, C4<1>, C4<1>; +L_0x1267610 .delay 1 (30000,30000,30000) L_0x1267610/d; +v0x106e510_0 .net *"_s0", 0 0, L_0x1267720; 1 drivers +v0x106e5f0_0 .net *"_s1", 0 0, L_0x1267910; 1 drivers +S_0x106e6d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x106e8e0 .param/l "i" 0 4 54, +C4<01>; +L_0x12679b0/d .functor AND 1, L_0x1267a70, L_0x1267bd0, C4<1>, C4<1>; +L_0x12679b0 .delay 1 (30000,30000,30000) L_0x12679b0/d; +v0x106e9a0_0 .net *"_s0", 0 0, L_0x1267a70; 1 drivers +v0x106ea80_0 .net *"_s1", 0 0, L_0x1267bd0; 1 drivers +S_0x106eb60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x106eda0 .param/l "i" 0 4 54, +C4<010>; +L_0x1267cc0/d .functor AND 1, L_0x1267d80, L_0x1267ee0, C4<1>, C4<1>; +L_0x1267cc0 .delay 1 (30000,30000,30000) L_0x1267cc0/d; +v0x106ee40_0 .net *"_s0", 0 0, L_0x1267d80; 1 drivers +v0x106ef20_0 .net *"_s1", 0 0, L_0x1267ee0; 1 drivers +S_0x106f000 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x106f210 .param/l "i" 0 4 54, +C4<011>; +L_0x1267fd0/d .functor AND 1, L_0x1268090, L_0x12681f0, C4<1>, C4<1>; +L_0x1267fd0 .delay 1 (30000,30000,30000) L_0x1267fd0/d; +v0x106f2d0_0 .net *"_s0", 0 0, L_0x1268090; 1 drivers +v0x106f3b0_0 .net *"_s1", 0 0, L_0x12681f0; 1 drivers +S_0x106f490 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x106f6f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1268330/d .functor AND 1, L_0x12683f0, L_0x1268660, C4<1>, C4<1>; +L_0x1268330 .delay 1 (30000,30000,30000) L_0x1268330/d; +v0x106f7b0_0 .net *"_s0", 0 0, L_0x12683f0; 1 drivers +v0x106f890_0 .net *"_s1", 0 0, L_0x1268660; 1 drivers +S_0x106f970 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x106fb80 .param/l "i" 0 4 54, +C4<0101>; +L_0x1268700/d .functor AND 1, L_0x1268770, L_0x12688d0, C4<1>, C4<1>; +L_0x1268700 .delay 1 (30000,30000,30000) L_0x1268700/d; +v0x106fc40_0 .net *"_s0", 0 0, L_0x1268770; 1 drivers +v0x106fd20_0 .net *"_s1", 0 0, L_0x12688d0; 1 drivers +S_0x106fe00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x1070010 .param/l "i" 0 4 54, +C4<0110>; +L_0x1268a30/d .functor AND 1, L_0x1268af0, L_0x1268c50, C4<1>, C4<1>; +L_0x1268a30 .delay 1 (30000,30000,30000) L_0x1268a30/d; +v0x10700d0_0 .net *"_s0", 0 0, L_0x1268af0; 1 drivers +v0x10701b0_0 .net *"_s1", 0 0, L_0x1268c50; 1 drivers +S_0x1070290 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x106dfe0; + .timescale -9 -12; +P_0x10704a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12689c0/d .functor AND 1, L_0x1269100, L_0x12692f0, C4<1>, C4<1>; +L_0x12689c0 .delay 1 (30000,30000,30000) L_0x12689c0/d; +v0x1070560_0 .net *"_s0", 0 0, L_0x1269100; 1 drivers +v0x1070640_0 .net *"_s1", 0 0, L_0x12692f0; 1 drivers +S_0x1071200 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x106dd90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dd7600/d .functor OR 1, L_0x1dd76c0, L_0x1dd7870, C4<0>, C4<0>; -L_0x1dd7600 .delay 1 (30000,30000,30000) L_0x1dd7600/d; -v0x1be00d0_0 .net *"_s10", 0 0, L_0x1dd76c0; 1 drivers -v0x1be01b0_0 .net *"_s12", 0 0, L_0x1dd7870; 1 drivers -v0x1be0290_0 .net "in", 7 0, L_0x1dd5600; alias, 1 drivers -v0x1be0360_0 .net "ors", 1 0, L_0x1dd7420; 1 drivers -v0x1be0420_0 .net "out", 0 0, L_0x1dd7600; alias, 1 drivers -L_0x1dd67f0 .part L_0x1dd5600, 0, 4; -L_0x1dd7420 .concat8 [ 1 1 0 0], L_0x1dd64e0, L_0x1dd7110; -L_0x1dd7560 .part L_0x1dd5600, 4, 4; -L_0x1dd76c0 .part L_0x1dd7420, 0, 1; -L_0x1dd7870 .part L_0x1dd7420, 1, 1; -S_0x1bde740 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bde580; +L_0x126ad40/d .functor OR 1, L_0x126ae00, L_0x126afb0, C4<0>, C4<0>; +L_0x126ad40 .delay 1 (30000,30000,30000) L_0x126ad40/d; +v0x1072d50_0 .net *"_s10", 0 0, L_0x126ae00; 1 drivers +v0x1072e30_0 .net *"_s12", 0 0, L_0x126afb0; 1 drivers +v0x1072f10_0 .net "in", 7 0, L_0x1268d40; alias, 1 drivers +v0x1072fe0_0 .net "ors", 1 0, L_0x126ab60; 1 drivers +v0x10730a0_0 .net "out", 0 0, L_0x126ad40; alias, 1 drivers +L_0x1269f30 .part L_0x1268d40, 0, 4; +L_0x126ab60 .concat8 [ 1 1 0 0], L_0x1269c20, L_0x126a850; +L_0x126aca0 .part L_0x1268d40, 4, 4; +L_0x126ae00 .part L_0x126ab60, 0, 1; +L_0x126afb0 .part L_0x126ab60, 1, 1; +S_0x10713c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1071200; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dd5ca0/d .functor OR 1, L_0x1dd5d60, L_0x1dd5ec0, C4<0>, C4<0>; -L_0x1dd5ca0 .delay 1 (30000,30000,30000) L_0x1dd5ca0/d; -L_0x1dd60f0/d .functor OR 1, L_0x1dd6200, L_0x1dd6360, C4<0>, C4<0>; -L_0x1dd60f0 .delay 1 (30000,30000,30000) L_0x1dd60f0/d; -L_0x1dd64e0/d .functor OR 1, L_0x1dd6550, L_0x1dd6700, C4<0>, C4<0>; -L_0x1dd64e0 .delay 1 (30000,30000,30000) L_0x1dd64e0/d; -v0x1bde990_0 .net *"_s0", 0 0, L_0x1dd5ca0; 1 drivers -v0x1bdea90_0 .net *"_s10", 0 0, L_0x1dd6200; 1 drivers -v0x1bdeb70_0 .net *"_s12", 0 0, L_0x1dd6360; 1 drivers -v0x1bdec30_0 .net *"_s14", 0 0, L_0x1dd6550; 1 drivers -v0x1bded10_0 .net *"_s16", 0 0, L_0x1dd6700; 1 drivers -v0x1bdee40_0 .net *"_s3", 0 0, L_0x1dd5d60; 1 drivers -v0x1bdef20_0 .net *"_s5", 0 0, L_0x1dd5ec0; 1 drivers -v0x1bdf000_0 .net *"_s6", 0 0, L_0x1dd60f0; 1 drivers -v0x1bdf0e0_0 .net "in", 3 0, L_0x1dd67f0; 1 drivers -v0x1bdf250_0 .net "ors", 1 0, L_0x1dd6000; 1 drivers -v0x1bdf330_0 .net "out", 0 0, L_0x1dd64e0; 1 drivers -L_0x1dd5d60 .part L_0x1dd67f0, 0, 1; -L_0x1dd5ec0 .part L_0x1dd67f0, 1, 1; -L_0x1dd6000 .concat8 [ 1 1 0 0], L_0x1dd5ca0, L_0x1dd60f0; -L_0x1dd6200 .part L_0x1dd67f0, 2, 1; -L_0x1dd6360 .part L_0x1dd67f0, 3, 1; -L_0x1dd6550 .part L_0x1dd6000, 0, 1; -L_0x1dd6700 .part L_0x1dd6000, 1, 1; -S_0x1bdf450 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bde580; +L_0x12693e0/d .functor OR 1, L_0x12694a0, L_0x1269600, C4<0>, C4<0>; +L_0x12693e0 .delay 1 (30000,30000,30000) L_0x12693e0/d; +L_0x1269830/d .functor OR 1, L_0x1269940, L_0x1269aa0, C4<0>, C4<0>; +L_0x1269830 .delay 1 (30000,30000,30000) L_0x1269830/d; +L_0x1269c20/d .functor OR 1, L_0x1269c90, L_0x1269e40, C4<0>, C4<0>; +L_0x1269c20 .delay 1 (30000,30000,30000) L_0x1269c20/d; +v0x1071610_0 .net *"_s0", 0 0, L_0x12693e0; 1 drivers +v0x1071710_0 .net *"_s10", 0 0, L_0x1269940; 1 drivers +v0x10717f0_0 .net *"_s12", 0 0, L_0x1269aa0; 1 drivers +v0x10718b0_0 .net *"_s14", 0 0, L_0x1269c90; 1 drivers +v0x1071990_0 .net *"_s16", 0 0, L_0x1269e40; 1 drivers +v0x1071ac0_0 .net *"_s3", 0 0, L_0x12694a0; 1 drivers +v0x1071ba0_0 .net *"_s5", 0 0, L_0x1269600; 1 drivers +v0x1071c80_0 .net *"_s6", 0 0, L_0x1269830; 1 drivers +v0x1071d60_0 .net "in", 3 0, L_0x1269f30; 1 drivers +v0x1071ed0_0 .net "ors", 1 0, L_0x1269740; 1 drivers +v0x1071fb0_0 .net "out", 0 0, L_0x1269c20; 1 drivers +L_0x12694a0 .part L_0x1269f30, 0, 1; +L_0x1269600 .part L_0x1269f30, 1, 1; +L_0x1269740 .concat8 [ 1 1 0 0], L_0x12693e0, L_0x1269830; +L_0x1269940 .part L_0x1269f30, 2, 1; +L_0x1269aa0 .part L_0x1269f30, 3, 1; +L_0x1269c90 .part L_0x1269740, 0, 1; +L_0x1269e40 .part L_0x1269740, 1, 1; +S_0x10720d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1071200; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dd6920/d .functor OR 1, L_0x1dd6990, L_0x1dd6af0, C4<0>, C4<0>; -L_0x1dd6920 .delay 1 (30000,30000,30000) L_0x1dd6920/d; -L_0x1dd6d20/d .functor OR 1, L_0x1dd6e30, L_0x1dd6f90, C4<0>, C4<0>; -L_0x1dd6d20 .delay 1 (30000,30000,30000) L_0x1dd6d20/d; -L_0x1dd7110/d .functor OR 1, L_0x1dd7180, L_0x1dd7330, C4<0>, C4<0>; -L_0x1dd7110 .delay 1 (30000,30000,30000) L_0x1dd7110/d; -v0x1bdf610_0 .net *"_s0", 0 0, L_0x1dd6920; 1 drivers -v0x1bdf710_0 .net *"_s10", 0 0, L_0x1dd6e30; 1 drivers -v0x1bdf7f0_0 .net *"_s12", 0 0, L_0x1dd6f90; 1 drivers -v0x1bdf8b0_0 .net *"_s14", 0 0, L_0x1dd7180; 1 drivers -v0x1bdf990_0 .net *"_s16", 0 0, L_0x1dd7330; 1 drivers -v0x1bdfac0_0 .net *"_s3", 0 0, L_0x1dd6990; 1 drivers -v0x1bdfba0_0 .net *"_s5", 0 0, L_0x1dd6af0; 1 drivers -v0x1bdfc80_0 .net *"_s6", 0 0, L_0x1dd6d20; 1 drivers -v0x1bdfd60_0 .net "in", 3 0, L_0x1dd7560; 1 drivers -v0x1bdfed0_0 .net "ors", 1 0, L_0x1dd6c30; 1 drivers -v0x1bdffb0_0 .net "out", 0 0, L_0x1dd7110; 1 drivers -L_0x1dd6990 .part L_0x1dd7560, 0, 1; -L_0x1dd6af0 .part L_0x1dd7560, 1, 1; -L_0x1dd6c30 .concat8 [ 1 1 0 0], L_0x1dd6920, L_0x1dd6d20; -L_0x1dd6e30 .part L_0x1dd7560, 2, 1; -L_0x1dd6f90 .part L_0x1dd7560, 3, 1; -L_0x1dd7180 .part L_0x1dd6c30, 0, 1; -L_0x1dd7330 .part L_0x1dd6c30, 1, 1; -S_0x1be08c0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bd4240; +L_0x126a060/d .functor OR 1, L_0x126a0d0, L_0x126a230, C4<0>, C4<0>; +L_0x126a060 .delay 1 (30000,30000,30000) L_0x126a060/d; +L_0x126a460/d .functor OR 1, L_0x126a570, L_0x126a6d0, C4<0>, C4<0>; +L_0x126a460 .delay 1 (30000,30000,30000) L_0x126a460/d; +L_0x126a850/d .functor OR 1, L_0x126a8c0, L_0x126aa70, C4<0>, C4<0>; +L_0x126a850 .delay 1 (30000,30000,30000) L_0x126a850/d; +v0x1072290_0 .net *"_s0", 0 0, L_0x126a060; 1 drivers +v0x1072390_0 .net *"_s10", 0 0, L_0x126a570; 1 drivers +v0x1072470_0 .net *"_s12", 0 0, L_0x126a6d0; 1 drivers +v0x1072530_0 .net *"_s14", 0 0, L_0x126a8c0; 1 drivers +v0x1072610_0 .net *"_s16", 0 0, L_0x126aa70; 1 drivers +v0x1072740_0 .net *"_s3", 0 0, L_0x126a0d0; 1 drivers +v0x1072820_0 .net *"_s5", 0 0, L_0x126a230; 1 drivers +v0x1072900_0 .net *"_s6", 0 0, L_0x126a460; 1 drivers +v0x10729e0_0 .net "in", 3 0, L_0x126aca0; 1 drivers +v0x1072b50_0 .net "ors", 1 0, L_0x126a370; 1 drivers +v0x1072c30_0 .net "out", 0 0, L_0x126a850; 1 drivers +L_0x126a0d0 .part L_0x126aca0, 0, 1; +L_0x126a230 .part L_0x126aca0, 1, 1; +L_0x126a370 .concat8 [ 1 1 0 0], L_0x126a060, L_0x126a460; +L_0x126a570 .part L_0x126aca0, 2, 1; +L_0x126a6d0 .part L_0x126aca0, 3, 1; +L_0x126a8c0 .part L_0x126a370, 0, 1; +L_0x126aa70 .part L_0x126a370, 1, 1; +S_0x1073540 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1066ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -5980,80 +5990,80 @@ S_0x1be08c0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bd4240; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1dd2eb0/d .functor XNOR 1, L_0x1ddb470, L_0x1ddb5d0, C4<0>, C4<0>; -L_0x1dd2eb0 .delay 1 (20000,20000,20000) L_0x1dd2eb0/d; -L_0x1dd3120/d .functor AND 1, L_0x1ddb470, L_0x1dd1da0, C4<1>, C4<1>; -L_0x1dd3120 .delay 1 (30000,30000,30000) L_0x1dd3120/d; -L_0x1dd3190/d .functor AND 1, L_0x1dd2eb0, L_0x1dd1b40, C4<1>, C4<1>; -L_0x1dd3190 .delay 1 (30000,30000,30000) L_0x1dd3190/d; -L_0x1dd32f0/d .functor OR 1, L_0x1dd3190, L_0x1dd3120, C4<0>, C4<0>; -L_0x1dd32f0 .delay 1 (30000,30000,30000) L_0x1dd32f0/d; -v0x1be0b70_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers -v0x1be0c60_0 .net "a_", 0 0, L_0x1dd1c90; alias, 1 drivers -v0x1be0d20_0 .net "b", 0 0, L_0x1ddb5d0; alias, 1 drivers -v0x1be0e10_0 .net "b_", 0 0, L_0x1dd1da0; alias, 1 drivers -v0x1be0eb0_0 .net "carryin", 0 0, L_0x1dd1b40; alias, 1 drivers -v0x1be0ff0_0 .net "eq", 0 0, L_0x1dd2eb0; 1 drivers -v0x1be10b0_0 .net "lt", 0 0, L_0x1dd3120; 1 drivers -v0x1be1170_0 .net "out", 0 0, L_0x1dd32f0; 1 drivers -v0x1be1230_0 .net "w0", 0 0, L_0x1dd3190; 1 drivers -S_0x1be1480 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bd4240; +L_0x12665f0/d .functor XNOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; +L_0x12665f0 .delay 1 (20000,20000,20000) L_0x12665f0/d; +L_0x1266860/d .functor AND 1, L_0x126ebe0, L_0x12654e0, C4<1>, C4<1>; +L_0x1266860 .delay 1 (30000,30000,30000) L_0x1266860/d; +L_0x12668d0/d .functor AND 1, L_0x12665f0, L_0x1265280, C4<1>, C4<1>; +L_0x12668d0 .delay 1 (30000,30000,30000) L_0x12668d0/d; +L_0x1266a30/d .functor OR 1, L_0x12668d0, L_0x1266860, C4<0>, C4<0>; +L_0x1266a30 .delay 1 (30000,30000,30000) L_0x1266a30/d; +v0x10737f0_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers +v0x10738e0_0 .net "a_", 0 0, L_0x12653d0; alias, 1 drivers +v0x10739a0_0 .net "b", 0 0, L_0x126ed40; alias, 1 drivers +v0x1073a90_0 .net "b_", 0 0, L_0x12654e0; alias, 1 drivers +v0x1073b30_0 .net "carryin", 0 0, L_0x1265280; alias, 1 drivers +v0x1073c70_0 .net "eq", 0 0, L_0x12665f0; 1 drivers +v0x1073d30_0 .net "lt", 0 0, L_0x1266860; 1 drivers +v0x1073df0_0 .net "out", 0 0, L_0x1266a30; 1 drivers +v0x1073eb0_0 .net "w0", 0 0, L_0x12668d0; 1 drivers +S_0x1074100 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1066ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1dd2c90/d .functor OR 1, L_0x1dd2790, L_0x1be26e0, C4<0>, C4<0>; -L_0x1dd2c90 .delay 1 (30000,30000,30000) L_0x1dd2c90/d; -v0x1be2270_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers -v0x1be23c0_0 .net "b", 0 0, L_0x1dd1da0; alias, 1 drivers -v0x1be2480_0 .net "c1", 0 0, L_0x1dd2790; 1 drivers -v0x1be2520_0 .net "c2", 0 0, L_0x1be26e0; 1 drivers -v0x1be25f0_0 .net "carryin", 0 0, L_0x1dd1b40; alias, 1 drivers -v0x1be2770_0 .net "carryout", 0 0, L_0x1dd2c90; 1 drivers -v0x1be2810_0 .net "s1", 0 0, L_0x1dd26d0; 1 drivers -v0x1be28b0_0 .net "sum", 0 0, L_0x1dd28f0; 1 drivers -S_0x1be16d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1be1480; +L_0x12663d0/d .functor OR 1, L_0x1265ed0, L_0x1075360, C4<0>, C4<0>; +L_0x12663d0 .delay 1 (30000,30000,30000) L_0x12663d0/d; +v0x1074ef0_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers +v0x1075040_0 .net "b", 0 0, L_0x12654e0; alias, 1 drivers +v0x1075100_0 .net "c1", 0 0, L_0x1265ed0; 1 drivers +v0x10751a0_0 .net "c2", 0 0, L_0x1075360; 1 drivers +v0x1075270_0 .net "carryin", 0 0, L_0x1265280; alias, 1 drivers +v0x10753f0_0 .net "carryout", 0 0, L_0x12663d0; 1 drivers +v0x1075490_0 .net "s1", 0 0, L_0x1265e10; 1 drivers +v0x1075530_0 .net "sum", 0 0, L_0x1266030; 1 drivers +S_0x1074350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1074100; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dd26d0/d .functor XOR 1, L_0x1ddb470, L_0x1dd1da0, C4<0>, C4<0>; -L_0x1dd26d0 .delay 1 (30000,30000,30000) L_0x1dd26d0/d; -L_0x1dd2790/d .functor AND 1, L_0x1ddb470, L_0x1dd1da0, C4<1>, C4<1>; -L_0x1dd2790 .delay 1 (30000,30000,30000) L_0x1dd2790/d; -v0x1be1930_0 .net "a", 0 0, L_0x1ddb470; alias, 1 drivers -v0x1be19f0_0 .net "b", 0 0, L_0x1dd1da0; alias, 1 drivers -v0x1be1ab0_0 .net "carryout", 0 0, L_0x1dd2790; alias, 1 drivers -v0x1be1b50_0 .net "sum", 0 0, L_0x1dd26d0; alias, 1 drivers -S_0x1be1c80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1be1480; +L_0x1265e10/d .functor XOR 1, L_0x126ebe0, L_0x12654e0, C4<0>, C4<0>; +L_0x1265e10 .delay 1 (30000,30000,30000) L_0x1265e10/d; +L_0x1265ed0/d .functor AND 1, L_0x126ebe0, L_0x12654e0, C4<1>, C4<1>; +L_0x1265ed0 .delay 1 (30000,30000,30000) L_0x1265ed0/d; +v0x10745b0_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers +v0x1074670_0 .net "b", 0 0, L_0x12654e0; alias, 1 drivers +v0x1074730_0 .net "carryout", 0 0, L_0x1265ed0; alias, 1 drivers +v0x10747d0_0 .net "sum", 0 0, L_0x1265e10; alias, 1 drivers +S_0x1074900 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1074100; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dd28f0/d .functor XOR 1, L_0x1dd26d0, L_0x1dd1b40, C4<0>, C4<0>; -L_0x1dd28f0 .delay 1 (30000,30000,30000) L_0x1dd28f0/d; -L_0x1be26e0/d .functor AND 1, L_0x1dd26d0, L_0x1dd1b40, C4<1>, C4<1>; -L_0x1be26e0 .delay 1 (30000,30000,30000) L_0x1be26e0/d; -v0x1be1ee0_0 .net "a", 0 0, L_0x1dd26d0; alias, 1 drivers -v0x1be1fb0_0 .net "b", 0 0, L_0x1dd1b40; alias, 1 drivers -v0x1be2050_0 .net "carryout", 0 0, L_0x1be26e0; alias, 1 drivers -v0x1be2120_0 .net "sum", 0 0, L_0x1dd28f0; alias, 1 drivers -S_0x1be3cd0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bd3f70; - .timescale -9 -12; -L_0x7f72592dab58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592daba0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1ddb510/d .functor OR 1, L_0x7f72592dab58, L_0x7f72592daba0, C4<0>, C4<0>; -L_0x1ddb510 .delay 1 (30000,30000,30000) L_0x1ddb510/d; -v0x1be3ec0_0 .net/2u *"_s0", 0 0, L_0x7f72592dab58; 1 drivers -v0x1be3fa0_0 .net/2u *"_s2", 0 0, L_0x7f72592daba0; 1 drivers -S_0x1be4080 .scope generate, "alu_slices[11]" "alu_slices[11]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1be4290 .param/l "i" 0 3 37, +C4<01011>; -S_0x1be4350 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1be4080; +L_0x1266030/d .functor XOR 1, L_0x1265e10, L_0x1265280, C4<0>, C4<0>; +L_0x1266030 .delay 1 (30000,30000,30000) L_0x1266030/d; +L_0x1075360/d .functor AND 1, L_0x1265e10, L_0x1265280, C4<1>, C4<1>; +L_0x1075360 .delay 1 (30000,30000,30000) L_0x1075360/d; +v0x1074b60_0 .net "a", 0 0, L_0x1265e10; alias, 1 drivers +v0x1074c30_0 .net "b", 0 0, L_0x1265280; alias, 1 drivers +v0x1074cd0_0 .net "carryout", 0 0, L_0x1075360; alias, 1 drivers +v0x1074da0_0 .net "sum", 0 0, L_0x1266030; alias, 1 drivers +S_0x1076950 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1066bf0; + .timescale -9 -12; +L_0x2b0ab3d05b58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05ba0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x126ec80/d .functor OR 1, L_0x2b0ab3d05b58, L_0x2b0ab3d05ba0, C4<0>, C4<0>; +L_0x126ec80 .delay 1 (30000,30000,30000) L_0x126ec80/d; +v0x1076b40_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05b58; 1 drivers +v0x1076c20_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05ba0; 1 drivers +S_0x1076d00 .scope generate, "alu_slices[11]" "alu_slices[11]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1076f10 .param/l "i" 0 3 41, +C4<01011>; +S_0x1076fd0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1076d00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -6062,445 +6072,445 @@ S_0x1be4350 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1be4080; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1ddb820/d .functor NOT 1, L_0x1de50a0, C4<0>, C4<0>, C4<0>; -L_0x1ddb820 .delay 1 (10000,10000,10000) L_0x1ddb820/d; -L_0x1ddb980/d .functor NOT 1, L_0x1ddb670, C4<0>, C4<0>, C4<0>; -L_0x1ddb980 .delay 1 (10000,10000,10000) L_0x1ddb980/d; -L_0x1ddc910/d .functor XOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; -L_0x1ddc910 .delay 1 (30000,30000,30000) L_0x1ddc910/d; -L_0x7f72592dabe8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dac30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1ddcfc0/d .functor OR 1, L_0x7f72592dabe8, L_0x7f72592dac30, C4<0>, C4<0>; -L_0x1ddcfc0 .delay 1 (30000,30000,30000) L_0x1ddcfc0/d; -L_0x1ddd1c0/d .functor AND 1, L_0x1de50a0, L_0x1ddb670, C4<1>, C4<1>; -L_0x1ddd1c0 .delay 1 (30000,30000,30000) L_0x1ddd1c0/d; -L_0x1ddd280/d .functor NAND 1, L_0x1de50a0, L_0x1ddb670, C4<1>, C4<1>; -L_0x1ddd280 .delay 1 (20000,20000,20000) L_0x1ddd280/d; -L_0x1ddd3e0/d .functor XOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; -L_0x1ddd3e0 .delay 1 (20000,20000,20000) L_0x1ddd3e0/d; -L_0x1ddd890/d .functor OR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; -L_0x1ddd890 .delay 1 (30000,30000,30000) L_0x1ddd890/d; -L_0x1de4fa0/d .functor NOT 1, L_0x1de1200, C4<0>, C4<0>, C4<0>; -L_0x1de4fa0 .delay 1 (10000,10000,10000) L_0x1de4fa0/d; -v0x1bf2a80_0 .net "A", 0 0, L_0x1de50a0; 1 drivers -v0x1bf2b40_0 .net "A_", 0 0, L_0x1ddb820; 1 drivers -v0x1bf2c00_0 .net "B", 0 0, L_0x1ddb670; 1 drivers -v0x1bf2cd0_0 .net "B_", 0 0, L_0x1ddb980; 1 drivers -v0x1bf2d70_0 .net *"_s12", 0 0, L_0x1ddcfc0; 1 drivers -v0x1bf2e60_0 .net/2s *"_s14", 0 0, L_0x7f72592dabe8; 1 drivers -v0x1bf2f20_0 .net/2s *"_s16", 0 0, L_0x7f72592dac30; 1 drivers -v0x1bf3000_0 .net *"_s18", 0 0, L_0x1ddd1c0; 1 drivers -v0x1bf30e0_0 .net *"_s20", 0 0, L_0x1ddd280; 1 drivers -v0x1bf3250_0 .net *"_s22", 0 0, L_0x1ddd3e0; 1 drivers -v0x1bf3330_0 .net *"_s24", 0 0, L_0x1ddd890; 1 drivers -o0x7f725936fd38 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1bf3410_0 name=_s30 -o0x7f725936fd68 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1bf34f0_0 name=_s32 -v0x1bf35d0_0 .net *"_s8", 0 0, L_0x1ddc910; 1 drivers -v0x1bf36b0_0 .net "carryin", 0 0, L_0x1de5320; 1 drivers -v0x1bf3750_0 .net "carryout", 0 0, L_0x1de4c40; 1 drivers -v0x1bf37f0_0 .net "carryouts", 7 0, L_0x1ebfce0; 1 drivers -v0x1bf39a0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bf3a40_0 .net "result", 0 0, L_0x1de1200; 1 drivers -v0x1bf3b30_0 .net "results", 7 0, L_0x1ddd660; 1 drivers -v0x1bf3c40_0 .net "zero", 0 0, L_0x1de4fa0; 1 drivers -LS_0x1ddd660_0_0 .concat8 [ 1 1 1 1], L_0x1ddbe30, L_0x1ddc460, L_0x1ddc910, L_0x1ddcfc0; -LS_0x1ddd660_0_4 .concat8 [ 1 1 1 1], L_0x1ddd1c0, L_0x1ddd280, L_0x1ddd3e0, L_0x1ddd890; -L_0x1ddd660 .concat8 [ 4 4 0 0], LS_0x1ddd660_0_0, LS_0x1ddd660_0_4; -LS_0x1ebfce0_0_0 .concat [ 1 1 1 1], L_0x1ddc0e0, L_0x1ddc7b0, o0x7f725936fd38, L_0x1ddce10; -LS_0x1ebfce0_0_4 .concat [ 4 0 0 0], o0x7f725936fd68; -L_0x1ebfce0 .concat [ 4 4 0 0], LS_0x1ebfce0_0_0, LS_0x1ebfce0_0_4; -S_0x1be45d0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1be4350; +L_0x126ef90/d .functor NOT 1, L_0x1278810, C4<0>, C4<0>, C4<0>; +L_0x126ef90 .delay 1 (10000,10000,10000) L_0x126ef90/d; +L_0x126f0f0/d .functor NOT 1, L_0x126ede0, C4<0>, C4<0>, C4<0>; +L_0x126f0f0 .delay 1 (10000,10000,10000) L_0x126f0f0/d; +L_0x1270140/d .functor XOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; +L_0x1270140 .delay 1 (30000,30000,30000) L_0x1270140/d; +L_0x2b0ab3d05be8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05c30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12707f0/d .functor OR 1, L_0x2b0ab3d05be8, L_0x2b0ab3d05c30, C4<0>, C4<0>; +L_0x12707f0 .delay 1 (30000,30000,30000) L_0x12707f0/d; +L_0x12709f0/d .functor AND 1, L_0x1278810, L_0x126ede0, C4<1>, C4<1>; +L_0x12709f0 .delay 1 (30000,30000,30000) L_0x12709f0/d; +L_0x1270ab0/d .functor NAND 1, L_0x1278810, L_0x126ede0, C4<1>, C4<1>; +L_0x1270ab0 .delay 1 (20000,20000,20000) L_0x1270ab0/d; +L_0x1270c10/d .functor XOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; +L_0x1270c10 .delay 1 (20000,20000,20000) L_0x1270c10/d; +L_0x12710c0/d .functor OR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; +L_0x12710c0 .delay 1 (30000,30000,30000) L_0x12710c0/d; +L_0x1278710/d .functor NOT 1, L_0x1274890, C4<0>, C4<0>, C4<0>; +L_0x1278710 .delay 1 (10000,10000,10000) L_0x1278710/d; +v0x10856c0_0 .net "A", 0 0, L_0x1278810; 1 drivers +v0x1085780_0 .net "A_", 0 0, L_0x126ef90; 1 drivers +v0x1085840_0 .net "B", 0 0, L_0x126ede0; 1 drivers +v0x1085910_0 .net "B_", 0 0, L_0x126f0f0; 1 drivers +v0x10859b0_0 .net *"_s12", 0 0, L_0x12707f0; 1 drivers +v0x1085aa0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05be8; 1 drivers +v0x1085b60_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05c30; 1 drivers +v0x1085c40_0 .net *"_s18", 0 0, L_0x12709f0; 1 drivers +v0x1085d20_0 .net *"_s20", 0 0, L_0x1270ab0; 1 drivers +v0x1085e90_0 .net *"_s22", 0 0, L_0x1270c10; 1 drivers +v0x1085f70_0 .net *"_s24", 0 0, L_0x12710c0; 1 drivers +o0x2b0ab3cbed38 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1086050_0 name=_s30 +o0x2b0ab3cbed68 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1086130_0 name=_s32 +v0x1086210_0 .net *"_s8", 0 0, L_0x1270140; 1 drivers +v0x10862f0_0 .net "carryin", 0 0, L_0x1278a90; 1 drivers +v0x1086390_0 .net "carryout", 0 0, L_0x12783b0; 1 drivers +v0x1086430_0 .net "carryouts", 7 0, L_0x1354090; 1 drivers +v0x10865e0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1086680_0 .net "result", 0 0, L_0x1274890; 1 drivers +v0x1086770_0 .net "results", 7 0, L_0x1270e90; 1 drivers +v0x1086880_0 .net "zero", 0 0, L_0x1278710; 1 drivers +LS_0x1270e90_0_0 .concat8 [ 1 1 1 1], L_0x126f610, L_0x126fc40, L_0x1270140, L_0x12707f0; +LS_0x1270e90_0_4 .concat8 [ 1 1 1 1], L_0x12709f0, L_0x1270ab0, L_0x1270c10, L_0x12710c0; +L_0x1270e90 .concat8 [ 4 4 0 0], LS_0x1270e90_0_0, LS_0x1270e90_0_4; +LS_0x1354090_0_0 .concat [ 1 1 1 1], L_0x126f8c0, L_0x126ffe0, o0x2b0ab3cbed38, L_0x1270640; +LS_0x1354090_0_4 .concat [ 4 0 0 0], o0x2b0ab3cbed68; +L_0x1354090 .concat [ 4 4 0 0], LS_0x1354090_0_0, LS_0x1354090_0_4; +S_0x1077250 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1076fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1ddc0e0/d .functor OR 1, L_0x1ddbbc0, L_0x1ddbf80, C4<0>, C4<0>; -L_0x1ddc0e0 .delay 1 (30000,30000,30000) L_0x1ddc0e0/d; -v0x1be5400_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers -v0x1be54c0_0 .net "b", 0 0, L_0x1ddb670; alias, 1 drivers -v0x1be5590_0 .net "c1", 0 0, L_0x1ddbbc0; 1 drivers -v0x1be5690_0 .net "c2", 0 0, L_0x1ddbf80; 1 drivers -v0x1be5760_0 .net "carryin", 0 0, L_0x1de5320; alias, 1 drivers -v0x1be5850_0 .net "carryout", 0 0, L_0x1ddc0e0; 1 drivers -v0x1be58f0_0 .net "s1", 0 0, L_0x1dcb930; 1 drivers -v0x1be59e0_0 .net "sum", 0 0, L_0x1ddbe30; 1 drivers -S_0x1be4840 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1be45d0; +L_0x126f8c0/d .functor OR 1, L_0x126f3a0, L_0x126f760, C4<0>, C4<0>; +L_0x126f8c0 .delay 1 (30000,30000,30000) L_0x126f8c0/d; +v0x1078080_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers +v0x1078140_0 .net "b", 0 0, L_0x126ede0; alias, 1 drivers +v0x1078210_0 .net "c1", 0 0, L_0x126f3a0; 1 drivers +v0x1078310_0 .net "c2", 0 0, L_0x126f760; 1 drivers +v0x10783e0_0 .net "carryin", 0 0, L_0x1278a90; alias, 1 drivers +v0x10784d0_0 .net "carryout", 0 0, L_0x126f8c0; 1 drivers +v0x1078570_0 .net "s1", 0 0, L_0x126f2e0; 1 drivers +v0x1078660_0 .net "sum", 0 0, L_0x126f610; 1 drivers +S_0x10774c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1077250; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dcb930/d .functor XOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; -L_0x1dcb930 .delay 1 (30000,30000,30000) L_0x1dcb930/d; -L_0x1ddbbc0/d .functor AND 1, L_0x1de50a0, L_0x1ddb670, C4<1>, C4<1>; -L_0x1ddbbc0 .delay 1 (30000,30000,30000) L_0x1ddbbc0/d; -v0x1be4aa0_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers -v0x1be4b80_0 .net "b", 0 0, L_0x1ddb670; alias, 1 drivers -v0x1be4c40_0 .net "carryout", 0 0, L_0x1ddbbc0; alias, 1 drivers -v0x1be4ce0_0 .net "sum", 0 0, L_0x1dcb930; alias, 1 drivers -S_0x1be4e20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1be45d0; +L_0x126f2e0/d .functor XOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; +L_0x126f2e0 .delay 1 (30000,30000,30000) L_0x126f2e0/d; +L_0x126f3a0/d .functor AND 1, L_0x1278810, L_0x126ede0, C4<1>, C4<1>; +L_0x126f3a0 .delay 1 (30000,30000,30000) L_0x126f3a0/d; +v0x1077720_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers +v0x1077800_0 .net "b", 0 0, L_0x126ede0; alias, 1 drivers +v0x10778c0_0 .net "carryout", 0 0, L_0x126f3a0; alias, 1 drivers +v0x1077960_0 .net "sum", 0 0, L_0x126f2e0; alias, 1 drivers +S_0x1077aa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1077250; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ddbe30/d .functor XOR 1, L_0x1dcb930, L_0x1de5320, C4<0>, C4<0>; -L_0x1ddbe30 .delay 1 (30000,30000,30000) L_0x1ddbe30/d; -L_0x1ddbf80/d .functor AND 1, L_0x1dcb930, L_0x1de5320, C4<1>, C4<1>; -L_0x1ddbf80 .delay 1 (30000,30000,30000) L_0x1ddbf80/d; -v0x1be5080_0 .net "a", 0 0, L_0x1dcb930; alias, 1 drivers -v0x1be5120_0 .net "b", 0 0, L_0x1de5320; alias, 1 drivers -v0x1be51c0_0 .net "carryout", 0 0, L_0x1ddbf80; alias, 1 drivers -v0x1be5290_0 .net "sum", 0 0, L_0x1ddbe30; alias, 1 drivers -S_0x1be5ab0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1be4350; +L_0x126f610/d .functor XOR 1, L_0x126f2e0, L_0x1278a90, C4<0>, C4<0>; +L_0x126f610 .delay 1 (30000,30000,30000) L_0x126f610/d; +L_0x126f760/d .functor AND 1, L_0x126f2e0, L_0x1278a90, C4<1>, C4<1>; +L_0x126f760 .delay 1 (30000,30000,30000) L_0x126f760/d; +v0x1077d00_0 .net "a", 0 0, L_0x126f2e0; alias, 1 drivers +v0x1077da0_0 .net "b", 0 0, L_0x1278a90; alias, 1 drivers +v0x1077e40_0 .net "carryout", 0 0, L_0x126f760; alias, 1 drivers +v0x1077f10_0 .net "sum", 0 0, L_0x126f610; alias, 1 drivers +S_0x1078730 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1076fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1beaea0_0 .net "ands", 7 0, L_0x1de2c40; 1 drivers -v0x1beafb0_0 .net "in", 7 0, L_0x1ebfce0; alias, 1 drivers -v0x1beb070_0 .net "out", 0 0, L_0x1de4c40; alias, 1 drivers -v0x1beb140_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1be5cd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1be5ab0; +v0x107db20_0 .net "ands", 7 0, L_0x12763b0; 1 drivers +v0x107dc30_0 .net "in", 7 0, L_0x1354090; alias, 1 drivers +v0x107dcf0_0 .net "out", 0 0, L_0x12783b0; alias, 1 drivers +v0x107ddc0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1078950 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1078730; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1be8400_0 .net "A", 7 0, L_0x1ebfce0; alias, 1 drivers -v0x1be8500_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1be85c0_0 .net *"_s0", 0 0, L_0x1de1560; 1 drivers -v0x1be8680_0 .net *"_s12", 0 0, L_0x1de1ed0; 1 drivers -v0x1be8760_0 .net *"_s16", 0 0, L_0x1de2230; 1 drivers -v0x1be8890_0 .net *"_s20", 0 0, L_0x1de2540; 1 drivers -v0x1be8970_0 .net *"_s24", 0 0, L_0x1de2930; 1 drivers -v0x1be8a50_0 .net *"_s28", 0 0, L_0x1de28c0; 1 drivers -v0x1be8b30_0 .net *"_s4", 0 0, L_0x1de1870; 1 drivers -v0x1be8ca0_0 .net *"_s8", 0 0, L_0x1de1bc0; 1 drivers -v0x1be8d80_0 .net "out", 7 0, L_0x1de2c40; alias, 1 drivers -L_0x1de1620 .part L_0x1ebfce0, 0, 1; -L_0x1de1780 .part v0x1d6daa0_0, 0, 1; -L_0x1de1930 .part L_0x1ebfce0, 1, 1; -L_0x1de1b20 .part v0x1d6daa0_0, 1, 1; -L_0x1de1c80 .part L_0x1ebfce0, 2, 1; -L_0x1de1de0 .part v0x1d6daa0_0, 2, 1; -L_0x1de1f90 .part L_0x1ebfce0, 3, 1; -L_0x1de20f0 .part v0x1d6daa0_0, 3, 1; -L_0x1de22f0 .part L_0x1ebfce0, 4, 1; -L_0x1de2450 .part v0x1d6daa0_0, 4, 1; -L_0x1de25b0 .part L_0x1ebfce0, 5, 1; -L_0x1de2820 .part v0x1d6daa0_0, 5, 1; -L_0x1de29f0 .part L_0x1ebfce0, 6, 1; -L_0x1de2b50 .part v0x1d6daa0_0, 6, 1; -LS_0x1de2c40_0_0 .concat8 [ 1 1 1 1], L_0x1de1560, L_0x1de1870, L_0x1de1bc0, L_0x1de1ed0; -LS_0x1de2c40_0_4 .concat8 [ 1 1 1 1], L_0x1de2230, L_0x1de2540, L_0x1de2930, L_0x1de28c0; -L_0x1de2c40 .concat8 [ 4 4 0 0], LS_0x1de2c40_0_0, LS_0x1de2c40_0_4; -L_0x1de3000 .part L_0x1ebfce0, 7, 1; -L_0x1de31f0 .part v0x1d6daa0_0, 7, 1; -S_0x1be5f30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be6140 .param/l "i" 0 4 54, +C4<00>; -L_0x1de1560/d .functor AND 1, L_0x1de1620, L_0x1de1780, C4<1>, C4<1>; -L_0x1de1560 .delay 1 (30000,30000,30000) L_0x1de1560/d; -v0x1be6220_0 .net *"_s0", 0 0, L_0x1de1620; 1 drivers -v0x1be6300_0 .net *"_s1", 0 0, L_0x1de1780; 1 drivers -S_0x1be63e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be65f0 .param/l "i" 0 4 54, +C4<01>; -L_0x1de1870/d .functor AND 1, L_0x1de1930, L_0x1de1b20, C4<1>, C4<1>; -L_0x1de1870 .delay 1 (30000,30000,30000) L_0x1de1870/d; -v0x1be66b0_0 .net *"_s0", 0 0, L_0x1de1930; 1 drivers -v0x1be6790_0 .net *"_s1", 0 0, L_0x1de1b20; 1 drivers -S_0x1be6870 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be6a80 .param/l "i" 0 4 54, +C4<010>; -L_0x1de1bc0/d .functor AND 1, L_0x1de1c80, L_0x1de1de0, C4<1>, C4<1>; -L_0x1de1bc0 .delay 1 (30000,30000,30000) L_0x1de1bc0/d; -v0x1be6b20_0 .net *"_s0", 0 0, L_0x1de1c80; 1 drivers -v0x1be6c00_0 .net *"_s1", 0 0, L_0x1de1de0; 1 drivers -S_0x1be6ce0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be6ef0 .param/l "i" 0 4 54, +C4<011>; -L_0x1de1ed0/d .functor AND 1, L_0x1de1f90, L_0x1de20f0, C4<1>, C4<1>; -L_0x1de1ed0 .delay 1 (30000,30000,30000) L_0x1de1ed0/d; -v0x1be6fb0_0 .net *"_s0", 0 0, L_0x1de1f90; 1 drivers -v0x1be7090_0 .net *"_s1", 0 0, L_0x1de20f0; 1 drivers -S_0x1be7170 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be73d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1de2230/d .functor AND 1, L_0x1de22f0, L_0x1de2450, C4<1>, C4<1>; -L_0x1de2230 .delay 1 (30000,30000,30000) L_0x1de2230/d; -v0x1be7490_0 .net *"_s0", 0 0, L_0x1de22f0; 1 drivers -v0x1be7570_0 .net *"_s1", 0 0, L_0x1de2450; 1 drivers -S_0x1be7650 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be7860 .param/l "i" 0 4 54, +C4<0101>; -L_0x1de2540/d .functor AND 1, L_0x1de25b0, L_0x1de2820, C4<1>, C4<1>; -L_0x1de2540 .delay 1 (30000,30000,30000) L_0x1de2540/d; -v0x1be7920_0 .net *"_s0", 0 0, L_0x1de25b0; 1 drivers -v0x1be7a00_0 .net *"_s1", 0 0, L_0x1de2820; 1 drivers -S_0x1be7ae0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be7cf0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1de2930/d .functor AND 1, L_0x1de29f0, L_0x1de2b50, C4<1>, C4<1>; -L_0x1de2930 .delay 1 (30000,30000,30000) L_0x1de2930/d; -v0x1be7db0_0 .net *"_s0", 0 0, L_0x1de29f0; 1 drivers -v0x1be7e90_0 .net *"_s1", 0 0, L_0x1de2b50; 1 drivers -S_0x1be7f70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1be5cd0; - .timescale -9 -12; -P_0x1be8180 .param/l "i" 0 4 54, +C4<0111>; -L_0x1de28c0/d .functor AND 1, L_0x1de3000, L_0x1de31f0, C4<1>, C4<1>; -L_0x1de28c0 .delay 1 (30000,30000,30000) L_0x1de28c0/d; -v0x1be8240_0 .net *"_s0", 0 0, L_0x1de3000; 1 drivers -v0x1be8320_0 .net *"_s1", 0 0, L_0x1de31f0; 1 drivers -S_0x1be8ee0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1be5ab0; +v0x107b080_0 .net "A", 7 0, L_0x1354090; alias, 1 drivers +v0x107b180_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x107b240_0 .net *"_s0", 0 0, L_0x1274bf0; 1 drivers +v0x107b300_0 .net *"_s12", 0 0, L_0x1275560; 1 drivers +v0x107b3e0_0 .net *"_s16", 0 0, L_0x12758c0; 1 drivers +v0x107b510_0 .net *"_s20", 0 0, L_0x1275c30; 1 drivers +v0x107b5f0_0 .net *"_s24", 0 0, L_0x1276020; 1 drivers +v0x107b6d0_0 .net *"_s28", 0 0, L_0x1275fb0; 1 drivers +v0x107b7b0_0 .net *"_s4", 0 0, L_0x1274f00; 1 drivers +v0x107b920_0 .net *"_s8", 0 0, L_0x1275250; 1 drivers +v0x107ba00_0 .net "out", 7 0, L_0x12763b0; alias, 1 drivers +L_0x1274cb0 .part L_0x1354090, 0, 1; +L_0x1274e10 .part v0x12010b0_0, 0, 1; +L_0x1274fc0 .part L_0x1354090, 1, 1; +L_0x12751b0 .part v0x12010b0_0, 1, 1; +L_0x1275310 .part L_0x1354090, 2, 1; +L_0x1275470 .part v0x12010b0_0, 2, 1; +L_0x1275620 .part L_0x1354090, 3, 1; +L_0x1275780 .part v0x12010b0_0, 3, 1; +L_0x1275980 .part L_0x1354090, 4, 1; +L_0x1275ae0 .part v0x12010b0_0, 4, 1; +L_0x1275ca0 .part L_0x1354090, 5, 1; +L_0x1275f10 .part v0x12010b0_0, 5, 1; +L_0x12760e0 .part L_0x1354090, 6, 1; +L_0x1276240 .part v0x12010b0_0, 6, 1; +LS_0x12763b0_0_0 .concat8 [ 1 1 1 1], L_0x1274bf0, L_0x1274f00, L_0x1275250, L_0x1275560; +LS_0x12763b0_0_4 .concat8 [ 1 1 1 1], L_0x12758c0, L_0x1275c30, L_0x1276020, L_0x1275fb0; +L_0x12763b0 .concat8 [ 4 4 0 0], LS_0x12763b0_0_0, LS_0x12763b0_0_4; +L_0x1276770 .part L_0x1354090, 7, 1; +L_0x1276960 .part v0x12010b0_0, 7, 1; +S_0x1078bb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x1078dc0 .param/l "i" 0 4 54, +C4<00>; +L_0x1274bf0/d .functor AND 1, L_0x1274cb0, L_0x1274e10, C4<1>, C4<1>; +L_0x1274bf0 .delay 1 (30000,30000,30000) L_0x1274bf0/d; +v0x1078ea0_0 .net *"_s0", 0 0, L_0x1274cb0; 1 drivers +v0x1078f80_0 .net *"_s1", 0 0, L_0x1274e10; 1 drivers +S_0x1079060 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x1079270 .param/l "i" 0 4 54, +C4<01>; +L_0x1274f00/d .functor AND 1, L_0x1274fc0, L_0x12751b0, C4<1>, C4<1>; +L_0x1274f00 .delay 1 (30000,30000,30000) L_0x1274f00/d; +v0x1079330_0 .net *"_s0", 0 0, L_0x1274fc0; 1 drivers +v0x1079410_0 .net *"_s1", 0 0, L_0x12751b0; 1 drivers +S_0x10794f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x1079700 .param/l "i" 0 4 54, +C4<010>; +L_0x1275250/d .functor AND 1, L_0x1275310, L_0x1275470, C4<1>, C4<1>; +L_0x1275250 .delay 1 (30000,30000,30000) L_0x1275250/d; +v0x10797a0_0 .net *"_s0", 0 0, L_0x1275310; 1 drivers +v0x1079880_0 .net *"_s1", 0 0, L_0x1275470; 1 drivers +S_0x1079960 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x1079b70 .param/l "i" 0 4 54, +C4<011>; +L_0x1275560/d .functor AND 1, L_0x1275620, L_0x1275780, C4<1>, C4<1>; +L_0x1275560 .delay 1 (30000,30000,30000) L_0x1275560/d; +v0x1079c30_0 .net *"_s0", 0 0, L_0x1275620; 1 drivers +v0x1079d10_0 .net *"_s1", 0 0, L_0x1275780; 1 drivers +S_0x1079df0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x107a050 .param/l "i" 0 4 54, +C4<0100>; +L_0x12758c0/d .functor AND 1, L_0x1275980, L_0x1275ae0, C4<1>, C4<1>; +L_0x12758c0 .delay 1 (30000,30000,30000) L_0x12758c0/d; +v0x107a110_0 .net *"_s0", 0 0, L_0x1275980; 1 drivers +v0x107a1f0_0 .net *"_s1", 0 0, L_0x1275ae0; 1 drivers +S_0x107a2d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x107a4e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1275c30/d .functor AND 1, L_0x1275ca0, L_0x1275f10, C4<1>, C4<1>; +L_0x1275c30 .delay 1 (30000,30000,30000) L_0x1275c30/d; +v0x107a5a0_0 .net *"_s0", 0 0, L_0x1275ca0; 1 drivers +v0x107a680_0 .net *"_s1", 0 0, L_0x1275f10; 1 drivers +S_0x107a760 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x107a970 .param/l "i" 0 4 54, +C4<0110>; +L_0x1276020/d .functor AND 1, L_0x12760e0, L_0x1276240, C4<1>, C4<1>; +L_0x1276020 .delay 1 (30000,30000,30000) L_0x1276020/d; +v0x107aa30_0 .net *"_s0", 0 0, L_0x12760e0; 1 drivers +v0x107ab10_0 .net *"_s1", 0 0, L_0x1276240; 1 drivers +S_0x107abf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1078950; + .timescale -9 -12; +P_0x107ae00 .param/l "i" 0 4 54, +C4<0111>; +L_0x1275fb0/d .functor AND 1, L_0x1276770, L_0x1276960, C4<1>, C4<1>; +L_0x1275fb0 .delay 1 (30000,30000,30000) L_0x1275fb0/d; +v0x107aec0_0 .net *"_s0", 0 0, L_0x1276770; 1 drivers +v0x107afa0_0 .net *"_s1", 0 0, L_0x1276960; 1 drivers +S_0x107bb60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1078730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1de4c40/d .functor OR 1, L_0x1de4d00, L_0x1de4eb0, C4<0>, C4<0>; -L_0x1de4c40 .delay 1 (30000,30000,30000) L_0x1de4c40/d; -v0x1beaa30_0 .net *"_s10", 0 0, L_0x1de4d00; 1 drivers -v0x1beab10_0 .net *"_s12", 0 0, L_0x1de4eb0; 1 drivers -v0x1beabf0_0 .net "in", 7 0, L_0x1de2c40; alias, 1 drivers -v0x1beacc0_0 .net "ors", 1 0, L_0x1de4a60; 1 drivers -v0x1bead80_0 .net "out", 0 0, L_0x1de4c40; alias, 1 drivers -L_0x1de3e30 .part L_0x1de2c40, 0, 4; -L_0x1de4a60 .concat8 [ 1 1 0 0], L_0x1de3b20, L_0x1de4750; -L_0x1de4ba0 .part L_0x1de2c40, 4, 4; -L_0x1de4d00 .part L_0x1de4a60, 0, 1; -L_0x1de4eb0 .part L_0x1de4a60, 1, 1; -S_0x1be90a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1be8ee0; +L_0x12783b0/d .functor OR 1, L_0x1278470, L_0x1278620, C4<0>, C4<0>; +L_0x12783b0 .delay 1 (30000,30000,30000) L_0x12783b0/d; +v0x107d6b0_0 .net *"_s10", 0 0, L_0x1278470; 1 drivers +v0x107d790_0 .net *"_s12", 0 0, L_0x1278620; 1 drivers +v0x107d870_0 .net "in", 7 0, L_0x12763b0; alias, 1 drivers +v0x107d940_0 .net "ors", 1 0, L_0x12781d0; 1 drivers +v0x107da00_0 .net "out", 0 0, L_0x12783b0; alias, 1 drivers +L_0x12775a0 .part L_0x12763b0, 0, 4; +L_0x12781d0 .concat8 [ 1 1 0 0], L_0x1277290, L_0x1277ec0; +L_0x1278310 .part L_0x12763b0, 4, 4; +L_0x1278470 .part L_0x12781d0, 0, 1; +L_0x1278620 .part L_0x12781d0, 1, 1; +S_0x107bd20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x107bb60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1de32e0/d .functor OR 1, L_0x1de33a0, L_0x1de3500, C4<0>, C4<0>; -L_0x1de32e0 .delay 1 (30000,30000,30000) L_0x1de32e0/d; -L_0x1de3730/d .functor OR 1, L_0x1de3840, L_0x1de39a0, C4<0>, C4<0>; -L_0x1de3730 .delay 1 (30000,30000,30000) L_0x1de3730/d; -L_0x1de3b20/d .functor OR 1, L_0x1de3b90, L_0x1de3d40, C4<0>, C4<0>; -L_0x1de3b20 .delay 1 (30000,30000,30000) L_0x1de3b20/d; -v0x1be92f0_0 .net *"_s0", 0 0, L_0x1de32e0; 1 drivers -v0x1be93f0_0 .net *"_s10", 0 0, L_0x1de3840; 1 drivers -v0x1be94d0_0 .net *"_s12", 0 0, L_0x1de39a0; 1 drivers -v0x1be9590_0 .net *"_s14", 0 0, L_0x1de3b90; 1 drivers -v0x1be9670_0 .net *"_s16", 0 0, L_0x1de3d40; 1 drivers -v0x1be97a0_0 .net *"_s3", 0 0, L_0x1de33a0; 1 drivers -v0x1be9880_0 .net *"_s5", 0 0, L_0x1de3500; 1 drivers -v0x1be9960_0 .net *"_s6", 0 0, L_0x1de3730; 1 drivers -v0x1be9a40_0 .net "in", 3 0, L_0x1de3e30; 1 drivers -v0x1be9bb0_0 .net "ors", 1 0, L_0x1de3640; 1 drivers -v0x1be9c90_0 .net "out", 0 0, L_0x1de3b20; 1 drivers -L_0x1de33a0 .part L_0x1de3e30, 0, 1; -L_0x1de3500 .part L_0x1de3e30, 1, 1; -L_0x1de3640 .concat8 [ 1 1 0 0], L_0x1de32e0, L_0x1de3730; -L_0x1de3840 .part L_0x1de3e30, 2, 1; -L_0x1de39a0 .part L_0x1de3e30, 3, 1; -L_0x1de3b90 .part L_0x1de3640, 0, 1; -L_0x1de3d40 .part L_0x1de3640, 1, 1; -S_0x1be9db0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1be8ee0; +L_0x1276a50/d .functor OR 1, L_0x1276b10, L_0x1276c70, C4<0>, C4<0>; +L_0x1276a50 .delay 1 (30000,30000,30000) L_0x1276a50/d; +L_0x1276ea0/d .functor OR 1, L_0x1276fb0, L_0x1277110, C4<0>, C4<0>; +L_0x1276ea0 .delay 1 (30000,30000,30000) L_0x1276ea0/d; +L_0x1277290/d .functor OR 1, L_0x1277300, L_0x12774b0, C4<0>, C4<0>; +L_0x1277290 .delay 1 (30000,30000,30000) L_0x1277290/d; +v0x107bf70_0 .net *"_s0", 0 0, L_0x1276a50; 1 drivers +v0x107c070_0 .net *"_s10", 0 0, L_0x1276fb0; 1 drivers +v0x107c150_0 .net *"_s12", 0 0, L_0x1277110; 1 drivers +v0x107c210_0 .net *"_s14", 0 0, L_0x1277300; 1 drivers +v0x107c2f0_0 .net *"_s16", 0 0, L_0x12774b0; 1 drivers +v0x107c420_0 .net *"_s3", 0 0, L_0x1276b10; 1 drivers +v0x107c500_0 .net *"_s5", 0 0, L_0x1276c70; 1 drivers +v0x107c5e0_0 .net *"_s6", 0 0, L_0x1276ea0; 1 drivers +v0x107c6c0_0 .net "in", 3 0, L_0x12775a0; 1 drivers +v0x107c830_0 .net "ors", 1 0, L_0x1276db0; 1 drivers +v0x107c910_0 .net "out", 0 0, L_0x1277290; 1 drivers +L_0x1276b10 .part L_0x12775a0, 0, 1; +L_0x1276c70 .part L_0x12775a0, 1, 1; +L_0x1276db0 .concat8 [ 1 1 0 0], L_0x1276a50, L_0x1276ea0; +L_0x1276fb0 .part L_0x12775a0, 2, 1; +L_0x1277110 .part L_0x12775a0, 3, 1; +L_0x1277300 .part L_0x1276db0, 0, 1; +L_0x12774b0 .part L_0x1276db0, 1, 1; +S_0x107ca30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x107bb60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1de3f60/d .functor OR 1, L_0x1de3fd0, L_0x1de4130, C4<0>, C4<0>; -L_0x1de3f60 .delay 1 (30000,30000,30000) L_0x1de3f60/d; -L_0x1de4360/d .functor OR 1, L_0x1de4470, L_0x1de45d0, C4<0>, C4<0>; -L_0x1de4360 .delay 1 (30000,30000,30000) L_0x1de4360/d; -L_0x1de4750/d .functor OR 1, L_0x1de47c0, L_0x1de4970, C4<0>, C4<0>; -L_0x1de4750 .delay 1 (30000,30000,30000) L_0x1de4750/d; -v0x1be9f70_0 .net *"_s0", 0 0, L_0x1de3f60; 1 drivers -v0x1bea070_0 .net *"_s10", 0 0, L_0x1de4470; 1 drivers -v0x1bea150_0 .net *"_s12", 0 0, L_0x1de45d0; 1 drivers -v0x1bea210_0 .net *"_s14", 0 0, L_0x1de47c0; 1 drivers -v0x1bea2f0_0 .net *"_s16", 0 0, L_0x1de4970; 1 drivers -v0x1bea420_0 .net *"_s3", 0 0, L_0x1de3fd0; 1 drivers -v0x1bea500_0 .net *"_s5", 0 0, L_0x1de4130; 1 drivers -v0x1bea5e0_0 .net *"_s6", 0 0, L_0x1de4360; 1 drivers -v0x1bea6c0_0 .net "in", 3 0, L_0x1de4ba0; 1 drivers -v0x1bea830_0 .net "ors", 1 0, L_0x1de4270; 1 drivers -v0x1bea910_0 .net "out", 0 0, L_0x1de4750; 1 drivers -L_0x1de3fd0 .part L_0x1de4ba0, 0, 1; -L_0x1de4130 .part L_0x1de4ba0, 1, 1; -L_0x1de4270 .concat8 [ 1 1 0 0], L_0x1de3f60, L_0x1de4360; -L_0x1de4470 .part L_0x1de4ba0, 2, 1; -L_0x1de45d0 .part L_0x1de4ba0, 3, 1; -L_0x1de47c0 .part L_0x1de4270, 0, 1; -L_0x1de4970 .part L_0x1de4270, 1, 1; -S_0x1beb220 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1be4350; +L_0x12776d0/d .functor OR 1, L_0x1277740, L_0x12778a0, C4<0>, C4<0>; +L_0x12776d0 .delay 1 (30000,30000,30000) L_0x12776d0/d; +L_0x1277ad0/d .functor OR 1, L_0x1277be0, L_0x1277d40, C4<0>, C4<0>; +L_0x1277ad0 .delay 1 (30000,30000,30000) L_0x1277ad0/d; +L_0x1277ec0/d .functor OR 1, L_0x1277f30, L_0x12780e0, C4<0>, C4<0>; +L_0x1277ec0 .delay 1 (30000,30000,30000) L_0x1277ec0/d; +v0x107cbf0_0 .net *"_s0", 0 0, L_0x12776d0; 1 drivers +v0x107ccf0_0 .net *"_s10", 0 0, L_0x1277be0; 1 drivers +v0x107cdd0_0 .net *"_s12", 0 0, L_0x1277d40; 1 drivers +v0x107ce90_0 .net *"_s14", 0 0, L_0x1277f30; 1 drivers +v0x107cf70_0 .net *"_s16", 0 0, L_0x12780e0; 1 drivers +v0x107d0a0_0 .net *"_s3", 0 0, L_0x1277740; 1 drivers +v0x107d180_0 .net *"_s5", 0 0, L_0x12778a0; 1 drivers +v0x107d260_0 .net *"_s6", 0 0, L_0x1277ad0; 1 drivers +v0x107d340_0 .net "in", 3 0, L_0x1278310; 1 drivers +v0x107d4b0_0 .net "ors", 1 0, L_0x12779e0; 1 drivers +v0x107d590_0 .net "out", 0 0, L_0x1277ec0; 1 drivers +L_0x1277740 .part L_0x1278310, 0, 1; +L_0x12778a0 .part L_0x1278310, 1, 1; +L_0x12779e0 .concat8 [ 1 1 0 0], L_0x12776d0, L_0x1277ad0; +L_0x1277be0 .part L_0x1278310, 2, 1; +L_0x1277d40 .part L_0x1278310, 3, 1; +L_0x1277f30 .part L_0x12779e0, 0, 1; +L_0x12780e0 .part L_0x12779e0, 1, 1; +S_0x107dea0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1076fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bf0650_0 .net "ands", 7 0, L_0x1ddf200; 1 drivers -v0x1bf0760_0 .net "in", 7 0, L_0x1ddd660; alias, 1 drivers -v0x1bf0820_0 .net "out", 0 0, L_0x1de1200; alias, 1 drivers -v0x1bf08f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1beb470 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1beb220; +v0x10832d0_0 .net "ands", 7 0, L_0x1272950; 1 drivers +v0x10833e0_0 .net "in", 7 0, L_0x1270e90; alias, 1 drivers +v0x10834a0_0 .net "out", 0 0, L_0x1274890; alias, 1 drivers +v0x1083570_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x107e0f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x107dea0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bedbb0_0 .net "A", 7 0, L_0x1ddd660; alias, 1 drivers -v0x1bedcb0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bedd70_0 .net *"_s0", 0 0, L_0x1ddd9f0; 1 drivers -v0x1bede30_0 .net *"_s12", 0 0, L_0x1dde3b0; 1 drivers -v0x1bedf10_0 .net *"_s16", 0 0, L_0x1dde710; 1 drivers -v0x1bee040_0 .net *"_s20", 0 0, L_0x1ddeb40; 1 drivers -v0x1bee120_0 .net *"_s24", 0 0, L_0x1ddee70; 1 drivers -v0x1bee200_0 .net *"_s28", 0 0, L_0x1ddee00; 1 drivers -v0x1bee2e0_0 .net *"_s4", 0 0, L_0x1dddd90; 1 drivers -v0x1bee450_0 .net *"_s8", 0 0, L_0x1dde0a0; 1 drivers -v0x1bee530_0 .net "out", 7 0, L_0x1ddf200; alias, 1 drivers -L_0x1dddb00 .part L_0x1ddd660, 0, 1; -L_0x1dddcf0 .part v0x1d6daa0_0, 0, 1; -L_0x1ddde50 .part L_0x1ddd660, 1, 1; -L_0x1dddfb0 .part v0x1d6daa0_0, 1, 1; -L_0x1dde160 .part L_0x1ddd660, 2, 1; -L_0x1dde2c0 .part v0x1d6daa0_0, 2, 1; -L_0x1dde470 .part L_0x1ddd660, 3, 1; -L_0x1dde5d0 .part v0x1d6daa0_0, 3, 1; -L_0x1dde7d0 .part L_0x1ddd660, 4, 1; -L_0x1ddea40 .part v0x1d6daa0_0, 4, 1; -L_0x1ddebb0 .part L_0x1ddd660, 5, 1; -L_0x1dded10 .part v0x1d6daa0_0, 5, 1; -L_0x1ddef30 .part L_0x1ddd660, 6, 1; -L_0x1ddf090 .part v0x1d6daa0_0, 6, 1; -LS_0x1ddf200_0_0 .concat8 [ 1 1 1 1], L_0x1ddd9f0, L_0x1dddd90, L_0x1dde0a0, L_0x1dde3b0; -LS_0x1ddf200_0_4 .concat8 [ 1 1 1 1], L_0x1dde710, L_0x1ddeb40, L_0x1ddee70, L_0x1ddee00; -L_0x1ddf200 .concat8 [ 4 4 0 0], LS_0x1ddf200_0_0, LS_0x1ddf200_0_4; -L_0x1ddf5c0 .part L_0x1ddd660, 7, 1; -L_0x1ddf7b0 .part v0x1d6daa0_0, 7, 1; -S_0x1beb6b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1beb8c0 .param/l "i" 0 4 54, +C4<00>; -L_0x1ddd9f0/d .functor AND 1, L_0x1dddb00, L_0x1dddcf0, C4<1>, C4<1>; -L_0x1ddd9f0 .delay 1 (30000,30000,30000) L_0x1ddd9f0/d; -v0x1beb9a0_0 .net *"_s0", 0 0, L_0x1dddb00; 1 drivers -v0x1beba80_0 .net *"_s1", 0 0, L_0x1dddcf0; 1 drivers -S_0x1bebb60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1bebd70 .param/l "i" 0 4 54, +C4<01>; -L_0x1dddd90/d .functor AND 1, L_0x1ddde50, L_0x1dddfb0, C4<1>, C4<1>; -L_0x1dddd90 .delay 1 (30000,30000,30000) L_0x1dddd90/d; -v0x1bebe30_0 .net *"_s0", 0 0, L_0x1ddde50; 1 drivers -v0x1bebf10_0 .net *"_s1", 0 0, L_0x1dddfb0; 1 drivers -S_0x1bebff0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1bec230 .param/l "i" 0 4 54, +C4<010>; -L_0x1dde0a0/d .functor AND 1, L_0x1dde160, L_0x1dde2c0, C4<1>, C4<1>; -L_0x1dde0a0 .delay 1 (30000,30000,30000) L_0x1dde0a0/d; -v0x1bec2d0_0 .net *"_s0", 0 0, L_0x1dde160; 1 drivers -v0x1bec3b0_0 .net *"_s1", 0 0, L_0x1dde2c0; 1 drivers -S_0x1bec490 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1bec6a0 .param/l "i" 0 4 54, +C4<011>; -L_0x1dde3b0/d .functor AND 1, L_0x1dde470, L_0x1dde5d0, C4<1>, C4<1>; -L_0x1dde3b0 .delay 1 (30000,30000,30000) L_0x1dde3b0/d; -v0x1bec760_0 .net *"_s0", 0 0, L_0x1dde470; 1 drivers -v0x1bec840_0 .net *"_s1", 0 0, L_0x1dde5d0; 1 drivers -S_0x1bec920 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1becb80 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dde710/d .functor AND 1, L_0x1dde7d0, L_0x1ddea40, C4<1>, C4<1>; -L_0x1dde710 .delay 1 (30000,30000,30000) L_0x1dde710/d; -v0x1becc40_0 .net *"_s0", 0 0, L_0x1dde7d0; 1 drivers -v0x1becd20_0 .net *"_s1", 0 0, L_0x1ddea40; 1 drivers -S_0x1bece00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1bed010 .param/l "i" 0 4 54, +C4<0101>; -L_0x1ddeb40/d .functor AND 1, L_0x1ddebb0, L_0x1dded10, C4<1>, C4<1>; -L_0x1ddeb40 .delay 1 (30000,30000,30000) L_0x1ddeb40/d; -v0x1bed0d0_0 .net *"_s0", 0 0, L_0x1ddebb0; 1 drivers -v0x1bed1b0_0 .net *"_s1", 0 0, L_0x1dded10; 1 drivers -S_0x1bed290 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1bed4a0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1ddee70/d .functor AND 1, L_0x1ddef30, L_0x1ddf090, C4<1>, C4<1>; -L_0x1ddee70 .delay 1 (30000,30000,30000) L_0x1ddee70/d; -v0x1bed560_0 .net *"_s0", 0 0, L_0x1ddef30; 1 drivers -v0x1bed640_0 .net *"_s1", 0 0, L_0x1ddf090; 1 drivers -S_0x1bed720 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1beb470; - .timescale -9 -12; -P_0x1bed930 .param/l "i" 0 4 54, +C4<0111>; -L_0x1ddee00/d .functor AND 1, L_0x1ddf5c0, L_0x1ddf7b0, C4<1>, C4<1>; -L_0x1ddee00 .delay 1 (30000,30000,30000) L_0x1ddee00/d; -v0x1bed9f0_0 .net *"_s0", 0 0, L_0x1ddf5c0; 1 drivers -v0x1bedad0_0 .net *"_s1", 0 0, L_0x1ddf7b0; 1 drivers -S_0x1bee690 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1beb220; +v0x1080830_0 .net "A", 7 0, L_0x1270e90; alias, 1 drivers +v0x1080930_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10809f0_0 .net *"_s0", 0 0, L_0x1271220; 1 drivers +v0x1080ab0_0 .net *"_s12", 0 0, L_0x1271be0; 1 drivers +v0x1080b90_0 .net *"_s16", 0 0, L_0x1271f40; 1 drivers +v0x1080cc0_0 .net *"_s20", 0 0, L_0x1272310; 1 drivers +v0x1080da0_0 .net *"_s24", 0 0, L_0x1272640; 1 drivers +v0x1080e80_0 .net *"_s28", 0 0, L_0x12725d0; 1 drivers +v0x1080f60_0 .net *"_s4", 0 0, L_0x12715c0; 1 drivers +v0x10810d0_0 .net *"_s8", 0 0, L_0x12718d0; 1 drivers +v0x10811b0_0 .net "out", 7 0, L_0x1272950; alias, 1 drivers +L_0x1271330 .part L_0x1270e90, 0, 1; +L_0x1271520 .part v0x12010b0_0, 0, 1; +L_0x1271680 .part L_0x1270e90, 1, 1; +L_0x12717e0 .part v0x12010b0_0, 1, 1; +L_0x1271990 .part L_0x1270e90, 2, 1; +L_0x1271af0 .part v0x12010b0_0, 2, 1; +L_0x1271ca0 .part L_0x1270e90, 3, 1; +L_0x1271e00 .part v0x12010b0_0, 3, 1; +L_0x1272000 .part L_0x1270e90, 4, 1; +L_0x1272270 .part v0x12010b0_0, 4, 1; +L_0x1272380 .part L_0x1270e90, 5, 1; +L_0x12724e0 .part v0x12010b0_0, 5, 1; +L_0x1272700 .part L_0x1270e90, 6, 1; +L_0x1272860 .part v0x12010b0_0, 6, 1; +LS_0x1272950_0_0 .concat8 [ 1 1 1 1], L_0x1271220, L_0x12715c0, L_0x12718d0, L_0x1271be0; +LS_0x1272950_0_4 .concat8 [ 1 1 1 1], L_0x1271f40, L_0x1272310, L_0x1272640, L_0x12725d0; +L_0x1272950 .concat8 [ 4 4 0 0], LS_0x1272950_0_0, LS_0x1272950_0_4; +L_0x1272d10 .part L_0x1270e90, 7, 1; +L_0x1272f00 .part v0x12010b0_0, 7, 1; +S_0x107e330 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x107e540 .param/l "i" 0 4 54, +C4<00>; +L_0x1271220/d .functor AND 1, L_0x1271330, L_0x1271520, C4<1>, C4<1>; +L_0x1271220 .delay 1 (30000,30000,30000) L_0x1271220/d; +v0x107e620_0 .net *"_s0", 0 0, L_0x1271330; 1 drivers +v0x107e700_0 .net *"_s1", 0 0, L_0x1271520; 1 drivers +S_0x107e7e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x107e9f0 .param/l "i" 0 4 54, +C4<01>; +L_0x12715c0/d .functor AND 1, L_0x1271680, L_0x12717e0, C4<1>, C4<1>; +L_0x12715c0 .delay 1 (30000,30000,30000) L_0x12715c0/d; +v0x107eab0_0 .net *"_s0", 0 0, L_0x1271680; 1 drivers +v0x107eb90_0 .net *"_s1", 0 0, L_0x12717e0; 1 drivers +S_0x107ec70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x107eeb0 .param/l "i" 0 4 54, +C4<010>; +L_0x12718d0/d .functor AND 1, L_0x1271990, L_0x1271af0, C4<1>, C4<1>; +L_0x12718d0 .delay 1 (30000,30000,30000) L_0x12718d0/d; +v0x107ef50_0 .net *"_s0", 0 0, L_0x1271990; 1 drivers +v0x107f030_0 .net *"_s1", 0 0, L_0x1271af0; 1 drivers +S_0x107f110 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x107f320 .param/l "i" 0 4 54, +C4<011>; +L_0x1271be0/d .functor AND 1, L_0x1271ca0, L_0x1271e00, C4<1>, C4<1>; +L_0x1271be0 .delay 1 (30000,30000,30000) L_0x1271be0/d; +v0x107f3e0_0 .net *"_s0", 0 0, L_0x1271ca0; 1 drivers +v0x107f4c0_0 .net *"_s1", 0 0, L_0x1271e00; 1 drivers +S_0x107f5a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x107f800 .param/l "i" 0 4 54, +C4<0100>; +L_0x1271f40/d .functor AND 1, L_0x1272000, L_0x1272270, C4<1>, C4<1>; +L_0x1271f40 .delay 1 (30000,30000,30000) L_0x1271f40/d; +v0x107f8c0_0 .net *"_s0", 0 0, L_0x1272000; 1 drivers +v0x107f9a0_0 .net *"_s1", 0 0, L_0x1272270; 1 drivers +S_0x107fa80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x107fc90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1272310/d .functor AND 1, L_0x1272380, L_0x12724e0, C4<1>, C4<1>; +L_0x1272310 .delay 1 (30000,30000,30000) L_0x1272310/d; +v0x107fd50_0 .net *"_s0", 0 0, L_0x1272380; 1 drivers +v0x107fe30_0 .net *"_s1", 0 0, L_0x12724e0; 1 drivers +S_0x107ff10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x1080120 .param/l "i" 0 4 54, +C4<0110>; +L_0x1272640/d .functor AND 1, L_0x1272700, L_0x1272860, C4<1>, C4<1>; +L_0x1272640 .delay 1 (30000,30000,30000) L_0x1272640/d; +v0x10801e0_0 .net *"_s0", 0 0, L_0x1272700; 1 drivers +v0x10802c0_0 .net *"_s1", 0 0, L_0x1272860; 1 drivers +S_0x10803a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x107e0f0; + .timescale -9 -12; +P_0x10805b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12725d0/d .functor AND 1, L_0x1272d10, L_0x1272f00, C4<1>, C4<1>; +L_0x12725d0 .delay 1 (30000,30000,30000) L_0x12725d0/d; +v0x1080670_0 .net *"_s0", 0 0, L_0x1272d10; 1 drivers +v0x1080750_0 .net *"_s1", 0 0, L_0x1272f00; 1 drivers +S_0x1081310 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x107dea0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1de1200/d .functor OR 1, L_0x1de12c0, L_0x1de1470, C4<0>, C4<0>; -L_0x1de1200 .delay 1 (30000,30000,30000) L_0x1de1200/d; -v0x1bf01e0_0 .net *"_s10", 0 0, L_0x1de12c0; 1 drivers -v0x1bf02c0_0 .net *"_s12", 0 0, L_0x1de1470; 1 drivers -v0x1bf03a0_0 .net "in", 7 0, L_0x1ddf200; alias, 1 drivers -v0x1bf0470_0 .net "ors", 1 0, L_0x1de1020; 1 drivers -v0x1bf0530_0 .net "out", 0 0, L_0x1de1200; alias, 1 drivers -L_0x1de03f0 .part L_0x1ddf200, 0, 4; -L_0x1de1020 .concat8 [ 1 1 0 0], L_0x1de00e0, L_0x1de0d10; -L_0x1de1160 .part L_0x1ddf200, 4, 4; -L_0x1de12c0 .part L_0x1de1020, 0, 1; -L_0x1de1470 .part L_0x1de1020, 1, 1; -S_0x1bee850 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bee690; +L_0x1274890/d .functor OR 1, L_0x1274950, L_0x1274b00, C4<0>, C4<0>; +L_0x1274890 .delay 1 (30000,30000,30000) L_0x1274890/d; +v0x1082e60_0 .net *"_s10", 0 0, L_0x1274950; 1 drivers +v0x1082f40_0 .net *"_s12", 0 0, L_0x1274b00; 1 drivers +v0x1083020_0 .net "in", 7 0, L_0x1272950; alias, 1 drivers +v0x10830f0_0 .net "ors", 1 0, L_0x12746b0; 1 drivers +v0x10831b0_0 .net "out", 0 0, L_0x1274890; alias, 1 drivers +L_0x1273a80 .part L_0x1272950, 0, 4; +L_0x12746b0 .concat8 [ 1 1 0 0], L_0x1273770, L_0x12743a0; +L_0x12747f0 .part L_0x1272950, 4, 4; +L_0x1274950 .part L_0x12746b0, 0, 1; +L_0x1274b00 .part L_0x12746b0, 1, 1; +S_0x10814d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1081310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1ddf8a0/d .functor OR 1, L_0x1ddf960, L_0x1ddfac0, C4<0>, C4<0>; -L_0x1ddf8a0 .delay 1 (30000,30000,30000) L_0x1ddf8a0/d; -L_0x1ddfcf0/d .functor OR 1, L_0x1ddfe00, L_0x1ddff60, C4<0>, C4<0>; -L_0x1ddfcf0 .delay 1 (30000,30000,30000) L_0x1ddfcf0/d; -L_0x1de00e0/d .functor OR 1, L_0x1de0150, L_0x1de0300, C4<0>, C4<0>; -L_0x1de00e0 .delay 1 (30000,30000,30000) L_0x1de00e0/d; -v0x1beeaa0_0 .net *"_s0", 0 0, L_0x1ddf8a0; 1 drivers -v0x1beeba0_0 .net *"_s10", 0 0, L_0x1ddfe00; 1 drivers -v0x1beec80_0 .net *"_s12", 0 0, L_0x1ddff60; 1 drivers -v0x1beed40_0 .net *"_s14", 0 0, L_0x1de0150; 1 drivers -v0x1beee20_0 .net *"_s16", 0 0, L_0x1de0300; 1 drivers -v0x1beef50_0 .net *"_s3", 0 0, L_0x1ddf960; 1 drivers -v0x1bef030_0 .net *"_s5", 0 0, L_0x1ddfac0; 1 drivers -v0x1bef110_0 .net *"_s6", 0 0, L_0x1ddfcf0; 1 drivers -v0x1bef1f0_0 .net "in", 3 0, L_0x1de03f0; 1 drivers -v0x1bef360_0 .net "ors", 1 0, L_0x1ddfc00; 1 drivers -v0x1bef440_0 .net "out", 0 0, L_0x1de00e0; 1 drivers -L_0x1ddf960 .part L_0x1de03f0, 0, 1; -L_0x1ddfac0 .part L_0x1de03f0, 1, 1; -L_0x1ddfc00 .concat8 [ 1 1 0 0], L_0x1ddf8a0, L_0x1ddfcf0; -L_0x1ddfe00 .part L_0x1de03f0, 2, 1; -L_0x1ddff60 .part L_0x1de03f0, 3, 1; -L_0x1de0150 .part L_0x1ddfc00, 0, 1; -L_0x1de0300 .part L_0x1ddfc00, 1, 1; -S_0x1bef560 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bee690; +L_0x125f070/d .functor OR 1, L_0x1272ff0, L_0x1273150, C4<0>, C4<0>; +L_0x125f070 .delay 1 (30000,30000,30000) L_0x125f070/d; +L_0x1273380/d .functor OR 1, L_0x1273490, L_0x12735f0, C4<0>, C4<0>; +L_0x1273380 .delay 1 (30000,30000,30000) L_0x1273380/d; +L_0x1273770/d .functor OR 1, L_0x12737e0, L_0x1273990, C4<0>, C4<0>; +L_0x1273770 .delay 1 (30000,30000,30000) L_0x1273770/d; +v0x1081720_0 .net *"_s0", 0 0, L_0x125f070; 1 drivers +v0x1081820_0 .net *"_s10", 0 0, L_0x1273490; 1 drivers +v0x1081900_0 .net *"_s12", 0 0, L_0x12735f0; 1 drivers +v0x10819c0_0 .net *"_s14", 0 0, L_0x12737e0; 1 drivers +v0x1081aa0_0 .net *"_s16", 0 0, L_0x1273990; 1 drivers +v0x1081bd0_0 .net *"_s3", 0 0, L_0x1272ff0; 1 drivers +v0x1081cb0_0 .net *"_s5", 0 0, L_0x1273150; 1 drivers +v0x1081d90_0 .net *"_s6", 0 0, L_0x1273380; 1 drivers +v0x1081e70_0 .net "in", 3 0, L_0x1273a80; 1 drivers +v0x1081fe0_0 .net "ors", 1 0, L_0x1273290; 1 drivers +v0x10820c0_0 .net "out", 0 0, L_0x1273770; 1 drivers +L_0x1272ff0 .part L_0x1273a80, 0, 1; +L_0x1273150 .part L_0x1273a80, 1, 1; +L_0x1273290 .concat8 [ 1 1 0 0], L_0x125f070, L_0x1273380; +L_0x1273490 .part L_0x1273a80, 2, 1; +L_0x12735f0 .part L_0x1273a80, 3, 1; +L_0x12737e0 .part L_0x1273290, 0, 1; +L_0x1273990 .part L_0x1273290, 1, 1; +S_0x10821e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1081310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1de0520/d .functor OR 1, L_0x1de0590, L_0x1de06f0, C4<0>, C4<0>; -L_0x1de0520 .delay 1 (30000,30000,30000) L_0x1de0520/d; -L_0x1de0920/d .functor OR 1, L_0x1de0a30, L_0x1de0b90, C4<0>, C4<0>; -L_0x1de0920 .delay 1 (30000,30000,30000) L_0x1de0920/d; -L_0x1de0d10/d .functor OR 1, L_0x1de0d80, L_0x1de0f30, C4<0>, C4<0>; -L_0x1de0d10 .delay 1 (30000,30000,30000) L_0x1de0d10/d; -v0x1bef720_0 .net *"_s0", 0 0, L_0x1de0520; 1 drivers -v0x1bef820_0 .net *"_s10", 0 0, L_0x1de0a30; 1 drivers -v0x1bef900_0 .net *"_s12", 0 0, L_0x1de0b90; 1 drivers -v0x1bef9c0_0 .net *"_s14", 0 0, L_0x1de0d80; 1 drivers -v0x1befaa0_0 .net *"_s16", 0 0, L_0x1de0f30; 1 drivers -v0x1befbd0_0 .net *"_s3", 0 0, L_0x1de0590; 1 drivers -v0x1befcb0_0 .net *"_s5", 0 0, L_0x1de06f0; 1 drivers -v0x1befd90_0 .net *"_s6", 0 0, L_0x1de0920; 1 drivers -v0x1befe70_0 .net "in", 3 0, L_0x1de1160; 1 drivers -v0x1beffe0_0 .net "ors", 1 0, L_0x1de0830; 1 drivers -v0x1bf00c0_0 .net "out", 0 0, L_0x1de0d10; 1 drivers -L_0x1de0590 .part L_0x1de1160, 0, 1; -L_0x1de06f0 .part L_0x1de1160, 1, 1; -L_0x1de0830 .concat8 [ 1 1 0 0], L_0x1de0520, L_0x1de0920; -L_0x1de0a30 .part L_0x1de1160, 2, 1; -L_0x1de0b90 .part L_0x1de1160, 3, 1; -L_0x1de0d80 .part L_0x1de0830, 0, 1; -L_0x1de0f30 .part L_0x1de0830, 1, 1; -S_0x1bf09d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1be4350; +L_0x1273bb0/d .functor OR 1, L_0x1273c20, L_0x1273d80, C4<0>, C4<0>; +L_0x1273bb0 .delay 1 (30000,30000,30000) L_0x1273bb0/d; +L_0x1273fb0/d .functor OR 1, L_0x12740c0, L_0x1274220, C4<0>, C4<0>; +L_0x1273fb0 .delay 1 (30000,30000,30000) L_0x1273fb0/d; +L_0x12743a0/d .functor OR 1, L_0x1274410, L_0x12745c0, C4<0>, C4<0>; +L_0x12743a0 .delay 1 (30000,30000,30000) L_0x12743a0/d; +v0x10823a0_0 .net *"_s0", 0 0, L_0x1273bb0; 1 drivers +v0x10824a0_0 .net *"_s10", 0 0, L_0x12740c0; 1 drivers +v0x1082580_0 .net *"_s12", 0 0, L_0x1274220; 1 drivers +v0x1082640_0 .net *"_s14", 0 0, L_0x1274410; 1 drivers +v0x1082720_0 .net *"_s16", 0 0, L_0x12745c0; 1 drivers +v0x1082850_0 .net *"_s3", 0 0, L_0x1273c20; 1 drivers +v0x1082930_0 .net *"_s5", 0 0, L_0x1273d80; 1 drivers +v0x1082a10_0 .net *"_s6", 0 0, L_0x1273fb0; 1 drivers +v0x1082af0_0 .net "in", 3 0, L_0x12747f0; 1 drivers +v0x1082c60_0 .net "ors", 1 0, L_0x1273ec0; 1 drivers +v0x1082d40_0 .net "out", 0 0, L_0x12743a0; 1 drivers +L_0x1273c20 .part L_0x12747f0, 0, 1; +L_0x1273d80 .part L_0x12747f0, 1, 1; +L_0x1273ec0 .concat8 [ 1 1 0 0], L_0x1273bb0, L_0x1273fb0; +L_0x12740c0 .part L_0x12747f0, 2, 1; +L_0x1274220 .part L_0x12747f0, 3, 1; +L_0x1274410 .part L_0x1273ec0, 0, 1; +L_0x12745c0 .part L_0x1273ec0, 1, 1; +S_0x1083650 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1076fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -6508,80 +6518,80 @@ S_0x1bf09d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1be4350; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1ddc9d0/d .functor XNOR 1, L_0x1de50a0, L_0x1ddb670, C4<0>, C4<0>; -L_0x1ddc9d0 .delay 1 (20000,20000,20000) L_0x1ddc9d0/d; -L_0x1ddcc40/d .functor AND 1, L_0x1de50a0, L_0x1ddb980, C4<1>, C4<1>; -L_0x1ddcc40 .delay 1 (30000,30000,30000) L_0x1ddcc40/d; -L_0x1ddccb0/d .functor AND 1, L_0x1ddc9d0, L_0x1de5320, C4<1>, C4<1>; -L_0x1ddccb0 .delay 1 (30000,30000,30000) L_0x1ddccb0/d; -L_0x1ddce10/d .functor OR 1, L_0x1ddccb0, L_0x1ddcc40, C4<0>, C4<0>; -L_0x1ddce10 .delay 1 (30000,30000,30000) L_0x1ddce10/d; -v0x1bf0c80_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers -v0x1bf0d70_0 .net "a_", 0 0, L_0x1ddb820; alias, 1 drivers -v0x1bf0e30_0 .net "b", 0 0, L_0x1ddb670; alias, 1 drivers -v0x1bf0f20_0 .net "b_", 0 0, L_0x1ddb980; alias, 1 drivers -v0x1bf0fc0_0 .net "carryin", 0 0, L_0x1de5320; alias, 1 drivers -v0x1bf1100_0 .net "eq", 0 0, L_0x1ddc9d0; 1 drivers -v0x1bf11c0_0 .net "lt", 0 0, L_0x1ddcc40; 1 drivers -v0x1bf1280_0 .net "out", 0 0, L_0x1ddce10; 1 drivers -v0x1bf1340_0 .net "w0", 0 0, L_0x1ddccb0; 1 drivers -S_0x1bf1590 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1be4350; +L_0x1270200/d .functor XNOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; +L_0x1270200 .delay 1 (20000,20000,20000) L_0x1270200/d; +L_0x1270470/d .functor AND 1, L_0x1278810, L_0x126f0f0, C4<1>, C4<1>; +L_0x1270470 .delay 1 (30000,30000,30000) L_0x1270470/d; +L_0x12704e0/d .functor AND 1, L_0x1270200, L_0x1278a90, C4<1>, C4<1>; +L_0x12704e0 .delay 1 (30000,30000,30000) L_0x12704e0/d; +L_0x1270640/d .functor OR 1, L_0x12704e0, L_0x1270470, C4<0>, C4<0>; +L_0x1270640 .delay 1 (30000,30000,30000) L_0x1270640/d; +v0x1083900_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers +v0x10839f0_0 .net "a_", 0 0, L_0x126ef90; alias, 1 drivers +v0x1083ab0_0 .net "b", 0 0, L_0x126ede0; alias, 1 drivers +v0x1083ba0_0 .net "b_", 0 0, L_0x126f0f0; alias, 1 drivers +v0x1083c40_0 .net "carryin", 0 0, L_0x1278a90; alias, 1 drivers +v0x1083d80_0 .net "eq", 0 0, L_0x1270200; 1 drivers +v0x1083e40_0 .net "lt", 0 0, L_0x1270470; 1 drivers +v0x1083f00_0 .net "out", 0 0, L_0x1270640; 1 drivers +v0x1083fc0_0 .net "w0", 0 0, L_0x12704e0; 1 drivers +S_0x1084210 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1076fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1ddc7b0/d .functor OR 1, L_0x1ddc300, L_0x1bf27f0, C4<0>, C4<0>; -L_0x1ddc7b0 .delay 1 (30000,30000,30000) L_0x1ddc7b0/d; -v0x1bf2380_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers -v0x1bf24d0_0 .net "b", 0 0, L_0x1ddb980; alias, 1 drivers -v0x1bf2590_0 .net "c1", 0 0, L_0x1ddc300; 1 drivers -v0x1bf2630_0 .net "c2", 0 0, L_0x1bf27f0; 1 drivers -v0x1bf2700_0 .net "carryin", 0 0, L_0x1de5320; alias, 1 drivers -v0x1bf2880_0 .net "carryout", 0 0, L_0x1ddc7b0; 1 drivers -v0x1bf2920_0 .net "s1", 0 0, L_0x1ddc240; 1 drivers -v0x1bf29c0_0 .net "sum", 0 0, L_0x1ddc460; 1 drivers -S_0x1bf17e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bf1590; +L_0x126ffe0/d .functor OR 1, L_0x126fae0, L_0x1085410, C4<0>, C4<0>; +L_0x126ffe0 .delay 1 (30000,30000,30000) L_0x126ffe0/d; +v0x1084fe0_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers +v0x1085110_0 .net "b", 0 0, L_0x126f0f0; alias, 1 drivers +v0x10851b0_0 .net "c1", 0 0, L_0x126fae0; 1 drivers +v0x1085250_0 .net "c2", 0 0, L_0x1085410; 1 drivers +v0x1085320_0 .net "carryin", 0 0, L_0x1278a90; alias, 1 drivers +v0x10854a0_0 .net "carryout", 0 0, L_0x126ffe0; 1 drivers +v0x1085540_0 .net "s1", 0 0, L_0x126fa20; 1 drivers +v0x10855e0_0 .net "sum", 0 0, L_0x126fc40; 1 drivers +S_0x1084460 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1084210; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ddc240/d .functor XOR 1, L_0x1de50a0, L_0x1ddb980, C4<0>, C4<0>; -L_0x1ddc240 .delay 1 (30000,30000,30000) L_0x1ddc240/d; -L_0x1ddc300/d .functor AND 1, L_0x1de50a0, L_0x1ddb980, C4<1>, C4<1>; -L_0x1ddc300 .delay 1 (30000,30000,30000) L_0x1ddc300/d; -v0x1bf1a40_0 .net "a", 0 0, L_0x1de50a0; alias, 1 drivers -v0x1bf1b00_0 .net "b", 0 0, L_0x1ddb980; alias, 1 drivers -v0x1bf1bc0_0 .net "carryout", 0 0, L_0x1ddc300; alias, 1 drivers -v0x1bf1c60_0 .net "sum", 0 0, L_0x1ddc240; alias, 1 drivers -S_0x1bf1d90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bf1590; +L_0x126fa20/d .functor XOR 1, L_0x1278810, L_0x126f0f0, C4<0>, C4<0>; +L_0x126fa20 .delay 1 (30000,30000,30000) L_0x126fa20/d; +L_0x126fae0/d .functor AND 1, L_0x1278810, L_0x126f0f0, C4<1>, C4<1>; +L_0x126fae0 .delay 1 (30000,30000,30000) L_0x126fae0/d; +v0x10846c0_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers +v0x1084780_0 .net "b", 0 0, L_0x126f0f0; alias, 1 drivers +v0x1084840_0 .net "carryout", 0 0, L_0x126fae0; alias, 1 drivers +v0x10848e0_0 .net "sum", 0 0, L_0x126fa20; alias, 1 drivers +S_0x1084a10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1084210; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ddc460/d .functor XOR 1, L_0x1ddc240, L_0x1de5320, C4<0>, C4<0>; -L_0x1ddc460 .delay 1 (30000,30000,30000) L_0x1ddc460/d; -L_0x1bf27f0/d .functor AND 1, L_0x1ddc240, L_0x1de5320, C4<1>, C4<1>; -L_0x1bf27f0 .delay 1 (30000,30000,30000) L_0x1bf27f0/d; -v0x1bf1ff0_0 .net "a", 0 0, L_0x1ddc240; alias, 1 drivers -v0x1bf20c0_0 .net "b", 0 0, L_0x1de5320; alias, 1 drivers -v0x1bf2160_0 .net "carryout", 0 0, L_0x1bf27f0; alias, 1 drivers -v0x1bf2230_0 .net "sum", 0 0, L_0x1ddc460; alias, 1 drivers -S_0x1bf3de0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1be4080; - .timescale -9 -12; -L_0x7f72592dac78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dacc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1de5140/d .functor OR 1, L_0x7f72592dac78, L_0x7f72592dacc0, C4<0>, C4<0>; -L_0x1de5140 .delay 1 (30000,30000,30000) L_0x1de5140/d; -v0x1bf3fd0_0 .net/2u *"_s0", 0 0, L_0x7f72592dac78; 1 drivers -v0x1bf40b0_0 .net/2u *"_s2", 0 0, L_0x7f72592dacc0; 1 drivers -S_0x1bf4190 .scope generate, "alu_slices[12]" "alu_slices[12]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1bf43a0 .param/l "i" 0 3 37, +C4<01100>; -S_0x1bf4460 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bf4190; +L_0x126fc40/d .functor XOR 1, L_0x126fa20, L_0x1278a90, C4<0>, C4<0>; +L_0x126fc40 .delay 1 (30000,30000,30000) L_0x126fc40/d; +L_0x1085410/d .functor AND 1, L_0x126fa20, L_0x1278a90, C4<1>, C4<1>; +L_0x1085410 .delay 1 (30000,30000,30000) L_0x1085410/d; +v0x1084c70_0 .net "a", 0 0, L_0x126fa20; alias, 1 drivers +v0x1084d40_0 .net "b", 0 0, L_0x1278a90; alias, 1 drivers +v0x1084de0_0 .net "carryout", 0 0, L_0x1085410; alias, 1 drivers +v0x1084eb0_0 .net "sum", 0 0, L_0x126fc40; alias, 1 drivers +S_0x1086a60 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1076d00; + .timescale -9 -12; +L_0x2b0ab3d05c78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05cc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12788b0/d .functor OR 1, L_0x2b0ab3d05c78, L_0x2b0ab3d05cc0, C4<0>, C4<0>; +L_0x12788b0 .delay 1 (30000,30000,30000) L_0x12788b0/d; +v0x1086c50_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05c78; 1 drivers +v0x1086d30_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05cc0; 1 drivers +S_0x1086e10 .scope generate, "alu_slices[12]" "alu_slices[12]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1087020 .param/l "i" 0 3 41, +C4<01100>; +S_0x10870e0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1086e10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -6590,445 +6600,445 @@ S_0x1bf4460 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1bf4190; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1de52a0/d .functor NOT 1, L_0x1deecb0, C4<0>, C4<0>, C4<0>; -L_0x1de52a0 .delay 1 (10000,10000,10000) L_0x1de52a0/d; -L_0x1de55e0/d .functor NOT 1, L_0x1deee10, C4<0>, C4<0>, C4<0>; -L_0x1de55e0 .delay 1 (10000,10000,10000) L_0x1de55e0/d; -L_0x1de6520/d .functor XOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; -L_0x1de6520 .delay 1 (30000,30000,30000) L_0x1de6520/d; -L_0x7f72592dad08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dad50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1de6bd0/d .functor OR 1, L_0x7f72592dad08, L_0x7f72592dad50, C4<0>, C4<0>; -L_0x1de6bd0 .delay 1 (30000,30000,30000) L_0x1de6bd0/d; -L_0x1de6dd0/d .functor AND 1, L_0x1deecb0, L_0x1deee10, C4<1>, C4<1>; -L_0x1de6dd0 .delay 1 (30000,30000,30000) L_0x1de6dd0/d; -L_0x1de6e90/d .functor NAND 1, L_0x1deecb0, L_0x1deee10, C4<1>, C4<1>; -L_0x1de6e90 .delay 1 (20000,20000,20000) L_0x1de6e90/d; -L_0x1de6ff0/d .functor XOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; -L_0x1de6ff0 .delay 1 (20000,20000,20000) L_0x1de6ff0/d; -L_0x1de74a0/d .functor OR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; -L_0x1de74a0 .delay 1 (30000,30000,30000) L_0x1de74a0/d; -L_0x1deebb0/d .functor NOT 1, L_0x1deae10, C4<0>, C4<0>, C4<0>; -L_0x1deebb0 .delay 1 (10000,10000,10000) L_0x1deebb0/d; -v0x1c02b90_0 .net "A", 0 0, L_0x1deecb0; 1 drivers -v0x1c02c50_0 .net "A_", 0 0, L_0x1de52a0; 1 drivers -v0x1c02d10_0 .net "B", 0 0, L_0x1deee10; 1 drivers -v0x1c02de0_0 .net "B_", 0 0, L_0x1de55e0; 1 drivers -v0x1c02e80_0 .net *"_s12", 0 0, L_0x1de6bd0; 1 drivers -v0x1c02f70_0 .net/2s *"_s14", 0 0, L_0x7f72592dad08; 1 drivers -v0x1c03030_0 .net/2s *"_s16", 0 0, L_0x7f72592dad50; 1 drivers -v0x1c03110_0 .net *"_s18", 0 0, L_0x1de6dd0; 1 drivers -v0x1c031f0_0 .net *"_s20", 0 0, L_0x1de6e90; 1 drivers -v0x1c03360_0 .net *"_s22", 0 0, L_0x1de6ff0; 1 drivers -v0x1c03440_0 .net *"_s24", 0 0, L_0x1de74a0; 1 drivers -o0x7f7259372288 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c03520_0 name=_s30 -o0x7f72593722b8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c03600_0 name=_s32 -v0x1c036e0_0 .net *"_s8", 0 0, L_0x1de6520; 1 drivers -v0x1c037c0_0 .net "carryin", 0 0, L_0x1de53c0; 1 drivers -v0x1c03860_0 .net "carryout", 0 0, L_0x1dee850; 1 drivers -v0x1c03900_0 .net "carryouts", 7 0, L_0x1ebfeb0; 1 drivers -v0x1c03ab0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1b9d5d0_0 .net "result", 0 0, L_0x1deae10; 1 drivers -v0x1b9d6c0_0 .net "results", 7 0, L_0x1de7270; 1 drivers -v0x1b9d7d0_0 .net "zero", 0 0, L_0x1deebb0; 1 drivers -LS_0x1de7270_0_0 .concat8 [ 1 1 1 1], L_0x1de5a40, L_0x1de6070, L_0x1de6520, L_0x1de6bd0; -LS_0x1de7270_0_4 .concat8 [ 1 1 1 1], L_0x1de6dd0, L_0x1de6e90, L_0x1de6ff0, L_0x1de74a0; -L_0x1de7270 .concat8 [ 4 4 0 0], LS_0x1de7270_0_0, LS_0x1de7270_0_4; -LS_0x1ebfeb0_0_0 .concat [ 1 1 1 1], L_0x1de5cf0, L_0x1de63c0, o0x7f7259372288, L_0x1de6a20; -LS_0x1ebfeb0_0_4 .concat [ 4 0 0 0], o0x7f72593722b8; -L_0x1ebfeb0 .concat [ 4 4 0 0], LS_0x1ebfeb0_0_0, LS_0x1ebfeb0_0_4; -S_0x1bf46e0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1bf4460; +L_0x1278a10/d .functor NOT 1, L_0x1282420, C4<0>, C4<0>, C4<0>; +L_0x1278a10 .delay 1 (10000,10000,10000) L_0x1278a10/d; +L_0x1278d50/d .functor NOT 1, L_0x1282580, C4<0>, C4<0>, C4<0>; +L_0x1278d50 .delay 1 (10000,10000,10000) L_0x1278d50/d; +L_0x1279c90/d .functor XOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; +L_0x1279c90 .delay 1 (30000,30000,30000) L_0x1279c90/d; +L_0x2b0ab3d05d08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05d50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x127a340/d .functor OR 1, L_0x2b0ab3d05d08, L_0x2b0ab3d05d50, C4<0>, C4<0>; +L_0x127a340 .delay 1 (30000,30000,30000) L_0x127a340/d; +L_0x127a540/d .functor AND 1, L_0x1282420, L_0x1282580, C4<1>, C4<1>; +L_0x127a540 .delay 1 (30000,30000,30000) L_0x127a540/d; +L_0x127a600/d .functor NAND 1, L_0x1282420, L_0x1282580, C4<1>, C4<1>; +L_0x127a600 .delay 1 (20000,20000,20000) L_0x127a600/d; +L_0x127a760/d .functor XOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; +L_0x127a760 .delay 1 (20000,20000,20000) L_0x127a760/d; +L_0x127ac10/d .functor OR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; +L_0x127ac10 .delay 1 (30000,30000,30000) L_0x127ac10/d; +L_0x1282320/d .functor NOT 1, L_0x127e580, C4<0>, C4<0>, C4<0>; +L_0x1282320 .delay 1 (10000,10000,10000) L_0x1282320/d; +v0x1095810_0 .net "A", 0 0, L_0x1282420; 1 drivers +v0x10958d0_0 .net "A_", 0 0, L_0x1278a10; 1 drivers +v0x1095990_0 .net "B", 0 0, L_0x1282580; 1 drivers +v0x1095a60_0 .net "B_", 0 0, L_0x1278d50; 1 drivers +v0x1095b00_0 .net *"_s12", 0 0, L_0x127a340; 1 drivers +v0x1095bf0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05d08; 1 drivers +v0x1095cb0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05d50; 1 drivers +v0x1095d90_0 .net *"_s18", 0 0, L_0x127a540; 1 drivers +v0x1095e70_0 .net *"_s20", 0 0, L_0x127a600; 1 drivers +v0x1095fe0_0 .net *"_s22", 0 0, L_0x127a760; 1 drivers +v0x10960c0_0 .net *"_s24", 0 0, L_0x127ac10; 1 drivers +o0x2b0ab3cc1288 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10961a0_0 name=_s30 +o0x2b0ab3cc12b8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1096280_0 name=_s32 +v0x1096360_0 .net *"_s8", 0 0, L_0x1279c90; 1 drivers +v0x1096440_0 .net "carryin", 0 0, L_0x1278b30; 1 drivers +v0x10964e0_0 .net "carryout", 0 0, L_0x1281fc0; 1 drivers +v0x1096580_0 .net "carryouts", 7 0, L_0x1354220; 1 drivers +v0x1096730_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1030260_0 .net "result", 0 0, L_0x127e580; 1 drivers +v0x1030350_0 .net "results", 7 0, L_0x127a9e0; 1 drivers +v0x1030460_0 .net "zero", 0 0, L_0x1282320; 1 drivers +LS_0x127a9e0_0_0 .concat8 [ 1 1 1 1], L_0x12791b0, L_0x12797e0, L_0x1279c90, L_0x127a340; +LS_0x127a9e0_0_4 .concat8 [ 1 1 1 1], L_0x127a540, L_0x127a600, L_0x127a760, L_0x127ac10; +L_0x127a9e0 .concat8 [ 4 4 0 0], LS_0x127a9e0_0_0, LS_0x127a9e0_0_4; +LS_0x1354220_0_0 .concat [ 1 1 1 1], L_0x1279460, L_0x1279b30, o0x2b0ab3cc1288, L_0x127a190; +LS_0x1354220_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc12b8; +L_0x1354220 .concat [ 4 4 0 0], LS_0x1354220_0_0, LS_0x1354220_0_4; +S_0x1087360 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10870e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1de5cf0/d .functor OR 1, L_0x1de57d0, L_0x1de5b90, C4<0>, C4<0>; -L_0x1de5cf0 .delay 1 (30000,30000,30000) L_0x1de5cf0/d; -v0x1bf5510_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers -v0x1bf55d0_0 .net "b", 0 0, L_0x1deee10; alias, 1 drivers -v0x1bf56a0_0 .net "c1", 0 0, L_0x1de57d0; 1 drivers -v0x1bf57a0_0 .net "c2", 0 0, L_0x1de5b90; 1 drivers -v0x1bf5870_0 .net "carryin", 0 0, L_0x1de53c0; alias, 1 drivers -v0x1bf5960_0 .net "carryout", 0 0, L_0x1de5cf0; 1 drivers -v0x1bf5a00_0 .net "s1", 0 0, L_0x1ddf180; 1 drivers -v0x1bf5af0_0 .net "sum", 0 0, L_0x1de5a40; 1 drivers -S_0x1bf4950 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1bf46e0; +L_0x1279460/d .functor OR 1, L_0x1278f40, L_0x1279300, C4<0>, C4<0>; +L_0x1279460 .delay 1 (30000,30000,30000) L_0x1279460/d; +v0x1088190_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers +v0x1088250_0 .net "b", 0 0, L_0x1282580; alias, 1 drivers +v0x1088320_0 .net "c1", 0 0, L_0x1278f40; 1 drivers +v0x1088420_0 .net "c2", 0 0, L_0x1279300; 1 drivers +v0x10884f0_0 .net "carryin", 0 0, L_0x1278b30; alias, 1 drivers +v0x10885e0_0 .net "carryout", 0 0, L_0x1279460; 1 drivers +v0x1088680_0 .net "s1", 0 0, L_0x1276330; 1 drivers +v0x1088770_0 .net "sum", 0 0, L_0x12791b0; 1 drivers +S_0x10875d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1087360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ddf180/d .functor XOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; -L_0x1ddf180 .delay 1 (30000,30000,30000) L_0x1ddf180/d; -L_0x1de57d0/d .functor AND 1, L_0x1deecb0, L_0x1deee10, C4<1>, C4<1>; -L_0x1de57d0 .delay 1 (30000,30000,30000) L_0x1de57d0/d; -v0x1bf4bb0_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers -v0x1bf4c90_0 .net "b", 0 0, L_0x1deee10; alias, 1 drivers -v0x1bf4d50_0 .net "carryout", 0 0, L_0x1de57d0; alias, 1 drivers -v0x1bf4df0_0 .net "sum", 0 0, L_0x1ddf180; alias, 1 drivers -S_0x1bf4f30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1bf46e0; +L_0x1276330/d .functor XOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; +L_0x1276330 .delay 1 (30000,30000,30000) L_0x1276330/d; +L_0x1278f40/d .functor AND 1, L_0x1282420, L_0x1282580, C4<1>, C4<1>; +L_0x1278f40 .delay 1 (30000,30000,30000) L_0x1278f40/d; +v0x1087830_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers +v0x1087910_0 .net "b", 0 0, L_0x1282580; alias, 1 drivers +v0x10879d0_0 .net "carryout", 0 0, L_0x1278f40; alias, 1 drivers +v0x1087a70_0 .net "sum", 0 0, L_0x1276330; alias, 1 drivers +S_0x1087bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1087360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1de5a40/d .functor XOR 1, L_0x1ddf180, L_0x1de53c0, C4<0>, C4<0>; -L_0x1de5a40 .delay 1 (30000,30000,30000) L_0x1de5a40/d; -L_0x1de5b90/d .functor AND 1, L_0x1ddf180, L_0x1de53c0, C4<1>, C4<1>; -L_0x1de5b90 .delay 1 (30000,30000,30000) L_0x1de5b90/d; -v0x1bf5190_0 .net "a", 0 0, L_0x1ddf180; alias, 1 drivers -v0x1bf5230_0 .net "b", 0 0, L_0x1de53c0; alias, 1 drivers -v0x1bf52d0_0 .net "carryout", 0 0, L_0x1de5b90; alias, 1 drivers -v0x1bf53a0_0 .net "sum", 0 0, L_0x1de5a40; alias, 1 drivers -S_0x1bf5bc0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1bf4460; +L_0x12791b0/d .functor XOR 1, L_0x1276330, L_0x1278b30, C4<0>, C4<0>; +L_0x12791b0 .delay 1 (30000,30000,30000) L_0x12791b0/d; +L_0x1279300/d .functor AND 1, L_0x1276330, L_0x1278b30, C4<1>, C4<1>; +L_0x1279300 .delay 1 (30000,30000,30000) L_0x1279300/d; +v0x1087e10_0 .net "a", 0 0, L_0x1276330; alias, 1 drivers +v0x1087eb0_0 .net "b", 0 0, L_0x1278b30; alias, 1 drivers +v0x1087f50_0 .net "carryout", 0 0, L_0x1279300; alias, 1 drivers +v0x1088020_0 .net "sum", 0 0, L_0x12791b0; alias, 1 drivers +S_0x1088840 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10870e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1bfafb0_0 .net "ands", 7 0, L_0x1dec850; 1 drivers -v0x1bfb0c0_0 .net "in", 7 0, L_0x1ebfeb0; alias, 1 drivers -v0x1bfb180_0 .net "out", 0 0, L_0x1dee850; alias, 1 drivers -v0x1bfb250_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bf5de0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bf5bc0; +v0x108dc30_0 .net "ands", 7 0, L_0x127ffc0; 1 drivers +v0x108dd40_0 .net "in", 7 0, L_0x1354220; alias, 1 drivers +v0x108de00_0 .net "out", 0 0, L_0x1281fc0; alias, 1 drivers +v0x108ded0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1088a60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1088840; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bf8510_0 .net "A", 7 0, L_0x1ebfeb0; alias, 1 drivers -v0x1bf8610_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bf86d0_0 .net *"_s0", 0 0, L_0x1deb170; 1 drivers -v0x1bf8790_0 .net *"_s12", 0 0, L_0x1debae0; 1 drivers -v0x1bf8870_0 .net *"_s16", 0 0, L_0x1debe40; 1 drivers -v0x1bf89a0_0 .net *"_s20", 0 0, L_0x1dec150; 1 drivers -v0x1bf8a80_0 .net *"_s24", 0 0, L_0x1dec540; 1 drivers -v0x1bf8b60_0 .net *"_s28", 0 0, L_0x1dec4d0; 1 drivers -v0x1bf8c40_0 .net *"_s4", 0 0, L_0x1deb480; 1 drivers -v0x1bf8db0_0 .net *"_s8", 0 0, L_0x1deb7d0; 1 drivers -v0x1bf8e90_0 .net "out", 7 0, L_0x1dec850; alias, 1 drivers -L_0x1deb230 .part L_0x1ebfeb0, 0, 1; -L_0x1deb390 .part v0x1d6daa0_0, 0, 1; -L_0x1deb540 .part L_0x1ebfeb0, 1, 1; -L_0x1deb730 .part v0x1d6daa0_0, 1, 1; -L_0x1deb890 .part L_0x1ebfeb0, 2, 1; -L_0x1deb9f0 .part v0x1d6daa0_0, 2, 1; -L_0x1debba0 .part L_0x1ebfeb0, 3, 1; -L_0x1debd00 .part v0x1d6daa0_0, 3, 1; -L_0x1debf00 .part L_0x1ebfeb0, 4, 1; -L_0x1dec060 .part v0x1d6daa0_0, 4, 1; -L_0x1dec1c0 .part L_0x1ebfeb0, 5, 1; -L_0x1dec430 .part v0x1d6daa0_0, 5, 1; -L_0x1dec600 .part L_0x1ebfeb0, 6, 1; -L_0x1dec760 .part v0x1d6daa0_0, 6, 1; -LS_0x1dec850_0_0 .concat8 [ 1 1 1 1], L_0x1deb170, L_0x1deb480, L_0x1deb7d0, L_0x1debae0; -LS_0x1dec850_0_4 .concat8 [ 1 1 1 1], L_0x1debe40, L_0x1dec150, L_0x1dec540, L_0x1dec4d0; -L_0x1dec850 .concat8 [ 4 4 0 0], LS_0x1dec850_0_0, LS_0x1dec850_0_4; -L_0x1decc10 .part L_0x1ebfeb0, 7, 1; -L_0x1dece00 .part v0x1d6daa0_0, 7, 1; -S_0x1bf6040 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf6250 .param/l "i" 0 4 54, +C4<00>; -L_0x1deb170/d .functor AND 1, L_0x1deb230, L_0x1deb390, C4<1>, C4<1>; -L_0x1deb170 .delay 1 (30000,30000,30000) L_0x1deb170/d; -v0x1bf6330_0 .net *"_s0", 0 0, L_0x1deb230; 1 drivers -v0x1bf6410_0 .net *"_s1", 0 0, L_0x1deb390; 1 drivers -S_0x1bf64f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf6700 .param/l "i" 0 4 54, +C4<01>; -L_0x1deb480/d .functor AND 1, L_0x1deb540, L_0x1deb730, C4<1>, C4<1>; -L_0x1deb480 .delay 1 (30000,30000,30000) L_0x1deb480/d; -v0x1bf67c0_0 .net *"_s0", 0 0, L_0x1deb540; 1 drivers -v0x1bf68a0_0 .net *"_s1", 0 0, L_0x1deb730; 1 drivers -S_0x1bf6980 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf6b90 .param/l "i" 0 4 54, +C4<010>; -L_0x1deb7d0/d .functor AND 1, L_0x1deb890, L_0x1deb9f0, C4<1>, C4<1>; -L_0x1deb7d0 .delay 1 (30000,30000,30000) L_0x1deb7d0/d; -v0x1bf6c30_0 .net *"_s0", 0 0, L_0x1deb890; 1 drivers -v0x1bf6d10_0 .net *"_s1", 0 0, L_0x1deb9f0; 1 drivers -S_0x1bf6df0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf7000 .param/l "i" 0 4 54, +C4<011>; -L_0x1debae0/d .functor AND 1, L_0x1debba0, L_0x1debd00, C4<1>, C4<1>; -L_0x1debae0 .delay 1 (30000,30000,30000) L_0x1debae0/d; -v0x1bf70c0_0 .net *"_s0", 0 0, L_0x1debba0; 1 drivers -v0x1bf71a0_0 .net *"_s1", 0 0, L_0x1debd00; 1 drivers -S_0x1bf7280 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf74e0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1debe40/d .functor AND 1, L_0x1debf00, L_0x1dec060, C4<1>, C4<1>; -L_0x1debe40 .delay 1 (30000,30000,30000) L_0x1debe40/d; -v0x1bf75a0_0 .net *"_s0", 0 0, L_0x1debf00; 1 drivers -v0x1bf7680_0 .net *"_s1", 0 0, L_0x1dec060; 1 drivers -S_0x1bf7760 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf7970 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dec150/d .functor AND 1, L_0x1dec1c0, L_0x1dec430, C4<1>, C4<1>; -L_0x1dec150 .delay 1 (30000,30000,30000) L_0x1dec150/d; -v0x1bf7a30_0 .net *"_s0", 0 0, L_0x1dec1c0; 1 drivers -v0x1bf7b10_0 .net *"_s1", 0 0, L_0x1dec430; 1 drivers -S_0x1bf7bf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf7e00 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dec540/d .functor AND 1, L_0x1dec600, L_0x1dec760, C4<1>, C4<1>; -L_0x1dec540 .delay 1 (30000,30000,30000) L_0x1dec540/d; -v0x1bf7ec0_0 .net *"_s0", 0 0, L_0x1dec600; 1 drivers -v0x1bf7fa0_0 .net *"_s1", 0 0, L_0x1dec760; 1 drivers -S_0x1bf8080 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bf5de0; - .timescale -9 -12; -P_0x1bf8290 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dec4d0/d .functor AND 1, L_0x1decc10, L_0x1dece00, C4<1>, C4<1>; -L_0x1dec4d0 .delay 1 (30000,30000,30000) L_0x1dec4d0/d; -v0x1bf8350_0 .net *"_s0", 0 0, L_0x1decc10; 1 drivers -v0x1bf8430_0 .net *"_s1", 0 0, L_0x1dece00; 1 drivers -S_0x1bf8ff0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bf5bc0; +v0x108b190_0 .net "A", 7 0, L_0x1354220; alias, 1 drivers +v0x108b290_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x108b350_0 .net *"_s0", 0 0, L_0x127e8e0; 1 drivers +v0x108b410_0 .net *"_s12", 0 0, L_0x127f250; 1 drivers +v0x108b4f0_0 .net *"_s16", 0 0, L_0x127f5b0; 1 drivers +v0x108b620_0 .net *"_s20", 0 0, L_0x127f8c0; 1 drivers +v0x108b700_0 .net *"_s24", 0 0, L_0x127fcb0; 1 drivers +v0x108b7e0_0 .net *"_s28", 0 0, L_0x127fc40; 1 drivers +v0x108b8c0_0 .net *"_s4", 0 0, L_0x127ebf0; 1 drivers +v0x108ba30_0 .net *"_s8", 0 0, L_0x127ef40; 1 drivers +v0x108bb10_0 .net "out", 7 0, L_0x127ffc0; alias, 1 drivers +L_0x127e9a0 .part L_0x1354220, 0, 1; +L_0x127eb00 .part v0x12010b0_0, 0, 1; +L_0x127ecb0 .part L_0x1354220, 1, 1; +L_0x127eea0 .part v0x12010b0_0, 1, 1; +L_0x127f000 .part L_0x1354220, 2, 1; +L_0x127f160 .part v0x12010b0_0, 2, 1; +L_0x127f310 .part L_0x1354220, 3, 1; +L_0x127f470 .part v0x12010b0_0, 3, 1; +L_0x127f670 .part L_0x1354220, 4, 1; +L_0x127f7d0 .part v0x12010b0_0, 4, 1; +L_0x127f930 .part L_0x1354220, 5, 1; +L_0x127fba0 .part v0x12010b0_0, 5, 1; +L_0x127fd70 .part L_0x1354220, 6, 1; +L_0x127fed0 .part v0x12010b0_0, 6, 1; +LS_0x127ffc0_0_0 .concat8 [ 1 1 1 1], L_0x127e8e0, L_0x127ebf0, L_0x127ef40, L_0x127f250; +LS_0x127ffc0_0_4 .concat8 [ 1 1 1 1], L_0x127f5b0, L_0x127f8c0, L_0x127fcb0, L_0x127fc40; +L_0x127ffc0 .concat8 [ 4 4 0 0], LS_0x127ffc0_0_0, LS_0x127ffc0_0_4; +L_0x1280380 .part L_0x1354220, 7, 1; +L_0x1280570 .part v0x12010b0_0, 7, 1; +S_0x1088cc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x1088ed0 .param/l "i" 0 4 54, +C4<00>; +L_0x127e8e0/d .functor AND 1, L_0x127e9a0, L_0x127eb00, C4<1>, C4<1>; +L_0x127e8e0 .delay 1 (30000,30000,30000) L_0x127e8e0/d; +v0x1088fb0_0 .net *"_s0", 0 0, L_0x127e9a0; 1 drivers +v0x1089090_0 .net *"_s1", 0 0, L_0x127eb00; 1 drivers +S_0x1089170 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x1089380 .param/l "i" 0 4 54, +C4<01>; +L_0x127ebf0/d .functor AND 1, L_0x127ecb0, L_0x127eea0, C4<1>, C4<1>; +L_0x127ebf0 .delay 1 (30000,30000,30000) L_0x127ebf0/d; +v0x1089440_0 .net *"_s0", 0 0, L_0x127ecb0; 1 drivers +v0x1089520_0 .net *"_s1", 0 0, L_0x127eea0; 1 drivers +S_0x1089600 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x1089810 .param/l "i" 0 4 54, +C4<010>; +L_0x127ef40/d .functor AND 1, L_0x127f000, L_0x127f160, C4<1>, C4<1>; +L_0x127ef40 .delay 1 (30000,30000,30000) L_0x127ef40/d; +v0x10898b0_0 .net *"_s0", 0 0, L_0x127f000; 1 drivers +v0x1089990_0 .net *"_s1", 0 0, L_0x127f160; 1 drivers +S_0x1089a70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x1089c80 .param/l "i" 0 4 54, +C4<011>; +L_0x127f250/d .functor AND 1, L_0x127f310, L_0x127f470, C4<1>, C4<1>; +L_0x127f250 .delay 1 (30000,30000,30000) L_0x127f250/d; +v0x1089d40_0 .net *"_s0", 0 0, L_0x127f310; 1 drivers +v0x1089e20_0 .net *"_s1", 0 0, L_0x127f470; 1 drivers +S_0x1089f00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x108a160 .param/l "i" 0 4 54, +C4<0100>; +L_0x127f5b0/d .functor AND 1, L_0x127f670, L_0x127f7d0, C4<1>, C4<1>; +L_0x127f5b0 .delay 1 (30000,30000,30000) L_0x127f5b0/d; +v0x108a220_0 .net *"_s0", 0 0, L_0x127f670; 1 drivers +v0x108a300_0 .net *"_s1", 0 0, L_0x127f7d0; 1 drivers +S_0x108a3e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x108a5f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x127f8c0/d .functor AND 1, L_0x127f930, L_0x127fba0, C4<1>, C4<1>; +L_0x127f8c0 .delay 1 (30000,30000,30000) L_0x127f8c0/d; +v0x108a6b0_0 .net *"_s0", 0 0, L_0x127f930; 1 drivers +v0x108a790_0 .net *"_s1", 0 0, L_0x127fba0; 1 drivers +S_0x108a870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x108aa80 .param/l "i" 0 4 54, +C4<0110>; +L_0x127fcb0/d .functor AND 1, L_0x127fd70, L_0x127fed0, C4<1>, C4<1>; +L_0x127fcb0 .delay 1 (30000,30000,30000) L_0x127fcb0/d; +v0x108ab40_0 .net *"_s0", 0 0, L_0x127fd70; 1 drivers +v0x108ac20_0 .net *"_s1", 0 0, L_0x127fed0; 1 drivers +S_0x108ad00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1088a60; + .timescale -9 -12; +P_0x108af10 .param/l "i" 0 4 54, +C4<0111>; +L_0x127fc40/d .functor AND 1, L_0x1280380, L_0x1280570, C4<1>, C4<1>; +L_0x127fc40 .delay 1 (30000,30000,30000) L_0x127fc40/d; +v0x108afd0_0 .net *"_s0", 0 0, L_0x1280380; 1 drivers +v0x108b0b0_0 .net *"_s1", 0 0, L_0x1280570; 1 drivers +S_0x108bc70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1088840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dee850/d .functor OR 1, L_0x1dee910, L_0x1deeac0, C4<0>, C4<0>; -L_0x1dee850 .delay 1 (30000,30000,30000) L_0x1dee850/d; -v0x1bfab40_0 .net *"_s10", 0 0, L_0x1dee910; 1 drivers -v0x1bfac20_0 .net *"_s12", 0 0, L_0x1deeac0; 1 drivers -v0x1bfad00_0 .net "in", 7 0, L_0x1dec850; alias, 1 drivers -v0x1bfadd0_0 .net "ors", 1 0, L_0x1dee670; 1 drivers -v0x1bfae90_0 .net "out", 0 0, L_0x1dee850; alias, 1 drivers -L_0x1deda40 .part L_0x1dec850, 0, 4; -L_0x1dee670 .concat8 [ 1 1 0 0], L_0x1ded730, L_0x1dee360; -L_0x1dee7b0 .part L_0x1dec850, 4, 4; -L_0x1dee910 .part L_0x1dee670, 0, 1; -L_0x1deeac0 .part L_0x1dee670, 1, 1; -S_0x1bf91b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bf8ff0; +L_0x1281fc0/d .functor OR 1, L_0x1282080, L_0x1282230, C4<0>, C4<0>; +L_0x1281fc0 .delay 1 (30000,30000,30000) L_0x1281fc0/d; +v0x108d7c0_0 .net *"_s10", 0 0, L_0x1282080; 1 drivers +v0x108d8a0_0 .net *"_s12", 0 0, L_0x1282230; 1 drivers +v0x108d980_0 .net "in", 7 0, L_0x127ffc0; alias, 1 drivers +v0x108da50_0 .net "ors", 1 0, L_0x1281de0; 1 drivers +v0x108db10_0 .net "out", 0 0, L_0x1281fc0; alias, 1 drivers +L_0x12811b0 .part L_0x127ffc0, 0, 4; +L_0x1281de0 .concat8 [ 1 1 0 0], L_0x1280ea0, L_0x1281ad0; +L_0x1281f20 .part L_0x127ffc0, 4, 4; +L_0x1282080 .part L_0x1281de0, 0, 1; +L_0x1282230 .part L_0x1281de0, 1, 1; +S_0x108be30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x108bc70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1decef0/d .functor OR 1, L_0x1decfb0, L_0x1ded110, C4<0>, C4<0>; -L_0x1decef0 .delay 1 (30000,30000,30000) L_0x1decef0/d; -L_0x1ded340/d .functor OR 1, L_0x1ded450, L_0x1ded5b0, C4<0>, C4<0>; -L_0x1ded340 .delay 1 (30000,30000,30000) L_0x1ded340/d; -L_0x1ded730/d .functor OR 1, L_0x1ded7a0, L_0x1ded950, C4<0>, C4<0>; -L_0x1ded730 .delay 1 (30000,30000,30000) L_0x1ded730/d; -v0x1bf9400_0 .net *"_s0", 0 0, L_0x1decef0; 1 drivers -v0x1bf9500_0 .net *"_s10", 0 0, L_0x1ded450; 1 drivers -v0x1bf95e0_0 .net *"_s12", 0 0, L_0x1ded5b0; 1 drivers -v0x1bf96a0_0 .net *"_s14", 0 0, L_0x1ded7a0; 1 drivers -v0x1bf9780_0 .net *"_s16", 0 0, L_0x1ded950; 1 drivers -v0x1bf98b0_0 .net *"_s3", 0 0, L_0x1decfb0; 1 drivers -v0x1bf9990_0 .net *"_s5", 0 0, L_0x1ded110; 1 drivers -v0x1bf9a70_0 .net *"_s6", 0 0, L_0x1ded340; 1 drivers -v0x1bf9b50_0 .net "in", 3 0, L_0x1deda40; 1 drivers -v0x1bf9cc0_0 .net "ors", 1 0, L_0x1ded250; 1 drivers -v0x1bf9da0_0 .net "out", 0 0, L_0x1ded730; 1 drivers -L_0x1decfb0 .part L_0x1deda40, 0, 1; -L_0x1ded110 .part L_0x1deda40, 1, 1; -L_0x1ded250 .concat8 [ 1 1 0 0], L_0x1decef0, L_0x1ded340; -L_0x1ded450 .part L_0x1deda40, 2, 1; -L_0x1ded5b0 .part L_0x1deda40, 3, 1; -L_0x1ded7a0 .part L_0x1ded250, 0, 1; -L_0x1ded950 .part L_0x1ded250, 1, 1; -S_0x1bf9ec0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bf8ff0; +L_0x1280660/d .functor OR 1, L_0x1280720, L_0x1280880, C4<0>, C4<0>; +L_0x1280660 .delay 1 (30000,30000,30000) L_0x1280660/d; +L_0x1280ab0/d .functor OR 1, L_0x1280bc0, L_0x1280d20, C4<0>, C4<0>; +L_0x1280ab0 .delay 1 (30000,30000,30000) L_0x1280ab0/d; +L_0x1280ea0/d .functor OR 1, L_0x1280f10, L_0x12810c0, C4<0>, C4<0>; +L_0x1280ea0 .delay 1 (30000,30000,30000) L_0x1280ea0/d; +v0x108c080_0 .net *"_s0", 0 0, L_0x1280660; 1 drivers +v0x108c180_0 .net *"_s10", 0 0, L_0x1280bc0; 1 drivers +v0x108c260_0 .net *"_s12", 0 0, L_0x1280d20; 1 drivers +v0x108c320_0 .net *"_s14", 0 0, L_0x1280f10; 1 drivers +v0x108c400_0 .net *"_s16", 0 0, L_0x12810c0; 1 drivers +v0x108c530_0 .net *"_s3", 0 0, L_0x1280720; 1 drivers +v0x108c610_0 .net *"_s5", 0 0, L_0x1280880; 1 drivers +v0x108c6f0_0 .net *"_s6", 0 0, L_0x1280ab0; 1 drivers +v0x108c7d0_0 .net "in", 3 0, L_0x12811b0; 1 drivers +v0x108c940_0 .net "ors", 1 0, L_0x12809c0; 1 drivers +v0x108ca20_0 .net "out", 0 0, L_0x1280ea0; 1 drivers +L_0x1280720 .part L_0x12811b0, 0, 1; +L_0x1280880 .part L_0x12811b0, 1, 1; +L_0x12809c0 .concat8 [ 1 1 0 0], L_0x1280660, L_0x1280ab0; +L_0x1280bc0 .part L_0x12811b0, 2, 1; +L_0x1280d20 .part L_0x12811b0, 3, 1; +L_0x1280f10 .part L_0x12809c0, 0, 1; +L_0x12810c0 .part L_0x12809c0, 1, 1; +S_0x108cb40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x108bc70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dedb70/d .functor OR 1, L_0x1dedbe0, L_0x1dedd40, C4<0>, C4<0>; -L_0x1dedb70 .delay 1 (30000,30000,30000) L_0x1dedb70/d; -L_0x1dedf70/d .functor OR 1, L_0x1dee080, L_0x1dee1e0, C4<0>, C4<0>; -L_0x1dedf70 .delay 1 (30000,30000,30000) L_0x1dedf70/d; -L_0x1dee360/d .functor OR 1, L_0x1dee3d0, L_0x1dee580, C4<0>, C4<0>; -L_0x1dee360 .delay 1 (30000,30000,30000) L_0x1dee360/d; -v0x1bfa080_0 .net *"_s0", 0 0, L_0x1dedb70; 1 drivers -v0x1bfa180_0 .net *"_s10", 0 0, L_0x1dee080; 1 drivers -v0x1bfa260_0 .net *"_s12", 0 0, L_0x1dee1e0; 1 drivers -v0x1bfa320_0 .net *"_s14", 0 0, L_0x1dee3d0; 1 drivers -v0x1bfa400_0 .net *"_s16", 0 0, L_0x1dee580; 1 drivers -v0x1bfa530_0 .net *"_s3", 0 0, L_0x1dedbe0; 1 drivers -v0x1bfa610_0 .net *"_s5", 0 0, L_0x1dedd40; 1 drivers -v0x1bfa6f0_0 .net *"_s6", 0 0, L_0x1dedf70; 1 drivers -v0x1bfa7d0_0 .net "in", 3 0, L_0x1dee7b0; 1 drivers -v0x1bfa940_0 .net "ors", 1 0, L_0x1dede80; 1 drivers -v0x1bfaa20_0 .net "out", 0 0, L_0x1dee360; 1 drivers -L_0x1dedbe0 .part L_0x1dee7b0, 0, 1; -L_0x1dedd40 .part L_0x1dee7b0, 1, 1; -L_0x1dede80 .concat8 [ 1 1 0 0], L_0x1dedb70, L_0x1dedf70; -L_0x1dee080 .part L_0x1dee7b0, 2, 1; -L_0x1dee1e0 .part L_0x1dee7b0, 3, 1; -L_0x1dee3d0 .part L_0x1dede80, 0, 1; -L_0x1dee580 .part L_0x1dede80, 1, 1; -S_0x1bfb330 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1bf4460; +L_0x12812e0/d .functor OR 1, L_0x1281350, L_0x12814b0, C4<0>, C4<0>; +L_0x12812e0 .delay 1 (30000,30000,30000) L_0x12812e0/d; +L_0x12816e0/d .functor OR 1, L_0x12817f0, L_0x1281950, C4<0>, C4<0>; +L_0x12816e0 .delay 1 (30000,30000,30000) L_0x12816e0/d; +L_0x1281ad0/d .functor OR 1, L_0x1281b40, L_0x1281cf0, C4<0>, C4<0>; +L_0x1281ad0 .delay 1 (30000,30000,30000) L_0x1281ad0/d; +v0x108cd00_0 .net *"_s0", 0 0, L_0x12812e0; 1 drivers +v0x108ce00_0 .net *"_s10", 0 0, L_0x12817f0; 1 drivers +v0x108cee0_0 .net *"_s12", 0 0, L_0x1281950; 1 drivers +v0x108cfa0_0 .net *"_s14", 0 0, L_0x1281b40; 1 drivers +v0x108d080_0 .net *"_s16", 0 0, L_0x1281cf0; 1 drivers +v0x108d1b0_0 .net *"_s3", 0 0, L_0x1281350; 1 drivers +v0x108d290_0 .net *"_s5", 0 0, L_0x12814b0; 1 drivers +v0x108d370_0 .net *"_s6", 0 0, L_0x12816e0; 1 drivers +v0x108d450_0 .net "in", 3 0, L_0x1281f20; 1 drivers +v0x108d5c0_0 .net "ors", 1 0, L_0x12815f0; 1 drivers +v0x108d6a0_0 .net "out", 0 0, L_0x1281ad0; 1 drivers +L_0x1281350 .part L_0x1281f20, 0, 1; +L_0x12814b0 .part L_0x1281f20, 1, 1; +L_0x12815f0 .concat8 [ 1 1 0 0], L_0x12812e0, L_0x12816e0; +L_0x12817f0 .part L_0x1281f20, 2, 1; +L_0x1281950 .part L_0x1281f20, 3, 1; +L_0x1281b40 .part L_0x12815f0, 0, 1; +L_0x1281cf0 .part L_0x12815f0, 1, 1; +S_0x108dfb0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10870e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c00760_0 .net "ands", 7 0, L_0x1de8e10; 1 drivers -v0x1c00870_0 .net "in", 7 0, L_0x1de7270; alias, 1 drivers -v0x1c00930_0 .net "out", 0 0, L_0x1deae10; alias, 1 drivers -v0x1c00a00_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1bfb580 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1bfb330; +v0x10933e0_0 .net "ands", 7 0, L_0x127c580; 1 drivers +v0x10934f0_0 .net "in", 7 0, L_0x127a9e0; alias, 1 drivers +v0x10935b0_0 .net "out", 0 0, L_0x127e580; alias, 1 drivers +v0x1093680_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x108e200 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x108dfb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1bfdcc0_0 .net "A", 7 0, L_0x1de7270; alias, 1 drivers -v0x1bfddc0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1bfde80_0 .net *"_s0", 0 0, L_0x1de7600; 1 drivers -v0x1bfdf40_0 .net *"_s12", 0 0, L_0x1de7fc0; 1 drivers -v0x1bfe020_0 .net *"_s16", 0 0, L_0x1de8320; 1 drivers -v0x1bfe150_0 .net *"_s20", 0 0, L_0x1de8750; 1 drivers -v0x1bfe230_0 .net *"_s24", 0 0, L_0x1de8a80; 1 drivers -v0x1bfe310_0 .net *"_s28", 0 0, L_0x1de8a10; 1 drivers -v0x1bfe3f0_0 .net *"_s4", 0 0, L_0x1de79a0; 1 drivers -v0x1bfe560_0 .net *"_s8", 0 0, L_0x1de7cb0; 1 drivers -v0x1bfe640_0 .net "out", 7 0, L_0x1de8e10; alias, 1 drivers -L_0x1de7710 .part L_0x1de7270, 0, 1; -L_0x1de7900 .part v0x1d6daa0_0, 0, 1; -L_0x1de7a60 .part L_0x1de7270, 1, 1; -L_0x1de7bc0 .part v0x1d6daa0_0, 1, 1; -L_0x1de7d70 .part L_0x1de7270, 2, 1; -L_0x1de7ed0 .part v0x1d6daa0_0, 2, 1; -L_0x1de8080 .part L_0x1de7270, 3, 1; -L_0x1de81e0 .part v0x1d6daa0_0, 3, 1; -L_0x1de83e0 .part L_0x1de7270, 4, 1; -L_0x1de8650 .part v0x1d6daa0_0, 4, 1; -L_0x1de87c0 .part L_0x1de7270, 5, 1; -L_0x1de8920 .part v0x1d6daa0_0, 5, 1; -L_0x1de8b40 .part L_0x1de7270, 6, 1; -L_0x1de8ca0 .part v0x1d6daa0_0, 6, 1; -LS_0x1de8e10_0_0 .concat8 [ 1 1 1 1], L_0x1de7600, L_0x1de79a0, L_0x1de7cb0, L_0x1de7fc0; -LS_0x1de8e10_0_4 .concat8 [ 1 1 1 1], L_0x1de8320, L_0x1de8750, L_0x1de8a80, L_0x1de8a10; -L_0x1de8e10 .concat8 [ 4 4 0 0], LS_0x1de8e10_0_0, LS_0x1de8e10_0_4; -L_0x1de91d0 .part L_0x1de7270, 7, 1; -L_0x1de93c0 .part v0x1d6daa0_0, 7, 1; -S_0x1bfb7c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfb9d0 .param/l "i" 0 4 54, +C4<00>; -L_0x1de7600/d .functor AND 1, L_0x1de7710, L_0x1de7900, C4<1>, C4<1>; -L_0x1de7600 .delay 1 (30000,30000,30000) L_0x1de7600/d; -v0x1bfbab0_0 .net *"_s0", 0 0, L_0x1de7710; 1 drivers -v0x1bfbb90_0 .net *"_s1", 0 0, L_0x1de7900; 1 drivers -S_0x1bfbc70 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfbe80 .param/l "i" 0 4 54, +C4<01>; -L_0x1de79a0/d .functor AND 1, L_0x1de7a60, L_0x1de7bc0, C4<1>, C4<1>; -L_0x1de79a0 .delay 1 (30000,30000,30000) L_0x1de79a0/d; -v0x1bfbf40_0 .net *"_s0", 0 0, L_0x1de7a60; 1 drivers -v0x1bfc020_0 .net *"_s1", 0 0, L_0x1de7bc0; 1 drivers -S_0x1bfc100 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfc340 .param/l "i" 0 4 54, +C4<010>; -L_0x1de7cb0/d .functor AND 1, L_0x1de7d70, L_0x1de7ed0, C4<1>, C4<1>; -L_0x1de7cb0 .delay 1 (30000,30000,30000) L_0x1de7cb0/d; -v0x1bfc3e0_0 .net *"_s0", 0 0, L_0x1de7d70; 1 drivers -v0x1bfc4c0_0 .net *"_s1", 0 0, L_0x1de7ed0; 1 drivers -S_0x1bfc5a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfc7b0 .param/l "i" 0 4 54, +C4<011>; -L_0x1de7fc0/d .functor AND 1, L_0x1de8080, L_0x1de81e0, C4<1>, C4<1>; -L_0x1de7fc0 .delay 1 (30000,30000,30000) L_0x1de7fc0/d; -v0x1bfc870_0 .net *"_s0", 0 0, L_0x1de8080; 1 drivers -v0x1bfc950_0 .net *"_s1", 0 0, L_0x1de81e0; 1 drivers -S_0x1bfca30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfcc90 .param/l "i" 0 4 54, +C4<0100>; -L_0x1de8320/d .functor AND 1, L_0x1de83e0, L_0x1de8650, C4<1>, C4<1>; -L_0x1de8320 .delay 1 (30000,30000,30000) L_0x1de8320/d; -v0x1bfcd50_0 .net *"_s0", 0 0, L_0x1de83e0; 1 drivers -v0x1bfce30_0 .net *"_s1", 0 0, L_0x1de8650; 1 drivers -S_0x1bfcf10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfd120 .param/l "i" 0 4 54, +C4<0101>; -L_0x1de8750/d .functor AND 1, L_0x1de87c0, L_0x1de8920, C4<1>, C4<1>; -L_0x1de8750 .delay 1 (30000,30000,30000) L_0x1de8750/d; -v0x1bfd1e0_0 .net *"_s0", 0 0, L_0x1de87c0; 1 drivers -v0x1bfd2c0_0 .net *"_s1", 0 0, L_0x1de8920; 1 drivers -S_0x1bfd3a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfd5b0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1de8a80/d .functor AND 1, L_0x1de8b40, L_0x1de8ca0, C4<1>, C4<1>; -L_0x1de8a80 .delay 1 (30000,30000,30000) L_0x1de8a80/d; -v0x1bfd670_0 .net *"_s0", 0 0, L_0x1de8b40; 1 drivers -v0x1bfd750_0 .net *"_s1", 0 0, L_0x1de8ca0; 1 drivers -S_0x1bfd830 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1bfb580; - .timescale -9 -12; -P_0x1bfda40 .param/l "i" 0 4 54, +C4<0111>; -L_0x1de8a10/d .functor AND 1, L_0x1de91d0, L_0x1de93c0, C4<1>, C4<1>; -L_0x1de8a10 .delay 1 (30000,30000,30000) L_0x1de8a10/d; -v0x1bfdb00_0 .net *"_s0", 0 0, L_0x1de91d0; 1 drivers -v0x1bfdbe0_0 .net *"_s1", 0 0, L_0x1de93c0; 1 drivers -S_0x1bfe7a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1bfb330; +v0x1090940_0 .net "A", 7 0, L_0x127a9e0; alias, 1 drivers +v0x1090a40_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1090b00_0 .net *"_s0", 0 0, L_0x127ad70; 1 drivers +v0x1090bc0_0 .net *"_s12", 0 0, L_0x127b730; 1 drivers +v0x1090ca0_0 .net *"_s16", 0 0, L_0x127ba90; 1 drivers +v0x1090dd0_0 .net *"_s20", 0 0, L_0x127bec0; 1 drivers +v0x1090eb0_0 .net *"_s24", 0 0, L_0x127c1f0; 1 drivers +v0x1090f90_0 .net *"_s28", 0 0, L_0x127c180; 1 drivers +v0x1091070_0 .net *"_s4", 0 0, L_0x127b110; 1 drivers +v0x10911e0_0 .net *"_s8", 0 0, L_0x127b420; 1 drivers +v0x10912c0_0 .net "out", 7 0, L_0x127c580; alias, 1 drivers +L_0x127ae80 .part L_0x127a9e0, 0, 1; +L_0x127b070 .part v0x12010b0_0, 0, 1; +L_0x127b1d0 .part L_0x127a9e0, 1, 1; +L_0x127b330 .part v0x12010b0_0, 1, 1; +L_0x127b4e0 .part L_0x127a9e0, 2, 1; +L_0x127b640 .part v0x12010b0_0, 2, 1; +L_0x127b7f0 .part L_0x127a9e0, 3, 1; +L_0x127b950 .part v0x12010b0_0, 3, 1; +L_0x127bb50 .part L_0x127a9e0, 4, 1; +L_0x127bdc0 .part v0x12010b0_0, 4, 1; +L_0x127bf30 .part L_0x127a9e0, 5, 1; +L_0x127c090 .part v0x12010b0_0, 5, 1; +L_0x127c2b0 .part L_0x127a9e0, 6, 1; +L_0x127c410 .part v0x12010b0_0, 6, 1; +LS_0x127c580_0_0 .concat8 [ 1 1 1 1], L_0x127ad70, L_0x127b110, L_0x127b420, L_0x127b730; +LS_0x127c580_0_4 .concat8 [ 1 1 1 1], L_0x127ba90, L_0x127bec0, L_0x127c1f0, L_0x127c180; +L_0x127c580 .concat8 [ 4 4 0 0], LS_0x127c580_0_0, LS_0x127c580_0_4; +L_0x127c940 .part L_0x127a9e0, 7, 1; +L_0x127cb30 .part v0x12010b0_0, 7, 1; +S_0x108e440 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x108e650 .param/l "i" 0 4 54, +C4<00>; +L_0x127ad70/d .functor AND 1, L_0x127ae80, L_0x127b070, C4<1>, C4<1>; +L_0x127ad70 .delay 1 (30000,30000,30000) L_0x127ad70/d; +v0x108e730_0 .net *"_s0", 0 0, L_0x127ae80; 1 drivers +v0x108e810_0 .net *"_s1", 0 0, L_0x127b070; 1 drivers +S_0x108e8f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x108eb00 .param/l "i" 0 4 54, +C4<01>; +L_0x127b110/d .functor AND 1, L_0x127b1d0, L_0x127b330, C4<1>, C4<1>; +L_0x127b110 .delay 1 (30000,30000,30000) L_0x127b110/d; +v0x108ebc0_0 .net *"_s0", 0 0, L_0x127b1d0; 1 drivers +v0x108eca0_0 .net *"_s1", 0 0, L_0x127b330; 1 drivers +S_0x108ed80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x108efc0 .param/l "i" 0 4 54, +C4<010>; +L_0x127b420/d .functor AND 1, L_0x127b4e0, L_0x127b640, C4<1>, C4<1>; +L_0x127b420 .delay 1 (30000,30000,30000) L_0x127b420/d; +v0x108f060_0 .net *"_s0", 0 0, L_0x127b4e0; 1 drivers +v0x108f140_0 .net *"_s1", 0 0, L_0x127b640; 1 drivers +S_0x108f220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x108f430 .param/l "i" 0 4 54, +C4<011>; +L_0x127b730/d .functor AND 1, L_0x127b7f0, L_0x127b950, C4<1>, C4<1>; +L_0x127b730 .delay 1 (30000,30000,30000) L_0x127b730/d; +v0x108f4f0_0 .net *"_s0", 0 0, L_0x127b7f0; 1 drivers +v0x108f5d0_0 .net *"_s1", 0 0, L_0x127b950; 1 drivers +S_0x108f6b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x108f910 .param/l "i" 0 4 54, +C4<0100>; +L_0x127ba90/d .functor AND 1, L_0x127bb50, L_0x127bdc0, C4<1>, C4<1>; +L_0x127ba90 .delay 1 (30000,30000,30000) L_0x127ba90/d; +v0x108f9d0_0 .net *"_s0", 0 0, L_0x127bb50; 1 drivers +v0x108fab0_0 .net *"_s1", 0 0, L_0x127bdc0; 1 drivers +S_0x108fb90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x108fda0 .param/l "i" 0 4 54, +C4<0101>; +L_0x127bec0/d .functor AND 1, L_0x127bf30, L_0x127c090, C4<1>, C4<1>; +L_0x127bec0 .delay 1 (30000,30000,30000) L_0x127bec0/d; +v0x108fe60_0 .net *"_s0", 0 0, L_0x127bf30; 1 drivers +v0x108ff40_0 .net *"_s1", 0 0, L_0x127c090; 1 drivers +S_0x1090020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x1090230 .param/l "i" 0 4 54, +C4<0110>; +L_0x127c1f0/d .functor AND 1, L_0x127c2b0, L_0x127c410, C4<1>, C4<1>; +L_0x127c1f0 .delay 1 (30000,30000,30000) L_0x127c1f0/d; +v0x10902f0_0 .net *"_s0", 0 0, L_0x127c2b0; 1 drivers +v0x10903d0_0 .net *"_s1", 0 0, L_0x127c410; 1 drivers +S_0x10904b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x108e200; + .timescale -9 -12; +P_0x10906c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x127c180/d .functor AND 1, L_0x127c940, L_0x127cb30, C4<1>, C4<1>; +L_0x127c180 .delay 1 (30000,30000,30000) L_0x127c180/d; +v0x1090780_0 .net *"_s0", 0 0, L_0x127c940; 1 drivers +v0x1090860_0 .net *"_s1", 0 0, L_0x127cb30; 1 drivers +S_0x1091420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x108dfb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1deae10/d .functor OR 1, L_0x1deaed0, L_0x1deb080, C4<0>, C4<0>; -L_0x1deae10 .delay 1 (30000,30000,30000) L_0x1deae10/d; -v0x1c002f0_0 .net *"_s10", 0 0, L_0x1deaed0; 1 drivers -v0x1c003d0_0 .net *"_s12", 0 0, L_0x1deb080; 1 drivers -v0x1c004b0_0 .net "in", 7 0, L_0x1de8e10; alias, 1 drivers -v0x1c00580_0 .net "ors", 1 0, L_0x1deac30; 1 drivers -v0x1c00640_0 .net "out", 0 0, L_0x1deae10; alias, 1 drivers -L_0x1dea000 .part L_0x1de8e10, 0, 4; -L_0x1deac30 .concat8 [ 1 1 0 0], L_0x1de9cf0, L_0x1dea920; -L_0x1dead70 .part L_0x1de8e10, 4, 4; -L_0x1deaed0 .part L_0x1deac30, 0, 1; -L_0x1deb080 .part L_0x1deac30, 1, 1; -S_0x1bfe960 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1bfe7a0; +L_0x127e580/d .functor OR 1, L_0x127e640, L_0x127e7f0, C4<0>, C4<0>; +L_0x127e580 .delay 1 (30000,30000,30000) L_0x127e580/d; +v0x1092f70_0 .net *"_s10", 0 0, L_0x127e640; 1 drivers +v0x1093050_0 .net *"_s12", 0 0, L_0x127e7f0; 1 drivers +v0x1093130_0 .net "in", 7 0, L_0x127c580; alias, 1 drivers +v0x1093200_0 .net "ors", 1 0, L_0x127e3a0; 1 drivers +v0x10932c0_0 .net "out", 0 0, L_0x127e580; alias, 1 drivers +L_0x127d770 .part L_0x127c580, 0, 4; +L_0x127e3a0 .concat8 [ 1 1 0 0], L_0x127d460, L_0x127e090; +L_0x127e4e0 .part L_0x127c580, 4, 4; +L_0x127e640 .part L_0x127e3a0, 0, 1; +L_0x127e7f0 .part L_0x127e3a0, 1, 1; +S_0x10915e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1091420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1de94b0/d .functor OR 1, L_0x1de9570, L_0x1de96d0, C4<0>, C4<0>; -L_0x1de94b0 .delay 1 (30000,30000,30000) L_0x1de94b0/d; -L_0x1de9900/d .functor OR 1, L_0x1de9a10, L_0x1de9b70, C4<0>, C4<0>; -L_0x1de9900 .delay 1 (30000,30000,30000) L_0x1de9900/d; -L_0x1de9cf0/d .functor OR 1, L_0x1de9d60, L_0x1de9f10, C4<0>, C4<0>; -L_0x1de9cf0 .delay 1 (30000,30000,30000) L_0x1de9cf0/d; -v0x1bfebb0_0 .net *"_s0", 0 0, L_0x1de94b0; 1 drivers -v0x1bfecb0_0 .net *"_s10", 0 0, L_0x1de9a10; 1 drivers -v0x1bfed90_0 .net *"_s12", 0 0, L_0x1de9b70; 1 drivers -v0x1bfee50_0 .net *"_s14", 0 0, L_0x1de9d60; 1 drivers -v0x1bfef30_0 .net *"_s16", 0 0, L_0x1de9f10; 1 drivers -v0x1bff060_0 .net *"_s3", 0 0, L_0x1de9570; 1 drivers -v0x1bff140_0 .net *"_s5", 0 0, L_0x1de96d0; 1 drivers -v0x1bff220_0 .net *"_s6", 0 0, L_0x1de9900; 1 drivers -v0x1bff300_0 .net "in", 3 0, L_0x1dea000; 1 drivers -v0x1bff470_0 .net "ors", 1 0, L_0x1de9810; 1 drivers -v0x1bff550_0 .net "out", 0 0, L_0x1de9cf0; 1 drivers -L_0x1de9570 .part L_0x1dea000, 0, 1; -L_0x1de96d0 .part L_0x1dea000, 1, 1; -L_0x1de9810 .concat8 [ 1 1 0 0], L_0x1de94b0, L_0x1de9900; -L_0x1de9a10 .part L_0x1dea000, 2, 1; -L_0x1de9b70 .part L_0x1dea000, 3, 1; -L_0x1de9d60 .part L_0x1de9810, 0, 1; -L_0x1de9f10 .part L_0x1de9810, 1, 1; -S_0x1bff670 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1bfe7a0; +L_0x127cc20/d .functor OR 1, L_0x127cce0, L_0x127ce40, C4<0>, C4<0>; +L_0x127cc20 .delay 1 (30000,30000,30000) L_0x127cc20/d; +L_0x127d070/d .functor OR 1, L_0x127d180, L_0x127d2e0, C4<0>, C4<0>; +L_0x127d070 .delay 1 (30000,30000,30000) L_0x127d070/d; +L_0x127d460/d .functor OR 1, L_0x127d4d0, L_0x127d680, C4<0>, C4<0>; +L_0x127d460 .delay 1 (30000,30000,30000) L_0x127d460/d; +v0x1091830_0 .net *"_s0", 0 0, L_0x127cc20; 1 drivers +v0x1091930_0 .net *"_s10", 0 0, L_0x127d180; 1 drivers +v0x1091a10_0 .net *"_s12", 0 0, L_0x127d2e0; 1 drivers +v0x1091ad0_0 .net *"_s14", 0 0, L_0x127d4d0; 1 drivers +v0x1091bb0_0 .net *"_s16", 0 0, L_0x127d680; 1 drivers +v0x1091ce0_0 .net *"_s3", 0 0, L_0x127cce0; 1 drivers +v0x1091dc0_0 .net *"_s5", 0 0, L_0x127ce40; 1 drivers +v0x1091ea0_0 .net *"_s6", 0 0, L_0x127d070; 1 drivers +v0x1091f80_0 .net "in", 3 0, L_0x127d770; 1 drivers +v0x10920f0_0 .net "ors", 1 0, L_0x127cf80; 1 drivers +v0x10921d0_0 .net "out", 0 0, L_0x127d460; 1 drivers +L_0x127cce0 .part L_0x127d770, 0, 1; +L_0x127ce40 .part L_0x127d770, 1, 1; +L_0x127cf80 .concat8 [ 1 1 0 0], L_0x127cc20, L_0x127d070; +L_0x127d180 .part L_0x127d770, 2, 1; +L_0x127d2e0 .part L_0x127d770, 3, 1; +L_0x127d4d0 .part L_0x127cf80, 0, 1; +L_0x127d680 .part L_0x127cf80, 1, 1; +S_0x10922f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1091420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dea130/d .functor OR 1, L_0x1dea1a0, L_0x1dea300, C4<0>, C4<0>; -L_0x1dea130 .delay 1 (30000,30000,30000) L_0x1dea130/d; -L_0x1dea530/d .functor OR 1, L_0x1dea640, L_0x1dea7a0, C4<0>, C4<0>; -L_0x1dea530 .delay 1 (30000,30000,30000) L_0x1dea530/d; -L_0x1dea920/d .functor OR 1, L_0x1dea990, L_0x1deab40, C4<0>, C4<0>; -L_0x1dea920 .delay 1 (30000,30000,30000) L_0x1dea920/d; -v0x1bff830_0 .net *"_s0", 0 0, L_0x1dea130; 1 drivers -v0x1bff930_0 .net *"_s10", 0 0, L_0x1dea640; 1 drivers -v0x1bffa10_0 .net *"_s12", 0 0, L_0x1dea7a0; 1 drivers -v0x1bffad0_0 .net *"_s14", 0 0, L_0x1dea990; 1 drivers -v0x1bffbb0_0 .net *"_s16", 0 0, L_0x1deab40; 1 drivers -v0x1bffce0_0 .net *"_s3", 0 0, L_0x1dea1a0; 1 drivers -v0x1bffdc0_0 .net *"_s5", 0 0, L_0x1dea300; 1 drivers -v0x1bffea0_0 .net *"_s6", 0 0, L_0x1dea530; 1 drivers -v0x1bfff80_0 .net "in", 3 0, L_0x1dead70; 1 drivers -v0x1c000f0_0 .net "ors", 1 0, L_0x1dea440; 1 drivers -v0x1c001d0_0 .net "out", 0 0, L_0x1dea920; 1 drivers -L_0x1dea1a0 .part L_0x1dead70, 0, 1; -L_0x1dea300 .part L_0x1dead70, 1, 1; -L_0x1dea440 .concat8 [ 1 1 0 0], L_0x1dea130, L_0x1dea530; -L_0x1dea640 .part L_0x1dead70, 2, 1; -L_0x1dea7a0 .part L_0x1dead70, 3, 1; -L_0x1dea990 .part L_0x1dea440, 0, 1; -L_0x1deab40 .part L_0x1dea440, 1, 1; -S_0x1c00ae0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bf4460; +L_0x127d8a0/d .functor OR 1, L_0x127d910, L_0x127da70, C4<0>, C4<0>; +L_0x127d8a0 .delay 1 (30000,30000,30000) L_0x127d8a0/d; +L_0x127dca0/d .functor OR 1, L_0x127ddb0, L_0x127df10, C4<0>, C4<0>; +L_0x127dca0 .delay 1 (30000,30000,30000) L_0x127dca0/d; +L_0x127e090/d .functor OR 1, L_0x127e100, L_0x127e2b0, C4<0>, C4<0>; +L_0x127e090 .delay 1 (30000,30000,30000) L_0x127e090/d; +v0x10924b0_0 .net *"_s0", 0 0, L_0x127d8a0; 1 drivers +v0x10925b0_0 .net *"_s10", 0 0, L_0x127ddb0; 1 drivers +v0x1092690_0 .net *"_s12", 0 0, L_0x127df10; 1 drivers +v0x1092750_0 .net *"_s14", 0 0, L_0x127e100; 1 drivers +v0x1092830_0 .net *"_s16", 0 0, L_0x127e2b0; 1 drivers +v0x1092960_0 .net *"_s3", 0 0, L_0x127d910; 1 drivers +v0x1092a40_0 .net *"_s5", 0 0, L_0x127da70; 1 drivers +v0x1092b20_0 .net *"_s6", 0 0, L_0x127dca0; 1 drivers +v0x1092c00_0 .net "in", 3 0, L_0x127e4e0; 1 drivers +v0x1092d70_0 .net "ors", 1 0, L_0x127dbb0; 1 drivers +v0x1092e50_0 .net "out", 0 0, L_0x127e090; 1 drivers +L_0x127d910 .part L_0x127e4e0, 0, 1; +L_0x127da70 .part L_0x127e4e0, 1, 1; +L_0x127dbb0 .concat8 [ 1 1 0 0], L_0x127d8a0, L_0x127dca0; +L_0x127ddb0 .part L_0x127e4e0, 2, 1; +L_0x127df10 .part L_0x127e4e0, 3, 1; +L_0x127e100 .part L_0x127dbb0, 0, 1; +L_0x127e2b0 .part L_0x127dbb0, 1, 1; +S_0x1093760 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10870e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -7036,80 +7046,80 @@ S_0x1c00ae0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1bf4460; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1de65e0/d .functor XNOR 1, L_0x1deecb0, L_0x1deee10, C4<0>, C4<0>; -L_0x1de65e0 .delay 1 (20000,20000,20000) L_0x1de65e0/d; -L_0x1de6850/d .functor AND 1, L_0x1deecb0, L_0x1de55e0, C4<1>, C4<1>; -L_0x1de6850 .delay 1 (30000,30000,30000) L_0x1de6850/d; -L_0x1de68c0/d .functor AND 1, L_0x1de65e0, L_0x1de53c0, C4<1>, C4<1>; -L_0x1de68c0 .delay 1 (30000,30000,30000) L_0x1de68c0/d; -L_0x1de6a20/d .functor OR 1, L_0x1de68c0, L_0x1de6850, C4<0>, C4<0>; -L_0x1de6a20 .delay 1 (30000,30000,30000) L_0x1de6a20/d; -v0x1c00d90_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers -v0x1c00e80_0 .net "a_", 0 0, L_0x1de52a0; alias, 1 drivers -v0x1c00f40_0 .net "b", 0 0, L_0x1deee10; alias, 1 drivers -v0x1c01030_0 .net "b_", 0 0, L_0x1de55e0; alias, 1 drivers -v0x1c010d0_0 .net "carryin", 0 0, L_0x1de53c0; alias, 1 drivers -v0x1c01210_0 .net "eq", 0 0, L_0x1de65e0; 1 drivers -v0x1c012d0_0 .net "lt", 0 0, L_0x1de6850; 1 drivers -v0x1c01390_0 .net "out", 0 0, L_0x1de6a20; 1 drivers -v0x1c01450_0 .net "w0", 0 0, L_0x1de68c0; 1 drivers -S_0x1c016a0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1bf4460; +L_0x1279d50/d .functor XNOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; +L_0x1279d50 .delay 1 (20000,20000,20000) L_0x1279d50/d; +L_0x1279fc0/d .functor AND 1, L_0x1282420, L_0x1278d50, C4<1>, C4<1>; +L_0x1279fc0 .delay 1 (30000,30000,30000) L_0x1279fc0/d; +L_0x127a030/d .functor AND 1, L_0x1279d50, L_0x1278b30, C4<1>, C4<1>; +L_0x127a030 .delay 1 (30000,30000,30000) L_0x127a030/d; +L_0x127a190/d .functor OR 1, L_0x127a030, L_0x1279fc0, C4<0>, C4<0>; +L_0x127a190 .delay 1 (30000,30000,30000) L_0x127a190/d; +v0x1093a10_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers +v0x1093b00_0 .net "a_", 0 0, L_0x1278a10; alias, 1 drivers +v0x1093bc0_0 .net "b", 0 0, L_0x1282580; alias, 1 drivers +v0x1093cb0_0 .net "b_", 0 0, L_0x1278d50; alias, 1 drivers +v0x1093d50_0 .net "carryin", 0 0, L_0x1278b30; alias, 1 drivers +v0x1093e90_0 .net "eq", 0 0, L_0x1279d50; 1 drivers +v0x1093f50_0 .net "lt", 0 0, L_0x1279fc0; 1 drivers +v0x1094010_0 .net "out", 0 0, L_0x127a190; 1 drivers +v0x10940d0_0 .net "w0", 0 0, L_0x127a030; 1 drivers +S_0x1094320 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10870e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1de63c0/d .functor OR 1, L_0x1de5f10, L_0x1c02900, C4<0>, C4<0>; -L_0x1de63c0 .delay 1 (30000,30000,30000) L_0x1de63c0/d; -v0x1c02490_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers -v0x1c025e0_0 .net "b", 0 0, L_0x1de55e0; alias, 1 drivers -v0x1c026a0_0 .net "c1", 0 0, L_0x1de5f10; 1 drivers -v0x1c02740_0 .net "c2", 0 0, L_0x1c02900; 1 drivers -v0x1c02810_0 .net "carryin", 0 0, L_0x1de53c0; alias, 1 drivers -v0x1c02990_0 .net "carryout", 0 0, L_0x1de63c0; 1 drivers -v0x1c02a30_0 .net "s1", 0 0, L_0x1de5e50; 1 drivers -v0x1c02ad0_0 .net "sum", 0 0, L_0x1de6070; 1 drivers -S_0x1c018f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c016a0; +L_0x1279b30/d .functor OR 1, L_0x1279680, L_0x1095580, C4<0>, C4<0>; +L_0x1279b30 .delay 1 (30000,30000,30000) L_0x1279b30/d; +v0x1095110_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers +v0x1095260_0 .net "b", 0 0, L_0x1278d50; alias, 1 drivers +v0x1095320_0 .net "c1", 0 0, L_0x1279680; 1 drivers +v0x10953c0_0 .net "c2", 0 0, L_0x1095580; 1 drivers +v0x1095490_0 .net "carryin", 0 0, L_0x1278b30; alias, 1 drivers +v0x1095610_0 .net "carryout", 0 0, L_0x1279b30; 1 drivers +v0x10956b0_0 .net "s1", 0 0, L_0x12795c0; 1 drivers +v0x1095750_0 .net "sum", 0 0, L_0x12797e0; 1 drivers +S_0x1094570 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1094320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1de5e50/d .functor XOR 1, L_0x1deecb0, L_0x1de55e0, C4<0>, C4<0>; -L_0x1de5e50 .delay 1 (30000,30000,30000) L_0x1de5e50/d; -L_0x1de5f10/d .functor AND 1, L_0x1deecb0, L_0x1de55e0, C4<1>, C4<1>; -L_0x1de5f10 .delay 1 (30000,30000,30000) L_0x1de5f10/d; -v0x1c01b50_0 .net "a", 0 0, L_0x1deecb0; alias, 1 drivers -v0x1c01c10_0 .net "b", 0 0, L_0x1de55e0; alias, 1 drivers -v0x1c01cd0_0 .net "carryout", 0 0, L_0x1de5f10; alias, 1 drivers -v0x1c01d70_0 .net "sum", 0 0, L_0x1de5e50; alias, 1 drivers -S_0x1c01ea0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c016a0; +L_0x12795c0/d .functor XOR 1, L_0x1282420, L_0x1278d50, C4<0>, C4<0>; +L_0x12795c0 .delay 1 (30000,30000,30000) L_0x12795c0/d; +L_0x1279680/d .functor AND 1, L_0x1282420, L_0x1278d50, C4<1>, C4<1>; +L_0x1279680 .delay 1 (30000,30000,30000) L_0x1279680/d; +v0x10947d0_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers +v0x1094890_0 .net "b", 0 0, L_0x1278d50; alias, 1 drivers +v0x1094950_0 .net "carryout", 0 0, L_0x1279680; alias, 1 drivers +v0x10949f0_0 .net "sum", 0 0, L_0x12795c0; alias, 1 drivers +S_0x1094b20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1094320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1de6070/d .functor XOR 1, L_0x1de5e50, L_0x1de53c0, C4<0>, C4<0>; -L_0x1de6070 .delay 1 (30000,30000,30000) L_0x1de6070/d; -L_0x1c02900/d .functor AND 1, L_0x1de5e50, L_0x1de53c0, C4<1>, C4<1>; -L_0x1c02900 .delay 1 (30000,30000,30000) L_0x1c02900/d; -v0x1c02100_0 .net "a", 0 0, L_0x1de5e50; alias, 1 drivers -v0x1c021d0_0 .net "b", 0 0, L_0x1de53c0; alias, 1 drivers -v0x1c02270_0 .net "carryout", 0 0, L_0x1c02900; alias, 1 drivers -v0x1c02340_0 .net "sum", 0 0, L_0x1de6070; alias, 1 drivers -S_0x1c04360 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1bf4190; - .timescale -9 -12; -L_0x7f72592dad98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dade0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1deed50/d .functor OR 1, L_0x7f72592dad98, L_0x7f72592dade0, C4<0>, C4<0>; -L_0x1deed50 .delay 1 (30000,30000,30000) L_0x1deed50/d; -v0x1c044e0_0 .net/2u *"_s0", 0 0, L_0x7f72592dad98; 1 drivers -v0x1c04580_0 .net/2u *"_s2", 0 0, L_0x7f72592dade0; 1 drivers -S_0x1c04640 .scope generate, "alu_slices[13]" "alu_slices[13]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c04850 .param/l "i" 0 3 37, +C4<01101>; -S_0x1c04910 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c04640; +L_0x12797e0/d .functor XOR 1, L_0x12795c0, L_0x1278b30, C4<0>, C4<0>; +L_0x12797e0 .delay 1 (30000,30000,30000) L_0x12797e0/d; +L_0x1095580/d .functor AND 1, L_0x12795c0, L_0x1278b30, C4<1>, C4<1>; +L_0x1095580 .delay 1 (30000,30000,30000) L_0x1095580/d; +v0x1094d80_0 .net "a", 0 0, L_0x12795c0; alias, 1 drivers +v0x1094e50_0 .net "b", 0 0, L_0x1278b30; alias, 1 drivers +v0x1094ef0_0 .net "carryout", 0 0, L_0x1095580; alias, 1 drivers +v0x1094fc0_0 .net "sum", 0 0, L_0x12797e0; alias, 1 drivers +S_0x1096fe0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1086e10; + .timescale -9 -12; +L_0x2b0ab3d05d98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05de0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12824c0/d .functor OR 1, L_0x2b0ab3d05d98, L_0x2b0ab3d05de0, C4<0>, C4<0>; +L_0x12824c0 .delay 1 (30000,30000,30000) L_0x12824c0/d; +v0x1097160_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05d98; 1 drivers +v0x1097200_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05de0; 1 drivers +S_0x10972c0 .scope generate, "alu_slices[13]" "alu_slices[13]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x10974d0 .param/l "i" 0 3 41, +C4<01101>; +S_0x1097590 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10972c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -7118,445 +7128,445 @@ S_0x1c04910 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c04640; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1def090/d .functor NOT 1, L_0x1df88f0, C4<0>, C4<0>, C4<0>; -L_0x1def090 .delay 1 (10000,10000,10000) L_0x1def090/d; -L_0x1def1f0/d .functor NOT 1, L_0x1deeeb0, C4<0>, C4<0>, C4<0>; -L_0x1def1f0 .delay 1 (10000,10000,10000) L_0x1def1f0/d; -L_0x1df0240/d .functor XOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; -L_0x1df0240 .delay 1 (30000,30000,30000) L_0x1df0240/d; -L_0x7f72592dae28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dae70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1df08f0/d .functor OR 1, L_0x7f72592dae28, L_0x7f72592dae70, C4<0>, C4<0>; -L_0x1df08f0 .delay 1 (30000,30000,30000) L_0x1df08f0/d; -L_0x1df0af0/d .functor AND 1, L_0x1df88f0, L_0x1deeeb0, C4<1>, C4<1>; -L_0x1df0af0 .delay 1 (30000,30000,30000) L_0x1df0af0/d; -L_0x1df0bb0/d .functor NAND 1, L_0x1df88f0, L_0x1deeeb0, C4<1>, C4<1>; -L_0x1df0bb0 .delay 1 (20000,20000,20000) L_0x1df0bb0/d; -L_0x1df0d10/d .functor XOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; -L_0x1df0d10 .delay 1 (20000,20000,20000) L_0x1df0d10/d; -L_0x1df11c0/d .functor OR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; -L_0x1df11c0 .delay 1 (30000,30000,30000) L_0x1df11c0/d; -L_0x1df87f0/d .functor NOT 1, L_0x1df4a50, C4<0>, C4<0>, C4<0>; -L_0x1df87f0 .delay 1 (10000,10000,10000) L_0x1df87f0/d; -v0x1c130d0_0 .net "A", 0 0, L_0x1df88f0; 1 drivers -v0x1c13190_0 .net "A_", 0 0, L_0x1def090; 1 drivers -v0x1c13250_0 .net "B", 0 0, L_0x1deeeb0; 1 drivers -v0x1c13320_0 .net "B_", 0 0, L_0x1def1f0; 1 drivers -v0x1c133c0_0 .net *"_s12", 0 0, L_0x1df08f0; 1 drivers -v0x1c134b0_0 .net/2s *"_s14", 0 0, L_0x7f72592dae28; 1 drivers -v0x1c13570_0 .net/2s *"_s16", 0 0, L_0x7f72592dae70; 1 drivers -v0x1c13650_0 .net *"_s18", 0 0, L_0x1df0af0; 1 drivers -v0x1c13730_0 .net *"_s20", 0 0, L_0x1df0bb0; 1 drivers -v0x1c138a0_0 .net *"_s22", 0 0, L_0x1df0d10; 1 drivers -v0x1c13980_0 .net *"_s24", 0 0, L_0x1df11c0; 1 drivers -o0x7f72593747d8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c13a60_0 name=_s30 -o0x7f7259374808 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c13b40_0 name=_s32 -v0x1c13c20_0 .net *"_s8", 0 0, L_0x1df0240; 1 drivers -v0x1c13d00_0 .net "carryin", 0 0, L_0x1deef50; 1 drivers -v0x1c13da0_0 .net "carryout", 0 0, L_0x1df8490; 1 drivers -v0x1c13e40_0 .net "carryouts", 7 0, L_0x1ec0080; 1 drivers -v0x1c13ff0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c14090_0 .net "result", 0 0, L_0x1df4a50; 1 drivers -v0x1c14180_0 .net "results", 7 0, L_0x1df0f90; 1 drivers -v0x1c14290_0 .net "zero", 0 0, L_0x1df87f0; 1 drivers -LS_0x1df0f90_0_0 .concat8 [ 1 1 1 1], L_0x1def710, L_0x1defd40, L_0x1df0240, L_0x1df08f0; -LS_0x1df0f90_0_4 .concat8 [ 1 1 1 1], L_0x1df0af0, L_0x1df0bb0, L_0x1df0d10, L_0x1df11c0; -L_0x1df0f90 .concat8 [ 4 4 0 0], LS_0x1df0f90_0_0, LS_0x1df0f90_0_4; -LS_0x1ec0080_0_0 .concat [ 1 1 1 1], L_0x1def9c0, L_0x1df00e0, o0x7f72593747d8, L_0x1df0740; -LS_0x1ec0080_0_4 .concat [ 4 0 0 0], o0x7f7259374808; -L_0x1ec0080 .concat [ 4 4 0 0], LS_0x1ec0080_0_0, LS_0x1ec0080_0_4; -S_0x1c04b90 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c04910; +L_0x1282800/d .functor NOT 1, L_0x128c030, C4<0>, C4<0>, C4<0>; +L_0x1282800 .delay 1 (10000,10000,10000) L_0x1282800/d; +L_0x1282960/d .functor NOT 1, L_0x1282620, C4<0>, C4<0>, C4<0>; +L_0x1282960 .delay 1 (10000,10000,10000) L_0x1282960/d; +L_0x12838a0/d .functor XOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; +L_0x12838a0 .delay 1 (30000,30000,30000) L_0x12838a0/d; +L_0x2b0ab3d05e28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05e70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1283f50/d .functor OR 1, L_0x2b0ab3d05e28, L_0x2b0ab3d05e70, C4<0>, C4<0>; +L_0x1283f50 .delay 1 (30000,30000,30000) L_0x1283f50/d; +L_0x1284150/d .functor AND 1, L_0x128c030, L_0x1282620, C4<1>, C4<1>; +L_0x1284150 .delay 1 (30000,30000,30000) L_0x1284150/d; +L_0x1284210/d .functor NAND 1, L_0x128c030, L_0x1282620, C4<1>, C4<1>; +L_0x1284210 .delay 1 (20000,20000,20000) L_0x1284210/d; +L_0x1284370/d .functor XOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; +L_0x1284370 .delay 1 (20000,20000,20000) L_0x1284370/d; +L_0x1284820/d .functor OR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; +L_0x1284820 .delay 1 (30000,30000,30000) L_0x1284820/d; +L_0x128bf30/d .functor NOT 1, L_0x1288190, C4<0>, C4<0>, C4<0>; +L_0x128bf30 .delay 1 (10000,10000,10000) L_0x128bf30/d; +v0x10a5d50_0 .net "A", 0 0, L_0x128c030; 1 drivers +v0x10a5e10_0 .net "A_", 0 0, L_0x1282800; 1 drivers +v0x10a5ed0_0 .net "B", 0 0, L_0x1282620; 1 drivers +v0x10a5fa0_0 .net "B_", 0 0, L_0x1282960; 1 drivers +v0x10a6040_0 .net *"_s12", 0 0, L_0x1283f50; 1 drivers +v0x10a6130_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05e28; 1 drivers +v0x10a61d0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05e70; 1 drivers +v0x10a6290_0 .net *"_s18", 0 0, L_0x1284150; 1 drivers +v0x10a6370_0 .net *"_s20", 0 0, L_0x1284210; 1 drivers +v0x10a64e0_0 .net *"_s22", 0 0, L_0x1284370; 1 drivers +v0x10a65c0_0 .net *"_s24", 0 0, L_0x1284820; 1 drivers +o0x2b0ab3cc37d8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10a66a0_0 name=_s30 +o0x2b0ab3cc3808 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10a6780_0 name=_s32 +v0x10a6860_0 .net *"_s8", 0 0, L_0x12838a0; 1 drivers +v0x10a6940_0 .net "carryin", 0 0, L_0x12826c0; 1 drivers +v0x10a69e0_0 .net "carryout", 0 0, L_0x128bbd0; 1 drivers +v0x10a6a80_0 .net "carryouts", 7 0, L_0x13543b0; 1 drivers +v0x10a6c30_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10a6cd0_0 .net "result", 0 0, L_0x1288190; 1 drivers +v0x10a6dc0_0 .net "results", 7 0, L_0x12845f0; 1 drivers +v0x10a6ed0_0 .net "zero", 0 0, L_0x128bf30; 1 drivers +LS_0x12845f0_0_0 .concat8 [ 1 1 1 1], L_0x1282dc0, L_0x12833f0, L_0x12838a0, L_0x1283f50; +LS_0x12845f0_0_4 .concat8 [ 1 1 1 1], L_0x1284150, L_0x1284210, L_0x1284370, L_0x1284820; +L_0x12845f0 .concat8 [ 4 4 0 0], LS_0x12845f0_0_0, LS_0x12845f0_0_4; +LS_0x13543b0_0_0 .concat [ 1 1 1 1], L_0x1283070, L_0x1283740, o0x2b0ab3cc37d8, L_0x1283da0; +LS_0x13543b0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc3808; +L_0x13543b0 .concat [ 4 4 0 0], LS_0x13543b0_0_0, LS_0x13543b0_0_4; +S_0x1097810 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1097590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1def9c0/d .functor OR 1, L_0x1def4a0, L_0x1def860, C4<0>, C4<0>; -L_0x1def9c0 .delay 1 (30000,30000,30000) L_0x1def9c0/d; -v0x1c05a50_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers -v0x1c05b10_0 .net "b", 0 0, L_0x1deeeb0; alias, 1 drivers -v0x1c05be0_0 .net "c1", 0 0, L_0x1def4a0; 1 drivers -v0x1c05ce0_0 .net "c2", 0 0, L_0x1def860; 1 drivers -v0x1c05db0_0 .net "carryin", 0 0, L_0x1deef50; alias, 1 drivers -v0x1c05ea0_0 .net "carryout", 0 0, L_0x1def9c0; 1 drivers -v0x1c05f40_0 .net "s1", 0 0, L_0x1def3e0; 1 drivers -v0x1c06030_0 .net "sum", 0 0, L_0x1def710; 1 drivers -S_0x1c04e00 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c04b90; +L_0x1283070/d .functor OR 1, L_0x1282b50, L_0x1282f10, C4<0>, C4<0>; +L_0x1283070 .delay 1 (30000,30000,30000) L_0x1283070/d; +v0x10986d0_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers +v0x1098790_0 .net "b", 0 0, L_0x1282620; alias, 1 drivers +v0x1098860_0 .net "c1", 0 0, L_0x1282b50; 1 drivers +v0x1098960_0 .net "c2", 0 0, L_0x1282f10; 1 drivers +v0x1098a30_0 .net "carryin", 0 0, L_0x12826c0; alias, 1 drivers +v0x1098b20_0 .net "carryout", 0 0, L_0x1283070; 1 drivers +v0x1098bc0_0 .net "s1", 0 0, L_0x127c500; 1 drivers +v0x1098cb0_0 .net "sum", 0 0, L_0x1282dc0; 1 drivers +S_0x1097a80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1097810; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1def3e0/d .functor XOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; -L_0x1def3e0 .delay 1 (30000,30000,30000) L_0x1def3e0/d; -L_0x1def4a0/d .functor AND 1, L_0x1df88f0, L_0x1deeeb0, C4<1>, C4<1>; -L_0x1def4a0 .delay 1 (30000,30000,30000) L_0x1def4a0/d; -v0x1c05060_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers -v0x1c05140_0 .net "b", 0 0, L_0x1deeeb0; alias, 1 drivers -v0x1c05200_0 .net "carryout", 0 0, L_0x1def4a0; alias, 1 drivers -v0x1c052d0_0 .net "sum", 0 0, L_0x1def3e0; alias, 1 drivers -S_0x1c05440 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c04b90; +L_0x127c500/d .functor XOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; +L_0x127c500 .delay 1 (30000,30000,30000) L_0x127c500/d; +L_0x1282b50/d .functor AND 1, L_0x128c030, L_0x1282620, C4<1>, C4<1>; +L_0x1282b50 .delay 1 (30000,30000,30000) L_0x1282b50/d; +v0x1097ce0_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers +v0x1097dc0_0 .net "b", 0 0, L_0x1282620; alias, 1 drivers +v0x1097e80_0 .net "carryout", 0 0, L_0x1282b50; alias, 1 drivers +v0x1097f50_0 .net "sum", 0 0, L_0x127c500; alias, 1 drivers +S_0x10980c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1097810; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1def710/d .functor XOR 1, L_0x1def3e0, L_0x1deef50, C4<0>, C4<0>; -L_0x1def710 .delay 1 (30000,30000,30000) L_0x1def710/d; -L_0x1def860/d .functor AND 1, L_0x1def3e0, L_0x1deef50, C4<1>, C4<1>; -L_0x1def860 .delay 1 (30000,30000,30000) L_0x1def860/d; -v0x1c056a0_0 .net "a", 0 0, L_0x1def3e0; alias, 1 drivers -v0x1c05770_0 .net "b", 0 0, L_0x1deef50; alias, 1 drivers -v0x1c05810_0 .net "carryout", 0 0, L_0x1def860; alias, 1 drivers -v0x1c058e0_0 .net "sum", 0 0, L_0x1def710; alias, 1 drivers -S_0x1c06100 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c04910; +L_0x1282dc0/d .functor XOR 1, L_0x127c500, L_0x12826c0, C4<0>, C4<0>; +L_0x1282dc0 .delay 1 (30000,30000,30000) L_0x1282dc0/d; +L_0x1282f10/d .functor AND 1, L_0x127c500, L_0x12826c0, C4<1>, C4<1>; +L_0x1282f10 .delay 1 (30000,30000,30000) L_0x1282f10/d; +v0x1098320_0 .net "a", 0 0, L_0x127c500; alias, 1 drivers +v0x10983f0_0 .net "b", 0 0, L_0x12826c0; alias, 1 drivers +v0x1098490_0 .net "carryout", 0 0, L_0x1282f10; alias, 1 drivers +v0x1098560_0 .net "sum", 0 0, L_0x1282dc0; alias, 1 drivers +S_0x1098d80 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1097590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c0b4f0_0 .net "ands", 7 0, L_0x1df6490; 1 drivers -v0x1c0b600_0 .net "in", 7 0, L_0x1ec0080; alias, 1 drivers -v0x1c0b6c0_0 .net "out", 0 0, L_0x1df8490; alias, 1 drivers -v0x1c0b790_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c06320 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c06100; +v0x109e170_0 .net "ands", 7 0, L_0x1289bd0; 1 drivers +v0x109e280_0 .net "in", 7 0, L_0x13543b0; alias, 1 drivers +v0x109e340_0 .net "out", 0 0, L_0x128bbd0; alias, 1 drivers +v0x109e410_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1098fa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1098d80; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c08a50_0 .net "A", 7 0, L_0x1ec0080; alias, 1 drivers -v0x1c08b50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c08c10_0 .net *"_s0", 0 0, L_0x1df4db0; 1 drivers -v0x1c08cd0_0 .net *"_s12", 0 0, L_0x1df5720; 1 drivers -v0x1c08db0_0 .net *"_s16", 0 0, L_0x1df5a80; 1 drivers -v0x1c08ee0_0 .net *"_s20", 0 0, L_0x1df5d90; 1 drivers -v0x1c08fc0_0 .net *"_s24", 0 0, L_0x1df6180; 1 drivers -v0x1c090a0_0 .net *"_s28", 0 0, L_0x1df6110; 1 drivers -v0x1c09180_0 .net *"_s4", 0 0, L_0x1df50c0; 1 drivers -v0x1c092f0_0 .net *"_s8", 0 0, L_0x1df5410; 1 drivers -v0x1c093d0_0 .net "out", 7 0, L_0x1df6490; alias, 1 drivers -L_0x1df4e70 .part L_0x1ec0080, 0, 1; -L_0x1df4fd0 .part v0x1d6daa0_0, 0, 1; -L_0x1df5180 .part L_0x1ec0080, 1, 1; -L_0x1df5370 .part v0x1d6daa0_0, 1, 1; -L_0x1df54d0 .part L_0x1ec0080, 2, 1; -L_0x1df5630 .part v0x1d6daa0_0, 2, 1; -L_0x1df57e0 .part L_0x1ec0080, 3, 1; -L_0x1df5940 .part v0x1d6daa0_0, 3, 1; -L_0x1df5b40 .part L_0x1ec0080, 4, 1; -L_0x1df5ca0 .part v0x1d6daa0_0, 4, 1; -L_0x1df5e00 .part L_0x1ec0080, 5, 1; -L_0x1df6070 .part v0x1d6daa0_0, 5, 1; -L_0x1df6240 .part L_0x1ec0080, 6, 1; -L_0x1df63a0 .part v0x1d6daa0_0, 6, 1; -LS_0x1df6490_0_0 .concat8 [ 1 1 1 1], L_0x1df4db0, L_0x1df50c0, L_0x1df5410, L_0x1df5720; -LS_0x1df6490_0_4 .concat8 [ 1 1 1 1], L_0x1df5a80, L_0x1df5d90, L_0x1df6180, L_0x1df6110; -L_0x1df6490 .concat8 [ 4 4 0 0], LS_0x1df6490_0_0, LS_0x1df6490_0_4; -L_0x1df6850 .part L_0x1ec0080, 7, 1; -L_0x1df6a40 .part v0x1d6daa0_0, 7, 1; -S_0x1c06580 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c06790 .param/l "i" 0 4 54, +C4<00>; -L_0x1df4db0/d .functor AND 1, L_0x1df4e70, L_0x1df4fd0, C4<1>, C4<1>; -L_0x1df4db0 .delay 1 (30000,30000,30000) L_0x1df4db0/d; -v0x1c06870_0 .net *"_s0", 0 0, L_0x1df4e70; 1 drivers -v0x1c06950_0 .net *"_s1", 0 0, L_0x1df4fd0; 1 drivers -S_0x1c06a30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c06c40 .param/l "i" 0 4 54, +C4<01>; -L_0x1df50c0/d .functor AND 1, L_0x1df5180, L_0x1df5370, C4<1>, C4<1>; -L_0x1df50c0 .delay 1 (30000,30000,30000) L_0x1df50c0/d; -v0x1c06d00_0 .net *"_s0", 0 0, L_0x1df5180; 1 drivers -v0x1c06de0_0 .net *"_s1", 0 0, L_0x1df5370; 1 drivers -S_0x1c06ec0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c070d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1df5410/d .functor AND 1, L_0x1df54d0, L_0x1df5630, C4<1>, C4<1>; -L_0x1df5410 .delay 1 (30000,30000,30000) L_0x1df5410/d; -v0x1c07170_0 .net *"_s0", 0 0, L_0x1df54d0; 1 drivers -v0x1c07250_0 .net *"_s1", 0 0, L_0x1df5630; 1 drivers -S_0x1c07330 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c07540 .param/l "i" 0 4 54, +C4<011>; -L_0x1df5720/d .functor AND 1, L_0x1df57e0, L_0x1df5940, C4<1>, C4<1>; -L_0x1df5720 .delay 1 (30000,30000,30000) L_0x1df5720/d; -v0x1c07600_0 .net *"_s0", 0 0, L_0x1df57e0; 1 drivers -v0x1c076e0_0 .net *"_s1", 0 0, L_0x1df5940; 1 drivers -S_0x1c077c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c07a20 .param/l "i" 0 4 54, +C4<0100>; -L_0x1df5a80/d .functor AND 1, L_0x1df5b40, L_0x1df5ca0, C4<1>, C4<1>; -L_0x1df5a80 .delay 1 (30000,30000,30000) L_0x1df5a80/d; -v0x1c07ae0_0 .net *"_s0", 0 0, L_0x1df5b40; 1 drivers -v0x1c07bc0_0 .net *"_s1", 0 0, L_0x1df5ca0; 1 drivers -S_0x1c07ca0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c07eb0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1df5d90/d .functor AND 1, L_0x1df5e00, L_0x1df6070, C4<1>, C4<1>; -L_0x1df5d90 .delay 1 (30000,30000,30000) L_0x1df5d90/d; -v0x1c07f70_0 .net *"_s0", 0 0, L_0x1df5e00; 1 drivers -v0x1c08050_0 .net *"_s1", 0 0, L_0x1df6070; 1 drivers -S_0x1c08130 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c08340 .param/l "i" 0 4 54, +C4<0110>; -L_0x1df6180/d .functor AND 1, L_0x1df6240, L_0x1df63a0, C4<1>, C4<1>; -L_0x1df6180 .delay 1 (30000,30000,30000) L_0x1df6180/d; -v0x1c08400_0 .net *"_s0", 0 0, L_0x1df6240; 1 drivers -v0x1c084e0_0 .net *"_s1", 0 0, L_0x1df63a0; 1 drivers -S_0x1c085c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c06320; - .timescale -9 -12; -P_0x1c087d0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1df6110/d .functor AND 1, L_0x1df6850, L_0x1df6a40, C4<1>, C4<1>; -L_0x1df6110 .delay 1 (30000,30000,30000) L_0x1df6110/d; -v0x1c08890_0 .net *"_s0", 0 0, L_0x1df6850; 1 drivers -v0x1c08970_0 .net *"_s1", 0 0, L_0x1df6a40; 1 drivers -S_0x1c09530 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c06100; +v0x109b6d0_0 .net "A", 7 0, L_0x13543b0; alias, 1 drivers +v0x109b7d0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x109b890_0 .net *"_s0", 0 0, L_0x12884f0; 1 drivers +v0x109b950_0 .net *"_s12", 0 0, L_0x1288e60; 1 drivers +v0x109ba30_0 .net *"_s16", 0 0, L_0x12891c0; 1 drivers +v0x109bb60_0 .net *"_s20", 0 0, L_0x12894d0; 1 drivers +v0x109bc40_0 .net *"_s24", 0 0, L_0x12898c0; 1 drivers +v0x109bd20_0 .net *"_s28", 0 0, L_0x1289850; 1 drivers +v0x109be00_0 .net *"_s4", 0 0, L_0x1288800; 1 drivers +v0x109bf70_0 .net *"_s8", 0 0, L_0x1288b50; 1 drivers +v0x109c050_0 .net "out", 7 0, L_0x1289bd0; alias, 1 drivers +L_0x12885b0 .part L_0x13543b0, 0, 1; +L_0x1288710 .part v0x12010b0_0, 0, 1; +L_0x12888c0 .part L_0x13543b0, 1, 1; +L_0x1288ab0 .part v0x12010b0_0, 1, 1; +L_0x1288c10 .part L_0x13543b0, 2, 1; +L_0x1288d70 .part v0x12010b0_0, 2, 1; +L_0x1288f20 .part L_0x13543b0, 3, 1; +L_0x1289080 .part v0x12010b0_0, 3, 1; +L_0x1289280 .part L_0x13543b0, 4, 1; +L_0x12893e0 .part v0x12010b0_0, 4, 1; +L_0x1289540 .part L_0x13543b0, 5, 1; +L_0x12897b0 .part v0x12010b0_0, 5, 1; +L_0x1289980 .part L_0x13543b0, 6, 1; +L_0x1289ae0 .part v0x12010b0_0, 6, 1; +LS_0x1289bd0_0_0 .concat8 [ 1 1 1 1], L_0x12884f0, L_0x1288800, L_0x1288b50, L_0x1288e60; +LS_0x1289bd0_0_4 .concat8 [ 1 1 1 1], L_0x12891c0, L_0x12894d0, L_0x12898c0, L_0x1289850; +L_0x1289bd0 .concat8 [ 4 4 0 0], LS_0x1289bd0_0_0, LS_0x1289bd0_0_4; +L_0x1289f90 .part L_0x13543b0, 7, 1; +L_0x128a180 .part v0x12010b0_0, 7, 1; +S_0x1099200 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x1099410 .param/l "i" 0 4 54, +C4<00>; +L_0x12884f0/d .functor AND 1, L_0x12885b0, L_0x1288710, C4<1>, C4<1>; +L_0x12884f0 .delay 1 (30000,30000,30000) L_0x12884f0/d; +v0x10994f0_0 .net *"_s0", 0 0, L_0x12885b0; 1 drivers +v0x10995d0_0 .net *"_s1", 0 0, L_0x1288710; 1 drivers +S_0x10996b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x10998c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1288800/d .functor AND 1, L_0x12888c0, L_0x1288ab0, C4<1>, C4<1>; +L_0x1288800 .delay 1 (30000,30000,30000) L_0x1288800/d; +v0x1099980_0 .net *"_s0", 0 0, L_0x12888c0; 1 drivers +v0x1099a60_0 .net *"_s1", 0 0, L_0x1288ab0; 1 drivers +S_0x1099b40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x1099d50 .param/l "i" 0 4 54, +C4<010>; +L_0x1288b50/d .functor AND 1, L_0x1288c10, L_0x1288d70, C4<1>, C4<1>; +L_0x1288b50 .delay 1 (30000,30000,30000) L_0x1288b50/d; +v0x1099df0_0 .net *"_s0", 0 0, L_0x1288c10; 1 drivers +v0x1099ed0_0 .net *"_s1", 0 0, L_0x1288d70; 1 drivers +S_0x1099fb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x109a1c0 .param/l "i" 0 4 54, +C4<011>; +L_0x1288e60/d .functor AND 1, L_0x1288f20, L_0x1289080, C4<1>, C4<1>; +L_0x1288e60 .delay 1 (30000,30000,30000) L_0x1288e60/d; +v0x109a280_0 .net *"_s0", 0 0, L_0x1288f20; 1 drivers +v0x109a360_0 .net *"_s1", 0 0, L_0x1289080; 1 drivers +S_0x109a440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x109a6a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12891c0/d .functor AND 1, L_0x1289280, L_0x12893e0, C4<1>, C4<1>; +L_0x12891c0 .delay 1 (30000,30000,30000) L_0x12891c0/d; +v0x109a760_0 .net *"_s0", 0 0, L_0x1289280; 1 drivers +v0x109a840_0 .net *"_s1", 0 0, L_0x12893e0; 1 drivers +S_0x109a920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x109ab30 .param/l "i" 0 4 54, +C4<0101>; +L_0x12894d0/d .functor AND 1, L_0x1289540, L_0x12897b0, C4<1>, C4<1>; +L_0x12894d0 .delay 1 (30000,30000,30000) L_0x12894d0/d; +v0x109abf0_0 .net *"_s0", 0 0, L_0x1289540; 1 drivers +v0x109acd0_0 .net *"_s1", 0 0, L_0x12897b0; 1 drivers +S_0x109adb0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x109afc0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12898c0/d .functor AND 1, L_0x1289980, L_0x1289ae0, C4<1>, C4<1>; +L_0x12898c0 .delay 1 (30000,30000,30000) L_0x12898c0/d; +v0x109b080_0 .net *"_s0", 0 0, L_0x1289980; 1 drivers +v0x109b160_0 .net *"_s1", 0 0, L_0x1289ae0; 1 drivers +S_0x109b240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1098fa0; + .timescale -9 -12; +P_0x109b450 .param/l "i" 0 4 54, +C4<0111>; +L_0x1289850/d .functor AND 1, L_0x1289f90, L_0x128a180, C4<1>, C4<1>; +L_0x1289850 .delay 1 (30000,30000,30000) L_0x1289850/d; +v0x109b510_0 .net *"_s0", 0 0, L_0x1289f90; 1 drivers +v0x109b5f0_0 .net *"_s1", 0 0, L_0x128a180; 1 drivers +S_0x109c1b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1098d80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1df8490/d .functor OR 1, L_0x1df8550, L_0x1df8700, C4<0>, C4<0>; -L_0x1df8490 .delay 1 (30000,30000,30000) L_0x1df8490/d; -v0x1c0b080_0 .net *"_s10", 0 0, L_0x1df8550; 1 drivers -v0x1c0b160_0 .net *"_s12", 0 0, L_0x1df8700; 1 drivers -v0x1c0b240_0 .net "in", 7 0, L_0x1df6490; alias, 1 drivers -v0x1c0b310_0 .net "ors", 1 0, L_0x1df82b0; 1 drivers -v0x1c0b3d0_0 .net "out", 0 0, L_0x1df8490; alias, 1 drivers -L_0x1df7680 .part L_0x1df6490, 0, 4; -L_0x1df82b0 .concat8 [ 1 1 0 0], L_0x1df7370, L_0x1df7fa0; -L_0x1df83f0 .part L_0x1df6490, 4, 4; -L_0x1df8550 .part L_0x1df82b0, 0, 1; -L_0x1df8700 .part L_0x1df82b0, 1, 1; -S_0x1c096f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c09530; +L_0x128bbd0/d .functor OR 1, L_0x128bc90, L_0x128be40, C4<0>, C4<0>; +L_0x128bbd0 .delay 1 (30000,30000,30000) L_0x128bbd0/d; +v0x109dd00_0 .net *"_s10", 0 0, L_0x128bc90; 1 drivers +v0x109dde0_0 .net *"_s12", 0 0, L_0x128be40; 1 drivers +v0x109dec0_0 .net "in", 7 0, L_0x1289bd0; alias, 1 drivers +v0x109df90_0 .net "ors", 1 0, L_0x128b9f0; 1 drivers +v0x109e050_0 .net "out", 0 0, L_0x128bbd0; alias, 1 drivers +L_0x128adc0 .part L_0x1289bd0, 0, 4; +L_0x128b9f0 .concat8 [ 1 1 0 0], L_0x128aab0, L_0x128b6e0; +L_0x128bb30 .part L_0x1289bd0, 4, 4; +L_0x128bc90 .part L_0x128b9f0, 0, 1; +L_0x128be40 .part L_0x128b9f0, 1, 1; +S_0x109c370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x109c1b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1df6b30/d .functor OR 1, L_0x1df6bf0, L_0x1df6d50, C4<0>, C4<0>; -L_0x1df6b30 .delay 1 (30000,30000,30000) L_0x1df6b30/d; -L_0x1df6f80/d .functor OR 1, L_0x1df7090, L_0x1df71f0, C4<0>, C4<0>; -L_0x1df6f80 .delay 1 (30000,30000,30000) L_0x1df6f80/d; -L_0x1df7370/d .functor OR 1, L_0x1df73e0, L_0x1df7590, C4<0>, C4<0>; -L_0x1df7370 .delay 1 (30000,30000,30000) L_0x1df7370/d; -v0x1c09940_0 .net *"_s0", 0 0, L_0x1df6b30; 1 drivers -v0x1c09a40_0 .net *"_s10", 0 0, L_0x1df7090; 1 drivers -v0x1c09b20_0 .net *"_s12", 0 0, L_0x1df71f0; 1 drivers -v0x1c09be0_0 .net *"_s14", 0 0, L_0x1df73e0; 1 drivers -v0x1c09cc0_0 .net *"_s16", 0 0, L_0x1df7590; 1 drivers -v0x1c09df0_0 .net *"_s3", 0 0, L_0x1df6bf0; 1 drivers -v0x1c09ed0_0 .net *"_s5", 0 0, L_0x1df6d50; 1 drivers -v0x1c09fb0_0 .net *"_s6", 0 0, L_0x1df6f80; 1 drivers -v0x1c0a090_0 .net "in", 3 0, L_0x1df7680; 1 drivers -v0x1c0a200_0 .net "ors", 1 0, L_0x1df6e90; 1 drivers -v0x1c0a2e0_0 .net "out", 0 0, L_0x1df7370; 1 drivers -L_0x1df6bf0 .part L_0x1df7680, 0, 1; -L_0x1df6d50 .part L_0x1df7680, 1, 1; -L_0x1df6e90 .concat8 [ 1 1 0 0], L_0x1df6b30, L_0x1df6f80; -L_0x1df7090 .part L_0x1df7680, 2, 1; -L_0x1df71f0 .part L_0x1df7680, 3, 1; -L_0x1df73e0 .part L_0x1df6e90, 0, 1; -L_0x1df7590 .part L_0x1df6e90, 1, 1; -S_0x1c0a400 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c09530; +L_0x128a270/d .functor OR 1, L_0x128a330, L_0x128a490, C4<0>, C4<0>; +L_0x128a270 .delay 1 (30000,30000,30000) L_0x128a270/d; +L_0x128a6c0/d .functor OR 1, L_0x128a7d0, L_0x128a930, C4<0>, C4<0>; +L_0x128a6c0 .delay 1 (30000,30000,30000) L_0x128a6c0/d; +L_0x128aab0/d .functor OR 1, L_0x128ab20, L_0x128acd0, C4<0>, C4<0>; +L_0x128aab0 .delay 1 (30000,30000,30000) L_0x128aab0/d; +v0x109c5c0_0 .net *"_s0", 0 0, L_0x128a270; 1 drivers +v0x109c6c0_0 .net *"_s10", 0 0, L_0x128a7d0; 1 drivers +v0x109c7a0_0 .net *"_s12", 0 0, L_0x128a930; 1 drivers +v0x109c860_0 .net *"_s14", 0 0, L_0x128ab20; 1 drivers +v0x109c940_0 .net *"_s16", 0 0, L_0x128acd0; 1 drivers +v0x109ca70_0 .net *"_s3", 0 0, L_0x128a330; 1 drivers +v0x109cb50_0 .net *"_s5", 0 0, L_0x128a490; 1 drivers +v0x109cc30_0 .net *"_s6", 0 0, L_0x128a6c0; 1 drivers +v0x109cd10_0 .net "in", 3 0, L_0x128adc0; 1 drivers +v0x109ce80_0 .net "ors", 1 0, L_0x128a5d0; 1 drivers +v0x109cf60_0 .net "out", 0 0, L_0x128aab0; 1 drivers +L_0x128a330 .part L_0x128adc0, 0, 1; +L_0x128a490 .part L_0x128adc0, 1, 1; +L_0x128a5d0 .concat8 [ 1 1 0 0], L_0x128a270, L_0x128a6c0; +L_0x128a7d0 .part L_0x128adc0, 2, 1; +L_0x128a930 .part L_0x128adc0, 3, 1; +L_0x128ab20 .part L_0x128a5d0, 0, 1; +L_0x128acd0 .part L_0x128a5d0, 1, 1; +S_0x109d080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x109c1b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1df77b0/d .functor OR 1, L_0x1df7820, L_0x1df7980, C4<0>, C4<0>; -L_0x1df77b0 .delay 1 (30000,30000,30000) L_0x1df77b0/d; -L_0x1df7bb0/d .functor OR 1, L_0x1df7cc0, L_0x1df7e20, C4<0>, C4<0>; -L_0x1df7bb0 .delay 1 (30000,30000,30000) L_0x1df7bb0/d; -L_0x1df7fa0/d .functor OR 1, L_0x1df8010, L_0x1df81c0, C4<0>, C4<0>; -L_0x1df7fa0 .delay 1 (30000,30000,30000) L_0x1df7fa0/d; -v0x1c0a5c0_0 .net *"_s0", 0 0, L_0x1df77b0; 1 drivers -v0x1c0a6c0_0 .net *"_s10", 0 0, L_0x1df7cc0; 1 drivers -v0x1c0a7a0_0 .net *"_s12", 0 0, L_0x1df7e20; 1 drivers -v0x1c0a860_0 .net *"_s14", 0 0, L_0x1df8010; 1 drivers -v0x1c0a940_0 .net *"_s16", 0 0, L_0x1df81c0; 1 drivers -v0x1c0aa70_0 .net *"_s3", 0 0, L_0x1df7820; 1 drivers -v0x1c0ab50_0 .net *"_s5", 0 0, L_0x1df7980; 1 drivers -v0x1c0ac30_0 .net *"_s6", 0 0, L_0x1df7bb0; 1 drivers -v0x1c0ad10_0 .net "in", 3 0, L_0x1df83f0; 1 drivers -v0x1c0ae80_0 .net "ors", 1 0, L_0x1df7ac0; 1 drivers -v0x1c0af60_0 .net "out", 0 0, L_0x1df7fa0; 1 drivers -L_0x1df7820 .part L_0x1df83f0, 0, 1; -L_0x1df7980 .part L_0x1df83f0, 1, 1; -L_0x1df7ac0 .concat8 [ 1 1 0 0], L_0x1df77b0, L_0x1df7bb0; -L_0x1df7cc0 .part L_0x1df83f0, 2, 1; -L_0x1df7e20 .part L_0x1df83f0, 3, 1; -L_0x1df8010 .part L_0x1df7ac0, 0, 1; -L_0x1df81c0 .part L_0x1df7ac0, 1, 1; -S_0x1c0b870 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c04910; +L_0x128aef0/d .functor OR 1, L_0x128af60, L_0x128b0c0, C4<0>, C4<0>; +L_0x128aef0 .delay 1 (30000,30000,30000) L_0x128aef0/d; +L_0x128b2f0/d .functor OR 1, L_0x128b400, L_0x128b560, C4<0>, C4<0>; +L_0x128b2f0 .delay 1 (30000,30000,30000) L_0x128b2f0/d; +L_0x128b6e0/d .functor OR 1, L_0x128b750, L_0x128b900, C4<0>, C4<0>; +L_0x128b6e0 .delay 1 (30000,30000,30000) L_0x128b6e0/d; +v0x109d240_0 .net *"_s0", 0 0, L_0x128aef0; 1 drivers +v0x109d340_0 .net *"_s10", 0 0, L_0x128b400; 1 drivers +v0x109d420_0 .net *"_s12", 0 0, L_0x128b560; 1 drivers +v0x109d4e0_0 .net *"_s14", 0 0, L_0x128b750; 1 drivers +v0x109d5c0_0 .net *"_s16", 0 0, L_0x128b900; 1 drivers +v0x109d6f0_0 .net *"_s3", 0 0, L_0x128af60; 1 drivers +v0x109d7d0_0 .net *"_s5", 0 0, L_0x128b0c0; 1 drivers +v0x109d8b0_0 .net *"_s6", 0 0, L_0x128b2f0; 1 drivers +v0x109d990_0 .net "in", 3 0, L_0x128bb30; 1 drivers +v0x109db00_0 .net "ors", 1 0, L_0x128b200; 1 drivers +v0x109dbe0_0 .net "out", 0 0, L_0x128b6e0; 1 drivers +L_0x128af60 .part L_0x128bb30, 0, 1; +L_0x128b0c0 .part L_0x128bb30, 1, 1; +L_0x128b200 .concat8 [ 1 1 0 0], L_0x128aef0, L_0x128b2f0; +L_0x128b400 .part L_0x128bb30, 2, 1; +L_0x128b560 .part L_0x128bb30, 3, 1; +L_0x128b750 .part L_0x128b200, 0, 1; +L_0x128b900 .part L_0x128b200, 1, 1; +S_0x109e4f0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1097590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c10ca0_0 .net "ands", 7 0, L_0x1df2a50; 1 drivers -v0x1c10db0_0 .net "in", 7 0, L_0x1df0f90; alias, 1 drivers -v0x1c10e70_0 .net "out", 0 0, L_0x1df4a50; alias, 1 drivers -v0x1c10f40_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c0bac0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c0b870; +v0x10a3920_0 .net "ands", 7 0, L_0x1286190; 1 drivers +v0x10a3a30_0 .net "in", 7 0, L_0x12845f0; alias, 1 drivers +v0x10a3af0_0 .net "out", 0 0, L_0x1288190; alias, 1 drivers +v0x10a3bc0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x109e740 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x109e4f0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c0e200_0 .net "A", 7 0, L_0x1df0f90; alias, 1 drivers -v0x1c0e300_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c0e3c0_0 .net *"_s0", 0 0, L_0x1df1320; 1 drivers -v0x1c0e480_0 .net *"_s12", 0 0, L_0x1df1ce0; 1 drivers -v0x1c0e560_0 .net *"_s16", 0 0, L_0x1df2040; 1 drivers -v0x1c0e690_0 .net *"_s20", 0 0, L_0x1df2410; 1 drivers -v0x1c0e770_0 .net *"_s24", 0 0, L_0x1df2740; 1 drivers -v0x1c0e850_0 .net *"_s28", 0 0, L_0x1df26d0; 1 drivers -v0x1c0e930_0 .net *"_s4", 0 0, L_0x1df16c0; 1 drivers -v0x1c0eaa0_0 .net *"_s8", 0 0, L_0x1df19d0; 1 drivers -v0x1c0eb80_0 .net "out", 7 0, L_0x1df2a50; alias, 1 drivers -L_0x1df1430 .part L_0x1df0f90, 0, 1; -L_0x1df1620 .part v0x1d6daa0_0, 0, 1; -L_0x1df1780 .part L_0x1df0f90, 1, 1; -L_0x1df18e0 .part v0x1d6daa0_0, 1, 1; -L_0x1df1a90 .part L_0x1df0f90, 2, 1; -L_0x1df1bf0 .part v0x1d6daa0_0, 2, 1; -L_0x1df1da0 .part L_0x1df0f90, 3, 1; -L_0x1df1f00 .part v0x1d6daa0_0, 3, 1; -L_0x1df2100 .part L_0x1df0f90, 4, 1; -L_0x1df2370 .part v0x1d6daa0_0, 4, 1; -L_0x1df2480 .part L_0x1df0f90, 5, 1; -L_0x1df25e0 .part v0x1d6daa0_0, 5, 1; -L_0x1df2800 .part L_0x1df0f90, 6, 1; -L_0x1df2960 .part v0x1d6daa0_0, 6, 1; -LS_0x1df2a50_0_0 .concat8 [ 1 1 1 1], L_0x1df1320, L_0x1df16c0, L_0x1df19d0, L_0x1df1ce0; -LS_0x1df2a50_0_4 .concat8 [ 1 1 1 1], L_0x1df2040, L_0x1df2410, L_0x1df2740, L_0x1df26d0; -L_0x1df2a50 .concat8 [ 4 4 0 0], LS_0x1df2a50_0_0, LS_0x1df2a50_0_4; -L_0x1df2e10 .part L_0x1df0f90, 7, 1; -L_0x1df3000 .part v0x1d6daa0_0, 7, 1; -S_0x1c0bd00 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0bf10 .param/l "i" 0 4 54, +C4<00>; -L_0x1df1320/d .functor AND 1, L_0x1df1430, L_0x1df1620, C4<1>, C4<1>; -L_0x1df1320 .delay 1 (30000,30000,30000) L_0x1df1320/d; -v0x1c0bff0_0 .net *"_s0", 0 0, L_0x1df1430; 1 drivers -v0x1c0c0d0_0 .net *"_s1", 0 0, L_0x1df1620; 1 drivers -S_0x1c0c1b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0c3c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1df16c0/d .functor AND 1, L_0x1df1780, L_0x1df18e0, C4<1>, C4<1>; -L_0x1df16c0 .delay 1 (30000,30000,30000) L_0x1df16c0/d; -v0x1c0c480_0 .net *"_s0", 0 0, L_0x1df1780; 1 drivers -v0x1c0c560_0 .net *"_s1", 0 0, L_0x1df18e0; 1 drivers -S_0x1c0c640 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0c880 .param/l "i" 0 4 54, +C4<010>; -L_0x1df19d0/d .functor AND 1, L_0x1df1a90, L_0x1df1bf0, C4<1>, C4<1>; -L_0x1df19d0 .delay 1 (30000,30000,30000) L_0x1df19d0/d; -v0x1c0c920_0 .net *"_s0", 0 0, L_0x1df1a90; 1 drivers -v0x1c0ca00_0 .net *"_s1", 0 0, L_0x1df1bf0; 1 drivers -S_0x1c0cae0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0ccf0 .param/l "i" 0 4 54, +C4<011>; -L_0x1df1ce0/d .functor AND 1, L_0x1df1da0, L_0x1df1f00, C4<1>, C4<1>; -L_0x1df1ce0 .delay 1 (30000,30000,30000) L_0x1df1ce0/d; -v0x1c0cdb0_0 .net *"_s0", 0 0, L_0x1df1da0; 1 drivers -v0x1c0ce90_0 .net *"_s1", 0 0, L_0x1df1f00; 1 drivers -S_0x1c0cf70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0d1d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1df2040/d .functor AND 1, L_0x1df2100, L_0x1df2370, C4<1>, C4<1>; -L_0x1df2040 .delay 1 (30000,30000,30000) L_0x1df2040/d; -v0x1c0d290_0 .net *"_s0", 0 0, L_0x1df2100; 1 drivers -v0x1c0d370_0 .net *"_s1", 0 0, L_0x1df2370; 1 drivers -S_0x1c0d450 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0d660 .param/l "i" 0 4 54, +C4<0101>; -L_0x1df2410/d .functor AND 1, L_0x1df2480, L_0x1df25e0, C4<1>, C4<1>; -L_0x1df2410 .delay 1 (30000,30000,30000) L_0x1df2410/d; -v0x1c0d720_0 .net *"_s0", 0 0, L_0x1df2480; 1 drivers -v0x1c0d800_0 .net *"_s1", 0 0, L_0x1df25e0; 1 drivers -S_0x1c0d8e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0daf0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1df2740/d .functor AND 1, L_0x1df2800, L_0x1df2960, C4<1>, C4<1>; -L_0x1df2740 .delay 1 (30000,30000,30000) L_0x1df2740/d; -v0x1c0dbb0_0 .net *"_s0", 0 0, L_0x1df2800; 1 drivers -v0x1c0dc90_0 .net *"_s1", 0 0, L_0x1df2960; 1 drivers -S_0x1c0dd70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c0bac0; - .timescale -9 -12; -P_0x1c0df80 .param/l "i" 0 4 54, +C4<0111>; -L_0x1df26d0/d .functor AND 1, L_0x1df2e10, L_0x1df3000, C4<1>, C4<1>; -L_0x1df26d0 .delay 1 (30000,30000,30000) L_0x1df26d0/d; -v0x1c0e040_0 .net *"_s0", 0 0, L_0x1df2e10; 1 drivers -v0x1c0e120_0 .net *"_s1", 0 0, L_0x1df3000; 1 drivers -S_0x1c0ece0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c0b870; +v0x10a0e80_0 .net "A", 7 0, L_0x12845f0; alias, 1 drivers +v0x10a0f80_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10a1040_0 .net *"_s0", 0 0, L_0x1284980; 1 drivers +v0x10a1100_0 .net *"_s12", 0 0, L_0x1285340; 1 drivers +v0x10a11e0_0 .net *"_s16", 0 0, L_0x12856a0; 1 drivers +v0x10a1310_0 .net *"_s20", 0 0, L_0x1285ad0; 1 drivers +v0x10a13f0_0 .net *"_s24", 0 0, L_0x1285e00; 1 drivers +v0x10a14d0_0 .net *"_s28", 0 0, L_0x1285d90; 1 drivers +v0x10a15b0_0 .net *"_s4", 0 0, L_0x1284d20; 1 drivers +v0x10a1720_0 .net *"_s8", 0 0, L_0x1285030; 1 drivers +v0x10a1800_0 .net "out", 7 0, L_0x1286190; alias, 1 drivers +L_0x1284a90 .part L_0x12845f0, 0, 1; +L_0x1284c80 .part v0x12010b0_0, 0, 1; +L_0x1284de0 .part L_0x12845f0, 1, 1; +L_0x1284f40 .part v0x12010b0_0, 1, 1; +L_0x12850f0 .part L_0x12845f0, 2, 1; +L_0x1285250 .part v0x12010b0_0, 2, 1; +L_0x1285400 .part L_0x12845f0, 3, 1; +L_0x1285560 .part v0x12010b0_0, 3, 1; +L_0x1285760 .part L_0x12845f0, 4, 1; +L_0x12859d0 .part v0x12010b0_0, 4, 1; +L_0x1285b40 .part L_0x12845f0, 5, 1; +L_0x1285ca0 .part v0x12010b0_0, 5, 1; +L_0x1285ec0 .part L_0x12845f0, 6, 1; +L_0x1286020 .part v0x12010b0_0, 6, 1; +LS_0x1286190_0_0 .concat8 [ 1 1 1 1], L_0x1284980, L_0x1284d20, L_0x1285030, L_0x1285340; +LS_0x1286190_0_4 .concat8 [ 1 1 1 1], L_0x12856a0, L_0x1285ad0, L_0x1285e00, L_0x1285d90; +L_0x1286190 .concat8 [ 4 4 0 0], LS_0x1286190_0_0, LS_0x1286190_0_4; +L_0x1286550 .part L_0x12845f0, 7, 1; +L_0x1286740 .part v0x12010b0_0, 7, 1; +S_0x109e980 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x109eb90 .param/l "i" 0 4 54, +C4<00>; +L_0x1284980/d .functor AND 1, L_0x1284a90, L_0x1284c80, C4<1>, C4<1>; +L_0x1284980 .delay 1 (30000,30000,30000) L_0x1284980/d; +v0x109ec70_0 .net *"_s0", 0 0, L_0x1284a90; 1 drivers +v0x109ed50_0 .net *"_s1", 0 0, L_0x1284c80; 1 drivers +S_0x109ee30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x109f040 .param/l "i" 0 4 54, +C4<01>; +L_0x1284d20/d .functor AND 1, L_0x1284de0, L_0x1284f40, C4<1>, C4<1>; +L_0x1284d20 .delay 1 (30000,30000,30000) L_0x1284d20/d; +v0x109f100_0 .net *"_s0", 0 0, L_0x1284de0; 1 drivers +v0x109f1e0_0 .net *"_s1", 0 0, L_0x1284f40; 1 drivers +S_0x109f2c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x109f500 .param/l "i" 0 4 54, +C4<010>; +L_0x1285030/d .functor AND 1, L_0x12850f0, L_0x1285250, C4<1>, C4<1>; +L_0x1285030 .delay 1 (30000,30000,30000) L_0x1285030/d; +v0x109f5a0_0 .net *"_s0", 0 0, L_0x12850f0; 1 drivers +v0x109f680_0 .net *"_s1", 0 0, L_0x1285250; 1 drivers +S_0x109f760 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x109f970 .param/l "i" 0 4 54, +C4<011>; +L_0x1285340/d .functor AND 1, L_0x1285400, L_0x1285560, C4<1>, C4<1>; +L_0x1285340 .delay 1 (30000,30000,30000) L_0x1285340/d; +v0x109fa30_0 .net *"_s0", 0 0, L_0x1285400; 1 drivers +v0x109fb10_0 .net *"_s1", 0 0, L_0x1285560; 1 drivers +S_0x109fbf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x109fe50 .param/l "i" 0 4 54, +C4<0100>; +L_0x12856a0/d .functor AND 1, L_0x1285760, L_0x12859d0, C4<1>, C4<1>; +L_0x12856a0 .delay 1 (30000,30000,30000) L_0x12856a0/d; +v0x109ff10_0 .net *"_s0", 0 0, L_0x1285760; 1 drivers +v0x109fff0_0 .net *"_s1", 0 0, L_0x12859d0; 1 drivers +S_0x10a00d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x10a02e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1285ad0/d .functor AND 1, L_0x1285b40, L_0x1285ca0, C4<1>, C4<1>; +L_0x1285ad0 .delay 1 (30000,30000,30000) L_0x1285ad0/d; +v0x10a03a0_0 .net *"_s0", 0 0, L_0x1285b40; 1 drivers +v0x10a0480_0 .net *"_s1", 0 0, L_0x1285ca0; 1 drivers +S_0x10a0560 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x10a0770 .param/l "i" 0 4 54, +C4<0110>; +L_0x1285e00/d .functor AND 1, L_0x1285ec0, L_0x1286020, C4<1>, C4<1>; +L_0x1285e00 .delay 1 (30000,30000,30000) L_0x1285e00/d; +v0x10a0830_0 .net *"_s0", 0 0, L_0x1285ec0; 1 drivers +v0x10a0910_0 .net *"_s1", 0 0, L_0x1286020; 1 drivers +S_0x10a09f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x109e740; + .timescale -9 -12; +P_0x10a0c00 .param/l "i" 0 4 54, +C4<0111>; +L_0x1285d90/d .functor AND 1, L_0x1286550, L_0x1286740, C4<1>, C4<1>; +L_0x1285d90 .delay 1 (30000,30000,30000) L_0x1285d90/d; +v0x10a0cc0_0 .net *"_s0", 0 0, L_0x1286550; 1 drivers +v0x10a0da0_0 .net *"_s1", 0 0, L_0x1286740; 1 drivers +S_0x10a1960 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x109e4f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1df4a50/d .functor OR 1, L_0x1df4b10, L_0x1df4cc0, C4<0>, C4<0>; -L_0x1df4a50 .delay 1 (30000,30000,30000) L_0x1df4a50/d; -v0x1c10830_0 .net *"_s10", 0 0, L_0x1df4b10; 1 drivers -v0x1c10910_0 .net *"_s12", 0 0, L_0x1df4cc0; 1 drivers -v0x1c109f0_0 .net "in", 7 0, L_0x1df2a50; alias, 1 drivers -v0x1c10ac0_0 .net "ors", 1 0, L_0x1df4870; 1 drivers -v0x1c10b80_0 .net "out", 0 0, L_0x1df4a50; alias, 1 drivers -L_0x1df3c40 .part L_0x1df2a50, 0, 4; -L_0x1df4870 .concat8 [ 1 1 0 0], L_0x1df3930, L_0x1df4560; -L_0x1df49b0 .part L_0x1df2a50, 4, 4; -L_0x1df4b10 .part L_0x1df4870, 0, 1; -L_0x1df4cc0 .part L_0x1df4870, 1, 1; -S_0x1c0eea0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c0ece0; +L_0x1288190/d .functor OR 1, L_0x1288250, L_0x1288400, C4<0>, C4<0>; +L_0x1288190 .delay 1 (30000,30000,30000) L_0x1288190/d; +v0x10a34b0_0 .net *"_s10", 0 0, L_0x1288250; 1 drivers +v0x10a3590_0 .net *"_s12", 0 0, L_0x1288400; 1 drivers +v0x10a3670_0 .net "in", 7 0, L_0x1286190; alias, 1 drivers +v0x10a3740_0 .net "ors", 1 0, L_0x1287fb0; 1 drivers +v0x10a3800_0 .net "out", 0 0, L_0x1288190; alias, 1 drivers +L_0x1287380 .part L_0x1286190, 0, 4; +L_0x1287fb0 .concat8 [ 1 1 0 0], L_0x1287070, L_0x1287ca0; +L_0x12880f0 .part L_0x1286190, 4, 4; +L_0x1288250 .part L_0x1287fb0, 0, 1; +L_0x1288400 .part L_0x1287fb0, 1, 1; +S_0x10a1b20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10a1960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1df30f0/d .functor OR 1, L_0x1df31b0, L_0x1df3310, C4<0>, C4<0>; -L_0x1df30f0 .delay 1 (30000,30000,30000) L_0x1df30f0/d; -L_0x1df3540/d .functor OR 1, L_0x1df3650, L_0x1df37b0, C4<0>, C4<0>; -L_0x1df3540 .delay 1 (30000,30000,30000) L_0x1df3540/d; -L_0x1df3930/d .functor OR 1, L_0x1df39a0, L_0x1df3b50, C4<0>, C4<0>; -L_0x1df3930 .delay 1 (30000,30000,30000) L_0x1df3930/d; -v0x1c0f0f0_0 .net *"_s0", 0 0, L_0x1df30f0; 1 drivers -v0x1c0f1f0_0 .net *"_s10", 0 0, L_0x1df3650; 1 drivers -v0x1c0f2d0_0 .net *"_s12", 0 0, L_0x1df37b0; 1 drivers -v0x1c0f390_0 .net *"_s14", 0 0, L_0x1df39a0; 1 drivers -v0x1c0f470_0 .net *"_s16", 0 0, L_0x1df3b50; 1 drivers -v0x1c0f5a0_0 .net *"_s3", 0 0, L_0x1df31b0; 1 drivers -v0x1c0f680_0 .net *"_s5", 0 0, L_0x1df3310; 1 drivers -v0x1c0f760_0 .net *"_s6", 0 0, L_0x1df3540; 1 drivers -v0x1c0f840_0 .net "in", 3 0, L_0x1df3c40; 1 drivers -v0x1c0f9b0_0 .net "ors", 1 0, L_0x1df3450; 1 drivers -v0x1c0fa90_0 .net "out", 0 0, L_0x1df3930; 1 drivers -L_0x1df31b0 .part L_0x1df3c40, 0, 1; -L_0x1df3310 .part L_0x1df3c40, 1, 1; -L_0x1df3450 .concat8 [ 1 1 0 0], L_0x1df30f0, L_0x1df3540; -L_0x1df3650 .part L_0x1df3c40, 2, 1; -L_0x1df37b0 .part L_0x1df3c40, 3, 1; -L_0x1df39a0 .part L_0x1df3450, 0, 1; -L_0x1df3b50 .part L_0x1df3450, 1, 1; -S_0x1c0fbb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c0ece0; +L_0x1286830/d .functor OR 1, L_0x12868f0, L_0x1286a50, C4<0>, C4<0>; +L_0x1286830 .delay 1 (30000,30000,30000) L_0x1286830/d; +L_0x1286c80/d .functor OR 1, L_0x1286d90, L_0x1286ef0, C4<0>, C4<0>; +L_0x1286c80 .delay 1 (30000,30000,30000) L_0x1286c80/d; +L_0x1287070/d .functor OR 1, L_0x12870e0, L_0x1287290, C4<0>, C4<0>; +L_0x1287070 .delay 1 (30000,30000,30000) L_0x1287070/d; +v0x10a1d70_0 .net *"_s0", 0 0, L_0x1286830; 1 drivers +v0x10a1e70_0 .net *"_s10", 0 0, L_0x1286d90; 1 drivers +v0x10a1f50_0 .net *"_s12", 0 0, L_0x1286ef0; 1 drivers +v0x10a2010_0 .net *"_s14", 0 0, L_0x12870e0; 1 drivers +v0x10a20f0_0 .net *"_s16", 0 0, L_0x1287290; 1 drivers +v0x10a2220_0 .net *"_s3", 0 0, L_0x12868f0; 1 drivers +v0x10a2300_0 .net *"_s5", 0 0, L_0x1286a50; 1 drivers +v0x10a23e0_0 .net *"_s6", 0 0, L_0x1286c80; 1 drivers +v0x10a24c0_0 .net "in", 3 0, L_0x1287380; 1 drivers +v0x10a2630_0 .net "ors", 1 0, L_0x1286b90; 1 drivers +v0x10a2710_0 .net "out", 0 0, L_0x1287070; 1 drivers +L_0x12868f0 .part L_0x1287380, 0, 1; +L_0x1286a50 .part L_0x1287380, 1, 1; +L_0x1286b90 .concat8 [ 1 1 0 0], L_0x1286830, L_0x1286c80; +L_0x1286d90 .part L_0x1287380, 2, 1; +L_0x1286ef0 .part L_0x1287380, 3, 1; +L_0x12870e0 .part L_0x1286b90, 0, 1; +L_0x1287290 .part L_0x1286b90, 1, 1; +S_0x10a2830 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10a1960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1df3d70/d .functor OR 1, L_0x1df3de0, L_0x1df3f40, C4<0>, C4<0>; -L_0x1df3d70 .delay 1 (30000,30000,30000) L_0x1df3d70/d; -L_0x1df4170/d .functor OR 1, L_0x1df4280, L_0x1df43e0, C4<0>, C4<0>; -L_0x1df4170 .delay 1 (30000,30000,30000) L_0x1df4170/d; -L_0x1df4560/d .functor OR 1, L_0x1df45d0, L_0x1df4780, C4<0>, C4<0>; -L_0x1df4560 .delay 1 (30000,30000,30000) L_0x1df4560/d; -v0x1c0fd70_0 .net *"_s0", 0 0, L_0x1df3d70; 1 drivers -v0x1c0fe70_0 .net *"_s10", 0 0, L_0x1df4280; 1 drivers -v0x1c0ff50_0 .net *"_s12", 0 0, L_0x1df43e0; 1 drivers -v0x1c10010_0 .net *"_s14", 0 0, L_0x1df45d0; 1 drivers -v0x1c100f0_0 .net *"_s16", 0 0, L_0x1df4780; 1 drivers -v0x1c10220_0 .net *"_s3", 0 0, L_0x1df3de0; 1 drivers -v0x1c10300_0 .net *"_s5", 0 0, L_0x1df3f40; 1 drivers -v0x1c103e0_0 .net *"_s6", 0 0, L_0x1df4170; 1 drivers -v0x1c104c0_0 .net "in", 3 0, L_0x1df49b0; 1 drivers -v0x1c10630_0 .net "ors", 1 0, L_0x1df4080; 1 drivers -v0x1c10710_0 .net "out", 0 0, L_0x1df4560; 1 drivers -L_0x1df3de0 .part L_0x1df49b0, 0, 1; -L_0x1df3f40 .part L_0x1df49b0, 1, 1; -L_0x1df4080 .concat8 [ 1 1 0 0], L_0x1df3d70, L_0x1df4170; -L_0x1df4280 .part L_0x1df49b0, 2, 1; -L_0x1df43e0 .part L_0x1df49b0, 3, 1; -L_0x1df45d0 .part L_0x1df4080, 0, 1; -L_0x1df4780 .part L_0x1df4080, 1, 1; -S_0x1c11020 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c04910; +L_0x12874b0/d .functor OR 1, L_0x1287520, L_0x1287680, C4<0>, C4<0>; +L_0x12874b0 .delay 1 (30000,30000,30000) L_0x12874b0/d; +L_0x12878b0/d .functor OR 1, L_0x12879c0, L_0x1287b20, C4<0>, C4<0>; +L_0x12878b0 .delay 1 (30000,30000,30000) L_0x12878b0/d; +L_0x1287ca0/d .functor OR 1, L_0x1287d10, L_0x1287ec0, C4<0>, C4<0>; +L_0x1287ca0 .delay 1 (30000,30000,30000) L_0x1287ca0/d; +v0x10a29f0_0 .net *"_s0", 0 0, L_0x12874b0; 1 drivers +v0x10a2af0_0 .net *"_s10", 0 0, L_0x12879c0; 1 drivers +v0x10a2bd0_0 .net *"_s12", 0 0, L_0x1287b20; 1 drivers +v0x10a2c90_0 .net *"_s14", 0 0, L_0x1287d10; 1 drivers +v0x10a2d70_0 .net *"_s16", 0 0, L_0x1287ec0; 1 drivers +v0x10a2ea0_0 .net *"_s3", 0 0, L_0x1287520; 1 drivers +v0x10a2f80_0 .net *"_s5", 0 0, L_0x1287680; 1 drivers +v0x10a3060_0 .net *"_s6", 0 0, L_0x12878b0; 1 drivers +v0x10a3140_0 .net "in", 3 0, L_0x12880f0; 1 drivers +v0x10a32b0_0 .net "ors", 1 0, L_0x12877c0; 1 drivers +v0x10a3390_0 .net "out", 0 0, L_0x1287ca0; 1 drivers +L_0x1287520 .part L_0x12880f0, 0, 1; +L_0x1287680 .part L_0x12880f0, 1, 1; +L_0x12877c0 .concat8 [ 1 1 0 0], L_0x12874b0, L_0x12878b0; +L_0x12879c0 .part L_0x12880f0, 2, 1; +L_0x1287b20 .part L_0x12880f0, 3, 1; +L_0x1287d10 .part L_0x12877c0, 0, 1; +L_0x1287ec0 .part L_0x12877c0, 1, 1; +S_0x10a3ca0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1097590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -7564,80 +7574,80 @@ S_0x1c11020 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c04910; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1df0300/d .functor XNOR 1, L_0x1df88f0, L_0x1deeeb0, C4<0>, C4<0>; -L_0x1df0300 .delay 1 (20000,20000,20000) L_0x1df0300/d; -L_0x1df0570/d .functor AND 1, L_0x1df88f0, L_0x1def1f0, C4<1>, C4<1>; -L_0x1df0570 .delay 1 (30000,30000,30000) L_0x1df0570/d; -L_0x1df05e0/d .functor AND 1, L_0x1df0300, L_0x1deef50, C4<1>, C4<1>; -L_0x1df05e0 .delay 1 (30000,30000,30000) L_0x1df05e0/d; -L_0x1df0740/d .functor OR 1, L_0x1df05e0, L_0x1df0570, C4<0>, C4<0>; -L_0x1df0740 .delay 1 (30000,30000,30000) L_0x1df0740/d; -v0x1c112d0_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers -v0x1c113c0_0 .net "a_", 0 0, L_0x1def090; alias, 1 drivers -v0x1c11480_0 .net "b", 0 0, L_0x1deeeb0; alias, 1 drivers -v0x1c11570_0 .net "b_", 0 0, L_0x1def1f0; alias, 1 drivers -v0x1c11610_0 .net "carryin", 0 0, L_0x1deef50; alias, 1 drivers -v0x1c11750_0 .net "eq", 0 0, L_0x1df0300; 1 drivers -v0x1c11810_0 .net "lt", 0 0, L_0x1df0570; 1 drivers -v0x1c118d0_0 .net "out", 0 0, L_0x1df0740; 1 drivers -v0x1c11990_0 .net "w0", 0 0, L_0x1df05e0; 1 drivers -S_0x1c11be0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c04910; +L_0x1283960/d .functor XNOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; +L_0x1283960 .delay 1 (20000,20000,20000) L_0x1283960/d; +L_0x1283bd0/d .functor AND 1, L_0x128c030, L_0x1282960, C4<1>, C4<1>; +L_0x1283bd0 .delay 1 (30000,30000,30000) L_0x1283bd0/d; +L_0x1283c40/d .functor AND 1, L_0x1283960, L_0x12826c0, C4<1>, C4<1>; +L_0x1283c40 .delay 1 (30000,30000,30000) L_0x1283c40/d; +L_0x1283da0/d .functor OR 1, L_0x1283c40, L_0x1283bd0, C4<0>, C4<0>; +L_0x1283da0 .delay 1 (30000,30000,30000) L_0x1283da0/d; +v0x10a3f50_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers +v0x10a4040_0 .net "a_", 0 0, L_0x1282800; alias, 1 drivers +v0x10a4100_0 .net "b", 0 0, L_0x1282620; alias, 1 drivers +v0x10a41f0_0 .net "b_", 0 0, L_0x1282960; alias, 1 drivers +v0x10a4290_0 .net "carryin", 0 0, L_0x12826c0; alias, 1 drivers +v0x10a43d0_0 .net "eq", 0 0, L_0x1283960; 1 drivers +v0x10a4490_0 .net "lt", 0 0, L_0x1283bd0; 1 drivers +v0x10a4550_0 .net "out", 0 0, L_0x1283da0; 1 drivers +v0x10a4610_0 .net "w0", 0 0, L_0x1283c40; 1 drivers +S_0x10a4860 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1097590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1df00e0/d .functor OR 1, L_0x1defbe0, L_0x1c12e40, C4<0>, C4<0>; -L_0x1df00e0 .delay 1 (30000,30000,30000) L_0x1df00e0/d; -v0x1c129d0_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers -v0x1c12b20_0 .net "b", 0 0, L_0x1def1f0; alias, 1 drivers -v0x1c12be0_0 .net "c1", 0 0, L_0x1defbe0; 1 drivers -v0x1c12c80_0 .net "c2", 0 0, L_0x1c12e40; 1 drivers -v0x1c12d50_0 .net "carryin", 0 0, L_0x1deef50; alias, 1 drivers -v0x1c12ed0_0 .net "carryout", 0 0, L_0x1df00e0; 1 drivers -v0x1c12f70_0 .net "s1", 0 0, L_0x1defb20; 1 drivers -v0x1c13010_0 .net "sum", 0 0, L_0x1defd40; 1 drivers -S_0x1c11e30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c11be0; +L_0x1283740/d .functor OR 1, L_0x1283290, L_0x10a5ac0, C4<0>, C4<0>; +L_0x1283740 .delay 1 (30000,30000,30000) L_0x1283740/d; +v0x10a5650_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers +v0x10a57a0_0 .net "b", 0 0, L_0x1282960; alias, 1 drivers +v0x10a5860_0 .net "c1", 0 0, L_0x1283290; 1 drivers +v0x10a5900_0 .net "c2", 0 0, L_0x10a5ac0; 1 drivers +v0x10a59d0_0 .net "carryin", 0 0, L_0x12826c0; alias, 1 drivers +v0x10a5b50_0 .net "carryout", 0 0, L_0x1283740; 1 drivers +v0x10a5bf0_0 .net "s1", 0 0, L_0x12831d0; 1 drivers +v0x10a5c90_0 .net "sum", 0 0, L_0x12833f0; 1 drivers +S_0x10a4ab0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10a4860; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1defb20/d .functor XOR 1, L_0x1df88f0, L_0x1def1f0, C4<0>, C4<0>; -L_0x1defb20 .delay 1 (30000,30000,30000) L_0x1defb20/d; -L_0x1defbe0/d .functor AND 1, L_0x1df88f0, L_0x1def1f0, C4<1>, C4<1>; -L_0x1defbe0 .delay 1 (30000,30000,30000) L_0x1defbe0/d; -v0x1c12090_0 .net "a", 0 0, L_0x1df88f0; alias, 1 drivers -v0x1c12150_0 .net "b", 0 0, L_0x1def1f0; alias, 1 drivers -v0x1c12210_0 .net "carryout", 0 0, L_0x1defbe0; alias, 1 drivers -v0x1c122b0_0 .net "sum", 0 0, L_0x1defb20; alias, 1 drivers -S_0x1c123e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c11be0; +L_0x12831d0/d .functor XOR 1, L_0x128c030, L_0x1282960, C4<0>, C4<0>; +L_0x12831d0 .delay 1 (30000,30000,30000) L_0x12831d0/d; +L_0x1283290/d .functor AND 1, L_0x128c030, L_0x1282960, C4<1>, C4<1>; +L_0x1283290 .delay 1 (30000,30000,30000) L_0x1283290/d; +v0x10a4d10_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers +v0x10a4dd0_0 .net "b", 0 0, L_0x1282960; alias, 1 drivers +v0x10a4e90_0 .net "carryout", 0 0, L_0x1283290; alias, 1 drivers +v0x10a4f30_0 .net "sum", 0 0, L_0x12831d0; alias, 1 drivers +S_0x10a5060 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10a4860; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1defd40/d .functor XOR 1, L_0x1defb20, L_0x1deef50, C4<0>, C4<0>; -L_0x1defd40 .delay 1 (30000,30000,30000) L_0x1defd40/d; -L_0x1c12e40/d .functor AND 1, L_0x1defb20, L_0x1deef50, C4<1>, C4<1>; -L_0x1c12e40 .delay 1 (30000,30000,30000) L_0x1c12e40/d; -v0x1c12640_0 .net "a", 0 0, L_0x1defb20; alias, 1 drivers -v0x1c12710_0 .net "b", 0 0, L_0x1deef50; alias, 1 drivers -v0x1c127b0_0 .net "carryout", 0 0, L_0x1c12e40; alias, 1 drivers -v0x1c12880_0 .net "sum", 0 0, L_0x1defd40; alias, 1 drivers -S_0x1c14430 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c04640; - .timescale -9 -12; -L_0x7f72592daeb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592daf00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1df8990/d .functor OR 1, L_0x7f72592daeb8, L_0x7f72592daf00, C4<0>, C4<0>; -L_0x1df8990 .delay 1 (30000,30000,30000) L_0x1df8990/d; -v0x1c14620_0 .net/2u *"_s0", 0 0, L_0x7f72592daeb8; 1 drivers -v0x1c14700_0 .net/2u *"_s2", 0 0, L_0x7f72592daf00; 1 drivers -S_0x1c147e0 .scope generate, "alu_slices[14]" "alu_slices[14]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c149f0 .param/l "i" 0 3 37, +C4<01110>; -S_0x1c14ab0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c147e0; +L_0x12833f0/d .functor XOR 1, L_0x12831d0, L_0x12826c0, C4<0>, C4<0>; +L_0x12833f0 .delay 1 (30000,30000,30000) L_0x12833f0/d; +L_0x10a5ac0/d .functor AND 1, L_0x12831d0, L_0x12826c0, C4<1>, C4<1>; +L_0x10a5ac0 .delay 1 (30000,30000,30000) L_0x10a5ac0/d; +v0x10a52c0_0 .net "a", 0 0, L_0x12831d0; alias, 1 drivers +v0x10a5390_0 .net "b", 0 0, L_0x12826c0; alias, 1 drivers +v0x10a5430_0 .net "carryout", 0 0, L_0x10a5ac0; alias, 1 drivers +v0x10a5500_0 .net "sum", 0 0, L_0x12833f0; alias, 1 drivers +S_0x10a70b0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10972c0; + .timescale -9 -12; +L_0x2b0ab3d05eb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05f00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x128c0d0/d .functor OR 1, L_0x2b0ab3d05eb8, L_0x2b0ab3d05f00, C4<0>, C4<0>; +L_0x128c0d0 .delay 1 (30000,30000,30000) L_0x128c0d0/d; +v0x10a72a0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05eb8; 1 drivers +v0x10a7380_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05f00; 1 drivers +S_0x10a7460 .scope generate, "alu_slices[14]" "alu_slices[14]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x10a7670 .param/l "i" 0 3 41, +C4<01110>; +S_0x10a7730 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10a7460; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -7646,445 +7656,445 @@ S_0x1c14ab0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c147e0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1df8ca0/d .functor NOT 1, L_0x1e024d0, C4<0>, C4<0>, C4<0>; -L_0x1df8ca0 .delay 1 (10000,10000,10000) L_0x1df8ca0/d; -L_0x1df8e00/d .functor NOT 1, L_0x1db4230, C4<0>, C4<0>, C4<0>; -L_0x1df8e00 .delay 1 (10000,10000,10000) L_0x1df8e00/d; -L_0x1df9e50/d .functor XOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; -L_0x1df9e50 .delay 1 (30000,30000,30000) L_0x1df9e50/d; -L_0x7f72592daf48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592daf90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1dfa3f0/d .functor OR 1, L_0x7f72592daf48, L_0x7f72592daf90, C4<0>, C4<0>; -L_0x1dfa3f0 .delay 1 (30000,30000,30000) L_0x1dfa3f0/d; -L_0x1dfa5f0/d .functor AND 1, L_0x1e024d0, L_0x1db4230, C4<1>, C4<1>; -L_0x1dfa5f0 .delay 1 (30000,30000,30000) L_0x1dfa5f0/d; -L_0x1dfa6b0/d .functor NAND 1, L_0x1e024d0, L_0x1db4230, C4<1>, C4<1>; -L_0x1dfa6b0 .delay 1 (20000,20000,20000) L_0x1dfa6b0/d; -L_0x1dfa810/d .functor XOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; -L_0x1dfa810 .delay 1 (20000,20000,20000) L_0x1dfa810/d; -L_0x1dfacc0/d .functor OR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; -L_0x1dfacc0 .delay 1 (30000,30000,30000) L_0x1dfacc0/d; -L_0x1e023d0/d .functor NOT 1, L_0x1dfe630, C4<0>, C4<0>, C4<0>; -L_0x1e023d0 .delay 1 (10000,10000,10000) L_0x1e023d0/d; -v0x1c231e0_0 .net "A", 0 0, L_0x1e024d0; 1 drivers -v0x1c232a0_0 .net "A_", 0 0, L_0x1df8ca0; 1 drivers -v0x1c23360_0 .net "B", 0 0, L_0x1db4230; 1 drivers -v0x1c23430_0 .net "B_", 0 0, L_0x1df8e00; 1 drivers -v0x1c234d0_0 .net *"_s12", 0 0, L_0x1dfa3f0; 1 drivers -v0x1c235c0_0 .net/2s *"_s14", 0 0, L_0x7f72592daf48; 1 drivers -v0x1c23680_0 .net/2s *"_s16", 0 0, L_0x7f72592daf90; 1 drivers -v0x1c23760_0 .net *"_s18", 0 0, L_0x1dfa5f0; 1 drivers -v0x1c23840_0 .net *"_s20", 0 0, L_0x1dfa6b0; 1 drivers -v0x1c239b0_0 .net *"_s22", 0 0, L_0x1dfa810; 1 drivers -v0x1c23a90_0 .net *"_s24", 0 0, L_0x1dfacc0; 1 drivers -o0x7f7259376d28 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c23b70_0 name=_s30 -o0x7f7259376d58 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c23c50_0 name=_s32 -v0x1c23d30_0 .net *"_s8", 0 0, L_0x1df9e50; 1 drivers -v0x1c23e10_0 .net "carryin", 0 0, L_0x1db43e0; 1 drivers -v0x1c23eb0_0 .net "carryout", 0 0, L_0x1e02070; 1 drivers -v0x1c23f50_0 .net "carryouts", 7 0, L_0x1ec0250; 1 drivers -v0x1c24100_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c241a0_0 .net "result", 0 0, L_0x1dfe630; 1 drivers -v0x1c24290_0 .net "results", 7 0, L_0x1dfaa90; 1 drivers -v0x1c243a0_0 .net "zero", 0 0, L_0x1e023d0; 1 drivers -LS_0x1dfaa90_0_0 .concat8 [ 1 1 1 1], L_0x1df9320, L_0x1df9950, L_0x1df9e50, L_0x1dfa3f0; -LS_0x1dfaa90_0_4 .concat8 [ 1 1 1 1], L_0x1dfa5f0, L_0x1dfa6b0, L_0x1dfa810, L_0x1dfacc0; -L_0x1dfaa90 .concat8 [ 4 4 0 0], LS_0x1dfaa90_0_0, LS_0x1dfaa90_0_4; -LS_0x1ec0250_0_0 .concat [ 1 1 1 1], L_0x1df95d0, L_0x1df9cf0, o0x7f7259376d28, L_0x1dfa240; -LS_0x1ec0250_0_4 .concat [ 4 0 0 0], o0x7f7259376d58; -L_0x1ec0250 .concat [ 4 4 0 0], LS_0x1ec0250_0_0, LS_0x1ec0250_0_4; -S_0x1c14d30 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c14ab0; +L_0x128c3e0/d .functor NOT 1, L_0x1295b80, C4<0>, C4<0>, C4<0>; +L_0x128c3e0 .delay 1 (10000,10000,10000) L_0x128c3e0/d; +L_0x128c540/d .functor NOT 1, L_0x1247990, C4<0>, C4<0>, C4<0>; +L_0x128c540 .delay 1 (10000,10000,10000) L_0x128c540/d; +L_0x128d590/d .functor XOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; +L_0x128d590 .delay 1 (30000,30000,30000) L_0x128d590/d; +L_0x2b0ab3d05f48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d05f90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x128dc40/d .functor OR 1, L_0x2b0ab3d05f48, L_0x2b0ab3d05f90, C4<0>, C4<0>; +L_0x128dc40 .delay 1 (30000,30000,30000) L_0x128dc40/d; +L_0x128de40/d .functor AND 1, L_0x1295b80, L_0x1247990, C4<1>, C4<1>; +L_0x128de40 .delay 1 (30000,30000,30000) L_0x128de40/d; +L_0x128df00/d .functor NAND 1, L_0x1295b80, L_0x1247990, C4<1>, C4<1>; +L_0x128df00 .delay 1 (20000,20000,20000) L_0x128df00/d; +L_0x128e060/d .functor XOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; +L_0x128e060 .delay 1 (20000,20000,20000) L_0x128e060/d; +L_0x128e510/d .functor OR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; +L_0x128e510 .delay 1 (30000,30000,30000) L_0x128e510/d; +L_0x1295a80/d .functor NOT 1, L_0x1291da0, C4<0>, C4<0>, C4<0>; +L_0x1295a80 .delay 1 (10000,10000,10000) L_0x1295a80/d; +v0x10b5e60_0 .net "A", 0 0, L_0x1295b80; 1 drivers +v0x10b5f20_0 .net "A_", 0 0, L_0x128c3e0; 1 drivers +v0x10b5fe0_0 .net "B", 0 0, L_0x1247990; 1 drivers +v0x10b60b0_0 .net "B_", 0 0, L_0x128c540; 1 drivers +v0x10b6150_0 .net *"_s12", 0 0, L_0x128dc40; 1 drivers +v0x10b6240_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05f48; 1 drivers +v0x10b6300_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05f90; 1 drivers +v0x10b63e0_0 .net *"_s18", 0 0, L_0x128de40; 1 drivers +v0x10b64c0_0 .net *"_s20", 0 0, L_0x128df00; 1 drivers +v0x10b6630_0 .net *"_s22", 0 0, L_0x128e060; 1 drivers +v0x10b6710_0 .net *"_s24", 0 0, L_0x128e510; 1 drivers +o0x2b0ab3cc5d28 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10b67f0_0 name=_s30 +o0x2b0ab3cc5d58 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10b68d0_0 name=_s32 +v0x10b69b0_0 .net *"_s8", 0 0, L_0x128d590; 1 drivers +v0x10b6a90_0 .net "carryin", 0 0, L_0x1247b40; 1 drivers +v0x10b6b30_0 .net "carryout", 0 0, L_0x1295720; 1 drivers +v0x10b6bd0_0 .net "carryouts", 7 0, L_0x1354580; 1 drivers +v0x10b6d80_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10b6e20_0 .net "result", 0 0, L_0x1291da0; 1 drivers +v0x10b6f10_0 .net "results", 7 0, L_0x128e2e0; 1 drivers +v0x10b7020_0 .net "zero", 0 0, L_0x1295a80; 1 drivers +LS_0x128e2e0_0_0 .concat8 [ 1 1 1 1], L_0x128ca60, L_0x128d090, L_0x128d590, L_0x128dc40; +LS_0x128e2e0_0_4 .concat8 [ 1 1 1 1], L_0x128de40, L_0x128df00, L_0x128e060, L_0x128e510; +L_0x128e2e0 .concat8 [ 4 4 0 0], LS_0x128e2e0_0_0, LS_0x128e2e0_0_4; +LS_0x1354580_0_0 .concat [ 1 1 1 1], L_0x128cd10, L_0x128d430, o0x2b0ab3cc5d28, L_0x128da90; +LS_0x1354580_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc5d58; +L_0x1354580 .concat [ 4 4 0 0], LS_0x1354580_0_0, LS_0x1354580_0_4; +S_0x10a79b0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10a7730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1df95d0/d .functor OR 1, L_0x1df90b0, L_0x1df9470, C4<0>, C4<0>; -L_0x1df95d0 .delay 1 (30000,30000,30000) L_0x1df95d0/d; -v0x1c15b60_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers -v0x1c15c20_0 .net "b", 0 0, L_0x1db4230; alias, 1 drivers -v0x1c15cf0_0 .net "c1", 0 0, L_0x1df90b0; 1 drivers -v0x1c15df0_0 .net "c2", 0 0, L_0x1df9470; 1 drivers -v0x1c15ec0_0 .net "carryin", 0 0, L_0x1db43e0; alias, 1 drivers -v0x1c15fb0_0 .net "carryout", 0 0, L_0x1df95d0; 1 drivers -v0x1c16050_0 .net "s1", 0 0, L_0x1df8ff0; 1 drivers -v0x1c16140_0 .net "sum", 0 0, L_0x1df9320; 1 drivers -S_0x1c14fa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c14d30; +L_0x128cd10/d .functor OR 1, L_0x128c7f0, L_0x128cbb0, C4<0>, C4<0>; +L_0x128cd10 .delay 1 (30000,30000,30000) L_0x128cd10/d; +v0x10a87e0_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers +v0x10a88a0_0 .net "b", 0 0, L_0x1247990; alias, 1 drivers +v0x10a8970_0 .net "c1", 0 0, L_0x128c7f0; 1 drivers +v0x10a8a70_0 .net "c2", 0 0, L_0x128cbb0; 1 drivers +v0x10a8b40_0 .net "carryin", 0 0, L_0x1247b40; alias, 1 drivers +v0x10a8c30_0 .net "carryout", 0 0, L_0x128cd10; 1 drivers +v0x10a8cd0_0 .net "s1", 0 0, L_0x128c730; 1 drivers +v0x10a8dc0_0 .net "sum", 0 0, L_0x128ca60; 1 drivers +S_0x10a7c20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10a79b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1df8ff0/d .functor XOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; -L_0x1df8ff0 .delay 1 (30000,30000,30000) L_0x1df8ff0/d; -L_0x1df90b0/d .functor AND 1, L_0x1e024d0, L_0x1db4230, C4<1>, C4<1>; -L_0x1df90b0 .delay 1 (30000,30000,30000) L_0x1df90b0/d; -v0x1c15200_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers -v0x1c152e0_0 .net "b", 0 0, L_0x1db4230; alias, 1 drivers -v0x1c153a0_0 .net "carryout", 0 0, L_0x1df90b0; alias, 1 drivers -v0x1c15440_0 .net "sum", 0 0, L_0x1df8ff0; alias, 1 drivers -S_0x1c15580 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c14d30; +L_0x128c730/d .functor XOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; +L_0x128c730 .delay 1 (30000,30000,30000) L_0x128c730/d; +L_0x128c7f0/d .functor AND 1, L_0x1295b80, L_0x1247990, C4<1>, C4<1>; +L_0x128c7f0 .delay 1 (30000,30000,30000) L_0x128c7f0/d; +v0x10a7e80_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers +v0x10a7f60_0 .net "b", 0 0, L_0x1247990; alias, 1 drivers +v0x10a8020_0 .net "carryout", 0 0, L_0x128c7f0; alias, 1 drivers +v0x10a80c0_0 .net "sum", 0 0, L_0x128c730; alias, 1 drivers +S_0x10a8200 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10a79b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1df9320/d .functor XOR 1, L_0x1df8ff0, L_0x1db43e0, C4<0>, C4<0>; -L_0x1df9320 .delay 1 (30000,30000,30000) L_0x1df9320/d; -L_0x1df9470/d .functor AND 1, L_0x1df8ff0, L_0x1db43e0, C4<1>, C4<1>; -L_0x1df9470 .delay 1 (30000,30000,30000) L_0x1df9470/d; -v0x1c157e0_0 .net "a", 0 0, L_0x1df8ff0; alias, 1 drivers -v0x1c15880_0 .net "b", 0 0, L_0x1db43e0; alias, 1 drivers -v0x1c15920_0 .net "carryout", 0 0, L_0x1df9470; alias, 1 drivers -v0x1c159f0_0 .net "sum", 0 0, L_0x1df9320; alias, 1 drivers -S_0x1c16210 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c14ab0; +L_0x128ca60/d .functor XOR 1, L_0x128c730, L_0x1247b40, C4<0>, C4<0>; +L_0x128ca60 .delay 1 (30000,30000,30000) L_0x128ca60/d; +L_0x128cbb0/d .functor AND 1, L_0x128c730, L_0x1247b40, C4<1>, C4<1>; +L_0x128cbb0 .delay 1 (30000,30000,30000) L_0x128cbb0/d; +v0x10a8460_0 .net "a", 0 0, L_0x128c730; alias, 1 drivers +v0x10a8500_0 .net "b", 0 0, L_0x1247b40; alias, 1 drivers +v0x10a85a0_0 .net "carryout", 0 0, L_0x128cbb0; alias, 1 drivers +v0x10a8670_0 .net "sum", 0 0, L_0x128ca60; alias, 1 drivers +S_0x10a8e90 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10a7730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c1b600_0 .net "ands", 7 0, L_0x1e00070; 1 drivers -v0x1c1b710_0 .net "in", 7 0, L_0x1ec0250; alias, 1 drivers -v0x1c1b7d0_0 .net "out", 0 0, L_0x1e02070; alias, 1 drivers -v0x1c1b8a0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c16430 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c16210; +v0x10ae280_0 .net "ands", 7 0, L_0x12937e0; 1 drivers +v0x10ae390_0 .net "in", 7 0, L_0x1354580; alias, 1 drivers +v0x10ae450_0 .net "out", 0 0, L_0x1295720; alias, 1 drivers +v0x10ae520_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10a90b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10a8e90; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c18b60_0 .net "A", 7 0, L_0x1ec0250; alias, 1 drivers -v0x1c18c60_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c18d20_0 .net *"_s0", 0 0, L_0x1dfe990; 1 drivers -v0x1c18de0_0 .net *"_s12", 0 0, L_0x1dff300; 1 drivers -v0x1c18ec0_0 .net *"_s16", 0 0, L_0x1dff660; 1 drivers -v0x1c18ff0_0 .net *"_s20", 0 0, L_0x1dff970; 1 drivers -v0x1c190d0_0 .net *"_s24", 0 0, L_0x1dffd60; 1 drivers -v0x1c191b0_0 .net *"_s28", 0 0, L_0x1dffcf0; 1 drivers -v0x1c19290_0 .net *"_s4", 0 0, L_0x1dfeca0; 1 drivers -v0x1c19400_0 .net *"_s8", 0 0, L_0x1dfeff0; 1 drivers -v0x1c194e0_0 .net "out", 7 0, L_0x1e00070; alias, 1 drivers -L_0x1dfea50 .part L_0x1ec0250, 0, 1; -L_0x1dfebb0 .part v0x1d6daa0_0, 0, 1; -L_0x1dfed60 .part L_0x1ec0250, 1, 1; -L_0x1dfef50 .part v0x1d6daa0_0, 1, 1; -L_0x1dff0b0 .part L_0x1ec0250, 2, 1; -L_0x1dff210 .part v0x1d6daa0_0, 2, 1; -L_0x1dff3c0 .part L_0x1ec0250, 3, 1; -L_0x1dff520 .part v0x1d6daa0_0, 3, 1; -L_0x1dff720 .part L_0x1ec0250, 4, 1; -L_0x1dff880 .part v0x1d6daa0_0, 4, 1; -L_0x1dff9e0 .part L_0x1ec0250, 5, 1; -L_0x1dffc50 .part v0x1d6daa0_0, 5, 1; -L_0x1dffe20 .part L_0x1ec0250, 6, 1; -L_0x1dfff80 .part v0x1d6daa0_0, 6, 1; -LS_0x1e00070_0_0 .concat8 [ 1 1 1 1], L_0x1dfe990, L_0x1dfeca0, L_0x1dfeff0, L_0x1dff300; -LS_0x1e00070_0_4 .concat8 [ 1 1 1 1], L_0x1dff660, L_0x1dff970, L_0x1dffd60, L_0x1dffcf0; -L_0x1e00070 .concat8 [ 4 4 0 0], LS_0x1e00070_0_0, LS_0x1e00070_0_4; -L_0x1e00430 .part L_0x1ec0250, 7, 1; -L_0x1e00620 .part v0x1d6daa0_0, 7, 1; -S_0x1c16690 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c168a0 .param/l "i" 0 4 54, +C4<00>; -L_0x1dfe990/d .functor AND 1, L_0x1dfea50, L_0x1dfebb0, C4<1>, C4<1>; -L_0x1dfe990 .delay 1 (30000,30000,30000) L_0x1dfe990/d; -v0x1c16980_0 .net *"_s0", 0 0, L_0x1dfea50; 1 drivers -v0x1c16a60_0 .net *"_s1", 0 0, L_0x1dfebb0; 1 drivers -S_0x1c16b40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c16d50 .param/l "i" 0 4 54, +C4<01>; -L_0x1dfeca0/d .functor AND 1, L_0x1dfed60, L_0x1dfef50, C4<1>, C4<1>; -L_0x1dfeca0 .delay 1 (30000,30000,30000) L_0x1dfeca0/d; -v0x1c16e10_0 .net *"_s0", 0 0, L_0x1dfed60; 1 drivers -v0x1c16ef0_0 .net *"_s1", 0 0, L_0x1dfef50; 1 drivers -S_0x1c16fd0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c171e0 .param/l "i" 0 4 54, +C4<010>; -L_0x1dfeff0/d .functor AND 1, L_0x1dff0b0, L_0x1dff210, C4<1>, C4<1>; -L_0x1dfeff0 .delay 1 (30000,30000,30000) L_0x1dfeff0/d; -v0x1c17280_0 .net *"_s0", 0 0, L_0x1dff0b0; 1 drivers -v0x1c17360_0 .net *"_s1", 0 0, L_0x1dff210; 1 drivers -S_0x1c17440 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c17650 .param/l "i" 0 4 54, +C4<011>; -L_0x1dff300/d .functor AND 1, L_0x1dff3c0, L_0x1dff520, C4<1>, C4<1>; -L_0x1dff300 .delay 1 (30000,30000,30000) L_0x1dff300/d; -v0x1c17710_0 .net *"_s0", 0 0, L_0x1dff3c0; 1 drivers -v0x1c177f0_0 .net *"_s1", 0 0, L_0x1dff520; 1 drivers -S_0x1c178d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c17b30 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dff660/d .functor AND 1, L_0x1dff720, L_0x1dff880, C4<1>, C4<1>; -L_0x1dff660 .delay 1 (30000,30000,30000) L_0x1dff660/d; -v0x1c17bf0_0 .net *"_s0", 0 0, L_0x1dff720; 1 drivers -v0x1c17cd0_0 .net *"_s1", 0 0, L_0x1dff880; 1 drivers -S_0x1c17db0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c17fc0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dff970/d .functor AND 1, L_0x1dff9e0, L_0x1dffc50, C4<1>, C4<1>; -L_0x1dff970 .delay 1 (30000,30000,30000) L_0x1dff970/d; -v0x1c18080_0 .net *"_s0", 0 0, L_0x1dff9e0; 1 drivers -v0x1c18160_0 .net *"_s1", 0 0, L_0x1dffc50; 1 drivers -S_0x1c18240 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c18450 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dffd60/d .functor AND 1, L_0x1dffe20, L_0x1dfff80, C4<1>, C4<1>; -L_0x1dffd60 .delay 1 (30000,30000,30000) L_0x1dffd60/d; -v0x1c18510_0 .net *"_s0", 0 0, L_0x1dffe20; 1 drivers -v0x1c185f0_0 .net *"_s1", 0 0, L_0x1dfff80; 1 drivers -S_0x1c186d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c16430; - .timescale -9 -12; -P_0x1c188e0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dffcf0/d .functor AND 1, L_0x1e00430, L_0x1e00620, C4<1>, C4<1>; -L_0x1dffcf0 .delay 1 (30000,30000,30000) L_0x1dffcf0/d; -v0x1c189a0_0 .net *"_s0", 0 0, L_0x1e00430; 1 drivers -v0x1c18a80_0 .net *"_s1", 0 0, L_0x1e00620; 1 drivers -S_0x1c19640 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c16210; +v0x10ab7e0_0 .net "A", 7 0, L_0x1354580; alias, 1 drivers +v0x10ab8e0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10ab9a0_0 .net *"_s0", 0 0, L_0x1292100; 1 drivers +v0x10aba60_0 .net *"_s12", 0 0, L_0x1292a70; 1 drivers +v0x10abb40_0 .net *"_s16", 0 0, L_0x1292dd0; 1 drivers +v0x10abc70_0 .net *"_s20", 0 0, L_0x12930e0; 1 drivers +v0x10abd50_0 .net *"_s24", 0 0, L_0x12934d0; 1 drivers +v0x10abe30_0 .net *"_s28", 0 0, L_0x1293460; 1 drivers +v0x10abf10_0 .net *"_s4", 0 0, L_0x1292410; 1 drivers +v0x10ac080_0 .net *"_s8", 0 0, L_0x1292760; 1 drivers +v0x10ac160_0 .net "out", 7 0, L_0x12937e0; alias, 1 drivers +L_0x12921c0 .part L_0x1354580, 0, 1; +L_0x1292320 .part v0x12010b0_0, 0, 1; +L_0x12924d0 .part L_0x1354580, 1, 1; +L_0x12926c0 .part v0x12010b0_0, 1, 1; +L_0x1292820 .part L_0x1354580, 2, 1; +L_0x1292980 .part v0x12010b0_0, 2, 1; +L_0x1292b30 .part L_0x1354580, 3, 1; +L_0x1292c90 .part v0x12010b0_0, 3, 1; +L_0x1292e90 .part L_0x1354580, 4, 1; +L_0x1292ff0 .part v0x12010b0_0, 4, 1; +L_0x1293150 .part L_0x1354580, 5, 1; +L_0x12933c0 .part v0x12010b0_0, 5, 1; +L_0x1293590 .part L_0x1354580, 6, 1; +L_0x12936f0 .part v0x12010b0_0, 6, 1; +LS_0x12937e0_0_0 .concat8 [ 1 1 1 1], L_0x1292100, L_0x1292410, L_0x1292760, L_0x1292a70; +LS_0x12937e0_0_4 .concat8 [ 1 1 1 1], L_0x1292dd0, L_0x12930e0, L_0x12934d0, L_0x1293460; +L_0x12937e0 .concat8 [ 4 4 0 0], LS_0x12937e0_0_0, LS_0x12937e0_0_4; +L_0x1293ba0 .part L_0x1354580, 7, 1; +L_0x1293d90 .part v0x12010b0_0, 7, 1; +S_0x10a9310 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10a9520 .param/l "i" 0 4 54, +C4<00>; +L_0x1292100/d .functor AND 1, L_0x12921c0, L_0x1292320, C4<1>, C4<1>; +L_0x1292100 .delay 1 (30000,30000,30000) L_0x1292100/d; +v0x10a9600_0 .net *"_s0", 0 0, L_0x12921c0; 1 drivers +v0x10a96e0_0 .net *"_s1", 0 0, L_0x1292320; 1 drivers +S_0x10a97c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10a99d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1292410/d .functor AND 1, L_0x12924d0, L_0x12926c0, C4<1>, C4<1>; +L_0x1292410 .delay 1 (30000,30000,30000) L_0x1292410/d; +v0x10a9a90_0 .net *"_s0", 0 0, L_0x12924d0; 1 drivers +v0x10a9b70_0 .net *"_s1", 0 0, L_0x12926c0; 1 drivers +S_0x10a9c50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10a9e60 .param/l "i" 0 4 54, +C4<010>; +L_0x1292760/d .functor AND 1, L_0x1292820, L_0x1292980, C4<1>, C4<1>; +L_0x1292760 .delay 1 (30000,30000,30000) L_0x1292760/d; +v0x10a9f00_0 .net *"_s0", 0 0, L_0x1292820; 1 drivers +v0x10a9fe0_0 .net *"_s1", 0 0, L_0x1292980; 1 drivers +S_0x10aa0c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10aa2d0 .param/l "i" 0 4 54, +C4<011>; +L_0x1292a70/d .functor AND 1, L_0x1292b30, L_0x1292c90, C4<1>, C4<1>; +L_0x1292a70 .delay 1 (30000,30000,30000) L_0x1292a70/d; +v0x10aa390_0 .net *"_s0", 0 0, L_0x1292b30; 1 drivers +v0x10aa470_0 .net *"_s1", 0 0, L_0x1292c90; 1 drivers +S_0x10aa550 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10aa7b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1292dd0/d .functor AND 1, L_0x1292e90, L_0x1292ff0, C4<1>, C4<1>; +L_0x1292dd0 .delay 1 (30000,30000,30000) L_0x1292dd0/d; +v0x10aa870_0 .net *"_s0", 0 0, L_0x1292e90; 1 drivers +v0x10aa950_0 .net *"_s1", 0 0, L_0x1292ff0; 1 drivers +S_0x10aaa30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10aac40 .param/l "i" 0 4 54, +C4<0101>; +L_0x12930e0/d .functor AND 1, L_0x1293150, L_0x12933c0, C4<1>, C4<1>; +L_0x12930e0 .delay 1 (30000,30000,30000) L_0x12930e0/d; +v0x10aad00_0 .net *"_s0", 0 0, L_0x1293150; 1 drivers +v0x10aade0_0 .net *"_s1", 0 0, L_0x12933c0; 1 drivers +S_0x10aaec0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10ab0d0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12934d0/d .functor AND 1, L_0x1293590, L_0x12936f0, C4<1>, C4<1>; +L_0x12934d0 .delay 1 (30000,30000,30000) L_0x12934d0/d; +v0x10ab190_0 .net *"_s0", 0 0, L_0x1293590; 1 drivers +v0x10ab270_0 .net *"_s1", 0 0, L_0x12936f0; 1 drivers +S_0x10ab350 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10a90b0; + .timescale -9 -12; +P_0x10ab560 .param/l "i" 0 4 54, +C4<0111>; +L_0x1293460/d .functor AND 1, L_0x1293ba0, L_0x1293d90, C4<1>, C4<1>; +L_0x1293460 .delay 1 (30000,30000,30000) L_0x1293460/d; +v0x10ab620_0 .net *"_s0", 0 0, L_0x1293ba0; 1 drivers +v0x10ab700_0 .net *"_s1", 0 0, L_0x1293d90; 1 drivers +S_0x10ac2c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10a8e90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e02070/d .functor OR 1, L_0x1e02130, L_0x1e022e0, C4<0>, C4<0>; -L_0x1e02070 .delay 1 (30000,30000,30000) L_0x1e02070/d; -v0x1c1b190_0 .net *"_s10", 0 0, L_0x1e02130; 1 drivers -v0x1c1b270_0 .net *"_s12", 0 0, L_0x1e022e0; 1 drivers -v0x1c1b350_0 .net "in", 7 0, L_0x1e00070; alias, 1 drivers -v0x1c1b420_0 .net "ors", 1 0, L_0x1e01e90; 1 drivers -v0x1c1b4e0_0 .net "out", 0 0, L_0x1e02070; alias, 1 drivers -L_0x1e01260 .part L_0x1e00070, 0, 4; -L_0x1e01e90 .concat8 [ 1 1 0 0], L_0x1e00f50, L_0x1e01b80; -L_0x1e01fd0 .part L_0x1e00070, 4, 4; -L_0x1e02130 .part L_0x1e01e90, 0, 1; -L_0x1e022e0 .part L_0x1e01e90, 1, 1; -S_0x1c19800 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c19640; +L_0x1295720/d .functor OR 1, L_0x12957e0, L_0x1295990, C4<0>, C4<0>; +L_0x1295720 .delay 1 (30000,30000,30000) L_0x1295720/d; +v0x10ade10_0 .net *"_s10", 0 0, L_0x12957e0; 1 drivers +v0x10adef0_0 .net *"_s12", 0 0, L_0x1295990; 1 drivers +v0x10adfd0_0 .net "in", 7 0, L_0x12937e0; alias, 1 drivers +v0x10ae0a0_0 .net "ors", 1 0, L_0x1295540; 1 drivers +v0x10ae160_0 .net "out", 0 0, L_0x1295720; alias, 1 drivers +L_0x1294910 .part L_0x12937e0, 0, 4; +L_0x1295540 .concat8 [ 1 1 0 0], L_0x1294600, L_0x1295230; +L_0x1295680 .part L_0x12937e0, 4, 4; +L_0x12957e0 .part L_0x1295540, 0, 1; +L_0x1295990 .part L_0x1295540, 1, 1; +S_0x10ac480 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10ac2c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e00710/d .functor OR 1, L_0x1e007d0, L_0x1e00930, C4<0>, C4<0>; -L_0x1e00710 .delay 1 (30000,30000,30000) L_0x1e00710/d; -L_0x1e00b60/d .functor OR 1, L_0x1e00c70, L_0x1e00dd0, C4<0>, C4<0>; -L_0x1e00b60 .delay 1 (30000,30000,30000) L_0x1e00b60/d; -L_0x1e00f50/d .functor OR 1, L_0x1e00fc0, L_0x1e01170, C4<0>, C4<0>; -L_0x1e00f50 .delay 1 (30000,30000,30000) L_0x1e00f50/d; -v0x1c19a50_0 .net *"_s0", 0 0, L_0x1e00710; 1 drivers -v0x1c19b50_0 .net *"_s10", 0 0, L_0x1e00c70; 1 drivers -v0x1c19c30_0 .net *"_s12", 0 0, L_0x1e00dd0; 1 drivers -v0x1c19cf0_0 .net *"_s14", 0 0, L_0x1e00fc0; 1 drivers -v0x1c19dd0_0 .net *"_s16", 0 0, L_0x1e01170; 1 drivers -v0x1c19f00_0 .net *"_s3", 0 0, L_0x1e007d0; 1 drivers -v0x1c19fe0_0 .net *"_s5", 0 0, L_0x1e00930; 1 drivers -v0x1c1a0c0_0 .net *"_s6", 0 0, L_0x1e00b60; 1 drivers -v0x1c1a1a0_0 .net "in", 3 0, L_0x1e01260; 1 drivers -v0x1c1a310_0 .net "ors", 1 0, L_0x1e00a70; 1 drivers -v0x1c1a3f0_0 .net "out", 0 0, L_0x1e00f50; 1 drivers -L_0x1e007d0 .part L_0x1e01260, 0, 1; -L_0x1e00930 .part L_0x1e01260, 1, 1; -L_0x1e00a70 .concat8 [ 1 1 0 0], L_0x1e00710, L_0x1e00b60; -L_0x1e00c70 .part L_0x1e01260, 2, 1; -L_0x1e00dd0 .part L_0x1e01260, 3, 1; -L_0x1e00fc0 .part L_0x1e00a70, 0, 1; -L_0x1e01170 .part L_0x1e00a70, 1, 1; -S_0x1c1a510 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c19640; +L_0x1293e80/d .functor OR 1, L_0x1293f40, L_0x1293fe0, C4<0>, C4<0>; +L_0x1293e80 .delay 1 (30000,30000,30000) L_0x1293e80/d; +L_0x1294210/d .functor OR 1, L_0x1294320, L_0x1294480, C4<0>, C4<0>; +L_0x1294210 .delay 1 (30000,30000,30000) L_0x1294210/d; +L_0x1294600/d .functor OR 1, L_0x1294670, L_0x1294820, C4<0>, C4<0>; +L_0x1294600 .delay 1 (30000,30000,30000) L_0x1294600/d; +v0x10ac6d0_0 .net *"_s0", 0 0, L_0x1293e80; 1 drivers +v0x10ac7d0_0 .net *"_s10", 0 0, L_0x1294320; 1 drivers +v0x10ac8b0_0 .net *"_s12", 0 0, L_0x1294480; 1 drivers +v0x10ac970_0 .net *"_s14", 0 0, L_0x1294670; 1 drivers +v0x10aca50_0 .net *"_s16", 0 0, L_0x1294820; 1 drivers +v0x10acb80_0 .net *"_s3", 0 0, L_0x1293f40; 1 drivers +v0x10acc60_0 .net *"_s5", 0 0, L_0x1293fe0; 1 drivers +v0x10acd40_0 .net *"_s6", 0 0, L_0x1294210; 1 drivers +v0x10ace20_0 .net "in", 3 0, L_0x1294910; 1 drivers +v0x10acf90_0 .net "ors", 1 0, L_0x1294120; 1 drivers +v0x10ad070_0 .net "out", 0 0, L_0x1294600; 1 drivers +L_0x1293f40 .part L_0x1294910, 0, 1; +L_0x1293fe0 .part L_0x1294910, 1, 1; +L_0x1294120 .concat8 [ 1 1 0 0], L_0x1293e80, L_0x1294210; +L_0x1294320 .part L_0x1294910, 2, 1; +L_0x1294480 .part L_0x1294910, 3, 1; +L_0x1294670 .part L_0x1294120, 0, 1; +L_0x1294820 .part L_0x1294120, 1, 1; +S_0x10ad190 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10ac2c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e01390/d .functor OR 1, L_0x1e01400, L_0x1e01560, C4<0>, C4<0>; -L_0x1e01390 .delay 1 (30000,30000,30000) L_0x1e01390/d; -L_0x1e01790/d .functor OR 1, L_0x1e018a0, L_0x1e01a00, C4<0>, C4<0>; -L_0x1e01790 .delay 1 (30000,30000,30000) L_0x1e01790/d; -L_0x1e01b80/d .functor OR 1, L_0x1e01bf0, L_0x1e01da0, C4<0>, C4<0>; -L_0x1e01b80 .delay 1 (30000,30000,30000) L_0x1e01b80/d; -v0x1c1a6d0_0 .net *"_s0", 0 0, L_0x1e01390; 1 drivers -v0x1c1a7d0_0 .net *"_s10", 0 0, L_0x1e018a0; 1 drivers -v0x1c1a8b0_0 .net *"_s12", 0 0, L_0x1e01a00; 1 drivers -v0x1c1a970_0 .net *"_s14", 0 0, L_0x1e01bf0; 1 drivers -v0x1c1aa50_0 .net *"_s16", 0 0, L_0x1e01da0; 1 drivers -v0x1c1ab80_0 .net *"_s3", 0 0, L_0x1e01400; 1 drivers -v0x1c1ac60_0 .net *"_s5", 0 0, L_0x1e01560; 1 drivers -v0x1c1ad40_0 .net *"_s6", 0 0, L_0x1e01790; 1 drivers -v0x1c1ae20_0 .net "in", 3 0, L_0x1e01fd0; 1 drivers -v0x1c1af90_0 .net "ors", 1 0, L_0x1e016a0; 1 drivers -v0x1c1b070_0 .net "out", 0 0, L_0x1e01b80; 1 drivers -L_0x1e01400 .part L_0x1e01fd0, 0, 1; -L_0x1e01560 .part L_0x1e01fd0, 1, 1; -L_0x1e016a0 .concat8 [ 1 1 0 0], L_0x1e01390, L_0x1e01790; -L_0x1e018a0 .part L_0x1e01fd0, 2, 1; -L_0x1e01a00 .part L_0x1e01fd0, 3, 1; -L_0x1e01bf0 .part L_0x1e016a0, 0, 1; -L_0x1e01da0 .part L_0x1e016a0, 1, 1; -S_0x1c1b980 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c14ab0; +L_0x1294a40/d .functor OR 1, L_0x1294ab0, L_0x1294c10, C4<0>, C4<0>; +L_0x1294a40 .delay 1 (30000,30000,30000) L_0x1294a40/d; +L_0x1294e40/d .functor OR 1, L_0x1294f50, L_0x12950b0, C4<0>, C4<0>; +L_0x1294e40 .delay 1 (30000,30000,30000) L_0x1294e40/d; +L_0x1295230/d .functor OR 1, L_0x12952a0, L_0x1295450, C4<0>, C4<0>; +L_0x1295230 .delay 1 (30000,30000,30000) L_0x1295230/d; +v0x10ad350_0 .net *"_s0", 0 0, L_0x1294a40; 1 drivers +v0x10ad450_0 .net *"_s10", 0 0, L_0x1294f50; 1 drivers +v0x10ad530_0 .net *"_s12", 0 0, L_0x12950b0; 1 drivers +v0x10ad5f0_0 .net *"_s14", 0 0, L_0x12952a0; 1 drivers +v0x10ad6d0_0 .net *"_s16", 0 0, L_0x1295450; 1 drivers +v0x10ad800_0 .net *"_s3", 0 0, L_0x1294ab0; 1 drivers +v0x10ad8e0_0 .net *"_s5", 0 0, L_0x1294c10; 1 drivers +v0x10ad9c0_0 .net *"_s6", 0 0, L_0x1294e40; 1 drivers +v0x10adaa0_0 .net "in", 3 0, L_0x1295680; 1 drivers +v0x10adc10_0 .net "ors", 1 0, L_0x1294d50; 1 drivers +v0x10adcf0_0 .net "out", 0 0, L_0x1295230; 1 drivers +L_0x1294ab0 .part L_0x1295680, 0, 1; +L_0x1294c10 .part L_0x1295680, 1, 1; +L_0x1294d50 .concat8 [ 1 1 0 0], L_0x1294a40, L_0x1294e40; +L_0x1294f50 .part L_0x1295680, 2, 1; +L_0x12950b0 .part L_0x1295680, 3, 1; +L_0x12952a0 .part L_0x1294d50, 0, 1; +L_0x1295450 .part L_0x1294d50, 1, 1; +S_0x10ae600 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10a7730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c20db0_0 .net "ands", 7 0, L_0x1dfc630; 1 drivers -v0x1c20ec0_0 .net "in", 7 0, L_0x1dfaa90; alias, 1 drivers -v0x1c20f80_0 .net "out", 0 0, L_0x1dfe630; alias, 1 drivers -v0x1c21050_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c1bbd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c1b980; +v0x10b3a30_0 .net "ands", 7 0, L_0x128fda0; 1 drivers +v0x10b3b40_0 .net "in", 7 0, L_0x128e2e0; alias, 1 drivers +v0x10b3c00_0 .net "out", 0 0, L_0x1291da0; alias, 1 drivers +v0x10b3cd0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10ae850 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10ae600; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c1e310_0 .net "A", 7 0, L_0x1dfaa90; alias, 1 drivers -v0x1c1e410_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c1e4d0_0 .net *"_s0", 0 0, L_0x1dfae20; 1 drivers -v0x1c1e590_0 .net *"_s12", 0 0, L_0x1dfb7e0; 1 drivers -v0x1c1e670_0 .net *"_s16", 0 0, L_0x1dfbb40; 1 drivers -v0x1c1e7a0_0 .net *"_s20", 0 0, L_0x1dfbf70; 1 drivers -v0x1c1e880_0 .net *"_s24", 0 0, L_0x1dfc2a0; 1 drivers -v0x1c1e960_0 .net *"_s28", 0 0, L_0x1dfc230; 1 drivers -v0x1c1ea40_0 .net *"_s4", 0 0, L_0x1dfb1c0; 1 drivers -v0x1c1ebb0_0 .net *"_s8", 0 0, L_0x1dfb4d0; 1 drivers -v0x1c1ec90_0 .net "out", 7 0, L_0x1dfc630; alias, 1 drivers -L_0x1dfaf30 .part L_0x1dfaa90, 0, 1; -L_0x1dfb120 .part v0x1d6daa0_0, 0, 1; -L_0x1dfb280 .part L_0x1dfaa90, 1, 1; -L_0x1dfb3e0 .part v0x1d6daa0_0, 1, 1; -L_0x1dfb590 .part L_0x1dfaa90, 2, 1; -L_0x1dfb6f0 .part v0x1d6daa0_0, 2, 1; -L_0x1dfb8a0 .part L_0x1dfaa90, 3, 1; -L_0x1dfba00 .part v0x1d6daa0_0, 3, 1; -L_0x1dfbc00 .part L_0x1dfaa90, 4, 1; -L_0x1dfbe70 .part v0x1d6daa0_0, 4, 1; -L_0x1dfbfe0 .part L_0x1dfaa90, 5, 1; -L_0x1dfc140 .part v0x1d6daa0_0, 5, 1; -L_0x1dfc360 .part L_0x1dfaa90, 6, 1; -L_0x1dfc4c0 .part v0x1d6daa0_0, 6, 1; -LS_0x1dfc630_0_0 .concat8 [ 1 1 1 1], L_0x1dfae20, L_0x1dfb1c0, L_0x1dfb4d0, L_0x1dfb7e0; -LS_0x1dfc630_0_4 .concat8 [ 1 1 1 1], L_0x1dfbb40, L_0x1dfbf70, L_0x1dfc2a0, L_0x1dfc230; -L_0x1dfc630 .concat8 [ 4 4 0 0], LS_0x1dfc630_0_0, LS_0x1dfc630_0_4; -L_0x1dfc9f0 .part L_0x1dfaa90, 7, 1; -L_0x1dfcbe0 .part v0x1d6daa0_0, 7, 1; -S_0x1c1be10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1c020 .param/l "i" 0 4 54, +C4<00>; -L_0x1dfae20/d .functor AND 1, L_0x1dfaf30, L_0x1dfb120, C4<1>, C4<1>; -L_0x1dfae20 .delay 1 (30000,30000,30000) L_0x1dfae20/d; -v0x1c1c100_0 .net *"_s0", 0 0, L_0x1dfaf30; 1 drivers -v0x1c1c1e0_0 .net *"_s1", 0 0, L_0x1dfb120; 1 drivers -S_0x1c1c2c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1c4d0 .param/l "i" 0 4 54, +C4<01>; -L_0x1dfb1c0/d .functor AND 1, L_0x1dfb280, L_0x1dfb3e0, C4<1>, C4<1>; -L_0x1dfb1c0 .delay 1 (30000,30000,30000) L_0x1dfb1c0/d; -v0x1c1c590_0 .net *"_s0", 0 0, L_0x1dfb280; 1 drivers -v0x1c1c670_0 .net *"_s1", 0 0, L_0x1dfb3e0; 1 drivers -S_0x1c1c750 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1c990 .param/l "i" 0 4 54, +C4<010>; -L_0x1dfb4d0/d .functor AND 1, L_0x1dfb590, L_0x1dfb6f0, C4<1>, C4<1>; -L_0x1dfb4d0 .delay 1 (30000,30000,30000) L_0x1dfb4d0/d; -v0x1c1ca30_0 .net *"_s0", 0 0, L_0x1dfb590; 1 drivers -v0x1c1cb10_0 .net *"_s1", 0 0, L_0x1dfb6f0; 1 drivers -S_0x1c1cbf0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1ce00 .param/l "i" 0 4 54, +C4<011>; -L_0x1dfb7e0/d .functor AND 1, L_0x1dfb8a0, L_0x1dfba00, C4<1>, C4<1>; -L_0x1dfb7e0 .delay 1 (30000,30000,30000) L_0x1dfb7e0/d; -v0x1c1cec0_0 .net *"_s0", 0 0, L_0x1dfb8a0; 1 drivers -v0x1c1cfa0_0 .net *"_s1", 0 0, L_0x1dfba00; 1 drivers -S_0x1c1d080 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1d2e0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1dfbb40/d .functor AND 1, L_0x1dfbc00, L_0x1dfbe70, C4<1>, C4<1>; -L_0x1dfbb40 .delay 1 (30000,30000,30000) L_0x1dfbb40/d; -v0x1c1d3a0_0 .net *"_s0", 0 0, L_0x1dfbc00; 1 drivers -v0x1c1d480_0 .net *"_s1", 0 0, L_0x1dfbe70; 1 drivers -S_0x1c1d560 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1d770 .param/l "i" 0 4 54, +C4<0101>; -L_0x1dfbf70/d .functor AND 1, L_0x1dfbfe0, L_0x1dfc140, C4<1>, C4<1>; -L_0x1dfbf70 .delay 1 (30000,30000,30000) L_0x1dfbf70/d; -v0x1c1d830_0 .net *"_s0", 0 0, L_0x1dfbfe0; 1 drivers -v0x1c1d910_0 .net *"_s1", 0 0, L_0x1dfc140; 1 drivers -S_0x1c1d9f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1dc00 .param/l "i" 0 4 54, +C4<0110>; -L_0x1dfc2a0/d .functor AND 1, L_0x1dfc360, L_0x1dfc4c0, C4<1>, C4<1>; -L_0x1dfc2a0 .delay 1 (30000,30000,30000) L_0x1dfc2a0/d; -v0x1c1dcc0_0 .net *"_s0", 0 0, L_0x1dfc360; 1 drivers -v0x1c1dda0_0 .net *"_s1", 0 0, L_0x1dfc4c0; 1 drivers -S_0x1c1de80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c1bbd0; - .timescale -9 -12; -P_0x1c1e090 .param/l "i" 0 4 54, +C4<0111>; -L_0x1dfc230/d .functor AND 1, L_0x1dfc9f0, L_0x1dfcbe0, C4<1>, C4<1>; -L_0x1dfc230 .delay 1 (30000,30000,30000) L_0x1dfc230/d; -v0x1c1e150_0 .net *"_s0", 0 0, L_0x1dfc9f0; 1 drivers -v0x1c1e230_0 .net *"_s1", 0 0, L_0x1dfcbe0; 1 drivers -S_0x1c1edf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c1b980; +v0x10b0f90_0 .net "A", 7 0, L_0x128e2e0; alias, 1 drivers +v0x10b1090_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10b1150_0 .net *"_s0", 0 0, L_0x128e670; 1 drivers +v0x10b1210_0 .net *"_s12", 0 0, L_0x128f030; 1 drivers +v0x10b12f0_0 .net *"_s16", 0 0, L_0x128f390; 1 drivers +v0x10b1420_0 .net *"_s20", 0 0, L_0x128f760; 1 drivers +v0x10b1500_0 .net *"_s24", 0 0, L_0x128fa90; 1 drivers +v0x10b15e0_0 .net *"_s28", 0 0, L_0x128fa20; 1 drivers +v0x10b16c0_0 .net *"_s4", 0 0, L_0x128ea10; 1 drivers +v0x10b1830_0 .net *"_s8", 0 0, L_0x128ed20; 1 drivers +v0x10b1910_0 .net "out", 7 0, L_0x128fda0; alias, 1 drivers +L_0x128e780 .part L_0x128e2e0, 0, 1; +L_0x128e970 .part v0x12010b0_0, 0, 1; +L_0x128ead0 .part L_0x128e2e0, 1, 1; +L_0x128ec30 .part v0x12010b0_0, 1, 1; +L_0x128ede0 .part L_0x128e2e0, 2, 1; +L_0x128ef40 .part v0x12010b0_0, 2, 1; +L_0x128f0f0 .part L_0x128e2e0, 3, 1; +L_0x128f250 .part v0x12010b0_0, 3, 1; +L_0x128f450 .part L_0x128e2e0, 4, 1; +L_0x128f6c0 .part v0x12010b0_0, 4, 1; +L_0x128f7d0 .part L_0x128e2e0, 5, 1; +L_0x128f930 .part v0x12010b0_0, 5, 1; +L_0x128fb50 .part L_0x128e2e0, 6, 1; +L_0x128fcb0 .part v0x12010b0_0, 6, 1; +LS_0x128fda0_0_0 .concat8 [ 1 1 1 1], L_0x128e670, L_0x128ea10, L_0x128ed20, L_0x128f030; +LS_0x128fda0_0_4 .concat8 [ 1 1 1 1], L_0x128f390, L_0x128f760, L_0x128fa90, L_0x128fa20; +L_0x128fda0 .concat8 [ 4 4 0 0], LS_0x128fda0_0_0, LS_0x128fda0_0_4; +L_0x1290160 .part L_0x128e2e0, 7, 1; +L_0x1290350 .part v0x12010b0_0, 7, 1; +S_0x10aea90 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10aeca0 .param/l "i" 0 4 54, +C4<00>; +L_0x128e670/d .functor AND 1, L_0x128e780, L_0x128e970, C4<1>, C4<1>; +L_0x128e670 .delay 1 (30000,30000,30000) L_0x128e670/d; +v0x10aed80_0 .net *"_s0", 0 0, L_0x128e780; 1 drivers +v0x10aee60_0 .net *"_s1", 0 0, L_0x128e970; 1 drivers +S_0x10aef40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10af150 .param/l "i" 0 4 54, +C4<01>; +L_0x128ea10/d .functor AND 1, L_0x128ead0, L_0x128ec30, C4<1>, C4<1>; +L_0x128ea10 .delay 1 (30000,30000,30000) L_0x128ea10/d; +v0x10af210_0 .net *"_s0", 0 0, L_0x128ead0; 1 drivers +v0x10af2f0_0 .net *"_s1", 0 0, L_0x128ec30; 1 drivers +S_0x10af3d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10af610 .param/l "i" 0 4 54, +C4<010>; +L_0x128ed20/d .functor AND 1, L_0x128ede0, L_0x128ef40, C4<1>, C4<1>; +L_0x128ed20 .delay 1 (30000,30000,30000) L_0x128ed20/d; +v0x10af6b0_0 .net *"_s0", 0 0, L_0x128ede0; 1 drivers +v0x10af790_0 .net *"_s1", 0 0, L_0x128ef40; 1 drivers +S_0x10af870 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10afa80 .param/l "i" 0 4 54, +C4<011>; +L_0x128f030/d .functor AND 1, L_0x128f0f0, L_0x128f250, C4<1>, C4<1>; +L_0x128f030 .delay 1 (30000,30000,30000) L_0x128f030/d; +v0x10afb40_0 .net *"_s0", 0 0, L_0x128f0f0; 1 drivers +v0x10afc20_0 .net *"_s1", 0 0, L_0x128f250; 1 drivers +S_0x10afd00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10aff60 .param/l "i" 0 4 54, +C4<0100>; +L_0x128f390/d .functor AND 1, L_0x128f450, L_0x128f6c0, C4<1>, C4<1>; +L_0x128f390 .delay 1 (30000,30000,30000) L_0x128f390/d; +v0x10b0020_0 .net *"_s0", 0 0, L_0x128f450; 1 drivers +v0x10b0100_0 .net *"_s1", 0 0, L_0x128f6c0; 1 drivers +S_0x10b01e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10b03f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x128f760/d .functor AND 1, L_0x128f7d0, L_0x128f930, C4<1>, C4<1>; +L_0x128f760 .delay 1 (30000,30000,30000) L_0x128f760/d; +v0x10b04b0_0 .net *"_s0", 0 0, L_0x128f7d0; 1 drivers +v0x10b0590_0 .net *"_s1", 0 0, L_0x128f930; 1 drivers +S_0x10b0670 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10b0880 .param/l "i" 0 4 54, +C4<0110>; +L_0x128fa90/d .functor AND 1, L_0x128fb50, L_0x128fcb0, C4<1>, C4<1>; +L_0x128fa90 .delay 1 (30000,30000,30000) L_0x128fa90/d; +v0x10b0940_0 .net *"_s0", 0 0, L_0x128fb50; 1 drivers +v0x10b0a20_0 .net *"_s1", 0 0, L_0x128fcb0; 1 drivers +S_0x10b0b00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10ae850; + .timescale -9 -12; +P_0x10b0d10 .param/l "i" 0 4 54, +C4<0111>; +L_0x128fa20/d .functor AND 1, L_0x1290160, L_0x1290350, C4<1>, C4<1>; +L_0x128fa20 .delay 1 (30000,30000,30000) L_0x128fa20/d; +v0x10b0dd0_0 .net *"_s0", 0 0, L_0x1290160; 1 drivers +v0x10b0eb0_0 .net *"_s1", 0 0, L_0x1290350; 1 drivers +S_0x10b1a70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10ae600; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1dfe630/d .functor OR 1, L_0x1dfe6f0, L_0x1dfe8a0, C4<0>, C4<0>; -L_0x1dfe630 .delay 1 (30000,30000,30000) L_0x1dfe630/d; -v0x1c20940_0 .net *"_s10", 0 0, L_0x1dfe6f0; 1 drivers -v0x1c20a20_0 .net *"_s12", 0 0, L_0x1dfe8a0; 1 drivers -v0x1c20b00_0 .net "in", 7 0, L_0x1dfc630; alias, 1 drivers -v0x1c20bd0_0 .net "ors", 1 0, L_0x1dfe450; 1 drivers -v0x1c20c90_0 .net "out", 0 0, L_0x1dfe630; alias, 1 drivers -L_0x1dfd820 .part L_0x1dfc630, 0, 4; -L_0x1dfe450 .concat8 [ 1 1 0 0], L_0x1dfd510, L_0x1dfe140; -L_0x1dfe590 .part L_0x1dfc630, 4, 4; -L_0x1dfe6f0 .part L_0x1dfe450, 0, 1; -L_0x1dfe8a0 .part L_0x1dfe450, 1, 1; -S_0x1c1efb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c1edf0; +L_0x1291da0/d .functor OR 1, L_0x1291e60, L_0x1292010, C4<0>, C4<0>; +L_0x1291da0 .delay 1 (30000,30000,30000) L_0x1291da0/d; +v0x10b35c0_0 .net *"_s10", 0 0, L_0x1291e60; 1 drivers +v0x10b36a0_0 .net *"_s12", 0 0, L_0x1292010; 1 drivers +v0x10b3780_0 .net "in", 7 0, L_0x128fda0; alias, 1 drivers +v0x10b3850_0 .net "ors", 1 0, L_0x1291bc0; 1 drivers +v0x10b3910_0 .net "out", 0 0, L_0x1291da0; alias, 1 drivers +L_0x1290f90 .part L_0x128fda0, 0, 4; +L_0x1291bc0 .concat8 [ 1 1 0 0], L_0x1290c80, L_0x12918b0; +L_0x1291d00 .part L_0x128fda0, 4, 4; +L_0x1291e60 .part L_0x1291bc0, 0, 1; +L_0x1292010 .part L_0x1291bc0, 1, 1; +S_0x10b1c30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10b1a70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dfccd0/d .functor OR 1, L_0x1dfcd90, L_0x1dfcef0, C4<0>, C4<0>; -L_0x1dfccd0 .delay 1 (30000,30000,30000) L_0x1dfccd0/d; -L_0x1dfd120/d .functor OR 1, L_0x1dfd230, L_0x1dfd390, C4<0>, C4<0>; -L_0x1dfd120 .delay 1 (30000,30000,30000) L_0x1dfd120/d; -L_0x1dfd510/d .functor OR 1, L_0x1dfd580, L_0x1dfd730, C4<0>, C4<0>; -L_0x1dfd510 .delay 1 (30000,30000,30000) L_0x1dfd510/d; -v0x1c1f200_0 .net *"_s0", 0 0, L_0x1dfccd0; 1 drivers -v0x1c1f300_0 .net *"_s10", 0 0, L_0x1dfd230; 1 drivers -v0x1c1f3e0_0 .net *"_s12", 0 0, L_0x1dfd390; 1 drivers -v0x1c1f4a0_0 .net *"_s14", 0 0, L_0x1dfd580; 1 drivers -v0x1c1f580_0 .net *"_s16", 0 0, L_0x1dfd730; 1 drivers -v0x1c1f6b0_0 .net *"_s3", 0 0, L_0x1dfcd90; 1 drivers -v0x1c1f790_0 .net *"_s5", 0 0, L_0x1dfcef0; 1 drivers -v0x1c1f870_0 .net *"_s6", 0 0, L_0x1dfd120; 1 drivers -v0x1c1f950_0 .net "in", 3 0, L_0x1dfd820; 1 drivers -v0x1c1fac0_0 .net "ors", 1 0, L_0x1dfd030; 1 drivers -v0x1c1fba0_0 .net "out", 0 0, L_0x1dfd510; 1 drivers -L_0x1dfcd90 .part L_0x1dfd820, 0, 1; -L_0x1dfcef0 .part L_0x1dfd820, 1, 1; -L_0x1dfd030 .concat8 [ 1 1 0 0], L_0x1dfccd0, L_0x1dfd120; -L_0x1dfd230 .part L_0x1dfd820, 2, 1; -L_0x1dfd390 .part L_0x1dfd820, 3, 1; -L_0x1dfd580 .part L_0x1dfd030, 0, 1; -L_0x1dfd730 .part L_0x1dfd030, 1, 1; -S_0x1c1fcc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c1edf0; +L_0x1290440/d .functor OR 1, L_0x1290500, L_0x1290660, C4<0>, C4<0>; +L_0x1290440 .delay 1 (30000,30000,30000) L_0x1290440/d; +L_0x1290890/d .functor OR 1, L_0x12909a0, L_0x1290b00, C4<0>, C4<0>; +L_0x1290890 .delay 1 (30000,30000,30000) L_0x1290890/d; +L_0x1290c80/d .functor OR 1, L_0x1290cf0, L_0x1290ea0, C4<0>, C4<0>; +L_0x1290c80 .delay 1 (30000,30000,30000) L_0x1290c80/d; +v0x10b1e80_0 .net *"_s0", 0 0, L_0x1290440; 1 drivers +v0x10b1f80_0 .net *"_s10", 0 0, L_0x12909a0; 1 drivers +v0x10b2060_0 .net *"_s12", 0 0, L_0x1290b00; 1 drivers +v0x10b2120_0 .net *"_s14", 0 0, L_0x1290cf0; 1 drivers +v0x10b2200_0 .net *"_s16", 0 0, L_0x1290ea0; 1 drivers +v0x10b2330_0 .net *"_s3", 0 0, L_0x1290500; 1 drivers +v0x10b2410_0 .net *"_s5", 0 0, L_0x1290660; 1 drivers +v0x10b24f0_0 .net *"_s6", 0 0, L_0x1290890; 1 drivers +v0x10b25d0_0 .net "in", 3 0, L_0x1290f90; 1 drivers +v0x10b2740_0 .net "ors", 1 0, L_0x12907a0; 1 drivers +v0x10b2820_0 .net "out", 0 0, L_0x1290c80; 1 drivers +L_0x1290500 .part L_0x1290f90, 0, 1; +L_0x1290660 .part L_0x1290f90, 1, 1; +L_0x12907a0 .concat8 [ 1 1 0 0], L_0x1290440, L_0x1290890; +L_0x12909a0 .part L_0x1290f90, 2, 1; +L_0x1290b00 .part L_0x1290f90, 3, 1; +L_0x1290cf0 .part L_0x12907a0, 0, 1; +L_0x1290ea0 .part L_0x12907a0, 1, 1; +S_0x10b2940 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10b1a70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1dfd950/d .functor OR 1, L_0x1dfd9c0, L_0x1dfdb20, C4<0>, C4<0>; -L_0x1dfd950 .delay 1 (30000,30000,30000) L_0x1dfd950/d; -L_0x1dfdd50/d .functor OR 1, L_0x1dfde60, L_0x1dfdfc0, C4<0>, C4<0>; -L_0x1dfdd50 .delay 1 (30000,30000,30000) L_0x1dfdd50/d; -L_0x1dfe140/d .functor OR 1, L_0x1dfe1b0, L_0x1dfe360, C4<0>, C4<0>; -L_0x1dfe140 .delay 1 (30000,30000,30000) L_0x1dfe140/d; -v0x1c1fe80_0 .net *"_s0", 0 0, L_0x1dfd950; 1 drivers -v0x1c1ff80_0 .net *"_s10", 0 0, L_0x1dfde60; 1 drivers -v0x1c20060_0 .net *"_s12", 0 0, L_0x1dfdfc0; 1 drivers -v0x1c20120_0 .net *"_s14", 0 0, L_0x1dfe1b0; 1 drivers -v0x1c20200_0 .net *"_s16", 0 0, L_0x1dfe360; 1 drivers -v0x1c20330_0 .net *"_s3", 0 0, L_0x1dfd9c0; 1 drivers -v0x1c20410_0 .net *"_s5", 0 0, L_0x1dfdb20; 1 drivers -v0x1c204f0_0 .net *"_s6", 0 0, L_0x1dfdd50; 1 drivers -v0x1c205d0_0 .net "in", 3 0, L_0x1dfe590; 1 drivers -v0x1c20740_0 .net "ors", 1 0, L_0x1dfdc60; 1 drivers -v0x1c20820_0 .net "out", 0 0, L_0x1dfe140; 1 drivers -L_0x1dfd9c0 .part L_0x1dfe590, 0, 1; -L_0x1dfdb20 .part L_0x1dfe590, 1, 1; -L_0x1dfdc60 .concat8 [ 1 1 0 0], L_0x1dfd950, L_0x1dfdd50; -L_0x1dfde60 .part L_0x1dfe590, 2, 1; -L_0x1dfdfc0 .part L_0x1dfe590, 3, 1; -L_0x1dfe1b0 .part L_0x1dfdc60, 0, 1; -L_0x1dfe360 .part L_0x1dfdc60, 1, 1; -S_0x1c21130 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c14ab0; +L_0x12910c0/d .functor OR 1, L_0x1291130, L_0x1291290, C4<0>, C4<0>; +L_0x12910c0 .delay 1 (30000,30000,30000) L_0x12910c0/d; +L_0x12914c0/d .functor OR 1, L_0x12915d0, L_0x1291730, C4<0>, C4<0>; +L_0x12914c0 .delay 1 (30000,30000,30000) L_0x12914c0/d; +L_0x12918b0/d .functor OR 1, L_0x1291920, L_0x1291ad0, C4<0>, C4<0>; +L_0x12918b0 .delay 1 (30000,30000,30000) L_0x12918b0/d; +v0x10b2b00_0 .net *"_s0", 0 0, L_0x12910c0; 1 drivers +v0x10b2c00_0 .net *"_s10", 0 0, L_0x12915d0; 1 drivers +v0x10b2ce0_0 .net *"_s12", 0 0, L_0x1291730; 1 drivers +v0x10b2da0_0 .net *"_s14", 0 0, L_0x1291920; 1 drivers +v0x10b2e80_0 .net *"_s16", 0 0, L_0x1291ad0; 1 drivers +v0x10b2fb0_0 .net *"_s3", 0 0, L_0x1291130; 1 drivers +v0x10b3090_0 .net *"_s5", 0 0, L_0x1291290; 1 drivers +v0x10b3170_0 .net *"_s6", 0 0, L_0x12914c0; 1 drivers +v0x10b3250_0 .net "in", 3 0, L_0x1291d00; 1 drivers +v0x10b33c0_0 .net "ors", 1 0, L_0x12913d0; 1 drivers +v0x10b34a0_0 .net "out", 0 0, L_0x12918b0; 1 drivers +L_0x1291130 .part L_0x1291d00, 0, 1; +L_0x1291290 .part L_0x1291d00, 1, 1; +L_0x12913d0 .concat8 [ 1 1 0 0], L_0x12910c0, L_0x12914c0; +L_0x12915d0 .part L_0x1291d00, 2, 1; +L_0x1291730 .part L_0x1291d00, 3, 1; +L_0x1291920 .part L_0x12913d0, 0, 1; +L_0x1291ad0 .part L_0x12913d0, 1, 1; +S_0x10b3db0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10a7730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -8092,80 +8102,80 @@ S_0x1c21130 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c14ab0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1de8d90/d .functor XNOR 1, L_0x1e024d0, L_0x1db4230, C4<0>, C4<0>; -L_0x1de8d90 .delay 1 (20000,20000,20000) L_0x1de8d90/d; -L_0x1dfa020/d .functor AND 1, L_0x1e024d0, L_0x1df8e00, C4<1>, C4<1>; -L_0x1dfa020 .delay 1 (30000,30000,30000) L_0x1dfa020/d; -L_0x1dfa0e0/d .functor AND 1, L_0x1de8d90, L_0x1db43e0, C4<1>, C4<1>; -L_0x1dfa0e0 .delay 1 (30000,30000,30000) L_0x1dfa0e0/d; -L_0x1dfa240/d .functor OR 1, L_0x1dfa0e0, L_0x1dfa020, C4<0>, C4<0>; -L_0x1dfa240 .delay 1 (30000,30000,30000) L_0x1dfa240/d; -v0x1c213e0_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers -v0x1c214d0_0 .net "a_", 0 0, L_0x1df8ca0; alias, 1 drivers -v0x1c21590_0 .net "b", 0 0, L_0x1db4230; alias, 1 drivers -v0x1c21680_0 .net "b_", 0 0, L_0x1df8e00; alias, 1 drivers -v0x1c21720_0 .net "carryin", 0 0, L_0x1db43e0; alias, 1 drivers -v0x1c21860_0 .net "eq", 0 0, L_0x1de8d90; 1 drivers -v0x1c21920_0 .net "lt", 0 0, L_0x1dfa020; 1 drivers -v0x1c219e0_0 .net "out", 0 0, L_0x1dfa240; 1 drivers -v0x1c21aa0_0 .net "w0", 0 0, L_0x1dfa0e0; 1 drivers -S_0x1c21cf0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c14ab0; +L_0x128d650/d .functor XNOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; +L_0x128d650 .delay 1 (20000,20000,20000) L_0x128d650/d; +L_0x128d8c0/d .functor AND 1, L_0x1295b80, L_0x128c540, C4<1>, C4<1>; +L_0x128d8c0 .delay 1 (30000,30000,30000) L_0x128d8c0/d; +L_0x128d930/d .functor AND 1, L_0x128d650, L_0x1247b40, C4<1>, C4<1>; +L_0x128d930 .delay 1 (30000,30000,30000) L_0x128d930/d; +L_0x128da90/d .functor OR 1, L_0x128d930, L_0x128d8c0, C4<0>, C4<0>; +L_0x128da90 .delay 1 (30000,30000,30000) L_0x128da90/d; +v0x10b4060_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers +v0x10b4150_0 .net "a_", 0 0, L_0x128c3e0; alias, 1 drivers +v0x10b4210_0 .net "b", 0 0, L_0x1247990; alias, 1 drivers +v0x10b4300_0 .net "b_", 0 0, L_0x128c540; alias, 1 drivers +v0x10b43a0_0 .net "carryin", 0 0, L_0x1247b40; alias, 1 drivers +v0x10b44e0_0 .net "eq", 0 0, L_0x128d650; 1 drivers +v0x10b45a0_0 .net "lt", 0 0, L_0x128d8c0; 1 drivers +v0x10b4660_0 .net "out", 0 0, L_0x128da90; 1 drivers +v0x10b4720_0 .net "w0", 0 0, L_0x128d930; 1 drivers +S_0x10b4970 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10a7730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1df9cf0/d .functor OR 1, L_0x1df97f0, L_0x1c22f50, C4<0>, C4<0>; -L_0x1df9cf0 .delay 1 (30000,30000,30000) L_0x1df9cf0/d; -v0x1c22ae0_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers -v0x1c22c30_0 .net "b", 0 0, L_0x1df8e00; alias, 1 drivers -v0x1c22cf0_0 .net "c1", 0 0, L_0x1df97f0; 1 drivers -v0x1c22d90_0 .net "c2", 0 0, L_0x1c22f50; 1 drivers -v0x1c22e60_0 .net "carryin", 0 0, L_0x1db43e0; alias, 1 drivers -v0x1c22fe0_0 .net "carryout", 0 0, L_0x1df9cf0; 1 drivers -v0x1c23080_0 .net "s1", 0 0, L_0x1df9730; 1 drivers -v0x1c23120_0 .net "sum", 0 0, L_0x1df9950; 1 drivers -S_0x1c21f40 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c21cf0; +L_0x128d430/d .functor OR 1, L_0x128cf30, L_0x10b5bd0, C4<0>, C4<0>; +L_0x128d430 .delay 1 (30000,30000,30000) L_0x128d430/d; +v0x10b5760_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers +v0x10b58b0_0 .net "b", 0 0, L_0x128c540; alias, 1 drivers +v0x10b5970_0 .net "c1", 0 0, L_0x128cf30; 1 drivers +v0x10b5a10_0 .net "c2", 0 0, L_0x10b5bd0; 1 drivers +v0x10b5ae0_0 .net "carryin", 0 0, L_0x1247b40; alias, 1 drivers +v0x10b5c60_0 .net "carryout", 0 0, L_0x128d430; 1 drivers +v0x10b5d00_0 .net "s1", 0 0, L_0x128ce70; 1 drivers +v0x10b5da0_0 .net "sum", 0 0, L_0x128d090; 1 drivers +S_0x10b4bc0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10b4970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1df9730/d .functor XOR 1, L_0x1e024d0, L_0x1df8e00, C4<0>, C4<0>; -L_0x1df9730 .delay 1 (30000,30000,30000) L_0x1df9730/d; -L_0x1df97f0/d .functor AND 1, L_0x1e024d0, L_0x1df8e00, C4<1>, C4<1>; -L_0x1df97f0 .delay 1 (30000,30000,30000) L_0x1df97f0/d; -v0x1c221a0_0 .net "a", 0 0, L_0x1e024d0; alias, 1 drivers -v0x1c22260_0 .net "b", 0 0, L_0x1df8e00; alias, 1 drivers -v0x1c22320_0 .net "carryout", 0 0, L_0x1df97f0; alias, 1 drivers -v0x1c223c0_0 .net "sum", 0 0, L_0x1df9730; alias, 1 drivers -S_0x1c224f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c21cf0; +L_0x128ce70/d .functor XOR 1, L_0x1295b80, L_0x128c540, C4<0>, C4<0>; +L_0x128ce70 .delay 1 (30000,30000,30000) L_0x128ce70/d; +L_0x128cf30/d .functor AND 1, L_0x1295b80, L_0x128c540, C4<1>, C4<1>; +L_0x128cf30 .delay 1 (30000,30000,30000) L_0x128cf30/d; +v0x10b4e20_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers +v0x10b4ee0_0 .net "b", 0 0, L_0x128c540; alias, 1 drivers +v0x10b4fa0_0 .net "carryout", 0 0, L_0x128cf30; alias, 1 drivers +v0x10b5040_0 .net "sum", 0 0, L_0x128ce70; alias, 1 drivers +S_0x10b5170 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10b4970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1df9950/d .functor XOR 1, L_0x1df9730, L_0x1db43e0, C4<0>, C4<0>; -L_0x1df9950 .delay 1 (30000,30000,30000) L_0x1df9950/d; -L_0x1c22f50/d .functor AND 1, L_0x1df9730, L_0x1db43e0, C4<1>, C4<1>; -L_0x1c22f50 .delay 1 (30000,30000,30000) L_0x1c22f50/d; -v0x1c22750_0 .net "a", 0 0, L_0x1df9730; alias, 1 drivers -v0x1c22820_0 .net "b", 0 0, L_0x1db43e0; alias, 1 drivers -v0x1c228c0_0 .net "carryout", 0 0, L_0x1c22f50; alias, 1 drivers -v0x1c22990_0 .net "sum", 0 0, L_0x1df9950; alias, 1 drivers -S_0x1c24540 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c147e0; - .timescale -9 -12; -L_0x7f72592dafd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db020 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e02570/d .functor OR 1, L_0x7f72592dafd8, L_0x7f72592db020, C4<0>, C4<0>; -L_0x1e02570 .delay 1 (30000,30000,30000) L_0x1e02570/d; -v0x1c24730_0 .net/2u *"_s0", 0 0, L_0x7f72592dafd8; 1 drivers -v0x1c24810_0 .net/2u *"_s2", 0 0, L_0x7f72592db020; 1 drivers -S_0x1c248f0 .scope generate, "alu_slices[15]" "alu_slices[15]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c24b00 .param/l "i" 0 3 37, +C4<01111>; -S_0x1c24bc0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c248f0; +L_0x128d090/d .functor XOR 1, L_0x128ce70, L_0x1247b40, C4<0>, C4<0>; +L_0x128d090 .delay 1 (30000,30000,30000) L_0x128d090/d; +L_0x10b5bd0/d .functor AND 1, L_0x128ce70, L_0x1247b40, C4<1>, C4<1>; +L_0x10b5bd0 .delay 1 (30000,30000,30000) L_0x10b5bd0/d; +v0x10b53d0_0 .net "a", 0 0, L_0x128ce70; alias, 1 drivers +v0x10b54a0_0 .net "b", 0 0, L_0x1247b40; alias, 1 drivers +v0x10b5540_0 .net "carryout", 0 0, L_0x10b5bd0; alias, 1 drivers +v0x10b5610_0 .net "sum", 0 0, L_0x128d090; alias, 1 drivers +S_0x10b71c0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10a7460; + .timescale -9 -12; +L_0x2b0ab3d05fd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06020 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1295c20/d .functor OR 1, L_0x2b0ab3d05fd8, L_0x2b0ab3d06020, C4<0>, C4<0>; +L_0x1295c20 .delay 1 (30000,30000,30000) L_0x1295c20/d; +v0x10b73b0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05fd8; 1 drivers +v0x10b7490_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06020; 1 drivers +S_0x10b7570 .scope generate, "alu_slices[15]" "alu_slices[15]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x10b7780 .param/l "i" 0 3 41, +C4<01111>; +S_0x10b7840 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10b7570; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -8174,445 +8184,445 @@ S_0x1c24bc0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c248f0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1df8aa0/d .functor NOT 1, L_0x1e0c2e0, C4<0>, C4<0>, C4<0>; -L_0x1df8aa0 .delay 1 (10000,10000,10000) L_0x1df8aa0/d; -L_0x1e02c10/d .functor NOT 1, L_0x1e02a50, C4<0>, C4<0>, C4<0>; -L_0x1e02c10 .delay 1 (10000,10000,10000) L_0x1e02c10/d; -L_0x1e03b50/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; -L_0x1e03b50 .delay 1 (30000,30000,30000) L_0x1e03b50/d; -L_0x7f72592db068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db0b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e04200/d .functor OR 1, L_0x7f72592db068, L_0x7f72592db0b0, C4<0>, C4<0>; -L_0x1e04200 .delay 1 (30000,30000,30000) L_0x1e04200/d; -L_0x1e04400/d .functor AND 1, L_0x1e0c2e0, L_0x1e02a50, C4<1>, C4<1>; -L_0x1e04400 .delay 1 (30000,30000,30000) L_0x1e04400/d; -L_0x1e044c0/d .functor NAND 1, L_0x1e0c2e0, L_0x1e02a50, C4<1>, C4<1>; -L_0x1e044c0 .delay 1 (20000,20000,20000) L_0x1e044c0/d; -L_0x1e04620/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; -L_0x1e04620 .delay 1 (20000,20000,20000) L_0x1e04620/d; -L_0x1e04ad0/d .functor OR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; -L_0x1e04ad0 .delay 1 (30000,30000,30000) L_0x1e04ad0/d; -L_0x1e0c1e0/d .functor NOT 1, L_0x1e08440, C4<0>, C4<0>, C4<0>; -L_0x1e0c1e0 .delay 1 (10000,10000,10000) L_0x1e0c1e0/d; -v0x1c332f0_0 .net "A", 0 0, L_0x1e0c2e0; 1 drivers -v0x1c333b0_0 .net "A_", 0 0, L_0x1df8aa0; 1 drivers -v0x1c33470_0 .net "B", 0 0, L_0x1e02a50; 1 drivers -v0x1c33540_0 .net "B_", 0 0, L_0x1e02c10; 1 drivers -v0x1c335e0_0 .net *"_s12", 0 0, L_0x1e04200; 1 drivers -v0x1c336d0_0 .net/2s *"_s14", 0 0, L_0x7f72592db068; 1 drivers -v0x1c33790_0 .net/2s *"_s16", 0 0, L_0x7f72592db0b0; 1 drivers -v0x1c33870_0 .net *"_s18", 0 0, L_0x1e04400; 1 drivers -v0x1c33950_0 .net *"_s20", 0 0, L_0x1e044c0; 1 drivers -v0x1c33ac0_0 .net *"_s22", 0 0, L_0x1e04620; 1 drivers -v0x1c33ba0_0 .net *"_s24", 0 0, L_0x1e04ad0; 1 drivers -o0x7f7259379278 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c33c80_0 name=_s30 -o0x7f72593792a8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c33d60_0 name=_s32 -v0x1c33e40_0 .net *"_s8", 0 0, L_0x1e03b50; 1 drivers -v0x1c33f20_0 .net "carryin", 0 0, L_0x1e02af0; 1 drivers -v0x1c33fc0_0 .net "carryout", 0 0, L_0x1e0be80; 1 drivers -v0x1c34060_0 .net "carryouts", 7 0, L_0x1ec0420; 1 drivers -v0x1c34210_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c342b0_0 .net "result", 0 0, L_0x1e08440; 1 drivers -v0x1c343a0_0 .net "results", 7 0, L_0x1e048a0; 1 drivers -v0x1c344b0_0 .net "zero", 0 0, L_0x1e0c1e0; 1 drivers -LS_0x1e048a0_0_0 .concat8 [ 1 1 1 1], L_0x1e03070, L_0x1e036a0, L_0x1e03b50, L_0x1e04200; -LS_0x1e048a0_0_4 .concat8 [ 1 1 1 1], L_0x1e04400, L_0x1e044c0, L_0x1e04620, L_0x1e04ad0; -L_0x1e048a0 .concat8 [ 4 4 0 0], LS_0x1e048a0_0_0, LS_0x1e048a0_0_4; -LS_0x1ec0420_0_0 .concat [ 1 1 1 1], L_0x1e03320, L_0x1e039f0, o0x7f7259379278, L_0x1e04050; -LS_0x1ec0420_0_4 .concat [ 4 0 0 0], o0x7f72593792a8; -L_0x1ec0420 .concat [ 4 4 0 0], LS_0x1ec0420_0_0, LS_0x1ec0420_0_4; -S_0x1c24e40 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c24bc0; +L_0x128c1e0/d .functor NOT 1, L_0x129fa50, C4<0>, C4<0>, C4<0>; +L_0x128c1e0 .delay 1 (10000,10000,10000) L_0x128c1e0/d; +L_0x12962c0/d .functor NOT 1, L_0x1296100, C4<0>, C4<0>, C4<0>; +L_0x12962c0 .delay 1 (10000,10000,10000) L_0x12962c0/d; +L_0x12972c0/d .functor XOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; +L_0x12972c0 .delay 1 (30000,30000,30000) L_0x12972c0/d; +L_0x2b0ab3d06068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d060b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1297970/d .functor OR 1, L_0x2b0ab3d06068, L_0x2b0ab3d060b0, C4<0>, C4<0>; +L_0x1297970 .delay 1 (30000,30000,30000) L_0x1297970/d; +L_0x1297b70/d .functor AND 1, L_0x129fa50, L_0x1296100, C4<1>, C4<1>; +L_0x1297b70 .delay 1 (30000,30000,30000) L_0x1297b70/d; +L_0x1297c30/d .functor NAND 1, L_0x129fa50, L_0x1296100, C4<1>, C4<1>; +L_0x1297c30 .delay 1 (20000,20000,20000) L_0x1297c30/d; +L_0x1297d90/d .functor XOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; +L_0x1297d90 .delay 1 (20000,20000,20000) L_0x1297d90/d; +L_0x1298240/d .functor OR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; +L_0x1298240 .delay 1 (30000,30000,30000) L_0x1298240/d; +L_0x129f950/d .functor NOT 1, L_0x129bbb0, C4<0>, C4<0>, C4<0>; +L_0x129f950 .delay 1 (10000,10000,10000) L_0x129f950/d; +v0x10c5f70_0 .net "A", 0 0, L_0x129fa50; 1 drivers +v0x10c6030_0 .net "A_", 0 0, L_0x128c1e0; 1 drivers +v0x10c60f0_0 .net "B", 0 0, L_0x1296100; 1 drivers +v0x10c61c0_0 .net "B_", 0 0, L_0x12962c0; 1 drivers +v0x10c6260_0 .net *"_s12", 0 0, L_0x1297970; 1 drivers +v0x10c6350_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06068; 1 drivers +v0x10c6410_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d060b0; 1 drivers +v0x10c64f0_0 .net *"_s18", 0 0, L_0x1297b70; 1 drivers +v0x10c65d0_0 .net *"_s20", 0 0, L_0x1297c30; 1 drivers +v0x10c6740_0 .net *"_s22", 0 0, L_0x1297d90; 1 drivers +v0x10c6820_0 .net *"_s24", 0 0, L_0x1298240; 1 drivers +o0x2b0ab3cc8278 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10c6900_0 name=_s30 +o0x2b0ab3cc82a8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10c69e0_0 name=_s32 +v0x10c6ac0_0 .net *"_s8", 0 0, L_0x12972c0; 1 drivers +v0x10c6ba0_0 .net "carryin", 0 0, L_0x12961a0; 1 drivers +v0x10c6c40_0 .net "carryout", 0 0, L_0x129f5f0; 1 drivers +v0x10c6ce0_0 .net "carryouts", 7 0, L_0x1354750; 1 drivers +v0x10c6e90_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10c6f30_0 .net "result", 0 0, L_0x129bbb0; 1 drivers +v0x10c7020_0 .net "results", 7 0, L_0x1298010; 1 drivers +v0x10c7110_0 .net "zero", 0 0, L_0x129f950; 1 drivers +LS_0x1298010_0_0 .concat8 [ 1 1 1 1], L_0x12967e0, L_0x1296e10, L_0x12972c0, L_0x1297970; +LS_0x1298010_0_4 .concat8 [ 1 1 1 1], L_0x1297b70, L_0x1297c30, L_0x1297d90, L_0x1298240; +L_0x1298010 .concat8 [ 4 4 0 0], LS_0x1298010_0_0, LS_0x1298010_0_4; +LS_0x1354750_0_0 .concat [ 1 1 1 1], L_0x1296a90, L_0x1297160, o0x2b0ab3cc8278, L_0x12977c0; +LS_0x1354750_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc82a8; +L_0x1354750 .concat [ 4 4 0 0], LS_0x1354750_0_0, LS_0x1354750_0_4; +S_0x10b7ac0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10b7840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e03320/d .functor OR 1, L_0x1e02e00, L_0x1e031c0, C4<0>, C4<0>; -L_0x1e03320 .delay 1 (30000,30000,30000) L_0x1e03320/d; -v0x1c25c70_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers -v0x1c25d30_0 .net "b", 0 0, L_0x1e02a50; alias, 1 drivers -v0x1c25e00_0 .net "c1", 0 0, L_0x1e02e00; 1 drivers -v0x1c25f00_0 .net "c2", 0 0, L_0x1e031c0; 1 drivers -v0x1c25fd0_0 .net "carryin", 0 0, L_0x1e02af0; alias, 1 drivers -v0x1c260c0_0 .net "carryout", 0 0, L_0x1e03320; 1 drivers -v0x1c26160_0 .net "s1", 0 0, L_0x1dfc5b0; 1 drivers -v0x1c26250_0 .net "sum", 0 0, L_0x1e03070; 1 drivers -S_0x1c250b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c24e40; +L_0x1296a90/d .functor OR 1, L_0x1296570, L_0x1296930, C4<0>, C4<0>; +L_0x1296a90 .delay 1 (30000,30000,30000) L_0x1296a90/d; +v0x10b88f0_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers +v0x10b89b0_0 .net "b", 0 0, L_0x1296100; alias, 1 drivers +v0x10b8a80_0 .net "c1", 0 0, L_0x1296570; 1 drivers +v0x10b8b80_0 .net "c2", 0 0, L_0x1296930; 1 drivers +v0x10b8c50_0 .net "carryin", 0 0, L_0x12961a0; alias, 1 drivers +v0x10b8d40_0 .net "carryout", 0 0, L_0x1296a90; 1 drivers +v0x10b8de0_0 .net "s1", 0 0, L_0x12964b0; 1 drivers +v0x10b8ed0_0 .net "sum", 0 0, L_0x12967e0; 1 drivers +S_0x10b7d30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10b7ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1dfc5b0/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; -L_0x1dfc5b0 .delay 1 (30000,30000,30000) L_0x1dfc5b0/d; -L_0x1e02e00/d .functor AND 1, L_0x1e0c2e0, L_0x1e02a50, C4<1>, C4<1>; -L_0x1e02e00 .delay 1 (30000,30000,30000) L_0x1e02e00/d; -v0x1c25310_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers -v0x1c253f0_0 .net "b", 0 0, L_0x1e02a50; alias, 1 drivers -v0x1c254b0_0 .net "carryout", 0 0, L_0x1e02e00; alias, 1 drivers -v0x1c25550_0 .net "sum", 0 0, L_0x1dfc5b0; alias, 1 drivers -S_0x1c25690 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c24e40; +L_0x12964b0/d .functor XOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; +L_0x12964b0 .delay 1 (30000,30000,30000) L_0x12964b0/d; +L_0x1296570/d .functor AND 1, L_0x129fa50, L_0x1296100, C4<1>, C4<1>; +L_0x1296570 .delay 1 (30000,30000,30000) L_0x1296570/d; +v0x10b7f90_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers +v0x10b8070_0 .net "b", 0 0, L_0x1296100; alias, 1 drivers +v0x10b8130_0 .net "carryout", 0 0, L_0x1296570; alias, 1 drivers +v0x10b81d0_0 .net "sum", 0 0, L_0x12964b0; alias, 1 drivers +S_0x10b8310 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10b7ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e03070/d .functor XOR 1, L_0x1dfc5b0, L_0x1e02af0, C4<0>, C4<0>; -L_0x1e03070 .delay 1 (30000,30000,30000) L_0x1e03070/d; -L_0x1e031c0/d .functor AND 1, L_0x1dfc5b0, L_0x1e02af0, C4<1>, C4<1>; -L_0x1e031c0 .delay 1 (30000,30000,30000) L_0x1e031c0/d; -v0x1c258f0_0 .net "a", 0 0, L_0x1dfc5b0; alias, 1 drivers -v0x1c25990_0 .net "b", 0 0, L_0x1e02af0; alias, 1 drivers -v0x1c25a30_0 .net "carryout", 0 0, L_0x1e031c0; alias, 1 drivers -v0x1c25b00_0 .net "sum", 0 0, L_0x1e03070; alias, 1 drivers -S_0x1c26320 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c24bc0; +L_0x12967e0/d .functor XOR 1, L_0x12964b0, L_0x12961a0, C4<0>, C4<0>; +L_0x12967e0 .delay 1 (30000,30000,30000) L_0x12967e0/d; +L_0x1296930/d .functor AND 1, L_0x12964b0, L_0x12961a0, C4<1>, C4<1>; +L_0x1296930 .delay 1 (30000,30000,30000) L_0x1296930/d; +v0x10b8570_0 .net "a", 0 0, L_0x12964b0; alias, 1 drivers +v0x10b8610_0 .net "b", 0 0, L_0x12961a0; alias, 1 drivers +v0x10b86b0_0 .net "carryout", 0 0, L_0x1296930; alias, 1 drivers +v0x10b8780_0 .net "sum", 0 0, L_0x12967e0; alias, 1 drivers +S_0x10b8fa0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10b7840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c2b710_0 .net "ands", 7 0, L_0x1e09e80; 1 drivers -v0x1c2b820_0 .net "in", 7 0, L_0x1ec0420; alias, 1 drivers -v0x1c2b8e0_0 .net "out", 0 0, L_0x1e0be80; alias, 1 drivers -v0x1c2b9b0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c26540 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c26320; +v0x10be390_0 .net "ands", 7 0, L_0x129d5f0; 1 drivers +v0x10be4a0_0 .net "in", 7 0, L_0x1354750; alias, 1 drivers +v0x10be560_0 .net "out", 0 0, L_0x129f5f0; alias, 1 drivers +v0x10be630_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10b91c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10b8fa0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c28c70_0 .net "A", 7 0, L_0x1ec0420; alias, 1 drivers -v0x1c28d70_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c28e30_0 .net *"_s0", 0 0, L_0x1e087a0; 1 drivers -v0x1c28ef0_0 .net *"_s12", 0 0, L_0x1e09110; 1 drivers -v0x1c28fd0_0 .net *"_s16", 0 0, L_0x1e09470; 1 drivers -v0x1c29100_0 .net *"_s20", 0 0, L_0x1e09780; 1 drivers -v0x1c291e0_0 .net *"_s24", 0 0, L_0x1e09b70; 1 drivers -v0x1c292c0_0 .net *"_s28", 0 0, L_0x1e09b00; 1 drivers -v0x1c293a0_0 .net *"_s4", 0 0, L_0x1e08ab0; 1 drivers -v0x1c29510_0 .net *"_s8", 0 0, L_0x1e08e00; 1 drivers -v0x1c295f0_0 .net "out", 7 0, L_0x1e09e80; alias, 1 drivers -L_0x1e08860 .part L_0x1ec0420, 0, 1; -L_0x1e089c0 .part v0x1d6daa0_0, 0, 1; -L_0x1e08b70 .part L_0x1ec0420, 1, 1; -L_0x1e08d60 .part v0x1d6daa0_0, 1, 1; -L_0x1e08ec0 .part L_0x1ec0420, 2, 1; -L_0x1e09020 .part v0x1d6daa0_0, 2, 1; -L_0x1e091d0 .part L_0x1ec0420, 3, 1; -L_0x1e09330 .part v0x1d6daa0_0, 3, 1; -L_0x1e09530 .part L_0x1ec0420, 4, 1; -L_0x1e09690 .part v0x1d6daa0_0, 4, 1; -L_0x1e097f0 .part L_0x1ec0420, 5, 1; -L_0x1e09a60 .part v0x1d6daa0_0, 5, 1; -L_0x1e09c30 .part L_0x1ec0420, 6, 1; -L_0x1e09d90 .part v0x1d6daa0_0, 6, 1; -LS_0x1e09e80_0_0 .concat8 [ 1 1 1 1], L_0x1e087a0, L_0x1e08ab0, L_0x1e08e00, L_0x1e09110; -LS_0x1e09e80_0_4 .concat8 [ 1 1 1 1], L_0x1e09470, L_0x1e09780, L_0x1e09b70, L_0x1e09b00; -L_0x1e09e80 .concat8 [ 4 4 0 0], LS_0x1e09e80_0_0, LS_0x1e09e80_0_4; -L_0x1e0a240 .part L_0x1ec0420, 7, 1; -L_0x1e0a430 .part v0x1d6daa0_0, 7, 1; -S_0x1c267a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c269b0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e087a0/d .functor AND 1, L_0x1e08860, L_0x1e089c0, C4<1>, C4<1>; -L_0x1e087a0 .delay 1 (30000,30000,30000) L_0x1e087a0/d; -v0x1c26a90_0 .net *"_s0", 0 0, L_0x1e08860; 1 drivers -v0x1c26b70_0 .net *"_s1", 0 0, L_0x1e089c0; 1 drivers -S_0x1c26c50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c26e60 .param/l "i" 0 4 54, +C4<01>; -L_0x1e08ab0/d .functor AND 1, L_0x1e08b70, L_0x1e08d60, C4<1>, C4<1>; -L_0x1e08ab0 .delay 1 (30000,30000,30000) L_0x1e08ab0/d; -v0x1c26f20_0 .net *"_s0", 0 0, L_0x1e08b70; 1 drivers -v0x1c27000_0 .net *"_s1", 0 0, L_0x1e08d60; 1 drivers -S_0x1c270e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c272f0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e08e00/d .functor AND 1, L_0x1e08ec0, L_0x1e09020, C4<1>, C4<1>; -L_0x1e08e00 .delay 1 (30000,30000,30000) L_0x1e08e00/d; -v0x1c27390_0 .net *"_s0", 0 0, L_0x1e08ec0; 1 drivers -v0x1c27470_0 .net *"_s1", 0 0, L_0x1e09020; 1 drivers -S_0x1c27550 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c27760 .param/l "i" 0 4 54, +C4<011>; -L_0x1e09110/d .functor AND 1, L_0x1e091d0, L_0x1e09330, C4<1>, C4<1>; -L_0x1e09110 .delay 1 (30000,30000,30000) L_0x1e09110/d; -v0x1c27820_0 .net *"_s0", 0 0, L_0x1e091d0; 1 drivers -v0x1c27900_0 .net *"_s1", 0 0, L_0x1e09330; 1 drivers -S_0x1c279e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c27c40 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e09470/d .functor AND 1, L_0x1e09530, L_0x1e09690, C4<1>, C4<1>; -L_0x1e09470 .delay 1 (30000,30000,30000) L_0x1e09470/d; -v0x1c27d00_0 .net *"_s0", 0 0, L_0x1e09530; 1 drivers -v0x1c27de0_0 .net *"_s1", 0 0, L_0x1e09690; 1 drivers -S_0x1c27ec0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c280d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e09780/d .functor AND 1, L_0x1e097f0, L_0x1e09a60, C4<1>, C4<1>; -L_0x1e09780 .delay 1 (30000,30000,30000) L_0x1e09780/d; -v0x1c28190_0 .net *"_s0", 0 0, L_0x1e097f0; 1 drivers -v0x1c28270_0 .net *"_s1", 0 0, L_0x1e09a60; 1 drivers -S_0x1c28350 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c28560 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e09b70/d .functor AND 1, L_0x1e09c30, L_0x1e09d90, C4<1>, C4<1>; -L_0x1e09b70 .delay 1 (30000,30000,30000) L_0x1e09b70/d; -v0x1c28620_0 .net *"_s0", 0 0, L_0x1e09c30; 1 drivers -v0x1c28700_0 .net *"_s1", 0 0, L_0x1e09d90; 1 drivers -S_0x1c287e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c26540; - .timescale -9 -12; -P_0x1c289f0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e09b00/d .functor AND 1, L_0x1e0a240, L_0x1e0a430, C4<1>, C4<1>; -L_0x1e09b00 .delay 1 (30000,30000,30000) L_0x1e09b00/d; -v0x1c28ab0_0 .net *"_s0", 0 0, L_0x1e0a240; 1 drivers -v0x1c28b90_0 .net *"_s1", 0 0, L_0x1e0a430; 1 drivers -S_0x1c29750 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c26320; +v0x10bb8f0_0 .net "A", 7 0, L_0x1354750; alias, 1 drivers +v0x10bb9f0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10bbab0_0 .net *"_s0", 0 0, L_0x129bf10; 1 drivers +v0x10bbb70_0 .net *"_s12", 0 0, L_0x129c880; 1 drivers +v0x10bbc50_0 .net *"_s16", 0 0, L_0x129cbe0; 1 drivers +v0x10bbd80_0 .net *"_s20", 0 0, L_0x129cef0; 1 drivers +v0x10bbe60_0 .net *"_s24", 0 0, L_0x129d2e0; 1 drivers +v0x10bbf40_0 .net *"_s28", 0 0, L_0x129d270; 1 drivers +v0x10bc020_0 .net *"_s4", 0 0, L_0x129c220; 1 drivers +v0x10bc190_0 .net *"_s8", 0 0, L_0x129c570; 1 drivers +v0x10bc270_0 .net "out", 7 0, L_0x129d5f0; alias, 1 drivers +L_0x129bfd0 .part L_0x1354750, 0, 1; +L_0x129c130 .part v0x12010b0_0, 0, 1; +L_0x129c2e0 .part L_0x1354750, 1, 1; +L_0x129c4d0 .part v0x12010b0_0, 1, 1; +L_0x129c630 .part L_0x1354750, 2, 1; +L_0x129c790 .part v0x12010b0_0, 2, 1; +L_0x129c940 .part L_0x1354750, 3, 1; +L_0x129caa0 .part v0x12010b0_0, 3, 1; +L_0x129cca0 .part L_0x1354750, 4, 1; +L_0x129ce00 .part v0x12010b0_0, 4, 1; +L_0x129cf60 .part L_0x1354750, 5, 1; +L_0x129d1d0 .part v0x12010b0_0, 5, 1; +L_0x129d3a0 .part L_0x1354750, 6, 1; +L_0x129d500 .part v0x12010b0_0, 6, 1; +LS_0x129d5f0_0_0 .concat8 [ 1 1 1 1], L_0x129bf10, L_0x129c220, L_0x129c570, L_0x129c880; +LS_0x129d5f0_0_4 .concat8 [ 1 1 1 1], L_0x129cbe0, L_0x129cef0, L_0x129d2e0, L_0x129d270; +L_0x129d5f0 .concat8 [ 4 4 0 0], LS_0x129d5f0_0_0, LS_0x129d5f0_0_4; +L_0x129d9b0 .part L_0x1354750, 7, 1; +L_0x129dba0 .part v0x12010b0_0, 7, 1; +S_0x10b9420 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10b9630 .param/l "i" 0 4 54, +C4<00>; +L_0x129bf10/d .functor AND 1, L_0x129bfd0, L_0x129c130, C4<1>, C4<1>; +L_0x129bf10 .delay 1 (30000,30000,30000) L_0x129bf10/d; +v0x10b9710_0 .net *"_s0", 0 0, L_0x129bfd0; 1 drivers +v0x10b97f0_0 .net *"_s1", 0 0, L_0x129c130; 1 drivers +S_0x10b98d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10b9ae0 .param/l "i" 0 4 54, +C4<01>; +L_0x129c220/d .functor AND 1, L_0x129c2e0, L_0x129c4d0, C4<1>, C4<1>; +L_0x129c220 .delay 1 (30000,30000,30000) L_0x129c220/d; +v0x10b9ba0_0 .net *"_s0", 0 0, L_0x129c2e0; 1 drivers +v0x10b9c80_0 .net *"_s1", 0 0, L_0x129c4d0; 1 drivers +S_0x10b9d60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10b9f70 .param/l "i" 0 4 54, +C4<010>; +L_0x129c570/d .functor AND 1, L_0x129c630, L_0x129c790, C4<1>, C4<1>; +L_0x129c570 .delay 1 (30000,30000,30000) L_0x129c570/d; +v0x10ba010_0 .net *"_s0", 0 0, L_0x129c630; 1 drivers +v0x10ba0f0_0 .net *"_s1", 0 0, L_0x129c790; 1 drivers +S_0x10ba1d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10ba3e0 .param/l "i" 0 4 54, +C4<011>; +L_0x129c880/d .functor AND 1, L_0x129c940, L_0x129caa0, C4<1>, C4<1>; +L_0x129c880 .delay 1 (30000,30000,30000) L_0x129c880/d; +v0x10ba4a0_0 .net *"_s0", 0 0, L_0x129c940; 1 drivers +v0x10ba580_0 .net *"_s1", 0 0, L_0x129caa0; 1 drivers +S_0x10ba660 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10ba8c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x129cbe0/d .functor AND 1, L_0x129cca0, L_0x129ce00, C4<1>, C4<1>; +L_0x129cbe0 .delay 1 (30000,30000,30000) L_0x129cbe0/d; +v0x10ba980_0 .net *"_s0", 0 0, L_0x129cca0; 1 drivers +v0x10baa60_0 .net *"_s1", 0 0, L_0x129ce00; 1 drivers +S_0x10bab40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10bad50 .param/l "i" 0 4 54, +C4<0101>; +L_0x129cef0/d .functor AND 1, L_0x129cf60, L_0x129d1d0, C4<1>, C4<1>; +L_0x129cef0 .delay 1 (30000,30000,30000) L_0x129cef0/d; +v0x10bae10_0 .net *"_s0", 0 0, L_0x129cf60; 1 drivers +v0x10baef0_0 .net *"_s1", 0 0, L_0x129d1d0; 1 drivers +S_0x10bafd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10bb1e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x129d2e0/d .functor AND 1, L_0x129d3a0, L_0x129d500, C4<1>, C4<1>; +L_0x129d2e0 .delay 1 (30000,30000,30000) L_0x129d2e0/d; +v0x10bb2a0_0 .net *"_s0", 0 0, L_0x129d3a0; 1 drivers +v0x10bb380_0 .net *"_s1", 0 0, L_0x129d500; 1 drivers +S_0x10bb460 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10b91c0; + .timescale -9 -12; +P_0x10bb670 .param/l "i" 0 4 54, +C4<0111>; +L_0x129d270/d .functor AND 1, L_0x129d9b0, L_0x129dba0, C4<1>, C4<1>; +L_0x129d270 .delay 1 (30000,30000,30000) L_0x129d270/d; +v0x10bb730_0 .net *"_s0", 0 0, L_0x129d9b0; 1 drivers +v0x10bb810_0 .net *"_s1", 0 0, L_0x129dba0; 1 drivers +S_0x10bc3d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10b8fa0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e0be80/d .functor OR 1, L_0x1e0bf40, L_0x1e0c0f0, C4<0>, C4<0>; -L_0x1e0be80 .delay 1 (30000,30000,30000) L_0x1e0be80/d; -v0x1c2b2a0_0 .net *"_s10", 0 0, L_0x1e0bf40; 1 drivers -v0x1c2b380_0 .net *"_s12", 0 0, L_0x1e0c0f0; 1 drivers -v0x1c2b460_0 .net "in", 7 0, L_0x1e09e80; alias, 1 drivers -v0x1c2b530_0 .net "ors", 1 0, L_0x1e0bca0; 1 drivers -v0x1c2b5f0_0 .net "out", 0 0, L_0x1e0be80; alias, 1 drivers -L_0x1e0b070 .part L_0x1e09e80, 0, 4; -L_0x1e0bca0 .concat8 [ 1 1 0 0], L_0x1e0ad60, L_0x1e0b990; -L_0x1e0bde0 .part L_0x1e09e80, 4, 4; -L_0x1e0bf40 .part L_0x1e0bca0, 0, 1; -L_0x1e0c0f0 .part L_0x1e0bca0, 1, 1; -S_0x1c29910 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c29750; +L_0x129f5f0/d .functor OR 1, L_0x129f6b0, L_0x129f860, C4<0>, C4<0>; +L_0x129f5f0 .delay 1 (30000,30000,30000) L_0x129f5f0/d; +v0x10bdf20_0 .net *"_s10", 0 0, L_0x129f6b0; 1 drivers +v0x10be000_0 .net *"_s12", 0 0, L_0x129f860; 1 drivers +v0x10be0e0_0 .net "in", 7 0, L_0x129d5f0; alias, 1 drivers +v0x10be1b0_0 .net "ors", 1 0, L_0x129f410; 1 drivers +v0x10be270_0 .net "out", 0 0, L_0x129f5f0; alias, 1 drivers +L_0x129e7e0 .part L_0x129d5f0, 0, 4; +L_0x129f410 .concat8 [ 1 1 0 0], L_0x129e4d0, L_0x129f100; +L_0x129f550 .part L_0x129d5f0, 4, 4; +L_0x129f6b0 .part L_0x129f410, 0, 1; +L_0x129f860 .part L_0x129f410, 1, 1; +S_0x10bc590 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10bc3d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e0a520/d .functor OR 1, L_0x1e0a5e0, L_0x1e0a740, C4<0>, C4<0>; -L_0x1e0a520 .delay 1 (30000,30000,30000) L_0x1e0a520/d; -L_0x1e0a970/d .functor OR 1, L_0x1e0aa80, L_0x1e0abe0, C4<0>, C4<0>; -L_0x1e0a970 .delay 1 (30000,30000,30000) L_0x1e0a970/d; -L_0x1e0ad60/d .functor OR 1, L_0x1e0add0, L_0x1e0af80, C4<0>, C4<0>; -L_0x1e0ad60 .delay 1 (30000,30000,30000) L_0x1e0ad60/d; -v0x1c29b60_0 .net *"_s0", 0 0, L_0x1e0a520; 1 drivers -v0x1c29c60_0 .net *"_s10", 0 0, L_0x1e0aa80; 1 drivers -v0x1c29d40_0 .net *"_s12", 0 0, L_0x1e0abe0; 1 drivers -v0x1c29e00_0 .net *"_s14", 0 0, L_0x1e0add0; 1 drivers -v0x1c29ee0_0 .net *"_s16", 0 0, L_0x1e0af80; 1 drivers -v0x1c2a010_0 .net *"_s3", 0 0, L_0x1e0a5e0; 1 drivers -v0x1c2a0f0_0 .net *"_s5", 0 0, L_0x1e0a740; 1 drivers -v0x1c2a1d0_0 .net *"_s6", 0 0, L_0x1e0a970; 1 drivers -v0x1c2a2b0_0 .net "in", 3 0, L_0x1e0b070; 1 drivers -v0x1c2a420_0 .net "ors", 1 0, L_0x1e0a880; 1 drivers -v0x1c2a500_0 .net "out", 0 0, L_0x1e0ad60; 1 drivers -L_0x1e0a5e0 .part L_0x1e0b070, 0, 1; -L_0x1e0a740 .part L_0x1e0b070, 1, 1; -L_0x1e0a880 .concat8 [ 1 1 0 0], L_0x1e0a520, L_0x1e0a970; -L_0x1e0aa80 .part L_0x1e0b070, 2, 1; -L_0x1e0abe0 .part L_0x1e0b070, 3, 1; -L_0x1e0add0 .part L_0x1e0a880, 0, 1; -L_0x1e0af80 .part L_0x1e0a880, 1, 1; -S_0x1c2a620 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c29750; +L_0x129dc90/d .functor OR 1, L_0x129dd50, L_0x129deb0, C4<0>, C4<0>; +L_0x129dc90 .delay 1 (30000,30000,30000) L_0x129dc90/d; +L_0x129e0e0/d .functor OR 1, L_0x129e1f0, L_0x129e350, C4<0>, C4<0>; +L_0x129e0e0 .delay 1 (30000,30000,30000) L_0x129e0e0/d; +L_0x129e4d0/d .functor OR 1, L_0x129e540, L_0x129e6f0, C4<0>, C4<0>; +L_0x129e4d0 .delay 1 (30000,30000,30000) L_0x129e4d0/d; +v0x10bc7e0_0 .net *"_s0", 0 0, L_0x129dc90; 1 drivers +v0x10bc8e0_0 .net *"_s10", 0 0, L_0x129e1f0; 1 drivers +v0x10bc9c0_0 .net *"_s12", 0 0, L_0x129e350; 1 drivers +v0x10bca80_0 .net *"_s14", 0 0, L_0x129e540; 1 drivers +v0x10bcb60_0 .net *"_s16", 0 0, L_0x129e6f0; 1 drivers +v0x10bcc90_0 .net *"_s3", 0 0, L_0x129dd50; 1 drivers +v0x10bcd70_0 .net *"_s5", 0 0, L_0x129deb0; 1 drivers +v0x10bce50_0 .net *"_s6", 0 0, L_0x129e0e0; 1 drivers +v0x10bcf30_0 .net "in", 3 0, L_0x129e7e0; 1 drivers +v0x10bd0a0_0 .net "ors", 1 0, L_0x129dff0; 1 drivers +v0x10bd180_0 .net "out", 0 0, L_0x129e4d0; 1 drivers +L_0x129dd50 .part L_0x129e7e0, 0, 1; +L_0x129deb0 .part L_0x129e7e0, 1, 1; +L_0x129dff0 .concat8 [ 1 1 0 0], L_0x129dc90, L_0x129e0e0; +L_0x129e1f0 .part L_0x129e7e0, 2, 1; +L_0x129e350 .part L_0x129e7e0, 3, 1; +L_0x129e540 .part L_0x129dff0, 0, 1; +L_0x129e6f0 .part L_0x129dff0, 1, 1; +S_0x10bd2a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10bc3d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e0b1a0/d .functor OR 1, L_0x1e0b210, L_0x1e0b370, C4<0>, C4<0>; -L_0x1e0b1a0 .delay 1 (30000,30000,30000) L_0x1e0b1a0/d; -L_0x1e0b5a0/d .functor OR 1, L_0x1e0b6b0, L_0x1e0b810, C4<0>, C4<0>; -L_0x1e0b5a0 .delay 1 (30000,30000,30000) L_0x1e0b5a0/d; -L_0x1e0b990/d .functor OR 1, L_0x1e0ba00, L_0x1e0bbb0, C4<0>, C4<0>; -L_0x1e0b990 .delay 1 (30000,30000,30000) L_0x1e0b990/d; -v0x1c2a7e0_0 .net *"_s0", 0 0, L_0x1e0b1a0; 1 drivers -v0x1c2a8e0_0 .net *"_s10", 0 0, L_0x1e0b6b0; 1 drivers -v0x1c2a9c0_0 .net *"_s12", 0 0, L_0x1e0b810; 1 drivers -v0x1c2aa80_0 .net *"_s14", 0 0, L_0x1e0ba00; 1 drivers -v0x1c2ab60_0 .net *"_s16", 0 0, L_0x1e0bbb0; 1 drivers -v0x1c2ac90_0 .net *"_s3", 0 0, L_0x1e0b210; 1 drivers -v0x1c2ad70_0 .net *"_s5", 0 0, L_0x1e0b370; 1 drivers -v0x1c2ae50_0 .net *"_s6", 0 0, L_0x1e0b5a0; 1 drivers -v0x1c2af30_0 .net "in", 3 0, L_0x1e0bde0; 1 drivers -v0x1c2b0a0_0 .net "ors", 1 0, L_0x1e0b4b0; 1 drivers -v0x1c2b180_0 .net "out", 0 0, L_0x1e0b990; 1 drivers -L_0x1e0b210 .part L_0x1e0bde0, 0, 1; -L_0x1e0b370 .part L_0x1e0bde0, 1, 1; -L_0x1e0b4b0 .concat8 [ 1 1 0 0], L_0x1e0b1a0, L_0x1e0b5a0; -L_0x1e0b6b0 .part L_0x1e0bde0, 2, 1; -L_0x1e0b810 .part L_0x1e0bde0, 3, 1; -L_0x1e0ba00 .part L_0x1e0b4b0, 0, 1; -L_0x1e0bbb0 .part L_0x1e0b4b0, 1, 1; -S_0x1c2ba90 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c24bc0; +L_0x129e910/d .functor OR 1, L_0x129e980, L_0x129eae0, C4<0>, C4<0>; +L_0x129e910 .delay 1 (30000,30000,30000) L_0x129e910/d; +L_0x129ed10/d .functor OR 1, L_0x129ee20, L_0x129ef80, C4<0>, C4<0>; +L_0x129ed10 .delay 1 (30000,30000,30000) L_0x129ed10/d; +L_0x129f100/d .functor OR 1, L_0x129f170, L_0x129f320, C4<0>, C4<0>; +L_0x129f100 .delay 1 (30000,30000,30000) L_0x129f100/d; +v0x10bd460_0 .net *"_s0", 0 0, L_0x129e910; 1 drivers +v0x10bd560_0 .net *"_s10", 0 0, L_0x129ee20; 1 drivers +v0x10bd640_0 .net *"_s12", 0 0, L_0x129ef80; 1 drivers +v0x10bd700_0 .net *"_s14", 0 0, L_0x129f170; 1 drivers +v0x10bd7e0_0 .net *"_s16", 0 0, L_0x129f320; 1 drivers +v0x10bd910_0 .net *"_s3", 0 0, L_0x129e980; 1 drivers +v0x10bd9f0_0 .net *"_s5", 0 0, L_0x129eae0; 1 drivers +v0x10bdad0_0 .net *"_s6", 0 0, L_0x129ed10; 1 drivers +v0x10bdbb0_0 .net "in", 3 0, L_0x129f550; 1 drivers +v0x10bdd20_0 .net "ors", 1 0, L_0x129ec20; 1 drivers +v0x10bde00_0 .net "out", 0 0, L_0x129f100; 1 drivers +L_0x129e980 .part L_0x129f550, 0, 1; +L_0x129eae0 .part L_0x129f550, 1, 1; +L_0x129ec20 .concat8 [ 1 1 0 0], L_0x129e910, L_0x129ed10; +L_0x129ee20 .part L_0x129f550, 2, 1; +L_0x129ef80 .part L_0x129f550, 3, 1; +L_0x129f170 .part L_0x129ec20, 0, 1; +L_0x129f320 .part L_0x129ec20, 1, 1; +S_0x10be710 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10b7840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c30ec0_0 .net "ands", 7 0, L_0x1e06440; 1 drivers -v0x1c30fd0_0 .net "in", 7 0, L_0x1e048a0; alias, 1 drivers -v0x1c31090_0 .net "out", 0 0, L_0x1e08440; alias, 1 drivers -v0x1c31160_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c2bce0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c2ba90; +v0x10c3b40_0 .net "ands", 7 0, L_0x1299bb0; 1 drivers +v0x10c3c50_0 .net "in", 7 0, L_0x1298010; alias, 1 drivers +v0x10c3d10_0 .net "out", 0 0, L_0x129bbb0; alias, 1 drivers +v0x10c3de0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10be960 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10be710; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c2e420_0 .net "A", 7 0, L_0x1e048a0; alias, 1 drivers -v0x1c2e520_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c2e5e0_0 .net *"_s0", 0 0, L_0x1e04c30; 1 drivers -v0x1c2e6a0_0 .net *"_s12", 0 0, L_0x1e055f0; 1 drivers -v0x1c2e780_0 .net *"_s16", 0 0, L_0x1e05950; 1 drivers -v0x1c2e8b0_0 .net *"_s20", 0 0, L_0x1e05d80; 1 drivers -v0x1c2e990_0 .net *"_s24", 0 0, L_0x1e060b0; 1 drivers -v0x1c2ea70_0 .net *"_s28", 0 0, L_0x1e06040; 1 drivers -v0x1c2eb50_0 .net *"_s4", 0 0, L_0x1e04fd0; 1 drivers -v0x1c2ecc0_0 .net *"_s8", 0 0, L_0x1e052e0; 1 drivers -v0x1c2eda0_0 .net "out", 7 0, L_0x1e06440; alias, 1 drivers -L_0x1e04d40 .part L_0x1e048a0, 0, 1; -L_0x1e04f30 .part v0x1d6daa0_0, 0, 1; -L_0x1e05090 .part L_0x1e048a0, 1, 1; -L_0x1e051f0 .part v0x1d6daa0_0, 1, 1; -L_0x1e053a0 .part L_0x1e048a0, 2, 1; -L_0x1e05500 .part v0x1d6daa0_0, 2, 1; -L_0x1e056b0 .part L_0x1e048a0, 3, 1; -L_0x1e05810 .part v0x1d6daa0_0, 3, 1; -L_0x1e05a10 .part L_0x1e048a0, 4, 1; -L_0x1e05c80 .part v0x1d6daa0_0, 4, 1; -L_0x1e05df0 .part L_0x1e048a0, 5, 1; -L_0x1e05f50 .part v0x1d6daa0_0, 5, 1; -L_0x1e06170 .part L_0x1e048a0, 6, 1; -L_0x1e062d0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e06440_0_0 .concat8 [ 1 1 1 1], L_0x1e04c30, L_0x1e04fd0, L_0x1e052e0, L_0x1e055f0; -LS_0x1e06440_0_4 .concat8 [ 1 1 1 1], L_0x1e05950, L_0x1e05d80, L_0x1e060b0, L_0x1e06040; -L_0x1e06440 .concat8 [ 4 4 0 0], LS_0x1e06440_0_0, LS_0x1e06440_0_4; -L_0x1e06800 .part L_0x1e048a0, 7, 1; -L_0x1e069f0 .part v0x1d6daa0_0, 7, 1; -S_0x1c2bf20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2c130 .param/l "i" 0 4 54, +C4<00>; -L_0x1e04c30/d .functor AND 1, L_0x1e04d40, L_0x1e04f30, C4<1>, C4<1>; -L_0x1e04c30 .delay 1 (30000,30000,30000) L_0x1e04c30/d; -v0x1c2c210_0 .net *"_s0", 0 0, L_0x1e04d40; 1 drivers -v0x1c2c2f0_0 .net *"_s1", 0 0, L_0x1e04f30; 1 drivers -S_0x1c2c3d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2c5e0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e04fd0/d .functor AND 1, L_0x1e05090, L_0x1e051f0, C4<1>, C4<1>; -L_0x1e04fd0 .delay 1 (30000,30000,30000) L_0x1e04fd0/d; -v0x1c2c6a0_0 .net *"_s0", 0 0, L_0x1e05090; 1 drivers -v0x1c2c780_0 .net *"_s1", 0 0, L_0x1e051f0; 1 drivers -S_0x1c2c860 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2caa0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e052e0/d .functor AND 1, L_0x1e053a0, L_0x1e05500, C4<1>, C4<1>; -L_0x1e052e0 .delay 1 (30000,30000,30000) L_0x1e052e0/d; -v0x1c2cb40_0 .net *"_s0", 0 0, L_0x1e053a0; 1 drivers -v0x1c2cc20_0 .net *"_s1", 0 0, L_0x1e05500; 1 drivers -S_0x1c2cd00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2cf10 .param/l "i" 0 4 54, +C4<011>; -L_0x1e055f0/d .functor AND 1, L_0x1e056b0, L_0x1e05810, C4<1>, C4<1>; -L_0x1e055f0 .delay 1 (30000,30000,30000) L_0x1e055f0/d; -v0x1c2cfd0_0 .net *"_s0", 0 0, L_0x1e056b0; 1 drivers -v0x1c2d0b0_0 .net *"_s1", 0 0, L_0x1e05810; 1 drivers -S_0x1c2d190 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2d3f0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e05950/d .functor AND 1, L_0x1e05a10, L_0x1e05c80, C4<1>, C4<1>; -L_0x1e05950 .delay 1 (30000,30000,30000) L_0x1e05950/d; -v0x1c2d4b0_0 .net *"_s0", 0 0, L_0x1e05a10; 1 drivers -v0x1c2d590_0 .net *"_s1", 0 0, L_0x1e05c80; 1 drivers -S_0x1c2d670 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2d880 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e05d80/d .functor AND 1, L_0x1e05df0, L_0x1e05f50, C4<1>, C4<1>; -L_0x1e05d80 .delay 1 (30000,30000,30000) L_0x1e05d80/d; -v0x1c2d940_0 .net *"_s0", 0 0, L_0x1e05df0; 1 drivers -v0x1c2da20_0 .net *"_s1", 0 0, L_0x1e05f50; 1 drivers -S_0x1c2db00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2dd10 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e060b0/d .functor AND 1, L_0x1e06170, L_0x1e062d0, C4<1>, C4<1>; -L_0x1e060b0 .delay 1 (30000,30000,30000) L_0x1e060b0/d; -v0x1c2ddd0_0 .net *"_s0", 0 0, L_0x1e06170; 1 drivers -v0x1c2deb0_0 .net *"_s1", 0 0, L_0x1e062d0; 1 drivers -S_0x1c2df90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c2bce0; - .timescale -9 -12; -P_0x1c2e180 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e06040/d .functor AND 1, L_0x1e06800, L_0x1e069f0, C4<1>, C4<1>; -L_0x1e06040 .delay 1 (30000,30000,30000) L_0x1e06040/d; -v0x1c2e260_0 .net *"_s0", 0 0, L_0x1e06800; 1 drivers -v0x1c2e340_0 .net *"_s1", 0 0, L_0x1e069f0; 1 drivers -S_0x1c2ef00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c2ba90; +v0x10c10a0_0 .net "A", 7 0, L_0x1298010; alias, 1 drivers +v0x10c11a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10c1260_0 .net *"_s0", 0 0, L_0x12983a0; 1 drivers +v0x10c1320_0 .net *"_s12", 0 0, L_0x1298d60; 1 drivers +v0x10c1400_0 .net *"_s16", 0 0, L_0x12990c0; 1 drivers +v0x10c1530_0 .net *"_s20", 0 0, L_0x12994f0; 1 drivers +v0x10c1610_0 .net *"_s24", 0 0, L_0x1299820; 1 drivers +v0x10c16f0_0 .net *"_s28", 0 0, L_0x12997b0; 1 drivers +v0x10c17d0_0 .net *"_s4", 0 0, L_0x1298740; 1 drivers +v0x10c1940_0 .net *"_s8", 0 0, L_0x1298a50; 1 drivers +v0x10c1a20_0 .net "out", 7 0, L_0x1299bb0; alias, 1 drivers +L_0x12984b0 .part L_0x1298010, 0, 1; +L_0x12986a0 .part v0x12010b0_0, 0, 1; +L_0x1298800 .part L_0x1298010, 1, 1; +L_0x1298960 .part v0x12010b0_0, 1, 1; +L_0x1298b10 .part L_0x1298010, 2, 1; +L_0x1298c70 .part v0x12010b0_0, 2, 1; +L_0x1298e20 .part L_0x1298010, 3, 1; +L_0x1298f80 .part v0x12010b0_0, 3, 1; +L_0x1299180 .part L_0x1298010, 4, 1; +L_0x12993f0 .part v0x12010b0_0, 4, 1; +L_0x1299560 .part L_0x1298010, 5, 1; +L_0x12996c0 .part v0x12010b0_0, 5, 1; +L_0x12998e0 .part L_0x1298010, 6, 1; +L_0x1299a40 .part v0x12010b0_0, 6, 1; +LS_0x1299bb0_0_0 .concat8 [ 1 1 1 1], L_0x12983a0, L_0x1298740, L_0x1298a50, L_0x1298d60; +LS_0x1299bb0_0_4 .concat8 [ 1 1 1 1], L_0x12990c0, L_0x12994f0, L_0x1299820, L_0x12997b0; +L_0x1299bb0 .concat8 [ 4 4 0 0], LS_0x1299bb0_0_0, LS_0x1299bb0_0_4; +L_0x1299f70 .part L_0x1298010, 7, 1; +L_0x129a160 .part v0x12010b0_0, 7, 1; +S_0x10beba0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10bedb0 .param/l "i" 0 4 54, +C4<00>; +L_0x12983a0/d .functor AND 1, L_0x12984b0, L_0x12986a0, C4<1>, C4<1>; +L_0x12983a0 .delay 1 (30000,30000,30000) L_0x12983a0/d; +v0x10bee90_0 .net *"_s0", 0 0, L_0x12984b0; 1 drivers +v0x10bef70_0 .net *"_s1", 0 0, L_0x12986a0; 1 drivers +S_0x10bf050 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10bf260 .param/l "i" 0 4 54, +C4<01>; +L_0x1298740/d .functor AND 1, L_0x1298800, L_0x1298960, C4<1>, C4<1>; +L_0x1298740 .delay 1 (30000,30000,30000) L_0x1298740/d; +v0x10bf320_0 .net *"_s0", 0 0, L_0x1298800; 1 drivers +v0x10bf400_0 .net *"_s1", 0 0, L_0x1298960; 1 drivers +S_0x10bf4e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10bf720 .param/l "i" 0 4 54, +C4<010>; +L_0x1298a50/d .functor AND 1, L_0x1298b10, L_0x1298c70, C4<1>, C4<1>; +L_0x1298a50 .delay 1 (30000,30000,30000) L_0x1298a50/d; +v0x10bf7c0_0 .net *"_s0", 0 0, L_0x1298b10; 1 drivers +v0x10bf8a0_0 .net *"_s1", 0 0, L_0x1298c70; 1 drivers +S_0x10bf980 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10bfb90 .param/l "i" 0 4 54, +C4<011>; +L_0x1298d60/d .functor AND 1, L_0x1298e20, L_0x1298f80, C4<1>, C4<1>; +L_0x1298d60 .delay 1 (30000,30000,30000) L_0x1298d60/d; +v0x10bfc50_0 .net *"_s0", 0 0, L_0x1298e20; 1 drivers +v0x10bfd30_0 .net *"_s1", 0 0, L_0x1298f80; 1 drivers +S_0x10bfe10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10c0070 .param/l "i" 0 4 54, +C4<0100>; +L_0x12990c0/d .functor AND 1, L_0x1299180, L_0x12993f0, C4<1>, C4<1>; +L_0x12990c0 .delay 1 (30000,30000,30000) L_0x12990c0/d; +v0x10c0130_0 .net *"_s0", 0 0, L_0x1299180; 1 drivers +v0x10c0210_0 .net *"_s1", 0 0, L_0x12993f0; 1 drivers +S_0x10c02f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10c0500 .param/l "i" 0 4 54, +C4<0101>; +L_0x12994f0/d .functor AND 1, L_0x1299560, L_0x12996c0, C4<1>, C4<1>; +L_0x12994f0 .delay 1 (30000,30000,30000) L_0x12994f0/d; +v0x10c05c0_0 .net *"_s0", 0 0, L_0x1299560; 1 drivers +v0x10c06a0_0 .net *"_s1", 0 0, L_0x12996c0; 1 drivers +S_0x10c0780 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10c0990 .param/l "i" 0 4 54, +C4<0110>; +L_0x1299820/d .functor AND 1, L_0x12998e0, L_0x1299a40, C4<1>, C4<1>; +L_0x1299820 .delay 1 (30000,30000,30000) L_0x1299820/d; +v0x10c0a50_0 .net *"_s0", 0 0, L_0x12998e0; 1 drivers +v0x10c0b30_0 .net *"_s1", 0 0, L_0x1299a40; 1 drivers +S_0x10c0c10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10be960; + .timescale -9 -12; +P_0x10c0e20 .param/l "i" 0 4 54, +C4<0111>; +L_0x12997b0/d .functor AND 1, L_0x1299f70, L_0x129a160, C4<1>, C4<1>; +L_0x12997b0 .delay 1 (30000,30000,30000) L_0x12997b0/d; +v0x10c0ee0_0 .net *"_s0", 0 0, L_0x1299f70; 1 drivers +v0x10c0fc0_0 .net *"_s1", 0 0, L_0x129a160; 1 drivers +S_0x10c1b80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10be710; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e08440/d .functor OR 1, L_0x1e08500, L_0x1e086b0, C4<0>, C4<0>; -L_0x1e08440 .delay 1 (30000,30000,30000) L_0x1e08440/d; -v0x1c30a50_0 .net *"_s10", 0 0, L_0x1e08500; 1 drivers -v0x1c30b30_0 .net *"_s12", 0 0, L_0x1e086b0; 1 drivers -v0x1c30c10_0 .net "in", 7 0, L_0x1e06440; alias, 1 drivers -v0x1c30ce0_0 .net "ors", 1 0, L_0x1e08260; 1 drivers -v0x1c30da0_0 .net "out", 0 0, L_0x1e08440; alias, 1 drivers -L_0x1e07630 .part L_0x1e06440, 0, 4; -L_0x1e08260 .concat8 [ 1 1 0 0], L_0x1e07320, L_0x1e07f50; -L_0x1e083a0 .part L_0x1e06440, 4, 4; -L_0x1e08500 .part L_0x1e08260, 0, 1; -L_0x1e086b0 .part L_0x1e08260, 1, 1; -S_0x1c2f0c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c2ef00; +L_0x129bbb0/d .functor OR 1, L_0x129bc70, L_0x129be20, C4<0>, C4<0>; +L_0x129bbb0 .delay 1 (30000,30000,30000) L_0x129bbb0/d; +v0x10c36d0_0 .net *"_s10", 0 0, L_0x129bc70; 1 drivers +v0x10c37b0_0 .net *"_s12", 0 0, L_0x129be20; 1 drivers +v0x10c3890_0 .net "in", 7 0, L_0x1299bb0; alias, 1 drivers +v0x10c3960_0 .net "ors", 1 0, L_0x129b9d0; 1 drivers +v0x10c3a20_0 .net "out", 0 0, L_0x129bbb0; alias, 1 drivers +L_0x129ada0 .part L_0x1299bb0, 0, 4; +L_0x129b9d0 .concat8 [ 1 1 0 0], L_0x129aa90, L_0x129b6c0; +L_0x129bb10 .part L_0x1299bb0, 4, 4; +L_0x129bc70 .part L_0x129b9d0, 0, 1; +L_0x129be20 .part L_0x129b9d0, 1, 1; +S_0x10c1d40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10c1b80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e06ae0/d .functor OR 1, L_0x1e06ba0, L_0x1e06d00, C4<0>, C4<0>; -L_0x1e06ae0 .delay 1 (30000,30000,30000) L_0x1e06ae0/d; -L_0x1e06f30/d .functor OR 1, L_0x1e07040, L_0x1e071a0, C4<0>, C4<0>; -L_0x1e06f30 .delay 1 (30000,30000,30000) L_0x1e06f30/d; -L_0x1e07320/d .functor OR 1, L_0x1e07390, L_0x1e07540, C4<0>, C4<0>; -L_0x1e07320 .delay 1 (30000,30000,30000) L_0x1e07320/d; -v0x1c2f310_0 .net *"_s0", 0 0, L_0x1e06ae0; 1 drivers -v0x1c2f410_0 .net *"_s10", 0 0, L_0x1e07040; 1 drivers -v0x1c2f4f0_0 .net *"_s12", 0 0, L_0x1e071a0; 1 drivers -v0x1c2f5b0_0 .net *"_s14", 0 0, L_0x1e07390; 1 drivers -v0x1c2f690_0 .net *"_s16", 0 0, L_0x1e07540; 1 drivers -v0x1c2f7c0_0 .net *"_s3", 0 0, L_0x1e06ba0; 1 drivers -v0x1c2f8a0_0 .net *"_s5", 0 0, L_0x1e06d00; 1 drivers -v0x1c2f980_0 .net *"_s6", 0 0, L_0x1e06f30; 1 drivers -v0x1c2fa60_0 .net "in", 3 0, L_0x1e07630; 1 drivers -v0x1c2fbd0_0 .net "ors", 1 0, L_0x1e06e40; 1 drivers -v0x1c2fcb0_0 .net "out", 0 0, L_0x1e07320; 1 drivers -L_0x1e06ba0 .part L_0x1e07630, 0, 1; -L_0x1e06d00 .part L_0x1e07630, 1, 1; -L_0x1e06e40 .concat8 [ 1 1 0 0], L_0x1e06ae0, L_0x1e06f30; -L_0x1e07040 .part L_0x1e07630, 2, 1; -L_0x1e071a0 .part L_0x1e07630, 3, 1; -L_0x1e07390 .part L_0x1e06e40, 0, 1; -L_0x1e07540 .part L_0x1e06e40, 1, 1; -S_0x1c2fdd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c2ef00; +L_0x129a250/d .functor OR 1, L_0x129a310, L_0x129a470, C4<0>, C4<0>; +L_0x129a250 .delay 1 (30000,30000,30000) L_0x129a250/d; +L_0x129a6a0/d .functor OR 1, L_0x129a7b0, L_0x129a910, C4<0>, C4<0>; +L_0x129a6a0 .delay 1 (30000,30000,30000) L_0x129a6a0/d; +L_0x129aa90/d .functor OR 1, L_0x129ab00, L_0x129acb0, C4<0>, C4<0>; +L_0x129aa90 .delay 1 (30000,30000,30000) L_0x129aa90/d; +v0x10c1f90_0 .net *"_s0", 0 0, L_0x129a250; 1 drivers +v0x10c2090_0 .net *"_s10", 0 0, L_0x129a7b0; 1 drivers +v0x10c2170_0 .net *"_s12", 0 0, L_0x129a910; 1 drivers +v0x10c2230_0 .net *"_s14", 0 0, L_0x129ab00; 1 drivers +v0x10c2310_0 .net *"_s16", 0 0, L_0x129acb0; 1 drivers +v0x10c2440_0 .net *"_s3", 0 0, L_0x129a310; 1 drivers +v0x10c2520_0 .net *"_s5", 0 0, L_0x129a470; 1 drivers +v0x10c2600_0 .net *"_s6", 0 0, L_0x129a6a0; 1 drivers +v0x10c26e0_0 .net "in", 3 0, L_0x129ada0; 1 drivers +v0x10c2850_0 .net "ors", 1 0, L_0x129a5b0; 1 drivers +v0x10c2930_0 .net "out", 0 0, L_0x129aa90; 1 drivers +L_0x129a310 .part L_0x129ada0, 0, 1; +L_0x129a470 .part L_0x129ada0, 1, 1; +L_0x129a5b0 .concat8 [ 1 1 0 0], L_0x129a250, L_0x129a6a0; +L_0x129a7b0 .part L_0x129ada0, 2, 1; +L_0x129a910 .part L_0x129ada0, 3, 1; +L_0x129ab00 .part L_0x129a5b0, 0, 1; +L_0x129acb0 .part L_0x129a5b0, 1, 1; +S_0x10c2a50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10c1b80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e07760/d .functor OR 1, L_0x1e077d0, L_0x1e07930, C4<0>, C4<0>; -L_0x1e07760 .delay 1 (30000,30000,30000) L_0x1e07760/d; -L_0x1e07b60/d .functor OR 1, L_0x1e07c70, L_0x1e07dd0, C4<0>, C4<0>; -L_0x1e07b60 .delay 1 (30000,30000,30000) L_0x1e07b60/d; -L_0x1e07f50/d .functor OR 1, L_0x1e07fc0, L_0x1e08170, C4<0>, C4<0>; -L_0x1e07f50 .delay 1 (30000,30000,30000) L_0x1e07f50/d; -v0x1c2ff90_0 .net *"_s0", 0 0, L_0x1e07760; 1 drivers -v0x1c30090_0 .net *"_s10", 0 0, L_0x1e07c70; 1 drivers -v0x1c30170_0 .net *"_s12", 0 0, L_0x1e07dd0; 1 drivers -v0x1c30230_0 .net *"_s14", 0 0, L_0x1e07fc0; 1 drivers -v0x1c30310_0 .net *"_s16", 0 0, L_0x1e08170; 1 drivers -v0x1c30440_0 .net *"_s3", 0 0, L_0x1e077d0; 1 drivers -v0x1c30520_0 .net *"_s5", 0 0, L_0x1e07930; 1 drivers -v0x1c30600_0 .net *"_s6", 0 0, L_0x1e07b60; 1 drivers -v0x1c306e0_0 .net "in", 3 0, L_0x1e083a0; 1 drivers -v0x1c30850_0 .net "ors", 1 0, L_0x1e07a70; 1 drivers -v0x1c30930_0 .net "out", 0 0, L_0x1e07f50; 1 drivers -L_0x1e077d0 .part L_0x1e083a0, 0, 1; -L_0x1e07930 .part L_0x1e083a0, 1, 1; -L_0x1e07a70 .concat8 [ 1 1 0 0], L_0x1e07760, L_0x1e07b60; -L_0x1e07c70 .part L_0x1e083a0, 2, 1; -L_0x1e07dd0 .part L_0x1e083a0, 3, 1; -L_0x1e07fc0 .part L_0x1e07a70, 0, 1; -L_0x1e08170 .part L_0x1e07a70, 1, 1; -S_0x1c31240 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c24bc0; +L_0x129aed0/d .functor OR 1, L_0x129af40, L_0x129b0a0, C4<0>, C4<0>; +L_0x129aed0 .delay 1 (30000,30000,30000) L_0x129aed0/d; +L_0x129b2d0/d .functor OR 1, L_0x129b3e0, L_0x129b540, C4<0>, C4<0>; +L_0x129b2d0 .delay 1 (30000,30000,30000) L_0x129b2d0/d; +L_0x129b6c0/d .functor OR 1, L_0x129b730, L_0x129b8e0, C4<0>, C4<0>; +L_0x129b6c0 .delay 1 (30000,30000,30000) L_0x129b6c0/d; +v0x10c2c10_0 .net *"_s0", 0 0, L_0x129aed0; 1 drivers +v0x10c2d10_0 .net *"_s10", 0 0, L_0x129b3e0; 1 drivers +v0x10c2df0_0 .net *"_s12", 0 0, L_0x129b540; 1 drivers +v0x10c2eb0_0 .net *"_s14", 0 0, L_0x129b730; 1 drivers +v0x10c2f90_0 .net *"_s16", 0 0, L_0x129b8e0; 1 drivers +v0x10c30c0_0 .net *"_s3", 0 0, L_0x129af40; 1 drivers +v0x10c31a0_0 .net *"_s5", 0 0, L_0x129b0a0; 1 drivers +v0x10c3280_0 .net *"_s6", 0 0, L_0x129b2d0; 1 drivers +v0x10c3360_0 .net "in", 3 0, L_0x129bb10; 1 drivers +v0x10c34d0_0 .net "ors", 1 0, L_0x129b1e0; 1 drivers +v0x10c35b0_0 .net "out", 0 0, L_0x129b6c0; 1 drivers +L_0x129af40 .part L_0x129bb10, 0, 1; +L_0x129b0a0 .part L_0x129bb10, 1, 1; +L_0x129b1e0 .concat8 [ 1 1 0 0], L_0x129aed0, L_0x129b2d0; +L_0x129b3e0 .part L_0x129bb10, 2, 1; +L_0x129b540 .part L_0x129bb10, 3, 1; +L_0x129b730 .part L_0x129b1e0, 0, 1; +L_0x129b8e0 .part L_0x129b1e0, 1, 1; +S_0x10c3ec0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10b7840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -8620,80 +8630,80 @@ S_0x1c31240 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c24bc0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e03c10/d .functor XNOR 1, L_0x1e0c2e0, L_0x1e02a50, C4<0>, C4<0>; -L_0x1e03c10 .delay 1 (20000,20000,20000) L_0x1e03c10/d; -L_0x1e03e80/d .functor AND 1, L_0x1e0c2e0, L_0x1e02c10, C4<1>, C4<1>; -L_0x1e03e80 .delay 1 (30000,30000,30000) L_0x1e03e80/d; -L_0x1e03ef0/d .functor AND 1, L_0x1e03c10, L_0x1e02af0, C4<1>, C4<1>; -L_0x1e03ef0 .delay 1 (30000,30000,30000) L_0x1e03ef0/d; -L_0x1e04050/d .functor OR 1, L_0x1e03ef0, L_0x1e03e80, C4<0>, C4<0>; -L_0x1e04050 .delay 1 (30000,30000,30000) L_0x1e04050/d; -v0x1c314f0_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers -v0x1c315e0_0 .net "a_", 0 0, L_0x1df8aa0; alias, 1 drivers -v0x1c316a0_0 .net "b", 0 0, L_0x1e02a50; alias, 1 drivers -v0x1c31790_0 .net "b_", 0 0, L_0x1e02c10; alias, 1 drivers -v0x1c31830_0 .net "carryin", 0 0, L_0x1e02af0; alias, 1 drivers -v0x1c31970_0 .net "eq", 0 0, L_0x1e03c10; 1 drivers -v0x1c31a30_0 .net "lt", 0 0, L_0x1e03e80; 1 drivers -v0x1c31af0_0 .net "out", 0 0, L_0x1e04050; 1 drivers -v0x1c31bb0_0 .net "w0", 0 0, L_0x1e03ef0; 1 drivers -S_0x1c31e00 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c24bc0; +L_0x1297380/d .functor XNOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; +L_0x1297380 .delay 1 (20000,20000,20000) L_0x1297380/d; +L_0x12975f0/d .functor AND 1, L_0x129fa50, L_0x12962c0, C4<1>, C4<1>; +L_0x12975f0 .delay 1 (30000,30000,30000) L_0x12975f0/d; +L_0x1297660/d .functor AND 1, L_0x1297380, L_0x12961a0, C4<1>, C4<1>; +L_0x1297660 .delay 1 (30000,30000,30000) L_0x1297660/d; +L_0x12977c0/d .functor OR 1, L_0x1297660, L_0x12975f0, C4<0>, C4<0>; +L_0x12977c0 .delay 1 (30000,30000,30000) L_0x12977c0/d; +v0x10c4170_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers +v0x10c4260_0 .net "a_", 0 0, L_0x128c1e0; alias, 1 drivers +v0x10c4320_0 .net "b", 0 0, L_0x1296100; alias, 1 drivers +v0x10c4410_0 .net "b_", 0 0, L_0x12962c0; alias, 1 drivers +v0x10c44b0_0 .net "carryin", 0 0, L_0x12961a0; alias, 1 drivers +v0x10c45f0_0 .net "eq", 0 0, L_0x1297380; 1 drivers +v0x10c46b0_0 .net "lt", 0 0, L_0x12975f0; 1 drivers +v0x10c4770_0 .net "out", 0 0, L_0x12977c0; 1 drivers +v0x10c4830_0 .net "w0", 0 0, L_0x1297660; 1 drivers +S_0x10c4a80 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10b7840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e039f0/d .functor OR 1, L_0x1e03540, L_0x1c33060, C4<0>, C4<0>; -L_0x1e039f0 .delay 1 (30000,30000,30000) L_0x1e039f0/d; -v0x1c32bf0_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers -v0x1c32d40_0 .net "b", 0 0, L_0x1e02c10; alias, 1 drivers -v0x1c32e00_0 .net "c1", 0 0, L_0x1e03540; 1 drivers -v0x1c32ea0_0 .net "c2", 0 0, L_0x1c33060; 1 drivers -v0x1c32f70_0 .net "carryin", 0 0, L_0x1e02af0; alias, 1 drivers -v0x1c330f0_0 .net "carryout", 0 0, L_0x1e039f0; 1 drivers -v0x1c33190_0 .net "s1", 0 0, L_0x1e03480; 1 drivers -v0x1c33230_0 .net "sum", 0 0, L_0x1e036a0; 1 drivers -S_0x1c32050 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c31e00; +L_0x1297160/d .functor OR 1, L_0x1296cb0, L_0x10c5ce0, C4<0>, C4<0>; +L_0x1297160 .delay 1 (30000,30000,30000) L_0x1297160/d; +v0x10c5870_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers +v0x10c59c0_0 .net "b", 0 0, L_0x12962c0; alias, 1 drivers +v0x10c5a80_0 .net "c1", 0 0, L_0x1296cb0; 1 drivers +v0x10c5b20_0 .net "c2", 0 0, L_0x10c5ce0; 1 drivers +v0x10c5bf0_0 .net "carryin", 0 0, L_0x12961a0; alias, 1 drivers +v0x10c5d70_0 .net "carryout", 0 0, L_0x1297160; 1 drivers +v0x10c5e10_0 .net "s1", 0 0, L_0x1296bf0; 1 drivers +v0x10c5eb0_0 .net "sum", 0 0, L_0x1296e10; 1 drivers +S_0x10c4cd0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10c4a80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e03480/d .functor XOR 1, L_0x1e0c2e0, L_0x1e02c10, C4<0>, C4<0>; -L_0x1e03480 .delay 1 (30000,30000,30000) L_0x1e03480/d; -L_0x1e03540/d .functor AND 1, L_0x1e0c2e0, L_0x1e02c10, C4<1>, C4<1>; -L_0x1e03540 .delay 1 (30000,30000,30000) L_0x1e03540/d; -v0x1c322b0_0 .net "a", 0 0, L_0x1e0c2e0; alias, 1 drivers -v0x1c32370_0 .net "b", 0 0, L_0x1e02c10; alias, 1 drivers -v0x1c32430_0 .net "carryout", 0 0, L_0x1e03540; alias, 1 drivers -v0x1c324d0_0 .net "sum", 0 0, L_0x1e03480; alias, 1 drivers -S_0x1c32600 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c31e00; +L_0x1296bf0/d .functor XOR 1, L_0x129fa50, L_0x12962c0, C4<0>, C4<0>; +L_0x1296bf0 .delay 1 (30000,30000,30000) L_0x1296bf0/d; +L_0x1296cb0/d .functor AND 1, L_0x129fa50, L_0x12962c0, C4<1>, C4<1>; +L_0x1296cb0 .delay 1 (30000,30000,30000) L_0x1296cb0/d; +v0x10c4f30_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers +v0x10c4ff0_0 .net "b", 0 0, L_0x12962c0; alias, 1 drivers +v0x10c50b0_0 .net "carryout", 0 0, L_0x1296cb0; alias, 1 drivers +v0x10c5150_0 .net "sum", 0 0, L_0x1296bf0; alias, 1 drivers +S_0x10c5280 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10c4a80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e036a0/d .functor XOR 1, L_0x1e03480, L_0x1e02af0, C4<0>, C4<0>; -L_0x1e036a0 .delay 1 (30000,30000,30000) L_0x1e036a0/d; -L_0x1c33060/d .functor AND 1, L_0x1e03480, L_0x1e02af0, C4<1>, C4<1>; -L_0x1c33060 .delay 1 (30000,30000,30000) L_0x1c33060/d; -v0x1c32860_0 .net "a", 0 0, L_0x1e03480; alias, 1 drivers -v0x1c32930_0 .net "b", 0 0, L_0x1e02af0; alias, 1 drivers -v0x1c329d0_0 .net "carryout", 0 0, L_0x1c33060; alias, 1 drivers -v0x1c32aa0_0 .net "sum", 0 0, L_0x1e036a0; alias, 1 drivers -S_0x1c34650 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c248f0; - .timescale -9 -12; -L_0x7f72592db0f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e0c380/d .functor OR 1, L_0x7f72592db0f8, L_0x7f72592db140, C4<0>, C4<0>; -L_0x1e0c380 .delay 1 (30000,30000,30000) L_0x1e0c380/d; -v0x1c34840_0 .net/2u *"_s0", 0 0, L_0x7f72592db0f8; 1 drivers -v0x1c34920_0 .net/2u *"_s2", 0 0, L_0x7f72592db140; 1 drivers -S_0x1c34a00 .scope generate, "alu_slices[16]" "alu_slices[16]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1bb3f20 .param/l "i" 0 3 37, +C4<010000>; -S_0x1c34d70 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c34a00; +L_0x1296e10/d .functor XOR 1, L_0x1296bf0, L_0x12961a0, C4<0>, C4<0>; +L_0x1296e10 .delay 1 (30000,30000,30000) L_0x1296e10/d; +L_0x10c5ce0/d .functor AND 1, L_0x1296bf0, L_0x12961a0, C4<1>, C4<1>; +L_0x10c5ce0 .delay 1 (30000,30000,30000) L_0x10c5ce0/d; +v0x10c54e0_0 .net "a", 0 0, L_0x1296bf0; alias, 1 drivers +v0x10c55b0_0 .net "b", 0 0, L_0x12961a0; alias, 1 drivers +v0x10c5650_0 .net "carryout", 0 0, L_0x10c5ce0; alias, 1 drivers +v0x10c5720_0 .net "sum", 0 0, L_0x1296e10; alias, 1 drivers +S_0x10c7270 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10b7570; + .timescale -9 -12; +L_0x2b0ab3d060f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x129faf0/d .functor OR 1, L_0x2b0ab3d060f8, L_0x2b0ab3d06140, C4<0>, C4<0>; +L_0x129faf0 .delay 1 (30000,30000,30000) L_0x129faf0/d; +v0x10c7460_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d060f8; 1 drivers +v0x10c7540_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06140; 1 drivers +S_0x10c7620 .scope generate, "alu_slices[16]" "alu_slices[16]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1046ba0 .param/l "i" 0 3 41, +C4<010000>; +S_0x10c7990 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10c7620; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -8702,445 +8712,445 @@ S_0x1c34d70 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c34a00; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e0c440/d .functor NOT 1, L_0x1e16060, C4<0>, C4<0>, C4<0>; -L_0x1e0c440 .delay 1 (10000,10000,10000) L_0x1e0c440/d; -L_0x1e0c960/d .functor NOT 1, L_0x1e161c0, C4<0>, C4<0>, C4<0>; -L_0x1e0c960 .delay 1 (10000,10000,10000) L_0x1e0c960/d; -L_0x1e0d9b0/d .functor XOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; -L_0x1e0d9b0 .delay 1 (30000,30000,30000) L_0x1e0d9b0/d; -L_0x7f72592db188 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db1d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e0e060/d .functor OR 1, L_0x7f72592db188, L_0x7f72592db1d0, C4<0>, C4<0>; -L_0x1e0e060 .delay 1 (30000,30000,30000) L_0x1e0e060/d; -L_0x1e0e260/d .functor AND 1, L_0x1e16060, L_0x1e161c0, C4<1>, C4<1>; -L_0x1e0e260 .delay 1 (30000,30000,30000) L_0x1e0e260/d; -L_0x1e0e320/d .functor NAND 1, L_0x1e16060, L_0x1e161c0, C4<1>, C4<1>; -L_0x1e0e320 .delay 1 (20000,20000,20000) L_0x1e0e320/d; -L_0x1e0e480/d .functor XOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; -L_0x1e0e480 .delay 1 (20000,20000,20000) L_0x1e0e480/d; -L_0x1e0e930/d .functor OR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; -L_0x1e0e930 .delay 1 (30000,30000,30000) L_0x1e0e930/d; -L_0x1e15f60/d .functor NOT 1, L_0x1e121c0, C4<0>, C4<0>, C4<0>; -L_0x1e15f60 .delay 1 (10000,10000,10000) L_0x1e15f60/d; -v0x1c43480_0 .net "A", 0 0, L_0x1e16060; 1 drivers -v0x1c43540_0 .net "A_", 0 0, L_0x1e0c440; 1 drivers -v0x1c43600_0 .net "B", 0 0, L_0x1e161c0; 1 drivers -v0x1c436d0_0 .net "B_", 0 0, L_0x1e0c960; 1 drivers -v0x1c43770_0 .net *"_s12", 0 0, L_0x1e0e060; 1 drivers -v0x1c43860_0 .net/2s *"_s14", 0 0, L_0x7f72592db188; 1 drivers -v0x1c43920_0 .net/2s *"_s16", 0 0, L_0x7f72592db1d0; 1 drivers -v0x1c43a00_0 .net *"_s18", 0 0, L_0x1e0e260; 1 drivers -v0x1c43ae0_0 .net *"_s20", 0 0, L_0x1e0e320; 1 drivers -v0x1c43c50_0 .net *"_s22", 0 0, L_0x1e0e480; 1 drivers -v0x1c43d30_0 .net *"_s24", 0 0, L_0x1e0e930; 1 drivers -o0x7f725937b7c8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c43e10_0 name=_s30 -o0x7f725937b7f8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c43ef0_0 name=_s32 -v0x1c43fd0_0 .net *"_s8", 0 0, L_0x1e0d9b0; 1 drivers -v0x1c440b0_0 .net "carryin", 0 0, L_0x1e0c7d0; 1 drivers -v0x1c44150_0 .net "carryout", 0 0, L_0x1e15c00; 1 drivers -v0x1c441f0_0 .net "carryouts", 7 0, L_0x1ec05f0; 1 drivers -v0x1c443a0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c44440_0 .net "result", 0 0, L_0x1e121c0; 1 drivers -v0x1c44530_0 .net "results", 7 0, L_0x1e0e700; 1 drivers -v0x1c44640_0 .net "zero", 0 0, L_0x1e15f60; 1 drivers -LS_0x1e0e700_0_0 .concat8 [ 1 1 1 1], L_0x1e0ce80, L_0x1e0d4b0, L_0x1e0d9b0, L_0x1e0e060; -LS_0x1e0e700_0_4 .concat8 [ 1 1 1 1], L_0x1e0e260, L_0x1e0e320, L_0x1e0e480, L_0x1e0e930; -L_0x1e0e700 .concat8 [ 4 4 0 0], LS_0x1e0e700_0_0, LS_0x1e0e700_0_4; -LS_0x1ec05f0_0_0 .concat [ 1 1 1 1], L_0x1e0d130, L_0x1e0d850, o0x7f725937b7c8, L_0x1e0deb0; -LS_0x1ec05f0_0_4 .concat [ 4 0 0 0], o0x7f725937b7f8; -L_0x1ec05f0 .concat [ 4 4 0 0], LS_0x1ec05f0_0_0, LS_0x1ec05f0_0_4; -S_0x1c34ff0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c34d70; +L_0x129fbb0/d .functor NOT 1, L_0x12a97d0, C4<0>, C4<0>, C4<0>; +L_0x129fbb0 .delay 1 (10000,10000,10000) L_0x129fbb0/d; +L_0x12a00d0/d .functor NOT 1, L_0x12a9930, C4<0>, C4<0>, C4<0>; +L_0x12a00d0 .delay 1 (10000,10000,10000) L_0x12a00d0/d; +L_0x12a1010/d .functor XOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; +L_0x12a1010 .delay 1 (30000,30000,30000) L_0x12a1010/d; +L_0x2b0ab3d06188 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d061d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a16c0/d .functor OR 1, L_0x2b0ab3d06188, L_0x2b0ab3d061d0, C4<0>, C4<0>; +L_0x12a16c0 .delay 1 (30000,30000,30000) L_0x12a16c0/d; +L_0x12a18c0/d .functor AND 1, L_0x12a97d0, L_0x12a9930, C4<1>, C4<1>; +L_0x12a18c0 .delay 1 (30000,30000,30000) L_0x12a18c0/d; +L_0x12a1980/d .functor NAND 1, L_0x12a97d0, L_0x12a9930, C4<1>, C4<1>; +L_0x12a1980 .delay 1 (20000,20000,20000) L_0x12a1980/d; +L_0x12a1ae0/d .functor XOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; +L_0x12a1ae0 .delay 1 (20000,20000,20000) L_0x12a1ae0/d; +L_0x12a1f90/d .functor OR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; +L_0x12a1f90 .delay 1 (30000,30000,30000) L_0x12a1f90/d; +L_0x12a96d0/d .functor NOT 1, L_0x12a5900, C4<0>, C4<0>, C4<0>; +L_0x12a96d0 .delay 1 (10000,10000,10000) L_0x12a96d0/d; +v0x10d6130_0 .net "A", 0 0, L_0x12a97d0; 1 drivers +v0x10d61f0_0 .net "A_", 0 0, L_0x129fbb0; 1 drivers +v0x10d62b0_0 .net "B", 0 0, L_0x12a9930; 1 drivers +v0x10d6380_0 .net "B_", 0 0, L_0x12a00d0; 1 drivers +v0x10d6420_0 .net *"_s12", 0 0, L_0x12a16c0; 1 drivers +v0x10d6510_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06188; 1 drivers +v0x10d65d0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d061d0; 1 drivers +v0x10d66b0_0 .net *"_s18", 0 0, L_0x12a18c0; 1 drivers +v0x10d6790_0 .net *"_s20", 0 0, L_0x12a1980; 1 drivers +v0x10d6900_0 .net *"_s22", 0 0, L_0x12a1ae0; 1 drivers +v0x10d69e0_0 .net *"_s24", 0 0, L_0x12a1f90; 1 drivers +o0x2b0ab3cca7c8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10d6ac0_0 name=_s30 +o0x2b0ab3cca7f8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10d6ba0_0 name=_s32 +v0x10d6c80_0 .net *"_s8", 0 0, L_0x12a1010; 1 drivers +v0x10d6d60_0 .net "carryin", 0 0, L_0x129ff40; 1 drivers +v0x10d6e00_0 .net "carryout", 0 0, L_0x12a9370; 1 drivers +v0x10d6ea0_0 .net "carryouts", 7 0, L_0x1354920; 1 drivers +v0x10d7050_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10d70f0_0 .net "result", 0 0, L_0x12a5900; 1 drivers +v0x10d71e0_0 .net "results", 7 0, L_0x12a1d60; 1 drivers +v0x10d72f0_0 .net "zero", 0 0, L_0x12a96d0; 1 drivers +LS_0x12a1d60_0_0 .concat8 [ 1 1 1 1], L_0x12a0530, L_0x12a0b60, L_0x12a1010, L_0x12a16c0; +LS_0x12a1d60_0_4 .concat8 [ 1 1 1 1], L_0x12a18c0, L_0x12a1980, L_0x12a1ae0, L_0x12a1f90; +L_0x12a1d60 .concat8 [ 4 4 0 0], LS_0x12a1d60_0_0, LS_0x12a1d60_0_4; +LS_0x1354920_0_0 .concat [ 1 1 1 1], L_0x12a07e0, L_0x12a0eb0, o0x2b0ab3cca7c8, L_0x12a1510; +LS_0x1354920_0_4 .concat [ 4 0 0 0], o0x2b0ab3cca7f8; +L_0x1354920 .concat [ 4 4 0 0], LS_0x1354920_0_0, LS_0x1354920_0_4; +S_0x10c7c10 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10c7990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e0d130/d .functor OR 1, L_0x1e0cc10, L_0x1e0cfd0, C4<0>, C4<0>; -L_0x1e0d130 .delay 1 (30000,30000,30000) L_0x1e0d130/d; -v0x1c35e00_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers -v0x1c35ec0_0 .net "b", 0 0, L_0x1e161c0; alias, 1 drivers -v0x1c35f90_0 .net "c1", 0 0, L_0x1e0cc10; 1 drivers -v0x1c36090_0 .net "c2", 0 0, L_0x1e0cfd0; 1 drivers -v0x1c36160_0 .net "carryin", 0 0, L_0x1e0c7d0; alias, 1 drivers -v0x1c36250_0 .net "carryout", 0 0, L_0x1e0d130; 1 drivers -v0x1c362f0_0 .net "s1", 0 0, L_0x1e0cb50; 1 drivers -v0x1c363e0_0 .net "sum", 0 0, L_0x1e0ce80; 1 drivers -S_0x1c35240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c34ff0; +L_0x12a07e0/d .functor OR 1, L_0x12a02c0, L_0x12a0680, C4<0>, C4<0>; +L_0x12a07e0 .delay 1 (30000,30000,30000) L_0x12a07e0/d; +v0x10c8ab0_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers +v0x10c8b70_0 .net "b", 0 0, L_0x12a9930; alias, 1 drivers +v0x10c8c40_0 .net "c1", 0 0, L_0x12a02c0; 1 drivers +v0x10c8d40_0 .net "c2", 0 0, L_0x12a0680; 1 drivers +v0x10c8e10_0 .net "carryin", 0 0, L_0x129ff40; alias, 1 drivers +v0x10c8f00_0 .net "carryout", 0 0, L_0x12a07e0; 1 drivers +v0x10c8fa0_0 .net "s1", 0 0, L_0x1299b30; 1 drivers +v0x10c9090_0 .net "sum", 0 0, L_0x12a0530; 1 drivers +S_0x10c7e60 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10c7c10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e0cb50/d .functor XOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; -L_0x1e0cb50 .delay 1 (30000,30000,30000) L_0x1e0cb50/d; -L_0x1e0cc10/d .functor AND 1, L_0x1e16060, L_0x1e161c0, C4<1>, C4<1>; -L_0x1e0cc10 .delay 1 (30000,30000,30000) L_0x1e0cc10/d; -v0x1c354a0_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers -v0x1c35580_0 .net "b", 0 0, L_0x1e161c0; alias, 1 drivers -v0x1c35640_0 .net "carryout", 0 0, L_0x1e0cc10; alias, 1 drivers -v0x1c356e0_0 .net "sum", 0 0, L_0x1e0cb50; alias, 1 drivers -S_0x1c35820 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c34ff0; +L_0x1299b30/d .functor XOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; +L_0x1299b30 .delay 1 (30000,30000,30000) L_0x1299b30/d; +L_0x12a02c0/d .functor AND 1, L_0x12a97d0, L_0x12a9930, C4<1>, C4<1>; +L_0x12a02c0 .delay 1 (30000,30000,30000) L_0x12a02c0/d; +v0x10c80c0_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers +v0x10c81a0_0 .net "b", 0 0, L_0x12a9930; alias, 1 drivers +v0x10c8260_0 .net "carryout", 0 0, L_0x12a02c0; alias, 1 drivers +v0x10c8330_0 .net "sum", 0 0, L_0x1299b30; alias, 1 drivers +S_0x10c84a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10c7c10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e0ce80/d .functor XOR 1, L_0x1e0cb50, L_0x1e0c7d0, C4<0>, C4<0>; -L_0x1e0ce80 .delay 1 (30000,30000,30000) L_0x1e0ce80/d; -L_0x1e0cfd0/d .functor AND 1, L_0x1e0cb50, L_0x1e0c7d0, C4<1>, C4<1>; -L_0x1e0cfd0 .delay 1 (30000,30000,30000) L_0x1e0cfd0/d; -v0x1c35a80_0 .net "a", 0 0, L_0x1e0cb50; alias, 1 drivers -v0x1c35b20_0 .net "b", 0 0, L_0x1e0c7d0; alias, 1 drivers -v0x1c35bc0_0 .net "carryout", 0 0, L_0x1e0cfd0; alias, 1 drivers -v0x1c35c90_0 .net "sum", 0 0, L_0x1e0ce80; alias, 1 drivers -S_0x1c364b0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c34d70; +L_0x12a0530/d .functor XOR 1, L_0x1299b30, L_0x129ff40, C4<0>, C4<0>; +L_0x12a0530 .delay 1 (30000,30000,30000) L_0x12a0530/d; +L_0x12a0680/d .functor AND 1, L_0x1299b30, L_0x129ff40, C4<1>, C4<1>; +L_0x12a0680 .delay 1 (30000,30000,30000) L_0x12a0680/d; +v0x10c8700_0 .net "a", 0 0, L_0x1299b30; alias, 1 drivers +v0x10c87d0_0 .net "b", 0 0, L_0x129ff40; alias, 1 drivers +v0x10c8870_0 .net "carryout", 0 0, L_0x12a0680; alias, 1 drivers +v0x10c8940_0 .net "sum", 0 0, L_0x12a0530; alias, 1 drivers +S_0x10c9160 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10c7990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c3b8a0_0 .net "ands", 7 0, L_0x1e13c00; 1 drivers -v0x1c3b9b0_0 .net "in", 7 0, L_0x1ec05f0; alias, 1 drivers -v0x1c3ba70_0 .net "out", 0 0, L_0x1e15c00; alias, 1 drivers -v0x1c3bb40_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c366d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c364b0; +v0x10ce550_0 .net "ands", 7 0, L_0x12a7370; 1 drivers +v0x10ce660_0 .net "in", 7 0, L_0x1354920; alias, 1 drivers +v0x10ce720_0 .net "out", 0 0, L_0x12a9370; alias, 1 drivers +v0x10ce7f0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10c9380 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10c9160; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c38e00_0 .net "A", 7 0, L_0x1ec05f0; alias, 1 drivers -v0x1c38f00_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c38fc0_0 .net *"_s0", 0 0, L_0x1e12520; 1 drivers -v0x1c39080_0 .net *"_s12", 0 0, L_0x1e12e90; 1 drivers -v0x1c39160_0 .net *"_s16", 0 0, L_0x1e131f0; 1 drivers -v0x1c39290_0 .net *"_s20", 0 0, L_0x1e13500; 1 drivers -v0x1c39370_0 .net *"_s24", 0 0, L_0x1e138f0; 1 drivers -v0x1c39450_0 .net *"_s28", 0 0, L_0x1e13880; 1 drivers -v0x1c39530_0 .net *"_s4", 0 0, L_0x1e12830; 1 drivers -v0x1c396a0_0 .net *"_s8", 0 0, L_0x1e12b80; 1 drivers -v0x1c39780_0 .net "out", 7 0, L_0x1e13c00; alias, 1 drivers -L_0x1e125e0 .part L_0x1ec05f0, 0, 1; -L_0x1e12740 .part v0x1d6daa0_0, 0, 1; -L_0x1e128f0 .part L_0x1ec05f0, 1, 1; -L_0x1e12ae0 .part v0x1d6daa0_0, 1, 1; -L_0x1e12c40 .part L_0x1ec05f0, 2, 1; -L_0x1e12da0 .part v0x1d6daa0_0, 2, 1; -L_0x1e12f50 .part L_0x1ec05f0, 3, 1; -L_0x1e130b0 .part v0x1d6daa0_0, 3, 1; -L_0x1e132b0 .part L_0x1ec05f0, 4, 1; -L_0x1e13410 .part v0x1d6daa0_0, 4, 1; -L_0x1e13570 .part L_0x1ec05f0, 5, 1; -L_0x1e137e0 .part v0x1d6daa0_0, 5, 1; -L_0x1e139b0 .part L_0x1ec05f0, 6, 1; -L_0x1e13b10 .part v0x1d6daa0_0, 6, 1; -LS_0x1e13c00_0_0 .concat8 [ 1 1 1 1], L_0x1e12520, L_0x1e12830, L_0x1e12b80, L_0x1e12e90; -LS_0x1e13c00_0_4 .concat8 [ 1 1 1 1], L_0x1e131f0, L_0x1e13500, L_0x1e138f0, L_0x1e13880; -L_0x1e13c00 .concat8 [ 4 4 0 0], LS_0x1e13c00_0_0, LS_0x1e13c00_0_4; -L_0x1e13fc0 .part L_0x1ec05f0, 7, 1; -L_0x1e141b0 .part v0x1d6daa0_0, 7, 1; -S_0x1c36930 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c36b40 .param/l "i" 0 4 54, +C4<00>; -L_0x1e12520/d .functor AND 1, L_0x1e125e0, L_0x1e12740, C4<1>, C4<1>; -L_0x1e12520 .delay 1 (30000,30000,30000) L_0x1e12520/d; -v0x1c36c20_0 .net *"_s0", 0 0, L_0x1e125e0; 1 drivers -v0x1c36d00_0 .net *"_s1", 0 0, L_0x1e12740; 1 drivers -S_0x1c36de0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c36ff0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e12830/d .functor AND 1, L_0x1e128f0, L_0x1e12ae0, C4<1>, C4<1>; -L_0x1e12830 .delay 1 (30000,30000,30000) L_0x1e12830/d; -v0x1c370b0_0 .net *"_s0", 0 0, L_0x1e128f0; 1 drivers -v0x1c37190_0 .net *"_s1", 0 0, L_0x1e12ae0; 1 drivers -S_0x1c37270 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c37480 .param/l "i" 0 4 54, +C4<010>; -L_0x1e12b80/d .functor AND 1, L_0x1e12c40, L_0x1e12da0, C4<1>, C4<1>; -L_0x1e12b80 .delay 1 (30000,30000,30000) L_0x1e12b80/d; -v0x1c37520_0 .net *"_s0", 0 0, L_0x1e12c40; 1 drivers -v0x1c37600_0 .net *"_s1", 0 0, L_0x1e12da0; 1 drivers -S_0x1c376e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c378f0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e12e90/d .functor AND 1, L_0x1e12f50, L_0x1e130b0, C4<1>, C4<1>; -L_0x1e12e90 .delay 1 (30000,30000,30000) L_0x1e12e90/d; -v0x1c379b0_0 .net *"_s0", 0 0, L_0x1e12f50; 1 drivers -v0x1c37a90_0 .net *"_s1", 0 0, L_0x1e130b0; 1 drivers -S_0x1c37b70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c37dd0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e131f0/d .functor AND 1, L_0x1e132b0, L_0x1e13410, C4<1>, C4<1>; -L_0x1e131f0 .delay 1 (30000,30000,30000) L_0x1e131f0/d; -v0x1c37e90_0 .net *"_s0", 0 0, L_0x1e132b0; 1 drivers -v0x1c37f70_0 .net *"_s1", 0 0, L_0x1e13410; 1 drivers -S_0x1c38050 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c38260 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e13500/d .functor AND 1, L_0x1e13570, L_0x1e137e0, C4<1>, C4<1>; -L_0x1e13500 .delay 1 (30000,30000,30000) L_0x1e13500/d; -v0x1c38320_0 .net *"_s0", 0 0, L_0x1e13570; 1 drivers -v0x1c38400_0 .net *"_s1", 0 0, L_0x1e137e0; 1 drivers -S_0x1c384e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c386f0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e138f0/d .functor AND 1, L_0x1e139b0, L_0x1e13b10, C4<1>, C4<1>; -L_0x1e138f0 .delay 1 (30000,30000,30000) L_0x1e138f0/d; -v0x1c387b0_0 .net *"_s0", 0 0, L_0x1e139b0; 1 drivers -v0x1c38890_0 .net *"_s1", 0 0, L_0x1e13b10; 1 drivers -S_0x1c38970 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c366d0; - .timescale -9 -12; -P_0x1c38b80 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e13880/d .functor AND 1, L_0x1e13fc0, L_0x1e141b0, C4<1>, C4<1>; -L_0x1e13880 .delay 1 (30000,30000,30000) L_0x1e13880/d; -v0x1c38c40_0 .net *"_s0", 0 0, L_0x1e13fc0; 1 drivers -v0x1c38d20_0 .net *"_s1", 0 0, L_0x1e141b0; 1 drivers -S_0x1c398e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c364b0; +v0x10cbab0_0 .net "A", 7 0, L_0x1354920; alias, 1 drivers +v0x10cbbb0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10cbc70_0 .net *"_s0", 0 0, L_0x12a5c60; 1 drivers +v0x10cbd30_0 .net *"_s12", 0 0, L_0x12a65d0; 1 drivers +v0x10cbe10_0 .net *"_s16", 0 0, L_0x12a6930; 1 drivers +v0x10cbf40_0 .net *"_s20", 0 0, L_0x12a6c40; 1 drivers +v0x10cc020_0 .net *"_s24", 0 0, L_0x12a7030; 1 drivers +v0x10cc100_0 .net *"_s28", 0 0, L_0x12a6fc0; 1 drivers +v0x10cc1e0_0 .net *"_s4", 0 0, L_0x12a5f70; 1 drivers +v0x10cc350_0 .net *"_s8", 0 0, L_0x12a62c0; 1 drivers +v0x10cc430_0 .net "out", 7 0, L_0x12a7370; alias, 1 drivers +L_0x12a5d20 .part L_0x1354920, 0, 1; +L_0x12a5e80 .part v0x12010b0_0, 0, 1; +L_0x12a6030 .part L_0x1354920, 1, 1; +L_0x12a6220 .part v0x12010b0_0, 1, 1; +L_0x12a6380 .part L_0x1354920, 2, 1; +L_0x12a64e0 .part v0x12010b0_0, 2, 1; +L_0x12a6690 .part L_0x1354920, 3, 1; +L_0x12a67f0 .part v0x12010b0_0, 3, 1; +L_0x12a69f0 .part L_0x1354920, 4, 1; +L_0x12a6b50 .part v0x12010b0_0, 4, 1; +L_0x12a6cb0 .part L_0x1354920, 5, 1; +L_0x12a6f20 .part v0x12010b0_0, 5, 1; +L_0x12a7120 .part L_0x1354920, 6, 1; +L_0x12a7280 .part v0x12010b0_0, 6, 1; +LS_0x12a7370_0_0 .concat8 [ 1 1 1 1], L_0x12a5c60, L_0x12a5f70, L_0x12a62c0, L_0x12a65d0; +LS_0x12a7370_0_4 .concat8 [ 1 1 1 1], L_0x12a6930, L_0x12a6c40, L_0x12a7030, L_0x12a6fc0; +L_0x12a7370 .concat8 [ 4 4 0 0], LS_0x12a7370_0_0, LS_0x12a7370_0_4; +L_0x12a7730 .part L_0x1354920, 7, 1; +L_0x12a7920 .part v0x12010b0_0, 7, 1; +S_0x10c95e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10c97f0 .param/l "i" 0 4 54, +C4<00>; +L_0x12a5c60/d .functor AND 1, L_0x12a5d20, L_0x12a5e80, C4<1>, C4<1>; +L_0x12a5c60 .delay 1 (30000,30000,30000) L_0x12a5c60/d; +v0x10c98d0_0 .net *"_s0", 0 0, L_0x12a5d20; 1 drivers +v0x10c99b0_0 .net *"_s1", 0 0, L_0x12a5e80; 1 drivers +S_0x10c9a90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10c9ca0 .param/l "i" 0 4 54, +C4<01>; +L_0x12a5f70/d .functor AND 1, L_0x12a6030, L_0x12a6220, C4<1>, C4<1>; +L_0x12a5f70 .delay 1 (30000,30000,30000) L_0x12a5f70/d; +v0x10c9d60_0 .net *"_s0", 0 0, L_0x12a6030; 1 drivers +v0x10c9e40_0 .net *"_s1", 0 0, L_0x12a6220; 1 drivers +S_0x10c9f20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10ca130 .param/l "i" 0 4 54, +C4<010>; +L_0x12a62c0/d .functor AND 1, L_0x12a6380, L_0x12a64e0, C4<1>, C4<1>; +L_0x12a62c0 .delay 1 (30000,30000,30000) L_0x12a62c0/d; +v0x10ca1d0_0 .net *"_s0", 0 0, L_0x12a6380; 1 drivers +v0x10ca2b0_0 .net *"_s1", 0 0, L_0x12a64e0; 1 drivers +S_0x10ca390 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10ca5a0 .param/l "i" 0 4 54, +C4<011>; +L_0x12a65d0/d .functor AND 1, L_0x12a6690, L_0x12a67f0, C4<1>, C4<1>; +L_0x12a65d0 .delay 1 (30000,30000,30000) L_0x12a65d0/d; +v0x10ca660_0 .net *"_s0", 0 0, L_0x12a6690; 1 drivers +v0x10ca740_0 .net *"_s1", 0 0, L_0x12a67f0; 1 drivers +S_0x10ca820 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10caa80 .param/l "i" 0 4 54, +C4<0100>; +L_0x12a6930/d .functor AND 1, L_0x12a69f0, L_0x12a6b50, C4<1>, C4<1>; +L_0x12a6930 .delay 1 (30000,30000,30000) L_0x12a6930/d; +v0x10cab40_0 .net *"_s0", 0 0, L_0x12a69f0; 1 drivers +v0x10cac20_0 .net *"_s1", 0 0, L_0x12a6b50; 1 drivers +S_0x10cad00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10caf10 .param/l "i" 0 4 54, +C4<0101>; +L_0x12a6c40/d .functor AND 1, L_0x12a6cb0, L_0x12a6f20, C4<1>, C4<1>; +L_0x12a6c40 .delay 1 (30000,30000,30000) L_0x12a6c40/d; +v0x10cafd0_0 .net *"_s0", 0 0, L_0x12a6cb0; 1 drivers +v0x10cb0b0_0 .net *"_s1", 0 0, L_0x12a6f20; 1 drivers +S_0x10cb190 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10cb3a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12a7030/d .functor AND 1, L_0x12a7120, L_0x12a7280, C4<1>, C4<1>; +L_0x12a7030 .delay 1 (30000,30000,30000) L_0x12a7030/d; +v0x10cb460_0 .net *"_s0", 0 0, L_0x12a7120; 1 drivers +v0x10cb540_0 .net *"_s1", 0 0, L_0x12a7280; 1 drivers +S_0x10cb620 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10c9380; + .timescale -9 -12; +P_0x10cb830 .param/l "i" 0 4 54, +C4<0111>; +L_0x12a6fc0/d .functor AND 1, L_0x12a7730, L_0x12a7920, C4<1>, C4<1>; +L_0x12a6fc0 .delay 1 (30000,30000,30000) L_0x12a6fc0/d; +v0x10cb8f0_0 .net *"_s0", 0 0, L_0x12a7730; 1 drivers +v0x10cb9d0_0 .net *"_s1", 0 0, L_0x12a7920; 1 drivers +S_0x10cc590 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10c9160; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e15c00/d .functor OR 1, L_0x1e15cc0, L_0x1e15e70, C4<0>, C4<0>; -L_0x1e15c00 .delay 1 (30000,30000,30000) L_0x1e15c00/d; -v0x1c3b430_0 .net *"_s10", 0 0, L_0x1e15cc0; 1 drivers -v0x1c3b510_0 .net *"_s12", 0 0, L_0x1e15e70; 1 drivers -v0x1c3b5f0_0 .net "in", 7 0, L_0x1e13c00; alias, 1 drivers -v0x1c3b6c0_0 .net "ors", 1 0, L_0x1e15a20; 1 drivers -v0x1c3b780_0 .net "out", 0 0, L_0x1e15c00; alias, 1 drivers -L_0x1e14df0 .part L_0x1e13c00, 0, 4; -L_0x1e15a20 .concat8 [ 1 1 0 0], L_0x1e14ae0, L_0x1e15710; -L_0x1e15b60 .part L_0x1e13c00, 4, 4; -L_0x1e15cc0 .part L_0x1e15a20, 0, 1; -L_0x1e15e70 .part L_0x1e15a20, 1, 1; -S_0x1c39aa0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c398e0; +L_0x12a9370/d .functor OR 1, L_0x12a9430, L_0x12a95e0, C4<0>, C4<0>; +L_0x12a9370 .delay 1 (30000,30000,30000) L_0x12a9370/d; +v0x10ce0e0_0 .net *"_s10", 0 0, L_0x12a9430; 1 drivers +v0x10ce1c0_0 .net *"_s12", 0 0, L_0x12a95e0; 1 drivers +v0x10ce2a0_0 .net "in", 7 0, L_0x12a7370; alias, 1 drivers +v0x10ce370_0 .net "ors", 1 0, L_0x12a9190; 1 drivers +v0x10ce430_0 .net "out", 0 0, L_0x12a9370; alias, 1 drivers +L_0x12a8560 .part L_0x12a7370, 0, 4; +L_0x12a9190 .concat8 [ 1 1 0 0], L_0x12a8250, L_0x12a8e80; +L_0x12a92d0 .part L_0x12a7370, 4, 4; +L_0x12a9430 .part L_0x12a9190, 0, 1; +L_0x12a95e0 .part L_0x12a9190, 1, 1; +S_0x10cc750 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10cc590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e142a0/d .functor OR 1, L_0x1e14360, L_0x1e144c0, C4<0>, C4<0>; -L_0x1e142a0 .delay 1 (30000,30000,30000) L_0x1e142a0/d; -L_0x1e146f0/d .functor OR 1, L_0x1e14800, L_0x1e14960, C4<0>, C4<0>; -L_0x1e146f0 .delay 1 (30000,30000,30000) L_0x1e146f0/d; -L_0x1e14ae0/d .functor OR 1, L_0x1e14b50, L_0x1e14d00, C4<0>, C4<0>; -L_0x1e14ae0 .delay 1 (30000,30000,30000) L_0x1e14ae0/d; -v0x1c39cf0_0 .net *"_s0", 0 0, L_0x1e142a0; 1 drivers -v0x1c39df0_0 .net *"_s10", 0 0, L_0x1e14800; 1 drivers -v0x1c39ed0_0 .net *"_s12", 0 0, L_0x1e14960; 1 drivers -v0x1c39f90_0 .net *"_s14", 0 0, L_0x1e14b50; 1 drivers -v0x1c3a070_0 .net *"_s16", 0 0, L_0x1e14d00; 1 drivers -v0x1c3a1a0_0 .net *"_s3", 0 0, L_0x1e14360; 1 drivers -v0x1c3a280_0 .net *"_s5", 0 0, L_0x1e144c0; 1 drivers -v0x1c3a360_0 .net *"_s6", 0 0, L_0x1e146f0; 1 drivers -v0x1c3a440_0 .net "in", 3 0, L_0x1e14df0; 1 drivers -v0x1c3a5b0_0 .net "ors", 1 0, L_0x1e14600; 1 drivers -v0x1c3a690_0 .net "out", 0 0, L_0x1e14ae0; 1 drivers -L_0x1e14360 .part L_0x1e14df0, 0, 1; -L_0x1e144c0 .part L_0x1e14df0, 1, 1; -L_0x1e14600 .concat8 [ 1 1 0 0], L_0x1e142a0, L_0x1e146f0; -L_0x1e14800 .part L_0x1e14df0, 2, 1; -L_0x1e14960 .part L_0x1e14df0, 3, 1; -L_0x1e14b50 .part L_0x1e14600, 0, 1; -L_0x1e14d00 .part L_0x1e14600, 1, 1; -S_0x1c3a7b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c398e0; +L_0x12a7a10/d .functor OR 1, L_0x12a7ad0, L_0x12a7c30, C4<0>, C4<0>; +L_0x12a7a10 .delay 1 (30000,30000,30000) L_0x12a7a10/d; +L_0x12a7e60/d .functor OR 1, L_0x12a7f70, L_0x12a80d0, C4<0>, C4<0>; +L_0x12a7e60 .delay 1 (30000,30000,30000) L_0x12a7e60/d; +L_0x12a8250/d .functor OR 1, L_0x12a82c0, L_0x12a8470, C4<0>, C4<0>; +L_0x12a8250 .delay 1 (30000,30000,30000) L_0x12a8250/d; +v0x10cc9a0_0 .net *"_s0", 0 0, L_0x12a7a10; 1 drivers +v0x10ccaa0_0 .net *"_s10", 0 0, L_0x12a7f70; 1 drivers +v0x10ccb80_0 .net *"_s12", 0 0, L_0x12a80d0; 1 drivers +v0x10ccc40_0 .net *"_s14", 0 0, L_0x12a82c0; 1 drivers +v0x10ccd20_0 .net *"_s16", 0 0, L_0x12a8470; 1 drivers +v0x10cce50_0 .net *"_s3", 0 0, L_0x12a7ad0; 1 drivers +v0x10ccf30_0 .net *"_s5", 0 0, L_0x12a7c30; 1 drivers +v0x10cd010_0 .net *"_s6", 0 0, L_0x12a7e60; 1 drivers +v0x10cd0f0_0 .net "in", 3 0, L_0x12a8560; 1 drivers +v0x10cd260_0 .net "ors", 1 0, L_0x12a7d70; 1 drivers +v0x10cd340_0 .net "out", 0 0, L_0x12a8250; 1 drivers +L_0x12a7ad0 .part L_0x12a8560, 0, 1; +L_0x12a7c30 .part L_0x12a8560, 1, 1; +L_0x12a7d70 .concat8 [ 1 1 0 0], L_0x12a7a10, L_0x12a7e60; +L_0x12a7f70 .part L_0x12a8560, 2, 1; +L_0x12a80d0 .part L_0x12a8560, 3, 1; +L_0x12a82c0 .part L_0x12a7d70, 0, 1; +L_0x12a8470 .part L_0x12a7d70, 1, 1; +S_0x10cd460 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10cc590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e14f20/d .functor OR 1, L_0x1e14f90, L_0x1e150f0, C4<0>, C4<0>; -L_0x1e14f20 .delay 1 (30000,30000,30000) L_0x1e14f20/d; -L_0x1e15320/d .functor OR 1, L_0x1e15430, L_0x1e15590, C4<0>, C4<0>; -L_0x1e15320 .delay 1 (30000,30000,30000) L_0x1e15320/d; -L_0x1e15710/d .functor OR 1, L_0x1e15780, L_0x1e15930, C4<0>, C4<0>; -L_0x1e15710 .delay 1 (30000,30000,30000) L_0x1e15710/d; -v0x1c3a970_0 .net *"_s0", 0 0, L_0x1e14f20; 1 drivers -v0x1c3aa70_0 .net *"_s10", 0 0, L_0x1e15430; 1 drivers -v0x1c3ab50_0 .net *"_s12", 0 0, L_0x1e15590; 1 drivers -v0x1c3ac10_0 .net *"_s14", 0 0, L_0x1e15780; 1 drivers -v0x1c3acf0_0 .net *"_s16", 0 0, L_0x1e15930; 1 drivers -v0x1c3ae20_0 .net *"_s3", 0 0, L_0x1e14f90; 1 drivers -v0x1c3af00_0 .net *"_s5", 0 0, L_0x1e150f0; 1 drivers -v0x1c3afe0_0 .net *"_s6", 0 0, L_0x1e15320; 1 drivers -v0x1c3b0c0_0 .net "in", 3 0, L_0x1e15b60; 1 drivers -v0x1c3b230_0 .net "ors", 1 0, L_0x1e15230; 1 drivers -v0x1c3b310_0 .net "out", 0 0, L_0x1e15710; 1 drivers -L_0x1e14f90 .part L_0x1e15b60, 0, 1; -L_0x1e150f0 .part L_0x1e15b60, 1, 1; -L_0x1e15230 .concat8 [ 1 1 0 0], L_0x1e14f20, L_0x1e15320; -L_0x1e15430 .part L_0x1e15b60, 2, 1; -L_0x1e15590 .part L_0x1e15b60, 3, 1; -L_0x1e15780 .part L_0x1e15230, 0, 1; -L_0x1e15930 .part L_0x1e15230, 1, 1; -S_0x1c3bc20 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c34d70; +L_0x12a8690/d .functor OR 1, L_0x12a8700, L_0x12a8860, C4<0>, C4<0>; +L_0x12a8690 .delay 1 (30000,30000,30000) L_0x12a8690/d; +L_0x12a8a90/d .functor OR 1, L_0x12a8ba0, L_0x12a8d00, C4<0>, C4<0>; +L_0x12a8a90 .delay 1 (30000,30000,30000) L_0x12a8a90/d; +L_0x12a8e80/d .functor OR 1, L_0x12a8ef0, L_0x12a90a0, C4<0>, C4<0>; +L_0x12a8e80 .delay 1 (30000,30000,30000) L_0x12a8e80/d; +v0x10cd620_0 .net *"_s0", 0 0, L_0x12a8690; 1 drivers +v0x10cd720_0 .net *"_s10", 0 0, L_0x12a8ba0; 1 drivers +v0x10cd800_0 .net *"_s12", 0 0, L_0x12a8d00; 1 drivers +v0x10cd8c0_0 .net *"_s14", 0 0, L_0x12a8ef0; 1 drivers +v0x10cd9a0_0 .net *"_s16", 0 0, L_0x12a90a0; 1 drivers +v0x10cdad0_0 .net *"_s3", 0 0, L_0x12a8700; 1 drivers +v0x10cdbb0_0 .net *"_s5", 0 0, L_0x12a8860; 1 drivers +v0x10cdc90_0 .net *"_s6", 0 0, L_0x12a8a90; 1 drivers +v0x10cdd70_0 .net "in", 3 0, L_0x12a92d0; 1 drivers +v0x10cdee0_0 .net "ors", 1 0, L_0x12a89a0; 1 drivers +v0x10cdfc0_0 .net "out", 0 0, L_0x12a8e80; 1 drivers +L_0x12a8700 .part L_0x12a92d0, 0, 1; +L_0x12a8860 .part L_0x12a92d0, 1, 1; +L_0x12a89a0 .concat8 [ 1 1 0 0], L_0x12a8690, L_0x12a8a90; +L_0x12a8ba0 .part L_0x12a92d0, 2, 1; +L_0x12a8d00 .part L_0x12a92d0, 3, 1; +L_0x12a8ef0 .part L_0x12a89a0, 0, 1; +L_0x12a90a0 .part L_0x12a89a0, 1, 1; +S_0x10ce8d0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10c7990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c41050_0 .net "ands", 7 0, L_0x1e101c0; 1 drivers -v0x1c41160_0 .net "in", 7 0, L_0x1e0e700; alias, 1 drivers -v0x1c41220_0 .net "out", 0 0, L_0x1e121c0; alias, 1 drivers -v0x1c412f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c3be70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c3bc20; +v0x10d3d00_0 .net "ands", 7 0, L_0x12a3900; 1 drivers +v0x10d3e10_0 .net "in", 7 0, L_0x12a1d60; alias, 1 drivers +v0x10d3ed0_0 .net "out", 0 0, L_0x12a5900; alias, 1 drivers +v0x10d3fa0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10ceb20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10ce8d0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c3e5b0_0 .net "A", 7 0, L_0x1e0e700; alias, 1 drivers -v0x1c3e6b0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c3e770_0 .net *"_s0", 0 0, L_0x1e0ea90; 1 drivers -v0x1c3e830_0 .net *"_s12", 0 0, L_0x1e0f450; 1 drivers -v0x1c3e910_0 .net *"_s16", 0 0, L_0x1e0f7b0; 1 drivers -v0x1c3ea40_0 .net *"_s20", 0 0, L_0x1e0fb80; 1 drivers -v0x1c3eb20_0 .net *"_s24", 0 0, L_0x1e0feb0; 1 drivers -v0x1c3ec00_0 .net *"_s28", 0 0, L_0x1e0fe40; 1 drivers -v0x1c3ece0_0 .net *"_s4", 0 0, L_0x1e0ee30; 1 drivers -v0x1c3ee50_0 .net *"_s8", 0 0, L_0x1e0f140; 1 drivers -v0x1c3ef30_0 .net "out", 7 0, L_0x1e101c0; alias, 1 drivers -L_0x1e0eba0 .part L_0x1e0e700, 0, 1; -L_0x1e0ed90 .part v0x1d6daa0_0, 0, 1; -L_0x1e0eef0 .part L_0x1e0e700, 1, 1; -L_0x1e0f050 .part v0x1d6daa0_0, 1, 1; -L_0x1e0f200 .part L_0x1e0e700, 2, 1; -L_0x1e0f360 .part v0x1d6daa0_0, 2, 1; -L_0x1e0f510 .part L_0x1e0e700, 3, 1; -L_0x1e0f670 .part v0x1d6daa0_0, 3, 1; -L_0x1e0f870 .part L_0x1e0e700, 4, 1; -L_0x1e0fae0 .part v0x1d6daa0_0, 4, 1; -L_0x1e0fbf0 .part L_0x1e0e700, 5, 1; -L_0x1e0fd50 .part v0x1d6daa0_0, 5, 1; -L_0x1e0ff70 .part L_0x1e0e700, 6, 1; -L_0x1e100d0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e101c0_0_0 .concat8 [ 1 1 1 1], L_0x1e0ea90, L_0x1e0ee30, L_0x1e0f140, L_0x1e0f450; -LS_0x1e101c0_0_4 .concat8 [ 1 1 1 1], L_0x1e0f7b0, L_0x1e0fb80, L_0x1e0feb0, L_0x1e0fe40; -L_0x1e101c0 .concat8 [ 4 4 0 0], LS_0x1e101c0_0_0, LS_0x1e101c0_0_4; -L_0x1e10580 .part L_0x1e0e700, 7, 1; -L_0x1e10770 .part v0x1d6daa0_0, 7, 1; -S_0x1c3c0b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3c2c0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e0ea90/d .functor AND 1, L_0x1e0eba0, L_0x1e0ed90, C4<1>, C4<1>; -L_0x1e0ea90 .delay 1 (30000,30000,30000) L_0x1e0ea90/d; -v0x1c3c3a0_0 .net *"_s0", 0 0, L_0x1e0eba0; 1 drivers -v0x1c3c480_0 .net *"_s1", 0 0, L_0x1e0ed90; 1 drivers -S_0x1c3c560 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3c770 .param/l "i" 0 4 54, +C4<01>; -L_0x1e0ee30/d .functor AND 1, L_0x1e0eef0, L_0x1e0f050, C4<1>, C4<1>; -L_0x1e0ee30 .delay 1 (30000,30000,30000) L_0x1e0ee30/d; -v0x1c3c830_0 .net *"_s0", 0 0, L_0x1e0eef0; 1 drivers -v0x1c3c910_0 .net *"_s1", 0 0, L_0x1e0f050; 1 drivers -S_0x1c3c9f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3cc30 .param/l "i" 0 4 54, +C4<010>; -L_0x1e0f140/d .functor AND 1, L_0x1e0f200, L_0x1e0f360, C4<1>, C4<1>; -L_0x1e0f140 .delay 1 (30000,30000,30000) L_0x1e0f140/d; -v0x1c3ccd0_0 .net *"_s0", 0 0, L_0x1e0f200; 1 drivers -v0x1c3cdb0_0 .net *"_s1", 0 0, L_0x1e0f360; 1 drivers -S_0x1c3ce90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3d0a0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e0f450/d .functor AND 1, L_0x1e0f510, L_0x1e0f670, C4<1>, C4<1>; -L_0x1e0f450 .delay 1 (30000,30000,30000) L_0x1e0f450/d; -v0x1c3d160_0 .net *"_s0", 0 0, L_0x1e0f510; 1 drivers -v0x1c3d240_0 .net *"_s1", 0 0, L_0x1e0f670; 1 drivers -S_0x1c3d320 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3d580 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e0f7b0/d .functor AND 1, L_0x1e0f870, L_0x1e0fae0, C4<1>, C4<1>; -L_0x1e0f7b0 .delay 1 (30000,30000,30000) L_0x1e0f7b0/d; -v0x1c3d640_0 .net *"_s0", 0 0, L_0x1e0f870; 1 drivers -v0x1c3d720_0 .net *"_s1", 0 0, L_0x1e0fae0; 1 drivers -S_0x1c3d800 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3da10 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e0fb80/d .functor AND 1, L_0x1e0fbf0, L_0x1e0fd50, C4<1>, C4<1>; -L_0x1e0fb80 .delay 1 (30000,30000,30000) L_0x1e0fb80/d; -v0x1c3dad0_0 .net *"_s0", 0 0, L_0x1e0fbf0; 1 drivers -v0x1c3dbb0_0 .net *"_s1", 0 0, L_0x1e0fd50; 1 drivers -S_0x1c3dc90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3dea0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e0feb0/d .functor AND 1, L_0x1e0ff70, L_0x1e100d0, C4<1>, C4<1>; -L_0x1e0feb0 .delay 1 (30000,30000,30000) L_0x1e0feb0/d; -v0x1c3df60_0 .net *"_s0", 0 0, L_0x1e0ff70; 1 drivers -v0x1c3e040_0 .net *"_s1", 0 0, L_0x1e100d0; 1 drivers -S_0x1c3e120 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c3be70; - .timescale -9 -12; -P_0x1c3e330 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e0fe40/d .functor AND 1, L_0x1e10580, L_0x1e10770, C4<1>, C4<1>; -L_0x1e0fe40 .delay 1 (30000,30000,30000) L_0x1e0fe40/d; -v0x1c3e3f0_0 .net *"_s0", 0 0, L_0x1e10580; 1 drivers -v0x1c3e4d0_0 .net *"_s1", 0 0, L_0x1e10770; 1 drivers -S_0x1c3f090 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c3bc20; +v0x10d1260_0 .net "A", 7 0, L_0x12a1d60; alias, 1 drivers +v0x10d1360_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10d1420_0 .net *"_s0", 0 0, L_0x12a20f0; 1 drivers +v0x10d14e0_0 .net *"_s12", 0 0, L_0x12a2ab0; 1 drivers +v0x10d15c0_0 .net *"_s16", 0 0, L_0x12a2e10; 1 drivers +v0x10d16f0_0 .net *"_s20", 0 0, L_0x12a3240; 1 drivers +v0x10d17d0_0 .net *"_s24", 0 0, L_0x12a3570; 1 drivers +v0x10d18b0_0 .net *"_s28", 0 0, L_0x12a3500; 1 drivers +v0x10d1990_0 .net *"_s4", 0 0, L_0x12a2490; 1 drivers +v0x10d1b00_0 .net *"_s8", 0 0, L_0x12a27a0; 1 drivers +v0x10d1be0_0 .net "out", 7 0, L_0x12a3900; alias, 1 drivers +L_0x12a2200 .part L_0x12a1d60, 0, 1; +L_0x12a23f0 .part v0x12010b0_0, 0, 1; +L_0x12a2550 .part L_0x12a1d60, 1, 1; +L_0x12a26b0 .part v0x12010b0_0, 1, 1; +L_0x12a2860 .part L_0x12a1d60, 2, 1; +L_0x12a29c0 .part v0x12010b0_0, 2, 1; +L_0x12a2b70 .part L_0x12a1d60, 3, 1; +L_0x12a2cd0 .part v0x12010b0_0, 3, 1; +L_0x12a2ed0 .part L_0x12a1d60, 4, 1; +L_0x12a3140 .part v0x12010b0_0, 4, 1; +L_0x12a32b0 .part L_0x12a1d60, 5, 1; +L_0x12a3410 .part v0x12010b0_0, 5, 1; +L_0x12a3630 .part L_0x12a1d60, 6, 1; +L_0x12a3790 .part v0x12010b0_0, 6, 1; +LS_0x12a3900_0_0 .concat8 [ 1 1 1 1], L_0x12a20f0, L_0x12a2490, L_0x12a27a0, L_0x12a2ab0; +LS_0x12a3900_0_4 .concat8 [ 1 1 1 1], L_0x12a2e10, L_0x12a3240, L_0x12a3570, L_0x12a3500; +L_0x12a3900 .concat8 [ 4 4 0 0], LS_0x12a3900_0_0, LS_0x12a3900_0_4; +L_0x12a3cc0 .part L_0x12a1d60, 7, 1; +L_0x12a3eb0 .part v0x12010b0_0, 7, 1; +S_0x10ced60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10cef70 .param/l "i" 0 4 54, +C4<00>; +L_0x12a20f0/d .functor AND 1, L_0x12a2200, L_0x12a23f0, C4<1>, C4<1>; +L_0x12a20f0 .delay 1 (30000,30000,30000) L_0x12a20f0/d; +v0x10cf050_0 .net *"_s0", 0 0, L_0x12a2200; 1 drivers +v0x10cf130_0 .net *"_s1", 0 0, L_0x12a23f0; 1 drivers +S_0x10cf210 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10cf420 .param/l "i" 0 4 54, +C4<01>; +L_0x12a2490/d .functor AND 1, L_0x12a2550, L_0x12a26b0, C4<1>, C4<1>; +L_0x12a2490 .delay 1 (30000,30000,30000) L_0x12a2490/d; +v0x10cf4e0_0 .net *"_s0", 0 0, L_0x12a2550; 1 drivers +v0x10cf5c0_0 .net *"_s1", 0 0, L_0x12a26b0; 1 drivers +S_0x10cf6a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10cf8e0 .param/l "i" 0 4 54, +C4<010>; +L_0x12a27a0/d .functor AND 1, L_0x12a2860, L_0x12a29c0, C4<1>, C4<1>; +L_0x12a27a0 .delay 1 (30000,30000,30000) L_0x12a27a0/d; +v0x10cf980_0 .net *"_s0", 0 0, L_0x12a2860; 1 drivers +v0x10cfa60_0 .net *"_s1", 0 0, L_0x12a29c0; 1 drivers +S_0x10cfb40 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10cfd50 .param/l "i" 0 4 54, +C4<011>; +L_0x12a2ab0/d .functor AND 1, L_0x12a2b70, L_0x12a2cd0, C4<1>, C4<1>; +L_0x12a2ab0 .delay 1 (30000,30000,30000) L_0x12a2ab0/d; +v0x10cfe10_0 .net *"_s0", 0 0, L_0x12a2b70; 1 drivers +v0x10cfef0_0 .net *"_s1", 0 0, L_0x12a2cd0; 1 drivers +S_0x10cffd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10d0230 .param/l "i" 0 4 54, +C4<0100>; +L_0x12a2e10/d .functor AND 1, L_0x12a2ed0, L_0x12a3140, C4<1>, C4<1>; +L_0x12a2e10 .delay 1 (30000,30000,30000) L_0x12a2e10/d; +v0x10d02f0_0 .net *"_s0", 0 0, L_0x12a2ed0; 1 drivers +v0x10d03d0_0 .net *"_s1", 0 0, L_0x12a3140; 1 drivers +S_0x10d04b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10d06c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12a3240/d .functor AND 1, L_0x12a32b0, L_0x12a3410, C4<1>, C4<1>; +L_0x12a3240 .delay 1 (30000,30000,30000) L_0x12a3240/d; +v0x10d0780_0 .net *"_s0", 0 0, L_0x12a32b0; 1 drivers +v0x10d0860_0 .net *"_s1", 0 0, L_0x12a3410; 1 drivers +S_0x10d0940 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10d0b50 .param/l "i" 0 4 54, +C4<0110>; +L_0x12a3570/d .functor AND 1, L_0x12a3630, L_0x12a3790, C4<1>, C4<1>; +L_0x12a3570 .delay 1 (30000,30000,30000) L_0x12a3570/d; +v0x10d0c10_0 .net *"_s0", 0 0, L_0x12a3630; 1 drivers +v0x10d0cf0_0 .net *"_s1", 0 0, L_0x12a3790; 1 drivers +S_0x10d0dd0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10ceb20; + .timescale -9 -12; +P_0x10d0fe0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12a3500/d .functor AND 1, L_0x12a3cc0, L_0x12a3eb0, C4<1>, C4<1>; +L_0x12a3500 .delay 1 (30000,30000,30000) L_0x12a3500/d; +v0x10d10a0_0 .net *"_s0", 0 0, L_0x12a3cc0; 1 drivers +v0x10d1180_0 .net *"_s1", 0 0, L_0x12a3eb0; 1 drivers +S_0x10d1d40 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10ce8d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e121c0/d .functor OR 1, L_0x1e12280, L_0x1e12430, C4<0>, C4<0>; -L_0x1e121c0 .delay 1 (30000,30000,30000) L_0x1e121c0/d; -v0x1c40be0_0 .net *"_s10", 0 0, L_0x1e12280; 1 drivers -v0x1c40cc0_0 .net *"_s12", 0 0, L_0x1e12430; 1 drivers -v0x1c40da0_0 .net "in", 7 0, L_0x1e101c0; alias, 1 drivers -v0x1c40e70_0 .net "ors", 1 0, L_0x1e11fe0; 1 drivers -v0x1c40f30_0 .net "out", 0 0, L_0x1e121c0; alias, 1 drivers -L_0x1e113b0 .part L_0x1e101c0, 0, 4; -L_0x1e11fe0 .concat8 [ 1 1 0 0], L_0x1e110a0, L_0x1e11cd0; -L_0x1e12120 .part L_0x1e101c0, 4, 4; -L_0x1e12280 .part L_0x1e11fe0, 0, 1; -L_0x1e12430 .part L_0x1e11fe0, 1, 1; -S_0x1c3f250 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c3f090; +L_0x12a5900/d .functor OR 1, L_0x12a59c0, L_0x12a5b70, C4<0>, C4<0>; +L_0x12a5900 .delay 1 (30000,30000,30000) L_0x12a5900/d; +v0x10d3890_0 .net *"_s10", 0 0, L_0x12a59c0; 1 drivers +v0x10d3970_0 .net *"_s12", 0 0, L_0x12a5b70; 1 drivers +v0x10d3a50_0 .net "in", 7 0, L_0x12a3900; alias, 1 drivers +v0x10d3b20_0 .net "ors", 1 0, L_0x12a5720; 1 drivers +v0x10d3be0_0 .net "out", 0 0, L_0x12a5900; alias, 1 drivers +L_0x12a4af0 .part L_0x12a3900, 0, 4; +L_0x12a5720 .concat8 [ 1 1 0 0], L_0x12a47e0, L_0x12a5410; +L_0x12a5860 .part L_0x12a3900, 4, 4; +L_0x12a59c0 .part L_0x12a5720, 0, 1; +L_0x12a5b70 .part L_0x12a5720, 1, 1; +S_0x10d1f00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10d1d40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e10860/d .functor OR 1, L_0x1e10920, L_0x1e10a80, C4<0>, C4<0>; -L_0x1e10860 .delay 1 (30000,30000,30000) L_0x1e10860/d; -L_0x1e10cb0/d .functor OR 1, L_0x1e10dc0, L_0x1e10f20, C4<0>, C4<0>; -L_0x1e10cb0 .delay 1 (30000,30000,30000) L_0x1e10cb0/d; -L_0x1e110a0/d .functor OR 1, L_0x1e11110, L_0x1e112c0, C4<0>, C4<0>; -L_0x1e110a0 .delay 1 (30000,30000,30000) L_0x1e110a0/d; -v0x1c3f4a0_0 .net *"_s0", 0 0, L_0x1e10860; 1 drivers -v0x1c3f5a0_0 .net *"_s10", 0 0, L_0x1e10dc0; 1 drivers -v0x1c3f680_0 .net *"_s12", 0 0, L_0x1e10f20; 1 drivers -v0x1c3f740_0 .net *"_s14", 0 0, L_0x1e11110; 1 drivers -v0x1c3f820_0 .net *"_s16", 0 0, L_0x1e112c0; 1 drivers -v0x1c3f950_0 .net *"_s3", 0 0, L_0x1e10920; 1 drivers -v0x1c3fa30_0 .net *"_s5", 0 0, L_0x1e10a80; 1 drivers -v0x1c3fb10_0 .net *"_s6", 0 0, L_0x1e10cb0; 1 drivers -v0x1c3fbf0_0 .net "in", 3 0, L_0x1e113b0; 1 drivers -v0x1c3fd60_0 .net "ors", 1 0, L_0x1e10bc0; 1 drivers -v0x1c3fe40_0 .net "out", 0 0, L_0x1e110a0; 1 drivers -L_0x1e10920 .part L_0x1e113b0, 0, 1; -L_0x1e10a80 .part L_0x1e113b0, 1, 1; -L_0x1e10bc0 .concat8 [ 1 1 0 0], L_0x1e10860, L_0x1e10cb0; -L_0x1e10dc0 .part L_0x1e113b0, 2, 1; -L_0x1e10f20 .part L_0x1e113b0, 3, 1; -L_0x1e11110 .part L_0x1e10bc0, 0, 1; -L_0x1e112c0 .part L_0x1e10bc0, 1, 1; -S_0x1c3ff60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c3f090; +L_0x12a3fa0/d .functor OR 1, L_0x12a4060, L_0x12a41c0, C4<0>, C4<0>; +L_0x12a3fa0 .delay 1 (30000,30000,30000) L_0x12a3fa0/d; +L_0x12a43f0/d .functor OR 1, L_0x12a4500, L_0x12a4660, C4<0>, C4<0>; +L_0x12a43f0 .delay 1 (30000,30000,30000) L_0x12a43f0/d; +L_0x12a47e0/d .functor OR 1, L_0x12a4850, L_0x12a4a00, C4<0>, C4<0>; +L_0x12a47e0 .delay 1 (30000,30000,30000) L_0x12a47e0/d; +v0x10d2150_0 .net *"_s0", 0 0, L_0x12a3fa0; 1 drivers +v0x10d2250_0 .net *"_s10", 0 0, L_0x12a4500; 1 drivers +v0x10d2330_0 .net *"_s12", 0 0, L_0x12a4660; 1 drivers +v0x10d23f0_0 .net *"_s14", 0 0, L_0x12a4850; 1 drivers +v0x10d24d0_0 .net *"_s16", 0 0, L_0x12a4a00; 1 drivers +v0x10d2600_0 .net *"_s3", 0 0, L_0x12a4060; 1 drivers +v0x10d26e0_0 .net *"_s5", 0 0, L_0x12a41c0; 1 drivers +v0x10d27c0_0 .net *"_s6", 0 0, L_0x12a43f0; 1 drivers +v0x10d28a0_0 .net "in", 3 0, L_0x12a4af0; 1 drivers +v0x10d2a10_0 .net "ors", 1 0, L_0x12a4300; 1 drivers +v0x10d2af0_0 .net "out", 0 0, L_0x12a47e0; 1 drivers +L_0x12a4060 .part L_0x12a4af0, 0, 1; +L_0x12a41c0 .part L_0x12a4af0, 1, 1; +L_0x12a4300 .concat8 [ 1 1 0 0], L_0x12a3fa0, L_0x12a43f0; +L_0x12a4500 .part L_0x12a4af0, 2, 1; +L_0x12a4660 .part L_0x12a4af0, 3, 1; +L_0x12a4850 .part L_0x12a4300, 0, 1; +L_0x12a4a00 .part L_0x12a4300, 1, 1; +S_0x10d2c10 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10d1d40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e114e0/d .functor OR 1, L_0x1e11550, L_0x1e116b0, C4<0>, C4<0>; -L_0x1e114e0 .delay 1 (30000,30000,30000) L_0x1e114e0/d; -L_0x1e118e0/d .functor OR 1, L_0x1e119f0, L_0x1e11b50, C4<0>, C4<0>; -L_0x1e118e0 .delay 1 (30000,30000,30000) L_0x1e118e0/d; -L_0x1e11cd0/d .functor OR 1, L_0x1e11d40, L_0x1e11ef0, C4<0>, C4<0>; -L_0x1e11cd0 .delay 1 (30000,30000,30000) L_0x1e11cd0/d; -v0x1c40120_0 .net *"_s0", 0 0, L_0x1e114e0; 1 drivers -v0x1c40220_0 .net *"_s10", 0 0, L_0x1e119f0; 1 drivers -v0x1c40300_0 .net *"_s12", 0 0, L_0x1e11b50; 1 drivers -v0x1c403c0_0 .net *"_s14", 0 0, L_0x1e11d40; 1 drivers -v0x1c404a0_0 .net *"_s16", 0 0, L_0x1e11ef0; 1 drivers -v0x1c405d0_0 .net *"_s3", 0 0, L_0x1e11550; 1 drivers -v0x1c406b0_0 .net *"_s5", 0 0, L_0x1e116b0; 1 drivers -v0x1c40790_0 .net *"_s6", 0 0, L_0x1e118e0; 1 drivers -v0x1c40870_0 .net "in", 3 0, L_0x1e12120; 1 drivers -v0x1c409e0_0 .net "ors", 1 0, L_0x1e117f0; 1 drivers -v0x1c40ac0_0 .net "out", 0 0, L_0x1e11cd0; 1 drivers -L_0x1e11550 .part L_0x1e12120, 0, 1; -L_0x1e116b0 .part L_0x1e12120, 1, 1; -L_0x1e117f0 .concat8 [ 1 1 0 0], L_0x1e114e0, L_0x1e118e0; -L_0x1e119f0 .part L_0x1e12120, 2, 1; -L_0x1e11b50 .part L_0x1e12120, 3, 1; -L_0x1e11d40 .part L_0x1e117f0, 0, 1; -L_0x1e11ef0 .part L_0x1e117f0, 1, 1; -S_0x1c413d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c34d70; +L_0x12a4c20/d .functor OR 1, L_0x12a4c90, L_0x12a4df0, C4<0>, C4<0>; +L_0x12a4c20 .delay 1 (30000,30000,30000) L_0x12a4c20/d; +L_0x12a5020/d .functor OR 1, L_0x12a5130, L_0x12a5290, C4<0>, C4<0>; +L_0x12a5020 .delay 1 (30000,30000,30000) L_0x12a5020/d; +L_0x12a5410/d .functor OR 1, L_0x12a5480, L_0x12a5630, C4<0>, C4<0>; +L_0x12a5410 .delay 1 (30000,30000,30000) L_0x12a5410/d; +v0x10d2dd0_0 .net *"_s0", 0 0, L_0x12a4c20; 1 drivers +v0x10d2ed0_0 .net *"_s10", 0 0, L_0x12a5130; 1 drivers +v0x10d2fb0_0 .net *"_s12", 0 0, L_0x12a5290; 1 drivers +v0x10d3070_0 .net *"_s14", 0 0, L_0x12a5480; 1 drivers +v0x10d3150_0 .net *"_s16", 0 0, L_0x12a5630; 1 drivers +v0x10d3280_0 .net *"_s3", 0 0, L_0x12a4c90; 1 drivers +v0x10d3360_0 .net *"_s5", 0 0, L_0x12a4df0; 1 drivers +v0x10d3440_0 .net *"_s6", 0 0, L_0x12a5020; 1 drivers +v0x10d3520_0 .net "in", 3 0, L_0x12a5860; 1 drivers +v0x10d3690_0 .net "ors", 1 0, L_0x12a4f30; 1 drivers +v0x10d3770_0 .net "out", 0 0, L_0x12a5410; 1 drivers +L_0x12a4c90 .part L_0x12a5860, 0, 1; +L_0x12a4df0 .part L_0x12a5860, 1, 1; +L_0x12a4f30 .concat8 [ 1 1 0 0], L_0x12a4c20, L_0x12a5020; +L_0x12a5130 .part L_0x12a5860, 2, 1; +L_0x12a5290 .part L_0x12a5860, 3, 1; +L_0x12a5480 .part L_0x12a4f30, 0, 1; +L_0x12a5630 .part L_0x12a4f30, 1, 1; +S_0x10d4080 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10c7990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -9148,80 +9158,80 @@ S_0x1c413d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c34d70; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e0da70/d .functor XNOR 1, L_0x1e16060, L_0x1e161c0, C4<0>, C4<0>; -L_0x1e0da70 .delay 1 (20000,20000,20000) L_0x1e0da70/d; -L_0x1e0dce0/d .functor AND 1, L_0x1e16060, L_0x1e0c960, C4<1>, C4<1>; -L_0x1e0dce0 .delay 1 (30000,30000,30000) L_0x1e0dce0/d; -L_0x1e0dd50/d .functor AND 1, L_0x1e0da70, L_0x1e0c7d0, C4<1>, C4<1>; -L_0x1e0dd50 .delay 1 (30000,30000,30000) L_0x1e0dd50/d; -L_0x1e0deb0/d .functor OR 1, L_0x1e0dd50, L_0x1e0dce0, C4<0>, C4<0>; -L_0x1e0deb0 .delay 1 (30000,30000,30000) L_0x1e0deb0/d; -v0x1c41680_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers -v0x1c41770_0 .net "a_", 0 0, L_0x1e0c440; alias, 1 drivers -v0x1c41830_0 .net "b", 0 0, L_0x1e161c0; alias, 1 drivers -v0x1c41920_0 .net "b_", 0 0, L_0x1e0c960; alias, 1 drivers -v0x1c419c0_0 .net "carryin", 0 0, L_0x1e0c7d0; alias, 1 drivers -v0x1c41b00_0 .net "eq", 0 0, L_0x1e0da70; 1 drivers -v0x1c41bc0_0 .net "lt", 0 0, L_0x1e0dce0; 1 drivers -v0x1c41c80_0 .net "out", 0 0, L_0x1e0deb0; 1 drivers -v0x1c41d40_0 .net "w0", 0 0, L_0x1e0dd50; 1 drivers -S_0x1c41f90 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c34d70; +L_0x12a10d0/d .functor XNOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; +L_0x12a10d0 .delay 1 (20000,20000,20000) L_0x12a10d0/d; +L_0x12a1340/d .functor AND 1, L_0x12a97d0, L_0x12a00d0, C4<1>, C4<1>; +L_0x12a1340 .delay 1 (30000,30000,30000) L_0x12a1340/d; +L_0x12a13b0/d .functor AND 1, L_0x12a10d0, L_0x129ff40, C4<1>, C4<1>; +L_0x12a13b0 .delay 1 (30000,30000,30000) L_0x12a13b0/d; +L_0x12a1510/d .functor OR 1, L_0x12a13b0, L_0x12a1340, C4<0>, C4<0>; +L_0x12a1510 .delay 1 (30000,30000,30000) L_0x12a1510/d; +v0x10d4330_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers +v0x10d4420_0 .net "a_", 0 0, L_0x129fbb0; alias, 1 drivers +v0x10d44e0_0 .net "b", 0 0, L_0x12a9930; alias, 1 drivers +v0x10d45d0_0 .net "b_", 0 0, L_0x12a00d0; alias, 1 drivers +v0x10d4670_0 .net "carryin", 0 0, L_0x129ff40; alias, 1 drivers +v0x10d47b0_0 .net "eq", 0 0, L_0x12a10d0; 1 drivers +v0x10d4870_0 .net "lt", 0 0, L_0x12a1340; 1 drivers +v0x10d4930_0 .net "out", 0 0, L_0x12a1510; 1 drivers +v0x10d49f0_0 .net "w0", 0 0, L_0x12a13b0; 1 drivers +S_0x10d4c40 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10c7990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e0d850/d .functor OR 1, L_0x1e0d350, L_0x1c431f0, C4<0>, C4<0>; -L_0x1e0d850 .delay 1 (30000,30000,30000) L_0x1e0d850/d; -v0x1c42d80_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers -v0x1c42ed0_0 .net "b", 0 0, L_0x1e0c960; alias, 1 drivers -v0x1c42f90_0 .net "c1", 0 0, L_0x1e0d350; 1 drivers -v0x1c43030_0 .net "c2", 0 0, L_0x1c431f0; 1 drivers -v0x1c43100_0 .net "carryin", 0 0, L_0x1e0c7d0; alias, 1 drivers -v0x1c43280_0 .net "carryout", 0 0, L_0x1e0d850; 1 drivers -v0x1c43320_0 .net "s1", 0 0, L_0x1e0d290; 1 drivers -v0x1c433c0_0 .net "sum", 0 0, L_0x1e0d4b0; 1 drivers -S_0x1c421e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c41f90; +L_0x12a0eb0/d .functor OR 1, L_0x12a0a00, L_0x10d5ea0, C4<0>, C4<0>; +L_0x12a0eb0 .delay 1 (30000,30000,30000) L_0x12a0eb0/d; +v0x10d5a30_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers +v0x10d5b80_0 .net "b", 0 0, L_0x12a00d0; alias, 1 drivers +v0x10d5c40_0 .net "c1", 0 0, L_0x12a0a00; 1 drivers +v0x10d5ce0_0 .net "c2", 0 0, L_0x10d5ea0; 1 drivers +v0x10d5db0_0 .net "carryin", 0 0, L_0x129ff40; alias, 1 drivers +v0x10d5f30_0 .net "carryout", 0 0, L_0x12a0eb0; 1 drivers +v0x10d5fd0_0 .net "s1", 0 0, L_0x12a0940; 1 drivers +v0x10d6070_0 .net "sum", 0 0, L_0x12a0b60; 1 drivers +S_0x10d4e90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10d4c40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e0d290/d .functor XOR 1, L_0x1e16060, L_0x1e0c960, C4<0>, C4<0>; -L_0x1e0d290 .delay 1 (30000,30000,30000) L_0x1e0d290/d; -L_0x1e0d350/d .functor AND 1, L_0x1e16060, L_0x1e0c960, C4<1>, C4<1>; -L_0x1e0d350 .delay 1 (30000,30000,30000) L_0x1e0d350/d; -v0x1c42440_0 .net "a", 0 0, L_0x1e16060; alias, 1 drivers -v0x1c42500_0 .net "b", 0 0, L_0x1e0c960; alias, 1 drivers -v0x1c425c0_0 .net "carryout", 0 0, L_0x1e0d350; alias, 1 drivers -v0x1c42660_0 .net "sum", 0 0, L_0x1e0d290; alias, 1 drivers -S_0x1c42790 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c41f90; +L_0x12a0940/d .functor XOR 1, L_0x12a97d0, L_0x12a00d0, C4<0>, C4<0>; +L_0x12a0940 .delay 1 (30000,30000,30000) L_0x12a0940/d; +L_0x12a0a00/d .functor AND 1, L_0x12a97d0, L_0x12a00d0, C4<1>, C4<1>; +L_0x12a0a00 .delay 1 (30000,30000,30000) L_0x12a0a00/d; +v0x10d50f0_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers +v0x10d51b0_0 .net "b", 0 0, L_0x12a00d0; alias, 1 drivers +v0x10d5270_0 .net "carryout", 0 0, L_0x12a0a00; alias, 1 drivers +v0x10d5310_0 .net "sum", 0 0, L_0x12a0940; alias, 1 drivers +S_0x10d5440 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10d4c40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e0d4b0/d .functor XOR 1, L_0x1e0d290, L_0x1e0c7d0, C4<0>, C4<0>; -L_0x1e0d4b0 .delay 1 (30000,30000,30000) L_0x1e0d4b0/d; -L_0x1c431f0/d .functor AND 1, L_0x1e0d290, L_0x1e0c7d0, C4<1>, C4<1>; -L_0x1c431f0 .delay 1 (30000,30000,30000) L_0x1c431f0/d; -v0x1c429f0_0 .net "a", 0 0, L_0x1e0d290; alias, 1 drivers -v0x1c42ac0_0 .net "b", 0 0, L_0x1e0c7d0; alias, 1 drivers -v0x1c42b60_0 .net "carryout", 0 0, L_0x1c431f0; alias, 1 drivers -v0x1c42c30_0 .net "sum", 0 0, L_0x1e0d4b0; alias, 1 drivers -S_0x1c447e0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c34a00; - .timescale -9 -12; -L_0x7f72592db218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db260 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e16100/d .functor OR 1, L_0x7f72592db218, L_0x7f72592db260, C4<0>, C4<0>; -L_0x1e16100 .delay 1 (30000,30000,30000) L_0x1e16100/d; -v0x1c449d0_0 .net/2u *"_s0", 0 0, L_0x7f72592db218; 1 drivers -v0x1c44ab0_0 .net/2u *"_s2", 0 0, L_0x7f72592db260; 1 drivers -S_0x1c44b90 .scope generate, "alu_slices[17]" "alu_slices[17]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c44da0 .param/l "i" 0 3 37, +C4<010001>; -S_0x1c44e60 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c44b90; +L_0x12a0b60/d .functor XOR 1, L_0x12a0940, L_0x129ff40, C4<0>, C4<0>; +L_0x12a0b60 .delay 1 (30000,30000,30000) L_0x12a0b60/d; +L_0x10d5ea0/d .functor AND 1, L_0x12a0940, L_0x129ff40, C4<1>, C4<1>; +L_0x10d5ea0 .delay 1 (30000,30000,30000) L_0x10d5ea0/d; +v0x10d56a0_0 .net "a", 0 0, L_0x12a0940; alias, 1 drivers +v0x10d5770_0 .net "b", 0 0, L_0x129ff40; alias, 1 drivers +v0x10d5810_0 .net "carryout", 0 0, L_0x10d5ea0; alias, 1 drivers +v0x10d58e0_0 .net "sum", 0 0, L_0x12a0b60; alias, 1 drivers +S_0x10d7490 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10c7620; + .timescale -9 -12; +L_0x2b0ab3d06218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06260 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12a9870/d .functor OR 1, L_0x2b0ab3d06218, L_0x2b0ab3d06260, C4<0>, C4<0>; +L_0x12a9870 .delay 1 (30000,30000,30000) L_0x12a9870/d; +v0x10d7680_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06218; 1 drivers +v0x10d7760_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06260; 1 drivers +S_0x10d7840 .scope generate, "alu_slices[17]" "alu_slices[17]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x10d7a50 .param/l "i" 0 3 41, +C4<010001>; +S_0x10d7b10 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10d7840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -9230,445 +9240,445 @@ S_0x1c44e60 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c44b90; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e063c0/d .functor NOT 1, L_0x1e1fec0, C4<0>, C4<0>, C4<0>; -L_0x1e063c0 .delay 1 (10000,10000,10000) L_0x1e063c0/d; -L_0x1dc8070/d .functor NOT 1, L_0x1e16260, C4<0>, C4<0>, C4<0>; -L_0x1dc8070 .delay 1 (10000,10000,10000) L_0x1dc8070/d; -L_0x1e17700/d .functor XOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; -L_0x1e17700 .delay 1 (30000,30000,30000) L_0x1e17700/d; -L_0x7f72592db2a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db2f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e17db0/d .functor OR 1, L_0x7f72592db2a8, L_0x7f72592db2f0, C4<0>, C4<0>; -L_0x1e17db0 .delay 1 (30000,30000,30000) L_0x1e17db0/d; -L_0x1e17fb0/d .functor AND 1, L_0x1e1fec0, L_0x1e16260, C4<1>, C4<1>; -L_0x1e17fb0 .delay 1 (30000,30000,30000) L_0x1e17fb0/d; -L_0x1e18070/d .functor NAND 1, L_0x1e1fec0, L_0x1e16260, C4<1>, C4<1>; -L_0x1e18070 .delay 1 (20000,20000,20000) L_0x1e18070/d; -L_0x1e181d0/d .functor XOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; -L_0x1e181d0 .delay 1 (20000,20000,20000) L_0x1e181d0/d; -L_0x1e18680/d .functor OR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; -L_0x1e18680 .delay 1 (30000,30000,30000) L_0x1e18680/d; -L_0x1e1fdc0/d .functor NOT 1, L_0x1e1bfc0, C4<0>, C4<0>, C4<0>; -L_0x1e1fdc0 .delay 1 (10000,10000,10000) L_0x1e1fdc0/d; -v0x1c535b0_0 .net "A", 0 0, L_0x1e1fec0; 1 drivers -v0x1c53670_0 .net "A_", 0 0, L_0x1e063c0; 1 drivers -v0x1c53730_0 .net "B", 0 0, L_0x1e16260; 1 drivers -v0x1c53800_0 .net "B_", 0 0, L_0x1dc8070; 1 drivers -v0x1c538a0_0 .net *"_s12", 0 0, L_0x1e17db0; 1 drivers -v0x1c53990_0 .net/2s *"_s14", 0 0, L_0x7f72592db2a8; 1 drivers -v0x1c53a50_0 .net/2s *"_s16", 0 0, L_0x7f72592db2f0; 1 drivers -v0x1c53b30_0 .net *"_s18", 0 0, L_0x1e17fb0; 1 drivers -v0x1c53c10_0 .net *"_s20", 0 0, L_0x1e18070; 1 drivers -v0x1c53d80_0 .net *"_s22", 0 0, L_0x1e181d0; 1 drivers -v0x1c53e60_0 .net *"_s24", 0 0, L_0x1e18680; 1 drivers -o0x7f725937dd18 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c53f40_0 name=_s30 -o0x7f725937dd48 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c54020_0 name=_s32 -v0x1c54100_0 .net *"_s8", 0 0, L_0x1e17700; 1 drivers -v0x1c541e0_0 .net "carryin", 0 0, L_0x1e16300; 1 drivers -v0x1c54280_0 .net "carryout", 0 0, L_0x1e1fa60; 1 drivers -v0x1c54320_0 .net "carryouts", 7 0, L_0x1ec07c0; 1 drivers -v0x1c544d0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c54570_0 .net "result", 0 0, L_0x1e1bfc0; 1 drivers -v0x1c54660_0 .net "results", 7 0, L_0x1e18450; 1 drivers -v0x1c54770_0 .net "zero", 0 0, L_0x1e1fdc0; 1 drivers -LS_0x1e18450_0_0 .concat8 [ 1 1 1 1], L_0x1e16bd0, L_0x1e17200, L_0x1e17700, L_0x1e17db0; -LS_0x1e18450_0_4 .concat8 [ 1 1 1 1], L_0x1e17fb0, L_0x1e18070, L_0x1e181d0, L_0x1e18680; -L_0x1e18450 .concat8 [ 4 4 0 0], LS_0x1e18450_0_0, LS_0x1e18450_0_4; -LS_0x1ec07c0_0_0 .concat [ 1 1 1 1], L_0x1e16e80, L_0x1e175a0, o0x7f725937dd18, L_0x1e17c00; -LS_0x1ec07c0_0_4 .concat [ 4 0 0 0], o0x7f725937dd48; -L_0x1ec07c0 .concat [ 4 4 0 0], LS_0x1ec07c0_0_0, LS_0x1ec07c0_0_4; -S_0x1c450e0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c44e60; +L_0x12a3880/d .functor NOT 1, L_0x12b3630, C4<0>, C4<0>, C4<0>; +L_0x12a3880 .delay 1 (10000,10000,10000) L_0x12a3880/d; +L_0x125b7b0/d .functor NOT 1, L_0x12a99d0, C4<0>, C4<0>, C4<0>; +L_0x125b7b0 .delay 1 (10000,10000,10000) L_0x125b7b0/d; +L_0x12aae70/d .functor XOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; +L_0x12aae70 .delay 1 (30000,30000,30000) L_0x12aae70/d; +L_0x2b0ab3d062a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d062f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12ab520/d .functor OR 1, L_0x2b0ab3d062a8, L_0x2b0ab3d062f0, C4<0>, C4<0>; +L_0x12ab520 .delay 1 (30000,30000,30000) L_0x12ab520/d; +L_0x12ab720/d .functor AND 1, L_0x12b3630, L_0x12a99d0, C4<1>, C4<1>; +L_0x12ab720 .delay 1 (30000,30000,30000) L_0x12ab720/d; +L_0x12ab7e0/d .functor NAND 1, L_0x12b3630, L_0x12a99d0, C4<1>, C4<1>; +L_0x12ab7e0 .delay 1 (20000,20000,20000) L_0x12ab7e0/d; +L_0x12ab940/d .functor XOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; +L_0x12ab940 .delay 1 (20000,20000,20000) L_0x12ab940/d; +L_0x12abdf0/d .functor OR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; +L_0x12abdf0 .delay 1 (30000,30000,30000) L_0x12abdf0/d; +L_0x12b3530/d .functor NOT 1, L_0x12af760, C4<0>, C4<0>, C4<0>; +L_0x12b3530 .delay 1 (10000,10000,10000) L_0x12b3530/d; +v0x10e6240_0 .net "A", 0 0, L_0x12b3630; 1 drivers +v0x10e6300_0 .net "A_", 0 0, L_0x12a3880; 1 drivers +v0x10e63c0_0 .net "B", 0 0, L_0x12a99d0; 1 drivers +v0x10e6490_0 .net "B_", 0 0, L_0x125b7b0; 1 drivers +v0x10e6530_0 .net *"_s12", 0 0, L_0x12ab520; 1 drivers +v0x10e6620_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d062a8; 1 drivers +v0x10e66e0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d062f0; 1 drivers +v0x10e67c0_0 .net *"_s18", 0 0, L_0x12ab720; 1 drivers +v0x10e68a0_0 .net *"_s20", 0 0, L_0x12ab7e0; 1 drivers +v0x10e6a10_0 .net *"_s22", 0 0, L_0x12ab940; 1 drivers +v0x10e6af0_0 .net *"_s24", 0 0, L_0x12abdf0; 1 drivers +o0x2b0ab3cccd18 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10e6bd0_0 name=_s30 +o0x2b0ab3cccd48 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10e6cb0_0 name=_s32 +v0x10e6d90_0 .net *"_s8", 0 0, L_0x12aae70; 1 drivers +v0x10e6e70_0 .net "carryin", 0 0, L_0x12a9a70; 1 drivers +v0x10e6f10_0 .net "carryout", 0 0, L_0x12b31d0; 1 drivers +v0x10e6fb0_0 .net "carryouts", 7 0, L_0x1354af0; 1 drivers +v0x10e7160_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10e7200_0 .net "result", 0 0, L_0x12af760; 1 drivers +v0x10e72f0_0 .net "results", 7 0, L_0x12abbc0; 1 drivers +v0x10e7400_0 .net "zero", 0 0, L_0x12b3530; 1 drivers +LS_0x12abbc0_0_0 .concat8 [ 1 1 1 1], L_0x12aa340, L_0x12aa970, L_0x12aae70, L_0x12ab520; +LS_0x12abbc0_0_4 .concat8 [ 1 1 1 1], L_0x12ab720, L_0x12ab7e0, L_0x12ab940, L_0x12abdf0; +L_0x12abbc0 .concat8 [ 4 4 0 0], LS_0x12abbc0_0_0, LS_0x12abbc0_0_4; +LS_0x1354af0_0_0 .concat [ 1 1 1 1], L_0x12aa5f0, L_0x12aad10, o0x2b0ab3cccd18, L_0x12ab370; +LS_0x1354af0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cccd48; +L_0x1354af0 .concat [ 4 4 0 0], LS_0x1354af0_0_0, LS_0x1354af0_0_4; +S_0x10d7d90 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10d7b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e16e80/d .functor OR 1, L_0x1e16960, L_0x1e16d20, C4<0>, C4<0>; -L_0x1e16e80 .delay 1 (30000,30000,30000) L_0x1e16e80/d; -v0x1c45f10_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers -v0x1c45fd0_0 .net "b", 0 0, L_0x1e16260; alias, 1 drivers -v0x1c460a0_0 .net "c1", 0 0, L_0x1e16960; 1 drivers -v0x1c461a0_0 .net "c2", 0 0, L_0x1e16d20; 1 drivers -v0x1c46270_0 .net "carryin", 0 0, L_0x1e16300; alias, 1 drivers -v0x1c46360_0 .net "carryout", 0 0, L_0x1e16e80; 1 drivers -v0x1c46400_0 .net "s1", 0 0, L_0x1e168a0; 1 drivers -v0x1c464f0_0 .net "sum", 0 0, L_0x1e16bd0; 1 drivers -S_0x1c45350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c450e0; +L_0x12aa5f0/d .functor OR 1, L_0x12aa0d0, L_0x12aa490, C4<0>, C4<0>; +L_0x12aa5f0 .delay 1 (30000,30000,30000) L_0x12aa5f0/d; +v0x10d8bc0_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers +v0x10d8c80_0 .net "b", 0 0, L_0x12a99d0; alias, 1 drivers +v0x10d8d50_0 .net "c1", 0 0, L_0x12aa0d0; 1 drivers +v0x10d8e50_0 .net "c2", 0 0, L_0x12aa490; 1 drivers +v0x10d8f20_0 .net "carryin", 0 0, L_0x12a9a70; alias, 1 drivers +v0x10d9010_0 .net "carryout", 0 0, L_0x12aa5f0; 1 drivers +v0x10d90b0_0 .net "s1", 0 0, L_0x12aa010; 1 drivers +v0x10d91a0_0 .net "sum", 0 0, L_0x12aa340; 1 drivers +S_0x10d8000 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10d7d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e168a0/d .functor XOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; -L_0x1e168a0 .delay 1 (30000,30000,30000) L_0x1e168a0/d; -L_0x1e16960/d .functor AND 1, L_0x1e1fec0, L_0x1e16260, C4<1>, C4<1>; -L_0x1e16960 .delay 1 (30000,30000,30000) L_0x1e16960/d; -v0x1c455b0_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers -v0x1c45690_0 .net "b", 0 0, L_0x1e16260; alias, 1 drivers -v0x1c45750_0 .net "carryout", 0 0, L_0x1e16960; alias, 1 drivers -v0x1c457f0_0 .net "sum", 0 0, L_0x1e168a0; alias, 1 drivers -S_0x1c45930 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c450e0; +L_0x12aa010/d .functor XOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; +L_0x12aa010 .delay 1 (30000,30000,30000) L_0x12aa010/d; +L_0x12aa0d0/d .functor AND 1, L_0x12b3630, L_0x12a99d0, C4<1>, C4<1>; +L_0x12aa0d0 .delay 1 (30000,30000,30000) L_0x12aa0d0/d; +v0x10d8260_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers +v0x10d8340_0 .net "b", 0 0, L_0x12a99d0; alias, 1 drivers +v0x10d8400_0 .net "carryout", 0 0, L_0x12aa0d0; alias, 1 drivers +v0x10d84a0_0 .net "sum", 0 0, L_0x12aa010; alias, 1 drivers +S_0x10d85e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10d7d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e16bd0/d .functor XOR 1, L_0x1e168a0, L_0x1e16300, C4<0>, C4<0>; -L_0x1e16bd0 .delay 1 (30000,30000,30000) L_0x1e16bd0/d; -L_0x1e16d20/d .functor AND 1, L_0x1e168a0, L_0x1e16300, C4<1>, C4<1>; -L_0x1e16d20 .delay 1 (30000,30000,30000) L_0x1e16d20/d; -v0x1c45b90_0 .net "a", 0 0, L_0x1e168a0; alias, 1 drivers -v0x1c45c30_0 .net "b", 0 0, L_0x1e16300; alias, 1 drivers -v0x1c45cd0_0 .net "carryout", 0 0, L_0x1e16d20; alias, 1 drivers -v0x1c45da0_0 .net "sum", 0 0, L_0x1e16bd0; alias, 1 drivers -S_0x1c465c0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c44e60; +L_0x12aa340/d .functor XOR 1, L_0x12aa010, L_0x12a9a70, C4<0>, C4<0>; +L_0x12aa340 .delay 1 (30000,30000,30000) L_0x12aa340/d; +L_0x12aa490/d .functor AND 1, L_0x12aa010, L_0x12a9a70, C4<1>, C4<1>; +L_0x12aa490 .delay 1 (30000,30000,30000) L_0x12aa490/d; +v0x10d8840_0 .net "a", 0 0, L_0x12aa010; alias, 1 drivers +v0x10d88e0_0 .net "b", 0 0, L_0x12a9a70; alias, 1 drivers +v0x10d8980_0 .net "carryout", 0 0, L_0x12aa490; alias, 1 drivers +v0x10d8a50_0 .net "sum", 0 0, L_0x12aa340; alias, 1 drivers +S_0x10d9270 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10d7b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c4b9b0_0 .net "ands", 7 0, L_0x1e1da60; 1 drivers -v0x1c4bac0_0 .net "in", 7 0, L_0x1ec07c0; alias, 1 drivers -v0x1c4bb80_0 .net "out", 0 0, L_0x1e1fa60; alias, 1 drivers -v0x1c4bc50_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c467e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c465c0; +v0x10de660_0 .net "ands", 7 0, L_0x12b11d0; 1 drivers +v0x10de770_0 .net "in", 7 0, L_0x1354af0; alias, 1 drivers +v0x10de830_0 .net "out", 0 0, L_0x12b31d0; alias, 1 drivers +v0x10de900_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10d9490 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10d9270; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c48f10_0 .net "A", 7 0, L_0x1ec07c0; alias, 1 drivers -v0x1c49010_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c490d0_0 .net *"_s0", 0 0, L_0x1e1c320; 1 drivers -v0x1c49190_0 .net *"_s12", 0 0, L_0x1e1cc90; 1 drivers -v0x1c49270_0 .net *"_s16", 0 0, L_0x1e1cff0; 1 drivers -v0x1c493a0_0 .net *"_s20", 0 0, L_0x1e1d360; 1 drivers -v0x1c49480_0 .net *"_s24", 0 0, L_0x1e1d750; 1 drivers -v0x1c49560_0 .net *"_s28", 0 0, L_0x1e1d6e0; 1 drivers -v0x1c49640_0 .net *"_s4", 0 0, L_0x1e1c630; 1 drivers -v0x1c497b0_0 .net *"_s8", 0 0, L_0x1e1c980; 1 drivers -v0x1c49890_0 .net "out", 7 0, L_0x1e1da60; alias, 1 drivers -L_0x1e1c3e0 .part L_0x1ec07c0, 0, 1; -L_0x1e1c540 .part v0x1d6daa0_0, 0, 1; -L_0x1e1c6f0 .part L_0x1ec07c0, 1, 1; -L_0x1e1c8e0 .part v0x1d6daa0_0, 1, 1; -L_0x1e1ca40 .part L_0x1ec07c0, 2, 1; -L_0x1e1cba0 .part v0x1d6daa0_0, 2, 1; -L_0x1e1cd50 .part L_0x1ec07c0, 3, 1; -L_0x1e1ceb0 .part v0x1d6daa0_0, 3, 1; -L_0x1e1d0b0 .part L_0x1ec07c0, 4, 1; -L_0x1e1d210 .part v0x1d6daa0_0, 4, 1; -L_0x1e1d3d0 .part L_0x1ec07c0, 5, 1; -L_0x1e1d640 .part v0x1d6daa0_0, 5, 1; -L_0x1e1d810 .part L_0x1ec07c0, 6, 1; -L_0x1e1d970 .part v0x1d6daa0_0, 6, 1; -LS_0x1e1da60_0_0 .concat8 [ 1 1 1 1], L_0x1e1c320, L_0x1e1c630, L_0x1e1c980, L_0x1e1cc90; -LS_0x1e1da60_0_4 .concat8 [ 1 1 1 1], L_0x1e1cff0, L_0x1e1d360, L_0x1e1d750, L_0x1e1d6e0; -L_0x1e1da60 .concat8 [ 4 4 0 0], LS_0x1e1da60_0_0, LS_0x1e1da60_0_4; -L_0x1e1de20 .part L_0x1ec07c0, 7, 1; -L_0x1e1e010 .part v0x1d6daa0_0, 7, 1; -S_0x1c46a40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c46c50 .param/l "i" 0 4 54, +C4<00>; -L_0x1e1c320/d .functor AND 1, L_0x1e1c3e0, L_0x1e1c540, C4<1>, C4<1>; -L_0x1e1c320 .delay 1 (30000,30000,30000) L_0x1e1c320/d; -v0x1c46d30_0 .net *"_s0", 0 0, L_0x1e1c3e0; 1 drivers -v0x1c46e10_0 .net *"_s1", 0 0, L_0x1e1c540; 1 drivers -S_0x1c46ef0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c47100 .param/l "i" 0 4 54, +C4<01>; -L_0x1e1c630/d .functor AND 1, L_0x1e1c6f0, L_0x1e1c8e0, C4<1>, C4<1>; -L_0x1e1c630 .delay 1 (30000,30000,30000) L_0x1e1c630/d; -v0x1c471c0_0 .net *"_s0", 0 0, L_0x1e1c6f0; 1 drivers -v0x1c472a0_0 .net *"_s1", 0 0, L_0x1e1c8e0; 1 drivers -S_0x1c47380 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c47590 .param/l "i" 0 4 54, +C4<010>; -L_0x1e1c980/d .functor AND 1, L_0x1e1ca40, L_0x1e1cba0, C4<1>, C4<1>; -L_0x1e1c980 .delay 1 (30000,30000,30000) L_0x1e1c980/d; -v0x1c47630_0 .net *"_s0", 0 0, L_0x1e1ca40; 1 drivers -v0x1c47710_0 .net *"_s1", 0 0, L_0x1e1cba0; 1 drivers -S_0x1c477f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c47a00 .param/l "i" 0 4 54, +C4<011>; -L_0x1e1cc90/d .functor AND 1, L_0x1e1cd50, L_0x1e1ceb0, C4<1>, C4<1>; -L_0x1e1cc90 .delay 1 (30000,30000,30000) L_0x1e1cc90/d; -v0x1c47ac0_0 .net *"_s0", 0 0, L_0x1e1cd50; 1 drivers -v0x1c47ba0_0 .net *"_s1", 0 0, L_0x1e1ceb0; 1 drivers -S_0x1c47c80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c47ee0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e1cff0/d .functor AND 1, L_0x1e1d0b0, L_0x1e1d210, C4<1>, C4<1>; -L_0x1e1cff0 .delay 1 (30000,30000,30000) L_0x1e1cff0/d; -v0x1c47fa0_0 .net *"_s0", 0 0, L_0x1e1d0b0; 1 drivers -v0x1c48080_0 .net *"_s1", 0 0, L_0x1e1d210; 1 drivers -S_0x1c48160 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c48370 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e1d360/d .functor AND 1, L_0x1e1d3d0, L_0x1e1d640, C4<1>, C4<1>; -L_0x1e1d360 .delay 1 (30000,30000,30000) L_0x1e1d360/d; -v0x1c48430_0 .net *"_s0", 0 0, L_0x1e1d3d0; 1 drivers -v0x1c48510_0 .net *"_s1", 0 0, L_0x1e1d640; 1 drivers -S_0x1c485f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c48800 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e1d750/d .functor AND 1, L_0x1e1d810, L_0x1e1d970, C4<1>, C4<1>; -L_0x1e1d750 .delay 1 (30000,30000,30000) L_0x1e1d750/d; -v0x1c488c0_0 .net *"_s0", 0 0, L_0x1e1d810; 1 drivers -v0x1c489a0_0 .net *"_s1", 0 0, L_0x1e1d970; 1 drivers -S_0x1c48a80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c467e0; - .timescale -9 -12; -P_0x1c48c90 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e1d6e0/d .functor AND 1, L_0x1e1de20, L_0x1e1e010, C4<1>, C4<1>; -L_0x1e1d6e0 .delay 1 (30000,30000,30000) L_0x1e1d6e0/d; -v0x1c48d50_0 .net *"_s0", 0 0, L_0x1e1de20; 1 drivers -v0x1c48e30_0 .net *"_s1", 0 0, L_0x1e1e010; 1 drivers -S_0x1c499f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c465c0; +v0x10dbbc0_0 .net "A", 7 0, L_0x1354af0; alias, 1 drivers +v0x10dbcc0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10dbd80_0 .net *"_s0", 0 0, L_0x12afac0; 1 drivers +v0x10dbe40_0 .net *"_s12", 0 0, L_0x12b0430; 1 drivers +v0x10dbf20_0 .net *"_s16", 0 0, L_0x12b0790; 1 drivers +v0x10dc050_0 .net *"_s20", 0 0, L_0x12b0aa0; 1 drivers +v0x10dc130_0 .net *"_s24", 0 0, L_0x12b0e90; 1 drivers +v0x10dc210_0 .net *"_s28", 0 0, L_0x12b0e20; 1 drivers +v0x10dc2f0_0 .net *"_s4", 0 0, L_0x12afdd0; 1 drivers +v0x10dc460_0 .net *"_s8", 0 0, L_0x12b0120; 1 drivers +v0x10dc540_0 .net "out", 7 0, L_0x12b11d0; alias, 1 drivers +L_0x12afb80 .part L_0x1354af0, 0, 1; +L_0x12afce0 .part v0x12010b0_0, 0, 1; +L_0x12afe90 .part L_0x1354af0, 1, 1; +L_0x12b0080 .part v0x12010b0_0, 1, 1; +L_0x12b01e0 .part L_0x1354af0, 2, 1; +L_0x12b0340 .part v0x12010b0_0, 2, 1; +L_0x12b04f0 .part L_0x1354af0, 3, 1; +L_0x12b0650 .part v0x12010b0_0, 3, 1; +L_0x12b0850 .part L_0x1354af0, 4, 1; +L_0x12b09b0 .part v0x12010b0_0, 4, 1; +L_0x12b0b10 .part L_0x1354af0, 5, 1; +L_0x12b0d80 .part v0x12010b0_0, 5, 1; +L_0x12b0f80 .part L_0x1354af0, 6, 1; +L_0x12b10e0 .part v0x12010b0_0, 6, 1; +LS_0x12b11d0_0_0 .concat8 [ 1 1 1 1], L_0x12afac0, L_0x12afdd0, L_0x12b0120, L_0x12b0430; +LS_0x12b11d0_0_4 .concat8 [ 1 1 1 1], L_0x12b0790, L_0x12b0aa0, L_0x12b0e90, L_0x12b0e20; +L_0x12b11d0 .concat8 [ 4 4 0 0], LS_0x12b11d0_0_0, LS_0x12b11d0_0_4; +L_0x12b1590 .part L_0x1354af0, 7, 1; +L_0x12b1780 .part v0x12010b0_0, 7, 1; +S_0x10d96f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10d9900 .param/l "i" 0 4 54, +C4<00>; +L_0x12afac0/d .functor AND 1, L_0x12afb80, L_0x12afce0, C4<1>, C4<1>; +L_0x12afac0 .delay 1 (30000,30000,30000) L_0x12afac0/d; +v0x10d99e0_0 .net *"_s0", 0 0, L_0x12afb80; 1 drivers +v0x10d9ac0_0 .net *"_s1", 0 0, L_0x12afce0; 1 drivers +S_0x10d9ba0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10d9db0 .param/l "i" 0 4 54, +C4<01>; +L_0x12afdd0/d .functor AND 1, L_0x12afe90, L_0x12b0080, C4<1>, C4<1>; +L_0x12afdd0 .delay 1 (30000,30000,30000) L_0x12afdd0/d; +v0x10d9e70_0 .net *"_s0", 0 0, L_0x12afe90; 1 drivers +v0x10d9f50_0 .net *"_s1", 0 0, L_0x12b0080; 1 drivers +S_0x10da030 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10da240 .param/l "i" 0 4 54, +C4<010>; +L_0x12b0120/d .functor AND 1, L_0x12b01e0, L_0x12b0340, C4<1>, C4<1>; +L_0x12b0120 .delay 1 (30000,30000,30000) L_0x12b0120/d; +v0x10da2e0_0 .net *"_s0", 0 0, L_0x12b01e0; 1 drivers +v0x10da3c0_0 .net *"_s1", 0 0, L_0x12b0340; 1 drivers +S_0x10da4a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10da6b0 .param/l "i" 0 4 54, +C4<011>; +L_0x12b0430/d .functor AND 1, L_0x12b04f0, L_0x12b0650, C4<1>, C4<1>; +L_0x12b0430 .delay 1 (30000,30000,30000) L_0x12b0430/d; +v0x10da770_0 .net *"_s0", 0 0, L_0x12b04f0; 1 drivers +v0x10da850_0 .net *"_s1", 0 0, L_0x12b0650; 1 drivers +S_0x10da930 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10dab90 .param/l "i" 0 4 54, +C4<0100>; +L_0x12b0790/d .functor AND 1, L_0x12b0850, L_0x12b09b0, C4<1>, C4<1>; +L_0x12b0790 .delay 1 (30000,30000,30000) L_0x12b0790/d; +v0x10dac50_0 .net *"_s0", 0 0, L_0x12b0850; 1 drivers +v0x10dad30_0 .net *"_s1", 0 0, L_0x12b09b0; 1 drivers +S_0x10dae10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10db020 .param/l "i" 0 4 54, +C4<0101>; +L_0x12b0aa0/d .functor AND 1, L_0x12b0b10, L_0x12b0d80, C4<1>, C4<1>; +L_0x12b0aa0 .delay 1 (30000,30000,30000) L_0x12b0aa0/d; +v0x10db0e0_0 .net *"_s0", 0 0, L_0x12b0b10; 1 drivers +v0x10db1c0_0 .net *"_s1", 0 0, L_0x12b0d80; 1 drivers +S_0x10db2a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10db4b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12b0e90/d .functor AND 1, L_0x12b0f80, L_0x12b10e0, C4<1>, C4<1>; +L_0x12b0e90 .delay 1 (30000,30000,30000) L_0x12b0e90/d; +v0x10db570_0 .net *"_s0", 0 0, L_0x12b0f80; 1 drivers +v0x10db650_0 .net *"_s1", 0 0, L_0x12b10e0; 1 drivers +S_0x10db730 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10d9490; + .timescale -9 -12; +P_0x10db940 .param/l "i" 0 4 54, +C4<0111>; +L_0x12b0e20/d .functor AND 1, L_0x12b1590, L_0x12b1780, C4<1>, C4<1>; +L_0x12b0e20 .delay 1 (30000,30000,30000) L_0x12b0e20/d; +v0x10dba00_0 .net *"_s0", 0 0, L_0x12b1590; 1 drivers +v0x10dbae0_0 .net *"_s1", 0 0, L_0x12b1780; 1 drivers +S_0x10dc6a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10d9270; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e1fa60/d .functor OR 1, L_0x1e1fb20, L_0x1e1fcd0, C4<0>, C4<0>; -L_0x1e1fa60 .delay 1 (30000,30000,30000) L_0x1e1fa60/d; -v0x1c4b540_0 .net *"_s10", 0 0, L_0x1e1fb20; 1 drivers -v0x1c4b620_0 .net *"_s12", 0 0, L_0x1e1fcd0; 1 drivers -v0x1c4b700_0 .net "in", 7 0, L_0x1e1da60; alias, 1 drivers -v0x1c4b7d0_0 .net "ors", 1 0, L_0x1e1f880; 1 drivers -v0x1c4b890_0 .net "out", 0 0, L_0x1e1fa60; alias, 1 drivers -L_0x1e1ec50 .part L_0x1e1da60, 0, 4; -L_0x1e1f880 .concat8 [ 1 1 0 0], L_0x1e1e940, L_0x1e1f570; -L_0x1e1f9c0 .part L_0x1e1da60, 4, 4; -L_0x1e1fb20 .part L_0x1e1f880, 0, 1; -L_0x1e1fcd0 .part L_0x1e1f880, 1, 1; -S_0x1c49bb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c499f0; +L_0x12b31d0/d .functor OR 1, L_0x12b3290, L_0x12b3440, C4<0>, C4<0>; +L_0x12b31d0 .delay 1 (30000,30000,30000) L_0x12b31d0/d; +v0x10de1f0_0 .net *"_s10", 0 0, L_0x12b3290; 1 drivers +v0x10de2d0_0 .net *"_s12", 0 0, L_0x12b3440; 1 drivers +v0x10de3b0_0 .net "in", 7 0, L_0x12b11d0; alias, 1 drivers +v0x10de480_0 .net "ors", 1 0, L_0x12b2ff0; 1 drivers +v0x10de540_0 .net "out", 0 0, L_0x12b31d0; alias, 1 drivers +L_0x12b23c0 .part L_0x12b11d0, 0, 4; +L_0x12b2ff0 .concat8 [ 1 1 0 0], L_0x12b20b0, L_0x12b2ce0; +L_0x12b3130 .part L_0x12b11d0, 4, 4; +L_0x12b3290 .part L_0x12b2ff0, 0, 1; +L_0x12b3440 .part L_0x12b2ff0, 1, 1; +S_0x10dc860 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10dc6a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e1e100/d .functor OR 1, L_0x1e1e1c0, L_0x1e1e320, C4<0>, C4<0>; -L_0x1e1e100 .delay 1 (30000,30000,30000) L_0x1e1e100/d; -L_0x1e1e550/d .functor OR 1, L_0x1e1e660, L_0x1e1e7c0, C4<0>, C4<0>; -L_0x1e1e550 .delay 1 (30000,30000,30000) L_0x1e1e550/d; -L_0x1e1e940/d .functor OR 1, L_0x1e1e9b0, L_0x1e1eb60, C4<0>, C4<0>; -L_0x1e1e940 .delay 1 (30000,30000,30000) L_0x1e1e940/d; -v0x1c49e00_0 .net *"_s0", 0 0, L_0x1e1e100; 1 drivers -v0x1c49f00_0 .net *"_s10", 0 0, L_0x1e1e660; 1 drivers -v0x1c49fe0_0 .net *"_s12", 0 0, L_0x1e1e7c0; 1 drivers -v0x1c4a0a0_0 .net *"_s14", 0 0, L_0x1e1e9b0; 1 drivers -v0x1c4a180_0 .net *"_s16", 0 0, L_0x1e1eb60; 1 drivers -v0x1c4a2b0_0 .net *"_s3", 0 0, L_0x1e1e1c0; 1 drivers -v0x1c4a390_0 .net *"_s5", 0 0, L_0x1e1e320; 1 drivers -v0x1c4a470_0 .net *"_s6", 0 0, L_0x1e1e550; 1 drivers -v0x1c4a550_0 .net "in", 3 0, L_0x1e1ec50; 1 drivers -v0x1c4a6c0_0 .net "ors", 1 0, L_0x1e1e460; 1 drivers -v0x1c4a7a0_0 .net "out", 0 0, L_0x1e1e940; 1 drivers -L_0x1e1e1c0 .part L_0x1e1ec50, 0, 1; -L_0x1e1e320 .part L_0x1e1ec50, 1, 1; -L_0x1e1e460 .concat8 [ 1 1 0 0], L_0x1e1e100, L_0x1e1e550; -L_0x1e1e660 .part L_0x1e1ec50, 2, 1; -L_0x1e1e7c0 .part L_0x1e1ec50, 3, 1; -L_0x1e1e9b0 .part L_0x1e1e460, 0, 1; -L_0x1e1eb60 .part L_0x1e1e460, 1, 1; -S_0x1c4a8c0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c499f0; +L_0x12b1870/d .functor OR 1, L_0x12b1930, L_0x12b1a90, C4<0>, C4<0>; +L_0x12b1870 .delay 1 (30000,30000,30000) L_0x12b1870/d; +L_0x12b1cc0/d .functor OR 1, L_0x12b1dd0, L_0x12b1f30, C4<0>, C4<0>; +L_0x12b1cc0 .delay 1 (30000,30000,30000) L_0x12b1cc0/d; +L_0x12b20b0/d .functor OR 1, L_0x12b2120, L_0x12b22d0, C4<0>, C4<0>; +L_0x12b20b0 .delay 1 (30000,30000,30000) L_0x12b20b0/d; +v0x10dcab0_0 .net *"_s0", 0 0, L_0x12b1870; 1 drivers +v0x10dcbb0_0 .net *"_s10", 0 0, L_0x12b1dd0; 1 drivers +v0x10dcc90_0 .net *"_s12", 0 0, L_0x12b1f30; 1 drivers +v0x10dcd50_0 .net *"_s14", 0 0, L_0x12b2120; 1 drivers +v0x10dce30_0 .net *"_s16", 0 0, L_0x12b22d0; 1 drivers +v0x10dcf60_0 .net *"_s3", 0 0, L_0x12b1930; 1 drivers +v0x10dd040_0 .net *"_s5", 0 0, L_0x12b1a90; 1 drivers +v0x10dd120_0 .net *"_s6", 0 0, L_0x12b1cc0; 1 drivers +v0x10dd200_0 .net "in", 3 0, L_0x12b23c0; 1 drivers +v0x10dd370_0 .net "ors", 1 0, L_0x12b1bd0; 1 drivers +v0x10dd450_0 .net "out", 0 0, L_0x12b20b0; 1 drivers +L_0x12b1930 .part L_0x12b23c0, 0, 1; +L_0x12b1a90 .part L_0x12b23c0, 1, 1; +L_0x12b1bd0 .concat8 [ 1 1 0 0], L_0x12b1870, L_0x12b1cc0; +L_0x12b1dd0 .part L_0x12b23c0, 2, 1; +L_0x12b1f30 .part L_0x12b23c0, 3, 1; +L_0x12b2120 .part L_0x12b1bd0, 0, 1; +L_0x12b22d0 .part L_0x12b1bd0, 1, 1; +S_0x10dd570 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10dc6a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e1ed80/d .functor OR 1, L_0x1e1edf0, L_0x1e1ef50, C4<0>, C4<0>; -L_0x1e1ed80 .delay 1 (30000,30000,30000) L_0x1e1ed80/d; -L_0x1e1f180/d .functor OR 1, L_0x1e1f290, L_0x1e1f3f0, C4<0>, C4<0>; -L_0x1e1f180 .delay 1 (30000,30000,30000) L_0x1e1f180/d; -L_0x1e1f570/d .functor OR 1, L_0x1e1f5e0, L_0x1e1f790, C4<0>, C4<0>; -L_0x1e1f570 .delay 1 (30000,30000,30000) L_0x1e1f570/d; -v0x1c4aa80_0 .net *"_s0", 0 0, L_0x1e1ed80; 1 drivers -v0x1c4ab80_0 .net *"_s10", 0 0, L_0x1e1f290; 1 drivers -v0x1c4ac60_0 .net *"_s12", 0 0, L_0x1e1f3f0; 1 drivers -v0x1c4ad20_0 .net *"_s14", 0 0, L_0x1e1f5e0; 1 drivers -v0x1c4ae00_0 .net *"_s16", 0 0, L_0x1e1f790; 1 drivers -v0x1c4af30_0 .net *"_s3", 0 0, L_0x1e1edf0; 1 drivers -v0x1c4b010_0 .net *"_s5", 0 0, L_0x1e1ef50; 1 drivers -v0x1c4b0f0_0 .net *"_s6", 0 0, L_0x1e1f180; 1 drivers -v0x1c4b1d0_0 .net "in", 3 0, L_0x1e1f9c0; 1 drivers -v0x1c4b340_0 .net "ors", 1 0, L_0x1e1f090; 1 drivers -v0x1c4b420_0 .net "out", 0 0, L_0x1e1f570; 1 drivers -L_0x1e1edf0 .part L_0x1e1f9c0, 0, 1; -L_0x1e1ef50 .part L_0x1e1f9c0, 1, 1; -L_0x1e1f090 .concat8 [ 1 1 0 0], L_0x1e1ed80, L_0x1e1f180; -L_0x1e1f290 .part L_0x1e1f9c0, 2, 1; -L_0x1e1f3f0 .part L_0x1e1f9c0, 3, 1; -L_0x1e1f5e0 .part L_0x1e1f090, 0, 1; -L_0x1e1f790 .part L_0x1e1f090, 1, 1; -S_0x1c4bd30 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c44e60; +L_0x12b24f0/d .functor OR 1, L_0x12b2560, L_0x12b26c0, C4<0>, C4<0>; +L_0x12b24f0 .delay 1 (30000,30000,30000) L_0x12b24f0/d; +L_0x12b28f0/d .functor OR 1, L_0x12b2a00, L_0x12b2b60, C4<0>, C4<0>; +L_0x12b28f0 .delay 1 (30000,30000,30000) L_0x12b28f0/d; +L_0x12b2ce0/d .functor OR 1, L_0x12b2d50, L_0x12b2f00, C4<0>, C4<0>; +L_0x12b2ce0 .delay 1 (30000,30000,30000) L_0x12b2ce0/d; +v0x10dd730_0 .net *"_s0", 0 0, L_0x12b24f0; 1 drivers +v0x10dd830_0 .net *"_s10", 0 0, L_0x12b2a00; 1 drivers +v0x10dd910_0 .net *"_s12", 0 0, L_0x12b2b60; 1 drivers +v0x10dd9d0_0 .net *"_s14", 0 0, L_0x12b2d50; 1 drivers +v0x10ddab0_0 .net *"_s16", 0 0, L_0x12b2f00; 1 drivers +v0x10ddbe0_0 .net *"_s3", 0 0, L_0x12b2560; 1 drivers +v0x10ddcc0_0 .net *"_s5", 0 0, L_0x12b26c0; 1 drivers +v0x10ddda0_0 .net *"_s6", 0 0, L_0x12b28f0; 1 drivers +v0x10dde80_0 .net "in", 3 0, L_0x12b3130; 1 drivers +v0x10ddff0_0 .net "ors", 1 0, L_0x12b2800; 1 drivers +v0x10de0d0_0 .net "out", 0 0, L_0x12b2ce0; 1 drivers +L_0x12b2560 .part L_0x12b3130, 0, 1; +L_0x12b26c0 .part L_0x12b3130, 1, 1; +L_0x12b2800 .concat8 [ 1 1 0 0], L_0x12b24f0, L_0x12b28f0; +L_0x12b2a00 .part L_0x12b3130, 2, 1; +L_0x12b2b60 .part L_0x12b3130, 3, 1; +L_0x12b2d50 .part L_0x12b2800, 0, 1; +L_0x12b2f00 .part L_0x12b2800, 1, 1; +S_0x10de9e0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10d7b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c51180_0 .net "ands", 7 0, L_0x1e19ff0; 1 drivers -v0x1c51290_0 .net "in", 7 0, L_0x1e18450; alias, 1 drivers -v0x1c51350_0 .net "out", 0 0, L_0x1e1bfc0; alias, 1 drivers -v0x1c51420_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c4bf80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c4bd30; +v0x10e3e10_0 .net "ands", 7 0, L_0x12ad760; 1 drivers +v0x10e3f20_0 .net "in", 7 0, L_0x12abbc0; alias, 1 drivers +v0x10e3fe0_0 .net "out", 0 0, L_0x12af760; alias, 1 drivers +v0x10e40b0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10dec30 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10de9e0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c4e6c0_0 .net "A", 7 0, L_0x1e18450; alias, 1 drivers -v0x1c4e7c0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c4e880_0 .net *"_s0", 0 0, L_0x1e187e0; 1 drivers -v0x1c4e940_0 .net *"_s12", 0 0, L_0x1e191a0; 1 drivers -v0x1c4ea20_0 .net *"_s16", 0 0, L_0x1e19500; 1 drivers -v0x1c4eb50_0 .net *"_s20", 0 0, L_0x1e19930; 1 drivers -v0x1c4ec30_0 .net *"_s24", 0 0, L_0x1e19c60; 1 drivers -v0x1c4ed10_0 .net *"_s28", 0 0, L_0x1e1a270; 1 drivers -v0x1c4edf0_0 .net *"_s4", 0 0, L_0x1e18b80; 1 drivers -v0x1c4ef60_0 .net *"_s8", 0 0, L_0x1e18e90; 1 drivers -v0x1c4f000_0 .net "out", 7 0, L_0x1e19ff0; alias, 1 drivers -L_0x1e188f0 .part L_0x1e18450, 0, 1; -L_0x1e18ae0 .part v0x1d6daa0_0, 0, 1; -L_0x1e18c40 .part L_0x1e18450, 1, 1; -L_0x1e18da0 .part v0x1d6daa0_0, 1, 1; -L_0x1e18f50 .part L_0x1e18450, 2, 1; -L_0x1e190b0 .part v0x1d6daa0_0, 2, 1; -L_0x1e19260 .part L_0x1e18450, 3, 1; -L_0x1e193c0 .part v0x1d6daa0_0, 3, 1; -L_0x1e195c0 .part L_0x1e18450, 4, 1; -L_0x1e19830 .part v0x1d6daa0_0, 4, 1; -L_0x1e199a0 .part L_0x1e18450, 5, 1; -L_0x1e19b00 .part v0x1d6daa0_0, 5, 1; -L_0x1e19d20 .part L_0x1e18450, 6, 1; -L_0x1e19e80 .part v0x1d6daa0_0, 6, 1; -LS_0x1e19ff0_0_0 .concat8 [ 1 1 1 1], L_0x1e187e0, L_0x1e18b80, L_0x1e18e90, L_0x1e191a0; -LS_0x1e19ff0_0_4 .concat8 [ 1 1 1 1], L_0x1e19500, L_0x1e19930, L_0x1e19c60, L_0x1e1a270; -L_0x1e19ff0 .concat8 [ 4 4 0 0], LS_0x1e19ff0_0_0, LS_0x1e19ff0_0_4; -L_0x1e1a380 .part L_0x1e18450, 7, 1; -L_0x1e1a570 .part v0x1d6daa0_0, 7, 1; -S_0x1c4c1c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4c3d0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e187e0/d .functor AND 1, L_0x1e188f0, L_0x1e18ae0, C4<1>, C4<1>; -L_0x1e187e0 .delay 1 (30000,30000,30000) L_0x1e187e0/d; -v0x1c4c4b0_0 .net *"_s0", 0 0, L_0x1e188f0; 1 drivers -v0x1c4c590_0 .net *"_s1", 0 0, L_0x1e18ae0; 1 drivers -S_0x1c4c670 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4c880 .param/l "i" 0 4 54, +C4<01>; -L_0x1e18b80/d .functor AND 1, L_0x1e18c40, L_0x1e18da0, C4<1>, C4<1>; -L_0x1e18b80 .delay 1 (30000,30000,30000) L_0x1e18b80/d; -v0x1c4c940_0 .net *"_s0", 0 0, L_0x1e18c40; 1 drivers -v0x1c4ca20_0 .net *"_s1", 0 0, L_0x1e18da0; 1 drivers -S_0x1c4cb00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4cd40 .param/l "i" 0 4 54, +C4<010>; -L_0x1e18e90/d .functor AND 1, L_0x1e18f50, L_0x1e190b0, C4<1>, C4<1>; -L_0x1e18e90 .delay 1 (30000,30000,30000) L_0x1e18e90/d; -v0x1c4cde0_0 .net *"_s0", 0 0, L_0x1e18f50; 1 drivers -v0x1c4cec0_0 .net *"_s1", 0 0, L_0x1e190b0; 1 drivers -S_0x1c4cfa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4d1b0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e191a0/d .functor AND 1, L_0x1e19260, L_0x1e193c0, C4<1>, C4<1>; -L_0x1e191a0 .delay 1 (30000,30000,30000) L_0x1e191a0/d; -v0x1c4d270_0 .net *"_s0", 0 0, L_0x1e19260; 1 drivers -v0x1c4d350_0 .net *"_s1", 0 0, L_0x1e193c0; 1 drivers -S_0x1c4d430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4d690 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e19500/d .functor AND 1, L_0x1e195c0, L_0x1e19830, C4<1>, C4<1>; -L_0x1e19500 .delay 1 (30000,30000,30000) L_0x1e19500/d; -v0x1c4d750_0 .net *"_s0", 0 0, L_0x1e195c0; 1 drivers -v0x1c4d830_0 .net *"_s1", 0 0, L_0x1e19830; 1 drivers -S_0x1c4d910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4db20 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e19930/d .functor AND 1, L_0x1e199a0, L_0x1e19b00, C4<1>, C4<1>; -L_0x1e19930 .delay 1 (30000,30000,30000) L_0x1e19930/d; -v0x1c4dbe0_0 .net *"_s0", 0 0, L_0x1e199a0; 1 drivers -v0x1c4dcc0_0 .net *"_s1", 0 0, L_0x1e19b00; 1 drivers -S_0x1c4dda0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4dfb0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e19c60/d .functor AND 1, L_0x1e19d20, L_0x1e19e80, C4<1>, C4<1>; -L_0x1e19c60 .delay 1 (30000,30000,30000) L_0x1e19c60/d; -v0x1c4e070_0 .net *"_s0", 0 0, L_0x1e19d20; 1 drivers -v0x1c4e150_0 .net *"_s1", 0 0, L_0x1e19e80; 1 drivers -S_0x1c4e230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c4bf80; - .timescale -9 -12; -P_0x1c4e440 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e1a270/d .functor AND 1, L_0x1e1a380, L_0x1e1a570, C4<1>, C4<1>; -L_0x1e1a270 .delay 1 (30000,30000,30000) L_0x1e1a270/d; -v0x1c4e500_0 .net *"_s0", 0 0, L_0x1e1a380; 1 drivers -v0x1c4e5e0_0 .net *"_s1", 0 0, L_0x1e1a570; 1 drivers -S_0x1c4f140 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c4bd30; +v0x10e1370_0 .net "A", 7 0, L_0x12abbc0; alias, 1 drivers +v0x10e1470_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10e1530_0 .net *"_s0", 0 0, L_0x12abf50; 1 drivers +v0x10e15f0_0 .net *"_s12", 0 0, L_0x12ac910; 1 drivers +v0x10e16d0_0 .net *"_s16", 0 0, L_0x12acc70; 1 drivers +v0x10e1800_0 .net *"_s20", 0 0, L_0x12ad0a0; 1 drivers +v0x10e18e0_0 .net *"_s24", 0 0, L_0x12ad3d0; 1 drivers +v0x10e19c0_0 .net *"_s28", 0 0, L_0x12ad360; 1 drivers +v0x10e1aa0_0 .net *"_s4", 0 0, L_0x12ac2f0; 1 drivers +v0x10e1c10_0 .net *"_s8", 0 0, L_0x12ac600; 1 drivers +v0x10e1cf0_0 .net "out", 7 0, L_0x12ad760; alias, 1 drivers +L_0x12ac060 .part L_0x12abbc0, 0, 1; +L_0x12ac250 .part v0x12010b0_0, 0, 1; +L_0x12ac3b0 .part L_0x12abbc0, 1, 1; +L_0x12ac510 .part v0x12010b0_0, 1, 1; +L_0x12ac6c0 .part L_0x12abbc0, 2, 1; +L_0x12ac820 .part v0x12010b0_0, 2, 1; +L_0x12ac9d0 .part L_0x12abbc0, 3, 1; +L_0x12acb30 .part v0x12010b0_0, 3, 1; +L_0x12acd30 .part L_0x12abbc0, 4, 1; +L_0x12acfa0 .part v0x12010b0_0, 4, 1; +L_0x12ad110 .part L_0x12abbc0, 5, 1; +L_0x12ad270 .part v0x12010b0_0, 5, 1; +L_0x12ad490 .part L_0x12abbc0, 6, 1; +L_0x12ad5f0 .part v0x12010b0_0, 6, 1; +LS_0x12ad760_0_0 .concat8 [ 1 1 1 1], L_0x12abf50, L_0x12ac2f0, L_0x12ac600, L_0x12ac910; +LS_0x12ad760_0_4 .concat8 [ 1 1 1 1], L_0x12acc70, L_0x12ad0a0, L_0x12ad3d0, L_0x12ad360; +L_0x12ad760 .concat8 [ 4 4 0 0], LS_0x12ad760_0_0, LS_0x12ad760_0_4; +L_0x12adb20 .part L_0x12abbc0, 7, 1; +L_0x12add10 .part v0x12010b0_0, 7, 1; +S_0x10dee70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10df080 .param/l "i" 0 4 54, +C4<00>; +L_0x12abf50/d .functor AND 1, L_0x12ac060, L_0x12ac250, C4<1>, C4<1>; +L_0x12abf50 .delay 1 (30000,30000,30000) L_0x12abf50/d; +v0x10df160_0 .net *"_s0", 0 0, L_0x12ac060; 1 drivers +v0x10df240_0 .net *"_s1", 0 0, L_0x12ac250; 1 drivers +S_0x10df320 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10df530 .param/l "i" 0 4 54, +C4<01>; +L_0x12ac2f0/d .functor AND 1, L_0x12ac3b0, L_0x12ac510, C4<1>, C4<1>; +L_0x12ac2f0 .delay 1 (30000,30000,30000) L_0x12ac2f0/d; +v0x10df5f0_0 .net *"_s0", 0 0, L_0x12ac3b0; 1 drivers +v0x10df6d0_0 .net *"_s1", 0 0, L_0x12ac510; 1 drivers +S_0x10df7b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10df9f0 .param/l "i" 0 4 54, +C4<010>; +L_0x12ac600/d .functor AND 1, L_0x12ac6c0, L_0x12ac820, C4<1>, C4<1>; +L_0x12ac600 .delay 1 (30000,30000,30000) L_0x12ac600/d; +v0x10dfa90_0 .net *"_s0", 0 0, L_0x12ac6c0; 1 drivers +v0x10dfb70_0 .net *"_s1", 0 0, L_0x12ac820; 1 drivers +S_0x10dfc50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10dfe60 .param/l "i" 0 4 54, +C4<011>; +L_0x12ac910/d .functor AND 1, L_0x12ac9d0, L_0x12acb30, C4<1>, C4<1>; +L_0x12ac910 .delay 1 (30000,30000,30000) L_0x12ac910/d; +v0x10dff20_0 .net *"_s0", 0 0, L_0x12ac9d0; 1 drivers +v0x10e0000_0 .net *"_s1", 0 0, L_0x12acb30; 1 drivers +S_0x10e00e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10e0340 .param/l "i" 0 4 54, +C4<0100>; +L_0x12acc70/d .functor AND 1, L_0x12acd30, L_0x12acfa0, C4<1>, C4<1>; +L_0x12acc70 .delay 1 (30000,30000,30000) L_0x12acc70/d; +v0x10e0400_0 .net *"_s0", 0 0, L_0x12acd30; 1 drivers +v0x10e04e0_0 .net *"_s1", 0 0, L_0x12acfa0; 1 drivers +S_0x10e05c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10e07d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ad0a0/d .functor AND 1, L_0x12ad110, L_0x12ad270, C4<1>, C4<1>; +L_0x12ad0a0 .delay 1 (30000,30000,30000) L_0x12ad0a0/d; +v0x10e0890_0 .net *"_s0", 0 0, L_0x12ad110; 1 drivers +v0x10e0970_0 .net *"_s1", 0 0, L_0x12ad270; 1 drivers +S_0x10e0a50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10e0c60 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ad3d0/d .functor AND 1, L_0x12ad490, L_0x12ad5f0, C4<1>, C4<1>; +L_0x12ad3d0 .delay 1 (30000,30000,30000) L_0x12ad3d0/d; +v0x10e0d20_0 .net *"_s0", 0 0, L_0x12ad490; 1 drivers +v0x10e0e00_0 .net *"_s1", 0 0, L_0x12ad5f0; 1 drivers +S_0x10e0ee0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10dec30; + .timescale -9 -12; +P_0x10e10f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ad360/d .functor AND 1, L_0x12adb20, L_0x12add10, C4<1>, C4<1>; +L_0x12ad360 .delay 1 (30000,30000,30000) L_0x12ad360/d; +v0x10e11b0_0 .net *"_s0", 0 0, L_0x12adb20; 1 drivers +v0x10e1290_0 .net *"_s1", 0 0, L_0x12add10; 1 drivers +S_0x10e1e50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10de9e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e1bfc0/d .functor OR 1, L_0x1e1c080, L_0x1e1c230, C4<0>, C4<0>; -L_0x1e1bfc0 .delay 1 (30000,30000,30000) L_0x1e1bfc0/d; -v0x1c50d10_0 .net *"_s10", 0 0, L_0x1e1c080; 1 drivers -v0x1c50df0_0 .net *"_s12", 0 0, L_0x1e1c230; 1 drivers -v0x1c50ed0_0 .net "in", 7 0, L_0x1e19ff0; alias, 1 drivers -v0x1c50fa0_0 .net "ors", 1 0, L_0x1e1bde0; 1 drivers -v0x1c51060_0 .net "out", 0 0, L_0x1e1bfc0; alias, 1 drivers -L_0x1e1b1b0 .part L_0x1e19ff0, 0, 4; -L_0x1e1bde0 .concat8 [ 1 1 0 0], L_0x1e1aea0, L_0x1e1bad0; -L_0x1e1bf20 .part L_0x1e19ff0, 4, 4; -L_0x1e1c080 .part L_0x1e1bde0, 0, 1; -L_0x1e1c230 .part L_0x1e1bde0, 1, 1; -S_0x1c4f350 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c4f140; +L_0x12af760/d .functor OR 1, L_0x12af820, L_0x12af9d0, C4<0>, C4<0>; +L_0x12af760 .delay 1 (30000,30000,30000) L_0x12af760/d; +v0x10e39a0_0 .net *"_s10", 0 0, L_0x12af820; 1 drivers +v0x10e3a80_0 .net *"_s12", 0 0, L_0x12af9d0; 1 drivers +v0x10e3b60_0 .net "in", 7 0, L_0x12ad760; alias, 1 drivers +v0x10e3c30_0 .net "ors", 1 0, L_0x12af580; 1 drivers +v0x10e3cf0_0 .net "out", 0 0, L_0x12af760; alias, 1 drivers +L_0x12ae950 .part L_0x12ad760, 0, 4; +L_0x12af580 .concat8 [ 1 1 0 0], L_0x12ae640, L_0x12af270; +L_0x12af6c0 .part L_0x12ad760, 4, 4; +L_0x12af820 .part L_0x12af580, 0, 1; +L_0x12af9d0 .part L_0x12af580, 1, 1; +S_0x10e2010 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10e1e50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e1a660/d .functor OR 1, L_0x1e1a720, L_0x1e1a880, C4<0>, C4<0>; -L_0x1e1a660 .delay 1 (30000,30000,30000) L_0x1e1a660/d; -L_0x1e1aab0/d .functor OR 1, L_0x1e1abc0, L_0x1e1ad20, C4<0>, C4<0>; -L_0x1e1aab0 .delay 1 (30000,30000,30000) L_0x1e1aab0/d; -L_0x1e1aea0/d .functor OR 1, L_0x1e1af10, L_0x1e1b0c0, C4<0>, C4<0>; -L_0x1e1aea0 .delay 1 (30000,30000,30000) L_0x1e1aea0/d; -v0x1c4f5a0_0 .net *"_s0", 0 0, L_0x1e1a660; 1 drivers -v0x1c4f6a0_0 .net *"_s10", 0 0, L_0x1e1abc0; 1 drivers -v0x1c4f780_0 .net *"_s12", 0 0, L_0x1e1ad20; 1 drivers -v0x1c4f870_0 .net *"_s14", 0 0, L_0x1e1af10; 1 drivers -v0x1c4f950_0 .net *"_s16", 0 0, L_0x1e1b0c0; 1 drivers -v0x1c4fa80_0 .net *"_s3", 0 0, L_0x1e1a720; 1 drivers -v0x1c4fb60_0 .net *"_s5", 0 0, L_0x1e1a880; 1 drivers -v0x1c4fc40_0 .net *"_s6", 0 0, L_0x1e1aab0; 1 drivers -v0x1c4fd20_0 .net "in", 3 0, L_0x1e1b1b0; 1 drivers -v0x1c4fe90_0 .net "ors", 1 0, L_0x1e1a9c0; 1 drivers -v0x1c4ff70_0 .net "out", 0 0, L_0x1e1aea0; 1 drivers -L_0x1e1a720 .part L_0x1e1b1b0, 0, 1; -L_0x1e1a880 .part L_0x1e1b1b0, 1, 1; -L_0x1e1a9c0 .concat8 [ 1 1 0 0], L_0x1e1a660, L_0x1e1aab0; -L_0x1e1abc0 .part L_0x1e1b1b0, 2, 1; -L_0x1e1ad20 .part L_0x1e1b1b0, 3, 1; -L_0x1e1af10 .part L_0x1e1a9c0, 0, 1; -L_0x1e1b0c0 .part L_0x1e1a9c0, 1, 1; -S_0x1c50090 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c4f140; +L_0x12ade00/d .functor OR 1, L_0x12adec0, L_0x12ae020, C4<0>, C4<0>; +L_0x12ade00 .delay 1 (30000,30000,30000) L_0x12ade00/d; +L_0x12ae250/d .functor OR 1, L_0x12ae360, L_0x12ae4c0, C4<0>, C4<0>; +L_0x12ae250 .delay 1 (30000,30000,30000) L_0x12ae250/d; +L_0x12ae640/d .functor OR 1, L_0x12ae6b0, L_0x12ae860, C4<0>, C4<0>; +L_0x12ae640 .delay 1 (30000,30000,30000) L_0x12ae640/d; +v0x10e2260_0 .net *"_s0", 0 0, L_0x12ade00; 1 drivers +v0x10e2360_0 .net *"_s10", 0 0, L_0x12ae360; 1 drivers +v0x10e2440_0 .net *"_s12", 0 0, L_0x12ae4c0; 1 drivers +v0x10e2500_0 .net *"_s14", 0 0, L_0x12ae6b0; 1 drivers +v0x10e25e0_0 .net *"_s16", 0 0, L_0x12ae860; 1 drivers +v0x10e2710_0 .net *"_s3", 0 0, L_0x12adec0; 1 drivers +v0x10e27f0_0 .net *"_s5", 0 0, L_0x12ae020; 1 drivers +v0x10e28d0_0 .net *"_s6", 0 0, L_0x12ae250; 1 drivers +v0x10e29b0_0 .net "in", 3 0, L_0x12ae950; 1 drivers +v0x10e2b20_0 .net "ors", 1 0, L_0x12ae160; 1 drivers +v0x10e2c00_0 .net "out", 0 0, L_0x12ae640; 1 drivers +L_0x12adec0 .part L_0x12ae950, 0, 1; +L_0x12ae020 .part L_0x12ae950, 1, 1; +L_0x12ae160 .concat8 [ 1 1 0 0], L_0x12ade00, L_0x12ae250; +L_0x12ae360 .part L_0x12ae950, 2, 1; +L_0x12ae4c0 .part L_0x12ae950, 3, 1; +L_0x12ae6b0 .part L_0x12ae160, 0, 1; +L_0x12ae860 .part L_0x12ae160, 1, 1; +S_0x10e2d20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10e1e50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e1b2e0/d .functor OR 1, L_0x1e1b350, L_0x1e1b4b0, C4<0>, C4<0>; -L_0x1e1b2e0 .delay 1 (30000,30000,30000) L_0x1e1b2e0/d; -L_0x1e1b6e0/d .functor OR 1, L_0x1e1b7f0, L_0x1e1b950, C4<0>, C4<0>; -L_0x1e1b6e0 .delay 1 (30000,30000,30000) L_0x1e1b6e0/d; -L_0x1e1bad0/d .functor OR 1, L_0x1e1bb40, L_0x1e1bcf0, C4<0>, C4<0>; -L_0x1e1bad0 .delay 1 (30000,30000,30000) L_0x1e1bad0/d; -v0x1c50250_0 .net *"_s0", 0 0, L_0x1e1b2e0; 1 drivers -v0x1c50350_0 .net *"_s10", 0 0, L_0x1e1b7f0; 1 drivers -v0x1c50430_0 .net *"_s12", 0 0, L_0x1e1b950; 1 drivers -v0x1c504f0_0 .net *"_s14", 0 0, L_0x1e1bb40; 1 drivers -v0x1c505d0_0 .net *"_s16", 0 0, L_0x1e1bcf0; 1 drivers -v0x1c50700_0 .net *"_s3", 0 0, L_0x1e1b350; 1 drivers -v0x1c507e0_0 .net *"_s5", 0 0, L_0x1e1b4b0; 1 drivers -v0x1c508c0_0 .net *"_s6", 0 0, L_0x1e1b6e0; 1 drivers -v0x1c509a0_0 .net "in", 3 0, L_0x1e1bf20; 1 drivers -v0x1c50b10_0 .net "ors", 1 0, L_0x1e1b5f0; 1 drivers -v0x1c50bf0_0 .net "out", 0 0, L_0x1e1bad0; 1 drivers -L_0x1e1b350 .part L_0x1e1bf20, 0, 1; -L_0x1e1b4b0 .part L_0x1e1bf20, 1, 1; -L_0x1e1b5f0 .concat8 [ 1 1 0 0], L_0x1e1b2e0, L_0x1e1b6e0; -L_0x1e1b7f0 .part L_0x1e1bf20, 2, 1; -L_0x1e1b950 .part L_0x1e1bf20, 3, 1; -L_0x1e1bb40 .part L_0x1e1b5f0, 0, 1; -L_0x1e1bcf0 .part L_0x1e1b5f0, 1, 1; -S_0x1c51500 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c44e60; +L_0x12aea80/d .functor OR 1, L_0x12aeaf0, L_0x12aec50, C4<0>, C4<0>; +L_0x12aea80 .delay 1 (30000,30000,30000) L_0x12aea80/d; +L_0x12aee80/d .functor OR 1, L_0x12aef90, L_0x12af0f0, C4<0>, C4<0>; +L_0x12aee80 .delay 1 (30000,30000,30000) L_0x12aee80/d; +L_0x12af270/d .functor OR 1, L_0x12af2e0, L_0x12af490, C4<0>, C4<0>; +L_0x12af270 .delay 1 (30000,30000,30000) L_0x12af270/d; +v0x10e2ee0_0 .net *"_s0", 0 0, L_0x12aea80; 1 drivers +v0x10e2fe0_0 .net *"_s10", 0 0, L_0x12aef90; 1 drivers +v0x10e30c0_0 .net *"_s12", 0 0, L_0x12af0f0; 1 drivers +v0x10e3180_0 .net *"_s14", 0 0, L_0x12af2e0; 1 drivers +v0x10e3260_0 .net *"_s16", 0 0, L_0x12af490; 1 drivers +v0x10e3390_0 .net *"_s3", 0 0, L_0x12aeaf0; 1 drivers +v0x10e3470_0 .net *"_s5", 0 0, L_0x12aec50; 1 drivers +v0x10e3550_0 .net *"_s6", 0 0, L_0x12aee80; 1 drivers +v0x10e3630_0 .net "in", 3 0, L_0x12af6c0; 1 drivers +v0x10e37a0_0 .net "ors", 1 0, L_0x12aed90; 1 drivers +v0x10e3880_0 .net "out", 0 0, L_0x12af270; 1 drivers +L_0x12aeaf0 .part L_0x12af6c0, 0, 1; +L_0x12aec50 .part L_0x12af6c0, 1, 1; +L_0x12aed90 .concat8 [ 1 1 0 0], L_0x12aea80, L_0x12aee80; +L_0x12aef90 .part L_0x12af6c0, 2, 1; +L_0x12af0f0 .part L_0x12af6c0, 3, 1; +L_0x12af2e0 .part L_0x12aed90, 0, 1; +L_0x12af490 .part L_0x12aed90, 1, 1; +S_0x10e4190 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10d7b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -9676,80 +9686,80 @@ S_0x1c51500 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c44e60; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e177c0/d .functor XNOR 1, L_0x1e1fec0, L_0x1e16260, C4<0>, C4<0>; -L_0x1e177c0 .delay 1 (20000,20000,20000) L_0x1e177c0/d; -L_0x1e17a30/d .functor AND 1, L_0x1e1fec0, L_0x1dc8070, C4<1>, C4<1>; -L_0x1e17a30 .delay 1 (30000,30000,30000) L_0x1e17a30/d; -L_0x1e17aa0/d .functor AND 1, L_0x1e177c0, L_0x1e16300, C4<1>, C4<1>; -L_0x1e17aa0 .delay 1 (30000,30000,30000) L_0x1e17aa0/d; -L_0x1e17c00/d .functor OR 1, L_0x1e17aa0, L_0x1e17a30, C4<0>, C4<0>; -L_0x1e17c00 .delay 1 (30000,30000,30000) L_0x1e17c00/d; -v0x1c517b0_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers -v0x1c518a0_0 .net "a_", 0 0, L_0x1e063c0; alias, 1 drivers -v0x1c51960_0 .net "b", 0 0, L_0x1e16260; alias, 1 drivers -v0x1c51a50_0 .net "b_", 0 0, L_0x1dc8070; alias, 1 drivers -v0x1c51af0_0 .net "carryin", 0 0, L_0x1e16300; alias, 1 drivers -v0x1c51c30_0 .net "eq", 0 0, L_0x1e177c0; 1 drivers -v0x1c51cf0_0 .net "lt", 0 0, L_0x1e17a30; 1 drivers -v0x1c51db0_0 .net "out", 0 0, L_0x1e17c00; 1 drivers -v0x1c51e70_0 .net "w0", 0 0, L_0x1e17aa0; 1 drivers -S_0x1c520c0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c44e60; +L_0x12aaf30/d .functor XNOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; +L_0x12aaf30 .delay 1 (20000,20000,20000) L_0x12aaf30/d; +L_0x12ab1a0/d .functor AND 1, L_0x12b3630, L_0x125b7b0, C4<1>, C4<1>; +L_0x12ab1a0 .delay 1 (30000,30000,30000) L_0x12ab1a0/d; +L_0x12ab210/d .functor AND 1, L_0x12aaf30, L_0x12a9a70, C4<1>, C4<1>; +L_0x12ab210 .delay 1 (30000,30000,30000) L_0x12ab210/d; +L_0x12ab370/d .functor OR 1, L_0x12ab210, L_0x12ab1a0, C4<0>, C4<0>; +L_0x12ab370 .delay 1 (30000,30000,30000) L_0x12ab370/d; +v0x10e4440_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers +v0x10e4530_0 .net "a_", 0 0, L_0x12a3880; alias, 1 drivers +v0x10e45f0_0 .net "b", 0 0, L_0x12a99d0; alias, 1 drivers +v0x10e46e0_0 .net "b_", 0 0, L_0x125b7b0; alias, 1 drivers +v0x10e4780_0 .net "carryin", 0 0, L_0x12a9a70; alias, 1 drivers +v0x10e48c0_0 .net "eq", 0 0, L_0x12aaf30; 1 drivers +v0x10e4980_0 .net "lt", 0 0, L_0x12ab1a0; 1 drivers +v0x10e4a40_0 .net "out", 0 0, L_0x12ab370; 1 drivers +v0x10e4b00_0 .net "w0", 0 0, L_0x12ab210; 1 drivers +S_0x10e4d50 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10d7b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e175a0/d .functor OR 1, L_0x1e170a0, L_0x1c53320, C4<0>, C4<0>; -L_0x1e175a0 .delay 1 (30000,30000,30000) L_0x1e175a0/d; -v0x1c52eb0_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers -v0x1c53000_0 .net "b", 0 0, L_0x1dc8070; alias, 1 drivers -v0x1c530c0_0 .net "c1", 0 0, L_0x1e170a0; 1 drivers -v0x1c53160_0 .net "c2", 0 0, L_0x1c53320; 1 drivers -v0x1c53230_0 .net "carryin", 0 0, L_0x1e16300; alias, 1 drivers -v0x1c533b0_0 .net "carryout", 0 0, L_0x1e175a0; 1 drivers -v0x1c53450_0 .net "s1", 0 0, L_0x1e16fe0; 1 drivers -v0x1c534f0_0 .net "sum", 0 0, L_0x1e17200; 1 drivers -S_0x1c52310 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c520c0; +L_0x12aad10/d .functor OR 1, L_0x12aa810, L_0x10e5fb0, C4<0>, C4<0>; +L_0x12aad10 .delay 1 (30000,30000,30000) L_0x12aad10/d; +v0x10e5b40_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers +v0x10e5c90_0 .net "b", 0 0, L_0x125b7b0; alias, 1 drivers +v0x10e5d50_0 .net "c1", 0 0, L_0x12aa810; 1 drivers +v0x10e5df0_0 .net "c2", 0 0, L_0x10e5fb0; 1 drivers +v0x10e5ec0_0 .net "carryin", 0 0, L_0x12a9a70; alias, 1 drivers +v0x10e6040_0 .net "carryout", 0 0, L_0x12aad10; 1 drivers +v0x10e60e0_0 .net "s1", 0 0, L_0x12aa750; 1 drivers +v0x10e6180_0 .net "sum", 0 0, L_0x12aa970; 1 drivers +S_0x10e4fa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10e4d50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e16fe0/d .functor XOR 1, L_0x1e1fec0, L_0x1dc8070, C4<0>, C4<0>; -L_0x1e16fe0 .delay 1 (30000,30000,30000) L_0x1e16fe0/d; -L_0x1e170a0/d .functor AND 1, L_0x1e1fec0, L_0x1dc8070, C4<1>, C4<1>; -L_0x1e170a0 .delay 1 (30000,30000,30000) L_0x1e170a0/d; -v0x1c52570_0 .net "a", 0 0, L_0x1e1fec0; alias, 1 drivers -v0x1c52630_0 .net "b", 0 0, L_0x1dc8070; alias, 1 drivers -v0x1c526f0_0 .net "carryout", 0 0, L_0x1e170a0; alias, 1 drivers -v0x1c52790_0 .net "sum", 0 0, L_0x1e16fe0; alias, 1 drivers -S_0x1c528c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c520c0; +L_0x12aa750/d .functor XOR 1, L_0x12b3630, L_0x125b7b0, C4<0>, C4<0>; +L_0x12aa750 .delay 1 (30000,30000,30000) L_0x12aa750/d; +L_0x12aa810/d .functor AND 1, L_0x12b3630, L_0x125b7b0, C4<1>, C4<1>; +L_0x12aa810 .delay 1 (30000,30000,30000) L_0x12aa810/d; +v0x10e5200_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers +v0x10e52c0_0 .net "b", 0 0, L_0x125b7b0; alias, 1 drivers +v0x10e5380_0 .net "carryout", 0 0, L_0x12aa810; alias, 1 drivers +v0x10e5420_0 .net "sum", 0 0, L_0x12aa750; alias, 1 drivers +S_0x10e5550 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10e4d50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e17200/d .functor XOR 1, L_0x1e16fe0, L_0x1e16300, C4<0>, C4<0>; -L_0x1e17200 .delay 1 (30000,30000,30000) L_0x1e17200/d; -L_0x1c53320/d .functor AND 1, L_0x1e16fe0, L_0x1e16300, C4<1>, C4<1>; -L_0x1c53320 .delay 1 (30000,30000,30000) L_0x1c53320/d; -v0x1c52b20_0 .net "a", 0 0, L_0x1e16fe0; alias, 1 drivers -v0x1c52bf0_0 .net "b", 0 0, L_0x1e16300; alias, 1 drivers -v0x1c52c90_0 .net "carryout", 0 0, L_0x1c53320; alias, 1 drivers -v0x1c52d60_0 .net "sum", 0 0, L_0x1e17200; alias, 1 drivers -S_0x1c54910 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c44b90; - .timescale -9 -12; -L_0x7f72592db338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db380 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e1ff60/d .functor OR 1, L_0x7f72592db338, L_0x7f72592db380, C4<0>, C4<0>; -L_0x1e1ff60 .delay 1 (30000,30000,30000) L_0x1e1ff60/d; -v0x1c54b00_0 .net/2u *"_s0", 0 0, L_0x7f72592db338; 1 drivers -v0x1c54be0_0 .net/2u *"_s2", 0 0, L_0x7f72592db380; 1 drivers -S_0x1c54cc0 .scope generate, "alu_slices[18]" "alu_slices[18]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c54ed0 .param/l "i" 0 3 37, +C4<010010>; -S_0x1c54f90 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c54cc0; +L_0x12aa970/d .functor XOR 1, L_0x12aa750, L_0x12a9a70, C4<0>, C4<0>; +L_0x12aa970 .delay 1 (30000,30000,30000) L_0x12aa970/d; +L_0x10e5fb0/d .functor AND 1, L_0x12aa750, L_0x12a9a70, C4<1>, C4<1>; +L_0x10e5fb0 .delay 1 (30000,30000,30000) L_0x10e5fb0/d; +v0x10e57b0_0 .net "a", 0 0, L_0x12aa750; alias, 1 drivers +v0x10e5880_0 .net "b", 0 0, L_0x12a9a70; alias, 1 drivers +v0x10e5920_0 .net "carryout", 0 0, L_0x10e5fb0; alias, 1 drivers +v0x10e59f0_0 .net "sum", 0 0, L_0x12aa970; alias, 1 drivers +S_0x10e75a0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10d7840; + .timescale -9 -12; +L_0x2b0ab3d06338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06380 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b36d0/d .functor OR 1, L_0x2b0ab3d06338, L_0x2b0ab3d06380, C4<0>, C4<0>; +L_0x12b36d0 .delay 1 (30000,30000,30000) L_0x12b36d0/d; +v0x10e7790_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06338; 1 drivers +v0x10e7870_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06380; 1 drivers +S_0x10e7950 .scope generate, "alu_slices[18]" "alu_slices[18]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x10e7b60 .param/l "i" 0 3 41, +C4<010010>; +S_0x10e7c20 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10e7950; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -9758,445 +9768,445 @@ S_0x1c54f90 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c54cc0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e20280/d .functor NOT 1, L_0x1e29ab0, C4<0>, C4<0>, C4<0>; -L_0x1e20280 .delay 1 (10000,10000,10000) L_0x1e20280/d; -L_0x1e203e0/d .functor NOT 1, L_0x1e29c10, C4<0>, C4<0>, C4<0>; -L_0x1e203e0 .delay 1 (10000,10000,10000) L_0x1e203e0/d; -L_0x1e21320/d .functor XOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; -L_0x1e21320 .delay 1 (30000,30000,30000) L_0x1e21320/d; -L_0x7f72592db3c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db410 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e219d0/d .functor OR 1, L_0x7f72592db3c8, L_0x7f72592db410, C4<0>, C4<0>; -L_0x1e219d0 .delay 1 (30000,30000,30000) L_0x1e219d0/d; -L_0x1e21bd0/d .functor AND 1, L_0x1e29ab0, L_0x1e29c10, C4<1>, C4<1>; -L_0x1e21bd0 .delay 1 (30000,30000,30000) L_0x1e21bd0/d; -L_0x1e21c90/d .functor NAND 1, L_0x1e29ab0, L_0x1e29c10, C4<1>, C4<1>; -L_0x1e21c90 .delay 1 (20000,20000,20000) L_0x1e21c90/d; -L_0x1e21df0/d .functor XOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; -L_0x1e21df0 .delay 1 (20000,20000,20000) L_0x1e21df0/d; -L_0x1e222a0/d .functor OR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; -L_0x1e222a0 .delay 1 (30000,30000,30000) L_0x1e222a0/d; -L_0x1e299b0/d .functor NOT 1, L_0x1e25c10, C4<0>, C4<0>, C4<0>; -L_0x1e299b0 .delay 1 (10000,10000,10000) L_0x1e299b0/d; -v0x1c636c0_0 .net "A", 0 0, L_0x1e29ab0; 1 drivers -v0x1c63780_0 .net "A_", 0 0, L_0x1e20280; 1 drivers -v0x1c63840_0 .net "B", 0 0, L_0x1e29c10; 1 drivers -v0x1c63910_0 .net "B_", 0 0, L_0x1e203e0; 1 drivers -v0x1c639b0_0 .net *"_s12", 0 0, L_0x1e219d0; 1 drivers -v0x1c63aa0_0 .net/2s *"_s14", 0 0, L_0x7f72592db3c8; 1 drivers -v0x1c63b60_0 .net/2s *"_s16", 0 0, L_0x7f72592db410; 1 drivers -v0x1c63c40_0 .net *"_s18", 0 0, L_0x1e21bd0; 1 drivers -v0x1c63d20_0 .net *"_s20", 0 0, L_0x1e21c90; 1 drivers -v0x1c63e90_0 .net *"_s22", 0 0, L_0x1e21df0; 1 drivers -v0x1c63f70_0 .net *"_s24", 0 0, L_0x1e222a0; 1 drivers -o0x7f7259380268 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c64050_0 name=_s30 -o0x7f7259380298 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c64130_0 name=_s32 -v0x1c64210_0 .net *"_s8", 0 0, L_0x1e21320; 1 drivers -v0x1c642f0_0 .net "carryin", 0 0, L_0x1e20020; 1 drivers -v0x1c64390_0 .net "carryout", 0 0, L_0x1e29650; 1 drivers -v0x1c64430_0 .net "carryouts", 7 0, L_0x1ec0990; 1 drivers -v0x1c645e0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c64680_0 .net "result", 0 0, L_0x1e25c10; 1 drivers -v0x1c64770_0 .net "results", 7 0, L_0x1e22070; 1 drivers -v0x1c64880_0 .net "zero", 0 0, L_0x1e299b0; 1 drivers -LS_0x1e22070_0_0 .concat8 [ 1 1 1 1], L_0x1e20840, L_0x1e20e70, L_0x1e21320, L_0x1e219d0; -LS_0x1e22070_0_4 .concat8 [ 1 1 1 1], L_0x1e21bd0, L_0x1e21c90, L_0x1e21df0, L_0x1e222a0; -L_0x1e22070 .concat8 [ 4 4 0 0], LS_0x1e22070_0_0, LS_0x1e22070_0_4; -LS_0x1ec0990_0_0 .concat [ 1 1 1 1], L_0x1e20af0, L_0x1e211c0, o0x7f7259380268, L_0x1e21820; -LS_0x1ec0990_0_4 .concat [ 4 0 0 0], o0x7f7259380298; -L_0x1ec0990 .concat [ 4 4 0 0], LS_0x1ec0990_0_0, LS_0x1ec0990_0_4; -S_0x1c55210 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c54f90; +L_0x12b39f0/d .functor NOT 1, L_0x12bd310, C4<0>, C4<0>, C4<0>; +L_0x12b39f0 .delay 1 (10000,10000,10000) L_0x12b39f0/d; +L_0x12b3b50/d .functor NOT 1, L_0x12bd470, C4<0>, C4<0>, C4<0>; +L_0x12b3b50 .delay 1 (10000,10000,10000) L_0x12b3b50/d; +L_0x12b4a90/d .functor XOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; +L_0x12b4a90 .delay 1 (30000,30000,30000) L_0x12b4a90/d; +L_0x2b0ab3d063c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06410 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12b5140/d .functor OR 1, L_0x2b0ab3d063c8, L_0x2b0ab3d06410, C4<0>, C4<0>; +L_0x12b5140 .delay 1 (30000,30000,30000) L_0x12b5140/d; +L_0x12b5340/d .functor AND 1, L_0x12bd310, L_0x12bd470, C4<1>, C4<1>; +L_0x12b5340 .delay 1 (30000,30000,30000) L_0x12b5340/d; +L_0x12b5400/d .functor NAND 1, L_0x12bd310, L_0x12bd470, C4<1>, C4<1>; +L_0x12b5400 .delay 1 (20000,20000,20000) L_0x12b5400/d; +L_0x12b5560/d .functor XOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; +L_0x12b5560 .delay 1 (20000,20000,20000) L_0x12b5560/d; +L_0x12b5a10/d .functor OR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; +L_0x12b5a10 .delay 1 (30000,30000,30000) L_0x12b5a10/d; +L_0x12bd210/d .functor NOT 1, L_0x12b93e0, C4<0>, C4<0>, C4<0>; +L_0x12bd210 .delay 1 (10000,10000,10000) L_0x12bd210/d; +v0x10f6350_0 .net "A", 0 0, L_0x12bd310; 1 drivers +v0x10f6410_0 .net "A_", 0 0, L_0x12b39f0; 1 drivers +v0x10f64d0_0 .net "B", 0 0, L_0x12bd470; 1 drivers +v0x10f65a0_0 .net "B_", 0 0, L_0x12b3b50; 1 drivers +v0x10f6640_0 .net *"_s12", 0 0, L_0x12b5140; 1 drivers +v0x10f6730_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d063c8; 1 drivers +v0x10f67f0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06410; 1 drivers +v0x10f68d0_0 .net *"_s18", 0 0, L_0x12b5340; 1 drivers +v0x10f69b0_0 .net *"_s20", 0 0, L_0x12b5400; 1 drivers +v0x10f6b20_0 .net *"_s22", 0 0, L_0x12b5560; 1 drivers +v0x10f6c00_0 .net *"_s24", 0 0, L_0x12b5a10; 1 drivers +o0x2b0ab3ccf268 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x10f6ce0_0 name=_s30 +o0x2b0ab3ccf298 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x10f6dc0_0 name=_s32 +v0x10f6ea0_0 .net *"_s8", 0 0, L_0x12b4a90; 1 drivers +v0x10f6f80_0 .net "carryin", 0 0, L_0x12b3790; 1 drivers +v0x10f7020_0 .net "carryout", 0 0, L_0x12bceb0; 1 drivers +v0x10f70c0_0 .net "carryouts", 7 0, L_0x1354cc0; 1 drivers +v0x10f7270_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10f7310_0 .net "result", 0 0, L_0x12b93e0; 1 drivers +v0x10f7400_0 .net "results", 7 0, L_0x12b57e0; 1 drivers +v0x10f7510_0 .net "zero", 0 0, L_0x12bd210; 1 drivers +LS_0x12b57e0_0_0 .concat8 [ 1 1 1 1], L_0x12ad6e0, L_0x12b45e0, L_0x12b4a90, L_0x12b5140; +LS_0x12b57e0_0_4 .concat8 [ 1 1 1 1], L_0x12b5340, L_0x12b5400, L_0x12b5560, L_0x12b5a10; +L_0x12b57e0 .concat8 [ 4 4 0 0], LS_0x12b57e0_0_0, LS_0x12b57e0_0_4; +LS_0x1354cc0_0_0 .concat [ 1 1 1 1], L_0x12b4260, L_0x12b4930, o0x2b0ab3ccf268, L_0x12b4f90; +LS_0x1354cc0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ccf298; +L_0x1354cc0 .concat [ 4 4 0 0], LS_0x1354cc0_0_0, LS_0x1354cc0_0_4; +S_0x10e7ea0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10e7c20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e20af0/d .functor OR 1, L_0x1e205d0, L_0x1e20990, C4<0>, C4<0>; -L_0x1e20af0 .delay 1 (30000,30000,30000) L_0x1e20af0/d; -v0x1c56040_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers -v0x1c56100_0 .net "b", 0 0, L_0x1e29c10; alias, 1 drivers -v0x1c561d0_0 .net "c1", 0 0, L_0x1e205d0; 1 drivers -v0x1c562d0_0 .net "c2", 0 0, L_0x1e20990; 1 drivers -v0x1c563a0_0 .net "carryin", 0 0, L_0x1e20020; alias, 1 drivers -v0x1c56490_0 .net "carryout", 0 0, L_0x1e20af0; 1 drivers -v0x1c56530_0 .net "s1", 0 0, L_0x1e19f70; 1 drivers -v0x1c56620_0 .net "sum", 0 0, L_0x1e20840; 1 drivers -S_0x1c55480 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c55210; +L_0x12b4260/d .functor OR 1, L_0x12b3e00, L_0x12b4100, C4<0>, C4<0>; +L_0x12b4260 .delay 1 (30000,30000,30000) L_0x12b4260/d; +v0x10e8ce0_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers +v0x10e8da0_0 .net "b", 0 0, L_0x12bd470; alias, 1 drivers +v0x10e8e70_0 .net "c1", 0 0, L_0x12b3e00; 1 drivers +v0x10e8f70_0 .net "c2", 0 0, L_0x12b4100; 1 drivers +v0x10e9040_0 .net "carryin", 0 0, L_0x12b3790; alias, 1 drivers +v0x10e9130_0 .net "carryout", 0 0, L_0x12b4260; 1 drivers +v0x10e91d0_0 .net "s1", 0 0, L_0x12b3d40; 1 drivers +v0x10e92c0_0 .net "sum", 0 0, L_0x12ad6e0; 1 drivers +S_0x10e80f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10e7ea0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e19f70/d .functor XOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; -L_0x1e19f70 .delay 1 (30000,30000,30000) L_0x1e19f70/d; -L_0x1e205d0/d .functor AND 1, L_0x1e29ab0, L_0x1e29c10, C4<1>, C4<1>; -L_0x1e205d0 .delay 1 (30000,30000,30000) L_0x1e205d0/d; -v0x1c556e0_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers -v0x1c557c0_0 .net "b", 0 0, L_0x1e29c10; alias, 1 drivers -v0x1c55880_0 .net "carryout", 0 0, L_0x1e205d0; alias, 1 drivers -v0x1c55920_0 .net "sum", 0 0, L_0x1e19f70; alias, 1 drivers -S_0x1c55a60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c55210; +L_0x12b3d40/d .functor XOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; +L_0x12b3d40 .delay 1 (30000,30000,30000) L_0x12b3d40/d; +L_0x12b3e00/d .functor AND 1, L_0x12bd310, L_0x12bd470, C4<1>, C4<1>; +L_0x12b3e00 .delay 1 (30000,30000,30000) L_0x12b3e00/d; +v0x10e8330_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers +v0x10e83f0_0 .net "b", 0 0, L_0x12bd470; alias, 1 drivers +v0x10e84d0_0 .net "carryout", 0 0, L_0x12b3e00; alias, 1 drivers +v0x10e8570_0 .net "sum", 0 0, L_0x12b3d40; alias, 1 drivers +S_0x10e86e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10e7ea0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e20840/d .functor XOR 1, L_0x1e19f70, L_0x1e20020, C4<0>, C4<0>; -L_0x1e20840 .delay 1 (30000,30000,30000) L_0x1e20840/d; -L_0x1e20990/d .functor AND 1, L_0x1e19f70, L_0x1e20020, C4<1>, C4<1>; -L_0x1e20990 .delay 1 (30000,30000,30000) L_0x1e20990/d; -v0x1c55cc0_0 .net "a", 0 0, L_0x1e19f70; alias, 1 drivers -v0x1c55d60_0 .net "b", 0 0, L_0x1e20020; alias, 1 drivers -v0x1c55e00_0 .net "carryout", 0 0, L_0x1e20990; alias, 1 drivers -v0x1c55ed0_0 .net "sum", 0 0, L_0x1e20840; alias, 1 drivers -S_0x1c566f0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c54f90; +L_0x12ad6e0/d .functor XOR 1, L_0x12b3d40, L_0x12b3790, C4<0>, C4<0>; +L_0x12ad6e0 .delay 1 (30000,30000,30000) L_0x12ad6e0/d; +L_0x12b4100/d .functor AND 1, L_0x12b3d40, L_0x12b3790, C4<1>, C4<1>; +L_0x12b4100 .delay 1 (30000,30000,30000) L_0x12b4100/d; +v0x10e8940_0 .net "a", 0 0, L_0x12b3d40; alias, 1 drivers +v0x10e8a00_0 .net "b", 0 0, L_0x12b3790; alias, 1 drivers +v0x10e8aa0_0 .net "carryout", 0 0, L_0x12b4100; alias, 1 drivers +v0x10e8b70_0 .net "sum", 0 0, L_0x12ad6e0; alias, 1 drivers +S_0x10e9390 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10e7c20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c5bae0_0 .net "ands", 7 0, L_0x1e27650; 1 drivers -v0x1c5bbf0_0 .net "in", 7 0, L_0x1ec0990; alias, 1 drivers -v0x1c5bcb0_0 .net "out", 0 0, L_0x1e29650; alias, 1 drivers -v0x1c5bd80_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c56910 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c566f0; +v0x10ee770_0 .net "ands", 7 0, L_0x12baeb0; 1 drivers +v0x10ee880_0 .net "in", 7 0, L_0x1354cc0; alias, 1 drivers +v0x10ee940_0 .net "out", 0 0, L_0x12bceb0; alias, 1 drivers +v0x10eea10_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10e95d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10e9390; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c59040_0 .net "A", 7 0, L_0x1ec0990; alias, 1 drivers -v0x1c59140_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c59200_0 .net *"_s0", 0 0, L_0x1e25f70; 1 drivers -v0x1c592c0_0 .net *"_s12", 0 0, L_0x1e268e0; 1 drivers -v0x1c593a0_0 .net *"_s16", 0 0, L_0x1e26c40; 1 drivers -v0x1c594d0_0 .net *"_s20", 0 0, L_0x1e26f50; 1 drivers -v0x1c595b0_0 .net *"_s24", 0 0, L_0x1e27340; 1 drivers -v0x1c59690_0 .net *"_s28", 0 0, L_0x1e272d0; 1 drivers -v0x1c59770_0 .net *"_s4", 0 0, L_0x1e26280; 1 drivers -v0x1c598e0_0 .net *"_s8", 0 0, L_0x1e265d0; 1 drivers -v0x1c599c0_0 .net "out", 7 0, L_0x1e27650; alias, 1 drivers -L_0x1e26030 .part L_0x1ec0990, 0, 1; -L_0x1e26190 .part v0x1d6daa0_0, 0, 1; -L_0x1e26340 .part L_0x1ec0990, 1, 1; -L_0x1e26530 .part v0x1d6daa0_0, 1, 1; -L_0x1e26690 .part L_0x1ec0990, 2, 1; -L_0x1e267f0 .part v0x1d6daa0_0, 2, 1; -L_0x1e269a0 .part L_0x1ec0990, 3, 1; -L_0x1e26b00 .part v0x1d6daa0_0, 3, 1; -L_0x1e26d00 .part L_0x1ec0990, 4, 1; -L_0x1e26e60 .part v0x1d6daa0_0, 4, 1; -L_0x1e26fc0 .part L_0x1ec0990, 5, 1; -L_0x1e27230 .part v0x1d6daa0_0, 5, 1; -L_0x1e27400 .part L_0x1ec0990, 6, 1; -L_0x1e27560 .part v0x1d6daa0_0, 6, 1; -LS_0x1e27650_0_0 .concat8 [ 1 1 1 1], L_0x1e25f70, L_0x1e26280, L_0x1e265d0, L_0x1e268e0; -LS_0x1e27650_0_4 .concat8 [ 1 1 1 1], L_0x1e26c40, L_0x1e26f50, L_0x1e27340, L_0x1e272d0; -L_0x1e27650 .concat8 [ 4 4 0 0], LS_0x1e27650_0_0, LS_0x1e27650_0_4; -L_0x1e27a10 .part L_0x1ec0990, 7, 1; -L_0x1e27c00 .part v0x1d6daa0_0, 7, 1; -S_0x1c56b70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c56d80 .param/l "i" 0 4 54, +C4<00>; -L_0x1e25f70/d .functor AND 1, L_0x1e26030, L_0x1e26190, C4<1>, C4<1>; -L_0x1e25f70 .delay 1 (30000,30000,30000) L_0x1e25f70/d; -v0x1c56e60_0 .net *"_s0", 0 0, L_0x1e26030; 1 drivers -v0x1c56f40_0 .net *"_s1", 0 0, L_0x1e26190; 1 drivers -S_0x1c57020 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c57230 .param/l "i" 0 4 54, +C4<01>; -L_0x1e26280/d .functor AND 1, L_0x1e26340, L_0x1e26530, C4<1>, C4<1>; -L_0x1e26280 .delay 1 (30000,30000,30000) L_0x1e26280/d; -v0x1c572f0_0 .net *"_s0", 0 0, L_0x1e26340; 1 drivers -v0x1c573d0_0 .net *"_s1", 0 0, L_0x1e26530; 1 drivers -S_0x1c574b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c576c0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e265d0/d .functor AND 1, L_0x1e26690, L_0x1e267f0, C4<1>, C4<1>; -L_0x1e265d0 .delay 1 (30000,30000,30000) L_0x1e265d0/d; -v0x1c57760_0 .net *"_s0", 0 0, L_0x1e26690; 1 drivers -v0x1c57840_0 .net *"_s1", 0 0, L_0x1e267f0; 1 drivers -S_0x1c57920 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c57b30 .param/l "i" 0 4 54, +C4<011>; -L_0x1e268e0/d .functor AND 1, L_0x1e269a0, L_0x1e26b00, C4<1>, C4<1>; -L_0x1e268e0 .delay 1 (30000,30000,30000) L_0x1e268e0/d; -v0x1c57bf0_0 .net *"_s0", 0 0, L_0x1e269a0; 1 drivers -v0x1c57cd0_0 .net *"_s1", 0 0, L_0x1e26b00; 1 drivers -S_0x1c57db0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c58010 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e26c40/d .functor AND 1, L_0x1e26d00, L_0x1e26e60, C4<1>, C4<1>; -L_0x1e26c40 .delay 1 (30000,30000,30000) L_0x1e26c40/d; -v0x1c580d0_0 .net *"_s0", 0 0, L_0x1e26d00; 1 drivers -v0x1c581b0_0 .net *"_s1", 0 0, L_0x1e26e60; 1 drivers -S_0x1c58290 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c584a0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e26f50/d .functor AND 1, L_0x1e26fc0, L_0x1e27230, C4<1>, C4<1>; -L_0x1e26f50 .delay 1 (30000,30000,30000) L_0x1e26f50/d; -v0x1c58560_0 .net *"_s0", 0 0, L_0x1e26fc0; 1 drivers -v0x1c58640_0 .net *"_s1", 0 0, L_0x1e27230; 1 drivers -S_0x1c58720 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c58930 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e27340/d .functor AND 1, L_0x1e27400, L_0x1e27560, C4<1>, C4<1>; -L_0x1e27340 .delay 1 (30000,30000,30000) L_0x1e27340/d; -v0x1c589f0_0 .net *"_s0", 0 0, L_0x1e27400; 1 drivers -v0x1c58ad0_0 .net *"_s1", 0 0, L_0x1e27560; 1 drivers -S_0x1c58bb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c56910; - .timescale -9 -12; -P_0x1c58dc0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e272d0/d .functor AND 1, L_0x1e27a10, L_0x1e27c00, C4<1>, C4<1>; -L_0x1e272d0 .delay 1 (30000,30000,30000) L_0x1e272d0/d; -v0x1c58e80_0 .net *"_s0", 0 0, L_0x1e27a10; 1 drivers -v0x1c58f60_0 .net *"_s1", 0 0, L_0x1e27c00; 1 drivers -S_0x1c59b20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c566f0; +v0x10ebd00_0 .net "A", 7 0, L_0x1354cc0; alias, 1 drivers +v0x10ebe00_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10ebec0_0 .net *"_s0", 0 0, L_0x12b9740; 1 drivers +v0x10ebf80_0 .net *"_s12", 0 0, L_0x12ba0e0; 1 drivers +v0x10ec060_0 .net *"_s16", 0 0, L_0x12ba440; 1 drivers +v0x10ec190_0 .net *"_s20", 0 0, L_0x12ba780; 1 drivers +v0x10ec270_0 .net *"_s24", 0 0, L_0x12baba0; 1 drivers +v0x10ec350_0 .net *"_s28", 0 0, L_0x12bab30; 1 drivers +v0x10ec430_0 .net *"_s4", 0 0, L_0x12b9a50; 1 drivers +v0x10ec5a0_0 .net *"_s8", 0 0, L_0x12b9da0; 1 drivers +v0x10ec680_0 .net "out", 7 0, L_0x12baeb0; alias, 1 drivers +L_0x12b9800 .part L_0x1354cc0, 0, 1; +L_0x12b9960 .part v0x12010b0_0, 0, 1; +L_0x12b9b10 .part L_0x1354cc0, 1, 1; +L_0x12b9d00 .part v0x12010b0_0, 1, 1; +L_0x12b9e90 .part L_0x1354cc0, 2, 1; +L_0x12b9ff0 .part v0x12010b0_0, 2, 1; +L_0x12ba1a0 .part L_0x1354cc0, 3, 1; +L_0x12ba300 .part v0x12010b0_0, 3, 1; +L_0x12ba530 .part L_0x1354cc0, 4, 1; +L_0x12ba690 .part v0x12010b0_0, 4, 1; +L_0x12ba820 .part L_0x1354cc0, 5, 1; +L_0x12baa90 .part v0x12010b0_0, 5, 1; +L_0x12bac60 .part L_0x1354cc0, 6, 1; +L_0x12badc0 .part v0x12010b0_0, 6, 1; +LS_0x12baeb0_0_0 .concat8 [ 1 1 1 1], L_0x12b9740, L_0x12b9a50, L_0x12b9da0, L_0x12ba0e0; +LS_0x12baeb0_0_4 .concat8 [ 1 1 1 1], L_0x12ba440, L_0x12ba780, L_0x12baba0, L_0x12bab30; +L_0x12baeb0 .concat8 [ 4 4 0 0], LS_0x12baeb0_0_0, LS_0x12baeb0_0_4; +L_0x12bb270 .part L_0x1354cc0, 7, 1; +L_0x12bb460 .part v0x12010b0_0, 7, 1; +S_0x10e9830 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10e9a40 .param/l "i" 0 4 54, +C4<00>; +L_0x12b9740/d .functor AND 1, L_0x12b9800, L_0x12b9960, C4<1>, C4<1>; +L_0x12b9740 .delay 1 (30000,30000,30000) L_0x12b9740/d; +v0x10e9b20_0 .net *"_s0", 0 0, L_0x12b9800; 1 drivers +v0x10e9c00_0 .net *"_s1", 0 0, L_0x12b9960; 1 drivers +S_0x10e9ce0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10e9ef0 .param/l "i" 0 4 54, +C4<01>; +L_0x12b9a50/d .functor AND 1, L_0x12b9b10, L_0x12b9d00, C4<1>, C4<1>; +L_0x12b9a50 .delay 1 (30000,30000,30000) L_0x12b9a50/d; +v0x10e9fb0_0 .net *"_s0", 0 0, L_0x12b9b10; 1 drivers +v0x10ea090_0 .net *"_s1", 0 0, L_0x12b9d00; 1 drivers +S_0x10ea170 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10ea380 .param/l "i" 0 4 54, +C4<010>; +L_0x12b9da0/d .functor AND 1, L_0x12b9e90, L_0x12b9ff0, C4<1>, C4<1>; +L_0x12b9da0 .delay 1 (30000,30000,30000) L_0x12b9da0/d; +v0x10ea420_0 .net *"_s0", 0 0, L_0x12b9e90; 1 drivers +v0x10ea500_0 .net *"_s1", 0 0, L_0x12b9ff0; 1 drivers +S_0x10ea5e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10ea7f0 .param/l "i" 0 4 54, +C4<011>; +L_0x12ba0e0/d .functor AND 1, L_0x12ba1a0, L_0x12ba300, C4<1>, C4<1>; +L_0x12ba0e0 .delay 1 (30000,30000,30000) L_0x12ba0e0/d; +v0x10ea8b0_0 .net *"_s0", 0 0, L_0x12ba1a0; 1 drivers +v0x10ea990_0 .net *"_s1", 0 0, L_0x12ba300; 1 drivers +S_0x10eaa70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10eacd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12ba440/d .functor AND 1, L_0x12ba530, L_0x12ba690, C4<1>, C4<1>; +L_0x12ba440 .delay 1 (30000,30000,30000) L_0x12ba440/d; +v0x10ead90_0 .net *"_s0", 0 0, L_0x12ba530; 1 drivers +v0x10eae70_0 .net *"_s1", 0 0, L_0x12ba690; 1 drivers +S_0x10eaf50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10eb160 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ba780/d .functor AND 1, L_0x12ba820, L_0x12baa90, C4<1>, C4<1>; +L_0x12ba780 .delay 1 (30000,30000,30000) L_0x12ba780/d; +v0x10eb220_0 .net *"_s0", 0 0, L_0x12ba820; 1 drivers +v0x10eb300_0 .net *"_s1", 0 0, L_0x12baa90; 1 drivers +S_0x10eb3e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10eb5f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12baba0/d .functor AND 1, L_0x12bac60, L_0x12badc0, C4<1>, C4<1>; +L_0x12baba0 .delay 1 (30000,30000,30000) L_0x12baba0/d; +v0x10eb6b0_0 .net *"_s0", 0 0, L_0x12bac60; 1 drivers +v0x10eb790_0 .net *"_s1", 0 0, L_0x12badc0; 1 drivers +S_0x10eb870 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10e95d0; + .timescale -9 -12; +P_0x10eba80 .param/l "i" 0 4 54, +C4<0111>; +L_0x12bab30/d .functor AND 1, L_0x12bb270, L_0x12bb460, C4<1>, C4<1>; +L_0x12bab30 .delay 1 (30000,30000,30000) L_0x12bab30/d; +v0x10ebb40_0 .net *"_s0", 0 0, L_0x12bb270; 1 drivers +v0x10ebc20_0 .net *"_s1", 0 0, L_0x12bb460; 1 drivers +S_0x10ec7e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10e9390; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e29650/d .functor OR 1, L_0x1e29710, L_0x1e298c0, C4<0>, C4<0>; -L_0x1e29650 .delay 1 (30000,30000,30000) L_0x1e29650/d; -v0x1c5b670_0 .net *"_s10", 0 0, L_0x1e29710; 1 drivers -v0x1c5b750_0 .net *"_s12", 0 0, L_0x1e298c0; 1 drivers -v0x1c5b830_0 .net "in", 7 0, L_0x1e27650; alias, 1 drivers -v0x1c5b900_0 .net "ors", 1 0, L_0x1e29470; 1 drivers -v0x1c5b9c0_0 .net "out", 0 0, L_0x1e29650; alias, 1 drivers -L_0x1e28840 .part L_0x1e27650, 0, 4; -L_0x1e29470 .concat8 [ 1 1 0 0], L_0x1e28530, L_0x1e29160; -L_0x1e295b0 .part L_0x1e27650, 4, 4; -L_0x1e29710 .part L_0x1e29470, 0, 1; -L_0x1e298c0 .part L_0x1e29470, 1, 1; -S_0x1c59ce0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c59b20; +L_0x12bceb0/d .functor OR 1, L_0x12bcf70, L_0x12bd120, C4<0>, C4<0>; +L_0x12bceb0 .delay 1 (30000,30000,30000) L_0x12bceb0/d; +v0x10ee330_0 .net *"_s10", 0 0, L_0x12bcf70; 1 drivers +v0x10ee410_0 .net *"_s12", 0 0, L_0x12bd120; 1 drivers +v0x10ee4f0_0 .net "in", 7 0, L_0x12baeb0; alias, 1 drivers +v0x10ee590_0 .net "ors", 1 0, L_0x12bccd0; 1 drivers +v0x10ee650_0 .net "out", 0 0, L_0x12bceb0; alias, 1 drivers +L_0x12bc0a0 .part L_0x12baeb0, 0, 4; +L_0x12bccd0 .concat8 [ 1 1 0 0], L_0x12bbd90, L_0x12bc9c0; +L_0x12bce10 .part L_0x12baeb0, 4, 4; +L_0x12bcf70 .part L_0x12bccd0, 0, 1; +L_0x12bd120 .part L_0x12bccd0, 1, 1; +S_0x10ec9a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10ec7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e27cf0/d .functor OR 1, L_0x1e27db0, L_0x1e27f10, C4<0>, C4<0>; -L_0x1e27cf0 .delay 1 (30000,30000,30000) L_0x1e27cf0/d; -L_0x1e28140/d .functor OR 1, L_0x1e28250, L_0x1e283b0, C4<0>, C4<0>; -L_0x1e28140 .delay 1 (30000,30000,30000) L_0x1e28140/d; -L_0x1e28530/d .functor OR 1, L_0x1e285a0, L_0x1e28750, C4<0>, C4<0>; -L_0x1e28530 .delay 1 (30000,30000,30000) L_0x1e28530/d; -v0x1c59f30_0 .net *"_s0", 0 0, L_0x1e27cf0; 1 drivers -v0x1c5a030_0 .net *"_s10", 0 0, L_0x1e28250; 1 drivers -v0x1c5a110_0 .net *"_s12", 0 0, L_0x1e283b0; 1 drivers -v0x1c5a1d0_0 .net *"_s14", 0 0, L_0x1e285a0; 1 drivers -v0x1c5a2b0_0 .net *"_s16", 0 0, L_0x1e28750; 1 drivers -v0x1c5a3e0_0 .net *"_s3", 0 0, L_0x1e27db0; 1 drivers -v0x1c5a4c0_0 .net *"_s5", 0 0, L_0x1e27f10; 1 drivers -v0x1c5a5a0_0 .net *"_s6", 0 0, L_0x1e28140; 1 drivers -v0x1c5a680_0 .net "in", 3 0, L_0x1e28840; 1 drivers -v0x1c5a7f0_0 .net "ors", 1 0, L_0x1e28050; 1 drivers -v0x1c5a8d0_0 .net "out", 0 0, L_0x1e28530; 1 drivers -L_0x1e27db0 .part L_0x1e28840, 0, 1; -L_0x1e27f10 .part L_0x1e28840, 1, 1; -L_0x1e28050 .concat8 [ 1 1 0 0], L_0x1e27cf0, L_0x1e28140; -L_0x1e28250 .part L_0x1e28840, 2, 1; -L_0x1e283b0 .part L_0x1e28840, 3, 1; -L_0x1e285a0 .part L_0x1e28050, 0, 1; -L_0x1e28750 .part L_0x1e28050, 1, 1; -S_0x1c5a9f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c59b20; +L_0x12bb550/d .functor OR 1, L_0x12bb610, L_0x12bb770, C4<0>, C4<0>; +L_0x12bb550 .delay 1 (30000,30000,30000) L_0x12bb550/d; +L_0x12bb9a0/d .functor OR 1, L_0x12bbab0, L_0x12bbc10, C4<0>, C4<0>; +L_0x12bb9a0 .delay 1 (30000,30000,30000) L_0x12bb9a0/d; +L_0x12bbd90/d .functor OR 1, L_0x12bbe00, L_0x12bbfb0, C4<0>, C4<0>; +L_0x12bbd90 .delay 1 (30000,30000,30000) L_0x12bbd90/d; +v0x10ecbf0_0 .net *"_s0", 0 0, L_0x12bb550; 1 drivers +v0x10eccf0_0 .net *"_s10", 0 0, L_0x12bbab0; 1 drivers +v0x10ecdd0_0 .net *"_s12", 0 0, L_0x12bbc10; 1 drivers +v0x10ece90_0 .net *"_s14", 0 0, L_0x12bbe00; 1 drivers +v0x10ecf70_0 .net *"_s16", 0 0, L_0x12bbfb0; 1 drivers +v0x10ed0a0_0 .net *"_s3", 0 0, L_0x12bb610; 1 drivers +v0x10ed180_0 .net *"_s5", 0 0, L_0x12bb770; 1 drivers +v0x10ed260_0 .net *"_s6", 0 0, L_0x12bb9a0; 1 drivers +v0x10ed340_0 .net "in", 3 0, L_0x12bc0a0; 1 drivers +v0x10ed4b0_0 .net "ors", 1 0, L_0x12bb8b0; 1 drivers +v0x10ed590_0 .net "out", 0 0, L_0x12bbd90; 1 drivers +L_0x12bb610 .part L_0x12bc0a0, 0, 1; +L_0x12bb770 .part L_0x12bc0a0, 1, 1; +L_0x12bb8b0 .concat8 [ 1 1 0 0], L_0x12bb550, L_0x12bb9a0; +L_0x12bbab0 .part L_0x12bc0a0, 2, 1; +L_0x12bbc10 .part L_0x12bc0a0, 3, 1; +L_0x12bbe00 .part L_0x12bb8b0, 0, 1; +L_0x12bbfb0 .part L_0x12bb8b0, 1, 1; +S_0x10ed6b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10ec7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e28970/d .functor OR 1, L_0x1e289e0, L_0x1e28b40, C4<0>, C4<0>; -L_0x1e28970 .delay 1 (30000,30000,30000) L_0x1e28970/d; -L_0x1e28d70/d .functor OR 1, L_0x1e28e80, L_0x1e28fe0, C4<0>, C4<0>; -L_0x1e28d70 .delay 1 (30000,30000,30000) L_0x1e28d70/d; -L_0x1e29160/d .functor OR 1, L_0x1e291d0, L_0x1e29380, C4<0>, C4<0>; -L_0x1e29160 .delay 1 (30000,30000,30000) L_0x1e29160/d; -v0x1c5abb0_0 .net *"_s0", 0 0, L_0x1e28970; 1 drivers -v0x1c5acb0_0 .net *"_s10", 0 0, L_0x1e28e80; 1 drivers -v0x1c5ad90_0 .net *"_s12", 0 0, L_0x1e28fe0; 1 drivers -v0x1c5ae50_0 .net *"_s14", 0 0, L_0x1e291d0; 1 drivers -v0x1c5af30_0 .net *"_s16", 0 0, L_0x1e29380; 1 drivers -v0x1c5b060_0 .net *"_s3", 0 0, L_0x1e289e0; 1 drivers -v0x1c5b140_0 .net *"_s5", 0 0, L_0x1e28b40; 1 drivers -v0x1c5b220_0 .net *"_s6", 0 0, L_0x1e28d70; 1 drivers -v0x1c5b300_0 .net "in", 3 0, L_0x1e295b0; 1 drivers -v0x1c5b470_0 .net "ors", 1 0, L_0x1e28c80; 1 drivers -v0x1c5b550_0 .net "out", 0 0, L_0x1e29160; 1 drivers -L_0x1e289e0 .part L_0x1e295b0, 0, 1; -L_0x1e28b40 .part L_0x1e295b0, 1, 1; -L_0x1e28c80 .concat8 [ 1 1 0 0], L_0x1e28970, L_0x1e28d70; -L_0x1e28e80 .part L_0x1e295b0, 2, 1; -L_0x1e28fe0 .part L_0x1e295b0, 3, 1; -L_0x1e291d0 .part L_0x1e28c80, 0, 1; -L_0x1e29380 .part L_0x1e28c80, 1, 1; -S_0x1c5be60 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c54f90; +L_0x12bc1d0/d .functor OR 1, L_0x12bc240, L_0x12bc3a0, C4<0>, C4<0>; +L_0x12bc1d0 .delay 1 (30000,30000,30000) L_0x12bc1d0/d; +L_0x12bc5d0/d .functor OR 1, L_0x12bc6e0, L_0x12bc840, C4<0>, C4<0>; +L_0x12bc5d0 .delay 1 (30000,30000,30000) L_0x12bc5d0/d; +L_0x12bc9c0/d .functor OR 1, L_0x12bca30, L_0x12bcbe0, C4<0>, C4<0>; +L_0x12bc9c0 .delay 1 (30000,30000,30000) L_0x12bc9c0/d; +v0x10ed870_0 .net *"_s0", 0 0, L_0x12bc1d0; 1 drivers +v0x10ed970_0 .net *"_s10", 0 0, L_0x12bc6e0; 1 drivers +v0x10eda50_0 .net *"_s12", 0 0, L_0x12bc840; 1 drivers +v0x10edb10_0 .net *"_s14", 0 0, L_0x12bca30; 1 drivers +v0x10edbf0_0 .net *"_s16", 0 0, L_0x12bcbe0; 1 drivers +v0x10edd20_0 .net *"_s3", 0 0, L_0x12bc240; 1 drivers +v0x10ede00_0 .net *"_s5", 0 0, L_0x12bc3a0; 1 drivers +v0x10edee0_0 .net *"_s6", 0 0, L_0x12bc5d0; 1 drivers +v0x10edfc0_0 .net "in", 3 0, L_0x12bce10; 1 drivers +v0x10ee130_0 .net "ors", 1 0, L_0x12bc4e0; 1 drivers +v0x10ee210_0 .net "out", 0 0, L_0x12bc9c0; 1 drivers +L_0x12bc240 .part L_0x12bce10, 0, 1; +L_0x12bc3a0 .part L_0x12bce10, 1, 1; +L_0x12bc4e0 .concat8 [ 1 1 0 0], L_0x12bc1d0, L_0x12bc5d0; +L_0x12bc6e0 .part L_0x12bce10, 2, 1; +L_0x12bc840 .part L_0x12bce10, 3, 1; +L_0x12bca30 .part L_0x12bc4e0, 0, 1; +L_0x12bcbe0 .part L_0x12bc4e0, 1, 1; +S_0x10eeaf0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10e7c20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c61290_0 .net "ands", 7 0, L_0x1e23c10; 1 drivers -v0x1c613a0_0 .net "in", 7 0, L_0x1e22070; alias, 1 drivers -v0x1c61460_0 .net "out", 0 0, L_0x1e25c10; alias, 1 drivers -v0x1c61530_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c5c0b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c5be60; +v0x10f3f20_0 .net "ands", 7 0, L_0x12b7380; 1 drivers +v0x10f4030_0 .net "in", 7 0, L_0x12b57e0; alias, 1 drivers +v0x10f40f0_0 .net "out", 0 0, L_0x12b93e0; alias, 1 drivers +v0x10f41c0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10eed40 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10eeaf0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c5e7f0_0 .net "A", 7 0, L_0x1e22070; alias, 1 drivers -v0x1c5e8f0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c5e9b0_0 .net *"_s0", 0 0, L_0x1e22400; 1 drivers -v0x1c5ea70_0 .net *"_s12", 0 0, L_0x1e22dc0; 1 drivers -v0x1c5eb50_0 .net *"_s16", 0 0, L_0x1e23120; 1 drivers -v0x1c5ec80_0 .net *"_s20", 0 0, L_0x1e23550; 1 drivers -v0x1c5ed60_0 .net *"_s24", 0 0, L_0x1e23880; 1 drivers -v0x1c5ee40_0 .net *"_s28", 0 0, L_0x1e23810; 1 drivers -v0x1c5ef20_0 .net *"_s4", 0 0, L_0x1e227a0; 1 drivers -v0x1c5f090_0 .net *"_s8", 0 0, L_0x1e22ab0; 1 drivers -v0x1c5f170_0 .net "out", 7 0, L_0x1e23c10; alias, 1 drivers -L_0x1e22510 .part L_0x1e22070, 0, 1; -L_0x1e22700 .part v0x1d6daa0_0, 0, 1; -L_0x1e22860 .part L_0x1e22070, 1, 1; -L_0x1e229c0 .part v0x1d6daa0_0, 1, 1; -L_0x1e22b70 .part L_0x1e22070, 2, 1; -L_0x1e22cd0 .part v0x1d6daa0_0, 2, 1; -L_0x1e22e80 .part L_0x1e22070, 3, 1; -L_0x1e22fe0 .part v0x1d6daa0_0, 3, 1; -L_0x1e231e0 .part L_0x1e22070, 4, 1; -L_0x1e23450 .part v0x1d6daa0_0, 4, 1; -L_0x1e235c0 .part L_0x1e22070, 5, 1; -L_0x1e23720 .part v0x1d6daa0_0, 5, 1; -L_0x1e23940 .part L_0x1e22070, 6, 1; -L_0x1e23aa0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e23c10_0_0 .concat8 [ 1 1 1 1], L_0x1e22400, L_0x1e227a0, L_0x1e22ab0, L_0x1e22dc0; -LS_0x1e23c10_0_4 .concat8 [ 1 1 1 1], L_0x1e23120, L_0x1e23550, L_0x1e23880, L_0x1e23810; -L_0x1e23c10 .concat8 [ 4 4 0 0], LS_0x1e23c10_0_0, LS_0x1e23c10_0_4; -L_0x1e23fd0 .part L_0x1e22070, 7, 1; -L_0x1e241c0 .part v0x1d6daa0_0, 7, 1; -S_0x1c5c2f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5c500 .param/l "i" 0 4 54, +C4<00>; -L_0x1e22400/d .functor AND 1, L_0x1e22510, L_0x1e22700, C4<1>, C4<1>; -L_0x1e22400 .delay 1 (30000,30000,30000) L_0x1e22400/d; -v0x1c5c5e0_0 .net *"_s0", 0 0, L_0x1e22510; 1 drivers -v0x1c5c6c0_0 .net *"_s1", 0 0, L_0x1e22700; 1 drivers -S_0x1c5c7a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5c9b0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e227a0/d .functor AND 1, L_0x1e22860, L_0x1e229c0, C4<1>, C4<1>; -L_0x1e227a0 .delay 1 (30000,30000,30000) L_0x1e227a0/d; -v0x1c5ca70_0 .net *"_s0", 0 0, L_0x1e22860; 1 drivers -v0x1c5cb50_0 .net *"_s1", 0 0, L_0x1e229c0; 1 drivers -S_0x1c5cc30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5ce70 .param/l "i" 0 4 54, +C4<010>; -L_0x1e22ab0/d .functor AND 1, L_0x1e22b70, L_0x1e22cd0, C4<1>, C4<1>; -L_0x1e22ab0 .delay 1 (30000,30000,30000) L_0x1e22ab0/d; -v0x1c5cf10_0 .net *"_s0", 0 0, L_0x1e22b70; 1 drivers -v0x1c5cff0_0 .net *"_s1", 0 0, L_0x1e22cd0; 1 drivers -S_0x1c5d0d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5d2e0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e22dc0/d .functor AND 1, L_0x1e22e80, L_0x1e22fe0, C4<1>, C4<1>; -L_0x1e22dc0 .delay 1 (30000,30000,30000) L_0x1e22dc0/d; -v0x1c5d3a0_0 .net *"_s0", 0 0, L_0x1e22e80; 1 drivers -v0x1c5d480_0 .net *"_s1", 0 0, L_0x1e22fe0; 1 drivers -S_0x1c5d560 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5d7c0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e23120/d .functor AND 1, L_0x1e231e0, L_0x1e23450, C4<1>, C4<1>; -L_0x1e23120 .delay 1 (30000,30000,30000) L_0x1e23120/d; -v0x1c5d880_0 .net *"_s0", 0 0, L_0x1e231e0; 1 drivers -v0x1c5d960_0 .net *"_s1", 0 0, L_0x1e23450; 1 drivers -S_0x1c5da40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5dc50 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e23550/d .functor AND 1, L_0x1e235c0, L_0x1e23720, C4<1>, C4<1>; -L_0x1e23550 .delay 1 (30000,30000,30000) L_0x1e23550/d; -v0x1c5dd10_0 .net *"_s0", 0 0, L_0x1e235c0; 1 drivers -v0x1c5ddf0_0 .net *"_s1", 0 0, L_0x1e23720; 1 drivers -S_0x1c5ded0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5e0e0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e23880/d .functor AND 1, L_0x1e23940, L_0x1e23aa0, C4<1>, C4<1>; -L_0x1e23880 .delay 1 (30000,30000,30000) L_0x1e23880/d; -v0x1c5e1a0_0 .net *"_s0", 0 0, L_0x1e23940; 1 drivers -v0x1c5e280_0 .net *"_s1", 0 0, L_0x1e23aa0; 1 drivers -S_0x1c5e360 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c5c0b0; - .timescale -9 -12; -P_0x1c5e570 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e23810/d .functor AND 1, L_0x1e23fd0, L_0x1e241c0, C4<1>, C4<1>; -L_0x1e23810 .delay 1 (30000,30000,30000) L_0x1e23810/d; -v0x1c5e630_0 .net *"_s0", 0 0, L_0x1e23fd0; 1 drivers -v0x1c5e710_0 .net *"_s1", 0 0, L_0x1e241c0; 1 drivers -S_0x1c5f2d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c5be60; +v0x10f1480_0 .net "A", 7 0, L_0x12b57e0; alias, 1 drivers +v0x10f1580_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10f1640_0 .net *"_s0", 0 0, L_0x12b5b70; 1 drivers +v0x10f1700_0 .net *"_s12", 0 0, L_0x12b6530; 1 drivers +v0x10f17e0_0 .net *"_s16", 0 0, L_0x12b6890; 1 drivers +v0x10f1910_0 .net *"_s20", 0 0, L_0x12b6cc0; 1 drivers +v0x10f19f0_0 .net *"_s24", 0 0, L_0x12b6ff0; 1 drivers +v0x10f1ad0_0 .net *"_s28", 0 0, L_0x12b6f80; 1 drivers +v0x10f1bb0_0 .net *"_s4", 0 0, L_0x12b5f10; 1 drivers +v0x10f1d20_0 .net *"_s8", 0 0, L_0x12b6220; 1 drivers +v0x10f1e00_0 .net "out", 7 0, L_0x12b7380; alias, 1 drivers +L_0x12b5c80 .part L_0x12b57e0, 0, 1; +L_0x12b5e70 .part v0x12010b0_0, 0, 1; +L_0x12b5fd0 .part L_0x12b57e0, 1, 1; +L_0x12b6130 .part v0x12010b0_0, 1, 1; +L_0x12b62e0 .part L_0x12b57e0, 2, 1; +L_0x12b6440 .part v0x12010b0_0, 2, 1; +L_0x12b65f0 .part L_0x12b57e0, 3, 1; +L_0x12b6750 .part v0x12010b0_0, 3, 1; +L_0x12b6950 .part L_0x12b57e0, 4, 1; +L_0x12b6bc0 .part v0x12010b0_0, 4, 1; +L_0x12b6d30 .part L_0x12b57e0, 5, 1; +L_0x12b6e90 .part v0x12010b0_0, 5, 1; +L_0x12b70b0 .part L_0x12b57e0, 6, 1; +L_0x12b7210 .part v0x12010b0_0, 6, 1; +LS_0x12b7380_0_0 .concat8 [ 1 1 1 1], L_0x12b5b70, L_0x12b5f10, L_0x12b6220, L_0x12b6530; +LS_0x12b7380_0_4 .concat8 [ 1 1 1 1], L_0x12b6890, L_0x12b6cc0, L_0x12b6ff0, L_0x12b6f80; +L_0x12b7380 .concat8 [ 4 4 0 0], LS_0x12b7380_0_0, LS_0x12b7380_0_4; +L_0x12b7740 .part L_0x12b57e0, 7, 1; +L_0x12b7930 .part v0x12010b0_0, 7, 1; +S_0x10eef80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10ef190 .param/l "i" 0 4 54, +C4<00>; +L_0x12b5b70/d .functor AND 1, L_0x12b5c80, L_0x12b5e70, C4<1>, C4<1>; +L_0x12b5b70 .delay 1 (30000,30000,30000) L_0x12b5b70/d; +v0x10ef270_0 .net *"_s0", 0 0, L_0x12b5c80; 1 drivers +v0x10ef350_0 .net *"_s1", 0 0, L_0x12b5e70; 1 drivers +S_0x10ef430 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10ef640 .param/l "i" 0 4 54, +C4<01>; +L_0x12b5f10/d .functor AND 1, L_0x12b5fd0, L_0x12b6130, C4<1>, C4<1>; +L_0x12b5f10 .delay 1 (30000,30000,30000) L_0x12b5f10/d; +v0x10ef700_0 .net *"_s0", 0 0, L_0x12b5fd0; 1 drivers +v0x10ef7e0_0 .net *"_s1", 0 0, L_0x12b6130; 1 drivers +S_0x10ef8c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10efb00 .param/l "i" 0 4 54, +C4<010>; +L_0x12b6220/d .functor AND 1, L_0x12b62e0, L_0x12b6440, C4<1>, C4<1>; +L_0x12b6220 .delay 1 (30000,30000,30000) L_0x12b6220/d; +v0x10efba0_0 .net *"_s0", 0 0, L_0x12b62e0; 1 drivers +v0x10efc80_0 .net *"_s1", 0 0, L_0x12b6440; 1 drivers +S_0x10efd60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10eff70 .param/l "i" 0 4 54, +C4<011>; +L_0x12b6530/d .functor AND 1, L_0x12b65f0, L_0x12b6750, C4<1>, C4<1>; +L_0x12b6530 .delay 1 (30000,30000,30000) L_0x12b6530/d; +v0x10f0030_0 .net *"_s0", 0 0, L_0x12b65f0; 1 drivers +v0x10f0110_0 .net *"_s1", 0 0, L_0x12b6750; 1 drivers +S_0x10f01f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10f0450 .param/l "i" 0 4 54, +C4<0100>; +L_0x12b6890/d .functor AND 1, L_0x12b6950, L_0x12b6bc0, C4<1>, C4<1>; +L_0x12b6890 .delay 1 (30000,30000,30000) L_0x12b6890/d; +v0x10f0510_0 .net *"_s0", 0 0, L_0x12b6950; 1 drivers +v0x10f05f0_0 .net *"_s1", 0 0, L_0x12b6bc0; 1 drivers +S_0x10f06d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10f08e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12b6cc0/d .functor AND 1, L_0x12b6d30, L_0x12b6e90, C4<1>, C4<1>; +L_0x12b6cc0 .delay 1 (30000,30000,30000) L_0x12b6cc0/d; +v0x10f09a0_0 .net *"_s0", 0 0, L_0x12b6d30; 1 drivers +v0x10f0a80_0 .net *"_s1", 0 0, L_0x12b6e90; 1 drivers +S_0x10f0b60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10f0d70 .param/l "i" 0 4 54, +C4<0110>; +L_0x12b6ff0/d .functor AND 1, L_0x12b70b0, L_0x12b7210, C4<1>, C4<1>; +L_0x12b6ff0 .delay 1 (30000,30000,30000) L_0x12b6ff0/d; +v0x10f0e30_0 .net *"_s0", 0 0, L_0x12b70b0; 1 drivers +v0x10f0f10_0 .net *"_s1", 0 0, L_0x12b7210; 1 drivers +S_0x10f0ff0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10eed40; + .timescale -9 -12; +P_0x10f1200 .param/l "i" 0 4 54, +C4<0111>; +L_0x12b6f80/d .functor AND 1, L_0x12b7740, L_0x12b7930, C4<1>, C4<1>; +L_0x12b6f80 .delay 1 (30000,30000,30000) L_0x12b6f80/d; +v0x10f12c0_0 .net *"_s0", 0 0, L_0x12b7740; 1 drivers +v0x10f13a0_0 .net *"_s1", 0 0, L_0x12b7930; 1 drivers +S_0x10f1f60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10eeaf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e25c10/d .functor OR 1, L_0x1e25cd0, L_0x1e25e80, C4<0>, C4<0>; -L_0x1e25c10 .delay 1 (30000,30000,30000) L_0x1e25c10/d; -v0x1c60e20_0 .net *"_s10", 0 0, L_0x1e25cd0; 1 drivers -v0x1c60f00_0 .net *"_s12", 0 0, L_0x1e25e80; 1 drivers -v0x1c60fe0_0 .net "in", 7 0, L_0x1e23c10; alias, 1 drivers -v0x1c610b0_0 .net "ors", 1 0, L_0x1e25a30; 1 drivers -v0x1c61170_0 .net "out", 0 0, L_0x1e25c10; alias, 1 drivers -L_0x1e24e00 .part L_0x1e23c10, 0, 4; -L_0x1e25a30 .concat8 [ 1 1 0 0], L_0x1e24af0, L_0x1e25720; -L_0x1e25b70 .part L_0x1e23c10, 4, 4; -L_0x1e25cd0 .part L_0x1e25a30, 0, 1; -L_0x1e25e80 .part L_0x1e25a30, 1, 1; -S_0x1c5f490 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c5f2d0; +L_0x12b93e0/d .functor OR 1, L_0x12b94a0, L_0x12b9650, C4<0>, C4<0>; +L_0x12b93e0 .delay 1 (30000,30000,30000) L_0x12b93e0/d; +v0x10f3ab0_0 .net *"_s10", 0 0, L_0x12b94a0; 1 drivers +v0x10f3b90_0 .net *"_s12", 0 0, L_0x12b9650; 1 drivers +v0x10f3c70_0 .net "in", 7 0, L_0x12b7380; alias, 1 drivers +v0x10f3d40_0 .net "ors", 1 0, L_0x12b9200; 1 drivers +v0x10f3e00_0 .net "out", 0 0, L_0x12b93e0; alias, 1 drivers +L_0x12b85a0 .part L_0x12b7380, 0, 4; +L_0x12b9200 .concat8 [ 1 1 0 0], L_0x12b8260, L_0x12b8ec0; +L_0x12b9340 .part L_0x12b7380, 4, 4; +L_0x12b94a0 .part L_0x12b9200, 0, 1; +L_0x12b9650 .part L_0x12b9200, 1, 1; +S_0x10f2120 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10f1f60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e242b0/d .functor OR 1, L_0x1e24370, L_0x1e244d0, C4<0>, C4<0>; -L_0x1e242b0 .delay 1 (30000,30000,30000) L_0x1e242b0/d; -L_0x1e24700/d .functor OR 1, L_0x1e24810, L_0x1e24970, C4<0>, C4<0>; -L_0x1e24700 .delay 1 (30000,30000,30000) L_0x1e24700/d; -L_0x1e24af0/d .functor OR 1, L_0x1e24b60, L_0x1e24d10, C4<0>, C4<0>; -L_0x1e24af0 .delay 1 (30000,30000,30000) L_0x1e24af0/d; -v0x1c5f6e0_0 .net *"_s0", 0 0, L_0x1e242b0; 1 drivers -v0x1c5f7e0_0 .net *"_s10", 0 0, L_0x1e24810; 1 drivers -v0x1c5f8c0_0 .net *"_s12", 0 0, L_0x1e24970; 1 drivers -v0x1c5f980_0 .net *"_s14", 0 0, L_0x1e24b60; 1 drivers -v0x1c5fa60_0 .net *"_s16", 0 0, L_0x1e24d10; 1 drivers -v0x1c5fb90_0 .net *"_s3", 0 0, L_0x1e24370; 1 drivers -v0x1c5fc70_0 .net *"_s5", 0 0, L_0x1e244d0; 1 drivers -v0x1c5fd50_0 .net *"_s6", 0 0, L_0x1e24700; 1 drivers -v0x1c5fe30_0 .net "in", 3 0, L_0x1e24e00; 1 drivers -v0x1c5ffa0_0 .net "ors", 1 0, L_0x1e24610; 1 drivers -v0x1c60080_0 .net "out", 0 0, L_0x1e24af0; 1 drivers -L_0x1e24370 .part L_0x1e24e00, 0, 1; -L_0x1e244d0 .part L_0x1e24e00, 1, 1; -L_0x1e24610 .concat8 [ 1 1 0 0], L_0x1e242b0, L_0x1e24700; -L_0x1e24810 .part L_0x1e24e00, 2, 1; -L_0x1e24970 .part L_0x1e24e00, 3, 1; -L_0x1e24b60 .part L_0x1e24610, 0, 1; -L_0x1e24d10 .part L_0x1e24610, 1, 1; -S_0x1c601a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c5f2d0; +L_0x12b7a20/d .functor OR 1, L_0x12b7ae0, L_0x12b7c40, C4<0>, C4<0>; +L_0x12b7a20 .delay 1 (30000,30000,30000) L_0x12b7a20/d; +L_0x12b7e70/d .functor OR 1, L_0x12b7f80, L_0x12b80e0, C4<0>, C4<0>; +L_0x12b7e70 .delay 1 (30000,30000,30000) L_0x12b7e70/d; +L_0x12b8260/d .functor OR 1, L_0x12b8300, L_0x12b84b0, C4<0>, C4<0>; +L_0x12b8260 .delay 1 (30000,30000,30000) L_0x12b8260/d; +v0x10f2370_0 .net *"_s0", 0 0, L_0x12b7a20; 1 drivers +v0x10f2470_0 .net *"_s10", 0 0, L_0x12b7f80; 1 drivers +v0x10f2550_0 .net *"_s12", 0 0, L_0x12b80e0; 1 drivers +v0x10f2610_0 .net *"_s14", 0 0, L_0x12b8300; 1 drivers +v0x10f26f0_0 .net *"_s16", 0 0, L_0x12b84b0; 1 drivers +v0x10f2820_0 .net *"_s3", 0 0, L_0x12b7ae0; 1 drivers +v0x10f2900_0 .net *"_s5", 0 0, L_0x12b7c40; 1 drivers +v0x10f29e0_0 .net *"_s6", 0 0, L_0x12b7e70; 1 drivers +v0x10f2ac0_0 .net "in", 3 0, L_0x12b85a0; 1 drivers +v0x10f2c30_0 .net "ors", 1 0, L_0x12b7d80; 1 drivers +v0x10f2d10_0 .net "out", 0 0, L_0x12b8260; 1 drivers +L_0x12b7ae0 .part L_0x12b85a0, 0, 1; +L_0x12b7c40 .part L_0x12b85a0, 1, 1; +L_0x12b7d80 .concat8 [ 1 1 0 0], L_0x12b7a20, L_0x12b7e70; +L_0x12b7f80 .part L_0x12b85a0, 2, 1; +L_0x12b80e0 .part L_0x12b85a0, 3, 1; +L_0x12b8300 .part L_0x12b7d80, 0, 1; +L_0x12b84b0 .part L_0x12b7d80, 1, 1; +S_0x10f2e30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10f1f60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e24f30/d .functor OR 1, L_0x1e24fa0, L_0x1e25100, C4<0>, C4<0>; -L_0x1e24f30 .delay 1 (30000,30000,30000) L_0x1e24f30/d; -L_0x1e25330/d .functor OR 1, L_0x1e25440, L_0x1e255a0, C4<0>, C4<0>; -L_0x1e25330 .delay 1 (30000,30000,30000) L_0x1e25330/d; -L_0x1e25720/d .functor OR 1, L_0x1e25790, L_0x1e25940, C4<0>, C4<0>; -L_0x1e25720 .delay 1 (30000,30000,30000) L_0x1e25720/d; -v0x1c60360_0 .net *"_s0", 0 0, L_0x1e24f30; 1 drivers -v0x1c60460_0 .net *"_s10", 0 0, L_0x1e25440; 1 drivers -v0x1c60540_0 .net *"_s12", 0 0, L_0x1e255a0; 1 drivers -v0x1c60600_0 .net *"_s14", 0 0, L_0x1e25790; 1 drivers -v0x1c606e0_0 .net *"_s16", 0 0, L_0x1e25940; 1 drivers -v0x1c60810_0 .net *"_s3", 0 0, L_0x1e24fa0; 1 drivers -v0x1c608f0_0 .net *"_s5", 0 0, L_0x1e25100; 1 drivers -v0x1c609d0_0 .net *"_s6", 0 0, L_0x1e25330; 1 drivers -v0x1c60ab0_0 .net "in", 3 0, L_0x1e25b70; 1 drivers -v0x1c60c20_0 .net "ors", 1 0, L_0x1e25240; 1 drivers -v0x1c60d00_0 .net "out", 0 0, L_0x1e25720; 1 drivers -L_0x1e24fa0 .part L_0x1e25b70, 0, 1; -L_0x1e25100 .part L_0x1e25b70, 1, 1; -L_0x1e25240 .concat8 [ 1 1 0 0], L_0x1e24f30, L_0x1e25330; -L_0x1e25440 .part L_0x1e25b70, 2, 1; -L_0x1e255a0 .part L_0x1e25b70, 3, 1; -L_0x1e25790 .part L_0x1e25240, 0, 1; -L_0x1e25940 .part L_0x1e25240, 1, 1; -S_0x1c61610 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c54f90; +L_0x12b86d0/d .functor OR 1, L_0x12b8740, L_0x12b88a0, C4<0>, C4<0>; +L_0x12b86d0 .delay 1 (30000,30000,30000) L_0x12b86d0/d; +L_0x12b8ad0/d .functor OR 1, L_0x12b8be0, L_0x12b8d40, C4<0>, C4<0>; +L_0x12b8ad0 .delay 1 (30000,30000,30000) L_0x12b8ad0/d; +L_0x12b8ec0/d .functor OR 1, L_0x12b8f60, L_0x12b9110, C4<0>, C4<0>; +L_0x12b8ec0 .delay 1 (30000,30000,30000) L_0x12b8ec0/d; +v0x10f2ff0_0 .net *"_s0", 0 0, L_0x12b86d0; 1 drivers +v0x10f30f0_0 .net *"_s10", 0 0, L_0x12b8be0; 1 drivers +v0x10f31d0_0 .net *"_s12", 0 0, L_0x12b8d40; 1 drivers +v0x10f3290_0 .net *"_s14", 0 0, L_0x12b8f60; 1 drivers +v0x10f3370_0 .net *"_s16", 0 0, L_0x12b9110; 1 drivers +v0x10f34a0_0 .net *"_s3", 0 0, L_0x12b8740; 1 drivers +v0x10f3580_0 .net *"_s5", 0 0, L_0x12b88a0; 1 drivers +v0x10f3660_0 .net *"_s6", 0 0, L_0x12b8ad0; 1 drivers +v0x10f3740_0 .net "in", 3 0, L_0x12b9340; 1 drivers +v0x10f38b0_0 .net "ors", 1 0, L_0x12b89e0; 1 drivers +v0x10f3990_0 .net "out", 0 0, L_0x12b8ec0; 1 drivers +L_0x12b8740 .part L_0x12b9340, 0, 1; +L_0x12b88a0 .part L_0x12b9340, 1, 1; +L_0x12b89e0 .concat8 [ 1 1 0 0], L_0x12b86d0, L_0x12b8ad0; +L_0x12b8be0 .part L_0x12b9340, 2, 1; +L_0x12b8d40 .part L_0x12b9340, 3, 1; +L_0x12b8f60 .part L_0x12b89e0, 0, 1; +L_0x12b9110 .part L_0x12b89e0, 1, 1; +S_0x10f42a0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10e7c20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -10204,80 +10214,80 @@ S_0x1c61610 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c54f90; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e213e0/d .functor XNOR 1, L_0x1e29ab0, L_0x1e29c10, C4<0>, C4<0>; -L_0x1e213e0 .delay 1 (20000,20000,20000) L_0x1e213e0/d; -L_0x1e21650/d .functor AND 1, L_0x1e29ab0, L_0x1e203e0, C4<1>, C4<1>; -L_0x1e21650 .delay 1 (30000,30000,30000) L_0x1e21650/d; -L_0x1e216c0/d .functor AND 1, L_0x1e213e0, L_0x1e20020, C4<1>, C4<1>; -L_0x1e216c0 .delay 1 (30000,30000,30000) L_0x1e216c0/d; -L_0x1e21820/d .functor OR 1, L_0x1e216c0, L_0x1e21650, C4<0>, C4<0>; -L_0x1e21820 .delay 1 (30000,30000,30000) L_0x1e21820/d; -v0x1c618c0_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers -v0x1c619b0_0 .net "a_", 0 0, L_0x1e20280; alias, 1 drivers -v0x1c61a70_0 .net "b", 0 0, L_0x1e29c10; alias, 1 drivers -v0x1c61b60_0 .net "b_", 0 0, L_0x1e203e0; alias, 1 drivers -v0x1c61c00_0 .net "carryin", 0 0, L_0x1e20020; alias, 1 drivers -v0x1c61d40_0 .net "eq", 0 0, L_0x1e213e0; 1 drivers -v0x1c61e00_0 .net "lt", 0 0, L_0x1e21650; 1 drivers -v0x1c61ec0_0 .net "out", 0 0, L_0x1e21820; 1 drivers -v0x1c61f80_0 .net "w0", 0 0, L_0x1e216c0; 1 drivers -S_0x1c621d0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c54f90; +L_0x12b4b50/d .functor XNOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; +L_0x12b4b50 .delay 1 (20000,20000,20000) L_0x12b4b50/d; +L_0x12b4dc0/d .functor AND 1, L_0x12bd310, L_0x12b3b50, C4<1>, C4<1>; +L_0x12b4dc0 .delay 1 (30000,30000,30000) L_0x12b4dc0/d; +L_0x12b4e30/d .functor AND 1, L_0x12b4b50, L_0x12b3790, C4<1>, C4<1>; +L_0x12b4e30 .delay 1 (30000,30000,30000) L_0x12b4e30/d; +L_0x12b4f90/d .functor OR 1, L_0x12b4e30, L_0x12b4dc0, C4<0>, C4<0>; +L_0x12b4f90 .delay 1 (30000,30000,30000) L_0x12b4f90/d; +v0x10f4550_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers +v0x10f4640_0 .net "a_", 0 0, L_0x12b39f0; alias, 1 drivers +v0x10f4700_0 .net "b", 0 0, L_0x12bd470; alias, 1 drivers +v0x10f47f0_0 .net "b_", 0 0, L_0x12b3b50; alias, 1 drivers +v0x10f4890_0 .net "carryin", 0 0, L_0x12b3790; alias, 1 drivers +v0x10f49d0_0 .net "eq", 0 0, L_0x12b4b50; 1 drivers +v0x10f4a90_0 .net "lt", 0 0, L_0x12b4dc0; 1 drivers +v0x10f4b50_0 .net "out", 0 0, L_0x12b4f90; 1 drivers +v0x10f4c10_0 .net "w0", 0 0, L_0x12b4e30; 1 drivers +S_0x10f4e60 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10e7c20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e211c0/d .functor OR 1, L_0x1e20d10, L_0x1c63430, C4<0>, C4<0>; -L_0x1e211c0 .delay 1 (30000,30000,30000) L_0x1e211c0/d; -v0x1c62fc0_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers -v0x1c63110_0 .net "b", 0 0, L_0x1e203e0; alias, 1 drivers -v0x1c631d0_0 .net "c1", 0 0, L_0x1e20d10; 1 drivers -v0x1c63270_0 .net "c2", 0 0, L_0x1c63430; 1 drivers -v0x1c63340_0 .net "carryin", 0 0, L_0x1e20020; alias, 1 drivers -v0x1c634c0_0 .net "carryout", 0 0, L_0x1e211c0; 1 drivers -v0x1c63560_0 .net "s1", 0 0, L_0x1e20c50; 1 drivers -v0x1c63600_0 .net "sum", 0 0, L_0x1e20e70; 1 drivers -S_0x1c62420 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c621d0; +L_0x12b4930/d .functor OR 1, L_0x12b4480, L_0x10f60c0, C4<0>, C4<0>; +L_0x12b4930 .delay 1 (30000,30000,30000) L_0x12b4930/d; +v0x10f5c50_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers +v0x10f5da0_0 .net "b", 0 0, L_0x12b3b50; alias, 1 drivers +v0x10f5e60_0 .net "c1", 0 0, L_0x12b4480; 1 drivers +v0x10f5f00_0 .net "c2", 0 0, L_0x10f60c0; 1 drivers +v0x10f5fd0_0 .net "carryin", 0 0, L_0x12b3790; alias, 1 drivers +v0x10f6150_0 .net "carryout", 0 0, L_0x12b4930; 1 drivers +v0x10f61f0_0 .net "s1", 0 0, L_0x12b43c0; 1 drivers +v0x10f6290_0 .net "sum", 0 0, L_0x12b45e0; 1 drivers +S_0x10f50b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10f4e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e20c50/d .functor XOR 1, L_0x1e29ab0, L_0x1e203e0, C4<0>, C4<0>; -L_0x1e20c50 .delay 1 (30000,30000,30000) L_0x1e20c50/d; -L_0x1e20d10/d .functor AND 1, L_0x1e29ab0, L_0x1e203e0, C4<1>, C4<1>; -L_0x1e20d10 .delay 1 (30000,30000,30000) L_0x1e20d10/d; -v0x1c62680_0 .net "a", 0 0, L_0x1e29ab0; alias, 1 drivers -v0x1c62740_0 .net "b", 0 0, L_0x1e203e0; alias, 1 drivers -v0x1c62800_0 .net "carryout", 0 0, L_0x1e20d10; alias, 1 drivers -v0x1c628a0_0 .net "sum", 0 0, L_0x1e20c50; alias, 1 drivers -S_0x1c629d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c621d0; +L_0x12b43c0/d .functor XOR 1, L_0x12bd310, L_0x12b3b50, C4<0>, C4<0>; +L_0x12b43c0 .delay 1 (30000,30000,30000) L_0x12b43c0/d; +L_0x12b4480/d .functor AND 1, L_0x12bd310, L_0x12b3b50, C4<1>, C4<1>; +L_0x12b4480 .delay 1 (30000,30000,30000) L_0x12b4480/d; +v0x10f5310_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers +v0x10f53d0_0 .net "b", 0 0, L_0x12b3b50; alias, 1 drivers +v0x10f5490_0 .net "carryout", 0 0, L_0x12b4480; alias, 1 drivers +v0x10f5530_0 .net "sum", 0 0, L_0x12b43c0; alias, 1 drivers +S_0x10f5660 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10f4e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e20e70/d .functor XOR 1, L_0x1e20c50, L_0x1e20020, C4<0>, C4<0>; -L_0x1e20e70 .delay 1 (30000,30000,30000) L_0x1e20e70/d; -L_0x1c63430/d .functor AND 1, L_0x1e20c50, L_0x1e20020, C4<1>, C4<1>; -L_0x1c63430 .delay 1 (30000,30000,30000) L_0x1c63430/d; -v0x1c62c30_0 .net "a", 0 0, L_0x1e20c50; alias, 1 drivers -v0x1c62d00_0 .net "b", 0 0, L_0x1e20020; alias, 1 drivers -v0x1c62da0_0 .net "carryout", 0 0, L_0x1c63430; alias, 1 drivers -v0x1c62e70_0 .net "sum", 0 0, L_0x1e20e70; alias, 1 drivers -S_0x1c64a20 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c54cc0; - .timescale -9 -12; -L_0x7f72592db458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db4a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e29b50/d .functor OR 1, L_0x7f72592db458, L_0x7f72592db4a0, C4<0>, C4<0>; -L_0x1e29b50 .delay 1 (30000,30000,30000) L_0x1e29b50/d; -v0x1c64c10_0 .net/2u *"_s0", 0 0, L_0x7f72592db458; 1 drivers -v0x1c64cf0_0 .net/2u *"_s2", 0 0, L_0x7f72592db4a0; 1 drivers -S_0x1c64dd0 .scope generate, "alu_slices[19]" "alu_slices[19]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c64fe0 .param/l "i" 0 3 37, +C4<010011>; -S_0x1c650a0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c64dd0; +L_0x12b45e0/d .functor XOR 1, L_0x12b43c0, L_0x12b3790, C4<0>, C4<0>; +L_0x12b45e0 .delay 1 (30000,30000,30000) L_0x12b45e0/d; +L_0x10f60c0/d .functor AND 1, L_0x12b43c0, L_0x12b3790, C4<1>, C4<1>; +L_0x10f60c0 .delay 1 (30000,30000,30000) L_0x10f60c0/d; +v0x10f58c0_0 .net "a", 0 0, L_0x12b43c0; alias, 1 drivers +v0x10f5990_0 .net "b", 0 0, L_0x12b3790; alias, 1 drivers +v0x10f5a30_0 .net "carryout", 0 0, L_0x10f60c0; alias, 1 drivers +v0x10f5b00_0 .net "sum", 0 0, L_0x12b45e0; alias, 1 drivers +S_0x10f76b0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10e7950; + .timescale -9 -12; +L_0x2b0ab3d06458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d064a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bd3b0/d .functor OR 1, L_0x2b0ab3d06458, L_0x2b0ab3d064a0, C4<0>, C4<0>; +L_0x12bd3b0 .delay 1 (30000,30000,30000) L_0x12bd3b0/d; +v0x10f78a0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06458; 1 drivers +v0x10f7980_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d064a0; 1 drivers +S_0x10f7a60 .scope generate, "alu_slices[19]" "alu_slices[19]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x10f7c70 .param/l "i" 0 3 41, +C4<010011>; +S_0x10f7d30 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10f7a60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -10286,445 +10296,445 @@ S_0x1c650a0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c64dd0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e23b90/d .functor NOT 1, L_0x1e33710, C4<0>, C4<0>, C4<0>; -L_0x1e23b90 .delay 1 (10000,10000,10000) L_0x1e23b90/d; -L_0x1e29f20/d .functor NOT 1, L_0x1e29cb0, C4<0>, C4<0>, C4<0>; -L_0x1e29f20 .delay 1 (10000,10000,10000) L_0x1e29f20/d; -L_0x1e2af20/d .functor XOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; -L_0x1e2af20 .delay 1 (30000,30000,30000) L_0x1e2af20/d; -L_0x7f72592db4e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db530 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e2b5d0/d .functor OR 1, L_0x7f72592db4e8, L_0x7f72592db530, C4<0>, C4<0>; -L_0x1e2b5d0 .delay 1 (30000,30000,30000) L_0x1e2b5d0/d; -L_0x1e2b7d0/d .functor AND 1, L_0x1e33710, L_0x1e29cb0, C4<1>, C4<1>; -L_0x1e2b7d0 .delay 1 (30000,30000,30000) L_0x1e2b7d0/d; -L_0x1e2b890/d .functor NAND 1, L_0x1e33710, L_0x1e29cb0, C4<1>, C4<1>; -L_0x1e2b890 .delay 1 (20000,20000,20000) L_0x1e2b890/d; -L_0x1e2b9f0/d .functor XOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; -L_0x1e2b9f0 .delay 1 (20000,20000,20000) L_0x1e2b9f0/d; -L_0x1e2bea0/d .functor OR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; -L_0x1e2bea0 .delay 1 (30000,30000,30000) L_0x1e2bea0/d; -L_0x1e33610/d .functor NOT 1, L_0x1e2f810, C4<0>, C4<0>, C4<0>; -L_0x1e33610 .delay 1 (10000,10000,10000) L_0x1e33610/d; -v0x1c737e0_0 .net "A", 0 0, L_0x1e33710; 1 drivers -v0x1c738a0_0 .net "A_", 0 0, L_0x1e23b90; 1 drivers -v0x1c73960_0 .net "B", 0 0, L_0x1e29cb0; 1 drivers -v0x1c73a30_0 .net "B_", 0 0, L_0x1e29f20; 1 drivers -v0x1c73ad0_0 .net *"_s12", 0 0, L_0x1e2b5d0; 1 drivers -v0x1c73bc0_0 .net/2s *"_s14", 0 0, L_0x7f72592db4e8; 1 drivers -v0x1c73c80_0 .net/2s *"_s16", 0 0, L_0x7f72592db530; 1 drivers -v0x1c73d60_0 .net *"_s18", 0 0, L_0x1e2b7d0; 1 drivers -v0x1c73e40_0 .net *"_s20", 0 0, L_0x1e2b890; 1 drivers -v0x1c73fb0_0 .net *"_s22", 0 0, L_0x1e2b9f0; 1 drivers -v0x1c74090_0 .net *"_s24", 0 0, L_0x1e2bea0; 1 drivers -o0x7f72593827b8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1c74170_0 name=_s30 -o0x7f72593827e8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1c74250_0 name=_s32 -v0x1c74330_0 .net *"_s8", 0 0, L_0x1e2af20; 1 drivers -v0x1c74410_0 .net "carryin", 0 0, L_0x1e29d50; 1 drivers -v0x1c744b0_0 .net "carryout", 0 0, L_0x1e332b0; 1 drivers -v0x1c74550_0 .net "carryouts", 7 0, L_0x1ec0b60; 1 drivers -v0x1c74700_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c747a0_0 .net "result", 0 0, L_0x1e2f810; 1 drivers -v0x1c74890_0 .net "results", 7 0, L_0x1e2bc70; 1 drivers -v0x1c749a0_0 .net "zero", 0 0, L_0x1e33610; 1 drivers -LS_0x1e2bc70_0_0 .concat8 [ 1 1 1 1], L_0x1e2a440, L_0x1e2aa70, L_0x1e2af20, L_0x1e2b5d0; -LS_0x1e2bc70_0_4 .concat8 [ 1 1 1 1], L_0x1e2b7d0, L_0x1e2b890, L_0x1e2b9f0, L_0x1e2bea0; -L_0x1e2bc70 .concat8 [ 4 4 0 0], LS_0x1e2bc70_0_0, LS_0x1e2bc70_0_4; -LS_0x1ec0b60_0_0 .concat [ 1 1 1 1], L_0x1e2a6f0, L_0x1e2adc0, o0x7f72593827b8, L_0x1e2b420; -LS_0x1ec0b60_0_4 .concat [ 4 0 0 0], o0x7f72593827e8; -L_0x1ec0b60 .concat [ 4 4 0 0], LS_0x1ec0b60_0_0, LS_0x1ec0b60_0_4; -S_0x1c65320 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c650a0; +L_0x12b7300/d .functor NOT 1, L_0x12c6f10, C4<0>, C4<0>, C4<0>; +L_0x12b7300 .delay 1 (10000,10000,10000) L_0x12b7300/d; +L_0x12bd780/d .functor NOT 1, L_0x12bd510, C4<0>, C4<0>, C4<0>; +L_0x12bd780 .delay 1 (10000,10000,10000) L_0x12bd780/d; +L_0x12be780/d .functor XOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; +L_0x12be780 .delay 1 (30000,30000,30000) L_0x12be780/d; +L_0x2b0ab3d064e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06530 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12bee30/d .functor OR 1, L_0x2b0ab3d064e8, L_0x2b0ab3d06530, C4<0>, C4<0>; +L_0x12bee30 .delay 1 (30000,30000,30000) L_0x12bee30/d; +L_0x12bf030/d .functor AND 1, L_0x12c6f10, L_0x12bd510, C4<1>, C4<1>; +L_0x12bf030 .delay 1 (30000,30000,30000) L_0x12bf030/d; +L_0x12bf0f0/d .functor NAND 1, L_0x12c6f10, L_0x12bd510, C4<1>, C4<1>; +L_0x12bf0f0 .delay 1 (20000,20000,20000) L_0x12bf0f0/d; +L_0x12bf250/d .functor XOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; +L_0x12bf250 .delay 1 (20000,20000,20000) L_0x12bf250/d; +L_0x12bf700/d .functor OR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; +L_0x12bf700 .delay 1 (30000,30000,30000) L_0x12bf700/d; +L_0x12c6e10/d .functor NOT 1, L_0x12c3070, C4<0>, C4<0>, C4<0>; +L_0x12c6e10 .delay 1 (10000,10000,10000) L_0x12c6e10/d; +v0x1106460_0 .net "A", 0 0, L_0x12c6f10; 1 drivers +v0x1106520_0 .net "A_", 0 0, L_0x12b7300; 1 drivers +v0x11065e0_0 .net "B", 0 0, L_0x12bd510; 1 drivers +v0x11066b0_0 .net "B_", 0 0, L_0x12bd780; 1 drivers +v0x1106750_0 .net *"_s12", 0 0, L_0x12bee30; 1 drivers +v0x1106840_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d064e8; 1 drivers +v0x1106900_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06530; 1 drivers +v0x11069e0_0 .net *"_s18", 0 0, L_0x12bf030; 1 drivers +v0x1106ac0_0 .net *"_s20", 0 0, L_0x12bf0f0; 1 drivers +v0x1106c30_0 .net *"_s22", 0 0, L_0x12bf250; 1 drivers +v0x1106d10_0 .net *"_s24", 0 0, L_0x12bf700; 1 drivers +o0x2b0ab3cd17b8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1106df0_0 name=_s30 +o0x2b0ab3cd17e8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1106ed0_0 name=_s32 +v0x1106fb0_0 .net *"_s8", 0 0, L_0x12be780; 1 drivers +v0x1107090_0 .net "carryin", 0 0, L_0x12bd5b0; 1 drivers +v0x1107130_0 .net "carryout", 0 0, L_0x12c6ab0; 1 drivers +v0x11071d0_0 .net "carryouts", 7 0, L_0x1354e90; 1 drivers +v0x1107380_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1107420_0 .net "result", 0 0, L_0x12c3070; 1 drivers +v0x1107510_0 .net "results", 7 0, L_0x12bf4d0; 1 drivers +v0x1107620_0 .net "zero", 0 0, L_0x12c6e10; 1 drivers +LS_0x12bf4d0_0_0 .concat8 [ 1 1 1 1], L_0x12bdca0, L_0x12be2d0, L_0x12be780, L_0x12bee30; +LS_0x12bf4d0_0_4 .concat8 [ 1 1 1 1], L_0x12bf030, L_0x12bf0f0, L_0x12bf250, L_0x12bf700; +L_0x12bf4d0 .concat8 [ 4 4 0 0], LS_0x12bf4d0_0_0, LS_0x12bf4d0_0_4; +LS_0x1354e90_0_0 .concat [ 1 1 1 1], L_0x12bdf50, L_0x12be620, o0x2b0ab3cd17b8, L_0x12bec80; +LS_0x1354e90_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd17e8; +L_0x1354e90 .concat [ 4 4 0 0], LS_0x1354e90_0_0, LS_0x1354e90_0_4; +S_0x10f7fb0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10f7d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e2a6f0/d .functor OR 1, L_0x1e2a1d0, L_0x1e2a590, C4<0>, C4<0>; -L_0x1e2a6f0 .delay 1 (30000,30000,30000) L_0x1e2a6f0/d; -v0x1c66150_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers -v0x1c66210_0 .net "b", 0 0, L_0x1e29cb0; alias, 1 drivers -v0x1c662e0_0 .net "c1", 0 0, L_0x1e2a1d0; 1 drivers -v0x1c663e0_0 .net "c2", 0 0, L_0x1e2a590; 1 drivers -v0x1c664b0_0 .net "carryin", 0 0, L_0x1e29d50; alias, 1 drivers -v0x1c665a0_0 .net "carryout", 0 0, L_0x1e2a6f0; 1 drivers -v0x1c66640_0 .net "s1", 0 0, L_0x1e2a110; 1 drivers -v0x1c66730_0 .net "sum", 0 0, L_0x1e2a440; 1 drivers -S_0x1c65590 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c65320; +L_0x12bdf50/d .functor OR 1, L_0x12bda30, L_0x12bddf0, C4<0>, C4<0>; +L_0x12bdf50 .delay 1 (30000,30000,30000) L_0x12bdf50/d; +v0x10f8de0_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers +v0x10f8ea0_0 .net "b", 0 0, L_0x12bd510; alias, 1 drivers +v0x10f8f70_0 .net "c1", 0 0, L_0x12bda30; 1 drivers +v0x10f9070_0 .net "c2", 0 0, L_0x12bddf0; 1 drivers +v0x10f9140_0 .net "carryin", 0 0, L_0x12bd5b0; alias, 1 drivers +v0x10f9230_0 .net "carryout", 0 0, L_0x12bdf50; 1 drivers +v0x10f92d0_0 .net "s1", 0 0, L_0x12bd970; 1 drivers +v0x10f93c0_0 .net "sum", 0 0, L_0x12bdca0; 1 drivers +S_0x10f8220 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10f7fb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e2a110/d .functor XOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; -L_0x1e2a110 .delay 1 (30000,30000,30000) L_0x1e2a110/d; -L_0x1e2a1d0/d .functor AND 1, L_0x1e33710, L_0x1e29cb0, C4<1>, C4<1>; -L_0x1e2a1d0 .delay 1 (30000,30000,30000) L_0x1e2a1d0/d; -v0x1c657f0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers -v0x1c658d0_0 .net "b", 0 0, L_0x1e29cb0; alias, 1 drivers -v0x1c65990_0 .net "carryout", 0 0, L_0x1e2a1d0; alias, 1 drivers -v0x1c65a30_0 .net "sum", 0 0, L_0x1e2a110; alias, 1 drivers -S_0x1c65b70 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c65320; +L_0x12bd970/d .functor XOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; +L_0x12bd970 .delay 1 (30000,30000,30000) L_0x12bd970/d; +L_0x12bda30/d .functor AND 1, L_0x12c6f10, L_0x12bd510, C4<1>, C4<1>; +L_0x12bda30 .delay 1 (30000,30000,30000) L_0x12bda30/d; +v0x10f8480_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers +v0x10f8560_0 .net "b", 0 0, L_0x12bd510; alias, 1 drivers +v0x10f8620_0 .net "carryout", 0 0, L_0x12bda30; alias, 1 drivers +v0x10f86c0_0 .net "sum", 0 0, L_0x12bd970; alias, 1 drivers +S_0x10f8800 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10f7fb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e2a440/d .functor XOR 1, L_0x1e2a110, L_0x1e29d50, C4<0>, C4<0>; -L_0x1e2a440 .delay 1 (30000,30000,30000) L_0x1e2a440/d; -L_0x1e2a590/d .functor AND 1, L_0x1e2a110, L_0x1e29d50, C4<1>, C4<1>; -L_0x1e2a590 .delay 1 (30000,30000,30000) L_0x1e2a590/d; -v0x1c65dd0_0 .net "a", 0 0, L_0x1e2a110; alias, 1 drivers -v0x1c65e70_0 .net "b", 0 0, L_0x1e29d50; alias, 1 drivers -v0x1c65f10_0 .net "carryout", 0 0, L_0x1e2a590; alias, 1 drivers -v0x1c65fe0_0 .net "sum", 0 0, L_0x1e2a440; alias, 1 drivers -S_0x1c66800 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c650a0; +L_0x12bdca0/d .functor XOR 1, L_0x12bd970, L_0x12bd5b0, C4<0>, C4<0>; +L_0x12bdca0 .delay 1 (30000,30000,30000) L_0x12bdca0/d; +L_0x12bddf0/d .functor AND 1, L_0x12bd970, L_0x12bd5b0, C4<1>, C4<1>; +L_0x12bddf0 .delay 1 (30000,30000,30000) L_0x12bddf0/d; +v0x10f8a60_0 .net "a", 0 0, L_0x12bd970; alias, 1 drivers +v0x10f8b00_0 .net "b", 0 0, L_0x12bd5b0; alias, 1 drivers +v0x10f8ba0_0 .net "carryout", 0 0, L_0x12bddf0; alias, 1 drivers +v0x10f8c70_0 .net "sum", 0 0, L_0x12bdca0; alias, 1 drivers +S_0x10f9490 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10f7d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c6bbf0_0 .net "ands", 7 0, L_0x1e312b0; 1 drivers -v0x1c6bd00_0 .net "in", 7 0, L_0x1ec0b60; alias, 1 drivers -v0x1c6bdc0_0 .net "out", 0 0, L_0x1e332b0; alias, 1 drivers -v0x1c6be90_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c66a20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c66800; +v0x10fe880_0 .net "ands", 7 0, L_0x12c4ab0; 1 drivers +v0x10fe990_0 .net "in", 7 0, L_0x1354e90; alias, 1 drivers +v0x10fea50_0 .net "out", 0 0, L_0x12c6ab0; alias, 1 drivers +v0x10feb20_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10f96b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10f9490; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c69150_0 .net "A", 7 0, L_0x1ec0b60; alias, 1 drivers -v0x1c69250_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c69310_0 .net *"_s0", 0 0, L_0x1e2fb70; 1 drivers -v0x1c693d0_0 .net *"_s12", 0 0, L_0x1e304e0; 1 drivers -v0x1c694b0_0 .net *"_s16", 0 0, L_0x1e30840; 1 drivers -v0x1c695e0_0 .net *"_s20", 0 0, L_0x1e30b50; 1 drivers -v0x1c696c0_0 .net *"_s24", 0 0, L_0x1e30f70; 1 drivers -v0x1c697a0_0 .net *"_s28", 0 0, L_0x1e30f00; 1 drivers -v0x1c69880_0 .net *"_s4", 0 0, L_0x1e2fe80; 1 drivers -v0x1c699f0_0 .net *"_s8", 0 0, L_0x1e301d0; 1 drivers -v0x1c69ad0_0 .net "out", 7 0, L_0x1e312b0; alias, 1 drivers -L_0x1e2fc30 .part L_0x1ec0b60, 0, 1; -L_0x1e2fd90 .part v0x1d6daa0_0, 0, 1; -L_0x1e2ff40 .part L_0x1ec0b60, 1, 1; -L_0x1e30130 .part v0x1d6daa0_0, 1, 1; -L_0x1e30290 .part L_0x1ec0b60, 2, 1; -L_0x1e303f0 .part v0x1d6daa0_0, 2, 1; -L_0x1e305a0 .part L_0x1ec0b60, 3, 1; -L_0x1e30700 .part v0x1d6daa0_0, 3, 1; -L_0x1e30900 .part L_0x1ec0b60, 4, 1; -L_0x1e30a60 .part v0x1d6daa0_0, 4, 1; -L_0x1e30bf0 .part L_0x1ec0b60, 5, 1; -L_0x1e30e60 .part v0x1d6daa0_0, 5, 1; -L_0x1e31060 .part L_0x1ec0b60, 6, 1; -L_0x1e311c0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e312b0_0_0 .concat8 [ 1 1 1 1], L_0x1e2fb70, L_0x1e2fe80, L_0x1e301d0, L_0x1e304e0; -LS_0x1e312b0_0_4 .concat8 [ 1 1 1 1], L_0x1e30840, L_0x1e30b50, L_0x1e30f70, L_0x1e30f00; -L_0x1e312b0 .concat8 [ 4 4 0 0], LS_0x1e312b0_0_0, LS_0x1e312b0_0_4; -L_0x1e31670 .part L_0x1ec0b60, 7, 1; -L_0x1e31860 .part v0x1d6daa0_0, 7, 1; -S_0x1c66c80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c66e90 .param/l "i" 0 4 54, +C4<00>; -L_0x1e2fb70/d .functor AND 1, L_0x1e2fc30, L_0x1e2fd90, C4<1>, C4<1>; -L_0x1e2fb70 .delay 1 (30000,30000,30000) L_0x1e2fb70/d; -v0x1c66f70_0 .net *"_s0", 0 0, L_0x1e2fc30; 1 drivers -v0x1c67050_0 .net *"_s1", 0 0, L_0x1e2fd90; 1 drivers -S_0x1c67130 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c67340 .param/l "i" 0 4 54, +C4<01>; -L_0x1e2fe80/d .functor AND 1, L_0x1e2ff40, L_0x1e30130, C4<1>, C4<1>; -L_0x1e2fe80 .delay 1 (30000,30000,30000) L_0x1e2fe80/d; -v0x1c67400_0 .net *"_s0", 0 0, L_0x1e2ff40; 1 drivers -v0x1c674e0_0 .net *"_s1", 0 0, L_0x1e30130; 1 drivers -S_0x1c675c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c677d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e301d0/d .functor AND 1, L_0x1e30290, L_0x1e303f0, C4<1>, C4<1>; -L_0x1e301d0 .delay 1 (30000,30000,30000) L_0x1e301d0/d; -v0x1c67870_0 .net *"_s0", 0 0, L_0x1e30290; 1 drivers -v0x1c67950_0 .net *"_s1", 0 0, L_0x1e303f0; 1 drivers -S_0x1c67a30 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c67c40 .param/l "i" 0 4 54, +C4<011>; -L_0x1e304e0/d .functor AND 1, L_0x1e305a0, L_0x1e30700, C4<1>, C4<1>; -L_0x1e304e0 .delay 1 (30000,30000,30000) L_0x1e304e0/d; -v0x1c67d00_0 .net *"_s0", 0 0, L_0x1e305a0; 1 drivers -v0x1c67de0_0 .net *"_s1", 0 0, L_0x1e30700; 1 drivers -S_0x1c67ec0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c68120 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e30840/d .functor AND 1, L_0x1e30900, L_0x1e30a60, C4<1>, C4<1>; -L_0x1e30840 .delay 1 (30000,30000,30000) L_0x1e30840/d; -v0x1c681e0_0 .net *"_s0", 0 0, L_0x1e30900; 1 drivers -v0x1c682c0_0 .net *"_s1", 0 0, L_0x1e30a60; 1 drivers -S_0x1c683a0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c685b0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e30b50/d .functor AND 1, L_0x1e30bf0, L_0x1e30e60, C4<1>, C4<1>; -L_0x1e30b50 .delay 1 (30000,30000,30000) L_0x1e30b50/d; -v0x1c68670_0 .net *"_s0", 0 0, L_0x1e30bf0; 1 drivers -v0x1c68750_0 .net *"_s1", 0 0, L_0x1e30e60; 1 drivers -S_0x1c68830 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c68a40 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e30f70/d .functor AND 1, L_0x1e31060, L_0x1e311c0, C4<1>, C4<1>; -L_0x1e30f70 .delay 1 (30000,30000,30000) L_0x1e30f70/d; -v0x1c68b00_0 .net *"_s0", 0 0, L_0x1e31060; 1 drivers -v0x1c68be0_0 .net *"_s1", 0 0, L_0x1e311c0; 1 drivers -S_0x1c68cc0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c66a20; - .timescale -9 -12; -P_0x1c68ed0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e30f00/d .functor AND 1, L_0x1e31670, L_0x1e31860, C4<1>, C4<1>; -L_0x1e30f00 .delay 1 (30000,30000,30000) L_0x1e30f00/d; -v0x1c68f90_0 .net *"_s0", 0 0, L_0x1e31670; 1 drivers -v0x1c69070_0 .net *"_s1", 0 0, L_0x1e31860; 1 drivers -S_0x1c69c30 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c66800; +v0x10fbde0_0 .net "A", 7 0, L_0x1354e90; alias, 1 drivers +v0x10fbee0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x10fbfa0_0 .net *"_s0", 0 0, L_0x12c33d0; 1 drivers +v0x10fc060_0 .net *"_s12", 0 0, L_0x12c3d40; 1 drivers +v0x10fc140_0 .net *"_s16", 0 0, L_0x12c40a0; 1 drivers +v0x10fc270_0 .net *"_s20", 0 0, L_0x12c43b0; 1 drivers +v0x10fc350_0 .net *"_s24", 0 0, L_0x12c47a0; 1 drivers +v0x10fc430_0 .net *"_s28", 0 0, L_0x12c4730; 1 drivers +v0x10fc510_0 .net *"_s4", 0 0, L_0x12c36e0; 1 drivers +v0x10fc680_0 .net *"_s8", 0 0, L_0x12c3a30; 1 drivers +v0x10fc760_0 .net "out", 7 0, L_0x12c4ab0; alias, 1 drivers +L_0x12c3490 .part L_0x1354e90, 0, 1; +L_0x12c35f0 .part v0x12010b0_0, 0, 1; +L_0x12c37a0 .part L_0x1354e90, 1, 1; +L_0x12c3990 .part v0x12010b0_0, 1, 1; +L_0x12c3af0 .part L_0x1354e90, 2, 1; +L_0x12c3c50 .part v0x12010b0_0, 2, 1; +L_0x12c3e00 .part L_0x1354e90, 3, 1; +L_0x12c3f60 .part v0x12010b0_0, 3, 1; +L_0x12c4160 .part L_0x1354e90, 4, 1; +L_0x12c42c0 .part v0x12010b0_0, 4, 1; +L_0x12c4420 .part L_0x1354e90, 5, 1; +L_0x12c4690 .part v0x12010b0_0, 5, 1; +L_0x12c4860 .part L_0x1354e90, 6, 1; +L_0x12c49c0 .part v0x12010b0_0, 6, 1; +LS_0x12c4ab0_0_0 .concat8 [ 1 1 1 1], L_0x12c33d0, L_0x12c36e0, L_0x12c3a30, L_0x12c3d40; +LS_0x12c4ab0_0_4 .concat8 [ 1 1 1 1], L_0x12c40a0, L_0x12c43b0, L_0x12c47a0, L_0x12c4730; +L_0x12c4ab0 .concat8 [ 4 4 0 0], LS_0x12c4ab0_0_0, LS_0x12c4ab0_0_4; +L_0x12c4e70 .part L_0x1354e90, 7, 1; +L_0x12c5060 .part v0x12010b0_0, 7, 1; +S_0x10f9910 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10f9b20 .param/l "i" 0 4 54, +C4<00>; +L_0x12c33d0/d .functor AND 1, L_0x12c3490, L_0x12c35f0, C4<1>, C4<1>; +L_0x12c33d0 .delay 1 (30000,30000,30000) L_0x12c33d0/d; +v0x10f9c00_0 .net *"_s0", 0 0, L_0x12c3490; 1 drivers +v0x10f9ce0_0 .net *"_s1", 0 0, L_0x12c35f0; 1 drivers +S_0x10f9dc0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10f9fd0 .param/l "i" 0 4 54, +C4<01>; +L_0x12c36e0/d .functor AND 1, L_0x12c37a0, L_0x12c3990, C4<1>, C4<1>; +L_0x12c36e0 .delay 1 (30000,30000,30000) L_0x12c36e0/d; +v0x10fa090_0 .net *"_s0", 0 0, L_0x12c37a0; 1 drivers +v0x10fa170_0 .net *"_s1", 0 0, L_0x12c3990; 1 drivers +S_0x10fa250 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10fa460 .param/l "i" 0 4 54, +C4<010>; +L_0x12c3a30/d .functor AND 1, L_0x12c3af0, L_0x12c3c50, C4<1>, C4<1>; +L_0x12c3a30 .delay 1 (30000,30000,30000) L_0x12c3a30/d; +v0x10fa500_0 .net *"_s0", 0 0, L_0x12c3af0; 1 drivers +v0x10fa5e0_0 .net *"_s1", 0 0, L_0x12c3c50; 1 drivers +S_0x10fa6c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10fa8d0 .param/l "i" 0 4 54, +C4<011>; +L_0x12c3d40/d .functor AND 1, L_0x12c3e00, L_0x12c3f60, C4<1>, C4<1>; +L_0x12c3d40 .delay 1 (30000,30000,30000) L_0x12c3d40/d; +v0x10fa990_0 .net *"_s0", 0 0, L_0x12c3e00; 1 drivers +v0x10faa70_0 .net *"_s1", 0 0, L_0x12c3f60; 1 drivers +S_0x10fab50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10fadb0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12c40a0/d .functor AND 1, L_0x12c4160, L_0x12c42c0, C4<1>, C4<1>; +L_0x12c40a0 .delay 1 (30000,30000,30000) L_0x12c40a0/d; +v0x10fae70_0 .net *"_s0", 0 0, L_0x12c4160; 1 drivers +v0x10faf50_0 .net *"_s1", 0 0, L_0x12c42c0; 1 drivers +S_0x10fb030 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10fb240 .param/l "i" 0 4 54, +C4<0101>; +L_0x12c43b0/d .functor AND 1, L_0x12c4420, L_0x12c4690, C4<1>, C4<1>; +L_0x12c43b0 .delay 1 (30000,30000,30000) L_0x12c43b0/d; +v0x10fb300_0 .net *"_s0", 0 0, L_0x12c4420; 1 drivers +v0x10fb3e0_0 .net *"_s1", 0 0, L_0x12c4690; 1 drivers +S_0x10fb4c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10fb6d0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12c47a0/d .functor AND 1, L_0x12c4860, L_0x12c49c0, C4<1>, C4<1>; +L_0x12c47a0 .delay 1 (30000,30000,30000) L_0x12c47a0/d; +v0x10fb790_0 .net *"_s0", 0 0, L_0x12c4860; 1 drivers +v0x10fb870_0 .net *"_s1", 0 0, L_0x12c49c0; 1 drivers +S_0x10fb950 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10f96b0; + .timescale -9 -12; +P_0x10fbb60 .param/l "i" 0 4 54, +C4<0111>; +L_0x12c4730/d .functor AND 1, L_0x12c4e70, L_0x12c5060, C4<1>, C4<1>; +L_0x12c4730 .delay 1 (30000,30000,30000) L_0x12c4730/d; +v0x10fbc20_0 .net *"_s0", 0 0, L_0x12c4e70; 1 drivers +v0x10fbd00_0 .net *"_s1", 0 0, L_0x12c5060; 1 drivers +S_0x10fc8c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10f9490; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e332b0/d .functor OR 1, L_0x1e33370, L_0x1e33520, C4<0>, C4<0>; -L_0x1e332b0 .delay 1 (30000,30000,30000) L_0x1e332b0/d; -v0x1c6b780_0 .net *"_s10", 0 0, L_0x1e33370; 1 drivers -v0x1c6b860_0 .net *"_s12", 0 0, L_0x1e33520; 1 drivers -v0x1c6b940_0 .net "in", 7 0, L_0x1e312b0; alias, 1 drivers -v0x1c6ba10_0 .net "ors", 1 0, L_0x1e330d0; 1 drivers -v0x1c6bad0_0 .net "out", 0 0, L_0x1e332b0; alias, 1 drivers -L_0x1e324a0 .part L_0x1e312b0, 0, 4; -L_0x1e330d0 .concat8 [ 1 1 0 0], L_0x1e32190, L_0x1e32dc0; -L_0x1e33210 .part L_0x1e312b0, 4, 4; -L_0x1e33370 .part L_0x1e330d0, 0, 1; -L_0x1e33520 .part L_0x1e330d0, 1, 1; -S_0x1c69df0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c69c30; +L_0x12c6ab0/d .functor OR 1, L_0x12c6b70, L_0x12c6d20, C4<0>, C4<0>; +L_0x12c6ab0 .delay 1 (30000,30000,30000) L_0x12c6ab0/d; +v0x10fe410_0 .net *"_s10", 0 0, L_0x12c6b70; 1 drivers +v0x10fe4f0_0 .net *"_s12", 0 0, L_0x12c6d20; 1 drivers +v0x10fe5d0_0 .net "in", 7 0, L_0x12c4ab0; alias, 1 drivers +v0x10fe6a0_0 .net "ors", 1 0, L_0x12c68d0; 1 drivers +v0x10fe760_0 .net "out", 0 0, L_0x12c6ab0; alias, 1 drivers +L_0x12c5ca0 .part L_0x12c4ab0, 0, 4; +L_0x12c68d0 .concat8 [ 1 1 0 0], L_0x12c5990, L_0x12c65c0; +L_0x12c6a10 .part L_0x12c4ab0, 4, 4; +L_0x12c6b70 .part L_0x12c68d0, 0, 1; +L_0x12c6d20 .part L_0x12c68d0, 1, 1; +S_0x10fca80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10fc8c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e31950/d .functor OR 1, L_0x1e31a10, L_0x1e31b70, C4<0>, C4<0>; -L_0x1e31950 .delay 1 (30000,30000,30000) L_0x1e31950/d; -L_0x1e31da0/d .functor OR 1, L_0x1e31eb0, L_0x1e32010, C4<0>, C4<0>; -L_0x1e31da0 .delay 1 (30000,30000,30000) L_0x1e31da0/d; -L_0x1e32190/d .functor OR 1, L_0x1e32200, L_0x1e323b0, C4<0>, C4<0>; -L_0x1e32190 .delay 1 (30000,30000,30000) L_0x1e32190/d; -v0x1c6a040_0 .net *"_s0", 0 0, L_0x1e31950; 1 drivers -v0x1c6a140_0 .net *"_s10", 0 0, L_0x1e31eb0; 1 drivers -v0x1c6a220_0 .net *"_s12", 0 0, L_0x1e32010; 1 drivers -v0x1c6a2e0_0 .net *"_s14", 0 0, L_0x1e32200; 1 drivers -v0x1c6a3c0_0 .net *"_s16", 0 0, L_0x1e323b0; 1 drivers -v0x1c6a4f0_0 .net *"_s3", 0 0, L_0x1e31a10; 1 drivers -v0x1c6a5d0_0 .net *"_s5", 0 0, L_0x1e31b70; 1 drivers -v0x1c6a6b0_0 .net *"_s6", 0 0, L_0x1e31da0; 1 drivers -v0x1c6a790_0 .net "in", 3 0, L_0x1e324a0; 1 drivers -v0x1c6a900_0 .net "ors", 1 0, L_0x1e31cb0; 1 drivers -v0x1c6a9e0_0 .net "out", 0 0, L_0x1e32190; 1 drivers -L_0x1e31a10 .part L_0x1e324a0, 0, 1; -L_0x1e31b70 .part L_0x1e324a0, 1, 1; -L_0x1e31cb0 .concat8 [ 1 1 0 0], L_0x1e31950, L_0x1e31da0; -L_0x1e31eb0 .part L_0x1e324a0, 2, 1; -L_0x1e32010 .part L_0x1e324a0, 3, 1; -L_0x1e32200 .part L_0x1e31cb0, 0, 1; -L_0x1e323b0 .part L_0x1e31cb0, 1, 1; -S_0x1c6ab00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c69c30; +L_0x12c5150/d .functor OR 1, L_0x12c5210, L_0x12c5370, C4<0>, C4<0>; +L_0x12c5150 .delay 1 (30000,30000,30000) L_0x12c5150/d; +L_0x12c55a0/d .functor OR 1, L_0x12c56b0, L_0x12c5810, C4<0>, C4<0>; +L_0x12c55a0 .delay 1 (30000,30000,30000) L_0x12c55a0/d; +L_0x12c5990/d .functor OR 1, L_0x12c5a00, L_0x12c5bb0, C4<0>, C4<0>; +L_0x12c5990 .delay 1 (30000,30000,30000) L_0x12c5990/d; +v0x10fccd0_0 .net *"_s0", 0 0, L_0x12c5150; 1 drivers +v0x10fcdd0_0 .net *"_s10", 0 0, L_0x12c56b0; 1 drivers +v0x10fceb0_0 .net *"_s12", 0 0, L_0x12c5810; 1 drivers +v0x10fcf70_0 .net *"_s14", 0 0, L_0x12c5a00; 1 drivers +v0x10fd050_0 .net *"_s16", 0 0, L_0x12c5bb0; 1 drivers +v0x10fd180_0 .net *"_s3", 0 0, L_0x12c5210; 1 drivers +v0x10fd260_0 .net *"_s5", 0 0, L_0x12c5370; 1 drivers +v0x10fd340_0 .net *"_s6", 0 0, L_0x12c55a0; 1 drivers +v0x10fd420_0 .net "in", 3 0, L_0x12c5ca0; 1 drivers +v0x10fd590_0 .net "ors", 1 0, L_0x12c54b0; 1 drivers +v0x10fd670_0 .net "out", 0 0, L_0x12c5990; 1 drivers +L_0x12c5210 .part L_0x12c5ca0, 0, 1; +L_0x12c5370 .part L_0x12c5ca0, 1, 1; +L_0x12c54b0 .concat8 [ 1 1 0 0], L_0x12c5150, L_0x12c55a0; +L_0x12c56b0 .part L_0x12c5ca0, 2, 1; +L_0x12c5810 .part L_0x12c5ca0, 3, 1; +L_0x12c5a00 .part L_0x12c54b0, 0, 1; +L_0x12c5bb0 .part L_0x12c54b0, 1, 1; +S_0x10fd790 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10fc8c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e325d0/d .functor OR 1, L_0x1e32640, L_0x1e327a0, C4<0>, C4<0>; -L_0x1e325d0 .delay 1 (30000,30000,30000) L_0x1e325d0/d; -L_0x1e329d0/d .functor OR 1, L_0x1e32ae0, L_0x1e32c40, C4<0>, C4<0>; -L_0x1e329d0 .delay 1 (30000,30000,30000) L_0x1e329d0/d; -L_0x1e32dc0/d .functor OR 1, L_0x1e32e30, L_0x1e32fe0, C4<0>, C4<0>; -L_0x1e32dc0 .delay 1 (30000,30000,30000) L_0x1e32dc0/d; -v0x1c6acc0_0 .net *"_s0", 0 0, L_0x1e325d0; 1 drivers -v0x1c6adc0_0 .net *"_s10", 0 0, L_0x1e32ae0; 1 drivers -v0x1c6aea0_0 .net *"_s12", 0 0, L_0x1e32c40; 1 drivers -v0x1c6af60_0 .net *"_s14", 0 0, L_0x1e32e30; 1 drivers -v0x1c6b040_0 .net *"_s16", 0 0, L_0x1e32fe0; 1 drivers -v0x1c6b170_0 .net *"_s3", 0 0, L_0x1e32640; 1 drivers -v0x1c6b250_0 .net *"_s5", 0 0, L_0x1e327a0; 1 drivers -v0x1c6b330_0 .net *"_s6", 0 0, L_0x1e329d0; 1 drivers -v0x1c6b410_0 .net "in", 3 0, L_0x1e33210; 1 drivers -v0x1c6b580_0 .net "ors", 1 0, L_0x1e328e0; 1 drivers -v0x1c6b660_0 .net "out", 0 0, L_0x1e32dc0; 1 drivers -L_0x1e32640 .part L_0x1e33210, 0, 1; -L_0x1e327a0 .part L_0x1e33210, 1, 1; -L_0x1e328e0 .concat8 [ 1 1 0 0], L_0x1e325d0, L_0x1e329d0; -L_0x1e32ae0 .part L_0x1e33210, 2, 1; -L_0x1e32c40 .part L_0x1e33210, 3, 1; -L_0x1e32e30 .part L_0x1e328e0, 0, 1; -L_0x1e32fe0 .part L_0x1e328e0, 1, 1; -S_0x1c6bf70 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c650a0; +L_0x12c5dd0/d .functor OR 1, L_0x12c5e40, L_0x12c5fa0, C4<0>, C4<0>; +L_0x12c5dd0 .delay 1 (30000,30000,30000) L_0x12c5dd0/d; +L_0x12c61d0/d .functor OR 1, L_0x12c62e0, L_0x12c6440, C4<0>, C4<0>; +L_0x12c61d0 .delay 1 (30000,30000,30000) L_0x12c61d0/d; +L_0x12c65c0/d .functor OR 1, L_0x12c6630, L_0x12c67e0, C4<0>, C4<0>; +L_0x12c65c0 .delay 1 (30000,30000,30000) L_0x12c65c0/d; +v0x10fd950_0 .net *"_s0", 0 0, L_0x12c5dd0; 1 drivers +v0x10fda50_0 .net *"_s10", 0 0, L_0x12c62e0; 1 drivers +v0x10fdb30_0 .net *"_s12", 0 0, L_0x12c6440; 1 drivers +v0x10fdbf0_0 .net *"_s14", 0 0, L_0x12c6630; 1 drivers +v0x10fdcd0_0 .net *"_s16", 0 0, L_0x12c67e0; 1 drivers +v0x10fde00_0 .net *"_s3", 0 0, L_0x12c5e40; 1 drivers +v0x10fdee0_0 .net *"_s5", 0 0, L_0x12c5fa0; 1 drivers +v0x10fdfc0_0 .net *"_s6", 0 0, L_0x12c61d0; 1 drivers +v0x10fe0a0_0 .net "in", 3 0, L_0x12c6a10; 1 drivers +v0x10fe210_0 .net "ors", 1 0, L_0x12c60e0; 1 drivers +v0x10fe2f0_0 .net "out", 0 0, L_0x12c65c0; 1 drivers +L_0x12c5e40 .part L_0x12c6a10, 0, 1; +L_0x12c5fa0 .part L_0x12c6a10, 1, 1; +L_0x12c60e0 .concat8 [ 1 1 0 0], L_0x12c5dd0, L_0x12c61d0; +L_0x12c62e0 .part L_0x12c6a10, 2, 1; +L_0x12c6440 .part L_0x12c6a10, 3, 1; +L_0x12c6630 .part L_0x12c60e0, 0, 1; +L_0x12c67e0 .part L_0x12c60e0, 1, 1; +S_0x10fec00 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10f7d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c713b0_0 .net "ands", 7 0, L_0x1e2d810; 1 drivers -v0x1c714c0_0 .net "in", 7 0, L_0x1e2bc70; alias, 1 drivers -v0x1c71580_0 .net "out", 0 0, L_0x1e2f810; alias, 1 drivers -v0x1c71650_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c6c1c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c6bf70; +v0x1104030_0 .net "ands", 7 0, L_0x12c1070; 1 drivers +v0x1104140_0 .net "in", 7 0, L_0x12bf4d0; alias, 1 drivers +v0x1104200_0 .net "out", 0 0, L_0x12c3070; alias, 1 drivers +v0x11042d0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x10fee50 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10fec00; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c6e900_0 .net "A", 7 0, L_0x1e2bc70; alias, 1 drivers -v0x1c6ea00_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c6eac0_0 .net *"_s0", 0 0, L_0x1e2c000; 1 drivers -v0x1c6eb80_0 .net *"_s12", 0 0, L_0x1e2c9c0; 1 drivers -v0x1c6ec60_0 .net *"_s16", 0 0, L_0x1e2cd20; 1 drivers -v0x1c6ed90_0 .net *"_s20", 0 0, L_0x1e2d150; 1 drivers -v0x1c6ee70_0 .net *"_s24", 0 0, L_0x1e2d480; 1 drivers -v0x1c6ef50_0 .net *"_s28", 0 0, L_0x1e2d410; 1 drivers -v0x1c6f030_0 .net *"_s4", 0 0, L_0x1e2c3a0; 1 drivers -v0x1c6f1a0_0 .net *"_s8", 0 0, L_0x1e2c6b0; 1 drivers -v0x1c6f280_0 .net "out", 7 0, L_0x1e2d810; alias, 1 drivers -L_0x1e2c110 .part L_0x1e2bc70, 0, 1; -L_0x1e2c300 .part v0x1d6daa0_0, 0, 1; -L_0x1e2c460 .part L_0x1e2bc70, 1, 1; -L_0x1e2c5c0 .part v0x1d6daa0_0, 1, 1; -L_0x1e2c770 .part L_0x1e2bc70, 2, 1; -L_0x1e2c8d0 .part v0x1d6daa0_0, 2, 1; -L_0x1e2ca80 .part L_0x1e2bc70, 3, 1; -L_0x1e2cbe0 .part v0x1d6daa0_0, 3, 1; -L_0x1e2cde0 .part L_0x1e2bc70, 4, 1; -L_0x1e2d050 .part v0x1d6daa0_0, 4, 1; -L_0x1e2d1c0 .part L_0x1e2bc70, 5, 1; -L_0x1e2d320 .part v0x1d6daa0_0, 5, 1; -L_0x1e2d540 .part L_0x1e2bc70, 6, 1; -L_0x1e2d6a0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e2d810_0_0 .concat8 [ 1 1 1 1], L_0x1e2c000, L_0x1e2c3a0, L_0x1e2c6b0, L_0x1e2c9c0; -LS_0x1e2d810_0_4 .concat8 [ 1 1 1 1], L_0x1e2cd20, L_0x1e2d150, L_0x1e2d480, L_0x1e2d410; -L_0x1e2d810 .concat8 [ 4 4 0 0], LS_0x1e2d810_0_0, LS_0x1e2d810_0_4; -L_0x1e2dbd0 .part L_0x1e2bc70, 7, 1; -L_0x1e2ddc0 .part v0x1d6daa0_0, 7, 1; -S_0x1c6c400 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6c610 .param/l "i" 0 4 54, +C4<00>; -L_0x1e2c000/d .functor AND 1, L_0x1e2c110, L_0x1e2c300, C4<1>, C4<1>; -L_0x1e2c000 .delay 1 (30000,30000,30000) L_0x1e2c000/d; -v0x1c6c6f0_0 .net *"_s0", 0 0, L_0x1e2c110; 1 drivers -v0x1c6c7d0_0 .net *"_s1", 0 0, L_0x1e2c300; 1 drivers -S_0x1c6c8b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6cac0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e2c3a0/d .functor AND 1, L_0x1e2c460, L_0x1e2c5c0, C4<1>, C4<1>; -L_0x1e2c3a0 .delay 1 (30000,30000,30000) L_0x1e2c3a0/d; -v0x1c6cb80_0 .net *"_s0", 0 0, L_0x1e2c460; 1 drivers -v0x1c6cc60_0 .net *"_s1", 0 0, L_0x1e2c5c0; 1 drivers -S_0x1c6cd40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6cf80 .param/l "i" 0 4 54, +C4<010>; -L_0x1e2c6b0/d .functor AND 1, L_0x1e2c770, L_0x1e2c8d0, C4<1>, C4<1>; -L_0x1e2c6b0 .delay 1 (30000,30000,30000) L_0x1e2c6b0/d; -v0x1c6d020_0 .net *"_s0", 0 0, L_0x1e2c770; 1 drivers -v0x1c6d100_0 .net *"_s1", 0 0, L_0x1e2c8d0; 1 drivers -S_0x1c6d1e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6d3f0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e2c9c0/d .functor AND 1, L_0x1e2ca80, L_0x1e2cbe0, C4<1>, C4<1>; -L_0x1e2c9c0 .delay 1 (30000,30000,30000) L_0x1e2c9c0/d; -v0x1c6d4b0_0 .net *"_s0", 0 0, L_0x1e2ca80; 1 drivers -v0x1c6d590_0 .net *"_s1", 0 0, L_0x1e2cbe0; 1 drivers -S_0x1c6d670 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6d8d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e2cd20/d .functor AND 1, L_0x1e2cde0, L_0x1e2d050, C4<1>, C4<1>; -L_0x1e2cd20 .delay 1 (30000,30000,30000) L_0x1e2cd20/d; -v0x1c6d990_0 .net *"_s0", 0 0, L_0x1e2cde0; 1 drivers -v0x1c6da70_0 .net *"_s1", 0 0, L_0x1e2d050; 1 drivers -S_0x1c6db50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6dd60 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e2d150/d .functor AND 1, L_0x1e2d1c0, L_0x1e2d320, C4<1>, C4<1>; -L_0x1e2d150 .delay 1 (30000,30000,30000) L_0x1e2d150/d; -v0x1c6de20_0 .net *"_s0", 0 0, L_0x1e2d1c0; 1 drivers -v0x1c6df00_0 .net *"_s1", 0 0, L_0x1e2d320; 1 drivers -S_0x1c6dfe0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6e1f0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e2d480/d .functor AND 1, L_0x1e2d540, L_0x1e2d6a0, C4<1>, C4<1>; -L_0x1e2d480 .delay 1 (30000,30000,30000) L_0x1e2d480/d; -v0x1c6e2b0_0 .net *"_s0", 0 0, L_0x1e2d540; 1 drivers -v0x1c6e390_0 .net *"_s1", 0 0, L_0x1e2d6a0; 1 drivers -S_0x1c6e470 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c6c1c0; - .timescale -9 -12; -P_0x1c6e680 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e2d410/d .functor AND 1, L_0x1e2dbd0, L_0x1e2ddc0, C4<1>, C4<1>; -L_0x1e2d410 .delay 1 (30000,30000,30000) L_0x1e2d410/d; -v0x1c6e740_0 .net *"_s0", 0 0, L_0x1e2dbd0; 1 drivers -v0x1c6e820_0 .net *"_s1", 0 0, L_0x1e2ddc0; 1 drivers -S_0x1c6f3e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c6bf70; +v0x1101590_0 .net "A", 7 0, L_0x12bf4d0; alias, 1 drivers +v0x1101690_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1101750_0 .net *"_s0", 0 0, L_0x12bf860; 1 drivers +v0x1101810_0 .net *"_s12", 0 0, L_0x12c0220; 1 drivers +v0x11018f0_0 .net *"_s16", 0 0, L_0x12c0580; 1 drivers +v0x1101a20_0 .net *"_s20", 0 0, L_0x12c09b0; 1 drivers +v0x1101b00_0 .net *"_s24", 0 0, L_0x12c0ce0; 1 drivers +v0x1101be0_0 .net *"_s28", 0 0, L_0x12c0c70; 1 drivers +v0x1101cc0_0 .net *"_s4", 0 0, L_0x12bfc00; 1 drivers +v0x1101e30_0 .net *"_s8", 0 0, L_0x12bff10; 1 drivers +v0x1101f10_0 .net "out", 7 0, L_0x12c1070; alias, 1 drivers +L_0x12bf970 .part L_0x12bf4d0, 0, 1; +L_0x12bfb60 .part v0x12010b0_0, 0, 1; +L_0x12bfcc0 .part L_0x12bf4d0, 1, 1; +L_0x12bfe20 .part v0x12010b0_0, 1, 1; +L_0x12bffd0 .part L_0x12bf4d0, 2, 1; +L_0x12c0130 .part v0x12010b0_0, 2, 1; +L_0x12c02e0 .part L_0x12bf4d0, 3, 1; +L_0x12c0440 .part v0x12010b0_0, 3, 1; +L_0x12c0640 .part L_0x12bf4d0, 4, 1; +L_0x12c08b0 .part v0x12010b0_0, 4, 1; +L_0x12c0a20 .part L_0x12bf4d0, 5, 1; +L_0x12c0b80 .part v0x12010b0_0, 5, 1; +L_0x12c0da0 .part L_0x12bf4d0, 6, 1; +L_0x12c0f00 .part v0x12010b0_0, 6, 1; +LS_0x12c1070_0_0 .concat8 [ 1 1 1 1], L_0x12bf860, L_0x12bfc00, L_0x12bff10, L_0x12c0220; +LS_0x12c1070_0_4 .concat8 [ 1 1 1 1], L_0x12c0580, L_0x12c09b0, L_0x12c0ce0, L_0x12c0c70; +L_0x12c1070 .concat8 [ 4 4 0 0], LS_0x12c1070_0_0, LS_0x12c1070_0_4; +L_0x12c1430 .part L_0x12bf4d0, 7, 1; +L_0x12c1620 .part v0x12010b0_0, 7, 1; +S_0x10ff090 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x10ff2a0 .param/l "i" 0 4 54, +C4<00>; +L_0x12bf860/d .functor AND 1, L_0x12bf970, L_0x12bfb60, C4<1>, C4<1>; +L_0x12bf860 .delay 1 (30000,30000,30000) L_0x12bf860/d; +v0x10ff380_0 .net *"_s0", 0 0, L_0x12bf970; 1 drivers +v0x10ff460_0 .net *"_s1", 0 0, L_0x12bfb60; 1 drivers +S_0x10ff540 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x10ff750 .param/l "i" 0 4 54, +C4<01>; +L_0x12bfc00/d .functor AND 1, L_0x12bfcc0, L_0x12bfe20, C4<1>, C4<1>; +L_0x12bfc00 .delay 1 (30000,30000,30000) L_0x12bfc00/d; +v0x10ff810_0 .net *"_s0", 0 0, L_0x12bfcc0; 1 drivers +v0x10ff8f0_0 .net *"_s1", 0 0, L_0x12bfe20; 1 drivers +S_0x10ff9d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x10ffc10 .param/l "i" 0 4 54, +C4<010>; +L_0x12bff10/d .functor AND 1, L_0x12bffd0, L_0x12c0130, C4<1>, C4<1>; +L_0x12bff10 .delay 1 (30000,30000,30000) L_0x12bff10/d; +v0x10ffcb0_0 .net *"_s0", 0 0, L_0x12bffd0; 1 drivers +v0x10ffd90_0 .net *"_s1", 0 0, L_0x12c0130; 1 drivers +S_0x10ffe70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x1100080 .param/l "i" 0 4 54, +C4<011>; +L_0x12c0220/d .functor AND 1, L_0x12c02e0, L_0x12c0440, C4<1>, C4<1>; +L_0x12c0220 .delay 1 (30000,30000,30000) L_0x12c0220/d; +v0x1100140_0 .net *"_s0", 0 0, L_0x12c02e0; 1 drivers +v0x1100220_0 .net *"_s1", 0 0, L_0x12c0440; 1 drivers +S_0x1100300 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x1100560 .param/l "i" 0 4 54, +C4<0100>; +L_0x12c0580/d .functor AND 1, L_0x12c0640, L_0x12c08b0, C4<1>, C4<1>; +L_0x12c0580 .delay 1 (30000,30000,30000) L_0x12c0580/d; +v0x1100620_0 .net *"_s0", 0 0, L_0x12c0640; 1 drivers +v0x1100700_0 .net *"_s1", 0 0, L_0x12c08b0; 1 drivers +S_0x11007e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x11009f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x12c09b0/d .functor AND 1, L_0x12c0a20, L_0x12c0b80, C4<1>, C4<1>; +L_0x12c09b0 .delay 1 (30000,30000,30000) L_0x12c09b0/d; +v0x1100ab0_0 .net *"_s0", 0 0, L_0x12c0a20; 1 drivers +v0x1100b90_0 .net *"_s1", 0 0, L_0x12c0b80; 1 drivers +S_0x1100c70 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x1100e80 .param/l "i" 0 4 54, +C4<0110>; +L_0x12c0ce0/d .functor AND 1, L_0x12c0da0, L_0x12c0f00, C4<1>, C4<1>; +L_0x12c0ce0 .delay 1 (30000,30000,30000) L_0x12c0ce0/d; +v0x1100f40_0 .net *"_s0", 0 0, L_0x12c0da0; 1 drivers +v0x1101020_0 .net *"_s1", 0 0, L_0x12c0f00; 1 drivers +S_0x1101100 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10fee50; + .timescale -9 -12; +P_0x1101310 .param/l "i" 0 4 54, +C4<0111>; +L_0x12c0c70/d .functor AND 1, L_0x12c1430, L_0x12c1620, C4<1>, C4<1>; +L_0x12c0c70 .delay 1 (30000,30000,30000) L_0x12c0c70/d; +v0x11013d0_0 .net *"_s0", 0 0, L_0x12c1430; 1 drivers +v0x11014b0_0 .net *"_s1", 0 0, L_0x12c1620; 1 drivers +S_0x1102070 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10fec00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e2f810/d .functor OR 1, L_0x1e2f8d0, L_0x1e2fa80, C4<0>, C4<0>; -L_0x1e2f810 .delay 1 (30000,30000,30000) L_0x1e2f810/d; -v0x1c70f40_0 .net *"_s10", 0 0, L_0x1e2f8d0; 1 drivers -v0x1c71020_0 .net *"_s12", 0 0, L_0x1e2fa80; 1 drivers -v0x1c71100_0 .net "in", 7 0, L_0x1e2d810; alias, 1 drivers -v0x1c711d0_0 .net "ors", 1 0, L_0x1e2f630; 1 drivers -v0x1c71290_0 .net "out", 0 0, L_0x1e2f810; alias, 1 drivers -L_0x1e2ea00 .part L_0x1e2d810, 0, 4; -L_0x1e2f630 .concat8 [ 1 1 0 0], L_0x1e2e6f0, L_0x1e2f320; -L_0x1e2f770 .part L_0x1e2d810, 4, 4; -L_0x1e2f8d0 .part L_0x1e2f630, 0, 1; -L_0x1e2fa80 .part L_0x1e2f630, 1, 1; -S_0x1c6f5a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c6f3e0; +L_0x12c3070/d .functor OR 1, L_0x12c3130, L_0x12c32e0, C4<0>, C4<0>; +L_0x12c3070 .delay 1 (30000,30000,30000) L_0x12c3070/d; +v0x1103bc0_0 .net *"_s10", 0 0, L_0x12c3130; 1 drivers +v0x1103ca0_0 .net *"_s12", 0 0, L_0x12c32e0; 1 drivers +v0x1103d80_0 .net "in", 7 0, L_0x12c1070; alias, 1 drivers +v0x1103e50_0 .net "ors", 1 0, L_0x12c2e90; 1 drivers +v0x1103f10_0 .net "out", 0 0, L_0x12c3070; alias, 1 drivers +L_0x12c2260 .part L_0x12c1070, 0, 4; +L_0x12c2e90 .concat8 [ 1 1 0 0], L_0x12c1f50, L_0x12c2b80; +L_0x12c2fd0 .part L_0x12c1070, 4, 4; +L_0x12c3130 .part L_0x12c2e90, 0, 1; +L_0x12c32e0 .part L_0x12c2e90, 1, 1; +S_0x1102230 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1102070; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e2deb0/d .functor OR 1, L_0x1e2df70, L_0x1e2e0d0, C4<0>, C4<0>; -L_0x1e2deb0 .delay 1 (30000,30000,30000) L_0x1e2deb0/d; -L_0x1e2e300/d .functor OR 1, L_0x1e2e410, L_0x1e2e570, C4<0>, C4<0>; -L_0x1e2e300 .delay 1 (30000,30000,30000) L_0x1e2e300/d; -L_0x1e2e6f0/d .functor OR 1, L_0x1e2e760, L_0x1e2e910, C4<0>, C4<0>; -L_0x1e2e6f0 .delay 1 (30000,30000,30000) L_0x1e2e6f0/d; -v0x1c6f7f0_0 .net *"_s0", 0 0, L_0x1e2deb0; 1 drivers -v0x1c6f8f0_0 .net *"_s10", 0 0, L_0x1e2e410; 1 drivers -v0x1c6f9d0_0 .net *"_s12", 0 0, L_0x1e2e570; 1 drivers -v0x1c6fa90_0 .net *"_s14", 0 0, L_0x1e2e760; 1 drivers -v0x1c6fb70_0 .net *"_s16", 0 0, L_0x1e2e910; 1 drivers -v0x1c6fca0_0 .net *"_s3", 0 0, L_0x1e2df70; 1 drivers -v0x1c6fd80_0 .net *"_s5", 0 0, L_0x1e2e0d0; 1 drivers -v0x1c6fe60_0 .net *"_s6", 0 0, L_0x1e2e300; 1 drivers -v0x1c6ff40_0 .net "in", 3 0, L_0x1e2ea00; 1 drivers -v0x1c70090_0 .net "ors", 1 0, L_0x1e2e210; 1 drivers -v0x1c70170_0 .net "out", 0 0, L_0x1e2e6f0; 1 drivers -L_0x1e2df70 .part L_0x1e2ea00, 0, 1; -L_0x1e2e0d0 .part L_0x1e2ea00, 1, 1; -L_0x1e2e210 .concat8 [ 1 1 0 0], L_0x1e2deb0, L_0x1e2e300; -L_0x1e2e410 .part L_0x1e2ea00, 2, 1; -L_0x1e2e570 .part L_0x1e2ea00, 3, 1; -L_0x1e2e760 .part L_0x1e2e210, 0, 1; -L_0x1e2e910 .part L_0x1e2e210, 1, 1; -S_0x1c70290 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c6f3e0; +L_0x12c1710/d .functor OR 1, L_0x12c17d0, L_0x12c1930, C4<0>, C4<0>; +L_0x12c1710 .delay 1 (30000,30000,30000) L_0x12c1710/d; +L_0x12c1b60/d .functor OR 1, L_0x12c1c70, L_0x12c1dd0, C4<0>, C4<0>; +L_0x12c1b60 .delay 1 (30000,30000,30000) L_0x12c1b60/d; +L_0x12c1f50/d .functor OR 1, L_0x12c1fc0, L_0x12c2170, C4<0>, C4<0>; +L_0x12c1f50 .delay 1 (30000,30000,30000) L_0x12c1f50/d; +v0x1102480_0 .net *"_s0", 0 0, L_0x12c1710; 1 drivers +v0x1102580_0 .net *"_s10", 0 0, L_0x12c1c70; 1 drivers +v0x1102660_0 .net *"_s12", 0 0, L_0x12c1dd0; 1 drivers +v0x1102720_0 .net *"_s14", 0 0, L_0x12c1fc0; 1 drivers +v0x1102800_0 .net *"_s16", 0 0, L_0x12c2170; 1 drivers +v0x1102930_0 .net *"_s3", 0 0, L_0x12c17d0; 1 drivers +v0x1102a10_0 .net *"_s5", 0 0, L_0x12c1930; 1 drivers +v0x1102af0_0 .net *"_s6", 0 0, L_0x12c1b60; 1 drivers +v0x1102bd0_0 .net "in", 3 0, L_0x12c2260; 1 drivers +v0x1102d40_0 .net "ors", 1 0, L_0x12c1a70; 1 drivers +v0x1102e20_0 .net "out", 0 0, L_0x12c1f50; 1 drivers +L_0x12c17d0 .part L_0x12c2260, 0, 1; +L_0x12c1930 .part L_0x12c2260, 1, 1; +L_0x12c1a70 .concat8 [ 1 1 0 0], L_0x12c1710, L_0x12c1b60; +L_0x12c1c70 .part L_0x12c2260, 2, 1; +L_0x12c1dd0 .part L_0x12c2260, 3, 1; +L_0x12c1fc0 .part L_0x12c1a70, 0, 1; +L_0x12c2170 .part L_0x12c1a70, 1, 1; +S_0x1102f40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1102070; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e2eb30/d .functor OR 1, L_0x1e2eba0, L_0x1e2ed00, C4<0>, C4<0>; -L_0x1e2eb30 .delay 1 (30000,30000,30000) L_0x1e2eb30/d; -L_0x1e2ef30/d .functor OR 1, L_0x1e2f040, L_0x1e2f1a0, C4<0>, C4<0>; -L_0x1e2ef30 .delay 1 (30000,30000,30000) L_0x1e2ef30/d; -L_0x1e2f320/d .functor OR 1, L_0x1e2f390, L_0x1e2f540, C4<0>, C4<0>; -L_0x1e2f320 .delay 1 (30000,30000,30000) L_0x1e2f320/d; -v0x1c70450_0 .net *"_s0", 0 0, L_0x1e2eb30; 1 drivers -v0x1c70550_0 .net *"_s10", 0 0, L_0x1e2f040; 1 drivers -v0x1c70630_0 .net *"_s12", 0 0, L_0x1e2f1a0; 1 drivers -v0x1c70720_0 .net *"_s14", 0 0, L_0x1e2f390; 1 drivers -v0x1c70800_0 .net *"_s16", 0 0, L_0x1e2f540; 1 drivers -v0x1c70930_0 .net *"_s3", 0 0, L_0x1e2eba0; 1 drivers -v0x1c70a10_0 .net *"_s5", 0 0, L_0x1e2ed00; 1 drivers -v0x1c70af0_0 .net *"_s6", 0 0, L_0x1e2ef30; 1 drivers -v0x1c70bd0_0 .net "in", 3 0, L_0x1e2f770; 1 drivers -v0x1c70d40_0 .net "ors", 1 0, L_0x1e2ee40; 1 drivers -v0x1c70e20_0 .net "out", 0 0, L_0x1e2f320; 1 drivers -L_0x1e2eba0 .part L_0x1e2f770, 0, 1; -L_0x1e2ed00 .part L_0x1e2f770, 1, 1; -L_0x1e2ee40 .concat8 [ 1 1 0 0], L_0x1e2eb30, L_0x1e2ef30; -L_0x1e2f040 .part L_0x1e2f770, 2, 1; -L_0x1e2f1a0 .part L_0x1e2f770, 3, 1; -L_0x1e2f390 .part L_0x1e2ee40, 0, 1; -L_0x1e2f540 .part L_0x1e2ee40, 1, 1; -S_0x1c71730 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c650a0; +L_0x12c2390/d .functor OR 1, L_0x12c2400, L_0x12c2560, C4<0>, C4<0>; +L_0x12c2390 .delay 1 (30000,30000,30000) L_0x12c2390/d; +L_0x12c2790/d .functor OR 1, L_0x12c28a0, L_0x12c2a00, C4<0>, C4<0>; +L_0x12c2790 .delay 1 (30000,30000,30000) L_0x12c2790/d; +L_0x12c2b80/d .functor OR 1, L_0x12c2bf0, L_0x12c2da0, C4<0>, C4<0>; +L_0x12c2b80 .delay 1 (30000,30000,30000) L_0x12c2b80/d; +v0x1103100_0 .net *"_s0", 0 0, L_0x12c2390; 1 drivers +v0x1103200_0 .net *"_s10", 0 0, L_0x12c28a0; 1 drivers +v0x11032e0_0 .net *"_s12", 0 0, L_0x12c2a00; 1 drivers +v0x11033a0_0 .net *"_s14", 0 0, L_0x12c2bf0; 1 drivers +v0x1103480_0 .net *"_s16", 0 0, L_0x12c2da0; 1 drivers +v0x11035b0_0 .net *"_s3", 0 0, L_0x12c2400; 1 drivers +v0x1103690_0 .net *"_s5", 0 0, L_0x12c2560; 1 drivers +v0x1103770_0 .net *"_s6", 0 0, L_0x12c2790; 1 drivers +v0x1103850_0 .net "in", 3 0, L_0x12c2fd0; 1 drivers +v0x11039c0_0 .net "ors", 1 0, L_0x12c26a0; 1 drivers +v0x1103aa0_0 .net "out", 0 0, L_0x12c2b80; 1 drivers +L_0x12c2400 .part L_0x12c2fd0, 0, 1; +L_0x12c2560 .part L_0x12c2fd0, 1, 1; +L_0x12c26a0 .concat8 [ 1 1 0 0], L_0x12c2390, L_0x12c2790; +L_0x12c28a0 .part L_0x12c2fd0, 2, 1; +L_0x12c2a00 .part L_0x12c2fd0, 3, 1; +L_0x12c2bf0 .part L_0x12c26a0, 0, 1; +L_0x12c2da0 .part L_0x12c26a0, 1, 1; +S_0x11043b0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10f7d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -10732,80 +10742,80 @@ S_0x1c71730 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c650a0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e2afe0/d .functor XNOR 1, L_0x1e33710, L_0x1e29cb0, C4<0>, C4<0>; -L_0x1e2afe0 .delay 1 (20000,20000,20000) L_0x1e2afe0/d; -L_0x1e2b250/d .functor AND 1, L_0x1e33710, L_0x1e29f20, C4<1>, C4<1>; -L_0x1e2b250 .delay 1 (30000,30000,30000) L_0x1e2b250/d; -L_0x1e2b2c0/d .functor AND 1, L_0x1e2afe0, L_0x1e29d50, C4<1>, C4<1>; -L_0x1e2b2c0 .delay 1 (30000,30000,30000) L_0x1e2b2c0/d; -L_0x1e2b420/d .functor OR 1, L_0x1e2b2c0, L_0x1e2b250, C4<0>, C4<0>; -L_0x1e2b420 .delay 1 (30000,30000,30000) L_0x1e2b420/d; -v0x1c719e0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers -v0x1c71ad0_0 .net "a_", 0 0, L_0x1e23b90; alias, 1 drivers -v0x1c71b90_0 .net "b", 0 0, L_0x1e29cb0; alias, 1 drivers -v0x1c71c80_0 .net "b_", 0 0, L_0x1e29f20; alias, 1 drivers -v0x1c71d20_0 .net "carryin", 0 0, L_0x1e29d50; alias, 1 drivers -v0x1c71e60_0 .net "eq", 0 0, L_0x1e2afe0; 1 drivers -v0x1c71f20_0 .net "lt", 0 0, L_0x1e2b250; 1 drivers -v0x1c71fe0_0 .net "out", 0 0, L_0x1e2b420; 1 drivers -v0x1c720a0_0 .net "w0", 0 0, L_0x1e2b2c0; 1 drivers -S_0x1c722f0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c650a0; +L_0x12be840/d .functor XNOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; +L_0x12be840 .delay 1 (20000,20000,20000) L_0x12be840/d; +L_0x12beab0/d .functor AND 1, L_0x12c6f10, L_0x12bd780, C4<1>, C4<1>; +L_0x12beab0 .delay 1 (30000,30000,30000) L_0x12beab0/d; +L_0x12beb20/d .functor AND 1, L_0x12be840, L_0x12bd5b0, C4<1>, C4<1>; +L_0x12beb20 .delay 1 (30000,30000,30000) L_0x12beb20/d; +L_0x12bec80/d .functor OR 1, L_0x12beb20, L_0x12beab0, C4<0>, C4<0>; +L_0x12bec80 .delay 1 (30000,30000,30000) L_0x12bec80/d; +v0x1104660_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers +v0x1104750_0 .net "a_", 0 0, L_0x12b7300; alias, 1 drivers +v0x1104810_0 .net "b", 0 0, L_0x12bd510; alias, 1 drivers +v0x1104900_0 .net "b_", 0 0, L_0x12bd780; alias, 1 drivers +v0x11049a0_0 .net "carryin", 0 0, L_0x12bd5b0; alias, 1 drivers +v0x1104ae0_0 .net "eq", 0 0, L_0x12be840; 1 drivers +v0x1104ba0_0 .net "lt", 0 0, L_0x12beab0; 1 drivers +v0x1104c60_0 .net "out", 0 0, L_0x12bec80; 1 drivers +v0x1104d20_0 .net "w0", 0 0, L_0x12beb20; 1 drivers +S_0x1104f70 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10f7d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e2adc0/d .functor OR 1, L_0x1e2a910, L_0x1c73550, C4<0>, C4<0>; -L_0x1e2adc0 .delay 1 (30000,30000,30000) L_0x1e2adc0/d; -v0x1c730e0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers -v0x1c73230_0 .net "b", 0 0, L_0x1e29f20; alias, 1 drivers -v0x1c732f0_0 .net "c1", 0 0, L_0x1e2a910; 1 drivers -v0x1c73390_0 .net "c2", 0 0, L_0x1c73550; 1 drivers -v0x1c73460_0 .net "carryin", 0 0, L_0x1e29d50; alias, 1 drivers -v0x1c735e0_0 .net "carryout", 0 0, L_0x1e2adc0; 1 drivers -v0x1c73680_0 .net "s1", 0 0, L_0x1e2a850; 1 drivers -v0x1c73720_0 .net "sum", 0 0, L_0x1e2aa70; 1 drivers -S_0x1c72540 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c722f0; +L_0x12be620/d .functor OR 1, L_0x12be170, L_0x11061d0, C4<0>, C4<0>; +L_0x12be620 .delay 1 (30000,30000,30000) L_0x12be620/d; +v0x1105d60_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers +v0x1105eb0_0 .net "b", 0 0, L_0x12bd780; alias, 1 drivers +v0x1105f70_0 .net "c1", 0 0, L_0x12be170; 1 drivers +v0x1106010_0 .net "c2", 0 0, L_0x11061d0; 1 drivers +v0x11060e0_0 .net "carryin", 0 0, L_0x12bd5b0; alias, 1 drivers +v0x1106260_0 .net "carryout", 0 0, L_0x12be620; 1 drivers +v0x1106300_0 .net "s1", 0 0, L_0x12be0b0; 1 drivers +v0x11063a0_0 .net "sum", 0 0, L_0x12be2d0; 1 drivers +S_0x11051c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1104f70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e2a850/d .functor XOR 1, L_0x1e33710, L_0x1e29f20, C4<0>, C4<0>; -L_0x1e2a850 .delay 1 (30000,30000,30000) L_0x1e2a850/d; -L_0x1e2a910/d .functor AND 1, L_0x1e33710, L_0x1e29f20, C4<1>, C4<1>; -L_0x1e2a910 .delay 1 (30000,30000,30000) L_0x1e2a910/d; -v0x1c727a0_0 .net "a", 0 0, L_0x1e33710; alias, 1 drivers -v0x1c72860_0 .net "b", 0 0, L_0x1e29f20; alias, 1 drivers -v0x1c72920_0 .net "carryout", 0 0, L_0x1e2a910; alias, 1 drivers -v0x1c729c0_0 .net "sum", 0 0, L_0x1e2a850; alias, 1 drivers -S_0x1c72af0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c722f0; +L_0x12be0b0/d .functor XOR 1, L_0x12c6f10, L_0x12bd780, C4<0>, C4<0>; +L_0x12be0b0 .delay 1 (30000,30000,30000) L_0x12be0b0/d; +L_0x12be170/d .functor AND 1, L_0x12c6f10, L_0x12bd780, C4<1>, C4<1>; +L_0x12be170 .delay 1 (30000,30000,30000) L_0x12be170/d; +v0x1105420_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers +v0x11054e0_0 .net "b", 0 0, L_0x12bd780; alias, 1 drivers +v0x11055a0_0 .net "carryout", 0 0, L_0x12be170; alias, 1 drivers +v0x1105640_0 .net "sum", 0 0, L_0x12be0b0; alias, 1 drivers +S_0x1105770 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1104f70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e2aa70/d .functor XOR 1, L_0x1e2a850, L_0x1e29d50, C4<0>, C4<0>; -L_0x1e2aa70 .delay 1 (30000,30000,30000) L_0x1e2aa70/d; -L_0x1c73550/d .functor AND 1, L_0x1e2a850, L_0x1e29d50, C4<1>, C4<1>; -L_0x1c73550 .delay 1 (30000,30000,30000) L_0x1c73550/d; -v0x1c72d50_0 .net "a", 0 0, L_0x1e2a850; alias, 1 drivers -v0x1c72e20_0 .net "b", 0 0, L_0x1e29d50; alias, 1 drivers -v0x1c72ec0_0 .net "carryout", 0 0, L_0x1c73550; alias, 1 drivers -v0x1c72f90_0 .net "sum", 0 0, L_0x1e2aa70; alias, 1 drivers -S_0x1c74b40 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c64dd0; - .timescale -9 -12; -L_0x7f72592db578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db5c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e337b0/d .functor OR 1, L_0x7f72592db578, L_0x7f72592db5c0, C4<0>, C4<0>; -L_0x1e337b0 .delay 1 (30000,30000,30000) L_0x1e337b0/d; -v0x1c74d30_0 .net/2u *"_s0", 0 0, L_0x7f72592db578; 1 drivers -v0x1c74e10_0 .net/2u *"_s2", 0 0, L_0x7f72592db5c0; 1 drivers -S_0x1c74ef0 .scope generate, "alu_slices[20]" "alu_slices[20]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1c75100 .param/l "i" 0 3 37, +C4<010100>; -S_0x1c751c0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c74ef0; +L_0x12be2d0/d .functor XOR 1, L_0x12be0b0, L_0x12bd5b0, C4<0>, C4<0>; +L_0x12be2d0 .delay 1 (30000,30000,30000) L_0x12be2d0/d; +L_0x11061d0/d .functor AND 1, L_0x12be0b0, L_0x12bd5b0, C4<1>, C4<1>; +L_0x11061d0 .delay 1 (30000,30000,30000) L_0x11061d0/d; +v0x11059d0_0 .net "a", 0 0, L_0x12be0b0; alias, 1 drivers +v0x1105aa0_0 .net "b", 0 0, L_0x12bd5b0; alias, 1 drivers +v0x1105b40_0 .net "carryout", 0 0, L_0x11061d0; alias, 1 drivers +v0x1105c10_0 .net "sum", 0 0, L_0x12be2d0; alias, 1 drivers +S_0x11077c0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10f7a60; + .timescale -9 -12; +L_0x2b0ab3d06578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d065c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c6fb0/d .functor OR 1, L_0x2b0ab3d06578, L_0x2b0ab3d065c0, C4<0>, C4<0>; +L_0x12c6fb0 .delay 1 (30000,30000,30000) L_0x12c6fb0/d; +v0x11079b0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06578; 1 drivers +v0x1107a90_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d065c0; 1 drivers +S_0x1107b70 .scope generate, "alu_slices[20]" "alu_slices[20]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1107d80 .param/l "i" 0 3 41, +C4<010100>; +S_0x1107e40 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1107b70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -10814,445 +10824,445 @@ S_0x1c751c0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1c74ef0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e33b00/d .functor NOT 1, L_0x1e3d390, C4<0>, C4<0>, C4<0>; -L_0x1e33b00 .delay 1 (10000,10000,10000) L_0x1e33b00/d; -L_0x1e33c60/d .functor NOT 1, L_0x1e3d4f0, C4<0>, C4<0>, C4<0>; -L_0x1e33c60 .delay 1 (10000,10000,10000) L_0x1e33c60/d; -L_0x1e34cb0/d .functor XOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; -L_0x1e34cb0 .delay 1 (30000,30000,30000) L_0x1e34cb0/d; -L_0x7f72592db608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e35360/d .functor OR 1, L_0x7f72592db608, L_0x7f72592db650, C4<0>, C4<0>; -L_0x1e35360 .delay 1 (30000,30000,30000) L_0x1e35360/d; -L_0x1e35560/d .functor AND 1, L_0x1e3d390, L_0x1e3d4f0, C4<1>, C4<1>; -L_0x1e35560 .delay 1 (30000,30000,30000) L_0x1e35560/d; -L_0x1e35620/d .functor NAND 1, L_0x1e3d390, L_0x1e3d4f0, C4<1>, C4<1>; -L_0x1e35620 .delay 1 (20000,20000,20000) L_0x1e35620/d; -L_0x1e35780/d .functor XOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; -L_0x1e35780 .delay 1 (20000,20000,20000) L_0x1e35780/d; -L_0x1e35c30/d .functor OR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; -L_0x1e35c30 .delay 1 (30000,30000,30000) L_0x1e35c30/d; -L_0x1e3d290/d .functor NOT 1, L_0x1e394c0, C4<0>, C4<0>, C4<0>; -L_0x1e3d290 .delay 1 (10000,10000,10000) L_0x1e3d290/d; -v0x1ca38f0_0 .net "A", 0 0, L_0x1e3d390; 1 drivers -v0x1ca39b0_0 .net "A_", 0 0, L_0x1e33b00; 1 drivers -v0x1ca3a70_0 .net "B", 0 0, L_0x1e3d4f0; 1 drivers -v0x1ca3b40_0 .net "B_", 0 0, L_0x1e33c60; 1 drivers -v0x1ca3be0_0 .net *"_s12", 0 0, L_0x1e35360; 1 drivers -v0x1ca3cd0_0 .net/2s *"_s14", 0 0, L_0x7f72592db608; 1 drivers -v0x1ca3d90_0 .net/2s *"_s16", 0 0, L_0x7f72592db650; 1 drivers -v0x1ca3e70_0 .net *"_s18", 0 0, L_0x1e35560; 1 drivers -v0x1ca3f50_0 .net *"_s20", 0 0, L_0x1e35620; 1 drivers -v0x1ca40c0_0 .net *"_s22", 0 0, L_0x1e35780; 1 drivers -v0x1ca41a0_0 .net *"_s24", 0 0, L_0x1e35c30; 1 drivers -o0x7f7259323d08 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1ca4280_0 name=_s30 -o0x7f7259323d38 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1ca4360_0 name=_s32 -v0x1ca4440_0 .net *"_s8", 0 0, L_0x1e34cb0; 1 drivers -v0x1ca4520_0 .net "carryin", 0 0, L_0x1e33870; 1 drivers -v0x1ca45c0_0 .net "carryout", 0 0, L_0x1e3cf30; 1 drivers -v0x1ca4660_0 .net "carryouts", 7 0, L_0x1ec0d30; 1 drivers -v0x1ca4810_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ca48b0_0 .net "result", 0 0, L_0x1e394c0; 1 drivers -v0x1ca49a0_0 .net "results", 7 0, L_0x1e35a00; 1 drivers -v0x1ca4ab0_0 .net "zero", 0 0, L_0x1e3d290; 1 drivers -LS_0x1e35a00_0_0 .concat8 [ 1 1 1 1], L_0x1e34180, L_0x1e347b0, L_0x1e34cb0, L_0x1e35360; -LS_0x1e35a00_0_4 .concat8 [ 1 1 1 1], L_0x1e35560, L_0x1e35620, L_0x1e35780, L_0x1e35c30; -L_0x1e35a00 .concat8 [ 4 4 0 0], LS_0x1e35a00_0_0, LS_0x1e35a00_0_4; -LS_0x1ec0d30_0_0 .concat [ 1 1 1 1], L_0x1e34430, L_0x1e34b50, o0x7f7259323d08, L_0x1e351b0; -LS_0x1ec0d30_0_4 .concat [ 4 0 0 0], o0x7f7259323d38; -L_0x1ec0d30 .concat [ 4 4 0 0], LS_0x1ec0d30_0_0, LS_0x1ec0d30_0_4; -S_0x1c75440 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1c751c0; +L_0x12c7300/d .functor NOT 1, L_0x12d0bf0, C4<0>, C4<0>, C4<0>; +L_0x12c7300 .delay 1 (10000,10000,10000) L_0x12c7300/d; +L_0x12c7460/d .functor NOT 1, L_0x12d0d50, C4<0>, C4<0>, C4<0>; +L_0x12c7460 .delay 1 (10000,10000,10000) L_0x12c7460/d; +L_0x12c84b0/d .functor XOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; +L_0x12c84b0 .delay 1 (30000,30000,30000) L_0x12c84b0/d; +L_0x2b0ab3d06608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12c8b60/d .functor OR 1, L_0x2b0ab3d06608, L_0x2b0ab3d06650, C4<0>, C4<0>; +L_0x12c8b60 .delay 1 (30000,30000,30000) L_0x12c8b60/d; +L_0x12c8d60/d .functor AND 1, L_0x12d0bf0, L_0x12d0d50, C4<1>, C4<1>; +L_0x12c8d60 .delay 1 (30000,30000,30000) L_0x12c8d60/d; +L_0x12c8e20/d .functor NAND 1, L_0x12d0bf0, L_0x12d0d50, C4<1>, C4<1>; +L_0x12c8e20 .delay 1 (20000,20000,20000) L_0x12c8e20/d; +L_0x12c8f80/d .functor XOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; +L_0x12c8f80 .delay 1 (20000,20000,20000) L_0x12c8f80/d; +L_0x12c9430/d .functor OR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; +L_0x12c9430 .delay 1 (30000,30000,30000) L_0x12c9430/d; +L_0x12d0af0/d .functor NOT 1, L_0x12cccc0, C4<0>, C4<0>, C4<0>; +L_0x12d0af0 .delay 1 (10000,10000,10000) L_0x12d0af0/d; +v0x1136570_0 .net "A", 0 0, L_0x12d0bf0; 1 drivers +v0x1136630_0 .net "A_", 0 0, L_0x12c7300; 1 drivers +v0x11366f0_0 .net "B", 0 0, L_0x12d0d50; 1 drivers +v0x11367c0_0 .net "B_", 0 0, L_0x12c7460; 1 drivers +v0x1136860_0 .net *"_s12", 0 0, L_0x12c8b60; 1 drivers +v0x1136950_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06608; 1 drivers +v0x1136a10_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06650; 1 drivers +v0x1136af0_0 .net *"_s18", 0 0, L_0x12c8d60; 1 drivers +v0x1136bd0_0 .net *"_s20", 0 0, L_0x12c8e20; 1 drivers +v0x1136d40_0 .net *"_s22", 0 0, L_0x12c8f80; 1 drivers +v0x1136e20_0 .net *"_s24", 0 0, L_0x12c9430; 1 drivers +o0x2b0ab3cd4d08 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1136f00_0 name=_s30 +o0x2b0ab3cd4d38 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1136fe0_0 name=_s32 +v0x11370c0_0 .net *"_s8", 0 0, L_0x12c84b0; 1 drivers +v0x11371a0_0 .net "carryin", 0 0, L_0x12c7070; 1 drivers +v0x1137240_0 .net "carryout", 0 0, L_0x12d0790; 1 drivers +v0x11372e0_0 .net "carryouts", 7 0, L_0x1355060; 1 drivers +v0x1137490_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1137530_0 .net "result", 0 0, L_0x12cccc0; 1 drivers +v0x1137620_0 .net "results", 7 0, L_0x12c9200; 1 drivers +v0x1137730_0 .net "zero", 0 0, L_0x12d0af0; 1 drivers +LS_0x12c9200_0_0 .concat8 [ 1 1 1 1], L_0x12c7980, L_0x12c7fb0, L_0x12c84b0, L_0x12c8b60; +LS_0x12c9200_0_4 .concat8 [ 1 1 1 1], L_0x12c8d60, L_0x12c8e20, L_0x12c8f80, L_0x12c9430; +L_0x12c9200 .concat8 [ 4 4 0 0], LS_0x12c9200_0_0, LS_0x12c9200_0_4; +LS_0x1355060_0_0 .concat [ 1 1 1 1], L_0x12c7c30, L_0x12c8350, o0x2b0ab3cd4d08, L_0x12c89b0; +LS_0x1355060_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd4d38; +L_0x1355060 .concat [ 4 4 0 0], LS_0x1355060_0_0, LS_0x1355060_0_4; +S_0x11080c0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1107e40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e34430/d .functor OR 1, L_0x1e33f10, L_0x1e342d0, C4<0>, C4<0>; -L_0x1e34430 .delay 1 (30000,30000,30000) L_0x1e34430/d; -v0x1c76270_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers -v0x1c76330_0 .net "b", 0 0, L_0x1e3d4f0; alias, 1 drivers -v0x1c76400_0 .net "c1", 0 0, L_0x1e33f10; 1 drivers -v0x1c76500_0 .net "c2", 0 0, L_0x1e342d0; 1 drivers -v0x1c765d0_0 .net "carryin", 0 0, L_0x1e33870; alias, 1 drivers -v0x1c766c0_0 .net "carryout", 0 0, L_0x1e34430; 1 drivers -v0x1c76760_0 .net "s1", 0 0, L_0x1e33e50; 1 drivers -v0x1c76850_0 .net "sum", 0 0, L_0x1e34180; 1 drivers -S_0x1c756b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1c75440; +L_0x12c7c30/d .functor OR 1, L_0x12c7710, L_0x12c7ad0, C4<0>, C4<0>; +L_0x12c7c30 .delay 1 (30000,30000,30000) L_0x12c7c30/d; +v0x1108ef0_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers +v0x1108fb0_0 .net "b", 0 0, L_0x12d0d50; alias, 1 drivers +v0x1109080_0 .net "c1", 0 0, L_0x12c7710; 1 drivers +v0x1109180_0 .net "c2", 0 0, L_0x12c7ad0; 1 drivers +v0x1109250_0 .net "carryin", 0 0, L_0x12c7070; alias, 1 drivers +v0x1109340_0 .net "carryout", 0 0, L_0x12c7c30; 1 drivers +v0x11093e0_0 .net "s1", 0 0, L_0x12c7650; 1 drivers +v0x11094d0_0 .net "sum", 0 0, L_0x12c7980; 1 drivers +S_0x1108330 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11080c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e33e50/d .functor XOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; -L_0x1e33e50 .delay 1 (30000,30000,30000) L_0x1e33e50/d; -L_0x1e33f10/d .functor AND 1, L_0x1e3d390, L_0x1e3d4f0, C4<1>, C4<1>; -L_0x1e33f10 .delay 1 (30000,30000,30000) L_0x1e33f10/d; -v0x1c75910_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers -v0x1c759f0_0 .net "b", 0 0, L_0x1e3d4f0; alias, 1 drivers -v0x1c75ab0_0 .net "carryout", 0 0, L_0x1e33f10; alias, 1 drivers -v0x1c75b50_0 .net "sum", 0 0, L_0x1e33e50; alias, 1 drivers -S_0x1c75c90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1c75440; +L_0x12c7650/d .functor XOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; +L_0x12c7650 .delay 1 (30000,30000,30000) L_0x12c7650/d; +L_0x12c7710/d .functor AND 1, L_0x12d0bf0, L_0x12d0d50, C4<1>, C4<1>; +L_0x12c7710 .delay 1 (30000,30000,30000) L_0x12c7710/d; +v0x1108590_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers +v0x1108670_0 .net "b", 0 0, L_0x12d0d50; alias, 1 drivers +v0x1108730_0 .net "carryout", 0 0, L_0x12c7710; alias, 1 drivers +v0x11087d0_0 .net "sum", 0 0, L_0x12c7650; alias, 1 drivers +S_0x1108910 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11080c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e34180/d .functor XOR 1, L_0x1e33e50, L_0x1e33870, C4<0>, C4<0>; -L_0x1e34180 .delay 1 (30000,30000,30000) L_0x1e34180/d; -L_0x1e342d0/d .functor AND 1, L_0x1e33e50, L_0x1e33870, C4<1>, C4<1>; -L_0x1e342d0 .delay 1 (30000,30000,30000) L_0x1e342d0/d; -v0x1c75ef0_0 .net "a", 0 0, L_0x1e33e50; alias, 1 drivers -v0x1c75f90_0 .net "b", 0 0, L_0x1e33870; alias, 1 drivers -v0x1c76030_0 .net "carryout", 0 0, L_0x1e342d0; alias, 1 drivers -v0x1c76100_0 .net "sum", 0 0, L_0x1e34180; alias, 1 drivers -S_0x1c76920 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1c751c0; +L_0x12c7980/d .functor XOR 1, L_0x12c7650, L_0x12c7070, C4<0>, C4<0>; +L_0x12c7980 .delay 1 (30000,30000,30000) L_0x12c7980/d; +L_0x12c7ad0/d .functor AND 1, L_0x12c7650, L_0x12c7070, C4<1>, C4<1>; +L_0x12c7ad0 .delay 1 (30000,30000,30000) L_0x12c7ad0/d; +v0x1108b70_0 .net "a", 0 0, L_0x12c7650; alias, 1 drivers +v0x1108c10_0 .net "b", 0 0, L_0x12c7070; alias, 1 drivers +v0x1108cb0_0 .net "carryout", 0 0, L_0x12c7ad0; alias, 1 drivers +v0x1108d80_0 .net "sum", 0 0, L_0x12c7980; alias, 1 drivers +S_0x11095a0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1107e40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1c7bd10_0 .net "ands", 7 0, L_0x1e3af60; 1 drivers -v0x1c7be20_0 .net "in", 7 0, L_0x1ec0d30; alias, 1 drivers -v0x1c7bee0_0 .net "out", 0 0, L_0x1e3cf30; alias, 1 drivers -v0x1c7bfb0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c76b40 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c76920; +v0x110e990_0 .net "ands", 7 0, L_0x12ce790; 1 drivers +v0x110eaa0_0 .net "in", 7 0, L_0x1355060; alias, 1 drivers +v0x110eb60_0 .net "out", 0 0, L_0x12d0790; alias, 1 drivers +v0x110ec30_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11097c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11095a0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c79270_0 .net "A", 7 0, L_0x1ec0d30; alias, 1 drivers -v0x1c79370_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c79430_0 .net *"_s0", 0 0, L_0x1e39820; 1 drivers -v0x1c794f0_0 .net *"_s12", 0 0, L_0x1e3a190; 1 drivers -v0x1c795d0_0 .net *"_s16", 0 0, L_0x1e3a4f0; 1 drivers -v0x1c79700_0 .net *"_s20", 0 0, L_0x1e3a800; 1 drivers -v0x1c797e0_0 .net *"_s24", 0 0, L_0x1e3ac50; 1 drivers -v0x1c798c0_0 .net *"_s28", 0 0, L_0x1e3b1e0; 1 drivers -v0x1c799a0_0 .net *"_s4", 0 0, L_0x1e39b30; 1 drivers -v0x1c79b10_0 .net *"_s8", 0 0, L_0x1e39e80; 1 drivers -v0x1c79bf0_0 .net "out", 7 0, L_0x1e3af60; alias, 1 drivers -L_0x1e398e0 .part L_0x1ec0d30, 0, 1; -L_0x1e39a40 .part v0x1d6daa0_0, 0, 1; -L_0x1e39bf0 .part L_0x1ec0d30, 1, 1; -L_0x1e39de0 .part v0x1d6daa0_0, 1, 1; -L_0x1e39f40 .part L_0x1ec0d30, 2, 1; -L_0x1e3a0a0 .part v0x1d6daa0_0, 2, 1; -L_0x1e3a250 .part L_0x1ec0d30, 3, 1; -L_0x1e3a3b0 .part v0x1d6daa0_0, 3, 1; -L_0x1e3a5b0 .part L_0x1ec0d30, 4, 1; -L_0x1e3a710 .part v0x1d6daa0_0, 4, 1; -L_0x1e3a8d0 .part L_0x1ec0d30, 5, 1; -L_0x1e3ab40 .part v0x1d6daa0_0, 5, 1; -L_0x1e3ad10 .part L_0x1ec0d30, 6, 1; -L_0x1e3ae70 .part v0x1d6daa0_0, 6, 1; -LS_0x1e3af60_0_0 .concat8 [ 1 1 1 1], L_0x1e39820, L_0x1e39b30, L_0x1e39e80, L_0x1e3a190; -LS_0x1e3af60_0_4 .concat8 [ 1 1 1 1], L_0x1e3a4f0, L_0x1e3a800, L_0x1e3ac50, L_0x1e3b1e0; -L_0x1e3af60 .concat8 [ 4 4 0 0], LS_0x1e3af60_0_0, LS_0x1e3af60_0_4; -L_0x1e3b2f0 .part L_0x1ec0d30, 7, 1; -L_0x1e3b4e0 .part v0x1d6daa0_0, 7, 1; -S_0x1c76da0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c76fb0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e39820/d .functor AND 1, L_0x1e398e0, L_0x1e39a40, C4<1>, C4<1>; -L_0x1e39820 .delay 1 (30000,30000,30000) L_0x1e39820/d; -v0x1c77090_0 .net *"_s0", 0 0, L_0x1e398e0; 1 drivers -v0x1c77170_0 .net *"_s1", 0 0, L_0x1e39a40; 1 drivers -S_0x1c77250 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c77460 .param/l "i" 0 4 54, +C4<01>; -L_0x1e39b30/d .functor AND 1, L_0x1e39bf0, L_0x1e39de0, C4<1>, C4<1>; -L_0x1e39b30 .delay 1 (30000,30000,30000) L_0x1e39b30/d; -v0x1c77520_0 .net *"_s0", 0 0, L_0x1e39bf0; 1 drivers -v0x1c77600_0 .net *"_s1", 0 0, L_0x1e39de0; 1 drivers -S_0x1c776e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c778f0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e39e80/d .functor AND 1, L_0x1e39f40, L_0x1e3a0a0, C4<1>, C4<1>; -L_0x1e39e80 .delay 1 (30000,30000,30000) L_0x1e39e80/d; -v0x1c77990_0 .net *"_s0", 0 0, L_0x1e39f40; 1 drivers -v0x1c77a70_0 .net *"_s1", 0 0, L_0x1e3a0a0; 1 drivers -S_0x1c77b50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c77d60 .param/l "i" 0 4 54, +C4<011>; -L_0x1e3a190/d .functor AND 1, L_0x1e3a250, L_0x1e3a3b0, C4<1>, C4<1>; -L_0x1e3a190 .delay 1 (30000,30000,30000) L_0x1e3a190/d; -v0x1c77e20_0 .net *"_s0", 0 0, L_0x1e3a250; 1 drivers -v0x1c77f00_0 .net *"_s1", 0 0, L_0x1e3a3b0; 1 drivers -S_0x1c77fe0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c78240 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e3a4f0/d .functor AND 1, L_0x1e3a5b0, L_0x1e3a710, C4<1>, C4<1>; -L_0x1e3a4f0 .delay 1 (30000,30000,30000) L_0x1e3a4f0/d; -v0x1c78300_0 .net *"_s0", 0 0, L_0x1e3a5b0; 1 drivers -v0x1c783e0_0 .net *"_s1", 0 0, L_0x1e3a710; 1 drivers -S_0x1c784c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c786d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e3a800/d .functor AND 1, L_0x1e3a8d0, L_0x1e3ab40, C4<1>, C4<1>; -L_0x1e3a800 .delay 1 (30000,30000,30000) L_0x1e3a800/d; -v0x1c78790_0 .net *"_s0", 0 0, L_0x1e3a8d0; 1 drivers -v0x1c78870_0 .net *"_s1", 0 0, L_0x1e3ab40; 1 drivers -S_0x1c78950 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c78b60 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e3ac50/d .functor AND 1, L_0x1e3ad10, L_0x1e3ae70, C4<1>, C4<1>; -L_0x1e3ac50 .delay 1 (30000,30000,30000) L_0x1e3ac50/d; -v0x1c78c20_0 .net *"_s0", 0 0, L_0x1e3ad10; 1 drivers -v0x1c78d00_0 .net *"_s1", 0 0, L_0x1e3ae70; 1 drivers -S_0x1c78de0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c76b40; - .timescale -9 -12; -P_0x1c78ff0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e3b1e0/d .functor AND 1, L_0x1e3b2f0, L_0x1e3b4e0, C4<1>, C4<1>; -L_0x1e3b1e0 .delay 1 (30000,30000,30000) L_0x1e3b1e0/d; -v0x1c790b0_0 .net *"_s0", 0 0, L_0x1e3b2f0; 1 drivers -v0x1c79190_0 .net *"_s1", 0 0, L_0x1e3b4e0; 1 drivers -S_0x1c79d50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c76920; +v0x110bef0_0 .net "A", 7 0, L_0x1355060; alias, 1 drivers +v0x110bff0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x110c0b0_0 .net *"_s0", 0 0, L_0x12cd020; 1 drivers +v0x110c170_0 .net *"_s12", 0 0, L_0x12cd990; 1 drivers +v0x110c250_0 .net *"_s16", 0 0, L_0x12cdcf0; 1 drivers +v0x110c380_0 .net *"_s20", 0 0, L_0x12ce000; 1 drivers +v0x110c460_0 .net *"_s24", 0 0, L_0x12ce480; 1 drivers +v0x110c540_0 .net *"_s28", 0 0, L_0x12ce410; 1 drivers +v0x110c620_0 .net *"_s4", 0 0, L_0x12cd330; 1 drivers +v0x110c790_0 .net *"_s8", 0 0, L_0x12cd680; 1 drivers +v0x110c870_0 .net "out", 7 0, L_0x12ce790; alias, 1 drivers +L_0x12cd0e0 .part L_0x1355060, 0, 1; +L_0x12cd240 .part v0x12010b0_0, 0, 1; +L_0x12cd3f0 .part L_0x1355060, 1, 1; +L_0x12cd5e0 .part v0x12010b0_0, 1, 1; +L_0x12cd740 .part L_0x1355060, 2, 1; +L_0x12cd8a0 .part v0x12010b0_0, 2, 1; +L_0x12cda50 .part L_0x1355060, 3, 1; +L_0x12cdbb0 .part v0x12010b0_0, 3, 1; +L_0x12cddb0 .part L_0x1355060, 4, 1; +L_0x12cdf10 .part v0x12010b0_0, 4, 1; +L_0x12ce100 .part L_0x1355060, 5, 1; +L_0x12ce370 .part v0x12010b0_0, 5, 1; +L_0x12ce540 .part L_0x1355060, 6, 1; +L_0x12ce6a0 .part v0x12010b0_0, 6, 1; +LS_0x12ce790_0_0 .concat8 [ 1 1 1 1], L_0x12cd020, L_0x12cd330, L_0x12cd680, L_0x12cd990; +LS_0x12ce790_0_4 .concat8 [ 1 1 1 1], L_0x12cdcf0, L_0x12ce000, L_0x12ce480, L_0x12ce410; +L_0x12ce790 .concat8 [ 4 4 0 0], LS_0x12ce790_0_0, LS_0x12ce790_0_4; +L_0x12ceb50 .part L_0x1355060, 7, 1; +L_0x12ced40 .part v0x12010b0_0, 7, 1; +S_0x1109a20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x1109c30 .param/l "i" 0 4 54, +C4<00>; +L_0x12cd020/d .functor AND 1, L_0x12cd0e0, L_0x12cd240, C4<1>, C4<1>; +L_0x12cd020 .delay 1 (30000,30000,30000) L_0x12cd020/d; +v0x1109d10_0 .net *"_s0", 0 0, L_0x12cd0e0; 1 drivers +v0x1109df0_0 .net *"_s1", 0 0, L_0x12cd240; 1 drivers +S_0x1109ed0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110a0e0 .param/l "i" 0 4 54, +C4<01>; +L_0x12cd330/d .functor AND 1, L_0x12cd3f0, L_0x12cd5e0, C4<1>, C4<1>; +L_0x12cd330 .delay 1 (30000,30000,30000) L_0x12cd330/d; +v0x110a1a0_0 .net *"_s0", 0 0, L_0x12cd3f0; 1 drivers +v0x110a280_0 .net *"_s1", 0 0, L_0x12cd5e0; 1 drivers +S_0x110a360 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110a570 .param/l "i" 0 4 54, +C4<010>; +L_0x12cd680/d .functor AND 1, L_0x12cd740, L_0x12cd8a0, C4<1>, C4<1>; +L_0x12cd680 .delay 1 (30000,30000,30000) L_0x12cd680/d; +v0x110a610_0 .net *"_s0", 0 0, L_0x12cd740; 1 drivers +v0x110a6f0_0 .net *"_s1", 0 0, L_0x12cd8a0; 1 drivers +S_0x110a7d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110a9e0 .param/l "i" 0 4 54, +C4<011>; +L_0x12cd990/d .functor AND 1, L_0x12cda50, L_0x12cdbb0, C4<1>, C4<1>; +L_0x12cd990 .delay 1 (30000,30000,30000) L_0x12cd990/d; +v0x110aaa0_0 .net *"_s0", 0 0, L_0x12cda50; 1 drivers +v0x110ab80_0 .net *"_s1", 0 0, L_0x12cdbb0; 1 drivers +S_0x110ac60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110aec0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12cdcf0/d .functor AND 1, L_0x12cddb0, L_0x12cdf10, C4<1>, C4<1>; +L_0x12cdcf0 .delay 1 (30000,30000,30000) L_0x12cdcf0/d; +v0x110af80_0 .net *"_s0", 0 0, L_0x12cddb0; 1 drivers +v0x110b060_0 .net *"_s1", 0 0, L_0x12cdf10; 1 drivers +S_0x110b140 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110b350 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ce000/d .functor AND 1, L_0x12ce100, L_0x12ce370, C4<1>, C4<1>; +L_0x12ce000 .delay 1 (30000,30000,30000) L_0x12ce000/d; +v0x110b410_0 .net *"_s0", 0 0, L_0x12ce100; 1 drivers +v0x110b4f0_0 .net *"_s1", 0 0, L_0x12ce370; 1 drivers +S_0x110b5d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110b7e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ce480/d .functor AND 1, L_0x12ce540, L_0x12ce6a0, C4<1>, C4<1>; +L_0x12ce480 .delay 1 (30000,30000,30000) L_0x12ce480/d; +v0x110b8a0_0 .net *"_s0", 0 0, L_0x12ce540; 1 drivers +v0x110b980_0 .net *"_s1", 0 0, L_0x12ce6a0; 1 drivers +S_0x110ba60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11097c0; + .timescale -9 -12; +P_0x110bc70 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ce410/d .functor AND 1, L_0x12ceb50, L_0x12ced40, C4<1>, C4<1>; +L_0x12ce410 .delay 1 (30000,30000,30000) L_0x12ce410/d; +v0x110bd30_0 .net *"_s0", 0 0, L_0x12ceb50; 1 drivers +v0x110be10_0 .net *"_s1", 0 0, L_0x12ced40; 1 drivers +S_0x110c9d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11095a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e3cf30/d .functor OR 1, L_0x1e3cff0, L_0x1e3d1a0, C4<0>, C4<0>; -L_0x1e3cf30 .delay 1 (30000,30000,30000) L_0x1e3cf30/d; -v0x1c7b8a0_0 .net *"_s10", 0 0, L_0x1e3cff0; 1 drivers -v0x1c7b980_0 .net *"_s12", 0 0, L_0x1e3d1a0; 1 drivers -v0x1c7ba60_0 .net "in", 7 0, L_0x1e3af60; alias, 1 drivers -v0x1c7bb30_0 .net "ors", 1 0, L_0x1e3cd50; 1 drivers -v0x1c7bbf0_0 .net "out", 0 0, L_0x1e3cf30; alias, 1 drivers -L_0x1e3c120 .part L_0x1e3af60, 0, 4; -L_0x1e3cd50 .concat8 [ 1 1 0 0], L_0x1e3be10, L_0x1e3ca40; -L_0x1e3ce90 .part L_0x1e3af60, 4, 4; -L_0x1e3cff0 .part L_0x1e3cd50, 0, 1; -L_0x1e3d1a0 .part L_0x1e3cd50, 1, 1; -S_0x1c79f10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c79d50; +L_0x12d0790/d .functor OR 1, L_0x12d0850, L_0x12d0a00, C4<0>, C4<0>; +L_0x12d0790 .delay 1 (30000,30000,30000) L_0x12d0790/d; +v0x110e520_0 .net *"_s10", 0 0, L_0x12d0850; 1 drivers +v0x110e600_0 .net *"_s12", 0 0, L_0x12d0a00; 1 drivers +v0x110e6e0_0 .net "in", 7 0, L_0x12ce790; alias, 1 drivers +v0x110e7b0_0 .net "ors", 1 0, L_0x12d05b0; 1 drivers +v0x110e870_0 .net "out", 0 0, L_0x12d0790; alias, 1 drivers +L_0x12cf980 .part L_0x12ce790, 0, 4; +L_0x12d05b0 .concat8 [ 1 1 0 0], L_0x12cf670, L_0x12d02a0; +L_0x12d06f0 .part L_0x12ce790, 4, 4; +L_0x12d0850 .part L_0x12d05b0, 0, 1; +L_0x12d0a00 .part L_0x12d05b0, 1, 1; +S_0x110cb90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x110c9d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e3b5d0/d .functor OR 1, L_0x1e3b690, L_0x1e3b7f0, C4<0>, C4<0>; -L_0x1e3b5d0 .delay 1 (30000,30000,30000) L_0x1e3b5d0/d; -L_0x1e3ba20/d .functor OR 1, L_0x1e3bb30, L_0x1e3bc90, C4<0>, C4<0>; -L_0x1e3ba20 .delay 1 (30000,30000,30000) L_0x1e3ba20/d; -L_0x1e3be10/d .functor OR 1, L_0x1e3be80, L_0x1e3c030, C4<0>, C4<0>; -L_0x1e3be10 .delay 1 (30000,30000,30000) L_0x1e3be10/d; -v0x1c7a160_0 .net *"_s0", 0 0, L_0x1e3b5d0; 1 drivers -v0x1c7a260_0 .net *"_s10", 0 0, L_0x1e3bb30; 1 drivers -v0x1c7a340_0 .net *"_s12", 0 0, L_0x1e3bc90; 1 drivers -v0x1c7a400_0 .net *"_s14", 0 0, L_0x1e3be80; 1 drivers -v0x1c7a4e0_0 .net *"_s16", 0 0, L_0x1e3c030; 1 drivers -v0x1c7a610_0 .net *"_s3", 0 0, L_0x1e3b690; 1 drivers -v0x1c7a6f0_0 .net *"_s5", 0 0, L_0x1e3b7f0; 1 drivers -v0x1c7a7d0_0 .net *"_s6", 0 0, L_0x1e3ba20; 1 drivers -v0x1c7a8b0_0 .net "in", 3 0, L_0x1e3c120; 1 drivers -v0x1c7aa20_0 .net "ors", 1 0, L_0x1e3b930; 1 drivers -v0x1c7ab00_0 .net "out", 0 0, L_0x1e3be10; 1 drivers -L_0x1e3b690 .part L_0x1e3c120, 0, 1; -L_0x1e3b7f0 .part L_0x1e3c120, 1, 1; -L_0x1e3b930 .concat8 [ 1 1 0 0], L_0x1e3b5d0, L_0x1e3ba20; -L_0x1e3bb30 .part L_0x1e3c120, 2, 1; -L_0x1e3bc90 .part L_0x1e3c120, 3, 1; -L_0x1e3be80 .part L_0x1e3b930, 0, 1; -L_0x1e3c030 .part L_0x1e3b930, 1, 1; -S_0x1c7ac20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c79d50; +L_0x12cee30/d .functor OR 1, L_0x12ceef0, L_0x12cf050, C4<0>, C4<0>; +L_0x12cee30 .delay 1 (30000,30000,30000) L_0x12cee30/d; +L_0x12cf280/d .functor OR 1, L_0x12cf390, L_0x12cf4f0, C4<0>, C4<0>; +L_0x12cf280 .delay 1 (30000,30000,30000) L_0x12cf280/d; +L_0x12cf670/d .functor OR 1, L_0x12cf6e0, L_0x12cf890, C4<0>, C4<0>; +L_0x12cf670 .delay 1 (30000,30000,30000) L_0x12cf670/d; +v0x110cde0_0 .net *"_s0", 0 0, L_0x12cee30; 1 drivers +v0x110cee0_0 .net *"_s10", 0 0, L_0x12cf390; 1 drivers +v0x110cfc0_0 .net *"_s12", 0 0, L_0x12cf4f0; 1 drivers +v0x110d080_0 .net *"_s14", 0 0, L_0x12cf6e0; 1 drivers +v0x110d160_0 .net *"_s16", 0 0, L_0x12cf890; 1 drivers +v0x110d290_0 .net *"_s3", 0 0, L_0x12ceef0; 1 drivers +v0x110d370_0 .net *"_s5", 0 0, L_0x12cf050; 1 drivers +v0x110d450_0 .net *"_s6", 0 0, L_0x12cf280; 1 drivers +v0x110d530_0 .net "in", 3 0, L_0x12cf980; 1 drivers +v0x110d6a0_0 .net "ors", 1 0, L_0x12cf190; 1 drivers +v0x110d780_0 .net "out", 0 0, L_0x12cf670; 1 drivers +L_0x12ceef0 .part L_0x12cf980, 0, 1; +L_0x12cf050 .part L_0x12cf980, 1, 1; +L_0x12cf190 .concat8 [ 1 1 0 0], L_0x12cee30, L_0x12cf280; +L_0x12cf390 .part L_0x12cf980, 2, 1; +L_0x12cf4f0 .part L_0x12cf980, 3, 1; +L_0x12cf6e0 .part L_0x12cf190, 0, 1; +L_0x12cf890 .part L_0x12cf190, 1, 1; +S_0x110d8a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x110c9d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e3c250/d .functor OR 1, L_0x1e3c2c0, L_0x1e3c420, C4<0>, C4<0>; -L_0x1e3c250 .delay 1 (30000,30000,30000) L_0x1e3c250/d; -L_0x1e3c650/d .functor OR 1, L_0x1e3c760, L_0x1e3c8c0, C4<0>, C4<0>; -L_0x1e3c650 .delay 1 (30000,30000,30000) L_0x1e3c650/d; -L_0x1e3ca40/d .functor OR 1, L_0x1e3cab0, L_0x1e3cc60, C4<0>, C4<0>; -L_0x1e3ca40 .delay 1 (30000,30000,30000) L_0x1e3ca40/d; -v0x1c7ade0_0 .net *"_s0", 0 0, L_0x1e3c250; 1 drivers -v0x1c7aee0_0 .net *"_s10", 0 0, L_0x1e3c760; 1 drivers -v0x1c7afc0_0 .net *"_s12", 0 0, L_0x1e3c8c0; 1 drivers -v0x1c7b080_0 .net *"_s14", 0 0, L_0x1e3cab0; 1 drivers -v0x1c7b160_0 .net *"_s16", 0 0, L_0x1e3cc60; 1 drivers -v0x1c7b290_0 .net *"_s3", 0 0, L_0x1e3c2c0; 1 drivers -v0x1c7b370_0 .net *"_s5", 0 0, L_0x1e3c420; 1 drivers -v0x1c7b450_0 .net *"_s6", 0 0, L_0x1e3c650; 1 drivers -v0x1c7b530_0 .net "in", 3 0, L_0x1e3ce90; 1 drivers -v0x1c7b6a0_0 .net "ors", 1 0, L_0x1e3c560; 1 drivers -v0x1c7b780_0 .net "out", 0 0, L_0x1e3ca40; 1 drivers -L_0x1e3c2c0 .part L_0x1e3ce90, 0, 1; -L_0x1e3c420 .part L_0x1e3ce90, 1, 1; -L_0x1e3c560 .concat8 [ 1 1 0 0], L_0x1e3c250, L_0x1e3c650; -L_0x1e3c760 .part L_0x1e3ce90, 2, 1; -L_0x1e3c8c0 .part L_0x1e3ce90, 3, 1; -L_0x1e3cab0 .part L_0x1e3c560, 0, 1; -L_0x1e3cc60 .part L_0x1e3c560, 1, 1; -S_0x1c7c090 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1c751c0; +L_0x12cfab0/d .functor OR 1, L_0x12cfb20, L_0x12cfc80, C4<0>, C4<0>; +L_0x12cfab0 .delay 1 (30000,30000,30000) L_0x12cfab0/d; +L_0x12cfeb0/d .functor OR 1, L_0x12cffc0, L_0x12d0120, C4<0>, C4<0>; +L_0x12cfeb0 .delay 1 (30000,30000,30000) L_0x12cfeb0/d; +L_0x12d02a0/d .functor OR 1, L_0x12d0310, L_0x12d04c0, C4<0>, C4<0>; +L_0x12d02a0 .delay 1 (30000,30000,30000) L_0x12d02a0/d; +v0x110da60_0 .net *"_s0", 0 0, L_0x12cfab0; 1 drivers +v0x110db60_0 .net *"_s10", 0 0, L_0x12cffc0; 1 drivers +v0x110dc40_0 .net *"_s12", 0 0, L_0x12d0120; 1 drivers +v0x110dd00_0 .net *"_s14", 0 0, L_0x12d0310; 1 drivers +v0x110dde0_0 .net *"_s16", 0 0, L_0x12d04c0; 1 drivers +v0x110df10_0 .net *"_s3", 0 0, L_0x12cfb20; 1 drivers +v0x110dff0_0 .net *"_s5", 0 0, L_0x12cfc80; 1 drivers +v0x110e0d0_0 .net *"_s6", 0 0, L_0x12cfeb0; 1 drivers +v0x110e1b0_0 .net "in", 3 0, L_0x12d06f0; 1 drivers +v0x110e320_0 .net "ors", 1 0, L_0x12cfdc0; 1 drivers +v0x110e400_0 .net "out", 0 0, L_0x12d02a0; 1 drivers +L_0x12cfb20 .part L_0x12d06f0, 0, 1; +L_0x12cfc80 .part L_0x12d06f0, 1, 1; +L_0x12cfdc0 .concat8 [ 1 1 0 0], L_0x12cfab0, L_0x12cfeb0; +L_0x12cffc0 .part L_0x12d06f0, 2, 1; +L_0x12d0120 .part L_0x12d06f0, 3, 1; +L_0x12d0310 .part L_0x12cfdc0, 0, 1; +L_0x12d04c0 .part L_0x12cfdc0, 1, 1; +S_0x110ed10 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1107e40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1ca14c0_0 .net "ands", 7 0, L_0x1e374c0; 1 drivers -v0x1ca15d0_0 .net "in", 7 0, L_0x1e35a00; alias, 1 drivers -v0x1ca1690_0 .net "out", 0 0, L_0x1e394c0; alias, 1 drivers -v0x1ca1760_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1c7c2e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1c7c090; +v0x1134140_0 .net "ands", 7 0, L_0x12cacc0; 1 drivers +v0x1134250_0 .net "in", 7 0, L_0x12c9200; alias, 1 drivers +v0x1134310_0 .net "out", 0 0, L_0x12cccc0; alias, 1 drivers +v0x11343e0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x110ef60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x110ed10; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1c7ea20_0 .net "A", 7 0, L_0x1e35a00; alias, 1 drivers -v0x1c7eb20_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1c7ebe0_0 .net *"_s0", 0 0, L_0x1e35d90; 1 drivers -v0x1c7eca0_0 .net *"_s12", 0 0, L_0x1e36750; 1 drivers -v0x1c7ed80_0 .net *"_s16", 0 0, L_0x1e36ab0; 1 drivers -v0x1c7eeb0_0 .net *"_s20", 0 0, L_0x1e36e80; 1 drivers -v0x1c7ef90_0 .net *"_s24", 0 0, L_0x1e371b0; 1 drivers -v0x1c7f070_0 .net *"_s28", 0 0, L_0x1e37140; 1 drivers -v0x1c7f150_0 .net *"_s4", 0 0, L_0x1e36130; 1 drivers -v0x1c7f2c0_0 .net *"_s8", 0 0, L_0x1e36440; 1 drivers -v0x1c7f3a0_0 .net "out", 7 0, L_0x1e374c0; alias, 1 drivers -L_0x1e35ea0 .part L_0x1e35a00, 0, 1; -L_0x1e36090 .part v0x1d6daa0_0, 0, 1; -L_0x1e361f0 .part L_0x1e35a00, 1, 1; -L_0x1e36350 .part v0x1d6daa0_0, 1, 1; -L_0x1e36500 .part L_0x1e35a00, 2, 1; -L_0x1e36660 .part v0x1d6daa0_0, 2, 1; -L_0x1e36810 .part L_0x1e35a00, 3, 1; -L_0x1e36970 .part v0x1d6daa0_0, 3, 1; -L_0x1e36b70 .part L_0x1e35a00, 4, 1; -L_0x1e36de0 .part v0x1d6daa0_0, 4, 1; -L_0x1e36ef0 .part L_0x1e35a00, 5, 1; -L_0x1e37050 .part v0x1d6daa0_0, 5, 1; -L_0x1e37270 .part L_0x1e35a00, 6, 1; -L_0x1e373d0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e374c0_0_0 .concat8 [ 1 1 1 1], L_0x1e35d90, L_0x1e36130, L_0x1e36440, L_0x1e36750; -LS_0x1e374c0_0_4 .concat8 [ 1 1 1 1], L_0x1e36ab0, L_0x1e36e80, L_0x1e371b0, L_0x1e37140; -L_0x1e374c0 .concat8 [ 4 4 0 0], LS_0x1e374c0_0_0, LS_0x1e374c0_0_4; -L_0x1e37880 .part L_0x1e35a00, 7, 1; -L_0x1e37a70 .part v0x1d6daa0_0, 7, 1; -S_0x1c7c520 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7c730 .param/l "i" 0 4 54, +C4<00>; -L_0x1e35d90/d .functor AND 1, L_0x1e35ea0, L_0x1e36090, C4<1>, C4<1>; -L_0x1e35d90 .delay 1 (30000,30000,30000) L_0x1e35d90/d; -v0x1c7c810_0 .net *"_s0", 0 0, L_0x1e35ea0; 1 drivers -v0x1c7c8f0_0 .net *"_s1", 0 0, L_0x1e36090; 1 drivers -S_0x1c7c9d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7cbe0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e36130/d .functor AND 1, L_0x1e361f0, L_0x1e36350, C4<1>, C4<1>; -L_0x1e36130 .delay 1 (30000,30000,30000) L_0x1e36130/d; -v0x1c7cca0_0 .net *"_s0", 0 0, L_0x1e361f0; 1 drivers -v0x1c7cd80_0 .net *"_s1", 0 0, L_0x1e36350; 1 drivers -S_0x1c7ce60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7d0a0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e36440/d .functor AND 1, L_0x1e36500, L_0x1e36660, C4<1>, C4<1>; -L_0x1e36440 .delay 1 (30000,30000,30000) L_0x1e36440/d; -v0x1c7d140_0 .net *"_s0", 0 0, L_0x1e36500; 1 drivers -v0x1c7d220_0 .net *"_s1", 0 0, L_0x1e36660; 1 drivers -S_0x1c7d300 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7d510 .param/l "i" 0 4 54, +C4<011>; -L_0x1e36750/d .functor AND 1, L_0x1e36810, L_0x1e36970, C4<1>, C4<1>; -L_0x1e36750 .delay 1 (30000,30000,30000) L_0x1e36750/d; -v0x1c7d5d0_0 .net *"_s0", 0 0, L_0x1e36810; 1 drivers -v0x1c7d6b0_0 .net *"_s1", 0 0, L_0x1e36970; 1 drivers -S_0x1c7d790 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7d9f0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e36ab0/d .functor AND 1, L_0x1e36b70, L_0x1e36de0, C4<1>, C4<1>; -L_0x1e36ab0 .delay 1 (30000,30000,30000) L_0x1e36ab0/d; -v0x1c7dab0_0 .net *"_s0", 0 0, L_0x1e36b70; 1 drivers -v0x1c7db90_0 .net *"_s1", 0 0, L_0x1e36de0; 1 drivers -S_0x1c7dc70 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7de80 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e36e80/d .functor AND 1, L_0x1e36ef0, L_0x1e37050, C4<1>, C4<1>; -L_0x1e36e80 .delay 1 (30000,30000,30000) L_0x1e36e80/d; -v0x1c7df40_0 .net *"_s0", 0 0, L_0x1e36ef0; 1 drivers -v0x1c7e020_0 .net *"_s1", 0 0, L_0x1e37050; 1 drivers -S_0x1c7e100 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7e310 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e371b0/d .functor AND 1, L_0x1e37270, L_0x1e373d0, C4<1>, C4<1>; -L_0x1e371b0 .delay 1 (30000,30000,30000) L_0x1e371b0/d; -v0x1c7e3d0_0 .net *"_s0", 0 0, L_0x1e37270; 1 drivers -v0x1c7e4b0_0 .net *"_s1", 0 0, L_0x1e373d0; 1 drivers -S_0x1c7e590 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1c7c2e0; - .timescale -9 -12; -P_0x1c7e7a0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e37140/d .functor AND 1, L_0x1e37880, L_0x1e37a70, C4<1>, C4<1>; -L_0x1e37140 .delay 1 (30000,30000,30000) L_0x1e37140/d; -v0x1c7e860_0 .net *"_s0", 0 0, L_0x1e37880; 1 drivers -v0x1c7e940_0 .net *"_s1", 0 0, L_0x1e37a70; 1 drivers -S_0x1c7f500 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1c7c090; +v0x11116a0_0 .net "A", 7 0, L_0x12c9200; alias, 1 drivers +v0x11117a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1111860_0 .net *"_s0", 0 0, L_0x12c9590; 1 drivers +v0x1111920_0 .net *"_s12", 0 0, L_0x12c9f50; 1 drivers +v0x1111a00_0 .net *"_s16", 0 0, L_0x12ca2b0; 1 drivers +v0x1111b30_0 .net *"_s20", 0 0, L_0x12ca680; 1 drivers +v0x1111c10_0 .net *"_s24", 0 0, L_0x12ca9b0; 1 drivers +v0x1111cf0_0 .net *"_s28", 0 0, L_0x12ca940; 1 drivers +v0x1111dd0_0 .net *"_s4", 0 0, L_0x12c9930; 1 drivers +v0x1111f40_0 .net *"_s8", 0 0, L_0x12c9c40; 1 drivers +v0x1112020_0 .net "out", 7 0, L_0x12cacc0; alias, 1 drivers +L_0x12c96a0 .part L_0x12c9200, 0, 1; +L_0x12c9890 .part v0x12010b0_0, 0, 1; +L_0x12c99f0 .part L_0x12c9200, 1, 1; +L_0x12c9b50 .part v0x12010b0_0, 1, 1; +L_0x12c9d00 .part L_0x12c9200, 2, 1; +L_0x12c9e60 .part v0x12010b0_0, 2, 1; +L_0x12ca010 .part L_0x12c9200, 3, 1; +L_0x12ca170 .part v0x12010b0_0, 3, 1; +L_0x12ca370 .part L_0x12c9200, 4, 1; +L_0x12ca5e0 .part v0x12010b0_0, 4, 1; +L_0x12ca6f0 .part L_0x12c9200, 5, 1; +L_0x12ca850 .part v0x12010b0_0, 5, 1; +L_0x12caa70 .part L_0x12c9200, 6, 1; +L_0x12cabd0 .part v0x12010b0_0, 6, 1; +LS_0x12cacc0_0_0 .concat8 [ 1 1 1 1], L_0x12c9590, L_0x12c9930, L_0x12c9c40, L_0x12c9f50; +LS_0x12cacc0_0_4 .concat8 [ 1 1 1 1], L_0x12ca2b0, L_0x12ca680, L_0x12ca9b0, L_0x12ca940; +L_0x12cacc0 .concat8 [ 4 4 0 0], LS_0x12cacc0_0_0, LS_0x12cacc0_0_4; +L_0x12cb080 .part L_0x12c9200, 7, 1; +L_0x12cb270 .part v0x12010b0_0, 7, 1; +S_0x110f1a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x110f3b0 .param/l "i" 0 4 54, +C4<00>; +L_0x12c9590/d .functor AND 1, L_0x12c96a0, L_0x12c9890, C4<1>, C4<1>; +L_0x12c9590 .delay 1 (30000,30000,30000) L_0x12c9590/d; +v0x110f490_0 .net *"_s0", 0 0, L_0x12c96a0; 1 drivers +v0x110f570_0 .net *"_s1", 0 0, L_0x12c9890; 1 drivers +S_0x110f650 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x110f860 .param/l "i" 0 4 54, +C4<01>; +L_0x12c9930/d .functor AND 1, L_0x12c99f0, L_0x12c9b50, C4<1>, C4<1>; +L_0x12c9930 .delay 1 (30000,30000,30000) L_0x12c9930/d; +v0x110f920_0 .net *"_s0", 0 0, L_0x12c99f0; 1 drivers +v0x110fa00_0 .net *"_s1", 0 0, L_0x12c9b50; 1 drivers +S_0x110fae0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x110fd20 .param/l "i" 0 4 54, +C4<010>; +L_0x12c9c40/d .functor AND 1, L_0x12c9d00, L_0x12c9e60, C4<1>, C4<1>; +L_0x12c9c40 .delay 1 (30000,30000,30000) L_0x12c9c40/d; +v0x110fdc0_0 .net *"_s0", 0 0, L_0x12c9d00; 1 drivers +v0x110fea0_0 .net *"_s1", 0 0, L_0x12c9e60; 1 drivers +S_0x110ff80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x1110190 .param/l "i" 0 4 54, +C4<011>; +L_0x12c9f50/d .functor AND 1, L_0x12ca010, L_0x12ca170, C4<1>, C4<1>; +L_0x12c9f50 .delay 1 (30000,30000,30000) L_0x12c9f50/d; +v0x1110250_0 .net *"_s0", 0 0, L_0x12ca010; 1 drivers +v0x1110330_0 .net *"_s1", 0 0, L_0x12ca170; 1 drivers +S_0x1110410 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x1110670 .param/l "i" 0 4 54, +C4<0100>; +L_0x12ca2b0/d .functor AND 1, L_0x12ca370, L_0x12ca5e0, C4<1>, C4<1>; +L_0x12ca2b0 .delay 1 (30000,30000,30000) L_0x12ca2b0/d; +v0x1110730_0 .net *"_s0", 0 0, L_0x12ca370; 1 drivers +v0x1110810_0 .net *"_s1", 0 0, L_0x12ca5e0; 1 drivers +S_0x11108f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x1110b00 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ca680/d .functor AND 1, L_0x12ca6f0, L_0x12ca850, C4<1>, C4<1>; +L_0x12ca680 .delay 1 (30000,30000,30000) L_0x12ca680/d; +v0x1110bc0_0 .net *"_s0", 0 0, L_0x12ca6f0; 1 drivers +v0x1110ca0_0 .net *"_s1", 0 0, L_0x12ca850; 1 drivers +S_0x1110d80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x1110f90 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ca9b0/d .functor AND 1, L_0x12caa70, L_0x12cabd0, C4<1>, C4<1>; +L_0x12ca9b0 .delay 1 (30000,30000,30000) L_0x12ca9b0/d; +v0x1111050_0 .net *"_s0", 0 0, L_0x12caa70; 1 drivers +v0x1111130_0 .net *"_s1", 0 0, L_0x12cabd0; 1 drivers +S_0x1111210 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x110ef60; + .timescale -9 -12; +P_0x1111420 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ca940/d .functor AND 1, L_0x12cb080, L_0x12cb270, C4<1>, C4<1>; +L_0x12ca940 .delay 1 (30000,30000,30000) L_0x12ca940/d; +v0x11114e0_0 .net *"_s0", 0 0, L_0x12cb080; 1 drivers +v0x11115c0_0 .net *"_s1", 0 0, L_0x12cb270; 1 drivers +S_0x1112180 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x110ed10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e394c0/d .functor OR 1, L_0x1e39580, L_0x1e39730, C4<0>, C4<0>; -L_0x1e394c0 .delay 1 (30000,30000,30000) L_0x1e394c0/d; -v0x1ca1050_0 .net *"_s10", 0 0, L_0x1e39580; 1 drivers -v0x1ca1130_0 .net *"_s12", 0 0, L_0x1e39730; 1 drivers -v0x1ca1210_0 .net "in", 7 0, L_0x1e374c0; alias, 1 drivers -v0x1ca12e0_0 .net "ors", 1 0, L_0x1e392e0; 1 drivers -v0x1ca13a0_0 .net "out", 0 0, L_0x1e394c0; alias, 1 drivers -L_0x1e386b0 .part L_0x1e374c0, 0, 4; -L_0x1e392e0 .concat8 [ 1 1 0 0], L_0x1e383a0, L_0x1e38fd0; -L_0x1e39420 .part L_0x1e374c0, 4, 4; -L_0x1e39580 .part L_0x1e392e0, 0, 1; -L_0x1e39730 .part L_0x1e392e0, 1, 1; -S_0x1c7f6c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1c7f500; +L_0x12cccc0/d .functor OR 1, L_0x12ccd80, L_0x12ccf30, C4<0>, C4<0>; +L_0x12cccc0 .delay 1 (30000,30000,30000) L_0x12cccc0/d; +v0x1133cd0_0 .net *"_s10", 0 0, L_0x12ccd80; 1 drivers +v0x1133db0_0 .net *"_s12", 0 0, L_0x12ccf30; 1 drivers +v0x1133e90_0 .net "in", 7 0, L_0x12cacc0; alias, 1 drivers +v0x1133f60_0 .net "ors", 1 0, L_0x12ccae0; 1 drivers +v0x1134020_0 .net "out", 0 0, L_0x12cccc0; alias, 1 drivers +L_0x12cbeb0 .part L_0x12cacc0, 0, 4; +L_0x12ccae0 .concat8 [ 1 1 0 0], L_0x12cbba0, L_0x12cc7d0; +L_0x12ccc20 .part L_0x12cacc0, 4, 4; +L_0x12ccd80 .part L_0x12ccae0, 0, 1; +L_0x12ccf30 .part L_0x12ccae0, 1, 1; +S_0x1112340 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1112180; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e37b60/d .functor OR 1, L_0x1e37c20, L_0x1e37d80, C4<0>, C4<0>; -L_0x1e37b60 .delay 1 (30000,30000,30000) L_0x1e37b60/d; -L_0x1e37fb0/d .functor OR 1, L_0x1e380c0, L_0x1e38220, C4<0>, C4<0>; -L_0x1e37fb0 .delay 1 (30000,30000,30000) L_0x1e37fb0/d; -L_0x1e383a0/d .functor OR 1, L_0x1e38410, L_0x1e385c0, C4<0>, C4<0>; -L_0x1e383a0 .delay 1 (30000,30000,30000) L_0x1e383a0/d; -v0x1c7f910_0 .net *"_s0", 0 0, L_0x1e37b60; 1 drivers -v0x1c7fa10_0 .net *"_s10", 0 0, L_0x1e380c0; 1 drivers -v0x1c7faf0_0 .net *"_s12", 0 0, L_0x1e38220; 1 drivers -v0x1c7fbb0_0 .net *"_s14", 0 0, L_0x1e38410; 1 drivers -v0x1c9fc90_0 .net *"_s16", 0 0, L_0x1e385c0; 1 drivers -v0x1c9fdc0_0 .net *"_s3", 0 0, L_0x1e37c20; 1 drivers -v0x1c9fea0_0 .net *"_s5", 0 0, L_0x1e37d80; 1 drivers -v0x1c9ff80_0 .net *"_s6", 0 0, L_0x1e37fb0; 1 drivers -v0x1ca0060_0 .net "in", 3 0, L_0x1e386b0; 1 drivers -v0x1ca01d0_0 .net "ors", 1 0, L_0x1e37ec0; 1 drivers -v0x1ca02b0_0 .net "out", 0 0, L_0x1e383a0; 1 drivers -L_0x1e37c20 .part L_0x1e386b0, 0, 1; -L_0x1e37d80 .part L_0x1e386b0, 1, 1; -L_0x1e37ec0 .concat8 [ 1 1 0 0], L_0x1e37b60, L_0x1e37fb0; -L_0x1e380c0 .part L_0x1e386b0, 2, 1; -L_0x1e38220 .part L_0x1e386b0, 3, 1; -L_0x1e38410 .part L_0x1e37ec0, 0, 1; -L_0x1e385c0 .part L_0x1e37ec0, 1, 1; -S_0x1ca03d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1c7f500; +L_0x12cb360/d .functor OR 1, L_0x12cb420, L_0x12cb580, C4<0>, C4<0>; +L_0x12cb360 .delay 1 (30000,30000,30000) L_0x12cb360/d; +L_0x12cb7b0/d .functor OR 1, L_0x12cb8c0, L_0x12cba20, C4<0>, C4<0>; +L_0x12cb7b0 .delay 1 (30000,30000,30000) L_0x12cb7b0/d; +L_0x12cbba0/d .functor OR 1, L_0x12cbc10, L_0x12cbdc0, C4<0>, C4<0>; +L_0x12cbba0 .delay 1 (30000,30000,30000) L_0x12cbba0/d; +v0x1112590_0 .net *"_s0", 0 0, L_0x12cb360; 1 drivers +v0x1112690_0 .net *"_s10", 0 0, L_0x12cb8c0; 1 drivers +v0x1112770_0 .net *"_s12", 0 0, L_0x12cba20; 1 drivers +v0x1112830_0 .net *"_s14", 0 0, L_0x12cbc10; 1 drivers +v0x1132910_0 .net *"_s16", 0 0, L_0x12cbdc0; 1 drivers +v0x1132a40_0 .net *"_s3", 0 0, L_0x12cb420; 1 drivers +v0x1132b20_0 .net *"_s5", 0 0, L_0x12cb580; 1 drivers +v0x1132c00_0 .net *"_s6", 0 0, L_0x12cb7b0; 1 drivers +v0x1132ce0_0 .net "in", 3 0, L_0x12cbeb0; 1 drivers +v0x1132e50_0 .net "ors", 1 0, L_0x12cb6c0; 1 drivers +v0x1132f30_0 .net "out", 0 0, L_0x12cbba0; 1 drivers +L_0x12cb420 .part L_0x12cbeb0, 0, 1; +L_0x12cb580 .part L_0x12cbeb0, 1, 1; +L_0x12cb6c0 .concat8 [ 1 1 0 0], L_0x12cb360, L_0x12cb7b0; +L_0x12cb8c0 .part L_0x12cbeb0, 2, 1; +L_0x12cba20 .part L_0x12cbeb0, 3, 1; +L_0x12cbc10 .part L_0x12cb6c0, 0, 1; +L_0x12cbdc0 .part L_0x12cb6c0, 1, 1; +S_0x1133050 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1112180; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e387e0/d .functor OR 1, L_0x1e38850, L_0x1e389b0, C4<0>, C4<0>; -L_0x1e387e0 .delay 1 (30000,30000,30000) L_0x1e387e0/d; -L_0x1e38be0/d .functor OR 1, L_0x1e38cf0, L_0x1e38e50, C4<0>, C4<0>; -L_0x1e38be0 .delay 1 (30000,30000,30000) L_0x1e38be0/d; -L_0x1e38fd0/d .functor OR 1, L_0x1e39040, L_0x1e391f0, C4<0>, C4<0>; -L_0x1e38fd0 .delay 1 (30000,30000,30000) L_0x1e38fd0/d; -v0x1ca0590_0 .net *"_s0", 0 0, L_0x1e387e0; 1 drivers -v0x1ca0690_0 .net *"_s10", 0 0, L_0x1e38cf0; 1 drivers -v0x1ca0770_0 .net *"_s12", 0 0, L_0x1e38e50; 1 drivers -v0x1ca0830_0 .net *"_s14", 0 0, L_0x1e39040; 1 drivers -v0x1ca0910_0 .net *"_s16", 0 0, L_0x1e391f0; 1 drivers -v0x1ca0a40_0 .net *"_s3", 0 0, L_0x1e38850; 1 drivers -v0x1ca0b20_0 .net *"_s5", 0 0, L_0x1e389b0; 1 drivers -v0x1ca0c00_0 .net *"_s6", 0 0, L_0x1e38be0; 1 drivers -v0x1ca0ce0_0 .net "in", 3 0, L_0x1e39420; 1 drivers -v0x1ca0e50_0 .net "ors", 1 0, L_0x1e38af0; 1 drivers -v0x1ca0f30_0 .net "out", 0 0, L_0x1e38fd0; 1 drivers -L_0x1e38850 .part L_0x1e39420, 0, 1; -L_0x1e389b0 .part L_0x1e39420, 1, 1; -L_0x1e38af0 .concat8 [ 1 1 0 0], L_0x1e387e0, L_0x1e38be0; -L_0x1e38cf0 .part L_0x1e39420, 2, 1; -L_0x1e38e50 .part L_0x1e39420, 3, 1; -L_0x1e39040 .part L_0x1e38af0, 0, 1; -L_0x1e391f0 .part L_0x1e38af0, 1, 1; -S_0x1ca1840 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c751c0; +L_0x12cbfe0/d .functor OR 1, L_0x12cc050, L_0x12cc1b0, C4<0>, C4<0>; +L_0x12cbfe0 .delay 1 (30000,30000,30000) L_0x12cbfe0/d; +L_0x12cc3e0/d .functor OR 1, L_0x12cc4f0, L_0x12cc650, C4<0>, C4<0>; +L_0x12cc3e0 .delay 1 (30000,30000,30000) L_0x12cc3e0/d; +L_0x12cc7d0/d .functor OR 1, L_0x12cc840, L_0x12cc9f0, C4<0>, C4<0>; +L_0x12cc7d0 .delay 1 (30000,30000,30000) L_0x12cc7d0/d; +v0x1133210_0 .net *"_s0", 0 0, L_0x12cbfe0; 1 drivers +v0x1133310_0 .net *"_s10", 0 0, L_0x12cc4f0; 1 drivers +v0x11333f0_0 .net *"_s12", 0 0, L_0x12cc650; 1 drivers +v0x11334b0_0 .net *"_s14", 0 0, L_0x12cc840; 1 drivers +v0x1133590_0 .net *"_s16", 0 0, L_0x12cc9f0; 1 drivers +v0x11336c0_0 .net *"_s3", 0 0, L_0x12cc050; 1 drivers +v0x11337a0_0 .net *"_s5", 0 0, L_0x12cc1b0; 1 drivers +v0x1133880_0 .net *"_s6", 0 0, L_0x12cc3e0; 1 drivers +v0x1133960_0 .net "in", 3 0, L_0x12ccc20; 1 drivers +v0x1133ad0_0 .net "ors", 1 0, L_0x12cc2f0; 1 drivers +v0x1133bb0_0 .net "out", 0 0, L_0x12cc7d0; 1 drivers +L_0x12cc050 .part L_0x12ccc20, 0, 1; +L_0x12cc1b0 .part L_0x12ccc20, 1, 1; +L_0x12cc2f0 .concat8 [ 1 1 0 0], L_0x12cbfe0, L_0x12cc3e0; +L_0x12cc4f0 .part L_0x12ccc20, 2, 1; +L_0x12cc650 .part L_0x12ccc20, 3, 1; +L_0x12cc840 .part L_0x12cc2f0, 0, 1; +L_0x12cc9f0 .part L_0x12cc2f0, 1, 1; +S_0x11344c0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1107e40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -11260,80 +11270,80 @@ S_0x1ca1840 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1c751c0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e34d70/d .functor XNOR 1, L_0x1e3d390, L_0x1e3d4f0, C4<0>, C4<0>; -L_0x1e34d70 .delay 1 (20000,20000,20000) L_0x1e34d70/d; -L_0x1e34fe0/d .functor AND 1, L_0x1e3d390, L_0x1e33c60, C4<1>, C4<1>; -L_0x1e34fe0 .delay 1 (30000,30000,30000) L_0x1e34fe0/d; -L_0x1e35050/d .functor AND 1, L_0x1e34d70, L_0x1e33870, C4<1>, C4<1>; -L_0x1e35050 .delay 1 (30000,30000,30000) L_0x1e35050/d; -L_0x1e351b0/d .functor OR 1, L_0x1e35050, L_0x1e34fe0, C4<0>, C4<0>; -L_0x1e351b0 .delay 1 (30000,30000,30000) L_0x1e351b0/d; -v0x1ca1af0_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers -v0x1ca1be0_0 .net "a_", 0 0, L_0x1e33b00; alias, 1 drivers -v0x1ca1ca0_0 .net "b", 0 0, L_0x1e3d4f0; alias, 1 drivers -v0x1ca1d90_0 .net "b_", 0 0, L_0x1e33c60; alias, 1 drivers -v0x1ca1e30_0 .net "carryin", 0 0, L_0x1e33870; alias, 1 drivers -v0x1ca1f70_0 .net "eq", 0 0, L_0x1e34d70; 1 drivers -v0x1ca2030_0 .net "lt", 0 0, L_0x1e34fe0; 1 drivers -v0x1ca20f0_0 .net "out", 0 0, L_0x1e351b0; 1 drivers -v0x1ca21b0_0 .net "w0", 0 0, L_0x1e35050; 1 drivers -S_0x1ca2400 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1c751c0; +L_0x12c8570/d .functor XNOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; +L_0x12c8570 .delay 1 (20000,20000,20000) L_0x12c8570/d; +L_0x12c87e0/d .functor AND 1, L_0x12d0bf0, L_0x12c7460, C4<1>, C4<1>; +L_0x12c87e0 .delay 1 (30000,30000,30000) L_0x12c87e0/d; +L_0x12c8850/d .functor AND 1, L_0x12c8570, L_0x12c7070, C4<1>, C4<1>; +L_0x12c8850 .delay 1 (30000,30000,30000) L_0x12c8850/d; +L_0x12c89b0/d .functor OR 1, L_0x12c8850, L_0x12c87e0, C4<0>, C4<0>; +L_0x12c89b0 .delay 1 (30000,30000,30000) L_0x12c89b0/d; +v0x1134770_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers +v0x1134860_0 .net "a_", 0 0, L_0x12c7300; alias, 1 drivers +v0x1134920_0 .net "b", 0 0, L_0x12d0d50; alias, 1 drivers +v0x1134a10_0 .net "b_", 0 0, L_0x12c7460; alias, 1 drivers +v0x1134ab0_0 .net "carryin", 0 0, L_0x12c7070; alias, 1 drivers +v0x1134bf0_0 .net "eq", 0 0, L_0x12c8570; 1 drivers +v0x1134cb0_0 .net "lt", 0 0, L_0x12c87e0; 1 drivers +v0x1134d70_0 .net "out", 0 0, L_0x12c89b0; 1 drivers +v0x1134e30_0 .net "w0", 0 0, L_0x12c8850; 1 drivers +S_0x1135080 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1107e40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e34b50/d .functor OR 1, L_0x1e34650, L_0x1ca3660, C4<0>, C4<0>; -L_0x1e34b50 .delay 1 (30000,30000,30000) L_0x1e34b50/d; -v0x1ca31f0_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers -v0x1ca3340_0 .net "b", 0 0, L_0x1e33c60; alias, 1 drivers -v0x1ca3400_0 .net "c1", 0 0, L_0x1e34650; 1 drivers -v0x1ca34a0_0 .net "c2", 0 0, L_0x1ca3660; 1 drivers -v0x1ca3570_0 .net "carryin", 0 0, L_0x1e33870; alias, 1 drivers -v0x1ca36f0_0 .net "carryout", 0 0, L_0x1e34b50; 1 drivers -v0x1ca3790_0 .net "s1", 0 0, L_0x1e34590; 1 drivers -v0x1ca3830_0 .net "sum", 0 0, L_0x1e347b0; 1 drivers -S_0x1ca2650 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ca2400; +L_0x12c8350/d .functor OR 1, L_0x12c7e50, L_0x11362e0, C4<0>, C4<0>; +L_0x12c8350 .delay 1 (30000,30000,30000) L_0x12c8350/d; +v0x1135e70_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers +v0x1135fc0_0 .net "b", 0 0, L_0x12c7460; alias, 1 drivers +v0x1136080_0 .net "c1", 0 0, L_0x12c7e50; 1 drivers +v0x1136120_0 .net "c2", 0 0, L_0x11362e0; 1 drivers +v0x11361f0_0 .net "carryin", 0 0, L_0x12c7070; alias, 1 drivers +v0x1136370_0 .net "carryout", 0 0, L_0x12c8350; 1 drivers +v0x1136410_0 .net "s1", 0 0, L_0x12c7d90; 1 drivers +v0x11364b0_0 .net "sum", 0 0, L_0x12c7fb0; 1 drivers +S_0x11352d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1135080; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e34590/d .functor XOR 1, L_0x1e3d390, L_0x1e33c60, C4<0>, C4<0>; -L_0x1e34590 .delay 1 (30000,30000,30000) L_0x1e34590/d; -L_0x1e34650/d .functor AND 1, L_0x1e3d390, L_0x1e33c60, C4<1>, C4<1>; -L_0x1e34650 .delay 1 (30000,30000,30000) L_0x1e34650/d; -v0x1ca28b0_0 .net "a", 0 0, L_0x1e3d390; alias, 1 drivers -v0x1ca2970_0 .net "b", 0 0, L_0x1e33c60; alias, 1 drivers -v0x1ca2a30_0 .net "carryout", 0 0, L_0x1e34650; alias, 1 drivers -v0x1ca2ad0_0 .net "sum", 0 0, L_0x1e34590; alias, 1 drivers -S_0x1ca2c00 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ca2400; +L_0x12c7d90/d .functor XOR 1, L_0x12d0bf0, L_0x12c7460, C4<0>, C4<0>; +L_0x12c7d90 .delay 1 (30000,30000,30000) L_0x12c7d90/d; +L_0x12c7e50/d .functor AND 1, L_0x12d0bf0, L_0x12c7460, C4<1>, C4<1>; +L_0x12c7e50 .delay 1 (30000,30000,30000) L_0x12c7e50/d; +v0x1135530_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers +v0x11355f0_0 .net "b", 0 0, L_0x12c7460; alias, 1 drivers +v0x11356b0_0 .net "carryout", 0 0, L_0x12c7e50; alias, 1 drivers +v0x1135750_0 .net "sum", 0 0, L_0x12c7d90; alias, 1 drivers +S_0x1135880 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1135080; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e347b0/d .functor XOR 1, L_0x1e34590, L_0x1e33870, C4<0>, C4<0>; -L_0x1e347b0 .delay 1 (30000,30000,30000) L_0x1e347b0/d; -L_0x1ca3660/d .functor AND 1, L_0x1e34590, L_0x1e33870, C4<1>, C4<1>; -L_0x1ca3660 .delay 1 (30000,30000,30000) L_0x1ca3660/d; -v0x1ca2e60_0 .net "a", 0 0, L_0x1e34590; alias, 1 drivers -v0x1ca2f30_0 .net "b", 0 0, L_0x1e33870; alias, 1 drivers -v0x1ca2fd0_0 .net "carryout", 0 0, L_0x1ca3660; alias, 1 drivers -v0x1ca30a0_0 .net "sum", 0 0, L_0x1e347b0; alias, 1 drivers -S_0x1ca4c50 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1c74ef0; - .timescale -9 -12; -L_0x7f72592db698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db6e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e3d430/d .functor OR 1, L_0x7f72592db698, L_0x7f72592db6e0, C4<0>, C4<0>; -L_0x1e3d430 .delay 1 (30000,30000,30000) L_0x1e3d430/d; -v0x1ca4e40_0 .net/2u *"_s0", 0 0, L_0x7f72592db698; 1 drivers -v0x1ca4f20_0 .net/2u *"_s2", 0 0, L_0x7f72592db6e0; 1 drivers -S_0x1ca5000 .scope generate, "alu_slices[21]" "alu_slices[21]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1ca5210 .param/l "i" 0 3 37, +C4<010101>; -S_0x1ca52d0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ca5000; +L_0x12c7fb0/d .functor XOR 1, L_0x12c7d90, L_0x12c7070, C4<0>, C4<0>; +L_0x12c7fb0 .delay 1 (30000,30000,30000) L_0x12c7fb0/d; +L_0x11362e0/d .functor AND 1, L_0x12c7d90, L_0x12c7070, C4<1>, C4<1>; +L_0x11362e0 .delay 1 (30000,30000,30000) L_0x11362e0/d; +v0x1135ae0_0 .net "a", 0 0, L_0x12c7d90; alias, 1 drivers +v0x1135bb0_0 .net "b", 0 0, L_0x12c7070; alias, 1 drivers +v0x1135c50_0 .net "carryout", 0 0, L_0x11362e0; alias, 1 drivers +v0x1135d20_0 .net "sum", 0 0, L_0x12c7fb0; alias, 1 drivers +S_0x11378d0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1107b70; + .timescale -9 -12; +L_0x2b0ab3d06698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d066e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d0c90/d .functor OR 1, L_0x2b0ab3d06698, L_0x2b0ab3d066e0, C4<0>, C4<0>; +L_0x12d0c90 .delay 1 (30000,30000,30000) L_0x12d0c90/d; +v0x1137ac0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06698; 1 drivers +v0x1137ba0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d066e0; 1 drivers +S_0x1137c80 .scope generate, "alu_slices[21]" "alu_slices[21]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1137e90 .param/l "i" 0 3 41, +C4<010101>; +S_0x1137f50 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1137c80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -11342,445 +11352,445 @@ S_0x1ca52d0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ca5000; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e3d790/d .functor NOT 1, L_0x1da93a0, C4<0>, C4<0>, C4<0>; -L_0x1e3d790 .delay 1 (10000,10000,10000) L_0x1e3d790/d; -L_0x1e3d850/d .functor NOT 1, L_0x1da9500, C4<0>, C4<0>, C4<0>; -L_0x1e3d850 .delay 1 (10000,10000,10000) L_0x1e3d850/d; -L_0x1e3e850/d .functor XOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; -L_0x1e3e850 .delay 1 (30000,30000,30000) L_0x1e3e850/d; -L_0x7f72592db728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e3ef00/d .functor OR 1, L_0x7f72592db728, L_0x7f72592db770, C4<0>, C4<0>; -L_0x1e3ef00 .delay 1 (30000,30000,30000) L_0x1e3ef00/d; -L_0x1e3f100/d .functor AND 1, L_0x1da93a0, L_0x1da9500, C4<1>, C4<1>; -L_0x1e3f100 .delay 1 (30000,30000,30000) L_0x1e3f100/d; -L_0x1e3f1c0/d .functor NAND 1, L_0x1da93a0, L_0x1da9500, C4<1>, C4<1>; -L_0x1e3f1c0 .delay 1 (20000,20000,20000) L_0x1e3f1c0/d; -L_0x1e3f320/d .functor XOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; -L_0x1e3f320 .delay 1 (20000,20000,20000) L_0x1e3f320/d; -L_0x1e3f7d0/d .functor OR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; -L_0x1e3f7d0 .delay 1 (30000,30000,30000) L_0x1e3f7d0/d; -L_0x1da92a0/d .functor NOT 1, L_0x1e43140, C4<0>, C4<0>, C4<0>; -L_0x1da92a0 .delay 1 (10000,10000,10000) L_0x1da92a0/d; -v0x1cb3a10_0 .net "A", 0 0, L_0x1da93a0; 1 drivers -v0x1cb3ad0_0 .net "A_", 0 0, L_0x1e3d790; 1 drivers -v0x1cb3b90_0 .net "B", 0 0, L_0x1da9500; 1 drivers -v0x1cb3c60_0 .net "B_", 0 0, L_0x1e3d850; 1 drivers -v0x1cb3d00_0 .net *"_s12", 0 0, L_0x1e3ef00; 1 drivers -v0x1cb3df0_0 .net/2s *"_s14", 0 0, L_0x7f72592db728; 1 drivers -v0x1cb3eb0_0 .net/2s *"_s16", 0 0, L_0x7f72592db770; 1 drivers -v0x1cb3f90_0 .net *"_s18", 0 0, L_0x1e3f100; 1 drivers -v0x1cb4070_0 .net *"_s20", 0 0, L_0x1e3f1c0; 1 drivers -v0x1cb41e0_0 .net *"_s22", 0 0, L_0x1e3f320; 1 drivers -v0x1cb42c0_0 .net *"_s24", 0 0, L_0x1e3f7d0; 1 drivers -o0x7f7259326258 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1cb43a0_0 name=_s30 -o0x7f7259326288 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1cb4480_0 name=_s32 -v0x1cb4560_0 .net *"_s8", 0 0, L_0x1e3e850; 1 drivers -v0x1cb4640_0 .net "carryin", 0 0, L_0x1da95a0; 1 drivers -v0x1cb46e0_0 .net "carryout", 0 0, L_0x1da8f40; 1 drivers -v0x1cb4780_0 .net "carryouts", 7 0, L_0x1ec0f00; 1 drivers -v0x1cb4930_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cb49d0_0 .net "result", 0 0, L_0x1e43140; 1 drivers -v0x1cb4ac0_0 .net "results", 7 0, L_0x1e3f5a0; 1 drivers -v0x1cb4bd0_0 .net "zero", 0 0, L_0x1da92a0; 1 drivers -LS_0x1e3f5a0_0_0 .concat8 [ 1 1 1 1], L_0x1e3dd70, L_0x1e3e3a0, L_0x1e3e850, L_0x1e3ef00; -LS_0x1e3f5a0_0_4 .concat8 [ 1 1 1 1], L_0x1e3f100, L_0x1e3f1c0, L_0x1e3f320, L_0x1e3f7d0; -L_0x1e3f5a0 .concat8 [ 4 4 0 0], LS_0x1e3f5a0_0_0, LS_0x1e3f5a0_0_4; -LS_0x1ec0f00_0_0 .concat [ 1 1 1 1], L_0x1e3e020, L_0x1e3e6f0, o0x7f7259326258, L_0x1e3ed50; -LS_0x1ec0f00_0_4 .concat [ 4 0 0 0], o0x7f7259326288; -L_0x1ec0f00 .concat [ 4 4 0 0], LS_0x1ec0f00_0_0, LS_0x1ec0f00_0_4; -S_0x1ca5550 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1ca52d0; +L_0x12d0ff0/d .functor NOT 1, L_0x123cb70, C4<0>, C4<0>, C4<0>; +L_0x12d0ff0 .delay 1 (10000,10000,10000) L_0x12d0ff0/d; +L_0x12d1100/d .functor NOT 1, L_0x123ccd0, C4<0>, C4<0>, C4<0>; +L_0x12d1100 .delay 1 (10000,10000,10000) L_0x12d1100/d; +L_0x12d2150/d .functor XOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; +L_0x12d2150 .delay 1 (30000,30000,30000) L_0x12d2150/d; +L_0x2b0ab3d06728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12d2800/d .functor OR 1, L_0x2b0ab3d06728, L_0x2b0ab3d06770, C4<0>, C4<0>; +L_0x12d2800 .delay 1 (30000,30000,30000) L_0x12d2800/d; +L_0x12d2a00/d .functor AND 1, L_0x123cb70, L_0x123ccd0, C4<1>, C4<1>; +L_0x12d2a00 .delay 1 (30000,30000,30000) L_0x12d2a00/d; +L_0x12d2ac0/d .functor NAND 1, L_0x123cb70, L_0x123ccd0, C4<1>, C4<1>; +L_0x12d2ac0 .delay 1 (20000,20000,20000) L_0x12d2ac0/d; +L_0x12d2c20/d .functor XOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; +L_0x12d2c20 .delay 1 (20000,20000,20000) L_0x12d2c20/d; +L_0x12d30d0/d .functor OR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; +L_0x12d30d0 .delay 1 (30000,30000,30000) L_0x12d30d0/d; +L_0x123ca70/d .functor NOT 1, L_0x12d6850, C4<0>, C4<0>, C4<0>; +L_0x123ca70 .delay 1 (10000,10000,10000) L_0x123ca70/d; +v0x1146680_0 .net "A", 0 0, L_0x123cb70; 1 drivers +v0x1146740_0 .net "A_", 0 0, L_0x12d0ff0; 1 drivers +v0x1146800_0 .net "B", 0 0, L_0x123ccd0; 1 drivers +v0x11468d0_0 .net "B_", 0 0, L_0x12d1100; 1 drivers +v0x1146970_0 .net *"_s12", 0 0, L_0x12d2800; 1 drivers +v0x1146a60_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06728; 1 drivers +v0x1146b20_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06770; 1 drivers +v0x1146c00_0 .net *"_s18", 0 0, L_0x12d2a00; 1 drivers +v0x1146ce0_0 .net *"_s20", 0 0, L_0x12d2ac0; 1 drivers +v0x1146e50_0 .net *"_s22", 0 0, L_0x12d2c20; 1 drivers +v0x1146f30_0 .net *"_s24", 0 0, L_0x12d30d0; 1 drivers +o0x2b0ab3cd7258 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1147010_0 name=_s30 +o0x2b0ab3cd7288 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x11470f0_0 name=_s32 +v0x11471d0_0 .net *"_s8", 0 0, L_0x12d2150; 1 drivers +v0x11472b0_0 .net "carryin", 0 0, L_0x123cd70; 1 drivers +v0x1147350_0 .net "carryout", 0 0, L_0x123c710; 1 drivers +v0x11473f0_0 .net "carryouts", 7 0, L_0x1355230; 1 drivers +v0x11475a0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1147640_0 .net "result", 0 0, L_0x12d6850; 1 drivers +v0x1147730_0 .net "results", 7 0, L_0x12d2ea0; 1 drivers +v0x1147840_0 .net "zero", 0 0, L_0x123ca70; 1 drivers +LS_0x12d2ea0_0_0 .concat8 [ 1 1 1 1], L_0x12d1620, L_0x12d1c50, L_0x12d2150, L_0x12d2800; +LS_0x12d2ea0_0_4 .concat8 [ 1 1 1 1], L_0x12d2a00, L_0x12d2ac0, L_0x12d2c20, L_0x12d30d0; +L_0x12d2ea0 .concat8 [ 4 4 0 0], LS_0x12d2ea0_0_0, LS_0x12d2ea0_0_4; +LS_0x1355230_0_0 .concat [ 1 1 1 1], L_0x12d18d0, L_0x12d1ff0, o0x2b0ab3cd7258, L_0x12d2650; +LS_0x1355230_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd7288; +L_0x1355230 .concat [ 4 4 0 0], LS_0x1355230_0_0, LS_0x1355230_0_4; +S_0x11381d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1137f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e3e020/d .functor OR 1, L_0x1e3db00, L_0x1e3dec0, C4<0>, C4<0>; -L_0x1e3e020 .delay 1 (30000,30000,30000) L_0x1e3e020/d; -v0x1ca6380_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers -v0x1ca6440_0 .net "b", 0 0, L_0x1da9500; alias, 1 drivers -v0x1ca6510_0 .net "c1", 0 0, L_0x1e3db00; 1 drivers -v0x1ca6610_0 .net "c2", 0 0, L_0x1e3dec0; 1 drivers -v0x1ca66e0_0 .net "carryin", 0 0, L_0x1da95a0; alias, 1 drivers -v0x1ca67d0_0 .net "carryout", 0 0, L_0x1e3e020; 1 drivers -v0x1ca6870_0 .net "s1", 0 0, L_0x1e3da40; 1 drivers -v0x1ca6960_0 .net "sum", 0 0, L_0x1e3dd70; 1 drivers -S_0x1ca57c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ca5550; +L_0x12d18d0/d .functor OR 1, L_0x12d13b0, L_0x12d1770, C4<0>, C4<0>; +L_0x12d18d0 .delay 1 (30000,30000,30000) L_0x12d18d0/d; +v0x1139000_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers +v0x11390c0_0 .net "b", 0 0, L_0x123ccd0; alias, 1 drivers +v0x1139190_0 .net "c1", 0 0, L_0x12d13b0; 1 drivers +v0x1139290_0 .net "c2", 0 0, L_0x12d1770; 1 drivers +v0x1139360_0 .net "carryin", 0 0, L_0x123cd70; alias, 1 drivers +v0x1139450_0 .net "carryout", 0 0, L_0x12d18d0; 1 drivers +v0x11394f0_0 .net "s1", 0 0, L_0x12d12f0; 1 drivers +v0x11395e0_0 .net "sum", 0 0, L_0x12d1620; 1 drivers +S_0x1138440 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11381d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e3da40/d .functor XOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; -L_0x1e3da40 .delay 1 (30000,30000,30000) L_0x1e3da40/d; -L_0x1e3db00/d .functor AND 1, L_0x1da93a0, L_0x1da9500, C4<1>, C4<1>; -L_0x1e3db00 .delay 1 (30000,30000,30000) L_0x1e3db00/d; -v0x1ca5a20_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers -v0x1ca5b00_0 .net "b", 0 0, L_0x1da9500; alias, 1 drivers -v0x1ca5bc0_0 .net "carryout", 0 0, L_0x1e3db00; alias, 1 drivers -v0x1ca5c60_0 .net "sum", 0 0, L_0x1e3da40; alias, 1 drivers -S_0x1ca5da0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ca5550; +L_0x12d12f0/d .functor XOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; +L_0x12d12f0 .delay 1 (30000,30000,30000) L_0x12d12f0/d; +L_0x12d13b0/d .functor AND 1, L_0x123cb70, L_0x123ccd0, C4<1>, C4<1>; +L_0x12d13b0 .delay 1 (30000,30000,30000) L_0x12d13b0/d; +v0x11386a0_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers +v0x1138780_0 .net "b", 0 0, L_0x123ccd0; alias, 1 drivers +v0x1138840_0 .net "carryout", 0 0, L_0x12d13b0; alias, 1 drivers +v0x11388e0_0 .net "sum", 0 0, L_0x12d12f0; alias, 1 drivers +S_0x1138a20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11381d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e3dd70/d .functor XOR 1, L_0x1e3da40, L_0x1da95a0, C4<0>, C4<0>; -L_0x1e3dd70 .delay 1 (30000,30000,30000) L_0x1e3dd70/d; -L_0x1e3dec0/d .functor AND 1, L_0x1e3da40, L_0x1da95a0, C4<1>, C4<1>; -L_0x1e3dec0 .delay 1 (30000,30000,30000) L_0x1e3dec0/d; -v0x1ca6000_0 .net "a", 0 0, L_0x1e3da40; alias, 1 drivers -v0x1ca60a0_0 .net "b", 0 0, L_0x1da95a0; alias, 1 drivers -v0x1ca6140_0 .net "carryout", 0 0, L_0x1e3dec0; alias, 1 drivers -v0x1ca6210_0 .net "sum", 0 0, L_0x1e3dd70; alias, 1 drivers -S_0x1ca6a30 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1ca52d0; +L_0x12d1620/d .functor XOR 1, L_0x12d12f0, L_0x123cd70, C4<0>, C4<0>; +L_0x12d1620 .delay 1 (30000,30000,30000) L_0x12d1620/d; +L_0x12d1770/d .functor AND 1, L_0x12d12f0, L_0x123cd70, C4<1>, C4<1>; +L_0x12d1770 .delay 1 (30000,30000,30000) L_0x12d1770/d; +v0x1138c80_0 .net "a", 0 0, L_0x12d12f0; alias, 1 drivers +v0x1138d20_0 .net "b", 0 0, L_0x123cd70; alias, 1 drivers +v0x1138dc0_0 .net "carryout", 0 0, L_0x12d1770; alias, 1 drivers +v0x1138e90_0 .net "sum", 0 0, L_0x12d1620; alias, 1 drivers +S_0x11396b0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1137f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cabe20_0 .net "ands", 7 0, L_0x1e44b80; 1 drivers -v0x1cabf30_0 .net "in", 7 0, L_0x1ec0f00; alias, 1 drivers -v0x1cabff0_0 .net "out", 0 0, L_0x1da8f40; alias, 1 drivers -v0x1cac0c0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1ca6c50 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ca6a30; +v0x113eaa0_0 .net "ands", 7 0, L_0x12d8370; 1 drivers +v0x113ebb0_0 .net "in", 7 0, L_0x1355230; alias, 1 drivers +v0x113ec70_0 .net "out", 0 0, L_0x123c710; alias, 1 drivers +v0x113ed40_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11398d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11396b0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1ca9380_0 .net "A", 7 0, L_0x1ec0f00; alias, 1 drivers -v0x1ca9480_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ca9540_0 .net *"_s0", 0 0, L_0x1e434a0; 1 drivers -v0x1ca9600_0 .net *"_s12", 0 0, L_0x1e43e10; 1 drivers -v0x1ca96e0_0 .net *"_s16", 0 0, L_0x1e44170; 1 drivers -v0x1ca9810_0 .net *"_s20", 0 0, L_0x1e44480; 1 drivers -v0x1ca98f0_0 .net *"_s24", 0 0, L_0x1e44870; 1 drivers -v0x1ca99d0_0 .net *"_s28", 0 0, L_0x1e44800; 1 drivers -v0x1ca9ab0_0 .net *"_s4", 0 0, L_0x1e437b0; 1 drivers -v0x1ca9c20_0 .net *"_s8", 0 0, L_0x1e43b00; 1 drivers -v0x1ca9d00_0 .net "out", 7 0, L_0x1e44b80; alias, 1 drivers -L_0x1e43560 .part L_0x1ec0f00, 0, 1; -L_0x1e436c0 .part v0x1d6daa0_0, 0, 1; -L_0x1e43870 .part L_0x1ec0f00, 1, 1; -L_0x1e43a60 .part v0x1d6daa0_0, 1, 1; -L_0x1e43bc0 .part L_0x1ec0f00, 2, 1; -L_0x1e43d20 .part v0x1d6daa0_0, 2, 1; -L_0x1e43ed0 .part L_0x1ec0f00, 3, 1; -L_0x1e44030 .part v0x1d6daa0_0, 3, 1; -L_0x1e44230 .part L_0x1ec0f00, 4, 1; -L_0x1e44390 .part v0x1d6daa0_0, 4, 1; -L_0x1e444f0 .part L_0x1ec0f00, 5, 1; -L_0x1e44760 .part v0x1d6daa0_0, 5, 1; -L_0x1e44930 .part L_0x1ec0f00, 6, 1; -L_0x1e44a90 .part v0x1d6daa0_0, 6, 1; -LS_0x1e44b80_0_0 .concat8 [ 1 1 1 1], L_0x1e434a0, L_0x1e437b0, L_0x1e43b00, L_0x1e43e10; -LS_0x1e44b80_0_4 .concat8 [ 1 1 1 1], L_0x1e44170, L_0x1e44480, L_0x1e44870, L_0x1e44800; -L_0x1e44b80 .concat8 [ 4 4 0 0], LS_0x1e44b80_0_0, LS_0x1e44b80_0_4; -L_0x1e44f40 .part L_0x1ec0f00, 7, 1; -L_0x1e45130 .part v0x1d6daa0_0, 7, 1; -S_0x1ca6eb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca70c0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e434a0/d .functor AND 1, L_0x1e43560, L_0x1e436c0, C4<1>, C4<1>; -L_0x1e434a0 .delay 1 (30000,30000,30000) L_0x1e434a0/d; -v0x1ca71a0_0 .net *"_s0", 0 0, L_0x1e43560; 1 drivers -v0x1ca7280_0 .net *"_s1", 0 0, L_0x1e436c0; 1 drivers -S_0x1ca7360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca7570 .param/l "i" 0 4 54, +C4<01>; -L_0x1e437b0/d .functor AND 1, L_0x1e43870, L_0x1e43a60, C4<1>, C4<1>; -L_0x1e437b0 .delay 1 (30000,30000,30000) L_0x1e437b0/d; -v0x1ca7630_0 .net *"_s0", 0 0, L_0x1e43870; 1 drivers -v0x1ca7710_0 .net *"_s1", 0 0, L_0x1e43a60; 1 drivers -S_0x1ca77f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca7a00 .param/l "i" 0 4 54, +C4<010>; -L_0x1e43b00/d .functor AND 1, L_0x1e43bc0, L_0x1e43d20, C4<1>, C4<1>; -L_0x1e43b00 .delay 1 (30000,30000,30000) L_0x1e43b00/d; -v0x1ca7aa0_0 .net *"_s0", 0 0, L_0x1e43bc0; 1 drivers -v0x1ca7b80_0 .net *"_s1", 0 0, L_0x1e43d20; 1 drivers -S_0x1ca7c60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca7e70 .param/l "i" 0 4 54, +C4<011>; -L_0x1e43e10/d .functor AND 1, L_0x1e43ed0, L_0x1e44030, C4<1>, C4<1>; -L_0x1e43e10 .delay 1 (30000,30000,30000) L_0x1e43e10/d; -v0x1ca7f30_0 .net *"_s0", 0 0, L_0x1e43ed0; 1 drivers -v0x1ca8010_0 .net *"_s1", 0 0, L_0x1e44030; 1 drivers -S_0x1ca80f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca8350 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e44170/d .functor AND 1, L_0x1e44230, L_0x1e44390, C4<1>, C4<1>; -L_0x1e44170 .delay 1 (30000,30000,30000) L_0x1e44170/d; -v0x1ca8410_0 .net *"_s0", 0 0, L_0x1e44230; 1 drivers -v0x1ca84f0_0 .net *"_s1", 0 0, L_0x1e44390; 1 drivers -S_0x1ca85d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca87e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e44480/d .functor AND 1, L_0x1e444f0, L_0x1e44760, C4<1>, C4<1>; -L_0x1e44480 .delay 1 (30000,30000,30000) L_0x1e44480/d; -v0x1ca88a0_0 .net *"_s0", 0 0, L_0x1e444f0; 1 drivers -v0x1ca8980_0 .net *"_s1", 0 0, L_0x1e44760; 1 drivers -S_0x1ca8a60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca8c70 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e44870/d .functor AND 1, L_0x1e44930, L_0x1e44a90, C4<1>, C4<1>; -L_0x1e44870 .delay 1 (30000,30000,30000) L_0x1e44870/d; -v0x1ca8d30_0 .net *"_s0", 0 0, L_0x1e44930; 1 drivers -v0x1ca8e10_0 .net *"_s1", 0 0, L_0x1e44a90; 1 drivers -S_0x1ca8ef0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ca6c50; - .timescale -9 -12; -P_0x1ca9100 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e44800/d .functor AND 1, L_0x1e44f40, L_0x1e45130, C4<1>, C4<1>; -L_0x1e44800 .delay 1 (30000,30000,30000) L_0x1e44800/d; -v0x1ca91c0_0 .net *"_s0", 0 0, L_0x1e44f40; 1 drivers -v0x1ca92a0_0 .net *"_s1", 0 0, L_0x1e45130; 1 drivers -S_0x1ca9e60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ca6a30; +v0x113c000_0 .net "A", 7 0, L_0x1355230; alias, 1 drivers +v0x113c100_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x113c1c0_0 .net *"_s0", 0 0, L_0x12d6bb0; 1 drivers +v0x113c280_0 .net *"_s12", 0 0, L_0x12d7520; 1 drivers +v0x113c360_0 .net *"_s16", 0 0, L_0x12d7880; 1 drivers +v0x113c490_0 .net *"_s20", 0 0, L_0x12d7bf0; 1 drivers +v0x113c570_0 .net *"_s24", 0 0, L_0x12d7fe0; 1 drivers +v0x113c650_0 .net *"_s28", 0 0, L_0x12d7f70; 1 drivers +v0x113c730_0 .net *"_s4", 0 0, L_0x12d6ec0; 1 drivers +v0x113c8a0_0 .net *"_s8", 0 0, L_0x12d7210; 1 drivers +v0x113c980_0 .net "out", 7 0, L_0x12d8370; alias, 1 drivers +L_0x12d6c70 .part L_0x1355230, 0, 1; +L_0x12d6dd0 .part v0x12010b0_0, 0, 1; +L_0x12d6f80 .part L_0x1355230, 1, 1; +L_0x12d7170 .part v0x12010b0_0, 1, 1; +L_0x12d72d0 .part L_0x1355230, 2, 1; +L_0x12d7430 .part v0x12010b0_0, 2, 1; +L_0x12d75e0 .part L_0x1355230, 3, 1; +L_0x12d7740 .part v0x12010b0_0, 3, 1; +L_0x12d7940 .part L_0x1355230, 4, 1; +L_0x12d7aa0 .part v0x12010b0_0, 4, 1; +L_0x12d7c60 .part L_0x1355230, 5, 1; +L_0x12d7ed0 .part v0x12010b0_0, 5, 1; +L_0x12d80a0 .part L_0x1355230, 6, 1; +L_0x12d8200 .part v0x12010b0_0, 6, 1; +LS_0x12d8370_0_0 .concat8 [ 1 1 1 1], L_0x12d6bb0, L_0x12d6ec0, L_0x12d7210, L_0x12d7520; +LS_0x12d8370_0_4 .concat8 [ 1 1 1 1], L_0x12d7880, L_0x12d7bf0, L_0x12d7fe0, L_0x12d7f70; +L_0x12d8370 .concat8 [ 4 4 0 0], LS_0x12d8370_0_0, LS_0x12d8370_0_4; +L_0x12d8730 .part L_0x1355230, 7, 1; +L_0x12d8920 .part v0x12010b0_0, 7, 1; +S_0x1139b30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x1139d40 .param/l "i" 0 4 54, +C4<00>; +L_0x12d6bb0/d .functor AND 1, L_0x12d6c70, L_0x12d6dd0, C4<1>, C4<1>; +L_0x12d6bb0 .delay 1 (30000,30000,30000) L_0x12d6bb0/d; +v0x1139e20_0 .net *"_s0", 0 0, L_0x12d6c70; 1 drivers +v0x1139f00_0 .net *"_s1", 0 0, L_0x12d6dd0; 1 drivers +S_0x1139fe0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113a1f0 .param/l "i" 0 4 54, +C4<01>; +L_0x12d6ec0/d .functor AND 1, L_0x12d6f80, L_0x12d7170, C4<1>, C4<1>; +L_0x12d6ec0 .delay 1 (30000,30000,30000) L_0x12d6ec0/d; +v0x113a2b0_0 .net *"_s0", 0 0, L_0x12d6f80; 1 drivers +v0x113a390_0 .net *"_s1", 0 0, L_0x12d7170; 1 drivers +S_0x113a470 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113a680 .param/l "i" 0 4 54, +C4<010>; +L_0x12d7210/d .functor AND 1, L_0x12d72d0, L_0x12d7430, C4<1>, C4<1>; +L_0x12d7210 .delay 1 (30000,30000,30000) L_0x12d7210/d; +v0x113a720_0 .net *"_s0", 0 0, L_0x12d72d0; 1 drivers +v0x113a800_0 .net *"_s1", 0 0, L_0x12d7430; 1 drivers +S_0x113a8e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113aaf0 .param/l "i" 0 4 54, +C4<011>; +L_0x12d7520/d .functor AND 1, L_0x12d75e0, L_0x12d7740, C4<1>, C4<1>; +L_0x12d7520 .delay 1 (30000,30000,30000) L_0x12d7520/d; +v0x113abb0_0 .net *"_s0", 0 0, L_0x12d75e0; 1 drivers +v0x113ac90_0 .net *"_s1", 0 0, L_0x12d7740; 1 drivers +S_0x113ad70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113afd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12d7880/d .functor AND 1, L_0x12d7940, L_0x12d7aa0, C4<1>, C4<1>; +L_0x12d7880 .delay 1 (30000,30000,30000) L_0x12d7880/d; +v0x113b090_0 .net *"_s0", 0 0, L_0x12d7940; 1 drivers +v0x113b170_0 .net *"_s1", 0 0, L_0x12d7aa0; 1 drivers +S_0x113b250 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113b460 .param/l "i" 0 4 54, +C4<0101>; +L_0x12d7bf0/d .functor AND 1, L_0x12d7c60, L_0x12d7ed0, C4<1>, C4<1>; +L_0x12d7bf0 .delay 1 (30000,30000,30000) L_0x12d7bf0/d; +v0x113b520_0 .net *"_s0", 0 0, L_0x12d7c60; 1 drivers +v0x113b600_0 .net *"_s1", 0 0, L_0x12d7ed0; 1 drivers +S_0x113b6e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113b8f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12d7fe0/d .functor AND 1, L_0x12d80a0, L_0x12d8200, C4<1>, C4<1>; +L_0x12d7fe0 .delay 1 (30000,30000,30000) L_0x12d7fe0/d; +v0x113b9b0_0 .net *"_s0", 0 0, L_0x12d80a0; 1 drivers +v0x113ba90_0 .net *"_s1", 0 0, L_0x12d8200; 1 drivers +S_0x113bb70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11398d0; + .timescale -9 -12; +P_0x113bd80 .param/l "i" 0 4 54, +C4<0111>; +L_0x12d7f70/d .functor AND 1, L_0x12d8730, L_0x12d8920, C4<1>, C4<1>; +L_0x12d7f70 .delay 1 (30000,30000,30000) L_0x12d7f70/d; +v0x113be40_0 .net *"_s0", 0 0, L_0x12d8730; 1 drivers +v0x113bf20_0 .net *"_s1", 0 0, L_0x12d8920; 1 drivers +S_0x113cae0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11396b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1da8f40/d .functor OR 1, L_0x1da9000, L_0x1da91b0, C4<0>, C4<0>; -L_0x1da8f40 .delay 1 (30000,30000,30000) L_0x1da8f40/d; -v0x1cab9b0_0 .net *"_s10", 0 0, L_0x1da9000; 1 drivers -v0x1caba90_0 .net *"_s12", 0 0, L_0x1da91b0; 1 drivers -v0x1cabb70_0 .net "in", 7 0, L_0x1e44b80; alias, 1 drivers -v0x1cabc40_0 .net "ors", 1 0, L_0x1da8d60; 1 drivers -v0x1cabd00_0 .net "out", 0 0, L_0x1da8f40; alias, 1 drivers -L_0x1da8130 .part L_0x1e44b80, 0, 4; -L_0x1da8d60 .concat8 [ 1 1 0 0], L_0x1da7e20, L_0x1da8a50; -L_0x1da8ea0 .part L_0x1e44b80, 4, 4; -L_0x1da9000 .part L_0x1da8d60, 0, 1; -L_0x1da91b0 .part L_0x1da8d60, 1, 1; -S_0x1caa020 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1ca9e60; +L_0x123c710/d .functor OR 1, L_0x123c7d0, L_0x123c980, C4<0>, C4<0>; +L_0x123c710 .delay 1 (30000,30000,30000) L_0x123c710/d; +v0x113e630_0 .net *"_s10", 0 0, L_0x123c7d0; 1 drivers +v0x113e710_0 .net *"_s12", 0 0, L_0x123c980; 1 drivers +v0x113e7f0_0 .net "in", 7 0, L_0x12d8370; alias, 1 drivers +v0x113e8c0_0 .net "ors", 1 0, L_0x123c530; 1 drivers +v0x113e980_0 .net "out", 0 0, L_0x123c710; alias, 1 drivers +L_0x123b8d0 .part L_0x12d8370, 0, 4; +L_0x123c530 .concat8 [ 1 1 0 0], L_0x123b5c0, L_0x123c1f0; +L_0x123c670 .part L_0x12d8370, 4, 4; +L_0x123c7d0 .part L_0x123c530, 0, 1; +L_0x123c980 .part L_0x123c530, 1, 1; +S_0x113cca0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x113cae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e410c0/d .functor OR 1, L_0x1da76a0, L_0x1da7800, C4<0>, C4<0>; -L_0x1e410c0 .delay 1 (30000,30000,30000) L_0x1e410c0/d; -L_0x1da7a30/d .functor OR 1, L_0x1da7b40, L_0x1da7ca0, C4<0>, C4<0>; -L_0x1da7a30 .delay 1 (30000,30000,30000) L_0x1da7a30/d; -L_0x1da7e20/d .functor OR 1, L_0x1da7e90, L_0x1da8040, C4<0>, C4<0>; -L_0x1da7e20 .delay 1 (30000,30000,30000) L_0x1da7e20/d; -v0x1caa270_0 .net *"_s0", 0 0, L_0x1e410c0; 1 drivers -v0x1caa370_0 .net *"_s10", 0 0, L_0x1da7b40; 1 drivers -v0x1caa450_0 .net *"_s12", 0 0, L_0x1da7ca0; 1 drivers -v0x1caa510_0 .net *"_s14", 0 0, L_0x1da7e90; 1 drivers -v0x1caa5f0_0 .net *"_s16", 0 0, L_0x1da8040; 1 drivers -v0x1caa720_0 .net *"_s3", 0 0, L_0x1da76a0; 1 drivers -v0x1caa800_0 .net *"_s5", 0 0, L_0x1da7800; 1 drivers -v0x1caa8e0_0 .net *"_s6", 0 0, L_0x1da7a30; 1 drivers -v0x1caa9c0_0 .net "in", 3 0, L_0x1da8130; 1 drivers -v0x1caab30_0 .net "ors", 1 0, L_0x1da7940; 1 drivers -v0x1caac10_0 .net "out", 0 0, L_0x1da7e20; 1 drivers -L_0x1da76a0 .part L_0x1da8130, 0, 1; -L_0x1da7800 .part L_0x1da8130, 1, 1; -L_0x1da7940 .concat8 [ 1 1 0 0], L_0x1e410c0, L_0x1da7a30; -L_0x1da7b40 .part L_0x1da8130, 2, 1; -L_0x1da7ca0 .part L_0x1da8130, 3, 1; -L_0x1da7e90 .part L_0x1da7940, 0, 1; -L_0x1da8040 .part L_0x1da7940, 1, 1; -S_0x1caad30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1ca9e60; +L_0x12d82f0/d .functor OR 1, L_0x123ae40, L_0x123afa0, C4<0>, C4<0>; +L_0x12d82f0 .delay 1 (30000,30000,30000) L_0x12d82f0/d; +L_0x123b1d0/d .functor OR 1, L_0x123b2e0, L_0x123b440, C4<0>, C4<0>; +L_0x123b1d0 .delay 1 (30000,30000,30000) L_0x123b1d0/d; +L_0x123b5c0/d .functor OR 1, L_0x123b630, L_0x123b7e0, C4<0>, C4<0>; +L_0x123b5c0 .delay 1 (30000,30000,30000) L_0x123b5c0/d; +v0x113cef0_0 .net *"_s0", 0 0, L_0x12d82f0; 1 drivers +v0x113cff0_0 .net *"_s10", 0 0, L_0x123b2e0; 1 drivers +v0x113d0d0_0 .net *"_s12", 0 0, L_0x123b440; 1 drivers +v0x113d190_0 .net *"_s14", 0 0, L_0x123b630; 1 drivers +v0x113d270_0 .net *"_s16", 0 0, L_0x123b7e0; 1 drivers +v0x113d3a0_0 .net *"_s3", 0 0, L_0x123ae40; 1 drivers +v0x113d480_0 .net *"_s5", 0 0, L_0x123afa0; 1 drivers +v0x113d560_0 .net *"_s6", 0 0, L_0x123b1d0; 1 drivers +v0x113d640_0 .net "in", 3 0, L_0x123b8d0; 1 drivers +v0x113d7b0_0 .net "ors", 1 0, L_0x123b0e0; 1 drivers +v0x113d890_0 .net "out", 0 0, L_0x123b5c0; 1 drivers +L_0x123ae40 .part L_0x123b8d0, 0, 1; +L_0x123afa0 .part L_0x123b8d0, 1, 1; +L_0x123b0e0 .concat8 [ 1 1 0 0], L_0x12d82f0, L_0x123b1d0; +L_0x123b2e0 .part L_0x123b8d0, 2, 1; +L_0x123b440 .part L_0x123b8d0, 3, 1; +L_0x123b630 .part L_0x123b0e0, 0, 1; +L_0x123b7e0 .part L_0x123b0e0, 1, 1; +S_0x113d9b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x113cae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1da8260/d .functor OR 1, L_0x1da82d0, L_0x1da8430, C4<0>, C4<0>; -L_0x1da8260 .delay 1 (30000,30000,30000) L_0x1da8260/d; -L_0x1da8660/d .functor OR 1, L_0x1da8770, L_0x1da88d0, C4<0>, C4<0>; -L_0x1da8660 .delay 1 (30000,30000,30000) L_0x1da8660/d; -L_0x1da8a50/d .functor OR 1, L_0x1da8ac0, L_0x1da8c70, C4<0>, C4<0>; -L_0x1da8a50 .delay 1 (30000,30000,30000) L_0x1da8a50/d; -v0x1caaef0_0 .net *"_s0", 0 0, L_0x1da8260; 1 drivers -v0x1caaff0_0 .net *"_s10", 0 0, L_0x1da8770; 1 drivers -v0x1cab0d0_0 .net *"_s12", 0 0, L_0x1da88d0; 1 drivers -v0x1cab190_0 .net *"_s14", 0 0, L_0x1da8ac0; 1 drivers -v0x1cab270_0 .net *"_s16", 0 0, L_0x1da8c70; 1 drivers -v0x1cab3a0_0 .net *"_s3", 0 0, L_0x1da82d0; 1 drivers -v0x1cab480_0 .net *"_s5", 0 0, L_0x1da8430; 1 drivers -v0x1cab560_0 .net *"_s6", 0 0, L_0x1da8660; 1 drivers -v0x1cab640_0 .net "in", 3 0, L_0x1da8ea0; 1 drivers -v0x1cab7b0_0 .net "ors", 1 0, L_0x1da8570; 1 drivers -v0x1cab890_0 .net "out", 0 0, L_0x1da8a50; 1 drivers -L_0x1da82d0 .part L_0x1da8ea0, 0, 1; -L_0x1da8430 .part L_0x1da8ea0, 1, 1; -L_0x1da8570 .concat8 [ 1 1 0 0], L_0x1da8260, L_0x1da8660; -L_0x1da8770 .part L_0x1da8ea0, 2, 1; -L_0x1da88d0 .part L_0x1da8ea0, 3, 1; -L_0x1da8ac0 .part L_0x1da8570, 0, 1; -L_0x1da8c70 .part L_0x1da8570, 1, 1; -S_0x1cac1a0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1ca52d0; +L_0x123ba00/d .functor OR 1, L_0x123ba70, L_0x123bbd0, C4<0>, C4<0>; +L_0x123ba00 .delay 1 (30000,30000,30000) L_0x123ba00/d; +L_0x123be00/d .functor OR 1, L_0x123bf10, L_0x123c070, C4<0>, C4<0>; +L_0x123be00 .delay 1 (30000,30000,30000) L_0x123be00/d; +L_0x123c1f0/d .functor OR 1, L_0x123c290, L_0x123c440, C4<0>, C4<0>; +L_0x123c1f0 .delay 1 (30000,30000,30000) L_0x123c1f0/d; +v0x113db70_0 .net *"_s0", 0 0, L_0x123ba00; 1 drivers +v0x113dc70_0 .net *"_s10", 0 0, L_0x123bf10; 1 drivers +v0x113dd50_0 .net *"_s12", 0 0, L_0x123c070; 1 drivers +v0x113de10_0 .net *"_s14", 0 0, L_0x123c290; 1 drivers +v0x113def0_0 .net *"_s16", 0 0, L_0x123c440; 1 drivers +v0x113e020_0 .net *"_s3", 0 0, L_0x123ba70; 1 drivers +v0x113e100_0 .net *"_s5", 0 0, L_0x123bbd0; 1 drivers +v0x113e1e0_0 .net *"_s6", 0 0, L_0x123be00; 1 drivers +v0x113e2c0_0 .net "in", 3 0, L_0x123c670; 1 drivers +v0x113e430_0 .net "ors", 1 0, L_0x123bd10; 1 drivers +v0x113e510_0 .net "out", 0 0, L_0x123c1f0; 1 drivers +L_0x123ba70 .part L_0x123c670, 0, 1; +L_0x123bbd0 .part L_0x123c670, 1, 1; +L_0x123bd10 .concat8 [ 1 1 0 0], L_0x123ba00, L_0x123be00; +L_0x123bf10 .part L_0x123c670, 2, 1; +L_0x123c070 .part L_0x123c670, 3, 1; +L_0x123c290 .part L_0x123bd10, 0, 1; +L_0x123c440 .part L_0x123bd10, 1, 1; +S_0x113ee20 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1137f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cb15d0_0 .net "ands", 7 0, L_0x1e41140; 1 drivers -v0x1cb16e0_0 .net "in", 7 0, L_0x1e3f5a0; alias, 1 drivers -v0x1cb17a0_0 .net "out", 0 0, L_0x1e43140; alias, 1 drivers -v0x1cb1870_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cac3f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cac1a0; +v0x1144250_0 .net "ands", 7 0, L_0x12d4960; 1 drivers +v0x1144360_0 .net "in", 7 0, L_0x12d2ea0; alias, 1 drivers +v0x1144420_0 .net "out", 0 0, L_0x12d6850; alias, 1 drivers +v0x11444f0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x113f070 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x113ee20; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1caeb30_0 .net "A", 7 0, L_0x1e3f5a0; alias, 1 drivers -v0x1caec30_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1caecf0_0 .net *"_s0", 0 0, L_0x1e3f930; 1 drivers -v0x1caedb0_0 .net *"_s12", 0 0, L_0x1e402f0; 1 drivers -v0x1caee90_0 .net *"_s16", 0 0, L_0x1e40650; 1 drivers -v0x1caefc0_0 .net *"_s20", 0 0, L_0x1e40a80; 1 drivers -v0x1caf0a0_0 .net *"_s24", 0 0, L_0x1e40db0; 1 drivers -v0x1caf180_0 .net *"_s28", 0 0, L_0x1e40d40; 1 drivers -v0x1caf260_0 .net *"_s4", 0 0, L_0x1e3fcd0; 1 drivers -v0x1caf3d0_0 .net *"_s8", 0 0, L_0x1e3ffe0; 1 drivers -v0x1caf4b0_0 .net "out", 7 0, L_0x1e41140; alias, 1 drivers -L_0x1e3fa40 .part L_0x1e3f5a0, 0, 1; -L_0x1e3fc30 .part v0x1d6daa0_0, 0, 1; -L_0x1e3fd90 .part L_0x1e3f5a0, 1, 1; -L_0x1e3fef0 .part v0x1d6daa0_0, 1, 1; -L_0x1e400a0 .part L_0x1e3f5a0, 2, 1; -L_0x1e40200 .part v0x1d6daa0_0, 2, 1; -L_0x1e403b0 .part L_0x1e3f5a0, 3, 1; -L_0x1e40510 .part v0x1d6daa0_0, 3, 1; -L_0x1e40710 .part L_0x1e3f5a0, 4, 1; -L_0x1e40980 .part v0x1d6daa0_0, 4, 1; -L_0x1e40af0 .part L_0x1e3f5a0, 5, 1; -L_0x1e40c50 .part v0x1d6daa0_0, 5, 1; -L_0x1e40e70 .part L_0x1e3f5a0, 6, 1; -L_0x1e40fd0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e41140_0_0 .concat8 [ 1 1 1 1], L_0x1e3f930, L_0x1e3fcd0, L_0x1e3ffe0, L_0x1e402f0; -LS_0x1e41140_0_4 .concat8 [ 1 1 1 1], L_0x1e40650, L_0x1e40a80, L_0x1e40db0, L_0x1e40d40; -L_0x1e41140 .concat8 [ 4 4 0 0], LS_0x1e41140_0_0, LS_0x1e41140_0_4; -L_0x1e41500 .part L_0x1e3f5a0, 7, 1; -L_0x1e416f0 .part v0x1d6daa0_0, 7, 1; -S_0x1cac630 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cac840 .param/l "i" 0 4 54, +C4<00>; -L_0x1e3f930/d .functor AND 1, L_0x1e3fa40, L_0x1e3fc30, C4<1>, C4<1>; -L_0x1e3f930 .delay 1 (30000,30000,30000) L_0x1e3f930/d; -v0x1cac920_0 .net *"_s0", 0 0, L_0x1e3fa40; 1 drivers -v0x1caca00_0 .net *"_s1", 0 0, L_0x1e3fc30; 1 drivers -S_0x1cacae0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1caccf0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e3fcd0/d .functor AND 1, L_0x1e3fd90, L_0x1e3fef0, C4<1>, C4<1>; -L_0x1e3fcd0 .delay 1 (30000,30000,30000) L_0x1e3fcd0/d; -v0x1cacdb0_0 .net *"_s0", 0 0, L_0x1e3fd90; 1 drivers -v0x1cace90_0 .net *"_s1", 0 0, L_0x1e3fef0; 1 drivers -S_0x1cacf70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cad1b0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e3ffe0/d .functor AND 1, L_0x1e400a0, L_0x1e40200, C4<1>, C4<1>; -L_0x1e3ffe0 .delay 1 (30000,30000,30000) L_0x1e3ffe0/d; -v0x1cad250_0 .net *"_s0", 0 0, L_0x1e400a0; 1 drivers -v0x1cad330_0 .net *"_s1", 0 0, L_0x1e40200; 1 drivers -S_0x1cad410 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cad620 .param/l "i" 0 4 54, +C4<011>; -L_0x1e402f0/d .functor AND 1, L_0x1e403b0, L_0x1e40510, C4<1>, C4<1>; -L_0x1e402f0 .delay 1 (30000,30000,30000) L_0x1e402f0/d; -v0x1cad6e0_0 .net *"_s0", 0 0, L_0x1e403b0; 1 drivers -v0x1cad7c0_0 .net *"_s1", 0 0, L_0x1e40510; 1 drivers -S_0x1cad8a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cadb00 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e40650/d .functor AND 1, L_0x1e40710, L_0x1e40980, C4<1>, C4<1>; -L_0x1e40650 .delay 1 (30000,30000,30000) L_0x1e40650/d; -v0x1cadbc0_0 .net *"_s0", 0 0, L_0x1e40710; 1 drivers -v0x1cadca0_0 .net *"_s1", 0 0, L_0x1e40980; 1 drivers -S_0x1cadd80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cadf90 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e40a80/d .functor AND 1, L_0x1e40af0, L_0x1e40c50, C4<1>, C4<1>; -L_0x1e40a80 .delay 1 (30000,30000,30000) L_0x1e40a80/d; -v0x1cae050_0 .net *"_s0", 0 0, L_0x1e40af0; 1 drivers -v0x1cae130_0 .net *"_s1", 0 0, L_0x1e40c50; 1 drivers -S_0x1cae210 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cae420 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e40db0/d .functor AND 1, L_0x1e40e70, L_0x1e40fd0, C4<1>, C4<1>; -L_0x1e40db0 .delay 1 (30000,30000,30000) L_0x1e40db0/d; -v0x1cae4e0_0 .net *"_s0", 0 0, L_0x1e40e70; 1 drivers -v0x1cae5c0_0 .net *"_s1", 0 0, L_0x1e40fd0; 1 drivers -S_0x1cae6a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cac3f0; - .timescale -9 -12; -P_0x1cae8b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e40d40/d .functor AND 1, L_0x1e41500, L_0x1e416f0, C4<1>, C4<1>; -L_0x1e40d40 .delay 1 (30000,30000,30000) L_0x1e40d40/d; -v0x1cae970_0 .net *"_s0", 0 0, L_0x1e41500; 1 drivers -v0x1caea50_0 .net *"_s1", 0 0, L_0x1e416f0; 1 drivers -S_0x1caf610 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cac1a0; +v0x11417b0_0 .net "A", 7 0, L_0x12d2ea0; alias, 1 drivers +v0x11418b0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1141970_0 .net *"_s0", 0 0, L_0x12d3230; 1 drivers +v0x1141a30_0 .net *"_s12", 0 0, L_0x12d3bf0; 1 drivers +v0x1141b10_0 .net *"_s16", 0 0, L_0x12d3f50; 1 drivers +v0x1141c40_0 .net *"_s20", 0 0, L_0x12d4320; 1 drivers +v0x1141d20_0 .net *"_s24", 0 0, L_0x12d4650; 1 drivers +v0x1141e00_0 .net *"_s28", 0 0, L_0x12d45e0; 1 drivers +v0x1141ee0_0 .net *"_s4", 0 0, L_0x12d35d0; 1 drivers +v0x1142050_0 .net *"_s8", 0 0, L_0x12d38e0; 1 drivers +v0x1142130_0 .net "out", 7 0, L_0x12d4960; alias, 1 drivers +L_0x12d3340 .part L_0x12d2ea0, 0, 1; +L_0x12d3530 .part v0x12010b0_0, 0, 1; +L_0x12d3690 .part L_0x12d2ea0, 1, 1; +L_0x12d37f0 .part v0x12010b0_0, 1, 1; +L_0x12d39a0 .part L_0x12d2ea0, 2, 1; +L_0x12d3b00 .part v0x12010b0_0, 2, 1; +L_0x12d3cb0 .part L_0x12d2ea0, 3, 1; +L_0x12d3e10 .part v0x12010b0_0, 3, 1; +L_0x12d4010 .part L_0x12d2ea0, 4, 1; +L_0x12d4280 .part v0x12010b0_0, 4, 1; +L_0x12d4390 .part L_0x12d2ea0, 5, 1; +L_0x12d44f0 .part v0x12010b0_0, 5, 1; +L_0x12d4710 .part L_0x12d2ea0, 6, 1; +L_0x12d4870 .part v0x12010b0_0, 6, 1; +LS_0x12d4960_0_0 .concat8 [ 1 1 1 1], L_0x12d3230, L_0x12d35d0, L_0x12d38e0, L_0x12d3bf0; +LS_0x12d4960_0_4 .concat8 [ 1 1 1 1], L_0x12d3f50, L_0x12d4320, L_0x12d4650, L_0x12d45e0; +L_0x12d4960 .concat8 [ 4 4 0 0], LS_0x12d4960_0_0, LS_0x12d4960_0_4; +L_0x12d4d20 .part L_0x12d2ea0, 7, 1; +L_0x12d4f10 .part v0x12010b0_0, 7, 1; +S_0x113f2b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x113f4c0 .param/l "i" 0 4 54, +C4<00>; +L_0x12d3230/d .functor AND 1, L_0x12d3340, L_0x12d3530, C4<1>, C4<1>; +L_0x12d3230 .delay 1 (30000,30000,30000) L_0x12d3230/d; +v0x113f5a0_0 .net *"_s0", 0 0, L_0x12d3340; 1 drivers +v0x113f680_0 .net *"_s1", 0 0, L_0x12d3530; 1 drivers +S_0x113f760 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x113f970 .param/l "i" 0 4 54, +C4<01>; +L_0x12d35d0/d .functor AND 1, L_0x12d3690, L_0x12d37f0, C4<1>, C4<1>; +L_0x12d35d0 .delay 1 (30000,30000,30000) L_0x12d35d0/d; +v0x113fa30_0 .net *"_s0", 0 0, L_0x12d3690; 1 drivers +v0x113fb10_0 .net *"_s1", 0 0, L_0x12d37f0; 1 drivers +S_0x113fbf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x113fe30 .param/l "i" 0 4 54, +C4<010>; +L_0x12d38e0/d .functor AND 1, L_0x12d39a0, L_0x12d3b00, C4<1>, C4<1>; +L_0x12d38e0 .delay 1 (30000,30000,30000) L_0x12d38e0/d; +v0x113fed0_0 .net *"_s0", 0 0, L_0x12d39a0; 1 drivers +v0x113ffb0_0 .net *"_s1", 0 0, L_0x12d3b00; 1 drivers +S_0x1140090 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x11402a0 .param/l "i" 0 4 54, +C4<011>; +L_0x12d3bf0/d .functor AND 1, L_0x12d3cb0, L_0x12d3e10, C4<1>, C4<1>; +L_0x12d3bf0 .delay 1 (30000,30000,30000) L_0x12d3bf0/d; +v0x1140360_0 .net *"_s0", 0 0, L_0x12d3cb0; 1 drivers +v0x1140440_0 .net *"_s1", 0 0, L_0x12d3e10; 1 drivers +S_0x1140520 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x1140780 .param/l "i" 0 4 54, +C4<0100>; +L_0x12d3f50/d .functor AND 1, L_0x12d4010, L_0x12d4280, C4<1>, C4<1>; +L_0x12d3f50 .delay 1 (30000,30000,30000) L_0x12d3f50/d; +v0x1140840_0 .net *"_s0", 0 0, L_0x12d4010; 1 drivers +v0x1140920_0 .net *"_s1", 0 0, L_0x12d4280; 1 drivers +S_0x1140a00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x1140c10 .param/l "i" 0 4 54, +C4<0101>; +L_0x12d4320/d .functor AND 1, L_0x12d4390, L_0x12d44f0, C4<1>, C4<1>; +L_0x12d4320 .delay 1 (30000,30000,30000) L_0x12d4320/d; +v0x1140cd0_0 .net *"_s0", 0 0, L_0x12d4390; 1 drivers +v0x1140db0_0 .net *"_s1", 0 0, L_0x12d44f0; 1 drivers +S_0x1140e90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x11410a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12d4650/d .functor AND 1, L_0x12d4710, L_0x12d4870, C4<1>, C4<1>; +L_0x12d4650 .delay 1 (30000,30000,30000) L_0x12d4650/d; +v0x1141160_0 .net *"_s0", 0 0, L_0x12d4710; 1 drivers +v0x1141240_0 .net *"_s1", 0 0, L_0x12d4870; 1 drivers +S_0x1141320 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x113f070; + .timescale -9 -12; +P_0x1141530 .param/l "i" 0 4 54, +C4<0111>; +L_0x12d45e0/d .functor AND 1, L_0x12d4d20, L_0x12d4f10, C4<1>, C4<1>; +L_0x12d45e0 .delay 1 (30000,30000,30000) L_0x12d45e0/d; +v0x11415f0_0 .net *"_s0", 0 0, L_0x12d4d20; 1 drivers +v0x11416d0_0 .net *"_s1", 0 0, L_0x12d4f10; 1 drivers +S_0x1142290 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x113ee20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e43140/d .functor OR 1, L_0x1e43200, L_0x1e433b0, C4<0>, C4<0>; -L_0x1e43140 .delay 1 (30000,30000,30000) L_0x1e43140/d; -v0x1cb1160_0 .net *"_s10", 0 0, L_0x1e43200; 1 drivers -v0x1cb1240_0 .net *"_s12", 0 0, L_0x1e433b0; 1 drivers -v0x1cb1320_0 .net "in", 7 0, L_0x1e41140; alias, 1 drivers -v0x1cb13f0_0 .net "ors", 1 0, L_0x1e42f60; 1 drivers -v0x1cb14b0_0 .net "out", 0 0, L_0x1e43140; alias, 1 drivers -L_0x1e42330 .part L_0x1e41140, 0, 4; -L_0x1e42f60 .concat8 [ 1 1 0 0], L_0x1e42020, L_0x1e42c50; -L_0x1e430a0 .part L_0x1e41140, 4, 4; -L_0x1e43200 .part L_0x1e42f60, 0, 1; -L_0x1e433b0 .part L_0x1e42f60, 1, 1; -S_0x1caf7d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1caf610; +L_0x12d6850/d .functor OR 1, L_0x12d6910, L_0x12d6ac0, C4<0>, C4<0>; +L_0x12d6850 .delay 1 (30000,30000,30000) L_0x12d6850/d; +v0x1143de0_0 .net *"_s10", 0 0, L_0x12d6910; 1 drivers +v0x1143ec0_0 .net *"_s12", 0 0, L_0x12d6ac0; 1 drivers +v0x1143fa0_0 .net "in", 7 0, L_0x12d4960; alias, 1 drivers +v0x1144070_0 .net "ors", 1 0, L_0x12d6670; 1 drivers +v0x1144130_0 .net "out", 0 0, L_0x12d6850; alias, 1 drivers +L_0x12d5a40 .part L_0x12d4960, 0, 4; +L_0x12d6670 .concat8 [ 1 1 0 0], L_0x12d5730, L_0x12d6360; +L_0x12d67b0 .part L_0x12d4960, 4, 4; +L_0x12d6910 .part L_0x12d6670, 0, 1; +L_0x12d6ac0 .part L_0x12d6670, 1, 1; +S_0x1142450 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1142290; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e417e0/d .functor OR 1, L_0x1e418a0, L_0x1e41a00, C4<0>, C4<0>; -L_0x1e417e0 .delay 1 (30000,30000,30000) L_0x1e417e0/d; -L_0x1e41c30/d .functor OR 1, L_0x1e41d40, L_0x1e41ea0, C4<0>, C4<0>; -L_0x1e41c30 .delay 1 (30000,30000,30000) L_0x1e41c30/d; -L_0x1e42020/d .functor OR 1, L_0x1e42090, L_0x1e42240, C4<0>, C4<0>; -L_0x1e42020 .delay 1 (30000,30000,30000) L_0x1e42020/d; -v0x1cafa20_0 .net *"_s0", 0 0, L_0x1e417e0; 1 drivers -v0x1cafb20_0 .net *"_s10", 0 0, L_0x1e41d40; 1 drivers -v0x1cafc00_0 .net *"_s12", 0 0, L_0x1e41ea0; 1 drivers -v0x1cafcc0_0 .net *"_s14", 0 0, L_0x1e42090; 1 drivers -v0x1cafda0_0 .net *"_s16", 0 0, L_0x1e42240; 1 drivers -v0x1cafed0_0 .net *"_s3", 0 0, L_0x1e418a0; 1 drivers -v0x1caffb0_0 .net *"_s5", 0 0, L_0x1e41a00; 1 drivers -v0x1cb0090_0 .net *"_s6", 0 0, L_0x1e41c30; 1 drivers -v0x1cb0170_0 .net "in", 3 0, L_0x1e42330; 1 drivers -v0x1cb02e0_0 .net "ors", 1 0, L_0x1e41b40; 1 drivers -v0x1cb03c0_0 .net "out", 0 0, L_0x1e42020; 1 drivers -L_0x1e418a0 .part L_0x1e42330, 0, 1; -L_0x1e41a00 .part L_0x1e42330, 1, 1; -L_0x1e41b40 .concat8 [ 1 1 0 0], L_0x1e417e0, L_0x1e41c30; -L_0x1e41d40 .part L_0x1e42330, 2, 1; -L_0x1e41ea0 .part L_0x1e42330, 3, 1; -L_0x1e42090 .part L_0x1e41b40, 0, 1; -L_0x1e42240 .part L_0x1e41b40, 1, 1; -S_0x1cb04e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1caf610; +L_0x12c0ff0/d .functor OR 1, L_0x12d4fb0, L_0x12d5110, C4<0>, C4<0>; +L_0x12c0ff0 .delay 1 (30000,30000,30000) L_0x12c0ff0/d; +L_0x12d5340/d .functor OR 1, L_0x12d5450, L_0x12d55b0, C4<0>, C4<0>; +L_0x12d5340 .delay 1 (30000,30000,30000) L_0x12d5340/d; +L_0x12d5730/d .functor OR 1, L_0x12d57a0, L_0x12d5950, C4<0>, C4<0>; +L_0x12d5730 .delay 1 (30000,30000,30000) L_0x12d5730/d; +v0x11426a0_0 .net *"_s0", 0 0, L_0x12c0ff0; 1 drivers +v0x11427a0_0 .net *"_s10", 0 0, L_0x12d5450; 1 drivers +v0x1142880_0 .net *"_s12", 0 0, L_0x12d55b0; 1 drivers +v0x1142940_0 .net *"_s14", 0 0, L_0x12d57a0; 1 drivers +v0x1142a20_0 .net *"_s16", 0 0, L_0x12d5950; 1 drivers +v0x1142b50_0 .net *"_s3", 0 0, L_0x12d4fb0; 1 drivers +v0x1142c30_0 .net *"_s5", 0 0, L_0x12d5110; 1 drivers +v0x1142d10_0 .net *"_s6", 0 0, L_0x12d5340; 1 drivers +v0x1142df0_0 .net "in", 3 0, L_0x12d5a40; 1 drivers +v0x1142f60_0 .net "ors", 1 0, L_0x12d5250; 1 drivers +v0x1143040_0 .net "out", 0 0, L_0x12d5730; 1 drivers +L_0x12d4fb0 .part L_0x12d5a40, 0, 1; +L_0x12d5110 .part L_0x12d5a40, 1, 1; +L_0x12d5250 .concat8 [ 1 1 0 0], L_0x12c0ff0, L_0x12d5340; +L_0x12d5450 .part L_0x12d5a40, 2, 1; +L_0x12d55b0 .part L_0x12d5a40, 3, 1; +L_0x12d57a0 .part L_0x12d5250, 0, 1; +L_0x12d5950 .part L_0x12d5250, 1, 1; +S_0x1143160 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1142290; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e42460/d .functor OR 1, L_0x1e424d0, L_0x1e42630, C4<0>, C4<0>; -L_0x1e42460 .delay 1 (30000,30000,30000) L_0x1e42460/d; -L_0x1e42860/d .functor OR 1, L_0x1e42970, L_0x1e42ad0, C4<0>, C4<0>; -L_0x1e42860 .delay 1 (30000,30000,30000) L_0x1e42860/d; -L_0x1e42c50/d .functor OR 1, L_0x1e42cc0, L_0x1e42e70, C4<0>, C4<0>; -L_0x1e42c50 .delay 1 (30000,30000,30000) L_0x1e42c50/d; -v0x1cb06a0_0 .net *"_s0", 0 0, L_0x1e42460; 1 drivers -v0x1cb07a0_0 .net *"_s10", 0 0, L_0x1e42970; 1 drivers -v0x1cb0880_0 .net *"_s12", 0 0, L_0x1e42ad0; 1 drivers -v0x1cb0940_0 .net *"_s14", 0 0, L_0x1e42cc0; 1 drivers -v0x1cb0a20_0 .net *"_s16", 0 0, L_0x1e42e70; 1 drivers -v0x1cb0b50_0 .net *"_s3", 0 0, L_0x1e424d0; 1 drivers -v0x1cb0c30_0 .net *"_s5", 0 0, L_0x1e42630; 1 drivers -v0x1cb0d10_0 .net *"_s6", 0 0, L_0x1e42860; 1 drivers -v0x1cb0df0_0 .net "in", 3 0, L_0x1e430a0; 1 drivers -v0x1cb0f60_0 .net "ors", 1 0, L_0x1e42770; 1 drivers -v0x1cb1040_0 .net "out", 0 0, L_0x1e42c50; 1 drivers -L_0x1e424d0 .part L_0x1e430a0, 0, 1; -L_0x1e42630 .part L_0x1e430a0, 1, 1; -L_0x1e42770 .concat8 [ 1 1 0 0], L_0x1e42460, L_0x1e42860; -L_0x1e42970 .part L_0x1e430a0, 2, 1; -L_0x1e42ad0 .part L_0x1e430a0, 3, 1; -L_0x1e42cc0 .part L_0x1e42770, 0, 1; -L_0x1e42e70 .part L_0x1e42770, 1, 1; -S_0x1cb1950 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ca52d0; +L_0x12d5b70/d .functor OR 1, L_0x12d5be0, L_0x12d5d40, C4<0>, C4<0>; +L_0x12d5b70 .delay 1 (30000,30000,30000) L_0x12d5b70/d; +L_0x12d5f70/d .functor OR 1, L_0x12d6080, L_0x12d61e0, C4<0>, C4<0>; +L_0x12d5f70 .delay 1 (30000,30000,30000) L_0x12d5f70/d; +L_0x12d6360/d .functor OR 1, L_0x12d63d0, L_0x12d6580, C4<0>, C4<0>; +L_0x12d6360 .delay 1 (30000,30000,30000) L_0x12d6360/d; +v0x1143320_0 .net *"_s0", 0 0, L_0x12d5b70; 1 drivers +v0x1143420_0 .net *"_s10", 0 0, L_0x12d6080; 1 drivers +v0x1143500_0 .net *"_s12", 0 0, L_0x12d61e0; 1 drivers +v0x11435c0_0 .net *"_s14", 0 0, L_0x12d63d0; 1 drivers +v0x11436a0_0 .net *"_s16", 0 0, L_0x12d6580; 1 drivers +v0x11437d0_0 .net *"_s3", 0 0, L_0x12d5be0; 1 drivers +v0x11438b0_0 .net *"_s5", 0 0, L_0x12d5d40; 1 drivers +v0x1143990_0 .net *"_s6", 0 0, L_0x12d5f70; 1 drivers +v0x1143a70_0 .net "in", 3 0, L_0x12d67b0; 1 drivers +v0x1143be0_0 .net "ors", 1 0, L_0x12d5e80; 1 drivers +v0x1143cc0_0 .net "out", 0 0, L_0x12d6360; 1 drivers +L_0x12d5be0 .part L_0x12d67b0, 0, 1; +L_0x12d5d40 .part L_0x12d67b0, 1, 1; +L_0x12d5e80 .concat8 [ 1 1 0 0], L_0x12d5b70, L_0x12d5f70; +L_0x12d6080 .part L_0x12d67b0, 2, 1; +L_0x12d61e0 .part L_0x12d67b0, 3, 1; +L_0x12d63d0 .part L_0x12d5e80, 0, 1; +L_0x12d6580 .part L_0x12d5e80, 1, 1; +S_0x11445d0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1137f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -11788,80 +11798,80 @@ S_0x1cb1950 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ca52d0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e3e910/d .functor XNOR 1, L_0x1da93a0, L_0x1da9500, C4<0>, C4<0>; -L_0x1e3e910 .delay 1 (20000,20000,20000) L_0x1e3e910/d; -L_0x1e3eb80/d .functor AND 1, L_0x1da93a0, L_0x1e3d850, C4<1>, C4<1>; -L_0x1e3eb80 .delay 1 (30000,30000,30000) L_0x1e3eb80/d; -L_0x1e3ebf0/d .functor AND 1, L_0x1e3e910, L_0x1da95a0, C4<1>, C4<1>; -L_0x1e3ebf0 .delay 1 (30000,30000,30000) L_0x1e3ebf0/d; -L_0x1e3ed50/d .functor OR 1, L_0x1e3ebf0, L_0x1e3eb80, C4<0>, C4<0>; -L_0x1e3ed50 .delay 1 (30000,30000,30000) L_0x1e3ed50/d; -v0x1cb1c00_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers -v0x1cb1cf0_0 .net "a_", 0 0, L_0x1e3d790; alias, 1 drivers -v0x1cb1db0_0 .net "b", 0 0, L_0x1da9500; alias, 1 drivers -v0x1cb1ea0_0 .net "b_", 0 0, L_0x1e3d850; alias, 1 drivers -v0x1cb1f40_0 .net "carryin", 0 0, L_0x1da95a0; alias, 1 drivers -v0x1cb2080_0 .net "eq", 0 0, L_0x1e3e910; 1 drivers -v0x1cb2120_0 .net "lt", 0 0, L_0x1e3eb80; 1 drivers -v0x1cb21e0_0 .net "out", 0 0, L_0x1e3ed50; 1 drivers -v0x1cb22a0_0 .net "w0", 0 0, L_0x1e3ebf0; 1 drivers -S_0x1cb24f0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1ca52d0; +L_0x12d2210/d .functor XNOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; +L_0x12d2210 .delay 1 (20000,20000,20000) L_0x12d2210/d; +L_0x12d2480/d .functor AND 1, L_0x123cb70, L_0x12d1100, C4<1>, C4<1>; +L_0x12d2480 .delay 1 (30000,30000,30000) L_0x12d2480/d; +L_0x12d24f0/d .functor AND 1, L_0x12d2210, L_0x123cd70, C4<1>, C4<1>; +L_0x12d24f0 .delay 1 (30000,30000,30000) L_0x12d24f0/d; +L_0x12d2650/d .functor OR 1, L_0x12d24f0, L_0x12d2480, C4<0>, C4<0>; +L_0x12d2650 .delay 1 (30000,30000,30000) L_0x12d2650/d; +v0x1144880_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers +v0x1144970_0 .net "a_", 0 0, L_0x12d0ff0; alias, 1 drivers +v0x1144a30_0 .net "b", 0 0, L_0x123ccd0; alias, 1 drivers +v0x1144b20_0 .net "b_", 0 0, L_0x12d1100; alias, 1 drivers +v0x1144bc0_0 .net "carryin", 0 0, L_0x123cd70; alias, 1 drivers +v0x1144d00_0 .net "eq", 0 0, L_0x12d2210; 1 drivers +v0x1144dc0_0 .net "lt", 0 0, L_0x12d2480; 1 drivers +v0x1144e80_0 .net "out", 0 0, L_0x12d2650; 1 drivers +v0x1144f40_0 .net "w0", 0 0, L_0x12d24f0; 1 drivers +S_0x1145190 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1137f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e3e6f0/d .functor OR 1, L_0x1e3e240, L_0x1cb3780, C4<0>, C4<0>; -L_0x1e3e6f0 .delay 1 (30000,30000,30000) L_0x1e3e6f0/d; -v0x1cb3310_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers -v0x1cb3460_0 .net "b", 0 0, L_0x1e3d850; alias, 1 drivers -v0x1cb3520_0 .net "c1", 0 0, L_0x1e3e240; 1 drivers -v0x1cb35c0_0 .net "c2", 0 0, L_0x1cb3780; 1 drivers -v0x1cb3690_0 .net "carryin", 0 0, L_0x1da95a0; alias, 1 drivers -v0x1cb3810_0 .net "carryout", 0 0, L_0x1e3e6f0; 1 drivers -v0x1cb38b0_0 .net "s1", 0 0, L_0x1e3e180; 1 drivers -v0x1cb3950_0 .net "sum", 0 0, L_0x1e3e3a0; 1 drivers -S_0x1cb2740 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cb24f0; +L_0x12d1ff0/d .functor OR 1, L_0x12d1af0, L_0x11463f0, C4<0>, C4<0>; +L_0x12d1ff0 .delay 1 (30000,30000,30000) L_0x12d1ff0/d; +v0x1145f80_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers +v0x11460d0_0 .net "b", 0 0, L_0x12d1100; alias, 1 drivers +v0x1146190_0 .net "c1", 0 0, L_0x12d1af0; 1 drivers +v0x1146230_0 .net "c2", 0 0, L_0x11463f0; 1 drivers +v0x1146300_0 .net "carryin", 0 0, L_0x123cd70; alias, 1 drivers +v0x1146480_0 .net "carryout", 0 0, L_0x12d1ff0; 1 drivers +v0x1146520_0 .net "s1", 0 0, L_0x12d1a30; 1 drivers +v0x11465c0_0 .net "sum", 0 0, L_0x12d1c50; 1 drivers +S_0x11453e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1145190; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e3e180/d .functor XOR 1, L_0x1da93a0, L_0x1e3d850, C4<0>, C4<0>; -L_0x1e3e180 .delay 1 (30000,30000,30000) L_0x1e3e180/d; -L_0x1e3e240/d .functor AND 1, L_0x1da93a0, L_0x1e3d850, C4<1>, C4<1>; -L_0x1e3e240 .delay 1 (30000,30000,30000) L_0x1e3e240/d; -v0x1cb29a0_0 .net "a", 0 0, L_0x1da93a0; alias, 1 drivers -v0x1cb2a60_0 .net "b", 0 0, L_0x1e3d850; alias, 1 drivers -v0x1cb2b20_0 .net "carryout", 0 0, L_0x1e3e240; alias, 1 drivers -v0x1cb2bf0_0 .net "sum", 0 0, L_0x1e3e180; alias, 1 drivers -S_0x1cb2d20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cb24f0; +L_0x12d1a30/d .functor XOR 1, L_0x123cb70, L_0x12d1100, C4<0>, C4<0>; +L_0x12d1a30 .delay 1 (30000,30000,30000) L_0x12d1a30/d; +L_0x12d1af0/d .functor AND 1, L_0x123cb70, L_0x12d1100, C4<1>, C4<1>; +L_0x12d1af0 .delay 1 (30000,30000,30000) L_0x12d1af0/d; +v0x1145640_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers +v0x1145700_0 .net "b", 0 0, L_0x12d1100; alias, 1 drivers +v0x11457c0_0 .net "carryout", 0 0, L_0x12d1af0; alias, 1 drivers +v0x1145860_0 .net "sum", 0 0, L_0x12d1a30; alias, 1 drivers +S_0x1145990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1145190; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e3e3a0/d .functor XOR 1, L_0x1e3e180, L_0x1da95a0, C4<0>, C4<0>; -L_0x1e3e3a0 .delay 1 (30000,30000,30000) L_0x1e3e3a0/d; -L_0x1cb3780/d .functor AND 1, L_0x1e3e180, L_0x1da95a0, C4<1>, C4<1>; -L_0x1cb3780 .delay 1 (30000,30000,30000) L_0x1cb3780/d; -v0x1cb2f80_0 .net "a", 0 0, L_0x1e3e180; alias, 1 drivers -v0x1cb3050_0 .net "b", 0 0, L_0x1da95a0; alias, 1 drivers -v0x1cb30f0_0 .net "carryout", 0 0, L_0x1cb3780; alias, 1 drivers -v0x1cb31c0_0 .net "sum", 0 0, L_0x1e3e3a0; alias, 1 drivers -S_0x1cb4d70 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1ca5000; - .timescale -9 -12; -L_0x7f72592db7b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1da9440/d .functor OR 1, L_0x7f72592db7b8, L_0x7f72592db800, C4<0>, C4<0>; -L_0x1da9440 .delay 1 (30000,30000,30000) L_0x1da9440/d; -v0x1cb4f60_0 .net/2u *"_s0", 0 0, L_0x7f72592db7b8; 1 drivers -v0x1cb5040_0 .net/2u *"_s2", 0 0, L_0x7f72592db800; 1 drivers -S_0x1cb5120 .scope generate, "alu_slices[22]" "alu_slices[22]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1cb5330 .param/l "i" 0 3 37, +C4<010110>; -S_0x1cb53f0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cb5120; +L_0x12d1c50/d .functor XOR 1, L_0x12d1a30, L_0x123cd70, C4<0>, C4<0>; +L_0x12d1c50 .delay 1 (30000,30000,30000) L_0x12d1c50/d; +L_0x11463f0/d .functor AND 1, L_0x12d1a30, L_0x123cd70, C4<1>, C4<1>; +L_0x11463f0 .delay 1 (30000,30000,30000) L_0x11463f0/d; +v0x1145bf0_0 .net "a", 0 0, L_0x12d1a30; alias, 1 drivers +v0x1145cc0_0 .net "b", 0 0, L_0x123cd70; alias, 1 drivers +v0x1145d60_0 .net "carryout", 0 0, L_0x11463f0; alias, 1 drivers +v0x1145e30_0 .net "sum", 0 0, L_0x12d1c50; alias, 1 drivers +S_0x11479e0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1137c80; + .timescale -9 -12; +L_0x2b0ab3d067b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x123cc10/d .functor OR 1, L_0x2b0ab3d067b8, L_0x2b0ab3d06800, C4<0>, C4<0>; +L_0x123cc10 .delay 1 (30000,30000,30000) L_0x123cc10/d; +v0x1147bd0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d067b8; 1 drivers +v0x1147cb0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06800; 1 drivers +S_0x1147d90 .scope generate, "alu_slices[22]" "alu_slices[22]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1147fa0 .param/l "i" 0 3 41, +C4<010110>; +S_0x1148060 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1147d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -11870,445 +11880,445 @@ S_0x1cb53f0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cb5120; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e3d590/d .functor NOT 1, L_0x1e52ca0, C4<0>, C4<0>, C4<0>; -L_0x1e3d590 .delay 1 (10000,10000,10000) L_0x1e3d590/d; -L_0x1e49450/d .functor NOT 1, L_0x1e52e00, C4<0>, C4<0>, C4<0>; -L_0x1e49450 .delay 1 (10000,10000,10000) L_0x1e49450/d; -L_0x1e4a450/d .functor XOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; -L_0x1e4a450 .delay 1 (30000,30000,30000) L_0x1e4a450/d; -L_0x7f72592db848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e4ab00/d .functor OR 1, L_0x7f72592db848, L_0x7f72592db890, C4<0>, C4<0>; -L_0x1e4ab00 .delay 1 (30000,30000,30000) L_0x1e4ab00/d; -L_0x1e4ad00/d .functor AND 1, L_0x1e52ca0, L_0x1e52e00, C4<1>, C4<1>; -L_0x1e4ad00 .delay 1 (30000,30000,30000) L_0x1e4ad00/d; -L_0x1e4adc0/d .functor NAND 1, L_0x1e52ca0, L_0x1e52e00, C4<1>, C4<1>; -L_0x1e4adc0 .delay 1 (20000,20000,20000) L_0x1e4adc0/d; -L_0x1e4af20/d .functor XOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; -L_0x1e4af20 .delay 1 (20000,20000,20000) L_0x1e4af20/d; -L_0x1e4b3d0/d .functor OR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; -L_0x1e4b3d0 .delay 1 (30000,30000,30000) L_0x1e4b3d0/d; -L_0x1e52ba0/d .functor NOT 1, L_0x1e4ed40, C4<0>, C4<0>, C4<0>; -L_0x1e52ba0 .delay 1 (10000,10000,10000) L_0x1e52ba0/d; -v0x1cc3b20_0 .net "A", 0 0, L_0x1e52ca0; 1 drivers -v0x1cc3be0_0 .net "A_", 0 0, L_0x1e3d590; 1 drivers -v0x1cc3ca0_0 .net "B", 0 0, L_0x1e52e00; 1 drivers -v0x1cc3d70_0 .net "B_", 0 0, L_0x1e49450; 1 drivers -v0x1cc3e10_0 .net *"_s12", 0 0, L_0x1e4ab00; 1 drivers -v0x1cc3f00_0 .net/2s *"_s14", 0 0, L_0x7f72592db848; 1 drivers -v0x1cc3fc0_0 .net/2s *"_s16", 0 0, L_0x7f72592db890; 1 drivers -v0x1cc40a0_0 .net *"_s18", 0 0, L_0x1e4ad00; 1 drivers -v0x1cc4180_0 .net *"_s20", 0 0, L_0x1e4adc0; 1 drivers -v0x1cc42f0_0 .net *"_s22", 0 0, L_0x1e4af20; 1 drivers -v0x1cc43d0_0 .net *"_s24", 0 0, L_0x1e4b3d0; 1 drivers -o0x7f72593287a8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1cc44b0_0 name=_s30 -o0x7f72593287d8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1cc4590_0 name=_s32 -v0x1cc4670_0 .net *"_s8", 0 0, L_0x1e4a450; 1 drivers -v0x1cc4750_0 .net "carryin", 0 0, L_0x1e49230; 1 drivers -v0x1cc47f0_0 .net "carryout", 0 0, L_0x1e52840; 1 drivers -v0x1cc4890_0 .net "carryouts", 7 0, L_0x1ec10d0; 1 drivers -v0x1cc4a40_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cc4ae0_0 .net "result", 0 0, L_0x1e4ed40; 1 drivers -v0x1cc4bd0_0 .net "results", 7 0, L_0x1e4b1a0; 1 drivers -v0x1cc4ce0_0 .net "zero", 0 0, L_0x1e52ba0; 1 drivers -LS_0x1e4b1a0_0_0 .concat8 [ 1 1 1 1], L_0x1e49970, L_0x1e49fa0, L_0x1e4a450, L_0x1e4ab00; -LS_0x1e4b1a0_0_4 .concat8 [ 1 1 1 1], L_0x1e4ad00, L_0x1e4adc0, L_0x1e4af20, L_0x1e4b3d0; -L_0x1e4b1a0 .concat8 [ 4 4 0 0], LS_0x1e4b1a0_0_0, LS_0x1e4b1a0_0_4; -LS_0x1ec10d0_0_0 .concat [ 1 1 1 1], L_0x1e49c20, L_0x1e4a2f0, o0x7f72593287a8, L_0x1e4a950; -LS_0x1ec10d0_0_4 .concat [ 4 0 0 0], o0x7f72593287d8; -L_0x1ec10d0 .concat [ 4 4 0 0], LS_0x1ec10d0_0_0, LS_0x1ec10d0_0_4; -S_0x1cb5670 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cb53f0; +L_0x12d0e90/d .functor NOT 1, L_0x12e6510, C4<0>, C4<0>, C4<0>; +L_0x12d0e90 .delay 1 (10000,10000,10000) L_0x12d0e90/d; +L_0x12dcc90/d .functor NOT 1, L_0x12e6670, C4<0>, C4<0>, C4<0>; +L_0x12dcc90 .delay 1 (10000,10000,10000) L_0x12dcc90/d; +L_0x12ddc90/d .functor XOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; +L_0x12ddc90 .delay 1 (30000,30000,30000) L_0x12ddc90/d; +L_0x2b0ab3d06848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12de340/d .functor OR 1, L_0x2b0ab3d06848, L_0x2b0ab3d06890, C4<0>, C4<0>; +L_0x12de340 .delay 1 (30000,30000,30000) L_0x12de340/d; +L_0x12de540/d .functor AND 1, L_0x12e6510, L_0x12e6670, C4<1>, C4<1>; +L_0x12de540 .delay 1 (30000,30000,30000) L_0x12de540/d; +L_0x12de600/d .functor NAND 1, L_0x12e6510, L_0x12e6670, C4<1>, C4<1>; +L_0x12de600 .delay 1 (20000,20000,20000) L_0x12de600/d; +L_0x12de760/d .functor XOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; +L_0x12de760 .delay 1 (20000,20000,20000) L_0x12de760/d; +L_0x12dec10/d .functor OR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; +L_0x12dec10 .delay 1 (30000,30000,30000) L_0x12dec10/d; +L_0x12e6410/d .functor NOT 1, L_0x12e25b0, C4<0>, C4<0>, C4<0>; +L_0x12e6410 .delay 1 (10000,10000,10000) L_0x12e6410/d; +v0x1156790_0 .net "A", 0 0, L_0x12e6510; 1 drivers +v0x1156850_0 .net "A_", 0 0, L_0x12d0e90; 1 drivers +v0x1156910_0 .net "B", 0 0, L_0x12e6670; 1 drivers +v0x11569e0_0 .net "B_", 0 0, L_0x12dcc90; 1 drivers +v0x1156a80_0 .net *"_s12", 0 0, L_0x12de340; 1 drivers +v0x1156b70_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06848; 1 drivers +v0x1156c30_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06890; 1 drivers +v0x1156d10_0 .net *"_s18", 0 0, L_0x12de540; 1 drivers +v0x1156df0_0 .net *"_s20", 0 0, L_0x12de600; 1 drivers +v0x1156f60_0 .net *"_s22", 0 0, L_0x12de760; 1 drivers +v0x1157040_0 .net *"_s24", 0 0, L_0x12dec10; 1 drivers +o0x2b0ab3cd97a8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1157120_0 name=_s30 +o0x2b0ab3cd97d8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1157200_0 name=_s32 +v0x11572e0_0 .net *"_s8", 0 0, L_0x12ddc90; 1 drivers +v0x11573c0_0 .net "carryin", 0 0, L_0x12dca20; 1 drivers +v0x1157460_0 .net "carryout", 0 0, L_0x12e60b0; 1 drivers +v0x1157500_0 .net "carryouts", 7 0, L_0x1355400; 1 drivers +v0x11576b0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1157750_0 .net "result", 0 0, L_0x12e25b0; 1 drivers +v0x1157840_0 .net "results", 7 0, L_0x12de9e0; 1 drivers +v0x1157950_0 .net "zero", 0 0, L_0x12e6410; 1 drivers +LS_0x12de9e0_0_0 .concat8 [ 1 1 1 1], L_0x12dd1b0, L_0x12dd7e0, L_0x12ddc90, L_0x12de340; +LS_0x12de9e0_0_4 .concat8 [ 1 1 1 1], L_0x12de540, L_0x12de600, L_0x12de760, L_0x12dec10; +L_0x12de9e0 .concat8 [ 4 4 0 0], LS_0x12de9e0_0_0, LS_0x12de9e0_0_4; +LS_0x1355400_0_0 .concat [ 1 1 1 1], L_0x12dd460, L_0x12ddb30, o0x2b0ab3cd97a8, L_0x12de190; +LS_0x1355400_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd97d8; +L_0x1355400 .concat [ 4 4 0 0], LS_0x1355400_0_0, LS_0x1355400_0_4; +S_0x11482e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1148060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e49c20/d .functor OR 1, L_0x1e49700, L_0x1e49ac0, C4<0>, C4<0>; -L_0x1e49c20 .delay 1 (30000,30000,30000) L_0x1e49c20/d; -v0x1cb64a0_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers -v0x1cb6560_0 .net "b", 0 0, L_0x1e52e00; alias, 1 drivers -v0x1cb6630_0 .net "c1", 0 0, L_0x1e49700; 1 drivers -v0x1cb6730_0 .net "c2", 0 0, L_0x1e49ac0; 1 drivers -v0x1cb6800_0 .net "carryin", 0 0, L_0x1e49230; alias, 1 drivers -v0x1cb68f0_0 .net "carryout", 0 0, L_0x1e49c20; 1 drivers -v0x1cb6990_0 .net "s1", 0 0, L_0x1e49640; 1 drivers -v0x1cb6a80_0 .net "sum", 0 0, L_0x1e49970; 1 drivers -S_0x1cb58e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cb5670; +L_0x12dd460/d .functor OR 1, L_0x12dcf40, L_0x12dd300, C4<0>, C4<0>; +L_0x12dd460 .delay 1 (30000,30000,30000) L_0x12dd460/d; +v0x1149110_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers +v0x11491d0_0 .net "b", 0 0, L_0x12e6670; alias, 1 drivers +v0x11492a0_0 .net "c1", 0 0, L_0x12dcf40; 1 drivers +v0x11493a0_0 .net "c2", 0 0, L_0x12dd300; 1 drivers +v0x1149470_0 .net "carryin", 0 0, L_0x12dca20; alias, 1 drivers +v0x1149560_0 .net "carryout", 0 0, L_0x12dd460; 1 drivers +v0x1149600_0 .net "s1", 0 0, L_0x12dce80; 1 drivers +v0x11496f0_0 .net "sum", 0 0, L_0x12dd1b0; 1 drivers +S_0x1148550 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11482e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e49640/d .functor XOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; -L_0x1e49640 .delay 1 (30000,30000,30000) L_0x1e49640/d; -L_0x1e49700/d .functor AND 1, L_0x1e52ca0, L_0x1e52e00, C4<1>, C4<1>; -L_0x1e49700 .delay 1 (30000,30000,30000) L_0x1e49700/d; -v0x1cb5b40_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers -v0x1cb5c20_0 .net "b", 0 0, L_0x1e52e00; alias, 1 drivers -v0x1cb5ce0_0 .net "carryout", 0 0, L_0x1e49700; alias, 1 drivers -v0x1cb5d80_0 .net "sum", 0 0, L_0x1e49640; alias, 1 drivers -S_0x1cb5ec0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cb5670; +L_0x12dce80/d .functor XOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; +L_0x12dce80 .delay 1 (30000,30000,30000) L_0x12dce80/d; +L_0x12dcf40/d .functor AND 1, L_0x12e6510, L_0x12e6670, C4<1>, C4<1>; +L_0x12dcf40 .delay 1 (30000,30000,30000) L_0x12dcf40/d; +v0x11487b0_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers +v0x1148890_0 .net "b", 0 0, L_0x12e6670; alias, 1 drivers +v0x1148950_0 .net "carryout", 0 0, L_0x12dcf40; alias, 1 drivers +v0x11489f0_0 .net "sum", 0 0, L_0x12dce80; alias, 1 drivers +S_0x1148b30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11482e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e49970/d .functor XOR 1, L_0x1e49640, L_0x1e49230, C4<0>, C4<0>; -L_0x1e49970 .delay 1 (30000,30000,30000) L_0x1e49970/d; -L_0x1e49ac0/d .functor AND 1, L_0x1e49640, L_0x1e49230, C4<1>, C4<1>; -L_0x1e49ac0 .delay 1 (30000,30000,30000) L_0x1e49ac0/d; -v0x1cb6120_0 .net "a", 0 0, L_0x1e49640; alias, 1 drivers -v0x1cb61c0_0 .net "b", 0 0, L_0x1e49230; alias, 1 drivers -v0x1cb6260_0 .net "carryout", 0 0, L_0x1e49ac0; alias, 1 drivers -v0x1cb6330_0 .net "sum", 0 0, L_0x1e49970; alias, 1 drivers -S_0x1cb6b50 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cb53f0; +L_0x12dd1b0/d .functor XOR 1, L_0x12dce80, L_0x12dca20, C4<0>, C4<0>; +L_0x12dd1b0 .delay 1 (30000,30000,30000) L_0x12dd1b0/d; +L_0x12dd300/d .functor AND 1, L_0x12dce80, L_0x12dca20, C4<1>, C4<1>; +L_0x12dd300 .delay 1 (30000,30000,30000) L_0x12dd300/d; +v0x1148d90_0 .net "a", 0 0, L_0x12dce80; alias, 1 drivers +v0x1148e30_0 .net "b", 0 0, L_0x12dca20; alias, 1 drivers +v0x1148ed0_0 .net "carryout", 0 0, L_0x12dd300; alias, 1 drivers +v0x1148fa0_0 .net "sum", 0 0, L_0x12dd1b0; alias, 1 drivers +S_0x11497c0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1148060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cbbf40_0 .net "ands", 7 0, L_0x1e50840; 1 drivers -v0x1cbc050_0 .net "in", 7 0, L_0x1ec10d0; alias, 1 drivers -v0x1cbc110_0 .net "out", 0 0, L_0x1e52840; alias, 1 drivers -v0x1cbc1e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cb6d70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cb6b50; +v0x114ebb0_0 .net "ands", 7 0, L_0x12e40b0; 1 drivers +v0x114ecc0_0 .net "in", 7 0, L_0x1355400; alias, 1 drivers +v0x114ed80_0 .net "out", 0 0, L_0x12e60b0; alias, 1 drivers +v0x114ee50_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11499e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11497c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cb94a0_0 .net "A", 7 0, L_0x1ec10d0; alias, 1 drivers -v0x1cb95a0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cb9660_0 .net *"_s0", 0 0, L_0x1e4f0a0; 1 drivers -v0x1cb9720_0 .net *"_s12", 0 0, L_0x1e4fa10; 1 drivers -v0x1cb9800_0 .net *"_s16", 0 0, L_0x1e4fdd0; 1 drivers -v0x1cb9930_0 .net *"_s20", 0 0, L_0x1e50110; 1 drivers -v0x1cb9a10_0 .net *"_s24", 0 0, L_0x1e50530; 1 drivers -v0x1cb9af0_0 .net *"_s28", 0 0, L_0x1e504c0; 1 drivers -v0x1cb9bd0_0 .net *"_s4", 0 0, L_0x1e4f3b0; 1 drivers -v0x1cb9d40_0 .net *"_s8", 0 0, L_0x1e4f700; 1 drivers -v0x1cb9e20_0 .net "out", 7 0, L_0x1e50840; alias, 1 drivers -L_0x1e4f160 .part L_0x1ec10d0, 0, 1; -L_0x1e4f2c0 .part v0x1d6daa0_0, 0, 1; -L_0x1e4f470 .part L_0x1ec10d0, 1, 1; -L_0x1e4f660 .part v0x1d6daa0_0, 1, 1; -L_0x1e4f7c0 .part L_0x1ec10d0, 2, 1; -L_0x1e4f920 .part v0x1d6daa0_0, 2, 1; -L_0x1e4fb30 .part L_0x1ec10d0, 3, 1; -L_0x1e4fc90 .part v0x1d6daa0_0, 3, 1; -L_0x1e4fec0 .part L_0x1ec10d0, 4, 1; -L_0x1e50020 .part v0x1d6daa0_0, 4, 1; -L_0x1e501b0 .part L_0x1ec10d0, 5, 1; -L_0x1e50420 .part v0x1d6daa0_0, 5, 1; -L_0x1e505f0 .part L_0x1ec10d0, 6, 1; -L_0x1e50750 .part v0x1d6daa0_0, 6, 1; -LS_0x1e50840_0_0 .concat8 [ 1 1 1 1], L_0x1e4f0a0, L_0x1e4f3b0, L_0x1e4f700, L_0x1e4fa10; -LS_0x1e50840_0_4 .concat8 [ 1 1 1 1], L_0x1e4fdd0, L_0x1e50110, L_0x1e50530, L_0x1e504c0; -L_0x1e50840 .concat8 [ 4 4 0 0], LS_0x1e50840_0_0, LS_0x1e50840_0_4; -L_0x1e50c00 .part L_0x1ec10d0, 7, 1; -L_0x1e50df0 .part v0x1d6daa0_0, 7, 1; -S_0x1cb6fd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb71e0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e4f0a0/d .functor AND 1, L_0x1e4f160, L_0x1e4f2c0, C4<1>, C4<1>; -L_0x1e4f0a0 .delay 1 (30000,30000,30000) L_0x1e4f0a0/d; -v0x1cb72c0_0 .net *"_s0", 0 0, L_0x1e4f160; 1 drivers -v0x1cb73a0_0 .net *"_s1", 0 0, L_0x1e4f2c0; 1 drivers -S_0x1cb7480 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb7690 .param/l "i" 0 4 54, +C4<01>; -L_0x1e4f3b0/d .functor AND 1, L_0x1e4f470, L_0x1e4f660, C4<1>, C4<1>; -L_0x1e4f3b0 .delay 1 (30000,30000,30000) L_0x1e4f3b0/d; -v0x1cb7750_0 .net *"_s0", 0 0, L_0x1e4f470; 1 drivers -v0x1cb7830_0 .net *"_s1", 0 0, L_0x1e4f660; 1 drivers -S_0x1cb7910 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb7b20 .param/l "i" 0 4 54, +C4<010>; -L_0x1e4f700/d .functor AND 1, L_0x1e4f7c0, L_0x1e4f920, C4<1>, C4<1>; -L_0x1e4f700 .delay 1 (30000,30000,30000) L_0x1e4f700/d; -v0x1cb7bc0_0 .net *"_s0", 0 0, L_0x1e4f7c0; 1 drivers -v0x1cb7ca0_0 .net *"_s1", 0 0, L_0x1e4f920; 1 drivers -S_0x1cb7d80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb7f90 .param/l "i" 0 4 54, +C4<011>; -L_0x1e4fa10/d .functor AND 1, L_0x1e4fb30, L_0x1e4fc90, C4<1>, C4<1>; -L_0x1e4fa10 .delay 1 (30000,30000,30000) L_0x1e4fa10/d; -v0x1cb8050_0 .net *"_s0", 0 0, L_0x1e4fb30; 1 drivers -v0x1cb8130_0 .net *"_s1", 0 0, L_0x1e4fc90; 1 drivers -S_0x1cb8210 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb8470 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e4fdd0/d .functor AND 1, L_0x1e4fec0, L_0x1e50020, C4<1>, C4<1>; -L_0x1e4fdd0 .delay 1 (30000,30000,30000) L_0x1e4fdd0/d; -v0x1cb8530_0 .net *"_s0", 0 0, L_0x1e4fec0; 1 drivers -v0x1cb8610_0 .net *"_s1", 0 0, L_0x1e50020; 1 drivers -S_0x1cb86f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb8900 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e50110/d .functor AND 1, L_0x1e501b0, L_0x1e50420, C4<1>, C4<1>; -L_0x1e50110 .delay 1 (30000,30000,30000) L_0x1e50110/d; -v0x1cb89c0_0 .net *"_s0", 0 0, L_0x1e501b0; 1 drivers -v0x1cb8aa0_0 .net *"_s1", 0 0, L_0x1e50420; 1 drivers -S_0x1cb8b80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb8d90 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e50530/d .functor AND 1, L_0x1e505f0, L_0x1e50750, C4<1>, C4<1>; -L_0x1e50530 .delay 1 (30000,30000,30000) L_0x1e50530/d; -v0x1cb8e50_0 .net *"_s0", 0 0, L_0x1e505f0; 1 drivers -v0x1cb8f30_0 .net *"_s1", 0 0, L_0x1e50750; 1 drivers -S_0x1cb9010 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cb6d70; - .timescale -9 -12; -P_0x1cb9220 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e504c0/d .functor AND 1, L_0x1e50c00, L_0x1e50df0, C4<1>, C4<1>; -L_0x1e504c0 .delay 1 (30000,30000,30000) L_0x1e504c0/d; -v0x1cb92e0_0 .net *"_s0", 0 0, L_0x1e50c00; 1 drivers -v0x1cb93c0_0 .net *"_s1", 0 0, L_0x1e50df0; 1 drivers -S_0x1cb9f80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cb6b50; +v0x114c110_0 .net "A", 7 0, L_0x1355400; alias, 1 drivers +v0x114c210_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x114c2d0_0 .net *"_s0", 0 0, L_0x12e2910; 1 drivers +v0x114c390_0 .net *"_s12", 0 0, L_0x12e32e0; 1 drivers +v0x114c470_0 .net *"_s16", 0 0, L_0x12e3640; 1 drivers +v0x114c5a0_0 .net *"_s20", 0 0, L_0x12e3980; 1 drivers +v0x114c680_0 .net *"_s24", 0 0, L_0x12e3da0; 1 drivers +v0x114c760_0 .net *"_s28", 0 0, L_0x12e3d30; 1 drivers +v0x114c840_0 .net *"_s4", 0 0, L_0x12e2c20; 1 drivers +v0x114c9b0_0 .net *"_s8", 0 0, L_0x12e2f70; 1 drivers +v0x114ca90_0 .net "out", 7 0, L_0x12e40b0; alias, 1 drivers +L_0x12e29d0 .part L_0x1355400, 0, 1; +L_0x12e2b30 .part v0x12010b0_0, 0, 1; +L_0x12e2ce0 .part L_0x1355400, 1, 1; +L_0x12e2ed0 .part v0x12010b0_0, 1, 1; +L_0x12e3090 .part L_0x1355400, 2, 1; +L_0x12e31f0 .part v0x12010b0_0, 2, 1; +L_0x12e33a0 .part L_0x1355400, 3, 1; +L_0x12e3500 .part v0x12010b0_0, 3, 1; +L_0x12e3730 .part L_0x1355400, 4, 1; +L_0x12e3890 .part v0x12010b0_0, 4, 1; +L_0x12e3a20 .part L_0x1355400, 5, 1; +L_0x12e3c90 .part v0x12010b0_0, 5, 1; +L_0x12e3e60 .part L_0x1355400, 6, 1; +L_0x12e3fc0 .part v0x12010b0_0, 6, 1; +LS_0x12e40b0_0_0 .concat8 [ 1 1 1 1], L_0x12e2910, L_0x12e2c20, L_0x12e2f70, L_0x12e32e0; +LS_0x12e40b0_0_4 .concat8 [ 1 1 1 1], L_0x12e3640, L_0x12e3980, L_0x12e3da0, L_0x12e3d30; +L_0x12e40b0 .concat8 [ 4 4 0 0], LS_0x12e40b0_0_0, LS_0x12e40b0_0_4; +L_0x12e4470 .part L_0x1355400, 7, 1; +L_0x12e4660 .part v0x12010b0_0, 7, 1; +S_0x1149c40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x1149e50 .param/l "i" 0 4 54, +C4<00>; +L_0x12e2910/d .functor AND 1, L_0x12e29d0, L_0x12e2b30, C4<1>, C4<1>; +L_0x12e2910 .delay 1 (30000,30000,30000) L_0x12e2910/d; +v0x1149f30_0 .net *"_s0", 0 0, L_0x12e29d0; 1 drivers +v0x114a010_0 .net *"_s1", 0 0, L_0x12e2b30; 1 drivers +S_0x114a0f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114a300 .param/l "i" 0 4 54, +C4<01>; +L_0x12e2c20/d .functor AND 1, L_0x12e2ce0, L_0x12e2ed0, C4<1>, C4<1>; +L_0x12e2c20 .delay 1 (30000,30000,30000) L_0x12e2c20/d; +v0x114a3c0_0 .net *"_s0", 0 0, L_0x12e2ce0; 1 drivers +v0x114a4a0_0 .net *"_s1", 0 0, L_0x12e2ed0; 1 drivers +S_0x114a580 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114a790 .param/l "i" 0 4 54, +C4<010>; +L_0x12e2f70/d .functor AND 1, L_0x12e3090, L_0x12e31f0, C4<1>, C4<1>; +L_0x12e2f70 .delay 1 (30000,30000,30000) L_0x12e2f70/d; +v0x114a830_0 .net *"_s0", 0 0, L_0x12e3090; 1 drivers +v0x114a910_0 .net *"_s1", 0 0, L_0x12e31f0; 1 drivers +S_0x114a9f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114ac00 .param/l "i" 0 4 54, +C4<011>; +L_0x12e32e0/d .functor AND 1, L_0x12e33a0, L_0x12e3500, C4<1>, C4<1>; +L_0x12e32e0 .delay 1 (30000,30000,30000) L_0x12e32e0/d; +v0x114acc0_0 .net *"_s0", 0 0, L_0x12e33a0; 1 drivers +v0x114ada0_0 .net *"_s1", 0 0, L_0x12e3500; 1 drivers +S_0x114ae80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114b0e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12e3640/d .functor AND 1, L_0x12e3730, L_0x12e3890, C4<1>, C4<1>; +L_0x12e3640 .delay 1 (30000,30000,30000) L_0x12e3640/d; +v0x114b1a0_0 .net *"_s0", 0 0, L_0x12e3730; 1 drivers +v0x114b280_0 .net *"_s1", 0 0, L_0x12e3890; 1 drivers +S_0x114b360 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114b570 .param/l "i" 0 4 54, +C4<0101>; +L_0x12e3980/d .functor AND 1, L_0x12e3a20, L_0x12e3c90, C4<1>, C4<1>; +L_0x12e3980 .delay 1 (30000,30000,30000) L_0x12e3980/d; +v0x114b630_0 .net *"_s0", 0 0, L_0x12e3a20; 1 drivers +v0x114b710_0 .net *"_s1", 0 0, L_0x12e3c90; 1 drivers +S_0x114b7f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114ba00 .param/l "i" 0 4 54, +C4<0110>; +L_0x12e3da0/d .functor AND 1, L_0x12e3e60, L_0x12e3fc0, C4<1>, C4<1>; +L_0x12e3da0 .delay 1 (30000,30000,30000) L_0x12e3da0/d; +v0x114bac0_0 .net *"_s0", 0 0, L_0x12e3e60; 1 drivers +v0x114bba0_0 .net *"_s1", 0 0, L_0x12e3fc0; 1 drivers +S_0x114bc80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11499e0; + .timescale -9 -12; +P_0x114be90 .param/l "i" 0 4 54, +C4<0111>; +L_0x12e3d30/d .functor AND 1, L_0x12e4470, L_0x12e4660, C4<1>, C4<1>; +L_0x12e3d30 .delay 1 (30000,30000,30000) L_0x12e3d30/d; +v0x114bf50_0 .net *"_s0", 0 0, L_0x12e4470; 1 drivers +v0x114c030_0 .net *"_s1", 0 0, L_0x12e4660; 1 drivers +S_0x114cbf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11497c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e52840/d .functor OR 1, L_0x1e52900, L_0x1e52ab0, C4<0>, C4<0>; -L_0x1e52840 .delay 1 (30000,30000,30000) L_0x1e52840/d; -v0x1cbbad0_0 .net *"_s10", 0 0, L_0x1e52900; 1 drivers -v0x1cbbbb0_0 .net *"_s12", 0 0, L_0x1e52ab0; 1 drivers -v0x1cbbc90_0 .net "in", 7 0, L_0x1e50840; alias, 1 drivers -v0x1cbbd60_0 .net "ors", 1 0, L_0x1e52660; 1 drivers -v0x1cbbe20_0 .net "out", 0 0, L_0x1e52840; alias, 1 drivers -L_0x1e51a30 .part L_0x1e50840, 0, 4; -L_0x1e52660 .concat8 [ 1 1 0 0], L_0x1e51720, L_0x1e52350; -L_0x1e527a0 .part L_0x1e50840, 4, 4; -L_0x1e52900 .part L_0x1e52660, 0, 1; -L_0x1e52ab0 .part L_0x1e52660, 1, 1; -S_0x1cba140 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cb9f80; +L_0x12e60b0/d .functor OR 1, L_0x12e6170, L_0x12e6320, C4<0>, C4<0>; +L_0x12e60b0 .delay 1 (30000,30000,30000) L_0x12e60b0/d; +v0x114e740_0 .net *"_s10", 0 0, L_0x12e6170; 1 drivers +v0x114e820_0 .net *"_s12", 0 0, L_0x12e6320; 1 drivers +v0x114e900_0 .net "in", 7 0, L_0x12e40b0; alias, 1 drivers +v0x114e9d0_0 .net "ors", 1 0, L_0x12e5ed0; 1 drivers +v0x114ea90_0 .net "out", 0 0, L_0x12e60b0; alias, 1 drivers +L_0x12e52a0 .part L_0x12e40b0, 0, 4; +L_0x12e5ed0 .concat8 [ 1 1 0 0], L_0x12e4f90, L_0x12e5bc0; +L_0x12e6010 .part L_0x12e40b0, 4, 4; +L_0x12e6170 .part L_0x12e5ed0, 0, 1; +L_0x12e6320 .part L_0x12e5ed0, 1, 1; +S_0x114cdb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x114cbf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e50ee0/d .functor OR 1, L_0x1e50fa0, L_0x1e51100, C4<0>, C4<0>; -L_0x1e50ee0 .delay 1 (30000,30000,30000) L_0x1e50ee0/d; -L_0x1e51330/d .functor OR 1, L_0x1e51440, L_0x1e515a0, C4<0>, C4<0>; -L_0x1e51330 .delay 1 (30000,30000,30000) L_0x1e51330/d; -L_0x1e51720/d .functor OR 1, L_0x1e51790, L_0x1e51940, C4<0>, C4<0>; -L_0x1e51720 .delay 1 (30000,30000,30000) L_0x1e51720/d; -v0x1cba390_0 .net *"_s0", 0 0, L_0x1e50ee0; 1 drivers -v0x1cba490_0 .net *"_s10", 0 0, L_0x1e51440; 1 drivers -v0x1cba570_0 .net *"_s12", 0 0, L_0x1e515a0; 1 drivers -v0x1cba630_0 .net *"_s14", 0 0, L_0x1e51790; 1 drivers -v0x1cba710_0 .net *"_s16", 0 0, L_0x1e51940; 1 drivers -v0x1cba840_0 .net *"_s3", 0 0, L_0x1e50fa0; 1 drivers -v0x1cba920_0 .net *"_s5", 0 0, L_0x1e51100; 1 drivers -v0x1cbaa00_0 .net *"_s6", 0 0, L_0x1e51330; 1 drivers -v0x1cbaae0_0 .net "in", 3 0, L_0x1e51a30; 1 drivers -v0x1cbac50_0 .net "ors", 1 0, L_0x1e51240; 1 drivers -v0x1cbad30_0 .net "out", 0 0, L_0x1e51720; 1 drivers -L_0x1e50fa0 .part L_0x1e51a30, 0, 1; -L_0x1e51100 .part L_0x1e51a30, 1, 1; -L_0x1e51240 .concat8 [ 1 1 0 0], L_0x1e50ee0, L_0x1e51330; -L_0x1e51440 .part L_0x1e51a30, 2, 1; -L_0x1e515a0 .part L_0x1e51a30, 3, 1; -L_0x1e51790 .part L_0x1e51240, 0, 1; -L_0x1e51940 .part L_0x1e51240, 1, 1; -S_0x1cbae50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cb9f80; +L_0x12e4750/d .functor OR 1, L_0x12e4810, L_0x12e4970, C4<0>, C4<0>; +L_0x12e4750 .delay 1 (30000,30000,30000) L_0x12e4750/d; +L_0x12e4ba0/d .functor OR 1, L_0x12e4cb0, L_0x12e4e10, C4<0>, C4<0>; +L_0x12e4ba0 .delay 1 (30000,30000,30000) L_0x12e4ba0/d; +L_0x12e4f90/d .functor OR 1, L_0x12e5000, L_0x12e51b0, C4<0>, C4<0>; +L_0x12e4f90 .delay 1 (30000,30000,30000) L_0x12e4f90/d; +v0x114d000_0 .net *"_s0", 0 0, L_0x12e4750; 1 drivers +v0x114d100_0 .net *"_s10", 0 0, L_0x12e4cb0; 1 drivers +v0x114d1e0_0 .net *"_s12", 0 0, L_0x12e4e10; 1 drivers +v0x114d2a0_0 .net *"_s14", 0 0, L_0x12e5000; 1 drivers +v0x114d380_0 .net *"_s16", 0 0, L_0x12e51b0; 1 drivers +v0x114d4b0_0 .net *"_s3", 0 0, L_0x12e4810; 1 drivers +v0x114d590_0 .net *"_s5", 0 0, L_0x12e4970; 1 drivers +v0x114d670_0 .net *"_s6", 0 0, L_0x12e4ba0; 1 drivers +v0x114d750_0 .net "in", 3 0, L_0x12e52a0; 1 drivers +v0x114d8c0_0 .net "ors", 1 0, L_0x12e4ab0; 1 drivers +v0x114d9a0_0 .net "out", 0 0, L_0x12e4f90; 1 drivers +L_0x12e4810 .part L_0x12e52a0, 0, 1; +L_0x12e4970 .part L_0x12e52a0, 1, 1; +L_0x12e4ab0 .concat8 [ 1 1 0 0], L_0x12e4750, L_0x12e4ba0; +L_0x12e4cb0 .part L_0x12e52a0, 2, 1; +L_0x12e4e10 .part L_0x12e52a0, 3, 1; +L_0x12e5000 .part L_0x12e4ab0, 0, 1; +L_0x12e51b0 .part L_0x12e4ab0, 1, 1; +S_0x114dac0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x114cbf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e51b60/d .functor OR 1, L_0x1e51bd0, L_0x1e51d30, C4<0>, C4<0>; -L_0x1e51b60 .delay 1 (30000,30000,30000) L_0x1e51b60/d; -L_0x1e51f60/d .functor OR 1, L_0x1e52070, L_0x1e521d0, C4<0>, C4<0>; -L_0x1e51f60 .delay 1 (30000,30000,30000) L_0x1e51f60/d; -L_0x1e52350/d .functor OR 1, L_0x1e523c0, L_0x1e52570, C4<0>, C4<0>; -L_0x1e52350 .delay 1 (30000,30000,30000) L_0x1e52350/d; -v0x1cbb010_0 .net *"_s0", 0 0, L_0x1e51b60; 1 drivers -v0x1cbb110_0 .net *"_s10", 0 0, L_0x1e52070; 1 drivers -v0x1cbb1f0_0 .net *"_s12", 0 0, L_0x1e521d0; 1 drivers -v0x1cbb2b0_0 .net *"_s14", 0 0, L_0x1e523c0; 1 drivers -v0x1cbb390_0 .net *"_s16", 0 0, L_0x1e52570; 1 drivers -v0x1cbb4c0_0 .net *"_s3", 0 0, L_0x1e51bd0; 1 drivers -v0x1cbb5a0_0 .net *"_s5", 0 0, L_0x1e51d30; 1 drivers -v0x1cbb680_0 .net *"_s6", 0 0, L_0x1e51f60; 1 drivers -v0x1cbb760_0 .net "in", 3 0, L_0x1e527a0; 1 drivers -v0x1cbb8d0_0 .net "ors", 1 0, L_0x1e51e70; 1 drivers -v0x1cbb9b0_0 .net "out", 0 0, L_0x1e52350; 1 drivers -L_0x1e51bd0 .part L_0x1e527a0, 0, 1; -L_0x1e51d30 .part L_0x1e527a0, 1, 1; -L_0x1e51e70 .concat8 [ 1 1 0 0], L_0x1e51b60, L_0x1e51f60; -L_0x1e52070 .part L_0x1e527a0, 2, 1; -L_0x1e521d0 .part L_0x1e527a0, 3, 1; -L_0x1e523c0 .part L_0x1e51e70, 0, 1; -L_0x1e52570 .part L_0x1e51e70, 1, 1; -S_0x1cbc2c0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cb53f0; +L_0x12e53d0/d .functor OR 1, L_0x12e5440, L_0x12e55a0, C4<0>, C4<0>; +L_0x12e53d0 .delay 1 (30000,30000,30000) L_0x12e53d0/d; +L_0x12e57d0/d .functor OR 1, L_0x12e58e0, L_0x12e5a40, C4<0>, C4<0>; +L_0x12e57d0 .delay 1 (30000,30000,30000) L_0x12e57d0/d; +L_0x12e5bc0/d .functor OR 1, L_0x12e5c30, L_0x12e5de0, C4<0>, C4<0>; +L_0x12e5bc0 .delay 1 (30000,30000,30000) L_0x12e5bc0/d; +v0x114dc80_0 .net *"_s0", 0 0, L_0x12e53d0; 1 drivers +v0x114dd80_0 .net *"_s10", 0 0, L_0x12e58e0; 1 drivers +v0x114de60_0 .net *"_s12", 0 0, L_0x12e5a40; 1 drivers +v0x114df20_0 .net *"_s14", 0 0, L_0x12e5c30; 1 drivers +v0x114e000_0 .net *"_s16", 0 0, L_0x12e5de0; 1 drivers +v0x114e130_0 .net *"_s3", 0 0, L_0x12e5440; 1 drivers +v0x114e210_0 .net *"_s5", 0 0, L_0x12e55a0; 1 drivers +v0x114e2f0_0 .net *"_s6", 0 0, L_0x12e57d0; 1 drivers +v0x114e3d0_0 .net "in", 3 0, L_0x12e6010; 1 drivers +v0x114e540_0 .net "ors", 1 0, L_0x12e56e0; 1 drivers +v0x114e620_0 .net "out", 0 0, L_0x12e5bc0; 1 drivers +L_0x12e5440 .part L_0x12e6010, 0, 1; +L_0x12e55a0 .part L_0x12e6010, 1, 1; +L_0x12e56e0 .concat8 [ 1 1 0 0], L_0x12e53d0, L_0x12e57d0; +L_0x12e58e0 .part L_0x12e6010, 2, 1; +L_0x12e5a40 .part L_0x12e6010, 3, 1; +L_0x12e5c30 .part L_0x12e56e0, 0, 1; +L_0x12e5de0 .part L_0x12e56e0, 1, 1; +S_0x114ef30 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1148060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cc16f0_0 .net "ands", 7 0, L_0x1e4cd40; 1 drivers -v0x1cc1800_0 .net "in", 7 0, L_0x1e4b1a0; alias, 1 drivers -v0x1cc18c0_0 .net "out", 0 0, L_0x1e4ed40; alias, 1 drivers -v0x1cc1990_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cbc510 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cbc2c0; +v0x1154360_0 .net "ands", 7 0, L_0x12e0580; 1 drivers +v0x1154470_0 .net "in", 7 0, L_0x12de9e0; alias, 1 drivers +v0x1154530_0 .net "out", 0 0, L_0x12e25b0; alias, 1 drivers +v0x1154600_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x114f180 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x114ef30; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cbec50_0 .net "A", 7 0, L_0x1e4b1a0; alias, 1 drivers -v0x1cbed50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cbee10_0 .net *"_s0", 0 0, L_0x1e4b530; 1 drivers -v0x1cbeed0_0 .net *"_s12", 0 0, L_0x1e4bef0; 1 drivers -v0x1cbefb0_0 .net *"_s16", 0 0, L_0x1e4c250; 1 drivers -v0x1cbf0e0_0 .net *"_s20", 0 0, L_0x1e4c680; 1 drivers -v0x1cbf1c0_0 .net *"_s24", 0 0, L_0x1e4c9b0; 1 drivers -v0x1cbf2a0_0 .net *"_s28", 0 0, L_0x1e4c940; 1 drivers -v0x1cbf380_0 .net *"_s4", 0 0, L_0x1e4b8d0; 1 drivers -v0x1cbf4f0_0 .net *"_s8", 0 0, L_0x1e4bbe0; 1 drivers -v0x1cbf5d0_0 .net "out", 7 0, L_0x1e4cd40; alias, 1 drivers -L_0x1e4b640 .part L_0x1e4b1a0, 0, 1; -L_0x1e4b830 .part v0x1d6daa0_0, 0, 1; -L_0x1e4b990 .part L_0x1e4b1a0, 1, 1; -L_0x1e4baf0 .part v0x1d6daa0_0, 1, 1; -L_0x1e4bca0 .part L_0x1e4b1a0, 2, 1; -L_0x1e4be00 .part v0x1d6daa0_0, 2, 1; -L_0x1e4bfb0 .part L_0x1e4b1a0, 3, 1; -L_0x1e4c110 .part v0x1d6daa0_0, 3, 1; -L_0x1e4c310 .part L_0x1e4b1a0, 4, 1; -L_0x1e4c580 .part v0x1d6daa0_0, 4, 1; -L_0x1e4c6f0 .part L_0x1e4b1a0, 5, 1; -L_0x1e4c850 .part v0x1d6daa0_0, 5, 1; -L_0x1e4ca70 .part L_0x1e4b1a0, 6, 1; -L_0x1e4cbd0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e4cd40_0_0 .concat8 [ 1 1 1 1], L_0x1e4b530, L_0x1e4b8d0, L_0x1e4bbe0, L_0x1e4bef0; -LS_0x1e4cd40_0_4 .concat8 [ 1 1 1 1], L_0x1e4c250, L_0x1e4c680, L_0x1e4c9b0, L_0x1e4c940; -L_0x1e4cd40 .concat8 [ 4 4 0 0], LS_0x1e4cd40_0_0, LS_0x1e4cd40_0_4; -L_0x1e4d100 .part L_0x1e4b1a0, 7, 1; -L_0x1e4d2f0 .part v0x1d6daa0_0, 7, 1; -S_0x1cbc750 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbc960 .param/l "i" 0 4 54, +C4<00>; -L_0x1e4b530/d .functor AND 1, L_0x1e4b640, L_0x1e4b830, C4<1>, C4<1>; -L_0x1e4b530 .delay 1 (30000,30000,30000) L_0x1e4b530/d; -v0x1cbca40_0 .net *"_s0", 0 0, L_0x1e4b640; 1 drivers -v0x1cbcb20_0 .net *"_s1", 0 0, L_0x1e4b830; 1 drivers -S_0x1cbcc00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbce10 .param/l "i" 0 4 54, +C4<01>; -L_0x1e4b8d0/d .functor AND 1, L_0x1e4b990, L_0x1e4baf0, C4<1>, C4<1>; -L_0x1e4b8d0 .delay 1 (30000,30000,30000) L_0x1e4b8d0/d; -v0x1cbced0_0 .net *"_s0", 0 0, L_0x1e4b990; 1 drivers -v0x1cbcfb0_0 .net *"_s1", 0 0, L_0x1e4baf0; 1 drivers -S_0x1cbd090 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbd2d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e4bbe0/d .functor AND 1, L_0x1e4bca0, L_0x1e4be00, C4<1>, C4<1>; -L_0x1e4bbe0 .delay 1 (30000,30000,30000) L_0x1e4bbe0/d; -v0x1cbd370_0 .net *"_s0", 0 0, L_0x1e4bca0; 1 drivers -v0x1cbd450_0 .net *"_s1", 0 0, L_0x1e4be00; 1 drivers -S_0x1cbd530 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbd740 .param/l "i" 0 4 54, +C4<011>; -L_0x1e4bef0/d .functor AND 1, L_0x1e4bfb0, L_0x1e4c110, C4<1>, C4<1>; -L_0x1e4bef0 .delay 1 (30000,30000,30000) L_0x1e4bef0/d; -v0x1cbd800_0 .net *"_s0", 0 0, L_0x1e4bfb0; 1 drivers -v0x1cbd8e0_0 .net *"_s1", 0 0, L_0x1e4c110; 1 drivers -S_0x1cbd9c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbdc20 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e4c250/d .functor AND 1, L_0x1e4c310, L_0x1e4c580, C4<1>, C4<1>; -L_0x1e4c250 .delay 1 (30000,30000,30000) L_0x1e4c250/d; -v0x1cbdce0_0 .net *"_s0", 0 0, L_0x1e4c310; 1 drivers -v0x1cbddc0_0 .net *"_s1", 0 0, L_0x1e4c580; 1 drivers -S_0x1cbdea0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbe0b0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e4c680/d .functor AND 1, L_0x1e4c6f0, L_0x1e4c850, C4<1>, C4<1>; -L_0x1e4c680 .delay 1 (30000,30000,30000) L_0x1e4c680/d; -v0x1cbe170_0 .net *"_s0", 0 0, L_0x1e4c6f0; 1 drivers -v0x1cbe250_0 .net *"_s1", 0 0, L_0x1e4c850; 1 drivers -S_0x1cbe330 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbe540 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e4c9b0/d .functor AND 1, L_0x1e4ca70, L_0x1e4cbd0, C4<1>, C4<1>; -L_0x1e4c9b0 .delay 1 (30000,30000,30000) L_0x1e4c9b0/d; -v0x1cbe600_0 .net *"_s0", 0 0, L_0x1e4ca70; 1 drivers -v0x1cbe6e0_0 .net *"_s1", 0 0, L_0x1e4cbd0; 1 drivers -S_0x1cbe7c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cbc510; - .timescale -9 -12; -P_0x1cbe9d0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e4c940/d .functor AND 1, L_0x1e4d100, L_0x1e4d2f0, C4<1>, C4<1>; -L_0x1e4c940 .delay 1 (30000,30000,30000) L_0x1e4c940/d; -v0x1cbea90_0 .net *"_s0", 0 0, L_0x1e4d100; 1 drivers -v0x1cbeb70_0 .net *"_s1", 0 0, L_0x1e4d2f0; 1 drivers -S_0x1cbf730 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cbc2c0; +v0x11518c0_0 .net "A", 7 0, L_0x12de9e0; alias, 1 drivers +v0x11519c0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1151a80_0 .net *"_s0", 0 0, L_0x12ded70; 1 drivers +v0x1151b40_0 .net *"_s12", 0 0, L_0x12df730; 1 drivers +v0x1151c20_0 .net *"_s16", 0 0, L_0x12dfa90; 1 drivers +v0x1151d50_0 .net *"_s20", 0 0, L_0x12dfec0; 1 drivers +v0x1151e30_0 .net *"_s24", 0 0, L_0x12e01f0; 1 drivers +v0x1151f10_0 .net *"_s28", 0 0, L_0x12e0180; 1 drivers +v0x1151ff0_0 .net *"_s4", 0 0, L_0x12df110; 1 drivers +v0x1152160_0 .net *"_s8", 0 0, L_0x12df420; 1 drivers +v0x1152240_0 .net "out", 7 0, L_0x12e0580; alias, 1 drivers +L_0x12dee80 .part L_0x12de9e0, 0, 1; +L_0x12df070 .part v0x12010b0_0, 0, 1; +L_0x12df1d0 .part L_0x12de9e0, 1, 1; +L_0x12df330 .part v0x12010b0_0, 1, 1; +L_0x12df4e0 .part L_0x12de9e0, 2, 1; +L_0x12df640 .part v0x12010b0_0, 2, 1; +L_0x12df7f0 .part L_0x12de9e0, 3, 1; +L_0x12df950 .part v0x12010b0_0, 3, 1; +L_0x12dfb50 .part L_0x12de9e0, 4, 1; +L_0x12dfdc0 .part v0x12010b0_0, 4, 1; +L_0x12dff30 .part L_0x12de9e0, 5, 1; +L_0x12e0090 .part v0x12010b0_0, 5, 1; +L_0x12e02b0 .part L_0x12de9e0, 6, 1; +L_0x12e0410 .part v0x12010b0_0, 6, 1; +LS_0x12e0580_0_0 .concat8 [ 1 1 1 1], L_0x12ded70, L_0x12df110, L_0x12df420, L_0x12df730; +LS_0x12e0580_0_4 .concat8 [ 1 1 1 1], L_0x12dfa90, L_0x12dfec0, L_0x12e01f0, L_0x12e0180; +L_0x12e0580 .concat8 [ 4 4 0 0], LS_0x12e0580_0_0, LS_0x12e0580_0_4; +L_0x12e0940 .part L_0x12de9e0, 7, 1; +L_0x12e0b30 .part v0x12010b0_0, 7, 1; +S_0x114f3c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x114f5d0 .param/l "i" 0 4 54, +C4<00>; +L_0x12ded70/d .functor AND 1, L_0x12dee80, L_0x12df070, C4<1>, C4<1>; +L_0x12ded70 .delay 1 (30000,30000,30000) L_0x12ded70/d; +v0x114f6b0_0 .net *"_s0", 0 0, L_0x12dee80; 1 drivers +v0x114f790_0 .net *"_s1", 0 0, L_0x12df070; 1 drivers +S_0x114f870 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x114fa80 .param/l "i" 0 4 54, +C4<01>; +L_0x12df110/d .functor AND 1, L_0x12df1d0, L_0x12df330, C4<1>, C4<1>; +L_0x12df110 .delay 1 (30000,30000,30000) L_0x12df110/d; +v0x114fb40_0 .net *"_s0", 0 0, L_0x12df1d0; 1 drivers +v0x114fc20_0 .net *"_s1", 0 0, L_0x12df330; 1 drivers +S_0x114fd00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x114ff40 .param/l "i" 0 4 54, +C4<010>; +L_0x12df420/d .functor AND 1, L_0x12df4e0, L_0x12df640, C4<1>, C4<1>; +L_0x12df420 .delay 1 (30000,30000,30000) L_0x12df420/d; +v0x114ffe0_0 .net *"_s0", 0 0, L_0x12df4e0; 1 drivers +v0x11500c0_0 .net *"_s1", 0 0, L_0x12df640; 1 drivers +S_0x11501a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x11503b0 .param/l "i" 0 4 54, +C4<011>; +L_0x12df730/d .functor AND 1, L_0x12df7f0, L_0x12df950, C4<1>, C4<1>; +L_0x12df730 .delay 1 (30000,30000,30000) L_0x12df730/d; +v0x1150470_0 .net *"_s0", 0 0, L_0x12df7f0; 1 drivers +v0x1150550_0 .net *"_s1", 0 0, L_0x12df950; 1 drivers +S_0x1150630 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x1150890 .param/l "i" 0 4 54, +C4<0100>; +L_0x12dfa90/d .functor AND 1, L_0x12dfb50, L_0x12dfdc0, C4<1>, C4<1>; +L_0x12dfa90 .delay 1 (30000,30000,30000) L_0x12dfa90/d; +v0x1150950_0 .net *"_s0", 0 0, L_0x12dfb50; 1 drivers +v0x1150a30_0 .net *"_s1", 0 0, L_0x12dfdc0; 1 drivers +S_0x1150b10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x1150d20 .param/l "i" 0 4 54, +C4<0101>; +L_0x12dfec0/d .functor AND 1, L_0x12dff30, L_0x12e0090, C4<1>, C4<1>; +L_0x12dfec0 .delay 1 (30000,30000,30000) L_0x12dfec0/d; +v0x1150de0_0 .net *"_s0", 0 0, L_0x12dff30; 1 drivers +v0x1150ec0_0 .net *"_s1", 0 0, L_0x12e0090; 1 drivers +S_0x1150fa0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x11511b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12e01f0/d .functor AND 1, L_0x12e02b0, L_0x12e0410, C4<1>, C4<1>; +L_0x12e01f0 .delay 1 (30000,30000,30000) L_0x12e01f0/d; +v0x1151270_0 .net *"_s0", 0 0, L_0x12e02b0; 1 drivers +v0x1151350_0 .net *"_s1", 0 0, L_0x12e0410; 1 drivers +S_0x1151430 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x114f180; + .timescale -9 -12; +P_0x1151640 .param/l "i" 0 4 54, +C4<0111>; +L_0x12e0180/d .functor AND 1, L_0x12e0940, L_0x12e0b30, C4<1>, C4<1>; +L_0x12e0180 .delay 1 (30000,30000,30000) L_0x12e0180/d; +v0x1151700_0 .net *"_s0", 0 0, L_0x12e0940; 1 drivers +v0x11517e0_0 .net *"_s1", 0 0, L_0x12e0b30; 1 drivers +S_0x11523a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x114ef30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e4ed40/d .functor OR 1, L_0x1e4ee00, L_0x1e4efb0, C4<0>, C4<0>; -L_0x1e4ed40 .delay 1 (30000,30000,30000) L_0x1e4ed40/d; -v0x1cc1280_0 .net *"_s10", 0 0, L_0x1e4ee00; 1 drivers -v0x1cc1360_0 .net *"_s12", 0 0, L_0x1e4efb0; 1 drivers -v0x1cc1440_0 .net "in", 7 0, L_0x1e4cd40; alias, 1 drivers -v0x1cc1510_0 .net "ors", 1 0, L_0x1e4eb60; 1 drivers -v0x1cc15d0_0 .net "out", 0 0, L_0x1e4ed40; alias, 1 drivers -L_0x1e4df30 .part L_0x1e4cd40, 0, 4; -L_0x1e4eb60 .concat8 [ 1 1 0 0], L_0x1e4dc20, L_0x1e4e850; -L_0x1e4eca0 .part L_0x1e4cd40, 4, 4; -L_0x1e4ee00 .part L_0x1e4eb60, 0, 1; -L_0x1e4efb0 .part L_0x1e4eb60, 1, 1; -S_0x1cbf8f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cbf730; +L_0x12e25b0/d .functor OR 1, L_0x12e2670, L_0x12e2820, C4<0>, C4<0>; +L_0x12e25b0 .delay 1 (30000,30000,30000) L_0x12e25b0/d; +v0x1153ef0_0 .net *"_s10", 0 0, L_0x12e2670; 1 drivers +v0x1153fd0_0 .net *"_s12", 0 0, L_0x12e2820; 1 drivers +v0x11540b0_0 .net "in", 7 0, L_0x12e0580; alias, 1 drivers +v0x1154180_0 .net "ors", 1 0, L_0x12e23d0; 1 drivers +v0x1154240_0 .net "out", 0 0, L_0x12e25b0; alias, 1 drivers +L_0x12e1770 .part L_0x12e0580, 0, 4; +L_0x12e23d0 .concat8 [ 1 1 0 0], L_0x12e1460, L_0x12e2090; +L_0x12e2510 .part L_0x12e0580, 4, 4; +L_0x12e2670 .part L_0x12e23d0, 0, 1; +L_0x12e2820 .part L_0x12e23d0, 1, 1; +S_0x1152560 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11523a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e4d3e0/d .functor OR 1, L_0x1e4d4a0, L_0x1e4d600, C4<0>, C4<0>; -L_0x1e4d3e0 .delay 1 (30000,30000,30000) L_0x1e4d3e0/d; -L_0x1e4d830/d .functor OR 1, L_0x1e4d940, L_0x1e4daa0, C4<0>, C4<0>; -L_0x1e4d830 .delay 1 (30000,30000,30000) L_0x1e4d830/d; -L_0x1e4dc20/d .functor OR 1, L_0x1e4dc90, L_0x1e4de40, C4<0>, C4<0>; -L_0x1e4dc20 .delay 1 (30000,30000,30000) L_0x1e4dc20/d; -v0x1cbfb40_0 .net *"_s0", 0 0, L_0x1e4d3e0; 1 drivers -v0x1cbfc40_0 .net *"_s10", 0 0, L_0x1e4d940; 1 drivers -v0x1cbfd20_0 .net *"_s12", 0 0, L_0x1e4daa0; 1 drivers -v0x1cbfde0_0 .net *"_s14", 0 0, L_0x1e4dc90; 1 drivers -v0x1cbfec0_0 .net *"_s16", 0 0, L_0x1e4de40; 1 drivers -v0x1cbfff0_0 .net *"_s3", 0 0, L_0x1e4d4a0; 1 drivers -v0x1cc00d0_0 .net *"_s5", 0 0, L_0x1e4d600; 1 drivers -v0x1cc01b0_0 .net *"_s6", 0 0, L_0x1e4d830; 1 drivers -v0x1cc0290_0 .net "in", 3 0, L_0x1e4df30; 1 drivers -v0x1cc0400_0 .net "ors", 1 0, L_0x1e4d740; 1 drivers -v0x1cc04e0_0 .net "out", 0 0, L_0x1e4dc20; 1 drivers -L_0x1e4d4a0 .part L_0x1e4df30, 0, 1; -L_0x1e4d600 .part L_0x1e4df30, 1, 1; -L_0x1e4d740 .concat8 [ 1 1 0 0], L_0x1e4d3e0, L_0x1e4d830; -L_0x1e4d940 .part L_0x1e4df30, 2, 1; -L_0x1e4daa0 .part L_0x1e4df30, 3, 1; -L_0x1e4dc90 .part L_0x1e4d740, 0, 1; -L_0x1e4de40 .part L_0x1e4d740, 1, 1; -S_0x1cc0600 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cbf730; +L_0x12e0c20/d .functor OR 1, L_0x12e0ce0, L_0x12e0e40, C4<0>, C4<0>; +L_0x12e0c20 .delay 1 (30000,30000,30000) L_0x12e0c20/d; +L_0x12e1070/d .functor OR 1, L_0x12e1180, L_0x12e12e0, C4<0>, C4<0>; +L_0x12e1070 .delay 1 (30000,30000,30000) L_0x12e1070/d; +L_0x12e1460/d .functor OR 1, L_0x12e14d0, L_0x12e1680, C4<0>, C4<0>; +L_0x12e1460 .delay 1 (30000,30000,30000) L_0x12e1460/d; +v0x11527b0_0 .net *"_s0", 0 0, L_0x12e0c20; 1 drivers +v0x11528b0_0 .net *"_s10", 0 0, L_0x12e1180; 1 drivers +v0x1152990_0 .net *"_s12", 0 0, L_0x12e12e0; 1 drivers +v0x1152a50_0 .net *"_s14", 0 0, L_0x12e14d0; 1 drivers +v0x1152b30_0 .net *"_s16", 0 0, L_0x12e1680; 1 drivers +v0x1152c60_0 .net *"_s3", 0 0, L_0x12e0ce0; 1 drivers +v0x1152d40_0 .net *"_s5", 0 0, L_0x12e0e40; 1 drivers +v0x1152e20_0 .net *"_s6", 0 0, L_0x12e1070; 1 drivers +v0x1152f00_0 .net "in", 3 0, L_0x12e1770; 1 drivers +v0x1153070_0 .net "ors", 1 0, L_0x12e0f80; 1 drivers +v0x1153150_0 .net "out", 0 0, L_0x12e1460; 1 drivers +L_0x12e0ce0 .part L_0x12e1770, 0, 1; +L_0x12e0e40 .part L_0x12e1770, 1, 1; +L_0x12e0f80 .concat8 [ 1 1 0 0], L_0x12e0c20, L_0x12e1070; +L_0x12e1180 .part L_0x12e1770, 2, 1; +L_0x12e12e0 .part L_0x12e1770, 3, 1; +L_0x12e14d0 .part L_0x12e0f80, 0, 1; +L_0x12e1680 .part L_0x12e0f80, 1, 1; +S_0x1153270 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11523a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e4e060/d .functor OR 1, L_0x1e4e0d0, L_0x1e4e230, C4<0>, C4<0>; -L_0x1e4e060 .delay 1 (30000,30000,30000) L_0x1e4e060/d; -L_0x1e4e460/d .functor OR 1, L_0x1e4e570, L_0x1e4e6d0, C4<0>, C4<0>; -L_0x1e4e460 .delay 1 (30000,30000,30000) L_0x1e4e460/d; -L_0x1e4e850/d .functor OR 1, L_0x1e4e8c0, L_0x1e4ea70, C4<0>, C4<0>; -L_0x1e4e850 .delay 1 (30000,30000,30000) L_0x1e4e850/d; -v0x1cc07c0_0 .net *"_s0", 0 0, L_0x1e4e060; 1 drivers -v0x1cc08c0_0 .net *"_s10", 0 0, L_0x1e4e570; 1 drivers -v0x1cc09a0_0 .net *"_s12", 0 0, L_0x1e4e6d0; 1 drivers -v0x1cc0a60_0 .net *"_s14", 0 0, L_0x1e4e8c0; 1 drivers -v0x1cc0b40_0 .net *"_s16", 0 0, L_0x1e4ea70; 1 drivers -v0x1cc0c70_0 .net *"_s3", 0 0, L_0x1e4e0d0; 1 drivers -v0x1cc0d50_0 .net *"_s5", 0 0, L_0x1e4e230; 1 drivers -v0x1cc0e30_0 .net *"_s6", 0 0, L_0x1e4e460; 1 drivers -v0x1cc0f10_0 .net "in", 3 0, L_0x1e4eca0; 1 drivers -v0x1cc1080_0 .net "ors", 1 0, L_0x1e4e370; 1 drivers -v0x1cc1160_0 .net "out", 0 0, L_0x1e4e850; 1 drivers -L_0x1e4e0d0 .part L_0x1e4eca0, 0, 1; -L_0x1e4e230 .part L_0x1e4eca0, 1, 1; -L_0x1e4e370 .concat8 [ 1 1 0 0], L_0x1e4e060, L_0x1e4e460; -L_0x1e4e570 .part L_0x1e4eca0, 2, 1; -L_0x1e4e6d0 .part L_0x1e4eca0, 3, 1; -L_0x1e4e8c0 .part L_0x1e4e370, 0, 1; -L_0x1e4ea70 .part L_0x1e4e370, 1, 1; -S_0x1cc1a70 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cb53f0; +L_0x12e18a0/d .functor OR 1, L_0x12e1910, L_0x12e1a70, C4<0>, C4<0>; +L_0x12e18a0 .delay 1 (30000,30000,30000) L_0x12e18a0/d; +L_0x12e1ca0/d .functor OR 1, L_0x12e1db0, L_0x12e1f10, C4<0>, C4<0>; +L_0x12e1ca0 .delay 1 (30000,30000,30000) L_0x12e1ca0/d; +L_0x12e2090/d .functor OR 1, L_0x12e2130, L_0x12e22e0, C4<0>, C4<0>; +L_0x12e2090 .delay 1 (30000,30000,30000) L_0x12e2090/d; +v0x1153430_0 .net *"_s0", 0 0, L_0x12e18a0; 1 drivers +v0x1153530_0 .net *"_s10", 0 0, L_0x12e1db0; 1 drivers +v0x1153610_0 .net *"_s12", 0 0, L_0x12e1f10; 1 drivers +v0x11536d0_0 .net *"_s14", 0 0, L_0x12e2130; 1 drivers +v0x11537b0_0 .net *"_s16", 0 0, L_0x12e22e0; 1 drivers +v0x11538e0_0 .net *"_s3", 0 0, L_0x12e1910; 1 drivers +v0x11539c0_0 .net *"_s5", 0 0, L_0x12e1a70; 1 drivers +v0x1153aa0_0 .net *"_s6", 0 0, L_0x12e1ca0; 1 drivers +v0x1153b80_0 .net "in", 3 0, L_0x12e2510; 1 drivers +v0x1153cf0_0 .net "ors", 1 0, L_0x12e1bb0; 1 drivers +v0x1153dd0_0 .net "out", 0 0, L_0x12e2090; 1 drivers +L_0x12e1910 .part L_0x12e2510, 0, 1; +L_0x12e1a70 .part L_0x12e2510, 1, 1; +L_0x12e1bb0 .concat8 [ 1 1 0 0], L_0x12e18a0, L_0x12e1ca0; +L_0x12e1db0 .part L_0x12e2510, 2, 1; +L_0x12e1f10 .part L_0x12e2510, 3, 1; +L_0x12e2130 .part L_0x12e1bb0, 0, 1; +L_0x12e22e0 .part L_0x12e1bb0, 1, 1; +S_0x11546e0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1148060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -12316,80 +12326,80 @@ S_0x1cc1a70 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cb53f0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e4a510/d .functor XNOR 1, L_0x1e52ca0, L_0x1e52e00, C4<0>, C4<0>; -L_0x1e4a510 .delay 1 (20000,20000,20000) L_0x1e4a510/d; -L_0x1e4a780/d .functor AND 1, L_0x1e52ca0, L_0x1e49450, C4<1>, C4<1>; -L_0x1e4a780 .delay 1 (30000,30000,30000) L_0x1e4a780/d; -L_0x1e4a7f0/d .functor AND 1, L_0x1e4a510, L_0x1e49230, C4<1>, C4<1>; -L_0x1e4a7f0 .delay 1 (30000,30000,30000) L_0x1e4a7f0/d; -L_0x1e4a950/d .functor OR 1, L_0x1e4a7f0, L_0x1e4a780, C4<0>, C4<0>; -L_0x1e4a950 .delay 1 (30000,30000,30000) L_0x1e4a950/d; -v0x1cc1d20_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers -v0x1cc1e10_0 .net "a_", 0 0, L_0x1e3d590; alias, 1 drivers -v0x1cc1ed0_0 .net "b", 0 0, L_0x1e52e00; alias, 1 drivers -v0x1cc1fc0_0 .net "b_", 0 0, L_0x1e49450; alias, 1 drivers -v0x1cc2060_0 .net "carryin", 0 0, L_0x1e49230; alias, 1 drivers -v0x1cc21a0_0 .net "eq", 0 0, L_0x1e4a510; 1 drivers -v0x1cc2260_0 .net "lt", 0 0, L_0x1e4a780; 1 drivers -v0x1cc2320_0 .net "out", 0 0, L_0x1e4a950; 1 drivers -v0x1cc23e0_0 .net "w0", 0 0, L_0x1e4a7f0; 1 drivers -S_0x1cc2630 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cb53f0; +L_0x12ddd50/d .functor XNOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; +L_0x12ddd50 .delay 1 (20000,20000,20000) L_0x12ddd50/d; +L_0x12ddfc0/d .functor AND 1, L_0x12e6510, L_0x12dcc90, C4<1>, C4<1>; +L_0x12ddfc0 .delay 1 (30000,30000,30000) L_0x12ddfc0/d; +L_0x12de030/d .functor AND 1, L_0x12ddd50, L_0x12dca20, C4<1>, C4<1>; +L_0x12de030 .delay 1 (30000,30000,30000) L_0x12de030/d; +L_0x12de190/d .functor OR 1, L_0x12de030, L_0x12ddfc0, C4<0>, C4<0>; +L_0x12de190 .delay 1 (30000,30000,30000) L_0x12de190/d; +v0x1154990_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers +v0x1154a80_0 .net "a_", 0 0, L_0x12d0e90; alias, 1 drivers +v0x1154b40_0 .net "b", 0 0, L_0x12e6670; alias, 1 drivers +v0x1154c30_0 .net "b_", 0 0, L_0x12dcc90; alias, 1 drivers +v0x1154cd0_0 .net "carryin", 0 0, L_0x12dca20; alias, 1 drivers +v0x1154e10_0 .net "eq", 0 0, L_0x12ddd50; 1 drivers +v0x1154ed0_0 .net "lt", 0 0, L_0x12ddfc0; 1 drivers +v0x1154f90_0 .net "out", 0 0, L_0x12de190; 1 drivers +v0x1155050_0 .net "w0", 0 0, L_0x12de030; 1 drivers +S_0x11552a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1148060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e4a2f0/d .functor OR 1, L_0x1e49e40, L_0x1cc3890, C4<0>, C4<0>; -L_0x1e4a2f0 .delay 1 (30000,30000,30000) L_0x1e4a2f0/d; -v0x1cc3420_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers -v0x1cc3570_0 .net "b", 0 0, L_0x1e49450; alias, 1 drivers -v0x1cc3630_0 .net "c1", 0 0, L_0x1e49e40; 1 drivers -v0x1cc36d0_0 .net "c2", 0 0, L_0x1cc3890; 1 drivers -v0x1cc37a0_0 .net "carryin", 0 0, L_0x1e49230; alias, 1 drivers -v0x1cc3920_0 .net "carryout", 0 0, L_0x1e4a2f0; 1 drivers -v0x1cc39c0_0 .net "s1", 0 0, L_0x1e49d80; 1 drivers -v0x1cc3a60_0 .net "sum", 0 0, L_0x1e49fa0; 1 drivers -S_0x1cc2880 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cc2630; +L_0x12ddb30/d .functor OR 1, L_0x12dd680, L_0x1156500, C4<0>, C4<0>; +L_0x12ddb30 .delay 1 (30000,30000,30000) L_0x12ddb30/d; +v0x1156090_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers +v0x11561e0_0 .net "b", 0 0, L_0x12dcc90; alias, 1 drivers +v0x11562a0_0 .net "c1", 0 0, L_0x12dd680; 1 drivers +v0x1156340_0 .net "c2", 0 0, L_0x1156500; 1 drivers +v0x1156410_0 .net "carryin", 0 0, L_0x12dca20; alias, 1 drivers +v0x1156590_0 .net "carryout", 0 0, L_0x12ddb30; 1 drivers +v0x1156630_0 .net "s1", 0 0, L_0x12dd5c0; 1 drivers +v0x11566d0_0 .net "sum", 0 0, L_0x12dd7e0; 1 drivers +S_0x11554f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11552a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e49d80/d .functor XOR 1, L_0x1e52ca0, L_0x1e49450, C4<0>, C4<0>; -L_0x1e49d80 .delay 1 (30000,30000,30000) L_0x1e49d80/d; -L_0x1e49e40/d .functor AND 1, L_0x1e52ca0, L_0x1e49450, C4<1>, C4<1>; -L_0x1e49e40 .delay 1 (30000,30000,30000) L_0x1e49e40/d; -v0x1cc2ae0_0 .net "a", 0 0, L_0x1e52ca0; alias, 1 drivers -v0x1cc2ba0_0 .net "b", 0 0, L_0x1e49450; alias, 1 drivers -v0x1cc2c60_0 .net "carryout", 0 0, L_0x1e49e40; alias, 1 drivers -v0x1cc2d00_0 .net "sum", 0 0, L_0x1e49d80; alias, 1 drivers -S_0x1cc2e30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cc2630; +L_0x12dd5c0/d .functor XOR 1, L_0x12e6510, L_0x12dcc90, C4<0>, C4<0>; +L_0x12dd5c0 .delay 1 (30000,30000,30000) L_0x12dd5c0/d; +L_0x12dd680/d .functor AND 1, L_0x12e6510, L_0x12dcc90, C4<1>, C4<1>; +L_0x12dd680 .delay 1 (30000,30000,30000) L_0x12dd680/d; +v0x1155750_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers +v0x1155810_0 .net "b", 0 0, L_0x12dcc90; alias, 1 drivers +v0x11558d0_0 .net "carryout", 0 0, L_0x12dd680; alias, 1 drivers +v0x1155970_0 .net "sum", 0 0, L_0x12dd5c0; alias, 1 drivers +S_0x1155aa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11552a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e49fa0/d .functor XOR 1, L_0x1e49d80, L_0x1e49230, C4<0>, C4<0>; -L_0x1e49fa0 .delay 1 (30000,30000,30000) L_0x1e49fa0/d; -L_0x1cc3890/d .functor AND 1, L_0x1e49d80, L_0x1e49230, C4<1>, C4<1>; -L_0x1cc3890 .delay 1 (30000,30000,30000) L_0x1cc3890/d; -v0x1cc3090_0 .net "a", 0 0, L_0x1e49d80; alias, 1 drivers -v0x1cc3160_0 .net "b", 0 0, L_0x1e49230; alias, 1 drivers -v0x1cc3200_0 .net "carryout", 0 0, L_0x1cc3890; alias, 1 drivers -v0x1cc32d0_0 .net "sum", 0 0, L_0x1e49fa0; alias, 1 drivers -S_0x1cc4e80 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cb5120; - .timescale -9 -12; -L_0x7f72592db8d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db920 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e52d40/d .functor OR 1, L_0x7f72592db8d8, L_0x7f72592db920, C4<0>, C4<0>; -L_0x1e52d40 .delay 1 (30000,30000,30000) L_0x1e52d40/d; -v0x1cc5070_0 .net/2u *"_s0", 0 0, L_0x7f72592db8d8; 1 drivers -v0x1cc5150_0 .net/2u *"_s2", 0 0, L_0x7f72592db920; 1 drivers -S_0x1cc5230 .scope generate, "alu_slices[23]" "alu_slices[23]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1cc5440 .param/l "i" 0 3 37, +C4<010111>; -S_0x1cc5500 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cc5230; +L_0x12dd7e0/d .functor XOR 1, L_0x12dd5c0, L_0x12dca20, C4<0>, C4<0>; +L_0x12dd7e0 .delay 1 (30000,30000,30000) L_0x12dd7e0/d; +L_0x1156500/d .functor AND 1, L_0x12dd5c0, L_0x12dca20, C4<1>, C4<1>; +L_0x1156500 .delay 1 (30000,30000,30000) L_0x1156500/d; +v0x1155d00_0 .net "a", 0 0, L_0x12dd5c0; alias, 1 drivers +v0x1155dd0_0 .net "b", 0 0, L_0x12dca20; alias, 1 drivers +v0x1155e70_0 .net "carryout", 0 0, L_0x1156500; alias, 1 drivers +v0x1155f40_0 .net "sum", 0 0, L_0x12dd7e0; alias, 1 drivers +S_0x1157af0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1147d90; + .timescale -9 -12; +L_0x2b0ab3d068d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06920 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e65b0/d .functor OR 1, L_0x2b0ab3d068d8, L_0x2b0ab3d06920, C4<0>, C4<0>; +L_0x12e65b0 .delay 1 (30000,30000,30000) L_0x12e65b0/d; +v0x1157ce0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d068d8; 1 drivers +v0x1157dc0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06920; 1 drivers +S_0x1157ea0 .scope generate, "alu_slices[23]" "alu_slices[23]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11580b0 .param/l "i" 0 3 41, +C4<010111>; +S_0x1158170 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1157ea0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -12398,445 +12408,445 @@ S_0x1cc5500 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cc5230; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e493c0/d .functor NOT 1, L_0x1e5c800, C4<0>, C4<0>, C4<0>; -L_0x1e493c0 .delay 1 (10000,10000,10000) L_0x1e493c0/d; -L_0x1e531c0/d .functor NOT 1, L_0x1e52ea0, C4<0>, C4<0>, C4<0>; -L_0x1e531c0 .delay 1 (10000,10000,10000) L_0x1e531c0/d; -L_0x1e54210/d .functor XOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; -L_0x1e54210 .delay 1 (30000,30000,30000) L_0x1e54210/d; -L_0x7f72592db968 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592db9b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e548c0/d .functor OR 1, L_0x7f72592db968, L_0x7f72592db9b0, C4<0>, C4<0>; -L_0x1e548c0 .delay 1 (30000,30000,30000) L_0x1e548c0/d; -L_0x1e54ac0/d .functor AND 1, L_0x1e5c800, L_0x1e52ea0, C4<1>, C4<1>; -L_0x1e54ac0 .delay 1 (30000,30000,30000) L_0x1e54ac0/d; -L_0x1e54b80/d .functor NAND 1, L_0x1e5c800, L_0x1e52ea0, C4<1>, C4<1>; -L_0x1e54b80 .delay 1 (20000,20000,20000) L_0x1e54b80/d; -L_0x1e54ce0/d .functor XOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; -L_0x1e54ce0 .delay 1 (20000,20000,20000) L_0x1e54ce0/d; -L_0x1e55190/d .functor OR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; -L_0x1e55190 .delay 1 (30000,30000,30000) L_0x1e55190/d; -L_0x1e5c700/d .functor NOT 1, L_0x1e58a20, C4<0>, C4<0>, C4<0>; -L_0x1e5c700 .delay 1 (10000,10000,10000) L_0x1e5c700/d; -v0x1cd3c40_0 .net "A", 0 0, L_0x1e5c800; 1 drivers -v0x1cd3d00_0 .net "A_", 0 0, L_0x1e493c0; 1 drivers -v0x1cd3dc0_0 .net "B", 0 0, L_0x1e52ea0; 1 drivers -v0x1cd3e90_0 .net "B_", 0 0, L_0x1e531c0; 1 drivers -v0x1cd3f30_0 .net *"_s12", 0 0, L_0x1e548c0; 1 drivers -v0x1cd4020_0 .net/2s *"_s14", 0 0, L_0x7f72592db968; 1 drivers -v0x1cd40e0_0 .net/2s *"_s16", 0 0, L_0x7f72592db9b0; 1 drivers -v0x1cd41c0_0 .net *"_s18", 0 0, L_0x1e54ac0; 1 drivers -v0x1cd42a0_0 .net *"_s20", 0 0, L_0x1e54b80; 1 drivers -v0x1cd4410_0 .net *"_s22", 0 0, L_0x1e54ce0; 1 drivers -v0x1cd44f0_0 .net *"_s24", 0 0, L_0x1e55190; 1 drivers -o0x7f725932acf8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1cd45d0_0 name=_s30 -o0x7f725932ad28 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1cd46b0_0 name=_s32 -v0x1cd4790_0 .net *"_s8", 0 0, L_0x1e54210; 1 drivers -v0x1cd4870_0 .net "carryin", 0 0, L_0x1e52f40; 1 drivers -v0x1cd4910_0 .net "carryout", 0 0, L_0x1e5c3a0; 1 drivers -v0x1cd49b0_0 .net "carryouts", 7 0, L_0x1ec12a0; 1 drivers -v0x1cd4b60_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cd4c00_0 .net "result", 0 0, L_0x1e58a20; 1 drivers -v0x1cd4cf0_0 .net "results", 7 0, L_0x1e54f60; 1 drivers -v0x1cd4e00_0 .net "zero", 0 0, L_0x1e5c700; 1 drivers -LS_0x1e54f60_0_0 .concat8 [ 1 1 1 1], L_0x1e536e0, L_0x1e53d10, L_0x1e54210, L_0x1e548c0; -LS_0x1e54f60_0_4 .concat8 [ 1 1 1 1], L_0x1e54ac0, L_0x1e54b80, L_0x1e54ce0, L_0x1e55190; -L_0x1e54f60 .concat8 [ 4 4 0 0], LS_0x1e54f60_0_0, LS_0x1e54f60_0_4; -LS_0x1ec12a0_0_0 .concat [ 1 1 1 1], L_0x1e53990, L_0x1e540b0, o0x7f725932acf8, L_0x1e54710; -LS_0x1ec12a0_0_4 .concat [ 4 0 0 0], o0x7f725932ad28; -L_0x1ec12a0 .concat [ 4 4 0 0], LS_0x1ec12a0_0_0, LS_0x1ec12a0_0_4; -S_0x1cc5780 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cc5500; +L_0x12dcbb0/d .functor NOT 1, L_0x12f0130, C4<0>, C4<0>, C4<0>; +L_0x12dcbb0 .delay 1 (10000,10000,10000) L_0x12dcbb0/d; +L_0x12e6a30/d .functor NOT 1, L_0x12e6710, C4<0>, C4<0>, C4<0>; +L_0x12e6a30 .delay 1 (10000,10000,10000) L_0x12e6a30/d; +L_0x12e7a80/d .functor XOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; +L_0x12e7a80 .delay 1 (30000,30000,30000) L_0x12e7a80/d; +L_0x2b0ab3d06968 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d069b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12e8130/d .functor OR 1, L_0x2b0ab3d06968, L_0x2b0ab3d069b0, C4<0>, C4<0>; +L_0x12e8130 .delay 1 (30000,30000,30000) L_0x12e8130/d; +L_0x12e8330/d .functor AND 1, L_0x12f0130, L_0x12e6710, C4<1>, C4<1>; +L_0x12e8330 .delay 1 (30000,30000,30000) L_0x12e8330/d; +L_0x12e83f0/d .functor NAND 1, L_0x12f0130, L_0x12e6710, C4<1>, C4<1>; +L_0x12e83f0 .delay 1 (20000,20000,20000) L_0x12e83f0/d; +L_0x12e8550/d .functor XOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; +L_0x12e8550 .delay 1 (20000,20000,20000) L_0x12e8550/d; +L_0x12e8a00/d .functor OR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; +L_0x12e8a00 .delay 1 (30000,30000,30000) L_0x12e8a00/d; +L_0x12f0030/d .functor NOT 1, L_0x12ec290, C4<0>, C4<0>, C4<0>; +L_0x12f0030 .delay 1 (10000,10000,10000) L_0x12f0030/d; +v0x11668a0_0 .net "A", 0 0, L_0x12f0130; 1 drivers +v0x1166960_0 .net "A_", 0 0, L_0x12dcbb0; 1 drivers +v0x1166a20_0 .net "B", 0 0, L_0x12e6710; 1 drivers +v0x1166af0_0 .net "B_", 0 0, L_0x12e6a30; 1 drivers +v0x1166b90_0 .net *"_s12", 0 0, L_0x12e8130; 1 drivers +v0x1166c80_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06968; 1 drivers +v0x1166d40_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d069b0; 1 drivers +v0x1166e20_0 .net *"_s18", 0 0, L_0x12e8330; 1 drivers +v0x1166f00_0 .net *"_s20", 0 0, L_0x12e83f0; 1 drivers +v0x1167070_0 .net *"_s22", 0 0, L_0x12e8550; 1 drivers +v0x1167150_0 .net *"_s24", 0 0, L_0x12e8a00; 1 drivers +o0x2b0ab3cdbcf8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1167230_0 name=_s30 +o0x2b0ab3cdbd28 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1167310_0 name=_s32 +v0x11673f0_0 .net *"_s8", 0 0, L_0x12e7a80; 1 drivers +v0x11674d0_0 .net "carryin", 0 0, L_0x12e67b0; 1 drivers +v0x1167570_0 .net "carryout", 0 0, L_0x12efcd0; 1 drivers +v0x1167610_0 .net "carryouts", 7 0, L_0x13555d0; 1 drivers +v0x11677c0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1167860_0 .net "result", 0 0, L_0x12ec290; 1 drivers +v0x1167950_0 .net "results", 7 0, L_0x12e87d0; 1 drivers +v0x1167a60_0 .net "zero", 0 0, L_0x12f0030; 1 drivers +LS_0x12e87d0_0_0 .concat8 [ 1 1 1 1], L_0x12e6f50, L_0x12e7580, L_0x12e7a80, L_0x12e8130; +LS_0x12e87d0_0_4 .concat8 [ 1 1 1 1], L_0x12e8330, L_0x12e83f0, L_0x12e8550, L_0x12e8a00; +L_0x12e87d0 .concat8 [ 4 4 0 0], LS_0x12e87d0_0_0, LS_0x12e87d0_0_4; +LS_0x13555d0_0_0 .concat [ 1 1 1 1], L_0x12e7200, L_0x12e7920, o0x2b0ab3cdbcf8, L_0x12e7f80; +LS_0x13555d0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cdbd28; +L_0x13555d0 .concat [ 4 4 0 0], LS_0x13555d0_0_0, LS_0x13555d0_0_4; +S_0x11583f0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1158170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e53990/d .functor OR 1, L_0x1e53470, L_0x1e53830, C4<0>, C4<0>; -L_0x1e53990 .delay 1 (30000,30000,30000) L_0x1e53990/d; -v0x1cc65b0_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers -v0x1cc6670_0 .net "b", 0 0, L_0x1e52ea0; alias, 1 drivers -v0x1cc6740_0 .net "c1", 0 0, L_0x1e53470; 1 drivers -v0x1cc6840_0 .net "c2", 0 0, L_0x1e53830; 1 drivers -v0x1cc6910_0 .net "carryin", 0 0, L_0x1e52f40; alias, 1 drivers -v0x1cc6a00_0 .net "carryout", 0 0, L_0x1e53990; 1 drivers -v0x1cc6aa0_0 .net "s1", 0 0, L_0x1e533b0; 1 drivers -v0x1cc6b90_0 .net "sum", 0 0, L_0x1e536e0; 1 drivers -S_0x1cc59f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cc5780; +L_0x12e7200/d .functor OR 1, L_0x12e6ce0, L_0x12e70a0, C4<0>, C4<0>; +L_0x12e7200 .delay 1 (30000,30000,30000) L_0x12e7200/d; +v0x1159220_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers +v0x11592e0_0 .net "b", 0 0, L_0x12e6710; alias, 1 drivers +v0x11593b0_0 .net "c1", 0 0, L_0x12e6ce0; 1 drivers +v0x11594b0_0 .net "c2", 0 0, L_0x12e70a0; 1 drivers +v0x1159580_0 .net "carryin", 0 0, L_0x12e67b0; alias, 1 drivers +v0x1159670_0 .net "carryout", 0 0, L_0x12e7200; 1 drivers +v0x1159710_0 .net "s1", 0 0, L_0x12e6c20; 1 drivers +v0x1159800_0 .net "sum", 0 0, L_0x12e6f50; 1 drivers +S_0x1158660 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11583f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e533b0/d .functor XOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; -L_0x1e533b0 .delay 1 (30000,30000,30000) L_0x1e533b0/d; -L_0x1e53470/d .functor AND 1, L_0x1e5c800, L_0x1e52ea0, C4<1>, C4<1>; -L_0x1e53470 .delay 1 (30000,30000,30000) L_0x1e53470/d; -v0x1cc5c50_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers -v0x1cc5d30_0 .net "b", 0 0, L_0x1e52ea0; alias, 1 drivers -v0x1cc5df0_0 .net "carryout", 0 0, L_0x1e53470; alias, 1 drivers -v0x1cc5e90_0 .net "sum", 0 0, L_0x1e533b0; alias, 1 drivers -S_0x1cc5fd0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cc5780; +L_0x12e6c20/d .functor XOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; +L_0x12e6c20 .delay 1 (30000,30000,30000) L_0x12e6c20/d; +L_0x12e6ce0/d .functor AND 1, L_0x12f0130, L_0x12e6710, C4<1>, C4<1>; +L_0x12e6ce0 .delay 1 (30000,30000,30000) L_0x12e6ce0/d; +v0x11588c0_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers +v0x11589a0_0 .net "b", 0 0, L_0x12e6710; alias, 1 drivers +v0x1158a60_0 .net "carryout", 0 0, L_0x12e6ce0; alias, 1 drivers +v0x1158b00_0 .net "sum", 0 0, L_0x12e6c20; alias, 1 drivers +S_0x1158c40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11583f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e536e0/d .functor XOR 1, L_0x1e533b0, L_0x1e52f40, C4<0>, C4<0>; -L_0x1e536e0 .delay 1 (30000,30000,30000) L_0x1e536e0/d; -L_0x1e53830/d .functor AND 1, L_0x1e533b0, L_0x1e52f40, C4<1>, C4<1>; -L_0x1e53830 .delay 1 (30000,30000,30000) L_0x1e53830/d; -v0x1cc6230_0 .net "a", 0 0, L_0x1e533b0; alias, 1 drivers -v0x1cc62d0_0 .net "b", 0 0, L_0x1e52f40; alias, 1 drivers -v0x1cc6370_0 .net "carryout", 0 0, L_0x1e53830; alias, 1 drivers -v0x1cc6440_0 .net "sum", 0 0, L_0x1e536e0; alias, 1 drivers -S_0x1cc6c60 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cc5500; +L_0x12e6f50/d .functor XOR 1, L_0x12e6c20, L_0x12e67b0, C4<0>, C4<0>; +L_0x12e6f50 .delay 1 (30000,30000,30000) L_0x12e6f50/d; +L_0x12e70a0/d .functor AND 1, L_0x12e6c20, L_0x12e67b0, C4<1>, C4<1>; +L_0x12e70a0 .delay 1 (30000,30000,30000) L_0x12e70a0/d; +v0x1158ea0_0 .net "a", 0 0, L_0x12e6c20; alias, 1 drivers +v0x1158f40_0 .net "b", 0 0, L_0x12e67b0; alias, 1 drivers +v0x1158fe0_0 .net "carryout", 0 0, L_0x12e70a0; alias, 1 drivers +v0x11590b0_0 .net "sum", 0 0, L_0x12e6f50; alias, 1 drivers +S_0x11598d0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1158170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1ccc050_0 .net "ands", 7 0, L_0x1e5a460; 1 drivers -v0x1ccc160_0 .net "in", 7 0, L_0x1ec12a0; alias, 1 drivers -v0x1ccc220_0 .net "out", 0 0, L_0x1e5c3a0; alias, 1 drivers -v0x1ccc2f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cc6e80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cc6c60; +v0x115ecc0_0 .net "ands", 7 0, L_0x12edcd0; 1 drivers +v0x115edd0_0 .net "in", 7 0, L_0x13555d0; alias, 1 drivers +v0x115ee90_0 .net "out", 0 0, L_0x12efcd0; alias, 1 drivers +v0x115ef60_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1159af0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11598d0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cc95b0_0 .net "A", 7 0, L_0x1ec12a0; alias, 1 drivers -v0x1cc96b0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cc9770_0 .net *"_s0", 0 0, L_0x1e58d80; 1 drivers -v0x1cc9830_0 .net *"_s12", 0 0, L_0x1e596f0; 1 drivers -v0x1cc9910_0 .net *"_s16", 0 0, L_0x1e59a50; 1 drivers -v0x1cc9a40_0 .net *"_s20", 0 0, L_0x1e59d60; 1 drivers -v0x1cc9b20_0 .net *"_s24", 0 0, L_0x1e5a150; 1 drivers -v0x1cc9c00_0 .net *"_s28", 0 0, L_0x1e5a0e0; 1 drivers -v0x1cc9ce0_0 .net *"_s4", 0 0, L_0x1e59090; 1 drivers -v0x1cc9e50_0 .net *"_s8", 0 0, L_0x1e593e0; 1 drivers -v0x1cc9f30_0 .net "out", 7 0, L_0x1e5a460; alias, 1 drivers -L_0x1e58e40 .part L_0x1ec12a0, 0, 1; -L_0x1e58fa0 .part v0x1d6daa0_0, 0, 1; -L_0x1e59150 .part L_0x1ec12a0, 1, 1; -L_0x1e59340 .part v0x1d6daa0_0, 1, 1; -L_0x1e594a0 .part L_0x1ec12a0, 2, 1; -L_0x1e59600 .part v0x1d6daa0_0, 2, 1; -L_0x1e597b0 .part L_0x1ec12a0, 3, 1; -L_0x1e59910 .part v0x1d6daa0_0, 3, 1; -L_0x1e59b10 .part L_0x1ec12a0, 4, 1; -L_0x1e59c70 .part v0x1d6daa0_0, 4, 1; -L_0x1e59dd0 .part L_0x1ec12a0, 5, 1; -L_0x1e5a040 .part v0x1d6daa0_0, 5, 1; -L_0x1e5a210 .part L_0x1ec12a0, 6, 1; -L_0x1e5a370 .part v0x1d6daa0_0, 6, 1; -LS_0x1e5a460_0_0 .concat8 [ 1 1 1 1], L_0x1e58d80, L_0x1e59090, L_0x1e593e0, L_0x1e596f0; -LS_0x1e5a460_0_4 .concat8 [ 1 1 1 1], L_0x1e59a50, L_0x1e59d60, L_0x1e5a150, L_0x1e5a0e0; -L_0x1e5a460 .concat8 [ 4 4 0 0], LS_0x1e5a460_0_0, LS_0x1e5a460_0_4; -L_0x1e5a820 .part L_0x1ec12a0, 7, 1; -L_0x1e5aa10 .part v0x1d6daa0_0, 7, 1; -S_0x1cc70e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc72f0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e58d80/d .functor AND 1, L_0x1e58e40, L_0x1e58fa0, C4<1>, C4<1>; -L_0x1e58d80 .delay 1 (30000,30000,30000) L_0x1e58d80/d; -v0x1cc73d0_0 .net *"_s0", 0 0, L_0x1e58e40; 1 drivers -v0x1cc74b0_0 .net *"_s1", 0 0, L_0x1e58fa0; 1 drivers -S_0x1cc7590 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc77a0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e59090/d .functor AND 1, L_0x1e59150, L_0x1e59340, C4<1>, C4<1>; -L_0x1e59090 .delay 1 (30000,30000,30000) L_0x1e59090/d; -v0x1cc7860_0 .net *"_s0", 0 0, L_0x1e59150; 1 drivers -v0x1cc7940_0 .net *"_s1", 0 0, L_0x1e59340; 1 drivers -S_0x1cc7a20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc7c30 .param/l "i" 0 4 54, +C4<010>; -L_0x1e593e0/d .functor AND 1, L_0x1e594a0, L_0x1e59600, C4<1>, C4<1>; -L_0x1e593e0 .delay 1 (30000,30000,30000) L_0x1e593e0/d; -v0x1cc7cd0_0 .net *"_s0", 0 0, L_0x1e594a0; 1 drivers -v0x1cc7db0_0 .net *"_s1", 0 0, L_0x1e59600; 1 drivers -S_0x1cc7e90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc80a0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e596f0/d .functor AND 1, L_0x1e597b0, L_0x1e59910, C4<1>, C4<1>; -L_0x1e596f0 .delay 1 (30000,30000,30000) L_0x1e596f0/d; -v0x1cc8160_0 .net *"_s0", 0 0, L_0x1e597b0; 1 drivers -v0x1cc8240_0 .net *"_s1", 0 0, L_0x1e59910; 1 drivers -S_0x1cc8320 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc8580 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e59a50/d .functor AND 1, L_0x1e59b10, L_0x1e59c70, C4<1>, C4<1>; -L_0x1e59a50 .delay 1 (30000,30000,30000) L_0x1e59a50/d; -v0x1cc8640_0 .net *"_s0", 0 0, L_0x1e59b10; 1 drivers -v0x1cc8720_0 .net *"_s1", 0 0, L_0x1e59c70; 1 drivers -S_0x1cc8800 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc8a10 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e59d60/d .functor AND 1, L_0x1e59dd0, L_0x1e5a040, C4<1>, C4<1>; -L_0x1e59d60 .delay 1 (30000,30000,30000) L_0x1e59d60/d; -v0x1cc8ad0_0 .net *"_s0", 0 0, L_0x1e59dd0; 1 drivers -v0x1cc8bb0_0 .net *"_s1", 0 0, L_0x1e5a040; 1 drivers -S_0x1cc8c90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc8ea0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e5a150/d .functor AND 1, L_0x1e5a210, L_0x1e5a370, C4<1>, C4<1>; -L_0x1e5a150 .delay 1 (30000,30000,30000) L_0x1e5a150/d; -v0x1cc8f60_0 .net *"_s0", 0 0, L_0x1e5a210; 1 drivers -v0x1cc9040_0 .net *"_s1", 0 0, L_0x1e5a370; 1 drivers -S_0x1cc9120 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cc6e80; - .timescale -9 -12; -P_0x1cc9330 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e5a0e0/d .functor AND 1, L_0x1e5a820, L_0x1e5aa10, C4<1>, C4<1>; -L_0x1e5a0e0 .delay 1 (30000,30000,30000) L_0x1e5a0e0/d; -v0x1cc93f0_0 .net *"_s0", 0 0, L_0x1e5a820; 1 drivers -v0x1cc94d0_0 .net *"_s1", 0 0, L_0x1e5aa10; 1 drivers -S_0x1cca090 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cc6c60; +v0x115c220_0 .net "A", 7 0, L_0x13555d0; alias, 1 drivers +v0x115c320_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x115c3e0_0 .net *"_s0", 0 0, L_0x12ec5f0; 1 drivers +v0x115c4a0_0 .net *"_s12", 0 0, L_0x12ecf60; 1 drivers +v0x115c580_0 .net *"_s16", 0 0, L_0x12ed2c0; 1 drivers +v0x115c6b0_0 .net *"_s20", 0 0, L_0x12ed5d0; 1 drivers +v0x115c790_0 .net *"_s24", 0 0, L_0x12ed9c0; 1 drivers +v0x115c870_0 .net *"_s28", 0 0, L_0x12ed950; 1 drivers +v0x115c950_0 .net *"_s4", 0 0, L_0x12ec900; 1 drivers +v0x115cac0_0 .net *"_s8", 0 0, L_0x12ecc50; 1 drivers +v0x115cba0_0 .net "out", 7 0, L_0x12edcd0; alias, 1 drivers +L_0x12ec6b0 .part L_0x13555d0, 0, 1; +L_0x12ec810 .part v0x12010b0_0, 0, 1; +L_0x12ec9c0 .part L_0x13555d0, 1, 1; +L_0x12ecbb0 .part v0x12010b0_0, 1, 1; +L_0x12ecd10 .part L_0x13555d0, 2, 1; +L_0x12ece70 .part v0x12010b0_0, 2, 1; +L_0x12ed020 .part L_0x13555d0, 3, 1; +L_0x12ed180 .part v0x12010b0_0, 3, 1; +L_0x12ed380 .part L_0x13555d0, 4, 1; +L_0x12ed4e0 .part v0x12010b0_0, 4, 1; +L_0x12ed640 .part L_0x13555d0, 5, 1; +L_0x12ed8b0 .part v0x12010b0_0, 5, 1; +L_0x12eda80 .part L_0x13555d0, 6, 1; +L_0x12edbe0 .part v0x12010b0_0, 6, 1; +LS_0x12edcd0_0_0 .concat8 [ 1 1 1 1], L_0x12ec5f0, L_0x12ec900, L_0x12ecc50, L_0x12ecf60; +LS_0x12edcd0_0_4 .concat8 [ 1 1 1 1], L_0x12ed2c0, L_0x12ed5d0, L_0x12ed9c0, L_0x12ed950; +L_0x12edcd0 .concat8 [ 4 4 0 0], LS_0x12edcd0_0_0, LS_0x12edcd0_0_4; +L_0x12ee090 .part L_0x13555d0, 7, 1; +L_0x12ee280 .part v0x12010b0_0, 7, 1; +S_0x1159d50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x1159f60 .param/l "i" 0 4 54, +C4<00>; +L_0x12ec5f0/d .functor AND 1, L_0x12ec6b0, L_0x12ec810, C4<1>, C4<1>; +L_0x12ec5f0 .delay 1 (30000,30000,30000) L_0x12ec5f0/d; +v0x115a040_0 .net *"_s0", 0 0, L_0x12ec6b0; 1 drivers +v0x115a120_0 .net *"_s1", 0 0, L_0x12ec810; 1 drivers +S_0x115a200 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115a410 .param/l "i" 0 4 54, +C4<01>; +L_0x12ec900/d .functor AND 1, L_0x12ec9c0, L_0x12ecbb0, C4<1>, C4<1>; +L_0x12ec900 .delay 1 (30000,30000,30000) L_0x12ec900/d; +v0x115a4d0_0 .net *"_s0", 0 0, L_0x12ec9c0; 1 drivers +v0x115a5b0_0 .net *"_s1", 0 0, L_0x12ecbb0; 1 drivers +S_0x115a690 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115a8a0 .param/l "i" 0 4 54, +C4<010>; +L_0x12ecc50/d .functor AND 1, L_0x12ecd10, L_0x12ece70, C4<1>, C4<1>; +L_0x12ecc50 .delay 1 (30000,30000,30000) L_0x12ecc50/d; +v0x115a940_0 .net *"_s0", 0 0, L_0x12ecd10; 1 drivers +v0x115aa20_0 .net *"_s1", 0 0, L_0x12ece70; 1 drivers +S_0x115ab00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115ad10 .param/l "i" 0 4 54, +C4<011>; +L_0x12ecf60/d .functor AND 1, L_0x12ed020, L_0x12ed180, C4<1>, C4<1>; +L_0x12ecf60 .delay 1 (30000,30000,30000) L_0x12ecf60/d; +v0x115add0_0 .net *"_s0", 0 0, L_0x12ed020; 1 drivers +v0x115aeb0_0 .net *"_s1", 0 0, L_0x12ed180; 1 drivers +S_0x115af90 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115b1f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12ed2c0/d .functor AND 1, L_0x12ed380, L_0x12ed4e0, C4<1>, C4<1>; +L_0x12ed2c0 .delay 1 (30000,30000,30000) L_0x12ed2c0/d; +v0x115b2b0_0 .net *"_s0", 0 0, L_0x12ed380; 1 drivers +v0x115b390_0 .net *"_s1", 0 0, L_0x12ed4e0; 1 drivers +S_0x115b470 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115b680 .param/l "i" 0 4 54, +C4<0101>; +L_0x12ed5d0/d .functor AND 1, L_0x12ed640, L_0x12ed8b0, C4<1>, C4<1>; +L_0x12ed5d0 .delay 1 (30000,30000,30000) L_0x12ed5d0/d; +v0x115b740_0 .net *"_s0", 0 0, L_0x12ed640; 1 drivers +v0x115b820_0 .net *"_s1", 0 0, L_0x12ed8b0; 1 drivers +S_0x115b900 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115bb10 .param/l "i" 0 4 54, +C4<0110>; +L_0x12ed9c0/d .functor AND 1, L_0x12eda80, L_0x12edbe0, C4<1>, C4<1>; +L_0x12ed9c0 .delay 1 (30000,30000,30000) L_0x12ed9c0/d; +v0x115bbd0_0 .net *"_s0", 0 0, L_0x12eda80; 1 drivers +v0x115bcb0_0 .net *"_s1", 0 0, L_0x12edbe0; 1 drivers +S_0x115bd90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1159af0; + .timescale -9 -12; +P_0x115bfa0 .param/l "i" 0 4 54, +C4<0111>; +L_0x12ed950/d .functor AND 1, L_0x12ee090, L_0x12ee280, C4<1>, C4<1>; +L_0x12ed950 .delay 1 (30000,30000,30000) L_0x12ed950/d; +v0x115c060_0 .net *"_s0", 0 0, L_0x12ee090; 1 drivers +v0x115c140_0 .net *"_s1", 0 0, L_0x12ee280; 1 drivers +S_0x115cd00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11598d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e5c3a0/d .functor OR 1, L_0x1e5c460, L_0x1e5c610, C4<0>, C4<0>; -L_0x1e5c3a0 .delay 1 (30000,30000,30000) L_0x1e5c3a0/d; -v0x1ccbbe0_0 .net *"_s10", 0 0, L_0x1e5c460; 1 drivers -v0x1ccbcc0_0 .net *"_s12", 0 0, L_0x1e5c610; 1 drivers -v0x1ccbda0_0 .net "in", 7 0, L_0x1e5a460; alias, 1 drivers -v0x1ccbe70_0 .net "ors", 1 0, L_0x1e5c1c0; 1 drivers -v0x1ccbf30_0 .net "out", 0 0, L_0x1e5c3a0; alias, 1 drivers -L_0x1e5b650 .part L_0x1e5a460, 0, 4; -L_0x1e5c1c0 .concat8 [ 1 1 0 0], L_0x1e5b340, L_0x1e5bf70; -L_0x1e5c300 .part L_0x1e5a460, 4, 4; -L_0x1e5c460 .part L_0x1e5c1c0, 0, 1; -L_0x1e5c610 .part L_0x1e5c1c0, 1, 1; -S_0x1cca250 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cca090; +L_0x12efcd0/d .functor OR 1, L_0x12efd90, L_0x12eff40, C4<0>, C4<0>; +L_0x12efcd0 .delay 1 (30000,30000,30000) L_0x12efcd0/d; +v0x115e850_0 .net *"_s10", 0 0, L_0x12efd90; 1 drivers +v0x115e930_0 .net *"_s12", 0 0, L_0x12eff40; 1 drivers +v0x115ea10_0 .net "in", 7 0, L_0x12edcd0; alias, 1 drivers +v0x115eae0_0 .net "ors", 1 0, L_0x12efaf0; 1 drivers +v0x115eba0_0 .net "out", 0 0, L_0x12efcd0; alias, 1 drivers +L_0x12eeec0 .part L_0x12edcd0, 0, 4; +L_0x12efaf0 .concat8 [ 1 1 0 0], L_0x12eebb0, L_0x12ef7e0; +L_0x12efc30 .part L_0x12edcd0, 4, 4; +L_0x12efd90 .part L_0x12efaf0, 0, 1; +L_0x12eff40 .part L_0x12efaf0, 1, 1; +S_0x115cec0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x115cd00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e5ab00/d .functor OR 1, L_0x1e5abc0, L_0x1e5ad20, C4<0>, C4<0>; -L_0x1e5ab00 .delay 1 (30000,30000,30000) L_0x1e5ab00/d; -L_0x1e5af50/d .functor OR 1, L_0x1e5b060, L_0x1e5b1c0, C4<0>, C4<0>; -L_0x1e5af50 .delay 1 (30000,30000,30000) L_0x1e5af50/d; -L_0x1e5b340/d .functor OR 1, L_0x1e5b3b0, L_0x1e5b560, C4<0>, C4<0>; -L_0x1e5b340 .delay 1 (30000,30000,30000) L_0x1e5b340/d; -v0x1cca4a0_0 .net *"_s0", 0 0, L_0x1e5ab00; 1 drivers -v0x1cca5a0_0 .net *"_s10", 0 0, L_0x1e5b060; 1 drivers -v0x1cca680_0 .net *"_s12", 0 0, L_0x1e5b1c0; 1 drivers -v0x1cca740_0 .net *"_s14", 0 0, L_0x1e5b3b0; 1 drivers -v0x1cca820_0 .net *"_s16", 0 0, L_0x1e5b560; 1 drivers -v0x1cca950_0 .net *"_s3", 0 0, L_0x1e5abc0; 1 drivers -v0x1ccaa30_0 .net *"_s5", 0 0, L_0x1e5ad20; 1 drivers -v0x1ccab10_0 .net *"_s6", 0 0, L_0x1e5af50; 1 drivers -v0x1ccabf0_0 .net "in", 3 0, L_0x1e5b650; 1 drivers -v0x1ccad60_0 .net "ors", 1 0, L_0x1e5ae60; 1 drivers -v0x1ccae40_0 .net "out", 0 0, L_0x1e5b340; 1 drivers -L_0x1e5abc0 .part L_0x1e5b650, 0, 1; -L_0x1e5ad20 .part L_0x1e5b650, 1, 1; -L_0x1e5ae60 .concat8 [ 1 1 0 0], L_0x1e5ab00, L_0x1e5af50; -L_0x1e5b060 .part L_0x1e5b650, 2, 1; -L_0x1e5b1c0 .part L_0x1e5b650, 3, 1; -L_0x1e5b3b0 .part L_0x1e5ae60, 0, 1; -L_0x1e5b560 .part L_0x1e5ae60, 1, 1; -S_0x1ccaf60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cca090; +L_0x12ee370/d .functor OR 1, L_0x12ee430, L_0x12ee590, C4<0>, C4<0>; +L_0x12ee370 .delay 1 (30000,30000,30000) L_0x12ee370/d; +L_0x12ee7c0/d .functor OR 1, L_0x12ee8d0, L_0x12eea30, C4<0>, C4<0>; +L_0x12ee7c0 .delay 1 (30000,30000,30000) L_0x12ee7c0/d; +L_0x12eebb0/d .functor OR 1, L_0x12eec20, L_0x12eedd0, C4<0>, C4<0>; +L_0x12eebb0 .delay 1 (30000,30000,30000) L_0x12eebb0/d; +v0x115d110_0 .net *"_s0", 0 0, L_0x12ee370; 1 drivers +v0x115d210_0 .net *"_s10", 0 0, L_0x12ee8d0; 1 drivers +v0x115d2f0_0 .net *"_s12", 0 0, L_0x12eea30; 1 drivers +v0x115d3b0_0 .net *"_s14", 0 0, L_0x12eec20; 1 drivers +v0x115d490_0 .net *"_s16", 0 0, L_0x12eedd0; 1 drivers +v0x115d5c0_0 .net *"_s3", 0 0, L_0x12ee430; 1 drivers +v0x115d6a0_0 .net *"_s5", 0 0, L_0x12ee590; 1 drivers +v0x115d780_0 .net *"_s6", 0 0, L_0x12ee7c0; 1 drivers +v0x115d860_0 .net "in", 3 0, L_0x12eeec0; 1 drivers +v0x115d9d0_0 .net "ors", 1 0, L_0x12ee6d0; 1 drivers +v0x115dab0_0 .net "out", 0 0, L_0x12eebb0; 1 drivers +L_0x12ee430 .part L_0x12eeec0, 0, 1; +L_0x12ee590 .part L_0x12eeec0, 1, 1; +L_0x12ee6d0 .concat8 [ 1 1 0 0], L_0x12ee370, L_0x12ee7c0; +L_0x12ee8d0 .part L_0x12eeec0, 2, 1; +L_0x12eea30 .part L_0x12eeec0, 3, 1; +L_0x12eec20 .part L_0x12ee6d0, 0, 1; +L_0x12eedd0 .part L_0x12ee6d0, 1, 1; +S_0x115dbd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x115cd00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e5b780/d .functor OR 1, L_0x1e5b7f0, L_0x1e5b950, C4<0>, C4<0>; -L_0x1e5b780 .delay 1 (30000,30000,30000) L_0x1e5b780/d; -L_0x1e5bb80/d .functor OR 1, L_0x1e5bc90, L_0x1e5bdf0, C4<0>, C4<0>; -L_0x1e5bb80 .delay 1 (30000,30000,30000) L_0x1e5bb80/d; -L_0x1e5bf70/d .functor OR 1, L_0x1e5bfe0, L_0x1e5c0d0, C4<0>, C4<0>; -L_0x1e5bf70 .delay 1 (30000,30000,30000) L_0x1e5bf70/d; -v0x1ccb120_0 .net *"_s0", 0 0, L_0x1e5b780; 1 drivers -v0x1ccb220_0 .net *"_s10", 0 0, L_0x1e5bc90; 1 drivers -v0x1ccb300_0 .net *"_s12", 0 0, L_0x1e5bdf0; 1 drivers -v0x1ccb3c0_0 .net *"_s14", 0 0, L_0x1e5bfe0; 1 drivers -v0x1ccb4a0_0 .net *"_s16", 0 0, L_0x1e5c0d0; 1 drivers -v0x1ccb5d0_0 .net *"_s3", 0 0, L_0x1e5b7f0; 1 drivers -v0x1ccb6b0_0 .net *"_s5", 0 0, L_0x1e5b950; 1 drivers -v0x1ccb790_0 .net *"_s6", 0 0, L_0x1e5bb80; 1 drivers -v0x1ccb870_0 .net "in", 3 0, L_0x1e5c300; 1 drivers -v0x1ccb9e0_0 .net "ors", 1 0, L_0x1e5ba90; 1 drivers -v0x1ccbac0_0 .net "out", 0 0, L_0x1e5bf70; 1 drivers -L_0x1e5b7f0 .part L_0x1e5c300, 0, 1; -L_0x1e5b950 .part L_0x1e5c300, 1, 1; -L_0x1e5ba90 .concat8 [ 1 1 0 0], L_0x1e5b780, L_0x1e5bb80; -L_0x1e5bc90 .part L_0x1e5c300, 2, 1; -L_0x1e5bdf0 .part L_0x1e5c300, 3, 1; -L_0x1e5bfe0 .part L_0x1e5ba90, 0, 1; -L_0x1e5c0d0 .part L_0x1e5ba90, 1, 1; -S_0x1ccc3d0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cc5500; +L_0x12eeff0/d .functor OR 1, L_0x12ef060, L_0x12ef1c0, C4<0>, C4<0>; +L_0x12eeff0 .delay 1 (30000,30000,30000) L_0x12eeff0/d; +L_0x12ef3f0/d .functor OR 1, L_0x12ef500, L_0x12ef660, C4<0>, C4<0>; +L_0x12ef3f0 .delay 1 (30000,30000,30000) L_0x12ef3f0/d; +L_0x12ef7e0/d .functor OR 1, L_0x12ef850, L_0x12efa00, C4<0>, C4<0>; +L_0x12ef7e0 .delay 1 (30000,30000,30000) L_0x12ef7e0/d; +v0x115dd90_0 .net *"_s0", 0 0, L_0x12eeff0; 1 drivers +v0x115de90_0 .net *"_s10", 0 0, L_0x12ef500; 1 drivers +v0x115df70_0 .net *"_s12", 0 0, L_0x12ef660; 1 drivers +v0x115e030_0 .net *"_s14", 0 0, L_0x12ef850; 1 drivers +v0x115e110_0 .net *"_s16", 0 0, L_0x12efa00; 1 drivers +v0x115e240_0 .net *"_s3", 0 0, L_0x12ef060; 1 drivers +v0x115e320_0 .net *"_s5", 0 0, L_0x12ef1c0; 1 drivers +v0x115e400_0 .net *"_s6", 0 0, L_0x12ef3f0; 1 drivers +v0x115e4e0_0 .net "in", 3 0, L_0x12efc30; 1 drivers +v0x115e650_0 .net "ors", 1 0, L_0x12ef300; 1 drivers +v0x115e730_0 .net "out", 0 0, L_0x12ef7e0; 1 drivers +L_0x12ef060 .part L_0x12efc30, 0, 1; +L_0x12ef1c0 .part L_0x12efc30, 1, 1; +L_0x12ef300 .concat8 [ 1 1 0 0], L_0x12eeff0, L_0x12ef3f0; +L_0x12ef500 .part L_0x12efc30, 2, 1; +L_0x12ef660 .part L_0x12efc30, 3, 1; +L_0x12ef850 .part L_0x12ef300, 0, 1; +L_0x12efa00 .part L_0x12ef300, 1, 1; +S_0x115f040 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1158170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cd1800_0 .net "ands", 7 0, L_0x1e56a20; 1 drivers -v0x1cd1910_0 .net "in", 7 0, L_0x1e54f60; alias, 1 drivers -v0x1cd19d0_0 .net "out", 0 0, L_0x1e58a20; alias, 1 drivers -v0x1cd1aa0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1ccc620 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ccc3d0; +v0x1164470_0 .net "ands", 7 0, L_0x12ea290; 1 drivers +v0x1164580_0 .net "in", 7 0, L_0x12e87d0; alias, 1 drivers +v0x1164640_0 .net "out", 0 0, L_0x12ec290; alias, 1 drivers +v0x1164710_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x115f290 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x115f040; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cced60_0 .net "A", 7 0, L_0x1e54f60; alias, 1 drivers -v0x1ccee60_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ccef20_0 .net *"_s0", 0 0, L_0x1e552f0; 1 drivers -v0x1ccefe0_0 .net *"_s12", 0 0, L_0x1e55cb0; 1 drivers -v0x1ccf0c0_0 .net *"_s16", 0 0, L_0x1e56010; 1 drivers -v0x1ccf1f0_0 .net *"_s20", 0 0, L_0x1e563e0; 1 drivers -v0x1ccf2d0_0 .net *"_s24", 0 0, L_0x1e56710; 1 drivers -v0x1ccf3b0_0 .net *"_s28", 0 0, L_0x1e566a0; 1 drivers -v0x1ccf490_0 .net *"_s4", 0 0, L_0x1e55690; 1 drivers -v0x1ccf600_0 .net *"_s8", 0 0, L_0x1e559a0; 1 drivers -v0x1ccf6e0_0 .net "out", 7 0, L_0x1e56a20; alias, 1 drivers -L_0x1e55400 .part L_0x1e54f60, 0, 1; -L_0x1e555f0 .part v0x1d6daa0_0, 0, 1; -L_0x1e55750 .part L_0x1e54f60, 1, 1; -L_0x1e558b0 .part v0x1d6daa0_0, 1, 1; -L_0x1e55a60 .part L_0x1e54f60, 2, 1; -L_0x1e55bc0 .part v0x1d6daa0_0, 2, 1; -L_0x1e55d70 .part L_0x1e54f60, 3, 1; -L_0x1e55ed0 .part v0x1d6daa0_0, 3, 1; -L_0x1e560d0 .part L_0x1e54f60, 4, 1; -L_0x1e56340 .part v0x1d6daa0_0, 4, 1; -L_0x1e56450 .part L_0x1e54f60, 5, 1; -L_0x1e565b0 .part v0x1d6daa0_0, 5, 1; -L_0x1e567d0 .part L_0x1e54f60, 6, 1; -L_0x1e56930 .part v0x1d6daa0_0, 6, 1; -LS_0x1e56a20_0_0 .concat8 [ 1 1 1 1], L_0x1e552f0, L_0x1e55690, L_0x1e559a0, L_0x1e55cb0; -LS_0x1e56a20_0_4 .concat8 [ 1 1 1 1], L_0x1e56010, L_0x1e563e0, L_0x1e56710, L_0x1e566a0; -L_0x1e56a20 .concat8 [ 4 4 0 0], LS_0x1e56a20_0_0, LS_0x1e56a20_0_4; -L_0x1e56de0 .part L_0x1e54f60, 7, 1; -L_0x1e56fd0 .part v0x1d6daa0_0, 7, 1; -S_0x1ccc860 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1ccca70 .param/l "i" 0 4 54, +C4<00>; -L_0x1e552f0/d .functor AND 1, L_0x1e55400, L_0x1e555f0, C4<1>, C4<1>; -L_0x1e552f0 .delay 1 (30000,30000,30000) L_0x1e552f0/d; -v0x1cccb50_0 .net *"_s0", 0 0, L_0x1e55400; 1 drivers -v0x1cccc30_0 .net *"_s1", 0 0, L_0x1e555f0; 1 drivers -S_0x1cccd10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1cccf20 .param/l "i" 0 4 54, +C4<01>; -L_0x1e55690/d .functor AND 1, L_0x1e55750, L_0x1e558b0, C4<1>, C4<1>; -L_0x1e55690 .delay 1 (30000,30000,30000) L_0x1e55690/d; -v0x1cccfe0_0 .net *"_s0", 0 0, L_0x1e55750; 1 drivers -v0x1ccd0c0_0 .net *"_s1", 0 0, L_0x1e558b0; 1 drivers -S_0x1ccd1a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1ccd3e0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e559a0/d .functor AND 1, L_0x1e55a60, L_0x1e55bc0, C4<1>, C4<1>; -L_0x1e559a0 .delay 1 (30000,30000,30000) L_0x1e559a0/d; -v0x1ccd480_0 .net *"_s0", 0 0, L_0x1e55a60; 1 drivers -v0x1ccd560_0 .net *"_s1", 0 0, L_0x1e55bc0; 1 drivers -S_0x1ccd640 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1ccd850 .param/l "i" 0 4 54, +C4<011>; -L_0x1e55cb0/d .functor AND 1, L_0x1e55d70, L_0x1e55ed0, C4<1>, C4<1>; -L_0x1e55cb0 .delay 1 (30000,30000,30000) L_0x1e55cb0/d; -v0x1ccd910_0 .net *"_s0", 0 0, L_0x1e55d70; 1 drivers -v0x1ccd9f0_0 .net *"_s1", 0 0, L_0x1e55ed0; 1 drivers -S_0x1ccdad0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1ccdd30 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e56010/d .functor AND 1, L_0x1e560d0, L_0x1e56340, C4<1>, C4<1>; -L_0x1e56010 .delay 1 (30000,30000,30000) L_0x1e56010/d; -v0x1ccddf0_0 .net *"_s0", 0 0, L_0x1e560d0; 1 drivers -v0x1ccded0_0 .net *"_s1", 0 0, L_0x1e56340; 1 drivers -S_0x1ccdfb0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1cce1c0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e563e0/d .functor AND 1, L_0x1e56450, L_0x1e565b0, C4<1>, C4<1>; -L_0x1e563e0 .delay 1 (30000,30000,30000) L_0x1e563e0/d; -v0x1cce280_0 .net *"_s0", 0 0, L_0x1e56450; 1 drivers -v0x1cce360_0 .net *"_s1", 0 0, L_0x1e565b0; 1 drivers -S_0x1cce440 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1cce650 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e56710/d .functor AND 1, L_0x1e567d0, L_0x1e56930, C4<1>, C4<1>; -L_0x1e56710 .delay 1 (30000,30000,30000) L_0x1e56710/d; -v0x1cce710_0 .net *"_s0", 0 0, L_0x1e567d0; 1 drivers -v0x1cce7f0_0 .net *"_s1", 0 0, L_0x1e56930; 1 drivers -S_0x1cce8d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ccc620; - .timescale -9 -12; -P_0x1cceae0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e566a0/d .functor AND 1, L_0x1e56de0, L_0x1e56fd0, C4<1>, C4<1>; -L_0x1e566a0 .delay 1 (30000,30000,30000) L_0x1e566a0/d; -v0x1cceba0_0 .net *"_s0", 0 0, L_0x1e56de0; 1 drivers -v0x1ccec80_0 .net *"_s1", 0 0, L_0x1e56fd0; 1 drivers -S_0x1ccf840 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ccc3d0; +v0x11619d0_0 .net "A", 7 0, L_0x12e87d0; alias, 1 drivers +v0x1161ad0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1161b90_0 .net *"_s0", 0 0, L_0x12e8b60; 1 drivers +v0x1161c50_0 .net *"_s12", 0 0, L_0x12e9520; 1 drivers +v0x1161d30_0 .net *"_s16", 0 0, L_0x12e9880; 1 drivers +v0x1161e60_0 .net *"_s20", 0 0, L_0x12e9c50; 1 drivers +v0x1161f40_0 .net *"_s24", 0 0, L_0x12e9f80; 1 drivers +v0x1162020_0 .net *"_s28", 0 0, L_0x12e9f10; 1 drivers +v0x1162100_0 .net *"_s4", 0 0, L_0x12e8f00; 1 drivers +v0x1162270_0 .net *"_s8", 0 0, L_0x12e9210; 1 drivers +v0x1162350_0 .net "out", 7 0, L_0x12ea290; alias, 1 drivers +L_0x12e8c70 .part L_0x12e87d0, 0, 1; +L_0x12e8e60 .part v0x12010b0_0, 0, 1; +L_0x12e8fc0 .part L_0x12e87d0, 1, 1; +L_0x12e9120 .part v0x12010b0_0, 1, 1; +L_0x12e92d0 .part L_0x12e87d0, 2, 1; +L_0x12e9430 .part v0x12010b0_0, 2, 1; +L_0x12e95e0 .part L_0x12e87d0, 3, 1; +L_0x12e9740 .part v0x12010b0_0, 3, 1; +L_0x12e9940 .part L_0x12e87d0, 4, 1; +L_0x12e9bb0 .part v0x12010b0_0, 4, 1; +L_0x12e9cc0 .part L_0x12e87d0, 5, 1; +L_0x12e9e20 .part v0x12010b0_0, 5, 1; +L_0x12ea040 .part L_0x12e87d0, 6, 1; +L_0x12ea1a0 .part v0x12010b0_0, 6, 1; +LS_0x12ea290_0_0 .concat8 [ 1 1 1 1], L_0x12e8b60, L_0x12e8f00, L_0x12e9210, L_0x12e9520; +LS_0x12ea290_0_4 .concat8 [ 1 1 1 1], L_0x12e9880, L_0x12e9c50, L_0x12e9f80, L_0x12e9f10; +L_0x12ea290 .concat8 [ 4 4 0 0], LS_0x12ea290_0_0, LS_0x12ea290_0_4; +L_0x12ea650 .part L_0x12e87d0, 7, 1; +L_0x12ea840 .part v0x12010b0_0, 7, 1; +S_0x115f4d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x115f6e0 .param/l "i" 0 4 54, +C4<00>; +L_0x12e8b60/d .functor AND 1, L_0x12e8c70, L_0x12e8e60, C4<1>, C4<1>; +L_0x12e8b60 .delay 1 (30000,30000,30000) L_0x12e8b60/d; +v0x115f7c0_0 .net *"_s0", 0 0, L_0x12e8c70; 1 drivers +v0x115f8a0_0 .net *"_s1", 0 0, L_0x12e8e60; 1 drivers +S_0x115f980 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x115fb90 .param/l "i" 0 4 54, +C4<01>; +L_0x12e8f00/d .functor AND 1, L_0x12e8fc0, L_0x12e9120, C4<1>, C4<1>; +L_0x12e8f00 .delay 1 (30000,30000,30000) L_0x12e8f00/d; +v0x115fc50_0 .net *"_s0", 0 0, L_0x12e8fc0; 1 drivers +v0x115fd30_0 .net *"_s1", 0 0, L_0x12e9120; 1 drivers +S_0x115fe10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x1160050 .param/l "i" 0 4 54, +C4<010>; +L_0x12e9210/d .functor AND 1, L_0x12e92d0, L_0x12e9430, C4<1>, C4<1>; +L_0x12e9210 .delay 1 (30000,30000,30000) L_0x12e9210/d; +v0x11600f0_0 .net *"_s0", 0 0, L_0x12e92d0; 1 drivers +v0x11601d0_0 .net *"_s1", 0 0, L_0x12e9430; 1 drivers +S_0x11602b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x11604c0 .param/l "i" 0 4 54, +C4<011>; +L_0x12e9520/d .functor AND 1, L_0x12e95e0, L_0x12e9740, C4<1>, C4<1>; +L_0x12e9520 .delay 1 (30000,30000,30000) L_0x12e9520/d; +v0x1160580_0 .net *"_s0", 0 0, L_0x12e95e0; 1 drivers +v0x1160660_0 .net *"_s1", 0 0, L_0x12e9740; 1 drivers +S_0x1160740 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x11609a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12e9880/d .functor AND 1, L_0x12e9940, L_0x12e9bb0, C4<1>, C4<1>; +L_0x12e9880 .delay 1 (30000,30000,30000) L_0x12e9880/d; +v0x1160a60_0 .net *"_s0", 0 0, L_0x12e9940; 1 drivers +v0x1160b40_0 .net *"_s1", 0 0, L_0x12e9bb0; 1 drivers +S_0x1160c20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x1160e30 .param/l "i" 0 4 54, +C4<0101>; +L_0x12e9c50/d .functor AND 1, L_0x12e9cc0, L_0x12e9e20, C4<1>, C4<1>; +L_0x12e9c50 .delay 1 (30000,30000,30000) L_0x12e9c50/d; +v0x1160ef0_0 .net *"_s0", 0 0, L_0x12e9cc0; 1 drivers +v0x1160fd0_0 .net *"_s1", 0 0, L_0x12e9e20; 1 drivers +S_0x11610b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x11612c0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12e9f80/d .functor AND 1, L_0x12ea040, L_0x12ea1a0, C4<1>, C4<1>; +L_0x12e9f80 .delay 1 (30000,30000,30000) L_0x12e9f80/d; +v0x1161380_0 .net *"_s0", 0 0, L_0x12ea040; 1 drivers +v0x1161460_0 .net *"_s1", 0 0, L_0x12ea1a0; 1 drivers +S_0x1161540 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x115f290; + .timescale -9 -12; +P_0x1161750 .param/l "i" 0 4 54, +C4<0111>; +L_0x12e9f10/d .functor AND 1, L_0x12ea650, L_0x12ea840, C4<1>, C4<1>; +L_0x12e9f10 .delay 1 (30000,30000,30000) L_0x12e9f10/d; +v0x1161810_0 .net *"_s0", 0 0, L_0x12ea650; 1 drivers +v0x11618f0_0 .net *"_s1", 0 0, L_0x12ea840; 1 drivers +S_0x11624b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x115f040; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e58a20/d .functor OR 1, L_0x1e58ae0, L_0x1e58c90, C4<0>, C4<0>; -L_0x1e58a20 .delay 1 (30000,30000,30000) L_0x1e58a20/d; -v0x1cd1390_0 .net *"_s10", 0 0, L_0x1e58ae0; 1 drivers -v0x1cd1470_0 .net *"_s12", 0 0, L_0x1e58c90; 1 drivers -v0x1cd1550_0 .net "in", 7 0, L_0x1e56a20; alias, 1 drivers -v0x1cd1620_0 .net "ors", 1 0, L_0x1e58840; 1 drivers -v0x1cd16e0_0 .net "out", 0 0, L_0x1e58a20; alias, 1 drivers -L_0x1e57c10 .part L_0x1e56a20, 0, 4; -L_0x1e58840 .concat8 [ 1 1 0 0], L_0x1e57900, L_0x1e58530; -L_0x1e58980 .part L_0x1e56a20, 4, 4; -L_0x1e58ae0 .part L_0x1e58840, 0, 1; -L_0x1e58c90 .part L_0x1e58840, 1, 1; -S_0x1ccfa00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1ccf840; +L_0x12ec290/d .functor OR 1, L_0x12ec350, L_0x12ec500, C4<0>, C4<0>; +L_0x12ec290 .delay 1 (30000,30000,30000) L_0x12ec290/d; +v0x1164000_0 .net *"_s10", 0 0, L_0x12ec350; 1 drivers +v0x11640e0_0 .net *"_s12", 0 0, L_0x12ec500; 1 drivers +v0x11641c0_0 .net "in", 7 0, L_0x12ea290; alias, 1 drivers +v0x1164290_0 .net "ors", 1 0, L_0x12ec0b0; 1 drivers +v0x1164350_0 .net "out", 0 0, L_0x12ec290; alias, 1 drivers +L_0x12eb480 .part L_0x12ea290, 0, 4; +L_0x12ec0b0 .concat8 [ 1 1 0 0], L_0x12eb170, L_0x12ebda0; +L_0x12ec1f0 .part L_0x12ea290, 4, 4; +L_0x12ec350 .part L_0x12ec0b0, 0, 1; +L_0x12ec500 .part L_0x12ec0b0, 1, 1; +S_0x1162670 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11624b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e570c0/d .functor OR 1, L_0x1e57180, L_0x1e572e0, C4<0>, C4<0>; -L_0x1e570c0 .delay 1 (30000,30000,30000) L_0x1e570c0/d; -L_0x1e57510/d .functor OR 1, L_0x1e57620, L_0x1e57780, C4<0>, C4<0>; -L_0x1e57510 .delay 1 (30000,30000,30000) L_0x1e57510/d; -L_0x1e57900/d .functor OR 1, L_0x1e57970, L_0x1e57b20, C4<0>, C4<0>; -L_0x1e57900 .delay 1 (30000,30000,30000) L_0x1e57900/d; -v0x1ccfc50_0 .net *"_s0", 0 0, L_0x1e570c0; 1 drivers -v0x1ccfd50_0 .net *"_s10", 0 0, L_0x1e57620; 1 drivers -v0x1ccfe30_0 .net *"_s12", 0 0, L_0x1e57780; 1 drivers -v0x1ccfef0_0 .net *"_s14", 0 0, L_0x1e57970; 1 drivers -v0x1ccffd0_0 .net *"_s16", 0 0, L_0x1e57b20; 1 drivers -v0x1cd0100_0 .net *"_s3", 0 0, L_0x1e57180; 1 drivers -v0x1cd01e0_0 .net *"_s5", 0 0, L_0x1e572e0; 1 drivers -v0x1cd02c0_0 .net *"_s6", 0 0, L_0x1e57510; 1 drivers -v0x1cd03a0_0 .net "in", 3 0, L_0x1e57c10; 1 drivers -v0x1cd0510_0 .net "ors", 1 0, L_0x1e57420; 1 drivers -v0x1cd05f0_0 .net "out", 0 0, L_0x1e57900; 1 drivers -L_0x1e57180 .part L_0x1e57c10, 0, 1; -L_0x1e572e0 .part L_0x1e57c10, 1, 1; -L_0x1e57420 .concat8 [ 1 1 0 0], L_0x1e570c0, L_0x1e57510; -L_0x1e57620 .part L_0x1e57c10, 2, 1; -L_0x1e57780 .part L_0x1e57c10, 3, 1; -L_0x1e57970 .part L_0x1e57420, 0, 1; -L_0x1e57b20 .part L_0x1e57420, 1, 1; -S_0x1cd0710 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1ccf840; +L_0x12ea930/d .functor OR 1, L_0x12ea9f0, L_0x12eab50, C4<0>, C4<0>; +L_0x12ea930 .delay 1 (30000,30000,30000) L_0x12ea930/d; +L_0x12ead80/d .functor OR 1, L_0x12eae90, L_0x12eaff0, C4<0>, C4<0>; +L_0x12ead80 .delay 1 (30000,30000,30000) L_0x12ead80/d; +L_0x12eb170/d .functor OR 1, L_0x12eb1e0, L_0x12eb390, C4<0>, C4<0>; +L_0x12eb170 .delay 1 (30000,30000,30000) L_0x12eb170/d; +v0x11628c0_0 .net *"_s0", 0 0, L_0x12ea930; 1 drivers +v0x11629c0_0 .net *"_s10", 0 0, L_0x12eae90; 1 drivers +v0x1162aa0_0 .net *"_s12", 0 0, L_0x12eaff0; 1 drivers +v0x1162b60_0 .net *"_s14", 0 0, L_0x12eb1e0; 1 drivers +v0x1162c40_0 .net *"_s16", 0 0, L_0x12eb390; 1 drivers +v0x1162d70_0 .net *"_s3", 0 0, L_0x12ea9f0; 1 drivers +v0x1162e50_0 .net *"_s5", 0 0, L_0x12eab50; 1 drivers +v0x1162f30_0 .net *"_s6", 0 0, L_0x12ead80; 1 drivers +v0x1163010_0 .net "in", 3 0, L_0x12eb480; 1 drivers +v0x1163180_0 .net "ors", 1 0, L_0x12eac90; 1 drivers +v0x1163260_0 .net "out", 0 0, L_0x12eb170; 1 drivers +L_0x12ea9f0 .part L_0x12eb480, 0, 1; +L_0x12eab50 .part L_0x12eb480, 1, 1; +L_0x12eac90 .concat8 [ 1 1 0 0], L_0x12ea930, L_0x12ead80; +L_0x12eae90 .part L_0x12eb480, 2, 1; +L_0x12eaff0 .part L_0x12eb480, 3, 1; +L_0x12eb1e0 .part L_0x12eac90, 0, 1; +L_0x12eb390 .part L_0x12eac90, 1, 1; +S_0x1163380 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11624b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e57d40/d .functor OR 1, L_0x1e57db0, L_0x1e57f10, C4<0>, C4<0>; -L_0x1e57d40 .delay 1 (30000,30000,30000) L_0x1e57d40/d; -L_0x1e58140/d .functor OR 1, L_0x1e58250, L_0x1e583b0, C4<0>, C4<0>; -L_0x1e58140 .delay 1 (30000,30000,30000) L_0x1e58140/d; -L_0x1e58530/d .functor OR 1, L_0x1e585a0, L_0x1e58750, C4<0>, C4<0>; -L_0x1e58530 .delay 1 (30000,30000,30000) L_0x1e58530/d; -v0x1cd08d0_0 .net *"_s0", 0 0, L_0x1e57d40; 1 drivers -v0x1cd09d0_0 .net *"_s10", 0 0, L_0x1e58250; 1 drivers -v0x1cd0ab0_0 .net *"_s12", 0 0, L_0x1e583b0; 1 drivers -v0x1cd0b70_0 .net *"_s14", 0 0, L_0x1e585a0; 1 drivers -v0x1cd0c50_0 .net *"_s16", 0 0, L_0x1e58750; 1 drivers -v0x1cd0d80_0 .net *"_s3", 0 0, L_0x1e57db0; 1 drivers -v0x1cd0e60_0 .net *"_s5", 0 0, L_0x1e57f10; 1 drivers -v0x1cd0f40_0 .net *"_s6", 0 0, L_0x1e58140; 1 drivers -v0x1cd1020_0 .net "in", 3 0, L_0x1e58980; 1 drivers -v0x1cd1190_0 .net "ors", 1 0, L_0x1e58050; 1 drivers -v0x1cd1270_0 .net "out", 0 0, L_0x1e58530; 1 drivers -L_0x1e57db0 .part L_0x1e58980, 0, 1; -L_0x1e57f10 .part L_0x1e58980, 1, 1; -L_0x1e58050 .concat8 [ 1 1 0 0], L_0x1e57d40, L_0x1e58140; -L_0x1e58250 .part L_0x1e58980, 2, 1; -L_0x1e583b0 .part L_0x1e58980, 3, 1; -L_0x1e585a0 .part L_0x1e58050, 0, 1; -L_0x1e58750 .part L_0x1e58050, 1, 1; -S_0x1cd1b80 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cc5500; +L_0x12eb5b0/d .functor OR 1, L_0x12eb620, L_0x12eb780, C4<0>, C4<0>; +L_0x12eb5b0 .delay 1 (30000,30000,30000) L_0x12eb5b0/d; +L_0x12eb9b0/d .functor OR 1, L_0x12ebac0, L_0x12ebc20, C4<0>, C4<0>; +L_0x12eb9b0 .delay 1 (30000,30000,30000) L_0x12eb9b0/d; +L_0x12ebda0/d .functor OR 1, L_0x12ebe10, L_0x12ebfc0, C4<0>, C4<0>; +L_0x12ebda0 .delay 1 (30000,30000,30000) L_0x12ebda0/d; +v0x1163540_0 .net *"_s0", 0 0, L_0x12eb5b0; 1 drivers +v0x1163640_0 .net *"_s10", 0 0, L_0x12ebac0; 1 drivers +v0x1163720_0 .net *"_s12", 0 0, L_0x12ebc20; 1 drivers +v0x11637e0_0 .net *"_s14", 0 0, L_0x12ebe10; 1 drivers +v0x11638c0_0 .net *"_s16", 0 0, L_0x12ebfc0; 1 drivers +v0x11639f0_0 .net *"_s3", 0 0, L_0x12eb620; 1 drivers +v0x1163ad0_0 .net *"_s5", 0 0, L_0x12eb780; 1 drivers +v0x1163bb0_0 .net *"_s6", 0 0, L_0x12eb9b0; 1 drivers +v0x1163c90_0 .net "in", 3 0, L_0x12ec1f0; 1 drivers +v0x1163e00_0 .net "ors", 1 0, L_0x12eb8c0; 1 drivers +v0x1163ee0_0 .net "out", 0 0, L_0x12ebda0; 1 drivers +L_0x12eb620 .part L_0x12ec1f0, 0, 1; +L_0x12eb780 .part L_0x12ec1f0, 1, 1; +L_0x12eb8c0 .concat8 [ 1 1 0 0], L_0x12eb5b0, L_0x12eb9b0; +L_0x12ebac0 .part L_0x12ec1f0, 2, 1; +L_0x12ebc20 .part L_0x12ec1f0, 3, 1; +L_0x12ebe10 .part L_0x12eb8c0, 0, 1; +L_0x12ebfc0 .part L_0x12eb8c0, 1, 1; +S_0x11647f0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1158170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -12844,80 +12854,80 @@ S_0x1cd1b80 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cc5500; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e542d0/d .functor XNOR 1, L_0x1e5c800, L_0x1e52ea0, C4<0>, C4<0>; -L_0x1e542d0 .delay 1 (20000,20000,20000) L_0x1e542d0/d; -L_0x1e54540/d .functor AND 1, L_0x1e5c800, L_0x1e531c0, C4<1>, C4<1>; -L_0x1e54540 .delay 1 (30000,30000,30000) L_0x1e54540/d; -L_0x1e545b0/d .functor AND 1, L_0x1e542d0, L_0x1e52f40, C4<1>, C4<1>; -L_0x1e545b0 .delay 1 (30000,30000,30000) L_0x1e545b0/d; -L_0x1e54710/d .functor OR 1, L_0x1e545b0, L_0x1e54540, C4<0>, C4<0>; -L_0x1e54710 .delay 1 (30000,30000,30000) L_0x1e54710/d; -v0x1cd1e30_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers -v0x1cd1f20_0 .net "a_", 0 0, L_0x1e493c0; alias, 1 drivers -v0x1cd1fe0_0 .net "b", 0 0, L_0x1e52ea0; alias, 1 drivers -v0x1cd20d0_0 .net "b_", 0 0, L_0x1e531c0; alias, 1 drivers -v0x1cd2170_0 .net "carryin", 0 0, L_0x1e52f40; alias, 1 drivers -v0x1cd22b0_0 .net "eq", 0 0, L_0x1e542d0; 1 drivers -v0x1cd2370_0 .net "lt", 0 0, L_0x1e54540; 1 drivers -v0x1cd2430_0 .net "out", 0 0, L_0x1e54710; 1 drivers -v0x1cd24f0_0 .net "w0", 0 0, L_0x1e545b0; 1 drivers -S_0x1cd2740 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cc5500; +L_0x12e7b40/d .functor XNOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; +L_0x12e7b40 .delay 1 (20000,20000,20000) L_0x12e7b40/d; +L_0x12e7db0/d .functor AND 1, L_0x12f0130, L_0x12e6a30, C4<1>, C4<1>; +L_0x12e7db0 .delay 1 (30000,30000,30000) L_0x12e7db0/d; +L_0x12e7e20/d .functor AND 1, L_0x12e7b40, L_0x12e67b0, C4<1>, C4<1>; +L_0x12e7e20 .delay 1 (30000,30000,30000) L_0x12e7e20/d; +L_0x12e7f80/d .functor OR 1, L_0x12e7e20, L_0x12e7db0, C4<0>, C4<0>; +L_0x12e7f80 .delay 1 (30000,30000,30000) L_0x12e7f80/d; +v0x1164aa0_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers +v0x1164b90_0 .net "a_", 0 0, L_0x12dcbb0; alias, 1 drivers +v0x1164c50_0 .net "b", 0 0, L_0x12e6710; alias, 1 drivers +v0x1164d40_0 .net "b_", 0 0, L_0x12e6a30; alias, 1 drivers +v0x1164de0_0 .net "carryin", 0 0, L_0x12e67b0; alias, 1 drivers +v0x1164f20_0 .net "eq", 0 0, L_0x12e7b40; 1 drivers +v0x1164fe0_0 .net "lt", 0 0, L_0x12e7db0; 1 drivers +v0x11650a0_0 .net "out", 0 0, L_0x12e7f80; 1 drivers +v0x1165160_0 .net "w0", 0 0, L_0x12e7e20; 1 drivers +S_0x11653b0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1158170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e540b0/d .functor OR 1, L_0x1e53bb0, L_0x1cd39b0, C4<0>, C4<0>; -L_0x1e540b0 .delay 1 (30000,30000,30000) L_0x1e540b0/d; -v0x1cd3510_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers -v0x1cd3660_0 .net "b", 0 0, L_0x1e531c0; alias, 1 drivers -v0x1cd3720_0 .net "c1", 0 0, L_0x1e53bb0; 1 drivers -v0x1cd37f0_0 .net "c2", 0 0, L_0x1cd39b0; 1 drivers -v0x1cd38c0_0 .net "carryin", 0 0, L_0x1e52f40; alias, 1 drivers -v0x1cd3a40_0 .net "carryout", 0 0, L_0x1e540b0; 1 drivers -v0x1cd3ae0_0 .net "s1", 0 0, L_0x1e53af0; 1 drivers -v0x1cd3b80_0 .net "sum", 0 0, L_0x1e53d10; 1 drivers -S_0x1cd2990 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cd2740; +L_0x12e7920/d .functor OR 1, L_0x12e7420, L_0x1166610, C4<0>, C4<0>; +L_0x12e7920 .delay 1 (30000,30000,30000) L_0x12e7920/d; +v0x11661a0_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers +v0x11662f0_0 .net "b", 0 0, L_0x12e6a30; alias, 1 drivers +v0x11663b0_0 .net "c1", 0 0, L_0x12e7420; 1 drivers +v0x1166450_0 .net "c2", 0 0, L_0x1166610; 1 drivers +v0x1166520_0 .net "carryin", 0 0, L_0x12e67b0; alias, 1 drivers +v0x11666a0_0 .net "carryout", 0 0, L_0x12e7920; 1 drivers +v0x1166740_0 .net "s1", 0 0, L_0x12e7360; 1 drivers +v0x11667e0_0 .net "sum", 0 0, L_0x12e7580; 1 drivers +S_0x1165600 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11653b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e53af0/d .functor XOR 1, L_0x1e5c800, L_0x1e531c0, C4<0>, C4<0>; -L_0x1e53af0 .delay 1 (30000,30000,30000) L_0x1e53af0/d; -L_0x1e53bb0/d .functor AND 1, L_0x1e5c800, L_0x1e531c0, C4<1>, C4<1>; -L_0x1e53bb0 .delay 1 (30000,30000,30000) L_0x1e53bb0/d; -v0x1cd2bf0_0 .net "a", 0 0, L_0x1e5c800; alias, 1 drivers -v0x1cd2cb0_0 .net "b", 0 0, L_0x1e531c0; alias, 1 drivers -v0x1cd2d70_0 .net "carryout", 0 0, L_0x1e53bb0; alias, 1 drivers -v0x1cd2e10_0 .net "sum", 0 0, L_0x1e53af0; alias, 1 drivers -S_0x1cd2f40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cd2740; +L_0x12e7360/d .functor XOR 1, L_0x12f0130, L_0x12e6a30, C4<0>, C4<0>; +L_0x12e7360 .delay 1 (30000,30000,30000) L_0x12e7360/d; +L_0x12e7420/d .functor AND 1, L_0x12f0130, L_0x12e6a30, C4<1>, C4<1>; +L_0x12e7420 .delay 1 (30000,30000,30000) L_0x12e7420/d; +v0x1165860_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers +v0x1165920_0 .net "b", 0 0, L_0x12e6a30; alias, 1 drivers +v0x11659e0_0 .net "carryout", 0 0, L_0x12e7420; alias, 1 drivers +v0x1165a80_0 .net "sum", 0 0, L_0x12e7360; alias, 1 drivers +S_0x1165bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11653b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e53d10/d .functor XOR 1, L_0x1e53af0, L_0x1e52f40, C4<0>, C4<0>; -L_0x1e53d10 .delay 1 (30000,30000,30000) L_0x1e53d10/d; -L_0x1cd39b0/d .functor AND 1, L_0x1e53af0, L_0x1e52f40, C4<1>, C4<1>; -L_0x1cd39b0 .delay 1 (30000,30000,30000) L_0x1cd39b0/d; -v0x1cd3180_0 .net "a", 0 0, L_0x1e53af0; alias, 1 drivers -v0x1cd3250_0 .net "b", 0 0, L_0x1e52f40; alias, 1 drivers -v0x1cd32f0_0 .net "carryout", 0 0, L_0x1cd39b0; alias, 1 drivers -v0x1cd33c0_0 .net "sum", 0 0, L_0x1e53d10; alias, 1 drivers -S_0x1cd4fa0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cc5230; - .timescale -9 -12; -L_0x7f72592db9f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dba40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e5c8a0/d .functor OR 1, L_0x7f72592db9f8, L_0x7f72592dba40, C4<0>, C4<0>; -L_0x1e5c8a0 .delay 1 (30000,30000,30000) L_0x1e5c8a0/d; -v0x1cd5190_0 .net/2u *"_s0", 0 0, L_0x7f72592db9f8; 1 drivers -v0x1cd5270_0 .net/2u *"_s2", 0 0, L_0x7f72592dba40; 1 drivers -S_0x1cd5350 .scope generate, "alu_slices[24]" "alu_slices[24]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1cd5560 .param/l "i" 0 3 37, +C4<011000>; -S_0x1cd5620 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cd5350; +L_0x12e7580/d .functor XOR 1, L_0x12e7360, L_0x12e67b0, C4<0>, C4<0>; +L_0x12e7580 .delay 1 (30000,30000,30000) L_0x12e7580/d; +L_0x1166610/d .functor AND 1, L_0x12e7360, L_0x12e67b0, C4<1>, C4<1>; +L_0x1166610 .delay 1 (30000,30000,30000) L_0x1166610/d; +v0x1165e10_0 .net "a", 0 0, L_0x12e7360; alias, 1 drivers +v0x1165ee0_0 .net "b", 0 0, L_0x12e67b0; alias, 1 drivers +v0x1165f80_0 .net "carryout", 0 0, L_0x1166610; alias, 1 drivers +v0x1166050_0 .net "sum", 0 0, L_0x12e7580; alias, 1 drivers +S_0x1167c00 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1157ea0; + .timescale -9 -12; +L_0x2b0ab3d069f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06a40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f01d0/d .functor OR 1, L_0x2b0ab3d069f8, L_0x2b0ab3d06a40, C4<0>, C4<0>; +L_0x12f01d0 .delay 1 (30000,30000,30000) L_0x12f01d0/d; +v0x1167df0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d069f8; 1 drivers +v0x1167ed0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06a40; 1 drivers +S_0x1167fb0 .scope generate, "alu_slices[24]" "alu_slices[24]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11681c0 .param/l "i" 0 3 41, +C4<011000>; +S_0x1168280 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1167fb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -12926,445 +12936,445 @@ S_0x1cd5620 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cd5350; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e5cc00/d .functor NOT 1, L_0x1e66500, C4<0>, C4<0>, C4<0>; -L_0x1e5cc00 .delay 1 (10000,10000,10000) L_0x1e5cc00/d; -L_0x1e5cd10/d .functor NOT 1, L_0x1e66660, C4<0>, C4<0>, C4<0>; -L_0x1e5cd10 .delay 1 (10000,10000,10000) L_0x1e5cd10/d; -L_0x1e5dd10/d .functor XOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; -L_0x1e5dd10 .delay 1 (30000,30000,30000) L_0x1e5dd10/d; -L_0x7f72592dba88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbad0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e5e3c0/d .functor OR 1, L_0x7f72592dba88, L_0x7f72592dbad0, C4<0>, C4<0>; -L_0x1e5e3c0 .delay 1 (30000,30000,30000) L_0x1e5e3c0/d; -L_0x1e5e5c0/d .functor AND 1, L_0x1e66500, L_0x1e66660, C4<1>, C4<1>; -L_0x1e5e5c0 .delay 1 (30000,30000,30000) L_0x1e5e5c0/d; -L_0x1e5e680/d .functor NAND 1, L_0x1e66500, L_0x1e66660, C4<1>, C4<1>; -L_0x1e5e680 .delay 1 (20000,20000,20000) L_0x1e5e680/d; -L_0x1e5e7e0/d .functor XOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; -L_0x1e5e7e0 .delay 1 (20000,20000,20000) L_0x1e5e7e0/d; -L_0x1e5ec90/d .functor OR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; -L_0x1e5ec90 .delay 1 (30000,30000,30000) L_0x1e5ec90/d; -L_0x1e66400/d .functor NOT 1, L_0x1e62600, C4<0>, C4<0>, C4<0>; -L_0x1e66400 .delay 1 (10000,10000,10000) L_0x1e66400/d; -v0x1ce3d50_0 .net "A", 0 0, L_0x1e66500; 1 drivers -v0x1ce3e10_0 .net "A_", 0 0, L_0x1e5cc00; 1 drivers -v0x1ce3ed0_0 .net "B", 0 0, L_0x1e66660; 1 drivers -v0x1ce3fa0_0 .net "B_", 0 0, L_0x1e5cd10; 1 drivers -v0x1ce4040_0 .net *"_s12", 0 0, L_0x1e5e3c0; 1 drivers -v0x1ce4130_0 .net/2s *"_s14", 0 0, L_0x7f72592dba88; 1 drivers -v0x1ce41f0_0 .net/2s *"_s16", 0 0, L_0x7f72592dbad0; 1 drivers -v0x1ce42d0_0 .net *"_s18", 0 0, L_0x1e5e5c0; 1 drivers -v0x1ce43b0_0 .net *"_s20", 0 0, L_0x1e5e680; 1 drivers -v0x1ce4520_0 .net *"_s22", 0 0, L_0x1e5e7e0; 1 drivers -v0x1ce4600_0 .net *"_s24", 0 0, L_0x1e5ec90; 1 drivers -o0x7f725932d248 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1ce46e0_0 name=_s30 -o0x7f725932d278 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1ce47c0_0 name=_s32 -v0x1ce48a0_0 .net *"_s8", 0 0, L_0x1e5dd10; 1 drivers -v0x1ce4980_0 .net "carryin", 0 0, L_0x1e5c960; 1 drivers -v0x1ce4a20_0 .net "carryout", 0 0, L_0x1e660a0; 1 drivers -v0x1ce4ac0_0 .net "carryouts", 7 0, L_0x1ec1470; 1 drivers -v0x1ce4c70_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ce4d10_0 .net "result", 0 0, L_0x1e62600; 1 drivers -v0x1ce4e00_0 .net "results", 7 0, L_0x1e5ea60; 1 drivers -v0x1ce4f10_0 .net "zero", 0 0, L_0x1e66400; 1 drivers -LS_0x1e5ea60_0_0 .concat8 [ 1 1 1 1], L_0x1e5d230, L_0x1e5d860, L_0x1e5dd10, L_0x1e5e3c0; -LS_0x1e5ea60_0_4 .concat8 [ 1 1 1 1], L_0x1e5e5c0, L_0x1e5e680, L_0x1e5e7e0, L_0x1e5ec90; -L_0x1e5ea60 .concat8 [ 4 4 0 0], LS_0x1e5ea60_0_0, LS_0x1e5ea60_0_4; -LS_0x1ec1470_0_0 .concat [ 1 1 1 1], L_0x1e5d4e0, L_0x1e5dbb0, o0x7f725932d248, L_0x1e5e210; -LS_0x1ec1470_0_4 .concat [ 4 0 0 0], o0x7f725932d278; -L_0x1ec1470 .concat [ 4 4 0 0], LS_0x1ec1470_0_0, LS_0x1ec1470_0_4; -S_0x1cd58a0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cd5620; +L_0x12f0530/d .functor NOT 1, L_0x12f9d60, C4<0>, C4<0>, C4<0>; +L_0x12f0530 .delay 1 (10000,10000,10000) L_0x12f0530/d; +L_0x12f0640/d .functor NOT 1, L_0x12f9ec0, C4<0>, C4<0>, C4<0>; +L_0x12f0640 .delay 1 (10000,10000,10000) L_0x12f0640/d; +L_0x12f1690/d .functor XOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; +L_0x12f1690 .delay 1 (30000,30000,30000) L_0x12f1690/d; +L_0x2b0ab3d06a88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06ad0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f1d40/d .functor OR 1, L_0x2b0ab3d06a88, L_0x2b0ab3d06ad0, C4<0>, C4<0>; +L_0x12f1d40 .delay 1 (30000,30000,30000) L_0x12f1d40/d; +L_0x12f1f40/d .functor AND 1, L_0x12f9d60, L_0x12f9ec0, C4<1>, C4<1>; +L_0x12f1f40 .delay 1 (30000,30000,30000) L_0x12f1f40/d; +L_0x12f2000/d .functor NAND 1, L_0x12f9d60, L_0x12f9ec0, C4<1>, C4<1>; +L_0x12f2000 .delay 1 (20000,20000,20000) L_0x12f2000/d; +L_0x12f2160/d .functor XOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; +L_0x12f2160 .delay 1 (20000,20000,20000) L_0x12f2160/d; +L_0x12f2610/d .functor OR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; +L_0x12f2610 .delay 1 (30000,30000,30000) L_0x12f2610/d; +L_0x12f9c60/d .functor NOT 1, L_0x12f5ea0, C4<0>, C4<0>, C4<0>; +L_0x12f9c60 .delay 1 (10000,10000,10000) L_0x12f9c60/d; +v0x11769b0_0 .net "A", 0 0, L_0x12f9d60; 1 drivers +v0x1176a70_0 .net "A_", 0 0, L_0x12f0530; 1 drivers +v0x1176b30_0 .net "B", 0 0, L_0x12f9ec0; 1 drivers +v0x1176c00_0 .net "B_", 0 0, L_0x12f0640; 1 drivers +v0x1176ca0_0 .net *"_s12", 0 0, L_0x12f1d40; 1 drivers +v0x1176d90_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06a88; 1 drivers +v0x1176e50_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06ad0; 1 drivers +v0x1176f30_0 .net *"_s18", 0 0, L_0x12f1f40; 1 drivers +v0x1177010_0 .net *"_s20", 0 0, L_0x12f2000; 1 drivers +v0x1177180_0 .net *"_s22", 0 0, L_0x12f2160; 1 drivers +v0x1177260_0 .net *"_s24", 0 0, L_0x12f2610; 1 drivers +o0x2b0ab3cde248 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1177340_0 name=_s30 +o0x2b0ab3cde278 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1177420_0 name=_s32 +v0x1177500_0 .net *"_s8", 0 0, L_0x12f1690; 1 drivers +v0x11775e0_0 .net "carryin", 0 0, L_0x12f0290; 1 drivers +v0x1177680_0 .net "carryout", 0 0, L_0x12f9900; 1 drivers +v0x1177720_0 .net "carryouts", 7 0, L_0x13557a0; 1 drivers +v0x11778d0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1177970_0 .net "result", 0 0, L_0x12f5ea0; 1 drivers +v0x1177a60_0 .net "results", 7 0, L_0x12f23e0; 1 drivers +v0x1177b70_0 .net "zero", 0 0, L_0x12f9c60; 1 drivers +LS_0x12f23e0_0_0 .concat8 [ 1 1 1 1], L_0x12f0b60, L_0x12f1190, L_0x12f1690, L_0x12f1d40; +LS_0x12f23e0_0_4 .concat8 [ 1 1 1 1], L_0x12f1f40, L_0x12f2000, L_0x12f2160, L_0x12f2610; +L_0x12f23e0 .concat8 [ 4 4 0 0], LS_0x12f23e0_0_0, LS_0x12f23e0_0_4; +LS_0x13557a0_0_0 .concat [ 1 1 1 1], L_0x12f0e10, L_0x12f1530, o0x2b0ab3cde248, L_0x12f1b90; +LS_0x13557a0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cde278; +L_0x13557a0 .concat [ 4 4 0 0], LS_0x13557a0_0_0, LS_0x13557a0_0_4; +S_0x1168500 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1168280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e5d4e0/d .functor OR 1, L_0x1e5cfc0, L_0x1e5d380, C4<0>, C4<0>; -L_0x1e5d4e0 .delay 1 (30000,30000,30000) L_0x1e5d4e0/d; -v0x1cd66d0_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers -v0x1cd6790_0 .net "b", 0 0, L_0x1e66660; alias, 1 drivers -v0x1cd6860_0 .net "c1", 0 0, L_0x1e5cfc0; 1 drivers -v0x1cd6960_0 .net "c2", 0 0, L_0x1e5d380; 1 drivers -v0x1cd6a30_0 .net "carryin", 0 0, L_0x1e5c960; alias, 1 drivers -v0x1cd6b20_0 .net "carryout", 0 0, L_0x1e5d4e0; 1 drivers -v0x1cd6bc0_0 .net "s1", 0 0, L_0x1e5cf00; 1 drivers -v0x1cd6cb0_0 .net "sum", 0 0, L_0x1e5d230; 1 drivers -S_0x1cd5b10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cd58a0; +L_0x12f0e10/d .functor OR 1, L_0x12f08f0, L_0x12f0cb0, C4<0>, C4<0>; +L_0x12f0e10 .delay 1 (30000,30000,30000) L_0x12f0e10/d; +v0x1169330_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers +v0x11693f0_0 .net "b", 0 0, L_0x12f9ec0; alias, 1 drivers +v0x11694c0_0 .net "c1", 0 0, L_0x12f08f0; 1 drivers +v0x11695c0_0 .net "c2", 0 0, L_0x12f0cb0; 1 drivers +v0x1169690_0 .net "carryin", 0 0, L_0x12f0290; alias, 1 drivers +v0x1169780_0 .net "carryout", 0 0, L_0x12f0e10; 1 drivers +v0x1169820_0 .net "s1", 0 0, L_0x12f0830; 1 drivers +v0x1169910_0 .net "sum", 0 0, L_0x12f0b60; 1 drivers +S_0x1168770 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1168500; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e5cf00/d .functor XOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; -L_0x1e5cf00 .delay 1 (30000,30000,30000) L_0x1e5cf00/d; -L_0x1e5cfc0/d .functor AND 1, L_0x1e66500, L_0x1e66660, C4<1>, C4<1>; -L_0x1e5cfc0 .delay 1 (30000,30000,30000) L_0x1e5cfc0/d; -v0x1cd5d70_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers -v0x1cd5e50_0 .net "b", 0 0, L_0x1e66660; alias, 1 drivers -v0x1cd5f10_0 .net "carryout", 0 0, L_0x1e5cfc0; alias, 1 drivers -v0x1cd5fb0_0 .net "sum", 0 0, L_0x1e5cf00; alias, 1 drivers -S_0x1cd60f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cd58a0; +L_0x12f0830/d .functor XOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; +L_0x12f0830 .delay 1 (30000,30000,30000) L_0x12f0830/d; +L_0x12f08f0/d .functor AND 1, L_0x12f9d60, L_0x12f9ec0, C4<1>, C4<1>; +L_0x12f08f0 .delay 1 (30000,30000,30000) L_0x12f08f0/d; +v0x11689d0_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers +v0x1168ab0_0 .net "b", 0 0, L_0x12f9ec0; alias, 1 drivers +v0x1168b70_0 .net "carryout", 0 0, L_0x12f08f0; alias, 1 drivers +v0x1168c10_0 .net "sum", 0 0, L_0x12f0830; alias, 1 drivers +S_0x1168d50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1168500; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e5d230/d .functor XOR 1, L_0x1e5cf00, L_0x1e5c960, C4<0>, C4<0>; -L_0x1e5d230 .delay 1 (30000,30000,30000) L_0x1e5d230/d; -L_0x1e5d380/d .functor AND 1, L_0x1e5cf00, L_0x1e5c960, C4<1>, C4<1>; -L_0x1e5d380 .delay 1 (30000,30000,30000) L_0x1e5d380/d; -v0x1cd6350_0 .net "a", 0 0, L_0x1e5cf00; alias, 1 drivers -v0x1cd63f0_0 .net "b", 0 0, L_0x1e5c960; alias, 1 drivers -v0x1cd6490_0 .net "carryout", 0 0, L_0x1e5d380; alias, 1 drivers -v0x1cd6560_0 .net "sum", 0 0, L_0x1e5d230; alias, 1 drivers -S_0x1cd6d80 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cd5620; +L_0x12f0b60/d .functor XOR 1, L_0x12f0830, L_0x12f0290, C4<0>, C4<0>; +L_0x12f0b60 .delay 1 (30000,30000,30000) L_0x12f0b60/d; +L_0x12f0cb0/d .functor AND 1, L_0x12f0830, L_0x12f0290, C4<1>, C4<1>; +L_0x12f0cb0 .delay 1 (30000,30000,30000) L_0x12f0cb0/d; +v0x1168fb0_0 .net "a", 0 0, L_0x12f0830; alias, 1 drivers +v0x1169050_0 .net "b", 0 0, L_0x12f0290; alias, 1 drivers +v0x11690f0_0 .net "carryout", 0 0, L_0x12f0cb0; alias, 1 drivers +v0x11691c0_0 .net "sum", 0 0, L_0x12f0b60; alias, 1 drivers +S_0x11699e0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1168280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cdc170_0 .net "ands", 7 0, L_0x1e640a0; 1 drivers -v0x1cdc280_0 .net "in", 7 0, L_0x1ec1470; alias, 1 drivers -v0x1cdc340_0 .net "out", 0 0, L_0x1e660a0; alias, 1 drivers -v0x1cdc410_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cd6fa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cd6d80; +v0x116edd0_0 .net "ands", 7 0, L_0x12f7900; 1 drivers +v0x116eee0_0 .net "in", 7 0, L_0x13557a0; alias, 1 drivers +v0x116efa0_0 .net "out", 0 0, L_0x12f9900; alias, 1 drivers +v0x116f070_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1169c00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11699e0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cd96d0_0 .net "A", 7 0, L_0x1ec1470; alias, 1 drivers -v0x1cd97d0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cd9890_0 .net *"_s0", 0 0, L_0x1e62960; 1 drivers -v0x1cd9950_0 .net *"_s12", 0 0, L_0x1e632d0; 1 drivers -v0x1cd9a30_0 .net *"_s16", 0 0, L_0x1e63630; 1 drivers -v0x1cd9b60_0 .net *"_s20", 0 0, L_0x1e63940; 1 drivers -v0x1cd9c40_0 .net *"_s24", 0 0, L_0x1e63d30; 1 drivers -v0x1cd9d20_0 .net *"_s28", 0 0, L_0x1e63cc0; 1 drivers -v0x1cd9e00_0 .net *"_s4", 0 0, L_0x1e62c70; 1 drivers -v0x1cd9f70_0 .net *"_s8", 0 0, L_0x1e62fc0; 1 drivers -v0x1cda050_0 .net "out", 7 0, L_0x1e640a0; alias, 1 drivers -L_0x1e62a20 .part L_0x1ec1470, 0, 1; -L_0x1e62b80 .part v0x1d6daa0_0, 0, 1; -L_0x1e62d30 .part L_0x1ec1470, 1, 1; -L_0x1e62f20 .part v0x1d6daa0_0, 1, 1; -L_0x1e63080 .part L_0x1ec1470, 2, 1; -L_0x1e631e0 .part v0x1d6daa0_0, 2, 1; -L_0x1e63390 .part L_0x1ec1470, 3, 1; -L_0x1e634f0 .part v0x1d6daa0_0, 3, 1; -L_0x1e636f0 .part L_0x1ec1470, 4, 1; -L_0x1e63850 .part v0x1d6daa0_0, 4, 1; -L_0x1e639b0 .part L_0x1ec1470, 5, 1; -L_0x1e63c20 .part v0x1d6daa0_0, 5, 1; -L_0x1e63e50 .part L_0x1ec1470, 6, 1; -L_0x1e63fb0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e640a0_0_0 .concat8 [ 1 1 1 1], L_0x1e62960, L_0x1e62c70, L_0x1e62fc0, L_0x1e632d0; -LS_0x1e640a0_0_4 .concat8 [ 1 1 1 1], L_0x1e63630, L_0x1e63940, L_0x1e63d30, L_0x1e63cc0; -L_0x1e640a0 .concat8 [ 4 4 0 0], LS_0x1e640a0_0_0, LS_0x1e640a0_0_4; -L_0x1e64460 .part L_0x1ec1470, 7, 1; -L_0x1e64650 .part v0x1d6daa0_0, 7, 1; -S_0x1cd7200 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd7410 .param/l "i" 0 4 54, +C4<00>; -L_0x1e62960/d .functor AND 1, L_0x1e62a20, L_0x1e62b80, C4<1>, C4<1>; -L_0x1e62960 .delay 1 (30000,30000,30000) L_0x1e62960/d; -v0x1cd74f0_0 .net *"_s0", 0 0, L_0x1e62a20; 1 drivers -v0x1cd75d0_0 .net *"_s1", 0 0, L_0x1e62b80; 1 drivers -S_0x1cd76b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd78c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e62c70/d .functor AND 1, L_0x1e62d30, L_0x1e62f20, C4<1>, C4<1>; -L_0x1e62c70 .delay 1 (30000,30000,30000) L_0x1e62c70/d; -v0x1cd7980_0 .net *"_s0", 0 0, L_0x1e62d30; 1 drivers -v0x1cd7a60_0 .net *"_s1", 0 0, L_0x1e62f20; 1 drivers -S_0x1cd7b40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd7d50 .param/l "i" 0 4 54, +C4<010>; -L_0x1e62fc0/d .functor AND 1, L_0x1e63080, L_0x1e631e0, C4<1>, C4<1>; -L_0x1e62fc0 .delay 1 (30000,30000,30000) L_0x1e62fc0/d; -v0x1cd7df0_0 .net *"_s0", 0 0, L_0x1e63080; 1 drivers -v0x1cd7ed0_0 .net *"_s1", 0 0, L_0x1e631e0; 1 drivers -S_0x1cd7fb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd81c0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e632d0/d .functor AND 1, L_0x1e63390, L_0x1e634f0, C4<1>, C4<1>; -L_0x1e632d0 .delay 1 (30000,30000,30000) L_0x1e632d0/d; -v0x1cd8280_0 .net *"_s0", 0 0, L_0x1e63390; 1 drivers -v0x1cd8360_0 .net *"_s1", 0 0, L_0x1e634f0; 1 drivers -S_0x1cd8440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd86a0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e63630/d .functor AND 1, L_0x1e636f0, L_0x1e63850, C4<1>, C4<1>; -L_0x1e63630 .delay 1 (30000,30000,30000) L_0x1e63630/d; -v0x1cd8760_0 .net *"_s0", 0 0, L_0x1e636f0; 1 drivers -v0x1cd8840_0 .net *"_s1", 0 0, L_0x1e63850; 1 drivers -S_0x1cd8920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd8b30 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e63940/d .functor AND 1, L_0x1e639b0, L_0x1e63c20, C4<1>, C4<1>; -L_0x1e63940 .delay 1 (30000,30000,30000) L_0x1e63940/d; -v0x1cd8bf0_0 .net *"_s0", 0 0, L_0x1e639b0; 1 drivers -v0x1cd8cd0_0 .net *"_s1", 0 0, L_0x1e63c20; 1 drivers -S_0x1cd8db0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd8fc0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e63d30/d .functor AND 1, L_0x1e63e50, L_0x1e63fb0, C4<1>, C4<1>; -L_0x1e63d30 .delay 1 (30000,30000,30000) L_0x1e63d30/d; -v0x1cd9080_0 .net *"_s0", 0 0, L_0x1e63e50; 1 drivers -v0x1cd9160_0 .net *"_s1", 0 0, L_0x1e63fb0; 1 drivers -S_0x1cd9240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cd6fa0; - .timescale -9 -12; -P_0x1cd9450 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e63cc0/d .functor AND 1, L_0x1e64460, L_0x1e64650, C4<1>, C4<1>; -L_0x1e63cc0 .delay 1 (30000,30000,30000) L_0x1e63cc0/d; -v0x1cd9510_0 .net *"_s0", 0 0, L_0x1e64460; 1 drivers -v0x1cd95f0_0 .net *"_s1", 0 0, L_0x1e64650; 1 drivers -S_0x1cda1b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cd6d80; +v0x116c330_0 .net "A", 7 0, L_0x13557a0; alias, 1 drivers +v0x116c430_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x116c4f0_0 .net *"_s0", 0 0, L_0x12f6140; 1 drivers +v0x116c5b0_0 .net *"_s12", 0 0, L_0x12f6ab0; 1 drivers +v0x116c690_0 .net *"_s16", 0 0, L_0x12f6e10; 1 drivers +v0x116c7c0_0 .net *"_s20", 0 0, L_0x12f7180; 1 drivers +v0x116c8a0_0 .net *"_s24", 0 0, L_0x12f7570; 1 drivers +v0x116c980_0 .net *"_s28", 0 0, L_0x12f7500; 1 drivers +v0x116ca60_0 .net *"_s4", 0 0, L_0x12f6450; 1 drivers +v0x116cbd0_0 .net *"_s8", 0 0, L_0x12f67a0; 1 drivers +v0x116ccb0_0 .net "out", 7 0, L_0x12f7900; alias, 1 drivers +L_0x12f6200 .part L_0x13557a0, 0, 1; +L_0x12f6360 .part v0x12010b0_0, 0, 1; +L_0x12f6510 .part L_0x13557a0, 1, 1; +L_0x12f6700 .part v0x12010b0_0, 1, 1; +L_0x12f6860 .part L_0x13557a0, 2, 1; +L_0x12f69c0 .part v0x12010b0_0, 2, 1; +L_0x12f6b70 .part L_0x13557a0, 3, 1; +L_0x12f6cd0 .part v0x12010b0_0, 3, 1; +L_0x12f6ed0 .part L_0x13557a0, 4, 1; +L_0x12f7030 .part v0x12010b0_0, 4, 1; +L_0x12f71f0 .part L_0x13557a0, 5, 1; +L_0x12f7460 .part v0x12010b0_0, 5, 1; +L_0x12f7630 .part L_0x13557a0, 6, 1; +L_0x12f7790 .part v0x12010b0_0, 6, 1; +LS_0x12f7900_0_0 .concat8 [ 1 1 1 1], L_0x12f6140, L_0x12f6450, L_0x12f67a0, L_0x12f6ab0; +LS_0x12f7900_0_4 .concat8 [ 1 1 1 1], L_0x12f6e10, L_0x12f7180, L_0x12f7570, L_0x12f7500; +L_0x12f7900 .concat8 [ 4 4 0 0], LS_0x12f7900_0_0, LS_0x12f7900_0_4; +L_0x12f7cc0 .part L_0x13557a0, 7, 1; +L_0x12f7eb0 .part v0x12010b0_0, 7, 1; +S_0x1169e60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116a070 .param/l "i" 0 4 54, +C4<00>; +L_0x12f6140/d .functor AND 1, L_0x12f6200, L_0x12f6360, C4<1>, C4<1>; +L_0x12f6140 .delay 1 (30000,30000,30000) L_0x12f6140/d; +v0x116a150_0 .net *"_s0", 0 0, L_0x12f6200; 1 drivers +v0x116a230_0 .net *"_s1", 0 0, L_0x12f6360; 1 drivers +S_0x116a310 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116a520 .param/l "i" 0 4 54, +C4<01>; +L_0x12f6450/d .functor AND 1, L_0x12f6510, L_0x12f6700, C4<1>, C4<1>; +L_0x12f6450 .delay 1 (30000,30000,30000) L_0x12f6450/d; +v0x116a5e0_0 .net *"_s0", 0 0, L_0x12f6510; 1 drivers +v0x116a6c0_0 .net *"_s1", 0 0, L_0x12f6700; 1 drivers +S_0x116a7a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116a9b0 .param/l "i" 0 4 54, +C4<010>; +L_0x12f67a0/d .functor AND 1, L_0x12f6860, L_0x12f69c0, C4<1>, C4<1>; +L_0x12f67a0 .delay 1 (30000,30000,30000) L_0x12f67a0/d; +v0x116aa50_0 .net *"_s0", 0 0, L_0x12f6860; 1 drivers +v0x116ab30_0 .net *"_s1", 0 0, L_0x12f69c0; 1 drivers +S_0x116ac10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116ae20 .param/l "i" 0 4 54, +C4<011>; +L_0x12f6ab0/d .functor AND 1, L_0x12f6b70, L_0x12f6cd0, C4<1>, C4<1>; +L_0x12f6ab0 .delay 1 (30000,30000,30000) L_0x12f6ab0/d; +v0x116aee0_0 .net *"_s0", 0 0, L_0x12f6b70; 1 drivers +v0x116afc0_0 .net *"_s1", 0 0, L_0x12f6cd0; 1 drivers +S_0x116b0a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116b300 .param/l "i" 0 4 54, +C4<0100>; +L_0x12f6e10/d .functor AND 1, L_0x12f6ed0, L_0x12f7030, C4<1>, C4<1>; +L_0x12f6e10 .delay 1 (30000,30000,30000) L_0x12f6e10/d; +v0x116b3c0_0 .net *"_s0", 0 0, L_0x12f6ed0; 1 drivers +v0x116b4a0_0 .net *"_s1", 0 0, L_0x12f7030; 1 drivers +S_0x116b580 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116b790 .param/l "i" 0 4 54, +C4<0101>; +L_0x12f7180/d .functor AND 1, L_0x12f71f0, L_0x12f7460, C4<1>, C4<1>; +L_0x12f7180 .delay 1 (30000,30000,30000) L_0x12f7180/d; +v0x116b850_0 .net *"_s0", 0 0, L_0x12f71f0; 1 drivers +v0x116b930_0 .net *"_s1", 0 0, L_0x12f7460; 1 drivers +S_0x116ba10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116bc20 .param/l "i" 0 4 54, +C4<0110>; +L_0x12f7570/d .functor AND 1, L_0x12f7630, L_0x12f7790, C4<1>, C4<1>; +L_0x12f7570 .delay 1 (30000,30000,30000) L_0x12f7570/d; +v0x116bce0_0 .net *"_s0", 0 0, L_0x12f7630; 1 drivers +v0x116bdc0_0 .net *"_s1", 0 0, L_0x12f7790; 1 drivers +S_0x116bea0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1169c00; + .timescale -9 -12; +P_0x116c090 .param/l "i" 0 4 54, +C4<0111>; +L_0x12f7500/d .functor AND 1, L_0x12f7cc0, L_0x12f7eb0, C4<1>, C4<1>; +L_0x12f7500 .delay 1 (30000,30000,30000) L_0x12f7500/d; +v0x116c170_0 .net *"_s0", 0 0, L_0x12f7cc0; 1 drivers +v0x116c250_0 .net *"_s1", 0 0, L_0x12f7eb0; 1 drivers +S_0x116ce10 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11699e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e660a0/d .functor OR 1, L_0x1e66160, L_0x1e66310, C4<0>, C4<0>; -L_0x1e660a0 .delay 1 (30000,30000,30000) L_0x1e660a0/d; -v0x1cdbd00_0 .net *"_s10", 0 0, L_0x1e66160; 1 drivers -v0x1cdbde0_0 .net *"_s12", 0 0, L_0x1e66310; 1 drivers -v0x1cdbec0_0 .net "in", 7 0, L_0x1e640a0; alias, 1 drivers -v0x1cdbf90_0 .net "ors", 1 0, L_0x1e65ec0; 1 drivers -v0x1cdc050_0 .net "out", 0 0, L_0x1e660a0; alias, 1 drivers -L_0x1e65290 .part L_0x1e640a0, 0, 4; -L_0x1e65ec0 .concat8 [ 1 1 0 0], L_0x1e64f80, L_0x1e65bb0; -L_0x1e66000 .part L_0x1e640a0, 4, 4; -L_0x1e66160 .part L_0x1e65ec0, 0, 1; -L_0x1e66310 .part L_0x1e65ec0, 1, 1; -S_0x1cda370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cda1b0; +L_0x12f9900/d .functor OR 1, L_0x12f99c0, L_0x12f9b70, C4<0>, C4<0>; +L_0x12f9900 .delay 1 (30000,30000,30000) L_0x12f9900/d; +v0x116e960_0 .net *"_s10", 0 0, L_0x12f99c0; 1 drivers +v0x116ea40_0 .net *"_s12", 0 0, L_0x12f9b70; 1 drivers +v0x116eb20_0 .net "in", 7 0, L_0x12f7900; alias, 1 drivers +v0x116ebf0_0 .net "ors", 1 0, L_0x12f9720; 1 drivers +v0x116ecb0_0 .net "out", 0 0, L_0x12f9900; alias, 1 drivers +L_0x12f8af0 .part L_0x12f7900, 0, 4; +L_0x12f9720 .concat8 [ 1 1 0 0], L_0x12f87e0, L_0x12f9410; +L_0x12f9860 .part L_0x12f7900, 4, 4; +L_0x12f99c0 .part L_0x12f9720, 0, 1; +L_0x12f9b70 .part L_0x12f9720, 1, 1; +S_0x116cfd0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x116ce10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e64740/d .functor OR 1, L_0x1e64800, L_0x1e64960, C4<0>, C4<0>; -L_0x1e64740 .delay 1 (30000,30000,30000) L_0x1e64740/d; -L_0x1e64b90/d .functor OR 1, L_0x1e64ca0, L_0x1e64e00, C4<0>, C4<0>; -L_0x1e64b90 .delay 1 (30000,30000,30000) L_0x1e64b90/d; -L_0x1e64f80/d .functor OR 1, L_0x1e64ff0, L_0x1e651a0, C4<0>, C4<0>; -L_0x1e64f80 .delay 1 (30000,30000,30000) L_0x1e64f80/d; -v0x1cda5c0_0 .net *"_s0", 0 0, L_0x1e64740; 1 drivers -v0x1cda6c0_0 .net *"_s10", 0 0, L_0x1e64ca0; 1 drivers -v0x1cda7a0_0 .net *"_s12", 0 0, L_0x1e64e00; 1 drivers -v0x1cda860_0 .net *"_s14", 0 0, L_0x1e64ff0; 1 drivers -v0x1cda940_0 .net *"_s16", 0 0, L_0x1e651a0; 1 drivers -v0x1cdaa70_0 .net *"_s3", 0 0, L_0x1e64800; 1 drivers -v0x1cdab50_0 .net *"_s5", 0 0, L_0x1e64960; 1 drivers -v0x1cdac30_0 .net *"_s6", 0 0, L_0x1e64b90; 1 drivers -v0x1cdad10_0 .net "in", 3 0, L_0x1e65290; 1 drivers -v0x1cdae80_0 .net "ors", 1 0, L_0x1e64aa0; 1 drivers -v0x1cdaf60_0 .net "out", 0 0, L_0x1e64f80; 1 drivers -L_0x1e64800 .part L_0x1e65290, 0, 1; -L_0x1e64960 .part L_0x1e65290, 1, 1; -L_0x1e64aa0 .concat8 [ 1 1 0 0], L_0x1e64740, L_0x1e64b90; -L_0x1e64ca0 .part L_0x1e65290, 2, 1; -L_0x1e64e00 .part L_0x1e65290, 3, 1; -L_0x1e64ff0 .part L_0x1e64aa0, 0, 1; -L_0x1e651a0 .part L_0x1e64aa0, 1, 1; -S_0x1cdb080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cda1b0; +L_0x12f7fa0/d .functor OR 1, L_0x12f8060, L_0x12f81c0, C4<0>, C4<0>; +L_0x12f7fa0 .delay 1 (30000,30000,30000) L_0x12f7fa0/d; +L_0x12f83f0/d .functor OR 1, L_0x12f8500, L_0x12f8660, C4<0>, C4<0>; +L_0x12f83f0 .delay 1 (30000,30000,30000) L_0x12f83f0/d; +L_0x12f87e0/d .functor OR 1, L_0x12f8850, L_0x12f8a00, C4<0>, C4<0>; +L_0x12f87e0 .delay 1 (30000,30000,30000) L_0x12f87e0/d; +v0x116d220_0 .net *"_s0", 0 0, L_0x12f7fa0; 1 drivers +v0x116d320_0 .net *"_s10", 0 0, L_0x12f8500; 1 drivers +v0x116d400_0 .net *"_s12", 0 0, L_0x12f8660; 1 drivers +v0x116d4c0_0 .net *"_s14", 0 0, L_0x12f8850; 1 drivers +v0x116d5a0_0 .net *"_s16", 0 0, L_0x12f8a00; 1 drivers +v0x116d6d0_0 .net *"_s3", 0 0, L_0x12f8060; 1 drivers +v0x116d7b0_0 .net *"_s5", 0 0, L_0x12f81c0; 1 drivers +v0x116d890_0 .net *"_s6", 0 0, L_0x12f83f0; 1 drivers +v0x116d970_0 .net "in", 3 0, L_0x12f8af0; 1 drivers +v0x116dae0_0 .net "ors", 1 0, L_0x12f8300; 1 drivers +v0x116dbc0_0 .net "out", 0 0, L_0x12f87e0; 1 drivers +L_0x12f8060 .part L_0x12f8af0, 0, 1; +L_0x12f81c0 .part L_0x12f8af0, 1, 1; +L_0x12f8300 .concat8 [ 1 1 0 0], L_0x12f7fa0, L_0x12f83f0; +L_0x12f8500 .part L_0x12f8af0, 2, 1; +L_0x12f8660 .part L_0x12f8af0, 3, 1; +L_0x12f8850 .part L_0x12f8300, 0, 1; +L_0x12f8a00 .part L_0x12f8300, 1, 1; +S_0x116dce0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x116ce10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e653c0/d .functor OR 1, L_0x1e65430, L_0x1e65590, C4<0>, C4<0>; -L_0x1e653c0 .delay 1 (30000,30000,30000) L_0x1e653c0/d; -L_0x1e657c0/d .functor OR 1, L_0x1e658d0, L_0x1e65a30, C4<0>, C4<0>; -L_0x1e657c0 .delay 1 (30000,30000,30000) L_0x1e657c0/d; -L_0x1e65bb0/d .functor OR 1, L_0x1e65c20, L_0x1e65dd0, C4<0>, C4<0>; -L_0x1e65bb0 .delay 1 (30000,30000,30000) L_0x1e65bb0/d; -v0x1cdb240_0 .net *"_s0", 0 0, L_0x1e653c0; 1 drivers -v0x1cdb340_0 .net *"_s10", 0 0, L_0x1e658d0; 1 drivers -v0x1cdb420_0 .net *"_s12", 0 0, L_0x1e65a30; 1 drivers -v0x1cdb4e0_0 .net *"_s14", 0 0, L_0x1e65c20; 1 drivers -v0x1cdb5c0_0 .net *"_s16", 0 0, L_0x1e65dd0; 1 drivers -v0x1cdb6f0_0 .net *"_s3", 0 0, L_0x1e65430; 1 drivers -v0x1cdb7d0_0 .net *"_s5", 0 0, L_0x1e65590; 1 drivers -v0x1cdb8b0_0 .net *"_s6", 0 0, L_0x1e657c0; 1 drivers -v0x1cdb990_0 .net "in", 3 0, L_0x1e66000; 1 drivers -v0x1cdbb00_0 .net "ors", 1 0, L_0x1e656d0; 1 drivers -v0x1cdbbe0_0 .net "out", 0 0, L_0x1e65bb0; 1 drivers -L_0x1e65430 .part L_0x1e66000, 0, 1; -L_0x1e65590 .part L_0x1e66000, 1, 1; -L_0x1e656d0 .concat8 [ 1 1 0 0], L_0x1e653c0, L_0x1e657c0; -L_0x1e658d0 .part L_0x1e66000, 2, 1; -L_0x1e65a30 .part L_0x1e66000, 3, 1; -L_0x1e65c20 .part L_0x1e656d0, 0, 1; -L_0x1e65dd0 .part L_0x1e656d0, 1, 1; -S_0x1cdc4f0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cd5620; +L_0x12f8c20/d .functor OR 1, L_0x12f8c90, L_0x12f8df0, C4<0>, C4<0>; +L_0x12f8c20 .delay 1 (30000,30000,30000) L_0x12f8c20/d; +L_0x12f9020/d .functor OR 1, L_0x12f9130, L_0x12f9290, C4<0>, C4<0>; +L_0x12f9020 .delay 1 (30000,30000,30000) L_0x12f9020/d; +L_0x12f9410/d .functor OR 1, L_0x12f9480, L_0x12f9630, C4<0>, C4<0>; +L_0x12f9410 .delay 1 (30000,30000,30000) L_0x12f9410/d; +v0x116dea0_0 .net *"_s0", 0 0, L_0x12f8c20; 1 drivers +v0x116dfa0_0 .net *"_s10", 0 0, L_0x12f9130; 1 drivers +v0x116e080_0 .net *"_s12", 0 0, L_0x12f9290; 1 drivers +v0x116e140_0 .net *"_s14", 0 0, L_0x12f9480; 1 drivers +v0x116e220_0 .net *"_s16", 0 0, L_0x12f9630; 1 drivers +v0x116e350_0 .net *"_s3", 0 0, L_0x12f8c90; 1 drivers +v0x116e430_0 .net *"_s5", 0 0, L_0x12f8df0; 1 drivers +v0x116e510_0 .net *"_s6", 0 0, L_0x12f9020; 1 drivers +v0x116e5f0_0 .net "in", 3 0, L_0x12f9860; 1 drivers +v0x116e760_0 .net "ors", 1 0, L_0x12f8f30; 1 drivers +v0x116e840_0 .net "out", 0 0, L_0x12f9410; 1 drivers +L_0x12f8c90 .part L_0x12f9860, 0, 1; +L_0x12f8df0 .part L_0x12f9860, 1, 1; +L_0x12f8f30 .concat8 [ 1 1 0 0], L_0x12f8c20, L_0x12f9020; +L_0x12f9130 .part L_0x12f9860, 2, 1; +L_0x12f9290 .part L_0x12f9860, 3, 1; +L_0x12f9480 .part L_0x12f8f30, 0, 1; +L_0x12f9630 .part L_0x12f8f30, 1, 1; +S_0x116f150 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1168280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1ce1920_0 .net "ands", 7 0, L_0x1e60600; 1 drivers -v0x1ce1a30_0 .net "in", 7 0, L_0x1e5ea60; alias, 1 drivers -v0x1ce1af0_0 .net "out", 0 0, L_0x1e62600; alias, 1 drivers -v0x1ce1bc0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cdc740 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cdc4f0; +v0x1174580_0 .net "ands", 7 0, L_0x12f3ea0; 1 drivers +v0x1174690_0 .net "in", 7 0, L_0x12f23e0; alias, 1 drivers +v0x1174750_0 .net "out", 0 0, L_0x12f5ea0; alias, 1 drivers +v0x1174820_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x116f3a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x116f150; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cdee80_0 .net "A", 7 0, L_0x1e5ea60; alias, 1 drivers -v0x1cdef80_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cdf040_0 .net *"_s0", 0 0, L_0x1e5edf0; 1 drivers -v0x1cdf100_0 .net *"_s12", 0 0, L_0x1e5f7b0; 1 drivers -v0x1cdf1e0_0 .net *"_s16", 0 0, L_0x1e5fb10; 1 drivers -v0x1cdf310_0 .net *"_s20", 0 0, L_0x1e5ff40; 1 drivers -v0x1cdf3f0_0 .net *"_s24", 0 0, L_0x1e60270; 1 drivers -v0x1cdf4d0_0 .net *"_s28", 0 0, L_0x1e60200; 1 drivers -v0x1cdf5b0_0 .net *"_s4", 0 0, L_0x1e5f190; 1 drivers -v0x1cdf720_0 .net *"_s8", 0 0, L_0x1e5f4a0; 1 drivers -v0x1cdf800_0 .net "out", 7 0, L_0x1e60600; alias, 1 drivers -L_0x1e5ef00 .part L_0x1e5ea60, 0, 1; -L_0x1e5f0f0 .part v0x1d6daa0_0, 0, 1; -L_0x1e5f250 .part L_0x1e5ea60, 1, 1; -L_0x1e5f3b0 .part v0x1d6daa0_0, 1, 1; -L_0x1e5f560 .part L_0x1e5ea60, 2, 1; -L_0x1e5f6c0 .part v0x1d6daa0_0, 2, 1; -L_0x1e5f870 .part L_0x1e5ea60, 3, 1; -L_0x1e5f9d0 .part v0x1d6daa0_0, 3, 1; -L_0x1e5fbd0 .part L_0x1e5ea60, 4, 1; -L_0x1e5fe40 .part v0x1d6daa0_0, 4, 1; -L_0x1e5ffb0 .part L_0x1e5ea60, 5, 1; -L_0x1e60110 .part v0x1d6daa0_0, 5, 1; -L_0x1e60330 .part L_0x1e5ea60, 6, 1; -L_0x1e60490 .part v0x1d6daa0_0, 6, 1; -LS_0x1e60600_0_0 .concat8 [ 1 1 1 1], L_0x1e5edf0, L_0x1e5f190, L_0x1e5f4a0, L_0x1e5f7b0; -LS_0x1e60600_0_4 .concat8 [ 1 1 1 1], L_0x1e5fb10, L_0x1e5ff40, L_0x1e60270, L_0x1e60200; -L_0x1e60600 .concat8 [ 4 4 0 0], LS_0x1e60600_0_0, LS_0x1e60600_0_4; -L_0x1e609c0 .part L_0x1e5ea60, 7, 1; -L_0x1e60bb0 .part v0x1d6daa0_0, 7, 1; -S_0x1cdc980 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cdcb90 .param/l "i" 0 4 54, +C4<00>; -L_0x1e5edf0/d .functor AND 1, L_0x1e5ef00, L_0x1e5f0f0, C4<1>, C4<1>; -L_0x1e5edf0 .delay 1 (30000,30000,30000) L_0x1e5edf0/d; -v0x1cdcc70_0 .net *"_s0", 0 0, L_0x1e5ef00; 1 drivers -v0x1cdcd50_0 .net *"_s1", 0 0, L_0x1e5f0f0; 1 drivers -S_0x1cdce30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cdd040 .param/l "i" 0 4 54, +C4<01>; -L_0x1e5f190/d .functor AND 1, L_0x1e5f250, L_0x1e5f3b0, C4<1>, C4<1>; -L_0x1e5f190 .delay 1 (30000,30000,30000) L_0x1e5f190/d; -v0x1cdd100_0 .net *"_s0", 0 0, L_0x1e5f250; 1 drivers -v0x1cdd1e0_0 .net *"_s1", 0 0, L_0x1e5f3b0; 1 drivers -S_0x1cdd2c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cdd500 .param/l "i" 0 4 54, +C4<010>; -L_0x1e5f4a0/d .functor AND 1, L_0x1e5f560, L_0x1e5f6c0, C4<1>, C4<1>; -L_0x1e5f4a0 .delay 1 (30000,30000,30000) L_0x1e5f4a0/d; -v0x1cdd5a0_0 .net *"_s0", 0 0, L_0x1e5f560; 1 drivers -v0x1cdd680_0 .net *"_s1", 0 0, L_0x1e5f6c0; 1 drivers -S_0x1cdd760 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cdd970 .param/l "i" 0 4 54, +C4<011>; -L_0x1e5f7b0/d .functor AND 1, L_0x1e5f870, L_0x1e5f9d0, C4<1>, C4<1>; -L_0x1e5f7b0 .delay 1 (30000,30000,30000) L_0x1e5f7b0/d; -v0x1cdda30_0 .net *"_s0", 0 0, L_0x1e5f870; 1 drivers -v0x1cddb10_0 .net *"_s1", 0 0, L_0x1e5f9d0; 1 drivers -S_0x1cddbf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cdde50 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e5fb10/d .functor AND 1, L_0x1e5fbd0, L_0x1e5fe40, C4<1>, C4<1>; -L_0x1e5fb10 .delay 1 (30000,30000,30000) L_0x1e5fb10/d; -v0x1cddf10_0 .net *"_s0", 0 0, L_0x1e5fbd0; 1 drivers -v0x1cddff0_0 .net *"_s1", 0 0, L_0x1e5fe40; 1 drivers -S_0x1cde0d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cde2e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e5ff40/d .functor AND 1, L_0x1e5ffb0, L_0x1e60110, C4<1>, C4<1>; -L_0x1e5ff40 .delay 1 (30000,30000,30000) L_0x1e5ff40/d; -v0x1cde3a0_0 .net *"_s0", 0 0, L_0x1e5ffb0; 1 drivers -v0x1cde480_0 .net *"_s1", 0 0, L_0x1e60110; 1 drivers -S_0x1cde560 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cde770 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e60270/d .functor AND 1, L_0x1e60330, L_0x1e60490, C4<1>, C4<1>; -L_0x1e60270 .delay 1 (30000,30000,30000) L_0x1e60270/d; -v0x1cde830_0 .net *"_s0", 0 0, L_0x1e60330; 1 drivers -v0x1cde910_0 .net *"_s1", 0 0, L_0x1e60490; 1 drivers -S_0x1cde9f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cdc740; - .timescale -9 -12; -P_0x1cdec00 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e60200/d .functor AND 1, L_0x1e609c0, L_0x1e60bb0, C4<1>, C4<1>; -L_0x1e60200 .delay 1 (30000,30000,30000) L_0x1e60200/d; -v0x1cdecc0_0 .net *"_s0", 0 0, L_0x1e609c0; 1 drivers -v0x1cdeda0_0 .net *"_s1", 0 0, L_0x1e60bb0; 1 drivers -S_0x1cdf960 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cdc4f0; +v0x1171ae0_0 .net "A", 7 0, L_0x12f23e0; alias, 1 drivers +v0x1171be0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1171ca0_0 .net *"_s0", 0 0, L_0x12f2770; 1 drivers +v0x1171d60_0 .net *"_s12", 0 0, L_0x12f3130; 1 drivers +v0x1171e40_0 .net *"_s16", 0 0, L_0x12f3490; 1 drivers +v0x1171f70_0 .net *"_s20", 0 0, L_0x12f3860; 1 drivers +v0x1172050_0 .net *"_s24", 0 0, L_0x12f3b90; 1 drivers +v0x1172130_0 .net *"_s28", 0 0, L_0x12f3b20; 1 drivers +v0x1172210_0 .net *"_s4", 0 0, L_0x12f2b10; 1 drivers +v0x1172380_0 .net *"_s8", 0 0, L_0x12f2e20; 1 drivers +v0x1172460_0 .net "out", 7 0, L_0x12f3ea0; alias, 1 drivers +L_0x12f2880 .part L_0x12f23e0, 0, 1; +L_0x12f2a70 .part v0x12010b0_0, 0, 1; +L_0x12f2bd0 .part L_0x12f23e0, 1, 1; +L_0x12f2d30 .part v0x12010b0_0, 1, 1; +L_0x12f2ee0 .part L_0x12f23e0, 2, 1; +L_0x12f3040 .part v0x12010b0_0, 2, 1; +L_0x12f31f0 .part L_0x12f23e0, 3, 1; +L_0x12f3350 .part v0x12010b0_0, 3, 1; +L_0x12f3550 .part L_0x12f23e0, 4, 1; +L_0x12f37c0 .part v0x12010b0_0, 4, 1; +L_0x12f38d0 .part L_0x12f23e0, 5, 1; +L_0x12f3a30 .part v0x12010b0_0, 5, 1; +L_0x12f3c50 .part L_0x12f23e0, 6, 1; +L_0x12f3db0 .part v0x12010b0_0, 6, 1; +LS_0x12f3ea0_0_0 .concat8 [ 1 1 1 1], L_0x12f2770, L_0x12f2b10, L_0x12f2e20, L_0x12f3130; +LS_0x12f3ea0_0_4 .concat8 [ 1 1 1 1], L_0x12f3490, L_0x12f3860, L_0x12f3b90, L_0x12f3b20; +L_0x12f3ea0 .concat8 [ 4 4 0 0], LS_0x12f3ea0_0_0, LS_0x12f3ea0_0_4; +L_0x12f4260 .part L_0x12f23e0, 7, 1; +L_0x12f4450 .part v0x12010b0_0, 7, 1; +S_0x116f5e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x116f7f0 .param/l "i" 0 4 54, +C4<00>; +L_0x12f2770/d .functor AND 1, L_0x12f2880, L_0x12f2a70, C4<1>, C4<1>; +L_0x12f2770 .delay 1 (30000,30000,30000) L_0x12f2770/d; +v0x116f8d0_0 .net *"_s0", 0 0, L_0x12f2880; 1 drivers +v0x116f9b0_0 .net *"_s1", 0 0, L_0x12f2a70; 1 drivers +S_0x116fa90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x116fca0 .param/l "i" 0 4 54, +C4<01>; +L_0x12f2b10/d .functor AND 1, L_0x12f2bd0, L_0x12f2d30, C4<1>, C4<1>; +L_0x12f2b10 .delay 1 (30000,30000,30000) L_0x12f2b10/d; +v0x116fd60_0 .net *"_s0", 0 0, L_0x12f2bd0; 1 drivers +v0x116fe40_0 .net *"_s1", 0 0, L_0x12f2d30; 1 drivers +S_0x116ff20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x1170160 .param/l "i" 0 4 54, +C4<010>; +L_0x12f2e20/d .functor AND 1, L_0x12f2ee0, L_0x12f3040, C4<1>, C4<1>; +L_0x12f2e20 .delay 1 (30000,30000,30000) L_0x12f2e20/d; +v0x1170200_0 .net *"_s0", 0 0, L_0x12f2ee0; 1 drivers +v0x11702e0_0 .net *"_s1", 0 0, L_0x12f3040; 1 drivers +S_0x11703c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x11705d0 .param/l "i" 0 4 54, +C4<011>; +L_0x12f3130/d .functor AND 1, L_0x12f31f0, L_0x12f3350, C4<1>, C4<1>; +L_0x12f3130 .delay 1 (30000,30000,30000) L_0x12f3130/d; +v0x1170690_0 .net *"_s0", 0 0, L_0x12f31f0; 1 drivers +v0x1170770_0 .net *"_s1", 0 0, L_0x12f3350; 1 drivers +S_0x1170850 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x1170ab0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12f3490/d .functor AND 1, L_0x12f3550, L_0x12f37c0, C4<1>, C4<1>; +L_0x12f3490 .delay 1 (30000,30000,30000) L_0x12f3490/d; +v0x1170b70_0 .net *"_s0", 0 0, L_0x12f3550; 1 drivers +v0x1170c50_0 .net *"_s1", 0 0, L_0x12f37c0; 1 drivers +S_0x1170d30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x1170f40 .param/l "i" 0 4 54, +C4<0101>; +L_0x12f3860/d .functor AND 1, L_0x12f38d0, L_0x12f3a30, C4<1>, C4<1>; +L_0x12f3860 .delay 1 (30000,30000,30000) L_0x12f3860/d; +v0x1171000_0 .net *"_s0", 0 0, L_0x12f38d0; 1 drivers +v0x11710e0_0 .net *"_s1", 0 0, L_0x12f3a30; 1 drivers +S_0x11711c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x11713d0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12f3b90/d .functor AND 1, L_0x12f3c50, L_0x12f3db0, C4<1>, C4<1>; +L_0x12f3b90 .delay 1 (30000,30000,30000) L_0x12f3b90/d; +v0x1171490_0 .net *"_s0", 0 0, L_0x12f3c50; 1 drivers +v0x1171570_0 .net *"_s1", 0 0, L_0x12f3db0; 1 drivers +S_0x1171650 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x116f3a0; + .timescale -9 -12; +P_0x1171860 .param/l "i" 0 4 54, +C4<0111>; +L_0x12f3b20/d .functor AND 1, L_0x12f4260, L_0x12f4450, C4<1>, C4<1>; +L_0x12f3b20 .delay 1 (30000,30000,30000) L_0x12f3b20/d; +v0x1171920_0 .net *"_s0", 0 0, L_0x12f4260; 1 drivers +v0x1171a00_0 .net *"_s1", 0 0, L_0x12f4450; 1 drivers +S_0x11725c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x116f150; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e62600/d .functor OR 1, L_0x1e626c0, L_0x1e62870, C4<0>, C4<0>; -L_0x1e62600 .delay 1 (30000,30000,30000) L_0x1e62600/d; -v0x1ce14b0_0 .net *"_s10", 0 0, L_0x1e626c0; 1 drivers -v0x1ce1590_0 .net *"_s12", 0 0, L_0x1e62870; 1 drivers -v0x1ce1670_0 .net "in", 7 0, L_0x1e60600; alias, 1 drivers -v0x1ce1740_0 .net "ors", 1 0, L_0x1e62420; 1 drivers -v0x1ce1800_0 .net "out", 0 0, L_0x1e62600; alias, 1 drivers -L_0x1e617f0 .part L_0x1e60600, 0, 4; -L_0x1e62420 .concat8 [ 1 1 0 0], L_0x1e614e0, L_0x1e62110; -L_0x1e62560 .part L_0x1e60600, 4, 4; -L_0x1e626c0 .part L_0x1e62420, 0, 1; -L_0x1e62870 .part L_0x1e62420, 1, 1; -S_0x1cdfb20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cdf960; +L_0x12f5ea0/d .functor OR 1, L_0x12f5f60, L_0x12f6050, C4<0>, C4<0>; +L_0x12f5ea0 .delay 1 (30000,30000,30000) L_0x12f5ea0/d; +v0x1174110_0 .net *"_s10", 0 0, L_0x12f5f60; 1 drivers +v0x11741f0_0 .net *"_s12", 0 0, L_0x12f6050; 1 drivers +v0x11742d0_0 .net "in", 7 0, L_0x12f3ea0; alias, 1 drivers +v0x11743a0_0 .net "ors", 1 0, L_0x12f5cc0; 1 drivers +v0x1174460_0 .net "out", 0 0, L_0x12f5ea0; alias, 1 drivers +L_0x12f5090 .part L_0x12f3ea0, 0, 4; +L_0x12f5cc0 .concat8 [ 1 1 0 0], L_0x12f4d80, L_0x12f59b0; +L_0x12f5e00 .part L_0x12f3ea0, 4, 4; +L_0x12f5f60 .part L_0x12f5cc0, 0, 1; +L_0x12f6050 .part L_0x12f5cc0, 1, 1; +S_0x1172780 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11725c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e60ca0/d .functor OR 1, L_0x1e60d60, L_0x1e60ec0, C4<0>, C4<0>; -L_0x1e60ca0 .delay 1 (30000,30000,30000) L_0x1e60ca0/d; -L_0x1e610f0/d .functor OR 1, L_0x1e61200, L_0x1e61360, C4<0>, C4<0>; -L_0x1e610f0 .delay 1 (30000,30000,30000) L_0x1e610f0/d; -L_0x1e614e0/d .functor OR 1, L_0x1e61550, L_0x1e61700, C4<0>, C4<0>; -L_0x1e614e0 .delay 1 (30000,30000,30000) L_0x1e614e0/d; -v0x1cdfd70_0 .net *"_s0", 0 0, L_0x1e60ca0; 1 drivers -v0x1cdfe70_0 .net *"_s10", 0 0, L_0x1e61200; 1 drivers -v0x1cdff50_0 .net *"_s12", 0 0, L_0x1e61360; 1 drivers -v0x1ce0010_0 .net *"_s14", 0 0, L_0x1e61550; 1 drivers -v0x1ce00f0_0 .net *"_s16", 0 0, L_0x1e61700; 1 drivers -v0x1ce0220_0 .net *"_s3", 0 0, L_0x1e60d60; 1 drivers -v0x1ce0300_0 .net *"_s5", 0 0, L_0x1e60ec0; 1 drivers -v0x1ce03e0_0 .net *"_s6", 0 0, L_0x1e610f0; 1 drivers -v0x1ce04c0_0 .net "in", 3 0, L_0x1e617f0; 1 drivers -v0x1ce0630_0 .net "ors", 1 0, L_0x1e61000; 1 drivers -v0x1ce0710_0 .net "out", 0 0, L_0x1e614e0; 1 drivers -L_0x1e60d60 .part L_0x1e617f0, 0, 1; -L_0x1e60ec0 .part L_0x1e617f0, 1, 1; -L_0x1e61000 .concat8 [ 1 1 0 0], L_0x1e60ca0, L_0x1e610f0; -L_0x1e61200 .part L_0x1e617f0, 2, 1; -L_0x1e61360 .part L_0x1e617f0, 3, 1; -L_0x1e61550 .part L_0x1e61000, 0, 1; -L_0x1e61700 .part L_0x1e61000, 1, 1; -S_0x1ce0830 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cdf960; +L_0x12f4540/d .functor OR 1, L_0x12f4600, L_0x12f4760, C4<0>, C4<0>; +L_0x12f4540 .delay 1 (30000,30000,30000) L_0x12f4540/d; +L_0x12f4990/d .functor OR 1, L_0x12f4aa0, L_0x12f4c00, C4<0>, C4<0>; +L_0x12f4990 .delay 1 (30000,30000,30000) L_0x12f4990/d; +L_0x12f4d80/d .functor OR 1, L_0x12f4df0, L_0x12f4fa0, C4<0>, C4<0>; +L_0x12f4d80 .delay 1 (30000,30000,30000) L_0x12f4d80/d; +v0x11729d0_0 .net *"_s0", 0 0, L_0x12f4540; 1 drivers +v0x1172ad0_0 .net *"_s10", 0 0, L_0x12f4aa0; 1 drivers +v0x1172bb0_0 .net *"_s12", 0 0, L_0x12f4c00; 1 drivers +v0x1172c70_0 .net *"_s14", 0 0, L_0x12f4df0; 1 drivers +v0x1172d50_0 .net *"_s16", 0 0, L_0x12f4fa0; 1 drivers +v0x1172e80_0 .net *"_s3", 0 0, L_0x12f4600; 1 drivers +v0x1172f60_0 .net *"_s5", 0 0, L_0x12f4760; 1 drivers +v0x1173040_0 .net *"_s6", 0 0, L_0x12f4990; 1 drivers +v0x1173120_0 .net "in", 3 0, L_0x12f5090; 1 drivers +v0x1173290_0 .net "ors", 1 0, L_0x12f48a0; 1 drivers +v0x1173370_0 .net "out", 0 0, L_0x12f4d80; 1 drivers +L_0x12f4600 .part L_0x12f5090, 0, 1; +L_0x12f4760 .part L_0x12f5090, 1, 1; +L_0x12f48a0 .concat8 [ 1 1 0 0], L_0x12f4540, L_0x12f4990; +L_0x12f4aa0 .part L_0x12f5090, 2, 1; +L_0x12f4c00 .part L_0x12f5090, 3, 1; +L_0x12f4df0 .part L_0x12f48a0, 0, 1; +L_0x12f4fa0 .part L_0x12f48a0, 1, 1; +S_0x1173490 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11725c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e61920/d .functor OR 1, L_0x1e61990, L_0x1e61af0, C4<0>, C4<0>; -L_0x1e61920 .delay 1 (30000,30000,30000) L_0x1e61920/d; -L_0x1e61d20/d .functor OR 1, L_0x1e61e30, L_0x1e61f90, C4<0>, C4<0>; -L_0x1e61d20 .delay 1 (30000,30000,30000) L_0x1e61d20/d; -L_0x1e62110/d .functor OR 1, L_0x1e62180, L_0x1e62330, C4<0>, C4<0>; -L_0x1e62110 .delay 1 (30000,30000,30000) L_0x1e62110/d; -v0x1ce09f0_0 .net *"_s0", 0 0, L_0x1e61920; 1 drivers -v0x1ce0af0_0 .net *"_s10", 0 0, L_0x1e61e30; 1 drivers -v0x1ce0bd0_0 .net *"_s12", 0 0, L_0x1e61f90; 1 drivers -v0x1ce0c90_0 .net *"_s14", 0 0, L_0x1e62180; 1 drivers -v0x1ce0d70_0 .net *"_s16", 0 0, L_0x1e62330; 1 drivers -v0x1ce0ea0_0 .net *"_s3", 0 0, L_0x1e61990; 1 drivers -v0x1ce0f80_0 .net *"_s5", 0 0, L_0x1e61af0; 1 drivers -v0x1ce1060_0 .net *"_s6", 0 0, L_0x1e61d20; 1 drivers -v0x1ce1140_0 .net "in", 3 0, L_0x1e62560; 1 drivers -v0x1ce12b0_0 .net "ors", 1 0, L_0x1e61c30; 1 drivers -v0x1ce1390_0 .net "out", 0 0, L_0x1e62110; 1 drivers -L_0x1e61990 .part L_0x1e62560, 0, 1; -L_0x1e61af0 .part L_0x1e62560, 1, 1; -L_0x1e61c30 .concat8 [ 1 1 0 0], L_0x1e61920, L_0x1e61d20; -L_0x1e61e30 .part L_0x1e62560, 2, 1; -L_0x1e61f90 .part L_0x1e62560, 3, 1; -L_0x1e62180 .part L_0x1e61c30, 0, 1; -L_0x1e62330 .part L_0x1e61c30, 1, 1; -S_0x1ce1ca0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cd5620; +L_0x12f51c0/d .functor OR 1, L_0x12f5230, L_0x12f5390, C4<0>, C4<0>; +L_0x12f51c0 .delay 1 (30000,30000,30000) L_0x12f51c0/d; +L_0x12f55c0/d .functor OR 1, L_0x12f56d0, L_0x12f5830, C4<0>, C4<0>; +L_0x12f55c0 .delay 1 (30000,30000,30000) L_0x12f55c0/d; +L_0x12f59b0/d .functor OR 1, L_0x12f5a20, L_0x12f5bd0, C4<0>, C4<0>; +L_0x12f59b0 .delay 1 (30000,30000,30000) L_0x12f59b0/d; +v0x1173650_0 .net *"_s0", 0 0, L_0x12f51c0; 1 drivers +v0x1173750_0 .net *"_s10", 0 0, L_0x12f56d0; 1 drivers +v0x1173830_0 .net *"_s12", 0 0, L_0x12f5830; 1 drivers +v0x11738f0_0 .net *"_s14", 0 0, L_0x12f5a20; 1 drivers +v0x11739d0_0 .net *"_s16", 0 0, L_0x12f5bd0; 1 drivers +v0x1173b00_0 .net *"_s3", 0 0, L_0x12f5230; 1 drivers +v0x1173be0_0 .net *"_s5", 0 0, L_0x12f5390; 1 drivers +v0x1173cc0_0 .net *"_s6", 0 0, L_0x12f55c0; 1 drivers +v0x1173da0_0 .net "in", 3 0, L_0x12f5e00; 1 drivers +v0x1173f10_0 .net "ors", 1 0, L_0x12f54d0; 1 drivers +v0x1173ff0_0 .net "out", 0 0, L_0x12f59b0; 1 drivers +L_0x12f5230 .part L_0x12f5e00, 0, 1; +L_0x12f5390 .part L_0x12f5e00, 1, 1; +L_0x12f54d0 .concat8 [ 1 1 0 0], L_0x12f51c0, L_0x12f55c0; +L_0x12f56d0 .part L_0x12f5e00, 2, 1; +L_0x12f5830 .part L_0x12f5e00, 3, 1; +L_0x12f5a20 .part L_0x12f54d0, 0, 1; +L_0x12f5bd0 .part L_0x12f54d0, 1, 1; +S_0x1174900 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1168280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -13372,80 +13382,80 @@ S_0x1ce1ca0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cd5620; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e5ddd0/d .functor XNOR 1, L_0x1e66500, L_0x1e66660, C4<0>, C4<0>; -L_0x1e5ddd0 .delay 1 (20000,20000,20000) L_0x1e5ddd0/d; -L_0x1e5e040/d .functor AND 1, L_0x1e66500, L_0x1e5cd10, C4<1>, C4<1>; -L_0x1e5e040 .delay 1 (30000,30000,30000) L_0x1e5e040/d; -L_0x1e5e0b0/d .functor AND 1, L_0x1e5ddd0, L_0x1e5c960, C4<1>, C4<1>; -L_0x1e5e0b0 .delay 1 (30000,30000,30000) L_0x1e5e0b0/d; -L_0x1e5e210/d .functor OR 1, L_0x1e5e0b0, L_0x1e5e040, C4<0>, C4<0>; -L_0x1e5e210 .delay 1 (30000,30000,30000) L_0x1e5e210/d; -v0x1ce1f50_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers -v0x1ce2040_0 .net "a_", 0 0, L_0x1e5cc00; alias, 1 drivers -v0x1ce2100_0 .net "b", 0 0, L_0x1e66660; alias, 1 drivers -v0x1ce21f0_0 .net "b_", 0 0, L_0x1e5cd10; alias, 1 drivers -v0x1ce2290_0 .net "carryin", 0 0, L_0x1e5c960; alias, 1 drivers -v0x1ce23d0_0 .net "eq", 0 0, L_0x1e5ddd0; 1 drivers -v0x1ce2490_0 .net "lt", 0 0, L_0x1e5e040; 1 drivers -v0x1ce2550_0 .net "out", 0 0, L_0x1e5e210; 1 drivers -v0x1ce2610_0 .net "w0", 0 0, L_0x1e5e0b0; 1 drivers -S_0x1ce2860 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cd5620; +L_0x12f1750/d .functor XNOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; +L_0x12f1750 .delay 1 (20000,20000,20000) L_0x12f1750/d; +L_0x12f19c0/d .functor AND 1, L_0x12f9d60, L_0x12f0640, C4<1>, C4<1>; +L_0x12f19c0 .delay 1 (30000,30000,30000) L_0x12f19c0/d; +L_0x12f1a30/d .functor AND 1, L_0x12f1750, L_0x12f0290, C4<1>, C4<1>; +L_0x12f1a30 .delay 1 (30000,30000,30000) L_0x12f1a30/d; +L_0x12f1b90/d .functor OR 1, L_0x12f1a30, L_0x12f19c0, C4<0>, C4<0>; +L_0x12f1b90 .delay 1 (30000,30000,30000) L_0x12f1b90/d; +v0x1174bb0_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers +v0x1174ca0_0 .net "a_", 0 0, L_0x12f0530; alias, 1 drivers +v0x1174d60_0 .net "b", 0 0, L_0x12f9ec0; alias, 1 drivers +v0x1174e50_0 .net "b_", 0 0, L_0x12f0640; alias, 1 drivers +v0x1174ef0_0 .net "carryin", 0 0, L_0x12f0290; alias, 1 drivers +v0x1175030_0 .net "eq", 0 0, L_0x12f1750; 1 drivers +v0x11750f0_0 .net "lt", 0 0, L_0x12f19c0; 1 drivers +v0x11751b0_0 .net "out", 0 0, L_0x12f1b90; 1 drivers +v0x1175270_0 .net "w0", 0 0, L_0x12f1a30; 1 drivers +S_0x11754c0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1168280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e5dbb0/d .functor OR 1, L_0x1e5d700, L_0x1ce3ac0, C4<0>, C4<0>; -L_0x1e5dbb0 .delay 1 (30000,30000,30000) L_0x1e5dbb0/d; -v0x1ce3650_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers -v0x1ce37a0_0 .net "b", 0 0, L_0x1e5cd10; alias, 1 drivers -v0x1ce3860_0 .net "c1", 0 0, L_0x1e5d700; 1 drivers -v0x1ce3900_0 .net "c2", 0 0, L_0x1ce3ac0; 1 drivers -v0x1ce39d0_0 .net "carryin", 0 0, L_0x1e5c960; alias, 1 drivers -v0x1ce3b50_0 .net "carryout", 0 0, L_0x1e5dbb0; 1 drivers -v0x1ce3bf0_0 .net "s1", 0 0, L_0x1e5d640; 1 drivers -v0x1ce3c90_0 .net "sum", 0 0, L_0x1e5d860; 1 drivers -S_0x1ce2ab0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ce2860; +L_0x12f1530/d .functor OR 1, L_0x12f1030, L_0x1176720, C4<0>, C4<0>; +L_0x12f1530 .delay 1 (30000,30000,30000) L_0x12f1530/d; +v0x11762b0_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers +v0x1176400_0 .net "b", 0 0, L_0x12f0640; alias, 1 drivers +v0x11764c0_0 .net "c1", 0 0, L_0x12f1030; 1 drivers +v0x1176560_0 .net "c2", 0 0, L_0x1176720; 1 drivers +v0x1176630_0 .net "carryin", 0 0, L_0x12f0290; alias, 1 drivers +v0x11767b0_0 .net "carryout", 0 0, L_0x12f1530; 1 drivers +v0x1176850_0 .net "s1", 0 0, L_0x12f0f70; 1 drivers +v0x11768f0_0 .net "sum", 0 0, L_0x12f1190; 1 drivers +S_0x1175710 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11754c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e5d640/d .functor XOR 1, L_0x1e66500, L_0x1e5cd10, C4<0>, C4<0>; -L_0x1e5d640 .delay 1 (30000,30000,30000) L_0x1e5d640/d; -L_0x1e5d700/d .functor AND 1, L_0x1e66500, L_0x1e5cd10, C4<1>, C4<1>; -L_0x1e5d700 .delay 1 (30000,30000,30000) L_0x1e5d700/d; -v0x1ce2d10_0 .net "a", 0 0, L_0x1e66500; alias, 1 drivers -v0x1ce2dd0_0 .net "b", 0 0, L_0x1e5cd10; alias, 1 drivers -v0x1ce2e90_0 .net "carryout", 0 0, L_0x1e5d700; alias, 1 drivers -v0x1ce2f30_0 .net "sum", 0 0, L_0x1e5d640; alias, 1 drivers -S_0x1ce3060 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ce2860; +L_0x12f0f70/d .functor XOR 1, L_0x12f9d60, L_0x12f0640, C4<0>, C4<0>; +L_0x12f0f70 .delay 1 (30000,30000,30000) L_0x12f0f70/d; +L_0x12f1030/d .functor AND 1, L_0x12f9d60, L_0x12f0640, C4<1>, C4<1>; +L_0x12f1030 .delay 1 (30000,30000,30000) L_0x12f1030/d; +v0x1175970_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers +v0x1175a30_0 .net "b", 0 0, L_0x12f0640; alias, 1 drivers +v0x1175af0_0 .net "carryout", 0 0, L_0x12f1030; alias, 1 drivers +v0x1175b90_0 .net "sum", 0 0, L_0x12f0f70; alias, 1 drivers +S_0x1175cc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11754c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e5d860/d .functor XOR 1, L_0x1e5d640, L_0x1e5c960, C4<0>, C4<0>; -L_0x1e5d860 .delay 1 (30000,30000,30000) L_0x1e5d860/d; -L_0x1ce3ac0/d .functor AND 1, L_0x1e5d640, L_0x1e5c960, C4<1>, C4<1>; -L_0x1ce3ac0 .delay 1 (30000,30000,30000) L_0x1ce3ac0/d; -v0x1ce32c0_0 .net "a", 0 0, L_0x1e5d640; alias, 1 drivers -v0x1ce3390_0 .net "b", 0 0, L_0x1e5c960; alias, 1 drivers -v0x1ce3430_0 .net "carryout", 0 0, L_0x1ce3ac0; alias, 1 drivers -v0x1ce3500_0 .net "sum", 0 0, L_0x1e5d860; alias, 1 drivers -S_0x1ce50b0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cd5350; - .timescale -9 -12; -L_0x7f72592dbb18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbb60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e665a0/d .functor OR 1, L_0x7f72592dbb18, L_0x7f72592dbb60, C4<0>, C4<0>; -L_0x1e665a0 .delay 1 (30000,30000,30000) L_0x1e665a0/d; -v0x1ce52a0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbb18; 1 drivers -v0x1ce5380_0 .net/2u *"_s2", 0 0, L_0x7f72592dbb60; 1 drivers -S_0x1ce5460 .scope generate, "alu_slices[25]" "alu_slices[25]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1ce5670 .param/l "i" 0 3 37, +C4<011001>; -S_0x1ce5730 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ce5460; +L_0x12f1190/d .functor XOR 1, L_0x12f0f70, L_0x12f0290, C4<0>, C4<0>; +L_0x12f1190 .delay 1 (30000,30000,30000) L_0x12f1190/d; +L_0x1176720/d .functor AND 1, L_0x12f0f70, L_0x12f0290, C4<1>, C4<1>; +L_0x1176720 .delay 1 (30000,30000,30000) L_0x1176720/d; +v0x1175f20_0 .net "a", 0 0, L_0x12f0f70; alias, 1 drivers +v0x1175ff0_0 .net "b", 0 0, L_0x12f0290; alias, 1 drivers +v0x1176090_0 .net "carryout", 0 0, L_0x1176720; alias, 1 drivers +v0x1176160_0 .net "sum", 0 0, L_0x12f1190; alias, 1 drivers +S_0x1177d10 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1167fb0; + .timescale -9 -12; +L_0x2b0ab3d06b18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06b60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12f9e00/d .functor OR 1, L_0x2b0ab3d06b18, L_0x2b0ab3d06b60, C4<0>, C4<0>; +L_0x12f9e00 .delay 1 (30000,30000,30000) L_0x12f9e00/d; +v0x1177f00_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06b18; 1 drivers +v0x1177fe0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06b60; 1 drivers +S_0x11780c0 .scope generate, "alu_slices[25]" "alu_slices[25]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11782d0 .param/l "i" 0 3 41, +C4<011001>; +S_0x1178390 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11780c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -13454,445 +13464,445 @@ S_0x1ce5730 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1ce5460; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e5caf0/d .functor NOT 1, L_0x1e70190, C4<0>, C4<0>, C4<0>; -L_0x1e5caf0 .delay 1 (10000,10000,10000) L_0x1e5caf0/d; -L_0x1e66a00/d .functor NOT 1, L_0x1e66700, C4<0>, C4<0>, C4<0>; -L_0x1e66a00 .delay 1 (10000,10000,10000) L_0x1e66a00/d; -L_0x1e67940/d .functor XOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; -L_0x1e67940 .delay 1 (30000,30000,30000) L_0x1e67940/d; -L_0x7f72592dbba8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbbf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e67ff0/d .functor OR 1, L_0x7f72592dbba8, L_0x7f72592dbbf0, C4<0>, C4<0>; -L_0x1e67ff0 .delay 1 (30000,30000,30000) L_0x1e67ff0/d; -L_0x1e681f0/d .functor AND 1, L_0x1e70190, L_0x1e66700, C4<1>, C4<1>; -L_0x1e681f0 .delay 1 (30000,30000,30000) L_0x1e681f0/d; -L_0x1e682b0/d .functor NAND 1, L_0x1e70190, L_0x1e66700, C4<1>, C4<1>; -L_0x1e682b0 .delay 1 (20000,20000,20000) L_0x1e682b0/d; -L_0x1e68410/d .functor XOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; -L_0x1e68410 .delay 1 (20000,20000,20000) L_0x1e68410/d; -L_0x1e688c0/d .functor OR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; -L_0x1e688c0 .delay 1 (30000,30000,30000) L_0x1e688c0/d; -L_0x1e70090/d .functor NOT 1, L_0x1e6c230, C4<0>, C4<0>, C4<0>; -L_0x1e70090 .delay 1 (10000,10000,10000) L_0x1e70090/d; -v0x1cf4620_0 .net "A", 0 0, L_0x1e70190; 1 drivers -v0x1cf46e0_0 .net "A_", 0 0, L_0x1e5caf0; 1 drivers -v0x1cf47a0_0 .net "B", 0 0, L_0x1e66700; 1 drivers -v0x1cf4870_0 .net "B_", 0 0, L_0x1e66a00; 1 drivers -v0x1cf4910_0 .net *"_s12", 0 0, L_0x1e67ff0; 1 drivers -v0x1cf4a00_0 .net/2s *"_s14", 0 0, L_0x7f72592dbba8; 1 drivers -v0x1cf4ac0_0 .net/2s *"_s16", 0 0, L_0x7f72592dbbf0; 1 drivers -v0x1cf4ba0_0 .net *"_s18", 0 0, L_0x1e681f0; 1 drivers -v0x1cf4c80_0 .net *"_s20", 0 0, L_0x1e682b0; 1 drivers -v0x1cf4df0_0 .net *"_s22", 0 0, L_0x1e68410; 1 drivers -v0x1cf4ed0_0 .net *"_s24", 0 0, L_0x1e688c0; 1 drivers -o0x7f725932f798 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1cf4fb0_0 name=_s30 -o0x7f725932f7c8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1cf5090_0 name=_s32 -v0x1cf5170_0 .net *"_s8", 0 0, L_0x1e67940; 1 drivers -v0x1cf5250_0 .net "carryin", 0 0, L_0x1e667a0; 1 drivers -v0x1cf52f0_0 .net "carryout", 0 0, L_0x1e6fd30; 1 drivers -v0x1cf5390_0 .net "carryouts", 7 0, L_0x1ec1640; 1 drivers -v0x1cf5540_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cf55e0_0 .net "result", 0 0, L_0x1e6c230; 1 drivers -v0x1cf56d0_0 .net "results", 7 0, L_0x1e68690; 1 drivers -v0x1cf57e0_0 .net "zero", 0 0, L_0x1e70090; 1 drivers -LS_0x1e68690_0_0 .concat8 [ 1 1 1 1], L_0x1e66e60, L_0x1e67490, L_0x1e67940, L_0x1e67ff0; -LS_0x1e68690_0_4 .concat8 [ 1 1 1 1], L_0x1e681f0, L_0x1e682b0, L_0x1e68410, L_0x1e688c0; -L_0x1e68690 .concat8 [ 4 4 0 0], LS_0x1e68690_0_0, LS_0x1e68690_0_4; -LS_0x1ec1640_0_0 .concat [ 1 1 1 1], L_0x1e67110, L_0x1e677e0, o0x7f725932f798, L_0x1e67e40; -LS_0x1ec1640_0_4 .concat [ 4 0 0 0], o0x7f725932f7c8; -L_0x1ec1640 .concat [ 4 4 0 0], LS_0x1ec1640_0_0, LS_0x1ec1640_0_4; -S_0x1ce59b0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1ce5730; +L_0x12f0420/d .functor NOT 1, L_0x13039c0, C4<0>, C4<0>, C4<0>; +L_0x12f0420 .delay 1 (10000,10000,10000) L_0x12f0420/d; +L_0x12fa260/d .functor NOT 1, L_0x12f9f60, C4<0>, C4<0>, C4<0>; +L_0x12fa260 .delay 1 (10000,10000,10000) L_0x12fa260/d; +L_0x12fb1a0/d .functor XOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; +L_0x12fb1a0 .delay 1 (30000,30000,30000) L_0x12fb1a0/d; +L_0x2b0ab3d06ba8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06bf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x12fb850/d .functor OR 1, L_0x2b0ab3d06ba8, L_0x2b0ab3d06bf0, C4<0>, C4<0>; +L_0x12fb850 .delay 1 (30000,30000,30000) L_0x12fb850/d; +L_0x12fba50/d .functor AND 1, L_0x13039c0, L_0x12f9f60, C4<1>, C4<1>; +L_0x12fba50 .delay 1 (30000,30000,30000) L_0x12fba50/d; +L_0x12fbb10/d .functor NAND 1, L_0x13039c0, L_0x12f9f60, C4<1>, C4<1>; +L_0x12fbb10 .delay 1 (20000,20000,20000) L_0x12fbb10/d; +L_0x12fbc70/d .functor XOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; +L_0x12fbc70 .delay 1 (20000,20000,20000) L_0x12fbc70/d; +L_0x12fc120/d .functor OR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; +L_0x12fc120 .delay 1 (30000,30000,30000) L_0x12fc120/d; +L_0x13038c0/d .functor NOT 1, L_0x12ffa90, C4<0>, C4<0>, C4<0>; +L_0x13038c0 .delay 1 (10000,10000,10000) L_0x13038c0/d; +v0x11872c0_0 .net "A", 0 0, L_0x13039c0; 1 drivers +v0x1187380_0 .net "A_", 0 0, L_0x12f0420; 1 drivers +v0x1187440_0 .net "B", 0 0, L_0x12f9f60; 1 drivers +v0x1187510_0 .net "B_", 0 0, L_0x12fa260; 1 drivers +v0x11875b0_0 .net *"_s12", 0 0, L_0x12fb850; 1 drivers +v0x11876a0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06ba8; 1 drivers +v0x1187760_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06bf0; 1 drivers +v0x1187840_0 .net *"_s18", 0 0, L_0x12fba50; 1 drivers +v0x1187920_0 .net *"_s20", 0 0, L_0x12fbb10; 1 drivers +v0x1187a90_0 .net *"_s22", 0 0, L_0x12fbc70; 1 drivers +v0x1187b70_0 .net *"_s24", 0 0, L_0x12fc120; 1 drivers +o0x2b0ab3ce0798 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1187c50_0 name=_s30 +o0x2b0ab3ce07c8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1187d30_0 name=_s32 +v0x1187e10_0 .net *"_s8", 0 0, L_0x12fb1a0; 1 drivers +v0x1187ef0_0 .net "carryin", 0 0, L_0x12fa000; 1 drivers +v0x1187f90_0 .net "carryout", 0 0, L_0x1303560; 1 drivers +v0x1188030_0 .net "carryouts", 7 0, L_0x1355970; 1 drivers +v0x11881e0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1188280_0 .net "result", 0 0, L_0x12ffa90; 1 drivers +v0x1188370_0 .net "results", 7 0, L_0x12fbef0; 1 drivers +v0x1188480_0 .net "zero", 0 0, L_0x13038c0; 1 drivers +LS_0x12fbef0_0_0 .concat8 [ 1 1 1 1], L_0x12fa6c0, L_0x12facf0, L_0x12fb1a0, L_0x12fb850; +LS_0x12fbef0_0_4 .concat8 [ 1 1 1 1], L_0x12fba50, L_0x12fbb10, L_0x12fbc70, L_0x12fc120; +L_0x12fbef0 .concat8 [ 4 4 0 0], LS_0x12fbef0_0_0, LS_0x12fbef0_0_4; +LS_0x1355970_0_0 .concat [ 1 1 1 1], L_0x12fa970, L_0x12fb040, o0x2b0ab3ce0798, L_0x12fb6a0; +LS_0x1355970_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce07c8; +L_0x1355970 .concat [ 4 4 0 0], LS_0x1355970_0_0, LS_0x1355970_0_4; +S_0x1178610 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1178390; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e67110/d .functor OR 1, L_0x1e66bf0, L_0x1e66fb0, C4<0>, C4<0>; -L_0x1e67110 .delay 1 (30000,30000,30000) L_0x1e67110/d; -v0x1ce67e0_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers -v0x1ce68a0_0 .net "b", 0 0, L_0x1e66700; alias, 1 drivers -v0x1ce6970_0 .net "c1", 0 0, L_0x1e66bf0; 1 drivers -v0x1ce6a70_0 .net "c2", 0 0, L_0x1e66fb0; 1 drivers -v0x1ce6b40_0 .net "carryin", 0 0, L_0x1e667a0; alias, 1 drivers -v0x1ce6c30_0 .net "carryout", 0 0, L_0x1e67110; 1 drivers -v0x1ce6cd0_0 .net "s1", 0 0, L_0x1e60580; 1 drivers -v0x1ce6dc0_0 .net "sum", 0 0, L_0x1e66e60; 1 drivers -S_0x1ce5c20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1ce59b0; +L_0x12fa970/d .functor OR 1, L_0x12fa450, L_0x12fa810, C4<0>, C4<0>; +L_0x12fa970 .delay 1 (30000,30000,30000) L_0x12fa970/d; +v0x1179440_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers +v0x1179500_0 .net "b", 0 0, L_0x12f9f60; alias, 1 drivers +v0x11795d0_0 .net "c1", 0 0, L_0x12fa450; 1 drivers +v0x11796d0_0 .net "c2", 0 0, L_0x12fa810; 1 drivers +v0x11797a0_0 .net "carryin", 0 0, L_0x12fa000; alias, 1 drivers +v0x1179890_0 .net "carryout", 0 0, L_0x12fa970; 1 drivers +v0x1179930_0 .net "s1", 0 0, L_0x12f7880; 1 drivers +v0x1179a20_0 .net "sum", 0 0, L_0x12fa6c0; 1 drivers +S_0x1178880 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1178610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e60580/d .functor XOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; -L_0x1e60580 .delay 1 (30000,30000,30000) L_0x1e60580/d; -L_0x1e66bf0/d .functor AND 1, L_0x1e70190, L_0x1e66700, C4<1>, C4<1>; -L_0x1e66bf0 .delay 1 (30000,30000,30000) L_0x1e66bf0/d; -v0x1ce5e80_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers -v0x1ce5f60_0 .net "b", 0 0, L_0x1e66700; alias, 1 drivers -v0x1ce6020_0 .net "carryout", 0 0, L_0x1e66bf0; alias, 1 drivers -v0x1ce60c0_0 .net "sum", 0 0, L_0x1e60580; alias, 1 drivers -S_0x1ce6200 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1ce59b0; +L_0x12f7880/d .functor XOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; +L_0x12f7880 .delay 1 (30000,30000,30000) L_0x12f7880/d; +L_0x12fa450/d .functor AND 1, L_0x13039c0, L_0x12f9f60, C4<1>, C4<1>; +L_0x12fa450 .delay 1 (30000,30000,30000) L_0x12fa450/d; +v0x1178ae0_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers +v0x1178bc0_0 .net "b", 0 0, L_0x12f9f60; alias, 1 drivers +v0x1178c80_0 .net "carryout", 0 0, L_0x12fa450; alias, 1 drivers +v0x1178d20_0 .net "sum", 0 0, L_0x12f7880; alias, 1 drivers +S_0x1178e60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1178610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e66e60/d .functor XOR 1, L_0x1e60580, L_0x1e667a0, C4<0>, C4<0>; -L_0x1e66e60 .delay 1 (30000,30000,30000) L_0x1e66e60/d; -L_0x1e66fb0/d .functor AND 1, L_0x1e60580, L_0x1e667a0, C4<1>, C4<1>; -L_0x1e66fb0 .delay 1 (30000,30000,30000) L_0x1e66fb0/d; -v0x1ce6460_0 .net "a", 0 0, L_0x1e60580; alias, 1 drivers -v0x1ce6500_0 .net "b", 0 0, L_0x1e667a0; alias, 1 drivers -v0x1ce65a0_0 .net "carryout", 0 0, L_0x1e66fb0; alias, 1 drivers -v0x1ce6670_0 .net "sum", 0 0, L_0x1e66e60; alias, 1 drivers -S_0x1ce6e90 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1ce5730; +L_0x12fa6c0/d .functor XOR 1, L_0x12f7880, L_0x12fa000, C4<0>, C4<0>; +L_0x12fa6c0 .delay 1 (30000,30000,30000) L_0x12fa6c0/d; +L_0x12fa810/d .functor AND 1, L_0x12f7880, L_0x12fa000, C4<1>, C4<1>; +L_0x12fa810 .delay 1 (30000,30000,30000) L_0x12fa810/d; +v0x11790c0_0 .net "a", 0 0, L_0x12f7880; alias, 1 drivers +v0x1179160_0 .net "b", 0 0, L_0x12fa000; alias, 1 drivers +v0x1179200_0 .net "carryout", 0 0, L_0x12fa810; alias, 1 drivers +v0x11792d0_0 .net "sum", 0 0, L_0x12fa6c0; alias, 1 drivers +S_0x1179af0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1178390; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cec280_0 .net "ands", 7 0, L_0x1e6dd30; 1 drivers -v0x1cec390_0 .net "in", 7 0, L_0x1ec1640; alias, 1 drivers -v0x1cec450_0 .net "out", 0 0, L_0x1e6fd30; alias, 1 drivers -v0x1cec520_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1ce70b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1ce6e90; +v0x117eee0_0 .net "ands", 7 0, L_0x1301560; 1 drivers +v0x117eff0_0 .net "in", 7 0, L_0x1355970; alias, 1 drivers +v0x117f0b0_0 .net "out", 0 0, L_0x1303560; alias, 1 drivers +v0x117f180_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x1179d10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1179af0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1ce97e0_0 .net "A", 7 0, L_0x1ec1640; alias, 1 drivers -v0x1ce98e0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1ce99a0_0 .net *"_s0", 0 0, L_0x1e6c590; 1 drivers -v0x1ce9a60_0 .net *"_s12", 0 0, L_0x1e6cf00; 1 drivers -v0x1ce9b40_0 .net *"_s16", 0 0, L_0x1e6d2c0; 1 drivers -v0x1ce9c70_0 .net *"_s20", 0 0, L_0x1e6d600; 1 drivers -v0x1ce9d50_0 .net *"_s24", 0 0, L_0x1e6da20; 1 drivers -v0x1ce9e30_0 .net *"_s28", 0 0, L_0x1e6d9b0; 1 drivers -v0x1ce9f10_0 .net *"_s4", 0 0, L_0x1e6c8a0; 1 drivers -v0x1cea080_0 .net *"_s8", 0 0, L_0x1e6cbf0; 1 drivers -v0x1cea160_0 .net "out", 7 0, L_0x1e6dd30; alias, 1 drivers -L_0x1e6c650 .part L_0x1ec1640, 0, 1; -L_0x1e6c7b0 .part v0x1d6daa0_0, 0, 1; -L_0x1e6c960 .part L_0x1ec1640, 1, 1; -L_0x1e6cb50 .part v0x1d6daa0_0, 1, 1; -L_0x1e6ccb0 .part L_0x1ec1640, 2, 1; -L_0x1e6ce10 .part v0x1d6daa0_0, 2, 1; -L_0x1e6d020 .part L_0x1ec1640, 3, 1; -L_0x1e6d180 .part v0x1d6daa0_0, 3, 1; -L_0x1e6d3b0 .part L_0x1ec1640, 4, 1; -L_0x1e6d510 .part v0x1d6daa0_0, 4, 1; -L_0x1e6d6a0 .part L_0x1ec1640, 5, 1; -L_0x1e6d910 .part v0x1d6daa0_0, 5, 1; -L_0x1e6dae0 .part L_0x1ec1640, 6, 1; -L_0x1e6dc40 .part v0x1d6daa0_0, 6, 1; -LS_0x1e6dd30_0_0 .concat8 [ 1 1 1 1], L_0x1e6c590, L_0x1e6c8a0, L_0x1e6cbf0, L_0x1e6cf00; -LS_0x1e6dd30_0_4 .concat8 [ 1 1 1 1], L_0x1e6d2c0, L_0x1e6d600, L_0x1e6da20, L_0x1e6d9b0; -L_0x1e6dd30 .concat8 [ 4 4 0 0], LS_0x1e6dd30_0_0, LS_0x1e6dd30_0_4; -L_0x1e6e0f0 .part L_0x1ec1640, 7, 1; -L_0x1e6e2e0 .part v0x1d6daa0_0, 7, 1; -S_0x1ce7310 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce7520 .param/l "i" 0 4 54, +C4<00>; -L_0x1e6c590/d .functor AND 1, L_0x1e6c650, L_0x1e6c7b0, C4<1>, C4<1>; -L_0x1e6c590 .delay 1 (30000,30000,30000) L_0x1e6c590/d; -v0x1ce7600_0 .net *"_s0", 0 0, L_0x1e6c650; 1 drivers -v0x1ce76e0_0 .net *"_s1", 0 0, L_0x1e6c7b0; 1 drivers -S_0x1ce77c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce79d0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e6c8a0/d .functor AND 1, L_0x1e6c960, L_0x1e6cb50, C4<1>, C4<1>; -L_0x1e6c8a0 .delay 1 (30000,30000,30000) L_0x1e6c8a0/d; -v0x1ce7a90_0 .net *"_s0", 0 0, L_0x1e6c960; 1 drivers -v0x1ce7b70_0 .net *"_s1", 0 0, L_0x1e6cb50; 1 drivers -S_0x1ce7c50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce7e60 .param/l "i" 0 4 54, +C4<010>; -L_0x1e6cbf0/d .functor AND 1, L_0x1e6ccb0, L_0x1e6ce10, C4<1>, C4<1>; -L_0x1e6cbf0 .delay 1 (30000,30000,30000) L_0x1e6cbf0/d; -v0x1ce7f00_0 .net *"_s0", 0 0, L_0x1e6ccb0; 1 drivers -v0x1ce7fe0_0 .net *"_s1", 0 0, L_0x1e6ce10; 1 drivers -S_0x1ce80c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce82d0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e6cf00/d .functor AND 1, L_0x1e6d020, L_0x1e6d180, C4<1>, C4<1>; -L_0x1e6cf00 .delay 1 (30000,30000,30000) L_0x1e6cf00/d; -v0x1ce8390_0 .net *"_s0", 0 0, L_0x1e6d020; 1 drivers -v0x1ce8470_0 .net *"_s1", 0 0, L_0x1e6d180; 1 drivers -S_0x1ce8550 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce87b0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e6d2c0/d .functor AND 1, L_0x1e6d3b0, L_0x1e6d510, C4<1>, C4<1>; -L_0x1e6d2c0 .delay 1 (30000,30000,30000) L_0x1e6d2c0/d; -v0x1ce8870_0 .net *"_s0", 0 0, L_0x1e6d3b0; 1 drivers -v0x1ce8950_0 .net *"_s1", 0 0, L_0x1e6d510; 1 drivers -S_0x1ce8a30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce8c40 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e6d600/d .functor AND 1, L_0x1e6d6a0, L_0x1e6d910, C4<1>, C4<1>; -L_0x1e6d600 .delay 1 (30000,30000,30000) L_0x1e6d600/d; -v0x1ce8d00_0 .net *"_s0", 0 0, L_0x1e6d6a0; 1 drivers -v0x1ce8de0_0 .net *"_s1", 0 0, L_0x1e6d910; 1 drivers -S_0x1ce8ec0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce90d0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e6da20/d .functor AND 1, L_0x1e6dae0, L_0x1e6dc40, C4<1>, C4<1>; -L_0x1e6da20 .delay 1 (30000,30000,30000) L_0x1e6da20/d; -v0x1ce9190_0 .net *"_s0", 0 0, L_0x1e6dae0; 1 drivers -v0x1ce9270_0 .net *"_s1", 0 0, L_0x1e6dc40; 1 drivers -S_0x1ce9350 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1ce70b0; - .timescale -9 -12; -P_0x1ce9560 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e6d9b0/d .functor AND 1, L_0x1e6e0f0, L_0x1e6e2e0, C4<1>, C4<1>; -L_0x1e6d9b0 .delay 1 (30000,30000,30000) L_0x1e6d9b0/d; -v0x1ce9620_0 .net *"_s0", 0 0, L_0x1e6e0f0; 1 drivers -v0x1ce9700_0 .net *"_s1", 0 0, L_0x1e6e2e0; 1 drivers -S_0x1cea2c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1ce6e90; +v0x117c440_0 .net "A", 7 0, L_0x1355970; alias, 1 drivers +v0x117c540_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x117c600_0 .net *"_s0", 0 0, L_0x12ffdf0; 1 drivers +v0x117c6c0_0 .net *"_s12", 0 0, L_0x1300760; 1 drivers +v0x117c7a0_0 .net *"_s16", 0 0, L_0x1300ac0; 1 drivers +v0x117c8d0_0 .net *"_s20", 0 0, L_0x1300e30; 1 drivers +v0x117c9b0_0 .net *"_s24", 0 0, L_0x1301250; 1 drivers +v0x117ca90_0 .net *"_s28", 0 0, L_0x13011e0; 1 drivers +v0x117cb70_0 .net *"_s4", 0 0, L_0x1300100; 1 drivers +v0x117cce0_0 .net *"_s8", 0 0, L_0x1300450; 1 drivers +v0x117cdc0_0 .net "out", 7 0, L_0x1301560; alias, 1 drivers +L_0x12ffeb0 .part L_0x1355970, 0, 1; +L_0x1300010 .part v0x12010b0_0, 0, 1; +L_0x13001c0 .part L_0x1355970, 1, 1; +L_0x13003b0 .part v0x12010b0_0, 1, 1; +L_0x1300510 .part L_0x1355970, 2, 1; +L_0x1300670 .part v0x12010b0_0, 2, 1; +L_0x1300820 .part L_0x1355970, 3, 1; +L_0x1300980 .part v0x12010b0_0, 3, 1; +L_0x1300be0 .part L_0x1355970, 4, 1; +L_0x1300d40 .part v0x12010b0_0, 4, 1; +L_0x1300ed0 .part L_0x1355970, 5, 1; +L_0x1301140 .part v0x12010b0_0, 5, 1; +L_0x1301310 .part L_0x1355970, 6, 1; +L_0x1301470 .part v0x12010b0_0, 6, 1; +LS_0x1301560_0_0 .concat8 [ 1 1 1 1], L_0x12ffdf0, L_0x1300100, L_0x1300450, L_0x1300760; +LS_0x1301560_0_4 .concat8 [ 1 1 1 1], L_0x1300ac0, L_0x1300e30, L_0x1301250, L_0x13011e0; +L_0x1301560 .concat8 [ 4 4 0 0], LS_0x1301560_0_0, LS_0x1301560_0_4; +L_0x1301920 .part L_0x1355970, 7, 1; +L_0x1301b10 .part v0x12010b0_0, 7, 1; +S_0x1179f70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117a180 .param/l "i" 0 4 54, +C4<00>; +L_0x12ffdf0/d .functor AND 1, L_0x12ffeb0, L_0x1300010, C4<1>, C4<1>; +L_0x12ffdf0 .delay 1 (30000,30000,30000) L_0x12ffdf0/d; +v0x117a260_0 .net *"_s0", 0 0, L_0x12ffeb0; 1 drivers +v0x117a340_0 .net *"_s1", 0 0, L_0x1300010; 1 drivers +S_0x117a420 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117a630 .param/l "i" 0 4 54, +C4<01>; +L_0x1300100/d .functor AND 1, L_0x13001c0, L_0x13003b0, C4<1>, C4<1>; +L_0x1300100 .delay 1 (30000,30000,30000) L_0x1300100/d; +v0x117a6f0_0 .net *"_s0", 0 0, L_0x13001c0; 1 drivers +v0x117a7d0_0 .net *"_s1", 0 0, L_0x13003b0; 1 drivers +S_0x117a8b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117aac0 .param/l "i" 0 4 54, +C4<010>; +L_0x1300450/d .functor AND 1, L_0x1300510, L_0x1300670, C4<1>, C4<1>; +L_0x1300450 .delay 1 (30000,30000,30000) L_0x1300450/d; +v0x117ab60_0 .net *"_s0", 0 0, L_0x1300510; 1 drivers +v0x117ac40_0 .net *"_s1", 0 0, L_0x1300670; 1 drivers +S_0x117ad20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117af30 .param/l "i" 0 4 54, +C4<011>; +L_0x1300760/d .functor AND 1, L_0x1300820, L_0x1300980, C4<1>, C4<1>; +L_0x1300760 .delay 1 (30000,30000,30000) L_0x1300760/d; +v0x117aff0_0 .net *"_s0", 0 0, L_0x1300820; 1 drivers +v0x117b0d0_0 .net *"_s1", 0 0, L_0x1300980; 1 drivers +S_0x117b1b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117b410 .param/l "i" 0 4 54, +C4<0100>; +L_0x1300ac0/d .functor AND 1, L_0x1300be0, L_0x1300d40, C4<1>, C4<1>; +L_0x1300ac0 .delay 1 (30000,30000,30000) L_0x1300ac0/d; +v0x117b4d0_0 .net *"_s0", 0 0, L_0x1300be0; 1 drivers +v0x117b5b0_0 .net *"_s1", 0 0, L_0x1300d40; 1 drivers +S_0x117b690 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117b8a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1300e30/d .functor AND 1, L_0x1300ed0, L_0x1301140, C4<1>, C4<1>; +L_0x1300e30 .delay 1 (30000,30000,30000) L_0x1300e30/d; +v0x117b960_0 .net *"_s0", 0 0, L_0x1300ed0; 1 drivers +v0x117ba40_0 .net *"_s1", 0 0, L_0x1301140; 1 drivers +S_0x117bb20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117bd30 .param/l "i" 0 4 54, +C4<0110>; +L_0x1301250/d .functor AND 1, L_0x1301310, L_0x1301470, C4<1>, C4<1>; +L_0x1301250 .delay 1 (30000,30000,30000) L_0x1301250/d; +v0x117bdf0_0 .net *"_s0", 0 0, L_0x1301310; 1 drivers +v0x117bed0_0 .net *"_s1", 0 0, L_0x1301470; 1 drivers +S_0x117bfb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1179d10; + .timescale -9 -12; +P_0x117c1c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x13011e0/d .functor AND 1, L_0x1301920, L_0x1301b10, C4<1>, C4<1>; +L_0x13011e0 .delay 1 (30000,30000,30000) L_0x13011e0/d; +v0x117c280_0 .net *"_s0", 0 0, L_0x1301920; 1 drivers +v0x117c360_0 .net *"_s1", 0 0, L_0x1301b10; 1 drivers +S_0x117cf20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1179af0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e6fd30/d .functor OR 1, L_0x1e6fdf0, L_0x1e6ffa0, C4<0>, C4<0>; -L_0x1e6fd30 .delay 1 (30000,30000,30000) L_0x1e6fd30/d; -v0x1cebe10_0 .net *"_s10", 0 0, L_0x1e6fdf0; 1 drivers -v0x1cebef0_0 .net *"_s12", 0 0, L_0x1e6ffa0; 1 drivers -v0x1cebfd0_0 .net "in", 7 0, L_0x1e6dd30; alias, 1 drivers -v0x1cec0a0_0 .net "ors", 1 0, L_0x1e6fb50; 1 drivers -v0x1cec160_0 .net "out", 0 0, L_0x1e6fd30; alias, 1 drivers -L_0x1e6ef20 .part L_0x1e6dd30, 0, 4; -L_0x1e6fb50 .concat8 [ 1 1 0 0], L_0x1e6ec10, L_0x1e6f840; -L_0x1e6fc90 .part L_0x1e6dd30, 4, 4; -L_0x1e6fdf0 .part L_0x1e6fb50, 0, 1; -L_0x1e6ffa0 .part L_0x1e6fb50, 1, 1; -S_0x1cea480 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cea2c0; +L_0x1303560/d .functor OR 1, L_0x1303620, L_0x13037d0, C4<0>, C4<0>; +L_0x1303560 .delay 1 (30000,30000,30000) L_0x1303560/d; +v0x117ea70_0 .net *"_s10", 0 0, L_0x1303620; 1 drivers +v0x117eb50_0 .net *"_s12", 0 0, L_0x13037d0; 1 drivers +v0x117ec30_0 .net "in", 7 0, L_0x1301560; alias, 1 drivers +v0x117ed00_0 .net "ors", 1 0, L_0x1303380; 1 drivers +v0x117edc0_0 .net "out", 0 0, L_0x1303560; alias, 1 drivers +L_0x1302750 .part L_0x1301560, 0, 4; +L_0x1303380 .concat8 [ 1 1 0 0], L_0x1302440, L_0x1303070; +L_0x13034c0 .part L_0x1301560, 4, 4; +L_0x1303620 .part L_0x1303380, 0, 1; +L_0x13037d0 .part L_0x1303380, 1, 1; +S_0x117d0e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x117cf20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e6e3d0/d .functor OR 1, L_0x1e6e490, L_0x1e6e5f0, C4<0>, C4<0>; -L_0x1e6e3d0 .delay 1 (30000,30000,30000) L_0x1e6e3d0/d; -L_0x1e6e820/d .functor OR 1, L_0x1e6e930, L_0x1e6ea90, C4<0>, C4<0>; -L_0x1e6e820 .delay 1 (30000,30000,30000) L_0x1e6e820/d; -L_0x1e6ec10/d .functor OR 1, L_0x1e6ec80, L_0x1e6ee30, C4<0>, C4<0>; -L_0x1e6ec10 .delay 1 (30000,30000,30000) L_0x1e6ec10/d; -v0x1cea6d0_0 .net *"_s0", 0 0, L_0x1e6e3d0; 1 drivers -v0x1cea7d0_0 .net *"_s10", 0 0, L_0x1e6e930; 1 drivers -v0x1cea8b0_0 .net *"_s12", 0 0, L_0x1e6ea90; 1 drivers -v0x1cea970_0 .net *"_s14", 0 0, L_0x1e6ec80; 1 drivers -v0x1ceaa50_0 .net *"_s16", 0 0, L_0x1e6ee30; 1 drivers -v0x1ceab80_0 .net *"_s3", 0 0, L_0x1e6e490; 1 drivers -v0x1ceac60_0 .net *"_s5", 0 0, L_0x1e6e5f0; 1 drivers -v0x1cead40_0 .net *"_s6", 0 0, L_0x1e6e820; 1 drivers -v0x1ceae20_0 .net "in", 3 0, L_0x1e6ef20; 1 drivers -v0x1ceaf90_0 .net "ors", 1 0, L_0x1e6e730; 1 drivers -v0x1ceb070_0 .net "out", 0 0, L_0x1e6ec10; 1 drivers -L_0x1e6e490 .part L_0x1e6ef20, 0, 1; -L_0x1e6e5f0 .part L_0x1e6ef20, 1, 1; -L_0x1e6e730 .concat8 [ 1 1 0 0], L_0x1e6e3d0, L_0x1e6e820; -L_0x1e6e930 .part L_0x1e6ef20, 2, 1; -L_0x1e6ea90 .part L_0x1e6ef20, 3, 1; -L_0x1e6ec80 .part L_0x1e6e730, 0, 1; -L_0x1e6ee30 .part L_0x1e6e730, 1, 1; -S_0x1ceb190 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cea2c0; +L_0x1301c00/d .functor OR 1, L_0x1301cc0, L_0x1301e20, C4<0>, C4<0>; +L_0x1301c00 .delay 1 (30000,30000,30000) L_0x1301c00/d; +L_0x1302050/d .functor OR 1, L_0x1302160, L_0x13022c0, C4<0>, C4<0>; +L_0x1302050 .delay 1 (30000,30000,30000) L_0x1302050/d; +L_0x1302440/d .functor OR 1, L_0x13024b0, L_0x1302660, C4<0>, C4<0>; +L_0x1302440 .delay 1 (30000,30000,30000) L_0x1302440/d; +v0x117d330_0 .net *"_s0", 0 0, L_0x1301c00; 1 drivers +v0x117d430_0 .net *"_s10", 0 0, L_0x1302160; 1 drivers +v0x117d510_0 .net *"_s12", 0 0, L_0x13022c0; 1 drivers +v0x117d5d0_0 .net *"_s14", 0 0, L_0x13024b0; 1 drivers +v0x117d6b0_0 .net *"_s16", 0 0, L_0x1302660; 1 drivers +v0x117d7e0_0 .net *"_s3", 0 0, L_0x1301cc0; 1 drivers +v0x117d8c0_0 .net *"_s5", 0 0, L_0x1301e20; 1 drivers +v0x117d9a0_0 .net *"_s6", 0 0, L_0x1302050; 1 drivers +v0x117da80_0 .net "in", 3 0, L_0x1302750; 1 drivers +v0x117dbf0_0 .net "ors", 1 0, L_0x1301f60; 1 drivers +v0x117dcd0_0 .net "out", 0 0, L_0x1302440; 1 drivers +L_0x1301cc0 .part L_0x1302750, 0, 1; +L_0x1301e20 .part L_0x1302750, 1, 1; +L_0x1301f60 .concat8 [ 1 1 0 0], L_0x1301c00, L_0x1302050; +L_0x1302160 .part L_0x1302750, 2, 1; +L_0x13022c0 .part L_0x1302750, 3, 1; +L_0x13024b0 .part L_0x1301f60, 0, 1; +L_0x1302660 .part L_0x1301f60, 1, 1; +S_0x117ddf0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x117cf20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e6f050/d .functor OR 1, L_0x1e6f0c0, L_0x1e6f220, C4<0>, C4<0>; -L_0x1e6f050 .delay 1 (30000,30000,30000) L_0x1e6f050/d; -L_0x1e6f450/d .functor OR 1, L_0x1e6f560, L_0x1e6f6c0, C4<0>, C4<0>; -L_0x1e6f450 .delay 1 (30000,30000,30000) L_0x1e6f450/d; -L_0x1e6f840/d .functor OR 1, L_0x1e6f8b0, L_0x1e6fa60, C4<0>, C4<0>; -L_0x1e6f840 .delay 1 (30000,30000,30000) L_0x1e6f840/d; -v0x1ceb350_0 .net *"_s0", 0 0, L_0x1e6f050; 1 drivers -v0x1ceb450_0 .net *"_s10", 0 0, L_0x1e6f560; 1 drivers -v0x1ceb530_0 .net *"_s12", 0 0, L_0x1e6f6c0; 1 drivers -v0x1ceb5f0_0 .net *"_s14", 0 0, L_0x1e6f8b0; 1 drivers -v0x1ceb6d0_0 .net *"_s16", 0 0, L_0x1e6fa60; 1 drivers -v0x1ceb800_0 .net *"_s3", 0 0, L_0x1e6f0c0; 1 drivers -v0x1ceb8e0_0 .net *"_s5", 0 0, L_0x1e6f220; 1 drivers -v0x1ceb9c0_0 .net *"_s6", 0 0, L_0x1e6f450; 1 drivers -v0x1cebaa0_0 .net "in", 3 0, L_0x1e6fc90; 1 drivers -v0x1cebc10_0 .net "ors", 1 0, L_0x1e6f360; 1 drivers -v0x1cebcf0_0 .net "out", 0 0, L_0x1e6f840; 1 drivers -L_0x1e6f0c0 .part L_0x1e6fc90, 0, 1; -L_0x1e6f220 .part L_0x1e6fc90, 1, 1; -L_0x1e6f360 .concat8 [ 1 1 0 0], L_0x1e6f050, L_0x1e6f450; -L_0x1e6f560 .part L_0x1e6fc90, 2, 1; -L_0x1e6f6c0 .part L_0x1e6fc90, 3, 1; -L_0x1e6f8b0 .part L_0x1e6f360, 0, 1; -L_0x1e6fa60 .part L_0x1e6f360, 1, 1; -S_0x1cec600 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1ce5730; +L_0x1302880/d .functor OR 1, L_0x13028f0, L_0x1302a50, C4<0>, C4<0>; +L_0x1302880 .delay 1 (30000,30000,30000) L_0x1302880/d; +L_0x1302c80/d .functor OR 1, L_0x1302d90, L_0x1302ef0, C4<0>, C4<0>; +L_0x1302c80 .delay 1 (30000,30000,30000) L_0x1302c80/d; +L_0x1303070/d .functor OR 1, L_0x13030e0, L_0x1303290, C4<0>, C4<0>; +L_0x1303070 .delay 1 (30000,30000,30000) L_0x1303070/d; +v0x117dfb0_0 .net *"_s0", 0 0, L_0x1302880; 1 drivers +v0x117e0b0_0 .net *"_s10", 0 0, L_0x1302d90; 1 drivers +v0x117e190_0 .net *"_s12", 0 0, L_0x1302ef0; 1 drivers +v0x117e250_0 .net *"_s14", 0 0, L_0x13030e0; 1 drivers +v0x117e330_0 .net *"_s16", 0 0, L_0x1303290; 1 drivers +v0x117e460_0 .net *"_s3", 0 0, L_0x13028f0; 1 drivers +v0x117e540_0 .net *"_s5", 0 0, L_0x1302a50; 1 drivers +v0x117e620_0 .net *"_s6", 0 0, L_0x1302c80; 1 drivers +v0x117e700_0 .net "in", 3 0, L_0x13034c0; 1 drivers +v0x117e870_0 .net "ors", 1 0, L_0x1302b90; 1 drivers +v0x117e950_0 .net "out", 0 0, L_0x1303070; 1 drivers +L_0x13028f0 .part L_0x13034c0, 0, 1; +L_0x1302a50 .part L_0x13034c0, 1, 1; +L_0x1302b90 .concat8 [ 1 1 0 0], L_0x1302880, L_0x1302c80; +L_0x1302d90 .part L_0x13034c0, 2, 1; +L_0x1302ef0 .part L_0x13034c0, 3, 1; +L_0x13030e0 .part L_0x1302b90, 0, 1; +L_0x1303290 .part L_0x1302b90, 1, 1; +S_0x117f260 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1178390; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cf1a30_0 .net "ands", 7 0, L_0x1e6a230; 1 drivers -v0x1cf1b40_0 .net "in", 7 0, L_0x1e68690; alias, 1 drivers -v0x1cf1c00_0 .net "out", 0 0, L_0x1e6c230; alias, 1 drivers -v0x1cf1cd0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cec850 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cec600; +v0x1184690_0 .net "ands", 7 0, L_0x12fda90; 1 drivers +v0x11847a0_0 .net "in", 7 0, L_0x12fbef0; alias, 1 drivers +v0x1184860_0 .net "out", 0 0, L_0x12ffa90; alias, 1 drivers +v0x1184930_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x117f4b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x117f260; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1ceef90_0 .net "A", 7 0, L_0x1e68690; alias, 1 drivers -v0x1cef090_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cef150_0 .net *"_s0", 0 0, L_0x1e68a20; 1 drivers -v0x1cef210_0 .net *"_s12", 0 0, L_0x1e693e0; 1 drivers -v0x1cef2f0_0 .net *"_s16", 0 0, L_0x1e69740; 1 drivers -v0x1cef420_0 .net *"_s20", 0 0, L_0x1e69b70; 1 drivers -v0x1cef500_0 .net *"_s24", 0 0, L_0x1e69ea0; 1 drivers -v0x1cef5e0_0 .net *"_s28", 0 0, L_0x1e69e30; 1 drivers -v0x1cef6c0_0 .net *"_s4", 0 0, L_0x1e68dc0; 1 drivers -v0x1cef830_0 .net *"_s8", 0 0, L_0x1e690d0; 1 drivers -v0x1cef910_0 .net "out", 7 0, L_0x1e6a230; alias, 1 drivers -L_0x1e68b30 .part L_0x1e68690, 0, 1; -L_0x1e68d20 .part v0x1d6daa0_0, 0, 1; -L_0x1e68e80 .part L_0x1e68690, 1, 1; -L_0x1e68fe0 .part v0x1d6daa0_0, 1, 1; -L_0x1e69190 .part L_0x1e68690, 2, 1; -L_0x1e692f0 .part v0x1d6daa0_0, 2, 1; -L_0x1e694a0 .part L_0x1e68690, 3, 1; -L_0x1e69600 .part v0x1d6daa0_0, 3, 1; -L_0x1e69800 .part L_0x1e68690, 4, 1; -L_0x1e69a70 .part v0x1d6daa0_0, 4, 1; -L_0x1e69be0 .part L_0x1e68690, 5, 1; -L_0x1e69d40 .part v0x1d6daa0_0, 5, 1; -L_0x1e69f60 .part L_0x1e68690, 6, 1; -L_0x1e6a0c0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e6a230_0_0 .concat8 [ 1 1 1 1], L_0x1e68a20, L_0x1e68dc0, L_0x1e690d0, L_0x1e693e0; -LS_0x1e6a230_0_4 .concat8 [ 1 1 1 1], L_0x1e69740, L_0x1e69b70, L_0x1e69ea0, L_0x1e69e30; -L_0x1e6a230 .concat8 [ 4 4 0 0], LS_0x1e6a230_0_0, LS_0x1e6a230_0_4; -L_0x1e6a5f0 .part L_0x1e68690, 7, 1; -L_0x1e6a7e0 .part v0x1d6daa0_0, 7, 1; -S_0x1ceca90 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1cecca0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e68a20/d .functor AND 1, L_0x1e68b30, L_0x1e68d20, C4<1>, C4<1>; -L_0x1e68a20 .delay 1 (30000,30000,30000) L_0x1e68a20/d; -v0x1cecd80_0 .net *"_s0", 0 0, L_0x1e68b30; 1 drivers -v0x1cece60_0 .net *"_s1", 0 0, L_0x1e68d20; 1 drivers -S_0x1cecf40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1ced150 .param/l "i" 0 4 54, +C4<01>; -L_0x1e68dc0/d .functor AND 1, L_0x1e68e80, L_0x1e68fe0, C4<1>, C4<1>; -L_0x1e68dc0 .delay 1 (30000,30000,30000) L_0x1e68dc0/d; -v0x1ced210_0 .net *"_s0", 0 0, L_0x1e68e80; 1 drivers -v0x1ced2f0_0 .net *"_s1", 0 0, L_0x1e68fe0; 1 drivers -S_0x1ced3d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1ced610 .param/l "i" 0 4 54, +C4<010>; -L_0x1e690d0/d .functor AND 1, L_0x1e69190, L_0x1e692f0, C4<1>, C4<1>; -L_0x1e690d0 .delay 1 (30000,30000,30000) L_0x1e690d0/d; -v0x1ced6b0_0 .net *"_s0", 0 0, L_0x1e69190; 1 drivers -v0x1ced790_0 .net *"_s1", 0 0, L_0x1e692f0; 1 drivers -S_0x1ced870 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1ceda80 .param/l "i" 0 4 54, +C4<011>; -L_0x1e693e0/d .functor AND 1, L_0x1e694a0, L_0x1e69600, C4<1>, C4<1>; -L_0x1e693e0 .delay 1 (30000,30000,30000) L_0x1e693e0/d; -v0x1cedb40_0 .net *"_s0", 0 0, L_0x1e694a0; 1 drivers -v0x1cedc20_0 .net *"_s1", 0 0, L_0x1e69600; 1 drivers -S_0x1cedd00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1cedf60 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e69740/d .functor AND 1, L_0x1e69800, L_0x1e69a70, C4<1>, C4<1>; -L_0x1e69740 .delay 1 (30000,30000,30000) L_0x1e69740/d; -v0x1cee020_0 .net *"_s0", 0 0, L_0x1e69800; 1 drivers -v0x1cee100_0 .net *"_s1", 0 0, L_0x1e69a70; 1 drivers -S_0x1cee1e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1cee3f0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e69b70/d .functor AND 1, L_0x1e69be0, L_0x1e69d40, C4<1>, C4<1>; -L_0x1e69b70 .delay 1 (30000,30000,30000) L_0x1e69b70/d; -v0x1cee4b0_0 .net *"_s0", 0 0, L_0x1e69be0; 1 drivers -v0x1cee590_0 .net *"_s1", 0 0, L_0x1e69d40; 1 drivers -S_0x1cee670 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1cee880 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e69ea0/d .functor AND 1, L_0x1e69f60, L_0x1e6a0c0, C4<1>, C4<1>; -L_0x1e69ea0 .delay 1 (30000,30000,30000) L_0x1e69ea0/d; -v0x1cee940_0 .net *"_s0", 0 0, L_0x1e69f60; 1 drivers -v0x1ceea20_0 .net *"_s1", 0 0, L_0x1e6a0c0; 1 drivers -S_0x1ceeb00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cec850; - .timescale -9 -12; -P_0x1ceed10 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e69e30/d .functor AND 1, L_0x1e6a5f0, L_0x1e6a7e0, C4<1>, C4<1>; -L_0x1e69e30 .delay 1 (30000,30000,30000) L_0x1e69e30/d; -v0x1ceedd0_0 .net *"_s0", 0 0, L_0x1e6a5f0; 1 drivers -v0x1ceeeb0_0 .net *"_s1", 0 0, L_0x1e6a7e0; 1 drivers -S_0x1cefa70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cec600; +v0x1181bf0_0 .net "A", 7 0, L_0x12fbef0; alias, 1 drivers +v0x1181cf0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1181db0_0 .net *"_s0", 0 0, L_0x12fc280; 1 drivers +v0x1181e70_0 .net *"_s12", 0 0, L_0x12fcc40; 1 drivers +v0x1181f50_0 .net *"_s16", 0 0, L_0x12fcfa0; 1 drivers +v0x1182080_0 .net *"_s20", 0 0, L_0x12fd3d0; 1 drivers +v0x1182160_0 .net *"_s24", 0 0, L_0x12fd700; 1 drivers +v0x1182240_0 .net *"_s28", 0 0, L_0x12fd690; 1 drivers +v0x1182320_0 .net *"_s4", 0 0, L_0x12fc620; 1 drivers +v0x1182490_0 .net *"_s8", 0 0, L_0x12fc930; 1 drivers +v0x1182570_0 .net "out", 7 0, L_0x12fda90; alias, 1 drivers +L_0x12fc390 .part L_0x12fbef0, 0, 1; +L_0x12fc580 .part v0x12010b0_0, 0, 1; +L_0x12fc6e0 .part L_0x12fbef0, 1, 1; +L_0x12fc840 .part v0x12010b0_0, 1, 1; +L_0x12fc9f0 .part L_0x12fbef0, 2, 1; +L_0x12fcb50 .part v0x12010b0_0, 2, 1; +L_0x12fcd00 .part L_0x12fbef0, 3, 1; +L_0x12fce60 .part v0x12010b0_0, 3, 1; +L_0x12fd060 .part L_0x12fbef0, 4, 1; +L_0x12fd2d0 .part v0x12010b0_0, 4, 1; +L_0x12fd440 .part L_0x12fbef0, 5, 1; +L_0x12fd5a0 .part v0x12010b0_0, 5, 1; +L_0x12fd7c0 .part L_0x12fbef0, 6, 1; +L_0x12fd920 .part v0x12010b0_0, 6, 1; +LS_0x12fda90_0_0 .concat8 [ 1 1 1 1], L_0x12fc280, L_0x12fc620, L_0x12fc930, L_0x12fcc40; +LS_0x12fda90_0_4 .concat8 [ 1 1 1 1], L_0x12fcfa0, L_0x12fd3d0, L_0x12fd700, L_0x12fd690; +L_0x12fda90 .concat8 [ 4 4 0 0], LS_0x12fda90_0_0, LS_0x12fda90_0_4; +L_0x12fde50 .part L_0x12fbef0, 7, 1; +L_0x12fe040 .part v0x12010b0_0, 7, 1; +S_0x117f6f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x117f900 .param/l "i" 0 4 54, +C4<00>; +L_0x12fc280/d .functor AND 1, L_0x12fc390, L_0x12fc580, C4<1>, C4<1>; +L_0x12fc280 .delay 1 (30000,30000,30000) L_0x12fc280/d; +v0x117f9e0_0 .net *"_s0", 0 0, L_0x12fc390; 1 drivers +v0x117fac0_0 .net *"_s1", 0 0, L_0x12fc580; 1 drivers +S_0x117fba0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x117fdb0 .param/l "i" 0 4 54, +C4<01>; +L_0x12fc620/d .functor AND 1, L_0x12fc6e0, L_0x12fc840, C4<1>, C4<1>; +L_0x12fc620 .delay 1 (30000,30000,30000) L_0x12fc620/d; +v0x117fe70_0 .net *"_s0", 0 0, L_0x12fc6e0; 1 drivers +v0x117ff50_0 .net *"_s1", 0 0, L_0x12fc840; 1 drivers +S_0x1180030 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x1180270 .param/l "i" 0 4 54, +C4<010>; +L_0x12fc930/d .functor AND 1, L_0x12fc9f0, L_0x12fcb50, C4<1>, C4<1>; +L_0x12fc930 .delay 1 (30000,30000,30000) L_0x12fc930/d; +v0x1180310_0 .net *"_s0", 0 0, L_0x12fc9f0; 1 drivers +v0x11803f0_0 .net *"_s1", 0 0, L_0x12fcb50; 1 drivers +S_0x11804d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x11806e0 .param/l "i" 0 4 54, +C4<011>; +L_0x12fcc40/d .functor AND 1, L_0x12fcd00, L_0x12fce60, C4<1>, C4<1>; +L_0x12fcc40 .delay 1 (30000,30000,30000) L_0x12fcc40/d; +v0x11807a0_0 .net *"_s0", 0 0, L_0x12fcd00; 1 drivers +v0x1180880_0 .net *"_s1", 0 0, L_0x12fce60; 1 drivers +S_0x1180960 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x1180bc0 .param/l "i" 0 4 54, +C4<0100>; +L_0x12fcfa0/d .functor AND 1, L_0x12fd060, L_0x12fd2d0, C4<1>, C4<1>; +L_0x12fcfa0 .delay 1 (30000,30000,30000) L_0x12fcfa0/d; +v0x1180c80_0 .net *"_s0", 0 0, L_0x12fd060; 1 drivers +v0x1180d60_0 .net *"_s1", 0 0, L_0x12fd2d0; 1 drivers +S_0x1180e40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x1181050 .param/l "i" 0 4 54, +C4<0101>; +L_0x12fd3d0/d .functor AND 1, L_0x12fd440, L_0x12fd5a0, C4<1>, C4<1>; +L_0x12fd3d0 .delay 1 (30000,30000,30000) L_0x12fd3d0/d; +v0x1181110_0 .net *"_s0", 0 0, L_0x12fd440; 1 drivers +v0x11811f0_0 .net *"_s1", 0 0, L_0x12fd5a0; 1 drivers +S_0x11812d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x11814e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x12fd700/d .functor AND 1, L_0x12fd7c0, L_0x12fd920, C4<1>, C4<1>; +L_0x12fd700 .delay 1 (30000,30000,30000) L_0x12fd700/d; +v0x11815a0_0 .net *"_s0", 0 0, L_0x12fd7c0; 1 drivers +v0x1181680_0 .net *"_s1", 0 0, L_0x12fd920; 1 drivers +S_0x1181760 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x117f4b0; + .timescale -9 -12; +P_0x1181970 .param/l "i" 0 4 54, +C4<0111>; +L_0x12fd690/d .functor AND 1, L_0x12fde50, L_0x12fe040, C4<1>, C4<1>; +L_0x12fd690 .delay 1 (30000,30000,30000) L_0x12fd690/d; +v0x1181a30_0 .net *"_s0", 0 0, L_0x12fde50; 1 drivers +v0x1181b10_0 .net *"_s1", 0 0, L_0x12fe040; 1 drivers +S_0x11826d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x117f260; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e6c230/d .functor OR 1, L_0x1e6c2f0, L_0x1e6c4a0, C4<0>, C4<0>; -L_0x1e6c230 .delay 1 (30000,30000,30000) L_0x1e6c230/d; -v0x1cf15c0_0 .net *"_s10", 0 0, L_0x1e6c2f0; 1 drivers -v0x1cf16a0_0 .net *"_s12", 0 0, L_0x1e6c4a0; 1 drivers -v0x1cf1780_0 .net "in", 7 0, L_0x1e6a230; alias, 1 drivers -v0x1cf1850_0 .net "ors", 1 0, L_0x1e6c050; 1 drivers -v0x1cf1910_0 .net "out", 0 0, L_0x1e6c230; alias, 1 drivers -L_0x1e6b420 .part L_0x1e6a230, 0, 4; -L_0x1e6c050 .concat8 [ 1 1 0 0], L_0x1e6b110, L_0x1e6bd40; -L_0x1e6c190 .part L_0x1e6a230, 4, 4; -L_0x1e6c2f0 .part L_0x1e6c050, 0, 1; -L_0x1e6c4a0 .part L_0x1e6c050, 1, 1; -S_0x1cefc30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cefa70; +L_0x12ffa90/d .functor OR 1, L_0x12ffb50, L_0x12ffd00, C4<0>, C4<0>; +L_0x12ffa90 .delay 1 (30000,30000,30000) L_0x12ffa90/d; +v0x1184220_0 .net *"_s10", 0 0, L_0x12ffb50; 1 drivers +v0x1184300_0 .net *"_s12", 0 0, L_0x12ffd00; 1 drivers +v0x11843e0_0 .net "in", 7 0, L_0x12fda90; alias, 1 drivers +v0x11844b0_0 .net "ors", 1 0, L_0x12ff8b0; 1 drivers +v0x1184570_0 .net "out", 0 0, L_0x12ffa90; alias, 1 drivers +L_0x12fec80 .part L_0x12fda90, 0, 4; +L_0x12ff8b0 .concat8 [ 1 1 0 0], L_0x12fe970, L_0x12ff5a0; +L_0x12ff9f0 .part L_0x12fda90, 4, 4; +L_0x12ffb50 .part L_0x12ff8b0, 0, 1; +L_0x12ffd00 .part L_0x12ff8b0, 1, 1; +S_0x1182890 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11826d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e6a8d0/d .functor OR 1, L_0x1e6a990, L_0x1e6aaf0, C4<0>, C4<0>; -L_0x1e6a8d0 .delay 1 (30000,30000,30000) L_0x1e6a8d0/d; -L_0x1e6ad20/d .functor OR 1, L_0x1e6ae30, L_0x1e6af90, C4<0>, C4<0>; -L_0x1e6ad20 .delay 1 (30000,30000,30000) L_0x1e6ad20/d; -L_0x1e6b110/d .functor OR 1, L_0x1e6b180, L_0x1e6b330, C4<0>, C4<0>; -L_0x1e6b110 .delay 1 (30000,30000,30000) L_0x1e6b110/d; -v0x1cefe80_0 .net *"_s0", 0 0, L_0x1e6a8d0; 1 drivers -v0x1ceff80_0 .net *"_s10", 0 0, L_0x1e6ae30; 1 drivers -v0x1cf0060_0 .net *"_s12", 0 0, L_0x1e6af90; 1 drivers -v0x1cf0120_0 .net *"_s14", 0 0, L_0x1e6b180; 1 drivers -v0x1cf0200_0 .net *"_s16", 0 0, L_0x1e6b330; 1 drivers -v0x1cf0330_0 .net *"_s3", 0 0, L_0x1e6a990; 1 drivers -v0x1cf0410_0 .net *"_s5", 0 0, L_0x1e6aaf0; 1 drivers -v0x1cf04f0_0 .net *"_s6", 0 0, L_0x1e6ad20; 1 drivers -v0x1cf05d0_0 .net "in", 3 0, L_0x1e6b420; 1 drivers -v0x1cf0740_0 .net "ors", 1 0, L_0x1e6ac30; 1 drivers -v0x1cf0820_0 .net "out", 0 0, L_0x1e6b110; 1 drivers -L_0x1e6a990 .part L_0x1e6b420, 0, 1; -L_0x1e6aaf0 .part L_0x1e6b420, 1, 1; -L_0x1e6ac30 .concat8 [ 1 1 0 0], L_0x1e6a8d0, L_0x1e6ad20; -L_0x1e6ae30 .part L_0x1e6b420, 2, 1; -L_0x1e6af90 .part L_0x1e6b420, 3, 1; -L_0x1e6b180 .part L_0x1e6ac30, 0, 1; -L_0x1e6b330 .part L_0x1e6ac30, 1, 1; -S_0x1cf0940 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cefa70; +L_0x12fe130/d .functor OR 1, L_0x12fe1f0, L_0x12fe350, C4<0>, C4<0>; +L_0x12fe130 .delay 1 (30000,30000,30000) L_0x12fe130/d; +L_0x12fe580/d .functor OR 1, L_0x12fe690, L_0x12fe7f0, C4<0>, C4<0>; +L_0x12fe580 .delay 1 (30000,30000,30000) L_0x12fe580/d; +L_0x12fe970/d .functor OR 1, L_0x12fe9e0, L_0x12feb90, C4<0>, C4<0>; +L_0x12fe970 .delay 1 (30000,30000,30000) L_0x12fe970/d; +v0x1182ae0_0 .net *"_s0", 0 0, L_0x12fe130; 1 drivers +v0x1182be0_0 .net *"_s10", 0 0, L_0x12fe690; 1 drivers +v0x1182cc0_0 .net *"_s12", 0 0, L_0x12fe7f0; 1 drivers +v0x1182d80_0 .net *"_s14", 0 0, L_0x12fe9e0; 1 drivers +v0x1182e60_0 .net *"_s16", 0 0, L_0x12feb90; 1 drivers +v0x1182f90_0 .net *"_s3", 0 0, L_0x12fe1f0; 1 drivers +v0x1183070_0 .net *"_s5", 0 0, L_0x12fe350; 1 drivers +v0x1183150_0 .net *"_s6", 0 0, L_0x12fe580; 1 drivers +v0x1183230_0 .net "in", 3 0, L_0x12fec80; 1 drivers +v0x11833a0_0 .net "ors", 1 0, L_0x12fe490; 1 drivers +v0x1183480_0 .net "out", 0 0, L_0x12fe970; 1 drivers +L_0x12fe1f0 .part L_0x12fec80, 0, 1; +L_0x12fe350 .part L_0x12fec80, 1, 1; +L_0x12fe490 .concat8 [ 1 1 0 0], L_0x12fe130, L_0x12fe580; +L_0x12fe690 .part L_0x12fec80, 2, 1; +L_0x12fe7f0 .part L_0x12fec80, 3, 1; +L_0x12fe9e0 .part L_0x12fe490, 0, 1; +L_0x12feb90 .part L_0x12fe490, 1, 1; +S_0x11835a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11826d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e6b550/d .functor OR 1, L_0x1e6b5c0, L_0x1e6b720, C4<0>, C4<0>; -L_0x1e6b550 .delay 1 (30000,30000,30000) L_0x1e6b550/d; -L_0x1e6b950/d .functor OR 1, L_0x1e6ba60, L_0x1e6bbc0, C4<0>, C4<0>; -L_0x1e6b950 .delay 1 (30000,30000,30000) L_0x1e6b950/d; -L_0x1e6bd40/d .functor OR 1, L_0x1e6bdb0, L_0x1e6bf60, C4<0>, C4<0>; -L_0x1e6bd40 .delay 1 (30000,30000,30000) L_0x1e6bd40/d; -v0x1cf0b00_0 .net *"_s0", 0 0, L_0x1e6b550; 1 drivers -v0x1cf0c00_0 .net *"_s10", 0 0, L_0x1e6ba60; 1 drivers -v0x1cf0ce0_0 .net *"_s12", 0 0, L_0x1e6bbc0; 1 drivers -v0x1cf0da0_0 .net *"_s14", 0 0, L_0x1e6bdb0; 1 drivers -v0x1cf0e80_0 .net *"_s16", 0 0, L_0x1e6bf60; 1 drivers -v0x1cf0fb0_0 .net *"_s3", 0 0, L_0x1e6b5c0; 1 drivers -v0x1cf1090_0 .net *"_s5", 0 0, L_0x1e6b720; 1 drivers -v0x1cf1170_0 .net *"_s6", 0 0, L_0x1e6b950; 1 drivers -v0x1cf1250_0 .net "in", 3 0, L_0x1e6c190; 1 drivers -v0x1cf13c0_0 .net "ors", 1 0, L_0x1e6b860; 1 drivers -v0x1cf14a0_0 .net "out", 0 0, L_0x1e6bd40; 1 drivers -L_0x1e6b5c0 .part L_0x1e6c190, 0, 1; -L_0x1e6b720 .part L_0x1e6c190, 1, 1; -L_0x1e6b860 .concat8 [ 1 1 0 0], L_0x1e6b550, L_0x1e6b950; -L_0x1e6ba60 .part L_0x1e6c190, 2, 1; -L_0x1e6bbc0 .part L_0x1e6c190, 3, 1; -L_0x1e6bdb0 .part L_0x1e6b860, 0, 1; -L_0x1e6bf60 .part L_0x1e6b860, 1, 1; -S_0x1c03b90 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ce5730; +L_0x12fedb0/d .functor OR 1, L_0x12fee20, L_0x12fef80, C4<0>, C4<0>; +L_0x12fedb0 .delay 1 (30000,30000,30000) L_0x12fedb0/d; +L_0x12ff1b0/d .functor OR 1, L_0x12ff2c0, L_0x12ff420, C4<0>, C4<0>; +L_0x12ff1b0 .delay 1 (30000,30000,30000) L_0x12ff1b0/d; +L_0x12ff5a0/d .functor OR 1, L_0x12ff610, L_0x12ff7c0, C4<0>, C4<0>; +L_0x12ff5a0 .delay 1 (30000,30000,30000) L_0x12ff5a0/d; +v0x1183760_0 .net *"_s0", 0 0, L_0x12fedb0; 1 drivers +v0x1183860_0 .net *"_s10", 0 0, L_0x12ff2c0; 1 drivers +v0x1183940_0 .net *"_s12", 0 0, L_0x12ff420; 1 drivers +v0x1183a00_0 .net *"_s14", 0 0, L_0x12ff610; 1 drivers +v0x1183ae0_0 .net *"_s16", 0 0, L_0x12ff7c0; 1 drivers +v0x1183c10_0 .net *"_s3", 0 0, L_0x12fee20; 1 drivers +v0x1183cf0_0 .net *"_s5", 0 0, L_0x12fef80; 1 drivers +v0x1183dd0_0 .net *"_s6", 0 0, L_0x12ff1b0; 1 drivers +v0x1183eb0_0 .net "in", 3 0, L_0x12ff9f0; 1 drivers +v0x1184020_0 .net "ors", 1 0, L_0x12ff0c0; 1 drivers +v0x1184100_0 .net "out", 0 0, L_0x12ff5a0; 1 drivers +L_0x12fee20 .part L_0x12ff9f0, 0, 1; +L_0x12fef80 .part L_0x12ff9f0, 1, 1; +L_0x12ff0c0 .concat8 [ 1 1 0 0], L_0x12fedb0, L_0x12ff1b0; +L_0x12ff2c0 .part L_0x12ff9f0, 2, 1; +L_0x12ff420 .part L_0x12ff9f0, 3, 1; +L_0x12ff610 .part L_0x12ff0c0, 0, 1; +L_0x12ff7c0 .part L_0x12ff0c0, 1, 1; +S_0x1096810 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1178390; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -13900,80 +13910,80 @@ S_0x1c03b90 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1ce5730; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e67a00/d .functor XNOR 1, L_0x1e70190, L_0x1e66700, C4<0>, C4<0>; -L_0x1e67a00 .delay 1 (20000,20000,20000) L_0x1e67a00/d; -L_0x1e67c70/d .functor AND 1, L_0x1e70190, L_0x1e66a00, C4<1>, C4<1>; -L_0x1e67c70 .delay 1 (30000,30000,30000) L_0x1e67c70/d; -L_0x1e67ce0/d .functor AND 1, L_0x1e67a00, L_0x1e667a0, C4<1>, C4<1>; -L_0x1e67ce0 .delay 1 (30000,30000,30000) L_0x1e67ce0/d; -L_0x1e67e40/d .functor OR 1, L_0x1e67ce0, L_0x1e67c70, C4<0>, C4<0>; -L_0x1e67e40 .delay 1 (30000,30000,30000) L_0x1e67e40/d; -v0x1c03e40_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers -v0x1c03f30_0 .net "a_", 0 0, L_0x1e5caf0; alias, 1 drivers -v0x1c03ff0_0 .net "b", 0 0, L_0x1e66700; alias, 1 drivers -v0x1c040e0_0 .net "b_", 0 0, L_0x1e66a00; alias, 1 drivers -v0x1c04180_0 .net "carryin", 0 0, L_0x1e667a0; alias, 1 drivers -v0x1c042c0_0 .net "eq", 0 0, L_0x1e67a00; 1 drivers -v0x1cf2da0_0 .net "lt", 0 0, L_0x1e67c70; 1 drivers -v0x1cf2e60_0 .net "out", 0 0, L_0x1e67e40; 1 drivers -v0x1cf2f20_0 .net "w0", 0 0, L_0x1e67ce0; 1 drivers -S_0x1cf3170 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1ce5730; +L_0x12fb260/d .functor XNOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; +L_0x12fb260 .delay 1 (20000,20000,20000) L_0x12fb260/d; +L_0x12fb4d0/d .functor AND 1, L_0x13039c0, L_0x12fa260, C4<1>, C4<1>; +L_0x12fb4d0 .delay 1 (30000,30000,30000) L_0x12fb4d0/d; +L_0x12fb540/d .functor AND 1, L_0x12fb260, L_0x12fa000, C4<1>, C4<1>; +L_0x12fb540 .delay 1 (30000,30000,30000) L_0x12fb540/d; +L_0x12fb6a0/d .functor OR 1, L_0x12fb540, L_0x12fb4d0, C4<0>, C4<0>; +L_0x12fb6a0 .delay 1 (30000,30000,30000) L_0x12fb6a0/d; +v0x1096ac0_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers +v0x1096bb0_0 .net "a_", 0 0, L_0x12f0420; alias, 1 drivers +v0x1096c70_0 .net "b", 0 0, L_0x12f9f60; alias, 1 drivers +v0x1096d60_0 .net "b_", 0 0, L_0x12fa260; alias, 1 drivers +v0x1096e00_0 .net "carryin", 0 0, L_0x12fa000; alias, 1 drivers +v0x1096f40_0 .net "eq", 0 0, L_0x12fb260; 1 drivers +v0x1185a00_0 .net "lt", 0 0, L_0x12fb4d0; 1 drivers +v0x1185ac0_0 .net "out", 0 0, L_0x12fb6a0; 1 drivers +v0x1185b80_0 .net "w0", 0 0, L_0x12fb540; 1 drivers +S_0x1185dd0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1178390; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e677e0/d .functor OR 1, L_0x1e67330, L_0x1cf4390, C4<0>, C4<0>; -L_0x1e677e0 .delay 1 (30000,30000,30000) L_0x1e677e0/d; -v0x1cf3f60_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers -v0x1cf4090_0 .net "b", 0 0, L_0x1e66a00; alias, 1 drivers -v0x1cf4130_0 .net "c1", 0 0, L_0x1e67330; 1 drivers -v0x1cf41d0_0 .net "c2", 0 0, L_0x1cf4390; 1 drivers -v0x1cf42a0_0 .net "carryin", 0 0, L_0x1e667a0; alias, 1 drivers -v0x1cf4420_0 .net "carryout", 0 0, L_0x1e677e0; 1 drivers -v0x1cf44c0_0 .net "s1", 0 0, L_0x1e67270; 1 drivers -v0x1cf4560_0 .net "sum", 0 0, L_0x1e67490; 1 drivers -S_0x1cf33c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cf3170; +L_0x12fb040/d .functor OR 1, L_0x12fab90, L_0x1187030, C4<0>, C4<0>; +L_0x12fb040 .delay 1 (30000,30000,30000) L_0x12fb040/d; +v0x1186bc0_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers +v0x1186d10_0 .net "b", 0 0, L_0x12fa260; alias, 1 drivers +v0x1186dd0_0 .net "c1", 0 0, L_0x12fab90; 1 drivers +v0x1186e70_0 .net "c2", 0 0, L_0x1187030; 1 drivers +v0x1186f40_0 .net "carryin", 0 0, L_0x12fa000; alias, 1 drivers +v0x11870c0_0 .net "carryout", 0 0, L_0x12fb040; 1 drivers +v0x1187160_0 .net "s1", 0 0, L_0x12faad0; 1 drivers +v0x1187200_0 .net "sum", 0 0, L_0x12facf0; 1 drivers +S_0x1186020 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1185dd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e67270/d .functor XOR 1, L_0x1e70190, L_0x1e66a00, C4<0>, C4<0>; -L_0x1e67270 .delay 1 (30000,30000,30000) L_0x1e67270/d; -L_0x1e67330/d .functor AND 1, L_0x1e70190, L_0x1e66a00, C4<1>, C4<1>; -L_0x1e67330 .delay 1 (30000,30000,30000) L_0x1e67330/d; -v0x1cf3620_0 .net "a", 0 0, L_0x1e70190; alias, 1 drivers -v0x1cf36e0_0 .net "b", 0 0, L_0x1e66a00; alias, 1 drivers -v0x1cf37a0_0 .net "carryout", 0 0, L_0x1e67330; alias, 1 drivers -v0x1cf3840_0 .net "sum", 0 0, L_0x1e67270; alias, 1 drivers -S_0x1cf3970 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cf3170; +L_0x12faad0/d .functor XOR 1, L_0x13039c0, L_0x12fa260, C4<0>, C4<0>; +L_0x12faad0 .delay 1 (30000,30000,30000) L_0x12faad0/d; +L_0x12fab90/d .functor AND 1, L_0x13039c0, L_0x12fa260, C4<1>, C4<1>; +L_0x12fab90 .delay 1 (30000,30000,30000) L_0x12fab90/d; +v0x1186280_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers +v0x1186340_0 .net "b", 0 0, L_0x12fa260; alias, 1 drivers +v0x1186400_0 .net "carryout", 0 0, L_0x12fab90; alias, 1 drivers +v0x11864a0_0 .net "sum", 0 0, L_0x12faad0; alias, 1 drivers +S_0x11865d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1185dd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e67490/d .functor XOR 1, L_0x1e67270, L_0x1e667a0, C4<0>, C4<0>; -L_0x1e67490 .delay 1 (30000,30000,30000) L_0x1e67490/d; -L_0x1cf4390/d .functor AND 1, L_0x1e67270, L_0x1e667a0, C4<1>, C4<1>; -L_0x1cf4390 .delay 1 (30000,30000,30000) L_0x1cf4390/d; -v0x1cf3bd0_0 .net "a", 0 0, L_0x1e67270; alias, 1 drivers -v0x1cf3ca0_0 .net "b", 0 0, L_0x1e667a0; alias, 1 drivers -v0x1cf3d40_0 .net "carryout", 0 0, L_0x1cf4390; alias, 1 drivers -v0x1cf3e10_0 .net "sum", 0 0, L_0x1e67490; alias, 1 drivers -S_0x1cf59c0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1ce5460; - .timescale -9 -12; -L_0x7f72592dbc38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbc80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e70230/d .functor OR 1, L_0x7f72592dbc38, L_0x7f72592dbc80, C4<0>, C4<0>; -L_0x1e70230 .delay 1 (30000,30000,30000) L_0x1e70230/d; -v0x1cf5bb0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbc38; 1 drivers -v0x1cf5c90_0 .net/2u *"_s2", 0 0, L_0x7f72592dbc80; 1 drivers -S_0x1cf5d70 .scope generate, "alu_slices[26]" "alu_slices[26]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1cf5f80 .param/l "i" 0 3 37, +C4<011010>; -S_0x1cf6040 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cf5d70; +L_0x12facf0/d .functor XOR 1, L_0x12faad0, L_0x12fa000, C4<0>, C4<0>; +L_0x12facf0 .delay 1 (30000,30000,30000) L_0x12facf0/d; +L_0x1187030/d .functor AND 1, L_0x12faad0, L_0x12fa000, C4<1>, C4<1>; +L_0x1187030 .delay 1 (30000,30000,30000) L_0x1187030/d; +v0x1186830_0 .net "a", 0 0, L_0x12faad0; alias, 1 drivers +v0x1186900_0 .net "b", 0 0, L_0x12fa000; alias, 1 drivers +v0x11869a0_0 .net "carryout", 0 0, L_0x1187030; alias, 1 drivers +v0x1186a70_0 .net "sum", 0 0, L_0x12facf0; alias, 1 drivers +S_0x1188620 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11780c0; + .timescale -9 -12; +L_0x2b0ab3d06c38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06c80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1303a60/d .functor OR 1, L_0x2b0ab3d06c38, L_0x2b0ab3d06c80, C4<0>, C4<0>; +L_0x1303a60 .delay 1 (30000,30000,30000) L_0x1303a60/d; +v0x1188810_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06c38; 1 drivers +v0x11888f0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06c80; 1 drivers +S_0x11889d0 .scope generate, "alu_slices[26]" "alu_slices[26]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1188be0 .param/l "i" 0 3 41, +C4<011010>; +S_0x1188ca0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11889d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -13982,445 +13992,445 @@ S_0x1cf6040 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1cf5d70; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e705c0/d .functor NOT 1, L_0x1e79dd0, C4<0>, C4<0>, C4<0>; -L_0x1e705c0 .delay 1 (10000,10000,10000) L_0x1e705c0/d; -L_0x1e706d0/d .functor NOT 1, L_0x1e79f30, C4<0>, C4<0>, C4<0>; -L_0x1e706d0 .delay 1 (10000,10000,10000) L_0x1e706d0/d; -L_0x1e71720/d .functor XOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; -L_0x1e71720 .delay 1 (30000,30000,30000) L_0x1e71720/d; -L_0x7f72592dbcc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbd10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e71dd0/d .functor OR 1, L_0x7f72592dbcc8, L_0x7f72592dbd10, C4<0>, C4<0>; -L_0x1e71dd0 .delay 1 (30000,30000,30000) L_0x1e71dd0/d; -L_0x1e71fd0/d .functor AND 1, L_0x1e79dd0, L_0x1e79f30, C4<1>, C4<1>; -L_0x1e71fd0 .delay 1 (30000,30000,30000) L_0x1e71fd0/d; -L_0x1e72090/d .functor NAND 1, L_0x1e79dd0, L_0x1e79f30, C4<1>, C4<1>; -L_0x1e72090 .delay 1 (20000,20000,20000) L_0x1e72090/d; -L_0x1e721f0/d .functor XOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; -L_0x1e721f0 .delay 1 (20000,20000,20000) L_0x1e721f0/d; -L_0x1e726a0/d .functor OR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; -L_0x1e726a0 .delay 1 (30000,30000,30000) L_0x1e726a0/d; -L_0x1e79cd0/d .functor NOT 1, L_0x1e75f30, C4<0>, C4<0>, C4<0>; -L_0x1e79cd0 .delay 1 (10000,10000,10000) L_0x1e79cd0/d; -v0x1d04770_0 .net "A", 0 0, L_0x1e79dd0; 1 drivers -v0x1d04830_0 .net "A_", 0 0, L_0x1e705c0; 1 drivers -v0x1d048f0_0 .net "B", 0 0, L_0x1e79f30; 1 drivers -v0x1d049c0_0 .net "B_", 0 0, L_0x1e706d0; 1 drivers -v0x1d04a60_0 .net *"_s12", 0 0, L_0x1e71dd0; 1 drivers -v0x1d04b50_0 .net/2s *"_s14", 0 0, L_0x7f72592dbcc8; 1 drivers -v0x1d04c10_0 .net/2s *"_s16", 0 0, L_0x7f72592dbd10; 1 drivers -v0x1d04cf0_0 .net *"_s18", 0 0, L_0x1e71fd0; 1 drivers -v0x1d04dd0_0 .net *"_s20", 0 0, L_0x1e72090; 1 drivers -v0x1d04f40_0 .net *"_s22", 0 0, L_0x1e721f0; 1 drivers -v0x1d05020_0 .net *"_s24", 0 0, L_0x1e726a0; 1 drivers -o0x7f7259331ce8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1d05100_0 name=_s30 -o0x7f7259331d18 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1d051e0_0 name=_s32 -v0x1d052c0_0 .net *"_s8", 0 0, L_0x1e71720; 1 drivers -v0x1d053a0_0 .net "carryin", 0 0, L_0x1e702f0; 1 drivers -v0x1d05440_0 .net "carryout", 0 0, L_0x1e79970; 1 drivers -v0x1d054e0_0 .net "carryouts", 7 0, L_0x1ec1810; 1 drivers -v0x1d05690_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d05730_0 .net "result", 0 0, L_0x1e75f30; 1 drivers -v0x1d05820_0 .net "results", 7 0, L_0x1e72470; 1 drivers -v0x1d05930_0 .net "zero", 0 0, L_0x1e79cd0; 1 drivers -LS_0x1e72470_0_0 .concat8 [ 1 1 1 1], L_0x1e70bf0, L_0x1e71220, L_0x1e71720, L_0x1e71dd0; -LS_0x1e72470_0_4 .concat8 [ 1 1 1 1], L_0x1e71fd0, L_0x1e72090, L_0x1e721f0, L_0x1e726a0; -L_0x1e72470 .concat8 [ 4 4 0 0], LS_0x1e72470_0_0, LS_0x1e72470_0_4; -LS_0x1ec1810_0_0 .concat [ 1 1 1 1], L_0x1e70ea0, L_0x1e715c0, o0x7f7259331ce8, L_0x1e71c20; -LS_0x1ec1810_0_4 .concat [ 4 0 0 0], o0x7f7259331d18; -L_0x1ec1810 .concat [ 4 4 0 0], LS_0x1ec1810_0_0, LS_0x1ec1810_0_4; -S_0x1cf62c0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1cf6040; +L_0x12fa140/d .functor NOT 1, L_0x130d610, C4<0>, C4<0>, C4<0>; +L_0x12fa140 .delay 1 (10000,10000,10000) L_0x12fa140/d; +L_0x1303df0/d .functor NOT 1, L_0x130d770, C4<0>, C4<0>, C4<0>; +L_0x1303df0 .delay 1 (10000,10000,10000) L_0x1303df0/d; +L_0x1304df0/d .functor XOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; +L_0x1304df0 .delay 1 (30000,30000,30000) L_0x1304df0/d; +L_0x2b0ab3d06cc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06d10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x13054a0/d .functor OR 1, L_0x2b0ab3d06cc8, L_0x2b0ab3d06d10, C4<0>, C4<0>; +L_0x13054a0 .delay 1 (30000,30000,30000) L_0x13054a0/d; +L_0x13056a0/d .functor AND 1, L_0x130d610, L_0x130d770, C4<1>, C4<1>; +L_0x13056a0 .delay 1 (30000,30000,30000) L_0x13056a0/d; +L_0x1305760/d .functor NAND 1, L_0x130d610, L_0x130d770, C4<1>, C4<1>; +L_0x1305760 .delay 1 (20000,20000,20000) L_0x1305760/d; +L_0x13058c0/d .functor XOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; +L_0x13058c0 .delay 1 (20000,20000,20000) L_0x13058c0/d; +L_0x1305d70/d .functor OR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; +L_0x1305d70 .delay 1 (30000,30000,30000) L_0x1305d70/d; +L_0x130d510/d .functor NOT 1, L_0x13096e0, C4<0>, C4<0>, C4<0>; +L_0x130d510 .delay 1 (10000,10000,10000) L_0x130d510/d; +v0x11973d0_0 .net "A", 0 0, L_0x130d610; 1 drivers +v0x1197490_0 .net "A_", 0 0, L_0x12fa140; 1 drivers +v0x1197550_0 .net "B", 0 0, L_0x130d770; 1 drivers +v0x1197620_0 .net "B_", 0 0, L_0x1303df0; 1 drivers +v0x11976c0_0 .net *"_s12", 0 0, L_0x13054a0; 1 drivers +v0x11977b0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06cc8; 1 drivers +v0x1197870_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06d10; 1 drivers +v0x1197950_0 .net *"_s18", 0 0, L_0x13056a0; 1 drivers +v0x1197a30_0 .net *"_s20", 0 0, L_0x1305760; 1 drivers +v0x1197ba0_0 .net *"_s22", 0 0, L_0x13058c0; 1 drivers +v0x1197c80_0 .net *"_s24", 0 0, L_0x1305d70; 1 drivers +o0x2b0ab3ce2ce8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x1197d60_0 name=_s30 +o0x2b0ab3ce2d18 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x1197e40_0 name=_s32 +v0x1197f20_0 .net *"_s8", 0 0, L_0x1304df0; 1 drivers +v0x1198000_0 .net "carryin", 0 0, L_0x1303b20; 1 drivers +v0x11980a0_0 .net "carryout", 0 0, L_0x130d1b0; 1 drivers +v0x1198140_0 .net "carryouts", 7 0, L_0x1355b40; 1 drivers +v0x11982f0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x1198390_0 .net "result", 0 0, L_0x13096e0; 1 drivers +v0x1198480_0 .net "results", 7 0, L_0x1305b40; 1 drivers +v0x1198590_0 .net "zero", 0 0, L_0x130d510; 1 drivers +LS_0x1305b40_0_0 .concat8 [ 1 1 1 1], L_0x1304310, L_0x1304940, L_0x1304df0, L_0x13054a0; +LS_0x1305b40_0_4 .concat8 [ 1 1 1 1], L_0x13056a0, L_0x1305760, L_0x13058c0, L_0x1305d70; +L_0x1305b40 .concat8 [ 4 4 0 0], LS_0x1305b40_0_0, LS_0x1305b40_0_4; +LS_0x1355b40_0_0 .concat [ 1 1 1 1], L_0x13045c0, L_0x1304c90, o0x2b0ab3ce2ce8, L_0x13052f0; +LS_0x1355b40_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce2d18; +L_0x1355b40 .concat [ 4 4 0 0], LS_0x1355b40_0_0, LS_0x1355b40_0_4; +S_0x1188f20 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1188ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e70ea0/d .functor OR 1, L_0x1e70980, L_0x1e70d40, C4<0>, C4<0>; -L_0x1e70ea0 .delay 1 (30000,30000,30000) L_0x1e70ea0/d; -v0x1cf70f0_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers -v0x1cf71b0_0 .net "b", 0 0, L_0x1e79f30; alias, 1 drivers -v0x1cf7280_0 .net "c1", 0 0, L_0x1e70980; 1 drivers -v0x1cf7380_0 .net "c2", 0 0, L_0x1e70d40; 1 drivers -v0x1cf7450_0 .net "carryin", 0 0, L_0x1e702f0; alias, 1 drivers -v0x1cf7540_0 .net "carryout", 0 0, L_0x1e70ea0; 1 drivers -v0x1cf75e0_0 .net "s1", 0 0, L_0x1e708c0; 1 drivers -v0x1cf76d0_0 .net "sum", 0 0, L_0x1e70bf0; 1 drivers -S_0x1cf6530 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1cf62c0; +L_0x13045c0/d .functor OR 1, L_0x13040a0, L_0x1304460, C4<0>, C4<0>; +L_0x13045c0 .delay 1 (30000,30000,30000) L_0x13045c0/d; +v0x1189d50_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers +v0x1189e10_0 .net "b", 0 0, L_0x130d770; alias, 1 drivers +v0x1189ee0_0 .net "c1", 0 0, L_0x13040a0; 1 drivers +v0x1189fe0_0 .net "c2", 0 0, L_0x1304460; 1 drivers +v0x118a0b0_0 .net "carryin", 0 0, L_0x1303b20; alias, 1 drivers +v0x118a1a0_0 .net "carryout", 0 0, L_0x13045c0; 1 drivers +v0x118a240_0 .net "s1", 0 0, L_0x1303fe0; 1 drivers +v0x118a330_0 .net "sum", 0 0, L_0x1304310; 1 drivers +S_0x1189190 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1188f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e708c0/d .functor XOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; -L_0x1e708c0 .delay 1 (30000,30000,30000) L_0x1e708c0/d; -L_0x1e70980/d .functor AND 1, L_0x1e79dd0, L_0x1e79f30, C4<1>, C4<1>; -L_0x1e70980 .delay 1 (30000,30000,30000) L_0x1e70980/d; -v0x1cf6790_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers -v0x1cf6870_0 .net "b", 0 0, L_0x1e79f30; alias, 1 drivers -v0x1cf6930_0 .net "carryout", 0 0, L_0x1e70980; alias, 1 drivers -v0x1cf69d0_0 .net "sum", 0 0, L_0x1e708c0; alias, 1 drivers -S_0x1cf6b10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1cf62c0; +L_0x1303fe0/d .functor XOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; +L_0x1303fe0 .delay 1 (30000,30000,30000) L_0x1303fe0/d; +L_0x13040a0/d .functor AND 1, L_0x130d610, L_0x130d770, C4<1>, C4<1>; +L_0x13040a0 .delay 1 (30000,30000,30000) L_0x13040a0/d; +v0x11893f0_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers +v0x11894d0_0 .net "b", 0 0, L_0x130d770; alias, 1 drivers +v0x1189590_0 .net "carryout", 0 0, L_0x13040a0; alias, 1 drivers +v0x1189630_0 .net "sum", 0 0, L_0x1303fe0; alias, 1 drivers +S_0x1189770 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1188f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e70bf0/d .functor XOR 1, L_0x1e708c0, L_0x1e702f0, C4<0>, C4<0>; -L_0x1e70bf0 .delay 1 (30000,30000,30000) L_0x1e70bf0/d; -L_0x1e70d40/d .functor AND 1, L_0x1e708c0, L_0x1e702f0, C4<1>, C4<1>; -L_0x1e70d40 .delay 1 (30000,30000,30000) L_0x1e70d40/d; -v0x1cf6d70_0 .net "a", 0 0, L_0x1e708c0; alias, 1 drivers -v0x1cf6e10_0 .net "b", 0 0, L_0x1e702f0; alias, 1 drivers -v0x1cf6eb0_0 .net "carryout", 0 0, L_0x1e70d40; alias, 1 drivers -v0x1cf6f80_0 .net "sum", 0 0, L_0x1e70bf0; alias, 1 drivers -S_0x1cf77a0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1cf6040; +L_0x1304310/d .functor XOR 1, L_0x1303fe0, L_0x1303b20, C4<0>, C4<0>; +L_0x1304310 .delay 1 (30000,30000,30000) L_0x1304310/d; +L_0x1304460/d .functor AND 1, L_0x1303fe0, L_0x1303b20, C4<1>, C4<1>; +L_0x1304460 .delay 1 (30000,30000,30000) L_0x1304460/d; +v0x11899d0_0 .net "a", 0 0, L_0x1303fe0; alias, 1 drivers +v0x1189a70_0 .net "b", 0 0, L_0x1303b20; alias, 1 drivers +v0x1189b10_0 .net "carryout", 0 0, L_0x1304460; alias, 1 drivers +v0x1189be0_0 .net "sum", 0 0, L_0x1304310; alias, 1 drivers +S_0x118a400 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1188ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1cfcb90_0 .net "ands", 7 0, L_0x1e77970; 1 drivers -v0x1cfcca0_0 .net "in", 7 0, L_0x1ec1810; alias, 1 drivers -v0x1cfcd60_0 .net "out", 0 0, L_0x1e79970; alias, 1 drivers -v0x1cfce30_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cf79c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cf77a0; +v0x118f7f0_0 .net "ands", 7 0, L_0x130b1b0; 1 drivers +v0x118f900_0 .net "in", 7 0, L_0x1355b40; alias, 1 drivers +v0x118f9c0_0 .net "out", 0 0, L_0x130d1b0; alias, 1 drivers +v0x118fa90_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x118a620 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x118a400; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cfa0f0_0 .net "A", 7 0, L_0x1ec1810; alias, 1 drivers -v0x1cfa1f0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cfa2b0_0 .net *"_s0", 0 0, L_0x1e76290; 1 drivers -v0x1cfa370_0 .net *"_s12", 0 0, L_0x1e76c00; 1 drivers -v0x1cfa450_0 .net *"_s16", 0 0, L_0x1e76f60; 1 drivers -v0x1cfa580_0 .net *"_s20", 0 0, L_0x1e77270; 1 drivers -v0x1cfa660_0 .net *"_s24", 0 0, L_0x1e77660; 1 drivers -v0x1cfa740_0 .net *"_s28", 0 0, L_0x1e775f0; 1 drivers -v0x1cfa820_0 .net *"_s4", 0 0, L_0x1e765a0; 1 drivers -v0x1cfa990_0 .net *"_s8", 0 0, L_0x1e768f0; 1 drivers -v0x1cfaa70_0 .net "out", 7 0, L_0x1e77970; alias, 1 drivers -L_0x1e76350 .part L_0x1ec1810, 0, 1; -L_0x1e764b0 .part v0x1d6daa0_0, 0, 1; -L_0x1e76660 .part L_0x1ec1810, 1, 1; -L_0x1e76850 .part v0x1d6daa0_0, 1, 1; -L_0x1e769b0 .part L_0x1ec1810, 2, 1; -L_0x1e76b10 .part v0x1d6daa0_0, 2, 1; -L_0x1e76cc0 .part L_0x1ec1810, 3, 1; -L_0x1e76e20 .part v0x1d6daa0_0, 3, 1; -L_0x1e77020 .part L_0x1ec1810, 4, 1; -L_0x1e77180 .part v0x1d6daa0_0, 4, 1; -L_0x1e772e0 .part L_0x1ec1810, 5, 1; -L_0x1e77550 .part v0x1d6daa0_0, 5, 1; -L_0x1e77720 .part L_0x1ec1810, 6, 1; -L_0x1e77880 .part v0x1d6daa0_0, 6, 1; -LS_0x1e77970_0_0 .concat8 [ 1 1 1 1], L_0x1e76290, L_0x1e765a0, L_0x1e768f0, L_0x1e76c00; -LS_0x1e77970_0_4 .concat8 [ 1 1 1 1], L_0x1e76f60, L_0x1e77270, L_0x1e77660, L_0x1e775f0; -L_0x1e77970 .concat8 [ 4 4 0 0], LS_0x1e77970_0_0, LS_0x1e77970_0_4; -L_0x1e77d30 .part L_0x1ec1810, 7, 1; -L_0x1e77f20 .part v0x1d6daa0_0, 7, 1; -S_0x1cf7c20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf7e30 .param/l "i" 0 4 54, +C4<00>; -L_0x1e76290/d .functor AND 1, L_0x1e76350, L_0x1e764b0, C4<1>, C4<1>; -L_0x1e76290 .delay 1 (30000,30000,30000) L_0x1e76290/d; -v0x1cf7f10_0 .net *"_s0", 0 0, L_0x1e76350; 1 drivers -v0x1cf7ff0_0 .net *"_s1", 0 0, L_0x1e764b0; 1 drivers -S_0x1cf80d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf82e0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e765a0/d .functor AND 1, L_0x1e76660, L_0x1e76850, C4<1>, C4<1>; -L_0x1e765a0 .delay 1 (30000,30000,30000) L_0x1e765a0/d; -v0x1cf83a0_0 .net *"_s0", 0 0, L_0x1e76660; 1 drivers -v0x1cf8480_0 .net *"_s1", 0 0, L_0x1e76850; 1 drivers -S_0x1cf8560 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf8770 .param/l "i" 0 4 54, +C4<010>; -L_0x1e768f0/d .functor AND 1, L_0x1e769b0, L_0x1e76b10, C4<1>, C4<1>; -L_0x1e768f0 .delay 1 (30000,30000,30000) L_0x1e768f0/d; -v0x1cf8810_0 .net *"_s0", 0 0, L_0x1e769b0; 1 drivers -v0x1cf88f0_0 .net *"_s1", 0 0, L_0x1e76b10; 1 drivers -S_0x1cf89d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf8be0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e76c00/d .functor AND 1, L_0x1e76cc0, L_0x1e76e20, C4<1>, C4<1>; -L_0x1e76c00 .delay 1 (30000,30000,30000) L_0x1e76c00/d; -v0x1cf8ca0_0 .net *"_s0", 0 0, L_0x1e76cc0; 1 drivers -v0x1cf8d80_0 .net *"_s1", 0 0, L_0x1e76e20; 1 drivers -S_0x1cf8e60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf90c0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e76f60/d .functor AND 1, L_0x1e77020, L_0x1e77180, C4<1>, C4<1>; -L_0x1e76f60 .delay 1 (30000,30000,30000) L_0x1e76f60/d; -v0x1cf9180_0 .net *"_s0", 0 0, L_0x1e77020; 1 drivers -v0x1cf9260_0 .net *"_s1", 0 0, L_0x1e77180; 1 drivers -S_0x1cf9340 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf9550 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e77270/d .functor AND 1, L_0x1e772e0, L_0x1e77550, C4<1>, C4<1>; -L_0x1e77270 .delay 1 (30000,30000,30000) L_0x1e77270/d; -v0x1cf9610_0 .net *"_s0", 0 0, L_0x1e772e0; 1 drivers -v0x1cf96f0_0 .net *"_s1", 0 0, L_0x1e77550; 1 drivers -S_0x1cf97d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf99e0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e77660/d .functor AND 1, L_0x1e77720, L_0x1e77880, C4<1>, C4<1>; -L_0x1e77660 .delay 1 (30000,30000,30000) L_0x1e77660/d; -v0x1cf9aa0_0 .net *"_s0", 0 0, L_0x1e77720; 1 drivers -v0x1cf9b80_0 .net *"_s1", 0 0, L_0x1e77880; 1 drivers -S_0x1cf9c60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cf79c0; - .timescale -9 -12; -P_0x1cf9e70 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e775f0/d .functor AND 1, L_0x1e77d30, L_0x1e77f20, C4<1>, C4<1>; -L_0x1e775f0 .delay 1 (30000,30000,30000) L_0x1e775f0/d; -v0x1cf9f30_0 .net *"_s0", 0 0, L_0x1e77d30; 1 drivers -v0x1cfa010_0 .net *"_s1", 0 0, L_0x1e77f20; 1 drivers -S_0x1cfabd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cf77a0; +v0x118cd50_0 .net "A", 7 0, L_0x1355b40; alias, 1 drivers +v0x118ce50_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x118cf10_0 .net *"_s0", 0 0, L_0x1309a40; 1 drivers +v0x118cfd0_0 .net *"_s12", 0 0, L_0x130a3b0; 1 drivers +v0x118d0b0_0 .net *"_s16", 0 0, L_0x130a710; 1 drivers +v0x118d1e0_0 .net *"_s20", 0 0, L_0x130aa80; 1 drivers +v0x118d2c0_0 .net *"_s24", 0 0, L_0x130aea0; 1 drivers +v0x118d3a0_0 .net *"_s28", 0 0, L_0x130ae30; 1 drivers +v0x118d480_0 .net *"_s4", 0 0, L_0x1309d50; 1 drivers +v0x118d5f0_0 .net *"_s8", 0 0, L_0x130a0a0; 1 drivers +v0x118d6d0_0 .net "out", 7 0, L_0x130b1b0; alias, 1 drivers +L_0x1309b00 .part L_0x1355b40, 0, 1; +L_0x1309c60 .part v0x12010b0_0, 0, 1; +L_0x1309e10 .part L_0x1355b40, 1, 1; +L_0x130a000 .part v0x12010b0_0, 1, 1; +L_0x130a160 .part L_0x1355b40, 2, 1; +L_0x130a2c0 .part v0x12010b0_0, 2, 1; +L_0x130a470 .part L_0x1355b40, 3, 1; +L_0x130a5d0 .part v0x12010b0_0, 3, 1; +L_0x130a830 .part L_0x1355b40, 4, 1; +L_0x130a990 .part v0x12010b0_0, 4, 1; +L_0x130ab20 .part L_0x1355b40, 5, 1; +L_0x130ad90 .part v0x12010b0_0, 5, 1; +L_0x130af60 .part L_0x1355b40, 6, 1; +L_0x130b0c0 .part v0x12010b0_0, 6, 1; +LS_0x130b1b0_0_0 .concat8 [ 1 1 1 1], L_0x1309a40, L_0x1309d50, L_0x130a0a0, L_0x130a3b0; +LS_0x130b1b0_0_4 .concat8 [ 1 1 1 1], L_0x130a710, L_0x130aa80, L_0x130aea0, L_0x130ae30; +L_0x130b1b0 .concat8 [ 4 4 0 0], LS_0x130b1b0_0_0, LS_0x130b1b0_0_4; +L_0x130b570 .part L_0x1355b40, 7, 1; +L_0x130b760 .part v0x12010b0_0, 7, 1; +S_0x118a880 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118aa90 .param/l "i" 0 4 54, +C4<00>; +L_0x1309a40/d .functor AND 1, L_0x1309b00, L_0x1309c60, C4<1>, C4<1>; +L_0x1309a40 .delay 1 (30000,30000,30000) L_0x1309a40/d; +v0x118ab70_0 .net *"_s0", 0 0, L_0x1309b00; 1 drivers +v0x118ac50_0 .net *"_s1", 0 0, L_0x1309c60; 1 drivers +S_0x118ad30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118af40 .param/l "i" 0 4 54, +C4<01>; +L_0x1309d50/d .functor AND 1, L_0x1309e10, L_0x130a000, C4<1>, C4<1>; +L_0x1309d50 .delay 1 (30000,30000,30000) L_0x1309d50/d; +v0x118b000_0 .net *"_s0", 0 0, L_0x1309e10; 1 drivers +v0x118b0e0_0 .net *"_s1", 0 0, L_0x130a000; 1 drivers +S_0x118b1c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118b3d0 .param/l "i" 0 4 54, +C4<010>; +L_0x130a0a0/d .functor AND 1, L_0x130a160, L_0x130a2c0, C4<1>, C4<1>; +L_0x130a0a0 .delay 1 (30000,30000,30000) L_0x130a0a0/d; +v0x118b470_0 .net *"_s0", 0 0, L_0x130a160; 1 drivers +v0x118b550_0 .net *"_s1", 0 0, L_0x130a2c0; 1 drivers +S_0x118b630 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118b840 .param/l "i" 0 4 54, +C4<011>; +L_0x130a3b0/d .functor AND 1, L_0x130a470, L_0x130a5d0, C4<1>, C4<1>; +L_0x130a3b0 .delay 1 (30000,30000,30000) L_0x130a3b0/d; +v0x118b900_0 .net *"_s0", 0 0, L_0x130a470; 1 drivers +v0x118b9e0_0 .net *"_s1", 0 0, L_0x130a5d0; 1 drivers +S_0x118bac0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118bd20 .param/l "i" 0 4 54, +C4<0100>; +L_0x130a710/d .functor AND 1, L_0x130a830, L_0x130a990, C4<1>, C4<1>; +L_0x130a710 .delay 1 (30000,30000,30000) L_0x130a710/d; +v0x118bde0_0 .net *"_s0", 0 0, L_0x130a830; 1 drivers +v0x118bec0_0 .net *"_s1", 0 0, L_0x130a990; 1 drivers +S_0x118bfa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118c1b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x130aa80/d .functor AND 1, L_0x130ab20, L_0x130ad90, C4<1>, C4<1>; +L_0x130aa80 .delay 1 (30000,30000,30000) L_0x130aa80/d; +v0x118c270_0 .net *"_s0", 0 0, L_0x130ab20; 1 drivers +v0x118c350_0 .net *"_s1", 0 0, L_0x130ad90; 1 drivers +S_0x118c430 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118c640 .param/l "i" 0 4 54, +C4<0110>; +L_0x130aea0/d .functor AND 1, L_0x130af60, L_0x130b0c0, C4<1>, C4<1>; +L_0x130aea0 .delay 1 (30000,30000,30000) L_0x130aea0/d; +v0x118c700_0 .net *"_s0", 0 0, L_0x130af60; 1 drivers +v0x118c7e0_0 .net *"_s1", 0 0, L_0x130b0c0; 1 drivers +S_0x118c8c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x118a620; + .timescale -9 -12; +P_0x118cad0 .param/l "i" 0 4 54, +C4<0111>; +L_0x130ae30/d .functor AND 1, L_0x130b570, L_0x130b760, C4<1>, C4<1>; +L_0x130ae30 .delay 1 (30000,30000,30000) L_0x130ae30/d; +v0x118cb90_0 .net *"_s0", 0 0, L_0x130b570; 1 drivers +v0x118cc70_0 .net *"_s1", 0 0, L_0x130b760; 1 drivers +S_0x118d830 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x118a400; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e79970/d .functor OR 1, L_0x1e79a30, L_0x1e79be0, C4<0>, C4<0>; -L_0x1e79970 .delay 1 (30000,30000,30000) L_0x1e79970/d; -v0x1cfc720_0 .net *"_s10", 0 0, L_0x1e79a30; 1 drivers -v0x1cfc800_0 .net *"_s12", 0 0, L_0x1e79be0; 1 drivers -v0x1cfc8e0_0 .net "in", 7 0, L_0x1e77970; alias, 1 drivers -v0x1cfc9b0_0 .net "ors", 1 0, L_0x1e79790; 1 drivers -v0x1cfca70_0 .net "out", 0 0, L_0x1e79970; alias, 1 drivers -L_0x1e78b60 .part L_0x1e77970, 0, 4; -L_0x1e79790 .concat8 [ 1 1 0 0], L_0x1e78850, L_0x1e79480; -L_0x1e798d0 .part L_0x1e77970, 4, 4; -L_0x1e79a30 .part L_0x1e79790, 0, 1; -L_0x1e79be0 .part L_0x1e79790, 1, 1; -S_0x1cfad90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1cfabd0; +L_0x130d1b0/d .functor OR 1, L_0x130d270, L_0x130d420, C4<0>, C4<0>; +L_0x130d1b0 .delay 1 (30000,30000,30000) L_0x130d1b0/d; +v0x118f380_0 .net *"_s10", 0 0, L_0x130d270; 1 drivers +v0x118f460_0 .net *"_s12", 0 0, L_0x130d420; 1 drivers +v0x118f540_0 .net "in", 7 0, L_0x130b1b0; alias, 1 drivers +v0x118f610_0 .net "ors", 1 0, L_0x130cfd0; 1 drivers +v0x118f6d0_0 .net "out", 0 0, L_0x130d1b0; alias, 1 drivers +L_0x130c3a0 .part L_0x130b1b0, 0, 4; +L_0x130cfd0 .concat8 [ 1 1 0 0], L_0x130c090, L_0x130ccc0; +L_0x130d110 .part L_0x130b1b0, 4, 4; +L_0x130d270 .part L_0x130cfd0, 0, 1; +L_0x130d420 .part L_0x130cfd0, 1, 1; +S_0x118d9f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x118d830; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e78010/d .functor OR 1, L_0x1e780d0, L_0x1e78230, C4<0>, C4<0>; -L_0x1e78010 .delay 1 (30000,30000,30000) L_0x1e78010/d; -L_0x1e78460/d .functor OR 1, L_0x1e78570, L_0x1e786d0, C4<0>, C4<0>; -L_0x1e78460 .delay 1 (30000,30000,30000) L_0x1e78460/d; -L_0x1e78850/d .functor OR 1, L_0x1e788c0, L_0x1e78a70, C4<0>, C4<0>; -L_0x1e78850 .delay 1 (30000,30000,30000) L_0x1e78850/d; -v0x1cfafe0_0 .net *"_s0", 0 0, L_0x1e78010; 1 drivers -v0x1cfb0e0_0 .net *"_s10", 0 0, L_0x1e78570; 1 drivers -v0x1cfb1c0_0 .net *"_s12", 0 0, L_0x1e786d0; 1 drivers -v0x1cfb280_0 .net *"_s14", 0 0, L_0x1e788c0; 1 drivers -v0x1cfb360_0 .net *"_s16", 0 0, L_0x1e78a70; 1 drivers -v0x1cfb490_0 .net *"_s3", 0 0, L_0x1e780d0; 1 drivers -v0x1cfb570_0 .net *"_s5", 0 0, L_0x1e78230; 1 drivers -v0x1cfb650_0 .net *"_s6", 0 0, L_0x1e78460; 1 drivers -v0x1cfb730_0 .net "in", 3 0, L_0x1e78b60; 1 drivers -v0x1cfb8a0_0 .net "ors", 1 0, L_0x1e78370; 1 drivers -v0x1cfb980_0 .net "out", 0 0, L_0x1e78850; 1 drivers -L_0x1e780d0 .part L_0x1e78b60, 0, 1; -L_0x1e78230 .part L_0x1e78b60, 1, 1; -L_0x1e78370 .concat8 [ 1 1 0 0], L_0x1e78010, L_0x1e78460; -L_0x1e78570 .part L_0x1e78b60, 2, 1; -L_0x1e786d0 .part L_0x1e78b60, 3, 1; -L_0x1e788c0 .part L_0x1e78370, 0, 1; -L_0x1e78a70 .part L_0x1e78370, 1, 1; -S_0x1cfbaa0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1cfabd0; +L_0x130b850/d .functor OR 1, L_0x130b910, L_0x130ba70, C4<0>, C4<0>; +L_0x130b850 .delay 1 (30000,30000,30000) L_0x130b850/d; +L_0x130bca0/d .functor OR 1, L_0x130bdb0, L_0x130bf10, C4<0>, C4<0>; +L_0x130bca0 .delay 1 (30000,30000,30000) L_0x130bca0/d; +L_0x130c090/d .functor OR 1, L_0x130c100, L_0x130c2b0, C4<0>, C4<0>; +L_0x130c090 .delay 1 (30000,30000,30000) L_0x130c090/d; +v0x118dc40_0 .net *"_s0", 0 0, L_0x130b850; 1 drivers +v0x118dd40_0 .net *"_s10", 0 0, L_0x130bdb0; 1 drivers +v0x118de20_0 .net *"_s12", 0 0, L_0x130bf10; 1 drivers +v0x118dee0_0 .net *"_s14", 0 0, L_0x130c100; 1 drivers +v0x118dfc0_0 .net *"_s16", 0 0, L_0x130c2b0; 1 drivers +v0x118e0f0_0 .net *"_s3", 0 0, L_0x130b910; 1 drivers +v0x118e1d0_0 .net *"_s5", 0 0, L_0x130ba70; 1 drivers +v0x118e2b0_0 .net *"_s6", 0 0, L_0x130bca0; 1 drivers +v0x118e390_0 .net "in", 3 0, L_0x130c3a0; 1 drivers +v0x118e500_0 .net "ors", 1 0, L_0x130bbb0; 1 drivers +v0x118e5e0_0 .net "out", 0 0, L_0x130c090; 1 drivers +L_0x130b910 .part L_0x130c3a0, 0, 1; +L_0x130ba70 .part L_0x130c3a0, 1, 1; +L_0x130bbb0 .concat8 [ 1 1 0 0], L_0x130b850, L_0x130bca0; +L_0x130bdb0 .part L_0x130c3a0, 2, 1; +L_0x130bf10 .part L_0x130c3a0, 3, 1; +L_0x130c100 .part L_0x130bbb0, 0, 1; +L_0x130c2b0 .part L_0x130bbb0, 1, 1; +S_0x118e700 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x118d830; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e78c90/d .functor OR 1, L_0x1e78d00, L_0x1e78e60, C4<0>, C4<0>; -L_0x1e78c90 .delay 1 (30000,30000,30000) L_0x1e78c90/d; -L_0x1e79090/d .functor OR 1, L_0x1e791a0, L_0x1e79300, C4<0>, C4<0>; -L_0x1e79090 .delay 1 (30000,30000,30000) L_0x1e79090/d; -L_0x1e79480/d .functor OR 1, L_0x1e794f0, L_0x1e796a0, C4<0>, C4<0>; -L_0x1e79480 .delay 1 (30000,30000,30000) L_0x1e79480/d; -v0x1cfbc60_0 .net *"_s0", 0 0, L_0x1e78c90; 1 drivers -v0x1cfbd60_0 .net *"_s10", 0 0, L_0x1e791a0; 1 drivers -v0x1cfbe40_0 .net *"_s12", 0 0, L_0x1e79300; 1 drivers -v0x1cfbf00_0 .net *"_s14", 0 0, L_0x1e794f0; 1 drivers -v0x1cfbfe0_0 .net *"_s16", 0 0, L_0x1e796a0; 1 drivers -v0x1cfc110_0 .net *"_s3", 0 0, L_0x1e78d00; 1 drivers -v0x1cfc1f0_0 .net *"_s5", 0 0, L_0x1e78e60; 1 drivers -v0x1cfc2d0_0 .net *"_s6", 0 0, L_0x1e79090; 1 drivers -v0x1cfc3b0_0 .net "in", 3 0, L_0x1e798d0; 1 drivers -v0x1cfc520_0 .net "ors", 1 0, L_0x1e78fa0; 1 drivers -v0x1cfc600_0 .net "out", 0 0, L_0x1e79480; 1 drivers -L_0x1e78d00 .part L_0x1e798d0, 0, 1; -L_0x1e78e60 .part L_0x1e798d0, 1, 1; -L_0x1e78fa0 .concat8 [ 1 1 0 0], L_0x1e78c90, L_0x1e79090; -L_0x1e791a0 .part L_0x1e798d0, 2, 1; -L_0x1e79300 .part L_0x1e798d0, 3, 1; -L_0x1e794f0 .part L_0x1e78fa0, 0, 1; -L_0x1e796a0 .part L_0x1e78fa0, 1, 1; -S_0x1cfcf10 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1cf6040; +L_0x130c4d0/d .functor OR 1, L_0x130c540, L_0x130c6a0, C4<0>, C4<0>; +L_0x130c4d0 .delay 1 (30000,30000,30000) L_0x130c4d0/d; +L_0x130c8d0/d .functor OR 1, L_0x130c9e0, L_0x130cb40, C4<0>, C4<0>; +L_0x130c8d0 .delay 1 (30000,30000,30000) L_0x130c8d0/d; +L_0x130ccc0/d .functor OR 1, L_0x130cd30, L_0x130cee0, C4<0>, C4<0>; +L_0x130ccc0 .delay 1 (30000,30000,30000) L_0x130ccc0/d; +v0x118e8c0_0 .net *"_s0", 0 0, L_0x130c4d0; 1 drivers +v0x118e9c0_0 .net *"_s10", 0 0, L_0x130c9e0; 1 drivers +v0x118eaa0_0 .net *"_s12", 0 0, L_0x130cb40; 1 drivers +v0x118eb60_0 .net *"_s14", 0 0, L_0x130cd30; 1 drivers +v0x118ec40_0 .net *"_s16", 0 0, L_0x130cee0; 1 drivers +v0x118ed70_0 .net *"_s3", 0 0, L_0x130c540; 1 drivers +v0x118ee50_0 .net *"_s5", 0 0, L_0x130c6a0; 1 drivers +v0x118ef30_0 .net *"_s6", 0 0, L_0x130c8d0; 1 drivers +v0x118f010_0 .net "in", 3 0, L_0x130d110; 1 drivers +v0x118f180_0 .net "ors", 1 0, L_0x130c7e0; 1 drivers +v0x118f260_0 .net "out", 0 0, L_0x130ccc0; 1 drivers +L_0x130c540 .part L_0x130d110, 0, 1; +L_0x130c6a0 .part L_0x130d110, 1, 1; +L_0x130c7e0 .concat8 [ 1 1 0 0], L_0x130c4d0, L_0x130c8d0; +L_0x130c9e0 .part L_0x130d110, 2, 1; +L_0x130cb40 .part L_0x130d110, 3, 1; +L_0x130cd30 .part L_0x130c7e0, 0, 1; +L_0x130cee0 .part L_0x130c7e0, 1, 1; +S_0x118fb70 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1188ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d02340_0 .net "ands", 7 0, L_0x1e73f30; 1 drivers -v0x1d02450_0 .net "in", 7 0, L_0x1e72470; alias, 1 drivers -v0x1d02510_0 .net "out", 0 0, L_0x1e75f30; alias, 1 drivers -v0x1d025e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1cfd160 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1cfcf10; +v0x1194fa0_0 .net "ands", 7 0, L_0x13076e0; 1 drivers +v0x11950b0_0 .net "in", 7 0, L_0x1305b40; alias, 1 drivers +v0x1195170_0 .net "out", 0 0, L_0x13096e0; alias, 1 drivers +v0x1195240_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x118fdc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x118fb70; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1cff8a0_0 .net "A", 7 0, L_0x1e72470; alias, 1 drivers -v0x1cff9a0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1cffa60_0 .net *"_s0", 0 0, L_0x1e72800; 1 drivers -v0x1cffb20_0 .net *"_s12", 0 0, L_0x1e731c0; 1 drivers -v0x1cffc00_0 .net *"_s16", 0 0, L_0x1e73520; 1 drivers -v0x1cffd30_0 .net *"_s20", 0 0, L_0x1e738f0; 1 drivers -v0x1cffe10_0 .net *"_s24", 0 0, L_0x1e73c20; 1 drivers -v0x1cffef0_0 .net *"_s28", 0 0, L_0x1e73bb0; 1 drivers -v0x1cfffd0_0 .net *"_s4", 0 0, L_0x1e72ba0; 1 drivers -v0x1d00140_0 .net *"_s8", 0 0, L_0x1e72eb0; 1 drivers -v0x1d00220_0 .net "out", 7 0, L_0x1e73f30; alias, 1 drivers -L_0x1e72910 .part L_0x1e72470, 0, 1; -L_0x1e72b00 .part v0x1d6daa0_0, 0, 1; -L_0x1e72c60 .part L_0x1e72470, 1, 1; -L_0x1e72dc0 .part v0x1d6daa0_0, 1, 1; -L_0x1e72f70 .part L_0x1e72470, 2, 1; -L_0x1e730d0 .part v0x1d6daa0_0, 2, 1; -L_0x1e73280 .part L_0x1e72470, 3, 1; -L_0x1e733e0 .part v0x1d6daa0_0, 3, 1; -L_0x1e735e0 .part L_0x1e72470, 4, 1; -L_0x1e73850 .part v0x1d6daa0_0, 4, 1; -L_0x1e73960 .part L_0x1e72470, 5, 1; -L_0x1e73ac0 .part v0x1d6daa0_0, 5, 1; -L_0x1e73ce0 .part L_0x1e72470, 6, 1; -L_0x1e73e40 .part v0x1d6daa0_0, 6, 1; -LS_0x1e73f30_0_0 .concat8 [ 1 1 1 1], L_0x1e72800, L_0x1e72ba0, L_0x1e72eb0, L_0x1e731c0; -LS_0x1e73f30_0_4 .concat8 [ 1 1 1 1], L_0x1e73520, L_0x1e738f0, L_0x1e73c20, L_0x1e73bb0; -L_0x1e73f30 .concat8 [ 4 4 0 0], LS_0x1e73f30_0_0, LS_0x1e73f30_0_4; -L_0x1e742f0 .part L_0x1e72470, 7, 1; -L_0x1e744e0 .part v0x1d6daa0_0, 7, 1; -S_0x1cfd3a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cfd5b0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e72800/d .functor AND 1, L_0x1e72910, L_0x1e72b00, C4<1>, C4<1>; -L_0x1e72800 .delay 1 (30000,30000,30000) L_0x1e72800/d; -v0x1cfd690_0 .net *"_s0", 0 0, L_0x1e72910; 1 drivers -v0x1cfd770_0 .net *"_s1", 0 0, L_0x1e72b00; 1 drivers -S_0x1cfd850 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cfda60 .param/l "i" 0 4 54, +C4<01>; -L_0x1e72ba0/d .functor AND 1, L_0x1e72c60, L_0x1e72dc0, C4<1>, C4<1>; -L_0x1e72ba0 .delay 1 (30000,30000,30000) L_0x1e72ba0/d; -v0x1cfdb20_0 .net *"_s0", 0 0, L_0x1e72c60; 1 drivers -v0x1cfdc00_0 .net *"_s1", 0 0, L_0x1e72dc0; 1 drivers -S_0x1cfdce0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cfdf20 .param/l "i" 0 4 54, +C4<010>; -L_0x1e72eb0/d .functor AND 1, L_0x1e72f70, L_0x1e730d0, C4<1>, C4<1>; -L_0x1e72eb0 .delay 1 (30000,30000,30000) L_0x1e72eb0/d; -v0x1cfdfc0_0 .net *"_s0", 0 0, L_0x1e72f70; 1 drivers -v0x1cfe0a0_0 .net *"_s1", 0 0, L_0x1e730d0; 1 drivers -S_0x1cfe180 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cfe390 .param/l "i" 0 4 54, +C4<011>; -L_0x1e731c0/d .functor AND 1, L_0x1e73280, L_0x1e733e0, C4<1>, C4<1>; -L_0x1e731c0 .delay 1 (30000,30000,30000) L_0x1e731c0/d; -v0x1cfe450_0 .net *"_s0", 0 0, L_0x1e73280; 1 drivers -v0x1cfe530_0 .net *"_s1", 0 0, L_0x1e733e0; 1 drivers -S_0x1cfe610 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cfe870 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e73520/d .functor AND 1, L_0x1e735e0, L_0x1e73850, C4<1>, C4<1>; -L_0x1e73520 .delay 1 (30000,30000,30000) L_0x1e73520/d; -v0x1cfe930_0 .net *"_s0", 0 0, L_0x1e735e0; 1 drivers -v0x1cfea10_0 .net *"_s1", 0 0, L_0x1e73850; 1 drivers -S_0x1cfeaf0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cfed00 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e738f0/d .functor AND 1, L_0x1e73960, L_0x1e73ac0, C4<1>, C4<1>; -L_0x1e738f0 .delay 1 (30000,30000,30000) L_0x1e738f0/d; -v0x1cfedc0_0 .net *"_s0", 0 0, L_0x1e73960; 1 drivers -v0x1cfeea0_0 .net *"_s1", 0 0, L_0x1e73ac0; 1 drivers -S_0x1cfef80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cff190 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e73c20/d .functor AND 1, L_0x1e73ce0, L_0x1e73e40, C4<1>, C4<1>; -L_0x1e73c20 .delay 1 (30000,30000,30000) L_0x1e73c20/d; -v0x1cff250_0 .net *"_s0", 0 0, L_0x1e73ce0; 1 drivers -v0x1cff330_0 .net *"_s1", 0 0, L_0x1e73e40; 1 drivers -S_0x1cff410 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1cfd160; - .timescale -9 -12; -P_0x1cff620 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e73bb0/d .functor AND 1, L_0x1e742f0, L_0x1e744e0, C4<1>, C4<1>; -L_0x1e73bb0 .delay 1 (30000,30000,30000) L_0x1e73bb0/d; -v0x1cff6e0_0 .net *"_s0", 0 0, L_0x1e742f0; 1 drivers -v0x1cff7c0_0 .net *"_s1", 0 0, L_0x1e744e0; 1 drivers -S_0x1d00380 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1cfcf10; +v0x1192500_0 .net "A", 7 0, L_0x1305b40; alias, 1 drivers +v0x1192600_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11926c0_0 .net *"_s0", 0 0, L_0x1305ed0; 1 drivers +v0x1192780_0 .net *"_s12", 0 0, L_0x1306890; 1 drivers +v0x1192860_0 .net *"_s16", 0 0, L_0x1306bf0; 1 drivers +v0x1192990_0 .net *"_s20", 0 0, L_0x1307020; 1 drivers +v0x1192a70_0 .net *"_s24", 0 0, L_0x1307350; 1 drivers +v0x1192b50_0 .net *"_s28", 0 0, L_0x13072e0; 1 drivers +v0x1192c30_0 .net *"_s4", 0 0, L_0x1306270; 1 drivers +v0x1192da0_0 .net *"_s8", 0 0, L_0x1306580; 1 drivers +v0x1192e80_0 .net "out", 7 0, L_0x13076e0; alias, 1 drivers +L_0x1305fe0 .part L_0x1305b40, 0, 1; +L_0x13061d0 .part v0x12010b0_0, 0, 1; +L_0x1306330 .part L_0x1305b40, 1, 1; +L_0x1306490 .part v0x12010b0_0, 1, 1; +L_0x1306640 .part L_0x1305b40, 2, 1; +L_0x13067a0 .part v0x12010b0_0, 2, 1; +L_0x1306950 .part L_0x1305b40, 3, 1; +L_0x1306ab0 .part v0x12010b0_0, 3, 1; +L_0x1306cb0 .part L_0x1305b40, 4, 1; +L_0x1306f20 .part v0x12010b0_0, 4, 1; +L_0x1307090 .part L_0x1305b40, 5, 1; +L_0x13071f0 .part v0x12010b0_0, 5, 1; +L_0x1307410 .part L_0x1305b40, 6, 1; +L_0x1307570 .part v0x12010b0_0, 6, 1; +LS_0x13076e0_0_0 .concat8 [ 1 1 1 1], L_0x1305ed0, L_0x1306270, L_0x1306580, L_0x1306890; +LS_0x13076e0_0_4 .concat8 [ 1 1 1 1], L_0x1306bf0, L_0x1307020, L_0x1307350, L_0x13072e0; +L_0x13076e0 .concat8 [ 4 4 0 0], LS_0x13076e0_0_0, LS_0x13076e0_0_4; +L_0x1307aa0 .part L_0x1305b40, 7, 1; +L_0x1307c90 .part v0x12010b0_0, 7, 1; +S_0x1190000 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x1190210 .param/l "i" 0 4 54, +C4<00>; +L_0x1305ed0/d .functor AND 1, L_0x1305fe0, L_0x13061d0, C4<1>, C4<1>; +L_0x1305ed0 .delay 1 (30000,30000,30000) L_0x1305ed0/d; +v0x11902f0_0 .net *"_s0", 0 0, L_0x1305fe0; 1 drivers +v0x11903d0_0 .net *"_s1", 0 0, L_0x13061d0; 1 drivers +S_0x11904b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x11906c0 .param/l "i" 0 4 54, +C4<01>; +L_0x1306270/d .functor AND 1, L_0x1306330, L_0x1306490, C4<1>, C4<1>; +L_0x1306270 .delay 1 (30000,30000,30000) L_0x1306270/d; +v0x1190780_0 .net *"_s0", 0 0, L_0x1306330; 1 drivers +v0x1190860_0 .net *"_s1", 0 0, L_0x1306490; 1 drivers +S_0x1190940 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x1190b80 .param/l "i" 0 4 54, +C4<010>; +L_0x1306580/d .functor AND 1, L_0x1306640, L_0x13067a0, C4<1>, C4<1>; +L_0x1306580 .delay 1 (30000,30000,30000) L_0x1306580/d; +v0x1190c20_0 .net *"_s0", 0 0, L_0x1306640; 1 drivers +v0x1190d00_0 .net *"_s1", 0 0, L_0x13067a0; 1 drivers +S_0x1190de0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x1190ff0 .param/l "i" 0 4 54, +C4<011>; +L_0x1306890/d .functor AND 1, L_0x1306950, L_0x1306ab0, C4<1>, C4<1>; +L_0x1306890 .delay 1 (30000,30000,30000) L_0x1306890/d; +v0x11910b0_0 .net *"_s0", 0 0, L_0x1306950; 1 drivers +v0x1191190_0 .net *"_s1", 0 0, L_0x1306ab0; 1 drivers +S_0x1191270 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x11914d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1306bf0/d .functor AND 1, L_0x1306cb0, L_0x1306f20, C4<1>, C4<1>; +L_0x1306bf0 .delay 1 (30000,30000,30000) L_0x1306bf0/d; +v0x1191590_0 .net *"_s0", 0 0, L_0x1306cb0; 1 drivers +v0x1191670_0 .net *"_s1", 0 0, L_0x1306f20; 1 drivers +S_0x1191750 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x1191960 .param/l "i" 0 4 54, +C4<0101>; +L_0x1307020/d .functor AND 1, L_0x1307090, L_0x13071f0, C4<1>, C4<1>; +L_0x1307020 .delay 1 (30000,30000,30000) L_0x1307020/d; +v0x1191a20_0 .net *"_s0", 0 0, L_0x1307090; 1 drivers +v0x1191b00_0 .net *"_s1", 0 0, L_0x13071f0; 1 drivers +S_0x1191be0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x1191df0 .param/l "i" 0 4 54, +C4<0110>; +L_0x1307350/d .functor AND 1, L_0x1307410, L_0x1307570, C4<1>, C4<1>; +L_0x1307350 .delay 1 (30000,30000,30000) L_0x1307350/d; +v0x1191eb0_0 .net *"_s0", 0 0, L_0x1307410; 1 drivers +v0x1191f90_0 .net *"_s1", 0 0, L_0x1307570; 1 drivers +S_0x1192070 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x118fdc0; + .timescale -9 -12; +P_0x1192280 .param/l "i" 0 4 54, +C4<0111>; +L_0x13072e0/d .functor AND 1, L_0x1307aa0, L_0x1307c90, C4<1>, C4<1>; +L_0x13072e0 .delay 1 (30000,30000,30000) L_0x13072e0/d; +v0x1192340_0 .net *"_s0", 0 0, L_0x1307aa0; 1 drivers +v0x1192420_0 .net *"_s1", 0 0, L_0x1307c90; 1 drivers +S_0x1192fe0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x118fb70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e75f30/d .functor OR 1, L_0x1e75ff0, L_0x1e761a0, C4<0>, C4<0>; -L_0x1e75f30 .delay 1 (30000,30000,30000) L_0x1e75f30/d; -v0x1d01ed0_0 .net *"_s10", 0 0, L_0x1e75ff0; 1 drivers -v0x1d01fb0_0 .net *"_s12", 0 0, L_0x1e761a0; 1 drivers -v0x1d02090_0 .net "in", 7 0, L_0x1e73f30; alias, 1 drivers -v0x1d02160_0 .net "ors", 1 0, L_0x1e75d50; 1 drivers -v0x1d02220_0 .net "out", 0 0, L_0x1e75f30; alias, 1 drivers -L_0x1e75120 .part L_0x1e73f30, 0, 4; -L_0x1e75d50 .concat8 [ 1 1 0 0], L_0x1e74e10, L_0x1e75a40; -L_0x1e75e90 .part L_0x1e73f30, 4, 4; -L_0x1e75ff0 .part L_0x1e75d50, 0, 1; -L_0x1e761a0 .part L_0x1e75d50, 1, 1; -S_0x1d00540 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d00380; +L_0x13096e0/d .functor OR 1, L_0x13097a0, L_0x1309950, C4<0>, C4<0>; +L_0x13096e0 .delay 1 (30000,30000,30000) L_0x13096e0/d; +v0x1194b30_0 .net *"_s10", 0 0, L_0x13097a0; 1 drivers +v0x1194c10_0 .net *"_s12", 0 0, L_0x1309950; 1 drivers +v0x1194cf0_0 .net "in", 7 0, L_0x13076e0; alias, 1 drivers +v0x1194dc0_0 .net "ors", 1 0, L_0x1309500; 1 drivers +v0x1194e80_0 .net "out", 0 0, L_0x13096e0; alias, 1 drivers +L_0x13088d0 .part L_0x13076e0, 0, 4; +L_0x1309500 .concat8 [ 1 1 0 0], L_0x13085c0, L_0x13091f0; +L_0x1309640 .part L_0x13076e0, 4, 4; +L_0x13097a0 .part L_0x1309500, 0, 1; +L_0x1309950 .part L_0x1309500, 1, 1; +S_0x11931a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1192fe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e745d0/d .functor OR 1, L_0x1e74690, L_0x1e747f0, C4<0>, C4<0>; -L_0x1e745d0 .delay 1 (30000,30000,30000) L_0x1e745d0/d; -L_0x1e74a20/d .functor OR 1, L_0x1e74b30, L_0x1e74c90, C4<0>, C4<0>; -L_0x1e74a20 .delay 1 (30000,30000,30000) L_0x1e74a20/d; -L_0x1e74e10/d .functor OR 1, L_0x1e74e80, L_0x1e75030, C4<0>, C4<0>; -L_0x1e74e10 .delay 1 (30000,30000,30000) L_0x1e74e10/d; -v0x1d00790_0 .net *"_s0", 0 0, L_0x1e745d0; 1 drivers -v0x1d00890_0 .net *"_s10", 0 0, L_0x1e74b30; 1 drivers -v0x1d00970_0 .net *"_s12", 0 0, L_0x1e74c90; 1 drivers -v0x1d00a30_0 .net *"_s14", 0 0, L_0x1e74e80; 1 drivers -v0x1d00b10_0 .net *"_s16", 0 0, L_0x1e75030; 1 drivers -v0x1d00c40_0 .net *"_s3", 0 0, L_0x1e74690; 1 drivers -v0x1d00d20_0 .net *"_s5", 0 0, L_0x1e747f0; 1 drivers -v0x1d00e00_0 .net *"_s6", 0 0, L_0x1e74a20; 1 drivers -v0x1d00ee0_0 .net "in", 3 0, L_0x1e75120; 1 drivers -v0x1d01050_0 .net "ors", 1 0, L_0x1e74930; 1 drivers -v0x1d01130_0 .net "out", 0 0, L_0x1e74e10; 1 drivers -L_0x1e74690 .part L_0x1e75120, 0, 1; -L_0x1e747f0 .part L_0x1e75120, 1, 1; -L_0x1e74930 .concat8 [ 1 1 0 0], L_0x1e745d0, L_0x1e74a20; -L_0x1e74b30 .part L_0x1e75120, 2, 1; -L_0x1e74c90 .part L_0x1e75120, 3, 1; -L_0x1e74e80 .part L_0x1e74930, 0, 1; -L_0x1e75030 .part L_0x1e74930, 1, 1; -S_0x1d01250 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d00380; +L_0x1307d80/d .functor OR 1, L_0x1307e40, L_0x1307fa0, C4<0>, C4<0>; +L_0x1307d80 .delay 1 (30000,30000,30000) L_0x1307d80/d; +L_0x13081d0/d .functor OR 1, L_0x13082e0, L_0x1308440, C4<0>, C4<0>; +L_0x13081d0 .delay 1 (30000,30000,30000) L_0x13081d0/d; +L_0x13085c0/d .functor OR 1, L_0x1308630, L_0x13087e0, C4<0>, C4<0>; +L_0x13085c0 .delay 1 (30000,30000,30000) L_0x13085c0/d; +v0x11933f0_0 .net *"_s0", 0 0, L_0x1307d80; 1 drivers +v0x11934f0_0 .net *"_s10", 0 0, L_0x13082e0; 1 drivers +v0x11935d0_0 .net *"_s12", 0 0, L_0x1308440; 1 drivers +v0x1193690_0 .net *"_s14", 0 0, L_0x1308630; 1 drivers +v0x1193770_0 .net *"_s16", 0 0, L_0x13087e0; 1 drivers +v0x11938a0_0 .net *"_s3", 0 0, L_0x1307e40; 1 drivers +v0x1193980_0 .net *"_s5", 0 0, L_0x1307fa0; 1 drivers +v0x1193a60_0 .net *"_s6", 0 0, L_0x13081d0; 1 drivers +v0x1193b40_0 .net "in", 3 0, L_0x13088d0; 1 drivers +v0x1193cb0_0 .net "ors", 1 0, L_0x13080e0; 1 drivers +v0x1193d90_0 .net "out", 0 0, L_0x13085c0; 1 drivers +L_0x1307e40 .part L_0x13088d0, 0, 1; +L_0x1307fa0 .part L_0x13088d0, 1, 1; +L_0x13080e0 .concat8 [ 1 1 0 0], L_0x1307d80, L_0x13081d0; +L_0x13082e0 .part L_0x13088d0, 2, 1; +L_0x1308440 .part L_0x13088d0, 3, 1; +L_0x1308630 .part L_0x13080e0, 0, 1; +L_0x13087e0 .part L_0x13080e0, 1, 1; +S_0x1193eb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1192fe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e75250/d .functor OR 1, L_0x1e752c0, L_0x1e75420, C4<0>, C4<0>; -L_0x1e75250 .delay 1 (30000,30000,30000) L_0x1e75250/d; -L_0x1e75650/d .functor OR 1, L_0x1e75760, L_0x1e758c0, C4<0>, C4<0>; -L_0x1e75650 .delay 1 (30000,30000,30000) L_0x1e75650/d; -L_0x1e75a40/d .functor OR 1, L_0x1e75ab0, L_0x1e75c60, C4<0>, C4<0>; -L_0x1e75a40 .delay 1 (30000,30000,30000) L_0x1e75a40/d; -v0x1d01410_0 .net *"_s0", 0 0, L_0x1e75250; 1 drivers -v0x1d01510_0 .net *"_s10", 0 0, L_0x1e75760; 1 drivers -v0x1d015f0_0 .net *"_s12", 0 0, L_0x1e758c0; 1 drivers -v0x1d016b0_0 .net *"_s14", 0 0, L_0x1e75ab0; 1 drivers -v0x1d01790_0 .net *"_s16", 0 0, L_0x1e75c60; 1 drivers -v0x1d018c0_0 .net *"_s3", 0 0, L_0x1e752c0; 1 drivers -v0x1d019a0_0 .net *"_s5", 0 0, L_0x1e75420; 1 drivers -v0x1d01a80_0 .net *"_s6", 0 0, L_0x1e75650; 1 drivers -v0x1d01b60_0 .net "in", 3 0, L_0x1e75e90; 1 drivers -v0x1d01cd0_0 .net "ors", 1 0, L_0x1e75560; 1 drivers -v0x1d01db0_0 .net "out", 0 0, L_0x1e75a40; 1 drivers -L_0x1e752c0 .part L_0x1e75e90, 0, 1; -L_0x1e75420 .part L_0x1e75e90, 1, 1; -L_0x1e75560 .concat8 [ 1 1 0 0], L_0x1e75250, L_0x1e75650; -L_0x1e75760 .part L_0x1e75e90, 2, 1; -L_0x1e758c0 .part L_0x1e75e90, 3, 1; -L_0x1e75ab0 .part L_0x1e75560, 0, 1; -L_0x1e75c60 .part L_0x1e75560, 1, 1; -S_0x1d026c0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cf6040; +L_0x1308a00/d .functor OR 1, L_0x1308a70, L_0x1308bd0, C4<0>, C4<0>; +L_0x1308a00 .delay 1 (30000,30000,30000) L_0x1308a00/d; +L_0x1308e00/d .functor OR 1, L_0x1308f10, L_0x1309070, C4<0>, C4<0>; +L_0x1308e00 .delay 1 (30000,30000,30000) L_0x1308e00/d; +L_0x13091f0/d .functor OR 1, L_0x1309260, L_0x1309410, C4<0>, C4<0>; +L_0x13091f0 .delay 1 (30000,30000,30000) L_0x13091f0/d; +v0x1194070_0 .net *"_s0", 0 0, L_0x1308a00; 1 drivers +v0x1194170_0 .net *"_s10", 0 0, L_0x1308f10; 1 drivers +v0x1194250_0 .net *"_s12", 0 0, L_0x1309070; 1 drivers +v0x1194310_0 .net *"_s14", 0 0, L_0x1309260; 1 drivers +v0x11943f0_0 .net *"_s16", 0 0, L_0x1309410; 1 drivers +v0x1194520_0 .net *"_s3", 0 0, L_0x1308a70; 1 drivers +v0x1194600_0 .net *"_s5", 0 0, L_0x1308bd0; 1 drivers +v0x11946e0_0 .net *"_s6", 0 0, L_0x1308e00; 1 drivers +v0x11947c0_0 .net "in", 3 0, L_0x1309640; 1 drivers +v0x1194930_0 .net "ors", 1 0, L_0x1308d10; 1 drivers +v0x1194a10_0 .net "out", 0 0, L_0x13091f0; 1 drivers +L_0x1308a70 .part L_0x1309640, 0, 1; +L_0x1308bd0 .part L_0x1309640, 1, 1; +L_0x1308d10 .concat8 [ 1 1 0 0], L_0x1308a00, L_0x1308e00; +L_0x1308f10 .part L_0x1309640, 2, 1; +L_0x1309070 .part L_0x1309640, 3, 1; +L_0x1309260 .part L_0x1308d10, 0, 1; +L_0x1309410 .part L_0x1308d10, 1, 1; +S_0x1195320 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1188ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -14428,80 +14438,80 @@ S_0x1d026c0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1cf6040; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e717e0/d .functor XNOR 1, L_0x1e79dd0, L_0x1e79f30, C4<0>, C4<0>; -L_0x1e717e0 .delay 1 (20000,20000,20000) L_0x1e717e0/d; -L_0x1e71a50/d .functor AND 1, L_0x1e79dd0, L_0x1e706d0, C4<1>, C4<1>; -L_0x1e71a50 .delay 1 (30000,30000,30000) L_0x1e71a50/d; -L_0x1e71ac0/d .functor AND 1, L_0x1e717e0, L_0x1e702f0, C4<1>, C4<1>; -L_0x1e71ac0 .delay 1 (30000,30000,30000) L_0x1e71ac0/d; -L_0x1e71c20/d .functor OR 1, L_0x1e71ac0, L_0x1e71a50, C4<0>, C4<0>; -L_0x1e71c20 .delay 1 (30000,30000,30000) L_0x1e71c20/d; -v0x1d02970_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers -v0x1d02a60_0 .net "a_", 0 0, L_0x1e705c0; alias, 1 drivers -v0x1d02b20_0 .net "b", 0 0, L_0x1e79f30; alias, 1 drivers -v0x1d02c10_0 .net "b_", 0 0, L_0x1e706d0; alias, 1 drivers -v0x1d02cb0_0 .net "carryin", 0 0, L_0x1e702f0; alias, 1 drivers -v0x1d02df0_0 .net "eq", 0 0, L_0x1e717e0; 1 drivers -v0x1d02eb0_0 .net "lt", 0 0, L_0x1e71a50; 1 drivers -v0x1d02f70_0 .net "out", 0 0, L_0x1e71c20; 1 drivers -v0x1d03030_0 .net "w0", 0 0, L_0x1e71ac0; 1 drivers -S_0x1d03280 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1cf6040; +L_0x1304eb0/d .functor XNOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; +L_0x1304eb0 .delay 1 (20000,20000,20000) L_0x1304eb0/d; +L_0x1305120/d .functor AND 1, L_0x130d610, L_0x1303df0, C4<1>, C4<1>; +L_0x1305120 .delay 1 (30000,30000,30000) L_0x1305120/d; +L_0x1305190/d .functor AND 1, L_0x1304eb0, L_0x1303b20, C4<1>, C4<1>; +L_0x1305190 .delay 1 (30000,30000,30000) L_0x1305190/d; +L_0x13052f0/d .functor OR 1, L_0x1305190, L_0x1305120, C4<0>, C4<0>; +L_0x13052f0 .delay 1 (30000,30000,30000) L_0x13052f0/d; +v0x11955d0_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers +v0x11956c0_0 .net "a_", 0 0, L_0x12fa140; alias, 1 drivers +v0x1195780_0 .net "b", 0 0, L_0x130d770; alias, 1 drivers +v0x1195870_0 .net "b_", 0 0, L_0x1303df0; alias, 1 drivers +v0x1195910_0 .net "carryin", 0 0, L_0x1303b20; alias, 1 drivers +v0x1195a50_0 .net "eq", 0 0, L_0x1304eb0; 1 drivers +v0x1195b10_0 .net "lt", 0 0, L_0x1305120; 1 drivers +v0x1195bd0_0 .net "out", 0 0, L_0x13052f0; 1 drivers +v0x1195c90_0 .net "w0", 0 0, L_0x1305190; 1 drivers +S_0x1195ee0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1188ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e715c0/d .functor OR 1, L_0x1e710c0, L_0x1d044e0, C4<0>, C4<0>; -L_0x1e715c0 .delay 1 (30000,30000,30000) L_0x1e715c0/d; -v0x1d04070_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers -v0x1d041c0_0 .net "b", 0 0, L_0x1e706d0; alias, 1 drivers -v0x1d04280_0 .net "c1", 0 0, L_0x1e710c0; 1 drivers -v0x1d04320_0 .net "c2", 0 0, L_0x1d044e0; 1 drivers -v0x1d043f0_0 .net "carryin", 0 0, L_0x1e702f0; alias, 1 drivers -v0x1d04570_0 .net "carryout", 0 0, L_0x1e715c0; 1 drivers -v0x1d04610_0 .net "s1", 0 0, L_0x1e71000; 1 drivers -v0x1d046b0_0 .net "sum", 0 0, L_0x1e71220; 1 drivers -S_0x1d034d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d03280; +L_0x1304c90/d .functor OR 1, L_0x13047e0, L_0x1197140, C4<0>, C4<0>; +L_0x1304c90 .delay 1 (30000,30000,30000) L_0x1304c90/d; +v0x1196cd0_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers +v0x1196e20_0 .net "b", 0 0, L_0x1303df0; alias, 1 drivers +v0x1196ee0_0 .net "c1", 0 0, L_0x13047e0; 1 drivers +v0x1196f80_0 .net "c2", 0 0, L_0x1197140; 1 drivers +v0x1197050_0 .net "carryin", 0 0, L_0x1303b20; alias, 1 drivers +v0x11971d0_0 .net "carryout", 0 0, L_0x1304c90; 1 drivers +v0x1197270_0 .net "s1", 0 0, L_0x1304720; 1 drivers +v0x1197310_0 .net "sum", 0 0, L_0x1304940; 1 drivers +S_0x1196130 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1195ee0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e71000/d .functor XOR 1, L_0x1e79dd0, L_0x1e706d0, C4<0>, C4<0>; -L_0x1e71000 .delay 1 (30000,30000,30000) L_0x1e71000/d; -L_0x1e710c0/d .functor AND 1, L_0x1e79dd0, L_0x1e706d0, C4<1>, C4<1>; -L_0x1e710c0 .delay 1 (30000,30000,30000) L_0x1e710c0/d; -v0x1d03730_0 .net "a", 0 0, L_0x1e79dd0; alias, 1 drivers -v0x1d037f0_0 .net "b", 0 0, L_0x1e706d0; alias, 1 drivers -v0x1d038b0_0 .net "carryout", 0 0, L_0x1e710c0; alias, 1 drivers -v0x1d03950_0 .net "sum", 0 0, L_0x1e71000; alias, 1 drivers -S_0x1d03a80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d03280; +L_0x1304720/d .functor XOR 1, L_0x130d610, L_0x1303df0, C4<0>, C4<0>; +L_0x1304720 .delay 1 (30000,30000,30000) L_0x1304720/d; +L_0x13047e0/d .functor AND 1, L_0x130d610, L_0x1303df0, C4<1>, C4<1>; +L_0x13047e0 .delay 1 (30000,30000,30000) L_0x13047e0/d; +v0x1196390_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers +v0x1196450_0 .net "b", 0 0, L_0x1303df0; alias, 1 drivers +v0x1196510_0 .net "carryout", 0 0, L_0x13047e0; alias, 1 drivers +v0x11965b0_0 .net "sum", 0 0, L_0x1304720; alias, 1 drivers +S_0x11966e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1195ee0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e71220/d .functor XOR 1, L_0x1e71000, L_0x1e702f0, C4<0>, C4<0>; -L_0x1e71220 .delay 1 (30000,30000,30000) L_0x1e71220/d; -L_0x1d044e0/d .functor AND 1, L_0x1e71000, L_0x1e702f0, C4<1>, C4<1>; -L_0x1d044e0 .delay 1 (30000,30000,30000) L_0x1d044e0/d; -v0x1d03ce0_0 .net "a", 0 0, L_0x1e71000; alias, 1 drivers -v0x1d03db0_0 .net "b", 0 0, L_0x1e702f0; alias, 1 drivers -v0x1d03e50_0 .net "carryout", 0 0, L_0x1d044e0; alias, 1 drivers -v0x1d03f20_0 .net "sum", 0 0, L_0x1e71220; alias, 1 drivers -S_0x1d05ad0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1cf5d70; - .timescale -9 -12; -L_0x7f72592dbd58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbda0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e79e70/d .functor OR 1, L_0x7f72592dbd58, L_0x7f72592dbda0, C4<0>, C4<0>; -L_0x1e79e70 .delay 1 (30000,30000,30000) L_0x1e79e70/d; -v0x1d05cc0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbd58; 1 drivers -v0x1d05da0_0 .net/2u *"_s2", 0 0, L_0x7f72592dbda0; 1 drivers -S_0x1d05e80 .scope generate, "alu_slices[27]" "alu_slices[27]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1d06090 .param/l "i" 0 3 37, +C4<011011>; -S_0x1d06150 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d05e80; +L_0x1304940/d .functor XOR 1, L_0x1304720, L_0x1303b20, C4<0>, C4<0>; +L_0x1304940 .delay 1 (30000,30000,30000) L_0x1304940/d; +L_0x1197140/d .functor AND 1, L_0x1304720, L_0x1303b20, C4<1>, C4<1>; +L_0x1197140 .delay 1 (30000,30000,30000) L_0x1197140/d; +v0x1196940_0 .net "a", 0 0, L_0x1304720; alias, 1 drivers +v0x1196a10_0 .net "b", 0 0, L_0x1303b20; alias, 1 drivers +v0x1196ab0_0 .net "carryout", 0 0, L_0x1197140; alias, 1 drivers +v0x1196b80_0 .net "sum", 0 0, L_0x1304940; alias, 1 drivers +S_0x1198730 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11889d0; + .timescale -9 -12; +L_0x2b0ab3d06d58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06da0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x130d6b0/d .functor OR 1, L_0x2b0ab3d06d58, L_0x2b0ab3d06da0, C4<0>, C4<0>; +L_0x130d6b0 .delay 1 (30000,30000,30000) L_0x130d6b0/d; +v0x1198920_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06d58; 1 drivers +v0x1198a00_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06da0; 1 drivers +S_0x1198ae0 .scope generate, "alu_slices[27]" "alu_slices[27]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x1198cf0 .param/l "i" 0 3 41, +C4<011011>; +S_0x1198db0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1198ae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -14510,445 +14520,445 @@ S_0x1d06150 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d05e80; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e70480/d .functor NOT 1, L_0x1e83a40, C4<0>, C4<0>, C4<0>; -L_0x1e70480 .delay 1 (10000,10000,10000) L_0x1e70480/d; -L_0x1e7a300/d .functor NOT 1, L_0x1e79fd0, C4<0>, C4<0>, C4<0>; -L_0x1e7a300 .delay 1 (10000,10000,10000) L_0x1e7a300/d; -L_0x1e7b350/d .functor XOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; -L_0x1e7b350 .delay 1 (30000,30000,30000) L_0x1e7b350/d; -L_0x7f72592dbde8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbe30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e7ba00/d .functor OR 1, L_0x7f72592dbde8, L_0x7f72592dbe30, C4<0>, C4<0>; -L_0x1e7ba00 .delay 1 (30000,30000,30000) L_0x1e7ba00/d; -L_0x1e7bc00/d .functor AND 1, L_0x1e83a40, L_0x1e79fd0, C4<1>, C4<1>; -L_0x1e7bc00 .delay 1 (30000,30000,30000) L_0x1e7bc00/d; -L_0x1e7bcc0/d .functor NAND 1, L_0x1e83a40, L_0x1e79fd0, C4<1>, C4<1>; -L_0x1e7bcc0 .delay 1 (20000,20000,20000) L_0x1e7bcc0/d; -L_0x1e7be20/d .functor XOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; -L_0x1e7be20 .delay 1 (20000,20000,20000) L_0x1e7be20/d; -L_0x1e7c230/d .functor OR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; -L_0x1e7c230 .delay 1 (30000,30000,30000) L_0x1e7c230/d; -L_0x1e83940/d .functor NOT 1, L_0x1e7fba0, C4<0>, C4<0>, C4<0>; -L_0x1e83940 .delay 1 (10000,10000,10000) L_0x1e83940/d; -v0x1d14880_0 .net "A", 0 0, L_0x1e83a40; 1 drivers -v0x1d14940_0 .net "A_", 0 0, L_0x1e70480; 1 drivers -v0x1d14a00_0 .net "B", 0 0, L_0x1e79fd0; 1 drivers -v0x1d14ad0_0 .net "B_", 0 0, L_0x1e7a300; 1 drivers -v0x1d14b70_0 .net *"_s12", 0 0, L_0x1e7ba00; 1 drivers -v0x1d14c60_0 .net/2s *"_s14", 0 0, L_0x7f72592dbde8; 1 drivers -v0x1d14d20_0 .net/2s *"_s16", 0 0, L_0x7f72592dbe30; 1 drivers -v0x1d14e00_0 .net *"_s18", 0 0, L_0x1e7bc00; 1 drivers -v0x1d14ee0_0 .net *"_s20", 0 0, L_0x1e7bcc0; 1 drivers -v0x1d15010_0 .net *"_s22", 0 0, L_0x1e7be20; 1 drivers -v0x1d150d0_0 .net *"_s24", 0 0, L_0x1e7c230; 1 drivers -o0x7f7259334238 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1d151b0_0 name=_s30 -o0x7f7259334268 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1d15290_0 name=_s32 -v0x1d15370_0 .net *"_s8", 0 0, L_0x1e7b350; 1 drivers -v0x1d15450_0 .net "carryin", 0 0, L_0x1e7a070; 1 drivers -v0x1d154f0_0 .net "carryout", 0 0, L_0x1e835e0; 1 drivers -v0x1d15590_0 .net "carryouts", 7 0, L_0x1ec19e0; 1 drivers -v0x1d15740_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d157e0_0 .net "result", 0 0, L_0x1e7fba0; 1 drivers -v0x1d158d0_0 .net "results", 7 0, L_0x1e7a710; 1 drivers -v0x1d159e0_0 .net "zero", 0 0, L_0x1e83940; 1 drivers -LS_0x1e7a710_0_0 .concat8 [ 1 1 1 1], L_0x1e7a820, L_0x1e7ae50, L_0x1e7b350, L_0x1e7ba00; -LS_0x1e7a710_0_4 .concat8 [ 1 1 1 1], L_0x1e7bc00, L_0x1e7bcc0, L_0x1e7be20, L_0x1e7c230; -L_0x1e7a710 .concat8 [ 4 4 0 0], LS_0x1e7a710_0_0, LS_0x1e7a710_0_4; -LS_0x1ec19e0_0_0 .concat [ 1 1 1 1], L_0x1e7aad0, L_0x1e7b1f0, o0x7f7259334238, L_0x1e7b850; -LS_0x1ec19e0_0_4 .concat [ 4 0 0 0], o0x7f7259334268; -L_0x1ec19e0 .concat [ 4 4 0 0], LS_0x1ec19e0_0_0, LS_0x1ec19e0_0_4; -S_0x1d063d0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d06150; +L_0x1303cb0/d .functor NOT 1, L_0x1317160, C4<0>, C4<0>, C4<0>; +L_0x1303cb0 .delay 1 (10000,10000,10000) L_0x1303cb0/d; +L_0x130db40/d .functor NOT 1, L_0x130d810, C4<0>, C4<0>, C4<0>; +L_0x130db40 .delay 1 (10000,10000,10000) L_0x130db40/d; +L_0x130eb90/d .functor XOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; +L_0x130eb90 .delay 1 (30000,30000,30000) L_0x130eb90/d; +L_0x2b0ab3d06de8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06e30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x130f240/d .functor OR 1, L_0x2b0ab3d06de8, L_0x2b0ab3d06e30, C4<0>, C4<0>; +L_0x130f240 .delay 1 (30000,30000,30000) L_0x130f240/d; +L_0x130f440/d .functor AND 1, L_0x1317160, L_0x130d810, C4<1>, C4<1>; +L_0x130f440 .delay 1 (30000,30000,30000) L_0x130f440/d; +L_0x130f500/d .functor NAND 1, L_0x1317160, L_0x130d810, C4<1>, C4<1>; +L_0x130f500 .delay 1 (20000,20000,20000) L_0x130f500/d; +L_0x130f660/d .functor XOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; +L_0x130f660 .delay 1 (20000,20000,20000) L_0x130f660/d; +L_0x130fb10/d .functor OR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; +L_0x130fb10 .delay 1 (30000,30000,30000) L_0x130fb10/d; +L_0x1317060/d .functor NOT 1, L_0x13133a0, C4<0>, C4<0>, C4<0>; +L_0x1317060 .delay 1 (10000,10000,10000) L_0x1317060/d; +v0x11a74e0_0 .net "A", 0 0, L_0x1317160; 1 drivers +v0x11a75a0_0 .net "A_", 0 0, L_0x1303cb0; 1 drivers +v0x11a7660_0 .net "B", 0 0, L_0x130d810; 1 drivers +v0x11a7730_0 .net "B_", 0 0, L_0x130db40; 1 drivers +v0x11a77d0_0 .net *"_s12", 0 0, L_0x130f240; 1 drivers +v0x11a78c0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06de8; 1 drivers +v0x11a7980_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06e30; 1 drivers +v0x11a7a60_0 .net *"_s18", 0 0, L_0x130f440; 1 drivers +v0x11a7b40_0 .net *"_s20", 0 0, L_0x130f500; 1 drivers +v0x11a7cb0_0 .net *"_s22", 0 0, L_0x130f660; 1 drivers +v0x11a7d90_0 .net *"_s24", 0 0, L_0x130fb10; 1 drivers +o0x2b0ab3ce5238 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x11a7e70_0 name=_s30 +o0x2b0ab3ce5268 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x11a7f50_0 name=_s32 +v0x11a8030_0 .net *"_s8", 0 0, L_0x130eb90; 1 drivers +v0x11a8110_0 .net "carryin", 0 0, L_0x130d8b0; 1 drivers +v0x11a81b0_0 .net "carryout", 0 0, L_0x1316d00; 1 drivers +v0x11a8250_0 .net "carryouts", 7 0, L_0x1355d10; 1 drivers +v0x11a8400_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11a84a0_0 .net "result", 0 0, L_0x13133a0; 1 drivers +v0x11a8590_0 .net "results", 7 0, L_0x130f8e0; 1 drivers +v0x11a86a0_0 .net "zero", 0 0, L_0x1317060; 1 drivers +LS_0x130f8e0_0_0 .concat8 [ 1 1 1 1], L_0x130e060, L_0x130e690, L_0x130eb90, L_0x130f240; +LS_0x130f8e0_0_4 .concat8 [ 1 1 1 1], L_0x130f440, L_0x130f500, L_0x130f660, L_0x130fb10; +L_0x130f8e0 .concat8 [ 4 4 0 0], LS_0x130f8e0_0_0, LS_0x130f8e0_0_4; +LS_0x1355d10_0_0 .concat [ 1 1 1 1], L_0x130e310, L_0x130ea30, o0x2b0ab3ce5238, L_0x130f090; +LS_0x1355d10_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce5268; +L_0x1355d10 .concat [ 4 4 0 0], LS_0x1355d10_0_0, LS_0x1355d10_0_4; +S_0x1199030 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1198db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e7aad0/d .functor OR 1, L_0x1e7a5b0, L_0x1e7a970, C4<0>, C4<0>; -L_0x1e7aad0 .delay 1 (30000,30000,30000) L_0x1e7aad0/d; -v0x1d07200_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers -v0x1d072c0_0 .net "b", 0 0, L_0x1e79fd0; alias, 1 drivers -v0x1d07390_0 .net "c1", 0 0, L_0x1e7a5b0; 1 drivers -v0x1d07490_0 .net "c2", 0 0, L_0x1e7a970; 1 drivers -v0x1d07560_0 .net "carryin", 0 0, L_0x1e7a070; alias, 1 drivers -v0x1d07650_0 .net "carryout", 0 0, L_0x1e7aad0; 1 drivers -v0x1d076f0_0 .net "s1", 0 0, L_0x1e7a4f0; 1 drivers -v0x1d077e0_0 .net "sum", 0 0, L_0x1e7a820; 1 drivers -S_0x1d06640 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d063d0; +L_0x130e310/d .functor OR 1, L_0x130ddf0, L_0x130e1b0, C4<0>, C4<0>; +L_0x130e310 .delay 1 (30000,30000,30000) L_0x130e310/d; +v0x1199e60_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers +v0x1199f20_0 .net "b", 0 0, L_0x130d810; alias, 1 drivers +v0x1199ff0_0 .net "c1", 0 0, L_0x130ddf0; 1 drivers +v0x119a0f0_0 .net "c2", 0 0, L_0x130e1b0; 1 drivers +v0x119a1c0_0 .net "carryin", 0 0, L_0x130d8b0; alias, 1 drivers +v0x119a2b0_0 .net "carryout", 0 0, L_0x130e310; 1 drivers +v0x119a350_0 .net "s1", 0 0, L_0x130dd30; 1 drivers +v0x119a440_0 .net "sum", 0 0, L_0x130e060; 1 drivers +S_0x11992a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1199030; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e7a4f0/d .functor XOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; -L_0x1e7a4f0 .delay 1 (30000,30000,30000) L_0x1e7a4f0/d; -L_0x1e7a5b0/d .functor AND 1, L_0x1e83a40, L_0x1e79fd0, C4<1>, C4<1>; -L_0x1e7a5b0 .delay 1 (30000,30000,30000) L_0x1e7a5b0/d; -v0x1d068a0_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers -v0x1d06980_0 .net "b", 0 0, L_0x1e79fd0; alias, 1 drivers -v0x1d06a40_0 .net "carryout", 0 0, L_0x1e7a5b0; alias, 1 drivers -v0x1d06ae0_0 .net "sum", 0 0, L_0x1e7a4f0; alias, 1 drivers -S_0x1d06c20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d063d0; +L_0x130dd30/d .functor XOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; +L_0x130dd30 .delay 1 (30000,30000,30000) L_0x130dd30/d; +L_0x130ddf0/d .functor AND 1, L_0x1317160, L_0x130d810, C4<1>, C4<1>; +L_0x130ddf0 .delay 1 (30000,30000,30000) L_0x130ddf0/d; +v0x1199500_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers +v0x11995e0_0 .net "b", 0 0, L_0x130d810; alias, 1 drivers +v0x11996a0_0 .net "carryout", 0 0, L_0x130ddf0; alias, 1 drivers +v0x1199740_0 .net "sum", 0 0, L_0x130dd30; alias, 1 drivers +S_0x1199880 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1199030; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e7a820/d .functor XOR 1, L_0x1e7a4f0, L_0x1e7a070, C4<0>, C4<0>; -L_0x1e7a820 .delay 1 (30000,30000,30000) L_0x1e7a820/d; -L_0x1e7a970/d .functor AND 1, L_0x1e7a4f0, L_0x1e7a070, C4<1>, C4<1>; -L_0x1e7a970 .delay 1 (30000,30000,30000) L_0x1e7a970/d; -v0x1d06e80_0 .net "a", 0 0, L_0x1e7a4f0; alias, 1 drivers -v0x1d06f20_0 .net "b", 0 0, L_0x1e7a070; alias, 1 drivers -v0x1d06fc0_0 .net "carryout", 0 0, L_0x1e7a970; alias, 1 drivers -v0x1d07090_0 .net "sum", 0 0, L_0x1e7a820; alias, 1 drivers -S_0x1d078b0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d06150; +L_0x130e060/d .functor XOR 1, L_0x130dd30, L_0x130d8b0, C4<0>, C4<0>; +L_0x130e060 .delay 1 (30000,30000,30000) L_0x130e060/d; +L_0x130e1b0/d .functor AND 1, L_0x130dd30, L_0x130d8b0, C4<1>, C4<1>; +L_0x130e1b0 .delay 1 (30000,30000,30000) L_0x130e1b0/d; +v0x1199ae0_0 .net "a", 0 0, L_0x130dd30; alias, 1 drivers +v0x1199b80_0 .net "b", 0 0, L_0x130d8b0; alias, 1 drivers +v0x1199c20_0 .net "carryout", 0 0, L_0x130e1b0; alias, 1 drivers +v0x1199cf0_0 .net "sum", 0 0, L_0x130e060; alias, 1 drivers +S_0x119a510 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1198db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d0cca0_0 .net "ands", 7 0, L_0x1e815e0; 1 drivers -v0x1d0cdb0_0 .net "in", 7 0, L_0x1ec19e0; alias, 1 drivers -v0x1d0ce70_0 .net "out", 0 0, L_0x1e835e0; alias, 1 drivers -v0x1d0cf40_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d07ad0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d078b0; +v0x119f900_0 .net "ands", 7 0, L_0x1314de0; 1 drivers +v0x119fa10_0 .net "in", 7 0, L_0x1355d10; alias, 1 drivers +v0x119fad0_0 .net "out", 0 0, L_0x1316d00; alias, 1 drivers +v0x119fba0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x119a730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x119a510; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d0a200_0 .net "A", 7 0, L_0x1ec19e0; alias, 1 drivers -v0x1d0a300_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d0a3c0_0 .net *"_s0", 0 0, L_0x1e7ff00; 1 drivers -v0x1d0a480_0 .net *"_s12", 0 0, L_0x1e80870; 1 drivers -v0x1d0a560_0 .net *"_s16", 0 0, L_0x1e80bd0; 1 drivers -v0x1d0a690_0 .net *"_s20", 0 0, L_0x1e80ee0; 1 drivers -v0x1d0a770_0 .net *"_s24", 0 0, L_0x1e812d0; 1 drivers -v0x1d0a850_0 .net *"_s28", 0 0, L_0x1e81260; 1 drivers -v0x1d0a930_0 .net *"_s4", 0 0, L_0x1e80210; 1 drivers -v0x1d0aaa0_0 .net *"_s8", 0 0, L_0x1e80560; 1 drivers -v0x1d0ab80_0 .net "out", 7 0, L_0x1e815e0; alias, 1 drivers -L_0x1e7ffc0 .part L_0x1ec19e0, 0, 1; -L_0x1e80120 .part v0x1d6daa0_0, 0, 1; -L_0x1e802d0 .part L_0x1ec19e0, 1, 1; -L_0x1e804c0 .part v0x1d6daa0_0, 1, 1; -L_0x1e80620 .part L_0x1ec19e0, 2, 1; -L_0x1e80780 .part v0x1d6daa0_0, 2, 1; -L_0x1e80930 .part L_0x1ec19e0, 3, 1; -L_0x1e80a90 .part v0x1d6daa0_0, 3, 1; -L_0x1e80c90 .part L_0x1ec19e0, 4, 1; -L_0x1e80df0 .part v0x1d6daa0_0, 4, 1; -L_0x1e80f50 .part L_0x1ec19e0, 5, 1; -L_0x1e811c0 .part v0x1d6daa0_0, 5, 1; -L_0x1e81390 .part L_0x1ec19e0, 6, 1; -L_0x1e814f0 .part v0x1d6daa0_0, 6, 1; -LS_0x1e815e0_0_0 .concat8 [ 1 1 1 1], L_0x1e7ff00, L_0x1e80210, L_0x1e80560, L_0x1e80870; -LS_0x1e815e0_0_4 .concat8 [ 1 1 1 1], L_0x1e80bd0, L_0x1e80ee0, L_0x1e812d0, L_0x1e81260; -L_0x1e815e0 .concat8 [ 4 4 0 0], LS_0x1e815e0_0_0, LS_0x1e815e0_0_4; -L_0x1e819a0 .part L_0x1ec19e0, 7, 1; -L_0x1e81b90 .part v0x1d6daa0_0, 7, 1; -S_0x1d07d30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d07f40 .param/l "i" 0 4 54, +C4<00>; -L_0x1e7ff00/d .functor AND 1, L_0x1e7ffc0, L_0x1e80120, C4<1>, C4<1>; -L_0x1e7ff00 .delay 1 (30000,30000,30000) L_0x1e7ff00/d; -v0x1d08020_0 .net *"_s0", 0 0, L_0x1e7ffc0; 1 drivers -v0x1d08100_0 .net *"_s1", 0 0, L_0x1e80120; 1 drivers -S_0x1d081e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d083f0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e80210/d .functor AND 1, L_0x1e802d0, L_0x1e804c0, C4<1>, C4<1>; -L_0x1e80210 .delay 1 (30000,30000,30000) L_0x1e80210/d; -v0x1d084b0_0 .net *"_s0", 0 0, L_0x1e802d0; 1 drivers -v0x1d08590_0 .net *"_s1", 0 0, L_0x1e804c0; 1 drivers -S_0x1d08670 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d08880 .param/l "i" 0 4 54, +C4<010>; -L_0x1e80560/d .functor AND 1, L_0x1e80620, L_0x1e80780, C4<1>, C4<1>; -L_0x1e80560 .delay 1 (30000,30000,30000) L_0x1e80560/d; -v0x1d08920_0 .net *"_s0", 0 0, L_0x1e80620; 1 drivers -v0x1d08a00_0 .net *"_s1", 0 0, L_0x1e80780; 1 drivers -S_0x1d08ae0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d08cf0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e80870/d .functor AND 1, L_0x1e80930, L_0x1e80a90, C4<1>, C4<1>; -L_0x1e80870 .delay 1 (30000,30000,30000) L_0x1e80870/d; -v0x1d08db0_0 .net *"_s0", 0 0, L_0x1e80930; 1 drivers -v0x1d08e90_0 .net *"_s1", 0 0, L_0x1e80a90; 1 drivers -S_0x1d08f70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d091d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e80bd0/d .functor AND 1, L_0x1e80c90, L_0x1e80df0, C4<1>, C4<1>; -L_0x1e80bd0 .delay 1 (30000,30000,30000) L_0x1e80bd0/d; -v0x1d09290_0 .net *"_s0", 0 0, L_0x1e80c90; 1 drivers -v0x1d09370_0 .net *"_s1", 0 0, L_0x1e80df0; 1 drivers -S_0x1d09450 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d09660 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e80ee0/d .functor AND 1, L_0x1e80f50, L_0x1e811c0, C4<1>, C4<1>; -L_0x1e80ee0 .delay 1 (30000,30000,30000) L_0x1e80ee0/d; -v0x1d09720_0 .net *"_s0", 0 0, L_0x1e80f50; 1 drivers -v0x1d09800_0 .net *"_s1", 0 0, L_0x1e811c0; 1 drivers -S_0x1d098e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d09af0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e812d0/d .functor AND 1, L_0x1e81390, L_0x1e814f0, C4<1>, C4<1>; -L_0x1e812d0 .delay 1 (30000,30000,30000) L_0x1e812d0/d; -v0x1d09bb0_0 .net *"_s0", 0 0, L_0x1e81390; 1 drivers -v0x1d09c90_0 .net *"_s1", 0 0, L_0x1e814f0; 1 drivers -S_0x1d09d70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d07ad0; - .timescale -9 -12; -P_0x1d09f80 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e81260/d .functor AND 1, L_0x1e819a0, L_0x1e81b90, C4<1>, C4<1>; -L_0x1e81260 .delay 1 (30000,30000,30000) L_0x1e81260/d; -v0x1d0a040_0 .net *"_s0", 0 0, L_0x1e819a0; 1 drivers -v0x1d0a120_0 .net *"_s1", 0 0, L_0x1e81b90; 1 drivers -S_0x1d0ace0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d078b0; +v0x119ce60_0 .net "A", 7 0, L_0x1355d10; alias, 1 drivers +v0x119cf60_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x119d020_0 .net *"_s0", 0 0, L_0x1313700; 1 drivers +v0x119d0e0_0 .net *"_s12", 0 0, L_0x1314070; 1 drivers +v0x119d1c0_0 .net *"_s16", 0 0, L_0x13143d0; 1 drivers +v0x119d2f0_0 .net *"_s20", 0 0, L_0x13146e0; 1 drivers +v0x119d3d0_0 .net *"_s24", 0 0, L_0x1314ad0; 1 drivers +v0x119d4b0_0 .net *"_s28", 0 0, L_0x1314a60; 1 drivers +v0x119d590_0 .net *"_s4", 0 0, L_0x1313a10; 1 drivers +v0x119d700_0 .net *"_s8", 0 0, L_0x1313d60; 1 drivers +v0x119d7e0_0 .net "out", 7 0, L_0x1314de0; alias, 1 drivers +L_0x13137c0 .part L_0x1355d10, 0, 1; +L_0x1313920 .part v0x12010b0_0, 0, 1; +L_0x1313ad0 .part L_0x1355d10, 1, 1; +L_0x1313cc0 .part v0x12010b0_0, 1, 1; +L_0x1313e20 .part L_0x1355d10, 2, 1; +L_0x1313f80 .part v0x12010b0_0, 2, 1; +L_0x1314130 .part L_0x1355d10, 3, 1; +L_0x1314290 .part v0x12010b0_0, 3, 1; +L_0x1314490 .part L_0x1355d10, 4, 1; +L_0x13145f0 .part v0x12010b0_0, 4, 1; +L_0x1314750 .part L_0x1355d10, 5, 1; +L_0x13149c0 .part v0x12010b0_0, 5, 1; +L_0x1314b90 .part L_0x1355d10, 6, 1; +L_0x1314cf0 .part v0x12010b0_0, 6, 1; +LS_0x1314de0_0_0 .concat8 [ 1 1 1 1], L_0x1313700, L_0x1313a10, L_0x1313d60, L_0x1314070; +LS_0x1314de0_0_4 .concat8 [ 1 1 1 1], L_0x13143d0, L_0x13146e0, L_0x1314ad0, L_0x1314a60; +L_0x1314de0 .concat8 [ 4 4 0 0], LS_0x1314de0_0_0, LS_0x1314de0_0_4; +L_0x13151a0 .part L_0x1355d10, 7, 1; +L_0x1315390 .part v0x12010b0_0, 7, 1; +S_0x119a990 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119aba0 .param/l "i" 0 4 54, +C4<00>; +L_0x1313700/d .functor AND 1, L_0x13137c0, L_0x1313920, C4<1>, C4<1>; +L_0x1313700 .delay 1 (30000,30000,30000) L_0x1313700/d; +v0x119ac80_0 .net *"_s0", 0 0, L_0x13137c0; 1 drivers +v0x119ad60_0 .net *"_s1", 0 0, L_0x1313920; 1 drivers +S_0x119ae40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119b050 .param/l "i" 0 4 54, +C4<01>; +L_0x1313a10/d .functor AND 1, L_0x1313ad0, L_0x1313cc0, C4<1>, C4<1>; +L_0x1313a10 .delay 1 (30000,30000,30000) L_0x1313a10/d; +v0x119b110_0 .net *"_s0", 0 0, L_0x1313ad0; 1 drivers +v0x119b1f0_0 .net *"_s1", 0 0, L_0x1313cc0; 1 drivers +S_0x119b2d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119b4e0 .param/l "i" 0 4 54, +C4<010>; +L_0x1313d60/d .functor AND 1, L_0x1313e20, L_0x1313f80, C4<1>, C4<1>; +L_0x1313d60 .delay 1 (30000,30000,30000) L_0x1313d60/d; +v0x119b580_0 .net *"_s0", 0 0, L_0x1313e20; 1 drivers +v0x119b660_0 .net *"_s1", 0 0, L_0x1313f80; 1 drivers +S_0x119b740 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119b950 .param/l "i" 0 4 54, +C4<011>; +L_0x1314070/d .functor AND 1, L_0x1314130, L_0x1314290, C4<1>, C4<1>; +L_0x1314070 .delay 1 (30000,30000,30000) L_0x1314070/d; +v0x119ba10_0 .net *"_s0", 0 0, L_0x1314130; 1 drivers +v0x119baf0_0 .net *"_s1", 0 0, L_0x1314290; 1 drivers +S_0x119bbd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119be30 .param/l "i" 0 4 54, +C4<0100>; +L_0x13143d0/d .functor AND 1, L_0x1314490, L_0x13145f0, C4<1>, C4<1>; +L_0x13143d0 .delay 1 (30000,30000,30000) L_0x13143d0/d; +v0x119bef0_0 .net *"_s0", 0 0, L_0x1314490; 1 drivers +v0x119bfd0_0 .net *"_s1", 0 0, L_0x13145f0; 1 drivers +S_0x119c0b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119c2c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13146e0/d .functor AND 1, L_0x1314750, L_0x13149c0, C4<1>, C4<1>; +L_0x13146e0 .delay 1 (30000,30000,30000) L_0x13146e0/d; +v0x119c380_0 .net *"_s0", 0 0, L_0x1314750; 1 drivers +v0x119c460_0 .net *"_s1", 0 0, L_0x13149c0; 1 drivers +S_0x119c540 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119c750 .param/l "i" 0 4 54, +C4<0110>; +L_0x1314ad0/d .functor AND 1, L_0x1314b90, L_0x1314cf0, C4<1>, C4<1>; +L_0x1314ad0 .delay 1 (30000,30000,30000) L_0x1314ad0/d; +v0x119c810_0 .net *"_s0", 0 0, L_0x1314b90; 1 drivers +v0x119c8f0_0 .net *"_s1", 0 0, L_0x1314cf0; 1 drivers +S_0x119c9d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x119a730; + .timescale -9 -12; +P_0x119cbe0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1314a60/d .functor AND 1, L_0x13151a0, L_0x1315390, C4<1>, C4<1>; +L_0x1314a60 .delay 1 (30000,30000,30000) L_0x1314a60/d; +v0x119cca0_0 .net *"_s0", 0 0, L_0x13151a0; 1 drivers +v0x119cd80_0 .net *"_s1", 0 0, L_0x1315390; 1 drivers +S_0x119d940 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x119a510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e835e0/d .functor OR 1, L_0x1e836a0, L_0x1e83850, C4<0>, C4<0>; -L_0x1e835e0 .delay 1 (30000,30000,30000) L_0x1e835e0/d; -v0x1d0c830_0 .net *"_s10", 0 0, L_0x1e836a0; 1 drivers -v0x1d0c910_0 .net *"_s12", 0 0, L_0x1e83850; 1 drivers -v0x1d0c9f0_0 .net "in", 7 0, L_0x1e815e0; alias, 1 drivers -v0x1d0cac0_0 .net "ors", 1 0, L_0x1e83400; 1 drivers -v0x1d0cb80_0 .net "out", 0 0, L_0x1e835e0; alias, 1 drivers -L_0x1e827d0 .part L_0x1e815e0, 0, 4; -L_0x1e83400 .concat8 [ 1 1 0 0], L_0x1e824c0, L_0x1e830f0; -L_0x1e83540 .part L_0x1e815e0, 4, 4; -L_0x1e836a0 .part L_0x1e83400, 0, 1; -L_0x1e83850 .part L_0x1e83400, 1, 1; -S_0x1d0aea0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d0ace0; +L_0x1316d00/d .functor OR 1, L_0x1316dc0, L_0x1316f70, C4<0>, C4<0>; +L_0x1316d00 .delay 1 (30000,30000,30000) L_0x1316d00/d; +v0x119f490_0 .net *"_s10", 0 0, L_0x1316dc0; 1 drivers +v0x119f570_0 .net *"_s12", 0 0, L_0x1316f70; 1 drivers +v0x119f650_0 .net "in", 7 0, L_0x1314de0; alias, 1 drivers +v0x119f720_0 .net "ors", 1 0, L_0x1316b20; 1 drivers +v0x119f7e0_0 .net "out", 0 0, L_0x1316d00; alias, 1 drivers +L_0x1315fd0 .part L_0x1314de0, 0, 4; +L_0x1316b20 .concat8 [ 1 1 0 0], L_0x1315cc0, L_0x1316810; +L_0x1316c60 .part L_0x1314de0, 4, 4; +L_0x1316dc0 .part L_0x1316b20, 0, 1; +L_0x1316f70 .part L_0x1316b20, 1, 1; +S_0x119db00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x119d940; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e81c80/d .functor OR 1, L_0x1e81d40, L_0x1e81ea0, C4<0>, C4<0>; -L_0x1e81c80 .delay 1 (30000,30000,30000) L_0x1e81c80/d; -L_0x1e820d0/d .functor OR 1, L_0x1e821e0, L_0x1e82340, C4<0>, C4<0>; -L_0x1e820d0 .delay 1 (30000,30000,30000) L_0x1e820d0/d; -L_0x1e824c0/d .functor OR 1, L_0x1e82530, L_0x1e826e0, C4<0>, C4<0>; -L_0x1e824c0 .delay 1 (30000,30000,30000) L_0x1e824c0/d; -v0x1d0b0f0_0 .net *"_s0", 0 0, L_0x1e81c80; 1 drivers -v0x1d0b1f0_0 .net *"_s10", 0 0, L_0x1e821e0; 1 drivers -v0x1d0b2d0_0 .net *"_s12", 0 0, L_0x1e82340; 1 drivers -v0x1d0b390_0 .net *"_s14", 0 0, L_0x1e82530; 1 drivers -v0x1d0b470_0 .net *"_s16", 0 0, L_0x1e826e0; 1 drivers -v0x1d0b5a0_0 .net *"_s3", 0 0, L_0x1e81d40; 1 drivers -v0x1d0b680_0 .net *"_s5", 0 0, L_0x1e81ea0; 1 drivers -v0x1d0b760_0 .net *"_s6", 0 0, L_0x1e820d0; 1 drivers -v0x1d0b840_0 .net "in", 3 0, L_0x1e827d0; 1 drivers -v0x1d0b9b0_0 .net "ors", 1 0, L_0x1e81fe0; 1 drivers -v0x1d0ba90_0 .net "out", 0 0, L_0x1e824c0; 1 drivers -L_0x1e81d40 .part L_0x1e827d0, 0, 1; -L_0x1e81ea0 .part L_0x1e827d0, 1, 1; -L_0x1e81fe0 .concat8 [ 1 1 0 0], L_0x1e81c80, L_0x1e820d0; -L_0x1e821e0 .part L_0x1e827d0, 2, 1; -L_0x1e82340 .part L_0x1e827d0, 3, 1; -L_0x1e82530 .part L_0x1e81fe0, 0, 1; -L_0x1e826e0 .part L_0x1e81fe0, 1, 1; -S_0x1d0bbb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d0ace0; +L_0x1315480/d .functor OR 1, L_0x1315540, L_0x13156a0, C4<0>, C4<0>; +L_0x1315480 .delay 1 (30000,30000,30000) L_0x1315480/d; +L_0x13158d0/d .functor OR 1, L_0x13159e0, L_0x1315b40, C4<0>, C4<0>; +L_0x13158d0 .delay 1 (30000,30000,30000) L_0x13158d0/d; +L_0x1315cc0/d .functor OR 1, L_0x1315d30, L_0x1315ee0, C4<0>, C4<0>; +L_0x1315cc0 .delay 1 (30000,30000,30000) L_0x1315cc0/d; +v0x119dd50_0 .net *"_s0", 0 0, L_0x1315480; 1 drivers +v0x119de50_0 .net *"_s10", 0 0, L_0x13159e0; 1 drivers +v0x119df30_0 .net *"_s12", 0 0, L_0x1315b40; 1 drivers +v0x119dff0_0 .net *"_s14", 0 0, L_0x1315d30; 1 drivers +v0x119e0d0_0 .net *"_s16", 0 0, L_0x1315ee0; 1 drivers +v0x119e200_0 .net *"_s3", 0 0, L_0x1315540; 1 drivers +v0x119e2e0_0 .net *"_s5", 0 0, L_0x13156a0; 1 drivers +v0x119e3c0_0 .net *"_s6", 0 0, L_0x13158d0; 1 drivers +v0x119e4a0_0 .net "in", 3 0, L_0x1315fd0; 1 drivers +v0x119e610_0 .net "ors", 1 0, L_0x13157e0; 1 drivers +v0x119e6f0_0 .net "out", 0 0, L_0x1315cc0; 1 drivers +L_0x1315540 .part L_0x1315fd0, 0, 1; +L_0x13156a0 .part L_0x1315fd0, 1, 1; +L_0x13157e0 .concat8 [ 1 1 0 0], L_0x1315480, L_0x13158d0; +L_0x13159e0 .part L_0x1315fd0, 2, 1; +L_0x1315b40 .part L_0x1315fd0, 3, 1; +L_0x1315d30 .part L_0x13157e0, 0, 1; +L_0x1315ee0 .part L_0x13157e0, 1, 1; +S_0x119e810 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x119d940; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e82900/d .functor OR 1, L_0x1e82970, L_0x1e82ad0, C4<0>, C4<0>; -L_0x1e82900 .delay 1 (30000,30000,30000) L_0x1e82900/d; -L_0x1e82d00/d .functor OR 1, L_0x1e82e10, L_0x1e82f70, C4<0>, C4<0>; -L_0x1e82d00 .delay 1 (30000,30000,30000) L_0x1e82d00/d; -L_0x1e830f0/d .functor OR 1, L_0x1e83160, L_0x1e83310, C4<0>, C4<0>; -L_0x1e830f0 .delay 1 (30000,30000,30000) L_0x1e830f0/d; -v0x1d0bd70_0 .net *"_s0", 0 0, L_0x1e82900; 1 drivers -v0x1d0be70_0 .net *"_s10", 0 0, L_0x1e82e10; 1 drivers -v0x1d0bf50_0 .net *"_s12", 0 0, L_0x1e82f70; 1 drivers -v0x1d0c010_0 .net *"_s14", 0 0, L_0x1e83160; 1 drivers -v0x1d0c0f0_0 .net *"_s16", 0 0, L_0x1e83310; 1 drivers -v0x1d0c220_0 .net *"_s3", 0 0, L_0x1e82970; 1 drivers -v0x1d0c300_0 .net *"_s5", 0 0, L_0x1e82ad0; 1 drivers -v0x1d0c3e0_0 .net *"_s6", 0 0, L_0x1e82d00; 1 drivers -v0x1d0c4c0_0 .net "in", 3 0, L_0x1e83540; 1 drivers -v0x1d0c630_0 .net "ors", 1 0, L_0x1e82c10; 1 drivers -v0x1d0c710_0 .net "out", 0 0, L_0x1e830f0; 1 drivers -L_0x1e82970 .part L_0x1e83540, 0, 1; -L_0x1e82ad0 .part L_0x1e83540, 1, 1; -L_0x1e82c10 .concat8 [ 1 1 0 0], L_0x1e82900, L_0x1e82d00; -L_0x1e82e10 .part L_0x1e83540, 2, 1; -L_0x1e82f70 .part L_0x1e83540, 3, 1; -L_0x1e83160 .part L_0x1e82c10, 0, 1; -L_0x1e83310 .part L_0x1e82c10, 1, 1; -S_0x1d0d020 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d06150; +L_0x1307660/d .functor OR 1, L_0x1316100, L_0x13161f0, C4<0>, C4<0>; +L_0x1307660 .delay 1 (30000,30000,30000) L_0x1307660/d; +L_0x1316420/d .functor OR 1, L_0x1316530, L_0x1316690, C4<0>, C4<0>; +L_0x1316420 .delay 1 (30000,30000,30000) L_0x1316420/d; +L_0x1316810/d .functor OR 1, L_0x1316880, L_0x1316a30, C4<0>, C4<0>; +L_0x1316810 .delay 1 (30000,30000,30000) L_0x1316810/d; +v0x119e9d0_0 .net *"_s0", 0 0, L_0x1307660; 1 drivers +v0x119ead0_0 .net *"_s10", 0 0, L_0x1316530; 1 drivers +v0x119ebb0_0 .net *"_s12", 0 0, L_0x1316690; 1 drivers +v0x119ec70_0 .net *"_s14", 0 0, L_0x1316880; 1 drivers +v0x119ed50_0 .net *"_s16", 0 0, L_0x1316a30; 1 drivers +v0x119ee80_0 .net *"_s3", 0 0, L_0x1316100; 1 drivers +v0x119ef60_0 .net *"_s5", 0 0, L_0x13161f0; 1 drivers +v0x119f040_0 .net *"_s6", 0 0, L_0x1316420; 1 drivers +v0x119f120_0 .net "in", 3 0, L_0x1316c60; 1 drivers +v0x119f290_0 .net "ors", 1 0, L_0x1316330; 1 drivers +v0x119f370_0 .net "out", 0 0, L_0x1316810; 1 drivers +L_0x1316100 .part L_0x1316c60, 0, 1; +L_0x13161f0 .part L_0x1316c60, 1, 1; +L_0x1316330 .concat8 [ 1 1 0 0], L_0x1307660, L_0x1316420; +L_0x1316530 .part L_0x1316c60, 2, 1; +L_0x1316690 .part L_0x1316c60, 3, 1; +L_0x1316880 .part L_0x1316330, 0, 1; +L_0x1316a30 .part L_0x1316330, 1, 1; +S_0x119fc80 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1198db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d12450_0 .net "ands", 7 0, L_0x1e7dba0; 1 drivers -v0x1d12560_0 .net "in", 7 0, L_0x1e7a710; alias, 1 drivers -v0x1d12620_0 .net "out", 0 0, L_0x1e7fba0; alias, 1 drivers -v0x1d126f0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d0d270 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d0d020; +v0x11a50b0_0 .net "ands", 7 0, L_0x13113a0; 1 drivers +v0x11a51c0_0 .net "in", 7 0, L_0x130f8e0; alias, 1 drivers +v0x11a5280_0 .net "out", 0 0, L_0x13133a0; alias, 1 drivers +v0x11a5350_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x119fed0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x119fc80; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d0f9b0_0 .net "A", 7 0, L_0x1e7a710; alias, 1 drivers -v0x1d0fab0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d0fb70_0 .net *"_s0", 0 0, L_0x1e7c390; 1 drivers -v0x1d0fc30_0 .net *"_s12", 0 0, L_0x1e7cd50; 1 drivers -v0x1d0fd10_0 .net *"_s16", 0 0, L_0x1e7d0b0; 1 drivers -v0x1d0fe40_0 .net *"_s20", 0 0, L_0x1e7d4e0; 1 drivers -v0x1d0ff20_0 .net *"_s24", 0 0, L_0x1e7d810; 1 drivers -v0x1d10000_0 .net *"_s28", 0 0, L_0x1e7d7a0; 1 drivers -v0x1d100e0_0 .net *"_s4", 0 0, L_0x1e7c730; 1 drivers -v0x1d10250_0 .net *"_s8", 0 0, L_0x1e7ca40; 1 drivers -v0x1d10330_0 .net "out", 7 0, L_0x1e7dba0; alias, 1 drivers -L_0x1e7c4a0 .part L_0x1e7a710, 0, 1; -L_0x1e7c690 .part v0x1d6daa0_0, 0, 1; -L_0x1e7c7f0 .part L_0x1e7a710, 1, 1; -L_0x1e7c950 .part v0x1d6daa0_0, 1, 1; -L_0x1e7cb00 .part L_0x1e7a710, 2, 1; -L_0x1e7cc60 .part v0x1d6daa0_0, 2, 1; -L_0x1e7ce10 .part L_0x1e7a710, 3, 1; -L_0x1e7cf70 .part v0x1d6daa0_0, 3, 1; -L_0x1e7d170 .part L_0x1e7a710, 4, 1; -L_0x1e7d3e0 .part v0x1d6daa0_0, 4, 1; -L_0x1e7d550 .part L_0x1e7a710, 5, 1; -L_0x1e7d6b0 .part v0x1d6daa0_0, 5, 1; -L_0x1e7d8d0 .part L_0x1e7a710, 6, 1; -L_0x1e7da30 .part v0x1d6daa0_0, 6, 1; -LS_0x1e7dba0_0_0 .concat8 [ 1 1 1 1], L_0x1e7c390, L_0x1e7c730, L_0x1e7ca40, L_0x1e7cd50; -LS_0x1e7dba0_0_4 .concat8 [ 1 1 1 1], L_0x1e7d0b0, L_0x1e7d4e0, L_0x1e7d810, L_0x1e7d7a0; -L_0x1e7dba0 .concat8 [ 4 4 0 0], LS_0x1e7dba0_0_0, LS_0x1e7dba0_0_4; -L_0x1e7df60 .part L_0x1e7a710, 7, 1; -L_0x1e7e150 .part v0x1d6daa0_0, 7, 1; -S_0x1d0d4b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0d6c0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e7c390/d .functor AND 1, L_0x1e7c4a0, L_0x1e7c690, C4<1>, C4<1>; -L_0x1e7c390 .delay 1 (30000,30000,30000) L_0x1e7c390/d; -v0x1d0d7a0_0 .net *"_s0", 0 0, L_0x1e7c4a0; 1 drivers -v0x1d0d880_0 .net *"_s1", 0 0, L_0x1e7c690; 1 drivers -S_0x1d0d960 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0db70 .param/l "i" 0 4 54, +C4<01>; -L_0x1e7c730/d .functor AND 1, L_0x1e7c7f0, L_0x1e7c950, C4<1>, C4<1>; -L_0x1e7c730 .delay 1 (30000,30000,30000) L_0x1e7c730/d; -v0x1d0dc30_0 .net *"_s0", 0 0, L_0x1e7c7f0; 1 drivers -v0x1d0dd10_0 .net *"_s1", 0 0, L_0x1e7c950; 1 drivers -S_0x1d0ddf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0e030 .param/l "i" 0 4 54, +C4<010>; -L_0x1e7ca40/d .functor AND 1, L_0x1e7cb00, L_0x1e7cc60, C4<1>, C4<1>; -L_0x1e7ca40 .delay 1 (30000,30000,30000) L_0x1e7ca40/d; -v0x1d0e0d0_0 .net *"_s0", 0 0, L_0x1e7cb00; 1 drivers -v0x1d0e1b0_0 .net *"_s1", 0 0, L_0x1e7cc60; 1 drivers -S_0x1d0e290 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0e4a0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e7cd50/d .functor AND 1, L_0x1e7ce10, L_0x1e7cf70, C4<1>, C4<1>; -L_0x1e7cd50 .delay 1 (30000,30000,30000) L_0x1e7cd50/d; -v0x1d0e560_0 .net *"_s0", 0 0, L_0x1e7ce10; 1 drivers -v0x1d0e640_0 .net *"_s1", 0 0, L_0x1e7cf70; 1 drivers -S_0x1d0e720 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0e980 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e7d0b0/d .functor AND 1, L_0x1e7d170, L_0x1e7d3e0, C4<1>, C4<1>; -L_0x1e7d0b0 .delay 1 (30000,30000,30000) L_0x1e7d0b0/d; -v0x1d0ea40_0 .net *"_s0", 0 0, L_0x1e7d170; 1 drivers -v0x1d0eb20_0 .net *"_s1", 0 0, L_0x1e7d3e0; 1 drivers -S_0x1d0ec00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0ee10 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e7d4e0/d .functor AND 1, L_0x1e7d550, L_0x1e7d6b0, C4<1>, C4<1>; -L_0x1e7d4e0 .delay 1 (30000,30000,30000) L_0x1e7d4e0/d; -v0x1d0eed0_0 .net *"_s0", 0 0, L_0x1e7d550; 1 drivers -v0x1d0efb0_0 .net *"_s1", 0 0, L_0x1e7d6b0; 1 drivers -S_0x1d0f090 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0f2a0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e7d810/d .functor AND 1, L_0x1e7d8d0, L_0x1e7da30, C4<1>, C4<1>; -L_0x1e7d810 .delay 1 (30000,30000,30000) L_0x1e7d810/d; -v0x1d0f360_0 .net *"_s0", 0 0, L_0x1e7d8d0; 1 drivers -v0x1d0f440_0 .net *"_s1", 0 0, L_0x1e7da30; 1 drivers -S_0x1d0f520 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d0d270; - .timescale -9 -12; -P_0x1d0f730 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e7d7a0/d .functor AND 1, L_0x1e7df60, L_0x1e7e150, C4<1>, C4<1>; -L_0x1e7d7a0 .delay 1 (30000,30000,30000) L_0x1e7d7a0/d; -v0x1d0f7f0_0 .net *"_s0", 0 0, L_0x1e7df60; 1 drivers -v0x1d0f8d0_0 .net *"_s1", 0 0, L_0x1e7e150; 1 drivers -S_0x1d10490 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d0d020; +v0x11a2610_0 .net "A", 7 0, L_0x130f8e0; alias, 1 drivers +v0x11a2710_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11a27d0_0 .net *"_s0", 0 0, L_0x130fc70; 1 drivers +v0x11a2890_0 .net *"_s12", 0 0, L_0x1310630; 1 drivers +v0x11a2970_0 .net *"_s16", 0 0, L_0x1310990; 1 drivers +v0x11a2aa0_0 .net *"_s20", 0 0, L_0x1310d60; 1 drivers +v0x11a2b80_0 .net *"_s24", 0 0, L_0x1311090; 1 drivers +v0x11a2c60_0 .net *"_s28", 0 0, L_0x1311020; 1 drivers +v0x11a2d40_0 .net *"_s4", 0 0, L_0x1310010; 1 drivers +v0x11a2eb0_0 .net *"_s8", 0 0, L_0x1310320; 1 drivers +v0x11a2f90_0 .net "out", 7 0, L_0x13113a0; alias, 1 drivers +L_0x130fd80 .part L_0x130f8e0, 0, 1; +L_0x130ff70 .part v0x12010b0_0, 0, 1; +L_0x13100d0 .part L_0x130f8e0, 1, 1; +L_0x1310230 .part v0x12010b0_0, 1, 1; +L_0x13103e0 .part L_0x130f8e0, 2, 1; +L_0x1310540 .part v0x12010b0_0, 2, 1; +L_0x13106f0 .part L_0x130f8e0, 3, 1; +L_0x1310850 .part v0x12010b0_0, 3, 1; +L_0x1310a50 .part L_0x130f8e0, 4, 1; +L_0x1310cc0 .part v0x12010b0_0, 4, 1; +L_0x1310dd0 .part L_0x130f8e0, 5, 1; +L_0x1310f30 .part v0x12010b0_0, 5, 1; +L_0x1311150 .part L_0x130f8e0, 6, 1; +L_0x13112b0 .part v0x12010b0_0, 6, 1; +LS_0x13113a0_0_0 .concat8 [ 1 1 1 1], L_0x130fc70, L_0x1310010, L_0x1310320, L_0x1310630; +LS_0x13113a0_0_4 .concat8 [ 1 1 1 1], L_0x1310990, L_0x1310d60, L_0x1311090, L_0x1311020; +L_0x13113a0 .concat8 [ 4 4 0 0], LS_0x13113a0_0_0, LS_0x13113a0_0_4; +L_0x1311760 .part L_0x130f8e0, 7, 1; +L_0x1311950 .part v0x12010b0_0, 7, 1; +S_0x11a0110 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a0320 .param/l "i" 0 4 54, +C4<00>; +L_0x130fc70/d .functor AND 1, L_0x130fd80, L_0x130ff70, C4<1>, C4<1>; +L_0x130fc70 .delay 1 (30000,30000,30000) L_0x130fc70/d; +v0x11a0400_0 .net *"_s0", 0 0, L_0x130fd80; 1 drivers +v0x11a04e0_0 .net *"_s1", 0 0, L_0x130ff70; 1 drivers +S_0x11a05c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a07d0 .param/l "i" 0 4 54, +C4<01>; +L_0x1310010/d .functor AND 1, L_0x13100d0, L_0x1310230, C4<1>, C4<1>; +L_0x1310010 .delay 1 (30000,30000,30000) L_0x1310010/d; +v0x11a0890_0 .net *"_s0", 0 0, L_0x13100d0; 1 drivers +v0x11a0970_0 .net *"_s1", 0 0, L_0x1310230; 1 drivers +S_0x11a0a50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a0c90 .param/l "i" 0 4 54, +C4<010>; +L_0x1310320/d .functor AND 1, L_0x13103e0, L_0x1310540, C4<1>, C4<1>; +L_0x1310320 .delay 1 (30000,30000,30000) L_0x1310320/d; +v0x11a0d30_0 .net *"_s0", 0 0, L_0x13103e0; 1 drivers +v0x11a0e10_0 .net *"_s1", 0 0, L_0x1310540; 1 drivers +S_0x11a0ef0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a1100 .param/l "i" 0 4 54, +C4<011>; +L_0x1310630/d .functor AND 1, L_0x13106f0, L_0x1310850, C4<1>, C4<1>; +L_0x1310630 .delay 1 (30000,30000,30000) L_0x1310630/d; +v0x11a11c0_0 .net *"_s0", 0 0, L_0x13106f0; 1 drivers +v0x11a12a0_0 .net *"_s1", 0 0, L_0x1310850; 1 drivers +S_0x11a1380 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a15e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x1310990/d .functor AND 1, L_0x1310a50, L_0x1310cc0, C4<1>, C4<1>; +L_0x1310990 .delay 1 (30000,30000,30000) L_0x1310990/d; +v0x11a16a0_0 .net *"_s0", 0 0, L_0x1310a50; 1 drivers +v0x11a1780_0 .net *"_s1", 0 0, L_0x1310cc0; 1 drivers +S_0x11a1860 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a1a70 .param/l "i" 0 4 54, +C4<0101>; +L_0x1310d60/d .functor AND 1, L_0x1310dd0, L_0x1310f30, C4<1>, C4<1>; +L_0x1310d60 .delay 1 (30000,30000,30000) L_0x1310d60/d; +v0x11a1b30_0 .net *"_s0", 0 0, L_0x1310dd0; 1 drivers +v0x11a1c10_0 .net *"_s1", 0 0, L_0x1310f30; 1 drivers +S_0x11a1cf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a1f00 .param/l "i" 0 4 54, +C4<0110>; +L_0x1311090/d .functor AND 1, L_0x1311150, L_0x13112b0, C4<1>, C4<1>; +L_0x1311090 .delay 1 (30000,30000,30000) L_0x1311090/d; +v0x11a1fc0_0 .net *"_s0", 0 0, L_0x1311150; 1 drivers +v0x11a20a0_0 .net *"_s1", 0 0, L_0x13112b0; 1 drivers +S_0x11a2180 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x119fed0; + .timescale -9 -12; +P_0x11a2390 .param/l "i" 0 4 54, +C4<0111>; +L_0x1311020/d .functor AND 1, L_0x1311760, L_0x1311950, C4<1>, C4<1>; +L_0x1311020 .delay 1 (30000,30000,30000) L_0x1311020/d; +v0x11a2450_0 .net *"_s0", 0 0, L_0x1311760; 1 drivers +v0x11a2530_0 .net *"_s1", 0 0, L_0x1311950; 1 drivers +S_0x11a30f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x119fc80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e7fba0/d .functor OR 1, L_0x1e7fc60, L_0x1e7fe10, C4<0>, C4<0>; -L_0x1e7fba0 .delay 1 (30000,30000,30000) L_0x1e7fba0/d; -v0x1d11fe0_0 .net *"_s10", 0 0, L_0x1e7fc60; 1 drivers -v0x1d120c0_0 .net *"_s12", 0 0, L_0x1e7fe10; 1 drivers -v0x1d121a0_0 .net "in", 7 0, L_0x1e7dba0; alias, 1 drivers -v0x1d12270_0 .net "ors", 1 0, L_0x1e7f9c0; 1 drivers -v0x1d12330_0 .net "out", 0 0, L_0x1e7fba0; alias, 1 drivers -L_0x1e7ed90 .part L_0x1e7dba0, 0, 4; -L_0x1e7f9c0 .concat8 [ 1 1 0 0], L_0x1e7ea80, L_0x1e7f6b0; -L_0x1e7fb00 .part L_0x1e7dba0, 4, 4; -L_0x1e7fc60 .part L_0x1e7f9c0, 0, 1; -L_0x1e7fe10 .part L_0x1e7f9c0, 1, 1; -S_0x1d10650 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d10490; +L_0x13133a0/d .functor OR 1, L_0x1313460, L_0x1313610, C4<0>, C4<0>; +L_0x13133a0 .delay 1 (30000,30000,30000) L_0x13133a0/d; +v0x11a4c40_0 .net *"_s10", 0 0, L_0x1313460; 1 drivers +v0x11a4d20_0 .net *"_s12", 0 0, L_0x1313610; 1 drivers +v0x11a4e00_0 .net "in", 7 0, L_0x13113a0; alias, 1 drivers +v0x11a4ed0_0 .net "ors", 1 0, L_0x13131c0; 1 drivers +v0x11a4f90_0 .net "out", 0 0, L_0x13133a0; alias, 1 drivers +L_0x1312590 .part L_0x13113a0, 0, 4; +L_0x13131c0 .concat8 [ 1 1 0 0], L_0x1312280, L_0x1312eb0; +L_0x1313300 .part L_0x13113a0, 4, 4; +L_0x1313460 .part L_0x13131c0, 0, 1; +L_0x1313610 .part L_0x13131c0, 1, 1; +S_0x11a32b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11a30f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e7e240/d .functor OR 1, L_0x1e7e300, L_0x1e7e460, C4<0>, C4<0>; -L_0x1e7e240 .delay 1 (30000,30000,30000) L_0x1e7e240/d; -L_0x1e7e690/d .functor OR 1, L_0x1e7e7a0, L_0x1e7e900, C4<0>, C4<0>; -L_0x1e7e690 .delay 1 (30000,30000,30000) L_0x1e7e690/d; -L_0x1e7ea80/d .functor OR 1, L_0x1e7eaf0, L_0x1e7eca0, C4<0>, C4<0>; -L_0x1e7ea80 .delay 1 (30000,30000,30000) L_0x1e7ea80/d; -v0x1d108a0_0 .net *"_s0", 0 0, L_0x1e7e240; 1 drivers -v0x1d109a0_0 .net *"_s10", 0 0, L_0x1e7e7a0; 1 drivers -v0x1d10a80_0 .net *"_s12", 0 0, L_0x1e7e900; 1 drivers -v0x1d10b40_0 .net *"_s14", 0 0, L_0x1e7eaf0; 1 drivers -v0x1d10c20_0 .net *"_s16", 0 0, L_0x1e7eca0; 1 drivers -v0x1d10d50_0 .net *"_s3", 0 0, L_0x1e7e300; 1 drivers -v0x1d10e30_0 .net *"_s5", 0 0, L_0x1e7e460; 1 drivers -v0x1d10f10_0 .net *"_s6", 0 0, L_0x1e7e690; 1 drivers -v0x1d10ff0_0 .net "in", 3 0, L_0x1e7ed90; 1 drivers -v0x1d11160_0 .net "ors", 1 0, L_0x1e7e5a0; 1 drivers -v0x1d11240_0 .net "out", 0 0, L_0x1e7ea80; 1 drivers -L_0x1e7e300 .part L_0x1e7ed90, 0, 1; -L_0x1e7e460 .part L_0x1e7ed90, 1, 1; -L_0x1e7e5a0 .concat8 [ 1 1 0 0], L_0x1e7e240, L_0x1e7e690; -L_0x1e7e7a0 .part L_0x1e7ed90, 2, 1; -L_0x1e7e900 .part L_0x1e7ed90, 3, 1; -L_0x1e7eaf0 .part L_0x1e7e5a0, 0, 1; -L_0x1e7eca0 .part L_0x1e7e5a0, 1, 1; -S_0x1d11360 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d10490; +L_0x1311a40/d .functor OR 1, L_0x1311b00, L_0x1311c60, C4<0>, C4<0>; +L_0x1311a40 .delay 1 (30000,30000,30000) L_0x1311a40/d; +L_0x1311e90/d .functor OR 1, L_0x1311fa0, L_0x1312100, C4<0>, C4<0>; +L_0x1311e90 .delay 1 (30000,30000,30000) L_0x1311e90/d; +L_0x1312280/d .functor OR 1, L_0x13122f0, L_0x13124a0, C4<0>, C4<0>; +L_0x1312280 .delay 1 (30000,30000,30000) L_0x1312280/d; +v0x11a3500_0 .net *"_s0", 0 0, L_0x1311a40; 1 drivers +v0x11a3600_0 .net *"_s10", 0 0, L_0x1311fa0; 1 drivers +v0x11a36e0_0 .net *"_s12", 0 0, L_0x1312100; 1 drivers +v0x11a37a0_0 .net *"_s14", 0 0, L_0x13122f0; 1 drivers +v0x11a3880_0 .net *"_s16", 0 0, L_0x13124a0; 1 drivers +v0x11a39b0_0 .net *"_s3", 0 0, L_0x1311b00; 1 drivers +v0x11a3a90_0 .net *"_s5", 0 0, L_0x1311c60; 1 drivers +v0x11a3b70_0 .net *"_s6", 0 0, L_0x1311e90; 1 drivers +v0x11a3c50_0 .net "in", 3 0, L_0x1312590; 1 drivers +v0x11a3dc0_0 .net "ors", 1 0, L_0x1311da0; 1 drivers +v0x11a3ea0_0 .net "out", 0 0, L_0x1312280; 1 drivers +L_0x1311b00 .part L_0x1312590, 0, 1; +L_0x1311c60 .part L_0x1312590, 1, 1; +L_0x1311da0 .concat8 [ 1 1 0 0], L_0x1311a40, L_0x1311e90; +L_0x1311fa0 .part L_0x1312590, 2, 1; +L_0x1312100 .part L_0x1312590, 3, 1; +L_0x13122f0 .part L_0x1311da0, 0, 1; +L_0x13124a0 .part L_0x1311da0, 1, 1; +S_0x11a3fc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11a30f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e7eec0/d .functor OR 1, L_0x1e7ef30, L_0x1e7f090, C4<0>, C4<0>; -L_0x1e7eec0 .delay 1 (30000,30000,30000) L_0x1e7eec0/d; -L_0x1e7f2c0/d .functor OR 1, L_0x1e7f3d0, L_0x1e7f530, C4<0>, C4<0>; -L_0x1e7f2c0 .delay 1 (30000,30000,30000) L_0x1e7f2c0/d; -L_0x1e7f6b0/d .functor OR 1, L_0x1e7f720, L_0x1e7f8d0, C4<0>, C4<0>; -L_0x1e7f6b0 .delay 1 (30000,30000,30000) L_0x1e7f6b0/d; -v0x1d11520_0 .net *"_s0", 0 0, L_0x1e7eec0; 1 drivers -v0x1d11620_0 .net *"_s10", 0 0, L_0x1e7f3d0; 1 drivers -v0x1d11700_0 .net *"_s12", 0 0, L_0x1e7f530; 1 drivers -v0x1d117c0_0 .net *"_s14", 0 0, L_0x1e7f720; 1 drivers -v0x1d118a0_0 .net *"_s16", 0 0, L_0x1e7f8d0; 1 drivers -v0x1d119d0_0 .net *"_s3", 0 0, L_0x1e7ef30; 1 drivers -v0x1d11ab0_0 .net *"_s5", 0 0, L_0x1e7f090; 1 drivers -v0x1d11b90_0 .net *"_s6", 0 0, L_0x1e7f2c0; 1 drivers -v0x1d11c70_0 .net "in", 3 0, L_0x1e7fb00; 1 drivers -v0x1d11de0_0 .net "ors", 1 0, L_0x1e7f1d0; 1 drivers -v0x1d11ec0_0 .net "out", 0 0, L_0x1e7f6b0; 1 drivers -L_0x1e7ef30 .part L_0x1e7fb00, 0, 1; -L_0x1e7f090 .part L_0x1e7fb00, 1, 1; -L_0x1e7f1d0 .concat8 [ 1 1 0 0], L_0x1e7eec0, L_0x1e7f2c0; -L_0x1e7f3d0 .part L_0x1e7fb00, 2, 1; -L_0x1e7f530 .part L_0x1e7fb00, 3, 1; -L_0x1e7f720 .part L_0x1e7f1d0, 0, 1; -L_0x1e7f8d0 .part L_0x1e7f1d0, 1, 1; -S_0x1d127d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d06150; +L_0x13126c0/d .functor OR 1, L_0x1312730, L_0x1312890, C4<0>, C4<0>; +L_0x13126c0 .delay 1 (30000,30000,30000) L_0x13126c0/d; +L_0x1312ac0/d .functor OR 1, L_0x1312bd0, L_0x1312d30, C4<0>, C4<0>; +L_0x1312ac0 .delay 1 (30000,30000,30000) L_0x1312ac0/d; +L_0x1312eb0/d .functor OR 1, L_0x1312f20, L_0x13130d0, C4<0>, C4<0>; +L_0x1312eb0 .delay 1 (30000,30000,30000) L_0x1312eb0/d; +v0x11a4180_0 .net *"_s0", 0 0, L_0x13126c0; 1 drivers +v0x11a4280_0 .net *"_s10", 0 0, L_0x1312bd0; 1 drivers +v0x11a4360_0 .net *"_s12", 0 0, L_0x1312d30; 1 drivers +v0x11a4420_0 .net *"_s14", 0 0, L_0x1312f20; 1 drivers +v0x11a4500_0 .net *"_s16", 0 0, L_0x13130d0; 1 drivers +v0x11a4630_0 .net *"_s3", 0 0, L_0x1312730; 1 drivers +v0x11a4710_0 .net *"_s5", 0 0, L_0x1312890; 1 drivers +v0x11a47f0_0 .net *"_s6", 0 0, L_0x1312ac0; 1 drivers +v0x11a48d0_0 .net "in", 3 0, L_0x1313300; 1 drivers +v0x11a4a40_0 .net "ors", 1 0, L_0x13129d0; 1 drivers +v0x11a4b20_0 .net "out", 0 0, L_0x1312eb0; 1 drivers +L_0x1312730 .part L_0x1313300, 0, 1; +L_0x1312890 .part L_0x1313300, 1, 1; +L_0x13129d0 .concat8 [ 1 1 0 0], L_0x13126c0, L_0x1312ac0; +L_0x1312bd0 .part L_0x1313300, 2, 1; +L_0x1312d30 .part L_0x1313300, 3, 1; +L_0x1312f20 .part L_0x13129d0, 0, 1; +L_0x13130d0 .part L_0x13129d0, 1, 1; +S_0x11a5430 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1198db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -14956,80 +14966,80 @@ S_0x1d127d0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d06150; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e7b410/d .functor XNOR 1, L_0x1e83a40, L_0x1e79fd0, C4<0>, C4<0>; -L_0x1e7b410 .delay 1 (20000,20000,20000) L_0x1e7b410/d; -L_0x1e7b680/d .functor AND 1, L_0x1e83a40, L_0x1e7a300, C4<1>, C4<1>; -L_0x1e7b680 .delay 1 (30000,30000,30000) L_0x1e7b680/d; -L_0x1e7b6f0/d .functor AND 1, L_0x1e7b410, L_0x1e7a070, C4<1>, C4<1>; -L_0x1e7b6f0 .delay 1 (30000,30000,30000) L_0x1e7b6f0/d; -L_0x1e7b850/d .functor OR 1, L_0x1e7b6f0, L_0x1e7b680, C4<0>, C4<0>; -L_0x1e7b850 .delay 1 (30000,30000,30000) L_0x1e7b850/d; -v0x1d12a80_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers -v0x1d12b70_0 .net "a_", 0 0, L_0x1e70480; alias, 1 drivers -v0x1d12c30_0 .net "b", 0 0, L_0x1e79fd0; alias, 1 drivers -v0x1d12d20_0 .net "b_", 0 0, L_0x1e7a300; alias, 1 drivers -v0x1d12dc0_0 .net "carryin", 0 0, L_0x1e7a070; alias, 1 drivers -v0x1d12f00_0 .net "eq", 0 0, L_0x1e7b410; 1 drivers -v0x1d12fc0_0 .net "lt", 0 0, L_0x1e7b680; 1 drivers -v0x1d13080_0 .net "out", 0 0, L_0x1e7b850; 1 drivers -v0x1d13140_0 .net "w0", 0 0, L_0x1e7b6f0; 1 drivers -S_0x1d13390 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d06150; +L_0x130ec50/d .functor XNOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; +L_0x130ec50 .delay 1 (20000,20000,20000) L_0x130ec50/d; +L_0x130eec0/d .functor AND 1, L_0x1317160, L_0x130db40, C4<1>, C4<1>; +L_0x130eec0 .delay 1 (30000,30000,30000) L_0x130eec0/d; +L_0x130ef30/d .functor AND 1, L_0x130ec50, L_0x130d8b0, C4<1>, C4<1>; +L_0x130ef30 .delay 1 (30000,30000,30000) L_0x130ef30/d; +L_0x130f090/d .functor OR 1, L_0x130ef30, L_0x130eec0, C4<0>, C4<0>; +L_0x130f090 .delay 1 (30000,30000,30000) L_0x130f090/d; +v0x11a56e0_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers +v0x11a57d0_0 .net "a_", 0 0, L_0x1303cb0; alias, 1 drivers +v0x11a5890_0 .net "b", 0 0, L_0x130d810; alias, 1 drivers +v0x11a5980_0 .net "b_", 0 0, L_0x130db40; alias, 1 drivers +v0x11a5a20_0 .net "carryin", 0 0, L_0x130d8b0; alias, 1 drivers +v0x11a5b60_0 .net "eq", 0 0, L_0x130ec50; 1 drivers +v0x11a5c20_0 .net "lt", 0 0, L_0x130eec0; 1 drivers +v0x11a5ce0_0 .net "out", 0 0, L_0x130f090; 1 drivers +v0x11a5da0_0 .net "w0", 0 0, L_0x130ef30; 1 drivers +S_0x11a5ff0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1198db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e7b1f0/d .functor OR 1, L_0x1e7acf0, L_0x1d145f0, C4<0>, C4<0>; -L_0x1e7b1f0 .delay 1 (30000,30000,30000) L_0x1e7b1f0/d; -v0x1d14180_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers -v0x1d142d0_0 .net "b", 0 0, L_0x1e7a300; alias, 1 drivers -v0x1d14390_0 .net "c1", 0 0, L_0x1e7acf0; 1 drivers -v0x1d14430_0 .net "c2", 0 0, L_0x1d145f0; 1 drivers -v0x1d14500_0 .net "carryin", 0 0, L_0x1e7a070; alias, 1 drivers -v0x1d14680_0 .net "carryout", 0 0, L_0x1e7b1f0; 1 drivers -v0x1d14720_0 .net "s1", 0 0, L_0x1e7ac30; 1 drivers -v0x1d147c0_0 .net "sum", 0 0, L_0x1e7ae50; 1 drivers -S_0x1d135e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d13390; +L_0x130ea30/d .functor OR 1, L_0x130e530, L_0x11a7250, C4<0>, C4<0>; +L_0x130ea30 .delay 1 (30000,30000,30000) L_0x130ea30/d; +v0x11a6de0_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers +v0x11a6f30_0 .net "b", 0 0, L_0x130db40; alias, 1 drivers +v0x11a6ff0_0 .net "c1", 0 0, L_0x130e530; 1 drivers +v0x11a7090_0 .net "c2", 0 0, L_0x11a7250; 1 drivers +v0x11a7160_0 .net "carryin", 0 0, L_0x130d8b0; alias, 1 drivers +v0x11a72e0_0 .net "carryout", 0 0, L_0x130ea30; 1 drivers +v0x11a7380_0 .net "s1", 0 0, L_0x130e470; 1 drivers +v0x11a7420_0 .net "sum", 0 0, L_0x130e690; 1 drivers +S_0x11a6240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11a5ff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e7ac30/d .functor XOR 1, L_0x1e83a40, L_0x1e7a300, C4<0>, C4<0>; -L_0x1e7ac30 .delay 1 (30000,30000,30000) L_0x1e7ac30/d; -L_0x1e7acf0/d .functor AND 1, L_0x1e83a40, L_0x1e7a300, C4<1>, C4<1>; -L_0x1e7acf0 .delay 1 (30000,30000,30000) L_0x1e7acf0/d; -v0x1d13840_0 .net "a", 0 0, L_0x1e83a40; alias, 1 drivers -v0x1d13900_0 .net "b", 0 0, L_0x1e7a300; alias, 1 drivers -v0x1d139c0_0 .net "carryout", 0 0, L_0x1e7acf0; alias, 1 drivers -v0x1d13a60_0 .net "sum", 0 0, L_0x1e7ac30; alias, 1 drivers -S_0x1d13b90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d13390; +L_0x130e470/d .functor XOR 1, L_0x1317160, L_0x130db40, C4<0>, C4<0>; +L_0x130e470 .delay 1 (30000,30000,30000) L_0x130e470/d; +L_0x130e530/d .functor AND 1, L_0x1317160, L_0x130db40, C4<1>, C4<1>; +L_0x130e530 .delay 1 (30000,30000,30000) L_0x130e530/d; +v0x11a64a0_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers +v0x11a6560_0 .net "b", 0 0, L_0x130db40; alias, 1 drivers +v0x11a6620_0 .net "carryout", 0 0, L_0x130e530; alias, 1 drivers +v0x11a66c0_0 .net "sum", 0 0, L_0x130e470; alias, 1 drivers +S_0x11a67f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11a5ff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e7ae50/d .functor XOR 1, L_0x1e7ac30, L_0x1e7a070, C4<0>, C4<0>; -L_0x1e7ae50 .delay 1 (30000,30000,30000) L_0x1e7ae50/d; -L_0x1d145f0/d .functor AND 1, L_0x1e7ac30, L_0x1e7a070, C4<1>, C4<1>; -L_0x1d145f0 .delay 1 (30000,30000,30000) L_0x1d145f0/d; -v0x1d13df0_0 .net "a", 0 0, L_0x1e7ac30; alias, 1 drivers -v0x1d13ec0_0 .net "b", 0 0, L_0x1e7a070; alias, 1 drivers -v0x1d13f60_0 .net "carryout", 0 0, L_0x1d145f0; alias, 1 drivers -v0x1d14030_0 .net "sum", 0 0, L_0x1e7ae50; alias, 1 drivers -S_0x1d15bc0 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d05e80; - .timescale -9 -12; -L_0x7f72592dbe78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbec0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e83ae0/d .functor OR 1, L_0x7f72592dbe78, L_0x7f72592dbec0, C4<0>, C4<0>; -L_0x1e83ae0 .delay 1 (30000,30000,30000) L_0x1e83ae0/d; -v0x1d15db0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbe78; 1 drivers -v0x1d15e90_0 .net/2u *"_s2", 0 0, L_0x7f72592dbec0; 1 drivers -S_0x1d15f70 .scope generate, "alu_slices[28]" "alu_slices[28]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1d16180 .param/l "i" 0 3 37, +C4<011100>; -S_0x1d16240 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d15f70; +L_0x130e690/d .functor XOR 1, L_0x130e470, L_0x130d8b0, C4<0>, C4<0>; +L_0x130e690 .delay 1 (30000,30000,30000) L_0x130e690/d; +L_0x11a7250/d .functor AND 1, L_0x130e470, L_0x130d8b0, C4<1>, C4<1>; +L_0x11a7250 .delay 1 (30000,30000,30000) L_0x11a7250/d; +v0x11a6a50_0 .net "a", 0 0, L_0x130e470; alias, 1 drivers +v0x11a6b20_0 .net "b", 0 0, L_0x130d8b0; alias, 1 drivers +v0x11a6bc0_0 .net "carryout", 0 0, L_0x11a7250; alias, 1 drivers +v0x11a6c90_0 .net "sum", 0 0, L_0x130e690; alias, 1 drivers +S_0x11a8840 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1198ae0; + .timescale -9 -12; +L_0x2b0ab3d06e78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06ec0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1317200/d .functor OR 1, L_0x2b0ab3d06e78, L_0x2b0ab3d06ec0, C4<0>, C4<0>; +L_0x1317200 .delay 1 (30000,30000,30000) L_0x1317200/d; +v0x11a8a30_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06e78; 1 drivers +v0x11a8b10_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06ec0; 1 drivers +S_0x11a8bf0 .scope generate, "alu_slices[28]" "alu_slices[28]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11a8e00 .param/l "i" 0 3 41, +C4<011100>; +S_0x11a8ec0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11a8bf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -15038,445 +15048,445 @@ S_0x1d16240 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d15f70; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e7a1b0/d .functor NOT 1, L_0x1e8d680, C4<0>, C4<0>, C4<0>; -L_0x1e7a1b0 .delay 1 (10000,10000,10000) L_0x1e7a1b0/d; -L_0x1e83ef0/d .functor NOT 1, L_0x1e8d7e0, C4<0>, C4<0>, C4<0>; -L_0x1e83ef0 .delay 1 (10000,10000,10000) L_0x1e83ef0/d; -L_0x1e84ef0/d .functor XOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; -L_0x1e84ef0 .delay 1 (30000,30000,30000) L_0x1e84ef0/d; -L_0x7f72592dbf08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbf50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e855a0/d .functor OR 1, L_0x7f72592dbf08, L_0x7f72592dbf50, C4<0>, C4<0>; -L_0x1e855a0 .delay 1 (30000,30000,30000) L_0x1e855a0/d; -L_0x1e857a0/d .functor AND 1, L_0x1e8d680, L_0x1e8d7e0, C4<1>, C4<1>; -L_0x1e857a0 .delay 1 (30000,30000,30000) L_0x1e857a0/d; -L_0x1e85860/d .functor NAND 1, L_0x1e8d680, L_0x1e8d7e0, C4<1>, C4<1>; -L_0x1e85860 .delay 1 (20000,20000,20000) L_0x1e85860/d; -L_0x1e859c0/d .functor XOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; -L_0x1e859c0 .delay 1 (20000,20000,20000) L_0x1e859c0/d; -L_0x1e85e70/d .functor OR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; -L_0x1e85e70 .delay 1 (30000,30000,30000) L_0x1e85e70/d; -L_0x1e8d580/d .functor NOT 1, L_0x1e897e0, C4<0>, C4<0>, C4<0>; -L_0x1e8d580 .delay 1 (10000,10000,10000) L_0x1e8d580/d; -v0x1d249a0_0 .net "A", 0 0, L_0x1e8d680; 1 drivers -v0x1d24a60_0 .net "A_", 0 0, L_0x1e7a1b0; 1 drivers -v0x1d24b20_0 .net "B", 0 0, L_0x1e8d7e0; 1 drivers -v0x1d24bf0_0 .net "B_", 0 0, L_0x1e83ef0; 1 drivers -v0x1d24c90_0 .net *"_s12", 0 0, L_0x1e855a0; 1 drivers -v0x1d24d80_0 .net/2s *"_s14", 0 0, L_0x7f72592dbf08; 1 drivers -v0x1d24e40_0 .net/2s *"_s16", 0 0, L_0x7f72592dbf50; 1 drivers -v0x1d24f20_0 .net *"_s18", 0 0, L_0x1e857a0; 1 drivers -v0x1d25000_0 .net *"_s20", 0 0, L_0x1e85860; 1 drivers -v0x1d25170_0 .net *"_s22", 0 0, L_0x1e859c0; 1 drivers -v0x1d25250_0 .net *"_s24", 0 0, L_0x1e85e70; 1 drivers -o0x7f7259336788 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1d25330_0 name=_s30 -o0x7f72593367b8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1d25410_0 name=_s32 -v0x1d254f0_0 .net *"_s8", 0 0, L_0x1e84ef0; 1 drivers -v0x1d255d0_0 .net "carryin", 0 0, L_0x1e83ba0; 1 drivers -v0x1d25670_0 .net "carryout", 0 0, L_0x1e8d220; 1 drivers -v0x1d25710_0 .net "carryouts", 7 0, L_0x1ec1bb0; 1 drivers -v0x1d258c0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d25960_0 .net "result", 0 0, L_0x1e897e0; 1 drivers -v0x1d25a50_0 .net "results", 7 0, L_0x1e85c40; 1 drivers -v0x1d25b60_0 .net "zero", 0 0, L_0x1e8d580; 1 drivers -LS_0x1e85c40_0_0 .concat8 [ 1 1 1 1], L_0x1e84410, L_0x1e84a40, L_0x1e84ef0, L_0x1e855a0; -LS_0x1e85c40_0_4 .concat8 [ 1 1 1 1], L_0x1e857a0, L_0x1e85860, L_0x1e859c0, L_0x1e85e70; -L_0x1e85c40 .concat8 [ 4 4 0 0], LS_0x1e85c40_0_0, LS_0x1e85c40_0_4; -LS_0x1ec1bb0_0_0 .concat [ 1 1 1 1], L_0x1e846c0, L_0x1e84d90, o0x7f7259336788, L_0x1e853f0; -LS_0x1ec1bb0_0_4 .concat [ 4 0 0 0], o0x7f72593367b8; -L_0x1ec1bb0 .concat [ 4 4 0 0], LS_0x1ec1bb0_0_0, LS_0x1ec1bb0_0_4; -S_0x1d164c0 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d16240; +L_0x1317570/d .functor NOT 1, L_0x1320ea0, C4<0>, C4<0>, C4<0>; +L_0x1317570 .delay 1 (10000,10000,10000) L_0x1317570/d; +L_0x1317680/d .functor NOT 1, L_0x1321000, C4<0>, C4<0>, C4<0>; +L_0x1317680 .delay 1 (10000,10000,10000) L_0x1317680/d; +L_0x1318680/d .functor XOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; +L_0x1318680 .delay 1 (30000,30000,30000) L_0x1318680/d; +L_0x2b0ab3d06f08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06f50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1318d30/d .functor OR 1, L_0x2b0ab3d06f08, L_0x2b0ab3d06f50, C4<0>, C4<0>; +L_0x1318d30 .delay 1 (30000,30000,30000) L_0x1318d30/d; +L_0x1318f30/d .functor AND 1, L_0x1320ea0, L_0x1321000, C4<1>, C4<1>; +L_0x1318f30 .delay 1 (30000,30000,30000) L_0x1318f30/d; +L_0x1318ff0/d .functor NAND 1, L_0x1320ea0, L_0x1321000, C4<1>, C4<1>; +L_0x1318ff0 .delay 1 (20000,20000,20000) L_0x1318ff0/d; +L_0x1319150/d .functor XOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; +L_0x1319150 .delay 1 (20000,20000,20000) L_0x1319150/d; +L_0x1319600/d .functor OR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; +L_0x1319600 .delay 1 (30000,30000,30000) L_0x1319600/d; +L_0x1320da0/d .functor NOT 1, L_0x131cf70, C4<0>, C4<0>, C4<0>; +L_0x1320da0 .delay 1 (10000,10000,10000) L_0x1320da0/d; +v0x11b75f0_0 .net "A", 0 0, L_0x1320ea0; 1 drivers +v0x11b76b0_0 .net "A_", 0 0, L_0x1317570; 1 drivers +v0x11b7770_0 .net "B", 0 0, L_0x1321000; 1 drivers +v0x11b7840_0 .net "B_", 0 0, L_0x1317680; 1 drivers +v0x11b78e0_0 .net *"_s12", 0 0, L_0x1318d30; 1 drivers +v0x11b79d0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06f08; 1 drivers +v0x11b7a90_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06f50; 1 drivers +v0x11b7b70_0 .net *"_s18", 0 0, L_0x1318f30; 1 drivers +v0x11b7c50_0 .net *"_s20", 0 0, L_0x1318ff0; 1 drivers +v0x11b7dc0_0 .net *"_s22", 0 0, L_0x1319150; 1 drivers +v0x11b7ea0_0 .net *"_s24", 0 0, L_0x1319600; 1 drivers +o0x2b0ab3ce7788 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x11b7f80_0 name=_s30 +o0x2b0ab3ce77b8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x11b8060_0 name=_s32 +v0x11b8140_0 .net *"_s8", 0 0, L_0x1318680; 1 drivers +v0x11b8220_0 .net "carryin", 0 0, L_0x13172c0; 1 drivers +v0x11b82c0_0 .net "carryout", 0 0, L_0x1320a40; 1 drivers +v0x11b8360_0 .net "carryouts", 7 0, L_0x1355ee0; 1 drivers +v0x11b8510_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11b85b0_0 .net "result", 0 0, L_0x131cf70; 1 drivers +v0x11b86a0_0 .net "results", 7 0, L_0x13193d0; 1 drivers +v0x11b87b0_0 .net "zero", 0 0, L_0x1320da0; 1 drivers +LS_0x13193d0_0_0 .concat8 [ 1 1 1 1], L_0x1317ba0, L_0x13181d0, L_0x1318680, L_0x1318d30; +LS_0x13193d0_0_4 .concat8 [ 1 1 1 1], L_0x1318f30, L_0x1318ff0, L_0x1319150, L_0x1319600; +L_0x13193d0 .concat8 [ 4 4 0 0], LS_0x13193d0_0_0, LS_0x13193d0_0_4; +LS_0x1355ee0_0_0 .concat [ 1 1 1 1], L_0x1317e50, L_0x1318520, o0x2b0ab3ce7788, L_0x1318b80; +LS_0x1355ee0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce77b8; +L_0x1355ee0 .concat [ 4 4 0 0], LS_0x1355ee0_0_0, LS_0x1355ee0_0_4; +S_0x11a9140 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11a8ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e846c0/d .functor OR 1, L_0x1e841a0, L_0x1e84560, C4<0>, C4<0>; -L_0x1e846c0 .delay 1 (30000,30000,30000) L_0x1e846c0/d; -v0x1d17320_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers -v0x1d173e0_0 .net "b", 0 0, L_0x1e8d7e0; alias, 1 drivers -v0x1d174b0_0 .net "c1", 0 0, L_0x1e841a0; 1 drivers -v0x1d175b0_0 .net "c2", 0 0, L_0x1e84560; 1 drivers -v0x1d17680_0 .net "carryin", 0 0, L_0x1e83ba0; alias, 1 drivers -v0x1d17770_0 .net "carryout", 0 0, L_0x1e846c0; 1 drivers -v0x1d17810_0 .net "s1", 0 0, L_0x1e840e0; 1 drivers -v0x1d17900_0 .net "sum", 0 0, L_0x1e84410; 1 drivers -S_0x1d16730 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d164c0; +L_0x1317e50/d .functor OR 1, L_0x1317930, L_0x1317cf0, C4<0>, C4<0>; +L_0x1317e50 .delay 1 (30000,30000,30000) L_0x1317e50/d; +v0x11a9f70_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers +v0x11aa030_0 .net "b", 0 0, L_0x1321000; alias, 1 drivers +v0x11aa100_0 .net "c1", 0 0, L_0x1317930; 1 drivers +v0x11aa200_0 .net "c2", 0 0, L_0x1317cf0; 1 drivers +v0x11aa2d0_0 .net "carryin", 0 0, L_0x13172c0; alias, 1 drivers +v0x11aa3c0_0 .net "carryout", 0 0, L_0x1317e50; 1 drivers +v0x11aa460_0 .net "s1", 0 0, L_0x1317870; 1 drivers +v0x11aa550_0 .net "sum", 0 0, L_0x1317ba0; 1 drivers +S_0x11a93b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11a9140; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e840e0/d .functor XOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; -L_0x1e840e0 .delay 1 (30000,30000,30000) L_0x1e840e0/d; -L_0x1e841a0/d .functor AND 1, L_0x1e8d680, L_0x1e8d7e0, C4<1>, C4<1>; -L_0x1e841a0 .delay 1 (30000,30000,30000) L_0x1e841a0/d; -v0x1d16990_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers -v0x1d16a70_0 .net "b", 0 0, L_0x1e8d7e0; alias, 1 drivers -v0x1d16b30_0 .net "carryout", 0 0, L_0x1e841a0; alias, 1 drivers -v0x1d16bd0_0 .net "sum", 0 0, L_0x1e840e0; alias, 1 drivers -S_0x1d16d10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d164c0; +L_0x1317870/d .functor XOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; +L_0x1317870 .delay 1 (30000,30000,30000) L_0x1317870/d; +L_0x1317930/d .functor AND 1, L_0x1320ea0, L_0x1321000, C4<1>, C4<1>; +L_0x1317930 .delay 1 (30000,30000,30000) L_0x1317930/d; +v0x11a9610_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers +v0x11a96f0_0 .net "b", 0 0, L_0x1321000; alias, 1 drivers +v0x11a97b0_0 .net "carryout", 0 0, L_0x1317930; alias, 1 drivers +v0x11a9850_0 .net "sum", 0 0, L_0x1317870; alias, 1 drivers +S_0x11a9990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11a9140; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e84410/d .functor XOR 1, L_0x1e840e0, L_0x1e83ba0, C4<0>, C4<0>; -L_0x1e84410 .delay 1 (30000,30000,30000) L_0x1e84410/d; -L_0x1e84560/d .functor AND 1, L_0x1e840e0, L_0x1e83ba0, C4<1>, C4<1>; -L_0x1e84560 .delay 1 (30000,30000,30000) L_0x1e84560/d; -v0x1d16f70_0 .net "a", 0 0, L_0x1e840e0; alias, 1 drivers -v0x1d17040_0 .net "b", 0 0, L_0x1e83ba0; alias, 1 drivers -v0x1d170e0_0 .net "carryout", 0 0, L_0x1e84560; alias, 1 drivers -v0x1d171b0_0 .net "sum", 0 0, L_0x1e84410; alias, 1 drivers -S_0x1d179d0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d16240; +L_0x1317ba0/d .functor XOR 1, L_0x1317870, L_0x13172c0, C4<0>, C4<0>; +L_0x1317ba0 .delay 1 (30000,30000,30000) L_0x1317ba0/d; +L_0x1317cf0/d .functor AND 1, L_0x1317870, L_0x13172c0, C4<1>, C4<1>; +L_0x1317cf0 .delay 1 (30000,30000,30000) L_0x1317cf0/d; +v0x11a9bf0_0 .net "a", 0 0, L_0x1317870; alias, 1 drivers +v0x11a9c90_0 .net "b", 0 0, L_0x13172c0; alias, 1 drivers +v0x11a9d30_0 .net "carryout", 0 0, L_0x1317cf0; alias, 1 drivers +v0x11a9e00_0 .net "sum", 0 0, L_0x1317ba0; alias, 1 drivers +S_0x11aa620 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11a8ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d1cdc0_0 .net "ands", 7 0, L_0x1e8b220; 1 drivers -v0x1d1ced0_0 .net "in", 7 0, L_0x1ec1bb0; alias, 1 drivers -v0x1d1cf90_0 .net "out", 0 0, L_0x1e8d220; alias, 1 drivers -v0x1d1d060_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d17bf0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d179d0; +v0x11afa10_0 .net "ands", 7 0, L_0x131ea40; 1 drivers +v0x11afb20_0 .net "in", 7 0, L_0x1355ee0; alias, 1 drivers +v0x11afbe0_0 .net "out", 0 0, L_0x1320a40; alias, 1 drivers +v0x11afcb0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11aa840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11aa620; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d1a320_0 .net "A", 7 0, L_0x1ec1bb0; alias, 1 drivers -v0x1d1a420_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d1a4e0_0 .net *"_s0", 0 0, L_0x1e89b40; 1 drivers -v0x1d1a5a0_0 .net *"_s12", 0 0, L_0x1e8a4b0; 1 drivers -v0x1d1a680_0 .net *"_s16", 0 0, L_0x1e8a810; 1 drivers -v0x1d1a7b0_0 .net *"_s20", 0 0, L_0x1e8ab20; 1 drivers -v0x1d1a890_0 .net *"_s24", 0 0, L_0x1e8af10; 1 drivers -v0x1d1a970_0 .net *"_s28", 0 0, L_0x1e8aea0; 1 drivers -v0x1d1aa50_0 .net *"_s4", 0 0, L_0x1e89e50; 1 drivers -v0x1d1abc0_0 .net *"_s8", 0 0, L_0x1e8a1a0; 1 drivers -v0x1d1aca0_0 .net "out", 7 0, L_0x1e8b220; alias, 1 drivers -L_0x1e89c00 .part L_0x1ec1bb0, 0, 1; -L_0x1e89d60 .part v0x1d6daa0_0, 0, 1; -L_0x1e89f10 .part L_0x1ec1bb0, 1, 1; -L_0x1e8a100 .part v0x1d6daa0_0, 1, 1; -L_0x1e8a260 .part L_0x1ec1bb0, 2, 1; -L_0x1e8a3c0 .part v0x1d6daa0_0, 2, 1; -L_0x1e8a570 .part L_0x1ec1bb0, 3, 1; -L_0x1e8a6d0 .part v0x1d6daa0_0, 3, 1; -L_0x1e8a8d0 .part L_0x1ec1bb0, 4, 1; -L_0x1e8aa30 .part v0x1d6daa0_0, 4, 1; -L_0x1e8ab90 .part L_0x1ec1bb0, 5, 1; -L_0x1e8ae00 .part v0x1d6daa0_0, 5, 1; -L_0x1e8afd0 .part L_0x1ec1bb0, 6, 1; -L_0x1e8b130 .part v0x1d6daa0_0, 6, 1; -LS_0x1e8b220_0_0 .concat8 [ 1 1 1 1], L_0x1e89b40, L_0x1e89e50, L_0x1e8a1a0, L_0x1e8a4b0; -LS_0x1e8b220_0_4 .concat8 [ 1 1 1 1], L_0x1e8a810, L_0x1e8ab20, L_0x1e8af10, L_0x1e8aea0; -L_0x1e8b220 .concat8 [ 4 4 0 0], LS_0x1e8b220_0_0, LS_0x1e8b220_0_4; -L_0x1e8b5e0 .part L_0x1ec1bb0, 7, 1; -L_0x1e8b7d0 .part v0x1d6daa0_0, 7, 1; -S_0x1d17e50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d18060 .param/l "i" 0 4 54, +C4<00>; -L_0x1e89b40/d .functor AND 1, L_0x1e89c00, L_0x1e89d60, C4<1>, C4<1>; -L_0x1e89b40 .delay 1 (30000,30000,30000) L_0x1e89b40/d; -v0x1d18140_0 .net *"_s0", 0 0, L_0x1e89c00; 1 drivers -v0x1d18220_0 .net *"_s1", 0 0, L_0x1e89d60; 1 drivers -S_0x1d18300 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d18510 .param/l "i" 0 4 54, +C4<01>; -L_0x1e89e50/d .functor AND 1, L_0x1e89f10, L_0x1e8a100, C4<1>, C4<1>; -L_0x1e89e50 .delay 1 (30000,30000,30000) L_0x1e89e50/d; -v0x1d185d0_0 .net *"_s0", 0 0, L_0x1e89f10; 1 drivers -v0x1d186b0_0 .net *"_s1", 0 0, L_0x1e8a100; 1 drivers -S_0x1d18790 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d189a0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e8a1a0/d .functor AND 1, L_0x1e8a260, L_0x1e8a3c0, C4<1>, C4<1>; -L_0x1e8a1a0 .delay 1 (30000,30000,30000) L_0x1e8a1a0/d; -v0x1d18a40_0 .net *"_s0", 0 0, L_0x1e8a260; 1 drivers -v0x1d18b20_0 .net *"_s1", 0 0, L_0x1e8a3c0; 1 drivers -S_0x1d18c00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d18e10 .param/l "i" 0 4 54, +C4<011>; -L_0x1e8a4b0/d .functor AND 1, L_0x1e8a570, L_0x1e8a6d0, C4<1>, C4<1>; -L_0x1e8a4b0 .delay 1 (30000,30000,30000) L_0x1e8a4b0/d; -v0x1d18ed0_0 .net *"_s0", 0 0, L_0x1e8a570; 1 drivers -v0x1d18fb0_0 .net *"_s1", 0 0, L_0x1e8a6d0; 1 drivers -S_0x1d19090 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d192f0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e8a810/d .functor AND 1, L_0x1e8a8d0, L_0x1e8aa30, C4<1>, C4<1>; -L_0x1e8a810 .delay 1 (30000,30000,30000) L_0x1e8a810/d; -v0x1d193b0_0 .net *"_s0", 0 0, L_0x1e8a8d0; 1 drivers -v0x1d19490_0 .net *"_s1", 0 0, L_0x1e8aa30; 1 drivers -S_0x1d19570 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d19780 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e8ab20/d .functor AND 1, L_0x1e8ab90, L_0x1e8ae00, C4<1>, C4<1>; -L_0x1e8ab20 .delay 1 (30000,30000,30000) L_0x1e8ab20/d; -v0x1d19840_0 .net *"_s0", 0 0, L_0x1e8ab90; 1 drivers -v0x1d19920_0 .net *"_s1", 0 0, L_0x1e8ae00; 1 drivers -S_0x1d19a00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d19c10 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e8af10/d .functor AND 1, L_0x1e8afd0, L_0x1e8b130, C4<1>, C4<1>; -L_0x1e8af10 .delay 1 (30000,30000,30000) L_0x1e8af10/d; -v0x1d19cd0_0 .net *"_s0", 0 0, L_0x1e8afd0; 1 drivers -v0x1d19db0_0 .net *"_s1", 0 0, L_0x1e8b130; 1 drivers -S_0x1d19e90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d17bf0; - .timescale -9 -12; -P_0x1d1a0a0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e8aea0/d .functor AND 1, L_0x1e8b5e0, L_0x1e8b7d0, C4<1>, C4<1>; -L_0x1e8aea0 .delay 1 (30000,30000,30000) L_0x1e8aea0/d; -v0x1d1a160_0 .net *"_s0", 0 0, L_0x1e8b5e0; 1 drivers -v0x1d1a240_0 .net *"_s1", 0 0, L_0x1e8b7d0; 1 drivers -S_0x1d1ae00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d179d0; +v0x11acf70_0 .net "A", 7 0, L_0x1355ee0; alias, 1 drivers +v0x11ad070_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11ad130_0 .net *"_s0", 0 0, L_0x131d2d0; 1 drivers +v0x11ad1f0_0 .net *"_s12", 0 0, L_0x131dc40; 1 drivers +v0x11ad2d0_0 .net *"_s16", 0 0, L_0x131dfa0; 1 drivers +v0x11ad400_0 .net *"_s20", 0 0, L_0x131e310; 1 drivers +v0x11ad4e0_0 .net *"_s24", 0 0, L_0x131e730; 1 drivers +v0x11ad5c0_0 .net *"_s28", 0 0, L_0x131e6c0; 1 drivers +v0x11ad6a0_0 .net *"_s4", 0 0, L_0x131d5e0; 1 drivers +v0x11ad810_0 .net *"_s8", 0 0, L_0x131d930; 1 drivers +v0x11ad8f0_0 .net "out", 7 0, L_0x131ea40; alias, 1 drivers +L_0x131d390 .part L_0x1355ee0, 0, 1; +L_0x131d4f0 .part v0x12010b0_0, 0, 1; +L_0x131d6a0 .part L_0x1355ee0, 1, 1; +L_0x131d890 .part v0x12010b0_0, 1, 1; +L_0x131d9f0 .part L_0x1355ee0, 2, 1; +L_0x131db50 .part v0x12010b0_0, 2, 1; +L_0x131dd00 .part L_0x1355ee0, 3, 1; +L_0x131de60 .part v0x12010b0_0, 3, 1; +L_0x131e0c0 .part L_0x1355ee0, 4, 1; +L_0x131e220 .part v0x12010b0_0, 4, 1; +L_0x131e3b0 .part L_0x1355ee0, 5, 1; +L_0x131e620 .part v0x12010b0_0, 5, 1; +L_0x131e7f0 .part L_0x1355ee0, 6, 1; +L_0x131e950 .part v0x12010b0_0, 6, 1; +LS_0x131ea40_0_0 .concat8 [ 1 1 1 1], L_0x131d2d0, L_0x131d5e0, L_0x131d930, L_0x131dc40; +LS_0x131ea40_0_4 .concat8 [ 1 1 1 1], L_0x131dfa0, L_0x131e310, L_0x131e730, L_0x131e6c0; +L_0x131ea40 .concat8 [ 4 4 0 0], LS_0x131ea40_0_0, LS_0x131ea40_0_4; +L_0x131ee00 .part L_0x1355ee0, 7, 1; +L_0x131eff0 .part v0x12010b0_0, 7, 1; +S_0x11aaaa0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11aacb0 .param/l "i" 0 4 54, +C4<00>; +L_0x131d2d0/d .functor AND 1, L_0x131d390, L_0x131d4f0, C4<1>, C4<1>; +L_0x131d2d0 .delay 1 (30000,30000,30000) L_0x131d2d0/d; +v0x11aad90_0 .net *"_s0", 0 0, L_0x131d390; 1 drivers +v0x11aae70_0 .net *"_s1", 0 0, L_0x131d4f0; 1 drivers +S_0x11aaf50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11ab160 .param/l "i" 0 4 54, +C4<01>; +L_0x131d5e0/d .functor AND 1, L_0x131d6a0, L_0x131d890, C4<1>, C4<1>; +L_0x131d5e0 .delay 1 (30000,30000,30000) L_0x131d5e0/d; +v0x11ab220_0 .net *"_s0", 0 0, L_0x131d6a0; 1 drivers +v0x11ab300_0 .net *"_s1", 0 0, L_0x131d890; 1 drivers +S_0x11ab3e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11ab5f0 .param/l "i" 0 4 54, +C4<010>; +L_0x131d930/d .functor AND 1, L_0x131d9f0, L_0x131db50, C4<1>, C4<1>; +L_0x131d930 .delay 1 (30000,30000,30000) L_0x131d930/d; +v0x11ab690_0 .net *"_s0", 0 0, L_0x131d9f0; 1 drivers +v0x11ab770_0 .net *"_s1", 0 0, L_0x131db50; 1 drivers +S_0x11ab850 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11aba60 .param/l "i" 0 4 54, +C4<011>; +L_0x131dc40/d .functor AND 1, L_0x131dd00, L_0x131de60, C4<1>, C4<1>; +L_0x131dc40 .delay 1 (30000,30000,30000) L_0x131dc40/d; +v0x11abb20_0 .net *"_s0", 0 0, L_0x131dd00; 1 drivers +v0x11abc00_0 .net *"_s1", 0 0, L_0x131de60; 1 drivers +S_0x11abce0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11abf40 .param/l "i" 0 4 54, +C4<0100>; +L_0x131dfa0/d .functor AND 1, L_0x131e0c0, L_0x131e220, C4<1>, C4<1>; +L_0x131dfa0 .delay 1 (30000,30000,30000) L_0x131dfa0/d; +v0x11ac000_0 .net *"_s0", 0 0, L_0x131e0c0; 1 drivers +v0x11ac0e0_0 .net *"_s1", 0 0, L_0x131e220; 1 drivers +S_0x11ac1c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11ac3d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x131e310/d .functor AND 1, L_0x131e3b0, L_0x131e620, C4<1>, C4<1>; +L_0x131e310 .delay 1 (30000,30000,30000) L_0x131e310/d; +v0x11ac490_0 .net *"_s0", 0 0, L_0x131e3b0; 1 drivers +v0x11ac570_0 .net *"_s1", 0 0, L_0x131e620; 1 drivers +S_0x11ac650 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11ac860 .param/l "i" 0 4 54, +C4<0110>; +L_0x131e730/d .functor AND 1, L_0x131e7f0, L_0x131e950, C4<1>, C4<1>; +L_0x131e730 .delay 1 (30000,30000,30000) L_0x131e730/d; +v0x11ac920_0 .net *"_s0", 0 0, L_0x131e7f0; 1 drivers +v0x11aca00_0 .net *"_s1", 0 0, L_0x131e950; 1 drivers +S_0x11acae0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11aa840; + .timescale -9 -12; +P_0x11accf0 .param/l "i" 0 4 54, +C4<0111>; +L_0x131e6c0/d .functor AND 1, L_0x131ee00, L_0x131eff0, C4<1>, C4<1>; +L_0x131e6c0 .delay 1 (30000,30000,30000) L_0x131e6c0/d; +v0x11acdb0_0 .net *"_s0", 0 0, L_0x131ee00; 1 drivers +v0x11ace90_0 .net *"_s1", 0 0, L_0x131eff0; 1 drivers +S_0x11ada50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11aa620; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e8d220/d .functor OR 1, L_0x1e8d2e0, L_0x1e8d490, C4<0>, C4<0>; -L_0x1e8d220 .delay 1 (30000,30000,30000) L_0x1e8d220/d; -v0x1d1c950_0 .net *"_s10", 0 0, L_0x1e8d2e0; 1 drivers -v0x1d1ca30_0 .net *"_s12", 0 0, L_0x1e8d490; 1 drivers -v0x1d1cb10_0 .net "in", 7 0, L_0x1e8b220; alias, 1 drivers -v0x1d1cbe0_0 .net "ors", 1 0, L_0x1e8d040; 1 drivers -v0x1d1cca0_0 .net "out", 0 0, L_0x1e8d220; alias, 1 drivers -L_0x1e8c410 .part L_0x1e8b220, 0, 4; -L_0x1e8d040 .concat8 [ 1 1 0 0], L_0x1e8c100, L_0x1e8cd30; -L_0x1e8d180 .part L_0x1e8b220, 4, 4; -L_0x1e8d2e0 .part L_0x1e8d040, 0, 1; -L_0x1e8d490 .part L_0x1e8d040, 1, 1; -S_0x1d1afc0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d1ae00; +L_0x1320a40/d .functor OR 1, L_0x1320b00, L_0x1320cb0, C4<0>, C4<0>; +L_0x1320a40 .delay 1 (30000,30000,30000) L_0x1320a40/d; +v0x11af5d0_0 .net *"_s10", 0 0, L_0x1320b00; 1 drivers +v0x11af6b0_0 .net *"_s12", 0 0, L_0x1320cb0; 1 drivers +v0x11af790_0 .net "in", 7 0, L_0x131ea40; alias, 1 drivers +v0x11af830_0 .net "ors", 1 0, L_0x1320860; 1 drivers +v0x11af8f0_0 .net "out", 0 0, L_0x1320a40; alias, 1 drivers +L_0x131fc30 .part L_0x131ea40, 0, 4; +L_0x1320860 .concat8 [ 1 1 0 0], L_0x131f920, L_0x1320550; +L_0x13209a0 .part L_0x131ea40, 4, 4; +L_0x1320b00 .part L_0x1320860, 0, 1; +L_0x1320cb0 .part L_0x1320860, 1, 1; +S_0x11adc10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11ada50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e8b8c0/d .functor OR 1, L_0x1e8b980, L_0x1e8bae0, C4<0>, C4<0>; -L_0x1e8b8c0 .delay 1 (30000,30000,30000) L_0x1e8b8c0/d; -L_0x1e8bd10/d .functor OR 1, L_0x1e8be20, L_0x1e8bf80, C4<0>, C4<0>; -L_0x1e8bd10 .delay 1 (30000,30000,30000) L_0x1e8bd10/d; -L_0x1e8c100/d .functor OR 1, L_0x1e8c170, L_0x1e8c320, C4<0>, C4<0>; -L_0x1e8c100 .delay 1 (30000,30000,30000) L_0x1e8c100/d; -v0x1d1b210_0 .net *"_s0", 0 0, L_0x1e8b8c0; 1 drivers -v0x1d1b310_0 .net *"_s10", 0 0, L_0x1e8be20; 1 drivers -v0x1d1b3f0_0 .net *"_s12", 0 0, L_0x1e8bf80; 1 drivers -v0x1d1b4b0_0 .net *"_s14", 0 0, L_0x1e8c170; 1 drivers -v0x1d1b590_0 .net *"_s16", 0 0, L_0x1e8c320; 1 drivers -v0x1d1b6c0_0 .net *"_s3", 0 0, L_0x1e8b980; 1 drivers -v0x1d1b7a0_0 .net *"_s5", 0 0, L_0x1e8bae0; 1 drivers -v0x1d1b880_0 .net *"_s6", 0 0, L_0x1e8bd10; 1 drivers -v0x1d1b960_0 .net "in", 3 0, L_0x1e8c410; 1 drivers -v0x1d1bad0_0 .net "ors", 1 0, L_0x1e8bc20; 1 drivers -v0x1d1bbb0_0 .net "out", 0 0, L_0x1e8c100; 1 drivers -L_0x1e8b980 .part L_0x1e8c410, 0, 1; -L_0x1e8bae0 .part L_0x1e8c410, 1, 1; -L_0x1e8bc20 .concat8 [ 1 1 0 0], L_0x1e8b8c0, L_0x1e8bd10; -L_0x1e8be20 .part L_0x1e8c410, 2, 1; -L_0x1e8bf80 .part L_0x1e8c410, 3, 1; -L_0x1e8c170 .part L_0x1e8bc20, 0, 1; -L_0x1e8c320 .part L_0x1e8bc20, 1, 1; -S_0x1d1bcd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d1ae00; +L_0x131f0e0/d .functor OR 1, L_0x131f1a0, L_0x131f300, C4<0>, C4<0>; +L_0x131f0e0 .delay 1 (30000,30000,30000) L_0x131f0e0/d; +L_0x131f530/d .functor OR 1, L_0x131f640, L_0x131f7a0, C4<0>, C4<0>; +L_0x131f530 .delay 1 (30000,30000,30000) L_0x131f530/d; +L_0x131f920/d .functor OR 1, L_0x131f990, L_0x131fb40, C4<0>, C4<0>; +L_0x131f920 .delay 1 (30000,30000,30000) L_0x131f920/d; +v0x11ade60_0 .net *"_s0", 0 0, L_0x131f0e0; 1 drivers +v0x11adf60_0 .net *"_s10", 0 0, L_0x131f640; 1 drivers +v0x11ae020_0 .net *"_s12", 0 0, L_0x131f7a0; 1 drivers +v0x11ae130_0 .net *"_s14", 0 0, L_0x131f990; 1 drivers +v0x11ae210_0 .net *"_s16", 0 0, L_0x131fb40; 1 drivers +v0x11ae340_0 .net *"_s3", 0 0, L_0x131f1a0; 1 drivers +v0x11ae420_0 .net *"_s5", 0 0, L_0x131f300; 1 drivers +v0x11ae500_0 .net *"_s6", 0 0, L_0x131f530; 1 drivers +v0x11ae5e0_0 .net "in", 3 0, L_0x131fc30; 1 drivers +v0x11ae750_0 .net "ors", 1 0, L_0x131f440; 1 drivers +v0x11ae830_0 .net "out", 0 0, L_0x131f920; 1 drivers +L_0x131f1a0 .part L_0x131fc30, 0, 1; +L_0x131f300 .part L_0x131fc30, 1, 1; +L_0x131f440 .concat8 [ 1 1 0 0], L_0x131f0e0, L_0x131f530; +L_0x131f640 .part L_0x131fc30, 2, 1; +L_0x131f7a0 .part L_0x131fc30, 3, 1; +L_0x131f990 .part L_0x131f440, 0, 1; +L_0x131fb40 .part L_0x131f440, 1, 1; +S_0x11ae950 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11ada50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e8c540/d .functor OR 1, L_0x1e8c5b0, L_0x1e8c710, C4<0>, C4<0>; -L_0x1e8c540 .delay 1 (30000,30000,30000) L_0x1e8c540/d; -L_0x1e8c940/d .functor OR 1, L_0x1e8ca50, L_0x1e8cbb0, C4<0>, C4<0>; -L_0x1e8c940 .delay 1 (30000,30000,30000) L_0x1e8c940/d; -L_0x1e8cd30/d .functor OR 1, L_0x1e8cda0, L_0x1e8cf50, C4<0>, C4<0>; -L_0x1e8cd30 .delay 1 (30000,30000,30000) L_0x1e8cd30/d; -v0x1d1be90_0 .net *"_s0", 0 0, L_0x1e8c540; 1 drivers -v0x1d1bf90_0 .net *"_s10", 0 0, L_0x1e8ca50; 1 drivers -v0x1d1c070_0 .net *"_s12", 0 0, L_0x1e8cbb0; 1 drivers -v0x1d1c130_0 .net *"_s14", 0 0, L_0x1e8cda0; 1 drivers -v0x1d1c210_0 .net *"_s16", 0 0, L_0x1e8cf50; 1 drivers -v0x1d1c340_0 .net *"_s3", 0 0, L_0x1e8c5b0; 1 drivers -v0x1d1c420_0 .net *"_s5", 0 0, L_0x1e8c710; 1 drivers -v0x1d1c500_0 .net *"_s6", 0 0, L_0x1e8c940; 1 drivers -v0x1d1c5e0_0 .net "in", 3 0, L_0x1e8d180; 1 drivers -v0x1d1c750_0 .net "ors", 1 0, L_0x1e8c850; 1 drivers -v0x1d1c830_0 .net "out", 0 0, L_0x1e8cd30; 1 drivers -L_0x1e8c5b0 .part L_0x1e8d180, 0, 1; -L_0x1e8c710 .part L_0x1e8d180, 1, 1; -L_0x1e8c850 .concat8 [ 1 1 0 0], L_0x1e8c540, L_0x1e8c940; -L_0x1e8ca50 .part L_0x1e8d180, 2, 1; -L_0x1e8cbb0 .part L_0x1e8d180, 3, 1; -L_0x1e8cda0 .part L_0x1e8c850, 0, 1; -L_0x1e8cf50 .part L_0x1e8c850, 1, 1; -S_0x1d1d140 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d16240; +L_0x131fd60/d .functor OR 1, L_0x131fdd0, L_0x131ff30, C4<0>, C4<0>; +L_0x131fd60 .delay 1 (30000,30000,30000) L_0x131fd60/d; +L_0x1320160/d .functor OR 1, L_0x1320270, L_0x13203d0, C4<0>, C4<0>; +L_0x1320160 .delay 1 (30000,30000,30000) L_0x1320160/d; +L_0x1320550/d .functor OR 1, L_0x13205c0, L_0x1320770, C4<0>, C4<0>; +L_0x1320550 .delay 1 (30000,30000,30000) L_0x1320550/d; +v0x11aeb10_0 .net *"_s0", 0 0, L_0x131fd60; 1 drivers +v0x11aec10_0 .net *"_s10", 0 0, L_0x1320270; 1 drivers +v0x11aecf0_0 .net *"_s12", 0 0, L_0x13203d0; 1 drivers +v0x11aedb0_0 .net *"_s14", 0 0, L_0x13205c0; 1 drivers +v0x11aee90_0 .net *"_s16", 0 0, L_0x1320770; 1 drivers +v0x11aefc0_0 .net *"_s3", 0 0, L_0x131fdd0; 1 drivers +v0x11af0a0_0 .net *"_s5", 0 0, L_0x131ff30; 1 drivers +v0x11af180_0 .net *"_s6", 0 0, L_0x1320160; 1 drivers +v0x11af260_0 .net "in", 3 0, L_0x13209a0; 1 drivers +v0x11af3d0_0 .net "ors", 1 0, L_0x1320070; 1 drivers +v0x11af4b0_0 .net "out", 0 0, L_0x1320550; 1 drivers +L_0x131fdd0 .part L_0x13209a0, 0, 1; +L_0x131ff30 .part L_0x13209a0, 1, 1; +L_0x1320070 .concat8 [ 1 1 0 0], L_0x131fd60, L_0x1320160; +L_0x1320270 .part L_0x13209a0, 2, 1; +L_0x13203d0 .part L_0x13209a0, 3, 1; +L_0x13205c0 .part L_0x1320070, 0, 1; +L_0x1320770 .part L_0x1320070, 1, 1; +S_0x11afd90 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11a8ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d22570_0 .net "ands", 7 0, L_0x1e877e0; 1 drivers -v0x1d22680_0 .net "in", 7 0, L_0x1e85c40; alias, 1 drivers -v0x1d22740_0 .net "out", 0 0, L_0x1e897e0; alias, 1 drivers -v0x1d22810_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d1d390 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d1d140; +v0x11b51c0_0 .net "ands", 7 0, L_0x131af70; 1 drivers +v0x11b52d0_0 .net "in", 7 0, L_0x13193d0; alias, 1 drivers +v0x11b5390_0 .net "out", 0 0, L_0x131cf70; alias, 1 drivers +v0x11b5460_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11affe0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11afd90; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d1fad0_0 .net "A", 7 0, L_0x1e85c40; alias, 1 drivers -v0x1d1fbd0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d1fc90_0 .net *"_s0", 0 0, L_0x1e85fd0; 1 drivers -v0x1d1fd50_0 .net *"_s12", 0 0, L_0x1e86990; 1 drivers -v0x1d1fe30_0 .net *"_s16", 0 0, L_0x1e86cf0; 1 drivers -v0x1d1ff60_0 .net *"_s20", 0 0, L_0x1e87120; 1 drivers -v0x1d20040_0 .net *"_s24", 0 0, L_0x1e87450; 1 drivers -v0x1d20120_0 .net *"_s28", 0 0, L_0x1e873e0; 1 drivers -v0x1d20200_0 .net *"_s4", 0 0, L_0x1e86370; 1 drivers -v0x1d20370_0 .net *"_s8", 0 0, L_0x1e86680; 1 drivers -v0x1d20450_0 .net "out", 7 0, L_0x1e877e0; alias, 1 drivers -L_0x1e860e0 .part L_0x1e85c40, 0, 1; -L_0x1e862d0 .part v0x1d6daa0_0, 0, 1; -L_0x1e86430 .part L_0x1e85c40, 1, 1; -L_0x1e86590 .part v0x1d6daa0_0, 1, 1; -L_0x1e86740 .part L_0x1e85c40, 2, 1; -L_0x1e868a0 .part v0x1d6daa0_0, 2, 1; -L_0x1e86a50 .part L_0x1e85c40, 3, 1; -L_0x1e86bb0 .part v0x1d6daa0_0, 3, 1; -L_0x1e86db0 .part L_0x1e85c40, 4, 1; -L_0x1e87020 .part v0x1d6daa0_0, 4, 1; -L_0x1e87190 .part L_0x1e85c40, 5, 1; -L_0x1e872f0 .part v0x1d6daa0_0, 5, 1; -L_0x1e87510 .part L_0x1e85c40, 6, 1; -L_0x1e87670 .part v0x1d6daa0_0, 6, 1; -LS_0x1e877e0_0_0 .concat8 [ 1 1 1 1], L_0x1e85fd0, L_0x1e86370, L_0x1e86680, L_0x1e86990; -LS_0x1e877e0_0_4 .concat8 [ 1 1 1 1], L_0x1e86cf0, L_0x1e87120, L_0x1e87450, L_0x1e873e0; -L_0x1e877e0 .concat8 [ 4 4 0 0], LS_0x1e877e0_0_0, LS_0x1e877e0_0_4; -L_0x1e87ba0 .part L_0x1e85c40, 7, 1; -L_0x1e87d90 .part v0x1d6daa0_0, 7, 1; -S_0x1d1d5d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1d7e0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e85fd0/d .functor AND 1, L_0x1e860e0, L_0x1e862d0, C4<1>, C4<1>; -L_0x1e85fd0 .delay 1 (30000,30000,30000) L_0x1e85fd0/d; -v0x1d1d8c0_0 .net *"_s0", 0 0, L_0x1e860e0; 1 drivers -v0x1d1d9a0_0 .net *"_s1", 0 0, L_0x1e862d0; 1 drivers -S_0x1d1da80 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1dc90 .param/l "i" 0 4 54, +C4<01>; -L_0x1e86370/d .functor AND 1, L_0x1e86430, L_0x1e86590, C4<1>, C4<1>; -L_0x1e86370 .delay 1 (30000,30000,30000) L_0x1e86370/d; -v0x1d1dd50_0 .net *"_s0", 0 0, L_0x1e86430; 1 drivers -v0x1d1de30_0 .net *"_s1", 0 0, L_0x1e86590; 1 drivers -S_0x1d1df10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1e150 .param/l "i" 0 4 54, +C4<010>; -L_0x1e86680/d .functor AND 1, L_0x1e86740, L_0x1e868a0, C4<1>, C4<1>; -L_0x1e86680 .delay 1 (30000,30000,30000) L_0x1e86680/d; -v0x1d1e1f0_0 .net *"_s0", 0 0, L_0x1e86740; 1 drivers -v0x1d1e2d0_0 .net *"_s1", 0 0, L_0x1e868a0; 1 drivers -S_0x1d1e3b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1e5c0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e86990/d .functor AND 1, L_0x1e86a50, L_0x1e86bb0, C4<1>, C4<1>; -L_0x1e86990 .delay 1 (30000,30000,30000) L_0x1e86990/d; -v0x1d1e680_0 .net *"_s0", 0 0, L_0x1e86a50; 1 drivers -v0x1d1e760_0 .net *"_s1", 0 0, L_0x1e86bb0; 1 drivers -S_0x1d1e840 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1eaa0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e86cf0/d .functor AND 1, L_0x1e86db0, L_0x1e87020, C4<1>, C4<1>; -L_0x1e86cf0 .delay 1 (30000,30000,30000) L_0x1e86cf0/d; -v0x1d1eb60_0 .net *"_s0", 0 0, L_0x1e86db0; 1 drivers -v0x1d1ec40_0 .net *"_s1", 0 0, L_0x1e87020; 1 drivers -S_0x1d1ed20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1ef30 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e87120/d .functor AND 1, L_0x1e87190, L_0x1e872f0, C4<1>, C4<1>; -L_0x1e87120 .delay 1 (30000,30000,30000) L_0x1e87120/d; -v0x1d1eff0_0 .net *"_s0", 0 0, L_0x1e87190; 1 drivers -v0x1d1f0d0_0 .net *"_s1", 0 0, L_0x1e872f0; 1 drivers -S_0x1d1f1b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1f3c0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e87450/d .functor AND 1, L_0x1e87510, L_0x1e87670, C4<1>, C4<1>; -L_0x1e87450 .delay 1 (30000,30000,30000) L_0x1e87450/d; -v0x1d1f480_0 .net *"_s0", 0 0, L_0x1e87510; 1 drivers -v0x1d1f560_0 .net *"_s1", 0 0, L_0x1e87670; 1 drivers -S_0x1d1f640 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d1d390; - .timescale -9 -12; -P_0x1d1f850 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e873e0/d .functor AND 1, L_0x1e87ba0, L_0x1e87d90, C4<1>, C4<1>; -L_0x1e873e0 .delay 1 (30000,30000,30000) L_0x1e873e0/d; -v0x1d1f910_0 .net *"_s0", 0 0, L_0x1e87ba0; 1 drivers -v0x1d1f9f0_0 .net *"_s1", 0 0, L_0x1e87d90; 1 drivers -S_0x1d205b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d1d140; +v0x11b2720_0 .net "A", 7 0, L_0x13193d0; alias, 1 drivers +v0x11b2820_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11b28e0_0 .net *"_s0", 0 0, L_0x1319760; 1 drivers +v0x11b29a0_0 .net *"_s12", 0 0, L_0x131a120; 1 drivers +v0x11b2a80_0 .net *"_s16", 0 0, L_0x131a480; 1 drivers +v0x11b2bb0_0 .net *"_s20", 0 0, L_0x131a8b0; 1 drivers +v0x11b2c90_0 .net *"_s24", 0 0, L_0x131abe0; 1 drivers +v0x11b2d70_0 .net *"_s28", 0 0, L_0x131ab70; 1 drivers +v0x11b2e50_0 .net *"_s4", 0 0, L_0x1319b00; 1 drivers +v0x11b2fc0_0 .net *"_s8", 0 0, L_0x1319e10; 1 drivers +v0x11b30a0_0 .net "out", 7 0, L_0x131af70; alias, 1 drivers +L_0x1319870 .part L_0x13193d0, 0, 1; +L_0x1319a60 .part v0x12010b0_0, 0, 1; +L_0x1319bc0 .part L_0x13193d0, 1, 1; +L_0x1319d20 .part v0x12010b0_0, 1, 1; +L_0x1319ed0 .part L_0x13193d0, 2, 1; +L_0x131a030 .part v0x12010b0_0, 2, 1; +L_0x131a1e0 .part L_0x13193d0, 3, 1; +L_0x131a340 .part v0x12010b0_0, 3, 1; +L_0x131a540 .part L_0x13193d0, 4, 1; +L_0x131a7b0 .part v0x12010b0_0, 4, 1; +L_0x131a920 .part L_0x13193d0, 5, 1; +L_0x131aa80 .part v0x12010b0_0, 5, 1; +L_0x131aca0 .part L_0x13193d0, 6, 1; +L_0x131ae00 .part v0x12010b0_0, 6, 1; +LS_0x131af70_0_0 .concat8 [ 1 1 1 1], L_0x1319760, L_0x1319b00, L_0x1319e10, L_0x131a120; +LS_0x131af70_0_4 .concat8 [ 1 1 1 1], L_0x131a480, L_0x131a8b0, L_0x131abe0, L_0x131ab70; +L_0x131af70 .concat8 [ 4 4 0 0], LS_0x131af70_0_0, LS_0x131af70_0_4; +L_0x131b330 .part L_0x13193d0, 7, 1; +L_0x131b520 .part v0x12010b0_0, 7, 1; +S_0x11b0220 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b0430 .param/l "i" 0 4 54, +C4<00>; +L_0x1319760/d .functor AND 1, L_0x1319870, L_0x1319a60, C4<1>, C4<1>; +L_0x1319760 .delay 1 (30000,30000,30000) L_0x1319760/d; +v0x11b0510_0 .net *"_s0", 0 0, L_0x1319870; 1 drivers +v0x11b05f0_0 .net *"_s1", 0 0, L_0x1319a60; 1 drivers +S_0x11b06d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b08e0 .param/l "i" 0 4 54, +C4<01>; +L_0x1319b00/d .functor AND 1, L_0x1319bc0, L_0x1319d20, C4<1>, C4<1>; +L_0x1319b00 .delay 1 (30000,30000,30000) L_0x1319b00/d; +v0x11b09a0_0 .net *"_s0", 0 0, L_0x1319bc0; 1 drivers +v0x11b0a80_0 .net *"_s1", 0 0, L_0x1319d20; 1 drivers +S_0x11b0b60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b0da0 .param/l "i" 0 4 54, +C4<010>; +L_0x1319e10/d .functor AND 1, L_0x1319ed0, L_0x131a030, C4<1>, C4<1>; +L_0x1319e10 .delay 1 (30000,30000,30000) L_0x1319e10/d; +v0x11b0e40_0 .net *"_s0", 0 0, L_0x1319ed0; 1 drivers +v0x11b0f20_0 .net *"_s1", 0 0, L_0x131a030; 1 drivers +S_0x11b1000 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b1210 .param/l "i" 0 4 54, +C4<011>; +L_0x131a120/d .functor AND 1, L_0x131a1e0, L_0x131a340, C4<1>, C4<1>; +L_0x131a120 .delay 1 (30000,30000,30000) L_0x131a120/d; +v0x11b12d0_0 .net *"_s0", 0 0, L_0x131a1e0; 1 drivers +v0x11b13b0_0 .net *"_s1", 0 0, L_0x131a340; 1 drivers +S_0x11b1490 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b16f0 .param/l "i" 0 4 54, +C4<0100>; +L_0x131a480/d .functor AND 1, L_0x131a540, L_0x131a7b0, C4<1>, C4<1>; +L_0x131a480 .delay 1 (30000,30000,30000) L_0x131a480/d; +v0x11b17b0_0 .net *"_s0", 0 0, L_0x131a540; 1 drivers +v0x11b1890_0 .net *"_s1", 0 0, L_0x131a7b0; 1 drivers +S_0x11b1970 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b1b80 .param/l "i" 0 4 54, +C4<0101>; +L_0x131a8b0/d .functor AND 1, L_0x131a920, L_0x131aa80, C4<1>, C4<1>; +L_0x131a8b0 .delay 1 (30000,30000,30000) L_0x131a8b0/d; +v0x11b1c40_0 .net *"_s0", 0 0, L_0x131a920; 1 drivers +v0x11b1d20_0 .net *"_s1", 0 0, L_0x131aa80; 1 drivers +S_0x11b1e00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b2010 .param/l "i" 0 4 54, +C4<0110>; +L_0x131abe0/d .functor AND 1, L_0x131aca0, L_0x131ae00, C4<1>, C4<1>; +L_0x131abe0 .delay 1 (30000,30000,30000) L_0x131abe0/d; +v0x11b20d0_0 .net *"_s0", 0 0, L_0x131aca0; 1 drivers +v0x11b21b0_0 .net *"_s1", 0 0, L_0x131ae00; 1 drivers +S_0x11b2290 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11affe0; + .timescale -9 -12; +P_0x11b24a0 .param/l "i" 0 4 54, +C4<0111>; +L_0x131ab70/d .functor AND 1, L_0x131b330, L_0x131b520, C4<1>, C4<1>; +L_0x131ab70 .delay 1 (30000,30000,30000) L_0x131ab70/d; +v0x11b2560_0 .net *"_s0", 0 0, L_0x131b330; 1 drivers +v0x11b2640_0 .net *"_s1", 0 0, L_0x131b520; 1 drivers +S_0x11b3200 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11afd90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e897e0/d .functor OR 1, L_0x1e898a0, L_0x1e89a50, C4<0>, C4<0>; -L_0x1e897e0 .delay 1 (30000,30000,30000) L_0x1e897e0/d; -v0x1d22100_0 .net *"_s10", 0 0, L_0x1e898a0; 1 drivers -v0x1d221e0_0 .net *"_s12", 0 0, L_0x1e89a50; 1 drivers -v0x1d222c0_0 .net "in", 7 0, L_0x1e877e0; alias, 1 drivers -v0x1d22390_0 .net "ors", 1 0, L_0x1e89600; 1 drivers -v0x1d22450_0 .net "out", 0 0, L_0x1e897e0; alias, 1 drivers -L_0x1e889d0 .part L_0x1e877e0, 0, 4; -L_0x1e89600 .concat8 [ 1 1 0 0], L_0x1e886c0, L_0x1e892f0; -L_0x1e89740 .part L_0x1e877e0, 4, 4; -L_0x1e898a0 .part L_0x1e89600, 0, 1; -L_0x1e89a50 .part L_0x1e89600, 1, 1; -S_0x1d20770 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d205b0; +L_0x131cf70/d .functor OR 1, L_0x131d030, L_0x131d1e0, C4<0>, C4<0>; +L_0x131cf70 .delay 1 (30000,30000,30000) L_0x131cf70/d; +v0x11b4d50_0 .net *"_s10", 0 0, L_0x131d030; 1 drivers +v0x11b4e30_0 .net *"_s12", 0 0, L_0x131d1e0; 1 drivers +v0x11b4f10_0 .net "in", 7 0, L_0x131af70; alias, 1 drivers +v0x11b4fe0_0 .net "ors", 1 0, L_0x131cd90; 1 drivers +v0x11b50a0_0 .net "out", 0 0, L_0x131cf70; alias, 1 drivers +L_0x131c160 .part L_0x131af70, 0, 4; +L_0x131cd90 .concat8 [ 1 1 0 0], L_0x131be50, L_0x131ca80; +L_0x131ced0 .part L_0x131af70, 4, 4; +L_0x131d030 .part L_0x131cd90, 0, 1; +L_0x131d1e0 .part L_0x131cd90, 1, 1; +S_0x11b33c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11b3200; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e87e80/d .functor OR 1, L_0x1e87f40, L_0x1e880a0, C4<0>, C4<0>; -L_0x1e87e80 .delay 1 (30000,30000,30000) L_0x1e87e80/d; -L_0x1e882d0/d .functor OR 1, L_0x1e883e0, L_0x1e88540, C4<0>, C4<0>; -L_0x1e882d0 .delay 1 (30000,30000,30000) L_0x1e882d0/d; -L_0x1e886c0/d .functor OR 1, L_0x1e88730, L_0x1e888e0, C4<0>, C4<0>; -L_0x1e886c0 .delay 1 (30000,30000,30000) L_0x1e886c0/d; -v0x1d209c0_0 .net *"_s0", 0 0, L_0x1e87e80; 1 drivers -v0x1d20ac0_0 .net *"_s10", 0 0, L_0x1e883e0; 1 drivers -v0x1d20ba0_0 .net *"_s12", 0 0, L_0x1e88540; 1 drivers -v0x1d20c60_0 .net *"_s14", 0 0, L_0x1e88730; 1 drivers -v0x1d20d40_0 .net *"_s16", 0 0, L_0x1e888e0; 1 drivers -v0x1d20e70_0 .net *"_s3", 0 0, L_0x1e87f40; 1 drivers -v0x1d20f50_0 .net *"_s5", 0 0, L_0x1e880a0; 1 drivers -v0x1d21030_0 .net *"_s6", 0 0, L_0x1e882d0; 1 drivers -v0x1d21110_0 .net "in", 3 0, L_0x1e889d0; 1 drivers -v0x1d21280_0 .net "ors", 1 0, L_0x1e881e0; 1 drivers -v0x1d21360_0 .net "out", 0 0, L_0x1e886c0; 1 drivers -L_0x1e87f40 .part L_0x1e889d0, 0, 1; -L_0x1e880a0 .part L_0x1e889d0, 1, 1; -L_0x1e881e0 .concat8 [ 1 1 0 0], L_0x1e87e80, L_0x1e882d0; -L_0x1e883e0 .part L_0x1e889d0, 2, 1; -L_0x1e88540 .part L_0x1e889d0, 3, 1; -L_0x1e88730 .part L_0x1e881e0, 0, 1; -L_0x1e888e0 .part L_0x1e881e0, 1, 1; -S_0x1d21480 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d205b0; +L_0x131b610/d .functor OR 1, L_0x131b6d0, L_0x131b830, C4<0>, C4<0>; +L_0x131b610 .delay 1 (30000,30000,30000) L_0x131b610/d; +L_0x131ba60/d .functor OR 1, L_0x131bb70, L_0x131bcd0, C4<0>, C4<0>; +L_0x131ba60 .delay 1 (30000,30000,30000) L_0x131ba60/d; +L_0x131be50/d .functor OR 1, L_0x131bec0, L_0x131c070, C4<0>, C4<0>; +L_0x131be50 .delay 1 (30000,30000,30000) L_0x131be50/d; +v0x11b3610_0 .net *"_s0", 0 0, L_0x131b610; 1 drivers +v0x11b3710_0 .net *"_s10", 0 0, L_0x131bb70; 1 drivers +v0x11b37f0_0 .net *"_s12", 0 0, L_0x131bcd0; 1 drivers +v0x11b38b0_0 .net *"_s14", 0 0, L_0x131bec0; 1 drivers +v0x11b3990_0 .net *"_s16", 0 0, L_0x131c070; 1 drivers +v0x11b3ac0_0 .net *"_s3", 0 0, L_0x131b6d0; 1 drivers +v0x11b3ba0_0 .net *"_s5", 0 0, L_0x131b830; 1 drivers +v0x11b3c80_0 .net *"_s6", 0 0, L_0x131ba60; 1 drivers +v0x11b3d60_0 .net "in", 3 0, L_0x131c160; 1 drivers +v0x11b3ed0_0 .net "ors", 1 0, L_0x131b970; 1 drivers +v0x11b3fb0_0 .net "out", 0 0, L_0x131be50; 1 drivers +L_0x131b6d0 .part L_0x131c160, 0, 1; +L_0x131b830 .part L_0x131c160, 1, 1; +L_0x131b970 .concat8 [ 1 1 0 0], L_0x131b610, L_0x131ba60; +L_0x131bb70 .part L_0x131c160, 2, 1; +L_0x131bcd0 .part L_0x131c160, 3, 1; +L_0x131bec0 .part L_0x131b970, 0, 1; +L_0x131c070 .part L_0x131b970, 1, 1; +S_0x11b40d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11b3200; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e88b00/d .functor OR 1, L_0x1e88b70, L_0x1e88cd0, C4<0>, C4<0>; -L_0x1e88b00 .delay 1 (30000,30000,30000) L_0x1e88b00/d; -L_0x1e88f00/d .functor OR 1, L_0x1e89010, L_0x1e89170, C4<0>, C4<0>; -L_0x1e88f00 .delay 1 (30000,30000,30000) L_0x1e88f00/d; -L_0x1e892f0/d .functor OR 1, L_0x1e89360, L_0x1e89510, C4<0>, C4<0>; -L_0x1e892f0 .delay 1 (30000,30000,30000) L_0x1e892f0/d; -v0x1d21640_0 .net *"_s0", 0 0, L_0x1e88b00; 1 drivers -v0x1d21740_0 .net *"_s10", 0 0, L_0x1e89010; 1 drivers -v0x1d21820_0 .net *"_s12", 0 0, L_0x1e89170; 1 drivers -v0x1d218e0_0 .net *"_s14", 0 0, L_0x1e89360; 1 drivers -v0x1d219c0_0 .net *"_s16", 0 0, L_0x1e89510; 1 drivers -v0x1d21af0_0 .net *"_s3", 0 0, L_0x1e88b70; 1 drivers -v0x1d21bd0_0 .net *"_s5", 0 0, L_0x1e88cd0; 1 drivers -v0x1d21cb0_0 .net *"_s6", 0 0, L_0x1e88f00; 1 drivers -v0x1d21d90_0 .net "in", 3 0, L_0x1e89740; 1 drivers -v0x1d21f00_0 .net "ors", 1 0, L_0x1e88e10; 1 drivers -v0x1d21fe0_0 .net "out", 0 0, L_0x1e892f0; 1 drivers -L_0x1e88b70 .part L_0x1e89740, 0, 1; -L_0x1e88cd0 .part L_0x1e89740, 1, 1; -L_0x1e88e10 .concat8 [ 1 1 0 0], L_0x1e88b00, L_0x1e88f00; -L_0x1e89010 .part L_0x1e89740, 2, 1; -L_0x1e89170 .part L_0x1e89740, 3, 1; -L_0x1e89360 .part L_0x1e88e10, 0, 1; -L_0x1e89510 .part L_0x1e88e10, 1, 1; -S_0x1d228f0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d16240; +L_0x131c290/d .functor OR 1, L_0x131c300, L_0x131c460, C4<0>, C4<0>; +L_0x131c290 .delay 1 (30000,30000,30000) L_0x131c290/d; +L_0x131c690/d .functor OR 1, L_0x131c7a0, L_0x131c900, C4<0>, C4<0>; +L_0x131c690 .delay 1 (30000,30000,30000) L_0x131c690/d; +L_0x131ca80/d .functor OR 1, L_0x131caf0, L_0x131cca0, C4<0>, C4<0>; +L_0x131ca80 .delay 1 (30000,30000,30000) L_0x131ca80/d; +v0x11b4290_0 .net *"_s0", 0 0, L_0x131c290; 1 drivers +v0x11b4390_0 .net *"_s10", 0 0, L_0x131c7a0; 1 drivers +v0x11b4470_0 .net *"_s12", 0 0, L_0x131c900; 1 drivers +v0x11b4530_0 .net *"_s14", 0 0, L_0x131caf0; 1 drivers +v0x11b4610_0 .net *"_s16", 0 0, L_0x131cca0; 1 drivers +v0x11b4740_0 .net *"_s3", 0 0, L_0x131c300; 1 drivers +v0x11b4820_0 .net *"_s5", 0 0, L_0x131c460; 1 drivers +v0x11b4900_0 .net *"_s6", 0 0, L_0x131c690; 1 drivers +v0x11b49e0_0 .net "in", 3 0, L_0x131ced0; 1 drivers +v0x11b4b50_0 .net "ors", 1 0, L_0x131c5a0; 1 drivers +v0x11b4c30_0 .net "out", 0 0, L_0x131ca80; 1 drivers +L_0x131c300 .part L_0x131ced0, 0, 1; +L_0x131c460 .part L_0x131ced0, 1, 1; +L_0x131c5a0 .concat8 [ 1 1 0 0], L_0x131c290, L_0x131c690; +L_0x131c7a0 .part L_0x131ced0, 2, 1; +L_0x131c900 .part L_0x131ced0, 3, 1; +L_0x131caf0 .part L_0x131c5a0, 0, 1; +L_0x131cca0 .part L_0x131c5a0, 1, 1; +S_0x11b5540 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11a8ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -15484,80 +15494,80 @@ S_0x1d228f0 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d16240; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e84fb0/d .functor XNOR 1, L_0x1e8d680, L_0x1e8d7e0, C4<0>, C4<0>; -L_0x1e84fb0 .delay 1 (20000,20000,20000) L_0x1e84fb0/d; -L_0x1e85220/d .functor AND 1, L_0x1e8d680, L_0x1e83ef0, C4<1>, C4<1>; -L_0x1e85220 .delay 1 (30000,30000,30000) L_0x1e85220/d; -L_0x1e85290/d .functor AND 1, L_0x1e84fb0, L_0x1e83ba0, C4<1>, C4<1>; -L_0x1e85290 .delay 1 (30000,30000,30000) L_0x1e85290/d; -L_0x1e853f0/d .functor OR 1, L_0x1e85290, L_0x1e85220, C4<0>, C4<0>; -L_0x1e853f0 .delay 1 (30000,30000,30000) L_0x1e853f0/d; -v0x1d22ba0_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers -v0x1d22c90_0 .net "a_", 0 0, L_0x1e7a1b0; alias, 1 drivers -v0x1d22d50_0 .net "b", 0 0, L_0x1e8d7e0; alias, 1 drivers -v0x1d22e40_0 .net "b_", 0 0, L_0x1e83ef0; alias, 1 drivers -v0x1d22ee0_0 .net "carryin", 0 0, L_0x1e83ba0; alias, 1 drivers -v0x1d23020_0 .net "eq", 0 0, L_0x1e84fb0; 1 drivers -v0x1d230e0_0 .net "lt", 0 0, L_0x1e85220; 1 drivers -v0x1d231a0_0 .net "out", 0 0, L_0x1e853f0; 1 drivers -v0x1d23260_0 .net "w0", 0 0, L_0x1e85290; 1 drivers -S_0x1d234b0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d16240; +L_0x1318740/d .functor XNOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; +L_0x1318740 .delay 1 (20000,20000,20000) L_0x1318740/d; +L_0x13189b0/d .functor AND 1, L_0x1320ea0, L_0x1317680, C4<1>, C4<1>; +L_0x13189b0 .delay 1 (30000,30000,30000) L_0x13189b0/d; +L_0x1318a20/d .functor AND 1, L_0x1318740, L_0x13172c0, C4<1>, C4<1>; +L_0x1318a20 .delay 1 (30000,30000,30000) L_0x1318a20/d; +L_0x1318b80/d .functor OR 1, L_0x1318a20, L_0x13189b0, C4<0>, C4<0>; +L_0x1318b80 .delay 1 (30000,30000,30000) L_0x1318b80/d; +v0x11b57f0_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers +v0x11b58e0_0 .net "a_", 0 0, L_0x1317570; alias, 1 drivers +v0x11b59a0_0 .net "b", 0 0, L_0x1321000; alias, 1 drivers +v0x11b5a90_0 .net "b_", 0 0, L_0x1317680; alias, 1 drivers +v0x11b5b30_0 .net "carryin", 0 0, L_0x13172c0; alias, 1 drivers +v0x11b5c70_0 .net "eq", 0 0, L_0x1318740; 1 drivers +v0x11b5d30_0 .net "lt", 0 0, L_0x13189b0; 1 drivers +v0x11b5df0_0 .net "out", 0 0, L_0x1318b80; 1 drivers +v0x11b5eb0_0 .net "w0", 0 0, L_0x1318a20; 1 drivers +S_0x11b6100 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11a8ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e84d90/d .functor OR 1, L_0x1e848e0, L_0x1d24710, C4<0>, C4<0>; -L_0x1e84d90 .delay 1 (30000,30000,30000) L_0x1e84d90/d; -v0x1d242a0_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers -v0x1d243f0_0 .net "b", 0 0, L_0x1e83ef0; alias, 1 drivers -v0x1d244b0_0 .net "c1", 0 0, L_0x1e848e0; 1 drivers -v0x1d24550_0 .net "c2", 0 0, L_0x1d24710; 1 drivers -v0x1d24620_0 .net "carryin", 0 0, L_0x1e83ba0; alias, 1 drivers -v0x1d247a0_0 .net "carryout", 0 0, L_0x1e84d90; 1 drivers -v0x1d24840_0 .net "s1", 0 0, L_0x1e84820; 1 drivers -v0x1d248e0_0 .net "sum", 0 0, L_0x1e84a40; 1 drivers -S_0x1d23700 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d234b0; +L_0x1318520/d .functor OR 1, L_0x1318070, L_0x11b7360, C4<0>, C4<0>; +L_0x1318520 .delay 1 (30000,30000,30000) L_0x1318520/d; +v0x11b6ef0_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers +v0x11b7040_0 .net "b", 0 0, L_0x1317680; alias, 1 drivers +v0x11b7100_0 .net "c1", 0 0, L_0x1318070; 1 drivers +v0x11b71a0_0 .net "c2", 0 0, L_0x11b7360; 1 drivers +v0x11b7270_0 .net "carryin", 0 0, L_0x13172c0; alias, 1 drivers +v0x11b73f0_0 .net "carryout", 0 0, L_0x1318520; 1 drivers +v0x11b7490_0 .net "s1", 0 0, L_0x1317fb0; 1 drivers +v0x11b7530_0 .net "sum", 0 0, L_0x13181d0; 1 drivers +S_0x11b6350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11b6100; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e84820/d .functor XOR 1, L_0x1e8d680, L_0x1e83ef0, C4<0>, C4<0>; -L_0x1e84820 .delay 1 (30000,30000,30000) L_0x1e84820/d; -L_0x1e848e0/d .functor AND 1, L_0x1e8d680, L_0x1e83ef0, C4<1>, C4<1>; -L_0x1e848e0 .delay 1 (30000,30000,30000) L_0x1e848e0/d; -v0x1d23960_0 .net "a", 0 0, L_0x1e8d680; alias, 1 drivers -v0x1d23a20_0 .net "b", 0 0, L_0x1e83ef0; alias, 1 drivers -v0x1d23ae0_0 .net "carryout", 0 0, L_0x1e848e0; alias, 1 drivers -v0x1d23b80_0 .net "sum", 0 0, L_0x1e84820; alias, 1 drivers -S_0x1d23cb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d234b0; +L_0x1317fb0/d .functor XOR 1, L_0x1320ea0, L_0x1317680, C4<0>, C4<0>; +L_0x1317fb0 .delay 1 (30000,30000,30000) L_0x1317fb0/d; +L_0x1318070/d .functor AND 1, L_0x1320ea0, L_0x1317680, C4<1>, C4<1>; +L_0x1318070 .delay 1 (30000,30000,30000) L_0x1318070/d; +v0x11b65b0_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers +v0x11b6670_0 .net "b", 0 0, L_0x1317680; alias, 1 drivers +v0x11b6730_0 .net "carryout", 0 0, L_0x1318070; alias, 1 drivers +v0x11b67d0_0 .net "sum", 0 0, L_0x1317fb0; alias, 1 drivers +S_0x11b6900 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11b6100; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e84a40/d .functor XOR 1, L_0x1e84820, L_0x1e83ba0, C4<0>, C4<0>; -L_0x1e84a40 .delay 1 (30000,30000,30000) L_0x1e84a40/d; -L_0x1d24710/d .functor AND 1, L_0x1e84820, L_0x1e83ba0, C4<1>, C4<1>; -L_0x1d24710 .delay 1 (30000,30000,30000) L_0x1d24710/d; -v0x1d23f10_0 .net "a", 0 0, L_0x1e84820; alias, 1 drivers -v0x1d23fe0_0 .net "b", 0 0, L_0x1e83ba0; alias, 1 drivers -v0x1d24080_0 .net "carryout", 0 0, L_0x1d24710; alias, 1 drivers -v0x1d24150_0 .net "sum", 0 0, L_0x1e84a40; alias, 1 drivers -S_0x1d25d00 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d15f70; - .timescale -9 -12; -L_0x7f72592dbf98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dbfe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e8d720/d .functor OR 1, L_0x7f72592dbf98, L_0x7f72592dbfe0, C4<0>, C4<0>; -L_0x1e8d720 .delay 1 (30000,30000,30000) L_0x1e8d720/d; -v0x1d25ef0_0 .net/2u *"_s0", 0 0, L_0x7f72592dbf98; 1 drivers -v0x1d25fd0_0 .net/2u *"_s2", 0 0, L_0x7f72592dbfe0; 1 drivers -S_0x1d260b0 .scope generate, "alu_slices[29]" "alu_slices[29]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1d262c0 .param/l "i" 0 3 37, +C4<011101>; -S_0x1d26380 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d260b0; +L_0x13181d0/d .functor XOR 1, L_0x1317fb0, L_0x13172c0, C4<0>, C4<0>; +L_0x13181d0 .delay 1 (30000,30000,30000) L_0x13181d0/d; +L_0x11b7360/d .functor AND 1, L_0x1317fb0, L_0x13172c0, C4<1>, C4<1>; +L_0x11b7360 .delay 1 (30000,30000,30000) L_0x11b7360/d; +v0x11b6b60_0 .net "a", 0 0, L_0x1317fb0; alias, 1 drivers +v0x11b6c30_0 .net "b", 0 0, L_0x13172c0; alias, 1 drivers +v0x11b6cd0_0 .net "carryout", 0 0, L_0x11b7360; alias, 1 drivers +v0x11b6da0_0 .net "sum", 0 0, L_0x13181d0; alias, 1 drivers +S_0x11b8950 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11a8bf0; + .timescale -9 -12; +L_0x2b0ab3d06f98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d06fe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1320f40/d .functor OR 1, L_0x2b0ab3d06f98, L_0x2b0ab3d06fe0, C4<0>, C4<0>; +L_0x1320f40 .delay 1 (30000,30000,30000) L_0x1320f40/d; +v0x11b8b40_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06f98; 1 drivers +v0x11b8c20_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06fe0; 1 drivers +S_0x11b8d00 .scope generate, "alu_slices[29]" "alu_slices[29]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11b8f10 .param/l "i" 0 3 41, +C4<011101>; +S_0x11b8fd0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11b8d00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -15566,445 +15576,445 @@ S_0x1d26380 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d260b0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e83ce0/d .functor NOT 1, L_0x1e97290, C4<0>, C4<0>, C4<0>; -L_0x1e83ce0 .delay 1 (10000,10000,10000) L_0x1e83ce0/d; -L_0x1e8db90/d .functor NOT 1, L_0x1e8d880, C4<0>, C4<0>, C4<0>; -L_0x1e8db90 .delay 1 (10000,10000,10000) L_0x1e8db90/d; -L_0x1e8ebe0/d .functor XOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; -L_0x1e8ebe0 .delay 1 (30000,30000,30000) L_0x1e8ebe0/d; -L_0x7f72592dc028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dc070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e8f290/d .functor OR 1, L_0x7f72592dc028, L_0x7f72592dc070, C4<0>, C4<0>; -L_0x1e8f290 .delay 1 (30000,30000,30000) L_0x1e8f290/d; -L_0x1e8f490/d .functor AND 1, L_0x1e97290, L_0x1e8d880, C4<1>, C4<1>; -L_0x1e8f490 .delay 1 (30000,30000,30000) L_0x1e8f490/d; -L_0x1e8f550/d .functor NAND 1, L_0x1e97290, L_0x1e8d880, C4<1>, C4<1>; -L_0x1e8f550 .delay 1 (20000,20000,20000) L_0x1e8f550/d; -L_0x1e8f6b0/d .functor XOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; -L_0x1e8f6b0 .delay 1 (20000,20000,20000) L_0x1e8f6b0/d; -L_0x1e8fb60/d .functor OR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; -L_0x1e8fb60 .delay 1 (30000,30000,30000) L_0x1e8fb60/d; -L_0x1e97190/d .functor NOT 1, L_0x1e933f0, C4<0>, C4<0>, C4<0>; -L_0x1e97190 .delay 1 (10000,10000,10000) L_0x1e97190/d; -v0x1d34ab0_0 .net "A", 0 0, L_0x1e97290; 1 drivers -v0x1d34b70_0 .net "A_", 0 0, L_0x1e83ce0; 1 drivers -v0x1d34c30_0 .net "B", 0 0, L_0x1e8d880; 1 drivers -v0x1d34d00_0 .net "B_", 0 0, L_0x1e8db90; 1 drivers -v0x1d34da0_0 .net *"_s12", 0 0, L_0x1e8f290; 1 drivers -v0x1d34e90_0 .net/2s *"_s14", 0 0, L_0x7f72592dc028; 1 drivers -v0x1d34f50_0 .net/2s *"_s16", 0 0, L_0x7f72592dc070; 1 drivers -v0x1d35030_0 .net *"_s18", 0 0, L_0x1e8f490; 1 drivers -v0x1d35110_0 .net *"_s20", 0 0, L_0x1e8f550; 1 drivers -v0x1d35280_0 .net *"_s22", 0 0, L_0x1e8f6b0; 1 drivers -v0x1d35360_0 .net *"_s24", 0 0, L_0x1e8fb60; 1 drivers -o0x7f7259338cd8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1d35440_0 name=_s30 -o0x7f7259338d08 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1d35520_0 name=_s32 -v0x1d35600_0 .net *"_s8", 0 0, L_0x1e8ebe0; 1 drivers -v0x1d356e0_0 .net "carryin", 0 0, L_0x1e8d920; 1 drivers -v0x1d35780_0 .net "carryout", 0 0, L_0x1e96e30; 1 drivers -v0x1d35820_0 .net "carryouts", 7 0, L_0x1ec1d80; 1 drivers -v0x1d359d0_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d35a70_0 .net "result", 0 0, L_0x1e933f0; 1 drivers -v0x1d35b60_0 .net "results", 7 0, L_0x1e8f930; 1 drivers -v0x1d35c70_0 .net "zero", 0 0, L_0x1e97190; 1 drivers -LS_0x1e8f930_0_0 .concat8 [ 1 1 1 1], L_0x1e8e0b0, L_0x1e8e6e0, L_0x1e8ebe0, L_0x1e8f290; -LS_0x1e8f930_0_4 .concat8 [ 1 1 1 1], L_0x1e8f490, L_0x1e8f550, L_0x1e8f6b0, L_0x1e8fb60; -L_0x1e8f930 .concat8 [ 4 4 0 0], LS_0x1e8f930_0_0, LS_0x1e8f930_0_4; -LS_0x1ec1d80_0_0 .concat [ 1 1 1 1], L_0x1e8e360, L_0x1e8ea80, o0x7f7259338cd8, L_0x1e8f0e0; -LS_0x1ec1d80_0_4 .concat [ 4 0 0 0], o0x7f7259338d08; -L_0x1ec1d80 .concat [ 4 4 0 0], LS_0x1ec1d80_0_0, LS_0x1ec1d80_0_4; -S_0x1d26600 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d26380; +L_0x1317400/d .functor NOT 1, L_0x132ab70, C4<0>, C4<0>, C4<0>; +L_0x1317400 .delay 1 (10000,10000,10000) L_0x1317400/d; +L_0x13213b0/d .functor NOT 1, L_0x13210a0, C4<0>, C4<0>, C4<0>; +L_0x13213b0 .delay 1 (10000,10000,10000) L_0x13213b0/d; +L_0x13222a0/d .functor XOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; +L_0x13222a0 .delay 1 (30000,30000,30000) L_0x13222a0/d; +L_0x2b0ab3d07028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d07070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1322950/d .functor OR 1, L_0x2b0ab3d07028, L_0x2b0ab3d07070, C4<0>, C4<0>; +L_0x1322950 .delay 1 (30000,30000,30000) L_0x1322950/d; +L_0x1322b50/d .functor AND 1, L_0x132ab70, L_0x13210a0, C4<1>, C4<1>; +L_0x1322b50 .delay 1 (30000,30000,30000) L_0x1322b50/d; +L_0x1322c60/d .functor NAND 1, L_0x132ab70, L_0x13210a0, C4<1>, C4<1>; +L_0x1322c60 .delay 1 (20000,20000,20000) L_0x1322c60/d; +L_0x1322dc0/d .functor XOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; +L_0x1322dc0 .delay 1 (20000,20000,20000) L_0x1322dc0/d; +L_0x1323270/d .functor OR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; +L_0x1323270 .delay 1 (30000,30000,30000) L_0x1323270/d; +L_0x132aa70/d .functor NOT 1, L_0x1326c10, C4<0>, C4<0>, C4<0>; +L_0x132aa70 .delay 1 (10000,10000,10000) L_0x132aa70/d; +v0x11c7700_0 .net "A", 0 0, L_0x132ab70; 1 drivers +v0x11c77c0_0 .net "A_", 0 0, L_0x1317400; 1 drivers +v0x11c7880_0 .net "B", 0 0, L_0x13210a0; 1 drivers +v0x11c7950_0 .net "B_", 0 0, L_0x13213b0; 1 drivers +v0x11c79f0_0 .net *"_s12", 0 0, L_0x1322950; 1 drivers +v0x11c7ae0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d07028; 1 drivers +v0x11c7ba0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d07070; 1 drivers +v0x11c7c80_0 .net *"_s18", 0 0, L_0x1322b50; 1 drivers +v0x11c7d60_0 .net *"_s20", 0 0, L_0x1322c60; 1 drivers +v0x11c7ed0_0 .net *"_s22", 0 0, L_0x1322dc0; 1 drivers +v0x11c7fb0_0 .net *"_s24", 0 0, L_0x1323270; 1 drivers +o0x2b0ab3ce9cd8 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x11c8090_0 name=_s30 +o0x2b0ab3ce9d08 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x11c8170_0 name=_s32 +v0x11c8250_0 .net *"_s8", 0 0, L_0x13222a0; 1 drivers +v0x11c8330_0 .net "carryin", 0 0, L_0x1321140; 1 drivers +v0x11c83d0_0 .net "carryout", 0 0, L_0x132a710; 1 drivers +v0x11c8470_0 .net "carryouts", 7 0, L_0x13560b0; 1 drivers +v0x11c8620_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11c86c0_0 .net "result", 0 0, L_0x1326c10; 1 drivers +v0x11c87b0_0 .net "results", 7 0, L_0x1323040; 1 drivers +v0x11c88c0_0 .net "zero", 0 0, L_0x132aa70; 1 drivers +LS_0x1323040_0_0 .concat8 [ 1 1 1 1], L_0x1321770, L_0x1321df0, L_0x13222a0, L_0x1322950; +LS_0x1323040_0_4 .concat8 [ 1 1 1 1], L_0x1322b50, L_0x1322c60, L_0x1322dc0, L_0x1323270; +L_0x1323040 .concat8 [ 4 4 0 0], LS_0x1323040_0_0, LS_0x1323040_0_4; +LS_0x13560b0_0_0 .concat [ 1 1 1 1], L_0x1321a70, L_0x1322140, o0x2b0ab3ce9cd8, L_0x13227a0; +LS_0x13560b0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce9d08; +L_0x13560b0 .concat [ 4 4 0 0], LS_0x13560b0_0_0, LS_0x13560b0_0_4; +S_0x11b9250 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11b8fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e8e360/d .functor OR 1, L_0x1e8de40, L_0x1e8e200, C4<0>, C4<0>; -L_0x1e8e360 .delay 1 (30000,30000,30000) L_0x1e8e360/d; -v0x1d27430_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers -v0x1d274f0_0 .net "b", 0 0, L_0x1e8d880; alias, 1 drivers -v0x1d275c0_0 .net "c1", 0 0, L_0x1e8de40; 1 drivers -v0x1d276c0_0 .net "c2", 0 0, L_0x1e8e200; 1 drivers -v0x1d27790_0 .net "carryin", 0 0, L_0x1e8d920; alias, 1 drivers -v0x1d27880_0 .net "carryout", 0 0, L_0x1e8e360; 1 drivers -v0x1d27920_0 .net "s1", 0 0, L_0x1e8dd80; 1 drivers -v0x1d27a10_0 .net "sum", 0 0, L_0x1e8e0b0; 1 drivers -S_0x1d26870 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d26600; +L_0x1321a70/d .functor OR 1, L_0x13215a0, L_0x1321960, C4<0>, C4<0>; +L_0x1321a70 .delay 1 (30000,30000,30000) L_0x1321a70/d; +v0x11ba080_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers +v0x11ba140_0 .net "b", 0 0, L_0x13210a0; alias, 1 drivers +v0x11ba210_0 .net "c1", 0 0, L_0x13215a0; 1 drivers +v0x11ba310_0 .net "c2", 0 0, L_0x1321960; 1 drivers +v0x11ba3e0_0 .net "carryin", 0 0, L_0x1321140; alias, 1 drivers +v0x11ba4d0_0 .net "carryout", 0 0, L_0x1321a70; 1 drivers +v0x11ba570_0 .net "s1", 0 0, L_0x131aef0; 1 drivers +v0x11ba660_0 .net "sum", 0 0, L_0x1321770; 1 drivers +S_0x11b94c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11b9250; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e8dd80/d .functor XOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; -L_0x1e8dd80 .delay 1 (30000,30000,30000) L_0x1e8dd80/d; -L_0x1e8de40/d .functor AND 1, L_0x1e97290, L_0x1e8d880, C4<1>, C4<1>; -L_0x1e8de40 .delay 1 (30000,30000,30000) L_0x1e8de40/d; -v0x1d26ad0_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers -v0x1d26bb0_0 .net "b", 0 0, L_0x1e8d880; alias, 1 drivers -v0x1d26c70_0 .net "carryout", 0 0, L_0x1e8de40; alias, 1 drivers -v0x1d26d10_0 .net "sum", 0 0, L_0x1e8dd80; alias, 1 drivers -S_0x1d26e50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d26600; +L_0x131aef0/d .functor XOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; +L_0x131aef0 .delay 1 (30000,30000,30000) L_0x131aef0/d; +L_0x13215a0/d .functor AND 1, L_0x132ab70, L_0x13210a0, C4<1>, C4<1>; +L_0x13215a0 .delay 1 (30000,30000,30000) L_0x13215a0/d; +v0x11b9720_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers +v0x11b9800_0 .net "b", 0 0, L_0x13210a0; alias, 1 drivers +v0x11b98c0_0 .net "carryout", 0 0, L_0x13215a0; alias, 1 drivers +v0x11b9960_0 .net "sum", 0 0, L_0x131aef0; alias, 1 drivers +S_0x11b9aa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11b9250; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e8e0b0/d .functor XOR 1, L_0x1e8dd80, L_0x1e8d920, C4<0>, C4<0>; -L_0x1e8e0b0 .delay 1 (30000,30000,30000) L_0x1e8e0b0/d; -L_0x1e8e200/d .functor AND 1, L_0x1e8dd80, L_0x1e8d920, C4<1>, C4<1>; -L_0x1e8e200 .delay 1 (30000,30000,30000) L_0x1e8e200/d; -v0x1d270b0_0 .net "a", 0 0, L_0x1e8dd80; alias, 1 drivers -v0x1d27150_0 .net "b", 0 0, L_0x1e8d920; alias, 1 drivers -v0x1d271f0_0 .net "carryout", 0 0, L_0x1e8e200; alias, 1 drivers -v0x1d272c0_0 .net "sum", 0 0, L_0x1e8e0b0; alias, 1 drivers -S_0x1d27ae0 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d26380; +L_0x1321770/d .functor XOR 1, L_0x131aef0, L_0x1321140, C4<0>, C4<0>; +L_0x1321770 .delay 1 (30000,30000,30000) L_0x1321770/d; +L_0x1321960/d .functor AND 1, L_0x131aef0, L_0x1321140, C4<1>, C4<1>; +L_0x1321960 .delay 1 (30000,30000,30000) L_0x1321960/d; +v0x11b9d00_0 .net "a", 0 0, L_0x131aef0; alias, 1 drivers +v0x11b9da0_0 .net "b", 0 0, L_0x1321140; alias, 1 drivers +v0x11b9e40_0 .net "carryout", 0 0, L_0x1321960; alias, 1 drivers +v0x11b9f10_0 .net "sum", 0 0, L_0x1321770; alias, 1 drivers +S_0x11ba730 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11b8fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d2ced0_0 .net "ands", 7 0, L_0x1e94e30; 1 drivers -v0x1d2cfe0_0 .net "in", 7 0, L_0x1ec1d80; alias, 1 drivers -v0x1d2d0a0_0 .net "out", 0 0, L_0x1e96e30; alias, 1 drivers -v0x1d2d170_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d27d00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d27ae0; +v0x11bfb20_0 .net "ands", 7 0, L_0x1328710; 1 drivers +v0x11bfc30_0 .net "in", 7 0, L_0x13560b0; alias, 1 drivers +v0x11bfcf0_0 .net "out", 0 0, L_0x132a710; alias, 1 drivers +v0x11bfdc0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11ba950 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11ba730; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d2a430_0 .net "A", 7 0, L_0x1ec1d80; alias, 1 drivers -v0x1d2a530_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d2a5f0_0 .net *"_s0", 0 0, L_0x1e93750; 1 drivers -v0x1d2a6b0_0 .net *"_s12", 0 0, L_0x1e940c0; 1 drivers -v0x1d2a790_0 .net *"_s16", 0 0, L_0x1e94420; 1 drivers -v0x1d2a8c0_0 .net *"_s20", 0 0, L_0x1e94730; 1 drivers -v0x1d2a9a0_0 .net *"_s24", 0 0, L_0x1e94b20; 1 drivers -v0x1d2aa80_0 .net *"_s28", 0 0, L_0x1e94ab0; 1 drivers -v0x1d2ab60_0 .net *"_s4", 0 0, L_0x1e93a60; 1 drivers -v0x1d2acd0_0 .net *"_s8", 0 0, L_0x1e93db0; 1 drivers -v0x1d2adb0_0 .net "out", 7 0, L_0x1e94e30; alias, 1 drivers -L_0x1e93810 .part L_0x1ec1d80, 0, 1; -L_0x1e93970 .part v0x1d6daa0_0, 0, 1; -L_0x1e93b20 .part L_0x1ec1d80, 1, 1; -L_0x1e93d10 .part v0x1d6daa0_0, 1, 1; -L_0x1e93e70 .part L_0x1ec1d80, 2, 1; -L_0x1e93fd0 .part v0x1d6daa0_0, 2, 1; -L_0x1e94180 .part L_0x1ec1d80, 3, 1; -L_0x1e942e0 .part v0x1d6daa0_0, 3, 1; -L_0x1e944e0 .part L_0x1ec1d80, 4, 1; -L_0x1e94640 .part v0x1d6daa0_0, 4, 1; -L_0x1e947a0 .part L_0x1ec1d80, 5, 1; -L_0x1e94a10 .part v0x1d6daa0_0, 5, 1; -L_0x1e94be0 .part L_0x1ec1d80, 6, 1; -L_0x1e94d40 .part v0x1d6daa0_0, 6, 1; -LS_0x1e94e30_0_0 .concat8 [ 1 1 1 1], L_0x1e93750, L_0x1e93a60, L_0x1e93db0, L_0x1e940c0; -LS_0x1e94e30_0_4 .concat8 [ 1 1 1 1], L_0x1e94420, L_0x1e94730, L_0x1e94b20, L_0x1e94ab0; -L_0x1e94e30 .concat8 [ 4 4 0 0], LS_0x1e94e30_0_0, LS_0x1e94e30_0_4; -L_0x1e951f0 .part L_0x1ec1d80, 7, 1; -L_0x1e953e0 .part v0x1d6daa0_0, 7, 1; -S_0x1d27f60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d28170 .param/l "i" 0 4 54, +C4<00>; -L_0x1e93750/d .functor AND 1, L_0x1e93810, L_0x1e93970, C4<1>, C4<1>; -L_0x1e93750 .delay 1 (30000,30000,30000) L_0x1e93750/d; -v0x1d28250_0 .net *"_s0", 0 0, L_0x1e93810; 1 drivers -v0x1d28330_0 .net *"_s1", 0 0, L_0x1e93970; 1 drivers -S_0x1d28410 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d28620 .param/l "i" 0 4 54, +C4<01>; -L_0x1e93a60/d .functor AND 1, L_0x1e93b20, L_0x1e93d10, C4<1>, C4<1>; -L_0x1e93a60 .delay 1 (30000,30000,30000) L_0x1e93a60/d; -v0x1d286e0_0 .net *"_s0", 0 0, L_0x1e93b20; 1 drivers -v0x1d287c0_0 .net *"_s1", 0 0, L_0x1e93d10; 1 drivers -S_0x1d288a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d28ab0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e93db0/d .functor AND 1, L_0x1e93e70, L_0x1e93fd0, C4<1>, C4<1>; -L_0x1e93db0 .delay 1 (30000,30000,30000) L_0x1e93db0/d; -v0x1d28b50_0 .net *"_s0", 0 0, L_0x1e93e70; 1 drivers -v0x1d28c30_0 .net *"_s1", 0 0, L_0x1e93fd0; 1 drivers -S_0x1d28d10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d28f20 .param/l "i" 0 4 54, +C4<011>; -L_0x1e940c0/d .functor AND 1, L_0x1e94180, L_0x1e942e0, C4<1>, C4<1>; -L_0x1e940c0 .delay 1 (30000,30000,30000) L_0x1e940c0/d; -v0x1d28fe0_0 .net *"_s0", 0 0, L_0x1e94180; 1 drivers -v0x1d290c0_0 .net *"_s1", 0 0, L_0x1e942e0; 1 drivers -S_0x1d291a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d29400 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e94420/d .functor AND 1, L_0x1e944e0, L_0x1e94640, C4<1>, C4<1>; -L_0x1e94420 .delay 1 (30000,30000,30000) L_0x1e94420/d; -v0x1d294c0_0 .net *"_s0", 0 0, L_0x1e944e0; 1 drivers -v0x1d295a0_0 .net *"_s1", 0 0, L_0x1e94640; 1 drivers -S_0x1d29680 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d29890 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e94730/d .functor AND 1, L_0x1e947a0, L_0x1e94a10, C4<1>, C4<1>; -L_0x1e94730 .delay 1 (30000,30000,30000) L_0x1e94730/d; -v0x1d29950_0 .net *"_s0", 0 0, L_0x1e947a0; 1 drivers -v0x1d29a30_0 .net *"_s1", 0 0, L_0x1e94a10; 1 drivers -S_0x1d29b10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d29d20 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e94b20/d .functor AND 1, L_0x1e94be0, L_0x1e94d40, C4<1>, C4<1>; -L_0x1e94b20 .delay 1 (30000,30000,30000) L_0x1e94b20/d; -v0x1d29de0_0 .net *"_s0", 0 0, L_0x1e94be0; 1 drivers -v0x1d29ec0_0 .net *"_s1", 0 0, L_0x1e94d40; 1 drivers -S_0x1d29fa0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d27d00; - .timescale -9 -12; -P_0x1d2a1b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e94ab0/d .functor AND 1, L_0x1e951f0, L_0x1e953e0, C4<1>, C4<1>; -L_0x1e94ab0 .delay 1 (30000,30000,30000) L_0x1e94ab0/d; -v0x1d2a270_0 .net *"_s0", 0 0, L_0x1e951f0; 1 drivers -v0x1d2a350_0 .net *"_s1", 0 0, L_0x1e953e0; 1 drivers -S_0x1d2af10 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d27ae0; +v0x11bd080_0 .net "A", 7 0, L_0x13560b0; alias, 1 drivers +v0x11bd180_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11bd240_0 .net *"_s0", 0 0, L_0x1326f70; 1 drivers +v0x11bd300_0 .net *"_s12", 0 0, L_0x1327940; 1 drivers +v0x11bd3e0_0 .net *"_s16", 0 0, L_0x1327ca0; 1 drivers +v0x11bd510_0 .net *"_s20", 0 0, L_0x1327fe0; 1 drivers +v0x11bd5f0_0 .net *"_s24", 0 0, L_0x1328400; 1 drivers +v0x11bd6d0_0 .net *"_s28", 0 0, L_0x1328390; 1 drivers +v0x11bd7b0_0 .net *"_s4", 0 0, L_0x1327280; 1 drivers +v0x11bd920_0 .net *"_s8", 0 0, L_0x13275d0; 1 drivers +v0x11bda00_0 .net "out", 7 0, L_0x1328710; alias, 1 drivers +L_0x1327030 .part L_0x13560b0, 0, 1; +L_0x1327190 .part v0x12010b0_0, 0, 1; +L_0x1327340 .part L_0x13560b0, 1, 1; +L_0x1327530 .part v0x12010b0_0, 1, 1; +L_0x13276f0 .part L_0x13560b0, 2, 1; +L_0x1327850 .part v0x12010b0_0, 2, 1; +L_0x1327a00 .part L_0x13560b0, 3, 1; +L_0x1327b60 .part v0x12010b0_0, 3, 1; +L_0x1327d90 .part L_0x13560b0, 4, 1; +L_0x1327ef0 .part v0x12010b0_0, 4, 1; +L_0x1328080 .part L_0x13560b0, 5, 1; +L_0x13282f0 .part v0x12010b0_0, 5, 1; +L_0x13284c0 .part L_0x13560b0, 6, 1; +L_0x1328620 .part v0x12010b0_0, 6, 1; +LS_0x1328710_0_0 .concat8 [ 1 1 1 1], L_0x1326f70, L_0x1327280, L_0x13275d0, L_0x1327940; +LS_0x1328710_0_4 .concat8 [ 1 1 1 1], L_0x1327ca0, L_0x1327fe0, L_0x1328400, L_0x1328390; +L_0x1328710 .concat8 [ 4 4 0 0], LS_0x1328710_0_0, LS_0x1328710_0_4; +L_0x1328ad0 .part L_0x13560b0, 7, 1; +L_0x1328cc0 .part v0x12010b0_0, 7, 1; +S_0x11babb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11badc0 .param/l "i" 0 4 54, +C4<00>; +L_0x1326f70/d .functor AND 1, L_0x1327030, L_0x1327190, C4<1>, C4<1>; +L_0x1326f70 .delay 1 (30000,30000,30000) L_0x1326f70/d; +v0x11baea0_0 .net *"_s0", 0 0, L_0x1327030; 1 drivers +v0x11baf80_0 .net *"_s1", 0 0, L_0x1327190; 1 drivers +S_0x11bb060 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bb270 .param/l "i" 0 4 54, +C4<01>; +L_0x1327280/d .functor AND 1, L_0x1327340, L_0x1327530, C4<1>, C4<1>; +L_0x1327280 .delay 1 (30000,30000,30000) L_0x1327280/d; +v0x11bb330_0 .net *"_s0", 0 0, L_0x1327340; 1 drivers +v0x11bb410_0 .net *"_s1", 0 0, L_0x1327530; 1 drivers +S_0x11bb4f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bb700 .param/l "i" 0 4 54, +C4<010>; +L_0x13275d0/d .functor AND 1, L_0x13276f0, L_0x1327850, C4<1>, C4<1>; +L_0x13275d0 .delay 1 (30000,30000,30000) L_0x13275d0/d; +v0x11bb7a0_0 .net *"_s0", 0 0, L_0x13276f0; 1 drivers +v0x11bb880_0 .net *"_s1", 0 0, L_0x1327850; 1 drivers +S_0x11bb960 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bbb70 .param/l "i" 0 4 54, +C4<011>; +L_0x1327940/d .functor AND 1, L_0x1327a00, L_0x1327b60, C4<1>, C4<1>; +L_0x1327940 .delay 1 (30000,30000,30000) L_0x1327940/d; +v0x11bbc30_0 .net *"_s0", 0 0, L_0x1327a00; 1 drivers +v0x11bbd10_0 .net *"_s1", 0 0, L_0x1327b60; 1 drivers +S_0x11bbdf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bc050 .param/l "i" 0 4 54, +C4<0100>; +L_0x1327ca0/d .functor AND 1, L_0x1327d90, L_0x1327ef0, C4<1>, C4<1>; +L_0x1327ca0 .delay 1 (30000,30000,30000) L_0x1327ca0/d; +v0x11bc110_0 .net *"_s0", 0 0, L_0x1327d90; 1 drivers +v0x11bc1f0_0 .net *"_s1", 0 0, L_0x1327ef0; 1 drivers +S_0x11bc2d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bc4e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1327fe0/d .functor AND 1, L_0x1328080, L_0x13282f0, C4<1>, C4<1>; +L_0x1327fe0 .delay 1 (30000,30000,30000) L_0x1327fe0/d; +v0x11bc5a0_0 .net *"_s0", 0 0, L_0x1328080; 1 drivers +v0x11bc680_0 .net *"_s1", 0 0, L_0x13282f0; 1 drivers +S_0x11bc760 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bc970 .param/l "i" 0 4 54, +C4<0110>; +L_0x1328400/d .functor AND 1, L_0x13284c0, L_0x1328620, C4<1>, C4<1>; +L_0x1328400 .delay 1 (30000,30000,30000) L_0x1328400/d; +v0x11bca30_0 .net *"_s0", 0 0, L_0x13284c0; 1 drivers +v0x11bcb10_0 .net *"_s1", 0 0, L_0x1328620; 1 drivers +S_0x11bcbf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11ba950; + .timescale -9 -12; +P_0x11bce00 .param/l "i" 0 4 54, +C4<0111>; +L_0x1328390/d .functor AND 1, L_0x1328ad0, L_0x1328cc0, C4<1>, C4<1>; +L_0x1328390 .delay 1 (30000,30000,30000) L_0x1328390/d; +v0x11bcec0_0 .net *"_s0", 0 0, L_0x1328ad0; 1 drivers +v0x11bcfa0_0 .net *"_s1", 0 0, L_0x1328cc0; 1 drivers +S_0x11bdb60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11ba730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e96e30/d .functor OR 1, L_0x1e96ef0, L_0x1e970a0, C4<0>, C4<0>; -L_0x1e96e30 .delay 1 (30000,30000,30000) L_0x1e96e30/d; -v0x1d2ca60_0 .net *"_s10", 0 0, L_0x1e96ef0; 1 drivers -v0x1d2cb40_0 .net *"_s12", 0 0, L_0x1e970a0; 1 drivers -v0x1d2cc20_0 .net "in", 7 0, L_0x1e94e30; alias, 1 drivers -v0x1d2ccf0_0 .net "ors", 1 0, L_0x1e96c50; 1 drivers -v0x1d2cdb0_0 .net "out", 0 0, L_0x1e96e30; alias, 1 drivers -L_0x1e96020 .part L_0x1e94e30, 0, 4; -L_0x1e96c50 .concat8 [ 1 1 0 0], L_0x1e95d10, L_0x1e96940; -L_0x1e96d90 .part L_0x1e94e30, 4, 4; -L_0x1e96ef0 .part L_0x1e96c50, 0, 1; -L_0x1e970a0 .part L_0x1e96c50, 1, 1; -S_0x1d2b0d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d2af10; +L_0x132a710/d .functor OR 1, L_0x132a7d0, L_0x132a980, C4<0>, C4<0>; +L_0x132a710 .delay 1 (30000,30000,30000) L_0x132a710/d; +v0x11bf6b0_0 .net *"_s10", 0 0, L_0x132a7d0; 1 drivers +v0x11bf790_0 .net *"_s12", 0 0, L_0x132a980; 1 drivers +v0x11bf870_0 .net "in", 7 0, L_0x1328710; alias, 1 drivers +v0x11bf940_0 .net "ors", 1 0, L_0x132a530; 1 drivers +v0x11bfa00_0 .net "out", 0 0, L_0x132a710; alias, 1 drivers +L_0x1329900 .part L_0x1328710, 0, 4; +L_0x132a530 .concat8 [ 1 1 0 0], L_0x13295f0, L_0x132a220; +L_0x132a670 .part L_0x1328710, 4, 4; +L_0x132a7d0 .part L_0x132a530, 0, 1; +L_0x132a980 .part L_0x132a530, 1, 1; +S_0x11bdd20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11bdb60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e954d0/d .functor OR 1, L_0x1e95590, L_0x1e956f0, C4<0>, C4<0>; -L_0x1e954d0 .delay 1 (30000,30000,30000) L_0x1e954d0/d; -L_0x1e95920/d .functor OR 1, L_0x1e95a30, L_0x1e95b90, C4<0>, C4<0>; -L_0x1e95920 .delay 1 (30000,30000,30000) L_0x1e95920/d; -L_0x1e95d10/d .functor OR 1, L_0x1e95d80, L_0x1e95f30, C4<0>, C4<0>; -L_0x1e95d10 .delay 1 (30000,30000,30000) L_0x1e95d10/d; -v0x1d2b320_0 .net *"_s0", 0 0, L_0x1e954d0; 1 drivers -v0x1d2b420_0 .net *"_s10", 0 0, L_0x1e95a30; 1 drivers -v0x1d2b500_0 .net *"_s12", 0 0, L_0x1e95b90; 1 drivers -v0x1d2b5c0_0 .net *"_s14", 0 0, L_0x1e95d80; 1 drivers -v0x1d2b6a0_0 .net *"_s16", 0 0, L_0x1e95f30; 1 drivers -v0x1d2b7d0_0 .net *"_s3", 0 0, L_0x1e95590; 1 drivers -v0x1d2b8b0_0 .net *"_s5", 0 0, L_0x1e956f0; 1 drivers -v0x1d2b990_0 .net *"_s6", 0 0, L_0x1e95920; 1 drivers -v0x1d2ba70_0 .net "in", 3 0, L_0x1e96020; 1 drivers -v0x1d2bbe0_0 .net "ors", 1 0, L_0x1e95830; 1 drivers -v0x1d2bcc0_0 .net "out", 0 0, L_0x1e95d10; 1 drivers -L_0x1e95590 .part L_0x1e96020, 0, 1; -L_0x1e956f0 .part L_0x1e96020, 1, 1; -L_0x1e95830 .concat8 [ 1 1 0 0], L_0x1e954d0, L_0x1e95920; -L_0x1e95a30 .part L_0x1e96020, 2, 1; -L_0x1e95b90 .part L_0x1e96020, 3, 1; -L_0x1e95d80 .part L_0x1e95830, 0, 1; -L_0x1e95f30 .part L_0x1e95830, 1, 1; -S_0x1d2bde0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d2af10; +L_0x1328db0/d .functor OR 1, L_0x1328e70, L_0x1328fd0, C4<0>, C4<0>; +L_0x1328db0 .delay 1 (30000,30000,30000) L_0x1328db0/d; +L_0x1329200/d .functor OR 1, L_0x1329310, L_0x1329470, C4<0>, C4<0>; +L_0x1329200 .delay 1 (30000,30000,30000) L_0x1329200/d; +L_0x13295f0/d .functor OR 1, L_0x1329660, L_0x1329810, C4<0>, C4<0>; +L_0x13295f0 .delay 1 (30000,30000,30000) L_0x13295f0/d; +v0x11bdf70_0 .net *"_s0", 0 0, L_0x1328db0; 1 drivers +v0x11be070_0 .net *"_s10", 0 0, L_0x1329310; 1 drivers +v0x11be150_0 .net *"_s12", 0 0, L_0x1329470; 1 drivers +v0x11be210_0 .net *"_s14", 0 0, L_0x1329660; 1 drivers +v0x11be2f0_0 .net *"_s16", 0 0, L_0x1329810; 1 drivers +v0x11be420_0 .net *"_s3", 0 0, L_0x1328e70; 1 drivers +v0x11be500_0 .net *"_s5", 0 0, L_0x1328fd0; 1 drivers +v0x11be5e0_0 .net *"_s6", 0 0, L_0x1329200; 1 drivers +v0x11be6c0_0 .net "in", 3 0, L_0x1329900; 1 drivers +v0x11be830_0 .net "ors", 1 0, L_0x1329110; 1 drivers +v0x11be910_0 .net "out", 0 0, L_0x13295f0; 1 drivers +L_0x1328e70 .part L_0x1329900, 0, 1; +L_0x1328fd0 .part L_0x1329900, 1, 1; +L_0x1329110 .concat8 [ 1 1 0 0], L_0x1328db0, L_0x1329200; +L_0x1329310 .part L_0x1329900, 2, 1; +L_0x1329470 .part L_0x1329900, 3, 1; +L_0x1329660 .part L_0x1329110, 0, 1; +L_0x1329810 .part L_0x1329110, 1, 1; +S_0x11bea30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11bdb60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e96150/d .functor OR 1, L_0x1e961c0, L_0x1e96320, C4<0>, C4<0>; -L_0x1e96150 .delay 1 (30000,30000,30000) L_0x1e96150/d; -L_0x1e96550/d .functor OR 1, L_0x1e96660, L_0x1e967c0, C4<0>, C4<0>; -L_0x1e96550 .delay 1 (30000,30000,30000) L_0x1e96550/d; -L_0x1e96940/d .functor OR 1, L_0x1e969b0, L_0x1e96b60, C4<0>, C4<0>; -L_0x1e96940 .delay 1 (30000,30000,30000) L_0x1e96940/d; -v0x1d2bfa0_0 .net *"_s0", 0 0, L_0x1e96150; 1 drivers -v0x1d2c0a0_0 .net *"_s10", 0 0, L_0x1e96660; 1 drivers -v0x1d2c180_0 .net *"_s12", 0 0, L_0x1e967c0; 1 drivers -v0x1d2c240_0 .net *"_s14", 0 0, L_0x1e969b0; 1 drivers -v0x1d2c320_0 .net *"_s16", 0 0, L_0x1e96b60; 1 drivers -v0x1d2c450_0 .net *"_s3", 0 0, L_0x1e961c0; 1 drivers -v0x1d2c530_0 .net *"_s5", 0 0, L_0x1e96320; 1 drivers -v0x1d2c610_0 .net *"_s6", 0 0, L_0x1e96550; 1 drivers -v0x1d2c6f0_0 .net "in", 3 0, L_0x1e96d90; 1 drivers -v0x1d2c860_0 .net "ors", 1 0, L_0x1e96460; 1 drivers -v0x1d2c940_0 .net "out", 0 0, L_0x1e96940; 1 drivers -L_0x1e961c0 .part L_0x1e96d90, 0, 1; -L_0x1e96320 .part L_0x1e96d90, 1, 1; -L_0x1e96460 .concat8 [ 1 1 0 0], L_0x1e96150, L_0x1e96550; -L_0x1e96660 .part L_0x1e96d90, 2, 1; -L_0x1e967c0 .part L_0x1e96d90, 3, 1; -L_0x1e969b0 .part L_0x1e96460, 0, 1; -L_0x1e96b60 .part L_0x1e96460, 1, 1; -S_0x1d2d250 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d26380; +L_0x1329a30/d .functor OR 1, L_0x1329aa0, L_0x1329c00, C4<0>, C4<0>; +L_0x1329a30 .delay 1 (30000,30000,30000) L_0x1329a30/d; +L_0x1329e30/d .functor OR 1, L_0x1329f40, L_0x132a0a0, C4<0>, C4<0>; +L_0x1329e30 .delay 1 (30000,30000,30000) L_0x1329e30/d; +L_0x132a220/d .functor OR 1, L_0x132a290, L_0x132a440, C4<0>, C4<0>; +L_0x132a220 .delay 1 (30000,30000,30000) L_0x132a220/d; +v0x11bebf0_0 .net *"_s0", 0 0, L_0x1329a30; 1 drivers +v0x11becf0_0 .net *"_s10", 0 0, L_0x1329f40; 1 drivers +v0x11bedd0_0 .net *"_s12", 0 0, L_0x132a0a0; 1 drivers +v0x11bee90_0 .net *"_s14", 0 0, L_0x132a290; 1 drivers +v0x11bef70_0 .net *"_s16", 0 0, L_0x132a440; 1 drivers +v0x11bf0a0_0 .net *"_s3", 0 0, L_0x1329aa0; 1 drivers +v0x11bf180_0 .net *"_s5", 0 0, L_0x1329c00; 1 drivers +v0x11bf260_0 .net *"_s6", 0 0, L_0x1329e30; 1 drivers +v0x11bf340_0 .net "in", 3 0, L_0x132a670; 1 drivers +v0x11bf4b0_0 .net "ors", 1 0, L_0x1329d40; 1 drivers +v0x11bf590_0 .net "out", 0 0, L_0x132a220; 1 drivers +L_0x1329aa0 .part L_0x132a670, 0, 1; +L_0x1329c00 .part L_0x132a670, 1, 1; +L_0x1329d40 .concat8 [ 1 1 0 0], L_0x1329a30, L_0x1329e30; +L_0x1329f40 .part L_0x132a670, 2, 1; +L_0x132a0a0 .part L_0x132a670, 3, 1; +L_0x132a290 .part L_0x1329d40, 0, 1; +L_0x132a440 .part L_0x1329d40, 1, 1; +S_0x11bfea0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11b8fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d32680_0 .net "ands", 7 0, L_0x1e913f0; 1 drivers -v0x1d32790_0 .net "in", 7 0, L_0x1e8f930; alias, 1 drivers -v0x1d32850_0 .net "out", 0 0, L_0x1e933f0; alias, 1 drivers -v0x1d32920_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d2d4a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d2d250; +v0x11c52d0_0 .net "ands", 7 0, L_0x1324be0; 1 drivers +v0x11c53e0_0 .net "in", 7 0, L_0x1323040; alias, 1 drivers +v0x11c54a0_0 .net "out", 0 0, L_0x1326c10; alias, 1 drivers +v0x11c5570_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11c00f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11bfea0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d2fbe0_0 .net "A", 7 0, L_0x1e8f930; alias, 1 drivers -v0x1d2fce0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d2fda0_0 .net *"_s0", 0 0, L_0x1e8fcc0; 1 drivers -v0x1d2fe60_0 .net *"_s12", 0 0, L_0x1e90680; 1 drivers -v0x1d2ff40_0 .net *"_s16", 0 0, L_0x1e909e0; 1 drivers -v0x1d30070_0 .net *"_s20", 0 0, L_0x1e90db0; 1 drivers -v0x1d30150_0 .net *"_s24", 0 0, L_0x1e910e0; 1 drivers -v0x1d30230_0 .net *"_s28", 0 0, L_0x1e91070; 1 drivers -v0x1d30310_0 .net *"_s4", 0 0, L_0x1e90060; 1 drivers -v0x1d30480_0 .net *"_s8", 0 0, L_0x1e90370; 1 drivers -v0x1d30560_0 .net "out", 7 0, L_0x1e913f0; alias, 1 drivers -L_0x1e8fdd0 .part L_0x1e8f930, 0, 1; -L_0x1e8ffc0 .part v0x1d6daa0_0, 0, 1; -L_0x1e90120 .part L_0x1e8f930, 1, 1; -L_0x1e90280 .part v0x1d6daa0_0, 1, 1; -L_0x1e90430 .part L_0x1e8f930, 2, 1; -L_0x1e90590 .part v0x1d6daa0_0, 2, 1; -L_0x1e90740 .part L_0x1e8f930, 3, 1; -L_0x1e908a0 .part v0x1d6daa0_0, 3, 1; -L_0x1e90aa0 .part L_0x1e8f930, 4, 1; -L_0x1e90d10 .part v0x1d6daa0_0, 4, 1; -L_0x1e90e20 .part L_0x1e8f930, 5, 1; -L_0x1e90f80 .part v0x1d6daa0_0, 5, 1; -L_0x1e911a0 .part L_0x1e8f930, 6, 1; -L_0x1e91300 .part v0x1d6daa0_0, 6, 1; -LS_0x1e913f0_0_0 .concat8 [ 1 1 1 1], L_0x1e8fcc0, L_0x1e90060, L_0x1e90370, L_0x1e90680; -LS_0x1e913f0_0_4 .concat8 [ 1 1 1 1], L_0x1e909e0, L_0x1e90db0, L_0x1e910e0, L_0x1e91070; -L_0x1e913f0 .concat8 [ 4 4 0 0], LS_0x1e913f0_0_0, LS_0x1e913f0_0_4; -L_0x1e917b0 .part L_0x1e8f930, 7, 1; -L_0x1e919a0 .part v0x1d6daa0_0, 7, 1; -S_0x1d2d6e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2d8f0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e8fcc0/d .functor AND 1, L_0x1e8fdd0, L_0x1e8ffc0, C4<1>, C4<1>; -L_0x1e8fcc0 .delay 1 (30000,30000,30000) L_0x1e8fcc0/d; -v0x1d2d9d0_0 .net *"_s0", 0 0, L_0x1e8fdd0; 1 drivers -v0x1d2dab0_0 .net *"_s1", 0 0, L_0x1e8ffc0; 1 drivers -S_0x1d2db90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2dda0 .param/l "i" 0 4 54, +C4<01>; -L_0x1e90060/d .functor AND 1, L_0x1e90120, L_0x1e90280, C4<1>, C4<1>; -L_0x1e90060 .delay 1 (30000,30000,30000) L_0x1e90060/d; -v0x1d2de60_0 .net *"_s0", 0 0, L_0x1e90120; 1 drivers -v0x1d2df40_0 .net *"_s1", 0 0, L_0x1e90280; 1 drivers -S_0x1d2e020 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2e260 .param/l "i" 0 4 54, +C4<010>; -L_0x1e90370/d .functor AND 1, L_0x1e90430, L_0x1e90590, C4<1>, C4<1>; -L_0x1e90370 .delay 1 (30000,30000,30000) L_0x1e90370/d; -v0x1d2e300_0 .net *"_s0", 0 0, L_0x1e90430; 1 drivers -v0x1d2e3e0_0 .net *"_s1", 0 0, L_0x1e90590; 1 drivers -S_0x1d2e4c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2e6d0 .param/l "i" 0 4 54, +C4<011>; -L_0x1e90680/d .functor AND 1, L_0x1e90740, L_0x1e908a0, C4<1>, C4<1>; -L_0x1e90680 .delay 1 (30000,30000,30000) L_0x1e90680/d; -v0x1d2e790_0 .net *"_s0", 0 0, L_0x1e90740; 1 drivers -v0x1d2e870_0 .net *"_s1", 0 0, L_0x1e908a0; 1 drivers -S_0x1d2e950 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2ebb0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e909e0/d .functor AND 1, L_0x1e90aa0, L_0x1e90d10, C4<1>, C4<1>; -L_0x1e909e0 .delay 1 (30000,30000,30000) L_0x1e909e0/d; -v0x1d2ec70_0 .net *"_s0", 0 0, L_0x1e90aa0; 1 drivers -v0x1d2ed50_0 .net *"_s1", 0 0, L_0x1e90d10; 1 drivers -S_0x1d2ee30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2f040 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e90db0/d .functor AND 1, L_0x1e90e20, L_0x1e90f80, C4<1>, C4<1>; -L_0x1e90db0 .delay 1 (30000,30000,30000) L_0x1e90db0/d; -v0x1d2f100_0 .net *"_s0", 0 0, L_0x1e90e20; 1 drivers -v0x1d2f1e0_0 .net *"_s1", 0 0, L_0x1e90f80; 1 drivers -S_0x1d2f2c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2f4d0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e910e0/d .functor AND 1, L_0x1e911a0, L_0x1e91300, C4<1>, C4<1>; -L_0x1e910e0 .delay 1 (30000,30000,30000) L_0x1e910e0/d; -v0x1d2f590_0 .net *"_s0", 0 0, L_0x1e911a0; 1 drivers -v0x1d2f670_0 .net *"_s1", 0 0, L_0x1e91300; 1 drivers -S_0x1d2f750 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d2d4a0; - .timescale -9 -12; -P_0x1d2f960 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e91070/d .functor AND 1, L_0x1e917b0, L_0x1e919a0, C4<1>, C4<1>; -L_0x1e91070 .delay 1 (30000,30000,30000) L_0x1e91070/d; -v0x1d2fa20_0 .net *"_s0", 0 0, L_0x1e917b0; 1 drivers -v0x1d2fb00_0 .net *"_s1", 0 0, L_0x1e919a0; 1 drivers -S_0x1d306c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d2d250; +v0x11c2830_0 .net "A", 7 0, L_0x1323040; alias, 1 drivers +v0x11c2930_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11c29f0_0 .net *"_s0", 0 0, L_0x13233d0; 1 drivers +v0x11c2ab0_0 .net *"_s12", 0 0, L_0x1323d90; 1 drivers +v0x11c2b90_0 .net *"_s16", 0 0, L_0x13240f0; 1 drivers +v0x11c2cc0_0 .net *"_s20", 0 0, L_0x1324520; 1 drivers +v0x11c2da0_0 .net *"_s24", 0 0, L_0x1324850; 1 drivers +v0x11c2e80_0 .net *"_s28", 0 0, L_0x13247e0; 1 drivers +v0x11c2f60_0 .net *"_s4", 0 0, L_0x1323770; 1 drivers +v0x11c30d0_0 .net *"_s8", 0 0, L_0x1323a80; 1 drivers +v0x11c31b0_0 .net "out", 7 0, L_0x1324be0; alias, 1 drivers +L_0x13234e0 .part L_0x1323040, 0, 1; +L_0x13236d0 .part v0x12010b0_0, 0, 1; +L_0x1323830 .part L_0x1323040, 1, 1; +L_0x1323990 .part v0x12010b0_0, 1, 1; +L_0x1323b40 .part L_0x1323040, 2, 1; +L_0x1323ca0 .part v0x12010b0_0, 2, 1; +L_0x1323e50 .part L_0x1323040, 3, 1; +L_0x1323fb0 .part v0x12010b0_0, 3, 1; +L_0x13241b0 .part L_0x1323040, 4, 1; +L_0x1324420 .part v0x12010b0_0, 4, 1; +L_0x1324590 .part L_0x1323040, 5, 1; +L_0x13246f0 .part v0x12010b0_0, 5, 1; +L_0x1324910 .part L_0x1323040, 6, 1; +L_0x1324a70 .part v0x12010b0_0, 6, 1; +LS_0x1324be0_0_0 .concat8 [ 1 1 1 1], L_0x13233d0, L_0x1323770, L_0x1323a80, L_0x1323d90; +LS_0x1324be0_0_4 .concat8 [ 1 1 1 1], L_0x13240f0, L_0x1324520, L_0x1324850, L_0x13247e0; +L_0x1324be0 .concat8 [ 4 4 0 0], LS_0x1324be0_0_0, LS_0x1324be0_0_4; +L_0x1324fa0 .part L_0x1323040, 7, 1; +L_0x1325190 .part v0x12010b0_0, 7, 1; +S_0x11c0330 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c0540 .param/l "i" 0 4 54, +C4<00>; +L_0x13233d0/d .functor AND 1, L_0x13234e0, L_0x13236d0, C4<1>, C4<1>; +L_0x13233d0 .delay 1 (30000,30000,30000) L_0x13233d0/d; +v0x11c0620_0 .net *"_s0", 0 0, L_0x13234e0; 1 drivers +v0x11c0700_0 .net *"_s1", 0 0, L_0x13236d0; 1 drivers +S_0x11c07e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c09f0 .param/l "i" 0 4 54, +C4<01>; +L_0x1323770/d .functor AND 1, L_0x1323830, L_0x1323990, C4<1>, C4<1>; +L_0x1323770 .delay 1 (30000,30000,30000) L_0x1323770/d; +v0x11c0ab0_0 .net *"_s0", 0 0, L_0x1323830; 1 drivers +v0x11c0b90_0 .net *"_s1", 0 0, L_0x1323990; 1 drivers +S_0x11c0c70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c0eb0 .param/l "i" 0 4 54, +C4<010>; +L_0x1323a80/d .functor AND 1, L_0x1323b40, L_0x1323ca0, C4<1>, C4<1>; +L_0x1323a80 .delay 1 (30000,30000,30000) L_0x1323a80/d; +v0x11c0f50_0 .net *"_s0", 0 0, L_0x1323b40; 1 drivers +v0x11c1030_0 .net *"_s1", 0 0, L_0x1323ca0; 1 drivers +S_0x11c1110 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c1320 .param/l "i" 0 4 54, +C4<011>; +L_0x1323d90/d .functor AND 1, L_0x1323e50, L_0x1323fb0, C4<1>, C4<1>; +L_0x1323d90 .delay 1 (30000,30000,30000) L_0x1323d90/d; +v0x11c13e0_0 .net *"_s0", 0 0, L_0x1323e50; 1 drivers +v0x11c14c0_0 .net *"_s1", 0 0, L_0x1323fb0; 1 drivers +S_0x11c15a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c1800 .param/l "i" 0 4 54, +C4<0100>; +L_0x13240f0/d .functor AND 1, L_0x13241b0, L_0x1324420, C4<1>, C4<1>; +L_0x13240f0 .delay 1 (30000,30000,30000) L_0x13240f0/d; +v0x11c18c0_0 .net *"_s0", 0 0, L_0x13241b0; 1 drivers +v0x11c19a0_0 .net *"_s1", 0 0, L_0x1324420; 1 drivers +S_0x11c1a80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c1c90 .param/l "i" 0 4 54, +C4<0101>; +L_0x1324520/d .functor AND 1, L_0x1324590, L_0x13246f0, C4<1>, C4<1>; +L_0x1324520 .delay 1 (30000,30000,30000) L_0x1324520/d; +v0x11c1d50_0 .net *"_s0", 0 0, L_0x1324590; 1 drivers +v0x11c1e30_0 .net *"_s1", 0 0, L_0x13246f0; 1 drivers +S_0x11c1f10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c2120 .param/l "i" 0 4 54, +C4<0110>; +L_0x1324850/d .functor AND 1, L_0x1324910, L_0x1324a70, C4<1>, C4<1>; +L_0x1324850 .delay 1 (30000,30000,30000) L_0x1324850/d; +v0x11c21e0_0 .net *"_s0", 0 0, L_0x1324910; 1 drivers +v0x11c22c0_0 .net *"_s1", 0 0, L_0x1324a70; 1 drivers +S_0x11c23a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11c00f0; + .timescale -9 -12; +P_0x11c25b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x13247e0/d .functor AND 1, L_0x1324fa0, L_0x1325190, C4<1>, C4<1>; +L_0x13247e0 .delay 1 (30000,30000,30000) L_0x13247e0/d; +v0x11c2670_0 .net *"_s0", 0 0, L_0x1324fa0; 1 drivers +v0x11c2750_0 .net *"_s1", 0 0, L_0x1325190; 1 drivers +S_0x11c3310 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11bfea0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e933f0/d .functor OR 1, L_0x1e934b0, L_0x1e93660, C4<0>, C4<0>; -L_0x1e933f0 .delay 1 (30000,30000,30000) L_0x1e933f0/d; -v0x1d32210_0 .net *"_s10", 0 0, L_0x1e934b0; 1 drivers -v0x1d322f0_0 .net *"_s12", 0 0, L_0x1e93660; 1 drivers -v0x1d323d0_0 .net "in", 7 0, L_0x1e913f0; alias, 1 drivers -v0x1d324a0_0 .net "ors", 1 0, L_0x1e93210; 1 drivers -v0x1d32560_0 .net "out", 0 0, L_0x1e933f0; alias, 1 drivers -L_0x1e925e0 .part L_0x1e913f0, 0, 4; -L_0x1e93210 .concat8 [ 1 1 0 0], L_0x1e922d0, L_0x1e92f00; -L_0x1e93350 .part L_0x1e913f0, 4, 4; -L_0x1e934b0 .part L_0x1e93210, 0, 1; -L_0x1e93660 .part L_0x1e93210, 1, 1; -S_0x1d30880 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d306c0; +L_0x1326c10/d .functor OR 1, L_0x1326cd0, L_0x1326e80, C4<0>, C4<0>; +L_0x1326c10 .delay 1 (30000,30000,30000) L_0x1326c10/d; +v0x11c4e60_0 .net *"_s10", 0 0, L_0x1326cd0; 1 drivers +v0x11c4f40_0 .net *"_s12", 0 0, L_0x1326e80; 1 drivers +v0x11c5020_0 .net "in", 7 0, L_0x1324be0; alias, 1 drivers +v0x11c50f0_0 .net "ors", 1 0, L_0x1326a30; 1 drivers +v0x11c51b0_0 .net "out", 0 0, L_0x1326c10; alias, 1 drivers +L_0x1325dd0 .part L_0x1324be0, 0, 4; +L_0x1326a30 .concat8 [ 1 1 0 0], L_0x1325ac0, L_0x13266f0; +L_0x1326b70 .part L_0x1324be0, 4, 4; +L_0x1326cd0 .part L_0x1326a30, 0, 1; +L_0x1326e80 .part L_0x1326a30, 1, 1; +S_0x11c34d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11c3310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e91a90/d .functor OR 1, L_0x1e91b50, L_0x1e91cb0, C4<0>, C4<0>; -L_0x1e91a90 .delay 1 (30000,30000,30000) L_0x1e91a90/d; -L_0x1e91ee0/d .functor OR 1, L_0x1e91ff0, L_0x1e92150, C4<0>, C4<0>; -L_0x1e91ee0 .delay 1 (30000,30000,30000) L_0x1e91ee0/d; -L_0x1e922d0/d .functor OR 1, L_0x1e92340, L_0x1e924f0, C4<0>, C4<0>; -L_0x1e922d0 .delay 1 (30000,30000,30000) L_0x1e922d0/d; -v0x1d30ad0_0 .net *"_s0", 0 0, L_0x1e91a90; 1 drivers -v0x1d30bd0_0 .net *"_s10", 0 0, L_0x1e91ff0; 1 drivers -v0x1d30cb0_0 .net *"_s12", 0 0, L_0x1e92150; 1 drivers -v0x1d30d70_0 .net *"_s14", 0 0, L_0x1e92340; 1 drivers -v0x1d30e50_0 .net *"_s16", 0 0, L_0x1e924f0; 1 drivers -v0x1d30f80_0 .net *"_s3", 0 0, L_0x1e91b50; 1 drivers -v0x1d31060_0 .net *"_s5", 0 0, L_0x1e91cb0; 1 drivers -v0x1d31140_0 .net *"_s6", 0 0, L_0x1e91ee0; 1 drivers -v0x1d31220_0 .net "in", 3 0, L_0x1e925e0; 1 drivers -v0x1d31390_0 .net "ors", 1 0, L_0x1e91df0; 1 drivers -v0x1d31470_0 .net "out", 0 0, L_0x1e922d0; 1 drivers -L_0x1e91b50 .part L_0x1e925e0, 0, 1; -L_0x1e91cb0 .part L_0x1e925e0, 1, 1; -L_0x1e91df0 .concat8 [ 1 1 0 0], L_0x1e91a90, L_0x1e91ee0; -L_0x1e91ff0 .part L_0x1e925e0, 2, 1; -L_0x1e92150 .part L_0x1e925e0, 3, 1; -L_0x1e92340 .part L_0x1e91df0, 0, 1; -L_0x1e924f0 .part L_0x1e91df0, 1, 1; -S_0x1d31590 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d306c0; +L_0x1325280/d .functor OR 1, L_0x1325340, L_0x13254a0, C4<0>, C4<0>; +L_0x1325280 .delay 1 (30000,30000,30000) L_0x1325280/d; +L_0x13256d0/d .functor OR 1, L_0x13257e0, L_0x1325940, C4<0>, C4<0>; +L_0x13256d0 .delay 1 (30000,30000,30000) L_0x13256d0/d; +L_0x1325ac0/d .functor OR 1, L_0x1325b30, L_0x1325ce0, C4<0>, C4<0>; +L_0x1325ac0 .delay 1 (30000,30000,30000) L_0x1325ac0/d; +v0x11c3720_0 .net *"_s0", 0 0, L_0x1325280; 1 drivers +v0x11c3820_0 .net *"_s10", 0 0, L_0x13257e0; 1 drivers +v0x11c3900_0 .net *"_s12", 0 0, L_0x1325940; 1 drivers +v0x11c39c0_0 .net *"_s14", 0 0, L_0x1325b30; 1 drivers +v0x11c3aa0_0 .net *"_s16", 0 0, L_0x1325ce0; 1 drivers +v0x11c3bd0_0 .net *"_s3", 0 0, L_0x1325340; 1 drivers +v0x11c3cb0_0 .net *"_s5", 0 0, L_0x13254a0; 1 drivers +v0x11c3d90_0 .net *"_s6", 0 0, L_0x13256d0; 1 drivers +v0x11c3e70_0 .net "in", 3 0, L_0x1325dd0; 1 drivers +v0x11c3fe0_0 .net "ors", 1 0, L_0x13255e0; 1 drivers +v0x11c40c0_0 .net "out", 0 0, L_0x1325ac0; 1 drivers +L_0x1325340 .part L_0x1325dd0, 0, 1; +L_0x13254a0 .part L_0x1325dd0, 1, 1; +L_0x13255e0 .concat8 [ 1 1 0 0], L_0x1325280, L_0x13256d0; +L_0x13257e0 .part L_0x1325dd0, 2, 1; +L_0x1325940 .part L_0x1325dd0, 3, 1; +L_0x1325b30 .part L_0x13255e0, 0, 1; +L_0x1325ce0 .part L_0x13255e0, 1, 1; +S_0x11c41e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11c3310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e92710/d .functor OR 1, L_0x1e92780, L_0x1e928e0, C4<0>, C4<0>; -L_0x1e92710 .delay 1 (30000,30000,30000) L_0x1e92710/d; -L_0x1e92b10/d .functor OR 1, L_0x1e92c20, L_0x1e92d80, C4<0>, C4<0>; -L_0x1e92b10 .delay 1 (30000,30000,30000) L_0x1e92b10/d; -L_0x1e92f00/d .functor OR 1, L_0x1e92f70, L_0x1e93120, C4<0>, C4<0>; -L_0x1e92f00 .delay 1 (30000,30000,30000) L_0x1e92f00/d; -v0x1d31750_0 .net *"_s0", 0 0, L_0x1e92710; 1 drivers -v0x1d31850_0 .net *"_s10", 0 0, L_0x1e92c20; 1 drivers -v0x1d31930_0 .net *"_s12", 0 0, L_0x1e92d80; 1 drivers -v0x1d319f0_0 .net *"_s14", 0 0, L_0x1e92f70; 1 drivers -v0x1d31ad0_0 .net *"_s16", 0 0, L_0x1e93120; 1 drivers -v0x1d31c00_0 .net *"_s3", 0 0, L_0x1e92780; 1 drivers -v0x1d31ce0_0 .net *"_s5", 0 0, L_0x1e928e0; 1 drivers -v0x1d31dc0_0 .net *"_s6", 0 0, L_0x1e92b10; 1 drivers -v0x1d31ea0_0 .net "in", 3 0, L_0x1e93350; 1 drivers -v0x1d32010_0 .net "ors", 1 0, L_0x1e92a20; 1 drivers -v0x1d320f0_0 .net "out", 0 0, L_0x1e92f00; 1 drivers -L_0x1e92780 .part L_0x1e93350, 0, 1; -L_0x1e928e0 .part L_0x1e93350, 1, 1; -L_0x1e92a20 .concat8 [ 1 1 0 0], L_0x1e92710, L_0x1e92b10; -L_0x1e92c20 .part L_0x1e93350, 2, 1; -L_0x1e92d80 .part L_0x1e93350, 3, 1; -L_0x1e92f70 .part L_0x1e92a20, 0, 1; -L_0x1e93120 .part L_0x1e92a20, 1, 1; -S_0x1d32a00 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d26380; +L_0x1325f00/d .functor OR 1, L_0x1325f70, L_0x13260d0, C4<0>, C4<0>; +L_0x1325f00 .delay 1 (30000,30000,30000) L_0x1325f00/d; +L_0x1326300/d .functor OR 1, L_0x1326410, L_0x1326570, C4<0>, C4<0>; +L_0x1326300 .delay 1 (30000,30000,30000) L_0x1326300/d; +L_0x13266f0/d .functor OR 1, L_0x1326790, L_0x1326940, C4<0>, C4<0>; +L_0x13266f0 .delay 1 (30000,30000,30000) L_0x13266f0/d; +v0x11c43a0_0 .net *"_s0", 0 0, L_0x1325f00; 1 drivers +v0x11c44a0_0 .net *"_s10", 0 0, L_0x1326410; 1 drivers +v0x11c4580_0 .net *"_s12", 0 0, L_0x1326570; 1 drivers +v0x11c4640_0 .net *"_s14", 0 0, L_0x1326790; 1 drivers +v0x11c4720_0 .net *"_s16", 0 0, L_0x1326940; 1 drivers +v0x11c4850_0 .net *"_s3", 0 0, L_0x1325f70; 1 drivers +v0x11c4930_0 .net *"_s5", 0 0, L_0x13260d0; 1 drivers +v0x11c4a10_0 .net *"_s6", 0 0, L_0x1326300; 1 drivers +v0x11c4af0_0 .net "in", 3 0, L_0x1326b70; 1 drivers +v0x11c4c60_0 .net "ors", 1 0, L_0x1326210; 1 drivers +v0x11c4d40_0 .net "out", 0 0, L_0x13266f0; 1 drivers +L_0x1325f70 .part L_0x1326b70, 0, 1; +L_0x13260d0 .part L_0x1326b70, 1, 1; +L_0x1326210 .concat8 [ 1 1 0 0], L_0x1325f00, L_0x1326300; +L_0x1326410 .part L_0x1326b70, 2, 1; +L_0x1326570 .part L_0x1326b70, 3, 1; +L_0x1326790 .part L_0x1326210, 0, 1; +L_0x1326940 .part L_0x1326210, 1, 1; +S_0x11c5650 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11b8fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -16012,80 +16022,80 @@ S_0x1d32a00 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d26380; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e8eca0/d .functor XNOR 1, L_0x1e97290, L_0x1e8d880, C4<0>, C4<0>; -L_0x1e8eca0 .delay 1 (20000,20000,20000) L_0x1e8eca0/d; -L_0x1e8ef10/d .functor AND 1, L_0x1e97290, L_0x1e8db90, C4<1>, C4<1>; -L_0x1e8ef10 .delay 1 (30000,30000,30000) L_0x1e8ef10/d; -L_0x1e8ef80/d .functor AND 1, L_0x1e8eca0, L_0x1e8d920, C4<1>, C4<1>; -L_0x1e8ef80 .delay 1 (30000,30000,30000) L_0x1e8ef80/d; -L_0x1e8f0e0/d .functor OR 1, L_0x1e8ef80, L_0x1e8ef10, C4<0>, C4<0>; -L_0x1e8f0e0 .delay 1 (30000,30000,30000) L_0x1e8f0e0/d; -v0x1d32cb0_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers -v0x1d32da0_0 .net "a_", 0 0, L_0x1e83ce0; alias, 1 drivers -v0x1d32e60_0 .net "b", 0 0, L_0x1e8d880; alias, 1 drivers -v0x1d32f50_0 .net "b_", 0 0, L_0x1e8db90; alias, 1 drivers -v0x1d32ff0_0 .net "carryin", 0 0, L_0x1e8d920; alias, 1 drivers -v0x1d33130_0 .net "eq", 0 0, L_0x1e8eca0; 1 drivers -v0x1d331f0_0 .net "lt", 0 0, L_0x1e8ef10; 1 drivers -v0x1d332b0_0 .net "out", 0 0, L_0x1e8f0e0; 1 drivers -v0x1d33370_0 .net "w0", 0 0, L_0x1e8ef80; 1 drivers -S_0x1d335c0 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d26380; +L_0x1322360/d .functor XNOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; +L_0x1322360 .delay 1 (20000,20000,20000) L_0x1322360/d; +L_0x13225d0/d .functor AND 1, L_0x132ab70, L_0x13213b0, C4<1>, C4<1>; +L_0x13225d0 .delay 1 (30000,30000,30000) L_0x13225d0/d; +L_0x1322640/d .functor AND 1, L_0x1322360, L_0x1321140, C4<1>, C4<1>; +L_0x1322640 .delay 1 (30000,30000,30000) L_0x1322640/d; +L_0x13227a0/d .functor OR 1, L_0x1322640, L_0x13225d0, C4<0>, C4<0>; +L_0x13227a0 .delay 1 (30000,30000,30000) L_0x13227a0/d; +v0x11c5900_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers +v0x11c59f0_0 .net "a_", 0 0, L_0x1317400; alias, 1 drivers +v0x11c5ab0_0 .net "b", 0 0, L_0x13210a0; alias, 1 drivers +v0x11c5ba0_0 .net "b_", 0 0, L_0x13213b0; alias, 1 drivers +v0x11c5c40_0 .net "carryin", 0 0, L_0x1321140; alias, 1 drivers +v0x11c5d80_0 .net "eq", 0 0, L_0x1322360; 1 drivers +v0x11c5e40_0 .net "lt", 0 0, L_0x13225d0; 1 drivers +v0x11c5f00_0 .net "out", 0 0, L_0x13227a0; 1 drivers +v0x11c5fc0_0 .net "w0", 0 0, L_0x1322640; 1 drivers +S_0x11c6210 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11b8fd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e8ea80/d .functor OR 1, L_0x1e8e580, L_0x1d34820, C4<0>, C4<0>; -L_0x1e8ea80 .delay 1 (30000,30000,30000) L_0x1e8ea80/d; -v0x1d343b0_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers -v0x1d34500_0 .net "b", 0 0, L_0x1e8db90; alias, 1 drivers -v0x1d345c0_0 .net "c1", 0 0, L_0x1e8e580; 1 drivers -v0x1d34660_0 .net "c2", 0 0, L_0x1d34820; 1 drivers -v0x1d34730_0 .net "carryin", 0 0, L_0x1e8d920; alias, 1 drivers -v0x1d348b0_0 .net "carryout", 0 0, L_0x1e8ea80; 1 drivers -v0x1d34950_0 .net "s1", 0 0, L_0x1e8e4c0; 1 drivers -v0x1d349f0_0 .net "sum", 0 0, L_0x1e8e6e0; 1 drivers -S_0x1d33810 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d335c0; +L_0x1322140/d .functor OR 1, L_0x1321c90, L_0x11c7470, C4<0>, C4<0>; +L_0x1322140 .delay 1 (30000,30000,30000) L_0x1322140/d; +v0x11c7000_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers +v0x11c7150_0 .net "b", 0 0, L_0x13213b0; alias, 1 drivers +v0x11c7210_0 .net "c1", 0 0, L_0x1321c90; 1 drivers +v0x11c72b0_0 .net "c2", 0 0, L_0x11c7470; 1 drivers +v0x11c7380_0 .net "carryin", 0 0, L_0x1321140; alias, 1 drivers +v0x11c7500_0 .net "carryout", 0 0, L_0x1322140; 1 drivers +v0x11c75a0_0 .net "s1", 0 0, L_0x1321bd0; 1 drivers +v0x11c7640_0 .net "sum", 0 0, L_0x1321df0; 1 drivers +S_0x11c6460 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11c6210; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e8e4c0/d .functor XOR 1, L_0x1e97290, L_0x1e8db90, C4<0>, C4<0>; -L_0x1e8e4c0 .delay 1 (30000,30000,30000) L_0x1e8e4c0/d; -L_0x1e8e580/d .functor AND 1, L_0x1e97290, L_0x1e8db90, C4<1>, C4<1>; -L_0x1e8e580 .delay 1 (30000,30000,30000) L_0x1e8e580/d; -v0x1d33a70_0 .net "a", 0 0, L_0x1e97290; alias, 1 drivers -v0x1d33b30_0 .net "b", 0 0, L_0x1e8db90; alias, 1 drivers -v0x1d33bf0_0 .net "carryout", 0 0, L_0x1e8e580; alias, 1 drivers -v0x1d33c90_0 .net "sum", 0 0, L_0x1e8e4c0; alias, 1 drivers -S_0x1d33dc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d335c0; +L_0x1321bd0/d .functor XOR 1, L_0x132ab70, L_0x13213b0, C4<0>, C4<0>; +L_0x1321bd0 .delay 1 (30000,30000,30000) L_0x1321bd0/d; +L_0x1321c90/d .functor AND 1, L_0x132ab70, L_0x13213b0, C4<1>, C4<1>; +L_0x1321c90 .delay 1 (30000,30000,30000) L_0x1321c90/d; +v0x11c66c0_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers +v0x11c6780_0 .net "b", 0 0, L_0x13213b0; alias, 1 drivers +v0x11c6840_0 .net "carryout", 0 0, L_0x1321c90; alias, 1 drivers +v0x11c68e0_0 .net "sum", 0 0, L_0x1321bd0; alias, 1 drivers +S_0x11c6a10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11c6210; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e8e6e0/d .functor XOR 1, L_0x1e8e4c0, L_0x1e8d920, C4<0>, C4<0>; -L_0x1e8e6e0 .delay 1 (30000,30000,30000) L_0x1e8e6e0/d; -L_0x1d34820/d .functor AND 1, L_0x1e8e4c0, L_0x1e8d920, C4<1>, C4<1>; -L_0x1d34820 .delay 1 (30000,30000,30000) L_0x1d34820/d; -v0x1d34020_0 .net "a", 0 0, L_0x1e8e4c0; alias, 1 drivers -v0x1d340f0_0 .net "b", 0 0, L_0x1e8d920; alias, 1 drivers -v0x1d34190_0 .net "carryout", 0 0, L_0x1d34820; alias, 1 drivers -v0x1d34260_0 .net "sum", 0 0, L_0x1e8e6e0; alias, 1 drivers -S_0x1d35e10 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d260b0; - .timescale -9 -12; -L_0x7f72592dc0b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dc100 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e97330/d .functor OR 1, L_0x7f72592dc0b8, L_0x7f72592dc100, C4<0>, C4<0>; -L_0x1e97330 .delay 1 (30000,30000,30000) L_0x1e97330/d; -v0x1d35fe0_0 .net/2u *"_s0", 0 0, L_0x7f72592dc0b8; 1 drivers -v0x1d36080_0 .net/2u *"_s2", 0 0, L_0x7f72592dc100; 1 drivers -S_0x1d36120 .scope generate, "alu_slices[30]" "alu_slices[30]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1d362f0 .param/l "i" 0 3 37, +C4<011110>; -S_0x1d363b0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d36120; +L_0x1321df0/d .functor XOR 1, L_0x1321bd0, L_0x1321140, C4<0>, C4<0>; +L_0x1321df0 .delay 1 (30000,30000,30000) L_0x1321df0/d; +L_0x11c7470/d .functor AND 1, L_0x1321bd0, L_0x1321140, C4<1>, C4<1>; +L_0x11c7470 .delay 1 (30000,30000,30000) L_0x11c7470/d; +v0x11c6c70_0 .net "a", 0 0, L_0x1321bd0; alias, 1 drivers +v0x11c6d40_0 .net "b", 0 0, L_0x1321140; alias, 1 drivers +v0x11c6de0_0 .net "carryout", 0 0, L_0x11c7470; alias, 1 drivers +v0x11c6eb0_0 .net "sum", 0 0, L_0x1321df0; alias, 1 drivers +S_0x11c8a60 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11b8d00; + .timescale -9 -12; +L_0x2b0ab3d070b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d07100 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x132ac10/d .functor OR 1, L_0x2b0ab3d070b8, L_0x2b0ab3d07100, C4<0>, C4<0>; +L_0x132ac10 .delay 1 (30000,30000,30000) L_0x132ac10/d; +v0x11c8c50_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d070b8; 1 drivers +v0x11c8d30_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d07100; 1 drivers +S_0x11c8e10 .scope generate, "alu_slices[30]" "alu_slices[30]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11c9020 .param/l "i" 0 3 41, +C4<011110>; +S_0x11c90e0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11c8e10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -16094,445 +16104,445 @@ S_0x1d363b0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d36120; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e8dab0/d .functor NOT 1, L_0x1ea0ee0, C4<0>, C4<0>, C4<0>; -L_0x1e8dab0 .delay 1 (10000,10000,10000) L_0x1e8dab0/d; -L_0x1e977c0/d .functor NOT 1, L_0x1e02630, C4<0>, C4<0>, C4<0>; -L_0x1e977c0 .delay 1 (10000,10000,10000) L_0x1e977c0/d; -L_0x1e98810/d .functor XOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; -L_0x1e98810 .delay 1 (30000,30000,30000) L_0x1e98810/d; -L_0x7f72592dc148 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dc190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1e98ec0/d .functor OR 1, L_0x7f72592dc148, L_0x7f72592dc190, C4<0>, C4<0>; -L_0x1e98ec0 .delay 1 (30000,30000,30000) L_0x1e98ec0/d; -L_0x1e990c0/d .functor AND 1, L_0x1ea0ee0, L_0x1e02630, C4<1>, C4<1>; -L_0x1e990c0 .delay 1 (30000,30000,30000) L_0x1e990c0/d; -L_0x1e99180/d .functor NAND 1, L_0x1ea0ee0, L_0x1e02630, C4<1>, C4<1>; -L_0x1e99180 .delay 1 (20000,20000,20000) L_0x1e99180/d; -L_0x1e992e0/d .functor XOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; -L_0x1e992e0 .delay 1 (20000,20000,20000) L_0x1e992e0/d; -L_0x1e99790/d .functor OR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; -L_0x1e99790 .delay 1 (30000,30000,30000) L_0x1e99790/d; -L_0x1ea0de0/d .functor NOT 1, L_0x1e87760, C4<0>, C4<0>, C4<0>; -L_0x1ea0de0 .delay 1 (10000,10000,10000) L_0x1ea0de0/d; -v0x1d44c10_0 .net "A", 0 0, L_0x1ea0ee0; 1 drivers -v0x1d44cd0_0 .net "A_", 0 0, L_0x1e8dab0; 1 drivers -v0x1d44d90_0 .net "B", 0 0, L_0x1e02630; 1 drivers -v0x1d44e60_0 .net "B_", 0 0, L_0x1e977c0; 1 drivers -v0x1d44f00_0 .net *"_s12", 0 0, L_0x1e98ec0; 1 drivers -v0x1d44ff0_0 .net/2s *"_s14", 0 0, L_0x7f72592dc148; 1 drivers -v0x1d450b0_0 .net/2s *"_s16", 0 0, L_0x7f72592dc190; 1 drivers -v0x1d45190_0 .net *"_s18", 0 0, L_0x1e990c0; 1 drivers -v0x1d45270_0 .net *"_s20", 0 0, L_0x1e99180; 1 drivers -v0x1d453e0_0 .net *"_s22", 0 0, L_0x1e992e0; 1 drivers -v0x1d454c0_0 .net *"_s24", 0 0, L_0x1e99790; 1 drivers -o0x7f725933b228 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1d455a0_0 name=_s30 -o0x7f725933b258 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1d45680_0 name=_s32 -v0x1d45760_0 .net *"_s8", 0 0, L_0x1e98810; 1 drivers -v0x1d45840_0 .net "carryin", 0 0, L_0x1e973f0; 1 drivers -v0x1d458e0_0 .net "carryout", 0 0, L_0x1ea0a80; 1 drivers -v0x1d45980_0 .net "carryouts", 7 0, L_0x1ec1f50; 1 drivers -v0x1d45b30_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d45bd0_0 .net "result", 0 0, L_0x1e87760; 1 drivers -v0x1d45cc0_0 .net "results", 7 0, L_0x1e99560; 1 drivers -v0x1d45dd0_0 .net "zero", 0 0, L_0x1ea0de0; 1 drivers -LS_0x1e99560_0_0 .concat8 [ 1 1 1 1], L_0x1e97ce0, L_0x1e98310, L_0x1e98810, L_0x1e98ec0; -LS_0x1e99560_0_4 .concat8 [ 1 1 1 1], L_0x1e990c0, L_0x1e99180, L_0x1e992e0, L_0x1e99790; -L_0x1e99560 .concat8 [ 4 4 0 0], LS_0x1e99560_0_0, LS_0x1e99560_0_4; -LS_0x1ec1f50_0_0 .concat [ 1 1 1 1], L_0x1e97f90, L_0x1e986b0, o0x7f725933b228, L_0x1e98d10; -LS_0x1ec1f50_0_4 .concat [ 4 0 0 0], o0x7f725933b258; -L_0x1ec1f50 .concat [ 4 4 0 0], LS_0x1ec1f50_0_0, LS_0x1ec1f50_0_4; -S_0x1d36670 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d363b0; +L_0x13212d0/d .functor NOT 1, L_0x13347a0, C4<0>, C4<0>, C4<0>; +L_0x13212d0 .delay 1 (10000,10000,10000) L_0x13212d0/d; +L_0x132b0a0/d .functor NOT 1, L_0x1295ce0, C4<0>, C4<0>, C4<0>; +L_0x132b0a0 .delay 1 (10000,10000,10000) L_0x132b0a0/d; +L_0x132c0f0/d .functor XOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; +L_0x132c0f0 .delay 1 (30000,30000,30000) L_0x132c0f0/d; +L_0x2b0ab3d07148 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d07190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x132c7a0/d .functor OR 1, L_0x2b0ab3d07148, L_0x2b0ab3d07190, C4<0>, C4<0>; +L_0x132c7a0 .delay 1 (30000,30000,30000) L_0x132c7a0/d; +L_0x132c9a0/d .functor AND 1, L_0x13347a0, L_0x1295ce0, C4<1>, C4<1>; +L_0x132c9a0 .delay 1 (30000,30000,30000) L_0x132c9a0/d; +L_0x132ca60/d .functor NAND 1, L_0x13347a0, L_0x1295ce0, C4<1>, C4<1>; +L_0x132ca60 .delay 1 (20000,20000,20000) L_0x132ca60/d; +L_0x132cbc0/d .functor XOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; +L_0x132cbc0 .delay 1 (20000,20000,20000) L_0x132cbc0/d; +L_0x132d070/d .functor OR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; +L_0x132d070 .delay 1 (30000,30000,30000) L_0x132d070/d; +L_0x13346a0/d .functor NOT 1, L_0x1330900, C4<0>, C4<0>, C4<0>; +L_0x13346a0 .delay 1 (10000,10000,10000) L_0x13346a0/d; +v0x11d7810_0 .net "A", 0 0, L_0x13347a0; 1 drivers +v0x11d78d0_0 .net "A_", 0 0, L_0x13212d0; 1 drivers +v0x11d7990_0 .net "B", 0 0, L_0x1295ce0; 1 drivers +v0x11d7a60_0 .net "B_", 0 0, L_0x132b0a0; 1 drivers +v0x11d7b00_0 .net *"_s12", 0 0, L_0x132c7a0; 1 drivers +v0x11d7bf0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d07148; 1 drivers +v0x11d7cb0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d07190; 1 drivers +v0x11d7d90_0 .net *"_s18", 0 0, L_0x132c9a0; 1 drivers +v0x11d7e70_0 .net *"_s20", 0 0, L_0x132ca60; 1 drivers +v0x11d7fe0_0 .net *"_s22", 0 0, L_0x132cbc0; 1 drivers +v0x11d80c0_0 .net *"_s24", 0 0, L_0x132d070; 1 drivers +o0x2b0ab3cec228 .functor BUFZ 1, C4; HiZ drive +; Elide local net with no drivers, v0x11d81a0_0 name=_s30 +o0x2b0ab3cec258 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x11d8280_0 name=_s32 +v0x11d8360_0 .net *"_s8", 0 0, L_0x132c0f0; 1 drivers +v0x11d8440_0 .net "carryin", 0 0, L_0x132acd0; 1 drivers +v0x11d84e0_0 .net "carryout", 0 0, L_0x1334340; 1 drivers +v0x11d8580_0 .net "carryouts", 7 0, L_0x1356280; 1 drivers +v0x11d8730_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11d87d0_0 .net "result", 0 0, L_0x1330900; 1 drivers +v0x11d88c0_0 .net "results", 7 0, L_0x132ce40; 1 drivers +v0x11d89d0_0 .net "zero", 0 0, L_0x13346a0; 1 drivers +LS_0x132ce40_0_0 .concat8 [ 1 1 1 1], L_0x132b5c0, L_0x132bbf0, L_0x132c0f0, L_0x132c7a0; +LS_0x132ce40_0_4 .concat8 [ 1 1 1 1], L_0x132c9a0, L_0x132ca60, L_0x132cbc0, L_0x132d070; +L_0x132ce40 .concat8 [ 4 4 0 0], LS_0x132ce40_0_0, LS_0x132ce40_0_4; +LS_0x1356280_0_0 .concat [ 1 1 1 1], L_0x132b870, L_0x132bf90, o0x2b0ab3cec228, L_0x132c5f0; +LS_0x1356280_0_4 .concat [ 4 0 0 0], o0x2b0ab3cec258; +L_0x1356280 .concat [ 4 4 0 0], LS_0x1356280_0_0, LS_0x1356280_0_4; +S_0x11c9360 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11c90e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e97f90/d .functor OR 1, L_0x1e97a70, L_0x1e97e30, C4<0>, C4<0>; -L_0x1e97f90 .delay 1 (30000,30000,30000) L_0x1e97f90/d; -v0x1d37590_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers -v0x1d37650_0 .net "b", 0 0, L_0x1e02630; alias, 1 drivers -v0x1d37720_0 .net "c1", 0 0, L_0x1e97a70; 1 drivers -v0x1d37820_0 .net "c2", 0 0, L_0x1e97e30; 1 drivers -v0x1d378f0_0 .net "carryin", 0 0, L_0x1e973f0; alias, 1 drivers -v0x1d379e0_0 .net "carryout", 0 0, L_0x1e97f90; 1 drivers -v0x1d37a80_0 .net "s1", 0 0, L_0x1e979b0; 1 drivers -v0x1d37b70_0 .net "sum", 0 0, L_0x1e97ce0; 1 drivers -S_0x1d36910 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d36670; +L_0x132b870/d .functor OR 1, L_0x132b350, L_0x132b710, C4<0>, C4<0>; +L_0x132b870 .delay 1 (30000,30000,30000) L_0x132b870/d; +v0x11ca190_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers +v0x11ca250_0 .net "b", 0 0, L_0x1295ce0; alias, 1 drivers +v0x11ca320_0 .net "c1", 0 0, L_0x132b350; 1 drivers +v0x11ca420_0 .net "c2", 0 0, L_0x132b710; 1 drivers +v0x11ca4f0_0 .net "carryin", 0 0, L_0x132acd0; alias, 1 drivers +v0x11ca5e0_0 .net "carryout", 0 0, L_0x132b870; 1 drivers +v0x11ca680_0 .net "s1", 0 0, L_0x132b290; 1 drivers +v0x11ca770_0 .net "sum", 0 0, L_0x132b5c0; 1 drivers +S_0x11c95d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11c9360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e979b0/d .functor XOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; -L_0x1e979b0 .delay 1 (30000,30000,30000) L_0x1e979b0/d; -L_0x1e97a70/d .functor AND 1, L_0x1ea0ee0, L_0x1e02630, C4<1>, C4<1>; -L_0x1e97a70 .delay 1 (30000,30000,30000) L_0x1e97a70/d; -v0x1d36ba0_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers -v0x1d36c80_0 .net "b", 0 0, L_0x1e02630; alias, 1 drivers -v0x1d36d40_0 .net "carryout", 0 0, L_0x1e97a70; alias, 1 drivers -v0x1d36e10_0 .net "sum", 0 0, L_0x1e979b0; alias, 1 drivers -S_0x1d36f80 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d36670; +L_0x132b290/d .functor XOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; +L_0x132b290 .delay 1 (30000,30000,30000) L_0x132b290/d; +L_0x132b350/d .functor AND 1, L_0x13347a0, L_0x1295ce0, C4<1>, C4<1>; +L_0x132b350 .delay 1 (30000,30000,30000) L_0x132b350/d; +v0x11c9830_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers +v0x11c9910_0 .net "b", 0 0, L_0x1295ce0; alias, 1 drivers +v0x11c99d0_0 .net "carryout", 0 0, L_0x132b350; alias, 1 drivers +v0x11c9a70_0 .net "sum", 0 0, L_0x132b290; alias, 1 drivers +S_0x11c9bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11c9360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e97ce0/d .functor XOR 1, L_0x1e979b0, L_0x1e973f0, C4<0>, C4<0>; -L_0x1e97ce0 .delay 1 (30000,30000,30000) L_0x1e97ce0/d; -L_0x1e97e30/d .functor AND 1, L_0x1e979b0, L_0x1e973f0, C4<1>, C4<1>; -L_0x1e97e30 .delay 1 (30000,30000,30000) L_0x1e97e30/d; -v0x1d371e0_0 .net "a", 0 0, L_0x1e979b0; alias, 1 drivers -v0x1d372b0_0 .net "b", 0 0, L_0x1e973f0; alias, 1 drivers -v0x1d37350_0 .net "carryout", 0 0, L_0x1e97e30; alias, 1 drivers -v0x1d37420_0 .net "sum", 0 0, L_0x1e97ce0; alias, 1 drivers -S_0x1d37c40 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d363b0; +L_0x132b5c0/d .functor XOR 1, L_0x132b290, L_0x132acd0, C4<0>, C4<0>; +L_0x132b5c0 .delay 1 (30000,30000,30000) L_0x132b5c0/d; +L_0x132b710/d .functor AND 1, L_0x132b290, L_0x132acd0, C4<1>, C4<1>; +L_0x132b710 .delay 1 (30000,30000,30000) L_0x132b710/d; +v0x11c9e10_0 .net "a", 0 0, L_0x132b290; alias, 1 drivers +v0x11c9eb0_0 .net "b", 0 0, L_0x132acd0; alias, 1 drivers +v0x11c9f50_0 .net "carryout", 0 0, L_0x132b710; alias, 1 drivers +v0x11ca020_0 .net "sum", 0 0, L_0x132b5c0; alias, 1 drivers +S_0x11ca840 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11c90e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d3d030_0 .net "ands", 7 0, L_0x1e9ea80; 1 drivers -v0x1d3d140_0 .net "in", 7 0, L_0x1ec1f50; alias, 1 drivers -v0x1d3d200_0 .net "out", 0 0, L_0x1ea0a80; alias, 1 drivers -v0x1d3d2d0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d37e60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d37c40; +v0x11cfc30_0 .net "ands", 7 0, L_0x1332340; 1 drivers +v0x11cfd40_0 .net "in", 7 0, L_0x1356280; alias, 1 drivers +v0x11cfe00_0 .net "out", 0 0, L_0x1334340; alias, 1 drivers +v0x11cfed0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11caa60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11ca840; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d3a590_0 .net "A", 7 0, L_0x1ec1f50; alias, 1 drivers -v0x1d3a690_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d3a750_0 .net *"_s0", 0 0, L_0x1e9d2c0; 1 drivers -v0x1d3a810_0 .net *"_s12", 0 0, L_0x1e9dc30; 1 drivers -v0x1d3a8f0_0 .net *"_s16", 0 0, L_0x1e9df90; 1 drivers -v0x1d3aa20_0 .net *"_s20", 0 0, L_0x1e9e300; 1 drivers -v0x1d3ab00_0 .net *"_s24", 0 0, L_0x1e9e6f0; 1 drivers -v0x1d3abe0_0 .net *"_s28", 0 0, L_0x1e9e680; 1 drivers -v0x1d3acc0_0 .net *"_s4", 0 0, L_0x1e9d5d0; 1 drivers -v0x1d3ae30_0 .net *"_s8", 0 0, L_0x1e9d920; 1 drivers -v0x1d3af10_0 .net "out", 7 0, L_0x1e9ea80; alias, 1 drivers -L_0x1e9d380 .part L_0x1ec1f50, 0, 1; -L_0x1e9d4e0 .part v0x1d6daa0_0, 0, 1; -L_0x1e9d690 .part L_0x1ec1f50, 1, 1; -L_0x1e9d880 .part v0x1d6daa0_0, 1, 1; -L_0x1e9d9e0 .part L_0x1ec1f50, 2, 1; -L_0x1e9db40 .part v0x1d6daa0_0, 2, 1; -L_0x1e9dcf0 .part L_0x1ec1f50, 3, 1; -L_0x1e9de50 .part v0x1d6daa0_0, 3, 1; -L_0x1e9e050 .part L_0x1ec1f50, 4, 1; -L_0x1e9e1b0 .part v0x1d6daa0_0, 4, 1; -L_0x1e9e370 .part L_0x1ec1f50, 5, 1; -L_0x1e9e5e0 .part v0x1d6daa0_0, 5, 1; -L_0x1e9e7b0 .part L_0x1ec1f50, 6, 1; -L_0x1e9e910 .part v0x1d6daa0_0, 6, 1; -LS_0x1e9ea80_0_0 .concat8 [ 1 1 1 1], L_0x1e9d2c0, L_0x1e9d5d0, L_0x1e9d920, L_0x1e9dc30; -LS_0x1e9ea80_0_4 .concat8 [ 1 1 1 1], L_0x1e9df90, L_0x1e9e300, L_0x1e9e6f0, L_0x1e9e680; -L_0x1e9ea80 .concat8 [ 4 4 0 0], LS_0x1e9ea80_0_0, LS_0x1e9ea80_0_4; -L_0x1e9ee40 .part L_0x1ec1f50, 7, 1; -L_0x1e9f030 .part v0x1d6daa0_0, 7, 1; -S_0x1d380c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d382d0 .param/l "i" 0 4 54, +C4<00>; -L_0x1e9d2c0/d .functor AND 1, L_0x1e9d380, L_0x1e9d4e0, C4<1>, C4<1>; -L_0x1e9d2c0 .delay 1 (30000,30000,30000) L_0x1e9d2c0/d; -v0x1d383b0_0 .net *"_s0", 0 0, L_0x1e9d380; 1 drivers -v0x1d38490_0 .net *"_s1", 0 0, L_0x1e9d4e0; 1 drivers -S_0x1d38570 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d38780 .param/l "i" 0 4 54, +C4<01>; -L_0x1e9d5d0/d .functor AND 1, L_0x1e9d690, L_0x1e9d880, C4<1>, C4<1>; -L_0x1e9d5d0 .delay 1 (30000,30000,30000) L_0x1e9d5d0/d; -v0x1d38840_0 .net *"_s0", 0 0, L_0x1e9d690; 1 drivers -v0x1d38920_0 .net *"_s1", 0 0, L_0x1e9d880; 1 drivers -S_0x1d38a00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d38c10 .param/l "i" 0 4 54, +C4<010>; -L_0x1e9d920/d .functor AND 1, L_0x1e9d9e0, L_0x1e9db40, C4<1>, C4<1>; -L_0x1e9d920 .delay 1 (30000,30000,30000) L_0x1e9d920/d; -v0x1d38cb0_0 .net *"_s0", 0 0, L_0x1e9d9e0; 1 drivers -v0x1d38d90_0 .net *"_s1", 0 0, L_0x1e9db40; 1 drivers -S_0x1d38e70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d39080 .param/l "i" 0 4 54, +C4<011>; -L_0x1e9dc30/d .functor AND 1, L_0x1e9dcf0, L_0x1e9de50, C4<1>, C4<1>; -L_0x1e9dc30 .delay 1 (30000,30000,30000) L_0x1e9dc30/d; -v0x1d39140_0 .net *"_s0", 0 0, L_0x1e9dcf0; 1 drivers -v0x1d39220_0 .net *"_s1", 0 0, L_0x1e9de50; 1 drivers -S_0x1d39300 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d39560 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e9df90/d .functor AND 1, L_0x1e9e050, L_0x1e9e1b0, C4<1>, C4<1>; -L_0x1e9df90 .delay 1 (30000,30000,30000) L_0x1e9df90/d; -v0x1d39620_0 .net *"_s0", 0 0, L_0x1e9e050; 1 drivers -v0x1d39700_0 .net *"_s1", 0 0, L_0x1e9e1b0; 1 drivers -S_0x1d397e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d399f0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e9e300/d .functor AND 1, L_0x1e9e370, L_0x1e9e5e0, C4<1>, C4<1>; -L_0x1e9e300 .delay 1 (30000,30000,30000) L_0x1e9e300/d; -v0x1d39ab0_0 .net *"_s0", 0 0, L_0x1e9e370; 1 drivers -v0x1d39b90_0 .net *"_s1", 0 0, L_0x1e9e5e0; 1 drivers -S_0x1d39c70 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d39e80 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e9e6f0/d .functor AND 1, L_0x1e9e7b0, L_0x1e9e910, C4<1>, C4<1>; -L_0x1e9e6f0 .delay 1 (30000,30000,30000) L_0x1e9e6f0/d; -v0x1d39f40_0 .net *"_s0", 0 0, L_0x1e9e7b0; 1 drivers -v0x1d3a020_0 .net *"_s1", 0 0, L_0x1e9e910; 1 drivers -S_0x1d3a100 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d37e60; - .timescale -9 -12; -P_0x1d3a310 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e9e680/d .functor AND 1, L_0x1e9ee40, L_0x1e9f030, C4<1>, C4<1>; -L_0x1e9e680 .delay 1 (30000,30000,30000) L_0x1e9e680/d; -v0x1d3a3d0_0 .net *"_s0", 0 0, L_0x1e9ee40; 1 drivers -v0x1d3a4b0_0 .net *"_s1", 0 0, L_0x1e9f030; 1 drivers -S_0x1d3b070 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d37c40; +v0x11cd190_0 .net "A", 7 0, L_0x1356280; alias, 1 drivers +v0x11cd290_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11cd350_0 .net *"_s0", 0 0, L_0x1330c60; 1 drivers +v0x11cd410_0 .net *"_s12", 0 0, L_0x13315d0; 1 drivers +v0x11cd4f0_0 .net *"_s16", 0 0, L_0x1331930; 1 drivers +v0x11cd620_0 .net *"_s20", 0 0, L_0x1331c40; 1 drivers +v0x11cd700_0 .net *"_s24", 0 0, L_0x1332030; 1 drivers +v0x11cd7e0_0 .net *"_s28", 0 0, L_0x1331fc0; 1 drivers +v0x11cd8c0_0 .net *"_s4", 0 0, L_0x1330f70; 1 drivers +v0x11cda30_0 .net *"_s8", 0 0, L_0x13312c0; 1 drivers +v0x11cdb10_0 .net "out", 7 0, L_0x1332340; alias, 1 drivers +L_0x1330d20 .part L_0x1356280, 0, 1; +L_0x1330e80 .part v0x12010b0_0, 0, 1; +L_0x1331030 .part L_0x1356280, 1, 1; +L_0x1331220 .part v0x12010b0_0, 1, 1; +L_0x1331380 .part L_0x1356280, 2, 1; +L_0x13314e0 .part v0x12010b0_0, 2, 1; +L_0x1331690 .part L_0x1356280, 3, 1; +L_0x13317f0 .part v0x12010b0_0, 3, 1; +L_0x13319f0 .part L_0x1356280, 4, 1; +L_0x1331b50 .part v0x12010b0_0, 4, 1; +L_0x1331cb0 .part L_0x1356280, 5, 1; +L_0x1331f20 .part v0x12010b0_0, 5, 1; +L_0x13320f0 .part L_0x1356280, 6, 1; +L_0x1332250 .part v0x12010b0_0, 6, 1; +LS_0x1332340_0_0 .concat8 [ 1 1 1 1], L_0x1330c60, L_0x1330f70, L_0x13312c0, L_0x13315d0; +LS_0x1332340_0_4 .concat8 [ 1 1 1 1], L_0x1331930, L_0x1331c40, L_0x1332030, L_0x1331fc0; +L_0x1332340 .concat8 [ 4 4 0 0], LS_0x1332340_0_0, LS_0x1332340_0_4; +L_0x1332700 .part L_0x1356280, 7, 1; +L_0x13328f0 .part v0x12010b0_0, 7, 1; +S_0x11cacc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11caed0 .param/l "i" 0 4 54, +C4<00>; +L_0x1330c60/d .functor AND 1, L_0x1330d20, L_0x1330e80, C4<1>, C4<1>; +L_0x1330c60 .delay 1 (30000,30000,30000) L_0x1330c60/d; +v0x11cafb0_0 .net *"_s0", 0 0, L_0x1330d20; 1 drivers +v0x11cb090_0 .net *"_s1", 0 0, L_0x1330e80; 1 drivers +S_0x11cb170 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11cb380 .param/l "i" 0 4 54, +C4<01>; +L_0x1330f70/d .functor AND 1, L_0x1331030, L_0x1331220, C4<1>, C4<1>; +L_0x1330f70 .delay 1 (30000,30000,30000) L_0x1330f70/d; +v0x11cb440_0 .net *"_s0", 0 0, L_0x1331030; 1 drivers +v0x11cb520_0 .net *"_s1", 0 0, L_0x1331220; 1 drivers +S_0x11cb600 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11cb810 .param/l "i" 0 4 54, +C4<010>; +L_0x13312c0/d .functor AND 1, L_0x1331380, L_0x13314e0, C4<1>, C4<1>; +L_0x13312c0 .delay 1 (30000,30000,30000) L_0x13312c0/d; +v0x11cb8b0_0 .net *"_s0", 0 0, L_0x1331380; 1 drivers +v0x11cb990_0 .net *"_s1", 0 0, L_0x13314e0; 1 drivers +S_0x11cba70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11cbc80 .param/l "i" 0 4 54, +C4<011>; +L_0x13315d0/d .functor AND 1, L_0x1331690, L_0x13317f0, C4<1>, C4<1>; +L_0x13315d0 .delay 1 (30000,30000,30000) L_0x13315d0/d; +v0x11cbd40_0 .net *"_s0", 0 0, L_0x1331690; 1 drivers +v0x11cbe20_0 .net *"_s1", 0 0, L_0x13317f0; 1 drivers +S_0x11cbf00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11cc160 .param/l "i" 0 4 54, +C4<0100>; +L_0x1331930/d .functor AND 1, L_0x13319f0, L_0x1331b50, C4<1>, C4<1>; +L_0x1331930 .delay 1 (30000,30000,30000) L_0x1331930/d; +v0x11cc220_0 .net *"_s0", 0 0, L_0x13319f0; 1 drivers +v0x11cc300_0 .net *"_s1", 0 0, L_0x1331b50; 1 drivers +S_0x11cc3e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11cc5f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x1331c40/d .functor AND 1, L_0x1331cb0, L_0x1331f20, C4<1>, C4<1>; +L_0x1331c40 .delay 1 (30000,30000,30000) L_0x1331c40/d; +v0x11cc6b0_0 .net *"_s0", 0 0, L_0x1331cb0; 1 drivers +v0x11cc790_0 .net *"_s1", 0 0, L_0x1331f20; 1 drivers +S_0x11cc870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11cca80 .param/l "i" 0 4 54, +C4<0110>; +L_0x1332030/d .functor AND 1, L_0x13320f0, L_0x1332250, C4<1>, C4<1>; +L_0x1332030 .delay 1 (30000,30000,30000) L_0x1332030/d; +v0x11ccb40_0 .net *"_s0", 0 0, L_0x13320f0; 1 drivers +v0x11ccc20_0 .net *"_s1", 0 0, L_0x1332250; 1 drivers +S_0x11ccd00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11caa60; + .timescale -9 -12; +P_0x11ccf10 .param/l "i" 0 4 54, +C4<0111>; +L_0x1331fc0/d .functor AND 1, L_0x1332700, L_0x13328f0, C4<1>, C4<1>; +L_0x1331fc0 .delay 1 (30000,30000,30000) L_0x1331fc0/d; +v0x11ccfd0_0 .net *"_s0", 0 0, L_0x1332700; 1 drivers +v0x11cd0b0_0 .net *"_s1", 0 0, L_0x13328f0; 1 drivers +S_0x11cdc70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11ca840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1ea0a80/d .functor OR 1, L_0x1ea0b40, L_0x1ea0cf0, C4<0>, C4<0>; -L_0x1ea0a80 .delay 1 (30000,30000,30000) L_0x1ea0a80/d; -v0x1d3cbc0_0 .net *"_s10", 0 0, L_0x1ea0b40; 1 drivers -v0x1d3cca0_0 .net *"_s12", 0 0, L_0x1ea0cf0; 1 drivers -v0x1d3cd80_0 .net "in", 7 0, L_0x1e9ea80; alias, 1 drivers -v0x1d3ce50_0 .net "ors", 1 0, L_0x1ea08a0; 1 drivers -v0x1d3cf10_0 .net "out", 0 0, L_0x1ea0a80; alias, 1 drivers -L_0x1e9fc70 .part L_0x1e9ea80, 0, 4; -L_0x1ea08a0 .concat8 [ 1 1 0 0], L_0x1e9f960, L_0x1ea0590; -L_0x1ea09e0 .part L_0x1e9ea80, 4, 4; -L_0x1ea0b40 .part L_0x1ea08a0, 0, 1; -L_0x1ea0cf0 .part L_0x1ea08a0, 1, 1; -S_0x1d3b230 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d3b070; +L_0x1334340/d .functor OR 1, L_0x1334400, L_0x13345b0, C4<0>, C4<0>; +L_0x1334340 .delay 1 (30000,30000,30000) L_0x1334340/d; +v0x11cf7c0_0 .net *"_s10", 0 0, L_0x1334400; 1 drivers +v0x11cf8a0_0 .net *"_s12", 0 0, L_0x13345b0; 1 drivers +v0x11cf980_0 .net "in", 7 0, L_0x1332340; alias, 1 drivers +v0x11cfa50_0 .net "ors", 1 0, L_0x1334160; 1 drivers +v0x11cfb10_0 .net "out", 0 0, L_0x1334340; alias, 1 drivers +L_0x1333530 .part L_0x1332340, 0, 4; +L_0x1334160 .concat8 [ 1 1 0 0], L_0x1333220, L_0x1333e50; +L_0x13342a0 .part L_0x1332340, 4, 4; +L_0x1334400 .part L_0x1334160, 0, 1; +L_0x13345b0 .part L_0x1334160, 1, 1; +S_0x11cde30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11cdc70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e9f120/d .functor OR 1, L_0x1e9f1e0, L_0x1e9f340, C4<0>, C4<0>; -L_0x1e9f120 .delay 1 (30000,30000,30000) L_0x1e9f120/d; -L_0x1e9f570/d .functor OR 1, L_0x1e9f680, L_0x1e9f7e0, C4<0>, C4<0>; -L_0x1e9f570 .delay 1 (30000,30000,30000) L_0x1e9f570/d; -L_0x1e9f960/d .functor OR 1, L_0x1e9f9d0, L_0x1e9fb80, C4<0>, C4<0>; -L_0x1e9f960 .delay 1 (30000,30000,30000) L_0x1e9f960/d; -v0x1d3b480_0 .net *"_s0", 0 0, L_0x1e9f120; 1 drivers -v0x1d3b580_0 .net *"_s10", 0 0, L_0x1e9f680; 1 drivers -v0x1d3b660_0 .net *"_s12", 0 0, L_0x1e9f7e0; 1 drivers -v0x1d3b720_0 .net *"_s14", 0 0, L_0x1e9f9d0; 1 drivers -v0x1d3b800_0 .net *"_s16", 0 0, L_0x1e9fb80; 1 drivers -v0x1d3b930_0 .net *"_s3", 0 0, L_0x1e9f1e0; 1 drivers -v0x1d3ba10_0 .net *"_s5", 0 0, L_0x1e9f340; 1 drivers -v0x1d3baf0_0 .net *"_s6", 0 0, L_0x1e9f570; 1 drivers -v0x1d3bbd0_0 .net "in", 3 0, L_0x1e9fc70; 1 drivers -v0x1d3bd40_0 .net "ors", 1 0, L_0x1e9f480; 1 drivers -v0x1d3be20_0 .net "out", 0 0, L_0x1e9f960; 1 drivers -L_0x1e9f1e0 .part L_0x1e9fc70, 0, 1; -L_0x1e9f340 .part L_0x1e9fc70, 1, 1; -L_0x1e9f480 .concat8 [ 1 1 0 0], L_0x1e9f120, L_0x1e9f570; -L_0x1e9f680 .part L_0x1e9fc70, 2, 1; -L_0x1e9f7e0 .part L_0x1e9fc70, 3, 1; -L_0x1e9f9d0 .part L_0x1e9f480, 0, 1; -L_0x1e9fb80 .part L_0x1e9f480, 1, 1; -S_0x1d3bf40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d3b070; +L_0x13329e0/d .functor OR 1, L_0x1332aa0, L_0x1332c00, C4<0>, C4<0>; +L_0x13329e0 .delay 1 (30000,30000,30000) L_0x13329e0/d; +L_0x1332e30/d .functor OR 1, L_0x1332f40, L_0x13330a0, C4<0>, C4<0>; +L_0x1332e30 .delay 1 (30000,30000,30000) L_0x1332e30/d; +L_0x1333220/d .functor OR 1, L_0x1333290, L_0x1333440, C4<0>, C4<0>; +L_0x1333220 .delay 1 (30000,30000,30000) L_0x1333220/d; +v0x11ce080_0 .net *"_s0", 0 0, L_0x13329e0; 1 drivers +v0x11ce180_0 .net *"_s10", 0 0, L_0x1332f40; 1 drivers +v0x11ce260_0 .net *"_s12", 0 0, L_0x13330a0; 1 drivers +v0x11ce320_0 .net *"_s14", 0 0, L_0x1333290; 1 drivers +v0x11ce400_0 .net *"_s16", 0 0, L_0x1333440; 1 drivers +v0x11ce530_0 .net *"_s3", 0 0, L_0x1332aa0; 1 drivers +v0x11ce610_0 .net *"_s5", 0 0, L_0x1332c00; 1 drivers +v0x11ce6f0_0 .net *"_s6", 0 0, L_0x1332e30; 1 drivers +v0x11ce7d0_0 .net "in", 3 0, L_0x1333530; 1 drivers +v0x11ce940_0 .net "ors", 1 0, L_0x1332d40; 1 drivers +v0x11cea20_0 .net "out", 0 0, L_0x1333220; 1 drivers +L_0x1332aa0 .part L_0x1333530, 0, 1; +L_0x1332c00 .part L_0x1333530, 1, 1; +L_0x1332d40 .concat8 [ 1 1 0 0], L_0x13329e0, L_0x1332e30; +L_0x1332f40 .part L_0x1333530, 2, 1; +L_0x13330a0 .part L_0x1333530, 3, 1; +L_0x1333290 .part L_0x1332d40, 0, 1; +L_0x1333440 .part L_0x1332d40, 1, 1; +S_0x11ceb40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11cdc70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e9fda0/d .functor OR 1, L_0x1e9fe10, L_0x1e9ff70, C4<0>, C4<0>; -L_0x1e9fda0 .delay 1 (30000,30000,30000) L_0x1e9fda0/d; -L_0x1ea01a0/d .functor OR 1, L_0x1ea02b0, L_0x1ea0410, C4<0>, C4<0>; -L_0x1ea01a0 .delay 1 (30000,30000,30000) L_0x1ea01a0/d; -L_0x1ea0590/d .functor OR 1, L_0x1ea0600, L_0x1ea07b0, C4<0>, C4<0>; -L_0x1ea0590 .delay 1 (30000,30000,30000) L_0x1ea0590/d; -v0x1d3c100_0 .net *"_s0", 0 0, L_0x1e9fda0; 1 drivers -v0x1d3c200_0 .net *"_s10", 0 0, L_0x1ea02b0; 1 drivers -v0x1d3c2e0_0 .net *"_s12", 0 0, L_0x1ea0410; 1 drivers -v0x1d3c3a0_0 .net *"_s14", 0 0, L_0x1ea0600; 1 drivers -v0x1d3c480_0 .net *"_s16", 0 0, L_0x1ea07b0; 1 drivers -v0x1d3c5b0_0 .net *"_s3", 0 0, L_0x1e9fe10; 1 drivers -v0x1d3c690_0 .net *"_s5", 0 0, L_0x1e9ff70; 1 drivers -v0x1d3c770_0 .net *"_s6", 0 0, L_0x1ea01a0; 1 drivers -v0x1d3c850_0 .net "in", 3 0, L_0x1ea09e0; 1 drivers -v0x1d3c9c0_0 .net "ors", 1 0, L_0x1ea00b0; 1 drivers -v0x1d3caa0_0 .net "out", 0 0, L_0x1ea0590; 1 drivers -L_0x1e9fe10 .part L_0x1ea09e0, 0, 1; -L_0x1e9ff70 .part L_0x1ea09e0, 1, 1; -L_0x1ea00b0 .concat8 [ 1 1 0 0], L_0x1e9fda0, L_0x1ea01a0; -L_0x1ea02b0 .part L_0x1ea09e0, 2, 1; -L_0x1ea0410 .part L_0x1ea09e0, 3, 1; -L_0x1ea0600 .part L_0x1ea00b0, 0, 1; -L_0x1ea07b0 .part L_0x1ea00b0, 1, 1; -S_0x1d3d3b0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d363b0; +L_0x1333660/d .functor OR 1, L_0x13336d0, L_0x1333830, C4<0>, C4<0>; +L_0x1333660 .delay 1 (30000,30000,30000) L_0x1333660/d; +L_0x1333a60/d .functor OR 1, L_0x1333b70, L_0x1333cd0, C4<0>, C4<0>; +L_0x1333a60 .delay 1 (30000,30000,30000) L_0x1333a60/d; +L_0x1333e50/d .functor OR 1, L_0x1333ec0, L_0x1334070, C4<0>, C4<0>; +L_0x1333e50 .delay 1 (30000,30000,30000) L_0x1333e50/d; +v0x11ced00_0 .net *"_s0", 0 0, L_0x1333660; 1 drivers +v0x11cee00_0 .net *"_s10", 0 0, L_0x1333b70; 1 drivers +v0x11ceee0_0 .net *"_s12", 0 0, L_0x1333cd0; 1 drivers +v0x11cefa0_0 .net *"_s14", 0 0, L_0x1333ec0; 1 drivers +v0x11cf080_0 .net *"_s16", 0 0, L_0x1334070; 1 drivers +v0x11cf1b0_0 .net *"_s3", 0 0, L_0x13336d0; 1 drivers +v0x11cf290_0 .net *"_s5", 0 0, L_0x1333830; 1 drivers +v0x11cf370_0 .net *"_s6", 0 0, L_0x1333a60; 1 drivers +v0x11cf450_0 .net "in", 3 0, L_0x13342a0; 1 drivers +v0x11cf5c0_0 .net "ors", 1 0, L_0x1333970; 1 drivers +v0x11cf6a0_0 .net "out", 0 0, L_0x1333e50; 1 drivers +L_0x13336d0 .part L_0x13342a0, 0, 1; +L_0x1333830 .part L_0x13342a0, 1, 1; +L_0x1333970 .concat8 [ 1 1 0 0], L_0x1333660, L_0x1333a60; +L_0x1333b70 .part L_0x13342a0, 2, 1; +L_0x1333cd0 .part L_0x13342a0, 3, 1; +L_0x1333ec0 .part L_0x1333970, 0, 1; +L_0x1334070 .part L_0x1333970, 1, 1; +S_0x11cffb0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11c90e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d427e0_0 .net "ands", 7 0, L_0x1e9b020; 1 drivers -v0x1d428f0_0 .net "in", 7 0, L_0x1e99560; alias, 1 drivers -v0x1d429b0_0 .net "out", 0 0, L_0x1e87760; alias, 1 drivers -v0x1d42a80_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d3d600 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d3d3b0; +v0x11d53e0_0 .net "ands", 7 0, L_0x132e900; 1 drivers +v0x11d54f0_0 .net "in", 7 0, L_0x132ce40; alias, 1 drivers +v0x11d55b0_0 .net "out", 0 0, L_0x1330900; alias, 1 drivers +v0x11d5680_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11d0200 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11cffb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d3fd40_0 .net "A", 7 0, L_0x1e99560; alias, 1 drivers -v0x1d3fe40_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d3ff00_0 .net *"_s0", 0 0, L_0x1e998f0; 1 drivers -v0x1d3ffc0_0 .net *"_s12", 0 0, L_0x1e9a2b0; 1 drivers -v0x1d400a0_0 .net *"_s16", 0 0, L_0x1e9a610; 1 drivers -v0x1d401d0_0 .net *"_s20", 0 0, L_0x1e9a9e0; 1 drivers -v0x1d402b0_0 .net *"_s24", 0 0, L_0x1e9ad10; 1 drivers -v0x1d40390_0 .net *"_s28", 0 0, L_0x1e9aca0; 1 drivers -v0x1d40470_0 .net *"_s4", 0 0, L_0x1e99c90; 1 drivers -v0x1d405e0_0 .net *"_s8", 0 0, L_0x1e99fa0; 1 drivers -v0x1d406c0_0 .net "out", 7 0, L_0x1e9b020; alias, 1 drivers -L_0x1e99a00 .part L_0x1e99560, 0, 1; -L_0x1e99bf0 .part v0x1d6daa0_0, 0, 1; -L_0x1e99d50 .part L_0x1e99560, 1, 1; -L_0x1e99eb0 .part v0x1d6daa0_0, 1, 1; -L_0x1e9a060 .part L_0x1e99560, 2, 1; -L_0x1e9a1c0 .part v0x1d6daa0_0, 2, 1; -L_0x1e9a370 .part L_0x1e99560, 3, 1; -L_0x1e9a4d0 .part v0x1d6daa0_0, 3, 1; -L_0x1e9a6d0 .part L_0x1e99560, 4, 1; -L_0x1e9a940 .part v0x1d6daa0_0, 4, 1; -L_0x1e9aa50 .part L_0x1e99560, 5, 1; -L_0x1e9abb0 .part v0x1d6daa0_0, 5, 1; -L_0x1e9add0 .part L_0x1e99560, 6, 1; -L_0x1e9af30 .part v0x1d6daa0_0, 6, 1; -LS_0x1e9b020_0_0 .concat8 [ 1 1 1 1], L_0x1e998f0, L_0x1e99c90, L_0x1e99fa0, L_0x1e9a2b0; -LS_0x1e9b020_0_4 .concat8 [ 1 1 1 1], L_0x1e9a610, L_0x1e9a9e0, L_0x1e9ad10, L_0x1e9aca0; -L_0x1e9b020 .concat8 [ 4 4 0 0], LS_0x1e9b020_0_0, LS_0x1e9b020_0_4; -L_0x1e9b3e0 .part L_0x1e99560, 7, 1; -L_0x1e9b5d0 .part v0x1d6daa0_0, 7, 1; -S_0x1d3d840 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3da50 .param/l "i" 0 4 54, +C4<00>; -L_0x1e998f0/d .functor AND 1, L_0x1e99a00, L_0x1e99bf0, C4<1>, C4<1>; -L_0x1e998f0 .delay 1 (30000,30000,30000) L_0x1e998f0/d; -v0x1d3db30_0 .net *"_s0", 0 0, L_0x1e99a00; 1 drivers -v0x1d3dc10_0 .net *"_s1", 0 0, L_0x1e99bf0; 1 drivers -S_0x1d3dcf0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3df00 .param/l "i" 0 4 54, +C4<01>; -L_0x1e99c90/d .functor AND 1, L_0x1e99d50, L_0x1e99eb0, C4<1>, C4<1>; -L_0x1e99c90 .delay 1 (30000,30000,30000) L_0x1e99c90/d; -v0x1d3dfc0_0 .net *"_s0", 0 0, L_0x1e99d50; 1 drivers -v0x1d3e0a0_0 .net *"_s1", 0 0, L_0x1e99eb0; 1 drivers -S_0x1d3e180 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3e3c0 .param/l "i" 0 4 54, +C4<010>; -L_0x1e99fa0/d .functor AND 1, L_0x1e9a060, L_0x1e9a1c0, C4<1>, C4<1>; -L_0x1e99fa0 .delay 1 (30000,30000,30000) L_0x1e99fa0/d; -v0x1d3e460_0 .net *"_s0", 0 0, L_0x1e9a060; 1 drivers -v0x1d3e540_0 .net *"_s1", 0 0, L_0x1e9a1c0; 1 drivers -S_0x1d3e620 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3e830 .param/l "i" 0 4 54, +C4<011>; -L_0x1e9a2b0/d .functor AND 1, L_0x1e9a370, L_0x1e9a4d0, C4<1>, C4<1>; -L_0x1e9a2b0 .delay 1 (30000,30000,30000) L_0x1e9a2b0/d; -v0x1d3e8f0_0 .net *"_s0", 0 0, L_0x1e9a370; 1 drivers -v0x1d3e9d0_0 .net *"_s1", 0 0, L_0x1e9a4d0; 1 drivers -S_0x1d3eab0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3ed10 .param/l "i" 0 4 54, +C4<0100>; -L_0x1e9a610/d .functor AND 1, L_0x1e9a6d0, L_0x1e9a940, C4<1>, C4<1>; -L_0x1e9a610 .delay 1 (30000,30000,30000) L_0x1e9a610/d; -v0x1d3edd0_0 .net *"_s0", 0 0, L_0x1e9a6d0; 1 drivers -v0x1d3eeb0_0 .net *"_s1", 0 0, L_0x1e9a940; 1 drivers -S_0x1d3ef90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3f1a0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1e9a9e0/d .functor AND 1, L_0x1e9aa50, L_0x1e9abb0, C4<1>, C4<1>; -L_0x1e9a9e0 .delay 1 (30000,30000,30000) L_0x1e9a9e0/d; -v0x1d3f260_0 .net *"_s0", 0 0, L_0x1e9aa50; 1 drivers -v0x1d3f340_0 .net *"_s1", 0 0, L_0x1e9abb0; 1 drivers -S_0x1d3f420 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3f630 .param/l "i" 0 4 54, +C4<0110>; -L_0x1e9ad10/d .functor AND 1, L_0x1e9add0, L_0x1e9af30, C4<1>, C4<1>; -L_0x1e9ad10 .delay 1 (30000,30000,30000) L_0x1e9ad10/d; -v0x1d3f6f0_0 .net *"_s0", 0 0, L_0x1e9add0; 1 drivers -v0x1d3f7d0_0 .net *"_s1", 0 0, L_0x1e9af30; 1 drivers -S_0x1d3f8b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d3d600; - .timescale -9 -12; -P_0x1d3fac0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1e9aca0/d .functor AND 1, L_0x1e9b3e0, L_0x1e9b5d0, C4<1>, C4<1>; -L_0x1e9aca0 .delay 1 (30000,30000,30000) L_0x1e9aca0/d; -v0x1d3fb80_0 .net *"_s0", 0 0, L_0x1e9b3e0; 1 drivers -v0x1d3fc60_0 .net *"_s1", 0 0, L_0x1e9b5d0; 1 drivers -S_0x1d40820 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d3d3b0; +v0x11d2940_0 .net "A", 7 0, L_0x132ce40; alias, 1 drivers +v0x11d2a40_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11d2b00_0 .net *"_s0", 0 0, L_0x132d1d0; 1 drivers +v0x11d2bc0_0 .net *"_s12", 0 0, L_0x132db90; 1 drivers +v0x11d2ca0_0 .net *"_s16", 0 0, L_0x132def0; 1 drivers +v0x11d2dd0_0 .net *"_s20", 0 0, L_0x132e2c0; 1 drivers +v0x11d2eb0_0 .net *"_s24", 0 0, L_0x132e5f0; 1 drivers +v0x11d2f90_0 .net *"_s28", 0 0, L_0x132e580; 1 drivers +v0x11d3070_0 .net *"_s4", 0 0, L_0x132d570; 1 drivers +v0x11d31e0_0 .net *"_s8", 0 0, L_0x132d880; 1 drivers +v0x11d32c0_0 .net "out", 7 0, L_0x132e900; alias, 1 drivers +L_0x132d2e0 .part L_0x132ce40, 0, 1; +L_0x132d4d0 .part v0x12010b0_0, 0, 1; +L_0x132d630 .part L_0x132ce40, 1, 1; +L_0x132d790 .part v0x12010b0_0, 1, 1; +L_0x132d940 .part L_0x132ce40, 2, 1; +L_0x132daa0 .part v0x12010b0_0, 2, 1; +L_0x132dc50 .part L_0x132ce40, 3, 1; +L_0x132ddb0 .part v0x12010b0_0, 3, 1; +L_0x132dfb0 .part L_0x132ce40, 4, 1; +L_0x132e220 .part v0x12010b0_0, 4, 1; +L_0x132e330 .part L_0x132ce40, 5, 1; +L_0x132e490 .part v0x12010b0_0, 5, 1; +L_0x132e6b0 .part L_0x132ce40, 6, 1; +L_0x132e810 .part v0x12010b0_0, 6, 1; +LS_0x132e900_0_0 .concat8 [ 1 1 1 1], L_0x132d1d0, L_0x132d570, L_0x132d880, L_0x132db90; +LS_0x132e900_0_4 .concat8 [ 1 1 1 1], L_0x132def0, L_0x132e2c0, L_0x132e5f0, L_0x132e580; +L_0x132e900 .concat8 [ 4 4 0 0], LS_0x132e900_0_0, LS_0x132e900_0_4; +L_0x132ecc0 .part L_0x132ce40, 7, 1; +L_0x132eeb0 .part v0x12010b0_0, 7, 1; +S_0x11d0440 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d0650 .param/l "i" 0 4 54, +C4<00>; +L_0x132d1d0/d .functor AND 1, L_0x132d2e0, L_0x132d4d0, C4<1>, C4<1>; +L_0x132d1d0 .delay 1 (30000,30000,30000) L_0x132d1d0/d; +v0x11d0730_0 .net *"_s0", 0 0, L_0x132d2e0; 1 drivers +v0x11d0810_0 .net *"_s1", 0 0, L_0x132d4d0; 1 drivers +S_0x11d08f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d0b00 .param/l "i" 0 4 54, +C4<01>; +L_0x132d570/d .functor AND 1, L_0x132d630, L_0x132d790, C4<1>, C4<1>; +L_0x132d570 .delay 1 (30000,30000,30000) L_0x132d570/d; +v0x11d0bc0_0 .net *"_s0", 0 0, L_0x132d630; 1 drivers +v0x11d0ca0_0 .net *"_s1", 0 0, L_0x132d790; 1 drivers +S_0x11d0d80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d0fc0 .param/l "i" 0 4 54, +C4<010>; +L_0x132d880/d .functor AND 1, L_0x132d940, L_0x132daa0, C4<1>, C4<1>; +L_0x132d880 .delay 1 (30000,30000,30000) L_0x132d880/d; +v0x11d1060_0 .net *"_s0", 0 0, L_0x132d940; 1 drivers +v0x11d1140_0 .net *"_s1", 0 0, L_0x132daa0; 1 drivers +S_0x11d1220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d1430 .param/l "i" 0 4 54, +C4<011>; +L_0x132db90/d .functor AND 1, L_0x132dc50, L_0x132ddb0, C4<1>, C4<1>; +L_0x132db90 .delay 1 (30000,30000,30000) L_0x132db90/d; +v0x11d14f0_0 .net *"_s0", 0 0, L_0x132dc50; 1 drivers +v0x11d15d0_0 .net *"_s1", 0 0, L_0x132ddb0; 1 drivers +S_0x11d16b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d1910 .param/l "i" 0 4 54, +C4<0100>; +L_0x132def0/d .functor AND 1, L_0x132dfb0, L_0x132e220, C4<1>, C4<1>; +L_0x132def0 .delay 1 (30000,30000,30000) L_0x132def0/d; +v0x11d19d0_0 .net *"_s0", 0 0, L_0x132dfb0; 1 drivers +v0x11d1ab0_0 .net *"_s1", 0 0, L_0x132e220; 1 drivers +S_0x11d1b90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d1da0 .param/l "i" 0 4 54, +C4<0101>; +L_0x132e2c0/d .functor AND 1, L_0x132e330, L_0x132e490, C4<1>, C4<1>; +L_0x132e2c0 .delay 1 (30000,30000,30000) L_0x132e2c0/d; +v0x11d1e60_0 .net *"_s0", 0 0, L_0x132e330; 1 drivers +v0x11d1f40_0 .net *"_s1", 0 0, L_0x132e490; 1 drivers +S_0x11d2020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d2230 .param/l "i" 0 4 54, +C4<0110>; +L_0x132e5f0/d .functor AND 1, L_0x132e6b0, L_0x132e810, C4<1>, C4<1>; +L_0x132e5f0 .delay 1 (30000,30000,30000) L_0x132e5f0/d; +v0x11d22f0_0 .net *"_s0", 0 0, L_0x132e6b0; 1 drivers +v0x11d23d0_0 .net *"_s1", 0 0, L_0x132e810; 1 drivers +S_0x11d24b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11d0200; + .timescale -9 -12; +P_0x11d26c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x132e580/d .functor AND 1, L_0x132ecc0, L_0x132eeb0, C4<1>, C4<1>; +L_0x132e580 .delay 1 (30000,30000,30000) L_0x132e580/d; +v0x11d2780_0 .net *"_s0", 0 0, L_0x132ecc0; 1 drivers +v0x11d2860_0 .net *"_s1", 0 0, L_0x132eeb0; 1 drivers +S_0x11d3420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11cffb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1e87760/d .functor OR 1, L_0x1e9d020, L_0x1e9d1d0, C4<0>, C4<0>; -L_0x1e87760 .delay 1 (30000,30000,30000) L_0x1e87760/d; -v0x1d42370_0 .net *"_s10", 0 0, L_0x1e9d020; 1 drivers -v0x1d42450_0 .net *"_s12", 0 0, L_0x1e9d1d0; 1 drivers -v0x1d42530_0 .net "in", 7 0, L_0x1e9b020; alias, 1 drivers -v0x1d42600_0 .net "ors", 1 0, L_0x1e9ce40; 1 drivers -v0x1d426c0_0 .net "out", 0 0, L_0x1e87760; alias, 1 drivers -L_0x1e9c210 .part L_0x1e9b020, 0, 4; -L_0x1e9ce40 .concat8 [ 1 1 0 0], L_0x1e9bf00, L_0x1e9cb30; -L_0x1e9cf80 .part L_0x1e9b020, 4, 4; -L_0x1e9d020 .part L_0x1e9ce40, 0, 1; -L_0x1e9d1d0 .part L_0x1e9ce40, 1, 1; -S_0x1d409e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d40820; +L_0x1330900/d .functor OR 1, L_0x13309c0, L_0x1330b70, C4<0>, C4<0>; +L_0x1330900 .delay 1 (30000,30000,30000) L_0x1330900/d; +v0x11d4f70_0 .net *"_s10", 0 0, L_0x13309c0; 1 drivers +v0x11d5050_0 .net *"_s12", 0 0, L_0x1330b70; 1 drivers +v0x11d5130_0 .net "in", 7 0, L_0x132e900; alias, 1 drivers +v0x11d5200_0 .net "ors", 1 0, L_0x1330720; 1 drivers +v0x11d52c0_0 .net "out", 0 0, L_0x1330900; alias, 1 drivers +L_0x132faf0 .part L_0x132e900, 0, 4; +L_0x1330720 .concat8 [ 1 1 0 0], L_0x132f7e0, L_0x1330410; +L_0x1330860 .part L_0x132e900, 4, 4; +L_0x13309c0 .part L_0x1330720, 0, 1; +L_0x1330b70 .part L_0x1330720, 1, 1; +S_0x11d35e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11d3420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e9b6c0/d .functor OR 1, L_0x1e9b780, L_0x1e9b8e0, C4<0>, C4<0>; -L_0x1e9b6c0 .delay 1 (30000,30000,30000) L_0x1e9b6c0/d; -L_0x1e9bb10/d .functor OR 1, L_0x1e9bc20, L_0x1e9bd80, C4<0>, C4<0>; -L_0x1e9bb10 .delay 1 (30000,30000,30000) L_0x1e9bb10/d; -L_0x1e9bf00/d .functor OR 1, L_0x1e9bf70, L_0x1e9c120, C4<0>, C4<0>; -L_0x1e9bf00 .delay 1 (30000,30000,30000) L_0x1e9bf00/d; -v0x1d40c30_0 .net *"_s0", 0 0, L_0x1e9b6c0; 1 drivers -v0x1d40d30_0 .net *"_s10", 0 0, L_0x1e9bc20; 1 drivers -v0x1d40e10_0 .net *"_s12", 0 0, L_0x1e9bd80; 1 drivers -v0x1d40ed0_0 .net *"_s14", 0 0, L_0x1e9bf70; 1 drivers -v0x1d40fb0_0 .net *"_s16", 0 0, L_0x1e9c120; 1 drivers -v0x1d410e0_0 .net *"_s3", 0 0, L_0x1e9b780; 1 drivers -v0x1d411c0_0 .net *"_s5", 0 0, L_0x1e9b8e0; 1 drivers -v0x1d412a0_0 .net *"_s6", 0 0, L_0x1e9bb10; 1 drivers -v0x1d41380_0 .net "in", 3 0, L_0x1e9c210; 1 drivers -v0x1d414f0_0 .net "ors", 1 0, L_0x1e9ba20; 1 drivers -v0x1d415d0_0 .net "out", 0 0, L_0x1e9bf00; 1 drivers -L_0x1e9b780 .part L_0x1e9c210, 0, 1; -L_0x1e9b8e0 .part L_0x1e9c210, 1, 1; -L_0x1e9ba20 .concat8 [ 1 1 0 0], L_0x1e9b6c0, L_0x1e9bb10; -L_0x1e9bc20 .part L_0x1e9c210, 2, 1; -L_0x1e9bd80 .part L_0x1e9c210, 3, 1; -L_0x1e9bf70 .part L_0x1e9ba20, 0, 1; -L_0x1e9c120 .part L_0x1e9ba20, 1, 1; -S_0x1d416f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d40820; +L_0x132efa0/d .functor OR 1, L_0x132f060, L_0x132f1c0, C4<0>, C4<0>; +L_0x132efa0 .delay 1 (30000,30000,30000) L_0x132efa0/d; +L_0x132f3f0/d .functor OR 1, L_0x132f500, L_0x132f660, C4<0>, C4<0>; +L_0x132f3f0 .delay 1 (30000,30000,30000) L_0x132f3f0/d; +L_0x132f7e0/d .functor OR 1, L_0x132f850, L_0x132fa00, C4<0>, C4<0>; +L_0x132f7e0 .delay 1 (30000,30000,30000) L_0x132f7e0/d; +v0x11d3830_0 .net *"_s0", 0 0, L_0x132efa0; 1 drivers +v0x11d3930_0 .net *"_s10", 0 0, L_0x132f500; 1 drivers +v0x11d3a10_0 .net *"_s12", 0 0, L_0x132f660; 1 drivers +v0x11d3ad0_0 .net *"_s14", 0 0, L_0x132f850; 1 drivers +v0x11d3bb0_0 .net *"_s16", 0 0, L_0x132fa00; 1 drivers +v0x11d3ce0_0 .net *"_s3", 0 0, L_0x132f060; 1 drivers +v0x11d3dc0_0 .net *"_s5", 0 0, L_0x132f1c0; 1 drivers +v0x11d3ea0_0 .net *"_s6", 0 0, L_0x132f3f0; 1 drivers +v0x11d3f80_0 .net "in", 3 0, L_0x132faf0; 1 drivers +v0x11d40f0_0 .net "ors", 1 0, L_0x132f300; 1 drivers +v0x11d41d0_0 .net "out", 0 0, L_0x132f7e0; 1 drivers +L_0x132f060 .part L_0x132faf0, 0, 1; +L_0x132f1c0 .part L_0x132faf0, 1, 1; +L_0x132f300 .concat8 [ 1 1 0 0], L_0x132efa0, L_0x132f3f0; +L_0x132f500 .part L_0x132faf0, 2, 1; +L_0x132f660 .part L_0x132faf0, 3, 1; +L_0x132f850 .part L_0x132f300, 0, 1; +L_0x132fa00 .part L_0x132f300, 1, 1; +S_0x11d42f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11d3420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1e9c340/d .functor OR 1, L_0x1e9c3b0, L_0x1e9c510, C4<0>, C4<0>; -L_0x1e9c340 .delay 1 (30000,30000,30000) L_0x1e9c340/d; -L_0x1e9c740/d .functor OR 1, L_0x1e9c850, L_0x1e9c9b0, C4<0>, C4<0>; -L_0x1e9c740 .delay 1 (30000,30000,30000) L_0x1e9c740/d; -L_0x1e9cb30/d .functor OR 1, L_0x1e9cba0, L_0x1e9cd50, C4<0>, C4<0>; -L_0x1e9cb30 .delay 1 (30000,30000,30000) L_0x1e9cb30/d; -v0x1d418b0_0 .net *"_s0", 0 0, L_0x1e9c340; 1 drivers -v0x1d419b0_0 .net *"_s10", 0 0, L_0x1e9c850; 1 drivers -v0x1d41a90_0 .net *"_s12", 0 0, L_0x1e9c9b0; 1 drivers -v0x1d41b50_0 .net *"_s14", 0 0, L_0x1e9cba0; 1 drivers -v0x1d41c30_0 .net *"_s16", 0 0, L_0x1e9cd50; 1 drivers -v0x1d41d60_0 .net *"_s3", 0 0, L_0x1e9c3b0; 1 drivers -v0x1d41e40_0 .net *"_s5", 0 0, L_0x1e9c510; 1 drivers -v0x1d41f20_0 .net *"_s6", 0 0, L_0x1e9c740; 1 drivers -v0x1d42000_0 .net "in", 3 0, L_0x1e9cf80; 1 drivers -v0x1d42170_0 .net "ors", 1 0, L_0x1e9c650; 1 drivers -v0x1d42250_0 .net "out", 0 0, L_0x1e9cb30; 1 drivers -L_0x1e9c3b0 .part L_0x1e9cf80, 0, 1; -L_0x1e9c510 .part L_0x1e9cf80, 1, 1; -L_0x1e9c650 .concat8 [ 1 1 0 0], L_0x1e9c340, L_0x1e9c740; -L_0x1e9c850 .part L_0x1e9cf80, 2, 1; -L_0x1e9c9b0 .part L_0x1e9cf80, 3, 1; -L_0x1e9cba0 .part L_0x1e9c650, 0, 1; -L_0x1e9cd50 .part L_0x1e9c650, 1, 1; -S_0x1d42b60 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d363b0; +L_0x132fc20/d .functor OR 1, L_0x132fc90, L_0x132fdf0, C4<0>, C4<0>; +L_0x132fc20 .delay 1 (30000,30000,30000) L_0x132fc20/d; +L_0x1330020/d .functor OR 1, L_0x1330130, L_0x1330290, C4<0>, C4<0>; +L_0x1330020 .delay 1 (30000,30000,30000) L_0x1330020/d; +L_0x1330410/d .functor OR 1, L_0x1330480, L_0x1330630, C4<0>, C4<0>; +L_0x1330410 .delay 1 (30000,30000,30000) L_0x1330410/d; +v0x11d44b0_0 .net *"_s0", 0 0, L_0x132fc20; 1 drivers +v0x11d45b0_0 .net *"_s10", 0 0, L_0x1330130; 1 drivers +v0x11d4690_0 .net *"_s12", 0 0, L_0x1330290; 1 drivers +v0x11d4750_0 .net *"_s14", 0 0, L_0x1330480; 1 drivers +v0x11d4830_0 .net *"_s16", 0 0, L_0x1330630; 1 drivers +v0x11d4960_0 .net *"_s3", 0 0, L_0x132fc90; 1 drivers +v0x11d4a40_0 .net *"_s5", 0 0, L_0x132fdf0; 1 drivers +v0x11d4b20_0 .net *"_s6", 0 0, L_0x1330020; 1 drivers +v0x11d4c00_0 .net "in", 3 0, L_0x1330860; 1 drivers +v0x11d4d70_0 .net "ors", 1 0, L_0x132ff30; 1 drivers +v0x11d4e50_0 .net "out", 0 0, L_0x1330410; 1 drivers +L_0x132fc90 .part L_0x1330860, 0, 1; +L_0x132fdf0 .part L_0x1330860, 1, 1; +L_0x132ff30 .concat8 [ 1 1 0 0], L_0x132fc20, L_0x1330020; +L_0x1330130 .part L_0x1330860, 2, 1; +L_0x1330290 .part L_0x1330860, 3, 1; +L_0x1330480 .part L_0x132ff30, 0, 1; +L_0x1330630 .part L_0x132ff30, 1, 1; +S_0x11d5760 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11c90e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -16540,80 +16550,80 @@ S_0x1d42b60 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d363b0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1e988d0/d .functor XNOR 1, L_0x1ea0ee0, L_0x1e02630, C4<0>, C4<0>; -L_0x1e988d0 .delay 1 (20000,20000,20000) L_0x1e988d0/d; -L_0x1e98b40/d .functor AND 1, L_0x1ea0ee0, L_0x1e977c0, C4<1>, C4<1>; -L_0x1e98b40 .delay 1 (30000,30000,30000) L_0x1e98b40/d; -L_0x1e98bb0/d .functor AND 1, L_0x1e988d0, L_0x1e973f0, C4<1>, C4<1>; -L_0x1e98bb0 .delay 1 (30000,30000,30000) L_0x1e98bb0/d; -L_0x1e98d10/d .functor OR 1, L_0x1e98bb0, L_0x1e98b40, C4<0>, C4<0>; -L_0x1e98d10 .delay 1 (30000,30000,30000) L_0x1e98d10/d; -v0x1d42e10_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers -v0x1d42f00_0 .net "a_", 0 0, L_0x1e8dab0; alias, 1 drivers -v0x1d42fc0_0 .net "b", 0 0, L_0x1e02630; alias, 1 drivers -v0x1d430b0_0 .net "b_", 0 0, L_0x1e977c0; alias, 1 drivers -v0x1d43150_0 .net "carryin", 0 0, L_0x1e973f0; alias, 1 drivers -v0x1d43290_0 .net "eq", 0 0, L_0x1e988d0; 1 drivers -v0x1d43350_0 .net "lt", 0 0, L_0x1e98b40; 1 drivers -v0x1d43410_0 .net "out", 0 0, L_0x1e98d10; 1 drivers -v0x1d434d0_0 .net "w0", 0 0, L_0x1e98bb0; 1 drivers -S_0x1d43720 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d363b0; +L_0x132c1b0/d .functor XNOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; +L_0x132c1b0 .delay 1 (20000,20000,20000) L_0x132c1b0/d; +L_0x132c420/d .functor AND 1, L_0x13347a0, L_0x132b0a0, C4<1>, C4<1>; +L_0x132c420 .delay 1 (30000,30000,30000) L_0x132c420/d; +L_0x132c490/d .functor AND 1, L_0x132c1b0, L_0x132acd0, C4<1>, C4<1>; +L_0x132c490 .delay 1 (30000,30000,30000) L_0x132c490/d; +L_0x132c5f0/d .functor OR 1, L_0x132c490, L_0x132c420, C4<0>, C4<0>; +L_0x132c5f0 .delay 1 (30000,30000,30000) L_0x132c5f0/d; +v0x11d5a10_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers +v0x11d5b00_0 .net "a_", 0 0, L_0x13212d0; alias, 1 drivers +v0x11d5bc0_0 .net "b", 0 0, L_0x1295ce0; alias, 1 drivers +v0x11d5cb0_0 .net "b_", 0 0, L_0x132b0a0; alias, 1 drivers +v0x11d5d50_0 .net "carryin", 0 0, L_0x132acd0; alias, 1 drivers +v0x11d5e90_0 .net "eq", 0 0, L_0x132c1b0; 1 drivers +v0x11d5f50_0 .net "lt", 0 0, L_0x132c420; 1 drivers +v0x11d6010_0 .net "out", 0 0, L_0x132c5f0; 1 drivers +v0x11d60d0_0 .net "w0", 0 0, L_0x132c490; 1 drivers +S_0x11d6320 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11c90e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1e986b0/d .functor OR 1, L_0x1e981b0, L_0x1d44980, C4<0>, C4<0>; -L_0x1e986b0 .delay 1 (30000,30000,30000) L_0x1e986b0/d; -v0x1d44510_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers -v0x1d44660_0 .net "b", 0 0, L_0x1e977c0; alias, 1 drivers -v0x1d44720_0 .net "c1", 0 0, L_0x1e981b0; 1 drivers -v0x1d447c0_0 .net "c2", 0 0, L_0x1d44980; 1 drivers -v0x1d44890_0 .net "carryin", 0 0, L_0x1e973f0; alias, 1 drivers -v0x1d44a10_0 .net "carryout", 0 0, L_0x1e986b0; 1 drivers -v0x1d44ab0_0 .net "s1", 0 0, L_0x1e980f0; 1 drivers -v0x1d44b50_0 .net "sum", 0 0, L_0x1e98310; 1 drivers -S_0x1d43970 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d43720; +L_0x132bf90/d .functor OR 1, L_0x132ba90, L_0x11d7580, C4<0>, C4<0>; +L_0x132bf90 .delay 1 (30000,30000,30000) L_0x132bf90/d; +v0x11d7110_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers +v0x11d7260_0 .net "b", 0 0, L_0x132b0a0; alias, 1 drivers +v0x11d7320_0 .net "c1", 0 0, L_0x132ba90; 1 drivers +v0x11d73c0_0 .net "c2", 0 0, L_0x11d7580; 1 drivers +v0x11d7490_0 .net "carryin", 0 0, L_0x132acd0; alias, 1 drivers +v0x11d7610_0 .net "carryout", 0 0, L_0x132bf90; 1 drivers +v0x11d76b0_0 .net "s1", 0 0, L_0x132b9d0; 1 drivers +v0x11d7750_0 .net "sum", 0 0, L_0x132bbf0; 1 drivers +S_0x11d6570 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11d6320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e980f0/d .functor XOR 1, L_0x1ea0ee0, L_0x1e977c0, C4<0>, C4<0>; -L_0x1e980f0 .delay 1 (30000,30000,30000) L_0x1e980f0/d; -L_0x1e981b0/d .functor AND 1, L_0x1ea0ee0, L_0x1e977c0, C4<1>, C4<1>; -L_0x1e981b0 .delay 1 (30000,30000,30000) L_0x1e981b0/d; -v0x1d43bd0_0 .net "a", 0 0, L_0x1ea0ee0; alias, 1 drivers -v0x1d43c90_0 .net "b", 0 0, L_0x1e977c0; alias, 1 drivers -v0x1d43d50_0 .net "carryout", 0 0, L_0x1e981b0; alias, 1 drivers -v0x1d43df0_0 .net "sum", 0 0, L_0x1e980f0; alias, 1 drivers -S_0x1d43f20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d43720; +L_0x132b9d0/d .functor XOR 1, L_0x13347a0, L_0x132b0a0, C4<0>, C4<0>; +L_0x132b9d0 .delay 1 (30000,30000,30000) L_0x132b9d0/d; +L_0x132ba90/d .functor AND 1, L_0x13347a0, L_0x132b0a0, C4<1>, C4<1>; +L_0x132ba90 .delay 1 (30000,30000,30000) L_0x132ba90/d; +v0x11d67d0_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers +v0x11d6890_0 .net "b", 0 0, L_0x132b0a0; alias, 1 drivers +v0x11d6950_0 .net "carryout", 0 0, L_0x132ba90; alias, 1 drivers +v0x11d69f0_0 .net "sum", 0 0, L_0x132b9d0; alias, 1 drivers +S_0x11d6b20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11d6320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1e98310/d .functor XOR 1, L_0x1e980f0, L_0x1e973f0, C4<0>, C4<0>; -L_0x1e98310 .delay 1 (30000,30000,30000) L_0x1e98310/d; -L_0x1d44980/d .functor AND 1, L_0x1e980f0, L_0x1e973f0, C4<1>, C4<1>; -L_0x1d44980 .delay 1 (30000,30000,30000) L_0x1d44980/d; -v0x1d44180_0 .net "a", 0 0, L_0x1e980f0; alias, 1 drivers -v0x1d44250_0 .net "b", 0 0, L_0x1e973f0; alias, 1 drivers -v0x1d442f0_0 .net "carryout", 0 0, L_0x1d44980; alias, 1 drivers -v0x1d443c0_0 .net "sum", 0 0, L_0x1e98310; alias, 1 drivers -S_0x1d45f70 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d36120; - .timescale -9 -12; -L_0x7f72592dc1d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dc220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1ea0f80/d .functor OR 1, L_0x7f72592dc1d8, L_0x7f72592dc220, C4<0>, C4<0>; -L_0x1ea0f80 .delay 1 (30000,30000,30000) L_0x1ea0f80/d; -v0x1d46160_0 .net/2u *"_s0", 0 0, L_0x7f72592dc1d8; 1 drivers -v0x1d46240_0 .net/2u *"_s2", 0 0, L_0x7f72592dc220; 1 drivers -S_0x1d46320 .scope generate, "alu_slices[31]" "alu_slices[31]" 3 37, 3 37 0, S_0x1a570b0; - .timescale -9 -12; -P_0x1d46530 .param/l "i" 0 3 37, +C4<011111>; -S_0x1d465f0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d46320; +L_0x132bbf0/d .functor XOR 1, L_0x132b9d0, L_0x132acd0, C4<0>, C4<0>; +L_0x132bbf0 .delay 1 (30000,30000,30000) L_0x132bbf0/d; +L_0x11d7580/d .functor AND 1, L_0x132b9d0, L_0x132acd0, C4<1>, C4<1>; +L_0x11d7580 .delay 1 (30000,30000,30000) L_0x11d7580/d; +v0x11d6d80_0 .net "a", 0 0, L_0x132b9d0; alias, 1 drivers +v0x11d6e50_0 .net "b", 0 0, L_0x132acd0; alias, 1 drivers +v0x11d6ef0_0 .net "carryout", 0 0, L_0x11d7580; alias, 1 drivers +v0x11d6fc0_0 .net "sum", 0 0, L_0x132bbf0; alias, 1 drivers +S_0x11d8b70 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11c8e10; + .timescale -9 -12; +L_0x2b0ab3d071d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d07220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1334840/d .functor OR 1, L_0x2b0ab3d071d8, L_0x2b0ab3d07220, C4<0>, C4<0>; +L_0x1334840 .delay 1 (30000,30000,30000) L_0x1334840/d; +v0x11d8d60_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d071d8; 1 drivers +v0x11d8e40_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d07220; 1 drivers +S_0x11d8f20 .scope generate, "alu_slices[31]" "alu_slices[31]" 3 41, 3 41 0, S_0xf2fc10; + .timescale -9 -12; +P_0x11d9130 .param/l "i" 0 3 41, +C4<011111>; +S_0x11d91f0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11d8f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -16622,445 +16632,445 @@ S_0x1d465f0 .scope module, "alu1_inst" "alu1" 3 38, 4 124 0, S_0x1d46320; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1e029c0/d .functor NOT 1, L_0x1eabda0, C4<0>, C4<0>, C4<0>; -L_0x1e029c0 .delay 1 (10000,10000,10000) L_0x1e029c0/d; -L_0x1e97580/d .functor NOT 1, L_0x1eab190, C4<0>, C4<0>, C4<0>; -L_0x1e97580 .delay 1 (10000,10000,10000) L_0x1e97580/d; -L_0x1ea2790/d .functor XOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; -L_0x1ea2790 .delay 1 (30000,30000,30000) L_0x1ea2790/d; -L_0x7f72592dc268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dc2b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1ea2e40/d .functor OR 1, L_0x7f72592dc268, L_0x7f72592dc2b0, C4<0>, C4<0>; -L_0x1ea2e40 .delay 1 (30000,30000,30000) L_0x1ea2e40/d; -L_0x1ea3040/d .functor AND 1, L_0x1eabda0, L_0x1eab190, C4<1>, C4<1>; -L_0x1ea3040 .delay 1 (30000,30000,30000) L_0x1ea3040/d; -L_0x1ea3100/d .functor NAND 1, L_0x1eabda0, L_0x1eab190, C4<1>, C4<1>; -L_0x1ea3100 .delay 1 (20000,20000,20000) L_0x1ea3100/d; -L_0x1ea3260/d .functor XOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; -L_0x1ea3260 .delay 1 (20000,20000,20000) L_0x1ea3260/d; -L_0x1ea3710/d .functor OR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; -L_0x1ea3710 .delay 1 (30000,30000,30000) L_0x1ea3710/d; -L_0x1eaae20/d .functor NOT 1, L_0x1ea7080, C4<0>, C4<0>, C4<0>; -L_0x1eaae20 .delay 1 (10000,10000,10000) L_0x1eaae20/d; -v0x1d54d20_0 .net "A", 0 0, L_0x1eabda0; 1 drivers -v0x1d54de0_0 .net "A_", 0 0, L_0x1e029c0; 1 drivers -v0x1d54ea0_0 .net "B", 0 0, L_0x1eab190; 1 drivers -v0x1d54f70_0 .net "B_", 0 0, L_0x1e97580; 1 drivers -v0x1d55010_0 .net *"_s12", 0 0, L_0x1ea2e40; 1 drivers -v0x1d55100_0 .net/2s *"_s14", 0 0, L_0x7f72592dc268; 1 drivers -v0x1d551c0_0 .net/2s *"_s16", 0 0, L_0x7f72592dc2b0; 1 drivers -v0x1d552a0_0 .net *"_s18", 0 0, L_0x1ea3040; 1 drivers -v0x1d55380_0 .net *"_s20", 0 0, L_0x1ea3100; 1 drivers -v0x1d554f0_0 .net *"_s22", 0 0, L_0x1ea3260; 1 drivers -v0x1d555d0_0 .net *"_s24", 0 0, L_0x1ea3710; 1 drivers -L_0x7f72592dc388 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; -v0x1d556b0_0 .net *"_s30", 0 0, L_0x7f72592dc388; 1 drivers -o0x7f725933d7a8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1d55790_0 name=_s32 -v0x1d55870_0 .net *"_s8", 0 0, L_0x1ea2790; 1 drivers -v0x1d55950_0 .net "carryin", 0 0, L_0x1eab230; 1 drivers -v0x1d559f0_0 .net "carryout", 0 0, L_0x1eaaac0; 1 drivers -v0x1d55a90_0 .net "carryouts", 7 0, L_0x1ec2120; 1 drivers -v0x1d55c40_0 .net "command", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d55ce0_0 .net "result", 0 0, L_0x1ea7080; 1 drivers -v0x1d55dd0_0 .net "results", 7 0, L_0x1ea34e0; 1 drivers -v0x1d55ee0_0 .net "zero", 0 0, L_0x1eaae20; 1 drivers -LS_0x1ea34e0_0_0 .concat8 [ 1 1 1 1], L_0x1ea1cb0, L_0x1ea22e0, L_0x1ea2790, L_0x1ea2e40; -LS_0x1ea34e0_0_4 .concat8 [ 1 1 1 1], L_0x1ea3040, L_0x1ea3100, L_0x1ea3260, L_0x1ea3710; -L_0x1ea34e0 .concat8 [ 4 4 0 0], LS_0x1ea34e0_0_0, LS_0x1ea34e0_0_4; -LS_0x1ec2120_0_0 .concat [ 1 1 1 1], L_0x1ea1f60, L_0x1ea2630, L_0x7f72592dc388, L_0x1ea2c90; -LS_0x1ec2120_0_4 .concat [ 4 0 0 0], o0x7f725933d7a8; -L_0x1ec2120 .concat [ 4 4 0 0], LS_0x1ec2120_0_0, LS_0x1ec2120_0_4; -S_0x1d46870 .scope module, "adder" "fullAdder" 4 139, 4 85 0, S_0x1d465f0; +L_0x1296070/d .functor NOT 1, L_0x133f6b0, C4<0>, C4<0>, C4<0>; +L_0x1296070 .delay 1 (10000,10000,10000) L_0x1296070/d; +L_0x132ae60/d .functor NOT 1, L_0x133eaa0, C4<0>, C4<0>, C4<0>; +L_0x132ae60 .delay 1 (10000,10000,10000) L_0x132ae60/d; +L_0x13360a0/d .functor XOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; +L_0x13360a0 .delay 1 (30000,30000,30000) L_0x13360a0/d; +L_0x2b0ab3d07268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d072b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1336750/d .functor OR 1, L_0x2b0ab3d07268, L_0x2b0ab3d072b0, C4<0>, C4<0>; +L_0x1336750 .delay 1 (30000,30000,30000) L_0x1336750/d; +L_0x1336950/d .functor AND 1, L_0x133f6b0, L_0x133eaa0, C4<1>, C4<1>; +L_0x1336950 .delay 1 (30000,30000,30000) L_0x1336950/d; +L_0x1336a10/d .functor NAND 1, L_0x133f6b0, L_0x133eaa0, C4<1>, C4<1>; +L_0x1336a10 .delay 1 (20000,20000,20000) L_0x1336a10/d; +L_0x1336b70/d .functor XOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; +L_0x1336b70 .delay 1 (20000,20000,20000) L_0x1336b70/d; +L_0x1337020/d .functor OR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; +L_0x1337020 .delay 1 (30000,30000,30000) L_0x1337020/d; +L_0x133e730/d .functor NOT 1, L_0x133a990, C4<0>, C4<0>, C4<0>; +L_0x133e730 .delay 1 (10000,10000,10000) L_0x133e730/d; +v0x11e7920_0 .net "A", 0 0, L_0x133f6b0; 1 drivers +v0x11e79e0_0 .net "A_", 0 0, L_0x1296070; 1 drivers +v0x11e7aa0_0 .net "B", 0 0, L_0x133eaa0; 1 drivers +v0x11e7b70_0 .net "B_", 0 0, L_0x132ae60; 1 drivers +v0x11e7c10_0 .net *"_s12", 0 0, L_0x1336750; 1 drivers +v0x11e7d00_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d07268; 1 drivers +v0x11e7dc0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d072b0; 1 drivers +v0x11e7ea0_0 .net *"_s18", 0 0, L_0x1336950; 1 drivers +v0x11e7f80_0 .net *"_s20", 0 0, L_0x1336a10; 1 drivers +v0x11e80f0_0 .net *"_s22", 0 0, L_0x1336b70; 1 drivers +v0x11e81d0_0 .net *"_s24", 0 0, L_0x1337020; 1 drivers +L_0x2b0ab3d07388 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; +v0x11e82b0_0 .net *"_s30", 0 0, L_0x2b0ab3d07388; 1 drivers +o0x2b0ab3cee7a8 .functor BUFZ 4, C4; HiZ drive +; Elide local net with no drivers, v0x11e8390_0 name=_s32 +v0x11e8470_0 .net *"_s8", 0 0, L_0x13360a0; 1 drivers +v0x11e8550_0 .net "carryin", 0 0, L_0x133eb40; 1 drivers +v0x11e85f0_0 .net "carryout", 0 0, L_0x133e3d0; 1 drivers +v0x11e8690_0 .net "carryouts", 7 0, L_0x1356450; 1 drivers +v0x11e8840_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11e88e0_0 .net "result", 0 0, L_0x133a990; 1 drivers +v0x11e89d0_0 .net "results", 7 0, L_0x1336df0; 1 drivers +v0x11e8ae0_0 .net "zero", 0 0, L_0x133e730; 1 drivers +LS_0x1336df0_0_0 .concat8 [ 1 1 1 1], L_0x1335570, L_0x1335ba0, L_0x13360a0, L_0x1336750; +LS_0x1336df0_0_4 .concat8 [ 1 1 1 1], L_0x1336950, L_0x1336a10, L_0x1336b70, L_0x1337020; +L_0x1336df0 .concat8 [ 4 4 0 0], LS_0x1336df0_0_0, LS_0x1336df0_0_4; +LS_0x1356450_0_0 .concat [ 1 1 1 1], L_0x1335820, L_0x1335f40, L_0x2b0ab3d07388, L_0x13365a0; +LS_0x1356450_0_4 .concat [ 4 0 0 0], o0x2b0ab3cee7a8; +L_0x1356450 .concat [ 4 4 0 0], LS_0x1356450_0_0, LS_0x1356450_0_4; +S_0x11d9470 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11d91f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1ea1f60/d .functor OR 1, L_0x1ea1a40, L_0x1ea1e00, C4<0>, C4<0>; -L_0x1ea1f60 .delay 1 (30000,30000,30000) L_0x1ea1f60/d; -v0x1d476a0_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers -v0x1d47760_0 .net "b", 0 0, L_0x1eab190; alias, 1 drivers -v0x1d47830_0 .net "c1", 0 0, L_0x1ea1a40; 1 drivers -v0x1d47930_0 .net "c2", 0 0, L_0x1ea1e00; 1 drivers -v0x1d47a00_0 .net "carryin", 0 0, L_0x1eab230; alias, 1 drivers -v0x1d47af0_0 .net "carryout", 0 0, L_0x1ea1f60; 1 drivers -v0x1d47b90_0 .net "s1", 0 0, L_0x1ea1980; 1 drivers -v0x1d47c80_0 .net "sum", 0 0, L_0x1ea1cb0; 1 drivers -S_0x1d46ae0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d46870; +L_0x1335820/d .functor OR 1, L_0x1335300, L_0x13356c0, C4<0>, C4<0>; +L_0x1335820 .delay 1 (30000,30000,30000) L_0x1335820/d; +v0x11da2a0_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers +v0x11da360_0 .net "b", 0 0, L_0x133eaa0; alias, 1 drivers +v0x11da430_0 .net "c1", 0 0, L_0x1335300; 1 drivers +v0x11da530_0 .net "c2", 0 0, L_0x13356c0; 1 drivers +v0x11da600_0 .net "carryin", 0 0, L_0x133eb40; alias, 1 drivers +v0x11da6f0_0 .net "carryout", 0 0, L_0x1335820; 1 drivers +v0x11da790_0 .net "s1", 0 0, L_0x1335240; 1 drivers +v0x11da880_0 .net "sum", 0 0, L_0x1335570; 1 drivers +S_0x11d96e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11d9470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ea1980/d .functor XOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; -L_0x1ea1980 .delay 1 (30000,30000,30000) L_0x1ea1980/d; -L_0x1ea1a40/d .functor AND 1, L_0x1eabda0, L_0x1eab190, C4<1>, C4<1>; -L_0x1ea1a40 .delay 1 (30000,30000,30000) L_0x1ea1a40/d; -v0x1d46d40_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers -v0x1d46e20_0 .net "b", 0 0, L_0x1eab190; alias, 1 drivers -v0x1d46ee0_0 .net "carryout", 0 0, L_0x1ea1a40; alias, 1 drivers -v0x1d46f80_0 .net "sum", 0 0, L_0x1ea1980; alias, 1 drivers -S_0x1d470c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d46870; +L_0x1335240/d .functor XOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; +L_0x1335240 .delay 1 (30000,30000,30000) L_0x1335240/d; +L_0x1335300/d .functor AND 1, L_0x133f6b0, L_0x133eaa0, C4<1>, C4<1>; +L_0x1335300 .delay 1 (30000,30000,30000) L_0x1335300/d; +v0x11d9940_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers +v0x11d9a20_0 .net "b", 0 0, L_0x133eaa0; alias, 1 drivers +v0x11d9ae0_0 .net "carryout", 0 0, L_0x1335300; alias, 1 drivers +v0x11d9b80_0 .net "sum", 0 0, L_0x1335240; alias, 1 drivers +S_0x11d9cc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11d9470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ea1cb0/d .functor XOR 1, L_0x1ea1980, L_0x1eab230, C4<0>, C4<0>; -L_0x1ea1cb0 .delay 1 (30000,30000,30000) L_0x1ea1cb0/d; -L_0x1ea1e00/d .functor AND 1, L_0x1ea1980, L_0x1eab230, C4<1>, C4<1>; -L_0x1ea1e00 .delay 1 (30000,30000,30000) L_0x1ea1e00/d; -v0x1d47320_0 .net "a", 0 0, L_0x1ea1980; alias, 1 drivers -v0x1d473c0_0 .net "b", 0 0, L_0x1eab230; alias, 1 drivers -v0x1d47460_0 .net "carryout", 0 0, L_0x1ea1e00; alias, 1 drivers -v0x1d47530_0 .net "sum", 0 0, L_0x1ea1cb0; alias, 1 drivers -S_0x1d47d50 .scope module, "cMux" "unaryMultiplexor" 4 149, 4 69 0, S_0x1d465f0; +L_0x1335570/d .functor XOR 1, L_0x1335240, L_0x133eb40, C4<0>, C4<0>; +L_0x1335570 .delay 1 (30000,30000,30000) L_0x1335570/d; +L_0x13356c0/d .functor AND 1, L_0x1335240, L_0x133eb40, C4<1>, C4<1>; +L_0x13356c0 .delay 1 (30000,30000,30000) L_0x13356c0/d; +v0x11d9f20_0 .net "a", 0 0, L_0x1335240; alias, 1 drivers +v0x11d9fc0_0 .net "b", 0 0, L_0x133eb40; alias, 1 drivers +v0x11da060_0 .net "carryout", 0 0, L_0x13356c0; alias, 1 drivers +v0x11da130_0 .net "sum", 0 0, L_0x1335570; alias, 1 drivers +S_0x11da950 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11d91f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d4d140_0 .net "ands", 7 0, L_0x1ea8ac0; 1 drivers -v0x1d4d250_0 .net "in", 7 0, L_0x1ec2120; alias, 1 drivers -v0x1d4d310_0 .net "out", 0 0, L_0x1eaaac0; alias, 1 drivers -v0x1d4d3e0_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d47f70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d47d50; +v0x11dfd40_0 .net "ands", 7 0, L_0x133c3d0; 1 drivers +v0x11dfe50_0 .net "in", 7 0, L_0x1356450; alias, 1 drivers +v0x11dff10_0 .net "out", 0 0, L_0x133e3d0; alias, 1 drivers +v0x11dffe0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11dab70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11da950; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d4a6a0_0 .net "A", 7 0, L_0x1ec2120; alias, 1 drivers -v0x1d4a7a0_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d4a860_0 .net *"_s0", 0 0, L_0x1ea73e0; 1 drivers -v0x1d4a920_0 .net *"_s12", 0 0, L_0x1ea7d50; 1 drivers -v0x1d4aa00_0 .net *"_s16", 0 0, L_0x1ea80b0; 1 drivers -v0x1d4ab30_0 .net *"_s20", 0 0, L_0x1ea83c0; 1 drivers -v0x1d4ac10_0 .net *"_s24", 0 0, L_0x1ea87b0; 1 drivers -v0x1d4acf0_0 .net *"_s28", 0 0, L_0x1ea8740; 1 drivers -v0x1d4add0_0 .net *"_s4", 0 0, L_0x1ea76f0; 1 drivers -v0x1d4af40_0 .net *"_s8", 0 0, L_0x1ea7a40; 1 drivers -v0x1d4b020_0 .net "out", 7 0, L_0x1ea8ac0; alias, 1 drivers -L_0x1ea74a0 .part L_0x1ec2120, 0, 1; -L_0x1ea7600 .part v0x1d6daa0_0, 0, 1; -L_0x1ea77b0 .part L_0x1ec2120, 1, 1; -L_0x1ea79a0 .part v0x1d6daa0_0, 1, 1; -L_0x1ea7b00 .part L_0x1ec2120, 2, 1; -L_0x1ea7c60 .part v0x1d6daa0_0, 2, 1; -L_0x1ea7e10 .part L_0x1ec2120, 3, 1; -L_0x1ea7f70 .part v0x1d6daa0_0, 3, 1; -L_0x1ea8170 .part L_0x1ec2120, 4, 1; -L_0x1ea82d0 .part v0x1d6daa0_0, 4, 1; -L_0x1ea8430 .part L_0x1ec2120, 5, 1; -L_0x1ea86a0 .part v0x1d6daa0_0, 5, 1; -L_0x1ea8870 .part L_0x1ec2120, 6, 1; -L_0x1ea89d0 .part v0x1d6daa0_0, 6, 1; -LS_0x1ea8ac0_0_0 .concat8 [ 1 1 1 1], L_0x1ea73e0, L_0x1ea76f0, L_0x1ea7a40, L_0x1ea7d50; -LS_0x1ea8ac0_0_4 .concat8 [ 1 1 1 1], L_0x1ea80b0, L_0x1ea83c0, L_0x1ea87b0, L_0x1ea8740; -L_0x1ea8ac0 .concat8 [ 4 4 0 0], LS_0x1ea8ac0_0_0, LS_0x1ea8ac0_0_4; -L_0x1ea8e80 .part L_0x1ec2120, 7, 1; -L_0x1ea9070 .part v0x1d6daa0_0, 7, 1; -S_0x1d481d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d483e0 .param/l "i" 0 4 54, +C4<00>; -L_0x1ea73e0/d .functor AND 1, L_0x1ea74a0, L_0x1ea7600, C4<1>, C4<1>; -L_0x1ea73e0 .delay 1 (30000,30000,30000) L_0x1ea73e0/d; -v0x1d484c0_0 .net *"_s0", 0 0, L_0x1ea74a0; 1 drivers -v0x1d485a0_0 .net *"_s1", 0 0, L_0x1ea7600; 1 drivers -S_0x1d48680 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d48890 .param/l "i" 0 4 54, +C4<01>; -L_0x1ea76f0/d .functor AND 1, L_0x1ea77b0, L_0x1ea79a0, C4<1>, C4<1>; -L_0x1ea76f0 .delay 1 (30000,30000,30000) L_0x1ea76f0/d; -v0x1d48950_0 .net *"_s0", 0 0, L_0x1ea77b0; 1 drivers -v0x1d48a30_0 .net *"_s1", 0 0, L_0x1ea79a0; 1 drivers -S_0x1d48b10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d48d20 .param/l "i" 0 4 54, +C4<010>; -L_0x1ea7a40/d .functor AND 1, L_0x1ea7b00, L_0x1ea7c60, C4<1>, C4<1>; -L_0x1ea7a40 .delay 1 (30000,30000,30000) L_0x1ea7a40/d; -v0x1d48dc0_0 .net *"_s0", 0 0, L_0x1ea7b00; 1 drivers -v0x1d48ea0_0 .net *"_s1", 0 0, L_0x1ea7c60; 1 drivers -S_0x1d48f80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d49190 .param/l "i" 0 4 54, +C4<011>; -L_0x1ea7d50/d .functor AND 1, L_0x1ea7e10, L_0x1ea7f70, C4<1>, C4<1>; -L_0x1ea7d50 .delay 1 (30000,30000,30000) L_0x1ea7d50/d; -v0x1d49250_0 .net *"_s0", 0 0, L_0x1ea7e10; 1 drivers -v0x1d49330_0 .net *"_s1", 0 0, L_0x1ea7f70; 1 drivers -S_0x1d49410 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d49670 .param/l "i" 0 4 54, +C4<0100>; -L_0x1ea80b0/d .functor AND 1, L_0x1ea8170, L_0x1ea82d0, C4<1>, C4<1>; -L_0x1ea80b0 .delay 1 (30000,30000,30000) L_0x1ea80b0/d; -v0x1d49730_0 .net *"_s0", 0 0, L_0x1ea8170; 1 drivers -v0x1d49810_0 .net *"_s1", 0 0, L_0x1ea82d0; 1 drivers -S_0x1d498f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d49b00 .param/l "i" 0 4 54, +C4<0101>; -L_0x1ea83c0/d .functor AND 1, L_0x1ea8430, L_0x1ea86a0, C4<1>, C4<1>; -L_0x1ea83c0 .delay 1 (30000,30000,30000) L_0x1ea83c0/d; -v0x1d49bc0_0 .net *"_s0", 0 0, L_0x1ea8430; 1 drivers -v0x1d49ca0_0 .net *"_s1", 0 0, L_0x1ea86a0; 1 drivers -S_0x1d49d80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d49f90 .param/l "i" 0 4 54, +C4<0110>; -L_0x1ea87b0/d .functor AND 1, L_0x1ea8870, L_0x1ea89d0, C4<1>, C4<1>; -L_0x1ea87b0 .delay 1 (30000,30000,30000) L_0x1ea87b0/d; -v0x1d4a050_0 .net *"_s0", 0 0, L_0x1ea8870; 1 drivers -v0x1d4a130_0 .net *"_s1", 0 0, L_0x1ea89d0; 1 drivers -S_0x1d4a210 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d47f70; - .timescale -9 -12; -P_0x1d4a420 .param/l "i" 0 4 54, +C4<0111>; -L_0x1ea8740/d .functor AND 1, L_0x1ea8e80, L_0x1ea9070, C4<1>, C4<1>; -L_0x1ea8740 .delay 1 (30000,30000,30000) L_0x1ea8740/d; -v0x1d4a4e0_0 .net *"_s0", 0 0, L_0x1ea8e80; 1 drivers -v0x1d4a5c0_0 .net *"_s1", 0 0, L_0x1ea9070; 1 drivers -S_0x1d4b180 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d47d50; +v0x11dd2a0_0 .net "A", 7 0, L_0x1356450; alias, 1 drivers +v0x11dd3a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11dd460_0 .net *"_s0", 0 0, L_0x133acf0; 1 drivers +v0x11dd520_0 .net *"_s12", 0 0, L_0x133b660; 1 drivers +v0x11dd600_0 .net *"_s16", 0 0, L_0x133b9c0; 1 drivers +v0x11dd730_0 .net *"_s20", 0 0, L_0x133bcd0; 1 drivers +v0x11dd810_0 .net *"_s24", 0 0, L_0x133c0c0; 1 drivers +v0x11dd8f0_0 .net *"_s28", 0 0, L_0x133c050; 1 drivers +v0x11dd9d0_0 .net *"_s4", 0 0, L_0x133b000; 1 drivers +v0x11ddb40_0 .net *"_s8", 0 0, L_0x133b350; 1 drivers +v0x11ddc20_0 .net "out", 7 0, L_0x133c3d0; alias, 1 drivers +L_0x133adb0 .part L_0x1356450, 0, 1; +L_0x133af10 .part v0x12010b0_0, 0, 1; +L_0x133b0c0 .part L_0x1356450, 1, 1; +L_0x133b2b0 .part v0x12010b0_0, 1, 1; +L_0x133b410 .part L_0x1356450, 2, 1; +L_0x133b570 .part v0x12010b0_0, 2, 1; +L_0x133b720 .part L_0x1356450, 3, 1; +L_0x133b880 .part v0x12010b0_0, 3, 1; +L_0x133ba80 .part L_0x1356450, 4, 1; +L_0x133bbe0 .part v0x12010b0_0, 4, 1; +L_0x133bd40 .part L_0x1356450, 5, 1; +L_0x133bfb0 .part v0x12010b0_0, 5, 1; +L_0x133c180 .part L_0x1356450, 6, 1; +L_0x133c2e0 .part v0x12010b0_0, 6, 1; +LS_0x133c3d0_0_0 .concat8 [ 1 1 1 1], L_0x133acf0, L_0x133b000, L_0x133b350, L_0x133b660; +LS_0x133c3d0_0_4 .concat8 [ 1 1 1 1], L_0x133b9c0, L_0x133bcd0, L_0x133c0c0, L_0x133c050; +L_0x133c3d0 .concat8 [ 4 4 0 0], LS_0x133c3d0_0_0, LS_0x133c3d0_0_4; +L_0x133c790 .part L_0x1356450, 7, 1; +L_0x133c980 .part v0x12010b0_0, 7, 1; +S_0x11dadd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11dafe0 .param/l "i" 0 4 54, +C4<00>; +L_0x133acf0/d .functor AND 1, L_0x133adb0, L_0x133af10, C4<1>, C4<1>; +L_0x133acf0 .delay 1 (30000,30000,30000) L_0x133acf0/d; +v0x11db0c0_0 .net *"_s0", 0 0, L_0x133adb0; 1 drivers +v0x11db1a0_0 .net *"_s1", 0 0, L_0x133af10; 1 drivers +S_0x11db280 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11db490 .param/l "i" 0 4 54, +C4<01>; +L_0x133b000/d .functor AND 1, L_0x133b0c0, L_0x133b2b0, C4<1>, C4<1>; +L_0x133b000 .delay 1 (30000,30000,30000) L_0x133b000/d; +v0x11db550_0 .net *"_s0", 0 0, L_0x133b0c0; 1 drivers +v0x11db630_0 .net *"_s1", 0 0, L_0x133b2b0; 1 drivers +S_0x11db710 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11db920 .param/l "i" 0 4 54, +C4<010>; +L_0x133b350/d .functor AND 1, L_0x133b410, L_0x133b570, C4<1>, C4<1>; +L_0x133b350 .delay 1 (30000,30000,30000) L_0x133b350/d; +v0x11db9c0_0 .net *"_s0", 0 0, L_0x133b410; 1 drivers +v0x11dbaa0_0 .net *"_s1", 0 0, L_0x133b570; 1 drivers +S_0x11dbb80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11dbd90 .param/l "i" 0 4 54, +C4<011>; +L_0x133b660/d .functor AND 1, L_0x133b720, L_0x133b880, C4<1>, C4<1>; +L_0x133b660 .delay 1 (30000,30000,30000) L_0x133b660/d; +v0x11dbe50_0 .net *"_s0", 0 0, L_0x133b720; 1 drivers +v0x11dbf30_0 .net *"_s1", 0 0, L_0x133b880; 1 drivers +S_0x11dc010 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11dc270 .param/l "i" 0 4 54, +C4<0100>; +L_0x133b9c0/d .functor AND 1, L_0x133ba80, L_0x133bbe0, C4<1>, C4<1>; +L_0x133b9c0 .delay 1 (30000,30000,30000) L_0x133b9c0/d; +v0x11dc330_0 .net *"_s0", 0 0, L_0x133ba80; 1 drivers +v0x11dc410_0 .net *"_s1", 0 0, L_0x133bbe0; 1 drivers +S_0x11dc4f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11dc700 .param/l "i" 0 4 54, +C4<0101>; +L_0x133bcd0/d .functor AND 1, L_0x133bd40, L_0x133bfb0, C4<1>, C4<1>; +L_0x133bcd0 .delay 1 (30000,30000,30000) L_0x133bcd0/d; +v0x11dc7c0_0 .net *"_s0", 0 0, L_0x133bd40; 1 drivers +v0x11dc8a0_0 .net *"_s1", 0 0, L_0x133bfb0; 1 drivers +S_0x11dc980 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11dcb90 .param/l "i" 0 4 54, +C4<0110>; +L_0x133c0c0/d .functor AND 1, L_0x133c180, L_0x133c2e0, C4<1>, C4<1>; +L_0x133c0c0 .delay 1 (30000,30000,30000) L_0x133c0c0/d; +v0x11dcc50_0 .net *"_s0", 0 0, L_0x133c180; 1 drivers +v0x11dcd30_0 .net *"_s1", 0 0, L_0x133c2e0; 1 drivers +S_0x11dce10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11dab70; + .timescale -9 -12; +P_0x11dd020 .param/l "i" 0 4 54, +C4<0111>; +L_0x133c050/d .functor AND 1, L_0x133c790, L_0x133c980, C4<1>, C4<1>; +L_0x133c050 .delay 1 (30000,30000,30000) L_0x133c050/d; +v0x11dd0e0_0 .net *"_s0", 0 0, L_0x133c790; 1 drivers +v0x11dd1c0_0 .net *"_s1", 0 0, L_0x133c980; 1 drivers +S_0x11ddd80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11da950; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1eaaac0/d .functor OR 1, L_0x1eaab80, L_0x1eaad30, C4<0>, C4<0>; -L_0x1eaaac0 .delay 1 (30000,30000,30000) L_0x1eaaac0/d; -v0x1d4ccd0_0 .net *"_s10", 0 0, L_0x1eaab80; 1 drivers -v0x1d4cdb0_0 .net *"_s12", 0 0, L_0x1eaad30; 1 drivers -v0x1d4ce90_0 .net "in", 7 0, L_0x1ea8ac0; alias, 1 drivers -v0x1d4cf60_0 .net "ors", 1 0, L_0x1eaa8e0; 1 drivers -v0x1d4d020_0 .net "out", 0 0, L_0x1eaaac0; alias, 1 drivers -L_0x1ea9cb0 .part L_0x1ea8ac0, 0, 4; -L_0x1eaa8e0 .concat8 [ 1 1 0 0], L_0x1ea99a0, L_0x1eaa5d0; -L_0x1eaaa20 .part L_0x1ea8ac0, 4, 4; -L_0x1eaab80 .part L_0x1eaa8e0, 0, 1; -L_0x1eaad30 .part L_0x1eaa8e0, 1, 1; -S_0x1d4b340 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d4b180; +L_0x133e3d0/d .functor OR 1, L_0x133e490, L_0x133e640, C4<0>, C4<0>; +L_0x133e3d0 .delay 1 (30000,30000,30000) L_0x133e3d0/d; +v0x11df8d0_0 .net *"_s10", 0 0, L_0x133e490; 1 drivers +v0x11df9b0_0 .net *"_s12", 0 0, L_0x133e640; 1 drivers +v0x11dfa90_0 .net "in", 7 0, L_0x133c3d0; alias, 1 drivers +v0x11dfb60_0 .net "ors", 1 0, L_0x133e1f0; 1 drivers +v0x11dfc20_0 .net "out", 0 0, L_0x133e3d0; alias, 1 drivers +L_0x133d5c0 .part L_0x133c3d0, 0, 4; +L_0x133e1f0 .concat8 [ 1 1 0 0], L_0x133d2b0, L_0x133dee0; +L_0x133e330 .part L_0x133c3d0, 4, 4; +L_0x133e490 .part L_0x133e1f0, 0, 1; +L_0x133e640 .part L_0x133e1f0, 1, 1; +S_0x11ddf40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11ddd80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1ea9160/d .functor OR 1, L_0x1ea9220, L_0x1ea9380, C4<0>, C4<0>; -L_0x1ea9160 .delay 1 (30000,30000,30000) L_0x1ea9160/d; -L_0x1ea95b0/d .functor OR 1, L_0x1ea96c0, L_0x1ea9820, C4<0>, C4<0>; -L_0x1ea95b0 .delay 1 (30000,30000,30000) L_0x1ea95b0/d; -L_0x1ea99a0/d .functor OR 1, L_0x1ea9a10, L_0x1ea9bc0, C4<0>, C4<0>; -L_0x1ea99a0 .delay 1 (30000,30000,30000) L_0x1ea99a0/d; -v0x1d4b590_0 .net *"_s0", 0 0, L_0x1ea9160; 1 drivers -v0x1d4b690_0 .net *"_s10", 0 0, L_0x1ea96c0; 1 drivers -v0x1d4b770_0 .net *"_s12", 0 0, L_0x1ea9820; 1 drivers -v0x1d4b830_0 .net *"_s14", 0 0, L_0x1ea9a10; 1 drivers -v0x1d4b910_0 .net *"_s16", 0 0, L_0x1ea9bc0; 1 drivers -v0x1d4ba40_0 .net *"_s3", 0 0, L_0x1ea9220; 1 drivers -v0x1d4bb20_0 .net *"_s5", 0 0, L_0x1ea9380; 1 drivers -v0x1d4bc00_0 .net *"_s6", 0 0, L_0x1ea95b0; 1 drivers -v0x1d4bce0_0 .net "in", 3 0, L_0x1ea9cb0; 1 drivers -v0x1d4be50_0 .net "ors", 1 0, L_0x1ea94c0; 1 drivers -v0x1d4bf30_0 .net "out", 0 0, L_0x1ea99a0; 1 drivers -L_0x1ea9220 .part L_0x1ea9cb0, 0, 1; -L_0x1ea9380 .part L_0x1ea9cb0, 1, 1; -L_0x1ea94c0 .concat8 [ 1 1 0 0], L_0x1ea9160, L_0x1ea95b0; -L_0x1ea96c0 .part L_0x1ea9cb0, 2, 1; -L_0x1ea9820 .part L_0x1ea9cb0, 3, 1; -L_0x1ea9a10 .part L_0x1ea94c0, 0, 1; -L_0x1ea9bc0 .part L_0x1ea94c0, 1, 1; -S_0x1d4c050 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d4b180; +L_0x133ca70/d .functor OR 1, L_0x133cb30, L_0x133cc90, C4<0>, C4<0>; +L_0x133ca70 .delay 1 (30000,30000,30000) L_0x133ca70/d; +L_0x133cec0/d .functor OR 1, L_0x133cfd0, L_0x133d130, C4<0>, C4<0>; +L_0x133cec0 .delay 1 (30000,30000,30000) L_0x133cec0/d; +L_0x133d2b0/d .functor OR 1, L_0x133d320, L_0x133d4d0, C4<0>, C4<0>; +L_0x133d2b0 .delay 1 (30000,30000,30000) L_0x133d2b0/d; +v0x11de190_0 .net *"_s0", 0 0, L_0x133ca70; 1 drivers +v0x11de290_0 .net *"_s10", 0 0, L_0x133cfd0; 1 drivers +v0x11de370_0 .net *"_s12", 0 0, L_0x133d130; 1 drivers +v0x11de430_0 .net *"_s14", 0 0, L_0x133d320; 1 drivers +v0x11de510_0 .net *"_s16", 0 0, L_0x133d4d0; 1 drivers +v0x11de640_0 .net *"_s3", 0 0, L_0x133cb30; 1 drivers +v0x11de720_0 .net *"_s5", 0 0, L_0x133cc90; 1 drivers +v0x11de800_0 .net *"_s6", 0 0, L_0x133cec0; 1 drivers +v0x11de8e0_0 .net "in", 3 0, L_0x133d5c0; 1 drivers +v0x11dea50_0 .net "ors", 1 0, L_0x133cdd0; 1 drivers +v0x11deb30_0 .net "out", 0 0, L_0x133d2b0; 1 drivers +L_0x133cb30 .part L_0x133d5c0, 0, 1; +L_0x133cc90 .part L_0x133d5c0, 1, 1; +L_0x133cdd0 .concat8 [ 1 1 0 0], L_0x133ca70, L_0x133cec0; +L_0x133cfd0 .part L_0x133d5c0, 2, 1; +L_0x133d130 .part L_0x133d5c0, 3, 1; +L_0x133d320 .part L_0x133cdd0, 0, 1; +L_0x133d4d0 .part L_0x133cdd0, 1, 1; +S_0x11dec50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11ddd80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1ea9de0/d .functor OR 1, L_0x1ea9e50, L_0x1ea9fb0, C4<0>, C4<0>; -L_0x1ea9de0 .delay 1 (30000,30000,30000) L_0x1ea9de0/d; -L_0x1eaa1e0/d .functor OR 1, L_0x1eaa2f0, L_0x1eaa450, C4<0>, C4<0>; -L_0x1eaa1e0 .delay 1 (30000,30000,30000) L_0x1eaa1e0/d; -L_0x1eaa5d0/d .functor OR 1, L_0x1eaa640, L_0x1eaa7f0, C4<0>, C4<0>; -L_0x1eaa5d0 .delay 1 (30000,30000,30000) L_0x1eaa5d0/d; -v0x1d4c210_0 .net *"_s0", 0 0, L_0x1ea9de0; 1 drivers -v0x1d4c310_0 .net *"_s10", 0 0, L_0x1eaa2f0; 1 drivers -v0x1d4c3f0_0 .net *"_s12", 0 0, L_0x1eaa450; 1 drivers -v0x1d4c4b0_0 .net *"_s14", 0 0, L_0x1eaa640; 1 drivers -v0x1d4c590_0 .net *"_s16", 0 0, L_0x1eaa7f0; 1 drivers -v0x1d4c6c0_0 .net *"_s3", 0 0, L_0x1ea9e50; 1 drivers -v0x1d4c7a0_0 .net *"_s5", 0 0, L_0x1ea9fb0; 1 drivers -v0x1d4c880_0 .net *"_s6", 0 0, L_0x1eaa1e0; 1 drivers -v0x1d4c960_0 .net "in", 3 0, L_0x1eaaa20; 1 drivers -v0x1d4cad0_0 .net "ors", 1 0, L_0x1eaa0f0; 1 drivers -v0x1d4cbb0_0 .net "out", 0 0, L_0x1eaa5d0; 1 drivers -L_0x1ea9e50 .part L_0x1eaaa20, 0, 1; -L_0x1ea9fb0 .part L_0x1eaaa20, 1, 1; -L_0x1eaa0f0 .concat8 [ 1 1 0 0], L_0x1ea9de0, L_0x1eaa1e0; -L_0x1eaa2f0 .part L_0x1eaaa20, 2, 1; -L_0x1eaa450 .part L_0x1eaaa20, 3, 1; -L_0x1eaa640 .part L_0x1eaa0f0, 0, 1; -L_0x1eaa7f0 .part L_0x1eaa0f0, 1, 1; -S_0x1d4d4c0 .scope module, "resMux" "unaryMultiplexor" 4 148, 4 69 0, S_0x1d465f0; +L_0x133d6f0/d .functor OR 1, L_0x133d760, L_0x133d8c0, C4<0>, C4<0>; +L_0x133d6f0 .delay 1 (30000,30000,30000) L_0x133d6f0/d; +L_0x133daf0/d .functor OR 1, L_0x133dc00, L_0x133dd60, C4<0>, C4<0>; +L_0x133daf0 .delay 1 (30000,30000,30000) L_0x133daf0/d; +L_0x133dee0/d .functor OR 1, L_0x133df50, L_0x133e100, C4<0>, C4<0>; +L_0x133dee0 .delay 1 (30000,30000,30000) L_0x133dee0/d; +v0x11dee10_0 .net *"_s0", 0 0, L_0x133d6f0; 1 drivers +v0x11def10_0 .net *"_s10", 0 0, L_0x133dc00; 1 drivers +v0x11deff0_0 .net *"_s12", 0 0, L_0x133dd60; 1 drivers +v0x11df0b0_0 .net *"_s14", 0 0, L_0x133df50; 1 drivers +v0x11df190_0 .net *"_s16", 0 0, L_0x133e100; 1 drivers +v0x11df2c0_0 .net *"_s3", 0 0, L_0x133d760; 1 drivers +v0x11df3a0_0 .net *"_s5", 0 0, L_0x133d8c0; 1 drivers +v0x11df480_0 .net *"_s6", 0 0, L_0x133daf0; 1 drivers +v0x11df560_0 .net "in", 3 0, L_0x133e330; 1 drivers +v0x11df6d0_0 .net "ors", 1 0, L_0x133da00; 1 drivers +v0x11df7b0_0 .net "out", 0 0, L_0x133dee0; 1 drivers +L_0x133d760 .part L_0x133e330, 0, 1; +L_0x133d8c0 .part L_0x133e330, 1, 1; +L_0x133da00 .concat8 [ 1 1 0 0], L_0x133d6f0, L_0x133daf0; +L_0x133dc00 .part L_0x133e330, 2, 1; +L_0x133dd60 .part L_0x133e330, 3, 1; +L_0x133df50 .part L_0x133da00, 0, 1; +L_0x133e100 .part L_0x133da00, 1, 1; +S_0x11e00c0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11d91f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1d528f0_0 .net "ands", 7 0, L_0x1ea5080; 1 drivers -v0x1d52a00_0 .net "in", 7 0, L_0x1ea34e0; alias, 1 drivers -v0x1d52ac0_0 .net "out", 0 0, L_0x1ea7080; alias, 1 drivers -v0x1d52b90_0 .net "sel", 7 0, v0x1d6daa0_0; alias, 1 drivers -S_0x1d4d710 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1d4d4c0; +v0x11e54f0_0 .net "ands", 7 0, L_0x1338990; 1 drivers +v0x11e5600_0 .net "in", 7 0, L_0x1336df0; alias, 1 drivers +v0x11e56c0_0 .net "out", 0 0, L_0x133a990; alias, 1 drivers +v0x11e5790_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers +S_0x11e0310 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11e00c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1d4fe50_0 .net "A", 7 0, L_0x1ea34e0; alias, 1 drivers -v0x1d4ff50_0 .net "B", 7 0, v0x1d6daa0_0; alias, 1 drivers -v0x1d50010_0 .net *"_s0", 0 0, L_0x1ea3870; 1 drivers -v0x1d500d0_0 .net *"_s12", 0 0, L_0x1ea4230; 1 drivers -v0x1d501b0_0 .net *"_s16", 0 0, L_0x1ea4590; 1 drivers -v0x1d502e0_0 .net *"_s20", 0 0, L_0x1ea49c0; 1 drivers -v0x1d503c0_0 .net *"_s24", 0 0, L_0x1ea4cf0; 1 drivers -v0x1d504a0_0 .net *"_s28", 0 0, L_0x1ea4c80; 1 drivers -v0x1d50580_0 .net *"_s4", 0 0, L_0x1ea3c10; 1 drivers -v0x1d506f0_0 .net *"_s8", 0 0, L_0x1ea3f20; 1 drivers -v0x1d507d0_0 .net "out", 7 0, L_0x1ea5080; alias, 1 drivers -L_0x1ea3980 .part L_0x1ea34e0, 0, 1; -L_0x1ea3b70 .part v0x1d6daa0_0, 0, 1; -L_0x1ea3cd0 .part L_0x1ea34e0, 1, 1; -L_0x1ea3e30 .part v0x1d6daa0_0, 1, 1; -L_0x1ea3fe0 .part L_0x1ea34e0, 2, 1; -L_0x1ea4140 .part v0x1d6daa0_0, 2, 1; -L_0x1ea42f0 .part L_0x1ea34e0, 3, 1; -L_0x1ea4450 .part v0x1d6daa0_0, 3, 1; -L_0x1ea4650 .part L_0x1ea34e0, 4, 1; -L_0x1ea48c0 .part v0x1d6daa0_0, 4, 1; -L_0x1ea4a30 .part L_0x1ea34e0, 5, 1; -L_0x1ea4b90 .part v0x1d6daa0_0, 5, 1; -L_0x1ea4db0 .part L_0x1ea34e0, 6, 1; -L_0x1ea4f10 .part v0x1d6daa0_0, 6, 1; -LS_0x1ea5080_0_0 .concat8 [ 1 1 1 1], L_0x1ea3870, L_0x1ea3c10, L_0x1ea3f20, L_0x1ea4230; -LS_0x1ea5080_0_4 .concat8 [ 1 1 1 1], L_0x1ea4590, L_0x1ea49c0, L_0x1ea4cf0, L_0x1ea4c80; -L_0x1ea5080 .concat8 [ 4 4 0 0], LS_0x1ea5080_0_0, LS_0x1ea5080_0_4; -L_0x1ea5440 .part L_0x1ea34e0, 7, 1; -L_0x1ea5630 .part v0x1d6daa0_0, 7, 1; -S_0x1d4d950 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4db60 .param/l "i" 0 4 54, +C4<00>; -L_0x1ea3870/d .functor AND 1, L_0x1ea3980, L_0x1ea3b70, C4<1>, C4<1>; -L_0x1ea3870 .delay 1 (30000,30000,30000) L_0x1ea3870/d; -v0x1d4dc40_0 .net *"_s0", 0 0, L_0x1ea3980; 1 drivers -v0x1d4dd20_0 .net *"_s1", 0 0, L_0x1ea3b70; 1 drivers -S_0x1d4de00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4e010 .param/l "i" 0 4 54, +C4<01>; -L_0x1ea3c10/d .functor AND 1, L_0x1ea3cd0, L_0x1ea3e30, C4<1>, C4<1>; -L_0x1ea3c10 .delay 1 (30000,30000,30000) L_0x1ea3c10/d; -v0x1d4e0d0_0 .net *"_s0", 0 0, L_0x1ea3cd0; 1 drivers -v0x1d4e1b0_0 .net *"_s1", 0 0, L_0x1ea3e30; 1 drivers -S_0x1d4e290 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4e4d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1ea3f20/d .functor AND 1, L_0x1ea3fe0, L_0x1ea4140, C4<1>, C4<1>; -L_0x1ea3f20 .delay 1 (30000,30000,30000) L_0x1ea3f20/d; -v0x1d4e570_0 .net *"_s0", 0 0, L_0x1ea3fe0; 1 drivers -v0x1d4e650_0 .net *"_s1", 0 0, L_0x1ea4140; 1 drivers -S_0x1d4e730 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4e940 .param/l "i" 0 4 54, +C4<011>; -L_0x1ea4230/d .functor AND 1, L_0x1ea42f0, L_0x1ea4450, C4<1>, C4<1>; -L_0x1ea4230 .delay 1 (30000,30000,30000) L_0x1ea4230/d; -v0x1d4ea00_0 .net *"_s0", 0 0, L_0x1ea42f0; 1 drivers -v0x1d4eae0_0 .net *"_s1", 0 0, L_0x1ea4450; 1 drivers -S_0x1d4ebc0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4ee20 .param/l "i" 0 4 54, +C4<0100>; -L_0x1ea4590/d .functor AND 1, L_0x1ea4650, L_0x1ea48c0, C4<1>, C4<1>; -L_0x1ea4590 .delay 1 (30000,30000,30000) L_0x1ea4590/d; -v0x1d4eee0_0 .net *"_s0", 0 0, L_0x1ea4650; 1 drivers -v0x1d4efc0_0 .net *"_s1", 0 0, L_0x1ea48c0; 1 drivers -S_0x1d4f0a0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4f2b0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1ea49c0/d .functor AND 1, L_0x1ea4a30, L_0x1ea4b90, C4<1>, C4<1>; -L_0x1ea49c0 .delay 1 (30000,30000,30000) L_0x1ea49c0/d; -v0x1d4f370_0 .net *"_s0", 0 0, L_0x1ea4a30; 1 drivers -v0x1d4f450_0 .net *"_s1", 0 0, L_0x1ea4b90; 1 drivers -S_0x1d4f530 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4f740 .param/l "i" 0 4 54, +C4<0110>; -L_0x1ea4cf0/d .functor AND 1, L_0x1ea4db0, L_0x1ea4f10, C4<1>, C4<1>; -L_0x1ea4cf0 .delay 1 (30000,30000,30000) L_0x1ea4cf0/d; -v0x1d4f800_0 .net *"_s0", 0 0, L_0x1ea4db0; 1 drivers -v0x1d4f8e0_0 .net *"_s1", 0 0, L_0x1ea4f10; 1 drivers -S_0x1d4f9c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1d4d710; - .timescale -9 -12; -P_0x1d4fbd0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1ea4c80/d .functor AND 1, L_0x1ea5440, L_0x1ea5630, C4<1>, C4<1>; -L_0x1ea4c80 .delay 1 (30000,30000,30000) L_0x1ea4c80/d; -v0x1d4fc90_0 .net *"_s0", 0 0, L_0x1ea5440; 1 drivers -v0x1d4fd70_0 .net *"_s1", 0 0, L_0x1ea5630; 1 drivers -S_0x1d50930 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1d4d4c0; +v0x11e2a50_0 .net "A", 7 0, L_0x1336df0; alias, 1 drivers +v0x11e2b50_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers +v0x11e2c10_0 .net *"_s0", 0 0, L_0x1337180; 1 drivers +v0x11e2cd0_0 .net *"_s12", 0 0, L_0x1337b40; 1 drivers +v0x11e2db0_0 .net *"_s16", 0 0, L_0x1337ea0; 1 drivers +v0x11e2ee0_0 .net *"_s20", 0 0, L_0x13382d0; 1 drivers +v0x11e2fc0_0 .net *"_s24", 0 0, L_0x1338600; 1 drivers +v0x11e30a0_0 .net *"_s28", 0 0, L_0x1338590; 1 drivers +v0x11e3180_0 .net *"_s4", 0 0, L_0x1337520; 1 drivers +v0x11e32f0_0 .net *"_s8", 0 0, L_0x1337830; 1 drivers +v0x11e33d0_0 .net "out", 7 0, L_0x1338990; alias, 1 drivers +L_0x1337290 .part L_0x1336df0, 0, 1; +L_0x1337480 .part v0x12010b0_0, 0, 1; +L_0x13375e0 .part L_0x1336df0, 1, 1; +L_0x1337740 .part v0x12010b0_0, 1, 1; +L_0x13378f0 .part L_0x1336df0, 2, 1; +L_0x1337a50 .part v0x12010b0_0, 2, 1; +L_0x1337c00 .part L_0x1336df0, 3, 1; +L_0x1337d60 .part v0x12010b0_0, 3, 1; +L_0x1337f60 .part L_0x1336df0, 4, 1; +L_0x13381d0 .part v0x12010b0_0, 4, 1; +L_0x1338340 .part L_0x1336df0, 5, 1; +L_0x13384a0 .part v0x12010b0_0, 5, 1; +L_0x13386c0 .part L_0x1336df0, 6, 1; +L_0x1338820 .part v0x12010b0_0, 6, 1; +LS_0x1338990_0_0 .concat8 [ 1 1 1 1], L_0x1337180, L_0x1337520, L_0x1337830, L_0x1337b40; +LS_0x1338990_0_4 .concat8 [ 1 1 1 1], L_0x1337ea0, L_0x13382d0, L_0x1338600, L_0x1338590; +L_0x1338990 .concat8 [ 4 4 0 0], LS_0x1338990_0_0, LS_0x1338990_0_4; +L_0x1338d50 .part L_0x1336df0, 7, 1; +L_0x1338f40 .part v0x12010b0_0, 7, 1; +S_0x11e0550 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e0760 .param/l "i" 0 4 54, +C4<00>; +L_0x1337180/d .functor AND 1, L_0x1337290, L_0x1337480, C4<1>, C4<1>; +L_0x1337180 .delay 1 (30000,30000,30000) L_0x1337180/d; +v0x11e0840_0 .net *"_s0", 0 0, L_0x1337290; 1 drivers +v0x11e0920_0 .net *"_s1", 0 0, L_0x1337480; 1 drivers +S_0x11e0a00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e0c10 .param/l "i" 0 4 54, +C4<01>; +L_0x1337520/d .functor AND 1, L_0x13375e0, L_0x1337740, C4<1>, C4<1>; +L_0x1337520 .delay 1 (30000,30000,30000) L_0x1337520/d; +v0x11e0cd0_0 .net *"_s0", 0 0, L_0x13375e0; 1 drivers +v0x11e0db0_0 .net *"_s1", 0 0, L_0x1337740; 1 drivers +S_0x11e0e90 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e10d0 .param/l "i" 0 4 54, +C4<010>; +L_0x1337830/d .functor AND 1, L_0x13378f0, L_0x1337a50, C4<1>, C4<1>; +L_0x1337830 .delay 1 (30000,30000,30000) L_0x1337830/d; +v0x11e1170_0 .net *"_s0", 0 0, L_0x13378f0; 1 drivers +v0x11e1250_0 .net *"_s1", 0 0, L_0x1337a50; 1 drivers +S_0x11e1330 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e1540 .param/l "i" 0 4 54, +C4<011>; +L_0x1337b40/d .functor AND 1, L_0x1337c00, L_0x1337d60, C4<1>, C4<1>; +L_0x1337b40 .delay 1 (30000,30000,30000) L_0x1337b40/d; +v0x11e1600_0 .net *"_s0", 0 0, L_0x1337c00; 1 drivers +v0x11e16e0_0 .net *"_s1", 0 0, L_0x1337d60; 1 drivers +S_0x11e17c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e1a20 .param/l "i" 0 4 54, +C4<0100>; +L_0x1337ea0/d .functor AND 1, L_0x1337f60, L_0x13381d0, C4<1>, C4<1>; +L_0x1337ea0 .delay 1 (30000,30000,30000) L_0x1337ea0/d; +v0x11e1ae0_0 .net *"_s0", 0 0, L_0x1337f60; 1 drivers +v0x11e1bc0_0 .net *"_s1", 0 0, L_0x13381d0; 1 drivers +S_0x11e1ca0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e1eb0 .param/l "i" 0 4 54, +C4<0101>; +L_0x13382d0/d .functor AND 1, L_0x1338340, L_0x13384a0, C4<1>, C4<1>; +L_0x13382d0 .delay 1 (30000,30000,30000) L_0x13382d0/d; +v0x11e1f70_0 .net *"_s0", 0 0, L_0x1338340; 1 drivers +v0x11e2050_0 .net *"_s1", 0 0, L_0x13384a0; 1 drivers +S_0x11e2130 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e2340 .param/l "i" 0 4 54, +C4<0110>; +L_0x1338600/d .functor AND 1, L_0x13386c0, L_0x1338820, C4<1>, C4<1>; +L_0x1338600 .delay 1 (30000,30000,30000) L_0x1338600/d; +v0x11e2400_0 .net *"_s0", 0 0, L_0x13386c0; 1 drivers +v0x11e24e0_0 .net *"_s1", 0 0, L_0x1338820; 1 drivers +S_0x11e25c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11e0310; + .timescale -9 -12; +P_0x11e27d0 .param/l "i" 0 4 54, +C4<0111>; +L_0x1338590/d .functor AND 1, L_0x1338d50, L_0x1338f40, C4<1>, C4<1>; +L_0x1338590 .delay 1 (30000,30000,30000) L_0x1338590/d; +v0x11e2890_0 .net *"_s0", 0 0, L_0x1338d50; 1 drivers +v0x11e2970_0 .net *"_s1", 0 0, L_0x1338f40; 1 drivers +S_0x11e3530 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11e00c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1ea7080/d .functor OR 1, L_0x1ea7140, L_0x1ea72f0, C4<0>, C4<0>; -L_0x1ea7080 .delay 1 (30000,30000,30000) L_0x1ea7080/d; -v0x1d52480_0 .net *"_s10", 0 0, L_0x1ea7140; 1 drivers -v0x1d52560_0 .net *"_s12", 0 0, L_0x1ea72f0; 1 drivers -v0x1d52640_0 .net "in", 7 0, L_0x1ea5080; alias, 1 drivers -v0x1d52710_0 .net "ors", 1 0, L_0x1ea6ea0; 1 drivers -v0x1d527d0_0 .net "out", 0 0, L_0x1ea7080; alias, 1 drivers -L_0x1ea6270 .part L_0x1ea5080, 0, 4; -L_0x1ea6ea0 .concat8 [ 1 1 0 0], L_0x1ea5f60, L_0x1ea6b90; -L_0x1ea6fe0 .part L_0x1ea5080, 4, 4; -L_0x1ea7140 .part L_0x1ea6ea0, 0, 1; -L_0x1ea72f0 .part L_0x1ea6ea0, 1, 1; -S_0x1d50af0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1d50930; +L_0x133a990/d .functor OR 1, L_0x133aa50, L_0x133ac00, C4<0>, C4<0>; +L_0x133a990 .delay 1 (30000,30000,30000) L_0x133a990/d; +v0x11e5080_0 .net *"_s10", 0 0, L_0x133aa50; 1 drivers +v0x11e5160_0 .net *"_s12", 0 0, L_0x133ac00; 1 drivers +v0x11e5240_0 .net "in", 7 0, L_0x1338990; alias, 1 drivers +v0x11e5310_0 .net "ors", 1 0, L_0x133a7b0; 1 drivers +v0x11e53d0_0 .net "out", 0 0, L_0x133a990; alias, 1 drivers +L_0x1339b80 .part L_0x1338990, 0, 4; +L_0x133a7b0 .concat8 [ 1 1 0 0], L_0x1339870, L_0x133a4a0; +L_0x133a8f0 .part L_0x1338990, 4, 4; +L_0x133aa50 .part L_0x133a7b0, 0, 1; +L_0x133ac00 .part L_0x133a7b0, 1, 1; +S_0x11e36f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11e3530; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1ea5720/d .functor OR 1, L_0x1ea57e0, L_0x1ea5940, C4<0>, C4<0>; -L_0x1ea5720 .delay 1 (30000,30000,30000) L_0x1ea5720/d; -L_0x1ea5b70/d .functor OR 1, L_0x1ea5c80, L_0x1ea5de0, C4<0>, C4<0>; -L_0x1ea5b70 .delay 1 (30000,30000,30000) L_0x1ea5b70/d; -L_0x1ea5f60/d .functor OR 1, L_0x1ea5fd0, L_0x1ea6180, C4<0>, C4<0>; -L_0x1ea5f60 .delay 1 (30000,30000,30000) L_0x1ea5f60/d; -v0x1d50d40_0 .net *"_s0", 0 0, L_0x1ea5720; 1 drivers -v0x1d50e40_0 .net *"_s10", 0 0, L_0x1ea5c80; 1 drivers -v0x1d50f20_0 .net *"_s12", 0 0, L_0x1ea5de0; 1 drivers -v0x1d50fe0_0 .net *"_s14", 0 0, L_0x1ea5fd0; 1 drivers -v0x1d510c0_0 .net *"_s16", 0 0, L_0x1ea6180; 1 drivers -v0x1d511f0_0 .net *"_s3", 0 0, L_0x1ea57e0; 1 drivers -v0x1d512d0_0 .net *"_s5", 0 0, L_0x1ea5940; 1 drivers -v0x1d513b0_0 .net *"_s6", 0 0, L_0x1ea5b70; 1 drivers -v0x1d51490_0 .net "in", 3 0, L_0x1ea6270; 1 drivers -v0x1d51600_0 .net "ors", 1 0, L_0x1ea5a80; 1 drivers -v0x1d516e0_0 .net "out", 0 0, L_0x1ea5f60; 1 drivers -L_0x1ea57e0 .part L_0x1ea6270, 0, 1; -L_0x1ea5940 .part L_0x1ea6270, 1, 1; -L_0x1ea5a80 .concat8 [ 1 1 0 0], L_0x1ea5720, L_0x1ea5b70; -L_0x1ea5c80 .part L_0x1ea6270, 2, 1; -L_0x1ea5de0 .part L_0x1ea6270, 3, 1; -L_0x1ea5fd0 .part L_0x1ea5a80, 0, 1; -L_0x1ea6180 .part L_0x1ea5a80, 1, 1; -S_0x1d51800 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1d50930; +L_0x1339030/d .functor OR 1, L_0x13390f0, L_0x1339250, C4<0>, C4<0>; +L_0x1339030 .delay 1 (30000,30000,30000) L_0x1339030/d; +L_0x1339480/d .functor OR 1, L_0x1339590, L_0x13396f0, C4<0>, C4<0>; +L_0x1339480 .delay 1 (30000,30000,30000) L_0x1339480/d; +L_0x1339870/d .functor OR 1, L_0x13398e0, L_0x1339a90, C4<0>, C4<0>; +L_0x1339870 .delay 1 (30000,30000,30000) L_0x1339870/d; +v0x11e3940_0 .net *"_s0", 0 0, L_0x1339030; 1 drivers +v0x11e3a40_0 .net *"_s10", 0 0, L_0x1339590; 1 drivers +v0x11e3b20_0 .net *"_s12", 0 0, L_0x13396f0; 1 drivers +v0x11e3be0_0 .net *"_s14", 0 0, L_0x13398e0; 1 drivers +v0x11e3cc0_0 .net *"_s16", 0 0, L_0x1339a90; 1 drivers +v0x11e3df0_0 .net *"_s3", 0 0, L_0x13390f0; 1 drivers +v0x11e3ed0_0 .net *"_s5", 0 0, L_0x1339250; 1 drivers +v0x11e3fb0_0 .net *"_s6", 0 0, L_0x1339480; 1 drivers +v0x11e4090_0 .net "in", 3 0, L_0x1339b80; 1 drivers +v0x11e4200_0 .net "ors", 1 0, L_0x1339390; 1 drivers +v0x11e42e0_0 .net "out", 0 0, L_0x1339870; 1 drivers +L_0x13390f0 .part L_0x1339b80, 0, 1; +L_0x1339250 .part L_0x1339b80, 1, 1; +L_0x1339390 .concat8 [ 1 1 0 0], L_0x1339030, L_0x1339480; +L_0x1339590 .part L_0x1339b80, 2, 1; +L_0x13396f0 .part L_0x1339b80, 3, 1; +L_0x13398e0 .part L_0x1339390, 0, 1; +L_0x1339a90 .part L_0x1339390, 1, 1; +S_0x11e4400 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11e3530; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1ea63a0/d .functor OR 1, L_0x1ea6410, L_0x1ea6570, C4<0>, C4<0>; -L_0x1ea63a0 .delay 1 (30000,30000,30000) L_0x1ea63a0/d; -L_0x1ea67a0/d .functor OR 1, L_0x1ea68b0, L_0x1ea6a10, C4<0>, C4<0>; -L_0x1ea67a0 .delay 1 (30000,30000,30000) L_0x1ea67a0/d; -L_0x1ea6b90/d .functor OR 1, L_0x1ea6c00, L_0x1ea6db0, C4<0>, C4<0>; -L_0x1ea6b90 .delay 1 (30000,30000,30000) L_0x1ea6b90/d; -v0x1d519c0_0 .net *"_s0", 0 0, L_0x1ea63a0; 1 drivers -v0x1d51ac0_0 .net *"_s10", 0 0, L_0x1ea68b0; 1 drivers -v0x1d51ba0_0 .net *"_s12", 0 0, L_0x1ea6a10; 1 drivers -v0x1d51c60_0 .net *"_s14", 0 0, L_0x1ea6c00; 1 drivers -v0x1d51d40_0 .net *"_s16", 0 0, L_0x1ea6db0; 1 drivers -v0x1d51e70_0 .net *"_s3", 0 0, L_0x1ea6410; 1 drivers -v0x1d51f50_0 .net *"_s5", 0 0, L_0x1ea6570; 1 drivers -v0x1d52030_0 .net *"_s6", 0 0, L_0x1ea67a0; 1 drivers -v0x1d52110_0 .net "in", 3 0, L_0x1ea6fe0; 1 drivers -v0x1d52280_0 .net "ors", 1 0, L_0x1ea66b0; 1 drivers -v0x1d52360_0 .net "out", 0 0, L_0x1ea6b90; 1 drivers -L_0x1ea6410 .part L_0x1ea6fe0, 0, 1; -L_0x1ea6570 .part L_0x1ea6fe0, 1, 1; -L_0x1ea66b0 .concat8 [ 1 1 0 0], L_0x1ea63a0, L_0x1ea67a0; -L_0x1ea68b0 .part L_0x1ea6fe0, 2, 1; -L_0x1ea6a10 .part L_0x1ea6fe0, 3, 1; -L_0x1ea6c00 .part L_0x1ea66b0, 0, 1; -L_0x1ea6db0 .part L_0x1ea66b0, 1, 1; -S_0x1d52c70 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d465f0; +L_0x1339cb0/d .functor OR 1, L_0x1339d20, L_0x1339e80, C4<0>, C4<0>; +L_0x1339cb0 .delay 1 (30000,30000,30000) L_0x1339cb0/d; +L_0x133a0b0/d .functor OR 1, L_0x133a1c0, L_0x133a320, C4<0>, C4<0>; +L_0x133a0b0 .delay 1 (30000,30000,30000) L_0x133a0b0/d; +L_0x133a4a0/d .functor OR 1, L_0x133a510, L_0x133a6c0, C4<0>, C4<0>; +L_0x133a4a0 .delay 1 (30000,30000,30000) L_0x133a4a0/d; +v0x11e45c0_0 .net *"_s0", 0 0, L_0x1339cb0; 1 drivers +v0x11e46c0_0 .net *"_s10", 0 0, L_0x133a1c0; 1 drivers +v0x11e47a0_0 .net *"_s12", 0 0, L_0x133a320; 1 drivers +v0x11e4860_0 .net *"_s14", 0 0, L_0x133a510; 1 drivers +v0x11e4940_0 .net *"_s16", 0 0, L_0x133a6c0; 1 drivers +v0x11e4a70_0 .net *"_s3", 0 0, L_0x1339d20; 1 drivers +v0x11e4b50_0 .net *"_s5", 0 0, L_0x1339e80; 1 drivers +v0x11e4c30_0 .net *"_s6", 0 0, L_0x133a0b0; 1 drivers +v0x11e4d10_0 .net "in", 3 0, L_0x133a8f0; 1 drivers +v0x11e4e80_0 .net "ors", 1 0, L_0x1339fc0; 1 drivers +v0x11e4f60_0 .net "out", 0 0, L_0x133a4a0; 1 drivers +L_0x1339d20 .part L_0x133a8f0, 0, 1; +L_0x1339e80 .part L_0x133a8f0, 1, 1; +L_0x1339fc0 .concat8 [ 1 1 0 0], L_0x1339cb0, L_0x133a0b0; +L_0x133a1c0 .part L_0x133a8f0, 2, 1; +L_0x133a320 .part L_0x133a8f0, 3, 1; +L_0x133a510 .part L_0x1339fc0, 0, 1; +L_0x133a6c0 .part L_0x1339fc0, 1, 1; +S_0x11e5870 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11d91f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -17068,755 +17078,776 @@ S_0x1d52c70 .scope module, "sltGate" "slt" 4 142, 4 101 0, S_0x1d465f0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1ea2850/d .functor XNOR 1, L_0x1eabda0, L_0x1eab190, C4<0>, C4<0>; -L_0x1ea2850 .delay 1 (20000,20000,20000) L_0x1ea2850/d; -L_0x1ea2ac0/d .functor AND 1, L_0x1eabda0, L_0x1e97580, C4<1>, C4<1>; -L_0x1ea2ac0 .delay 1 (30000,30000,30000) L_0x1ea2ac0/d; -L_0x1ea2b30/d .functor AND 1, L_0x1ea2850, L_0x1eab230, C4<1>, C4<1>; -L_0x1ea2b30 .delay 1 (30000,30000,30000) L_0x1ea2b30/d; -L_0x1ea2c90/d .functor OR 1, L_0x1ea2b30, L_0x1ea2ac0, C4<0>, C4<0>; -L_0x1ea2c90 .delay 1 (30000,30000,30000) L_0x1ea2c90/d; -v0x1d52f20_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers -v0x1d53010_0 .net "a_", 0 0, L_0x1e029c0; alias, 1 drivers -v0x1d530d0_0 .net "b", 0 0, L_0x1eab190; alias, 1 drivers -v0x1d531c0_0 .net "b_", 0 0, L_0x1e97580; alias, 1 drivers -v0x1d53260_0 .net "carryin", 0 0, L_0x1eab230; alias, 1 drivers -v0x1d533a0_0 .net "eq", 0 0, L_0x1ea2850; 1 drivers -v0x1d53460_0 .net "lt", 0 0, L_0x1ea2ac0; 1 drivers -v0x1d53520_0 .net "out", 0 0, L_0x1ea2c90; 1 drivers -v0x1d535e0_0 .net "w0", 0 0, L_0x1ea2b30; 1 drivers -S_0x1d53830 .scope module, "sub" "fullAdder" 4 140, 4 85 0, S_0x1d465f0; +L_0x1336160/d .functor XNOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; +L_0x1336160 .delay 1 (20000,20000,20000) L_0x1336160/d; +L_0x13363d0/d .functor AND 1, L_0x133f6b0, L_0x132ae60, C4<1>, C4<1>; +L_0x13363d0 .delay 1 (30000,30000,30000) L_0x13363d0/d; +L_0x1336440/d .functor AND 1, L_0x1336160, L_0x133eb40, C4<1>, C4<1>; +L_0x1336440 .delay 1 (30000,30000,30000) L_0x1336440/d; +L_0x13365a0/d .functor OR 1, L_0x1336440, L_0x13363d0, C4<0>, C4<0>; +L_0x13365a0 .delay 1 (30000,30000,30000) L_0x13365a0/d; +v0x11e5b20_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers +v0x11e5c10_0 .net "a_", 0 0, L_0x1296070; alias, 1 drivers +v0x11e5cd0_0 .net "b", 0 0, L_0x133eaa0; alias, 1 drivers +v0x11e5dc0_0 .net "b_", 0 0, L_0x132ae60; alias, 1 drivers +v0x11e5e60_0 .net "carryin", 0 0, L_0x133eb40; alias, 1 drivers +v0x11e5fa0_0 .net "eq", 0 0, L_0x1336160; 1 drivers +v0x11e6060_0 .net "lt", 0 0, L_0x13363d0; 1 drivers +v0x11e6120_0 .net "out", 0 0, L_0x13365a0; 1 drivers +v0x11e61e0_0 .net "w0", 0 0, L_0x1336440; 1 drivers +S_0x11e6430 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11d91f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1ea2630/d .functor OR 1, L_0x1ea2180, L_0x1d54a90, C4<0>, C4<0>; -L_0x1ea2630 .delay 1 (30000,30000,30000) L_0x1ea2630/d; -v0x1d54620_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers -v0x1d54770_0 .net "b", 0 0, L_0x1e97580; alias, 1 drivers -v0x1d54830_0 .net "c1", 0 0, L_0x1ea2180; 1 drivers -v0x1d548d0_0 .net "c2", 0 0, L_0x1d54a90; 1 drivers -v0x1d549a0_0 .net "carryin", 0 0, L_0x1eab230; alias, 1 drivers -v0x1d54b20_0 .net "carryout", 0 0, L_0x1ea2630; 1 drivers -v0x1d54bc0_0 .net "s1", 0 0, L_0x1ea20c0; 1 drivers -v0x1d54c60_0 .net "sum", 0 0, L_0x1ea22e0; 1 drivers -S_0x1d53a80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1d53830; +L_0x1335f40/d .functor OR 1, L_0x1335a40, L_0x11e7690, C4<0>, C4<0>; +L_0x1335f40 .delay 1 (30000,30000,30000) L_0x1335f40/d; +v0x11e7220_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers +v0x11e7370_0 .net "b", 0 0, L_0x132ae60; alias, 1 drivers +v0x11e7430_0 .net "c1", 0 0, L_0x1335a40; 1 drivers +v0x11e74d0_0 .net "c2", 0 0, L_0x11e7690; 1 drivers +v0x11e75a0_0 .net "carryin", 0 0, L_0x133eb40; alias, 1 drivers +v0x11e7720_0 .net "carryout", 0 0, L_0x1335f40; 1 drivers +v0x11e77c0_0 .net "s1", 0 0, L_0x1335980; 1 drivers +v0x11e7860_0 .net "sum", 0 0, L_0x1335ba0; 1 drivers +S_0x11e6680 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11e6430; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ea20c0/d .functor XOR 1, L_0x1eabda0, L_0x1e97580, C4<0>, C4<0>; -L_0x1ea20c0 .delay 1 (30000,30000,30000) L_0x1ea20c0/d; -L_0x1ea2180/d .functor AND 1, L_0x1eabda0, L_0x1e97580, C4<1>, C4<1>; -L_0x1ea2180 .delay 1 (30000,30000,30000) L_0x1ea2180/d; -v0x1d53ce0_0 .net "a", 0 0, L_0x1eabda0; alias, 1 drivers -v0x1d53da0_0 .net "b", 0 0, L_0x1e97580; alias, 1 drivers -v0x1d53e60_0 .net "carryout", 0 0, L_0x1ea2180; alias, 1 drivers -v0x1d53f00_0 .net "sum", 0 0, L_0x1ea20c0; alias, 1 drivers -S_0x1d54030 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1d53830; +L_0x1335980/d .functor XOR 1, L_0x133f6b0, L_0x132ae60, C4<0>, C4<0>; +L_0x1335980 .delay 1 (30000,30000,30000) L_0x1335980/d; +L_0x1335a40/d .functor AND 1, L_0x133f6b0, L_0x132ae60, C4<1>, C4<1>; +L_0x1335a40 .delay 1 (30000,30000,30000) L_0x1335a40/d; +v0x11e68e0_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers +v0x11e69a0_0 .net "b", 0 0, L_0x132ae60; alias, 1 drivers +v0x11e6a60_0 .net "carryout", 0 0, L_0x1335a40; alias, 1 drivers +v0x11e6b00_0 .net "sum", 0 0, L_0x1335980; alias, 1 drivers +S_0x11e6c30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11e6430; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1ea22e0/d .functor XOR 1, L_0x1ea20c0, L_0x1eab230, C4<0>, C4<0>; -L_0x1ea22e0 .delay 1 (30000,30000,30000) L_0x1ea22e0/d; -L_0x1d54a90/d .functor AND 1, L_0x1ea20c0, L_0x1eab230, C4<1>, C4<1>; -L_0x1d54a90 .delay 1 (30000,30000,30000) L_0x1d54a90/d; -v0x1d54290_0 .net "a", 0 0, L_0x1ea20c0; alias, 1 drivers -v0x1d54360_0 .net "b", 0 0, L_0x1eab230; alias, 1 drivers -v0x1d54400_0 .net "carryout", 0 0, L_0x1d54a90; alias, 1 drivers -v0x1d544d0_0 .net "sum", 0 0, L_0x1ea22e0; alias, 1 drivers -S_0x1d56080 .scope generate, "genblk2" "genblk2" 3 45, 3 45 0, S_0x1d46320; - .timescale -9 -12; -L_0x7f72592dc2f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x7f72592dc340 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1ea5000/d .functor OR 1, L_0x7f72592dc2f8, L_0x7f72592dc340, C4<0>, C4<0>; -L_0x1ea5000 .delay 1 (30000,30000,30000) L_0x1ea5000/d; -v0x1d56270_0 .net/2u *"_s0", 0 0, L_0x7f72592dc2f8; 1 drivers -v0x1d56350_0 .net/2u *"_s2", 0 0, L_0x7f72592dc340; 1 drivers -S_0x1d56430 .scope module, "resultOr" "or32P" 3 64, 4 60 0, S_0x1a570b0; +L_0x1335ba0/d .functor XOR 1, L_0x1335980, L_0x133eb40, C4<0>, C4<0>; +L_0x1335ba0 .delay 1 (30000,30000,30000) L_0x1335ba0/d; +L_0x11e7690/d .functor AND 1, L_0x1335980, L_0x133eb40, C4<1>, C4<1>; +L_0x11e7690 .delay 1 (30000,30000,30000) L_0x11e7690/d; +v0x11e6e90_0 .net "a", 0 0, L_0x1335980; alias, 1 drivers +v0x11e6f60_0 .net "b", 0 0, L_0x133eb40; alias, 1 drivers +v0x11e7000_0 .net "carryout", 0 0, L_0x11e7690; alias, 1 drivers +v0x11e70d0_0 .net "sum", 0 0, L_0x1335ba0; alias, 1 drivers +S_0x11e8c80 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11d8f20; + .timescale -9 -12; +L_0x2b0ab3d072f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2b0ab3d07340 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x1338910/d .functor OR 1, L_0x2b0ab3d072f8, L_0x2b0ab3d07340, C4<0>, C4<0>; +L_0x1338910 .delay 1 (30000,30000,30000) L_0x1338910/d; +v0x11e8e70_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d072f8; 1 drivers +v0x11e8f50_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d07340; 1 drivers +S_0x11e9030 .scope module, "overflowMux" "mux1" 3 68, 4 122 0, S_0xf2fc10; + .timescale -9 -12; + .port_info 0 /OUTPUT 1 "out" + .port_info 1 /INPUT 1 "a" + .port_info 2 /INPUT 1 "b" + .port_info 3 /INPUT 1 "s" +L_0x13495d0/d .functor NOT 1, L_0x1349e60, C4<0>, C4<0>, C4<0>; +L_0x13495d0 .delay 1 (10000,10000,10000) L_0x13495d0/d; +L_0x1349470/d .functor AND 1, L_0x1349360, L_0x13495d0, C4<1>, C4<1>; +L_0x1349470 .delay 1 (30000,30000,30000) L_0x1349470/d; +L_0x1349ab0/d .functor AND 1, L_0x13410d0, L_0x1349e60, C4<1>, C4<1>; +L_0x1349ab0 .delay 1 (30000,30000,30000) L_0x1349ab0/d; +L_0x1349c60/d .functor OR 1, L_0x1349470, L_0x1349ab0, C4<0>, C4<0>; +L_0x1349c60 .delay 1 (30000,30000,30000) L_0x1349c60/d; +v0x10c78a0_0 .net "a", 0 0, L_0x1349360; alias, 1 drivers +v0x11e9450_0 .net "b", 0 0, L_0x13410d0; alias, 1 drivers +v0x11e9510_0 .net "out", 0 0, L_0x1349c60; alias, 1 drivers +v0x11e95b0_0 .net "s", 0 0, L_0x1349e60; 1 drivers +v0x11e9670_0 .net "s_", 0 0, L_0x13495d0; 1 drivers +v0x11e9780_0 .net "w0", 0 0, L_0x1349470; 1 drivers +v0x11e9840_0 .net "w1", 0 0, L_0x1349ab0; 1 drivers +S_0x11e9980 .scope module, "resultOr" "or32P" 3 76, 4 60 0, S_0xf2fc10; .timescale -9 -12; .port_info 0 /OUTPUT 32 "out" .port_info 1 /INPUT 32 "A" .port_info 2 /INPUT 32 "B" -v0x1d5f9d0_0 .net "A", 31 0, L_0x1eaaf20; alias, 1 drivers -v0x1d5fad0_0 .net "B", 31 0, L_0x1eb5ac0; alias, 1 drivers -v0x1d5fbb0_0 .net *"_s0", 0 0, L_0x1eb7220; 1 drivers -v0x1d5fc70_0 .net *"_s100", 0 0, L_0x1ebc240; 1 drivers -v0x1d5fd50_0 .net *"_s104", 0 0, L_0x1ebc560; 1 drivers -v0x1d5fe80_0 .net *"_s108", 0 0, L_0x1ebc890; 1 drivers -v0x1d5ff60_0 .net *"_s112", 0 0, L_0x1ebcbd0; 1 drivers -v0x1d60040_0 .net *"_s116", 0 0, L_0x1ebced0; 1 drivers -v0x1d60120_0 .net *"_s12", 0 0, L_0x1eb7c20; 1 drivers -v0x1d60290_0 .net *"_s120", 0 0, L_0x1eba2e0; 1 drivers -v0x1d60370_0 .net *"_s124", 0 0, L_0x1ebe820; 1 drivers -v0x1d60450_0 .net *"_s16", 0 0, L_0x1eb7f80; 1 drivers -v0x1d60530_0 .net *"_s20", 0 0, L_0x1eb82f0; 1 drivers -v0x1d60610_0 .net *"_s24", 0 0, L_0x1eb8780; 1 drivers -v0x1d606f0_0 .net *"_s28", 0 0, L_0x1eb8a90; 1 drivers -v0x1d607d0_0 .net *"_s32", 0 0, L_0x1eb8da0; 1 drivers -v0x1d608b0_0 .net *"_s36", 0 0, L_0x1eb78d0; 1 drivers -v0x1d60a60_0 .net *"_s4", 0 0, L_0x1eb7580; 1 drivers -v0x1d60b00_0 .net *"_s40", 0 0, L_0x1eb90b0; 1 drivers -v0x1d60be0_0 .net *"_s44", 0 0, L_0x1eb93f0; 1 drivers -v0x1d60cc0_0 .net *"_s48", 0 0, L_0x1eb9740; 1 drivers -v0x1d60da0_0 .net *"_s52", 0 0, L_0x1eb9aa0; 1 drivers -v0x1d60e80_0 .net *"_s56", 0 0, L_0x1eb9dc0; 1 drivers -v0x1d60f60_0 .net *"_s60", 0 0, L_0x1eba670; 1 drivers -v0x1d61040_0 .net *"_s64", 0 0, L_0x1eba980; 1 drivers -v0x1d61120_0 .net *"_s68", 0 0, L_0x1eb8670; 1 drivers -v0x1d61200_0 .net *"_s72", 0 0, L_0x1ebac90; 1 drivers -v0x1d612e0_0 .net *"_s76", 0 0, L_0x1ebaf90; 1 drivers -v0x1d613c0_0 .net *"_s8", 0 0, L_0x1eb7960; 1 drivers -v0x1d614a0_0 .net *"_s80", 0 0, L_0x1ebb2a0; 1 drivers -v0x1d61580_0 .net *"_s84", 0 0, L_0x1ebb5c0; 1 drivers -v0x1d61660_0 .net *"_s88", 0 0, L_0x1ebb8f0; 1 drivers -v0x1d61740_0 .net *"_s92", 0 0, L_0x1ebbc30; 1 drivers -v0x1d60990_0 .net *"_s96", 0 0, L_0x1ebbf30; 1 drivers -v0x1d61a10_0 .net "out", 31 0, L_0x1eba0f0; alias, 1 drivers -L_0x1eb7330 .part L_0x1eaaf20, 0, 1; -L_0x1eb7490 .part L_0x1eb5ac0, 0, 1; -L_0x1eb7640 .part L_0x1eaaf20, 1, 1; -L_0x1eb7830 .part L_0x1eb5ac0, 1, 1; -L_0x1eb79d0 .part L_0x1eaaf20, 2, 1; -L_0x1eb7b30 .part L_0x1eb5ac0, 2, 1; -L_0x1eb7ce0 .part L_0x1eaaf20, 3, 1; -L_0x1eb7e40 .part L_0x1eb5ac0, 3, 1; -L_0x1eb8040 .part L_0x1eaaf20, 4, 1; -L_0x1eb81a0 .part L_0x1eb5ac0, 4, 1; -L_0x1eb8360 .part L_0x1eaaf20, 5, 1; -L_0x1eb85d0 .part L_0x1eb5ac0, 5, 1; -L_0x1eb8840 .part L_0x1eaaf20, 6, 1; -L_0x1eb89a0 .part L_0x1eb5ac0, 6, 1; -L_0x1eb8b50 .part L_0x1eaaf20, 7, 1; -L_0x1eb8cb0 .part L_0x1eb5ac0, 7, 1; -L_0x1eb8e60 .part L_0x1eaaf20, 8, 1; -L_0x1eb8fc0 .part L_0x1eb5ac0, 8, 1; -L_0x1eb91a0 .part L_0x1eaaf20, 9, 1; -L_0x1eb9300 .part L_0x1eb5ac0, 9, 1; -L_0x1eb94f0 .part L_0x1eaaf20, 10, 1; -L_0x1eb9650 .part L_0x1eb5ac0, 10, 1; -L_0x1eb9850 .part L_0x1eaaf20, 11, 1; -L_0x1eb99b0 .part L_0x1eb5ac0, 11, 1; -L_0x1eb9b70 .part L_0x1eaaf20, 12, 1; -L_0x1eb9cd0 .part L_0x1eb5ac0, 12, 1; -L_0x1eb9ea0 .part L_0x1eaaf20, 13, 1; -L_0x1eb84c0 .part L_0x1eb5ac0, 13, 1; -L_0x1eba420 .part L_0x1eaaf20, 14, 1; -L_0x1eba580 .part L_0x1eb5ac0, 14, 1; -L_0x1eba730 .part L_0x1eaaf20, 15, 1; -L_0x1eba890 .part L_0x1eb5ac0, 15, 1; -L_0x1ebaa40 .part L_0x1eaaf20, 16, 1; -L_0x1ebaba0 .part L_0x1eb5ac0, 16, 1; -L_0x1ebadb0 .part L_0x1eaaf20, 17, 1; -L_0x1ebaea0 .part L_0x1eb5ac0, 17, 1; -L_0x1ebb0c0 .part L_0x1eaaf20, 18, 1; -L_0x1ebb1b0 .part L_0x1eb5ac0, 18, 1; -L_0x1ebb3e0 .part L_0x1eaaf20, 19, 1; -L_0x1ebb4d0 .part L_0x1eb5ac0, 19, 1; -L_0x1ebb710 .part L_0x1eaaf20, 20, 1; -L_0x1ebb800 .part L_0x1eb5ac0, 20, 1; -L_0x1ebba50 .part L_0x1eaaf20, 21, 1; -L_0x1ebbb40 .part L_0x1eb5ac0, 21, 1; -L_0x1ebbda0 .part L_0x1eaaf20, 22, 1; -L_0x1ebbe40 .part L_0x1eb5ac0, 22, 1; -L_0x1ebc0b0 .part L_0x1eaaf20, 23, 1; -L_0x1ebc150 .part L_0x1eb5ac0, 23, 1; -L_0x1ebc3d0 .part L_0x1eaaf20, 24, 1; -L_0x1ebc470 .part L_0x1eb5ac0, 24, 1; -L_0x1ebc700 .part L_0x1eaaf20, 25, 1; -L_0x1ebc7a0 .part L_0x1eb5ac0, 25, 1; -L_0x1ebca40 .part L_0x1eaaf20, 26, 1; -L_0x1ebcae0 .part L_0x1eb5ac0, 26, 1; -L_0x1ebc9a0 .part L_0x1eaaf20, 27, 1; -L_0x1ebcde0 .part L_0x1eb5ac0, 27, 1; -L_0x1ebcce0 .part L_0x1eaaf20, 28, 1; -L_0x1ebd0f0 .part L_0x1eb5ac0, 28, 1; -L_0x1ebcf90 .part L_0x1eaaf20, 29, 1; -L_0x1eba000 .part L_0x1eb5ac0, 29, 1; -L_0x1ebd1e0 .part L_0x1eaaf20, 30, 1; -L_0x1ebdc30 .part L_0x1eb5ac0, 30, 1; -LS_0x1eba0f0_0_0 .concat8 [ 1 1 1 1], L_0x1eb7220, L_0x1eb7580, L_0x1eb7960, L_0x1eb7c20; -LS_0x1eba0f0_0_4 .concat8 [ 1 1 1 1], L_0x1eb7f80, L_0x1eb82f0, L_0x1eb8780, L_0x1eb8a90; -LS_0x1eba0f0_0_8 .concat8 [ 1 1 1 1], L_0x1eb8da0, L_0x1eb78d0, L_0x1eb90b0, L_0x1eb93f0; -LS_0x1eba0f0_0_12 .concat8 [ 1 1 1 1], L_0x1eb9740, L_0x1eb9aa0, L_0x1eb9dc0, L_0x1eba670; -LS_0x1eba0f0_0_16 .concat8 [ 1 1 1 1], L_0x1eba980, L_0x1eb8670, L_0x1ebac90, L_0x1ebaf90; -LS_0x1eba0f0_0_20 .concat8 [ 1 1 1 1], L_0x1ebb2a0, L_0x1ebb5c0, L_0x1ebb8f0, L_0x1ebbc30; -LS_0x1eba0f0_0_24 .concat8 [ 1 1 1 1], L_0x1ebbf30, L_0x1ebc240, L_0x1ebc560, L_0x1ebc890; -LS_0x1eba0f0_0_28 .concat8 [ 1 1 1 1], L_0x1ebcbd0, L_0x1ebced0, L_0x1eba2e0, L_0x1ebe820; -LS_0x1eba0f0_1_0 .concat8 [ 4 4 4 4], LS_0x1eba0f0_0_0, LS_0x1eba0f0_0_4, LS_0x1eba0f0_0_8, LS_0x1eba0f0_0_12; -LS_0x1eba0f0_1_4 .concat8 [ 4 4 4 4], LS_0x1eba0f0_0_16, LS_0x1eba0f0_0_20, LS_0x1eba0f0_0_24, LS_0x1eba0f0_0_28; -L_0x1eba0f0 .concat8 [ 16 16 0 0], LS_0x1eba0f0_1_0, LS_0x1eba0f0_1_4; -L_0x1ebe930 .part L_0x1eaaf20, 31, 1; -L_0x1ebdcd0 .part L_0x1eb5ac0, 31, 1; -S_0x1d56810 .scope generate, "or_slces[0]" "or_slces[0]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d56990 .param/l "i" 0 4 63, +C4<00>; -L_0x1eb7220/d .functor OR 1, L_0x1eb7330, L_0x1eb7490, C4<0>, C4<0>; -L_0x1eb7220 .delay 1 (30000,30000,30000) L_0x1eb7220/d; -v0x1d56a70_0 .net *"_s0", 0 0, L_0x1eb7330; 1 drivers -v0x1d56b50_0 .net *"_s1", 0 0, L_0x1eb7490; 1 drivers -S_0x1d56c30 .scope generate, "or_slces[1]" "or_slces[1]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d56e40 .param/l "i" 0 4 63, +C4<01>; -L_0x1eb7580/d .functor OR 1, L_0x1eb7640, L_0x1eb7830, C4<0>, C4<0>; -L_0x1eb7580 .delay 1 (30000,30000,30000) L_0x1eb7580/d; -v0x1d56f00_0 .net *"_s0", 0 0, L_0x1eb7640; 1 drivers -v0x1d56fe0_0 .net *"_s1", 0 0, L_0x1eb7830; 1 drivers -S_0x1d57080 .scope generate, "or_slces[2]" "or_slces[2]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d57250 .param/l "i" 0 4 63, +C4<010>; -L_0x1eb7960/d .functor OR 1, L_0x1eb79d0, L_0x1eb7b30, C4<0>, C4<0>; -L_0x1eb7960 .delay 1 (30000,30000,30000) L_0x1eb7960/d; -v0x1d572f0_0 .net *"_s0", 0 0, L_0x1eb79d0; 1 drivers -v0x1d57390_0 .net *"_s1", 0 0, L_0x1eb7b30; 1 drivers -S_0x1d57470 .scope generate, "or_slces[3]" "or_slces[3]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d57680 .param/l "i" 0 4 63, +C4<011>; -L_0x1eb7c20/d .functor OR 1, L_0x1eb7ce0, L_0x1eb7e40, C4<0>, C4<0>; -L_0x1eb7c20 .delay 1 (30000,30000,30000) L_0x1eb7c20/d; -v0x1d57740_0 .net *"_s0", 0 0, L_0x1eb7ce0; 1 drivers -v0x1d57820_0 .net *"_s1", 0 0, L_0x1eb7e40; 1 drivers -S_0x1d57900 .scope generate, "or_slces[4]" "or_slces[4]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d57b60 .param/l "i" 0 4 63, +C4<0100>; -L_0x1eb7f80/d .functor OR 1, L_0x1eb8040, L_0x1eb81a0, C4<0>, C4<0>; -L_0x1eb7f80 .delay 1 (30000,30000,30000) L_0x1eb7f80/d; -v0x1d57c20_0 .net *"_s0", 0 0, L_0x1eb8040; 1 drivers -v0x1d57d00_0 .net *"_s1", 0 0, L_0x1eb81a0; 1 drivers -S_0x1d57de0 .scope generate, "or_slces[5]" "or_slces[5]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d57ff0 .param/l "i" 0 4 63, +C4<0101>; -L_0x1eb82f0/d .functor OR 1, L_0x1eb8360, L_0x1eb85d0, C4<0>, C4<0>; -L_0x1eb82f0 .delay 1 (30000,30000,30000) L_0x1eb82f0/d; -v0x1d580b0_0 .net *"_s0", 0 0, L_0x1eb8360; 1 drivers -v0x1d58190_0 .net *"_s1", 0 0, L_0x1eb85d0; 1 drivers -S_0x1d58270 .scope generate, "or_slces[6]" "or_slces[6]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d58480 .param/l "i" 0 4 63, +C4<0110>; -L_0x1eb8780/d .functor OR 1, L_0x1eb8840, L_0x1eb89a0, C4<0>, C4<0>; -L_0x1eb8780 .delay 1 (30000,30000,30000) L_0x1eb8780/d; -v0x1d58540_0 .net *"_s0", 0 0, L_0x1eb8840; 1 drivers -v0x1d58620_0 .net *"_s1", 0 0, L_0x1eb89a0; 1 drivers -S_0x1d58700 .scope generate, "or_slces[7]" "or_slces[7]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d58910 .param/l "i" 0 4 63, +C4<0111>; -L_0x1eb8a90/d .functor OR 1, L_0x1eb8b50, L_0x1eb8cb0, C4<0>, C4<0>; -L_0x1eb8a90 .delay 1 (30000,30000,30000) L_0x1eb8a90/d; -v0x1d589d0_0 .net *"_s0", 0 0, L_0x1eb8b50; 1 drivers -v0x1d58ab0_0 .net *"_s1", 0 0, L_0x1eb8cb0; 1 drivers -S_0x1d58b90 .scope generate, "or_slces[8]" "or_slces[8]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d57b10 .param/l "i" 0 4 63, +C4<01000>; -L_0x1eb8da0/d .functor OR 1, L_0x1eb8e60, L_0x1eb8fc0, C4<0>, C4<0>; -L_0x1eb8da0 .delay 1 (30000,30000,30000) L_0x1eb8da0/d; -v0x1d58ea0_0 .net *"_s0", 0 0, L_0x1eb8e60; 1 drivers -v0x1d58f80_0 .net *"_s1", 0 0, L_0x1eb8fc0; 1 drivers -S_0x1d59060 .scope generate, "or_slces[9]" "or_slces[9]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d59270 .param/l "i" 0 4 63, +C4<01001>; -L_0x1eb78d0/d .functor OR 1, L_0x1eb91a0, L_0x1eb9300, C4<0>, C4<0>; -L_0x1eb78d0 .delay 1 (30000,30000,30000) L_0x1eb78d0/d; -v0x1d59330_0 .net *"_s0", 0 0, L_0x1eb91a0; 1 drivers -v0x1d59410_0 .net *"_s1", 0 0, L_0x1eb9300; 1 drivers -S_0x1d594f0 .scope generate, "or_slces[10]" "or_slces[10]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d59700 .param/l "i" 0 4 63, +C4<01010>; -L_0x1eb90b0/d .functor OR 1, L_0x1eb94f0, L_0x1eb9650, C4<0>, C4<0>; -L_0x1eb90b0 .delay 1 (30000,30000,30000) L_0x1eb90b0/d; -v0x1d597c0_0 .net *"_s0", 0 0, L_0x1eb94f0; 1 drivers -v0x1d598a0_0 .net *"_s1", 0 0, L_0x1eb9650; 1 drivers -S_0x1d59980 .scope generate, "or_slces[11]" "or_slces[11]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d59b90 .param/l "i" 0 4 63, +C4<01011>; -L_0x1eb93f0/d .functor OR 1, L_0x1eb9850, L_0x1eb99b0, C4<0>, C4<0>; -L_0x1eb93f0 .delay 1 (30000,30000,30000) L_0x1eb93f0/d; -v0x1d59c50_0 .net *"_s0", 0 0, L_0x1eb9850; 1 drivers -v0x1d59d30_0 .net *"_s1", 0 0, L_0x1eb99b0; 1 drivers -S_0x1d59e10 .scope generate, "or_slces[12]" "or_slces[12]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5a020 .param/l "i" 0 4 63, +C4<01100>; -L_0x1eb9740/d .functor OR 1, L_0x1eb9b70, L_0x1eb9cd0, C4<0>, C4<0>; -L_0x1eb9740 .delay 1 (30000,30000,30000) L_0x1eb9740/d; -v0x1d5a0e0_0 .net *"_s0", 0 0, L_0x1eb9b70; 1 drivers -v0x1d5a1c0_0 .net *"_s1", 0 0, L_0x1eb9cd0; 1 drivers -S_0x1d5a2a0 .scope generate, "or_slces[13]" "or_slces[13]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5a4b0 .param/l "i" 0 4 63, +C4<01101>; -L_0x1eb9aa0/d .functor OR 1, L_0x1eb9ea0, L_0x1eb84c0, C4<0>, C4<0>; -L_0x1eb9aa0 .delay 1 (30000,30000,30000) L_0x1eb9aa0/d; -v0x1d5a570_0 .net *"_s0", 0 0, L_0x1eb9ea0; 1 drivers -v0x1d5a650_0 .net *"_s1", 0 0, L_0x1eb84c0; 1 drivers -S_0x1d5a730 .scope generate, "or_slces[14]" "or_slces[14]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5a940 .param/l "i" 0 4 63, +C4<01110>; -L_0x1eb9dc0/d .functor OR 1, L_0x1eba420, L_0x1eba580, C4<0>, C4<0>; -L_0x1eb9dc0 .delay 1 (30000,30000,30000) L_0x1eb9dc0/d; -v0x1d5aa00_0 .net *"_s0", 0 0, L_0x1eba420; 1 drivers -v0x1d5aae0_0 .net *"_s1", 0 0, L_0x1eba580; 1 drivers -S_0x1d5abc0 .scope generate, "or_slces[15]" "or_slces[15]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5add0 .param/l "i" 0 4 63, +C4<01111>; -L_0x1eba670/d .functor OR 1, L_0x1eba730, L_0x1eba890, C4<0>, C4<0>; -L_0x1eba670 .delay 1 (30000,30000,30000) L_0x1eba670/d; -v0x1d5ae90_0 .net *"_s0", 0 0, L_0x1eba730; 1 drivers -v0x1d5af70_0 .net *"_s1", 0 0, L_0x1eba890; 1 drivers -S_0x1d5b050 .scope generate, "or_slces[16]" "or_slces[16]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d58da0 .param/l "i" 0 4 63, +C4<010000>; -L_0x1eba980/d .functor OR 1, L_0x1ebaa40, L_0x1ebaba0, C4<0>, C4<0>; -L_0x1eba980 .delay 1 (30000,30000,30000) L_0x1eba980/d; -v0x1d5b3c0_0 .net *"_s0", 0 0, L_0x1ebaa40; 1 drivers -v0x1d5b480_0 .net *"_s1", 0 0, L_0x1ebaba0; 1 drivers -S_0x1d5b560 .scope generate, "or_slces[17]" "or_slces[17]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5b770 .param/l "i" 0 4 63, +C4<010001>; -L_0x1eb8670/d .functor OR 1, L_0x1ebadb0, L_0x1ebaea0, C4<0>, C4<0>; -L_0x1eb8670 .delay 1 (30000,30000,30000) L_0x1eb8670/d; -v0x1d5b830_0 .net *"_s0", 0 0, L_0x1ebadb0; 1 drivers -v0x1d5b910_0 .net *"_s1", 0 0, L_0x1ebaea0; 1 drivers -S_0x1d5b9f0 .scope generate, "or_slces[18]" "or_slces[18]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5bc00 .param/l "i" 0 4 63, +C4<010010>; -L_0x1ebac90/d .functor OR 1, L_0x1ebb0c0, L_0x1ebb1b0, C4<0>, C4<0>; -L_0x1ebac90 .delay 1 (30000,30000,30000) L_0x1ebac90/d; -v0x1d5bcc0_0 .net *"_s0", 0 0, L_0x1ebb0c0; 1 drivers -v0x1d5bda0_0 .net *"_s1", 0 0, L_0x1ebb1b0; 1 drivers -S_0x1d5be80 .scope generate, "or_slces[19]" "or_slces[19]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5c090 .param/l "i" 0 4 63, +C4<010011>; -L_0x1ebaf90/d .functor OR 1, L_0x1ebb3e0, L_0x1ebb4d0, C4<0>, C4<0>; -L_0x1ebaf90 .delay 1 (30000,30000,30000) L_0x1ebaf90/d; -v0x1d5c150_0 .net *"_s0", 0 0, L_0x1ebb3e0; 1 drivers -v0x1d5c230_0 .net *"_s1", 0 0, L_0x1ebb4d0; 1 drivers -S_0x1d5c310 .scope generate, "or_slces[20]" "or_slces[20]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5c520 .param/l "i" 0 4 63, +C4<010100>; -L_0x1ebb2a0/d .functor OR 1, L_0x1ebb710, L_0x1ebb800, C4<0>, C4<0>; -L_0x1ebb2a0 .delay 1 (30000,30000,30000) L_0x1ebb2a0/d; -v0x1d5c5e0_0 .net *"_s0", 0 0, L_0x1ebb710; 1 drivers -v0x1d5c6c0_0 .net *"_s1", 0 0, L_0x1ebb800; 1 drivers -S_0x1d5c7a0 .scope generate, "or_slces[21]" "or_slces[21]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5c9b0 .param/l "i" 0 4 63, +C4<010101>; -L_0x1ebb5c0/d .functor OR 1, L_0x1ebba50, L_0x1ebbb40, C4<0>, C4<0>; -L_0x1ebb5c0 .delay 1 (30000,30000,30000) L_0x1ebb5c0/d; -v0x1d5ca70_0 .net *"_s0", 0 0, L_0x1ebba50; 1 drivers -v0x1d5cb50_0 .net *"_s1", 0 0, L_0x1ebbb40; 1 drivers -S_0x1d5cc30 .scope generate, "or_slces[22]" "or_slces[22]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5ce40 .param/l "i" 0 4 63, +C4<010110>; -L_0x1ebb8f0/d .functor OR 1, L_0x1ebbda0, L_0x1ebbe40, C4<0>, C4<0>; -L_0x1ebb8f0 .delay 1 (30000,30000,30000) L_0x1ebb8f0/d; -v0x1d5cf00_0 .net *"_s0", 0 0, L_0x1ebbda0; 1 drivers -v0x1d5cfe0_0 .net *"_s1", 0 0, L_0x1ebbe40; 1 drivers -S_0x1d5d0c0 .scope generate, "or_slces[23]" "or_slces[23]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5d2d0 .param/l "i" 0 4 63, +C4<010111>; -L_0x1ebbc30/d .functor OR 1, L_0x1ebc0b0, L_0x1ebc150, C4<0>, C4<0>; -L_0x1ebbc30 .delay 1 (30000,30000,30000) L_0x1ebbc30/d; -v0x1d5d390_0 .net *"_s0", 0 0, L_0x1ebc0b0; 1 drivers -v0x1d5d470_0 .net *"_s1", 0 0, L_0x1ebc150; 1 drivers -S_0x1d5d550 .scope generate, "or_slces[24]" "or_slces[24]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5d760 .param/l "i" 0 4 63, +C4<011000>; -L_0x1ebbf30/d .functor OR 1, L_0x1ebc3d0, L_0x1ebc470, C4<0>, C4<0>; -L_0x1ebbf30 .delay 1 (30000,30000,30000) L_0x1ebbf30/d; -v0x1d5d820_0 .net *"_s0", 0 0, L_0x1ebc3d0; 1 drivers -v0x1d5d900_0 .net *"_s1", 0 0, L_0x1ebc470; 1 drivers -S_0x1d5d9e0 .scope generate, "or_slces[25]" "or_slces[25]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5dbf0 .param/l "i" 0 4 63, +C4<011001>; -L_0x1ebc240/d .functor OR 1, L_0x1ebc700, L_0x1ebc7a0, C4<0>, C4<0>; -L_0x1ebc240 .delay 1 (30000,30000,30000) L_0x1ebc240/d; -v0x1d5dcb0_0 .net *"_s0", 0 0, L_0x1ebc700; 1 drivers -v0x1d5dd90_0 .net *"_s1", 0 0, L_0x1ebc7a0; 1 drivers -S_0x1d5de70 .scope generate, "or_slces[26]" "or_slces[26]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5e080 .param/l "i" 0 4 63, +C4<011010>; -L_0x1ebc560/d .functor OR 1, L_0x1ebca40, L_0x1ebcae0, C4<0>, C4<0>; -L_0x1ebc560 .delay 1 (30000,30000,30000) L_0x1ebc560/d; -v0x1d5e140_0 .net *"_s0", 0 0, L_0x1ebca40; 1 drivers -v0x1d5e220_0 .net *"_s1", 0 0, L_0x1ebcae0; 1 drivers -S_0x1d5e300 .scope generate, "or_slces[27]" "or_slces[27]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5e510 .param/l "i" 0 4 63, +C4<011011>; -L_0x1ebc890/d .functor OR 1, L_0x1ebc9a0, L_0x1ebcde0, C4<0>, C4<0>; -L_0x1ebc890 .delay 1 (30000,30000,30000) L_0x1ebc890/d; -v0x1d5e5d0_0 .net *"_s0", 0 0, L_0x1ebc9a0; 1 drivers -v0x1d5e6b0_0 .net *"_s1", 0 0, L_0x1ebcde0; 1 drivers -S_0x1d5e790 .scope generate, "or_slces[28]" "or_slces[28]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5e9a0 .param/l "i" 0 4 63, +C4<011100>; -L_0x1ebcbd0/d .functor OR 1, L_0x1ebcce0, L_0x1ebd0f0, C4<0>, C4<0>; -L_0x1ebcbd0 .delay 1 (30000,30000,30000) L_0x1ebcbd0/d; -v0x1d5ea60_0 .net *"_s0", 0 0, L_0x1ebcce0; 1 drivers -v0x1d5eb40_0 .net *"_s1", 0 0, L_0x1ebd0f0; 1 drivers -S_0x1d5ec20 .scope generate, "or_slces[29]" "or_slces[29]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5ee30 .param/l "i" 0 4 63, +C4<011101>; -L_0x1ebced0/d .functor OR 1, L_0x1ebcf90, L_0x1eba000, C4<0>, C4<0>; -L_0x1ebced0 .delay 1 (30000,30000,30000) L_0x1ebced0/d; -v0x1d5eef0_0 .net *"_s0", 0 0, L_0x1ebcf90; 1 drivers -v0x1d5efd0_0 .net *"_s1", 0 0, L_0x1eba000; 1 drivers -S_0x1d5f0b0 .scope generate, "or_slces[30]" "or_slces[30]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5f2c0 .param/l "i" 0 4 63, +C4<011110>; -L_0x1eba2e0/d .functor OR 1, L_0x1ebd1e0, L_0x1ebdc30, C4<0>, C4<0>; -L_0x1eba2e0 .delay 1 (30000,30000,30000) L_0x1eba2e0/d; -v0x1d5f380_0 .net *"_s0", 0 0, L_0x1ebd1e0; 1 drivers -v0x1d5f460_0 .net *"_s1", 0 0, L_0x1ebdc30; 1 drivers -S_0x1d5f540 .scope generate, "or_slces[31]" "or_slces[31]" 4 63, 4 63 0, S_0x1d56430; - .timescale -9 -12; -P_0x1d5f750 .param/l "i" 0 4 63, +C4<011111>; -L_0x1ebe820/d .functor OR 1, L_0x1ebe930, L_0x1ebdcd0, C4<0>, C4<0>; -L_0x1ebe820 .delay 1 (30000,30000,30000) L_0x1ebe820/d; -v0x1d5f810_0 .net *"_s0", 0 0, L_0x1ebe930; 1 drivers -v0x1d5f8f0_0 .net *"_s1", 0 0, L_0x1ebdcd0; 1 drivers -S_0x1d61b70 .scope module, "zeroout" "and32" 3 55, 4 44 0, S_0x1a570b0; +v0x11f2e10_0 .net "A", 31 0, L_0x133e830; alias, 1 drivers +v0x11f2f10_0 .net "B", 31 0, L_0x134a800; alias, 1 drivers +v0x11f2ff0_0 .net *"_s0", 0 0, L_0x134a370; 1 drivers +v0x11f30e0_0 .net *"_s100", 0 0, L_0x13505f0; 1 drivers +v0x11f31c0_0 .net *"_s104", 0 0, L_0x1350910; 1 drivers +v0x11f32f0_0 .net *"_s108", 0 0, L_0x1350c40; 1 drivers +v0x11f33d0_0 .net *"_s112", 0 0, L_0x1350f80; 1 drivers +v0x11f34b0_0 .net *"_s116", 0 0, L_0x1351280; 1 drivers +v0x11f3590_0 .net *"_s12", 0 0, L_0x134bfd0; 1 drivers +v0x11f3700_0 .net *"_s120", 0 0, L_0x134e690; 1 drivers +v0x11f37e0_0 .net *"_s124", 0 0, L_0x1352bd0; 1 drivers +v0x11f38c0_0 .net *"_s16", 0 0, L_0x134c330; 1 drivers +v0x11f39a0_0 .net *"_s20", 0 0, L_0x134c6a0; 1 drivers +v0x11f3a80_0 .net *"_s24", 0 0, L_0x134cb30; 1 drivers +v0x11f3b60_0 .net *"_s28", 0 0, L_0x134ce40; 1 drivers +v0x11f3c40_0 .net *"_s32", 0 0, L_0x134d150; 1 drivers +v0x11f3d20_0 .net *"_s36", 0 0, L_0x134bc80; 1 drivers +v0x11f3ed0_0 .net *"_s4", 0 0, L_0x134b930; 1 drivers +v0x11f3f70_0 .net *"_s40", 0 0, L_0x134d460; 1 drivers +v0x11f4050_0 .net *"_s44", 0 0, L_0x134d7a0; 1 drivers +v0x11f4130_0 .net *"_s48", 0 0, L_0x134daf0; 1 drivers +v0x11f4210_0 .net *"_s52", 0 0, L_0x134de50; 1 drivers +v0x11f42f0_0 .net *"_s56", 0 0, L_0x134e170; 1 drivers +v0x11f43d0_0 .net *"_s60", 0 0, L_0x134ea20; 1 drivers +v0x11f44b0_0 .net *"_s64", 0 0, L_0x134ed30; 1 drivers +v0x11f4590_0 .net *"_s68", 0 0, L_0x134ca20; 1 drivers +v0x11f4670_0 .net *"_s72", 0 0, L_0x134f040; 1 drivers +v0x11f4750_0 .net *"_s76", 0 0, L_0x134f340; 1 drivers +v0x11f4830_0 .net *"_s8", 0 0, L_0x134bd10; 1 drivers +v0x11f4910_0 .net *"_s80", 0 0, L_0x134f650; 1 drivers +v0x11f49f0_0 .net *"_s84", 0 0, L_0x134f970; 1 drivers +v0x11f4ad0_0 .net *"_s88", 0 0, L_0x134fca0; 1 drivers +v0x11f4bb0_0 .net *"_s92", 0 0, L_0x134ffe0; 1 drivers +v0x11f3e00_0 .net *"_s96", 0 0, L_0x13502e0; 1 drivers +v0x11f4e80_0 .net "out", 31 0, L_0x134e4a0; alias, 1 drivers +L_0x134b6e0 .part L_0x133e830, 0, 1; +L_0x134b840 .part L_0x134a800, 0, 1; +L_0x134b9f0 .part L_0x133e830, 1, 1; +L_0x134bbe0 .part L_0x134a800, 1, 1; +L_0x134bd80 .part L_0x133e830, 2, 1; +L_0x134bee0 .part L_0x134a800, 2, 1; +L_0x134c090 .part L_0x133e830, 3, 1; +L_0x134c1f0 .part L_0x134a800, 3, 1; +L_0x134c3f0 .part L_0x133e830, 4, 1; +L_0x134c550 .part L_0x134a800, 4, 1; +L_0x134c710 .part L_0x133e830, 5, 1; +L_0x134c980 .part L_0x134a800, 5, 1; +L_0x134cbf0 .part L_0x133e830, 6, 1; +L_0x134cd50 .part L_0x134a800, 6, 1; +L_0x134cf00 .part L_0x133e830, 7, 1; +L_0x134d060 .part L_0x134a800, 7, 1; +L_0x134d210 .part L_0x133e830, 8, 1; +L_0x134d370 .part L_0x134a800, 8, 1; +L_0x134d550 .part L_0x133e830, 9, 1; +L_0x134d6b0 .part L_0x134a800, 9, 1; +L_0x134d8a0 .part L_0x133e830, 10, 1; +L_0x134da00 .part L_0x134a800, 10, 1; +L_0x134dc00 .part L_0x133e830, 11, 1; +L_0x134dd60 .part L_0x134a800, 11, 1; +L_0x134df20 .part L_0x133e830, 12, 1; +L_0x134e080 .part L_0x134a800, 12, 1; +L_0x134e250 .part L_0x133e830, 13, 1; +L_0x134c870 .part L_0x134a800, 13, 1; +L_0x134e7d0 .part L_0x133e830, 14, 1; +L_0x134e930 .part L_0x134a800, 14, 1; +L_0x134eae0 .part L_0x133e830, 15, 1; +L_0x134ec40 .part L_0x134a800, 15, 1; +L_0x134edf0 .part L_0x133e830, 16, 1; +L_0x134ef50 .part L_0x134a800, 16, 1; +L_0x134f160 .part L_0x133e830, 17, 1; +L_0x134f250 .part L_0x134a800, 17, 1; +L_0x134f470 .part L_0x133e830, 18, 1; +L_0x134f560 .part L_0x134a800, 18, 1; +L_0x134f790 .part L_0x133e830, 19, 1; +L_0x134f880 .part L_0x134a800, 19, 1; +L_0x134fac0 .part L_0x133e830, 20, 1; +L_0x134fbb0 .part L_0x134a800, 20, 1; +L_0x134fe00 .part L_0x133e830, 21, 1; +L_0x134fef0 .part L_0x134a800, 21, 1; +L_0x1350150 .part L_0x133e830, 22, 1; +L_0x13501f0 .part L_0x134a800, 22, 1; +L_0x1350460 .part L_0x133e830, 23, 1; +L_0x1350500 .part L_0x134a800, 23, 1; +L_0x1350780 .part L_0x133e830, 24, 1; +L_0x1350820 .part L_0x134a800, 24, 1; +L_0x1350ab0 .part L_0x133e830, 25, 1; +L_0x1350b50 .part L_0x134a800, 25, 1; +L_0x1350df0 .part L_0x133e830, 26, 1; +L_0x1350e90 .part L_0x134a800, 26, 1; +L_0x1350d50 .part L_0x133e830, 27, 1; +L_0x1351190 .part L_0x134a800, 27, 1; +L_0x1351090 .part L_0x133e830, 28, 1; +L_0x13514a0 .part L_0x134a800, 28, 1; +L_0x1351340 .part L_0x133e830, 29, 1; +L_0x134e3b0 .part L_0x134a800, 29, 1; +L_0x1351590 .part L_0x133e830, 30, 1; +L_0x1351fe0 .part L_0x134a800, 30, 1; +LS_0x134e4a0_0_0 .concat8 [ 1 1 1 1], L_0x134a370, L_0x134b930, L_0x134bd10, L_0x134bfd0; +LS_0x134e4a0_0_4 .concat8 [ 1 1 1 1], L_0x134c330, L_0x134c6a0, L_0x134cb30, L_0x134ce40; +LS_0x134e4a0_0_8 .concat8 [ 1 1 1 1], L_0x134d150, L_0x134bc80, L_0x134d460, L_0x134d7a0; +LS_0x134e4a0_0_12 .concat8 [ 1 1 1 1], L_0x134daf0, L_0x134de50, L_0x134e170, L_0x134ea20; +LS_0x134e4a0_0_16 .concat8 [ 1 1 1 1], L_0x134ed30, L_0x134ca20, L_0x134f040, L_0x134f340; +LS_0x134e4a0_0_20 .concat8 [ 1 1 1 1], L_0x134f650, L_0x134f970, L_0x134fca0, L_0x134ffe0; +LS_0x134e4a0_0_24 .concat8 [ 1 1 1 1], L_0x13502e0, L_0x13505f0, L_0x1350910, L_0x1350c40; +LS_0x134e4a0_0_28 .concat8 [ 1 1 1 1], L_0x1350f80, L_0x1351280, L_0x134e690, L_0x1352bd0; +LS_0x134e4a0_1_0 .concat8 [ 4 4 4 4], LS_0x134e4a0_0_0, LS_0x134e4a0_0_4, LS_0x134e4a0_0_8, LS_0x134e4a0_0_12; +LS_0x134e4a0_1_4 .concat8 [ 4 4 4 4], LS_0x134e4a0_0_16, LS_0x134e4a0_0_20, LS_0x134e4a0_0_24, LS_0x134e4a0_0_28; +L_0x134e4a0 .concat8 [ 16 16 0 0], LS_0x134e4a0_1_0, LS_0x134e4a0_1_4; +L_0x1352ce0 .part L_0x133e830, 31, 1; +L_0x1352080 .part L_0x134a800, 31, 1; +S_0x11e9bc0 .scope generate, "or_slces[0]" "or_slces[0]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11e9dd0 .param/l "i" 0 4 63, +C4<00>; +L_0x134a370/d .functor OR 1, L_0x134b6e0, L_0x134b840, C4<0>, C4<0>; +L_0x134a370 .delay 1 (30000,30000,30000) L_0x134a370/d; +v0x11e9eb0_0 .net *"_s0", 0 0, L_0x134b6e0; 1 drivers +v0x11e9f90_0 .net *"_s1", 0 0, L_0x134b840; 1 drivers +S_0x11ea070 .scope generate, "or_slces[1]" "or_slces[1]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ea280 .param/l "i" 0 4 63, +C4<01>; +L_0x134b930/d .functor OR 1, L_0x134b9f0, L_0x134bbe0, C4<0>, C4<0>; +L_0x134b930 .delay 1 (30000,30000,30000) L_0x134b930/d; +v0x11ea340_0 .net *"_s0", 0 0, L_0x134b9f0; 1 drivers +v0x11ea420_0 .net *"_s1", 0 0, L_0x134bbe0; 1 drivers +S_0x11ea500 .scope generate, "or_slces[2]" "or_slces[2]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ea710 .param/l "i" 0 4 63, +C4<010>; +L_0x134bd10/d .functor OR 1, L_0x134bd80, L_0x134bee0, C4<0>, C4<0>; +L_0x134bd10 .delay 1 (30000,30000,30000) L_0x134bd10/d; +v0x11ea7b0_0 .net *"_s0", 0 0, L_0x134bd80; 1 drivers +v0x11ea890_0 .net *"_s1", 0 0, L_0x134bee0; 1 drivers +S_0x11ea970 .scope generate, "or_slces[3]" "or_slces[3]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11eab80 .param/l "i" 0 4 63, +C4<011>; +L_0x134bfd0/d .functor OR 1, L_0x134c090, L_0x134c1f0, C4<0>, C4<0>; +L_0x134bfd0 .delay 1 (30000,30000,30000) L_0x134bfd0/d; +v0x11eac40_0 .net *"_s0", 0 0, L_0x134c090; 1 drivers +v0x11ead20_0 .net *"_s1", 0 0, L_0x134c1f0; 1 drivers +S_0x11eae00 .scope generate, "or_slces[4]" "or_slces[4]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11eb060 .param/l "i" 0 4 63, +C4<0100>; +L_0x134c330/d .functor OR 1, L_0x134c3f0, L_0x134c550, C4<0>, C4<0>; +L_0x134c330 .delay 1 (30000,30000,30000) L_0x134c330/d; +v0x11eb120_0 .net *"_s0", 0 0, L_0x134c3f0; 1 drivers +v0x11eb200_0 .net *"_s1", 0 0, L_0x134c550; 1 drivers +S_0x11eb2e0 .scope generate, "or_slces[5]" "or_slces[5]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11eb4f0 .param/l "i" 0 4 63, +C4<0101>; +L_0x134c6a0/d .functor OR 1, L_0x134c710, L_0x134c980, C4<0>, C4<0>; +L_0x134c6a0 .delay 1 (30000,30000,30000) L_0x134c6a0/d; +v0x11eb5b0_0 .net *"_s0", 0 0, L_0x134c710; 1 drivers +v0x11eb690_0 .net *"_s1", 0 0, L_0x134c980; 1 drivers +S_0x11eb770 .scope generate, "or_slces[6]" "or_slces[6]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11eb980 .param/l "i" 0 4 63, +C4<0110>; +L_0x134cb30/d .functor OR 1, L_0x134cbf0, L_0x134cd50, C4<0>, C4<0>; +L_0x134cb30 .delay 1 (30000,30000,30000) L_0x134cb30/d; +v0x11eba40_0 .net *"_s0", 0 0, L_0x134cbf0; 1 drivers +v0x11ebb20_0 .net *"_s1", 0 0, L_0x134cd50; 1 drivers +S_0x11ebc00 .scope generate, "or_slces[7]" "or_slces[7]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ebe10 .param/l "i" 0 4 63, +C4<0111>; +L_0x134ce40/d .functor OR 1, L_0x134cf00, L_0x134d060, C4<0>, C4<0>; +L_0x134ce40 .delay 1 (30000,30000,30000) L_0x134ce40/d; +v0x11ebed0_0 .net *"_s0", 0 0, L_0x134cf00; 1 drivers +v0x11ebfb0_0 .net *"_s1", 0 0, L_0x134d060; 1 drivers +S_0x11ec090 .scope generate, "or_slces[8]" "or_slces[8]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11eb010 .param/l "i" 0 4 63, +C4<01000>; +L_0x134d150/d .functor OR 1, L_0x134d210, L_0x134d370, C4<0>, C4<0>; +L_0x134d150 .delay 1 (30000,30000,30000) L_0x134d150/d; +v0x11ec3a0_0 .net *"_s0", 0 0, L_0x134d210; 1 drivers +v0x11ec480_0 .net *"_s1", 0 0, L_0x134d370; 1 drivers +S_0x11ec560 .scope generate, "or_slces[9]" "or_slces[9]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ec770 .param/l "i" 0 4 63, +C4<01001>; +L_0x134bc80/d .functor OR 1, L_0x134d550, L_0x134d6b0, C4<0>, C4<0>; +L_0x134bc80 .delay 1 (30000,30000,30000) L_0x134bc80/d; +v0x11ec830_0 .net *"_s0", 0 0, L_0x134d550; 1 drivers +v0x11ec910_0 .net *"_s1", 0 0, L_0x134d6b0; 1 drivers +S_0x11ec9f0 .scope generate, "or_slces[10]" "or_slces[10]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ecc00 .param/l "i" 0 4 63, +C4<01010>; +L_0x134d460/d .functor OR 1, L_0x134d8a0, L_0x134da00, C4<0>, C4<0>; +L_0x134d460 .delay 1 (30000,30000,30000) L_0x134d460/d; +v0x11eccc0_0 .net *"_s0", 0 0, L_0x134d8a0; 1 drivers +v0x11ecda0_0 .net *"_s1", 0 0, L_0x134da00; 1 drivers +S_0x11ece80 .scope generate, "or_slces[11]" "or_slces[11]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ed090 .param/l "i" 0 4 63, +C4<01011>; +L_0x134d7a0/d .functor OR 1, L_0x134dc00, L_0x134dd60, C4<0>, C4<0>; +L_0x134d7a0 .delay 1 (30000,30000,30000) L_0x134d7a0/d; +v0x11ed150_0 .net *"_s0", 0 0, L_0x134dc00; 1 drivers +v0x11ed230_0 .net *"_s1", 0 0, L_0x134dd60; 1 drivers +S_0x11ed310 .scope generate, "or_slces[12]" "or_slces[12]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ed520 .param/l "i" 0 4 63, +C4<01100>; +L_0x134daf0/d .functor OR 1, L_0x134df20, L_0x134e080, C4<0>, C4<0>; +L_0x134daf0 .delay 1 (30000,30000,30000) L_0x134daf0/d; +v0x11ed5e0_0 .net *"_s0", 0 0, L_0x134df20; 1 drivers +v0x11ed6c0_0 .net *"_s1", 0 0, L_0x134e080; 1 drivers +S_0x11ed7a0 .scope generate, "or_slces[13]" "or_slces[13]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ed9b0 .param/l "i" 0 4 63, +C4<01101>; +L_0x134de50/d .functor OR 1, L_0x134e250, L_0x134c870, C4<0>, C4<0>; +L_0x134de50 .delay 1 (30000,30000,30000) L_0x134de50/d; +v0x11eda70_0 .net *"_s0", 0 0, L_0x134e250; 1 drivers +v0x11edb50_0 .net *"_s1", 0 0, L_0x134c870; 1 drivers +S_0x11edc30 .scope generate, "or_slces[14]" "or_slces[14]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ede40 .param/l "i" 0 4 63, +C4<01110>; +L_0x134e170/d .functor OR 1, L_0x134e7d0, L_0x134e930, C4<0>, C4<0>; +L_0x134e170 .delay 1 (30000,30000,30000) L_0x134e170/d; +v0x11edf00_0 .net *"_s0", 0 0, L_0x134e7d0; 1 drivers +v0x11edfe0_0 .net *"_s1", 0 0, L_0x134e930; 1 drivers +S_0x11ee0c0 .scope generate, "or_slces[15]" "or_slces[15]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ee2d0 .param/l "i" 0 4 63, +C4<01111>; +L_0x134ea20/d .functor OR 1, L_0x134eae0, L_0x134ec40, C4<0>, C4<0>; +L_0x134ea20 .delay 1 (30000,30000,30000) L_0x134ea20/d; +v0x11ee390_0 .net *"_s0", 0 0, L_0x134eae0; 1 drivers +v0x11ee470_0 .net *"_s1", 0 0, L_0x134ec40; 1 drivers +S_0x11ee550 .scope generate, "or_slces[16]" "or_slces[16]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ec2a0 .param/l "i" 0 4 63, +C4<010000>; +L_0x134ed30/d .functor OR 1, L_0x134edf0, L_0x134ef50, C4<0>, C4<0>; +L_0x134ed30 .delay 1 (30000,30000,30000) L_0x134ed30/d; +v0x11ee8c0_0 .net *"_s0", 0 0, L_0x134edf0; 1 drivers +v0x11ee980_0 .net *"_s1", 0 0, L_0x134ef50; 1 drivers +S_0x11eea60 .scope generate, "or_slces[17]" "or_slces[17]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11eec70 .param/l "i" 0 4 63, +C4<010001>; +L_0x134ca20/d .functor OR 1, L_0x134f160, L_0x134f250, C4<0>, C4<0>; +L_0x134ca20 .delay 1 (30000,30000,30000) L_0x134ca20/d; +v0x11eed30_0 .net *"_s0", 0 0, L_0x134f160; 1 drivers +v0x11eee10_0 .net *"_s1", 0 0, L_0x134f250; 1 drivers +S_0x11eeef0 .scope generate, "or_slces[18]" "or_slces[18]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ef100 .param/l "i" 0 4 63, +C4<010010>; +L_0x134f040/d .functor OR 1, L_0x134f470, L_0x134f560, C4<0>, C4<0>; +L_0x134f040 .delay 1 (30000,30000,30000) L_0x134f040/d; +v0x11ef1c0_0 .net *"_s0", 0 0, L_0x134f470; 1 drivers +v0x11ef2a0_0 .net *"_s1", 0 0, L_0x134f560; 1 drivers +S_0x11ef380 .scope generate, "or_slces[19]" "or_slces[19]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11ef590 .param/l "i" 0 4 63, +C4<010011>; +L_0x134f340/d .functor OR 1, L_0x134f790, L_0x134f880, C4<0>, C4<0>; +L_0x134f340 .delay 1 (30000,30000,30000) L_0x134f340/d; +v0x11ef650_0 .net *"_s0", 0 0, L_0x134f790; 1 drivers +v0x11ef730_0 .net *"_s1", 0 0, L_0x134f880; 1 drivers +S_0x11ef810 .scope generate, "or_slces[20]" "or_slces[20]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11efa20 .param/l "i" 0 4 63, +C4<010100>; +L_0x134f650/d .functor OR 1, L_0x134fac0, L_0x134fbb0, C4<0>, C4<0>; +L_0x134f650 .delay 1 (30000,30000,30000) L_0x134f650/d; +v0x11efae0_0 .net *"_s0", 0 0, L_0x134fac0; 1 drivers +v0x11efbc0_0 .net *"_s1", 0 0, L_0x134fbb0; 1 drivers +S_0x11efca0 .scope generate, "or_slces[21]" "or_slces[21]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11efeb0 .param/l "i" 0 4 63, +C4<010101>; +L_0x134f970/d .functor OR 1, L_0x134fe00, L_0x134fef0, C4<0>, C4<0>; +L_0x134f970 .delay 1 (30000,30000,30000) L_0x134f970/d; +v0x11eff70_0 .net *"_s0", 0 0, L_0x134fe00; 1 drivers +v0x11f0010_0 .net *"_s1", 0 0, L_0x134fef0; 1 drivers +S_0x11f00b0 .scope generate, "or_slces[22]" "or_slces[22]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f0280 .param/l "i" 0 4 63, +C4<010110>; +L_0x134fca0/d .functor OR 1, L_0x1350150, L_0x13501f0, C4<0>, C4<0>; +L_0x134fca0 .delay 1 (30000,30000,30000) L_0x134fca0/d; +v0x11f0340_0 .net *"_s0", 0 0, L_0x1350150; 1 drivers +v0x11f0420_0 .net *"_s1", 0 0, L_0x13501f0; 1 drivers +S_0x11f0500 .scope generate, "or_slces[23]" "or_slces[23]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f0710 .param/l "i" 0 4 63, +C4<010111>; +L_0x134ffe0/d .functor OR 1, L_0x1350460, L_0x1350500, C4<0>, C4<0>; +L_0x134ffe0 .delay 1 (30000,30000,30000) L_0x134ffe0/d; +v0x11f07d0_0 .net *"_s0", 0 0, L_0x1350460; 1 drivers +v0x11f08b0_0 .net *"_s1", 0 0, L_0x1350500; 1 drivers +S_0x11f0990 .scope generate, "or_slces[24]" "or_slces[24]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f0ba0 .param/l "i" 0 4 63, +C4<011000>; +L_0x13502e0/d .functor OR 1, L_0x1350780, L_0x1350820, C4<0>, C4<0>; +L_0x13502e0 .delay 1 (30000,30000,30000) L_0x13502e0/d; +v0x11f0c60_0 .net *"_s0", 0 0, L_0x1350780; 1 drivers +v0x11f0d40_0 .net *"_s1", 0 0, L_0x1350820; 1 drivers +S_0x11f0e20 .scope generate, "or_slces[25]" "or_slces[25]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f1030 .param/l "i" 0 4 63, +C4<011001>; +L_0x13505f0/d .functor OR 1, L_0x1350ab0, L_0x1350b50, C4<0>, C4<0>; +L_0x13505f0 .delay 1 (30000,30000,30000) L_0x13505f0/d; +v0x11f10f0_0 .net *"_s0", 0 0, L_0x1350ab0; 1 drivers +v0x11f11d0_0 .net *"_s1", 0 0, L_0x1350b50; 1 drivers +S_0x11f12b0 .scope generate, "or_slces[26]" "or_slces[26]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f14c0 .param/l "i" 0 4 63, +C4<011010>; +L_0x1350910/d .functor OR 1, L_0x1350df0, L_0x1350e90, C4<0>, C4<0>; +L_0x1350910 .delay 1 (30000,30000,30000) L_0x1350910/d; +v0x11f1580_0 .net *"_s0", 0 0, L_0x1350df0; 1 drivers +v0x11f1660_0 .net *"_s1", 0 0, L_0x1350e90; 1 drivers +S_0x11f1740 .scope generate, "or_slces[27]" "or_slces[27]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f1950 .param/l "i" 0 4 63, +C4<011011>; +L_0x1350c40/d .functor OR 1, L_0x1350d50, L_0x1351190, C4<0>, C4<0>; +L_0x1350c40 .delay 1 (30000,30000,30000) L_0x1350c40/d; +v0x11f1a10_0 .net *"_s0", 0 0, L_0x1350d50; 1 drivers +v0x11f1af0_0 .net *"_s1", 0 0, L_0x1351190; 1 drivers +S_0x11f1bd0 .scope generate, "or_slces[28]" "or_slces[28]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f1de0 .param/l "i" 0 4 63, +C4<011100>; +L_0x1350f80/d .functor OR 1, L_0x1351090, L_0x13514a0, C4<0>, C4<0>; +L_0x1350f80 .delay 1 (30000,30000,30000) L_0x1350f80/d; +v0x11f1ea0_0 .net *"_s0", 0 0, L_0x1351090; 1 drivers +v0x11f1f80_0 .net *"_s1", 0 0, L_0x13514a0; 1 drivers +S_0x11f2060 .scope generate, "or_slces[29]" "or_slces[29]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f2270 .param/l "i" 0 4 63, +C4<011101>; +L_0x1351280/d .functor OR 1, L_0x1351340, L_0x134e3b0, C4<0>, C4<0>; +L_0x1351280 .delay 1 (30000,30000,30000) L_0x1351280/d; +v0x11f2330_0 .net *"_s0", 0 0, L_0x1351340; 1 drivers +v0x11f2410_0 .net *"_s1", 0 0, L_0x134e3b0; 1 drivers +S_0x11f24f0 .scope generate, "or_slces[30]" "or_slces[30]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f2700 .param/l "i" 0 4 63, +C4<011110>; +L_0x134e690/d .functor OR 1, L_0x1351590, L_0x1351fe0, C4<0>, C4<0>; +L_0x134e690 .delay 1 (30000,30000,30000) L_0x134e690/d; +v0x11f27c0_0 .net *"_s0", 0 0, L_0x1351590; 1 drivers +v0x11f28a0_0 .net *"_s1", 0 0, L_0x1351fe0; 1 drivers +S_0x11f2980 .scope generate, "or_slces[31]" "or_slces[31]" 4 63, 4 63 0, S_0x11e9980; + .timescale -9 -12; +P_0x11f2b90 .param/l "i" 0 4 63, +C4<011111>; +L_0x1352bd0/d .functor OR 1, L_0x1352ce0, L_0x1352080, C4<0>, C4<0>; +L_0x1352bd0 .delay 1 (30000,30000,30000) L_0x1352bd0/d; +v0x11f2c50_0 .net *"_s0", 0 0, L_0x1352ce0; 1 drivers +v0x11f2d30_0 .net *"_s1", 0 0, L_0x1352080; 1 drivers +S_0x11f4fe0 .scope module, "zeroout" "and32" 3 63, 4 44 0, S_0xf2fc10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 32 "in" -L_0x1eb5590/d .functor AND 1, L_0x1eb5600, L_0x1eb57b0, C4<1>, C4<1>; -L_0x1eb5590 .delay 1 (30000,30000,30000) L_0x1eb5590/d; -v0x1d6ac30_0 .net *"_s10", 0 0, L_0x1eb5600; 1 drivers -v0x1d6ad10_0 .net *"_s12", 0 0, L_0x1eb57b0; 1 drivers -v0x1d6adf0_0 .net "ands", 1 0, L_0x1eb5320; 1 drivers -v0x1d6aeb0_0 .net "in", 31 0, L_0x1e026d0; alias, 1 drivers -v0x1d6af90_0 .net "out", 0 0, L_0x1eb5590; alias, 1 drivers -L_0x1eb12b0 .part L_0x1e026d0, 0, 16; -L_0x1eb5320 .concat8 [ 1 1 0 0], L_0x1eb0f50, L_0x1eb4fc0; -L_0x1eb5460 .part L_0x1e026d0, 16, 16; -L_0x1eb5600 .part L_0x1eb5320, 0, 1; -L_0x1eb57b0 .part L_0x1eb5320, 1, 1; -S_0x1d61d30 .scope module, "and_1" "and16" 4 46, 4 37 0, S_0x1d61b70; +L_0x1348e30/d .functor AND 1, L_0x1348ea0, L_0x1349050, C4<1>, C4<1>; +L_0x1348e30 .delay 1 (30000,30000,30000) L_0x1348e30/d; +v0x11fe0a0_0 .net *"_s10", 0 0, L_0x1348ea0; 1 drivers +v0x11fe180_0 .net *"_s12", 0 0, L_0x1349050; 1 drivers +v0x11fe260_0 .net "ands", 1 0, L_0x1348bc0; 1 drivers +v0x11fe320_0 .net "in", 31 0, L_0x1295d80; alias, 1 drivers +v0x11fe400_0 .net "out", 0 0, L_0x1348e30; alias, 1 drivers +L_0x1344b50 .part L_0x1295d80, 0, 16; +L_0x1348bc0 .concat8 [ 1 1 0 0], L_0x13447f0, L_0x1348860; +L_0x1348d00 .part L_0x1295d80, 16, 16; +L_0x1348ea0 .part L_0x1348bc0, 0, 1; +L_0x1349050 .part L_0x1348bc0, 1, 1; +S_0x11f51a0 .scope module, "and_1" "and16" 4 46, 4 37 0, S_0x11f4fe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 16 "in" -L_0x1eb0f50/d .functor AND 1, L_0x1eb1010, L_0x1eb11c0, C4<1>, C4<1>; -L_0x1eb0f50 .delay 1 (30000,30000,30000) L_0x1eb0f50/d; -v0x1d66000_0 .net *"_s10", 0 0, L_0x1eb1010; 1 drivers -v0x1d660e0_0 .net *"_s12", 0 0, L_0x1eb11c0; 1 drivers -v0x1d661c0_0 .net "ands", 1 0, L_0x1eb0d20; 1 drivers -v0x1d66280_0 .net "in", 15 0, L_0x1eb12b0; 1 drivers -v0x1d66360_0 .net "out", 0 0, L_0x1eb0f50; 1 drivers -L_0x1eaefb0 .part L_0x1eb12b0, 0, 8; -L_0x1eb0d20 .concat8 [ 1 1 0 0], L_0x1eaec50, L_0x1eb09c0; -L_0x1eb0e60 .part L_0x1eb12b0, 8, 8; -L_0x1eb1010 .part L_0x1eb0d20, 0, 1; -L_0x1eb11c0 .part L_0x1eb0d20, 1, 1; -S_0x1d61f80 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x1d61d30; +L_0x13447f0/d .functor AND 1, L_0x13448b0, L_0x1344a60, C4<1>, C4<1>; +L_0x13447f0 .delay 1 (30000,30000,30000) L_0x13447f0/d; +v0x11f9470_0 .net *"_s10", 0 0, L_0x13448b0; 1 drivers +v0x11f9550_0 .net *"_s12", 0 0, L_0x1344a60; 1 drivers +v0x11f9630_0 .net "ands", 1 0, L_0x13445c0; 1 drivers +v0x11f96f0_0 .net "in", 15 0, L_0x1344b50; 1 drivers +v0x11f97d0_0 .net "out", 0 0, L_0x13447f0; 1 drivers +L_0x1342850 .part L_0x1344b50, 0, 8; +L_0x13445c0 .concat8 [ 1 1 0 0], L_0x13424f0, L_0x1344260; +L_0x1344700 .part L_0x1344b50, 8, 8; +L_0x13448b0 .part L_0x13445c0, 0, 1; +L_0x1344a60 .part L_0x13445c0, 1, 1; +S_0x11f53f0 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x11f51a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1eaec50/d .functor AND 1, L_0x1eaed10, L_0x1eaeec0, C4<1>, C4<1>; -L_0x1eaec50 .delay 1 (30000,30000,30000) L_0x1eaec50/d; -v0x1d63b60_0 .net *"_s10", 0 0, L_0x1eaed10; 1 drivers -v0x1d63c40_0 .net *"_s12", 0 0, L_0x1eaeec0; 1 drivers -v0x1d63d20_0 .net "ands", 1 0, L_0x1eaea20; 1 drivers -v0x1d63de0_0 .net "in", 7 0, L_0x1eaefb0; 1 drivers -v0x1d63ec0_0 .net "out", 0 0, L_0x1eaec50; 1 drivers -L_0x1eae0d0 .part L_0x1eaefb0, 0, 4; -L_0x1eaea20 .concat8 [ 1 1 0 0], L_0x1eadf20, L_0x1eae710; -L_0x1eaeb60 .part L_0x1eaefb0, 4, 4; -L_0x1eaed10 .part L_0x1eaea20, 0, 1; -L_0x1eaeec0 .part L_0x1eaea20, 1, 1; -S_0x1d621d0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d61f80; +L_0x13424f0/d .functor AND 1, L_0x13425b0, L_0x1342760, C4<1>, C4<1>; +L_0x13424f0 .delay 1 (30000,30000,30000) L_0x13424f0/d; +v0x11f6fd0_0 .net *"_s10", 0 0, L_0x13425b0; 1 drivers +v0x11f70b0_0 .net *"_s12", 0 0, L_0x1342760; 1 drivers +v0x11f7190_0 .net "ands", 1 0, L_0x13422c0; 1 drivers +v0x11f7250_0 .net "in", 7 0, L_0x1342850; 1 drivers +v0x11f7330_0 .net "out", 0 0, L_0x13424f0; 1 drivers +L_0x1341970 .part L_0x1342850, 0, 4; +L_0x13422c0 .concat8 [ 1 1 0 0], L_0x13417c0, L_0x1341fb0; +L_0x1342400 .part L_0x1342850, 4, 4; +L_0x13425b0 .part L_0x13422c0, 0, 1; +L_0x1342760 .part L_0x13422c0, 1, 1; +S_0x11f5640 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11f53f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eac7b0/d .functor AND 1, L_0x1eadb00, L_0x1eadba0, C4<1>, C4<1>; -L_0x1eac7b0 .delay 1 (30000,30000,30000) L_0x1eac7b0/d; -L_0x1eadce0/d .functor AND 1, L_0x1eadd50, L_0x1eaddf0, C4<1>, C4<1>; -L_0x1eadce0 .delay 1 (30000,30000,30000) L_0x1eadce0/d; -L_0x1eadf20/d .functor AND 1, L_0x1eadf90, L_0x1eae030, C4<1>, C4<1>; -L_0x1eadf20 .delay 1 (30000,30000,30000) L_0x1eadf20/d; -v0x1d62420_0 .net *"_s0", 0 0, L_0x1eac7b0; 1 drivers -v0x1d62520_0 .net *"_s10", 0 0, L_0x1eadd50; 1 drivers -v0x1d62600_0 .net *"_s12", 0 0, L_0x1eaddf0; 1 drivers -v0x1d626c0_0 .net *"_s14", 0 0, L_0x1eadf90; 1 drivers -v0x1d627a0_0 .net *"_s16", 0 0, L_0x1eae030; 1 drivers -v0x1d628d0_0 .net *"_s3", 0 0, L_0x1eadb00; 1 drivers -v0x1d629b0_0 .net *"_s5", 0 0, L_0x1eadba0; 1 drivers -v0x1d62a90_0 .net *"_s6", 0 0, L_0x1eadce0; 1 drivers -v0x1d62b70_0 .net "ands", 1 0, L_0x1eadc40; 1 drivers -v0x1d62ce0_0 .net "in", 3 0, L_0x1eae0d0; 1 drivers -v0x1d62dc0_0 .net "out", 0 0, L_0x1eadf20; 1 drivers -L_0x1eadb00 .part L_0x1eae0d0, 0, 1; -L_0x1eadba0 .part L_0x1eae0d0, 1, 1; -L_0x1eadc40 .concat8 [ 1 1 0 0], L_0x1eac7b0, L_0x1eadce0; -L_0x1eadd50 .part L_0x1eae0d0, 2, 1; -L_0x1eaddf0 .part L_0x1eae0d0, 3, 1; -L_0x1eadf90 .part L_0x1eadc40, 0, 1; -L_0x1eae030 .part L_0x1eadc40, 1, 1; -S_0x1d62ee0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d61f80; +L_0x13400c0/d .functor AND 1, L_0x1341410, L_0x13414b0, C4<1>, C4<1>; +L_0x13400c0 .delay 1 (30000,30000,30000) L_0x13400c0/d; +L_0x129fec0/d .functor AND 1, L_0x13415f0, L_0x1341690, C4<1>, C4<1>; +L_0x129fec0 .delay 1 (30000,30000,30000) L_0x129fec0/d; +L_0x13417c0/d .functor AND 1, L_0x1341830, L_0x13418d0, C4<1>, C4<1>; +L_0x13417c0 .delay 1 (30000,30000,30000) L_0x13417c0/d; +v0x11f5890_0 .net *"_s0", 0 0, L_0x13400c0; 1 drivers +v0x11f5990_0 .net *"_s10", 0 0, L_0x13415f0; 1 drivers +v0x11f5a70_0 .net *"_s12", 0 0, L_0x1341690; 1 drivers +v0x11f5b30_0 .net *"_s14", 0 0, L_0x1341830; 1 drivers +v0x11f5c10_0 .net *"_s16", 0 0, L_0x13418d0; 1 drivers +v0x11f5d40_0 .net *"_s3", 0 0, L_0x1341410; 1 drivers +v0x11f5e20_0 .net *"_s5", 0 0, L_0x13414b0; 1 drivers +v0x11f5f00_0 .net *"_s6", 0 0, L_0x129fec0; 1 drivers +v0x11f5fe0_0 .net "ands", 1 0, L_0x1341550; 1 drivers +v0x11f6150_0 .net "in", 3 0, L_0x1341970; 1 drivers +v0x11f6230_0 .net "out", 0 0, L_0x13417c0; 1 drivers +L_0x1341410 .part L_0x1341970, 0, 1; +L_0x13414b0 .part L_0x1341970, 1, 1; +L_0x1341550 .concat8 [ 1 1 0 0], L_0x13400c0, L_0x129fec0; +L_0x13415f0 .part L_0x1341970, 2, 1; +L_0x1341690 .part L_0x1341970, 3, 1; +L_0x1341830 .part L_0x1341550, 0, 1; +L_0x13418d0 .part L_0x1341550, 1, 1; +S_0x11f6350 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11f53f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eae170/d .functor AND 1, L_0x1eae1e0, L_0x1eae280, C4<1>, C4<1>; -L_0x1eae170 .delay 1 (30000,30000,30000) L_0x1eae170/d; -L_0x1eae3c0/d .functor AND 1, L_0x1eae430, L_0x1eae590, C4<1>, C4<1>; -L_0x1eae3c0 .delay 1 (30000,30000,30000) L_0x1eae3c0/d; -L_0x1eae710/d .functor AND 1, L_0x1eae780, L_0x1eae930, C4<1>, C4<1>; -L_0x1eae710 .delay 1 (30000,30000,30000) L_0x1eae710/d; -v0x1d630a0_0 .net *"_s0", 0 0, L_0x1eae170; 1 drivers -v0x1d631a0_0 .net *"_s10", 0 0, L_0x1eae430; 1 drivers -v0x1d63280_0 .net *"_s12", 0 0, L_0x1eae590; 1 drivers -v0x1d63340_0 .net *"_s14", 0 0, L_0x1eae780; 1 drivers -v0x1d63420_0 .net *"_s16", 0 0, L_0x1eae930; 1 drivers -v0x1d63550_0 .net *"_s3", 0 0, L_0x1eae1e0; 1 drivers -v0x1d63630_0 .net *"_s5", 0 0, L_0x1eae280; 1 drivers -v0x1d63710_0 .net *"_s6", 0 0, L_0x1eae3c0; 1 drivers -v0x1d637f0_0 .net "ands", 1 0, L_0x1eae320; 1 drivers -v0x1d63960_0 .net "in", 3 0, L_0x1eaeb60; 1 drivers -v0x1d63a40_0 .net "out", 0 0, L_0x1eae710; 1 drivers -L_0x1eae1e0 .part L_0x1eaeb60, 0, 1; -L_0x1eae280 .part L_0x1eaeb60, 1, 1; -L_0x1eae320 .concat8 [ 1 1 0 0], L_0x1eae170, L_0x1eae3c0; -L_0x1eae430 .part L_0x1eaeb60, 2, 1; -L_0x1eae590 .part L_0x1eaeb60, 3, 1; -L_0x1eae780 .part L_0x1eae320, 0, 1; -L_0x1eae930 .part L_0x1eae320, 1, 1; -S_0x1d63fe0 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x1d61d30; +L_0x1341a10/d .functor AND 1, L_0x1341a80, L_0x1341b20, C4<1>, C4<1>; +L_0x1341a10 .delay 1 (30000,30000,30000) L_0x1341a10/d; +L_0x1341c60/d .functor AND 1, L_0x1341cd0, L_0x1341e30, C4<1>, C4<1>; +L_0x1341c60 .delay 1 (30000,30000,30000) L_0x1341c60/d; +L_0x1341fb0/d .functor AND 1, L_0x1342020, L_0x13421d0, C4<1>, C4<1>; +L_0x1341fb0 .delay 1 (30000,30000,30000) L_0x1341fb0/d; +v0x11f6510_0 .net *"_s0", 0 0, L_0x1341a10; 1 drivers +v0x11f6610_0 .net *"_s10", 0 0, L_0x1341cd0; 1 drivers +v0x11f66f0_0 .net *"_s12", 0 0, L_0x1341e30; 1 drivers +v0x11f67b0_0 .net *"_s14", 0 0, L_0x1342020; 1 drivers +v0x11f6890_0 .net *"_s16", 0 0, L_0x13421d0; 1 drivers +v0x11f69c0_0 .net *"_s3", 0 0, L_0x1341a80; 1 drivers +v0x11f6aa0_0 .net *"_s5", 0 0, L_0x1341b20; 1 drivers +v0x11f6b80_0 .net *"_s6", 0 0, L_0x1341c60; 1 drivers +v0x11f6c60_0 .net "ands", 1 0, L_0x1341bc0; 1 drivers +v0x11f6dd0_0 .net "in", 3 0, L_0x1342400; 1 drivers +v0x11f6eb0_0 .net "out", 0 0, L_0x1341fb0; 1 drivers +L_0x1341a80 .part L_0x1342400, 0, 1; +L_0x1341b20 .part L_0x1342400, 1, 1; +L_0x1341bc0 .concat8 [ 1 1 0 0], L_0x1341a10, L_0x1341c60; +L_0x1341cd0 .part L_0x1342400, 2, 1; +L_0x1341e30 .part L_0x1342400, 3, 1; +L_0x1342020 .part L_0x1341bc0, 0, 1; +L_0x13421d0 .part L_0x1341bc0, 1, 1; +S_0x11f7450 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x11f51a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1eb09c0/d .functor AND 1, L_0x1eb0a80, L_0x1eb0c30, C4<1>, C4<1>; -L_0x1eb09c0 .delay 1 (30000,30000,30000) L_0x1eb09c0/d; -v0x1d65b80_0 .net *"_s10", 0 0, L_0x1eb0a80; 1 drivers -v0x1d65c60_0 .net *"_s12", 0 0, L_0x1eb0c30; 1 drivers -v0x1d65d40_0 .net "ands", 1 0, L_0x1eb0790; 1 drivers -v0x1d65e00_0 .net "in", 7 0, L_0x1eb0e60; 1 drivers -v0x1d65ee0_0 .net "out", 0 0, L_0x1eb09c0; 1 drivers -L_0x1eafba0 .part L_0x1eb0e60, 0, 4; -L_0x1eb0790 .concat8 [ 1 1 0 0], L_0x1eaf890, L_0x1eb0480; -L_0x1eb08d0 .part L_0x1eb0e60, 4, 4; -L_0x1eb0a80 .part L_0x1eb0790, 0, 1; -L_0x1eb0c30 .part L_0x1eb0790, 1, 1; -S_0x1d641f0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d63fe0; +L_0x1344260/d .functor AND 1, L_0x1344320, L_0x13444d0, C4<1>, C4<1>; +L_0x1344260 .delay 1 (30000,30000,30000) L_0x1344260/d; +v0x11f8ff0_0 .net *"_s10", 0 0, L_0x1344320; 1 drivers +v0x11f90d0_0 .net *"_s12", 0 0, L_0x13444d0; 1 drivers +v0x11f91b0_0 .net "ands", 1 0, L_0x1344030; 1 drivers +v0x11f9270_0 .net "in", 7 0, L_0x1344700; 1 drivers +v0x11f9350_0 .net "out", 0 0, L_0x1344260; 1 drivers +L_0x1343440 .part L_0x1344700, 0, 4; +L_0x1344030 .concat8 [ 1 1 0 0], L_0x1343130, L_0x1343d20; +L_0x1344170 .part L_0x1344700, 4, 4; +L_0x1344320 .part L_0x1344030, 0, 1; +L_0x13444d0 .part L_0x1344030, 1, 1; +S_0x11f7660 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11f7450; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eaf050/d .functor AND 1, L_0x1eaf110, L_0x1eaf270, C4<1>, C4<1>; -L_0x1eaf050 .delay 1 (30000,30000,30000) L_0x1eaf050/d; -L_0x1eaf4a0/d .functor AND 1, L_0x1eaf5b0, L_0x1eaf710, C4<1>, C4<1>; -L_0x1eaf4a0 .delay 1 (30000,30000,30000) L_0x1eaf4a0/d; -L_0x1eaf890/d .functor AND 1, L_0x1eaf900, L_0x1eafab0, C4<1>, C4<1>; -L_0x1eaf890 .delay 1 (30000,30000,30000) L_0x1eaf890/d; -v0x1d64440_0 .net *"_s0", 0 0, L_0x1eaf050; 1 drivers -v0x1d64540_0 .net *"_s10", 0 0, L_0x1eaf5b0; 1 drivers -v0x1d64620_0 .net *"_s12", 0 0, L_0x1eaf710; 1 drivers -v0x1d646e0_0 .net *"_s14", 0 0, L_0x1eaf900; 1 drivers -v0x1d647c0_0 .net *"_s16", 0 0, L_0x1eafab0; 1 drivers -v0x1d648f0_0 .net *"_s3", 0 0, L_0x1eaf110; 1 drivers -v0x1d649d0_0 .net *"_s5", 0 0, L_0x1eaf270; 1 drivers -v0x1d64ab0_0 .net *"_s6", 0 0, L_0x1eaf4a0; 1 drivers -v0x1d64b90_0 .net "ands", 1 0, L_0x1eaf3b0; 1 drivers -v0x1d64d00_0 .net "in", 3 0, L_0x1eafba0; 1 drivers -v0x1d64de0_0 .net "out", 0 0, L_0x1eaf890; 1 drivers -L_0x1eaf110 .part L_0x1eafba0, 0, 1; -L_0x1eaf270 .part L_0x1eafba0, 1, 1; -L_0x1eaf3b0 .concat8 [ 1 1 0 0], L_0x1eaf050, L_0x1eaf4a0; -L_0x1eaf5b0 .part L_0x1eafba0, 2, 1; -L_0x1eaf710 .part L_0x1eafba0, 3, 1; -L_0x1eaf900 .part L_0x1eaf3b0, 0, 1; -L_0x1eafab0 .part L_0x1eaf3b0, 1, 1; -S_0x1d64f00 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d63fe0; +L_0x13428f0/d .functor AND 1, L_0x13429b0, L_0x1342b10, C4<1>, C4<1>; +L_0x13428f0 .delay 1 (30000,30000,30000) L_0x13428f0/d; +L_0x1342d40/d .functor AND 1, L_0x1342e50, L_0x1342fb0, C4<1>, C4<1>; +L_0x1342d40 .delay 1 (30000,30000,30000) L_0x1342d40/d; +L_0x1343130/d .functor AND 1, L_0x13431a0, L_0x1343350, C4<1>, C4<1>; +L_0x1343130 .delay 1 (30000,30000,30000) L_0x1343130/d; +v0x11f78b0_0 .net *"_s0", 0 0, L_0x13428f0; 1 drivers +v0x11f79b0_0 .net *"_s10", 0 0, L_0x1342e50; 1 drivers +v0x11f7a90_0 .net *"_s12", 0 0, L_0x1342fb0; 1 drivers +v0x11f7b50_0 .net *"_s14", 0 0, L_0x13431a0; 1 drivers +v0x11f7c30_0 .net *"_s16", 0 0, L_0x1343350; 1 drivers +v0x11f7d60_0 .net *"_s3", 0 0, L_0x13429b0; 1 drivers +v0x11f7e40_0 .net *"_s5", 0 0, L_0x1342b10; 1 drivers +v0x11f7f20_0 .net *"_s6", 0 0, L_0x1342d40; 1 drivers +v0x11f8000_0 .net "ands", 1 0, L_0x1342c50; 1 drivers +v0x11f8170_0 .net "in", 3 0, L_0x1343440; 1 drivers +v0x11f8250_0 .net "out", 0 0, L_0x1343130; 1 drivers +L_0x13429b0 .part L_0x1343440, 0, 1; +L_0x1342b10 .part L_0x1343440, 1, 1; +L_0x1342c50 .concat8 [ 1 1 0 0], L_0x13428f0, L_0x1342d40; +L_0x1342e50 .part L_0x1343440, 2, 1; +L_0x1342fb0 .part L_0x1343440, 3, 1; +L_0x13431a0 .part L_0x1342c50, 0, 1; +L_0x1343350 .part L_0x1342c50, 1, 1; +S_0x11f8370 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11f7450; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eafc40/d .functor AND 1, L_0x1eafd00, L_0x1eafe60, C4<1>, C4<1>; -L_0x1eafc40 .delay 1 (30000,30000,30000) L_0x1eafc40/d; -L_0x1eb0090/d .functor AND 1, L_0x1eb01a0, L_0x1eb0300, C4<1>, C4<1>; -L_0x1eb0090 .delay 1 (30000,30000,30000) L_0x1eb0090/d; -L_0x1eb0480/d .functor AND 1, L_0x1eb04f0, L_0x1eb06a0, C4<1>, C4<1>; -L_0x1eb0480 .delay 1 (30000,30000,30000) L_0x1eb0480/d; -v0x1d650c0_0 .net *"_s0", 0 0, L_0x1eafc40; 1 drivers -v0x1d651c0_0 .net *"_s10", 0 0, L_0x1eb01a0; 1 drivers -v0x1d652a0_0 .net *"_s12", 0 0, L_0x1eb0300; 1 drivers -v0x1d65360_0 .net *"_s14", 0 0, L_0x1eb04f0; 1 drivers -v0x1d65440_0 .net *"_s16", 0 0, L_0x1eb06a0; 1 drivers -v0x1d65570_0 .net *"_s3", 0 0, L_0x1eafd00; 1 drivers -v0x1d65650_0 .net *"_s5", 0 0, L_0x1eafe60; 1 drivers -v0x1d65730_0 .net *"_s6", 0 0, L_0x1eb0090; 1 drivers -v0x1d65810_0 .net "ands", 1 0, L_0x1eaffa0; 1 drivers -v0x1d65980_0 .net "in", 3 0, L_0x1eb08d0; 1 drivers -v0x1d65a60_0 .net "out", 0 0, L_0x1eb0480; 1 drivers -L_0x1eafd00 .part L_0x1eb08d0, 0, 1; -L_0x1eafe60 .part L_0x1eb08d0, 1, 1; -L_0x1eaffa0 .concat8 [ 1 1 0 0], L_0x1eafc40, L_0x1eb0090; -L_0x1eb01a0 .part L_0x1eb08d0, 2, 1; -L_0x1eb0300 .part L_0x1eb08d0, 3, 1; -L_0x1eb04f0 .part L_0x1eaffa0, 0, 1; -L_0x1eb06a0 .part L_0x1eaffa0, 1, 1; -S_0x1d664d0 .scope module, "and_2" "and16" 4 47, 4 37 0, S_0x1d61b70; +L_0x13434e0/d .functor AND 1, L_0x13435a0, L_0x1343700, C4<1>, C4<1>; +L_0x13434e0 .delay 1 (30000,30000,30000) L_0x13434e0/d; +L_0x1343930/d .functor AND 1, L_0x1343a40, L_0x1343ba0, C4<1>, C4<1>; +L_0x1343930 .delay 1 (30000,30000,30000) L_0x1343930/d; +L_0x1343d20/d .functor AND 1, L_0x1343d90, L_0x1343f40, C4<1>, C4<1>; +L_0x1343d20 .delay 1 (30000,30000,30000) L_0x1343d20/d; +v0x11f8530_0 .net *"_s0", 0 0, L_0x13434e0; 1 drivers +v0x11f8630_0 .net *"_s10", 0 0, L_0x1343a40; 1 drivers +v0x11f8710_0 .net *"_s12", 0 0, L_0x1343ba0; 1 drivers +v0x11f87d0_0 .net *"_s14", 0 0, L_0x1343d90; 1 drivers +v0x11f88b0_0 .net *"_s16", 0 0, L_0x1343f40; 1 drivers +v0x11f89e0_0 .net *"_s3", 0 0, L_0x13435a0; 1 drivers +v0x11f8ac0_0 .net *"_s5", 0 0, L_0x1343700; 1 drivers +v0x11f8ba0_0 .net *"_s6", 0 0, L_0x1343930; 1 drivers +v0x11f8c80_0 .net "ands", 1 0, L_0x1343840; 1 drivers +v0x11f8df0_0 .net "in", 3 0, L_0x1344170; 1 drivers +v0x11f8ed0_0 .net "out", 0 0, L_0x1343d20; 1 drivers +L_0x13435a0 .part L_0x1344170, 0, 1; +L_0x1343700 .part L_0x1344170, 1, 1; +L_0x1343840 .concat8 [ 1 1 0 0], L_0x13434e0, L_0x1343930; +L_0x1343a40 .part L_0x1344170, 2, 1; +L_0x1343ba0 .part L_0x1344170, 3, 1; +L_0x1343d90 .part L_0x1343840, 0, 1; +L_0x1343f40 .part L_0x1343840, 1, 1; +S_0x11f9940 .scope module, "and_2" "and16" 4 47, 4 37 0, S_0x11f4fe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 16 "in" -L_0x1eb4fc0/d .functor AND 1, L_0x1eb5080, L_0x1eb5230, C4<1>, C4<1>; -L_0x1eb4fc0 .delay 1 (30000,30000,30000) L_0x1eb4fc0/d; -v0x1d6a760_0 .net *"_s10", 0 0, L_0x1eb5080; 1 drivers -v0x1d6a840_0 .net *"_s12", 0 0, L_0x1eb5230; 1 drivers -v0x1d6a920_0 .net "ands", 1 0, L_0x1eb4d90; 1 drivers -v0x1d6a9e0_0 .net "in", 15 0, L_0x1eb5460; 1 drivers -v0x1d6aac0_0 .net "out", 0 0, L_0x1eb4fc0; 1 drivers -L_0x1eb3020 .part L_0x1eb5460, 0, 8; -L_0x1eb4d90 .concat8 [ 1 1 0 0], L_0x1eb2cc0, L_0x1eb4a30; -L_0x1eb4ed0 .part L_0x1eb5460, 8, 8; -L_0x1eb5080 .part L_0x1eb4d90, 0, 1; -L_0x1eb5230 .part L_0x1eb4d90, 1, 1; -S_0x1d666e0 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x1d664d0; +L_0x1348860/d .functor AND 1, L_0x1348920, L_0x1348ad0, C4<1>, C4<1>; +L_0x1348860 .delay 1 (30000,30000,30000) L_0x1348860/d; +v0x11fdbd0_0 .net *"_s10", 0 0, L_0x1348920; 1 drivers +v0x11fdcb0_0 .net *"_s12", 0 0, L_0x1348ad0; 1 drivers +v0x11fdd90_0 .net "ands", 1 0, L_0x1348630; 1 drivers +v0x11fde50_0 .net "in", 15 0, L_0x1348d00; 1 drivers +v0x11fdf30_0 .net "out", 0 0, L_0x1348860; 1 drivers +L_0x13468c0 .part L_0x1348d00, 0, 8; +L_0x1348630 .concat8 [ 1 1 0 0], L_0x1346560, L_0x13482d0; +L_0x1348770 .part L_0x1348d00, 8, 8; +L_0x1348920 .part L_0x1348630, 0, 1; +L_0x1348ad0 .part L_0x1348630, 1, 1; +S_0x11f9b50 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x11f9940; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1eb2cc0/d .functor AND 1, L_0x1eb2d80, L_0x1eb2f30, C4<1>, C4<1>; -L_0x1eb2cc0 .delay 1 (30000,30000,30000) L_0x1eb2cc0/d; -v0x1d682c0_0 .net *"_s10", 0 0, L_0x1eb2d80; 1 drivers -v0x1d683a0_0 .net *"_s12", 0 0, L_0x1eb2f30; 1 drivers -v0x1d68480_0 .net "ands", 1 0, L_0x1eb2a90; 1 drivers -v0x1d68540_0 .net "in", 7 0, L_0x1eb3020; 1 drivers -v0x1d68620_0 .net "out", 0 0, L_0x1eb2cc0; 1 drivers -L_0x1eb1ea0 .part L_0x1eb3020, 0, 4; -L_0x1eb2a90 .concat8 [ 1 1 0 0], L_0x1eb1b90, L_0x1eb2780; -L_0x1eb2bd0 .part L_0x1eb3020, 4, 4; -L_0x1eb2d80 .part L_0x1eb2a90, 0, 1; -L_0x1eb2f30 .part L_0x1eb2a90, 1, 1; -S_0x1d66930 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d666e0; +L_0x1346560/d .functor AND 1, L_0x1346620, L_0x13467d0, C4<1>, C4<1>; +L_0x1346560 .delay 1 (30000,30000,30000) L_0x1346560/d; +v0x11fb730_0 .net *"_s10", 0 0, L_0x1346620; 1 drivers +v0x11fb810_0 .net *"_s12", 0 0, L_0x13467d0; 1 drivers +v0x11fb8f0_0 .net "ands", 1 0, L_0x1346330; 1 drivers +v0x11fb9b0_0 .net "in", 7 0, L_0x13468c0; 1 drivers +v0x11fba90_0 .net "out", 0 0, L_0x1346560; 1 drivers +L_0x1345740 .part L_0x13468c0, 0, 4; +L_0x1346330 .concat8 [ 1 1 0 0], L_0x1345430, L_0x1346020; +L_0x1346470 .part L_0x13468c0, 4, 4; +L_0x1346620 .part L_0x1346330, 0, 1; +L_0x13467d0 .part L_0x1346330, 1, 1; +S_0x11f9da0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11f9b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eb1350/d .functor AND 1, L_0x1eb1410, L_0x1eb1570, C4<1>, C4<1>; -L_0x1eb1350 .delay 1 (30000,30000,30000) L_0x1eb1350/d; -L_0x1eb17a0/d .functor AND 1, L_0x1eb18b0, L_0x1eb1a10, C4<1>, C4<1>; -L_0x1eb17a0 .delay 1 (30000,30000,30000) L_0x1eb17a0/d; -L_0x1eb1b90/d .functor AND 1, L_0x1eb1c00, L_0x1eb1db0, C4<1>, C4<1>; -L_0x1eb1b90 .delay 1 (30000,30000,30000) L_0x1eb1b90/d; -v0x1d66b80_0 .net *"_s0", 0 0, L_0x1eb1350; 1 drivers -v0x1d66c80_0 .net *"_s10", 0 0, L_0x1eb18b0; 1 drivers -v0x1d66d60_0 .net *"_s12", 0 0, L_0x1eb1a10; 1 drivers -v0x1d66e20_0 .net *"_s14", 0 0, L_0x1eb1c00; 1 drivers -v0x1d66f00_0 .net *"_s16", 0 0, L_0x1eb1db0; 1 drivers -v0x1d67030_0 .net *"_s3", 0 0, L_0x1eb1410; 1 drivers -v0x1d67110_0 .net *"_s5", 0 0, L_0x1eb1570; 1 drivers -v0x1d671f0_0 .net *"_s6", 0 0, L_0x1eb17a0; 1 drivers -v0x1d672d0_0 .net "ands", 1 0, L_0x1eb16b0; 1 drivers -v0x1d67440_0 .net "in", 3 0, L_0x1eb1ea0; 1 drivers -v0x1d67520_0 .net "out", 0 0, L_0x1eb1b90; 1 drivers -L_0x1eb1410 .part L_0x1eb1ea0, 0, 1; -L_0x1eb1570 .part L_0x1eb1ea0, 1, 1; -L_0x1eb16b0 .concat8 [ 1 1 0 0], L_0x1eb1350, L_0x1eb17a0; -L_0x1eb18b0 .part L_0x1eb1ea0, 2, 1; -L_0x1eb1a10 .part L_0x1eb1ea0, 3, 1; -L_0x1eb1c00 .part L_0x1eb16b0, 0, 1; -L_0x1eb1db0 .part L_0x1eb16b0, 1, 1; -S_0x1d67640 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d666e0; +L_0x1344bf0/d .functor AND 1, L_0x1344cb0, L_0x1344e10, C4<1>, C4<1>; +L_0x1344bf0 .delay 1 (30000,30000,30000) L_0x1344bf0/d; +L_0x1345040/d .functor AND 1, L_0x1345150, L_0x13452b0, C4<1>, C4<1>; +L_0x1345040 .delay 1 (30000,30000,30000) L_0x1345040/d; +L_0x1345430/d .functor AND 1, L_0x13454a0, L_0x1345650, C4<1>, C4<1>; +L_0x1345430 .delay 1 (30000,30000,30000) L_0x1345430/d; +v0x11f9ff0_0 .net *"_s0", 0 0, L_0x1344bf0; 1 drivers +v0x11fa0f0_0 .net *"_s10", 0 0, L_0x1345150; 1 drivers +v0x11fa1d0_0 .net *"_s12", 0 0, L_0x13452b0; 1 drivers +v0x11fa290_0 .net *"_s14", 0 0, L_0x13454a0; 1 drivers +v0x11fa370_0 .net *"_s16", 0 0, L_0x1345650; 1 drivers +v0x11fa4a0_0 .net *"_s3", 0 0, L_0x1344cb0; 1 drivers +v0x11fa580_0 .net *"_s5", 0 0, L_0x1344e10; 1 drivers +v0x11fa660_0 .net *"_s6", 0 0, L_0x1345040; 1 drivers +v0x11fa740_0 .net "ands", 1 0, L_0x1344f50; 1 drivers +v0x11fa8b0_0 .net "in", 3 0, L_0x1345740; 1 drivers +v0x11fa990_0 .net "out", 0 0, L_0x1345430; 1 drivers +L_0x1344cb0 .part L_0x1345740, 0, 1; +L_0x1344e10 .part L_0x1345740, 1, 1; +L_0x1344f50 .concat8 [ 1 1 0 0], L_0x1344bf0, L_0x1345040; +L_0x1345150 .part L_0x1345740, 2, 1; +L_0x13452b0 .part L_0x1345740, 3, 1; +L_0x13454a0 .part L_0x1344f50, 0, 1; +L_0x1345650 .part L_0x1344f50, 1, 1; +S_0x11faab0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11f9b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eb1f40/d .functor AND 1, L_0x1eb2000, L_0x1eb2160, C4<1>, C4<1>; -L_0x1eb1f40 .delay 1 (30000,30000,30000) L_0x1eb1f40/d; -L_0x1eb2390/d .functor AND 1, L_0x1eb24a0, L_0x1eb2600, C4<1>, C4<1>; -L_0x1eb2390 .delay 1 (30000,30000,30000) L_0x1eb2390/d; -L_0x1eb2780/d .functor AND 1, L_0x1eb27f0, L_0x1eb29a0, C4<1>, C4<1>; -L_0x1eb2780 .delay 1 (30000,30000,30000) L_0x1eb2780/d; -v0x1d67800_0 .net *"_s0", 0 0, L_0x1eb1f40; 1 drivers -v0x1d67900_0 .net *"_s10", 0 0, L_0x1eb24a0; 1 drivers -v0x1d679e0_0 .net *"_s12", 0 0, L_0x1eb2600; 1 drivers -v0x1d67aa0_0 .net *"_s14", 0 0, L_0x1eb27f0; 1 drivers -v0x1d67b80_0 .net *"_s16", 0 0, L_0x1eb29a0; 1 drivers -v0x1d67cb0_0 .net *"_s3", 0 0, L_0x1eb2000; 1 drivers -v0x1d67d90_0 .net *"_s5", 0 0, L_0x1eb2160; 1 drivers -v0x1d67e70_0 .net *"_s6", 0 0, L_0x1eb2390; 1 drivers -v0x1d67f50_0 .net "ands", 1 0, L_0x1eb22a0; 1 drivers -v0x1d680c0_0 .net "in", 3 0, L_0x1eb2bd0; 1 drivers -v0x1d681a0_0 .net "out", 0 0, L_0x1eb2780; 1 drivers -L_0x1eb2000 .part L_0x1eb2bd0, 0, 1; -L_0x1eb2160 .part L_0x1eb2bd0, 1, 1; -L_0x1eb22a0 .concat8 [ 1 1 0 0], L_0x1eb1f40, L_0x1eb2390; -L_0x1eb24a0 .part L_0x1eb2bd0, 2, 1; -L_0x1eb2600 .part L_0x1eb2bd0, 3, 1; -L_0x1eb27f0 .part L_0x1eb22a0, 0, 1; -L_0x1eb29a0 .part L_0x1eb22a0, 1, 1; -S_0x1d68740 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x1d664d0; +L_0x13457e0/d .functor AND 1, L_0x13458a0, L_0x1345a00, C4<1>, C4<1>; +L_0x13457e0 .delay 1 (30000,30000,30000) L_0x13457e0/d; +L_0x1345c30/d .functor AND 1, L_0x1345d40, L_0x1345ea0, C4<1>, C4<1>; +L_0x1345c30 .delay 1 (30000,30000,30000) L_0x1345c30/d; +L_0x1346020/d .functor AND 1, L_0x1346090, L_0x1346240, C4<1>, C4<1>; +L_0x1346020 .delay 1 (30000,30000,30000) L_0x1346020/d; +v0x11fac70_0 .net *"_s0", 0 0, L_0x13457e0; 1 drivers +v0x11fad70_0 .net *"_s10", 0 0, L_0x1345d40; 1 drivers +v0x11fae50_0 .net *"_s12", 0 0, L_0x1345ea0; 1 drivers +v0x11faf10_0 .net *"_s14", 0 0, L_0x1346090; 1 drivers +v0x11faff0_0 .net *"_s16", 0 0, L_0x1346240; 1 drivers +v0x11fb120_0 .net *"_s3", 0 0, L_0x13458a0; 1 drivers +v0x11fb200_0 .net *"_s5", 0 0, L_0x1345a00; 1 drivers +v0x11fb2e0_0 .net *"_s6", 0 0, L_0x1345c30; 1 drivers +v0x11fb3c0_0 .net "ands", 1 0, L_0x1345b40; 1 drivers +v0x11fb530_0 .net "in", 3 0, L_0x1346470; 1 drivers +v0x11fb610_0 .net "out", 0 0, L_0x1346020; 1 drivers +L_0x13458a0 .part L_0x1346470, 0, 1; +L_0x1345a00 .part L_0x1346470, 1, 1; +L_0x1345b40 .concat8 [ 1 1 0 0], L_0x13457e0, L_0x1345c30; +L_0x1345d40 .part L_0x1346470, 2, 1; +L_0x1345ea0 .part L_0x1346470, 3, 1; +L_0x1346090 .part L_0x1345b40, 0, 1; +L_0x1346240 .part L_0x1345b40, 1, 1; +S_0x11fbbb0 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x11f9940; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1eb4a30/d .functor AND 1, L_0x1eb4af0, L_0x1eb4ca0, C4<1>, C4<1>; -L_0x1eb4a30 .delay 1 (30000,30000,30000) L_0x1eb4a30/d; -v0x1d6a2e0_0 .net *"_s10", 0 0, L_0x1eb4af0; 1 drivers -v0x1d6a3c0_0 .net *"_s12", 0 0, L_0x1eb4ca0; 1 drivers -v0x1d6a4a0_0 .net "ands", 1 0, L_0x1eb4800; 1 drivers -v0x1d6a560_0 .net "in", 7 0, L_0x1eb4ed0; 1 drivers -v0x1d6a640_0 .net "out", 0 0, L_0x1eb4a30; 1 drivers -L_0x1eb3c10 .part L_0x1eb4ed0, 0, 4; -L_0x1eb4800 .concat8 [ 1 1 0 0], L_0x1eb3900, L_0x1eb44f0; -L_0x1eb4940 .part L_0x1eb4ed0, 4, 4; -L_0x1eb4af0 .part L_0x1eb4800, 0, 1; -L_0x1eb4ca0 .part L_0x1eb4800, 1, 1; -S_0x1d68950 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x1d68740; +L_0x13482d0/d .functor AND 1, L_0x1348390, L_0x1348540, C4<1>, C4<1>; +L_0x13482d0 .delay 1 (30000,30000,30000) L_0x13482d0/d; +v0x11fd750_0 .net *"_s10", 0 0, L_0x1348390; 1 drivers +v0x11fd830_0 .net *"_s12", 0 0, L_0x1348540; 1 drivers +v0x11fd910_0 .net "ands", 1 0, L_0x13480a0; 1 drivers +v0x11fd9d0_0 .net "in", 7 0, L_0x1348770; 1 drivers +v0x11fdab0_0 .net "out", 0 0, L_0x13482d0; 1 drivers +L_0x13474b0 .part L_0x1348770, 0, 4; +L_0x13480a0 .concat8 [ 1 1 0 0], L_0x13471a0, L_0x1347d90; +L_0x13481e0 .part L_0x1348770, 4, 4; +L_0x1348390 .part L_0x13480a0, 0, 1; +L_0x1348540 .part L_0x13480a0, 1, 1; +S_0x11fbdc0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11fbbb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eb30c0/d .functor AND 1, L_0x1eb3180, L_0x1eb32e0, C4<1>, C4<1>; -L_0x1eb30c0 .delay 1 (30000,30000,30000) L_0x1eb30c0/d; -L_0x1eb3510/d .functor AND 1, L_0x1eb3620, L_0x1eb3780, C4<1>, C4<1>; -L_0x1eb3510 .delay 1 (30000,30000,30000) L_0x1eb3510/d; -L_0x1eb3900/d .functor AND 1, L_0x1eb3970, L_0x1eb3b20, C4<1>, C4<1>; -L_0x1eb3900 .delay 1 (30000,30000,30000) L_0x1eb3900/d; -v0x1d68ba0_0 .net *"_s0", 0 0, L_0x1eb30c0; 1 drivers -v0x1d68ca0_0 .net *"_s10", 0 0, L_0x1eb3620; 1 drivers -v0x1d68d80_0 .net *"_s12", 0 0, L_0x1eb3780; 1 drivers -v0x1d68e40_0 .net *"_s14", 0 0, L_0x1eb3970; 1 drivers -v0x1d68f20_0 .net *"_s16", 0 0, L_0x1eb3b20; 1 drivers -v0x1d69050_0 .net *"_s3", 0 0, L_0x1eb3180; 1 drivers -v0x1d69130_0 .net *"_s5", 0 0, L_0x1eb32e0; 1 drivers -v0x1d69210_0 .net *"_s6", 0 0, L_0x1eb3510; 1 drivers -v0x1d692f0_0 .net "ands", 1 0, L_0x1eb3420; 1 drivers -v0x1d69460_0 .net "in", 3 0, L_0x1eb3c10; 1 drivers -v0x1d69540_0 .net "out", 0 0, L_0x1eb3900; 1 drivers -L_0x1eb3180 .part L_0x1eb3c10, 0, 1; -L_0x1eb32e0 .part L_0x1eb3c10, 1, 1; -L_0x1eb3420 .concat8 [ 1 1 0 0], L_0x1eb30c0, L_0x1eb3510; -L_0x1eb3620 .part L_0x1eb3c10, 2, 1; -L_0x1eb3780 .part L_0x1eb3c10, 3, 1; -L_0x1eb3970 .part L_0x1eb3420, 0, 1; -L_0x1eb3b20 .part L_0x1eb3420, 1, 1; -S_0x1d69660 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x1d68740; +L_0x1346960/d .functor AND 1, L_0x1346a20, L_0x1346b80, C4<1>, C4<1>; +L_0x1346960 .delay 1 (30000,30000,30000) L_0x1346960/d; +L_0x1346db0/d .functor AND 1, L_0x1346ec0, L_0x1347020, C4<1>, C4<1>; +L_0x1346db0 .delay 1 (30000,30000,30000) L_0x1346db0/d; +L_0x13471a0/d .functor AND 1, L_0x1347210, L_0x13473c0, C4<1>, C4<1>; +L_0x13471a0 .delay 1 (30000,30000,30000) L_0x13471a0/d; +v0x11fc010_0 .net *"_s0", 0 0, L_0x1346960; 1 drivers +v0x11fc110_0 .net *"_s10", 0 0, L_0x1346ec0; 1 drivers +v0x11fc1f0_0 .net *"_s12", 0 0, L_0x1347020; 1 drivers +v0x11fc2b0_0 .net *"_s14", 0 0, L_0x1347210; 1 drivers +v0x11fc390_0 .net *"_s16", 0 0, L_0x13473c0; 1 drivers +v0x11fc4c0_0 .net *"_s3", 0 0, L_0x1346a20; 1 drivers +v0x11fc5a0_0 .net *"_s5", 0 0, L_0x1346b80; 1 drivers +v0x11fc680_0 .net *"_s6", 0 0, L_0x1346db0; 1 drivers +v0x11fc760_0 .net "ands", 1 0, L_0x1346cc0; 1 drivers +v0x11fc8d0_0 .net "in", 3 0, L_0x13474b0; 1 drivers +v0x11fc9b0_0 .net "out", 0 0, L_0x13471a0; 1 drivers +L_0x1346a20 .part L_0x13474b0, 0, 1; +L_0x1346b80 .part L_0x13474b0, 1, 1; +L_0x1346cc0 .concat8 [ 1 1 0 0], L_0x1346960, L_0x1346db0; +L_0x1346ec0 .part L_0x13474b0, 2, 1; +L_0x1347020 .part L_0x13474b0, 3, 1; +L_0x1347210 .part L_0x1346cc0, 0, 1; +L_0x13473c0 .part L_0x1346cc0, 1, 1; +S_0x11fcad0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11fbbb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1eb3cb0/d .functor AND 1, L_0x1eb3d70, L_0x1eb3ed0, C4<1>, C4<1>; -L_0x1eb3cb0 .delay 1 (30000,30000,30000) L_0x1eb3cb0/d; -L_0x1eb4100/d .functor AND 1, L_0x1eb4210, L_0x1eb4370, C4<1>, C4<1>; -L_0x1eb4100 .delay 1 (30000,30000,30000) L_0x1eb4100/d; -L_0x1eb44f0/d .functor AND 1, L_0x1eb4560, L_0x1eb4710, C4<1>, C4<1>; -L_0x1eb44f0 .delay 1 (30000,30000,30000) L_0x1eb44f0/d; -v0x1d69820_0 .net *"_s0", 0 0, L_0x1eb3cb0; 1 drivers -v0x1d69920_0 .net *"_s10", 0 0, L_0x1eb4210; 1 drivers -v0x1d69a00_0 .net *"_s12", 0 0, L_0x1eb4370; 1 drivers -v0x1d69ac0_0 .net *"_s14", 0 0, L_0x1eb4560; 1 drivers -v0x1d69ba0_0 .net *"_s16", 0 0, L_0x1eb4710; 1 drivers -v0x1d69cd0_0 .net *"_s3", 0 0, L_0x1eb3d70; 1 drivers -v0x1d69db0_0 .net *"_s5", 0 0, L_0x1eb3ed0; 1 drivers -v0x1d69e90_0 .net *"_s6", 0 0, L_0x1eb4100; 1 drivers -v0x1d69f70_0 .net "ands", 1 0, L_0x1eb4010; 1 drivers -v0x1d6a0e0_0 .net "in", 3 0, L_0x1eb4940; 1 drivers -v0x1d6a1c0_0 .net "out", 0 0, L_0x1eb44f0; 1 drivers -L_0x1eb3d70 .part L_0x1eb4940, 0, 1; -L_0x1eb3ed0 .part L_0x1eb4940, 1, 1; -L_0x1eb4010 .concat8 [ 1 1 0 0], L_0x1eb3cb0, L_0x1eb4100; -L_0x1eb4210 .part L_0x1eb4940, 2, 1; -L_0x1eb4370 .part L_0x1eb4940, 3, 1; -L_0x1eb4560 .part L_0x1eb4010, 0, 1; -L_0x1eb4710 .part L_0x1eb4010, 1, 1; - .scope S_0x1a570b0; +L_0x1347550/d .functor AND 1, L_0x1347610, L_0x1347770, C4<1>, C4<1>; +L_0x1347550 .delay 1 (30000,30000,30000) L_0x1347550/d; +L_0x13479a0/d .functor AND 1, L_0x1347ab0, L_0x1347c10, C4<1>, C4<1>; +L_0x13479a0 .delay 1 (30000,30000,30000) L_0x13479a0/d; +L_0x1347d90/d .functor AND 1, L_0x1347e00, L_0x1347fb0, C4<1>, C4<1>; +L_0x1347d90 .delay 1 (30000,30000,30000) L_0x1347d90/d; +v0x11fcc90_0 .net *"_s0", 0 0, L_0x1347550; 1 drivers +v0x11fcd90_0 .net *"_s10", 0 0, L_0x1347ab0; 1 drivers +v0x11fce70_0 .net *"_s12", 0 0, L_0x1347c10; 1 drivers +v0x11fcf30_0 .net *"_s14", 0 0, L_0x1347e00; 1 drivers +v0x11fd010_0 .net *"_s16", 0 0, L_0x1347fb0; 1 drivers +v0x11fd140_0 .net *"_s3", 0 0, L_0x1347610; 1 drivers +v0x11fd220_0 .net *"_s5", 0 0, L_0x1347770; 1 drivers +v0x11fd300_0 .net *"_s6", 0 0, L_0x13479a0; 1 drivers +v0x11fd3e0_0 .net "ands", 1 0, L_0x13478b0; 1 drivers +v0x11fd550_0 .net "in", 3 0, L_0x13481e0; 1 drivers +v0x11fd630_0 .net "out", 0 0, L_0x1347d90; 1 drivers +L_0x1347610 .part L_0x13481e0, 0, 1; +L_0x1347770 .part L_0x13481e0, 1, 1; +L_0x13478b0 .concat8 [ 1 1 0 0], L_0x1347550, L_0x13479a0; +L_0x1347ab0 .part L_0x13481e0, 2, 1; +L_0x1347c10 .part L_0x13481e0, 3, 1; +L_0x1347e00 .part L_0x13478b0, 0, 1; +L_0x1347fb0 .part L_0x13478b0, 1, 1; + .scope S_0xf2fc10; T_0 ; - %wait E_0x1b385b0; - %load/vec4 v0x1d6d9c0_0; + %wait E_0xfc9f50; + %load/vec4 v0x1200fd0_0; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; @@ -17852,116 +17883,50 @@ T_0 ; %jmp T_0.8; T_0.0 ; %pushi/vec4 1, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.1 ; %pushi/vec4 2, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.2 ; %pushi/vec4 4, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.3 ; %pushi/vec4 8, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.4 ; %pushi/vec4 16, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.5 ; %pushi/vec4 32, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.6 ; %pushi/vec4 64, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.7 ; %pushi/vec4 128, 0, 8; - %store/vec4 v0x1d6daa0_0, 0, 8; + %store/vec4 v0x12010b0_0, 0, 8; %jmp T_0.8; T_0.8 ; %pop/vec4 1; %jmp T_0; .thread T_0, $push; - .scope S_0x17c4680; + .scope S_0xf510b0; T_1 ; - %pushi/vec4 2, 0, 3; - %store/vec4 v0x1d6e8a0_0, 0, 3; - %pushi/vec4 4294967292, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4294967292, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 19 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4294967293, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4294967292, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 22 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4294967292, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4294967293, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 25 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 28 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 31 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 34 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 37 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 40 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4294967293, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 43 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4294967293, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 46 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 4294967293, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 49 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; - %pushi/vec4 4294967292, 0, 32; - %store/vec4 v0x1d6e5c0_0, 0, 32; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x1d6e6d0_0, 0, 32; + %pushi/vec4 3, 0, 3; + %store/vec4 v0x1202000_0, 0, 3; + %pushi/vec4 4294967294, 0, 32; + %store/vec4 v0x1201d20_0, 0, 32; + %pushi/vec4 4294967295, 0, 32; + %store/vec4 v0x1201e30_0, 0, 32; %delay 1410065408, 2; - %vpi_call 2 52 "$display", "%d %d %d", v0x1d6e5c0_0, v0x1d6e6d0_0, v0x1d6ea10_0 {0 0 0}; + %vpi_call 2 19 "$display", "%d %d %d %b", v0x1201d20_0, v0x1201e30_0, v0x1202170_0, v0x12020d0_0 {0 0 0}; %end; .thread T_1; # The file index is used to find the file name in the following table. diff --git a/alu.t.v b/alu.t.v index 409c4b5..778e523 100644 --- a/alu.t.v +++ b/alu.t.v @@ -13,42 +13,9 @@ module testALU(); ALU dut(result, carryout, zero, overflow, a, b, command); initial begin - command = 3'd2; - a = -4; - b = -4; #10000000 - $display("%d %d %d", a, b, result); - a = -3; - b = -4; #10000000 - $display("%d %d %d", a, b, result); - a = -4; - b = -3; #10000000 - $display("%d %d %d", a, b, result); - a = 4; - b = 4; #10000000 - $display("%d %d %d", a, b, result); - a = 3; - b = 4; #10000000 - $display("%d %d %d", a, b, result); - a = 4; - b = 3; #10000000 - $display("%d %d %d", a, b, result); - a = 3; - b = 0; #10000000 - $display("%d %d %d", a, b, result); - a = 0; - b = 3; #10000000 - $display("%d %d %d", a, b, result); - a = -3; - b = 0; #10000000 - $display("%d %d %d", a, b, result); - a = 0; - b = -3; #10000000 - $display("%d %d %d", a, b, result); - a = 4; - b = -3; #10000000 - $display("%d %d %d", a, b, result); - a = -4; - b = 3; #10000000 - $display("%d %d %d", a, b, result); + command = 3'd3; + a = -2; + b = -1; #10000000 + $display("%d %d %d %b", a, b, result, overflow); end endmodule diff --git a/alu.v b/alu.v index eb4ec75..88e0bb6 100644 --- a/alu.v +++ b/alu.v @@ -16,7 +16,11 @@ input[2:0] command wire mixedSigns; wire sameSigns; wire possibleOverflow; + wire overFlowPossible; + wire overflowPre; + wire addOrSub; wire sltPre; + wire B31_; reg[7:0] commandslice; always @(command) begin @@ -59,11 +63,15 @@ input[2:0] command and32 zeroout(zero, zerobus); //calculate overflow `XOR overflowXor(possibleOverflow, result[31], carryout); - `XNOR overflowXnor(sameSigns, operandA[31], operandB[31]); - `AND overflowAnd(overflow, possibleOverflow, sameSigns); + `XNOR overflowXnorAdd(sameSigns, operandA[31], operandB[31]); + `NOT overflowNot(mixedSigns, sameSigns); + mux1 overflowMux(overFlowPossible, mixedSigns, sameSigns, commandslice[0]); + `OR addSubOr(addOrSub, commandslice[0], commandslice[1]); + `AND overflowAnd(overflowPre, possibleOverflow, overFlowPossible); + `AND overflowOut(overflow, overflowPre, addOrSub); //handle the slt stuff - `NOT sltNot(mixedSigns, sameSigns); - `AND sltOut(sltPre, carryinbus[32], commandslice[3]); - `XOR sltOut2(overrideBus[0], sltPre, mixedSigns); + `XOR sltOut(sltPre, carryout, mixedSigns); + `AND sltOut2(overrideBus[0], sltPre, commandslice[3]); + or32P resultOr(result, resultBus, overrideBus); endmodule diff --git a/alu1.v b/alu1.v index 05bfd9d..0b15701 100644 --- a/alu1.v +++ b/alu1.v @@ -119,6 +119,17 @@ module slt(output out, `OR or1(out, w0, lt); endmodule +module mux1(output out, input a, input b, input s); + wire s_; + wire w0; + wire w1; + + `NOT sNot(s_,s); + `AND aAnd(w0, a, s_); + `AND bAnd(w1, b, s); + `OR(out,w0,w1); +endmodule + `define ADDSig command[0] `define SUBSig command[1] `define XORSig command[2] From 2ffeca3a4fe80795a91fd39c87cec757925bdf8d Mon Sep 17 00:00:00 2001 From: TShapinsky Date: Fri, 13 Oct 2017 01:05:51 -0400 Subject: [PATCH 16/26] Update Writeup.md --- Writeup.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Writeup.md b/Writeup.md index f369dea..175d8cf 100644 --- a/Writeup.md +++ b/Writeup.md @@ -17,9 +17,10 @@ In the case of addition each the LSB of the carryin bus is left empty and the ca ## Test Results ### Test Choice ### Test Driven Development Catches Bugs +We waited until after writing the ALU to begin writing comprehensive test cases. After writing just two test cases we were able to find and fix two ### Discovered Tests ## Timing ## Work Plan Reflection -Writing the implementation happened fairly quickly in about the time we predicted, however the act of gathering information and creating visuals for the +Writing the implementation happened fairly quickly in about the time we predicted, however the act of gathering information and creating visuals for the final write up turned out to be more time intensive than we had planned From b2452d10a123b9e541ae6c57cee27a93d04c401b Mon Sep 17 00:00:00 2001 From: Henry Rachootin Date: Fri, 13 Oct 2017 01:06:30 -0400 Subject: [PATCH 17/26] for real --- alu.v | 7 ------- 1 file changed, 7 deletions(-) diff --git a/alu.v b/alu.v index 5d3c528..b6c4a99 100644 --- a/alu.v +++ b/alu.v @@ -19,13 +19,6 @@ input[2:0] command wire overflowPre; wire addOrSub; wire sltPre; -<<<<<<< HEAD - wire B31_; -======= - wire flagsEnable; - wire carryoutint, overflowint; - ->>>>>>> 01e44d4a2603a90d54d9733c1c5803503d771d61 reg[7:0] commandslice; always @(command) begin From e43e86c78cff90fe3903b8b703fa0ba47d8b9ac8 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Fri, 13 Oct 2017 01:10:49 -0400 Subject: [PATCH 18/26] added tests for all operations --- alu.t.v | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/alu.t.v b/alu.t.v index e23e6bd..99b244b 100644 --- a/alu.t.v +++ b/alu.t.v @@ -16,6 +16,7 @@ module testALU(); initial begin $dumpfile("alu.vcd"); $dumpvars(0, testALU); + //Addition tests command = 3'd0; a = -4; b = 4; #1000000 @@ -28,6 +29,7 @@ module testALU(); $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); end + //Subtraction tests command = 3'd1; a = 4; b = 4; #1000000 @@ -39,5 +41,93 @@ module testALU(); if (result != 31'h7fffffff || !overflow || zero) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); end + + //XOR tests + command = 3'd2; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != a^b) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != a^b) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + + //SLT tests + command = 3'd3; + a = -8; + b = -16; #1000000 + if (!result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 8; + b = 16; #1000000 + if (result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 8; + b = -16; #1000000 + if (!result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = -8; + b = 16; #1000000 + if (result) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + + //AND tests + command = 3'd4; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != a&b) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != a&b) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + + //AND tests + command = 3'd5; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != ~(a&b)) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != ~(a&b)) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + + //NOR tests + command = 3'd6; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != ~(a|b)) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != ~(a|b)) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + + //OR tests + command = 3'd7; + a = 4'b1001; + b = 4'b1010; #1000000 + if (result != (a|b)) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end + a = 4'b0000; + b = 4'b1111; #1000000 + if (result != (a|b)) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + end end endmodule From c5c08335585ecd1347ca2ac17acc0cbf705d0b65 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Fri, 13 Oct 2017 01:24:54 -0400 Subject: [PATCH 19/26] added binary display to test cases --- alu.t.v | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/alu.t.v b/alu.t.v index 99b244b..ca4a7bc 100644 --- a/alu.t.v +++ b/alu.t.v @@ -21,12 +21,12 @@ module testALU(); a = -4; b = 4; #1000000 if (result != 0 || overflow || !zero) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); end a = 31'h7fffffff; b = 1; #1000000 if (result != 31'h80000000 || !overflow || zero) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 31'h8000000); end //Subtraction tests @@ -34,12 +34,12 @@ module testALU(); a = 4; b = 4; #1000000 if (result != 0 || overflow || !zero) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); end a = 31'h80000000; b = 1; #1000000 if (result != 31'h7fffffff || !overflow || zero) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 31'h7fffffff); end //XOR tests @@ -47,12 +47,12 @@ module testALU(); a = 4'b1001; b = 4'b1010; #1000000 if (result != a^b) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, a^b); end a = 4'b0000; b = 4'b1111; #1000000 if (result != a^b) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, a^b); end //SLT tests @@ -60,22 +60,22 @@ module testALU(); a = -8; b = -16; #1000000 if (!result) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); end a = 8; b = 16; #1000000 if (result) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 1); end a = 8; b = -16; #1000000 if (!result) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 0); end a = -8; b = 16; #1000000 if (result) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 1); end //AND tests @@ -83,12 +83,12 @@ module testALU(); a = 4'b1001; b = 4'b1010; #1000000 if (result != a&b) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a&b); end a = 4'b0000; b = 4'b1111; #1000000 if (result != a&b) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a&b); end //AND tests @@ -96,12 +96,12 @@ module testALU(); a = 4'b1001; b = 4'b1010; #1000000 if (result != ~(a&b)) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a&b)); end a = 4'b0000; b = 4'b1111; #1000000 if (result != ~(a&b)) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a&b)); end //NOR tests @@ -109,12 +109,12 @@ module testALU(); a = 4'b1001; b = 4'b1010; #1000000 if (result != ~(a|b)) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a|b)); end a = 4'b0000; b = 4'b1111; #1000000 if (result != ~(a|b)) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a|b)); end //OR tests @@ -122,12 +122,12 @@ module testALU(); a = 4'b1001; b = 4'b1010; #1000000 if (result != (a|b)) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, (a|b)); end a = 4'b0000; b = 4'b1111; #1000000 if (result != (a|b)) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d", a, b, result, command, overflow, zero, carryout); + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, (a|b)); end end endmodule From b7695f069453f5780c5e613ec971d8ab19550def Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Fri, 13 Oct 2017 01:39:30 -0400 Subject: [PATCH 20/26] fixed ooo --- alu.t.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/alu.t.v b/alu.t.v index ca4a7bc..8efc58a 100644 --- a/alu.t.v +++ b/alu.t.v @@ -25,8 +25,8 @@ module testALU(); end a = 31'h7fffffff; b = 1; #1000000 - if (result != 31'h80000000 || !overflow || zero) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 31'h8000000); + if (result != -2147483648 || !overflow || zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, -2147483648); end //Subtraction tests @@ -38,21 +38,21 @@ module testALU(); end a = 31'h80000000; b = 1; #1000000 - if (result != 31'h7fffffff || !overflow || zero) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 31'h7fffffff); + if (result != -1 || !overflow || zero) begin + $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, -1); end //XOR tests command = 3'd2; a = 4'b1001; b = 4'b1010; #1000000 - if (result != a^b) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, a^b); + if (result != (a^b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a^b); end a = 4'b0000; b = 4'b1111; #1000000 - if (result != a^b) begin - $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, a^b); + if (result != (a^b)) begin + $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a^b); end //SLT tests From e31c893b71cb6e7f2058030c95bbbc7534143b18 Mon Sep 17 00:00:00 2001 From: Henry Rachootin Date: Fri, 13 Oct 2017 01:40:14 -0400 Subject: [PATCH 21/26] stuff --- alu | 31698 +++++++++++++++-------------- alu.t.v | 18 +- alu.v | 30 +- alu.vcd | 58895 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ alu1.v | 7 +- 5 files changed, 75420 insertions(+), 15228 deletions(-) create mode 100644 alu.vcd diff --git a/alu b/alu index 6b00501..5815feb 100755 --- a/alu +++ b/alu @@ -6,16 +6,16 @@ :vpi_module "vhdl_sys"; :vpi_module "v2005_math"; :vpi_module "va_math"; -S_0xf510b0 .scope module, "testALU" "testALU" 2 4; +S_0x26fb580 .scope module, "testALU" "testALU" 2 4; .timescale -9 -12; -v0x1201d20_0 .var/s "a", 31 0; -v0x1201e30_0 .var/s "b", 31 0; -v0x1201f00_0 .net "carryout", 0 0, L_0x133ff10; 1 drivers -v0x1202000_0 .var "command", 2 0; -v0x12020d0_0 .net "overflow", 0 0, L_0x1349900; 1 drivers -v0x1202170_0 .net/s "result", 31 0, L_0x134e4a0; 1 drivers -v0x1202260_0 .net "zero", 0 0, L_0x1348e30; 1 drivers -S_0xf2fc10 .scope module, "dut" "ALU" 2 13, 3 2 0, S_0xf510b0; +v0x2cddf50_0 .var/s "a", 31 0; +v0x2cde060_0 .var/s "b", 31 0; +v0x2cde130_0 .net "carryout", 0 0, L_0x2e34f10; 1 drivers +v0x2cde230_0 .var "command", 2 0; +v0x2cde300_0 .net "overflow", 0 0, L_0x2e3e7a0; 1 drivers +v0x2cde3a0_0 .net/s "result", 31 0, L_0x2e43190; 1 drivers +v0x2cde490_0 .net "zero", 0 0, L_0x2e3db90; 1 drivers +S_0x26b20c0 .scope module, "dut" "ALU" 2 14, 3 2 0, S_0x26fb580; .timescale -9 -12; .port_info 0 /OUTPUT 32 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -24,246 +24,248 @@ S_0xf2fc10 .scope module, "dut" "ALU" 2 13, 3 2 0, S_0xf510b0; .port_info 4 /INPUT 32 "operandA" .port_info 5 /INPUT 32 "operandB" .port_info 6 /INPUT 3 "command" -L_0x133ec80/d .functor OR 1, L_0x1341030, L_0x133fe70, C4<0>, C4<0>; -L_0x133ec80 .delay 1 (30000,30000,30000) L_0x133ec80/d; -L_0x133ff10/d .functor OR 1, L_0x133ff80, L_0x1340020, C4<0>, C4<0>; -L_0x133ff10 .delay 1 (30000,30000,30000) L_0x133ff10/d; -L_0x1349140/d .functor XOR 1, L_0x1349200, L_0x133ff10, C4<0>, C4<0>; -L_0x1349140 .delay 1 (30000,30000,30000) L_0x1349140/d; -L_0x13410d0/d .functor XNOR 1, L_0x1341340, L_0x1341230, C4<0>, C4<0>; -L_0x13410d0 .delay 1 (20000,20000,20000) L_0x13410d0/d; -L_0x1349360/d .functor NOT 1, L_0x13410d0, C4<0>, C4<0>, C4<0>; -L_0x1349360 .delay 1 (10000,10000,10000) L_0x1349360/d; -L_0x1349f00/d .functor OR 1, L_0x134a010, L_0x1349700, C4<0>, C4<0>; -L_0x1349f00 .delay 1 (30000,30000,30000) L_0x1349f00/d; -L_0x13497f0/d .functor AND 1, L_0x1349140, L_0x1349c60, C4<1>, C4<1>; -L_0x13497f0 .delay 1 (30000,30000,30000) L_0x13497f0/d; -L_0x1349900/d .functor AND 1, L_0x13497f0, L_0x1349f00, C4<1>, C4<1>; -L_0x1349900 .delay 1 (30000,30000,30000) L_0x1349900/d; -L_0x134a5d0/d .functor XOR 1, L_0x133ff10, L_0x1349360, C4<0>, C4<0>; -L_0x134a5d0 .delay 1 (30000,30000,30000) L_0x134a5d0/d; -L_0x134a170/d .functor AND 1, L_0x134a5d0, L_0x134a2d0, C4<1>, C4<1>; -L_0x134a170 .delay 1 (30000,30000,30000) L_0x134a170/d; -v0x11fe570_0 .net *"_s106", 0 0, L_0x1265030; 1 drivers -v0x11fe650_0 .net *"_s117", 0 0, L_0x126ec80; 1 drivers -v0x11fe730_0 .net *"_s128", 0 0, L_0x12788b0; 1 drivers -v0x11fe7f0_0 .net *"_s139", 0 0, L_0x12824c0; 1 drivers -v0x11fe8d0_0 .net *"_s150", 0 0, L_0x128c0d0; 1 drivers -v0x11fea00_0 .net *"_s161", 0 0, L_0x1295c20; 1 drivers -v0x11feae0_0 .net *"_s172", 0 0, L_0x129faf0; 1 drivers -v0x11febc0_0 .net *"_s18", 0 0, L_0x1215c80; 1 drivers -v0x11feca0_0 .net *"_s183", 0 0, L_0x12a9870; 1 drivers -v0x11fee10_0 .net *"_s194", 0 0, L_0x12b36d0; 1 drivers -v0x11feef0_0 .net *"_s205", 0 0, L_0x12bd3b0; 1 drivers -v0x11fefd0_0 .net *"_s216", 0 0, L_0x12c6fb0; 1 drivers -v0x11ff0b0_0 .net *"_s227", 0 0, L_0x12d0c90; 1 drivers -v0x11ff190_0 .net *"_s238", 0 0, L_0x123cc10; 1 drivers -v0x11ff270_0 .net *"_s249", 0 0, L_0x12e65b0; 1 drivers -v0x11ff350_0 .net *"_s260", 0 0, L_0x12f01d0; 1 drivers -v0x11ff430_0 .net *"_s271", 0 0, L_0x12f9e00; 1 drivers -v0x11ff5e0_0 .net *"_s282", 0 0, L_0x1303a60; 1 drivers -v0x11ff680_0 .net *"_s29", 0 0, L_0x121f720; 1 drivers -v0x11ff760_0 .net *"_s293", 0 0, L_0x130d6b0; 1 drivers -v0x11ff840_0 .net *"_s304", 0 0, L_0x1317200; 1 drivers -v0x11ff920_0 .net *"_s315", 0 0, L_0x1320f40; 1 drivers -v0x11ffa00_0 .net *"_s326", 0 0, L_0x132ac10; 1 drivers -v0x11ffae0_0 .net *"_s337", 0 0, L_0x1334840; 1 drivers -v0x11ffbc0_0 .net *"_s350", 0 0, L_0x1338910; 1 drivers -v0x11ffca0_0 .net *"_s352", 0 0, L_0x133ec80; 1 drivers -v0x11ffd80_0 .net *"_s356", 0 0, L_0x1341030; 1 drivers -v0x11ffe60_0 .net *"_s358", 0 0, L_0x133fe70; 1 drivers -v0x11fff40_0 .net *"_s360", 0 0, L_0x133ff80; 1 drivers -v0x1200020_0 .net *"_s362", 0 0, L_0x1340020; 1 drivers -v0x1200100_0 .net *"_s364", 0 0, L_0x1349200; 1 drivers -v0x12001e0_0 .net *"_s366", 0 0, L_0x1341340; 1 drivers -v0x12002c0_0 .net *"_s368", 0 0, L_0x1341230; 1 drivers -v0x11ff510_0 .net *"_s372", 0 0, L_0x134a010; 1 drivers -v0x1200590_0 .net *"_s374", 0 0, L_0x1349700; 1 drivers -v0x1200670_0 .net *"_s375", 0 0, L_0x134a170; 1 drivers -v0x1200750_0 .net *"_s379", 0 0, L_0x134a2d0; 1 drivers -v0x1200830_0 .net *"_s40", 0 0, L_0x1229660; 1 drivers -v0x1200910_0 .net *"_s51", 0 0, L_0x12293d0; 1 drivers -v0x12009f0_0 .net *"_s62", 0 0, L_0x123dbe0; 1 drivers -v0x1200ad0_0 .net *"_s73", 0 0, L_0x12478d0; 1 drivers -v0x1200bb0_0 .net *"_s84", 0 0, L_0x1251650; 1 drivers -v0x1200c90_0 .net *"_s95", 0 0, L_0x125b320; 1 drivers -v0x1200d70_0 .net "addOrSub", 0 0, L_0x1349f00; 1 drivers -v0x1200e30_0 .net "carryinbus", 32 0, L_0x133ebe0; 1 drivers -v0x1200f10_0 .net "carryout", 0 0, L_0x133ff10; alias, 1 drivers -v0x1200fd0_0 .net "command", 2 0, v0x1202000_0; 1 drivers -v0x12010b0_0 .var "commandslice", 7 0; -v0x1201170_0 .net "mixedSigns", 0 0, L_0x1349360; 1 drivers -v0x1201210_0 .net "operandA", 31 0, v0x1201d20_0; 1 drivers -v0x12012d0_0 .net "operandB", 31 0, v0x1201e30_0; 1 drivers -v0x12013b0_0 .net "overFlowPossible", 0 0, L_0x1349c60; 1 drivers -v0x1201480_0 .net "overflow", 0 0, L_0x1349900; alias, 1 drivers -v0x1201520_0 .net "overflowPre", 0 0, L_0x13497f0; 1 drivers -v0x12015e0_0 .net "overrideBus", 31 0, L_0x134a800; 1 drivers -v0x12016d0_0 .net "possibleOverflow", 0 0, L_0x1349140; 1 drivers -v0x1201770_0 .net "result", 31 0, L_0x134e4a0; alias, 1 drivers -v0x1201860_0 .net "resultBus", 31 0, L_0x133e830; 1 drivers -v0x1201930_0 .net "sameSigns", 0 0, L_0x13410d0; 1 drivers -v0x1201a00_0 .net "sltPre", 0 0, L_0x134a5d0; 1 drivers -v0x1201aa0_0 .net "zero", 0 0, L_0x1348e30; alias, 1 drivers -v0x1201b70_0 .net "zerobus", 31 0, L_0x1295d80; 1 drivers -E_0xfc9f50 .event edge, v0x1200fd0_0; -L_0x120bed0 .part v0x1201d20_0, 0, 1; -L_0x120c030 .part v0x1201e30_0, 0, 1; -L_0x120c120 .part L_0x133ebe0, 0, 1; -L_0x12159e0 .part v0x1201d20_0, 1, 1; -L_0x1215b40 .part v0x1201e30_0, 1, 1; -L_0x1215be0 .part L_0x133ebe0, 1, 1; -L_0x121f680 .part v0x1201d20_0, 2, 1; -L_0x121f870 .part v0x1201e30_0, 2, 1; -L_0x121f9a0 .part L_0x133ebe0, 2, 1; -L_0x1229330 .part v0x1201d20_0, 3, 1; -L_0x1229490 .part v0x1201e30_0, 3, 1; -L_0x1229530 .part L_0x133ebe0, 3, 1; -L_0x1232f10 .part v0x1201d20_0, 4, 1; -L_0x1233070 .part v0x1201e30_0, 4, 1; -L_0x1233110 .part L_0x133ebe0, 4, 1; -L_0x123db40 .part v0x1201d20_0, 5, 1; -L_0x123dd30 .part v0x1201e30_0, 5, 1; -L_0x123ddd0 .part L_0x133ebe0, 5, 1; -L_0x1247830 .part v0x1201d20_0, 6, 1; -L_0x1247aa0 .part v0x1201e30_0, 6, 1; -L_0x123de70 .part L_0x133ebe0, 6, 1; -L_0x12515b0 .part v0x1201d20_0, 7, 1; -L_0x1247c50 .part v0x1201e30_0, 7, 1; -L_0x12517d0 .part L_0x133ebe0, 7, 1; -L_0x125b280 .part v0x1201d20_0, 8, 1; -L_0x125b3e0 .part v0x1201e30_0, 8, 1; -L_0x1251980 .part L_0x133ebe0, 8, 1; -L_0x1264f90 .part v0x1201d20_0, 9, 1; -L_0x125b480 .part v0x1201e30_0, 9, 1; -L_0x12651e0 .part L_0x133ebe0, 9, 1; -L_0x126ebe0 .part v0x1201d20_0, 10, 1; -L_0x126ed40 .part v0x1201e30_0, 10, 1; -L_0x1265280 .part L_0x133ebe0, 10, 1; -L_0x1278810 .part v0x1201d20_0, 11, 1; -L_0x126ede0 .part v0x1201e30_0, 11, 1; -L_0x1278a90 .part L_0x133ebe0, 11, 1; -L_0x1282420 .part v0x1201d20_0, 12, 1; -L_0x1282580 .part v0x1201e30_0, 12, 1; -L_0x1278b30 .part L_0x133ebe0, 12, 1; -L_0x128c030 .part v0x1201d20_0, 13, 1; -L_0x1282620 .part v0x1201e30_0, 13, 1; -L_0x12826c0 .part L_0x133ebe0, 13, 1; -L_0x1295b80 .part v0x1201d20_0, 14, 1; -L_0x1247990 .part v0x1201e30_0, 14, 1; -L_0x1247b40 .part L_0x133ebe0, 14, 1; -L_0x129fa50 .part v0x1201d20_0, 15, 1; -L_0x1296100 .part v0x1201e30_0, 15, 1; -L_0x12961a0 .part L_0x133ebe0, 15, 1; -L_0x12a97d0 .part v0x1201d20_0, 16, 1; -L_0x12a9930 .part v0x1201e30_0, 16, 1; -L_0x129ff40 .part L_0x133ebe0, 16, 1; -L_0x12b3630 .part v0x1201d20_0, 17, 1; -L_0x12a99d0 .part v0x1201e30_0, 17, 1; -L_0x12a9a70 .part L_0x133ebe0, 17, 1; -L_0x12bd310 .part v0x1201d20_0, 18, 1; -L_0x12bd470 .part v0x1201e30_0, 18, 1; -L_0x12b3790 .part L_0x133ebe0, 18, 1; -L_0x12c6f10 .part v0x1201d20_0, 19, 1; -L_0x12bd510 .part v0x1201e30_0, 19, 1; -L_0x12bd5b0 .part L_0x133ebe0, 19, 1; -L_0x12d0bf0 .part v0x1201d20_0, 20, 1; -L_0x12d0d50 .part v0x1201e30_0, 20, 1; -L_0x12c7070 .part L_0x133ebe0, 20, 1; -L_0x123cb70 .part v0x1201d20_0, 21, 1; -L_0x123ccd0 .part v0x1201e30_0, 21, 1; -L_0x123cd70 .part L_0x133ebe0, 21, 1; -L_0x12e6510 .part v0x1201d20_0, 22, 1; -L_0x12e6670 .part v0x1201e30_0, 22, 1; -L_0x12dca20 .part L_0x133ebe0, 22, 1; -L_0x12f0130 .part v0x1201d20_0, 23, 1; -L_0x12e6710 .part v0x1201e30_0, 23, 1; -L_0x12e67b0 .part L_0x133ebe0, 23, 1; -L_0x12f9d60 .part v0x1201d20_0, 24, 1; -L_0x12f9ec0 .part v0x1201e30_0, 24, 1; -L_0x12f0290 .part L_0x133ebe0, 24, 1; -L_0x13039c0 .part v0x1201d20_0, 25, 1; -L_0x12f9f60 .part v0x1201e30_0, 25, 1; -L_0x12fa000 .part L_0x133ebe0, 25, 1; -L_0x130d610 .part v0x1201d20_0, 26, 1; -L_0x130d770 .part v0x1201e30_0, 26, 1; -L_0x1303b20 .part L_0x133ebe0, 26, 1; -L_0x1317160 .part v0x1201d20_0, 27, 1; -L_0x130d810 .part v0x1201e30_0, 27, 1; -L_0x130d8b0 .part L_0x133ebe0, 27, 1; -L_0x1320ea0 .part v0x1201d20_0, 28, 1; -L_0x1321000 .part v0x1201e30_0, 28, 1; -L_0x13172c0 .part L_0x133ebe0, 28, 1; -L_0x132ab70 .part v0x1201d20_0, 29, 1; -L_0x13210a0 .part v0x1201e30_0, 29, 1; -L_0x1321140 .part L_0x133ebe0, 29, 1; -L_0x13347a0 .part v0x1201d20_0, 30, 1; -L_0x1295ce0 .part v0x1201e30_0, 30, 1; -L_0x132acd0 .part L_0x133ebe0, 30, 1; -LS_0x133e830_0_0 .concat8 [ 1 1 1 1], L_0x1208030, L_0x1211a70, L_0x121b7e0, L_0x1225490; -LS_0x133e830_0_4 .concat8 [ 1 1 1 1], L_0x122f0e0, L_0x1238d60, L_0x1243990, L_0x124d710; -LS_0x133e830_0_8 .concat8 [ 1 1 1 1], L_0x12573e0, L_0x12610f0, L_0x126ad40, L_0x1274890; -LS_0x133e830_0_12 .concat8 [ 1 1 1 1], L_0x127e580, L_0x1288190, L_0x1291da0, L_0x129bbb0; -LS_0x133e830_0_16 .concat8 [ 1 1 1 1], L_0x12a5900, L_0x12af760, L_0x12b93e0, L_0x12c3070; -LS_0x133e830_0_20 .concat8 [ 1 1 1 1], L_0x12cccc0, L_0x12d6850, L_0x12e25b0, L_0x12ec290; -LS_0x133e830_0_24 .concat8 [ 1 1 1 1], L_0x12f5ea0, L_0x12ffa90, L_0x13096e0, L_0x13133a0; -LS_0x133e830_0_28 .concat8 [ 1 1 1 1], L_0x131cf70, L_0x1326c10, L_0x1330900, L_0x133a990; -LS_0x133e830_1_0 .concat8 [ 4 4 4 4], LS_0x133e830_0_0, LS_0x133e830_0_4, LS_0x133e830_0_8, LS_0x133e830_0_12; -LS_0x133e830_1_4 .concat8 [ 4 4 4 4], LS_0x133e830_0_16, LS_0x133e830_0_20, LS_0x133e830_0_24, LS_0x133e830_0_28; -L_0x133e830 .concat8 [ 16 16 0 0], LS_0x133e830_1_0, LS_0x133e830_1_4; -LS_0x1295d80_0_0 .concat8 [ 1 1 1 1], L_0x120bdd0, L_0x12158e0, L_0x121f580, L_0x1229230; -LS_0x1295d80_0_4 .concat8 [ 1 1 1 1], L_0x1232e10, L_0x123da40, L_0x1247730, L_0x12514b0; -LS_0x1295d80_0_8 .concat8 [ 1 1 1 1], L_0x125b180, L_0x1264e90, L_0x126eae0, L_0x1278710; -LS_0x1295d80_0_12 .concat8 [ 1 1 1 1], L_0x1282320, L_0x128bf30, L_0x1295a80, L_0x129f950; -LS_0x1295d80_0_16 .concat8 [ 1 1 1 1], L_0x12a96d0, L_0x12b3530, L_0x12bd210, L_0x12c6e10; -LS_0x1295d80_0_20 .concat8 [ 1 1 1 1], L_0x12d0af0, L_0x123ca70, L_0x12e6410, L_0x12f0030; -LS_0x1295d80_0_24 .concat8 [ 1 1 1 1], L_0x12f9c60, L_0x13038c0, L_0x130d510, L_0x1317060; -LS_0x1295d80_0_28 .concat8 [ 1 1 1 1], L_0x1320da0, L_0x132aa70, L_0x13346a0, L_0x133e730; -LS_0x1295d80_1_0 .concat8 [ 4 4 4 4], LS_0x1295d80_0_0, LS_0x1295d80_0_4, LS_0x1295d80_0_8, LS_0x1295d80_0_12; -LS_0x1295d80_1_4 .concat8 [ 4 4 4 4], LS_0x1295d80_0_16, LS_0x1295d80_0_20, LS_0x1295d80_0_24, LS_0x1295d80_0_28; -L_0x1295d80 .concat8 [ 16 16 0 0], LS_0x1295d80_1_0, LS_0x1295d80_1_4; -L_0x133f6b0 .part v0x1201d20_0, 31, 1; -L_0x133eaa0 .part v0x1201e30_0, 31, 1; -L_0x133eb40 .part L_0x133ebe0, 31, 1; -LS_0x133ebe0_0_0 .concat8 [ 1 1 1 1], L_0x133ec80, L_0x120ba70, L_0x1215580, L_0x121f220; -LS_0x133ebe0_0_4 .concat8 [ 1 1 1 1], L_0x1228ed0, L_0x1232ab0, L_0x123d6e0, L_0x12473d0; -LS_0x133ebe0_0_8 .concat8 [ 1 1 1 1], L_0x1251150, L_0x125ae20, L_0x1264b30, L_0x126e780; -LS_0x133ebe0_0_12 .concat8 [ 1 1 1 1], L_0x12783b0, L_0x1281fc0, L_0x128bbd0, L_0x1295720; -LS_0x133ebe0_0_16 .concat8 [ 1 1 1 1], L_0x129f5f0, L_0x12a9370, L_0x12b31d0, L_0x12bceb0; -LS_0x133ebe0_0_20 .concat8 [ 1 1 1 1], L_0x12c6ab0, L_0x12d0790, L_0x123c710, L_0x12e60b0; -LS_0x133ebe0_0_24 .concat8 [ 1 1 1 1], L_0x12efcd0, L_0x12f9900, L_0x1303560, L_0x130d1b0; -LS_0x133ebe0_0_28 .concat8 [ 1 1 1 1], L_0x1316d00, L_0x1320a40, L_0x132a710, L_0x1334340; -LS_0x133ebe0_0_32 .concat8 [ 1 0 0 0], L_0x133e3d0; -LS_0x133ebe0_1_0 .concat8 [ 4 4 4 4], LS_0x133ebe0_0_0, LS_0x133ebe0_0_4, LS_0x133ebe0_0_8, LS_0x133ebe0_0_12; -LS_0x133ebe0_1_4 .concat8 [ 4 4 4 4], LS_0x133ebe0_0_16, LS_0x133ebe0_0_20, LS_0x133ebe0_0_24, LS_0x133ebe0_0_28; -LS_0x133ebe0_1_8 .concat8 [ 1 0 0 0], LS_0x133ebe0_0_32; -L_0x133ebe0 .concat8 [ 16 16 1 0], LS_0x133ebe0_1_0, LS_0x133ebe0_1_4, LS_0x133ebe0_1_8; -L_0x1341030 .part v0x12010b0_0, 1, 1; -L_0x133fe70 .part v0x12010b0_0, 1, 1; -L_0x133ff80 .part L_0x133ebe0, 32, 1; -L_0x1340020 .part L_0x133ebe0, 32, 1; -L_0x1349200 .part L_0x134e4a0, 31, 1; -L_0x1341340 .part v0x1201d20_0, 31, 1; -L_0x1341230 .part v0x1201e30_0, 31, 1; -L_0x1349e60 .part v0x12010b0_0, 0, 1; -L_0x134a010 .part v0x12010b0_0, 0, 1; -L_0x1349700 .part v0x12010b0_0, 1, 1; -LS_0x134a800_0_0 .concat8 [ 1 1 1 1], L_0x134a170, L_0x1215c80, L_0x121f720, L_0x1229660; -LS_0x134a800_0_4 .concat8 [ 1 1 1 1], L_0x12293d0, L_0x123dbe0, L_0x12478d0, L_0x1251650; -LS_0x134a800_0_8 .concat8 [ 1 1 1 1], L_0x125b320, L_0x1265030, L_0x126ec80, L_0x12788b0; -LS_0x134a800_0_12 .concat8 [ 1 1 1 1], L_0x12824c0, L_0x128c0d0, L_0x1295c20, L_0x129faf0; -LS_0x134a800_0_16 .concat8 [ 1 1 1 1], L_0x12a9870, L_0x12b36d0, L_0x12bd3b0, L_0x12c6fb0; -LS_0x134a800_0_20 .concat8 [ 1 1 1 1], L_0x12d0c90, L_0x123cc10, L_0x12e65b0, L_0x12f01d0; -LS_0x134a800_0_24 .concat8 [ 1 1 1 1], L_0x12f9e00, L_0x1303a60, L_0x130d6b0, L_0x1317200; -LS_0x134a800_0_28 .concat8 [ 1 1 1 1], L_0x1320f40, L_0x132ac10, L_0x1334840, L_0x1338910; -LS_0x134a800_1_0 .concat8 [ 4 4 4 4], LS_0x134a800_0_0, LS_0x134a800_0_4, LS_0x134a800_0_8, LS_0x134a800_0_12; -LS_0x134a800_1_4 .concat8 [ 4 4 4 4], LS_0x134a800_0_16, LS_0x134a800_0_20, LS_0x134a800_0_24, LS_0x134a800_0_28; -L_0x134a800 .concat8 [ 16 16 0 0], LS_0x134a800_1_0, LS_0x134a800_1_4; -L_0x134a2d0 .part v0x12010b0_0, 3, 1; -S_0xf0e870 .scope generate, "alu_slices[0]" "alu_slices[0]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0xfcf020 .param/l "i" 0 3 41, +C4<00>; -S_0xeed4d0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xf0e870; +L_0x2e33c80/d .functor OR 1, L_0x2e36030, L_0x2e34e70, C4<0>, C4<0>; +L_0x2e33c80 .delay 1 (30000,30000,30000) L_0x2e33c80/d; +L_0x2e34f10/d .functor OR 1, L_0x2e34f80, L_0x2e35020, C4<0>, C4<0>; +L_0x2e34f10 .delay 1 (30000,30000,30000) L_0x2e34f10/d; +L_0x2e3dea0/d .functor XNOR 1, L_0x2e3dfb0, L_0x2e360d0, C4<0>, C4<0>; +L_0x2e3dea0 .delay 1 (20000,20000,20000) L_0x2e3dea0/d; +L_0x2e361c0/d .functor NOT 1, L_0x2e3dea0, C4<0>, C4<0>, C4<0>; +L_0x2e361c0 .delay 1 (10000,10000,10000) L_0x2e361c0/d; +L_0x2e362d0/d .functor XOR 1, L_0x2e3e4b0, L_0x2e34f10, C4<0>, C4<0>; +L_0x2e362d0 .delay 1 (30000,30000,30000) L_0x2e362d0/d; +L_0x2e3ec40/d .functor OR 1, L_0x2e3ed50, L_0x2e3e5a0, C4<0>, C4<0>; +L_0x2e3ec40 .delay 1 (30000,30000,30000) L_0x2e3ec40/d; +L_0x2e3e690/d .functor AND 1, L_0x2e362d0, L_0x2e3e9a0, C4<1>, C4<1>; +L_0x2e3e690 .delay 1 (30000,30000,30000) L_0x2e3e690/d; +o0x2ac6110a81d8 .functor BUFZ 1, C4; HiZ drive +L_0x2e3e7a0/d .functor AND 1, L_0x2e3e690, o0x2ac6110a81d8, C4<1>, C4<1>; +L_0x2e3e7a0 .delay 1 (30000,30000,30000) L_0x2e3e7a0/d; +L_0x2e3f2c0/d .functor XOR 1, L_0x2e34f10, L_0x2e361c0, C4<0>, C4<0>; +L_0x2e3f2c0 .delay 1 (30000,30000,30000) L_0x2e3f2c0/d; +L_0x2e3eeb0/d .functor AND 1, L_0x2e3f2c0, L_0x2e3f010, C4<1>, C4<1>; +L_0x2e3eeb0 .delay 1 (30000,30000,30000) L_0x2e3eeb0/d; +v0x2cda6e0_0 .net *"_s106", 0 0, L_0x2d41600; 1 drivers +v0x2cda7c0_0 .net *"_s117", 0 0, L_0x2d49b90; 1 drivers +v0x2cda8a0_0 .net *"_s128", 0 0, L_0x2d54360; 1 drivers +v0x2cda960_0 .net *"_s139", 0 0, L_0x2d60ef0; 1 drivers +v0x2cdaa40_0 .net *"_s150", 0 0, L_0x2d69470; 1 drivers +v0x2cdab70_0 .net *"_s161", 0 0, L_0x2d73c90; 1 drivers +v0x2cdac50_0 .net *"_s172", 0 0, L_0x2d80a20; 1 drivers +v0x2cdad30_0 .net *"_s18", 0 0, L_0x2ce9560; 1 drivers +v0x2cdae10_0 .net *"_s183", 0 0, L_0x2d8b3c0; 1 drivers +v0x2cdaf80_0 .net *"_s194", 0 0, L_0x2d938b0; 1 drivers +v0x2cdb060_0 .net *"_s205", 0 0, L_0x2d40dd0; 1 drivers +v0x2cdb140_0 .net *"_s216", 0 0, L_0x2dab520; 1 drivers +v0x2cdb220_0 .net *"_s227", 0 0, L_0x2db3a60; 1 drivers +v0x2cdb300_0 .net *"_s238", 0 0, L_0x2dc05c0; 1 drivers +v0x2cdb3e0_0 .net *"_s249", 0 0, L_0x2dcaac0; 1 drivers +v0x2cdb4c0_0 .net *"_s260", 0 0, L_0x2dd5340; 1 drivers +v0x2cdb5a0_0 .net *"_s271", 0 0, L_0x2de1ea0; 1 drivers +v0x2cdb750_0 .net *"_s282", 0 0, L_0x2dec6d0; 1 drivers +v0x2cdb7f0_0 .net *"_s29", 0 0, L_0x2ceaec0; 1 drivers +v0x2cdb8d0_0 .net *"_s293", 0 0, L_0x2df4b80; 1 drivers +v0x2cdb9b0_0 .net *"_s304", 0 0, L_0x2e01700; 1 drivers +v0x2cdba90_0 .net *"_s315", 0 0, L_0x2e0bf50; 1 drivers +v0x2cdbb70_0 .net *"_s326", 0 0, L_0x2e14410; 1 drivers +v0x2cdbc50_0 .net *"_s337", 0 0, L_0x2e28c40; 1 drivers +v0x2cdbd30_0 .net *"_s350", 0 0, L_0x2e298c0; 1 drivers +v0x2cdbe10_0 .net *"_s352", 0 0, L_0x2e33c80; 1 drivers +v0x2cdbef0_0 .net *"_s356", 0 0, L_0x2e36030; 1 drivers +v0x2cdbfd0_0 .net *"_s358", 0 0, L_0x2e34e70; 1 drivers +v0x2cdc0b0_0 .net *"_s360", 0 0, L_0x2e34f80; 1 drivers +v0x2cdc190_0 .net *"_s362", 0 0, L_0x2e35020; 1 drivers +v0x2cdc270_0 .net *"_s364", 0 0, L_0x2e3dfb0; 1 drivers +v0x2cdc350_0 .net *"_s366", 0 0, L_0x2e360d0; 1 drivers +v0x2cdc430_0 .net *"_s368", 0 0, L_0x2e3e4b0; 1 drivers +v0x2cdb680_0 .net *"_s372", 0 0, L_0x2e3ed50; 1 drivers +v0x2cdc700_0 .net *"_s374", 0 0, L_0x2e3e5a0; 1 drivers +v0x2cdc7e0_0 .net *"_s375", 0 0, L_0x2e3eeb0; 1 drivers +v0x2cdc8c0_0 .net *"_s379", 0 0, L_0x2e3f010; 1 drivers +v0x2cdc9a0_0 .net *"_s40", 0 0, L_0x2d08880; 1 drivers +v0x2cdca80_0 .net *"_s51", 0 0, L_0x2d00c00; 1 drivers +v0x2cdcb60_0 .net *"_s62", 0 0, L_0x2d13a80; 1 drivers +v0x2cdcc40_0 .net *"_s73", 0 0, L_0x2d1f3a0; 1 drivers +v0x2cdcd20_0 .net *"_s84", 0 0, L_0x2d29d50; 1 drivers +v0x2cdce00_0 .net *"_s95", 0 0, L_0x2d345f0; 1 drivers +v0x2cdcee0_0 .net "adOrSub", 0 0, o0x2ac6110a81d8; 0 drivers +v0x2cdcfa0_0 .net "addOrSub", 0 0, L_0x2e3ec40; 1 drivers +v0x2cdd060_0 .net "carryinbus", 32 0, L_0x2e33be0; 1 drivers +v0x2cdd140_0 .net "carryout", 0 0, L_0x2e34f10; alias, 1 drivers +v0x2cdd200_0 .net "command", 2 0, v0x2cde230_0; 1 drivers +v0x2cdd2e0_0 .var "commandslice", 7 0; +v0x2cdd3a0_0 .net "mixedSigns", 0 0, L_0x2e361c0; 1 drivers +v0x2cdd440_0 .net "operandA", 31 0, v0x2cddf50_0; 1 drivers +v0x2cdd500_0 .net "operandB", 31 0, v0x2cde060_0; 1 drivers +v0x2cdd5e0_0 .net "overFlowPossible", 0 0, L_0x2e3e9a0; 1 drivers +v0x2cdd6b0_0 .net "overflow", 0 0, L_0x2e3e7a0; alias, 1 drivers +v0x2cdd750_0 .net "overflowPre", 0 0, L_0x2e3e690; 1 drivers +v0x2cdd810_0 .net "overrideBus", 31 0, L_0x2e3f4f0; 1 drivers +v0x2cdd900_0 .net "possibleOverflow", 0 0, L_0x2e362d0; 1 drivers +v0x2cdd9a0_0 .net "result", 31 0, L_0x2e43190; alias, 1 drivers +v0x2cdda90_0 .net "resultBus", 31 0, L_0x2e33830; 1 drivers +v0x2cddb60_0 .net "sameSigns", 0 0, L_0x2e3dea0; 1 drivers +v0x2cddc30_0 .net "sltPre", 0 0, L_0x2e3f2c0; 1 drivers +v0x2cddcd0_0 .net "zero", 0 0, L_0x2e3db90; alias, 1 drivers +v0x2cddda0_0 .net "zerobus", 31 0, L_0x2d7dd90; 1 drivers +E_0x2a83c80 .event edge, v0x2cdd200_0; +L_0x2ce8dc0 .part v0x2cddf50_0, 0, 1; +L_0x2ce8f20 .part v0x2cde060_0, 0, 1; +L_0x2ce8fc0 .part L_0x2e33be0, 0, 1; +L_0x2cf3660 .part v0x2cddf50_0, 1, 1; +L_0x2cf37c0 .part v0x2cde060_0, 1, 1; +L_0x2cf3860 .part L_0x2e33be0, 1, 1; +L_0x2cfdef0 .part v0x2cddf50_0, 2, 1; +L_0x2cfe0e0 .part v0x2cde060_0, 2, 1; +L_0x2cfe210 .part L_0x2e33be0, 2, 1; +L_0x2d087e0 .part v0x2cddf50_0, 3, 1; +L_0x2d08940 .part v0x2cde060_0, 3, 1; +L_0x2d089e0 .part L_0x2e33be0, 3, 1; +L_0x2d131f0 .part v0x2cddf50_0, 4, 1; +L_0x2d13350 .part v0x2cde060_0, 4, 1; +L_0x2d13470 .part L_0x2e33be0, 4, 1; +L_0x2d1ea70 .part v0x2cddf50_0, 5, 1; +L_0x2d1eb10 .part v0x2cde060_0, 5, 1; +L_0x2d1ebb0 .part L_0x2e33be0, 5, 1; +L_0x2d29270 .part v0x2cddf50_0, 6, 1; +L_0x2d294e0 .part v0x2cde060_0, 6, 1; +L_0x2d1ec50 .part L_0x2e33be0, 6, 1; +L_0x2d33c00 .part v0x2cddf50_0, 7, 1; +L_0x2d29690 .part v0x2cde060_0, 7, 1; +L_0x2d33e20 .part L_0x2e33be0, 7, 1; +L_0x2d3e4f0 .part v0x2cddf50_0, 8, 1; +L_0x2d3e650 .part v0x2cde060_0, 8, 1; +L_0x2d33fd0 .part L_0x2e33be0, 8, 1; +L_0x2d491e0 .part v0x2cddf50_0, 9, 1; +L_0x2d3e6f0 .part v0x2cde060_0, 9, 1; +L_0x2d49430 .part L_0x2e33be0, 9, 1; +L_0x2d53a40 .part v0x2cddf50_0, 10, 1; +L_0x2d53ba0 .part v0x2cde060_0, 10, 1; +L_0x2d494d0 .part L_0x2e33be0, 10, 1; +L_0x2d5e260 .part v0x2cddf50_0, 11, 1; +L_0x2d53c40 .part v0x2cde060_0, 11, 1; +L_0x2d5e4e0 .part L_0x2e33be0, 11, 1; +L_0x2d68ad0 .part v0x2cddf50_0, 12, 1; +L_0x2d68c30 .part v0x2cde060_0, 12, 1; +L_0x2d5e580 .part L_0x2e33be0, 12, 1; +L_0x2d73370 .part v0x2cddf50_0, 13, 1; +L_0x2d68cd0 .part v0x2cde060_0, 13, 1; +L_0x2d68d70 .part L_0x2e33be0, 13, 1; +L_0x2d7db90 .part v0x2cddf50_0, 14, 1; +L_0x2d293d0 .part v0x2cde060_0, 14, 1; +L_0x2d29580 .part L_0x2e33be0, 14, 1; +L_0x2d88600 .part v0x2cddf50_0, 15, 1; +L_0x2d7e110 .part v0x2cde060_0, 15, 1; +L_0x2d7e1b0 .part L_0x2e33be0, 15, 1; +L_0x2d92fa0 .part v0x2cddf50_0, 16, 1; +L_0x2d93100 .part v0x2cde060_0, 16, 1; +L_0x2d88af0 .part L_0x2e33be0, 16, 1; +L_0x2d9d7b0 .part v0x2cddf50_0, 17, 1; +L_0x2d931a0 .part v0x2cde060_0, 17, 1; +L_0x2d93240 .part L_0x2e33be0, 17, 1; +L_0x2da8850 .part v0x2cddf50_0, 18, 1; +L_0x2da89b0 .part v0x2cde060_0, 18, 1; +L_0x2d9d910 .part L_0x2e33be0, 18, 1; +L_0x2db3100 .part v0x2cddf50_0, 19, 1; +L_0x2da8a50 .part v0x2cde060_0, 19, 1; +L_0x2da8af0 .part L_0x2e33be0, 19, 1; +L_0x2dbd960 .part v0x2cddf50_0, 20, 1; +L_0x2dbdac0 .part v0x2cde060_0, 20, 1; +L_0x2db3260 .part L_0x2e33be0, 20, 1; +L_0x2d1da00 .part v0x2cddf50_0, 21, 1; +L_0x2d1daa0 .part v0x2cde060_0, 21, 1; +L_0x2d1db40 .part L_0x2e33be0, 21, 1; +L_0x2dd4a10 .part v0x2cddf50_0, 22, 1; +L_0x2dd4b70 .part v0x2cde060_0, 22, 1; +L_0x2dca3f0 .part L_0x2e33be0, 22, 1; +L_0x2ddf240 .part v0x2cddf50_0, 23, 1; +L_0x2dd4c10 .part v0x2cde060_0, 23, 1; +L_0x2dd4cb0 .part L_0x2e33be0, 23, 1; +L_0x2de9a80 .part v0x2cddf50_0, 24, 1; +L_0x2de9be0 .part v0x2cde060_0, 24, 1; +L_0x2ddf3a0 .part L_0x2e33be0, 24, 1; +L_0x2df4250 .part v0x2cddf50_0, 25, 1; +L_0x2de9c80 .part v0x2cde060_0, 25, 1; +L_0x2de9d20 .part L_0x2e33be0, 25, 1; +L_0x2dfea80 .part v0x2cddf50_0, 26, 1; +L_0x2dfebe0 .part v0x2cde060_0, 26, 1; +L_0x2df43b0 .part L_0x2e33be0, 26, 1; +L_0x2e092e0 .part v0x2cddf50_0, 27, 1; +L_0x2dfec80 .part v0x2cde060_0, 27, 1; +L_0x2dfed20 .part L_0x2e33be0, 27, 1; +L_0x2e13af0 .part v0x2cddf50_0, 28, 1; +L_0x2e13c50 .part v0x2cde060_0, 28, 1; +L_0x2e09440 .part L_0x2e33be0, 28, 1; +L_0x2e1e310 .part v0x2cddf50_0, 29, 1; +L_0x2e13cf0 .part v0x2cde060_0, 29, 1; +L_0x2e13d90 .part L_0x2e33be0, 29, 1; +L_0x2e28ba0 .part v0x2cddf50_0, 30, 1; +L_0x2d7dcf0 .part v0x2cde060_0, 30, 1; +L_0x2e1e470 .part L_0x2e33be0, 30, 1; +LS_0x2e33830_0_0 .concat8 [ 1 1 1 1], L_0x2ce4f20, L_0x2cef720, L_0x2cfa050, L_0x2d04940; +LS_0x2e33830_0_4 .concat8 [ 1 1 1 1], L_0x2d0f350, L_0x2d19b30, L_0x2d253d0, L_0x2d2fd60; +LS_0x2e33830_0_8 .concat8 [ 1 1 1 1], L_0x2d3a650, L_0x2d45340, L_0x2d4fba0, L_0x2d5a3c0; +LS_0x2e33830_0_12 .concat8 [ 1 1 1 1], L_0x2d64c30, L_0x2d6f4d0, L_0x2d79cf0, L_0x2d84760; +LS_0x2e33830_0_16 .concat8 [ 1 1 1 1], L_0x2d8f100, L_0x2d99910, L_0x2da49b0, L_0x2daf260; +LS_0x2e33830_0_20 .concat8 [ 1 1 1 1], L_0x2db9ac0, L_0x2dc4300, L_0x2dd0b70, L_0x2ddb3a0; +LS_0x2e33830_0_24 .concat8 [ 1 1 1 1], L_0x2de5be0, L_0x2df03b0, L_0x2dfabe0, L_0x2e05440; +LS_0x2e33830_0_28 .concat8 [ 1 1 1 1], L_0x2e0fbf0, L_0x2e1a470, L_0x2e24d00, L_0x2e2f8b0; +LS_0x2e33830_1_0 .concat8 [ 4 4 4 4], LS_0x2e33830_0_0, LS_0x2e33830_0_4, LS_0x2e33830_0_8, LS_0x2e33830_0_12; +LS_0x2e33830_1_4 .concat8 [ 4 4 4 4], LS_0x2e33830_0_16, LS_0x2e33830_0_20, LS_0x2e33830_0_24, LS_0x2e33830_0_28; +L_0x2e33830 .concat8 [ 16 16 0 0], LS_0x2e33830_1_0, LS_0x2e33830_1_4; +LS_0x2d7dd90_0_0 .concat8 [ 1 1 1 1], L_0x2ce8cc0, L_0x2cf3510, L_0x2cfddf0, L_0x2d086e0; +LS_0x2d7dd90_0_4 .concat8 [ 1 1 1 1], L_0x2d130f0, L_0x2d1e810, L_0x2d29170, L_0x2d33b00; +LS_0x2d7dd90_0_8 .concat8 [ 1 1 1 1], L_0x2d3e3f0, L_0x2d490e0, L_0x2d53940, L_0x2d5e160; +LS_0x2d7dd90_0_12 .concat8 [ 1 1 1 1], L_0x2d689d0, L_0x2d73270, L_0x2d7da90, L_0x2d88500; +LS_0x2d7dd90_0_16 .concat8 [ 1 1 1 1], L_0x2d92ea0, L_0x2d9d6b0, L_0x2da8750, L_0x2db3000; +LS_0x2d7dd90_0_20 .concat8 [ 1 1 1 1], L_0x2dbd860, L_0x2d1d7a0, L_0x2dd4910, L_0x2ddf140; +LS_0x2d7dd90_0_24 .concat8 [ 1 1 1 1], L_0x2de9980, L_0x2df4150, L_0x2dfe980, L_0x2e091e0; +LS_0x2d7dd90_0_28 .concat8 [ 1 1 1 1], L_0x2e139f0, L_0x2e1e210, L_0x2e28aa0, L_0x2e33730; +LS_0x2d7dd90_1_0 .concat8 [ 4 4 4 4], LS_0x2d7dd90_0_0, LS_0x2d7dd90_0_4, LS_0x2d7dd90_0_8, LS_0x2d7dd90_0_12; +LS_0x2d7dd90_1_4 .concat8 [ 4 4 4 4], LS_0x2d7dd90_0_16, LS_0x2d7dd90_0_20, LS_0x2d7dd90_0_24, LS_0x2d7dd90_0_28; +L_0x2d7dd90 .concat8 [ 16 16 0 0], LS_0x2d7dd90_1_0, LS_0x2d7dd90_1_4; +L_0x2e346b0 .part v0x2cddf50_0, 31, 1; +L_0x2e33aa0 .part v0x2cde060_0, 31, 1; +L_0x2e33b40 .part L_0x2e33be0, 31, 1; +LS_0x2e33be0_0_0 .concat8 [ 1 1 1 1], L_0x2e33c80, L_0x2ce8960, L_0x2cf31b0, L_0x2cfda90; +LS_0x2e33be0_0_4 .concat8 [ 1 1 1 1], L_0x2d08380, L_0x2d12d90, L_0x2d1e4b0, L_0x2d28e10; +LS_0x2e33be0_0_8 .concat8 [ 1 1 1 1], L_0x2d337a0, L_0x2d3e090, L_0x2d48d80, L_0x2d535e0; +LS_0x2e33be0_0_12 .concat8 [ 1 1 1 1], L_0x2d5de00, L_0x2d68670, L_0x2d72f10, L_0x2d7d730; +LS_0x2e33be0_0_16 .concat8 [ 1 1 1 1], L_0x2d881a0, L_0x2d92b40, L_0x2d9d350, L_0x2da83f0; +LS_0x2e33be0_0_20 .concat8 [ 1 1 1 1], L_0x2db2ca0, L_0x2dbd500, L_0x2d1d440, L_0x2dd45b0; +LS_0x2e33be0_0_24 .concat8 [ 1 1 1 1], L_0x2ddede0, L_0x2de9620, L_0x2df3df0, L_0x2dfe620; +LS_0x2e33be0_0_28 .concat8 [ 1 1 1 1], L_0x2e08e80, L_0x2e13690, L_0x2e1deb0, L_0x2e28740; +LS_0x2e33be0_0_32 .concat8 [ 1 0 0 0], L_0x2e333d0; +LS_0x2e33be0_1_0 .concat8 [ 4 4 4 4], LS_0x2e33be0_0_0, LS_0x2e33be0_0_4, LS_0x2e33be0_0_8, LS_0x2e33be0_0_12; +LS_0x2e33be0_1_4 .concat8 [ 4 4 4 4], LS_0x2e33be0_0_16, LS_0x2e33be0_0_20, LS_0x2e33be0_0_24, LS_0x2e33be0_0_28; +LS_0x2e33be0_1_8 .concat8 [ 1 0 0 0], LS_0x2e33be0_0_32; +L_0x2e33be0 .concat8 [ 16 16 1 0], LS_0x2e33be0_1_0, LS_0x2e33be0_1_4, LS_0x2e33be0_1_8; +L_0x2e36030 .part v0x2cdd2e0_0, 1, 1; +L_0x2e34e70 .part v0x2cdd2e0_0, 1, 1; +L_0x2e34f80 .part L_0x2e33be0, 32, 1; +L_0x2e35020 .part L_0x2e33be0, 32, 1; +L_0x2e3dfb0 .part v0x2cddf50_0, 31, 1; +L_0x2e360d0 .part v0x2cde060_0, 31, 1; +L_0x2e3e4b0 .part L_0x2e43190, 31, 1; +L_0x2e3eba0 .part v0x2cdd2e0_0, 0, 1; +L_0x2e3ed50 .part v0x2cdd2e0_0, 0, 1; +L_0x2e3e5a0 .part v0x2cdd2e0_0, 1, 1; +LS_0x2e3f4f0_0_0 .concat8 [ 1 1 1 1], L_0x2e3eeb0, L_0x2ce9560, L_0x2ceaec0, L_0x2d08880; +LS_0x2e3f4f0_0_4 .concat8 [ 1 1 1 1], L_0x2d00c00, L_0x2d13a80, L_0x2d1f3a0, L_0x2d29d50; +LS_0x2e3f4f0_0_8 .concat8 [ 1 1 1 1], L_0x2d345f0, L_0x2d41600, L_0x2d49b90, L_0x2d54360; +LS_0x2e3f4f0_0_12 .concat8 [ 1 1 1 1], L_0x2d60ef0, L_0x2d69470, L_0x2d73c90, L_0x2d80a20; +LS_0x2e3f4f0_0_16 .concat8 [ 1 1 1 1], L_0x2d8b3c0, L_0x2d938b0, L_0x2d40dd0, L_0x2dab520; +LS_0x2e3f4f0_0_20 .concat8 [ 1 1 1 1], L_0x2db3a60, L_0x2dc05c0, L_0x2dcaac0, L_0x2dd5340; +LS_0x2e3f4f0_0_24 .concat8 [ 1 1 1 1], L_0x2de1ea0, L_0x2dec6d0, L_0x2df4b80, L_0x2e01700; +LS_0x2e3f4f0_0_28 .concat8 [ 1 1 1 1], L_0x2e0bf50, L_0x2e14410, L_0x2e28c40, L_0x2e298c0; +LS_0x2e3f4f0_1_0 .concat8 [ 4 4 4 4], LS_0x2e3f4f0_0_0, LS_0x2e3f4f0_0_4, LS_0x2e3f4f0_0_8, LS_0x2e3f4f0_0_12; +LS_0x2e3f4f0_1_4 .concat8 [ 4 4 4 4], LS_0x2e3f4f0_0_16, LS_0x2e3f4f0_0_20, LS_0x2e3f4f0_0_24, LS_0x2e3f4f0_0_28; +L_0x2e3f4f0 .concat8 [ 16 16 0 0], LS_0x2e3f4f0_1_0, LS_0x2e3f4f0_1_4; +L_0x2e3f010 .part v0x2cdd2e0_0, 3, 1; +S_0x25fb430 .scope generate, "alu_slices[0]" "alu_slices[0]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2a850d0 .param/l "i" 0 3 39, +C4<00>; +S_0x27d7440 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x25fb430; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -272,445 +274,476 @@ S_0xeed4d0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xf0e870; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1202350/d .functor NOT 1, L_0x120bed0, C4<0>, C4<0>, C4<0>; -L_0x1202350 .delay 1 (10000,10000,10000) L_0x1202350/d; -L_0x1202460/d .functor NOT 1, L_0x120c030, C4<0>, C4<0>, C4<0>; -L_0x1202460 .delay 1 (10000,10000,10000) L_0x1202460/d; -L_0x12036a0/d .functor XOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; -L_0x12036a0 .delay 1 (30000,30000,30000) L_0x12036a0/d; -L_0x2b0ab3d05018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1203df0/d .functor OR 1, L_0x2b0ab3d05018, L_0x2b0ab3d05060, C4<0>, C4<0>; -L_0x1203df0 .delay 1 (30000,30000,30000) L_0x1203df0/d; -L_0x1203ff0/d .functor AND 1, L_0x120bed0, L_0x120c030, C4<1>, C4<1>; -L_0x1203ff0 .delay 1 (30000,30000,30000) L_0x1203ff0/d; -L_0x12040b0/d .functor NAND 1, L_0x120bed0, L_0x120c030, C4<1>, C4<1>; -L_0x12040b0 .delay 1 (20000,20000,20000) L_0x12040b0/d; -L_0x1204210/d .functor XOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; -L_0x1204210 .delay 1 (20000,20000,20000) L_0x1204210/d; -L_0x12046c0/d .functor OR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; -L_0x12046c0 .delay 1 (30000,30000,30000) L_0x12046c0/d; -L_0x120bdd0/d .functor NOT 1, L_0x1208030, C4<0>, C4<0>, C4<0>; -L_0x120bdd0 .delay 1 (10000,10000,10000) L_0x120bdd0/d; -v0xc655e0_0 .net "A", 0 0, L_0x120bed0; 1 drivers -v0xc65680_0 .net "A_", 0 0, L_0x1202350; 1 drivers -v0xc74f90_0 .net "B", 0 0, L_0x120c030; 1 drivers -v0xc75030_0 .net "B_", 0 0, L_0x1202460; 1 drivers -v0xc74c00_0 .net *"_s12", 0 0, L_0x1203df0; 1 drivers -v0xc71f50_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05018; 1 drivers -v0xc71ff0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05060; 1 drivers -v0xc36e40_0 .net *"_s18", 0 0, L_0x1203ff0; 1 drivers -v0xc397b0_0 .net *"_s20", 0 0, L_0x12040b0; 1 drivers -v0xc47270_0 .net *"_s22", 0 0, L_0x1204210; 1 drivers -v0xc46e30_0 .net *"_s24", 0 0, L_0x12046c0; 1 drivers -o0x2b0ab3ca5328 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0xc44140_0 name=_s30 -o0x2b0ab3ca5358 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0xc53b50_0 name=_s32 -v0xc537c0_0 .net *"_s8", 0 0, L_0x12036a0; 1 drivers -v0xc50b10_0 .net "carryin", 0 0, L_0x120c120; 1 drivers -v0xc50bb0_0 .net "carryout", 0 0, L_0x120ba70; 1 drivers -v0xc15a10_0 .net "carryouts", 7 0, L_0x1352170; 1 drivers -v0xc15ab0_0 .net "command", 7 0, v0x12010b0_0; 1 drivers -v0xc25950_0 .net "result", 0 0, L_0x1208030; 1 drivers -v0xc259f0_0 .net "results", 7 0, L_0x1204490; 1 drivers -v0xc22c60_0 .net "zero", 0 0, L_0x120bdd0; 1 drivers -LS_0x1204490_0_0 .concat8 [ 1 1 1 1], L_0x12029a0, L_0x1203130, L_0x12036a0, L_0x1203df0; -LS_0x1204490_0_4 .concat8 [ 1 1 1 1], L_0x1203ff0, L_0x12040b0, L_0x1204210, L_0x12046c0; -L_0x1204490 .concat8 [ 4 4 0 0], LS_0x1204490_0_0, LS_0x1204490_0_4; -LS_0x1352170_0_0 .concat [ 1 1 1 1], L_0x1202cc0, L_0x1203540, o0x2b0ab3ca5328, L_0x1203c40; -LS_0x1352170_0_4 .concat [ 4 0 0 0], o0x2b0ab3ca5358; -L_0x1352170 .concat [ 4 4 0 0], LS_0x1352170_0_0, LS_0x1352170_0_4; -S_0xecc120 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xeed4d0; +L_0x2cde580/d .functor NOT 1, L_0x2ce8dc0, C4<0>, C4<0>, C4<0>; +L_0x2cde580 .delay 1 (10000,10000,10000) L_0x2cde580/d; +L_0x2cde690/d .functor NOT 1, L_0x2ce8f20, C4<0>, C4<0>, C4<0>; +L_0x2cde690 .delay 1 (10000,10000,10000) L_0x2cde690/d; +L_0x2cdf920/d .functor XOR 1, L_0x2ce8dc0, L_0x2ce8f20, C4<0>, C4<0>; +L_0x2cdf920 .delay 1 (30000,30000,30000) L_0x2cdf920/d; +L_0x2ac6110b6018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cdfa80/d .functor OR 1, L_0x2ac6110b6018, L_0x2ac6110b6060, C4<0>, C4<0>; +L_0x2cdfa80 .delay 1 (30000,30000,30000) L_0x2cdfa80/d; +L_0x2ac6110b60a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b60f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ce01d0/d .functor OR 1, L_0x2ac6110b60a8, L_0x2ac6110b60f0, C4<0>, C4<0>; +L_0x2ce01d0 .delay 1 (30000,30000,30000) L_0x2ce01d0/d; +L_0x2ce03d0/d .functor AND 1, L_0x2ce8dc0, L_0x2ce8f20, C4<1>, C4<1>; +L_0x2ce03d0 .delay 1 (30000,30000,30000) L_0x2ce03d0/d; +L_0x2ac6110b6138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ce0490/d .functor OR 1, L_0x2ac6110b6138, L_0x2ac6110b6180, C4<0>, C4<0>; +L_0x2ce0490 .delay 1 (30000,30000,30000) L_0x2ce0490/d; +L_0x2ce06e0/d .functor NAND 1, L_0x2ce8dc0, L_0x2ce8f20, C4<1>, C4<1>; +L_0x2ce06e0 .delay 1 (20000,20000,20000) L_0x2ce06e0/d; +L_0x2ac6110b61c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ce07f0/d .functor OR 1, L_0x2ac6110b61c8, L_0x2ac6110b6210, C4<0>, C4<0>; +L_0x2ce07f0 .delay 1 (30000,30000,30000) L_0x2ce07f0/d; +L_0x2ce09a0/d .functor NOR 1, L_0x2ce8dc0, L_0x2ce8f20, C4<0>, C4<0>; +L_0x2ce09a0 .delay 1 (20000,20000,20000) L_0x2ce09a0/d; +L_0x2ac6110b6258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b62a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ce0c70/d .functor OR 1, L_0x2ac6110b6258, L_0x2ac6110b62a0, C4<0>, C4<0>; +L_0x2ce0c70 .delay 1 (30000,30000,30000) L_0x2ce0c70/d; +L_0x2ce10c0/d .functor OR 1, L_0x2ce8dc0, L_0x2ce8f20, C4<0>, C4<0>; +L_0x2ce10c0 .delay 1 (30000,30000,30000) L_0x2ce10c0/d; +L_0x2ac6110b62e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ce1560/d .functor OR 1, L_0x2ac6110b62e8, L_0x2ac6110b6330, C4<0>, C4<0>; +L_0x2ce1560 .delay 1 (30000,30000,30000) L_0x2ce1560/d; +L_0x2ce8cc0/d .functor NOT 1, L_0x2ce4f20, C4<0>, C4<0>, C4<0>; +L_0x2ce8cc0 .delay 1 (10000,10000,10000) L_0x2ce8cc0/d; +v0x2780310_0 .net "A", 0 0, L_0x2ce8dc0; 1 drivers +v0x27803b0_0 .net "A_", 0 0, L_0x2cde580; 1 drivers +v0x278cff0_0 .net "B", 0 0, L_0x2ce8f20; 1 drivers +v0x278d090_0 .net "B_", 0 0, L_0x2cde690; 1 drivers +v0x278cc60_0 .net *"_s11", 0 0, L_0x2cdfa80; 1 drivers +v0x2789fb0_0 .net/2s *"_s13", 0 0, L_0x2ac6110b6018; 1 drivers +v0x278a050_0 .net/2s *"_s15", 0 0, L_0x2ac6110b6060; 1 drivers +v0x27495a0_0 .net *"_s19", 0 0, L_0x2ce01d0; 1 drivers +v0x2748030_0 .net/2s *"_s21", 0 0, L_0x2ac6110b60a8; 1 drivers +v0x274b620_0 .net/2s *"_s23", 0 0, L_0x2ac6110b60f0; 1 drivers +v0x275bac0_0 .net *"_s25", 0 0, L_0x2ce03d0; 1 drivers +v0x275b680_0 .net *"_s28", 0 0, L_0x2ce0490; 1 drivers +v0x2758990_0 .net/2s *"_s30", 0 0, L_0x2ac6110b6138; 1 drivers +v0x27683f0_0 .net/2s *"_s32", 0 0, L_0x2ac6110b6180; 1 drivers +v0x2768060_0 .net *"_s34", 0 0, L_0x2ce06e0; 1 drivers +v0x27653b0_0 .net *"_s37", 0 0, L_0x2ce07f0; 1 drivers +v0x27249b0_0 .net/2s *"_s39", 0 0, L_0x2ac6110b61c8; 1 drivers +v0x2724a50_0 .net/2s *"_s41", 0 0, L_0x2ac6110b6210; 1 drivers +v0x2726a30_0 .net *"_s43", 0 0, L_0x2ce09a0; 1 drivers +v0x2736ed0_0 .net *"_s46", 0 0, L_0x2ce0c70; 1 drivers +v0x2736a90_0 .net/2s *"_s48", 0 0, L_0x2ac6110b6258; 1 drivers +v0x2743870_0 .net/2s *"_s50", 0 0, L_0x2ac6110b62a0; 1 drivers +v0x27434e0_0 .net *"_s52", 0 0, L_0x2ce10c0; 1 drivers +v0x2740680_0 .net *"_s56", 0 0, L_0x2ce1560; 1 drivers +v0x2711f40_0 .net/2s *"_s59", 0 0, L_0x2ac6110b62e8; 1 drivers +v0x270f420_0 .net/2s *"_s61", 0 0, L_0x2ac6110b6330; 1 drivers +v0x271ec10_0 .net *"_s8", 0 0, L_0x2cdf920; 1 drivers +v0x271e7d0_0 .net "carryin", 0 0, L_0x2ce8fc0; 1 drivers +v0x271e870_0 .net "carryout", 0 0, L_0x2ce8960; 1 drivers +v0x26ed9d0_0 .net "carryouts", 7 0, L_0x2ce11d0; 1 drivers +v0x26ed640_0 .net "command", 7 0, v0x2cdd2e0_0; 1 drivers +v0x26ed700_0 .net "result", 0 0, L_0x2ce4f20; 1 drivers +v0x26ea990_0 .net "results", 7 0, L_0x2ce0e40; 1 drivers +v0x26eaa30_0 .net "zero", 0 0, L_0x2ce8cc0; 1 drivers +LS_0x2ce0e40_0_0 .concat8 [ 1 1 1 1], L_0x2cdebd0, L_0x2cdf3b0, L_0x2cdf920, L_0x2ce01d0; +LS_0x2ce0e40_0_4 .concat8 [ 1 1 1 1], L_0x2ce03d0, L_0x2ce06e0, L_0x2ce09a0, L_0x2ce10c0; +L_0x2ce0e40 .concat8 [ 4 4 0 0], LS_0x2ce0e40_0_0, LS_0x2ce0e40_0_4; +LS_0x2ce11d0_0_0 .concat8 [ 1 1 1 1], L_0x2cdef40, L_0x2cdf7c0, L_0x2cdfa80, L_0x2ce0020; +LS_0x2ce11d0_0_4 .concat8 [ 1 1 1 1], L_0x2ce0490, L_0x2ce07f0, L_0x2ce0c70, L_0x2ce1560; +L_0x2ce11d0 .concat8 [ 4 4 0 0], LS_0x2ce11d0_0_0, LS_0x2ce11d0_0_4; +S_0x27b2bb0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x27d7440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1202cc0/d .functor OR 1, L_0x1202750, L_0x1202b30, C4<0>, C4<0>; -L_0x1202cc0 .delay 1 (30000,30000,30000) L_0x1202cc0/d; -v0xf70aa0_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers -v0xf70b60_0 .net "b", 0 0, L_0x120c030; alias, 1 drivers -v0xf6ddb0_0 .net "c1", 0 0, L_0x1202750; 1 drivers -v0xf345c0_0 .net "c2", 0 0, L_0x1202b30; 1 drivers -v0xf33050_0 .net "carryin", 0 0, L_0x120c120; alias, 1 drivers -v0xf42e40_0 .net "carryout", 0 0, L_0x1202cc0; 1 drivers -v0xf42ee0_0 .net "s1", 0 0, L_0x1202650; 1 drivers -v0xf4fb30_0 .net "sum", 0 0, L_0x12029a0; 1 drivers -S_0xeaad90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xecc120; +L_0x2cdef40/d .functor OR 1, L_0x2cde980, L_0x2cdedb0, C4<0>, C4<0>; +L_0x2cdef40 .delay 1 (30000,30000,30000) L_0x2cdef40/d; +v0x2a28ea0_0 .net "a", 0 0, L_0x2ce8dc0; alias, 1 drivers +v0x2a28f60_0 .net "b", 0 0, L_0x2ce8f20; alias, 1 drivers +v0x2a38ea0_0 .net "c1", 0 0, L_0x2cde980; 1 drivers +v0x2a45ba0_0 .net "c2", 0 0, L_0x2cdedb0; 1 drivers +v0x2a45760_0 .net "carryin", 0 0, L_0x2ce8fc0; alias, 1 drivers +v0x2a148d0_0 .net "carryout", 0 0, L_0x2cdef40; 1 drivers +v0x2a14970_0 .net "s1", 0 0, L_0x2cde880; 1 drivers +v0x2a14540_0 .net "sum", 0 0, L_0x2cdebd0; 1 drivers +S_0x261f460 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x27b2bb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1202650/d .functor XOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; -L_0x1202650 .delay 1 (30000,30000,30000) L_0x1202650/d; -L_0x1202750/d .functor AND 1, L_0x120bed0, L_0x120c030, C4<1>, C4<1>; -L_0x1202750 .delay 1 (30000,30000,30000) L_0x1202750/d; -v0x90cb20_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers -v0xf91fc0_0 .net "b", 0 0, L_0x120c030; alias, 1 drivers -v0xf8f170_0 .net "carryout", 0 0, L_0x1202750; alias, 1 drivers -v0xf55940_0 .net "sum", 0 0, L_0x1202650; alias, 1 drivers -S_0xe899e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xecc120; +L_0x2cde880/d .functor XOR 1, L_0x2ce8dc0, L_0x2ce8f20, C4<0>, C4<0>; +L_0x2cde880 .delay 1 (30000,30000,30000) L_0x2cde880/d; +L_0x2cde980/d .functor AND 1, L_0x2ce8dc0, L_0x2ce8f20, C4<1>, C4<1>; +L_0x2cde980 .delay 1 (30000,30000,30000) L_0x2cde980/d; +v0x25eacb0_0 .net "a", 0 0, L_0x2ce8dc0; alias, 1 drivers +v0x2a5d9e0_0 .net "b", 0 0, L_0x2ce8f20; alias, 1 drivers +v0x2a5daa0_0 .net "carryout", 0 0, L_0x2cde980; alias, 1 drivers +v0x2a5acf0_0 .net "sum", 0 0, L_0x2cde880; alias, 1 drivers +S_0x2a77fa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x27b2bb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12029a0/d .functor XOR 1, L_0x1202650, L_0x120c120, C4<0>, C4<0>; -L_0x12029a0 .delay 1 (30000,30000,30000) L_0x12029a0/d; -L_0x1202b30/d .functor AND 1, L_0x1202650, L_0x120c120, C4<1>, C4<1>; -L_0x1202b30 .delay 1 (30000,30000,30000) L_0x1202b30/d; -v0xf64600_0 .net "a", 0 0, L_0x1202650; alias, 1 drivers -v0xf641c0_0 .net "b", 0 0, L_0x120c120; alias, 1 drivers -v0xf64260_0 .net "carryout", 0 0, L_0x1202b30; alias, 1 drivers -v0xf70ee0_0 .net "sum", 0 0, L_0x12029a0; alias, 1 drivers -S_0xd5e8d0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xeed4d0; +L_0x2cdebd0/d .functor XOR 1, L_0x2cde880, L_0x2ce8fc0, C4<0>, C4<0>; +L_0x2cdebd0 .delay 1 (30000,30000,30000) L_0x2cdebd0/d; +L_0x2cdedb0/d .functor AND 1, L_0x2cde880, L_0x2ce8fc0, C4<1>, C4<1>; +L_0x2cdedb0 .delay 1 (30000,30000,30000) L_0x2cdedb0/d; +v0x2a6a850_0 .net "a", 0 0, L_0x2cde880; alias, 1 drivers +v0x2a6a430_0 .net "b", 0 0, L_0x2ce8fc0; alias, 1 drivers +v0x2a675d0_0 .net "carryout", 0 0, L_0x2cdedb0; alias, 1 drivers +v0x2a26e20_0 .net "sum", 0 0, L_0x2cdebd0; alias, 1 drivers +S_0x2a4b690 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x27d7440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xe24c40_0 .net "ands", 7 0, L_0x1209a70; 1 drivers -v0xe24800_0 .net "in", 7 0, L_0x1352170; alias, 1 drivers -v0xe248c0_0 .net "out", 0 0, L_0x120ba70; alias, 1 drivers -v0xdf72b0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xfc0f60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xd5e8d0; +v0x28ec260_0 .net "ands", 7 0, L_0x2ce6960; 1 drivers +v0x28fb970_0 .net "in", 7 0, L_0x2ce11d0; alias, 1 drivers +v0x28fba30_0 .net "out", 0 0, L_0x2ce8960; alias, 1 drivers +v0x28fb530_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2a4a0f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2a4b690; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xee8f30_0 .net "A", 7 0, L_0x1352170; alias, 1 drivers -v0xebe530_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xebe1a0_0 .net *"_s0", 0 0, L_0x1208390; 1 drivers -v0xebe260_0 .net *"_s12", 0 0, L_0x1208d00; 1 drivers -v0xebb4f0_0 .net *"_s16", 0 0, L_0x1209060; 1 drivers -v0xecacb0_0 .net *"_s20", 0 0, L_0x1209370; 1 drivers -v0xeca870_0 .net *"_s24", 0 0, L_0x1209760; 1 drivers -v0xec7b80_0 .net *"_s28", 0 0, L_0x12096f0; 1 drivers -v0xe9d1b0_0 .net *"_s4", 0 0, L_0x12086a0; 1 drivers -v0xe9ce20_0 .net *"_s8", 0 0, L_0x12089f0; 1 drivers -v0xe9a170_0 .net "out", 7 0, L_0x1209a70; alias, 1 drivers -L_0x1208450 .part L_0x1352170, 0, 1; -L_0x12085b0 .part v0x12010b0_0, 0, 1; -L_0x1208760 .part L_0x1352170, 1, 1; -L_0x1208950 .part v0x12010b0_0, 1, 1; -L_0x1208ab0 .part L_0x1352170, 2, 1; -L_0x1208c10 .part v0x12010b0_0, 2, 1; -L_0x1208dc0 .part L_0x1352170, 3, 1; -L_0x1208f20 .part v0x12010b0_0, 3, 1; -L_0x1209120 .part L_0x1352170, 4, 1; -L_0x1209280 .part v0x12010b0_0, 4, 1; -L_0x12093e0 .part L_0x1352170, 5, 1; -L_0x1209650 .part v0x12010b0_0, 5, 1; -L_0x1209820 .part L_0x1352170, 6, 1; -L_0x1209980 .part v0x12010b0_0, 6, 1; -LS_0x1209a70_0_0 .concat8 [ 1 1 1 1], L_0x1208390, L_0x12086a0, L_0x12089f0, L_0x1208d00; -LS_0x1209a70_0_4 .concat8 [ 1 1 1 1], L_0x1209060, L_0x1209370, L_0x1209760, L_0x12096f0; -L_0x1209a70 .concat8 [ 4 4 0 0], LS_0x1209a70_0_0, LS_0x1209a70_0_4; -L_0x1209e30 .part L_0x1352170, 7, 1; -L_0x120a020 .part v0x12010b0_0, 7, 1; -S_0xf97d50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xf4f7d0 .param/l "i" 0 4 54, +C4<00>; -L_0x1208390/d .functor AND 1, L_0x1208450, L_0x12085b0, C4<1>, C4<1>; -L_0x1208390 .delay 1 (30000,30000,30000) L_0x1208390/d; -v0xf13220_0 .net *"_s0", 0 0, L_0x1208450; 1 drivers -v0xf11c20_0 .net *"_s1", 0 0, L_0x12085b0; 1 drivers -S_0xf967b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xf21ab0 .param/l "i" 0 4 54, +C4<01>; -L_0x12086a0/d .functor AND 1, L_0x1208760, L_0x1208950, C4<1>, C4<1>; -L_0x12086a0 .delay 1 (30000,30000,30000) L_0x12086a0/d; -v0xf21b50_0 .net *"_s0", 0 0, L_0x1208760; 1 drivers -v0xf1ef40_0 .net *"_s1", 0 0, L_0x1208950; 1 drivers -S_0xf769d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xf2e7a0 .param/l "i" 0 4 54, +C4<010>; -L_0x12089f0/d .functor AND 1, L_0x1208ab0, L_0x1208c10, C4<1>, C4<1>; -L_0x12089f0 .delay 1 (30000,30000,30000) L_0x12089f0/d; -v0xf2e840_0 .net *"_s0", 0 0, L_0x1208ab0; 1 drivers -v0xf2e360_0 .net *"_s1", 0 0, L_0x1208c10; 1 drivers -S_0xf75430 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xef1df0 .param/l "i" 0 4 54, +C4<011>; -L_0x1208d00/d .functor AND 1, L_0x1208dc0, L_0x1208f20, C4<1>, C4<1>; -L_0x1208d00 .delay 1 (30000,30000,30000) L_0x1208d00/d; -v0xef1eb0_0 .net *"_s0", 0 0, L_0x1208dc0; 1 drivers -v0xef08c0_0 .net *"_s1", 0 0, L_0x1208f20; 1 drivers -S_0xf55630 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xefdc40 .param/l "i" 0 4 54, +C4<0100>; -L_0x1209060/d .functor AND 1, L_0x1209120, L_0x1209280, C4<1>, C4<1>; -L_0x1209060 .delay 1 (30000,30000,30000) L_0x1209060/d; -v0xf0d400_0 .net *"_s0", 0 0, L_0x1209120; 1 drivers -v0xf0cfc0_0 .net *"_s1", 0 0, L_0x1209280; 1 drivers -S_0xf54090 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xf0d500 .param/l "i" 0 4 54, +C4<0101>; -L_0x1209370/d .functor AND 1, L_0x12093e0, L_0x1209650, C4<1>, C4<1>; -L_0x1209370 .delay 1 (30000,30000,30000) L_0x1209370/d; -v0xed0aa0_0 .net *"_s0", 0 0, L_0x12093e0; 1 drivers -v0xed0740_0 .net *"_s1", 0 0, L_0x1209650; 1 drivers -S_0xf342b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xedf860 .param/l "i" 0 4 54, +C4<0110>; -L_0x1209760/d .functor AND 1, L_0x1209820, L_0x1209980, C4<1>, C4<1>; -L_0x1209760 .delay 1 (30000,30000,30000) L_0x1209760/d; -v0xedf4b0_0 .net *"_s0", 0 0, L_0x1209820; 1 drivers -v0xedc800_0 .net *"_s1", 0 0, L_0x1209980; 1 drivers -S_0xf32d10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xfc0f60; - .timescale -9 -12; -P_0xedf940 .param/l "i" 0 4 54, +C4<0111>; -L_0x12096f0/d .functor AND 1, L_0x1209e30, L_0x120a020, C4<1>, C4<1>; -L_0x12096f0 .delay 1 (30000,30000,30000) L_0x12096f0/d; -v0xeec060_0 .net *"_s0", 0 0, L_0x1209e30; 1 drivers -v0xeebc20_0 .net *"_s1", 0 0, L_0x120a020; 1 drivers -S_0xf12e80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xd5e8d0; +v0x29a6780_0 .net "A", 7 0, L_0x2ce11d0; alias, 1 drivers +v0x29b31c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x29b2e30_0 .net *"_s0", 0 0, L_0x2ce5280; 1 drivers +v0x29b2ef0_0 .net *"_s12", 0 0, L_0x2ce5bf0; 1 drivers +v0x29b0180_0 .net *"_s16", 0 0, L_0x2ce5f50; 1 drivers +v0x296f8d0_0 .net *"_s20", 0 0, L_0x2ce6320; 1 drivers +v0x296e360_0 .net *"_s24", 0 0, L_0x2ce6650; 1 drivers +v0x2971950_0 .net *"_s28", 0 0, L_0x2ce65e0; 1 drivers +v0x2981f00_0 .net *"_s4", 0 0, L_0x2ce55d0; 1 drivers +v0x2981ac0_0 .net *"_s8", 0 0, L_0x2ce58e0; 1 drivers +v0x297edd0_0 .net "out", 7 0, L_0x2ce6960; alias, 1 drivers +L_0x2ce5340 .part L_0x2ce11d0, 0, 1; +L_0x2ce5530 .part v0x2cdd2e0_0, 0, 1; +L_0x2ce5690 .part L_0x2ce11d0, 1, 1; +L_0x2ce57f0 .part v0x2cdd2e0_0, 1, 1; +L_0x2ce59a0 .part L_0x2ce11d0, 2, 1; +L_0x2ce5b00 .part v0x2cdd2e0_0, 2, 1; +L_0x2ce5cb0 .part L_0x2ce11d0, 3, 1; +L_0x2ce5e10 .part v0x2cdd2e0_0, 3, 1; +L_0x2ce6010 .part L_0x2ce11d0, 4, 1; +L_0x2ce6280 .part v0x2cdd2e0_0, 4, 1; +L_0x2ce6390 .part L_0x2ce11d0, 5, 1; +L_0x2ce64f0 .part v0x2cdd2e0_0, 5, 1; +L_0x2ce6710 .part L_0x2ce11d0, 6, 1; +L_0x2ce6870 .part v0x2cdd2e0_0, 6, 1; +LS_0x2ce6960_0_0 .concat8 [ 1 1 1 1], L_0x2ce5280, L_0x2ce55d0, L_0x2ce58e0, L_0x2ce5bf0; +LS_0x2ce6960_0_4 .concat8 [ 1 1 1 1], L_0x2ce5f50, L_0x2ce6320, L_0x2ce6650, L_0x2ce65e0; +L_0x2ce6960 .concat8 [ 4 4 0 0], LS_0x2ce6960_0_0, LS_0x2ce6960_0_4; +L_0x2ce6d20 .part L_0x2ce11d0, 7, 1; +L_0x2ce6f10 .part v0x2cdd2e0_0, 7, 1; +S_0x2a26b10 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x2a118e0 .param/l "i" 0 4 54, +C4<00>; +L_0x2ce5280/d .functor AND 1, L_0x2ce5340, L_0x2ce5530, C4<1>, C4<1>; +L_0x2ce5280 .delay 1 (30000,30000,30000) L_0x2ce5280/d; +v0x2a21080_0 .net *"_s0", 0 0, L_0x2ce5340; 1 drivers +v0x2a20c40_0 .net *"_s1", 0 0, L_0x2ce5530; 1 drivers +S_0x2a361a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x2a21160 .param/l "i" 0 4 54, +C4<01>; +L_0x2ce55d0/d .functor AND 1, L_0x2ce5690, L_0x2ce57f0, C4<1>, C4<1>; +L_0x2ce55d0 .delay 1 (30000,30000,30000) L_0x2ce55d0/d; +v0x2a1dfc0_0 .net *"_s0", 0 0, L_0x2ce5690; 1 drivers +v0x29efec0_0 .net *"_s1", 0 0, L_0x2ce57f0; 1 drivers +S_0x2994180 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x29efb30 .param/l "i" 0 4 54, +C4<010>; +L_0x2ce58e0/d .functor AND 1, L_0x2ce59a0, L_0x2ce5b00, C4<1>, C4<1>; +L_0x2ce58e0 .delay 1 (30000,30000,30000) L_0x2ce58e0/d; +v0x29efbd0_0 .net *"_s0", 0 0, L_0x2ce59a0; 1 drivers +v0x29ece80_0 .net *"_s1", 0 0, L_0x2ce5b00; 1 drivers +S_0x2992be0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x29fc590 .param/l "i" 0 4 54, +C4<011>; +L_0x2ce5bf0/d .functor AND 1, L_0x2ce5cb0, L_0x2ce5e10, C4<1>, C4<1>; +L_0x2ce5bf0 .delay 1 (30000,30000,30000) L_0x2ce5bf0/d; +v0x29fc650_0 .net *"_s0", 0 0, L_0x2ce5cb0; 1 drivers +v0x29fc150_0 .net *"_s1", 0 0, L_0x2ce5e10; 1 drivers +S_0x296f5c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x29f94b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2ce5f50/d .functor AND 1, L_0x2ce6010, L_0x2ce6280, C4<1>, C4<1>; +L_0x2ce5f50 .delay 1 (30000,30000,30000) L_0x2ce5f50/d; +v0x29cb4e0_0 .net *"_s0", 0 0, L_0x2ce6010; 1 drivers +v0x29cb150_0 .net *"_s1", 0 0, L_0x2ce6280; 1 drivers +S_0x296e020 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x29f9570 .param/l "i" 0 4 54, +C4<0101>; +L_0x2ce6320/d .functor AND 1, L_0x2ce6390, L_0x2ce64f0, C4<1>, C4<1>; +L_0x2ce6320 .delay 1 (30000,30000,30000) L_0x2ce6320/d; +v0x29c84a0_0 .net *"_s0", 0 0, L_0x2ce6390; 1 drivers +v0x29d76e0_0 .net *"_s1", 0 0, L_0x2ce64f0; 1 drivers +S_0x294aa80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x29c85a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2ce6650/d .functor AND 1, L_0x2ce6710, L_0x2ce6870, C4<1>, C4<1>; +L_0x2ce6650 .delay 1 (30000,30000,30000) L_0x2ce6650/d; +v0x29d4bc0_0 .net *"_s0", 0 0, L_0x2ce6710; 1 drivers +v0x29b4eb0_0 .net *"_s1", 0 0, L_0x2ce6870; 1 drivers +S_0x29494e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2a4a0f0; + .timescale -9 -12; +P_0x29944b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2ce65e0/d .functor AND 1, L_0x2ce6d20, L_0x2ce6f10, C4<1>, C4<1>; +L_0x2ce65e0 .delay 1 (30000,30000,30000) L_0x2ce65e0/d; +v0x2992f20_0 .net *"_s0", 0 0, L_0x2ce6d20; 1 drivers +v0x29a6b10_0 .net *"_s1", 0 0, L_0x2ce6f10; 1 drivers +S_0x2925f70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2a4b690; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x120ba70/d .functor OR 1, L_0x120bb30, L_0x120bce0, C4<0>, C4<0>; -L_0x120ba70 .delay 1 (30000,30000,30000) L_0x120ba70/d; -v0xe42e00_0 .net *"_s10", 0 0, L_0x120bb30; 1 drivers -v0xe185d0_0 .net *"_s12", 0 0, L_0x120bce0; 1 drivers -v0xe18240_0 .net "in", 7 0, L_0x1209a70; alias, 1 drivers -v0xe182e0_0 .net "ors", 1 0, L_0x120b890; 1 drivers -v0xe15590_0 .net "out", 0 0, L_0x120ba70; alias, 1 drivers -L_0x120ac60 .part L_0x1209a70, 0, 4; -L_0x120b890 .concat8 [ 1 1 0 0], L_0x120a950, L_0x120b580; -L_0x120b9d0 .part L_0x1209a70, 4, 4; -L_0x120bb30 .part L_0x120b890, 0, 1; -L_0x120bce0 .part L_0x120b890, 1, 1; -S_0xf118e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xf12e80; +L_0x2ce8960/d .functor OR 1, L_0x2ce8a20, L_0x2ce8bd0, C4<0>, C4<0>; +L_0x2ce8960 .delay 1 (30000,30000,30000) L_0x2ce8960/d; +v0x2920040_0 .net *"_s10", 0 0, L_0x2ce8a20; 1 drivers +v0x291d350_0 .net *"_s12", 0 0, L_0x2ce8bd0; 1 drivers +v0x28ef2a0_0 .net "in", 7 0, L_0x2ce6960; alias, 1 drivers +v0x28ef340_0 .net "ors", 1 0, L_0x2ce8780; 1 drivers +v0x28eef10_0 .net "out", 0 0, L_0x2ce8960; alias, 1 drivers +L_0x2ce7b50 .part L_0x2ce6960, 0, 4; +L_0x2ce8780 .concat8 [ 1 1 0 0], L_0x2ce7840, L_0x2ce8470; +L_0x2ce88c0 .part L_0x2ce6960, 4, 4; +L_0x2ce8a20 .part L_0x2ce8780, 0, 1; +L_0x2ce8bd0 .part L_0x2ce8780, 1, 1; +S_0x2893570 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2925f70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x120a110/d .functor OR 1, L_0x120a1d0, L_0x120a330, C4<0>, C4<0>; -L_0x120a110 .delay 1 (30000,30000,30000) L_0x120a110/d; -L_0x120a560/d .functor OR 1, L_0x120a670, L_0x120a7d0, C4<0>, C4<0>; -L_0x120a560 .delay 1 (30000,30000,30000) L_0x120a560/d; -L_0x120a950/d .functor OR 1, L_0x120a9c0, L_0x120ab70, C4<0>, C4<0>; -L_0x120a950 .delay 1 (30000,30000,30000) L_0x120a950/d; -v0xea9920_0 .net *"_s0", 0 0, L_0x120a110; 1 drivers -v0xea94e0_0 .net *"_s10", 0 0, L_0x120a670; 1 drivers -v0xea67f0_0 .net *"_s12", 0 0, L_0x120a7d0; 1 drivers -v0xea68b0_0 .net *"_s14", 0 0, L_0x120a9c0; 1 drivers -v0xe7be80_0 .net *"_s16", 0 0, L_0x120ab70; 1 drivers -v0xe7baf0_0 .net *"_s3", 0 0, L_0x120a1d0; 1 drivers -v0xe78e40_0 .net *"_s5", 0 0, L_0x120a330; 1 drivers -v0xe88570_0 .net *"_s6", 0 0, L_0x120a560; 1 drivers -v0xe88130_0 .net "in", 3 0, L_0x120ac60; 1 drivers -v0xe85440_0 .net "ors", 1 0, L_0x120a470; 1 drivers -v0xe5ab40_0 .net "out", 0 0, L_0x120a950; 1 drivers -L_0x120a1d0 .part L_0x120ac60, 0, 1; -L_0x120a330 .part L_0x120ac60, 1, 1; -L_0x120a470 .concat8 [ 1 1 0 0], L_0x120a110, L_0x120a560; -L_0x120a670 .part L_0x120ac60, 2, 1; -L_0x120a7d0 .part L_0x120ac60, 3, 1; -L_0x120a9c0 .part L_0x120a470, 0, 1; -L_0x120ab70 .part L_0x120a470, 1, 1; -S_0xef1ae0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xf12e80; +L_0x2ce7000/d .functor OR 1, L_0x2ce70c0, L_0x2ce7220, C4<0>, C4<0>; +L_0x2ce7000 .delay 1 (30000,30000,30000) L_0x2ce7000/d; +L_0x2ce7450/d .functor OR 1, L_0x2ce7560, L_0x2ce76c0, C4<0>, C4<0>; +L_0x2ce7450 .delay 1 (30000,30000,30000) L_0x2ce7450/d; +L_0x2ce7840/d .functor OR 1, L_0x2ce78b0, L_0x2ce7a60, C4<0>, C4<0>; +L_0x2ce7840 .delay 1 (30000,30000,30000) L_0x2ce7840/d; +v0x298e760_0 .net *"_s0", 0 0, L_0x2ce7000; 1 drivers +v0x298e3d0_0 .net *"_s10", 0 0, L_0x2ce7560; 1 drivers +v0x298b720_0 .net *"_s12", 0 0, L_0x2ce76c0; 1 drivers +v0x298b7e0_0 .net *"_s14", 0 0, L_0x2ce78b0; 1 drivers +v0x294ad90_0 .net *"_s16", 0 0, L_0x2ce7a60; 1 drivers +v0x2949820_0 .net *"_s3", 0 0, L_0x2ce70c0; 1 drivers +v0x294ce10_0 .net *"_s5", 0 0, L_0x2ce7220; 1 drivers +v0x295d280_0 .net *"_s6", 0 0, L_0x2ce7450; 1 drivers +v0x295ce40_0 .net "in", 3 0, L_0x2ce7b50; 1 drivers +v0x295a150_0 .net "ors", 1 0, L_0x2ce7360; 1 drivers +v0x2969ba0_0 .net "out", 0 0, L_0x2ce7840; 1 drivers +L_0x2ce70c0 .part L_0x2ce7b50, 0, 1; +L_0x2ce7220 .part L_0x2ce7b50, 1, 1; +L_0x2ce7360 .concat8 [ 1 1 0 0], L_0x2ce7000, L_0x2ce7450; +L_0x2ce7560 .part L_0x2ce7b50, 2, 1; +L_0x2ce76c0 .part L_0x2ce7b50, 3, 1; +L_0x2ce78b0 .part L_0x2ce7360, 0, 1; +L_0x2ce7a60 .part L_0x2ce7360, 1, 1; +S_0x2891fd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2925f70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x120ad90/d .functor OR 1, L_0x120ae00, L_0x120af60, C4<0>, C4<0>; -L_0x120ad90 .delay 1 (30000,30000,30000) L_0x120ad90/d; -L_0x120b190/d .functor OR 1, L_0x120b2a0, L_0x120b400, C4<0>, C4<0>; -L_0x120b190 .delay 1 (30000,30000,30000) L_0x120b190/d; -L_0x120b580/d .functor OR 1, L_0x120b5f0, L_0x120b7a0, C4<0>, C4<0>; -L_0x120b580 .delay 1 (30000,30000,30000) L_0x120b580/d; -v0xe5a7b0_0 .net *"_s0", 0 0, L_0x120ad90; 1 drivers -v0xe57b00_0 .net *"_s10", 0 0, L_0x120b2a0; 1 drivers -v0xe67240_0 .net *"_s12", 0 0, L_0x120b400; 1 drivers -v0xe67300_0 .net *"_s14", 0 0, L_0x120b5f0; 1 drivers -v0xe66e00_0 .net *"_s16", 0 0, L_0x120b7a0; 1 drivers -v0xe64110_0 .net *"_s3", 0 0, L_0x120ae00; 1 drivers -v0xe39850_0 .net *"_s5", 0 0, L_0x120af60; 1 drivers -v0xe394c0_0 .net *"_s6", 0 0, L_0x120b190; 1 drivers -v0xe36810_0 .net "in", 3 0, L_0x120b9d0; 1 drivers -v0xe45f30_0 .net "ors", 1 0, L_0x120b0a0; 1 drivers -v0xe45af0_0 .net "out", 0 0, L_0x120b580; 1 drivers -L_0x120ae00 .part L_0x120b9d0, 0, 1; -L_0x120af60 .part L_0x120b9d0, 1, 1; -L_0x120b0a0 .concat8 [ 1 1 0 0], L_0x120ad90, L_0x120b190; -L_0x120b2a0 .part L_0x120b9d0, 2, 1; -L_0x120b400 .part L_0x120b9d0, 3, 1; -L_0x120b5f0 .part L_0x120b0a0, 0, 1; -L_0x120b7a0 .part L_0x120b0a0, 1, 1; -S_0xef0540 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xeed4d0; +L_0x2ce7c80/d .functor OR 1, L_0x2ce7cf0, L_0x2ce7e50, C4<0>, C4<0>; +L_0x2ce7c80 .delay 1 (30000,30000,30000) L_0x2ce7c80/d; +L_0x2ce8080/d .functor OR 1, L_0x2ce8190, L_0x2ce82f0, C4<0>, C4<0>; +L_0x2ce8080 .delay 1 (30000,30000,30000) L_0x2ce8080/d; +L_0x2ce8470/d .functor OR 1, L_0x2ce84e0, L_0x2ce8690, C4<0>, C4<0>; +L_0x2ce8470 .delay 1 (30000,30000,30000) L_0x2ce8470/d; +v0x2969810_0 .net *"_s0", 0 0, L_0x2ce7c80; 1 drivers +v0x2966b60_0 .net *"_s10", 0 0, L_0x2ce8190; 1 drivers +v0x2926280_0 .net *"_s12", 0 0, L_0x2ce82f0; 1 drivers +v0x2926340_0 .net *"_s14", 0 0, L_0x2ce84e0; 1 drivers +v0x2928300_0 .net *"_s16", 0 0, L_0x2ce8690; 1 drivers +v0x29382a0_0 .net *"_s3", 0 0, L_0x2ce7cf0; 1 drivers +v0x2944b50_0 .net *"_s5", 0 0, L_0x2ce7e50; 1 drivers +v0x2913cb0_0 .net *"_s6", 0 0, L_0x2ce8080; 1 drivers +v0x2913920_0 .net "in", 3 0, L_0x2ce88c0; 1 drivers +v0x2910c70_0 .net "ors", 1 0, L_0x2ce7f90; 1 drivers +v0x2920480_0 .net "out", 0 0, L_0x2ce8470; 1 drivers +L_0x2ce7cf0 .part L_0x2ce88c0, 0, 1; +L_0x2ce7e50 .part L_0x2ce88c0, 1, 1; +L_0x2ce7f90 .concat8 [ 1 1 0 0], L_0x2ce7c80, L_0x2ce8080; +L_0x2ce8190 .part L_0x2ce88c0, 2, 1; +L_0x2ce82f0 .part L_0x2ce88c0, 3, 1; +L_0x2ce84e0 .part L_0x2ce7f90, 0, 1; +L_0x2ce8690 .part L_0x2ce7f90, 1, 1; +S_0x286e960 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x27d7440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xcd5a00_0 .net "ands", 7 0, L_0x1206030; 1 drivers -v0xc9ab10_0 .net "in", 7 0, L_0x1204490; alias, 1 drivers -v0xc9abd0_0 .net "out", 0 0, L_0x1208030; alias, 1 drivers -v0xcaaf00_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xf00ae0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xef0540; +v0x27fad60_0 .net "ands", 7 0, L_0x2ce2f20; 1 drivers +v0x27fa920_0 .net "in", 7 0, L_0x2ce0e40; alias, 1 drivers +v0x27fa9e0_0 .net "out", 0 0, L_0x2ce4f20; alias, 1 drivers +v0x27f7c30_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x286d3c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x286e960; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xd908a0_0 .net "A", 7 0, L_0x1204490; alias, 1 drivers -v0xd9fac0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xd9cf50_0 .net *"_s0", 0 0, L_0x1204820; 1 drivers -v0xd9d010_0 .net *"_s12", 0 0, L_0x12051e0; 1 drivers -v0xd72590_0 .net *"_s16", 0 0, L_0x1205540; 1 drivers -v0xd72200_0 .net *"_s20", 0 0, L_0x1205970; 1 drivers -v0xd6f550_0 .net *"_s24", 0 0, L_0x1205ca0; 1 drivers -v0xd7bc00_0 .net *"_s28", 0 0, L_0x1205c30; 1 drivers -v0xd51170_0 .net *"_s4", 0 0, L_0x1204bc0; 1 drivers -v0xd50de0_0 .net *"_s8", 0 0, L_0x1204ed0; 1 drivers -v0xd4e130_0 .net "out", 7 0, L_0x1206030; alias, 1 drivers -L_0x1204930 .part L_0x1204490, 0, 1; -L_0x1204b20 .part v0x12010b0_0, 0, 1; -L_0x1204c80 .part L_0x1204490, 1, 1; -L_0x1204de0 .part v0x12010b0_0, 1, 1; -L_0x1204f90 .part L_0x1204490, 2, 1; -L_0x12050f0 .part v0x12010b0_0, 2, 1; -L_0x12052a0 .part L_0x1204490, 3, 1; -L_0x1205400 .part v0x12010b0_0, 3, 1; -L_0x1205600 .part L_0x1204490, 4, 1; -L_0x1205870 .part v0x12010b0_0, 4, 1; -L_0x12059e0 .part L_0x1204490, 5, 1; -L_0x1205b40 .part v0x12010b0_0, 5, 1; -L_0x1205d60 .part L_0x1204490, 6, 1; -L_0x1205ec0 .part v0x12010b0_0, 6, 1; -LS_0x1206030_0_0 .concat8 [ 1 1 1 1], L_0x1204820, L_0x1204bc0, L_0x1204ed0, L_0x12051e0; -LS_0x1206030_0_4 .concat8 [ 1 1 1 1], L_0x1205540, L_0x1205970, L_0x1205ca0, L_0x1205c30; -L_0x1206030 .concat8 [ 4 4 0 0], LS_0x1206030_0_0, LS_0x1206030_0_4; -L_0x12063f0 .part L_0x1204490, 7, 1; -L_0x12065e0 .part v0x12010b0_0, 7, 1; -S_0xddf4b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xe9cf00 .param/l "i" 0 4 54, +C4<00>; -L_0x1204820/d .functor AND 1, L_0x1204930, L_0x1204b20, C4<1>, C4<1>; -L_0x1204820 .delay 1 (30000,30000,30000) L_0x1204820/d; -v0xdf6f20_0 .net *"_s0", 0 0, L_0x1204930; 1 drivers -v0xdf4270_0 .net *"_s1", 0 0, L_0x1204b20; 1 drivers -S_0xdbe150 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xdf4370 .param/l "i" 0 4 54, +C4<01>; -L_0x1204bc0/d .functor AND 1, L_0x1204c80, L_0x1204de0, C4<1>, C4<1>; -L_0x1204bc0 .delay 1 (30000,30000,30000) L_0x1204bc0/d; -v0xe03970_0 .net *"_s0", 0 0, L_0x1204c80; 1 drivers -v0xe03530_0 .net *"_s1", 0 0, L_0x1204de0; 1 drivers -S_0xd7eaf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xe78f20 .param/l "i" 0 4 54, +C4<010>; -L_0x1204ed0/d .functor AND 1, L_0x1204f90, L_0x12050f0, C4<1>, C4<1>; -L_0x1204ed0 .delay 1 (30000,30000,30000) L_0x1204ed0/d; -v0xe00840_0 .net *"_s0", 0 0, L_0x1204f90; 1 drivers -v0xe00900_0 .net *"_s1", 0 0, L_0x12050f0; 1 drivers -S_0xd5d330 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xe57be0 .param/l "i" 0 4 54, +C4<011>; -L_0x12051e0/d .functor AND 1, L_0x12052a0, L_0x1205400, C4<1>, C4<1>; -L_0x12051e0 .delay 1 (30000,30000,30000) L_0x12051e0/d; -v0xdd5f80_0 .net *"_s0", 0 0, L_0x12052a0; 1 drivers -v0xdd5bf0_0 .net *"_s1", 0 0, L_0x1205400; 1 drivers -S_0xc9a7d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xe395a0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1205540/d .functor AND 1, L_0x1205600, L_0x1205870, C4<1>, C4<1>; -L_0x1205540 .delay 1 (30000,30000,30000) L_0x1205540/d; -v0xdd2f40_0 .net *"_s0", 0 0, L_0x1205600; 1 drivers -v0xde21b0_0 .net *"_s1", 0 0, L_0x1205870; 1 drivers -S_0xc7a9b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xe42ee0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1205970/d .functor AND 1, L_0x12059e0, L_0x1205b40, C4<1>, C4<1>; -L_0x1205970 .delay 1 (30000,30000,30000) L_0x1205970/d; -v0xdb4c40_0 .net *"_s0", 0 0, L_0x12059e0; 1 drivers -v0xdb48b0_0 .net *"_s1", 0 0, L_0x1205b40; 1 drivers -S_0xc79410 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xe03a50 .param/l "i" 0 4 54, +C4<0110>; -L_0x1205ca0/d .functor AND 1, L_0x1205d60, L_0x1205ec0, C4<1>, C4<1>; -L_0x1205ca0 .delay 1 (30000,30000,30000) L_0x1205ca0/d; -v0xdb1c00_0 .net *"_s0", 0 0, L_0x1205d60; 1 drivers -v0xdc0e50_0 .net *"_s1", 0 0, L_0x1205ec0; 1 drivers -S_0xc59570 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xf00ae0; - .timescale -9 -12; -P_0xdd3020 .param/l "i" 0 4 54, +C4<0111>; -L_0x1205c30/d .functor AND 1, L_0x12063f0, L_0x12065e0, C4<1>, C4<1>; -L_0x1205c30 .delay 1 (30000,30000,30000) L_0x1205c30/d; -v0xd938e0_0 .net *"_s0", 0 0, L_0x12063f0; 1 drivers -v0xd93550_0 .net *"_s1", 0 0, L_0x12065e0; 1 drivers -S_0xc57fd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xef0540; +v0x286d700_0 .net "A", 7 0, L_0x2ce0e40; alias, 1 drivers +v0x2870cf0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x28812c0_0 .net *"_s0", 0 0, L_0x2ce1710; 1 drivers +v0x2881380_0 .net *"_s12", 0 0, L_0x2ce20d0; 1 drivers +v0x2880e80_0 .net *"_s16", 0 0, L_0x2ce2430; 1 drivers +v0x287e190_0 .net *"_s20", 0 0, L_0x2ce2860; 1 drivers +v0x288db50_0 .net *"_s24", 0 0, L_0x2ce2b90; 1 drivers +v0x288d7c0_0 .net *"_s28", 0 0, L_0x2ce2b20; 1 drivers +v0x288ab10_0 .net *"_s4", 0 0, L_0x2ce1ab0; 1 drivers +v0x284a180_0 .net *"_s8", 0 0, L_0x2ce1dc0; 1 drivers +v0x2848c10_0 .net "out", 7 0, L_0x2ce2f20; alias, 1 drivers +L_0x2ce1820 .part L_0x2ce0e40, 0, 1; +L_0x2ce1a10 .part v0x2cdd2e0_0, 0, 1; +L_0x2ce1b70 .part L_0x2ce0e40, 1, 1; +L_0x2ce1cd0 .part v0x2cdd2e0_0, 1, 1; +L_0x2ce1e80 .part L_0x2ce0e40, 2, 1; +L_0x2ce1fe0 .part v0x2cdd2e0_0, 2, 1; +L_0x2ce2190 .part L_0x2ce0e40, 3, 1; +L_0x2ce22f0 .part v0x2cdd2e0_0, 3, 1; +L_0x2ce24f0 .part L_0x2ce0e40, 4, 1; +L_0x2ce2760 .part v0x2cdd2e0_0, 4, 1; +L_0x2ce28d0 .part L_0x2ce0e40, 5, 1; +L_0x2ce2a30 .part v0x2cdd2e0_0, 5, 1; +L_0x2ce2c50 .part L_0x2ce0e40, 6, 1; +L_0x2ce2db0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2ce2f20_0_0 .concat8 [ 1 1 1 1], L_0x2ce1710, L_0x2ce1ab0, L_0x2ce1dc0, L_0x2ce20d0; +LS_0x2ce2f20_0_4 .concat8 [ 1 1 1 1], L_0x2ce2430, L_0x2ce2860, L_0x2ce2b90, L_0x2ce2b20; +L_0x2ce2f20 .concat8 [ 4 4 0 0], LS_0x2ce2f20_0_0, LS_0x2ce2f20_0_4; +L_0x2ce32e0 .part L_0x2ce0e40, 7, 1; +L_0x2ce34d0 .part v0x2cdd2e0_0, 7, 1; +S_0x2849e70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x2971a30 .param/l "i" 0 4 54, +C4<00>; +L_0x2ce1710/d .functor AND 1, L_0x2ce1820, L_0x2ce1a10, C4<1>, C4<1>; +L_0x2ce1710 .delay 1 (30000,30000,30000) L_0x2ce1710/d; +v0x28f8840_0 .net *"_s0", 0 0, L_0x2ce1820; 1 drivers +v0x28ca900_0 .net *"_s1", 0 0, L_0x2ce1a10; 1 drivers +S_0x28488d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x28caa00 .param/l "i" 0 4 54, +C4<01>; +L_0x2ce1ab0/d .functor AND 1, L_0x2ce1b70, L_0x2ce1cd0, C4<1>, C4<1>; +L_0x2ce1ab0 .delay 1 (30000,30000,30000) L_0x2ce1ab0/d; +v0x28ca570_0 .net *"_s0", 0 0, L_0x2ce1b70; 1 drivers +v0x28c78c0_0 .net *"_s1", 0 0, L_0x2ce1cd0; 1 drivers +S_0x27d31b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x2949900 .param/l "i" 0 4 54, +C4<010>; +L_0x2ce1dc0/d .functor AND 1, L_0x2ce1e80, L_0x2ce1fe0, C4<1>, C4<1>; +L_0x2ce1dc0 .delay 1 (30000,30000,30000) L_0x2ce1dc0/d; +v0x28d6ae0_0 .net *"_s0", 0 0, L_0x2ce1e80; 1 drivers +v0x28d6ba0_0 .net *"_s1", 0 0, L_0x2ce1fe0; 1 drivers +S_0x2792a10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x295a230 .param/l "i" 0 4 54, +C4<011>; +L_0x2ce20d0/d .functor AND 1, L_0x2ce2190, L_0x2ce22f0, C4<1>, C4<1>; +L_0x2ce20d0 .delay 1 (30000,30000,30000) L_0x2ce20d0/d; +v0x28d3f70_0 .net *"_s0", 0 0, L_0x2ce2190; 1 drivers +v0x2893880_0 .net *"_s1", 0 0, L_0x2ce22f0; 1 drivers +S_0x2791470 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x2944c30 .param/l "i" 0 4 54, +C4<0100>; +L_0x2ce2430/d .functor AND 1, L_0x2ce24f0, L_0x2ce2760, C4<1>, C4<1>; +L_0x2ce2430 .delay 1 (30000,30000,30000) L_0x2ce2430/d; +v0x2892310_0 .net *"_s0", 0 0, L_0x2ce24f0; 1 drivers +v0x28a5ed0_0 .net *"_s1", 0 0, L_0x2ce2760; 1 drivers +S_0x276de10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x2910d50 .param/l "i" 0 4 54, +C4<0101>; +L_0x2ce2860/d .functor AND 1, L_0x2ce28d0, L_0x2ce2a30, C4<1>, C4<1>; +L_0x2ce2860 .delay 1 (30000,30000,30000) L_0x2ce2860/d; +v0x28a5b40_0 .net *"_s0", 0 0, L_0x2ce28d0; 1 drivers +v0x28a2ce0_0 .net *"_s1", 0 0, L_0x2ce2a30; 1 drivers +S_0x276c870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x291d430 .param/l "i" 0 4 54, +C4<0110>; +L_0x2ce2b90/d .functor AND 1, L_0x2ce2c50, L_0x2ce2db0, C4<1>, C4<1>; +L_0x2ce2b90 .delay 1 (30000,30000,30000) L_0x2ce2b90/d; +v0x28b2580_0 .net *"_s0", 0 0, L_0x2ce2c50; 1 drivers +v0x28b21f0_0 .net *"_s1", 0 0, L_0x2ce2db0; 1 drivers +S_0x2749290 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x286d3c0; + .timescale -9 -12; +P_0x28d4050 .param/l "i" 0 4 54, +C4<0111>; +L_0x2ce2b20/d .functor AND 1, L_0x2ce32e0, L_0x2ce34d0, C4<1>, C4<1>; +L_0x2ce2b20 .delay 1 (30000,30000,30000) L_0x2ce2b20/d; +v0x28af540_0 .net *"_s0", 0 0, L_0x2ce32e0; 1 drivers +v0x286ec70_0 .net *"_s1", 0 0, L_0x2ce34d0; 1 drivers +S_0x2747cf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x286e960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1208030/d .functor OR 1, L_0x12080f0, L_0x12082a0, C4<0>, C4<0>; -L_0x1208030 .delay 1 (30000,30000,30000) L_0x1208030/d; -v0xccbe80_0 .net *"_s10", 0 0, L_0x12080f0; 1 drivers -v0xcc9190_0 .net *"_s12", 0 0, L_0x12082a0; 1 drivers -v0xcd8a40_0 .net "in", 7 0, L_0x1206030; alias, 1 drivers -v0xcd8ae0_0 .net "ors", 1 0, L_0x1207e50; 1 drivers -v0xcd86b0_0 .net "out", 0 0, L_0x1208030; alias, 1 drivers -L_0x1207220 .part L_0x1206030, 0, 4; -L_0x1207e50 .concat8 [ 1 1 0 0], L_0x1206f10, L_0x1207b40; -L_0x1207f90 .part L_0x1206030, 4, 4; -L_0x12080f0 .part L_0x1207e50, 0, 1; -L_0x12082a0 .part L_0x1207e50, 1, 1; -S_0xc380a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xc57fd0; +L_0x2ce4f20/d .functor OR 1, L_0x2ce4fe0, L_0x2ce5190, C4<0>, C4<0>; +L_0x2ce4f20 .delay 1 (30000,30000,30000) L_0x2ce4f20/d; +v0x281c740_0 .net *"_s10", 0 0, L_0x2ce4fe0; 1 drivers +v0x27ee670_0 .net *"_s12", 0 0, L_0x2ce5190; 1 drivers +v0x27ee2e0_0 .net "in", 7 0, L_0x2ce2f20; alias, 1 drivers +v0x27ee380_0 .net "ors", 1 0, L_0x2ce4d40; 1 drivers +v0x27eb630_0 .net "out", 0 0, L_0x2ce4f20; alias, 1 drivers +L_0x2ce4110 .part L_0x2ce2f20, 0, 4; +L_0x2ce4d40 .concat8 [ 1 1 0 0], L_0x2ce3e00, L_0x2ce4a30; +L_0x2ce4e80 .part L_0x2ce2f20, 4, 4; +L_0x2ce4fe0 .part L_0x2ce4d40, 0, 1; +L_0x2ce5190 .part L_0x2ce4d40, 1, 1; +S_0x27246a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2747cf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12066d0/d .functor OR 1, L_0x1206790, L_0x12068f0, C4<0>, C4<0>; -L_0x12066d0 .delay 1 (30000,30000,30000) L_0x12066d0/d; -L_0x1206b20/d .functor OR 1, L_0x1206c30, L_0x1206d90, C4<0>, C4<0>; -L_0x1206b20 .delay 1 (30000,30000,30000) L_0x1206b20/d; -L_0x1206f10/d .functor OR 1, L_0x1206f80, L_0x1207130, C4<0>, C4<0>; -L_0x1206f10 .delay 1 (30000,30000,30000) L_0x1206f10/d; -v0xd5a7e0_0 .net *"_s0", 0 0, L_0x12066d0; 1 drivers -v0xd2fde0_0 .net *"_s10", 0 0, L_0x1206c30; 1 drivers -v0xd2fa50_0 .net *"_s12", 0 0, L_0x1206d90; 1 drivers -v0xd2fb10_0 .net *"_s14", 0 0, L_0x1206f80; 1 drivers -v0xd2cc20_0 .net *"_s16", 0 0, L_0x1207130; 1 drivers -v0xd3c490_0 .net *"_s3", 0 0, L_0x1206790; 1 drivers -v0xd3c100_0 .net *"_s5", 0 0, L_0x12068f0; 1 drivers -v0xd39450_0 .net *"_s6", 0 0, L_0x1206b20; 1 drivers -v0xd1ce50_0 .net "in", 3 0, L_0x1207220; 1 drivers -v0xd0eab0_0 .net "ors", 1 0, L_0x1206a30; 1 drivers -v0xd0e720_0 .net "out", 0 0, L_0x1206f10; 1 drivers -L_0x1206790 .part L_0x1207220, 0, 1; -L_0x12068f0 .part L_0x1207220, 1, 1; -L_0x1206a30 .concat8 [ 1 1 0 0], L_0x12066d0, L_0x1206b20; -L_0x1206c30 .part L_0x1207220, 2, 1; -L_0x1206d90 .part L_0x1207220, 3, 1; -L_0x1206f80 .part L_0x1206a30, 0, 1; -L_0x1207130 .part L_0x1206a30, 1, 1; -S_0xc36b00 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xc57fd0; +L_0x2ce35c0/d .functor OR 1, L_0x2ce3680, L_0x2ce37e0, C4<0>, C4<0>; +L_0x2ce35c0 .delay 1 (30000,30000,30000) L_0x2ce35c0/d; +L_0x2ce3a10/d .functor OR 1, L_0x2ce3b20, L_0x2ce3c80, C4<0>, C4<0>; +L_0x2ce3a10 .delay 1 (30000,30000,30000) L_0x2ce3a10/d; +L_0x2ce3e00/d .functor OR 1, L_0x2ce3e70, L_0x2ce4020, C4<0>, C4<0>; +L_0x2ce3e00 .delay 1 (30000,30000,30000) L_0x2ce3e00/d; +v0x284c200_0 .net *"_s0", 0 0, L_0x2ce35c0; 1 drivers +v0x285c610_0 .net *"_s10", 0 0, L_0x2ce3b20; 1 drivers +v0x285c1d0_0 .net *"_s12", 0 0, L_0x2ce3c80; 1 drivers +v0x285c290_0 .net *"_s14", 0 0, L_0x2ce3e70; 1 drivers +v0x28594e0_0 .net *"_s16", 0 0, L_0x2ce4020; 1 drivers +v0x2868f40_0 .net *"_s3", 0 0, L_0x2ce3680; 1 drivers +v0x2868bb0_0 .net *"_s5", 0 0, L_0x2ce37e0; 1 drivers +v0x2865f00_0 .net *"_s6", 0 0, L_0x2ce3a10; 1 drivers +v0x28255f0_0 .net "in", 3 0, L_0x2ce4110; 1 drivers +v0x2825300_0 .net "ors", 1 0, L_0x2ce3920; 1 drivers +v0x2824080_0 .net "out", 0 0, L_0x2ce3e00; 1 drivers +L_0x2ce3680 .part L_0x2ce4110, 0, 1; +L_0x2ce37e0 .part L_0x2ce4110, 1, 1; +L_0x2ce3920 .concat8 [ 1 1 0 0], L_0x2ce35c0, L_0x2ce3a10; +L_0x2ce3b20 .part L_0x2ce4110, 2, 1; +L_0x2ce3c80 .part L_0x2ce4110, 3, 1; +L_0x2ce3e70 .part L_0x2ce3920, 0, 1; +L_0x2ce4020 .part L_0x2ce3920, 1, 1; +S_0x2723100 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2747cf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1207350/d .functor OR 1, L_0x12073c0, L_0x1207520, C4<0>, C4<0>; -L_0x1207350 .delay 1 (30000,30000,30000) L_0x1207350/d; -L_0x1207750/d .functor OR 1, L_0x1207860, L_0x12079c0, C4<0>, C4<0>; -L_0x1207750 .delay 1 (30000,30000,30000) L_0x1207750/d; -L_0x1207b40/d .functor OR 1, L_0x1207bb0, L_0x1207d60, C4<0>, C4<0>; -L_0x1207b40 .delay 1 (30000,30000,30000) L_0x1207b40/d; -v0xd0b8a0_0 .net *"_s0", 0 0, L_0x1207350; 1 drivers -v0xd1b160_0 .net *"_s10", 0 0, L_0x1207860; 1 drivers -v0xd1add0_0 .net *"_s12", 0 0, L_0x12079c0; 1 drivers -v0xd1ae90_0 .net *"_s14", 0 0, L_0x1207bb0; 1 drivers -v0xd18120_0 .net *"_s16", 0 0, L_0x1207d60; 1 drivers -v0xced720_0 .net *"_s3", 0 0, L_0x12073c0; 1 drivers -v0xced390_0 .net *"_s5", 0 0, L_0x1207520; 1 drivers -v0xcea520_0 .net *"_s6", 0 0, L_0x1207750; 1 drivers -v0xcf9dd0_0 .net "in", 3 0, L_0x1207f90; 1 drivers -v0xcf9a40_0 .net "ors", 1 0, L_0x1207660; 1 drivers -v0xcf6d90_0 .net "out", 0 0, L_0x1207b40; 1 drivers -L_0x12073c0 .part L_0x1207f90, 0, 1; -L_0x1207520 .part L_0x1207f90, 1, 1; -L_0x1207660 .concat8 [ 1 1 0 0], L_0x1207350, L_0x1207750; -L_0x1207860 .part L_0x1207f90, 2, 1; -L_0x12079c0 .part L_0x1207f90, 3, 1; -L_0x1207bb0 .part L_0x1207660, 0, 1; -L_0x1207d60 .part L_0x1207660, 1, 1; -S_0xc16c70 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xeed4d0; +L_0x2ce4240/d .functor OR 1, L_0x2ce42b0, L_0x2ce4410, C4<0>, C4<0>; +L_0x2ce4240 .delay 1 (30000,30000,30000) L_0x2ce4240/d; +L_0x2ce4640/d .functor OR 1, L_0x2ce4750, L_0x2ce48b0, C4<0>, C4<0>; +L_0x2ce4640 .delay 1 (30000,30000,30000) L_0x2ce4640/d; +L_0x2ce4a30/d .functor OR 1, L_0x2ce4aa0, L_0x2ce4c50, C4<0>, C4<0>; +L_0x2ce4a30 .delay 1 (30000,30000,30000) L_0x2ce4a30/d; +v0x2827690_0 .net *"_s0", 0 0, L_0x2ce4240; 1 drivers +v0x2837680_0 .net *"_s10", 0 0, L_0x2ce4750; 1 drivers +v0x28349b0_0 .net *"_s12", 0 0, L_0x2ce48b0; 1 drivers +v0x2834a70_0 .net *"_s14", 0 0, L_0x2ce4aa0; 1 drivers +v0x2844370_0 .net *"_s16", 0 0, L_0x2ce4c50; 1 drivers +v0x2843f30_0 .net *"_s3", 0 0, L_0x2ce42b0; 1 drivers +v0x28130b0_0 .net *"_s5", 0 0, L_0x2ce4410; 1 drivers +v0x2812d20_0 .net *"_s6", 0 0, L_0x2ce4640; 1 drivers +v0x2810070_0 .net "in", 3 0, L_0x2ce4e80; 1 drivers +v0x281f870_0 .net "ors", 1 0, L_0x2ce4550; 1 drivers +v0x281f430_0 .net "out", 0 0, L_0x2ce4a30; 1 drivers +L_0x2ce42b0 .part L_0x2ce4e80, 0, 1; +L_0x2ce4410 .part L_0x2ce4e80, 1, 1; +L_0x2ce4550 .concat8 [ 1 1 0 0], L_0x2ce4240, L_0x2ce4640; +L_0x2ce4750 .part L_0x2ce4e80, 2, 1; +L_0x2ce48b0 .part L_0x2ce4e80, 3, 1; +L_0x2ce4aa0 .part L_0x2ce4550, 0, 1; +L_0x2ce4c50 .part L_0x2ce4550, 1, 1; +S_0x27122f0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x27d7440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -718,72 +751,72 @@ S_0xc16c70 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xeed4d0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1203800/d .functor XNOR 1, L_0x120bed0, L_0x120c030, C4<0>, C4<0>; -L_0x1203800 .delay 1 (20000,20000,20000) L_0x1203800/d; -L_0x1203a70/d .functor AND 1, L_0x120bed0, L_0x1202460, C4<1>, C4<1>; -L_0x1203a70 .delay 1 (30000,30000,30000) L_0x1203a70/d; -L_0x1203ae0/d .functor AND 1, L_0x1203800, L_0x120c120, C4<1>, C4<1>; -L_0x1203ae0 .delay 1 (30000,30000,30000) L_0x1203ae0/d; -L_0x1203c40/d .functor OR 1, L_0x1203ae0, L_0x1203a70, C4<0>, C4<0>; -L_0x1203c40 .delay 1 (30000,30000,30000) L_0x1203c40/d; -v0xcaab60_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers -v0xca7dd0_0 .net "a_", 0 0, L_0x1202350; alias, 1 drivers -v0xca7e70_0 .net "b", 0 0, L_0x120c030; alias, 1 drivers -v0xcb76f0_0 .net "b_", 0 0, L_0x1202460; alias, 1 drivers -v0xcb7790_0 .net "carryin", 0 0, L_0x120c120; alias, 1 drivers -v0xcb7360_0 .net "eq", 0 0, L_0x1203800; 1 drivers -v0xcb7400_0 .net "lt", 0 0, L_0x1203a70; 1 drivers -v0xcb46b0_0 .net "out", 0 0, L_0x1203c40; 1 drivers -v0xcb4750_0 .net "w0", 0 0, L_0x1203ae0; 1 drivers -S_0xc156d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xeed4d0; +L_0x2cdfc30/d .functor XNOR 1, L_0x2ce8dc0, L_0x2ce8f20, C4<0>, C4<0>; +L_0x2cdfc30 .delay 1 (20000,20000,20000) L_0x2cdfc30/d; +L_0x2cdfdb0/d .functor AND 1, L_0x2ce8dc0, L_0x2cde690, C4<1>, C4<1>; +L_0x2cdfdb0 .delay 1 (30000,30000,30000) L_0x2cdfdb0/d; +L_0x2cdff10/d .functor AND 1, L_0x2cdfc30, L_0x2ce8fc0, C4<1>, C4<1>; +L_0x2cdff10 .delay 1 (30000,30000,30000) L_0x2cdff10/d; +L_0x2ce0020/d .functor OR 1, L_0x2cdff10, L_0x2cdfdb0, C4<0>, C4<0>; +L_0x2ce0020 .delay 1 (30000,30000,30000) L_0x2ce0020/d; +v0x27c9d40_0 .net "a", 0 0, L_0x2ce8dc0; alias, 1 drivers +v0x27c9910_0 .net "a_", 0 0, L_0x2cde580; alias, 1 drivers +v0x27c99b0_0 .net "b", 0 0, L_0x2ce8f20; alias, 1 drivers +v0x27c6c60_0 .net "b_", 0 0, L_0x2cde690; alias, 1 drivers +v0x27c6d00_0 .net "carryin", 0 0, L_0x2ce8fc0; alias, 1 drivers +v0x27d5eb0_0 .net "eq", 0 0, L_0x2cdfc30; 1 drivers +v0x27d5f50_0 .net "lt", 0 0, L_0x2cdfdb0; 1 drivers +v0x2792d20_0 .net "out", 0 0, L_0x2ce0020; 1 drivers +v0x2792dc0_0 .net "w0", 0 0, L_0x2cdff10; 1 drivers +S_0x2690730 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x27d7440; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1203540/d .functor OR 1, L_0x1202f80, L_0x1203430, C4<0>, C4<0>; -L_0x1203540 .delay 1 (30000,30000,30000) L_0x1203540/d; -v0xc95fc0_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers -v0xc93310_0 .net "b", 0 0, L_0x1202460; alias, 1 drivers -v0xc933d0_0 .net "c1", 0 0, L_0x1202f80; 1 drivers -v0xc59880_0 .net "c2", 0 0, L_0x1203430; 1 drivers -v0xc59920_0 .net "carryin", 0 0, L_0x120c120; alias, 1 drivers -v0xc687a0_0 .net "carryout", 0 0, L_0x1203540; 1 drivers -v0xc682d0_0 .net "s1", 0 0, L_0x1202e20; 1 drivers -v0xc68370_0 .net "sum", 0 0, L_0x1203130; 1 drivers -S_0xbf57f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xc156d0; +L_0x2cdf7c0/d .functor OR 1, L_0x2cdf200, L_0x2cdf6b0, C4<0>, C4<0>; +L_0x2cdf7c0 .delay 1 (30000,30000,30000) L_0x2cdf7c0/d; +v0x27ae8f0_0 .net "a", 0 0, L_0x2ce8dc0; alias, 1 drivers +v0x276e120_0 .net "b", 0 0, L_0x2cde690; alias, 1 drivers +v0x276e1e0_0 .net "c1", 0 0, L_0x2cdf200; 1 drivers +v0x276cbb0_0 .net "c2", 0 0, L_0x2cdf6b0; 1 drivers +v0x276cc50_0 .net "carryin", 0 0, L_0x2ce8fc0; alias, 1 drivers +v0x2770230_0 .net "carryout", 0 0, L_0x2cdf7c0; 1 drivers +v0x2780750_0 .net "s1", 0 0, L_0x2cdf0a0; 1 drivers +v0x27807f0_0 .net "sum", 0 0, L_0x2cdf3b0; 1 drivers +S_0x266d250 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2690730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1202e20/d .functor XOR 1, L_0x120bed0, L_0x1202460, C4<0>, C4<0>; -L_0x1202e20 .delay 1 (30000,30000,30000) L_0x1202e20/d; -L_0x1202f80/d .functor AND 1, L_0x120bed0, L_0x1202460, C4<1>, C4<1>; -L_0x1202f80 .delay 1 (30000,30000,30000) L_0x1202f80/d; -v0xc89b30_0 .net "a", 0 0, L_0x120bed0; alias, 1 drivers -v0xc89bf0_0 .net "b", 0 0, L_0x1202460; alias, 1 drivers -v0xc896f0_0 .net "carryout", 0 0, L_0x1202f80; alias, 1 drivers -v0xc89790_0 .net "sum", 0 0, L_0x1202e20; alias, 1 drivers -S_0xbf4250 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xc156d0; +L_0x2cdf0a0/d .functor XOR 1, L_0x2ce8dc0, L_0x2cde690, C4<0>, C4<0>; +L_0x2cdf0a0 .delay 1 (30000,30000,30000) L_0x2cdf0a0/d; +L_0x2cdf200/d .functor AND 1, L_0x2ce8dc0, L_0x2cde690, C4<1>, C4<1>; +L_0x2cdf200 .delay 1 (30000,30000,30000) L_0x2cdf200/d; +v0x27a5280_0 .net "a", 0 0, L_0x2ce8dc0; alias, 1 drivers +v0x27a5340_0 .net "b", 0 0, L_0x2cde690; alias, 1 drivers +v0x27a4ef0_0 .net "carryout", 0 0, L_0x2cdf200; alias, 1 drivers +v0x27a4f90_0 .net "sum", 0 0, L_0x2cdf0a0; alias, 1 drivers +S_0x266bcb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2690730; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1203130/d .functor XOR 1, L_0x1202e20, L_0x120c120, C4<0>, C4<0>; -L_0x1203130 .delay 1 (30000,30000,30000) L_0x1203130/d; -L_0x1203430/d .functor AND 1, L_0x1202e20, L_0x120c120, C4<1>, C4<1>; -L_0x1203430 .delay 1 (30000,30000,30000) L_0x1203430/d; -v0xc86a00_0 .net "a", 0 0, L_0x1202e20; alias, 1 drivers -v0xc86ac0_0 .net "b", 0 0, L_0x120c120; alias, 1 drivers -v0xc96350_0 .net "carryout", 0 0, L_0x1203430; alias, 1 drivers -v0xc963f0_0 .net "sum", 0 0, L_0x1203130; alias, 1 drivers -S_0xbd4310 .scope generate, "alu_slices[1]" "alu_slices[1]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0xced470 .param/l "i" 0 3 41, +C4<01>; -S_0xbd2d70 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xbd4310; +L_0x2cdf3b0/d .functor XOR 1, L_0x2cdf0a0, L_0x2ce8fc0, C4<0>, C4<0>; +L_0x2cdf3b0 .delay 1 (30000,30000,30000) L_0x2cdf3b0/d; +L_0x2cdf6b0/d .functor AND 1, L_0x2cdf0a0, L_0x2ce8fc0, C4<1>, C4<1>; +L_0x2cdf6b0 .delay 1 (30000,30000,30000) L_0x2cdf6b0/d; +v0x27b1930_0 .net "a", 0 0, L_0x2cdf0a0; alias, 1 drivers +v0x27b19f0_0 .net "b", 0 0, L_0x2ce8fc0; alias, 1 drivers +v0x27b15a0_0 .net "carryout", 0 0, L_0x2cdf6b0; alias, 1 drivers +v0x27b1640_0 .net "sum", 0 0, L_0x2cdf3b0; alias, 1 drivers +S_0x2648650 .scope generate, "alu_slices[1]" "alu_slices[1]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2813190 .param/l "i" 0 3 39, +C4<01>; +S_0x26470b0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2648650; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -792,445 +825,476 @@ S_0xbd2d70 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xbd4310; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x120c1c0/d .functor NOT 1, L_0x12159e0, C4<0>, C4<0>, C4<0>; -L_0x120c1c0 .delay 1 (10000,10000,10000) L_0x120c1c0/d; -L_0x120c2d0/d .functor NOT 1, L_0x1215b40, C4<0>, C4<0>, C4<0>; -L_0x120c2d0 .delay 1 (10000,10000,10000) L_0x120c2d0/d; -L_0x120d320/d .functor XOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; -L_0x120d320 .delay 1 (30000,30000,30000) L_0x120d320/d; -L_0x2b0ab3d050a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d050f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x120d9d0/d .functor OR 1, L_0x2b0ab3d050a8, L_0x2b0ab3d050f0, C4<0>, C4<0>; -L_0x120d9d0 .delay 1 (30000,30000,30000) L_0x120d9d0/d; -L_0x120dbd0/d .functor AND 1, L_0x12159e0, L_0x1215b40, C4<1>, C4<1>; -L_0x120dbd0 .delay 1 (30000,30000,30000) L_0x120dbd0/d; -L_0x120dc90/d .functor NAND 1, L_0x12159e0, L_0x1215b40, C4<1>, C4<1>; -L_0x120dc90 .delay 1 (20000,20000,20000) L_0x120dc90/d; -L_0x120ddf0/d .functor XOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; -L_0x120ddf0 .delay 1 (20000,20000,20000) L_0x120ddf0/d; -L_0x120e2a0/d .functor OR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; -L_0x120e2a0 .delay 1 (30000,30000,30000) L_0x120e2a0/d; -L_0x12158e0/d .functor NOT 1, L_0x1211a70, C4<0>, C4<0>, C4<0>; -L_0x12158e0 .delay 1 (10000,10000,10000) L_0x12158e0/d; -v0xcc9750_0 .net "A", 0 0, L_0x12159e0; 1 drivers -v0xcb97d0_0 .net "A_", 0 0, L_0x120c1c0; 1 drivers -v0xcb9890_0 .net "B", 0 0, L_0x1215b40; 1 drivers -v0xcb9450_0 .net "B_", 0 0, L_0x120c2d0; 1 drivers -v0xcb94f0_0 .net *"_s12", 0 0, L_0x120d9d0; 1 drivers -v0xca82f0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d050a8; 1 drivers -v0xca83b0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d050f0; 1 drivers -v0xc98430_0 .net *"_s18", 0 0, L_0x120dbd0; 1 drivers -v0xc98510_0 .net *"_s20", 0 0, L_0x120dc90; 1 drivers -v0xc98160_0 .net *"_s22", 0 0, L_0x120ddf0; 1 drivers -v0xc86f20_0 .net *"_s24", 0 0, L_0x120e2a0; 1 drivers -o0x2b0ab3ca7818 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0xc87000_0 name=_s30 -o0x2b0ab3ca7848 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0xc77070_0 name=_s32 -v0xc77130_0 .net *"_s8", 0 0, L_0x120d320; 1 drivers -v0xc76cf0_0 .net "carryin", 0 0, L_0x1215be0; 1 drivers -v0xc76d90_0 .net "carryout", 0 0, L_0x1215580; 1 drivers -v0xc65b00_0 .net "carryouts", 7 0, L_0x13530f0; 1 drivers -v0xc65ba0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0xc558b0_0 .net "result", 0 0, L_0x1211a70; 1 drivers -v0xc559a0_0 .net "results", 7 0, L_0x120e070; 1 drivers -v0xc44660_0 .net "zero", 0 0, L_0x12158e0; 1 drivers -LS_0x120e070_0_0 .concat8 [ 1 1 1 1], L_0x120c7f0, L_0x120ce20, L_0x120d320, L_0x120d9d0; -LS_0x120e070_0_4 .concat8 [ 1 1 1 1], L_0x120dbd0, L_0x120dc90, L_0x120ddf0, L_0x120e2a0; -L_0x120e070 .concat8 [ 4 4 0 0], LS_0x120e070_0_0, LS_0x120e070_0_4; -LS_0x13530f0_0_0 .concat [ 1 1 1 1], L_0x120caa0, L_0x120d1c0, o0x2b0ab3ca7818, L_0x120d820; -LS_0x13530f0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ca7848; -L_0x13530f0 .concat [ 4 4 0 0], LS_0x13530f0_0_0, LS_0x13530f0_0_4; -S_0xbb2ed0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xbd2d70; +L_0x2cdeb60/d .functor NOT 1, L_0x2cf3660, C4<0>, C4<0>, C4<0>; +L_0x2cdeb60 .delay 1 (10000,10000,10000) L_0x2cdeb60/d; +L_0x2ce9100/d .functor NOT 1, L_0x2cf37c0, C4<0>, C4<0>, C4<0>; +L_0x2ce9100 .delay 1 (10000,10000,10000) L_0x2ce9100/d; +L_0x2cea150/d .functor XOR 1, L_0x2cf3660, L_0x2cf37c0, C4<0>, C4<0>; +L_0x2cea150 .delay 1 (30000,30000,30000) L_0x2cea150/d; +L_0x2ac6110b6378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b63c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cea210/d .functor OR 1, L_0x2ac6110b6378, L_0x2ac6110b63c0, C4<0>, C4<0>; +L_0x2cea210 .delay 1 (30000,30000,30000) L_0x2cea210/d; +L_0x2ac6110b6408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cea9b0/d .functor OR 1, L_0x2ac6110b6408, L_0x2ac6110b6450, C4<0>, C4<0>; +L_0x2cea9b0 .delay 1 (30000,30000,30000) L_0x2cea9b0/d; +L_0x2ceabb0/d .functor AND 1, L_0x2cf3660, L_0x2cf37c0, C4<1>, C4<1>; +L_0x2ceabb0 .delay 1 (30000,30000,30000) L_0x2ceabb0/d; +L_0x2ac6110b6498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b64e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ceac70/d .functor OR 1, L_0x2ac6110b6498, L_0x2ac6110b64e0, C4<0>, C4<0>; +L_0x2ceac70 .delay 1 (30000,30000,30000) L_0x2ceac70/d; +L_0x2ceaf30/d .functor NAND 1, L_0x2cf3660, L_0x2cf37c0, C4<1>, C4<1>; +L_0x2ceaf30 .delay 1 (20000,20000,20000) L_0x2ceaf30/d; +L_0x2ac6110b6528 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6570 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ceb040/d .functor OR 1, L_0x2ac6110b6528, L_0x2ac6110b6570, C4<0>, C4<0>; +L_0x2ceb040 .delay 1 (30000,30000,30000) L_0x2ceb040/d; +L_0x2ceb1f0/d .functor NOR 1, L_0x2cf3660, L_0x2cf37c0, C4<0>, C4<0>; +L_0x2ceb1f0 .delay 1 (20000,20000,20000) L_0x2ceb1f0/d; +L_0x2ac6110b65b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ceb4c0/d .functor OR 1, L_0x2ac6110b65b8, L_0x2ac6110b6600, C4<0>, C4<0>; +L_0x2ceb4c0 .delay 1 (30000,30000,30000) L_0x2ceb4c0/d; +L_0x2ceb8c0/d .functor OR 1, L_0x2cf3660, L_0x2cf37c0, C4<0>, C4<0>; +L_0x2ceb8c0 .delay 1 (30000,30000,30000) L_0x2ceb8c0/d; +L_0x2ac6110b6648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cebd60/d .functor OR 1, L_0x2ac6110b6648, L_0x2ac6110b6690, C4<0>, C4<0>; +L_0x2cebd60 .delay 1 (30000,30000,30000) L_0x2cebd60/d; +L_0x2cf3510/d .functor NOT 1, L_0x2cef720, C4<0>, C4<0>, C4<0>; +L_0x2cf3510 .delay 1 (10000,10000,10000) L_0x2cf3510/d; +v0x28b4700_0 .net "A", 0 0, L_0x2cf3660; 1 drivers +v0x28b42e0_0 .net "A_", 0 0, L_0x2cdeb60; 1 drivers +v0x28b43a0_0 .net "B", 0 0, L_0x2cf37c0; 1 drivers +v0x28a3200_0 .net "B_", 0 0, L_0x2ce9100; 1 drivers +v0x28a32a0_0 .net *"_s11", 0 0, L_0x2cea210; 1 drivers +v0x288fc30_0 .net/2s *"_s13", 0 0, L_0x2ac6110b6378; 1 drivers +v0x288fcf0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b63c0; 1 drivers +v0x288f8b0_0 .net *"_s19", 0 0, L_0x2cea9b0; 1 drivers +v0x288f990_0 .net/2s *"_s21", 0 0, L_0x2ac6110b6408; 1 drivers +v0x287e760_0 .net/2s *"_s23", 0 0, L_0x2ac6110b6450; 1 drivers +v0x286b020_0 .net *"_s25", 0 0, L_0x2ceabb0; 1 drivers +v0x286b100_0 .net *"_s28", 0 0, L_0x2ceac70; 1 drivers +v0x286aca0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b6498; 1 drivers +v0x286ad60_0 .net/2s *"_s32", 0 0, L_0x2ac6110b64e0; 1 drivers +v0x2859a00_0 .net *"_s34", 0 0, L_0x2ceaf30; 1 drivers +v0x2859ae0_0 .net *"_s37", 0 0, L_0x2ceb040; 1 drivers +v0x2846530_0 .net/2s *"_s39", 0 0, L_0x2ac6110b6528; 1 drivers +v0x28465d0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b6570; 1 drivers +v0x2837a50_0 .net *"_s43", 0 0, L_0x2ceb1f0; 1 drivers +v0x2837b30_0 .net *"_s46", 0 0, L_0x2ceb4c0; 1 drivers +v0x2834eb0_0 .net/2s *"_s48", 0 0, L_0x2ac6110b65b8; 1 drivers +v0x2834f70_0 .net/2s *"_s50", 0 0, L_0x2ac6110b6600; 1 drivers +v0x2841760_0 .net *"_s52", 0 0, L_0x2ceb8c0; 1 drivers +v0x2841840_0 .net *"_s56", 0 0, L_0x2cebd60; 1 drivers +v0x2800980_0 .net/2s *"_s59", 0 0, L_0x2ac6110b6648; 1 drivers +v0x2800a40_0 .net/2s *"_s61", 0 0, L_0x2ac6110b6690; 1 drivers +v0x281cc60_0 .net *"_s8", 0 0, L_0x2cea150; 1 drivers +v0x281cd40_0 .net "carryin", 0 0, L_0x2cf3860; 1 drivers +v0x27dbf30_0 .net "carryout", 0 0, L_0x2cf31b0; 1 drivers +v0x27dc020_0 .net "carryouts", 7 0, L_0x2ceb9d0; 1 drivers +v0x27f8150_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x27f8210_0 .net "result", 0 0, L_0x2cef720; 1 drivers +v0x27b7460_0 .net "results", 7 0, L_0x2ceb690; 1 drivers +v0x27b7500_0 .net "zero", 0 0, L_0x2cf3510; 1 drivers +LS_0x2ceb690_0_0 .concat8 [ 1 1 1 1], L_0x2ce95d0, L_0x2ce9c30, L_0x2cea150, L_0x2cea9b0; +LS_0x2ceb690_0_4 .concat8 [ 1 1 1 1], L_0x2ceabb0, L_0x2ceaf30, L_0x2ceb1f0, L_0x2ceb8c0; +L_0x2ceb690 .concat8 [ 4 4 0 0], LS_0x2ceb690_0_0, LS_0x2ceb690_0_4; +LS_0x2ceb9d0_0_0 .concat8 [ 1 1 1 1], L_0x2ce9920, L_0x2ce9ff0, L_0x2cea210, L_0x2cea800; +LS_0x2ceb9d0_0_4 .concat8 [ 1 1 1 1], L_0x2ceac70, L_0x2ceb040, L_0x2ceb4c0, L_0x2cebd60; +L_0x2ceb9d0 .concat8 [ 4 4 0 0], LS_0x2ceb9d0_0_0, LS_0x2ceb9d0_0_4; +S_0x2623be0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x26470b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x120caa0/d .functor OR 1, L_0x120c580, L_0x120c940, C4<0>, C4<0>; -L_0x120caa0 .delay 1 (30000,30000,30000) L_0x120caa0/d; -v0xc017e0_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers -v0xc01880_0 .net "b", 0 0, L_0x1215b40; alias, 1 drivers -v0xc11250_0 .net "c1", 0 0, L_0x120c580; 1 drivers -v0xc10ec0_0 .net "c2", 0 0, L_0x120c940; 1 drivers -v0xc0e210_0 .net "carryin", 0 0, L_0x1215be0; alias, 1 drivers -v0xc0e2b0_0 .net "carryout", 0 0, L_0x120caa0; 1 drivers -v0xbd30b0_0 .net "s1", 0 0, L_0x120c4c0; 1 drivers -v0xbe34b0_0 .net "sum", 0 0, L_0x120c7f0; 1 drivers -S_0xbb1930 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xbb2ed0; +L_0x2ce9920/d .functor OR 1, L_0x2ce9450, L_0x2ce97c0, C4<0>, C4<0>; +L_0x2ce9920 .delay 1 (30000,30000,30000) L_0x2ce9920/d; +v0x26c6050_0 .net "a", 0 0, L_0x2cf3660; alias, 1 drivers +v0x26c6110_0 .net "b", 0 0, L_0x2cf37c0; alias, 1 drivers +v0x26d52b0_0 .net "c1", 0 0, L_0x2ce9450; 1 drivers +v0x2690a70_0 .net "c2", 0 0, L_0x2ce97c0; 1 drivers +v0x26a4650_0 .net "carryin", 0 0, L_0x2cf3860; alias, 1 drivers +v0x26a42c0_0 .net "carryout", 0 0, L_0x2ce9920; 1 drivers +v0x26a4360_0 .net "s1", 0 0, L_0x2ce92f0; 1 drivers +v0x26a1610_0 .net "sum", 0 0, L_0x2ce95d0; 1 drivers +S_0x2622640 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2623be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x120c4c0/d .functor XOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; -L_0x120c4c0 .delay 1 (30000,30000,30000) L_0x120c4c0/d; -L_0x120c580/d .functor AND 1, L_0x12159e0, L_0x1215b40, C4<1>, C4<1>; -L_0x120c580 .delay 1 (30000,30000,30000) L_0x120c580/d; -v0xc322f0_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers -v0xc2f640_0 .net "b", 0 0, L_0x1215b40; alias, 1 drivers -v0xc2f700_0 .net "carryout", 0 0, L_0x120c580; alias, 1 drivers -v0xbf4590_0 .net "sum", 0 0, L_0x120c4c0; alias, 1 drivers -S_0xb92720 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xbb2ed0; +L_0x2ce92f0/d .functor XOR 1, L_0x2cf3660, L_0x2cf37c0, C4<0>, C4<0>; +L_0x2ce92f0 .delay 1 (30000,30000,30000) L_0x2ce92f0/d; +L_0x2ce9450/d .functor AND 1, L_0x2cf3660, L_0x2cf37c0, C4<1>, C4<1>; +L_0x2ce9450 .delay 1 (30000,30000,30000) L_0x2ce9450/d; +v0x26fa110_0 .net "a", 0 0, L_0x2cf3660; alias, 1 drivers +v0x26f9cd0_0 .net "b", 0 0, L_0x2cf37c0; alias, 1 drivers +v0x26f9d90_0 .net "carryout", 0 0, L_0x2ce9450; alias, 1 drivers +v0x26f6fe0_0 .net "sum", 0 0, L_0x2ce92f0; alias, 1 drivers +S_0x2611650 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2623be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x120c7f0/d .functor XOR 1, L_0x120c4c0, L_0x1215be0, C4<0>, C4<0>; -L_0x120c7f0 .delay 1 (30000,30000,30000) L_0x120c7f0/d; -L_0x120c940/d .functor AND 1, L_0x120c4c0, L_0x1215be0, C4<1>, C4<1>; -L_0x120c940 .delay 1 (30000,30000,30000) L_0x120c940/d; -v0xc04910_0 .net "a", 0 0, L_0x120c4c0; alias, 1 drivers -v0xc049d0_0 .net "b", 0 0, L_0x1215be0; alias, 1 drivers -v0xc044d0_0 .net "carryout", 0 0, L_0x120c940; alias, 1 drivers -v0xc04570_0 .net "sum", 0 0, L_0x120c7f0; alias, 1 drivers -S_0xb91180 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xbd2d70; +L_0x2ce95d0/d .functor XOR 1, L_0x2ce92f0, L_0x2cf3860, C4<0>, C4<0>; +L_0x2ce95d0 .delay 1 (30000,30000,30000) L_0x2ce95d0/d; +L_0x2ce97c0/d .functor AND 1, L_0x2ce92f0, L_0x2cf3860, C4<1>, C4<1>; +L_0x2ce97c0 .delay 1 (30000,30000,30000) L_0x2ce97c0/d; +v0x26c9090_0 .net "a", 0 0, L_0x2ce92f0; alias, 1 drivers +v0x26c9150_0 .net "b", 0 0, L_0x2cf3860; alias, 1 drivers +v0x26c8d00_0 .net "carryout", 0 0, L_0x2ce97c0; alias, 1 drivers +v0x26c8da0_0 .net "sum", 0 0, L_0x2ce95d0; alias, 1 drivers +S_0x25fbe00 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x26470b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xdc2d00_0 .net "ands", 7 0, L_0x1213580; 1 drivers -v0xda20b0_0 .net "in", 7 0, L_0x13530f0; alias, 1 drivers -v0xda2170_0 .net "out", 0 0, L_0x1215580; alias, 1 drivers -v0xda1d20_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xf543d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xb91180; +v0x2922600_0 .net "ands", 7 0, L_0x2cf11b0; 1 drivers +v0x29226c0_0 .net "in", 7 0, L_0x2ceb9d0; alias, 1 drivers +v0x2922270_0 .net "out", 0 0, L_0x2cf31b0; alias, 1 drivers +v0x2922310_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x29a3e10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x25fbe00; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xbaae90_0 .net "A", 7 0, L_0x13530f0; alias, 1 drivers -v0xda0ea0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xda0f60_0 .net *"_s0", 0 0, L_0x1211dd0; 1 drivers -v0xccc350_0 .net *"_s12", 0 0, L_0x1212790; 1 drivers -v0xd7fb00_0 .net *"_s16", 0 0, L_0x1212af0; 1 drivers -v0xecc6f0_0 .net *"_s20", 0 0, L_0x1212e00; 1 drivers -v0xecc7d0_0 .net *"_s24", 0 0, L_0x12131f0; 1 drivers -v0xeabaa0_0 .net *"_s28", 0 0, L_0x1213180; 1 drivers -v0xeabb80_0 .net *"_s4", 0 0, L_0x12120e0; 1 drivers -v0xeab710_0 .net *"_s8", 0 0, L_0x1212480; 1 drivers -v0xeab7f0_0 .net "out", 7 0, L_0x1213580; alias, 1 drivers -L_0x1211e90 .part L_0x13530f0, 0, 1; -L_0x1211ff0 .part v0x12010b0_0, 0, 1; -L_0x12121a0 .part L_0x13530f0, 1, 1; -L_0x1212390 .part v0x12010b0_0, 1, 1; -L_0x1212540 .part L_0x13530f0, 2, 1; -L_0x12126a0 .part v0x12010b0_0, 2, 1; -L_0x1212850 .part L_0x13530f0, 3, 1; -L_0x12129b0 .part v0x12010b0_0, 3, 1; -L_0x1212bb0 .part L_0x13530f0, 4, 1; -L_0x1212d10 .part v0x12010b0_0, 4, 1; -L_0x1212e70 .part L_0x13530f0, 5, 1; -L_0x12130e0 .part v0x12010b0_0, 5, 1; -L_0x12132b0 .part L_0x13530f0, 6, 1; -L_0x1213410 .part v0x12010b0_0, 6, 1; -LS_0x1213580_0_0 .concat8 [ 1 1 1 1], L_0x1211dd0, L_0x12120e0, L_0x1212480, L_0x1212790; -LS_0x1213580_0_4 .concat8 [ 1 1 1 1], L_0x1212af0, L_0x1212e00, L_0x12131f0, L_0x1213180; -L_0x1213580 .concat8 [ 4 4 0 0], LS_0x1213580_0_0, LS_0x1213580_0_4; -L_0x1213940 .part L_0x13530f0, 7, 1; -L_0x1213b30 .part v0x12010b0_0, 7, 1; -S_0xf0f580 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xc538a0 .param/l "i" 0 4 54, +C4<00>; -L_0x1211dd0/d .functor AND 1, L_0x1211e90, L_0x1211ff0, C4<1>, C4<1>; -L_0x1211dd0 .delay 1 (30000,30000,30000) L_0x1211dd0/d; -v0xbe3070_0 .net *"_s0", 0 0, L_0x1211e90; 1 drivers -v0xbe0380_0 .net *"_s1", 0 0, L_0x1211ff0; 1 drivers -S_0xf0f1f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbe0460 .param/l "i" 0 4 54, +C4<01>; -L_0x12120e0/d .functor AND 1, L_0x12121a0, L_0x1212390, C4<1>, C4<1>; -L_0x12120e0 .delay 1 (30000,30000,30000) L_0x12120e0/d; -v0xbefdd0_0 .net *"_s0", 0 0, L_0x12121a0; 1 drivers -v0xbefa40_0 .net *"_s1", 0 0, L_0x1212390; 1 drivers -S_0xf0ee40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbefb20 .param/l "i" 0 4 54, +C4<010>; -L_0x1212480/d .functor AND 1, L_0x1212540, L_0x12126a0, C4<1>, C4<1>; -L_0x1212480 .delay 1 (30000,30000,30000) L_0x1212480/d; -v0xbecde0_0 .net *"_s0", 0 0, L_0x1212540; 1 drivers -v0xbb1c70_0 .net *"_s1", 0 0, L_0x12126a0; 1 drivers -S_0xeee1e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbb45e0 .param/l "i" 0 4 54, +C4<011>; -L_0x1212790/d .functor AND 1, L_0x1212850, L_0x12129b0, C4<1>, C4<1>; -L_0x1212790 .delay 1 (30000,30000,30000) L_0x1212790/d; -v0xbc2020_0 .net *"_s0", 0 0, L_0x1212850; 1 drivers -v0xbc1be0_0 .net *"_s1", 0 0, L_0x12129b0; 1 drivers -S_0xeede50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbc1cc0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1212af0/d .functor AND 1, L_0x1212bb0, L_0x1212d10, C4<1>, C4<1>; -L_0x1212af0 .delay 1 (30000,30000,30000) L_0x1212af0/d; -v0xbbef80_0 .net *"_s0", 0 0, L_0x1212bb0; 1 drivers -v0xbce970_0 .net *"_s1", 0 0, L_0x1212d10; 1 drivers -S_0xeedaa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbce5e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1212e00/d .functor AND 1, L_0x1212e70, L_0x12130e0, C4<1>, C4<1>; -L_0x1212e00 .delay 1 (30000,30000,30000) L_0x1212e00/d; -v0xbcb930_0 .net *"_s0", 0 0, L_0x1212e70; 1 drivers -v0xb914c0_0 .net *"_s1", 0 0, L_0x12130e0; 1 drivers -S_0xecce30 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbcba10 .param/l "i" 0 4 54, +C4<0110>; -L_0x12131f0/d .functor AND 1, L_0x12132b0, L_0x1213410, C4<1>, C4<1>; -L_0x12131f0 .delay 1 (30000,30000,30000) L_0x12131f0/d; -v0xba16e0_0 .net *"_s0", 0 0, L_0x12132b0; 1 drivers -v0xba12a0_0 .net *"_s1", 0 0, L_0x1213410; 1 drivers -S_0xeccaa0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xf543d0; - .timescale -9 -12; -P_0xbae050 .param/l "i" 0 4 54, +C4<0111>; -L_0x1213180/d .functor AND 1, L_0x1213940, L_0x1213b30, C4<1>, C4<1>; -L_0x1213180 .delay 1 (30000,30000,30000) L_0x1213180/d; -v0xbae110_0 .net *"_s0", 0 0, L_0x1213940; 1 drivers -v0xbadcc0_0 .net *"_s1", 0 0, L_0x1213b30; 1 drivers -S_0xe8a6f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xb91180; +v0x265aac0_0 .net "A", 7 0, L_0x2ceb9d0; alias, 1 drivers +v0x2667830_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x26678f0_0 .net *"_s0", 0 0, L_0x2cefa80; 1 drivers +v0x26674a0_0 .net *"_s12", 0 0, L_0x2cf0440; 1 drivers +v0x26647f0_0 .net *"_s16", 0 0, L_0x2cf07a0; 1 drivers +v0x2623ef0_0 .net *"_s20", 0 0, L_0x2cf0b70; 1 drivers +v0x2622980_0 .net *"_s24", 0 0, L_0x2cf0ea0; 1 drivers +v0x2625f70_0 .net *"_s28", 0 0, L_0x2cf0e30; 1 drivers +v0x26362d0_0 .net *"_s4", 0 0, L_0x2cefe20; 1 drivers +v0x2635e90_0 .net *"_s8", 0 0, L_0x2cf0130; 1 drivers +v0x2642c30_0 .net "out", 7 0, L_0x2cf11b0; alias, 1 drivers +L_0x2cefb40 .part L_0x2ceb9d0, 0, 1; +L_0x2cefd30 .part v0x2cdd2e0_0, 0, 1; +L_0x2cefee0 .part L_0x2ceb9d0, 1, 1; +L_0x2cf0040 .part v0x2cdd2e0_0, 1, 1; +L_0x2cf01f0 .part L_0x2ceb9d0, 2, 1; +L_0x2cf0350 .part v0x2cdd2e0_0, 2, 1; +L_0x2cf0500 .part L_0x2ceb9d0, 3, 1; +L_0x2cf0660 .part v0x2cdd2e0_0, 3, 1; +L_0x2cf0860 .part L_0x2ceb9d0, 4, 1; +L_0x2cf0ad0 .part v0x2cdd2e0_0, 4, 1; +L_0x2cf0be0 .part L_0x2ceb9d0, 5, 1; +L_0x2cf0d40 .part v0x2cdd2e0_0, 5, 1; +L_0x2cf0f60 .part L_0x2ceb9d0, 6, 1; +L_0x2cf10c0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2cf11b0_0_0 .concat8 [ 1 1 1 1], L_0x2cefa80, L_0x2cefe20, L_0x2cf0130, L_0x2cf0440; +LS_0x2cf11b0_0_4 .concat8 [ 1 1 1 1], L_0x2cf07a0, L_0x2cf0b70, L_0x2cf0ea0, L_0x2cf0e30; +L_0x2cf11b0 .concat8 [ 4 4 0 0], LS_0x2cf11b0_0_0, LS_0x2cf11b0_0_4; +L_0x2cf1570 .part L_0x2ceb9d0, 7, 1; +L_0x2cf1760 .part v0x2cdd2e0_0, 7, 1; +S_0x277db30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x2768140 .param/l "i" 0 4 54, +C4<00>; +L_0x2cefa80/d .functor AND 1, L_0x2cefb40, L_0x2cefd30, C4<1>, C4<1>; +L_0x2cefa80 .delay 1 (30000,30000,30000) L_0x2cefa80/d; +v0x26b0d00_0 .net *"_s0", 0 0, L_0x2cefb40; 1 drivers +v0x26b0970_0 .net *"_s1", 0 0, L_0x2cefd30; 1 drivers +S_0x27342b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x2736fd0 .param/l "i" 0 4 54, +C4<01>; +L_0x2cefe20/d .functor AND 1, L_0x2cefee0, L_0x2cf0040, C4<1>, C4<1>; +L_0x2cefe20 .delay 1 (30000,30000,30000) L_0x2cefe20/d; +v0x26adcc0_0 .net *"_s0", 0 0, L_0x2cefee0; 1 drivers +v0x266d560_0 .net *"_s1", 0 0, L_0x2cf0040; 1 drivers +S_0x26d2ad0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x27435e0 .param/l "i" 0 4 54, +C4<010>; +L_0x2cf0130/d .functor AND 1, L_0x2cf01f0, L_0x2cf0350, C4<1>, C4<1>; +L_0x2cf0130 .delay 1 (30000,30000,30000) L_0x2cf0130/d; +v0x266bff0_0 .net *"_s0", 0 0, L_0x2cf01f0; 1 drivers +v0x266f5e0_0 .net *"_s1", 0 0, L_0x2cf0350; 1 drivers +S_0x26582e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x270f500 .param/l "i" 0 4 54, +C4<011>; +L_0x2cf0440/d .functor AND 1, L_0x2cf0500, L_0x2cf0660, C4<1>, C4<1>; +L_0x2cf0440 .delay 1 (30000,30000,30000) L_0x2cf0440/d; +v0x267fac0_0 .net *"_s0", 0 0, L_0x2cf0500; 1 drivers +v0x267f680_0 .net *"_s1", 0 0, L_0x2cf0660; 1 drivers +S_0x26336b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x26b0a50 .param/l "i" 0 4 54, +C4<0100>; +L_0x2cf07a0/d .functor AND 1, L_0x2cf0860, L_0x2cf0ad0, C4<1>, C4<1>; +L_0x2cf07a0 .delay 1 (30000,30000,30000) L_0x2cf07a0/d; +v0x267c990_0 .net *"_s0", 0 0, L_0x2cf0860; 1 drivers +v0x268c2b0_0 .net *"_s1", 0 0, L_0x2cf0ad0; 1 drivers +S_0x26d6830 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x266c0d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2cf0b70/d .functor AND 1, L_0x2cf0be0, L_0x2cf0d40, C4<1>, C4<1>; +L_0x2cf0b70 .delay 1 (30000,30000,30000) L_0x2cf0b70/d; +v0x268bf20_0 .net *"_s0", 0 0, L_0x2cf0be0; 1 drivers +v0x2689270_0 .net *"_s1", 0 0, L_0x2cf0d40; 1 drivers +S_0x261ef50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x267f760 .param/l "i" 0 4 54, +C4<0110>; +L_0x2cf0ea0/d .functor AND 1, L_0x2cf0f60, L_0x2cf10c0, C4<1>, C4<1>; +L_0x2cf0ea0 .delay 1 (30000,30000,30000) L_0x2cf0ea0/d; +v0x2648960_0 .net *"_s0", 0 0, L_0x2cf0f60; 1 drivers +v0x26473f0_0 .net *"_s1", 0 0, L_0x2cf10c0; 1 drivers +S_0x2a23200 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x29a3e10; + .timescale -9 -12; +P_0x2689350 .param/l "i" 0 4 54, +C4<0111>; +L_0x2cf0e30/d .functor AND 1, L_0x2cf1570, L_0x2cf1760, C4<1>, C4<1>; +L_0x2cf0e30 .delay 1 (30000,30000,30000) L_0x2cf0e30/d; +v0x264a9e0_0 .net *"_s0", 0 0, L_0x2cf1570; 1 drivers +v0x265af00_0 .net *"_s1", 0 0, L_0x2cf1760; 1 drivers +S_0x2a22e70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x25fbe00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1215580/d .functor OR 1, L_0x1215640, L_0x12157f0, C4<0>, C4<0>; -L_0x1215580 .delay 1 (30000,30000,30000) L_0x1215580/d; -v0xde40a0_0 .net *"_s10", 0 0, L_0x1215640; 1 drivers -v0xdc3440_0 .net *"_s12", 0 0, L_0x12157f0; 1 drivers -v0xdc3520_0 .net "in", 7 0, L_0x1213580; alias, 1 drivers -v0xdc30b0_0 .net "ors", 1 0, L_0x12153a0; 1 drivers -v0xdc3170_0 .net "out", 0 0, L_0x1215580; alias, 1 drivers -L_0x1214770 .part L_0x1213580, 0, 4; -L_0x12153a0 .concat8 [ 1 1 0 0], L_0x1214460, L_0x1215090; -L_0x12154e0 .part L_0x1213580, 4, 4; -L_0x1215640 .part L_0x12153a0, 0, 1; -L_0x12157f0 .part L_0x12153a0, 1, 1; -S_0xe8a360 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xe8a6f0; +L_0x2cf31b0/d .functor OR 1, L_0x2cf3270, L_0x2cf3420, C4<0>, C4<0>; +L_0x2cf31b0 .delay 1 (30000,30000,30000) L_0x2cf31b0/d; +v0x29d9930_0 .net *"_s10", 0 0, L_0x2cf3270; 1 drivers +v0x29d9a10_0 .net *"_s12", 0 0, L_0x2cf3420; 1 drivers +v0x29d9580_0 .net "in", 7 0, L_0x2cf11b0; alias, 1 drivers +v0x29d9620_0 .net "ors", 1 0, L_0x2cf2fd0; 1 drivers +v0x29b51f0_0 .net "out", 0 0, L_0x2cf31b0; alias, 1 drivers +L_0x2cf23a0 .part L_0x2cf11b0, 0, 4; +L_0x2cf2fd0 .concat8 [ 1 1 0 0], L_0x2cf2090, L_0x2cf2cc0; +L_0x2cf3110 .part L_0x2cf11b0, 4, 4; +L_0x2cf3270 .part L_0x2cf2fd0, 0, 1; +L_0x2cf3420 .part L_0x2cf2fd0, 1, 1; +S_0x2a22ac0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2a22e70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1213c20/d .functor OR 1, L_0x1213ce0, L_0x1213e40, C4<0>, C4<0>; -L_0x1213c20 .delay 1 (30000,30000,30000) L_0x1213c20/d; -L_0x1214070/d .functor OR 1, L_0x1214180, L_0x12142e0, C4<0>, C4<0>; -L_0x1214070 .delay 1 (30000,30000,30000) L_0x1214070/d; -L_0x1214460/d .functor OR 1, L_0x12144d0, L_0x1214680, C4<0>, C4<0>; -L_0x1214460 .delay 1 (30000,30000,30000) L_0x1214460/d; -v0xe89fb0_0 .net *"_s0", 0 0, L_0x1213c20; 1 drivers -v0xe693c0_0 .net *"_s10", 0 0, L_0x1214180; 1 drivers -v0xe694a0_0 .net *"_s12", 0 0, L_0x12142e0; 1 drivers -v0xe69030_0 .net *"_s14", 0 0, L_0x12144d0; 1 drivers -v0xe690f0_0 .net *"_s16", 0 0, L_0x1214680; 1 drivers -v0xe68c80_0 .net *"_s3", 0 0, L_0x1213ce0; 1 drivers -v0xe68d40_0 .net *"_s5", 0 0, L_0x1213e40; 1 drivers -v0xe480d0_0 .net *"_s6", 0 0, L_0x1214070; 1 drivers -v0xe47d20_0 .net "in", 3 0, L_0x1214770; 1 drivers -v0xe47e00_0 .net "ors", 1 0, L_0x1213f80; 1 drivers -v0xe479b0_0 .net "out", 0 0, L_0x1214460; 1 drivers -L_0x1213ce0 .part L_0x1214770, 0, 1; -L_0x1213e40 .part L_0x1214770, 1, 1; -L_0x1213f80 .concat8 [ 1 1 0 0], L_0x1213c20, L_0x1214070; -L_0x1214180 .part L_0x1214770, 2, 1; -L_0x12142e0 .part L_0x1214770, 3, 1; -L_0x12144d0 .part L_0x1213f80, 0, 1; -L_0x1214680 .part L_0x1213f80, 1, 1; -S_0xe26dc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xe8a6f0; +L_0x2cf1850/d .functor OR 1, L_0x2cf1910, L_0x2cf1a70, C4<0>, C4<0>; +L_0x2cf1850 .delay 1 (30000,30000,30000) L_0x2cf1850/d; +L_0x2cf1ca0/d .functor OR 1, L_0x2cf1db0, L_0x2cf1f10, C4<0>, C4<0>; +L_0x2cf1ca0 .delay 1 (30000,30000,30000) L_0x2cf1ca0/d; +L_0x2cf2090/d .functor OR 1, L_0x2cf2100, L_0x2cf22b0, C4<0>, C4<0>; +L_0x2cf2090 .delay 1 (30000,30000,30000) L_0x2cf2090/d; +v0x26428a0_0 .net *"_s0", 0 0, L_0x2cf1850; 1 drivers +v0x263fa80_0 .net *"_s10", 0 0, L_0x2cf1db0; 1 drivers +v0x2601280_0 .net *"_s12", 0 0, L_0x2cf1f10; 1 drivers +v0x2601340_0 .net *"_s14", 0 0, L_0x2cf2100; 1 drivers +v0x2611280_0 .net *"_s16", 0 0, L_0x2cf22b0; 1 drivers +v0x260e780_0 .net *"_s3", 0 0, L_0x2cf1910; 1 drivers +v0x261dff0_0 .net *"_s5", 0 0, L_0x2cf1a70; 1 drivers +v0x261dbb0_0 .net *"_s6", 0 0, L_0x2cf1ca0; 1 drivers +v0x261aec0_0 .net "in", 3 0, L_0x2cf23a0; 1 drivers +v0x25ed850_0 .net "ors", 1 0, L_0x2cf1bb0; 1 drivers +v0x25ed4c0_0 .net "out", 0 0, L_0x2cf2090; 1 drivers +L_0x2cf1910 .part L_0x2cf23a0, 0, 1; +L_0x2cf1a70 .part L_0x2cf23a0, 1, 1; +L_0x2cf1bb0 .concat8 [ 1 1 0 0], L_0x2cf1850, L_0x2cf1ca0; +L_0x2cf1db0 .part L_0x2cf23a0, 2, 1; +L_0x2cf1f10 .part L_0x2cf23a0, 3, 1; +L_0x2cf2100 .part L_0x2cf1bb0, 0, 1; +L_0x2cf22b0 .part L_0x2cf1bb0, 1, 1; +S_0x29fe710 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2a22e70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12148a0/d .functor OR 1, L_0x1214910, L_0x1214a70, C4<0>, C4<0>; -L_0x12148a0 .delay 1 (30000,30000,30000) L_0x12148a0/d; -L_0x1214ca0/d .functor OR 1, L_0x1214db0, L_0x1214f10, C4<0>, C4<0>; -L_0x1214ca0 .delay 1 (30000,30000,30000) L_0x1214ca0/d; -L_0x1215090/d .functor OR 1, L_0x1215100, L_0x12152b0, C4<0>, C4<0>; -L_0x1215090 .delay 1 (30000,30000,30000) L_0x1215090/d; -v0xe26a70_0 .net *"_s0", 0 0, L_0x12148a0; 1 drivers -v0xe26680_0 .net *"_s10", 0 0, L_0x1214db0; 1 drivers -v0xe26760_0 .net *"_s12", 0 0, L_0x1214f10; 1 drivers -v0xe05af0_0 .net *"_s14", 0 0, L_0x1215100; 1 drivers -v0xe05bd0_0 .net *"_s16", 0 0, L_0x12152b0; 1 drivers -v0xe057a0_0 .net *"_s3", 0 0, L_0x1214910; 1 drivers -v0xe053b0_0 .net *"_s5", 0 0, L_0x1214a70; 1 drivers -v0xe05490_0 .net *"_s6", 0 0, L_0x1214ca0; 1 drivers -v0xde47a0_0 .net "in", 3 0, L_0x12154e0; 1 drivers -v0xde4410_0 .net "ors", 1 0, L_0x1214bb0; 1 drivers -v0xde44f0_0 .net "out", 0 0, L_0x1215090; 1 drivers -L_0x1214910 .part L_0x12154e0, 0, 1; -L_0x1214a70 .part L_0x12154e0, 1, 1; -L_0x1214bb0 .concat8 [ 1 1 0 0], L_0x12148a0, L_0x1214ca0; -L_0x1214db0 .part L_0x12154e0, 2, 1; -L_0x1214f10 .part L_0x12154e0, 3, 1; -L_0x1215100 .part L_0x1214bb0, 0, 1; -L_0x12152b0 .part L_0x1214bb0, 1, 1; -S_0xda1970 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xbd2d70; +L_0x2cf24d0/d .functor OR 1, L_0x2cf2540, L_0x2cf26a0, C4<0>, C4<0>; +L_0x2cf24d0 .delay 1 (30000,30000,30000) L_0x2cf24d0/d; +L_0x2cf28d0/d .functor OR 1, L_0x2cf29e0, L_0x2cf2b40, C4<0>, C4<0>; +L_0x2cf28d0 .delay 1 (30000,30000,30000) L_0x2cf28d0/d; +L_0x2cf2cc0/d .functor OR 1, L_0x2cf2d30, L_0x2cf2ee0, C4<0>, C4<0>; +L_0x2cf2cc0 .delay 1 (30000,30000,30000) L_0x2cf2cc0/d; +v0x25ea810_0 .net *"_s0", 0 0, L_0x2cf24d0; 1 drivers +v0x25f9f60_0 .net *"_s10", 0 0, L_0x2cf29e0; 1 drivers +v0x25f9b20_0 .net *"_s12", 0 0, L_0x2cf2b40; 1 drivers +v0x25f9be0_0 .net *"_s14", 0 0, L_0x2cf2d30; 1 drivers +v0x25f6e30_0 .net *"_s16", 0 0, L_0x2cf2ee0; 1 drivers +v0x2945020_0 .net *"_s3", 0 0, L_0x2cf2540; 1 drivers +v0x29fe380_0 .net *"_s5", 0 0, L_0x2cf26a0; 1 drivers +v0x29fe460_0 .net *"_s6", 0 0, L_0x2cf28d0; 1 drivers +v0x29fdfd0_0 .net "in", 3 0, L_0x2cf3110; 1 drivers +v0x29fe090_0 .net "ors", 1 0, L_0x2cf27e0; 1 drivers +v0x29d9cc0_0 .net "out", 0 0, L_0x2cf2cc0; 1 drivers +L_0x2cf2540 .part L_0x2cf3110, 0, 1; +L_0x2cf26a0 .part L_0x2cf3110, 1, 1; +L_0x2cf27e0 .concat8 [ 1 1 0 0], L_0x2cf24d0, L_0x2cf28d0; +L_0x2cf29e0 .part L_0x2cf3110, 2, 1; +L_0x2cf2b40 .part L_0x2cf3110, 3, 1; +L_0x2cf2d30 .part L_0x2cf27e0, 0, 1; +L_0x2cf2ee0 .part L_0x2cf27e0, 1, 1; +S_0x2921ec0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x26470b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xe00d60_0 .net "ands", 7 0, L_0x120fb80; 1 drivers -v0xdc6ed0_0 .net "in", 7 0, L_0x120e070; alias, 1 drivers -v0xdc6f90_0 .net "out", 0 0, L_0x1211a70; alias, 1 drivers -v0xde2570_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xd80d10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xda1970; +v0x2a022a0_0 .net "ands", 7 0, L_0x2ced720; 1 drivers +v0x2a1e4e0_0 .net "in", 7 0, L_0x2ceb690; alias, 1 drivers +v0x29dd750_0 .net "out", 0 0, L_0x2cef720; alias, 1 drivers +v0x29dd7f0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x28fdaf0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2921ec0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xf73190_0 .net "A", 7 0, L_0x120e070; alias, 1 drivers -v0xf72d70_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xf619f0_0 .net *"_s0", 0 0, L_0x120e400; 1 drivers -v0xf61ab0_0 .net *"_s12", 0 0, L_0x120ee10; 1 drivers -v0xf6e2d0_0 .net *"_s16", 0 0, L_0x120f170; 1 drivers -v0xf51cf0_0 .net *"_s20", 0 0, L_0x120f540; 1 drivers -v0xf51dd0_0 .net *"_s24", 0 0, L_0x120f870; 1 drivers -v0xf51970_0 .net *"_s28", 0 0, L_0x120f800; 1 drivers -v0xf51a50_0 .net *"_s4", 0 0, L_0x120e7f0; 1 drivers -v0xf432c0_0 .net *"_s8", 0 0, L_0x120eb00; 1 drivers -v0xf40670_0 .net "out", 7 0, L_0x120fb80; alias, 1 drivers -L_0x120e510 .part L_0x120e070, 0, 1; -L_0x120e700 .part v0x12010b0_0, 0, 1; -L_0x120e8b0 .part L_0x120e070, 1, 1; -L_0x120ea10 .part v0x12010b0_0, 1, 1; -L_0x120ebc0 .part L_0x120e070, 2, 1; -L_0x120ed20 .part v0x12010b0_0, 2, 1; -L_0x120eed0 .part L_0x120e070, 3, 1; -L_0x120f030 .part v0x12010b0_0, 3, 1; -L_0x120f230 .part L_0x120e070, 4, 1; -L_0x120f4a0 .part v0x12010b0_0, 4, 1; -L_0x120f5b0 .part L_0x120e070, 5, 1; -L_0x120f710 .part v0x12010b0_0, 5, 1; -L_0x120f930 .part L_0x120e070, 6, 1; -L_0x120fa90 .part v0x12010b0_0, 6, 1; -LS_0x120fb80_0_0 .concat8 [ 1 1 1 1], L_0x120e400, L_0x120e7f0, L_0x120eb00, L_0x120ee10; -LS_0x120fb80_0_4 .concat8 [ 1 1 1 1], L_0x120f170, L_0x120f540, L_0x120f870, L_0x120f800; -L_0x120fb80 .concat8 [ 4 4 0 0], LS_0x120fb80_0_0, LS_0x120fb80_0_4; -L_0x120ff40 .part L_0x120e070, 7, 1; -L_0x1210130 .part v0x12010b0_0, 7, 1; -S_0xd805d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xd5f930 .param/l "i" 0 4 54, +C4<00>; -L_0x120e400/d .functor AND 1, L_0x120e510, L_0x120e700, C4<1>, C4<1>; -L_0x120e400 .delay 1 (30000,30000,30000) L_0x120e400/d; -v0xd5fa10_0 .net *"_s0", 0 0, L_0x120e510; 1 drivers -v0xd5f5a0_0 .net *"_s1", 0 0, L_0x120e700; 1 drivers -S_0xd5f1f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xd5f6b0 .param/l "i" 0 4 54, +C4<01>; -L_0x120e7f0/d .functor AND 1, L_0x120e8b0, L_0x120ea10, C4<1>, C4<1>; -L_0x120e7f0 .delay 1 (30000,30000,30000) L_0x120e7f0/d; -v0xd3e5d0_0 .net *"_s0", 0 0, L_0x120e8b0; 1 drivers -v0xd3e1d0_0 .net *"_s1", 0 0, L_0x120ea10; 1 drivers -S_0xd3de20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xd1d190 .param/l "i" 0 4 54, +C4<010>; -L_0x120eb00/d .functor AND 1, L_0x120ebc0, L_0x120ed20, C4<1>, C4<1>; -L_0x120eb00 .delay 1 (30000,30000,30000) L_0x120eb00/d; -v0xd1d250_0 .net *"_s0", 0 0, L_0x120ebc0; 1 drivers -v0xc58310_0 .net *"_s1", 0 0, L_0x120ed20; 1 drivers -S_0xfd2680 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xc58440 .param/l "i" 0 4 54, +C4<011>; -L_0x120ee10/d .functor AND 1, L_0x120eed0, L_0x120f030, C4<1>, C4<1>; -L_0x120ee10 .delay 1 (30000,30000,30000) L_0x120ee10/d; -v0xbf0d40_0 .net *"_s0", 0 0, L_0x120eed0; 1 drivers -v0xfcf810_0 .net *"_s1", 0 0, L_0x120f030; 1 drivers -S_0xfc1490 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xfcf940 .param/l "i" 0 4 54, +C4<0100>; -L_0x120f170/d .functor AND 1, L_0x120f230, L_0x120f4a0, C4<1>, C4<1>; -L_0x120f170 .delay 1 (30000,30000,30000) L_0x120f170/d; -v0xfc7f40_0 .net *"_s0", 0 0, L_0x120f230; 1 drivers -v0xfcac20_0 .net *"_s1", 0 0, L_0x120f4a0; 1 drivers -S_0xfc41d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xfcad00 .param/l "i" 0 4 54, +C4<0101>; -L_0x120f540/d .functor AND 1, L_0x120f5b0, L_0x120f710, C4<1>, C4<1>; -L_0x120f540 .delay 1 (30000,30000,30000) L_0x120f540/d; -v0xfa4180_0 .net *"_s0", 0 0, L_0x120f5b0; 1 drivers -v0xfa4240_0 .net *"_s1", 0 0, L_0x120f710; 1 drivers -S_0xfb0a60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xf94480 .param/l "i" 0 4 54, +C4<0110>; -L_0x120f870/d .functor AND 1, L_0x120f930, L_0x120fa90, C4<1>, C4<1>; -L_0x120f870 .delay 1 (30000,30000,30000) L_0x120f870/d; -v0xf94090_0 .net *"_s0", 0 0, L_0x120f930; 1 drivers -v0xf94170_0 .net *"_s1", 0 0, L_0x120fa90; 1 drivers -S_0xf82db0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xd80d10; - .timescale -9 -12; -P_0xf8f6b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x120f800/d .functor AND 1, L_0x120ff40, L_0x1210130, C4<1>, C4<1>; -L_0x120f800 .delay 1 (30000,30000,30000) L_0x120f800/d; -v0xf8f770_0 .net *"_s0", 0 0, L_0x120ff40; 1 drivers -v0xf730b0_0 .net *"_s1", 0 0, L_0x1210130; 1 drivers -S_0xf4cf20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xda1970; +v0x26fbfc0_0 .net "A", 7 0, L_0x2ceb690; alias, 1 drivers +v0x26fbb90_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x26d7890_0 .net *"_s0", 0 0, L_0x2cebf10; 1 drivers +v0x26d7950_0 .net *"_s12", 0 0, L_0x2cec8d0; 1 drivers +v0x26d7500_0 .net *"_s16", 0 0, L_0x2cecc30; 1 drivers +v0x26d75e0_0 .net *"_s20", 0 0, L_0x2ced060; 1 drivers +v0x26d7190_0 .net *"_s24", 0 0, L_0x2ced390; 1 drivers +v0x26b2dd0_0 .net *"_s28", 0 0, L_0x2ced320; 1 drivers +v0x26b2eb0_0 .net *"_s4", 0 0, L_0x2cec2b0; 1 drivers +v0x26b2b10_0 .net *"_s8", 0 0, L_0x2cec5c0; 1 drivers +v0x26b2690_0 .net "out", 7 0, L_0x2ced720; alias, 1 drivers +L_0x2cec020 .part L_0x2ceb690, 0, 1; +L_0x2cec210 .part v0x2cdd2e0_0, 0, 1; +L_0x2cec370 .part L_0x2ceb690, 1, 1; +L_0x2cec4d0 .part v0x2cdd2e0_0, 1, 1; +L_0x2cec680 .part L_0x2ceb690, 2, 1; +L_0x2cec7e0 .part v0x2cdd2e0_0, 2, 1; +L_0x2cec990 .part L_0x2ceb690, 3, 1; +L_0x2cecaf0 .part v0x2cdd2e0_0, 3, 1; +L_0x2ceccf0 .part L_0x2ceb690, 4, 1; +L_0x2cecf60 .part v0x2cdd2e0_0, 4, 1; +L_0x2ced0d0 .part L_0x2ceb690, 5, 1; +L_0x2ced230 .part v0x2cdd2e0_0, 5, 1; +L_0x2ced450 .part L_0x2ceb690, 6, 1; +L_0x2ced5b0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2ced720_0_0 .concat8 [ 1 1 1 1], L_0x2cebf10, L_0x2cec2b0, L_0x2cec5c0, L_0x2cec8d0; +LS_0x2ced720_0_4 .concat8 [ 1 1 1 1], L_0x2cecc30, L_0x2ced060, L_0x2ced390, L_0x2ced320; +L_0x2ced720 .concat8 [ 4 4 0 0], LS_0x2ced720_0_0, LS_0x2ced720_0_4; +L_0x2cedae0 .part L_0x2ceb690, 7, 1; +L_0x2cedcd0 .part v0x2cdd2e0_0, 7, 1; +S_0x28fd760 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x2626050 .param/l "i" 0 4 54, +C4<00>; +L_0x2cebf10/d .functor AND 1, L_0x2cec020, L_0x2cec210, C4<1>, C4<1>; +L_0x2cebf10 .delay 1 (30000,30000,30000) L_0x2cebf10/d; +v0x28fd3b0_0 .net *"_s0", 0 0, L_0x2cec020; 1 drivers +v0x28d90c0_0 .net *"_s1", 0 0, L_0x2cec210; 1 drivers +S_0x28d8d30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x263fb80 .param/l "i" 0 4 54, +C4<01>; +L_0x2cec2b0/d .functor AND 1, L_0x2cec370, L_0x2cec4d0, C4<1>, C4<1>; +L_0x2cec2b0 .delay 1 (30000,30000,30000) L_0x2cec2b0/d; +v0x28d91a0_0 .net *"_s0", 0 0, L_0x2cec370; 1 drivers +v0x28d8980_0 .net *"_s1", 0 0, L_0x2cec4d0; 1 drivers +S_0x2821a00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x25ed950 .param/l "i" 0 4 54, +C4<010>; +L_0x2cec5c0/d .functor AND 1, L_0x2cec680, L_0x2cec7e0, C4<1>, C4<1>; +L_0x2cec5c0 .delay 1 (30000,30000,30000) L_0x2cec5c0/d; +v0x28d8a60_0 .net *"_s0", 0 0, L_0x2cec680; 1 drivers +v0x2821670_0 .net *"_s1", 0 0, L_0x2cec7e0; 1 drivers +S_0x28212c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x2821770 .param/l "i" 0 4 54, +C4<011>; +L_0x2cec8d0/d .functor AND 1, L_0x2cec990, L_0x2cecaf0, C4<1>, C4<1>; +L_0x2cec8d0 .delay 1 (30000,30000,30000) L_0x2cec8d0/d; +v0x27fcf60_0 .net *"_s0", 0 0, L_0x2cec990; 1 drivers +v0x27fcb60_0 .net *"_s1", 0 0, L_0x2cecaf0; 1 drivers +S_0x27fc7b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x27d84a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2cecc30/d .functor AND 1, L_0x2ceccf0, L_0x2cecf60, C4<1>, C4<1>; +L_0x2cecc30 .delay 1 (30000,30000,30000) L_0x2cecc30/d; +v0x27d8560_0 .net *"_s0", 0 0, L_0x2ceccf0; 1 drivers +v0x27d8110_0 .net *"_s1", 0 0, L_0x2cecf60; 1 drivers +S_0x27d7d60 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x27b39d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2ced060/d .functor AND 1, L_0x2ced0d0, L_0x2ced230, C4<1>, C4<1>; +L_0x2ced060 .delay 1 (30000,30000,30000) L_0x2ced060/d; +v0x27b3a90_0 .net *"_s0", 0 0, L_0x2ced0d0; 1 drivers +v0x27b3640_0 .net *"_s1", 0 0, L_0x2ced230; 1 drivers +S_0x27b3290 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x2720da0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2ced390/d .functor AND 1, L_0x2ced450, L_0x2ced5b0, C4<1>, C4<1>; +L_0x2ced390 .delay 1 (30000,30000,30000) L_0x2ced390/d; +v0x2720e60_0 .net *"_s0", 0 0, L_0x2ced450; 1 drivers +v0x2720a10_0 .net *"_s1", 0 0, L_0x2ced5b0; 1 drivers +S_0x2720660 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x28fdaf0; + .timescale -9 -12; +P_0x26fc290 .param/l "i" 0 4 54, +C4<0111>; +L_0x2ced320/d .functor AND 1, L_0x2cedae0, L_0x2cedcd0, C4<1>, C4<1>; +L_0x2ced320 .delay 1 (30000,30000,30000) L_0x2ced320/d; +v0x26fc350_0 .net *"_s0", 0 0, L_0x2cedae0; 1 drivers +v0x26fbf00_0 .net *"_s1", 0 0, L_0x2cedcd0; 1 drivers +S_0x2620170 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2921ec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1211a70/d .functor OR 1, L_0x1211b30, L_0x1211ce0, C4<0>, C4<0>; -L_0x1211a70 .delay 1 (30000,30000,30000) L_0x1211a70/d; -v0xe09580_0 .net *"_s10", 0 0, L_0x1211b30; 1 drivers -v0xe09660_0 .net *"_s12", 0 0, L_0x1211ce0; 1 drivers -v0xe22030_0 .net "in", 7 0, L_0x120fb80; alias, 1 drivers -v0xe220d0_0 .net "ors", 1 0, L_0x1211890; 1 drivers -v0xde8230_0 .net "out", 0 0, L_0x1211a70; alias, 1 drivers -L_0x1210d70 .part L_0x120fb80, 0, 4; -L_0x1211890 .concat8 [ 1 1 0 0], L_0x1210a60, L_0x1211580; -L_0x12119d0 .part L_0x120fb80, 4, 4; -L_0x1211b30 .part L_0x1211890, 0, 1; -L_0x1211ce0 .part L_0x1211890, 1, 1; -S_0xf30970 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xf4cf20; +L_0x2cef720/d .functor OR 1, L_0x2cef7e0, L_0x2cef990, C4<0>, C4<0>; +L_0x2cef720 .delay 1 (30000,30000,30000) L_0x2cef720/d; +v0x2a366d0_0 .net *"_s10", 0 0, L_0x2cef7e0; 1 drivers +v0x2a367b0_0 .net *"_s12", 0 0, L_0x2cef990; 1 drivers +v0x2a42fb0_0 .net "in", 7 0, L_0x2ced720; alias, 1 drivers +v0x2a43050_0 .net "ors", 1 0, L_0x2cef540; 1 drivers +v0x2a021a0_0 .net "out", 0 0, L_0x2cef720; alias, 1 drivers +L_0x2cee910 .part L_0x2ced720, 0, 4; +L_0x2cef540 .concat8 [ 1 1 0 0], L_0x2cee600, L_0x2cef230; +L_0x2cef680 .part L_0x2ced720, 4, 4; +L_0x2cef7e0 .part L_0x2cef540, 0, 1; +L_0x2cef990 .part L_0x2cef540, 1, 1; +S_0x261fde0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2620170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1210220/d .functor OR 1, L_0x12102e0, L_0x1210440, C4<0>, C4<0>; -L_0x1210220 .delay 1 (30000,30000,30000) L_0x1210220/d; -L_0x1210670/d .functor OR 1, L_0x1210780, L_0x12108e0, C4<0>, C4<0>; -L_0x1210670 .delay 1 (30000,30000,30000) L_0x1210670/d; -L_0x1210a60/d .functor OR 1, L_0x1210ad0, L_0x1210c80, C4<0>, C4<0>; -L_0x1210a60 .delay 1 (30000,30000,30000) L_0x1210a60/d; -v0xf305f0_0 .net *"_s0", 0 0, L_0x1210220; 1 drivers -v0xf306f0_0 .net *"_s10", 0 0, L_0x1210780; 1 drivers -v0xf21e80_0 .net *"_s12", 0 0, L_0x12108e0; 1 drivers -v0xf21f40_0 .net *"_s14", 0 0, L_0x1210ad0; 1 drivers -v0xf2bb90_0 .net *"_s16", 0 0, L_0x1210c80; 1 drivers -v0xf0a7f0_0 .net *"_s3", 0 0, L_0x12102e0; 1 drivers -v0xf0a8d0_0 .net *"_s5", 0 0, L_0x1210440; 1 drivers -v0xee9450_0 .net *"_s6", 0 0, L_0x1210670; 1 drivers -v0xee9530_0 .net "in", 3 0, L_0x1210d70; 1 drivers -v0xeaf5e0_0 .net "ors", 1 0, L_0x1210580; 1 drivers -v0xec80a0_0 .net "out", 0 0, L_0x1210a60; 1 drivers -L_0x12102e0 .part L_0x1210d70, 0, 1; -L_0x1210440 .part L_0x1210d70, 1, 1; -L_0x1210580 .concat8 [ 1 1 0 0], L_0x1210220, L_0x1210670; -L_0x1210780 .part L_0x1210d70, 2, 1; -L_0x12108e0 .part L_0x1210d70, 3, 1; -L_0x1210ad0 .part L_0x1210580, 0, 1; -L_0x1210c80 .part L_0x1210580, 1, 1; -S_0xe8e180 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xf4cf20; +L_0x2ceddc0/d .functor OR 1, L_0x2cede80, L_0x2cedfe0, C4<0>, C4<0>; +L_0x2ceddc0 .delay 1 (30000,30000,30000) L_0x2ceddc0/d; +L_0x2cee210/d .functor OR 1, L_0x2cee320, L_0x2cee480, C4<0>, C4<0>; +L_0x2cee210 .delay 1 (30000,30000,30000) L_0x2cee210/d; +L_0x2cee600/d .functor OR 1, L_0x2cee670, L_0x2cee820, C4<0>, C4<0>; +L_0x2cee600 .delay 1 (30000,30000,30000) L_0x2cee600/d; +v0x261fb00_0 .net *"_s0", 0 0, L_0x2ceddc0; 1 drivers +v0x25fc1d0_0 .net *"_s10", 0 0, L_0x2cee320; 1 drivers +v0x25fba50_0 .net *"_s12", 0 0, L_0x2cee480; 1 drivers +v0x25fbb10_0 .net *"_s14", 0 0, L_0x2cee670; 1 drivers +v0x2a896d0_0 .net *"_s16", 0 0, L_0x2cee820; 1 drivers +v0x2643b30_0 .net *"_s3", 0 0, L_0x2cede80; 1 drivers +v0x2643c10_0 .net *"_s5", 0 0, L_0x2cedfe0; 1 drivers +v0x2a86850_0 .net *"_s6", 0 0, L_0x2cee210; 1 drivers +v0x2a86930_0 .net "in", 3 0, L_0x2cee910; 1 drivers +v0x2a78580_0 .net "ors", 1 0, L_0x2cee120; 1 drivers +v0x2a7ef30_0 .net "out", 0 0, L_0x2cee600; 1 drivers +L_0x2cede80 .part L_0x2cee910, 0, 1; +L_0x2cedfe0 .part L_0x2cee910, 1, 1; +L_0x2cee120 .concat8 [ 1 1 0 0], L_0x2ceddc0, L_0x2cee210; +L_0x2cee320 .part L_0x2cee910, 2, 1; +L_0x2cee480 .part L_0x2cee910, 3, 1; +L_0x2cee670 .part L_0x2cee120, 0, 1; +L_0x2cee820 .part L_0x2cee120, 1, 1; +S_0x2a81c60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2620170; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1210ea0/d .functor OR 1, L_0x1210f10, L_0x1210fb0, C4<0>, C4<0>; -L_0x1210ea0 .delay 1 (30000,30000,30000) L_0x1210ea0/d; -L_0x1211190/d .functor OR 1, L_0x12112a0, L_0x1211400, C4<0>, C4<0>; -L_0x1211190 .delay 1 (30000,30000,30000) L_0x1211190/d; -L_0x1211580/d .functor OR 1, L_0x12115f0, L_0x12117a0, C4<0>, C4<0>; -L_0x1211580 .delay 1 (30000,30000,30000) L_0x1211580/d; -v0xea6d10_0 .net *"_s0", 0 0, L_0x1210ea0; 1 drivers -v0xea6df0_0 .net *"_s10", 0 0, L_0x12112a0; 1 drivers -v0xe6ce50_0 .net *"_s12", 0 0, L_0x1211400; 1 drivers -v0xe6cf10_0 .net *"_s14", 0 0, L_0x12115f0; 1 drivers -v0xe85960_0 .net *"_s16", 0 0, L_0x12117a0; 1 drivers -v0xe4bb40_0 .net *"_s3", 0 0, L_0x1210f10; 1 drivers -v0xe4bc20_0 .net *"_s5", 0 0, L_0x1210fb0; 1 drivers -v0xe64630_0 .net *"_s6", 0 0, L_0x1211190; 1 drivers -v0xe64710_0 .net "in", 3 0, L_0x12119d0; 1 drivers -v0xe2a900_0 .net "ors", 1 0, L_0x12110a0; 1 drivers -v0xe43320_0 .net "out", 0 0, L_0x1211580; 1 drivers -L_0x1210f10 .part L_0x12119d0, 0, 1; -L_0x1210fb0 .part L_0x12119d0, 1, 1; -L_0x12110a0 .concat8 [ 1 1 0 0], L_0x1210ea0, L_0x1211190; -L_0x12112a0 .part L_0x12119d0, 2, 1; -L_0x1211400 .part L_0x12119d0, 3, 1; -L_0x12115f0 .part L_0x12110a0, 0, 1; -L_0x12117a0 .part L_0x12110a0, 1, 1; -S_0xda5b40 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xbd2d70; +L_0x2ceea40/d .functor OR 1, L_0x2ceeab0, L_0x2ceec10, C4<0>, C4<0>; +L_0x2ceea40 .delay 1 (30000,30000,30000) L_0x2ceea40/d; +L_0x2ceee40/d .functor OR 1, L_0x2ceef50, L_0x2cef0b0, C4<0>, C4<0>; +L_0x2ceee40 .delay 1 (30000,30000,30000) L_0x2ceee40/d; +L_0x2cef230/d .functor OR 1, L_0x2cef2a0, L_0x2cef450, C4<0>, C4<0>; +L_0x2cef230 .delay 1 (30000,30000,30000) L_0x2cef230/d; +v0x2a7b210_0 .net *"_s0", 0 0, L_0x2ceea40; 1 drivers +v0x2a7b2f0_0 .net *"_s10", 0 0, L_0x2ceef50; 1 drivers +v0x2a5b210_0 .net *"_s12", 0 0, L_0x2cef0b0; 1 drivers +v0x2a5b2d0_0 .net *"_s14", 0 0, L_0x2cef2a0; 1 drivers +v0x2a67af0_0 .net *"_s16", 0 0, L_0x2cef450; 1 drivers +v0x2a67bd0_0 .net *"_s3", 0 0, L_0x2ceeab0; 1 drivers +v0x2a47d50_0 .net *"_s5", 0 0, L_0x2ceec10; 1 drivers +v0x2a47e30_0 .net *"_s6", 0 0, L_0x2ceee40; 1 drivers +v0x2a479d0_0 .net "in", 3 0, L_0x2cef680; 1 drivers +v0x2a39260_0 .net "ors", 1 0, L_0x2ceed50; 1 drivers +v0x2a39340_0 .net "out", 0 0, L_0x2cef230; 1 drivers +L_0x2ceeab0 .part L_0x2cef680, 0, 1; +L_0x2ceec10 .part L_0x2cef680, 1, 1; +L_0x2ceed50 .concat8 [ 1 1 0 0], L_0x2ceea40, L_0x2ceee40; +L_0x2ceef50 .part L_0x2cef680, 2, 1; +L_0x2cef0b0 .part L_0x2cef680, 3, 1; +L_0x2cef2a0 .part L_0x2ceed50, 0, 1; +L_0x2cef450 .part L_0x2ceed50, 1, 1; +S_0x29b8c80 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x26470b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -1238,80 +1302,80 @@ S_0xda5b40 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xbd2d70; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x120d3e0/d .functor XNOR 1, L_0x12159e0, L_0x1215b40, C4<0>, C4<0>; -L_0x120d3e0 .delay 1 (20000,20000,20000) L_0x120d3e0/d; -L_0x120d650/d .functor AND 1, L_0x12159e0, L_0x120c2d0, C4<1>, C4<1>; -L_0x120d650 .delay 1 (30000,30000,30000) L_0x120d650/d; -L_0x120d6c0/d .functor AND 1, L_0x120d3e0, L_0x1215be0, C4<1>, C4<1>; -L_0x120d6c0 .delay 1 (30000,30000,30000) L_0x120d6c0/d; -L_0x120d820/d .functor OR 1, L_0x120d6c0, L_0x120d650, C4<0>, C4<0>; -L_0x120d820 .delay 1 (30000,30000,30000) L_0x120d820/d; -v0xdc1210_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers -v0xdc1300_0 .net "a_", 0 0, L_0x120c1c0; alias, 1 drivers -v0xdbe680_0 .net "b", 0 0, L_0x1215b40; alias, 1 drivers -v0xdbe770_0 .net "b_", 0 0, L_0x120c2d0; alias, 1 drivers -v0xd847a0_0 .net "carryin", 0 0, L_0x1215be0; alias, 1 drivers -v0xd9fe90_0 .net "eq", 0 0, L_0x120d3e0; 1 drivers -v0xd9ff50_0 .net "lt", 0 0, L_0x120d650; 1 drivers -v0xd633c0_0 .net "out", 0 0, L_0x120d820; 1 drivers -v0xd63480_0 .net "w0", 0 0, L_0x120d6c0; 1 drivers -S_0xd41ff0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xbd2d70; +L_0x2cea410/d .functor XNOR 1, L_0x2cf3660, L_0x2cf37c0, C4<0>, C4<0>; +L_0x2cea410 .delay 1 (20000,20000,20000) L_0x2cea410/d; +L_0x2cea590/d .functor AND 1, L_0x2cf3660, L_0x2ce9100, C4<1>, C4<1>; +L_0x2cea590 .delay 1 (30000,30000,30000) L_0x2cea590/d; +L_0x2cea6f0/d .functor AND 1, L_0x2cea410, L_0x2cf3860, C4<1>, C4<1>; +L_0x2cea6f0 .delay 1 (30000,30000,30000) L_0x2cea6f0/d; +L_0x2cea800/d .functor OR 1, L_0x2cea6f0, L_0x2cea590, C4<0>, C4<0>; +L_0x2cea800 .delay 1 (30000,30000,30000) L_0x2cea800/d; +v0x29d7b50_0 .net "a", 0 0, L_0x2cf3660; alias, 1 drivers +v0x29b4b80_0 .net "a_", 0 0, L_0x2cdeb60; alias, 1 drivers +v0x29b4c20_0 .net "b", 0 0, L_0x2cf37c0; alias, 1 drivers +v0x2990840_0 .net "b_", 0 0, L_0x2ce9100; alias, 1 drivers +v0x29908e0_0 .net "carryin", 0 0, L_0x2cf3860; alias, 1 drivers +v0x29904c0_0 .net "eq", 0 0, L_0x2cea410; 1 drivers +v0x2990560_0 .net "lt", 0 0, L_0x2cea590; 1 drivers +v0x297f2f0_0 .net "out", 0 0, L_0x2cea800; 1 drivers +v0x297f3b0_0 .net "w0", 0 0, L_0x2cea6f0; 1 drivers +S_0x296b900 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x26470b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x120d1c0/d .functor OR 1, L_0x120ccc0, L_0xcdac10, C4<0>, C4<0>; -L_0x120d1c0 .delay 1 (30000,30000,30000) L_0x120d1c0/d; -v0xcde530_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers -v0xcde5f0_0 .net "b", 0 0, L_0x120c2d0; alias, 1 drivers -v0xceaa40_0 .net "c1", 0 0, L_0x120ccc0; 1 drivers -v0xceaae0_0 .net "c2", 0 0, L_0xcdac10; 1 drivers -v0xcdab20_0 .net "carryin", 0 0, L_0x1215be0; alias, 1 drivers -v0xcda7a0_0 .net "carryout", 0 0, L_0x120d1c0; 1 drivers -v0xcda840_0 .net "s1", 0 0, L_0x120cc00; 1 drivers -v0xcc96b0_0 .net "sum", 0 0, L_0x120ce20; 1 drivers -S_0xd5d700 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xd41ff0; +L_0x2ce9ff0/d .functor OR 1, L_0x2ce9ad0, L_0x2ce9f30, C4<0>, C4<0>; +L_0x2ce9ff0 .delay 1 (30000,30000,30000) L_0x2ce9ff0/d; +v0x28dcb50_0 .net "a", 0 0, L_0x2cf3660; alias, 1 drivers +v0x28dcc10_0 .net "b", 0 0, L_0x2ce9100; alias, 1 drivers +v0x28f8d60_0 .net "c1", 0 0, L_0x2ce9ad0; 1 drivers +v0x28f8e00_0 .net "c2", 0 0, L_0x2ce9f30; 1 drivers +v0x28b8060_0 .net "carryin", 0 0, L_0x2cf3860; alias, 1 drivers +v0x28d6eb0_0 .net "carryout", 0 0, L_0x2ce9ff0; 1 drivers +v0x28d6f50_0 .net "s1", 0 0, L_0x26d5380; 1 drivers +v0x28b4660_0 .net "sum", 0 0, L_0x2ce9c30; 1 drivers +S_0x295a670 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x296b900; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x120cc00/d .functor XOR 1, L_0x12159e0, L_0x120c2d0, C4<0>, C4<0>; -L_0x120cc00 .delay 1 (30000,30000,30000) L_0x120cc00/d; -L_0x120ccc0/d .functor AND 1, L_0x12159e0, L_0x120c2d0, C4<1>, C4<1>; -L_0x120ccc0 .delay 1 (30000,30000,30000) L_0x120ccc0/d; -v0xd20c20_0 .net "a", 0 0, L_0x12159e0; alias, 1 drivers -v0xd20cc0_0 .net "b", 0 0, L_0x120c2d0; alias, 1 drivers -v0xd1cb20_0 .net "carryout", 0 0, L_0x120ccc0; alias, 1 drivers -v0xd1cbc0_0 .net "sum", 0 0, L_0x120cc00; alias, 1 drivers -S_0xcff8c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xd41ff0; +L_0x26d5380/d .functor XOR 1, L_0x2cf3660, L_0x2ce9100, C4<0>, C4<0>; +L_0x26d5380 .delay 1 (30000,30000,30000) L_0x26d5380/d; +L_0x2ce9ad0/d .functor AND 1, L_0x2cf3660, L_0x2ce9100, C4<1>, C4<1>; +L_0x2ce9ad0 .delay 1 (30000,30000,30000) L_0x2ce9ad0/d; +v0x2947200_0 .net "a", 0 0, L_0x2cf3660; alias, 1 drivers +v0x2946dc0_0 .net "b", 0 0, L_0x2ce9100; alias, 1 drivers +v0x2946e80_0 .net "carryout", 0 0, L_0x2ce9ad0; alias, 1 drivers +v0x2938670_0 .net "sum", 0 0, L_0x26d5380; alias, 1 drivers +S_0x2935ad0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x296b900; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x120ce20/d .functor XOR 1, L_0x120cc00, L_0x1215be0, C4<0>, C4<0>; -L_0x120ce20 .delay 1 (30000,30000,30000) L_0x120ce20/d; -L_0xcdac10/d .functor AND 1, L_0x120cc00, L_0x1215be0, C4<1>, C4<1>; -L_0xcdac10 .delay 1 (30000,30000,30000) L_0xcdac10/d; -v0xd0be30_0 .net "a", 0 0, L_0x120cc00; alias, 1 drivers -v0xcfbeb0_0 .net "b", 0 0, L_0x1215be0; alias, 1 drivers -v0xcfbf50_0 .net "carryout", 0 0, L_0xcdac10; alias, 1 drivers -v0xcfbb30_0 .net "sum", 0 0, L_0x120ce20; alias, 1 drivers -S_0xc34760 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0xbd4310; - .timescale -9 -12; -L_0x2b0ab3d05138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1215c80/d .functor OR 1, L_0x2b0ab3d05138, L_0x2b0ab3d05180, C4<0>, C4<0>; -L_0x1215c80 .delay 1 (30000,30000,30000) L_0x1215c80/d; -v0xc343e0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05138; 1 drivers -v0xc344a0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05180; 1 drivers -S_0xc23180 .scope generate, "alu_slices[2]" "alu_slices[2]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0xcfbc70 .param/l "i" 0 3 41, +C4<010>; -S_0xc13330 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xc23180; +L_0x2ce9c30/d .functor XOR 1, L_0x26d5380, L_0x2cf3860, C4<0>, C4<0>; +L_0x2ce9c30 .delay 1 (30000,30000,30000) L_0x2ce9c30/d; +L_0x2ce9f30/d .functor AND 1, L_0x26d5380, L_0x2cf3860, C4<1>, C4<1>; +L_0x2ce9f30 .delay 1 (30000,30000,30000) L_0x2ce9f30/d; +v0x29423f0_0 .net "a", 0 0, L_0x26d5380; alias, 1 drivers +v0x2901580_0 .net "b", 0 0, L_0x2cf3860; alias, 1 drivers +v0x2901620_0 .net "carryout", 0 0, L_0x2ce9f30; alias, 1 drivers +v0x291d870_0 .net "sum", 0 0, L_0x2ce9c30; alias, 1 drivers +S_0x27d6270 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2648650; + .timescale -9 -12; +L_0x2ac6110b66d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ce9560/d .functor OR 1, L_0x2ac6110b66d8, L_0x2ac6110b6720, C4<0>, C4<0>; +L_0x2ce9560 .delay 1 (30000,30000,30000) L_0x2ce9560/d; +v0x27d36e0_0 .net/2u *"_s0", 0 0, L_0x2ac6110b66d8; 1 drivers +v0x27d37a0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b6720; 1 drivers +S_0x27a25f0 .scope generate, "alu_slices[2]" "alu_slices[2]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x278f0d0 .param/l "i" 0 3 39, +C4<010>; +S_0x278ed50 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x27a25f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -1320,445 +1384,476 @@ S_0xc13330 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xc23180; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1215ea0/d .functor NOT 1, L_0x121f680, C4<0>, C4<0>, C4<0>; -L_0x1215ea0 .delay 1 (10000,10000,10000) L_0x1215ea0/d; -L_0x1215fb0/d .functor NOT 1, L_0x121f870, C4<0>, C4<0>, C4<0>; -L_0x1215fb0 .delay 1 (10000,10000,10000) L_0x1215fb0/d; -L_0x1216ef0/d .functor XOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; -L_0x1216ef0 .delay 1 (30000,30000,30000) L_0x1216ef0/d; -L_0x2b0ab3d051c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12175a0/d .functor OR 1, L_0x2b0ab3d051c8, L_0x2b0ab3d05210, C4<0>, C4<0>; -L_0x12175a0 .delay 1 (30000,30000,30000) L_0x12175a0/d; -L_0x12177a0/d .functor AND 1, L_0x121f680, L_0x121f870, C4<1>, C4<1>; -L_0x12177a0 .delay 1 (30000,30000,30000) L_0x12177a0/d; -L_0x1217860/d .functor NAND 1, L_0x121f680, L_0x121f870, C4<1>, C4<1>; -L_0x1217860 .delay 1 (20000,20000,20000) L_0x1217860/d; -L_0x12179c0/d .functor XOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; -L_0x12179c0 .delay 1 (20000,20000,20000) L_0x12179c0/d; -L_0x1217e70/d .functor OR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; -L_0x1217e70 .delay 1 (30000,30000,30000) L_0x1217e70/d; -L_0x121f580/d .functor NOT 1, L_0x121b7e0, C4<0>, C4<0>, C4<0>; -L_0x121f580 .delay 1 (10000,10000,10000) L_0x121f580/d; -v0xff4a60_0 .net "A", 0 0, L_0x121f680; 1 drivers -v0xff4b20_0 .net "A_", 0 0, L_0x1215ea0; 1 drivers -v0xff4be0_0 .net "B", 0 0, L_0x121f870; 1 drivers -v0xff4cb0_0 .net "B_", 0 0, L_0x1215fb0; 1 drivers -v0xff4d50_0 .net *"_s12", 0 0, L_0x12175a0; 1 drivers -v0xff4e40_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d051c8; 1 drivers -v0xff4f00_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05210; 1 drivers -v0xff4fe0_0 .net *"_s18", 0 0, L_0x12177a0; 1 drivers -v0xff50c0_0 .net *"_s20", 0 0, L_0x1217860; 1 drivers -v0xff5230_0 .net *"_s22", 0 0, L_0x12179c0; 1 drivers -v0xff5310_0 .net *"_s24", 0 0, L_0x1217e70; 1 drivers -o0x2b0ab3ca9d68 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0xff53f0_0 name=_s30 -o0x2b0ab3ca9d98 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0xff54d0_0 name=_s32 -v0xff55b0_0 .net *"_s8", 0 0, L_0x1216ef0; 1 drivers -v0xff5690_0 .net "carryin", 0 0, L_0x121f9a0; 1 drivers -v0xff5730_0 .net "carryout", 0 0, L_0x121f220; 1 drivers -v0xff57d0_0 .net "carryouts", 7 0, L_0x1353280; 1 drivers -v0xff5980_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0xff5a20_0 .net "result", 0 0, L_0x121b7e0; 1 drivers -v0xff5b10_0 .net "results", 7 0, L_0x1217c40; 1 drivers -v0xff5c20_0 .net "zero", 0 0, L_0x121f580; 1 drivers -LS_0x1217c40_0_0 .concat8 [ 1 1 1 1], L_0x1216410, L_0x1216a40, L_0x1216ef0, L_0x12175a0; -LS_0x1217c40_0_4 .concat8 [ 1 1 1 1], L_0x12177a0, L_0x1217860, L_0x12179c0, L_0x1217e70; -L_0x1217c40 .concat8 [ 4 4 0 0], LS_0x1217c40_0_0, LS_0x1217c40_0_4; -LS_0x1353280_0_0 .concat [ 1 1 1 1], L_0x12166c0, L_0x1216d90, o0x2b0ab3ca9d68, L_0x12173f0; -LS_0x1353280_0_4 .concat [ 4 0 0 0], o0x2b0ab3ca9d98; -L_0x1353280 .concat [ 4 4 0 0], LS_0x1353280_0_0, LS_0x1353280_0_4; -S_0xc01d00 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xc13330; +L_0x2cf39f0/d .functor NOT 1, L_0x2cfdef0, C4<0>, C4<0>, C4<0>; +L_0x2cf39f0 .delay 1 (10000,10000,10000) L_0x2cf39f0/d; +L_0x2cf3b50/d .functor NOT 1, L_0x2cfe0e0, C4<0>, C4<0>, C4<0>; +L_0x2cf3b50 .delay 1 (10000,10000,10000) L_0x2cf3b50/d; +L_0x2cf4a60/d .functor XOR 1, L_0x2cfdef0, L_0x2cfe0e0, C4<0>, C4<0>; +L_0x2cf4a60 .delay 1 (30000,30000,30000) L_0x2cf4a60/d; +L_0x2ac6110b6768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b67b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cf4b20/d .functor OR 1, L_0x2ac6110b6768, L_0x2ac6110b67b0, C4<0>, C4<0>; +L_0x2cf4b20 .delay 1 (30000,30000,30000) L_0x2cf4b20/d; +L_0x2ac6110b67f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6840 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cf52c0/d .functor OR 1, L_0x2ac6110b67f8, L_0x2ac6110b6840, C4<0>, C4<0>; +L_0x2cf52c0 .delay 1 (30000,30000,30000) L_0x2cf52c0/d; +L_0x2cf54c0/d .functor AND 1, L_0x2cfdef0, L_0x2cfe0e0, C4<1>, C4<1>; +L_0x2cf54c0 .delay 1 (30000,30000,30000) L_0x2cf54c0/d; +L_0x2ac6110b6888 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b68d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cf5580/d .functor OR 1, L_0x2ac6110b6888, L_0x2ac6110b68d0, C4<0>, C4<0>; +L_0x2cf5580 .delay 1 (30000,30000,30000) L_0x2cf5580/d; +L_0x2cf5780/d .functor NAND 1, L_0x2cfdef0, L_0x2cfe0e0, C4<1>, C4<1>; +L_0x2cf5780 .delay 1 (20000,20000,20000) L_0x2cf5780/d; +L_0x2ac6110b6918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cf5890/d .functor OR 1, L_0x2ac6110b6918, L_0x2ac6110b6960, C4<0>, C4<0>; +L_0x2cf5890 .delay 1 (30000,30000,30000) L_0x2cf5890/d; +L_0x2cf5a40/d .functor NOR 1, L_0x2cfdef0, L_0x2cfe0e0, C4<0>, C4<0>; +L_0x2cf5a40 .delay 1 (20000,20000,20000) L_0x2cf5a40/d; +L_0x2ac6110b69a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b69f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cf3e20/d .functor OR 1, L_0x2ac6110b69a8, L_0x2ac6110b69f0, C4<0>, C4<0>; +L_0x2cf3e20 .delay 1 (30000,30000,30000) L_0x2cf3e20/d; +L_0x2cf61f0/d .functor OR 1, L_0x2cfdef0, L_0x2cfe0e0, C4<0>, C4<0>; +L_0x2cf61f0 .delay 1 (30000,30000,30000) L_0x2cf61f0/d; +L_0x2ac6110b6a38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6a80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cf6690/d .functor OR 1, L_0x2ac6110b6a38, L_0x2ac6110b6a80, C4<0>, C4<0>; +L_0x2cf6690 .delay 1 (30000,30000,30000) L_0x2cf6690/d; +L_0x2cfddf0/d .functor NOT 1, L_0x2cfa050, C4<0>, C4<0>, C4<0>; +L_0x2cfddf0 .delay 1 (10000,10000,10000) L_0x2cfddf0/d; +v0x2ab9720_0 .net "A", 0 0, L_0x2cfdef0; 1 drivers +v0x2ab97e0_0 .net "A_", 0 0, L_0x2cf39f0; 1 drivers +v0x2ab98a0_0 .net "B", 0 0, L_0x2cfe0e0; 1 drivers +v0x2ab9970_0 .net "B_", 0 0, L_0x2cf3b50; 1 drivers +v0x2ab9a10_0 .net *"_s11", 0 0, L_0x2cf4b20; 1 drivers +v0x2ab9b00_0 .net/2s *"_s13", 0 0, L_0x2ac6110b6768; 1 drivers +v0x2ab9bc0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b67b0; 1 drivers +v0x2ab9ca0_0 .net *"_s19", 0 0, L_0x2cf52c0; 1 drivers +v0x2ab9d80_0 .net/2s *"_s21", 0 0, L_0x2ac6110b67f8; 1 drivers +v0x2ab9ef0_0 .net/2s *"_s23", 0 0, L_0x2ac6110b6840; 1 drivers +v0x2ab9fd0_0 .net *"_s25", 0 0, L_0x2cf54c0; 1 drivers +v0x2aba0b0_0 .net *"_s28", 0 0, L_0x2cf5580; 1 drivers +v0x2aba190_0 .net/2s *"_s30", 0 0, L_0x2ac6110b6888; 1 drivers +v0x2aba270_0 .net/2s *"_s32", 0 0, L_0x2ac6110b68d0; 1 drivers +v0x2aba350_0 .net *"_s34", 0 0, L_0x2cf5780; 1 drivers +v0x2aba430_0 .net *"_s37", 0 0, L_0x2cf5890; 1 drivers +v0x2aba510_0 .net/2s *"_s39", 0 0, L_0x2ac6110b6918; 1 drivers +v0x2aba6c0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b6960; 1 drivers +v0x2aba760_0 .net *"_s43", 0 0, L_0x2cf5a40; 1 drivers +v0x2aba840_0 .net *"_s46", 0 0, L_0x2cf3e20; 1 drivers +v0x2aba920_0 .net/2s *"_s48", 0 0, L_0x2ac6110b69a8; 1 drivers +v0x2abaa00_0 .net/2s *"_s50", 0 0, L_0x2ac6110b69f0; 1 drivers +v0x2abaae0_0 .net *"_s52", 0 0, L_0x2cf61f0; 1 drivers +v0x2ababc0_0 .net *"_s56", 0 0, L_0x2cf6690; 1 drivers +v0x2abaca0_0 .net/2s *"_s59", 0 0, L_0x2ac6110b6a38; 1 drivers +v0x2abad80_0 .net/2s *"_s61", 0 0, L_0x2ac6110b6a80; 1 drivers +v0x2abae60_0 .net *"_s8", 0 0, L_0x2cf4a60; 1 drivers +v0x2abaf40_0 .net "carryin", 0 0, L_0x2cfe210; 1 drivers +v0x2abafe0_0 .net "carryout", 0 0, L_0x2cfda90; 1 drivers +v0x2abb080_0 .net "carryouts", 7 0, L_0x2cf6300; 1 drivers +v0x2abb190_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2abb250_0 .net "result", 0 0, L_0x2cfa050; 1 drivers +v0x2abb340_0 .net "results", 7 0, L_0x2cf5f70; 1 drivers +v0x2aba620_0 .net "zero", 0 0, L_0x2cfddf0; 1 drivers +LS_0x2cf5f70_0_0 .concat8 [ 1 1 1 1], L_0x2cf3f30, L_0x2cf45b0, L_0x2cf4a60, L_0x2cf52c0; +LS_0x2cf5f70_0_4 .concat8 [ 1 1 1 1], L_0x2cf54c0, L_0x2cf5780, L_0x2cf5a40, L_0x2cf61f0; +L_0x2cf5f70 .concat8 [ 4 4 0 0], LS_0x2cf5f70_0_0, LS_0x2cf5f70_0_4; +LS_0x2cf6300_0_0 .concat8 [ 1 1 1 1], L_0x2cf4230, L_0x2cf4900, L_0x2cf4b20, L_0x2cf5110; +LS_0x2cf6300_0_4 .concat8 [ 1 1 1 1], L_0x2cf5580, L_0x2cf5890, L_0x2cf3e20, L_0x2cf6690; +L_0x2cf6300 .concat8 [ 4 4 0 0], LS_0x2cf6300_0_0, LS_0x2cf6300_0_4; +S_0x276a4d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x278ed50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12166c0/d .functor OR 1, L_0x12161a0, L_0x1216560, C4<0>, C4<0>; -L_0x12166c0 .delay 1 (30000,30000,30000) L_0x12166c0/d; -v0xb9ead0_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers -v0xb9eb90_0 .net "b", 0 0, L_0x121f870; alias, 1 drivers -v0xcdcfd0_0 .net "c1", 0 0, L_0x12161a0; 1 drivers -v0xcdd0d0_0 .net "c2", 0 0, L_0x1216560; 1 drivers -v0xf93560_0 .net "carryin", 0 0, L_0x121f9a0; alias, 1 drivers -v0xf93650_0 .net "carryout", 0 0, L_0x12166c0; 1 drivers -v0xf721e0_0 .net "s1", 0 0, L_0x1213500; 1 drivers -v0xf722d0_0 .net "sum", 0 0, L_0x1216410; 1 drivers -S_0xbf1eb0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xc01d00; +L_0x2cf4230/d .functor OR 1, L_0x2cf3db0, L_0x2cf4120, C4<0>, C4<0>; +L_0x2cf4230 .delay 1 (30000,30000,30000) L_0x2cf4230/d; +v0x26f7500_0 .net "a", 0 0, L_0x2cfdef0; alias, 1 drivers +v0x26f75c0_0 .net "b", 0 0, L_0x2cfe0e0; alias, 1 drivers +v0x26b6860_0 .net "c1", 0 0, L_0x2cf3db0; 1 drivers +v0x26b6960_0 .net "c2", 0 0, L_0x2cf4120; 1 drivers +v0x26d5680_0 .net "carryin", 0 0, L_0x2cfe210; alias, 1 drivers +v0x26d5770_0 .net "carryout", 0 0, L_0x2cf4230; 1 drivers +v0x268e390_0 .net "s1", 0 0, L_0x2cf3d40; 1 drivers +v0x268e480_0 .net "sum", 0 0, L_0x2cf3f30; 1 drivers +S_0x2758eb0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x276a4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1213500/d .functor XOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; -L_0x1213500 .delay 1 (30000,30000,30000) L_0x1213500/d; -L_0x12161a0/d .functor AND 1, L_0x121f680, L_0x121f870, C4<1>, C4<1>; -L_0x12161a0 .delay 1 (30000,30000,30000) L_0x12161a0/d; -v0xbf1bf0_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers -v0xbe08a0_0 .net "b", 0 0, L_0x121f870; alias, 1 drivers -v0xbe0960_0 .net "carryout", 0 0, L_0x12161a0; alias, 1 drivers -v0xbd0a50_0 .net "sum", 0 0, L_0x1213500; alias, 1 drivers -S_0xbd06d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xc01d00; +L_0x2cf3d40/d .functor XOR 1, L_0x2cfdef0, L_0x2cfe0e0, C4<0>, C4<0>; +L_0x2cf3d40 .delay 1 (30000,30000,30000) L_0x2cf3d40/d; +L_0x2cf3db0/d .functor AND 1, L_0x2cfdef0, L_0x2cfe0e0, C4<1>, C4<1>; +L_0x2cf3db0 .delay 1 (30000,30000,30000) L_0x2cf3db0/d; +v0x2745950_0 .net "a", 0 0, L_0x2cfdef0; alias, 1 drivers +v0x2745a10_0 .net "b", 0 0, L_0x2cfe0e0; alias, 1 drivers +v0x27455d0_0 .net "carryout", 0 0, L_0x2cf3db0; alias, 1 drivers +v0x2745670_0 .net "sum", 0 0, L_0x2cf3d40; alias, 1 drivers +S_0x2740ba0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x276a4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1216410/d .functor XOR 1, L_0x1213500, L_0x121f9a0, C4<0>, C4<0>; -L_0x1216410 .delay 1 (30000,30000,30000) L_0x1216410/d; -L_0x1216560/d .functor AND 1, L_0x1213500, L_0x121f9a0, C4<1>, C4<1>; -L_0x1216560 .delay 1 (30000,30000,30000) L_0x1216560/d; -v0xbbf480_0 .net "a", 0 0, L_0x1213500; alias, 1 drivers -v0xbb0220_0 .net "b", 0 0, L_0x121f9a0; alias, 1 drivers -v0xbb02c0_0 .net "carryout", 0 0, L_0x1216560; alias, 1 drivers -v0xbafe70_0 .net "sum", 0 0, L_0x1216410; alias, 1 drivers -S_0xb84020 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xc13330; +L_0x2cf3f30/d .functor XOR 1, L_0x2cf3d40, L_0x2cfe210, C4<0>, C4<0>; +L_0x2cf3f30 .delay 1 (30000,30000,30000) L_0x2cf3f30/d; +L_0x2cf4120/d .functor AND 1, L_0x2cf3d40, L_0x2cfe210, C4<1>, C4<1>; +L_0x2cf4120 .delay 1 (30000,30000,30000) L_0x2cf4120/d; +v0x26ffde0_0 .net "a", 0 0, L_0x2cf3d40; alias, 1 drivers +v0x271c000_0 .net "b", 0 0, L_0x2cfe210; alias, 1 drivers +v0x271c0a0_0 .net "carryout", 0 0, L_0x2cf4120; alias, 1 drivers +v0x26db320_0 .net "sum", 0 0, L_0x2cf3f30; alias, 1 drivers +S_0x268e010 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x278ed50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xcdfa30_0 .net "ands", 7 0, L_0x121d220; 1 drivers -v0xcdfaf0_0 .net "in", 7 0, L_0x1353280; alias, 1 drivers -v0xcbe660_0 .net "out", 0 0, L_0x121f220; alias, 1 drivers -v0xcbe700_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xb79a00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xb84020; +v0x2a47630_0 .net "ands", 7 0, L_0x2cfba90; 1 drivers +v0x2a47740_0 .net "in", 7 0, L_0x2cf6300; alias, 1 drivers +v0x2990120_0 .net "out", 0 0, L_0x2cfda90; alias, 1 drivers +v0x29901c0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x267ceb0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x268e010; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xa807e0_0 .net "A", 7 0, L_0x1353280; alias, 1 drivers -v0xa760e0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xa761c0_0 .net *"_s0", 0 0, L_0x121bb40; 1 drivers -v0xa6bb10_0 .net *"_s12", 0 0, L_0x121c4b0; 1 drivers -v0xa6bbf0_0 .net *"_s16", 0 0, L_0x121c810; 1 drivers -v0xa61580_0 .net *"_s20", 0 0, L_0x121cb20; 1 drivers -v0xa56ed0_0 .net *"_s24", 0 0, L_0x121cf10; 1 drivers -v0xa56fb0_0 .net *"_s28", 0 0, L_0x121cea0; 1 drivers -v0xa4c8b0_0 .net *"_s4", 0 0, L_0x121be50; 1 drivers -v0xa42290_0 .net *"_s8", 0 0, L_0x121c1a0; 1 drivers -v0xa42370_0 .net "out", 7 0, L_0x121d220; alias, 1 drivers -L_0x121bc00 .part L_0x1353280, 0, 1; -L_0x121bd60 .part v0x12010b0_0, 0, 1; -L_0x121bf10 .part L_0x1353280, 1, 1; -L_0x121c100 .part v0x12010b0_0, 1, 1; -L_0x121c260 .part L_0x1353280, 2, 1; -L_0x121c3c0 .part v0x12010b0_0, 2, 1; -L_0x121c570 .part L_0x1353280, 3, 1; -L_0x121c6d0 .part v0x12010b0_0, 3, 1; -L_0x121c8d0 .part L_0x1353280, 4, 1; -L_0x121ca30 .part v0x12010b0_0, 4, 1; -L_0x121cb90 .part L_0x1353280, 5, 1; -L_0x121ce00 .part v0x12010b0_0, 5, 1; -L_0x121cfd0 .part L_0x1353280, 6, 1; -L_0x121d130 .part v0x12010b0_0, 6, 1; -LS_0x121d220_0_0 .concat8 [ 1 1 1 1], L_0x121bb40, L_0x121be50, L_0x121c1a0, L_0x121c4b0; -LS_0x121d220_0_4 .concat8 [ 1 1 1 1], L_0x121c810, L_0x121cb20, L_0x121cf10, L_0x121cea0; -L_0x121d220 .concat8 [ 4 4 0 0], LS_0x121d220_0_0, LS_0x121d220_0_4; -L_0x121d5e0 .part L_0x1353280, 7, 1; -L_0x121d7d0 .part v0x12010b0_0, 7, 1; -S_0xb64dc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xb6f510 .param/l "i" 0 4 54, +C4<00>; -L_0x121bb40/d .functor AND 1, L_0x121bc00, L_0x121bd60, C4<1>, C4<1>; -L_0x121bb40 .delay 1 (30000,30000,30000) L_0x121bb40/d; -v0xb5a830_0 .net *"_s0", 0 0, L_0x121bc00; 1 drivers -v0xb50180_0 .net *"_s1", 0 0, L_0x121bd60; 1 drivers -S_0xb45b60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xb3b540 .param/l "i" 0 4 54, +C4<01>; -L_0x121be50/d .functor AND 1, L_0x121bf10, L_0x121c100, C4<1>, C4<1>; -L_0x121be50 .delay 1 (30000,30000,30000) L_0x121be50/d; -v0xb3b600_0 .net *"_s0", 0 0, L_0x121bf10; 1 drivers -v0xb30f20_0 .net *"_s1", 0 0, L_0x121c100; 1 drivers -S_0xb26900 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xb31070 .param/l "i" 0 4 54, +C4<010>; -L_0x121c1a0/d .functor AND 1, L_0x121c260, L_0x121c3c0, C4<1>, C4<1>; -L_0x121c1a0 .delay 1 (30000,30000,30000) L_0x121c1a0/d; -v0xb1c350_0 .net *"_s0", 0 0, L_0x121c260; 1 drivers -v0xb11cc0_0 .net *"_s1", 0 0, L_0x121c3c0; 1 drivers -S_0xb076a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xb11da0 .param/l "i" 0 4 54, +C4<011>; -L_0x121c4b0/d .functor AND 1, L_0x121c570, L_0x121c6d0, C4<1>, C4<1>; -L_0x121c4b0 .delay 1 (30000,30000,30000) L_0x121c4b0/d; -v0xafd080_0 .net *"_s0", 0 0, L_0x121c570; 1 drivers -v0xafd180_0 .net *"_s1", 0 0, L_0x121c6d0; 1 drivers -S_0xaf2a60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xae8500 .param/l "i" 0 4 54, +C4<0100>; -L_0x121c810/d .functor AND 1, L_0x121c8d0, L_0x121ca30, C4<1>, C4<1>; -L_0x121c810 .delay 1 (30000,30000,30000) L_0x121c810/d; -v0xadde20_0 .net *"_s0", 0 0, L_0x121c8d0; 1 drivers -v0xaddf00_0 .net *"_s1", 0 0, L_0x121ca30; 1 drivers -S_0xad3800 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xac9250 .param/l "i" 0 4 54, +C4<0101>; -L_0x121cb20/d .functor AND 1, L_0x121cb90, L_0x121ce00, C4<1>, C4<1>; -L_0x121cb20 .delay 1 (30000,30000,30000) L_0x121cb20/d; -v0xabebc0_0 .net *"_s0", 0 0, L_0x121cb90; 1 drivers -v0xabeca0_0 .net *"_s1", 0 0, L_0x121ce00; 1 drivers -S_0xab45a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xaa9f80 .param/l "i" 0 4 54, +C4<0110>; -L_0x121cf10/d .functor AND 1, L_0x121cfd0, L_0x121d130, C4<1>, C4<1>; -L_0x121cf10 .delay 1 (30000,30000,30000) L_0x121cf10/d; -v0xaaa040_0 .net *"_s0", 0 0, L_0x121cfd0; 1 drivers -v0xa9f960_0 .net *"_s1", 0 0, L_0x121d130; 1 drivers -S_0xa95340 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xb79a00; - .timescale -9 -12; -P_0xa9fab0 .param/l "i" 0 4 54, +C4<0111>; -L_0x121cea0/d .functor AND 1, L_0x121d5e0, L_0x121d7d0, C4<1>, C4<1>; -L_0x121cea0 .delay 1 (30000,30000,30000) L_0x121cea0/d; -v0xa8adb0_0 .net *"_s0", 0 0, L_0x121d5e0; 1 drivers -v0xa80700_0 .net *"_s1", 0 0, L_0x121d7d0; 1 drivers -S_0xc9be60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xb84020; +v0x2598be0_0 .net "A", 7 0, L_0x2cf6300; alias, 1 drivers +v0x258e4e0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x258e5a0_0 .net *"_s0", 0 0, L_0x2cfa3b0; 1 drivers +v0x2583ec0_0 .net *"_s12", 0 0, L_0x2cfad20; 1 drivers +v0x2583fa0_0 .net *"_s16", 0 0, L_0x2cfb080; 1 drivers +v0x2579930_0 .net *"_s20", 0 0, L_0x2cfb450; 1 drivers +v0x256f280_0 .net *"_s24", 0 0, L_0x2cfb780; 1 drivers +v0x256f360_0 .net *"_s28", 0 0, L_0x2cfb710; 1 drivers +v0x2564c60_0 .net *"_s4", 0 0, L_0x2cfa700; 1 drivers +v0x255a640_0 .net *"_s8", 0 0, L_0x2cfaa10; 1 drivers +v0x255a720_0 .net "out", 7 0, L_0x2cfba90; alias, 1 drivers +L_0x2cfa470 .part L_0x2cf6300, 0, 1; +L_0x2cfa660 .part v0x2cdd2e0_0, 0, 1; +L_0x2cfa7c0 .part L_0x2cf6300, 1, 1; +L_0x2cfa920 .part v0x2cdd2e0_0, 1, 1; +L_0x2cfaad0 .part L_0x2cf6300, 2, 1; +L_0x2cfac30 .part v0x2cdd2e0_0, 2, 1; +L_0x2cfade0 .part L_0x2cf6300, 3, 1; +L_0x2cfaf40 .part v0x2cdd2e0_0, 3, 1; +L_0x2cfb140 .part L_0x2cf6300, 4, 1; +L_0x2cfb3b0 .part v0x2cdd2e0_0, 4, 1; +L_0x2cfb4c0 .part L_0x2cf6300, 5, 1; +L_0x2cfb620 .part v0x2cdd2e0_0, 5, 1; +L_0x2cfb840 .part L_0x2cf6300, 6, 1; +L_0x2cfb9a0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2cfba90_0_0 .concat8 [ 1 1 1 1], L_0x2cfa3b0, L_0x2cfa700, L_0x2cfaa10, L_0x2cfad20; +LS_0x2cfba90_0_4 .concat8 [ 1 1 1 1], L_0x2cfb080, L_0x2cfb450, L_0x2cfb780, L_0x2cfb710; +L_0x2cfba90 .concat8 [ 4 4 0 0], LS_0x2cfba90_0_0, LS_0x2cfba90_0_4; +L_0x2cfbe50 .part L_0x2cf6300, 7, 1; +L_0x2cfc040 .part v0x2cdd2e0_0, 7, 1; +S_0x2669590 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x2669a20 .param/l "i" 0 4 54, +C4<00>; +L_0x2cfa3b0/d .functor AND 1, L_0x2cfa470, L_0x2cfa660, C4<1>, C4<1>; +L_0x2cfa3b0 .delay 1 (30000,30000,30000) L_0x2cfa3b0/d; +v0x2644da0_0 .net *"_s0", 0 0, L_0x2cfa470; 1 drivers +v0x2644990_0 .net *"_s1", 0 0, L_0x2cfa660; 1 drivers +S_0x263ffa0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x2644ae0 .param/l "i" 0 4 54, +C4<01>; +L_0x2cfa700/d .functor AND 1, L_0x2cfa7c0, L_0x2cfa920, C4<1>, C4<1>; +L_0x2cfa700 .delay 1 (30000,30000,30000) L_0x2cfa700/d; +v0x25ff0f0_0 .net *"_s0", 0 0, L_0x2cfa7c0; 1 drivers +v0x261b3e0_0 .net *"_s1", 0 0, L_0x2cfa920; 1 drivers +S_0x25db110 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x261b4c0 .param/l "i" 0 4 54, +C4<010>; +L_0x2cfaa10/d .functor AND 1, L_0x2cfaad0, L_0x2cfac30, C4<1>, C4<1>; +L_0x2cfaa10 .delay 1 (30000,30000,30000) L_0x2cfaa10/d; +v0x25f7350_0 .net *"_s0", 0 0, L_0x2cfaad0; 1 drivers +v0x25f7410_0 .net *"_s1", 0 0, L_0x2cfac30; 1 drivers +S_0x28461b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x29b4440 .param/l "i" 0 4 54, +C4<011>; +L_0x2cfad20/d .functor AND 1, L_0x2cfade0, L_0x2cfaf40, C4<1>, C4<1>; +L_0x2cfad20 .delay 1 (30000,30000,30000) L_0x2cfad20/d; +v0x29b4500_0 .net *"_s0", 0 0, L_0x2cfade0; 1 drivers +v0x298f990_0 .net *"_s1", 0 0, L_0x2cfaf40; 1 drivers +S_0x296add0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x2946290 .param/l "i" 0 4 54, +C4<0100>; +L_0x2cfb080/d .functor AND 1, L_0x2cfb140, L_0x2cfb3b0, C4<1>, C4<1>; +L_0x2cfb080 .delay 1 (30000,30000,30000) L_0x2cfb080/d; +v0x2946370_0 .net *"_s0", 0 0, L_0x2cfb140; 1 drivers +v0x28b37d0_0 .net *"_s1", 0 0, L_0x2cfb3b0; 1 drivers +S_0x288ed80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x286a170 .param/l "i" 0 4 54, +C4<0101>; +L_0x2cfb450/d .functor AND 1, L_0x2cfb4c0, L_0x2cfb620, C4<1>, C4<1>; +L_0x2cfb450 .delay 1 (30000,30000,30000) L_0x2cfb450/d; +v0x286a250_0 .net *"_s0", 0 0, L_0x2cfb4c0; 1 drivers +v0x2845680_0 .net *"_s1", 0 0, L_0x2cfb620; 1 drivers +S_0x25cc9a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x28457b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2cfb780/d .functor AND 1, L_0x2cfb840, L_0x2cfb9a0, C4<1>, C4<1>; +L_0x2cfb780 .delay 1 (30000,30000,30000) L_0x2cfb780/d; +v0x25c2410_0 .net *"_s0", 0 0, L_0x2cfb840; 1 drivers +v0x25b7d60_0 .net *"_s1", 0 0, L_0x2cfb9a0; 1 drivers +S_0x25ad740 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x267ceb0; + .timescale -9 -12; +P_0x25b7eb0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2cfb710/d .functor AND 1, L_0x2cfbe50, L_0x2cfc040, C4<1>, C4<1>; +L_0x2cfb710 .delay 1 (30000,30000,30000) L_0x2cfb710/d; +v0x25a31b0_0 .net *"_s0", 0 0, L_0x2cfbe50; 1 drivers +v0x2598b00_0 .net *"_s1", 0 0, L_0x2cfc040; 1 drivers +S_0x2550020 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x268e010; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x121f220/d .functor OR 1, L_0x121f2e0, L_0x121f490, C4<0>, C4<0>; -L_0x121f220 .delay 1 (30000,30000,30000) L_0x121f220/d; -v0xbf1890_0 .net *"_s10", 0 0, L_0x121f2e0; 1 drivers -v0xbd0330_0 .net *"_s12", 0 0, L_0x121f490; 1 drivers -v0xbd0410_0 .net "in", 7 0, L_0x121d220; alias, 1 drivers -v0xbafaa0_0 .net "ors", 1 0, L_0x121f040; 1 drivers -v0xbafb60_0 .net "out", 0 0, L_0x121f220; alias, 1 drivers -L_0x121e410 .part L_0x121d220, 0, 4; -L_0x121f040 .concat8 [ 1 1 0 0], L_0x121e100, L_0x121ed30; -L_0x121f180 .part L_0x121d220, 4, 4; -L_0x121f2e0 .part L_0x121f040, 0, 1; -L_0x121f490 .part L_0x121f040, 1, 1; -S_0xbf6f00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xc9be60; +L_0x2cfda90/d .functor OR 1, L_0x2cfdb50, L_0x2cfdd00, C4<0>, C4<0>; +L_0x2cfda90 .delay 1 (30000,30000,30000) L_0x2cfda90/d; +v0x249f850_0 .net *"_s10", 0 0, L_0x2cfdb50; 1 drivers +v0x249f930_0 .net *"_s12", 0 0, L_0x2cfdd00; 1 drivers +v0x24951e0_0 .net "in", 7 0, L_0x2cfba90; alias, 1 drivers +v0x24952a0_0 .net "ors", 1 0, L_0x2cfd8b0; 1 drivers +v0x248abc0_0 .net "out", 0 0, L_0x2cfda90; alias, 1 drivers +L_0x2cfcc80 .part L_0x2cfba90, 0, 4; +L_0x2cfd8b0 .concat8 [ 1 1 0 0], L_0x2cfc970, L_0x2cfd5a0; +L_0x2cfd9f0 .part L_0x2cfba90, 4, 4; +L_0x2cfdb50 .part L_0x2cfd8b0, 0, 1; +L_0x2cfdd00 .part L_0x2cfd8b0, 1, 1; +S_0x2545a00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2550020; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x121d8c0/d .functor OR 1, L_0x121d980, L_0x121dae0, C4<0>, C4<0>; -L_0x121d8c0 .delay 1 (30000,30000,30000) L_0x121d8c0/d; -L_0x121dd10/d .functor OR 1, L_0x121de20, L_0x121df80, C4<0>, C4<0>; -L_0x121dd10 .delay 1 (30000,30000,30000) L_0x121dd10/d; -L_0x121e100/d .functor OR 1, L_0x121e170, L_0x121e320, C4<0>, C4<0>; -L_0x121e100 .delay 1 (30000,30000,30000) L_0x121e100/d; -v0xbcf8e0_0 .net *"_s0", 0 0, L_0x121d8c0; 1 drivers -v0xf93cf0_0 .net *"_s10", 0 0, L_0x121de20; 1 drivers -v0xf93dd0_0 .net *"_s12", 0 0, L_0x121df80; 1 drivers -v0xf72970_0 .net *"_s14", 0 0, L_0x121e170; 1 drivers -v0xf72a50_0 .net *"_s16", 0 0, L_0x121e320; 1 drivers -v0xf515d0_0 .net *"_s3", 0 0, L_0x121d980; 1 drivers -v0xf51690_0 .net *"_s5", 0 0, L_0x121dae0; 1 drivers -v0xf30250_0 .net *"_s6", 0 0, L_0x121dd10; 1 drivers -v0xf30330_0 .net "in", 3 0, L_0x121e410; 1 drivers -v0xcfb860_0 .net "ors", 1 0, L_0x121dc20; 1 drivers -v0xcda400_0 .net "out", 0 0, L_0x121e100; 1 drivers -L_0x121d980 .part L_0x121e410, 0, 1; -L_0x121dae0 .part L_0x121e410, 1, 1; -L_0x121dc20 .concat8 [ 1 1 0 0], L_0x121d8c0, L_0x121dd10; -L_0x121de20 .part L_0x121e410, 2, 1; -L_0x121df80 .part L_0x121e410, 3, 1; -L_0x121e170 .part L_0x121dc20, 0, 1; -L_0x121e320 .part L_0x121dc20, 1, 1; -S_0xcb90b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xc9be60; +L_0x2cfc130/d .functor OR 1, L_0x2cfc1f0, L_0x2cfc350, C4<0>, C4<0>; +L_0x2cfc130 .delay 1 (30000,30000,30000) L_0x2cfc130/d; +L_0x2cfc580/d .functor OR 1, L_0x2cfc690, L_0x2cfc7f0, C4<0>, C4<0>; +L_0x2cfc580 .delay 1 (30000,30000,30000) L_0x2cfc580/d; +L_0x2cfc970/d .functor OR 1, L_0x2cfc9e0, L_0x2cfcb90, C4<0>, C4<0>; +L_0x2cfc970 .delay 1 (30000,30000,30000) L_0x2cfc970/d; +v0x253b4b0_0 .net *"_s0", 0 0, L_0x2cfc130; 1 drivers +v0x2530dc0_0 .net *"_s10", 0 0, L_0x2cfc690; 1 drivers +v0x2530ea0_0 .net *"_s12", 0 0, L_0x2cfc7f0; 1 drivers +v0x25267a0_0 .net *"_s14", 0 0, L_0x2cfc9e0; 1 drivers +v0x2526880_0 .net *"_s16", 0 0, L_0x2cfcb90; 1 drivers +v0x251c210_0 .net *"_s3", 0 0, L_0x2cfc1f0; 1 drivers +v0x2511b60_0 .net *"_s5", 0 0, L_0x2cfc350; 1 drivers +v0x2511c40_0 .net *"_s6", 0 0, L_0x2cfc580; 1 drivers +v0x2507540_0 .net "in", 3 0, L_0x2cfcc80; 1 drivers +v0x24fcf20_0 .net "ors", 1 0, L_0x2cfc490; 1 drivers +v0x24fd000_0 .net "out", 0 0, L_0x2cfc970; 1 drivers +L_0x2cfc1f0 .part L_0x2cfcc80, 0, 1; +L_0x2cfc350 .part L_0x2cfcc80, 1, 1; +L_0x2cfc490 .concat8 [ 1 1 0 0], L_0x2cfc130, L_0x2cfc580; +L_0x2cfc690 .part L_0x2cfcc80, 2, 1; +L_0x2cfc7f0 .part L_0x2cfcc80, 3, 1; +L_0x2cfc9e0 .part L_0x2cfc490, 0, 1; +L_0x2cfcb90 .part L_0x2cfc490, 1, 1; +S_0x24f2900 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2550020; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x121e540/d .functor OR 1, L_0x121e5b0, L_0x121e710, C4<0>, C4<0>; -L_0x121e540 .delay 1 (30000,30000,30000) L_0x121e540/d; -L_0x121e940/d .functor OR 1, L_0x121ea50, L_0x121ebb0, C4<0>, C4<0>; -L_0x121e940 .delay 1 (30000,30000,30000) L_0x121e940/d; -L_0x121ed30/d .functor OR 1, L_0x121eda0, L_0x121ef50, C4<0>, C4<0>; -L_0x121ed30 .delay 1 (30000,30000,30000) L_0x121ed30/d; -v0xcda520_0 .net *"_s0", 0 0, L_0x121e540; 1 drivers -v0xc97d10_0 .net *"_s10", 0 0, L_0x121ea50; 1 drivers -v0xc97df0_0 .net *"_s12", 0 0, L_0x121ebb0; 1 drivers -v0xc76950_0 .net *"_s14", 0 0, L_0x121eda0; 1 drivers -v0xc76a30_0 .net *"_s16", 0 0, L_0x121ef50; 1 drivers -v0xc55510_0 .net *"_s3", 0 0, L_0x121e5b0; 1 drivers -v0xc555f0_0 .net *"_s5", 0 0, L_0x121e710; 1 drivers -v0xc34040_0 .net *"_s6", 0 0, L_0x121e940; 1 drivers -v0xc34120_0 .net "in", 3 0, L_0x121f180; 1 drivers -v0xc12ce0_0 .net "ors", 1 0, L_0x121e850; 1 drivers -v0xbf1790_0 .net "out", 0 0, L_0x121ed30; 1 drivers -L_0x121e5b0 .part L_0x121f180, 0, 1; -L_0x121e710 .part L_0x121f180, 1, 1; -L_0x121e850 .concat8 [ 1 1 0 0], L_0x121e540, L_0x121e940; -L_0x121ea50 .part L_0x121f180, 2, 1; -L_0x121ebb0 .part L_0x121f180, 3, 1; -L_0x121eda0 .part L_0x121e850, 0, 1; -L_0x121ef50 .part L_0x121e850, 1, 1; -S_0xde3b20 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xc13330; +L_0x2cfcdb0/d .functor OR 1, L_0x2cfce20, L_0x2cfcf80, C4<0>, C4<0>; +L_0x2cfcdb0 .delay 1 (30000,30000,30000) L_0x2cfcdb0/d; +L_0x2cfd1b0/d .functor OR 1, L_0x2cfd2c0, L_0x2cfd420, C4<0>, C4<0>; +L_0x2cfd1b0 .delay 1 (30000,30000,30000) L_0x2cfd1b0/d; +L_0x2cfd5a0/d .functor OR 1, L_0x2cfd610, L_0x2cfd7c0, C4<0>, C4<0>; +L_0x2cfd5a0 .delay 1 (30000,30000,30000) L_0x2cfd5a0/d; +v0x24e8320_0 .net *"_s0", 0 0, L_0x2cfcdb0; 1 drivers +v0x24ddcc0_0 .net *"_s10", 0 0, L_0x2cfd2c0; 1 drivers +v0x24ddda0_0 .net *"_s12", 0 0, L_0x2cfd420; 1 drivers +v0x24d36a0_0 .net *"_s14", 0 0, L_0x2cfd610; 1 drivers +v0x24d3780_0 .net *"_s16", 0 0, L_0x2cfd7c0; 1 drivers +v0x24c9080_0 .net *"_s3", 0 0, L_0x2cfce20; 1 drivers +v0x24c9160_0 .net *"_s5", 0 0, L_0x2cfcf80; 1 drivers +v0x24bea60_0 .net *"_s6", 0 0, L_0x2cfd1b0; 1 drivers +v0x24beb20_0 .net "in", 3 0, L_0x2cfd9f0; 1 drivers +v0x24b4510_0 .net "ors", 1 0, L_0x2cfd0c0; 1 drivers +v0x24a9e20_0 .net "out", 0 0, L_0x2cfd5a0; 1 drivers +L_0x2cfce20 .part L_0x2cfd9f0, 0, 1; +L_0x2cfcf80 .part L_0x2cfd9f0, 1, 1; +L_0x2cfd0c0 .concat8 [ 1 1 0 0], L_0x2cfcdb0, L_0x2cfd1b0; +L_0x2cfd2c0 .part L_0x2cfd9f0, 2, 1; +L_0x2cfd420 .part L_0x2cfd9f0, 3, 1; +L_0x2cfd610 .part L_0x2cfd0c0, 0, 1; +L_0x2cfd7c0 .part L_0x2cfd0c0, 1, 1; +S_0x296b560 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x278ed50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xff28b0_0 .net "ands", 7 0, L_0x12197e0; 1 drivers -v0xff2950_0 .net "in", 7 0, L_0x1217c40; alias, 1 drivers -v0xff29f0_0 .net "out", 0 0, L_0x121b7e0; alias, 1 drivers -v0xff2a90_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xdc27c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xde3b20; +v0x23534e0_0 .net "ands", 7 0, L_0x2cf8050; 1 drivers +v0x23535f0_0 .net "in", 7 0, L_0x2cf5f70; alias, 1 drivers +v0x23536b0_0 .net "out", 0 0, L_0x2cfa050; alias, 1 drivers +v0x2353750_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2946a20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x296b560; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xf56e40_0 .net "A", 7 0, L_0x1217c40; alias, 1 drivers -v0xf359c0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xf35a80_0 .net *"_s0", 0 0, L_0x1217fd0; 1 drivers -v0xf14590_0 .net *"_s12", 0 0, L_0x1218990; 1 drivers -v0xf14670_0 .net *"_s16", 0 0, L_0x1218cf0; 1 drivers -v0xef31f0_0 .net *"_s20", 0 0, L_0x1219120; 1 drivers -v0xef32d0_0 .net *"_s24", 0 0, L_0x1219450; 1 drivers -v0xed1ea0_0 .net *"_s28", 0 0, L_0x12193e0; 1 drivers -v0xed1f80_0 .net *"_s4", 0 0, L_0x1218370; 1 drivers -v0xc7ad90_0 .net *"_s8", 0 0, L_0x1218680; 1 drivers -v0xc5ac80_0 .net "out", 7 0, L_0x12197e0; alias, 1 drivers -L_0x12180e0 .part L_0x1217c40, 0, 1; -L_0x12182d0 .part v0x12010b0_0, 0, 1; -L_0x1218430 .part L_0x1217c40, 1, 1; -L_0x1218590 .part v0x12010b0_0, 1, 1; -L_0x1218740 .part L_0x1217c40, 2, 1; -L_0x12188a0 .part v0x12010b0_0, 2, 1; -L_0x1218a50 .part L_0x1217c40, 3, 1; -L_0x1218bb0 .part v0x12010b0_0, 3, 1; -L_0x1218db0 .part L_0x1217c40, 4, 1; -L_0x1219020 .part v0x12010b0_0, 4, 1; -L_0x1219190 .part L_0x1217c40, 5, 1; -L_0x12192f0 .part v0x12010b0_0, 5, 1; -L_0x1219510 .part L_0x1217c40, 6, 1; -L_0x1219670 .part v0x12010b0_0, 6, 1; -LS_0x12197e0_0_0 .concat8 [ 1 1 1 1], L_0x1217fd0, L_0x1218370, L_0x1218680, L_0x1218990; -LS_0x12197e0_0_4 .concat8 [ 1 1 1 1], L_0x1218cf0, L_0x1219120, L_0x1219450, L_0x12193e0; -L_0x12197e0 .concat8 [ 4 4 0 0], LS_0x12197e0_0_0, LS_0x12197e0_0_4; -L_0x1219ba0 .part L_0x1217c40, 7, 1; -L_0x1219d90 .part v0x12010b0_0, 7, 1; -S_0xeadfd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xdc2940 .param/l "i" 0 4 54, +C4<00>; -L_0x1217fd0/d .functor AND 1, L_0x12180e0, L_0x12182d0, C4<1>, C4<1>; -L_0x1217fd0 .delay 1 (30000,30000,30000) L_0x1217fd0/d; -v0xe8cc90_0 .net *"_s0", 0 0, L_0x12180e0; 1 drivers -v0xe8cd70_0 .net *"_s1", 0 0, L_0x12182d0; 1 drivers -S_0xe6b910 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xe4a650 .param/l "i" 0 4 54, +C4<01>; -L_0x1218370/d .functor AND 1, L_0x1218430, L_0x1218590, C4<1>, C4<1>; -L_0x1218370 .delay 1 (30000,30000,30000) L_0x1218370/d; -v0xe4a710_0 .net *"_s0", 0 0, L_0x1218430; 1 drivers -v0xe292f0_0 .net *"_s1", 0 0, L_0x1218590; 1 drivers -S_0xe08020 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xe293d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1218680/d .functor AND 1, L_0x1218740, L_0x12188a0, C4<1>, C4<1>; -L_0x1218680 .delay 1 (30000,30000,30000) L_0x1218680/d; -v0xde6cd0_0 .net *"_s0", 0 0, L_0x1218740; 1 drivers -v0xde6db0_0 .net *"_s1", 0 0, L_0x12188a0; 1 drivers -S_0xdc5970 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xe29470 .param/l "i" 0 4 54, +C4<011>; -L_0x1218990/d .functor AND 1, L_0x1218a50, L_0x1218bb0, C4<1>, C4<1>; -L_0x1218990 .delay 1 (30000,30000,30000) L_0x1218990/d; -v0xda4630_0 .net *"_s0", 0 0, L_0x1218a50; 1 drivers -v0xda4710_0 .net *"_s1", 0 0, L_0x1218bb0; 1 drivers -S_0xd83240 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xd61ed0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1218cf0/d .functor AND 1, L_0x1218db0, L_0x1219020, C4<1>, C4<1>; -L_0x1218cf0 .delay 1 (30000,30000,30000) L_0x1218cf0/d; -v0xd61f90_0 .net *"_s0", 0 0, L_0x1218db0; 1 drivers -v0xd40ab0_0 .net *"_s1", 0 0, L_0x1219020; 1 drivers -S_0xd1f6c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xd40bb0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1219120/d .functor AND 1, L_0x1219190, L_0x12192f0, C4<1>, C4<1>; -L_0x1219120 .delay 1 (30000,30000,30000) L_0x1219120/d; -v0xcfe360_0 .net *"_s0", 0 0, L_0x1219190; 1 drivers -v0xcfe420_0 .net *"_s1", 0 0, L_0x12192f0; 1 drivers -S_0xcbd1a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xf98060 .param/l "i" 0 4 54, +C4<0110>; -L_0x1219450/d .functor AND 1, L_0x1219510, L_0x1219670, C4<1>, C4<1>; -L_0x1219450 .delay 1 (30000,30000,30000) L_0x1219450/d; -v0xf98120_0 .net *"_s0", 0 0, L_0x1219510; 1 drivers -v0xf96af0_0 .net *"_s1", 0 0, L_0x1219670; 1 drivers -S_0xf99460 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xdc27c0; - .timescale -9 -12; -P_0xf99600 .param/l "i" 0 4 54, +C4<0111>; -L_0x12193e0/d .functor AND 1, L_0x1219ba0, L_0x1219d90, C4<1>, C4<1>; -L_0x12193e0 .delay 1 (30000,30000,30000) L_0x12193e0/d; -v0xf96c20_0 .net *"_s0", 0 0, L_0x1219ba0; 1 drivers -v0xf56d60_0 .net *"_s1", 0 0, L_0x1219d90; 1 drivers -S_0xc383b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xde3b20; +v0x23343d0_0 .net "A", 7 0, L_0x2cf5f70; alias, 1 drivers +v0x2335ab0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2335b70_0 .net *"_s0", 0 0, L_0x2cf6840; 1 drivers +v0x2335c30_0 .net *"_s12", 0 0, L_0x2cf7200; 1 drivers +v0x2335d10_0 .net *"_s16", 0 0, L_0x2cf7560; 1 drivers +v0x2330d00_0 .net *"_s20", 0 0, L_0x2cf7990; 1 drivers +v0x2330de0_0 .net *"_s24", 0 0, L_0x2cf7cc0; 1 drivers +v0x2330ec0_0 .net *"_s28", 0 0, L_0x2cf7c50; 1 drivers +v0x2330fa0_0 .net *"_s4", 0 0, L_0x2cf6be0; 1 drivers +v0x2332890_0 .net *"_s8", 0 0, L_0x2cf6ef0; 1 drivers +v0x2332970_0 .net "out", 7 0, L_0x2cf8050; alias, 1 drivers +L_0x2cf6950 .part L_0x2cf5f70, 0, 1; +L_0x2cf6b40 .part v0x2cdd2e0_0, 0, 1; +L_0x2cf6ca0 .part L_0x2cf5f70, 1, 1; +L_0x2cf6e00 .part v0x2cdd2e0_0, 1, 1; +L_0x2cf6fb0 .part L_0x2cf5f70, 2, 1; +L_0x2cf7110 .part v0x2cdd2e0_0, 2, 1; +L_0x2cf72c0 .part L_0x2cf5f70, 3, 1; +L_0x2cf7420 .part v0x2cdd2e0_0, 3, 1; +L_0x2cf7620 .part L_0x2cf5f70, 4, 1; +L_0x2cf7890 .part v0x2cdd2e0_0, 4, 1; +L_0x2cf7a00 .part L_0x2cf5f70, 5, 1; +L_0x2cf7b60 .part v0x2cdd2e0_0, 5, 1; +L_0x2cf7d80 .part L_0x2cf5f70, 6, 1; +L_0x2cf7ee0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2cf8050_0_0 .concat8 [ 1 1 1 1], L_0x2cf6840, L_0x2cf6be0, L_0x2cf6ef0, L_0x2cf7200; +LS_0x2cf8050_0_4 .concat8 [ 1 1 1 1], L_0x2cf7560, L_0x2cf7990, L_0x2cf7cc0, L_0x2cf7c50; +L_0x2cf8050 .concat8 [ 4 4 0 0], LS_0x2cf8050_0_0, LS_0x2cf8050_0_4; +L_0x2cf8410 .part L_0x2cf5f70, 7, 1; +L_0x2cf8600 .part v0x2cdd2e0_0, 7, 1; +S_0x28b3f40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x288f510 .param/l "i" 0 4 54, +C4<00>; +L_0x2cf6840/d .functor AND 1, L_0x2cf6950, L_0x2cf6b40, C4<1>, C4<1>; +L_0x2cf6840 .delay 1 (30000,30000,30000) L_0x2cf6840/d; +v0x288f5f0_0 .net *"_s0", 0 0, L_0x2cf6950; 1 drivers +v0x286a900_0 .net *"_s1", 0 0, L_0x2cf6b40; 1 drivers +S_0x2845e10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x286aa50 .param/l "i" 0 4 54, +C4<01>; +L_0x2cf6be0/d .functor AND 1, L_0x2cf6ca0, L_0x2cf6e00, C4<1>, C4<1>; +L_0x2cf6be0 .delay 1 (30000,30000,30000) L_0x2cf6be0/d; +v0x278ea20_0 .net *"_s0", 0 0, L_0x2cf6ca0; 1 drivers +v0x2769db0_0 .net *"_s1", 0 0, L_0x2cf6e00; 1 drivers +S_0x2745230 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x2769e90 .param/l "i" 0 4 54, +C4<010>; +L_0x2cf6ef0/d .functor AND 1, L_0x2cf6fb0, L_0x2cf7110, C4<1>, C4<1>; +L_0x2cf6ef0 .delay 1 (30000,30000,30000) L_0x2cf6ef0/d; +v0x268dc70_0 .net *"_s0", 0 0, L_0x2cf6fb0; 1 drivers +v0x268dd50_0 .net *"_s1", 0 0, L_0x2cf7110; 1 drivers +S_0x26691f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x26445f0 .param/l "i" 0 4 54, +C4<011>; +L_0x2cf7200/d .functor AND 1, L_0x2cf72c0, L_0x2cf7420, C4<1>, C4<1>; +L_0x2cf7200 .delay 1 (30000,30000,30000) L_0x2cf7200/d; +v0x26446b0_0 .net *"_s0", 0 0, L_0x2cf72c0; 1 drivers +v0x28d7ec0_0 .net *"_s1", 0 0, L_0x2cf7420; 1 drivers +S_0x2a47110 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x28d7ff0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2cf7560/d .functor AND 1, L_0x2cf7620, L_0x2cf7890, C4<1>, C4<1>; +L_0x2cf7560 .delay 1 (30000,30000,30000) L_0x2cf7560/d; +v0x2a6b690_0 .net *"_s0", 0 0, L_0x2cf7620; 1 drivers +v0x2a6b770_0 .net *"_s1", 0 0, L_0x2cf7890; 1 drivers +S_0x2a6c4c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x2a6c6d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2cf7990/d .functor AND 1, L_0x2cf7a00, L_0x2cf7b60, C4<1>, C4<1>; +L_0x2cf7990 .delay 1 (30000,30000,30000) L_0x2cf7990/d; +v0x2a6b850_0 .net *"_s0", 0 0, L_0x2cf7a00; 1 drivers +v0x2348a30_0 .net *"_s1", 0 0, L_0x2cf7b60; 1 drivers +S_0x2348b10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x2348d20 .param/l "i" 0 4 54, +C4<0110>; +L_0x2cf7cc0/d .functor AND 1, L_0x2cf7d80, L_0x2cf7ee0, C4<1>, C4<1>; +L_0x2cf7cc0 .delay 1 (30000,30000,30000) L_0x2cf7cc0/d; +v0x2342800_0 .net *"_s0", 0 0, L_0x2cf7d80; 1 drivers +v0x23428e0_0 .net *"_s1", 0 0, L_0x2cf7ee0; 1 drivers +S_0x23429c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2946a20; + .timescale -9 -12; +P_0x2a6c790 .param/l "i" 0 4 54, +C4<0111>; +L_0x2cf7c50/d .functor AND 1, L_0x2cf8410, L_0x2cf8600, C4<1>, C4<1>; +L_0x2cf7c50 .delay 1 (30000,30000,30000) L_0x2cf7c50/d; +v0x2334210_0 .net *"_s0", 0 0, L_0x2cf8410; 1 drivers +v0x23342f0_0 .net *"_s1", 0 0, L_0x2cf8600; 1 drivers +S_0x2332ad0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x296b560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x121b7e0/d .functor OR 1, L_0x121b8a0, L_0x121ba50, C4<0>, C4<0>; -L_0x121b7e0 .delay 1 (30000,30000,30000) L_0x121b7e0/d; -v0xff2590_0 .net *"_s10", 0 0, L_0x121b8a0; 1 drivers -v0xff2630_0 .net *"_s12", 0 0, L_0x121ba50; 1 drivers -v0xff26d0_0 .net "in", 7 0, L_0x12197e0; alias, 1 drivers -v0xff2770_0 .net "ors", 1 0, L_0x121b600; 1 drivers -v0xff2810_0 .net "out", 0 0, L_0x121b7e0; alias, 1 drivers -L_0x121a9d0 .part L_0x12197e0, 0, 4; -L_0x121b600 .concat8 [ 1 1 0 0], L_0x121a6c0, L_0x121b2f0; -L_0x121b740 .part L_0x12197e0, 4, 4; -L_0x121b8a0 .part L_0x121b600, 0, 1; -L_0x121ba50 .part L_0x121b600, 1, 1; -S_0xc16f80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xc383b0; +L_0x2cfa050/d .functor OR 1, L_0x2cfa110, L_0x2cfa2c0, C4<0>, C4<0>; +L_0x2cfa050 .delay 1 (30000,30000,30000) L_0x2cfa050/d; +v0x232f6b0_0 .net *"_s10", 0 0, L_0x2cfa110; 1 drivers +v0x233ead0_0 .net *"_s12", 0 0, L_0x2cfa2c0; 1 drivers +v0x233eb90_0 .net "in", 7 0, L_0x2cf8050; alias, 1 drivers +v0x233ec30_0 .net "ors", 1 0, L_0x2cf9e70; 1 drivers +v0x233ecf0_0 .net "out", 0 0, L_0x2cfa050; alias, 1 drivers +L_0x2cf9240 .part L_0x2cf8050, 0, 4; +L_0x2cf9e70 .concat8 [ 1 1 0 0], L_0x2cf8f30, L_0x2cf9b60; +L_0x2cf9fb0 .part L_0x2cf8050, 4, 4; +L_0x2cfa110 .part L_0x2cf9e70, 0, 1; +L_0x2cfa2c0 .part L_0x2cf9e70, 1, 1; +S_0x23373c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2332ad0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1219e80/d .functor OR 1, L_0x1219f40, L_0x121a0a0, C4<0>, C4<0>; -L_0x1219e80 .delay 1 (30000,30000,30000) L_0x1219e80/d; -L_0x121a2d0/d .functor OR 1, L_0x121a3e0, L_0x121a540, C4<0>, C4<0>; -L_0x121a2d0 .delay 1 (30000,30000,30000) L_0x121a2d0/d; -L_0x121a6c0/d .functor OR 1, L_0x121a730, L_0x121a8e0, C4<0>, C4<0>; -L_0x121a6c0 .delay 1 (30000,30000,30000) L_0x121a6c0/d; -v0xc5ade0_0 .net *"_s0", 0 0, L_0x1219e80; 1 drivers -v0xc18380_0 .net *"_s10", 0 0, L_0x121a3e0; 1 drivers -v0xc18460_0 .net *"_s12", 0 0, L_0x121a540; 1 drivers -v0xbf5b00_0 .net *"_s14", 0 0, L_0x121a730; 1 drivers -v0xbf5be0_0 .net *"_s16", 0 0, L_0x121a8e0; 1 drivers -v0xbd4620_0 .net *"_s3", 0 0, L_0x1219f40; 1 drivers -v0xbd4700_0 .net *"_s5", 0 0, L_0x121a0a0; 1 drivers -v0xbd5a20_0 .net *"_s6", 0 0, L_0x121a2d0; 1 drivers -v0xbd5b00_0 .net "in", 3 0, L_0x121a9d0; 1 drivers -v0xbb32b0_0 .net "ors", 1 0, L_0x121a1e0; 1 drivers -v0xb92a30_0 .net "out", 0 0, L_0x121a6c0; 1 drivers -L_0x1219f40 .part L_0x121a9d0, 0, 1; -L_0x121a0a0 .part L_0x121a9d0, 1, 1; -L_0x121a1e0 .concat8 [ 1 1 0 0], L_0x1219e80, L_0x121a2d0; -L_0x121a3e0 .part L_0x121a9d0, 2, 1; -L_0x121a540 .part L_0x121a9d0, 3, 1; -L_0x121a730 .part L_0x121a1e0, 0, 1; -L_0x121a8e0 .part L_0x121a1e0, 1, 1; -S_0xb93e30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xc383b0; +L_0x2cf86f0/d .functor OR 1, L_0x2cf87b0, L_0x2cf8910, C4<0>, C4<0>; +L_0x2cf86f0 .delay 1 (30000,30000,30000) L_0x2cf86f0/d; +L_0x2cf8b40/d .functor OR 1, L_0x2cf8c50, L_0x2cf8db0, C4<0>, C4<0>; +L_0x2cf8b40 .delay 1 (30000,30000,30000) L_0x2cf8b40/d; +L_0x2cf8f30/d .functor OR 1, L_0x2cf8fa0, L_0x2cf9150, C4<0>, C4<0>; +L_0x2cf8f30 .delay 1 (30000,30000,30000) L_0x2cf8f30/d; +v0x23375d0_0 .net *"_s0", 0 0, L_0x2cf86f0; 1 drivers +v0x23376d0_0 .net *"_s10", 0 0, L_0x2cf8c50; 1 drivers +v0x233cfe0_0 .net *"_s12", 0 0, L_0x2cf8db0; 1 drivers +v0x233d0a0_0 .net *"_s14", 0 0, L_0x2cf8fa0; 1 drivers +v0x233d180_0 .net *"_s16", 0 0, L_0x2cf9150; 1 drivers +v0x233d2b0_0 .net *"_s3", 0 0, L_0x2cf87b0; 1 drivers +v0x233be10_0 .net *"_s5", 0 0, L_0x2cf8910; 1 drivers +v0x233bef0_0 .net *"_s6", 0 0, L_0x2cf8b40; 1 drivers +v0x233bfd0_0 .net "in", 3 0, L_0x2cf9240; 1 drivers +v0x2340c30_0 .net "ors", 1 0, L_0x2cf8a50; 1 drivers +v0x2340d10_0 .net "out", 0 0, L_0x2cf8f30; 1 drivers +L_0x2cf87b0 .part L_0x2cf9240, 0, 1; +L_0x2cf8910 .part L_0x2cf9240, 1, 1; +L_0x2cf8a50 .concat8 [ 1 1 0 0], L_0x2cf86f0, L_0x2cf8b40; +L_0x2cf8c50 .part L_0x2cf9240, 2, 1; +L_0x2cf8db0 .part L_0x2cf9240, 3, 1; +L_0x2cf8fa0 .part L_0x2cf8a50, 0, 1; +L_0x2cf9150 .part L_0x2cf8a50, 1, 1; +S_0x2340e30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2332ad0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x121ab00/d .functor OR 1, L_0x121ab70, L_0x121acd0, C4<0>, C4<0>; -L_0x121ab00 .delay 1 (30000,30000,30000) L_0x121ab00/d; -L_0x121af00/d .functor OR 1, L_0x121b010, L_0x121b170, C4<0>, C4<0>; -L_0x121af00 .delay 1 (30000,30000,30000) L_0x121af00/d; -L_0x121b2f0/d .functor OR 1, L_0x121b360, L_0x121b510, C4<0>, C4<0>; -L_0x121b2f0 .delay 1 (30000,30000,30000) L_0x121b2f0/d; -v0xb92b50_0 .net *"_s0", 0 0, L_0x121ab00; 1 drivers -v0xcbbad0_0 .net *"_s10", 0 0, L_0x121b010; 1 drivers -v0xcbbb90_0 .net *"_s12", 0 0, L_0x121b170; 1 drivers -v0xcbbc50_0 .net *"_s14", 0 0, L_0x121b360; 1 drivers -v0xfb7440_0 .net *"_s16", 0 0, L_0x121b510; 1 drivers -v0xfb7570_0 .net *"_s3", 0 0, L_0x121ab70; 1 drivers -v0xfb4600_0 .net *"_s5", 0 0, L_0x121acd0; 1 drivers -v0xfb46e0_0 .net *"_s6", 0 0, L_0x121af00; 1 drivers -v0xfb47c0_0 .net "in", 3 0, L_0x121b740; 1 drivers -v0xfb5500_0 .net "ors", 1 0, L_0x121ae10; 1 drivers -v0xfb55e0_0 .net "out", 0 0, L_0x121b2f0; 1 drivers -L_0x121ab70 .part L_0x121b740, 0, 1; -L_0x121acd0 .part L_0x121b740, 1, 1; -L_0x121ae10 .concat8 [ 1 1 0 0], L_0x121ab00, L_0x121af00; -L_0x121b010 .part L_0x121b740, 2, 1; -L_0x121b170 .part L_0x121b740, 3, 1; -L_0x121b360 .part L_0x121ae10, 0, 1; -L_0x121b510 .part L_0x121ae10, 1, 1; -S_0xff2b30 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xc13330; +L_0x2cf9370/d .functor OR 1, L_0x2cf93e0, L_0x2cf9540, C4<0>, C4<0>; +L_0x2cf9370 .delay 1 (30000,30000,30000) L_0x2cf9370/d; +L_0x2cf9770/d .functor OR 1, L_0x2cf9880, L_0x2cf99e0, C4<0>, C4<0>; +L_0x2cf9770 .delay 1 (30000,30000,30000) L_0x2cf9770/d; +L_0x2cf9b60/d .functor OR 1, L_0x2cf9bd0, L_0x2cf9d80, C4<0>, C4<0>; +L_0x2cf9b60 .delay 1 (30000,30000,30000) L_0x2cf9b60/d; +v0x2338ea0_0 .net *"_s0", 0 0, L_0x2cf9370; 1 drivers +v0x2338fa0_0 .net *"_s10", 0 0, L_0x2cf9880; 1 drivers +v0x2339080_0 .net *"_s12", 0 0, L_0x2cf99e0; 1 drivers +v0x2339140_0 .net *"_s14", 0 0, L_0x2cf9bd0; 1 drivers +v0x232d710_0 .net *"_s16", 0 0, L_0x2cf9d80; 1 drivers +v0x232d840_0 .net *"_s3", 0 0, L_0x2cf93e0; 1 drivers +v0x232d920_0 .net *"_s5", 0 0, L_0x2cf9540; 1 drivers +v0x232da00_0 .net *"_s6", 0 0, L_0x2cf9770; 1 drivers +v0x232f3f0_0 .net "in", 3 0, L_0x2cf9fb0; 1 drivers +v0x232f4b0_0 .net "ors", 1 0, L_0x2cf9680; 1 drivers +v0x232f590_0 .net "out", 0 0, L_0x2cf9b60; 1 drivers +L_0x2cf93e0 .part L_0x2cf9fb0, 0, 1; +L_0x2cf9540 .part L_0x2cf9fb0, 1, 1; +L_0x2cf9680 .concat8 [ 1 1 0 0], L_0x2cf9370, L_0x2cf9770; +L_0x2cf9880 .part L_0x2cf9fb0, 2, 1; +L_0x2cf99e0 .part L_0x2cf9fb0, 3, 1; +L_0x2cf9bd0 .part L_0x2cf9680, 0, 1; +L_0x2cf9d80 .part L_0x2cf9680, 1, 1; +S_0x233a970 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x278ed50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -1766,80 +1861,80 @@ S_0xff2b30 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xc13330; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1216fb0/d .functor XNOR 1, L_0x121f680, L_0x121f870, C4<0>, C4<0>; -L_0x1216fb0 .delay 1 (20000,20000,20000) L_0x1216fb0/d; -L_0x1217220/d .functor AND 1, L_0x121f680, L_0x1215fb0, C4<1>, C4<1>; -L_0x1217220 .delay 1 (30000,30000,30000) L_0x1217220/d; -L_0x1217290/d .functor AND 1, L_0x1216fb0, L_0x121f9a0, C4<1>, C4<1>; -L_0x1217290 .delay 1 (30000,30000,30000) L_0x1217290/d; -L_0x12173f0/d .functor OR 1, L_0x1217290, L_0x1217220, C4<0>, C4<0>; -L_0x12173f0 .delay 1 (30000,30000,30000) L_0x12173f0/d; -v0xff2d50_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers -v0xff2df0_0 .net "a_", 0 0, L_0x1215ea0; alias, 1 drivers -v0xff2eb0_0 .net "b", 0 0, L_0x121f870; alias, 1 drivers -v0xff2fa0_0 .net "b_", 0 0, L_0x1215fb0; alias, 1 drivers -v0xff3040_0 .net "carryin", 0 0, L_0x121f9a0; alias, 1 drivers -v0xff3180_0 .net "eq", 0 0, L_0x1216fb0; 1 drivers -v0xff3240_0 .net "lt", 0 0, L_0x1217220; 1 drivers -v0xff3300_0 .net "out", 0 0, L_0x12173f0; 1 drivers -v0xff33c0_0 .net "w0", 0 0, L_0x1217290; 1 drivers -S_0xff35d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xc13330; +L_0x2cf4d20/d .functor XNOR 1, L_0x2cfdef0, L_0x2cfe0e0, C4<0>, C4<0>; +L_0x2cf4d20 .delay 1 (20000,20000,20000) L_0x2cf4d20/d; +L_0x2cf4ea0/d .functor AND 1, L_0x2cfdef0, L_0x2cf3b50, C4<1>, C4<1>; +L_0x2cf4ea0 .delay 1 (30000,30000,30000) L_0x2cf4ea0/d; +L_0x2cf5000/d .functor AND 1, L_0x2cf4d20, L_0x2cfe210, C4<1>, C4<1>; +L_0x2cf5000 .delay 1 (30000,30000,30000) L_0x2cf5000/d; +L_0x2cf5110/d .functor OR 1, L_0x2cf5000, L_0x2cf4ea0, C4<0>, C4<0>; +L_0x2cf5110 .delay 1 (30000,30000,30000) L_0x2cf5110/d; +v0x233abe0_0 .net "a", 0 0, L_0x2cfdef0; alias, 1 drivers +v0x2ab7060_0 .net "a_", 0 0, L_0x2cf39f0; alias, 1 drivers +v0x2ab7120_0 .net "b", 0 0, L_0x2cfe0e0; alias, 1 drivers +v0x2ab7210_0 .net "b_", 0 0, L_0x2cf3b50; alias, 1 drivers +v0x2ab72b0_0 .net "carryin", 0 0, L_0x2cfe210; alias, 1 drivers +v0x2ab73f0_0 .net "eq", 0 0, L_0x2cf4d20; 1 drivers +v0x2ab80a0_0 .net "lt", 0 0, L_0x2cf4ea0; 1 drivers +v0x2ab8140_0 .net "out", 0 0, L_0x2cf5110; 1 drivers +v0x2ab81e0_0 .net "w0", 0 0, L_0x2cf5000; 1 drivers +S_0x2ab8310 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x278ed50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1216d90/d .functor OR 1, L_0x12168e0, L_0xff47d0, C4<0>, C4<0>; -L_0x1216d90 .delay 1 (30000,30000,30000) L_0x1216d90/d; -v0xff4360_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers -v0xff44b0_0 .net "b", 0 0, L_0x1215fb0; alias, 1 drivers -v0xff4570_0 .net "c1", 0 0, L_0x12168e0; 1 drivers -v0xff4610_0 .net "c2", 0 0, L_0xff47d0; 1 drivers -v0xff46e0_0 .net "carryin", 0 0, L_0x121f9a0; alias, 1 drivers -v0xff4860_0 .net "carryout", 0 0, L_0x1216d90; 1 drivers -v0xff4900_0 .net "s1", 0 0, L_0x1216820; 1 drivers -v0xff49a0_0 .net "sum", 0 0, L_0x1216a40; 1 drivers -S_0xff3820 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xff35d0; +L_0x2cf4900/d .functor OR 1, L_0x2cf4450, L_0x2ab9490, C4<0>, C4<0>; +L_0x2cf4900 .delay 1 (30000,30000,30000) L_0x2cf4900/d; +v0x2ab9020_0 .net "a", 0 0, L_0x2cfdef0; alias, 1 drivers +v0x2ab9170_0 .net "b", 0 0, L_0x2cf3b50; alias, 1 drivers +v0x2ab9230_0 .net "c1", 0 0, L_0x2cf4450; 1 drivers +v0x2ab92d0_0 .net "c2", 0 0, L_0x2ab9490; 1 drivers +v0x2ab93a0_0 .net "carryin", 0 0, L_0x2cfe210; alias, 1 drivers +v0x2ab9520_0 .net "carryout", 0 0, L_0x2cf4900; 1 drivers +v0x2ab95c0_0 .net "s1", 0 0, L_0x2cf4390; 1 drivers +v0x2ab9660_0 .net "sum", 0 0, L_0x2cf45b0; 1 drivers +S_0x2ab8510 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2ab8310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1216820/d .functor XOR 1, L_0x121f680, L_0x1215fb0, C4<0>, C4<0>; -L_0x1216820 .delay 1 (30000,30000,30000) L_0x1216820/d; -L_0x12168e0/d .functor AND 1, L_0x121f680, L_0x1215fb0, C4<1>, C4<1>; -L_0x12168e0 .delay 1 (30000,30000,30000) L_0x12168e0/d; -v0xff3a80_0 .net "a", 0 0, L_0x121f680; alias, 1 drivers -v0xff3b40_0 .net "b", 0 0, L_0x1215fb0; alias, 1 drivers -v0xff3c00_0 .net "carryout", 0 0, L_0x12168e0; alias, 1 drivers -v0xff3ca0_0 .net "sum", 0 0, L_0x1216820; alias, 1 drivers -S_0xff3da0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xff35d0; +L_0x2cf4390/d .functor XOR 1, L_0x2cfdef0, L_0x2cf3b50, C4<0>, C4<0>; +L_0x2cf4390 .delay 1 (30000,30000,30000) L_0x2cf4390/d; +L_0x2cf4450/d .functor AND 1, L_0x2cfdef0, L_0x2cf3b50, C4<1>, C4<1>; +L_0x2cf4450 .delay 1 (30000,30000,30000) L_0x2cf4450/d; +v0x2ab8770_0 .net "a", 0 0, L_0x2cfdef0; alias, 1 drivers +v0x2ab8830_0 .net "b", 0 0, L_0x2cf3b50; alias, 1 drivers +v0x2ab88f0_0 .net "carryout", 0 0, L_0x2cf4450; alias, 1 drivers +v0x2ab8990_0 .net "sum", 0 0, L_0x2cf4390; alias, 1 drivers +S_0x2ab8a90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2ab8310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1216a40/d .functor XOR 1, L_0x1216820, L_0x121f9a0, C4<0>, C4<0>; -L_0x1216a40 .delay 1 (30000,30000,30000) L_0x1216a40/d; -L_0xff47d0/d .functor AND 1, L_0x1216820, L_0x121f9a0, C4<1>, C4<1>; -L_0xff47d0 .delay 1 (30000,30000,30000) L_0xff47d0/d; -v0xff4000_0 .net "a", 0 0, L_0x1216820; alias, 1 drivers -v0xff40a0_0 .net "b", 0 0, L_0x121f9a0; alias, 1 drivers -v0xff4140_0 .net "carryout", 0 0, L_0xff47d0; alias, 1 drivers -v0xff4210_0 .net "sum", 0 0, L_0x1216a40; alias, 1 drivers -S_0xff5dc0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0xc23180; - .timescale -9 -12; -L_0x2b0ab3d05258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d052a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x121f720/d .functor OR 1, L_0x2b0ab3d05258, L_0x2b0ab3d052a0, C4<0>, C4<0>; -L_0x121f720 .delay 1 (30000,30000,30000) L_0x121f720/d; -v0xff5fb0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05258; 1 drivers -v0xff6090_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d052a0; 1 drivers -S_0xff6170 .scope generate, "alu_slices[3]" "alu_slices[3]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0xff6380 .param/l "i" 0 3 41, +C4<011>; -S_0xff6440 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xff6170; +L_0x2cf45b0/d .functor XOR 1, L_0x2cf4390, L_0x2cfe210, C4<0>, C4<0>; +L_0x2cf45b0 .delay 1 (30000,30000,30000) L_0x2cf45b0/d; +L_0x2ab9490/d .functor AND 1, L_0x2cf4390, L_0x2cfe210, C4<1>, C4<1>; +L_0x2ab9490 .delay 1 (30000,30000,30000) L_0x2ab9490/d; +v0x2ab8cf0_0 .net "a", 0 0, L_0x2cf4390; alias, 1 drivers +v0x2ab8d90_0 .net "b", 0 0, L_0x2cfe210; alias, 1 drivers +v0x2ab8e30_0 .net "carryout", 0 0, L_0x2ab9490; alias, 1 drivers +v0x2ab8ed0_0 .net "sum", 0 0, L_0x2cf45b0; alias, 1 drivers +S_0x2abb6f0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x27a25f0; + .timescale -9 -12; +L_0x2ac6110b6ac8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6b10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ceaec0/d .functor OR 1, L_0x2ac6110b6ac8, L_0x2ac6110b6b10, C4<0>, C4<0>; +L_0x2ceaec0 .delay 1 (30000,30000,30000) L_0x2ceaec0/d; +v0x2abb8e0_0 .net/2u *"_s0", 0 0, L_0x2ac6110b6ac8; 1 drivers +v0x2abb9c0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b6b10; 1 drivers +S_0x2abbaa0 .scope generate, "alu_slices[3]" "alu_slices[3]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2abbcb0 .param/l "i" 0 3 39, +C4<011>; +S_0x2abbd70 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2abbaa0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -1848,445 +1943,476 @@ S_0xff6440 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0xff6170; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x121fba0/d .functor NOT 1, L_0x1229330, C4<0>, C4<0>, C4<0>; -L_0x121fba0 .delay 1 (10000,10000,10000) L_0x121fba0/d; -L_0x121fcb0/d .functor NOT 1, L_0x1229490, C4<0>, C4<0>, C4<0>; -L_0x121fcb0 .delay 1 (10000,10000,10000) L_0x121fcb0/d; -L_0x1220ba0/d .functor XOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; -L_0x1220ba0 .delay 1 (30000,30000,30000) L_0x1220ba0/d; -L_0x2b0ab3d052e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1221250/d .functor OR 1, L_0x2b0ab3d052e8, L_0x2b0ab3d05330, C4<0>, C4<0>; -L_0x1221250 .delay 1 (30000,30000,30000) L_0x1221250/d; -L_0x1221450/d .functor AND 1, L_0x1229330, L_0x1229490, C4<1>, C4<1>; -L_0x1221450 .delay 1 (30000,30000,30000) L_0x1221450/d; -L_0x1221510/d .functor NAND 1, L_0x1229330, L_0x1229490, C4<1>, C4<1>; -L_0x1221510 .delay 1 (20000,20000,20000) L_0x1221510/d; -L_0x1221670/d .functor XOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; -L_0x1221670 .delay 1 (20000,20000,20000) L_0x1221670/d; -L_0x1221b20/d .functor OR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; -L_0x1221b20 .delay 1 (30000,30000,30000) L_0x1221b20/d; -L_0x1229230/d .functor NOT 1, L_0x1225490, C4<0>, C4<0>, C4<0>; -L_0x1229230 .delay 1 (10000,10000,10000) L_0x1229230/d; -v0x1004c10_0 .net "A", 0 0, L_0x1229330; 1 drivers -v0x1004cd0_0 .net "A_", 0 0, L_0x121fba0; 1 drivers -v0x1004d90_0 .net "B", 0 0, L_0x1229490; 1 drivers -v0x1004e60_0 .net "B_", 0 0, L_0x121fcb0; 1 drivers -v0x1004f00_0 .net *"_s12", 0 0, L_0x1221250; 1 drivers -v0x1004ff0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d052e8; 1 drivers -v0x10050b0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05330; 1 drivers -v0x1005190_0 .net *"_s18", 0 0, L_0x1221450; 1 drivers -v0x1005270_0 .net *"_s20", 0 0, L_0x1221510; 1 drivers -v0x10053e0_0 .net *"_s22", 0 0, L_0x1221670; 1 drivers -v0x10054c0_0 .net *"_s24", 0 0, L_0x1221b20; 1 drivers -o0x2b0ab3cac2b8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10055a0_0 name=_s30 -o0x2b0ab3cac2e8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1005680_0 name=_s32 -v0x1005760_0 .net *"_s8", 0 0, L_0x1220ba0; 1 drivers -v0x1005840_0 .net "carryin", 0 0, L_0x1229530; 1 drivers -v0x10058e0_0 .net "carryout", 0 0, L_0x1228ed0; 1 drivers -v0x1005980_0 .net "carryouts", 7 0, L_0x1353410; 1 drivers -v0x1005b30_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1005bd0_0 .net "result", 0 0, L_0x1225490; 1 drivers -v0x1005cc0_0 .net "results", 7 0, L_0x12218f0; 1 drivers -v0x1005dd0_0 .net "zero", 0 0, L_0x1229230; 1 drivers -LS_0x12218f0_0_0 .concat8 [ 1 1 1 1], L_0x1220070, L_0x12206f0, L_0x1220ba0, L_0x1221250; -LS_0x12218f0_0_4 .concat8 [ 1 1 1 1], L_0x1221450, L_0x1221510, L_0x1221670, L_0x1221b20; -L_0x12218f0 .concat8 [ 4 4 0 0], LS_0x12218f0_0_0, LS_0x12218f0_0_4; -LS_0x1353410_0_0 .concat [ 1 1 1 1], L_0x1220370, L_0x1220a40, o0x2b0ab3cac2b8, L_0x12210a0; -LS_0x1353410_0_4 .concat [ 4 0 0 0], o0x2b0ab3cac2e8; -L_0x1353410 .concat [ 4 4 0 0], LS_0x1353410_0_0, LS_0x1353410_0_4; -S_0xff66c0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0xff6440; +L_0x2cfe350/d .functor NOT 1, L_0x2d087e0, C4<0>, C4<0>, C4<0>; +L_0x2cfe350 .delay 1 (10000,10000,10000) L_0x2cfe350/d; +L_0x2cfe460/d .functor NOT 1, L_0x2d08940, C4<0>, C4<0>, C4<0>; +L_0x2cfe460 .delay 1 (10000,10000,10000) L_0x2cfe460/d; +L_0x2cff4b0/d .functor XOR 1, L_0x2d087e0, L_0x2d08940, C4<0>, C4<0>; +L_0x2cff4b0 .delay 1 (30000,30000,30000) L_0x2cff4b0/d; +L_0x2ac6110b6b58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6ba0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cff570/d .functor OR 1, L_0x2ac6110b6b58, L_0x2ac6110b6ba0, C4<0>, C4<0>; +L_0x2cff570 .delay 1 (30000,30000,30000) L_0x2cff570/d; +L_0x2ac6110b6be8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6c30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cffd10/d .functor OR 1, L_0x2ac6110b6be8, L_0x2ac6110b6c30, C4<0>, C4<0>; +L_0x2cffd10 .delay 1 (30000,30000,30000) L_0x2cffd10/d; +L_0x2cfff10/d .functor AND 1, L_0x2d087e0, L_0x2d08940, C4<1>, C4<1>; +L_0x2cfff10 .delay 1 (30000,30000,30000) L_0x2cfff10/d; +L_0x2ac6110b6c78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6cc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cfffd0/d .functor OR 1, L_0x2ac6110b6c78, L_0x2ac6110b6cc0, C4<0>, C4<0>; +L_0x2cfffd0 .delay 1 (30000,30000,30000) L_0x2cfffd0/d; +L_0x2d001d0/d .functor NAND 1, L_0x2d087e0, L_0x2d08940, C4<1>, C4<1>; +L_0x2d001d0 .delay 1 (20000,20000,20000) L_0x2d001d0/d; +L_0x2ac6110b6d08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6d50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d002e0/d .functor OR 1, L_0x2ac6110b6d08, L_0x2ac6110b6d50, C4<0>, C4<0>; +L_0x2d002e0 .delay 1 (30000,30000,30000) L_0x2d002e0/d; +L_0x2d00490/d .functor NOR 1, L_0x2d087e0, L_0x2d08940, C4<0>, C4<0>; +L_0x2d00490 .delay 1 (20000,20000,20000) L_0x2d00490/d; +L_0x2ac6110b6d98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6de0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2cfe910/d .functor OR 1, L_0x2ac6110b6d98, L_0x2ac6110b6de0, C4<0>, C4<0>; +L_0x2cfe910 .delay 1 (30000,30000,30000) L_0x2cfe910/d; +L_0x2d00af0/d .functor OR 1, L_0x2d087e0, L_0x2d08940, C4<0>, C4<0>; +L_0x2d00af0 .delay 1 (30000,30000,30000) L_0x2d00af0/d; +L_0x2ac6110b6e28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6e70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d00fe0/d .functor OR 1, L_0x2ac6110b6e28, L_0x2ac6110b6e70, C4<0>, C4<0>; +L_0x2d00fe0 .delay 1 (30000,30000,30000) L_0x2d00fe0/d; +L_0x2d086e0/d .functor NOT 1, L_0x2d04940, C4<0>, C4<0>, C4<0>; +L_0x2d086e0 .delay 1 (10000,10000,10000) L_0x2d086e0/d; +v0x2aca5a0_0 .net "A", 0 0, L_0x2d087e0; 1 drivers +v0x2aca660_0 .net "A_", 0 0, L_0x2cfe350; 1 drivers +v0x2aca720_0 .net "B", 0 0, L_0x2d08940; 1 drivers +v0x2aca7f0_0 .net "B_", 0 0, L_0x2cfe460; 1 drivers +v0x2aca890_0 .net *"_s11", 0 0, L_0x2cff570; 1 drivers +v0x2aca980_0 .net/2s *"_s13", 0 0, L_0x2ac6110b6b58; 1 drivers +v0x2acaa40_0 .net/2s *"_s15", 0 0, L_0x2ac6110b6ba0; 1 drivers +v0x2acab20_0 .net *"_s19", 0 0, L_0x2cffd10; 1 drivers +v0x2acac00_0 .net/2s *"_s21", 0 0, L_0x2ac6110b6be8; 1 drivers +v0x2acad70_0 .net/2s *"_s23", 0 0, L_0x2ac6110b6c30; 1 drivers +v0x2acae50_0 .net *"_s25", 0 0, L_0x2cfff10; 1 drivers +v0x2acaf30_0 .net *"_s28", 0 0, L_0x2cfffd0; 1 drivers +v0x2acb010_0 .net/2s *"_s30", 0 0, L_0x2ac6110b6c78; 1 drivers +v0x2acb0f0_0 .net/2s *"_s32", 0 0, L_0x2ac6110b6cc0; 1 drivers +v0x2acb1d0_0 .net *"_s34", 0 0, L_0x2d001d0; 1 drivers +v0x2acb2b0_0 .net *"_s37", 0 0, L_0x2d002e0; 1 drivers +v0x2acb390_0 .net/2s *"_s39", 0 0, L_0x2ac6110b6d08; 1 drivers +v0x2acb540_0 .net/2s *"_s41", 0 0, L_0x2ac6110b6d50; 1 drivers +v0x2acb5e0_0 .net *"_s43", 0 0, L_0x2d00490; 1 drivers +v0x2acb6c0_0 .net *"_s46", 0 0, L_0x2cfe910; 1 drivers +v0x2acb7a0_0 .net/2s *"_s48", 0 0, L_0x2ac6110b6d98; 1 drivers +v0x2acb880_0 .net/2s *"_s50", 0 0, L_0x2ac6110b6de0; 1 drivers +v0x2acb960_0 .net *"_s52", 0 0, L_0x2d00af0; 1 drivers +v0x2acba40_0 .net *"_s56", 0 0, L_0x2d00fe0; 1 drivers +v0x2acbb20_0 .net/2s *"_s59", 0 0, L_0x2ac6110b6e28; 1 drivers +v0x2acbc00_0 .net/2s *"_s61", 0 0, L_0x2ac6110b6e70; 1 drivers +v0x2acbce0_0 .net *"_s8", 0 0, L_0x2cff4b0; 1 drivers +v0x2acbdc0_0 .net "carryin", 0 0, L_0x2d089e0; 1 drivers +v0x2acbe60_0 .net "carryout", 0 0, L_0x2d08380; 1 drivers +v0x2acbf00_0 .net "carryouts", 7 0, L_0x2d00c70; 1 drivers +v0x2acc010_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2acc0d0_0 .net "result", 0 0, L_0x2d04940; 1 drivers +v0x2acc1c0_0 .net "results", 7 0, L_0x2d008c0; 1 drivers +v0x2acb4a0_0 .net "zero", 0 0, L_0x2d086e0; 1 drivers +LS_0x2d008c0_0_0 .concat8 [ 1 1 1 1], L_0x2cfe980, L_0x2cfefb0, L_0x2cff4b0, L_0x2cffd10; +LS_0x2d008c0_0_4 .concat8 [ 1 1 1 1], L_0x2cfff10, L_0x2d001d0, L_0x2d00490, L_0x2d00af0; +L_0x2d008c0 .concat8 [ 4 4 0 0], LS_0x2d008c0_0_0, LS_0x2d008c0_0_4; +LS_0x2d00c70_0_0 .concat8 [ 1 1 1 1], L_0x2cfec30, L_0x2cff350, L_0x2cff570, L_0x2cffb60; +LS_0x2d00c70_0_4 .concat8 [ 1 1 1 1], L_0x2cfffd0, L_0x2d002e0, L_0x2cfe910, L_0x2d00fe0; +L_0x2d00c70 .concat8 [ 4 4 0 0], LS_0x2d00c70_0_0, LS_0x2d00c70_0_4; +S_0x2abbff0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2abbd70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1220370/d .functor OR 1, L_0x121fea0, L_0x1220260, C4<0>, C4<0>; -L_0x1220370 .delay 1 (30000,30000,30000) L_0x1220370/d; -v0xff74f0_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers -v0xff75b0_0 .net "b", 0 0, L_0x1229490; alias, 1 drivers -v0xff7680_0 .net "c1", 0 0, L_0x121fea0; 1 drivers -v0xff7780_0 .net "c2", 0 0, L_0x1220260; 1 drivers -v0xff7850_0 .net "carryin", 0 0, L_0x1229530; alias, 1 drivers -v0xff7940_0 .net "carryout", 0 0, L_0x1220370; 1 drivers -v0xff79e0_0 .net "s1", 0 0, L_0x1219760; 1 drivers -v0xff7ad0_0 .net "sum", 0 0, L_0x1220070; 1 drivers -S_0xff6930 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0xff66c0; +L_0x2cfec30/d .functor OR 1, L_0x2cfe710, L_0x2cfead0, C4<0>, C4<0>; +L_0x2cfec30 .delay 1 (30000,30000,30000) L_0x2cfec30/d; +v0x2abce20_0 .net "a", 0 0, L_0x2d087e0; alias, 1 drivers +v0x2abcee0_0 .net "b", 0 0, L_0x2d08940; alias, 1 drivers +v0x2abcfb0_0 .net "c1", 0 0, L_0x2cfe710; 1 drivers +v0x2abd0b0_0 .net "c2", 0 0, L_0x2cfead0; 1 drivers +v0x2abd180_0 .net "carryin", 0 0, L_0x2d089e0; alias, 1 drivers +v0x2abd270_0 .net "carryout", 0 0, L_0x2cfec30; 1 drivers +v0x2abd310_0 .net "s1", 0 0, L_0x2cfe650; 1 drivers +v0x2abd400_0 .net "sum", 0 0, L_0x2cfe980; 1 drivers +S_0x2abc260 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2abbff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1219760/d .functor XOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; -L_0x1219760 .delay 1 (30000,30000,30000) L_0x1219760/d; -L_0x121fea0/d .functor AND 1, L_0x1229330, L_0x1229490, C4<1>, C4<1>; -L_0x121fea0 .delay 1 (30000,30000,30000) L_0x121fea0/d; -v0xff6b90_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers -v0xff6c70_0 .net "b", 0 0, L_0x1229490; alias, 1 drivers -v0xff6d30_0 .net "carryout", 0 0, L_0x121fea0; alias, 1 drivers -v0xff6dd0_0 .net "sum", 0 0, L_0x1219760; alias, 1 drivers -S_0xff6f10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0xff66c0; +L_0x2cfe650/d .functor XOR 1, L_0x2d087e0, L_0x2d08940, C4<0>, C4<0>; +L_0x2cfe650 .delay 1 (30000,30000,30000) L_0x2cfe650/d; +L_0x2cfe710/d .functor AND 1, L_0x2d087e0, L_0x2d08940, C4<1>, C4<1>; +L_0x2cfe710 .delay 1 (30000,30000,30000) L_0x2cfe710/d; +v0x2abc4c0_0 .net "a", 0 0, L_0x2d087e0; alias, 1 drivers +v0x2abc5a0_0 .net "b", 0 0, L_0x2d08940; alias, 1 drivers +v0x2abc660_0 .net "carryout", 0 0, L_0x2cfe710; alias, 1 drivers +v0x2abc700_0 .net "sum", 0 0, L_0x2cfe650; alias, 1 drivers +S_0x2abc840 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2abbff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1220070/d .functor XOR 1, L_0x1219760, L_0x1229530, C4<0>, C4<0>; -L_0x1220070 .delay 1 (30000,30000,30000) L_0x1220070/d; -L_0x1220260/d .functor AND 1, L_0x1219760, L_0x1229530, C4<1>, C4<1>; -L_0x1220260 .delay 1 (30000,30000,30000) L_0x1220260/d; -v0xff7170_0 .net "a", 0 0, L_0x1219760; alias, 1 drivers -v0xff7210_0 .net "b", 0 0, L_0x1229530; alias, 1 drivers -v0xff72b0_0 .net "carryout", 0 0, L_0x1220260; alias, 1 drivers -v0xff7380_0 .net "sum", 0 0, L_0x1220070; alias, 1 drivers -S_0xff7ba0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0xff6440; +L_0x2cfe980/d .functor XOR 1, L_0x2cfe650, L_0x2d089e0, C4<0>, C4<0>; +L_0x2cfe980 .delay 1 (30000,30000,30000) L_0x2cfe980/d; +L_0x2cfead0/d .functor AND 1, L_0x2cfe650, L_0x2d089e0, C4<1>, C4<1>; +L_0x2cfead0 .delay 1 (30000,30000,30000) L_0x2cfead0/d; +v0x2abcaa0_0 .net "a", 0 0, L_0x2cfe650; alias, 1 drivers +v0x2abcb40_0 .net "b", 0 0, L_0x2d089e0; alias, 1 drivers +v0x2abcbe0_0 .net "carryout", 0 0, L_0x2cfead0; alias, 1 drivers +v0x2abccb0_0 .net "sum", 0 0, L_0x2cfe980; alias, 1 drivers +S_0x2abd4d0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2abbd70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0xffcf90_0 .net "ands", 7 0, L_0x1226ed0; 1 drivers -v0xffd0a0_0 .net "in", 7 0, L_0x1353410; alias, 1 drivers -v0xffd160_0 .net "out", 0 0, L_0x1228ed0; alias, 1 drivers -v0xffd230_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xff7dc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xff7ba0; +v0x2ac28c0_0 .net "ands", 7 0, L_0x2d06380; 1 drivers +v0x2ac29d0_0 .net "in", 7 0, L_0x2d00c70; alias, 1 drivers +v0x2ac2a90_0 .net "out", 0 0, L_0x2d08380; alias, 1 drivers +v0x2ac2b60_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2abd6f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2abd4d0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xffa4f0_0 .net "A", 7 0, L_0x1353410; alias, 1 drivers -v0xffa5f0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xffa6b0_0 .net *"_s0", 0 0, L_0x12257f0; 1 drivers -v0xffa770_0 .net *"_s12", 0 0, L_0x1226160; 1 drivers -v0xffa850_0 .net *"_s16", 0 0, L_0x12264c0; 1 drivers -v0xffa980_0 .net *"_s20", 0 0, L_0x12267d0; 1 drivers -v0xffaa60_0 .net *"_s24", 0 0, L_0x1226bc0; 1 drivers -v0xffab40_0 .net *"_s28", 0 0, L_0x1226b50; 1 drivers -v0xffac20_0 .net *"_s4", 0 0, L_0x1225b00; 1 drivers -v0xffad90_0 .net *"_s8", 0 0, L_0x1225e50; 1 drivers -v0xffae70_0 .net "out", 7 0, L_0x1226ed0; alias, 1 drivers -L_0x12258b0 .part L_0x1353410, 0, 1; -L_0x1225a10 .part v0x12010b0_0, 0, 1; -L_0x1225bc0 .part L_0x1353410, 1, 1; -L_0x1225db0 .part v0x12010b0_0, 1, 1; -L_0x1225f10 .part L_0x1353410, 2, 1; -L_0x1226070 .part v0x12010b0_0, 2, 1; -L_0x1226220 .part L_0x1353410, 3, 1; -L_0x1226380 .part v0x12010b0_0, 3, 1; -L_0x1226580 .part L_0x1353410, 4, 1; -L_0x12266e0 .part v0x12010b0_0, 4, 1; -L_0x1226840 .part L_0x1353410, 5, 1; -L_0x1226ab0 .part v0x12010b0_0, 5, 1; -L_0x1226c80 .part L_0x1353410, 6, 1; -L_0x1226de0 .part v0x12010b0_0, 6, 1; -LS_0x1226ed0_0_0 .concat8 [ 1 1 1 1], L_0x12257f0, L_0x1225b00, L_0x1225e50, L_0x1226160; -LS_0x1226ed0_0_4 .concat8 [ 1 1 1 1], L_0x12264c0, L_0x12267d0, L_0x1226bc0, L_0x1226b50; -L_0x1226ed0 .concat8 [ 4 4 0 0], LS_0x1226ed0_0_0, LS_0x1226ed0_0_4; -L_0x1227290 .part L_0x1353410, 7, 1; -L_0x1227480 .part v0x12010b0_0, 7, 1; -S_0xff8020 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff8230 .param/l "i" 0 4 54, +C4<00>; -L_0x12257f0/d .functor AND 1, L_0x12258b0, L_0x1225a10, C4<1>, C4<1>; -L_0x12257f0 .delay 1 (30000,30000,30000) L_0x12257f0/d; -v0xff8310_0 .net *"_s0", 0 0, L_0x12258b0; 1 drivers -v0xff83f0_0 .net *"_s1", 0 0, L_0x1225a10; 1 drivers -S_0xff84d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff86e0 .param/l "i" 0 4 54, +C4<01>; -L_0x1225b00/d .functor AND 1, L_0x1225bc0, L_0x1225db0, C4<1>, C4<1>; -L_0x1225b00 .delay 1 (30000,30000,30000) L_0x1225b00/d; -v0xff87a0_0 .net *"_s0", 0 0, L_0x1225bc0; 1 drivers -v0xff8880_0 .net *"_s1", 0 0, L_0x1225db0; 1 drivers -S_0xff8960 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff8b70 .param/l "i" 0 4 54, +C4<010>; -L_0x1225e50/d .functor AND 1, L_0x1225f10, L_0x1226070, C4<1>, C4<1>; -L_0x1225e50 .delay 1 (30000,30000,30000) L_0x1225e50/d; -v0xff8c10_0 .net *"_s0", 0 0, L_0x1225f10; 1 drivers -v0xff8cf0_0 .net *"_s1", 0 0, L_0x1226070; 1 drivers -S_0xff8dd0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff8fe0 .param/l "i" 0 4 54, +C4<011>; -L_0x1226160/d .functor AND 1, L_0x1226220, L_0x1226380, C4<1>, C4<1>; -L_0x1226160 .delay 1 (30000,30000,30000) L_0x1226160/d; -v0xff90a0_0 .net *"_s0", 0 0, L_0x1226220; 1 drivers -v0xff9180_0 .net *"_s1", 0 0, L_0x1226380; 1 drivers -S_0xff9260 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff94c0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12264c0/d .functor AND 1, L_0x1226580, L_0x12266e0, C4<1>, C4<1>; -L_0x12264c0 .delay 1 (30000,30000,30000) L_0x12264c0/d; -v0xff9580_0 .net *"_s0", 0 0, L_0x1226580; 1 drivers -v0xff9660_0 .net *"_s1", 0 0, L_0x12266e0; 1 drivers -S_0xff9740 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff9950 .param/l "i" 0 4 54, +C4<0101>; -L_0x12267d0/d .functor AND 1, L_0x1226840, L_0x1226ab0, C4<1>, C4<1>; -L_0x12267d0 .delay 1 (30000,30000,30000) L_0x12267d0/d; -v0xff9a10_0 .net *"_s0", 0 0, L_0x1226840; 1 drivers -v0xff9af0_0 .net *"_s1", 0 0, L_0x1226ab0; 1 drivers -S_0xff9bd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xff9de0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1226bc0/d .functor AND 1, L_0x1226c80, L_0x1226de0, C4<1>, C4<1>; -L_0x1226bc0 .delay 1 (30000,30000,30000) L_0x1226bc0/d; -v0xff9ea0_0 .net *"_s0", 0 0, L_0x1226c80; 1 drivers -v0xff9f80_0 .net *"_s1", 0 0, L_0x1226de0; 1 drivers -S_0xffa060 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xff7dc0; - .timescale -9 -12; -P_0xffa270 .param/l "i" 0 4 54, +C4<0111>; -L_0x1226b50/d .functor AND 1, L_0x1227290, L_0x1227480, C4<1>, C4<1>; -L_0x1226b50 .delay 1 (30000,30000,30000) L_0x1226b50/d; -v0xffa330_0 .net *"_s0", 0 0, L_0x1227290; 1 drivers -v0xffa410_0 .net *"_s1", 0 0, L_0x1227480; 1 drivers -S_0xffafd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xff7ba0; +v0x2abfe20_0 .net "A", 7 0, L_0x2d00c70; alias, 1 drivers +v0x2abff20_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2abffe0_0 .net *"_s0", 0 0, L_0x2d04ca0; 1 drivers +v0x2ac00a0_0 .net *"_s12", 0 0, L_0x2d05610; 1 drivers +v0x2ac0180_0 .net *"_s16", 0 0, L_0x2d05970; 1 drivers +v0x2ac02b0_0 .net *"_s20", 0 0, L_0x2d05d40; 1 drivers +v0x2ac0390_0 .net *"_s24", 0 0, L_0x2d06070; 1 drivers +v0x2ac0470_0 .net *"_s28", 0 0, L_0x2d06000; 1 drivers +v0x2ac0550_0 .net *"_s4", 0 0, L_0x2d04ff0; 1 drivers +v0x2ac06c0_0 .net *"_s8", 0 0, L_0x2d05300; 1 drivers +v0x2ac07a0_0 .net "out", 7 0, L_0x2d06380; alias, 1 drivers +L_0x2d04d60 .part L_0x2d00c70, 0, 1; +L_0x2d04f50 .part v0x2cdd2e0_0, 0, 1; +L_0x2d050b0 .part L_0x2d00c70, 1, 1; +L_0x2d05210 .part v0x2cdd2e0_0, 1, 1; +L_0x2d053c0 .part L_0x2d00c70, 2, 1; +L_0x2d05520 .part v0x2cdd2e0_0, 2, 1; +L_0x2d056d0 .part L_0x2d00c70, 3, 1; +L_0x2d05830 .part v0x2cdd2e0_0, 3, 1; +L_0x2d05a30 .part L_0x2d00c70, 4, 1; +L_0x2d05ca0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d05db0 .part L_0x2d00c70, 5, 1; +L_0x2d05f10 .part v0x2cdd2e0_0, 5, 1; +L_0x2d06130 .part L_0x2d00c70, 6, 1; +L_0x2d06290 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d06380_0_0 .concat8 [ 1 1 1 1], L_0x2d04ca0, L_0x2d04ff0, L_0x2d05300, L_0x2d05610; +LS_0x2d06380_0_4 .concat8 [ 1 1 1 1], L_0x2d05970, L_0x2d05d40, L_0x2d06070, L_0x2d06000; +L_0x2d06380 .concat8 [ 4 4 0 0], LS_0x2d06380_0_0, LS_0x2d06380_0_4; +L_0x2d06740 .part L_0x2d00c70, 7, 1; +L_0x2d06930 .part v0x2cdd2e0_0, 7, 1; +S_0x2abd950 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abdb60 .param/l "i" 0 4 54, +C4<00>; +L_0x2d04ca0/d .functor AND 1, L_0x2d04d60, L_0x2d04f50, C4<1>, C4<1>; +L_0x2d04ca0 .delay 1 (30000,30000,30000) L_0x2d04ca0/d; +v0x2abdc40_0 .net *"_s0", 0 0, L_0x2d04d60; 1 drivers +v0x2abdd20_0 .net *"_s1", 0 0, L_0x2d04f50; 1 drivers +S_0x2abde00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abe010 .param/l "i" 0 4 54, +C4<01>; +L_0x2d04ff0/d .functor AND 1, L_0x2d050b0, L_0x2d05210, C4<1>, C4<1>; +L_0x2d04ff0 .delay 1 (30000,30000,30000) L_0x2d04ff0/d; +v0x2abe0d0_0 .net *"_s0", 0 0, L_0x2d050b0; 1 drivers +v0x2abe1b0_0 .net *"_s1", 0 0, L_0x2d05210; 1 drivers +S_0x2abe290 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abe4a0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d05300/d .functor AND 1, L_0x2d053c0, L_0x2d05520, C4<1>, C4<1>; +L_0x2d05300 .delay 1 (30000,30000,30000) L_0x2d05300/d; +v0x2abe540_0 .net *"_s0", 0 0, L_0x2d053c0; 1 drivers +v0x2abe620_0 .net *"_s1", 0 0, L_0x2d05520; 1 drivers +S_0x2abe700 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abe910 .param/l "i" 0 4 54, +C4<011>; +L_0x2d05610/d .functor AND 1, L_0x2d056d0, L_0x2d05830, C4<1>, C4<1>; +L_0x2d05610 .delay 1 (30000,30000,30000) L_0x2d05610/d; +v0x2abe9d0_0 .net *"_s0", 0 0, L_0x2d056d0; 1 drivers +v0x2abeab0_0 .net *"_s1", 0 0, L_0x2d05830; 1 drivers +S_0x2abeb90 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abedf0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d05970/d .functor AND 1, L_0x2d05a30, L_0x2d05ca0, C4<1>, C4<1>; +L_0x2d05970 .delay 1 (30000,30000,30000) L_0x2d05970/d; +v0x2abeeb0_0 .net *"_s0", 0 0, L_0x2d05a30; 1 drivers +v0x2abef90_0 .net *"_s1", 0 0, L_0x2d05ca0; 1 drivers +S_0x2abf070 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abf280 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d05d40/d .functor AND 1, L_0x2d05db0, L_0x2d05f10, C4<1>, C4<1>; +L_0x2d05d40 .delay 1 (30000,30000,30000) L_0x2d05d40/d; +v0x2abf340_0 .net *"_s0", 0 0, L_0x2d05db0; 1 drivers +v0x2abf420_0 .net *"_s1", 0 0, L_0x2d05f10; 1 drivers +S_0x2abf500 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abf710 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d06070/d .functor AND 1, L_0x2d06130, L_0x2d06290, C4<1>, C4<1>; +L_0x2d06070 .delay 1 (30000,30000,30000) L_0x2d06070/d; +v0x2abf7d0_0 .net *"_s0", 0 0, L_0x2d06130; 1 drivers +v0x2abf8b0_0 .net *"_s1", 0 0, L_0x2d06290; 1 drivers +S_0x2abf990 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2abd6f0; + .timescale -9 -12; +P_0x2abfba0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d06000/d .functor AND 1, L_0x2d06740, L_0x2d06930, C4<1>, C4<1>; +L_0x2d06000 .delay 1 (30000,30000,30000) L_0x2d06000/d; +v0x2abfc60_0 .net *"_s0", 0 0, L_0x2d06740; 1 drivers +v0x2abfd40_0 .net *"_s1", 0 0, L_0x2d06930; 1 drivers +S_0x2ac0900 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2abd4d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1228ed0/d .functor OR 1, L_0x1228f90, L_0x1229140, C4<0>, C4<0>; -L_0x1228ed0 .delay 1 (30000,30000,30000) L_0x1228ed0/d; -v0xffcb20_0 .net *"_s10", 0 0, L_0x1228f90; 1 drivers -v0xffcc00_0 .net *"_s12", 0 0, L_0x1229140; 1 drivers -v0xffcce0_0 .net "in", 7 0, L_0x1226ed0; alias, 1 drivers -v0xffcdb0_0 .net "ors", 1 0, L_0x1228cf0; 1 drivers -v0xffce70_0 .net "out", 0 0, L_0x1228ed0; alias, 1 drivers -L_0x12280c0 .part L_0x1226ed0, 0, 4; -L_0x1228cf0 .concat8 [ 1 1 0 0], L_0x1227db0, L_0x12289e0; -L_0x1228e30 .part L_0x1226ed0, 4, 4; -L_0x1228f90 .part L_0x1228cf0, 0, 1; -L_0x1229140 .part L_0x1228cf0, 1, 1; -S_0xffb190 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0xffafd0; +L_0x2d08380/d .functor OR 1, L_0x2d08440, L_0x2d085f0, C4<0>, C4<0>; +L_0x2d08380 .delay 1 (30000,30000,30000) L_0x2d08380/d; +v0x2ac2450_0 .net *"_s10", 0 0, L_0x2d08440; 1 drivers +v0x2ac2530_0 .net *"_s12", 0 0, L_0x2d085f0; 1 drivers +v0x2ac2610_0 .net "in", 7 0, L_0x2d06380; alias, 1 drivers +v0x2ac26e0_0 .net "ors", 1 0, L_0x2d081a0; 1 drivers +v0x2ac27a0_0 .net "out", 0 0, L_0x2d08380; alias, 1 drivers +L_0x2d07570 .part L_0x2d06380, 0, 4; +L_0x2d081a0 .concat8 [ 1 1 0 0], L_0x2d07260, L_0x2d07e90; +L_0x2d082e0 .part L_0x2d06380, 4, 4; +L_0x2d08440 .part L_0x2d081a0, 0, 1; +L_0x2d085f0 .part L_0x2d081a0, 1, 1; +S_0x2ac0ac0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ac0900; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1227570/d .functor OR 1, L_0x1227630, L_0x1227790, C4<0>, C4<0>; -L_0x1227570 .delay 1 (30000,30000,30000) L_0x1227570/d; -L_0x12279c0/d .functor OR 1, L_0x1227ad0, L_0x1227c30, C4<0>, C4<0>; -L_0x12279c0 .delay 1 (30000,30000,30000) L_0x12279c0/d; -L_0x1227db0/d .functor OR 1, L_0x1227e20, L_0x1227fd0, C4<0>, C4<0>; -L_0x1227db0 .delay 1 (30000,30000,30000) L_0x1227db0/d; -v0xffb3e0_0 .net *"_s0", 0 0, L_0x1227570; 1 drivers -v0xffb4e0_0 .net *"_s10", 0 0, L_0x1227ad0; 1 drivers -v0xffb5c0_0 .net *"_s12", 0 0, L_0x1227c30; 1 drivers -v0xffb680_0 .net *"_s14", 0 0, L_0x1227e20; 1 drivers -v0xffb760_0 .net *"_s16", 0 0, L_0x1227fd0; 1 drivers -v0xffb890_0 .net *"_s3", 0 0, L_0x1227630; 1 drivers -v0xffb970_0 .net *"_s5", 0 0, L_0x1227790; 1 drivers -v0xffba50_0 .net *"_s6", 0 0, L_0x12279c0; 1 drivers -v0xffbb30_0 .net "in", 3 0, L_0x12280c0; 1 drivers -v0xffbca0_0 .net "ors", 1 0, L_0x12278d0; 1 drivers -v0xffbd80_0 .net "out", 0 0, L_0x1227db0; 1 drivers -L_0x1227630 .part L_0x12280c0, 0, 1; -L_0x1227790 .part L_0x12280c0, 1, 1; -L_0x12278d0 .concat8 [ 1 1 0 0], L_0x1227570, L_0x12279c0; -L_0x1227ad0 .part L_0x12280c0, 2, 1; -L_0x1227c30 .part L_0x12280c0, 3, 1; -L_0x1227e20 .part L_0x12278d0, 0, 1; -L_0x1227fd0 .part L_0x12278d0, 1, 1; -S_0xffbea0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0xffafd0; +L_0x2d06a20/d .functor OR 1, L_0x2d06ae0, L_0x2d06c40, C4<0>, C4<0>; +L_0x2d06a20 .delay 1 (30000,30000,30000) L_0x2d06a20/d; +L_0x2d06e70/d .functor OR 1, L_0x2d06f80, L_0x2d070e0, C4<0>, C4<0>; +L_0x2d06e70 .delay 1 (30000,30000,30000) L_0x2d06e70/d; +L_0x2d07260/d .functor OR 1, L_0x2d072d0, L_0x2d07480, C4<0>, C4<0>; +L_0x2d07260 .delay 1 (30000,30000,30000) L_0x2d07260/d; +v0x2ac0d10_0 .net *"_s0", 0 0, L_0x2d06a20; 1 drivers +v0x2ac0e10_0 .net *"_s10", 0 0, L_0x2d06f80; 1 drivers +v0x2ac0ef0_0 .net *"_s12", 0 0, L_0x2d070e0; 1 drivers +v0x2ac0fb0_0 .net *"_s14", 0 0, L_0x2d072d0; 1 drivers +v0x2ac1090_0 .net *"_s16", 0 0, L_0x2d07480; 1 drivers +v0x2ac11c0_0 .net *"_s3", 0 0, L_0x2d06ae0; 1 drivers +v0x2ac12a0_0 .net *"_s5", 0 0, L_0x2d06c40; 1 drivers +v0x2ac1380_0 .net *"_s6", 0 0, L_0x2d06e70; 1 drivers +v0x2ac1460_0 .net "in", 3 0, L_0x2d07570; 1 drivers +v0x2ac15d0_0 .net "ors", 1 0, L_0x2d06d80; 1 drivers +v0x2ac16b0_0 .net "out", 0 0, L_0x2d07260; 1 drivers +L_0x2d06ae0 .part L_0x2d07570, 0, 1; +L_0x2d06c40 .part L_0x2d07570, 1, 1; +L_0x2d06d80 .concat8 [ 1 1 0 0], L_0x2d06a20, L_0x2d06e70; +L_0x2d06f80 .part L_0x2d07570, 2, 1; +L_0x2d070e0 .part L_0x2d07570, 3, 1; +L_0x2d072d0 .part L_0x2d06d80, 0, 1; +L_0x2d07480 .part L_0x2d06d80, 1, 1; +S_0x2ac17d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ac0900; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12281f0/d .functor OR 1, L_0x1228260, L_0x12283c0, C4<0>, C4<0>; -L_0x12281f0 .delay 1 (30000,30000,30000) L_0x12281f0/d; -L_0x12285f0/d .functor OR 1, L_0x1228700, L_0x1228860, C4<0>, C4<0>; -L_0x12285f0 .delay 1 (30000,30000,30000) L_0x12285f0/d; -L_0x12289e0/d .functor OR 1, L_0x1228a50, L_0x1228c00, C4<0>, C4<0>; -L_0x12289e0 .delay 1 (30000,30000,30000) L_0x12289e0/d; -v0xffc060_0 .net *"_s0", 0 0, L_0x12281f0; 1 drivers -v0xffc160_0 .net *"_s10", 0 0, L_0x1228700; 1 drivers -v0xffc240_0 .net *"_s12", 0 0, L_0x1228860; 1 drivers -v0xffc300_0 .net *"_s14", 0 0, L_0x1228a50; 1 drivers -v0xffc3e0_0 .net *"_s16", 0 0, L_0x1228c00; 1 drivers -v0xffc510_0 .net *"_s3", 0 0, L_0x1228260; 1 drivers -v0xffc5f0_0 .net *"_s5", 0 0, L_0x12283c0; 1 drivers -v0xffc6d0_0 .net *"_s6", 0 0, L_0x12285f0; 1 drivers -v0xffc7b0_0 .net "in", 3 0, L_0x1228e30; 1 drivers -v0xffc920_0 .net "ors", 1 0, L_0x1228500; 1 drivers -v0xffca00_0 .net "out", 0 0, L_0x12289e0; 1 drivers -L_0x1228260 .part L_0x1228e30, 0, 1; -L_0x12283c0 .part L_0x1228e30, 1, 1; -L_0x1228500 .concat8 [ 1 1 0 0], L_0x12281f0, L_0x12285f0; -L_0x1228700 .part L_0x1228e30, 2, 1; -L_0x1228860 .part L_0x1228e30, 3, 1; -L_0x1228a50 .part L_0x1228500, 0, 1; -L_0x1228c00 .part L_0x1228500, 1, 1; -S_0xffd4e0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0xff6440; +L_0x2d076a0/d .functor OR 1, L_0x2d07710, L_0x2d07870, C4<0>, C4<0>; +L_0x2d076a0 .delay 1 (30000,30000,30000) L_0x2d076a0/d; +L_0x2d07aa0/d .functor OR 1, L_0x2d07bb0, L_0x2d07d10, C4<0>, C4<0>; +L_0x2d07aa0 .delay 1 (30000,30000,30000) L_0x2d07aa0/d; +L_0x2d07e90/d .functor OR 1, L_0x2d07f00, L_0x2d080b0, C4<0>, C4<0>; +L_0x2d07e90 .delay 1 (30000,30000,30000) L_0x2d07e90/d; +v0x2ac1990_0 .net *"_s0", 0 0, L_0x2d076a0; 1 drivers +v0x2ac1a90_0 .net *"_s10", 0 0, L_0x2d07bb0; 1 drivers +v0x2ac1b70_0 .net *"_s12", 0 0, L_0x2d07d10; 1 drivers +v0x2ac1c30_0 .net *"_s14", 0 0, L_0x2d07f00; 1 drivers +v0x2ac1d10_0 .net *"_s16", 0 0, L_0x2d080b0; 1 drivers +v0x2ac1e40_0 .net *"_s3", 0 0, L_0x2d07710; 1 drivers +v0x2ac1f20_0 .net *"_s5", 0 0, L_0x2d07870; 1 drivers +v0x2ac2000_0 .net *"_s6", 0 0, L_0x2d07aa0; 1 drivers +v0x2ac20e0_0 .net "in", 3 0, L_0x2d082e0; 1 drivers +v0x2ac2250_0 .net "ors", 1 0, L_0x2d079b0; 1 drivers +v0x2ac2330_0 .net "out", 0 0, L_0x2d07e90; 1 drivers +L_0x2d07710 .part L_0x2d082e0, 0, 1; +L_0x2d07870 .part L_0x2d082e0, 1, 1; +L_0x2d079b0 .concat8 [ 1 1 0 0], L_0x2d076a0, L_0x2d07aa0; +L_0x2d07bb0 .part L_0x2d082e0, 2, 1; +L_0x2d07d10 .part L_0x2d082e0, 3, 1; +L_0x2d07f00 .part L_0x2d079b0, 0, 1; +L_0x2d080b0 .part L_0x2d079b0, 1, 1; +S_0x2ac2e10 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2abbd70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10027e0_0 .net "ands", 7 0, L_0x1223490; 1 drivers -v0x10028f0_0 .net "in", 7 0, L_0x12218f0; alias, 1 drivers -v0x10029b0_0 .net "out", 0 0, L_0x1225490; alias, 1 drivers -v0x1002a80_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0xffd660 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0xffd4e0; +v0x2ac8170_0 .net "ands", 7 0, L_0x2d02940; 1 drivers +v0x2ac8280_0 .net "in", 7 0, L_0x2d008c0; alias, 1 drivers +v0x2ac8340_0 .net "out", 0 0, L_0x2d04940; alias, 1 drivers +v0x2ac8410_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2ac2f90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2ac2e10; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0xfffda0_0 .net "A", 7 0, L_0x12218f0; alias, 1 drivers -v0xfffea0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xffff60_0 .net *"_s0", 0 0, L_0x1221c80; 1 drivers -v0x1000020_0 .net *"_s12", 0 0, L_0x1222640; 1 drivers -v0x1000100_0 .net *"_s16", 0 0, L_0x12229a0; 1 drivers -v0x1000230_0 .net *"_s20", 0 0, L_0x1222dd0; 1 drivers -v0x1000310_0 .net *"_s24", 0 0, L_0x1223100; 1 drivers -v0x10003f0_0 .net *"_s28", 0 0, L_0x1223090; 1 drivers -v0x10004d0_0 .net *"_s4", 0 0, L_0x1222020; 1 drivers -v0x1000640_0 .net *"_s8", 0 0, L_0x1222330; 1 drivers -v0x1000720_0 .net "out", 7 0, L_0x1223490; alias, 1 drivers -L_0x1221d90 .part L_0x12218f0, 0, 1; -L_0x1221f80 .part v0x12010b0_0, 0, 1; -L_0x12220e0 .part L_0x12218f0, 1, 1; -L_0x1222240 .part v0x12010b0_0, 1, 1; -L_0x12223f0 .part L_0x12218f0, 2, 1; -L_0x1222550 .part v0x12010b0_0, 2, 1; -L_0x1222700 .part L_0x12218f0, 3, 1; -L_0x1222860 .part v0x12010b0_0, 3, 1; -L_0x1222a60 .part L_0x12218f0, 4, 1; -L_0x1222cd0 .part v0x12010b0_0, 4, 1; -L_0x1222e40 .part L_0x12218f0, 5, 1; -L_0x1222fa0 .part v0x12010b0_0, 5, 1; -L_0x12231c0 .part L_0x12218f0, 6, 1; -L_0x1223320 .part v0x12010b0_0, 6, 1; -LS_0x1223490_0_0 .concat8 [ 1 1 1 1], L_0x1221c80, L_0x1222020, L_0x1222330, L_0x1222640; -LS_0x1223490_0_4 .concat8 [ 1 1 1 1], L_0x12229a0, L_0x1222dd0, L_0x1223100, L_0x1223090; -L_0x1223490 .concat8 [ 4 4 0 0], LS_0x1223490_0_0, LS_0x1223490_0_4; -L_0x1223850 .part L_0x12218f0, 7, 1; -L_0x1223a40 .part v0x12010b0_0, 7, 1; -S_0xffd8a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xffdab0 .param/l "i" 0 4 54, +C4<00>; -L_0x1221c80/d .functor AND 1, L_0x1221d90, L_0x1221f80, C4<1>, C4<1>; -L_0x1221c80 .delay 1 (30000,30000,30000) L_0x1221c80/d; -v0xffdb90_0 .net *"_s0", 0 0, L_0x1221d90; 1 drivers -v0xffdc70_0 .net *"_s1", 0 0, L_0x1221f80; 1 drivers -S_0xffdd50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xffdf60 .param/l "i" 0 4 54, +C4<01>; -L_0x1222020/d .functor AND 1, L_0x12220e0, L_0x1222240, C4<1>, C4<1>; -L_0x1222020 .delay 1 (30000,30000,30000) L_0x1222020/d; -v0xffe020_0 .net *"_s0", 0 0, L_0x12220e0; 1 drivers -v0xffe100_0 .net *"_s1", 0 0, L_0x1222240; 1 drivers -S_0xffe1e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xffe420 .param/l "i" 0 4 54, +C4<010>; -L_0x1222330/d .functor AND 1, L_0x12223f0, L_0x1222550, C4<1>, C4<1>; -L_0x1222330 .delay 1 (30000,30000,30000) L_0x1222330/d; -v0xffe4c0_0 .net *"_s0", 0 0, L_0x12223f0; 1 drivers -v0xffe5a0_0 .net *"_s1", 0 0, L_0x1222550; 1 drivers -S_0xffe680 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xffe890 .param/l "i" 0 4 54, +C4<011>; -L_0x1222640/d .functor AND 1, L_0x1222700, L_0x1222860, C4<1>, C4<1>; -L_0x1222640 .delay 1 (30000,30000,30000) L_0x1222640/d; -v0xffe950_0 .net *"_s0", 0 0, L_0x1222700; 1 drivers -v0xffea30_0 .net *"_s1", 0 0, L_0x1222860; 1 drivers -S_0xffeb10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xffed70 .param/l "i" 0 4 54, +C4<0100>; -L_0x12229a0/d .functor AND 1, L_0x1222a60, L_0x1222cd0, C4<1>, C4<1>; -L_0x12229a0 .delay 1 (30000,30000,30000) L_0x12229a0/d; -v0xffee30_0 .net *"_s0", 0 0, L_0x1222a60; 1 drivers -v0xffef10_0 .net *"_s1", 0 0, L_0x1222cd0; 1 drivers -S_0xffeff0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xfff200 .param/l "i" 0 4 54, +C4<0101>; -L_0x1222dd0/d .functor AND 1, L_0x1222e40, L_0x1222fa0, C4<1>, C4<1>; -L_0x1222dd0 .delay 1 (30000,30000,30000) L_0x1222dd0/d; -v0xfff2c0_0 .net *"_s0", 0 0, L_0x1222e40; 1 drivers -v0xfff3a0_0 .net *"_s1", 0 0, L_0x1222fa0; 1 drivers -S_0xfff480 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xfff690 .param/l "i" 0 4 54, +C4<0110>; -L_0x1223100/d .functor AND 1, L_0x12231c0, L_0x1223320, C4<1>, C4<1>; -L_0x1223100 .delay 1 (30000,30000,30000) L_0x1223100/d; -v0xfff750_0 .net *"_s0", 0 0, L_0x12231c0; 1 drivers -v0xfff830_0 .net *"_s1", 0 0, L_0x1223320; 1 drivers -S_0xfff910 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0xffd660; - .timescale -9 -12; -P_0xfffb20 .param/l "i" 0 4 54, +C4<0111>; -L_0x1223090/d .functor AND 1, L_0x1223850, L_0x1223a40, C4<1>, C4<1>; -L_0x1223090 .delay 1 (30000,30000,30000) L_0x1223090/d; -v0xfffbe0_0 .net *"_s0", 0 0, L_0x1223850; 1 drivers -v0xfffcc0_0 .net *"_s1", 0 0, L_0x1223a40; 1 drivers -S_0x1000880 .scope module, "ors" "or8" 4 72, 4 16 0, S_0xffd4e0; +v0x2ac56d0_0 .net "A", 7 0, L_0x2d008c0; alias, 1 drivers +v0x2ac57d0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ac5890_0 .net *"_s0", 0 0, L_0x2d01190; 1 drivers +v0x2ac5950_0 .net *"_s12", 0 0, L_0x2d01b50; 1 drivers +v0x2ac5a30_0 .net *"_s16", 0 0, L_0x2d01eb0; 1 drivers +v0x2ac5b60_0 .net *"_s20", 0 0, L_0x2d02280; 1 drivers +v0x2ac5c40_0 .net *"_s24", 0 0, L_0x2d025b0; 1 drivers +v0x2ac5d20_0 .net *"_s28", 0 0, L_0x2d02540; 1 drivers +v0x2ac5e00_0 .net *"_s4", 0 0, L_0x2d01530; 1 drivers +v0x2ac5f70_0 .net *"_s8", 0 0, L_0x2d01840; 1 drivers +v0x2ac6050_0 .net "out", 7 0, L_0x2d02940; alias, 1 drivers +L_0x2d012a0 .part L_0x2d008c0, 0, 1; +L_0x2d01490 .part v0x2cdd2e0_0, 0, 1; +L_0x2d015f0 .part L_0x2d008c0, 1, 1; +L_0x2d01750 .part v0x2cdd2e0_0, 1, 1; +L_0x2d01900 .part L_0x2d008c0, 2, 1; +L_0x2d01a60 .part v0x2cdd2e0_0, 2, 1; +L_0x2d01c10 .part L_0x2d008c0, 3, 1; +L_0x2d01d70 .part v0x2cdd2e0_0, 3, 1; +L_0x2d01f70 .part L_0x2d008c0, 4, 1; +L_0x2d021e0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d022f0 .part L_0x2d008c0, 5, 1; +L_0x2d02450 .part v0x2cdd2e0_0, 5, 1; +L_0x2d02670 .part L_0x2d008c0, 6, 1; +L_0x2d027d0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d02940_0_0 .concat8 [ 1 1 1 1], L_0x2d01190, L_0x2d01530, L_0x2d01840, L_0x2d01b50; +LS_0x2d02940_0_4 .concat8 [ 1 1 1 1], L_0x2d01eb0, L_0x2d02280, L_0x2d025b0, L_0x2d02540; +L_0x2d02940 .concat8 [ 4 4 0 0], LS_0x2d02940_0_0, LS_0x2d02940_0_4; +L_0x2d02d00 .part L_0x2d008c0, 7, 1; +L_0x2d02ef0 .part v0x2cdd2e0_0, 7, 1; +S_0x2ac31d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac33e0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d01190/d .functor AND 1, L_0x2d012a0, L_0x2d01490, C4<1>, C4<1>; +L_0x2d01190 .delay 1 (30000,30000,30000) L_0x2d01190/d; +v0x2ac34c0_0 .net *"_s0", 0 0, L_0x2d012a0; 1 drivers +v0x2ac35a0_0 .net *"_s1", 0 0, L_0x2d01490; 1 drivers +S_0x2ac3680 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac3890 .param/l "i" 0 4 54, +C4<01>; +L_0x2d01530/d .functor AND 1, L_0x2d015f0, L_0x2d01750, C4<1>, C4<1>; +L_0x2d01530 .delay 1 (30000,30000,30000) L_0x2d01530/d; +v0x2ac3950_0 .net *"_s0", 0 0, L_0x2d015f0; 1 drivers +v0x2ac3a30_0 .net *"_s1", 0 0, L_0x2d01750; 1 drivers +S_0x2ac3b10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac3d50 .param/l "i" 0 4 54, +C4<010>; +L_0x2d01840/d .functor AND 1, L_0x2d01900, L_0x2d01a60, C4<1>, C4<1>; +L_0x2d01840 .delay 1 (30000,30000,30000) L_0x2d01840/d; +v0x2ac3df0_0 .net *"_s0", 0 0, L_0x2d01900; 1 drivers +v0x2ac3ed0_0 .net *"_s1", 0 0, L_0x2d01a60; 1 drivers +S_0x2ac3fb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac41c0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d01b50/d .functor AND 1, L_0x2d01c10, L_0x2d01d70, C4<1>, C4<1>; +L_0x2d01b50 .delay 1 (30000,30000,30000) L_0x2d01b50/d; +v0x2ac4280_0 .net *"_s0", 0 0, L_0x2d01c10; 1 drivers +v0x2ac4360_0 .net *"_s1", 0 0, L_0x2d01d70; 1 drivers +S_0x2ac4440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac46a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d01eb0/d .functor AND 1, L_0x2d01f70, L_0x2d021e0, C4<1>, C4<1>; +L_0x2d01eb0 .delay 1 (30000,30000,30000) L_0x2d01eb0/d; +v0x2ac4760_0 .net *"_s0", 0 0, L_0x2d01f70; 1 drivers +v0x2ac4840_0 .net *"_s1", 0 0, L_0x2d021e0; 1 drivers +S_0x2ac4920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac4b30 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d02280/d .functor AND 1, L_0x2d022f0, L_0x2d02450, C4<1>, C4<1>; +L_0x2d02280 .delay 1 (30000,30000,30000) L_0x2d02280/d; +v0x2ac4bf0_0 .net *"_s0", 0 0, L_0x2d022f0; 1 drivers +v0x2ac4cd0_0 .net *"_s1", 0 0, L_0x2d02450; 1 drivers +S_0x2ac4db0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac4fc0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d025b0/d .functor AND 1, L_0x2d02670, L_0x2d027d0, C4<1>, C4<1>; +L_0x2d025b0 .delay 1 (30000,30000,30000) L_0x2d025b0/d; +v0x2ac5080_0 .net *"_s0", 0 0, L_0x2d02670; 1 drivers +v0x2ac5160_0 .net *"_s1", 0 0, L_0x2d027d0; 1 drivers +S_0x2ac5240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2ac2f90; + .timescale -9 -12; +P_0x2ac5450 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d02540/d .functor AND 1, L_0x2d02d00, L_0x2d02ef0, C4<1>, C4<1>; +L_0x2d02540 .delay 1 (30000,30000,30000) L_0x2d02540/d; +v0x2ac5510_0 .net *"_s0", 0 0, L_0x2d02d00; 1 drivers +v0x2ac55f0_0 .net *"_s1", 0 0, L_0x2d02ef0; 1 drivers +S_0x2ac61b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2ac2e10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1225490/d .functor OR 1, L_0x1225550, L_0x1225700, C4<0>, C4<0>; -L_0x1225490 .delay 1 (30000,30000,30000) L_0x1225490/d; -v0x1002370_0 .net *"_s10", 0 0, L_0x1225550; 1 drivers -v0x1002450_0 .net *"_s12", 0 0, L_0x1225700; 1 drivers -v0x1002530_0 .net "in", 7 0, L_0x1223490; alias, 1 drivers -v0x1002600_0 .net "ors", 1 0, L_0x12252b0; 1 drivers -v0x10026c0_0 .net "out", 0 0, L_0x1225490; alias, 1 drivers -L_0x1224680 .part L_0x1223490, 0, 4; -L_0x12252b0 .concat8 [ 1 1 0 0], L_0x1224370, L_0x1224fa0; -L_0x12253f0 .part L_0x1223490, 4, 4; -L_0x1225550 .part L_0x12252b0, 0, 1; -L_0x1225700 .part L_0x12252b0, 1, 1; -S_0x1000a40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1000880; +L_0x2d04940/d .functor OR 1, L_0x2d04a00, L_0x2d04bb0, C4<0>, C4<0>; +L_0x2d04940 .delay 1 (30000,30000,30000) L_0x2d04940/d; +v0x2ac7d00_0 .net *"_s10", 0 0, L_0x2d04a00; 1 drivers +v0x2ac7de0_0 .net *"_s12", 0 0, L_0x2d04bb0; 1 drivers +v0x2ac7ec0_0 .net "in", 7 0, L_0x2d02940; alias, 1 drivers +v0x2ac7f90_0 .net "ors", 1 0, L_0x2d04760; 1 drivers +v0x2ac8050_0 .net "out", 0 0, L_0x2d04940; alias, 1 drivers +L_0x2d03b30 .part L_0x2d02940, 0, 4; +L_0x2d04760 .concat8 [ 1 1 0 0], L_0x2d03820, L_0x2d04450; +L_0x2d048a0 .part L_0x2d02940, 4, 4; +L_0x2d04a00 .part L_0x2d04760, 0, 1; +L_0x2d04bb0 .part L_0x2d04760, 1, 1; +S_0x2ac6370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ac61b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1223b30/d .functor OR 1, L_0x1223bf0, L_0x1223d50, C4<0>, C4<0>; -L_0x1223b30 .delay 1 (30000,30000,30000) L_0x1223b30/d; -L_0x1223f80/d .functor OR 1, L_0x1224090, L_0x12241f0, C4<0>, C4<0>; -L_0x1223f80 .delay 1 (30000,30000,30000) L_0x1223f80/d; -L_0x1224370/d .functor OR 1, L_0x12243e0, L_0x1224590, C4<0>, C4<0>; -L_0x1224370 .delay 1 (30000,30000,30000) L_0x1224370/d; -v0x1000c90_0 .net *"_s0", 0 0, L_0x1223b30; 1 drivers -v0x1000d90_0 .net *"_s10", 0 0, L_0x1224090; 1 drivers -v0x1000e70_0 .net *"_s12", 0 0, L_0x12241f0; 1 drivers -v0x1000f30_0 .net *"_s14", 0 0, L_0x12243e0; 1 drivers -v0x1000ff0_0 .net *"_s16", 0 0, L_0x1224590; 1 drivers -v0x10010e0_0 .net *"_s3", 0 0, L_0x1223bf0; 1 drivers -v0x10011c0_0 .net *"_s5", 0 0, L_0x1223d50; 1 drivers -v0x10012a0_0 .net *"_s6", 0 0, L_0x1223f80; 1 drivers -v0x1001380_0 .net "in", 3 0, L_0x1224680; 1 drivers -v0x10014f0_0 .net "ors", 1 0, L_0x1223e90; 1 drivers -v0x10015d0_0 .net "out", 0 0, L_0x1224370; 1 drivers -L_0x1223bf0 .part L_0x1224680, 0, 1; -L_0x1223d50 .part L_0x1224680, 1, 1; -L_0x1223e90 .concat8 [ 1 1 0 0], L_0x1223b30, L_0x1223f80; -L_0x1224090 .part L_0x1224680, 2, 1; -L_0x12241f0 .part L_0x1224680, 3, 1; -L_0x12243e0 .part L_0x1223e90, 0, 1; -L_0x1224590 .part L_0x1223e90, 1, 1; -S_0x10016f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1000880; +L_0x2d02fe0/d .functor OR 1, L_0x2d030a0, L_0x2d03200, C4<0>, C4<0>; +L_0x2d02fe0 .delay 1 (30000,30000,30000) L_0x2d02fe0/d; +L_0x2d03430/d .functor OR 1, L_0x2d03540, L_0x2d036a0, C4<0>, C4<0>; +L_0x2d03430 .delay 1 (30000,30000,30000) L_0x2d03430/d; +L_0x2d03820/d .functor OR 1, L_0x2d03890, L_0x2d03a40, C4<0>, C4<0>; +L_0x2d03820 .delay 1 (30000,30000,30000) L_0x2d03820/d; +v0x2ac65c0_0 .net *"_s0", 0 0, L_0x2d02fe0; 1 drivers +v0x2ac66c0_0 .net *"_s10", 0 0, L_0x2d03540; 1 drivers +v0x2ac67a0_0 .net *"_s12", 0 0, L_0x2d036a0; 1 drivers +v0x2ac6860_0 .net *"_s14", 0 0, L_0x2d03890; 1 drivers +v0x2ac6940_0 .net *"_s16", 0 0, L_0x2d03a40; 1 drivers +v0x2ac6a70_0 .net *"_s3", 0 0, L_0x2d030a0; 1 drivers +v0x2ac6b50_0 .net *"_s5", 0 0, L_0x2d03200; 1 drivers +v0x2ac6c30_0 .net *"_s6", 0 0, L_0x2d03430; 1 drivers +v0x2ac6d10_0 .net "in", 3 0, L_0x2d03b30; 1 drivers +v0x2ac6e80_0 .net "ors", 1 0, L_0x2d03340; 1 drivers +v0x2ac6f60_0 .net "out", 0 0, L_0x2d03820; 1 drivers +L_0x2d030a0 .part L_0x2d03b30, 0, 1; +L_0x2d03200 .part L_0x2d03b30, 1, 1; +L_0x2d03340 .concat8 [ 1 1 0 0], L_0x2d02fe0, L_0x2d03430; +L_0x2d03540 .part L_0x2d03b30, 2, 1; +L_0x2d036a0 .part L_0x2d03b30, 3, 1; +L_0x2d03890 .part L_0x2d03340, 0, 1; +L_0x2d03a40 .part L_0x2d03340, 1, 1; +S_0x2ac7080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ac61b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12247b0/d .functor OR 1, L_0x1224820, L_0x1224980, C4<0>, C4<0>; -L_0x12247b0 .delay 1 (30000,30000,30000) L_0x12247b0/d; -L_0x1224bb0/d .functor OR 1, L_0x1224cc0, L_0x1224e20, C4<0>, C4<0>; -L_0x1224bb0 .delay 1 (30000,30000,30000) L_0x1224bb0/d; -L_0x1224fa0/d .functor OR 1, L_0x1225010, L_0x12251c0, C4<0>, C4<0>; -L_0x1224fa0 .delay 1 (30000,30000,30000) L_0x1224fa0/d; -v0x10018b0_0 .net *"_s0", 0 0, L_0x12247b0; 1 drivers -v0x10019b0_0 .net *"_s10", 0 0, L_0x1224cc0; 1 drivers -v0x1001a90_0 .net *"_s12", 0 0, L_0x1224e20; 1 drivers -v0x1001b50_0 .net *"_s14", 0 0, L_0x1225010; 1 drivers -v0x1001c30_0 .net *"_s16", 0 0, L_0x12251c0; 1 drivers -v0x1001d60_0 .net *"_s3", 0 0, L_0x1224820; 1 drivers -v0x1001e40_0 .net *"_s5", 0 0, L_0x1224980; 1 drivers -v0x1001f20_0 .net *"_s6", 0 0, L_0x1224bb0; 1 drivers -v0x1002000_0 .net "in", 3 0, L_0x12253f0; 1 drivers -v0x1002170_0 .net "ors", 1 0, L_0x1224ac0; 1 drivers -v0x1002250_0 .net "out", 0 0, L_0x1224fa0; 1 drivers -L_0x1224820 .part L_0x12253f0, 0, 1; -L_0x1224980 .part L_0x12253f0, 1, 1; -L_0x1224ac0 .concat8 [ 1 1 0 0], L_0x12247b0, L_0x1224bb0; -L_0x1224cc0 .part L_0x12253f0, 2, 1; -L_0x1224e20 .part L_0x12253f0, 3, 1; -L_0x1225010 .part L_0x1224ac0, 0, 1; -L_0x12251c0 .part L_0x1224ac0, 1, 1; -S_0x1002b60 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xff6440; +L_0x2d03c60/d .functor OR 1, L_0x2d03cd0, L_0x2d03e30, C4<0>, C4<0>; +L_0x2d03c60 .delay 1 (30000,30000,30000) L_0x2d03c60/d; +L_0x2d04060/d .functor OR 1, L_0x2d04170, L_0x2d042d0, C4<0>, C4<0>; +L_0x2d04060 .delay 1 (30000,30000,30000) L_0x2d04060/d; +L_0x2d04450/d .functor OR 1, L_0x2d044c0, L_0x2d04670, C4<0>, C4<0>; +L_0x2d04450 .delay 1 (30000,30000,30000) L_0x2d04450/d; +v0x2ac7240_0 .net *"_s0", 0 0, L_0x2d03c60; 1 drivers +v0x2ac7340_0 .net *"_s10", 0 0, L_0x2d04170; 1 drivers +v0x2ac7420_0 .net *"_s12", 0 0, L_0x2d042d0; 1 drivers +v0x2ac74e0_0 .net *"_s14", 0 0, L_0x2d044c0; 1 drivers +v0x2ac75c0_0 .net *"_s16", 0 0, L_0x2d04670; 1 drivers +v0x2ac76f0_0 .net *"_s3", 0 0, L_0x2d03cd0; 1 drivers +v0x2ac77d0_0 .net *"_s5", 0 0, L_0x2d03e30; 1 drivers +v0x2ac78b0_0 .net *"_s6", 0 0, L_0x2d04060; 1 drivers +v0x2ac7990_0 .net "in", 3 0, L_0x2d048a0; 1 drivers +v0x2ac7b00_0 .net "ors", 1 0, L_0x2d03f70; 1 drivers +v0x2ac7be0_0 .net "out", 0 0, L_0x2d04450; 1 drivers +L_0x2d03cd0 .part L_0x2d048a0, 0, 1; +L_0x2d03e30 .part L_0x2d048a0, 1, 1; +L_0x2d03f70 .concat8 [ 1 1 0 0], L_0x2d03c60, L_0x2d04060; +L_0x2d04170 .part L_0x2d048a0, 2, 1; +L_0x2d042d0 .part L_0x2d048a0, 3, 1; +L_0x2d044c0 .part L_0x2d03f70, 0, 1; +L_0x2d04670 .part L_0x2d03f70, 1, 1; +S_0x2ac84f0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2abbd70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -2294,80 +2420,80 @@ S_0x1002b60 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0xff6440; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1220c60/d .functor XNOR 1, L_0x1229330, L_0x1229490, C4<0>, C4<0>; -L_0x1220c60 .delay 1 (20000,20000,20000) L_0x1220c60/d; -L_0x1220ed0/d .functor AND 1, L_0x1229330, L_0x121fcb0, C4<1>, C4<1>; -L_0x1220ed0 .delay 1 (30000,30000,30000) L_0x1220ed0/d; -L_0x1220f40/d .functor AND 1, L_0x1220c60, L_0x1229530, C4<1>, C4<1>; -L_0x1220f40 .delay 1 (30000,30000,30000) L_0x1220f40/d; -L_0x12210a0/d .functor OR 1, L_0x1220f40, L_0x1220ed0, C4<0>, C4<0>; -L_0x12210a0 .delay 1 (30000,30000,30000) L_0x12210a0/d; -v0x1002e10_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers -v0x1002f00_0 .net "a_", 0 0, L_0x121fba0; alias, 1 drivers -v0x1002fc0_0 .net "b", 0 0, L_0x1229490; alias, 1 drivers -v0x10030b0_0 .net "b_", 0 0, L_0x121fcb0; alias, 1 drivers -v0x1003150_0 .net "carryin", 0 0, L_0x1229530; alias, 1 drivers -v0x1003290_0 .net "eq", 0 0, L_0x1220c60; 1 drivers -v0x1003350_0 .net "lt", 0 0, L_0x1220ed0; 1 drivers -v0x1003410_0 .net "out", 0 0, L_0x12210a0; 1 drivers -v0x10034d0_0 .net "w0", 0 0, L_0x1220f40; 1 drivers -S_0x1003720 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0xff6440; +L_0x2cff770/d .functor XNOR 1, L_0x2d087e0, L_0x2d08940, C4<0>, C4<0>; +L_0x2cff770 .delay 1 (20000,20000,20000) L_0x2cff770/d; +L_0x2cff8f0/d .functor AND 1, L_0x2d087e0, L_0x2cfe460, C4<1>, C4<1>; +L_0x2cff8f0 .delay 1 (30000,30000,30000) L_0x2cff8f0/d; +L_0x2cffa50/d .functor AND 1, L_0x2cff770, L_0x2d089e0, C4<1>, C4<1>; +L_0x2cffa50 .delay 1 (30000,30000,30000) L_0x2cffa50/d; +L_0x2cffb60/d .functor OR 1, L_0x2cffa50, L_0x2cff8f0, C4<0>, C4<0>; +L_0x2cffb60 .delay 1 (30000,30000,30000) L_0x2cffb60/d; +v0x2ac87a0_0 .net "a", 0 0, L_0x2d087e0; alias, 1 drivers +v0x2ac8890_0 .net "a_", 0 0, L_0x2cfe350; alias, 1 drivers +v0x2ac8950_0 .net "b", 0 0, L_0x2d08940; alias, 1 drivers +v0x2ac8a40_0 .net "b_", 0 0, L_0x2cfe460; alias, 1 drivers +v0x2ac8ae0_0 .net "carryin", 0 0, L_0x2d089e0; alias, 1 drivers +v0x2ac8c20_0 .net "eq", 0 0, L_0x2cff770; 1 drivers +v0x2ac8ce0_0 .net "lt", 0 0, L_0x2cff8f0; 1 drivers +v0x2ac8da0_0 .net "out", 0 0, L_0x2cffb60; 1 drivers +v0x2ac8e60_0 .net "w0", 0 0, L_0x2cffa50; 1 drivers +S_0x2ac90b0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2abbd70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1220a40/d .functor OR 1, L_0x1220590, L_0x1004980, C4<0>, C4<0>; -L_0x1220a40 .delay 1 (30000,30000,30000) L_0x1220a40/d; -v0x1004510_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers -v0x1004660_0 .net "b", 0 0, L_0x121fcb0; alias, 1 drivers -v0x1004720_0 .net "c1", 0 0, L_0x1220590; 1 drivers -v0x10047c0_0 .net "c2", 0 0, L_0x1004980; 1 drivers -v0x1004890_0 .net "carryin", 0 0, L_0x1229530; alias, 1 drivers -v0x1004a10_0 .net "carryout", 0 0, L_0x1220a40; 1 drivers -v0x1004ab0_0 .net "s1", 0 0, L_0x12204d0; 1 drivers -v0x1004b50_0 .net "sum", 0 0, L_0x12206f0; 1 drivers -S_0x1003970 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1003720; +L_0x2cff350/d .functor OR 1, L_0x2cfee50, L_0x2aca310, C4<0>, C4<0>; +L_0x2cff350 .delay 1 (30000,30000,30000) L_0x2cff350/d; +v0x2ac9ea0_0 .net "a", 0 0, L_0x2d087e0; alias, 1 drivers +v0x2ac9ff0_0 .net "b", 0 0, L_0x2cfe460; alias, 1 drivers +v0x2aca0b0_0 .net "c1", 0 0, L_0x2cfee50; 1 drivers +v0x2aca150_0 .net "c2", 0 0, L_0x2aca310; 1 drivers +v0x2aca220_0 .net "carryin", 0 0, L_0x2d089e0; alias, 1 drivers +v0x2aca3a0_0 .net "carryout", 0 0, L_0x2cff350; 1 drivers +v0x2aca440_0 .net "s1", 0 0, L_0x2cfed90; 1 drivers +v0x2aca4e0_0 .net "sum", 0 0, L_0x2cfefb0; 1 drivers +S_0x2ac9300 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2ac90b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12204d0/d .functor XOR 1, L_0x1229330, L_0x121fcb0, C4<0>, C4<0>; -L_0x12204d0 .delay 1 (30000,30000,30000) L_0x12204d0/d; -L_0x1220590/d .functor AND 1, L_0x1229330, L_0x121fcb0, C4<1>, C4<1>; -L_0x1220590 .delay 1 (30000,30000,30000) L_0x1220590/d; -v0x1003bd0_0 .net "a", 0 0, L_0x1229330; alias, 1 drivers -v0x1003c90_0 .net "b", 0 0, L_0x121fcb0; alias, 1 drivers -v0x1003d50_0 .net "carryout", 0 0, L_0x1220590; alias, 1 drivers -v0x1003df0_0 .net "sum", 0 0, L_0x12204d0; alias, 1 drivers -S_0x1003f20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1003720; +L_0x2cfed90/d .functor XOR 1, L_0x2d087e0, L_0x2cfe460, C4<0>, C4<0>; +L_0x2cfed90 .delay 1 (30000,30000,30000) L_0x2cfed90/d; +L_0x2cfee50/d .functor AND 1, L_0x2d087e0, L_0x2cfe460, C4<1>, C4<1>; +L_0x2cfee50 .delay 1 (30000,30000,30000) L_0x2cfee50/d; +v0x2ac9560_0 .net "a", 0 0, L_0x2d087e0; alias, 1 drivers +v0x2ac9620_0 .net "b", 0 0, L_0x2cfe460; alias, 1 drivers +v0x2ac96e0_0 .net "carryout", 0 0, L_0x2cfee50; alias, 1 drivers +v0x2ac9780_0 .net "sum", 0 0, L_0x2cfed90; alias, 1 drivers +S_0x2ac98b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2ac90b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12206f0/d .functor XOR 1, L_0x12204d0, L_0x1229530, C4<0>, C4<0>; -L_0x12206f0 .delay 1 (30000,30000,30000) L_0x12206f0/d; -L_0x1004980/d .functor AND 1, L_0x12204d0, L_0x1229530, C4<1>, C4<1>; -L_0x1004980 .delay 1 (30000,30000,30000) L_0x1004980/d; -v0x1004180_0 .net "a", 0 0, L_0x12204d0; alias, 1 drivers -v0x1004250_0 .net "b", 0 0, L_0x1229530; alias, 1 drivers -v0x10042f0_0 .net "carryout", 0 0, L_0x1004980; alias, 1 drivers -v0x10043c0_0 .net "sum", 0 0, L_0x12206f0; alias, 1 drivers -S_0x1005f70 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0xff6170; - .timescale -9 -12; -L_0x2b0ab3d05378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d053c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1229660/d .functor OR 1, L_0x2b0ab3d05378, L_0x2b0ab3d053c0, C4<0>, C4<0>; -L_0x1229660 .delay 1 (30000,30000,30000) L_0x1229660/d; -v0x1006160_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05378; 1 drivers -v0x1006240_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d053c0; 1 drivers -S_0x1006320 .scope generate, "alu_slices[4]" "alu_slices[4]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1006580 .param/l "i" 0 3 41, +C4<0100>; -S_0x1006640 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1006320; +L_0x2cfefb0/d .functor XOR 1, L_0x2cfed90, L_0x2d089e0, C4<0>, C4<0>; +L_0x2cfefb0 .delay 1 (30000,30000,30000) L_0x2cfefb0/d; +L_0x2aca310/d .functor AND 1, L_0x2cfed90, L_0x2d089e0, C4<1>, C4<1>; +L_0x2aca310 .delay 1 (30000,30000,30000) L_0x2aca310/d; +v0x2ac9b10_0 .net "a", 0 0, L_0x2cfed90; alias, 1 drivers +v0x2ac9be0_0 .net "b", 0 0, L_0x2d089e0; alias, 1 drivers +v0x2ac9c80_0 .net "carryout", 0 0, L_0x2aca310; alias, 1 drivers +v0x2ac9d50_0 .net "sum", 0 0, L_0x2cfefb0; alias, 1 drivers +S_0x2acc570 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2abbaa0; + .timescale -9 -12; +L_0x2ac6110b6eb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6f00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d08880/d .functor OR 1, L_0x2ac6110b6eb8, L_0x2ac6110b6f00, C4<0>, C4<0>; +L_0x2d08880 .delay 1 (30000,30000,30000) L_0x2d08880/d; +v0x2acc760_0 .net/2u *"_s0", 0 0, L_0x2ac6110b6eb8; 1 drivers +v0x2acc840_0 .net/2u *"_s2", 0 0, L_0x2ac6110b6f00; 1 drivers +S_0x2acc920 .scope generate, "alu_slices[4]" "alu_slices[4]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2accb80 .param/l "i" 0 3 39, +C4<0100>; +S_0x2accc40 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2acc920; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -2376,445 +2502,476 @@ S_0x1006640 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1006320; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1229770/d .functor NOT 1, L_0x1232f10, C4<0>, C4<0>, C4<0>; -L_0x1229770 .delay 1 (10000,10000,10000) L_0x1229770/d; -L_0x1229880/d .functor NOT 1, L_0x1233070, C4<0>, C4<0>, C4<0>; -L_0x1229880 .delay 1 (10000,10000,10000) L_0x1229880/d; -L_0x122a8d0/d .functor XOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; -L_0x122a8d0 .delay 1 (30000,30000,30000) L_0x122a8d0/d; -L_0x2b0ab3d05408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x122af80/d .functor OR 1, L_0x2b0ab3d05408, L_0x2b0ab3d05450, C4<0>, C4<0>; -L_0x122af80 .delay 1 (30000,30000,30000) L_0x122af80/d; -L_0x122b180/d .functor AND 1, L_0x1232f10, L_0x1233070, C4<1>, C4<1>; -L_0x122b180 .delay 1 (30000,30000,30000) L_0x122b180/d; -L_0x122b240/d .functor NAND 1, L_0x1232f10, L_0x1233070, C4<1>, C4<1>; -L_0x122b240 .delay 1 (20000,20000,20000) L_0x122b240/d; -L_0x122b3a0/d .functor XOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; -L_0x122b3a0 .delay 1 (20000,20000,20000) L_0x122b3a0/d; -L_0x122b850/d .functor OR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; -L_0x122b850 .delay 1 (30000,30000,30000) L_0x122b850/d; -L_0x1232e10/d .functor NOT 1, L_0x122f0e0, C4<0>, C4<0>, C4<0>; -L_0x1232e10 .delay 1 (10000,10000,10000) L_0x1232e10/d; -v0x1014d40_0 .net "A", 0 0, L_0x1232f10; 1 drivers -v0x1014e00_0 .net "A_", 0 0, L_0x1229770; 1 drivers -v0x1014ec0_0 .net "B", 0 0, L_0x1233070; 1 drivers -v0x1014f90_0 .net "B_", 0 0, L_0x1229880; 1 drivers -v0x1015030_0 .net *"_s12", 0 0, L_0x122af80; 1 drivers -v0x1015120_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05408; 1 drivers -v0x10151e0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05450; 1 drivers -v0x10152c0_0 .net *"_s18", 0 0, L_0x122b180; 1 drivers -v0x10153a0_0 .net *"_s20", 0 0, L_0x122b240; 1 drivers -v0x1015510_0 .net *"_s22", 0 0, L_0x122b3a0; 1 drivers -v0x10155f0_0 .net *"_s24", 0 0, L_0x122b850; 1 drivers -o0x2b0ab3cae808 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10156d0_0 name=_s30 -o0x2b0ab3cae838 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10157b0_0 name=_s32 -v0x1015890_0 .net *"_s8", 0 0, L_0x122a8d0; 1 drivers -v0x1015970_0 .net "carryin", 0 0, L_0x1233110; 1 drivers -v0x1015a10_0 .net "carryout", 0 0, L_0x1232ab0; 1 drivers -v0x1015ab0_0 .net "carryouts", 7 0, L_0x13535a0; 1 drivers -v0x1015c60_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1015d00_0 .net "result", 0 0, L_0x122f0e0; 1 drivers -v0x1015df0_0 .net "results", 7 0, L_0x122b620; 1 drivers -v0x1015f00_0 .net "zero", 0 0, L_0x1232e10; 1 drivers -LS_0x122b620_0_0 .concat8 [ 1 1 1 1], L_0x1229da0, L_0x122a3d0, L_0x122a8d0, L_0x122af80; -LS_0x122b620_0_4 .concat8 [ 1 1 1 1], L_0x122b180, L_0x122b240, L_0x122b3a0, L_0x122b850; -L_0x122b620 .concat8 [ 4 4 0 0], LS_0x122b620_0_0, LS_0x122b620_0_4; -LS_0x13535a0_0_0 .concat [ 1 1 1 1], L_0x122a050, L_0x122a770, o0x2b0ab3cae808, L_0x122add0; -LS_0x13535a0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cae838; -L_0x13535a0 .concat [ 4 4 0 0], LS_0x13535a0_0_0, LS_0x13535a0_0_4; -S_0x10068c0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1006640; +L_0x2d08bb0/d .functor NOT 1, L_0x2d131f0, C4<0>, C4<0>, C4<0>; +L_0x2d08bb0 .delay 1 (10000,10000,10000) L_0x2d08bb0/d; +L_0x2d08cc0/d .functor NOT 1, L_0x2d13350, C4<0>, C4<0>, C4<0>; +L_0x2d08cc0 .delay 1 (10000,10000,10000) L_0x2d08cc0/d; +L_0x2d09d10/d .functor XOR 1, L_0x2d131f0, L_0x2d13350, C4<0>, C4<0>; +L_0x2d09d10 .delay 1 (30000,30000,30000) L_0x2d09d10/d; +L_0x2ac6110b6f48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b6f90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d09dd0/d .functor OR 1, L_0x2ac6110b6f48, L_0x2ac6110b6f90, C4<0>, C4<0>; +L_0x2d09dd0 .delay 1 (30000,30000,30000) L_0x2d09dd0/d; +L_0x2ac6110b6fd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7020 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d0a4d0/d .functor OR 1, L_0x2ac6110b6fd8, L_0x2ac6110b7020, C4<0>, C4<0>; +L_0x2d0a4d0 .delay 1 (30000,30000,30000) L_0x2d0a4d0/d; +L_0x2d0a6d0/d .functor AND 1, L_0x2d131f0, L_0x2d13350, C4<1>, C4<1>; +L_0x2d0a6d0 .delay 1 (30000,30000,30000) L_0x2d0a6d0/d; +L_0x2ac6110b7068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b70b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d0a790/d .functor OR 1, L_0x2ac6110b7068, L_0x2ac6110b70b0, C4<0>, C4<0>; +L_0x2d0a790 .delay 1 (30000,30000,30000) L_0x2d0a790/d; +L_0x2d0a990/d .functor NAND 1, L_0x2d131f0, L_0x2d13350, C4<1>, C4<1>; +L_0x2d0a990 .delay 1 (20000,20000,20000) L_0x2d0a990/d; +L_0x2ac6110b70f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d0aaa0/d .functor OR 1, L_0x2ac6110b70f8, L_0x2ac6110b7140, C4<0>, C4<0>; +L_0x2d0aaa0 .delay 1 (30000,30000,30000) L_0x2d0aaa0/d; +L_0x2d0ac50/d .functor NOR 1, L_0x2d131f0, L_0x2d13350, C4<0>, C4<0>; +L_0x2d0ac50 .delay 1 (20000,20000,20000) L_0x2d0ac50/d; +L_0x2ac6110b7188 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b71d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d0af20/d .functor OR 1, L_0x2ac6110b7188, L_0x2ac6110b71d0, C4<0>, C4<0>; +L_0x2d0af20 .delay 1 (30000,30000,30000) L_0x2d0af20/d; +L_0x2d0b320/d .functor OR 1, L_0x2d131f0, L_0x2d13350, C4<0>, C4<0>; +L_0x2d0b320 .delay 1 (30000,30000,30000) L_0x2d0b320/d; +L_0x2ac6110b7218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7260 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d0b7c0/d .functor OR 1, L_0x2ac6110b7218, L_0x2ac6110b7260, C4<0>, C4<0>; +L_0x2d0b7c0 .delay 1 (30000,30000,30000) L_0x2d0b7c0/d; +L_0x2d130f0/d .functor NOT 1, L_0x2d0f350, C4<0>, C4<0>, C4<0>; +L_0x2d130f0 .delay 1 (10000,10000,10000) L_0x2d130f0/d; +v0x2adb240_0 .net "A", 0 0, L_0x2d131f0; 1 drivers +v0x2adb300_0 .net "A_", 0 0, L_0x2d08bb0; 1 drivers +v0x2adb3c0_0 .net "B", 0 0, L_0x2d13350; 1 drivers +v0x2adb490_0 .net "B_", 0 0, L_0x2d08cc0; 1 drivers +v0x2adb530_0 .net *"_s11", 0 0, L_0x2d09dd0; 1 drivers +v0x2adb620_0 .net/2s *"_s13", 0 0, L_0x2ac6110b6f48; 1 drivers +v0x2adb6e0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b6f90; 1 drivers +v0x2adb7c0_0 .net *"_s19", 0 0, L_0x2d0a4d0; 1 drivers +v0x2adb8a0_0 .net/2s *"_s21", 0 0, L_0x2ac6110b6fd8; 1 drivers +v0x2adba10_0 .net/2s *"_s23", 0 0, L_0x2ac6110b7020; 1 drivers +v0x2adbaf0_0 .net *"_s25", 0 0, L_0x2d0a6d0; 1 drivers +v0x2adbbd0_0 .net *"_s28", 0 0, L_0x2d0a790; 1 drivers +v0x2adbcb0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b7068; 1 drivers +v0x2adbd90_0 .net/2s *"_s32", 0 0, L_0x2ac6110b70b0; 1 drivers +v0x2adbe70_0 .net *"_s34", 0 0, L_0x2d0a990; 1 drivers +v0x2adbf50_0 .net *"_s37", 0 0, L_0x2d0aaa0; 1 drivers +v0x2adc030_0 .net/2s *"_s39", 0 0, L_0x2ac6110b70f8; 1 drivers +v0x2adc1e0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b7140; 1 drivers +v0x2adc280_0 .net *"_s43", 0 0, L_0x2d0ac50; 1 drivers +v0x2adc360_0 .net *"_s46", 0 0, L_0x2d0af20; 1 drivers +v0x2adc440_0 .net/2s *"_s48", 0 0, L_0x2ac6110b7188; 1 drivers +v0x2adc520_0 .net/2s *"_s50", 0 0, L_0x2ac6110b71d0; 1 drivers +v0x2adc600_0 .net *"_s52", 0 0, L_0x2d0b320; 1 drivers +v0x2adc6e0_0 .net *"_s56", 0 0, L_0x2d0b7c0; 1 drivers +v0x2adc7c0_0 .net/2s *"_s59", 0 0, L_0x2ac6110b7218; 1 drivers +v0x2adc8a0_0 .net/2s *"_s61", 0 0, L_0x2ac6110b7260; 1 drivers +v0x2adc980_0 .net *"_s8", 0 0, L_0x2d09d10; 1 drivers +v0x2adca60_0 .net "carryin", 0 0, L_0x2d13470; 1 drivers +v0x2adcb00_0 .net "carryout", 0 0, L_0x2d12d90; 1 drivers +v0x2adcba0_0 .net "carryouts", 7 0, L_0x2d0b430; 1 drivers +v0x2adccb0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2adcd70_0 .net "result", 0 0, L_0x2d0f350; 1 drivers +v0x2adce60_0 .net "results", 7 0, L_0x2d0b0f0; 1 drivers +v0x2adc140_0 .net "zero", 0 0, L_0x2d130f0; 1 drivers +LS_0x2d0b0f0_0_0 .concat8 [ 1 1 1 1], L_0x2d091e0, L_0x2d09810, L_0x2d09d10, L_0x2d0a4d0; +LS_0x2d0b0f0_0_4 .concat8 [ 1 1 1 1], L_0x2d0a6d0, L_0x2d0a990, L_0x2d0ac50, L_0x2d0b320; +L_0x2d0b0f0 .concat8 [ 4 4 0 0], LS_0x2d0b0f0_0_0, LS_0x2d0b0f0_0_4; +LS_0x2d0b430_0_0 .concat8 [ 1 1 1 1], L_0x2d09490, L_0x2d09bb0, L_0x2d09dd0, L_0x2d0a320; +LS_0x2d0b430_0_4 .concat8 [ 1 1 1 1], L_0x2d0a790, L_0x2d0aaa0, L_0x2d0af20, L_0x2d0b7c0; +L_0x2d0b430 .concat8 [ 4 4 0 0], LS_0x2d0b430_0_0, LS_0x2d0b430_0_4; +S_0x2accec0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2accc40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x122a050/d .functor OR 1, L_0x1229b30, L_0x1229ef0, C4<0>, C4<0>; -L_0x122a050 .delay 1 (30000,30000,30000) L_0x122a050/d; -v0x10076c0_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers -v0x1007780_0 .net "b", 0 0, L_0x1233070; alias, 1 drivers -v0x1007850_0 .net "c1", 0 0, L_0x1229b30; 1 drivers -v0x1007950_0 .net "c2", 0 0, L_0x1229ef0; 1 drivers -v0x1007a20_0 .net "carryin", 0 0, L_0x1233110; alias, 1 drivers -v0x1007b10_0 .net "carryout", 0 0, L_0x122a050; 1 drivers -v0x1007bb0_0 .net "s1", 0 0, L_0x1229a70; 1 drivers -v0x1007ca0_0 .net "sum", 0 0, L_0x1229da0; 1 drivers -S_0x1006b30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10068c0; +L_0x2d09490/d .functor OR 1, L_0x2d08f70, L_0x2d09330, C4<0>, C4<0>; +L_0x2d09490 .delay 1 (30000,30000,30000) L_0x2d09490/d; +v0x2acdcc0_0 .net "a", 0 0, L_0x2d131f0; alias, 1 drivers +v0x2acdd80_0 .net "b", 0 0, L_0x2d13350; alias, 1 drivers +v0x2acde50_0 .net "c1", 0 0, L_0x2d08f70; 1 drivers +v0x2acdf50_0 .net "c2", 0 0, L_0x2d09330; 1 drivers +v0x2ace020_0 .net "carryin", 0 0, L_0x2d13470; alias, 1 drivers +v0x2ace110_0 .net "carryout", 0 0, L_0x2d09490; 1 drivers +v0x2ace1b0_0 .net "s1", 0 0, L_0x2d08eb0; 1 drivers +v0x2ace2a0_0 .net "sum", 0 0, L_0x2d091e0; 1 drivers +S_0x2acd130 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2accec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1229a70/d .functor XOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; -L_0x1229a70 .delay 1 (30000,30000,30000) L_0x1229a70/d; -L_0x1229b30/d .functor AND 1, L_0x1232f10, L_0x1233070, C4<1>, C4<1>; -L_0x1229b30 .delay 1 (30000,30000,30000) L_0x1229b30/d; -v0x1006d90_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers -v0x1006e70_0 .net "b", 0 0, L_0x1233070; alias, 1 drivers -v0x1006f30_0 .net "carryout", 0 0, L_0x1229b30; alias, 1 drivers -v0x1006fd0_0 .net "sum", 0 0, L_0x1229a70; alias, 1 drivers -S_0x1007110 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10068c0; +L_0x2d08eb0/d .functor XOR 1, L_0x2d131f0, L_0x2d13350, C4<0>, C4<0>; +L_0x2d08eb0 .delay 1 (30000,30000,30000) L_0x2d08eb0/d; +L_0x2d08f70/d .functor AND 1, L_0x2d131f0, L_0x2d13350, C4<1>, C4<1>; +L_0x2d08f70 .delay 1 (30000,30000,30000) L_0x2d08f70/d; +v0x2acd390_0 .net "a", 0 0, L_0x2d131f0; alias, 1 drivers +v0x2acd470_0 .net "b", 0 0, L_0x2d13350; alias, 1 drivers +v0x2acd530_0 .net "carryout", 0 0, L_0x2d08f70; alias, 1 drivers +v0x2acd5d0_0 .net "sum", 0 0, L_0x2d08eb0; alias, 1 drivers +S_0x2acd710 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2accec0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1229da0/d .functor XOR 1, L_0x1229a70, L_0x1233110, C4<0>, C4<0>; -L_0x1229da0 .delay 1 (30000,30000,30000) L_0x1229da0/d; -L_0x1229ef0/d .functor AND 1, L_0x1229a70, L_0x1233110, C4<1>, C4<1>; -L_0x1229ef0 .delay 1 (30000,30000,30000) L_0x1229ef0/d; -v0x1007370_0 .net "a", 0 0, L_0x1229a70; alias, 1 drivers -v0x1007410_0 .net "b", 0 0, L_0x1233110; alias, 1 drivers -v0x10074b0_0 .net "carryout", 0 0, L_0x1229ef0; alias, 1 drivers -v0x1007550_0 .net "sum", 0 0, L_0x1229da0; alias, 1 drivers -S_0x1007d70 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1006640; +L_0x2d091e0/d .functor XOR 1, L_0x2d08eb0, L_0x2d13470, C4<0>, C4<0>; +L_0x2d091e0 .delay 1 (30000,30000,30000) L_0x2d091e0/d; +L_0x2d09330/d .functor AND 1, L_0x2d08eb0, L_0x2d13470, C4<1>, C4<1>; +L_0x2d09330 .delay 1 (30000,30000,30000) L_0x2d09330/d; +v0x2acd970_0 .net "a", 0 0, L_0x2d08eb0; alias, 1 drivers +v0x2acda10_0 .net "b", 0 0, L_0x2d13470; alias, 1 drivers +v0x2acdab0_0 .net "carryout", 0 0, L_0x2d09330; alias, 1 drivers +v0x2acdb50_0 .net "sum", 0 0, L_0x2d091e0; alias, 1 drivers +S_0x2ace370 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2accc40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x100d160_0 .net "ands", 7 0, L_0x1230b20; 1 drivers -v0x100d270_0 .net "in", 7 0, L_0x13535a0; alias, 1 drivers -v0x100d330_0 .net "out", 0 0, L_0x1232ab0; alias, 1 drivers -v0x100d400_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1007f90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1007d70; +v0x2ad3760_0 .net "ands", 7 0, L_0x2d10d90; 1 drivers +v0x2ad3870_0 .net "in", 7 0, L_0x2d0b430; alias, 1 drivers +v0x2ad3930_0 .net "out", 0 0, L_0x2d12d90; alias, 1 drivers +v0x2ad3a00_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2ace590 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2ace370; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x100a6c0_0 .net "A", 7 0, L_0x13535a0; alias, 1 drivers -v0x100a7c0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x100a880_0 .net *"_s0", 0 0, L_0x122f440; 1 drivers -v0x100a940_0 .net *"_s12", 0 0, L_0x122fdb0; 1 drivers -v0x100aa20_0 .net *"_s16", 0 0, L_0x1230110; 1 drivers -v0x100ab50_0 .net *"_s20", 0 0, L_0x1230420; 1 drivers -v0x100ac30_0 .net *"_s24", 0 0, L_0x1230810; 1 drivers -v0x100ad10_0 .net *"_s28", 0 0, L_0x12307a0; 1 drivers -v0x100adf0_0 .net *"_s4", 0 0, L_0x122f750; 1 drivers -v0x100af60_0 .net *"_s8", 0 0, L_0x122faa0; 1 drivers -v0x100b040_0 .net "out", 7 0, L_0x1230b20; alias, 1 drivers -L_0x122f500 .part L_0x13535a0, 0, 1; -L_0x122f660 .part v0x12010b0_0, 0, 1; -L_0x122f810 .part L_0x13535a0, 1, 1; -L_0x122fa00 .part v0x12010b0_0, 1, 1; -L_0x122fb60 .part L_0x13535a0, 2, 1; -L_0x122fcc0 .part v0x12010b0_0, 2, 1; -L_0x122fe70 .part L_0x13535a0, 3, 1; -L_0x122ffd0 .part v0x12010b0_0, 3, 1; -L_0x12301d0 .part L_0x13535a0, 4, 1; -L_0x1230330 .part v0x12010b0_0, 4, 1; -L_0x1230490 .part L_0x13535a0, 5, 1; -L_0x1230700 .part v0x12010b0_0, 5, 1; -L_0x12308d0 .part L_0x13535a0, 6, 1; -L_0x1230a30 .part v0x12010b0_0, 6, 1; -LS_0x1230b20_0_0 .concat8 [ 1 1 1 1], L_0x122f440, L_0x122f750, L_0x122faa0, L_0x122fdb0; -LS_0x1230b20_0_4 .concat8 [ 1 1 1 1], L_0x1230110, L_0x1230420, L_0x1230810, L_0x12307a0; -L_0x1230b20 .concat8 [ 4 4 0 0], LS_0x1230b20_0_0, LS_0x1230b20_0_4; -L_0x1230ee0 .part L_0x13535a0, 7, 1; -L_0x1231060 .part v0x12010b0_0, 7, 1; -S_0x10081f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x1008400 .param/l "i" 0 4 54, +C4<00>; -L_0x122f440/d .functor AND 1, L_0x122f500, L_0x122f660, C4<1>, C4<1>; -L_0x122f440 .delay 1 (30000,30000,30000) L_0x122f440/d; -v0x10084e0_0 .net *"_s0", 0 0, L_0x122f500; 1 drivers -v0x10085c0_0 .net *"_s1", 0 0, L_0x122f660; 1 drivers -S_0x10086a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x10088b0 .param/l "i" 0 4 54, +C4<01>; -L_0x122f750/d .functor AND 1, L_0x122f810, L_0x122fa00, C4<1>, C4<1>; -L_0x122f750 .delay 1 (30000,30000,30000) L_0x122f750/d; -v0x1008970_0 .net *"_s0", 0 0, L_0x122f810; 1 drivers -v0x1008a50_0 .net *"_s1", 0 0, L_0x122fa00; 1 drivers -S_0x1008b30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x1008d40 .param/l "i" 0 4 54, +C4<010>; -L_0x122faa0/d .functor AND 1, L_0x122fb60, L_0x122fcc0, C4<1>, C4<1>; -L_0x122faa0 .delay 1 (30000,30000,30000) L_0x122faa0/d; -v0x1008de0_0 .net *"_s0", 0 0, L_0x122fb60; 1 drivers -v0x1008ec0_0 .net *"_s1", 0 0, L_0x122fcc0; 1 drivers -S_0x1008fa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x10091b0 .param/l "i" 0 4 54, +C4<011>; -L_0x122fdb0/d .functor AND 1, L_0x122fe70, L_0x122ffd0, C4<1>, C4<1>; -L_0x122fdb0 .delay 1 (30000,30000,30000) L_0x122fdb0/d; -v0x1009270_0 .net *"_s0", 0 0, L_0x122fe70; 1 drivers -v0x1009350_0 .net *"_s1", 0 0, L_0x122ffd0; 1 drivers -S_0x1009430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x1009690 .param/l "i" 0 4 54, +C4<0100>; -L_0x1230110/d .functor AND 1, L_0x12301d0, L_0x1230330, C4<1>, C4<1>; -L_0x1230110 .delay 1 (30000,30000,30000) L_0x1230110/d; -v0x1009750_0 .net *"_s0", 0 0, L_0x12301d0; 1 drivers -v0x1009830_0 .net *"_s1", 0 0, L_0x1230330; 1 drivers -S_0x1009910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x1009b20 .param/l "i" 0 4 54, +C4<0101>; -L_0x1230420/d .functor AND 1, L_0x1230490, L_0x1230700, C4<1>, C4<1>; -L_0x1230420 .delay 1 (30000,30000,30000) L_0x1230420/d; -v0x1009be0_0 .net *"_s0", 0 0, L_0x1230490; 1 drivers -v0x1009cc0_0 .net *"_s1", 0 0, L_0x1230700; 1 drivers -S_0x1009da0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x1009fb0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1230810/d .functor AND 1, L_0x12308d0, L_0x1230a30, C4<1>, C4<1>; -L_0x1230810 .delay 1 (30000,30000,30000) L_0x1230810/d; -v0x100a070_0 .net *"_s0", 0 0, L_0x12308d0; 1 drivers -v0x100a150_0 .net *"_s1", 0 0, L_0x1230a30; 1 drivers -S_0x100a230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1007f90; - .timescale -9 -12; -P_0x100a440 .param/l "i" 0 4 54, +C4<0111>; -L_0x12307a0/d .functor AND 1, L_0x1230ee0, L_0x1231060, C4<1>, C4<1>; -L_0x12307a0 .delay 1 (30000,30000,30000) L_0x12307a0/d; -v0x100a500_0 .net *"_s0", 0 0, L_0x1230ee0; 1 drivers -v0x100a5e0_0 .net *"_s1", 0 0, L_0x1231060; 1 drivers -S_0x100b1a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1007d70; +v0x2ad0cc0_0 .net "A", 7 0, L_0x2d0b430; alias, 1 drivers +v0x2ad0dc0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ad0e80_0 .net *"_s0", 0 0, L_0x2d0f6b0; 1 drivers +v0x2ad0f40_0 .net *"_s12", 0 0, L_0x2d10020; 1 drivers +v0x2ad1020_0 .net *"_s16", 0 0, L_0x2d10380; 1 drivers +v0x2ad1150_0 .net *"_s20", 0 0, L_0x2d10750; 1 drivers +v0x2ad1230_0 .net *"_s24", 0 0, L_0x2d10a80; 1 drivers +v0x2ad1310_0 .net *"_s28", 0 0, L_0x2d10a10; 1 drivers +v0x2ad13f0_0 .net *"_s4", 0 0, L_0x2d0fa00; 1 drivers +v0x2ad1560_0 .net *"_s8", 0 0, L_0x2d0fd10; 1 drivers +v0x2ad1640_0 .net "out", 7 0, L_0x2d10d90; alias, 1 drivers +L_0x2d0f770 .part L_0x2d0b430, 0, 1; +L_0x2d0f960 .part v0x2cdd2e0_0, 0, 1; +L_0x2d0fac0 .part L_0x2d0b430, 1, 1; +L_0x2d0fc20 .part v0x2cdd2e0_0, 1, 1; +L_0x2d0fdd0 .part L_0x2d0b430, 2, 1; +L_0x2d0ff30 .part v0x2cdd2e0_0, 2, 1; +L_0x2d100e0 .part L_0x2d0b430, 3, 1; +L_0x2d10240 .part v0x2cdd2e0_0, 3, 1; +L_0x2d10440 .part L_0x2d0b430, 4, 1; +L_0x2d106b0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d107c0 .part L_0x2d0b430, 5, 1; +L_0x2d10920 .part v0x2cdd2e0_0, 5, 1; +L_0x2d10b40 .part L_0x2d0b430, 6, 1; +L_0x2d10ca0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d10d90_0_0 .concat8 [ 1 1 1 1], L_0x2d0f6b0, L_0x2d0fa00, L_0x2d0fd10, L_0x2d10020; +LS_0x2d10d90_0_4 .concat8 [ 1 1 1 1], L_0x2d10380, L_0x2d10750, L_0x2d10a80, L_0x2d10a10; +L_0x2d10d90 .concat8 [ 4 4 0 0], LS_0x2d10d90_0_0, LS_0x2d10d90_0_4; +L_0x2d11150 .part L_0x2d0b430, 7, 1; +L_0x2d11340 .part v0x2cdd2e0_0, 7, 1; +S_0x2ace7f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2acea00 .param/l "i" 0 4 54, +C4<00>; +L_0x2d0f6b0/d .functor AND 1, L_0x2d0f770, L_0x2d0f960, C4<1>, C4<1>; +L_0x2d0f6b0 .delay 1 (30000,30000,30000) L_0x2d0f6b0/d; +v0x2aceae0_0 .net *"_s0", 0 0, L_0x2d0f770; 1 drivers +v0x2acebc0_0 .net *"_s1", 0 0, L_0x2d0f960; 1 drivers +S_0x2aceca0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2aceeb0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d0fa00/d .functor AND 1, L_0x2d0fac0, L_0x2d0fc20, C4<1>, C4<1>; +L_0x2d0fa00 .delay 1 (30000,30000,30000) L_0x2d0fa00/d; +v0x2acef70_0 .net *"_s0", 0 0, L_0x2d0fac0; 1 drivers +v0x2acf050_0 .net *"_s1", 0 0, L_0x2d0fc20; 1 drivers +S_0x2acf130 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2acf340 .param/l "i" 0 4 54, +C4<010>; +L_0x2d0fd10/d .functor AND 1, L_0x2d0fdd0, L_0x2d0ff30, C4<1>, C4<1>; +L_0x2d0fd10 .delay 1 (30000,30000,30000) L_0x2d0fd10/d; +v0x2acf3e0_0 .net *"_s0", 0 0, L_0x2d0fdd0; 1 drivers +v0x2acf4c0_0 .net *"_s1", 0 0, L_0x2d0ff30; 1 drivers +S_0x2acf5a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2acf7b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d10020/d .functor AND 1, L_0x2d100e0, L_0x2d10240, C4<1>, C4<1>; +L_0x2d10020 .delay 1 (30000,30000,30000) L_0x2d10020/d; +v0x2acf870_0 .net *"_s0", 0 0, L_0x2d100e0; 1 drivers +v0x2acf950_0 .net *"_s1", 0 0, L_0x2d10240; 1 drivers +S_0x2acfa30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2acfc90 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d10380/d .functor AND 1, L_0x2d10440, L_0x2d106b0, C4<1>, C4<1>; +L_0x2d10380 .delay 1 (30000,30000,30000) L_0x2d10380/d; +v0x2acfd50_0 .net *"_s0", 0 0, L_0x2d10440; 1 drivers +v0x2acfe30_0 .net *"_s1", 0 0, L_0x2d106b0; 1 drivers +S_0x2acff10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2ad0120 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d10750/d .functor AND 1, L_0x2d107c0, L_0x2d10920, C4<1>, C4<1>; +L_0x2d10750 .delay 1 (30000,30000,30000) L_0x2d10750/d; +v0x2ad01e0_0 .net *"_s0", 0 0, L_0x2d107c0; 1 drivers +v0x2ad02c0_0 .net *"_s1", 0 0, L_0x2d10920; 1 drivers +S_0x2ad03a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2ad05b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d10a80/d .functor AND 1, L_0x2d10b40, L_0x2d10ca0, C4<1>, C4<1>; +L_0x2d10a80 .delay 1 (30000,30000,30000) L_0x2d10a80/d; +v0x2ad0670_0 .net *"_s0", 0 0, L_0x2d10b40; 1 drivers +v0x2ad0750_0 .net *"_s1", 0 0, L_0x2d10ca0; 1 drivers +S_0x2ad0830 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2ace590; + .timescale -9 -12; +P_0x2ad0a40 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d10a10/d .functor AND 1, L_0x2d11150, L_0x2d11340, C4<1>, C4<1>; +L_0x2d10a10 .delay 1 (30000,30000,30000) L_0x2d10a10/d; +v0x2ad0b00_0 .net *"_s0", 0 0, L_0x2d11150; 1 drivers +v0x2ad0be0_0 .net *"_s1", 0 0, L_0x2d11340; 1 drivers +S_0x2ad17a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2ace370; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1232ab0/d .functor OR 1, L_0x1232b70, L_0x1232d20, C4<0>, C4<0>; -L_0x1232ab0 .delay 1 (30000,30000,30000) L_0x1232ab0/d; -v0x100ccf0_0 .net *"_s10", 0 0, L_0x1232b70; 1 drivers -v0x100cdd0_0 .net *"_s12", 0 0, L_0x1232d20; 1 drivers -v0x100ceb0_0 .net "in", 7 0, L_0x1230b20; alias, 1 drivers -v0x100cf80_0 .net "ors", 1 0, L_0x12328d0; 1 drivers -v0x100d040_0 .net "out", 0 0, L_0x1232ab0; alias, 1 drivers -L_0x1231ca0 .part L_0x1230b20, 0, 4; -L_0x12328d0 .concat8 [ 1 1 0 0], L_0x1231990, L_0x12325c0; -L_0x1232a10 .part L_0x1230b20, 4, 4; -L_0x1232b70 .part L_0x12328d0, 0, 1; -L_0x1232d20 .part L_0x12328d0, 1, 1; -S_0x100b360 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x100b1a0; +L_0x2d12d90/d .functor OR 1, L_0x2d12e50, L_0x2d13000, C4<0>, C4<0>; +L_0x2d12d90 .delay 1 (30000,30000,30000) L_0x2d12d90/d; +v0x2ad32f0_0 .net *"_s10", 0 0, L_0x2d12e50; 1 drivers +v0x2ad33d0_0 .net *"_s12", 0 0, L_0x2d13000; 1 drivers +v0x2ad34b0_0 .net "in", 7 0, L_0x2d10d90; alias, 1 drivers +v0x2ad3580_0 .net "ors", 1 0, L_0x2d12bb0; 1 drivers +v0x2ad3640_0 .net "out", 0 0, L_0x2d12d90; alias, 1 drivers +L_0x2d11f80 .part L_0x2d10d90, 0, 4; +L_0x2d12bb0 .concat8 [ 1 1 0 0], L_0x2d11c70, L_0x2d128a0; +L_0x2d12cf0 .part L_0x2d10d90, 4, 4; +L_0x2d12e50 .part L_0x2d12bb0, 0, 1; +L_0x2d13000 .part L_0x2d12bb0, 1, 1; +S_0x2ad1960 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ad17a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1231150/d .functor OR 1, L_0x1231210, L_0x1231370, C4<0>, C4<0>; -L_0x1231150 .delay 1 (30000,30000,30000) L_0x1231150/d; -L_0x12315a0/d .functor OR 1, L_0x12316b0, L_0x1231810, C4<0>, C4<0>; -L_0x12315a0 .delay 1 (30000,30000,30000) L_0x12315a0/d; -L_0x1231990/d .functor OR 1, L_0x1231a00, L_0x1231bb0, C4<0>, C4<0>; -L_0x1231990 .delay 1 (30000,30000,30000) L_0x1231990/d; -v0x100b5b0_0 .net *"_s0", 0 0, L_0x1231150; 1 drivers -v0x100b6b0_0 .net *"_s10", 0 0, L_0x12316b0; 1 drivers -v0x100b790_0 .net *"_s12", 0 0, L_0x1231810; 1 drivers -v0x100b850_0 .net *"_s14", 0 0, L_0x1231a00; 1 drivers -v0x100b930_0 .net *"_s16", 0 0, L_0x1231bb0; 1 drivers -v0x100ba60_0 .net *"_s3", 0 0, L_0x1231210; 1 drivers -v0x100bb40_0 .net *"_s5", 0 0, L_0x1231370; 1 drivers -v0x100bc20_0 .net *"_s6", 0 0, L_0x12315a0; 1 drivers -v0x100bd00_0 .net "in", 3 0, L_0x1231ca0; 1 drivers -v0x100be70_0 .net "ors", 1 0, L_0x12314b0; 1 drivers -v0x100bf50_0 .net "out", 0 0, L_0x1231990; 1 drivers -L_0x1231210 .part L_0x1231ca0, 0, 1; -L_0x1231370 .part L_0x1231ca0, 1, 1; -L_0x12314b0 .concat8 [ 1 1 0 0], L_0x1231150, L_0x12315a0; -L_0x12316b0 .part L_0x1231ca0, 2, 1; -L_0x1231810 .part L_0x1231ca0, 3, 1; -L_0x1231a00 .part L_0x12314b0, 0, 1; -L_0x1231bb0 .part L_0x12314b0, 1, 1; -S_0x100c070 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x100b1a0; +L_0x2d11430/d .functor OR 1, L_0x2d114f0, L_0x2d11650, C4<0>, C4<0>; +L_0x2d11430 .delay 1 (30000,30000,30000) L_0x2d11430/d; +L_0x2d11880/d .functor OR 1, L_0x2d11990, L_0x2d11af0, C4<0>, C4<0>; +L_0x2d11880 .delay 1 (30000,30000,30000) L_0x2d11880/d; +L_0x2d11c70/d .functor OR 1, L_0x2d11ce0, L_0x2d11e90, C4<0>, C4<0>; +L_0x2d11c70 .delay 1 (30000,30000,30000) L_0x2d11c70/d; +v0x2ad1bb0_0 .net *"_s0", 0 0, L_0x2d11430; 1 drivers +v0x2ad1cb0_0 .net *"_s10", 0 0, L_0x2d11990; 1 drivers +v0x2ad1d90_0 .net *"_s12", 0 0, L_0x2d11af0; 1 drivers +v0x2ad1e50_0 .net *"_s14", 0 0, L_0x2d11ce0; 1 drivers +v0x2ad1f30_0 .net *"_s16", 0 0, L_0x2d11e90; 1 drivers +v0x2ad2060_0 .net *"_s3", 0 0, L_0x2d114f0; 1 drivers +v0x2ad2140_0 .net *"_s5", 0 0, L_0x2d11650; 1 drivers +v0x2ad2220_0 .net *"_s6", 0 0, L_0x2d11880; 1 drivers +v0x2ad2300_0 .net "in", 3 0, L_0x2d11f80; 1 drivers +v0x2ad2470_0 .net "ors", 1 0, L_0x2d11790; 1 drivers +v0x2ad2550_0 .net "out", 0 0, L_0x2d11c70; 1 drivers +L_0x2d114f0 .part L_0x2d11f80, 0, 1; +L_0x2d11650 .part L_0x2d11f80, 1, 1; +L_0x2d11790 .concat8 [ 1 1 0 0], L_0x2d11430, L_0x2d11880; +L_0x2d11990 .part L_0x2d11f80, 2, 1; +L_0x2d11af0 .part L_0x2d11f80, 3, 1; +L_0x2d11ce0 .part L_0x2d11790, 0, 1; +L_0x2d11e90 .part L_0x2d11790, 1, 1; +S_0x2ad2670 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ad17a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1231dd0/d .functor OR 1, L_0x1231e40, L_0x1231fa0, C4<0>, C4<0>; -L_0x1231dd0 .delay 1 (30000,30000,30000) L_0x1231dd0/d; -L_0x12321d0/d .functor OR 1, L_0x12322e0, L_0x1232440, C4<0>, C4<0>; -L_0x12321d0 .delay 1 (30000,30000,30000) L_0x12321d0/d; -L_0x12325c0/d .functor OR 1, L_0x1232630, L_0x12327e0, C4<0>, C4<0>; -L_0x12325c0 .delay 1 (30000,30000,30000) L_0x12325c0/d; -v0x100c230_0 .net *"_s0", 0 0, L_0x1231dd0; 1 drivers -v0x100c330_0 .net *"_s10", 0 0, L_0x12322e0; 1 drivers -v0x100c410_0 .net *"_s12", 0 0, L_0x1232440; 1 drivers -v0x100c4d0_0 .net *"_s14", 0 0, L_0x1232630; 1 drivers -v0x100c5b0_0 .net *"_s16", 0 0, L_0x12327e0; 1 drivers -v0x100c6e0_0 .net *"_s3", 0 0, L_0x1231e40; 1 drivers -v0x100c7c0_0 .net *"_s5", 0 0, L_0x1231fa0; 1 drivers -v0x100c8a0_0 .net *"_s6", 0 0, L_0x12321d0; 1 drivers -v0x100c980_0 .net "in", 3 0, L_0x1232a10; 1 drivers -v0x100caf0_0 .net "ors", 1 0, L_0x12320e0; 1 drivers -v0x100cbd0_0 .net "out", 0 0, L_0x12325c0; 1 drivers -L_0x1231e40 .part L_0x1232a10, 0, 1; -L_0x1231fa0 .part L_0x1232a10, 1, 1; -L_0x12320e0 .concat8 [ 1 1 0 0], L_0x1231dd0, L_0x12321d0; -L_0x12322e0 .part L_0x1232a10, 2, 1; -L_0x1232440 .part L_0x1232a10, 3, 1; -L_0x1232630 .part L_0x12320e0, 0, 1; -L_0x12327e0 .part L_0x12320e0, 1, 1; -S_0x100d4e0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1006640; +L_0x2d120b0/d .functor OR 1, L_0x2d12120, L_0x2d12280, C4<0>, C4<0>; +L_0x2d120b0 .delay 1 (30000,30000,30000) L_0x2d120b0/d; +L_0x2d124b0/d .functor OR 1, L_0x2d125c0, L_0x2d12720, C4<0>, C4<0>; +L_0x2d124b0 .delay 1 (30000,30000,30000) L_0x2d124b0/d; +L_0x2d128a0/d .functor OR 1, L_0x2d12910, L_0x2d12ac0, C4<0>, C4<0>; +L_0x2d128a0 .delay 1 (30000,30000,30000) L_0x2d128a0/d; +v0x2ad2830_0 .net *"_s0", 0 0, L_0x2d120b0; 1 drivers +v0x2ad2930_0 .net *"_s10", 0 0, L_0x2d125c0; 1 drivers +v0x2ad2a10_0 .net *"_s12", 0 0, L_0x2d12720; 1 drivers +v0x2ad2ad0_0 .net *"_s14", 0 0, L_0x2d12910; 1 drivers +v0x2ad2bb0_0 .net *"_s16", 0 0, L_0x2d12ac0; 1 drivers +v0x2ad2ce0_0 .net *"_s3", 0 0, L_0x2d12120; 1 drivers +v0x2ad2dc0_0 .net *"_s5", 0 0, L_0x2d12280; 1 drivers +v0x2ad2ea0_0 .net *"_s6", 0 0, L_0x2d124b0; 1 drivers +v0x2ad2f80_0 .net "in", 3 0, L_0x2d12cf0; 1 drivers +v0x2ad30f0_0 .net "ors", 1 0, L_0x2d123c0; 1 drivers +v0x2ad31d0_0 .net "out", 0 0, L_0x2d128a0; 1 drivers +L_0x2d12120 .part L_0x2d12cf0, 0, 1; +L_0x2d12280 .part L_0x2d12cf0, 1, 1; +L_0x2d123c0 .concat8 [ 1 1 0 0], L_0x2d120b0, L_0x2d124b0; +L_0x2d125c0 .part L_0x2d12cf0, 2, 1; +L_0x2d12720 .part L_0x2d12cf0, 3, 1; +L_0x2d12910 .part L_0x2d123c0, 0, 1; +L_0x2d12ac0 .part L_0x2d123c0, 1, 1; +S_0x2ad3ae0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2accc40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1012910_0 .net "ands", 7 0, L_0x122d0e0; 1 drivers -v0x1012a20_0 .net "in", 7 0, L_0x122b620; alias, 1 drivers -v0x1012ae0_0 .net "out", 0 0, L_0x122f0e0; alias, 1 drivers -v0x1012bb0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x100d730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x100d4e0; +v0x2ad8f10_0 .net "ands", 7 0, L_0x2d0d300; 1 drivers +v0x2ad8fd0_0 .net "in", 7 0, L_0x2d0b0f0; alias, 1 drivers +v0x2ad9070_0 .net "out", 0 0, L_0x2d0f350; alias, 1 drivers +v0x2ad9110_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2ad3d30 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2ad3ae0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x100fe70_0 .net "A", 7 0, L_0x122b620; alias, 1 drivers -v0x100ff70_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1010030_0 .net *"_s0", 0 0, L_0x122b9b0; 1 drivers -v0x10100f0_0 .net *"_s12", 0 0, L_0x122c370; 1 drivers -v0x10101d0_0 .net *"_s16", 0 0, L_0x122c6d0; 1 drivers -v0x1010300_0 .net *"_s20", 0 0, L_0x122caa0; 1 drivers -v0x10103e0_0 .net *"_s24", 0 0, L_0x122cdd0; 1 drivers -v0x10104c0_0 .net *"_s28", 0 0, L_0x122cd60; 1 drivers -v0x10105a0_0 .net *"_s4", 0 0, L_0x122bd50; 1 drivers -v0x1010710_0 .net *"_s8", 0 0, L_0x122c060; 1 drivers -v0x10107f0_0 .net "out", 7 0, L_0x122d0e0; alias, 1 drivers -L_0x122bac0 .part L_0x122b620, 0, 1; -L_0x122bcb0 .part v0x12010b0_0, 0, 1; -L_0x122be10 .part L_0x122b620, 1, 1; -L_0x122bf70 .part v0x12010b0_0, 1, 1; -L_0x122c120 .part L_0x122b620, 2, 1; -L_0x122c280 .part v0x12010b0_0, 2, 1; -L_0x122c430 .part L_0x122b620, 3, 1; -L_0x122c590 .part v0x12010b0_0, 3, 1; -L_0x122c790 .part L_0x122b620, 4, 1; -L_0x122ca00 .part v0x12010b0_0, 4, 1; -L_0x122cb10 .part L_0x122b620, 5, 1; -L_0x122cc70 .part v0x12010b0_0, 5, 1; -L_0x122ce90 .part L_0x122b620, 6, 1; -L_0x122cff0 .part v0x12010b0_0, 6, 1; -LS_0x122d0e0_0_0 .concat8 [ 1 1 1 1], L_0x122b9b0, L_0x122bd50, L_0x122c060, L_0x122c370; -LS_0x122d0e0_0_4 .concat8 [ 1 1 1 1], L_0x122c6d0, L_0x122caa0, L_0x122cdd0, L_0x122cd60; -L_0x122d0e0 .concat8 [ 4 4 0 0], LS_0x122d0e0_0_0, LS_0x122d0e0_0_4; -L_0x122d4a0 .part L_0x122b620, 7, 1; -L_0x122d690 .part v0x12010b0_0, 7, 1; -S_0x100d970 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100db80 .param/l "i" 0 4 54, +C4<00>; -L_0x122b9b0/d .functor AND 1, L_0x122bac0, L_0x122bcb0, C4<1>, C4<1>; -L_0x122b9b0 .delay 1 (30000,30000,30000) L_0x122b9b0/d; -v0x100dc60_0 .net *"_s0", 0 0, L_0x122bac0; 1 drivers -v0x100dd40_0 .net *"_s1", 0 0, L_0x122bcb0; 1 drivers -S_0x100de20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100e030 .param/l "i" 0 4 54, +C4<01>; -L_0x122bd50/d .functor AND 1, L_0x122be10, L_0x122bf70, C4<1>, C4<1>; -L_0x122bd50 .delay 1 (30000,30000,30000) L_0x122bd50/d; -v0x100e0f0_0 .net *"_s0", 0 0, L_0x122be10; 1 drivers -v0x100e1d0_0 .net *"_s1", 0 0, L_0x122bf70; 1 drivers -S_0x100e2b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100e4f0 .param/l "i" 0 4 54, +C4<010>; -L_0x122c060/d .functor AND 1, L_0x122c120, L_0x122c280, C4<1>, C4<1>; -L_0x122c060 .delay 1 (30000,30000,30000) L_0x122c060/d; -v0x100e590_0 .net *"_s0", 0 0, L_0x122c120; 1 drivers -v0x100e670_0 .net *"_s1", 0 0, L_0x122c280; 1 drivers -S_0x100e750 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100e960 .param/l "i" 0 4 54, +C4<011>; -L_0x122c370/d .functor AND 1, L_0x122c430, L_0x122c590, C4<1>, C4<1>; -L_0x122c370 .delay 1 (30000,30000,30000) L_0x122c370/d; -v0x100ea20_0 .net *"_s0", 0 0, L_0x122c430; 1 drivers -v0x100eb00_0 .net *"_s1", 0 0, L_0x122c590; 1 drivers -S_0x100ebe0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100ee40 .param/l "i" 0 4 54, +C4<0100>; -L_0x122c6d0/d .functor AND 1, L_0x122c790, L_0x122ca00, C4<1>, C4<1>; -L_0x122c6d0 .delay 1 (30000,30000,30000) L_0x122c6d0/d; -v0x100ef00_0 .net *"_s0", 0 0, L_0x122c790; 1 drivers -v0x100efe0_0 .net *"_s1", 0 0, L_0x122ca00; 1 drivers -S_0x100f0c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100f2d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x122caa0/d .functor AND 1, L_0x122cb10, L_0x122cc70, C4<1>, C4<1>; -L_0x122caa0 .delay 1 (30000,30000,30000) L_0x122caa0/d; -v0x100f390_0 .net *"_s0", 0 0, L_0x122cb10; 1 drivers -v0x100f470_0 .net *"_s1", 0 0, L_0x122cc70; 1 drivers -S_0x100f550 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100f760 .param/l "i" 0 4 54, +C4<0110>; -L_0x122cdd0/d .functor AND 1, L_0x122ce90, L_0x122cff0, C4<1>, C4<1>; -L_0x122cdd0 .delay 1 (30000,30000,30000) L_0x122cdd0/d; -v0x100f820_0 .net *"_s0", 0 0, L_0x122ce90; 1 drivers -v0x100f900_0 .net *"_s1", 0 0, L_0x122cff0; 1 drivers -S_0x100f9e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x100d730; - .timescale -9 -12; -P_0x100fbf0 .param/l "i" 0 4 54, +C4<0111>; -L_0x122cd60/d .functor AND 1, L_0x122d4a0, L_0x122d690, C4<1>, C4<1>; -L_0x122cd60 .delay 1 (30000,30000,30000) L_0x122cd60/d; -v0x100fcb0_0 .net *"_s0", 0 0, L_0x122d4a0; 1 drivers -v0x100fd90_0 .net *"_s1", 0 0, L_0x122d690; 1 drivers -S_0x1010950 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x100d4e0; +v0x2ad6470_0 .net "A", 7 0, L_0x2d0b0f0; alias, 1 drivers +v0x2ad6570_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ad6630_0 .net *"_s0", 0 0, L_0x2d0b920; 1 drivers +v0x2ad66f0_0 .net *"_s12", 0 0, L_0x2d0c500; 1 drivers +v0x2ad67d0_0 .net *"_s16", 0 0, L_0x2d0c860; 1 drivers +v0x2ad6900_0 .net *"_s20", 0 0, L_0x2d0cc40; 1 drivers +v0x2ad69e0_0 .net *"_s24", 0 0, L_0x2d0cf70; 1 drivers +v0x2ad6ac0_0 .net *"_s28", 0 0, L_0x2d0cf00; 1 drivers +v0x2ad6ba0_0 .net *"_s4", 0 0, L_0x2d0bee0; 1 drivers +v0x2ad6d10_0 .net *"_s8", 0 0, L_0x2d0c1f0; 1 drivers +v0x2ad6df0_0 .net "out", 7 0, L_0x2d0d300; alias, 1 drivers +L_0x2cf5c60 .part L_0x2d0b0f0, 0, 1; +L_0x2d0be40 .part v0x2cdd2e0_0, 0, 1; +L_0x2d0bfa0 .part L_0x2d0b0f0, 1, 1; +L_0x2d0c100 .part v0x2cdd2e0_0, 1, 1; +L_0x2d0c2b0 .part L_0x2d0b0f0, 2, 1; +L_0x2d0c410 .part v0x2cdd2e0_0, 2, 1; +L_0x2d0c5c0 .part L_0x2d0b0f0, 3, 1; +L_0x2d0c720 .part v0x2cdd2e0_0, 3, 1; +L_0x2d0c920 .part L_0x2d0b0f0, 4, 1; +L_0x2cf5b50 .part v0x2cdd2e0_0, 4, 1; +L_0x2d0ccb0 .part L_0x2d0b0f0, 5, 1; +L_0x2d0ce10 .part v0x2cdd2e0_0, 5, 1; +L_0x2d0d030 .part L_0x2d0b0f0, 6, 1; +L_0x2d0d190 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d0d300_0_0 .concat8 [ 1 1 1 1], L_0x2d0b920, L_0x2d0bee0, L_0x2d0c1f0, L_0x2d0c500; +LS_0x2d0d300_0_4 .concat8 [ 1 1 1 1], L_0x2d0c860, L_0x2d0cc40, L_0x2d0cf70, L_0x2d0cf00; +L_0x2d0d300 .concat8 [ 4 4 0 0], LS_0x2d0d300_0_0, LS_0x2d0d300_0_4; +L_0x2d0d6c0 .part L_0x2d0b0f0, 7, 1; +L_0x2d0d8b0 .part v0x2cdd2e0_0, 7, 1; +S_0x2ad3f70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad4180 .param/l "i" 0 4 54, +C4<00>; +L_0x2d0b920/d .functor AND 1, L_0x2cf5c60, L_0x2d0be40, C4<1>, C4<1>; +L_0x2d0b920 .delay 1 (30000,30000,30000) L_0x2d0b920/d; +v0x2ad4260_0 .net *"_s0", 0 0, L_0x2cf5c60; 1 drivers +v0x2ad4340_0 .net *"_s1", 0 0, L_0x2d0be40; 1 drivers +S_0x2ad4420 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad4630 .param/l "i" 0 4 54, +C4<01>; +L_0x2d0bee0/d .functor AND 1, L_0x2d0bfa0, L_0x2d0c100, C4<1>, C4<1>; +L_0x2d0bee0 .delay 1 (30000,30000,30000) L_0x2d0bee0/d; +v0x2ad46f0_0 .net *"_s0", 0 0, L_0x2d0bfa0; 1 drivers +v0x2ad47d0_0 .net *"_s1", 0 0, L_0x2d0c100; 1 drivers +S_0x2ad48b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad4af0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d0c1f0/d .functor AND 1, L_0x2d0c2b0, L_0x2d0c410, C4<1>, C4<1>; +L_0x2d0c1f0 .delay 1 (30000,30000,30000) L_0x2d0c1f0/d; +v0x2ad4b90_0 .net *"_s0", 0 0, L_0x2d0c2b0; 1 drivers +v0x2ad4c70_0 .net *"_s1", 0 0, L_0x2d0c410; 1 drivers +S_0x2ad4d50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad4f60 .param/l "i" 0 4 54, +C4<011>; +L_0x2d0c500/d .functor AND 1, L_0x2d0c5c0, L_0x2d0c720, C4<1>, C4<1>; +L_0x2d0c500 .delay 1 (30000,30000,30000) L_0x2d0c500/d; +v0x2ad5020_0 .net *"_s0", 0 0, L_0x2d0c5c0; 1 drivers +v0x2ad5100_0 .net *"_s1", 0 0, L_0x2d0c720; 1 drivers +S_0x2ad51e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad5440 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d0c860/d .functor AND 1, L_0x2d0c920, L_0x2cf5b50, C4<1>, C4<1>; +L_0x2d0c860 .delay 1 (30000,30000,30000) L_0x2d0c860/d; +v0x2ad5500_0 .net *"_s0", 0 0, L_0x2d0c920; 1 drivers +v0x2ad55e0_0 .net *"_s1", 0 0, L_0x2cf5b50; 1 drivers +S_0x2ad56c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad58d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d0cc40/d .functor AND 1, L_0x2d0ccb0, L_0x2d0ce10, C4<1>, C4<1>; +L_0x2d0cc40 .delay 1 (30000,30000,30000) L_0x2d0cc40/d; +v0x2ad5990_0 .net *"_s0", 0 0, L_0x2d0ccb0; 1 drivers +v0x2ad5a70_0 .net *"_s1", 0 0, L_0x2d0ce10; 1 drivers +S_0x2ad5b50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad5d60 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d0cf70/d .functor AND 1, L_0x2d0d030, L_0x2d0d190, C4<1>, C4<1>; +L_0x2d0cf70 .delay 1 (30000,30000,30000) L_0x2d0cf70/d; +v0x2ad5e20_0 .net *"_s0", 0 0, L_0x2d0d030; 1 drivers +v0x2ad5f00_0 .net *"_s1", 0 0, L_0x2d0d190; 1 drivers +S_0x2ad5fe0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2ad3d30; + .timescale -9 -12; +P_0x2ad61f0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d0cf00/d .functor AND 1, L_0x2d0d6c0, L_0x2d0d8b0, C4<1>, C4<1>; +L_0x2d0cf00 .delay 1 (30000,30000,30000) L_0x2d0cf00/d; +v0x2ad62b0_0 .net *"_s0", 0 0, L_0x2d0d6c0; 1 drivers +v0x2ad6390_0 .net *"_s1", 0 0, L_0x2d0d8b0; 1 drivers +S_0x2ad6f50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2ad3ae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x122f0e0/d .functor OR 1, L_0x122f1a0, L_0x122f350, C4<0>, C4<0>; -L_0x122f0e0 .delay 1 (30000,30000,30000) L_0x122f0e0/d; -v0x10124a0_0 .net *"_s10", 0 0, L_0x122f1a0; 1 drivers -v0x1012580_0 .net *"_s12", 0 0, L_0x122f350; 1 drivers -v0x1012660_0 .net "in", 7 0, L_0x122d0e0; alias, 1 drivers -v0x1012730_0 .net "ors", 1 0, L_0x122ef00; 1 drivers -v0x10127f0_0 .net "out", 0 0, L_0x122f0e0; alias, 1 drivers -L_0x122e2d0 .part L_0x122d0e0, 0, 4; -L_0x122ef00 .concat8 [ 1 1 0 0], L_0x122dfc0, L_0x122ebf0; -L_0x122f040 .part L_0x122d0e0, 4, 4; -L_0x122f1a0 .part L_0x122ef00, 0, 1; -L_0x122f350 .part L_0x122ef00, 1, 1; -S_0x1010b10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1010950; +L_0x2d0f350/d .functor OR 1, L_0x2d0f410, L_0x2d0f5c0, C4<0>, C4<0>; +L_0x2d0f350 .delay 1 (30000,30000,30000) L_0x2d0f350/d; +v0x2ad8aa0_0 .net *"_s10", 0 0, L_0x2d0f410; 1 drivers +v0x2ad8b80_0 .net *"_s12", 0 0, L_0x2d0f5c0; 1 drivers +v0x2ad8c60_0 .net "in", 7 0, L_0x2d0d300; alias, 1 drivers +v0x2ad8d30_0 .net "ors", 1 0, L_0x2d0f170; 1 drivers +v0x2ad8df0_0 .net "out", 0 0, L_0x2d0f350; alias, 1 drivers +L_0x2d0e4f0 .part L_0x2d0d300, 0, 4; +L_0x2d0f170 .concat8 [ 1 1 0 0], L_0x2d0e1e0, L_0x2d0ee60; +L_0x2d0f2b0 .part L_0x2d0d300, 4, 4; +L_0x2d0f410 .part L_0x2d0f170, 0, 1; +L_0x2d0f5c0 .part L_0x2d0f170, 1, 1; +S_0x2ad7110 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ad6f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x122d780/d .functor OR 1, L_0x122d840, L_0x122d9a0, C4<0>, C4<0>; -L_0x122d780 .delay 1 (30000,30000,30000) L_0x122d780/d; -L_0x122dbd0/d .functor OR 1, L_0x122dce0, L_0x122de40, C4<0>, C4<0>; -L_0x122dbd0 .delay 1 (30000,30000,30000) L_0x122dbd0/d; -L_0x122dfc0/d .functor OR 1, L_0x122e030, L_0x122e1e0, C4<0>, C4<0>; -L_0x122dfc0 .delay 1 (30000,30000,30000) L_0x122dfc0/d; -v0x1010d60_0 .net *"_s0", 0 0, L_0x122d780; 1 drivers -v0x1010e60_0 .net *"_s10", 0 0, L_0x122dce0; 1 drivers -v0x1010f40_0 .net *"_s12", 0 0, L_0x122de40; 1 drivers -v0x1011000_0 .net *"_s14", 0 0, L_0x122e030; 1 drivers -v0x10110e0_0 .net *"_s16", 0 0, L_0x122e1e0; 1 drivers -v0x1011210_0 .net *"_s3", 0 0, L_0x122d840; 1 drivers -v0x10112f0_0 .net *"_s5", 0 0, L_0x122d9a0; 1 drivers -v0x10113d0_0 .net *"_s6", 0 0, L_0x122dbd0; 1 drivers -v0x10114b0_0 .net "in", 3 0, L_0x122e2d0; 1 drivers -v0x1011620_0 .net "ors", 1 0, L_0x122dae0; 1 drivers -v0x1011700_0 .net "out", 0 0, L_0x122dfc0; 1 drivers -L_0x122d840 .part L_0x122e2d0, 0, 1; -L_0x122d9a0 .part L_0x122e2d0, 1, 1; -L_0x122dae0 .concat8 [ 1 1 0 0], L_0x122d780, L_0x122dbd0; -L_0x122dce0 .part L_0x122e2d0, 2, 1; -L_0x122de40 .part L_0x122e2d0, 3, 1; -L_0x122e030 .part L_0x122dae0, 0, 1; -L_0x122e1e0 .part L_0x122dae0, 1, 1; -S_0x1011820 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1010950; +L_0x2d0d9a0/d .functor OR 1, L_0x2d0da60, L_0x2d0dbc0, C4<0>, C4<0>; +L_0x2d0d9a0 .delay 1 (30000,30000,30000) L_0x2d0d9a0/d; +L_0x2d0ddf0/d .functor OR 1, L_0x2d0df00, L_0x2d0e060, C4<0>, C4<0>; +L_0x2d0ddf0 .delay 1 (30000,30000,30000) L_0x2d0ddf0/d; +L_0x2d0e1e0/d .functor OR 1, L_0x2d0e250, L_0x2d0e400, C4<0>, C4<0>; +L_0x2d0e1e0 .delay 1 (30000,30000,30000) L_0x2d0e1e0/d; +v0x2ad7360_0 .net *"_s0", 0 0, L_0x2d0d9a0; 1 drivers +v0x2ad7460_0 .net *"_s10", 0 0, L_0x2d0df00; 1 drivers +v0x2ad7540_0 .net *"_s12", 0 0, L_0x2d0e060; 1 drivers +v0x2ad7600_0 .net *"_s14", 0 0, L_0x2d0e250; 1 drivers +v0x2ad76e0_0 .net *"_s16", 0 0, L_0x2d0e400; 1 drivers +v0x2ad7810_0 .net *"_s3", 0 0, L_0x2d0da60; 1 drivers +v0x2ad78f0_0 .net *"_s5", 0 0, L_0x2d0dbc0; 1 drivers +v0x2ad79d0_0 .net *"_s6", 0 0, L_0x2d0ddf0; 1 drivers +v0x2ad7ab0_0 .net "in", 3 0, L_0x2d0e4f0; 1 drivers +v0x2ad7c20_0 .net "ors", 1 0, L_0x2d0dd00; 1 drivers +v0x2ad7d00_0 .net "out", 0 0, L_0x2d0e1e0; 1 drivers +L_0x2d0da60 .part L_0x2d0e4f0, 0, 1; +L_0x2d0dbc0 .part L_0x2d0e4f0, 1, 1; +L_0x2d0dd00 .concat8 [ 1 1 0 0], L_0x2d0d9a0, L_0x2d0ddf0; +L_0x2d0df00 .part L_0x2d0e4f0, 2, 1; +L_0x2d0e060 .part L_0x2d0e4f0, 3, 1; +L_0x2d0e250 .part L_0x2d0dd00, 0, 1; +L_0x2d0e400 .part L_0x2d0dd00, 1, 1; +S_0x2ad7e20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ad6f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x122e400/d .functor OR 1, L_0x122e470, L_0x122e5d0, C4<0>, C4<0>; -L_0x122e400 .delay 1 (30000,30000,30000) L_0x122e400/d; -L_0x122e800/d .functor OR 1, L_0x122e910, L_0x122ea70, C4<0>, C4<0>; -L_0x122e800 .delay 1 (30000,30000,30000) L_0x122e800/d; -L_0x122ebf0/d .functor OR 1, L_0x122ec60, L_0x122ee10, C4<0>, C4<0>; -L_0x122ebf0 .delay 1 (30000,30000,30000) L_0x122ebf0/d; -v0x10119e0_0 .net *"_s0", 0 0, L_0x122e400; 1 drivers -v0x1011ae0_0 .net *"_s10", 0 0, L_0x122e910; 1 drivers -v0x1011bc0_0 .net *"_s12", 0 0, L_0x122ea70; 1 drivers -v0x1011c80_0 .net *"_s14", 0 0, L_0x122ec60; 1 drivers -v0x1011d60_0 .net *"_s16", 0 0, L_0x122ee10; 1 drivers -v0x1011e90_0 .net *"_s3", 0 0, L_0x122e470; 1 drivers -v0x1011f70_0 .net *"_s5", 0 0, L_0x122e5d0; 1 drivers -v0x1012050_0 .net *"_s6", 0 0, L_0x122e800; 1 drivers -v0x1012130_0 .net "in", 3 0, L_0x122f040; 1 drivers -v0x10122a0_0 .net "ors", 1 0, L_0x122e710; 1 drivers -v0x1012380_0 .net "out", 0 0, L_0x122ebf0; 1 drivers -L_0x122e470 .part L_0x122f040, 0, 1; -L_0x122e5d0 .part L_0x122f040, 1, 1; -L_0x122e710 .concat8 [ 1 1 0 0], L_0x122e400, L_0x122e800; -L_0x122e910 .part L_0x122f040, 2, 1; -L_0x122ea70 .part L_0x122f040, 3, 1; -L_0x122ec60 .part L_0x122e710, 0, 1; -L_0x122ee10 .part L_0x122e710, 1, 1; -S_0x1012c90 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1006640; +L_0x2d0e620/d .functor OR 1, L_0x2d0e6e0, L_0x2d0e840, C4<0>, C4<0>; +L_0x2d0e620 .delay 1 (30000,30000,30000) L_0x2d0e620/d; +L_0x2d0ea70/d .functor OR 1, L_0x2d0eb80, L_0x2d0ece0, C4<0>, C4<0>; +L_0x2d0ea70 .delay 1 (30000,30000,30000) L_0x2d0ea70/d; +L_0x2d0ee60/d .functor OR 1, L_0x2d0eed0, L_0x2d0f080, C4<0>, C4<0>; +L_0x2d0ee60 .delay 1 (30000,30000,30000) L_0x2d0ee60/d; +v0x2ad7fe0_0 .net *"_s0", 0 0, L_0x2d0e620; 1 drivers +v0x2ad80e0_0 .net *"_s10", 0 0, L_0x2d0eb80; 1 drivers +v0x2ad81c0_0 .net *"_s12", 0 0, L_0x2d0ece0; 1 drivers +v0x2ad8280_0 .net *"_s14", 0 0, L_0x2d0eed0; 1 drivers +v0x2ad8360_0 .net *"_s16", 0 0, L_0x2d0f080; 1 drivers +v0x2ad8490_0 .net *"_s3", 0 0, L_0x2d0e6e0; 1 drivers +v0x2ad8570_0 .net *"_s5", 0 0, L_0x2d0e840; 1 drivers +v0x2ad8650_0 .net *"_s6", 0 0, L_0x2d0ea70; 1 drivers +v0x2ad8730_0 .net "in", 3 0, L_0x2d0f2b0; 1 drivers +v0x2ad88a0_0 .net "ors", 1 0, L_0x2d0e980; 1 drivers +v0x2ad8980_0 .net "out", 0 0, L_0x2d0ee60; 1 drivers +L_0x2d0e6e0 .part L_0x2d0f2b0, 0, 1; +L_0x2d0e840 .part L_0x2d0f2b0, 1, 1; +L_0x2d0e980 .concat8 [ 1 1 0 0], L_0x2d0e620, L_0x2d0ea70; +L_0x2d0eb80 .part L_0x2d0f2b0, 2, 1; +L_0x2d0ece0 .part L_0x2d0f2b0, 3, 1; +L_0x2d0eed0 .part L_0x2d0e980, 0, 1; +L_0x2d0f080 .part L_0x2d0e980, 1, 1; +S_0x2ad91b0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2accc40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -2822,80 +2979,80 @@ S_0x1012c90 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1006640; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x122a990/d .functor XNOR 1, L_0x1232f10, L_0x1233070, C4<0>, C4<0>; -L_0x122a990 .delay 1 (20000,20000,20000) L_0x122a990/d; -L_0x122ac00/d .functor AND 1, L_0x1232f10, L_0x1229880, C4<1>, C4<1>; -L_0x122ac00 .delay 1 (30000,30000,30000) L_0x122ac00/d; -L_0x122ac70/d .functor AND 1, L_0x122a990, L_0x1233110, C4<1>, C4<1>; -L_0x122ac70 .delay 1 (30000,30000,30000) L_0x122ac70/d; -L_0x122add0/d .functor OR 1, L_0x122ac70, L_0x122ac00, C4<0>, C4<0>; -L_0x122add0 .delay 1 (30000,30000,30000) L_0x122add0/d; -v0x1012f40_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers -v0x1013030_0 .net "a_", 0 0, L_0x1229770; alias, 1 drivers -v0x10130f0_0 .net "b", 0 0, L_0x1233070; alias, 1 drivers -v0x10131e0_0 .net "b_", 0 0, L_0x1229880; alias, 1 drivers -v0x1013280_0 .net "carryin", 0 0, L_0x1233110; alias, 1 drivers -v0x10133c0_0 .net "eq", 0 0, L_0x122a990; 1 drivers -v0x1013480_0 .net "lt", 0 0, L_0x122ac00; 1 drivers -v0x1013540_0 .net "out", 0 0, L_0x122add0; 1 drivers -v0x1013600_0 .net "w0", 0 0, L_0x122ac70; 1 drivers -S_0x1013850 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1006640; +L_0x2d09f30/d .functor XNOR 1, L_0x2d131f0, L_0x2d13350, C4<0>, C4<0>; +L_0x2d09f30 .delay 1 (20000,20000,20000) L_0x2d09f30/d; +L_0x2d0a0b0/d .functor AND 1, L_0x2d131f0, L_0x2d08cc0, C4<1>, C4<1>; +L_0x2d0a0b0 .delay 1 (30000,30000,30000) L_0x2d0a0b0/d; +L_0x2d0a210/d .functor AND 1, L_0x2d09f30, L_0x2d13470, C4<1>, C4<1>; +L_0x2d0a210 .delay 1 (30000,30000,30000) L_0x2d0a210/d; +L_0x2d0a320/d .functor OR 1, L_0x2d0a210, L_0x2d0a0b0, C4<0>, C4<0>; +L_0x2d0a320 .delay 1 (30000,30000,30000) L_0x2d0a320/d; +v0x2ad9460_0 .net "a", 0 0, L_0x2d131f0; alias, 1 drivers +v0x2ad9550_0 .net "a_", 0 0, L_0x2d08bb0; alias, 1 drivers +v0x2ad95f0_0 .net "b", 0 0, L_0x2d13350; alias, 1 drivers +v0x2ad96e0_0 .net "b_", 0 0, L_0x2d08cc0; alias, 1 drivers +v0x2ad9780_0 .net "carryin", 0 0, L_0x2d13470; alias, 1 drivers +v0x2ad98c0_0 .net "eq", 0 0, L_0x2d09f30; 1 drivers +v0x2ad9980_0 .net "lt", 0 0, L_0x2d0a0b0; 1 drivers +v0x2ad9a40_0 .net "out", 0 0, L_0x2d0a320; 1 drivers +v0x2ad9b00_0 .net "w0", 0 0, L_0x2d0a210; 1 drivers +S_0x2ad9d50 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2accc40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x122a770/d .functor OR 1, L_0x122a270, L_0x1014ab0, C4<0>, C4<0>; -L_0x122a770 .delay 1 (30000,30000,30000) L_0x122a770/d; -v0x1014640_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers -v0x1014790_0 .net "b", 0 0, L_0x1229880; alias, 1 drivers -v0x1014850_0 .net "c1", 0 0, L_0x122a270; 1 drivers -v0x10148f0_0 .net "c2", 0 0, L_0x1014ab0; 1 drivers -v0x10149c0_0 .net "carryin", 0 0, L_0x1233110; alias, 1 drivers -v0x1014b40_0 .net "carryout", 0 0, L_0x122a770; 1 drivers -v0x1014be0_0 .net "s1", 0 0, L_0x122a1b0; 1 drivers -v0x1014c80_0 .net "sum", 0 0, L_0x122a3d0; 1 drivers -S_0x1013aa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1013850; +L_0x2d09bb0/d .functor OR 1, L_0x2d096b0, L_0x2adafb0, C4<0>, C4<0>; +L_0x2d09bb0 .delay 1 (30000,30000,30000) L_0x2d09bb0/d; +v0x2adab40_0 .net "a", 0 0, L_0x2d131f0; alias, 1 drivers +v0x2adac90_0 .net "b", 0 0, L_0x2d08cc0; alias, 1 drivers +v0x2adad50_0 .net "c1", 0 0, L_0x2d096b0; 1 drivers +v0x2adadf0_0 .net "c2", 0 0, L_0x2adafb0; 1 drivers +v0x2adaec0_0 .net "carryin", 0 0, L_0x2d13470; alias, 1 drivers +v0x2adb040_0 .net "carryout", 0 0, L_0x2d09bb0; 1 drivers +v0x2adb0e0_0 .net "s1", 0 0, L_0x2d095f0; 1 drivers +v0x2adb180_0 .net "sum", 0 0, L_0x2d09810; 1 drivers +S_0x2ad9fa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2ad9d50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x122a1b0/d .functor XOR 1, L_0x1232f10, L_0x1229880, C4<0>, C4<0>; -L_0x122a1b0 .delay 1 (30000,30000,30000) L_0x122a1b0/d; -L_0x122a270/d .functor AND 1, L_0x1232f10, L_0x1229880, C4<1>, C4<1>; -L_0x122a270 .delay 1 (30000,30000,30000) L_0x122a270/d; -v0x1013d00_0 .net "a", 0 0, L_0x1232f10; alias, 1 drivers -v0x1013dc0_0 .net "b", 0 0, L_0x1229880; alias, 1 drivers -v0x1013e80_0 .net "carryout", 0 0, L_0x122a270; alias, 1 drivers -v0x1013f20_0 .net "sum", 0 0, L_0x122a1b0; alias, 1 drivers -S_0x1014050 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1013850; +L_0x2d095f0/d .functor XOR 1, L_0x2d131f0, L_0x2d08cc0, C4<0>, C4<0>; +L_0x2d095f0 .delay 1 (30000,30000,30000) L_0x2d095f0/d; +L_0x2d096b0/d .functor AND 1, L_0x2d131f0, L_0x2d08cc0, C4<1>, C4<1>; +L_0x2d096b0 .delay 1 (30000,30000,30000) L_0x2d096b0/d; +v0x2ada200_0 .net "a", 0 0, L_0x2d131f0; alias, 1 drivers +v0x2ada2c0_0 .net "b", 0 0, L_0x2d08cc0; alias, 1 drivers +v0x2ada380_0 .net "carryout", 0 0, L_0x2d096b0; alias, 1 drivers +v0x2ada420_0 .net "sum", 0 0, L_0x2d095f0; alias, 1 drivers +S_0x2ada550 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2ad9d50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x122a3d0/d .functor XOR 1, L_0x122a1b0, L_0x1233110, C4<0>, C4<0>; -L_0x122a3d0 .delay 1 (30000,30000,30000) L_0x122a3d0/d; -L_0x1014ab0/d .functor AND 1, L_0x122a1b0, L_0x1233110, C4<1>, C4<1>; -L_0x1014ab0 .delay 1 (30000,30000,30000) L_0x1014ab0/d; -v0x10142b0_0 .net "a", 0 0, L_0x122a1b0; alias, 1 drivers -v0x1014380_0 .net "b", 0 0, L_0x1233110; alias, 1 drivers -v0x1014420_0 .net "carryout", 0 0, L_0x1014ab0; alias, 1 drivers -v0x10144f0_0 .net "sum", 0 0, L_0x122a3d0; alias, 1 drivers -S_0x10160a0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1006320; - .timescale -9 -12; -L_0x2b0ab3d05498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d054e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12293d0/d .functor OR 1, L_0x2b0ab3d05498, L_0x2b0ab3d054e0, C4<0>, C4<0>; -L_0x12293d0 .delay 1 (30000,30000,30000) L_0x12293d0/d; -v0x1016290_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05498; 1 drivers -v0x1016370_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d054e0; 1 drivers -S_0x1016450 .scope generate, "alu_slices[5]" "alu_slices[5]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1016660 .param/l "i" 0 3 41, +C4<0101>; -S_0x1016720 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1016450; +L_0x2d09810/d .functor XOR 1, L_0x2d095f0, L_0x2d13470, C4<0>, C4<0>; +L_0x2d09810 .delay 1 (30000,30000,30000) L_0x2d09810/d; +L_0x2adafb0/d .functor AND 1, L_0x2d095f0, L_0x2d13470, C4<1>, C4<1>; +L_0x2adafb0 .delay 1 (30000,30000,30000) L_0x2adafb0/d; +v0x2ada7b0_0 .net "a", 0 0, L_0x2d095f0; alias, 1 drivers +v0x2ada880_0 .net "b", 0 0, L_0x2d13470; alias, 1 drivers +v0x2ada920_0 .net "carryout", 0 0, L_0x2adafb0; alias, 1 drivers +v0x2ada9f0_0 .net "sum", 0 0, L_0x2d09810; alias, 1 drivers +S_0x2add210 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2acc920; + .timescale -9 -12; +L_0x2ac6110b72a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b72f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d00c00/d .functor OR 1, L_0x2ac6110b72a8, L_0x2ac6110b72f0, C4<0>, C4<0>; +L_0x2d00c00 .delay 1 (30000,30000,30000) L_0x2d00c00/d; +v0x2add400_0 .net/2u *"_s0", 0 0, L_0x2ac6110b72a8; 1 drivers +v0x2add4e0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b72f0; 1 drivers +S_0x2add5c0 .scope generate, "alu_slices[5]" "alu_slices[5]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2add7d0 .param/l "i" 0 3 39, +C4<0101>; +S_0x2add890 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2add5c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -2904,445 +3061,476 @@ S_0x1016720 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1016450; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1233200/d .functor NOT 1, L_0x123db40, C4<0>, C4<0>, C4<0>; -L_0x1233200 .delay 1 (10000,10000,10000) L_0x1233200/d; -L_0x1233470/d .functor NOT 1, L_0x123dd30, C4<0>, C4<0>, C4<0>; -L_0x1233470 .delay 1 (10000,10000,10000) L_0x1233470/d; -L_0x1234470/d .functor XOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; -L_0x1234470 .delay 1 (30000,30000,30000) L_0x1234470/d; -L_0x2b0ab3d05528 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05570 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1234b20/d .functor OR 1, L_0x2b0ab3d05528, L_0x2b0ab3d05570, C4<0>, C4<0>; -L_0x1234b20 .delay 1 (30000,30000,30000) L_0x1234b20/d; -L_0x1234d20/d .functor AND 1, L_0x123db40, L_0x123dd30, C4<1>, C4<1>; -L_0x1234d20 .delay 1 (30000,30000,30000) L_0x1234d20/d; -L_0x1234de0/d .functor NAND 1, L_0x123db40, L_0x123dd30, C4<1>, C4<1>; -L_0x1234de0 .delay 1 (20000,20000,20000) L_0x1234de0/d; -L_0x1234f40/d .functor XOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; -L_0x1234f40 .delay 1 (20000,20000,20000) L_0x1234f40/d; -L_0x12353f0/d .functor OR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; -L_0x12353f0 .delay 1 (30000,30000,30000) L_0x12353f0/d; -L_0x123da40/d .functor NOT 1, L_0x1238d60, C4<0>, C4<0>, C4<0>; -L_0x123da40 .delay 1 (10000,10000,10000) L_0x123da40/d; -v0x1024e60_0 .net "A", 0 0, L_0x123db40; 1 drivers -v0x1024f20_0 .net "A_", 0 0, L_0x1233200; 1 drivers -v0x1024fe0_0 .net "B", 0 0, L_0x123dd30; 1 drivers -v0x10250b0_0 .net "B_", 0 0, L_0x1233470; 1 drivers -v0x1025150_0 .net *"_s12", 0 0, L_0x1234b20; 1 drivers -v0x1025240_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05528; 1 drivers -v0x1025300_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05570; 1 drivers -v0x10253e0_0 .net *"_s18", 0 0, L_0x1234d20; 1 drivers -v0x10254c0_0 .net *"_s20", 0 0, L_0x1234de0; 1 drivers -v0x1025630_0 .net *"_s22", 0 0, L_0x1234f40; 1 drivers -v0x1025710_0 .net *"_s24", 0 0, L_0x12353f0; 1 drivers -o0x2b0ab3cb0d58 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10257f0_0 name=_s30 -o0x2b0ab3cb0d88 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10258d0_0 name=_s32 -v0x10259b0_0 .net *"_s8", 0 0, L_0x1234470; 1 drivers -v0x1025a90_0 .net "carryin", 0 0, L_0x123ddd0; 1 drivers -v0x1025b30_0 .net "carryout", 0 0, L_0x123d6e0; 1 drivers -v0x1025bd0_0 .net "carryouts", 7 0, L_0x1353730; 1 drivers -v0x1025d80_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1025e20_0 .net "result", 0 0, L_0x1238d60; 1 drivers -v0x1025f10_0 .net "results", 7 0, L_0x12351c0; 1 drivers -v0x1026020_0 .net "zero", 0 0, L_0x123da40; 1 drivers -LS_0x12351c0_0_0 .concat8 [ 1 1 1 1], L_0x1233990, L_0x1233fc0, L_0x1234470, L_0x1234b20; -LS_0x12351c0_0_4 .concat8 [ 1 1 1 1], L_0x1234d20, L_0x1234de0, L_0x1234f40, L_0x12353f0; -L_0x12351c0 .concat8 [ 4 4 0 0], LS_0x12351c0_0_0, LS_0x12351c0_0_4; -LS_0x1353730_0_0 .concat [ 1 1 1 1], L_0x1233c40, L_0x1234310, o0x2b0ab3cb0d58, L_0x1234970; -LS_0x1353730_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb0d88; -L_0x1353730 .concat [ 4 4 0 0], LS_0x1353730_0_0, LS_0x1353730_0_4; -S_0x10169a0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1016720; +L_0x2d09170/d .functor NOT 1, L_0x2d1ea70, C4<0>, C4<0>, C4<0>; +L_0x2d09170 .delay 1 (10000,10000,10000) L_0x2d09170/d; +L_0x2d136c0/d .functor NOT 1, L_0x2d1eb10, C4<0>, C4<0>, C4<0>; +L_0x2d136c0 .delay 1 (10000,10000,10000) L_0x2d136c0/d; +L_0x2d14620/d .functor XOR 1, L_0x2d1ea70, L_0x2d1eb10, C4<0>, C4<0>; +L_0x2d14620 .delay 1 (30000,30000,30000) L_0x2d14620/d; +L_0x2ac6110b7338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7380 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d146e0/d .functor OR 1, L_0x2ac6110b7338, L_0x2ac6110b7380, C4<0>, C4<0>; +L_0x2d146e0 .delay 1 (30000,30000,30000) L_0x2d146e0/d; +L_0x2ac6110b73c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7410 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d14e80/d .functor OR 1, L_0x2ac6110b73c8, L_0x2ac6110b7410, C4<0>, C4<0>; +L_0x2d14e80 .delay 1 (30000,30000,30000) L_0x2d14e80/d; +L_0x2d15080/d .functor AND 1, L_0x2d1ea70, L_0x2d1eb10, C4<1>, C4<1>; +L_0x2d15080 .delay 1 (30000,30000,30000) L_0x2d15080/d; +L_0x2ac6110b7458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b74a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d15140/d .functor OR 1, L_0x2ac6110b7458, L_0x2ac6110b74a0, C4<0>, C4<0>; +L_0x2d15140 .delay 1 (30000,30000,30000) L_0x2d15140/d; +L_0x2d15340/d .functor NAND 1, L_0x2d1ea70, L_0x2d1eb10, C4<1>, C4<1>; +L_0x2d15340 .delay 1 (20000,20000,20000) L_0x2d15340/d; +L_0x2ac6110b74e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7530 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d15450/d .functor OR 1, L_0x2ac6110b74e8, L_0x2ac6110b7530, C4<0>, C4<0>; +L_0x2d15450 .delay 1 (30000,30000,30000) L_0x2d15450/d; +L_0x2d15600/d .functor NOR 1, L_0x2d1ea70, L_0x2d1eb10, C4<0>, C4<0>; +L_0x2d15600 .delay 1 (20000,20000,20000) L_0x2d15600/d; +L_0x2ac6110b7578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b75c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d158d0/d .functor OR 1, L_0x2ac6110b7578, L_0x2ac6110b75c0, C4<0>, C4<0>; +L_0x2d158d0 .delay 1 (30000,30000,30000) L_0x2d158d0/d; +L_0x2d15cd0/d .functor OR 1, L_0x2d1ea70, L_0x2d1eb10, C4<0>, C4<0>; +L_0x2d15cd0 .delay 1 (30000,30000,30000) L_0x2d15cd0/d; +L_0x2ac6110b7608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d16170/d .functor OR 1, L_0x2ac6110b7608, L_0x2ac6110b7650, C4<0>, C4<0>; +L_0x2d16170 .delay 1 (30000,30000,30000) L_0x2d16170/d; +L_0x2d1e810/d .functor NOT 1, L_0x2d19b30, C4<0>, C4<0>, C4<0>; +L_0x2d1e810 .delay 1 (10000,10000,10000) L_0x2d1e810/d; +v0x2aebfc0_0 .net "A", 0 0, L_0x2d1ea70; 1 drivers +v0x2aec080_0 .net "A_", 0 0, L_0x2d09170; 1 drivers +v0x2aec140_0 .net "B", 0 0, L_0x2d1eb10; 1 drivers +v0x2aec210_0 .net "B_", 0 0, L_0x2d136c0; 1 drivers +v0x2aec2b0_0 .net *"_s11", 0 0, L_0x2d146e0; 1 drivers +v0x2aec3a0_0 .net/2s *"_s13", 0 0, L_0x2ac6110b7338; 1 drivers +v0x2aec460_0 .net/2s *"_s15", 0 0, L_0x2ac6110b7380; 1 drivers +v0x2aec540_0 .net *"_s19", 0 0, L_0x2d14e80; 1 drivers +v0x2aec620_0 .net/2s *"_s21", 0 0, L_0x2ac6110b73c8; 1 drivers +v0x2aec790_0 .net/2s *"_s23", 0 0, L_0x2ac6110b7410; 1 drivers +v0x2aec870_0 .net *"_s25", 0 0, L_0x2d15080; 1 drivers +v0x2aec950_0 .net *"_s28", 0 0, L_0x2d15140; 1 drivers +v0x2aeca30_0 .net/2s *"_s30", 0 0, L_0x2ac6110b7458; 1 drivers +v0x2aecb10_0 .net/2s *"_s32", 0 0, L_0x2ac6110b74a0; 1 drivers +v0x2aecbf0_0 .net *"_s34", 0 0, L_0x2d15340; 1 drivers +v0x2aeccd0_0 .net *"_s37", 0 0, L_0x2d15450; 1 drivers +v0x2aecdb0_0 .net/2s *"_s39", 0 0, L_0x2ac6110b74e8; 1 drivers +v0x2aecf60_0 .net/2s *"_s41", 0 0, L_0x2ac6110b7530; 1 drivers +v0x2aed000_0 .net *"_s43", 0 0, L_0x2d15600; 1 drivers +v0x2aed0e0_0 .net *"_s46", 0 0, L_0x2d158d0; 1 drivers +v0x2aed1c0_0 .net/2s *"_s48", 0 0, L_0x2ac6110b7578; 1 drivers +v0x2aed2a0_0 .net/2s *"_s50", 0 0, L_0x2ac6110b75c0; 1 drivers +v0x2aed380_0 .net *"_s52", 0 0, L_0x2d15cd0; 1 drivers +v0x2aed460_0 .net *"_s56", 0 0, L_0x2d16170; 1 drivers +v0x2aed540_0 .net/2s *"_s59", 0 0, L_0x2ac6110b7608; 1 drivers +v0x2aed620_0 .net/2s *"_s61", 0 0, L_0x2ac6110b7650; 1 drivers +v0x2aed700_0 .net *"_s8", 0 0, L_0x2d14620; 1 drivers +v0x2aed7e0_0 .net "carryin", 0 0, L_0x2d1ebb0; 1 drivers +v0x2aed880_0 .net "carryout", 0 0, L_0x2d1e4b0; 1 drivers +v0x2aed920_0 .net "carryouts", 7 0, L_0x2d15de0; 1 drivers +v0x2aeda30_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2aedaf0_0 .net "result", 0 0, L_0x2d19b30; 1 drivers +v0x2aedbe0_0 .net "results", 7 0, L_0x2d15aa0; 1 drivers +v0x2aecec0_0 .net "zero", 0 0, L_0x2d1e810; 1 drivers +LS_0x2d15aa0_0_0 .concat8 [ 1 1 1 1], L_0x2d13af0, L_0x2d14170, L_0x2d14620, L_0x2d14e80; +LS_0x2d15aa0_0_4 .concat8 [ 1 1 1 1], L_0x2d15080, L_0x2d15340, L_0x2d15600, L_0x2d15cd0; +L_0x2d15aa0 .concat8 [ 4 4 0 0], LS_0x2d15aa0_0_0, LS_0x2d15aa0_0_4; +LS_0x2d15de0_0_0 .concat8 [ 1 1 1 1], L_0x2d13df0, L_0x2d144c0, L_0x2d146e0, L_0x2d14cd0; +LS_0x2d15de0_0_4 .concat8 [ 1 1 1 1], L_0x2d15140, L_0x2d15450, L_0x2d158d0, L_0x2d16170; +L_0x2d15de0 .concat8 [ 4 4 0 0], LS_0x2d15de0_0_0, LS_0x2d15de0_0_4; +S_0x2addb10 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2add890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1233c40/d .functor OR 1, L_0x1233720, L_0x1233ae0, C4<0>, C4<0>; -L_0x1233c40 .delay 1 (30000,30000,30000) L_0x1233c40/d; -v0x10177d0_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers -v0x1017890_0 .net "b", 0 0, L_0x123dd30; alias, 1 drivers -v0x1017960_0 .net "c1", 0 0, L_0x1233720; 1 drivers -v0x1017a60_0 .net "c2", 0 0, L_0x1233ae0; 1 drivers -v0x1017b30_0 .net "carryin", 0 0, L_0x123ddd0; alias, 1 drivers -v0x1017c20_0 .net "carryout", 0 0, L_0x1233c40; 1 drivers -v0x1017cc0_0 .net "s1", 0 0, L_0x1233660; 1 drivers -v0x1017db0_0 .net "sum", 0 0, L_0x1233990; 1 drivers -S_0x1016c10 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10169a0; +L_0x2d13df0/d .functor OR 1, L_0x2d13920, L_0x2d13ce0, C4<0>, C4<0>; +L_0x2d13df0 .delay 1 (30000,30000,30000) L_0x2d13df0/d; +v0x2ade940_0 .net "a", 0 0, L_0x2d1ea70; alias, 1 drivers +v0x2adea00_0 .net "b", 0 0, L_0x2d1eb10; alias, 1 drivers +v0x2adead0_0 .net "c1", 0 0, L_0x2d13920; 1 drivers +v0x2adebd0_0 .net "c2", 0 0, L_0x2d13ce0; 1 drivers +v0x2adeca0_0 .net "carryin", 0 0, L_0x2d1ebb0; alias, 1 drivers +v0x2aded90_0 .net "carryout", 0 0, L_0x2d13df0; 1 drivers +v0x2adee30_0 .net "s1", 0 0, L_0x2d138b0; 1 drivers +v0x2adef20_0 .net "sum", 0 0, L_0x2d13af0; 1 drivers +S_0x2addd80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2addb10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1233660/d .functor XOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; -L_0x1233660 .delay 1 (30000,30000,30000) L_0x1233660/d; -L_0x1233720/d .functor AND 1, L_0x123db40, L_0x123dd30, C4<1>, C4<1>; -L_0x1233720 .delay 1 (30000,30000,30000) L_0x1233720/d; -v0x1016e70_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers -v0x1016f50_0 .net "b", 0 0, L_0x123dd30; alias, 1 drivers -v0x1017010_0 .net "carryout", 0 0, L_0x1233720; alias, 1 drivers -v0x10170b0_0 .net "sum", 0 0, L_0x1233660; alias, 1 drivers -S_0x10171f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10169a0; +L_0x2d138b0/d .functor XOR 1, L_0x2d1ea70, L_0x2d1eb10, C4<0>, C4<0>; +L_0x2d138b0 .delay 1 (30000,30000,30000) L_0x2d138b0/d; +L_0x2d13920/d .functor AND 1, L_0x2d1ea70, L_0x2d1eb10, C4<1>, C4<1>; +L_0x2d13920 .delay 1 (30000,30000,30000) L_0x2d13920/d; +v0x2addfe0_0 .net "a", 0 0, L_0x2d1ea70; alias, 1 drivers +v0x2ade0c0_0 .net "b", 0 0, L_0x2d1eb10; alias, 1 drivers +v0x2ade180_0 .net "carryout", 0 0, L_0x2d13920; alias, 1 drivers +v0x2ade220_0 .net "sum", 0 0, L_0x2d138b0; alias, 1 drivers +S_0x2ade360 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2addb10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1233990/d .functor XOR 1, L_0x1233660, L_0x123ddd0, C4<0>, C4<0>; -L_0x1233990 .delay 1 (30000,30000,30000) L_0x1233990/d; -L_0x1233ae0/d .functor AND 1, L_0x1233660, L_0x123ddd0, C4<1>, C4<1>; -L_0x1233ae0 .delay 1 (30000,30000,30000) L_0x1233ae0/d; -v0x1017450_0 .net "a", 0 0, L_0x1233660; alias, 1 drivers -v0x10174f0_0 .net "b", 0 0, L_0x123ddd0; alias, 1 drivers -v0x1017590_0 .net "carryout", 0 0, L_0x1233ae0; alias, 1 drivers -v0x1017660_0 .net "sum", 0 0, L_0x1233990; alias, 1 drivers -S_0x1017e80 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1016720; +L_0x2d13af0/d .functor XOR 1, L_0x2d138b0, L_0x2d1ebb0, C4<0>, C4<0>; +L_0x2d13af0 .delay 1 (30000,30000,30000) L_0x2d13af0/d; +L_0x2d13ce0/d .functor AND 1, L_0x2d138b0, L_0x2d1ebb0, C4<1>, C4<1>; +L_0x2d13ce0 .delay 1 (30000,30000,30000) L_0x2d13ce0/d; +v0x2ade5c0_0 .net "a", 0 0, L_0x2d138b0; alias, 1 drivers +v0x2ade660_0 .net "b", 0 0, L_0x2d1ebb0; alias, 1 drivers +v0x2ade700_0 .net "carryout", 0 0, L_0x2d13ce0; alias, 1 drivers +v0x2ade7d0_0 .net "sum", 0 0, L_0x2d13af0; alias, 1 drivers +S_0x2adeff0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2add890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x101d270_0 .net "ands", 7 0, L_0x123a7a0; 1 drivers -v0x101d380_0 .net "in", 7 0, L_0x1353730; alias, 1 drivers -v0x101d440_0 .net "out", 0 0, L_0x123d6e0; alias, 1 drivers -v0x101d510_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10180a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1017e80; +v0x2ae43e0_0 .net "ands", 7 0, L_0x2d1b570; 1 drivers +v0x2ae44f0_0 .net "in", 7 0, L_0x2d15de0; alias, 1 drivers +v0x2ae45b0_0 .net "out", 0 0, L_0x2d1e4b0; alias, 1 drivers +v0x2ae4680_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2adf210 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2adeff0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x101a7d0_0 .net "A", 7 0, L_0x1353730; alias, 1 drivers -v0x101a8d0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x101a990_0 .net *"_s0", 0 0, L_0x12390c0; 1 drivers -v0x101aa50_0 .net *"_s12", 0 0, L_0x1239a30; 1 drivers -v0x101ab30_0 .net *"_s16", 0 0, L_0x1239d90; 1 drivers -v0x101ac60_0 .net *"_s20", 0 0, L_0x123a0a0; 1 drivers -v0x101ad40_0 .net *"_s24", 0 0, L_0x123a490; 1 drivers -v0x101ae20_0 .net *"_s28", 0 0, L_0x123a420; 1 drivers -v0x101af00_0 .net *"_s4", 0 0, L_0x12393d0; 1 drivers -v0x101b070_0 .net *"_s8", 0 0, L_0x1239720; 1 drivers -v0x101b150_0 .net "out", 7 0, L_0x123a7a0; alias, 1 drivers -L_0x1239180 .part L_0x1353730, 0, 1; -L_0x12392e0 .part v0x12010b0_0, 0, 1; -L_0x1239490 .part L_0x1353730, 1, 1; -L_0x1239680 .part v0x12010b0_0, 1, 1; -L_0x12397e0 .part L_0x1353730, 2, 1; -L_0x1239940 .part v0x12010b0_0, 2, 1; -L_0x1239af0 .part L_0x1353730, 3, 1; -L_0x1239c50 .part v0x12010b0_0, 3, 1; -L_0x1239e50 .part L_0x1353730, 4, 1; -L_0x1239fb0 .part v0x12010b0_0, 4, 1; -L_0x123a110 .part L_0x1353730, 5, 1; -L_0x123a380 .part v0x12010b0_0, 5, 1; -L_0x123a550 .part L_0x1353730, 6, 1; -L_0x123a6b0 .part v0x12010b0_0, 6, 1; -LS_0x123a7a0_0_0 .concat8 [ 1 1 1 1], L_0x12390c0, L_0x12393d0, L_0x1239720, L_0x1239a30; -LS_0x123a7a0_0_4 .concat8 [ 1 1 1 1], L_0x1239d90, L_0x123a0a0, L_0x123a490, L_0x123a420; -L_0x123a7a0 .concat8 [ 4 4 0 0], LS_0x123a7a0_0_0, LS_0x123a7a0_0_4; -L_0x123ab60 .part L_0x1353730, 7, 1; -L_0x123ad50 .part v0x12010b0_0, 7, 1; -S_0x1018300 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x1018510 .param/l "i" 0 4 54, +C4<00>; -L_0x12390c0/d .functor AND 1, L_0x1239180, L_0x12392e0, C4<1>, C4<1>; -L_0x12390c0 .delay 1 (30000,30000,30000) L_0x12390c0/d; -v0x10185f0_0 .net *"_s0", 0 0, L_0x1239180; 1 drivers -v0x10186d0_0 .net *"_s1", 0 0, L_0x12392e0; 1 drivers -S_0x10187b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x10189c0 .param/l "i" 0 4 54, +C4<01>; -L_0x12393d0/d .functor AND 1, L_0x1239490, L_0x1239680, C4<1>, C4<1>; -L_0x12393d0 .delay 1 (30000,30000,30000) L_0x12393d0/d; -v0x1018a80_0 .net *"_s0", 0 0, L_0x1239490; 1 drivers -v0x1018b60_0 .net *"_s1", 0 0, L_0x1239680; 1 drivers -S_0x1018c40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x1018e50 .param/l "i" 0 4 54, +C4<010>; -L_0x1239720/d .functor AND 1, L_0x12397e0, L_0x1239940, C4<1>, C4<1>; -L_0x1239720 .delay 1 (30000,30000,30000) L_0x1239720/d; -v0x1018ef0_0 .net *"_s0", 0 0, L_0x12397e0; 1 drivers -v0x1018fd0_0 .net *"_s1", 0 0, L_0x1239940; 1 drivers -S_0x10190b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x10192c0 .param/l "i" 0 4 54, +C4<011>; -L_0x1239a30/d .functor AND 1, L_0x1239af0, L_0x1239c50, C4<1>, C4<1>; -L_0x1239a30 .delay 1 (30000,30000,30000) L_0x1239a30/d; -v0x1019380_0 .net *"_s0", 0 0, L_0x1239af0; 1 drivers -v0x1019460_0 .net *"_s1", 0 0, L_0x1239c50; 1 drivers -S_0x1019540 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x10197a0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1239d90/d .functor AND 1, L_0x1239e50, L_0x1239fb0, C4<1>, C4<1>; -L_0x1239d90 .delay 1 (30000,30000,30000) L_0x1239d90/d; -v0x1019860_0 .net *"_s0", 0 0, L_0x1239e50; 1 drivers -v0x1019940_0 .net *"_s1", 0 0, L_0x1239fb0; 1 drivers -S_0x1019a20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x1019c30 .param/l "i" 0 4 54, +C4<0101>; -L_0x123a0a0/d .functor AND 1, L_0x123a110, L_0x123a380, C4<1>, C4<1>; -L_0x123a0a0 .delay 1 (30000,30000,30000) L_0x123a0a0/d; -v0x1019cf0_0 .net *"_s0", 0 0, L_0x123a110; 1 drivers -v0x1019dd0_0 .net *"_s1", 0 0, L_0x123a380; 1 drivers -S_0x1019eb0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x101a0c0 .param/l "i" 0 4 54, +C4<0110>; -L_0x123a490/d .functor AND 1, L_0x123a550, L_0x123a6b0, C4<1>, C4<1>; -L_0x123a490 .delay 1 (30000,30000,30000) L_0x123a490/d; -v0x101a180_0 .net *"_s0", 0 0, L_0x123a550; 1 drivers -v0x101a260_0 .net *"_s1", 0 0, L_0x123a6b0; 1 drivers -S_0x101a340 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10180a0; - .timescale -9 -12; -P_0x101a550 .param/l "i" 0 4 54, +C4<0111>; -L_0x123a420/d .functor AND 1, L_0x123ab60, L_0x123ad50, C4<1>, C4<1>; -L_0x123a420 .delay 1 (30000,30000,30000) L_0x123a420/d; -v0x101a610_0 .net *"_s0", 0 0, L_0x123ab60; 1 drivers -v0x101a6f0_0 .net *"_s1", 0 0, L_0x123ad50; 1 drivers -S_0x101b2b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1017e80; +v0x2ae1940_0 .net "A", 7 0, L_0x2d15de0; alias, 1 drivers +v0x2ae1a40_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ae1b00_0 .net *"_s0", 0 0, L_0x2d19e90; 1 drivers +v0x2ae1bc0_0 .net *"_s12", 0 0, L_0x2d1a800; 1 drivers +v0x2ae1ca0_0 .net *"_s16", 0 0, L_0x2d1ab60; 1 drivers +v0x2ae1dd0_0 .net *"_s20", 0 0, L_0x2d1af30; 1 drivers +v0x2ae1eb0_0 .net *"_s24", 0 0, L_0x2d1b260; 1 drivers +v0x2ae1f90_0 .net *"_s28", 0 0, L_0x2d1b1f0; 1 drivers +v0x2ae2070_0 .net *"_s4", 0 0, L_0x2d1a1e0; 1 drivers +v0x2ae21e0_0 .net *"_s8", 0 0, L_0x2d1a4f0; 1 drivers +v0x2ae22c0_0 .net "out", 7 0, L_0x2d1b570; alias, 1 drivers +L_0x2d19f50 .part L_0x2d15de0, 0, 1; +L_0x2d1a140 .part v0x2cdd2e0_0, 0, 1; +L_0x2d1a2a0 .part L_0x2d15de0, 1, 1; +L_0x2d1a400 .part v0x2cdd2e0_0, 1, 1; +L_0x2d1a5b0 .part L_0x2d15de0, 2, 1; +L_0x2d1a710 .part v0x2cdd2e0_0, 2, 1; +L_0x2d1a8c0 .part L_0x2d15de0, 3, 1; +L_0x2d1aa20 .part v0x2cdd2e0_0, 3, 1; +L_0x2d1ac20 .part L_0x2d15de0, 4, 1; +L_0x2d1ae90 .part v0x2cdd2e0_0, 4, 1; +L_0x2d1afa0 .part L_0x2d15de0, 5, 1; +L_0x2d1b100 .part v0x2cdd2e0_0, 5, 1; +L_0x2d1b320 .part L_0x2d15de0, 6, 1; +L_0x2d1b480 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d1b570_0_0 .concat8 [ 1 1 1 1], L_0x2d19e90, L_0x2d1a1e0, L_0x2d1a4f0, L_0x2d1a800; +LS_0x2d1b570_0_4 .concat8 [ 1 1 1 1], L_0x2d1ab60, L_0x2d1af30, L_0x2d1b260, L_0x2d1b1f0; +L_0x2d1b570 .concat8 [ 4 4 0 0], LS_0x2d1b570_0_0, LS_0x2d1b570_0_4; +L_0x2d1b930 .part L_0x2d15de0, 7, 1; +L_0x2d1bb20 .part v0x2cdd2e0_0, 7, 1; +S_0x2adf470 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2adf680 .param/l "i" 0 4 54, +C4<00>; +L_0x2d19e90/d .functor AND 1, L_0x2d19f50, L_0x2d1a140, C4<1>, C4<1>; +L_0x2d19e90 .delay 1 (30000,30000,30000) L_0x2d19e90/d; +v0x2adf760_0 .net *"_s0", 0 0, L_0x2d19f50; 1 drivers +v0x2adf840_0 .net *"_s1", 0 0, L_0x2d1a140; 1 drivers +S_0x2adf920 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2adfb30 .param/l "i" 0 4 54, +C4<01>; +L_0x2d1a1e0/d .functor AND 1, L_0x2d1a2a0, L_0x2d1a400, C4<1>, C4<1>; +L_0x2d1a1e0 .delay 1 (30000,30000,30000) L_0x2d1a1e0/d; +v0x2adfbf0_0 .net *"_s0", 0 0, L_0x2d1a2a0; 1 drivers +v0x2adfcd0_0 .net *"_s1", 0 0, L_0x2d1a400; 1 drivers +S_0x2adfdb0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2adffc0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d1a4f0/d .functor AND 1, L_0x2d1a5b0, L_0x2d1a710, C4<1>, C4<1>; +L_0x2d1a4f0 .delay 1 (30000,30000,30000) L_0x2d1a4f0/d; +v0x2ae0060_0 .net *"_s0", 0 0, L_0x2d1a5b0; 1 drivers +v0x2ae0140_0 .net *"_s1", 0 0, L_0x2d1a710; 1 drivers +S_0x2ae0220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2ae0430 .param/l "i" 0 4 54, +C4<011>; +L_0x2d1a800/d .functor AND 1, L_0x2d1a8c0, L_0x2d1aa20, C4<1>, C4<1>; +L_0x2d1a800 .delay 1 (30000,30000,30000) L_0x2d1a800/d; +v0x2ae04f0_0 .net *"_s0", 0 0, L_0x2d1a8c0; 1 drivers +v0x2ae05d0_0 .net *"_s1", 0 0, L_0x2d1aa20; 1 drivers +S_0x2ae06b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2ae0910 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d1ab60/d .functor AND 1, L_0x2d1ac20, L_0x2d1ae90, C4<1>, C4<1>; +L_0x2d1ab60 .delay 1 (30000,30000,30000) L_0x2d1ab60/d; +v0x2ae09d0_0 .net *"_s0", 0 0, L_0x2d1ac20; 1 drivers +v0x2ae0ab0_0 .net *"_s1", 0 0, L_0x2d1ae90; 1 drivers +S_0x2ae0b90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2ae0da0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d1af30/d .functor AND 1, L_0x2d1afa0, L_0x2d1b100, C4<1>, C4<1>; +L_0x2d1af30 .delay 1 (30000,30000,30000) L_0x2d1af30/d; +v0x2ae0e60_0 .net *"_s0", 0 0, L_0x2d1afa0; 1 drivers +v0x2ae0f40_0 .net *"_s1", 0 0, L_0x2d1b100; 1 drivers +S_0x2ae1020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2ae1230 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d1b260/d .functor AND 1, L_0x2d1b320, L_0x2d1b480, C4<1>, C4<1>; +L_0x2d1b260 .delay 1 (30000,30000,30000) L_0x2d1b260/d; +v0x2ae12f0_0 .net *"_s0", 0 0, L_0x2d1b320; 1 drivers +v0x2ae13d0_0 .net *"_s1", 0 0, L_0x2d1b480; 1 drivers +S_0x2ae14b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2adf210; + .timescale -9 -12; +P_0x2ae16c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d1b1f0/d .functor AND 1, L_0x2d1b930, L_0x2d1bb20, C4<1>, C4<1>; +L_0x2d1b1f0 .delay 1 (30000,30000,30000) L_0x2d1b1f0/d; +v0x2ae1780_0 .net *"_s0", 0 0, L_0x2d1b930; 1 drivers +v0x2ae1860_0 .net *"_s1", 0 0, L_0x2d1bb20; 1 drivers +S_0x2ae2420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2adeff0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x123d6e0/d .functor OR 1, L_0x123d7a0, L_0x123d950, C4<0>, C4<0>; -L_0x123d6e0 .delay 1 (30000,30000,30000) L_0x123d6e0/d; -v0x101ce00_0 .net *"_s10", 0 0, L_0x123d7a0; 1 drivers -v0x101cee0_0 .net *"_s12", 0 0, L_0x123d950; 1 drivers -v0x101cfc0_0 .net "in", 7 0, L_0x123a7a0; alias, 1 drivers -v0x101d090_0 .net "ors", 1 0, L_0x123d500; 1 drivers -v0x101d150_0 .net "out", 0 0, L_0x123d6e0; alias, 1 drivers -L_0x1185460 .part L_0x123a7a0, 0, 4; -L_0x123d500 .concat8 [ 1 1 0 0], L_0x1185150, L_0x123d1f0; -L_0x123d640 .part L_0x123a7a0, 4, 4; -L_0x123d7a0 .part L_0x123d500, 0, 1; -L_0x123d950 .part L_0x123d500, 1, 1; -S_0x101b470 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x101b2b0; +L_0x2d1e4b0/d .functor OR 1, L_0x2d1e570, L_0x2d1e720, C4<0>, C4<0>; +L_0x2d1e4b0 .delay 1 (30000,30000,30000) L_0x2d1e4b0/d; +v0x2ae3f70_0 .net *"_s10", 0 0, L_0x2d1e570; 1 drivers +v0x2ae4050_0 .net *"_s12", 0 0, L_0x2d1e720; 1 drivers +v0x2ae4130_0 .net "in", 7 0, L_0x2d1b570; alias, 1 drivers +v0x2ae4200_0 .net "ors", 1 0, L_0x2d1e2d0; 1 drivers +v0x2ae42c0_0 .net "out", 0 0, L_0x2d1e4b0; alias, 1 drivers +L_0x2c5beb0 .part L_0x2d1b570, 0, 4; +L_0x2d1e2d0 .concat8 [ 1 1 0 0], L_0x2c5bba0, L_0x2d1dfc0; +L_0x2d1e410 .part L_0x2d1b570, 4, 4; +L_0x2d1e570 .part L_0x2d1e2d0, 0, 1; +L_0x2d1e720 .part L_0x2d1e2d0, 1, 1; +S_0x2ae25e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ae2420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1236ce0/d .functor OR 1, L_0x11849d0, L_0x1184b30, C4<0>, C4<0>; -L_0x1236ce0 .delay 1 (30000,30000,30000) L_0x1236ce0/d; -L_0x1184d60/d .functor OR 1, L_0x1184e70, L_0x1184fd0, C4<0>, C4<0>; -L_0x1184d60 .delay 1 (30000,30000,30000) L_0x1184d60/d; -L_0x1185150/d .functor OR 1, L_0x11851c0, L_0x1185370, C4<0>, C4<0>; -L_0x1185150 .delay 1 (30000,30000,30000) L_0x1185150/d; -v0x101b6c0_0 .net *"_s0", 0 0, L_0x1236ce0; 1 drivers -v0x101b7c0_0 .net *"_s10", 0 0, L_0x1184e70; 1 drivers -v0x101b8a0_0 .net *"_s12", 0 0, L_0x1184fd0; 1 drivers -v0x101b960_0 .net *"_s14", 0 0, L_0x11851c0; 1 drivers -v0x101ba40_0 .net *"_s16", 0 0, L_0x1185370; 1 drivers -v0x101bb70_0 .net *"_s3", 0 0, L_0x11849d0; 1 drivers -v0x101bc50_0 .net *"_s5", 0 0, L_0x1184b30; 1 drivers -v0x101bd30_0 .net *"_s6", 0 0, L_0x1184d60; 1 drivers -v0x101be10_0 .net "in", 3 0, L_0x1185460; 1 drivers -v0x101bf80_0 .net "ors", 1 0, L_0x1184c70; 1 drivers -v0x101c060_0 .net "out", 0 0, L_0x1185150; 1 drivers -L_0x11849d0 .part L_0x1185460, 0, 1; -L_0x1184b30 .part L_0x1185460, 1, 1; -L_0x1184c70 .concat8 [ 1 1 0 0], L_0x1236ce0, L_0x1184d60; -L_0x1184e70 .part L_0x1185460, 2, 1; -L_0x1184fd0 .part L_0x1185460, 3, 1; -L_0x11851c0 .part L_0x1184c70, 0, 1; -L_0x1185370 .part L_0x1184c70, 1, 1; -S_0x101c180 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x101b2b0; +L_0x2d17ab0/d .functor OR 1, L_0x2c5b420, L_0x2c5b580, C4<0>, C4<0>; +L_0x2d17ab0 .delay 1 (30000,30000,30000) L_0x2d17ab0/d; +L_0x2c5b7b0/d .functor OR 1, L_0x2c5b8c0, L_0x2c5ba20, C4<0>, C4<0>; +L_0x2c5b7b0 .delay 1 (30000,30000,30000) L_0x2c5b7b0/d; +L_0x2c5bba0/d .functor OR 1, L_0x2c5bc10, L_0x2c5bdc0, C4<0>, C4<0>; +L_0x2c5bba0 .delay 1 (30000,30000,30000) L_0x2c5bba0/d; +v0x2ae2830_0 .net *"_s0", 0 0, L_0x2d17ab0; 1 drivers +v0x2ae2930_0 .net *"_s10", 0 0, L_0x2c5b8c0; 1 drivers +v0x2ae2a10_0 .net *"_s12", 0 0, L_0x2c5ba20; 1 drivers +v0x2ae2ad0_0 .net *"_s14", 0 0, L_0x2c5bc10; 1 drivers +v0x2ae2bb0_0 .net *"_s16", 0 0, L_0x2c5bdc0; 1 drivers +v0x2ae2ce0_0 .net *"_s3", 0 0, L_0x2c5b420; 1 drivers +v0x2ae2dc0_0 .net *"_s5", 0 0, L_0x2c5b580; 1 drivers +v0x2ae2ea0_0 .net *"_s6", 0 0, L_0x2c5b7b0; 1 drivers +v0x2ae2f80_0 .net "in", 3 0, L_0x2c5beb0; 1 drivers +v0x2ae30f0_0 .net "ors", 1 0, L_0x2c5b6c0; 1 drivers +v0x2ae31d0_0 .net "out", 0 0, L_0x2c5bba0; 1 drivers +L_0x2c5b420 .part L_0x2c5beb0, 0, 1; +L_0x2c5b580 .part L_0x2c5beb0, 1, 1; +L_0x2c5b6c0 .concat8 [ 1 1 0 0], L_0x2d17ab0, L_0x2c5b7b0; +L_0x2c5b8c0 .part L_0x2c5beb0, 2, 1; +L_0x2c5ba20 .part L_0x2c5beb0, 3, 1; +L_0x2c5bc10 .part L_0x2c5b6c0, 0, 1; +L_0x2c5bdc0 .part L_0x2c5b6c0, 1, 1; +S_0x2ae32f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ae2420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1185590/d .functor OR 1, L_0x1185600, L_0x1185760, C4<0>, C4<0>; -L_0x1185590 .delay 1 (30000,30000,30000) L_0x1185590/d; -L_0x123ce50/d .functor OR 1, L_0x123cf10, L_0x123d070, C4<0>, C4<0>; -L_0x123ce50 .delay 1 (30000,30000,30000) L_0x123ce50/d; -L_0x123d1f0/d .functor OR 1, L_0x123d260, L_0x123d410, C4<0>, C4<0>; -L_0x123d1f0 .delay 1 (30000,30000,30000) L_0x123d1f0/d; -v0x101c340_0 .net *"_s0", 0 0, L_0x1185590; 1 drivers -v0x101c440_0 .net *"_s10", 0 0, L_0x123cf10; 1 drivers -v0x101c520_0 .net *"_s12", 0 0, L_0x123d070; 1 drivers -v0x101c5e0_0 .net *"_s14", 0 0, L_0x123d260; 1 drivers -v0x101c6c0_0 .net *"_s16", 0 0, L_0x123d410; 1 drivers -v0x101c7f0_0 .net *"_s3", 0 0, L_0x1185600; 1 drivers -v0x101c8d0_0 .net *"_s5", 0 0, L_0x1185760; 1 drivers -v0x101c9b0_0 .net *"_s6", 0 0, L_0x123ce50; 1 drivers -v0x101ca90_0 .net "in", 3 0, L_0x123d640; 1 drivers -v0x101cc00_0 .net "ors", 1 0, L_0x11858a0; 1 drivers -v0x101cce0_0 .net "out", 0 0, L_0x123d1f0; 1 drivers -L_0x1185600 .part L_0x123d640, 0, 1; -L_0x1185760 .part L_0x123d640, 1, 1; -L_0x11858a0 .concat8 [ 1 1 0 0], L_0x1185590, L_0x123ce50; -L_0x123cf10 .part L_0x123d640, 2, 1; -L_0x123d070 .part L_0x123d640, 3, 1; -L_0x123d260 .part L_0x11858a0, 0, 1; -L_0x123d410 .part L_0x11858a0, 1, 1; -S_0x101d5f0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1016720; +L_0x2c5bfe0/d .functor OR 1, L_0x2c5c050, L_0x2c5c1b0, C4<0>, C4<0>; +L_0x2c5bfe0 .delay 1 (30000,30000,30000) L_0x2c5bfe0/d; +L_0x2d1dc20/d .functor OR 1, L_0x2d1dce0, L_0x2d1de40, C4<0>, C4<0>; +L_0x2d1dc20 .delay 1 (30000,30000,30000) L_0x2d1dc20/d; +L_0x2d1dfc0/d .functor OR 1, L_0x2d1e030, L_0x2d1e1e0, C4<0>, C4<0>; +L_0x2d1dfc0 .delay 1 (30000,30000,30000) L_0x2d1dfc0/d; +v0x2ae34b0_0 .net *"_s0", 0 0, L_0x2c5bfe0; 1 drivers +v0x2ae35b0_0 .net *"_s10", 0 0, L_0x2d1dce0; 1 drivers +v0x2ae3690_0 .net *"_s12", 0 0, L_0x2d1de40; 1 drivers +v0x2ae3750_0 .net *"_s14", 0 0, L_0x2d1e030; 1 drivers +v0x2ae3830_0 .net *"_s16", 0 0, L_0x2d1e1e0; 1 drivers +v0x2ae3960_0 .net *"_s3", 0 0, L_0x2c5c050; 1 drivers +v0x2ae3a40_0 .net *"_s5", 0 0, L_0x2c5c1b0; 1 drivers +v0x2ae3b20_0 .net *"_s6", 0 0, L_0x2d1dc20; 1 drivers +v0x2ae3c00_0 .net "in", 3 0, L_0x2d1e410; 1 drivers +v0x2ae3d70_0 .net "ors", 1 0, L_0x2c5c2f0; 1 drivers +v0x2ae3e50_0 .net "out", 0 0, L_0x2d1dfc0; 1 drivers +L_0x2c5c050 .part L_0x2d1e410, 0, 1; +L_0x2c5c1b0 .part L_0x2d1e410, 1, 1; +L_0x2c5c2f0 .concat8 [ 1 1 0 0], L_0x2c5bfe0, L_0x2d1dc20; +L_0x2d1dce0 .part L_0x2d1e410, 2, 1; +L_0x2d1de40 .part L_0x2d1e410, 3, 1; +L_0x2d1e030 .part L_0x2c5c2f0, 0, 1; +L_0x2d1e1e0 .part L_0x2c5c2f0, 1, 1; +S_0x2ae4760 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2add890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1022a30_0 .net "ands", 7 0, L_0x1236d60; 1 drivers -v0x1022b40_0 .net "in", 7 0, L_0x12351c0; alias, 1 drivers -v0x1022c00_0 .net "out", 0 0, L_0x1238d60; alias, 1 drivers -v0x1022cd0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x101d840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x101d5f0; +v0x2ae9b90_0 .net "ands", 7 0, L_0x2d17b30; 1 drivers +v0x2ae9ca0_0 .net "in", 7 0, L_0x2d15aa0; alias, 1 drivers +v0x2ae9d60_0 .net "out", 0 0, L_0x2d19b30; alias, 1 drivers +v0x2ae9e30_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2ae49b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2ae4760; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x101ff80_0 .net "A", 7 0, L_0x12351c0; alias, 1 drivers -v0x1020080_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1020140_0 .net *"_s0", 0 0, L_0x1235550; 1 drivers -v0x1020200_0 .net *"_s12", 0 0, L_0x1235f10; 1 drivers -v0x10202e0_0 .net *"_s16", 0 0, L_0x1236270; 1 drivers -v0x1020410_0 .net *"_s20", 0 0, L_0x12366a0; 1 drivers -v0x10204f0_0 .net *"_s24", 0 0, L_0x12369d0; 1 drivers -v0x10205d0_0 .net *"_s28", 0 0, L_0x1236960; 1 drivers -v0x10206b0_0 .net *"_s4", 0 0, L_0x12358f0; 1 drivers -v0x1020820_0 .net *"_s8", 0 0, L_0x1235c00; 1 drivers -v0x1020900_0 .net "out", 7 0, L_0x1236d60; alias, 1 drivers -L_0x1235660 .part L_0x12351c0, 0, 1; -L_0x1235850 .part v0x12010b0_0, 0, 1; -L_0x12359b0 .part L_0x12351c0, 1, 1; -L_0x1235b10 .part v0x12010b0_0, 1, 1; -L_0x1235cc0 .part L_0x12351c0, 2, 1; -L_0x1235e20 .part v0x12010b0_0, 2, 1; -L_0x1235fd0 .part L_0x12351c0, 3, 1; -L_0x1236130 .part v0x12010b0_0, 3, 1; -L_0x1236330 .part L_0x12351c0, 4, 1; -L_0x12365a0 .part v0x12010b0_0, 4, 1; -L_0x1236710 .part L_0x12351c0, 5, 1; -L_0x1236870 .part v0x12010b0_0, 5, 1; -L_0x1236a90 .part L_0x12351c0, 6, 1; -L_0x1236bf0 .part v0x12010b0_0, 6, 1; -LS_0x1236d60_0_0 .concat8 [ 1 1 1 1], L_0x1235550, L_0x12358f0, L_0x1235c00, L_0x1235f10; -LS_0x1236d60_0_4 .concat8 [ 1 1 1 1], L_0x1236270, L_0x12366a0, L_0x12369d0, L_0x1236960; -L_0x1236d60 .concat8 [ 4 4 0 0], LS_0x1236d60_0_0, LS_0x1236d60_0_4; -L_0x1237120 .part L_0x12351c0, 7, 1; -L_0x1237310 .part v0x12010b0_0, 7, 1; -S_0x101da80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101dc90 .param/l "i" 0 4 54, +C4<00>; -L_0x1235550/d .functor AND 1, L_0x1235660, L_0x1235850, C4<1>, C4<1>; -L_0x1235550 .delay 1 (30000,30000,30000) L_0x1235550/d; -v0x101dd70_0 .net *"_s0", 0 0, L_0x1235660; 1 drivers -v0x101de50_0 .net *"_s1", 0 0, L_0x1235850; 1 drivers -S_0x101df30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101e140 .param/l "i" 0 4 54, +C4<01>; -L_0x12358f0/d .functor AND 1, L_0x12359b0, L_0x1235b10, C4<1>, C4<1>; -L_0x12358f0 .delay 1 (30000,30000,30000) L_0x12358f0/d; -v0x101e200_0 .net *"_s0", 0 0, L_0x12359b0; 1 drivers -v0x101e2e0_0 .net *"_s1", 0 0, L_0x1235b10; 1 drivers -S_0x101e3c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101e600 .param/l "i" 0 4 54, +C4<010>; -L_0x1235c00/d .functor AND 1, L_0x1235cc0, L_0x1235e20, C4<1>, C4<1>; -L_0x1235c00 .delay 1 (30000,30000,30000) L_0x1235c00/d; -v0x101e6a0_0 .net *"_s0", 0 0, L_0x1235cc0; 1 drivers -v0x101e780_0 .net *"_s1", 0 0, L_0x1235e20; 1 drivers -S_0x101e860 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101ea70 .param/l "i" 0 4 54, +C4<011>; -L_0x1235f10/d .functor AND 1, L_0x1235fd0, L_0x1236130, C4<1>, C4<1>; -L_0x1235f10 .delay 1 (30000,30000,30000) L_0x1235f10/d; -v0x101eb30_0 .net *"_s0", 0 0, L_0x1235fd0; 1 drivers -v0x101ec10_0 .net *"_s1", 0 0, L_0x1236130; 1 drivers -S_0x101ecf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101ef50 .param/l "i" 0 4 54, +C4<0100>; -L_0x1236270/d .functor AND 1, L_0x1236330, L_0x12365a0, C4<1>, C4<1>; -L_0x1236270 .delay 1 (30000,30000,30000) L_0x1236270/d; -v0x101f010_0 .net *"_s0", 0 0, L_0x1236330; 1 drivers -v0x101f0f0_0 .net *"_s1", 0 0, L_0x12365a0; 1 drivers -S_0x101f1d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101f3e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x12366a0/d .functor AND 1, L_0x1236710, L_0x1236870, C4<1>, C4<1>; -L_0x12366a0 .delay 1 (30000,30000,30000) L_0x12366a0/d; -v0x101f4a0_0 .net *"_s0", 0 0, L_0x1236710; 1 drivers -v0x101f580_0 .net *"_s1", 0 0, L_0x1236870; 1 drivers -S_0x101f660 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101f870 .param/l "i" 0 4 54, +C4<0110>; -L_0x12369d0/d .functor AND 1, L_0x1236a90, L_0x1236bf0, C4<1>, C4<1>; -L_0x12369d0 .delay 1 (30000,30000,30000) L_0x12369d0/d; -v0x101f930_0 .net *"_s0", 0 0, L_0x1236a90; 1 drivers -v0x101fa10_0 .net *"_s1", 0 0, L_0x1236bf0; 1 drivers -S_0x101faf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x101d840; - .timescale -9 -12; -P_0x101fd00 .param/l "i" 0 4 54, +C4<0111>; -L_0x1236960/d .functor AND 1, L_0x1237120, L_0x1237310, C4<1>, C4<1>; -L_0x1236960 .delay 1 (30000,30000,30000) L_0x1236960/d; -v0x101fdc0_0 .net *"_s0", 0 0, L_0x1237120; 1 drivers -v0x101fea0_0 .net *"_s1", 0 0, L_0x1237310; 1 drivers -S_0x1020a60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x101d5f0; +v0x2ae70f0_0 .net "A", 7 0, L_0x2d15aa0; alias, 1 drivers +v0x2ae71f0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ae72b0_0 .net *"_s0", 0 0, L_0x2d16320; 1 drivers +v0x2ae7370_0 .net *"_s12", 0 0, L_0x2d16ce0; 1 drivers +v0x2ae7450_0 .net *"_s16", 0 0, L_0x2d17040; 1 drivers +v0x2ae7580_0 .net *"_s20", 0 0, L_0x2d17470; 1 drivers +v0x2ae7660_0 .net *"_s24", 0 0, L_0x2d177a0; 1 drivers +v0x2ae7740_0 .net *"_s28", 0 0, L_0x2d17730; 1 drivers +v0x2ae7820_0 .net *"_s4", 0 0, L_0x2d166c0; 1 drivers +v0x2ae7990_0 .net *"_s8", 0 0, L_0x2d169d0; 1 drivers +v0x2ae7a70_0 .net "out", 7 0, L_0x2d17b30; alias, 1 drivers +L_0x2d16430 .part L_0x2d15aa0, 0, 1; +L_0x2d16620 .part v0x2cdd2e0_0, 0, 1; +L_0x2d16780 .part L_0x2d15aa0, 1, 1; +L_0x2d168e0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d16a90 .part L_0x2d15aa0, 2, 1; +L_0x2d16bf0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d16da0 .part L_0x2d15aa0, 3, 1; +L_0x2d16f00 .part v0x2cdd2e0_0, 3, 1; +L_0x2d17100 .part L_0x2d15aa0, 4, 1; +L_0x2d17370 .part v0x2cdd2e0_0, 4, 1; +L_0x2d174e0 .part L_0x2d15aa0, 5, 1; +L_0x2d17640 .part v0x2cdd2e0_0, 5, 1; +L_0x2d17860 .part L_0x2d15aa0, 6, 1; +L_0x2d179c0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d17b30_0_0 .concat8 [ 1 1 1 1], L_0x2d16320, L_0x2d166c0, L_0x2d169d0, L_0x2d16ce0; +LS_0x2d17b30_0_4 .concat8 [ 1 1 1 1], L_0x2d17040, L_0x2d17470, L_0x2d177a0, L_0x2d17730; +L_0x2d17b30 .concat8 [ 4 4 0 0], LS_0x2d17b30_0_0, LS_0x2d17b30_0_4; +L_0x2d17ef0 .part L_0x2d15aa0, 7, 1; +L_0x2d180e0 .part v0x2cdd2e0_0, 7, 1; +S_0x2ae4bf0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae4e00 .param/l "i" 0 4 54, +C4<00>; +L_0x2d16320/d .functor AND 1, L_0x2d16430, L_0x2d16620, C4<1>, C4<1>; +L_0x2d16320 .delay 1 (30000,30000,30000) L_0x2d16320/d; +v0x2ae4ee0_0 .net *"_s0", 0 0, L_0x2d16430; 1 drivers +v0x2ae4fc0_0 .net *"_s1", 0 0, L_0x2d16620; 1 drivers +S_0x2ae50a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae52b0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d166c0/d .functor AND 1, L_0x2d16780, L_0x2d168e0, C4<1>, C4<1>; +L_0x2d166c0 .delay 1 (30000,30000,30000) L_0x2d166c0/d; +v0x2ae5370_0 .net *"_s0", 0 0, L_0x2d16780; 1 drivers +v0x2ae5450_0 .net *"_s1", 0 0, L_0x2d168e0; 1 drivers +S_0x2ae5530 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae5770 .param/l "i" 0 4 54, +C4<010>; +L_0x2d169d0/d .functor AND 1, L_0x2d16a90, L_0x2d16bf0, C4<1>, C4<1>; +L_0x2d169d0 .delay 1 (30000,30000,30000) L_0x2d169d0/d; +v0x2ae5810_0 .net *"_s0", 0 0, L_0x2d16a90; 1 drivers +v0x2ae58f0_0 .net *"_s1", 0 0, L_0x2d16bf0; 1 drivers +S_0x2ae59d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae5be0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d16ce0/d .functor AND 1, L_0x2d16da0, L_0x2d16f00, C4<1>, C4<1>; +L_0x2d16ce0 .delay 1 (30000,30000,30000) L_0x2d16ce0/d; +v0x2ae5ca0_0 .net *"_s0", 0 0, L_0x2d16da0; 1 drivers +v0x2ae5d80_0 .net *"_s1", 0 0, L_0x2d16f00; 1 drivers +S_0x2ae5e60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae60c0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d17040/d .functor AND 1, L_0x2d17100, L_0x2d17370, C4<1>, C4<1>; +L_0x2d17040 .delay 1 (30000,30000,30000) L_0x2d17040/d; +v0x2ae6180_0 .net *"_s0", 0 0, L_0x2d17100; 1 drivers +v0x2ae6260_0 .net *"_s1", 0 0, L_0x2d17370; 1 drivers +S_0x2ae6340 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae6550 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d17470/d .functor AND 1, L_0x2d174e0, L_0x2d17640, C4<1>, C4<1>; +L_0x2d17470 .delay 1 (30000,30000,30000) L_0x2d17470/d; +v0x2ae6610_0 .net *"_s0", 0 0, L_0x2d174e0; 1 drivers +v0x2ae66f0_0 .net *"_s1", 0 0, L_0x2d17640; 1 drivers +S_0x2ae67d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae69e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d177a0/d .functor AND 1, L_0x2d17860, L_0x2d179c0, C4<1>, C4<1>; +L_0x2d177a0 .delay 1 (30000,30000,30000) L_0x2d177a0/d; +v0x2ae6aa0_0 .net *"_s0", 0 0, L_0x2d17860; 1 drivers +v0x2ae6b80_0 .net *"_s1", 0 0, L_0x2d179c0; 1 drivers +S_0x2ae6c60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2ae49b0; + .timescale -9 -12; +P_0x2ae6e70 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d17730/d .functor AND 1, L_0x2d17ef0, L_0x2d180e0, C4<1>, C4<1>; +L_0x2d17730 .delay 1 (30000,30000,30000) L_0x2d17730/d; +v0x2ae6f30_0 .net *"_s0", 0 0, L_0x2d17ef0; 1 drivers +v0x2ae7010_0 .net *"_s1", 0 0, L_0x2d180e0; 1 drivers +S_0x2ae7bd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2ae4760; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1238d60/d .functor OR 1, L_0x1238e20, L_0x1238fd0, C4<0>, C4<0>; -L_0x1238d60 .delay 1 (30000,30000,30000) L_0x1238d60/d; -v0x1022590_0 .net *"_s10", 0 0, L_0x1238e20; 1 drivers -v0x1022670_0 .net *"_s12", 0 0, L_0x1238fd0; 1 drivers -v0x1022750_0 .net "in", 7 0, L_0x1236d60; alias, 1 drivers -v0x1022850_0 .net "ors", 1 0, L_0x1238b80; 1 drivers -v0x1022910_0 .net "out", 0 0, L_0x1238d60; alias, 1 drivers -L_0x1237f50 .part L_0x1236d60, 0, 4; -L_0x1238b80 .concat8 [ 1 1 0 0], L_0x1237c40, L_0x1238870; -L_0x1238cc0 .part L_0x1236d60, 4, 4; -L_0x1238e20 .part L_0x1238b80, 0, 1; -L_0x1238fd0 .part L_0x1238b80, 1, 1; -S_0x1020c20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1020a60; +L_0x2d19b30/d .functor OR 1, L_0x2d19bf0, L_0x2d19da0, C4<0>, C4<0>; +L_0x2d19b30 .delay 1 (30000,30000,30000) L_0x2d19b30/d; +v0x2ae9720_0 .net *"_s10", 0 0, L_0x2d19bf0; 1 drivers +v0x2ae9800_0 .net *"_s12", 0 0, L_0x2d19da0; 1 drivers +v0x2ae98e0_0 .net "in", 7 0, L_0x2d17b30; alias, 1 drivers +v0x2ae99b0_0 .net "ors", 1 0, L_0x2d19950; 1 drivers +v0x2ae9a70_0 .net "out", 0 0, L_0x2d19b30; alias, 1 drivers +L_0x2d18d20 .part L_0x2d17b30, 0, 4; +L_0x2d19950 .concat8 [ 1 1 0 0], L_0x2d18a10, L_0x2d19640; +L_0x2d19a90 .part L_0x2d17b30, 4, 4; +L_0x2d19bf0 .part L_0x2d19950, 0, 1; +L_0x2d19da0 .part L_0x2d19950, 1, 1; +S_0x2ae7d90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ae7bd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1237400/d .functor OR 1, L_0x12374c0, L_0x1237620, C4<0>, C4<0>; -L_0x1237400 .delay 1 (30000,30000,30000) L_0x1237400/d; -L_0x1237850/d .functor OR 1, L_0x1237960, L_0x1237ac0, C4<0>, C4<0>; -L_0x1237850 .delay 1 (30000,30000,30000) L_0x1237850/d; -L_0x1237c40/d .functor OR 1, L_0x1237cb0, L_0x1237e60, C4<0>, C4<0>; -L_0x1237c40 .delay 1 (30000,30000,30000) L_0x1237c40/d; -v0x1020e70_0 .net *"_s0", 0 0, L_0x1237400; 1 drivers -v0x1020f70_0 .net *"_s10", 0 0, L_0x1237960; 1 drivers -v0x1021050_0 .net *"_s12", 0 0, L_0x1237ac0; 1 drivers -v0x1021110_0 .net *"_s14", 0 0, L_0x1237cb0; 1 drivers -v0x10211f0_0 .net *"_s16", 0 0, L_0x1237e60; 1 drivers -v0x1021320_0 .net *"_s3", 0 0, L_0x12374c0; 1 drivers -v0x1021400_0 .net *"_s5", 0 0, L_0x1237620; 1 drivers -v0x10214e0_0 .net *"_s6", 0 0, L_0x1237850; 1 drivers -v0x10215c0_0 .net "in", 3 0, L_0x1237f50; 1 drivers -v0x1021730_0 .net "ors", 1 0, L_0x1237760; 1 drivers -v0x1021810_0 .net "out", 0 0, L_0x1237c40; 1 drivers -L_0x12374c0 .part L_0x1237f50, 0, 1; -L_0x1237620 .part L_0x1237f50, 1, 1; -L_0x1237760 .concat8 [ 1 1 0 0], L_0x1237400, L_0x1237850; -L_0x1237960 .part L_0x1237f50, 2, 1; -L_0x1237ac0 .part L_0x1237f50, 3, 1; -L_0x1237cb0 .part L_0x1237760, 0, 1; -L_0x1237e60 .part L_0x1237760, 1, 1; -S_0x1021930 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1020a60; +L_0x2d181d0/d .functor OR 1, L_0x2d18290, L_0x2d183f0, C4<0>, C4<0>; +L_0x2d181d0 .delay 1 (30000,30000,30000) L_0x2d181d0/d; +L_0x2d18620/d .functor OR 1, L_0x2d18730, L_0x2d18890, C4<0>, C4<0>; +L_0x2d18620 .delay 1 (30000,30000,30000) L_0x2d18620/d; +L_0x2d18a10/d .functor OR 1, L_0x2d18a80, L_0x2d18c30, C4<0>, C4<0>; +L_0x2d18a10 .delay 1 (30000,30000,30000) L_0x2d18a10/d; +v0x2ae7fe0_0 .net *"_s0", 0 0, L_0x2d181d0; 1 drivers +v0x2ae80e0_0 .net *"_s10", 0 0, L_0x2d18730; 1 drivers +v0x2ae81c0_0 .net *"_s12", 0 0, L_0x2d18890; 1 drivers +v0x2ae8280_0 .net *"_s14", 0 0, L_0x2d18a80; 1 drivers +v0x2ae8360_0 .net *"_s16", 0 0, L_0x2d18c30; 1 drivers +v0x2ae8490_0 .net *"_s3", 0 0, L_0x2d18290; 1 drivers +v0x2ae8570_0 .net *"_s5", 0 0, L_0x2d183f0; 1 drivers +v0x2ae8650_0 .net *"_s6", 0 0, L_0x2d18620; 1 drivers +v0x2ae8730_0 .net "in", 3 0, L_0x2d18d20; 1 drivers +v0x2ae88a0_0 .net "ors", 1 0, L_0x2d18530; 1 drivers +v0x2ae8980_0 .net "out", 0 0, L_0x2d18a10; 1 drivers +L_0x2d18290 .part L_0x2d18d20, 0, 1; +L_0x2d183f0 .part L_0x2d18d20, 1, 1; +L_0x2d18530 .concat8 [ 1 1 0 0], L_0x2d181d0, L_0x2d18620; +L_0x2d18730 .part L_0x2d18d20, 2, 1; +L_0x2d18890 .part L_0x2d18d20, 3, 1; +L_0x2d18a80 .part L_0x2d18530, 0, 1; +L_0x2d18c30 .part L_0x2d18530, 1, 1; +S_0x2ae8aa0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ae7bd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1238080/d .functor OR 1, L_0x12380f0, L_0x1238250, C4<0>, C4<0>; -L_0x1238080 .delay 1 (30000,30000,30000) L_0x1238080/d; -L_0x1238480/d .functor OR 1, L_0x1238590, L_0x12386f0, C4<0>, C4<0>; -L_0x1238480 .delay 1 (30000,30000,30000) L_0x1238480/d; -L_0x1238870/d .functor OR 1, L_0x12388e0, L_0x1238a90, C4<0>, C4<0>; -L_0x1238870 .delay 1 (30000,30000,30000) L_0x1238870/d; -v0x1021af0_0 .net *"_s0", 0 0, L_0x1238080; 1 drivers -v0x1021bf0_0 .net *"_s10", 0 0, L_0x1238590; 1 drivers -v0x1021cd0_0 .net *"_s12", 0 0, L_0x12386f0; 1 drivers -v0x1021d90_0 .net *"_s14", 0 0, L_0x12388e0; 1 drivers -v0x1021e70_0 .net *"_s16", 0 0, L_0x1238a90; 1 drivers -v0x1021fa0_0 .net *"_s3", 0 0, L_0x12380f0; 1 drivers -v0x1022060_0 .net *"_s5", 0 0, L_0x1238250; 1 drivers -v0x1022140_0 .net *"_s6", 0 0, L_0x1238480; 1 drivers -v0x1022220_0 .net "in", 3 0, L_0x1238cc0; 1 drivers -v0x1022390_0 .net "ors", 1 0, L_0x1238390; 1 drivers -v0x1022470_0 .net "out", 0 0, L_0x1238870; 1 drivers -L_0x12380f0 .part L_0x1238cc0, 0, 1; -L_0x1238250 .part L_0x1238cc0, 1, 1; -L_0x1238390 .concat8 [ 1 1 0 0], L_0x1238080, L_0x1238480; -L_0x1238590 .part L_0x1238cc0, 2, 1; -L_0x12386f0 .part L_0x1238cc0, 3, 1; -L_0x12388e0 .part L_0x1238390, 0, 1; -L_0x1238a90 .part L_0x1238390, 1, 1; -S_0x1022db0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1016720; +L_0x2d18e50/d .functor OR 1, L_0x2d18ec0, L_0x2d19020, C4<0>, C4<0>; +L_0x2d18e50 .delay 1 (30000,30000,30000) L_0x2d18e50/d; +L_0x2d19250/d .functor OR 1, L_0x2d19360, L_0x2d194c0, C4<0>, C4<0>; +L_0x2d19250 .delay 1 (30000,30000,30000) L_0x2d19250/d; +L_0x2d19640/d .functor OR 1, L_0x2d196b0, L_0x2d19860, C4<0>, C4<0>; +L_0x2d19640 .delay 1 (30000,30000,30000) L_0x2d19640/d; +v0x2ae8c60_0 .net *"_s0", 0 0, L_0x2d18e50; 1 drivers +v0x2ae8d60_0 .net *"_s10", 0 0, L_0x2d19360; 1 drivers +v0x2ae8e40_0 .net *"_s12", 0 0, L_0x2d194c0; 1 drivers +v0x2ae8f00_0 .net *"_s14", 0 0, L_0x2d196b0; 1 drivers +v0x2ae8fe0_0 .net *"_s16", 0 0, L_0x2d19860; 1 drivers +v0x2ae9110_0 .net *"_s3", 0 0, L_0x2d18ec0; 1 drivers +v0x2ae91f0_0 .net *"_s5", 0 0, L_0x2d19020; 1 drivers +v0x2ae92d0_0 .net *"_s6", 0 0, L_0x2d19250; 1 drivers +v0x2ae93b0_0 .net "in", 3 0, L_0x2d19a90; 1 drivers +v0x2ae9520_0 .net "ors", 1 0, L_0x2d19160; 1 drivers +v0x2ae9600_0 .net "out", 0 0, L_0x2d19640; 1 drivers +L_0x2d18ec0 .part L_0x2d19a90, 0, 1; +L_0x2d19020 .part L_0x2d19a90, 1, 1; +L_0x2d19160 .concat8 [ 1 1 0 0], L_0x2d18e50, L_0x2d19250; +L_0x2d19360 .part L_0x2d19a90, 2, 1; +L_0x2d194c0 .part L_0x2d19a90, 3, 1; +L_0x2d196b0 .part L_0x2d19160, 0, 1; +L_0x2d19860 .part L_0x2d19160, 1, 1; +S_0x2ae9f10 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2add890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -3350,80 +3538,80 @@ S_0x1022db0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1016720; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1234530/d .functor XNOR 1, L_0x123db40, L_0x123dd30, C4<0>, C4<0>; -L_0x1234530 .delay 1 (20000,20000,20000) L_0x1234530/d; -L_0x12347a0/d .functor AND 1, L_0x123db40, L_0x1233470, C4<1>, C4<1>; -L_0x12347a0 .delay 1 (30000,30000,30000) L_0x12347a0/d; -L_0x1234810/d .functor AND 1, L_0x1234530, L_0x123ddd0, C4<1>, C4<1>; -L_0x1234810 .delay 1 (30000,30000,30000) L_0x1234810/d; -L_0x1234970/d .functor OR 1, L_0x1234810, L_0x12347a0, C4<0>, C4<0>; -L_0x1234970 .delay 1 (30000,30000,30000) L_0x1234970/d; -v0x1023060_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers -v0x1023150_0 .net "a_", 0 0, L_0x1233200; alias, 1 drivers -v0x1023210_0 .net "b", 0 0, L_0x123dd30; alias, 1 drivers -v0x1023300_0 .net "b_", 0 0, L_0x1233470; alias, 1 drivers -v0x10233a0_0 .net "carryin", 0 0, L_0x123ddd0; alias, 1 drivers -v0x10234e0_0 .net "eq", 0 0, L_0x1234530; 1 drivers -v0x10235a0_0 .net "lt", 0 0, L_0x12347a0; 1 drivers -v0x1023660_0 .net "out", 0 0, L_0x1234970; 1 drivers -v0x1023720_0 .net "w0", 0 0, L_0x1234810; 1 drivers -S_0x1023970 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1016720; +L_0x2d148e0/d .functor XNOR 1, L_0x2d1ea70, L_0x2d1eb10, C4<0>, C4<0>; +L_0x2d148e0 .delay 1 (20000,20000,20000) L_0x2d148e0/d; +L_0x2d14a60/d .functor AND 1, L_0x2d1ea70, L_0x2d136c0, C4<1>, C4<1>; +L_0x2d14a60 .delay 1 (30000,30000,30000) L_0x2d14a60/d; +L_0x2d14bc0/d .functor AND 1, L_0x2d148e0, L_0x2d1ebb0, C4<1>, C4<1>; +L_0x2d14bc0 .delay 1 (30000,30000,30000) L_0x2d14bc0/d; +L_0x2d14cd0/d .functor OR 1, L_0x2d14bc0, L_0x2d14a60, C4<0>, C4<0>; +L_0x2d14cd0 .delay 1 (30000,30000,30000) L_0x2d14cd0/d; +v0x2aea1c0_0 .net "a", 0 0, L_0x2d1ea70; alias, 1 drivers +v0x2aea2b0_0 .net "a_", 0 0, L_0x2d09170; alias, 1 drivers +v0x2aea370_0 .net "b", 0 0, L_0x2d1eb10; alias, 1 drivers +v0x2aea460_0 .net "b_", 0 0, L_0x2d136c0; alias, 1 drivers +v0x2aea500_0 .net "carryin", 0 0, L_0x2d1ebb0; alias, 1 drivers +v0x2aea640_0 .net "eq", 0 0, L_0x2d148e0; 1 drivers +v0x2aea700_0 .net "lt", 0 0, L_0x2d14a60; 1 drivers +v0x2aea7c0_0 .net "out", 0 0, L_0x2d14cd0; 1 drivers +v0x2aea880_0 .net "w0", 0 0, L_0x2d14bc0; 1 drivers +S_0x2aeaad0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2add890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1234310/d .functor OR 1, L_0x1233e60, L_0x1024bd0, C4<0>, C4<0>; -L_0x1234310 .delay 1 (30000,30000,30000) L_0x1234310/d; -v0x1024760_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers -v0x10248b0_0 .net "b", 0 0, L_0x1233470; alias, 1 drivers -v0x1024970_0 .net "c1", 0 0, L_0x1233e60; 1 drivers -v0x1024a10_0 .net "c2", 0 0, L_0x1024bd0; 1 drivers -v0x1024ae0_0 .net "carryin", 0 0, L_0x123ddd0; alias, 1 drivers -v0x1024c60_0 .net "carryout", 0 0, L_0x1234310; 1 drivers -v0x1024d00_0 .net "s1", 0 0, L_0x1233da0; 1 drivers -v0x1024da0_0 .net "sum", 0 0, L_0x1233fc0; 1 drivers -S_0x1023bc0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1023970; +L_0x2d144c0/d .functor OR 1, L_0x2d14010, L_0x2aebd30, C4<0>, C4<0>; +L_0x2d144c0 .delay 1 (30000,30000,30000) L_0x2d144c0/d; +v0x2aeb8c0_0 .net "a", 0 0, L_0x2d1ea70; alias, 1 drivers +v0x2aeba10_0 .net "b", 0 0, L_0x2d136c0; alias, 1 drivers +v0x2aebad0_0 .net "c1", 0 0, L_0x2d14010; 1 drivers +v0x2aebb70_0 .net "c2", 0 0, L_0x2aebd30; 1 drivers +v0x2aebc40_0 .net "carryin", 0 0, L_0x2d1ebb0; alias, 1 drivers +v0x2aebdc0_0 .net "carryout", 0 0, L_0x2d144c0; 1 drivers +v0x2aebe60_0 .net "s1", 0 0, L_0x2d13f50; 1 drivers +v0x2aebf00_0 .net "sum", 0 0, L_0x2d14170; 1 drivers +S_0x2aead20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2aeaad0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1233da0/d .functor XOR 1, L_0x123db40, L_0x1233470, C4<0>, C4<0>; -L_0x1233da0 .delay 1 (30000,30000,30000) L_0x1233da0/d; -L_0x1233e60/d .functor AND 1, L_0x123db40, L_0x1233470, C4<1>, C4<1>; -L_0x1233e60 .delay 1 (30000,30000,30000) L_0x1233e60/d; -v0x1023e20_0 .net "a", 0 0, L_0x123db40; alias, 1 drivers -v0x1023ee0_0 .net "b", 0 0, L_0x1233470; alias, 1 drivers -v0x1023fa0_0 .net "carryout", 0 0, L_0x1233e60; alias, 1 drivers -v0x1024040_0 .net "sum", 0 0, L_0x1233da0; alias, 1 drivers -S_0x1024170 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1023970; +L_0x2d13f50/d .functor XOR 1, L_0x2d1ea70, L_0x2d136c0, C4<0>, C4<0>; +L_0x2d13f50 .delay 1 (30000,30000,30000) L_0x2d13f50/d; +L_0x2d14010/d .functor AND 1, L_0x2d1ea70, L_0x2d136c0, C4<1>, C4<1>; +L_0x2d14010 .delay 1 (30000,30000,30000) L_0x2d14010/d; +v0x2aeaf80_0 .net "a", 0 0, L_0x2d1ea70; alias, 1 drivers +v0x2aeb040_0 .net "b", 0 0, L_0x2d136c0; alias, 1 drivers +v0x2aeb100_0 .net "carryout", 0 0, L_0x2d14010; alias, 1 drivers +v0x2aeb1a0_0 .net "sum", 0 0, L_0x2d13f50; alias, 1 drivers +S_0x2aeb2d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2aeaad0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1233fc0/d .functor XOR 1, L_0x1233da0, L_0x123ddd0, C4<0>, C4<0>; -L_0x1233fc0 .delay 1 (30000,30000,30000) L_0x1233fc0/d; -L_0x1024bd0/d .functor AND 1, L_0x1233da0, L_0x123ddd0, C4<1>, C4<1>; -L_0x1024bd0 .delay 1 (30000,30000,30000) L_0x1024bd0/d; -v0x10243d0_0 .net "a", 0 0, L_0x1233da0; alias, 1 drivers -v0x10244a0_0 .net "b", 0 0, L_0x123ddd0; alias, 1 drivers -v0x1024540_0 .net "carryout", 0 0, L_0x1024bd0; alias, 1 drivers -v0x1024610_0 .net "sum", 0 0, L_0x1233fc0; alias, 1 drivers -S_0x10261c0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1016450; - .timescale -9 -12; -L_0x2b0ab3d055b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05600 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x123dbe0/d .functor OR 1, L_0x2b0ab3d055b8, L_0x2b0ab3d05600, C4<0>, C4<0>; -L_0x123dbe0 .delay 1 (30000,30000,30000) L_0x123dbe0/d; -v0x10263b0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d055b8; 1 drivers -v0x1026490_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05600; 1 drivers -S_0x1026570 .scope generate, "alu_slices[6]" "alu_slices[6]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1026780 .param/l "i" 0 3 41, +C4<0110>; -S_0x1026840 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1026570; +L_0x2d14170/d .functor XOR 1, L_0x2d13f50, L_0x2d1ebb0, C4<0>, C4<0>; +L_0x2d14170 .delay 1 (30000,30000,30000) L_0x2d14170/d; +L_0x2aebd30/d .functor AND 1, L_0x2d13f50, L_0x2d1ebb0, C4<1>, C4<1>; +L_0x2aebd30 .delay 1 (30000,30000,30000) L_0x2aebd30/d; +v0x2aeb530_0 .net "a", 0 0, L_0x2d13f50; alias, 1 drivers +v0x2aeb600_0 .net "b", 0 0, L_0x2d1ebb0; alias, 1 drivers +v0x2aeb6a0_0 .net "carryout", 0 0, L_0x2aebd30; alias, 1 drivers +v0x2aeb770_0 .net "sum", 0 0, L_0x2d14170; alias, 1 drivers +S_0x2aedf90 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2add5c0; + .timescale -9 -12; +L_0x2ac6110b7698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b76e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d13a80/d .functor OR 1, L_0x2ac6110b7698, L_0x2ac6110b76e0, C4<0>, C4<0>; +L_0x2d13a80 .delay 1 (30000,30000,30000) L_0x2d13a80/d; +v0x2aee180_0 .net/2u *"_s0", 0 0, L_0x2ac6110b7698; 1 drivers +v0x2aee260_0 .net/2u *"_s2", 0 0, L_0x2ac6110b76e0; 1 drivers +S_0x2aee340 .scope generate, "alu_slices[6]" "alu_slices[6]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2aee550 .param/l "i" 0 3 39, +C4<0110>; +S_0x2aee610 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2aee340; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -3432,445 +3620,476 @@ S_0x1026840 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1026570; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x123dfb0/d .functor NOT 1, L_0x1247830, C4<0>, C4<0>, C4<0>; -L_0x123dfb0 .delay 1 (10000,10000,10000) L_0x123dfb0/d; -L_0x123e110/d .functor NOT 1, L_0x1247aa0, C4<0>, C4<0>, C4<0>; -L_0x123e110 .delay 1 (10000,10000,10000) L_0x123e110/d; -L_0x123f0a0/d .functor XOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; -L_0x123f0a0 .delay 1 (30000,30000,30000) L_0x123f0a0/d; -L_0x2b0ab3d05648 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05690 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x123f750/d .functor OR 1, L_0x2b0ab3d05648, L_0x2b0ab3d05690, C4<0>, C4<0>; -L_0x123f750 .delay 1 (30000,30000,30000) L_0x123f750/d; -L_0x123f950/d .functor AND 1, L_0x1247830, L_0x1247aa0, C4<1>, C4<1>; -L_0x123f950 .delay 1 (30000,30000,30000) L_0x123f950/d; -L_0x123fa10/d .functor NAND 1, L_0x1247830, L_0x1247aa0, C4<1>, C4<1>; -L_0x123fa10 .delay 1 (20000,20000,20000) L_0x123fa10/d; -L_0x123fb70/d .functor XOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; -L_0x123fb70 .delay 1 (20000,20000,20000) L_0x123fb70/d; -L_0x1240020/d .functor OR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; -L_0x1240020 .delay 1 (30000,30000,30000) L_0x1240020/d; -L_0x1247730/d .functor NOT 1, L_0x1243990, C4<0>, C4<0>, C4<0>; -L_0x1247730 .delay 1 (10000,10000,10000) L_0x1247730/d; -v0x1035170_0 .net "A", 0 0, L_0x1247830; 1 drivers -v0x1035230_0 .net "A_", 0 0, L_0x123dfb0; 1 drivers -v0x10352f0_0 .net "B", 0 0, L_0x1247aa0; 1 drivers -v0x10353c0_0 .net "B_", 0 0, L_0x123e110; 1 drivers -v0x1035460_0 .net *"_s12", 0 0, L_0x123f750; 1 drivers -v0x1035550_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05648; 1 drivers -v0x1035610_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05690; 1 drivers -v0x10356f0_0 .net *"_s18", 0 0, L_0x123f950; 1 drivers -v0x10357d0_0 .net *"_s20", 0 0, L_0x123fa10; 1 drivers -v0x1035940_0 .net *"_s22", 0 0, L_0x123fb70; 1 drivers -v0x1035a20_0 .net *"_s24", 0 0, L_0x1240020; 1 drivers -o0x2b0ab3cb32a8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1035b00_0 name=_s30 -o0x2b0ab3cb32d8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1035be0_0 name=_s32 -v0x1035cc0_0 .net *"_s8", 0 0, L_0x123f0a0; 1 drivers -v0x1035da0_0 .net "carryin", 0 0, L_0x123de70; 1 drivers -v0x1035e40_0 .net "carryout", 0 0, L_0x12473d0; 1 drivers -v0x1035ee0_0 .net "carryouts", 7 0, L_0x13538c0; 1 drivers -v0x1036090_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1036130_0 .net "result", 0 0, L_0x1243990; 1 drivers -v0x1036220_0 .net "results", 7 0, L_0x123fdf0; 1 drivers -v0x1036330_0 .net "zero", 0 0, L_0x1247730; 1 drivers -LS_0x123fdf0_0_0 .concat8 [ 1 1 1 1], L_0x123e5c0, L_0x123ebf0, L_0x123f0a0, L_0x123f750; -LS_0x123fdf0_0_4 .concat8 [ 1 1 1 1], L_0x123f950, L_0x123fa10, L_0x123fb70, L_0x1240020; -L_0x123fdf0 .concat8 [ 4 4 0 0], LS_0x123fdf0_0_0, LS_0x123fdf0_0_4; -LS_0x13538c0_0_0 .concat [ 1 1 1 1], L_0x123e870, L_0x123ef40, o0x2b0ab3cb32a8, L_0x123f5a0; -LS_0x13538c0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb32d8; -L_0x13538c0 .concat [ 4 4 0 0], LS_0x13538c0_0_0, LS_0x13538c0_0_4; -S_0x1026ac0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1026840; +L_0x2d1ed90/d .functor NOT 1, L_0x2d29270, C4<0>, C4<0>, C4<0>; +L_0x2d1ed90 .delay 1 (10000,10000,10000) L_0x2d1ed90/d; +L_0x2d1eef0/d .functor NOT 1, L_0x2d294e0, C4<0>, C4<0>, C4<0>; +L_0x2d1eef0 .delay 1 (10000,10000,10000) L_0x2d1eef0/d; +L_0x2d1ff40/d .functor XOR 1, L_0x2d29270, L_0x2d294e0, C4<0>, C4<0>; +L_0x2d1ff40 .delay 1 (30000,30000,30000) L_0x2d1ff40/d; +L_0x2ac6110b7728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d20000/d .functor OR 1, L_0x2ac6110b7728, L_0x2ac6110b7770, C4<0>, C4<0>; +L_0x2d20000 .delay 1 (30000,30000,30000) L_0x2d20000/d; +L_0x2ac6110b77b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d207a0/d .functor OR 1, L_0x2ac6110b77b8, L_0x2ac6110b7800, C4<0>, C4<0>; +L_0x2d207a0 .delay 1 (30000,30000,30000) L_0x2d207a0/d; +L_0x2d209a0/d .functor AND 1, L_0x2d29270, L_0x2d294e0, C4<1>, C4<1>; +L_0x2d209a0 .delay 1 (30000,30000,30000) L_0x2d209a0/d; +L_0x2ac6110b7848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d20a60/d .functor OR 1, L_0x2ac6110b7848, L_0x2ac6110b7890, C4<0>, C4<0>; +L_0x2d20a60 .delay 1 (30000,30000,30000) L_0x2d20a60/d; +L_0x2d20c60/d .functor NAND 1, L_0x2d29270, L_0x2d294e0, C4<1>, C4<1>; +L_0x2d20c60 .delay 1 (20000,20000,20000) L_0x2d20c60/d; +L_0x2ac6110b78d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7920 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d20d70/d .functor OR 1, L_0x2ac6110b78d8, L_0x2ac6110b7920, C4<0>, C4<0>; +L_0x2d20d70 .delay 1 (30000,30000,30000) L_0x2d20d70/d; +L_0x2d20f20/d .functor NOR 1, L_0x2d29270, L_0x2d294e0, C4<0>, C4<0>; +L_0x2d20f20 .delay 1 (20000,20000,20000) L_0x2d20f20/d; +L_0x2ac6110b7968 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b79b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d211f0/d .functor OR 1, L_0x2ac6110b7968, L_0x2ac6110b79b0, C4<0>, C4<0>; +L_0x2d211f0 .delay 1 (30000,30000,30000) L_0x2d211f0/d; +L_0x2d215f0/d .functor OR 1, L_0x2d29270, L_0x2d294e0, C4<0>, C4<0>; +L_0x2d215f0 .delay 1 (30000,30000,30000) L_0x2d215f0/d; +L_0x2ac6110b79f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7a40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d21a90/d .functor OR 1, L_0x2ac6110b79f8, L_0x2ac6110b7a40, C4<0>, C4<0>; +L_0x2d21a90 .delay 1 (30000,30000,30000) L_0x2d21a90/d; +L_0x2d29170/d .functor NOT 1, L_0x2d253d0, C4<0>, C4<0>, C4<0>; +L_0x2d29170 .delay 1 (10000,10000,10000) L_0x2d29170/d; +v0x2afcf40_0 .net "A", 0 0, L_0x2d29270; 1 drivers +v0x2afd000_0 .net "A_", 0 0, L_0x2d1ed90; 1 drivers +v0x2afd0c0_0 .net "B", 0 0, L_0x2d294e0; 1 drivers +v0x2afd190_0 .net "B_", 0 0, L_0x2d1eef0; 1 drivers +v0x2afd230_0 .net *"_s11", 0 0, L_0x2d20000; 1 drivers +v0x2afd320_0 .net/2s *"_s13", 0 0, L_0x2ac6110b7728; 1 drivers +v0x2afd3e0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b7770; 1 drivers +v0x2afd4c0_0 .net *"_s19", 0 0, L_0x2d207a0; 1 drivers +v0x2afd5a0_0 .net/2s *"_s21", 0 0, L_0x2ac6110b77b8; 1 drivers +v0x2afd710_0 .net/2s *"_s23", 0 0, L_0x2ac6110b7800; 1 drivers +v0x2afd7f0_0 .net *"_s25", 0 0, L_0x2d209a0; 1 drivers +v0x2afd8d0_0 .net *"_s28", 0 0, L_0x2d20a60; 1 drivers +v0x2afd9b0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b7848; 1 drivers +v0x2afda90_0 .net/2s *"_s32", 0 0, L_0x2ac6110b7890; 1 drivers +v0x2afdb70_0 .net *"_s34", 0 0, L_0x2d20c60; 1 drivers +v0x2afdc50_0 .net *"_s37", 0 0, L_0x2d20d70; 1 drivers +v0x2afdd30_0 .net/2s *"_s39", 0 0, L_0x2ac6110b78d8; 1 drivers +v0x2afdee0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b7920; 1 drivers +v0x2afdf80_0 .net *"_s43", 0 0, L_0x2d20f20; 1 drivers +v0x2afe060_0 .net *"_s46", 0 0, L_0x2d211f0; 1 drivers +v0x2afe140_0 .net/2s *"_s48", 0 0, L_0x2ac6110b7968; 1 drivers +v0x2afe220_0 .net/2s *"_s50", 0 0, L_0x2ac6110b79b0; 1 drivers +v0x2afe300_0 .net *"_s52", 0 0, L_0x2d215f0; 1 drivers +v0x2afe3e0_0 .net *"_s56", 0 0, L_0x2d21a90; 1 drivers +v0x2afe4c0_0 .net/2s *"_s59", 0 0, L_0x2ac6110b79f8; 1 drivers +v0x2afe5a0_0 .net/2s *"_s61", 0 0, L_0x2ac6110b7a40; 1 drivers +v0x2afe680_0 .net *"_s8", 0 0, L_0x2d1ff40; 1 drivers +v0x2afe760_0 .net "carryin", 0 0, L_0x2d1ec50; 1 drivers +v0x2afe800_0 .net "carryout", 0 0, L_0x2d28e10; 1 drivers +v0x2afe8a0_0 .net "carryouts", 7 0, L_0x2d21700; 1 drivers +v0x2afe9b0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2afea70_0 .net "result", 0 0, L_0x2d253d0; 1 drivers +v0x2afeb60_0 .net "results", 7 0, L_0x2d213c0; 1 drivers +v0x2afde40_0 .net "zero", 0 0, L_0x2d29170; 1 drivers +LS_0x2d213c0_0_0 .concat8 [ 1 1 1 1], L_0x2d1f410, L_0x2d1fa40, L_0x2d1ff40, L_0x2d207a0; +LS_0x2d213c0_0_4 .concat8 [ 1 1 1 1], L_0x2d209a0, L_0x2d20c60, L_0x2d20f20, L_0x2d215f0; +L_0x2d213c0 .concat8 [ 4 4 0 0], LS_0x2d213c0_0_0, LS_0x2d213c0_0_4; +LS_0x2d21700_0_0 .concat8 [ 1 1 1 1], L_0x2d1f6c0, L_0x2d1fde0, L_0x2d20000, L_0x2d205f0; +LS_0x2d21700_0_4 .concat8 [ 1 1 1 1], L_0x2d20a60, L_0x2d20d70, L_0x2d211f0, L_0x2d21a90; +L_0x2d21700 .concat8 [ 4 4 0 0], LS_0x2d21700_0_0, LS_0x2d21700_0_4; +S_0x2aee890 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2aee610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x123e870/d .functor OR 1, L_0x123e350, L_0x123e710, C4<0>, C4<0>; -L_0x123e870 .delay 1 (30000,30000,30000) L_0x123e870/d; -v0x10278f0_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers -v0x10279b0_0 .net "b", 0 0, L_0x1247aa0; alias, 1 drivers -v0x1027a80_0 .net "c1", 0 0, L_0x123e350; 1 drivers -v0x1027b80_0 .net "c2", 0 0, L_0x123e710; 1 drivers -v0x1027c50_0 .net "carryin", 0 0, L_0x123de70; alias, 1 drivers -v0x1027d40_0 .net "carryout", 0 0, L_0x123e870; 1 drivers -v0x1027de0_0 .net "s1", 0 0, L_0x1223410; 1 drivers -v0x1027ed0_0 .net "sum", 0 0, L_0x123e5c0; 1 drivers -S_0x1026d30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1026ac0; +L_0x2d1f6c0/d .functor OR 1, L_0x2d1f1a0, L_0x2d1f560, C4<0>, C4<0>; +L_0x2d1f6c0 .delay 1 (30000,30000,30000) L_0x2d1f6c0/d; +v0x2aef6c0_0 .net "a", 0 0, L_0x2d29270; alias, 1 drivers +v0x2aef780_0 .net "b", 0 0, L_0x2d294e0; alias, 1 drivers +v0x2aef850_0 .net "c1", 0 0, L_0x2d1f1a0; 1 drivers +v0x2aef950_0 .net "c2", 0 0, L_0x2d1f560; 1 drivers +v0x2aefa20_0 .net "carryin", 0 0, L_0x2d1ec50; alias, 1 drivers +v0x2aefb10_0 .net "carryout", 0 0, L_0x2d1f6c0; 1 drivers +v0x2aefbb0_0 .net "s1", 0 0, L_0x2d1f0e0; 1 drivers +v0x2aefca0_0 .net "sum", 0 0, L_0x2d1f410; 1 drivers +S_0x2aeeb00 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2aee890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1223410/d .functor XOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; -L_0x1223410 .delay 1 (30000,30000,30000) L_0x1223410/d; -L_0x123e350/d .functor AND 1, L_0x1247830, L_0x1247aa0, C4<1>, C4<1>; -L_0x123e350 .delay 1 (30000,30000,30000) L_0x123e350/d; -v0x1026f90_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers -v0x1027070_0 .net "b", 0 0, L_0x1247aa0; alias, 1 drivers -v0x1027130_0 .net "carryout", 0 0, L_0x123e350; alias, 1 drivers -v0x10271d0_0 .net "sum", 0 0, L_0x1223410; alias, 1 drivers -S_0x1027310 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1026ac0; +L_0x2d1f0e0/d .functor XOR 1, L_0x2d29270, L_0x2d294e0, C4<0>, C4<0>; +L_0x2d1f0e0 .delay 1 (30000,30000,30000) L_0x2d1f0e0/d; +L_0x2d1f1a0/d .functor AND 1, L_0x2d29270, L_0x2d294e0, C4<1>, C4<1>; +L_0x2d1f1a0 .delay 1 (30000,30000,30000) L_0x2d1f1a0/d; +v0x2aeed60_0 .net "a", 0 0, L_0x2d29270; alias, 1 drivers +v0x2aeee40_0 .net "b", 0 0, L_0x2d294e0; alias, 1 drivers +v0x2aeef00_0 .net "carryout", 0 0, L_0x2d1f1a0; alias, 1 drivers +v0x2aeefa0_0 .net "sum", 0 0, L_0x2d1f0e0; alias, 1 drivers +S_0x2aef0e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2aee890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x123e5c0/d .functor XOR 1, L_0x1223410, L_0x123de70, C4<0>, C4<0>; -L_0x123e5c0 .delay 1 (30000,30000,30000) L_0x123e5c0/d; -L_0x123e710/d .functor AND 1, L_0x1223410, L_0x123de70, C4<1>, C4<1>; -L_0x123e710 .delay 1 (30000,30000,30000) L_0x123e710/d; -v0x1027570_0 .net "a", 0 0, L_0x1223410; alias, 1 drivers -v0x1027610_0 .net "b", 0 0, L_0x123de70; alias, 1 drivers -v0x10276b0_0 .net "carryout", 0 0, L_0x123e710; alias, 1 drivers -v0x1027780_0 .net "sum", 0 0, L_0x123e5c0; alias, 1 drivers -S_0x1027fa0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1026840; +L_0x2d1f410/d .functor XOR 1, L_0x2d1f0e0, L_0x2d1ec50, C4<0>, C4<0>; +L_0x2d1f410 .delay 1 (30000,30000,30000) L_0x2d1f410/d; +L_0x2d1f560/d .functor AND 1, L_0x2d1f0e0, L_0x2d1ec50, C4<1>, C4<1>; +L_0x2d1f560 .delay 1 (30000,30000,30000) L_0x2d1f560/d; +v0x2aef340_0 .net "a", 0 0, L_0x2d1f0e0; alias, 1 drivers +v0x2aef3e0_0 .net "b", 0 0, L_0x2d1ec50; alias, 1 drivers +v0x2aef480_0 .net "carryout", 0 0, L_0x2d1f560; alias, 1 drivers +v0x2aef550_0 .net "sum", 0 0, L_0x2d1f410; alias, 1 drivers +S_0x2aefd70 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2aee610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x102d390_0 .net "ands", 7 0, L_0x12453d0; 1 drivers -v0x102d4a0_0 .net "in", 7 0, L_0x13538c0; alias, 1 drivers -v0x102d560_0 .net "out", 0 0, L_0x12473d0; alias, 1 drivers -v0x102d630_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10281c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1027fa0; +v0x2af5160_0 .net "ands", 7 0, L_0x2d26e10; 1 drivers +v0x2af5270_0 .net "in", 7 0, L_0x2d21700; alias, 1 drivers +v0x2af5330_0 .net "out", 0 0, L_0x2d28e10; alias, 1 drivers +v0x2af5400_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2aeff90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2aefd70; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x102a8f0_0 .net "A", 7 0, L_0x13538c0; alias, 1 drivers -v0x102a9f0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x102aab0_0 .net *"_s0", 0 0, L_0x1243cf0; 1 drivers -v0x102ab70_0 .net *"_s12", 0 0, L_0x1244660; 1 drivers -v0x102ac50_0 .net *"_s16", 0 0, L_0x12449c0; 1 drivers -v0x102ad80_0 .net *"_s20", 0 0, L_0x1244cd0; 1 drivers -v0x102ae60_0 .net *"_s24", 0 0, L_0x12450c0; 1 drivers -v0x102af40_0 .net *"_s28", 0 0, L_0x1245050; 1 drivers -v0x102b020_0 .net *"_s4", 0 0, L_0x1244000; 1 drivers -v0x102b190_0 .net *"_s8", 0 0, L_0x1244350; 1 drivers -v0x102b270_0 .net "out", 7 0, L_0x12453d0; alias, 1 drivers -L_0x1243db0 .part L_0x13538c0, 0, 1; -L_0x1243f10 .part v0x12010b0_0, 0, 1; -L_0x12440c0 .part L_0x13538c0, 1, 1; -L_0x12442b0 .part v0x12010b0_0, 1, 1; -L_0x1244410 .part L_0x13538c0, 2, 1; -L_0x1244570 .part v0x12010b0_0, 2, 1; -L_0x1244720 .part L_0x13538c0, 3, 1; -L_0x1244880 .part v0x12010b0_0, 3, 1; -L_0x1244a80 .part L_0x13538c0, 4, 1; -L_0x1244be0 .part v0x12010b0_0, 4, 1; -L_0x1244d40 .part L_0x13538c0, 5, 1; -L_0x1244fb0 .part v0x12010b0_0, 5, 1; -L_0x1245180 .part L_0x13538c0, 6, 1; -L_0x12452e0 .part v0x12010b0_0, 6, 1; -LS_0x12453d0_0_0 .concat8 [ 1 1 1 1], L_0x1243cf0, L_0x1244000, L_0x1244350, L_0x1244660; -LS_0x12453d0_0_4 .concat8 [ 1 1 1 1], L_0x12449c0, L_0x1244cd0, L_0x12450c0, L_0x1245050; -L_0x12453d0 .concat8 [ 4 4 0 0], LS_0x12453d0_0_0, LS_0x12453d0_0_4; -L_0x1245790 .part L_0x13538c0, 7, 1; -L_0x1245980 .part v0x12010b0_0, 7, 1; -S_0x1028420 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x1028630 .param/l "i" 0 4 54, +C4<00>; -L_0x1243cf0/d .functor AND 1, L_0x1243db0, L_0x1243f10, C4<1>, C4<1>; -L_0x1243cf0 .delay 1 (30000,30000,30000) L_0x1243cf0/d; -v0x1028710_0 .net *"_s0", 0 0, L_0x1243db0; 1 drivers -v0x10287f0_0 .net *"_s1", 0 0, L_0x1243f10; 1 drivers -S_0x10288d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x1028ae0 .param/l "i" 0 4 54, +C4<01>; -L_0x1244000/d .functor AND 1, L_0x12440c0, L_0x12442b0, C4<1>, C4<1>; -L_0x1244000 .delay 1 (30000,30000,30000) L_0x1244000/d; -v0x1028ba0_0 .net *"_s0", 0 0, L_0x12440c0; 1 drivers -v0x1028c80_0 .net *"_s1", 0 0, L_0x12442b0; 1 drivers -S_0x1028d60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x1028f70 .param/l "i" 0 4 54, +C4<010>; -L_0x1244350/d .functor AND 1, L_0x1244410, L_0x1244570, C4<1>, C4<1>; -L_0x1244350 .delay 1 (30000,30000,30000) L_0x1244350/d; -v0x1029010_0 .net *"_s0", 0 0, L_0x1244410; 1 drivers -v0x10290f0_0 .net *"_s1", 0 0, L_0x1244570; 1 drivers -S_0x10291d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x10293e0 .param/l "i" 0 4 54, +C4<011>; -L_0x1244660/d .functor AND 1, L_0x1244720, L_0x1244880, C4<1>, C4<1>; -L_0x1244660 .delay 1 (30000,30000,30000) L_0x1244660/d; -v0x10294a0_0 .net *"_s0", 0 0, L_0x1244720; 1 drivers -v0x1029580_0 .net *"_s1", 0 0, L_0x1244880; 1 drivers -S_0x1029660 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x10298c0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12449c0/d .functor AND 1, L_0x1244a80, L_0x1244be0, C4<1>, C4<1>; -L_0x12449c0 .delay 1 (30000,30000,30000) L_0x12449c0/d; -v0x1029980_0 .net *"_s0", 0 0, L_0x1244a80; 1 drivers -v0x1029a60_0 .net *"_s1", 0 0, L_0x1244be0; 1 drivers -S_0x1029b40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x1029d50 .param/l "i" 0 4 54, +C4<0101>; -L_0x1244cd0/d .functor AND 1, L_0x1244d40, L_0x1244fb0, C4<1>, C4<1>; -L_0x1244cd0 .delay 1 (30000,30000,30000) L_0x1244cd0/d; -v0x1029e10_0 .net *"_s0", 0 0, L_0x1244d40; 1 drivers -v0x1029ef0_0 .net *"_s1", 0 0, L_0x1244fb0; 1 drivers -S_0x1029fd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x102a1e0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12450c0/d .functor AND 1, L_0x1245180, L_0x12452e0, C4<1>, C4<1>; -L_0x12450c0 .delay 1 (30000,30000,30000) L_0x12450c0/d; -v0x102a2a0_0 .net *"_s0", 0 0, L_0x1245180; 1 drivers -v0x102a380_0 .net *"_s1", 0 0, L_0x12452e0; 1 drivers -S_0x102a460 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10281c0; - .timescale -9 -12; -P_0x102a670 .param/l "i" 0 4 54, +C4<0111>; -L_0x1245050/d .functor AND 1, L_0x1245790, L_0x1245980, C4<1>, C4<1>; -L_0x1245050 .delay 1 (30000,30000,30000) L_0x1245050/d; -v0x102a730_0 .net *"_s0", 0 0, L_0x1245790; 1 drivers -v0x102a810_0 .net *"_s1", 0 0, L_0x1245980; 1 drivers -S_0x102b3d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1027fa0; +v0x2af26c0_0 .net "A", 7 0, L_0x2d21700; alias, 1 drivers +v0x2af27c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2af2880_0 .net *"_s0", 0 0, L_0x2d25730; 1 drivers +v0x2af2940_0 .net *"_s12", 0 0, L_0x2d260a0; 1 drivers +v0x2af2a20_0 .net *"_s16", 0 0, L_0x2d26400; 1 drivers +v0x2af2b50_0 .net *"_s20", 0 0, L_0x2d267d0; 1 drivers +v0x2af2c30_0 .net *"_s24", 0 0, L_0x2d26b00; 1 drivers +v0x2af2d10_0 .net *"_s28", 0 0, L_0x2d26a90; 1 drivers +v0x2af2df0_0 .net *"_s4", 0 0, L_0x2d25a80; 1 drivers +v0x2af2f60_0 .net *"_s8", 0 0, L_0x2d25d90; 1 drivers +v0x2af3040_0 .net "out", 7 0, L_0x2d26e10; alias, 1 drivers +L_0x2d257f0 .part L_0x2d21700, 0, 1; +L_0x2d259e0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d25b40 .part L_0x2d21700, 1, 1; +L_0x2d25ca0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d25e50 .part L_0x2d21700, 2, 1; +L_0x2d25fb0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d26160 .part L_0x2d21700, 3, 1; +L_0x2d262c0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d264c0 .part L_0x2d21700, 4, 1; +L_0x2d26730 .part v0x2cdd2e0_0, 4, 1; +L_0x2d26840 .part L_0x2d21700, 5, 1; +L_0x2d269a0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d26bc0 .part L_0x2d21700, 6, 1; +L_0x2d26d20 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d26e10_0_0 .concat8 [ 1 1 1 1], L_0x2d25730, L_0x2d25a80, L_0x2d25d90, L_0x2d260a0; +LS_0x2d26e10_0_4 .concat8 [ 1 1 1 1], L_0x2d26400, L_0x2d267d0, L_0x2d26b00, L_0x2d26a90; +L_0x2d26e10 .concat8 [ 4 4 0 0], LS_0x2d26e10_0_0, LS_0x2d26e10_0_4; +L_0x2d271d0 .part L_0x2d21700, 7, 1; +L_0x2d273c0 .part v0x2cdd2e0_0, 7, 1; +S_0x2af01f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af0400 .param/l "i" 0 4 54, +C4<00>; +L_0x2d25730/d .functor AND 1, L_0x2d257f0, L_0x2d259e0, C4<1>, C4<1>; +L_0x2d25730 .delay 1 (30000,30000,30000) L_0x2d25730/d; +v0x2af04e0_0 .net *"_s0", 0 0, L_0x2d257f0; 1 drivers +v0x2af05c0_0 .net *"_s1", 0 0, L_0x2d259e0; 1 drivers +S_0x2af06a0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af08b0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d25a80/d .functor AND 1, L_0x2d25b40, L_0x2d25ca0, C4<1>, C4<1>; +L_0x2d25a80 .delay 1 (30000,30000,30000) L_0x2d25a80/d; +v0x2af0970_0 .net *"_s0", 0 0, L_0x2d25b40; 1 drivers +v0x2af0a50_0 .net *"_s1", 0 0, L_0x2d25ca0; 1 drivers +S_0x2af0b30 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af0d40 .param/l "i" 0 4 54, +C4<010>; +L_0x2d25d90/d .functor AND 1, L_0x2d25e50, L_0x2d25fb0, C4<1>, C4<1>; +L_0x2d25d90 .delay 1 (30000,30000,30000) L_0x2d25d90/d; +v0x2af0de0_0 .net *"_s0", 0 0, L_0x2d25e50; 1 drivers +v0x2af0ec0_0 .net *"_s1", 0 0, L_0x2d25fb0; 1 drivers +S_0x2af0fa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af11b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d260a0/d .functor AND 1, L_0x2d26160, L_0x2d262c0, C4<1>, C4<1>; +L_0x2d260a0 .delay 1 (30000,30000,30000) L_0x2d260a0/d; +v0x2af1270_0 .net *"_s0", 0 0, L_0x2d26160; 1 drivers +v0x2af1350_0 .net *"_s1", 0 0, L_0x2d262c0; 1 drivers +S_0x2af1430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af1690 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d26400/d .functor AND 1, L_0x2d264c0, L_0x2d26730, C4<1>, C4<1>; +L_0x2d26400 .delay 1 (30000,30000,30000) L_0x2d26400/d; +v0x2af1750_0 .net *"_s0", 0 0, L_0x2d264c0; 1 drivers +v0x2af1830_0 .net *"_s1", 0 0, L_0x2d26730; 1 drivers +S_0x2af1910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af1b20 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d267d0/d .functor AND 1, L_0x2d26840, L_0x2d269a0, C4<1>, C4<1>; +L_0x2d267d0 .delay 1 (30000,30000,30000) L_0x2d267d0/d; +v0x2af1be0_0 .net *"_s0", 0 0, L_0x2d26840; 1 drivers +v0x2af1cc0_0 .net *"_s1", 0 0, L_0x2d269a0; 1 drivers +S_0x2af1da0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af1fb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d26b00/d .functor AND 1, L_0x2d26bc0, L_0x2d26d20, C4<1>, C4<1>; +L_0x2d26b00 .delay 1 (30000,30000,30000) L_0x2d26b00/d; +v0x2af2070_0 .net *"_s0", 0 0, L_0x2d26bc0; 1 drivers +v0x2af2150_0 .net *"_s1", 0 0, L_0x2d26d20; 1 drivers +S_0x2af2230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2aeff90; + .timescale -9 -12; +P_0x2af2440 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d26a90/d .functor AND 1, L_0x2d271d0, L_0x2d273c0, C4<1>, C4<1>; +L_0x2d26a90 .delay 1 (30000,30000,30000) L_0x2d26a90/d; +v0x2af2500_0 .net *"_s0", 0 0, L_0x2d271d0; 1 drivers +v0x2af25e0_0 .net *"_s1", 0 0, L_0x2d273c0; 1 drivers +S_0x2af31a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2aefd70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12473d0/d .functor OR 1, L_0x1247490, L_0x1247640, C4<0>, C4<0>; -L_0x12473d0 .delay 1 (30000,30000,30000) L_0x12473d0/d; -v0x102cf20_0 .net *"_s10", 0 0, L_0x1247490; 1 drivers -v0x102d000_0 .net *"_s12", 0 0, L_0x1247640; 1 drivers -v0x102d0e0_0 .net "in", 7 0, L_0x12453d0; alias, 1 drivers -v0x102d1b0_0 .net "ors", 1 0, L_0x12471f0; 1 drivers -v0x102d270_0 .net "out", 0 0, L_0x12473d0; alias, 1 drivers -L_0x12465c0 .part L_0x12453d0, 0, 4; -L_0x12471f0 .concat8 [ 1 1 0 0], L_0x12462b0, L_0x1246ee0; -L_0x1247330 .part L_0x12453d0, 4, 4; -L_0x1247490 .part L_0x12471f0, 0, 1; -L_0x1247640 .part L_0x12471f0, 1, 1; -S_0x102b590 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x102b3d0; +L_0x2d28e10/d .functor OR 1, L_0x2d28ed0, L_0x2d29080, C4<0>, C4<0>; +L_0x2d28e10 .delay 1 (30000,30000,30000) L_0x2d28e10/d; +v0x2af4cf0_0 .net *"_s10", 0 0, L_0x2d28ed0; 1 drivers +v0x2af4dd0_0 .net *"_s12", 0 0, L_0x2d29080; 1 drivers +v0x2af4eb0_0 .net "in", 7 0, L_0x2d26e10; alias, 1 drivers +v0x2af4f80_0 .net "ors", 1 0, L_0x2d28c30; 1 drivers +v0x2af5040_0 .net "out", 0 0, L_0x2d28e10; alias, 1 drivers +L_0x2d28000 .part L_0x2d26e10, 0, 4; +L_0x2d28c30 .concat8 [ 1 1 0 0], L_0x2d27cf0, L_0x2d28920; +L_0x2d28d70 .part L_0x2d26e10, 4, 4; +L_0x2d28ed0 .part L_0x2d28c30, 0, 1; +L_0x2d29080 .part L_0x2d28c30, 1, 1; +S_0x2af3360 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2af31a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1245a70/d .functor OR 1, L_0x1245b30, L_0x1245c90, C4<0>, C4<0>; -L_0x1245a70 .delay 1 (30000,30000,30000) L_0x1245a70/d; -L_0x1245ec0/d .functor OR 1, L_0x1245fd0, L_0x1246130, C4<0>, C4<0>; -L_0x1245ec0 .delay 1 (30000,30000,30000) L_0x1245ec0/d; -L_0x12462b0/d .functor OR 1, L_0x1246320, L_0x12464d0, C4<0>, C4<0>; -L_0x12462b0 .delay 1 (30000,30000,30000) L_0x12462b0/d; -v0x102b7e0_0 .net *"_s0", 0 0, L_0x1245a70; 1 drivers -v0x102b8e0_0 .net *"_s10", 0 0, L_0x1245fd0; 1 drivers -v0x102b9c0_0 .net *"_s12", 0 0, L_0x1246130; 1 drivers -v0x102ba80_0 .net *"_s14", 0 0, L_0x1246320; 1 drivers -v0x102bb60_0 .net *"_s16", 0 0, L_0x12464d0; 1 drivers -v0x102bc90_0 .net *"_s3", 0 0, L_0x1245b30; 1 drivers -v0x102bd70_0 .net *"_s5", 0 0, L_0x1245c90; 1 drivers -v0x102be50_0 .net *"_s6", 0 0, L_0x1245ec0; 1 drivers -v0x102bf30_0 .net "in", 3 0, L_0x12465c0; 1 drivers -v0x102c0a0_0 .net "ors", 1 0, L_0x1245dd0; 1 drivers -v0x102c180_0 .net "out", 0 0, L_0x12462b0; 1 drivers -L_0x1245b30 .part L_0x12465c0, 0, 1; -L_0x1245c90 .part L_0x12465c0, 1, 1; -L_0x1245dd0 .concat8 [ 1 1 0 0], L_0x1245a70, L_0x1245ec0; -L_0x1245fd0 .part L_0x12465c0, 2, 1; -L_0x1246130 .part L_0x12465c0, 3, 1; -L_0x1246320 .part L_0x1245dd0, 0, 1; -L_0x12464d0 .part L_0x1245dd0, 1, 1; -S_0x102c2a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x102b3d0; +L_0x2d274b0/d .functor OR 1, L_0x2d27570, L_0x2d276d0, C4<0>, C4<0>; +L_0x2d274b0 .delay 1 (30000,30000,30000) L_0x2d274b0/d; +L_0x2d27900/d .functor OR 1, L_0x2d27a10, L_0x2d27b70, C4<0>, C4<0>; +L_0x2d27900 .delay 1 (30000,30000,30000) L_0x2d27900/d; +L_0x2d27cf0/d .functor OR 1, L_0x2d27d60, L_0x2d27f10, C4<0>, C4<0>; +L_0x2d27cf0 .delay 1 (30000,30000,30000) L_0x2d27cf0/d; +v0x2af35b0_0 .net *"_s0", 0 0, L_0x2d274b0; 1 drivers +v0x2af36b0_0 .net *"_s10", 0 0, L_0x2d27a10; 1 drivers +v0x2af3790_0 .net *"_s12", 0 0, L_0x2d27b70; 1 drivers +v0x2af3850_0 .net *"_s14", 0 0, L_0x2d27d60; 1 drivers +v0x2af3930_0 .net *"_s16", 0 0, L_0x2d27f10; 1 drivers +v0x2af3a60_0 .net *"_s3", 0 0, L_0x2d27570; 1 drivers +v0x2af3b40_0 .net *"_s5", 0 0, L_0x2d276d0; 1 drivers +v0x2af3c20_0 .net *"_s6", 0 0, L_0x2d27900; 1 drivers +v0x2af3d00_0 .net "in", 3 0, L_0x2d28000; 1 drivers +v0x2af3e70_0 .net "ors", 1 0, L_0x2d27810; 1 drivers +v0x2af3f50_0 .net "out", 0 0, L_0x2d27cf0; 1 drivers +L_0x2d27570 .part L_0x2d28000, 0, 1; +L_0x2d276d0 .part L_0x2d28000, 1, 1; +L_0x2d27810 .concat8 [ 1 1 0 0], L_0x2d274b0, L_0x2d27900; +L_0x2d27a10 .part L_0x2d28000, 2, 1; +L_0x2d27b70 .part L_0x2d28000, 3, 1; +L_0x2d27d60 .part L_0x2d27810, 0, 1; +L_0x2d27f10 .part L_0x2d27810, 1, 1; +S_0x2af4070 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2af31a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12466f0/d .functor OR 1, L_0x1246760, L_0x12468c0, C4<0>, C4<0>; -L_0x12466f0 .delay 1 (30000,30000,30000) L_0x12466f0/d; -L_0x1246af0/d .functor OR 1, L_0x1246c00, L_0x1246d60, C4<0>, C4<0>; -L_0x1246af0 .delay 1 (30000,30000,30000) L_0x1246af0/d; -L_0x1246ee0/d .functor OR 1, L_0x1246f50, L_0x1247100, C4<0>, C4<0>; -L_0x1246ee0 .delay 1 (30000,30000,30000) L_0x1246ee0/d; -v0x102c460_0 .net *"_s0", 0 0, L_0x12466f0; 1 drivers -v0x102c560_0 .net *"_s10", 0 0, L_0x1246c00; 1 drivers -v0x102c640_0 .net *"_s12", 0 0, L_0x1246d60; 1 drivers -v0x102c700_0 .net *"_s14", 0 0, L_0x1246f50; 1 drivers -v0x102c7e0_0 .net *"_s16", 0 0, L_0x1247100; 1 drivers -v0x102c910_0 .net *"_s3", 0 0, L_0x1246760; 1 drivers -v0x102c9f0_0 .net *"_s5", 0 0, L_0x12468c0; 1 drivers -v0x102cad0_0 .net *"_s6", 0 0, L_0x1246af0; 1 drivers -v0x102cbb0_0 .net "in", 3 0, L_0x1247330; 1 drivers -v0x102cd20_0 .net "ors", 1 0, L_0x1246a00; 1 drivers -v0x102ce00_0 .net "out", 0 0, L_0x1246ee0; 1 drivers -L_0x1246760 .part L_0x1247330, 0, 1; -L_0x12468c0 .part L_0x1247330, 1, 1; -L_0x1246a00 .concat8 [ 1 1 0 0], L_0x12466f0, L_0x1246af0; -L_0x1246c00 .part L_0x1247330, 2, 1; -L_0x1246d60 .part L_0x1247330, 3, 1; -L_0x1246f50 .part L_0x1246a00, 0, 1; -L_0x1247100 .part L_0x1246a00, 1, 1; -S_0x102d710 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1026840; +L_0x2d28130/d .functor OR 1, L_0x2d281a0, L_0x2d28300, C4<0>, C4<0>; +L_0x2d28130 .delay 1 (30000,30000,30000) L_0x2d28130/d; +L_0x2d28530/d .functor OR 1, L_0x2d28640, L_0x2d287a0, C4<0>, C4<0>; +L_0x2d28530 .delay 1 (30000,30000,30000) L_0x2d28530/d; +L_0x2d28920/d .functor OR 1, L_0x2d28990, L_0x2d28b40, C4<0>, C4<0>; +L_0x2d28920 .delay 1 (30000,30000,30000) L_0x2d28920/d; +v0x2af4230_0 .net *"_s0", 0 0, L_0x2d28130; 1 drivers +v0x2af4330_0 .net *"_s10", 0 0, L_0x2d28640; 1 drivers +v0x2af4410_0 .net *"_s12", 0 0, L_0x2d287a0; 1 drivers +v0x2af44d0_0 .net *"_s14", 0 0, L_0x2d28990; 1 drivers +v0x2af45b0_0 .net *"_s16", 0 0, L_0x2d28b40; 1 drivers +v0x2af46e0_0 .net *"_s3", 0 0, L_0x2d281a0; 1 drivers +v0x2af47c0_0 .net *"_s5", 0 0, L_0x2d28300; 1 drivers +v0x2af48a0_0 .net *"_s6", 0 0, L_0x2d28530; 1 drivers +v0x2af4980_0 .net "in", 3 0, L_0x2d28d70; 1 drivers +v0x2af4af0_0 .net "ors", 1 0, L_0x2d28440; 1 drivers +v0x2af4bd0_0 .net "out", 0 0, L_0x2d28920; 1 drivers +L_0x2d281a0 .part L_0x2d28d70, 0, 1; +L_0x2d28300 .part L_0x2d28d70, 1, 1; +L_0x2d28440 .concat8 [ 1 1 0 0], L_0x2d28130, L_0x2d28530; +L_0x2d28640 .part L_0x2d28d70, 2, 1; +L_0x2d287a0 .part L_0x2d28d70, 3, 1; +L_0x2d28990 .part L_0x2d28440, 0, 1; +L_0x2d28b40 .part L_0x2d28440, 1, 1; +S_0x2af54e0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2aee610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1032d40_0 .net "ands", 7 0, L_0x1241990; 1 drivers -v0x1032e50_0 .net "in", 7 0, L_0x123fdf0; alias, 1 drivers -v0x1032f10_0 .net "out", 0 0, L_0x1243990; alias, 1 drivers -v0x1032fe0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x102d960 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x102d710; +v0x2afab10_0 .net "ands", 7 0, L_0x2d233d0; 1 drivers +v0x2afac20_0 .net "in", 7 0, L_0x2d213c0; alias, 1 drivers +v0x2aface0_0 .net "out", 0 0, L_0x2d253d0; alias, 1 drivers +v0x2afadb0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2af5730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2af54e0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10300a0_0 .net "A", 7 0, L_0x123fdf0; alias, 1 drivers -v0x10301a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0xffd2d0_0 .net *"_s0", 0 0, L_0x1240180; 1 drivers -v0xffd390_0 .net *"_s12", 0 0, L_0x1240b40; 1 drivers -v0x1030670_0 .net *"_s16", 0 0, L_0x1240ea0; 1 drivers -v0x1030730_0 .net *"_s20", 0 0, L_0x12412d0; 1 drivers -v0x1030810_0 .net *"_s24", 0 0, L_0x1241600; 1 drivers -v0x10308f0_0 .net *"_s28", 0 0, L_0x1241590; 1 drivers -v0x10309d0_0 .net *"_s4", 0 0, L_0x1240520; 1 drivers -v0x1030b40_0 .net *"_s8", 0 0, L_0x1240830; 1 drivers -v0x1030c20_0 .net "out", 7 0, L_0x1241990; alias, 1 drivers -L_0x1240290 .part L_0x123fdf0, 0, 1; -L_0x1240480 .part v0x12010b0_0, 0, 1; -L_0x12405e0 .part L_0x123fdf0, 1, 1; -L_0x1240740 .part v0x12010b0_0, 1, 1; -L_0x12408f0 .part L_0x123fdf0, 2, 1; -L_0x1240a50 .part v0x12010b0_0, 2, 1; -L_0x1240c00 .part L_0x123fdf0, 3, 1; -L_0x1240d60 .part v0x12010b0_0, 3, 1; -L_0x1240f60 .part L_0x123fdf0, 4, 1; -L_0x12411d0 .part v0x12010b0_0, 4, 1; -L_0x1241340 .part L_0x123fdf0, 5, 1; -L_0x12414a0 .part v0x12010b0_0, 5, 1; -L_0x12416c0 .part L_0x123fdf0, 6, 1; -L_0x1241820 .part v0x12010b0_0, 6, 1; -LS_0x1241990_0_0 .concat8 [ 1 1 1 1], L_0x1240180, L_0x1240520, L_0x1240830, L_0x1240b40; -LS_0x1241990_0_4 .concat8 [ 1 1 1 1], L_0x1240ea0, L_0x12412d0, L_0x1241600, L_0x1241590; -L_0x1241990 .concat8 [ 4 4 0 0], LS_0x1241990_0_0, LS_0x1241990_0_4; -L_0x1241d50 .part L_0x123fdf0, 7, 1; -L_0x1241f40 .part v0x12010b0_0, 7, 1; -S_0x102dba0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102ddb0 .param/l "i" 0 4 54, +C4<00>; -L_0x1240180/d .functor AND 1, L_0x1240290, L_0x1240480, C4<1>, C4<1>; -L_0x1240180 .delay 1 (30000,30000,30000) L_0x1240180/d; -v0x102de90_0 .net *"_s0", 0 0, L_0x1240290; 1 drivers -v0x102df70_0 .net *"_s1", 0 0, L_0x1240480; 1 drivers -S_0x102e050 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102e260 .param/l "i" 0 4 54, +C4<01>; -L_0x1240520/d .functor AND 1, L_0x12405e0, L_0x1240740, C4<1>, C4<1>; -L_0x1240520 .delay 1 (30000,30000,30000) L_0x1240520/d; -v0x102e320_0 .net *"_s0", 0 0, L_0x12405e0; 1 drivers -v0x102e400_0 .net *"_s1", 0 0, L_0x1240740; 1 drivers -S_0x102e4e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102e720 .param/l "i" 0 4 54, +C4<010>; -L_0x1240830/d .functor AND 1, L_0x12408f0, L_0x1240a50, C4<1>, C4<1>; -L_0x1240830 .delay 1 (30000,30000,30000) L_0x1240830/d; -v0x102e7c0_0 .net *"_s0", 0 0, L_0x12408f0; 1 drivers -v0x102e8a0_0 .net *"_s1", 0 0, L_0x1240a50; 1 drivers -S_0x102e980 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102eb90 .param/l "i" 0 4 54, +C4<011>; -L_0x1240b40/d .functor AND 1, L_0x1240c00, L_0x1240d60, C4<1>, C4<1>; -L_0x1240b40 .delay 1 (30000,30000,30000) L_0x1240b40/d; -v0x102ec50_0 .net *"_s0", 0 0, L_0x1240c00; 1 drivers -v0x102ed30_0 .net *"_s1", 0 0, L_0x1240d60; 1 drivers -S_0x102ee10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102f070 .param/l "i" 0 4 54, +C4<0100>; -L_0x1240ea0/d .functor AND 1, L_0x1240f60, L_0x12411d0, C4<1>, C4<1>; -L_0x1240ea0 .delay 1 (30000,30000,30000) L_0x1240ea0/d; -v0x102f130_0 .net *"_s0", 0 0, L_0x1240f60; 1 drivers -v0x102f210_0 .net *"_s1", 0 0, L_0x12411d0; 1 drivers -S_0x102f2f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102f500 .param/l "i" 0 4 54, +C4<0101>; -L_0x12412d0/d .functor AND 1, L_0x1241340, L_0x12414a0, C4<1>, C4<1>; -L_0x12412d0 .delay 1 (30000,30000,30000) L_0x12412d0/d; -v0x102f5c0_0 .net *"_s0", 0 0, L_0x1241340; 1 drivers -v0x102f6a0_0 .net *"_s1", 0 0, L_0x12414a0; 1 drivers -S_0x102f780 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102f990 .param/l "i" 0 4 54, +C4<0110>; -L_0x1241600/d .functor AND 1, L_0x12416c0, L_0x1241820, C4<1>, C4<1>; -L_0x1241600 .delay 1 (30000,30000,30000) L_0x1241600/d; -v0x102fa50_0 .net *"_s0", 0 0, L_0x12416c0; 1 drivers -v0x102fb30_0 .net *"_s1", 0 0, L_0x1241820; 1 drivers -S_0x102fc10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x102d960; - .timescale -9 -12; -P_0x102fe20 .param/l "i" 0 4 54, +C4<0111>; -L_0x1241590/d .functor AND 1, L_0x1241d50, L_0x1241f40, C4<1>, C4<1>; -L_0x1241590 .delay 1 (30000,30000,30000) L_0x1241590/d; -v0x102fee0_0 .net *"_s0", 0 0, L_0x1241d50; 1 drivers -v0x102ffc0_0 .net *"_s1", 0 0, L_0x1241f40; 1 drivers -S_0x1030d80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x102d710; +v0x2af7e70_0 .net "A", 7 0, L_0x2d213c0; alias, 1 drivers +v0x2af7f70_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ac2c00_0 .net *"_s0", 0 0, L_0x2d21c40; 1 drivers +v0x2ac2cc0_0 .net *"_s12", 0 0, L_0x2d22600; 1 drivers +v0x2af8440_0 .net *"_s16", 0 0, L_0x2d22960; 1 drivers +v0x2af8500_0 .net *"_s20", 0 0, L_0x2d22d90; 1 drivers +v0x2af85e0_0 .net *"_s24", 0 0, L_0x2d230c0; 1 drivers +v0x2af86c0_0 .net *"_s28", 0 0, L_0x2d23050; 1 drivers +v0x2af87a0_0 .net *"_s4", 0 0, L_0x2d21fe0; 1 drivers +v0x2af8910_0 .net *"_s8", 0 0, L_0x2d222f0; 1 drivers +v0x2af89f0_0 .net "out", 7 0, L_0x2d233d0; alias, 1 drivers +L_0x2d21d50 .part L_0x2d213c0, 0, 1; +L_0x2d21f40 .part v0x2cdd2e0_0, 0, 1; +L_0x2d220a0 .part L_0x2d213c0, 1, 1; +L_0x2d22200 .part v0x2cdd2e0_0, 1, 1; +L_0x2d223b0 .part L_0x2d213c0, 2, 1; +L_0x2d22510 .part v0x2cdd2e0_0, 2, 1; +L_0x2d226c0 .part L_0x2d213c0, 3, 1; +L_0x2d22820 .part v0x2cdd2e0_0, 3, 1; +L_0x2d22a20 .part L_0x2d213c0, 4, 1; +L_0x2d22c90 .part v0x2cdd2e0_0, 4, 1; +L_0x2d22e00 .part L_0x2d213c0, 5, 1; +L_0x2d22f60 .part v0x2cdd2e0_0, 5, 1; +L_0x2d23180 .part L_0x2d213c0, 6, 1; +L_0x2d232e0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d233d0_0_0 .concat8 [ 1 1 1 1], L_0x2d21c40, L_0x2d21fe0, L_0x2d222f0, L_0x2d22600; +LS_0x2d233d0_0_4 .concat8 [ 1 1 1 1], L_0x2d22960, L_0x2d22d90, L_0x2d230c0, L_0x2d23050; +L_0x2d233d0 .concat8 [ 4 4 0 0], LS_0x2d233d0_0_0, LS_0x2d233d0_0_4; +L_0x2d23790 .part L_0x2d213c0, 7, 1; +L_0x2d23980 .part v0x2cdd2e0_0, 7, 1; +S_0x2af5970 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af5b80 .param/l "i" 0 4 54, +C4<00>; +L_0x2d21c40/d .functor AND 1, L_0x2d21d50, L_0x2d21f40, C4<1>, C4<1>; +L_0x2d21c40 .delay 1 (30000,30000,30000) L_0x2d21c40/d; +v0x2af5c60_0 .net *"_s0", 0 0, L_0x2d21d50; 1 drivers +v0x2af5d40_0 .net *"_s1", 0 0, L_0x2d21f40; 1 drivers +S_0x2af5e20 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af6030 .param/l "i" 0 4 54, +C4<01>; +L_0x2d21fe0/d .functor AND 1, L_0x2d220a0, L_0x2d22200, C4<1>, C4<1>; +L_0x2d21fe0 .delay 1 (30000,30000,30000) L_0x2d21fe0/d; +v0x2af60f0_0 .net *"_s0", 0 0, L_0x2d220a0; 1 drivers +v0x2af61d0_0 .net *"_s1", 0 0, L_0x2d22200; 1 drivers +S_0x2af62b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af64f0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d222f0/d .functor AND 1, L_0x2d223b0, L_0x2d22510, C4<1>, C4<1>; +L_0x2d222f0 .delay 1 (30000,30000,30000) L_0x2d222f0/d; +v0x2af6590_0 .net *"_s0", 0 0, L_0x2d223b0; 1 drivers +v0x2af6670_0 .net *"_s1", 0 0, L_0x2d22510; 1 drivers +S_0x2af6750 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af6960 .param/l "i" 0 4 54, +C4<011>; +L_0x2d22600/d .functor AND 1, L_0x2d226c0, L_0x2d22820, C4<1>, C4<1>; +L_0x2d22600 .delay 1 (30000,30000,30000) L_0x2d22600/d; +v0x2af6a20_0 .net *"_s0", 0 0, L_0x2d226c0; 1 drivers +v0x2af6b00_0 .net *"_s1", 0 0, L_0x2d22820; 1 drivers +S_0x2af6be0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af6e40 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d22960/d .functor AND 1, L_0x2d22a20, L_0x2d22c90, C4<1>, C4<1>; +L_0x2d22960 .delay 1 (30000,30000,30000) L_0x2d22960/d; +v0x2af6f00_0 .net *"_s0", 0 0, L_0x2d22a20; 1 drivers +v0x2af6fe0_0 .net *"_s1", 0 0, L_0x2d22c90; 1 drivers +S_0x2af70c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af72d0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d22d90/d .functor AND 1, L_0x2d22e00, L_0x2d22f60, C4<1>, C4<1>; +L_0x2d22d90 .delay 1 (30000,30000,30000) L_0x2d22d90/d; +v0x2af7390_0 .net *"_s0", 0 0, L_0x2d22e00; 1 drivers +v0x2af7470_0 .net *"_s1", 0 0, L_0x2d22f60; 1 drivers +S_0x2af7550 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af7760 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d230c0/d .functor AND 1, L_0x2d23180, L_0x2d232e0, C4<1>, C4<1>; +L_0x2d230c0 .delay 1 (30000,30000,30000) L_0x2d230c0/d; +v0x2af7820_0 .net *"_s0", 0 0, L_0x2d23180; 1 drivers +v0x2af7900_0 .net *"_s1", 0 0, L_0x2d232e0; 1 drivers +S_0x2af79e0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2af5730; + .timescale -9 -12; +P_0x2af7bf0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d23050/d .functor AND 1, L_0x2d23790, L_0x2d23980, C4<1>, C4<1>; +L_0x2d23050 .delay 1 (30000,30000,30000) L_0x2d23050/d; +v0x2af7cb0_0 .net *"_s0", 0 0, L_0x2d23790; 1 drivers +v0x2af7d90_0 .net *"_s1", 0 0, L_0x2d23980; 1 drivers +S_0x2af8b50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2af54e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1243990/d .functor OR 1, L_0x1243a50, L_0x1243c00, C4<0>, C4<0>; -L_0x1243990 .delay 1 (30000,30000,30000) L_0x1243990/d; -v0x10328d0_0 .net *"_s10", 0 0, L_0x1243a50; 1 drivers -v0x10329b0_0 .net *"_s12", 0 0, L_0x1243c00; 1 drivers -v0x1032a90_0 .net "in", 7 0, L_0x1241990; alias, 1 drivers -v0x1032b60_0 .net "ors", 1 0, L_0x12437b0; 1 drivers -v0x1032c20_0 .net "out", 0 0, L_0x1243990; alias, 1 drivers -L_0x1242b80 .part L_0x1241990, 0, 4; -L_0x12437b0 .concat8 [ 1 1 0 0], L_0x1242870, L_0x12434a0; -L_0x12438f0 .part L_0x1241990, 4, 4; -L_0x1243a50 .part L_0x12437b0, 0, 1; -L_0x1243c00 .part L_0x12437b0, 1, 1; -S_0x1030f40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1030d80; +L_0x2d253d0/d .functor OR 1, L_0x2d25490, L_0x2d25640, C4<0>, C4<0>; +L_0x2d253d0 .delay 1 (30000,30000,30000) L_0x2d253d0/d; +v0x2afa6a0_0 .net *"_s10", 0 0, L_0x2d25490; 1 drivers +v0x2afa780_0 .net *"_s12", 0 0, L_0x2d25640; 1 drivers +v0x2afa860_0 .net "in", 7 0, L_0x2d233d0; alias, 1 drivers +v0x2afa930_0 .net "ors", 1 0, L_0x2d251f0; 1 drivers +v0x2afa9f0_0 .net "out", 0 0, L_0x2d253d0; alias, 1 drivers +L_0x2d245c0 .part L_0x2d233d0, 0, 4; +L_0x2d251f0 .concat8 [ 1 1 0 0], L_0x2d242b0, L_0x2d24ee0; +L_0x2d25330 .part L_0x2d233d0, 4, 4; +L_0x2d25490 .part L_0x2d251f0, 0, 1; +L_0x2d25640 .part L_0x2d251f0, 1, 1; +S_0x2af8d10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2af8b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1242030/d .functor OR 1, L_0x12420f0, L_0x1242250, C4<0>, C4<0>; -L_0x1242030 .delay 1 (30000,30000,30000) L_0x1242030/d; -L_0x1242480/d .functor OR 1, L_0x1242590, L_0x12426f0, C4<0>, C4<0>; -L_0x1242480 .delay 1 (30000,30000,30000) L_0x1242480/d; -L_0x1242870/d .functor OR 1, L_0x12428e0, L_0x1242a90, C4<0>, C4<0>; -L_0x1242870 .delay 1 (30000,30000,30000) L_0x1242870/d; -v0x1031190_0 .net *"_s0", 0 0, L_0x1242030; 1 drivers -v0x1031290_0 .net *"_s10", 0 0, L_0x1242590; 1 drivers -v0x1031370_0 .net *"_s12", 0 0, L_0x12426f0; 1 drivers -v0x1031430_0 .net *"_s14", 0 0, L_0x12428e0; 1 drivers -v0x1031510_0 .net *"_s16", 0 0, L_0x1242a90; 1 drivers -v0x1031640_0 .net *"_s3", 0 0, L_0x12420f0; 1 drivers -v0x1031720_0 .net *"_s5", 0 0, L_0x1242250; 1 drivers -v0x1031800_0 .net *"_s6", 0 0, L_0x1242480; 1 drivers -v0x10318e0_0 .net "in", 3 0, L_0x1242b80; 1 drivers -v0x1031a50_0 .net "ors", 1 0, L_0x1242390; 1 drivers -v0x1031b30_0 .net "out", 0 0, L_0x1242870; 1 drivers -L_0x12420f0 .part L_0x1242b80, 0, 1; -L_0x1242250 .part L_0x1242b80, 1, 1; -L_0x1242390 .concat8 [ 1 1 0 0], L_0x1242030, L_0x1242480; -L_0x1242590 .part L_0x1242b80, 2, 1; -L_0x12426f0 .part L_0x1242b80, 3, 1; -L_0x12428e0 .part L_0x1242390, 0, 1; -L_0x1242a90 .part L_0x1242390, 1, 1; -S_0x1031c50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1030d80; +L_0x2d23a70/d .functor OR 1, L_0x2d23b30, L_0x2d23c90, C4<0>, C4<0>; +L_0x2d23a70 .delay 1 (30000,30000,30000) L_0x2d23a70/d; +L_0x2d23ec0/d .functor OR 1, L_0x2d23fd0, L_0x2d24130, C4<0>, C4<0>; +L_0x2d23ec0 .delay 1 (30000,30000,30000) L_0x2d23ec0/d; +L_0x2d242b0/d .functor OR 1, L_0x2d24320, L_0x2d244d0, C4<0>, C4<0>; +L_0x2d242b0 .delay 1 (30000,30000,30000) L_0x2d242b0/d; +v0x2af8f60_0 .net *"_s0", 0 0, L_0x2d23a70; 1 drivers +v0x2af9060_0 .net *"_s10", 0 0, L_0x2d23fd0; 1 drivers +v0x2af9140_0 .net *"_s12", 0 0, L_0x2d24130; 1 drivers +v0x2af9200_0 .net *"_s14", 0 0, L_0x2d24320; 1 drivers +v0x2af92e0_0 .net *"_s16", 0 0, L_0x2d244d0; 1 drivers +v0x2af9410_0 .net *"_s3", 0 0, L_0x2d23b30; 1 drivers +v0x2af94f0_0 .net *"_s5", 0 0, L_0x2d23c90; 1 drivers +v0x2af95d0_0 .net *"_s6", 0 0, L_0x2d23ec0; 1 drivers +v0x2af96b0_0 .net "in", 3 0, L_0x2d245c0; 1 drivers +v0x2af9820_0 .net "ors", 1 0, L_0x2d23dd0; 1 drivers +v0x2af9900_0 .net "out", 0 0, L_0x2d242b0; 1 drivers +L_0x2d23b30 .part L_0x2d245c0, 0, 1; +L_0x2d23c90 .part L_0x2d245c0, 1, 1; +L_0x2d23dd0 .concat8 [ 1 1 0 0], L_0x2d23a70, L_0x2d23ec0; +L_0x2d23fd0 .part L_0x2d245c0, 2, 1; +L_0x2d24130 .part L_0x2d245c0, 3, 1; +L_0x2d24320 .part L_0x2d23dd0, 0, 1; +L_0x2d244d0 .part L_0x2d23dd0, 1, 1; +S_0x2af9a20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2af8b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1242cb0/d .functor OR 1, L_0x1242d20, L_0x1242e80, C4<0>, C4<0>; -L_0x1242cb0 .delay 1 (30000,30000,30000) L_0x1242cb0/d; -L_0x12430b0/d .functor OR 1, L_0x12431c0, L_0x1243320, C4<0>, C4<0>; -L_0x12430b0 .delay 1 (30000,30000,30000) L_0x12430b0/d; -L_0x12434a0/d .functor OR 1, L_0x1243510, L_0x12436c0, C4<0>, C4<0>; -L_0x12434a0 .delay 1 (30000,30000,30000) L_0x12434a0/d; -v0x1031e10_0 .net *"_s0", 0 0, L_0x1242cb0; 1 drivers -v0x1031f10_0 .net *"_s10", 0 0, L_0x12431c0; 1 drivers -v0x1031ff0_0 .net *"_s12", 0 0, L_0x1243320; 1 drivers -v0x10320b0_0 .net *"_s14", 0 0, L_0x1243510; 1 drivers -v0x1032190_0 .net *"_s16", 0 0, L_0x12436c0; 1 drivers -v0x10322c0_0 .net *"_s3", 0 0, L_0x1242d20; 1 drivers -v0x10323a0_0 .net *"_s5", 0 0, L_0x1242e80; 1 drivers -v0x1032480_0 .net *"_s6", 0 0, L_0x12430b0; 1 drivers -v0x1032560_0 .net "in", 3 0, L_0x12438f0; 1 drivers -v0x10326d0_0 .net "ors", 1 0, L_0x1242fc0; 1 drivers -v0x10327b0_0 .net "out", 0 0, L_0x12434a0; 1 drivers -L_0x1242d20 .part L_0x12438f0, 0, 1; -L_0x1242e80 .part L_0x12438f0, 1, 1; -L_0x1242fc0 .concat8 [ 1 1 0 0], L_0x1242cb0, L_0x12430b0; -L_0x12431c0 .part L_0x12438f0, 2, 1; -L_0x1243320 .part L_0x12438f0, 3, 1; -L_0x1243510 .part L_0x1242fc0, 0, 1; -L_0x12436c0 .part L_0x1242fc0, 1, 1; -S_0x10330c0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1026840; +L_0x2d246f0/d .functor OR 1, L_0x2d24760, L_0x2d248c0, C4<0>, C4<0>; +L_0x2d246f0 .delay 1 (30000,30000,30000) L_0x2d246f0/d; +L_0x2d24af0/d .functor OR 1, L_0x2d24c00, L_0x2d24d60, C4<0>, C4<0>; +L_0x2d24af0 .delay 1 (30000,30000,30000) L_0x2d24af0/d; +L_0x2d24ee0/d .functor OR 1, L_0x2d24f50, L_0x2d25100, C4<0>, C4<0>; +L_0x2d24ee0 .delay 1 (30000,30000,30000) L_0x2d24ee0/d; +v0x2af9be0_0 .net *"_s0", 0 0, L_0x2d246f0; 1 drivers +v0x2af9ce0_0 .net *"_s10", 0 0, L_0x2d24c00; 1 drivers +v0x2af9dc0_0 .net *"_s12", 0 0, L_0x2d24d60; 1 drivers +v0x2af9e80_0 .net *"_s14", 0 0, L_0x2d24f50; 1 drivers +v0x2af9f60_0 .net *"_s16", 0 0, L_0x2d25100; 1 drivers +v0x2afa090_0 .net *"_s3", 0 0, L_0x2d24760; 1 drivers +v0x2afa170_0 .net *"_s5", 0 0, L_0x2d248c0; 1 drivers +v0x2afa250_0 .net *"_s6", 0 0, L_0x2d24af0; 1 drivers +v0x2afa330_0 .net "in", 3 0, L_0x2d25330; 1 drivers +v0x2afa4a0_0 .net "ors", 1 0, L_0x2d24a00; 1 drivers +v0x2afa580_0 .net "out", 0 0, L_0x2d24ee0; 1 drivers +L_0x2d24760 .part L_0x2d25330, 0, 1; +L_0x2d248c0 .part L_0x2d25330, 1, 1; +L_0x2d24a00 .concat8 [ 1 1 0 0], L_0x2d246f0, L_0x2d24af0; +L_0x2d24c00 .part L_0x2d25330, 2, 1; +L_0x2d24d60 .part L_0x2d25330, 3, 1; +L_0x2d24f50 .part L_0x2d24a00, 0, 1; +L_0x2d25100 .part L_0x2d24a00, 1, 1; +S_0x2afae90 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2aee610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -3878,80 +4097,80 @@ S_0x10330c0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1026840; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x123f160/d .functor XNOR 1, L_0x1247830, L_0x1247aa0, C4<0>, C4<0>; -L_0x123f160 .delay 1 (20000,20000,20000) L_0x123f160/d; -L_0x123f3d0/d .functor AND 1, L_0x1247830, L_0x123e110, C4<1>, C4<1>; -L_0x123f3d0 .delay 1 (30000,30000,30000) L_0x123f3d0/d; -L_0x123f440/d .functor AND 1, L_0x123f160, L_0x123de70, C4<1>, C4<1>; -L_0x123f440 .delay 1 (30000,30000,30000) L_0x123f440/d; -L_0x123f5a0/d .functor OR 1, L_0x123f440, L_0x123f3d0, C4<0>, C4<0>; -L_0x123f5a0 .delay 1 (30000,30000,30000) L_0x123f5a0/d; -v0x1033370_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers -v0x1033460_0 .net "a_", 0 0, L_0x123dfb0; alias, 1 drivers -v0x1033520_0 .net "b", 0 0, L_0x1247aa0; alias, 1 drivers -v0x1033610_0 .net "b_", 0 0, L_0x123e110; alias, 1 drivers -v0x10336b0_0 .net "carryin", 0 0, L_0x123de70; alias, 1 drivers -v0x10337f0_0 .net "eq", 0 0, L_0x123f160; 1 drivers -v0x10338b0_0 .net "lt", 0 0, L_0x123f3d0; 1 drivers -v0x1033970_0 .net "out", 0 0, L_0x123f5a0; 1 drivers -v0x1033a30_0 .net "w0", 0 0, L_0x123f440; 1 drivers -S_0x1033c80 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1026840; +L_0x2d20200/d .functor XNOR 1, L_0x2d29270, L_0x2d294e0, C4<0>, C4<0>; +L_0x2d20200 .delay 1 (20000,20000,20000) L_0x2d20200/d; +L_0x2d20380/d .functor AND 1, L_0x2d29270, L_0x2d1eef0, C4<1>, C4<1>; +L_0x2d20380 .delay 1 (30000,30000,30000) L_0x2d20380/d; +L_0x2d204e0/d .functor AND 1, L_0x2d20200, L_0x2d1ec50, C4<1>, C4<1>; +L_0x2d204e0 .delay 1 (30000,30000,30000) L_0x2d204e0/d; +L_0x2d205f0/d .functor OR 1, L_0x2d204e0, L_0x2d20380, C4<0>, C4<0>; +L_0x2d205f0 .delay 1 (30000,30000,30000) L_0x2d205f0/d; +v0x2afb140_0 .net "a", 0 0, L_0x2d29270; alias, 1 drivers +v0x2afb230_0 .net "a_", 0 0, L_0x2d1ed90; alias, 1 drivers +v0x2afb2f0_0 .net "b", 0 0, L_0x2d294e0; alias, 1 drivers +v0x2afb3e0_0 .net "b_", 0 0, L_0x2d1eef0; alias, 1 drivers +v0x2afb480_0 .net "carryin", 0 0, L_0x2d1ec50; alias, 1 drivers +v0x2afb5c0_0 .net "eq", 0 0, L_0x2d20200; 1 drivers +v0x2afb680_0 .net "lt", 0 0, L_0x2d20380; 1 drivers +v0x2afb740_0 .net "out", 0 0, L_0x2d205f0; 1 drivers +v0x2afb800_0 .net "w0", 0 0, L_0x2d204e0; 1 drivers +S_0x2afba50 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2aee610; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x123ef40/d .functor OR 1, L_0x123ea90, L_0x1034ee0, C4<0>, C4<0>; -L_0x123ef40 .delay 1 (30000,30000,30000) L_0x123ef40/d; -v0x1034a70_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers -v0x1034bc0_0 .net "b", 0 0, L_0x123e110; alias, 1 drivers -v0x1034c80_0 .net "c1", 0 0, L_0x123ea90; 1 drivers -v0x1034d20_0 .net "c2", 0 0, L_0x1034ee0; 1 drivers -v0x1034df0_0 .net "carryin", 0 0, L_0x123de70; alias, 1 drivers -v0x1034f70_0 .net "carryout", 0 0, L_0x123ef40; 1 drivers -v0x1035010_0 .net "s1", 0 0, L_0x123e9d0; 1 drivers -v0x10350b0_0 .net "sum", 0 0, L_0x123ebf0; 1 drivers -S_0x1033ed0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1033c80; +L_0x2d1fde0/d .functor OR 1, L_0x2d1f8e0, L_0x2afccb0, C4<0>, C4<0>; +L_0x2d1fde0 .delay 1 (30000,30000,30000) L_0x2d1fde0/d; +v0x2afc840_0 .net "a", 0 0, L_0x2d29270; alias, 1 drivers +v0x2afc990_0 .net "b", 0 0, L_0x2d1eef0; alias, 1 drivers +v0x2afca50_0 .net "c1", 0 0, L_0x2d1f8e0; 1 drivers +v0x2afcaf0_0 .net "c2", 0 0, L_0x2afccb0; 1 drivers +v0x2afcbc0_0 .net "carryin", 0 0, L_0x2d1ec50; alias, 1 drivers +v0x2afcd40_0 .net "carryout", 0 0, L_0x2d1fde0; 1 drivers +v0x2afcde0_0 .net "s1", 0 0, L_0x2d1f820; 1 drivers +v0x2afce80_0 .net "sum", 0 0, L_0x2d1fa40; 1 drivers +S_0x2afbca0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2afba50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x123e9d0/d .functor XOR 1, L_0x1247830, L_0x123e110, C4<0>, C4<0>; -L_0x123e9d0 .delay 1 (30000,30000,30000) L_0x123e9d0/d; -L_0x123ea90/d .functor AND 1, L_0x1247830, L_0x123e110, C4<1>, C4<1>; -L_0x123ea90 .delay 1 (30000,30000,30000) L_0x123ea90/d; -v0x1034130_0 .net "a", 0 0, L_0x1247830; alias, 1 drivers -v0x10341f0_0 .net "b", 0 0, L_0x123e110; alias, 1 drivers -v0x10342b0_0 .net "carryout", 0 0, L_0x123ea90; alias, 1 drivers -v0x1034350_0 .net "sum", 0 0, L_0x123e9d0; alias, 1 drivers -S_0x1034480 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1033c80; +L_0x2d1f820/d .functor XOR 1, L_0x2d29270, L_0x2d1eef0, C4<0>, C4<0>; +L_0x2d1f820 .delay 1 (30000,30000,30000) L_0x2d1f820/d; +L_0x2d1f8e0/d .functor AND 1, L_0x2d29270, L_0x2d1eef0, C4<1>, C4<1>; +L_0x2d1f8e0 .delay 1 (30000,30000,30000) L_0x2d1f8e0/d; +v0x2afbf00_0 .net "a", 0 0, L_0x2d29270; alias, 1 drivers +v0x2afbfc0_0 .net "b", 0 0, L_0x2d1eef0; alias, 1 drivers +v0x2afc080_0 .net "carryout", 0 0, L_0x2d1f8e0; alias, 1 drivers +v0x2afc120_0 .net "sum", 0 0, L_0x2d1f820; alias, 1 drivers +S_0x2afc250 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2afba50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x123ebf0/d .functor XOR 1, L_0x123e9d0, L_0x123de70, C4<0>, C4<0>; -L_0x123ebf0 .delay 1 (30000,30000,30000) L_0x123ebf0/d; -L_0x1034ee0/d .functor AND 1, L_0x123e9d0, L_0x123de70, C4<1>, C4<1>; -L_0x1034ee0 .delay 1 (30000,30000,30000) L_0x1034ee0/d; -v0x10346e0_0 .net "a", 0 0, L_0x123e9d0; alias, 1 drivers -v0x10347b0_0 .net "b", 0 0, L_0x123de70; alias, 1 drivers -v0x1034850_0 .net "carryout", 0 0, L_0x1034ee0; alias, 1 drivers -v0x1034920_0 .net "sum", 0 0, L_0x123ebf0; alias, 1 drivers -S_0x10364d0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1026570; - .timescale -9 -12; -L_0x2b0ab3d056d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12478d0/d .functor OR 1, L_0x2b0ab3d056d8, L_0x2b0ab3d05720, C4<0>, C4<0>; -L_0x12478d0 .delay 1 (30000,30000,30000) L_0x12478d0/d; -v0x10366c0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d056d8; 1 drivers -v0x10367a0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05720; 1 drivers -S_0x1036880 .scope generate, "alu_slices[7]" "alu_slices[7]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1036a90 .param/l "i" 0 3 41, +C4<0111>; -S_0x1036b50 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1036880; +L_0x2d1fa40/d .functor XOR 1, L_0x2d1f820, L_0x2d1ec50, C4<0>, C4<0>; +L_0x2d1fa40 .delay 1 (30000,30000,30000) L_0x2d1fa40/d; +L_0x2afccb0/d .functor AND 1, L_0x2d1f820, L_0x2d1ec50, C4<1>, C4<1>; +L_0x2afccb0 .delay 1 (30000,30000,30000) L_0x2afccb0/d; +v0x2afc4b0_0 .net "a", 0 0, L_0x2d1f820; alias, 1 drivers +v0x2afc580_0 .net "b", 0 0, L_0x2d1ec50; alias, 1 drivers +v0x2afc620_0 .net "carryout", 0 0, L_0x2afccb0; alias, 1 drivers +v0x2afc6f0_0 .net "sum", 0 0, L_0x2d1fa40; alias, 1 drivers +S_0x2afef10 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2aee340; + .timescale -9 -12; +L_0x2ac6110b7a88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7ad0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d1f3a0/d .functor OR 1, L_0x2ac6110b7a88, L_0x2ac6110b7ad0, C4<0>, C4<0>; +L_0x2d1f3a0 .delay 1 (30000,30000,30000) L_0x2d1f3a0/d; +v0x2aff100_0 .net/2u *"_s0", 0 0, L_0x2ac6110b7a88; 1 drivers +v0x2aff1e0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b7ad0; 1 drivers +S_0x2aff2c0 .scope generate, "alu_slices[7]" "alu_slices[7]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2aff4d0 .param/l "i" 0 3 39, +C4<0111>; +S_0x2aff590 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2aff2c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -3960,445 +4179,476 @@ S_0x1036b50 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1036880; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1247da0/d .functor NOT 1, L_0x12515b0, C4<0>, C4<0>, C4<0>; -L_0x1247da0 .delay 1 (10000,10000,10000) L_0x1247da0/d; -L_0x1247eb0/d .functor NOT 1, L_0x1247c50, C4<0>, C4<0>, C4<0>; -L_0x1247eb0 .delay 1 (10000,10000,10000) L_0x1247eb0/d; -L_0x1248f00/d .functor XOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; -L_0x1248f00 .delay 1 (30000,30000,30000) L_0x1248f00/d; -L_0x2b0ab3d05768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d057b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12495b0/d .functor OR 1, L_0x2b0ab3d05768, L_0x2b0ab3d057b0, C4<0>, C4<0>; -L_0x12495b0 .delay 1 (30000,30000,30000) L_0x12495b0/d; -L_0x12497b0/d .functor AND 1, L_0x12515b0, L_0x1247c50, C4<1>, C4<1>; -L_0x12497b0 .delay 1 (30000,30000,30000) L_0x12497b0/d; -L_0x1249870/d .functor NAND 1, L_0x12515b0, L_0x1247c50, C4<1>, C4<1>; -L_0x1249870 .delay 1 (20000,20000,20000) L_0x1249870/d; -L_0x12499d0/d .functor XOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; -L_0x12499d0 .delay 1 (20000,20000,20000) L_0x12499d0/d; -L_0x1249e80/d .functor OR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; -L_0x1249e80 .delay 1 (30000,30000,30000) L_0x1249e80/d; -L_0x12514b0/d .functor NOT 1, L_0x124d710, C4<0>, C4<0>, C4<0>; -L_0x12514b0 .delay 1 (10000,10000,10000) L_0x12514b0/d; -v0x1045280_0 .net "A", 0 0, L_0x12515b0; 1 drivers -v0x1045340_0 .net "A_", 0 0, L_0x1247da0; 1 drivers -v0x1045400_0 .net "B", 0 0, L_0x1247c50; 1 drivers -v0x10454d0_0 .net "B_", 0 0, L_0x1247eb0; 1 drivers -v0x1045570_0 .net *"_s12", 0 0, L_0x12495b0; 1 drivers -v0x1045660_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05768; 1 drivers -v0x1045720_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d057b0; 1 drivers -v0x1045800_0 .net *"_s18", 0 0, L_0x12497b0; 1 drivers -v0x10458e0_0 .net *"_s20", 0 0, L_0x1249870; 1 drivers -v0x1045a50_0 .net *"_s22", 0 0, L_0x12499d0; 1 drivers -v0x1045b30_0 .net *"_s24", 0 0, L_0x1249e80; 1 drivers -o0x2b0ab3cb57f8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1045c10_0 name=_s30 -o0x2b0ab3cb5828 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1045cf0_0 name=_s32 -v0x1045dd0_0 .net *"_s8", 0 0, L_0x1248f00; 1 drivers -v0x1045eb0_0 .net "carryin", 0 0, L_0x12517d0; 1 drivers -v0x1045f50_0 .net "carryout", 0 0, L_0x1251150; 1 drivers -v0x1045ff0_0 .net "carryouts", 7 0, L_0x1353a50; 1 drivers -v0x10461a0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1046240_0 .net "result", 0 0, L_0x124d710; 1 drivers -v0x1046330_0 .net "results", 7 0, L_0x1249c50; 1 drivers -v0x1046440_0 .net "zero", 0 0, L_0x12514b0; 1 drivers -LS_0x1249c50_0_0 .concat8 [ 1 1 1 1], L_0x12483d0, L_0x1248a00, L_0x1248f00, L_0x12495b0; -LS_0x1249c50_0_4 .concat8 [ 1 1 1 1], L_0x12497b0, L_0x1249870, L_0x12499d0, L_0x1249e80; -L_0x1249c50 .concat8 [ 4 4 0 0], LS_0x1249c50_0_0, LS_0x1249c50_0_4; -LS_0x1353a50_0_0 .concat [ 1 1 1 1], L_0x1248680, L_0x1248da0, o0x2b0ab3cb57f8, L_0x1249400; -LS_0x1353a50_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb5828; -L_0x1353a50 .concat [ 4 4 0 0], LS_0x1353a50_0_0, LS_0x1353a50_0_4; -S_0x1036dd0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1036b50; +L_0x2d29790/d .functor NOT 1, L_0x2d33c00, C4<0>, C4<0>, C4<0>; +L_0x2d29790 .delay 1 (10000,10000,10000) L_0x2d29790/d; +L_0x2d298a0/d .functor NOT 1, L_0x2d29690, C4<0>, C4<0>, C4<0>; +L_0x2d298a0 .delay 1 (10000,10000,10000) L_0x2d298a0/d; +L_0x2d2a850/d .functor XOR 1, L_0x2d33c00, L_0x2d29690, C4<0>, C4<0>; +L_0x2d2a850 .delay 1 (30000,30000,30000) L_0x2d2a850/d; +L_0x2ac6110b7b18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7b60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d2a910/d .functor OR 1, L_0x2ac6110b7b18, L_0x2ac6110b7b60, C4<0>, C4<0>; +L_0x2d2a910 .delay 1 (30000,30000,30000) L_0x2d2a910/d; +L_0x2ac6110b7ba8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7bf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d2b0b0/d .functor OR 1, L_0x2ac6110b7ba8, L_0x2ac6110b7bf0, C4<0>, C4<0>; +L_0x2d2b0b0 .delay 1 (30000,30000,30000) L_0x2d2b0b0/d; +L_0x2d2b2b0/d .functor AND 1, L_0x2d33c00, L_0x2d29690, C4<1>, C4<1>; +L_0x2d2b2b0 .delay 1 (30000,30000,30000) L_0x2d2b2b0/d; +L_0x2ac6110b7c38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7c80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d2b370/d .functor OR 1, L_0x2ac6110b7c38, L_0x2ac6110b7c80, C4<0>, C4<0>; +L_0x2d2b370 .delay 1 (30000,30000,30000) L_0x2d2b370/d; +L_0x2d2b570/d .functor NAND 1, L_0x2d33c00, L_0x2d29690, C4<1>, C4<1>; +L_0x2d2b570 .delay 1 (20000,20000,20000) L_0x2d2b570/d; +L_0x2ac6110b7cc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7d10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d2b680/d .functor OR 1, L_0x2ac6110b7cc8, L_0x2ac6110b7d10, C4<0>, C4<0>; +L_0x2d2b680 .delay 1 (30000,30000,30000) L_0x2d2b680/d; +L_0x2d2b830/d .functor NOR 1, L_0x2d33c00, L_0x2d29690, C4<0>, C4<0>; +L_0x2d2b830 .delay 1 (20000,20000,20000) L_0x2d2b830/d; +L_0x2ac6110b7d58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7da0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d2bb00/d .functor OR 1, L_0x2ac6110b7d58, L_0x2ac6110b7da0, C4<0>, C4<0>; +L_0x2d2bb00 .delay 1 (30000,30000,30000) L_0x2d2bb00/d; +L_0x2d2bf00/d .functor OR 1, L_0x2d33c00, L_0x2d29690, C4<0>, C4<0>; +L_0x2d2bf00 .delay 1 (30000,30000,30000) L_0x2d2bf00/d; +L_0x2ac6110b7de8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7e30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d2c3a0/d .functor OR 1, L_0x2ac6110b7de8, L_0x2ac6110b7e30, C4<0>, C4<0>; +L_0x2d2c3a0 .delay 1 (30000,30000,30000) L_0x2d2c3a0/d; +L_0x2d33b00/d .functor NOT 1, L_0x2d2fd60, C4<0>, C4<0>, C4<0>; +L_0x2d33b00 .delay 1 (10000,10000,10000) L_0x2d33b00/d; +v0x2b0dcc0_0 .net "A", 0 0, L_0x2d33c00; 1 drivers +v0x2b0dd80_0 .net "A_", 0 0, L_0x2d29790; 1 drivers +v0x2b0de40_0 .net "B", 0 0, L_0x2d29690; 1 drivers +v0x2b0df10_0 .net "B_", 0 0, L_0x2d298a0; 1 drivers +v0x2b0dfb0_0 .net *"_s11", 0 0, L_0x2d2a910; 1 drivers +v0x2b0e0a0_0 .net/2s *"_s13", 0 0, L_0x2ac6110b7b18; 1 drivers +v0x2b0e160_0 .net/2s *"_s15", 0 0, L_0x2ac6110b7b60; 1 drivers +v0x2b0e240_0 .net *"_s19", 0 0, L_0x2d2b0b0; 1 drivers +v0x2b0e320_0 .net/2s *"_s21", 0 0, L_0x2ac6110b7ba8; 1 drivers +v0x2b0e490_0 .net/2s *"_s23", 0 0, L_0x2ac6110b7bf0; 1 drivers +v0x2b0e570_0 .net *"_s25", 0 0, L_0x2d2b2b0; 1 drivers +v0x2b0e650_0 .net *"_s28", 0 0, L_0x2d2b370; 1 drivers +v0x2b0e730_0 .net/2s *"_s30", 0 0, L_0x2ac6110b7c38; 1 drivers +v0x2b0e810_0 .net/2s *"_s32", 0 0, L_0x2ac6110b7c80; 1 drivers +v0x2b0e8f0_0 .net *"_s34", 0 0, L_0x2d2b570; 1 drivers +v0x2b0e9d0_0 .net *"_s37", 0 0, L_0x2d2b680; 1 drivers +v0x2b0eab0_0 .net/2s *"_s39", 0 0, L_0x2ac6110b7cc8; 1 drivers +v0x2b0ec60_0 .net/2s *"_s41", 0 0, L_0x2ac6110b7d10; 1 drivers +v0x2b0ed00_0 .net *"_s43", 0 0, L_0x2d2b830; 1 drivers +v0x2b0ede0_0 .net *"_s46", 0 0, L_0x2d2bb00; 1 drivers +v0x2b0eec0_0 .net/2s *"_s48", 0 0, L_0x2ac6110b7d58; 1 drivers +v0x2b0efa0_0 .net/2s *"_s50", 0 0, L_0x2ac6110b7da0; 1 drivers +v0x2b0f080_0 .net *"_s52", 0 0, L_0x2d2bf00; 1 drivers +v0x2b0f160_0 .net *"_s56", 0 0, L_0x2d2c3a0; 1 drivers +v0x2b0f240_0 .net/2s *"_s59", 0 0, L_0x2ac6110b7de8; 1 drivers +v0x2b0f320_0 .net/2s *"_s61", 0 0, L_0x2ac6110b7e30; 1 drivers +v0x2b0f400_0 .net *"_s8", 0 0, L_0x2d2a850; 1 drivers +v0x2b0f4e0_0 .net "carryin", 0 0, L_0x2d33e20; 1 drivers +v0x2b0f580_0 .net "carryout", 0 0, L_0x2d337a0; 1 drivers +v0x2b0f620_0 .net "carryouts", 7 0, L_0x2d2c010; 1 drivers +v0x2b0f730_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b0f7f0_0 .net "result", 0 0, L_0x2d2fd60; 1 drivers +v0x2b0f8e0_0 .net "results", 7 0, L_0x2d2bcd0; 1 drivers +v0x2b0ebc0_0 .net "zero", 0 0, L_0x2d33b00; 1 drivers +LS_0x2d2bcd0_0_0 .concat8 [ 1 1 1 1], L_0x2d29dc0, L_0x2d2a3a0, L_0x2d2a850, L_0x2d2b0b0; +LS_0x2d2bcd0_0_4 .concat8 [ 1 1 1 1], L_0x2d2b2b0, L_0x2d2b570, L_0x2d2b830, L_0x2d2bf00; +L_0x2d2bcd0 .concat8 [ 4 4 0 0], LS_0x2d2bcd0_0_0, LS_0x2d2bcd0_0_4; +LS_0x2d2c010_0_0 .concat8 [ 1 1 1 1], L_0x2d2a020, L_0x2d2a6f0, L_0x2d2a910, L_0x2d2af00; +LS_0x2d2c010_0_4 .concat8 [ 1 1 1 1], L_0x2d2b370, L_0x2d2b680, L_0x2d2bb00, L_0x2d2c3a0; +L_0x2d2c010 .concat8 [ 4 4 0 0], LS_0x2d2c010_0_0, LS_0x2d2c010_0_4; +S_0x2aff810 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2aff590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1248680/d .functor OR 1, L_0x1248160, L_0x1248520, C4<0>, C4<0>; -L_0x1248680 .delay 1 (30000,30000,30000) L_0x1248680/d; -v0x1037c00_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers -v0x1037cc0_0 .net "b", 0 0, L_0x1247c50; alias, 1 drivers -v0x1037d90_0 .net "c1", 0 0, L_0x1248160; 1 drivers -v0x1037e90_0 .net "c2", 0 0, L_0x1248520; 1 drivers -v0x1037f60_0 .net "carryin", 0 0, L_0x12517d0; alias, 1 drivers -v0x1038050_0 .net "carryout", 0 0, L_0x1248680; 1 drivers -v0x10380f0_0 .net "s1", 0 0, L_0x12480a0; 1 drivers -v0x10381e0_0 .net "sum", 0 0, L_0x12483d0; 1 drivers -S_0x1037040 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1036dd0; +L_0x2d2a020/d .functor OR 1, L_0x2d29b50, L_0x2d29f10, C4<0>, C4<0>; +L_0x2d2a020 .delay 1 (30000,30000,30000) L_0x2d2a020/d; +v0x2b00640_0 .net "a", 0 0, L_0x2d33c00; alias, 1 drivers +v0x2b00700_0 .net "b", 0 0, L_0x2d29690; alias, 1 drivers +v0x2b007d0_0 .net "c1", 0 0, L_0x2d29b50; 1 drivers +v0x2b008d0_0 .net "c2", 0 0, L_0x2d29f10; 1 drivers +v0x2b009a0_0 .net "carryin", 0 0, L_0x2d33e20; alias, 1 drivers +v0x2b00a90_0 .net "carryout", 0 0, L_0x2d2a020; 1 drivers +v0x2b00b30_0 .net "s1", 0 0, L_0x2d29a90; 1 drivers +v0x2b00c20_0 .net "sum", 0 0, L_0x2d29dc0; 1 drivers +S_0x2affa80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2aff810; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12480a0/d .functor XOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; -L_0x12480a0 .delay 1 (30000,30000,30000) L_0x12480a0/d; -L_0x1248160/d .functor AND 1, L_0x12515b0, L_0x1247c50, C4<1>, C4<1>; -L_0x1248160 .delay 1 (30000,30000,30000) L_0x1248160/d; -v0x10372a0_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers -v0x1037380_0 .net "b", 0 0, L_0x1247c50; alias, 1 drivers -v0x1037440_0 .net "carryout", 0 0, L_0x1248160; alias, 1 drivers -v0x10374e0_0 .net "sum", 0 0, L_0x12480a0; alias, 1 drivers -S_0x1037620 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1036dd0; +L_0x2d29a90/d .functor XOR 1, L_0x2d33c00, L_0x2d29690, C4<0>, C4<0>; +L_0x2d29a90 .delay 1 (30000,30000,30000) L_0x2d29a90/d; +L_0x2d29b50/d .functor AND 1, L_0x2d33c00, L_0x2d29690, C4<1>, C4<1>; +L_0x2d29b50 .delay 1 (30000,30000,30000) L_0x2d29b50/d; +v0x2affce0_0 .net "a", 0 0, L_0x2d33c00; alias, 1 drivers +v0x2affdc0_0 .net "b", 0 0, L_0x2d29690; alias, 1 drivers +v0x2affe80_0 .net "carryout", 0 0, L_0x2d29b50; alias, 1 drivers +v0x2afff20_0 .net "sum", 0 0, L_0x2d29a90; alias, 1 drivers +S_0x2b00060 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2aff810; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12483d0/d .functor XOR 1, L_0x12480a0, L_0x12517d0, C4<0>, C4<0>; -L_0x12483d0 .delay 1 (30000,30000,30000) L_0x12483d0/d; -L_0x1248520/d .functor AND 1, L_0x12480a0, L_0x12517d0, C4<1>, C4<1>; -L_0x1248520 .delay 1 (30000,30000,30000) L_0x1248520/d; -v0x1037880_0 .net "a", 0 0, L_0x12480a0; alias, 1 drivers -v0x1037920_0 .net "b", 0 0, L_0x12517d0; alias, 1 drivers -v0x10379c0_0 .net "carryout", 0 0, L_0x1248520; alias, 1 drivers -v0x1037a90_0 .net "sum", 0 0, L_0x12483d0; alias, 1 drivers -S_0x10382b0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1036b50; +L_0x2d29dc0/d .functor XOR 1, L_0x2d29a90, L_0x2d33e20, C4<0>, C4<0>; +L_0x2d29dc0 .delay 1 (30000,30000,30000) L_0x2d29dc0/d; +L_0x2d29f10/d .functor AND 1, L_0x2d29a90, L_0x2d33e20, C4<1>, C4<1>; +L_0x2d29f10 .delay 1 (30000,30000,30000) L_0x2d29f10/d; +v0x2b002c0_0 .net "a", 0 0, L_0x2d29a90; alias, 1 drivers +v0x2b00360_0 .net "b", 0 0, L_0x2d33e20; alias, 1 drivers +v0x2b00400_0 .net "carryout", 0 0, L_0x2d29f10; alias, 1 drivers +v0x2b004d0_0 .net "sum", 0 0, L_0x2d29dc0; alias, 1 drivers +S_0x2b00cf0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2aff590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x103d6a0_0 .net "ands", 7 0, L_0x124f150; 1 drivers -v0x103d7b0_0 .net "in", 7 0, L_0x1353a50; alias, 1 drivers -v0x103d870_0 .net "out", 0 0, L_0x1251150; alias, 1 drivers -v0x103d940_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10384d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10382b0; +v0x2b060e0_0 .net "ands", 7 0, L_0x2d317a0; 1 drivers +v0x2b061f0_0 .net "in", 7 0, L_0x2d2c010; alias, 1 drivers +v0x2b062b0_0 .net "out", 0 0, L_0x2d337a0; alias, 1 drivers +v0x2b06380_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b00f10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b00cf0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x103ac00_0 .net "A", 7 0, L_0x1353a50; alias, 1 drivers -v0x103ad00_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x103adc0_0 .net *"_s0", 0 0, L_0x124da70; 1 drivers -v0x103ae80_0 .net *"_s12", 0 0, L_0x124e3e0; 1 drivers -v0x103af60_0 .net *"_s16", 0 0, L_0x124e740; 1 drivers -v0x103b090_0 .net *"_s20", 0 0, L_0x124ea50; 1 drivers -v0x103b170_0 .net *"_s24", 0 0, L_0x124ee40; 1 drivers -v0x103b250_0 .net *"_s28", 0 0, L_0x124edd0; 1 drivers -v0x103b330_0 .net *"_s4", 0 0, L_0x124dd80; 1 drivers -v0x103b4a0_0 .net *"_s8", 0 0, L_0x124e0d0; 1 drivers -v0x103b580_0 .net "out", 7 0, L_0x124f150; alias, 1 drivers -L_0x124db30 .part L_0x1353a50, 0, 1; -L_0x124dc90 .part v0x12010b0_0, 0, 1; -L_0x124de40 .part L_0x1353a50, 1, 1; -L_0x124e030 .part v0x12010b0_0, 1, 1; -L_0x124e190 .part L_0x1353a50, 2, 1; -L_0x124e2f0 .part v0x12010b0_0, 2, 1; -L_0x124e4a0 .part L_0x1353a50, 3, 1; -L_0x124e600 .part v0x12010b0_0, 3, 1; -L_0x124e800 .part L_0x1353a50, 4, 1; -L_0x124e960 .part v0x12010b0_0, 4, 1; -L_0x124eac0 .part L_0x1353a50, 5, 1; -L_0x124ed30 .part v0x12010b0_0, 5, 1; -L_0x124ef00 .part L_0x1353a50, 6, 1; -L_0x124f060 .part v0x12010b0_0, 6, 1; -LS_0x124f150_0_0 .concat8 [ 1 1 1 1], L_0x124da70, L_0x124dd80, L_0x124e0d0, L_0x124e3e0; -LS_0x124f150_0_4 .concat8 [ 1 1 1 1], L_0x124e740, L_0x124ea50, L_0x124ee40, L_0x124edd0; -L_0x124f150 .concat8 [ 4 4 0 0], LS_0x124f150_0_0, LS_0x124f150_0_4; -L_0x124f510 .part L_0x1353a50, 7, 1; -L_0x124f700 .part v0x12010b0_0, 7, 1; -S_0x1038730 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x1038940 .param/l "i" 0 4 54, +C4<00>; -L_0x124da70/d .functor AND 1, L_0x124db30, L_0x124dc90, C4<1>, C4<1>; -L_0x124da70 .delay 1 (30000,30000,30000) L_0x124da70/d; -v0x1038a20_0 .net *"_s0", 0 0, L_0x124db30; 1 drivers -v0x1038b00_0 .net *"_s1", 0 0, L_0x124dc90; 1 drivers -S_0x1038be0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x1038df0 .param/l "i" 0 4 54, +C4<01>; -L_0x124dd80/d .functor AND 1, L_0x124de40, L_0x124e030, C4<1>, C4<1>; -L_0x124dd80 .delay 1 (30000,30000,30000) L_0x124dd80/d; -v0x1038eb0_0 .net *"_s0", 0 0, L_0x124de40; 1 drivers -v0x1038f90_0 .net *"_s1", 0 0, L_0x124e030; 1 drivers -S_0x1039070 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x1039280 .param/l "i" 0 4 54, +C4<010>; -L_0x124e0d0/d .functor AND 1, L_0x124e190, L_0x124e2f0, C4<1>, C4<1>; -L_0x124e0d0 .delay 1 (30000,30000,30000) L_0x124e0d0/d; -v0x1039320_0 .net *"_s0", 0 0, L_0x124e190; 1 drivers -v0x1039400_0 .net *"_s1", 0 0, L_0x124e2f0; 1 drivers -S_0x10394e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x10396f0 .param/l "i" 0 4 54, +C4<011>; -L_0x124e3e0/d .functor AND 1, L_0x124e4a0, L_0x124e600, C4<1>, C4<1>; -L_0x124e3e0 .delay 1 (30000,30000,30000) L_0x124e3e0/d; -v0x10397b0_0 .net *"_s0", 0 0, L_0x124e4a0; 1 drivers -v0x1039890_0 .net *"_s1", 0 0, L_0x124e600; 1 drivers -S_0x1039970 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x1039bd0 .param/l "i" 0 4 54, +C4<0100>; -L_0x124e740/d .functor AND 1, L_0x124e800, L_0x124e960, C4<1>, C4<1>; -L_0x124e740 .delay 1 (30000,30000,30000) L_0x124e740/d; -v0x1039c90_0 .net *"_s0", 0 0, L_0x124e800; 1 drivers -v0x1039d70_0 .net *"_s1", 0 0, L_0x124e960; 1 drivers -S_0x1039e50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x103a060 .param/l "i" 0 4 54, +C4<0101>; -L_0x124ea50/d .functor AND 1, L_0x124eac0, L_0x124ed30, C4<1>, C4<1>; -L_0x124ea50 .delay 1 (30000,30000,30000) L_0x124ea50/d; -v0x103a120_0 .net *"_s0", 0 0, L_0x124eac0; 1 drivers -v0x103a200_0 .net *"_s1", 0 0, L_0x124ed30; 1 drivers -S_0x103a2e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x103a4f0 .param/l "i" 0 4 54, +C4<0110>; -L_0x124ee40/d .functor AND 1, L_0x124ef00, L_0x124f060, C4<1>, C4<1>; -L_0x124ee40 .delay 1 (30000,30000,30000) L_0x124ee40/d; -v0x103a5b0_0 .net *"_s0", 0 0, L_0x124ef00; 1 drivers -v0x103a690_0 .net *"_s1", 0 0, L_0x124f060; 1 drivers -S_0x103a770 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10384d0; - .timescale -9 -12; -P_0x103a980 .param/l "i" 0 4 54, +C4<0111>; -L_0x124edd0/d .functor AND 1, L_0x124f510, L_0x124f700, C4<1>, C4<1>; -L_0x124edd0 .delay 1 (30000,30000,30000) L_0x124edd0/d; -v0x103aa40_0 .net *"_s0", 0 0, L_0x124f510; 1 drivers -v0x103ab20_0 .net *"_s1", 0 0, L_0x124f700; 1 drivers -S_0x103b6e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10382b0; +v0x2b03640_0 .net "A", 7 0, L_0x2d2c010; alias, 1 drivers +v0x2b03740_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b03800_0 .net *"_s0", 0 0, L_0x2d300c0; 1 drivers +v0x2b038c0_0 .net *"_s12", 0 0, L_0x2d30a30; 1 drivers +v0x2b039a0_0 .net *"_s16", 0 0, L_0x2d30d90; 1 drivers +v0x2b03ad0_0 .net *"_s20", 0 0, L_0x2d31160; 1 drivers +v0x2b03bb0_0 .net *"_s24", 0 0, L_0x2d31490; 1 drivers +v0x2b03c90_0 .net *"_s28", 0 0, L_0x2d31420; 1 drivers +v0x2b03d70_0 .net *"_s4", 0 0, L_0x2d30410; 1 drivers +v0x2b03ee0_0 .net *"_s8", 0 0, L_0x2d30720; 1 drivers +v0x2b03fc0_0 .net "out", 7 0, L_0x2d317a0; alias, 1 drivers +L_0x2d30180 .part L_0x2d2c010, 0, 1; +L_0x2d30370 .part v0x2cdd2e0_0, 0, 1; +L_0x2d304d0 .part L_0x2d2c010, 1, 1; +L_0x2d30630 .part v0x2cdd2e0_0, 1, 1; +L_0x2d307e0 .part L_0x2d2c010, 2, 1; +L_0x2d30940 .part v0x2cdd2e0_0, 2, 1; +L_0x2d30af0 .part L_0x2d2c010, 3, 1; +L_0x2d30c50 .part v0x2cdd2e0_0, 3, 1; +L_0x2d30e50 .part L_0x2d2c010, 4, 1; +L_0x2d310c0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d311d0 .part L_0x2d2c010, 5, 1; +L_0x2d31330 .part v0x2cdd2e0_0, 5, 1; +L_0x2d31550 .part L_0x2d2c010, 6, 1; +L_0x2d316b0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d317a0_0_0 .concat8 [ 1 1 1 1], L_0x2d300c0, L_0x2d30410, L_0x2d30720, L_0x2d30a30; +LS_0x2d317a0_0_4 .concat8 [ 1 1 1 1], L_0x2d30d90, L_0x2d31160, L_0x2d31490, L_0x2d31420; +L_0x2d317a0 .concat8 [ 4 4 0 0], LS_0x2d317a0_0_0, LS_0x2d317a0_0_4; +L_0x2d31b60 .part L_0x2d2c010, 7, 1; +L_0x2d31d50 .part v0x2cdd2e0_0, 7, 1; +S_0x2b01170 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b01380 .param/l "i" 0 4 54, +C4<00>; +L_0x2d300c0/d .functor AND 1, L_0x2d30180, L_0x2d30370, C4<1>, C4<1>; +L_0x2d300c0 .delay 1 (30000,30000,30000) L_0x2d300c0/d; +v0x2b01460_0 .net *"_s0", 0 0, L_0x2d30180; 1 drivers +v0x2b01540_0 .net *"_s1", 0 0, L_0x2d30370; 1 drivers +S_0x2b01620 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b01830 .param/l "i" 0 4 54, +C4<01>; +L_0x2d30410/d .functor AND 1, L_0x2d304d0, L_0x2d30630, C4<1>, C4<1>; +L_0x2d30410 .delay 1 (30000,30000,30000) L_0x2d30410/d; +v0x2b018f0_0 .net *"_s0", 0 0, L_0x2d304d0; 1 drivers +v0x2b019d0_0 .net *"_s1", 0 0, L_0x2d30630; 1 drivers +S_0x2b01ab0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b01cc0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d30720/d .functor AND 1, L_0x2d307e0, L_0x2d30940, C4<1>, C4<1>; +L_0x2d30720 .delay 1 (30000,30000,30000) L_0x2d30720/d; +v0x2b01d60_0 .net *"_s0", 0 0, L_0x2d307e0; 1 drivers +v0x2b01e40_0 .net *"_s1", 0 0, L_0x2d30940; 1 drivers +S_0x2b01f20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b02130 .param/l "i" 0 4 54, +C4<011>; +L_0x2d30a30/d .functor AND 1, L_0x2d30af0, L_0x2d30c50, C4<1>, C4<1>; +L_0x2d30a30 .delay 1 (30000,30000,30000) L_0x2d30a30/d; +v0x2b021f0_0 .net *"_s0", 0 0, L_0x2d30af0; 1 drivers +v0x2b022d0_0 .net *"_s1", 0 0, L_0x2d30c50; 1 drivers +S_0x2b023b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b02610 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d30d90/d .functor AND 1, L_0x2d30e50, L_0x2d310c0, C4<1>, C4<1>; +L_0x2d30d90 .delay 1 (30000,30000,30000) L_0x2d30d90/d; +v0x2b026d0_0 .net *"_s0", 0 0, L_0x2d30e50; 1 drivers +v0x2b027b0_0 .net *"_s1", 0 0, L_0x2d310c0; 1 drivers +S_0x2b02890 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b02aa0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d31160/d .functor AND 1, L_0x2d311d0, L_0x2d31330, C4<1>, C4<1>; +L_0x2d31160 .delay 1 (30000,30000,30000) L_0x2d31160/d; +v0x2b02b60_0 .net *"_s0", 0 0, L_0x2d311d0; 1 drivers +v0x2b02c40_0 .net *"_s1", 0 0, L_0x2d31330; 1 drivers +S_0x2b02d20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b02f30 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d31490/d .functor AND 1, L_0x2d31550, L_0x2d316b0, C4<1>, C4<1>; +L_0x2d31490 .delay 1 (30000,30000,30000) L_0x2d31490/d; +v0x2b02ff0_0 .net *"_s0", 0 0, L_0x2d31550; 1 drivers +v0x2b030d0_0 .net *"_s1", 0 0, L_0x2d316b0; 1 drivers +S_0x2b031b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b00f10; + .timescale -9 -12; +P_0x2b033c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d31420/d .functor AND 1, L_0x2d31b60, L_0x2d31d50, C4<1>, C4<1>; +L_0x2d31420 .delay 1 (30000,30000,30000) L_0x2d31420/d; +v0x2b03480_0 .net *"_s0", 0 0, L_0x2d31b60; 1 drivers +v0x2b03560_0 .net *"_s1", 0 0, L_0x2d31d50; 1 drivers +S_0x2b04120 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b00cf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1251150/d .functor OR 1, L_0x1251210, L_0x12513c0, C4<0>, C4<0>; -L_0x1251150 .delay 1 (30000,30000,30000) L_0x1251150/d; -v0x103d230_0 .net *"_s10", 0 0, L_0x1251210; 1 drivers -v0x103d310_0 .net *"_s12", 0 0, L_0x12513c0; 1 drivers -v0x103d3f0_0 .net "in", 7 0, L_0x124f150; alias, 1 drivers -v0x103d4c0_0 .net "ors", 1 0, L_0x1250f70; 1 drivers -v0x103d580_0 .net "out", 0 0, L_0x1251150; alias, 1 drivers -L_0x1250340 .part L_0x124f150, 0, 4; -L_0x1250f70 .concat8 [ 1 1 0 0], L_0x1250030, L_0x1250c60; -L_0x12510b0 .part L_0x124f150, 4, 4; -L_0x1251210 .part L_0x1250f70, 0, 1; -L_0x12513c0 .part L_0x1250f70, 1, 1; -S_0x103b8a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x103b6e0; +L_0x2d337a0/d .functor OR 1, L_0x2d33860, L_0x2d33a10, C4<0>, C4<0>; +L_0x2d337a0 .delay 1 (30000,30000,30000) L_0x2d337a0/d; +v0x2b05c70_0 .net *"_s10", 0 0, L_0x2d33860; 1 drivers +v0x2b05d50_0 .net *"_s12", 0 0, L_0x2d33a10; 1 drivers +v0x2b05e30_0 .net "in", 7 0, L_0x2d317a0; alias, 1 drivers +v0x2b05f00_0 .net "ors", 1 0, L_0x2d335c0; 1 drivers +v0x2b05fc0_0 .net "out", 0 0, L_0x2d337a0; alias, 1 drivers +L_0x2d32990 .part L_0x2d317a0, 0, 4; +L_0x2d335c0 .concat8 [ 1 1 0 0], L_0x2d32680, L_0x2d332b0; +L_0x2d33700 .part L_0x2d317a0, 4, 4; +L_0x2d33860 .part L_0x2d335c0, 0, 1; +L_0x2d33a10 .part L_0x2d335c0, 1, 1; +S_0x2b042e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b04120; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x124f7f0/d .functor OR 1, L_0x124f8b0, L_0x124fa10, C4<0>, C4<0>; -L_0x124f7f0 .delay 1 (30000,30000,30000) L_0x124f7f0/d; -L_0x124fc40/d .functor OR 1, L_0x124fd50, L_0x124feb0, C4<0>, C4<0>; -L_0x124fc40 .delay 1 (30000,30000,30000) L_0x124fc40/d; -L_0x1250030/d .functor OR 1, L_0x12500a0, L_0x1250250, C4<0>, C4<0>; -L_0x1250030 .delay 1 (30000,30000,30000) L_0x1250030/d; -v0x103baf0_0 .net *"_s0", 0 0, L_0x124f7f0; 1 drivers -v0x103bbf0_0 .net *"_s10", 0 0, L_0x124fd50; 1 drivers -v0x103bcd0_0 .net *"_s12", 0 0, L_0x124feb0; 1 drivers -v0x103bd90_0 .net *"_s14", 0 0, L_0x12500a0; 1 drivers -v0x103be70_0 .net *"_s16", 0 0, L_0x1250250; 1 drivers -v0x103bfa0_0 .net *"_s3", 0 0, L_0x124f8b0; 1 drivers -v0x103c080_0 .net *"_s5", 0 0, L_0x124fa10; 1 drivers -v0x103c160_0 .net *"_s6", 0 0, L_0x124fc40; 1 drivers -v0x103c240_0 .net "in", 3 0, L_0x1250340; 1 drivers -v0x103c3b0_0 .net "ors", 1 0, L_0x124fb50; 1 drivers -v0x103c490_0 .net "out", 0 0, L_0x1250030; 1 drivers -L_0x124f8b0 .part L_0x1250340, 0, 1; -L_0x124fa10 .part L_0x1250340, 1, 1; -L_0x124fb50 .concat8 [ 1 1 0 0], L_0x124f7f0, L_0x124fc40; -L_0x124fd50 .part L_0x1250340, 2, 1; -L_0x124feb0 .part L_0x1250340, 3, 1; -L_0x12500a0 .part L_0x124fb50, 0, 1; -L_0x1250250 .part L_0x124fb50, 1, 1; -S_0x103c5b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x103b6e0; +L_0x2d31e40/d .functor OR 1, L_0x2d31f00, L_0x2d32060, C4<0>, C4<0>; +L_0x2d31e40 .delay 1 (30000,30000,30000) L_0x2d31e40/d; +L_0x2d32290/d .functor OR 1, L_0x2d323a0, L_0x2d32500, C4<0>, C4<0>; +L_0x2d32290 .delay 1 (30000,30000,30000) L_0x2d32290/d; +L_0x2d32680/d .functor OR 1, L_0x2d326f0, L_0x2d328a0, C4<0>, C4<0>; +L_0x2d32680 .delay 1 (30000,30000,30000) L_0x2d32680/d; +v0x2b04530_0 .net *"_s0", 0 0, L_0x2d31e40; 1 drivers +v0x2b04630_0 .net *"_s10", 0 0, L_0x2d323a0; 1 drivers +v0x2b04710_0 .net *"_s12", 0 0, L_0x2d32500; 1 drivers +v0x2b047d0_0 .net *"_s14", 0 0, L_0x2d326f0; 1 drivers +v0x2b048b0_0 .net *"_s16", 0 0, L_0x2d328a0; 1 drivers +v0x2b049e0_0 .net *"_s3", 0 0, L_0x2d31f00; 1 drivers +v0x2b04ac0_0 .net *"_s5", 0 0, L_0x2d32060; 1 drivers +v0x2b04ba0_0 .net *"_s6", 0 0, L_0x2d32290; 1 drivers +v0x2b04c80_0 .net "in", 3 0, L_0x2d32990; 1 drivers +v0x2b04df0_0 .net "ors", 1 0, L_0x2d321a0; 1 drivers +v0x2b04ed0_0 .net "out", 0 0, L_0x2d32680; 1 drivers +L_0x2d31f00 .part L_0x2d32990, 0, 1; +L_0x2d32060 .part L_0x2d32990, 1, 1; +L_0x2d321a0 .concat8 [ 1 1 0 0], L_0x2d31e40, L_0x2d32290; +L_0x2d323a0 .part L_0x2d32990, 2, 1; +L_0x2d32500 .part L_0x2d32990, 3, 1; +L_0x2d326f0 .part L_0x2d321a0, 0, 1; +L_0x2d328a0 .part L_0x2d321a0, 1, 1; +S_0x2b04ff0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b04120; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1250470/d .functor OR 1, L_0x12504e0, L_0x1250640, C4<0>, C4<0>; -L_0x1250470 .delay 1 (30000,30000,30000) L_0x1250470/d; -L_0x1250870/d .functor OR 1, L_0x1250980, L_0x1250ae0, C4<0>, C4<0>; -L_0x1250870 .delay 1 (30000,30000,30000) L_0x1250870/d; -L_0x1250c60/d .functor OR 1, L_0x1250cd0, L_0x1250e80, C4<0>, C4<0>; -L_0x1250c60 .delay 1 (30000,30000,30000) L_0x1250c60/d; -v0x103c770_0 .net *"_s0", 0 0, L_0x1250470; 1 drivers -v0x103c870_0 .net *"_s10", 0 0, L_0x1250980; 1 drivers -v0x103c950_0 .net *"_s12", 0 0, L_0x1250ae0; 1 drivers -v0x103ca10_0 .net *"_s14", 0 0, L_0x1250cd0; 1 drivers -v0x103caf0_0 .net *"_s16", 0 0, L_0x1250e80; 1 drivers -v0x103cc20_0 .net *"_s3", 0 0, L_0x12504e0; 1 drivers -v0x103cd00_0 .net *"_s5", 0 0, L_0x1250640; 1 drivers -v0x103cde0_0 .net *"_s6", 0 0, L_0x1250870; 1 drivers -v0x103cec0_0 .net "in", 3 0, L_0x12510b0; 1 drivers -v0x103d030_0 .net "ors", 1 0, L_0x1250780; 1 drivers -v0x103d110_0 .net "out", 0 0, L_0x1250c60; 1 drivers -L_0x12504e0 .part L_0x12510b0, 0, 1; -L_0x1250640 .part L_0x12510b0, 1, 1; -L_0x1250780 .concat8 [ 1 1 0 0], L_0x1250470, L_0x1250870; -L_0x1250980 .part L_0x12510b0, 2, 1; -L_0x1250ae0 .part L_0x12510b0, 3, 1; -L_0x1250cd0 .part L_0x1250780, 0, 1; -L_0x1250e80 .part L_0x1250780, 1, 1; -S_0x103da20 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1036b50; +L_0x2d32ac0/d .functor OR 1, L_0x2d32b30, L_0x2d32c90, C4<0>, C4<0>; +L_0x2d32ac0 .delay 1 (30000,30000,30000) L_0x2d32ac0/d; +L_0x2d32ec0/d .functor OR 1, L_0x2d32fd0, L_0x2d33130, C4<0>, C4<0>; +L_0x2d32ec0 .delay 1 (30000,30000,30000) L_0x2d32ec0/d; +L_0x2d332b0/d .functor OR 1, L_0x2d33320, L_0x2d334d0, C4<0>, C4<0>; +L_0x2d332b0 .delay 1 (30000,30000,30000) L_0x2d332b0/d; +v0x2b051b0_0 .net *"_s0", 0 0, L_0x2d32ac0; 1 drivers +v0x2b052b0_0 .net *"_s10", 0 0, L_0x2d32fd0; 1 drivers +v0x2b05390_0 .net *"_s12", 0 0, L_0x2d33130; 1 drivers +v0x2b05450_0 .net *"_s14", 0 0, L_0x2d33320; 1 drivers +v0x2b05530_0 .net *"_s16", 0 0, L_0x2d334d0; 1 drivers +v0x2b05660_0 .net *"_s3", 0 0, L_0x2d32b30; 1 drivers +v0x2b05740_0 .net *"_s5", 0 0, L_0x2d32c90; 1 drivers +v0x2b05820_0 .net *"_s6", 0 0, L_0x2d32ec0; 1 drivers +v0x2b05900_0 .net "in", 3 0, L_0x2d33700; 1 drivers +v0x2b05a70_0 .net "ors", 1 0, L_0x2d32dd0; 1 drivers +v0x2b05b50_0 .net "out", 0 0, L_0x2d332b0; 1 drivers +L_0x2d32b30 .part L_0x2d33700, 0, 1; +L_0x2d32c90 .part L_0x2d33700, 1, 1; +L_0x2d32dd0 .concat8 [ 1 1 0 0], L_0x2d32ac0, L_0x2d32ec0; +L_0x2d32fd0 .part L_0x2d33700, 2, 1; +L_0x2d33130 .part L_0x2d33700, 3, 1; +L_0x2d33320 .part L_0x2d32dd0, 0, 1; +L_0x2d334d0 .part L_0x2d32dd0, 1, 1; +S_0x2b06460 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2aff590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1042e50_0 .net "ands", 7 0, L_0x124b710; 1 drivers -v0x1042f60_0 .net "in", 7 0, L_0x1249c50; alias, 1 drivers -v0x1043000_0 .net "out", 0 0, L_0x124d710; alias, 1 drivers -v0x10430d0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x103dc70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x103da20; +v0x2b0b890_0 .net "ands", 7 0, L_0x2d2dd60; 1 drivers +v0x2b0b9a0_0 .net "in", 7 0, L_0x2d2bcd0; alias, 1 drivers +v0x2b0ba60_0 .net "out", 0 0, L_0x2d2fd60; alias, 1 drivers +v0x2b0bb30_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b066b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b06460; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10403b0_0 .net "A", 7 0, L_0x1249c50; alias, 1 drivers -v0x10404b0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1040570_0 .net *"_s0", 0 0, L_0x1249fe0; 1 drivers -v0x1040630_0 .net *"_s12", 0 0, L_0x124a9a0; 1 drivers -v0x1040710_0 .net *"_s16", 0 0, L_0x124ad00; 1 drivers -v0x1040840_0 .net *"_s20", 0 0, L_0x124b0d0; 1 drivers -v0x1040920_0 .net *"_s24", 0 0, L_0x124b400; 1 drivers -v0x1040a00_0 .net *"_s28", 0 0, L_0x124b390; 1 drivers -v0x1040ae0_0 .net *"_s4", 0 0, L_0x124a380; 1 drivers -v0x1040c50_0 .net *"_s8", 0 0, L_0x124a690; 1 drivers -v0x1040d30_0 .net "out", 7 0, L_0x124b710; alias, 1 drivers -L_0x124a0f0 .part L_0x1249c50, 0, 1; -L_0x124a2e0 .part v0x12010b0_0, 0, 1; -L_0x124a440 .part L_0x1249c50, 1, 1; -L_0x124a5a0 .part v0x12010b0_0, 1, 1; -L_0x124a750 .part L_0x1249c50, 2, 1; -L_0x124a8b0 .part v0x12010b0_0, 2, 1; -L_0x124aa60 .part L_0x1249c50, 3, 1; -L_0x124abc0 .part v0x12010b0_0, 3, 1; -L_0x124adc0 .part L_0x1249c50, 4, 1; -L_0x124b030 .part v0x12010b0_0, 4, 1; -L_0x124b140 .part L_0x1249c50, 5, 1; -L_0x124b2a0 .part v0x12010b0_0, 5, 1; -L_0x124b4c0 .part L_0x1249c50, 6, 1; -L_0x124b620 .part v0x12010b0_0, 6, 1; -LS_0x124b710_0_0 .concat8 [ 1 1 1 1], L_0x1249fe0, L_0x124a380, L_0x124a690, L_0x124a9a0; -LS_0x124b710_0_4 .concat8 [ 1 1 1 1], L_0x124ad00, L_0x124b0d0, L_0x124b400, L_0x124b390; -L_0x124b710 .concat8 [ 4 4 0 0], LS_0x124b710_0_0, LS_0x124b710_0_4; -L_0x124bad0 .part L_0x1249c50, 7, 1; -L_0x124bcc0 .part v0x12010b0_0, 7, 1; -S_0x103deb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103e0c0 .param/l "i" 0 4 54, +C4<00>; -L_0x1249fe0/d .functor AND 1, L_0x124a0f0, L_0x124a2e0, C4<1>, C4<1>; -L_0x1249fe0 .delay 1 (30000,30000,30000) L_0x1249fe0/d; -v0x103e1a0_0 .net *"_s0", 0 0, L_0x124a0f0; 1 drivers -v0x103e280_0 .net *"_s1", 0 0, L_0x124a2e0; 1 drivers -S_0x103e360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103e570 .param/l "i" 0 4 54, +C4<01>; -L_0x124a380/d .functor AND 1, L_0x124a440, L_0x124a5a0, C4<1>, C4<1>; -L_0x124a380 .delay 1 (30000,30000,30000) L_0x124a380/d; -v0x103e630_0 .net *"_s0", 0 0, L_0x124a440; 1 drivers -v0x103e710_0 .net *"_s1", 0 0, L_0x124a5a0; 1 drivers -S_0x103e7f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103ea30 .param/l "i" 0 4 54, +C4<010>; -L_0x124a690/d .functor AND 1, L_0x124a750, L_0x124a8b0, C4<1>, C4<1>; -L_0x124a690 .delay 1 (30000,30000,30000) L_0x124a690/d; -v0x103ead0_0 .net *"_s0", 0 0, L_0x124a750; 1 drivers -v0x103ebb0_0 .net *"_s1", 0 0, L_0x124a8b0; 1 drivers -S_0x103ec90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103eea0 .param/l "i" 0 4 54, +C4<011>; -L_0x124a9a0/d .functor AND 1, L_0x124aa60, L_0x124abc0, C4<1>, C4<1>; -L_0x124a9a0 .delay 1 (30000,30000,30000) L_0x124a9a0/d; -v0x103ef60_0 .net *"_s0", 0 0, L_0x124aa60; 1 drivers -v0x103f040_0 .net *"_s1", 0 0, L_0x124abc0; 1 drivers -S_0x103f120 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103f380 .param/l "i" 0 4 54, +C4<0100>; -L_0x124ad00/d .functor AND 1, L_0x124adc0, L_0x124b030, C4<1>, C4<1>; -L_0x124ad00 .delay 1 (30000,30000,30000) L_0x124ad00/d; -v0x103f440_0 .net *"_s0", 0 0, L_0x124adc0; 1 drivers -v0x103f520_0 .net *"_s1", 0 0, L_0x124b030; 1 drivers -S_0x103f600 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103f810 .param/l "i" 0 4 54, +C4<0101>; -L_0x124b0d0/d .functor AND 1, L_0x124b140, L_0x124b2a0, C4<1>, C4<1>; -L_0x124b0d0 .delay 1 (30000,30000,30000) L_0x124b0d0/d; -v0x103f8d0_0 .net *"_s0", 0 0, L_0x124b140; 1 drivers -v0x103f9b0_0 .net *"_s1", 0 0, L_0x124b2a0; 1 drivers -S_0x103fa90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x103fca0 .param/l "i" 0 4 54, +C4<0110>; -L_0x124b400/d .functor AND 1, L_0x124b4c0, L_0x124b620, C4<1>, C4<1>; -L_0x124b400 .delay 1 (30000,30000,30000) L_0x124b400/d; -v0x103fd60_0 .net *"_s0", 0 0, L_0x124b4c0; 1 drivers -v0x103fe40_0 .net *"_s1", 0 0, L_0x124b620; 1 drivers -S_0x103ff20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x103dc70; - .timescale -9 -12; -P_0x1040130 .param/l "i" 0 4 54, +C4<0111>; -L_0x124b390/d .functor AND 1, L_0x124bad0, L_0x124bcc0, C4<1>, C4<1>; -L_0x124b390 .delay 1 (30000,30000,30000) L_0x124b390/d; -v0x10401f0_0 .net *"_s0", 0 0, L_0x124bad0; 1 drivers -v0x10402d0_0 .net *"_s1", 0 0, L_0x124bcc0; 1 drivers -S_0x1040e90 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x103da20; +v0x2b08df0_0 .net "A", 7 0, L_0x2d2bcd0; alias, 1 drivers +v0x2b08ef0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b08fb0_0 .net *"_s0", 0 0, L_0x2d2c550; 1 drivers +v0x2b09070_0 .net *"_s12", 0 0, L_0x2d2cf10; 1 drivers +v0x2b09150_0 .net *"_s16", 0 0, L_0x2d2d270; 1 drivers +v0x2b09280_0 .net *"_s20", 0 0, L_0x2d2d6a0; 1 drivers +v0x2b09360_0 .net *"_s24", 0 0, L_0x2d2d9d0; 1 drivers +v0x2b09440_0 .net *"_s28", 0 0, L_0x2d2d960; 1 drivers +v0x2b09520_0 .net *"_s4", 0 0, L_0x2d2c8f0; 1 drivers +v0x2b09690_0 .net *"_s8", 0 0, L_0x2d2cc00; 1 drivers +v0x2b09770_0 .net "out", 7 0, L_0x2d2dd60; alias, 1 drivers +L_0x2d2c660 .part L_0x2d2bcd0, 0, 1; +L_0x2d2c850 .part v0x2cdd2e0_0, 0, 1; +L_0x2d2c9b0 .part L_0x2d2bcd0, 1, 1; +L_0x2d2cb10 .part v0x2cdd2e0_0, 1, 1; +L_0x2d2ccc0 .part L_0x2d2bcd0, 2, 1; +L_0x2d2ce20 .part v0x2cdd2e0_0, 2, 1; +L_0x2d2cfd0 .part L_0x2d2bcd0, 3, 1; +L_0x2d2d130 .part v0x2cdd2e0_0, 3, 1; +L_0x2d2d330 .part L_0x2d2bcd0, 4, 1; +L_0x2d2d5a0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d2d710 .part L_0x2d2bcd0, 5, 1; +L_0x2d2d870 .part v0x2cdd2e0_0, 5, 1; +L_0x2d2da90 .part L_0x2d2bcd0, 6, 1; +L_0x2d2dbf0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d2dd60_0_0 .concat8 [ 1 1 1 1], L_0x2d2c550, L_0x2d2c8f0, L_0x2d2cc00, L_0x2d2cf10; +LS_0x2d2dd60_0_4 .concat8 [ 1 1 1 1], L_0x2d2d270, L_0x2d2d6a0, L_0x2d2d9d0, L_0x2d2d960; +L_0x2d2dd60 .concat8 [ 4 4 0 0], LS_0x2d2dd60_0_0, LS_0x2d2dd60_0_4; +L_0x2d2e120 .part L_0x2d2bcd0, 7, 1; +L_0x2d2e310 .part v0x2cdd2e0_0, 7, 1; +S_0x2b068f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b06b00 .param/l "i" 0 4 54, +C4<00>; +L_0x2d2c550/d .functor AND 1, L_0x2d2c660, L_0x2d2c850, C4<1>, C4<1>; +L_0x2d2c550 .delay 1 (30000,30000,30000) L_0x2d2c550/d; +v0x2b06be0_0 .net *"_s0", 0 0, L_0x2d2c660; 1 drivers +v0x2b06cc0_0 .net *"_s1", 0 0, L_0x2d2c850; 1 drivers +S_0x2b06da0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b06fb0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d2c8f0/d .functor AND 1, L_0x2d2c9b0, L_0x2d2cb10, C4<1>, C4<1>; +L_0x2d2c8f0 .delay 1 (30000,30000,30000) L_0x2d2c8f0/d; +v0x2b07070_0 .net *"_s0", 0 0, L_0x2d2c9b0; 1 drivers +v0x2b07150_0 .net *"_s1", 0 0, L_0x2d2cb10; 1 drivers +S_0x2b07230 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b07470 .param/l "i" 0 4 54, +C4<010>; +L_0x2d2cc00/d .functor AND 1, L_0x2d2ccc0, L_0x2d2ce20, C4<1>, C4<1>; +L_0x2d2cc00 .delay 1 (30000,30000,30000) L_0x2d2cc00/d; +v0x2b07510_0 .net *"_s0", 0 0, L_0x2d2ccc0; 1 drivers +v0x2b075f0_0 .net *"_s1", 0 0, L_0x2d2ce20; 1 drivers +S_0x2b076d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b078e0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d2cf10/d .functor AND 1, L_0x2d2cfd0, L_0x2d2d130, C4<1>, C4<1>; +L_0x2d2cf10 .delay 1 (30000,30000,30000) L_0x2d2cf10/d; +v0x2b079a0_0 .net *"_s0", 0 0, L_0x2d2cfd0; 1 drivers +v0x2b07a80_0 .net *"_s1", 0 0, L_0x2d2d130; 1 drivers +S_0x2b07b60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b07dc0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d2d270/d .functor AND 1, L_0x2d2d330, L_0x2d2d5a0, C4<1>, C4<1>; +L_0x2d2d270 .delay 1 (30000,30000,30000) L_0x2d2d270/d; +v0x2b07e80_0 .net *"_s0", 0 0, L_0x2d2d330; 1 drivers +v0x2b07f60_0 .net *"_s1", 0 0, L_0x2d2d5a0; 1 drivers +S_0x2b08040 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b08250 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d2d6a0/d .functor AND 1, L_0x2d2d710, L_0x2d2d870, C4<1>, C4<1>; +L_0x2d2d6a0 .delay 1 (30000,30000,30000) L_0x2d2d6a0/d; +v0x2b08310_0 .net *"_s0", 0 0, L_0x2d2d710; 1 drivers +v0x2b083f0_0 .net *"_s1", 0 0, L_0x2d2d870; 1 drivers +S_0x2b084d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b086e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d2d9d0/d .functor AND 1, L_0x2d2da90, L_0x2d2dbf0, C4<1>, C4<1>; +L_0x2d2d9d0 .delay 1 (30000,30000,30000) L_0x2d2d9d0/d; +v0x2b087a0_0 .net *"_s0", 0 0, L_0x2d2da90; 1 drivers +v0x2b08880_0 .net *"_s1", 0 0, L_0x2d2dbf0; 1 drivers +S_0x2b08960 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b066b0; + .timescale -9 -12; +P_0x2b08b70 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d2d960/d .functor AND 1, L_0x2d2e120, L_0x2d2e310, C4<1>, C4<1>; +L_0x2d2d960 .delay 1 (30000,30000,30000) L_0x2d2d960/d; +v0x2b08c30_0 .net *"_s0", 0 0, L_0x2d2e120; 1 drivers +v0x2b08d10_0 .net *"_s1", 0 0, L_0x2d2e310; 1 drivers +S_0x2b098d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b06460; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x124d710/d .functor OR 1, L_0x124d7d0, L_0x124d980, C4<0>, C4<0>; -L_0x124d710 .delay 1 (30000,30000,30000) L_0x124d710/d; -v0x10429e0_0 .net *"_s10", 0 0, L_0x124d7d0; 1 drivers -v0x1042ac0_0 .net *"_s12", 0 0, L_0x124d980; 1 drivers -v0x1042ba0_0 .net "in", 7 0, L_0x124b710; alias, 1 drivers -v0x1042c70_0 .net "ors", 1 0, L_0x124d530; 1 drivers -v0x1042d30_0 .net "out", 0 0, L_0x124d710; alias, 1 drivers -L_0x124c900 .part L_0x124b710, 0, 4; -L_0x124d530 .concat8 [ 1 1 0 0], L_0x124c5f0, L_0x124d220; -L_0x124d670 .part L_0x124b710, 4, 4; -L_0x124d7d0 .part L_0x124d530, 0, 1; -L_0x124d980 .part L_0x124d530, 1, 1; -S_0x1041050 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1040e90; +L_0x2d2fd60/d .functor OR 1, L_0x2d2fe20, L_0x2d2ffd0, C4<0>, C4<0>; +L_0x2d2fd60 .delay 1 (30000,30000,30000) L_0x2d2fd60/d; +v0x2b0b420_0 .net *"_s10", 0 0, L_0x2d2fe20; 1 drivers +v0x2b0b500_0 .net *"_s12", 0 0, L_0x2d2ffd0; 1 drivers +v0x2b0b5e0_0 .net "in", 7 0, L_0x2d2dd60; alias, 1 drivers +v0x2b0b6b0_0 .net "ors", 1 0, L_0x2d2fb80; 1 drivers +v0x2b0b770_0 .net "out", 0 0, L_0x2d2fd60; alias, 1 drivers +L_0x2d2ef50 .part L_0x2d2dd60, 0, 4; +L_0x2d2fb80 .concat8 [ 1 1 0 0], L_0x2d2ec40, L_0x2d2f870; +L_0x2d2fcc0 .part L_0x2d2dd60, 4, 4; +L_0x2d2fe20 .part L_0x2d2fb80, 0, 1; +L_0x2d2ffd0 .part L_0x2d2fb80, 1, 1; +S_0x2b09a90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b098d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x124bdb0/d .functor OR 1, L_0x124be70, L_0x124bfd0, C4<0>, C4<0>; -L_0x124bdb0 .delay 1 (30000,30000,30000) L_0x124bdb0/d; -L_0x124c200/d .functor OR 1, L_0x124c310, L_0x124c470, C4<0>, C4<0>; -L_0x124c200 .delay 1 (30000,30000,30000) L_0x124c200/d; -L_0x124c5f0/d .functor OR 1, L_0x124c660, L_0x124c810, C4<0>, C4<0>; -L_0x124c5f0 .delay 1 (30000,30000,30000) L_0x124c5f0/d; -v0x10412a0_0 .net *"_s0", 0 0, L_0x124bdb0; 1 drivers -v0x10413a0_0 .net *"_s10", 0 0, L_0x124c310; 1 drivers -v0x1041480_0 .net *"_s12", 0 0, L_0x124c470; 1 drivers -v0x1041540_0 .net *"_s14", 0 0, L_0x124c660; 1 drivers -v0x1041620_0 .net *"_s16", 0 0, L_0x124c810; 1 drivers -v0x1041750_0 .net *"_s3", 0 0, L_0x124be70; 1 drivers -v0x1041830_0 .net *"_s5", 0 0, L_0x124bfd0; 1 drivers -v0x1041910_0 .net *"_s6", 0 0, L_0x124c200; 1 drivers -v0x10419f0_0 .net "in", 3 0, L_0x124c900; 1 drivers -v0x1041b60_0 .net "ors", 1 0, L_0x124c110; 1 drivers -v0x1041c40_0 .net "out", 0 0, L_0x124c5f0; 1 drivers -L_0x124be70 .part L_0x124c900, 0, 1; -L_0x124bfd0 .part L_0x124c900, 1, 1; -L_0x124c110 .concat8 [ 1 1 0 0], L_0x124bdb0, L_0x124c200; -L_0x124c310 .part L_0x124c900, 2, 1; -L_0x124c470 .part L_0x124c900, 3, 1; -L_0x124c660 .part L_0x124c110, 0, 1; -L_0x124c810 .part L_0x124c110, 1, 1; -S_0x1041d60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1040e90; +L_0x2d2e400/d .functor OR 1, L_0x2d2e4c0, L_0x2d2e620, C4<0>, C4<0>; +L_0x2d2e400 .delay 1 (30000,30000,30000) L_0x2d2e400/d; +L_0x2d2e850/d .functor OR 1, L_0x2d2e960, L_0x2d2eac0, C4<0>, C4<0>; +L_0x2d2e850 .delay 1 (30000,30000,30000) L_0x2d2e850/d; +L_0x2d2ec40/d .functor OR 1, L_0x2d2ecb0, L_0x2d2ee60, C4<0>, C4<0>; +L_0x2d2ec40 .delay 1 (30000,30000,30000) L_0x2d2ec40/d; +v0x2b09ce0_0 .net *"_s0", 0 0, L_0x2d2e400; 1 drivers +v0x2b09de0_0 .net *"_s10", 0 0, L_0x2d2e960; 1 drivers +v0x2b09ec0_0 .net *"_s12", 0 0, L_0x2d2eac0; 1 drivers +v0x2b09f80_0 .net *"_s14", 0 0, L_0x2d2ecb0; 1 drivers +v0x2b0a060_0 .net *"_s16", 0 0, L_0x2d2ee60; 1 drivers +v0x2b0a190_0 .net *"_s3", 0 0, L_0x2d2e4c0; 1 drivers +v0x2b0a270_0 .net *"_s5", 0 0, L_0x2d2e620; 1 drivers +v0x2b0a350_0 .net *"_s6", 0 0, L_0x2d2e850; 1 drivers +v0x2b0a430_0 .net "in", 3 0, L_0x2d2ef50; 1 drivers +v0x2b0a5a0_0 .net "ors", 1 0, L_0x2d2e760; 1 drivers +v0x2b0a680_0 .net "out", 0 0, L_0x2d2ec40; 1 drivers +L_0x2d2e4c0 .part L_0x2d2ef50, 0, 1; +L_0x2d2e620 .part L_0x2d2ef50, 1, 1; +L_0x2d2e760 .concat8 [ 1 1 0 0], L_0x2d2e400, L_0x2d2e850; +L_0x2d2e960 .part L_0x2d2ef50, 2, 1; +L_0x2d2eac0 .part L_0x2d2ef50, 3, 1; +L_0x2d2ecb0 .part L_0x2d2e760, 0, 1; +L_0x2d2ee60 .part L_0x2d2e760, 1, 1; +S_0x2b0a7a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b098d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x124ca30/d .functor OR 1, L_0x124caa0, L_0x124cc00, C4<0>, C4<0>; -L_0x124ca30 .delay 1 (30000,30000,30000) L_0x124ca30/d; -L_0x124ce30/d .functor OR 1, L_0x124cf40, L_0x124d0a0, C4<0>, C4<0>; -L_0x124ce30 .delay 1 (30000,30000,30000) L_0x124ce30/d; -L_0x124d220/d .functor OR 1, L_0x124d290, L_0x124d440, C4<0>, C4<0>; -L_0x124d220 .delay 1 (30000,30000,30000) L_0x124d220/d; -v0x1041f20_0 .net *"_s0", 0 0, L_0x124ca30; 1 drivers -v0x1042020_0 .net *"_s10", 0 0, L_0x124cf40; 1 drivers -v0x1042100_0 .net *"_s12", 0 0, L_0x124d0a0; 1 drivers -v0x10421c0_0 .net *"_s14", 0 0, L_0x124d290; 1 drivers -v0x10422a0_0 .net *"_s16", 0 0, L_0x124d440; 1 drivers -v0x10423d0_0 .net *"_s3", 0 0, L_0x124caa0; 1 drivers -v0x10424b0_0 .net *"_s5", 0 0, L_0x124cc00; 1 drivers -v0x1042590_0 .net *"_s6", 0 0, L_0x124ce30; 1 drivers -v0x1042670_0 .net "in", 3 0, L_0x124d670; 1 drivers -v0x10427e0_0 .net "ors", 1 0, L_0x124cd40; 1 drivers -v0x10428c0_0 .net "out", 0 0, L_0x124d220; 1 drivers -L_0x124caa0 .part L_0x124d670, 0, 1; -L_0x124cc00 .part L_0x124d670, 1, 1; -L_0x124cd40 .concat8 [ 1 1 0 0], L_0x124ca30, L_0x124ce30; -L_0x124cf40 .part L_0x124d670, 2, 1; -L_0x124d0a0 .part L_0x124d670, 3, 1; -L_0x124d290 .part L_0x124cd40, 0, 1; -L_0x124d440 .part L_0x124cd40, 1, 1; -S_0x10431d0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1036b50; +L_0x2d2f080/d .functor OR 1, L_0x2d2f0f0, L_0x2d2f250, C4<0>, C4<0>; +L_0x2d2f080 .delay 1 (30000,30000,30000) L_0x2d2f080/d; +L_0x2d2f480/d .functor OR 1, L_0x2d2f590, L_0x2d2f6f0, C4<0>, C4<0>; +L_0x2d2f480 .delay 1 (30000,30000,30000) L_0x2d2f480/d; +L_0x2d2f870/d .functor OR 1, L_0x2d2f8e0, L_0x2d2fa90, C4<0>, C4<0>; +L_0x2d2f870 .delay 1 (30000,30000,30000) L_0x2d2f870/d; +v0x2b0a960_0 .net *"_s0", 0 0, L_0x2d2f080; 1 drivers +v0x2b0aa60_0 .net *"_s10", 0 0, L_0x2d2f590; 1 drivers +v0x2b0ab40_0 .net *"_s12", 0 0, L_0x2d2f6f0; 1 drivers +v0x2b0ac00_0 .net *"_s14", 0 0, L_0x2d2f8e0; 1 drivers +v0x2b0ace0_0 .net *"_s16", 0 0, L_0x2d2fa90; 1 drivers +v0x2b0ae10_0 .net *"_s3", 0 0, L_0x2d2f0f0; 1 drivers +v0x2b0aef0_0 .net *"_s5", 0 0, L_0x2d2f250; 1 drivers +v0x2b0afd0_0 .net *"_s6", 0 0, L_0x2d2f480; 1 drivers +v0x2b0b0b0_0 .net "in", 3 0, L_0x2d2fcc0; 1 drivers +v0x2b0b220_0 .net "ors", 1 0, L_0x2d2f390; 1 drivers +v0x2b0b300_0 .net "out", 0 0, L_0x2d2f870; 1 drivers +L_0x2d2f0f0 .part L_0x2d2fcc0, 0, 1; +L_0x2d2f250 .part L_0x2d2fcc0, 1, 1; +L_0x2d2f390 .concat8 [ 1 1 0 0], L_0x2d2f080, L_0x2d2f480; +L_0x2d2f590 .part L_0x2d2fcc0, 2, 1; +L_0x2d2f6f0 .part L_0x2d2fcc0, 3, 1; +L_0x2d2f8e0 .part L_0x2d2f390, 0, 1; +L_0x2d2fa90 .part L_0x2d2f390, 1, 1; +S_0x2b0bc10 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2aff590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -4406,80 +4656,80 @@ S_0x10431d0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1036b50; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1248fc0/d .functor XNOR 1, L_0x12515b0, L_0x1247c50, C4<0>, C4<0>; -L_0x1248fc0 .delay 1 (20000,20000,20000) L_0x1248fc0/d; -L_0x1249230/d .functor AND 1, L_0x12515b0, L_0x1247eb0, C4<1>, C4<1>; -L_0x1249230 .delay 1 (30000,30000,30000) L_0x1249230/d; -L_0x12492a0/d .functor AND 1, L_0x1248fc0, L_0x12517d0, C4<1>, C4<1>; -L_0x12492a0 .delay 1 (30000,30000,30000) L_0x12492a0/d; -L_0x1249400/d .functor OR 1, L_0x12492a0, L_0x1249230, C4<0>, C4<0>; -L_0x1249400 .delay 1 (30000,30000,30000) L_0x1249400/d; -v0x1043480_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers -v0x1043570_0 .net "a_", 0 0, L_0x1247da0; alias, 1 drivers -v0x1043630_0 .net "b", 0 0, L_0x1247c50; alias, 1 drivers -v0x1043720_0 .net "b_", 0 0, L_0x1247eb0; alias, 1 drivers -v0x10437c0_0 .net "carryin", 0 0, L_0x12517d0; alias, 1 drivers -v0x1043900_0 .net "eq", 0 0, L_0x1248fc0; 1 drivers -v0x10439c0_0 .net "lt", 0 0, L_0x1249230; 1 drivers -v0x1043a80_0 .net "out", 0 0, L_0x1249400; 1 drivers -v0x1043b40_0 .net "w0", 0 0, L_0x12492a0; 1 drivers -S_0x1043d90 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1036b50; +L_0x2d2ab10/d .functor XNOR 1, L_0x2d33c00, L_0x2d29690, C4<0>, C4<0>; +L_0x2d2ab10 .delay 1 (20000,20000,20000) L_0x2d2ab10/d; +L_0x2d2ac90/d .functor AND 1, L_0x2d33c00, L_0x2d298a0, C4<1>, C4<1>; +L_0x2d2ac90 .delay 1 (30000,30000,30000) L_0x2d2ac90/d; +L_0x2d2adf0/d .functor AND 1, L_0x2d2ab10, L_0x2d33e20, C4<1>, C4<1>; +L_0x2d2adf0 .delay 1 (30000,30000,30000) L_0x2d2adf0/d; +L_0x2d2af00/d .functor OR 1, L_0x2d2adf0, L_0x2d2ac90, C4<0>, C4<0>; +L_0x2d2af00 .delay 1 (30000,30000,30000) L_0x2d2af00/d; +v0x2b0bec0_0 .net "a", 0 0, L_0x2d33c00; alias, 1 drivers +v0x2b0bfb0_0 .net "a_", 0 0, L_0x2d29790; alias, 1 drivers +v0x2b0c070_0 .net "b", 0 0, L_0x2d29690; alias, 1 drivers +v0x2b0c160_0 .net "b_", 0 0, L_0x2d298a0; alias, 1 drivers +v0x2b0c200_0 .net "carryin", 0 0, L_0x2d33e20; alias, 1 drivers +v0x2b0c340_0 .net "eq", 0 0, L_0x2d2ab10; 1 drivers +v0x2b0c400_0 .net "lt", 0 0, L_0x2d2ac90; 1 drivers +v0x2b0c4c0_0 .net "out", 0 0, L_0x2d2af00; 1 drivers +v0x2b0c580_0 .net "w0", 0 0, L_0x2d2adf0; 1 drivers +S_0x2b0c7d0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2aff590; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1248da0/d .functor OR 1, L_0x12488a0, L_0x1044ff0, C4<0>, C4<0>; -L_0x1248da0 .delay 1 (30000,30000,30000) L_0x1248da0/d; -v0x1044b80_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers -v0x1044cd0_0 .net "b", 0 0, L_0x1247eb0; alias, 1 drivers -v0x1044d90_0 .net "c1", 0 0, L_0x12488a0; 1 drivers -v0x1044e30_0 .net "c2", 0 0, L_0x1044ff0; 1 drivers -v0x1044f00_0 .net "carryin", 0 0, L_0x12517d0; alias, 1 drivers -v0x1045080_0 .net "carryout", 0 0, L_0x1248da0; 1 drivers -v0x1045120_0 .net "s1", 0 0, L_0x12487e0; 1 drivers -v0x10451c0_0 .net "sum", 0 0, L_0x1248a00; 1 drivers -S_0x1043fe0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1043d90; +L_0x2d2a6f0/d .functor OR 1, L_0x2d2a240, L_0x2b0da30, C4<0>, C4<0>; +L_0x2d2a6f0 .delay 1 (30000,30000,30000) L_0x2d2a6f0/d; +v0x2b0d5c0_0 .net "a", 0 0, L_0x2d33c00; alias, 1 drivers +v0x2b0d710_0 .net "b", 0 0, L_0x2d298a0; alias, 1 drivers +v0x2b0d7d0_0 .net "c1", 0 0, L_0x2d2a240; 1 drivers +v0x2b0d870_0 .net "c2", 0 0, L_0x2b0da30; 1 drivers +v0x2b0d940_0 .net "carryin", 0 0, L_0x2d33e20; alias, 1 drivers +v0x2b0dac0_0 .net "carryout", 0 0, L_0x2d2a6f0; 1 drivers +v0x2b0db60_0 .net "s1", 0 0, L_0x2d2a180; 1 drivers +v0x2b0dc00_0 .net "sum", 0 0, L_0x2d2a3a0; 1 drivers +S_0x2b0ca20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b0c7d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12487e0/d .functor XOR 1, L_0x12515b0, L_0x1247eb0, C4<0>, C4<0>; -L_0x12487e0 .delay 1 (30000,30000,30000) L_0x12487e0/d; -L_0x12488a0/d .functor AND 1, L_0x12515b0, L_0x1247eb0, C4<1>, C4<1>; -L_0x12488a0 .delay 1 (30000,30000,30000) L_0x12488a0/d; -v0x1044240_0 .net "a", 0 0, L_0x12515b0; alias, 1 drivers -v0x1044300_0 .net "b", 0 0, L_0x1247eb0; alias, 1 drivers -v0x10443c0_0 .net "carryout", 0 0, L_0x12488a0; alias, 1 drivers -v0x1044460_0 .net "sum", 0 0, L_0x12487e0; alias, 1 drivers -S_0x1044590 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1043d90; +L_0x2d2a180/d .functor XOR 1, L_0x2d33c00, L_0x2d298a0, C4<0>, C4<0>; +L_0x2d2a180 .delay 1 (30000,30000,30000) L_0x2d2a180/d; +L_0x2d2a240/d .functor AND 1, L_0x2d33c00, L_0x2d298a0, C4<1>, C4<1>; +L_0x2d2a240 .delay 1 (30000,30000,30000) L_0x2d2a240/d; +v0x2b0cc80_0 .net "a", 0 0, L_0x2d33c00; alias, 1 drivers +v0x2b0cd40_0 .net "b", 0 0, L_0x2d298a0; alias, 1 drivers +v0x2b0ce00_0 .net "carryout", 0 0, L_0x2d2a240; alias, 1 drivers +v0x2b0cea0_0 .net "sum", 0 0, L_0x2d2a180; alias, 1 drivers +S_0x2b0cfd0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b0c7d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1248a00/d .functor XOR 1, L_0x12487e0, L_0x12517d0, C4<0>, C4<0>; -L_0x1248a00 .delay 1 (30000,30000,30000) L_0x1248a00/d; -L_0x1044ff0/d .functor AND 1, L_0x12487e0, L_0x12517d0, C4<1>, C4<1>; -L_0x1044ff0 .delay 1 (30000,30000,30000) L_0x1044ff0/d; -v0x10447f0_0 .net "a", 0 0, L_0x12487e0; alias, 1 drivers -v0x10448c0_0 .net "b", 0 0, L_0x12517d0; alias, 1 drivers -v0x1044960_0 .net "carryout", 0 0, L_0x1044ff0; alias, 1 drivers -v0x1044a30_0 .net "sum", 0 0, L_0x1248a00; alias, 1 drivers -S_0x10465e0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1036880; - .timescale -9 -12; -L_0x2b0ab3d057f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05840 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1251650/d .functor OR 1, L_0x2b0ab3d057f8, L_0x2b0ab3d05840, C4<0>, C4<0>; -L_0x1251650 .delay 1 (30000,30000,30000) L_0x1251650/d; -v0x10467d0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d057f8; 1 drivers -v0x10468b0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05840; 1 drivers -S_0x1046990 .scope generate, "alu_slices[8]" "alu_slices[8]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1006530 .param/l "i" 0 3 41, +C4<01000>; -S_0x1046ca0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1046990; +L_0x2d2a3a0/d .functor XOR 1, L_0x2d2a180, L_0x2d33e20, C4<0>, C4<0>; +L_0x2d2a3a0 .delay 1 (30000,30000,30000) L_0x2d2a3a0/d; +L_0x2b0da30/d .functor AND 1, L_0x2d2a180, L_0x2d33e20, C4<1>, C4<1>; +L_0x2b0da30 .delay 1 (30000,30000,30000) L_0x2b0da30/d; +v0x2b0d230_0 .net "a", 0 0, L_0x2d2a180; alias, 1 drivers +v0x2b0d300_0 .net "b", 0 0, L_0x2d33e20; alias, 1 drivers +v0x2b0d3a0_0 .net "carryout", 0 0, L_0x2b0da30; alias, 1 drivers +v0x2b0d470_0 .net "sum", 0 0, L_0x2d2a3a0; alias, 1 drivers +S_0x2b0fc90 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2aff2c0; + .timescale -9 -12; +L_0x2ac6110b7e78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7ec0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d29d50/d .functor OR 1, L_0x2ac6110b7e78, L_0x2ac6110b7ec0, C4<0>, C4<0>; +L_0x2d29d50 .delay 1 (30000,30000,30000) L_0x2d29d50/d; +v0x2b0fe80_0 .net/2u *"_s0", 0 0, L_0x2ac6110b7e78; 1 drivers +v0x2b0ff60_0 .net/2u *"_s2", 0 0, L_0x2ac6110b7ec0; 1 drivers +S_0x2b10040 .scope generate, "alu_slices[8]" "alu_slices[8]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2accb30 .param/l "i" 0 3 39, +C4<01000>; +S_0x2b10350 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b10040; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -4488,445 +4738,476 @@ S_0x1046ca0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1046990; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1251aa0/d .functor NOT 1, L_0x125b280, C4<0>, C4<0>, C4<0>; -L_0x1251aa0 .delay 1 (10000,10000,10000) L_0x1251aa0/d; -L_0x1251bb0/d .functor NOT 1, L_0x125b3e0, C4<0>, C4<0>, C4<0>; -L_0x1251bb0 .delay 1 (10000,10000,10000) L_0x1251bb0/d; -L_0x1252af0/d .functor XOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; -L_0x1252af0 .delay 1 (30000,30000,30000) L_0x1252af0/d; -L_0x2b0ab3d05888 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d058d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12531a0/d .functor OR 1, L_0x2b0ab3d05888, L_0x2b0ab3d058d0, C4<0>, C4<0>; -L_0x12531a0 .delay 1 (30000,30000,30000) L_0x12531a0/d; -L_0x12533a0/d .functor AND 1, L_0x125b280, L_0x125b3e0, C4<1>, C4<1>; -L_0x12533a0 .delay 1 (30000,30000,30000) L_0x12533a0/d; -L_0x1253460/d .functor NAND 1, L_0x125b280, L_0x125b3e0, C4<1>, C4<1>; -L_0x1253460 .delay 1 (20000,20000,20000) L_0x1253460/d; -L_0x12535c0/d .functor XOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; -L_0x12535c0 .delay 1 (20000,20000,20000) L_0x12535c0/d; -L_0x1253a70/d .functor OR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; -L_0x1253a70 .delay 1 (30000,30000,30000) L_0x1253a70/d; -L_0x125b180/d .functor NOT 1, L_0x12573e0, C4<0>, C4<0>, C4<0>; -L_0x125b180 .delay 1 (10000,10000,10000) L_0x125b180/d; -v0x10553d0_0 .net "A", 0 0, L_0x125b280; 1 drivers -v0x1055490_0 .net "A_", 0 0, L_0x1251aa0; 1 drivers -v0x1055550_0 .net "B", 0 0, L_0x125b3e0; 1 drivers -v0x1055620_0 .net "B_", 0 0, L_0x1251bb0; 1 drivers -v0x10556c0_0 .net *"_s12", 0 0, L_0x12531a0; 1 drivers -v0x10557b0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05888; 1 drivers -v0x1055870_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d058d0; 1 drivers -v0x1055950_0 .net *"_s18", 0 0, L_0x12533a0; 1 drivers -v0x1055a30_0 .net *"_s20", 0 0, L_0x1253460; 1 drivers -v0x1055ba0_0 .net *"_s22", 0 0, L_0x12535c0; 1 drivers -v0x1055c80_0 .net *"_s24", 0 0, L_0x1253a70; 1 drivers -o0x2b0ab3cb7d48 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1055d60_0 name=_s30 -o0x2b0ab3cb7d78 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1055e40_0 name=_s32 -v0x1055f20_0 .net *"_s8", 0 0, L_0x1252af0; 1 drivers -v0x1056000_0 .net "carryin", 0 0, L_0x1251980; 1 drivers -v0x10560a0_0 .net "carryout", 0 0, L_0x125ae20; 1 drivers -v0x1056140_0 .net "carryouts", 7 0, L_0x1353be0; 1 drivers -v0x10562f0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1056390_0 .net "result", 0 0, L_0x12573e0; 1 drivers -v0x1056480_0 .net "results", 7 0, L_0x1253840; 1 drivers -v0x1056590_0 .net "zero", 0 0, L_0x125b180; 1 drivers -LS_0x1253840_0_0 .concat8 [ 1 1 1 1], L_0x1241910, L_0x1252640, L_0x1252af0, L_0x12531a0; -LS_0x1253840_0_4 .concat8 [ 1 1 1 1], L_0x12533a0, L_0x1253460, L_0x12535c0, L_0x1253a70; -L_0x1253840 .concat8 [ 4 4 0 0], LS_0x1253840_0_0, LS_0x1253840_0_4; -LS_0x1353be0_0_0 .concat [ 1 1 1 1], L_0x12522c0, L_0x1252990, o0x2b0ab3cb7d48, L_0x1252ff0; -LS_0x1353be0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cb7d78; -L_0x1353be0 .concat [ 4 4 0 0], LS_0x1353be0_0_0, LS_0x1353be0_0_4; -S_0x1046f20 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1046ca0; +L_0x2d33db0/d .functor NOT 1, L_0x2d3e4f0, C4<0>, C4<0>, C4<0>; +L_0x2d33db0 .delay 1 (10000,10000,10000) L_0x2d33db0/d; +L_0x2d34140/d .functor NOT 1, L_0x2d3e650, C4<0>, C4<0>, C4<0>; +L_0x2d34140 .delay 1 (10000,10000,10000) L_0x2d34140/d; +L_0x2d35140/d .functor XOR 1, L_0x2d3e4f0, L_0x2d3e650, C4<0>, C4<0>; +L_0x2d35140 .delay 1 (30000,30000,30000) L_0x2d35140/d; +L_0x2ac6110b7f08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7f50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d35200/d .functor OR 1, L_0x2ac6110b7f08, L_0x2ac6110b7f50, C4<0>, C4<0>; +L_0x2d35200 .delay 1 (30000,30000,30000) L_0x2d35200/d; +L_0x2ac6110b7f98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b7fe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d359a0/d .functor OR 1, L_0x2ac6110b7f98, L_0x2ac6110b7fe0, C4<0>, C4<0>; +L_0x2d359a0 .delay 1 (30000,30000,30000) L_0x2d359a0/d; +L_0x2d35ba0/d .functor AND 1, L_0x2d3e4f0, L_0x2d3e650, C4<1>, C4<1>; +L_0x2d35ba0 .delay 1 (30000,30000,30000) L_0x2d35ba0/d; +L_0x2ac6110b8028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d35c60/d .functor OR 1, L_0x2ac6110b8028, L_0x2ac6110b8070, C4<0>, C4<0>; +L_0x2d35c60 .delay 1 (30000,30000,30000) L_0x2d35c60/d; +L_0x2d35e60/d .functor NAND 1, L_0x2d3e4f0, L_0x2d3e650, C4<1>, C4<1>; +L_0x2d35e60 .delay 1 (20000,20000,20000) L_0x2d35e60/d; +L_0x2ac6110b80b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8100 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d35f70/d .functor OR 1, L_0x2ac6110b80b8, L_0x2ac6110b8100, C4<0>, C4<0>; +L_0x2d35f70 .delay 1 (30000,30000,30000) L_0x2d35f70/d; +L_0x2d36120/d .functor NOR 1, L_0x2d3e4f0, L_0x2d3e650, C4<0>, C4<0>; +L_0x2d36120 .delay 1 (20000,20000,20000) L_0x2d36120/d; +L_0x2ac6110b8148 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d363f0/d .functor OR 1, L_0x2ac6110b8148, L_0x2ac6110b8190, C4<0>, C4<0>; +L_0x2d363f0 .delay 1 (30000,30000,30000) L_0x2d363f0/d; +L_0x2d367f0/d .functor OR 1, L_0x2d3e4f0, L_0x2d3e650, C4<0>, C4<0>; +L_0x2d367f0 .delay 1 (30000,30000,30000) L_0x2d367f0/d; +L_0x2ac6110b81d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d36c90/d .functor OR 1, L_0x2ac6110b81d8, L_0x2ac6110b8220, C4<0>, C4<0>; +L_0x2d36c90 .delay 1 (30000,30000,30000) L_0x2d36c90/d; +L_0x2d3e3f0/d .functor NOT 1, L_0x2d3a650, C4<0>, C4<0>, C4<0>; +L_0x2d3e3f0 .delay 1 (10000,10000,10000) L_0x2d3e3f0/d; +v0x2b1ea90_0 .net "A", 0 0, L_0x2d3e4f0; 1 drivers +v0x2b1eb50_0 .net "A_", 0 0, L_0x2d33db0; 1 drivers +v0x2b1ec10_0 .net "B", 0 0, L_0x2d3e650; 1 drivers +v0x2b1ece0_0 .net "B_", 0 0, L_0x2d34140; 1 drivers +v0x2b1ed80_0 .net *"_s11", 0 0, L_0x2d35200; 1 drivers +v0x2b1ee70_0 .net/2s *"_s13", 0 0, L_0x2ac6110b7f08; 1 drivers +v0x2b1ef30_0 .net/2s *"_s15", 0 0, L_0x2ac6110b7f50; 1 drivers +v0x2b1f010_0 .net *"_s19", 0 0, L_0x2d359a0; 1 drivers +v0x2b1f0f0_0 .net/2s *"_s21", 0 0, L_0x2ac6110b7f98; 1 drivers +v0x2b1f260_0 .net/2s *"_s23", 0 0, L_0x2ac6110b7fe0; 1 drivers +v0x2b1f340_0 .net *"_s25", 0 0, L_0x2d35ba0; 1 drivers +v0x2b1f420_0 .net *"_s28", 0 0, L_0x2d35c60; 1 drivers +v0x2b1f500_0 .net/2s *"_s30", 0 0, L_0x2ac6110b8028; 1 drivers +v0x2b1f5e0_0 .net/2s *"_s32", 0 0, L_0x2ac6110b8070; 1 drivers +v0x2b1f6c0_0 .net *"_s34", 0 0, L_0x2d35e60; 1 drivers +v0x2b1f7a0_0 .net *"_s37", 0 0, L_0x2d35f70; 1 drivers +v0x2b1f880_0 .net/2s *"_s39", 0 0, L_0x2ac6110b80b8; 1 drivers +v0x2b1fa30_0 .net/2s *"_s41", 0 0, L_0x2ac6110b8100; 1 drivers +v0x2b1fad0_0 .net *"_s43", 0 0, L_0x2d36120; 1 drivers +v0x2b1fbb0_0 .net *"_s46", 0 0, L_0x2d363f0; 1 drivers +v0x2b1fc90_0 .net/2s *"_s48", 0 0, L_0x2ac6110b8148; 1 drivers +v0x2b1fd70_0 .net/2s *"_s50", 0 0, L_0x2ac6110b8190; 1 drivers +v0x2b1fe50_0 .net *"_s52", 0 0, L_0x2d367f0; 1 drivers +v0x2b1ff30_0 .net *"_s56", 0 0, L_0x2d36c90; 1 drivers +v0x2b20010_0 .net/2s *"_s59", 0 0, L_0x2ac6110b81d8; 1 drivers +v0x2b200f0_0 .net/2s *"_s61", 0 0, L_0x2ac6110b8220; 1 drivers +v0x2b201d0_0 .net *"_s8", 0 0, L_0x2d35140; 1 drivers +v0x2b202b0_0 .net "carryin", 0 0, L_0x2d33fd0; 1 drivers +v0x2b20350_0 .net "carryout", 0 0, L_0x2d3e090; 1 drivers +v0x2b203f0_0 .net "carryouts", 7 0, L_0x2d36900; 1 drivers +v0x2b20500_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b205c0_0 .net "result", 0 0, L_0x2d3a650; 1 drivers +v0x2b206b0_0 .net "results", 7 0, L_0x2d365c0; 1 drivers +v0x2b1f990_0 .net "zero", 0 0, L_0x2d3e3f0; 1 drivers +LS_0x2d365c0_0_0 .concat8 [ 1 1 1 1], L_0x2d34660, L_0x2d34c90, L_0x2d35140, L_0x2d359a0; +LS_0x2d365c0_0_4 .concat8 [ 1 1 1 1], L_0x2d35ba0, L_0x2d35e60, L_0x2d36120, L_0x2d367f0; +L_0x2d365c0 .concat8 [ 4 4 0 0], LS_0x2d365c0_0_0, LS_0x2d365c0_0_4; +LS_0x2d36900_0_0 .concat8 [ 1 1 1 1], L_0x2d34910, L_0x2d34fe0, L_0x2d35200, L_0x2d357f0; +LS_0x2d36900_0_4 .concat8 [ 1 1 1 1], L_0x2d35c60, L_0x2d35f70, L_0x2d363f0, L_0x2d36c90; +L_0x2d36900 .concat8 [ 4 4 0 0], LS_0x2d36900_0_0, LS_0x2d36900_0_4; +S_0x2b105d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b10350; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12522c0/d .functor OR 1, L_0x1251e60, L_0x1252160, C4<0>, C4<0>; -L_0x12522c0 .delay 1 (30000,30000,30000) L_0x12522c0/d; -v0x1047d50_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers -v0x1047e10_0 .net "b", 0 0, L_0x125b3e0; alias, 1 drivers -v0x1047ee0_0 .net "c1", 0 0, L_0x1251e60; 1 drivers -v0x1047fe0_0 .net "c2", 0 0, L_0x1252160; 1 drivers -v0x10480b0_0 .net "carryin", 0 0, L_0x1251980; alias, 1 drivers -v0x10481a0_0 .net "carryout", 0 0, L_0x12522c0; 1 drivers -v0x1048240_0 .net "s1", 0 0, L_0x1251da0; 1 drivers -v0x1048330_0 .net "sum", 0 0, L_0x1241910; 1 drivers -S_0x1047190 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1046f20; +L_0x2d34910/d .functor OR 1, L_0x2d343f0, L_0x2d347b0, C4<0>, C4<0>; +L_0x2d34910 .delay 1 (30000,30000,30000) L_0x2d34910/d; +v0x2b11400_0 .net "a", 0 0, L_0x2d3e4f0; alias, 1 drivers +v0x2b114c0_0 .net "b", 0 0, L_0x2d3e650; alias, 1 drivers +v0x2b11590_0 .net "c1", 0 0, L_0x2d343f0; 1 drivers +v0x2b11690_0 .net "c2", 0 0, L_0x2d347b0; 1 drivers +v0x2b11760_0 .net "carryin", 0 0, L_0x2d33fd0; alias, 1 drivers +v0x2b11850_0 .net "carryout", 0 0, L_0x2d34910; 1 drivers +v0x2b118f0_0 .net "s1", 0 0, L_0x2d34330; 1 drivers +v0x2b119e0_0 .net "sum", 0 0, L_0x2d34660; 1 drivers +S_0x2b10840 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b105d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1251da0/d .functor XOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; -L_0x1251da0 .delay 1 (30000,30000,30000) L_0x1251da0/d; -L_0x1251e60/d .functor AND 1, L_0x125b280, L_0x125b3e0, C4<1>, C4<1>; -L_0x1251e60 .delay 1 (30000,30000,30000) L_0x1251e60/d; -v0x10473f0_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers -v0x10474d0_0 .net "b", 0 0, L_0x125b3e0; alias, 1 drivers -v0x1047590_0 .net "carryout", 0 0, L_0x1251e60; alias, 1 drivers -v0x1047630_0 .net "sum", 0 0, L_0x1251da0; alias, 1 drivers -S_0x1047770 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1046f20; +L_0x2d34330/d .functor XOR 1, L_0x2d3e4f0, L_0x2d3e650, C4<0>, C4<0>; +L_0x2d34330 .delay 1 (30000,30000,30000) L_0x2d34330/d; +L_0x2d343f0/d .functor AND 1, L_0x2d3e4f0, L_0x2d3e650, C4<1>, C4<1>; +L_0x2d343f0 .delay 1 (30000,30000,30000) L_0x2d343f0/d; +v0x2b10aa0_0 .net "a", 0 0, L_0x2d3e4f0; alias, 1 drivers +v0x2b10b80_0 .net "b", 0 0, L_0x2d3e650; alias, 1 drivers +v0x2b10c40_0 .net "carryout", 0 0, L_0x2d343f0; alias, 1 drivers +v0x2b10ce0_0 .net "sum", 0 0, L_0x2d34330; alias, 1 drivers +S_0x2b10e20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b105d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1241910/d .functor XOR 1, L_0x1251da0, L_0x1251980, C4<0>, C4<0>; -L_0x1241910 .delay 1 (30000,30000,30000) L_0x1241910/d; -L_0x1252160/d .functor AND 1, L_0x1251da0, L_0x1251980, C4<1>, C4<1>; -L_0x1252160 .delay 1 (30000,30000,30000) L_0x1252160/d; -v0x10479d0_0 .net "a", 0 0, L_0x1251da0; alias, 1 drivers -v0x1047a70_0 .net "b", 0 0, L_0x1251980; alias, 1 drivers -v0x1047b10_0 .net "carryout", 0 0, L_0x1252160; alias, 1 drivers -v0x1047be0_0 .net "sum", 0 0, L_0x1241910; alias, 1 drivers -S_0x1048400 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1046ca0; +L_0x2d34660/d .functor XOR 1, L_0x2d34330, L_0x2d33fd0, C4<0>, C4<0>; +L_0x2d34660 .delay 1 (30000,30000,30000) L_0x2d34660/d; +L_0x2d347b0/d .functor AND 1, L_0x2d34330, L_0x2d33fd0, C4<1>, C4<1>; +L_0x2d347b0 .delay 1 (30000,30000,30000) L_0x2d347b0/d; +v0x2b11080_0 .net "a", 0 0, L_0x2d34330; alias, 1 drivers +v0x2b11120_0 .net "b", 0 0, L_0x2d33fd0; alias, 1 drivers +v0x2b111c0_0 .net "carryout", 0 0, L_0x2d347b0; alias, 1 drivers +v0x2b11290_0 .net "sum", 0 0, L_0x2d34660; alias, 1 drivers +S_0x2b11ab0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b10350; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x104d7f0_0 .net "ands", 7 0, L_0x1258e20; 1 drivers -v0x104d900_0 .net "in", 7 0, L_0x1353be0; alias, 1 drivers -v0x104d9c0_0 .net "out", 0 0, L_0x125ae20; alias, 1 drivers -v0x104da90_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1048620 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1048400; +v0x2b16ea0_0 .net "ands", 7 0, L_0x2d3c090; 1 drivers +v0x2b16fb0_0 .net "in", 7 0, L_0x2d36900; alias, 1 drivers +v0x2b17070_0 .net "out", 0 0, L_0x2d3e090; alias, 1 drivers +v0x2b17140_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b11cd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b11ab0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x104ad50_0 .net "A", 7 0, L_0x1353be0; alias, 1 drivers -v0x104ae50_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x104af10_0 .net *"_s0", 0 0, L_0x1257740; 1 drivers -v0x104afd0_0 .net *"_s12", 0 0, L_0x12580b0; 1 drivers -v0x104b0b0_0 .net *"_s16", 0 0, L_0x1258410; 1 drivers -v0x104b1e0_0 .net *"_s20", 0 0, L_0x1258720; 1 drivers -v0x104b2c0_0 .net *"_s24", 0 0, L_0x1258b10; 1 drivers -v0x104b3a0_0 .net *"_s28", 0 0, L_0x1258aa0; 1 drivers -v0x104b480_0 .net *"_s4", 0 0, L_0x1257a50; 1 drivers -v0x104b5f0_0 .net *"_s8", 0 0, L_0x1257da0; 1 drivers -v0x104b6d0_0 .net "out", 7 0, L_0x1258e20; alias, 1 drivers -L_0x1257800 .part L_0x1353be0, 0, 1; -L_0x1257960 .part v0x12010b0_0, 0, 1; -L_0x1257b10 .part L_0x1353be0, 1, 1; -L_0x1257d00 .part v0x12010b0_0, 1, 1; -L_0x1257e60 .part L_0x1353be0, 2, 1; -L_0x1257fc0 .part v0x12010b0_0, 2, 1; -L_0x1258170 .part L_0x1353be0, 3, 1; -L_0x12582d0 .part v0x12010b0_0, 3, 1; -L_0x12584d0 .part L_0x1353be0, 4, 1; -L_0x1258630 .part v0x12010b0_0, 4, 1; -L_0x1258790 .part L_0x1353be0, 5, 1; -L_0x1258a00 .part v0x12010b0_0, 5, 1; -L_0x1258bd0 .part L_0x1353be0, 6, 1; -L_0x1258d30 .part v0x12010b0_0, 6, 1; -LS_0x1258e20_0_0 .concat8 [ 1 1 1 1], L_0x1257740, L_0x1257a50, L_0x1257da0, L_0x12580b0; -LS_0x1258e20_0_4 .concat8 [ 1 1 1 1], L_0x1258410, L_0x1258720, L_0x1258b10, L_0x1258aa0; -L_0x1258e20 .concat8 [ 4 4 0 0], LS_0x1258e20_0_0, LS_0x1258e20_0_4; -L_0x12591e0 .part L_0x1353be0, 7, 1; -L_0x12593d0 .part v0x12010b0_0, 7, 1; -S_0x1048880 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x1048a90 .param/l "i" 0 4 54, +C4<00>; -L_0x1257740/d .functor AND 1, L_0x1257800, L_0x1257960, C4<1>, C4<1>; -L_0x1257740 .delay 1 (30000,30000,30000) L_0x1257740/d; -v0x1048b70_0 .net *"_s0", 0 0, L_0x1257800; 1 drivers -v0x1048c50_0 .net *"_s1", 0 0, L_0x1257960; 1 drivers -S_0x1048d30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x1048f40 .param/l "i" 0 4 54, +C4<01>; -L_0x1257a50/d .functor AND 1, L_0x1257b10, L_0x1257d00, C4<1>, C4<1>; -L_0x1257a50 .delay 1 (30000,30000,30000) L_0x1257a50/d; -v0x1049000_0 .net *"_s0", 0 0, L_0x1257b10; 1 drivers -v0x10490e0_0 .net *"_s1", 0 0, L_0x1257d00; 1 drivers -S_0x10491c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x10493d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1257da0/d .functor AND 1, L_0x1257e60, L_0x1257fc0, C4<1>, C4<1>; -L_0x1257da0 .delay 1 (30000,30000,30000) L_0x1257da0/d; -v0x1049470_0 .net *"_s0", 0 0, L_0x1257e60; 1 drivers -v0x1049550_0 .net *"_s1", 0 0, L_0x1257fc0; 1 drivers -S_0x1049630 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x1049840 .param/l "i" 0 4 54, +C4<011>; -L_0x12580b0/d .functor AND 1, L_0x1258170, L_0x12582d0, C4<1>, C4<1>; -L_0x12580b0 .delay 1 (30000,30000,30000) L_0x12580b0/d; -v0x1049900_0 .net *"_s0", 0 0, L_0x1258170; 1 drivers -v0x10499e0_0 .net *"_s1", 0 0, L_0x12582d0; 1 drivers -S_0x1049ac0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x1049d20 .param/l "i" 0 4 54, +C4<0100>; -L_0x1258410/d .functor AND 1, L_0x12584d0, L_0x1258630, C4<1>, C4<1>; -L_0x1258410 .delay 1 (30000,30000,30000) L_0x1258410/d; -v0x1049de0_0 .net *"_s0", 0 0, L_0x12584d0; 1 drivers -v0x1049ec0_0 .net *"_s1", 0 0, L_0x1258630; 1 drivers -S_0x1049fa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x104a1b0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1258720/d .functor AND 1, L_0x1258790, L_0x1258a00, C4<1>, C4<1>; -L_0x1258720 .delay 1 (30000,30000,30000) L_0x1258720/d; -v0x104a270_0 .net *"_s0", 0 0, L_0x1258790; 1 drivers -v0x104a350_0 .net *"_s1", 0 0, L_0x1258a00; 1 drivers -S_0x104a430 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x104a640 .param/l "i" 0 4 54, +C4<0110>; -L_0x1258b10/d .functor AND 1, L_0x1258bd0, L_0x1258d30, C4<1>, C4<1>; -L_0x1258b10 .delay 1 (30000,30000,30000) L_0x1258b10/d; -v0x104a700_0 .net *"_s0", 0 0, L_0x1258bd0; 1 drivers -v0x104a7e0_0 .net *"_s1", 0 0, L_0x1258d30; 1 drivers -S_0x104a8c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1048620; - .timescale -9 -12; -P_0x104aad0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1258aa0/d .functor AND 1, L_0x12591e0, L_0x12593d0, C4<1>, C4<1>; -L_0x1258aa0 .delay 1 (30000,30000,30000) L_0x1258aa0/d; -v0x104ab90_0 .net *"_s0", 0 0, L_0x12591e0; 1 drivers -v0x104ac70_0 .net *"_s1", 0 0, L_0x12593d0; 1 drivers -S_0x104b830 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1048400; +v0x2b14400_0 .net "A", 7 0, L_0x2d36900; alias, 1 drivers +v0x2b14500_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b145c0_0 .net *"_s0", 0 0, L_0x2d3a9b0; 1 drivers +v0x2b14680_0 .net *"_s12", 0 0, L_0x2d3b320; 1 drivers +v0x2b14760_0 .net *"_s16", 0 0, L_0x2d3b680; 1 drivers +v0x2b14890_0 .net *"_s20", 0 0, L_0x2d3ba50; 1 drivers +v0x2b14970_0 .net *"_s24", 0 0, L_0x2d3bd80; 1 drivers +v0x2b14a50_0 .net *"_s28", 0 0, L_0x2d3bd10; 1 drivers +v0x2b14b30_0 .net *"_s4", 0 0, L_0x2d3ad00; 1 drivers +v0x2b14ca0_0 .net *"_s8", 0 0, L_0x2d3b010; 1 drivers +v0x2b14d80_0 .net "out", 7 0, L_0x2d3c090; alias, 1 drivers +L_0x2d3aa70 .part L_0x2d36900, 0, 1; +L_0x2d3ac60 .part v0x2cdd2e0_0, 0, 1; +L_0x2d3adc0 .part L_0x2d36900, 1, 1; +L_0x2d3af20 .part v0x2cdd2e0_0, 1, 1; +L_0x2d3b0d0 .part L_0x2d36900, 2, 1; +L_0x2d3b230 .part v0x2cdd2e0_0, 2, 1; +L_0x2d3b3e0 .part L_0x2d36900, 3, 1; +L_0x2d3b540 .part v0x2cdd2e0_0, 3, 1; +L_0x2d3b740 .part L_0x2d36900, 4, 1; +L_0x2d3b9b0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d3bac0 .part L_0x2d36900, 5, 1; +L_0x2d3bc20 .part v0x2cdd2e0_0, 5, 1; +L_0x2d3be40 .part L_0x2d36900, 6, 1; +L_0x2d3bfa0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d3c090_0_0 .concat8 [ 1 1 1 1], L_0x2d3a9b0, L_0x2d3ad00, L_0x2d3b010, L_0x2d3b320; +LS_0x2d3c090_0_4 .concat8 [ 1 1 1 1], L_0x2d3b680, L_0x2d3ba50, L_0x2d3bd80, L_0x2d3bd10; +L_0x2d3c090 .concat8 [ 4 4 0 0], LS_0x2d3c090_0_0, LS_0x2d3c090_0_4; +L_0x2d3c450 .part L_0x2d36900, 7, 1; +L_0x2d3c640 .part v0x2cdd2e0_0, 7, 1; +S_0x2b11f30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b12140 .param/l "i" 0 4 54, +C4<00>; +L_0x2d3a9b0/d .functor AND 1, L_0x2d3aa70, L_0x2d3ac60, C4<1>, C4<1>; +L_0x2d3a9b0 .delay 1 (30000,30000,30000) L_0x2d3a9b0/d; +v0x2b12220_0 .net *"_s0", 0 0, L_0x2d3aa70; 1 drivers +v0x2b12300_0 .net *"_s1", 0 0, L_0x2d3ac60; 1 drivers +S_0x2b123e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b125f0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d3ad00/d .functor AND 1, L_0x2d3adc0, L_0x2d3af20, C4<1>, C4<1>; +L_0x2d3ad00 .delay 1 (30000,30000,30000) L_0x2d3ad00/d; +v0x2b126b0_0 .net *"_s0", 0 0, L_0x2d3adc0; 1 drivers +v0x2b12790_0 .net *"_s1", 0 0, L_0x2d3af20; 1 drivers +S_0x2b12870 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b12a80 .param/l "i" 0 4 54, +C4<010>; +L_0x2d3b010/d .functor AND 1, L_0x2d3b0d0, L_0x2d3b230, C4<1>, C4<1>; +L_0x2d3b010 .delay 1 (30000,30000,30000) L_0x2d3b010/d; +v0x2b12b20_0 .net *"_s0", 0 0, L_0x2d3b0d0; 1 drivers +v0x2b12c00_0 .net *"_s1", 0 0, L_0x2d3b230; 1 drivers +S_0x2b12ce0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b12ef0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d3b320/d .functor AND 1, L_0x2d3b3e0, L_0x2d3b540, C4<1>, C4<1>; +L_0x2d3b320 .delay 1 (30000,30000,30000) L_0x2d3b320/d; +v0x2b12fb0_0 .net *"_s0", 0 0, L_0x2d3b3e0; 1 drivers +v0x2b13090_0 .net *"_s1", 0 0, L_0x2d3b540; 1 drivers +S_0x2b13170 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b133d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d3b680/d .functor AND 1, L_0x2d3b740, L_0x2d3b9b0, C4<1>, C4<1>; +L_0x2d3b680 .delay 1 (30000,30000,30000) L_0x2d3b680/d; +v0x2b13490_0 .net *"_s0", 0 0, L_0x2d3b740; 1 drivers +v0x2b13570_0 .net *"_s1", 0 0, L_0x2d3b9b0; 1 drivers +S_0x2b13650 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b13860 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d3ba50/d .functor AND 1, L_0x2d3bac0, L_0x2d3bc20, C4<1>, C4<1>; +L_0x2d3ba50 .delay 1 (30000,30000,30000) L_0x2d3ba50/d; +v0x2b13920_0 .net *"_s0", 0 0, L_0x2d3bac0; 1 drivers +v0x2b13a00_0 .net *"_s1", 0 0, L_0x2d3bc20; 1 drivers +S_0x2b13ae0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b13cf0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d3bd80/d .functor AND 1, L_0x2d3be40, L_0x2d3bfa0, C4<1>, C4<1>; +L_0x2d3bd80 .delay 1 (30000,30000,30000) L_0x2d3bd80/d; +v0x2b13db0_0 .net *"_s0", 0 0, L_0x2d3be40; 1 drivers +v0x2b13e90_0 .net *"_s1", 0 0, L_0x2d3bfa0; 1 drivers +S_0x2b13f70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b11cd0; + .timescale -9 -12; +P_0x2b14180 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d3bd10/d .functor AND 1, L_0x2d3c450, L_0x2d3c640, C4<1>, C4<1>; +L_0x2d3bd10 .delay 1 (30000,30000,30000) L_0x2d3bd10/d; +v0x2b14240_0 .net *"_s0", 0 0, L_0x2d3c450; 1 drivers +v0x2b14320_0 .net *"_s1", 0 0, L_0x2d3c640; 1 drivers +S_0x2b14ee0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b11ab0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x125ae20/d .functor OR 1, L_0x125aee0, L_0x125b090, C4<0>, C4<0>; -L_0x125ae20 .delay 1 (30000,30000,30000) L_0x125ae20/d; -v0x104d380_0 .net *"_s10", 0 0, L_0x125aee0; 1 drivers -v0x104d460_0 .net *"_s12", 0 0, L_0x125b090; 1 drivers -v0x104d540_0 .net "in", 7 0, L_0x1258e20; alias, 1 drivers -v0x104d610_0 .net "ors", 1 0, L_0x125ac40; 1 drivers -v0x104d6d0_0 .net "out", 0 0, L_0x125ae20; alias, 1 drivers -L_0x125a010 .part L_0x1258e20, 0, 4; -L_0x125ac40 .concat8 [ 1 1 0 0], L_0x1259d00, L_0x125a930; -L_0x125ad80 .part L_0x1258e20, 4, 4; -L_0x125aee0 .part L_0x125ac40, 0, 1; -L_0x125b090 .part L_0x125ac40, 1, 1; -S_0x104b9f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x104b830; +L_0x2d3e090/d .functor OR 1, L_0x2d3e150, L_0x2d3e300, C4<0>, C4<0>; +L_0x2d3e090 .delay 1 (30000,30000,30000) L_0x2d3e090/d; +v0x2b16a30_0 .net *"_s10", 0 0, L_0x2d3e150; 1 drivers +v0x2b16b10_0 .net *"_s12", 0 0, L_0x2d3e300; 1 drivers +v0x2b16bf0_0 .net "in", 7 0, L_0x2d3c090; alias, 1 drivers +v0x2b16cc0_0 .net "ors", 1 0, L_0x2d3deb0; 1 drivers +v0x2b16d80_0 .net "out", 0 0, L_0x2d3e090; alias, 1 drivers +L_0x2d3d280 .part L_0x2d3c090, 0, 4; +L_0x2d3deb0 .concat8 [ 1 1 0 0], L_0x2d3cf70, L_0x2d3dba0; +L_0x2d3dff0 .part L_0x2d3c090, 4, 4; +L_0x2d3e150 .part L_0x2d3deb0, 0, 1; +L_0x2d3e300 .part L_0x2d3deb0, 1, 1; +S_0x2b150a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b14ee0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12594c0/d .functor OR 1, L_0x1259580, L_0x12596e0, C4<0>, C4<0>; -L_0x12594c0 .delay 1 (30000,30000,30000) L_0x12594c0/d; -L_0x1259910/d .functor OR 1, L_0x1259a20, L_0x1259b80, C4<0>, C4<0>; -L_0x1259910 .delay 1 (30000,30000,30000) L_0x1259910/d; -L_0x1259d00/d .functor OR 1, L_0x1259d70, L_0x1259f20, C4<0>, C4<0>; -L_0x1259d00 .delay 1 (30000,30000,30000) L_0x1259d00/d; -v0x104bc40_0 .net *"_s0", 0 0, L_0x12594c0; 1 drivers -v0x104bd40_0 .net *"_s10", 0 0, L_0x1259a20; 1 drivers -v0x104be20_0 .net *"_s12", 0 0, L_0x1259b80; 1 drivers -v0x104bee0_0 .net *"_s14", 0 0, L_0x1259d70; 1 drivers -v0x104bfc0_0 .net *"_s16", 0 0, L_0x1259f20; 1 drivers -v0x104c0f0_0 .net *"_s3", 0 0, L_0x1259580; 1 drivers -v0x104c1d0_0 .net *"_s5", 0 0, L_0x12596e0; 1 drivers -v0x104c2b0_0 .net *"_s6", 0 0, L_0x1259910; 1 drivers -v0x104c390_0 .net "in", 3 0, L_0x125a010; 1 drivers -v0x104c500_0 .net "ors", 1 0, L_0x1259820; 1 drivers -v0x104c5e0_0 .net "out", 0 0, L_0x1259d00; 1 drivers -L_0x1259580 .part L_0x125a010, 0, 1; -L_0x12596e0 .part L_0x125a010, 1, 1; -L_0x1259820 .concat8 [ 1 1 0 0], L_0x12594c0, L_0x1259910; -L_0x1259a20 .part L_0x125a010, 2, 1; -L_0x1259b80 .part L_0x125a010, 3, 1; -L_0x1259d70 .part L_0x1259820, 0, 1; -L_0x1259f20 .part L_0x1259820, 1, 1; -S_0x104c700 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x104b830; +L_0x2d3c730/d .functor OR 1, L_0x2d3c7f0, L_0x2d3c950, C4<0>, C4<0>; +L_0x2d3c730 .delay 1 (30000,30000,30000) L_0x2d3c730/d; +L_0x2d3cb80/d .functor OR 1, L_0x2d3cc90, L_0x2d3cdf0, C4<0>, C4<0>; +L_0x2d3cb80 .delay 1 (30000,30000,30000) L_0x2d3cb80/d; +L_0x2d3cf70/d .functor OR 1, L_0x2d3cfe0, L_0x2d3d190, C4<0>, C4<0>; +L_0x2d3cf70 .delay 1 (30000,30000,30000) L_0x2d3cf70/d; +v0x2b152f0_0 .net *"_s0", 0 0, L_0x2d3c730; 1 drivers +v0x2b153f0_0 .net *"_s10", 0 0, L_0x2d3cc90; 1 drivers +v0x2b154d0_0 .net *"_s12", 0 0, L_0x2d3cdf0; 1 drivers +v0x2b15590_0 .net *"_s14", 0 0, L_0x2d3cfe0; 1 drivers +v0x2b15670_0 .net *"_s16", 0 0, L_0x2d3d190; 1 drivers +v0x2b157a0_0 .net *"_s3", 0 0, L_0x2d3c7f0; 1 drivers +v0x2b15880_0 .net *"_s5", 0 0, L_0x2d3c950; 1 drivers +v0x2b15960_0 .net *"_s6", 0 0, L_0x2d3cb80; 1 drivers +v0x2b15a40_0 .net "in", 3 0, L_0x2d3d280; 1 drivers +v0x2b15bb0_0 .net "ors", 1 0, L_0x2d3ca90; 1 drivers +v0x2b15c90_0 .net "out", 0 0, L_0x2d3cf70; 1 drivers +L_0x2d3c7f0 .part L_0x2d3d280, 0, 1; +L_0x2d3c950 .part L_0x2d3d280, 1, 1; +L_0x2d3ca90 .concat8 [ 1 1 0 0], L_0x2d3c730, L_0x2d3cb80; +L_0x2d3cc90 .part L_0x2d3d280, 2, 1; +L_0x2d3cdf0 .part L_0x2d3d280, 3, 1; +L_0x2d3cfe0 .part L_0x2d3ca90, 0, 1; +L_0x2d3d190 .part L_0x2d3ca90, 1, 1; +S_0x2b15db0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b14ee0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x125a140/d .functor OR 1, L_0x125a1b0, L_0x125a310, C4<0>, C4<0>; -L_0x125a140 .delay 1 (30000,30000,30000) L_0x125a140/d; -L_0x125a540/d .functor OR 1, L_0x125a650, L_0x125a7b0, C4<0>, C4<0>; -L_0x125a540 .delay 1 (30000,30000,30000) L_0x125a540/d; -L_0x125a930/d .functor OR 1, L_0x125a9a0, L_0x125ab50, C4<0>, C4<0>; -L_0x125a930 .delay 1 (30000,30000,30000) L_0x125a930/d; -v0x104c8c0_0 .net *"_s0", 0 0, L_0x125a140; 1 drivers -v0x104c9c0_0 .net *"_s10", 0 0, L_0x125a650; 1 drivers -v0x104caa0_0 .net *"_s12", 0 0, L_0x125a7b0; 1 drivers -v0x104cb60_0 .net *"_s14", 0 0, L_0x125a9a0; 1 drivers -v0x104cc40_0 .net *"_s16", 0 0, L_0x125ab50; 1 drivers -v0x104cd70_0 .net *"_s3", 0 0, L_0x125a1b0; 1 drivers -v0x104ce50_0 .net *"_s5", 0 0, L_0x125a310; 1 drivers -v0x104cf30_0 .net *"_s6", 0 0, L_0x125a540; 1 drivers -v0x104d010_0 .net "in", 3 0, L_0x125ad80; 1 drivers -v0x104d180_0 .net "ors", 1 0, L_0x125a450; 1 drivers -v0x104d260_0 .net "out", 0 0, L_0x125a930; 1 drivers -L_0x125a1b0 .part L_0x125ad80, 0, 1; -L_0x125a310 .part L_0x125ad80, 1, 1; -L_0x125a450 .concat8 [ 1 1 0 0], L_0x125a140, L_0x125a540; -L_0x125a650 .part L_0x125ad80, 2, 1; -L_0x125a7b0 .part L_0x125ad80, 3, 1; -L_0x125a9a0 .part L_0x125a450, 0, 1; -L_0x125ab50 .part L_0x125a450, 1, 1; -S_0x104db70 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1046ca0; +L_0x2d3d3b0/d .functor OR 1, L_0x2d3d420, L_0x2d3d580, C4<0>, C4<0>; +L_0x2d3d3b0 .delay 1 (30000,30000,30000) L_0x2d3d3b0/d; +L_0x2d3d7b0/d .functor OR 1, L_0x2d3d8c0, L_0x2d3da20, C4<0>, C4<0>; +L_0x2d3d7b0 .delay 1 (30000,30000,30000) L_0x2d3d7b0/d; +L_0x2d3dba0/d .functor OR 1, L_0x2d3dc10, L_0x2d3ddc0, C4<0>, C4<0>; +L_0x2d3dba0 .delay 1 (30000,30000,30000) L_0x2d3dba0/d; +v0x2b15f70_0 .net *"_s0", 0 0, L_0x2d3d3b0; 1 drivers +v0x2b16070_0 .net *"_s10", 0 0, L_0x2d3d8c0; 1 drivers +v0x2b16150_0 .net *"_s12", 0 0, L_0x2d3da20; 1 drivers +v0x2b16210_0 .net *"_s14", 0 0, L_0x2d3dc10; 1 drivers +v0x2b162f0_0 .net *"_s16", 0 0, L_0x2d3ddc0; 1 drivers +v0x2b16420_0 .net *"_s3", 0 0, L_0x2d3d420; 1 drivers +v0x2b16500_0 .net *"_s5", 0 0, L_0x2d3d580; 1 drivers +v0x2b165e0_0 .net *"_s6", 0 0, L_0x2d3d7b0; 1 drivers +v0x2b166c0_0 .net "in", 3 0, L_0x2d3dff0; 1 drivers +v0x2b16830_0 .net "ors", 1 0, L_0x2d3d6c0; 1 drivers +v0x2b16910_0 .net "out", 0 0, L_0x2d3dba0; 1 drivers +L_0x2d3d420 .part L_0x2d3dff0, 0, 1; +L_0x2d3d580 .part L_0x2d3dff0, 1, 1; +L_0x2d3d6c0 .concat8 [ 1 1 0 0], L_0x2d3d3b0, L_0x2d3d7b0; +L_0x2d3d8c0 .part L_0x2d3dff0, 2, 1; +L_0x2d3da20 .part L_0x2d3dff0, 3, 1; +L_0x2d3dc10 .part L_0x2d3d6c0, 0, 1; +L_0x2d3ddc0 .part L_0x2d3d6c0, 1, 1; +S_0x2b17220 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b10350; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1052fa0_0 .net "ands", 7 0, L_0x12553e0; 1 drivers -v0x10530b0_0 .net "in", 7 0, L_0x1253840; alias, 1 drivers -v0x1053170_0 .net "out", 0 0, L_0x12573e0; alias, 1 drivers -v0x1053240_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x104ddc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x104db70; +v0x2b1c660_0 .net "ands", 7 0, L_0x2d38650; 1 drivers +v0x2b1c770_0 .net "in", 7 0, L_0x2d365c0; alias, 1 drivers +v0x2b1c830_0 .net "out", 0 0, L_0x2d3a650; alias, 1 drivers +v0x2b1c900_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b17470 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b17220; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1050500_0 .net "A", 7 0, L_0x1253840; alias, 1 drivers -v0x1050600_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10506c0_0 .net *"_s0", 0 0, L_0x1253bd0; 1 drivers -v0x1050780_0 .net *"_s12", 0 0, L_0x1254590; 1 drivers -v0x1050860_0 .net *"_s16", 0 0, L_0x12548f0; 1 drivers -v0x1050990_0 .net *"_s20", 0 0, L_0x1254d20; 1 drivers -v0x1050a70_0 .net *"_s24", 0 0, L_0x1255050; 1 drivers -v0x1050b50_0 .net *"_s28", 0 0, L_0x1254fe0; 1 drivers -v0x1050c30_0 .net *"_s4", 0 0, L_0x1253f70; 1 drivers -v0x1050da0_0 .net *"_s8", 0 0, L_0x1254280; 1 drivers -v0x1050e80_0 .net "out", 7 0, L_0x12553e0; alias, 1 drivers -L_0x1253ce0 .part L_0x1253840, 0, 1; -L_0x1253ed0 .part v0x12010b0_0, 0, 1; -L_0x1254030 .part L_0x1253840, 1, 1; -L_0x1254190 .part v0x12010b0_0, 1, 1; -L_0x1254340 .part L_0x1253840, 2, 1; -L_0x12544a0 .part v0x12010b0_0, 2, 1; -L_0x1254650 .part L_0x1253840, 3, 1; -L_0x12547b0 .part v0x12010b0_0, 3, 1; -L_0x12549b0 .part L_0x1253840, 4, 1; -L_0x1254c20 .part v0x12010b0_0, 4, 1; -L_0x1254d90 .part L_0x1253840, 5, 1; -L_0x1254ef0 .part v0x12010b0_0, 5, 1; -L_0x1255110 .part L_0x1253840, 6, 1; -L_0x1255270 .part v0x12010b0_0, 6, 1; -LS_0x12553e0_0_0 .concat8 [ 1 1 1 1], L_0x1253bd0, L_0x1253f70, L_0x1254280, L_0x1254590; -LS_0x12553e0_0_4 .concat8 [ 1 1 1 1], L_0x12548f0, L_0x1254d20, L_0x1255050, L_0x1254fe0; -L_0x12553e0 .concat8 [ 4 4 0 0], LS_0x12553e0_0_0, LS_0x12553e0_0_4; -L_0x12557a0 .part L_0x1253840, 7, 1; -L_0x1255990 .part v0x12010b0_0, 7, 1; -S_0x104e000 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104e210 .param/l "i" 0 4 54, +C4<00>; -L_0x1253bd0/d .functor AND 1, L_0x1253ce0, L_0x1253ed0, C4<1>, C4<1>; -L_0x1253bd0 .delay 1 (30000,30000,30000) L_0x1253bd0/d; -v0x104e2f0_0 .net *"_s0", 0 0, L_0x1253ce0; 1 drivers -v0x104e3d0_0 .net *"_s1", 0 0, L_0x1253ed0; 1 drivers -S_0x104e4b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104e6c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1253f70/d .functor AND 1, L_0x1254030, L_0x1254190, C4<1>, C4<1>; -L_0x1253f70 .delay 1 (30000,30000,30000) L_0x1253f70/d; -v0x104e780_0 .net *"_s0", 0 0, L_0x1254030; 1 drivers -v0x104e860_0 .net *"_s1", 0 0, L_0x1254190; 1 drivers -S_0x104e940 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104eb80 .param/l "i" 0 4 54, +C4<010>; -L_0x1254280/d .functor AND 1, L_0x1254340, L_0x12544a0, C4<1>, C4<1>; -L_0x1254280 .delay 1 (30000,30000,30000) L_0x1254280/d; -v0x104ec20_0 .net *"_s0", 0 0, L_0x1254340; 1 drivers -v0x104ed00_0 .net *"_s1", 0 0, L_0x12544a0; 1 drivers -S_0x104ede0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104eff0 .param/l "i" 0 4 54, +C4<011>; -L_0x1254590/d .functor AND 1, L_0x1254650, L_0x12547b0, C4<1>, C4<1>; -L_0x1254590 .delay 1 (30000,30000,30000) L_0x1254590/d; -v0x104f0b0_0 .net *"_s0", 0 0, L_0x1254650; 1 drivers -v0x104f190_0 .net *"_s1", 0 0, L_0x12547b0; 1 drivers -S_0x104f270 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104f4d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12548f0/d .functor AND 1, L_0x12549b0, L_0x1254c20, C4<1>, C4<1>; -L_0x12548f0 .delay 1 (30000,30000,30000) L_0x12548f0/d; -v0x104f590_0 .net *"_s0", 0 0, L_0x12549b0; 1 drivers -v0x104f670_0 .net *"_s1", 0 0, L_0x1254c20; 1 drivers -S_0x104f750 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104f960 .param/l "i" 0 4 54, +C4<0101>; -L_0x1254d20/d .functor AND 1, L_0x1254d90, L_0x1254ef0, C4<1>, C4<1>; -L_0x1254d20 .delay 1 (30000,30000,30000) L_0x1254d20/d; -v0x104fa20_0 .net *"_s0", 0 0, L_0x1254d90; 1 drivers -v0x104fb00_0 .net *"_s1", 0 0, L_0x1254ef0; 1 drivers -S_0x104fbe0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x104fdf0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1255050/d .functor AND 1, L_0x1255110, L_0x1255270, C4<1>, C4<1>; -L_0x1255050 .delay 1 (30000,30000,30000) L_0x1255050/d; -v0x104feb0_0 .net *"_s0", 0 0, L_0x1255110; 1 drivers -v0x104ff90_0 .net *"_s1", 0 0, L_0x1255270; 1 drivers -S_0x1050070 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x104ddc0; - .timescale -9 -12; -P_0x1050280 .param/l "i" 0 4 54, +C4<0111>; -L_0x1254fe0/d .functor AND 1, L_0x12557a0, L_0x1255990, C4<1>, C4<1>; -L_0x1254fe0 .delay 1 (30000,30000,30000) L_0x1254fe0/d; -v0x1050340_0 .net *"_s0", 0 0, L_0x12557a0; 1 drivers -v0x1050420_0 .net *"_s1", 0 0, L_0x1255990; 1 drivers -S_0x1050fe0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x104db70; +v0x2b19bb0_0 .net "A", 7 0, L_0x2d365c0; alias, 1 drivers +v0x2b19cb0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b19d70_0 .net *"_s0", 0 0, L_0x2d36e40; 1 drivers +v0x2b19e30_0 .net *"_s12", 0 0, L_0x2d37800; 1 drivers +v0x2b19f10_0 .net *"_s16", 0 0, L_0x2d37b60; 1 drivers +v0x2b1a040_0 .net *"_s20", 0 0, L_0x2d37f90; 1 drivers +v0x2b1a120_0 .net *"_s24", 0 0, L_0x2d382c0; 1 drivers +v0x2b1a200_0 .net *"_s28", 0 0, L_0x2d38250; 1 drivers +v0x2b1a2e0_0 .net *"_s4", 0 0, L_0x2d371e0; 1 drivers +v0x2b1a450_0 .net *"_s8", 0 0, L_0x2d374f0; 1 drivers +v0x2b1a530_0 .net "out", 7 0, L_0x2d38650; alias, 1 drivers +L_0x2d36f50 .part L_0x2d365c0, 0, 1; +L_0x2d37140 .part v0x2cdd2e0_0, 0, 1; +L_0x2d372a0 .part L_0x2d365c0, 1, 1; +L_0x2d37400 .part v0x2cdd2e0_0, 1, 1; +L_0x2d375b0 .part L_0x2d365c0, 2, 1; +L_0x2d37710 .part v0x2cdd2e0_0, 2, 1; +L_0x2d378c0 .part L_0x2d365c0, 3, 1; +L_0x2d37a20 .part v0x2cdd2e0_0, 3, 1; +L_0x2d37c20 .part L_0x2d365c0, 4, 1; +L_0x2d37e90 .part v0x2cdd2e0_0, 4, 1; +L_0x2d38000 .part L_0x2d365c0, 5, 1; +L_0x2d38160 .part v0x2cdd2e0_0, 5, 1; +L_0x2d38380 .part L_0x2d365c0, 6, 1; +L_0x2d384e0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d38650_0_0 .concat8 [ 1 1 1 1], L_0x2d36e40, L_0x2d371e0, L_0x2d374f0, L_0x2d37800; +LS_0x2d38650_0_4 .concat8 [ 1 1 1 1], L_0x2d37b60, L_0x2d37f90, L_0x2d382c0, L_0x2d38250; +L_0x2d38650 .concat8 [ 4 4 0 0], LS_0x2d38650_0_0, LS_0x2d38650_0_4; +L_0x2d38a10 .part L_0x2d365c0, 7, 1; +L_0x2d38c00 .part v0x2cdd2e0_0, 7, 1; +S_0x2b176b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b178c0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d36e40/d .functor AND 1, L_0x2d36f50, L_0x2d37140, C4<1>, C4<1>; +L_0x2d36e40 .delay 1 (30000,30000,30000) L_0x2d36e40/d; +v0x2b179a0_0 .net *"_s0", 0 0, L_0x2d36f50; 1 drivers +v0x2b17a80_0 .net *"_s1", 0 0, L_0x2d37140; 1 drivers +S_0x2b17b60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b17d70 .param/l "i" 0 4 54, +C4<01>; +L_0x2d371e0/d .functor AND 1, L_0x2d372a0, L_0x2d37400, C4<1>, C4<1>; +L_0x2d371e0 .delay 1 (30000,30000,30000) L_0x2d371e0/d; +v0x2b17e30_0 .net *"_s0", 0 0, L_0x2d372a0; 1 drivers +v0x2b17f10_0 .net *"_s1", 0 0, L_0x2d37400; 1 drivers +S_0x2b17ff0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b18230 .param/l "i" 0 4 54, +C4<010>; +L_0x2d374f0/d .functor AND 1, L_0x2d375b0, L_0x2d37710, C4<1>, C4<1>; +L_0x2d374f0 .delay 1 (30000,30000,30000) L_0x2d374f0/d; +v0x2b182d0_0 .net *"_s0", 0 0, L_0x2d375b0; 1 drivers +v0x2b183b0_0 .net *"_s1", 0 0, L_0x2d37710; 1 drivers +S_0x2b18490 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b186a0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d37800/d .functor AND 1, L_0x2d378c0, L_0x2d37a20, C4<1>, C4<1>; +L_0x2d37800 .delay 1 (30000,30000,30000) L_0x2d37800/d; +v0x2b18760_0 .net *"_s0", 0 0, L_0x2d378c0; 1 drivers +v0x2b18840_0 .net *"_s1", 0 0, L_0x2d37a20; 1 drivers +S_0x2b18920 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b18b80 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d37b60/d .functor AND 1, L_0x2d37c20, L_0x2d37e90, C4<1>, C4<1>; +L_0x2d37b60 .delay 1 (30000,30000,30000) L_0x2d37b60/d; +v0x2b18c40_0 .net *"_s0", 0 0, L_0x2d37c20; 1 drivers +v0x2b18d20_0 .net *"_s1", 0 0, L_0x2d37e90; 1 drivers +S_0x2b18e00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b19010 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d37f90/d .functor AND 1, L_0x2d38000, L_0x2d38160, C4<1>, C4<1>; +L_0x2d37f90 .delay 1 (30000,30000,30000) L_0x2d37f90/d; +v0x2b190d0_0 .net *"_s0", 0 0, L_0x2d38000; 1 drivers +v0x2b191b0_0 .net *"_s1", 0 0, L_0x2d38160; 1 drivers +S_0x2b19290 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b194a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d382c0/d .functor AND 1, L_0x2d38380, L_0x2d384e0, C4<1>, C4<1>; +L_0x2d382c0 .delay 1 (30000,30000,30000) L_0x2d382c0/d; +v0x2b19560_0 .net *"_s0", 0 0, L_0x2d38380; 1 drivers +v0x2b19640_0 .net *"_s1", 0 0, L_0x2d384e0; 1 drivers +S_0x2b19720 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b17470; + .timescale -9 -12; +P_0x2b19930 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d38250/d .functor AND 1, L_0x2d38a10, L_0x2d38c00, C4<1>, C4<1>; +L_0x2d38250 .delay 1 (30000,30000,30000) L_0x2d38250/d; +v0x2b199f0_0 .net *"_s0", 0 0, L_0x2d38a10; 1 drivers +v0x2b19ad0_0 .net *"_s1", 0 0, L_0x2d38c00; 1 drivers +S_0x2b1a690 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b17220; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12573e0/d .functor OR 1, L_0x12574a0, L_0x1257650, C4<0>, C4<0>; -L_0x12573e0 .delay 1 (30000,30000,30000) L_0x12573e0/d; -v0x1052b30_0 .net *"_s10", 0 0, L_0x12574a0; 1 drivers -v0x1052c10_0 .net *"_s12", 0 0, L_0x1257650; 1 drivers -v0x1052cf0_0 .net "in", 7 0, L_0x12553e0; alias, 1 drivers -v0x1052dc0_0 .net "ors", 1 0, L_0x1257200; 1 drivers -v0x1052e80_0 .net "out", 0 0, L_0x12573e0; alias, 1 drivers -L_0x12565d0 .part L_0x12553e0, 0, 4; -L_0x1257200 .concat8 [ 1 1 0 0], L_0x12562c0, L_0x1256ef0; -L_0x1257340 .part L_0x12553e0, 4, 4; -L_0x12574a0 .part L_0x1257200, 0, 1; -L_0x1257650 .part L_0x1257200, 1, 1; -S_0x10511a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1050fe0; +L_0x2d3a650/d .functor OR 1, L_0x2d3a710, L_0x2d3a8c0, C4<0>, C4<0>; +L_0x2d3a650 .delay 1 (30000,30000,30000) L_0x2d3a650/d; +v0x2b1c1f0_0 .net *"_s10", 0 0, L_0x2d3a710; 1 drivers +v0x2b1c2d0_0 .net *"_s12", 0 0, L_0x2d3a8c0; 1 drivers +v0x2b1c3b0_0 .net "in", 7 0, L_0x2d38650; alias, 1 drivers +v0x2b1c480_0 .net "ors", 1 0, L_0x2d3a470; 1 drivers +v0x2b1c540_0 .net "out", 0 0, L_0x2d3a650; alias, 1 drivers +L_0x2d39840 .part L_0x2d38650, 0, 4; +L_0x2d3a470 .concat8 [ 1 1 0 0], L_0x2d39530, L_0x2d3a160; +L_0x2d3a5b0 .part L_0x2d38650, 4, 4; +L_0x2d3a710 .part L_0x2d3a470, 0, 1; +L_0x2d3a8c0 .part L_0x2d3a470, 1, 1; +S_0x2b1a850 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b1a690; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1255a80/d .functor OR 1, L_0x1255b40, L_0x1255ca0, C4<0>, C4<0>; -L_0x1255a80 .delay 1 (30000,30000,30000) L_0x1255a80/d; -L_0x1255ed0/d .functor OR 1, L_0x1255fe0, L_0x1256140, C4<0>, C4<0>; -L_0x1255ed0 .delay 1 (30000,30000,30000) L_0x1255ed0/d; -L_0x12562c0/d .functor OR 1, L_0x1256330, L_0x12564e0, C4<0>, C4<0>; -L_0x12562c0 .delay 1 (30000,30000,30000) L_0x12562c0/d; -v0x10513f0_0 .net *"_s0", 0 0, L_0x1255a80; 1 drivers -v0x10514f0_0 .net *"_s10", 0 0, L_0x1255fe0; 1 drivers -v0x10515d0_0 .net *"_s12", 0 0, L_0x1256140; 1 drivers -v0x1051690_0 .net *"_s14", 0 0, L_0x1256330; 1 drivers -v0x1051770_0 .net *"_s16", 0 0, L_0x12564e0; 1 drivers -v0x10518a0_0 .net *"_s3", 0 0, L_0x1255b40; 1 drivers -v0x1051980_0 .net *"_s5", 0 0, L_0x1255ca0; 1 drivers -v0x1051a60_0 .net *"_s6", 0 0, L_0x1255ed0; 1 drivers -v0x1051b40_0 .net "in", 3 0, L_0x12565d0; 1 drivers -v0x1051cb0_0 .net "ors", 1 0, L_0x1255de0; 1 drivers -v0x1051d90_0 .net "out", 0 0, L_0x12562c0; 1 drivers -L_0x1255b40 .part L_0x12565d0, 0, 1; -L_0x1255ca0 .part L_0x12565d0, 1, 1; -L_0x1255de0 .concat8 [ 1 1 0 0], L_0x1255a80, L_0x1255ed0; -L_0x1255fe0 .part L_0x12565d0, 2, 1; -L_0x1256140 .part L_0x12565d0, 3, 1; -L_0x1256330 .part L_0x1255de0, 0, 1; -L_0x12564e0 .part L_0x1255de0, 1, 1; -S_0x1051eb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1050fe0; +L_0x2d38cf0/d .functor OR 1, L_0x2d38db0, L_0x2d38f10, C4<0>, C4<0>; +L_0x2d38cf0 .delay 1 (30000,30000,30000) L_0x2d38cf0/d; +L_0x2d39140/d .functor OR 1, L_0x2d39250, L_0x2d393b0, C4<0>, C4<0>; +L_0x2d39140 .delay 1 (30000,30000,30000) L_0x2d39140/d; +L_0x2d39530/d .functor OR 1, L_0x2d395a0, L_0x2d39750, C4<0>, C4<0>; +L_0x2d39530 .delay 1 (30000,30000,30000) L_0x2d39530/d; +v0x2b1aaa0_0 .net *"_s0", 0 0, L_0x2d38cf0; 1 drivers +v0x2b1aba0_0 .net *"_s10", 0 0, L_0x2d39250; 1 drivers +v0x2b1ac80_0 .net *"_s12", 0 0, L_0x2d393b0; 1 drivers +v0x2b1ad40_0 .net *"_s14", 0 0, L_0x2d395a0; 1 drivers +v0x2b1ae20_0 .net *"_s16", 0 0, L_0x2d39750; 1 drivers +v0x2b1af50_0 .net *"_s3", 0 0, L_0x2d38db0; 1 drivers +v0x2b1b010_0 .net *"_s5", 0 0, L_0x2d38f10; 1 drivers +v0x2b1b0f0_0 .net *"_s6", 0 0, L_0x2d39140; 1 drivers +v0x2b1b1d0_0 .net "in", 3 0, L_0x2d39840; 1 drivers +v0x2b1b340_0 .net "ors", 1 0, L_0x2d39050; 1 drivers +v0x2b1b420_0 .net "out", 0 0, L_0x2d39530; 1 drivers +L_0x2d38db0 .part L_0x2d39840, 0, 1; +L_0x2d38f10 .part L_0x2d39840, 1, 1; +L_0x2d39050 .concat8 [ 1 1 0 0], L_0x2d38cf0, L_0x2d39140; +L_0x2d39250 .part L_0x2d39840, 2, 1; +L_0x2d393b0 .part L_0x2d39840, 3, 1; +L_0x2d395a0 .part L_0x2d39050, 0, 1; +L_0x2d39750 .part L_0x2d39050, 1, 1; +S_0x2b1b540 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b1a690; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1256700/d .functor OR 1, L_0x1256770, L_0x12568d0, C4<0>, C4<0>; -L_0x1256700 .delay 1 (30000,30000,30000) L_0x1256700/d; -L_0x1256b00/d .functor OR 1, L_0x1256c10, L_0x1256d70, C4<0>, C4<0>; -L_0x1256b00 .delay 1 (30000,30000,30000) L_0x1256b00/d; -L_0x1256ef0/d .functor OR 1, L_0x1256f60, L_0x1257110, C4<0>, C4<0>; -L_0x1256ef0 .delay 1 (30000,30000,30000) L_0x1256ef0/d; -v0x1052070_0 .net *"_s0", 0 0, L_0x1256700; 1 drivers -v0x1052170_0 .net *"_s10", 0 0, L_0x1256c10; 1 drivers -v0x1052250_0 .net *"_s12", 0 0, L_0x1256d70; 1 drivers -v0x1052310_0 .net *"_s14", 0 0, L_0x1256f60; 1 drivers -v0x10523f0_0 .net *"_s16", 0 0, L_0x1257110; 1 drivers -v0x1052520_0 .net *"_s3", 0 0, L_0x1256770; 1 drivers -v0x1052600_0 .net *"_s5", 0 0, L_0x12568d0; 1 drivers -v0x10526e0_0 .net *"_s6", 0 0, L_0x1256b00; 1 drivers -v0x10527c0_0 .net "in", 3 0, L_0x1257340; 1 drivers -v0x1052930_0 .net "ors", 1 0, L_0x1256a10; 1 drivers -v0x1052a10_0 .net "out", 0 0, L_0x1256ef0; 1 drivers -L_0x1256770 .part L_0x1257340, 0, 1; -L_0x12568d0 .part L_0x1257340, 1, 1; -L_0x1256a10 .concat8 [ 1 1 0 0], L_0x1256700, L_0x1256b00; -L_0x1256c10 .part L_0x1257340, 2, 1; -L_0x1256d70 .part L_0x1257340, 3, 1; -L_0x1256f60 .part L_0x1256a10, 0, 1; -L_0x1257110 .part L_0x1256a10, 1, 1; -S_0x1053320 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1046ca0; +L_0x2d39970/d .functor OR 1, L_0x2d399e0, L_0x2d39b40, C4<0>, C4<0>; +L_0x2d39970 .delay 1 (30000,30000,30000) L_0x2d39970/d; +L_0x2d39d70/d .functor OR 1, L_0x2d39e80, L_0x2d39fe0, C4<0>, C4<0>; +L_0x2d39d70 .delay 1 (30000,30000,30000) L_0x2d39d70/d; +L_0x2d3a160/d .functor OR 1, L_0x2d3a1d0, L_0x2d3a380, C4<0>, C4<0>; +L_0x2d3a160 .delay 1 (30000,30000,30000) L_0x2d3a160/d; +v0x2b1b700_0 .net *"_s0", 0 0, L_0x2d39970; 1 drivers +v0x2b1b800_0 .net *"_s10", 0 0, L_0x2d39e80; 1 drivers +v0x2b1b8e0_0 .net *"_s12", 0 0, L_0x2d39fe0; 1 drivers +v0x2b1b9d0_0 .net *"_s14", 0 0, L_0x2d3a1d0; 1 drivers +v0x2b1bab0_0 .net *"_s16", 0 0, L_0x2d3a380; 1 drivers +v0x2b1bbe0_0 .net *"_s3", 0 0, L_0x2d399e0; 1 drivers +v0x2b1bcc0_0 .net *"_s5", 0 0, L_0x2d39b40; 1 drivers +v0x2b1bda0_0 .net *"_s6", 0 0, L_0x2d39d70; 1 drivers +v0x2b1be80_0 .net "in", 3 0, L_0x2d3a5b0; 1 drivers +v0x2b1bff0_0 .net "ors", 1 0, L_0x2d39c80; 1 drivers +v0x2b1c0d0_0 .net "out", 0 0, L_0x2d3a160; 1 drivers +L_0x2d399e0 .part L_0x2d3a5b0, 0, 1; +L_0x2d39b40 .part L_0x2d3a5b0, 1, 1; +L_0x2d39c80 .concat8 [ 1 1 0 0], L_0x2d39970, L_0x2d39d70; +L_0x2d39e80 .part L_0x2d3a5b0, 2, 1; +L_0x2d39fe0 .part L_0x2d3a5b0, 3, 1; +L_0x2d3a1d0 .part L_0x2d39c80, 0, 1; +L_0x2d3a380 .part L_0x2d39c80, 1, 1; +S_0x2b1c9e0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b10350; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -4934,80 +5215,80 @@ S_0x1053320 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1046ca0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1252bb0/d .functor XNOR 1, L_0x125b280, L_0x125b3e0, C4<0>, C4<0>; -L_0x1252bb0 .delay 1 (20000,20000,20000) L_0x1252bb0/d; -L_0x1252e20/d .functor AND 1, L_0x125b280, L_0x1251bb0, C4<1>, C4<1>; -L_0x1252e20 .delay 1 (30000,30000,30000) L_0x1252e20/d; -L_0x1252e90/d .functor AND 1, L_0x1252bb0, L_0x1251980, C4<1>, C4<1>; -L_0x1252e90 .delay 1 (30000,30000,30000) L_0x1252e90/d; -L_0x1252ff0/d .functor OR 1, L_0x1252e90, L_0x1252e20, C4<0>, C4<0>; -L_0x1252ff0 .delay 1 (30000,30000,30000) L_0x1252ff0/d; -v0x10535d0_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers -v0x10536c0_0 .net "a_", 0 0, L_0x1251aa0; alias, 1 drivers -v0x1053780_0 .net "b", 0 0, L_0x125b3e0; alias, 1 drivers -v0x1053870_0 .net "b_", 0 0, L_0x1251bb0; alias, 1 drivers -v0x1053910_0 .net "carryin", 0 0, L_0x1251980; alias, 1 drivers -v0x1053a50_0 .net "eq", 0 0, L_0x1252bb0; 1 drivers -v0x1053b10_0 .net "lt", 0 0, L_0x1252e20; 1 drivers -v0x1053bd0_0 .net "out", 0 0, L_0x1252ff0; 1 drivers -v0x1053c90_0 .net "w0", 0 0, L_0x1252e90; 1 drivers -S_0x1053ee0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1046ca0; +L_0x2d35400/d .functor XNOR 1, L_0x2d3e4f0, L_0x2d3e650, C4<0>, C4<0>; +L_0x2d35400 .delay 1 (20000,20000,20000) L_0x2d35400/d; +L_0x2d35580/d .functor AND 1, L_0x2d3e4f0, L_0x2d34140, C4<1>, C4<1>; +L_0x2d35580 .delay 1 (30000,30000,30000) L_0x2d35580/d; +L_0x2d356e0/d .functor AND 1, L_0x2d35400, L_0x2d33fd0, C4<1>, C4<1>; +L_0x2d356e0 .delay 1 (30000,30000,30000) L_0x2d356e0/d; +L_0x2d357f0/d .functor OR 1, L_0x2d356e0, L_0x2d35580, C4<0>, C4<0>; +L_0x2d357f0 .delay 1 (30000,30000,30000) L_0x2d357f0/d; +v0x2b1cc90_0 .net "a", 0 0, L_0x2d3e4f0; alias, 1 drivers +v0x2b1cd80_0 .net "a_", 0 0, L_0x2d33db0; alias, 1 drivers +v0x2b1ce40_0 .net "b", 0 0, L_0x2d3e650; alias, 1 drivers +v0x2b1cf30_0 .net "b_", 0 0, L_0x2d34140; alias, 1 drivers +v0x2b1cfd0_0 .net "carryin", 0 0, L_0x2d33fd0; alias, 1 drivers +v0x2b1d110_0 .net "eq", 0 0, L_0x2d35400; 1 drivers +v0x2b1d1d0_0 .net "lt", 0 0, L_0x2d35580; 1 drivers +v0x2b1d290_0 .net "out", 0 0, L_0x2d357f0; 1 drivers +v0x2b1d350_0 .net "w0", 0 0, L_0x2d356e0; 1 drivers +S_0x2b1d5a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b10350; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1252990/d .functor OR 1, L_0x12524e0, L_0x1055140, C4<0>, C4<0>; -L_0x1252990 .delay 1 (30000,30000,30000) L_0x1252990/d; -v0x1054cd0_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers -v0x1054e20_0 .net "b", 0 0, L_0x1251bb0; alias, 1 drivers -v0x1054ee0_0 .net "c1", 0 0, L_0x12524e0; 1 drivers -v0x1054f80_0 .net "c2", 0 0, L_0x1055140; 1 drivers -v0x1055050_0 .net "carryin", 0 0, L_0x1251980; alias, 1 drivers -v0x10551d0_0 .net "carryout", 0 0, L_0x1252990; 1 drivers -v0x1055270_0 .net "s1", 0 0, L_0x1252420; 1 drivers -v0x1055310_0 .net "sum", 0 0, L_0x1252640; 1 drivers -S_0x1054130 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1053ee0; +L_0x2d34fe0/d .functor OR 1, L_0x2d34b30, L_0x2b1e800, C4<0>, C4<0>; +L_0x2d34fe0 .delay 1 (30000,30000,30000) L_0x2d34fe0/d; +v0x2b1e390_0 .net "a", 0 0, L_0x2d3e4f0; alias, 1 drivers +v0x2b1e4e0_0 .net "b", 0 0, L_0x2d34140; alias, 1 drivers +v0x2b1e5a0_0 .net "c1", 0 0, L_0x2d34b30; 1 drivers +v0x2b1e640_0 .net "c2", 0 0, L_0x2b1e800; 1 drivers +v0x2b1e710_0 .net "carryin", 0 0, L_0x2d33fd0; alias, 1 drivers +v0x2b1e890_0 .net "carryout", 0 0, L_0x2d34fe0; 1 drivers +v0x2b1e930_0 .net "s1", 0 0, L_0x2d34a70; 1 drivers +v0x2b1e9d0_0 .net "sum", 0 0, L_0x2d34c90; 1 drivers +S_0x2b1d7f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b1d5a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1252420/d .functor XOR 1, L_0x125b280, L_0x1251bb0, C4<0>, C4<0>; -L_0x1252420 .delay 1 (30000,30000,30000) L_0x1252420/d; -L_0x12524e0/d .functor AND 1, L_0x125b280, L_0x1251bb0, C4<1>, C4<1>; -L_0x12524e0 .delay 1 (30000,30000,30000) L_0x12524e0/d; -v0x1054390_0 .net "a", 0 0, L_0x125b280; alias, 1 drivers -v0x1054450_0 .net "b", 0 0, L_0x1251bb0; alias, 1 drivers -v0x1054510_0 .net "carryout", 0 0, L_0x12524e0; alias, 1 drivers -v0x10545b0_0 .net "sum", 0 0, L_0x1252420; alias, 1 drivers -S_0x10546e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1053ee0; +L_0x2d34a70/d .functor XOR 1, L_0x2d3e4f0, L_0x2d34140, C4<0>, C4<0>; +L_0x2d34a70 .delay 1 (30000,30000,30000) L_0x2d34a70/d; +L_0x2d34b30/d .functor AND 1, L_0x2d3e4f0, L_0x2d34140, C4<1>, C4<1>; +L_0x2d34b30 .delay 1 (30000,30000,30000) L_0x2d34b30/d; +v0x2b1da50_0 .net "a", 0 0, L_0x2d3e4f0; alias, 1 drivers +v0x2b1db10_0 .net "b", 0 0, L_0x2d34140; alias, 1 drivers +v0x2b1dbd0_0 .net "carryout", 0 0, L_0x2d34b30; alias, 1 drivers +v0x2b1dc70_0 .net "sum", 0 0, L_0x2d34a70; alias, 1 drivers +S_0x2b1dda0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b1d5a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1252640/d .functor XOR 1, L_0x1252420, L_0x1251980, C4<0>, C4<0>; -L_0x1252640 .delay 1 (30000,30000,30000) L_0x1252640/d; -L_0x1055140/d .functor AND 1, L_0x1252420, L_0x1251980, C4<1>, C4<1>; -L_0x1055140 .delay 1 (30000,30000,30000) L_0x1055140/d; -v0x1054940_0 .net "a", 0 0, L_0x1252420; alias, 1 drivers -v0x1054a10_0 .net "b", 0 0, L_0x1251980; alias, 1 drivers -v0x1054ab0_0 .net "carryout", 0 0, L_0x1055140; alias, 1 drivers -v0x1054b80_0 .net "sum", 0 0, L_0x1252640; alias, 1 drivers -S_0x1056730 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1046990; - .timescale -9 -12; -L_0x2b0ab3d05918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05960 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x125b320/d .functor OR 1, L_0x2b0ab3d05918, L_0x2b0ab3d05960, C4<0>, C4<0>; -L_0x125b320 .delay 1 (30000,30000,30000) L_0x125b320/d; -v0x1056920_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05918; 1 drivers -v0x1056a00_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05960; 1 drivers -S_0x1056ae0 .scope generate, "alu_slices[9]" "alu_slices[9]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1056cf0 .param/l "i" 0 3 41, +C4<01001>; -S_0x1056db0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1056ae0; +L_0x2d34c90/d .functor XOR 1, L_0x2d34a70, L_0x2d33fd0, C4<0>, C4<0>; +L_0x2d34c90 .delay 1 (30000,30000,30000) L_0x2d34c90/d; +L_0x2b1e800/d .functor AND 1, L_0x2d34a70, L_0x2d33fd0, C4<1>, C4<1>; +L_0x2b1e800 .delay 1 (30000,30000,30000) L_0x2b1e800/d; +v0x2b1e000_0 .net "a", 0 0, L_0x2d34a70; alias, 1 drivers +v0x2b1e0d0_0 .net "b", 0 0, L_0x2d33fd0; alias, 1 drivers +v0x2b1e170_0 .net "carryout", 0 0, L_0x2b1e800; alias, 1 drivers +v0x2b1e240_0 .net "sum", 0 0, L_0x2d34c90; alias, 1 drivers +S_0x2b20a60 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b10040; + .timescale -9 -12; +L_0x2ac6110b8268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b82b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d345f0/d .functor OR 1, L_0x2ac6110b8268, L_0x2ac6110b82b0, C4<0>, C4<0>; +L_0x2d345f0 .delay 1 (30000,30000,30000) L_0x2d345f0/d; +v0x2b20c50_0 .net/2u *"_s0", 0 0, L_0x2ac6110b8268; 1 drivers +v0x2b20d30_0 .net/2u *"_s2", 0 0, L_0x2ac6110b82b0; 1 drivers +S_0x2b20e10 .scope generate, "alu_slices[9]" "alu_slices[9]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b21020 .param/l "i" 0 3 39, +C4<01001>; +S_0x2b210e0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b20e10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -5016,445 +5297,476 @@ S_0x1056db0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1056ae0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x125b650/d .functor NOT 1, L_0x1264f90, C4<0>, C4<0>, C4<0>; -L_0x125b650 .delay 1 (10000,10000,10000) L_0x125b650/d; -L_0x1255360/d .functor NOT 1, L_0x125b480, C4<0>, C4<0>, C4<0>; -L_0x1255360 .delay 1 (10000,10000,10000) L_0x1255360/d; -L_0x125c800/d .functor XOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; -L_0x125c800 .delay 1 (30000,30000,30000) L_0x125c800/d; -L_0x2b0ab3d059a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d059f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x125ceb0/d .functor OR 1, L_0x2b0ab3d059a8, L_0x2b0ab3d059f0, C4<0>, C4<0>; -L_0x125ceb0 .delay 1 (30000,30000,30000) L_0x125ceb0/d; -L_0x125d0b0/d .functor AND 1, L_0x1264f90, L_0x125b480, C4<1>, C4<1>; -L_0x125d0b0 .delay 1 (30000,30000,30000) L_0x125d0b0/d; -L_0x125d170/d .functor NAND 1, L_0x1264f90, L_0x125b480, C4<1>, C4<1>; -L_0x125d170 .delay 1 (20000,20000,20000) L_0x125d170/d; -L_0x125d2d0/d .functor XOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; -L_0x125d2d0 .delay 1 (20000,20000,20000) L_0x125d2d0/d; -L_0x125d780/d .functor OR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; -L_0x125d780 .delay 1 (30000,30000,30000) L_0x125d780/d; -L_0x1264e90/d .functor NOT 1, L_0x12610f0, C4<0>, C4<0>, C4<0>; -L_0x1264e90 .delay 1 (10000,10000,10000) L_0x1264e90/d; -v0x10654a0_0 .net "A", 0 0, L_0x1264f90; 1 drivers -v0x1065560_0 .net "A_", 0 0, L_0x125b650; 1 drivers -v0x1065620_0 .net "B", 0 0, L_0x125b480; 1 drivers -v0x10656f0_0 .net "B_", 0 0, L_0x1255360; 1 drivers -v0x1065790_0 .net *"_s12", 0 0, L_0x125ceb0; 1 drivers -v0x1065880_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d059a8; 1 drivers -v0x1065940_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d059f0; 1 drivers -v0x1065a20_0 .net *"_s18", 0 0, L_0x125d0b0; 1 drivers -v0x1065b00_0 .net *"_s20", 0 0, L_0x125d170; 1 drivers -v0x1065c70_0 .net *"_s22", 0 0, L_0x125d2d0; 1 drivers -v0x1065d50_0 .net *"_s24", 0 0, L_0x125d780; 1 drivers -o0x2b0ab3cba298 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1065e30_0 name=_s30 -o0x2b0ab3cba2c8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1065f10_0 name=_s32 -v0x1065ff0_0 .net *"_s8", 0 0, L_0x125c800; 1 drivers -v0x10660d0_0 .net "carryin", 0 0, L_0x12651e0; 1 drivers -v0x1066170_0 .net "carryout", 0 0, L_0x1264b30; 1 drivers -v0x1066210_0 .net "carryouts", 7 0, L_0x1353d70; 1 drivers -v0x10663c0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1066460_0 .net "result", 0 0, L_0x12610f0; 1 drivers -v0x1066550_0 .net "results", 7 0, L_0x125d550; 1 drivers -v0x1066660_0 .net "zero", 0 0, L_0x1264e90; 1 drivers -LS_0x125d550_0_0 .concat8 [ 1 1 1 1], L_0x125bd20, L_0x125c350, L_0x125c800, L_0x125ceb0; -LS_0x125d550_0_4 .concat8 [ 1 1 1 1], L_0x125d0b0, L_0x125d170, L_0x125d2d0, L_0x125d780; -L_0x125d550 .concat8 [ 4 4 0 0], LS_0x125d550_0_0, LS_0x125d550_0_4; -LS_0x1353d70_0_0 .concat [ 1 1 1 1], L_0x125bfd0, L_0x125c6a0, o0x2b0ab3cba298, L_0x125cd00; -LS_0x1353d70_0_4 .concat [ 4 0 0 0], o0x2b0ab3cba2c8; -L_0x1353d70 .concat [ 4 4 0 0], LS_0x1353d70_0_0, LS_0x1353d70_0_4; -S_0x1057030 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1056db0; +L_0x2d3e870/d .functor NOT 1, L_0x2d491e0, C4<0>, C4<0>, C4<0>; +L_0x2d3e870 .delay 1 (10000,10000,10000) L_0x2d3e870/d; +L_0x2d3e9d0/d .functor NOT 1, L_0x2d3e6f0, C4<0>, C4<0>, C4<0>; +L_0x2d3e9d0 .delay 1 (10000,10000,10000) L_0x2d3e9d0/d; +L_0x2d3fa20/d .functor XOR 1, L_0x2d491e0, L_0x2d3e6f0, C4<0>, C4<0>; +L_0x2d3fa20 .delay 1 (30000,30000,30000) L_0x2d3fa20/d; +L_0x2ac6110b82f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8340 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d3fae0/d .functor OR 1, L_0x2ac6110b82f8, L_0x2ac6110b8340, C4<0>, C4<0>; +L_0x2d3fae0 .delay 1 (30000,30000,30000) L_0x2d3fae0/d; +L_0x2ac6110b8388 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b83d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d40280/d .functor OR 1, L_0x2ac6110b8388, L_0x2ac6110b83d0, C4<0>, C4<0>; +L_0x2d40280 .delay 1 (30000,30000,30000) L_0x2d40280/d; +L_0x2d40480/d .functor AND 1, L_0x2d491e0, L_0x2d3e6f0, C4<1>, C4<1>; +L_0x2d40480 .delay 1 (30000,30000,30000) L_0x2d40480/d; +L_0x2ac6110b8418 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8460 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d40540/d .functor OR 1, L_0x2ac6110b8418, L_0x2ac6110b8460, C4<0>, C4<0>; +L_0x2d40540 .delay 1 (30000,30000,30000) L_0x2d40540/d; +L_0x2d0ba30/d .functor NAND 1, L_0x2d491e0, L_0x2d3e6f0, C4<1>, C4<1>; +L_0x2d0ba30 .delay 1 (20000,20000,20000) L_0x2d0ba30/d; +L_0x2ac6110b84a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b84f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d0bb40/d .functor OR 1, L_0x2ac6110b84a8, L_0x2ac6110b84f0, C4<0>, C4<0>; +L_0x2d0bb40 .delay 1 (30000,30000,30000) L_0x2d0bb40/d; +L_0x2d0bca0/d .functor NOR 1, L_0x2d491e0, L_0x2d3e6f0, C4<0>, C4<0>; +L_0x2d0bca0 .delay 1 (20000,20000,20000) L_0x2d0bca0/d; +L_0x2ac6110b8538 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8580 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d3ee40/d .functor OR 1, L_0x2ac6110b8538, L_0x2ac6110b8580, C4<0>, C4<0>; +L_0x2d3ee40 .delay 1 (30000,30000,30000) L_0x2d3ee40/d; +L_0x2d414f0/d .functor OR 1, L_0x2d491e0, L_0x2d3e6f0, C4<0>, C4<0>; +L_0x2d414f0 .delay 1 (30000,30000,30000) L_0x2d414f0/d; +L_0x2ac6110b85c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8610 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d419e0/d .functor OR 1, L_0x2ac6110b85c8, L_0x2ac6110b8610, C4<0>, C4<0>; +L_0x2d419e0 .delay 1 (30000,30000,30000) L_0x2d419e0/d; +L_0x2d490e0/d .functor NOT 1, L_0x2d45340, C4<0>, C4<0>, C4<0>; +L_0x2d490e0 .delay 1 (10000,10000,10000) L_0x2d490e0/d; +v0x2b2f810_0 .net "A", 0 0, L_0x2d491e0; 1 drivers +v0x2b2f8d0_0 .net "A_", 0 0, L_0x2d3e870; 1 drivers +v0x2b2f990_0 .net "B", 0 0, L_0x2d3e6f0; 1 drivers +v0x2b2fa60_0 .net "B_", 0 0, L_0x2d3e9d0; 1 drivers +v0x2b2fb00_0 .net *"_s11", 0 0, L_0x2d3fae0; 1 drivers +v0x2b2fbf0_0 .net/2s *"_s13", 0 0, L_0x2ac6110b82f8; 1 drivers +v0x2b2fcb0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b8340; 1 drivers +v0x2b2fd90_0 .net *"_s19", 0 0, L_0x2d40280; 1 drivers +v0x2b2fe70_0 .net/2s *"_s21", 0 0, L_0x2ac6110b8388; 1 drivers +v0x2b2ffe0_0 .net/2s *"_s23", 0 0, L_0x2ac6110b83d0; 1 drivers +v0x2b300c0_0 .net *"_s25", 0 0, L_0x2d40480; 1 drivers +v0x2b301a0_0 .net *"_s28", 0 0, L_0x2d40540; 1 drivers +v0x2b30280_0 .net/2s *"_s30", 0 0, L_0x2ac6110b8418; 1 drivers +v0x2b30360_0 .net/2s *"_s32", 0 0, L_0x2ac6110b8460; 1 drivers +v0x2b30440_0 .net *"_s34", 0 0, L_0x2d0ba30; 1 drivers +v0x2b30520_0 .net *"_s37", 0 0, L_0x2d0bb40; 1 drivers +v0x2b30600_0 .net/2s *"_s39", 0 0, L_0x2ac6110b84a8; 1 drivers +v0x2b307b0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b84f0; 1 drivers +v0x2b30850_0 .net *"_s43", 0 0, L_0x2d0bca0; 1 drivers +v0x2b30930_0 .net *"_s46", 0 0, L_0x2d3ee40; 1 drivers +v0x2b30a10_0 .net/2s *"_s48", 0 0, L_0x2ac6110b8538; 1 drivers +v0x2b30af0_0 .net/2s *"_s50", 0 0, L_0x2ac6110b8580; 1 drivers +v0x2b30bd0_0 .net *"_s52", 0 0, L_0x2d414f0; 1 drivers +v0x2b30cb0_0 .net *"_s56", 0 0, L_0x2d419e0; 1 drivers +v0x2b30d90_0 .net/2s *"_s59", 0 0, L_0x2ac6110b85c8; 1 drivers +v0x2b30e70_0 .net/2s *"_s61", 0 0, L_0x2ac6110b8610; 1 drivers +v0x2b30f50_0 .net *"_s8", 0 0, L_0x2d3fa20; 1 drivers +v0x2b31030_0 .net "carryin", 0 0, L_0x2d49430; 1 drivers +v0x2b310d0_0 .net "carryout", 0 0, L_0x2d48d80; 1 drivers +v0x2b31170_0 .net "carryouts", 7 0, L_0x2d41670; 1 drivers +v0x2b31280_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b31340_0 .net "result", 0 0, L_0x2d45340; 1 drivers +v0x2b31430_0 .net "results", 7 0, L_0x2d412c0; 1 drivers +v0x2b30710_0 .net "zero", 0 0, L_0x2d490e0; 1 drivers +LS_0x2d412c0_0_0 .concat8 [ 1 1 1 1], L_0x2d3eef0, L_0x2d3f520, L_0x2d3fa20, L_0x2d40280; +LS_0x2d412c0_0_4 .concat8 [ 1 1 1 1], L_0x2d40480, L_0x2d0ba30, L_0x2d0bca0, L_0x2d414f0; +L_0x2d412c0 .concat8 [ 4 4 0 0], LS_0x2d412c0_0_0, LS_0x2d412c0_0_4; +LS_0x2d41670_0_0 .concat8 [ 1 1 1 1], L_0x2d3f1a0, L_0x2d3f8c0, L_0x2d3fae0, L_0x2d400d0; +LS_0x2d41670_0_4 .concat8 [ 1 1 1 1], L_0x2d40540, L_0x2d0bb40, L_0x2d3ee40, L_0x2d419e0; +L_0x2d41670 .concat8 [ 4 4 0 0], LS_0x2d41670_0_0, LS_0x2d41670_0_4; +S_0x2b21360 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b210e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x125bfd0/d .functor OR 1, L_0x125bab0, L_0x125be70, C4<0>, C4<0>; -L_0x125bfd0 .delay 1 (30000,30000,30000) L_0x125bfd0/d; -v0x1057e60_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers -v0x1057f20_0 .net "b", 0 0, L_0x125b480; alias, 1 drivers -v0x1057ff0_0 .net "c1", 0 0, L_0x125bab0; 1 drivers -v0x10580f0_0 .net "c2", 0 0, L_0x125be70; 1 drivers -v0x10581c0_0 .net "carryin", 0 0, L_0x12651e0; alias, 1 drivers -v0x10582b0_0 .net "carryout", 0 0, L_0x125bfd0; 1 drivers -v0x1058350_0 .net "s1", 0 0, L_0x125ba40; 1 drivers -v0x1058440_0 .net "sum", 0 0, L_0x125bd20; 1 drivers -S_0x10572a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1057030; +L_0x2d3f1a0/d .functor OR 1, L_0x2d3ec80, L_0x2d3f040, C4<0>, C4<0>; +L_0x2d3f1a0 .delay 1 (30000,30000,30000) L_0x2d3f1a0/d; +v0x2b22190_0 .net "a", 0 0, L_0x2d491e0; alias, 1 drivers +v0x2b22250_0 .net "b", 0 0, L_0x2d3e6f0; alias, 1 drivers +v0x2b22320_0 .net "c1", 0 0, L_0x2d3ec80; 1 drivers +v0x2b22420_0 .net "c2", 0 0, L_0x2d3f040; 1 drivers +v0x2b224f0_0 .net "carryin", 0 0, L_0x2d49430; alias, 1 drivers +v0x2b225e0_0 .net "carryout", 0 0, L_0x2d3f1a0; 1 drivers +v0x2b22680_0 .net "s1", 0 0, L_0x2d3ebc0; 1 drivers +v0x2b22770_0 .net "sum", 0 0, L_0x2d3eef0; 1 drivers +S_0x2b215d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b21360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x125ba40/d .functor XOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; -L_0x125ba40 .delay 1 (30000,30000,30000) L_0x125ba40/d; -L_0x125bab0/d .functor AND 1, L_0x1264f90, L_0x125b480, C4<1>, C4<1>; -L_0x125bab0 .delay 1 (30000,30000,30000) L_0x125bab0/d; -v0x1057500_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers -v0x10575e0_0 .net "b", 0 0, L_0x125b480; alias, 1 drivers -v0x10576a0_0 .net "carryout", 0 0, L_0x125bab0; alias, 1 drivers -v0x1057740_0 .net "sum", 0 0, L_0x125ba40; alias, 1 drivers -S_0x1057880 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1057030; +L_0x2d3ebc0/d .functor XOR 1, L_0x2d491e0, L_0x2d3e6f0, C4<0>, C4<0>; +L_0x2d3ebc0 .delay 1 (30000,30000,30000) L_0x2d3ebc0/d; +L_0x2d3ec80/d .functor AND 1, L_0x2d491e0, L_0x2d3e6f0, C4<1>, C4<1>; +L_0x2d3ec80 .delay 1 (30000,30000,30000) L_0x2d3ec80/d; +v0x2b21830_0 .net "a", 0 0, L_0x2d491e0; alias, 1 drivers +v0x2b21910_0 .net "b", 0 0, L_0x2d3e6f0; alias, 1 drivers +v0x2b219d0_0 .net "carryout", 0 0, L_0x2d3ec80; alias, 1 drivers +v0x2b21a70_0 .net "sum", 0 0, L_0x2d3ebc0; alias, 1 drivers +S_0x2b21bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b21360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x125bd20/d .functor XOR 1, L_0x125ba40, L_0x12651e0, C4<0>, C4<0>; -L_0x125bd20 .delay 1 (30000,30000,30000) L_0x125bd20/d; -L_0x125be70/d .functor AND 1, L_0x125ba40, L_0x12651e0, C4<1>, C4<1>; -L_0x125be70 .delay 1 (30000,30000,30000) L_0x125be70/d; -v0x1057ae0_0 .net "a", 0 0, L_0x125ba40; alias, 1 drivers -v0x1057b80_0 .net "b", 0 0, L_0x12651e0; alias, 1 drivers -v0x1057c20_0 .net "carryout", 0 0, L_0x125be70; alias, 1 drivers -v0x1057cf0_0 .net "sum", 0 0, L_0x125bd20; alias, 1 drivers -S_0x1058510 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1056db0; +L_0x2d3eef0/d .functor XOR 1, L_0x2d3ebc0, L_0x2d49430, C4<0>, C4<0>; +L_0x2d3eef0 .delay 1 (30000,30000,30000) L_0x2d3eef0/d; +L_0x2d3f040/d .functor AND 1, L_0x2d3ebc0, L_0x2d49430, C4<1>, C4<1>; +L_0x2d3f040 .delay 1 (30000,30000,30000) L_0x2d3f040/d; +v0x2b21e10_0 .net "a", 0 0, L_0x2d3ebc0; alias, 1 drivers +v0x2b21eb0_0 .net "b", 0 0, L_0x2d49430; alias, 1 drivers +v0x2b21f50_0 .net "carryout", 0 0, L_0x2d3f040; alias, 1 drivers +v0x2b22020_0 .net "sum", 0 0, L_0x2d3eef0; alias, 1 drivers +S_0x2b22840 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b210e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x105d900_0 .net "ands", 7 0, L_0x1262b30; 1 drivers -v0x105da10_0 .net "in", 7 0, L_0x1353d70; alias, 1 drivers -v0x105dad0_0 .net "out", 0 0, L_0x1264b30; alias, 1 drivers -v0x105dba0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1058730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1058510; +v0x2b27c30_0 .net "ands", 7 0, L_0x2d46d80; 1 drivers +v0x2b27d40_0 .net "in", 7 0, L_0x2d41670; alias, 1 drivers +v0x2b27e00_0 .net "out", 0 0, L_0x2d48d80; alias, 1 drivers +v0x2b27ed0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b22a60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b22840; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x105ae60_0 .net "A", 7 0, L_0x1353d70; alias, 1 drivers -v0x105af60_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x105b020_0 .net *"_s0", 0 0, L_0x1261450; 1 drivers -v0x105b0e0_0 .net *"_s12", 0 0, L_0x1261dc0; 1 drivers -v0x105b1c0_0 .net *"_s16", 0 0, L_0x1262120; 1 drivers -v0x105b2f0_0 .net *"_s20", 0 0, L_0x1262430; 1 drivers -v0x105b3d0_0 .net *"_s24", 0 0, L_0x1262820; 1 drivers -v0x105b4b0_0 .net *"_s28", 0 0, L_0x12627b0; 1 drivers -v0x105b590_0 .net *"_s4", 0 0, L_0x1261760; 1 drivers -v0x105b700_0 .net *"_s8", 0 0, L_0x1261ab0; 1 drivers -v0x105b7e0_0 .net "out", 7 0, L_0x1262b30; alias, 1 drivers -L_0x1261510 .part L_0x1353d70, 0, 1; -L_0x1261670 .part v0x12010b0_0, 0, 1; -L_0x1261820 .part L_0x1353d70, 1, 1; -L_0x1261a10 .part v0x12010b0_0, 1, 1; -L_0x1261b70 .part L_0x1353d70, 2, 1; -L_0x1261cd0 .part v0x12010b0_0, 2, 1; -L_0x1261e80 .part L_0x1353d70, 3, 1; -L_0x1261fe0 .part v0x12010b0_0, 3, 1; -L_0x12621e0 .part L_0x1353d70, 4, 1; -L_0x1262340 .part v0x12010b0_0, 4, 1; -L_0x12624a0 .part L_0x1353d70, 5, 1; -L_0x1262710 .part v0x12010b0_0, 5, 1; -L_0x12628e0 .part L_0x1353d70, 6, 1; -L_0x1262a40 .part v0x12010b0_0, 6, 1; -LS_0x1262b30_0_0 .concat8 [ 1 1 1 1], L_0x1261450, L_0x1261760, L_0x1261ab0, L_0x1261dc0; -LS_0x1262b30_0_4 .concat8 [ 1 1 1 1], L_0x1262120, L_0x1262430, L_0x1262820, L_0x12627b0; -L_0x1262b30 .concat8 [ 4 4 0 0], LS_0x1262b30_0_0, LS_0x1262b30_0_4; -L_0x1262ef0 .part L_0x1353d70, 7, 1; -L_0x12630e0 .part v0x12010b0_0, 7, 1; -S_0x1058990 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x1058ba0 .param/l "i" 0 4 54, +C4<00>; -L_0x1261450/d .functor AND 1, L_0x1261510, L_0x1261670, C4<1>, C4<1>; -L_0x1261450 .delay 1 (30000,30000,30000) L_0x1261450/d; -v0x1058c80_0 .net *"_s0", 0 0, L_0x1261510; 1 drivers -v0x1058d60_0 .net *"_s1", 0 0, L_0x1261670; 1 drivers -S_0x1058e40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x1059050 .param/l "i" 0 4 54, +C4<01>; -L_0x1261760/d .functor AND 1, L_0x1261820, L_0x1261a10, C4<1>, C4<1>; -L_0x1261760 .delay 1 (30000,30000,30000) L_0x1261760/d; -v0x1059110_0 .net *"_s0", 0 0, L_0x1261820; 1 drivers -v0x10591f0_0 .net *"_s1", 0 0, L_0x1261a10; 1 drivers -S_0x10592d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x10594e0 .param/l "i" 0 4 54, +C4<010>; -L_0x1261ab0/d .functor AND 1, L_0x1261b70, L_0x1261cd0, C4<1>, C4<1>; -L_0x1261ab0 .delay 1 (30000,30000,30000) L_0x1261ab0/d; -v0x1059580_0 .net *"_s0", 0 0, L_0x1261b70; 1 drivers -v0x1059660_0 .net *"_s1", 0 0, L_0x1261cd0; 1 drivers -S_0x1059740 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x1059950 .param/l "i" 0 4 54, +C4<011>; -L_0x1261dc0/d .functor AND 1, L_0x1261e80, L_0x1261fe0, C4<1>, C4<1>; -L_0x1261dc0 .delay 1 (30000,30000,30000) L_0x1261dc0/d; -v0x1059a10_0 .net *"_s0", 0 0, L_0x1261e80; 1 drivers -v0x1059af0_0 .net *"_s1", 0 0, L_0x1261fe0; 1 drivers -S_0x1059bd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x1059e30 .param/l "i" 0 4 54, +C4<0100>; -L_0x1262120/d .functor AND 1, L_0x12621e0, L_0x1262340, C4<1>, C4<1>; -L_0x1262120 .delay 1 (30000,30000,30000) L_0x1262120/d; -v0x1059ef0_0 .net *"_s0", 0 0, L_0x12621e0; 1 drivers -v0x1059fd0_0 .net *"_s1", 0 0, L_0x1262340; 1 drivers -S_0x105a0b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x105a2c0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1262430/d .functor AND 1, L_0x12624a0, L_0x1262710, C4<1>, C4<1>; -L_0x1262430 .delay 1 (30000,30000,30000) L_0x1262430/d; -v0x105a380_0 .net *"_s0", 0 0, L_0x12624a0; 1 drivers -v0x105a460_0 .net *"_s1", 0 0, L_0x1262710; 1 drivers -S_0x105a540 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x105a750 .param/l "i" 0 4 54, +C4<0110>; -L_0x1262820/d .functor AND 1, L_0x12628e0, L_0x1262a40, C4<1>, C4<1>; -L_0x1262820 .delay 1 (30000,30000,30000) L_0x1262820/d; -v0x105a810_0 .net *"_s0", 0 0, L_0x12628e0; 1 drivers -v0x105a8f0_0 .net *"_s1", 0 0, L_0x1262a40; 1 drivers -S_0x105a9d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1058730; - .timescale -9 -12; -P_0x105abe0 .param/l "i" 0 4 54, +C4<0111>; -L_0x12627b0/d .functor AND 1, L_0x1262ef0, L_0x12630e0, C4<1>, C4<1>; -L_0x12627b0 .delay 1 (30000,30000,30000) L_0x12627b0/d; -v0x105aca0_0 .net *"_s0", 0 0, L_0x1262ef0; 1 drivers -v0x105ad80_0 .net *"_s1", 0 0, L_0x12630e0; 1 drivers -S_0x105b940 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1058510; +v0x2b25190_0 .net "A", 7 0, L_0x2d41670; alias, 1 drivers +v0x2b25290_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b25350_0 .net *"_s0", 0 0, L_0x2d456a0; 1 drivers +v0x2b25410_0 .net *"_s12", 0 0, L_0x2d46010; 1 drivers +v0x2b254f0_0 .net *"_s16", 0 0, L_0x2d46370; 1 drivers +v0x2b25620_0 .net *"_s20", 0 0, L_0x2d46740; 1 drivers +v0x2b25700_0 .net *"_s24", 0 0, L_0x2d46a70; 1 drivers +v0x2b257e0_0 .net *"_s28", 0 0, L_0x2d46a00; 1 drivers +v0x2b258c0_0 .net *"_s4", 0 0, L_0x2d459f0; 1 drivers +v0x2b25a30_0 .net *"_s8", 0 0, L_0x2d45d00; 1 drivers +v0x2b25b10_0 .net "out", 7 0, L_0x2d46d80; alias, 1 drivers +L_0x2d45760 .part L_0x2d41670, 0, 1; +L_0x2d45950 .part v0x2cdd2e0_0, 0, 1; +L_0x2d45ab0 .part L_0x2d41670, 1, 1; +L_0x2d45c10 .part v0x2cdd2e0_0, 1, 1; +L_0x2d45dc0 .part L_0x2d41670, 2, 1; +L_0x2d45f20 .part v0x2cdd2e0_0, 2, 1; +L_0x2d460d0 .part L_0x2d41670, 3, 1; +L_0x2d46230 .part v0x2cdd2e0_0, 3, 1; +L_0x2d46430 .part L_0x2d41670, 4, 1; +L_0x2d466a0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d467b0 .part L_0x2d41670, 5, 1; +L_0x2d46910 .part v0x2cdd2e0_0, 5, 1; +L_0x2d46b30 .part L_0x2d41670, 6, 1; +L_0x2d46c90 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d46d80_0_0 .concat8 [ 1 1 1 1], L_0x2d456a0, L_0x2d459f0, L_0x2d45d00, L_0x2d46010; +LS_0x2d46d80_0_4 .concat8 [ 1 1 1 1], L_0x2d46370, L_0x2d46740, L_0x2d46a70, L_0x2d46a00; +L_0x2d46d80 .concat8 [ 4 4 0 0], LS_0x2d46d80_0_0, LS_0x2d46d80_0_4; +L_0x2d47140 .part L_0x2d41670, 7, 1; +L_0x2d47330 .part v0x2cdd2e0_0, 7, 1; +S_0x2b22cc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b22ed0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d456a0/d .functor AND 1, L_0x2d45760, L_0x2d45950, C4<1>, C4<1>; +L_0x2d456a0 .delay 1 (30000,30000,30000) L_0x2d456a0/d; +v0x2b22fb0_0 .net *"_s0", 0 0, L_0x2d45760; 1 drivers +v0x2b23090_0 .net *"_s1", 0 0, L_0x2d45950; 1 drivers +S_0x2b23170 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b23380 .param/l "i" 0 4 54, +C4<01>; +L_0x2d459f0/d .functor AND 1, L_0x2d45ab0, L_0x2d45c10, C4<1>, C4<1>; +L_0x2d459f0 .delay 1 (30000,30000,30000) L_0x2d459f0/d; +v0x2b23440_0 .net *"_s0", 0 0, L_0x2d45ab0; 1 drivers +v0x2b23520_0 .net *"_s1", 0 0, L_0x2d45c10; 1 drivers +S_0x2b23600 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b23810 .param/l "i" 0 4 54, +C4<010>; +L_0x2d45d00/d .functor AND 1, L_0x2d45dc0, L_0x2d45f20, C4<1>, C4<1>; +L_0x2d45d00 .delay 1 (30000,30000,30000) L_0x2d45d00/d; +v0x2b238b0_0 .net *"_s0", 0 0, L_0x2d45dc0; 1 drivers +v0x2b23990_0 .net *"_s1", 0 0, L_0x2d45f20; 1 drivers +S_0x2b23a70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b23c80 .param/l "i" 0 4 54, +C4<011>; +L_0x2d46010/d .functor AND 1, L_0x2d460d0, L_0x2d46230, C4<1>, C4<1>; +L_0x2d46010 .delay 1 (30000,30000,30000) L_0x2d46010/d; +v0x2b23d40_0 .net *"_s0", 0 0, L_0x2d460d0; 1 drivers +v0x2b23e20_0 .net *"_s1", 0 0, L_0x2d46230; 1 drivers +S_0x2b23f00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b24160 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d46370/d .functor AND 1, L_0x2d46430, L_0x2d466a0, C4<1>, C4<1>; +L_0x2d46370 .delay 1 (30000,30000,30000) L_0x2d46370/d; +v0x2b24220_0 .net *"_s0", 0 0, L_0x2d46430; 1 drivers +v0x2b24300_0 .net *"_s1", 0 0, L_0x2d466a0; 1 drivers +S_0x2b243e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b245f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d46740/d .functor AND 1, L_0x2d467b0, L_0x2d46910, C4<1>, C4<1>; +L_0x2d46740 .delay 1 (30000,30000,30000) L_0x2d46740/d; +v0x2b246b0_0 .net *"_s0", 0 0, L_0x2d467b0; 1 drivers +v0x2b24790_0 .net *"_s1", 0 0, L_0x2d46910; 1 drivers +S_0x2b24870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b24a80 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d46a70/d .functor AND 1, L_0x2d46b30, L_0x2d46c90, C4<1>, C4<1>; +L_0x2d46a70 .delay 1 (30000,30000,30000) L_0x2d46a70/d; +v0x2b24b40_0 .net *"_s0", 0 0, L_0x2d46b30; 1 drivers +v0x2b24c20_0 .net *"_s1", 0 0, L_0x2d46c90; 1 drivers +S_0x2b24d00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b22a60; + .timescale -9 -12; +P_0x2b24f10 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d46a00/d .functor AND 1, L_0x2d47140, L_0x2d47330, C4<1>, C4<1>; +L_0x2d46a00 .delay 1 (30000,30000,30000) L_0x2d46a00/d; +v0x2b24fd0_0 .net *"_s0", 0 0, L_0x2d47140; 1 drivers +v0x2b250b0_0 .net *"_s1", 0 0, L_0x2d47330; 1 drivers +S_0x2b25c70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b22840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1264b30/d .functor OR 1, L_0x1264bf0, L_0x1264da0, C4<0>, C4<0>; -L_0x1264b30 .delay 1 (30000,30000,30000) L_0x1264b30/d; -v0x105d490_0 .net *"_s10", 0 0, L_0x1264bf0; 1 drivers -v0x105d570_0 .net *"_s12", 0 0, L_0x1264da0; 1 drivers -v0x105d650_0 .net "in", 7 0, L_0x1262b30; alias, 1 drivers -v0x105d720_0 .net "ors", 1 0, L_0x1264950; 1 drivers -v0x105d7e0_0 .net "out", 0 0, L_0x1264b30; alias, 1 drivers -L_0x1263d20 .part L_0x1262b30, 0, 4; -L_0x1264950 .concat8 [ 1 1 0 0], L_0x1263a10, L_0x1264640; -L_0x1264a90 .part L_0x1262b30, 4, 4; -L_0x1264bf0 .part L_0x1264950, 0, 1; -L_0x1264da0 .part L_0x1264950, 1, 1; -S_0x105bb00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x105b940; +L_0x2d48d80/d .functor OR 1, L_0x2d48e40, L_0x2d48ff0, C4<0>, C4<0>; +L_0x2d48d80 .delay 1 (30000,30000,30000) L_0x2d48d80/d; +v0x2b277c0_0 .net *"_s10", 0 0, L_0x2d48e40; 1 drivers +v0x2b278a0_0 .net *"_s12", 0 0, L_0x2d48ff0; 1 drivers +v0x2b27980_0 .net "in", 7 0, L_0x2d46d80; alias, 1 drivers +v0x2b27a50_0 .net "ors", 1 0, L_0x2d48ba0; 1 drivers +v0x2b27b10_0 .net "out", 0 0, L_0x2d48d80; alias, 1 drivers +L_0x2d47f70 .part L_0x2d46d80, 0, 4; +L_0x2d48ba0 .concat8 [ 1 1 0 0], L_0x2d47c60, L_0x2d48890; +L_0x2d48ce0 .part L_0x2d46d80, 4, 4; +L_0x2d48e40 .part L_0x2d48ba0, 0, 1; +L_0x2d48ff0 .part L_0x2d48ba0, 1, 1; +S_0x2b25e30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b25c70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12631d0/d .functor OR 1, L_0x1263290, L_0x12633f0, C4<0>, C4<0>; -L_0x12631d0 .delay 1 (30000,30000,30000) L_0x12631d0/d; -L_0x1263620/d .functor OR 1, L_0x1263730, L_0x1263890, C4<0>, C4<0>; -L_0x1263620 .delay 1 (30000,30000,30000) L_0x1263620/d; -L_0x1263a10/d .functor OR 1, L_0x1263a80, L_0x1263c30, C4<0>, C4<0>; -L_0x1263a10 .delay 1 (30000,30000,30000) L_0x1263a10/d; -v0x105bd50_0 .net *"_s0", 0 0, L_0x12631d0; 1 drivers -v0x105be50_0 .net *"_s10", 0 0, L_0x1263730; 1 drivers -v0x105bf30_0 .net *"_s12", 0 0, L_0x1263890; 1 drivers -v0x105bff0_0 .net *"_s14", 0 0, L_0x1263a80; 1 drivers -v0x105c0d0_0 .net *"_s16", 0 0, L_0x1263c30; 1 drivers -v0x105c200_0 .net *"_s3", 0 0, L_0x1263290; 1 drivers -v0x105c2e0_0 .net *"_s5", 0 0, L_0x12633f0; 1 drivers -v0x105c3c0_0 .net *"_s6", 0 0, L_0x1263620; 1 drivers -v0x105c4a0_0 .net "in", 3 0, L_0x1263d20; 1 drivers -v0x105c610_0 .net "ors", 1 0, L_0x1263530; 1 drivers -v0x105c6f0_0 .net "out", 0 0, L_0x1263a10; 1 drivers -L_0x1263290 .part L_0x1263d20, 0, 1; -L_0x12633f0 .part L_0x1263d20, 1, 1; -L_0x1263530 .concat8 [ 1 1 0 0], L_0x12631d0, L_0x1263620; -L_0x1263730 .part L_0x1263d20, 2, 1; -L_0x1263890 .part L_0x1263d20, 3, 1; -L_0x1263a80 .part L_0x1263530, 0, 1; -L_0x1263c30 .part L_0x1263530, 1, 1; -S_0x105c810 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x105b940; +L_0x2d47420/d .functor OR 1, L_0x2d474e0, L_0x2d47640, C4<0>, C4<0>; +L_0x2d47420 .delay 1 (30000,30000,30000) L_0x2d47420/d; +L_0x2d47870/d .functor OR 1, L_0x2d47980, L_0x2d47ae0, C4<0>, C4<0>; +L_0x2d47870 .delay 1 (30000,30000,30000) L_0x2d47870/d; +L_0x2d47c60/d .functor OR 1, L_0x2d47cd0, L_0x2d47e80, C4<0>, C4<0>; +L_0x2d47c60 .delay 1 (30000,30000,30000) L_0x2d47c60/d; +v0x2b26080_0 .net *"_s0", 0 0, L_0x2d47420; 1 drivers +v0x2b26180_0 .net *"_s10", 0 0, L_0x2d47980; 1 drivers +v0x2b26260_0 .net *"_s12", 0 0, L_0x2d47ae0; 1 drivers +v0x2b26320_0 .net *"_s14", 0 0, L_0x2d47cd0; 1 drivers +v0x2b26400_0 .net *"_s16", 0 0, L_0x2d47e80; 1 drivers +v0x2b26530_0 .net *"_s3", 0 0, L_0x2d474e0; 1 drivers +v0x2b26610_0 .net *"_s5", 0 0, L_0x2d47640; 1 drivers +v0x2b266f0_0 .net *"_s6", 0 0, L_0x2d47870; 1 drivers +v0x2b267d0_0 .net "in", 3 0, L_0x2d47f70; 1 drivers +v0x2b26940_0 .net "ors", 1 0, L_0x2d47780; 1 drivers +v0x2b26a20_0 .net "out", 0 0, L_0x2d47c60; 1 drivers +L_0x2d474e0 .part L_0x2d47f70, 0, 1; +L_0x2d47640 .part L_0x2d47f70, 1, 1; +L_0x2d47780 .concat8 [ 1 1 0 0], L_0x2d47420, L_0x2d47870; +L_0x2d47980 .part L_0x2d47f70, 2, 1; +L_0x2d47ae0 .part L_0x2d47f70, 3, 1; +L_0x2d47cd0 .part L_0x2d47780, 0, 1; +L_0x2d47e80 .part L_0x2d47780, 1, 1; +S_0x2b26b40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b25c70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1263e50/d .functor OR 1, L_0x1263ec0, L_0x1264020, C4<0>, C4<0>; -L_0x1263e50 .delay 1 (30000,30000,30000) L_0x1263e50/d; -L_0x1264250/d .functor OR 1, L_0x1264360, L_0x12644c0, C4<0>, C4<0>; -L_0x1264250 .delay 1 (30000,30000,30000) L_0x1264250/d; -L_0x1264640/d .functor OR 1, L_0x12646b0, L_0x1264860, C4<0>, C4<0>; -L_0x1264640 .delay 1 (30000,30000,30000) L_0x1264640/d; -v0x105c9d0_0 .net *"_s0", 0 0, L_0x1263e50; 1 drivers -v0x105cad0_0 .net *"_s10", 0 0, L_0x1264360; 1 drivers -v0x105cbb0_0 .net *"_s12", 0 0, L_0x12644c0; 1 drivers -v0x105cc70_0 .net *"_s14", 0 0, L_0x12646b0; 1 drivers -v0x105cd50_0 .net *"_s16", 0 0, L_0x1264860; 1 drivers -v0x105ce80_0 .net *"_s3", 0 0, L_0x1263ec0; 1 drivers -v0x105cf60_0 .net *"_s5", 0 0, L_0x1264020; 1 drivers -v0x105d040_0 .net *"_s6", 0 0, L_0x1264250; 1 drivers -v0x105d120_0 .net "in", 3 0, L_0x1264a90; 1 drivers -v0x105d290_0 .net "ors", 1 0, L_0x1264160; 1 drivers -v0x105d370_0 .net "out", 0 0, L_0x1264640; 1 drivers -L_0x1263ec0 .part L_0x1264a90, 0, 1; -L_0x1264020 .part L_0x1264a90, 1, 1; -L_0x1264160 .concat8 [ 1 1 0 0], L_0x1263e50, L_0x1264250; -L_0x1264360 .part L_0x1264a90, 2, 1; -L_0x12644c0 .part L_0x1264a90, 3, 1; -L_0x12646b0 .part L_0x1264160, 0, 1; -L_0x1264860 .part L_0x1264160, 1, 1; -S_0x105dc80 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1056db0; +L_0x2d480a0/d .functor OR 1, L_0x2d48110, L_0x2d48270, C4<0>, C4<0>; +L_0x2d480a0 .delay 1 (30000,30000,30000) L_0x2d480a0/d; +L_0x2d484a0/d .functor OR 1, L_0x2d485b0, L_0x2d48710, C4<0>, C4<0>; +L_0x2d484a0 .delay 1 (30000,30000,30000) L_0x2d484a0/d; +L_0x2d48890/d .functor OR 1, L_0x2d48900, L_0x2d48ab0, C4<0>, C4<0>; +L_0x2d48890 .delay 1 (30000,30000,30000) L_0x2d48890/d; +v0x2b26d00_0 .net *"_s0", 0 0, L_0x2d480a0; 1 drivers +v0x2b26e00_0 .net *"_s10", 0 0, L_0x2d485b0; 1 drivers +v0x2b26ee0_0 .net *"_s12", 0 0, L_0x2d48710; 1 drivers +v0x2b26fa0_0 .net *"_s14", 0 0, L_0x2d48900; 1 drivers +v0x2b27080_0 .net *"_s16", 0 0, L_0x2d48ab0; 1 drivers +v0x2b271b0_0 .net *"_s3", 0 0, L_0x2d48110; 1 drivers +v0x2b27290_0 .net *"_s5", 0 0, L_0x2d48270; 1 drivers +v0x2b27370_0 .net *"_s6", 0 0, L_0x2d484a0; 1 drivers +v0x2b27450_0 .net "in", 3 0, L_0x2d48ce0; 1 drivers +v0x2b275c0_0 .net "ors", 1 0, L_0x2d483b0; 1 drivers +v0x2b276a0_0 .net "out", 0 0, L_0x2d48890; 1 drivers +L_0x2d48110 .part L_0x2d48ce0, 0, 1; +L_0x2d48270 .part L_0x2d48ce0, 1, 1; +L_0x2d483b0 .concat8 [ 1 1 0 0], L_0x2d480a0, L_0x2d484a0; +L_0x2d485b0 .part L_0x2d48ce0, 2, 1; +L_0x2d48710 .part L_0x2d48ce0, 3, 1; +L_0x2d48900 .part L_0x2d483b0, 0, 1; +L_0x2d48ab0 .part L_0x2d483b0, 1, 1; +S_0x2b27fb0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b210e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10630b0_0 .net "ands", 7 0, L_0x125f0f0; 1 drivers -v0x10631c0_0 .net "in", 7 0, L_0x125d550; alias, 1 drivers -v0x1063280_0 .net "out", 0 0, L_0x12610f0; alias, 1 drivers -v0x1063350_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x105ded0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x105dc80; +v0x2b2d3e0_0 .net "ands", 7 0, L_0x2d43340; 1 drivers +v0x2b2d4f0_0 .net "in", 7 0, L_0x2d412c0; alias, 1 drivers +v0x2b2d5b0_0 .net "out", 0 0, L_0x2d45340; alias, 1 drivers +v0x2b2d680_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b28200 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b27fb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1060610_0 .net "A", 7 0, L_0x125d550; alias, 1 drivers -v0x1060710_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10607d0_0 .net *"_s0", 0 0, L_0x125d8e0; 1 drivers -v0x1060890_0 .net *"_s12", 0 0, L_0x125e2a0; 1 drivers -v0x1060970_0 .net *"_s16", 0 0, L_0x125e600; 1 drivers -v0x1060aa0_0 .net *"_s20", 0 0, L_0x125ea30; 1 drivers -v0x1060b80_0 .net *"_s24", 0 0, L_0x125ed60; 1 drivers -v0x1060c60_0 .net *"_s28", 0 0, L_0x125ecf0; 1 drivers -v0x1060d40_0 .net *"_s4", 0 0, L_0x125dc80; 1 drivers -v0x1060eb0_0 .net *"_s8", 0 0, L_0x125df90; 1 drivers -v0x1060f90_0 .net "out", 7 0, L_0x125f0f0; alias, 1 drivers -L_0x125d9f0 .part L_0x125d550, 0, 1; -L_0x125dbe0 .part v0x12010b0_0, 0, 1; -L_0x125dd40 .part L_0x125d550, 1, 1; -L_0x125dea0 .part v0x12010b0_0, 1, 1; -L_0x125e050 .part L_0x125d550, 2, 1; -L_0x125e1b0 .part v0x12010b0_0, 2, 1; -L_0x125e360 .part L_0x125d550, 3, 1; -L_0x125e4c0 .part v0x12010b0_0, 3, 1; -L_0x125e6c0 .part L_0x125d550, 4, 1; -L_0x125e930 .part v0x12010b0_0, 4, 1; -L_0x125eaa0 .part L_0x125d550, 5, 1; -L_0x125ec00 .part v0x12010b0_0, 5, 1; -L_0x125ee20 .part L_0x125d550, 6, 1; -L_0x125ef80 .part v0x12010b0_0, 6, 1; -LS_0x125f0f0_0_0 .concat8 [ 1 1 1 1], L_0x125d8e0, L_0x125dc80, L_0x125df90, L_0x125e2a0; -LS_0x125f0f0_0_4 .concat8 [ 1 1 1 1], L_0x125e600, L_0x125ea30, L_0x125ed60, L_0x125ecf0; -L_0x125f0f0 .concat8 [ 4 4 0 0], LS_0x125f0f0_0_0, LS_0x125f0f0_0_4; -L_0x125f4b0 .part L_0x125d550, 7, 1; -L_0x125f6a0 .part v0x12010b0_0, 7, 1; -S_0x105e110 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105e320 .param/l "i" 0 4 54, +C4<00>; -L_0x125d8e0/d .functor AND 1, L_0x125d9f0, L_0x125dbe0, C4<1>, C4<1>; -L_0x125d8e0 .delay 1 (30000,30000,30000) L_0x125d8e0/d; -v0x105e400_0 .net *"_s0", 0 0, L_0x125d9f0; 1 drivers -v0x105e4e0_0 .net *"_s1", 0 0, L_0x125dbe0; 1 drivers -S_0x105e5c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105e7d0 .param/l "i" 0 4 54, +C4<01>; -L_0x125dc80/d .functor AND 1, L_0x125dd40, L_0x125dea0, C4<1>, C4<1>; -L_0x125dc80 .delay 1 (30000,30000,30000) L_0x125dc80/d; -v0x105e890_0 .net *"_s0", 0 0, L_0x125dd40; 1 drivers -v0x105e970_0 .net *"_s1", 0 0, L_0x125dea0; 1 drivers -S_0x105ea50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105ec90 .param/l "i" 0 4 54, +C4<010>; -L_0x125df90/d .functor AND 1, L_0x125e050, L_0x125e1b0, C4<1>, C4<1>; -L_0x125df90 .delay 1 (30000,30000,30000) L_0x125df90/d; -v0x105ed30_0 .net *"_s0", 0 0, L_0x125e050; 1 drivers -v0x105ee10_0 .net *"_s1", 0 0, L_0x125e1b0; 1 drivers -S_0x105eef0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105f100 .param/l "i" 0 4 54, +C4<011>; -L_0x125e2a0/d .functor AND 1, L_0x125e360, L_0x125e4c0, C4<1>, C4<1>; -L_0x125e2a0 .delay 1 (30000,30000,30000) L_0x125e2a0/d; -v0x105f1c0_0 .net *"_s0", 0 0, L_0x125e360; 1 drivers -v0x105f2a0_0 .net *"_s1", 0 0, L_0x125e4c0; 1 drivers -S_0x105f380 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105f5e0 .param/l "i" 0 4 54, +C4<0100>; -L_0x125e600/d .functor AND 1, L_0x125e6c0, L_0x125e930, C4<1>, C4<1>; -L_0x125e600 .delay 1 (30000,30000,30000) L_0x125e600/d; -v0x105f6a0_0 .net *"_s0", 0 0, L_0x125e6c0; 1 drivers -v0x105f780_0 .net *"_s1", 0 0, L_0x125e930; 1 drivers -S_0x105f860 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105fa70 .param/l "i" 0 4 54, +C4<0101>; -L_0x125ea30/d .functor AND 1, L_0x125eaa0, L_0x125ec00, C4<1>, C4<1>; -L_0x125ea30 .delay 1 (30000,30000,30000) L_0x125ea30/d; -v0x105fb30_0 .net *"_s0", 0 0, L_0x125eaa0; 1 drivers -v0x105fc10_0 .net *"_s1", 0 0, L_0x125ec00; 1 drivers -S_0x105fcf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x105ff00 .param/l "i" 0 4 54, +C4<0110>; -L_0x125ed60/d .functor AND 1, L_0x125ee20, L_0x125ef80, C4<1>, C4<1>; -L_0x125ed60 .delay 1 (30000,30000,30000) L_0x125ed60/d; -v0x105ffc0_0 .net *"_s0", 0 0, L_0x125ee20; 1 drivers -v0x10600a0_0 .net *"_s1", 0 0, L_0x125ef80; 1 drivers -S_0x1060180 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x105ded0; - .timescale -9 -12; -P_0x1060390 .param/l "i" 0 4 54, +C4<0111>; -L_0x125ecf0/d .functor AND 1, L_0x125f4b0, L_0x125f6a0, C4<1>, C4<1>; -L_0x125ecf0 .delay 1 (30000,30000,30000) L_0x125ecf0/d; -v0x1060450_0 .net *"_s0", 0 0, L_0x125f4b0; 1 drivers -v0x1060530_0 .net *"_s1", 0 0, L_0x125f6a0; 1 drivers -S_0x10610f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x105dc80; +v0x2b2a940_0 .net "A", 7 0, L_0x2d412c0; alias, 1 drivers +v0x2b2aa40_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b2ab00_0 .net *"_s0", 0 0, L_0x2d41b90; 1 drivers +v0x2b2abc0_0 .net *"_s12", 0 0, L_0x2d42550; 1 drivers +v0x2b2aca0_0 .net *"_s16", 0 0, L_0x2d428b0; 1 drivers +v0x2b2add0_0 .net *"_s20", 0 0, L_0x2d42c80; 1 drivers +v0x2b2aeb0_0 .net *"_s24", 0 0, L_0x2d42fb0; 1 drivers +v0x2b2af90_0 .net *"_s28", 0 0, L_0x2d42f40; 1 drivers +v0x2b2b070_0 .net *"_s4", 0 0, L_0x2d41f30; 1 drivers +v0x2b2b1e0_0 .net *"_s8", 0 0, L_0x2d42240; 1 drivers +v0x2b2b2c0_0 .net "out", 7 0, L_0x2d43340; alias, 1 drivers +L_0x2d41ca0 .part L_0x2d412c0, 0, 1; +L_0x2d41e90 .part v0x2cdd2e0_0, 0, 1; +L_0x2d41ff0 .part L_0x2d412c0, 1, 1; +L_0x2d42150 .part v0x2cdd2e0_0, 1, 1; +L_0x2d42300 .part L_0x2d412c0, 2, 1; +L_0x2d42460 .part v0x2cdd2e0_0, 2, 1; +L_0x2d42610 .part L_0x2d412c0, 3, 1; +L_0x2d42770 .part v0x2cdd2e0_0, 3, 1; +L_0x2d42970 .part L_0x2d412c0, 4, 1; +L_0x2d42be0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d42cf0 .part L_0x2d412c0, 5, 1; +L_0x2d42e50 .part v0x2cdd2e0_0, 5, 1; +L_0x2d43070 .part L_0x2d412c0, 6, 1; +L_0x2d431d0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d43340_0_0 .concat8 [ 1 1 1 1], L_0x2d41b90, L_0x2d41f30, L_0x2d42240, L_0x2d42550; +LS_0x2d43340_0_4 .concat8 [ 1 1 1 1], L_0x2d428b0, L_0x2d42c80, L_0x2d42fb0, L_0x2d42f40; +L_0x2d43340 .concat8 [ 4 4 0 0], LS_0x2d43340_0_0, LS_0x2d43340_0_4; +L_0x2d43700 .part L_0x2d412c0, 7, 1; +L_0x2d438f0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b28440 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b28650 .param/l "i" 0 4 54, +C4<00>; +L_0x2d41b90/d .functor AND 1, L_0x2d41ca0, L_0x2d41e90, C4<1>, C4<1>; +L_0x2d41b90 .delay 1 (30000,30000,30000) L_0x2d41b90/d; +v0x2b28730_0 .net *"_s0", 0 0, L_0x2d41ca0; 1 drivers +v0x2b28810_0 .net *"_s1", 0 0, L_0x2d41e90; 1 drivers +S_0x2b288f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b28b00 .param/l "i" 0 4 54, +C4<01>; +L_0x2d41f30/d .functor AND 1, L_0x2d41ff0, L_0x2d42150, C4<1>, C4<1>; +L_0x2d41f30 .delay 1 (30000,30000,30000) L_0x2d41f30/d; +v0x2b28bc0_0 .net *"_s0", 0 0, L_0x2d41ff0; 1 drivers +v0x2b28ca0_0 .net *"_s1", 0 0, L_0x2d42150; 1 drivers +S_0x2b28d80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b28fc0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d42240/d .functor AND 1, L_0x2d42300, L_0x2d42460, C4<1>, C4<1>; +L_0x2d42240 .delay 1 (30000,30000,30000) L_0x2d42240/d; +v0x2b29060_0 .net *"_s0", 0 0, L_0x2d42300; 1 drivers +v0x2b29140_0 .net *"_s1", 0 0, L_0x2d42460; 1 drivers +S_0x2b29220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b29430 .param/l "i" 0 4 54, +C4<011>; +L_0x2d42550/d .functor AND 1, L_0x2d42610, L_0x2d42770, C4<1>, C4<1>; +L_0x2d42550 .delay 1 (30000,30000,30000) L_0x2d42550/d; +v0x2b294f0_0 .net *"_s0", 0 0, L_0x2d42610; 1 drivers +v0x2b295d0_0 .net *"_s1", 0 0, L_0x2d42770; 1 drivers +S_0x2b296b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b29910 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d428b0/d .functor AND 1, L_0x2d42970, L_0x2d42be0, C4<1>, C4<1>; +L_0x2d428b0 .delay 1 (30000,30000,30000) L_0x2d428b0/d; +v0x2b299d0_0 .net *"_s0", 0 0, L_0x2d42970; 1 drivers +v0x2b29ab0_0 .net *"_s1", 0 0, L_0x2d42be0; 1 drivers +S_0x2b29b90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b29da0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d42c80/d .functor AND 1, L_0x2d42cf0, L_0x2d42e50, C4<1>, C4<1>; +L_0x2d42c80 .delay 1 (30000,30000,30000) L_0x2d42c80/d; +v0x2b29e60_0 .net *"_s0", 0 0, L_0x2d42cf0; 1 drivers +v0x2b29f40_0 .net *"_s1", 0 0, L_0x2d42e50; 1 drivers +S_0x2b2a020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b2a230 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d42fb0/d .functor AND 1, L_0x2d43070, L_0x2d431d0, C4<1>, C4<1>; +L_0x2d42fb0 .delay 1 (30000,30000,30000) L_0x2d42fb0/d; +v0x2b2a2f0_0 .net *"_s0", 0 0, L_0x2d43070; 1 drivers +v0x2b2a3d0_0 .net *"_s1", 0 0, L_0x2d431d0; 1 drivers +S_0x2b2a4b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b28200; + .timescale -9 -12; +P_0x2b2a6c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d42f40/d .functor AND 1, L_0x2d43700, L_0x2d438f0, C4<1>, C4<1>; +L_0x2d42f40 .delay 1 (30000,30000,30000) L_0x2d42f40/d; +v0x2b2a780_0 .net *"_s0", 0 0, L_0x2d43700; 1 drivers +v0x2b2a860_0 .net *"_s1", 0 0, L_0x2d438f0; 1 drivers +S_0x2b2b420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b27fb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12610f0/d .functor OR 1, L_0x12611b0, L_0x1261360, C4<0>, C4<0>; -L_0x12610f0 .delay 1 (30000,30000,30000) L_0x12610f0/d; -v0x1062c40_0 .net *"_s10", 0 0, L_0x12611b0; 1 drivers -v0x1062d20_0 .net *"_s12", 0 0, L_0x1261360; 1 drivers -v0x1062e00_0 .net "in", 7 0, L_0x125f0f0; alias, 1 drivers -v0x1062ed0_0 .net "ors", 1 0, L_0x1260f10; 1 drivers -v0x1062f90_0 .net "out", 0 0, L_0x12610f0; alias, 1 drivers -L_0x12602e0 .part L_0x125f0f0, 0, 4; -L_0x1260f10 .concat8 [ 1 1 0 0], L_0x125ffd0, L_0x1260c00; -L_0x1261050 .part L_0x125f0f0, 4, 4; -L_0x12611b0 .part L_0x1260f10, 0, 1; -L_0x1261360 .part L_0x1260f10, 1, 1; -S_0x10612b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10610f0; +L_0x2d45340/d .functor OR 1, L_0x2d45400, L_0x2d455b0, C4<0>, C4<0>; +L_0x2d45340 .delay 1 (30000,30000,30000) L_0x2d45340/d; +v0x2b2cf70_0 .net *"_s10", 0 0, L_0x2d45400; 1 drivers +v0x2b2d050_0 .net *"_s12", 0 0, L_0x2d455b0; 1 drivers +v0x2b2d130_0 .net "in", 7 0, L_0x2d43340; alias, 1 drivers +v0x2b2d200_0 .net "ors", 1 0, L_0x2d45160; 1 drivers +v0x2b2d2c0_0 .net "out", 0 0, L_0x2d45340; alias, 1 drivers +L_0x2d44530 .part L_0x2d43340, 0, 4; +L_0x2d45160 .concat8 [ 1 1 0 0], L_0x2d44220, L_0x2d44e50; +L_0x2d452a0 .part L_0x2d43340, 4, 4; +L_0x2d45400 .part L_0x2d45160, 0, 1; +L_0x2d455b0 .part L_0x2d45160, 1, 1; +S_0x2b2b5e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b2b420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x125f790/d .functor OR 1, L_0x125f850, L_0x125f9b0, C4<0>, C4<0>; -L_0x125f790 .delay 1 (30000,30000,30000) L_0x125f790/d; -L_0x125fbe0/d .functor OR 1, L_0x125fcf0, L_0x125fe50, C4<0>, C4<0>; -L_0x125fbe0 .delay 1 (30000,30000,30000) L_0x125fbe0/d; -L_0x125ffd0/d .functor OR 1, L_0x1260040, L_0x12601f0, C4<0>, C4<0>; -L_0x125ffd0 .delay 1 (30000,30000,30000) L_0x125ffd0/d; -v0x1061500_0 .net *"_s0", 0 0, L_0x125f790; 1 drivers -v0x1061600_0 .net *"_s10", 0 0, L_0x125fcf0; 1 drivers -v0x10616e0_0 .net *"_s12", 0 0, L_0x125fe50; 1 drivers -v0x10617a0_0 .net *"_s14", 0 0, L_0x1260040; 1 drivers -v0x1061880_0 .net *"_s16", 0 0, L_0x12601f0; 1 drivers -v0x10619b0_0 .net *"_s3", 0 0, L_0x125f850; 1 drivers -v0x1061a90_0 .net *"_s5", 0 0, L_0x125f9b0; 1 drivers -v0x1061b70_0 .net *"_s6", 0 0, L_0x125fbe0; 1 drivers -v0x1061c50_0 .net "in", 3 0, L_0x12602e0; 1 drivers -v0x1061dc0_0 .net "ors", 1 0, L_0x125faf0; 1 drivers -v0x1061ea0_0 .net "out", 0 0, L_0x125ffd0; 1 drivers -L_0x125f850 .part L_0x12602e0, 0, 1; -L_0x125f9b0 .part L_0x12602e0, 1, 1; -L_0x125faf0 .concat8 [ 1 1 0 0], L_0x125f790, L_0x125fbe0; -L_0x125fcf0 .part L_0x12602e0, 2, 1; -L_0x125fe50 .part L_0x12602e0, 3, 1; -L_0x1260040 .part L_0x125faf0, 0, 1; -L_0x12601f0 .part L_0x125faf0, 1, 1; -S_0x1061fc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10610f0; +L_0x2d439e0/d .functor OR 1, L_0x2d43aa0, L_0x2d43c00, C4<0>, C4<0>; +L_0x2d439e0 .delay 1 (30000,30000,30000) L_0x2d439e0/d; +L_0x2d43e30/d .functor OR 1, L_0x2d43f40, L_0x2d440a0, C4<0>, C4<0>; +L_0x2d43e30 .delay 1 (30000,30000,30000) L_0x2d43e30/d; +L_0x2d44220/d .functor OR 1, L_0x2d44290, L_0x2d44440, C4<0>, C4<0>; +L_0x2d44220 .delay 1 (30000,30000,30000) L_0x2d44220/d; +v0x2b2b830_0 .net *"_s0", 0 0, L_0x2d439e0; 1 drivers +v0x2b2b930_0 .net *"_s10", 0 0, L_0x2d43f40; 1 drivers +v0x2b2ba10_0 .net *"_s12", 0 0, L_0x2d440a0; 1 drivers +v0x2b2bad0_0 .net *"_s14", 0 0, L_0x2d44290; 1 drivers +v0x2b2bbb0_0 .net *"_s16", 0 0, L_0x2d44440; 1 drivers +v0x2b2bce0_0 .net *"_s3", 0 0, L_0x2d43aa0; 1 drivers +v0x2b2bdc0_0 .net *"_s5", 0 0, L_0x2d43c00; 1 drivers +v0x2b2bea0_0 .net *"_s6", 0 0, L_0x2d43e30; 1 drivers +v0x2b2bf80_0 .net "in", 3 0, L_0x2d44530; 1 drivers +v0x2b2c0f0_0 .net "ors", 1 0, L_0x2d43d40; 1 drivers +v0x2b2c1d0_0 .net "out", 0 0, L_0x2d44220; 1 drivers +L_0x2d43aa0 .part L_0x2d44530, 0, 1; +L_0x2d43c00 .part L_0x2d44530, 1, 1; +L_0x2d43d40 .concat8 [ 1 1 0 0], L_0x2d439e0, L_0x2d43e30; +L_0x2d43f40 .part L_0x2d44530, 2, 1; +L_0x2d440a0 .part L_0x2d44530, 3, 1; +L_0x2d44290 .part L_0x2d43d40, 0, 1; +L_0x2d44440 .part L_0x2d43d40, 1, 1; +S_0x2b2c2f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b2b420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1260410/d .functor OR 1, L_0x1260480, L_0x12605e0, C4<0>, C4<0>; -L_0x1260410 .delay 1 (30000,30000,30000) L_0x1260410/d; -L_0x1260810/d .functor OR 1, L_0x1260920, L_0x1260a80, C4<0>, C4<0>; -L_0x1260810 .delay 1 (30000,30000,30000) L_0x1260810/d; -L_0x1260c00/d .functor OR 1, L_0x1260c70, L_0x1260e20, C4<0>, C4<0>; -L_0x1260c00 .delay 1 (30000,30000,30000) L_0x1260c00/d; -v0x1062180_0 .net *"_s0", 0 0, L_0x1260410; 1 drivers -v0x1062280_0 .net *"_s10", 0 0, L_0x1260920; 1 drivers -v0x1062360_0 .net *"_s12", 0 0, L_0x1260a80; 1 drivers -v0x1062420_0 .net *"_s14", 0 0, L_0x1260c70; 1 drivers -v0x1062500_0 .net *"_s16", 0 0, L_0x1260e20; 1 drivers -v0x1062630_0 .net *"_s3", 0 0, L_0x1260480; 1 drivers -v0x1062710_0 .net *"_s5", 0 0, L_0x12605e0; 1 drivers -v0x10627f0_0 .net *"_s6", 0 0, L_0x1260810; 1 drivers -v0x10628d0_0 .net "in", 3 0, L_0x1261050; 1 drivers -v0x1062a40_0 .net "ors", 1 0, L_0x1260720; 1 drivers -v0x1062b20_0 .net "out", 0 0, L_0x1260c00; 1 drivers -L_0x1260480 .part L_0x1261050, 0, 1; -L_0x12605e0 .part L_0x1261050, 1, 1; -L_0x1260720 .concat8 [ 1 1 0 0], L_0x1260410, L_0x1260810; -L_0x1260920 .part L_0x1261050, 2, 1; -L_0x1260a80 .part L_0x1261050, 3, 1; -L_0x1260c70 .part L_0x1260720, 0, 1; -L_0x1260e20 .part L_0x1260720, 1, 1; -S_0x1063430 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1056db0; +L_0x2d44660/d .functor OR 1, L_0x2d446d0, L_0x2d44830, C4<0>, C4<0>; +L_0x2d44660 .delay 1 (30000,30000,30000) L_0x2d44660/d; +L_0x2d44a60/d .functor OR 1, L_0x2d44b70, L_0x2d44cd0, C4<0>, C4<0>; +L_0x2d44a60 .delay 1 (30000,30000,30000) L_0x2d44a60/d; +L_0x2d44e50/d .functor OR 1, L_0x2d44ec0, L_0x2d45070, C4<0>, C4<0>; +L_0x2d44e50 .delay 1 (30000,30000,30000) L_0x2d44e50/d; +v0x2b2c4b0_0 .net *"_s0", 0 0, L_0x2d44660; 1 drivers +v0x2b2c5b0_0 .net *"_s10", 0 0, L_0x2d44b70; 1 drivers +v0x2b2c690_0 .net *"_s12", 0 0, L_0x2d44cd0; 1 drivers +v0x2b2c750_0 .net *"_s14", 0 0, L_0x2d44ec0; 1 drivers +v0x2b2c830_0 .net *"_s16", 0 0, L_0x2d45070; 1 drivers +v0x2b2c960_0 .net *"_s3", 0 0, L_0x2d446d0; 1 drivers +v0x2b2ca40_0 .net *"_s5", 0 0, L_0x2d44830; 1 drivers +v0x2b2cb20_0 .net *"_s6", 0 0, L_0x2d44a60; 1 drivers +v0x2b2cc00_0 .net "in", 3 0, L_0x2d452a0; 1 drivers +v0x2b2cd70_0 .net "ors", 1 0, L_0x2d44970; 1 drivers +v0x2b2ce50_0 .net "out", 0 0, L_0x2d44e50; 1 drivers +L_0x2d446d0 .part L_0x2d452a0, 0, 1; +L_0x2d44830 .part L_0x2d452a0, 1, 1; +L_0x2d44970 .concat8 [ 1 1 0 0], L_0x2d44660, L_0x2d44a60; +L_0x2d44b70 .part L_0x2d452a0, 2, 1; +L_0x2d44cd0 .part L_0x2d452a0, 3, 1; +L_0x2d44ec0 .part L_0x2d44970, 0, 1; +L_0x2d45070 .part L_0x2d44970, 1, 1; +S_0x2b2d760 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b210e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -5462,80 +5774,80 @@ S_0x1063430 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1056db0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x125c8c0/d .functor XNOR 1, L_0x1264f90, L_0x125b480, C4<0>, C4<0>; -L_0x125c8c0 .delay 1 (20000,20000,20000) L_0x125c8c0/d; -L_0x125cb30/d .functor AND 1, L_0x1264f90, L_0x1255360, C4<1>, C4<1>; -L_0x125cb30 .delay 1 (30000,30000,30000) L_0x125cb30/d; -L_0x125cba0/d .functor AND 1, L_0x125c8c0, L_0x12651e0, C4<1>, C4<1>; -L_0x125cba0 .delay 1 (30000,30000,30000) L_0x125cba0/d; -L_0x125cd00/d .functor OR 1, L_0x125cba0, L_0x125cb30, C4<0>, C4<0>; -L_0x125cd00 .delay 1 (30000,30000,30000) L_0x125cd00/d; -v0x10636e0_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers -v0x10637d0_0 .net "a_", 0 0, L_0x125b650; alias, 1 drivers -v0x1063890_0 .net "b", 0 0, L_0x125b480; alias, 1 drivers -v0x1063980_0 .net "b_", 0 0, L_0x1255360; alias, 1 drivers -v0x1063a20_0 .net "carryin", 0 0, L_0x12651e0; alias, 1 drivers -v0x1063b60_0 .net "eq", 0 0, L_0x125c8c0; 1 drivers -v0x1063c20_0 .net "lt", 0 0, L_0x125cb30; 1 drivers -v0x1063ce0_0 .net "out", 0 0, L_0x125cd00; 1 drivers -v0x1063da0_0 .net "w0", 0 0, L_0x125cba0; 1 drivers -S_0x1063ff0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1056db0; +L_0x2d3fce0/d .functor XNOR 1, L_0x2d491e0, L_0x2d3e6f0, C4<0>, C4<0>; +L_0x2d3fce0 .delay 1 (20000,20000,20000) L_0x2d3fce0/d; +L_0x2d3fe60/d .functor AND 1, L_0x2d491e0, L_0x2d3e9d0, C4<1>, C4<1>; +L_0x2d3fe60 .delay 1 (30000,30000,30000) L_0x2d3fe60/d; +L_0x2d3ffc0/d .functor AND 1, L_0x2d3fce0, L_0x2d49430, C4<1>, C4<1>; +L_0x2d3ffc0 .delay 1 (30000,30000,30000) L_0x2d3ffc0/d; +L_0x2d400d0/d .functor OR 1, L_0x2d3ffc0, L_0x2d3fe60, C4<0>, C4<0>; +L_0x2d400d0 .delay 1 (30000,30000,30000) L_0x2d400d0/d; +v0x2b2da10_0 .net "a", 0 0, L_0x2d491e0; alias, 1 drivers +v0x2b2db00_0 .net "a_", 0 0, L_0x2d3e870; alias, 1 drivers +v0x2b2dbc0_0 .net "b", 0 0, L_0x2d3e6f0; alias, 1 drivers +v0x2b2dcb0_0 .net "b_", 0 0, L_0x2d3e9d0; alias, 1 drivers +v0x2b2dd50_0 .net "carryin", 0 0, L_0x2d49430; alias, 1 drivers +v0x2b2de90_0 .net "eq", 0 0, L_0x2d3fce0; 1 drivers +v0x2b2df50_0 .net "lt", 0 0, L_0x2d3fe60; 1 drivers +v0x2b2e010_0 .net "out", 0 0, L_0x2d400d0; 1 drivers +v0x2b2e0d0_0 .net "w0", 0 0, L_0x2d3ffc0; 1 drivers +S_0x2b2e320 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b210e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x125c6a0/d .functor OR 1, L_0x125c1f0, L_0x1065210, C4<0>, C4<0>; -L_0x125c6a0 .delay 1 (30000,30000,30000) L_0x125c6a0/d; -v0x1064da0_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers -v0x1064ef0_0 .net "b", 0 0, L_0x1255360; alias, 1 drivers -v0x1064fb0_0 .net "c1", 0 0, L_0x125c1f0; 1 drivers -v0x1065050_0 .net "c2", 0 0, L_0x1065210; 1 drivers -v0x1065120_0 .net "carryin", 0 0, L_0x12651e0; alias, 1 drivers -v0x10652a0_0 .net "carryout", 0 0, L_0x125c6a0; 1 drivers -v0x1065340_0 .net "s1", 0 0, L_0x125c130; 1 drivers -v0x10653e0_0 .net "sum", 0 0, L_0x125c350; 1 drivers -S_0x1064240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1063ff0; +L_0x2d3f8c0/d .functor OR 1, L_0x2d3f3c0, L_0x2b2f580, C4<0>, C4<0>; +L_0x2d3f8c0 .delay 1 (30000,30000,30000) L_0x2d3f8c0/d; +v0x2b2f110_0 .net "a", 0 0, L_0x2d491e0; alias, 1 drivers +v0x2b2f260_0 .net "b", 0 0, L_0x2d3e9d0; alias, 1 drivers +v0x2b2f320_0 .net "c1", 0 0, L_0x2d3f3c0; 1 drivers +v0x2b2f3c0_0 .net "c2", 0 0, L_0x2b2f580; 1 drivers +v0x2b2f490_0 .net "carryin", 0 0, L_0x2d49430; alias, 1 drivers +v0x2b2f610_0 .net "carryout", 0 0, L_0x2d3f8c0; 1 drivers +v0x2b2f6b0_0 .net "s1", 0 0, L_0x2d3f300; 1 drivers +v0x2b2f750_0 .net "sum", 0 0, L_0x2d3f520; 1 drivers +S_0x2b2e570 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b2e320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x125c130/d .functor XOR 1, L_0x1264f90, L_0x1255360, C4<0>, C4<0>; -L_0x125c130 .delay 1 (30000,30000,30000) L_0x125c130/d; -L_0x125c1f0/d .functor AND 1, L_0x1264f90, L_0x1255360, C4<1>, C4<1>; -L_0x125c1f0 .delay 1 (30000,30000,30000) L_0x125c1f0/d; -v0x1064480_0 .net "a", 0 0, L_0x1264f90; alias, 1 drivers -v0x1064520_0 .net "b", 0 0, L_0x1255360; alias, 1 drivers -v0x10645c0_0 .net "carryout", 0 0, L_0x125c1f0; alias, 1 drivers -v0x1064690_0 .net "sum", 0 0, L_0x125c130; alias, 1 drivers -S_0x10647c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1063ff0; +L_0x2d3f300/d .functor XOR 1, L_0x2d491e0, L_0x2d3e9d0, C4<0>, C4<0>; +L_0x2d3f300 .delay 1 (30000,30000,30000) L_0x2d3f300/d; +L_0x2d3f3c0/d .functor AND 1, L_0x2d491e0, L_0x2d3e9d0, C4<1>, C4<1>; +L_0x2d3f3c0 .delay 1 (30000,30000,30000) L_0x2d3f3c0/d; +v0x2b2e7d0_0 .net "a", 0 0, L_0x2d491e0; alias, 1 drivers +v0x2b2e890_0 .net "b", 0 0, L_0x2d3e9d0; alias, 1 drivers +v0x2b2e950_0 .net "carryout", 0 0, L_0x2d3f3c0; alias, 1 drivers +v0x2b2e9f0_0 .net "sum", 0 0, L_0x2d3f300; alias, 1 drivers +S_0x2b2eb20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b2e320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x125c350/d .functor XOR 1, L_0x125c130, L_0x12651e0, C4<0>, C4<0>; -L_0x125c350 .delay 1 (30000,30000,30000) L_0x125c350/d; -L_0x1065210/d .functor AND 1, L_0x125c130, L_0x12651e0, C4<1>, C4<1>; -L_0x1065210 .delay 1 (30000,30000,30000) L_0x1065210/d; -v0x1064a20_0 .net "a", 0 0, L_0x125c130; alias, 1 drivers -v0x1064ae0_0 .net "b", 0 0, L_0x12651e0; alias, 1 drivers -v0x1064b80_0 .net "carryout", 0 0, L_0x1065210; alias, 1 drivers -v0x1064c50_0 .net "sum", 0 0, L_0x125c350; alias, 1 drivers -S_0x1066840 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1056ae0; - .timescale -9 -12; -L_0x2b0ab3d05a38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05a80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1265030/d .functor OR 1, L_0x2b0ab3d05a38, L_0x2b0ab3d05a80, C4<0>, C4<0>; -L_0x1265030 .delay 1 (30000,30000,30000) L_0x1265030/d; -v0x1066a30_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05a38; 1 drivers -v0x1066b10_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05a80; 1 drivers -S_0x1066bf0 .scope generate, "alu_slices[10]" "alu_slices[10]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1066e00 .param/l "i" 0 3 41, +C4<01010>; -S_0x1066ec0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1066bf0; +L_0x2d3f520/d .functor XOR 1, L_0x2d3f300, L_0x2d49430, C4<0>, C4<0>; +L_0x2d3f520 .delay 1 (30000,30000,30000) L_0x2d3f520/d; +L_0x2b2f580/d .functor AND 1, L_0x2d3f300, L_0x2d49430, C4<1>, C4<1>; +L_0x2b2f580 .delay 1 (30000,30000,30000) L_0x2b2f580/d; +v0x2b2ed80_0 .net "a", 0 0, L_0x2d3f300; alias, 1 drivers +v0x2b2ee50_0 .net "b", 0 0, L_0x2d49430; alias, 1 drivers +v0x2b2eef0_0 .net "carryout", 0 0, L_0x2b2f580; alias, 1 drivers +v0x2b2efc0_0 .net "sum", 0 0, L_0x2d3f520; alias, 1 drivers +S_0x2b317e0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b20e10; + .timescale -9 -12; +L_0x2ac6110b8658 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b86a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d41600/d .functor OR 1, L_0x2ac6110b8658, L_0x2ac6110b86a0, C4<0>, C4<0>; +L_0x2d41600 .delay 1 (30000,30000,30000) L_0x2d41600/d; +v0x2b319d0_0 .net/2u *"_s0", 0 0, L_0x2ac6110b8658; 1 drivers +v0x2b31ab0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b86a0; 1 drivers +S_0x2b31b90 .scope generate, "alu_slices[10]" "alu_slices[10]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b31da0 .param/l "i" 0 3 39, +C4<01010>; +S_0x2b31e60 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b31b90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -5544,445 +5856,476 @@ S_0x1066ec0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1066bf0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12653d0/d .functor NOT 1, L_0x126ebe0, C4<0>, C4<0>, C4<0>; -L_0x12653d0 .delay 1 (10000,10000,10000) L_0x12653d0/d; -L_0x12654e0/d .functor NOT 1, L_0x126ed40, C4<0>, C4<0>, C4<0>; -L_0x12654e0 .delay 1 (10000,10000,10000) L_0x12654e0/d; -L_0x1266530/d .functor XOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; -L_0x1266530 .delay 1 (30000,30000,30000) L_0x1266530/d; -L_0x2b0ab3d05ac8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05b10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1266be0/d .functor OR 1, L_0x2b0ab3d05ac8, L_0x2b0ab3d05b10, C4<0>, C4<0>; -L_0x1266be0 .delay 1 (30000,30000,30000) L_0x1266be0/d; -L_0x1266de0/d .functor AND 1, L_0x126ebe0, L_0x126ed40, C4<1>, C4<1>; -L_0x1266de0 .delay 1 (30000,30000,30000) L_0x1266de0/d; -L_0x1266ea0/d .functor NAND 1, L_0x126ebe0, L_0x126ed40, C4<1>, C4<1>; -L_0x1266ea0 .delay 1 (20000,20000,20000) L_0x1266ea0/d; -L_0x1267000/d .functor XOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; -L_0x1267000 .delay 1 (20000,20000,20000) L_0x1267000/d; -L_0x12674b0/d .functor OR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; -L_0x12674b0 .delay 1 (30000,30000,30000) L_0x12674b0/d; -L_0x126eae0/d .functor NOT 1, L_0x126ad40, C4<0>, C4<0>, C4<0>; -L_0x126eae0 .delay 1 (10000,10000,10000) L_0x126eae0/d; -v0x10755f0_0 .net "A", 0 0, L_0x126ebe0; 1 drivers -v0x10756b0_0 .net "A_", 0 0, L_0x12653d0; 1 drivers -v0x1075770_0 .net "B", 0 0, L_0x126ed40; 1 drivers -v0x1075840_0 .net "B_", 0 0, L_0x12654e0; 1 drivers -v0x10758e0_0 .net *"_s12", 0 0, L_0x1266be0; 1 drivers -v0x10759d0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05ac8; 1 drivers -v0x1075a90_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05b10; 1 drivers -v0x1075b70_0 .net *"_s18", 0 0, L_0x1266de0; 1 drivers -v0x1075c50_0 .net *"_s20", 0 0, L_0x1266ea0; 1 drivers -v0x1075dc0_0 .net *"_s22", 0 0, L_0x1267000; 1 drivers -v0x1075ea0_0 .net *"_s24", 0 0, L_0x12674b0; 1 drivers -o0x2b0ab3cbc7e8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1075f80_0 name=_s30 -o0x2b0ab3cbc818 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1076060_0 name=_s32 -v0x1076140_0 .net *"_s8", 0 0, L_0x1266530; 1 drivers -v0x1076220_0 .net "carryin", 0 0, L_0x1265280; 1 drivers -v0x10762c0_0 .net "carryout", 0 0, L_0x126e780; 1 drivers -v0x1076360_0 .net "carryouts", 7 0, L_0x1353f00; 1 drivers -v0x1076510_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10765b0_0 .net "result", 0 0, L_0x126ad40; 1 drivers -v0x10766a0_0 .net "results", 7 0, L_0x1267280; 1 drivers -v0x10767b0_0 .net "zero", 0 0, L_0x126eae0; 1 drivers -LS_0x1267280_0_0 .concat8 [ 1 1 1 1], L_0x1265a00, L_0x1266030, L_0x1266530, L_0x1266be0; -LS_0x1267280_0_4 .concat8 [ 1 1 1 1], L_0x1266de0, L_0x1266ea0, L_0x1267000, L_0x12674b0; -L_0x1267280 .concat8 [ 4 4 0 0], LS_0x1267280_0_0, LS_0x1267280_0_4; -LS_0x1353f00_0_0 .concat [ 1 1 1 1], L_0x1265cb0, L_0x12663d0, o0x2b0ab3cbc7e8, L_0x1266a30; -LS_0x1353f00_0_4 .concat [ 4 0 0 0], o0x2b0ab3cbc818; -L_0x1353f00 .concat [ 4 4 0 0], LS_0x1353f00_0_0, LS_0x1353f00_0_4; -S_0x1067140 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1066ec0; +L_0x2d495d0/d .functor NOT 1, L_0x2d53a40, C4<0>, C4<0>, C4<0>; +L_0x2d495d0 .delay 1 (10000,10000,10000) L_0x2d495d0/d; +L_0x2d496e0/d .functor NOT 1, L_0x2d53ba0, C4<0>, C4<0>, C4<0>; +L_0x2d496e0 .delay 1 (10000,10000,10000) L_0x2d496e0/d; +L_0x2d4a690/d .functor XOR 1, L_0x2d53a40, L_0x2d53ba0, C4<0>, C4<0>; +L_0x2d4a690 .delay 1 (30000,30000,30000) L_0x2d4a690/d; +L_0x2ac6110b86e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8730 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d4a750/d .functor OR 1, L_0x2ac6110b86e8, L_0x2ac6110b8730, C4<0>, C4<0>; +L_0x2d4a750 .delay 1 (30000,30000,30000) L_0x2d4a750/d; +L_0x2ac6110b8778 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b87c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d4aef0/d .functor OR 1, L_0x2ac6110b8778, L_0x2ac6110b87c0, C4<0>, C4<0>; +L_0x2d4aef0 .delay 1 (30000,30000,30000) L_0x2d4aef0/d; +L_0x2d4b0f0/d .functor AND 1, L_0x2d53a40, L_0x2d53ba0, C4<1>, C4<1>; +L_0x2d4b0f0 .delay 1 (30000,30000,30000) L_0x2d4b0f0/d; +L_0x2ac6110b8808 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8850 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d4b1b0/d .functor OR 1, L_0x2ac6110b8808, L_0x2ac6110b8850, C4<0>, C4<0>; +L_0x2d4b1b0 .delay 1 (30000,30000,30000) L_0x2d4b1b0/d; +L_0x2d4b3b0/d .functor NAND 1, L_0x2d53a40, L_0x2d53ba0, C4<1>, C4<1>; +L_0x2d4b3b0 .delay 1 (20000,20000,20000) L_0x2d4b3b0/d; +L_0x2ac6110b8898 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b88e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d4b4c0/d .functor OR 1, L_0x2ac6110b8898, L_0x2ac6110b88e0, C4<0>, C4<0>; +L_0x2d4b4c0 .delay 1 (30000,30000,30000) L_0x2d4b4c0/d; +L_0x2d4b670/d .functor NOR 1, L_0x2d53a40, L_0x2d53ba0, C4<0>, C4<0>; +L_0x2d4b670 .delay 1 (20000,20000,20000) L_0x2d4b670/d; +L_0x2ac6110b8928 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8970 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d4b940/d .functor OR 1, L_0x2ac6110b8928, L_0x2ac6110b8970, C4<0>, C4<0>; +L_0x2d4b940 .delay 1 (30000,30000,30000) L_0x2d4b940/d; +L_0x2d4bd40/d .functor OR 1, L_0x2d53a40, L_0x2d53ba0, C4<0>, C4<0>; +L_0x2d4bd40 .delay 1 (30000,30000,30000) L_0x2d4bd40/d; +L_0x2ac6110b89b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8a00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d4c1e0/d .functor OR 1, L_0x2ac6110b89b8, L_0x2ac6110b8a00, C4<0>, C4<0>; +L_0x2d4c1e0 .delay 1 (30000,30000,30000) L_0x2d4c1e0/d; +L_0x2d53940/d .functor NOT 1, L_0x2d4fba0, C4<0>, C4<0>, C4<0>; +L_0x2d53940 .delay 1 (10000,10000,10000) L_0x2d53940/d; +v0x2b405b0_0 .net "A", 0 0, L_0x2d53a40; 1 drivers +v0x2b40670_0 .net "A_", 0 0, L_0x2d495d0; 1 drivers +v0x2b40730_0 .net "B", 0 0, L_0x2d53ba0; 1 drivers +v0x2b40800_0 .net "B_", 0 0, L_0x2d496e0; 1 drivers +v0x2b408a0_0 .net *"_s11", 0 0, L_0x2d4a750; 1 drivers +v0x2b40990_0 .net/2s *"_s13", 0 0, L_0x2ac6110b86e8; 1 drivers +v0x2b40a50_0 .net/2s *"_s15", 0 0, L_0x2ac6110b8730; 1 drivers +v0x2b40b30_0 .net *"_s19", 0 0, L_0x2d4aef0; 1 drivers +v0x2b40c10_0 .net/2s *"_s21", 0 0, L_0x2ac6110b8778; 1 drivers +v0x2b40d80_0 .net/2s *"_s23", 0 0, L_0x2ac6110b87c0; 1 drivers +v0x2b40e60_0 .net *"_s25", 0 0, L_0x2d4b0f0; 1 drivers +v0x2b40f40_0 .net *"_s28", 0 0, L_0x2d4b1b0; 1 drivers +v0x2b41020_0 .net/2s *"_s30", 0 0, L_0x2ac6110b8808; 1 drivers +v0x2b41100_0 .net/2s *"_s32", 0 0, L_0x2ac6110b8850; 1 drivers +v0x2b411e0_0 .net *"_s34", 0 0, L_0x2d4b3b0; 1 drivers +v0x2b412c0_0 .net *"_s37", 0 0, L_0x2d4b4c0; 1 drivers +v0x2b413a0_0 .net/2s *"_s39", 0 0, L_0x2ac6110b8898; 1 drivers +v0x2b41550_0 .net/2s *"_s41", 0 0, L_0x2ac6110b88e0; 1 drivers +v0x2b415f0_0 .net *"_s43", 0 0, L_0x2d4b670; 1 drivers +v0x2b416d0_0 .net *"_s46", 0 0, L_0x2d4b940; 1 drivers +v0x2b417b0_0 .net/2s *"_s48", 0 0, L_0x2ac6110b8928; 1 drivers +v0x2b41890_0 .net/2s *"_s50", 0 0, L_0x2ac6110b8970; 1 drivers +v0x2b41970_0 .net *"_s52", 0 0, L_0x2d4bd40; 1 drivers +v0x2b41a50_0 .net *"_s56", 0 0, L_0x2d4c1e0; 1 drivers +v0x2b41b30_0 .net/2s *"_s59", 0 0, L_0x2ac6110b89b8; 1 drivers +v0x2b41c10_0 .net/2s *"_s61", 0 0, L_0x2ac6110b8a00; 1 drivers +v0x2b41cf0_0 .net *"_s8", 0 0, L_0x2d4a690; 1 drivers +v0x2b41dd0_0 .net "carryin", 0 0, L_0x2d494d0; 1 drivers +v0x2b41e70_0 .net "carryout", 0 0, L_0x2d535e0; 1 drivers +v0x2b41f10_0 .net "carryouts", 7 0, L_0x2d4be50; 1 drivers +v0x2b42020_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b420e0_0 .net "result", 0 0, L_0x2d4fba0; 1 drivers +v0x2b421d0_0 .net "results", 7 0, L_0x2d4bb10; 1 drivers +v0x2b414b0_0 .net "zero", 0 0, L_0x2d53940; 1 drivers +LS_0x2d4bb10_0_0 .concat8 [ 1 1 1 1], L_0x2d49c00, L_0x2d4a1e0, L_0x2d4a690, L_0x2d4aef0; +LS_0x2d4bb10_0_4 .concat8 [ 1 1 1 1], L_0x2d4b0f0, L_0x2d4b3b0, L_0x2d4b670, L_0x2d4bd40; +L_0x2d4bb10 .concat8 [ 4 4 0 0], LS_0x2d4bb10_0_0, LS_0x2d4bb10_0_4; +LS_0x2d4be50_0_0 .concat8 [ 1 1 1 1], L_0x2d49eb0, L_0x2d4a530, L_0x2d4a750, L_0x2d4ad40; +LS_0x2d4be50_0_4 .concat8 [ 1 1 1 1], L_0x2d4b1b0, L_0x2d4b4c0, L_0x2d4b940, L_0x2d4c1e0; +L_0x2d4be50 .concat8 [ 4 4 0 0], LS_0x2d4be50_0_0, LS_0x2d4be50_0_4; +S_0x2b320e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b31e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1265cb0/d .functor OR 1, L_0x1265790, L_0x1265b50, C4<0>, C4<0>; -L_0x1265cb0 .delay 1 (30000,30000,30000) L_0x1265cb0/d; -v0x1067f70_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers -v0x1068030_0 .net "b", 0 0, L_0x126ed40; alias, 1 drivers -v0x1068100_0 .net "c1", 0 0, L_0x1265790; 1 drivers -v0x1068200_0 .net "c2", 0 0, L_0x1265b50; 1 drivers -v0x10682d0_0 .net "carryin", 0 0, L_0x1265280; alias, 1 drivers -v0x10683c0_0 .net "carryout", 0 0, L_0x1265cb0; 1 drivers -v0x1068460_0 .net "s1", 0 0, L_0x12656d0; 1 drivers -v0x1068550_0 .net "sum", 0 0, L_0x1265a00; 1 drivers -S_0x10673b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1067140; +L_0x2d49eb0/d .functor OR 1, L_0x2d49990, L_0x2d49d50, C4<0>, C4<0>; +L_0x2d49eb0 .delay 1 (30000,30000,30000) L_0x2d49eb0/d; +v0x2b32f10_0 .net "a", 0 0, L_0x2d53a40; alias, 1 drivers +v0x2b32fd0_0 .net "b", 0 0, L_0x2d53ba0; alias, 1 drivers +v0x2b330a0_0 .net "c1", 0 0, L_0x2d49990; 1 drivers +v0x2b331a0_0 .net "c2", 0 0, L_0x2d49d50; 1 drivers +v0x2b33270_0 .net "carryin", 0 0, L_0x2d494d0; alias, 1 drivers +v0x2b33360_0 .net "carryout", 0 0, L_0x2d49eb0; 1 drivers +v0x2b33400_0 .net "s1", 0 0, L_0x2d498d0; 1 drivers +v0x2b334f0_0 .net "sum", 0 0, L_0x2d49c00; 1 drivers +S_0x2b32350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b320e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12656d0/d .functor XOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; -L_0x12656d0 .delay 1 (30000,30000,30000) L_0x12656d0/d; -L_0x1265790/d .functor AND 1, L_0x126ebe0, L_0x126ed40, C4<1>, C4<1>; -L_0x1265790 .delay 1 (30000,30000,30000) L_0x1265790/d; -v0x1067610_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers -v0x10676f0_0 .net "b", 0 0, L_0x126ed40; alias, 1 drivers -v0x10677b0_0 .net "carryout", 0 0, L_0x1265790; alias, 1 drivers -v0x1067850_0 .net "sum", 0 0, L_0x12656d0; alias, 1 drivers -S_0x1067990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1067140; +L_0x2d498d0/d .functor XOR 1, L_0x2d53a40, L_0x2d53ba0, C4<0>, C4<0>; +L_0x2d498d0 .delay 1 (30000,30000,30000) L_0x2d498d0/d; +L_0x2d49990/d .functor AND 1, L_0x2d53a40, L_0x2d53ba0, C4<1>, C4<1>; +L_0x2d49990 .delay 1 (30000,30000,30000) L_0x2d49990/d; +v0x2b325b0_0 .net "a", 0 0, L_0x2d53a40; alias, 1 drivers +v0x2b32690_0 .net "b", 0 0, L_0x2d53ba0; alias, 1 drivers +v0x2b32750_0 .net "carryout", 0 0, L_0x2d49990; alias, 1 drivers +v0x2b327f0_0 .net "sum", 0 0, L_0x2d498d0; alias, 1 drivers +S_0x2b32930 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b320e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1265a00/d .functor XOR 1, L_0x12656d0, L_0x1265280, C4<0>, C4<0>; -L_0x1265a00 .delay 1 (30000,30000,30000) L_0x1265a00/d; -L_0x1265b50/d .functor AND 1, L_0x12656d0, L_0x1265280, C4<1>, C4<1>; -L_0x1265b50 .delay 1 (30000,30000,30000) L_0x1265b50/d; -v0x1067bf0_0 .net "a", 0 0, L_0x12656d0; alias, 1 drivers -v0x1067c90_0 .net "b", 0 0, L_0x1265280; alias, 1 drivers -v0x1067d30_0 .net "carryout", 0 0, L_0x1265b50; alias, 1 drivers -v0x1067e00_0 .net "sum", 0 0, L_0x1265a00; alias, 1 drivers -S_0x1068620 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1066ec0; +L_0x2d49c00/d .functor XOR 1, L_0x2d498d0, L_0x2d494d0, C4<0>, C4<0>; +L_0x2d49c00 .delay 1 (30000,30000,30000) L_0x2d49c00/d; +L_0x2d49d50/d .functor AND 1, L_0x2d498d0, L_0x2d494d0, C4<1>, C4<1>; +L_0x2d49d50 .delay 1 (30000,30000,30000) L_0x2d49d50/d; +v0x2b32b90_0 .net "a", 0 0, L_0x2d498d0; alias, 1 drivers +v0x2b32c30_0 .net "b", 0 0, L_0x2d494d0; alias, 1 drivers +v0x2b32cd0_0 .net "carryout", 0 0, L_0x2d49d50; alias, 1 drivers +v0x2b32da0_0 .net "sum", 0 0, L_0x2d49c00; alias, 1 drivers +S_0x2b335c0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b31e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x106da10_0 .net "ands", 7 0, L_0x126c780; 1 drivers -v0x106db20_0 .net "in", 7 0, L_0x1353f00; alias, 1 drivers -v0x106dbe0_0 .net "out", 0 0, L_0x126e780; alias, 1 drivers -v0x106dcb0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1068840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1068620; +v0x2b389b0_0 .net "ands", 7 0, L_0x2d515e0; 1 drivers +v0x2b38ac0_0 .net "in", 7 0, L_0x2d4be50; alias, 1 drivers +v0x2b38b80_0 .net "out", 0 0, L_0x2d535e0; alias, 1 drivers +v0x2b38c50_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b337e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b335c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x106af70_0 .net "A", 7 0, L_0x1353f00; alias, 1 drivers -v0x106b070_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x106b130_0 .net *"_s0", 0 0, L_0x126b0a0; 1 drivers -v0x106b1f0_0 .net *"_s12", 0 0, L_0x126ba10; 1 drivers -v0x106b2d0_0 .net *"_s16", 0 0, L_0x126bd70; 1 drivers -v0x106b400_0 .net *"_s20", 0 0, L_0x126c080; 1 drivers -v0x106b4e0_0 .net *"_s24", 0 0, L_0x126c470; 1 drivers -v0x106b5c0_0 .net *"_s28", 0 0, L_0x126c400; 1 drivers -v0x106b6a0_0 .net *"_s4", 0 0, L_0x126b3b0; 1 drivers -v0x106b810_0 .net *"_s8", 0 0, L_0x126b700; 1 drivers -v0x106b8f0_0 .net "out", 7 0, L_0x126c780; alias, 1 drivers -L_0x126b160 .part L_0x1353f00, 0, 1; -L_0x126b2c0 .part v0x12010b0_0, 0, 1; -L_0x126b470 .part L_0x1353f00, 1, 1; -L_0x126b660 .part v0x12010b0_0, 1, 1; -L_0x126b7c0 .part L_0x1353f00, 2, 1; -L_0x126b920 .part v0x12010b0_0, 2, 1; -L_0x126bad0 .part L_0x1353f00, 3, 1; -L_0x126bc30 .part v0x12010b0_0, 3, 1; -L_0x126be30 .part L_0x1353f00, 4, 1; -L_0x126bf90 .part v0x12010b0_0, 4, 1; -L_0x126c0f0 .part L_0x1353f00, 5, 1; -L_0x126c360 .part v0x12010b0_0, 5, 1; -L_0x126c530 .part L_0x1353f00, 6, 1; -L_0x126c690 .part v0x12010b0_0, 6, 1; -LS_0x126c780_0_0 .concat8 [ 1 1 1 1], L_0x126b0a0, L_0x126b3b0, L_0x126b700, L_0x126ba10; -LS_0x126c780_0_4 .concat8 [ 1 1 1 1], L_0x126bd70, L_0x126c080, L_0x126c470, L_0x126c400; -L_0x126c780 .concat8 [ 4 4 0 0], LS_0x126c780_0_0, LS_0x126c780_0_4; -L_0x126cb40 .part L_0x1353f00, 7, 1; -L_0x126cd30 .part v0x12010b0_0, 7, 1; -S_0x1068aa0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x1068cb0 .param/l "i" 0 4 54, +C4<00>; -L_0x126b0a0/d .functor AND 1, L_0x126b160, L_0x126b2c0, C4<1>, C4<1>; -L_0x126b0a0 .delay 1 (30000,30000,30000) L_0x126b0a0/d; -v0x1068d90_0 .net *"_s0", 0 0, L_0x126b160; 1 drivers -v0x1068e70_0 .net *"_s1", 0 0, L_0x126b2c0; 1 drivers -S_0x1068f50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x1069160 .param/l "i" 0 4 54, +C4<01>; -L_0x126b3b0/d .functor AND 1, L_0x126b470, L_0x126b660, C4<1>, C4<1>; -L_0x126b3b0 .delay 1 (30000,30000,30000) L_0x126b3b0/d; -v0x1069220_0 .net *"_s0", 0 0, L_0x126b470; 1 drivers -v0x1069300_0 .net *"_s1", 0 0, L_0x126b660; 1 drivers -S_0x10693e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x10695f0 .param/l "i" 0 4 54, +C4<010>; -L_0x126b700/d .functor AND 1, L_0x126b7c0, L_0x126b920, C4<1>, C4<1>; -L_0x126b700 .delay 1 (30000,30000,30000) L_0x126b700/d; -v0x1069690_0 .net *"_s0", 0 0, L_0x126b7c0; 1 drivers -v0x1069770_0 .net *"_s1", 0 0, L_0x126b920; 1 drivers -S_0x1069850 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x1069a60 .param/l "i" 0 4 54, +C4<011>; -L_0x126ba10/d .functor AND 1, L_0x126bad0, L_0x126bc30, C4<1>, C4<1>; -L_0x126ba10 .delay 1 (30000,30000,30000) L_0x126ba10/d; -v0x1069b20_0 .net *"_s0", 0 0, L_0x126bad0; 1 drivers -v0x1069c00_0 .net *"_s1", 0 0, L_0x126bc30; 1 drivers -S_0x1069ce0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x1069f40 .param/l "i" 0 4 54, +C4<0100>; -L_0x126bd70/d .functor AND 1, L_0x126be30, L_0x126bf90, C4<1>, C4<1>; -L_0x126bd70 .delay 1 (30000,30000,30000) L_0x126bd70/d; -v0x106a000_0 .net *"_s0", 0 0, L_0x126be30; 1 drivers -v0x106a0e0_0 .net *"_s1", 0 0, L_0x126bf90; 1 drivers -S_0x106a1c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x106a3d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x126c080/d .functor AND 1, L_0x126c0f0, L_0x126c360, C4<1>, C4<1>; -L_0x126c080 .delay 1 (30000,30000,30000) L_0x126c080/d; -v0x106a490_0 .net *"_s0", 0 0, L_0x126c0f0; 1 drivers -v0x106a570_0 .net *"_s1", 0 0, L_0x126c360; 1 drivers -S_0x106a650 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x106a860 .param/l "i" 0 4 54, +C4<0110>; -L_0x126c470/d .functor AND 1, L_0x126c530, L_0x126c690, C4<1>, C4<1>; -L_0x126c470 .delay 1 (30000,30000,30000) L_0x126c470/d; -v0x106a920_0 .net *"_s0", 0 0, L_0x126c530; 1 drivers -v0x106aa00_0 .net *"_s1", 0 0, L_0x126c690; 1 drivers -S_0x106aae0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1068840; - .timescale -9 -12; -P_0x106acf0 .param/l "i" 0 4 54, +C4<0111>; -L_0x126c400/d .functor AND 1, L_0x126cb40, L_0x126cd30, C4<1>, C4<1>; -L_0x126c400 .delay 1 (30000,30000,30000) L_0x126c400/d; -v0x106adb0_0 .net *"_s0", 0 0, L_0x126cb40; 1 drivers -v0x106ae90_0 .net *"_s1", 0 0, L_0x126cd30; 1 drivers -S_0x106ba50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1068620; +v0x2b35f10_0 .net "A", 7 0, L_0x2d4be50; alias, 1 drivers +v0x2b36010_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b360d0_0 .net *"_s0", 0 0, L_0x2d4ff00; 1 drivers +v0x2b36190_0 .net *"_s12", 0 0, L_0x2d50870; 1 drivers +v0x2b36270_0 .net *"_s16", 0 0, L_0x2d50bd0; 1 drivers +v0x2b363a0_0 .net *"_s20", 0 0, L_0x2d50fa0; 1 drivers +v0x2b36480_0 .net *"_s24", 0 0, L_0x2d512d0; 1 drivers +v0x2b36560_0 .net *"_s28", 0 0, L_0x2d51260; 1 drivers +v0x2b36640_0 .net *"_s4", 0 0, L_0x2d50250; 1 drivers +v0x2b367b0_0 .net *"_s8", 0 0, L_0x2d50560; 1 drivers +v0x2b36890_0 .net "out", 7 0, L_0x2d515e0; alias, 1 drivers +L_0x2d4ffc0 .part L_0x2d4be50, 0, 1; +L_0x2d501b0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d50310 .part L_0x2d4be50, 1, 1; +L_0x2d50470 .part v0x2cdd2e0_0, 1, 1; +L_0x2d50620 .part L_0x2d4be50, 2, 1; +L_0x2d50780 .part v0x2cdd2e0_0, 2, 1; +L_0x2d50930 .part L_0x2d4be50, 3, 1; +L_0x2d50a90 .part v0x2cdd2e0_0, 3, 1; +L_0x2d50c90 .part L_0x2d4be50, 4, 1; +L_0x2d50f00 .part v0x2cdd2e0_0, 4, 1; +L_0x2d51010 .part L_0x2d4be50, 5, 1; +L_0x2d51170 .part v0x2cdd2e0_0, 5, 1; +L_0x2d51390 .part L_0x2d4be50, 6, 1; +L_0x2d514f0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d515e0_0_0 .concat8 [ 1 1 1 1], L_0x2d4ff00, L_0x2d50250, L_0x2d50560, L_0x2d50870; +LS_0x2d515e0_0_4 .concat8 [ 1 1 1 1], L_0x2d50bd0, L_0x2d50fa0, L_0x2d512d0, L_0x2d51260; +L_0x2d515e0 .concat8 [ 4 4 0 0], LS_0x2d515e0_0_0, LS_0x2d515e0_0_4; +L_0x2d519a0 .part L_0x2d4be50, 7, 1; +L_0x2d51b90 .part v0x2cdd2e0_0, 7, 1; +S_0x2b33a40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b33c50 .param/l "i" 0 4 54, +C4<00>; +L_0x2d4ff00/d .functor AND 1, L_0x2d4ffc0, L_0x2d501b0, C4<1>, C4<1>; +L_0x2d4ff00 .delay 1 (30000,30000,30000) L_0x2d4ff00/d; +v0x2b33d30_0 .net *"_s0", 0 0, L_0x2d4ffc0; 1 drivers +v0x2b33e10_0 .net *"_s1", 0 0, L_0x2d501b0; 1 drivers +S_0x2b33ef0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b34100 .param/l "i" 0 4 54, +C4<01>; +L_0x2d50250/d .functor AND 1, L_0x2d50310, L_0x2d50470, C4<1>, C4<1>; +L_0x2d50250 .delay 1 (30000,30000,30000) L_0x2d50250/d; +v0x2b341c0_0 .net *"_s0", 0 0, L_0x2d50310; 1 drivers +v0x2b342a0_0 .net *"_s1", 0 0, L_0x2d50470; 1 drivers +S_0x2b34380 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b34590 .param/l "i" 0 4 54, +C4<010>; +L_0x2d50560/d .functor AND 1, L_0x2d50620, L_0x2d50780, C4<1>, C4<1>; +L_0x2d50560 .delay 1 (30000,30000,30000) L_0x2d50560/d; +v0x2b34630_0 .net *"_s0", 0 0, L_0x2d50620; 1 drivers +v0x2b34710_0 .net *"_s1", 0 0, L_0x2d50780; 1 drivers +S_0x2b347f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b34a00 .param/l "i" 0 4 54, +C4<011>; +L_0x2d50870/d .functor AND 1, L_0x2d50930, L_0x2d50a90, C4<1>, C4<1>; +L_0x2d50870 .delay 1 (30000,30000,30000) L_0x2d50870/d; +v0x2b34ac0_0 .net *"_s0", 0 0, L_0x2d50930; 1 drivers +v0x2b34ba0_0 .net *"_s1", 0 0, L_0x2d50a90; 1 drivers +S_0x2b34c80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b34ee0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d50bd0/d .functor AND 1, L_0x2d50c90, L_0x2d50f00, C4<1>, C4<1>; +L_0x2d50bd0 .delay 1 (30000,30000,30000) L_0x2d50bd0/d; +v0x2b34fa0_0 .net *"_s0", 0 0, L_0x2d50c90; 1 drivers +v0x2b35080_0 .net *"_s1", 0 0, L_0x2d50f00; 1 drivers +S_0x2b35160 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b35370 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d50fa0/d .functor AND 1, L_0x2d51010, L_0x2d51170, C4<1>, C4<1>; +L_0x2d50fa0 .delay 1 (30000,30000,30000) L_0x2d50fa0/d; +v0x2b35430_0 .net *"_s0", 0 0, L_0x2d51010; 1 drivers +v0x2b35510_0 .net *"_s1", 0 0, L_0x2d51170; 1 drivers +S_0x2b355f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b35800 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d512d0/d .functor AND 1, L_0x2d51390, L_0x2d514f0, C4<1>, C4<1>; +L_0x2d512d0 .delay 1 (30000,30000,30000) L_0x2d512d0/d; +v0x2b358c0_0 .net *"_s0", 0 0, L_0x2d51390; 1 drivers +v0x2b359a0_0 .net *"_s1", 0 0, L_0x2d514f0; 1 drivers +S_0x2b35a80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b337e0; + .timescale -9 -12; +P_0x2b35c90 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d51260/d .functor AND 1, L_0x2d519a0, L_0x2d51b90, C4<1>, C4<1>; +L_0x2d51260 .delay 1 (30000,30000,30000) L_0x2d51260/d; +v0x2b35d50_0 .net *"_s0", 0 0, L_0x2d519a0; 1 drivers +v0x2b35e30_0 .net *"_s1", 0 0, L_0x2d51b90; 1 drivers +S_0x2b369f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b335c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x126e780/d .functor OR 1, L_0x126e840, L_0x126e9f0, C4<0>, C4<0>; -L_0x126e780 .delay 1 (30000,30000,30000) L_0x126e780/d; -v0x106d5a0_0 .net *"_s10", 0 0, L_0x126e840; 1 drivers -v0x106d680_0 .net *"_s12", 0 0, L_0x126e9f0; 1 drivers -v0x106d760_0 .net "in", 7 0, L_0x126c780; alias, 1 drivers -v0x106d830_0 .net "ors", 1 0, L_0x126e5a0; 1 drivers -v0x106d8f0_0 .net "out", 0 0, L_0x126e780; alias, 1 drivers -L_0x126d970 .part L_0x126c780, 0, 4; -L_0x126e5a0 .concat8 [ 1 1 0 0], L_0x126d660, L_0x126e290; -L_0x126e6e0 .part L_0x126c780, 4, 4; -L_0x126e840 .part L_0x126e5a0, 0, 1; -L_0x126e9f0 .part L_0x126e5a0, 1, 1; -S_0x106bc10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x106ba50; +L_0x2d535e0/d .functor OR 1, L_0x2d536a0, L_0x2d53850, C4<0>, C4<0>; +L_0x2d535e0 .delay 1 (30000,30000,30000) L_0x2d535e0/d; +v0x2b38540_0 .net *"_s10", 0 0, L_0x2d536a0; 1 drivers +v0x2b38620_0 .net *"_s12", 0 0, L_0x2d53850; 1 drivers +v0x2b38700_0 .net "in", 7 0, L_0x2d515e0; alias, 1 drivers +v0x2b387d0_0 .net "ors", 1 0, L_0x2d53400; 1 drivers +v0x2b38890_0 .net "out", 0 0, L_0x2d535e0; alias, 1 drivers +L_0x2d527d0 .part L_0x2d515e0, 0, 4; +L_0x2d53400 .concat8 [ 1 1 0 0], L_0x2d524c0, L_0x2d530f0; +L_0x2d53540 .part L_0x2d515e0, 4, 4; +L_0x2d536a0 .part L_0x2d53400, 0, 1; +L_0x2d53850 .part L_0x2d53400, 1, 1; +S_0x2b36bb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b369f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x126ce20/d .functor OR 1, L_0x126cee0, L_0x126d040, C4<0>, C4<0>; -L_0x126ce20 .delay 1 (30000,30000,30000) L_0x126ce20/d; -L_0x126d270/d .functor OR 1, L_0x126d380, L_0x126d4e0, C4<0>, C4<0>; -L_0x126d270 .delay 1 (30000,30000,30000) L_0x126d270/d; -L_0x126d660/d .functor OR 1, L_0x126d6d0, L_0x126d880, C4<0>, C4<0>; -L_0x126d660 .delay 1 (30000,30000,30000) L_0x126d660/d; -v0x106be60_0 .net *"_s0", 0 0, L_0x126ce20; 1 drivers -v0x106bf60_0 .net *"_s10", 0 0, L_0x126d380; 1 drivers -v0x106c040_0 .net *"_s12", 0 0, L_0x126d4e0; 1 drivers -v0x106c100_0 .net *"_s14", 0 0, L_0x126d6d0; 1 drivers -v0x106c1e0_0 .net *"_s16", 0 0, L_0x126d880; 1 drivers -v0x106c310_0 .net *"_s3", 0 0, L_0x126cee0; 1 drivers -v0x106c3f0_0 .net *"_s5", 0 0, L_0x126d040; 1 drivers -v0x106c4d0_0 .net *"_s6", 0 0, L_0x126d270; 1 drivers -v0x106c5b0_0 .net "in", 3 0, L_0x126d970; 1 drivers -v0x106c720_0 .net "ors", 1 0, L_0x126d180; 1 drivers -v0x106c800_0 .net "out", 0 0, L_0x126d660; 1 drivers -L_0x126cee0 .part L_0x126d970, 0, 1; -L_0x126d040 .part L_0x126d970, 1, 1; -L_0x126d180 .concat8 [ 1 1 0 0], L_0x126ce20, L_0x126d270; -L_0x126d380 .part L_0x126d970, 2, 1; -L_0x126d4e0 .part L_0x126d970, 3, 1; -L_0x126d6d0 .part L_0x126d180, 0, 1; -L_0x126d880 .part L_0x126d180, 1, 1; -S_0x106c920 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x106ba50; +L_0x2d51c80/d .functor OR 1, L_0x2d51d40, L_0x2d51ea0, C4<0>, C4<0>; +L_0x2d51c80 .delay 1 (30000,30000,30000) L_0x2d51c80/d; +L_0x2d520d0/d .functor OR 1, L_0x2d521e0, L_0x2d52340, C4<0>, C4<0>; +L_0x2d520d0 .delay 1 (30000,30000,30000) L_0x2d520d0/d; +L_0x2d524c0/d .functor OR 1, L_0x2d52530, L_0x2d526e0, C4<0>, C4<0>; +L_0x2d524c0 .delay 1 (30000,30000,30000) L_0x2d524c0/d; +v0x2b36e00_0 .net *"_s0", 0 0, L_0x2d51c80; 1 drivers +v0x2b36f00_0 .net *"_s10", 0 0, L_0x2d521e0; 1 drivers +v0x2b36fe0_0 .net *"_s12", 0 0, L_0x2d52340; 1 drivers +v0x2b370a0_0 .net *"_s14", 0 0, L_0x2d52530; 1 drivers +v0x2b37180_0 .net *"_s16", 0 0, L_0x2d526e0; 1 drivers +v0x2b372b0_0 .net *"_s3", 0 0, L_0x2d51d40; 1 drivers +v0x2b37390_0 .net *"_s5", 0 0, L_0x2d51ea0; 1 drivers +v0x2b37470_0 .net *"_s6", 0 0, L_0x2d520d0; 1 drivers +v0x2b37550_0 .net "in", 3 0, L_0x2d527d0; 1 drivers +v0x2b376c0_0 .net "ors", 1 0, L_0x2d51fe0; 1 drivers +v0x2b377a0_0 .net "out", 0 0, L_0x2d524c0; 1 drivers +L_0x2d51d40 .part L_0x2d527d0, 0, 1; +L_0x2d51ea0 .part L_0x2d527d0, 1, 1; +L_0x2d51fe0 .concat8 [ 1 1 0 0], L_0x2d51c80, L_0x2d520d0; +L_0x2d521e0 .part L_0x2d527d0, 2, 1; +L_0x2d52340 .part L_0x2d527d0, 3, 1; +L_0x2d52530 .part L_0x2d51fe0, 0, 1; +L_0x2d526e0 .part L_0x2d51fe0, 1, 1; +S_0x2b378c0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b369f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x126daa0/d .functor OR 1, L_0x126db10, L_0x126dc70, C4<0>, C4<0>; -L_0x126daa0 .delay 1 (30000,30000,30000) L_0x126daa0/d; -L_0x126dea0/d .functor OR 1, L_0x126dfb0, L_0x126e110, C4<0>, C4<0>; -L_0x126dea0 .delay 1 (30000,30000,30000) L_0x126dea0/d; -L_0x126e290/d .functor OR 1, L_0x126e300, L_0x126e4b0, C4<0>, C4<0>; -L_0x126e290 .delay 1 (30000,30000,30000) L_0x126e290/d; -v0x106cae0_0 .net *"_s0", 0 0, L_0x126daa0; 1 drivers -v0x106cbe0_0 .net *"_s10", 0 0, L_0x126dfb0; 1 drivers -v0x106ccc0_0 .net *"_s12", 0 0, L_0x126e110; 1 drivers -v0x106cd80_0 .net *"_s14", 0 0, L_0x126e300; 1 drivers -v0x106ce60_0 .net *"_s16", 0 0, L_0x126e4b0; 1 drivers -v0x106cf90_0 .net *"_s3", 0 0, L_0x126db10; 1 drivers -v0x106d070_0 .net *"_s5", 0 0, L_0x126dc70; 1 drivers -v0x106d150_0 .net *"_s6", 0 0, L_0x126dea0; 1 drivers -v0x106d230_0 .net "in", 3 0, L_0x126e6e0; 1 drivers -v0x106d3a0_0 .net "ors", 1 0, L_0x126ddb0; 1 drivers -v0x106d480_0 .net "out", 0 0, L_0x126e290; 1 drivers -L_0x126db10 .part L_0x126e6e0, 0, 1; -L_0x126dc70 .part L_0x126e6e0, 1, 1; -L_0x126ddb0 .concat8 [ 1 1 0 0], L_0x126daa0, L_0x126dea0; -L_0x126dfb0 .part L_0x126e6e0, 2, 1; -L_0x126e110 .part L_0x126e6e0, 3, 1; -L_0x126e300 .part L_0x126ddb0, 0, 1; -L_0x126e4b0 .part L_0x126ddb0, 1, 1; -S_0x106dd90 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1066ec0; +L_0x2d52900/d .functor OR 1, L_0x2d52970, L_0x2d52ad0, C4<0>, C4<0>; +L_0x2d52900 .delay 1 (30000,30000,30000) L_0x2d52900/d; +L_0x2d52d00/d .functor OR 1, L_0x2d52e10, L_0x2d52f70, C4<0>, C4<0>; +L_0x2d52d00 .delay 1 (30000,30000,30000) L_0x2d52d00/d; +L_0x2d530f0/d .functor OR 1, L_0x2d53160, L_0x2d53310, C4<0>, C4<0>; +L_0x2d530f0 .delay 1 (30000,30000,30000) L_0x2d530f0/d; +v0x2b37a80_0 .net *"_s0", 0 0, L_0x2d52900; 1 drivers +v0x2b37b80_0 .net *"_s10", 0 0, L_0x2d52e10; 1 drivers +v0x2b37c60_0 .net *"_s12", 0 0, L_0x2d52f70; 1 drivers +v0x2b37d20_0 .net *"_s14", 0 0, L_0x2d53160; 1 drivers +v0x2b37e00_0 .net *"_s16", 0 0, L_0x2d53310; 1 drivers +v0x2b37f30_0 .net *"_s3", 0 0, L_0x2d52970; 1 drivers +v0x2b38010_0 .net *"_s5", 0 0, L_0x2d52ad0; 1 drivers +v0x2b380f0_0 .net *"_s6", 0 0, L_0x2d52d00; 1 drivers +v0x2b381d0_0 .net "in", 3 0, L_0x2d53540; 1 drivers +v0x2b38340_0 .net "ors", 1 0, L_0x2d52c10; 1 drivers +v0x2b38420_0 .net "out", 0 0, L_0x2d530f0; 1 drivers +L_0x2d52970 .part L_0x2d53540, 0, 1; +L_0x2d52ad0 .part L_0x2d53540, 1, 1; +L_0x2d52c10 .concat8 [ 1 1 0 0], L_0x2d52900, L_0x2d52d00; +L_0x2d52e10 .part L_0x2d53540, 2, 1; +L_0x2d52f70 .part L_0x2d53540, 3, 1; +L_0x2d53160 .part L_0x2d52c10, 0, 1; +L_0x2d53310 .part L_0x2d52c10, 1, 1; +S_0x2b38d30 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b31e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10731c0_0 .net "ands", 7 0, L_0x1268d40; 1 drivers -v0x10732d0_0 .net "in", 7 0, L_0x1267280; alias, 1 drivers -v0x1073390_0 .net "out", 0 0, L_0x126ad40; alias, 1 drivers -v0x1073460_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x106dfe0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x106dd90; +v0x2b3e180_0 .net "ands", 7 0, L_0x2d4dba0; 1 drivers +v0x2b3e290_0 .net "in", 7 0, L_0x2d4bb10; alias, 1 drivers +v0x2b3e350_0 .net "out", 0 0, L_0x2d4fba0; alias, 1 drivers +v0x2b3e420_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b38f80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b38d30; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1070720_0 .net "A", 7 0, L_0x1267280; alias, 1 drivers -v0x1070820_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10708e0_0 .net *"_s0", 0 0, L_0x1267610; 1 drivers -v0x10709a0_0 .net *"_s12", 0 0, L_0x1267fd0; 1 drivers -v0x1070a80_0 .net *"_s16", 0 0, L_0x1268330; 1 drivers -v0x1070bb0_0 .net *"_s20", 0 0, L_0x1268700; 1 drivers -v0x1070c90_0 .net *"_s24", 0 0, L_0x1268a30; 1 drivers -v0x1070d70_0 .net *"_s28", 0 0, L_0x12689c0; 1 drivers -v0x1070e50_0 .net *"_s4", 0 0, L_0x12679b0; 1 drivers -v0x1070fc0_0 .net *"_s8", 0 0, L_0x1267cc0; 1 drivers -v0x10710a0_0 .net "out", 7 0, L_0x1268d40; alias, 1 drivers -L_0x1267720 .part L_0x1267280, 0, 1; -L_0x1267910 .part v0x12010b0_0, 0, 1; -L_0x1267a70 .part L_0x1267280, 1, 1; -L_0x1267bd0 .part v0x12010b0_0, 1, 1; -L_0x1267d80 .part L_0x1267280, 2, 1; -L_0x1267ee0 .part v0x12010b0_0, 2, 1; -L_0x1268090 .part L_0x1267280, 3, 1; -L_0x12681f0 .part v0x12010b0_0, 3, 1; -L_0x12683f0 .part L_0x1267280, 4, 1; -L_0x1268660 .part v0x12010b0_0, 4, 1; -L_0x1268770 .part L_0x1267280, 5, 1; -L_0x12688d0 .part v0x12010b0_0, 5, 1; -L_0x1268af0 .part L_0x1267280, 6, 1; -L_0x1268c50 .part v0x12010b0_0, 6, 1; -LS_0x1268d40_0_0 .concat8 [ 1 1 1 1], L_0x1267610, L_0x12679b0, L_0x1267cc0, L_0x1267fd0; -LS_0x1268d40_0_4 .concat8 [ 1 1 1 1], L_0x1268330, L_0x1268700, L_0x1268a30, L_0x12689c0; -L_0x1268d40 .concat8 [ 4 4 0 0], LS_0x1268d40_0_0, LS_0x1268d40_0_4; -L_0x1269100 .part L_0x1267280, 7, 1; -L_0x12692f0 .part v0x12010b0_0, 7, 1; -S_0x106e220 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x106e430 .param/l "i" 0 4 54, +C4<00>; -L_0x1267610/d .functor AND 1, L_0x1267720, L_0x1267910, C4<1>, C4<1>; -L_0x1267610 .delay 1 (30000,30000,30000) L_0x1267610/d; -v0x106e510_0 .net *"_s0", 0 0, L_0x1267720; 1 drivers -v0x106e5f0_0 .net *"_s1", 0 0, L_0x1267910; 1 drivers -S_0x106e6d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x106e8e0 .param/l "i" 0 4 54, +C4<01>; -L_0x12679b0/d .functor AND 1, L_0x1267a70, L_0x1267bd0, C4<1>, C4<1>; -L_0x12679b0 .delay 1 (30000,30000,30000) L_0x12679b0/d; -v0x106e9a0_0 .net *"_s0", 0 0, L_0x1267a70; 1 drivers -v0x106ea80_0 .net *"_s1", 0 0, L_0x1267bd0; 1 drivers -S_0x106eb60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x106eda0 .param/l "i" 0 4 54, +C4<010>; -L_0x1267cc0/d .functor AND 1, L_0x1267d80, L_0x1267ee0, C4<1>, C4<1>; -L_0x1267cc0 .delay 1 (30000,30000,30000) L_0x1267cc0/d; -v0x106ee40_0 .net *"_s0", 0 0, L_0x1267d80; 1 drivers -v0x106ef20_0 .net *"_s1", 0 0, L_0x1267ee0; 1 drivers -S_0x106f000 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x106f210 .param/l "i" 0 4 54, +C4<011>; -L_0x1267fd0/d .functor AND 1, L_0x1268090, L_0x12681f0, C4<1>, C4<1>; -L_0x1267fd0 .delay 1 (30000,30000,30000) L_0x1267fd0/d; -v0x106f2d0_0 .net *"_s0", 0 0, L_0x1268090; 1 drivers -v0x106f3b0_0 .net *"_s1", 0 0, L_0x12681f0; 1 drivers -S_0x106f490 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x106f6f0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1268330/d .functor AND 1, L_0x12683f0, L_0x1268660, C4<1>, C4<1>; -L_0x1268330 .delay 1 (30000,30000,30000) L_0x1268330/d; -v0x106f7b0_0 .net *"_s0", 0 0, L_0x12683f0; 1 drivers -v0x106f890_0 .net *"_s1", 0 0, L_0x1268660; 1 drivers -S_0x106f970 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x106fb80 .param/l "i" 0 4 54, +C4<0101>; -L_0x1268700/d .functor AND 1, L_0x1268770, L_0x12688d0, C4<1>, C4<1>; -L_0x1268700 .delay 1 (30000,30000,30000) L_0x1268700/d; -v0x106fc40_0 .net *"_s0", 0 0, L_0x1268770; 1 drivers -v0x106fd20_0 .net *"_s1", 0 0, L_0x12688d0; 1 drivers -S_0x106fe00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x1070010 .param/l "i" 0 4 54, +C4<0110>; -L_0x1268a30/d .functor AND 1, L_0x1268af0, L_0x1268c50, C4<1>, C4<1>; -L_0x1268a30 .delay 1 (30000,30000,30000) L_0x1268a30/d; -v0x10700d0_0 .net *"_s0", 0 0, L_0x1268af0; 1 drivers -v0x10701b0_0 .net *"_s1", 0 0, L_0x1268c50; 1 drivers -S_0x1070290 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x106dfe0; - .timescale -9 -12; -P_0x10704a0 .param/l "i" 0 4 54, +C4<0111>; -L_0x12689c0/d .functor AND 1, L_0x1269100, L_0x12692f0, C4<1>, C4<1>; -L_0x12689c0 .delay 1 (30000,30000,30000) L_0x12689c0/d; -v0x1070560_0 .net *"_s0", 0 0, L_0x1269100; 1 drivers -v0x1070640_0 .net *"_s1", 0 0, L_0x12692f0; 1 drivers -S_0x1071200 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x106dd90; +v0x2b3b6c0_0 .net "A", 7 0, L_0x2d4bb10; alias, 1 drivers +v0x2b3b7c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b3b880_0 .net *"_s0", 0 0, L_0x2d4c390; 1 drivers +v0x2b3b940_0 .net *"_s12", 0 0, L_0x2d4cd50; 1 drivers +v0x2b3ba20_0 .net *"_s16", 0 0, L_0x2d4d0b0; 1 drivers +v0x2b3bb50_0 .net *"_s20", 0 0, L_0x2d4d4e0; 1 drivers +v0x2b3bc30_0 .net *"_s24", 0 0, L_0x2d4d810; 1 drivers +v0x2b3bd10_0 .net *"_s28", 0 0, L_0x2d4d7a0; 1 drivers +v0x2b3bdf0_0 .net *"_s4", 0 0, L_0x2d4c730; 1 drivers +v0x2b3bf60_0 .net *"_s8", 0 0, L_0x2d4ca40; 1 drivers +v0x2b3c000_0 .net "out", 7 0, L_0x2d4dba0; alias, 1 drivers +L_0x2d4c4a0 .part L_0x2d4bb10, 0, 1; +L_0x2d4c690 .part v0x2cdd2e0_0, 0, 1; +L_0x2d4c7f0 .part L_0x2d4bb10, 1, 1; +L_0x2d4c950 .part v0x2cdd2e0_0, 1, 1; +L_0x2d4cb00 .part L_0x2d4bb10, 2, 1; +L_0x2d4cc60 .part v0x2cdd2e0_0, 2, 1; +L_0x2d4ce10 .part L_0x2d4bb10, 3, 1; +L_0x2d4cf70 .part v0x2cdd2e0_0, 3, 1; +L_0x2d4d170 .part L_0x2d4bb10, 4, 1; +L_0x2d4d3e0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d4d550 .part L_0x2d4bb10, 5, 1; +L_0x2d4d6b0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d4d8d0 .part L_0x2d4bb10, 6, 1; +L_0x2d4da30 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d4dba0_0_0 .concat8 [ 1 1 1 1], L_0x2d4c390, L_0x2d4c730, L_0x2d4ca40, L_0x2d4cd50; +LS_0x2d4dba0_0_4 .concat8 [ 1 1 1 1], L_0x2d4d0b0, L_0x2d4d4e0, L_0x2d4d810, L_0x2d4d7a0; +L_0x2d4dba0 .concat8 [ 4 4 0 0], LS_0x2d4dba0_0_0, LS_0x2d4dba0_0_4; +L_0x2d4df60 .part L_0x2d4bb10, 7, 1; +L_0x2d4e150 .part v0x2cdd2e0_0, 7, 1; +S_0x2b391c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b393d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d4c390/d .functor AND 1, L_0x2d4c4a0, L_0x2d4c690, C4<1>, C4<1>; +L_0x2d4c390 .delay 1 (30000,30000,30000) L_0x2d4c390/d; +v0x2b394b0_0 .net *"_s0", 0 0, L_0x2d4c4a0; 1 drivers +v0x2b39590_0 .net *"_s1", 0 0, L_0x2d4c690; 1 drivers +S_0x2b39670 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b39880 .param/l "i" 0 4 54, +C4<01>; +L_0x2d4c730/d .functor AND 1, L_0x2d4c7f0, L_0x2d4c950, C4<1>, C4<1>; +L_0x2d4c730 .delay 1 (30000,30000,30000) L_0x2d4c730/d; +v0x2b39940_0 .net *"_s0", 0 0, L_0x2d4c7f0; 1 drivers +v0x2b39a20_0 .net *"_s1", 0 0, L_0x2d4c950; 1 drivers +S_0x2b39b00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b39d40 .param/l "i" 0 4 54, +C4<010>; +L_0x2d4ca40/d .functor AND 1, L_0x2d4cb00, L_0x2d4cc60, C4<1>, C4<1>; +L_0x2d4ca40 .delay 1 (30000,30000,30000) L_0x2d4ca40/d; +v0x2b39de0_0 .net *"_s0", 0 0, L_0x2d4cb00; 1 drivers +v0x2b39ec0_0 .net *"_s1", 0 0, L_0x2d4cc60; 1 drivers +S_0x2b39fa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b3a1b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d4cd50/d .functor AND 1, L_0x2d4ce10, L_0x2d4cf70, C4<1>, C4<1>; +L_0x2d4cd50 .delay 1 (30000,30000,30000) L_0x2d4cd50/d; +v0x2b3a270_0 .net *"_s0", 0 0, L_0x2d4ce10; 1 drivers +v0x2b3a350_0 .net *"_s1", 0 0, L_0x2d4cf70; 1 drivers +S_0x2b3a430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b3a690 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d4d0b0/d .functor AND 1, L_0x2d4d170, L_0x2d4d3e0, C4<1>, C4<1>; +L_0x2d4d0b0 .delay 1 (30000,30000,30000) L_0x2d4d0b0/d; +v0x2b3a750_0 .net *"_s0", 0 0, L_0x2d4d170; 1 drivers +v0x2b3a830_0 .net *"_s1", 0 0, L_0x2d4d3e0; 1 drivers +S_0x2b3a910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b3ab20 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d4d4e0/d .functor AND 1, L_0x2d4d550, L_0x2d4d6b0, C4<1>, C4<1>; +L_0x2d4d4e0 .delay 1 (30000,30000,30000) L_0x2d4d4e0/d; +v0x2b3abe0_0 .net *"_s0", 0 0, L_0x2d4d550; 1 drivers +v0x2b3acc0_0 .net *"_s1", 0 0, L_0x2d4d6b0; 1 drivers +S_0x2b3ada0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b3afb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d4d810/d .functor AND 1, L_0x2d4d8d0, L_0x2d4da30, C4<1>, C4<1>; +L_0x2d4d810 .delay 1 (30000,30000,30000) L_0x2d4d810/d; +v0x2b3b070_0 .net *"_s0", 0 0, L_0x2d4d8d0; 1 drivers +v0x2b3b150_0 .net *"_s1", 0 0, L_0x2d4da30; 1 drivers +S_0x2b3b230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b38f80; + .timescale -9 -12; +P_0x2b3b440 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d4d7a0/d .functor AND 1, L_0x2d4df60, L_0x2d4e150, C4<1>, C4<1>; +L_0x2d4d7a0 .delay 1 (30000,30000,30000) L_0x2d4d7a0/d; +v0x2b3b500_0 .net *"_s0", 0 0, L_0x2d4df60; 1 drivers +v0x2b3b5e0_0 .net *"_s1", 0 0, L_0x2d4e150; 1 drivers +S_0x2b3c140 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b38d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x126ad40/d .functor OR 1, L_0x126ae00, L_0x126afb0, C4<0>, C4<0>; -L_0x126ad40 .delay 1 (30000,30000,30000) L_0x126ad40/d; -v0x1072d50_0 .net *"_s10", 0 0, L_0x126ae00; 1 drivers -v0x1072e30_0 .net *"_s12", 0 0, L_0x126afb0; 1 drivers -v0x1072f10_0 .net "in", 7 0, L_0x1268d40; alias, 1 drivers -v0x1072fe0_0 .net "ors", 1 0, L_0x126ab60; 1 drivers -v0x10730a0_0 .net "out", 0 0, L_0x126ad40; alias, 1 drivers -L_0x1269f30 .part L_0x1268d40, 0, 4; -L_0x126ab60 .concat8 [ 1 1 0 0], L_0x1269c20, L_0x126a850; -L_0x126aca0 .part L_0x1268d40, 4, 4; -L_0x126ae00 .part L_0x126ab60, 0, 1; -L_0x126afb0 .part L_0x126ab60, 1, 1; -S_0x10713c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1071200; +L_0x2d4fba0/d .functor OR 1, L_0x2d4fc60, L_0x2d4fe10, C4<0>, C4<0>; +L_0x2d4fba0 .delay 1 (30000,30000,30000) L_0x2d4fba0/d; +v0x2b3dd10_0 .net *"_s10", 0 0, L_0x2d4fc60; 1 drivers +v0x2b3ddf0_0 .net *"_s12", 0 0, L_0x2d4fe10; 1 drivers +v0x2b3ded0_0 .net "in", 7 0, L_0x2d4dba0; alias, 1 drivers +v0x2b3dfa0_0 .net "ors", 1 0, L_0x2d4f9c0; 1 drivers +v0x2b3e060_0 .net "out", 0 0, L_0x2d4fba0; alias, 1 drivers +L_0x2d4ed90 .part L_0x2d4dba0, 0, 4; +L_0x2d4f9c0 .concat8 [ 1 1 0 0], L_0x2d4ea80, L_0x2d4f6b0; +L_0x2d4fb00 .part L_0x2d4dba0, 4, 4; +L_0x2d4fc60 .part L_0x2d4f9c0, 0, 1; +L_0x2d4fe10 .part L_0x2d4f9c0, 1, 1; +S_0x2b3c350 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b3c140; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12693e0/d .functor OR 1, L_0x12694a0, L_0x1269600, C4<0>, C4<0>; -L_0x12693e0 .delay 1 (30000,30000,30000) L_0x12693e0/d; -L_0x1269830/d .functor OR 1, L_0x1269940, L_0x1269aa0, C4<0>, C4<0>; -L_0x1269830 .delay 1 (30000,30000,30000) L_0x1269830/d; -L_0x1269c20/d .functor OR 1, L_0x1269c90, L_0x1269e40, C4<0>, C4<0>; -L_0x1269c20 .delay 1 (30000,30000,30000) L_0x1269c20/d; -v0x1071610_0 .net *"_s0", 0 0, L_0x12693e0; 1 drivers -v0x1071710_0 .net *"_s10", 0 0, L_0x1269940; 1 drivers -v0x10717f0_0 .net *"_s12", 0 0, L_0x1269aa0; 1 drivers -v0x10718b0_0 .net *"_s14", 0 0, L_0x1269c90; 1 drivers -v0x1071990_0 .net *"_s16", 0 0, L_0x1269e40; 1 drivers -v0x1071ac0_0 .net *"_s3", 0 0, L_0x12694a0; 1 drivers -v0x1071ba0_0 .net *"_s5", 0 0, L_0x1269600; 1 drivers -v0x1071c80_0 .net *"_s6", 0 0, L_0x1269830; 1 drivers -v0x1071d60_0 .net "in", 3 0, L_0x1269f30; 1 drivers -v0x1071ed0_0 .net "ors", 1 0, L_0x1269740; 1 drivers -v0x1071fb0_0 .net "out", 0 0, L_0x1269c20; 1 drivers -L_0x12694a0 .part L_0x1269f30, 0, 1; -L_0x1269600 .part L_0x1269f30, 1, 1; -L_0x1269740 .concat8 [ 1 1 0 0], L_0x12693e0, L_0x1269830; -L_0x1269940 .part L_0x1269f30, 2, 1; -L_0x1269aa0 .part L_0x1269f30, 3, 1; -L_0x1269c90 .part L_0x1269740, 0, 1; -L_0x1269e40 .part L_0x1269740, 1, 1; -S_0x10720d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1071200; +L_0x2d4e240/d .functor OR 1, L_0x2d4e300, L_0x2d4e460, C4<0>, C4<0>; +L_0x2d4e240 .delay 1 (30000,30000,30000) L_0x2d4e240/d; +L_0x2d4e690/d .functor OR 1, L_0x2d4e7a0, L_0x2d4e900, C4<0>, C4<0>; +L_0x2d4e690 .delay 1 (30000,30000,30000) L_0x2d4e690/d; +L_0x2d4ea80/d .functor OR 1, L_0x2d4eaf0, L_0x2d4eca0, C4<0>, C4<0>; +L_0x2d4ea80 .delay 1 (30000,30000,30000) L_0x2d4ea80/d; +v0x2b3c5a0_0 .net *"_s0", 0 0, L_0x2d4e240; 1 drivers +v0x2b3c6a0_0 .net *"_s10", 0 0, L_0x2d4e7a0; 1 drivers +v0x2b3c780_0 .net *"_s12", 0 0, L_0x2d4e900; 1 drivers +v0x2b3c870_0 .net *"_s14", 0 0, L_0x2d4eaf0; 1 drivers +v0x2b3c950_0 .net *"_s16", 0 0, L_0x2d4eca0; 1 drivers +v0x2b3ca80_0 .net *"_s3", 0 0, L_0x2d4e300; 1 drivers +v0x2b3cb60_0 .net *"_s5", 0 0, L_0x2d4e460; 1 drivers +v0x2b3cc40_0 .net *"_s6", 0 0, L_0x2d4e690; 1 drivers +v0x2b3cd20_0 .net "in", 3 0, L_0x2d4ed90; 1 drivers +v0x2b3ce90_0 .net "ors", 1 0, L_0x2d4e5a0; 1 drivers +v0x2b3cf70_0 .net "out", 0 0, L_0x2d4ea80; 1 drivers +L_0x2d4e300 .part L_0x2d4ed90, 0, 1; +L_0x2d4e460 .part L_0x2d4ed90, 1, 1; +L_0x2d4e5a0 .concat8 [ 1 1 0 0], L_0x2d4e240, L_0x2d4e690; +L_0x2d4e7a0 .part L_0x2d4ed90, 2, 1; +L_0x2d4e900 .part L_0x2d4ed90, 3, 1; +L_0x2d4eaf0 .part L_0x2d4e5a0, 0, 1; +L_0x2d4eca0 .part L_0x2d4e5a0, 1, 1; +S_0x2b3d090 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b3c140; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x126a060/d .functor OR 1, L_0x126a0d0, L_0x126a230, C4<0>, C4<0>; -L_0x126a060 .delay 1 (30000,30000,30000) L_0x126a060/d; -L_0x126a460/d .functor OR 1, L_0x126a570, L_0x126a6d0, C4<0>, C4<0>; -L_0x126a460 .delay 1 (30000,30000,30000) L_0x126a460/d; -L_0x126a850/d .functor OR 1, L_0x126a8c0, L_0x126aa70, C4<0>, C4<0>; -L_0x126a850 .delay 1 (30000,30000,30000) L_0x126a850/d; -v0x1072290_0 .net *"_s0", 0 0, L_0x126a060; 1 drivers -v0x1072390_0 .net *"_s10", 0 0, L_0x126a570; 1 drivers -v0x1072470_0 .net *"_s12", 0 0, L_0x126a6d0; 1 drivers -v0x1072530_0 .net *"_s14", 0 0, L_0x126a8c0; 1 drivers -v0x1072610_0 .net *"_s16", 0 0, L_0x126aa70; 1 drivers -v0x1072740_0 .net *"_s3", 0 0, L_0x126a0d0; 1 drivers -v0x1072820_0 .net *"_s5", 0 0, L_0x126a230; 1 drivers -v0x1072900_0 .net *"_s6", 0 0, L_0x126a460; 1 drivers -v0x10729e0_0 .net "in", 3 0, L_0x126aca0; 1 drivers -v0x1072b50_0 .net "ors", 1 0, L_0x126a370; 1 drivers -v0x1072c30_0 .net "out", 0 0, L_0x126a850; 1 drivers -L_0x126a0d0 .part L_0x126aca0, 0, 1; -L_0x126a230 .part L_0x126aca0, 1, 1; -L_0x126a370 .concat8 [ 1 1 0 0], L_0x126a060, L_0x126a460; -L_0x126a570 .part L_0x126aca0, 2, 1; -L_0x126a6d0 .part L_0x126aca0, 3, 1; -L_0x126a8c0 .part L_0x126a370, 0, 1; -L_0x126aa70 .part L_0x126a370, 1, 1; -S_0x1073540 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1066ec0; +L_0x2d4eec0/d .functor OR 1, L_0x2d4ef30, L_0x2d4f090, C4<0>, C4<0>; +L_0x2d4eec0 .delay 1 (30000,30000,30000) L_0x2d4eec0/d; +L_0x2d4f2c0/d .functor OR 1, L_0x2d4f3d0, L_0x2d4f530, C4<0>, C4<0>; +L_0x2d4f2c0 .delay 1 (30000,30000,30000) L_0x2d4f2c0/d; +L_0x2d4f6b0/d .functor OR 1, L_0x2d4f720, L_0x2d4f8d0, C4<0>, C4<0>; +L_0x2d4f6b0 .delay 1 (30000,30000,30000) L_0x2d4f6b0/d; +v0x2b3d250_0 .net *"_s0", 0 0, L_0x2d4eec0; 1 drivers +v0x2b3d350_0 .net *"_s10", 0 0, L_0x2d4f3d0; 1 drivers +v0x2b3d430_0 .net *"_s12", 0 0, L_0x2d4f530; 1 drivers +v0x2b3d4f0_0 .net *"_s14", 0 0, L_0x2d4f720; 1 drivers +v0x2b3d5d0_0 .net *"_s16", 0 0, L_0x2d4f8d0; 1 drivers +v0x2b3d700_0 .net *"_s3", 0 0, L_0x2d4ef30; 1 drivers +v0x2b3d7e0_0 .net *"_s5", 0 0, L_0x2d4f090; 1 drivers +v0x2b3d8c0_0 .net *"_s6", 0 0, L_0x2d4f2c0; 1 drivers +v0x2b3d9a0_0 .net "in", 3 0, L_0x2d4fb00; 1 drivers +v0x2b3db10_0 .net "ors", 1 0, L_0x2d4f1d0; 1 drivers +v0x2b3dbf0_0 .net "out", 0 0, L_0x2d4f6b0; 1 drivers +L_0x2d4ef30 .part L_0x2d4fb00, 0, 1; +L_0x2d4f090 .part L_0x2d4fb00, 1, 1; +L_0x2d4f1d0 .concat8 [ 1 1 0 0], L_0x2d4eec0, L_0x2d4f2c0; +L_0x2d4f3d0 .part L_0x2d4fb00, 2, 1; +L_0x2d4f530 .part L_0x2d4fb00, 3, 1; +L_0x2d4f720 .part L_0x2d4f1d0, 0, 1; +L_0x2d4f8d0 .part L_0x2d4f1d0, 1, 1; +S_0x2b3e500 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b31e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -5990,80 +6333,80 @@ S_0x1073540 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1066ec0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12665f0/d .functor XNOR 1, L_0x126ebe0, L_0x126ed40, C4<0>, C4<0>; -L_0x12665f0 .delay 1 (20000,20000,20000) L_0x12665f0/d; -L_0x1266860/d .functor AND 1, L_0x126ebe0, L_0x12654e0, C4<1>, C4<1>; -L_0x1266860 .delay 1 (30000,30000,30000) L_0x1266860/d; -L_0x12668d0/d .functor AND 1, L_0x12665f0, L_0x1265280, C4<1>, C4<1>; -L_0x12668d0 .delay 1 (30000,30000,30000) L_0x12668d0/d; -L_0x1266a30/d .functor OR 1, L_0x12668d0, L_0x1266860, C4<0>, C4<0>; -L_0x1266a30 .delay 1 (30000,30000,30000) L_0x1266a30/d; -v0x10737f0_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers -v0x10738e0_0 .net "a_", 0 0, L_0x12653d0; alias, 1 drivers -v0x10739a0_0 .net "b", 0 0, L_0x126ed40; alias, 1 drivers -v0x1073a90_0 .net "b_", 0 0, L_0x12654e0; alias, 1 drivers -v0x1073b30_0 .net "carryin", 0 0, L_0x1265280; alias, 1 drivers -v0x1073c70_0 .net "eq", 0 0, L_0x12665f0; 1 drivers -v0x1073d30_0 .net "lt", 0 0, L_0x1266860; 1 drivers -v0x1073df0_0 .net "out", 0 0, L_0x1266a30; 1 drivers -v0x1073eb0_0 .net "w0", 0 0, L_0x12668d0; 1 drivers -S_0x1074100 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1066ec0; +L_0x2d4a950/d .functor XNOR 1, L_0x2d53a40, L_0x2d53ba0, C4<0>, C4<0>; +L_0x2d4a950 .delay 1 (20000,20000,20000) L_0x2d4a950/d; +L_0x2d4aad0/d .functor AND 1, L_0x2d53a40, L_0x2d496e0, C4<1>, C4<1>; +L_0x2d4aad0 .delay 1 (30000,30000,30000) L_0x2d4aad0/d; +L_0x2d4ac30/d .functor AND 1, L_0x2d4a950, L_0x2d494d0, C4<1>, C4<1>; +L_0x2d4ac30 .delay 1 (30000,30000,30000) L_0x2d4ac30/d; +L_0x2d4ad40/d .functor OR 1, L_0x2d4ac30, L_0x2d4aad0, C4<0>, C4<0>; +L_0x2d4ad40 .delay 1 (30000,30000,30000) L_0x2d4ad40/d; +v0x2b3e7b0_0 .net "a", 0 0, L_0x2d53a40; alias, 1 drivers +v0x2b3e8a0_0 .net "a_", 0 0, L_0x2d495d0; alias, 1 drivers +v0x2b3e960_0 .net "b", 0 0, L_0x2d53ba0; alias, 1 drivers +v0x2b3ea50_0 .net "b_", 0 0, L_0x2d496e0; alias, 1 drivers +v0x2b3eaf0_0 .net "carryin", 0 0, L_0x2d494d0; alias, 1 drivers +v0x2b3ec30_0 .net "eq", 0 0, L_0x2d4a950; 1 drivers +v0x2b3ecf0_0 .net "lt", 0 0, L_0x2d4aad0; 1 drivers +v0x2b3edb0_0 .net "out", 0 0, L_0x2d4ad40; 1 drivers +v0x2b3ee70_0 .net "w0", 0 0, L_0x2d4ac30; 1 drivers +S_0x2b3f0c0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b31e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12663d0/d .functor OR 1, L_0x1265ed0, L_0x1075360, C4<0>, C4<0>; -L_0x12663d0 .delay 1 (30000,30000,30000) L_0x12663d0/d; -v0x1074ef0_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers -v0x1075040_0 .net "b", 0 0, L_0x12654e0; alias, 1 drivers -v0x1075100_0 .net "c1", 0 0, L_0x1265ed0; 1 drivers -v0x10751a0_0 .net "c2", 0 0, L_0x1075360; 1 drivers -v0x1075270_0 .net "carryin", 0 0, L_0x1265280; alias, 1 drivers -v0x10753f0_0 .net "carryout", 0 0, L_0x12663d0; 1 drivers -v0x1075490_0 .net "s1", 0 0, L_0x1265e10; 1 drivers -v0x1075530_0 .net "sum", 0 0, L_0x1266030; 1 drivers -S_0x1074350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1074100; +L_0x2d4a530/d .functor OR 1, L_0x2d4a0d0, L_0x2b40320, C4<0>, C4<0>; +L_0x2d4a530 .delay 1 (30000,30000,30000) L_0x2d4a530/d; +v0x2b3feb0_0 .net "a", 0 0, L_0x2d53a40; alias, 1 drivers +v0x2b40000_0 .net "b", 0 0, L_0x2d496e0; alias, 1 drivers +v0x2b400c0_0 .net "c1", 0 0, L_0x2d4a0d0; 1 drivers +v0x2b40160_0 .net "c2", 0 0, L_0x2b40320; 1 drivers +v0x2b40230_0 .net "carryin", 0 0, L_0x2d494d0; alias, 1 drivers +v0x2b403b0_0 .net "carryout", 0 0, L_0x2d4a530; 1 drivers +v0x2b40450_0 .net "s1", 0 0, L_0x2d49f70; 1 drivers +v0x2b404f0_0 .net "sum", 0 0, L_0x2d4a1e0; 1 drivers +S_0x2b3f310 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b3f0c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1265e10/d .functor XOR 1, L_0x126ebe0, L_0x12654e0, C4<0>, C4<0>; -L_0x1265e10 .delay 1 (30000,30000,30000) L_0x1265e10/d; -L_0x1265ed0/d .functor AND 1, L_0x126ebe0, L_0x12654e0, C4<1>, C4<1>; -L_0x1265ed0 .delay 1 (30000,30000,30000) L_0x1265ed0/d; -v0x10745b0_0 .net "a", 0 0, L_0x126ebe0; alias, 1 drivers -v0x1074670_0 .net "b", 0 0, L_0x12654e0; alias, 1 drivers -v0x1074730_0 .net "carryout", 0 0, L_0x1265ed0; alias, 1 drivers -v0x10747d0_0 .net "sum", 0 0, L_0x1265e10; alias, 1 drivers -S_0x1074900 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1074100; +L_0x2d49f70/d .functor XOR 1, L_0x2d53a40, L_0x2d496e0, C4<0>, C4<0>; +L_0x2d49f70 .delay 1 (30000,30000,30000) L_0x2d49f70/d; +L_0x2d4a0d0/d .functor AND 1, L_0x2d53a40, L_0x2d496e0, C4<1>, C4<1>; +L_0x2d4a0d0 .delay 1 (30000,30000,30000) L_0x2d4a0d0/d; +v0x2b3f570_0 .net "a", 0 0, L_0x2d53a40; alias, 1 drivers +v0x2b3f630_0 .net "b", 0 0, L_0x2d496e0; alias, 1 drivers +v0x2b3f6f0_0 .net "carryout", 0 0, L_0x2d4a0d0; alias, 1 drivers +v0x2b3f790_0 .net "sum", 0 0, L_0x2d49f70; alias, 1 drivers +S_0x2b3f8c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b3f0c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1266030/d .functor XOR 1, L_0x1265e10, L_0x1265280, C4<0>, C4<0>; -L_0x1266030 .delay 1 (30000,30000,30000) L_0x1266030/d; -L_0x1075360/d .functor AND 1, L_0x1265e10, L_0x1265280, C4<1>, C4<1>; -L_0x1075360 .delay 1 (30000,30000,30000) L_0x1075360/d; -v0x1074b60_0 .net "a", 0 0, L_0x1265e10; alias, 1 drivers -v0x1074c30_0 .net "b", 0 0, L_0x1265280; alias, 1 drivers -v0x1074cd0_0 .net "carryout", 0 0, L_0x1075360; alias, 1 drivers -v0x1074da0_0 .net "sum", 0 0, L_0x1266030; alias, 1 drivers -S_0x1076950 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1066bf0; - .timescale -9 -12; -L_0x2b0ab3d05b58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05ba0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x126ec80/d .functor OR 1, L_0x2b0ab3d05b58, L_0x2b0ab3d05ba0, C4<0>, C4<0>; -L_0x126ec80 .delay 1 (30000,30000,30000) L_0x126ec80/d; -v0x1076b40_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05b58; 1 drivers -v0x1076c20_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05ba0; 1 drivers -S_0x1076d00 .scope generate, "alu_slices[11]" "alu_slices[11]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1076f10 .param/l "i" 0 3 41, +C4<01011>; -S_0x1076fd0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1076d00; +L_0x2d4a1e0/d .functor XOR 1, L_0x2d49f70, L_0x2d494d0, C4<0>, C4<0>; +L_0x2d4a1e0 .delay 1 (30000,30000,30000) L_0x2d4a1e0/d; +L_0x2b40320/d .functor AND 1, L_0x2d49f70, L_0x2d494d0, C4<1>, C4<1>; +L_0x2b40320 .delay 1 (30000,30000,30000) L_0x2b40320/d; +v0x2b3fb20_0 .net "a", 0 0, L_0x2d49f70; alias, 1 drivers +v0x2b3fbf0_0 .net "b", 0 0, L_0x2d494d0; alias, 1 drivers +v0x2b3fc90_0 .net "carryout", 0 0, L_0x2b40320; alias, 1 drivers +v0x2b3fd60_0 .net "sum", 0 0, L_0x2d4a1e0; alias, 1 drivers +S_0x2b42580 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b31b90; + .timescale -9 -12; +L_0x2ac6110b8a48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8a90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d49b90/d .functor OR 1, L_0x2ac6110b8a48, L_0x2ac6110b8a90, C4<0>, C4<0>; +L_0x2d49b90 .delay 1 (30000,30000,30000) L_0x2d49b90/d; +v0x2b42770_0 .net/2u *"_s0", 0 0, L_0x2ac6110b8a48; 1 drivers +v0x2b42850_0 .net/2u *"_s2", 0 0, L_0x2ac6110b8a90; 1 drivers +S_0x2b42930 .scope generate, "alu_slices[11]" "alu_slices[11]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b42b40 .param/l "i" 0 3 39, +C4<01011>; +S_0x2b42c00 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b42930; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -6072,445 +6415,476 @@ S_0x1076fd0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1076d00; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x126ef90/d .functor NOT 1, L_0x1278810, C4<0>, C4<0>, C4<0>; -L_0x126ef90 .delay 1 (10000,10000,10000) L_0x126ef90/d; -L_0x126f0f0/d .functor NOT 1, L_0x126ede0, C4<0>, C4<0>, C4<0>; -L_0x126f0f0 .delay 1 (10000,10000,10000) L_0x126f0f0/d; -L_0x1270140/d .functor XOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; -L_0x1270140 .delay 1 (30000,30000,30000) L_0x1270140/d; -L_0x2b0ab3d05be8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05c30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12707f0/d .functor OR 1, L_0x2b0ab3d05be8, L_0x2b0ab3d05c30, C4<0>, C4<0>; -L_0x12707f0 .delay 1 (30000,30000,30000) L_0x12707f0/d; -L_0x12709f0/d .functor AND 1, L_0x1278810, L_0x126ede0, C4<1>, C4<1>; -L_0x12709f0 .delay 1 (30000,30000,30000) L_0x12709f0/d; -L_0x1270ab0/d .functor NAND 1, L_0x1278810, L_0x126ede0, C4<1>, C4<1>; -L_0x1270ab0 .delay 1 (20000,20000,20000) L_0x1270ab0/d; -L_0x1270c10/d .functor XOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; -L_0x1270c10 .delay 1 (20000,20000,20000) L_0x1270c10/d; -L_0x12710c0/d .functor OR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; -L_0x12710c0 .delay 1 (30000,30000,30000) L_0x12710c0/d; -L_0x1278710/d .functor NOT 1, L_0x1274890, C4<0>, C4<0>, C4<0>; -L_0x1278710 .delay 1 (10000,10000,10000) L_0x1278710/d; -v0x10856c0_0 .net "A", 0 0, L_0x1278810; 1 drivers -v0x1085780_0 .net "A_", 0 0, L_0x126ef90; 1 drivers -v0x1085840_0 .net "B", 0 0, L_0x126ede0; 1 drivers -v0x1085910_0 .net "B_", 0 0, L_0x126f0f0; 1 drivers -v0x10859b0_0 .net *"_s12", 0 0, L_0x12707f0; 1 drivers -v0x1085aa0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05be8; 1 drivers -v0x1085b60_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05c30; 1 drivers -v0x1085c40_0 .net *"_s18", 0 0, L_0x12709f0; 1 drivers -v0x1085d20_0 .net *"_s20", 0 0, L_0x1270ab0; 1 drivers -v0x1085e90_0 .net *"_s22", 0 0, L_0x1270c10; 1 drivers -v0x1085f70_0 .net *"_s24", 0 0, L_0x12710c0; 1 drivers -o0x2b0ab3cbed38 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1086050_0 name=_s30 -o0x2b0ab3cbed68 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1086130_0 name=_s32 -v0x1086210_0 .net *"_s8", 0 0, L_0x1270140; 1 drivers -v0x10862f0_0 .net "carryin", 0 0, L_0x1278a90; 1 drivers -v0x1086390_0 .net "carryout", 0 0, L_0x12783b0; 1 drivers -v0x1086430_0 .net "carryouts", 7 0, L_0x1354090; 1 drivers -v0x10865e0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1086680_0 .net "result", 0 0, L_0x1274890; 1 drivers -v0x1086770_0 .net "results", 7 0, L_0x1270e90; 1 drivers -v0x1086880_0 .net "zero", 0 0, L_0x1278710; 1 drivers -LS_0x1270e90_0_0 .concat8 [ 1 1 1 1], L_0x126f610, L_0x126fc40, L_0x1270140, L_0x12707f0; -LS_0x1270e90_0_4 .concat8 [ 1 1 1 1], L_0x12709f0, L_0x1270ab0, L_0x1270c10, L_0x12710c0; -L_0x1270e90 .concat8 [ 4 4 0 0], LS_0x1270e90_0_0, LS_0x1270e90_0_4; -LS_0x1354090_0_0 .concat [ 1 1 1 1], L_0x126f8c0, L_0x126ffe0, o0x2b0ab3cbed38, L_0x1270640; -LS_0x1354090_0_4 .concat [ 4 0 0 0], o0x2b0ab3cbed68; -L_0x1354090 .concat [ 4 4 0 0], LS_0x1354090_0_0, LS_0x1354090_0_4; -S_0x1077250 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1076fd0; +L_0x2d53da0/d .functor NOT 1, L_0x2d5e260, C4<0>, C4<0>, C4<0>; +L_0x2d53da0 .delay 1 (10000,10000,10000) L_0x2d53da0/d; +L_0x2d53eb0/d .functor NOT 1, L_0x2d53c40, C4<0>, C4<0>, C4<0>; +L_0x2d53eb0 .delay 1 (10000,10000,10000) L_0x2d53eb0/d; +L_0x2d54eb0/d .functor XOR 1, L_0x2d5e260, L_0x2d53c40, C4<0>, C4<0>; +L_0x2d54eb0 .delay 1 (30000,30000,30000) L_0x2d54eb0/d; +L_0x2ac6110b8ad8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8b20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d54f70/d .functor OR 1, L_0x2ac6110b8ad8, L_0x2ac6110b8b20, C4<0>, C4<0>; +L_0x2d54f70 .delay 1 (30000,30000,30000) L_0x2d54f70/d; +L_0x2ac6110b8b68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8bb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d55710/d .functor OR 1, L_0x2ac6110b8b68, L_0x2ac6110b8bb0, C4<0>, C4<0>; +L_0x2d55710 .delay 1 (30000,30000,30000) L_0x2d55710/d; +L_0x2d55910/d .functor AND 1, L_0x2d5e260, L_0x2d53c40, C4<1>, C4<1>; +L_0x2d55910 .delay 1 (30000,30000,30000) L_0x2d55910/d; +L_0x2ac6110b8bf8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8c40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d559d0/d .functor OR 1, L_0x2ac6110b8bf8, L_0x2ac6110b8c40, C4<0>, C4<0>; +L_0x2d559d0 .delay 1 (30000,30000,30000) L_0x2d559d0/d; +L_0x2d55bd0/d .functor NAND 1, L_0x2d5e260, L_0x2d53c40, C4<1>, C4<1>; +L_0x2d55bd0 .delay 1 (20000,20000,20000) L_0x2d55bd0/d; +L_0x2ac6110b8c88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8cd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d55ce0/d .functor OR 1, L_0x2ac6110b8c88, L_0x2ac6110b8cd0, C4<0>, C4<0>; +L_0x2d55ce0 .delay 1 (30000,30000,30000) L_0x2d55ce0/d; +L_0x2d55e90/d .functor NOR 1, L_0x2d5e260, L_0x2d53c40, C4<0>, C4<0>; +L_0x2d55e90 .delay 1 (20000,20000,20000) L_0x2d55e90/d; +L_0x2ac6110b8d18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8d60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d56160/d .functor OR 1, L_0x2ac6110b8d18, L_0x2ac6110b8d60, C4<0>, C4<0>; +L_0x2d56160 .delay 1 (30000,30000,30000) L_0x2d56160/d; +L_0x2d56560/d .functor OR 1, L_0x2d5e260, L_0x2d53c40, C4<0>, C4<0>; +L_0x2d56560 .delay 1 (30000,30000,30000) L_0x2d56560/d; +L_0x2ac6110b8da8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8df0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d56a00/d .functor OR 1, L_0x2ac6110b8da8, L_0x2ac6110b8df0, C4<0>, C4<0>; +L_0x2d56a00 .delay 1 (30000,30000,30000) L_0x2d56a00/d; +L_0x2d5e160/d .functor NOT 1, L_0x2d5a3c0, C4<0>, C4<0>, C4<0>; +L_0x2d5e160 .delay 1 (10000,10000,10000) L_0x2d5e160/d; +v0x2b51330_0 .net "A", 0 0, L_0x2d5e260; 1 drivers +v0x2b513f0_0 .net "A_", 0 0, L_0x2d53da0; 1 drivers +v0x2b514b0_0 .net "B", 0 0, L_0x2d53c40; 1 drivers +v0x2b51580_0 .net "B_", 0 0, L_0x2d53eb0; 1 drivers +v0x2b51620_0 .net *"_s11", 0 0, L_0x2d54f70; 1 drivers +v0x2b51710_0 .net/2s *"_s13", 0 0, L_0x2ac6110b8ad8; 1 drivers +v0x2b517d0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b8b20; 1 drivers +v0x2b518b0_0 .net *"_s19", 0 0, L_0x2d55710; 1 drivers +v0x2b51990_0 .net/2s *"_s21", 0 0, L_0x2ac6110b8b68; 1 drivers +v0x2b51b00_0 .net/2s *"_s23", 0 0, L_0x2ac6110b8bb0; 1 drivers +v0x2b51be0_0 .net *"_s25", 0 0, L_0x2d55910; 1 drivers +v0x2b51cc0_0 .net *"_s28", 0 0, L_0x2d559d0; 1 drivers +v0x2b51da0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b8bf8; 1 drivers +v0x2b51e80_0 .net/2s *"_s32", 0 0, L_0x2ac6110b8c40; 1 drivers +v0x2b51f60_0 .net *"_s34", 0 0, L_0x2d55bd0; 1 drivers +v0x2b52040_0 .net *"_s37", 0 0, L_0x2d55ce0; 1 drivers +v0x2b52120_0 .net/2s *"_s39", 0 0, L_0x2ac6110b8c88; 1 drivers +v0x2b522d0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b8cd0; 1 drivers +v0x2b52370_0 .net *"_s43", 0 0, L_0x2d55e90; 1 drivers +v0x2b52450_0 .net *"_s46", 0 0, L_0x2d56160; 1 drivers +v0x2b52530_0 .net/2s *"_s48", 0 0, L_0x2ac6110b8d18; 1 drivers +v0x2b52610_0 .net/2s *"_s50", 0 0, L_0x2ac6110b8d60; 1 drivers +v0x2b526f0_0 .net *"_s52", 0 0, L_0x2d56560; 1 drivers +v0x2b527d0_0 .net *"_s56", 0 0, L_0x2d56a00; 1 drivers +v0x2b528b0_0 .net/2s *"_s59", 0 0, L_0x2ac6110b8da8; 1 drivers +v0x2b52990_0 .net/2s *"_s61", 0 0, L_0x2ac6110b8df0; 1 drivers +v0x2b52a70_0 .net *"_s8", 0 0, L_0x2d54eb0; 1 drivers +v0x2b52b50_0 .net "carryin", 0 0, L_0x2d5e4e0; 1 drivers +v0x2b52bf0_0 .net "carryout", 0 0, L_0x2d5de00; 1 drivers +v0x2b52c90_0 .net "carryouts", 7 0, L_0x2d56670; 1 drivers +v0x2b52da0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b52e60_0 .net "result", 0 0, L_0x2d5a3c0; 1 drivers +v0x2b52f50_0 .net "results", 7 0, L_0x2d56330; 1 drivers +v0x2b52230_0 .net "zero", 0 0, L_0x2d5e160; 1 drivers +LS_0x2d56330_0_0 .concat8 [ 1 1 1 1], L_0x2d543d0, L_0x2d54a00, L_0x2d54eb0, L_0x2d55710; +LS_0x2d56330_0_4 .concat8 [ 1 1 1 1], L_0x2d55910, L_0x2d55bd0, L_0x2d55e90, L_0x2d56560; +L_0x2d56330 .concat8 [ 4 4 0 0], LS_0x2d56330_0_0, LS_0x2d56330_0_4; +LS_0x2d56670_0_0 .concat8 [ 1 1 1 1], L_0x2d54680, L_0x2d54d50, L_0x2d54f70, L_0x2d55560; +LS_0x2d56670_0_4 .concat8 [ 1 1 1 1], L_0x2d559d0, L_0x2d55ce0, L_0x2d56160, L_0x2d56a00; +L_0x2d56670 .concat8 [ 4 4 0 0], LS_0x2d56670_0_0, LS_0x2d56670_0_4; +S_0x2b42e80 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b42c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x126f8c0/d .functor OR 1, L_0x126f3a0, L_0x126f760, C4<0>, C4<0>; -L_0x126f8c0 .delay 1 (30000,30000,30000) L_0x126f8c0/d; -v0x1078080_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers -v0x1078140_0 .net "b", 0 0, L_0x126ede0; alias, 1 drivers -v0x1078210_0 .net "c1", 0 0, L_0x126f3a0; 1 drivers -v0x1078310_0 .net "c2", 0 0, L_0x126f760; 1 drivers -v0x10783e0_0 .net "carryin", 0 0, L_0x1278a90; alias, 1 drivers -v0x10784d0_0 .net "carryout", 0 0, L_0x126f8c0; 1 drivers -v0x1078570_0 .net "s1", 0 0, L_0x126f2e0; 1 drivers -v0x1078660_0 .net "sum", 0 0, L_0x126f610; 1 drivers -S_0x10774c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1077250; +L_0x2d54680/d .functor OR 1, L_0x2d54160, L_0x2d54520, C4<0>, C4<0>; +L_0x2d54680 .delay 1 (30000,30000,30000) L_0x2d54680/d; +v0x2b43cb0_0 .net "a", 0 0, L_0x2d5e260; alias, 1 drivers +v0x2b43d70_0 .net "b", 0 0, L_0x2d53c40; alias, 1 drivers +v0x2b43e40_0 .net "c1", 0 0, L_0x2d54160; 1 drivers +v0x2b43f40_0 .net "c2", 0 0, L_0x2d54520; 1 drivers +v0x2b44010_0 .net "carryin", 0 0, L_0x2d5e4e0; alias, 1 drivers +v0x2b44100_0 .net "carryout", 0 0, L_0x2d54680; 1 drivers +v0x2b441a0_0 .net "s1", 0 0, L_0x2d540a0; 1 drivers +v0x2b44290_0 .net "sum", 0 0, L_0x2d543d0; 1 drivers +S_0x2b430f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b42e80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x126f2e0/d .functor XOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; -L_0x126f2e0 .delay 1 (30000,30000,30000) L_0x126f2e0/d; -L_0x126f3a0/d .functor AND 1, L_0x1278810, L_0x126ede0, C4<1>, C4<1>; -L_0x126f3a0 .delay 1 (30000,30000,30000) L_0x126f3a0/d; -v0x1077720_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers -v0x1077800_0 .net "b", 0 0, L_0x126ede0; alias, 1 drivers -v0x10778c0_0 .net "carryout", 0 0, L_0x126f3a0; alias, 1 drivers -v0x1077960_0 .net "sum", 0 0, L_0x126f2e0; alias, 1 drivers -S_0x1077aa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1077250; +L_0x2d540a0/d .functor XOR 1, L_0x2d5e260, L_0x2d53c40, C4<0>, C4<0>; +L_0x2d540a0 .delay 1 (30000,30000,30000) L_0x2d540a0/d; +L_0x2d54160/d .functor AND 1, L_0x2d5e260, L_0x2d53c40, C4<1>, C4<1>; +L_0x2d54160 .delay 1 (30000,30000,30000) L_0x2d54160/d; +v0x2b43350_0 .net "a", 0 0, L_0x2d5e260; alias, 1 drivers +v0x2b43430_0 .net "b", 0 0, L_0x2d53c40; alias, 1 drivers +v0x2b434f0_0 .net "carryout", 0 0, L_0x2d54160; alias, 1 drivers +v0x2b43590_0 .net "sum", 0 0, L_0x2d540a0; alias, 1 drivers +S_0x2b436d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b42e80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x126f610/d .functor XOR 1, L_0x126f2e0, L_0x1278a90, C4<0>, C4<0>; -L_0x126f610 .delay 1 (30000,30000,30000) L_0x126f610/d; -L_0x126f760/d .functor AND 1, L_0x126f2e0, L_0x1278a90, C4<1>, C4<1>; -L_0x126f760 .delay 1 (30000,30000,30000) L_0x126f760/d; -v0x1077d00_0 .net "a", 0 0, L_0x126f2e0; alias, 1 drivers -v0x1077da0_0 .net "b", 0 0, L_0x1278a90; alias, 1 drivers -v0x1077e40_0 .net "carryout", 0 0, L_0x126f760; alias, 1 drivers -v0x1077f10_0 .net "sum", 0 0, L_0x126f610; alias, 1 drivers -S_0x1078730 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1076fd0; +L_0x2d543d0/d .functor XOR 1, L_0x2d540a0, L_0x2d5e4e0, C4<0>, C4<0>; +L_0x2d543d0 .delay 1 (30000,30000,30000) L_0x2d543d0/d; +L_0x2d54520/d .functor AND 1, L_0x2d540a0, L_0x2d5e4e0, C4<1>, C4<1>; +L_0x2d54520 .delay 1 (30000,30000,30000) L_0x2d54520/d; +v0x2b43930_0 .net "a", 0 0, L_0x2d540a0; alias, 1 drivers +v0x2b439d0_0 .net "b", 0 0, L_0x2d5e4e0; alias, 1 drivers +v0x2b43a70_0 .net "carryout", 0 0, L_0x2d54520; alias, 1 drivers +v0x2b43b40_0 .net "sum", 0 0, L_0x2d543d0; alias, 1 drivers +S_0x2b44360 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b42c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x107db20_0 .net "ands", 7 0, L_0x12763b0; 1 drivers -v0x107dc30_0 .net "in", 7 0, L_0x1354090; alias, 1 drivers -v0x107dcf0_0 .net "out", 0 0, L_0x12783b0; alias, 1 drivers -v0x107ddc0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1078950 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1078730; +v0x2b49750_0 .net "ands", 7 0, L_0x2d5be00; 1 drivers +v0x2b49860_0 .net "in", 7 0, L_0x2d56670; alias, 1 drivers +v0x2b49920_0 .net "out", 0 0, L_0x2d5de00; alias, 1 drivers +v0x2b499f0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b44580 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b44360; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x107b080_0 .net "A", 7 0, L_0x1354090; alias, 1 drivers -v0x107b180_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x107b240_0 .net *"_s0", 0 0, L_0x1274bf0; 1 drivers -v0x107b300_0 .net *"_s12", 0 0, L_0x1275560; 1 drivers -v0x107b3e0_0 .net *"_s16", 0 0, L_0x12758c0; 1 drivers -v0x107b510_0 .net *"_s20", 0 0, L_0x1275c30; 1 drivers -v0x107b5f0_0 .net *"_s24", 0 0, L_0x1276020; 1 drivers -v0x107b6d0_0 .net *"_s28", 0 0, L_0x1275fb0; 1 drivers -v0x107b7b0_0 .net *"_s4", 0 0, L_0x1274f00; 1 drivers -v0x107b920_0 .net *"_s8", 0 0, L_0x1275250; 1 drivers -v0x107ba00_0 .net "out", 7 0, L_0x12763b0; alias, 1 drivers -L_0x1274cb0 .part L_0x1354090, 0, 1; -L_0x1274e10 .part v0x12010b0_0, 0, 1; -L_0x1274fc0 .part L_0x1354090, 1, 1; -L_0x12751b0 .part v0x12010b0_0, 1, 1; -L_0x1275310 .part L_0x1354090, 2, 1; -L_0x1275470 .part v0x12010b0_0, 2, 1; -L_0x1275620 .part L_0x1354090, 3, 1; -L_0x1275780 .part v0x12010b0_0, 3, 1; -L_0x1275980 .part L_0x1354090, 4, 1; -L_0x1275ae0 .part v0x12010b0_0, 4, 1; -L_0x1275ca0 .part L_0x1354090, 5, 1; -L_0x1275f10 .part v0x12010b0_0, 5, 1; -L_0x12760e0 .part L_0x1354090, 6, 1; -L_0x1276240 .part v0x12010b0_0, 6, 1; -LS_0x12763b0_0_0 .concat8 [ 1 1 1 1], L_0x1274bf0, L_0x1274f00, L_0x1275250, L_0x1275560; -LS_0x12763b0_0_4 .concat8 [ 1 1 1 1], L_0x12758c0, L_0x1275c30, L_0x1276020, L_0x1275fb0; -L_0x12763b0 .concat8 [ 4 4 0 0], LS_0x12763b0_0_0, LS_0x12763b0_0_4; -L_0x1276770 .part L_0x1354090, 7, 1; -L_0x1276960 .part v0x12010b0_0, 7, 1; -S_0x1078bb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x1078dc0 .param/l "i" 0 4 54, +C4<00>; -L_0x1274bf0/d .functor AND 1, L_0x1274cb0, L_0x1274e10, C4<1>, C4<1>; -L_0x1274bf0 .delay 1 (30000,30000,30000) L_0x1274bf0/d; -v0x1078ea0_0 .net *"_s0", 0 0, L_0x1274cb0; 1 drivers -v0x1078f80_0 .net *"_s1", 0 0, L_0x1274e10; 1 drivers -S_0x1079060 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x1079270 .param/l "i" 0 4 54, +C4<01>; -L_0x1274f00/d .functor AND 1, L_0x1274fc0, L_0x12751b0, C4<1>, C4<1>; -L_0x1274f00 .delay 1 (30000,30000,30000) L_0x1274f00/d; -v0x1079330_0 .net *"_s0", 0 0, L_0x1274fc0; 1 drivers -v0x1079410_0 .net *"_s1", 0 0, L_0x12751b0; 1 drivers -S_0x10794f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x1079700 .param/l "i" 0 4 54, +C4<010>; -L_0x1275250/d .functor AND 1, L_0x1275310, L_0x1275470, C4<1>, C4<1>; -L_0x1275250 .delay 1 (30000,30000,30000) L_0x1275250/d; -v0x10797a0_0 .net *"_s0", 0 0, L_0x1275310; 1 drivers -v0x1079880_0 .net *"_s1", 0 0, L_0x1275470; 1 drivers -S_0x1079960 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x1079b70 .param/l "i" 0 4 54, +C4<011>; -L_0x1275560/d .functor AND 1, L_0x1275620, L_0x1275780, C4<1>, C4<1>; -L_0x1275560 .delay 1 (30000,30000,30000) L_0x1275560/d; -v0x1079c30_0 .net *"_s0", 0 0, L_0x1275620; 1 drivers -v0x1079d10_0 .net *"_s1", 0 0, L_0x1275780; 1 drivers -S_0x1079df0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x107a050 .param/l "i" 0 4 54, +C4<0100>; -L_0x12758c0/d .functor AND 1, L_0x1275980, L_0x1275ae0, C4<1>, C4<1>; -L_0x12758c0 .delay 1 (30000,30000,30000) L_0x12758c0/d; -v0x107a110_0 .net *"_s0", 0 0, L_0x1275980; 1 drivers -v0x107a1f0_0 .net *"_s1", 0 0, L_0x1275ae0; 1 drivers -S_0x107a2d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x107a4e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1275c30/d .functor AND 1, L_0x1275ca0, L_0x1275f10, C4<1>, C4<1>; -L_0x1275c30 .delay 1 (30000,30000,30000) L_0x1275c30/d; -v0x107a5a0_0 .net *"_s0", 0 0, L_0x1275ca0; 1 drivers -v0x107a680_0 .net *"_s1", 0 0, L_0x1275f10; 1 drivers -S_0x107a760 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x107a970 .param/l "i" 0 4 54, +C4<0110>; -L_0x1276020/d .functor AND 1, L_0x12760e0, L_0x1276240, C4<1>, C4<1>; -L_0x1276020 .delay 1 (30000,30000,30000) L_0x1276020/d; -v0x107aa30_0 .net *"_s0", 0 0, L_0x12760e0; 1 drivers -v0x107ab10_0 .net *"_s1", 0 0, L_0x1276240; 1 drivers -S_0x107abf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1078950; - .timescale -9 -12; -P_0x107ae00 .param/l "i" 0 4 54, +C4<0111>; -L_0x1275fb0/d .functor AND 1, L_0x1276770, L_0x1276960, C4<1>, C4<1>; -L_0x1275fb0 .delay 1 (30000,30000,30000) L_0x1275fb0/d; -v0x107aec0_0 .net *"_s0", 0 0, L_0x1276770; 1 drivers -v0x107afa0_0 .net *"_s1", 0 0, L_0x1276960; 1 drivers -S_0x107bb60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1078730; +v0x2b46cb0_0 .net "A", 7 0, L_0x2d56670; alias, 1 drivers +v0x2b46db0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b46e70_0 .net *"_s0", 0 0, L_0x2d5a720; 1 drivers +v0x2b46f30_0 .net *"_s12", 0 0, L_0x2d5b090; 1 drivers +v0x2b47010_0 .net *"_s16", 0 0, L_0x2d5b3f0; 1 drivers +v0x2b47140_0 .net *"_s20", 0 0, L_0x2d5b7c0; 1 drivers +v0x2b47220_0 .net *"_s24", 0 0, L_0x2d5baf0; 1 drivers +v0x2b47300_0 .net *"_s28", 0 0, L_0x2d5ba80; 1 drivers +v0x2b473e0_0 .net *"_s4", 0 0, L_0x2d5aa70; 1 drivers +v0x2b47550_0 .net *"_s8", 0 0, L_0x2d5ad80; 1 drivers +v0x2b47630_0 .net "out", 7 0, L_0x2d5be00; alias, 1 drivers +L_0x2d5a7e0 .part L_0x2d56670, 0, 1; +L_0x2d5a9d0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d5ab30 .part L_0x2d56670, 1, 1; +L_0x2d5ac90 .part v0x2cdd2e0_0, 1, 1; +L_0x2d5ae40 .part L_0x2d56670, 2, 1; +L_0x2d5afa0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d5b150 .part L_0x2d56670, 3, 1; +L_0x2d5b2b0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d5b4b0 .part L_0x2d56670, 4, 1; +L_0x2d5b720 .part v0x2cdd2e0_0, 4, 1; +L_0x2d5b830 .part L_0x2d56670, 5, 1; +L_0x2d5b990 .part v0x2cdd2e0_0, 5, 1; +L_0x2d5bbb0 .part L_0x2d56670, 6, 1; +L_0x2d5bd10 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d5be00_0_0 .concat8 [ 1 1 1 1], L_0x2d5a720, L_0x2d5aa70, L_0x2d5ad80, L_0x2d5b090; +LS_0x2d5be00_0_4 .concat8 [ 1 1 1 1], L_0x2d5b3f0, L_0x2d5b7c0, L_0x2d5baf0, L_0x2d5ba80; +L_0x2d5be00 .concat8 [ 4 4 0 0], LS_0x2d5be00_0_0, LS_0x2d5be00_0_4; +L_0x2d5c1c0 .part L_0x2d56670, 7, 1; +L_0x2d5c3b0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b447e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b449f0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d5a720/d .functor AND 1, L_0x2d5a7e0, L_0x2d5a9d0, C4<1>, C4<1>; +L_0x2d5a720 .delay 1 (30000,30000,30000) L_0x2d5a720/d; +v0x2b44ad0_0 .net *"_s0", 0 0, L_0x2d5a7e0; 1 drivers +v0x2b44bb0_0 .net *"_s1", 0 0, L_0x2d5a9d0; 1 drivers +S_0x2b44c90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b44ea0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d5aa70/d .functor AND 1, L_0x2d5ab30, L_0x2d5ac90, C4<1>, C4<1>; +L_0x2d5aa70 .delay 1 (30000,30000,30000) L_0x2d5aa70/d; +v0x2b44f60_0 .net *"_s0", 0 0, L_0x2d5ab30; 1 drivers +v0x2b45040_0 .net *"_s1", 0 0, L_0x2d5ac90; 1 drivers +S_0x2b45120 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b45330 .param/l "i" 0 4 54, +C4<010>; +L_0x2d5ad80/d .functor AND 1, L_0x2d5ae40, L_0x2d5afa0, C4<1>, C4<1>; +L_0x2d5ad80 .delay 1 (30000,30000,30000) L_0x2d5ad80/d; +v0x2b453d0_0 .net *"_s0", 0 0, L_0x2d5ae40; 1 drivers +v0x2b454b0_0 .net *"_s1", 0 0, L_0x2d5afa0; 1 drivers +S_0x2b45590 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b457a0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d5b090/d .functor AND 1, L_0x2d5b150, L_0x2d5b2b0, C4<1>, C4<1>; +L_0x2d5b090 .delay 1 (30000,30000,30000) L_0x2d5b090/d; +v0x2b45860_0 .net *"_s0", 0 0, L_0x2d5b150; 1 drivers +v0x2b45940_0 .net *"_s1", 0 0, L_0x2d5b2b0; 1 drivers +S_0x2b45a20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b45c80 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d5b3f0/d .functor AND 1, L_0x2d5b4b0, L_0x2d5b720, C4<1>, C4<1>; +L_0x2d5b3f0 .delay 1 (30000,30000,30000) L_0x2d5b3f0/d; +v0x2b45d40_0 .net *"_s0", 0 0, L_0x2d5b4b0; 1 drivers +v0x2b45e20_0 .net *"_s1", 0 0, L_0x2d5b720; 1 drivers +S_0x2b45f00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b46110 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d5b7c0/d .functor AND 1, L_0x2d5b830, L_0x2d5b990, C4<1>, C4<1>; +L_0x2d5b7c0 .delay 1 (30000,30000,30000) L_0x2d5b7c0/d; +v0x2b461d0_0 .net *"_s0", 0 0, L_0x2d5b830; 1 drivers +v0x2b462b0_0 .net *"_s1", 0 0, L_0x2d5b990; 1 drivers +S_0x2b46390 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b465a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d5baf0/d .functor AND 1, L_0x2d5bbb0, L_0x2d5bd10, C4<1>, C4<1>; +L_0x2d5baf0 .delay 1 (30000,30000,30000) L_0x2d5baf0/d; +v0x2b46660_0 .net *"_s0", 0 0, L_0x2d5bbb0; 1 drivers +v0x2b46740_0 .net *"_s1", 0 0, L_0x2d5bd10; 1 drivers +S_0x2b46820 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b44580; + .timescale -9 -12; +P_0x2b46a30 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d5ba80/d .functor AND 1, L_0x2d5c1c0, L_0x2d5c3b0, C4<1>, C4<1>; +L_0x2d5ba80 .delay 1 (30000,30000,30000) L_0x2d5ba80/d; +v0x2b46af0_0 .net *"_s0", 0 0, L_0x2d5c1c0; 1 drivers +v0x2b46bd0_0 .net *"_s1", 0 0, L_0x2d5c3b0; 1 drivers +S_0x2b47790 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b44360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12783b0/d .functor OR 1, L_0x1278470, L_0x1278620, C4<0>, C4<0>; -L_0x12783b0 .delay 1 (30000,30000,30000) L_0x12783b0/d; -v0x107d6b0_0 .net *"_s10", 0 0, L_0x1278470; 1 drivers -v0x107d790_0 .net *"_s12", 0 0, L_0x1278620; 1 drivers -v0x107d870_0 .net "in", 7 0, L_0x12763b0; alias, 1 drivers -v0x107d940_0 .net "ors", 1 0, L_0x12781d0; 1 drivers -v0x107da00_0 .net "out", 0 0, L_0x12783b0; alias, 1 drivers -L_0x12775a0 .part L_0x12763b0, 0, 4; -L_0x12781d0 .concat8 [ 1 1 0 0], L_0x1277290, L_0x1277ec0; -L_0x1278310 .part L_0x12763b0, 4, 4; -L_0x1278470 .part L_0x12781d0, 0, 1; -L_0x1278620 .part L_0x12781d0, 1, 1; -S_0x107bd20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x107bb60; +L_0x2d5de00/d .functor OR 1, L_0x2d5dec0, L_0x2d5e070, C4<0>, C4<0>; +L_0x2d5de00 .delay 1 (30000,30000,30000) L_0x2d5de00/d; +v0x2b492e0_0 .net *"_s10", 0 0, L_0x2d5dec0; 1 drivers +v0x2b493c0_0 .net *"_s12", 0 0, L_0x2d5e070; 1 drivers +v0x2b494a0_0 .net "in", 7 0, L_0x2d5be00; alias, 1 drivers +v0x2b49570_0 .net "ors", 1 0, L_0x2d5dc20; 1 drivers +v0x2b49630_0 .net "out", 0 0, L_0x2d5de00; alias, 1 drivers +L_0x2d5cff0 .part L_0x2d5be00, 0, 4; +L_0x2d5dc20 .concat8 [ 1 1 0 0], L_0x2d5cce0, L_0x2d5d910; +L_0x2d5dd60 .part L_0x2d5be00, 4, 4; +L_0x2d5dec0 .part L_0x2d5dc20, 0, 1; +L_0x2d5e070 .part L_0x2d5dc20, 1, 1; +S_0x2b47950 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b47790; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1276a50/d .functor OR 1, L_0x1276b10, L_0x1276c70, C4<0>, C4<0>; -L_0x1276a50 .delay 1 (30000,30000,30000) L_0x1276a50/d; -L_0x1276ea0/d .functor OR 1, L_0x1276fb0, L_0x1277110, C4<0>, C4<0>; -L_0x1276ea0 .delay 1 (30000,30000,30000) L_0x1276ea0/d; -L_0x1277290/d .functor OR 1, L_0x1277300, L_0x12774b0, C4<0>, C4<0>; -L_0x1277290 .delay 1 (30000,30000,30000) L_0x1277290/d; -v0x107bf70_0 .net *"_s0", 0 0, L_0x1276a50; 1 drivers -v0x107c070_0 .net *"_s10", 0 0, L_0x1276fb0; 1 drivers -v0x107c150_0 .net *"_s12", 0 0, L_0x1277110; 1 drivers -v0x107c210_0 .net *"_s14", 0 0, L_0x1277300; 1 drivers -v0x107c2f0_0 .net *"_s16", 0 0, L_0x12774b0; 1 drivers -v0x107c420_0 .net *"_s3", 0 0, L_0x1276b10; 1 drivers -v0x107c500_0 .net *"_s5", 0 0, L_0x1276c70; 1 drivers -v0x107c5e0_0 .net *"_s6", 0 0, L_0x1276ea0; 1 drivers -v0x107c6c0_0 .net "in", 3 0, L_0x12775a0; 1 drivers -v0x107c830_0 .net "ors", 1 0, L_0x1276db0; 1 drivers -v0x107c910_0 .net "out", 0 0, L_0x1277290; 1 drivers -L_0x1276b10 .part L_0x12775a0, 0, 1; -L_0x1276c70 .part L_0x12775a0, 1, 1; -L_0x1276db0 .concat8 [ 1 1 0 0], L_0x1276a50, L_0x1276ea0; -L_0x1276fb0 .part L_0x12775a0, 2, 1; -L_0x1277110 .part L_0x12775a0, 3, 1; -L_0x1277300 .part L_0x1276db0, 0, 1; -L_0x12774b0 .part L_0x1276db0, 1, 1; -S_0x107ca30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x107bb60; +L_0x2d5c4a0/d .functor OR 1, L_0x2d5c560, L_0x2d5c6c0, C4<0>, C4<0>; +L_0x2d5c4a0 .delay 1 (30000,30000,30000) L_0x2d5c4a0/d; +L_0x2d5c8f0/d .functor OR 1, L_0x2d5ca00, L_0x2d5cb60, C4<0>, C4<0>; +L_0x2d5c8f0 .delay 1 (30000,30000,30000) L_0x2d5c8f0/d; +L_0x2d5cce0/d .functor OR 1, L_0x2d5cd50, L_0x2d5cf00, C4<0>, C4<0>; +L_0x2d5cce0 .delay 1 (30000,30000,30000) L_0x2d5cce0/d; +v0x2b47ba0_0 .net *"_s0", 0 0, L_0x2d5c4a0; 1 drivers +v0x2b47ca0_0 .net *"_s10", 0 0, L_0x2d5ca00; 1 drivers +v0x2b47d80_0 .net *"_s12", 0 0, L_0x2d5cb60; 1 drivers +v0x2b47e40_0 .net *"_s14", 0 0, L_0x2d5cd50; 1 drivers +v0x2b47f20_0 .net *"_s16", 0 0, L_0x2d5cf00; 1 drivers +v0x2b48050_0 .net *"_s3", 0 0, L_0x2d5c560; 1 drivers +v0x2b48130_0 .net *"_s5", 0 0, L_0x2d5c6c0; 1 drivers +v0x2b48210_0 .net *"_s6", 0 0, L_0x2d5c8f0; 1 drivers +v0x2b482f0_0 .net "in", 3 0, L_0x2d5cff0; 1 drivers +v0x2b48460_0 .net "ors", 1 0, L_0x2d5c800; 1 drivers +v0x2b48540_0 .net "out", 0 0, L_0x2d5cce0; 1 drivers +L_0x2d5c560 .part L_0x2d5cff0, 0, 1; +L_0x2d5c6c0 .part L_0x2d5cff0, 1, 1; +L_0x2d5c800 .concat8 [ 1 1 0 0], L_0x2d5c4a0, L_0x2d5c8f0; +L_0x2d5ca00 .part L_0x2d5cff0, 2, 1; +L_0x2d5cb60 .part L_0x2d5cff0, 3, 1; +L_0x2d5cd50 .part L_0x2d5c800, 0, 1; +L_0x2d5cf00 .part L_0x2d5c800, 1, 1; +S_0x2b48660 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b47790; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12776d0/d .functor OR 1, L_0x1277740, L_0x12778a0, C4<0>, C4<0>; -L_0x12776d0 .delay 1 (30000,30000,30000) L_0x12776d0/d; -L_0x1277ad0/d .functor OR 1, L_0x1277be0, L_0x1277d40, C4<0>, C4<0>; -L_0x1277ad0 .delay 1 (30000,30000,30000) L_0x1277ad0/d; -L_0x1277ec0/d .functor OR 1, L_0x1277f30, L_0x12780e0, C4<0>, C4<0>; -L_0x1277ec0 .delay 1 (30000,30000,30000) L_0x1277ec0/d; -v0x107cbf0_0 .net *"_s0", 0 0, L_0x12776d0; 1 drivers -v0x107ccf0_0 .net *"_s10", 0 0, L_0x1277be0; 1 drivers -v0x107cdd0_0 .net *"_s12", 0 0, L_0x1277d40; 1 drivers -v0x107ce90_0 .net *"_s14", 0 0, L_0x1277f30; 1 drivers -v0x107cf70_0 .net *"_s16", 0 0, L_0x12780e0; 1 drivers -v0x107d0a0_0 .net *"_s3", 0 0, L_0x1277740; 1 drivers -v0x107d180_0 .net *"_s5", 0 0, L_0x12778a0; 1 drivers -v0x107d260_0 .net *"_s6", 0 0, L_0x1277ad0; 1 drivers -v0x107d340_0 .net "in", 3 0, L_0x1278310; 1 drivers -v0x107d4b0_0 .net "ors", 1 0, L_0x12779e0; 1 drivers -v0x107d590_0 .net "out", 0 0, L_0x1277ec0; 1 drivers -L_0x1277740 .part L_0x1278310, 0, 1; -L_0x12778a0 .part L_0x1278310, 1, 1; -L_0x12779e0 .concat8 [ 1 1 0 0], L_0x12776d0, L_0x1277ad0; -L_0x1277be0 .part L_0x1278310, 2, 1; -L_0x1277d40 .part L_0x1278310, 3, 1; -L_0x1277f30 .part L_0x12779e0, 0, 1; -L_0x12780e0 .part L_0x12779e0, 1, 1; -S_0x107dea0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1076fd0; +L_0x2d5d120/d .functor OR 1, L_0x2d5d190, L_0x2d5d2f0, C4<0>, C4<0>; +L_0x2d5d120 .delay 1 (30000,30000,30000) L_0x2d5d120/d; +L_0x2d5d520/d .functor OR 1, L_0x2d5d630, L_0x2d5d790, C4<0>, C4<0>; +L_0x2d5d520 .delay 1 (30000,30000,30000) L_0x2d5d520/d; +L_0x2d5d910/d .functor OR 1, L_0x2d5d980, L_0x2d5db30, C4<0>, C4<0>; +L_0x2d5d910 .delay 1 (30000,30000,30000) L_0x2d5d910/d; +v0x2b48820_0 .net *"_s0", 0 0, L_0x2d5d120; 1 drivers +v0x2b48920_0 .net *"_s10", 0 0, L_0x2d5d630; 1 drivers +v0x2b48a00_0 .net *"_s12", 0 0, L_0x2d5d790; 1 drivers +v0x2b48ac0_0 .net *"_s14", 0 0, L_0x2d5d980; 1 drivers +v0x2b48ba0_0 .net *"_s16", 0 0, L_0x2d5db30; 1 drivers +v0x2b48cd0_0 .net *"_s3", 0 0, L_0x2d5d190; 1 drivers +v0x2b48db0_0 .net *"_s5", 0 0, L_0x2d5d2f0; 1 drivers +v0x2b48e90_0 .net *"_s6", 0 0, L_0x2d5d520; 1 drivers +v0x2b48f70_0 .net "in", 3 0, L_0x2d5dd60; 1 drivers +v0x2b490e0_0 .net "ors", 1 0, L_0x2d5d430; 1 drivers +v0x2b491c0_0 .net "out", 0 0, L_0x2d5d910; 1 drivers +L_0x2d5d190 .part L_0x2d5dd60, 0, 1; +L_0x2d5d2f0 .part L_0x2d5dd60, 1, 1; +L_0x2d5d430 .concat8 [ 1 1 0 0], L_0x2d5d120, L_0x2d5d520; +L_0x2d5d630 .part L_0x2d5dd60, 2, 1; +L_0x2d5d790 .part L_0x2d5dd60, 3, 1; +L_0x2d5d980 .part L_0x2d5d430, 0, 1; +L_0x2d5db30 .part L_0x2d5d430, 1, 1; +S_0x2b49ad0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b42c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10832d0_0 .net "ands", 7 0, L_0x1272950; 1 drivers -v0x10833e0_0 .net "in", 7 0, L_0x1270e90; alias, 1 drivers -v0x10834a0_0 .net "out", 0 0, L_0x1274890; alias, 1 drivers -v0x1083570_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x107e0f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x107dea0; +v0x2b4ef00_0 .net "ands", 7 0, L_0x2d583c0; 1 drivers +v0x2b4f010_0 .net "in", 7 0, L_0x2d56330; alias, 1 drivers +v0x2b4f0d0_0 .net "out", 0 0, L_0x2d5a3c0; alias, 1 drivers +v0x2b4f1a0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b49d20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b49ad0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1080830_0 .net "A", 7 0, L_0x1270e90; alias, 1 drivers -v0x1080930_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10809f0_0 .net *"_s0", 0 0, L_0x1271220; 1 drivers -v0x1080ab0_0 .net *"_s12", 0 0, L_0x1271be0; 1 drivers -v0x1080b90_0 .net *"_s16", 0 0, L_0x1271f40; 1 drivers -v0x1080cc0_0 .net *"_s20", 0 0, L_0x1272310; 1 drivers -v0x1080da0_0 .net *"_s24", 0 0, L_0x1272640; 1 drivers -v0x1080e80_0 .net *"_s28", 0 0, L_0x12725d0; 1 drivers -v0x1080f60_0 .net *"_s4", 0 0, L_0x12715c0; 1 drivers -v0x10810d0_0 .net *"_s8", 0 0, L_0x12718d0; 1 drivers -v0x10811b0_0 .net "out", 7 0, L_0x1272950; alias, 1 drivers -L_0x1271330 .part L_0x1270e90, 0, 1; -L_0x1271520 .part v0x12010b0_0, 0, 1; -L_0x1271680 .part L_0x1270e90, 1, 1; -L_0x12717e0 .part v0x12010b0_0, 1, 1; -L_0x1271990 .part L_0x1270e90, 2, 1; -L_0x1271af0 .part v0x12010b0_0, 2, 1; -L_0x1271ca0 .part L_0x1270e90, 3, 1; -L_0x1271e00 .part v0x12010b0_0, 3, 1; -L_0x1272000 .part L_0x1270e90, 4, 1; -L_0x1272270 .part v0x12010b0_0, 4, 1; -L_0x1272380 .part L_0x1270e90, 5, 1; -L_0x12724e0 .part v0x12010b0_0, 5, 1; -L_0x1272700 .part L_0x1270e90, 6, 1; -L_0x1272860 .part v0x12010b0_0, 6, 1; -LS_0x1272950_0_0 .concat8 [ 1 1 1 1], L_0x1271220, L_0x12715c0, L_0x12718d0, L_0x1271be0; -LS_0x1272950_0_4 .concat8 [ 1 1 1 1], L_0x1271f40, L_0x1272310, L_0x1272640, L_0x12725d0; -L_0x1272950 .concat8 [ 4 4 0 0], LS_0x1272950_0_0, LS_0x1272950_0_4; -L_0x1272d10 .part L_0x1270e90, 7, 1; -L_0x1272f00 .part v0x12010b0_0, 7, 1; -S_0x107e330 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x107e540 .param/l "i" 0 4 54, +C4<00>; -L_0x1271220/d .functor AND 1, L_0x1271330, L_0x1271520, C4<1>, C4<1>; -L_0x1271220 .delay 1 (30000,30000,30000) L_0x1271220/d; -v0x107e620_0 .net *"_s0", 0 0, L_0x1271330; 1 drivers -v0x107e700_0 .net *"_s1", 0 0, L_0x1271520; 1 drivers -S_0x107e7e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x107e9f0 .param/l "i" 0 4 54, +C4<01>; -L_0x12715c0/d .functor AND 1, L_0x1271680, L_0x12717e0, C4<1>, C4<1>; -L_0x12715c0 .delay 1 (30000,30000,30000) L_0x12715c0/d; -v0x107eab0_0 .net *"_s0", 0 0, L_0x1271680; 1 drivers -v0x107eb90_0 .net *"_s1", 0 0, L_0x12717e0; 1 drivers -S_0x107ec70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x107eeb0 .param/l "i" 0 4 54, +C4<010>; -L_0x12718d0/d .functor AND 1, L_0x1271990, L_0x1271af0, C4<1>, C4<1>; -L_0x12718d0 .delay 1 (30000,30000,30000) L_0x12718d0/d; -v0x107ef50_0 .net *"_s0", 0 0, L_0x1271990; 1 drivers -v0x107f030_0 .net *"_s1", 0 0, L_0x1271af0; 1 drivers -S_0x107f110 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x107f320 .param/l "i" 0 4 54, +C4<011>; -L_0x1271be0/d .functor AND 1, L_0x1271ca0, L_0x1271e00, C4<1>, C4<1>; -L_0x1271be0 .delay 1 (30000,30000,30000) L_0x1271be0/d; -v0x107f3e0_0 .net *"_s0", 0 0, L_0x1271ca0; 1 drivers -v0x107f4c0_0 .net *"_s1", 0 0, L_0x1271e00; 1 drivers -S_0x107f5a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x107f800 .param/l "i" 0 4 54, +C4<0100>; -L_0x1271f40/d .functor AND 1, L_0x1272000, L_0x1272270, C4<1>, C4<1>; -L_0x1271f40 .delay 1 (30000,30000,30000) L_0x1271f40/d; -v0x107f8c0_0 .net *"_s0", 0 0, L_0x1272000; 1 drivers -v0x107f9a0_0 .net *"_s1", 0 0, L_0x1272270; 1 drivers -S_0x107fa80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x107fc90 .param/l "i" 0 4 54, +C4<0101>; -L_0x1272310/d .functor AND 1, L_0x1272380, L_0x12724e0, C4<1>, C4<1>; -L_0x1272310 .delay 1 (30000,30000,30000) L_0x1272310/d; -v0x107fd50_0 .net *"_s0", 0 0, L_0x1272380; 1 drivers -v0x107fe30_0 .net *"_s1", 0 0, L_0x12724e0; 1 drivers -S_0x107ff10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x1080120 .param/l "i" 0 4 54, +C4<0110>; -L_0x1272640/d .functor AND 1, L_0x1272700, L_0x1272860, C4<1>, C4<1>; -L_0x1272640 .delay 1 (30000,30000,30000) L_0x1272640/d; -v0x10801e0_0 .net *"_s0", 0 0, L_0x1272700; 1 drivers -v0x10802c0_0 .net *"_s1", 0 0, L_0x1272860; 1 drivers -S_0x10803a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x107e0f0; - .timescale -9 -12; -P_0x10805b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x12725d0/d .functor AND 1, L_0x1272d10, L_0x1272f00, C4<1>, C4<1>; -L_0x12725d0 .delay 1 (30000,30000,30000) L_0x12725d0/d; -v0x1080670_0 .net *"_s0", 0 0, L_0x1272d10; 1 drivers -v0x1080750_0 .net *"_s1", 0 0, L_0x1272f00; 1 drivers -S_0x1081310 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x107dea0; +v0x2b4c460_0 .net "A", 7 0, L_0x2d56330; alias, 1 drivers +v0x2b4c560_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b4c620_0 .net *"_s0", 0 0, L_0x2d56bb0; 1 drivers +v0x2b4c6e0_0 .net *"_s12", 0 0, L_0x2d57570; 1 drivers +v0x2b4c7c0_0 .net *"_s16", 0 0, L_0x2d578d0; 1 drivers +v0x2b4c8f0_0 .net *"_s20", 0 0, L_0x2d57d00; 1 drivers +v0x2b4c9d0_0 .net *"_s24", 0 0, L_0x2d58030; 1 drivers +v0x2b4cab0_0 .net *"_s28", 0 0, L_0x2d57fc0; 1 drivers +v0x2b4cb90_0 .net *"_s4", 0 0, L_0x2d56f50; 1 drivers +v0x2b4cd00_0 .net *"_s8", 0 0, L_0x2d57260; 1 drivers +v0x2b4cde0_0 .net "out", 7 0, L_0x2d583c0; alias, 1 drivers +L_0x2d56cc0 .part L_0x2d56330, 0, 1; +L_0x2d56eb0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d57010 .part L_0x2d56330, 1, 1; +L_0x2d57170 .part v0x2cdd2e0_0, 1, 1; +L_0x2d57320 .part L_0x2d56330, 2, 1; +L_0x2d57480 .part v0x2cdd2e0_0, 2, 1; +L_0x2d57630 .part L_0x2d56330, 3, 1; +L_0x2d57790 .part v0x2cdd2e0_0, 3, 1; +L_0x2d57990 .part L_0x2d56330, 4, 1; +L_0x2d57c00 .part v0x2cdd2e0_0, 4, 1; +L_0x2d57d70 .part L_0x2d56330, 5, 1; +L_0x2d57ed0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d580f0 .part L_0x2d56330, 6, 1; +L_0x2d58250 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d583c0_0_0 .concat8 [ 1 1 1 1], L_0x2d56bb0, L_0x2d56f50, L_0x2d57260, L_0x2d57570; +LS_0x2d583c0_0_4 .concat8 [ 1 1 1 1], L_0x2d578d0, L_0x2d57d00, L_0x2d58030, L_0x2d57fc0; +L_0x2d583c0 .concat8 [ 4 4 0 0], LS_0x2d583c0_0_0, LS_0x2d583c0_0_4; +L_0x2d58780 .part L_0x2d56330, 7, 1; +L_0x2d58970 .part v0x2cdd2e0_0, 7, 1; +S_0x2b49f60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4a170 .param/l "i" 0 4 54, +C4<00>; +L_0x2d56bb0/d .functor AND 1, L_0x2d56cc0, L_0x2d56eb0, C4<1>, C4<1>; +L_0x2d56bb0 .delay 1 (30000,30000,30000) L_0x2d56bb0/d; +v0x2b4a250_0 .net *"_s0", 0 0, L_0x2d56cc0; 1 drivers +v0x2b4a330_0 .net *"_s1", 0 0, L_0x2d56eb0; 1 drivers +S_0x2b4a410 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4a620 .param/l "i" 0 4 54, +C4<01>; +L_0x2d56f50/d .functor AND 1, L_0x2d57010, L_0x2d57170, C4<1>, C4<1>; +L_0x2d56f50 .delay 1 (30000,30000,30000) L_0x2d56f50/d; +v0x2b4a6e0_0 .net *"_s0", 0 0, L_0x2d57010; 1 drivers +v0x2b4a7c0_0 .net *"_s1", 0 0, L_0x2d57170; 1 drivers +S_0x2b4a8a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4aae0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d57260/d .functor AND 1, L_0x2d57320, L_0x2d57480, C4<1>, C4<1>; +L_0x2d57260 .delay 1 (30000,30000,30000) L_0x2d57260/d; +v0x2b4ab80_0 .net *"_s0", 0 0, L_0x2d57320; 1 drivers +v0x2b4ac60_0 .net *"_s1", 0 0, L_0x2d57480; 1 drivers +S_0x2b4ad40 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4af50 .param/l "i" 0 4 54, +C4<011>; +L_0x2d57570/d .functor AND 1, L_0x2d57630, L_0x2d57790, C4<1>, C4<1>; +L_0x2d57570 .delay 1 (30000,30000,30000) L_0x2d57570/d; +v0x2b4b010_0 .net *"_s0", 0 0, L_0x2d57630; 1 drivers +v0x2b4b0f0_0 .net *"_s1", 0 0, L_0x2d57790; 1 drivers +S_0x2b4b1d0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4b430 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d578d0/d .functor AND 1, L_0x2d57990, L_0x2d57c00, C4<1>, C4<1>; +L_0x2d578d0 .delay 1 (30000,30000,30000) L_0x2d578d0/d; +v0x2b4b4f0_0 .net *"_s0", 0 0, L_0x2d57990; 1 drivers +v0x2b4b5d0_0 .net *"_s1", 0 0, L_0x2d57c00; 1 drivers +S_0x2b4b6b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4b8c0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d57d00/d .functor AND 1, L_0x2d57d70, L_0x2d57ed0, C4<1>, C4<1>; +L_0x2d57d00 .delay 1 (30000,30000,30000) L_0x2d57d00/d; +v0x2b4b980_0 .net *"_s0", 0 0, L_0x2d57d70; 1 drivers +v0x2b4ba60_0 .net *"_s1", 0 0, L_0x2d57ed0; 1 drivers +S_0x2b4bb40 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4bd50 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d58030/d .functor AND 1, L_0x2d580f0, L_0x2d58250, C4<1>, C4<1>; +L_0x2d58030 .delay 1 (30000,30000,30000) L_0x2d58030/d; +v0x2b4be10_0 .net *"_s0", 0 0, L_0x2d580f0; 1 drivers +v0x2b4bef0_0 .net *"_s1", 0 0, L_0x2d58250; 1 drivers +S_0x2b4bfd0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b49d20; + .timescale -9 -12; +P_0x2b4c1e0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d57fc0/d .functor AND 1, L_0x2d58780, L_0x2d58970, C4<1>, C4<1>; +L_0x2d57fc0 .delay 1 (30000,30000,30000) L_0x2d57fc0/d; +v0x2b4c2a0_0 .net *"_s0", 0 0, L_0x2d58780; 1 drivers +v0x2b4c380_0 .net *"_s1", 0 0, L_0x2d58970; 1 drivers +S_0x2b4cf40 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b49ad0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1274890/d .functor OR 1, L_0x1274950, L_0x1274b00, C4<0>, C4<0>; -L_0x1274890 .delay 1 (30000,30000,30000) L_0x1274890/d; -v0x1082e60_0 .net *"_s10", 0 0, L_0x1274950; 1 drivers -v0x1082f40_0 .net *"_s12", 0 0, L_0x1274b00; 1 drivers -v0x1083020_0 .net "in", 7 0, L_0x1272950; alias, 1 drivers -v0x10830f0_0 .net "ors", 1 0, L_0x12746b0; 1 drivers -v0x10831b0_0 .net "out", 0 0, L_0x1274890; alias, 1 drivers -L_0x1273a80 .part L_0x1272950, 0, 4; -L_0x12746b0 .concat8 [ 1 1 0 0], L_0x1273770, L_0x12743a0; -L_0x12747f0 .part L_0x1272950, 4, 4; -L_0x1274950 .part L_0x12746b0, 0, 1; -L_0x1274b00 .part L_0x12746b0, 1, 1; -S_0x10814d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1081310; +L_0x2d5a3c0/d .functor OR 1, L_0x2d5a480, L_0x2d5a630, C4<0>, C4<0>; +L_0x2d5a3c0 .delay 1 (30000,30000,30000) L_0x2d5a3c0/d; +v0x2b4ea90_0 .net *"_s10", 0 0, L_0x2d5a480; 1 drivers +v0x2b4eb70_0 .net *"_s12", 0 0, L_0x2d5a630; 1 drivers +v0x2b4ec50_0 .net "in", 7 0, L_0x2d583c0; alias, 1 drivers +v0x2b4ed20_0 .net "ors", 1 0, L_0x2d5a1e0; 1 drivers +v0x2b4ede0_0 .net "out", 0 0, L_0x2d5a3c0; alias, 1 drivers +L_0x2d595b0 .part L_0x2d583c0, 0, 4; +L_0x2d5a1e0 .concat8 [ 1 1 0 0], L_0x2d592a0, L_0x2d59ed0; +L_0x2d5a320 .part L_0x2d583c0, 4, 4; +L_0x2d5a480 .part L_0x2d5a1e0, 0, 1; +L_0x2d5a630 .part L_0x2d5a1e0, 1, 1; +S_0x2b4d100 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b4cf40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x125f070/d .functor OR 1, L_0x1272ff0, L_0x1273150, C4<0>, C4<0>; -L_0x125f070 .delay 1 (30000,30000,30000) L_0x125f070/d; -L_0x1273380/d .functor OR 1, L_0x1273490, L_0x12735f0, C4<0>, C4<0>; -L_0x1273380 .delay 1 (30000,30000,30000) L_0x1273380/d; -L_0x1273770/d .functor OR 1, L_0x12737e0, L_0x1273990, C4<0>, C4<0>; -L_0x1273770 .delay 1 (30000,30000,30000) L_0x1273770/d; -v0x1081720_0 .net *"_s0", 0 0, L_0x125f070; 1 drivers -v0x1081820_0 .net *"_s10", 0 0, L_0x1273490; 1 drivers -v0x1081900_0 .net *"_s12", 0 0, L_0x12735f0; 1 drivers -v0x10819c0_0 .net *"_s14", 0 0, L_0x12737e0; 1 drivers -v0x1081aa0_0 .net *"_s16", 0 0, L_0x1273990; 1 drivers -v0x1081bd0_0 .net *"_s3", 0 0, L_0x1272ff0; 1 drivers -v0x1081cb0_0 .net *"_s5", 0 0, L_0x1273150; 1 drivers -v0x1081d90_0 .net *"_s6", 0 0, L_0x1273380; 1 drivers -v0x1081e70_0 .net "in", 3 0, L_0x1273a80; 1 drivers -v0x1081fe0_0 .net "ors", 1 0, L_0x1273290; 1 drivers -v0x10820c0_0 .net "out", 0 0, L_0x1273770; 1 drivers -L_0x1272ff0 .part L_0x1273a80, 0, 1; -L_0x1273150 .part L_0x1273a80, 1, 1; -L_0x1273290 .concat8 [ 1 1 0 0], L_0x125f070, L_0x1273380; -L_0x1273490 .part L_0x1273a80, 2, 1; -L_0x12735f0 .part L_0x1273a80, 3, 1; -L_0x12737e0 .part L_0x1273290, 0, 1; -L_0x1273990 .part L_0x1273290, 1, 1; -S_0x10821e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1081310; +L_0x2d58a60/d .functor OR 1, L_0x2d58b20, L_0x2d58c80, C4<0>, C4<0>; +L_0x2d58a60 .delay 1 (30000,30000,30000) L_0x2d58a60/d; +L_0x2d58eb0/d .functor OR 1, L_0x2d58fc0, L_0x2d59120, C4<0>, C4<0>; +L_0x2d58eb0 .delay 1 (30000,30000,30000) L_0x2d58eb0/d; +L_0x2d592a0/d .functor OR 1, L_0x2d59310, L_0x2d594c0, C4<0>, C4<0>; +L_0x2d592a0 .delay 1 (30000,30000,30000) L_0x2d592a0/d; +v0x2b4d350_0 .net *"_s0", 0 0, L_0x2d58a60; 1 drivers +v0x2b4d450_0 .net *"_s10", 0 0, L_0x2d58fc0; 1 drivers +v0x2b4d530_0 .net *"_s12", 0 0, L_0x2d59120; 1 drivers +v0x2b4d5f0_0 .net *"_s14", 0 0, L_0x2d59310; 1 drivers +v0x2b4d6d0_0 .net *"_s16", 0 0, L_0x2d594c0; 1 drivers +v0x2b4d800_0 .net *"_s3", 0 0, L_0x2d58b20; 1 drivers +v0x2b4d8e0_0 .net *"_s5", 0 0, L_0x2d58c80; 1 drivers +v0x2b4d9c0_0 .net *"_s6", 0 0, L_0x2d58eb0; 1 drivers +v0x2b4daa0_0 .net "in", 3 0, L_0x2d595b0; 1 drivers +v0x2b4dc10_0 .net "ors", 1 0, L_0x2d58dc0; 1 drivers +v0x2b4dcf0_0 .net "out", 0 0, L_0x2d592a0; 1 drivers +L_0x2d58b20 .part L_0x2d595b0, 0, 1; +L_0x2d58c80 .part L_0x2d595b0, 1, 1; +L_0x2d58dc0 .concat8 [ 1 1 0 0], L_0x2d58a60, L_0x2d58eb0; +L_0x2d58fc0 .part L_0x2d595b0, 2, 1; +L_0x2d59120 .part L_0x2d595b0, 3, 1; +L_0x2d59310 .part L_0x2d58dc0, 0, 1; +L_0x2d594c0 .part L_0x2d58dc0, 1, 1; +S_0x2b4de10 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b4cf40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1273bb0/d .functor OR 1, L_0x1273c20, L_0x1273d80, C4<0>, C4<0>; -L_0x1273bb0 .delay 1 (30000,30000,30000) L_0x1273bb0/d; -L_0x1273fb0/d .functor OR 1, L_0x12740c0, L_0x1274220, C4<0>, C4<0>; -L_0x1273fb0 .delay 1 (30000,30000,30000) L_0x1273fb0/d; -L_0x12743a0/d .functor OR 1, L_0x1274410, L_0x12745c0, C4<0>, C4<0>; -L_0x12743a0 .delay 1 (30000,30000,30000) L_0x12743a0/d; -v0x10823a0_0 .net *"_s0", 0 0, L_0x1273bb0; 1 drivers -v0x10824a0_0 .net *"_s10", 0 0, L_0x12740c0; 1 drivers -v0x1082580_0 .net *"_s12", 0 0, L_0x1274220; 1 drivers -v0x1082640_0 .net *"_s14", 0 0, L_0x1274410; 1 drivers -v0x1082720_0 .net *"_s16", 0 0, L_0x12745c0; 1 drivers -v0x1082850_0 .net *"_s3", 0 0, L_0x1273c20; 1 drivers -v0x1082930_0 .net *"_s5", 0 0, L_0x1273d80; 1 drivers -v0x1082a10_0 .net *"_s6", 0 0, L_0x1273fb0; 1 drivers -v0x1082af0_0 .net "in", 3 0, L_0x12747f0; 1 drivers -v0x1082c60_0 .net "ors", 1 0, L_0x1273ec0; 1 drivers -v0x1082d40_0 .net "out", 0 0, L_0x12743a0; 1 drivers -L_0x1273c20 .part L_0x12747f0, 0, 1; -L_0x1273d80 .part L_0x12747f0, 1, 1; -L_0x1273ec0 .concat8 [ 1 1 0 0], L_0x1273bb0, L_0x1273fb0; -L_0x12740c0 .part L_0x12747f0, 2, 1; -L_0x1274220 .part L_0x12747f0, 3, 1; -L_0x1274410 .part L_0x1273ec0, 0, 1; -L_0x12745c0 .part L_0x1273ec0, 1, 1; -S_0x1083650 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1076fd0; +L_0x2d596e0/d .functor OR 1, L_0x2d59750, L_0x2d598b0, C4<0>, C4<0>; +L_0x2d596e0 .delay 1 (30000,30000,30000) L_0x2d596e0/d; +L_0x2d59ae0/d .functor OR 1, L_0x2d59bf0, L_0x2d59d50, C4<0>, C4<0>; +L_0x2d59ae0 .delay 1 (30000,30000,30000) L_0x2d59ae0/d; +L_0x2d59ed0/d .functor OR 1, L_0x2d59f40, L_0x2d5a0f0, C4<0>, C4<0>; +L_0x2d59ed0 .delay 1 (30000,30000,30000) L_0x2d59ed0/d; +v0x2b4dfd0_0 .net *"_s0", 0 0, L_0x2d596e0; 1 drivers +v0x2b4e0d0_0 .net *"_s10", 0 0, L_0x2d59bf0; 1 drivers +v0x2b4e1b0_0 .net *"_s12", 0 0, L_0x2d59d50; 1 drivers +v0x2b4e270_0 .net *"_s14", 0 0, L_0x2d59f40; 1 drivers +v0x2b4e350_0 .net *"_s16", 0 0, L_0x2d5a0f0; 1 drivers +v0x2b4e480_0 .net *"_s3", 0 0, L_0x2d59750; 1 drivers +v0x2b4e560_0 .net *"_s5", 0 0, L_0x2d598b0; 1 drivers +v0x2b4e640_0 .net *"_s6", 0 0, L_0x2d59ae0; 1 drivers +v0x2b4e720_0 .net "in", 3 0, L_0x2d5a320; 1 drivers +v0x2b4e890_0 .net "ors", 1 0, L_0x2d599f0; 1 drivers +v0x2b4e970_0 .net "out", 0 0, L_0x2d59ed0; 1 drivers +L_0x2d59750 .part L_0x2d5a320, 0, 1; +L_0x2d598b0 .part L_0x2d5a320, 1, 1; +L_0x2d599f0 .concat8 [ 1 1 0 0], L_0x2d596e0, L_0x2d59ae0; +L_0x2d59bf0 .part L_0x2d5a320, 2, 1; +L_0x2d59d50 .part L_0x2d5a320, 3, 1; +L_0x2d59f40 .part L_0x2d599f0, 0, 1; +L_0x2d5a0f0 .part L_0x2d599f0, 1, 1; +S_0x2b4f280 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b42c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -6518,80 +6892,80 @@ S_0x1083650 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1076fd0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1270200/d .functor XNOR 1, L_0x1278810, L_0x126ede0, C4<0>, C4<0>; -L_0x1270200 .delay 1 (20000,20000,20000) L_0x1270200/d; -L_0x1270470/d .functor AND 1, L_0x1278810, L_0x126f0f0, C4<1>, C4<1>; -L_0x1270470 .delay 1 (30000,30000,30000) L_0x1270470/d; -L_0x12704e0/d .functor AND 1, L_0x1270200, L_0x1278a90, C4<1>, C4<1>; -L_0x12704e0 .delay 1 (30000,30000,30000) L_0x12704e0/d; -L_0x1270640/d .functor OR 1, L_0x12704e0, L_0x1270470, C4<0>, C4<0>; -L_0x1270640 .delay 1 (30000,30000,30000) L_0x1270640/d; -v0x1083900_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers -v0x10839f0_0 .net "a_", 0 0, L_0x126ef90; alias, 1 drivers -v0x1083ab0_0 .net "b", 0 0, L_0x126ede0; alias, 1 drivers -v0x1083ba0_0 .net "b_", 0 0, L_0x126f0f0; alias, 1 drivers -v0x1083c40_0 .net "carryin", 0 0, L_0x1278a90; alias, 1 drivers -v0x1083d80_0 .net "eq", 0 0, L_0x1270200; 1 drivers -v0x1083e40_0 .net "lt", 0 0, L_0x1270470; 1 drivers -v0x1083f00_0 .net "out", 0 0, L_0x1270640; 1 drivers -v0x1083fc0_0 .net "w0", 0 0, L_0x12704e0; 1 drivers -S_0x1084210 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1076fd0; +L_0x2d55170/d .functor XNOR 1, L_0x2d5e260, L_0x2d53c40, C4<0>, C4<0>; +L_0x2d55170 .delay 1 (20000,20000,20000) L_0x2d55170/d; +L_0x2d552f0/d .functor AND 1, L_0x2d5e260, L_0x2d53eb0, C4<1>, C4<1>; +L_0x2d552f0 .delay 1 (30000,30000,30000) L_0x2d552f0/d; +L_0x2d55450/d .functor AND 1, L_0x2d55170, L_0x2d5e4e0, C4<1>, C4<1>; +L_0x2d55450 .delay 1 (30000,30000,30000) L_0x2d55450/d; +L_0x2d55560/d .functor OR 1, L_0x2d55450, L_0x2d552f0, C4<0>, C4<0>; +L_0x2d55560 .delay 1 (30000,30000,30000) L_0x2d55560/d; +v0x2b4f530_0 .net "a", 0 0, L_0x2d5e260; alias, 1 drivers +v0x2b4f620_0 .net "a_", 0 0, L_0x2d53da0; alias, 1 drivers +v0x2b4f6e0_0 .net "b", 0 0, L_0x2d53c40; alias, 1 drivers +v0x2b4f7d0_0 .net "b_", 0 0, L_0x2d53eb0; alias, 1 drivers +v0x2b4f870_0 .net "carryin", 0 0, L_0x2d5e4e0; alias, 1 drivers +v0x2b4f9b0_0 .net "eq", 0 0, L_0x2d55170; 1 drivers +v0x2b4fa70_0 .net "lt", 0 0, L_0x2d552f0; 1 drivers +v0x2b4fb30_0 .net "out", 0 0, L_0x2d55560; 1 drivers +v0x2b4fbf0_0 .net "w0", 0 0, L_0x2d55450; 1 drivers +S_0x2b4fe40 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b42c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x126ffe0/d .functor OR 1, L_0x126fae0, L_0x1085410, C4<0>, C4<0>; -L_0x126ffe0 .delay 1 (30000,30000,30000) L_0x126ffe0/d; -v0x1084fe0_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers -v0x1085110_0 .net "b", 0 0, L_0x126f0f0; alias, 1 drivers -v0x10851b0_0 .net "c1", 0 0, L_0x126fae0; 1 drivers -v0x1085250_0 .net "c2", 0 0, L_0x1085410; 1 drivers -v0x1085320_0 .net "carryin", 0 0, L_0x1278a90; alias, 1 drivers -v0x10854a0_0 .net "carryout", 0 0, L_0x126ffe0; 1 drivers -v0x1085540_0 .net "s1", 0 0, L_0x126fa20; 1 drivers -v0x10855e0_0 .net "sum", 0 0, L_0x126fc40; 1 drivers -S_0x1084460 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1084210; +L_0x2d54d50/d .functor OR 1, L_0x2d548a0, L_0x2b510a0, C4<0>, C4<0>; +L_0x2d54d50 .delay 1 (30000,30000,30000) L_0x2d54d50/d; +v0x2b50c30_0 .net "a", 0 0, L_0x2d5e260; alias, 1 drivers +v0x2b50d80_0 .net "b", 0 0, L_0x2d53eb0; alias, 1 drivers +v0x2b50e40_0 .net "c1", 0 0, L_0x2d548a0; 1 drivers +v0x2b50ee0_0 .net "c2", 0 0, L_0x2b510a0; 1 drivers +v0x2b50fb0_0 .net "carryin", 0 0, L_0x2d5e4e0; alias, 1 drivers +v0x2b51130_0 .net "carryout", 0 0, L_0x2d54d50; 1 drivers +v0x2b511d0_0 .net "s1", 0 0, L_0x2d547e0; 1 drivers +v0x2b51270_0 .net "sum", 0 0, L_0x2d54a00; 1 drivers +S_0x2b50090 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b4fe40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x126fa20/d .functor XOR 1, L_0x1278810, L_0x126f0f0, C4<0>, C4<0>; -L_0x126fa20 .delay 1 (30000,30000,30000) L_0x126fa20/d; -L_0x126fae0/d .functor AND 1, L_0x1278810, L_0x126f0f0, C4<1>, C4<1>; -L_0x126fae0 .delay 1 (30000,30000,30000) L_0x126fae0/d; -v0x10846c0_0 .net "a", 0 0, L_0x1278810; alias, 1 drivers -v0x1084780_0 .net "b", 0 0, L_0x126f0f0; alias, 1 drivers -v0x1084840_0 .net "carryout", 0 0, L_0x126fae0; alias, 1 drivers -v0x10848e0_0 .net "sum", 0 0, L_0x126fa20; alias, 1 drivers -S_0x1084a10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1084210; +L_0x2d547e0/d .functor XOR 1, L_0x2d5e260, L_0x2d53eb0, C4<0>, C4<0>; +L_0x2d547e0 .delay 1 (30000,30000,30000) L_0x2d547e0/d; +L_0x2d548a0/d .functor AND 1, L_0x2d5e260, L_0x2d53eb0, C4<1>, C4<1>; +L_0x2d548a0 .delay 1 (30000,30000,30000) L_0x2d548a0/d; +v0x2b502f0_0 .net "a", 0 0, L_0x2d5e260; alias, 1 drivers +v0x2b503b0_0 .net "b", 0 0, L_0x2d53eb0; alias, 1 drivers +v0x2b50470_0 .net "carryout", 0 0, L_0x2d548a0; alias, 1 drivers +v0x2b50510_0 .net "sum", 0 0, L_0x2d547e0; alias, 1 drivers +S_0x2b50640 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b4fe40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x126fc40/d .functor XOR 1, L_0x126fa20, L_0x1278a90, C4<0>, C4<0>; -L_0x126fc40 .delay 1 (30000,30000,30000) L_0x126fc40/d; -L_0x1085410/d .functor AND 1, L_0x126fa20, L_0x1278a90, C4<1>, C4<1>; -L_0x1085410 .delay 1 (30000,30000,30000) L_0x1085410/d; -v0x1084c70_0 .net "a", 0 0, L_0x126fa20; alias, 1 drivers -v0x1084d40_0 .net "b", 0 0, L_0x1278a90; alias, 1 drivers -v0x1084de0_0 .net "carryout", 0 0, L_0x1085410; alias, 1 drivers -v0x1084eb0_0 .net "sum", 0 0, L_0x126fc40; alias, 1 drivers -S_0x1086a60 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1076d00; - .timescale -9 -12; -L_0x2b0ab3d05c78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05cc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12788b0/d .functor OR 1, L_0x2b0ab3d05c78, L_0x2b0ab3d05cc0, C4<0>, C4<0>; -L_0x12788b0 .delay 1 (30000,30000,30000) L_0x12788b0/d; -v0x1086c50_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05c78; 1 drivers -v0x1086d30_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05cc0; 1 drivers -S_0x1086e10 .scope generate, "alu_slices[12]" "alu_slices[12]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1087020 .param/l "i" 0 3 41, +C4<01100>; -S_0x10870e0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1086e10; +L_0x2d54a00/d .functor XOR 1, L_0x2d547e0, L_0x2d5e4e0, C4<0>, C4<0>; +L_0x2d54a00 .delay 1 (30000,30000,30000) L_0x2d54a00/d; +L_0x2b510a0/d .functor AND 1, L_0x2d547e0, L_0x2d5e4e0, C4<1>, C4<1>; +L_0x2b510a0 .delay 1 (30000,30000,30000) L_0x2b510a0/d; +v0x2b508a0_0 .net "a", 0 0, L_0x2d547e0; alias, 1 drivers +v0x2b50970_0 .net "b", 0 0, L_0x2d5e4e0; alias, 1 drivers +v0x2b50a10_0 .net "carryout", 0 0, L_0x2b510a0; alias, 1 drivers +v0x2b50ae0_0 .net "sum", 0 0, L_0x2d54a00; alias, 1 drivers +S_0x2b53300 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b42930; + .timescale -9 -12; +L_0x2ac6110b8e38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8e80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d54360/d .functor OR 1, L_0x2ac6110b8e38, L_0x2ac6110b8e80, C4<0>, C4<0>; +L_0x2d54360 .delay 1 (30000,30000,30000) L_0x2d54360/d; +v0x2b534f0_0 .net/2u *"_s0", 0 0, L_0x2ac6110b8e38; 1 drivers +v0x2b535d0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b8e80; 1 drivers +S_0x2b536b0 .scope generate, "alu_slices[12]" "alu_slices[12]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b538c0 .param/l "i" 0 3 39, +C4<01100>; +S_0x2b53980 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b536b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -6600,445 +6974,476 @@ S_0x10870e0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1086e10; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1278a10/d .functor NOT 1, L_0x1282420, C4<0>, C4<0>, C4<0>; -L_0x1278a10 .delay 1 (10000,10000,10000) L_0x1278a10/d; -L_0x1278d50/d .functor NOT 1, L_0x1282580, C4<0>, C4<0>, C4<0>; -L_0x1278d50 .delay 1 (10000,10000,10000) L_0x1278d50/d; -L_0x1279c90/d .functor XOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; -L_0x1279c90 .delay 1 (30000,30000,30000) L_0x1279c90/d; -L_0x2b0ab3d05d08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05d50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x127a340/d .functor OR 1, L_0x2b0ab3d05d08, L_0x2b0ab3d05d50, C4<0>, C4<0>; -L_0x127a340 .delay 1 (30000,30000,30000) L_0x127a340/d; -L_0x127a540/d .functor AND 1, L_0x1282420, L_0x1282580, C4<1>, C4<1>; -L_0x127a540 .delay 1 (30000,30000,30000) L_0x127a540/d; -L_0x127a600/d .functor NAND 1, L_0x1282420, L_0x1282580, C4<1>, C4<1>; -L_0x127a600 .delay 1 (20000,20000,20000) L_0x127a600/d; -L_0x127a760/d .functor XOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; -L_0x127a760 .delay 1 (20000,20000,20000) L_0x127a760/d; -L_0x127ac10/d .functor OR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; -L_0x127ac10 .delay 1 (30000,30000,30000) L_0x127ac10/d; -L_0x1282320/d .functor NOT 1, L_0x127e580, C4<0>, C4<0>, C4<0>; -L_0x1282320 .delay 1 (10000,10000,10000) L_0x1282320/d; -v0x1095810_0 .net "A", 0 0, L_0x1282420; 1 drivers -v0x10958d0_0 .net "A_", 0 0, L_0x1278a10; 1 drivers -v0x1095990_0 .net "B", 0 0, L_0x1282580; 1 drivers -v0x1095a60_0 .net "B_", 0 0, L_0x1278d50; 1 drivers -v0x1095b00_0 .net *"_s12", 0 0, L_0x127a340; 1 drivers -v0x1095bf0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05d08; 1 drivers -v0x1095cb0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05d50; 1 drivers -v0x1095d90_0 .net *"_s18", 0 0, L_0x127a540; 1 drivers -v0x1095e70_0 .net *"_s20", 0 0, L_0x127a600; 1 drivers -v0x1095fe0_0 .net *"_s22", 0 0, L_0x127a760; 1 drivers -v0x10960c0_0 .net *"_s24", 0 0, L_0x127ac10; 1 drivers -o0x2b0ab3cc1288 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10961a0_0 name=_s30 -o0x2b0ab3cc12b8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1096280_0 name=_s32 -v0x1096360_0 .net *"_s8", 0 0, L_0x1279c90; 1 drivers -v0x1096440_0 .net "carryin", 0 0, L_0x1278b30; 1 drivers -v0x10964e0_0 .net "carryout", 0 0, L_0x1281fc0; 1 drivers -v0x1096580_0 .net "carryouts", 7 0, L_0x1354220; 1 drivers -v0x1096730_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1030260_0 .net "result", 0 0, L_0x127e580; 1 drivers -v0x1030350_0 .net "results", 7 0, L_0x127a9e0; 1 drivers -v0x1030460_0 .net "zero", 0 0, L_0x1282320; 1 drivers -LS_0x127a9e0_0_0 .concat8 [ 1 1 1 1], L_0x12791b0, L_0x12797e0, L_0x1279c90, L_0x127a340; -LS_0x127a9e0_0_4 .concat8 [ 1 1 1 1], L_0x127a540, L_0x127a600, L_0x127a760, L_0x127ac10; -L_0x127a9e0 .concat8 [ 4 4 0 0], LS_0x127a9e0_0_0, LS_0x127a9e0_0_4; -LS_0x1354220_0_0 .concat [ 1 1 1 1], L_0x1279460, L_0x1279b30, o0x2b0ab3cc1288, L_0x127a190; -LS_0x1354220_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc12b8; -L_0x1354220 .concat [ 4 4 0 0], LS_0x1354220_0_0, LS_0x1354220_0_4; -S_0x1087360 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10870e0; +L_0x2d5e460/d .functor NOT 1, L_0x2d68ad0, C4<0>, C4<0>, C4<0>; +L_0x2d5e460 .delay 1 (10000,10000,10000) L_0x2d5e460/d; +L_0x2d5e750/d .functor NOT 1, L_0x2d68c30, C4<0>, C4<0>, C4<0>; +L_0x2d5e750 .delay 1 (10000,10000,10000) L_0x2d5e750/d; +L_0x2d5f7a0/d .functor XOR 1, L_0x2d68ad0, L_0x2d68c30, C4<0>, C4<0>; +L_0x2d5f7a0 .delay 1 (30000,30000,30000) L_0x2d5f7a0/d; +L_0x2ac6110b8ec8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8f10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d5f860/d .functor OR 1, L_0x2ac6110b8ec8, L_0x2ac6110b8f10, C4<0>, C4<0>; +L_0x2d5f860 .delay 1 (30000,30000,30000) L_0x2d5f860/d; +L_0x2ac6110b8f58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b8fa0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d60000/d .functor OR 1, L_0x2ac6110b8f58, L_0x2ac6110b8fa0, C4<0>, C4<0>; +L_0x2d60000 .delay 1 (30000,30000,30000) L_0x2d60000/d; +L_0x2d60200/d .functor AND 1, L_0x2d68ad0, L_0x2d68c30, C4<1>, C4<1>; +L_0x2d60200 .delay 1 (30000,30000,30000) L_0x2d60200/d; +L_0x2ac6110b8fe8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9030 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d602c0/d .functor OR 1, L_0x2ac6110b8fe8, L_0x2ac6110b9030, C4<0>, C4<0>; +L_0x2d602c0 .delay 1 (30000,30000,30000) L_0x2d602c0/d; +L_0x2d604c0/d .functor NAND 1, L_0x2d68ad0, L_0x2d68c30, C4<1>, C4<1>; +L_0x2d604c0 .delay 1 (20000,20000,20000) L_0x2d604c0/d; +L_0x2ac6110b9078 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b90c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d605d0/d .functor OR 1, L_0x2ac6110b9078, L_0x2ac6110b90c0, C4<0>, C4<0>; +L_0x2d605d0 .delay 1 (30000,30000,30000) L_0x2d605d0/d; +L_0x2d60780/d .functor NOR 1, L_0x2d68ad0, L_0x2d68c30, C4<0>, C4<0>; +L_0x2d60780 .delay 1 (20000,20000,20000) L_0x2d60780/d; +L_0x2ac6110b9108 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9150 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d5ec00/d .functor OR 1, L_0x2ac6110b9108, L_0x2ac6110b9150, C4<0>, C4<0>; +L_0x2d5ec00 .delay 1 (30000,30000,30000) L_0x2d5ec00/d; +L_0x2d60de0/d .functor OR 1, L_0x2d68ad0, L_0x2d68c30, C4<0>, C4<0>; +L_0x2d60de0 .delay 1 (30000,30000,30000) L_0x2d60de0/d; +L_0x2ac6110b9198 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b91e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d612d0/d .functor OR 1, L_0x2ac6110b9198, L_0x2ac6110b91e0, C4<0>, C4<0>; +L_0x2d612d0 .delay 1 (30000,30000,30000) L_0x2d612d0/d; +L_0x2d689d0/d .functor NOT 1, L_0x2d64c30, C4<0>, C4<0>, C4<0>; +L_0x2d689d0 .delay 1 (10000,10000,10000) L_0x2d689d0/d; +v0x2b620c0_0 .net "A", 0 0, L_0x2d68ad0; 1 drivers +v0x2b62180_0 .net "A_", 0 0, L_0x2d5e460; 1 drivers +v0x2b62240_0 .net "B", 0 0, L_0x2d68c30; 1 drivers +v0x2b62310_0 .net "B_", 0 0, L_0x2d5e750; 1 drivers +v0x2b623b0_0 .net *"_s11", 0 0, L_0x2d5f860; 1 drivers +v0x2b624a0_0 .net/2s *"_s13", 0 0, L_0x2ac6110b8ec8; 1 drivers +v0x2b62560_0 .net/2s *"_s15", 0 0, L_0x2ac6110b8f10; 1 drivers +v0x2b62640_0 .net *"_s19", 0 0, L_0x2d60000; 1 drivers +v0x2b62720_0 .net/2s *"_s21", 0 0, L_0x2ac6110b8f58; 1 drivers +v0x2b62890_0 .net/2s *"_s23", 0 0, L_0x2ac6110b8fa0; 1 drivers +v0x2b62970_0 .net *"_s25", 0 0, L_0x2d60200; 1 drivers +v0x2b62a50_0 .net *"_s28", 0 0, L_0x2d602c0; 1 drivers +v0x2b62b30_0 .net/2s *"_s30", 0 0, L_0x2ac6110b8fe8; 1 drivers +v0x2b62c10_0 .net/2s *"_s32", 0 0, L_0x2ac6110b9030; 1 drivers +v0x2b62cf0_0 .net *"_s34", 0 0, L_0x2d604c0; 1 drivers +v0x2b62dd0_0 .net *"_s37", 0 0, L_0x2d605d0; 1 drivers +v0x2b62eb0_0 .net/2s *"_s39", 0 0, L_0x2ac6110b9078; 1 drivers +v0x2b63060_0 .net/2s *"_s41", 0 0, L_0x2ac6110b90c0; 1 drivers +v0x2b63100_0 .net *"_s43", 0 0, L_0x2d60780; 1 drivers +v0x2b631e0_0 .net *"_s46", 0 0, L_0x2d5ec00; 1 drivers +v0x2b632c0_0 .net/2s *"_s48", 0 0, L_0x2ac6110b9108; 1 drivers +v0x2b633a0_0 .net/2s *"_s50", 0 0, L_0x2ac6110b9150; 1 drivers +v0x2b63480_0 .net *"_s52", 0 0, L_0x2d60de0; 1 drivers +v0x2b63560_0 .net *"_s56", 0 0, L_0x2d612d0; 1 drivers +v0x2b63640_0 .net/2s *"_s59", 0 0, L_0x2ac6110b9198; 1 drivers +v0x2b63720_0 .net/2s *"_s61", 0 0, L_0x2ac6110b91e0; 1 drivers +v0x2b63800_0 .net *"_s8", 0 0, L_0x2d5f7a0; 1 drivers +v0x2b638e0_0 .net "carryin", 0 0, L_0x2d5e580; 1 drivers +v0x2b63980_0 .net "carryout", 0 0, L_0x2d68670; 1 drivers +v0x2b63a20_0 .net "carryouts", 7 0, L_0x2d60f60; 1 drivers +v0x2b63b30_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2af8030_0 .net "result", 0 0, L_0x2d64c30; 1 drivers +v0x2af8120_0 .net "results", 7 0, L_0x2d60bb0; 1 drivers +v0x2b62f50_0 .net "zero", 0 0, L_0x2d689d0; 1 drivers +LS_0x2d60bb0_0_0 .concat8 [ 1 1 1 1], L_0x2d5ec70, L_0x2d5f2a0, L_0x2d5f7a0, L_0x2d60000; +LS_0x2d60bb0_0_4 .concat8 [ 1 1 1 1], L_0x2d60200, L_0x2d604c0, L_0x2d60780, L_0x2d60de0; +L_0x2d60bb0 .concat8 [ 4 4 0 0], LS_0x2d60bb0_0_0, LS_0x2d60bb0_0_4; +LS_0x2d60f60_0_0 .concat8 [ 1 1 1 1], L_0x2d5ef20, L_0x2d5f640, L_0x2d5f860, L_0x2d5fe50; +LS_0x2d60f60_0_4 .concat8 [ 1 1 1 1], L_0x2d602c0, L_0x2d605d0, L_0x2d5ec00, L_0x2d612d0; +L_0x2d60f60 .concat8 [ 4 4 0 0], LS_0x2d60f60_0_0, LS_0x2d60f60_0_4; +S_0x2b53c00 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b53980; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1279460/d .functor OR 1, L_0x1278f40, L_0x1279300, C4<0>, C4<0>; -L_0x1279460 .delay 1 (30000,30000,30000) L_0x1279460/d; -v0x1088190_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers -v0x1088250_0 .net "b", 0 0, L_0x1282580; alias, 1 drivers -v0x1088320_0 .net "c1", 0 0, L_0x1278f40; 1 drivers -v0x1088420_0 .net "c2", 0 0, L_0x1279300; 1 drivers -v0x10884f0_0 .net "carryin", 0 0, L_0x1278b30; alias, 1 drivers -v0x10885e0_0 .net "carryout", 0 0, L_0x1279460; 1 drivers -v0x1088680_0 .net "s1", 0 0, L_0x1276330; 1 drivers -v0x1088770_0 .net "sum", 0 0, L_0x12791b0; 1 drivers -S_0x10875d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1087360; +L_0x2d5ef20/d .functor OR 1, L_0x2d5ea00, L_0x2d5edc0, C4<0>, C4<0>; +L_0x2d5ef20 .delay 1 (30000,30000,30000) L_0x2d5ef20/d; +v0x2b54a30_0 .net "a", 0 0, L_0x2d68ad0; alias, 1 drivers +v0x2b54af0_0 .net "b", 0 0, L_0x2d68c30; alias, 1 drivers +v0x2b54bc0_0 .net "c1", 0 0, L_0x2d5ea00; 1 drivers +v0x2b54cc0_0 .net "c2", 0 0, L_0x2d5edc0; 1 drivers +v0x2b54d90_0 .net "carryin", 0 0, L_0x2d5e580; alias, 1 drivers +v0x2b54e80_0 .net "carryout", 0 0, L_0x2d5ef20; 1 drivers +v0x2b54f20_0 .net "s1", 0 0, L_0x2d5e940; 1 drivers +v0x2b55010_0 .net "sum", 0 0, L_0x2d5ec70; 1 drivers +S_0x2b53e70 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b53c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1276330/d .functor XOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; -L_0x1276330 .delay 1 (30000,30000,30000) L_0x1276330/d; -L_0x1278f40/d .functor AND 1, L_0x1282420, L_0x1282580, C4<1>, C4<1>; -L_0x1278f40 .delay 1 (30000,30000,30000) L_0x1278f40/d; -v0x1087830_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers -v0x1087910_0 .net "b", 0 0, L_0x1282580; alias, 1 drivers -v0x10879d0_0 .net "carryout", 0 0, L_0x1278f40; alias, 1 drivers -v0x1087a70_0 .net "sum", 0 0, L_0x1276330; alias, 1 drivers -S_0x1087bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1087360; +L_0x2d5e940/d .functor XOR 1, L_0x2d68ad0, L_0x2d68c30, C4<0>, C4<0>; +L_0x2d5e940 .delay 1 (30000,30000,30000) L_0x2d5e940/d; +L_0x2d5ea00/d .functor AND 1, L_0x2d68ad0, L_0x2d68c30, C4<1>, C4<1>; +L_0x2d5ea00 .delay 1 (30000,30000,30000) L_0x2d5ea00/d; +v0x2b540d0_0 .net "a", 0 0, L_0x2d68ad0; alias, 1 drivers +v0x2b541b0_0 .net "b", 0 0, L_0x2d68c30; alias, 1 drivers +v0x2b54270_0 .net "carryout", 0 0, L_0x2d5ea00; alias, 1 drivers +v0x2b54310_0 .net "sum", 0 0, L_0x2d5e940; alias, 1 drivers +S_0x2b54450 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b53c00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12791b0/d .functor XOR 1, L_0x1276330, L_0x1278b30, C4<0>, C4<0>; -L_0x12791b0 .delay 1 (30000,30000,30000) L_0x12791b0/d; -L_0x1279300/d .functor AND 1, L_0x1276330, L_0x1278b30, C4<1>, C4<1>; -L_0x1279300 .delay 1 (30000,30000,30000) L_0x1279300/d; -v0x1087e10_0 .net "a", 0 0, L_0x1276330; alias, 1 drivers -v0x1087eb0_0 .net "b", 0 0, L_0x1278b30; alias, 1 drivers -v0x1087f50_0 .net "carryout", 0 0, L_0x1279300; alias, 1 drivers -v0x1088020_0 .net "sum", 0 0, L_0x12791b0; alias, 1 drivers -S_0x1088840 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10870e0; +L_0x2d5ec70/d .functor XOR 1, L_0x2d5e940, L_0x2d5e580, C4<0>, C4<0>; +L_0x2d5ec70 .delay 1 (30000,30000,30000) L_0x2d5ec70/d; +L_0x2d5edc0/d .functor AND 1, L_0x2d5e940, L_0x2d5e580, C4<1>, C4<1>; +L_0x2d5edc0 .delay 1 (30000,30000,30000) L_0x2d5edc0/d; +v0x2b546b0_0 .net "a", 0 0, L_0x2d5e940; alias, 1 drivers +v0x2b54750_0 .net "b", 0 0, L_0x2d5e580; alias, 1 drivers +v0x2b547f0_0 .net "carryout", 0 0, L_0x2d5edc0; alias, 1 drivers +v0x2b548c0_0 .net "sum", 0 0, L_0x2d5ec70; alias, 1 drivers +S_0x2b550e0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b53980; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x108dc30_0 .net "ands", 7 0, L_0x127ffc0; 1 drivers -v0x108dd40_0 .net "in", 7 0, L_0x1354220; alias, 1 drivers -v0x108de00_0 .net "out", 0 0, L_0x1281fc0; alias, 1 drivers -v0x108ded0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1088a60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1088840; +v0x2b5a4d0_0 .net "ands", 7 0, L_0x2d66670; 1 drivers +v0x2b5a5e0_0 .net "in", 7 0, L_0x2d60f60; alias, 1 drivers +v0x2b5a6a0_0 .net "out", 0 0, L_0x2d68670; alias, 1 drivers +v0x2b5a770_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b55300 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b550e0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x108b190_0 .net "A", 7 0, L_0x1354220; alias, 1 drivers -v0x108b290_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x108b350_0 .net *"_s0", 0 0, L_0x127e8e0; 1 drivers -v0x108b410_0 .net *"_s12", 0 0, L_0x127f250; 1 drivers -v0x108b4f0_0 .net *"_s16", 0 0, L_0x127f5b0; 1 drivers -v0x108b620_0 .net *"_s20", 0 0, L_0x127f8c0; 1 drivers -v0x108b700_0 .net *"_s24", 0 0, L_0x127fcb0; 1 drivers -v0x108b7e0_0 .net *"_s28", 0 0, L_0x127fc40; 1 drivers -v0x108b8c0_0 .net *"_s4", 0 0, L_0x127ebf0; 1 drivers -v0x108ba30_0 .net *"_s8", 0 0, L_0x127ef40; 1 drivers -v0x108bb10_0 .net "out", 7 0, L_0x127ffc0; alias, 1 drivers -L_0x127e9a0 .part L_0x1354220, 0, 1; -L_0x127eb00 .part v0x12010b0_0, 0, 1; -L_0x127ecb0 .part L_0x1354220, 1, 1; -L_0x127eea0 .part v0x12010b0_0, 1, 1; -L_0x127f000 .part L_0x1354220, 2, 1; -L_0x127f160 .part v0x12010b0_0, 2, 1; -L_0x127f310 .part L_0x1354220, 3, 1; -L_0x127f470 .part v0x12010b0_0, 3, 1; -L_0x127f670 .part L_0x1354220, 4, 1; -L_0x127f7d0 .part v0x12010b0_0, 4, 1; -L_0x127f930 .part L_0x1354220, 5, 1; -L_0x127fba0 .part v0x12010b0_0, 5, 1; -L_0x127fd70 .part L_0x1354220, 6, 1; -L_0x127fed0 .part v0x12010b0_0, 6, 1; -LS_0x127ffc0_0_0 .concat8 [ 1 1 1 1], L_0x127e8e0, L_0x127ebf0, L_0x127ef40, L_0x127f250; -LS_0x127ffc0_0_4 .concat8 [ 1 1 1 1], L_0x127f5b0, L_0x127f8c0, L_0x127fcb0, L_0x127fc40; -L_0x127ffc0 .concat8 [ 4 4 0 0], LS_0x127ffc0_0_0, LS_0x127ffc0_0_4; -L_0x1280380 .part L_0x1354220, 7, 1; -L_0x1280570 .part v0x12010b0_0, 7, 1; -S_0x1088cc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x1088ed0 .param/l "i" 0 4 54, +C4<00>; -L_0x127e8e0/d .functor AND 1, L_0x127e9a0, L_0x127eb00, C4<1>, C4<1>; -L_0x127e8e0 .delay 1 (30000,30000,30000) L_0x127e8e0/d; -v0x1088fb0_0 .net *"_s0", 0 0, L_0x127e9a0; 1 drivers -v0x1089090_0 .net *"_s1", 0 0, L_0x127eb00; 1 drivers -S_0x1089170 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x1089380 .param/l "i" 0 4 54, +C4<01>; -L_0x127ebf0/d .functor AND 1, L_0x127ecb0, L_0x127eea0, C4<1>, C4<1>; -L_0x127ebf0 .delay 1 (30000,30000,30000) L_0x127ebf0/d; -v0x1089440_0 .net *"_s0", 0 0, L_0x127ecb0; 1 drivers -v0x1089520_0 .net *"_s1", 0 0, L_0x127eea0; 1 drivers -S_0x1089600 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x1089810 .param/l "i" 0 4 54, +C4<010>; -L_0x127ef40/d .functor AND 1, L_0x127f000, L_0x127f160, C4<1>, C4<1>; -L_0x127ef40 .delay 1 (30000,30000,30000) L_0x127ef40/d; -v0x10898b0_0 .net *"_s0", 0 0, L_0x127f000; 1 drivers -v0x1089990_0 .net *"_s1", 0 0, L_0x127f160; 1 drivers -S_0x1089a70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x1089c80 .param/l "i" 0 4 54, +C4<011>; -L_0x127f250/d .functor AND 1, L_0x127f310, L_0x127f470, C4<1>, C4<1>; -L_0x127f250 .delay 1 (30000,30000,30000) L_0x127f250/d; -v0x1089d40_0 .net *"_s0", 0 0, L_0x127f310; 1 drivers -v0x1089e20_0 .net *"_s1", 0 0, L_0x127f470; 1 drivers -S_0x1089f00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x108a160 .param/l "i" 0 4 54, +C4<0100>; -L_0x127f5b0/d .functor AND 1, L_0x127f670, L_0x127f7d0, C4<1>, C4<1>; -L_0x127f5b0 .delay 1 (30000,30000,30000) L_0x127f5b0/d; -v0x108a220_0 .net *"_s0", 0 0, L_0x127f670; 1 drivers -v0x108a300_0 .net *"_s1", 0 0, L_0x127f7d0; 1 drivers -S_0x108a3e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x108a5f0 .param/l "i" 0 4 54, +C4<0101>; -L_0x127f8c0/d .functor AND 1, L_0x127f930, L_0x127fba0, C4<1>, C4<1>; -L_0x127f8c0 .delay 1 (30000,30000,30000) L_0x127f8c0/d; -v0x108a6b0_0 .net *"_s0", 0 0, L_0x127f930; 1 drivers -v0x108a790_0 .net *"_s1", 0 0, L_0x127fba0; 1 drivers -S_0x108a870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x108aa80 .param/l "i" 0 4 54, +C4<0110>; -L_0x127fcb0/d .functor AND 1, L_0x127fd70, L_0x127fed0, C4<1>, C4<1>; -L_0x127fcb0 .delay 1 (30000,30000,30000) L_0x127fcb0/d; -v0x108ab40_0 .net *"_s0", 0 0, L_0x127fd70; 1 drivers -v0x108ac20_0 .net *"_s1", 0 0, L_0x127fed0; 1 drivers -S_0x108ad00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1088a60; - .timescale -9 -12; -P_0x108af10 .param/l "i" 0 4 54, +C4<0111>; -L_0x127fc40/d .functor AND 1, L_0x1280380, L_0x1280570, C4<1>, C4<1>; -L_0x127fc40 .delay 1 (30000,30000,30000) L_0x127fc40/d; -v0x108afd0_0 .net *"_s0", 0 0, L_0x1280380; 1 drivers -v0x108b0b0_0 .net *"_s1", 0 0, L_0x1280570; 1 drivers -S_0x108bc70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1088840; +v0x2b57a30_0 .net "A", 7 0, L_0x2d60f60; alias, 1 drivers +v0x2b57b30_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b57bf0_0 .net *"_s0", 0 0, L_0x2d64f90; 1 drivers +v0x2b57cb0_0 .net *"_s12", 0 0, L_0x2d65900; 1 drivers +v0x2b57d90_0 .net *"_s16", 0 0, L_0x2d65c60; 1 drivers +v0x2b57ec0_0 .net *"_s20", 0 0, L_0x2d66030; 1 drivers +v0x2b57fa0_0 .net *"_s24", 0 0, L_0x2d66360; 1 drivers +v0x2b58080_0 .net *"_s28", 0 0, L_0x2d662f0; 1 drivers +v0x2b58160_0 .net *"_s4", 0 0, L_0x2d652e0; 1 drivers +v0x2b582d0_0 .net *"_s8", 0 0, L_0x2d655f0; 1 drivers +v0x2b583b0_0 .net "out", 7 0, L_0x2d66670; alias, 1 drivers +L_0x2d65050 .part L_0x2d60f60, 0, 1; +L_0x2d65240 .part v0x2cdd2e0_0, 0, 1; +L_0x2d653a0 .part L_0x2d60f60, 1, 1; +L_0x2d65500 .part v0x2cdd2e0_0, 1, 1; +L_0x2d656b0 .part L_0x2d60f60, 2, 1; +L_0x2d65810 .part v0x2cdd2e0_0, 2, 1; +L_0x2d659c0 .part L_0x2d60f60, 3, 1; +L_0x2d65b20 .part v0x2cdd2e0_0, 3, 1; +L_0x2d65d20 .part L_0x2d60f60, 4, 1; +L_0x2d65f90 .part v0x2cdd2e0_0, 4, 1; +L_0x2d660a0 .part L_0x2d60f60, 5, 1; +L_0x2d66200 .part v0x2cdd2e0_0, 5, 1; +L_0x2d66420 .part L_0x2d60f60, 6, 1; +L_0x2d66580 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d66670_0_0 .concat8 [ 1 1 1 1], L_0x2d64f90, L_0x2d652e0, L_0x2d655f0, L_0x2d65900; +LS_0x2d66670_0_4 .concat8 [ 1 1 1 1], L_0x2d65c60, L_0x2d66030, L_0x2d66360, L_0x2d662f0; +L_0x2d66670 .concat8 [ 4 4 0 0], LS_0x2d66670_0_0, LS_0x2d66670_0_4; +L_0x2d66a30 .part L_0x2d60f60, 7, 1; +L_0x2d66c20 .part v0x2cdd2e0_0, 7, 1; +S_0x2b55560 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b55770 .param/l "i" 0 4 54, +C4<00>; +L_0x2d64f90/d .functor AND 1, L_0x2d65050, L_0x2d65240, C4<1>, C4<1>; +L_0x2d64f90 .delay 1 (30000,30000,30000) L_0x2d64f90/d; +v0x2b55850_0 .net *"_s0", 0 0, L_0x2d65050; 1 drivers +v0x2b55930_0 .net *"_s1", 0 0, L_0x2d65240; 1 drivers +S_0x2b55a10 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b55c20 .param/l "i" 0 4 54, +C4<01>; +L_0x2d652e0/d .functor AND 1, L_0x2d653a0, L_0x2d65500, C4<1>, C4<1>; +L_0x2d652e0 .delay 1 (30000,30000,30000) L_0x2d652e0/d; +v0x2b55ce0_0 .net *"_s0", 0 0, L_0x2d653a0; 1 drivers +v0x2b55dc0_0 .net *"_s1", 0 0, L_0x2d65500; 1 drivers +S_0x2b55ea0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b560b0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d655f0/d .functor AND 1, L_0x2d656b0, L_0x2d65810, C4<1>, C4<1>; +L_0x2d655f0 .delay 1 (30000,30000,30000) L_0x2d655f0/d; +v0x2b56150_0 .net *"_s0", 0 0, L_0x2d656b0; 1 drivers +v0x2b56230_0 .net *"_s1", 0 0, L_0x2d65810; 1 drivers +S_0x2b56310 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b56520 .param/l "i" 0 4 54, +C4<011>; +L_0x2d65900/d .functor AND 1, L_0x2d659c0, L_0x2d65b20, C4<1>, C4<1>; +L_0x2d65900 .delay 1 (30000,30000,30000) L_0x2d65900/d; +v0x2b565e0_0 .net *"_s0", 0 0, L_0x2d659c0; 1 drivers +v0x2b566c0_0 .net *"_s1", 0 0, L_0x2d65b20; 1 drivers +S_0x2b567a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b56a00 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d65c60/d .functor AND 1, L_0x2d65d20, L_0x2d65f90, C4<1>, C4<1>; +L_0x2d65c60 .delay 1 (30000,30000,30000) L_0x2d65c60/d; +v0x2b56ac0_0 .net *"_s0", 0 0, L_0x2d65d20; 1 drivers +v0x2b56ba0_0 .net *"_s1", 0 0, L_0x2d65f90; 1 drivers +S_0x2b56c80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b56e90 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d66030/d .functor AND 1, L_0x2d660a0, L_0x2d66200, C4<1>, C4<1>; +L_0x2d66030 .delay 1 (30000,30000,30000) L_0x2d66030/d; +v0x2b56f50_0 .net *"_s0", 0 0, L_0x2d660a0; 1 drivers +v0x2b57030_0 .net *"_s1", 0 0, L_0x2d66200; 1 drivers +S_0x2b57110 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b57320 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d66360/d .functor AND 1, L_0x2d66420, L_0x2d66580, C4<1>, C4<1>; +L_0x2d66360 .delay 1 (30000,30000,30000) L_0x2d66360/d; +v0x2b573e0_0 .net *"_s0", 0 0, L_0x2d66420; 1 drivers +v0x2b574c0_0 .net *"_s1", 0 0, L_0x2d66580; 1 drivers +S_0x2b575a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b55300; + .timescale -9 -12; +P_0x2b577b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d662f0/d .functor AND 1, L_0x2d66a30, L_0x2d66c20, C4<1>, C4<1>; +L_0x2d662f0 .delay 1 (30000,30000,30000) L_0x2d662f0/d; +v0x2b57870_0 .net *"_s0", 0 0, L_0x2d66a30; 1 drivers +v0x2b57950_0 .net *"_s1", 0 0, L_0x2d66c20; 1 drivers +S_0x2b58510 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b550e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1281fc0/d .functor OR 1, L_0x1282080, L_0x1282230, C4<0>, C4<0>; -L_0x1281fc0 .delay 1 (30000,30000,30000) L_0x1281fc0/d; -v0x108d7c0_0 .net *"_s10", 0 0, L_0x1282080; 1 drivers -v0x108d8a0_0 .net *"_s12", 0 0, L_0x1282230; 1 drivers -v0x108d980_0 .net "in", 7 0, L_0x127ffc0; alias, 1 drivers -v0x108da50_0 .net "ors", 1 0, L_0x1281de0; 1 drivers -v0x108db10_0 .net "out", 0 0, L_0x1281fc0; alias, 1 drivers -L_0x12811b0 .part L_0x127ffc0, 0, 4; -L_0x1281de0 .concat8 [ 1 1 0 0], L_0x1280ea0, L_0x1281ad0; -L_0x1281f20 .part L_0x127ffc0, 4, 4; -L_0x1282080 .part L_0x1281de0, 0, 1; -L_0x1282230 .part L_0x1281de0, 1, 1; -S_0x108be30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x108bc70; +L_0x2d68670/d .functor OR 1, L_0x2d68730, L_0x2d688e0, C4<0>, C4<0>; +L_0x2d68670 .delay 1 (30000,30000,30000) L_0x2d68670/d; +v0x2b5a060_0 .net *"_s10", 0 0, L_0x2d68730; 1 drivers +v0x2b5a140_0 .net *"_s12", 0 0, L_0x2d688e0; 1 drivers +v0x2b5a220_0 .net "in", 7 0, L_0x2d66670; alias, 1 drivers +v0x2b5a2f0_0 .net "ors", 1 0, L_0x2d68490; 1 drivers +v0x2b5a3b0_0 .net "out", 0 0, L_0x2d68670; alias, 1 drivers +L_0x2d67860 .part L_0x2d66670, 0, 4; +L_0x2d68490 .concat8 [ 1 1 0 0], L_0x2d67550, L_0x2d68180; +L_0x2d685d0 .part L_0x2d66670, 4, 4; +L_0x2d68730 .part L_0x2d68490, 0, 1; +L_0x2d688e0 .part L_0x2d68490, 1, 1; +S_0x2b586d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b58510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1280660/d .functor OR 1, L_0x1280720, L_0x1280880, C4<0>, C4<0>; -L_0x1280660 .delay 1 (30000,30000,30000) L_0x1280660/d; -L_0x1280ab0/d .functor OR 1, L_0x1280bc0, L_0x1280d20, C4<0>, C4<0>; -L_0x1280ab0 .delay 1 (30000,30000,30000) L_0x1280ab0/d; -L_0x1280ea0/d .functor OR 1, L_0x1280f10, L_0x12810c0, C4<0>, C4<0>; -L_0x1280ea0 .delay 1 (30000,30000,30000) L_0x1280ea0/d; -v0x108c080_0 .net *"_s0", 0 0, L_0x1280660; 1 drivers -v0x108c180_0 .net *"_s10", 0 0, L_0x1280bc0; 1 drivers -v0x108c260_0 .net *"_s12", 0 0, L_0x1280d20; 1 drivers -v0x108c320_0 .net *"_s14", 0 0, L_0x1280f10; 1 drivers -v0x108c400_0 .net *"_s16", 0 0, L_0x12810c0; 1 drivers -v0x108c530_0 .net *"_s3", 0 0, L_0x1280720; 1 drivers -v0x108c610_0 .net *"_s5", 0 0, L_0x1280880; 1 drivers -v0x108c6f0_0 .net *"_s6", 0 0, L_0x1280ab0; 1 drivers -v0x108c7d0_0 .net "in", 3 0, L_0x12811b0; 1 drivers -v0x108c940_0 .net "ors", 1 0, L_0x12809c0; 1 drivers -v0x108ca20_0 .net "out", 0 0, L_0x1280ea0; 1 drivers -L_0x1280720 .part L_0x12811b0, 0, 1; -L_0x1280880 .part L_0x12811b0, 1, 1; -L_0x12809c0 .concat8 [ 1 1 0 0], L_0x1280660, L_0x1280ab0; -L_0x1280bc0 .part L_0x12811b0, 2, 1; -L_0x1280d20 .part L_0x12811b0, 3, 1; -L_0x1280f10 .part L_0x12809c0, 0, 1; -L_0x12810c0 .part L_0x12809c0, 1, 1; -S_0x108cb40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x108bc70; +L_0x2d66d10/d .functor OR 1, L_0x2d66dd0, L_0x2d66f30, C4<0>, C4<0>; +L_0x2d66d10 .delay 1 (30000,30000,30000) L_0x2d66d10/d; +L_0x2d67160/d .functor OR 1, L_0x2d67270, L_0x2d673d0, C4<0>, C4<0>; +L_0x2d67160 .delay 1 (30000,30000,30000) L_0x2d67160/d; +L_0x2d67550/d .functor OR 1, L_0x2d675c0, L_0x2d67770, C4<0>, C4<0>; +L_0x2d67550 .delay 1 (30000,30000,30000) L_0x2d67550/d; +v0x2b58920_0 .net *"_s0", 0 0, L_0x2d66d10; 1 drivers +v0x2b58a20_0 .net *"_s10", 0 0, L_0x2d67270; 1 drivers +v0x2b58b00_0 .net *"_s12", 0 0, L_0x2d673d0; 1 drivers +v0x2b58bc0_0 .net *"_s14", 0 0, L_0x2d675c0; 1 drivers +v0x2b58ca0_0 .net *"_s16", 0 0, L_0x2d67770; 1 drivers +v0x2b58dd0_0 .net *"_s3", 0 0, L_0x2d66dd0; 1 drivers +v0x2b58eb0_0 .net *"_s5", 0 0, L_0x2d66f30; 1 drivers +v0x2b58f90_0 .net *"_s6", 0 0, L_0x2d67160; 1 drivers +v0x2b59070_0 .net "in", 3 0, L_0x2d67860; 1 drivers +v0x2b591e0_0 .net "ors", 1 0, L_0x2d67070; 1 drivers +v0x2b592c0_0 .net "out", 0 0, L_0x2d67550; 1 drivers +L_0x2d66dd0 .part L_0x2d67860, 0, 1; +L_0x2d66f30 .part L_0x2d67860, 1, 1; +L_0x2d67070 .concat8 [ 1 1 0 0], L_0x2d66d10, L_0x2d67160; +L_0x2d67270 .part L_0x2d67860, 2, 1; +L_0x2d673d0 .part L_0x2d67860, 3, 1; +L_0x2d675c0 .part L_0x2d67070, 0, 1; +L_0x2d67770 .part L_0x2d67070, 1, 1; +S_0x2b593e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b58510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12812e0/d .functor OR 1, L_0x1281350, L_0x12814b0, C4<0>, C4<0>; -L_0x12812e0 .delay 1 (30000,30000,30000) L_0x12812e0/d; -L_0x12816e0/d .functor OR 1, L_0x12817f0, L_0x1281950, C4<0>, C4<0>; -L_0x12816e0 .delay 1 (30000,30000,30000) L_0x12816e0/d; -L_0x1281ad0/d .functor OR 1, L_0x1281b40, L_0x1281cf0, C4<0>, C4<0>; -L_0x1281ad0 .delay 1 (30000,30000,30000) L_0x1281ad0/d; -v0x108cd00_0 .net *"_s0", 0 0, L_0x12812e0; 1 drivers -v0x108ce00_0 .net *"_s10", 0 0, L_0x12817f0; 1 drivers -v0x108cee0_0 .net *"_s12", 0 0, L_0x1281950; 1 drivers -v0x108cfa0_0 .net *"_s14", 0 0, L_0x1281b40; 1 drivers -v0x108d080_0 .net *"_s16", 0 0, L_0x1281cf0; 1 drivers -v0x108d1b0_0 .net *"_s3", 0 0, L_0x1281350; 1 drivers -v0x108d290_0 .net *"_s5", 0 0, L_0x12814b0; 1 drivers -v0x108d370_0 .net *"_s6", 0 0, L_0x12816e0; 1 drivers -v0x108d450_0 .net "in", 3 0, L_0x1281f20; 1 drivers -v0x108d5c0_0 .net "ors", 1 0, L_0x12815f0; 1 drivers -v0x108d6a0_0 .net "out", 0 0, L_0x1281ad0; 1 drivers -L_0x1281350 .part L_0x1281f20, 0, 1; -L_0x12814b0 .part L_0x1281f20, 1, 1; -L_0x12815f0 .concat8 [ 1 1 0 0], L_0x12812e0, L_0x12816e0; -L_0x12817f0 .part L_0x1281f20, 2, 1; -L_0x1281950 .part L_0x1281f20, 3, 1; -L_0x1281b40 .part L_0x12815f0, 0, 1; -L_0x1281cf0 .part L_0x12815f0, 1, 1; -S_0x108dfb0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10870e0; +L_0x2d67990/d .functor OR 1, L_0x2d67a00, L_0x2d67b60, C4<0>, C4<0>; +L_0x2d67990 .delay 1 (30000,30000,30000) L_0x2d67990/d; +L_0x2d67d90/d .functor OR 1, L_0x2d67ea0, L_0x2d68000, C4<0>, C4<0>; +L_0x2d67d90 .delay 1 (30000,30000,30000) L_0x2d67d90/d; +L_0x2d68180/d .functor OR 1, L_0x2d681f0, L_0x2d683a0, C4<0>, C4<0>; +L_0x2d68180 .delay 1 (30000,30000,30000) L_0x2d68180/d; +v0x2b595a0_0 .net *"_s0", 0 0, L_0x2d67990; 1 drivers +v0x2b596a0_0 .net *"_s10", 0 0, L_0x2d67ea0; 1 drivers +v0x2b59780_0 .net *"_s12", 0 0, L_0x2d68000; 1 drivers +v0x2b59840_0 .net *"_s14", 0 0, L_0x2d681f0; 1 drivers +v0x2b59920_0 .net *"_s16", 0 0, L_0x2d683a0; 1 drivers +v0x2b59a50_0 .net *"_s3", 0 0, L_0x2d67a00; 1 drivers +v0x2b59b30_0 .net *"_s5", 0 0, L_0x2d67b60; 1 drivers +v0x2b59c10_0 .net *"_s6", 0 0, L_0x2d67d90; 1 drivers +v0x2b59cf0_0 .net "in", 3 0, L_0x2d685d0; 1 drivers +v0x2b59e60_0 .net "ors", 1 0, L_0x2d67ca0; 1 drivers +v0x2b59f40_0 .net "out", 0 0, L_0x2d68180; 1 drivers +L_0x2d67a00 .part L_0x2d685d0, 0, 1; +L_0x2d67b60 .part L_0x2d685d0, 1, 1; +L_0x2d67ca0 .concat8 [ 1 1 0 0], L_0x2d67990, L_0x2d67d90; +L_0x2d67ea0 .part L_0x2d685d0, 2, 1; +L_0x2d68000 .part L_0x2d685d0, 3, 1; +L_0x2d681f0 .part L_0x2d67ca0, 0, 1; +L_0x2d683a0 .part L_0x2d67ca0, 1, 1; +S_0x2b5a850 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b53980; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10933e0_0 .net "ands", 7 0, L_0x127c580; 1 drivers -v0x10934f0_0 .net "in", 7 0, L_0x127a9e0; alias, 1 drivers -v0x10935b0_0 .net "out", 0 0, L_0x127e580; alias, 1 drivers -v0x1093680_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x108e200 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x108dfb0; +v0x2b5fc90_0 .net "ands", 7 0, L_0x2d62c30; 1 drivers +v0x2b5fda0_0 .net "in", 7 0, L_0x2d60bb0; alias, 1 drivers +v0x2b5fe60_0 .net "out", 0 0, L_0x2d64c30; alias, 1 drivers +v0x2b5ff30_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b5aaa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b5a850; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1090940_0 .net "A", 7 0, L_0x127a9e0; alias, 1 drivers -v0x1090a40_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1090b00_0 .net *"_s0", 0 0, L_0x127ad70; 1 drivers -v0x1090bc0_0 .net *"_s12", 0 0, L_0x127b730; 1 drivers -v0x1090ca0_0 .net *"_s16", 0 0, L_0x127ba90; 1 drivers -v0x1090dd0_0 .net *"_s20", 0 0, L_0x127bec0; 1 drivers -v0x1090eb0_0 .net *"_s24", 0 0, L_0x127c1f0; 1 drivers -v0x1090f90_0 .net *"_s28", 0 0, L_0x127c180; 1 drivers -v0x1091070_0 .net *"_s4", 0 0, L_0x127b110; 1 drivers -v0x10911e0_0 .net *"_s8", 0 0, L_0x127b420; 1 drivers -v0x10912c0_0 .net "out", 7 0, L_0x127c580; alias, 1 drivers -L_0x127ae80 .part L_0x127a9e0, 0, 1; -L_0x127b070 .part v0x12010b0_0, 0, 1; -L_0x127b1d0 .part L_0x127a9e0, 1, 1; -L_0x127b330 .part v0x12010b0_0, 1, 1; -L_0x127b4e0 .part L_0x127a9e0, 2, 1; -L_0x127b640 .part v0x12010b0_0, 2, 1; -L_0x127b7f0 .part L_0x127a9e0, 3, 1; -L_0x127b950 .part v0x12010b0_0, 3, 1; -L_0x127bb50 .part L_0x127a9e0, 4, 1; -L_0x127bdc0 .part v0x12010b0_0, 4, 1; -L_0x127bf30 .part L_0x127a9e0, 5, 1; -L_0x127c090 .part v0x12010b0_0, 5, 1; -L_0x127c2b0 .part L_0x127a9e0, 6, 1; -L_0x127c410 .part v0x12010b0_0, 6, 1; -LS_0x127c580_0_0 .concat8 [ 1 1 1 1], L_0x127ad70, L_0x127b110, L_0x127b420, L_0x127b730; -LS_0x127c580_0_4 .concat8 [ 1 1 1 1], L_0x127ba90, L_0x127bec0, L_0x127c1f0, L_0x127c180; -L_0x127c580 .concat8 [ 4 4 0 0], LS_0x127c580_0_0, LS_0x127c580_0_4; -L_0x127c940 .part L_0x127a9e0, 7, 1; -L_0x127cb30 .part v0x12010b0_0, 7, 1; -S_0x108e440 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x108e650 .param/l "i" 0 4 54, +C4<00>; -L_0x127ad70/d .functor AND 1, L_0x127ae80, L_0x127b070, C4<1>, C4<1>; -L_0x127ad70 .delay 1 (30000,30000,30000) L_0x127ad70/d; -v0x108e730_0 .net *"_s0", 0 0, L_0x127ae80; 1 drivers -v0x108e810_0 .net *"_s1", 0 0, L_0x127b070; 1 drivers -S_0x108e8f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x108eb00 .param/l "i" 0 4 54, +C4<01>; -L_0x127b110/d .functor AND 1, L_0x127b1d0, L_0x127b330, C4<1>, C4<1>; -L_0x127b110 .delay 1 (30000,30000,30000) L_0x127b110/d; -v0x108ebc0_0 .net *"_s0", 0 0, L_0x127b1d0; 1 drivers -v0x108eca0_0 .net *"_s1", 0 0, L_0x127b330; 1 drivers -S_0x108ed80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x108efc0 .param/l "i" 0 4 54, +C4<010>; -L_0x127b420/d .functor AND 1, L_0x127b4e0, L_0x127b640, C4<1>, C4<1>; -L_0x127b420 .delay 1 (30000,30000,30000) L_0x127b420/d; -v0x108f060_0 .net *"_s0", 0 0, L_0x127b4e0; 1 drivers -v0x108f140_0 .net *"_s1", 0 0, L_0x127b640; 1 drivers -S_0x108f220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x108f430 .param/l "i" 0 4 54, +C4<011>; -L_0x127b730/d .functor AND 1, L_0x127b7f0, L_0x127b950, C4<1>, C4<1>; -L_0x127b730 .delay 1 (30000,30000,30000) L_0x127b730/d; -v0x108f4f0_0 .net *"_s0", 0 0, L_0x127b7f0; 1 drivers -v0x108f5d0_0 .net *"_s1", 0 0, L_0x127b950; 1 drivers -S_0x108f6b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x108f910 .param/l "i" 0 4 54, +C4<0100>; -L_0x127ba90/d .functor AND 1, L_0x127bb50, L_0x127bdc0, C4<1>, C4<1>; -L_0x127ba90 .delay 1 (30000,30000,30000) L_0x127ba90/d; -v0x108f9d0_0 .net *"_s0", 0 0, L_0x127bb50; 1 drivers -v0x108fab0_0 .net *"_s1", 0 0, L_0x127bdc0; 1 drivers -S_0x108fb90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x108fda0 .param/l "i" 0 4 54, +C4<0101>; -L_0x127bec0/d .functor AND 1, L_0x127bf30, L_0x127c090, C4<1>, C4<1>; -L_0x127bec0 .delay 1 (30000,30000,30000) L_0x127bec0/d; -v0x108fe60_0 .net *"_s0", 0 0, L_0x127bf30; 1 drivers -v0x108ff40_0 .net *"_s1", 0 0, L_0x127c090; 1 drivers -S_0x1090020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x1090230 .param/l "i" 0 4 54, +C4<0110>; -L_0x127c1f0/d .functor AND 1, L_0x127c2b0, L_0x127c410, C4<1>, C4<1>; -L_0x127c1f0 .delay 1 (30000,30000,30000) L_0x127c1f0/d; -v0x10902f0_0 .net *"_s0", 0 0, L_0x127c2b0; 1 drivers -v0x10903d0_0 .net *"_s1", 0 0, L_0x127c410; 1 drivers -S_0x10904b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x108e200; - .timescale -9 -12; -P_0x10906c0 .param/l "i" 0 4 54, +C4<0111>; -L_0x127c180/d .functor AND 1, L_0x127c940, L_0x127cb30, C4<1>, C4<1>; -L_0x127c180 .delay 1 (30000,30000,30000) L_0x127c180/d; -v0x1090780_0 .net *"_s0", 0 0, L_0x127c940; 1 drivers -v0x1090860_0 .net *"_s1", 0 0, L_0x127cb30; 1 drivers -S_0x1091420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x108dfb0; +v0x2b5d1c0_0 .net "A", 7 0, L_0x2d60bb0; alias, 1 drivers +v0x2b5d2c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b5d380_0 .net *"_s0", 0 0, L_0x2d61480; 1 drivers +v0x2b5d470_0 .net *"_s12", 0 0, L_0x2d61e40; 1 drivers +v0x2b5d550_0 .net *"_s16", 0 0, L_0x2d621a0; 1 drivers +v0x2b5d680_0 .net *"_s20", 0 0, L_0x2d62570; 1 drivers +v0x2b5d760_0 .net *"_s24", 0 0, L_0x2d628a0; 1 drivers +v0x2b5d840_0 .net *"_s28", 0 0, L_0x2d62830; 1 drivers +v0x2b5d920_0 .net *"_s4", 0 0, L_0x2d61820; 1 drivers +v0x2b5da90_0 .net *"_s8", 0 0, L_0x2d61b30; 1 drivers +v0x2b5db70_0 .net "out", 7 0, L_0x2d62c30; alias, 1 drivers +L_0x2d61590 .part L_0x2d60bb0, 0, 1; +L_0x2d61780 .part v0x2cdd2e0_0, 0, 1; +L_0x2d618e0 .part L_0x2d60bb0, 1, 1; +L_0x2d61a40 .part v0x2cdd2e0_0, 1, 1; +L_0x2d61bf0 .part L_0x2d60bb0, 2, 1; +L_0x2d61d50 .part v0x2cdd2e0_0, 2, 1; +L_0x2d61f00 .part L_0x2d60bb0, 3, 1; +L_0x2d62060 .part v0x2cdd2e0_0, 3, 1; +L_0x2d62260 .part L_0x2d60bb0, 4, 1; +L_0x2d624d0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d625e0 .part L_0x2d60bb0, 5, 1; +L_0x2d62740 .part v0x2cdd2e0_0, 5, 1; +L_0x2d62960 .part L_0x2d60bb0, 6, 1; +L_0x2d62ac0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d62c30_0_0 .concat8 [ 1 1 1 1], L_0x2d61480, L_0x2d61820, L_0x2d61b30, L_0x2d61e40; +LS_0x2d62c30_0_4 .concat8 [ 1 1 1 1], L_0x2d621a0, L_0x2d62570, L_0x2d628a0, L_0x2d62830; +L_0x2d62c30 .concat8 [ 4 4 0 0], LS_0x2d62c30_0_0, LS_0x2d62c30_0_4; +L_0x2d62ff0 .part L_0x2d60bb0, 7, 1; +L_0x2d631e0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b5ace0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5aef0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d61480/d .functor AND 1, L_0x2d61590, L_0x2d61780, C4<1>, C4<1>; +L_0x2d61480 .delay 1 (30000,30000,30000) L_0x2d61480/d; +v0x2b5afd0_0 .net *"_s0", 0 0, L_0x2d61590; 1 drivers +v0x2b5b0b0_0 .net *"_s1", 0 0, L_0x2d61780; 1 drivers +S_0x2b5b190 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5b3a0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d61820/d .functor AND 1, L_0x2d618e0, L_0x2d61a40, C4<1>, C4<1>; +L_0x2d61820 .delay 1 (30000,30000,30000) L_0x2d61820/d; +v0x2b5b460_0 .net *"_s0", 0 0, L_0x2d618e0; 1 drivers +v0x2b5b540_0 .net *"_s1", 0 0, L_0x2d61a40; 1 drivers +S_0x2b5b620 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5b860 .param/l "i" 0 4 54, +C4<010>; +L_0x2d61b30/d .functor AND 1, L_0x2d61bf0, L_0x2d61d50, C4<1>, C4<1>; +L_0x2d61b30 .delay 1 (30000,30000,30000) L_0x2d61b30/d; +v0x2b5b900_0 .net *"_s0", 0 0, L_0x2d61bf0; 1 drivers +v0x2b5b9e0_0 .net *"_s1", 0 0, L_0x2d61d50; 1 drivers +S_0x2b5bac0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5bcd0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d61e40/d .functor AND 1, L_0x2d61f00, L_0x2d62060, C4<1>, C4<1>; +L_0x2d61e40 .delay 1 (30000,30000,30000) L_0x2d61e40/d; +v0x2b5bd90_0 .net *"_s0", 0 0, L_0x2d61f00; 1 drivers +v0x2b5be70_0 .net *"_s1", 0 0, L_0x2d62060; 1 drivers +S_0x2b5bf50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5c1b0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d621a0/d .functor AND 1, L_0x2d62260, L_0x2d624d0, C4<1>, C4<1>; +L_0x2d621a0 .delay 1 (30000,30000,30000) L_0x2d621a0/d; +v0x2b5c270_0 .net *"_s0", 0 0, L_0x2d62260; 1 drivers +v0x2b5c350_0 .net *"_s1", 0 0, L_0x2d624d0; 1 drivers +S_0x2b5c430 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5c640 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d62570/d .functor AND 1, L_0x2d625e0, L_0x2d62740, C4<1>, C4<1>; +L_0x2d62570 .delay 1 (30000,30000,30000) L_0x2d62570/d; +v0x2b5c700_0 .net *"_s0", 0 0, L_0x2d625e0; 1 drivers +v0x2b5c7e0_0 .net *"_s1", 0 0, L_0x2d62740; 1 drivers +S_0x2b5c8c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5cad0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d628a0/d .functor AND 1, L_0x2d62960, L_0x2d62ac0, C4<1>, C4<1>; +L_0x2d628a0 .delay 1 (30000,30000,30000) L_0x2d628a0/d; +v0x2b5cb90_0 .net *"_s0", 0 0, L_0x2d62960; 1 drivers +v0x2b5cc70_0 .net *"_s1", 0 0, L_0x2d62ac0; 1 drivers +S_0x2b5cd50 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b5aaa0; + .timescale -9 -12; +P_0x2b5cf60 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d62830/d .functor AND 1, L_0x2d62ff0, L_0x2d631e0, C4<1>, C4<1>; +L_0x2d62830 .delay 1 (30000,30000,30000) L_0x2d62830/d; +v0x2b5d000_0 .net *"_s0", 0 0, L_0x2d62ff0; 1 drivers +v0x2b5d0e0_0 .net *"_s1", 0 0, L_0x2d631e0; 1 drivers +S_0x2b5dcd0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b5a850; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x127e580/d .functor OR 1, L_0x127e640, L_0x127e7f0, C4<0>, C4<0>; -L_0x127e580 .delay 1 (30000,30000,30000) L_0x127e580/d; -v0x1092f70_0 .net *"_s10", 0 0, L_0x127e640; 1 drivers -v0x1093050_0 .net *"_s12", 0 0, L_0x127e7f0; 1 drivers -v0x1093130_0 .net "in", 7 0, L_0x127c580; alias, 1 drivers -v0x1093200_0 .net "ors", 1 0, L_0x127e3a0; 1 drivers -v0x10932c0_0 .net "out", 0 0, L_0x127e580; alias, 1 drivers -L_0x127d770 .part L_0x127c580, 0, 4; -L_0x127e3a0 .concat8 [ 1 1 0 0], L_0x127d460, L_0x127e090; -L_0x127e4e0 .part L_0x127c580, 4, 4; -L_0x127e640 .part L_0x127e3a0, 0, 1; -L_0x127e7f0 .part L_0x127e3a0, 1, 1; -S_0x10915e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1091420; +L_0x2d64c30/d .functor OR 1, L_0x2d64cf0, L_0x2d64ea0, C4<0>, C4<0>; +L_0x2d64c30 .delay 1 (30000,30000,30000) L_0x2d64c30/d; +v0x2b5f820_0 .net *"_s10", 0 0, L_0x2d64cf0; 1 drivers +v0x2b5f900_0 .net *"_s12", 0 0, L_0x2d64ea0; 1 drivers +v0x2b5f9e0_0 .net "in", 7 0, L_0x2d62c30; alias, 1 drivers +v0x2b5fab0_0 .net "ors", 1 0, L_0x2d64a50; 1 drivers +v0x2b5fb70_0 .net "out", 0 0, L_0x2d64c30; alias, 1 drivers +L_0x2d63e20 .part L_0x2d62c30, 0, 4; +L_0x2d64a50 .concat8 [ 1 1 0 0], L_0x2d63b10, L_0x2d64740; +L_0x2d64b90 .part L_0x2d62c30, 4, 4; +L_0x2d64cf0 .part L_0x2d64a50, 0, 1; +L_0x2d64ea0 .part L_0x2d64a50, 1, 1; +S_0x2b5de90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b5dcd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x127cc20/d .functor OR 1, L_0x127cce0, L_0x127ce40, C4<0>, C4<0>; -L_0x127cc20 .delay 1 (30000,30000,30000) L_0x127cc20/d; -L_0x127d070/d .functor OR 1, L_0x127d180, L_0x127d2e0, C4<0>, C4<0>; -L_0x127d070 .delay 1 (30000,30000,30000) L_0x127d070/d; -L_0x127d460/d .functor OR 1, L_0x127d4d0, L_0x127d680, C4<0>, C4<0>; -L_0x127d460 .delay 1 (30000,30000,30000) L_0x127d460/d; -v0x1091830_0 .net *"_s0", 0 0, L_0x127cc20; 1 drivers -v0x1091930_0 .net *"_s10", 0 0, L_0x127d180; 1 drivers -v0x1091a10_0 .net *"_s12", 0 0, L_0x127d2e0; 1 drivers -v0x1091ad0_0 .net *"_s14", 0 0, L_0x127d4d0; 1 drivers -v0x1091bb0_0 .net *"_s16", 0 0, L_0x127d680; 1 drivers -v0x1091ce0_0 .net *"_s3", 0 0, L_0x127cce0; 1 drivers -v0x1091dc0_0 .net *"_s5", 0 0, L_0x127ce40; 1 drivers -v0x1091ea0_0 .net *"_s6", 0 0, L_0x127d070; 1 drivers -v0x1091f80_0 .net "in", 3 0, L_0x127d770; 1 drivers -v0x10920f0_0 .net "ors", 1 0, L_0x127cf80; 1 drivers -v0x10921d0_0 .net "out", 0 0, L_0x127d460; 1 drivers -L_0x127cce0 .part L_0x127d770, 0, 1; -L_0x127ce40 .part L_0x127d770, 1, 1; -L_0x127cf80 .concat8 [ 1 1 0 0], L_0x127cc20, L_0x127d070; -L_0x127d180 .part L_0x127d770, 2, 1; -L_0x127d2e0 .part L_0x127d770, 3, 1; -L_0x127d4d0 .part L_0x127cf80, 0, 1; -L_0x127d680 .part L_0x127cf80, 1, 1; -S_0x10922f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1091420; +L_0x2d632d0/d .functor OR 1, L_0x2d63390, L_0x2d634f0, C4<0>, C4<0>; +L_0x2d632d0 .delay 1 (30000,30000,30000) L_0x2d632d0/d; +L_0x2d63720/d .functor OR 1, L_0x2d63830, L_0x2d63990, C4<0>, C4<0>; +L_0x2d63720 .delay 1 (30000,30000,30000) L_0x2d63720/d; +L_0x2d63b10/d .functor OR 1, L_0x2d63b80, L_0x2d63d30, C4<0>, C4<0>; +L_0x2d63b10 .delay 1 (30000,30000,30000) L_0x2d63b10/d; +v0x2b5e0e0_0 .net *"_s0", 0 0, L_0x2d632d0; 1 drivers +v0x2b5e1e0_0 .net *"_s10", 0 0, L_0x2d63830; 1 drivers +v0x2b5e2c0_0 .net *"_s12", 0 0, L_0x2d63990; 1 drivers +v0x2b5e380_0 .net *"_s14", 0 0, L_0x2d63b80; 1 drivers +v0x2b5e460_0 .net *"_s16", 0 0, L_0x2d63d30; 1 drivers +v0x2b5e590_0 .net *"_s3", 0 0, L_0x2d63390; 1 drivers +v0x2b5e670_0 .net *"_s5", 0 0, L_0x2d634f0; 1 drivers +v0x2b5e750_0 .net *"_s6", 0 0, L_0x2d63720; 1 drivers +v0x2b5e830_0 .net "in", 3 0, L_0x2d63e20; 1 drivers +v0x2b5e9a0_0 .net "ors", 1 0, L_0x2d63630; 1 drivers +v0x2b5ea80_0 .net "out", 0 0, L_0x2d63b10; 1 drivers +L_0x2d63390 .part L_0x2d63e20, 0, 1; +L_0x2d634f0 .part L_0x2d63e20, 1, 1; +L_0x2d63630 .concat8 [ 1 1 0 0], L_0x2d632d0, L_0x2d63720; +L_0x2d63830 .part L_0x2d63e20, 2, 1; +L_0x2d63990 .part L_0x2d63e20, 3, 1; +L_0x2d63b80 .part L_0x2d63630, 0, 1; +L_0x2d63d30 .part L_0x2d63630, 1, 1; +S_0x2b5eba0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b5dcd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x127d8a0/d .functor OR 1, L_0x127d910, L_0x127da70, C4<0>, C4<0>; -L_0x127d8a0 .delay 1 (30000,30000,30000) L_0x127d8a0/d; -L_0x127dca0/d .functor OR 1, L_0x127ddb0, L_0x127df10, C4<0>, C4<0>; -L_0x127dca0 .delay 1 (30000,30000,30000) L_0x127dca0/d; -L_0x127e090/d .functor OR 1, L_0x127e100, L_0x127e2b0, C4<0>, C4<0>; -L_0x127e090 .delay 1 (30000,30000,30000) L_0x127e090/d; -v0x10924b0_0 .net *"_s0", 0 0, L_0x127d8a0; 1 drivers -v0x10925b0_0 .net *"_s10", 0 0, L_0x127ddb0; 1 drivers -v0x1092690_0 .net *"_s12", 0 0, L_0x127df10; 1 drivers -v0x1092750_0 .net *"_s14", 0 0, L_0x127e100; 1 drivers -v0x1092830_0 .net *"_s16", 0 0, L_0x127e2b0; 1 drivers -v0x1092960_0 .net *"_s3", 0 0, L_0x127d910; 1 drivers -v0x1092a40_0 .net *"_s5", 0 0, L_0x127da70; 1 drivers -v0x1092b20_0 .net *"_s6", 0 0, L_0x127dca0; 1 drivers -v0x1092c00_0 .net "in", 3 0, L_0x127e4e0; 1 drivers -v0x1092d70_0 .net "ors", 1 0, L_0x127dbb0; 1 drivers -v0x1092e50_0 .net "out", 0 0, L_0x127e090; 1 drivers -L_0x127d910 .part L_0x127e4e0, 0, 1; -L_0x127da70 .part L_0x127e4e0, 1, 1; -L_0x127dbb0 .concat8 [ 1 1 0 0], L_0x127d8a0, L_0x127dca0; -L_0x127ddb0 .part L_0x127e4e0, 2, 1; -L_0x127df10 .part L_0x127e4e0, 3, 1; -L_0x127e100 .part L_0x127dbb0, 0, 1; -L_0x127e2b0 .part L_0x127dbb0, 1, 1; -S_0x1093760 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10870e0; +L_0x2d63f50/d .functor OR 1, L_0x2d63fc0, L_0x2d64120, C4<0>, C4<0>; +L_0x2d63f50 .delay 1 (30000,30000,30000) L_0x2d63f50/d; +L_0x2d64350/d .functor OR 1, L_0x2d64460, L_0x2d645c0, C4<0>, C4<0>; +L_0x2d64350 .delay 1 (30000,30000,30000) L_0x2d64350/d; +L_0x2d64740/d .functor OR 1, L_0x2d647b0, L_0x2d64960, C4<0>, C4<0>; +L_0x2d64740 .delay 1 (30000,30000,30000) L_0x2d64740/d; +v0x2b5ed60_0 .net *"_s0", 0 0, L_0x2d63f50; 1 drivers +v0x2b5ee60_0 .net *"_s10", 0 0, L_0x2d64460; 1 drivers +v0x2b5ef40_0 .net *"_s12", 0 0, L_0x2d645c0; 1 drivers +v0x2b5f000_0 .net *"_s14", 0 0, L_0x2d647b0; 1 drivers +v0x2b5f0e0_0 .net *"_s16", 0 0, L_0x2d64960; 1 drivers +v0x2b5f210_0 .net *"_s3", 0 0, L_0x2d63fc0; 1 drivers +v0x2b5f2f0_0 .net *"_s5", 0 0, L_0x2d64120; 1 drivers +v0x2b5f3d0_0 .net *"_s6", 0 0, L_0x2d64350; 1 drivers +v0x2b5f4b0_0 .net "in", 3 0, L_0x2d64b90; 1 drivers +v0x2b5f620_0 .net "ors", 1 0, L_0x2d64260; 1 drivers +v0x2b5f700_0 .net "out", 0 0, L_0x2d64740; 1 drivers +L_0x2d63fc0 .part L_0x2d64b90, 0, 1; +L_0x2d64120 .part L_0x2d64b90, 1, 1; +L_0x2d64260 .concat8 [ 1 1 0 0], L_0x2d63f50, L_0x2d64350; +L_0x2d64460 .part L_0x2d64b90, 2, 1; +L_0x2d645c0 .part L_0x2d64b90, 3, 1; +L_0x2d647b0 .part L_0x2d64260, 0, 1; +L_0x2d64960 .part L_0x2d64260, 1, 1; +S_0x2b60010 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b53980; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -7046,80 +7451,80 @@ S_0x1093760 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10870e0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1279d50/d .functor XNOR 1, L_0x1282420, L_0x1282580, C4<0>, C4<0>; -L_0x1279d50 .delay 1 (20000,20000,20000) L_0x1279d50/d; -L_0x1279fc0/d .functor AND 1, L_0x1282420, L_0x1278d50, C4<1>, C4<1>; -L_0x1279fc0 .delay 1 (30000,30000,30000) L_0x1279fc0/d; -L_0x127a030/d .functor AND 1, L_0x1279d50, L_0x1278b30, C4<1>, C4<1>; -L_0x127a030 .delay 1 (30000,30000,30000) L_0x127a030/d; -L_0x127a190/d .functor OR 1, L_0x127a030, L_0x1279fc0, C4<0>, C4<0>; -L_0x127a190 .delay 1 (30000,30000,30000) L_0x127a190/d; -v0x1093a10_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers -v0x1093b00_0 .net "a_", 0 0, L_0x1278a10; alias, 1 drivers -v0x1093bc0_0 .net "b", 0 0, L_0x1282580; alias, 1 drivers -v0x1093cb0_0 .net "b_", 0 0, L_0x1278d50; alias, 1 drivers -v0x1093d50_0 .net "carryin", 0 0, L_0x1278b30; alias, 1 drivers -v0x1093e90_0 .net "eq", 0 0, L_0x1279d50; 1 drivers -v0x1093f50_0 .net "lt", 0 0, L_0x1279fc0; 1 drivers -v0x1094010_0 .net "out", 0 0, L_0x127a190; 1 drivers -v0x10940d0_0 .net "w0", 0 0, L_0x127a030; 1 drivers -S_0x1094320 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10870e0; +L_0x2d5fa60/d .functor XNOR 1, L_0x2d68ad0, L_0x2d68c30, C4<0>, C4<0>; +L_0x2d5fa60 .delay 1 (20000,20000,20000) L_0x2d5fa60/d; +L_0x2d5fbe0/d .functor AND 1, L_0x2d68ad0, L_0x2d5e750, C4<1>, C4<1>; +L_0x2d5fbe0 .delay 1 (30000,30000,30000) L_0x2d5fbe0/d; +L_0x2d5fd40/d .functor AND 1, L_0x2d5fa60, L_0x2d5e580, C4<1>, C4<1>; +L_0x2d5fd40 .delay 1 (30000,30000,30000) L_0x2d5fd40/d; +L_0x2d5fe50/d .functor OR 1, L_0x2d5fd40, L_0x2d5fbe0, C4<0>, C4<0>; +L_0x2d5fe50 .delay 1 (30000,30000,30000) L_0x2d5fe50/d; +v0x2b602c0_0 .net "a", 0 0, L_0x2d68ad0; alias, 1 drivers +v0x2b603b0_0 .net "a_", 0 0, L_0x2d5e460; alias, 1 drivers +v0x2b60470_0 .net "b", 0 0, L_0x2d68c30; alias, 1 drivers +v0x2b60560_0 .net "b_", 0 0, L_0x2d5e750; alias, 1 drivers +v0x2b60600_0 .net "carryin", 0 0, L_0x2d5e580; alias, 1 drivers +v0x2b60740_0 .net "eq", 0 0, L_0x2d5fa60; 1 drivers +v0x2b60800_0 .net "lt", 0 0, L_0x2d5fbe0; 1 drivers +v0x2b608c0_0 .net "out", 0 0, L_0x2d5fe50; 1 drivers +v0x2b60980_0 .net "w0", 0 0, L_0x2d5fd40; 1 drivers +S_0x2b60bd0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b53980; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1279b30/d .functor OR 1, L_0x1279680, L_0x1095580, C4<0>, C4<0>; -L_0x1279b30 .delay 1 (30000,30000,30000) L_0x1279b30/d; -v0x1095110_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers -v0x1095260_0 .net "b", 0 0, L_0x1278d50; alias, 1 drivers -v0x1095320_0 .net "c1", 0 0, L_0x1279680; 1 drivers -v0x10953c0_0 .net "c2", 0 0, L_0x1095580; 1 drivers -v0x1095490_0 .net "carryin", 0 0, L_0x1278b30; alias, 1 drivers -v0x1095610_0 .net "carryout", 0 0, L_0x1279b30; 1 drivers -v0x10956b0_0 .net "s1", 0 0, L_0x12795c0; 1 drivers -v0x1095750_0 .net "sum", 0 0, L_0x12797e0; 1 drivers -S_0x1094570 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1094320; +L_0x2d5f640/d .functor OR 1, L_0x2d5f140, L_0x2b61e30, C4<0>, C4<0>; +L_0x2d5f640 .delay 1 (30000,30000,30000) L_0x2d5f640/d; +v0x2b619c0_0 .net "a", 0 0, L_0x2d68ad0; alias, 1 drivers +v0x2b61b10_0 .net "b", 0 0, L_0x2d5e750; alias, 1 drivers +v0x2b61bd0_0 .net "c1", 0 0, L_0x2d5f140; 1 drivers +v0x2b61c70_0 .net "c2", 0 0, L_0x2b61e30; 1 drivers +v0x2b61d40_0 .net "carryin", 0 0, L_0x2d5e580; alias, 1 drivers +v0x2b61ec0_0 .net "carryout", 0 0, L_0x2d5f640; 1 drivers +v0x2b61f60_0 .net "s1", 0 0, L_0x2d5f080; 1 drivers +v0x2b62000_0 .net "sum", 0 0, L_0x2d5f2a0; 1 drivers +S_0x2b60e20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b60bd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12795c0/d .functor XOR 1, L_0x1282420, L_0x1278d50, C4<0>, C4<0>; -L_0x12795c0 .delay 1 (30000,30000,30000) L_0x12795c0/d; -L_0x1279680/d .functor AND 1, L_0x1282420, L_0x1278d50, C4<1>, C4<1>; -L_0x1279680 .delay 1 (30000,30000,30000) L_0x1279680/d; -v0x10947d0_0 .net "a", 0 0, L_0x1282420; alias, 1 drivers -v0x1094890_0 .net "b", 0 0, L_0x1278d50; alias, 1 drivers -v0x1094950_0 .net "carryout", 0 0, L_0x1279680; alias, 1 drivers -v0x10949f0_0 .net "sum", 0 0, L_0x12795c0; alias, 1 drivers -S_0x1094b20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1094320; +L_0x2d5f080/d .functor XOR 1, L_0x2d68ad0, L_0x2d5e750, C4<0>, C4<0>; +L_0x2d5f080 .delay 1 (30000,30000,30000) L_0x2d5f080/d; +L_0x2d5f140/d .functor AND 1, L_0x2d68ad0, L_0x2d5e750, C4<1>, C4<1>; +L_0x2d5f140 .delay 1 (30000,30000,30000) L_0x2d5f140/d; +v0x2b61080_0 .net "a", 0 0, L_0x2d68ad0; alias, 1 drivers +v0x2b61140_0 .net "b", 0 0, L_0x2d5e750; alias, 1 drivers +v0x2b61200_0 .net "carryout", 0 0, L_0x2d5f140; alias, 1 drivers +v0x2b612a0_0 .net "sum", 0 0, L_0x2d5f080; alias, 1 drivers +S_0x2b613d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b60bd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12797e0/d .functor XOR 1, L_0x12795c0, L_0x1278b30, C4<0>, C4<0>; -L_0x12797e0 .delay 1 (30000,30000,30000) L_0x12797e0/d; -L_0x1095580/d .functor AND 1, L_0x12795c0, L_0x1278b30, C4<1>, C4<1>; -L_0x1095580 .delay 1 (30000,30000,30000) L_0x1095580/d; -v0x1094d80_0 .net "a", 0 0, L_0x12795c0; alias, 1 drivers -v0x1094e50_0 .net "b", 0 0, L_0x1278b30; alias, 1 drivers -v0x1094ef0_0 .net "carryout", 0 0, L_0x1095580; alias, 1 drivers -v0x1094fc0_0 .net "sum", 0 0, L_0x12797e0; alias, 1 drivers -S_0x1096fe0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1086e10; - .timescale -9 -12; -L_0x2b0ab3d05d98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05de0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12824c0/d .functor OR 1, L_0x2b0ab3d05d98, L_0x2b0ab3d05de0, C4<0>, C4<0>; -L_0x12824c0 .delay 1 (30000,30000,30000) L_0x12824c0/d; -v0x1097160_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05d98; 1 drivers -v0x1097200_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05de0; 1 drivers -S_0x10972c0 .scope generate, "alu_slices[13]" "alu_slices[13]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x10974d0 .param/l "i" 0 3 41, +C4<01101>; -S_0x1097590 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10972c0; +L_0x2d5f2a0/d .functor XOR 1, L_0x2d5f080, L_0x2d5e580, C4<0>, C4<0>; +L_0x2d5f2a0 .delay 1 (30000,30000,30000) L_0x2d5f2a0/d; +L_0x2b61e30/d .functor AND 1, L_0x2d5f080, L_0x2d5e580, C4<1>, C4<1>; +L_0x2b61e30 .delay 1 (30000,30000,30000) L_0x2b61e30/d; +v0x2b61630_0 .net "a", 0 0, L_0x2d5f080; alias, 1 drivers +v0x2b61700_0 .net "b", 0 0, L_0x2d5e580; alias, 1 drivers +v0x2b617a0_0 .net "carryout", 0 0, L_0x2b61e30; alias, 1 drivers +v0x2b61870_0 .net "sum", 0 0, L_0x2d5f2a0; alias, 1 drivers +S_0x2b64440 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b536b0; + .timescale -9 -12; +L_0x2ac6110b9228 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9270 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d60ef0/d .functor OR 1, L_0x2ac6110b9228, L_0x2ac6110b9270, C4<0>, C4<0>; +L_0x2d60ef0 .delay 1 (30000,30000,30000) L_0x2d60ef0/d; +v0x2b64630_0 .net/2u *"_s0", 0 0, L_0x2ac6110b9228; 1 drivers +v0x2b64710_0 .net/2u *"_s2", 0 0, L_0x2ac6110b9270; 1 drivers +S_0x2b647f0 .scope generate, "alu_slices[13]" "alu_slices[13]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b64a00 .param/l "i" 0 3 39, +C4<01101>; +S_0x2b64ac0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b647f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -7128,445 +7533,476 @@ S_0x1097590 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10972c0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1282800/d .functor NOT 1, L_0x128c030, C4<0>, C4<0>, C4<0>; -L_0x1282800 .delay 1 (10000,10000,10000) L_0x1282800/d; -L_0x1282960/d .functor NOT 1, L_0x1282620, C4<0>, C4<0>, C4<0>; -L_0x1282960 .delay 1 (10000,10000,10000) L_0x1282960/d; -L_0x12838a0/d .functor XOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; -L_0x12838a0 .delay 1 (30000,30000,30000) L_0x12838a0/d; -L_0x2b0ab3d05e28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05e70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1283f50/d .functor OR 1, L_0x2b0ab3d05e28, L_0x2b0ab3d05e70, C4<0>, C4<0>; -L_0x1283f50 .delay 1 (30000,30000,30000) L_0x1283f50/d; -L_0x1284150/d .functor AND 1, L_0x128c030, L_0x1282620, C4<1>, C4<1>; -L_0x1284150 .delay 1 (30000,30000,30000) L_0x1284150/d; -L_0x1284210/d .functor NAND 1, L_0x128c030, L_0x1282620, C4<1>, C4<1>; -L_0x1284210 .delay 1 (20000,20000,20000) L_0x1284210/d; -L_0x1284370/d .functor XOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; -L_0x1284370 .delay 1 (20000,20000,20000) L_0x1284370/d; -L_0x1284820/d .functor OR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; -L_0x1284820 .delay 1 (30000,30000,30000) L_0x1284820/d; -L_0x128bf30/d .functor NOT 1, L_0x1288190, C4<0>, C4<0>, C4<0>; -L_0x128bf30 .delay 1 (10000,10000,10000) L_0x128bf30/d; -v0x10a5d50_0 .net "A", 0 0, L_0x128c030; 1 drivers -v0x10a5e10_0 .net "A_", 0 0, L_0x1282800; 1 drivers -v0x10a5ed0_0 .net "B", 0 0, L_0x1282620; 1 drivers -v0x10a5fa0_0 .net "B_", 0 0, L_0x1282960; 1 drivers -v0x10a6040_0 .net *"_s12", 0 0, L_0x1283f50; 1 drivers -v0x10a6130_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05e28; 1 drivers -v0x10a61d0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05e70; 1 drivers -v0x10a6290_0 .net *"_s18", 0 0, L_0x1284150; 1 drivers -v0x10a6370_0 .net *"_s20", 0 0, L_0x1284210; 1 drivers -v0x10a64e0_0 .net *"_s22", 0 0, L_0x1284370; 1 drivers -v0x10a65c0_0 .net *"_s24", 0 0, L_0x1284820; 1 drivers -o0x2b0ab3cc37d8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10a66a0_0 name=_s30 -o0x2b0ab3cc3808 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10a6780_0 name=_s32 -v0x10a6860_0 .net *"_s8", 0 0, L_0x12838a0; 1 drivers -v0x10a6940_0 .net "carryin", 0 0, L_0x12826c0; 1 drivers -v0x10a69e0_0 .net "carryout", 0 0, L_0x128bbd0; 1 drivers -v0x10a6a80_0 .net "carryouts", 7 0, L_0x13543b0; 1 drivers -v0x10a6c30_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10a6cd0_0 .net "result", 0 0, L_0x1288190; 1 drivers -v0x10a6dc0_0 .net "results", 7 0, L_0x12845f0; 1 drivers -v0x10a6ed0_0 .net "zero", 0 0, L_0x128bf30; 1 drivers -LS_0x12845f0_0_0 .concat8 [ 1 1 1 1], L_0x1282dc0, L_0x12833f0, L_0x12838a0, L_0x1283f50; -LS_0x12845f0_0_4 .concat8 [ 1 1 1 1], L_0x1284150, L_0x1284210, L_0x1284370, L_0x1284820; -L_0x12845f0 .concat8 [ 4 4 0 0], LS_0x12845f0_0_0, LS_0x12845f0_0_4; -LS_0x13543b0_0_0 .concat [ 1 1 1 1], L_0x1283070, L_0x1283740, o0x2b0ab3cc37d8, L_0x1283da0; -LS_0x13543b0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc3808; -L_0x13543b0 .concat [ 4 4 0 0], LS_0x13543b0_0_0, LS_0x13543b0_0_4; -S_0x1097810 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1097590; +L_0x2d68eb0/d .functor NOT 1, L_0x2d73370, C4<0>, C4<0>, C4<0>; +L_0x2d68eb0 .delay 1 (10000,10000,10000) L_0x2d68eb0/d; +L_0x2d68fc0/d .functor NOT 1, L_0x2d68cd0, C4<0>, C4<0>, C4<0>; +L_0x2d68fc0 .delay 1 (10000,10000,10000) L_0x2d68fc0/d; +L_0x2d6a010/d .functor XOR 1, L_0x2d73370, L_0x2d68cd0, C4<0>, C4<0>; +L_0x2d6a010 .delay 1 (30000,30000,30000) L_0x2d6a010/d; +L_0x2ac6110b92b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9300 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d6a0d0/d .functor OR 1, L_0x2ac6110b92b8, L_0x2ac6110b9300, C4<0>, C4<0>; +L_0x2d6a0d0 .delay 1 (30000,30000,30000) L_0x2d6a0d0/d; +L_0x2ac6110b9348 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9390 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d6a870/d .functor OR 1, L_0x2ac6110b9348, L_0x2ac6110b9390, C4<0>, C4<0>; +L_0x2d6a870 .delay 1 (30000,30000,30000) L_0x2d6a870/d; +L_0x2d6aa70/d .functor AND 1, L_0x2d73370, L_0x2d68cd0, C4<1>, C4<1>; +L_0x2d6aa70 .delay 1 (30000,30000,30000) L_0x2d6aa70/d; +L_0x2ac6110b93d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9420 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d6ab30/d .functor OR 1, L_0x2ac6110b93d8, L_0x2ac6110b9420, C4<0>, C4<0>; +L_0x2d6ab30 .delay 1 (30000,30000,30000) L_0x2d6ab30/d; +L_0x2d6ad30/d .functor NAND 1, L_0x2d73370, L_0x2d68cd0, C4<1>, C4<1>; +L_0x2d6ad30 .delay 1 (20000,20000,20000) L_0x2d6ad30/d; +L_0x2ac6110b9468 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b94b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d6ae40/d .functor OR 1, L_0x2ac6110b9468, L_0x2ac6110b94b0, C4<0>, C4<0>; +L_0x2d6ae40 .delay 1 (30000,30000,30000) L_0x2d6ae40/d; +L_0x2d6aff0/d .functor NOR 1, L_0x2d73370, L_0x2d68cd0, C4<0>, C4<0>; +L_0x2d6aff0 .delay 1 (20000,20000,20000) L_0x2d6aff0/d; +L_0x2ac6110b94f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9540 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d6b270/d .functor OR 1, L_0x2ac6110b94f8, L_0x2ac6110b9540, C4<0>, C4<0>; +L_0x2d6b270 .delay 1 (30000,30000,30000) L_0x2d6b270/d; +L_0x2d6b670/d .functor OR 1, L_0x2d73370, L_0x2d68cd0, C4<0>, C4<0>; +L_0x2d6b670 .delay 1 (30000,30000,30000) L_0x2d6b670/d; +L_0x2ac6110b9588 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b95d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d6bb10/d .functor OR 1, L_0x2ac6110b9588, L_0x2ac6110b95d0, C4<0>, C4<0>; +L_0x2d6bb10 .delay 1 (30000,30000,30000) L_0x2d6bb10/d; +L_0x2d73270/d .functor NOT 1, L_0x2d6f4d0, C4<0>, C4<0>, C4<0>; +L_0x2d73270 .delay 1 (10000,10000,10000) L_0x2d73270/d; +v0x2b73280_0 .net "A", 0 0, L_0x2d73370; 1 drivers +v0x2b73340_0 .net "A_", 0 0, L_0x2d68eb0; 1 drivers +v0x2b73400_0 .net "B", 0 0, L_0x2d68cd0; 1 drivers +v0x2b734d0_0 .net "B_", 0 0, L_0x2d68fc0; 1 drivers +v0x2b73570_0 .net *"_s11", 0 0, L_0x2d6a0d0; 1 drivers +v0x2b73660_0 .net/2s *"_s13", 0 0, L_0x2ac6110b92b8; 1 drivers +v0x2b73720_0 .net/2s *"_s15", 0 0, L_0x2ac6110b9300; 1 drivers +v0x2b73800_0 .net *"_s19", 0 0, L_0x2d6a870; 1 drivers +v0x2b738e0_0 .net/2s *"_s21", 0 0, L_0x2ac6110b9348; 1 drivers +v0x2b73a50_0 .net/2s *"_s23", 0 0, L_0x2ac6110b9390; 1 drivers +v0x2b73b30_0 .net *"_s25", 0 0, L_0x2d6aa70; 1 drivers +v0x2b73c10_0 .net *"_s28", 0 0, L_0x2d6ab30; 1 drivers +v0x2b73cf0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b93d8; 1 drivers +v0x2b73dd0_0 .net/2s *"_s32", 0 0, L_0x2ac6110b9420; 1 drivers +v0x2b73eb0_0 .net *"_s34", 0 0, L_0x2d6ad30; 1 drivers +v0x2b73f90_0 .net *"_s37", 0 0, L_0x2d6ae40; 1 drivers +v0x2b74070_0 .net/2s *"_s39", 0 0, L_0x2ac6110b9468; 1 drivers +v0x2b74220_0 .net/2s *"_s41", 0 0, L_0x2ac6110b94b0; 1 drivers +v0x2b742c0_0 .net *"_s43", 0 0, L_0x2d6aff0; 1 drivers +v0x2b743a0_0 .net *"_s46", 0 0, L_0x2d6b270; 1 drivers +v0x2b74480_0 .net/2s *"_s48", 0 0, L_0x2ac6110b94f8; 1 drivers +v0x2b74560_0 .net/2s *"_s50", 0 0, L_0x2ac6110b9540; 1 drivers +v0x2b74640_0 .net *"_s52", 0 0, L_0x2d6b670; 1 drivers +v0x2b74720_0 .net *"_s56", 0 0, L_0x2d6bb10; 1 drivers +v0x2b74800_0 .net/2s *"_s59", 0 0, L_0x2ac6110b9588; 1 drivers +v0x2b748e0_0 .net/2s *"_s61", 0 0, L_0x2ac6110b95d0; 1 drivers +v0x2b749c0_0 .net *"_s8", 0 0, L_0x2d6a010; 1 drivers +v0x2b74aa0_0 .net "carryin", 0 0, L_0x2d68d70; 1 drivers +v0x2b74b40_0 .net "carryout", 0 0, L_0x2d72f10; 1 drivers +v0x2b74be0_0 .net "carryouts", 7 0, L_0x2d6b780; 1 drivers +v0x2b74cf0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b74db0_0 .net "result", 0 0, L_0x2d6f4d0; 1 drivers +v0x2b74ea0_0 .net "results", 7 0, L_0x2d6b440; 1 drivers +v0x2b74180_0 .net "zero", 0 0, L_0x2d73270; 1 drivers +LS_0x2d6b440_0_0 .concat8 [ 1 1 1 1], L_0x2d694e0, L_0x2d69b10, L_0x2d6a010, L_0x2d6a870; +LS_0x2d6b440_0_4 .concat8 [ 1 1 1 1], L_0x2d6aa70, L_0x2d6ad30, L_0x2d6aff0, L_0x2d6b670; +L_0x2d6b440 .concat8 [ 4 4 0 0], LS_0x2d6b440_0_0, LS_0x2d6b440_0_4; +LS_0x2d6b780_0_0 .concat8 [ 1 1 1 1], L_0x2d69790, L_0x2d69eb0, L_0x2d6a0d0, L_0x2d6a6c0; +LS_0x2d6b780_0_4 .concat8 [ 1 1 1 1], L_0x2d6ab30, L_0x2d6ae40, L_0x2d6b270, L_0x2d6bb10; +L_0x2d6b780 .concat8 [ 4 4 0 0], LS_0x2d6b780_0_0, LS_0x2d6b780_0_4; +S_0x2b64d40 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b64ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1283070/d .functor OR 1, L_0x1282b50, L_0x1282f10, C4<0>, C4<0>; -L_0x1283070 .delay 1 (30000,30000,30000) L_0x1283070/d; -v0x10986d0_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers -v0x1098790_0 .net "b", 0 0, L_0x1282620; alias, 1 drivers -v0x1098860_0 .net "c1", 0 0, L_0x1282b50; 1 drivers -v0x1098960_0 .net "c2", 0 0, L_0x1282f10; 1 drivers -v0x1098a30_0 .net "carryin", 0 0, L_0x12826c0; alias, 1 drivers -v0x1098b20_0 .net "carryout", 0 0, L_0x1283070; 1 drivers -v0x1098bc0_0 .net "s1", 0 0, L_0x127c500; 1 drivers -v0x1098cb0_0 .net "sum", 0 0, L_0x1282dc0; 1 drivers -S_0x1097a80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1097810; +L_0x2d69790/d .functor OR 1, L_0x2d69270, L_0x2d69630, C4<0>, C4<0>; +L_0x2d69790 .delay 1 (30000,30000,30000) L_0x2d69790/d; +v0x2b65c00_0 .net "a", 0 0, L_0x2d73370; alias, 1 drivers +v0x2b65cc0_0 .net "b", 0 0, L_0x2d68cd0; alias, 1 drivers +v0x2b65d90_0 .net "c1", 0 0, L_0x2d69270; 1 drivers +v0x2b65e90_0 .net "c2", 0 0, L_0x2d69630; 1 drivers +v0x2b65f60_0 .net "carryin", 0 0, L_0x2d68d70; alias, 1 drivers +v0x2b66050_0 .net "carryout", 0 0, L_0x2d69790; 1 drivers +v0x2b660f0_0 .net "s1", 0 0, L_0x2d691b0; 1 drivers +v0x2b661e0_0 .net "sum", 0 0, L_0x2d694e0; 1 drivers +S_0x2b64fb0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b64d40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x127c500/d .functor XOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; -L_0x127c500 .delay 1 (30000,30000,30000) L_0x127c500/d; -L_0x1282b50/d .functor AND 1, L_0x128c030, L_0x1282620, C4<1>, C4<1>; -L_0x1282b50 .delay 1 (30000,30000,30000) L_0x1282b50/d; -v0x1097ce0_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers -v0x1097dc0_0 .net "b", 0 0, L_0x1282620; alias, 1 drivers -v0x1097e80_0 .net "carryout", 0 0, L_0x1282b50; alias, 1 drivers -v0x1097f50_0 .net "sum", 0 0, L_0x127c500; alias, 1 drivers -S_0x10980c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1097810; +L_0x2d691b0/d .functor XOR 1, L_0x2d73370, L_0x2d68cd0, C4<0>, C4<0>; +L_0x2d691b0 .delay 1 (30000,30000,30000) L_0x2d691b0/d; +L_0x2d69270/d .functor AND 1, L_0x2d73370, L_0x2d68cd0, C4<1>, C4<1>; +L_0x2d69270 .delay 1 (30000,30000,30000) L_0x2d69270/d; +v0x2b65210_0 .net "a", 0 0, L_0x2d73370; alias, 1 drivers +v0x2b652f0_0 .net "b", 0 0, L_0x2d68cd0; alias, 1 drivers +v0x2b653b0_0 .net "carryout", 0 0, L_0x2d69270; alias, 1 drivers +v0x2b65480_0 .net "sum", 0 0, L_0x2d691b0; alias, 1 drivers +S_0x2b655f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b64d40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1282dc0/d .functor XOR 1, L_0x127c500, L_0x12826c0, C4<0>, C4<0>; -L_0x1282dc0 .delay 1 (30000,30000,30000) L_0x1282dc0/d; -L_0x1282f10/d .functor AND 1, L_0x127c500, L_0x12826c0, C4<1>, C4<1>; -L_0x1282f10 .delay 1 (30000,30000,30000) L_0x1282f10/d; -v0x1098320_0 .net "a", 0 0, L_0x127c500; alias, 1 drivers -v0x10983f0_0 .net "b", 0 0, L_0x12826c0; alias, 1 drivers -v0x1098490_0 .net "carryout", 0 0, L_0x1282f10; alias, 1 drivers -v0x1098560_0 .net "sum", 0 0, L_0x1282dc0; alias, 1 drivers -S_0x1098d80 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1097590; +L_0x2d694e0/d .functor XOR 1, L_0x2d691b0, L_0x2d68d70, C4<0>, C4<0>; +L_0x2d694e0 .delay 1 (30000,30000,30000) L_0x2d694e0/d; +L_0x2d69630/d .functor AND 1, L_0x2d691b0, L_0x2d68d70, C4<1>, C4<1>; +L_0x2d69630 .delay 1 (30000,30000,30000) L_0x2d69630/d; +v0x2b65850_0 .net "a", 0 0, L_0x2d691b0; alias, 1 drivers +v0x2b65920_0 .net "b", 0 0, L_0x2d68d70; alias, 1 drivers +v0x2b659c0_0 .net "carryout", 0 0, L_0x2d69630; alias, 1 drivers +v0x2b65a90_0 .net "sum", 0 0, L_0x2d694e0; alias, 1 drivers +S_0x2b662b0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b64ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x109e170_0 .net "ands", 7 0, L_0x1289bd0; 1 drivers -v0x109e280_0 .net "in", 7 0, L_0x13543b0; alias, 1 drivers -v0x109e340_0 .net "out", 0 0, L_0x128bbd0; alias, 1 drivers -v0x109e410_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1098fa0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1098d80; +v0x2b6b6a0_0 .net "ands", 7 0, L_0x2d70f10; 1 drivers +v0x2b6b7b0_0 .net "in", 7 0, L_0x2d6b780; alias, 1 drivers +v0x2b6b870_0 .net "out", 0 0, L_0x2d72f10; alias, 1 drivers +v0x2b6b940_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b664d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b662b0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x109b6d0_0 .net "A", 7 0, L_0x13543b0; alias, 1 drivers -v0x109b7d0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x109b890_0 .net *"_s0", 0 0, L_0x12884f0; 1 drivers -v0x109b950_0 .net *"_s12", 0 0, L_0x1288e60; 1 drivers -v0x109ba30_0 .net *"_s16", 0 0, L_0x12891c0; 1 drivers -v0x109bb60_0 .net *"_s20", 0 0, L_0x12894d0; 1 drivers -v0x109bc40_0 .net *"_s24", 0 0, L_0x12898c0; 1 drivers -v0x109bd20_0 .net *"_s28", 0 0, L_0x1289850; 1 drivers -v0x109be00_0 .net *"_s4", 0 0, L_0x1288800; 1 drivers -v0x109bf70_0 .net *"_s8", 0 0, L_0x1288b50; 1 drivers -v0x109c050_0 .net "out", 7 0, L_0x1289bd0; alias, 1 drivers -L_0x12885b0 .part L_0x13543b0, 0, 1; -L_0x1288710 .part v0x12010b0_0, 0, 1; -L_0x12888c0 .part L_0x13543b0, 1, 1; -L_0x1288ab0 .part v0x12010b0_0, 1, 1; -L_0x1288c10 .part L_0x13543b0, 2, 1; -L_0x1288d70 .part v0x12010b0_0, 2, 1; -L_0x1288f20 .part L_0x13543b0, 3, 1; -L_0x1289080 .part v0x12010b0_0, 3, 1; -L_0x1289280 .part L_0x13543b0, 4, 1; -L_0x12893e0 .part v0x12010b0_0, 4, 1; -L_0x1289540 .part L_0x13543b0, 5, 1; -L_0x12897b0 .part v0x12010b0_0, 5, 1; -L_0x1289980 .part L_0x13543b0, 6, 1; -L_0x1289ae0 .part v0x12010b0_0, 6, 1; -LS_0x1289bd0_0_0 .concat8 [ 1 1 1 1], L_0x12884f0, L_0x1288800, L_0x1288b50, L_0x1288e60; -LS_0x1289bd0_0_4 .concat8 [ 1 1 1 1], L_0x12891c0, L_0x12894d0, L_0x12898c0, L_0x1289850; -L_0x1289bd0 .concat8 [ 4 4 0 0], LS_0x1289bd0_0_0, LS_0x1289bd0_0_4; -L_0x1289f90 .part L_0x13543b0, 7, 1; -L_0x128a180 .part v0x12010b0_0, 7, 1; -S_0x1099200 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x1099410 .param/l "i" 0 4 54, +C4<00>; -L_0x12884f0/d .functor AND 1, L_0x12885b0, L_0x1288710, C4<1>, C4<1>; -L_0x12884f0 .delay 1 (30000,30000,30000) L_0x12884f0/d; -v0x10994f0_0 .net *"_s0", 0 0, L_0x12885b0; 1 drivers -v0x10995d0_0 .net *"_s1", 0 0, L_0x1288710; 1 drivers -S_0x10996b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x10998c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1288800/d .functor AND 1, L_0x12888c0, L_0x1288ab0, C4<1>, C4<1>; -L_0x1288800 .delay 1 (30000,30000,30000) L_0x1288800/d; -v0x1099980_0 .net *"_s0", 0 0, L_0x12888c0; 1 drivers -v0x1099a60_0 .net *"_s1", 0 0, L_0x1288ab0; 1 drivers -S_0x1099b40 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x1099d50 .param/l "i" 0 4 54, +C4<010>; -L_0x1288b50/d .functor AND 1, L_0x1288c10, L_0x1288d70, C4<1>, C4<1>; -L_0x1288b50 .delay 1 (30000,30000,30000) L_0x1288b50/d; -v0x1099df0_0 .net *"_s0", 0 0, L_0x1288c10; 1 drivers -v0x1099ed0_0 .net *"_s1", 0 0, L_0x1288d70; 1 drivers -S_0x1099fb0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x109a1c0 .param/l "i" 0 4 54, +C4<011>; -L_0x1288e60/d .functor AND 1, L_0x1288f20, L_0x1289080, C4<1>, C4<1>; -L_0x1288e60 .delay 1 (30000,30000,30000) L_0x1288e60/d; -v0x109a280_0 .net *"_s0", 0 0, L_0x1288f20; 1 drivers -v0x109a360_0 .net *"_s1", 0 0, L_0x1289080; 1 drivers -S_0x109a440 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x109a6a0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12891c0/d .functor AND 1, L_0x1289280, L_0x12893e0, C4<1>, C4<1>; -L_0x12891c0 .delay 1 (30000,30000,30000) L_0x12891c0/d; -v0x109a760_0 .net *"_s0", 0 0, L_0x1289280; 1 drivers -v0x109a840_0 .net *"_s1", 0 0, L_0x12893e0; 1 drivers -S_0x109a920 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x109ab30 .param/l "i" 0 4 54, +C4<0101>; -L_0x12894d0/d .functor AND 1, L_0x1289540, L_0x12897b0, C4<1>, C4<1>; -L_0x12894d0 .delay 1 (30000,30000,30000) L_0x12894d0/d; -v0x109abf0_0 .net *"_s0", 0 0, L_0x1289540; 1 drivers -v0x109acd0_0 .net *"_s1", 0 0, L_0x12897b0; 1 drivers -S_0x109adb0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x109afc0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12898c0/d .functor AND 1, L_0x1289980, L_0x1289ae0, C4<1>, C4<1>; -L_0x12898c0 .delay 1 (30000,30000,30000) L_0x12898c0/d; -v0x109b080_0 .net *"_s0", 0 0, L_0x1289980; 1 drivers -v0x109b160_0 .net *"_s1", 0 0, L_0x1289ae0; 1 drivers -S_0x109b240 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1098fa0; - .timescale -9 -12; -P_0x109b450 .param/l "i" 0 4 54, +C4<0111>; -L_0x1289850/d .functor AND 1, L_0x1289f90, L_0x128a180, C4<1>, C4<1>; -L_0x1289850 .delay 1 (30000,30000,30000) L_0x1289850/d; -v0x109b510_0 .net *"_s0", 0 0, L_0x1289f90; 1 drivers -v0x109b5f0_0 .net *"_s1", 0 0, L_0x128a180; 1 drivers -S_0x109c1b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1098d80; +v0x2b68c00_0 .net "A", 7 0, L_0x2d6b780; alias, 1 drivers +v0x2b68d00_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b68dc0_0 .net *"_s0", 0 0, L_0x2d6f830; 1 drivers +v0x2b68e80_0 .net *"_s12", 0 0, L_0x2d701a0; 1 drivers +v0x2b68f60_0 .net *"_s16", 0 0, L_0x2d70500; 1 drivers +v0x2b69090_0 .net *"_s20", 0 0, L_0x2d708d0; 1 drivers +v0x2b69170_0 .net *"_s24", 0 0, L_0x2d70c00; 1 drivers +v0x2b69250_0 .net *"_s28", 0 0, L_0x2d70b90; 1 drivers +v0x2b69330_0 .net *"_s4", 0 0, L_0x2d6fb80; 1 drivers +v0x2b694a0_0 .net *"_s8", 0 0, L_0x2d6fe90; 1 drivers +v0x2b69580_0 .net "out", 7 0, L_0x2d70f10; alias, 1 drivers +L_0x2d6f8f0 .part L_0x2d6b780, 0, 1; +L_0x2d6fae0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d6fc40 .part L_0x2d6b780, 1, 1; +L_0x2d6fda0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d6ff50 .part L_0x2d6b780, 2, 1; +L_0x2d700b0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d70260 .part L_0x2d6b780, 3, 1; +L_0x2d703c0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d705c0 .part L_0x2d6b780, 4, 1; +L_0x2d70830 .part v0x2cdd2e0_0, 4, 1; +L_0x2d70940 .part L_0x2d6b780, 5, 1; +L_0x2d70aa0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d70cc0 .part L_0x2d6b780, 6, 1; +L_0x2d70e20 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d70f10_0_0 .concat8 [ 1 1 1 1], L_0x2d6f830, L_0x2d6fb80, L_0x2d6fe90, L_0x2d701a0; +LS_0x2d70f10_0_4 .concat8 [ 1 1 1 1], L_0x2d70500, L_0x2d708d0, L_0x2d70c00, L_0x2d70b90; +L_0x2d70f10 .concat8 [ 4 4 0 0], LS_0x2d70f10_0_0, LS_0x2d70f10_0_4; +L_0x2d712d0 .part L_0x2d6b780, 7, 1; +L_0x2d714c0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b66730 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b66940 .param/l "i" 0 4 54, +C4<00>; +L_0x2d6f830/d .functor AND 1, L_0x2d6f8f0, L_0x2d6fae0, C4<1>, C4<1>; +L_0x2d6f830 .delay 1 (30000,30000,30000) L_0x2d6f830/d; +v0x2b66a20_0 .net *"_s0", 0 0, L_0x2d6f8f0; 1 drivers +v0x2b66b00_0 .net *"_s1", 0 0, L_0x2d6fae0; 1 drivers +S_0x2b66be0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b66df0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d6fb80/d .functor AND 1, L_0x2d6fc40, L_0x2d6fda0, C4<1>, C4<1>; +L_0x2d6fb80 .delay 1 (30000,30000,30000) L_0x2d6fb80/d; +v0x2b66eb0_0 .net *"_s0", 0 0, L_0x2d6fc40; 1 drivers +v0x2b66f90_0 .net *"_s1", 0 0, L_0x2d6fda0; 1 drivers +S_0x2b67070 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b67280 .param/l "i" 0 4 54, +C4<010>; +L_0x2d6fe90/d .functor AND 1, L_0x2d6ff50, L_0x2d700b0, C4<1>, C4<1>; +L_0x2d6fe90 .delay 1 (30000,30000,30000) L_0x2d6fe90/d; +v0x2b67320_0 .net *"_s0", 0 0, L_0x2d6ff50; 1 drivers +v0x2b67400_0 .net *"_s1", 0 0, L_0x2d700b0; 1 drivers +S_0x2b674e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b676f0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d701a0/d .functor AND 1, L_0x2d70260, L_0x2d703c0, C4<1>, C4<1>; +L_0x2d701a0 .delay 1 (30000,30000,30000) L_0x2d701a0/d; +v0x2b677b0_0 .net *"_s0", 0 0, L_0x2d70260; 1 drivers +v0x2b67890_0 .net *"_s1", 0 0, L_0x2d703c0; 1 drivers +S_0x2b67970 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b67bd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d70500/d .functor AND 1, L_0x2d705c0, L_0x2d70830, C4<1>, C4<1>; +L_0x2d70500 .delay 1 (30000,30000,30000) L_0x2d70500/d; +v0x2b67c90_0 .net *"_s0", 0 0, L_0x2d705c0; 1 drivers +v0x2b67d70_0 .net *"_s1", 0 0, L_0x2d70830; 1 drivers +S_0x2b67e50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b68060 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d708d0/d .functor AND 1, L_0x2d70940, L_0x2d70aa0, C4<1>, C4<1>; +L_0x2d708d0 .delay 1 (30000,30000,30000) L_0x2d708d0/d; +v0x2b68120_0 .net *"_s0", 0 0, L_0x2d70940; 1 drivers +v0x2b68200_0 .net *"_s1", 0 0, L_0x2d70aa0; 1 drivers +S_0x2b682e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b684f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d70c00/d .functor AND 1, L_0x2d70cc0, L_0x2d70e20, C4<1>, C4<1>; +L_0x2d70c00 .delay 1 (30000,30000,30000) L_0x2d70c00/d; +v0x2b685b0_0 .net *"_s0", 0 0, L_0x2d70cc0; 1 drivers +v0x2b68690_0 .net *"_s1", 0 0, L_0x2d70e20; 1 drivers +S_0x2b68770 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b664d0; + .timescale -9 -12; +P_0x2b68980 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d70b90/d .functor AND 1, L_0x2d712d0, L_0x2d714c0, C4<1>, C4<1>; +L_0x2d70b90 .delay 1 (30000,30000,30000) L_0x2d70b90/d; +v0x2b68a40_0 .net *"_s0", 0 0, L_0x2d712d0; 1 drivers +v0x2b68b20_0 .net *"_s1", 0 0, L_0x2d714c0; 1 drivers +S_0x2b696e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b662b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x128bbd0/d .functor OR 1, L_0x128bc90, L_0x128be40, C4<0>, C4<0>; -L_0x128bbd0 .delay 1 (30000,30000,30000) L_0x128bbd0/d; -v0x109dd00_0 .net *"_s10", 0 0, L_0x128bc90; 1 drivers -v0x109dde0_0 .net *"_s12", 0 0, L_0x128be40; 1 drivers -v0x109dec0_0 .net "in", 7 0, L_0x1289bd0; alias, 1 drivers -v0x109df90_0 .net "ors", 1 0, L_0x128b9f0; 1 drivers -v0x109e050_0 .net "out", 0 0, L_0x128bbd0; alias, 1 drivers -L_0x128adc0 .part L_0x1289bd0, 0, 4; -L_0x128b9f0 .concat8 [ 1 1 0 0], L_0x128aab0, L_0x128b6e0; -L_0x128bb30 .part L_0x1289bd0, 4, 4; -L_0x128bc90 .part L_0x128b9f0, 0, 1; -L_0x128be40 .part L_0x128b9f0, 1, 1; -S_0x109c370 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x109c1b0; +L_0x2d72f10/d .functor OR 1, L_0x2d72fd0, L_0x2d73180, C4<0>, C4<0>; +L_0x2d72f10 .delay 1 (30000,30000,30000) L_0x2d72f10/d; +v0x2b6b230_0 .net *"_s10", 0 0, L_0x2d72fd0; 1 drivers +v0x2b6b310_0 .net *"_s12", 0 0, L_0x2d73180; 1 drivers +v0x2b6b3f0_0 .net "in", 7 0, L_0x2d70f10; alias, 1 drivers +v0x2b6b4c0_0 .net "ors", 1 0, L_0x2d72d30; 1 drivers +v0x2b6b580_0 .net "out", 0 0, L_0x2d72f10; alias, 1 drivers +L_0x2d72100 .part L_0x2d70f10, 0, 4; +L_0x2d72d30 .concat8 [ 1 1 0 0], L_0x2d71df0, L_0x2d72a20; +L_0x2d72e70 .part L_0x2d70f10, 4, 4; +L_0x2d72fd0 .part L_0x2d72d30, 0, 1; +L_0x2d73180 .part L_0x2d72d30, 1, 1; +S_0x2b698a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b696e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x128a270/d .functor OR 1, L_0x128a330, L_0x128a490, C4<0>, C4<0>; -L_0x128a270 .delay 1 (30000,30000,30000) L_0x128a270/d; -L_0x128a6c0/d .functor OR 1, L_0x128a7d0, L_0x128a930, C4<0>, C4<0>; -L_0x128a6c0 .delay 1 (30000,30000,30000) L_0x128a6c0/d; -L_0x128aab0/d .functor OR 1, L_0x128ab20, L_0x128acd0, C4<0>, C4<0>; -L_0x128aab0 .delay 1 (30000,30000,30000) L_0x128aab0/d; -v0x109c5c0_0 .net *"_s0", 0 0, L_0x128a270; 1 drivers -v0x109c6c0_0 .net *"_s10", 0 0, L_0x128a7d0; 1 drivers -v0x109c7a0_0 .net *"_s12", 0 0, L_0x128a930; 1 drivers -v0x109c860_0 .net *"_s14", 0 0, L_0x128ab20; 1 drivers -v0x109c940_0 .net *"_s16", 0 0, L_0x128acd0; 1 drivers -v0x109ca70_0 .net *"_s3", 0 0, L_0x128a330; 1 drivers -v0x109cb50_0 .net *"_s5", 0 0, L_0x128a490; 1 drivers -v0x109cc30_0 .net *"_s6", 0 0, L_0x128a6c0; 1 drivers -v0x109cd10_0 .net "in", 3 0, L_0x128adc0; 1 drivers -v0x109ce80_0 .net "ors", 1 0, L_0x128a5d0; 1 drivers -v0x109cf60_0 .net "out", 0 0, L_0x128aab0; 1 drivers -L_0x128a330 .part L_0x128adc0, 0, 1; -L_0x128a490 .part L_0x128adc0, 1, 1; -L_0x128a5d0 .concat8 [ 1 1 0 0], L_0x128a270, L_0x128a6c0; -L_0x128a7d0 .part L_0x128adc0, 2, 1; -L_0x128a930 .part L_0x128adc0, 3, 1; -L_0x128ab20 .part L_0x128a5d0, 0, 1; -L_0x128acd0 .part L_0x128a5d0, 1, 1; -S_0x109d080 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x109c1b0; +L_0x2d715b0/d .functor OR 1, L_0x2d71670, L_0x2d717d0, C4<0>, C4<0>; +L_0x2d715b0 .delay 1 (30000,30000,30000) L_0x2d715b0/d; +L_0x2d71a00/d .functor OR 1, L_0x2d71b10, L_0x2d71c70, C4<0>, C4<0>; +L_0x2d71a00 .delay 1 (30000,30000,30000) L_0x2d71a00/d; +L_0x2d71df0/d .functor OR 1, L_0x2d71e60, L_0x2d72010, C4<0>, C4<0>; +L_0x2d71df0 .delay 1 (30000,30000,30000) L_0x2d71df0/d; +v0x2b69af0_0 .net *"_s0", 0 0, L_0x2d715b0; 1 drivers +v0x2b69bf0_0 .net *"_s10", 0 0, L_0x2d71b10; 1 drivers +v0x2b69cd0_0 .net *"_s12", 0 0, L_0x2d71c70; 1 drivers +v0x2b69d90_0 .net *"_s14", 0 0, L_0x2d71e60; 1 drivers +v0x2b69e70_0 .net *"_s16", 0 0, L_0x2d72010; 1 drivers +v0x2b69fa0_0 .net *"_s3", 0 0, L_0x2d71670; 1 drivers +v0x2b6a080_0 .net *"_s5", 0 0, L_0x2d717d0; 1 drivers +v0x2b6a160_0 .net *"_s6", 0 0, L_0x2d71a00; 1 drivers +v0x2b6a240_0 .net "in", 3 0, L_0x2d72100; 1 drivers +v0x2b6a3b0_0 .net "ors", 1 0, L_0x2d71910; 1 drivers +v0x2b6a490_0 .net "out", 0 0, L_0x2d71df0; 1 drivers +L_0x2d71670 .part L_0x2d72100, 0, 1; +L_0x2d717d0 .part L_0x2d72100, 1, 1; +L_0x2d71910 .concat8 [ 1 1 0 0], L_0x2d715b0, L_0x2d71a00; +L_0x2d71b10 .part L_0x2d72100, 2, 1; +L_0x2d71c70 .part L_0x2d72100, 3, 1; +L_0x2d71e60 .part L_0x2d71910, 0, 1; +L_0x2d72010 .part L_0x2d71910, 1, 1; +S_0x2b6a5b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b696e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x128aef0/d .functor OR 1, L_0x128af60, L_0x128b0c0, C4<0>, C4<0>; -L_0x128aef0 .delay 1 (30000,30000,30000) L_0x128aef0/d; -L_0x128b2f0/d .functor OR 1, L_0x128b400, L_0x128b560, C4<0>, C4<0>; -L_0x128b2f0 .delay 1 (30000,30000,30000) L_0x128b2f0/d; -L_0x128b6e0/d .functor OR 1, L_0x128b750, L_0x128b900, C4<0>, C4<0>; -L_0x128b6e0 .delay 1 (30000,30000,30000) L_0x128b6e0/d; -v0x109d240_0 .net *"_s0", 0 0, L_0x128aef0; 1 drivers -v0x109d340_0 .net *"_s10", 0 0, L_0x128b400; 1 drivers -v0x109d420_0 .net *"_s12", 0 0, L_0x128b560; 1 drivers -v0x109d4e0_0 .net *"_s14", 0 0, L_0x128b750; 1 drivers -v0x109d5c0_0 .net *"_s16", 0 0, L_0x128b900; 1 drivers -v0x109d6f0_0 .net *"_s3", 0 0, L_0x128af60; 1 drivers -v0x109d7d0_0 .net *"_s5", 0 0, L_0x128b0c0; 1 drivers -v0x109d8b0_0 .net *"_s6", 0 0, L_0x128b2f0; 1 drivers -v0x109d990_0 .net "in", 3 0, L_0x128bb30; 1 drivers -v0x109db00_0 .net "ors", 1 0, L_0x128b200; 1 drivers -v0x109dbe0_0 .net "out", 0 0, L_0x128b6e0; 1 drivers -L_0x128af60 .part L_0x128bb30, 0, 1; -L_0x128b0c0 .part L_0x128bb30, 1, 1; -L_0x128b200 .concat8 [ 1 1 0 0], L_0x128aef0, L_0x128b2f0; -L_0x128b400 .part L_0x128bb30, 2, 1; -L_0x128b560 .part L_0x128bb30, 3, 1; -L_0x128b750 .part L_0x128b200, 0, 1; -L_0x128b900 .part L_0x128b200, 1, 1; -S_0x109e4f0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1097590; +L_0x2d72230/d .functor OR 1, L_0x2d722a0, L_0x2d72400, C4<0>, C4<0>; +L_0x2d72230 .delay 1 (30000,30000,30000) L_0x2d72230/d; +L_0x2d72630/d .functor OR 1, L_0x2d72740, L_0x2d728a0, C4<0>, C4<0>; +L_0x2d72630 .delay 1 (30000,30000,30000) L_0x2d72630/d; +L_0x2d72a20/d .functor OR 1, L_0x2d72a90, L_0x2d72c40, C4<0>, C4<0>; +L_0x2d72a20 .delay 1 (30000,30000,30000) L_0x2d72a20/d; +v0x2b6a770_0 .net *"_s0", 0 0, L_0x2d72230; 1 drivers +v0x2b6a870_0 .net *"_s10", 0 0, L_0x2d72740; 1 drivers +v0x2b6a950_0 .net *"_s12", 0 0, L_0x2d728a0; 1 drivers +v0x2b6aa10_0 .net *"_s14", 0 0, L_0x2d72a90; 1 drivers +v0x2b6aaf0_0 .net *"_s16", 0 0, L_0x2d72c40; 1 drivers +v0x2b6ac20_0 .net *"_s3", 0 0, L_0x2d722a0; 1 drivers +v0x2b6ad00_0 .net *"_s5", 0 0, L_0x2d72400; 1 drivers +v0x2b6ade0_0 .net *"_s6", 0 0, L_0x2d72630; 1 drivers +v0x2b6aec0_0 .net "in", 3 0, L_0x2d72e70; 1 drivers +v0x2b6b030_0 .net "ors", 1 0, L_0x2d72540; 1 drivers +v0x2b6b110_0 .net "out", 0 0, L_0x2d72a20; 1 drivers +L_0x2d722a0 .part L_0x2d72e70, 0, 1; +L_0x2d72400 .part L_0x2d72e70, 1, 1; +L_0x2d72540 .concat8 [ 1 1 0 0], L_0x2d72230, L_0x2d72630; +L_0x2d72740 .part L_0x2d72e70, 2, 1; +L_0x2d728a0 .part L_0x2d72e70, 3, 1; +L_0x2d72a90 .part L_0x2d72540, 0, 1; +L_0x2d72c40 .part L_0x2d72540, 1, 1; +S_0x2b6ba20 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b64ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10a3920_0 .net "ands", 7 0, L_0x1286190; 1 drivers -v0x10a3a30_0 .net "in", 7 0, L_0x12845f0; alias, 1 drivers -v0x10a3af0_0 .net "out", 0 0, L_0x1288190; alias, 1 drivers -v0x10a3bc0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x109e740 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x109e4f0; +v0x2b70e50_0 .net "ands", 7 0, L_0x2d6d4d0; 1 drivers +v0x2b70f60_0 .net "in", 7 0, L_0x2d6b440; alias, 1 drivers +v0x2b71020_0 .net "out", 0 0, L_0x2d6f4d0; alias, 1 drivers +v0x2b710f0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b6bc70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b6ba20; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10a0e80_0 .net "A", 7 0, L_0x12845f0; alias, 1 drivers -v0x10a0f80_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10a1040_0 .net *"_s0", 0 0, L_0x1284980; 1 drivers -v0x10a1100_0 .net *"_s12", 0 0, L_0x1285340; 1 drivers -v0x10a11e0_0 .net *"_s16", 0 0, L_0x12856a0; 1 drivers -v0x10a1310_0 .net *"_s20", 0 0, L_0x1285ad0; 1 drivers -v0x10a13f0_0 .net *"_s24", 0 0, L_0x1285e00; 1 drivers -v0x10a14d0_0 .net *"_s28", 0 0, L_0x1285d90; 1 drivers -v0x10a15b0_0 .net *"_s4", 0 0, L_0x1284d20; 1 drivers -v0x10a1720_0 .net *"_s8", 0 0, L_0x1285030; 1 drivers -v0x10a1800_0 .net "out", 7 0, L_0x1286190; alias, 1 drivers -L_0x1284a90 .part L_0x12845f0, 0, 1; -L_0x1284c80 .part v0x12010b0_0, 0, 1; -L_0x1284de0 .part L_0x12845f0, 1, 1; -L_0x1284f40 .part v0x12010b0_0, 1, 1; -L_0x12850f0 .part L_0x12845f0, 2, 1; -L_0x1285250 .part v0x12010b0_0, 2, 1; -L_0x1285400 .part L_0x12845f0, 3, 1; -L_0x1285560 .part v0x12010b0_0, 3, 1; -L_0x1285760 .part L_0x12845f0, 4, 1; -L_0x12859d0 .part v0x12010b0_0, 4, 1; -L_0x1285b40 .part L_0x12845f0, 5, 1; -L_0x1285ca0 .part v0x12010b0_0, 5, 1; -L_0x1285ec0 .part L_0x12845f0, 6, 1; -L_0x1286020 .part v0x12010b0_0, 6, 1; -LS_0x1286190_0_0 .concat8 [ 1 1 1 1], L_0x1284980, L_0x1284d20, L_0x1285030, L_0x1285340; -LS_0x1286190_0_4 .concat8 [ 1 1 1 1], L_0x12856a0, L_0x1285ad0, L_0x1285e00, L_0x1285d90; -L_0x1286190 .concat8 [ 4 4 0 0], LS_0x1286190_0_0, LS_0x1286190_0_4; -L_0x1286550 .part L_0x12845f0, 7, 1; -L_0x1286740 .part v0x12010b0_0, 7, 1; -S_0x109e980 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x109eb90 .param/l "i" 0 4 54, +C4<00>; -L_0x1284980/d .functor AND 1, L_0x1284a90, L_0x1284c80, C4<1>, C4<1>; -L_0x1284980 .delay 1 (30000,30000,30000) L_0x1284980/d; -v0x109ec70_0 .net *"_s0", 0 0, L_0x1284a90; 1 drivers -v0x109ed50_0 .net *"_s1", 0 0, L_0x1284c80; 1 drivers -S_0x109ee30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x109f040 .param/l "i" 0 4 54, +C4<01>; -L_0x1284d20/d .functor AND 1, L_0x1284de0, L_0x1284f40, C4<1>, C4<1>; -L_0x1284d20 .delay 1 (30000,30000,30000) L_0x1284d20/d; -v0x109f100_0 .net *"_s0", 0 0, L_0x1284de0; 1 drivers -v0x109f1e0_0 .net *"_s1", 0 0, L_0x1284f40; 1 drivers -S_0x109f2c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x109f500 .param/l "i" 0 4 54, +C4<010>; -L_0x1285030/d .functor AND 1, L_0x12850f0, L_0x1285250, C4<1>, C4<1>; -L_0x1285030 .delay 1 (30000,30000,30000) L_0x1285030/d; -v0x109f5a0_0 .net *"_s0", 0 0, L_0x12850f0; 1 drivers -v0x109f680_0 .net *"_s1", 0 0, L_0x1285250; 1 drivers -S_0x109f760 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x109f970 .param/l "i" 0 4 54, +C4<011>; -L_0x1285340/d .functor AND 1, L_0x1285400, L_0x1285560, C4<1>, C4<1>; -L_0x1285340 .delay 1 (30000,30000,30000) L_0x1285340/d; -v0x109fa30_0 .net *"_s0", 0 0, L_0x1285400; 1 drivers -v0x109fb10_0 .net *"_s1", 0 0, L_0x1285560; 1 drivers -S_0x109fbf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x109fe50 .param/l "i" 0 4 54, +C4<0100>; -L_0x12856a0/d .functor AND 1, L_0x1285760, L_0x12859d0, C4<1>, C4<1>; -L_0x12856a0 .delay 1 (30000,30000,30000) L_0x12856a0/d; -v0x109ff10_0 .net *"_s0", 0 0, L_0x1285760; 1 drivers -v0x109fff0_0 .net *"_s1", 0 0, L_0x12859d0; 1 drivers -S_0x10a00d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x10a02e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1285ad0/d .functor AND 1, L_0x1285b40, L_0x1285ca0, C4<1>, C4<1>; -L_0x1285ad0 .delay 1 (30000,30000,30000) L_0x1285ad0/d; -v0x10a03a0_0 .net *"_s0", 0 0, L_0x1285b40; 1 drivers -v0x10a0480_0 .net *"_s1", 0 0, L_0x1285ca0; 1 drivers -S_0x10a0560 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x10a0770 .param/l "i" 0 4 54, +C4<0110>; -L_0x1285e00/d .functor AND 1, L_0x1285ec0, L_0x1286020, C4<1>, C4<1>; -L_0x1285e00 .delay 1 (30000,30000,30000) L_0x1285e00/d; -v0x10a0830_0 .net *"_s0", 0 0, L_0x1285ec0; 1 drivers -v0x10a0910_0 .net *"_s1", 0 0, L_0x1286020; 1 drivers -S_0x10a09f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x109e740; - .timescale -9 -12; -P_0x10a0c00 .param/l "i" 0 4 54, +C4<0111>; -L_0x1285d90/d .functor AND 1, L_0x1286550, L_0x1286740, C4<1>, C4<1>; -L_0x1285d90 .delay 1 (30000,30000,30000) L_0x1285d90/d; -v0x10a0cc0_0 .net *"_s0", 0 0, L_0x1286550; 1 drivers -v0x10a0da0_0 .net *"_s1", 0 0, L_0x1286740; 1 drivers -S_0x10a1960 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x109e4f0; +v0x2b6e3b0_0 .net "A", 7 0, L_0x2d6b440; alias, 1 drivers +v0x2b6e4b0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b6e570_0 .net *"_s0", 0 0, L_0x2d6bcc0; 1 drivers +v0x2b6e630_0 .net *"_s12", 0 0, L_0x2d6c680; 1 drivers +v0x2b6e710_0 .net *"_s16", 0 0, L_0x2d6c9e0; 1 drivers +v0x2b6e840_0 .net *"_s20", 0 0, L_0x2d6ce10; 1 drivers +v0x2b6e920_0 .net *"_s24", 0 0, L_0x2d6d140; 1 drivers +v0x2b6ea00_0 .net *"_s28", 0 0, L_0x2d6d0d0; 1 drivers +v0x2b6eae0_0 .net *"_s4", 0 0, L_0x2d6c060; 1 drivers +v0x2b6ec50_0 .net *"_s8", 0 0, L_0x2d6c370; 1 drivers +v0x2b6ed30_0 .net "out", 7 0, L_0x2d6d4d0; alias, 1 drivers +L_0x2d6bdd0 .part L_0x2d6b440, 0, 1; +L_0x2d6bfc0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d6c120 .part L_0x2d6b440, 1, 1; +L_0x2d6c280 .part v0x2cdd2e0_0, 1, 1; +L_0x2d6c430 .part L_0x2d6b440, 2, 1; +L_0x2d6c590 .part v0x2cdd2e0_0, 2, 1; +L_0x2d6c740 .part L_0x2d6b440, 3, 1; +L_0x2d6c8a0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d6caa0 .part L_0x2d6b440, 4, 1; +L_0x2d6cd10 .part v0x2cdd2e0_0, 4, 1; +L_0x2d6ce80 .part L_0x2d6b440, 5, 1; +L_0x2d6cfe0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d6d200 .part L_0x2d6b440, 6, 1; +L_0x2d6d360 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d6d4d0_0_0 .concat8 [ 1 1 1 1], L_0x2d6bcc0, L_0x2d6c060, L_0x2d6c370, L_0x2d6c680; +LS_0x2d6d4d0_0_4 .concat8 [ 1 1 1 1], L_0x2d6c9e0, L_0x2d6ce10, L_0x2d6d140, L_0x2d6d0d0; +L_0x2d6d4d0 .concat8 [ 4 4 0 0], LS_0x2d6d4d0_0_0, LS_0x2d6d4d0_0_4; +L_0x2d6d890 .part L_0x2d6b440, 7, 1; +L_0x2d6da80 .part v0x2cdd2e0_0, 7, 1; +S_0x2b6beb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6c0c0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d6bcc0/d .functor AND 1, L_0x2d6bdd0, L_0x2d6bfc0, C4<1>, C4<1>; +L_0x2d6bcc0 .delay 1 (30000,30000,30000) L_0x2d6bcc0/d; +v0x2b6c1a0_0 .net *"_s0", 0 0, L_0x2d6bdd0; 1 drivers +v0x2b6c280_0 .net *"_s1", 0 0, L_0x2d6bfc0; 1 drivers +S_0x2b6c360 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6c570 .param/l "i" 0 4 54, +C4<01>; +L_0x2d6c060/d .functor AND 1, L_0x2d6c120, L_0x2d6c280, C4<1>, C4<1>; +L_0x2d6c060 .delay 1 (30000,30000,30000) L_0x2d6c060/d; +v0x2b6c630_0 .net *"_s0", 0 0, L_0x2d6c120; 1 drivers +v0x2b6c710_0 .net *"_s1", 0 0, L_0x2d6c280; 1 drivers +S_0x2b6c7f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6ca30 .param/l "i" 0 4 54, +C4<010>; +L_0x2d6c370/d .functor AND 1, L_0x2d6c430, L_0x2d6c590, C4<1>, C4<1>; +L_0x2d6c370 .delay 1 (30000,30000,30000) L_0x2d6c370/d; +v0x2b6cad0_0 .net *"_s0", 0 0, L_0x2d6c430; 1 drivers +v0x2b6cbb0_0 .net *"_s1", 0 0, L_0x2d6c590; 1 drivers +S_0x2b6cc90 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6cea0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d6c680/d .functor AND 1, L_0x2d6c740, L_0x2d6c8a0, C4<1>, C4<1>; +L_0x2d6c680 .delay 1 (30000,30000,30000) L_0x2d6c680/d; +v0x2b6cf60_0 .net *"_s0", 0 0, L_0x2d6c740; 1 drivers +v0x2b6d040_0 .net *"_s1", 0 0, L_0x2d6c8a0; 1 drivers +S_0x2b6d120 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6d380 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d6c9e0/d .functor AND 1, L_0x2d6caa0, L_0x2d6cd10, C4<1>, C4<1>; +L_0x2d6c9e0 .delay 1 (30000,30000,30000) L_0x2d6c9e0/d; +v0x2b6d440_0 .net *"_s0", 0 0, L_0x2d6caa0; 1 drivers +v0x2b6d520_0 .net *"_s1", 0 0, L_0x2d6cd10; 1 drivers +S_0x2b6d600 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6d810 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d6ce10/d .functor AND 1, L_0x2d6ce80, L_0x2d6cfe0, C4<1>, C4<1>; +L_0x2d6ce10 .delay 1 (30000,30000,30000) L_0x2d6ce10/d; +v0x2b6d8d0_0 .net *"_s0", 0 0, L_0x2d6ce80; 1 drivers +v0x2b6d9b0_0 .net *"_s1", 0 0, L_0x2d6cfe0; 1 drivers +S_0x2b6da90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6dca0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d6d140/d .functor AND 1, L_0x2d6d200, L_0x2d6d360, C4<1>, C4<1>; +L_0x2d6d140 .delay 1 (30000,30000,30000) L_0x2d6d140/d; +v0x2b6dd60_0 .net *"_s0", 0 0, L_0x2d6d200; 1 drivers +v0x2b6de40_0 .net *"_s1", 0 0, L_0x2d6d360; 1 drivers +S_0x2b6df20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b6bc70; + .timescale -9 -12; +P_0x2b6e130 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d6d0d0/d .functor AND 1, L_0x2d6d890, L_0x2d6da80, C4<1>, C4<1>; +L_0x2d6d0d0 .delay 1 (30000,30000,30000) L_0x2d6d0d0/d; +v0x2b6e1f0_0 .net *"_s0", 0 0, L_0x2d6d890; 1 drivers +v0x2b6e2d0_0 .net *"_s1", 0 0, L_0x2d6da80; 1 drivers +S_0x2b6ee90 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b6ba20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1288190/d .functor OR 1, L_0x1288250, L_0x1288400, C4<0>, C4<0>; -L_0x1288190 .delay 1 (30000,30000,30000) L_0x1288190/d; -v0x10a34b0_0 .net *"_s10", 0 0, L_0x1288250; 1 drivers -v0x10a3590_0 .net *"_s12", 0 0, L_0x1288400; 1 drivers -v0x10a3670_0 .net "in", 7 0, L_0x1286190; alias, 1 drivers -v0x10a3740_0 .net "ors", 1 0, L_0x1287fb0; 1 drivers -v0x10a3800_0 .net "out", 0 0, L_0x1288190; alias, 1 drivers -L_0x1287380 .part L_0x1286190, 0, 4; -L_0x1287fb0 .concat8 [ 1 1 0 0], L_0x1287070, L_0x1287ca0; -L_0x12880f0 .part L_0x1286190, 4, 4; -L_0x1288250 .part L_0x1287fb0, 0, 1; -L_0x1288400 .part L_0x1287fb0, 1, 1; -S_0x10a1b20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10a1960; +L_0x2d6f4d0/d .functor OR 1, L_0x2d6f590, L_0x2d6f740, C4<0>, C4<0>; +L_0x2d6f4d0 .delay 1 (30000,30000,30000) L_0x2d6f4d0/d; +v0x2b709e0_0 .net *"_s10", 0 0, L_0x2d6f590; 1 drivers +v0x2b70ac0_0 .net *"_s12", 0 0, L_0x2d6f740; 1 drivers +v0x2b70ba0_0 .net "in", 7 0, L_0x2d6d4d0; alias, 1 drivers +v0x2b70c70_0 .net "ors", 1 0, L_0x2d6f2f0; 1 drivers +v0x2b70d30_0 .net "out", 0 0, L_0x2d6f4d0; alias, 1 drivers +L_0x2d6e6c0 .part L_0x2d6d4d0, 0, 4; +L_0x2d6f2f0 .concat8 [ 1 1 0 0], L_0x2d6e3b0, L_0x2d6efe0; +L_0x2d6f430 .part L_0x2d6d4d0, 4, 4; +L_0x2d6f590 .part L_0x2d6f2f0, 0, 1; +L_0x2d6f740 .part L_0x2d6f2f0, 1, 1; +S_0x2b6f050 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b6ee90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1286830/d .functor OR 1, L_0x12868f0, L_0x1286a50, C4<0>, C4<0>; -L_0x1286830 .delay 1 (30000,30000,30000) L_0x1286830/d; -L_0x1286c80/d .functor OR 1, L_0x1286d90, L_0x1286ef0, C4<0>, C4<0>; -L_0x1286c80 .delay 1 (30000,30000,30000) L_0x1286c80/d; -L_0x1287070/d .functor OR 1, L_0x12870e0, L_0x1287290, C4<0>, C4<0>; -L_0x1287070 .delay 1 (30000,30000,30000) L_0x1287070/d; -v0x10a1d70_0 .net *"_s0", 0 0, L_0x1286830; 1 drivers -v0x10a1e70_0 .net *"_s10", 0 0, L_0x1286d90; 1 drivers -v0x10a1f50_0 .net *"_s12", 0 0, L_0x1286ef0; 1 drivers -v0x10a2010_0 .net *"_s14", 0 0, L_0x12870e0; 1 drivers -v0x10a20f0_0 .net *"_s16", 0 0, L_0x1287290; 1 drivers -v0x10a2220_0 .net *"_s3", 0 0, L_0x12868f0; 1 drivers -v0x10a2300_0 .net *"_s5", 0 0, L_0x1286a50; 1 drivers -v0x10a23e0_0 .net *"_s6", 0 0, L_0x1286c80; 1 drivers -v0x10a24c0_0 .net "in", 3 0, L_0x1287380; 1 drivers -v0x10a2630_0 .net "ors", 1 0, L_0x1286b90; 1 drivers -v0x10a2710_0 .net "out", 0 0, L_0x1287070; 1 drivers -L_0x12868f0 .part L_0x1287380, 0, 1; -L_0x1286a50 .part L_0x1287380, 1, 1; -L_0x1286b90 .concat8 [ 1 1 0 0], L_0x1286830, L_0x1286c80; -L_0x1286d90 .part L_0x1287380, 2, 1; -L_0x1286ef0 .part L_0x1287380, 3, 1; -L_0x12870e0 .part L_0x1286b90, 0, 1; -L_0x1287290 .part L_0x1286b90, 1, 1; -S_0x10a2830 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10a1960; +L_0x2d6db70/d .functor OR 1, L_0x2d6dc30, L_0x2d6dd90, C4<0>, C4<0>; +L_0x2d6db70 .delay 1 (30000,30000,30000) L_0x2d6db70/d; +L_0x2d6dfc0/d .functor OR 1, L_0x2d6e0d0, L_0x2d6e230, C4<0>, C4<0>; +L_0x2d6dfc0 .delay 1 (30000,30000,30000) L_0x2d6dfc0/d; +L_0x2d6e3b0/d .functor OR 1, L_0x2d6e420, L_0x2d6e5d0, C4<0>, C4<0>; +L_0x2d6e3b0 .delay 1 (30000,30000,30000) L_0x2d6e3b0/d; +v0x2b6f2a0_0 .net *"_s0", 0 0, L_0x2d6db70; 1 drivers +v0x2b6f3a0_0 .net *"_s10", 0 0, L_0x2d6e0d0; 1 drivers +v0x2b6f480_0 .net *"_s12", 0 0, L_0x2d6e230; 1 drivers +v0x2b6f540_0 .net *"_s14", 0 0, L_0x2d6e420; 1 drivers +v0x2b6f620_0 .net *"_s16", 0 0, L_0x2d6e5d0; 1 drivers +v0x2b6f750_0 .net *"_s3", 0 0, L_0x2d6dc30; 1 drivers +v0x2b6f830_0 .net *"_s5", 0 0, L_0x2d6dd90; 1 drivers +v0x2b6f910_0 .net *"_s6", 0 0, L_0x2d6dfc0; 1 drivers +v0x2b6f9f0_0 .net "in", 3 0, L_0x2d6e6c0; 1 drivers +v0x2b6fb60_0 .net "ors", 1 0, L_0x2d6ded0; 1 drivers +v0x2b6fc40_0 .net "out", 0 0, L_0x2d6e3b0; 1 drivers +L_0x2d6dc30 .part L_0x2d6e6c0, 0, 1; +L_0x2d6dd90 .part L_0x2d6e6c0, 1, 1; +L_0x2d6ded0 .concat8 [ 1 1 0 0], L_0x2d6db70, L_0x2d6dfc0; +L_0x2d6e0d0 .part L_0x2d6e6c0, 2, 1; +L_0x2d6e230 .part L_0x2d6e6c0, 3, 1; +L_0x2d6e420 .part L_0x2d6ded0, 0, 1; +L_0x2d6e5d0 .part L_0x2d6ded0, 1, 1; +S_0x2b6fd60 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b6ee90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12874b0/d .functor OR 1, L_0x1287520, L_0x1287680, C4<0>, C4<0>; -L_0x12874b0 .delay 1 (30000,30000,30000) L_0x12874b0/d; -L_0x12878b0/d .functor OR 1, L_0x12879c0, L_0x1287b20, C4<0>, C4<0>; -L_0x12878b0 .delay 1 (30000,30000,30000) L_0x12878b0/d; -L_0x1287ca0/d .functor OR 1, L_0x1287d10, L_0x1287ec0, C4<0>, C4<0>; -L_0x1287ca0 .delay 1 (30000,30000,30000) L_0x1287ca0/d; -v0x10a29f0_0 .net *"_s0", 0 0, L_0x12874b0; 1 drivers -v0x10a2af0_0 .net *"_s10", 0 0, L_0x12879c0; 1 drivers -v0x10a2bd0_0 .net *"_s12", 0 0, L_0x1287b20; 1 drivers -v0x10a2c90_0 .net *"_s14", 0 0, L_0x1287d10; 1 drivers -v0x10a2d70_0 .net *"_s16", 0 0, L_0x1287ec0; 1 drivers -v0x10a2ea0_0 .net *"_s3", 0 0, L_0x1287520; 1 drivers -v0x10a2f80_0 .net *"_s5", 0 0, L_0x1287680; 1 drivers -v0x10a3060_0 .net *"_s6", 0 0, L_0x12878b0; 1 drivers -v0x10a3140_0 .net "in", 3 0, L_0x12880f0; 1 drivers -v0x10a32b0_0 .net "ors", 1 0, L_0x12877c0; 1 drivers -v0x10a3390_0 .net "out", 0 0, L_0x1287ca0; 1 drivers -L_0x1287520 .part L_0x12880f0, 0, 1; -L_0x1287680 .part L_0x12880f0, 1, 1; -L_0x12877c0 .concat8 [ 1 1 0 0], L_0x12874b0, L_0x12878b0; -L_0x12879c0 .part L_0x12880f0, 2, 1; -L_0x1287b20 .part L_0x12880f0, 3, 1; -L_0x1287d10 .part L_0x12877c0, 0, 1; -L_0x1287ec0 .part L_0x12877c0, 1, 1; -S_0x10a3ca0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1097590; +L_0x2d6e7f0/d .functor OR 1, L_0x2d6e860, L_0x2d6e9c0, C4<0>, C4<0>; +L_0x2d6e7f0 .delay 1 (30000,30000,30000) L_0x2d6e7f0/d; +L_0x2d6ebf0/d .functor OR 1, L_0x2d6ed00, L_0x2d6ee60, C4<0>, C4<0>; +L_0x2d6ebf0 .delay 1 (30000,30000,30000) L_0x2d6ebf0/d; +L_0x2d6efe0/d .functor OR 1, L_0x2d6f050, L_0x2d6f200, C4<0>, C4<0>; +L_0x2d6efe0 .delay 1 (30000,30000,30000) L_0x2d6efe0/d; +v0x2b6ff20_0 .net *"_s0", 0 0, L_0x2d6e7f0; 1 drivers +v0x2b70020_0 .net *"_s10", 0 0, L_0x2d6ed00; 1 drivers +v0x2b70100_0 .net *"_s12", 0 0, L_0x2d6ee60; 1 drivers +v0x2b701c0_0 .net *"_s14", 0 0, L_0x2d6f050; 1 drivers +v0x2b702a0_0 .net *"_s16", 0 0, L_0x2d6f200; 1 drivers +v0x2b703d0_0 .net *"_s3", 0 0, L_0x2d6e860; 1 drivers +v0x2b704b0_0 .net *"_s5", 0 0, L_0x2d6e9c0; 1 drivers +v0x2b70590_0 .net *"_s6", 0 0, L_0x2d6ebf0; 1 drivers +v0x2b70670_0 .net "in", 3 0, L_0x2d6f430; 1 drivers +v0x2b707e0_0 .net "ors", 1 0, L_0x2d6eb00; 1 drivers +v0x2b708c0_0 .net "out", 0 0, L_0x2d6efe0; 1 drivers +L_0x2d6e860 .part L_0x2d6f430, 0, 1; +L_0x2d6e9c0 .part L_0x2d6f430, 1, 1; +L_0x2d6eb00 .concat8 [ 1 1 0 0], L_0x2d6e7f0, L_0x2d6ebf0; +L_0x2d6ed00 .part L_0x2d6f430, 2, 1; +L_0x2d6ee60 .part L_0x2d6f430, 3, 1; +L_0x2d6f050 .part L_0x2d6eb00, 0, 1; +L_0x2d6f200 .part L_0x2d6eb00, 1, 1; +S_0x2b711d0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b64ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -7574,80 +8010,80 @@ S_0x10a3ca0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1097590; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1283960/d .functor XNOR 1, L_0x128c030, L_0x1282620, C4<0>, C4<0>; -L_0x1283960 .delay 1 (20000,20000,20000) L_0x1283960/d; -L_0x1283bd0/d .functor AND 1, L_0x128c030, L_0x1282960, C4<1>, C4<1>; -L_0x1283bd0 .delay 1 (30000,30000,30000) L_0x1283bd0/d; -L_0x1283c40/d .functor AND 1, L_0x1283960, L_0x12826c0, C4<1>, C4<1>; -L_0x1283c40 .delay 1 (30000,30000,30000) L_0x1283c40/d; -L_0x1283da0/d .functor OR 1, L_0x1283c40, L_0x1283bd0, C4<0>, C4<0>; -L_0x1283da0 .delay 1 (30000,30000,30000) L_0x1283da0/d; -v0x10a3f50_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers -v0x10a4040_0 .net "a_", 0 0, L_0x1282800; alias, 1 drivers -v0x10a4100_0 .net "b", 0 0, L_0x1282620; alias, 1 drivers -v0x10a41f0_0 .net "b_", 0 0, L_0x1282960; alias, 1 drivers -v0x10a4290_0 .net "carryin", 0 0, L_0x12826c0; alias, 1 drivers -v0x10a43d0_0 .net "eq", 0 0, L_0x1283960; 1 drivers -v0x10a4490_0 .net "lt", 0 0, L_0x1283bd0; 1 drivers -v0x10a4550_0 .net "out", 0 0, L_0x1283da0; 1 drivers -v0x10a4610_0 .net "w0", 0 0, L_0x1283c40; 1 drivers -S_0x10a4860 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1097590; +L_0x2d6a2d0/d .functor XNOR 1, L_0x2d73370, L_0x2d68cd0, C4<0>, C4<0>; +L_0x2d6a2d0 .delay 1 (20000,20000,20000) L_0x2d6a2d0/d; +L_0x2d6a450/d .functor AND 1, L_0x2d73370, L_0x2d68fc0, C4<1>, C4<1>; +L_0x2d6a450 .delay 1 (30000,30000,30000) L_0x2d6a450/d; +L_0x2d6a5b0/d .functor AND 1, L_0x2d6a2d0, L_0x2d68d70, C4<1>, C4<1>; +L_0x2d6a5b0 .delay 1 (30000,30000,30000) L_0x2d6a5b0/d; +L_0x2d6a6c0/d .functor OR 1, L_0x2d6a5b0, L_0x2d6a450, C4<0>, C4<0>; +L_0x2d6a6c0 .delay 1 (30000,30000,30000) L_0x2d6a6c0/d; +v0x2b71480_0 .net "a", 0 0, L_0x2d73370; alias, 1 drivers +v0x2b71570_0 .net "a_", 0 0, L_0x2d68eb0; alias, 1 drivers +v0x2b71630_0 .net "b", 0 0, L_0x2d68cd0; alias, 1 drivers +v0x2b71720_0 .net "b_", 0 0, L_0x2d68fc0; alias, 1 drivers +v0x2b717c0_0 .net "carryin", 0 0, L_0x2d68d70; alias, 1 drivers +v0x2b71900_0 .net "eq", 0 0, L_0x2d6a2d0; 1 drivers +v0x2b719c0_0 .net "lt", 0 0, L_0x2d6a450; 1 drivers +v0x2b71a80_0 .net "out", 0 0, L_0x2d6a6c0; 1 drivers +v0x2b71b40_0 .net "w0", 0 0, L_0x2d6a5b0; 1 drivers +S_0x2b71d90 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b64ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1283740/d .functor OR 1, L_0x1283290, L_0x10a5ac0, C4<0>, C4<0>; -L_0x1283740 .delay 1 (30000,30000,30000) L_0x1283740/d; -v0x10a5650_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers -v0x10a57a0_0 .net "b", 0 0, L_0x1282960; alias, 1 drivers -v0x10a5860_0 .net "c1", 0 0, L_0x1283290; 1 drivers -v0x10a5900_0 .net "c2", 0 0, L_0x10a5ac0; 1 drivers -v0x10a59d0_0 .net "carryin", 0 0, L_0x12826c0; alias, 1 drivers -v0x10a5b50_0 .net "carryout", 0 0, L_0x1283740; 1 drivers -v0x10a5bf0_0 .net "s1", 0 0, L_0x12831d0; 1 drivers -v0x10a5c90_0 .net "sum", 0 0, L_0x12833f0; 1 drivers -S_0x10a4ab0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10a4860; +L_0x2d69eb0/d .functor OR 1, L_0x2d699b0, L_0x2b72ff0, C4<0>, C4<0>; +L_0x2d69eb0 .delay 1 (30000,30000,30000) L_0x2d69eb0/d; +v0x2b72b80_0 .net "a", 0 0, L_0x2d73370; alias, 1 drivers +v0x2b72cd0_0 .net "b", 0 0, L_0x2d68fc0; alias, 1 drivers +v0x2b72d90_0 .net "c1", 0 0, L_0x2d699b0; 1 drivers +v0x2b72e30_0 .net "c2", 0 0, L_0x2b72ff0; 1 drivers +v0x2b72f00_0 .net "carryin", 0 0, L_0x2d68d70; alias, 1 drivers +v0x2b73080_0 .net "carryout", 0 0, L_0x2d69eb0; 1 drivers +v0x2b73120_0 .net "s1", 0 0, L_0x2d698f0; 1 drivers +v0x2b731c0_0 .net "sum", 0 0, L_0x2d69b10; 1 drivers +S_0x2b71fe0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b71d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12831d0/d .functor XOR 1, L_0x128c030, L_0x1282960, C4<0>, C4<0>; -L_0x12831d0 .delay 1 (30000,30000,30000) L_0x12831d0/d; -L_0x1283290/d .functor AND 1, L_0x128c030, L_0x1282960, C4<1>, C4<1>; -L_0x1283290 .delay 1 (30000,30000,30000) L_0x1283290/d; -v0x10a4d10_0 .net "a", 0 0, L_0x128c030; alias, 1 drivers -v0x10a4dd0_0 .net "b", 0 0, L_0x1282960; alias, 1 drivers -v0x10a4e90_0 .net "carryout", 0 0, L_0x1283290; alias, 1 drivers -v0x10a4f30_0 .net "sum", 0 0, L_0x12831d0; alias, 1 drivers -S_0x10a5060 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10a4860; +L_0x2d698f0/d .functor XOR 1, L_0x2d73370, L_0x2d68fc0, C4<0>, C4<0>; +L_0x2d698f0 .delay 1 (30000,30000,30000) L_0x2d698f0/d; +L_0x2d699b0/d .functor AND 1, L_0x2d73370, L_0x2d68fc0, C4<1>, C4<1>; +L_0x2d699b0 .delay 1 (30000,30000,30000) L_0x2d699b0/d; +v0x2b72240_0 .net "a", 0 0, L_0x2d73370; alias, 1 drivers +v0x2b72300_0 .net "b", 0 0, L_0x2d68fc0; alias, 1 drivers +v0x2b723c0_0 .net "carryout", 0 0, L_0x2d699b0; alias, 1 drivers +v0x2b72460_0 .net "sum", 0 0, L_0x2d698f0; alias, 1 drivers +S_0x2b72590 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b71d90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12833f0/d .functor XOR 1, L_0x12831d0, L_0x12826c0, C4<0>, C4<0>; -L_0x12833f0 .delay 1 (30000,30000,30000) L_0x12833f0/d; -L_0x10a5ac0/d .functor AND 1, L_0x12831d0, L_0x12826c0, C4<1>, C4<1>; -L_0x10a5ac0 .delay 1 (30000,30000,30000) L_0x10a5ac0/d; -v0x10a52c0_0 .net "a", 0 0, L_0x12831d0; alias, 1 drivers -v0x10a5390_0 .net "b", 0 0, L_0x12826c0; alias, 1 drivers -v0x10a5430_0 .net "carryout", 0 0, L_0x10a5ac0; alias, 1 drivers -v0x10a5500_0 .net "sum", 0 0, L_0x12833f0; alias, 1 drivers -S_0x10a70b0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10972c0; - .timescale -9 -12; -L_0x2b0ab3d05eb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05f00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x128c0d0/d .functor OR 1, L_0x2b0ab3d05eb8, L_0x2b0ab3d05f00, C4<0>, C4<0>; -L_0x128c0d0 .delay 1 (30000,30000,30000) L_0x128c0d0/d; -v0x10a72a0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05eb8; 1 drivers -v0x10a7380_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d05f00; 1 drivers -S_0x10a7460 .scope generate, "alu_slices[14]" "alu_slices[14]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x10a7670 .param/l "i" 0 3 41, +C4<01110>; -S_0x10a7730 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10a7460; +L_0x2d69b10/d .functor XOR 1, L_0x2d698f0, L_0x2d68d70, C4<0>, C4<0>; +L_0x2d69b10 .delay 1 (30000,30000,30000) L_0x2d69b10/d; +L_0x2b72ff0/d .functor AND 1, L_0x2d698f0, L_0x2d68d70, C4<1>, C4<1>; +L_0x2b72ff0 .delay 1 (30000,30000,30000) L_0x2b72ff0/d; +v0x2b727f0_0 .net "a", 0 0, L_0x2d698f0; alias, 1 drivers +v0x2b728c0_0 .net "b", 0 0, L_0x2d68d70; alias, 1 drivers +v0x2b72960_0 .net "carryout", 0 0, L_0x2b72ff0; alias, 1 drivers +v0x2b72a30_0 .net "sum", 0 0, L_0x2d69b10; alias, 1 drivers +S_0x2b75250 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b647f0; + .timescale -9 -12; +L_0x2ac6110b9618 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9660 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d69470/d .functor OR 1, L_0x2ac6110b9618, L_0x2ac6110b9660, C4<0>, C4<0>; +L_0x2d69470 .delay 1 (30000,30000,30000) L_0x2d69470/d; +v0x2b75440_0 .net/2u *"_s0", 0 0, L_0x2ac6110b9618; 1 drivers +v0x2b75520_0 .net/2u *"_s2", 0 0, L_0x2ac6110b9660; 1 drivers +S_0x2b75600 .scope generate, "alu_slices[14]" "alu_slices[14]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b75810 .param/l "i" 0 3 39, +C4<01110>; +S_0x2b758d0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b75600; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -7656,445 +8092,476 @@ S_0x10a7730 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10a7460; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x128c3e0/d .functor NOT 1, L_0x1295b80, C4<0>, C4<0>, C4<0>; -L_0x128c3e0 .delay 1 (10000,10000,10000) L_0x128c3e0/d; -L_0x128c540/d .functor NOT 1, L_0x1247990, C4<0>, C4<0>, C4<0>; -L_0x128c540 .delay 1 (10000,10000,10000) L_0x128c540/d; -L_0x128d590/d .functor XOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; -L_0x128d590 .delay 1 (30000,30000,30000) L_0x128d590/d; -L_0x2b0ab3d05f48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d05f90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x128dc40/d .functor OR 1, L_0x2b0ab3d05f48, L_0x2b0ab3d05f90, C4<0>, C4<0>; -L_0x128dc40 .delay 1 (30000,30000,30000) L_0x128dc40/d; -L_0x128de40/d .functor AND 1, L_0x1295b80, L_0x1247990, C4<1>, C4<1>; -L_0x128de40 .delay 1 (30000,30000,30000) L_0x128de40/d; -L_0x128df00/d .functor NAND 1, L_0x1295b80, L_0x1247990, C4<1>, C4<1>; -L_0x128df00 .delay 1 (20000,20000,20000) L_0x128df00/d; -L_0x128e060/d .functor XOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; -L_0x128e060 .delay 1 (20000,20000,20000) L_0x128e060/d; -L_0x128e510/d .functor OR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; -L_0x128e510 .delay 1 (30000,30000,30000) L_0x128e510/d; -L_0x1295a80/d .functor NOT 1, L_0x1291da0, C4<0>, C4<0>, C4<0>; -L_0x1295a80 .delay 1 (10000,10000,10000) L_0x1295a80/d; -v0x10b5e60_0 .net "A", 0 0, L_0x1295b80; 1 drivers -v0x10b5f20_0 .net "A_", 0 0, L_0x128c3e0; 1 drivers -v0x10b5fe0_0 .net "B", 0 0, L_0x1247990; 1 drivers -v0x10b60b0_0 .net "B_", 0 0, L_0x128c540; 1 drivers -v0x10b6150_0 .net *"_s12", 0 0, L_0x128dc40; 1 drivers -v0x10b6240_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d05f48; 1 drivers -v0x10b6300_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d05f90; 1 drivers -v0x10b63e0_0 .net *"_s18", 0 0, L_0x128de40; 1 drivers -v0x10b64c0_0 .net *"_s20", 0 0, L_0x128df00; 1 drivers -v0x10b6630_0 .net *"_s22", 0 0, L_0x128e060; 1 drivers -v0x10b6710_0 .net *"_s24", 0 0, L_0x128e510; 1 drivers -o0x2b0ab3cc5d28 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10b67f0_0 name=_s30 -o0x2b0ab3cc5d58 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10b68d0_0 name=_s32 -v0x10b69b0_0 .net *"_s8", 0 0, L_0x128d590; 1 drivers -v0x10b6a90_0 .net "carryin", 0 0, L_0x1247b40; 1 drivers -v0x10b6b30_0 .net "carryout", 0 0, L_0x1295720; 1 drivers -v0x10b6bd0_0 .net "carryouts", 7 0, L_0x1354580; 1 drivers -v0x10b6d80_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10b6e20_0 .net "result", 0 0, L_0x1291da0; 1 drivers -v0x10b6f10_0 .net "results", 7 0, L_0x128e2e0; 1 drivers -v0x10b7020_0 .net "zero", 0 0, L_0x1295a80; 1 drivers -LS_0x128e2e0_0_0 .concat8 [ 1 1 1 1], L_0x128ca60, L_0x128d090, L_0x128d590, L_0x128dc40; -LS_0x128e2e0_0_4 .concat8 [ 1 1 1 1], L_0x128de40, L_0x128df00, L_0x128e060, L_0x128e510; -L_0x128e2e0 .concat8 [ 4 4 0 0], LS_0x128e2e0_0_0, LS_0x128e2e0_0_4; -LS_0x1354580_0_0 .concat [ 1 1 1 1], L_0x128cd10, L_0x128d430, o0x2b0ab3cc5d28, L_0x128da90; -LS_0x1354580_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc5d58; -L_0x1354580 .concat [ 4 4 0 0], LS_0x1354580_0_0, LS_0x1354580_0_4; -S_0x10a79b0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10a7730; +L_0x2d736d0/d .functor NOT 1, L_0x2d7db90, C4<0>, C4<0>, C4<0>; +L_0x2d736d0 .delay 1 (10000,10000,10000) L_0x2d736d0/d; +L_0x2d73830/d .functor NOT 1, L_0x2d293d0, C4<0>, C4<0>, C4<0>; +L_0x2d73830 .delay 1 (10000,10000,10000) L_0x2d73830/d; +L_0x2d747e0/d .functor XOR 1, L_0x2d7db90, L_0x2d293d0, C4<0>, C4<0>; +L_0x2d747e0 .delay 1 (30000,30000,30000) L_0x2d747e0/d; +L_0x2ac6110b96a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b96f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d748a0/d .functor OR 1, L_0x2ac6110b96a8, L_0x2ac6110b96f0, C4<0>, C4<0>; +L_0x2d748a0 .delay 1 (30000,30000,30000) L_0x2d748a0/d; +L_0x2ac6110b9738 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9780 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d75040/d .functor OR 1, L_0x2ac6110b9738, L_0x2ac6110b9780, C4<0>, C4<0>; +L_0x2d75040 .delay 1 (30000,30000,30000) L_0x2d75040/d; +L_0x2d75240/d .functor AND 1, L_0x2d7db90, L_0x2d293d0, C4<1>, C4<1>; +L_0x2d75240 .delay 1 (30000,30000,30000) L_0x2d75240/d; +L_0x2ac6110b97c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9810 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d75300/d .functor OR 1, L_0x2ac6110b97c8, L_0x2ac6110b9810, C4<0>, C4<0>; +L_0x2d75300 .delay 1 (30000,30000,30000) L_0x2d75300/d; +L_0x2d75500/d .functor NAND 1, L_0x2d7db90, L_0x2d293d0, C4<1>, C4<1>; +L_0x2d75500 .delay 1 (20000,20000,20000) L_0x2d75500/d; +L_0x2ac6110b9858 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b98a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d75610/d .functor OR 1, L_0x2ac6110b9858, L_0x2ac6110b98a0, C4<0>, C4<0>; +L_0x2d75610 .delay 1 (30000,30000,30000) L_0x2d75610/d; +L_0x2d757c0/d .functor NOR 1, L_0x2d7db90, L_0x2d293d0, C4<0>, C4<0>; +L_0x2d757c0 .delay 1 (20000,20000,20000) L_0x2d757c0/d; +L_0x2ac6110b98e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9930 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d75a90/d .functor OR 1, L_0x2ac6110b98e8, L_0x2ac6110b9930, C4<0>, C4<0>; +L_0x2d75a90 .delay 1 (30000,30000,30000) L_0x2d75a90/d; +L_0x2d75e90/d .functor OR 1, L_0x2d7db90, L_0x2d293d0, C4<0>, C4<0>; +L_0x2d75e90 .delay 1 (30000,30000,30000) L_0x2d75e90/d; +L_0x2ac6110b9978 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b99c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d76330/d .functor OR 1, L_0x2ac6110b9978, L_0x2ac6110b99c0, C4<0>, C4<0>; +L_0x2d76330 .delay 1 (30000,30000,30000) L_0x2d76330/d; +L_0x2d7da90/d .functor NOT 1, L_0x2d79cf0, C4<0>, C4<0>, C4<0>; +L_0x2d7da90 .delay 1 (10000,10000,10000) L_0x2d7da90/d; +v0x2b84000_0 .net "A", 0 0, L_0x2d7db90; 1 drivers +v0x2b840c0_0 .net "A_", 0 0, L_0x2d736d0; 1 drivers +v0x2b84180_0 .net "B", 0 0, L_0x2d293d0; 1 drivers +v0x2b84250_0 .net "B_", 0 0, L_0x2d73830; 1 drivers +v0x2b842f0_0 .net *"_s11", 0 0, L_0x2d748a0; 1 drivers +v0x2b843e0_0 .net/2s *"_s13", 0 0, L_0x2ac6110b96a8; 1 drivers +v0x2b844a0_0 .net/2s *"_s15", 0 0, L_0x2ac6110b96f0; 1 drivers +v0x2b84580_0 .net *"_s19", 0 0, L_0x2d75040; 1 drivers +v0x2b84660_0 .net/2s *"_s21", 0 0, L_0x2ac6110b9738; 1 drivers +v0x2b847d0_0 .net/2s *"_s23", 0 0, L_0x2ac6110b9780; 1 drivers +v0x2b848b0_0 .net *"_s25", 0 0, L_0x2d75240; 1 drivers +v0x2b84990_0 .net *"_s28", 0 0, L_0x2d75300; 1 drivers +v0x2b84a70_0 .net/2s *"_s30", 0 0, L_0x2ac6110b97c8; 1 drivers +v0x2b84b50_0 .net/2s *"_s32", 0 0, L_0x2ac6110b9810; 1 drivers +v0x2b84c30_0 .net *"_s34", 0 0, L_0x2d75500; 1 drivers +v0x2b84d10_0 .net *"_s37", 0 0, L_0x2d75610; 1 drivers +v0x2b84df0_0 .net/2s *"_s39", 0 0, L_0x2ac6110b9858; 1 drivers +v0x2b84fa0_0 .net/2s *"_s41", 0 0, L_0x2ac6110b98a0; 1 drivers +v0x2b85040_0 .net *"_s43", 0 0, L_0x2d757c0; 1 drivers +v0x2b85120_0 .net *"_s46", 0 0, L_0x2d75a90; 1 drivers +v0x2b85200_0 .net/2s *"_s48", 0 0, L_0x2ac6110b98e8; 1 drivers +v0x2b852e0_0 .net/2s *"_s50", 0 0, L_0x2ac6110b9930; 1 drivers +v0x2b853c0_0 .net *"_s52", 0 0, L_0x2d75e90; 1 drivers +v0x2b854a0_0 .net *"_s56", 0 0, L_0x2d76330; 1 drivers +v0x2b85580_0 .net/2s *"_s59", 0 0, L_0x2ac6110b9978; 1 drivers +v0x2b85660_0 .net/2s *"_s61", 0 0, L_0x2ac6110b99c0; 1 drivers +v0x2b85740_0 .net *"_s8", 0 0, L_0x2d747e0; 1 drivers +v0x2b85820_0 .net "carryin", 0 0, L_0x2d29580; 1 drivers +v0x2b858c0_0 .net "carryout", 0 0, L_0x2d7d730; 1 drivers +v0x2b85960_0 .net "carryouts", 7 0, L_0x2d75fa0; 1 drivers +v0x2b85a70_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b85b30_0 .net "result", 0 0, L_0x2d79cf0; 1 drivers +v0x2b85c20_0 .net "results", 7 0, L_0x2d75c60; 1 drivers +v0x2b84f00_0 .net "zero", 0 0, L_0x2d7da90; 1 drivers +LS_0x2d75c60_0_0 .concat8 [ 1 1 1 1], L_0x2d73d00, L_0x2d74330, L_0x2d747e0, L_0x2d75040; +LS_0x2d75c60_0_4 .concat8 [ 1 1 1 1], L_0x2d75240, L_0x2d75500, L_0x2d757c0, L_0x2d75e90; +L_0x2d75c60 .concat8 [ 4 4 0 0], LS_0x2d75c60_0_0, LS_0x2d75c60_0_4; +LS_0x2d75fa0_0_0 .concat8 [ 1 1 1 1], L_0x2d73fb0, L_0x2d74680, L_0x2d748a0, L_0x2d74e90; +LS_0x2d75fa0_0_4 .concat8 [ 1 1 1 1], L_0x2d75300, L_0x2d75610, L_0x2d75a90, L_0x2d76330; +L_0x2d75fa0 .concat8 [ 4 4 0 0], LS_0x2d75fa0_0_0, LS_0x2d75fa0_0_4; +S_0x2b75b50 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b758d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x128cd10/d .functor OR 1, L_0x128c7f0, L_0x128cbb0, C4<0>, C4<0>; -L_0x128cd10 .delay 1 (30000,30000,30000) L_0x128cd10/d; -v0x10a87e0_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers -v0x10a88a0_0 .net "b", 0 0, L_0x1247990; alias, 1 drivers -v0x10a8970_0 .net "c1", 0 0, L_0x128c7f0; 1 drivers -v0x10a8a70_0 .net "c2", 0 0, L_0x128cbb0; 1 drivers -v0x10a8b40_0 .net "carryin", 0 0, L_0x1247b40; alias, 1 drivers -v0x10a8c30_0 .net "carryout", 0 0, L_0x128cd10; 1 drivers -v0x10a8cd0_0 .net "s1", 0 0, L_0x128c730; 1 drivers -v0x10a8dc0_0 .net "sum", 0 0, L_0x128ca60; 1 drivers -S_0x10a7c20 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10a79b0; +L_0x2d73fb0/d .functor OR 1, L_0x2d73a90, L_0x2d73e50, C4<0>, C4<0>; +L_0x2d73fb0 .delay 1 (30000,30000,30000) L_0x2d73fb0/d; +v0x2b76980_0 .net "a", 0 0, L_0x2d7db90; alias, 1 drivers +v0x2b76a40_0 .net "b", 0 0, L_0x2d293d0; alias, 1 drivers +v0x2b76b10_0 .net "c1", 0 0, L_0x2d73a90; 1 drivers +v0x2b76c10_0 .net "c2", 0 0, L_0x2d73e50; 1 drivers +v0x2b76ce0_0 .net "carryin", 0 0, L_0x2d29580; alias, 1 drivers +v0x2b76dd0_0 .net "carryout", 0 0, L_0x2d73fb0; 1 drivers +v0x2b76e70_0 .net "s1", 0 0, L_0x2d73a20; 1 drivers +v0x2b76f60_0 .net "sum", 0 0, L_0x2d73d00; 1 drivers +S_0x2b75dc0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b75b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x128c730/d .functor XOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; -L_0x128c730 .delay 1 (30000,30000,30000) L_0x128c730/d; -L_0x128c7f0/d .functor AND 1, L_0x1295b80, L_0x1247990, C4<1>, C4<1>; -L_0x128c7f0 .delay 1 (30000,30000,30000) L_0x128c7f0/d; -v0x10a7e80_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers -v0x10a7f60_0 .net "b", 0 0, L_0x1247990; alias, 1 drivers -v0x10a8020_0 .net "carryout", 0 0, L_0x128c7f0; alias, 1 drivers -v0x10a80c0_0 .net "sum", 0 0, L_0x128c730; alias, 1 drivers -S_0x10a8200 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10a79b0; +L_0x2d73a20/d .functor XOR 1, L_0x2d7db90, L_0x2d293d0, C4<0>, C4<0>; +L_0x2d73a20 .delay 1 (30000,30000,30000) L_0x2d73a20/d; +L_0x2d73a90/d .functor AND 1, L_0x2d7db90, L_0x2d293d0, C4<1>, C4<1>; +L_0x2d73a90 .delay 1 (30000,30000,30000) L_0x2d73a90/d; +v0x2b76020_0 .net "a", 0 0, L_0x2d7db90; alias, 1 drivers +v0x2b76100_0 .net "b", 0 0, L_0x2d293d0; alias, 1 drivers +v0x2b761c0_0 .net "carryout", 0 0, L_0x2d73a90; alias, 1 drivers +v0x2b76260_0 .net "sum", 0 0, L_0x2d73a20; alias, 1 drivers +S_0x2b763a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b75b50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x128ca60/d .functor XOR 1, L_0x128c730, L_0x1247b40, C4<0>, C4<0>; -L_0x128ca60 .delay 1 (30000,30000,30000) L_0x128ca60/d; -L_0x128cbb0/d .functor AND 1, L_0x128c730, L_0x1247b40, C4<1>, C4<1>; -L_0x128cbb0 .delay 1 (30000,30000,30000) L_0x128cbb0/d; -v0x10a8460_0 .net "a", 0 0, L_0x128c730; alias, 1 drivers -v0x10a8500_0 .net "b", 0 0, L_0x1247b40; alias, 1 drivers -v0x10a85a0_0 .net "carryout", 0 0, L_0x128cbb0; alias, 1 drivers -v0x10a8670_0 .net "sum", 0 0, L_0x128ca60; alias, 1 drivers -S_0x10a8e90 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10a7730; +L_0x2d73d00/d .functor XOR 1, L_0x2d73a20, L_0x2d29580, C4<0>, C4<0>; +L_0x2d73d00 .delay 1 (30000,30000,30000) L_0x2d73d00/d; +L_0x2d73e50/d .functor AND 1, L_0x2d73a20, L_0x2d29580, C4<1>, C4<1>; +L_0x2d73e50 .delay 1 (30000,30000,30000) L_0x2d73e50/d; +v0x2b76600_0 .net "a", 0 0, L_0x2d73a20; alias, 1 drivers +v0x2b766a0_0 .net "b", 0 0, L_0x2d29580; alias, 1 drivers +v0x2b76740_0 .net "carryout", 0 0, L_0x2d73e50; alias, 1 drivers +v0x2b76810_0 .net "sum", 0 0, L_0x2d73d00; alias, 1 drivers +S_0x2b77030 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b758d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10ae280_0 .net "ands", 7 0, L_0x12937e0; 1 drivers -v0x10ae390_0 .net "in", 7 0, L_0x1354580; alias, 1 drivers -v0x10ae450_0 .net "out", 0 0, L_0x1295720; alias, 1 drivers -v0x10ae520_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10a90b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10a8e90; +v0x2b7c420_0 .net "ands", 7 0, L_0x2d7b730; 1 drivers +v0x2b7c530_0 .net "in", 7 0, L_0x2d75fa0; alias, 1 drivers +v0x2b7c5f0_0 .net "out", 0 0, L_0x2d7d730; alias, 1 drivers +v0x2b7c6c0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b77250 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b77030; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10ab7e0_0 .net "A", 7 0, L_0x1354580; alias, 1 drivers -v0x10ab8e0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10ab9a0_0 .net *"_s0", 0 0, L_0x1292100; 1 drivers -v0x10aba60_0 .net *"_s12", 0 0, L_0x1292a70; 1 drivers -v0x10abb40_0 .net *"_s16", 0 0, L_0x1292dd0; 1 drivers -v0x10abc70_0 .net *"_s20", 0 0, L_0x12930e0; 1 drivers -v0x10abd50_0 .net *"_s24", 0 0, L_0x12934d0; 1 drivers -v0x10abe30_0 .net *"_s28", 0 0, L_0x1293460; 1 drivers -v0x10abf10_0 .net *"_s4", 0 0, L_0x1292410; 1 drivers -v0x10ac080_0 .net *"_s8", 0 0, L_0x1292760; 1 drivers -v0x10ac160_0 .net "out", 7 0, L_0x12937e0; alias, 1 drivers -L_0x12921c0 .part L_0x1354580, 0, 1; -L_0x1292320 .part v0x12010b0_0, 0, 1; -L_0x12924d0 .part L_0x1354580, 1, 1; -L_0x12926c0 .part v0x12010b0_0, 1, 1; -L_0x1292820 .part L_0x1354580, 2, 1; -L_0x1292980 .part v0x12010b0_0, 2, 1; -L_0x1292b30 .part L_0x1354580, 3, 1; -L_0x1292c90 .part v0x12010b0_0, 3, 1; -L_0x1292e90 .part L_0x1354580, 4, 1; -L_0x1292ff0 .part v0x12010b0_0, 4, 1; -L_0x1293150 .part L_0x1354580, 5, 1; -L_0x12933c0 .part v0x12010b0_0, 5, 1; -L_0x1293590 .part L_0x1354580, 6, 1; -L_0x12936f0 .part v0x12010b0_0, 6, 1; -LS_0x12937e0_0_0 .concat8 [ 1 1 1 1], L_0x1292100, L_0x1292410, L_0x1292760, L_0x1292a70; -LS_0x12937e0_0_4 .concat8 [ 1 1 1 1], L_0x1292dd0, L_0x12930e0, L_0x12934d0, L_0x1293460; -L_0x12937e0 .concat8 [ 4 4 0 0], LS_0x12937e0_0_0, LS_0x12937e0_0_4; -L_0x1293ba0 .part L_0x1354580, 7, 1; -L_0x1293d90 .part v0x12010b0_0, 7, 1; -S_0x10a9310 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10a9520 .param/l "i" 0 4 54, +C4<00>; -L_0x1292100/d .functor AND 1, L_0x12921c0, L_0x1292320, C4<1>, C4<1>; -L_0x1292100 .delay 1 (30000,30000,30000) L_0x1292100/d; -v0x10a9600_0 .net *"_s0", 0 0, L_0x12921c0; 1 drivers -v0x10a96e0_0 .net *"_s1", 0 0, L_0x1292320; 1 drivers -S_0x10a97c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10a99d0 .param/l "i" 0 4 54, +C4<01>; -L_0x1292410/d .functor AND 1, L_0x12924d0, L_0x12926c0, C4<1>, C4<1>; -L_0x1292410 .delay 1 (30000,30000,30000) L_0x1292410/d; -v0x10a9a90_0 .net *"_s0", 0 0, L_0x12924d0; 1 drivers -v0x10a9b70_0 .net *"_s1", 0 0, L_0x12926c0; 1 drivers -S_0x10a9c50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10a9e60 .param/l "i" 0 4 54, +C4<010>; -L_0x1292760/d .functor AND 1, L_0x1292820, L_0x1292980, C4<1>, C4<1>; -L_0x1292760 .delay 1 (30000,30000,30000) L_0x1292760/d; -v0x10a9f00_0 .net *"_s0", 0 0, L_0x1292820; 1 drivers -v0x10a9fe0_0 .net *"_s1", 0 0, L_0x1292980; 1 drivers -S_0x10aa0c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10aa2d0 .param/l "i" 0 4 54, +C4<011>; -L_0x1292a70/d .functor AND 1, L_0x1292b30, L_0x1292c90, C4<1>, C4<1>; -L_0x1292a70 .delay 1 (30000,30000,30000) L_0x1292a70/d; -v0x10aa390_0 .net *"_s0", 0 0, L_0x1292b30; 1 drivers -v0x10aa470_0 .net *"_s1", 0 0, L_0x1292c90; 1 drivers -S_0x10aa550 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10aa7b0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1292dd0/d .functor AND 1, L_0x1292e90, L_0x1292ff0, C4<1>, C4<1>; -L_0x1292dd0 .delay 1 (30000,30000,30000) L_0x1292dd0/d; -v0x10aa870_0 .net *"_s0", 0 0, L_0x1292e90; 1 drivers -v0x10aa950_0 .net *"_s1", 0 0, L_0x1292ff0; 1 drivers -S_0x10aaa30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10aac40 .param/l "i" 0 4 54, +C4<0101>; -L_0x12930e0/d .functor AND 1, L_0x1293150, L_0x12933c0, C4<1>, C4<1>; -L_0x12930e0 .delay 1 (30000,30000,30000) L_0x12930e0/d; -v0x10aad00_0 .net *"_s0", 0 0, L_0x1293150; 1 drivers -v0x10aade0_0 .net *"_s1", 0 0, L_0x12933c0; 1 drivers -S_0x10aaec0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10ab0d0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12934d0/d .functor AND 1, L_0x1293590, L_0x12936f0, C4<1>, C4<1>; -L_0x12934d0 .delay 1 (30000,30000,30000) L_0x12934d0/d; -v0x10ab190_0 .net *"_s0", 0 0, L_0x1293590; 1 drivers -v0x10ab270_0 .net *"_s1", 0 0, L_0x12936f0; 1 drivers -S_0x10ab350 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10a90b0; - .timescale -9 -12; -P_0x10ab560 .param/l "i" 0 4 54, +C4<0111>; -L_0x1293460/d .functor AND 1, L_0x1293ba0, L_0x1293d90, C4<1>, C4<1>; -L_0x1293460 .delay 1 (30000,30000,30000) L_0x1293460/d; -v0x10ab620_0 .net *"_s0", 0 0, L_0x1293ba0; 1 drivers -v0x10ab700_0 .net *"_s1", 0 0, L_0x1293d90; 1 drivers -S_0x10ac2c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10a8e90; +v0x2b79980_0 .net "A", 7 0, L_0x2d75fa0; alias, 1 drivers +v0x2b79a80_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b79b40_0 .net *"_s0", 0 0, L_0x2d7a050; 1 drivers +v0x2b79c00_0 .net *"_s12", 0 0, L_0x2d7a9c0; 1 drivers +v0x2b79ce0_0 .net *"_s16", 0 0, L_0x2d7ad20; 1 drivers +v0x2b79e10_0 .net *"_s20", 0 0, L_0x2d7b0f0; 1 drivers +v0x2b79ef0_0 .net *"_s24", 0 0, L_0x2d7b420; 1 drivers +v0x2b79fd0_0 .net *"_s28", 0 0, L_0x2d7b3b0; 1 drivers +v0x2b7a0b0_0 .net *"_s4", 0 0, L_0x2d7a3a0; 1 drivers +v0x2b7a220_0 .net *"_s8", 0 0, L_0x2d7a6b0; 1 drivers +v0x2b7a300_0 .net "out", 7 0, L_0x2d7b730; alias, 1 drivers +L_0x2d7a110 .part L_0x2d75fa0, 0, 1; +L_0x2d7a300 .part v0x2cdd2e0_0, 0, 1; +L_0x2d7a460 .part L_0x2d75fa0, 1, 1; +L_0x2d7a5c0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d7a770 .part L_0x2d75fa0, 2, 1; +L_0x2d7a8d0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d7aa80 .part L_0x2d75fa0, 3, 1; +L_0x2d7abe0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d7ade0 .part L_0x2d75fa0, 4, 1; +L_0x2d7b050 .part v0x2cdd2e0_0, 4, 1; +L_0x2d7b160 .part L_0x2d75fa0, 5, 1; +L_0x2d7b2c0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d7b4e0 .part L_0x2d75fa0, 6, 1; +L_0x2d7b640 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d7b730_0_0 .concat8 [ 1 1 1 1], L_0x2d7a050, L_0x2d7a3a0, L_0x2d7a6b0, L_0x2d7a9c0; +LS_0x2d7b730_0_4 .concat8 [ 1 1 1 1], L_0x2d7ad20, L_0x2d7b0f0, L_0x2d7b420, L_0x2d7b3b0; +L_0x2d7b730 .concat8 [ 4 4 0 0], LS_0x2d7b730_0_0, LS_0x2d7b730_0_4; +L_0x2d7baf0 .part L_0x2d75fa0, 7, 1; +L_0x2d7bce0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b774b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b776c0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d7a050/d .functor AND 1, L_0x2d7a110, L_0x2d7a300, C4<1>, C4<1>; +L_0x2d7a050 .delay 1 (30000,30000,30000) L_0x2d7a050/d; +v0x2b777a0_0 .net *"_s0", 0 0, L_0x2d7a110; 1 drivers +v0x2b77880_0 .net *"_s1", 0 0, L_0x2d7a300; 1 drivers +S_0x2b77960 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b77b70 .param/l "i" 0 4 54, +C4<01>; +L_0x2d7a3a0/d .functor AND 1, L_0x2d7a460, L_0x2d7a5c0, C4<1>, C4<1>; +L_0x2d7a3a0 .delay 1 (30000,30000,30000) L_0x2d7a3a0/d; +v0x2b77c30_0 .net *"_s0", 0 0, L_0x2d7a460; 1 drivers +v0x2b77d10_0 .net *"_s1", 0 0, L_0x2d7a5c0; 1 drivers +S_0x2b77df0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b78000 .param/l "i" 0 4 54, +C4<010>; +L_0x2d7a6b0/d .functor AND 1, L_0x2d7a770, L_0x2d7a8d0, C4<1>, C4<1>; +L_0x2d7a6b0 .delay 1 (30000,30000,30000) L_0x2d7a6b0/d; +v0x2b780a0_0 .net *"_s0", 0 0, L_0x2d7a770; 1 drivers +v0x2b78180_0 .net *"_s1", 0 0, L_0x2d7a8d0; 1 drivers +S_0x2b78260 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b78470 .param/l "i" 0 4 54, +C4<011>; +L_0x2d7a9c0/d .functor AND 1, L_0x2d7aa80, L_0x2d7abe0, C4<1>, C4<1>; +L_0x2d7a9c0 .delay 1 (30000,30000,30000) L_0x2d7a9c0/d; +v0x2b78530_0 .net *"_s0", 0 0, L_0x2d7aa80; 1 drivers +v0x2b78610_0 .net *"_s1", 0 0, L_0x2d7abe0; 1 drivers +S_0x2b786f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b78950 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d7ad20/d .functor AND 1, L_0x2d7ade0, L_0x2d7b050, C4<1>, C4<1>; +L_0x2d7ad20 .delay 1 (30000,30000,30000) L_0x2d7ad20/d; +v0x2b78a10_0 .net *"_s0", 0 0, L_0x2d7ade0; 1 drivers +v0x2b78af0_0 .net *"_s1", 0 0, L_0x2d7b050; 1 drivers +S_0x2b78bd0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b78de0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d7b0f0/d .functor AND 1, L_0x2d7b160, L_0x2d7b2c0, C4<1>, C4<1>; +L_0x2d7b0f0 .delay 1 (30000,30000,30000) L_0x2d7b0f0/d; +v0x2b78ea0_0 .net *"_s0", 0 0, L_0x2d7b160; 1 drivers +v0x2b78f80_0 .net *"_s1", 0 0, L_0x2d7b2c0; 1 drivers +S_0x2b79060 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b79270 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d7b420/d .functor AND 1, L_0x2d7b4e0, L_0x2d7b640, C4<1>, C4<1>; +L_0x2d7b420 .delay 1 (30000,30000,30000) L_0x2d7b420/d; +v0x2b79330_0 .net *"_s0", 0 0, L_0x2d7b4e0; 1 drivers +v0x2b79410_0 .net *"_s1", 0 0, L_0x2d7b640; 1 drivers +S_0x2b794f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b77250; + .timescale -9 -12; +P_0x2b79700 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d7b3b0/d .functor AND 1, L_0x2d7baf0, L_0x2d7bce0, C4<1>, C4<1>; +L_0x2d7b3b0 .delay 1 (30000,30000,30000) L_0x2d7b3b0/d; +v0x2b797c0_0 .net *"_s0", 0 0, L_0x2d7baf0; 1 drivers +v0x2b798a0_0 .net *"_s1", 0 0, L_0x2d7bce0; 1 drivers +S_0x2b7a460 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b77030; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1295720/d .functor OR 1, L_0x12957e0, L_0x1295990, C4<0>, C4<0>; -L_0x1295720 .delay 1 (30000,30000,30000) L_0x1295720/d; -v0x10ade10_0 .net *"_s10", 0 0, L_0x12957e0; 1 drivers -v0x10adef0_0 .net *"_s12", 0 0, L_0x1295990; 1 drivers -v0x10adfd0_0 .net "in", 7 0, L_0x12937e0; alias, 1 drivers -v0x10ae0a0_0 .net "ors", 1 0, L_0x1295540; 1 drivers -v0x10ae160_0 .net "out", 0 0, L_0x1295720; alias, 1 drivers -L_0x1294910 .part L_0x12937e0, 0, 4; -L_0x1295540 .concat8 [ 1 1 0 0], L_0x1294600, L_0x1295230; -L_0x1295680 .part L_0x12937e0, 4, 4; -L_0x12957e0 .part L_0x1295540, 0, 1; -L_0x1295990 .part L_0x1295540, 1, 1; -S_0x10ac480 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10ac2c0; +L_0x2d7d730/d .functor OR 1, L_0x2d7d7f0, L_0x2d7d9a0, C4<0>, C4<0>; +L_0x2d7d730 .delay 1 (30000,30000,30000) L_0x2d7d730/d; +v0x2b7bfb0_0 .net *"_s10", 0 0, L_0x2d7d7f0; 1 drivers +v0x2b7c090_0 .net *"_s12", 0 0, L_0x2d7d9a0; 1 drivers +v0x2b7c170_0 .net "in", 7 0, L_0x2d7b730; alias, 1 drivers +v0x2b7c240_0 .net "ors", 1 0, L_0x2d7d550; 1 drivers +v0x2b7c300_0 .net "out", 0 0, L_0x2d7d730; alias, 1 drivers +L_0x2d7c920 .part L_0x2d7b730, 0, 4; +L_0x2d7d550 .concat8 [ 1 1 0 0], L_0x2d7c610, L_0x2d7d240; +L_0x2d7d690 .part L_0x2d7b730, 4, 4; +L_0x2d7d7f0 .part L_0x2d7d550, 0, 1; +L_0x2d7d9a0 .part L_0x2d7d550, 1, 1; +S_0x2b7a620 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b7a460; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1293e80/d .functor OR 1, L_0x1293f40, L_0x1293fe0, C4<0>, C4<0>; -L_0x1293e80 .delay 1 (30000,30000,30000) L_0x1293e80/d; -L_0x1294210/d .functor OR 1, L_0x1294320, L_0x1294480, C4<0>, C4<0>; -L_0x1294210 .delay 1 (30000,30000,30000) L_0x1294210/d; -L_0x1294600/d .functor OR 1, L_0x1294670, L_0x1294820, C4<0>, C4<0>; -L_0x1294600 .delay 1 (30000,30000,30000) L_0x1294600/d; -v0x10ac6d0_0 .net *"_s0", 0 0, L_0x1293e80; 1 drivers -v0x10ac7d0_0 .net *"_s10", 0 0, L_0x1294320; 1 drivers -v0x10ac8b0_0 .net *"_s12", 0 0, L_0x1294480; 1 drivers -v0x10ac970_0 .net *"_s14", 0 0, L_0x1294670; 1 drivers -v0x10aca50_0 .net *"_s16", 0 0, L_0x1294820; 1 drivers -v0x10acb80_0 .net *"_s3", 0 0, L_0x1293f40; 1 drivers -v0x10acc60_0 .net *"_s5", 0 0, L_0x1293fe0; 1 drivers -v0x10acd40_0 .net *"_s6", 0 0, L_0x1294210; 1 drivers -v0x10ace20_0 .net "in", 3 0, L_0x1294910; 1 drivers -v0x10acf90_0 .net "ors", 1 0, L_0x1294120; 1 drivers -v0x10ad070_0 .net "out", 0 0, L_0x1294600; 1 drivers -L_0x1293f40 .part L_0x1294910, 0, 1; -L_0x1293fe0 .part L_0x1294910, 1, 1; -L_0x1294120 .concat8 [ 1 1 0 0], L_0x1293e80, L_0x1294210; -L_0x1294320 .part L_0x1294910, 2, 1; -L_0x1294480 .part L_0x1294910, 3, 1; -L_0x1294670 .part L_0x1294120, 0, 1; -L_0x1294820 .part L_0x1294120, 1, 1; -S_0x10ad190 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10ac2c0; +L_0x2d7bdd0/d .functor OR 1, L_0x2d7be90, L_0x2d7bff0, C4<0>, C4<0>; +L_0x2d7bdd0 .delay 1 (30000,30000,30000) L_0x2d7bdd0/d; +L_0x2d7c220/d .functor OR 1, L_0x2d7c330, L_0x2d7c490, C4<0>, C4<0>; +L_0x2d7c220 .delay 1 (30000,30000,30000) L_0x2d7c220/d; +L_0x2d7c610/d .functor OR 1, L_0x2d7c680, L_0x2d7c830, C4<0>, C4<0>; +L_0x2d7c610 .delay 1 (30000,30000,30000) L_0x2d7c610/d; +v0x2b7a870_0 .net *"_s0", 0 0, L_0x2d7bdd0; 1 drivers +v0x2b7a970_0 .net *"_s10", 0 0, L_0x2d7c330; 1 drivers +v0x2b7aa50_0 .net *"_s12", 0 0, L_0x2d7c490; 1 drivers +v0x2b7ab10_0 .net *"_s14", 0 0, L_0x2d7c680; 1 drivers +v0x2b7abf0_0 .net *"_s16", 0 0, L_0x2d7c830; 1 drivers +v0x2b7ad20_0 .net *"_s3", 0 0, L_0x2d7be90; 1 drivers +v0x2b7ae00_0 .net *"_s5", 0 0, L_0x2d7bff0; 1 drivers +v0x2b7aee0_0 .net *"_s6", 0 0, L_0x2d7c220; 1 drivers +v0x2b7afc0_0 .net "in", 3 0, L_0x2d7c920; 1 drivers +v0x2b7b130_0 .net "ors", 1 0, L_0x2d7c130; 1 drivers +v0x2b7b210_0 .net "out", 0 0, L_0x2d7c610; 1 drivers +L_0x2d7be90 .part L_0x2d7c920, 0, 1; +L_0x2d7bff0 .part L_0x2d7c920, 1, 1; +L_0x2d7c130 .concat8 [ 1 1 0 0], L_0x2d7bdd0, L_0x2d7c220; +L_0x2d7c330 .part L_0x2d7c920, 2, 1; +L_0x2d7c490 .part L_0x2d7c920, 3, 1; +L_0x2d7c680 .part L_0x2d7c130, 0, 1; +L_0x2d7c830 .part L_0x2d7c130, 1, 1; +S_0x2b7b330 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b7a460; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1294a40/d .functor OR 1, L_0x1294ab0, L_0x1294c10, C4<0>, C4<0>; -L_0x1294a40 .delay 1 (30000,30000,30000) L_0x1294a40/d; -L_0x1294e40/d .functor OR 1, L_0x1294f50, L_0x12950b0, C4<0>, C4<0>; -L_0x1294e40 .delay 1 (30000,30000,30000) L_0x1294e40/d; -L_0x1295230/d .functor OR 1, L_0x12952a0, L_0x1295450, C4<0>, C4<0>; -L_0x1295230 .delay 1 (30000,30000,30000) L_0x1295230/d; -v0x10ad350_0 .net *"_s0", 0 0, L_0x1294a40; 1 drivers -v0x10ad450_0 .net *"_s10", 0 0, L_0x1294f50; 1 drivers -v0x10ad530_0 .net *"_s12", 0 0, L_0x12950b0; 1 drivers -v0x10ad5f0_0 .net *"_s14", 0 0, L_0x12952a0; 1 drivers -v0x10ad6d0_0 .net *"_s16", 0 0, L_0x1295450; 1 drivers -v0x10ad800_0 .net *"_s3", 0 0, L_0x1294ab0; 1 drivers -v0x10ad8e0_0 .net *"_s5", 0 0, L_0x1294c10; 1 drivers -v0x10ad9c0_0 .net *"_s6", 0 0, L_0x1294e40; 1 drivers -v0x10adaa0_0 .net "in", 3 0, L_0x1295680; 1 drivers -v0x10adc10_0 .net "ors", 1 0, L_0x1294d50; 1 drivers -v0x10adcf0_0 .net "out", 0 0, L_0x1295230; 1 drivers -L_0x1294ab0 .part L_0x1295680, 0, 1; -L_0x1294c10 .part L_0x1295680, 1, 1; -L_0x1294d50 .concat8 [ 1 1 0 0], L_0x1294a40, L_0x1294e40; -L_0x1294f50 .part L_0x1295680, 2, 1; -L_0x12950b0 .part L_0x1295680, 3, 1; -L_0x12952a0 .part L_0x1294d50, 0, 1; -L_0x1295450 .part L_0x1294d50, 1, 1; -S_0x10ae600 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10a7730; +L_0x2d7ca50/d .functor OR 1, L_0x2d7cac0, L_0x2d7cc20, C4<0>, C4<0>; +L_0x2d7ca50 .delay 1 (30000,30000,30000) L_0x2d7ca50/d; +L_0x2d7ce50/d .functor OR 1, L_0x2d7cf60, L_0x2d7d0c0, C4<0>, C4<0>; +L_0x2d7ce50 .delay 1 (30000,30000,30000) L_0x2d7ce50/d; +L_0x2d7d240/d .functor OR 1, L_0x2d7d2b0, L_0x2d7d460, C4<0>, C4<0>; +L_0x2d7d240 .delay 1 (30000,30000,30000) L_0x2d7d240/d; +v0x2b7b4f0_0 .net *"_s0", 0 0, L_0x2d7ca50; 1 drivers +v0x2b7b5f0_0 .net *"_s10", 0 0, L_0x2d7cf60; 1 drivers +v0x2b7b6d0_0 .net *"_s12", 0 0, L_0x2d7d0c0; 1 drivers +v0x2b7b790_0 .net *"_s14", 0 0, L_0x2d7d2b0; 1 drivers +v0x2b7b870_0 .net *"_s16", 0 0, L_0x2d7d460; 1 drivers +v0x2b7b9a0_0 .net *"_s3", 0 0, L_0x2d7cac0; 1 drivers +v0x2b7ba80_0 .net *"_s5", 0 0, L_0x2d7cc20; 1 drivers +v0x2b7bb60_0 .net *"_s6", 0 0, L_0x2d7ce50; 1 drivers +v0x2b7bc40_0 .net "in", 3 0, L_0x2d7d690; 1 drivers +v0x2b7bdb0_0 .net "ors", 1 0, L_0x2d7cd60; 1 drivers +v0x2b7be90_0 .net "out", 0 0, L_0x2d7d240; 1 drivers +L_0x2d7cac0 .part L_0x2d7d690, 0, 1; +L_0x2d7cc20 .part L_0x2d7d690, 1, 1; +L_0x2d7cd60 .concat8 [ 1 1 0 0], L_0x2d7ca50, L_0x2d7ce50; +L_0x2d7cf60 .part L_0x2d7d690, 2, 1; +L_0x2d7d0c0 .part L_0x2d7d690, 3, 1; +L_0x2d7d2b0 .part L_0x2d7cd60, 0, 1; +L_0x2d7d460 .part L_0x2d7cd60, 1, 1; +S_0x2b7c7a0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b758d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10b3a30_0 .net "ands", 7 0, L_0x128fda0; 1 drivers -v0x10b3b40_0 .net "in", 7 0, L_0x128e2e0; alias, 1 drivers -v0x10b3c00_0 .net "out", 0 0, L_0x1291da0; alias, 1 drivers -v0x10b3cd0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10ae850 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10ae600; +v0x2b81bd0_0 .net "ands", 7 0, L_0x2d77cf0; 1 drivers +v0x2b81ce0_0 .net "in", 7 0, L_0x2d75c60; alias, 1 drivers +v0x2b81da0_0 .net "out", 0 0, L_0x2d79cf0; alias, 1 drivers +v0x2b81e70_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b7c9f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b7c7a0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10b0f90_0 .net "A", 7 0, L_0x128e2e0; alias, 1 drivers -v0x10b1090_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10b1150_0 .net *"_s0", 0 0, L_0x128e670; 1 drivers -v0x10b1210_0 .net *"_s12", 0 0, L_0x128f030; 1 drivers -v0x10b12f0_0 .net *"_s16", 0 0, L_0x128f390; 1 drivers -v0x10b1420_0 .net *"_s20", 0 0, L_0x128f760; 1 drivers -v0x10b1500_0 .net *"_s24", 0 0, L_0x128fa90; 1 drivers -v0x10b15e0_0 .net *"_s28", 0 0, L_0x128fa20; 1 drivers -v0x10b16c0_0 .net *"_s4", 0 0, L_0x128ea10; 1 drivers -v0x10b1830_0 .net *"_s8", 0 0, L_0x128ed20; 1 drivers -v0x10b1910_0 .net "out", 7 0, L_0x128fda0; alias, 1 drivers -L_0x128e780 .part L_0x128e2e0, 0, 1; -L_0x128e970 .part v0x12010b0_0, 0, 1; -L_0x128ead0 .part L_0x128e2e0, 1, 1; -L_0x128ec30 .part v0x12010b0_0, 1, 1; -L_0x128ede0 .part L_0x128e2e0, 2, 1; -L_0x128ef40 .part v0x12010b0_0, 2, 1; -L_0x128f0f0 .part L_0x128e2e0, 3, 1; -L_0x128f250 .part v0x12010b0_0, 3, 1; -L_0x128f450 .part L_0x128e2e0, 4, 1; -L_0x128f6c0 .part v0x12010b0_0, 4, 1; -L_0x128f7d0 .part L_0x128e2e0, 5, 1; -L_0x128f930 .part v0x12010b0_0, 5, 1; -L_0x128fb50 .part L_0x128e2e0, 6, 1; -L_0x128fcb0 .part v0x12010b0_0, 6, 1; -LS_0x128fda0_0_0 .concat8 [ 1 1 1 1], L_0x128e670, L_0x128ea10, L_0x128ed20, L_0x128f030; -LS_0x128fda0_0_4 .concat8 [ 1 1 1 1], L_0x128f390, L_0x128f760, L_0x128fa90, L_0x128fa20; -L_0x128fda0 .concat8 [ 4 4 0 0], LS_0x128fda0_0_0, LS_0x128fda0_0_4; -L_0x1290160 .part L_0x128e2e0, 7, 1; -L_0x1290350 .part v0x12010b0_0, 7, 1; -S_0x10aea90 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10aeca0 .param/l "i" 0 4 54, +C4<00>; -L_0x128e670/d .functor AND 1, L_0x128e780, L_0x128e970, C4<1>, C4<1>; -L_0x128e670 .delay 1 (30000,30000,30000) L_0x128e670/d; -v0x10aed80_0 .net *"_s0", 0 0, L_0x128e780; 1 drivers -v0x10aee60_0 .net *"_s1", 0 0, L_0x128e970; 1 drivers -S_0x10aef40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10af150 .param/l "i" 0 4 54, +C4<01>; -L_0x128ea10/d .functor AND 1, L_0x128ead0, L_0x128ec30, C4<1>, C4<1>; -L_0x128ea10 .delay 1 (30000,30000,30000) L_0x128ea10/d; -v0x10af210_0 .net *"_s0", 0 0, L_0x128ead0; 1 drivers -v0x10af2f0_0 .net *"_s1", 0 0, L_0x128ec30; 1 drivers -S_0x10af3d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10af610 .param/l "i" 0 4 54, +C4<010>; -L_0x128ed20/d .functor AND 1, L_0x128ede0, L_0x128ef40, C4<1>, C4<1>; -L_0x128ed20 .delay 1 (30000,30000,30000) L_0x128ed20/d; -v0x10af6b0_0 .net *"_s0", 0 0, L_0x128ede0; 1 drivers -v0x10af790_0 .net *"_s1", 0 0, L_0x128ef40; 1 drivers -S_0x10af870 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10afa80 .param/l "i" 0 4 54, +C4<011>; -L_0x128f030/d .functor AND 1, L_0x128f0f0, L_0x128f250, C4<1>, C4<1>; -L_0x128f030 .delay 1 (30000,30000,30000) L_0x128f030/d; -v0x10afb40_0 .net *"_s0", 0 0, L_0x128f0f0; 1 drivers -v0x10afc20_0 .net *"_s1", 0 0, L_0x128f250; 1 drivers -S_0x10afd00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10aff60 .param/l "i" 0 4 54, +C4<0100>; -L_0x128f390/d .functor AND 1, L_0x128f450, L_0x128f6c0, C4<1>, C4<1>; -L_0x128f390 .delay 1 (30000,30000,30000) L_0x128f390/d; -v0x10b0020_0 .net *"_s0", 0 0, L_0x128f450; 1 drivers -v0x10b0100_0 .net *"_s1", 0 0, L_0x128f6c0; 1 drivers -S_0x10b01e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10b03f0 .param/l "i" 0 4 54, +C4<0101>; -L_0x128f760/d .functor AND 1, L_0x128f7d0, L_0x128f930, C4<1>, C4<1>; -L_0x128f760 .delay 1 (30000,30000,30000) L_0x128f760/d; -v0x10b04b0_0 .net *"_s0", 0 0, L_0x128f7d0; 1 drivers -v0x10b0590_0 .net *"_s1", 0 0, L_0x128f930; 1 drivers -S_0x10b0670 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10b0880 .param/l "i" 0 4 54, +C4<0110>; -L_0x128fa90/d .functor AND 1, L_0x128fb50, L_0x128fcb0, C4<1>, C4<1>; -L_0x128fa90 .delay 1 (30000,30000,30000) L_0x128fa90/d; -v0x10b0940_0 .net *"_s0", 0 0, L_0x128fb50; 1 drivers -v0x10b0a20_0 .net *"_s1", 0 0, L_0x128fcb0; 1 drivers -S_0x10b0b00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10ae850; - .timescale -9 -12; -P_0x10b0d10 .param/l "i" 0 4 54, +C4<0111>; -L_0x128fa20/d .functor AND 1, L_0x1290160, L_0x1290350, C4<1>, C4<1>; -L_0x128fa20 .delay 1 (30000,30000,30000) L_0x128fa20/d; -v0x10b0dd0_0 .net *"_s0", 0 0, L_0x1290160; 1 drivers -v0x10b0eb0_0 .net *"_s1", 0 0, L_0x1290350; 1 drivers -S_0x10b1a70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10ae600; +v0x2b7f130_0 .net "A", 7 0, L_0x2d75c60; alias, 1 drivers +v0x2b7f230_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b7f2f0_0 .net *"_s0", 0 0, L_0x2d764e0; 1 drivers +v0x2b7f3b0_0 .net *"_s12", 0 0, L_0x2d76ea0; 1 drivers +v0x2b7f490_0 .net *"_s16", 0 0, L_0x2d77200; 1 drivers +v0x2b7f5c0_0 .net *"_s20", 0 0, L_0x2d77630; 1 drivers +v0x2b7f6a0_0 .net *"_s24", 0 0, L_0x2d77960; 1 drivers +v0x2b7f780_0 .net *"_s28", 0 0, L_0x2d778f0; 1 drivers +v0x2b7f860_0 .net *"_s4", 0 0, L_0x2d76880; 1 drivers +v0x2b7f9d0_0 .net *"_s8", 0 0, L_0x2d76b90; 1 drivers +v0x2b7fab0_0 .net "out", 7 0, L_0x2d77cf0; alias, 1 drivers +L_0x2d765f0 .part L_0x2d75c60, 0, 1; +L_0x2d767e0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d76940 .part L_0x2d75c60, 1, 1; +L_0x2d76aa0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d76c50 .part L_0x2d75c60, 2, 1; +L_0x2d76db0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d76f60 .part L_0x2d75c60, 3, 1; +L_0x2d770c0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d772c0 .part L_0x2d75c60, 4, 1; +L_0x2d77530 .part v0x2cdd2e0_0, 4, 1; +L_0x2d776a0 .part L_0x2d75c60, 5, 1; +L_0x2d77800 .part v0x2cdd2e0_0, 5, 1; +L_0x2d77a20 .part L_0x2d75c60, 6, 1; +L_0x2d77b80 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d77cf0_0_0 .concat8 [ 1 1 1 1], L_0x2d764e0, L_0x2d76880, L_0x2d76b90, L_0x2d76ea0; +LS_0x2d77cf0_0_4 .concat8 [ 1 1 1 1], L_0x2d77200, L_0x2d77630, L_0x2d77960, L_0x2d778f0; +L_0x2d77cf0 .concat8 [ 4 4 0 0], LS_0x2d77cf0_0_0, LS_0x2d77cf0_0_4; +L_0x2d780b0 .part L_0x2d75c60, 7, 1; +L_0x2d782a0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b7cc30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7ce40 .param/l "i" 0 4 54, +C4<00>; +L_0x2d764e0/d .functor AND 1, L_0x2d765f0, L_0x2d767e0, C4<1>, C4<1>; +L_0x2d764e0 .delay 1 (30000,30000,30000) L_0x2d764e0/d; +v0x2b7cf20_0 .net *"_s0", 0 0, L_0x2d765f0; 1 drivers +v0x2b7d000_0 .net *"_s1", 0 0, L_0x2d767e0; 1 drivers +S_0x2b7d0e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7d2f0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d76880/d .functor AND 1, L_0x2d76940, L_0x2d76aa0, C4<1>, C4<1>; +L_0x2d76880 .delay 1 (30000,30000,30000) L_0x2d76880/d; +v0x2b7d3b0_0 .net *"_s0", 0 0, L_0x2d76940; 1 drivers +v0x2b7d490_0 .net *"_s1", 0 0, L_0x2d76aa0; 1 drivers +S_0x2b7d570 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7d7b0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d76b90/d .functor AND 1, L_0x2d76c50, L_0x2d76db0, C4<1>, C4<1>; +L_0x2d76b90 .delay 1 (30000,30000,30000) L_0x2d76b90/d; +v0x2b7d850_0 .net *"_s0", 0 0, L_0x2d76c50; 1 drivers +v0x2b7d930_0 .net *"_s1", 0 0, L_0x2d76db0; 1 drivers +S_0x2b7da10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7dc20 .param/l "i" 0 4 54, +C4<011>; +L_0x2d76ea0/d .functor AND 1, L_0x2d76f60, L_0x2d770c0, C4<1>, C4<1>; +L_0x2d76ea0 .delay 1 (30000,30000,30000) L_0x2d76ea0/d; +v0x2b7dce0_0 .net *"_s0", 0 0, L_0x2d76f60; 1 drivers +v0x2b7ddc0_0 .net *"_s1", 0 0, L_0x2d770c0; 1 drivers +S_0x2b7dea0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7e100 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d77200/d .functor AND 1, L_0x2d772c0, L_0x2d77530, C4<1>, C4<1>; +L_0x2d77200 .delay 1 (30000,30000,30000) L_0x2d77200/d; +v0x2b7e1c0_0 .net *"_s0", 0 0, L_0x2d772c0; 1 drivers +v0x2b7e2a0_0 .net *"_s1", 0 0, L_0x2d77530; 1 drivers +S_0x2b7e380 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7e590 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d77630/d .functor AND 1, L_0x2d776a0, L_0x2d77800, C4<1>, C4<1>; +L_0x2d77630 .delay 1 (30000,30000,30000) L_0x2d77630/d; +v0x2b7e650_0 .net *"_s0", 0 0, L_0x2d776a0; 1 drivers +v0x2b7e730_0 .net *"_s1", 0 0, L_0x2d77800; 1 drivers +S_0x2b7e810 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7ea20 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d77960/d .functor AND 1, L_0x2d77a20, L_0x2d77b80, C4<1>, C4<1>; +L_0x2d77960 .delay 1 (30000,30000,30000) L_0x2d77960/d; +v0x2b7eae0_0 .net *"_s0", 0 0, L_0x2d77a20; 1 drivers +v0x2b7ebc0_0 .net *"_s1", 0 0, L_0x2d77b80; 1 drivers +S_0x2b7eca0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b7c9f0; + .timescale -9 -12; +P_0x2b7eeb0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d778f0/d .functor AND 1, L_0x2d780b0, L_0x2d782a0, C4<1>, C4<1>; +L_0x2d778f0 .delay 1 (30000,30000,30000) L_0x2d778f0/d; +v0x2b7ef70_0 .net *"_s0", 0 0, L_0x2d780b0; 1 drivers +v0x2b7f050_0 .net *"_s1", 0 0, L_0x2d782a0; 1 drivers +S_0x2b7fc10 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b7c7a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1291da0/d .functor OR 1, L_0x1291e60, L_0x1292010, C4<0>, C4<0>; -L_0x1291da0 .delay 1 (30000,30000,30000) L_0x1291da0/d; -v0x10b35c0_0 .net *"_s10", 0 0, L_0x1291e60; 1 drivers -v0x10b36a0_0 .net *"_s12", 0 0, L_0x1292010; 1 drivers -v0x10b3780_0 .net "in", 7 0, L_0x128fda0; alias, 1 drivers -v0x10b3850_0 .net "ors", 1 0, L_0x1291bc0; 1 drivers -v0x10b3910_0 .net "out", 0 0, L_0x1291da0; alias, 1 drivers -L_0x1290f90 .part L_0x128fda0, 0, 4; -L_0x1291bc0 .concat8 [ 1 1 0 0], L_0x1290c80, L_0x12918b0; -L_0x1291d00 .part L_0x128fda0, 4, 4; -L_0x1291e60 .part L_0x1291bc0, 0, 1; -L_0x1292010 .part L_0x1291bc0, 1, 1; -S_0x10b1c30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10b1a70; +L_0x2d79cf0/d .functor OR 1, L_0x2d79db0, L_0x2d79f60, C4<0>, C4<0>; +L_0x2d79cf0 .delay 1 (30000,30000,30000) L_0x2d79cf0/d; +v0x2b81760_0 .net *"_s10", 0 0, L_0x2d79db0; 1 drivers +v0x2b81840_0 .net *"_s12", 0 0, L_0x2d79f60; 1 drivers +v0x2b81920_0 .net "in", 7 0, L_0x2d77cf0; alias, 1 drivers +v0x2b819f0_0 .net "ors", 1 0, L_0x2d79b10; 1 drivers +v0x2b81ab0_0 .net "out", 0 0, L_0x2d79cf0; alias, 1 drivers +L_0x2d78ee0 .part L_0x2d77cf0, 0, 4; +L_0x2d79b10 .concat8 [ 1 1 0 0], L_0x2d78bd0, L_0x2d79800; +L_0x2d79c50 .part L_0x2d77cf0, 4, 4; +L_0x2d79db0 .part L_0x2d79b10, 0, 1; +L_0x2d79f60 .part L_0x2d79b10, 1, 1; +S_0x2b7fdd0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b7fc10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1290440/d .functor OR 1, L_0x1290500, L_0x1290660, C4<0>, C4<0>; -L_0x1290440 .delay 1 (30000,30000,30000) L_0x1290440/d; -L_0x1290890/d .functor OR 1, L_0x12909a0, L_0x1290b00, C4<0>, C4<0>; -L_0x1290890 .delay 1 (30000,30000,30000) L_0x1290890/d; -L_0x1290c80/d .functor OR 1, L_0x1290cf0, L_0x1290ea0, C4<0>, C4<0>; -L_0x1290c80 .delay 1 (30000,30000,30000) L_0x1290c80/d; -v0x10b1e80_0 .net *"_s0", 0 0, L_0x1290440; 1 drivers -v0x10b1f80_0 .net *"_s10", 0 0, L_0x12909a0; 1 drivers -v0x10b2060_0 .net *"_s12", 0 0, L_0x1290b00; 1 drivers -v0x10b2120_0 .net *"_s14", 0 0, L_0x1290cf0; 1 drivers -v0x10b2200_0 .net *"_s16", 0 0, L_0x1290ea0; 1 drivers -v0x10b2330_0 .net *"_s3", 0 0, L_0x1290500; 1 drivers -v0x10b2410_0 .net *"_s5", 0 0, L_0x1290660; 1 drivers -v0x10b24f0_0 .net *"_s6", 0 0, L_0x1290890; 1 drivers -v0x10b25d0_0 .net "in", 3 0, L_0x1290f90; 1 drivers -v0x10b2740_0 .net "ors", 1 0, L_0x12907a0; 1 drivers -v0x10b2820_0 .net "out", 0 0, L_0x1290c80; 1 drivers -L_0x1290500 .part L_0x1290f90, 0, 1; -L_0x1290660 .part L_0x1290f90, 1, 1; -L_0x12907a0 .concat8 [ 1 1 0 0], L_0x1290440, L_0x1290890; -L_0x12909a0 .part L_0x1290f90, 2, 1; -L_0x1290b00 .part L_0x1290f90, 3, 1; -L_0x1290cf0 .part L_0x12907a0, 0, 1; -L_0x1290ea0 .part L_0x12907a0, 1, 1; -S_0x10b2940 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10b1a70; +L_0x2d78390/d .functor OR 1, L_0x2d78450, L_0x2d785b0, C4<0>, C4<0>; +L_0x2d78390 .delay 1 (30000,30000,30000) L_0x2d78390/d; +L_0x2d787e0/d .functor OR 1, L_0x2d788f0, L_0x2d78a50, C4<0>, C4<0>; +L_0x2d787e0 .delay 1 (30000,30000,30000) L_0x2d787e0/d; +L_0x2d78bd0/d .functor OR 1, L_0x2d78c40, L_0x2d78df0, C4<0>, C4<0>; +L_0x2d78bd0 .delay 1 (30000,30000,30000) L_0x2d78bd0/d; +v0x2b80020_0 .net *"_s0", 0 0, L_0x2d78390; 1 drivers +v0x2b80120_0 .net *"_s10", 0 0, L_0x2d788f0; 1 drivers +v0x2b80200_0 .net *"_s12", 0 0, L_0x2d78a50; 1 drivers +v0x2b802c0_0 .net *"_s14", 0 0, L_0x2d78c40; 1 drivers +v0x2b803a0_0 .net *"_s16", 0 0, L_0x2d78df0; 1 drivers +v0x2b804d0_0 .net *"_s3", 0 0, L_0x2d78450; 1 drivers +v0x2b805b0_0 .net *"_s5", 0 0, L_0x2d785b0; 1 drivers +v0x2b80690_0 .net *"_s6", 0 0, L_0x2d787e0; 1 drivers +v0x2b80770_0 .net "in", 3 0, L_0x2d78ee0; 1 drivers +v0x2b808e0_0 .net "ors", 1 0, L_0x2d786f0; 1 drivers +v0x2b809c0_0 .net "out", 0 0, L_0x2d78bd0; 1 drivers +L_0x2d78450 .part L_0x2d78ee0, 0, 1; +L_0x2d785b0 .part L_0x2d78ee0, 1, 1; +L_0x2d786f0 .concat8 [ 1 1 0 0], L_0x2d78390, L_0x2d787e0; +L_0x2d788f0 .part L_0x2d78ee0, 2, 1; +L_0x2d78a50 .part L_0x2d78ee0, 3, 1; +L_0x2d78c40 .part L_0x2d786f0, 0, 1; +L_0x2d78df0 .part L_0x2d786f0, 1, 1; +S_0x2b80ae0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b7fc10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12910c0/d .functor OR 1, L_0x1291130, L_0x1291290, C4<0>, C4<0>; -L_0x12910c0 .delay 1 (30000,30000,30000) L_0x12910c0/d; -L_0x12914c0/d .functor OR 1, L_0x12915d0, L_0x1291730, C4<0>, C4<0>; -L_0x12914c0 .delay 1 (30000,30000,30000) L_0x12914c0/d; -L_0x12918b0/d .functor OR 1, L_0x1291920, L_0x1291ad0, C4<0>, C4<0>; -L_0x12918b0 .delay 1 (30000,30000,30000) L_0x12918b0/d; -v0x10b2b00_0 .net *"_s0", 0 0, L_0x12910c0; 1 drivers -v0x10b2c00_0 .net *"_s10", 0 0, L_0x12915d0; 1 drivers -v0x10b2ce0_0 .net *"_s12", 0 0, L_0x1291730; 1 drivers -v0x10b2da0_0 .net *"_s14", 0 0, L_0x1291920; 1 drivers -v0x10b2e80_0 .net *"_s16", 0 0, L_0x1291ad0; 1 drivers -v0x10b2fb0_0 .net *"_s3", 0 0, L_0x1291130; 1 drivers -v0x10b3090_0 .net *"_s5", 0 0, L_0x1291290; 1 drivers -v0x10b3170_0 .net *"_s6", 0 0, L_0x12914c0; 1 drivers -v0x10b3250_0 .net "in", 3 0, L_0x1291d00; 1 drivers -v0x10b33c0_0 .net "ors", 1 0, L_0x12913d0; 1 drivers -v0x10b34a0_0 .net "out", 0 0, L_0x12918b0; 1 drivers -L_0x1291130 .part L_0x1291d00, 0, 1; -L_0x1291290 .part L_0x1291d00, 1, 1; -L_0x12913d0 .concat8 [ 1 1 0 0], L_0x12910c0, L_0x12914c0; -L_0x12915d0 .part L_0x1291d00, 2, 1; -L_0x1291730 .part L_0x1291d00, 3, 1; -L_0x1291920 .part L_0x12913d0, 0, 1; -L_0x1291ad0 .part L_0x12913d0, 1, 1; -S_0x10b3db0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10a7730; +L_0x2d79010/d .functor OR 1, L_0x2d79080, L_0x2d791e0, C4<0>, C4<0>; +L_0x2d79010 .delay 1 (30000,30000,30000) L_0x2d79010/d; +L_0x2d79410/d .functor OR 1, L_0x2d79520, L_0x2d79680, C4<0>, C4<0>; +L_0x2d79410 .delay 1 (30000,30000,30000) L_0x2d79410/d; +L_0x2d79800/d .functor OR 1, L_0x2d79870, L_0x2d79a20, C4<0>, C4<0>; +L_0x2d79800 .delay 1 (30000,30000,30000) L_0x2d79800/d; +v0x2b80ca0_0 .net *"_s0", 0 0, L_0x2d79010; 1 drivers +v0x2b80da0_0 .net *"_s10", 0 0, L_0x2d79520; 1 drivers +v0x2b80e80_0 .net *"_s12", 0 0, L_0x2d79680; 1 drivers +v0x2b80f40_0 .net *"_s14", 0 0, L_0x2d79870; 1 drivers +v0x2b81020_0 .net *"_s16", 0 0, L_0x2d79a20; 1 drivers +v0x2b81150_0 .net *"_s3", 0 0, L_0x2d79080; 1 drivers +v0x2b81230_0 .net *"_s5", 0 0, L_0x2d791e0; 1 drivers +v0x2b81310_0 .net *"_s6", 0 0, L_0x2d79410; 1 drivers +v0x2b813f0_0 .net "in", 3 0, L_0x2d79c50; 1 drivers +v0x2b81560_0 .net "ors", 1 0, L_0x2d79320; 1 drivers +v0x2b81640_0 .net "out", 0 0, L_0x2d79800; 1 drivers +L_0x2d79080 .part L_0x2d79c50, 0, 1; +L_0x2d791e0 .part L_0x2d79c50, 1, 1; +L_0x2d79320 .concat8 [ 1 1 0 0], L_0x2d79010, L_0x2d79410; +L_0x2d79520 .part L_0x2d79c50, 2, 1; +L_0x2d79680 .part L_0x2d79c50, 3, 1; +L_0x2d79870 .part L_0x2d79320, 0, 1; +L_0x2d79a20 .part L_0x2d79320, 1, 1; +S_0x2b81f50 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b758d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -8102,80 +8569,80 @@ S_0x10b3db0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10a7730; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x128d650/d .functor XNOR 1, L_0x1295b80, L_0x1247990, C4<0>, C4<0>; -L_0x128d650 .delay 1 (20000,20000,20000) L_0x128d650/d; -L_0x128d8c0/d .functor AND 1, L_0x1295b80, L_0x128c540, C4<1>, C4<1>; -L_0x128d8c0 .delay 1 (30000,30000,30000) L_0x128d8c0/d; -L_0x128d930/d .functor AND 1, L_0x128d650, L_0x1247b40, C4<1>, C4<1>; -L_0x128d930 .delay 1 (30000,30000,30000) L_0x128d930/d; -L_0x128da90/d .functor OR 1, L_0x128d930, L_0x128d8c0, C4<0>, C4<0>; -L_0x128da90 .delay 1 (30000,30000,30000) L_0x128da90/d; -v0x10b4060_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers -v0x10b4150_0 .net "a_", 0 0, L_0x128c3e0; alias, 1 drivers -v0x10b4210_0 .net "b", 0 0, L_0x1247990; alias, 1 drivers -v0x10b4300_0 .net "b_", 0 0, L_0x128c540; alias, 1 drivers -v0x10b43a0_0 .net "carryin", 0 0, L_0x1247b40; alias, 1 drivers -v0x10b44e0_0 .net "eq", 0 0, L_0x128d650; 1 drivers -v0x10b45a0_0 .net "lt", 0 0, L_0x128d8c0; 1 drivers -v0x10b4660_0 .net "out", 0 0, L_0x128da90; 1 drivers -v0x10b4720_0 .net "w0", 0 0, L_0x128d930; 1 drivers -S_0x10b4970 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10a7730; +L_0x2d74aa0/d .functor XNOR 1, L_0x2d7db90, L_0x2d293d0, C4<0>, C4<0>; +L_0x2d74aa0 .delay 1 (20000,20000,20000) L_0x2d74aa0/d; +L_0x2d74c20/d .functor AND 1, L_0x2d7db90, L_0x2d73830, C4<1>, C4<1>; +L_0x2d74c20 .delay 1 (30000,30000,30000) L_0x2d74c20/d; +L_0x2d74d80/d .functor AND 1, L_0x2d74aa0, L_0x2d29580, C4<1>, C4<1>; +L_0x2d74d80 .delay 1 (30000,30000,30000) L_0x2d74d80/d; +L_0x2d74e90/d .functor OR 1, L_0x2d74d80, L_0x2d74c20, C4<0>, C4<0>; +L_0x2d74e90 .delay 1 (30000,30000,30000) L_0x2d74e90/d; +v0x2b82200_0 .net "a", 0 0, L_0x2d7db90; alias, 1 drivers +v0x2b822f0_0 .net "a_", 0 0, L_0x2d736d0; alias, 1 drivers +v0x2b823b0_0 .net "b", 0 0, L_0x2d293d0; alias, 1 drivers +v0x2b824a0_0 .net "b_", 0 0, L_0x2d73830; alias, 1 drivers +v0x2b82540_0 .net "carryin", 0 0, L_0x2d29580; alias, 1 drivers +v0x2b82680_0 .net "eq", 0 0, L_0x2d74aa0; 1 drivers +v0x2b82740_0 .net "lt", 0 0, L_0x2d74c20; 1 drivers +v0x2b82800_0 .net "out", 0 0, L_0x2d74e90; 1 drivers +v0x2b828c0_0 .net "w0", 0 0, L_0x2d74d80; 1 drivers +S_0x2b82b10 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b758d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x128d430/d .functor OR 1, L_0x128cf30, L_0x10b5bd0, C4<0>, C4<0>; -L_0x128d430 .delay 1 (30000,30000,30000) L_0x128d430/d; -v0x10b5760_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers -v0x10b58b0_0 .net "b", 0 0, L_0x128c540; alias, 1 drivers -v0x10b5970_0 .net "c1", 0 0, L_0x128cf30; 1 drivers -v0x10b5a10_0 .net "c2", 0 0, L_0x10b5bd0; 1 drivers -v0x10b5ae0_0 .net "carryin", 0 0, L_0x1247b40; alias, 1 drivers -v0x10b5c60_0 .net "carryout", 0 0, L_0x128d430; 1 drivers -v0x10b5d00_0 .net "s1", 0 0, L_0x128ce70; 1 drivers -v0x10b5da0_0 .net "sum", 0 0, L_0x128d090; 1 drivers -S_0x10b4bc0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10b4970; +L_0x2d74680/d .functor OR 1, L_0x2d741d0, L_0x2b83d70, C4<0>, C4<0>; +L_0x2d74680 .delay 1 (30000,30000,30000) L_0x2d74680/d; +v0x2b83900_0 .net "a", 0 0, L_0x2d7db90; alias, 1 drivers +v0x2b83a50_0 .net "b", 0 0, L_0x2d73830; alias, 1 drivers +v0x2b83b10_0 .net "c1", 0 0, L_0x2d741d0; 1 drivers +v0x2b83bb0_0 .net "c2", 0 0, L_0x2b83d70; 1 drivers +v0x2b83c80_0 .net "carryin", 0 0, L_0x2d29580; alias, 1 drivers +v0x2b83e00_0 .net "carryout", 0 0, L_0x2d74680; 1 drivers +v0x2b83ea0_0 .net "s1", 0 0, L_0x2d74110; 1 drivers +v0x2b83f40_0 .net "sum", 0 0, L_0x2d74330; 1 drivers +S_0x2b82d60 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b82b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x128ce70/d .functor XOR 1, L_0x1295b80, L_0x128c540, C4<0>, C4<0>; -L_0x128ce70 .delay 1 (30000,30000,30000) L_0x128ce70/d; -L_0x128cf30/d .functor AND 1, L_0x1295b80, L_0x128c540, C4<1>, C4<1>; -L_0x128cf30 .delay 1 (30000,30000,30000) L_0x128cf30/d; -v0x10b4e20_0 .net "a", 0 0, L_0x1295b80; alias, 1 drivers -v0x10b4ee0_0 .net "b", 0 0, L_0x128c540; alias, 1 drivers -v0x10b4fa0_0 .net "carryout", 0 0, L_0x128cf30; alias, 1 drivers -v0x10b5040_0 .net "sum", 0 0, L_0x128ce70; alias, 1 drivers -S_0x10b5170 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10b4970; +L_0x2d74110/d .functor XOR 1, L_0x2d7db90, L_0x2d73830, C4<0>, C4<0>; +L_0x2d74110 .delay 1 (30000,30000,30000) L_0x2d74110/d; +L_0x2d741d0/d .functor AND 1, L_0x2d7db90, L_0x2d73830, C4<1>, C4<1>; +L_0x2d741d0 .delay 1 (30000,30000,30000) L_0x2d741d0/d; +v0x2b82fc0_0 .net "a", 0 0, L_0x2d7db90; alias, 1 drivers +v0x2b83080_0 .net "b", 0 0, L_0x2d73830; alias, 1 drivers +v0x2b83140_0 .net "carryout", 0 0, L_0x2d741d0; alias, 1 drivers +v0x2b831e0_0 .net "sum", 0 0, L_0x2d74110; alias, 1 drivers +S_0x2b83310 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b82b10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x128d090/d .functor XOR 1, L_0x128ce70, L_0x1247b40, C4<0>, C4<0>; -L_0x128d090 .delay 1 (30000,30000,30000) L_0x128d090/d; -L_0x10b5bd0/d .functor AND 1, L_0x128ce70, L_0x1247b40, C4<1>, C4<1>; -L_0x10b5bd0 .delay 1 (30000,30000,30000) L_0x10b5bd0/d; -v0x10b53d0_0 .net "a", 0 0, L_0x128ce70; alias, 1 drivers -v0x10b54a0_0 .net "b", 0 0, L_0x1247b40; alias, 1 drivers -v0x10b5540_0 .net "carryout", 0 0, L_0x10b5bd0; alias, 1 drivers -v0x10b5610_0 .net "sum", 0 0, L_0x128d090; alias, 1 drivers -S_0x10b71c0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10a7460; - .timescale -9 -12; -L_0x2b0ab3d05fd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06020 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1295c20/d .functor OR 1, L_0x2b0ab3d05fd8, L_0x2b0ab3d06020, C4<0>, C4<0>; -L_0x1295c20 .delay 1 (30000,30000,30000) L_0x1295c20/d; -v0x10b73b0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d05fd8; 1 drivers -v0x10b7490_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06020; 1 drivers -S_0x10b7570 .scope generate, "alu_slices[15]" "alu_slices[15]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x10b7780 .param/l "i" 0 3 41, +C4<01111>; -S_0x10b7840 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10b7570; +L_0x2d74330/d .functor XOR 1, L_0x2d74110, L_0x2d29580, C4<0>, C4<0>; +L_0x2d74330 .delay 1 (30000,30000,30000) L_0x2d74330/d; +L_0x2b83d70/d .functor AND 1, L_0x2d74110, L_0x2d29580, C4<1>, C4<1>; +L_0x2b83d70 .delay 1 (30000,30000,30000) L_0x2b83d70/d; +v0x2b83570_0 .net "a", 0 0, L_0x2d74110; alias, 1 drivers +v0x2b83640_0 .net "b", 0 0, L_0x2d29580; alias, 1 drivers +v0x2b836e0_0 .net "carryout", 0 0, L_0x2b83d70; alias, 1 drivers +v0x2b837b0_0 .net "sum", 0 0, L_0x2d74330; alias, 1 drivers +S_0x2b85fd0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b75600; + .timescale -9 -12; +L_0x2ac6110b9a08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9a50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d73c90/d .functor OR 1, L_0x2ac6110b9a08, L_0x2ac6110b9a50, C4<0>, C4<0>; +L_0x2d73c90 .delay 1 (30000,30000,30000) L_0x2d73c90/d; +v0x2b861c0_0 .net/2u *"_s0", 0 0, L_0x2ac6110b9a08; 1 drivers +v0x2b862a0_0 .net/2u *"_s2", 0 0, L_0x2ac6110b9a50; 1 drivers +S_0x2b86380 .scope generate, "alu_slices[15]" "alu_slices[15]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b86590 .param/l "i" 0 3 39, +C4<01111>; +S_0x2b86650 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b86380; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -8184,445 +8651,476 @@ S_0x10b7840 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10b7570; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x128c1e0/d .functor NOT 1, L_0x129fa50, C4<0>, C4<0>, C4<0>; -L_0x128c1e0 .delay 1 (10000,10000,10000) L_0x128c1e0/d; -L_0x12962c0/d .functor NOT 1, L_0x1296100, C4<0>, C4<0>, C4<0>; -L_0x12962c0 .delay 1 (10000,10000,10000) L_0x12962c0/d; -L_0x12972c0/d .functor XOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; -L_0x12972c0 .delay 1 (30000,30000,30000) L_0x12972c0/d; -L_0x2b0ab3d06068 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d060b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1297970/d .functor OR 1, L_0x2b0ab3d06068, L_0x2b0ab3d060b0, C4<0>, C4<0>; -L_0x1297970 .delay 1 (30000,30000,30000) L_0x1297970/d; -L_0x1297b70/d .functor AND 1, L_0x129fa50, L_0x1296100, C4<1>, C4<1>; -L_0x1297b70 .delay 1 (30000,30000,30000) L_0x1297b70/d; -L_0x1297c30/d .functor NAND 1, L_0x129fa50, L_0x1296100, C4<1>, C4<1>; -L_0x1297c30 .delay 1 (20000,20000,20000) L_0x1297c30/d; -L_0x1297d90/d .functor XOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; -L_0x1297d90 .delay 1 (20000,20000,20000) L_0x1297d90/d; -L_0x1298240/d .functor OR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; -L_0x1298240 .delay 1 (30000,30000,30000) L_0x1298240/d; -L_0x129f950/d .functor NOT 1, L_0x129bbb0, C4<0>, C4<0>, C4<0>; -L_0x129f950 .delay 1 (10000,10000,10000) L_0x129f950/d; -v0x10c5f70_0 .net "A", 0 0, L_0x129fa50; 1 drivers -v0x10c6030_0 .net "A_", 0 0, L_0x128c1e0; 1 drivers -v0x10c60f0_0 .net "B", 0 0, L_0x1296100; 1 drivers -v0x10c61c0_0 .net "B_", 0 0, L_0x12962c0; 1 drivers -v0x10c6260_0 .net *"_s12", 0 0, L_0x1297970; 1 drivers -v0x10c6350_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06068; 1 drivers -v0x10c6410_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d060b0; 1 drivers -v0x10c64f0_0 .net *"_s18", 0 0, L_0x1297b70; 1 drivers -v0x10c65d0_0 .net *"_s20", 0 0, L_0x1297c30; 1 drivers -v0x10c6740_0 .net *"_s22", 0 0, L_0x1297d90; 1 drivers -v0x10c6820_0 .net *"_s24", 0 0, L_0x1298240; 1 drivers -o0x2b0ab3cc8278 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10c6900_0 name=_s30 -o0x2b0ab3cc82a8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10c69e0_0 name=_s32 -v0x10c6ac0_0 .net *"_s8", 0 0, L_0x12972c0; 1 drivers -v0x10c6ba0_0 .net "carryin", 0 0, L_0x12961a0; 1 drivers -v0x10c6c40_0 .net "carryout", 0 0, L_0x129f5f0; 1 drivers -v0x10c6ce0_0 .net "carryouts", 7 0, L_0x1354750; 1 drivers -v0x10c6e90_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10c6f30_0 .net "result", 0 0, L_0x129bbb0; 1 drivers -v0x10c7020_0 .net "results", 7 0, L_0x1298010; 1 drivers -v0x10c7110_0 .net "zero", 0 0, L_0x129f950; 1 drivers -LS_0x1298010_0_0 .concat8 [ 1 1 1 1], L_0x12967e0, L_0x1296e10, L_0x12972c0, L_0x1297970; -LS_0x1298010_0_4 .concat8 [ 1 1 1 1], L_0x1297b70, L_0x1297c30, L_0x1297d90, L_0x1298240; -L_0x1298010 .concat8 [ 4 4 0 0], LS_0x1298010_0_0, LS_0x1298010_0_4; -LS_0x1354750_0_0 .concat [ 1 1 1 1], L_0x1296a90, L_0x1297160, o0x2b0ab3cc8278, L_0x12977c0; -LS_0x1354750_0_4 .concat [ 4 0 0 0], o0x2b0ab3cc82a8; -L_0x1354750 .concat [ 4 4 0 0], LS_0x1354750_0_0, LS_0x1354750_0_4; -S_0x10b7ac0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10b7840; +L_0x2d734d0/d .functor NOT 1, L_0x2d88600, C4<0>, C4<0>, C4<0>; +L_0x2d734d0 .delay 1 (10000,10000,10000) L_0x2d734d0/d; +L_0x2d7e280/d .functor NOT 1, L_0x2d7e110, C4<0>, C4<0>, C4<0>; +L_0x2d7e280 .delay 1 (10000,10000,10000) L_0x2d7e280/d; +L_0x2d7f2d0/d .functor XOR 1, L_0x2d88600, L_0x2d7e110, C4<0>, C4<0>; +L_0x2d7f2d0 .delay 1 (30000,30000,30000) L_0x2d7f2d0/d; +L_0x2ac6110b9a98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9ae0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d7f390/d .functor OR 1, L_0x2ac6110b9a98, L_0x2ac6110b9ae0, C4<0>, C4<0>; +L_0x2d7f390 .delay 1 (30000,30000,30000) L_0x2d7f390/d; +L_0x2ac6110b9b28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9b70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d7fb30/d .functor OR 1, L_0x2ac6110b9b28, L_0x2ac6110b9b70, C4<0>, C4<0>; +L_0x2d7fb30 .delay 1 (30000,30000,30000) L_0x2d7fb30/d; +L_0x2d7fd30/d .functor AND 1, L_0x2d88600, L_0x2d7e110, C4<1>, C4<1>; +L_0x2d7fd30 .delay 1 (30000,30000,30000) L_0x2d7fd30/d; +L_0x2ac6110b9bb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9c00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d7fdf0/d .functor OR 1, L_0x2ac6110b9bb8, L_0x2ac6110b9c00, C4<0>, C4<0>; +L_0x2d7fdf0 .delay 1 (30000,30000,30000) L_0x2d7fdf0/d; +L_0x2d7fff0/d .functor NAND 1, L_0x2d88600, L_0x2d7e110, C4<1>, C4<1>; +L_0x2d7fff0 .delay 1 (20000,20000,20000) L_0x2d7fff0/d; +L_0x2ac6110b9c48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9c90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d80100/d .functor OR 1, L_0x2ac6110b9c48, L_0x2ac6110b9c90, C4<0>, C4<0>; +L_0x2d80100 .delay 1 (30000,30000,30000) L_0x2d80100/d; +L_0x2d802b0/d .functor NOR 1, L_0x2d88600, L_0x2d7e110, C4<0>, C4<0>; +L_0x2d802b0 .delay 1 (20000,20000,20000) L_0x2d802b0/d; +L_0x2ac6110b9cd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9d20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d7e730/d .functor OR 1, L_0x2ac6110b9cd8, L_0x2ac6110b9d20, C4<0>, C4<0>; +L_0x2d7e730 .delay 1 (30000,30000,30000) L_0x2d7e730/d; +L_0x2d80910/d .functor OR 1, L_0x2d88600, L_0x2d7e110, C4<0>, C4<0>; +L_0x2d80910 .delay 1 (30000,30000,30000) L_0x2d80910/d; +L_0x2ac6110b9d68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9db0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d80e00/d .functor OR 1, L_0x2ac6110b9d68, L_0x2ac6110b9db0, C4<0>, C4<0>; +L_0x2d80e00 .delay 1 (30000,30000,30000) L_0x2d80e00/d; +L_0x2d88500/d .functor NOT 1, L_0x2d84760, C4<0>, C4<0>, C4<0>; +L_0x2d88500 .delay 1 (10000,10000,10000) L_0x2d88500/d; +v0x2b94d80_0 .net "A", 0 0, L_0x2d88600; 1 drivers +v0x2b94e40_0 .net "A_", 0 0, L_0x2d734d0; 1 drivers +v0x2b94f00_0 .net "B", 0 0, L_0x2d7e110; 1 drivers +v0x2b94fd0_0 .net "B_", 0 0, L_0x2d7e280; 1 drivers +v0x2b95070_0 .net *"_s11", 0 0, L_0x2d7f390; 1 drivers +v0x2b95160_0 .net/2s *"_s13", 0 0, L_0x2ac6110b9a98; 1 drivers +v0x2b95220_0 .net/2s *"_s15", 0 0, L_0x2ac6110b9ae0; 1 drivers +v0x2b95300_0 .net *"_s19", 0 0, L_0x2d7fb30; 1 drivers +v0x2b953e0_0 .net/2s *"_s21", 0 0, L_0x2ac6110b9b28; 1 drivers +v0x2b95550_0 .net/2s *"_s23", 0 0, L_0x2ac6110b9b70; 1 drivers +v0x2b95630_0 .net *"_s25", 0 0, L_0x2d7fd30; 1 drivers +v0x2b95710_0 .net *"_s28", 0 0, L_0x2d7fdf0; 1 drivers +v0x2b957f0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b9bb8; 1 drivers +v0x2b958d0_0 .net/2s *"_s32", 0 0, L_0x2ac6110b9c00; 1 drivers +v0x2b959b0_0 .net *"_s34", 0 0, L_0x2d7fff0; 1 drivers +v0x2b95a90_0 .net *"_s37", 0 0, L_0x2d80100; 1 drivers +v0x2b95b70_0 .net/2s *"_s39", 0 0, L_0x2ac6110b9c48; 1 drivers +v0x2b95d20_0 .net/2s *"_s41", 0 0, L_0x2ac6110b9c90; 1 drivers +v0x2b95dc0_0 .net *"_s43", 0 0, L_0x2d802b0; 1 drivers +v0x2b95ea0_0 .net *"_s46", 0 0, L_0x2d7e730; 1 drivers +v0x2b95f80_0 .net/2s *"_s48", 0 0, L_0x2ac6110b9cd8; 1 drivers +v0x2b96060_0 .net/2s *"_s50", 0 0, L_0x2ac6110b9d20; 1 drivers +v0x2b96140_0 .net *"_s52", 0 0, L_0x2d80910; 1 drivers +v0x2b96220_0 .net *"_s56", 0 0, L_0x2d80e00; 1 drivers +v0x2b96300_0 .net/2s *"_s59", 0 0, L_0x2ac6110b9d68; 1 drivers +v0x2b963e0_0 .net/2s *"_s61", 0 0, L_0x2ac6110b9db0; 1 drivers +v0x2b964c0_0 .net *"_s8", 0 0, L_0x2d7f2d0; 1 drivers +v0x2b965a0_0 .net "carryin", 0 0, L_0x2d7e1b0; 1 drivers +v0x2b96640_0 .net "carryout", 0 0, L_0x2d881a0; 1 drivers +v0x2b966e0_0 .net "carryouts", 7 0, L_0x2d80a90; 1 drivers +v0x2b967f0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b968b0_0 .net "result", 0 0, L_0x2d84760; 1 drivers +v0x2b969a0_0 .net "results", 7 0, L_0x2d806e0; 1 drivers +v0x2b95c80_0 .net "zero", 0 0, L_0x2d88500; 1 drivers +LS_0x2d806e0_0_0 .concat8 [ 1 1 1 1], L_0x2d7e7a0, L_0x2d7edd0, L_0x2d7f2d0, L_0x2d7fb30; +LS_0x2d806e0_0_4 .concat8 [ 1 1 1 1], L_0x2d7fd30, L_0x2d7fff0, L_0x2d802b0, L_0x2d80910; +L_0x2d806e0 .concat8 [ 4 4 0 0], LS_0x2d806e0_0_0, LS_0x2d806e0_0_4; +LS_0x2d80a90_0_0 .concat8 [ 1 1 1 1], L_0x2d7ea50, L_0x2d7f170, L_0x2d7f390, L_0x2d7f980; +LS_0x2d80a90_0_4 .concat8 [ 1 1 1 1], L_0x2d7fdf0, L_0x2d80100, L_0x2d7e730, L_0x2d80e00; +L_0x2d80a90 .concat8 [ 4 4 0 0], LS_0x2d80a90_0_0, LS_0x2d80a90_0_4; +S_0x2b868d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b86650; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1296a90/d .functor OR 1, L_0x1296570, L_0x1296930, C4<0>, C4<0>; -L_0x1296a90 .delay 1 (30000,30000,30000) L_0x1296a90/d; -v0x10b88f0_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers -v0x10b89b0_0 .net "b", 0 0, L_0x1296100; alias, 1 drivers -v0x10b8a80_0 .net "c1", 0 0, L_0x1296570; 1 drivers -v0x10b8b80_0 .net "c2", 0 0, L_0x1296930; 1 drivers -v0x10b8c50_0 .net "carryin", 0 0, L_0x12961a0; alias, 1 drivers -v0x10b8d40_0 .net "carryout", 0 0, L_0x1296a90; 1 drivers -v0x10b8de0_0 .net "s1", 0 0, L_0x12964b0; 1 drivers -v0x10b8ed0_0 .net "sum", 0 0, L_0x12967e0; 1 drivers -S_0x10b7d30 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10b7ac0; +L_0x2d7ea50/d .functor OR 1, L_0x2d7e530, L_0x2d7e8f0, C4<0>, C4<0>; +L_0x2d7ea50 .delay 1 (30000,30000,30000) L_0x2d7ea50/d; +v0x2b87700_0 .net "a", 0 0, L_0x2d88600; alias, 1 drivers +v0x2b877c0_0 .net "b", 0 0, L_0x2d7e110; alias, 1 drivers +v0x2b87890_0 .net "c1", 0 0, L_0x2d7e530; 1 drivers +v0x2b87990_0 .net "c2", 0 0, L_0x2d7e8f0; 1 drivers +v0x2b87a60_0 .net "carryin", 0 0, L_0x2d7e1b0; alias, 1 drivers +v0x2b87b50_0 .net "carryout", 0 0, L_0x2d7ea50; 1 drivers +v0x2b87bf0_0 .net "s1", 0 0, L_0x2d7e470; 1 drivers +v0x2b87ce0_0 .net "sum", 0 0, L_0x2d7e7a0; 1 drivers +S_0x2b86b40 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b868d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12964b0/d .functor XOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; -L_0x12964b0 .delay 1 (30000,30000,30000) L_0x12964b0/d; -L_0x1296570/d .functor AND 1, L_0x129fa50, L_0x1296100, C4<1>, C4<1>; -L_0x1296570 .delay 1 (30000,30000,30000) L_0x1296570/d; -v0x10b7f90_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers -v0x10b8070_0 .net "b", 0 0, L_0x1296100; alias, 1 drivers -v0x10b8130_0 .net "carryout", 0 0, L_0x1296570; alias, 1 drivers -v0x10b81d0_0 .net "sum", 0 0, L_0x12964b0; alias, 1 drivers -S_0x10b8310 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10b7ac0; +L_0x2d7e470/d .functor XOR 1, L_0x2d88600, L_0x2d7e110, C4<0>, C4<0>; +L_0x2d7e470 .delay 1 (30000,30000,30000) L_0x2d7e470/d; +L_0x2d7e530/d .functor AND 1, L_0x2d88600, L_0x2d7e110, C4<1>, C4<1>; +L_0x2d7e530 .delay 1 (30000,30000,30000) L_0x2d7e530/d; +v0x2b86da0_0 .net "a", 0 0, L_0x2d88600; alias, 1 drivers +v0x2b86e80_0 .net "b", 0 0, L_0x2d7e110; alias, 1 drivers +v0x2b86f40_0 .net "carryout", 0 0, L_0x2d7e530; alias, 1 drivers +v0x2b86fe0_0 .net "sum", 0 0, L_0x2d7e470; alias, 1 drivers +S_0x2b87120 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b868d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12967e0/d .functor XOR 1, L_0x12964b0, L_0x12961a0, C4<0>, C4<0>; -L_0x12967e0 .delay 1 (30000,30000,30000) L_0x12967e0/d; -L_0x1296930/d .functor AND 1, L_0x12964b0, L_0x12961a0, C4<1>, C4<1>; -L_0x1296930 .delay 1 (30000,30000,30000) L_0x1296930/d; -v0x10b8570_0 .net "a", 0 0, L_0x12964b0; alias, 1 drivers -v0x10b8610_0 .net "b", 0 0, L_0x12961a0; alias, 1 drivers -v0x10b86b0_0 .net "carryout", 0 0, L_0x1296930; alias, 1 drivers -v0x10b8780_0 .net "sum", 0 0, L_0x12967e0; alias, 1 drivers -S_0x10b8fa0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10b7840; +L_0x2d7e7a0/d .functor XOR 1, L_0x2d7e470, L_0x2d7e1b0, C4<0>, C4<0>; +L_0x2d7e7a0 .delay 1 (30000,30000,30000) L_0x2d7e7a0/d; +L_0x2d7e8f0/d .functor AND 1, L_0x2d7e470, L_0x2d7e1b0, C4<1>, C4<1>; +L_0x2d7e8f0 .delay 1 (30000,30000,30000) L_0x2d7e8f0/d; +v0x2b87380_0 .net "a", 0 0, L_0x2d7e470; alias, 1 drivers +v0x2b87420_0 .net "b", 0 0, L_0x2d7e1b0; alias, 1 drivers +v0x2b874c0_0 .net "carryout", 0 0, L_0x2d7e8f0; alias, 1 drivers +v0x2b87590_0 .net "sum", 0 0, L_0x2d7e7a0; alias, 1 drivers +S_0x2b87db0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b86650; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10be390_0 .net "ands", 7 0, L_0x129d5f0; 1 drivers -v0x10be4a0_0 .net "in", 7 0, L_0x1354750; alias, 1 drivers -v0x10be560_0 .net "out", 0 0, L_0x129f5f0; alias, 1 drivers -v0x10be630_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10b91c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10b8fa0; +v0x2b8d1a0_0 .net "ands", 7 0, L_0x2d861a0; 1 drivers +v0x2b8d2b0_0 .net "in", 7 0, L_0x2d80a90; alias, 1 drivers +v0x2b8d370_0 .net "out", 0 0, L_0x2d881a0; alias, 1 drivers +v0x2b8d440_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b87fd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b87db0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10bb8f0_0 .net "A", 7 0, L_0x1354750; alias, 1 drivers -v0x10bb9f0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10bbab0_0 .net *"_s0", 0 0, L_0x129bf10; 1 drivers -v0x10bbb70_0 .net *"_s12", 0 0, L_0x129c880; 1 drivers -v0x10bbc50_0 .net *"_s16", 0 0, L_0x129cbe0; 1 drivers -v0x10bbd80_0 .net *"_s20", 0 0, L_0x129cef0; 1 drivers -v0x10bbe60_0 .net *"_s24", 0 0, L_0x129d2e0; 1 drivers -v0x10bbf40_0 .net *"_s28", 0 0, L_0x129d270; 1 drivers -v0x10bc020_0 .net *"_s4", 0 0, L_0x129c220; 1 drivers -v0x10bc190_0 .net *"_s8", 0 0, L_0x129c570; 1 drivers -v0x10bc270_0 .net "out", 7 0, L_0x129d5f0; alias, 1 drivers -L_0x129bfd0 .part L_0x1354750, 0, 1; -L_0x129c130 .part v0x12010b0_0, 0, 1; -L_0x129c2e0 .part L_0x1354750, 1, 1; -L_0x129c4d0 .part v0x12010b0_0, 1, 1; -L_0x129c630 .part L_0x1354750, 2, 1; -L_0x129c790 .part v0x12010b0_0, 2, 1; -L_0x129c940 .part L_0x1354750, 3, 1; -L_0x129caa0 .part v0x12010b0_0, 3, 1; -L_0x129cca0 .part L_0x1354750, 4, 1; -L_0x129ce00 .part v0x12010b0_0, 4, 1; -L_0x129cf60 .part L_0x1354750, 5, 1; -L_0x129d1d0 .part v0x12010b0_0, 5, 1; -L_0x129d3a0 .part L_0x1354750, 6, 1; -L_0x129d500 .part v0x12010b0_0, 6, 1; -LS_0x129d5f0_0_0 .concat8 [ 1 1 1 1], L_0x129bf10, L_0x129c220, L_0x129c570, L_0x129c880; -LS_0x129d5f0_0_4 .concat8 [ 1 1 1 1], L_0x129cbe0, L_0x129cef0, L_0x129d2e0, L_0x129d270; -L_0x129d5f0 .concat8 [ 4 4 0 0], LS_0x129d5f0_0_0, LS_0x129d5f0_0_4; -L_0x129d9b0 .part L_0x1354750, 7, 1; -L_0x129dba0 .part v0x12010b0_0, 7, 1; -S_0x10b9420 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10b9630 .param/l "i" 0 4 54, +C4<00>; -L_0x129bf10/d .functor AND 1, L_0x129bfd0, L_0x129c130, C4<1>, C4<1>; -L_0x129bf10 .delay 1 (30000,30000,30000) L_0x129bf10/d; -v0x10b9710_0 .net *"_s0", 0 0, L_0x129bfd0; 1 drivers -v0x10b97f0_0 .net *"_s1", 0 0, L_0x129c130; 1 drivers -S_0x10b98d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10b9ae0 .param/l "i" 0 4 54, +C4<01>; -L_0x129c220/d .functor AND 1, L_0x129c2e0, L_0x129c4d0, C4<1>, C4<1>; -L_0x129c220 .delay 1 (30000,30000,30000) L_0x129c220/d; -v0x10b9ba0_0 .net *"_s0", 0 0, L_0x129c2e0; 1 drivers -v0x10b9c80_0 .net *"_s1", 0 0, L_0x129c4d0; 1 drivers -S_0x10b9d60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10b9f70 .param/l "i" 0 4 54, +C4<010>; -L_0x129c570/d .functor AND 1, L_0x129c630, L_0x129c790, C4<1>, C4<1>; -L_0x129c570 .delay 1 (30000,30000,30000) L_0x129c570/d; -v0x10ba010_0 .net *"_s0", 0 0, L_0x129c630; 1 drivers -v0x10ba0f0_0 .net *"_s1", 0 0, L_0x129c790; 1 drivers -S_0x10ba1d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10ba3e0 .param/l "i" 0 4 54, +C4<011>; -L_0x129c880/d .functor AND 1, L_0x129c940, L_0x129caa0, C4<1>, C4<1>; -L_0x129c880 .delay 1 (30000,30000,30000) L_0x129c880/d; -v0x10ba4a0_0 .net *"_s0", 0 0, L_0x129c940; 1 drivers -v0x10ba580_0 .net *"_s1", 0 0, L_0x129caa0; 1 drivers -S_0x10ba660 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10ba8c0 .param/l "i" 0 4 54, +C4<0100>; -L_0x129cbe0/d .functor AND 1, L_0x129cca0, L_0x129ce00, C4<1>, C4<1>; -L_0x129cbe0 .delay 1 (30000,30000,30000) L_0x129cbe0/d; -v0x10ba980_0 .net *"_s0", 0 0, L_0x129cca0; 1 drivers -v0x10baa60_0 .net *"_s1", 0 0, L_0x129ce00; 1 drivers -S_0x10bab40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10bad50 .param/l "i" 0 4 54, +C4<0101>; -L_0x129cef0/d .functor AND 1, L_0x129cf60, L_0x129d1d0, C4<1>, C4<1>; -L_0x129cef0 .delay 1 (30000,30000,30000) L_0x129cef0/d; -v0x10bae10_0 .net *"_s0", 0 0, L_0x129cf60; 1 drivers -v0x10baef0_0 .net *"_s1", 0 0, L_0x129d1d0; 1 drivers -S_0x10bafd0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10bb1e0 .param/l "i" 0 4 54, +C4<0110>; -L_0x129d2e0/d .functor AND 1, L_0x129d3a0, L_0x129d500, C4<1>, C4<1>; -L_0x129d2e0 .delay 1 (30000,30000,30000) L_0x129d2e0/d; -v0x10bb2a0_0 .net *"_s0", 0 0, L_0x129d3a0; 1 drivers -v0x10bb380_0 .net *"_s1", 0 0, L_0x129d500; 1 drivers -S_0x10bb460 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10b91c0; - .timescale -9 -12; -P_0x10bb670 .param/l "i" 0 4 54, +C4<0111>; -L_0x129d270/d .functor AND 1, L_0x129d9b0, L_0x129dba0, C4<1>, C4<1>; -L_0x129d270 .delay 1 (30000,30000,30000) L_0x129d270/d; -v0x10bb730_0 .net *"_s0", 0 0, L_0x129d9b0; 1 drivers -v0x10bb810_0 .net *"_s1", 0 0, L_0x129dba0; 1 drivers -S_0x10bc3d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10b8fa0; +v0x2b8a700_0 .net "A", 7 0, L_0x2d80a90; alias, 1 drivers +v0x2b8a800_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b8a8c0_0 .net *"_s0", 0 0, L_0x2d84ac0; 1 drivers +v0x2b8a980_0 .net *"_s12", 0 0, L_0x2d85430; 1 drivers +v0x2b8aa60_0 .net *"_s16", 0 0, L_0x2d85790; 1 drivers +v0x2b8ab90_0 .net *"_s20", 0 0, L_0x2d85b60; 1 drivers +v0x2b8ac70_0 .net *"_s24", 0 0, L_0x2d85e90; 1 drivers +v0x2b8ad50_0 .net *"_s28", 0 0, L_0x2d85e20; 1 drivers +v0x2b8ae30_0 .net *"_s4", 0 0, L_0x2d84e10; 1 drivers +v0x2b8afa0_0 .net *"_s8", 0 0, L_0x2d85120; 1 drivers +v0x2b8b080_0 .net "out", 7 0, L_0x2d861a0; alias, 1 drivers +L_0x2d84b80 .part L_0x2d80a90, 0, 1; +L_0x2d84d70 .part v0x2cdd2e0_0, 0, 1; +L_0x2d84ed0 .part L_0x2d80a90, 1, 1; +L_0x2d85030 .part v0x2cdd2e0_0, 1, 1; +L_0x2d851e0 .part L_0x2d80a90, 2, 1; +L_0x2d85340 .part v0x2cdd2e0_0, 2, 1; +L_0x2d854f0 .part L_0x2d80a90, 3, 1; +L_0x2d85650 .part v0x2cdd2e0_0, 3, 1; +L_0x2d85850 .part L_0x2d80a90, 4, 1; +L_0x2d85ac0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d85bd0 .part L_0x2d80a90, 5, 1; +L_0x2d85d30 .part v0x2cdd2e0_0, 5, 1; +L_0x2d85f50 .part L_0x2d80a90, 6, 1; +L_0x2d860b0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d861a0_0_0 .concat8 [ 1 1 1 1], L_0x2d84ac0, L_0x2d84e10, L_0x2d85120, L_0x2d85430; +LS_0x2d861a0_0_4 .concat8 [ 1 1 1 1], L_0x2d85790, L_0x2d85b60, L_0x2d85e90, L_0x2d85e20; +L_0x2d861a0 .concat8 [ 4 4 0 0], LS_0x2d861a0_0_0, LS_0x2d861a0_0_4; +L_0x2d86560 .part L_0x2d80a90, 7, 1; +L_0x2d86750 .part v0x2cdd2e0_0, 7, 1; +S_0x2b88230 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b88440 .param/l "i" 0 4 54, +C4<00>; +L_0x2d84ac0/d .functor AND 1, L_0x2d84b80, L_0x2d84d70, C4<1>, C4<1>; +L_0x2d84ac0 .delay 1 (30000,30000,30000) L_0x2d84ac0/d; +v0x2b88520_0 .net *"_s0", 0 0, L_0x2d84b80; 1 drivers +v0x2b88600_0 .net *"_s1", 0 0, L_0x2d84d70; 1 drivers +S_0x2b886e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b888f0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d84e10/d .functor AND 1, L_0x2d84ed0, L_0x2d85030, C4<1>, C4<1>; +L_0x2d84e10 .delay 1 (30000,30000,30000) L_0x2d84e10/d; +v0x2b889b0_0 .net *"_s0", 0 0, L_0x2d84ed0; 1 drivers +v0x2b88a90_0 .net *"_s1", 0 0, L_0x2d85030; 1 drivers +S_0x2b88b70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b88d80 .param/l "i" 0 4 54, +C4<010>; +L_0x2d85120/d .functor AND 1, L_0x2d851e0, L_0x2d85340, C4<1>, C4<1>; +L_0x2d85120 .delay 1 (30000,30000,30000) L_0x2d85120/d; +v0x2b88e20_0 .net *"_s0", 0 0, L_0x2d851e0; 1 drivers +v0x2b88f00_0 .net *"_s1", 0 0, L_0x2d85340; 1 drivers +S_0x2b88fe0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b891f0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d85430/d .functor AND 1, L_0x2d854f0, L_0x2d85650, C4<1>, C4<1>; +L_0x2d85430 .delay 1 (30000,30000,30000) L_0x2d85430/d; +v0x2b892b0_0 .net *"_s0", 0 0, L_0x2d854f0; 1 drivers +v0x2b89390_0 .net *"_s1", 0 0, L_0x2d85650; 1 drivers +S_0x2b89470 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b896d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d85790/d .functor AND 1, L_0x2d85850, L_0x2d85ac0, C4<1>, C4<1>; +L_0x2d85790 .delay 1 (30000,30000,30000) L_0x2d85790/d; +v0x2b89790_0 .net *"_s0", 0 0, L_0x2d85850; 1 drivers +v0x2b89870_0 .net *"_s1", 0 0, L_0x2d85ac0; 1 drivers +S_0x2b89950 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b89b60 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d85b60/d .functor AND 1, L_0x2d85bd0, L_0x2d85d30, C4<1>, C4<1>; +L_0x2d85b60 .delay 1 (30000,30000,30000) L_0x2d85b60/d; +v0x2b89c20_0 .net *"_s0", 0 0, L_0x2d85bd0; 1 drivers +v0x2b89d00_0 .net *"_s1", 0 0, L_0x2d85d30; 1 drivers +S_0x2b89de0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b89ff0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d85e90/d .functor AND 1, L_0x2d85f50, L_0x2d860b0, C4<1>, C4<1>; +L_0x2d85e90 .delay 1 (30000,30000,30000) L_0x2d85e90/d; +v0x2b8a0b0_0 .net *"_s0", 0 0, L_0x2d85f50; 1 drivers +v0x2b8a190_0 .net *"_s1", 0 0, L_0x2d860b0; 1 drivers +S_0x2b8a270 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b87fd0; + .timescale -9 -12; +P_0x2b8a480 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d85e20/d .functor AND 1, L_0x2d86560, L_0x2d86750, C4<1>, C4<1>; +L_0x2d85e20 .delay 1 (30000,30000,30000) L_0x2d85e20/d; +v0x2b8a540_0 .net *"_s0", 0 0, L_0x2d86560; 1 drivers +v0x2b8a620_0 .net *"_s1", 0 0, L_0x2d86750; 1 drivers +S_0x2b8b1e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b87db0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x129f5f0/d .functor OR 1, L_0x129f6b0, L_0x129f860, C4<0>, C4<0>; -L_0x129f5f0 .delay 1 (30000,30000,30000) L_0x129f5f0/d; -v0x10bdf20_0 .net *"_s10", 0 0, L_0x129f6b0; 1 drivers -v0x10be000_0 .net *"_s12", 0 0, L_0x129f860; 1 drivers -v0x10be0e0_0 .net "in", 7 0, L_0x129d5f0; alias, 1 drivers -v0x10be1b0_0 .net "ors", 1 0, L_0x129f410; 1 drivers -v0x10be270_0 .net "out", 0 0, L_0x129f5f0; alias, 1 drivers -L_0x129e7e0 .part L_0x129d5f0, 0, 4; -L_0x129f410 .concat8 [ 1 1 0 0], L_0x129e4d0, L_0x129f100; -L_0x129f550 .part L_0x129d5f0, 4, 4; -L_0x129f6b0 .part L_0x129f410, 0, 1; -L_0x129f860 .part L_0x129f410, 1, 1; -S_0x10bc590 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10bc3d0; +L_0x2d881a0/d .functor OR 1, L_0x2d88260, L_0x2d88410, C4<0>, C4<0>; +L_0x2d881a0 .delay 1 (30000,30000,30000) L_0x2d881a0/d; +v0x2b8cd30_0 .net *"_s10", 0 0, L_0x2d88260; 1 drivers +v0x2b8ce10_0 .net *"_s12", 0 0, L_0x2d88410; 1 drivers +v0x2b8cef0_0 .net "in", 7 0, L_0x2d861a0; alias, 1 drivers +v0x2b8cfc0_0 .net "ors", 1 0, L_0x2d87fc0; 1 drivers +v0x2b8d080_0 .net "out", 0 0, L_0x2d881a0; alias, 1 drivers +L_0x2d87390 .part L_0x2d861a0, 0, 4; +L_0x2d87fc0 .concat8 [ 1 1 0 0], L_0x2d87080, L_0x2d87cb0; +L_0x2d88100 .part L_0x2d861a0, 4, 4; +L_0x2d88260 .part L_0x2d87fc0, 0, 1; +L_0x2d88410 .part L_0x2d87fc0, 1, 1; +S_0x2b8b3a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b8b1e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x129dc90/d .functor OR 1, L_0x129dd50, L_0x129deb0, C4<0>, C4<0>; -L_0x129dc90 .delay 1 (30000,30000,30000) L_0x129dc90/d; -L_0x129e0e0/d .functor OR 1, L_0x129e1f0, L_0x129e350, C4<0>, C4<0>; -L_0x129e0e0 .delay 1 (30000,30000,30000) L_0x129e0e0/d; -L_0x129e4d0/d .functor OR 1, L_0x129e540, L_0x129e6f0, C4<0>, C4<0>; -L_0x129e4d0 .delay 1 (30000,30000,30000) L_0x129e4d0/d; -v0x10bc7e0_0 .net *"_s0", 0 0, L_0x129dc90; 1 drivers -v0x10bc8e0_0 .net *"_s10", 0 0, L_0x129e1f0; 1 drivers -v0x10bc9c0_0 .net *"_s12", 0 0, L_0x129e350; 1 drivers -v0x10bca80_0 .net *"_s14", 0 0, L_0x129e540; 1 drivers -v0x10bcb60_0 .net *"_s16", 0 0, L_0x129e6f0; 1 drivers -v0x10bcc90_0 .net *"_s3", 0 0, L_0x129dd50; 1 drivers -v0x10bcd70_0 .net *"_s5", 0 0, L_0x129deb0; 1 drivers -v0x10bce50_0 .net *"_s6", 0 0, L_0x129e0e0; 1 drivers -v0x10bcf30_0 .net "in", 3 0, L_0x129e7e0; 1 drivers -v0x10bd0a0_0 .net "ors", 1 0, L_0x129dff0; 1 drivers -v0x10bd180_0 .net "out", 0 0, L_0x129e4d0; 1 drivers -L_0x129dd50 .part L_0x129e7e0, 0, 1; -L_0x129deb0 .part L_0x129e7e0, 1, 1; -L_0x129dff0 .concat8 [ 1 1 0 0], L_0x129dc90, L_0x129e0e0; -L_0x129e1f0 .part L_0x129e7e0, 2, 1; -L_0x129e350 .part L_0x129e7e0, 3, 1; -L_0x129e540 .part L_0x129dff0, 0, 1; -L_0x129e6f0 .part L_0x129dff0, 1, 1; -S_0x10bd2a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10bc3d0; +L_0x2d86840/d .functor OR 1, L_0x2d86900, L_0x2d86a60, C4<0>, C4<0>; +L_0x2d86840 .delay 1 (30000,30000,30000) L_0x2d86840/d; +L_0x2d86c90/d .functor OR 1, L_0x2d86da0, L_0x2d86f00, C4<0>, C4<0>; +L_0x2d86c90 .delay 1 (30000,30000,30000) L_0x2d86c90/d; +L_0x2d87080/d .functor OR 1, L_0x2d870f0, L_0x2d872a0, C4<0>, C4<0>; +L_0x2d87080 .delay 1 (30000,30000,30000) L_0x2d87080/d; +v0x2b8b5f0_0 .net *"_s0", 0 0, L_0x2d86840; 1 drivers +v0x2b8b6f0_0 .net *"_s10", 0 0, L_0x2d86da0; 1 drivers +v0x2b8b7d0_0 .net *"_s12", 0 0, L_0x2d86f00; 1 drivers +v0x2b8b890_0 .net *"_s14", 0 0, L_0x2d870f0; 1 drivers +v0x2b8b970_0 .net *"_s16", 0 0, L_0x2d872a0; 1 drivers +v0x2b8baa0_0 .net *"_s3", 0 0, L_0x2d86900; 1 drivers +v0x2b8bb80_0 .net *"_s5", 0 0, L_0x2d86a60; 1 drivers +v0x2b8bc60_0 .net *"_s6", 0 0, L_0x2d86c90; 1 drivers +v0x2b8bd40_0 .net "in", 3 0, L_0x2d87390; 1 drivers +v0x2b8beb0_0 .net "ors", 1 0, L_0x2d86ba0; 1 drivers +v0x2b8bf90_0 .net "out", 0 0, L_0x2d87080; 1 drivers +L_0x2d86900 .part L_0x2d87390, 0, 1; +L_0x2d86a60 .part L_0x2d87390, 1, 1; +L_0x2d86ba0 .concat8 [ 1 1 0 0], L_0x2d86840, L_0x2d86c90; +L_0x2d86da0 .part L_0x2d87390, 2, 1; +L_0x2d86f00 .part L_0x2d87390, 3, 1; +L_0x2d870f0 .part L_0x2d86ba0, 0, 1; +L_0x2d872a0 .part L_0x2d86ba0, 1, 1; +S_0x2b8c0b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b8b1e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x129e910/d .functor OR 1, L_0x129e980, L_0x129eae0, C4<0>, C4<0>; -L_0x129e910 .delay 1 (30000,30000,30000) L_0x129e910/d; -L_0x129ed10/d .functor OR 1, L_0x129ee20, L_0x129ef80, C4<0>, C4<0>; -L_0x129ed10 .delay 1 (30000,30000,30000) L_0x129ed10/d; -L_0x129f100/d .functor OR 1, L_0x129f170, L_0x129f320, C4<0>, C4<0>; -L_0x129f100 .delay 1 (30000,30000,30000) L_0x129f100/d; -v0x10bd460_0 .net *"_s0", 0 0, L_0x129e910; 1 drivers -v0x10bd560_0 .net *"_s10", 0 0, L_0x129ee20; 1 drivers -v0x10bd640_0 .net *"_s12", 0 0, L_0x129ef80; 1 drivers -v0x10bd700_0 .net *"_s14", 0 0, L_0x129f170; 1 drivers -v0x10bd7e0_0 .net *"_s16", 0 0, L_0x129f320; 1 drivers -v0x10bd910_0 .net *"_s3", 0 0, L_0x129e980; 1 drivers -v0x10bd9f0_0 .net *"_s5", 0 0, L_0x129eae0; 1 drivers -v0x10bdad0_0 .net *"_s6", 0 0, L_0x129ed10; 1 drivers -v0x10bdbb0_0 .net "in", 3 0, L_0x129f550; 1 drivers -v0x10bdd20_0 .net "ors", 1 0, L_0x129ec20; 1 drivers -v0x10bde00_0 .net "out", 0 0, L_0x129f100; 1 drivers -L_0x129e980 .part L_0x129f550, 0, 1; -L_0x129eae0 .part L_0x129f550, 1, 1; -L_0x129ec20 .concat8 [ 1 1 0 0], L_0x129e910, L_0x129ed10; -L_0x129ee20 .part L_0x129f550, 2, 1; -L_0x129ef80 .part L_0x129f550, 3, 1; -L_0x129f170 .part L_0x129ec20, 0, 1; -L_0x129f320 .part L_0x129ec20, 1, 1; -S_0x10be710 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10b7840; +L_0x2d874c0/d .functor OR 1, L_0x2d87530, L_0x2d87690, C4<0>, C4<0>; +L_0x2d874c0 .delay 1 (30000,30000,30000) L_0x2d874c0/d; +L_0x2d878c0/d .functor OR 1, L_0x2d879d0, L_0x2d87b30, C4<0>, C4<0>; +L_0x2d878c0 .delay 1 (30000,30000,30000) L_0x2d878c0/d; +L_0x2d87cb0/d .functor OR 1, L_0x2d87d20, L_0x2d87ed0, C4<0>, C4<0>; +L_0x2d87cb0 .delay 1 (30000,30000,30000) L_0x2d87cb0/d; +v0x2b8c270_0 .net *"_s0", 0 0, L_0x2d874c0; 1 drivers +v0x2b8c370_0 .net *"_s10", 0 0, L_0x2d879d0; 1 drivers +v0x2b8c450_0 .net *"_s12", 0 0, L_0x2d87b30; 1 drivers +v0x2b8c510_0 .net *"_s14", 0 0, L_0x2d87d20; 1 drivers +v0x2b8c5f0_0 .net *"_s16", 0 0, L_0x2d87ed0; 1 drivers +v0x2b8c720_0 .net *"_s3", 0 0, L_0x2d87530; 1 drivers +v0x2b8c800_0 .net *"_s5", 0 0, L_0x2d87690; 1 drivers +v0x2b8c8e0_0 .net *"_s6", 0 0, L_0x2d878c0; 1 drivers +v0x2b8c9c0_0 .net "in", 3 0, L_0x2d88100; 1 drivers +v0x2b8cb30_0 .net "ors", 1 0, L_0x2d877d0; 1 drivers +v0x2b8cc10_0 .net "out", 0 0, L_0x2d87cb0; 1 drivers +L_0x2d87530 .part L_0x2d88100, 0, 1; +L_0x2d87690 .part L_0x2d88100, 1, 1; +L_0x2d877d0 .concat8 [ 1 1 0 0], L_0x2d874c0, L_0x2d878c0; +L_0x2d879d0 .part L_0x2d88100, 2, 1; +L_0x2d87b30 .part L_0x2d88100, 3, 1; +L_0x2d87d20 .part L_0x2d877d0, 0, 1; +L_0x2d87ed0 .part L_0x2d877d0, 1, 1; +S_0x2b8d520 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b86650; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10c3b40_0 .net "ands", 7 0, L_0x1299bb0; 1 drivers -v0x10c3c50_0 .net "in", 7 0, L_0x1298010; alias, 1 drivers -v0x10c3d10_0 .net "out", 0 0, L_0x129bbb0; alias, 1 drivers -v0x10c3de0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10be960 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10be710; +v0x2b92950_0 .net "ands", 7 0, L_0x2d82760; 1 drivers +v0x2b92a60_0 .net "in", 7 0, L_0x2d806e0; alias, 1 drivers +v0x2b92b20_0 .net "out", 0 0, L_0x2d84760; alias, 1 drivers +v0x2b92bf0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b8d770 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b8d520; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10c10a0_0 .net "A", 7 0, L_0x1298010; alias, 1 drivers -v0x10c11a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10c1260_0 .net *"_s0", 0 0, L_0x12983a0; 1 drivers -v0x10c1320_0 .net *"_s12", 0 0, L_0x1298d60; 1 drivers -v0x10c1400_0 .net *"_s16", 0 0, L_0x12990c0; 1 drivers -v0x10c1530_0 .net *"_s20", 0 0, L_0x12994f0; 1 drivers -v0x10c1610_0 .net *"_s24", 0 0, L_0x1299820; 1 drivers -v0x10c16f0_0 .net *"_s28", 0 0, L_0x12997b0; 1 drivers -v0x10c17d0_0 .net *"_s4", 0 0, L_0x1298740; 1 drivers -v0x10c1940_0 .net *"_s8", 0 0, L_0x1298a50; 1 drivers -v0x10c1a20_0 .net "out", 7 0, L_0x1299bb0; alias, 1 drivers -L_0x12984b0 .part L_0x1298010, 0, 1; -L_0x12986a0 .part v0x12010b0_0, 0, 1; -L_0x1298800 .part L_0x1298010, 1, 1; -L_0x1298960 .part v0x12010b0_0, 1, 1; -L_0x1298b10 .part L_0x1298010, 2, 1; -L_0x1298c70 .part v0x12010b0_0, 2, 1; -L_0x1298e20 .part L_0x1298010, 3, 1; -L_0x1298f80 .part v0x12010b0_0, 3, 1; -L_0x1299180 .part L_0x1298010, 4, 1; -L_0x12993f0 .part v0x12010b0_0, 4, 1; -L_0x1299560 .part L_0x1298010, 5, 1; -L_0x12996c0 .part v0x12010b0_0, 5, 1; -L_0x12998e0 .part L_0x1298010, 6, 1; -L_0x1299a40 .part v0x12010b0_0, 6, 1; -LS_0x1299bb0_0_0 .concat8 [ 1 1 1 1], L_0x12983a0, L_0x1298740, L_0x1298a50, L_0x1298d60; -LS_0x1299bb0_0_4 .concat8 [ 1 1 1 1], L_0x12990c0, L_0x12994f0, L_0x1299820, L_0x12997b0; -L_0x1299bb0 .concat8 [ 4 4 0 0], LS_0x1299bb0_0_0, LS_0x1299bb0_0_4; -L_0x1299f70 .part L_0x1298010, 7, 1; -L_0x129a160 .part v0x12010b0_0, 7, 1; -S_0x10beba0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10bedb0 .param/l "i" 0 4 54, +C4<00>; -L_0x12983a0/d .functor AND 1, L_0x12984b0, L_0x12986a0, C4<1>, C4<1>; -L_0x12983a0 .delay 1 (30000,30000,30000) L_0x12983a0/d; -v0x10bee90_0 .net *"_s0", 0 0, L_0x12984b0; 1 drivers -v0x10bef70_0 .net *"_s1", 0 0, L_0x12986a0; 1 drivers -S_0x10bf050 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10bf260 .param/l "i" 0 4 54, +C4<01>; -L_0x1298740/d .functor AND 1, L_0x1298800, L_0x1298960, C4<1>, C4<1>; -L_0x1298740 .delay 1 (30000,30000,30000) L_0x1298740/d; -v0x10bf320_0 .net *"_s0", 0 0, L_0x1298800; 1 drivers -v0x10bf400_0 .net *"_s1", 0 0, L_0x1298960; 1 drivers -S_0x10bf4e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10bf720 .param/l "i" 0 4 54, +C4<010>; -L_0x1298a50/d .functor AND 1, L_0x1298b10, L_0x1298c70, C4<1>, C4<1>; -L_0x1298a50 .delay 1 (30000,30000,30000) L_0x1298a50/d; -v0x10bf7c0_0 .net *"_s0", 0 0, L_0x1298b10; 1 drivers -v0x10bf8a0_0 .net *"_s1", 0 0, L_0x1298c70; 1 drivers -S_0x10bf980 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10bfb90 .param/l "i" 0 4 54, +C4<011>; -L_0x1298d60/d .functor AND 1, L_0x1298e20, L_0x1298f80, C4<1>, C4<1>; -L_0x1298d60 .delay 1 (30000,30000,30000) L_0x1298d60/d; -v0x10bfc50_0 .net *"_s0", 0 0, L_0x1298e20; 1 drivers -v0x10bfd30_0 .net *"_s1", 0 0, L_0x1298f80; 1 drivers -S_0x10bfe10 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10c0070 .param/l "i" 0 4 54, +C4<0100>; -L_0x12990c0/d .functor AND 1, L_0x1299180, L_0x12993f0, C4<1>, C4<1>; -L_0x12990c0 .delay 1 (30000,30000,30000) L_0x12990c0/d; -v0x10c0130_0 .net *"_s0", 0 0, L_0x1299180; 1 drivers -v0x10c0210_0 .net *"_s1", 0 0, L_0x12993f0; 1 drivers -S_0x10c02f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10c0500 .param/l "i" 0 4 54, +C4<0101>; -L_0x12994f0/d .functor AND 1, L_0x1299560, L_0x12996c0, C4<1>, C4<1>; -L_0x12994f0 .delay 1 (30000,30000,30000) L_0x12994f0/d; -v0x10c05c0_0 .net *"_s0", 0 0, L_0x1299560; 1 drivers -v0x10c06a0_0 .net *"_s1", 0 0, L_0x12996c0; 1 drivers -S_0x10c0780 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10c0990 .param/l "i" 0 4 54, +C4<0110>; -L_0x1299820/d .functor AND 1, L_0x12998e0, L_0x1299a40, C4<1>, C4<1>; -L_0x1299820 .delay 1 (30000,30000,30000) L_0x1299820/d; -v0x10c0a50_0 .net *"_s0", 0 0, L_0x12998e0; 1 drivers -v0x10c0b30_0 .net *"_s1", 0 0, L_0x1299a40; 1 drivers -S_0x10c0c10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10be960; - .timescale -9 -12; -P_0x10c0e20 .param/l "i" 0 4 54, +C4<0111>; -L_0x12997b0/d .functor AND 1, L_0x1299f70, L_0x129a160, C4<1>, C4<1>; -L_0x12997b0 .delay 1 (30000,30000,30000) L_0x12997b0/d; -v0x10c0ee0_0 .net *"_s0", 0 0, L_0x1299f70; 1 drivers -v0x10c0fc0_0 .net *"_s1", 0 0, L_0x129a160; 1 drivers -S_0x10c1b80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10be710; +v0x2b8feb0_0 .net "A", 7 0, L_0x2d806e0; alias, 1 drivers +v0x2b8ffb0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b90070_0 .net *"_s0", 0 0, L_0x2d80fb0; 1 drivers +v0x2b90130_0 .net *"_s12", 0 0, L_0x2d81970; 1 drivers +v0x2b90210_0 .net *"_s16", 0 0, L_0x2d81cd0; 1 drivers +v0x2b90340_0 .net *"_s20", 0 0, L_0x2d820a0; 1 drivers +v0x2b90420_0 .net *"_s24", 0 0, L_0x2d823d0; 1 drivers +v0x2b90500_0 .net *"_s28", 0 0, L_0x2d82360; 1 drivers +v0x2b905e0_0 .net *"_s4", 0 0, L_0x2d81350; 1 drivers +v0x2b90750_0 .net *"_s8", 0 0, L_0x2d81660; 1 drivers +v0x2b90830_0 .net "out", 7 0, L_0x2d82760; alias, 1 drivers +L_0x2d810c0 .part L_0x2d806e0, 0, 1; +L_0x2d812b0 .part v0x2cdd2e0_0, 0, 1; +L_0x2d81410 .part L_0x2d806e0, 1, 1; +L_0x2d81570 .part v0x2cdd2e0_0, 1, 1; +L_0x2d81720 .part L_0x2d806e0, 2, 1; +L_0x2d81880 .part v0x2cdd2e0_0, 2, 1; +L_0x2d81a30 .part L_0x2d806e0, 3, 1; +L_0x2d81b90 .part v0x2cdd2e0_0, 3, 1; +L_0x2d81d90 .part L_0x2d806e0, 4, 1; +L_0x2d82000 .part v0x2cdd2e0_0, 4, 1; +L_0x2d82110 .part L_0x2d806e0, 5, 1; +L_0x2d82270 .part v0x2cdd2e0_0, 5, 1; +L_0x2d82490 .part L_0x2d806e0, 6, 1; +L_0x2d825f0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d82760_0_0 .concat8 [ 1 1 1 1], L_0x2d80fb0, L_0x2d81350, L_0x2d81660, L_0x2d81970; +LS_0x2d82760_0_4 .concat8 [ 1 1 1 1], L_0x2d81cd0, L_0x2d820a0, L_0x2d823d0, L_0x2d82360; +L_0x2d82760 .concat8 [ 4 4 0 0], LS_0x2d82760_0_0, LS_0x2d82760_0_4; +L_0x2d82b20 .part L_0x2d806e0, 7, 1; +L_0x2d82d10 .part v0x2cdd2e0_0, 7, 1; +S_0x2b8d9b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8dbc0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d80fb0/d .functor AND 1, L_0x2d810c0, L_0x2d812b0, C4<1>, C4<1>; +L_0x2d80fb0 .delay 1 (30000,30000,30000) L_0x2d80fb0/d; +v0x2b8dca0_0 .net *"_s0", 0 0, L_0x2d810c0; 1 drivers +v0x2b8dd80_0 .net *"_s1", 0 0, L_0x2d812b0; 1 drivers +S_0x2b8de60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8e070 .param/l "i" 0 4 54, +C4<01>; +L_0x2d81350/d .functor AND 1, L_0x2d81410, L_0x2d81570, C4<1>, C4<1>; +L_0x2d81350 .delay 1 (30000,30000,30000) L_0x2d81350/d; +v0x2b8e130_0 .net *"_s0", 0 0, L_0x2d81410; 1 drivers +v0x2b8e210_0 .net *"_s1", 0 0, L_0x2d81570; 1 drivers +S_0x2b8e2f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8e530 .param/l "i" 0 4 54, +C4<010>; +L_0x2d81660/d .functor AND 1, L_0x2d81720, L_0x2d81880, C4<1>, C4<1>; +L_0x2d81660 .delay 1 (30000,30000,30000) L_0x2d81660/d; +v0x2b8e5d0_0 .net *"_s0", 0 0, L_0x2d81720; 1 drivers +v0x2b8e6b0_0 .net *"_s1", 0 0, L_0x2d81880; 1 drivers +S_0x2b8e790 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8e9a0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d81970/d .functor AND 1, L_0x2d81a30, L_0x2d81b90, C4<1>, C4<1>; +L_0x2d81970 .delay 1 (30000,30000,30000) L_0x2d81970/d; +v0x2b8ea60_0 .net *"_s0", 0 0, L_0x2d81a30; 1 drivers +v0x2b8eb40_0 .net *"_s1", 0 0, L_0x2d81b90; 1 drivers +S_0x2b8ec20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8ee80 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d81cd0/d .functor AND 1, L_0x2d81d90, L_0x2d82000, C4<1>, C4<1>; +L_0x2d81cd0 .delay 1 (30000,30000,30000) L_0x2d81cd0/d; +v0x2b8ef40_0 .net *"_s0", 0 0, L_0x2d81d90; 1 drivers +v0x2b8f020_0 .net *"_s1", 0 0, L_0x2d82000; 1 drivers +S_0x2b8f100 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8f310 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d820a0/d .functor AND 1, L_0x2d82110, L_0x2d82270, C4<1>, C4<1>; +L_0x2d820a0 .delay 1 (30000,30000,30000) L_0x2d820a0/d; +v0x2b8f3d0_0 .net *"_s0", 0 0, L_0x2d82110; 1 drivers +v0x2b8f4b0_0 .net *"_s1", 0 0, L_0x2d82270; 1 drivers +S_0x2b8f590 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8f7a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d823d0/d .functor AND 1, L_0x2d82490, L_0x2d825f0, C4<1>, C4<1>; +L_0x2d823d0 .delay 1 (30000,30000,30000) L_0x2d823d0/d; +v0x2b8f860_0 .net *"_s0", 0 0, L_0x2d82490; 1 drivers +v0x2b8f940_0 .net *"_s1", 0 0, L_0x2d825f0; 1 drivers +S_0x2b8fa20 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b8d770; + .timescale -9 -12; +P_0x2b8fc30 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d82360/d .functor AND 1, L_0x2d82b20, L_0x2d82d10, C4<1>, C4<1>; +L_0x2d82360 .delay 1 (30000,30000,30000) L_0x2d82360/d; +v0x2b8fcf0_0 .net *"_s0", 0 0, L_0x2d82b20; 1 drivers +v0x2b8fdd0_0 .net *"_s1", 0 0, L_0x2d82d10; 1 drivers +S_0x2b90990 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b8d520; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x129bbb0/d .functor OR 1, L_0x129bc70, L_0x129be20, C4<0>, C4<0>; -L_0x129bbb0 .delay 1 (30000,30000,30000) L_0x129bbb0/d; -v0x10c36d0_0 .net *"_s10", 0 0, L_0x129bc70; 1 drivers -v0x10c37b0_0 .net *"_s12", 0 0, L_0x129be20; 1 drivers -v0x10c3890_0 .net "in", 7 0, L_0x1299bb0; alias, 1 drivers -v0x10c3960_0 .net "ors", 1 0, L_0x129b9d0; 1 drivers -v0x10c3a20_0 .net "out", 0 0, L_0x129bbb0; alias, 1 drivers -L_0x129ada0 .part L_0x1299bb0, 0, 4; -L_0x129b9d0 .concat8 [ 1 1 0 0], L_0x129aa90, L_0x129b6c0; -L_0x129bb10 .part L_0x1299bb0, 4, 4; -L_0x129bc70 .part L_0x129b9d0, 0, 1; -L_0x129be20 .part L_0x129b9d0, 1, 1; -S_0x10c1d40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10c1b80; +L_0x2d84760/d .functor OR 1, L_0x2d84820, L_0x2d849d0, C4<0>, C4<0>; +L_0x2d84760 .delay 1 (30000,30000,30000) L_0x2d84760/d; +v0x2b924e0_0 .net *"_s10", 0 0, L_0x2d84820; 1 drivers +v0x2b925c0_0 .net *"_s12", 0 0, L_0x2d849d0; 1 drivers +v0x2b926a0_0 .net "in", 7 0, L_0x2d82760; alias, 1 drivers +v0x2b92770_0 .net "ors", 1 0, L_0x2d84580; 1 drivers +v0x2b92830_0 .net "out", 0 0, L_0x2d84760; alias, 1 drivers +L_0x2d83950 .part L_0x2d82760, 0, 4; +L_0x2d84580 .concat8 [ 1 1 0 0], L_0x2d83640, L_0x2d84270; +L_0x2d846c0 .part L_0x2d82760, 4, 4; +L_0x2d84820 .part L_0x2d84580, 0, 1; +L_0x2d849d0 .part L_0x2d84580, 1, 1; +S_0x2b90b50 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b90990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x129a250/d .functor OR 1, L_0x129a310, L_0x129a470, C4<0>, C4<0>; -L_0x129a250 .delay 1 (30000,30000,30000) L_0x129a250/d; -L_0x129a6a0/d .functor OR 1, L_0x129a7b0, L_0x129a910, C4<0>, C4<0>; -L_0x129a6a0 .delay 1 (30000,30000,30000) L_0x129a6a0/d; -L_0x129aa90/d .functor OR 1, L_0x129ab00, L_0x129acb0, C4<0>, C4<0>; -L_0x129aa90 .delay 1 (30000,30000,30000) L_0x129aa90/d; -v0x10c1f90_0 .net *"_s0", 0 0, L_0x129a250; 1 drivers -v0x10c2090_0 .net *"_s10", 0 0, L_0x129a7b0; 1 drivers -v0x10c2170_0 .net *"_s12", 0 0, L_0x129a910; 1 drivers -v0x10c2230_0 .net *"_s14", 0 0, L_0x129ab00; 1 drivers -v0x10c2310_0 .net *"_s16", 0 0, L_0x129acb0; 1 drivers -v0x10c2440_0 .net *"_s3", 0 0, L_0x129a310; 1 drivers -v0x10c2520_0 .net *"_s5", 0 0, L_0x129a470; 1 drivers -v0x10c2600_0 .net *"_s6", 0 0, L_0x129a6a0; 1 drivers -v0x10c26e0_0 .net "in", 3 0, L_0x129ada0; 1 drivers -v0x10c2850_0 .net "ors", 1 0, L_0x129a5b0; 1 drivers -v0x10c2930_0 .net "out", 0 0, L_0x129aa90; 1 drivers -L_0x129a310 .part L_0x129ada0, 0, 1; -L_0x129a470 .part L_0x129ada0, 1, 1; -L_0x129a5b0 .concat8 [ 1 1 0 0], L_0x129a250, L_0x129a6a0; -L_0x129a7b0 .part L_0x129ada0, 2, 1; -L_0x129a910 .part L_0x129ada0, 3, 1; -L_0x129ab00 .part L_0x129a5b0, 0, 1; -L_0x129acb0 .part L_0x129a5b0, 1, 1; -S_0x10c2a50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10c1b80; +L_0x2d82e00/d .functor OR 1, L_0x2d82ec0, L_0x2d83020, C4<0>, C4<0>; +L_0x2d82e00 .delay 1 (30000,30000,30000) L_0x2d82e00/d; +L_0x2d83250/d .functor OR 1, L_0x2d83360, L_0x2d834c0, C4<0>, C4<0>; +L_0x2d83250 .delay 1 (30000,30000,30000) L_0x2d83250/d; +L_0x2d83640/d .functor OR 1, L_0x2d836b0, L_0x2d83860, C4<0>, C4<0>; +L_0x2d83640 .delay 1 (30000,30000,30000) L_0x2d83640/d; +v0x2b90da0_0 .net *"_s0", 0 0, L_0x2d82e00; 1 drivers +v0x2b90ea0_0 .net *"_s10", 0 0, L_0x2d83360; 1 drivers +v0x2b90f80_0 .net *"_s12", 0 0, L_0x2d834c0; 1 drivers +v0x2b91040_0 .net *"_s14", 0 0, L_0x2d836b0; 1 drivers +v0x2b91120_0 .net *"_s16", 0 0, L_0x2d83860; 1 drivers +v0x2b91250_0 .net *"_s3", 0 0, L_0x2d82ec0; 1 drivers +v0x2b91330_0 .net *"_s5", 0 0, L_0x2d83020; 1 drivers +v0x2b91410_0 .net *"_s6", 0 0, L_0x2d83250; 1 drivers +v0x2b914f0_0 .net "in", 3 0, L_0x2d83950; 1 drivers +v0x2b91660_0 .net "ors", 1 0, L_0x2d83160; 1 drivers +v0x2b91740_0 .net "out", 0 0, L_0x2d83640; 1 drivers +L_0x2d82ec0 .part L_0x2d83950, 0, 1; +L_0x2d83020 .part L_0x2d83950, 1, 1; +L_0x2d83160 .concat8 [ 1 1 0 0], L_0x2d82e00, L_0x2d83250; +L_0x2d83360 .part L_0x2d83950, 2, 1; +L_0x2d834c0 .part L_0x2d83950, 3, 1; +L_0x2d836b0 .part L_0x2d83160, 0, 1; +L_0x2d83860 .part L_0x2d83160, 1, 1; +S_0x2b91860 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b90990; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x129aed0/d .functor OR 1, L_0x129af40, L_0x129b0a0, C4<0>, C4<0>; -L_0x129aed0 .delay 1 (30000,30000,30000) L_0x129aed0/d; -L_0x129b2d0/d .functor OR 1, L_0x129b3e0, L_0x129b540, C4<0>, C4<0>; -L_0x129b2d0 .delay 1 (30000,30000,30000) L_0x129b2d0/d; -L_0x129b6c0/d .functor OR 1, L_0x129b730, L_0x129b8e0, C4<0>, C4<0>; -L_0x129b6c0 .delay 1 (30000,30000,30000) L_0x129b6c0/d; -v0x10c2c10_0 .net *"_s0", 0 0, L_0x129aed0; 1 drivers -v0x10c2d10_0 .net *"_s10", 0 0, L_0x129b3e0; 1 drivers -v0x10c2df0_0 .net *"_s12", 0 0, L_0x129b540; 1 drivers -v0x10c2eb0_0 .net *"_s14", 0 0, L_0x129b730; 1 drivers -v0x10c2f90_0 .net *"_s16", 0 0, L_0x129b8e0; 1 drivers -v0x10c30c0_0 .net *"_s3", 0 0, L_0x129af40; 1 drivers -v0x10c31a0_0 .net *"_s5", 0 0, L_0x129b0a0; 1 drivers -v0x10c3280_0 .net *"_s6", 0 0, L_0x129b2d0; 1 drivers -v0x10c3360_0 .net "in", 3 0, L_0x129bb10; 1 drivers -v0x10c34d0_0 .net "ors", 1 0, L_0x129b1e0; 1 drivers -v0x10c35b0_0 .net "out", 0 0, L_0x129b6c0; 1 drivers -L_0x129af40 .part L_0x129bb10, 0, 1; -L_0x129b0a0 .part L_0x129bb10, 1, 1; -L_0x129b1e0 .concat8 [ 1 1 0 0], L_0x129aed0, L_0x129b2d0; -L_0x129b3e0 .part L_0x129bb10, 2, 1; -L_0x129b540 .part L_0x129bb10, 3, 1; -L_0x129b730 .part L_0x129b1e0, 0, 1; -L_0x129b8e0 .part L_0x129b1e0, 1, 1; -S_0x10c3ec0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10b7840; +L_0x2d83a80/d .functor OR 1, L_0x2d83af0, L_0x2d83c50, C4<0>, C4<0>; +L_0x2d83a80 .delay 1 (30000,30000,30000) L_0x2d83a80/d; +L_0x2d83e80/d .functor OR 1, L_0x2d83f90, L_0x2d840f0, C4<0>, C4<0>; +L_0x2d83e80 .delay 1 (30000,30000,30000) L_0x2d83e80/d; +L_0x2d84270/d .functor OR 1, L_0x2d842e0, L_0x2d84490, C4<0>, C4<0>; +L_0x2d84270 .delay 1 (30000,30000,30000) L_0x2d84270/d; +v0x2b91a20_0 .net *"_s0", 0 0, L_0x2d83a80; 1 drivers +v0x2b91b20_0 .net *"_s10", 0 0, L_0x2d83f90; 1 drivers +v0x2b91c00_0 .net *"_s12", 0 0, L_0x2d840f0; 1 drivers +v0x2b91cc0_0 .net *"_s14", 0 0, L_0x2d842e0; 1 drivers +v0x2b91da0_0 .net *"_s16", 0 0, L_0x2d84490; 1 drivers +v0x2b91ed0_0 .net *"_s3", 0 0, L_0x2d83af0; 1 drivers +v0x2b91fb0_0 .net *"_s5", 0 0, L_0x2d83c50; 1 drivers +v0x2b92090_0 .net *"_s6", 0 0, L_0x2d83e80; 1 drivers +v0x2b92170_0 .net "in", 3 0, L_0x2d846c0; 1 drivers +v0x2b922e0_0 .net "ors", 1 0, L_0x2d83d90; 1 drivers +v0x2b923c0_0 .net "out", 0 0, L_0x2d84270; 1 drivers +L_0x2d83af0 .part L_0x2d846c0, 0, 1; +L_0x2d83c50 .part L_0x2d846c0, 1, 1; +L_0x2d83d90 .concat8 [ 1 1 0 0], L_0x2d83a80, L_0x2d83e80; +L_0x2d83f90 .part L_0x2d846c0, 2, 1; +L_0x2d840f0 .part L_0x2d846c0, 3, 1; +L_0x2d842e0 .part L_0x2d83d90, 0, 1; +L_0x2d84490 .part L_0x2d83d90, 1, 1; +S_0x2b92cd0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b86650; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -8630,80 +9128,80 @@ S_0x10c3ec0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10b7840; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1297380/d .functor XNOR 1, L_0x129fa50, L_0x1296100, C4<0>, C4<0>; -L_0x1297380 .delay 1 (20000,20000,20000) L_0x1297380/d; -L_0x12975f0/d .functor AND 1, L_0x129fa50, L_0x12962c0, C4<1>, C4<1>; -L_0x12975f0 .delay 1 (30000,30000,30000) L_0x12975f0/d; -L_0x1297660/d .functor AND 1, L_0x1297380, L_0x12961a0, C4<1>, C4<1>; -L_0x1297660 .delay 1 (30000,30000,30000) L_0x1297660/d; -L_0x12977c0/d .functor OR 1, L_0x1297660, L_0x12975f0, C4<0>, C4<0>; -L_0x12977c0 .delay 1 (30000,30000,30000) L_0x12977c0/d; -v0x10c4170_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers -v0x10c4260_0 .net "a_", 0 0, L_0x128c1e0; alias, 1 drivers -v0x10c4320_0 .net "b", 0 0, L_0x1296100; alias, 1 drivers -v0x10c4410_0 .net "b_", 0 0, L_0x12962c0; alias, 1 drivers -v0x10c44b0_0 .net "carryin", 0 0, L_0x12961a0; alias, 1 drivers -v0x10c45f0_0 .net "eq", 0 0, L_0x1297380; 1 drivers -v0x10c46b0_0 .net "lt", 0 0, L_0x12975f0; 1 drivers -v0x10c4770_0 .net "out", 0 0, L_0x12977c0; 1 drivers -v0x10c4830_0 .net "w0", 0 0, L_0x1297660; 1 drivers -S_0x10c4a80 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10b7840; +L_0x2d7f590/d .functor XNOR 1, L_0x2d88600, L_0x2d7e110, C4<0>, C4<0>; +L_0x2d7f590 .delay 1 (20000,20000,20000) L_0x2d7f590/d; +L_0x2d7f710/d .functor AND 1, L_0x2d88600, L_0x2d7e280, C4<1>, C4<1>; +L_0x2d7f710 .delay 1 (30000,30000,30000) L_0x2d7f710/d; +L_0x2d7f870/d .functor AND 1, L_0x2d7f590, L_0x2d7e1b0, C4<1>, C4<1>; +L_0x2d7f870 .delay 1 (30000,30000,30000) L_0x2d7f870/d; +L_0x2d7f980/d .functor OR 1, L_0x2d7f870, L_0x2d7f710, C4<0>, C4<0>; +L_0x2d7f980 .delay 1 (30000,30000,30000) L_0x2d7f980/d; +v0x2b92f80_0 .net "a", 0 0, L_0x2d88600; alias, 1 drivers +v0x2b93070_0 .net "a_", 0 0, L_0x2d734d0; alias, 1 drivers +v0x2b93130_0 .net "b", 0 0, L_0x2d7e110; alias, 1 drivers +v0x2b93220_0 .net "b_", 0 0, L_0x2d7e280; alias, 1 drivers +v0x2b932c0_0 .net "carryin", 0 0, L_0x2d7e1b0; alias, 1 drivers +v0x2b93400_0 .net "eq", 0 0, L_0x2d7f590; 1 drivers +v0x2b934c0_0 .net "lt", 0 0, L_0x2d7f710; 1 drivers +v0x2b93580_0 .net "out", 0 0, L_0x2d7f980; 1 drivers +v0x2b93640_0 .net "w0", 0 0, L_0x2d7f870; 1 drivers +S_0x2b93890 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b86650; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1297160/d .functor OR 1, L_0x1296cb0, L_0x10c5ce0, C4<0>, C4<0>; -L_0x1297160 .delay 1 (30000,30000,30000) L_0x1297160/d; -v0x10c5870_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers -v0x10c59c0_0 .net "b", 0 0, L_0x12962c0; alias, 1 drivers -v0x10c5a80_0 .net "c1", 0 0, L_0x1296cb0; 1 drivers -v0x10c5b20_0 .net "c2", 0 0, L_0x10c5ce0; 1 drivers -v0x10c5bf0_0 .net "carryin", 0 0, L_0x12961a0; alias, 1 drivers -v0x10c5d70_0 .net "carryout", 0 0, L_0x1297160; 1 drivers -v0x10c5e10_0 .net "s1", 0 0, L_0x1296bf0; 1 drivers -v0x10c5eb0_0 .net "sum", 0 0, L_0x1296e10; 1 drivers -S_0x10c4cd0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10c4a80; +L_0x2d7f170/d .functor OR 1, L_0x2d7ec70, L_0x2b94af0, C4<0>, C4<0>; +L_0x2d7f170 .delay 1 (30000,30000,30000) L_0x2d7f170/d; +v0x2b94680_0 .net "a", 0 0, L_0x2d88600; alias, 1 drivers +v0x2b947d0_0 .net "b", 0 0, L_0x2d7e280; alias, 1 drivers +v0x2b94890_0 .net "c1", 0 0, L_0x2d7ec70; 1 drivers +v0x2b94930_0 .net "c2", 0 0, L_0x2b94af0; 1 drivers +v0x2b94a00_0 .net "carryin", 0 0, L_0x2d7e1b0; alias, 1 drivers +v0x2b94b80_0 .net "carryout", 0 0, L_0x2d7f170; 1 drivers +v0x2b94c20_0 .net "s1", 0 0, L_0x2d7ebb0; 1 drivers +v0x2b94cc0_0 .net "sum", 0 0, L_0x2d7edd0; 1 drivers +S_0x2b93ae0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b93890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1296bf0/d .functor XOR 1, L_0x129fa50, L_0x12962c0, C4<0>, C4<0>; -L_0x1296bf0 .delay 1 (30000,30000,30000) L_0x1296bf0/d; -L_0x1296cb0/d .functor AND 1, L_0x129fa50, L_0x12962c0, C4<1>, C4<1>; -L_0x1296cb0 .delay 1 (30000,30000,30000) L_0x1296cb0/d; -v0x10c4f30_0 .net "a", 0 0, L_0x129fa50; alias, 1 drivers -v0x10c4ff0_0 .net "b", 0 0, L_0x12962c0; alias, 1 drivers -v0x10c50b0_0 .net "carryout", 0 0, L_0x1296cb0; alias, 1 drivers -v0x10c5150_0 .net "sum", 0 0, L_0x1296bf0; alias, 1 drivers -S_0x10c5280 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10c4a80; +L_0x2d7ebb0/d .functor XOR 1, L_0x2d88600, L_0x2d7e280, C4<0>, C4<0>; +L_0x2d7ebb0 .delay 1 (30000,30000,30000) L_0x2d7ebb0/d; +L_0x2d7ec70/d .functor AND 1, L_0x2d88600, L_0x2d7e280, C4<1>, C4<1>; +L_0x2d7ec70 .delay 1 (30000,30000,30000) L_0x2d7ec70/d; +v0x2b93d40_0 .net "a", 0 0, L_0x2d88600; alias, 1 drivers +v0x2b93e00_0 .net "b", 0 0, L_0x2d7e280; alias, 1 drivers +v0x2b93ec0_0 .net "carryout", 0 0, L_0x2d7ec70; alias, 1 drivers +v0x2b93f60_0 .net "sum", 0 0, L_0x2d7ebb0; alias, 1 drivers +S_0x2b94090 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b93890; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1296e10/d .functor XOR 1, L_0x1296bf0, L_0x12961a0, C4<0>, C4<0>; -L_0x1296e10 .delay 1 (30000,30000,30000) L_0x1296e10/d; -L_0x10c5ce0/d .functor AND 1, L_0x1296bf0, L_0x12961a0, C4<1>, C4<1>; -L_0x10c5ce0 .delay 1 (30000,30000,30000) L_0x10c5ce0/d; -v0x10c54e0_0 .net "a", 0 0, L_0x1296bf0; alias, 1 drivers -v0x10c55b0_0 .net "b", 0 0, L_0x12961a0; alias, 1 drivers -v0x10c5650_0 .net "carryout", 0 0, L_0x10c5ce0; alias, 1 drivers -v0x10c5720_0 .net "sum", 0 0, L_0x1296e10; alias, 1 drivers -S_0x10c7270 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10b7570; - .timescale -9 -12; -L_0x2b0ab3d060f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06140 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x129faf0/d .functor OR 1, L_0x2b0ab3d060f8, L_0x2b0ab3d06140, C4<0>, C4<0>; -L_0x129faf0 .delay 1 (30000,30000,30000) L_0x129faf0/d; -v0x10c7460_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d060f8; 1 drivers -v0x10c7540_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06140; 1 drivers -S_0x10c7620 .scope generate, "alu_slices[16]" "alu_slices[16]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1046ba0 .param/l "i" 0 3 41, +C4<010000>; -S_0x10c7990 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10c7620; +L_0x2d7edd0/d .functor XOR 1, L_0x2d7ebb0, L_0x2d7e1b0, C4<0>, C4<0>; +L_0x2d7edd0 .delay 1 (30000,30000,30000) L_0x2d7edd0/d; +L_0x2b94af0/d .functor AND 1, L_0x2d7ebb0, L_0x2d7e1b0, C4<1>, C4<1>; +L_0x2b94af0 .delay 1 (30000,30000,30000) L_0x2b94af0/d; +v0x2b942f0_0 .net "a", 0 0, L_0x2d7ebb0; alias, 1 drivers +v0x2b943c0_0 .net "b", 0 0, L_0x2d7e1b0; alias, 1 drivers +v0x2b94460_0 .net "carryout", 0 0, L_0x2b94af0; alias, 1 drivers +v0x2b94530_0 .net "sum", 0 0, L_0x2d7edd0; alias, 1 drivers +S_0x2b96d50 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b86380; + .timescale -9 -12; +L_0x2ac6110b9df8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9e40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d80a20/d .functor OR 1, L_0x2ac6110b9df8, L_0x2ac6110b9e40, C4<0>, C4<0>; +L_0x2d80a20 .delay 1 (30000,30000,30000) L_0x2d80a20/d; +v0x2b96f40_0 .net/2u *"_s0", 0 0, L_0x2ac6110b9df8; 1 drivers +v0x2b97020_0 .net/2u *"_s2", 0 0, L_0x2ac6110b9e40; 1 drivers +S_0x2b97100 .scope generate, "alu_slices[16]" "alu_slices[16]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2b10250 .param/l "i" 0 3 39, +C4<010000>; +S_0x2b97470 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2b97100; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -8712,445 +9210,476 @@ S_0x10c7990 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10c7620; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x129fbb0/d .functor NOT 1, L_0x12a97d0, C4<0>, C4<0>, C4<0>; -L_0x129fbb0 .delay 1 (10000,10000,10000) L_0x129fbb0/d; -L_0x12a00d0/d .functor NOT 1, L_0x12a9930, C4<0>, C4<0>, C4<0>; -L_0x12a00d0 .delay 1 (10000,10000,10000) L_0x12a00d0/d; -L_0x12a1010/d .functor XOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; -L_0x12a1010 .delay 1 (30000,30000,30000) L_0x12a1010/d; -L_0x2b0ab3d06188 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d061d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12a16c0/d .functor OR 1, L_0x2b0ab3d06188, L_0x2b0ab3d061d0, C4<0>, C4<0>; -L_0x12a16c0 .delay 1 (30000,30000,30000) L_0x12a16c0/d; -L_0x12a18c0/d .functor AND 1, L_0x12a97d0, L_0x12a9930, C4<1>, C4<1>; -L_0x12a18c0 .delay 1 (30000,30000,30000) L_0x12a18c0/d; -L_0x12a1980/d .functor NAND 1, L_0x12a97d0, L_0x12a9930, C4<1>, C4<1>; -L_0x12a1980 .delay 1 (20000,20000,20000) L_0x12a1980/d; -L_0x12a1ae0/d .functor XOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; -L_0x12a1ae0 .delay 1 (20000,20000,20000) L_0x12a1ae0/d; -L_0x12a1f90/d .functor OR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; -L_0x12a1f90 .delay 1 (30000,30000,30000) L_0x12a1f90/d; -L_0x12a96d0/d .functor NOT 1, L_0x12a5900, C4<0>, C4<0>, C4<0>; -L_0x12a96d0 .delay 1 (10000,10000,10000) L_0x12a96d0/d; -v0x10d6130_0 .net "A", 0 0, L_0x12a97d0; 1 drivers -v0x10d61f0_0 .net "A_", 0 0, L_0x129fbb0; 1 drivers -v0x10d62b0_0 .net "B", 0 0, L_0x12a9930; 1 drivers -v0x10d6380_0 .net "B_", 0 0, L_0x12a00d0; 1 drivers -v0x10d6420_0 .net *"_s12", 0 0, L_0x12a16c0; 1 drivers -v0x10d6510_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06188; 1 drivers -v0x10d65d0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d061d0; 1 drivers -v0x10d66b0_0 .net *"_s18", 0 0, L_0x12a18c0; 1 drivers -v0x10d6790_0 .net *"_s20", 0 0, L_0x12a1980; 1 drivers -v0x10d6900_0 .net *"_s22", 0 0, L_0x12a1ae0; 1 drivers -v0x10d69e0_0 .net *"_s24", 0 0, L_0x12a1f90; 1 drivers -o0x2b0ab3cca7c8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10d6ac0_0 name=_s30 -o0x2b0ab3cca7f8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10d6ba0_0 name=_s32 -v0x10d6c80_0 .net *"_s8", 0 0, L_0x12a1010; 1 drivers -v0x10d6d60_0 .net "carryin", 0 0, L_0x129ff40; 1 drivers -v0x10d6e00_0 .net "carryout", 0 0, L_0x12a9370; 1 drivers -v0x10d6ea0_0 .net "carryouts", 7 0, L_0x1354920; 1 drivers -v0x10d7050_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10d70f0_0 .net "result", 0 0, L_0x12a5900; 1 drivers -v0x10d71e0_0 .net "results", 7 0, L_0x12a1d60; 1 drivers -v0x10d72f0_0 .net "zero", 0 0, L_0x12a96d0; 1 drivers -LS_0x12a1d60_0_0 .concat8 [ 1 1 1 1], L_0x12a0530, L_0x12a0b60, L_0x12a1010, L_0x12a16c0; -LS_0x12a1d60_0_4 .concat8 [ 1 1 1 1], L_0x12a18c0, L_0x12a1980, L_0x12a1ae0, L_0x12a1f90; -L_0x12a1d60 .concat8 [ 4 4 0 0], LS_0x12a1d60_0_0, LS_0x12a1d60_0_4; -LS_0x1354920_0_0 .concat [ 1 1 1 1], L_0x12a07e0, L_0x12a0eb0, o0x2b0ab3cca7c8, L_0x12a1510; -LS_0x1354920_0_4 .concat [ 4 0 0 0], o0x2b0ab3cca7f8; -L_0x1354920 .concat [ 4 4 0 0], LS_0x1354920_0_0, LS_0x1354920_0_4; -S_0x10c7c10 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10c7990; +L_0x2d33f60/d .functor NOT 1, L_0x2d92fa0, C4<0>, C4<0>, C4<0>; +L_0x2d33f60 .delay 1 (10000,10000,10000) L_0x2d33f60/d; +L_0x2d88c80/d .functor NOT 1, L_0x2d93100, C4<0>, C4<0>, C4<0>; +L_0x2d88c80 .delay 1 (10000,10000,10000) L_0x2d88c80/d; +L_0x2d89c70/d .functor XOR 1, L_0x2d92fa0, L_0x2d93100, C4<0>, C4<0>; +L_0x2d89c70 .delay 1 (30000,30000,30000) L_0x2d89c70/d; +L_0x2ac6110b9e88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9ed0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d89d30/d .functor OR 1, L_0x2ac6110b9e88, L_0x2ac6110b9ed0, C4<0>, C4<0>; +L_0x2d89d30 .delay 1 (30000,30000,30000) L_0x2d89d30/d; +L_0x2ac6110b9f18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9f60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d8a4d0/d .functor OR 1, L_0x2ac6110b9f18, L_0x2ac6110b9f60, C4<0>, C4<0>; +L_0x2d8a4d0 .delay 1 (30000,30000,30000) L_0x2d8a4d0/d; +L_0x2d8a6d0/d .functor AND 1, L_0x2d92fa0, L_0x2d93100, C4<1>, C4<1>; +L_0x2d8a6d0 .delay 1 (30000,30000,30000) L_0x2d8a6d0/d; +L_0x2ac6110b9fa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110b9ff0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d8a790/d .functor OR 1, L_0x2ac6110b9fa8, L_0x2ac6110b9ff0, C4<0>, C4<0>; +L_0x2d8a790 .delay 1 (30000,30000,30000) L_0x2d8a790/d; +L_0x2d8a990/d .functor NAND 1, L_0x2d92fa0, L_0x2d93100, C4<1>, C4<1>; +L_0x2d8a990 .delay 1 (20000,20000,20000) L_0x2d8a990/d; +L_0x2ac6110ba038 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba080 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d8aaa0/d .functor OR 1, L_0x2ac6110ba038, L_0x2ac6110ba080, C4<0>, C4<0>; +L_0x2d8aaa0 .delay 1 (30000,30000,30000) L_0x2d8aaa0/d; +L_0x2d8ac50/d .functor NOR 1, L_0x2d92fa0, L_0x2d93100, C4<0>, C4<0>; +L_0x2d8ac50 .delay 1 (20000,20000,20000) L_0x2d8ac50/d; +L_0x2ac6110ba0c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba110 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d8af20/d .functor OR 1, L_0x2ac6110ba0c8, L_0x2ac6110ba110, C4<0>, C4<0>; +L_0x2d8af20 .delay 1 (30000,30000,30000) L_0x2d8af20/d; +L_0x2d8b2b0/d .functor OR 1, L_0x2d92fa0, L_0x2d93100, C4<0>, C4<0>; +L_0x2d8b2b0 .delay 1 (30000,30000,30000) L_0x2d8b2b0/d; +L_0x2ac6110ba158 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba1a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d8b7a0/d .functor OR 1, L_0x2ac6110ba158, L_0x2ac6110ba1a0, C4<0>, C4<0>; +L_0x2d8b7a0 .delay 1 (30000,30000,30000) L_0x2d8b7a0/d; +L_0x2d92ea0/d .functor NOT 1, L_0x2d8f100, C4<0>, C4<0>, C4<0>; +L_0x2d92ea0 .delay 1 (10000,10000,10000) L_0x2d92ea0/d; +v0x2ba5b80_0 .net "A", 0 0, L_0x2d92fa0; 1 drivers +v0x2ba5c40_0 .net "A_", 0 0, L_0x2d33f60; 1 drivers +v0x2ba5d00_0 .net "B", 0 0, L_0x2d93100; 1 drivers +v0x2ba5dd0_0 .net "B_", 0 0, L_0x2d88c80; 1 drivers +v0x2ba5e70_0 .net *"_s11", 0 0, L_0x2d89d30; 1 drivers +v0x2ba5f60_0 .net/2s *"_s13", 0 0, L_0x2ac6110b9e88; 1 drivers +v0x2ba6020_0 .net/2s *"_s15", 0 0, L_0x2ac6110b9ed0; 1 drivers +v0x2ba6100_0 .net *"_s19", 0 0, L_0x2d8a4d0; 1 drivers +v0x2ba61e0_0 .net/2s *"_s21", 0 0, L_0x2ac6110b9f18; 1 drivers +v0x2ba6350_0 .net/2s *"_s23", 0 0, L_0x2ac6110b9f60; 1 drivers +v0x2ba6430_0 .net *"_s25", 0 0, L_0x2d8a6d0; 1 drivers +v0x2ba6510_0 .net *"_s28", 0 0, L_0x2d8a790; 1 drivers +v0x2ba65f0_0 .net/2s *"_s30", 0 0, L_0x2ac6110b9fa8; 1 drivers +v0x2ba66d0_0 .net/2s *"_s32", 0 0, L_0x2ac6110b9ff0; 1 drivers +v0x2ba67b0_0 .net *"_s34", 0 0, L_0x2d8a990; 1 drivers +v0x2ba6890_0 .net *"_s37", 0 0, L_0x2d8aaa0; 1 drivers +v0x2ba6970_0 .net/2s *"_s39", 0 0, L_0x2ac6110ba038; 1 drivers +v0x2ba6b20_0 .net/2s *"_s41", 0 0, L_0x2ac6110ba080; 1 drivers +v0x2ba6bc0_0 .net *"_s43", 0 0, L_0x2d8ac50; 1 drivers +v0x2ba6ca0_0 .net *"_s46", 0 0, L_0x2d8af20; 1 drivers +v0x2ba6d80_0 .net/2s *"_s48", 0 0, L_0x2ac6110ba0c8; 1 drivers +v0x2ba6e60_0 .net/2s *"_s50", 0 0, L_0x2ac6110ba110; 1 drivers +v0x2ba6f40_0 .net *"_s52", 0 0, L_0x2d8b2b0; 1 drivers +v0x2ba7020_0 .net *"_s56", 0 0, L_0x2d8b7a0; 1 drivers +v0x2ba7100_0 .net/2s *"_s59", 0 0, L_0x2ac6110ba158; 1 drivers +v0x2ba71e0_0 .net/2s *"_s61", 0 0, L_0x2ac6110ba1a0; 1 drivers +v0x2ba72c0_0 .net *"_s8", 0 0, L_0x2d89c70; 1 drivers +v0x2ba73a0_0 .net "carryin", 0 0, L_0x2d88af0; 1 drivers +v0x2ba7440_0 .net "carryout", 0 0, L_0x2d92b40; 1 drivers +v0x2ba74e0_0 .net "carryouts", 7 0, L_0x2d8b430; 1 drivers +v0x2ba75f0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ba76b0_0 .net "result", 0 0, L_0x2d8f100; 1 drivers +v0x2ba77a0_0 .net "results", 7 0, L_0x2d8b030; 1 drivers +v0x2ba6a80_0 .net "zero", 0 0, L_0x2d92ea0; 1 drivers +LS_0x2d8b030_0_0 .concat8 [ 1 1 1 1], L_0x2d89140, L_0x2d89770, L_0x2d89c70, L_0x2d8a4d0; +LS_0x2d8b030_0_4 .concat8 [ 1 1 1 1], L_0x2d8a6d0, L_0x2d8a990, L_0x2d8ac50, L_0x2d8b2b0; +L_0x2d8b030 .concat8 [ 4 4 0 0], LS_0x2d8b030_0_0, LS_0x2d8b030_0_4; +LS_0x2d8b430_0_0 .concat8 [ 1 1 1 1], L_0x2d893f0, L_0x2d89b10, L_0x2d89d30, L_0x2d8a320; +LS_0x2d8b430_0_4 .concat8 [ 1 1 1 1], L_0x2d8a790, L_0x2d8aaa0, L_0x2d8af20, L_0x2d8b7a0; +L_0x2d8b430 .concat8 [ 4 4 0 0], LS_0x2d8b430_0_0, LS_0x2d8b430_0_4; +S_0x2b976f0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2b97470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12a07e0/d .functor OR 1, L_0x12a02c0, L_0x12a0680, C4<0>, C4<0>; -L_0x12a07e0 .delay 1 (30000,30000,30000) L_0x12a07e0/d; -v0x10c8ab0_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers -v0x10c8b70_0 .net "b", 0 0, L_0x12a9930; alias, 1 drivers -v0x10c8c40_0 .net "c1", 0 0, L_0x12a02c0; 1 drivers -v0x10c8d40_0 .net "c2", 0 0, L_0x12a0680; 1 drivers -v0x10c8e10_0 .net "carryin", 0 0, L_0x129ff40; alias, 1 drivers -v0x10c8f00_0 .net "carryout", 0 0, L_0x12a07e0; 1 drivers -v0x10c8fa0_0 .net "s1", 0 0, L_0x1299b30; 1 drivers -v0x10c9090_0 .net "sum", 0 0, L_0x12a0530; 1 drivers -S_0x10c7e60 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10c7c10; +L_0x2d893f0/d .functor OR 1, L_0x2d88ed0, L_0x2d89290, C4<0>, C4<0>; +L_0x2d893f0 .delay 1 (30000,30000,30000) L_0x2d893f0/d; +v0x2b98500_0 .net "a", 0 0, L_0x2d92fa0; alias, 1 drivers +v0x2b985c0_0 .net "b", 0 0, L_0x2d93100; alias, 1 drivers +v0x2b98690_0 .net "c1", 0 0, L_0x2d88ed0; 1 drivers +v0x2b98790_0 .net "c2", 0 0, L_0x2d89290; 1 drivers +v0x2b98860_0 .net "carryin", 0 0, L_0x2d88af0; alias, 1 drivers +v0x2b98950_0 .net "carryout", 0 0, L_0x2d893f0; 1 drivers +v0x2b989f0_0 .net "s1", 0 0, L_0x2d88e10; 1 drivers +v0x2b98ae0_0 .net "sum", 0 0, L_0x2d89140; 1 drivers +S_0x2b97940 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2b976f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1299b30/d .functor XOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; -L_0x1299b30 .delay 1 (30000,30000,30000) L_0x1299b30/d; -L_0x12a02c0/d .functor AND 1, L_0x12a97d0, L_0x12a9930, C4<1>, C4<1>; -L_0x12a02c0 .delay 1 (30000,30000,30000) L_0x12a02c0/d; -v0x10c80c0_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers -v0x10c81a0_0 .net "b", 0 0, L_0x12a9930; alias, 1 drivers -v0x10c8260_0 .net "carryout", 0 0, L_0x12a02c0; alias, 1 drivers -v0x10c8330_0 .net "sum", 0 0, L_0x1299b30; alias, 1 drivers -S_0x10c84a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10c7c10; +L_0x2d88e10/d .functor XOR 1, L_0x2d92fa0, L_0x2d93100, C4<0>, C4<0>; +L_0x2d88e10 .delay 1 (30000,30000,30000) L_0x2d88e10/d; +L_0x2d88ed0/d .functor AND 1, L_0x2d92fa0, L_0x2d93100, C4<1>, C4<1>; +L_0x2d88ed0 .delay 1 (30000,30000,30000) L_0x2d88ed0/d; +v0x2b97ba0_0 .net "a", 0 0, L_0x2d92fa0; alias, 1 drivers +v0x2b97c80_0 .net "b", 0 0, L_0x2d93100; alias, 1 drivers +v0x2b97d40_0 .net "carryout", 0 0, L_0x2d88ed0; alias, 1 drivers +v0x2b97de0_0 .net "sum", 0 0, L_0x2d88e10; alias, 1 drivers +S_0x2b97f20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2b976f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12a0530/d .functor XOR 1, L_0x1299b30, L_0x129ff40, C4<0>, C4<0>; -L_0x12a0530 .delay 1 (30000,30000,30000) L_0x12a0530/d; -L_0x12a0680/d .functor AND 1, L_0x1299b30, L_0x129ff40, C4<1>, C4<1>; -L_0x12a0680 .delay 1 (30000,30000,30000) L_0x12a0680/d; -v0x10c8700_0 .net "a", 0 0, L_0x1299b30; alias, 1 drivers -v0x10c87d0_0 .net "b", 0 0, L_0x129ff40; alias, 1 drivers -v0x10c8870_0 .net "carryout", 0 0, L_0x12a0680; alias, 1 drivers -v0x10c8940_0 .net "sum", 0 0, L_0x12a0530; alias, 1 drivers -S_0x10c9160 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10c7990; +L_0x2d89140/d .functor XOR 1, L_0x2d88e10, L_0x2d88af0, C4<0>, C4<0>; +L_0x2d89140 .delay 1 (30000,30000,30000) L_0x2d89140/d; +L_0x2d89290/d .functor AND 1, L_0x2d88e10, L_0x2d88af0, C4<1>, C4<1>; +L_0x2d89290 .delay 1 (30000,30000,30000) L_0x2d89290/d; +v0x2b98180_0 .net "a", 0 0, L_0x2d88e10; alias, 1 drivers +v0x2b98220_0 .net "b", 0 0, L_0x2d88af0; alias, 1 drivers +v0x2b982c0_0 .net "carryout", 0 0, L_0x2d89290; alias, 1 drivers +v0x2b98390_0 .net "sum", 0 0, L_0x2d89140; alias, 1 drivers +S_0x2b98bb0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2b97470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10ce550_0 .net "ands", 7 0, L_0x12a7370; 1 drivers -v0x10ce660_0 .net "in", 7 0, L_0x1354920; alias, 1 drivers -v0x10ce720_0 .net "out", 0 0, L_0x12a9370; alias, 1 drivers -v0x10ce7f0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10c9380 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10c9160; +v0x2b9dfa0_0 .net "ands", 7 0, L_0x2d90b40; 1 drivers +v0x2b9e0b0_0 .net "in", 7 0, L_0x2d8b430; alias, 1 drivers +v0x2b9e170_0 .net "out", 0 0, L_0x2d92b40; alias, 1 drivers +v0x2b9e240_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b98dd0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b98bb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10cbab0_0 .net "A", 7 0, L_0x1354920; alias, 1 drivers -v0x10cbbb0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10cbc70_0 .net *"_s0", 0 0, L_0x12a5c60; 1 drivers -v0x10cbd30_0 .net *"_s12", 0 0, L_0x12a65d0; 1 drivers -v0x10cbe10_0 .net *"_s16", 0 0, L_0x12a6930; 1 drivers -v0x10cbf40_0 .net *"_s20", 0 0, L_0x12a6c40; 1 drivers -v0x10cc020_0 .net *"_s24", 0 0, L_0x12a7030; 1 drivers -v0x10cc100_0 .net *"_s28", 0 0, L_0x12a6fc0; 1 drivers -v0x10cc1e0_0 .net *"_s4", 0 0, L_0x12a5f70; 1 drivers -v0x10cc350_0 .net *"_s8", 0 0, L_0x12a62c0; 1 drivers -v0x10cc430_0 .net "out", 7 0, L_0x12a7370; alias, 1 drivers -L_0x12a5d20 .part L_0x1354920, 0, 1; -L_0x12a5e80 .part v0x12010b0_0, 0, 1; -L_0x12a6030 .part L_0x1354920, 1, 1; -L_0x12a6220 .part v0x12010b0_0, 1, 1; -L_0x12a6380 .part L_0x1354920, 2, 1; -L_0x12a64e0 .part v0x12010b0_0, 2, 1; -L_0x12a6690 .part L_0x1354920, 3, 1; -L_0x12a67f0 .part v0x12010b0_0, 3, 1; -L_0x12a69f0 .part L_0x1354920, 4, 1; -L_0x12a6b50 .part v0x12010b0_0, 4, 1; -L_0x12a6cb0 .part L_0x1354920, 5, 1; -L_0x12a6f20 .part v0x12010b0_0, 5, 1; -L_0x12a7120 .part L_0x1354920, 6, 1; -L_0x12a7280 .part v0x12010b0_0, 6, 1; -LS_0x12a7370_0_0 .concat8 [ 1 1 1 1], L_0x12a5c60, L_0x12a5f70, L_0x12a62c0, L_0x12a65d0; -LS_0x12a7370_0_4 .concat8 [ 1 1 1 1], L_0x12a6930, L_0x12a6c40, L_0x12a7030, L_0x12a6fc0; -L_0x12a7370 .concat8 [ 4 4 0 0], LS_0x12a7370_0_0, LS_0x12a7370_0_4; -L_0x12a7730 .part L_0x1354920, 7, 1; -L_0x12a7920 .part v0x12010b0_0, 7, 1; -S_0x10c95e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10c97f0 .param/l "i" 0 4 54, +C4<00>; -L_0x12a5c60/d .functor AND 1, L_0x12a5d20, L_0x12a5e80, C4<1>, C4<1>; -L_0x12a5c60 .delay 1 (30000,30000,30000) L_0x12a5c60/d; -v0x10c98d0_0 .net *"_s0", 0 0, L_0x12a5d20; 1 drivers -v0x10c99b0_0 .net *"_s1", 0 0, L_0x12a5e80; 1 drivers -S_0x10c9a90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10c9ca0 .param/l "i" 0 4 54, +C4<01>; -L_0x12a5f70/d .functor AND 1, L_0x12a6030, L_0x12a6220, C4<1>, C4<1>; -L_0x12a5f70 .delay 1 (30000,30000,30000) L_0x12a5f70/d; -v0x10c9d60_0 .net *"_s0", 0 0, L_0x12a6030; 1 drivers -v0x10c9e40_0 .net *"_s1", 0 0, L_0x12a6220; 1 drivers -S_0x10c9f20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10ca130 .param/l "i" 0 4 54, +C4<010>; -L_0x12a62c0/d .functor AND 1, L_0x12a6380, L_0x12a64e0, C4<1>, C4<1>; -L_0x12a62c0 .delay 1 (30000,30000,30000) L_0x12a62c0/d; -v0x10ca1d0_0 .net *"_s0", 0 0, L_0x12a6380; 1 drivers -v0x10ca2b0_0 .net *"_s1", 0 0, L_0x12a64e0; 1 drivers -S_0x10ca390 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10ca5a0 .param/l "i" 0 4 54, +C4<011>; -L_0x12a65d0/d .functor AND 1, L_0x12a6690, L_0x12a67f0, C4<1>, C4<1>; -L_0x12a65d0 .delay 1 (30000,30000,30000) L_0x12a65d0/d; -v0x10ca660_0 .net *"_s0", 0 0, L_0x12a6690; 1 drivers -v0x10ca740_0 .net *"_s1", 0 0, L_0x12a67f0; 1 drivers -S_0x10ca820 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10caa80 .param/l "i" 0 4 54, +C4<0100>; -L_0x12a6930/d .functor AND 1, L_0x12a69f0, L_0x12a6b50, C4<1>, C4<1>; -L_0x12a6930 .delay 1 (30000,30000,30000) L_0x12a6930/d; -v0x10cab40_0 .net *"_s0", 0 0, L_0x12a69f0; 1 drivers -v0x10cac20_0 .net *"_s1", 0 0, L_0x12a6b50; 1 drivers -S_0x10cad00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10caf10 .param/l "i" 0 4 54, +C4<0101>; -L_0x12a6c40/d .functor AND 1, L_0x12a6cb0, L_0x12a6f20, C4<1>, C4<1>; -L_0x12a6c40 .delay 1 (30000,30000,30000) L_0x12a6c40/d; -v0x10cafd0_0 .net *"_s0", 0 0, L_0x12a6cb0; 1 drivers -v0x10cb0b0_0 .net *"_s1", 0 0, L_0x12a6f20; 1 drivers -S_0x10cb190 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10cb3a0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12a7030/d .functor AND 1, L_0x12a7120, L_0x12a7280, C4<1>, C4<1>; -L_0x12a7030 .delay 1 (30000,30000,30000) L_0x12a7030/d; -v0x10cb460_0 .net *"_s0", 0 0, L_0x12a7120; 1 drivers -v0x10cb540_0 .net *"_s1", 0 0, L_0x12a7280; 1 drivers -S_0x10cb620 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10c9380; - .timescale -9 -12; -P_0x10cb830 .param/l "i" 0 4 54, +C4<0111>; -L_0x12a6fc0/d .functor AND 1, L_0x12a7730, L_0x12a7920, C4<1>, C4<1>; -L_0x12a6fc0 .delay 1 (30000,30000,30000) L_0x12a6fc0/d; -v0x10cb8f0_0 .net *"_s0", 0 0, L_0x12a7730; 1 drivers -v0x10cb9d0_0 .net *"_s1", 0 0, L_0x12a7920; 1 drivers -S_0x10cc590 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10c9160; +v0x2b9b500_0 .net "A", 7 0, L_0x2d8b430; alias, 1 drivers +v0x2b9b600_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2b9b6c0_0 .net *"_s0", 0 0, L_0x2d8f460; 1 drivers +v0x2b9b780_0 .net *"_s12", 0 0, L_0x2d8fdd0; 1 drivers +v0x2b9b860_0 .net *"_s16", 0 0, L_0x2d90130; 1 drivers +v0x2b9b990_0 .net *"_s20", 0 0, L_0x2d90500; 1 drivers +v0x2b9ba70_0 .net *"_s24", 0 0, L_0x2d90830; 1 drivers +v0x2b9bb50_0 .net *"_s28", 0 0, L_0x2d907c0; 1 drivers +v0x2b9bc30_0 .net *"_s4", 0 0, L_0x2d8f7b0; 1 drivers +v0x2b9bda0_0 .net *"_s8", 0 0, L_0x2d8fac0; 1 drivers +v0x2b9be80_0 .net "out", 7 0, L_0x2d90b40; alias, 1 drivers +L_0x2d8f520 .part L_0x2d8b430, 0, 1; +L_0x2d8f710 .part v0x2cdd2e0_0, 0, 1; +L_0x2d8f870 .part L_0x2d8b430, 1, 1; +L_0x2d8f9d0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d8fb80 .part L_0x2d8b430, 2, 1; +L_0x2d8fce0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d8fe90 .part L_0x2d8b430, 3, 1; +L_0x2d8fff0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d901f0 .part L_0x2d8b430, 4, 1; +L_0x2d90460 .part v0x2cdd2e0_0, 4, 1; +L_0x2d90570 .part L_0x2d8b430, 5, 1; +L_0x2d906d0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d908f0 .part L_0x2d8b430, 6, 1; +L_0x2d90a50 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d90b40_0_0 .concat8 [ 1 1 1 1], L_0x2d8f460, L_0x2d8f7b0, L_0x2d8fac0, L_0x2d8fdd0; +LS_0x2d90b40_0_4 .concat8 [ 1 1 1 1], L_0x2d90130, L_0x2d90500, L_0x2d90830, L_0x2d907c0; +L_0x2d90b40 .concat8 [ 4 4 0 0], LS_0x2d90b40_0_0, LS_0x2d90b40_0_4; +L_0x2d90f00 .part L_0x2d8b430, 7, 1; +L_0x2d910f0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b99030 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b99240 .param/l "i" 0 4 54, +C4<00>; +L_0x2d8f460/d .functor AND 1, L_0x2d8f520, L_0x2d8f710, C4<1>, C4<1>; +L_0x2d8f460 .delay 1 (30000,30000,30000) L_0x2d8f460/d; +v0x2b99320_0 .net *"_s0", 0 0, L_0x2d8f520; 1 drivers +v0x2b99400_0 .net *"_s1", 0 0, L_0x2d8f710; 1 drivers +S_0x2b994e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b996f0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d8f7b0/d .functor AND 1, L_0x2d8f870, L_0x2d8f9d0, C4<1>, C4<1>; +L_0x2d8f7b0 .delay 1 (30000,30000,30000) L_0x2d8f7b0/d; +v0x2b997b0_0 .net *"_s0", 0 0, L_0x2d8f870; 1 drivers +v0x2b99890_0 .net *"_s1", 0 0, L_0x2d8f9d0; 1 drivers +S_0x2b99970 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b99b80 .param/l "i" 0 4 54, +C4<010>; +L_0x2d8fac0/d .functor AND 1, L_0x2d8fb80, L_0x2d8fce0, C4<1>, C4<1>; +L_0x2d8fac0 .delay 1 (30000,30000,30000) L_0x2d8fac0/d; +v0x2b99c20_0 .net *"_s0", 0 0, L_0x2d8fb80; 1 drivers +v0x2b99d00_0 .net *"_s1", 0 0, L_0x2d8fce0; 1 drivers +S_0x2b99de0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b99ff0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d8fdd0/d .functor AND 1, L_0x2d8fe90, L_0x2d8fff0, C4<1>, C4<1>; +L_0x2d8fdd0 .delay 1 (30000,30000,30000) L_0x2d8fdd0/d; +v0x2b9a0b0_0 .net *"_s0", 0 0, L_0x2d8fe90; 1 drivers +v0x2b9a190_0 .net *"_s1", 0 0, L_0x2d8fff0; 1 drivers +S_0x2b9a270 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b9a4d0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d90130/d .functor AND 1, L_0x2d901f0, L_0x2d90460, C4<1>, C4<1>; +L_0x2d90130 .delay 1 (30000,30000,30000) L_0x2d90130/d; +v0x2b9a590_0 .net *"_s0", 0 0, L_0x2d901f0; 1 drivers +v0x2b9a670_0 .net *"_s1", 0 0, L_0x2d90460; 1 drivers +S_0x2b9a750 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b9a960 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d90500/d .functor AND 1, L_0x2d90570, L_0x2d906d0, C4<1>, C4<1>; +L_0x2d90500 .delay 1 (30000,30000,30000) L_0x2d90500/d; +v0x2b9aa20_0 .net *"_s0", 0 0, L_0x2d90570; 1 drivers +v0x2b9ab00_0 .net *"_s1", 0 0, L_0x2d906d0; 1 drivers +S_0x2b9abe0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b9adf0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d90830/d .functor AND 1, L_0x2d908f0, L_0x2d90a50, C4<1>, C4<1>; +L_0x2d90830 .delay 1 (30000,30000,30000) L_0x2d90830/d; +v0x2b9aeb0_0 .net *"_s0", 0 0, L_0x2d908f0; 1 drivers +v0x2b9af90_0 .net *"_s1", 0 0, L_0x2d90a50; 1 drivers +S_0x2b9b070 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b98dd0; + .timescale -9 -12; +P_0x2b9b280 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d907c0/d .functor AND 1, L_0x2d90f00, L_0x2d910f0, C4<1>, C4<1>; +L_0x2d907c0 .delay 1 (30000,30000,30000) L_0x2d907c0/d; +v0x2b9b340_0 .net *"_s0", 0 0, L_0x2d90f00; 1 drivers +v0x2b9b420_0 .net *"_s1", 0 0, L_0x2d910f0; 1 drivers +S_0x2b9bfe0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b98bb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12a9370/d .functor OR 1, L_0x12a9430, L_0x12a95e0, C4<0>, C4<0>; -L_0x12a9370 .delay 1 (30000,30000,30000) L_0x12a9370/d; -v0x10ce0e0_0 .net *"_s10", 0 0, L_0x12a9430; 1 drivers -v0x10ce1c0_0 .net *"_s12", 0 0, L_0x12a95e0; 1 drivers -v0x10ce2a0_0 .net "in", 7 0, L_0x12a7370; alias, 1 drivers -v0x10ce370_0 .net "ors", 1 0, L_0x12a9190; 1 drivers -v0x10ce430_0 .net "out", 0 0, L_0x12a9370; alias, 1 drivers -L_0x12a8560 .part L_0x12a7370, 0, 4; -L_0x12a9190 .concat8 [ 1 1 0 0], L_0x12a8250, L_0x12a8e80; -L_0x12a92d0 .part L_0x12a7370, 4, 4; -L_0x12a9430 .part L_0x12a9190, 0, 1; -L_0x12a95e0 .part L_0x12a9190, 1, 1; -S_0x10cc750 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10cc590; +L_0x2d92b40/d .functor OR 1, L_0x2d92c00, L_0x2d92db0, C4<0>, C4<0>; +L_0x2d92b40 .delay 1 (30000,30000,30000) L_0x2d92b40/d; +v0x2b9db30_0 .net *"_s10", 0 0, L_0x2d92c00; 1 drivers +v0x2b9dc10_0 .net *"_s12", 0 0, L_0x2d92db0; 1 drivers +v0x2b9dcf0_0 .net "in", 7 0, L_0x2d90b40; alias, 1 drivers +v0x2b9ddc0_0 .net "ors", 1 0, L_0x2d92960; 1 drivers +v0x2b9de80_0 .net "out", 0 0, L_0x2d92b40; alias, 1 drivers +L_0x2d91d30 .part L_0x2d90b40, 0, 4; +L_0x2d92960 .concat8 [ 1 1 0 0], L_0x2d91a20, L_0x2d92650; +L_0x2d92aa0 .part L_0x2d90b40, 4, 4; +L_0x2d92c00 .part L_0x2d92960, 0, 1; +L_0x2d92db0 .part L_0x2d92960, 1, 1; +S_0x2b9c1a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2b9bfe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12a7a10/d .functor OR 1, L_0x12a7ad0, L_0x12a7c30, C4<0>, C4<0>; -L_0x12a7a10 .delay 1 (30000,30000,30000) L_0x12a7a10/d; -L_0x12a7e60/d .functor OR 1, L_0x12a7f70, L_0x12a80d0, C4<0>, C4<0>; -L_0x12a7e60 .delay 1 (30000,30000,30000) L_0x12a7e60/d; -L_0x12a8250/d .functor OR 1, L_0x12a82c0, L_0x12a8470, C4<0>, C4<0>; -L_0x12a8250 .delay 1 (30000,30000,30000) L_0x12a8250/d; -v0x10cc9a0_0 .net *"_s0", 0 0, L_0x12a7a10; 1 drivers -v0x10ccaa0_0 .net *"_s10", 0 0, L_0x12a7f70; 1 drivers -v0x10ccb80_0 .net *"_s12", 0 0, L_0x12a80d0; 1 drivers -v0x10ccc40_0 .net *"_s14", 0 0, L_0x12a82c0; 1 drivers -v0x10ccd20_0 .net *"_s16", 0 0, L_0x12a8470; 1 drivers -v0x10cce50_0 .net *"_s3", 0 0, L_0x12a7ad0; 1 drivers -v0x10ccf30_0 .net *"_s5", 0 0, L_0x12a7c30; 1 drivers -v0x10cd010_0 .net *"_s6", 0 0, L_0x12a7e60; 1 drivers -v0x10cd0f0_0 .net "in", 3 0, L_0x12a8560; 1 drivers -v0x10cd260_0 .net "ors", 1 0, L_0x12a7d70; 1 drivers -v0x10cd340_0 .net "out", 0 0, L_0x12a8250; 1 drivers -L_0x12a7ad0 .part L_0x12a8560, 0, 1; -L_0x12a7c30 .part L_0x12a8560, 1, 1; -L_0x12a7d70 .concat8 [ 1 1 0 0], L_0x12a7a10, L_0x12a7e60; -L_0x12a7f70 .part L_0x12a8560, 2, 1; -L_0x12a80d0 .part L_0x12a8560, 3, 1; -L_0x12a82c0 .part L_0x12a7d70, 0, 1; -L_0x12a8470 .part L_0x12a7d70, 1, 1; -S_0x10cd460 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10cc590; +L_0x2d911e0/d .functor OR 1, L_0x2d912a0, L_0x2d91400, C4<0>, C4<0>; +L_0x2d911e0 .delay 1 (30000,30000,30000) L_0x2d911e0/d; +L_0x2d91630/d .functor OR 1, L_0x2d91740, L_0x2d918a0, C4<0>, C4<0>; +L_0x2d91630 .delay 1 (30000,30000,30000) L_0x2d91630/d; +L_0x2d91a20/d .functor OR 1, L_0x2d91a90, L_0x2d91c40, C4<0>, C4<0>; +L_0x2d91a20 .delay 1 (30000,30000,30000) L_0x2d91a20/d; +v0x2b9c3f0_0 .net *"_s0", 0 0, L_0x2d911e0; 1 drivers +v0x2b9c4f0_0 .net *"_s10", 0 0, L_0x2d91740; 1 drivers +v0x2b9c5d0_0 .net *"_s12", 0 0, L_0x2d918a0; 1 drivers +v0x2b9c690_0 .net *"_s14", 0 0, L_0x2d91a90; 1 drivers +v0x2b9c770_0 .net *"_s16", 0 0, L_0x2d91c40; 1 drivers +v0x2b9c8a0_0 .net *"_s3", 0 0, L_0x2d912a0; 1 drivers +v0x2b9c980_0 .net *"_s5", 0 0, L_0x2d91400; 1 drivers +v0x2b9ca60_0 .net *"_s6", 0 0, L_0x2d91630; 1 drivers +v0x2b9cb40_0 .net "in", 3 0, L_0x2d91d30; 1 drivers +v0x2b9ccb0_0 .net "ors", 1 0, L_0x2d91540; 1 drivers +v0x2b9cd90_0 .net "out", 0 0, L_0x2d91a20; 1 drivers +L_0x2d912a0 .part L_0x2d91d30, 0, 1; +L_0x2d91400 .part L_0x2d91d30, 1, 1; +L_0x2d91540 .concat8 [ 1 1 0 0], L_0x2d911e0, L_0x2d91630; +L_0x2d91740 .part L_0x2d91d30, 2, 1; +L_0x2d918a0 .part L_0x2d91d30, 3, 1; +L_0x2d91a90 .part L_0x2d91540, 0, 1; +L_0x2d91c40 .part L_0x2d91540, 1, 1; +S_0x2b9ceb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2b9bfe0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12a8690/d .functor OR 1, L_0x12a8700, L_0x12a8860, C4<0>, C4<0>; -L_0x12a8690 .delay 1 (30000,30000,30000) L_0x12a8690/d; -L_0x12a8a90/d .functor OR 1, L_0x12a8ba0, L_0x12a8d00, C4<0>, C4<0>; -L_0x12a8a90 .delay 1 (30000,30000,30000) L_0x12a8a90/d; -L_0x12a8e80/d .functor OR 1, L_0x12a8ef0, L_0x12a90a0, C4<0>, C4<0>; -L_0x12a8e80 .delay 1 (30000,30000,30000) L_0x12a8e80/d; -v0x10cd620_0 .net *"_s0", 0 0, L_0x12a8690; 1 drivers -v0x10cd720_0 .net *"_s10", 0 0, L_0x12a8ba0; 1 drivers -v0x10cd800_0 .net *"_s12", 0 0, L_0x12a8d00; 1 drivers -v0x10cd8c0_0 .net *"_s14", 0 0, L_0x12a8ef0; 1 drivers -v0x10cd9a0_0 .net *"_s16", 0 0, L_0x12a90a0; 1 drivers -v0x10cdad0_0 .net *"_s3", 0 0, L_0x12a8700; 1 drivers -v0x10cdbb0_0 .net *"_s5", 0 0, L_0x12a8860; 1 drivers -v0x10cdc90_0 .net *"_s6", 0 0, L_0x12a8a90; 1 drivers -v0x10cdd70_0 .net "in", 3 0, L_0x12a92d0; 1 drivers -v0x10cdee0_0 .net "ors", 1 0, L_0x12a89a0; 1 drivers -v0x10cdfc0_0 .net "out", 0 0, L_0x12a8e80; 1 drivers -L_0x12a8700 .part L_0x12a92d0, 0, 1; -L_0x12a8860 .part L_0x12a92d0, 1, 1; -L_0x12a89a0 .concat8 [ 1 1 0 0], L_0x12a8690, L_0x12a8a90; -L_0x12a8ba0 .part L_0x12a92d0, 2, 1; -L_0x12a8d00 .part L_0x12a92d0, 3, 1; -L_0x12a8ef0 .part L_0x12a89a0, 0, 1; -L_0x12a90a0 .part L_0x12a89a0, 1, 1; -S_0x10ce8d0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10c7990; +L_0x2d91e60/d .functor OR 1, L_0x2d91ed0, L_0x2d92030, C4<0>, C4<0>; +L_0x2d91e60 .delay 1 (30000,30000,30000) L_0x2d91e60/d; +L_0x2d92260/d .functor OR 1, L_0x2d92370, L_0x2d924d0, C4<0>, C4<0>; +L_0x2d92260 .delay 1 (30000,30000,30000) L_0x2d92260/d; +L_0x2d92650/d .functor OR 1, L_0x2d926c0, L_0x2d92870, C4<0>, C4<0>; +L_0x2d92650 .delay 1 (30000,30000,30000) L_0x2d92650/d; +v0x2b9d070_0 .net *"_s0", 0 0, L_0x2d91e60; 1 drivers +v0x2b9d170_0 .net *"_s10", 0 0, L_0x2d92370; 1 drivers +v0x2b9d250_0 .net *"_s12", 0 0, L_0x2d924d0; 1 drivers +v0x2b9d310_0 .net *"_s14", 0 0, L_0x2d926c0; 1 drivers +v0x2b9d3f0_0 .net *"_s16", 0 0, L_0x2d92870; 1 drivers +v0x2b9d520_0 .net *"_s3", 0 0, L_0x2d91ed0; 1 drivers +v0x2b9d600_0 .net *"_s5", 0 0, L_0x2d92030; 1 drivers +v0x2b9d6e0_0 .net *"_s6", 0 0, L_0x2d92260; 1 drivers +v0x2b9d7c0_0 .net "in", 3 0, L_0x2d92aa0; 1 drivers +v0x2b9d930_0 .net "ors", 1 0, L_0x2d92170; 1 drivers +v0x2b9da10_0 .net "out", 0 0, L_0x2d92650; 1 drivers +L_0x2d91ed0 .part L_0x2d92aa0, 0, 1; +L_0x2d92030 .part L_0x2d92aa0, 1, 1; +L_0x2d92170 .concat8 [ 1 1 0 0], L_0x2d91e60, L_0x2d92260; +L_0x2d92370 .part L_0x2d92aa0, 2, 1; +L_0x2d924d0 .part L_0x2d92aa0, 3, 1; +L_0x2d926c0 .part L_0x2d92170, 0, 1; +L_0x2d92870 .part L_0x2d92170, 1, 1; +S_0x2b9e320 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2b97470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10d3d00_0 .net "ands", 7 0, L_0x12a3900; 1 drivers -v0x10d3e10_0 .net "in", 7 0, L_0x12a1d60; alias, 1 drivers -v0x10d3ed0_0 .net "out", 0 0, L_0x12a5900; alias, 1 drivers -v0x10d3fa0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10ceb20 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10ce8d0; +v0x2ba3750_0 .net "ands", 7 0, L_0x2d8d100; 1 drivers +v0x2ba3860_0 .net "in", 7 0, L_0x2d8b030; alias, 1 drivers +v0x2ba3920_0 .net "out", 0 0, L_0x2d8f100; alias, 1 drivers +v0x2ba39f0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2b9e570 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2b9e320; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10d1260_0 .net "A", 7 0, L_0x12a1d60; alias, 1 drivers -v0x10d1360_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10d1420_0 .net *"_s0", 0 0, L_0x12a20f0; 1 drivers -v0x10d14e0_0 .net *"_s12", 0 0, L_0x12a2ab0; 1 drivers -v0x10d15c0_0 .net *"_s16", 0 0, L_0x12a2e10; 1 drivers -v0x10d16f0_0 .net *"_s20", 0 0, L_0x12a3240; 1 drivers -v0x10d17d0_0 .net *"_s24", 0 0, L_0x12a3570; 1 drivers -v0x10d18b0_0 .net *"_s28", 0 0, L_0x12a3500; 1 drivers -v0x10d1990_0 .net *"_s4", 0 0, L_0x12a2490; 1 drivers -v0x10d1b00_0 .net *"_s8", 0 0, L_0x12a27a0; 1 drivers -v0x10d1be0_0 .net "out", 7 0, L_0x12a3900; alias, 1 drivers -L_0x12a2200 .part L_0x12a1d60, 0, 1; -L_0x12a23f0 .part v0x12010b0_0, 0, 1; -L_0x12a2550 .part L_0x12a1d60, 1, 1; -L_0x12a26b0 .part v0x12010b0_0, 1, 1; -L_0x12a2860 .part L_0x12a1d60, 2, 1; -L_0x12a29c0 .part v0x12010b0_0, 2, 1; -L_0x12a2b70 .part L_0x12a1d60, 3, 1; -L_0x12a2cd0 .part v0x12010b0_0, 3, 1; -L_0x12a2ed0 .part L_0x12a1d60, 4, 1; -L_0x12a3140 .part v0x12010b0_0, 4, 1; -L_0x12a32b0 .part L_0x12a1d60, 5, 1; -L_0x12a3410 .part v0x12010b0_0, 5, 1; -L_0x12a3630 .part L_0x12a1d60, 6, 1; -L_0x12a3790 .part v0x12010b0_0, 6, 1; -LS_0x12a3900_0_0 .concat8 [ 1 1 1 1], L_0x12a20f0, L_0x12a2490, L_0x12a27a0, L_0x12a2ab0; -LS_0x12a3900_0_4 .concat8 [ 1 1 1 1], L_0x12a2e10, L_0x12a3240, L_0x12a3570, L_0x12a3500; -L_0x12a3900 .concat8 [ 4 4 0 0], LS_0x12a3900_0_0, LS_0x12a3900_0_4; -L_0x12a3cc0 .part L_0x12a1d60, 7, 1; -L_0x12a3eb0 .part v0x12010b0_0, 7, 1; -S_0x10ced60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10cef70 .param/l "i" 0 4 54, +C4<00>; -L_0x12a20f0/d .functor AND 1, L_0x12a2200, L_0x12a23f0, C4<1>, C4<1>; -L_0x12a20f0 .delay 1 (30000,30000,30000) L_0x12a20f0/d; -v0x10cf050_0 .net *"_s0", 0 0, L_0x12a2200; 1 drivers -v0x10cf130_0 .net *"_s1", 0 0, L_0x12a23f0; 1 drivers -S_0x10cf210 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10cf420 .param/l "i" 0 4 54, +C4<01>; -L_0x12a2490/d .functor AND 1, L_0x12a2550, L_0x12a26b0, C4<1>, C4<1>; -L_0x12a2490 .delay 1 (30000,30000,30000) L_0x12a2490/d; -v0x10cf4e0_0 .net *"_s0", 0 0, L_0x12a2550; 1 drivers -v0x10cf5c0_0 .net *"_s1", 0 0, L_0x12a26b0; 1 drivers -S_0x10cf6a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10cf8e0 .param/l "i" 0 4 54, +C4<010>; -L_0x12a27a0/d .functor AND 1, L_0x12a2860, L_0x12a29c0, C4<1>, C4<1>; -L_0x12a27a0 .delay 1 (30000,30000,30000) L_0x12a27a0/d; -v0x10cf980_0 .net *"_s0", 0 0, L_0x12a2860; 1 drivers -v0x10cfa60_0 .net *"_s1", 0 0, L_0x12a29c0; 1 drivers -S_0x10cfb40 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10cfd50 .param/l "i" 0 4 54, +C4<011>; -L_0x12a2ab0/d .functor AND 1, L_0x12a2b70, L_0x12a2cd0, C4<1>, C4<1>; -L_0x12a2ab0 .delay 1 (30000,30000,30000) L_0x12a2ab0/d; -v0x10cfe10_0 .net *"_s0", 0 0, L_0x12a2b70; 1 drivers -v0x10cfef0_0 .net *"_s1", 0 0, L_0x12a2cd0; 1 drivers -S_0x10cffd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10d0230 .param/l "i" 0 4 54, +C4<0100>; -L_0x12a2e10/d .functor AND 1, L_0x12a2ed0, L_0x12a3140, C4<1>, C4<1>; -L_0x12a2e10 .delay 1 (30000,30000,30000) L_0x12a2e10/d; -v0x10d02f0_0 .net *"_s0", 0 0, L_0x12a2ed0; 1 drivers -v0x10d03d0_0 .net *"_s1", 0 0, L_0x12a3140; 1 drivers -S_0x10d04b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10d06c0 .param/l "i" 0 4 54, +C4<0101>; -L_0x12a3240/d .functor AND 1, L_0x12a32b0, L_0x12a3410, C4<1>, C4<1>; -L_0x12a3240 .delay 1 (30000,30000,30000) L_0x12a3240/d; -v0x10d0780_0 .net *"_s0", 0 0, L_0x12a32b0; 1 drivers -v0x10d0860_0 .net *"_s1", 0 0, L_0x12a3410; 1 drivers -S_0x10d0940 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10d0b50 .param/l "i" 0 4 54, +C4<0110>; -L_0x12a3570/d .functor AND 1, L_0x12a3630, L_0x12a3790, C4<1>, C4<1>; -L_0x12a3570 .delay 1 (30000,30000,30000) L_0x12a3570/d; -v0x10d0c10_0 .net *"_s0", 0 0, L_0x12a3630; 1 drivers -v0x10d0cf0_0 .net *"_s1", 0 0, L_0x12a3790; 1 drivers -S_0x10d0dd0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10ceb20; - .timescale -9 -12; -P_0x10d0fe0 .param/l "i" 0 4 54, +C4<0111>; -L_0x12a3500/d .functor AND 1, L_0x12a3cc0, L_0x12a3eb0, C4<1>, C4<1>; -L_0x12a3500 .delay 1 (30000,30000,30000) L_0x12a3500/d; -v0x10d10a0_0 .net *"_s0", 0 0, L_0x12a3cc0; 1 drivers -v0x10d1180_0 .net *"_s1", 0 0, L_0x12a3eb0; 1 drivers -S_0x10d1d40 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10ce8d0; +v0x2ba0cb0_0 .net "A", 7 0, L_0x2d8b030; alias, 1 drivers +v0x2ba0db0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ba0e70_0 .net *"_s0", 0 0, L_0x2d8b950; 1 drivers +v0x2ba0f30_0 .net *"_s12", 0 0, L_0x2d8c310; 1 drivers +v0x2ba1010_0 .net *"_s16", 0 0, L_0x2d8c670; 1 drivers +v0x2ba1140_0 .net *"_s20", 0 0, L_0x2d8ca40; 1 drivers +v0x2ba1220_0 .net *"_s24", 0 0, L_0x2d8cd70; 1 drivers +v0x2ba1300_0 .net *"_s28", 0 0, L_0x2d8cd00; 1 drivers +v0x2ba13e0_0 .net *"_s4", 0 0, L_0x2d8bcf0; 1 drivers +v0x2ba1550_0 .net *"_s8", 0 0, L_0x2d8c000; 1 drivers +v0x2ba1630_0 .net "out", 7 0, L_0x2d8d100; alias, 1 drivers +L_0x2d8ba60 .part L_0x2d8b030, 0, 1; +L_0x2d8bc50 .part v0x2cdd2e0_0, 0, 1; +L_0x2d8bdb0 .part L_0x2d8b030, 1, 1; +L_0x2d8bf10 .part v0x2cdd2e0_0, 1, 1; +L_0x2d8c0c0 .part L_0x2d8b030, 2, 1; +L_0x2d8c220 .part v0x2cdd2e0_0, 2, 1; +L_0x2d8c3d0 .part L_0x2d8b030, 3, 1; +L_0x2d8c530 .part v0x2cdd2e0_0, 3, 1; +L_0x2d8c730 .part L_0x2d8b030, 4, 1; +L_0x2d8c9a0 .part v0x2cdd2e0_0, 4, 1; +L_0x2d8cab0 .part L_0x2d8b030, 5, 1; +L_0x2d8cc10 .part v0x2cdd2e0_0, 5, 1; +L_0x2d8ce30 .part L_0x2d8b030, 6, 1; +L_0x2d8cf90 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d8d100_0_0 .concat8 [ 1 1 1 1], L_0x2d8b950, L_0x2d8bcf0, L_0x2d8c000, L_0x2d8c310; +LS_0x2d8d100_0_4 .concat8 [ 1 1 1 1], L_0x2d8c670, L_0x2d8ca40, L_0x2d8cd70, L_0x2d8cd00; +L_0x2d8d100 .concat8 [ 4 4 0 0], LS_0x2d8d100_0_0, LS_0x2d8d100_0_4; +L_0x2d8d4c0 .part L_0x2d8b030, 7, 1; +L_0x2d8d6b0 .part v0x2cdd2e0_0, 7, 1; +S_0x2b9e7b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2b9e9c0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d8b950/d .functor AND 1, L_0x2d8ba60, L_0x2d8bc50, C4<1>, C4<1>; +L_0x2d8b950 .delay 1 (30000,30000,30000) L_0x2d8b950/d; +v0x2b9eaa0_0 .net *"_s0", 0 0, L_0x2d8ba60; 1 drivers +v0x2b9eb80_0 .net *"_s1", 0 0, L_0x2d8bc50; 1 drivers +S_0x2b9ec60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2b9ee70 .param/l "i" 0 4 54, +C4<01>; +L_0x2d8bcf0/d .functor AND 1, L_0x2d8bdb0, L_0x2d8bf10, C4<1>, C4<1>; +L_0x2d8bcf0 .delay 1 (30000,30000,30000) L_0x2d8bcf0/d; +v0x2b9ef30_0 .net *"_s0", 0 0, L_0x2d8bdb0; 1 drivers +v0x2b9f010_0 .net *"_s1", 0 0, L_0x2d8bf10; 1 drivers +S_0x2b9f0f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2b9f330 .param/l "i" 0 4 54, +C4<010>; +L_0x2d8c000/d .functor AND 1, L_0x2d8c0c0, L_0x2d8c220, C4<1>, C4<1>; +L_0x2d8c000 .delay 1 (30000,30000,30000) L_0x2d8c000/d; +v0x2b9f3d0_0 .net *"_s0", 0 0, L_0x2d8c0c0; 1 drivers +v0x2b9f4b0_0 .net *"_s1", 0 0, L_0x2d8c220; 1 drivers +S_0x2b9f590 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2b9f7a0 .param/l "i" 0 4 54, +C4<011>; +L_0x2d8c310/d .functor AND 1, L_0x2d8c3d0, L_0x2d8c530, C4<1>, C4<1>; +L_0x2d8c310 .delay 1 (30000,30000,30000) L_0x2d8c310/d; +v0x2b9f860_0 .net *"_s0", 0 0, L_0x2d8c3d0; 1 drivers +v0x2b9f940_0 .net *"_s1", 0 0, L_0x2d8c530; 1 drivers +S_0x2b9fa20 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2b9fc80 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d8c670/d .functor AND 1, L_0x2d8c730, L_0x2d8c9a0, C4<1>, C4<1>; +L_0x2d8c670 .delay 1 (30000,30000,30000) L_0x2d8c670/d; +v0x2b9fd40_0 .net *"_s0", 0 0, L_0x2d8c730; 1 drivers +v0x2b9fe20_0 .net *"_s1", 0 0, L_0x2d8c9a0; 1 drivers +S_0x2b9ff00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2ba0110 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d8ca40/d .functor AND 1, L_0x2d8cab0, L_0x2d8cc10, C4<1>, C4<1>; +L_0x2d8ca40 .delay 1 (30000,30000,30000) L_0x2d8ca40/d; +v0x2ba01d0_0 .net *"_s0", 0 0, L_0x2d8cab0; 1 drivers +v0x2ba02b0_0 .net *"_s1", 0 0, L_0x2d8cc10; 1 drivers +S_0x2ba0390 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2ba05a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d8cd70/d .functor AND 1, L_0x2d8ce30, L_0x2d8cf90, C4<1>, C4<1>; +L_0x2d8cd70 .delay 1 (30000,30000,30000) L_0x2d8cd70/d; +v0x2ba0660_0 .net *"_s0", 0 0, L_0x2d8ce30; 1 drivers +v0x2ba0740_0 .net *"_s1", 0 0, L_0x2d8cf90; 1 drivers +S_0x2ba0820 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2b9e570; + .timescale -9 -12; +P_0x2ba0a30 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d8cd00/d .functor AND 1, L_0x2d8d4c0, L_0x2d8d6b0, C4<1>, C4<1>; +L_0x2d8cd00 .delay 1 (30000,30000,30000) L_0x2d8cd00/d; +v0x2ba0af0_0 .net *"_s0", 0 0, L_0x2d8d4c0; 1 drivers +v0x2ba0bd0_0 .net *"_s1", 0 0, L_0x2d8d6b0; 1 drivers +S_0x2ba1790 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2b9e320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12a5900/d .functor OR 1, L_0x12a59c0, L_0x12a5b70, C4<0>, C4<0>; -L_0x12a5900 .delay 1 (30000,30000,30000) L_0x12a5900/d; -v0x10d3890_0 .net *"_s10", 0 0, L_0x12a59c0; 1 drivers -v0x10d3970_0 .net *"_s12", 0 0, L_0x12a5b70; 1 drivers -v0x10d3a50_0 .net "in", 7 0, L_0x12a3900; alias, 1 drivers -v0x10d3b20_0 .net "ors", 1 0, L_0x12a5720; 1 drivers -v0x10d3be0_0 .net "out", 0 0, L_0x12a5900; alias, 1 drivers -L_0x12a4af0 .part L_0x12a3900, 0, 4; -L_0x12a5720 .concat8 [ 1 1 0 0], L_0x12a47e0, L_0x12a5410; -L_0x12a5860 .part L_0x12a3900, 4, 4; -L_0x12a59c0 .part L_0x12a5720, 0, 1; -L_0x12a5b70 .part L_0x12a5720, 1, 1; -S_0x10d1f00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10d1d40; +L_0x2d8f100/d .functor OR 1, L_0x2d8f1c0, L_0x2d8f370, C4<0>, C4<0>; +L_0x2d8f100 .delay 1 (30000,30000,30000) L_0x2d8f100/d; +v0x2ba32e0_0 .net *"_s10", 0 0, L_0x2d8f1c0; 1 drivers +v0x2ba33c0_0 .net *"_s12", 0 0, L_0x2d8f370; 1 drivers +v0x2ba34a0_0 .net "in", 7 0, L_0x2d8d100; alias, 1 drivers +v0x2ba3570_0 .net "ors", 1 0, L_0x2d8ef20; 1 drivers +v0x2ba3630_0 .net "out", 0 0, L_0x2d8f100; alias, 1 drivers +L_0x2d8e2f0 .part L_0x2d8d100, 0, 4; +L_0x2d8ef20 .concat8 [ 1 1 0 0], L_0x2d8dfe0, L_0x2d8ec10; +L_0x2d8f060 .part L_0x2d8d100, 4, 4; +L_0x2d8f1c0 .part L_0x2d8ef20, 0, 1; +L_0x2d8f370 .part L_0x2d8ef20, 1, 1; +S_0x2ba1950 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ba1790; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12a3fa0/d .functor OR 1, L_0x12a4060, L_0x12a41c0, C4<0>, C4<0>; -L_0x12a3fa0 .delay 1 (30000,30000,30000) L_0x12a3fa0/d; -L_0x12a43f0/d .functor OR 1, L_0x12a4500, L_0x12a4660, C4<0>, C4<0>; -L_0x12a43f0 .delay 1 (30000,30000,30000) L_0x12a43f0/d; -L_0x12a47e0/d .functor OR 1, L_0x12a4850, L_0x12a4a00, C4<0>, C4<0>; -L_0x12a47e0 .delay 1 (30000,30000,30000) L_0x12a47e0/d; -v0x10d2150_0 .net *"_s0", 0 0, L_0x12a3fa0; 1 drivers -v0x10d2250_0 .net *"_s10", 0 0, L_0x12a4500; 1 drivers -v0x10d2330_0 .net *"_s12", 0 0, L_0x12a4660; 1 drivers -v0x10d23f0_0 .net *"_s14", 0 0, L_0x12a4850; 1 drivers -v0x10d24d0_0 .net *"_s16", 0 0, L_0x12a4a00; 1 drivers -v0x10d2600_0 .net *"_s3", 0 0, L_0x12a4060; 1 drivers -v0x10d26e0_0 .net *"_s5", 0 0, L_0x12a41c0; 1 drivers -v0x10d27c0_0 .net *"_s6", 0 0, L_0x12a43f0; 1 drivers -v0x10d28a0_0 .net "in", 3 0, L_0x12a4af0; 1 drivers -v0x10d2a10_0 .net "ors", 1 0, L_0x12a4300; 1 drivers -v0x10d2af0_0 .net "out", 0 0, L_0x12a47e0; 1 drivers -L_0x12a4060 .part L_0x12a4af0, 0, 1; -L_0x12a41c0 .part L_0x12a4af0, 1, 1; -L_0x12a4300 .concat8 [ 1 1 0 0], L_0x12a3fa0, L_0x12a43f0; -L_0x12a4500 .part L_0x12a4af0, 2, 1; -L_0x12a4660 .part L_0x12a4af0, 3, 1; -L_0x12a4850 .part L_0x12a4300, 0, 1; -L_0x12a4a00 .part L_0x12a4300, 1, 1; -S_0x10d2c10 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10d1d40; +L_0x2d8d7a0/d .functor OR 1, L_0x2d8d860, L_0x2d8d9c0, C4<0>, C4<0>; +L_0x2d8d7a0 .delay 1 (30000,30000,30000) L_0x2d8d7a0/d; +L_0x2d8dbf0/d .functor OR 1, L_0x2d8dd00, L_0x2d8de60, C4<0>, C4<0>; +L_0x2d8dbf0 .delay 1 (30000,30000,30000) L_0x2d8dbf0/d; +L_0x2d8dfe0/d .functor OR 1, L_0x2d8e050, L_0x2d8e200, C4<0>, C4<0>; +L_0x2d8dfe0 .delay 1 (30000,30000,30000) L_0x2d8dfe0/d; +v0x2ba1ba0_0 .net *"_s0", 0 0, L_0x2d8d7a0; 1 drivers +v0x2ba1ca0_0 .net *"_s10", 0 0, L_0x2d8dd00; 1 drivers +v0x2ba1d80_0 .net *"_s12", 0 0, L_0x2d8de60; 1 drivers +v0x2ba1e40_0 .net *"_s14", 0 0, L_0x2d8e050; 1 drivers +v0x2ba1f20_0 .net *"_s16", 0 0, L_0x2d8e200; 1 drivers +v0x2ba2050_0 .net *"_s3", 0 0, L_0x2d8d860; 1 drivers +v0x2ba2130_0 .net *"_s5", 0 0, L_0x2d8d9c0; 1 drivers +v0x2ba2210_0 .net *"_s6", 0 0, L_0x2d8dbf0; 1 drivers +v0x2ba22f0_0 .net "in", 3 0, L_0x2d8e2f0; 1 drivers +v0x2ba2460_0 .net "ors", 1 0, L_0x2d8db00; 1 drivers +v0x2ba2540_0 .net "out", 0 0, L_0x2d8dfe0; 1 drivers +L_0x2d8d860 .part L_0x2d8e2f0, 0, 1; +L_0x2d8d9c0 .part L_0x2d8e2f0, 1, 1; +L_0x2d8db00 .concat8 [ 1 1 0 0], L_0x2d8d7a0, L_0x2d8dbf0; +L_0x2d8dd00 .part L_0x2d8e2f0, 2, 1; +L_0x2d8de60 .part L_0x2d8e2f0, 3, 1; +L_0x2d8e050 .part L_0x2d8db00, 0, 1; +L_0x2d8e200 .part L_0x2d8db00, 1, 1; +S_0x2ba2660 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ba1790; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12a4c20/d .functor OR 1, L_0x12a4c90, L_0x12a4df0, C4<0>, C4<0>; -L_0x12a4c20 .delay 1 (30000,30000,30000) L_0x12a4c20/d; -L_0x12a5020/d .functor OR 1, L_0x12a5130, L_0x12a5290, C4<0>, C4<0>; -L_0x12a5020 .delay 1 (30000,30000,30000) L_0x12a5020/d; -L_0x12a5410/d .functor OR 1, L_0x12a5480, L_0x12a5630, C4<0>, C4<0>; -L_0x12a5410 .delay 1 (30000,30000,30000) L_0x12a5410/d; -v0x10d2dd0_0 .net *"_s0", 0 0, L_0x12a4c20; 1 drivers -v0x10d2ed0_0 .net *"_s10", 0 0, L_0x12a5130; 1 drivers -v0x10d2fb0_0 .net *"_s12", 0 0, L_0x12a5290; 1 drivers -v0x10d3070_0 .net *"_s14", 0 0, L_0x12a5480; 1 drivers -v0x10d3150_0 .net *"_s16", 0 0, L_0x12a5630; 1 drivers -v0x10d3280_0 .net *"_s3", 0 0, L_0x12a4c90; 1 drivers -v0x10d3360_0 .net *"_s5", 0 0, L_0x12a4df0; 1 drivers -v0x10d3440_0 .net *"_s6", 0 0, L_0x12a5020; 1 drivers -v0x10d3520_0 .net "in", 3 0, L_0x12a5860; 1 drivers -v0x10d3690_0 .net "ors", 1 0, L_0x12a4f30; 1 drivers -v0x10d3770_0 .net "out", 0 0, L_0x12a5410; 1 drivers -L_0x12a4c90 .part L_0x12a5860, 0, 1; -L_0x12a4df0 .part L_0x12a5860, 1, 1; -L_0x12a4f30 .concat8 [ 1 1 0 0], L_0x12a4c20, L_0x12a5020; -L_0x12a5130 .part L_0x12a5860, 2, 1; -L_0x12a5290 .part L_0x12a5860, 3, 1; -L_0x12a5480 .part L_0x12a4f30, 0, 1; -L_0x12a5630 .part L_0x12a4f30, 1, 1; -S_0x10d4080 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10c7990; +L_0x2d8e420/d .functor OR 1, L_0x2d8e490, L_0x2d8e5f0, C4<0>, C4<0>; +L_0x2d8e420 .delay 1 (30000,30000,30000) L_0x2d8e420/d; +L_0x2d8e820/d .functor OR 1, L_0x2d8e930, L_0x2d8ea90, C4<0>, C4<0>; +L_0x2d8e820 .delay 1 (30000,30000,30000) L_0x2d8e820/d; +L_0x2d8ec10/d .functor OR 1, L_0x2d8ec80, L_0x2d8ee30, C4<0>, C4<0>; +L_0x2d8ec10 .delay 1 (30000,30000,30000) L_0x2d8ec10/d; +v0x2ba2820_0 .net *"_s0", 0 0, L_0x2d8e420; 1 drivers +v0x2ba2920_0 .net *"_s10", 0 0, L_0x2d8e930; 1 drivers +v0x2ba2a00_0 .net *"_s12", 0 0, L_0x2d8ea90; 1 drivers +v0x2ba2ac0_0 .net *"_s14", 0 0, L_0x2d8ec80; 1 drivers +v0x2ba2ba0_0 .net *"_s16", 0 0, L_0x2d8ee30; 1 drivers +v0x2ba2cd0_0 .net *"_s3", 0 0, L_0x2d8e490; 1 drivers +v0x2ba2db0_0 .net *"_s5", 0 0, L_0x2d8e5f0; 1 drivers +v0x2ba2e90_0 .net *"_s6", 0 0, L_0x2d8e820; 1 drivers +v0x2ba2f70_0 .net "in", 3 0, L_0x2d8f060; 1 drivers +v0x2ba30e0_0 .net "ors", 1 0, L_0x2d8e730; 1 drivers +v0x2ba31c0_0 .net "out", 0 0, L_0x2d8ec10; 1 drivers +L_0x2d8e490 .part L_0x2d8f060, 0, 1; +L_0x2d8e5f0 .part L_0x2d8f060, 1, 1; +L_0x2d8e730 .concat8 [ 1 1 0 0], L_0x2d8e420, L_0x2d8e820; +L_0x2d8e930 .part L_0x2d8f060, 2, 1; +L_0x2d8ea90 .part L_0x2d8f060, 3, 1; +L_0x2d8ec80 .part L_0x2d8e730, 0, 1; +L_0x2d8ee30 .part L_0x2d8e730, 1, 1; +S_0x2ba3ad0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2b97470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -9158,80 +9687,80 @@ S_0x10d4080 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10c7990; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12a10d0/d .functor XNOR 1, L_0x12a97d0, L_0x12a9930, C4<0>, C4<0>; -L_0x12a10d0 .delay 1 (20000,20000,20000) L_0x12a10d0/d; -L_0x12a1340/d .functor AND 1, L_0x12a97d0, L_0x12a00d0, C4<1>, C4<1>; -L_0x12a1340 .delay 1 (30000,30000,30000) L_0x12a1340/d; -L_0x12a13b0/d .functor AND 1, L_0x12a10d0, L_0x129ff40, C4<1>, C4<1>; -L_0x12a13b0 .delay 1 (30000,30000,30000) L_0x12a13b0/d; -L_0x12a1510/d .functor OR 1, L_0x12a13b0, L_0x12a1340, C4<0>, C4<0>; -L_0x12a1510 .delay 1 (30000,30000,30000) L_0x12a1510/d; -v0x10d4330_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers -v0x10d4420_0 .net "a_", 0 0, L_0x129fbb0; alias, 1 drivers -v0x10d44e0_0 .net "b", 0 0, L_0x12a9930; alias, 1 drivers -v0x10d45d0_0 .net "b_", 0 0, L_0x12a00d0; alias, 1 drivers -v0x10d4670_0 .net "carryin", 0 0, L_0x129ff40; alias, 1 drivers -v0x10d47b0_0 .net "eq", 0 0, L_0x12a10d0; 1 drivers -v0x10d4870_0 .net "lt", 0 0, L_0x12a1340; 1 drivers -v0x10d4930_0 .net "out", 0 0, L_0x12a1510; 1 drivers -v0x10d49f0_0 .net "w0", 0 0, L_0x12a13b0; 1 drivers -S_0x10d4c40 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10c7990; +L_0x2d89f30/d .functor XNOR 1, L_0x2d92fa0, L_0x2d93100, C4<0>, C4<0>; +L_0x2d89f30 .delay 1 (20000,20000,20000) L_0x2d89f30/d; +L_0x2d8a0b0/d .functor AND 1, L_0x2d92fa0, L_0x2d88c80, C4<1>, C4<1>; +L_0x2d8a0b0 .delay 1 (30000,30000,30000) L_0x2d8a0b0/d; +L_0x2d8a210/d .functor AND 1, L_0x2d89f30, L_0x2d88af0, C4<1>, C4<1>; +L_0x2d8a210 .delay 1 (30000,30000,30000) L_0x2d8a210/d; +L_0x2d8a320/d .functor OR 1, L_0x2d8a210, L_0x2d8a0b0, C4<0>, C4<0>; +L_0x2d8a320 .delay 1 (30000,30000,30000) L_0x2d8a320/d; +v0x2ba3d80_0 .net "a", 0 0, L_0x2d92fa0; alias, 1 drivers +v0x2ba3e70_0 .net "a_", 0 0, L_0x2d33f60; alias, 1 drivers +v0x2ba3f30_0 .net "b", 0 0, L_0x2d93100; alias, 1 drivers +v0x2ba4020_0 .net "b_", 0 0, L_0x2d88c80; alias, 1 drivers +v0x2ba40c0_0 .net "carryin", 0 0, L_0x2d88af0; alias, 1 drivers +v0x2ba4200_0 .net "eq", 0 0, L_0x2d89f30; 1 drivers +v0x2ba42c0_0 .net "lt", 0 0, L_0x2d8a0b0; 1 drivers +v0x2ba4380_0 .net "out", 0 0, L_0x2d8a320; 1 drivers +v0x2ba4440_0 .net "w0", 0 0, L_0x2d8a210; 1 drivers +S_0x2ba4690 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2b97470; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12a0eb0/d .functor OR 1, L_0x12a0a00, L_0x10d5ea0, C4<0>, C4<0>; -L_0x12a0eb0 .delay 1 (30000,30000,30000) L_0x12a0eb0/d; -v0x10d5a30_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers -v0x10d5b80_0 .net "b", 0 0, L_0x12a00d0; alias, 1 drivers -v0x10d5c40_0 .net "c1", 0 0, L_0x12a0a00; 1 drivers -v0x10d5ce0_0 .net "c2", 0 0, L_0x10d5ea0; 1 drivers -v0x10d5db0_0 .net "carryin", 0 0, L_0x129ff40; alias, 1 drivers -v0x10d5f30_0 .net "carryout", 0 0, L_0x12a0eb0; 1 drivers -v0x10d5fd0_0 .net "s1", 0 0, L_0x12a0940; 1 drivers -v0x10d6070_0 .net "sum", 0 0, L_0x12a0b60; 1 drivers -S_0x10d4e90 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10d4c40; +L_0x2d89b10/d .functor OR 1, L_0x2d89610, L_0x2ba58f0, C4<0>, C4<0>; +L_0x2d89b10 .delay 1 (30000,30000,30000) L_0x2d89b10/d; +v0x2ba5480_0 .net "a", 0 0, L_0x2d92fa0; alias, 1 drivers +v0x2ba55d0_0 .net "b", 0 0, L_0x2d88c80; alias, 1 drivers +v0x2ba5690_0 .net "c1", 0 0, L_0x2d89610; 1 drivers +v0x2ba5730_0 .net "c2", 0 0, L_0x2ba58f0; 1 drivers +v0x2ba5800_0 .net "carryin", 0 0, L_0x2d88af0; alias, 1 drivers +v0x2ba5980_0 .net "carryout", 0 0, L_0x2d89b10; 1 drivers +v0x2ba5a20_0 .net "s1", 0 0, L_0x2d89550; 1 drivers +v0x2ba5ac0_0 .net "sum", 0 0, L_0x2d89770; 1 drivers +S_0x2ba48e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2ba4690; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12a0940/d .functor XOR 1, L_0x12a97d0, L_0x12a00d0, C4<0>, C4<0>; -L_0x12a0940 .delay 1 (30000,30000,30000) L_0x12a0940/d; -L_0x12a0a00/d .functor AND 1, L_0x12a97d0, L_0x12a00d0, C4<1>, C4<1>; -L_0x12a0a00 .delay 1 (30000,30000,30000) L_0x12a0a00/d; -v0x10d50f0_0 .net "a", 0 0, L_0x12a97d0; alias, 1 drivers -v0x10d51b0_0 .net "b", 0 0, L_0x12a00d0; alias, 1 drivers -v0x10d5270_0 .net "carryout", 0 0, L_0x12a0a00; alias, 1 drivers -v0x10d5310_0 .net "sum", 0 0, L_0x12a0940; alias, 1 drivers -S_0x10d5440 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10d4c40; +L_0x2d89550/d .functor XOR 1, L_0x2d92fa0, L_0x2d88c80, C4<0>, C4<0>; +L_0x2d89550 .delay 1 (30000,30000,30000) L_0x2d89550/d; +L_0x2d89610/d .functor AND 1, L_0x2d92fa0, L_0x2d88c80, C4<1>, C4<1>; +L_0x2d89610 .delay 1 (30000,30000,30000) L_0x2d89610/d; +v0x2ba4b40_0 .net "a", 0 0, L_0x2d92fa0; alias, 1 drivers +v0x2ba4c00_0 .net "b", 0 0, L_0x2d88c80; alias, 1 drivers +v0x2ba4cc0_0 .net "carryout", 0 0, L_0x2d89610; alias, 1 drivers +v0x2ba4d60_0 .net "sum", 0 0, L_0x2d89550; alias, 1 drivers +S_0x2ba4e90 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2ba4690; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12a0b60/d .functor XOR 1, L_0x12a0940, L_0x129ff40, C4<0>, C4<0>; -L_0x12a0b60 .delay 1 (30000,30000,30000) L_0x12a0b60/d; -L_0x10d5ea0/d .functor AND 1, L_0x12a0940, L_0x129ff40, C4<1>, C4<1>; -L_0x10d5ea0 .delay 1 (30000,30000,30000) L_0x10d5ea0/d; -v0x10d56a0_0 .net "a", 0 0, L_0x12a0940; alias, 1 drivers -v0x10d5770_0 .net "b", 0 0, L_0x129ff40; alias, 1 drivers -v0x10d5810_0 .net "carryout", 0 0, L_0x10d5ea0; alias, 1 drivers -v0x10d58e0_0 .net "sum", 0 0, L_0x12a0b60; alias, 1 drivers -S_0x10d7490 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10c7620; - .timescale -9 -12; -L_0x2b0ab3d06218 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06260 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12a9870/d .functor OR 1, L_0x2b0ab3d06218, L_0x2b0ab3d06260, C4<0>, C4<0>; -L_0x12a9870 .delay 1 (30000,30000,30000) L_0x12a9870/d; -v0x10d7680_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06218; 1 drivers -v0x10d7760_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06260; 1 drivers -S_0x10d7840 .scope generate, "alu_slices[17]" "alu_slices[17]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x10d7a50 .param/l "i" 0 3 41, +C4<010001>; -S_0x10d7b10 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10d7840; +L_0x2d89770/d .functor XOR 1, L_0x2d89550, L_0x2d88af0, C4<0>, C4<0>; +L_0x2d89770 .delay 1 (30000,30000,30000) L_0x2d89770/d; +L_0x2ba58f0/d .functor AND 1, L_0x2d89550, L_0x2d88af0, C4<1>, C4<1>; +L_0x2ba58f0 .delay 1 (30000,30000,30000) L_0x2ba58f0/d; +v0x2ba50f0_0 .net "a", 0 0, L_0x2d89550; alias, 1 drivers +v0x2ba51c0_0 .net "b", 0 0, L_0x2d88af0; alias, 1 drivers +v0x2ba5260_0 .net "carryout", 0 0, L_0x2ba58f0; alias, 1 drivers +v0x2ba5330_0 .net "sum", 0 0, L_0x2d89770; alias, 1 drivers +S_0x2ba7b50 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2b97100; + .timescale -9 -12; +L_0x2ac6110ba1e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba230 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d8b3c0/d .functor OR 1, L_0x2ac6110ba1e8, L_0x2ac6110ba230, C4<0>, C4<0>; +L_0x2d8b3c0 .delay 1 (30000,30000,30000) L_0x2d8b3c0/d; +v0x2ba7d40_0 .net/2u *"_s0", 0 0, L_0x2ac6110ba1e8; 1 drivers +v0x2ba7e20_0 .net/2u *"_s2", 0 0, L_0x2ac6110ba230; 1 drivers +S_0x2ba7f00 .scope generate, "alu_slices[17]" "alu_slices[17]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2ba8110 .param/l "i" 0 3 39, +C4<010001>; +S_0x2ba81d0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2ba7f00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -9240,445 +9769,476 @@ S_0x10d7b10 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10d7840; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12a3880/d .functor NOT 1, L_0x12b3630, C4<0>, C4<0>, C4<0>; -L_0x12a3880 .delay 1 (10000,10000,10000) L_0x12a3880/d; -L_0x125b7b0/d .functor NOT 1, L_0x12a99d0, C4<0>, C4<0>, C4<0>; -L_0x125b7b0 .delay 1 (10000,10000,10000) L_0x125b7b0/d; -L_0x12aae70/d .functor XOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; -L_0x12aae70 .delay 1 (30000,30000,30000) L_0x12aae70/d; -L_0x2b0ab3d062a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d062f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12ab520/d .functor OR 1, L_0x2b0ab3d062a8, L_0x2b0ab3d062f0, C4<0>, C4<0>; -L_0x12ab520 .delay 1 (30000,30000,30000) L_0x12ab520/d; -L_0x12ab720/d .functor AND 1, L_0x12b3630, L_0x12a99d0, C4<1>, C4<1>; -L_0x12ab720 .delay 1 (30000,30000,30000) L_0x12ab720/d; -L_0x12ab7e0/d .functor NAND 1, L_0x12b3630, L_0x12a99d0, C4<1>, C4<1>; -L_0x12ab7e0 .delay 1 (20000,20000,20000) L_0x12ab7e0/d; -L_0x12ab940/d .functor XOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; -L_0x12ab940 .delay 1 (20000,20000,20000) L_0x12ab940/d; -L_0x12abdf0/d .functor OR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; -L_0x12abdf0 .delay 1 (30000,30000,30000) L_0x12abdf0/d; -L_0x12b3530/d .functor NOT 1, L_0x12af760, C4<0>, C4<0>, C4<0>; -L_0x12b3530 .delay 1 (10000,10000,10000) L_0x12b3530/d; -v0x10e6240_0 .net "A", 0 0, L_0x12b3630; 1 drivers -v0x10e6300_0 .net "A_", 0 0, L_0x12a3880; 1 drivers -v0x10e63c0_0 .net "B", 0 0, L_0x12a99d0; 1 drivers -v0x10e6490_0 .net "B_", 0 0, L_0x125b7b0; 1 drivers -v0x10e6530_0 .net *"_s12", 0 0, L_0x12ab520; 1 drivers -v0x10e6620_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d062a8; 1 drivers -v0x10e66e0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d062f0; 1 drivers -v0x10e67c0_0 .net *"_s18", 0 0, L_0x12ab720; 1 drivers -v0x10e68a0_0 .net *"_s20", 0 0, L_0x12ab7e0; 1 drivers -v0x10e6a10_0 .net *"_s22", 0 0, L_0x12ab940; 1 drivers -v0x10e6af0_0 .net *"_s24", 0 0, L_0x12abdf0; 1 drivers -o0x2b0ab3cccd18 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10e6bd0_0 name=_s30 -o0x2b0ab3cccd48 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10e6cb0_0 name=_s32 -v0x10e6d90_0 .net *"_s8", 0 0, L_0x12aae70; 1 drivers -v0x10e6e70_0 .net "carryin", 0 0, L_0x12a9a70; 1 drivers -v0x10e6f10_0 .net "carryout", 0 0, L_0x12b31d0; 1 drivers -v0x10e6fb0_0 .net "carryouts", 7 0, L_0x1354af0; 1 drivers -v0x10e7160_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10e7200_0 .net "result", 0 0, L_0x12af760; 1 drivers -v0x10e72f0_0 .net "results", 7 0, L_0x12abbc0; 1 drivers -v0x10e7400_0 .net "zero", 0 0, L_0x12b3530; 1 drivers -LS_0x12abbc0_0_0 .concat8 [ 1 1 1 1], L_0x12aa340, L_0x12aa970, L_0x12aae70, L_0x12ab520; -LS_0x12abbc0_0_4 .concat8 [ 1 1 1 1], L_0x12ab720, L_0x12ab7e0, L_0x12ab940, L_0x12abdf0; -L_0x12abbc0 .concat8 [ 4 4 0 0], LS_0x12abbc0_0_0, LS_0x12abbc0_0_4; -LS_0x1354af0_0_0 .concat [ 1 1 1 1], L_0x12aa5f0, L_0x12aad10, o0x2b0ab3cccd18, L_0x12ab370; -LS_0x1354af0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cccd48; -L_0x1354af0 .concat [ 4 4 0 0], LS_0x1354af0_0_0, LS_0x1354af0_0_4; -S_0x10d7d90 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10d7b10; +L_0x2d93340/d .functor NOT 1, L_0x2d9d7b0, C4<0>, C4<0>, C4<0>; +L_0x2d93340 .delay 1 (10000,10000,10000) L_0x2d93340/d; +L_0x2d93400/d .functor NOT 1, L_0x2d931a0, C4<0>, C4<0>, C4<0>; +L_0x2d93400 .delay 1 (10000,10000,10000) L_0x2d93400/d; +L_0x2d94400/d .functor XOR 1, L_0x2d9d7b0, L_0x2d931a0, C4<0>, C4<0>; +L_0x2d94400 .delay 1 (30000,30000,30000) L_0x2d94400/d; +L_0x2ac6110ba278 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba2c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d944c0/d .functor OR 1, L_0x2ac6110ba278, L_0x2ac6110ba2c0, C4<0>, C4<0>; +L_0x2d944c0 .delay 1 (30000,30000,30000) L_0x2d944c0/d; +L_0x2ac6110ba308 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba350 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d94c60/d .functor OR 1, L_0x2ac6110ba308, L_0x2ac6110ba350, C4<0>, C4<0>; +L_0x2d94c60 .delay 1 (30000,30000,30000) L_0x2d94c60/d; +L_0x2d94e60/d .functor AND 1, L_0x2d9d7b0, L_0x2d931a0, C4<1>, C4<1>; +L_0x2d94e60 .delay 1 (30000,30000,30000) L_0x2d94e60/d; +L_0x2ac6110ba398 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba3e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d94f20/d .functor OR 1, L_0x2ac6110ba398, L_0x2ac6110ba3e0, C4<0>, C4<0>; +L_0x2d94f20 .delay 1 (30000,30000,30000) L_0x2d94f20/d; +L_0x2d95120/d .functor NAND 1, L_0x2d9d7b0, L_0x2d931a0, C4<1>, C4<1>; +L_0x2d95120 .delay 1 (20000,20000,20000) L_0x2d95120/d; +L_0x2ac6110ba428 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba470 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d95230/d .functor OR 1, L_0x2ac6110ba428, L_0x2ac6110ba470, C4<0>, C4<0>; +L_0x2d95230 .delay 1 (30000,30000,30000) L_0x2d95230/d; +L_0x2d953e0/d .functor NOR 1, L_0x2d9d7b0, L_0x2d931a0, C4<0>, C4<0>; +L_0x2d953e0 .delay 1 (20000,20000,20000) L_0x2d953e0/d; +L_0x2ac6110ba4b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba500 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d956b0/d .functor OR 1, L_0x2ac6110ba4b8, L_0x2ac6110ba500, C4<0>, C4<0>; +L_0x2d956b0 .delay 1 (30000,30000,30000) L_0x2d956b0/d; +L_0x2d95ab0/d .functor OR 1, L_0x2d9d7b0, L_0x2d931a0, C4<0>, C4<0>; +L_0x2d95ab0 .delay 1 (30000,30000,30000) L_0x2d95ab0/d; +L_0x2ac6110ba548 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba590 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d95f50/d .functor OR 1, L_0x2ac6110ba548, L_0x2ac6110ba590, C4<0>, C4<0>; +L_0x2d95f50 .delay 1 (30000,30000,30000) L_0x2d95f50/d; +L_0x2d9d6b0/d .functor NOT 1, L_0x2d99910, C4<0>, C4<0>, C4<0>; +L_0x2d9d6b0 .delay 1 (10000,10000,10000) L_0x2d9d6b0/d; +v0x2bb6900_0 .net "A", 0 0, L_0x2d9d7b0; 1 drivers +v0x2bb69c0_0 .net "A_", 0 0, L_0x2d93340; 1 drivers +v0x2bb6a80_0 .net "B", 0 0, L_0x2d931a0; 1 drivers +v0x2bb6b50_0 .net "B_", 0 0, L_0x2d93400; 1 drivers +v0x2bb6bf0_0 .net *"_s11", 0 0, L_0x2d944c0; 1 drivers +v0x2bb6ce0_0 .net/2s *"_s13", 0 0, L_0x2ac6110ba278; 1 drivers +v0x2bb6da0_0 .net/2s *"_s15", 0 0, L_0x2ac6110ba2c0; 1 drivers +v0x2bb6e80_0 .net *"_s19", 0 0, L_0x2d94c60; 1 drivers +v0x2bb6f60_0 .net/2s *"_s21", 0 0, L_0x2ac6110ba308; 1 drivers +v0x2bb70d0_0 .net/2s *"_s23", 0 0, L_0x2ac6110ba350; 1 drivers +v0x2bb71b0_0 .net *"_s25", 0 0, L_0x2d94e60; 1 drivers +v0x2bb7290_0 .net *"_s28", 0 0, L_0x2d94f20; 1 drivers +v0x2bb7370_0 .net/2s *"_s30", 0 0, L_0x2ac6110ba398; 1 drivers +v0x2bb7450_0 .net/2s *"_s32", 0 0, L_0x2ac6110ba3e0; 1 drivers +v0x2bb7530_0 .net *"_s34", 0 0, L_0x2d95120; 1 drivers +v0x2bb7610_0 .net *"_s37", 0 0, L_0x2d95230; 1 drivers +v0x2bb76f0_0 .net/2s *"_s39", 0 0, L_0x2ac6110ba428; 1 drivers +v0x2bb78a0_0 .net/2s *"_s41", 0 0, L_0x2ac6110ba470; 1 drivers +v0x2bb7940_0 .net *"_s43", 0 0, L_0x2d953e0; 1 drivers +v0x2bb7a20_0 .net *"_s46", 0 0, L_0x2d956b0; 1 drivers +v0x2bb7b00_0 .net/2s *"_s48", 0 0, L_0x2ac6110ba4b8; 1 drivers +v0x2bb7be0_0 .net/2s *"_s50", 0 0, L_0x2ac6110ba500; 1 drivers +v0x2bb7cc0_0 .net *"_s52", 0 0, L_0x2d95ab0; 1 drivers +v0x2bb7da0_0 .net *"_s56", 0 0, L_0x2d95f50; 1 drivers +v0x2bb7e80_0 .net/2s *"_s59", 0 0, L_0x2ac6110ba548; 1 drivers +v0x2bb7f60_0 .net/2s *"_s61", 0 0, L_0x2ac6110ba590; 1 drivers +v0x2bb8040_0 .net *"_s8", 0 0, L_0x2d94400; 1 drivers +v0x2bb8120_0 .net "carryin", 0 0, L_0x2d93240; 1 drivers +v0x2bb81c0_0 .net "carryout", 0 0, L_0x2d9d350; 1 drivers +v0x2bb8260_0 .net "carryouts", 7 0, L_0x2d95bc0; 1 drivers +v0x2bb8370_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bb8430_0 .net "result", 0 0, L_0x2d99910; 1 drivers +v0x2bb8520_0 .net "results", 7 0, L_0x2d95880; 1 drivers +v0x2bb7800_0 .net "zero", 0 0, L_0x2d9d6b0; 1 drivers +LS_0x2d95880_0_0 .concat8 [ 1 1 1 1], L_0x2d93920, L_0x2d93f50, L_0x2d94400, L_0x2d94c60; +LS_0x2d95880_0_4 .concat8 [ 1 1 1 1], L_0x2d94e60, L_0x2d95120, L_0x2d953e0, L_0x2d95ab0; +L_0x2d95880 .concat8 [ 4 4 0 0], LS_0x2d95880_0_0, LS_0x2d95880_0_4; +LS_0x2d95bc0_0_0 .concat8 [ 1 1 1 1], L_0x2d93bd0, L_0x2d942a0, L_0x2d944c0, L_0x2d94ab0; +LS_0x2d95bc0_0_4 .concat8 [ 1 1 1 1], L_0x2d94f20, L_0x2d95230, L_0x2d956b0, L_0x2d95f50; +L_0x2d95bc0 .concat8 [ 4 4 0 0], LS_0x2d95bc0_0_0, LS_0x2d95bc0_0_4; +S_0x2ba8450 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2ba81d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12aa5f0/d .functor OR 1, L_0x12aa0d0, L_0x12aa490, C4<0>, C4<0>; -L_0x12aa5f0 .delay 1 (30000,30000,30000) L_0x12aa5f0/d; -v0x10d8bc0_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers -v0x10d8c80_0 .net "b", 0 0, L_0x12a99d0; alias, 1 drivers -v0x10d8d50_0 .net "c1", 0 0, L_0x12aa0d0; 1 drivers -v0x10d8e50_0 .net "c2", 0 0, L_0x12aa490; 1 drivers -v0x10d8f20_0 .net "carryin", 0 0, L_0x12a9a70; alias, 1 drivers -v0x10d9010_0 .net "carryout", 0 0, L_0x12aa5f0; 1 drivers -v0x10d90b0_0 .net "s1", 0 0, L_0x12aa010; 1 drivers -v0x10d91a0_0 .net "sum", 0 0, L_0x12aa340; 1 drivers -S_0x10d8000 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10d7d90; +L_0x2d93bd0/d .functor OR 1, L_0x2d936b0, L_0x2d93a70, C4<0>, C4<0>; +L_0x2d93bd0 .delay 1 (30000,30000,30000) L_0x2d93bd0/d; +v0x2ba9280_0 .net "a", 0 0, L_0x2d9d7b0; alias, 1 drivers +v0x2ba9340_0 .net "b", 0 0, L_0x2d931a0; alias, 1 drivers +v0x2ba9410_0 .net "c1", 0 0, L_0x2d936b0; 1 drivers +v0x2ba9510_0 .net "c2", 0 0, L_0x2d93a70; 1 drivers +v0x2ba95e0_0 .net "carryin", 0 0, L_0x2d93240; alias, 1 drivers +v0x2ba96d0_0 .net "carryout", 0 0, L_0x2d93bd0; 1 drivers +v0x2ba9770_0 .net "s1", 0 0, L_0x2d935f0; 1 drivers +v0x2ba9860_0 .net "sum", 0 0, L_0x2d93920; 1 drivers +S_0x2ba86c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2ba8450; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12aa010/d .functor XOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; -L_0x12aa010 .delay 1 (30000,30000,30000) L_0x12aa010/d; -L_0x12aa0d0/d .functor AND 1, L_0x12b3630, L_0x12a99d0, C4<1>, C4<1>; -L_0x12aa0d0 .delay 1 (30000,30000,30000) L_0x12aa0d0/d; -v0x10d8260_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers -v0x10d8340_0 .net "b", 0 0, L_0x12a99d0; alias, 1 drivers -v0x10d8400_0 .net "carryout", 0 0, L_0x12aa0d0; alias, 1 drivers -v0x10d84a0_0 .net "sum", 0 0, L_0x12aa010; alias, 1 drivers -S_0x10d85e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10d7d90; +L_0x2d935f0/d .functor XOR 1, L_0x2d9d7b0, L_0x2d931a0, C4<0>, C4<0>; +L_0x2d935f0 .delay 1 (30000,30000,30000) L_0x2d935f0/d; +L_0x2d936b0/d .functor AND 1, L_0x2d9d7b0, L_0x2d931a0, C4<1>, C4<1>; +L_0x2d936b0 .delay 1 (30000,30000,30000) L_0x2d936b0/d; +v0x2ba8920_0 .net "a", 0 0, L_0x2d9d7b0; alias, 1 drivers +v0x2ba8a00_0 .net "b", 0 0, L_0x2d931a0; alias, 1 drivers +v0x2ba8ac0_0 .net "carryout", 0 0, L_0x2d936b0; alias, 1 drivers +v0x2ba8b60_0 .net "sum", 0 0, L_0x2d935f0; alias, 1 drivers +S_0x2ba8ca0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2ba8450; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12aa340/d .functor XOR 1, L_0x12aa010, L_0x12a9a70, C4<0>, C4<0>; -L_0x12aa340 .delay 1 (30000,30000,30000) L_0x12aa340/d; -L_0x12aa490/d .functor AND 1, L_0x12aa010, L_0x12a9a70, C4<1>, C4<1>; -L_0x12aa490 .delay 1 (30000,30000,30000) L_0x12aa490/d; -v0x10d8840_0 .net "a", 0 0, L_0x12aa010; alias, 1 drivers -v0x10d88e0_0 .net "b", 0 0, L_0x12a9a70; alias, 1 drivers -v0x10d8980_0 .net "carryout", 0 0, L_0x12aa490; alias, 1 drivers -v0x10d8a50_0 .net "sum", 0 0, L_0x12aa340; alias, 1 drivers -S_0x10d9270 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10d7b10; +L_0x2d93920/d .functor XOR 1, L_0x2d935f0, L_0x2d93240, C4<0>, C4<0>; +L_0x2d93920 .delay 1 (30000,30000,30000) L_0x2d93920/d; +L_0x2d93a70/d .functor AND 1, L_0x2d935f0, L_0x2d93240, C4<1>, C4<1>; +L_0x2d93a70 .delay 1 (30000,30000,30000) L_0x2d93a70/d; +v0x2ba8f00_0 .net "a", 0 0, L_0x2d935f0; alias, 1 drivers +v0x2ba8fa0_0 .net "b", 0 0, L_0x2d93240; alias, 1 drivers +v0x2ba9040_0 .net "carryout", 0 0, L_0x2d93a70; alias, 1 drivers +v0x2ba9110_0 .net "sum", 0 0, L_0x2d93920; alias, 1 drivers +S_0x2ba9930 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2ba81d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10de660_0 .net "ands", 7 0, L_0x12b11d0; 1 drivers -v0x10de770_0 .net "in", 7 0, L_0x1354af0; alias, 1 drivers -v0x10de830_0 .net "out", 0 0, L_0x12b31d0; alias, 1 drivers -v0x10de900_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10d9490 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10d9270; +v0x2baed20_0 .net "ands", 7 0, L_0x2d9b350; 1 drivers +v0x2baee30_0 .net "in", 7 0, L_0x2d95bc0; alias, 1 drivers +v0x2baeef0_0 .net "out", 0 0, L_0x2d9d350; alias, 1 drivers +v0x2baefc0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2ba9b50 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2ba9930; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10dbbc0_0 .net "A", 7 0, L_0x1354af0; alias, 1 drivers -v0x10dbcc0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10dbd80_0 .net *"_s0", 0 0, L_0x12afac0; 1 drivers -v0x10dbe40_0 .net *"_s12", 0 0, L_0x12b0430; 1 drivers -v0x10dbf20_0 .net *"_s16", 0 0, L_0x12b0790; 1 drivers -v0x10dc050_0 .net *"_s20", 0 0, L_0x12b0aa0; 1 drivers -v0x10dc130_0 .net *"_s24", 0 0, L_0x12b0e90; 1 drivers -v0x10dc210_0 .net *"_s28", 0 0, L_0x12b0e20; 1 drivers -v0x10dc2f0_0 .net *"_s4", 0 0, L_0x12afdd0; 1 drivers -v0x10dc460_0 .net *"_s8", 0 0, L_0x12b0120; 1 drivers -v0x10dc540_0 .net "out", 7 0, L_0x12b11d0; alias, 1 drivers -L_0x12afb80 .part L_0x1354af0, 0, 1; -L_0x12afce0 .part v0x12010b0_0, 0, 1; -L_0x12afe90 .part L_0x1354af0, 1, 1; -L_0x12b0080 .part v0x12010b0_0, 1, 1; -L_0x12b01e0 .part L_0x1354af0, 2, 1; -L_0x12b0340 .part v0x12010b0_0, 2, 1; -L_0x12b04f0 .part L_0x1354af0, 3, 1; -L_0x12b0650 .part v0x12010b0_0, 3, 1; -L_0x12b0850 .part L_0x1354af0, 4, 1; -L_0x12b09b0 .part v0x12010b0_0, 4, 1; -L_0x12b0b10 .part L_0x1354af0, 5, 1; -L_0x12b0d80 .part v0x12010b0_0, 5, 1; -L_0x12b0f80 .part L_0x1354af0, 6, 1; -L_0x12b10e0 .part v0x12010b0_0, 6, 1; -LS_0x12b11d0_0_0 .concat8 [ 1 1 1 1], L_0x12afac0, L_0x12afdd0, L_0x12b0120, L_0x12b0430; -LS_0x12b11d0_0_4 .concat8 [ 1 1 1 1], L_0x12b0790, L_0x12b0aa0, L_0x12b0e90, L_0x12b0e20; -L_0x12b11d0 .concat8 [ 4 4 0 0], LS_0x12b11d0_0_0, LS_0x12b11d0_0_4; -L_0x12b1590 .part L_0x1354af0, 7, 1; -L_0x12b1780 .part v0x12010b0_0, 7, 1; -S_0x10d96f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10d9900 .param/l "i" 0 4 54, +C4<00>; -L_0x12afac0/d .functor AND 1, L_0x12afb80, L_0x12afce0, C4<1>, C4<1>; -L_0x12afac0 .delay 1 (30000,30000,30000) L_0x12afac0/d; -v0x10d99e0_0 .net *"_s0", 0 0, L_0x12afb80; 1 drivers -v0x10d9ac0_0 .net *"_s1", 0 0, L_0x12afce0; 1 drivers -S_0x10d9ba0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10d9db0 .param/l "i" 0 4 54, +C4<01>; -L_0x12afdd0/d .functor AND 1, L_0x12afe90, L_0x12b0080, C4<1>, C4<1>; -L_0x12afdd0 .delay 1 (30000,30000,30000) L_0x12afdd0/d; -v0x10d9e70_0 .net *"_s0", 0 0, L_0x12afe90; 1 drivers -v0x10d9f50_0 .net *"_s1", 0 0, L_0x12b0080; 1 drivers -S_0x10da030 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10da240 .param/l "i" 0 4 54, +C4<010>; -L_0x12b0120/d .functor AND 1, L_0x12b01e0, L_0x12b0340, C4<1>, C4<1>; -L_0x12b0120 .delay 1 (30000,30000,30000) L_0x12b0120/d; -v0x10da2e0_0 .net *"_s0", 0 0, L_0x12b01e0; 1 drivers -v0x10da3c0_0 .net *"_s1", 0 0, L_0x12b0340; 1 drivers -S_0x10da4a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10da6b0 .param/l "i" 0 4 54, +C4<011>; -L_0x12b0430/d .functor AND 1, L_0x12b04f0, L_0x12b0650, C4<1>, C4<1>; -L_0x12b0430 .delay 1 (30000,30000,30000) L_0x12b0430/d; -v0x10da770_0 .net *"_s0", 0 0, L_0x12b04f0; 1 drivers -v0x10da850_0 .net *"_s1", 0 0, L_0x12b0650; 1 drivers -S_0x10da930 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10dab90 .param/l "i" 0 4 54, +C4<0100>; -L_0x12b0790/d .functor AND 1, L_0x12b0850, L_0x12b09b0, C4<1>, C4<1>; -L_0x12b0790 .delay 1 (30000,30000,30000) L_0x12b0790/d; -v0x10dac50_0 .net *"_s0", 0 0, L_0x12b0850; 1 drivers -v0x10dad30_0 .net *"_s1", 0 0, L_0x12b09b0; 1 drivers -S_0x10dae10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10db020 .param/l "i" 0 4 54, +C4<0101>; -L_0x12b0aa0/d .functor AND 1, L_0x12b0b10, L_0x12b0d80, C4<1>, C4<1>; -L_0x12b0aa0 .delay 1 (30000,30000,30000) L_0x12b0aa0/d; -v0x10db0e0_0 .net *"_s0", 0 0, L_0x12b0b10; 1 drivers -v0x10db1c0_0 .net *"_s1", 0 0, L_0x12b0d80; 1 drivers -S_0x10db2a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10db4b0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12b0e90/d .functor AND 1, L_0x12b0f80, L_0x12b10e0, C4<1>, C4<1>; -L_0x12b0e90 .delay 1 (30000,30000,30000) L_0x12b0e90/d; -v0x10db570_0 .net *"_s0", 0 0, L_0x12b0f80; 1 drivers -v0x10db650_0 .net *"_s1", 0 0, L_0x12b10e0; 1 drivers -S_0x10db730 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10d9490; - .timescale -9 -12; -P_0x10db940 .param/l "i" 0 4 54, +C4<0111>; -L_0x12b0e20/d .functor AND 1, L_0x12b1590, L_0x12b1780, C4<1>, C4<1>; -L_0x12b0e20 .delay 1 (30000,30000,30000) L_0x12b0e20/d; -v0x10dba00_0 .net *"_s0", 0 0, L_0x12b1590; 1 drivers -v0x10dbae0_0 .net *"_s1", 0 0, L_0x12b1780; 1 drivers -S_0x10dc6a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10d9270; +v0x2bac280_0 .net "A", 7 0, L_0x2d95bc0; alias, 1 drivers +v0x2bac380_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bac440_0 .net *"_s0", 0 0, L_0x2d99c70; 1 drivers +v0x2bac500_0 .net *"_s12", 0 0, L_0x2d9a5e0; 1 drivers +v0x2bac5e0_0 .net *"_s16", 0 0, L_0x2d9a940; 1 drivers +v0x2bac710_0 .net *"_s20", 0 0, L_0x2d9ad10; 1 drivers +v0x2bac7f0_0 .net *"_s24", 0 0, L_0x2d9b040; 1 drivers +v0x2bac8d0_0 .net *"_s28", 0 0, L_0x2d9afd0; 1 drivers +v0x2bac9b0_0 .net *"_s4", 0 0, L_0x2d99fc0; 1 drivers +v0x2bacb20_0 .net *"_s8", 0 0, L_0x2d9a2d0; 1 drivers +v0x2bacc00_0 .net "out", 7 0, L_0x2d9b350; alias, 1 drivers +L_0x2d99d30 .part L_0x2d95bc0, 0, 1; +L_0x2d99f20 .part v0x2cdd2e0_0, 0, 1; +L_0x2d9a080 .part L_0x2d95bc0, 1, 1; +L_0x2d9a1e0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d9a390 .part L_0x2d95bc0, 2, 1; +L_0x2d9a4f0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d9a6a0 .part L_0x2d95bc0, 3, 1; +L_0x2d9a800 .part v0x2cdd2e0_0, 3, 1; +L_0x2d9aa00 .part L_0x2d95bc0, 4, 1; +L_0x2d9ac70 .part v0x2cdd2e0_0, 4, 1; +L_0x2d9ad80 .part L_0x2d95bc0, 5, 1; +L_0x2d9aee0 .part v0x2cdd2e0_0, 5, 1; +L_0x2d9b100 .part L_0x2d95bc0, 6, 1; +L_0x2d9b260 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d9b350_0_0 .concat8 [ 1 1 1 1], L_0x2d99c70, L_0x2d99fc0, L_0x2d9a2d0, L_0x2d9a5e0; +LS_0x2d9b350_0_4 .concat8 [ 1 1 1 1], L_0x2d9a940, L_0x2d9ad10, L_0x2d9b040, L_0x2d9afd0; +L_0x2d9b350 .concat8 [ 4 4 0 0], LS_0x2d9b350_0_0, LS_0x2d9b350_0_4; +L_0x2d9b710 .part L_0x2d95bc0, 7, 1; +L_0x2d9b900 .part v0x2cdd2e0_0, 7, 1; +S_0x2ba9db0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2ba9fc0 .param/l "i" 0 4 54, +C4<00>; +L_0x2d99c70/d .functor AND 1, L_0x2d99d30, L_0x2d99f20, C4<1>, C4<1>; +L_0x2d99c70 .delay 1 (30000,30000,30000) L_0x2d99c70/d; +v0x2baa0a0_0 .net *"_s0", 0 0, L_0x2d99d30; 1 drivers +v0x2baa180_0 .net *"_s1", 0 0, L_0x2d99f20; 1 drivers +S_0x2baa260 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2baa470 .param/l "i" 0 4 54, +C4<01>; +L_0x2d99fc0/d .functor AND 1, L_0x2d9a080, L_0x2d9a1e0, C4<1>, C4<1>; +L_0x2d99fc0 .delay 1 (30000,30000,30000) L_0x2d99fc0/d; +v0x2baa530_0 .net *"_s0", 0 0, L_0x2d9a080; 1 drivers +v0x2baa610_0 .net *"_s1", 0 0, L_0x2d9a1e0; 1 drivers +S_0x2baa6f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2baa900 .param/l "i" 0 4 54, +C4<010>; +L_0x2d9a2d0/d .functor AND 1, L_0x2d9a390, L_0x2d9a4f0, C4<1>, C4<1>; +L_0x2d9a2d0 .delay 1 (30000,30000,30000) L_0x2d9a2d0/d; +v0x2baa9a0_0 .net *"_s0", 0 0, L_0x2d9a390; 1 drivers +v0x2baaa80_0 .net *"_s1", 0 0, L_0x2d9a4f0; 1 drivers +S_0x2baab60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2baad70 .param/l "i" 0 4 54, +C4<011>; +L_0x2d9a5e0/d .functor AND 1, L_0x2d9a6a0, L_0x2d9a800, C4<1>, C4<1>; +L_0x2d9a5e0 .delay 1 (30000,30000,30000) L_0x2d9a5e0/d; +v0x2baae30_0 .net *"_s0", 0 0, L_0x2d9a6a0; 1 drivers +v0x2baaf10_0 .net *"_s1", 0 0, L_0x2d9a800; 1 drivers +S_0x2baaff0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2bab250 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d9a940/d .functor AND 1, L_0x2d9aa00, L_0x2d9ac70, C4<1>, C4<1>; +L_0x2d9a940 .delay 1 (30000,30000,30000) L_0x2d9a940/d; +v0x2bab310_0 .net *"_s0", 0 0, L_0x2d9aa00; 1 drivers +v0x2bab3f0_0 .net *"_s1", 0 0, L_0x2d9ac70; 1 drivers +S_0x2bab4d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2bab6e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d9ad10/d .functor AND 1, L_0x2d9ad80, L_0x2d9aee0, C4<1>, C4<1>; +L_0x2d9ad10 .delay 1 (30000,30000,30000) L_0x2d9ad10/d; +v0x2bab7a0_0 .net *"_s0", 0 0, L_0x2d9ad80; 1 drivers +v0x2bab880_0 .net *"_s1", 0 0, L_0x2d9aee0; 1 drivers +S_0x2bab960 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2babb70 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d9b040/d .functor AND 1, L_0x2d9b100, L_0x2d9b260, C4<1>, C4<1>; +L_0x2d9b040 .delay 1 (30000,30000,30000) L_0x2d9b040/d; +v0x2babc30_0 .net *"_s0", 0 0, L_0x2d9b100; 1 drivers +v0x2babd10_0 .net *"_s1", 0 0, L_0x2d9b260; 1 drivers +S_0x2babdf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2ba9b50; + .timescale -9 -12; +P_0x2bac000 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d9afd0/d .functor AND 1, L_0x2d9b710, L_0x2d9b900, C4<1>, C4<1>; +L_0x2d9afd0 .delay 1 (30000,30000,30000) L_0x2d9afd0/d; +v0x2bac0c0_0 .net *"_s0", 0 0, L_0x2d9b710; 1 drivers +v0x2bac1a0_0 .net *"_s1", 0 0, L_0x2d9b900; 1 drivers +S_0x2bacd60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2ba9930; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12b31d0/d .functor OR 1, L_0x12b3290, L_0x12b3440, C4<0>, C4<0>; -L_0x12b31d0 .delay 1 (30000,30000,30000) L_0x12b31d0/d; -v0x10de1f0_0 .net *"_s10", 0 0, L_0x12b3290; 1 drivers -v0x10de2d0_0 .net *"_s12", 0 0, L_0x12b3440; 1 drivers -v0x10de3b0_0 .net "in", 7 0, L_0x12b11d0; alias, 1 drivers -v0x10de480_0 .net "ors", 1 0, L_0x12b2ff0; 1 drivers -v0x10de540_0 .net "out", 0 0, L_0x12b31d0; alias, 1 drivers -L_0x12b23c0 .part L_0x12b11d0, 0, 4; -L_0x12b2ff0 .concat8 [ 1 1 0 0], L_0x12b20b0, L_0x12b2ce0; -L_0x12b3130 .part L_0x12b11d0, 4, 4; -L_0x12b3290 .part L_0x12b2ff0, 0, 1; -L_0x12b3440 .part L_0x12b2ff0, 1, 1; -S_0x10dc860 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10dc6a0; +L_0x2d9d350/d .functor OR 1, L_0x2d9d410, L_0x2d9d5c0, C4<0>, C4<0>; +L_0x2d9d350 .delay 1 (30000,30000,30000) L_0x2d9d350/d; +v0x2bae8b0_0 .net *"_s10", 0 0, L_0x2d9d410; 1 drivers +v0x2bae990_0 .net *"_s12", 0 0, L_0x2d9d5c0; 1 drivers +v0x2baea70_0 .net "in", 7 0, L_0x2d9b350; alias, 1 drivers +v0x2baeb40_0 .net "ors", 1 0, L_0x2d9d170; 1 drivers +v0x2baec00_0 .net "out", 0 0, L_0x2d9d350; alias, 1 drivers +L_0x2d9c540 .part L_0x2d9b350, 0, 4; +L_0x2d9d170 .concat8 [ 1 1 0 0], L_0x2d9c230, L_0x2d9ce60; +L_0x2d9d2b0 .part L_0x2d9b350, 4, 4; +L_0x2d9d410 .part L_0x2d9d170, 0, 1; +L_0x2d9d5c0 .part L_0x2d9d170, 1, 1; +S_0x2bacf20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bacd60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12b1870/d .functor OR 1, L_0x12b1930, L_0x12b1a90, C4<0>, C4<0>; -L_0x12b1870 .delay 1 (30000,30000,30000) L_0x12b1870/d; -L_0x12b1cc0/d .functor OR 1, L_0x12b1dd0, L_0x12b1f30, C4<0>, C4<0>; -L_0x12b1cc0 .delay 1 (30000,30000,30000) L_0x12b1cc0/d; -L_0x12b20b0/d .functor OR 1, L_0x12b2120, L_0x12b22d0, C4<0>, C4<0>; -L_0x12b20b0 .delay 1 (30000,30000,30000) L_0x12b20b0/d; -v0x10dcab0_0 .net *"_s0", 0 0, L_0x12b1870; 1 drivers -v0x10dcbb0_0 .net *"_s10", 0 0, L_0x12b1dd0; 1 drivers -v0x10dcc90_0 .net *"_s12", 0 0, L_0x12b1f30; 1 drivers -v0x10dcd50_0 .net *"_s14", 0 0, L_0x12b2120; 1 drivers -v0x10dce30_0 .net *"_s16", 0 0, L_0x12b22d0; 1 drivers -v0x10dcf60_0 .net *"_s3", 0 0, L_0x12b1930; 1 drivers -v0x10dd040_0 .net *"_s5", 0 0, L_0x12b1a90; 1 drivers -v0x10dd120_0 .net *"_s6", 0 0, L_0x12b1cc0; 1 drivers -v0x10dd200_0 .net "in", 3 0, L_0x12b23c0; 1 drivers -v0x10dd370_0 .net "ors", 1 0, L_0x12b1bd0; 1 drivers -v0x10dd450_0 .net "out", 0 0, L_0x12b20b0; 1 drivers -L_0x12b1930 .part L_0x12b23c0, 0, 1; -L_0x12b1a90 .part L_0x12b23c0, 1, 1; -L_0x12b1bd0 .concat8 [ 1 1 0 0], L_0x12b1870, L_0x12b1cc0; -L_0x12b1dd0 .part L_0x12b23c0, 2, 1; -L_0x12b1f30 .part L_0x12b23c0, 3, 1; -L_0x12b2120 .part L_0x12b1bd0, 0, 1; -L_0x12b22d0 .part L_0x12b1bd0, 1, 1; -S_0x10dd570 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10dc6a0; +L_0x2d9b9f0/d .functor OR 1, L_0x2d9bab0, L_0x2d9bc10, C4<0>, C4<0>; +L_0x2d9b9f0 .delay 1 (30000,30000,30000) L_0x2d9b9f0/d; +L_0x2d9be40/d .functor OR 1, L_0x2d9bf50, L_0x2d9c0b0, C4<0>, C4<0>; +L_0x2d9be40 .delay 1 (30000,30000,30000) L_0x2d9be40/d; +L_0x2d9c230/d .functor OR 1, L_0x2d9c2a0, L_0x2d9c450, C4<0>, C4<0>; +L_0x2d9c230 .delay 1 (30000,30000,30000) L_0x2d9c230/d; +v0x2bad170_0 .net *"_s0", 0 0, L_0x2d9b9f0; 1 drivers +v0x2bad270_0 .net *"_s10", 0 0, L_0x2d9bf50; 1 drivers +v0x2bad350_0 .net *"_s12", 0 0, L_0x2d9c0b0; 1 drivers +v0x2bad410_0 .net *"_s14", 0 0, L_0x2d9c2a0; 1 drivers +v0x2bad4f0_0 .net *"_s16", 0 0, L_0x2d9c450; 1 drivers +v0x2bad620_0 .net *"_s3", 0 0, L_0x2d9bab0; 1 drivers +v0x2bad700_0 .net *"_s5", 0 0, L_0x2d9bc10; 1 drivers +v0x2bad7e0_0 .net *"_s6", 0 0, L_0x2d9be40; 1 drivers +v0x2bad8c0_0 .net "in", 3 0, L_0x2d9c540; 1 drivers +v0x2bada30_0 .net "ors", 1 0, L_0x2d9bd50; 1 drivers +v0x2badb10_0 .net "out", 0 0, L_0x2d9c230; 1 drivers +L_0x2d9bab0 .part L_0x2d9c540, 0, 1; +L_0x2d9bc10 .part L_0x2d9c540, 1, 1; +L_0x2d9bd50 .concat8 [ 1 1 0 0], L_0x2d9b9f0, L_0x2d9be40; +L_0x2d9bf50 .part L_0x2d9c540, 2, 1; +L_0x2d9c0b0 .part L_0x2d9c540, 3, 1; +L_0x2d9c2a0 .part L_0x2d9bd50, 0, 1; +L_0x2d9c450 .part L_0x2d9bd50, 1, 1; +S_0x2badc30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bacd60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12b24f0/d .functor OR 1, L_0x12b2560, L_0x12b26c0, C4<0>, C4<0>; -L_0x12b24f0 .delay 1 (30000,30000,30000) L_0x12b24f0/d; -L_0x12b28f0/d .functor OR 1, L_0x12b2a00, L_0x12b2b60, C4<0>, C4<0>; -L_0x12b28f0 .delay 1 (30000,30000,30000) L_0x12b28f0/d; -L_0x12b2ce0/d .functor OR 1, L_0x12b2d50, L_0x12b2f00, C4<0>, C4<0>; -L_0x12b2ce0 .delay 1 (30000,30000,30000) L_0x12b2ce0/d; -v0x10dd730_0 .net *"_s0", 0 0, L_0x12b24f0; 1 drivers -v0x10dd830_0 .net *"_s10", 0 0, L_0x12b2a00; 1 drivers -v0x10dd910_0 .net *"_s12", 0 0, L_0x12b2b60; 1 drivers -v0x10dd9d0_0 .net *"_s14", 0 0, L_0x12b2d50; 1 drivers -v0x10ddab0_0 .net *"_s16", 0 0, L_0x12b2f00; 1 drivers -v0x10ddbe0_0 .net *"_s3", 0 0, L_0x12b2560; 1 drivers -v0x10ddcc0_0 .net *"_s5", 0 0, L_0x12b26c0; 1 drivers -v0x10ddda0_0 .net *"_s6", 0 0, L_0x12b28f0; 1 drivers -v0x10dde80_0 .net "in", 3 0, L_0x12b3130; 1 drivers -v0x10ddff0_0 .net "ors", 1 0, L_0x12b2800; 1 drivers -v0x10de0d0_0 .net "out", 0 0, L_0x12b2ce0; 1 drivers -L_0x12b2560 .part L_0x12b3130, 0, 1; -L_0x12b26c0 .part L_0x12b3130, 1, 1; -L_0x12b2800 .concat8 [ 1 1 0 0], L_0x12b24f0, L_0x12b28f0; -L_0x12b2a00 .part L_0x12b3130, 2, 1; -L_0x12b2b60 .part L_0x12b3130, 3, 1; -L_0x12b2d50 .part L_0x12b2800, 0, 1; -L_0x12b2f00 .part L_0x12b2800, 1, 1; -S_0x10de9e0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10d7b10; +L_0x2d9c670/d .functor OR 1, L_0x2d9c6e0, L_0x2d9c840, C4<0>, C4<0>; +L_0x2d9c670 .delay 1 (30000,30000,30000) L_0x2d9c670/d; +L_0x2d9ca70/d .functor OR 1, L_0x2d9cb80, L_0x2d9cce0, C4<0>, C4<0>; +L_0x2d9ca70 .delay 1 (30000,30000,30000) L_0x2d9ca70/d; +L_0x2d9ce60/d .functor OR 1, L_0x2d9ced0, L_0x2d9d080, C4<0>, C4<0>; +L_0x2d9ce60 .delay 1 (30000,30000,30000) L_0x2d9ce60/d; +v0x2baddf0_0 .net *"_s0", 0 0, L_0x2d9c670; 1 drivers +v0x2badef0_0 .net *"_s10", 0 0, L_0x2d9cb80; 1 drivers +v0x2badfd0_0 .net *"_s12", 0 0, L_0x2d9cce0; 1 drivers +v0x2bae090_0 .net *"_s14", 0 0, L_0x2d9ced0; 1 drivers +v0x2bae170_0 .net *"_s16", 0 0, L_0x2d9d080; 1 drivers +v0x2bae2a0_0 .net *"_s3", 0 0, L_0x2d9c6e0; 1 drivers +v0x2bae380_0 .net *"_s5", 0 0, L_0x2d9c840; 1 drivers +v0x2bae460_0 .net *"_s6", 0 0, L_0x2d9ca70; 1 drivers +v0x2bae540_0 .net "in", 3 0, L_0x2d9d2b0; 1 drivers +v0x2bae6b0_0 .net "ors", 1 0, L_0x2d9c980; 1 drivers +v0x2bae790_0 .net "out", 0 0, L_0x2d9ce60; 1 drivers +L_0x2d9c6e0 .part L_0x2d9d2b0, 0, 1; +L_0x2d9c840 .part L_0x2d9d2b0, 1, 1; +L_0x2d9c980 .concat8 [ 1 1 0 0], L_0x2d9c670, L_0x2d9ca70; +L_0x2d9cb80 .part L_0x2d9d2b0, 2, 1; +L_0x2d9cce0 .part L_0x2d9d2b0, 3, 1; +L_0x2d9ced0 .part L_0x2d9c980, 0, 1; +L_0x2d9d080 .part L_0x2d9c980, 1, 1; +S_0x2baf0a0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2ba81d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10e3e10_0 .net "ands", 7 0, L_0x12ad760; 1 drivers -v0x10e3f20_0 .net "in", 7 0, L_0x12abbc0; alias, 1 drivers -v0x10e3fe0_0 .net "out", 0 0, L_0x12af760; alias, 1 drivers -v0x10e40b0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10dec30 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10de9e0; +v0x2bb44d0_0 .net "ands", 7 0, L_0x2d97910; 1 drivers +v0x2bb45e0_0 .net "in", 7 0, L_0x2d95880; alias, 1 drivers +v0x2bb46a0_0 .net "out", 0 0, L_0x2d99910; alias, 1 drivers +v0x2bb4770_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2baf2f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2baf0a0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10e1370_0 .net "A", 7 0, L_0x12abbc0; alias, 1 drivers -v0x10e1470_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10e1530_0 .net *"_s0", 0 0, L_0x12abf50; 1 drivers -v0x10e15f0_0 .net *"_s12", 0 0, L_0x12ac910; 1 drivers -v0x10e16d0_0 .net *"_s16", 0 0, L_0x12acc70; 1 drivers -v0x10e1800_0 .net *"_s20", 0 0, L_0x12ad0a0; 1 drivers -v0x10e18e0_0 .net *"_s24", 0 0, L_0x12ad3d0; 1 drivers -v0x10e19c0_0 .net *"_s28", 0 0, L_0x12ad360; 1 drivers -v0x10e1aa0_0 .net *"_s4", 0 0, L_0x12ac2f0; 1 drivers -v0x10e1c10_0 .net *"_s8", 0 0, L_0x12ac600; 1 drivers -v0x10e1cf0_0 .net "out", 7 0, L_0x12ad760; alias, 1 drivers -L_0x12ac060 .part L_0x12abbc0, 0, 1; -L_0x12ac250 .part v0x12010b0_0, 0, 1; -L_0x12ac3b0 .part L_0x12abbc0, 1, 1; -L_0x12ac510 .part v0x12010b0_0, 1, 1; -L_0x12ac6c0 .part L_0x12abbc0, 2, 1; -L_0x12ac820 .part v0x12010b0_0, 2, 1; -L_0x12ac9d0 .part L_0x12abbc0, 3, 1; -L_0x12acb30 .part v0x12010b0_0, 3, 1; -L_0x12acd30 .part L_0x12abbc0, 4, 1; -L_0x12acfa0 .part v0x12010b0_0, 4, 1; -L_0x12ad110 .part L_0x12abbc0, 5, 1; -L_0x12ad270 .part v0x12010b0_0, 5, 1; -L_0x12ad490 .part L_0x12abbc0, 6, 1; -L_0x12ad5f0 .part v0x12010b0_0, 6, 1; -LS_0x12ad760_0_0 .concat8 [ 1 1 1 1], L_0x12abf50, L_0x12ac2f0, L_0x12ac600, L_0x12ac910; -LS_0x12ad760_0_4 .concat8 [ 1 1 1 1], L_0x12acc70, L_0x12ad0a0, L_0x12ad3d0, L_0x12ad360; -L_0x12ad760 .concat8 [ 4 4 0 0], LS_0x12ad760_0_0, LS_0x12ad760_0_4; -L_0x12adb20 .part L_0x12abbc0, 7, 1; -L_0x12add10 .part v0x12010b0_0, 7, 1; -S_0x10dee70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10df080 .param/l "i" 0 4 54, +C4<00>; -L_0x12abf50/d .functor AND 1, L_0x12ac060, L_0x12ac250, C4<1>, C4<1>; -L_0x12abf50 .delay 1 (30000,30000,30000) L_0x12abf50/d; -v0x10df160_0 .net *"_s0", 0 0, L_0x12ac060; 1 drivers -v0x10df240_0 .net *"_s1", 0 0, L_0x12ac250; 1 drivers -S_0x10df320 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10df530 .param/l "i" 0 4 54, +C4<01>; -L_0x12ac2f0/d .functor AND 1, L_0x12ac3b0, L_0x12ac510, C4<1>, C4<1>; -L_0x12ac2f0 .delay 1 (30000,30000,30000) L_0x12ac2f0/d; -v0x10df5f0_0 .net *"_s0", 0 0, L_0x12ac3b0; 1 drivers -v0x10df6d0_0 .net *"_s1", 0 0, L_0x12ac510; 1 drivers -S_0x10df7b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10df9f0 .param/l "i" 0 4 54, +C4<010>; -L_0x12ac600/d .functor AND 1, L_0x12ac6c0, L_0x12ac820, C4<1>, C4<1>; -L_0x12ac600 .delay 1 (30000,30000,30000) L_0x12ac600/d; -v0x10dfa90_0 .net *"_s0", 0 0, L_0x12ac6c0; 1 drivers -v0x10dfb70_0 .net *"_s1", 0 0, L_0x12ac820; 1 drivers -S_0x10dfc50 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10dfe60 .param/l "i" 0 4 54, +C4<011>; -L_0x12ac910/d .functor AND 1, L_0x12ac9d0, L_0x12acb30, C4<1>, C4<1>; -L_0x12ac910 .delay 1 (30000,30000,30000) L_0x12ac910/d; -v0x10dff20_0 .net *"_s0", 0 0, L_0x12ac9d0; 1 drivers -v0x10e0000_0 .net *"_s1", 0 0, L_0x12acb30; 1 drivers -S_0x10e00e0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10e0340 .param/l "i" 0 4 54, +C4<0100>; -L_0x12acc70/d .functor AND 1, L_0x12acd30, L_0x12acfa0, C4<1>, C4<1>; -L_0x12acc70 .delay 1 (30000,30000,30000) L_0x12acc70/d; -v0x10e0400_0 .net *"_s0", 0 0, L_0x12acd30; 1 drivers -v0x10e04e0_0 .net *"_s1", 0 0, L_0x12acfa0; 1 drivers -S_0x10e05c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10e07d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x12ad0a0/d .functor AND 1, L_0x12ad110, L_0x12ad270, C4<1>, C4<1>; -L_0x12ad0a0 .delay 1 (30000,30000,30000) L_0x12ad0a0/d; -v0x10e0890_0 .net *"_s0", 0 0, L_0x12ad110; 1 drivers -v0x10e0970_0 .net *"_s1", 0 0, L_0x12ad270; 1 drivers -S_0x10e0a50 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10e0c60 .param/l "i" 0 4 54, +C4<0110>; -L_0x12ad3d0/d .functor AND 1, L_0x12ad490, L_0x12ad5f0, C4<1>, C4<1>; -L_0x12ad3d0 .delay 1 (30000,30000,30000) L_0x12ad3d0/d; -v0x10e0d20_0 .net *"_s0", 0 0, L_0x12ad490; 1 drivers -v0x10e0e00_0 .net *"_s1", 0 0, L_0x12ad5f0; 1 drivers -S_0x10e0ee0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10dec30; - .timescale -9 -12; -P_0x10e10f0 .param/l "i" 0 4 54, +C4<0111>; -L_0x12ad360/d .functor AND 1, L_0x12adb20, L_0x12add10, C4<1>, C4<1>; -L_0x12ad360 .delay 1 (30000,30000,30000) L_0x12ad360/d; -v0x10e11b0_0 .net *"_s0", 0 0, L_0x12adb20; 1 drivers -v0x10e1290_0 .net *"_s1", 0 0, L_0x12add10; 1 drivers -S_0x10e1e50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10de9e0; +v0x2bb1a30_0 .net "A", 7 0, L_0x2d95880; alias, 1 drivers +v0x2bb1b30_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bb1bf0_0 .net *"_s0", 0 0, L_0x2d96100; 1 drivers +v0x2bb1cb0_0 .net *"_s12", 0 0, L_0x2d96ac0; 1 drivers +v0x2bb1d90_0 .net *"_s16", 0 0, L_0x2d96e20; 1 drivers +v0x2bb1ec0_0 .net *"_s20", 0 0, L_0x2d97250; 1 drivers +v0x2bb1fa0_0 .net *"_s24", 0 0, L_0x2d97580; 1 drivers +v0x2bb2080_0 .net *"_s28", 0 0, L_0x2d97510; 1 drivers +v0x2bb2160_0 .net *"_s4", 0 0, L_0x2d964a0; 1 drivers +v0x2bb22d0_0 .net *"_s8", 0 0, L_0x2d967b0; 1 drivers +v0x2bb23b0_0 .net "out", 7 0, L_0x2d97910; alias, 1 drivers +L_0x2d96210 .part L_0x2d95880, 0, 1; +L_0x2d96400 .part v0x2cdd2e0_0, 0, 1; +L_0x2d96560 .part L_0x2d95880, 1, 1; +L_0x2d966c0 .part v0x2cdd2e0_0, 1, 1; +L_0x2d96870 .part L_0x2d95880, 2, 1; +L_0x2d969d0 .part v0x2cdd2e0_0, 2, 1; +L_0x2d96b80 .part L_0x2d95880, 3, 1; +L_0x2d96ce0 .part v0x2cdd2e0_0, 3, 1; +L_0x2d96ee0 .part L_0x2d95880, 4, 1; +L_0x2d97150 .part v0x2cdd2e0_0, 4, 1; +L_0x2d972c0 .part L_0x2d95880, 5, 1; +L_0x2d97420 .part v0x2cdd2e0_0, 5, 1; +L_0x2d97640 .part L_0x2d95880, 6, 1; +L_0x2d977a0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2d97910_0_0 .concat8 [ 1 1 1 1], L_0x2d96100, L_0x2d964a0, L_0x2d967b0, L_0x2d96ac0; +LS_0x2d97910_0_4 .concat8 [ 1 1 1 1], L_0x2d96e20, L_0x2d97250, L_0x2d97580, L_0x2d97510; +L_0x2d97910 .concat8 [ 4 4 0 0], LS_0x2d97910_0_0, LS_0x2d97910_0_4; +L_0x2d97cd0 .part L_0x2d95880, 7, 1; +L_0x2d97ec0 .part v0x2cdd2e0_0, 7, 1; +S_0x2baf530 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2baf740 .param/l "i" 0 4 54, +C4<00>; +L_0x2d96100/d .functor AND 1, L_0x2d96210, L_0x2d96400, C4<1>, C4<1>; +L_0x2d96100 .delay 1 (30000,30000,30000) L_0x2d96100/d; +v0x2baf820_0 .net *"_s0", 0 0, L_0x2d96210; 1 drivers +v0x2baf900_0 .net *"_s1", 0 0, L_0x2d96400; 1 drivers +S_0x2baf9e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bafbf0 .param/l "i" 0 4 54, +C4<01>; +L_0x2d964a0/d .functor AND 1, L_0x2d96560, L_0x2d966c0, C4<1>, C4<1>; +L_0x2d964a0 .delay 1 (30000,30000,30000) L_0x2d964a0/d; +v0x2bafcb0_0 .net *"_s0", 0 0, L_0x2d96560; 1 drivers +v0x2bafd90_0 .net *"_s1", 0 0, L_0x2d966c0; 1 drivers +S_0x2bafe70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bb00b0 .param/l "i" 0 4 54, +C4<010>; +L_0x2d967b0/d .functor AND 1, L_0x2d96870, L_0x2d969d0, C4<1>, C4<1>; +L_0x2d967b0 .delay 1 (30000,30000,30000) L_0x2d967b0/d; +v0x2bb0150_0 .net *"_s0", 0 0, L_0x2d96870; 1 drivers +v0x2bb0230_0 .net *"_s1", 0 0, L_0x2d969d0; 1 drivers +S_0x2bb0310 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bb0520 .param/l "i" 0 4 54, +C4<011>; +L_0x2d96ac0/d .functor AND 1, L_0x2d96b80, L_0x2d96ce0, C4<1>, C4<1>; +L_0x2d96ac0 .delay 1 (30000,30000,30000) L_0x2d96ac0/d; +v0x2bb05e0_0 .net *"_s0", 0 0, L_0x2d96b80; 1 drivers +v0x2bb06c0_0 .net *"_s1", 0 0, L_0x2d96ce0; 1 drivers +S_0x2bb07a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bb0a00 .param/l "i" 0 4 54, +C4<0100>; +L_0x2d96e20/d .functor AND 1, L_0x2d96ee0, L_0x2d97150, C4<1>, C4<1>; +L_0x2d96e20 .delay 1 (30000,30000,30000) L_0x2d96e20/d; +v0x2bb0ac0_0 .net *"_s0", 0 0, L_0x2d96ee0; 1 drivers +v0x2bb0ba0_0 .net *"_s1", 0 0, L_0x2d97150; 1 drivers +S_0x2bb0c80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bb0e90 .param/l "i" 0 4 54, +C4<0101>; +L_0x2d97250/d .functor AND 1, L_0x2d972c0, L_0x2d97420, C4<1>, C4<1>; +L_0x2d97250 .delay 1 (30000,30000,30000) L_0x2d97250/d; +v0x2bb0f50_0 .net *"_s0", 0 0, L_0x2d972c0; 1 drivers +v0x2bb1030_0 .net *"_s1", 0 0, L_0x2d97420; 1 drivers +S_0x2bb1110 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bb1320 .param/l "i" 0 4 54, +C4<0110>; +L_0x2d97580/d .functor AND 1, L_0x2d97640, L_0x2d977a0, C4<1>, C4<1>; +L_0x2d97580 .delay 1 (30000,30000,30000) L_0x2d97580/d; +v0x2bb13e0_0 .net *"_s0", 0 0, L_0x2d97640; 1 drivers +v0x2bb14c0_0 .net *"_s1", 0 0, L_0x2d977a0; 1 drivers +S_0x2bb15a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2baf2f0; + .timescale -9 -12; +P_0x2bb17b0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2d97510/d .functor AND 1, L_0x2d97cd0, L_0x2d97ec0, C4<1>, C4<1>; +L_0x2d97510 .delay 1 (30000,30000,30000) L_0x2d97510/d; +v0x2bb1870_0 .net *"_s0", 0 0, L_0x2d97cd0; 1 drivers +v0x2bb1950_0 .net *"_s1", 0 0, L_0x2d97ec0; 1 drivers +S_0x2bb2510 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2baf0a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12af760/d .functor OR 1, L_0x12af820, L_0x12af9d0, C4<0>, C4<0>; -L_0x12af760 .delay 1 (30000,30000,30000) L_0x12af760/d; -v0x10e39a0_0 .net *"_s10", 0 0, L_0x12af820; 1 drivers -v0x10e3a80_0 .net *"_s12", 0 0, L_0x12af9d0; 1 drivers -v0x10e3b60_0 .net "in", 7 0, L_0x12ad760; alias, 1 drivers -v0x10e3c30_0 .net "ors", 1 0, L_0x12af580; 1 drivers -v0x10e3cf0_0 .net "out", 0 0, L_0x12af760; alias, 1 drivers -L_0x12ae950 .part L_0x12ad760, 0, 4; -L_0x12af580 .concat8 [ 1 1 0 0], L_0x12ae640, L_0x12af270; -L_0x12af6c0 .part L_0x12ad760, 4, 4; -L_0x12af820 .part L_0x12af580, 0, 1; -L_0x12af9d0 .part L_0x12af580, 1, 1; -S_0x10e2010 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10e1e50; +L_0x2d99910/d .functor OR 1, L_0x2d999d0, L_0x2d99b80, C4<0>, C4<0>; +L_0x2d99910 .delay 1 (30000,30000,30000) L_0x2d99910/d; +v0x2bb4060_0 .net *"_s10", 0 0, L_0x2d999d0; 1 drivers +v0x2bb4140_0 .net *"_s12", 0 0, L_0x2d99b80; 1 drivers +v0x2bb4220_0 .net "in", 7 0, L_0x2d97910; alias, 1 drivers +v0x2bb42f0_0 .net "ors", 1 0, L_0x2d99730; 1 drivers +v0x2bb43b0_0 .net "out", 0 0, L_0x2d99910; alias, 1 drivers +L_0x2d98b00 .part L_0x2d97910, 0, 4; +L_0x2d99730 .concat8 [ 1 1 0 0], L_0x2d987f0, L_0x2d99420; +L_0x2d99870 .part L_0x2d97910, 4, 4; +L_0x2d999d0 .part L_0x2d99730, 0, 1; +L_0x2d99b80 .part L_0x2d99730, 1, 1; +S_0x2bb26d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bb2510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12ade00/d .functor OR 1, L_0x12adec0, L_0x12ae020, C4<0>, C4<0>; -L_0x12ade00 .delay 1 (30000,30000,30000) L_0x12ade00/d; -L_0x12ae250/d .functor OR 1, L_0x12ae360, L_0x12ae4c0, C4<0>, C4<0>; -L_0x12ae250 .delay 1 (30000,30000,30000) L_0x12ae250/d; -L_0x12ae640/d .functor OR 1, L_0x12ae6b0, L_0x12ae860, C4<0>, C4<0>; -L_0x12ae640 .delay 1 (30000,30000,30000) L_0x12ae640/d; -v0x10e2260_0 .net *"_s0", 0 0, L_0x12ade00; 1 drivers -v0x10e2360_0 .net *"_s10", 0 0, L_0x12ae360; 1 drivers -v0x10e2440_0 .net *"_s12", 0 0, L_0x12ae4c0; 1 drivers -v0x10e2500_0 .net *"_s14", 0 0, L_0x12ae6b0; 1 drivers -v0x10e25e0_0 .net *"_s16", 0 0, L_0x12ae860; 1 drivers -v0x10e2710_0 .net *"_s3", 0 0, L_0x12adec0; 1 drivers -v0x10e27f0_0 .net *"_s5", 0 0, L_0x12ae020; 1 drivers -v0x10e28d0_0 .net *"_s6", 0 0, L_0x12ae250; 1 drivers -v0x10e29b0_0 .net "in", 3 0, L_0x12ae950; 1 drivers -v0x10e2b20_0 .net "ors", 1 0, L_0x12ae160; 1 drivers -v0x10e2c00_0 .net "out", 0 0, L_0x12ae640; 1 drivers -L_0x12adec0 .part L_0x12ae950, 0, 1; -L_0x12ae020 .part L_0x12ae950, 1, 1; -L_0x12ae160 .concat8 [ 1 1 0 0], L_0x12ade00, L_0x12ae250; -L_0x12ae360 .part L_0x12ae950, 2, 1; -L_0x12ae4c0 .part L_0x12ae950, 3, 1; -L_0x12ae6b0 .part L_0x12ae160, 0, 1; -L_0x12ae860 .part L_0x12ae160, 1, 1; -S_0x10e2d20 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10e1e50; +L_0x2d97fb0/d .functor OR 1, L_0x2d98070, L_0x2d981d0, C4<0>, C4<0>; +L_0x2d97fb0 .delay 1 (30000,30000,30000) L_0x2d97fb0/d; +L_0x2d98400/d .functor OR 1, L_0x2d98510, L_0x2d98670, C4<0>, C4<0>; +L_0x2d98400 .delay 1 (30000,30000,30000) L_0x2d98400/d; +L_0x2d987f0/d .functor OR 1, L_0x2d98860, L_0x2d98a10, C4<0>, C4<0>; +L_0x2d987f0 .delay 1 (30000,30000,30000) L_0x2d987f0/d; +v0x2bb2920_0 .net *"_s0", 0 0, L_0x2d97fb0; 1 drivers +v0x2bb2a20_0 .net *"_s10", 0 0, L_0x2d98510; 1 drivers +v0x2bb2b00_0 .net *"_s12", 0 0, L_0x2d98670; 1 drivers +v0x2bb2bc0_0 .net *"_s14", 0 0, L_0x2d98860; 1 drivers +v0x2bb2ca0_0 .net *"_s16", 0 0, L_0x2d98a10; 1 drivers +v0x2bb2dd0_0 .net *"_s3", 0 0, L_0x2d98070; 1 drivers +v0x2bb2eb0_0 .net *"_s5", 0 0, L_0x2d981d0; 1 drivers +v0x2bb2f90_0 .net *"_s6", 0 0, L_0x2d98400; 1 drivers +v0x2bb3070_0 .net "in", 3 0, L_0x2d98b00; 1 drivers +v0x2bb31e0_0 .net "ors", 1 0, L_0x2d98310; 1 drivers +v0x2bb32c0_0 .net "out", 0 0, L_0x2d987f0; 1 drivers +L_0x2d98070 .part L_0x2d98b00, 0, 1; +L_0x2d981d0 .part L_0x2d98b00, 1, 1; +L_0x2d98310 .concat8 [ 1 1 0 0], L_0x2d97fb0, L_0x2d98400; +L_0x2d98510 .part L_0x2d98b00, 2, 1; +L_0x2d98670 .part L_0x2d98b00, 3, 1; +L_0x2d98860 .part L_0x2d98310, 0, 1; +L_0x2d98a10 .part L_0x2d98310, 1, 1; +S_0x2bb33e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bb2510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12aea80/d .functor OR 1, L_0x12aeaf0, L_0x12aec50, C4<0>, C4<0>; -L_0x12aea80 .delay 1 (30000,30000,30000) L_0x12aea80/d; -L_0x12aee80/d .functor OR 1, L_0x12aef90, L_0x12af0f0, C4<0>, C4<0>; -L_0x12aee80 .delay 1 (30000,30000,30000) L_0x12aee80/d; -L_0x12af270/d .functor OR 1, L_0x12af2e0, L_0x12af490, C4<0>, C4<0>; -L_0x12af270 .delay 1 (30000,30000,30000) L_0x12af270/d; -v0x10e2ee0_0 .net *"_s0", 0 0, L_0x12aea80; 1 drivers -v0x10e2fe0_0 .net *"_s10", 0 0, L_0x12aef90; 1 drivers -v0x10e30c0_0 .net *"_s12", 0 0, L_0x12af0f0; 1 drivers -v0x10e3180_0 .net *"_s14", 0 0, L_0x12af2e0; 1 drivers -v0x10e3260_0 .net *"_s16", 0 0, L_0x12af490; 1 drivers -v0x10e3390_0 .net *"_s3", 0 0, L_0x12aeaf0; 1 drivers -v0x10e3470_0 .net *"_s5", 0 0, L_0x12aec50; 1 drivers -v0x10e3550_0 .net *"_s6", 0 0, L_0x12aee80; 1 drivers -v0x10e3630_0 .net "in", 3 0, L_0x12af6c0; 1 drivers -v0x10e37a0_0 .net "ors", 1 0, L_0x12aed90; 1 drivers -v0x10e3880_0 .net "out", 0 0, L_0x12af270; 1 drivers -L_0x12aeaf0 .part L_0x12af6c0, 0, 1; -L_0x12aec50 .part L_0x12af6c0, 1, 1; -L_0x12aed90 .concat8 [ 1 1 0 0], L_0x12aea80, L_0x12aee80; -L_0x12aef90 .part L_0x12af6c0, 2, 1; -L_0x12af0f0 .part L_0x12af6c0, 3, 1; -L_0x12af2e0 .part L_0x12aed90, 0, 1; -L_0x12af490 .part L_0x12aed90, 1, 1; -S_0x10e4190 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10d7b10; +L_0x2d98c30/d .functor OR 1, L_0x2d98ca0, L_0x2d98e00, C4<0>, C4<0>; +L_0x2d98c30 .delay 1 (30000,30000,30000) L_0x2d98c30/d; +L_0x2d99030/d .functor OR 1, L_0x2d99140, L_0x2d992a0, C4<0>, C4<0>; +L_0x2d99030 .delay 1 (30000,30000,30000) L_0x2d99030/d; +L_0x2d99420/d .functor OR 1, L_0x2d99490, L_0x2d99640, C4<0>, C4<0>; +L_0x2d99420 .delay 1 (30000,30000,30000) L_0x2d99420/d; +v0x2bb35a0_0 .net *"_s0", 0 0, L_0x2d98c30; 1 drivers +v0x2bb36a0_0 .net *"_s10", 0 0, L_0x2d99140; 1 drivers +v0x2bb3780_0 .net *"_s12", 0 0, L_0x2d992a0; 1 drivers +v0x2bb3840_0 .net *"_s14", 0 0, L_0x2d99490; 1 drivers +v0x2bb3920_0 .net *"_s16", 0 0, L_0x2d99640; 1 drivers +v0x2bb3a50_0 .net *"_s3", 0 0, L_0x2d98ca0; 1 drivers +v0x2bb3b30_0 .net *"_s5", 0 0, L_0x2d98e00; 1 drivers +v0x2bb3c10_0 .net *"_s6", 0 0, L_0x2d99030; 1 drivers +v0x2bb3cf0_0 .net "in", 3 0, L_0x2d99870; 1 drivers +v0x2bb3e60_0 .net "ors", 1 0, L_0x2d98f40; 1 drivers +v0x2bb3f40_0 .net "out", 0 0, L_0x2d99420; 1 drivers +L_0x2d98ca0 .part L_0x2d99870, 0, 1; +L_0x2d98e00 .part L_0x2d99870, 1, 1; +L_0x2d98f40 .concat8 [ 1 1 0 0], L_0x2d98c30, L_0x2d99030; +L_0x2d99140 .part L_0x2d99870, 2, 1; +L_0x2d992a0 .part L_0x2d99870, 3, 1; +L_0x2d99490 .part L_0x2d98f40, 0, 1; +L_0x2d99640 .part L_0x2d98f40, 1, 1; +S_0x2bb4850 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2ba81d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -9686,80 +10246,80 @@ S_0x10e4190 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10d7b10; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12aaf30/d .functor XNOR 1, L_0x12b3630, L_0x12a99d0, C4<0>, C4<0>; -L_0x12aaf30 .delay 1 (20000,20000,20000) L_0x12aaf30/d; -L_0x12ab1a0/d .functor AND 1, L_0x12b3630, L_0x125b7b0, C4<1>, C4<1>; -L_0x12ab1a0 .delay 1 (30000,30000,30000) L_0x12ab1a0/d; -L_0x12ab210/d .functor AND 1, L_0x12aaf30, L_0x12a9a70, C4<1>, C4<1>; -L_0x12ab210 .delay 1 (30000,30000,30000) L_0x12ab210/d; -L_0x12ab370/d .functor OR 1, L_0x12ab210, L_0x12ab1a0, C4<0>, C4<0>; -L_0x12ab370 .delay 1 (30000,30000,30000) L_0x12ab370/d; -v0x10e4440_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers -v0x10e4530_0 .net "a_", 0 0, L_0x12a3880; alias, 1 drivers -v0x10e45f0_0 .net "b", 0 0, L_0x12a99d0; alias, 1 drivers -v0x10e46e0_0 .net "b_", 0 0, L_0x125b7b0; alias, 1 drivers -v0x10e4780_0 .net "carryin", 0 0, L_0x12a9a70; alias, 1 drivers -v0x10e48c0_0 .net "eq", 0 0, L_0x12aaf30; 1 drivers -v0x10e4980_0 .net "lt", 0 0, L_0x12ab1a0; 1 drivers -v0x10e4a40_0 .net "out", 0 0, L_0x12ab370; 1 drivers -v0x10e4b00_0 .net "w0", 0 0, L_0x12ab210; 1 drivers -S_0x10e4d50 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10d7b10; +L_0x2d946c0/d .functor XNOR 1, L_0x2d9d7b0, L_0x2d931a0, C4<0>, C4<0>; +L_0x2d946c0 .delay 1 (20000,20000,20000) L_0x2d946c0/d; +L_0x2d94840/d .functor AND 1, L_0x2d9d7b0, L_0x2d93400, C4<1>, C4<1>; +L_0x2d94840 .delay 1 (30000,30000,30000) L_0x2d94840/d; +L_0x2d949a0/d .functor AND 1, L_0x2d946c0, L_0x2d93240, C4<1>, C4<1>; +L_0x2d949a0 .delay 1 (30000,30000,30000) L_0x2d949a0/d; +L_0x2d94ab0/d .functor OR 1, L_0x2d949a0, L_0x2d94840, C4<0>, C4<0>; +L_0x2d94ab0 .delay 1 (30000,30000,30000) L_0x2d94ab0/d; +v0x2bb4b00_0 .net "a", 0 0, L_0x2d9d7b0; alias, 1 drivers +v0x2bb4bf0_0 .net "a_", 0 0, L_0x2d93340; alias, 1 drivers +v0x2bb4cb0_0 .net "b", 0 0, L_0x2d931a0; alias, 1 drivers +v0x2bb4da0_0 .net "b_", 0 0, L_0x2d93400; alias, 1 drivers +v0x2bb4e40_0 .net "carryin", 0 0, L_0x2d93240; alias, 1 drivers +v0x2bb4f80_0 .net "eq", 0 0, L_0x2d946c0; 1 drivers +v0x2bb5040_0 .net "lt", 0 0, L_0x2d94840; 1 drivers +v0x2bb5100_0 .net "out", 0 0, L_0x2d94ab0; 1 drivers +v0x2bb51c0_0 .net "w0", 0 0, L_0x2d949a0; 1 drivers +S_0x2bb5410 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2ba81d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12aad10/d .functor OR 1, L_0x12aa810, L_0x10e5fb0, C4<0>, C4<0>; -L_0x12aad10 .delay 1 (30000,30000,30000) L_0x12aad10/d; -v0x10e5b40_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers -v0x10e5c90_0 .net "b", 0 0, L_0x125b7b0; alias, 1 drivers -v0x10e5d50_0 .net "c1", 0 0, L_0x12aa810; 1 drivers -v0x10e5df0_0 .net "c2", 0 0, L_0x10e5fb0; 1 drivers -v0x10e5ec0_0 .net "carryin", 0 0, L_0x12a9a70; alias, 1 drivers -v0x10e6040_0 .net "carryout", 0 0, L_0x12aad10; 1 drivers -v0x10e60e0_0 .net "s1", 0 0, L_0x12aa750; 1 drivers -v0x10e6180_0 .net "sum", 0 0, L_0x12aa970; 1 drivers -S_0x10e4fa0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10e4d50; +L_0x2d942a0/d .functor OR 1, L_0x2d93df0, L_0x2bb6670, C4<0>, C4<0>; +L_0x2d942a0 .delay 1 (30000,30000,30000) L_0x2d942a0/d; +v0x2bb6200_0 .net "a", 0 0, L_0x2d9d7b0; alias, 1 drivers +v0x2bb6350_0 .net "b", 0 0, L_0x2d93400; alias, 1 drivers +v0x2bb6410_0 .net "c1", 0 0, L_0x2d93df0; 1 drivers +v0x2bb64b0_0 .net "c2", 0 0, L_0x2bb6670; 1 drivers +v0x2bb6580_0 .net "carryin", 0 0, L_0x2d93240; alias, 1 drivers +v0x2bb6700_0 .net "carryout", 0 0, L_0x2d942a0; 1 drivers +v0x2bb67a0_0 .net "s1", 0 0, L_0x2d93d30; 1 drivers +v0x2bb6840_0 .net "sum", 0 0, L_0x2d93f50; 1 drivers +S_0x2bb5660 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2bb5410; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12aa750/d .functor XOR 1, L_0x12b3630, L_0x125b7b0, C4<0>, C4<0>; -L_0x12aa750 .delay 1 (30000,30000,30000) L_0x12aa750/d; -L_0x12aa810/d .functor AND 1, L_0x12b3630, L_0x125b7b0, C4<1>, C4<1>; -L_0x12aa810 .delay 1 (30000,30000,30000) L_0x12aa810/d; -v0x10e5200_0 .net "a", 0 0, L_0x12b3630; alias, 1 drivers -v0x10e52c0_0 .net "b", 0 0, L_0x125b7b0; alias, 1 drivers -v0x10e5380_0 .net "carryout", 0 0, L_0x12aa810; alias, 1 drivers -v0x10e5420_0 .net "sum", 0 0, L_0x12aa750; alias, 1 drivers -S_0x10e5550 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10e4d50; +L_0x2d93d30/d .functor XOR 1, L_0x2d9d7b0, L_0x2d93400, C4<0>, C4<0>; +L_0x2d93d30 .delay 1 (30000,30000,30000) L_0x2d93d30/d; +L_0x2d93df0/d .functor AND 1, L_0x2d9d7b0, L_0x2d93400, C4<1>, C4<1>; +L_0x2d93df0 .delay 1 (30000,30000,30000) L_0x2d93df0/d; +v0x2bb58c0_0 .net "a", 0 0, L_0x2d9d7b0; alias, 1 drivers +v0x2bb5980_0 .net "b", 0 0, L_0x2d93400; alias, 1 drivers +v0x2bb5a40_0 .net "carryout", 0 0, L_0x2d93df0; alias, 1 drivers +v0x2bb5ae0_0 .net "sum", 0 0, L_0x2d93d30; alias, 1 drivers +S_0x2bb5c10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2bb5410; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12aa970/d .functor XOR 1, L_0x12aa750, L_0x12a9a70, C4<0>, C4<0>; -L_0x12aa970 .delay 1 (30000,30000,30000) L_0x12aa970/d; -L_0x10e5fb0/d .functor AND 1, L_0x12aa750, L_0x12a9a70, C4<1>, C4<1>; -L_0x10e5fb0 .delay 1 (30000,30000,30000) L_0x10e5fb0/d; -v0x10e57b0_0 .net "a", 0 0, L_0x12aa750; alias, 1 drivers -v0x10e5880_0 .net "b", 0 0, L_0x12a9a70; alias, 1 drivers -v0x10e5920_0 .net "carryout", 0 0, L_0x10e5fb0; alias, 1 drivers -v0x10e59f0_0 .net "sum", 0 0, L_0x12aa970; alias, 1 drivers -S_0x10e75a0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10d7840; - .timescale -9 -12; -L_0x2b0ab3d06338 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06380 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12b36d0/d .functor OR 1, L_0x2b0ab3d06338, L_0x2b0ab3d06380, C4<0>, C4<0>; -L_0x12b36d0 .delay 1 (30000,30000,30000) L_0x12b36d0/d; -v0x10e7790_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06338; 1 drivers -v0x10e7870_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06380; 1 drivers -S_0x10e7950 .scope generate, "alu_slices[18]" "alu_slices[18]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x10e7b60 .param/l "i" 0 3 41, +C4<010010>; -S_0x10e7c20 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10e7950; +L_0x2d93f50/d .functor XOR 1, L_0x2d93d30, L_0x2d93240, C4<0>, C4<0>; +L_0x2d93f50 .delay 1 (30000,30000,30000) L_0x2d93f50/d; +L_0x2bb6670/d .functor AND 1, L_0x2d93d30, L_0x2d93240, C4<1>, C4<1>; +L_0x2bb6670 .delay 1 (30000,30000,30000) L_0x2bb6670/d; +v0x2bb5e70_0 .net "a", 0 0, L_0x2d93d30; alias, 1 drivers +v0x2bb5f40_0 .net "b", 0 0, L_0x2d93240; alias, 1 drivers +v0x2bb5fe0_0 .net "carryout", 0 0, L_0x2bb6670; alias, 1 drivers +v0x2bb60b0_0 .net "sum", 0 0, L_0x2d93f50; alias, 1 drivers +S_0x2bb88d0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2ba7f00; + .timescale -9 -12; +L_0x2ac6110ba5d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba620 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d938b0/d .functor OR 1, L_0x2ac6110ba5d8, L_0x2ac6110ba620, C4<0>, C4<0>; +L_0x2d938b0 .delay 1 (30000,30000,30000) L_0x2d938b0/d; +v0x2bb8ac0_0 .net/2u *"_s0", 0 0, L_0x2ac6110ba5d8; 1 drivers +v0x2bb8ba0_0 .net/2u *"_s2", 0 0, L_0x2ac6110ba620; 1 drivers +S_0x2bb8c80 .scope generate, "alu_slices[18]" "alu_slices[18]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2bb8e90 .param/l "i" 0 3 39, +C4<010010>; +S_0x2bb8f50 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2bb8c80; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -9768,445 +10328,476 @@ S_0x10e7c20 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10e7950; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12b39f0/d .functor NOT 1, L_0x12bd310, C4<0>, C4<0>, C4<0>; -L_0x12b39f0 .delay 1 (10000,10000,10000) L_0x12b39f0/d; -L_0x12b3b50/d .functor NOT 1, L_0x12bd470, C4<0>, C4<0>, C4<0>; -L_0x12b3b50 .delay 1 (10000,10000,10000) L_0x12b3b50/d; -L_0x12b4a90/d .functor XOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; -L_0x12b4a90 .delay 1 (30000,30000,30000) L_0x12b4a90/d; -L_0x2b0ab3d063c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06410 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12b5140/d .functor OR 1, L_0x2b0ab3d063c8, L_0x2b0ab3d06410, C4<0>, C4<0>; -L_0x12b5140 .delay 1 (30000,30000,30000) L_0x12b5140/d; -L_0x12b5340/d .functor AND 1, L_0x12bd310, L_0x12bd470, C4<1>, C4<1>; -L_0x12b5340 .delay 1 (30000,30000,30000) L_0x12b5340/d; -L_0x12b5400/d .functor NAND 1, L_0x12bd310, L_0x12bd470, C4<1>, C4<1>; -L_0x12b5400 .delay 1 (20000,20000,20000) L_0x12b5400/d; -L_0x12b5560/d .functor XOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; -L_0x12b5560 .delay 1 (20000,20000,20000) L_0x12b5560/d; -L_0x12b5a10/d .functor OR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; -L_0x12b5a10 .delay 1 (30000,30000,30000) L_0x12b5a10/d; -L_0x12bd210/d .functor NOT 1, L_0x12b93e0, C4<0>, C4<0>, C4<0>; -L_0x12bd210 .delay 1 (10000,10000,10000) L_0x12bd210/d; -v0x10f6350_0 .net "A", 0 0, L_0x12bd310; 1 drivers -v0x10f6410_0 .net "A_", 0 0, L_0x12b39f0; 1 drivers -v0x10f64d0_0 .net "B", 0 0, L_0x12bd470; 1 drivers -v0x10f65a0_0 .net "B_", 0 0, L_0x12b3b50; 1 drivers -v0x10f6640_0 .net *"_s12", 0 0, L_0x12b5140; 1 drivers -v0x10f6730_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d063c8; 1 drivers -v0x10f67f0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06410; 1 drivers -v0x10f68d0_0 .net *"_s18", 0 0, L_0x12b5340; 1 drivers -v0x10f69b0_0 .net *"_s20", 0 0, L_0x12b5400; 1 drivers -v0x10f6b20_0 .net *"_s22", 0 0, L_0x12b5560; 1 drivers -v0x10f6c00_0 .net *"_s24", 0 0, L_0x12b5a10; 1 drivers -o0x2b0ab3ccf268 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x10f6ce0_0 name=_s30 -o0x2b0ab3ccf298 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x10f6dc0_0 name=_s32 -v0x10f6ea0_0 .net *"_s8", 0 0, L_0x12b4a90; 1 drivers -v0x10f6f80_0 .net "carryin", 0 0, L_0x12b3790; 1 drivers -v0x10f7020_0 .net "carryout", 0 0, L_0x12bceb0; 1 drivers -v0x10f70c0_0 .net "carryouts", 7 0, L_0x1354cc0; 1 drivers -v0x10f7270_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10f7310_0 .net "result", 0 0, L_0x12b93e0; 1 drivers -v0x10f7400_0 .net "results", 7 0, L_0x12b57e0; 1 drivers -v0x10f7510_0 .net "zero", 0 0, L_0x12bd210; 1 drivers -LS_0x12b57e0_0_0 .concat8 [ 1 1 1 1], L_0x12ad6e0, L_0x12b45e0, L_0x12b4a90, L_0x12b5140; -LS_0x12b57e0_0_4 .concat8 [ 1 1 1 1], L_0x12b5340, L_0x12b5400, L_0x12b5560, L_0x12b5a10; -L_0x12b57e0 .concat8 [ 4 4 0 0], LS_0x12b57e0_0_0, LS_0x12b57e0_0_4; -LS_0x1354cc0_0_0 .concat [ 1 1 1 1], L_0x12b4260, L_0x12b4930, o0x2b0ab3ccf268, L_0x12b4f90; -LS_0x1354cc0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ccf298; -L_0x1354cc0 .concat [ 4 4 0 0], LS_0x1354cc0_0_0, LS_0x1354cc0_0_4; -S_0x10e7ea0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10e7c20; +L_0x2d9db70/d .functor NOT 1, L_0x2da8850, C4<0>, C4<0>, C4<0>; +L_0x2d9db70 .delay 1 (10000,10000,10000) L_0x2d9db70/d; +L_0x2d9dc80/d .functor NOT 1, L_0x2da89b0, C4<0>, C4<0>, C4<0>; +L_0x2d9dc80 .delay 1 (10000,10000,10000) L_0x2d9dc80/d; +L_0x2d9ecd0/d .functor XOR 1, L_0x2da8850, L_0x2da89b0, C4<0>, C4<0>; +L_0x2d9ecd0 .delay 1 (30000,30000,30000) L_0x2d9ecd0/d; +L_0x2ac6110ba668 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba6b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d9ed90/d .functor OR 1, L_0x2ac6110ba668, L_0x2ac6110ba6b0, C4<0>, C4<0>; +L_0x2d9ed90 .delay 1 (30000,30000,30000) L_0x2d9ed90/d; +L_0x2ac6110ba6f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba740 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d9f530/d .functor OR 1, L_0x2ac6110ba6f8, L_0x2ac6110ba740, C4<0>, C4<0>; +L_0x2d9f530 .delay 1 (30000,30000,30000) L_0x2d9f530/d; +L_0x2d9f730/d .functor AND 1, L_0x2da8850, L_0x2da89b0, C4<1>, C4<1>; +L_0x2d9f730 .delay 1 (30000,30000,30000) L_0x2d9f730/d; +L_0x2ac6110ba788 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba7d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d9f7f0/d .functor OR 1, L_0x2ac6110ba788, L_0x2ac6110ba7d0, C4<0>, C4<0>; +L_0x2d9f7f0 .delay 1 (30000,30000,30000) L_0x2d9f7f0/d; +L_0x2d9f9f0/d .functor NAND 1, L_0x2da8850, L_0x2da89b0, C4<1>, C4<1>; +L_0x2d9f9f0 .delay 1 (20000,20000,20000) L_0x2d9f9f0/d; +L_0x2ac6110ba818 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba860 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d9fb00/d .functor OR 1, L_0x2ac6110ba818, L_0x2ac6110ba860, C4<0>, C4<0>; +L_0x2d9fb00 .delay 1 (30000,30000,30000) L_0x2d9fb00/d; +L_0x2d9fc60/d .functor NOR 1, L_0x2da8850, L_0x2da89b0, C4<0>, C4<0>; +L_0x2d9fc60 .delay 1 (20000,20000,20000) L_0x2d9fc60/d; +L_0x2ac6110ba8a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba8f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d9e0f0/d .functor OR 1, L_0x2ac6110ba8a8, L_0x2ac6110ba8f0, C4<0>, C4<0>; +L_0x2d9e0f0 .delay 1 (30000,30000,30000) L_0x2d9e0f0/d; +L_0x2d409f0/d .functor OR 1, L_0x2da8850, L_0x2da89b0, C4<0>, C4<0>; +L_0x2d409f0 .delay 1 (30000,30000,30000) L_0x2d409f0/d; +L_0x2ac6110ba938 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110ba980 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2da1050/d .functor OR 1, L_0x2ac6110ba938, L_0x2ac6110ba980, C4<0>, C4<0>; +L_0x2da1050 .delay 1 (30000,30000,30000) L_0x2da1050/d; +L_0x2da8750/d .functor NOT 1, L_0x2da49b0, C4<0>, C4<0>, C4<0>; +L_0x2da8750 .delay 1 (10000,10000,10000) L_0x2da8750/d; +v0x2bc7680_0 .net "A", 0 0, L_0x2da8850; 1 drivers +v0x2bc7740_0 .net "A_", 0 0, L_0x2d9db70; 1 drivers +v0x2bc7800_0 .net "B", 0 0, L_0x2da89b0; 1 drivers +v0x2bc78d0_0 .net "B_", 0 0, L_0x2d9dc80; 1 drivers +v0x2bc7970_0 .net *"_s11", 0 0, L_0x2d9ed90; 1 drivers +v0x2bc7a60_0 .net/2s *"_s13", 0 0, L_0x2ac6110ba668; 1 drivers +v0x2bc7b20_0 .net/2s *"_s15", 0 0, L_0x2ac6110ba6b0; 1 drivers +v0x2bc7c00_0 .net *"_s19", 0 0, L_0x2d9f530; 1 drivers +v0x2bc7ce0_0 .net/2s *"_s21", 0 0, L_0x2ac6110ba6f8; 1 drivers +v0x2bc7e50_0 .net/2s *"_s23", 0 0, L_0x2ac6110ba740; 1 drivers +v0x2bc7f30_0 .net *"_s25", 0 0, L_0x2d9f730; 1 drivers +v0x2bc8010_0 .net *"_s28", 0 0, L_0x2d9f7f0; 1 drivers +v0x2bc80f0_0 .net/2s *"_s30", 0 0, L_0x2ac6110ba788; 1 drivers +v0x2bc81d0_0 .net/2s *"_s32", 0 0, L_0x2ac6110ba7d0; 1 drivers +v0x2bc82b0_0 .net *"_s34", 0 0, L_0x2d9f9f0; 1 drivers +v0x2bc8390_0 .net *"_s37", 0 0, L_0x2d9fb00; 1 drivers +v0x2bc8470_0 .net/2s *"_s39", 0 0, L_0x2ac6110ba818; 1 drivers +v0x2bc8620_0 .net/2s *"_s41", 0 0, L_0x2ac6110ba860; 1 drivers +v0x2bc86c0_0 .net *"_s43", 0 0, L_0x2d9fc60; 1 drivers +v0x2bc87a0_0 .net *"_s46", 0 0, L_0x2d9e0f0; 1 drivers +v0x2bc8880_0 .net/2s *"_s48", 0 0, L_0x2ac6110ba8a8; 1 drivers +v0x2bc8960_0 .net/2s *"_s50", 0 0, L_0x2ac6110ba8f0; 1 drivers +v0x2bc8a40_0 .net *"_s52", 0 0, L_0x2d409f0; 1 drivers +v0x2bc8b20_0 .net *"_s56", 0 0, L_0x2da1050; 1 drivers +v0x2bc8c00_0 .net/2s *"_s59", 0 0, L_0x2ac6110ba938; 1 drivers +v0x2bc8ce0_0 .net/2s *"_s61", 0 0, L_0x2ac6110ba980; 1 drivers +v0x2bc8dc0_0 .net *"_s8", 0 0, L_0x2d9ecd0; 1 drivers +v0x2bc8ea0_0 .net "carryin", 0 0, L_0x2d9d910; 1 drivers +v0x2bc8f40_0 .net "carryout", 0 0, L_0x2da83f0; 1 drivers +v0x2bc8fe0_0 .net "carryouts", 7 0, L_0x2d40e40; 1 drivers +v0x2bc90f0_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bc91b0_0 .net "result", 0 0, L_0x2da49b0; 1 drivers +v0x2bc92a0_0 .net "results", 7 0, L_0x2d40ab0; 1 drivers +v0x2bc8580_0 .net "zero", 0 0, L_0x2da8750; 1 drivers +LS_0x2d40ab0_0_0 .concat8 [ 1 1 1 1], L_0x2d9e1a0, L_0x2d9e7d0, L_0x2d9ecd0, L_0x2d9f530; +LS_0x2d40ab0_0_4 .concat8 [ 1 1 1 1], L_0x2d9f730, L_0x2d9f9f0, L_0x2d9fc60, L_0x2d409f0; +L_0x2d40ab0 .concat8 [ 4 4 0 0], LS_0x2d40ab0_0_0, LS_0x2d40ab0_0_4; +LS_0x2d40e40_0_0 .concat8 [ 1 1 1 1], L_0x2d9e450, L_0x2d9eb70, L_0x2d9ed90, L_0x2d9f380; +LS_0x2d40e40_0_4 .concat8 [ 1 1 1 1], L_0x2d9f7f0, L_0x2d9fb00, L_0x2d9e0f0, L_0x2da1050; +L_0x2d40e40 .concat8 [ 4 4 0 0], LS_0x2d40e40_0_0, LS_0x2d40e40_0_4; +S_0x2bb91d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2bb8f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12b4260/d .functor OR 1, L_0x12b3e00, L_0x12b4100, C4<0>, C4<0>; -L_0x12b4260 .delay 1 (30000,30000,30000) L_0x12b4260/d; -v0x10e8ce0_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers -v0x10e8da0_0 .net "b", 0 0, L_0x12bd470; alias, 1 drivers -v0x10e8e70_0 .net "c1", 0 0, L_0x12b3e00; 1 drivers -v0x10e8f70_0 .net "c2", 0 0, L_0x12b4100; 1 drivers -v0x10e9040_0 .net "carryin", 0 0, L_0x12b3790; alias, 1 drivers -v0x10e9130_0 .net "carryout", 0 0, L_0x12b4260; 1 drivers -v0x10e91d0_0 .net "s1", 0 0, L_0x12b3d40; 1 drivers -v0x10e92c0_0 .net "sum", 0 0, L_0x12ad6e0; 1 drivers -S_0x10e80f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10e7ea0; +L_0x2d9e450/d .functor OR 1, L_0x2d9df30, L_0x2d9e2f0, C4<0>, C4<0>; +L_0x2d9e450 .delay 1 (30000,30000,30000) L_0x2d9e450/d; +v0x2bba000_0 .net "a", 0 0, L_0x2da8850; alias, 1 drivers +v0x2bba0c0_0 .net "b", 0 0, L_0x2da89b0; alias, 1 drivers +v0x2bba190_0 .net "c1", 0 0, L_0x2d9df30; 1 drivers +v0x2bba290_0 .net "c2", 0 0, L_0x2d9e2f0; 1 drivers +v0x2bba360_0 .net "carryin", 0 0, L_0x2d9d910; alias, 1 drivers +v0x2bba450_0 .net "carryout", 0 0, L_0x2d9e450; 1 drivers +v0x2bba4f0_0 .net "s1", 0 0, L_0x2d9de70; 1 drivers +v0x2bba5e0_0 .net "sum", 0 0, L_0x2d9e1a0; 1 drivers +S_0x2bb9440 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2bb91d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12b3d40/d .functor XOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; -L_0x12b3d40 .delay 1 (30000,30000,30000) L_0x12b3d40/d; -L_0x12b3e00/d .functor AND 1, L_0x12bd310, L_0x12bd470, C4<1>, C4<1>; -L_0x12b3e00 .delay 1 (30000,30000,30000) L_0x12b3e00/d; -v0x10e8330_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers -v0x10e83f0_0 .net "b", 0 0, L_0x12bd470; alias, 1 drivers -v0x10e84d0_0 .net "carryout", 0 0, L_0x12b3e00; alias, 1 drivers -v0x10e8570_0 .net "sum", 0 0, L_0x12b3d40; alias, 1 drivers -S_0x10e86e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10e7ea0; +L_0x2d9de70/d .functor XOR 1, L_0x2da8850, L_0x2da89b0, C4<0>, C4<0>; +L_0x2d9de70 .delay 1 (30000,30000,30000) L_0x2d9de70/d; +L_0x2d9df30/d .functor AND 1, L_0x2da8850, L_0x2da89b0, C4<1>, C4<1>; +L_0x2d9df30 .delay 1 (30000,30000,30000) L_0x2d9df30/d; +v0x2bb96a0_0 .net "a", 0 0, L_0x2da8850; alias, 1 drivers +v0x2bb9780_0 .net "b", 0 0, L_0x2da89b0; alias, 1 drivers +v0x2bb9840_0 .net "carryout", 0 0, L_0x2d9df30; alias, 1 drivers +v0x2bb98e0_0 .net "sum", 0 0, L_0x2d9de70; alias, 1 drivers +S_0x2bb9a20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2bb91d0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12ad6e0/d .functor XOR 1, L_0x12b3d40, L_0x12b3790, C4<0>, C4<0>; -L_0x12ad6e0 .delay 1 (30000,30000,30000) L_0x12ad6e0/d; -L_0x12b4100/d .functor AND 1, L_0x12b3d40, L_0x12b3790, C4<1>, C4<1>; -L_0x12b4100 .delay 1 (30000,30000,30000) L_0x12b4100/d; -v0x10e8940_0 .net "a", 0 0, L_0x12b3d40; alias, 1 drivers -v0x10e8a00_0 .net "b", 0 0, L_0x12b3790; alias, 1 drivers -v0x10e8aa0_0 .net "carryout", 0 0, L_0x12b4100; alias, 1 drivers -v0x10e8b70_0 .net "sum", 0 0, L_0x12ad6e0; alias, 1 drivers -S_0x10e9390 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10e7c20; +L_0x2d9e1a0/d .functor XOR 1, L_0x2d9de70, L_0x2d9d910, C4<0>, C4<0>; +L_0x2d9e1a0 .delay 1 (30000,30000,30000) L_0x2d9e1a0/d; +L_0x2d9e2f0/d .functor AND 1, L_0x2d9de70, L_0x2d9d910, C4<1>, C4<1>; +L_0x2d9e2f0 .delay 1 (30000,30000,30000) L_0x2d9e2f0/d; +v0x2bb9c80_0 .net "a", 0 0, L_0x2d9de70; alias, 1 drivers +v0x2bb9d20_0 .net "b", 0 0, L_0x2d9d910; alias, 1 drivers +v0x2bb9dc0_0 .net "carryout", 0 0, L_0x2d9e2f0; alias, 1 drivers +v0x2bb9e90_0 .net "sum", 0 0, L_0x2d9e1a0; alias, 1 drivers +S_0x2bba6b0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2bb8f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10ee770_0 .net "ands", 7 0, L_0x12baeb0; 1 drivers -v0x10ee880_0 .net "in", 7 0, L_0x1354cc0; alias, 1 drivers -v0x10ee940_0 .net "out", 0 0, L_0x12bceb0; alias, 1 drivers -v0x10eea10_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10e95d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10e9390; +v0x2bbfaa0_0 .net "ands", 7 0, L_0x2da63f0; 1 drivers +v0x2bbfbb0_0 .net "in", 7 0, L_0x2d40e40; alias, 1 drivers +v0x2bbfc70_0 .net "out", 0 0, L_0x2da83f0; alias, 1 drivers +v0x2bbfd40_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2bba8d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2bba6b0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10ebd00_0 .net "A", 7 0, L_0x1354cc0; alias, 1 drivers -v0x10ebe00_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10ebec0_0 .net *"_s0", 0 0, L_0x12b9740; 1 drivers -v0x10ebf80_0 .net *"_s12", 0 0, L_0x12ba0e0; 1 drivers -v0x10ec060_0 .net *"_s16", 0 0, L_0x12ba440; 1 drivers -v0x10ec190_0 .net *"_s20", 0 0, L_0x12ba780; 1 drivers -v0x10ec270_0 .net *"_s24", 0 0, L_0x12baba0; 1 drivers -v0x10ec350_0 .net *"_s28", 0 0, L_0x12bab30; 1 drivers -v0x10ec430_0 .net *"_s4", 0 0, L_0x12b9a50; 1 drivers -v0x10ec5a0_0 .net *"_s8", 0 0, L_0x12b9da0; 1 drivers -v0x10ec680_0 .net "out", 7 0, L_0x12baeb0; alias, 1 drivers -L_0x12b9800 .part L_0x1354cc0, 0, 1; -L_0x12b9960 .part v0x12010b0_0, 0, 1; -L_0x12b9b10 .part L_0x1354cc0, 1, 1; -L_0x12b9d00 .part v0x12010b0_0, 1, 1; -L_0x12b9e90 .part L_0x1354cc0, 2, 1; -L_0x12b9ff0 .part v0x12010b0_0, 2, 1; -L_0x12ba1a0 .part L_0x1354cc0, 3, 1; -L_0x12ba300 .part v0x12010b0_0, 3, 1; -L_0x12ba530 .part L_0x1354cc0, 4, 1; -L_0x12ba690 .part v0x12010b0_0, 4, 1; -L_0x12ba820 .part L_0x1354cc0, 5, 1; -L_0x12baa90 .part v0x12010b0_0, 5, 1; -L_0x12bac60 .part L_0x1354cc0, 6, 1; -L_0x12badc0 .part v0x12010b0_0, 6, 1; -LS_0x12baeb0_0_0 .concat8 [ 1 1 1 1], L_0x12b9740, L_0x12b9a50, L_0x12b9da0, L_0x12ba0e0; -LS_0x12baeb0_0_4 .concat8 [ 1 1 1 1], L_0x12ba440, L_0x12ba780, L_0x12baba0, L_0x12bab30; -L_0x12baeb0 .concat8 [ 4 4 0 0], LS_0x12baeb0_0_0, LS_0x12baeb0_0_4; -L_0x12bb270 .part L_0x1354cc0, 7, 1; -L_0x12bb460 .part v0x12010b0_0, 7, 1; -S_0x10e9830 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10e9a40 .param/l "i" 0 4 54, +C4<00>; -L_0x12b9740/d .functor AND 1, L_0x12b9800, L_0x12b9960, C4<1>, C4<1>; -L_0x12b9740 .delay 1 (30000,30000,30000) L_0x12b9740/d; -v0x10e9b20_0 .net *"_s0", 0 0, L_0x12b9800; 1 drivers -v0x10e9c00_0 .net *"_s1", 0 0, L_0x12b9960; 1 drivers -S_0x10e9ce0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10e9ef0 .param/l "i" 0 4 54, +C4<01>; -L_0x12b9a50/d .functor AND 1, L_0x12b9b10, L_0x12b9d00, C4<1>, C4<1>; -L_0x12b9a50 .delay 1 (30000,30000,30000) L_0x12b9a50/d; -v0x10e9fb0_0 .net *"_s0", 0 0, L_0x12b9b10; 1 drivers -v0x10ea090_0 .net *"_s1", 0 0, L_0x12b9d00; 1 drivers -S_0x10ea170 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10ea380 .param/l "i" 0 4 54, +C4<010>; -L_0x12b9da0/d .functor AND 1, L_0x12b9e90, L_0x12b9ff0, C4<1>, C4<1>; -L_0x12b9da0 .delay 1 (30000,30000,30000) L_0x12b9da0/d; -v0x10ea420_0 .net *"_s0", 0 0, L_0x12b9e90; 1 drivers -v0x10ea500_0 .net *"_s1", 0 0, L_0x12b9ff0; 1 drivers -S_0x10ea5e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10ea7f0 .param/l "i" 0 4 54, +C4<011>; -L_0x12ba0e0/d .functor AND 1, L_0x12ba1a0, L_0x12ba300, C4<1>, C4<1>; -L_0x12ba0e0 .delay 1 (30000,30000,30000) L_0x12ba0e0/d; -v0x10ea8b0_0 .net *"_s0", 0 0, L_0x12ba1a0; 1 drivers -v0x10ea990_0 .net *"_s1", 0 0, L_0x12ba300; 1 drivers -S_0x10eaa70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10eacd0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12ba440/d .functor AND 1, L_0x12ba530, L_0x12ba690, C4<1>, C4<1>; -L_0x12ba440 .delay 1 (30000,30000,30000) L_0x12ba440/d; -v0x10ead90_0 .net *"_s0", 0 0, L_0x12ba530; 1 drivers -v0x10eae70_0 .net *"_s1", 0 0, L_0x12ba690; 1 drivers -S_0x10eaf50 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10eb160 .param/l "i" 0 4 54, +C4<0101>; -L_0x12ba780/d .functor AND 1, L_0x12ba820, L_0x12baa90, C4<1>, C4<1>; -L_0x12ba780 .delay 1 (30000,30000,30000) L_0x12ba780/d; -v0x10eb220_0 .net *"_s0", 0 0, L_0x12ba820; 1 drivers -v0x10eb300_0 .net *"_s1", 0 0, L_0x12baa90; 1 drivers -S_0x10eb3e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10eb5f0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12baba0/d .functor AND 1, L_0x12bac60, L_0x12badc0, C4<1>, C4<1>; -L_0x12baba0 .delay 1 (30000,30000,30000) L_0x12baba0/d; -v0x10eb6b0_0 .net *"_s0", 0 0, L_0x12bac60; 1 drivers -v0x10eb790_0 .net *"_s1", 0 0, L_0x12badc0; 1 drivers -S_0x10eb870 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10e95d0; - .timescale -9 -12; -P_0x10eba80 .param/l "i" 0 4 54, +C4<0111>; -L_0x12bab30/d .functor AND 1, L_0x12bb270, L_0x12bb460, C4<1>, C4<1>; -L_0x12bab30 .delay 1 (30000,30000,30000) L_0x12bab30/d; -v0x10ebb40_0 .net *"_s0", 0 0, L_0x12bb270; 1 drivers -v0x10ebc20_0 .net *"_s1", 0 0, L_0x12bb460; 1 drivers -S_0x10ec7e0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10e9390; +v0x2bbd000_0 .net "A", 7 0, L_0x2d40e40; alias, 1 drivers +v0x2bbd100_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bbd1c0_0 .net *"_s0", 0 0, L_0x2da4d10; 1 drivers +v0x2bbd280_0 .net *"_s12", 0 0, L_0x2da5680; 1 drivers +v0x2bbd360_0 .net *"_s16", 0 0, L_0x2da59e0; 1 drivers +v0x2bbd490_0 .net *"_s20", 0 0, L_0x2da5db0; 1 drivers +v0x2bbd570_0 .net *"_s24", 0 0, L_0x2da60e0; 1 drivers +v0x2bbd650_0 .net *"_s28", 0 0, L_0x2da6070; 1 drivers +v0x2bbd730_0 .net *"_s4", 0 0, L_0x2da5060; 1 drivers +v0x2bbd8a0_0 .net *"_s8", 0 0, L_0x2da5370; 1 drivers +v0x2bbd980_0 .net "out", 7 0, L_0x2da63f0; alias, 1 drivers +L_0x2da4dd0 .part L_0x2d40e40, 0, 1; +L_0x2da4fc0 .part v0x2cdd2e0_0, 0, 1; +L_0x2da5120 .part L_0x2d40e40, 1, 1; +L_0x2da5280 .part v0x2cdd2e0_0, 1, 1; +L_0x2da5430 .part L_0x2d40e40, 2, 1; +L_0x2da5590 .part v0x2cdd2e0_0, 2, 1; +L_0x2da5740 .part L_0x2d40e40, 3, 1; +L_0x2da58a0 .part v0x2cdd2e0_0, 3, 1; +L_0x2da5aa0 .part L_0x2d40e40, 4, 1; +L_0x2da5d10 .part v0x2cdd2e0_0, 4, 1; +L_0x2da5e20 .part L_0x2d40e40, 5, 1; +L_0x2da5f80 .part v0x2cdd2e0_0, 5, 1; +L_0x2da61a0 .part L_0x2d40e40, 6, 1; +L_0x2da6300 .part v0x2cdd2e0_0, 6, 1; +LS_0x2da63f0_0_0 .concat8 [ 1 1 1 1], L_0x2da4d10, L_0x2da5060, L_0x2da5370, L_0x2da5680; +LS_0x2da63f0_0_4 .concat8 [ 1 1 1 1], L_0x2da59e0, L_0x2da5db0, L_0x2da60e0, L_0x2da6070; +L_0x2da63f0 .concat8 [ 4 4 0 0], LS_0x2da63f0_0_0, LS_0x2da63f0_0_4; +L_0x2da67b0 .part L_0x2d40e40, 7, 1; +L_0x2da69a0 .part v0x2cdd2e0_0, 7, 1; +S_0x2bbab30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbad40 .param/l "i" 0 4 54, +C4<00>; +L_0x2da4d10/d .functor AND 1, L_0x2da4dd0, L_0x2da4fc0, C4<1>, C4<1>; +L_0x2da4d10 .delay 1 (30000,30000,30000) L_0x2da4d10/d; +v0x2bbae20_0 .net *"_s0", 0 0, L_0x2da4dd0; 1 drivers +v0x2bbaf00_0 .net *"_s1", 0 0, L_0x2da4fc0; 1 drivers +S_0x2bbafe0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbb1f0 .param/l "i" 0 4 54, +C4<01>; +L_0x2da5060/d .functor AND 1, L_0x2da5120, L_0x2da5280, C4<1>, C4<1>; +L_0x2da5060 .delay 1 (30000,30000,30000) L_0x2da5060/d; +v0x2bbb2b0_0 .net *"_s0", 0 0, L_0x2da5120; 1 drivers +v0x2bbb390_0 .net *"_s1", 0 0, L_0x2da5280; 1 drivers +S_0x2bbb470 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbb680 .param/l "i" 0 4 54, +C4<010>; +L_0x2da5370/d .functor AND 1, L_0x2da5430, L_0x2da5590, C4<1>, C4<1>; +L_0x2da5370 .delay 1 (30000,30000,30000) L_0x2da5370/d; +v0x2bbb720_0 .net *"_s0", 0 0, L_0x2da5430; 1 drivers +v0x2bbb800_0 .net *"_s1", 0 0, L_0x2da5590; 1 drivers +S_0x2bbb8e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbbaf0 .param/l "i" 0 4 54, +C4<011>; +L_0x2da5680/d .functor AND 1, L_0x2da5740, L_0x2da58a0, C4<1>, C4<1>; +L_0x2da5680 .delay 1 (30000,30000,30000) L_0x2da5680/d; +v0x2bbbbb0_0 .net *"_s0", 0 0, L_0x2da5740; 1 drivers +v0x2bbbc90_0 .net *"_s1", 0 0, L_0x2da58a0; 1 drivers +S_0x2bbbd70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbbfd0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2da59e0/d .functor AND 1, L_0x2da5aa0, L_0x2da5d10, C4<1>, C4<1>; +L_0x2da59e0 .delay 1 (30000,30000,30000) L_0x2da59e0/d; +v0x2bbc090_0 .net *"_s0", 0 0, L_0x2da5aa0; 1 drivers +v0x2bbc170_0 .net *"_s1", 0 0, L_0x2da5d10; 1 drivers +S_0x2bbc250 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbc460 .param/l "i" 0 4 54, +C4<0101>; +L_0x2da5db0/d .functor AND 1, L_0x2da5e20, L_0x2da5f80, C4<1>, C4<1>; +L_0x2da5db0 .delay 1 (30000,30000,30000) L_0x2da5db0/d; +v0x2bbc520_0 .net *"_s0", 0 0, L_0x2da5e20; 1 drivers +v0x2bbc600_0 .net *"_s1", 0 0, L_0x2da5f80; 1 drivers +S_0x2bbc6e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbc8f0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2da60e0/d .functor AND 1, L_0x2da61a0, L_0x2da6300, C4<1>, C4<1>; +L_0x2da60e0 .delay 1 (30000,30000,30000) L_0x2da60e0/d; +v0x2bbc9b0_0 .net *"_s0", 0 0, L_0x2da61a0; 1 drivers +v0x2bbca90_0 .net *"_s1", 0 0, L_0x2da6300; 1 drivers +S_0x2bbcb70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2bba8d0; + .timescale -9 -12; +P_0x2bbcd80 .param/l "i" 0 4 54, +C4<0111>; +L_0x2da6070/d .functor AND 1, L_0x2da67b0, L_0x2da69a0, C4<1>, C4<1>; +L_0x2da6070 .delay 1 (30000,30000,30000) L_0x2da6070/d; +v0x2bbce40_0 .net *"_s0", 0 0, L_0x2da67b0; 1 drivers +v0x2bbcf20_0 .net *"_s1", 0 0, L_0x2da69a0; 1 drivers +S_0x2bbdae0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2bba6b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12bceb0/d .functor OR 1, L_0x12bcf70, L_0x12bd120, C4<0>, C4<0>; -L_0x12bceb0 .delay 1 (30000,30000,30000) L_0x12bceb0/d; -v0x10ee330_0 .net *"_s10", 0 0, L_0x12bcf70; 1 drivers -v0x10ee410_0 .net *"_s12", 0 0, L_0x12bd120; 1 drivers -v0x10ee4f0_0 .net "in", 7 0, L_0x12baeb0; alias, 1 drivers -v0x10ee590_0 .net "ors", 1 0, L_0x12bccd0; 1 drivers -v0x10ee650_0 .net "out", 0 0, L_0x12bceb0; alias, 1 drivers -L_0x12bc0a0 .part L_0x12baeb0, 0, 4; -L_0x12bccd0 .concat8 [ 1 1 0 0], L_0x12bbd90, L_0x12bc9c0; -L_0x12bce10 .part L_0x12baeb0, 4, 4; -L_0x12bcf70 .part L_0x12bccd0, 0, 1; -L_0x12bd120 .part L_0x12bccd0, 1, 1; -S_0x10ec9a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10ec7e0; +L_0x2da83f0/d .functor OR 1, L_0x2da84b0, L_0x2da8660, C4<0>, C4<0>; +L_0x2da83f0 .delay 1 (30000,30000,30000) L_0x2da83f0/d; +v0x2bbf630_0 .net *"_s10", 0 0, L_0x2da84b0; 1 drivers +v0x2bbf710_0 .net *"_s12", 0 0, L_0x2da8660; 1 drivers +v0x2bbf7f0_0 .net "in", 7 0, L_0x2da63f0; alias, 1 drivers +v0x2bbf8c0_0 .net "ors", 1 0, L_0x2da8210; 1 drivers +v0x2bbf980_0 .net "out", 0 0, L_0x2da83f0; alias, 1 drivers +L_0x2da75e0 .part L_0x2da63f0, 0, 4; +L_0x2da8210 .concat8 [ 1 1 0 0], L_0x2da72d0, L_0x2da7f00; +L_0x2da8350 .part L_0x2da63f0, 4, 4; +L_0x2da84b0 .part L_0x2da8210, 0, 1; +L_0x2da8660 .part L_0x2da8210, 1, 1; +S_0x2bbdca0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bbdae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12bb550/d .functor OR 1, L_0x12bb610, L_0x12bb770, C4<0>, C4<0>; -L_0x12bb550 .delay 1 (30000,30000,30000) L_0x12bb550/d; -L_0x12bb9a0/d .functor OR 1, L_0x12bbab0, L_0x12bbc10, C4<0>, C4<0>; -L_0x12bb9a0 .delay 1 (30000,30000,30000) L_0x12bb9a0/d; -L_0x12bbd90/d .functor OR 1, L_0x12bbe00, L_0x12bbfb0, C4<0>, C4<0>; -L_0x12bbd90 .delay 1 (30000,30000,30000) L_0x12bbd90/d; -v0x10ecbf0_0 .net *"_s0", 0 0, L_0x12bb550; 1 drivers -v0x10eccf0_0 .net *"_s10", 0 0, L_0x12bbab0; 1 drivers -v0x10ecdd0_0 .net *"_s12", 0 0, L_0x12bbc10; 1 drivers -v0x10ece90_0 .net *"_s14", 0 0, L_0x12bbe00; 1 drivers -v0x10ecf70_0 .net *"_s16", 0 0, L_0x12bbfb0; 1 drivers -v0x10ed0a0_0 .net *"_s3", 0 0, L_0x12bb610; 1 drivers -v0x10ed180_0 .net *"_s5", 0 0, L_0x12bb770; 1 drivers -v0x10ed260_0 .net *"_s6", 0 0, L_0x12bb9a0; 1 drivers -v0x10ed340_0 .net "in", 3 0, L_0x12bc0a0; 1 drivers -v0x10ed4b0_0 .net "ors", 1 0, L_0x12bb8b0; 1 drivers -v0x10ed590_0 .net "out", 0 0, L_0x12bbd90; 1 drivers -L_0x12bb610 .part L_0x12bc0a0, 0, 1; -L_0x12bb770 .part L_0x12bc0a0, 1, 1; -L_0x12bb8b0 .concat8 [ 1 1 0 0], L_0x12bb550, L_0x12bb9a0; -L_0x12bbab0 .part L_0x12bc0a0, 2, 1; -L_0x12bbc10 .part L_0x12bc0a0, 3, 1; -L_0x12bbe00 .part L_0x12bb8b0, 0, 1; -L_0x12bbfb0 .part L_0x12bb8b0, 1, 1; -S_0x10ed6b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10ec7e0; +L_0x2da6a90/d .functor OR 1, L_0x2da6b50, L_0x2da6cb0, C4<0>, C4<0>; +L_0x2da6a90 .delay 1 (30000,30000,30000) L_0x2da6a90/d; +L_0x2da6ee0/d .functor OR 1, L_0x2da6ff0, L_0x2da7150, C4<0>, C4<0>; +L_0x2da6ee0 .delay 1 (30000,30000,30000) L_0x2da6ee0/d; +L_0x2da72d0/d .functor OR 1, L_0x2da7340, L_0x2da74f0, C4<0>, C4<0>; +L_0x2da72d0 .delay 1 (30000,30000,30000) L_0x2da72d0/d; +v0x2bbdef0_0 .net *"_s0", 0 0, L_0x2da6a90; 1 drivers +v0x2bbdff0_0 .net *"_s10", 0 0, L_0x2da6ff0; 1 drivers +v0x2bbe0d0_0 .net *"_s12", 0 0, L_0x2da7150; 1 drivers +v0x2bbe190_0 .net *"_s14", 0 0, L_0x2da7340; 1 drivers +v0x2bbe270_0 .net *"_s16", 0 0, L_0x2da74f0; 1 drivers +v0x2bbe3a0_0 .net *"_s3", 0 0, L_0x2da6b50; 1 drivers +v0x2bbe480_0 .net *"_s5", 0 0, L_0x2da6cb0; 1 drivers +v0x2bbe560_0 .net *"_s6", 0 0, L_0x2da6ee0; 1 drivers +v0x2bbe640_0 .net "in", 3 0, L_0x2da75e0; 1 drivers +v0x2bbe7b0_0 .net "ors", 1 0, L_0x2da6df0; 1 drivers +v0x2bbe890_0 .net "out", 0 0, L_0x2da72d0; 1 drivers +L_0x2da6b50 .part L_0x2da75e0, 0, 1; +L_0x2da6cb0 .part L_0x2da75e0, 1, 1; +L_0x2da6df0 .concat8 [ 1 1 0 0], L_0x2da6a90, L_0x2da6ee0; +L_0x2da6ff0 .part L_0x2da75e0, 2, 1; +L_0x2da7150 .part L_0x2da75e0, 3, 1; +L_0x2da7340 .part L_0x2da6df0, 0, 1; +L_0x2da74f0 .part L_0x2da6df0, 1, 1; +S_0x2bbe9b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bbdae0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12bc1d0/d .functor OR 1, L_0x12bc240, L_0x12bc3a0, C4<0>, C4<0>; -L_0x12bc1d0 .delay 1 (30000,30000,30000) L_0x12bc1d0/d; -L_0x12bc5d0/d .functor OR 1, L_0x12bc6e0, L_0x12bc840, C4<0>, C4<0>; -L_0x12bc5d0 .delay 1 (30000,30000,30000) L_0x12bc5d0/d; -L_0x12bc9c0/d .functor OR 1, L_0x12bca30, L_0x12bcbe0, C4<0>, C4<0>; -L_0x12bc9c0 .delay 1 (30000,30000,30000) L_0x12bc9c0/d; -v0x10ed870_0 .net *"_s0", 0 0, L_0x12bc1d0; 1 drivers -v0x10ed970_0 .net *"_s10", 0 0, L_0x12bc6e0; 1 drivers -v0x10eda50_0 .net *"_s12", 0 0, L_0x12bc840; 1 drivers -v0x10edb10_0 .net *"_s14", 0 0, L_0x12bca30; 1 drivers -v0x10edbf0_0 .net *"_s16", 0 0, L_0x12bcbe0; 1 drivers -v0x10edd20_0 .net *"_s3", 0 0, L_0x12bc240; 1 drivers -v0x10ede00_0 .net *"_s5", 0 0, L_0x12bc3a0; 1 drivers -v0x10edee0_0 .net *"_s6", 0 0, L_0x12bc5d0; 1 drivers -v0x10edfc0_0 .net "in", 3 0, L_0x12bce10; 1 drivers -v0x10ee130_0 .net "ors", 1 0, L_0x12bc4e0; 1 drivers -v0x10ee210_0 .net "out", 0 0, L_0x12bc9c0; 1 drivers -L_0x12bc240 .part L_0x12bce10, 0, 1; -L_0x12bc3a0 .part L_0x12bce10, 1, 1; -L_0x12bc4e0 .concat8 [ 1 1 0 0], L_0x12bc1d0, L_0x12bc5d0; -L_0x12bc6e0 .part L_0x12bce10, 2, 1; -L_0x12bc840 .part L_0x12bce10, 3, 1; -L_0x12bca30 .part L_0x12bc4e0, 0, 1; -L_0x12bcbe0 .part L_0x12bc4e0, 1, 1; -S_0x10eeaf0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10e7c20; +L_0x2da7710/d .functor OR 1, L_0x2da7780, L_0x2da78e0, C4<0>, C4<0>; +L_0x2da7710 .delay 1 (30000,30000,30000) L_0x2da7710/d; +L_0x2da7b10/d .functor OR 1, L_0x2da7c20, L_0x2da7d80, C4<0>, C4<0>; +L_0x2da7b10 .delay 1 (30000,30000,30000) L_0x2da7b10/d; +L_0x2da7f00/d .functor OR 1, L_0x2da7f70, L_0x2da8120, C4<0>, C4<0>; +L_0x2da7f00 .delay 1 (30000,30000,30000) L_0x2da7f00/d; +v0x2bbeb70_0 .net *"_s0", 0 0, L_0x2da7710; 1 drivers +v0x2bbec70_0 .net *"_s10", 0 0, L_0x2da7c20; 1 drivers +v0x2bbed50_0 .net *"_s12", 0 0, L_0x2da7d80; 1 drivers +v0x2bbee10_0 .net *"_s14", 0 0, L_0x2da7f70; 1 drivers +v0x2bbeef0_0 .net *"_s16", 0 0, L_0x2da8120; 1 drivers +v0x2bbf020_0 .net *"_s3", 0 0, L_0x2da7780; 1 drivers +v0x2bbf100_0 .net *"_s5", 0 0, L_0x2da78e0; 1 drivers +v0x2bbf1e0_0 .net *"_s6", 0 0, L_0x2da7b10; 1 drivers +v0x2bbf2c0_0 .net "in", 3 0, L_0x2da8350; 1 drivers +v0x2bbf430_0 .net "ors", 1 0, L_0x2da7a20; 1 drivers +v0x2bbf510_0 .net "out", 0 0, L_0x2da7f00; 1 drivers +L_0x2da7780 .part L_0x2da8350, 0, 1; +L_0x2da78e0 .part L_0x2da8350, 1, 1; +L_0x2da7a20 .concat8 [ 1 1 0 0], L_0x2da7710, L_0x2da7b10; +L_0x2da7c20 .part L_0x2da8350, 2, 1; +L_0x2da7d80 .part L_0x2da8350, 3, 1; +L_0x2da7f70 .part L_0x2da7a20, 0, 1; +L_0x2da8120 .part L_0x2da7a20, 1, 1; +S_0x2bbfe20 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2bb8f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10f3f20_0 .net "ands", 7 0, L_0x12b7380; 1 drivers -v0x10f4030_0 .net "in", 7 0, L_0x12b57e0; alias, 1 drivers -v0x10f40f0_0 .net "out", 0 0, L_0x12b93e0; alias, 1 drivers -v0x10f41c0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10eed40 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10eeaf0; +v0x2bc5250_0 .net "ands", 7 0, L_0x2da29b0; 1 drivers +v0x2bc5360_0 .net "in", 7 0, L_0x2d40ab0; alias, 1 drivers +v0x2bc5420_0 .net "out", 0 0, L_0x2da49b0; alias, 1 drivers +v0x2bc54f0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2bc0070 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2bbfe20; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10f1480_0 .net "A", 7 0, L_0x12b57e0; alias, 1 drivers -v0x10f1580_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10f1640_0 .net *"_s0", 0 0, L_0x12b5b70; 1 drivers -v0x10f1700_0 .net *"_s12", 0 0, L_0x12b6530; 1 drivers -v0x10f17e0_0 .net *"_s16", 0 0, L_0x12b6890; 1 drivers -v0x10f1910_0 .net *"_s20", 0 0, L_0x12b6cc0; 1 drivers -v0x10f19f0_0 .net *"_s24", 0 0, L_0x12b6ff0; 1 drivers -v0x10f1ad0_0 .net *"_s28", 0 0, L_0x12b6f80; 1 drivers -v0x10f1bb0_0 .net *"_s4", 0 0, L_0x12b5f10; 1 drivers -v0x10f1d20_0 .net *"_s8", 0 0, L_0x12b6220; 1 drivers -v0x10f1e00_0 .net "out", 7 0, L_0x12b7380; alias, 1 drivers -L_0x12b5c80 .part L_0x12b57e0, 0, 1; -L_0x12b5e70 .part v0x12010b0_0, 0, 1; -L_0x12b5fd0 .part L_0x12b57e0, 1, 1; -L_0x12b6130 .part v0x12010b0_0, 1, 1; -L_0x12b62e0 .part L_0x12b57e0, 2, 1; -L_0x12b6440 .part v0x12010b0_0, 2, 1; -L_0x12b65f0 .part L_0x12b57e0, 3, 1; -L_0x12b6750 .part v0x12010b0_0, 3, 1; -L_0x12b6950 .part L_0x12b57e0, 4, 1; -L_0x12b6bc0 .part v0x12010b0_0, 4, 1; -L_0x12b6d30 .part L_0x12b57e0, 5, 1; -L_0x12b6e90 .part v0x12010b0_0, 5, 1; -L_0x12b70b0 .part L_0x12b57e0, 6, 1; -L_0x12b7210 .part v0x12010b0_0, 6, 1; -LS_0x12b7380_0_0 .concat8 [ 1 1 1 1], L_0x12b5b70, L_0x12b5f10, L_0x12b6220, L_0x12b6530; -LS_0x12b7380_0_4 .concat8 [ 1 1 1 1], L_0x12b6890, L_0x12b6cc0, L_0x12b6ff0, L_0x12b6f80; -L_0x12b7380 .concat8 [ 4 4 0 0], LS_0x12b7380_0_0, LS_0x12b7380_0_4; -L_0x12b7740 .part L_0x12b57e0, 7, 1; -L_0x12b7930 .part v0x12010b0_0, 7, 1; -S_0x10eef80 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10ef190 .param/l "i" 0 4 54, +C4<00>; -L_0x12b5b70/d .functor AND 1, L_0x12b5c80, L_0x12b5e70, C4<1>, C4<1>; -L_0x12b5b70 .delay 1 (30000,30000,30000) L_0x12b5b70/d; -v0x10ef270_0 .net *"_s0", 0 0, L_0x12b5c80; 1 drivers -v0x10ef350_0 .net *"_s1", 0 0, L_0x12b5e70; 1 drivers -S_0x10ef430 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10ef640 .param/l "i" 0 4 54, +C4<01>; -L_0x12b5f10/d .functor AND 1, L_0x12b5fd0, L_0x12b6130, C4<1>, C4<1>; -L_0x12b5f10 .delay 1 (30000,30000,30000) L_0x12b5f10/d; -v0x10ef700_0 .net *"_s0", 0 0, L_0x12b5fd0; 1 drivers -v0x10ef7e0_0 .net *"_s1", 0 0, L_0x12b6130; 1 drivers -S_0x10ef8c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10efb00 .param/l "i" 0 4 54, +C4<010>; -L_0x12b6220/d .functor AND 1, L_0x12b62e0, L_0x12b6440, C4<1>, C4<1>; -L_0x12b6220 .delay 1 (30000,30000,30000) L_0x12b6220/d; -v0x10efba0_0 .net *"_s0", 0 0, L_0x12b62e0; 1 drivers -v0x10efc80_0 .net *"_s1", 0 0, L_0x12b6440; 1 drivers -S_0x10efd60 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10eff70 .param/l "i" 0 4 54, +C4<011>; -L_0x12b6530/d .functor AND 1, L_0x12b65f0, L_0x12b6750, C4<1>, C4<1>; -L_0x12b6530 .delay 1 (30000,30000,30000) L_0x12b6530/d; -v0x10f0030_0 .net *"_s0", 0 0, L_0x12b65f0; 1 drivers -v0x10f0110_0 .net *"_s1", 0 0, L_0x12b6750; 1 drivers -S_0x10f01f0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10f0450 .param/l "i" 0 4 54, +C4<0100>; -L_0x12b6890/d .functor AND 1, L_0x12b6950, L_0x12b6bc0, C4<1>, C4<1>; -L_0x12b6890 .delay 1 (30000,30000,30000) L_0x12b6890/d; -v0x10f0510_0 .net *"_s0", 0 0, L_0x12b6950; 1 drivers -v0x10f05f0_0 .net *"_s1", 0 0, L_0x12b6bc0; 1 drivers -S_0x10f06d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10f08e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x12b6cc0/d .functor AND 1, L_0x12b6d30, L_0x12b6e90, C4<1>, C4<1>; -L_0x12b6cc0 .delay 1 (30000,30000,30000) L_0x12b6cc0/d; -v0x10f09a0_0 .net *"_s0", 0 0, L_0x12b6d30; 1 drivers -v0x10f0a80_0 .net *"_s1", 0 0, L_0x12b6e90; 1 drivers -S_0x10f0b60 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10f0d70 .param/l "i" 0 4 54, +C4<0110>; -L_0x12b6ff0/d .functor AND 1, L_0x12b70b0, L_0x12b7210, C4<1>, C4<1>; -L_0x12b6ff0 .delay 1 (30000,30000,30000) L_0x12b6ff0/d; -v0x10f0e30_0 .net *"_s0", 0 0, L_0x12b70b0; 1 drivers -v0x10f0f10_0 .net *"_s1", 0 0, L_0x12b7210; 1 drivers -S_0x10f0ff0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10eed40; - .timescale -9 -12; -P_0x10f1200 .param/l "i" 0 4 54, +C4<0111>; -L_0x12b6f80/d .functor AND 1, L_0x12b7740, L_0x12b7930, C4<1>, C4<1>; -L_0x12b6f80 .delay 1 (30000,30000,30000) L_0x12b6f80/d; -v0x10f12c0_0 .net *"_s0", 0 0, L_0x12b7740; 1 drivers -v0x10f13a0_0 .net *"_s1", 0 0, L_0x12b7930; 1 drivers -S_0x10f1f60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10eeaf0; +v0x2bc27b0_0 .net "A", 7 0, L_0x2d40ab0; alias, 1 drivers +v0x2bc28b0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bc2970_0 .net *"_s0", 0 0, L_0x2da1200; 1 drivers +v0x2bc2a30_0 .net *"_s12", 0 0, L_0x2da1bc0; 1 drivers +v0x2bc2b10_0 .net *"_s16", 0 0, L_0x2da1f20; 1 drivers +v0x2bc2c40_0 .net *"_s20", 0 0, L_0x2da22f0; 1 drivers +v0x2bc2d20_0 .net *"_s24", 0 0, L_0x2da2620; 1 drivers +v0x2bc2e00_0 .net *"_s28", 0 0, L_0x2da25b0; 1 drivers +v0x2bc2ee0_0 .net *"_s4", 0 0, L_0x2da15a0; 1 drivers +v0x2bc3050_0 .net *"_s8", 0 0, L_0x2da18b0; 1 drivers +v0x2bc3130_0 .net "out", 7 0, L_0x2da29b0; alias, 1 drivers +L_0x2da1310 .part L_0x2d40ab0, 0, 1; +L_0x2da1500 .part v0x2cdd2e0_0, 0, 1; +L_0x2da1660 .part L_0x2d40ab0, 1, 1; +L_0x2da17c0 .part v0x2cdd2e0_0, 1, 1; +L_0x2da1970 .part L_0x2d40ab0, 2, 1; +L_0x2da1ad0 .part v0x2cdd2e0_0, 2, 1; +L_0x2da1c80 .part L_0x2d40ab0, 3, 1; +L_0x2da1de0 .part v0x2cdd2e0_0, 3, 1; +L_0x2da1fe0 .part L_0x2d40ab0, 4, 1; +L_0x2da2250 .part v0x2cdd2e0_0, 4, 1; +L_0x2da2360 .part L_0x2d40ab0, 5, 1; +L_0x2da24c0 .part v0x2cdd2e0_0, 5, 1; +L_0x2da26e0 .part L_0x2d40ab0, 6, 1; +L_0x2da2840 .part v0x2cdd2e0_0, 6, 1; +LS_0x2da29b0_0_0 .concat8 [ 1 1 1 1], L_0x2da1200, L_0x2da15a0, L_0x2da18b0, L_0x2da1bc0; +LS_0x2da29b0_0_4 .concat8 [ 1 1 1 1], L_0x2da1f20, L_0x2da22f0, L_0x2da2620, L_0x2da25b0; +L_0x2da29b0 .concat8 [ 4 4 0 0], LS_0x2da29b0_0_0, LS_0x2da29b0_0_4; +L_0x2da2d70 .part L_0x2d40ab0, 7, 1; +L_0x2da2f60 .part v0x2cdd2e0_0, 7, 1; +S_0x2bc02b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc04c0 .param/l "i" 0 4 54, +C4<00>; +L_0x2da1200/d .functor AND 1, L_0x2da1310, L_0x2da1500, C4<1>, C4<1>; +L_0x2da1200 .delay 1 (30000,30000,30000) L_0x2da1200/d; +v0x2bc05a0_0 .net *"_s0", 0 0, L_0x2da1310; 1 drivers +v0x2bc0680_0 .net *"_s1", 0 0, L_0x2da1500; 1 drivers +S_0x2bc0760 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc0970 .param/l "i" 0 4 54, +C4<01>; +L_0x2da15a0/d .functor AND 1, L_0x2da1660, L_0x2da17c0, C4<1>, C4<1>; +L_0x2da15a0 .delay 1 (30000,30000,30000) L_0x2da15a0/d; +v0x2bc0a30_0 .net *"_s0", 0 0, L_0x2da1660; 1 drivers +v0x2bc0b10_0 .net *"_s1", 0 0, L_0x2da17c0; 1 drivers +S_0x2bc0bf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc0e30 .param/l "i" 0 4 54, +C4<010>; +L_0x2da18b0/d .functor AND 1, L_0x2da1970, L_0x2da1ad0, C4<1>, C4<1>; +L_0x2da18b0 .delay 1 (30000,30000,30000) L_0x2da18b0/d; +v0x2bc0ed0_0 .net *"_s0", 0 0, L_0x2da1970; 1 drivers +v0x2bc0fb0_0 .net *"_s1", 0 0, L_0x2da1ad0; 1 drivers +S_0x2bc1090 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc12a0 .param/l "i" 0 4 54, +C4<011>; +L_0x2da1bc0/d .functor AND 1, L_0x2da1c80, L_0x2da1de0, C4<1>, C4<1>; +L_0x2da1bc0 .delay 1 (30000,30000,30000) L_0x2da1bc0/d; +v0x2bc1360_0 .net *"_s0", 0 0, L_0x2da1c80; 1 drivers +v0x2bc1440_0 .net *"_s1", 0 0, L_0x2da1de0; 1 drivers +S_0x2bc1520 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc1780 .param/l "i" 0 4 54, +C4<0100>; +L_0x2da1f20/d .functor AND 1, L_0x2da1fe0, L_0x2da2250, C4<1>, C4<1>; +L_0x2da1f20 .delay 1 (30000,30000,30000) L_0x2da1f20/d; +v0x2bc1840_0 .net *"_s0", 0 0, L_0x2da1fe0; 1 drivers +v0x2bc1920_0 .net *"_s1", 0 0, L_0x2da2250; 1 drivers +S_0x2bc1a00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc1c10 .param/l "i" 0 4 54, +C4<0101>; +L_0x2da22f0/d .functor AND 1, L_0x2da2360, L_0x2da24c0, C4<1>, C4<1>; +L_0x2da22f0 .delay 1 (30000,30000,30000) L_0x2da22f0/d; +v0x2bc1cd0_0 .net *"_s0", 0 0, L_0x2da2360; 1 drivers +v0x2bc1db0_0 .net *"_s1", 0 0, L_0x2da24c0; 1 drivers +S_0x2bc1e90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc20a0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2da2620/d .functor AND 1, L_0x2da26e0, L_0x2da2840, C4<1>, C4<1>; +L_0x2da2620 .delay 1 (30000,30000,30000) L_0x2da2620/d; +v0x2bc2160_0 .net *"_s0", 0 0, L_0x2da26e0; 1 drivers +v0x2bc2240_0 .net *"_s1", 0 0, L_0x2da2840; 1 drivers +S_0x2bc2320 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2bc0070; + .timescale -9 -12; +P_0x2bc2530 .param/l "i" 0 4 54, +C4<0111>; +L_0x2da25b0/d .functor AND 1, L_0x2da2d70, L_0x2da2f60, C4<1>, C4<1>; +L_0x2da25b0 .delay 1 (30000,30000,30000) L_0x2da25b0/d; +v0x2bc25f0_0 .net *"_s0", 0 0, L_0x2da2d70; 1 drivers +v0x2bc26d0_0 .net *"_s1", 0 0, L_0x2da2f60; 1 drivers +S_0x2bc3290 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2bbfe20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12b93e0/d .functor OR 1, L_0x12b94a0, L_0x12b9650, C4<0>, C4<0>; -L_0x12b93e0 .delay 1 (30000,30000,30000) L_0x12b93e0/d; -v0x10f3ab0_0 .net *"_s10", 0 0, L_0x12b94a0; 1 drivers -v0x10f3b90_0 .net *"_s12", 0 0, L_0x12b9650; 1 drivers -v0x10f3c70_0 .net "in", 7 0, L_0x12b7380; alias, 1 drivers -v0x10f3d40_0 .net "ors", 1 0, L_0x12b9200; 1 drivers -v0x10f3e00_0 .net "out", 0 0, L_0x12b93e0; alias, 1 drivers -L_0x12b85a0 .part L_0x12b7380, 0, 4; -L_0x12b9200 .concat8 [ 1 1 0 0], L_0x12b8260, L_0x12b8ec0; -L_0x12b9340 .part L_0x12b7380, 4, 4; -L_0x12b94a0 .part L_0x12b9200, 0, 1; -L_0x12b9650 .part L_0x12b9200, 1, 1; -S_0x10f2120 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10f1f60; +L_0x2da49b0/d .functor OR 1, L_0x2da4a70, L_0x2da4c20, C4<0>, C4<0>; +L_0x2da49b0 .delay 1 (30000,30000,30000) L_0x2da49b0/d; +v0x2bc4de0_0 .net *"_s10", 0 0, L_0x2da4a70; 1 drivers +v0x2bc4ec0_0 .net *"_s12", 0 0, L_0x2da4c20; 1 drivers +v0x2bc4fa0_0 .net "in", 7 0, L_0x2da29b0; alias, 1 drivers +v0x2bc5070_0 .net "ors", 1 0, L_0x2da47d0; 1 drivers +v0x2bc5130_0 .net "out", 0 0, L_0x2da49b0; alias, 1 drivers +L_0x2da3ba0 .part L_0x2da29b0, 0, 4; +L_0x2da47d0 .concat8 [ 1 1 0 0], L_0x2da3890, L_0x2da44c0; +L_0x2da4910 .part L_0x2da29b0, 4, 4; +L_0x2da4a70 .part L_0x2da47d0, 0, 1; +L_0x2da4c20 .part L_0x2da47d0, 1, 1; +S_0x2bc3450 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bc3290; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12b7a20/d .functor OR 1, L_0x12b7ae0, L_0x12b7c40, C4<0>, C4<0>; -L_0x12b7a20 .delay 1 (30000,30000,30000) L_0x12b7a20/d; -L_0x12b7e70/d .functor OR 1, L_0x12b7f80, L_0x12b80e0, C4<0>, C4<0>; -L_0x12b7e70 .delay 1 (30000,30000,30000) L_0x12b7e70/d; -L_0x12b8260/d .functor OR 1, L_0x12b8300, L_0x12b84b0, C4<0>, C4<0>; -L_0x12b8260 .delay 1 (30000,30000,30000) L_0x12b8260/d; -v0x10f2370_0 .net *"_s0", 0 0, L_0x12b7a20; 1 drivers -v0x10f2470_0 .net *"_s10", 0 0, L_0x12b7f80; 1 drivers -v0x10f2550_0 .net *"_s12", 0 0, L_0x12b80e0; 1 drivers -v0x10f2610_0 .net *"_s14", 0 0, L_0x12b8300; 1 drivers -v0x10f26f0_0 .net *"_s16", 0 0, L_0x12b84b0; 1 drivers -v0x10f2820_0 .net *"_s3", 0 0, L_0x12b7ae0; 1 drivers -v0x10f2900_0 .net *"_s5", 0 0, L_0x12b7c40; 1 drivers -v0x10f29e0_0 .net *"_s6", 0 0, L_0x12b7e70; 1 drivers -v0x10f2ac0_0 .net "in", 3 0, L_0x12b85a0; 1 drivers -v0x10f2c30_0 .net "ors", 1 0, L_0x12b7d80; 1 drivers -v0x10f2d10_0 .net "out", 0 0, L_0x12b8260; 1 drivers -L_0x12b7ae0 .part L_0x12b85a0, 0, 1; -L_0x12b7c40 .part L_0x12b85a0, 1, 1; -L_0x12b7d80 .concat8 [ 1 1 0 0], L_0x12b7a20, L_0x12b7e70; -L_0x12b7f80 .part L_0x12b85a0, 2, 1; -L_0x12b80e0 .part L_0x12b85a0, 3, 1; -L_0x12b8300 .part L_0x12b7d80, 0, 1; -L_0x12b84b0 .part L_0x12b7d80, 1, 1; -S_0x10f2e30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10f1f60; +L_0x2da3050/d .functor OR 1, L_0x2da3110, L_0x2da3270, C4<0>, C4<0>; +L_0x2da3050 .delay 1 (30000,30000,30000) L_0x2da3050/d; +L_0x2da34a0/d .functor OR 1, L_0x2da35b0, L_0x2da3710, C4<0>, C4<0>; +L_0x2da34a0 .delay 1 (30000,30000,30000) L_0x2da34a0/d; +L_0x2da3890/d .functor OR 1, L_0x2da3900, L_0x2da3ab0, C4<0>, C4<0>; +L_0x2da3890 .delay 1 (30000,30000,30000) L_0x2da3890/d; +v0x2bc36a0_0 .net *"_s0", 0 0, L_0x2da3050; 1 drivers +v0x2bc37a0_0 .net *"_s10", 0 0, L_0x2da35b0; 1 drivers +v0x2bc3880_0 .net *"_s12", 0 0, L_0x2da3710; 1 drivers +v0x2bc3940_0 .net *"_s14", 0 0, L_0x2da3900; 1 drivers +v0x2bc3a20_0 .net *"_s16", 0 0, L_0x2da3ab0; 1 drivers +v0x2bc3b50_0 .net *"_s3", 0 0, L_0x2da3110; 1 drivers +v0x2bc3c30_0 .net *"_s5", 0 0, L_0x2da3270; 1 drivers +v0x2bc3d10_0 .net *"_s6", 0 0, L_0x2da34a0; 1 drivers +v0x2bc3df0_0 .net "in", 3 0, L_0x2da3ba0; 1 drivers +v0x2bc3f60_0 .net "ors", 1 0, L_0x2da33b0; 1 drivers +v0x2bc4040_0 .net "out", 0 0, L_0x2da3890; 1 drivers +L_0x2da3110 .part L_0x2da3ba0, 0, 1; +L_0x2da3270 .part L_0x2da3ba0, 1, 1; +L_0x2da33b0 .concat8 [ 1 1 0 0], L_0x2da3050, L_0x2da34a0; +L_0x2da35b0 .part L_0x2da3ba0, 2, 1; +L_0x2da3710 .part L_0x2da3ba0, 3, 1; +L_0x2da3900 .part L_0x2da33b0, 0, 1; +L_0x2da3ab0 .part L_0x2da33b0, 1, 1; +S_0x2bc4160 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bc3290; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12b86d0/d .functor OR 1, L_0x12b8740, L_0x12b88a0, C4<0>, C4<0>; -L_0x12b86d0 .delay 1 (30000,30000,30000) L_0x12b86d0/d; -L_0x12b8ad0/d .functor OR 1, L_0x12b8be0, L_0x12b8d40, C4<0>, C4<0>; -L_0x12b8ad0 .delay 1 (30000,30000,30000) L_0x12b8ad0/d; -L_0x12b8ec0/d .functor OR 1, L_0x12b8f60, L_0x12b9110, C4<0>, C4<0>; -L_0x12b8ec0 .delay 1 (30000,30000,30000) L_0x12b8ec0/d; -v0x10f2ff0_0 .net *"_s0", 0 0, L_0x12b86d0; 1 drivers -v0x10f30f0_0 .net *"_s10", 0 0, L_0x12b8be0; 1 drivers -v0x10f31d0_0 .net *"_s12", 0 0, L_0x12b8d40; 1 drivers -v0x10f3290_0 .net *"_s14", 0 0, L_0x12b8f60; 1 drivers -v0x10f3370_0 .net *"_s16", 0 0, L_0x12b9110; 1 drivers -v0x10f34a0_0 .net *"_s3", 0 0, L_0x12b8740; 1 drivers -v0x10f3580_0 .net *"_s5", 0 0, L_0x12b88a0; 1 drivers -v0x10f3660_0 .net *"_s6", 0 0, L_0x12b8ad0; 1 drivers -v0x10f3740_0 .net "in", 3 0, L_0x12b9340; 1 drivers -v0x10f38b0_0 .net "ors", 1 0, L_0x12b89e0; 1 drivers -v0x10f3990_0 .net "out", 0 0, L_0x12b8ec0; 1 drivers -L_0x12b8740 .part L_0x12b9340, 0, 1; -L_0x12b88a0 .part L_0x12b9340, 1, 1; -L_0x12b89e0 .concat8 [ 1 1 0 0], L_0x12b86d0, L_0x12b8ad0; -L_0x12b8be0 .part L_0x12b9340, 2, 1; -L_0x12b8d40 .part L_0x12b9340, 3, 1; -L_0x12b8f60 .part L_0x12b89e0, 0, 1; -L_0x12b9110 .part L_0x12b89e0, 1, 1; -S_0x10f42a0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10e7c20; +L_0x2da3cd0/d .functor OR 1, L_0x2da3d40, L_0x2da3ea0, C4<0>, C4<0>; +L_0x2da3cd0 .delay 1 (30000,30000,30000) L_0x2da3cd0/d; +L_0x2da40d0/d .functor OR 1, L_0x2da41e0, L_0x2da4340, C4<0>, C4<0>; +L_0x2da40d0 .delay 1 (30000,30000,30000) L_0x2da40d0/d; +L_0x2da44c0/d .functor OR 1, L_0x2da4530, L_0x2da46e0, C4<0>, C4<0>; +L_0x2da44c0 .delay 1 (30000,30000,30000) L_0x2da44c0/d; +v0x2bc4320_0 .net *"_s0", 0 0, L_0x2da3cd0; 1 drivers +v0x2bc4420_0 .net *"_s10", 0 0, L_0x2da41e0; 1 drivers +v0x2bc4500_0 .net *"_s12", 0 0, L_0x2da4340; 1 drivers +v0x2bc45c0_0 .net *"_s14", 0 0, L_0x2da4530; 1 drivers +v0x2bc46a0_0 .net *"_s16", 0 0, L_0x2da46e0; 1 drivers +v0x2bc47d0_0 .net *"_s3", 0 0, L_0x2da3d40; 1 drivers +v0x2bc48b0_0 .net *"_s5", 0 0, L_0x2da3ea0; 1 drivers +v0x2bc4990_0 .net *"_s6", 0 0, L_0x2da40d0; 1 drivers +v0x2bc4a70_0 .net "in", 3 0, L_0x2da4910; 1 drivers +v0x2bc4be0_0 .net "ors", 1 0, L_0x2da3fe0; 1 drivers +v0x2bc4cc0_0 .net "out", 0 0, L_0x2da44c0; 1 drivers +L_0x2da3d40 .part L_0x2da4910, 0, 1; +L_0x2da3ea0 .part L_0x2da4910, 1, 1; +L_0x2da3fe0 .concat8 [ 1 1 0 0], L_0x2da3cd0, L_0x2da40d0; +L_0x2da41e0 .part L_0x2da4910, 2, 1; +L_0x2da4340 .part L_0x2da4910, 3, 1; +L_0x2da4530 .part L_0x2da3fe0, 0, 1; +L_0x2da46e0 .part L_0x2da3fe0, 1, 1; +S_0x2bc55d0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2bb8f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -10214,80 +10805,80 @@ S_0x10f42a0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10e7c20; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12b4b50/d .functor XNOR 1, L_0x12bd310, L_0x12bd470, C4<0>, C4<0>; -L_0x12b4b50 .delay 1 (20000,20000,20000) L_0x12b4b50/d; -L_0x12b4dc0/d .functor AND 1, L_0x12bd310, L_0x12b3b50, C4<1>, C4<1>; -L_0x12b4dc0 .delay 1 (30000,30000,30000) L_0x12b4dc0/d; -L_0x12b4e30/d .functor AND 1, L_0x12b4b50, L_0x12b3790, C4<1>, C4<1>; -L_0x12b4e30 .delay 1 (30000,30000,30000) L_0x12b4e30/d; -L_0x12b4f90/d .functor OR 1, L_0x12b4e30, L_0x12b4dc0, C4<0>, C4<0>; -L_0x12b4f90 .delay 1 (30000,30000,30000) L_0x12b4f90/d; -v0x10f4550_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers -v0x10f4640_0 .net "a_", 0 0, L_0x12b39f0; alias, 1 drivers -v0x10f4700_0 .net "b", 0 0, L_0x12bd470; alias, 1 drivers -v0x10f47f0_0 .net "b_", 0 0, L_0x12b3b50; alias, 1 drivers -v0x10f4890_0 .net "carryin", 0 0, L_0x12b3790; alias, 1 drivers -v0x10f49d0_0 .net "eq", 0 0, L_0x12b4b50; 1 drivers -v0x10f4a90_0 .net "lt", 0 0, L_0x12b4dc0; 1 drivers -v0x10f4b50_0 .net "out", 0 0, L_0x12b4f90; 1 drivers -v0x10f4c10_0 .net "w0", 0 0, L_0x12b4e30; 1 drivers -S_0x10f4e60 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10e7c20; +L_0x2d9ef90/d .functor XNOR 1, L_0x2da8850, L_0x2da89b0, C4<0>, C4<0>; +L_0x2d9ef90 .delay 1 (20000,20000,20000) L_0x2d9ef90/d; +L_0x2d9f110/d .functor AND 1, L_0x2da8850, L_0x2d9dc80, C4<1>, C4<1>; +L_0x2d9f110 .delay 1 (30000,30000,30000) L_0x2d9f110/d; +L_0x2d9f270/d .functor AND 1, L_0x2d9ef90, L_0x2d9d910, C4<1>, C4<1>; +L_0x2d9f270 .delay 1 (30000,30000,30000) L_0x2d9f270/d; +L_0x2d9f380/d .functor OR 1, L_0x2d9f270, L_0x2d9f110, C4<0>, C4<0>; +L_0x2d9f380 .delay 1 (30000,30000,30000) L_0x2d9f380/d; +v0x2bc5880_0 .net "a", 0 0, L_0x2da8850; alias, 1 drivers +v0x2bc5970_0 .net "a_", 0 0, L_0x2d9db70; alias, 1 drivers +v0x2bc5a30_0 .net "b", 0 0, L_0x2da89b0; alias, 1 drivers +v0x2bc5b20_0 .net "b_", 0 0, L_0x2d9dc80; alias, 1 drivers +v0x2bc5bc0_0 .net "carryin", 0 0, L_0x2d9d910; alias, 1 drivers +v0x2bc5d00_0 .net "eq", 0 0, L_0x2d9ef90; 1 drivers +v0x2bc5dc0_0 .net "lt", 0 0, L_0x2d9f110; 1 drivers +v0x2bc5e80_0 .net "out", 0 0, L_0x2d9f380; 1 drivers +v0x2bc5f40_0 .net "w0", 0 0, L_0x2d9f270; 1 drivers +S_0x2bc6190 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2bb8f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12b4930/d .functor OR 1, L_0x12b4480, L_0x10f60c0, C4<0>, C4<0>; -L_0x12b4930 .delay 1 (30000,30000,30000) L_0x12b4930/d; -v0x10f5c50_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers -v0x10f5da0_0 .net "b", 0 0, L_0x12b3b50; alias, 1 drivers -v0x10f5e60_0 .net "c1", 0 0, L_0x12b4480; 1 drivers -v0x10f5f00_0 .net "c2", 0 0, L_0x10f60c0; 1 drivers -v0x10f5fd0_0 .net "carryin", 0 0, L_0x12b3790; alias, 1 drivers -v0x10f6150_0 .net "carryout", 0 0, L_0x12b4930; 1 drivers -v0x10f61f0_0 .net "s1", 0 0, L_0x12b43c0; 1 drivers -v0x10f6290_0 .net "sum", 0 0, L_0x12b45e0; 1 drivers -S_0x10f50b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10f4e60; +L_0x2d9eb70/d .functor OR 1, L_0x2d9e670, L_0x2bc73f0, C4<0>, C4<0>; +L_0x2d9eb70 .delay 1 (30000,30000,30000) L_0x2d9eb70/d; +v0x2bc6f80_0 .net "a", 0 0, L_0x2da8850; alias, 1 drivers +v0x2bc70d0_0 .net "b", 0 0, L_0x2d9dc80; alias, 1 drivers +v0x2bc7190_0 .net "c1", 0 0, L_0x2d9e670; 1 drivers +v0x2bc7230_0 .net "c2", 0 0, L_0x2bc73f0; 1 drivers +v0x2bc7300_0 .net "carryin", 0 0, L_0x2d9d910; alias, 1 drivers +v0x2bc7480_0 .net "carryout", 0 0, L_0x2d9eb70; 1 drivers +v0x2bc7520_0 .net "s1", 0 0, L_0x2d9e5b0; 1 drivers +v0x2bc75c0_0 .net "sum", 0 0, L_0x2d9e7d0; 1 drivers +S_0x2bc63e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2bc6190; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12b43c0/d .functor XOR 1, L_0x12bd310, L_0x12b3b50, C4<0>, C4<0>; -L_0x12b43c0 .delay 1 (30000,30000,30000) L_0x12b43c0/d; -L_0x12b4480/d .functor AND 1, L_0x12bd310, L_0x12b3b50, C4<1>, C4<1>; -L_0x12b4480 .delay 1 (30000,30000,30000) L_0x12b4480/d; -v0x10f5310_0 .net "a", 0 0, L_0x12bd310; alias, 1 drivers -v0x10f53d0_0 .net "b", 0 0, L_0x12b3b50; alias, 1 drivers -v0x10f5490_0 .net "carryout", 0 0, L_0x12b4480; alias, 1 drivers -v0x10f5530_0 .net "sum", 0 0, L_0x12b43c0; alias, 1 drivers -S_0x10f5660 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10f4e60; +L_0x2d9e5b0/d .functor XOR 1, L_0x2da8850, L_0x2d9dc80, C4<0>, C4<0>; +L_0x2d9e5b0 .delay 1 (30000,30000,30000) L_0x2d9e5b0/d; +L_0x2d9e670/d .functor AND 1, L_0x2da8850, L_0x2d9dc80, C4<1>, C4<1>; +L_0x2d9e670 .delay 1 (30000,30000,30000) L_0x2d9e670/d; +v0x2bc6640_0 .net "a", 0 0, L_0x2da8850; alias, 1 drivers +v0x2bc6700_0 .net "b", 0 0, L_0x2d9dc80; alias, 1 drivers +v0x2bc67c0_0 .net "carryout", 0 0, L_0x2d9e670; alias, 1 drivers +v0x2bc6860_0 .net "sum", 0 0, L_0x2d9e5b0; alias, 1 drivers +S_0x2bc6990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2bc6190; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12b45e0/d .functor XOR 1, L_0x12b43c0, L_0x12b3790, C4<0>, C4<0>; -L_0x12b45e0 .delay 1 (30000,30000,30000) L_0x12b45e0/d; -L_0x10f60c0/d .functor AND 1, L_0x12b43c0, L_0x12b3790, C4<1>, C4<1>; -L_0x10f60c0 .delay 1 (30000,30000,30000) L_0x10f60c0/d; -v0x10f58c0_0 .net "a", 0 0, L_0x12b43c0; alias, 1 drivers -v0x10f5990_0 .net "b", 0 0, L_0x12b3790; alias, 1 drivers -v0x10f5a30_0 .net "carryout", 0 0, L_0x10f60c0; alias, 1 drivers -v0x10f5b00_0 .net "sum", 0 0, L_0x12b45e0; alias, 1 drivers -S_0x10f76b0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10e7950; - .timescale -9 -12; -L_0x2b0ab3d06458 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d064a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12bd3b0/d .functor OR 1, L_0x2b0ab3d06458, L_0x2b0ab3d064a0, C4<0>, C4<0>; -L_0x12bd3b0 .delay 1 (30000,30000,30000) L_0x12bd3b0/d; -v0x10f78a0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06458; 1 drivers -v0x10f7980_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d064a0; 1 drivers -S_0x10f7a60 .scope generate, "alu_slices[19]" "alu_slices[19]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x10f7c70 .param/l "i" 0 3 41, +C4<010011>; -S_0x10f7d30 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10f7a60; +L_0x2d9e7d0/d .functor XOR 1, L_0x2d9e5b0, L_0x2d9d910, C4<0>, C4<0>; +L_0x2d9e7d0 .delay 1 (30000,30000,30000) L_0x2d9e7d0/d; +L_0x2bc73f0/d .functor AND 1, L_0x2d9e5b0, L_0x2d9d910, C4<1>, C4<1>; +L_0x2bc73f0 .delay 1 (30000,30000,30000) L_0x2bc73f0/d; +v0x2bc6bf0_0 .net "a", 0 0, L_0x2d9e5b0; alias, 1 drivers +v0x2bc6cc0_0 .net "b", 0 0, L_0x2d9d910; alias, 1 drivers +v0x2bc6d60_0 .net "carryout", 0 0, L_0x2bc73f0; alias, 1 drivers +v0x2bc6e30_0 .net "sum", 0 0, L_0x2d9e7d0; alias, 1 drivers +S_0x2bc9650 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2bb8c80; + .timescale -9 -12; +L_0x2ac6110ba9c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110baa10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2d40dd0/d .functor OR 1, L_0x2ac6110ba9c8, L_0x2ac6110baa10, C4<0>, C4<0>; +L_0x2d40dd0 .delay 1 (30000,30000,30000) L_0x2d40dd0/d; +v0x2bc9840_0 .net/2u *"_s0", 0 0, L_0x2ac6110ba9c8; 1 drivers +v0x2bc9920_0 .net/2u *"_s2", 0 0, L_0x2ac6110baa10; 1 drivers +S_0x2bc9a00 .scope generate, "alu_slices[19]" "alu_slices[19]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2bc9c10 .param/l "i" 0 3 39, +C4<010011>; +S_0x2bc9cd0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2bc9a00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -10296,445 +10887,476 @@ S_0x10f7d30 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x10f7a60; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12b7300/d .functor NOT 1, L_0x12c6f10, C4<0>, C4<0>, C4<0>; -L_0x12b7300 .delay 1 (10000,10000,10000) L_0x12b7300/d; -L_0x12bd780/d .functor NOT 1, L_0x12bd510, C4<0>, C4<0>, C4<0>; -L_0x12bd780 .delay 1 (10000,10000,10000) L_0x12bd780/d; -L_0x12be780/d .functor XOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; -L_0x12be780 .delay 1 (30000,30000,30000) L_0x12be780/d; -L_0x2b0ab3d064e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06530 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12bee30/d .functor OR 1, L_0x2b0ab3d064e8, L_0x2b0ab3d06530, C4<0>, C4<0>; -L_0x12bee30 .delay 1 (30000,30000,30000) L_0x12bee30/d; -L_0x12bf030/d .functor AND 1, L_0x12c6f10, L_0x12bd510, C4<1>, C4<1>; -L_0x12bf030 .delay 1 (30000,30000,30000) L_0x12bf030/d; -L_0x12bf0f0/d .functor NAND 1, L_0x12c6f10, L_0x12bd510, C4<1>, C4<1>; -L_0x12bf0f0 .delay 1 (20000,20000,20000) L_0x12bf0f0/d; -L_0x12bf250/d .functor XOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; -L_0x12bf250 .delay 1 (20000,20000,20000) L_0x12bf250/d; -L_0x12bf700/d .functor OR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; -L_0x12bf700 .delay 1 (30000,30000,30000) L_0x12bf700/d; -L_0x12c6e10/d .functor NOT 1, L_0x12c3070, C4<0>, C4<0>, C4<0>; -L_0x12c6e10 .delay 1 (10000,10000,10000) L_0x12c6e10/d; -v0x1106460_0 .net "A", 0 0, L_0x12c6f10; 1 drivers -v0x1106520_0 .net "A_", 0 0, L_0x12b7300; 1 drivers -v0x11065e0_0 .net "B", 0 0, L_0x12bd510; 1 drivers -v0x11066b0_0 .net "B_", 0 0, L_0x12bd780; 1 drivers -v0x1106750_0 .net *"_s12", 0 0, L_0x12bee30; 1 drivers -v0x1106840_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d064e8; 1 drivers -v0x1106900_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06530; 1 drivers -v0x11069e0_0 .net *"_s18", 0 0, L_0x12bf030; 1 drivers -v0x1106ac0_0 .net *"_s20", 0 0, L_0x12bf0f0; 1 drivers -v0x1106c30_0 .net *"_s22", 0 0, L_0x12bf250; 1 drivers -v0x1106d10_0 .net *"_s24", 0 0, L_0x12bf700; 1 drivers -o0x2b0ab3cd17b8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1106df0_0 name=_s30 -o0x2b0ab3cd17e8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1106ed0_0 name=_s32 -v0x1106fb0_0 .net *"_s8", 0 0, L_0x12be780; 1 drivers -v0x1107090_0 .net "carryin", 0 0, L_0x12bd5b0; 1 drivers -v0x1107130_0 .net "carryout", 0 0, L_0x12c6ab0; 1 drivers -v0x11071d0_0 .net "carryouts", 7 0, L_0x1354e90; 1 drivers -v0x1107380_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1107420_0 .net "result", 0 0, L_0x12c3070; 1 drivers -v0x1107510_0 .net "results", 7 0, L_0x12bf4d0; 1 drivers -v0x1107620_0 .net "zero", 0 0, L_0x12c6e10; 1 drivers -LS_0x12bf4d0_0_0 .concat8 [ 1 1 1 1], L_0x12bdca0, L_0x12be2d0, L_0x12be780, L_0x12bee30; -LS_0x12bf4d0_0_4 .concat8 [ 1 1 1 1], L_0x12bf030, L_0x12bf0f0, L_0x12bf250, L_0x12bf700; -L_0x12bf4d0 .concat8 [ 4 4 0 0], LS_0x12bf4d0_0_0, LS_0x12bf4d0_0_4; -LS_0x1354e90_0_0 .concat [ 1 1 1 1], L_0x12bdf50, L_0x12be620, o0x2b0ab3cd17b8, L_0x12bec80; -LS_0x1354e90_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd17e8; -L_0x1354e90 .concat [ 4 4 0 0], LS_0x1354e90_0_0, LS_0x1354e90_0_4; -S_0x10f7fb0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x10f7d30; +L_0x2da8c20/d .functor NOT 1, L_0x2db3100, C4<0>, C4<0>, C4<0>; +L_0x2da8c20 .delay 1 (10000,10000,10000) L_0x2da8c20/d; +L_0x2da8d30/d .functor NOT 1, L_0x2da8a50, C4<0>, C4<0>, C4<0>; +L_0x2da8d30 .delay 1 (10000,10000,10000) L_0x2da8d30/d; +L_0x2da9d80/d .functor XOR 1, L_0x2db3100, L_0x2da8a50, C4<0>, C4<0>; +L_0x2da9d80 .delay 1 (30000,30000,30000) L_0x2da9d80/d; +L_0x2ac6110baa58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110baaa0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2da9e40/d .functor OR 1, L_0x2ac6110baa58, L_0x2ac6110baaa0, C4<0>, C4<0>; +L_0x2da9e40 .delay 1 (30000,30000,30000) L_0x2da9e40/d; +L_0x2ac6110baae8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bab30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2daa5e0/d .functor OR 1, L_0x2ac6110baae8, L_0x2ac6110bab30, C4<0>, C4<0>; +L_0x2daa5e0 .delay 1 (30000,30000,30000) L_0x2daa5e0/d; +L_0x2daa7e0/d .functor AND 1, L_0x2db3100, L_0x2da8a50, C4<1>, C4<1>; +L_0x2daa7e0 .delay 1 (30000,30000,30000) L_0x2daa7e0/d; +L_0x2ac6110bab78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110babc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2daa8a0/d .functor OR 1, L_0x2ac6110bab78, L_0x2ac6110babc0, C4<0>, C4<0>; +L_0x2daa8a0 .delay 1 (30000,30000,30000) L_0x2daa8a0/d; +L_0x2daaaa0/d .functor NAND 1, L_0x2db3100, L_0x2da8a50, C4<1>, C4<1>; +L_0x2daaaa0 .delay 1 (20000,20000,20000) L_0x2daaaa0/d; +L_0x2ac6110bac08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bac50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2daabb0/d .functor OR 1, L_0x2ac6110bac08, L_0x2ac6110bac50, C4<0>, C4<0>; +L_0x2daabb0 .delay 1 (30000,30000,30000) L_0x2daabb0/d; +L_0x2daad60/d .functor NOR 1, L_0x2db3100, L_0x2da8a50, C4<0>, C4<0>; +L_0x2daad60 .delay 1 (20000,20000,20000) L_0x2daad60/d; +L_0x2ac6110bac98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bace0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2da91a0/d .functor OR 1, L_0x2ac6110bac98, L_0x2ac6110bace0, C4<0>, C4<0>; +L_0x2da91a0 .delay 1 (30000,30000,30000) L_0x2da91a0/d; +L_0x2dab410/d .functor OR 1, L_0x2db3100, L_0x2da8a50, C4<0>, C4<0>; +L_0x2dab410 .delay 1 (30000,30000,30000) L_0x2dab410/d; +L_0x2ac6110bad28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bad70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dab900/d .functor OR 1, L_0x2ac6110bad28, L_0x2ac6110bad70, C4<0>, C4<0>; +L_0x2dab900 .delay 1 (30000,30000,30000) L_0x2dab900/d; +L_0x2db3000/d .functor NOT 1, L_0x2daf260, C4<0>, C4<0>, C4<0>; +L_0x2db3000 .delay 1 (10000,10000,10000) L_0x2db3000/d; +v0x2bf8410_0 .net "A", 0 0, L_0x2db3100; 1 drivers +v0x2bf84d0_0 .net "A_", 0 0, L_0x2da8c20; 1 drivers +v0x2bf8590_0 .net "B", 0 0, L_0x2da8a50; 1 drivers +v0x2bf8660_0 .net "B_", 0 0, L_0x2da8d30; 1 drivers +v0x2bf8700_0 .net *"_s11", 0 0, L_0x2da9e40; 1 drivers +v0x2bf87f0_0 .net/2s *"_s13", 0 0, L_0x2ac6110baa58; 1 drivers +v0x2bf88b0_0 .net/2s *"_s15", 0 0, L_0x2ac6110baaa0; 1 drivers +v0x2bf8990_0 .net *"_s19", 0 0, L_0x2daa5e0; 1 drivers +v0x2bf8a70_0 .net/2s *"_s21", 0 0, L_0x2ac6110baae8; 1 drivers +v0x2bf8be0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bab30; 1 drivers +v0x2bf8cc0_0 .net *"_s25", 0 0, L_0x2daa7e0; 1 drivers +v0x2bf8da0_0 .net *"_s28", 0 0, L_0x2daa8a0; 1 drivers +v0x2bf8e80_0 .net/2s *"_s30", 0 0, L_0x2ac6110bab78; 1 drivers +v0x2bf8f60_0 .net/2s *"_s32", 0 0, L_0x2ac6110babc0; 1 drivers +v0x2bf9040_0 .net *"_s34", 0 0, L_0x2daaaa0; 1 drivers +v0x2bf9120_0 .net *"_s37", 0 0, L_0x2daabb0; 1 drivers +v0x2bf9200_0 .net/2s *"_s39", 0 0, L_0x2ac6110bac08; 1 drivers +v0x2bf93b0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bac50; 1 drivers +v0x2bf9450_0 .net *"_s43", 0 0, L_0x2daad60; 1 drivers +v0x2bf9530_0 .net *"_s46", 0 0, L_0x2da91a0; 1 drivers +v0x2bf9610_0 .net/2s *"_s48", 0 0, L_0x2ac6110bac98; 1 drivers +v0x2bf96f0_0 .net/2s *"_s50", 0 0, L_0x2ac6110bace0; 1 drivers +v0x2bf97d0_0 .net *"_s52", 0 0, L_0x2dab410; 1 drivers +v0x2bf98b0_0 .net *"_s56", 0 0, L_0x2dab900; 1 drivers +v0x2bf9990_0 .net/2s *"_s59", 0 0, L_0x2ac6110bad28; 1 drivers +v0x2bf9a70_0 .net/2s *"_s61", 0 0, L_0x2ac6110bad70; 1 drivers +v0x2bf9b50_0 .net *"_s8", 0 0, L_0x2da9d80; 1 drivers +v0x2bf9c30_0 .net "carryin", 0 0, L_0x2da8af0; 1 drivers +v0x2bf9cd0_0 .net "carryout", 0 0, L_0x2db2ca0; 1 drivers +v0x2bf9d70_0 .net "carryouts", 7 0, L_0x2dab590; 1 drivers +v0x2bf9e80_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bf9f40_0 .net "result", 0 0, L_0x2daf260; 1 drivers +v0x2bfa030_0 .net "results", 7 0, L_0x2dab1e0; 1 drivers +v0x2bf9310_0 .net "zero", 0 0, L_0x2db3000; 1 drivers +LS_0x2dab1e0_0_0 .concat8 [ 1 1 1 1], L_0x2da9250, L_0x2da9880, L_0x2da9d80, L_0x2daa5e0; +LS_0x2dab1e0_0_4 .concat8 [ 1 1 1 1], L_0x2daa7e0, L_0x2daaaa0, L_0x2daad60, L_0x2dab410; +L_0x2dab1e0 .concat8 [ 4 4 0 0], LS_0x2dab1e0_0_0, LS_0x2dab1e0_0_4; +LS_0x2dab590_0_0 .concat8 [ 1 1 1 1], L_0x2da9500, L_0x2da9c20, L_0x2da9e40, L_0x2daa430; +LS_0x2dab590_0_4 .concat8 [ 1 1 1 1], L_0x2daa8a0, L_0x2daabb0, L_0x2da91a0, L_0x2dab900; +L_0x2dab590 .concat8 [ 4 4 0 0], LS_0x2dab590_0_0, LS_0x2dab590_0_4; +S_0x2bc9f50 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2bc9cd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12bdf50/d .functor OR 1, L_0x12bda30, L_0x12bddf0, C4<0>, C4<0>; -L_0x12bdf50 .delay 1 (30000,30000,30000) L_0x12bdf50/d; -v0x10f8de0_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers -v0x10f8ea0_0 .net "b", 0 0, L_0x12bd510; alias, 1 drivers -v0x10f8f70_0 .net "c1", 0 0, L_0x12bda30; 1 drivers -v0x10f9070_0 .net "c2", 0 0, L_0x12bddf0; 1 drivers -v0x10f9140_0 .net "carryin", 0 0, L_0x12bd5b0; alias, 1 drivers -v0x10f9230_0 .net "carryout", 0 0, L_0x12bdf50; 1 drivers -v0x10f92d0_0 .net "s1", 0 0, L_0x12bd970; 1 drivers -v0x10f93c0_0 .net "sum", 0 0, L_0x12bdca0; 1 drivers -S_0x10f8220 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x10f7fb0; +L_0x2da9500/d .functor OR 1, L_0x2da8fe0, L_0x2da93a0, C4<0>, C4<0>; +L_0x2da9500 .delay 1 (30000,30000,30000) L_0x2da9500/d; +v0x2bcad80_0 .net "a", 0 0, L_0x2db3100; alias, 1 drivers +v0x2bcae40_0 .net "b", 0 0, L_0x2da8a50; alias, 1 drivers +v0x2bcaf10_0 .net "c1", 0 0, L_0x2da8fe0; 1 drivers +v0x2bcb010_0 .net "c2", 0 0, L_0x2da93a0; 1 drivers +v0x2bcb0e0_0 .net "carryin", 0 0, L_0x2da8af0; alias, 1 drivers +v0x2bcb1d0_0 .net "carryout", 0 0, L_0x2da9500; 1 drivers +v0x2bcb270_0 .net "s1", 0 0, L_0x2da8f20; 1 drivers +v0x2bcb360_0 .net "sum", 0 0, L_0x2da9250; 1 drivers +S_0x2bca1c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2bc9f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12bd970/d .functor XOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; -L_0x12bd970 .delay 1 (30000,30000,30000) L_0x12bd970/d; -L_0x12bda30/d .functor AND 1, L_0x12c6f10, L_0x12bd510, C4<1>, C4<1>; -L_0x12bda30 .delay 1 (30000,30000,30000) L_0x12bda30/d; -v0x10f8480_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers -v0x10f8560_0 .net "b", 0 0, L_0x12bd510; alias, 1 drivers -v0x10f8620_0 .net "carryout", 0 0, L_0x12bda30; alias, 1 drivers -v0x10f86c0_0 .net "sum", 0 0, L_0x12bd970; alias, 1 drivers -S_0x10f8800 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x10f7fb0; +L_0x2da8f20/d .functor XOR 1, L_0x2db3100, L_0x2da8a50, C4<0>, C4<0>; +L_0x2da8f20 .delay 1 (30000,30000,30000) L_0x2da8f20/d; +L_0x2da8fe0/d .functor AND 1, L_0x2db3100, L_0x2da8a50, C4<1>, C4<1>; +L_0x2da8fe0 .delay 1 (30000,30000,30000) L_0x2da8fe0/d; +v0x2bca420_0 .net "a", 0 0, L_0x2db3100; alias, 1 drivers +v0x2bca500_0 .net "b", 0 0, L_0x2da8a50; alias, 1 drivers +v0x2bca5c0_0 .net "carryout", 0 0, L_0x2da8fe0; alias, 1 drivers +v0x2bca660_0 .net "sum", 0 0, L_0x2da8f20; alias, 1 drivers +S_0x2bca7a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2bc9f50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12bdca0/d .functor XOR 1, L_0x12bd970, L_0x12bd5b0, C4<0>, C4<0>; -L_0x12bdca0 .delay 1 (30000,30000,30000) L_0x12bdca0/d; -L_0x12bddf0/d .functor AND 1, L_0x12bd970, L_0x12bd5b0, C4<1>, C4<1>; -L_0x12bddf0 .delay 1 (30000,30000,30000) L_0x12bddf0/d; -v0x10f8a60_0 .net "a", 0 0, L_0x12bd970; alias, 1 drivers -v0x10f8b00_0 .net "b", 0 0, L_0x12bd5b0; alias, 1 drivers -v0x10f8ba0_0 .net "carryout", 0 0, L_0x12bddf0; alias, 1 drivers -v0x10f8c70_0 .net "sum", 0 0, L_0x12bdca0; alias, 1 drivers -S_0x10f9490 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x10f7d30; +L_0x2da9250/d .functor XOR 1, L_0x2da8f20, L_0x2da8af0, C4<0>, C4<0>; +L_0x2da9250 .delay 1 (30000,30000,30000) L_0x2da9250/d; +L_0x2da93a0/d .functor AND 1, L_0x2da8f20, L_0x2da8af0, C4<1>, C4<1>; +L_0x2da93a0 .delay 1 (30000,30000,30000) L_0x2da93a0/d; +v0x2bcaa00_0 .net "a", 0 0, L_0x2da8f20; alias, 1 drivers +v0x2bcaaa0_0 .net "b", 0 0, L_0x2da8af0; alias, 1 drivers +v0x2bcab40_0 .net "carryout", 0 0, L_0x2da93a0; alias, 1 drivers +v0x2bcac10_0 .net "sum", 0 0, L_0x2da9250; alias, 1 drivers +S_0x2bcb430 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2bc9cd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x10fe880_0 .net "ands", 7 0, L_0x12c4ab0; 1 drivers -v0x10fe990_0 .net "in", 7 0, L_0x1354e90; alias, 1 drivers -v0x10fea50_0 .net "out", 0 0, L_0x12c6ab0; alias, 1 drivers -v0x10feb20_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10f96b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10f9490; +v0x2bf0830_0 .net "ands", 7 0, L_0x2db0ca0; 1 drivers +v0x2bf0940_0 .net "in", 7 0, L_0x2dab590; alias, 1 drivers +v0x2bf0a00_0 .net "out", 0 0, L_0x2db2ca0; alias, 1 drivers +v0x2bf0ad0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2bcb650 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2bcb430; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x10fbde0_0 .net "A", 7 0, L_0x1354e90; alias, 1 drivers -v0x10fbee0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x10fbfa0_0 .net *"_s0", 0 0, L_0x12c33d0; 1 drivers -v0x10fc060_0 .net *"_s12", 0 0, L_0x12c3d40; 1 drivers -v0x10fc140_0 .net *"_s16", 0 0, L_0x12c40a0; 1 drivers -v0x10fc270_0 .net *"_s20", 0 0, L_0x12c43b0; 1 drivers -v0x10fc350_0 .net *"_s24", 0 0, L_0x12c47a0; 1 drivers -v0x10fc430_0 .net *"_s28", 0 0, L_0x12c4730; 1 drivers -v0x10fc510_0 .net *"_s4", 0 0, L_0x12c36e0; 1 drivers -v0x10fc680_0 .net *"_s8", 0 0, L_0x12c3a30; 1 drivers -v0x10fc760_0 .net "out", 7 0, L_0x12c4ab0; alias, 1 drivers -L_0x12c3490 .part L_0x1354e90, 0, 1; -L_0x12c35f0 .part v0x12010b0_0, 0, 1; -L_0x12c37a0 .part L_0x1354e90, 1, 1; -L_0x12c3990 .part v0x12010b0_0, 1, 1; -L_0x12c3af0 .part L_0x1354e90, 2, 1; -L_0x12c3c50 .part v0x12010b0_0, 2, 1; -L_0x12c3e00 .part L_0x1354e90, 3, 1; -L_0x12c3f60 .part v0x12010b0_0, 3, 1; -L_0x12c4160 .part L_0x1354e90, 4, 1; -L_0x12c42c0 .part v0x12010b0_0, 4, 1; -L_0x12c4420 .part L_0x1354e90, 5, 1; -L_0x12c4690 .part v0x12010b0_0, 5, 1; -L_0x12c4860 .part L_0x1354e90, 6, 1; -L_0x12c49c0 .part v0x12010b0_0, 6, 1; -LS_0x12c4ab0_0_0 .concat8 [ 1 1 1 1], L_0x12c33d0, L_0x12c36e0, L_0x12c3a30, L_0x12c3d40; -LS_0x12c4ab0_0_4 .concat8 [ 1 1 1 1], L_0x12c40a0, L_0x12c43b0, L_0x12c47a0, L_0x12c4730; -L_0x12c4ab0 .concat8 [ 4 4 0 0], LS_0x12c4ab0_0_0, LS_0x12c4ab0_0_4; -L_0x12c4e70 .part L_0x1354e90, 7, 1; -L_0x12c5060 .part v0x12010b0_0, 7, 1; -S_0x10f9910 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10f9b20 .param/l "i" 0 4 54, +C4<00>; -L_0x12c33d0/d .functor AND 1, L_0x12c3490, L_0x12c35f0, C4<1>, C4<1>; -L_0x12c33d0 .delay 1 (30000,30000,30000) L_0x12c33d0/d; -v0x10f9c00_0 .net *"_s0", 0 0, L_0x12c3490; 1 drivers -v0x10f9ce0_0 .net *"_s1", 0 0, L_0x12c35f0; 1 drivers -S_0x10f9dc0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10f9fd0 .param/l "i" 0 4 54, +C4<01>; -L_0x12c36e0/d .functor AND 1, L_0x12c37a0, L_0x12c3990, C4<1>, C4<1>; -L_0x12c36e0 .delay 1 (30000,30000,30000) L_0x12c36e0/d; -v0x10fa090_0 .net *"_s0", 0 0, L_0x12c37a0; 1 drivers -v0x10fa170_0 .net *"_s1", 0 0, L_0x12c3990; 1 drivers -S_0x10fa250 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10fa460 .param/l "i" 0 4 54, +C4<010>; -L_0x12c3a30/d .functor AND 1, L_0x12c3af0, L_0x12c3c50, C4<1>, C4<1>; -L_0x12c3a30 .delay 1 (30000,30000,30000) L_0x12c3a30/d; -v0x10fa500_0 .net *"_s0", 0 0, L_0x12c3af0; 1 drivers -v0x10fa5e0_0 .net *"_s1", 0 0, L_0x12c3c50; 1 drivers -S_0x10fa6c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10fa8d0 .param/l "i" 0 4 54, +C4<011>; -L_0x12c3d40/d .functor AND 1, L_0x12c3e00, L_0x12c3f60, C4<1>, C4<1>; -L_0x12c3d40 .delay 1 (30000,30000,30000) L_0x12c3d40/d; -v0x10fa990_0 .net *"_s0", 0 0, L_0x12c3e00; 1 drivers -v0x10faa70_0 .net *"_s1", 0 0, L_0x12c3f60; 1 drivers -S_0x10fab50 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10fadb0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12c40a0/d .functor AND 1, L_0x12c4160, L_0x12c42c0, C4<1>, C4<1>; -L_0x12c40a0 .delay 1 (30000,30000,30000) L_0x12c40a0/d; -v0x10fae70_0 .net *"_s0", 0 0, L_0x12c4160; 1 drivers -v0x10faf50_0 .net *"_s1", 0 0, L_0x12c42c0; 1 drivers -S_0x10fb030 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10fb240 .param/l "i" 0 4 54, +C4<0101>; -L_0x12c43b0/d .functor AND 1, L_0x12c4420, L_0x12c4690, C4<1>, C4<1>; -L_0x12c43b0 .delay 1 (30000,30000,30000) L_0x12c43b0/d; -v0x10fb300_0 .net *"_s0", 0 0, L_0x12c4420; 1 drivers -v0x10fb3e0_0 .net *"_s1", 0 0, L_0x12c4690; 1 drivers -S_0x10fb4c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10fb6d0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12c47a0/d .functor AND 1, L_0x12c4860, L_0x12c49c0, C4<1>, C4<1>; -L_0x12c47a0 .delay 1 (30000,30000,30000) L_0x12c47a0/d; -v0x10fb790_0 .net *"_s0", 0 0, L_0x12c4860; 1 drivers -v0x10fb870_0 .net *"_s1", 0 0, L_0x12c49c0; 1 drivers -S_0x10fb950 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10f96b0; - .timescale -9 -12; -P_0x10fbb60 .param/l "i" 0 4 54, +C4<0111>; -L_0x12c4730/d .functor AND 1, L_0x12c4e70, L_0x12c5060, C4<1>, C4<1>; -L_0x12c4730 .delay 1 (30000,30000,30000) L_0x12c4730/d; -v0x10fbc20_0 .net *"_s0", 0 0, L_0x12c4e70; 1 drivers -v0x10fbd00_0 .net *"_s1", 0 0, L_0x12c5060; 1 drivers -S_0x10fc8c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10f9490; +v0x2bcdd80_0 .net "A", 7 0, L_0x2dab590; alias, 1 drivers +v0x2bcde80_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bcdf40_0 .net *"_s0", 0 0, L_0x2daf5c0; 1 drivers +v0x2bce000_0 .net *"_s12", 0 0, L_0x2daff30; 1 drivers +v0x2bce0e0_0 .net *"_s16", 0 0, L_0x2db0290; 1 drivers +v0x2bce210_0 .net *"_s20", 0 0, L_0x2db0660; 1 drivers +v0x2bce2f0_0 .net *"_s24", 0 0, L_0x2db0990; 1 drivers +v0x2bce3d0_0 .net *"_s28", 0 0, L_0x2db0920; 1 drivers +v0x2bce4b0_0 .net *"_s4", 0 0, L_0x2daf910; 1 drivers +v0x2bce620_0 .net *"_s8", 0 0, L_0x2dafc20; 1 drivers +v0x2bce700_0 .net "out", 7 0, L_0x2db0ca0; alias, 1 drivers +L_0x2daf680 .part L_0x2dab590, 0, 1; +L_0x2daf870 .part v0x2cdd2e0_0, 0, 1; +L_0x2daf9d0 .part L_0x2dab590, 1, 1; +L_0x2dafb30 .part v0x2cdd2e0_0, 1, 1; +L_0x2dafce0 .part L_0x2dab590, 2, 1; +L_0x2dafe40 .part v0x2cdd2e0_0, 2, 1; +L_0x2dafff0 .part L_0x2dab590, 3, 1; +L_0x2db0150 .part v0x2cdd2e0_0, 3, 1; +L_0x2db0350 .part L_0x2dab590, 4, 1; +L_0x2db05c0 .part v0x2cdd2e0_0, 4, 1; +L_0x2db06d0 .part L_0x2dab590, 5, 1; +L_0x2db0830 .part v0x2cdd2e0_0, 5, 1; +L_0x2db0a50 .part L_0x2dab590, 6, 1; +L_0x2db0bb0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2db0ca0_0_0 .concat8 [ 1 1 1 1], L_0x2daf5c0, L_0x2daf910, L_0x2dafc20, L_0x2daff30; +LS_0x2db0ca0_0_4 .concat8 [ 1 1 1 1], L_0x2db0290, L_0x2db0660, L_0x2db0990, L_0x2db0920; +L_0x2db0ca0 .concat8 [ 4 4 0 0], LS_0x2db0ca0_0_0, LS_0x2db0ca0_0_4; +L_0x2db1060 .part L_0x2dab590, 7, 1; +L_0x2db1250 .part v0x2cdd2e0_0, 7, 1; +S_0x2bcb8b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcbac0 .param/l "i" 0 4 54, +C4<00>; +L_0x2daf5c0/d .functor AND 1, L_0x2daf680, L_0x2daf870, C4<1>, C4<1>; +L_0x2daf5c0 .delay 1 (30000,30000,30000) L_0x2daf5c0/d; +v0x2bcbba0_0 .net *"_s0", 0 0, L_0x2daf680; 1 drivers +v0x2bcbc80_0 .net *"_s1", 0 0, L_0x2daf870; 1 drivers +S_0x2bcbd60 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcbf70 .param/l "i" 0 4 54, +C4<01>; +L_0x2daf910/d .functor AND 1, L_0x2daf9d0, L_0x2dafb30, C4<1>, C4<1>; +L_0x2daf910 .delay 1 (30000,30000,30000) L_0x2daf910/d; +v0x2bcc030_0 .net *"_s0", 0 0, L_0x2daf9d0; 1 drivers +v0x2bcc110_0 .net *"_s1", 0 0, L_0x2dafb30; 1 drivers +S_0x2bcc1f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcc400 .param/l "i" 0 4 54, +C4<010>; +L_0x2dafc20/d .functor AND 1, L_0x2dafce0, L_0x2dafe40, C4<1>, C4<1>; +L_0x2dafc20 .delay 1 (30000,30000,30000) L_0x2dafc20/d; +v0x2bcc4a0_0 .net *"_s0", 0 0, L_0x2dafce0; 1 drivers +v0x2bcc580_0 .net *"_s1", 0 0, L_0x2dafe40; 1 drivers +S_0x2bcc660 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcc870 .param/l "i" 0 4 54, +C4<011>; +L_0x2daff30/d .functor AND 1, L_0x2dafff0, L_0x2db0150, C4<1>, C4<1>; +L_0x2daff30 .delay 1 (30000,30000,30000) L_0x2daff30/d; +v0x2bcc930_0 .net *"_s0", 0 0, L_0x2dafff0; 1 drivers +v0x2bcca10_0 .net *"_s1", 0 0, L_0x2db0150; 1 drivers +S_0x2bccaf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bccd50 .param/l "i" 0 4 54, +C4<0100>; +L_0x2db0290/d .functor AND 1, L_0x2db0350, L_0x2db05c0, C4<1>, C4<1>; +L_0x2db0290 .delay 1 (30000,30000,30000) L_0x2db0290/d; +v0x2bcce10_0 .net *"_s0", 0 0, L_0x2db0350; 1 drivers +v0x2bccef0_0 .net *"_s1", 0 0, L_0x2db05c0; 1 drivers +S_0x2bccfd0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcd1e0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2db0660/d .functor AND 1, L_0x2db06d0, L_0x2db0830, C4<1>, C4<1>; +L_0x2db0660 .delay 1 (30000,30000,30000) L_0x2db0660/d; +v0x2bcd2a0_0 .net *"_s0", 0 0, L_0x2db06d0; 1 drivers +v0x2bcd380_0 .net *"_s1", 0 0, L_0x2db0830; 1 drivers +S_0x2bcd460 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcd670 .param/l "i" 0 4 54, +C4<0110>; +L_0x2db0990/d .functor AND 1, L_0x2db0a50, L_0x2db0bb0, C4<1>, C4<1>; +L_0x2db0990 .delay 1 (30000,30000,30000) L_0x2db0990/d; +v0x2bcd730_0 .net *"_s0", 0 0, L_0x2db0a50; 1 drivers +v0x2bcd810_0 .net *"_s1", 0 0, L_0x2db0bb0; 1 drivers +S_0x2bcd8f0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2bcb650; + .timescale -9 -12; +P_0x2bcdb00 .param/l "i" 0 4 54, +C4<0111>; +L_0x2db0920/d .functor AND 1, L_0x2db1060, L_0x2db1250, C4<1>, C4<1>; +L_0x2db0920 .delay 1 (30000,30000,30000) L_0x2db0920/d; +v0x2bcdbc0_0 .net *"_s0", 0 0, L_0x2db1060; 1 drivers +v0x2bcdca0_0 .net *"_s1", 0 0, L_0x2db1250; 1 drivers +S_0x2bce860 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2bcb430; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12c6ab0/d .functor OR 1, L_0x12c6b70, L_0x12c6d20, C4<0>, C4<0>; -L_0x12c6ab0 .delay 1 (30000,30000,30000) L_0x12c6ab0/d; -v0x10fe410_0 .net *"_s10", 0 0, L_0x12c6b70; 1 drivers -v0x10fe4f0_0 .net *"_s12", 0 0, L_0x12c6d20; 1 drivers -v0x10fe5d0_0 .net "in", 7 0, L_0x12c4ab0; alias, 1 drivers -v0x10fe6a0_0 .net "ors", 1 0, L_0x12c68d0; 1 drivers -v0x10fe760_0 .net "out", 0 0, L_0x12c6ab0; alias, 1 drivers -L_0x12c5ca0 .part L_0x12c4ab0, 0, 4; -L_0x12c68d0 .concat8 [ 1 1 0 0], L_0x12c5990, L_0x12c65c0; -L_0x12c6a10 .part L_0x12c4ab0, 4, 4; -L_0x12c6b70 .part L_0x12c68d0, 0, 1; -L_0x12c6d20 .part L_0x12c68d0, 1, 1; -S_0x10fca80 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x10fc8c0; +L_0x2db2ca0/d .functor OR 1, L_0x2db2d60, L_0x2db2f10, C4<0>, C4<0>; +L_0x2db2ca0 .delay 1 (30000,30000,30000) L_0x2db2ca0/d; +v0x2bf0390_0 .net *"_s10", 0 0, L_0x2db2d60; 1 drivers +v0x2bf0470_0 .net *"_s12", 0 0, L_0x2db2f10; 1 drivers +v0x2bf0550_0 .net "in", 7 0, L_0x2db0ca0; alias, 1 drivers +v0x2bf0650_0 .net "ors", 1 0, L_0x2db2ac0; 1 drivers +v0x2bf0710_0 .net "out", 0 0, L_0x2db2ca0; alias, 1 drivers +L_0x2db1e90 .part L_0x2db0ca0, 0, 4; +L_0x2db2ac0 .concat8 [ 1 1 0 0], L_0x2db1b80, L_0x2db27b0; +L_0x2db2c00 .part L_0x2db0ca0, 4, 4; +L_0x2db2d60 .part L_0x2db2ac0, 0, 1; +L_0x2db2f10 .part L_0x2db2ac0, 1, 1; +S_0x2bcea20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bce860; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12c5150/d .functor OR 1, L_0x12c5210, L_0x12c5370, C4<0>, C4<0>; -L_0x12c5150 .delay 1 (30000,30000,30000) L_0x12c5150/d; -L_0x12c55a0/d .functor OR 1, L_0x12c56b0, L_0x12c5810, C4<0>, C4<0>; -L_0x12c55a0 .delay 1 (30000,30000,30000) L_0x12c55a0/d; -L_0x12c5990/d .functor OR 1, L_0x12c5a00, L_0x12c5bb0, C4<0>, C4<0>; -L_0x12c5990 .delay 1 (30000,30000,30000) L_0x12c5990/d; -v0x10fccd0_0 .net *"_s0", 0 0, L_0x12c5150; 1 drivers -v0x10fcdd0_0 .net *"_s10", 0 0, L_0x12c56b0; 1 drivers -v0x10fceb0_0 .net *"_s12", 0 0, L_0x12c5810; 1 drivers -v0x10fcf70_0 .net *"_s14", 0 0, L_0x12c5a00; 1 drivers -v0x10fd050_0 .net *"_s16", 0 0, L_0x12c5bb0; 1 drivers -v0x10fd180_0 .net *"_s3", 0 0, L_0x12c5210; 1 drivers -v0x10fd260_0 .net *"_s5", 0 0, L_0x12c5370; 1 drivers -v0x10fd340_0 .net *"_s6", 0 0, L_0x12c55a0; 1 drivers -v0x10fd420_0 .net "in", 3 0, L_0x12c5ca0; 1 drivers -v0x10fd590_0 .net "ors", 1 0, L_0x12c54b0; 1 drivers -v0x10fd670_0 .net "out", 0 0, L_0x12c5990; 1 drivers -L_0x12c5210 .part L_0x12c5ca0, 0, 1; -L_0x12c5370 .part L_0x12c5ca0, 1, 1; -L_0x12c54b0 .concat8 [ 1 1 0 0], L_0x12c5150, L_0x12c55a0; -L_0x12c56b0 .part L_0x12c5ca0, 2, 1; -L_0x12c5810 .part L_0x12c5ca0, 3, 1; -L_0x12c5a00 .part L_0x12c54b0, 0, 1; -L_0x12c5bb0 .part L_0x12c54b0, 1, 1; -S_0x10fd790 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x10fc8c0; +L_0x2db1340/d .functor OR 1, L_0x2db1400, L_0x2db1560, C4<0>, C4<0>; +L_0x2db1340 .delay 1 (30000,30000,30000) L_0x2db1340/d; +L_0x2db1790/d .functor OR 1, L_0x2db18a0, L_0x2db1a00, C4<0>, C4<0>; +L_0x2db1790 .delay 1 (30000,30000,30000) L_0x2db1790/d; +L_0x2db1b80/d .functor OR 1, L_0x2db1bf0, L_0x2db1da0, C4<0>, C4<0>; +L_0x2db1b80 .delay 1 (30000,30000,30000) L_0x2db1b80/d; +v0x2bcec70_0 .net *"_s0", 0 0, L_0x2db1340; 1 drivers +v0x2bced70_0 .net *"_s10", 0 0, L_0x2db18a0; 1 drivers +v0x2bcee50_0 .net *"_s12", 0 0, L_0x2db1a00; 1 drivers +v0x2bcef10_0 .net *"_s14", 0 0, L_0x2db1bf0; 1 drivers +v0x2bceff0_0 .net *"_s16", 0 0, L_0x2db1da0; 1 drivers +v0x2bcf120_0 .net *"_s3", 0 0, L_0x2db1400; 1 drivers +v0x2bcf200_0 .net *"_s5", 0 0, L_0x2db1560; 1 drivers +v0x2bcf2e0_0 .net *"_s6", 0 0, L_0x2db1790; 1 drivers +v0x2bcf3c0_0 .net "in", 3 0, L_0x2db1e90; 1 drivers +v0x2bcf530_0 .net "ors", 1 0, L_0x2db16a0; 1 drivers +v0x2bcf610_0 .net "out", 0 0, L_0x2db1b80; 1 drivers +L_0x2db1400 .part L_0x2db1e90, 0, 1; +L_0x2db1560 .part L_0x2db1e90, 1, 1; +L_0x2db16a0 .concat8 [ 1 1 0 0], L_0x2db1340, L_0x2db1790; +L_0x2db18a0 .part L_0x2db1e90, 2, 1; +L_0x2db1a00 .part L_0x2db1e90, 3, 1; +L_0x2db1bf0 .part L_0x2db16a0, 0, 1; +L_0x2db1da0 .part L_0x2db16a0, 1, 1; +S_0x2bcf730 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bce860; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12c5dd0/d .functor OR 1, L_0x12c5e40, L_0x12c5fa0, C4<0>, C4<0>; -L_0x12c5dd0 .delay 1 (30000,30000,30000) L_0x12c5dd0/d; -L_0x12c61d0/d .functor OR 1, L_0x12c62e0, L_0x12c6440, C4<0>, C4<0>; -L_0x12c61d0 .delay 1 (30000,30000,30000) L_0x12c61d0/d; -L_0x12c65c0/d .functor OR 1, L_0x12c6630, L_0x12c67e0, C4<0>, C4<0>; -L_0x12c65c0 .delay 1 (30000,30000,30000) L_0x12c65c0/d; -v0x10fd950_0 .net *"_s0", 0 0, L_0x12c5dd0; 1 drivers -v0x10fda50_0 .net *"_s10", 0 0, L_0x12c62e0; 1 drivers -v0x10fdb30_0 .net *"_s12", 0 0, L_0x12c6440; 1 drivers -v0x10fdbf0_0 .net *"_s14", 0 0, L_0x12c6630; 1 drivers -v0x10fdcd0_0 .net *"_s16", 0 0, L_0x12c67e0; 1 drivers -v0x10fde00_0 .net *"_s3", 0 0, L_0x12c5e40; 1 drivers -v0x10fdee0_0 .net *"_s5", 0 0, L_0x12c5fa0; 1 drivers -v0x10fdfc0_0 .net *"_s6", 0 0, L_0x12c61d0; 1 drivers -v0x10fe0a0_0 .net "in", 3 0, L_0x12c6a10; 1 drivers -v0x10fe210_0 .net "ors", 1 0, L_0x12c60e0; 1 drivers -v0x10fe2f0_0 .net "out", 0 0, L_0x12c65c0; 1 drivers -L_0x12c5e40 .part L_0x12c6a10, 0, 1; -L_0x12c5fa0 .part L_0x12c6a10, 1, 1; -L_0x12c60e0 .concat8 [ 1 1 0 0], L_0x12c5dd0, L_0x12c61d0; -L_0x12c62e0 .part L_0x12c6a10, 2, 1; -L_0x12c6440 .part L_0x12c6a10, 3, 1; -L_0x12c6630 .part L_0x12c60e0, 0, 1; -L_0x12c67e0 .part L_0x12c60e0, 1, 1; -S_0x10fec00 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x10f7d30; +L_0x2db1fc0/d .functor OR 1, L_0x2db2030, L_0x2db2190, C4<0>, C4<0>; +L_0x2db1fc0 .delay 1 (30000,30000,30000) L_0x2db1fc0/d; +L_0x2db23c0/d .functor OR 1, L_0x2db24d0, L_0x2db2630, C4<0>, C4<0>; +L_0x2db23c0 .delay 1 (30000,30000,30000) L_0x2db23c0/d; +L_0x2db27b0/d .functor OR 1, L_0x2db2820, L_0x2db29d0, C4<0>, C4<0>; +L_0x2db27b0 .delay 1 (30000,30000,30000) L_0x2db27b0/d; +v0x2bcf8f0_0 .net *"_s0", 0 0, L_0x2db1fc0; 1 drivers +v0x2bcf9f0_0 .net *"_s10", 0 0, L_0x2db24d0; 1 drivers +v0x2bcfad0_0 .net *"_s12", 0 0, L_0x2db2630; 1 drivers +v0x2bcfb90_0 .net *"_s14", 0 0, L_0x2db2820; 1 drivers +v0x2bcfc70_0 .net *"_s16", 0 0, L_0x2db29d0; 1 drivers +v0x2bcfda0_0 .net *"_s3", 0 0, L_0x2db2030; 1 drivers +v0x2bcfe80_0 .net *"_s5", 0 0, L_0x2db2190; 1 drivers +v0x2beff40_0 .net *"_s6", 0 0, L_0x2db23c0; 1 drivers +v0x2bf0020_0 .net "in", 3 0, L_0x2db2c00; 1 drivers +v0x2bf0190_0 .net "ors", 1 0, L_0x2db22d0; 1 drivers +v0x2bf0270_0 .net "out", 0 0, L_0x2db27b0; 1 drivers +L_0x2db2030 .part L_0x2db2c00, 0, 1; +L_0x2db2190 .part L_0x2db2c00, 1, 1; +L_0x2db22d0 .concat8 [ 1 1 0 0], L_0x2db1fc0, L_0x2db23c0; +L_0x2db24d0 .part L_0x2db2c00, 2, 1; +L_0x2db2630 .part L_0x2db2c00, 3, 1; +L_0x2db2820 .part L_0x2db22d0, 0, 1; +L_0x2db29d0 .part L_0x2db22d0, 1, 1; +S_0x2bf0bb0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2bc9cd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1104030_0 .net "ands", 7 0, L_0x12c1070; 1 drivers -v0x1104140_0 .net "in", 7 0, L_0x12bf4d0; alias, 1 drivers -v0x1104200_0 .net "out", 0 0, L_0x12c3070; alias, 1 drivers -v0x11042d0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x10fee50 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x10fec00; +v0x2bf5fe0_0 .net "ands", 7 0, L_0x2dad260; 1 drivers +v0x2bf60f0_0 .net "in", 7 0, L_0x2dab1e0; alias, 1 drivers +v0x2bf61b0_0 .net "out", 0 0, L_0x2daf260; alias, 1 drivers +v0x2bf6280_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2bf0e00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2bf0bb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1101590_0 .net "A", 7 0, L_0x12bf4d0; alias, 1 drivers -v0x1101690_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1101750_0 .net *"_s0", 0 0, L_0x12bf860; 1 drivers -v0x1101810_0 .net *"_s12", 0 0, L_0x12c0220; 1 drivers -v0x11018f0_0 .net *"_s16", 0 0, L_0x12c0580; 1 drivers -v0x1101a20_0 .net *"_s20", 0 0, L_0x12c09b0; 1 drivers -v0x1101b00_0 .net *"_s24", 0 0, L_0x12c0ce0; 1 drivers -v0x1101be0_0 .net *"_s28", 0 0, L_0x12c0c70; 1 drivers -v0x1101cc0_0 .net *"_s4", 0 0, L_0x12bfc00; 1 drivers -v0x1101e30_0 .net *"_s8", 0 0, L_0x12bff10; 1 drivers -v0x1101f10_0 .net "out", 7 0, L_0x12c1070; alias, 1 drivers -L_0x12bf970 .part L_0x12bf4d0, 0, 1; -L_0x12bfb60 .part v0x12010b0_0, 0, 1; -L_0x12bfcc0 .part L_0x12bf4d0, 1, 1; -L_0x12bfe20 .part v0x12010b0_0, 1, 1; -L_0x12bffd0 .part L_0x12bf4d0, 2, 1; -L_0x12c0130 .part v0x12010b0_0, 2, 1; -L_0x12c02e0 .part L_0x12bf4d0, 3, 1; -L_0x12c0440 .part v0x12010b0_0, 3, 1; -L_0x12c0640 .part L_0x12bf4d0, 4, 1; -L_0x12c08b0 .part v0x12010b0_0, 4, 1; -L_0x12c0a20 .part L_0x12bf4d0, 5, 1; -L_0x12c0b80 .part v0x12010b0_0, 5, 1; -L_0x12c0da0 .part L_0x12bf4d0, 6, 1; -L_0x12c0f00 .part v0x12010b0_0, 6, 1; -LS_0x12c1070_0_0 .concat8 [ 1 1 1 1], L_0x12bf860, L_0x12bfc00, L_0x12bff10, L_0x12c0220; -LS_0x12c1070_0_4 .concat8 [ 1 1 1 1], L_0x12c0580, L_0x12c09b0, L_0x12c0ce0, L_0x12c0c70; -L_0x12c1070 .concat8 [ 4 4 0 0], LS_0x12c1070_0_0, LS_0x12c1070_0_4; -L_0x12c1430 .part L_0x12bf4d0, 7, 1; -L_0x12c1620 .part v0x12010b0_0, 7, 1; -S_0x10ff090 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x10ff2a0 .param/l "i" 0 4 54, +C4<00>; -L_0x12bf860/d .functor AND 1, L_0x12bf970, L_0x12bfb60, C4<1>, C4<1>; -L_0x12bf860 .delay 1 (30000,30000,30000) L_0x12bf860/d; -v0x10ff380_0 .net *"_s0", 0 0, L_0x12bf970; 1 drivers -v0x10ff460_0 .net *"_s1", 0 0, L_0x12bfb60; 1 drivers -S_0x10ff540 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x10ff750 .param/l "i" 0 4 54, +C4<01>; -L_0x12bfc00/d .functor AND 1, L_0x12bfcc0, L_0x12bfe20, C4<1>, C4<1>; -L_0x12bfc00 .delay 1 (30000,30000,30000) L_0x12bfc00/d; -v0x10ff810_0 .net *"_s0", 0 0, L_0x12bfcc0; 1 drivers -v0x10ff8f0_0 .net *"_s1", 0 0, L_0x12bfe20; 1 drivers -S_0x10ff9d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x10ffc10 .param/l "i" 0 4 54, +C4<010>; -L_0x12bff10/d .functor AND 1, L_0x12bffd0, L_0x12c0130, C4<1>, C4<1>; -L_0x12bff10 .delay 1 (30000,30000,30000) L_0x12bff10/d; -v0x10ffcb0_0 .net *"_s0", 0 0, L_0x12bffd0; 1 drivers -v0x10ffd90_0 .net *"_s1", 0 0, L_0x12c0130; 1 drivers -S_0x10ffe70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x1100080 .param/l "i" 0 4 54, +C4<011>; -L_0x12c0220/d .functor AND 1, L_0x12c02e0, L_0x12c0440, C4<1>, C4<1>; -L_0x12c0220 .delay 1 (30000,30000,30000) L_0x12c0220/d; -v0x1100140_0 .net *"_s0", 0 0, L_0x12c02e0; 1 drivers -v0x1100220_0 .net *"_s1", 0 0, L_0x12c0440; 1 drivers -S_0x1100300 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x1100560 .param/l "i" 0 4 54, +C4<0100>; -L_0x12c0580/d .functor AND 1, L_0x12c0640, L_0x12c08b0, C4<1>, C4<1>; -L_0x12c0580 .delay 1 (30000,30000,30000) L_0x12c0580/d; -v0x1100620_0 .net *"_s0", 0 0, L_0x12c0640; 1 drivers -v0x1100700_0 .net *"_s1", 0 0, L_0x12c08b0; 1 drivers -S_0x11007e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x11009f0 .param/l "i" 0 4 54, +C4<0101>; -L_0x12c09b0/d .functor AND 1, L_0x12c0a20, L_0x12c0b80, C4<1>, C4<1>; -L_0x12c09b0 .delay 1 (30000,30000,30000) L_0x12c09b0/d; -v0x1100ab0_0 .net *"_s0", 0 0, L_0x12c0a20; 1 drivers -v0x1100b90_0 .net *"_s1", 0 0, L_0x12c0b80; 1 drivers -S_0x1100c70 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x1100e80 .param/l "i" 0 4 54, +C4<0110>; -L_0x12c0ce0/d .functor AND 1, L_0x12c0da0, L_0x12c0f00, C4<1>, C4<1>; -L_0x12c0ce0 .delay 1 (30000,30000,30000) L_0x12c0ce0/d; -v0x1100f40_0 .net *"_s0", 0 0, L_0x12c0da0; 1 drivers -v0x1101020_0 .net *"_s1", 0 0, L_0x12c0f00; 1 drivers -S_0x1101100 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x10fee50; - .timescale -9 -12; -P_0x1101310 .param/l "i" 0 4 54, +C4<0111>; -L_0x12c0c70/d .functor AND 1, L_0x12c1430, L_0x12c1620, C4<1>, C4<1>; -L_0x12c0c70 .delay 1 (30000,30000,30000) L_0x12c0c70/d; -v0x11013d0_0 .net *"_s0", 0 0, L_0x12c1430; 1 drivers -v0x11014b0_0 .net *"_s1", 0 0, L_0x12c1620; 1 drivers -S_0x1102070 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x10fec00; +v0x2bf3540_0 .net "A", 7 0, L_0x2dab1e0; alias, 1 drivers +v0x2bf3640_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bf3700_0 .net *"_s0", 0 0, L_0x2dabab0; 1 drivers +v0x2bf37c0_0 .net *"_s12", 0 0, L_0x2dac470; 1 drivers +v0x2bf38a0_0 .net *"_s16", 0 0, L_0x2dac7d0; 1 drivers +v0x2bf39d0_0 .net *"_s20", 0 0, L_0x2dacba0; 1 drivers +v0x2bf3ab0_0 .net *"_s24", 0 0, L_0x2daced0; 1 drivers +v0x2bf3b90_0 .net *"_s28", 0 0, L_0x2dace60; 1 drivers +v0x2bf3c70_0 .net *"_s4", 0 0, L_0x2dabe50; 1 drivers +v0x2bf3de0_0 .net *"_s8", 0 0, L_0x2dac160; 1 drivers +v0x2bf3ec0_0 .net "out", 7 0, L_0x2dad260; alias, 1 drivers +L_0x2dabbc0 .part L_0x2dab1e0, 0, 1; +L_0x2dabdb0 .part v0x2cdd2e0_0, 0, 1; +L_0x2dabf10 .part L_0x2dab1e0, 1, 1; +L_0x2dac070 .part v0x2cdd2e0_0, 1, 1; +L_0x2dac220 .part L_0x2dab1e0, 2, 1; +L_0x2dac380 .part v0x2cdd2e0_0, 2, 1; +L_0x2dac530 .part L_0x2dab1e0, 3, 1; +L_0x2dac690 .part v0x2cdd2e0_0, 3, 1; +L_0x2dac890 .part L_0x2dab1e0, 4, 1; +L_0x2dacb00 .part v0x2cdd2e0_0, 4, 1; +L_0x2dacc10 .part L_0x2dab1e0, 5, 1; +L_0x2dacd70 .part v0x2cdd2e0_0, 5, 1; +L_0x2dacf90 .part L_0x2dab1e0, 6, 1; +L_0x2dad0f0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dad260_0_0 .concat8 [ 1 1 1 1], L_0x2dabab0, L_0x2dabe50, L_0x2dac160, L_0x2dac470; +LS_0x2dad260_0_4 .concat8 [ 1 1 1 1], L_0x2dac7d0, L_0x2dacba0, L_0x2daced0, L_0x2dace60; +L_0x2dad260 .concat8 [ 4 4 0 0], LS_0x2dad260_0_0, LS_0x2dad260_0_4; +L_0x2dad620 .part L_0x2dab1e0, 7, 1; +L_0x2dad810 .part v0x2cdd2e0_0, 7, 1; +S_0x2bf1040 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf1250 .param/l "i" 0 4 54, +C4<00>; +L_0x2dabab0/d .functor AND 1, L_0x2dabbc0, L_0x2dabdb0, C4<1>, C4<1>; +L_0x2dabab0 .delay 1 (30000,30000,30000) L_0x2dabab0/d; +v0x2bf1330_0 .net *"_s0", 0 0, L_0x2dabbc0; 1 drivers +v0x2bf1410_0 .net *"_s1", 0 0, L_0x2dabdb0; 1 drivers +S_0x2bf14f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf1700 .param/l "i" 0 4 54, +C4<01>; +L_0x2dabe50/d .functor AND 1, L_0x2dabf10, L_0x2dac070, C4<1>, C4<1>; +L_0x2dabe50 .delay 1 (30000,30000,30000) L_0x2dabe50/d; +v0x2bf17c0_0 .net *"_s0", 0 0, L_0x2dabf10; 1 drivers +v0x2bf18a0_0 .net *"_s1", 0 0, L_0x2dac070; 1 drivers +S_0x2bf1980 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf1bc0 .param/l "i" 0 4 54, +C4<010>; +L_0x2dac160/d .functor AND 1, L_0x2dac220, L_0x2dac380, C4<1>, C4<1>; +L_0x2dac160 .delay 1 (30000,30000,30000) L_0x2dac160/d; +v0x2bf1c60_0 .net *"_s0", 0 0, L_0x2dac220; 1 drivers +v0x2bf1d40_0 .net *"_s1", 0 0, L_0x2dac380; 1 drivers +S_0x2bf1e20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf2030 .param/l "i" 0 4 54, +C4<011>; +L_0x2dac470/d .functor AND 1, L_0x2dac530, L_0x2dac690, C4<1>, C4<1>; +L_0x2dac470 .delay 1 (30000,30000,30000) L_0x2dac470/d; +v0x2bf20f0_0 .net *"_s0", 0 0, L_0x2dac530; 1 drivers +v0x2bf21d0_0 .net *"_s1", 0 0, L_0x2dac690; 1 drivers +S_0x2bf22b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf2510 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dac7d0/d .functor AND 1, L_0x2dac890, L_0x2dacb00, C4<1>, C4<1>; +L_0x2dac7d0 .delay 1 (30000,30000,30000) L_0x2dac7d0/d; +v0x2bf25d0_0 .net *"_s0", 0 0, L_0x2dac890; 1 drivers +v0x2bf26b0_0 .net *"_s1", 0 0, L_0x2dacb00; 1 drivers +S_0x2bf2790 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf29a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dacba0/d .functor AND 1, L_0x2dacc10, L_0x2dacd70, C4<1>, C4<1>; +L_0x2dacba0 .delay 1 (30000,30000,30000) L_0x2dacba0/d; +v0x2bf2a60_0 .net *"_s0", 0 0, L_0x2dacc10; 1 drivers +v0x2bf2b40_0 .net *"_s1", 0 0, L_0x2dacd70; 1 drivers +S_0x2bf2c20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf2e30 .param/l "i" 0 4 54, +C4<0110>; +L_0x2daced0/d .functor AND 1, L_0x2dacf90, L_0x2dad0f0, C4<1>, C4<1>; +L_0x2daced0 .delay 1 (30000,30000,30000) L_0x2daced0/d; +v0x2bf2ef0_0 .net *"_s0", 0 0, L_0x2dacf90; 1 drivers +v0x2bf2fd0_0 .net *"_s1", 0 0, L_0x2dad0f0; 1 drivers +S_0x2bf30b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2bf0e00; + .timescale -9 -12; +P_0x2bf32c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dace60/d .functor AND 1, L_0x2dad620, L_0x2dad810, C4<1>, C4<1>; +L_0x2dace60 .delay 1 (30000,30000,30000) L_0x2dace60/d; +v0x2bf3380_0 .net *"_s0", 0 0, L_0x2dad620; 1 drivers +v0x2bf3460_0 .net *"_s1", 0 0, L_0x2dad810; 1 drivers +S_0x2bf4020 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2bf0bb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12c3070/d .functor OR 1, L_0x12c3130, L_0x12c32e0, C4<0>, C4<0>; -L_0x12c3070 .delay 1 (30000,30000,30000) L_0x12c3070/d; -v0x1103bc0_0 .net *"_s10", 0 0, L_0x12c3130; 1 drivers -v0x1103ca0_0 .net *"_s12", 0 0, L_0x12c32e0; 1 drivers -v0x1103d80_0 .net "in", 7 0, L_0x12c1070; alias, 1 drivers -v0x1103e50_0 .net "ors", 1 0, L_0x12c2e90; 1 drivers -v0x1103f10_0 .net "out", 0 0, L_0x12c3070; alias, 1 drivers -L_0x12c2260 .part L_0x12c1070, 0, 4; -L_0x12c2e90 .concat8 [ 1 1 0 0], L_0x12c1f50, L_0x12c2b80; -L_0x12c2fd0 .part L_0x12c1070, 4, 4; -L_0x12c3130 .part L_0x12c2e90, 0, 1; -L_0x12c32e0 .part L_0x12c2e90, 1, 1; -S_0x1102230 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1102070; +L_0x2daf260/d .functor OR 1, L_0x2daf320, L_0x2daf4d0, C4<0>, C4<0>; +L_0x2daf260 .delay 1 (30000,30000,30000) L_0x2daf260/d; +v0x2bf5b70_0 .net *"_s10", 0 0, L_0x2daf320; 1 drivers +v0x2bf5c50_0 .net *"_s12", 0 0, L_0x2daf4d0; 1 drivers +v0x2bf5d30_0 .net "in", 7 0, L_0x2dad260; alias, 1 drivers +v0x2bf5e00_0 .net "ors", 1 0, L_0x2daf080; 1 drivers +v0x2bf5ec0_0 .net "out", 0 0, L_0x2daf260; alias, 1 drivers +L_0x2dae450 .part L_0x2dad260, 0, 4; +L_0x2daf080 .concat8 [ 1 1 0 0], L_0x2dae140, L_0x2daed70; +L_0x2daf1c0 .part L_0x2dad260, 4, 4; +L_0x2daf320 .part L_0x2daf080, 0, 1; +L_0x2daf4d0 .part L_0x2daf080, 1, 1; +S_0x2bf41e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bf4020; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12c1710/d .functor OR 1, L_0x12c17d0, L_0x12c1930, C4<0>, C4<0>; -L_0x12c1710 .delay 1 (30000,30000,30000) L_0x12c1710/d; -L_0x12c1b60/d .functor OR 1, L_0x12c1c70, L_0x12c1dd0, C4<0>, C4<0>; -L_0x12c1b60 .delay 1 (30000,30000,30000) L_0x12c1b60/d; -L_0x12c1f50/d .functor OR 1, L_0x12c1fc0, L_0x12c2170, C4<0>, C4<0>; -L_0x12c1f50 .delay 1 (30000,30000,30000) L_0x12c1f50/d; -v0x1102480_0 .net *"_s0", 0 0, L_0x12c1710; 1 drivers -v0x1102580_0 .net *"_s10", 0 0, L_0x12c1c70; 1 drivers -v0x1102660_0 .net *"_s12", 0 0, L_0x12c1dd0; 1 drivers -v0x1102720_0 .net *"_s14", 0 0, L_0x12c1fc0; 1 drivers -v0x1102800_0 .net *"_s16", 0 0, L_0x12c2170; 1 drivers -v0x1102930_0 .net *"_s3", 0 0, L_0x12c17d0; 1 drivers -v0x1102a10_0 .net *"_s5", 0 0, L_0x12c1930; 1 drivers -v0x1102af0_0 .net *"_s6", 0 0, L_0x12c1b60; 1 drivers -v0x1102bd0_0 .net "in", 3 0, L_0x12c2260; 1 drivers -v0x1102d40_0 .net "ors", 1 0, L_0x12c1a70; 1 drivers -v0x1102e20_0 .net "out", 0 0, L_0x12c1f50; 1 drivers -L_0x12c17d0 .part L_0x12c2260, 0, 1; -L_0x12c1930 .part L_0x12c2260, 1, 1; -L_0x12c1a70 .concat8 [ 1 1 0 0], L_0x12c1710, L_0x12c1b60; -L_0x12c1c70 .part L_0x12c2260, 2, 1; -L_0x12c1dd0 .part L_0x12c2260, 3, 1; -L_0x12c1fc0 .part L_0x12c1a70, 0, 1; -L_0x12c2170 .part L_0x12c1a70, 1, 1; -S_0x1102f40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1102070; +L_0x2dad900/d .functor OR 1, L_0x2dad9c0, L_0x2dadb20, C4<0>, C4<0>; +L_0x2dad900 .delay 1 (30000,30000,30000) L_0x2dad900/d; +L_0x2dadd50/d .functor OR 1, L_0x2dade60, L_0x2dadfc0, C4<0>, C4<0>; +L_0x2dadd50 .delay 1 (30000,30000,30000) L_0x2dadd50/d; +L_0x2dae140/d .functor OR 1, L_0x2dae1b0, L_0x2dae360, C4<0>, C4<0>; +L_0x2dae140 .delay 1 (30000,30000,30000) L_0x2dae140/d; +v0x2bf4430_0 .net *"_s0", 0 0, L_0x2dad900; 1 drivers +v0x2bf4530_0 .net *"_s10", 0 0, L_0x2dade60; 1 drivers +v0x2bf4610_0 .net *"_s12", 0 0, L_0x2dadfc0; 1 drivers +v0x2bf46d0_0 .net *"_s14", 0 0, L_0x2dae1b0; 1 drivers +v0x2bf47b0_0 .net *"_s16", 0 0, L_0x2dae360; 1 drivers +v0x2bf48e0_0 .net *"_s3", 0 0, L_0x2dad9c0; 1 drivers +v0x2bf49c0_0 .net *"_s5", 0 0, L_0x2dadb20; 1 drivers +v0x2bf4aa0_0 .net *"_s6", 0 0, L_0x2dadd50; 1 drivers +v0x2bf4b80_0 .net "in", 3 0, L_0x2dae450; 1 drivers +v0x2bf4cf0_0 .net "ors", 1 0, L_0x2dadc60; 1 drivers +v0x2bf4dd0_0 .net "out", 0 0, L_0x2dae140; 1 drivers +L_0x2dad9c0 .part L_0x2dae450, 0, 1; +L_0x2dadb20 .part L_0x2dae450, 1, 1; +L_0x2dadc60 .concat8 [ 1 1 0 0], L_0x2dad900, L_0x2dadd50; +L_0x2dade60 .part L_0x2dae450, 2, 1; +L_0x2dadfc0 .part L_0x2dae450, 3, 1; +L_0x2dae1b0 .part L_0x2dadc60, 0, 1; +L_0x2dae360 .part L_0x2dadc60, 1, 1; +S_0x2bf4ef0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bf4020; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12c2390/d .functor OR 1, L_0x12c2400, L_0x12c2560, C4<0>, C4<0>; -L_0x12c2390 .delay 1 (30000,30000,30000) L_0x12c2390/d; -L_0x12c2790/d .functor OR 1, L_0x12c28a0, L_0x12c2a00, C4<0>, C4<0>; -L_0x12c2790 .delay 1 (30000,30000,30000) L_0x12c2790/d; -L_0x12c2b80/d .functor OR 1, L_0x12c2bf0, L_0x12c2da0, C4<0>, C4<0>; -L_0x12c2b80 .delay 1 (30000,30000,30000) L_0x12c2b80/d; -v0x1103100_0 .net *"_s0", 0 0, L_0x12c2390; 1 drivers -v0x1103200_0 .net *"_s10", 0 0, L_0x12c28a0; 1 drivers -v0x11032e0_0 .net *"_s12", 0 0, L_0x12c2a00; 1 drivers -v0x11033a0_0 .net *"_s14", 0 0, L_0x12c2bf0; 1 drivers -v0x1103480_0 .net *"_s16", 0 0, L_0x12c2da0; 1 drivers -v0x11035b0_0 .net *"_s3", 0 0, L_0x12c2400; 1 drivers -v0x1103690_0 .net *"_s5", 0 0, L_0x12c2560; 1 drivers -v0x1103770_0 .net *"_s6", 0 0, L_0x12c2790; 1 drivers -v0x1103850_0 .net "in", 3 0, L_0x12c2fd0; 1 drivers -v0x11039c0_0 .net "ors", 1 0, L_0x12c26a0; 1 drivers -v0x1103aa0_0 .net "out", 0 0, L_0x12c2b80; 1 drivers -L_0x12c2400 .part L_0x12c2fd0, 0, 1; -L_0x12c2560 .part L_0x12c2fd0, 1, 1; -L_0x12c26a0 .concat8 [ 1 1 0 0], L_0x12c2390, L_0x12c2790; -L_0x12c28a0 .part L_0x12c2fd0, 2, 1; -L_0x12c2a00 .part L_0x12c2fd0, 3, 1; -L_0x12c2bf0 .part L_0x12c26a0, 0, 1; -L_0x12c2da0 .part L_0x12c26a0, 1, 1; -S_0x11043b0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10f7d30; +L_0x2dae580/d .functor OR 1, L_0x2dae5f0, L_0x2dae750, C4<0>, C4<0>; +L_0x2dae580 .delay 1 (30000,30000,30000) L_0x2dae580/d; +L_0x2dae980/d .functor OR 1, L_0x2daea90, L_0x2daebf0, C4<0>, C4<0>; +L_0x2dae980 .delay 1 (30000,30000,30000) L_0x2dae980/d; +L_0x2daed70/d .functor OR 1, L_0x2daede0, L_0x2daef90, C4<0>, C4<0>; +L_0x2daed70 .delay 1 (30000,30000,30000) L_0x2daed70/d; +v0x2bf50b0_0 .net *"_s0", 0 0, L_0x2dae580; 1 drivers +v0x2bf51b0_0 .net *"_s10", 0 0, L_0x2daea90; 1 drivers +v0x2bf5290_0 .net *"_s12", 0 0, L_0x2daebf0; 1 drivers +v0x2bf5350_0 .net *"_s14", 0 0, L_0x2daede0; 1 drivers +v0x2bf5430_0 .net *"_s16", 0 0, L_0x2daef90; 1 drivers +v0x2bf5560_0 .net *"_s3", 0 0, L_0x2dae5f0; 1 drivers +v0x2bf5640_0 .net *"_s5", 0 0, L_0x2dae750; 1 drivers +v0x2bf5720_0 .net *"_s6", 0 0, L_0x2dae980; 1 drivers +v0x2bf5800_0 .net "in", 3 0, L_0x2daf1c0; 1 drivers +v0x2bf5970_0 .net "ors", 1 0, L_0x2dae890; 1 drivers +v0x2bf5a50_0 .net "out", 0 0, L_0x2daed70; 1 drivers +L_0x2dae5f0 .part L_0x2daf1c0, 0, 1; +L_0x2dae750 .part L_0x2daf1c0, 1, 1; +L_0x2dae890 .concat8 [ 1 1 0 0], L_0x2dae580, L_0x2dae980; +L_0x2daea90 .part L_0x2daf1c0, 2, 1; +L_0x2daebf0 .part L_0x2daf1c0, 3, 1; +L_0x2daede0 .part L_0x2dae890, 0, 1; +L_0x2daef90 .part L_0x2dae890, 1, 1; +S_0x2bf6360 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2bc9cd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -10742,80 +11364,80 @@ S_0x11043b0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x10f7d30; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12be840/d .functor XNOR 1, L_0x12c6f10, L_0x12bd510, C4<0>, C4<0>; -L_0x12be840 .delay 1 (20000,20000,20000) L_0x12be840/d; -L_0x12beab0/d .functor AND 1, L_0x12c6f10, L_0x12bd780, C4<1>, C4<1>; -L_0x12beab0 .delay 1 (30000,30000,30000) L_0x12beab0/d; -L_0x12beb20/d .functor AND 1, L_0x12be840, L_0x12bd5b0, C4<1>, C4<1>; -L_0x12beb20 .delay 1 (30000,30000,30000) L_0x12beb20/d; -L_0x12bec80/d .functor OR 1, L_0x12beb20, L_0x12beab0, C4<0>, C4<0>; -L_0x12bec80 .delay 1 (30000,30000,30000) L_0x12bec80/d; -v0x1104660_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers -v0x1104750_0 .net "a_", 0 0, L_0x12b7300; alias, 1 drivers -v0x1104810_0 .net "b", 0 0, L_0x12bd510; alias, 1 drivers -v0x1104900_0 .net "b_", 0 0, L_0x12bd780; alias, 1 drivers -v0x11049a0_0 .net "carryin", 0 0, L_0x12bd5b0; alias, 1 drivers -v0x1104ae0_0 .net "eq", 0 0, L_0x12be840; 1 drivers -v0x1104ba0_0 .net "lt", 0 0, L_0x12beab0; 1 drivers -v0x1104c60_0 .net "out", 0 0, L_0x12bec80; 1 drivers -v0x1104d20_0 .net "w0", 0 0, L_0x12beb20; 1 drivers -S_0x1104f70 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x10f7d30; +L_0x2daa040/d .functor XNOR 1, L_0x2db3100, L_0x2da8a50, C4<0>, C4<0>; +L_0x2daa040 .delay 1 (20000,20000,20000) L_0x2daa040/d; +L_0x2daa1c0/d .functor AND 1, L_0x2db3100, L_0x2da8d30, C4<1>, C4<1>; +L_0x2daa1c0 .delay 1 (30000,30000,30000) L_0x2daa1c0/d; +L_0x2daa320/d .functor AND 1, L_0x2daa040, L_0x2da8af0, C4<1>, C4<1>; +L_0x2daa320 .delay 1 (30000,30000,30000) L_0x2daa320/d; +L_0x2daa430/d .functor OR 1, L_0x2daa320, L_0x2daa1c0, C4<0>, C4<0>; +L_0x2daa430 .delay 1 (30000,30000,30000) L_0x2daa430/d; +v0x2bf6610_0 .net "a", 0 0, L_0x2db3100; alias, 1 drivers +v0x2bf6700_0 .net "a_", 0 0, L_0x2da8c20; alias, 1 drivers +v0x2bf67c0_0 .net "b", 0 0, L_0x2da8a50; alias, 1 drivers +v0x2bf68b0_0 .net "b_", 0 0, L_0x2da8d30; alias, 1 drivers +v0x2bf6950_0 .net "carryin", 0 0, L_0x2da8af0; alias, 1 drivers +v0x2bf6a90_0 .net "eq", 0 0, L_0x2daa040; 1 drivers +v0x2bf6b50_0 .net "lt", 0 0, L_0x2daa1c0; 1 drivers +v0x2bf6c10_0 .net "out", 0 0, L_0x2daa430; 1 drivers +v0x2bf6cd0_0 .net "w0", 0 0, L_0x2daa320; 1 drivers +S_0x2bf6f20 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2bc9cd0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12be620/d .functor OR 1, L_0x12be170, L_0x11061d0, C4<0>, C4<0>; -L_0x12be620 .delay 1 (30000,30000,30000) L_0x12be620/d; -v0x1105d60_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers -v0x1105eb0_0 .net "b", 0 0, L_0x12bd780; alias, 1 drivers -v0x1105f70_0 .net "c1", 0 0, L_0x12be170; 1 drivers -v0x1106010_0 .net "c2", 0 0, L_0x11061d0; 1 drivers -v0x11060e0_0 .net "carryin", 0 0, L_0x12bd5b0; alias, 1 drivers -v0x1106260_0 .net "carryout", 0 0, L_0x12be620; 1 drivers -v0x1106300_0 .net "s1", 0 0, L_0x12be0b0; 1 drivers -v0x11063a0_0 .net "sum", 0 0, L_0x12be2d0; 1 drivers -S_0x11051c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1104f70; +L_0x2da9c20/d .functor OR 1, L_0x2da9720, L_0x2bf8180, C4<0>, C4<0>; +L_0x2da9c20 .delay 1 (30000,30000,30000) L_0x2da9c20/d; +v0x2bf7d10_0 .net "a", 0 0, L_0x2db3100; alias, 1 drivers +v0x2bf7e60_0 .net "b", 0 0, L_0x2da8d30; alias, 1 drivers +v0x2bf7f20_0 .net "c1", 0 0, L_0x2da9720; 1 drivers +v0x2bf7fc0_0 .net "c2", 0 0, L_0x2bf8180; 1 drivers +v0x2bf8090_0 .net "carryin", 0 0, L_0x2da8af0; alias, 1 drivers +v0x2bf8210_0 .net "carryout", 0 0, L_0x2da9c20; 1 drivers +v0x2bf82b0_0 .net "s1", 0 0, L_0x2da9660; 1 drivers +v0x2bf8350_0 .net "sum", 0 0, L_0x2da9880; 1 drivers +S_0x2bf7170 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2bf6f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12be0b0/d .functor XOR 1, L_0x12c6f10, L_0x12bd780, C4<0>, C4<0>; -L_0x12be0b0 .delay 1 (30000,30000,30000) L_0x12be0b0/d; -L_0x12be170/d .functor AND 1, L_0x12c6f10, L_0x12bd780, C4<1>, C4<1>; -L_0x12be170 .delay 1 (30000,30000,30000) L_0x12be170/d; -v0x1105420_0 .net "a", 0 0, L_0x12c6f10; alias, 1 drivers -v0x11054e0_0 .net "b", 0 0, L_0x12bd780; alias, 1 drivers -v0x11055a0_0 .net "carryout", 0 0, L_0x12be170; alias, 1 drivers -v0x1105640_0 .net "sum", 0 0, L_0x12be0b0; alias, 1 drivers -S_0x1105770 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1104f70; +L_0x2da9660/d .functor XOR 1, L_0x2db3100, L_0x2da8d30, C4<0>, C4<0>; +L_0x2da9660 .delay 1 (30000,30000,30000) L_0x2da9660/d; +L_0x2da9720/d .functor AND 1, L_0x2db3100, L_0x2da8d30, C4<1>, C4<1>; +L_0x2da9720 .delay 1 (30000,30000,30000) L_0x2da9720/d; +v0x2bf73d0_0 .net "a", 0 0, L_0x2db3100; alias, 1 drivers +v0x2bf7490_0 .net "b", 0 0, L_0x2da8d30; alias, 1 drivers +v0x2bf7550_0 .net "carryout", 0 0, L_0x2da9720; alias, 1 drivers +v0x2bf75f0_0 .net "sum", 0 0, L_0x2da9660; alias, 1 drivers +S_0x2bf7720 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2bf6f20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12be2d0/d .functor XOR 1, L_0x12be0b0, L_0x12bd5b0, C4<0>, C4<0>; -L_0x12be2d0 .delay 1 (30000,30000,30000) L_0x12be2d0/d; -L_0x11061d0/d .functor AND 1, L_0x12be0b0, L_0x12bd5b0, C4<1>, C4<1>; -L_0x11061d0 .delay 1 (30000,30000,30000) L_0x11061d0/d; -v0x11059d0_0 .net "a", 0 0, L_0x12be0b0; alias, 1 drivers -v0x1105aa0_0 .net "b", 0 0, L_0x12bd5b0; alias, 1 drivers -v0x1105b40_0 .net "carryout", 0 0, L_0x11061d0; alias, 1 drivers -v0x1105c10_0 .net "sum", 0 0, L_0x12be2d0; alias, 1 drivers -S_0x11077c0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x10f7a60; - .timescale -9 -12; -L_0x2b0ab3d06578 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d065c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12c6fb0/d .functor OR 1, L_0x2b0ab3d06578, L_0x2b0ab3d065c0, C4<0>, C4<0>; -L_0x12c6fb0 .delay 1 (30000,30000,30000) L_0x12c6fb0/d; -v0x11079b0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06578; 1 drivers -v0x1107a90_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d065c0; 1 drivers -S_0x1107b70 .scope generate, "alu_slices[20]" "alu_slices[20]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1107d80 .param/l "i" 0 3 41, +C4<010100>; -S_0x1107e40 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1107b70; +L_0x2da9880/d .functor XOR 1, L_0x2da9660, L_0x2da8af0, C4<0>, C4<0>; +L_0x2da9880 .delay 1 (30000,30000,30000) L_0x2da9880/d; +L_0x2bf8180/d .functor AND 1, L_0x2da9660, L_0x2da8af0, C4<1>, C4<1>; +L_0x2bf8180 .delay 1 (30000,30000,30000) L_0x2bf8180/d; +v0x2bf7980_0 .net "a", 0 0, L_0x2da9660; alias, 1 drivers +v0x2bf7a50_0 .net "b", 0 0, L_0x2da8af0; alias, 1 drivers +v0x2bf7af0_0 .net "carryout", 0 0, L_0x2bf8180; alias, 1 drivers +v0x2bf7bc0_0 .net "sum", 0 0, L_0x2da9880; alias, 1 drivers +S_0x2bfa3e0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2bc9a00; + .timescale -9 -12; +L_0x2ac6110badb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bae00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dab520/d .functor OR 1, L_0x2ac6110badb8, L_0x2ac6110bae00, C4<0>, C4<0>; +L_0x2dab520 .delay 1 (30000,30000,30000) L_0x2dab520/d; +v0x2bfa5d0_0 .net/2u *"_s0", 0 0, L_0x2ac6110badb8; 1 drivers +v0x2bfa6b0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bae00; 1 drivers +S_0x2bfa790 .scope generate, "alu_slices[20]" "alu_slices[20]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2bfa9a0 .param/l "i" 0 3 39, +C4<010100>; +S_0x2bfaa60 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2bfa790; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -10824,445 +11446,476 @@ S_0x1107e40 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1107b70; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12c7300/d .functor NOT 1, L_0x12d0bf0, C4<0>, C4<0>, C4<0>; -L_0x12c7300 .delay 1 (10000,10000,10000) L_0x12c7300/d; -L_0x12c7460/d .functor NOT 1, L_0x12d0d50, C4<0>, C4<0>, C4<0>; -L_0x12c7460 .delay 1 (10000,10000,10000) L_0x12c7460/d; -L_0x12c84b0/d .functor XOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; -L_0x12c84b0 .delay 1 (30000,30000,30000) L_0x12c84b0/d; -L_0x2b0ab3d06608 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06650 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12c8b60/d .functor OR 1, L_0x2b0ab3d06608, L_0x2b0ab3d06650, C4<0>, C4<0>; -L_0x12c8b60 .delay 1 (30000,30000,30000) L_0x12c8b60/d; -L_0x12c8d60/d .functor AND 1, L_0x12d0bf0, L_0x12d0d50, C4<1>, C4<1>; -L_0x12c8d60 .delay 1 (30000,30000,30000) L_0x12c8d60/d; -L_0x12c8e20/d .functor NAND 1, L_0x12d0bf0, L_0x12d0d50, C4<1>, C4<1>; -L_0x12c8e20 .delay 1 (20000,20000,20000) L_0x12c8e20/d; -L_0x12c8f80/d .functor XOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; -L_0x12c8f80 .delay 1 (20000,20000,20000) L_0x12c8f80/d; -L_0x12c9430/d .functor OR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; -L_0x12c9430 .delay 1 (30000,30000,30000) L_0x12c9430/d; -L_0x12d0af0/d .functor NOT 1, L_0x12cccc0, C4<0>, C4<0>, C4<0>; -L_0x12d0af0 .delay 1 (10000,10000,10000) L_0x12d0af0/d; -v0x1136570_0 .net "A", 0 0, L_0x12d0bf0; 1 drivers -v0x1136630_0 .net "A_", 0 0, L_0x12c7300; 1 drivers -v0x11366f0_0 .net "B", 0 0, L_0x12d0d50; 1 drivers -v0x11367c0_0 .net "B_", 0 0, L_0x12c7460; 1 drivers -v0x1136860_0 .net *"_s12", 0 0, L_0x12c8b60; 1 drivers -v0x1136950_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06608; 1 drivers -v0x1136a10_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06650; 1 drivers -v0x1136af0_0 .net *"_s18", 0 0, L_0x12c8d60; 1 drivers -v0x1136bd0_0 .net *"_s20", 0 0, L_0x12c8e20; 1 drivers -v0x1136d40_0 .net *"_s22", 0 0, L_0x12c8f80; 1 drivers -v0x1136e20_0 .net *"_s24", 0 0, L_0x12c9430; 1 drivers -o0x2b0ab3cd4d08 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1136f00_0 name=_s30 -o0x2b0ab3cd4d38 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1136fe0_0 name=_s32 -v0x11370c0_0 .net *"_s8", 0 0, L_0x12c84b0; 1 drivers -v0x11371a0_0 .net "carryin", 0 0, L_0x12c7070; 1 drivers -v0x1137240_0 .net "carryout", 0 0, L_0x12d0790; 1 drivers -v0x11372e0_0 .net "carryouts", 7 0, L_0x1355060; 1 drivers -v0x1137490_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1137530_0 .net "result", 0 0, L_0x12cccc0; 1 drivers -v0x1137620_0 .net "results", 7 0, L_0x12c9200; 1 drivers -v0x1137730_0 .net "zero", 0 0, L_0x12d0af0; 1 drivers -LS_0x12c9200_0_0 .concat8 [ 1 1 1 1], L_0x12c7980, L_0x12c7fb0, L_0x12c84b0, L_0x12c8b60; -LS_0x12c9200_0_4 .concat8 [ 1 1 1 1], L_0x12c8d60, L_0x12c8e20, L_0x12c8f80, L_0x12c9430; -L_0x12c9200 .concat8 [ 4 4 0 0], LS_0x12c9200_0_0, LS_0x12c9200_0_4; -LS_0x1355060_0_0 .concat [ 1 1 1 1], L_0x12c7c30, L_0x12c8350, o0x2b0ab3cd4d08, L_0x12c89b0; -LS_0x1355060_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd4d38; -L_0x1355060 .concat [ 4 4 0 0], LS_0x1355060_0_0, LS_0x1355060_0_4; -S_0x11080c0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1107e40; +L_0x2db34a0/d .functor NOT 1, L_0x2dbd960, C4<0>, C4<0>, C4<0>; +L_0x2db34a0 .delay 1 (10000,10000,10000) L_0x2db34a0/d; +L_0x2db35b0/d .functor NOT 1, L_0x2dbdac0, C4<0>, C4<0>, C4<0>; +L_0x2db35b0 .delay 1 (10000,10000,10000) L_0x2db35b0/d; +L_0x2db45b0/d .functor XOR 1, L_0x2dbd960, L_0x2dbdac0, C4<0>, C4<0>; +L_0x2db45b0 .delay 1 (30000,30000,30000) L_0x2db45b0/d; +L_0x2ac6110bae48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bae90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db4670/d .functor OR 1, L_0x2ac6110bae48, L_0x2ac6110bae90, C4<0>, C4<0>; +L_0x2db4670 .delay 1 (30000,30000,30000) L_0x2db4670/d; +L_0x2ac6110baed8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110baf20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db4e10/d .functor OR 1, L_0x2ac6110baed8, L_0x2ac6110baf20, C4<0>, C4<0>; +L_0x2db4e10 .delay 1 (30000,30000,30000) L_0x2db4e10/d; +L_0x2db5010/d .functor AND 1, L_0x2dbd960, L_0x2dbdac0, C4<1>, C4<1>; +L_0x2db5010 .delay 1 (30000,30000,30000) L_0x2db5010/d; +L_0x2ac6110baf68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bafb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db50d0/d .functor OR 1, L_0x2ac6110baf68, L_0x2ac6110bafb0, C4<0>, C4<0>; +L_0x2db50d0 .delay 1 (30000,30000,30000) L_0x2db50d0/d; +L_0x2db52d0/d .functor NAND 1, L_0x2dbd960, L_0x2dbdac0, C4<1>, C4<1>; +L_0x2db52d0 .delay 1 (20000,20000,20000) L_0x2db52d0/d; +L_0x2ac6110baff8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb040 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db53e0/d .functor OR 1, L_0x2ac6110baff8, L_0x2ac6110bb040, C4<0>, C4<0>; +L_0x2db53e0 .delay 1 (30000,30000,30000) L_0x2db53e0/d; +L_0x2db5590/d .functor NOR 1, L_0x2dbd960, L_0x2dbdac0, C4<0>, C4<0>; +L_0x2db5590 .delay 1 (20000,20000,20000) L_0x2db5590/d; +L_0x2ac6110bb088 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb0d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db5860/d .functor OR 1, L_0x2ac6110bb088, L_0x2ac6110bb0d0, C4<0>, C4<0>; +L_0x2db5860 .delay 1 (30000,30000,30000) L_0x2db5860/d; +L_0x2db5c60/d .functor OR 1, L_0x2dbd960, L_0x2dbdac0, C4<0>, C4<0>; +L_0x2db5c60 .delay 1 (30000,30000,30000) L_0x2db5c60/d; +L_0x2ac6110bb118 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb160 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db6100/d .functor OR 1, L_0x2ac6110bb118, L_0x2ac6110bb160, C4<0>, C4<0>; +L_0x2db6100 .delay 1 (30000,30000,30000) L_0x2db6100/d; +L_0x2dbd860/d .functor NOT 1, L_0x2db9ac0, C4<0>, C4<0>, C4<0>; +L_0x2dbd860 .delay 1 (10000,10000,10000) L_0x2dbd860/d; +v0x2c09190_0 .net "A", 0 0, L_0x2dbd960; 1 drivers +v0x2c09250_0 .net "A_", 0 0, L_0x2db34a0; 1 drivers +v0x2c09310_0 .net "B", 0 0, L_0x2dbdac0; 1 drivers +v0x2c093e0_0 .net "B_", 0 0, L_0x2db35b0; 1 drivers +v0x2c09480_0 .net *"_s11", 0 0, L_0x2db4670; 1 drivers +v0x2c09570_0 .net/2s *"_s13", 0 0, L_0x2ac6110bae48; 1 drivers +v0x2c09630_0 .net/2s *"_s15", 0 0, L_0x2ac6110bae90; 1 drivers +v0x2c09710_0 .net *"_s19", 0 0, L_0x2db4e10; 1 drivers +v0x2c097f0_0 .net/2s *"_s21", 0 0, L_0x2ac6110baed8; 1 drivers +v0x2c09960_0 .net/2s *"_s23", 0 0, L_0x2ac6110baf20; 1 drivers +v0x2c09a40_0 .net *"_s25", 0 0, L_0x2db5010; 1 drivers +v0x2c09b20_0 .net *"_s28", 0 0, L_0x2db50d0; 1 drivers +v0x2c09c00_0 .net/2s *"_s30", 0 0, L_0x2ac6110baf68; 1 drivers +v0x2c09ce0_0 .net/2s *"_s32", 0 0, L_0x2ac6110bafb0; 1 drivers +v0x2c09dc0_0 .net *"_s34", 0 0, L_0x2db52d0; 1 drivers +v0x2c09ea0_0 .net *"_s37", 0 0, L_0x2db53e0; 1 drivers +v0x2c09f80_0 .net/2s *"_s39", 0 0, L_0x2ac6110baff8; 1 drivers +v0x2c0a130_0 .net/2s *"_s41", 0 0, L_0x2ac6110bb040; 1 drivers +v0x2c0a1d0_0 .net *"_s43", 0 0, L_0x2db5590; 1 drivers +v0x2c0a2b0_0 .net *"_s46", 0 0, L_0x2db5860; 1 drivers +v0x2c0a390_0 .net/2s *"_s48", 0 0, L_0x2ac6110bb088; 1 drivers +v0x2c0a470_0 .net/2s *"_s50", 0 0, L_0x2ac6110bb0d0; 1 drivers +v0x2c0a550_0 .net *"_s52", 0 0, L_0x2db5c60; 1 drivers +v0x2c0a630_0 .net *"_s56", 0 0, L_0x2db6100; 1 drivers +v0x2c0a710_0 .net/2s *"_s59", 0 0, L_0x2ac6110bb118; 1 drivers +v0x2c0a7f0_0 .net/2s *"_s61", 0 0, L_0x2ac6110bb160; 1 drivers +v0x2c0a8d0_0 .net *"_s8", 0 0, L_0x2db45b0; 1 drivers +v0x2c0a9b0_0 .net "carryin", 0 0, L_0x2db3260; 1 drivers +v0x2c0aa50_0 .net "carryout", 0 0, L_0x2dbd500; 1 drivers +v0x2c0aaf0_0 .net "carryouts", 7 0, L_0x2db5d70; 1 drivers +v0x2c0ac00_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c0acc0_0 .net "result", 0 0, L_0x2db9ac0; 1 drivers +v0x2c0adb0_0 .net "results", 7 0, L_0x2db5a30; 1 drivers +v0x2c0a090_0 .net "zero", 0 0, L_0x2dbd860; 1 drivers +LS_0x2db5a30_0_0 .concat8 [ 1 1 1 1], L_0x2db3ad0, L_0x2db4100, L_0x2db45b0, L_0x2db4e10; +LS_0x2db5a30_0_4 .concat8 [ 1 1 1 1], L_0x2db5010, L_0x2db52d0, L_0x2db5590, L_0x2db5c60; +L_0x2db5a30 .concat8 [ 4 4 0 0], LS_0x2db5a30_0_0, LS_0x2db5a30_0_4; +LS_0x2db5d70_0_0 .concat8 [ 1 1 1 1], L_0x2db3d80, L_0x2db4450, L_0x2db4670, L_0x2db4c60; +LS_0x2db5d70_0_4 .concat8 [ 1 1 1 1], L_0x2db50d0, L_0x2db53e0, L_0x2db5860, L_0x2db6100; +L_0x2db5d70 .concat8 [ 4 4 0 0], LS_0x2db5d70_0_0, LS_0x2db5d70_0_4; +S_0x2bface0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2bfaa60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12c7c30/d .functor OR 1, L_0x12c7710, L_0x12c7ad0, C4<0>, C4<0>; -L_0x12c7c30 .delay 1 (30000,30000,30000) L_0x12c7c30/d; -v0x1108ef0_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers -v0x1108fb0_0 .net "b", 0 0, L_0x12d0d50; alias, 1 drivers -v0x1109080_0 .net "c1", 0 0, L_0x12c7710; 1 drivers -v0x1109180_0 .net "c2", 0 0, L_0x12c7ad0; 1 drivers -v0x1109250_0 .net "carryin", 0 0, L_0x12c7070; alias, 1 drivers -v0x1109340_0 .net "carryout", 0 0, L_0x12c7c30; 1 drivers -v0x11093e0_0 .net "s1", 0 0, L_0x12c7650; 1 drivers -v0x11094d0_0 .net "sum", 0 0, L_0x12c7980; 1 drivers -S_0x1108330 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11080c0; +L_0x2db3d80/d .functor OR 1, L_0x2db3860, L_0x2db3c20, C4<0>, C4<0>; +L_0x2db3d80 .delay 1 (30000,30000,30000) L_0x2db3d80/d; +v0x2bfbb10_0 .net "a", 0 0, L_0x2dbd960; alias, 1 drivers +v0x2bfbbd0_0 .net "b", 0 0, L_0x2dbdac0; alias, 1 drivers +v0x2bfbca0_0 .net "c1", 0 0, L_0x2db3860; 1 drivers +v0x2bfbda0_0 .net "c2", 0 0, L_0x2db3c20; 1 drivers +v0x2bfbe70_0 .net "carryin", 0 0, L_0x2db3260; alias, 1 drivers +v0x2bfbf60_0 .net "carryout", 0 0, L_0x2db3d80; 1 drivers +v0x2bfc000_0 .net "s1", 0 0, L_0x2db37a0; 1 drivers +v0x2bfc0f0_0 .net "sum", 0 0, L_0x2db3ad0; 1 drivers +S_0x2bfaf50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2bface0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12c7650/d .functor XOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; -L_0x12c7650 .delay 1 (30000,30000,30000) L_0x12c7650/d; -L_0x12c7710/d .functor AND 1, L_0x12d0bf0, L_0x12d0d50, C4<1>, C4<1>; -L_0x12c7710 .delay 1 (30000,30000,30000) L_0x12c7710/d; -v0x1108590_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers -v0x1108670_0 .net "b", 0 0, L_0x12d0d50; alias, 1 drivers -v0x1108730_0 .net "carryout", 0 0, L_0x12c7710; alias, 1 drivers -v0x11087d0_0 .net "sum", 0 0, L_0x12c7650; alias, 1 drivers -S_0x1108910 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11080c0; +L_0x2db37a0/d .functor XOR 1, L_0x2dbd960, L_0x2dbdac0, C4<0>, C4<0>; +L_0x2db37a0 .delay 1 (30000,30000,30000) L_0x2db37a0/d; +L_0x2db3860/d .functor AND 1, L_0x2dbd960, L_0x2dbdac0, C4<1>, C4<1>; +L_0x2db3860 .delay 1 (30000,30000,30000) L_0x2db3860/d; +v0x2bfb1b0_0 .net "a", 0 0, L_0x2dbd960; alias, 1 drivers +v0x2bfb290_0 .net "b", 0 0, L_0x2dbdac0; alias, 1 drivers +v0x2bfb350_0 .net "carryout", 0 0, L_0x2db3860; alias, 1 drivers +v0x2bfb3f0_0 .net "sum", 0 0, L_0x2db37a0; alias, 1 drivers +S_0x2bfb530 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2bface0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12c7980/d .functor XOR 1, L_0x12c7650, L_0x12c7070, C4<0>, C4<0>; -L_0x12c7980 .delay 1 (30000,30000,30000) L_0x12c7980/d; -L_0x12c7ad0/d .functor AND 1, L_0x12c7650, L_0x12c7070, C4<1>, C4<1>; -L_0x12c7ad0 .delay 1 (30000,30000,30000) L_0x12c7ad0/d; -v0x1108b70_0 .net "a", 0 0, L_0x12c7650; alias, 1 drivers -v0x1108c10_0 .net "b", 0 0, L_0x12c7070; alias, 1 drivers -v0x1108cb0_0 .net "carryout", 0 0, L_0x12c7ad0; alias, 1 drivers -v0x1108d80_0 .net "sum", 0 0, L_0x12c7980; alias, 1 drivers -S_0x11095a0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1107e40; +L_0x2db3ad0/d .functor XOR 1, L_0x2db37a0, L_0x2db3260, C4<0>, C4<0>; +L_0x2db3ad0 .delay 1 (30000,30000,30000) L_0x2db3ad0/d; +L_0x2db3c20/d .functor AND 1, L_0x2db37a0, L_0x2db3260, C4<1>, C4<1>; +L_0x2db3c20 .delay 1 (30000,30000,30000) L_0x2db3c20/d; +v0x2bfb790_0 .net "a", 0 0, L_0x2db37a0; alias, 1 drivers +v0x2bfb830_0 .net "b", 0 0, L_0x2db3260; alias, 1 drivers +v0x2bfb8d0_0 .net "carryout", 0 0, L_0x2db3c20; alias, 1 drivers +v0x2bfb9a0_0 .net "sum", 0 0, L_0x2db3ad0; alias, 1 drivers +S_0x2bfc1c0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2bfaa60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x110e990_0 .net "ands", 7 0, L_0x12ce790; 1 drivers -v0x110eaa0_0 .net "in", 7 0, L_0x1355060; alias, 1 drivers -v0x110eb60_0 .net "out", 0 0, L_0x12d0790; alias, 1 drivers -v0x110ec30_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11097c0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11095a0; +v0x2c015b0_0 .net "ands", 7 0, L_0x2dbb500; 1 drivers +v0x2c016c0_0 .net "in", 7 0, L_0x2db5d70; alias, 1 drivers +v0x2c01780_0 .net "out", 0 0, L_0x2dbd500; alias, 1 drivers +v0x2c01850_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2bfc3e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2bfc1c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x110bef0_0 .net "A", 7 0, L_0x1355060; alias, 1 drivers -v0x110bff0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x110c0b0_0 .net *"_s0", 0 0, L_0x12cd020; 1 drivers -v0x110c170_0 .net *"_s12", 0 0, L_0x12cd990; 1 drivers -v0x110c250_0 .net *"_s16", 0 0, L_0x12cdcf0; 1 drivers -v0x110c380_0 .net *"_s20", 0 0, L_0x12ce000; 1 drivers -v0x110c460_0 .net *"_s24", 0 0, L_0x12ce480; 1 drivers -v0x110c540_0 .net *"_s28", 0 0, L_0x12ce410; 1 drivers -v0x110c620_0 .net *"_s4", 0 0, L_0x12cd330; 1 drivers -v0x110c790_0 .net *"_s8", 0 0, L_0x12cd680; 1 drivers -v0x110c870_0 .net "out", 7 0, L_0x12ce790; alias, 1 drivers -L_0x12cd0e0 .part L_0x1355060, 0, 1; -L_0x12cd240 .part v0x12010b0_0, 0, 1; -L_0x12cd3f0 .part L_0x1355060, 1, 1; -L_0x12cd5e0 .part v0x12010b0_0, 1, 1; -L_0x12cd740 .part L_0x1355060, 2, 1; -L_0x12cd8a0 .part v0x12010b0_0, 2, 1; -L_0x12cda50 .part L_0x1355060, 3, 1; -L_0x12cdbb0 .part v0x12010b0_0, 3, 1; -L_0x12cddb0 .part L_0x1355060, 4, 1; -L_0x12cdf10 .part v0x12010b0_0, 4, 1; -L_0x12ce100 .part L_0x1355060, 5, 1; -L_0x12ce370 .part v0x12010b0_0, 5, 1; -L_0x12ce540 .part L_0x1355060, 6, 1; -L_0x12ce6a0 .part v0x12010b0_0, 6, 1; -LS_0x12ce790_0_0 .concat8 [ 1 1 1 1], L_0x12cd020, L_0x12cd330, L_0x12cd680, L_0x12cd990; -LS_0x12ce790_0_4 .concat8 [ 1 1 1 1], L_0x12cdcf0, L_0x12ce000, L_0x12ce480, L_0x12ce410; -L_0x12ce790 .concat8 [ 4 4 0 0], LS_0x12ce790_0_0, LS_0x12ce790_0_4; -L_0x12ceb50 .part L_0x1355060, 7, 1; -L_0x12ced40 .part v0x12010b0_0, 7, 1; -S_0x1109a20 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x1109c30 .param/l "i" 0 4 54, +C4<00>; -L_0x12cd020/d .functor AND 1, L_0x12cd0e0, L_0x12cd240, C4<1>, C4<1>; -L_0x12cd020 .delay 1 (30000,30000,30000) L_0x12cd020/d; -v0x1109d10_0 .net *"_s0", 0 0, L_0x12cd0e0; 1 drivers -v0x1109df0_0 .net *"_s1", 0 0, L_0x12cd240; 1 drivers -S_0x1109ed0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110a0e0 .param/l "i" 0 4 54, +C4<01>; -L_0x12cd330/d .functor AND 1, L_0x12cd3f0, L_0x12cd5e0, C4<1>, C4<1>; -L_0x12cd330 .delay 1 (30000,30000,30000) L_0x12cd330/d; -v0x110a1a0_0 .net *"_s0", 0 0, L_0x12cd3f0; 1 drivers -v0x110a280_0 .net *"_s1", 0 0, L_0x12cd5e0; 1 drivers -S_0x110a360 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110a570 .param/l "i" 0 4 54, +C4<010>; -L_0x12cd680/d .functor AND 1, L_0x12cd740, L_0x12cd8a0, C4<1>, C4<1>; -L_0x12cd680 .delay 1 (30000,30000,30000) L_0x12cd680/d; -v0x110a610_0 .net *"_s0", 0 0, L_0x12cd740; 1 drivers -v0x110a6f0_0 .net *"_s1", 0 0, L_0x12cd8a0; 1 drivers -S_0x110a7d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110a9e0 .param/l "i" 0 4 54, +C4<011>; -L_0x12cd990/d .functor AND 1, L_0x12cda50, L_0x12cdbb0, C4<1>, C4<1>; -L_0x12cd990 .delay 1 (30000,30000,30000) L_0x12cd990/d; -v0x110aaa0_0 .net *"_s0", 0 0, L_0x12cda50; 1 drivers -v0x110ab80_0 .net *"_s1", 0 0, L_0x12cdbb0; 1 drivers -S_0x110ac60 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110aec0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12cdcf0/d .functor AND 1, L_0x12cddb0, L_0x12cdf10, C4<1>, C4<1>; -L_0x12cdcf0 .delay 1 (30000,30000,30000) L_0x12cdcf0/d; -v0x110af80_0 .net *"_s0", 0 0, L_0x12cddb0; 1 drivers -v0x110b060_0 .net *"_s1", 0 0, L_0x12cdf10; 1 drivers -S_0x110b140 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110b350 .param/l "i" 0 4 54, +C4<0101>; -L_0x12ce000/d .functor AND 1, L_0x12ce100, L_0x12ce370, C4<1>, C4<1>; -L_0x12ce000 .delay 1 (30000,30000,30000) L_0x12ce000/d; -v0x110b410_0 .net *"_s0", 0 0, L_0x12ce100; 1 drivers -v0x110b4f0_0 .net *"_s1", 0 0, L_0x12ce370; 1 drivers -S_0x110b5d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110b7e0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12ce480/d .functor AND 1, L_0x12ce540, L_0x12ce6a0, C4<1>, C4<1>; -L_0x12ce480 .delay 1 (30000,30000,30000) L_0x12ce480/d; -v0x110b8a0_0 .net *"_s0", 0 0, L_0x12ce540; 1 drivers -v0x110b980_0 .net *"_s1", 0 0, L_0x12ce6a0; 1 drivers -S_0x110ba60 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11097c0; - .timescale -9 -12; -P_0x110bc70 .param/l "i" 0 4 54, +C4<0111>; -L_0x12ce410/d .functor AND 1, L_0x12ceb50, L_0x12ced40, C4<1>, C4<1>; -L_0x12ce410 .delay 1 (30000,30000,30000) L_0x12ce410/d; -v0x110bd30_0 .net *"_s0", 0 0, L_0x12ceb50; 1 drivers -v0x110be10_0 .net *"_s1", 0 0, L_0x12ced40; 1 drivers -S_0x110c9d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11095a0; +v0x2bfeb10_0 .net "A", 7 0, L_0x2db5d70; alias, 1 drivers +v0x2bfec10_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2bfecd0_0 .net *"_s0", 0 0, L_0x2db9e20; 1 drivers +v0x2bfed90_0 .net *"_s12", 0 0, L_0x2dba790; 1 drivers +v0x2bfee70_0 .net *"_s16", 0 0, L_0x2dbaaf0; 1 drivers +v0x2bfefa0_0 .net *"_s20", 0 0, L_0x2dbaec0; 1 drivers +v0x2bff080_0 .net *"_s24", 0 0, L_0x2dbb1f0; 1 drivers +v0x2bff160_0 .net *"_s28", 0 0, L_0x2dbb180; 1 drivers +v0x2bff240_0 .net *"_s4", 0 0, L_0x2dba170; 1 drivers +v0x2bff3b0_0 .net *"_s8", 0 0, L_0x2dba480; 1 drivers +v0x2bff490_0 .net "out", 7 0, L_0x2dbb500; alias, 1 drivers +L_0x2db9ee0 .part L_0x2db5d70, 0, 1; +L_0x2dba0d0 .part v0x2cdd2e0_0, 0, 1; +L_0x2dba230 .part L_0x2db5d70, 1, 1; +L_0x2dba390 .part v0x2cdd2e0_0, 1, 1; +L_0x2dba540 .part L_0x2db5d70, 2, 1; +L_0x2dba6a0 .part v0x2cdd2e0_0, 2, 1; +L_0x2dba850 .part L_0x2db5d70, 3, 1; +L_0x2dba9b0 .part v0x2cdd2e0_0, 3, 1; +L_0x2dbabb0 .part L_0x2db5d70, 4, 1; +L_0x2dbae20 .part v0x2cdd2e0_0, 4, 1; +L_0x2dbaf30 .part L_0x2db5d70, 5, 1; +L_0x2dbb090 .part v0x2cdd2e0_0, 5, 1; +L_0x2dbb2b0 .part L_0x2db5d70, 6, 1; +L_0x2dbb410 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dbb500_0_0 .concat8 [ 1 1 1 1], L_0x2db9e20, L_0x2dba170, L_0x2dba480, L_0x2dba790; +LS_0x2dbb500_0_4 .concat8 [ 1 1 1 1], L_0x2dbaaf0, L_0x2dbaec0, L_0x2dbb1f0, L_0x2dbb180; +L_0x2dbb500 .concat8 [ 4 4 0 0], LS_0x2dbb500_0_0, LS_0x2dbb500_0_4; +L_0x2dbb8c0 .part L_0x2db5d70, 7, 1; +L_0x2dbbab0 .part v0x2cdd2e0_0, 7, 1; +S_0x2bfc640 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfc850 .param/l "i" 0 4 54, +C4<00>; +L_0x2db9e20/d .functor AND 1, L_0x2db9ee0, L_0x2dba0d0, C4<1>, C4<1>; +L_0x2db9e20 .delay 1 (30000,30000,30000) L_0x2db9e20/d; +v0x2bfc930_0 .net *"_s0", 0 0, L_0x2db9ee0; 1 drivers +v0x2bfca10_0 .net *"_s1", 0 0, L_0x2dba0d0; 1 drivers +S_0x2bfcaf0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfcd00 .param/l "i" 0 4 54, +C4<01>; +L_0x2dba170/d .functor AND 1, L_0x2dba230, L_0x2dba390, C4<1>, C4<1>; +L_0x2dba170 .delay 1 (30000,30000,30000) L_0x2dba170/d; +v0x2bfcdc0_0 .net *"_s0", 0 0, L_0x2dba230; 1 drivers +v0x2bfcea0_0 .net *"_s1", 0 0, L_0x2dba390; 1 drivers +S_0x2bfcf80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfd190 .param/l "i" 0 4 54, +C4<010>; +L_0x2dba480/d .functor AND 1, L_0x2dba540, L_0x2dba6a0, C4<1>, C4<1>; +L_0x2dba480 .delay 1 (30000,30000,30000) L_0x2dba480/d; +v0x2bfd230_0 .net *"_s0", 0 0, L_0x2dba540; 1 drivers +v0x2bfd310_0 .net *"_s1", 0 0, L_0x2dba6a0; 1 drivers +S_0x2bfd3f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfd600 .param/l "i" 0 4 54, +C4<011>; +L_0x2dba790/d .functor AND 1, L_0x2dba850, L_0x2dba9b0, C4<1>, C4<1>; +L_0x2dba790 .delay 1 (30000,30000,30000) L_0x2dba790/d; +v0x2bfd6c0_0 .net *"_s0", 0 0, L_0x2dba850; 1 drivers +v0x2bfd7a0_0 .net *"_s1", 0 0, L_0x2dba9b0; 1 drivers +S_0x2bfd880 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfdae0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dbaaf0/d .functor AND 1, L_0x2dbabb0, L_0x2dbae20, C4<1>, C4<1>; +L_0x2dbaaf0 .delay 1 (30000,30000,30000) L_0x2dbaaf0/d; +v0x2bfdba0_0 .net *"_s0", 0 0, L_0x2dbabb0; 1 drivers +v0x2bfdc80_0 .net *"_s1", 0 0, L_0x2dbae20; 1 drivers +S_0x2bfdd60 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfdf70 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dbaec0/d .functor AND 1, L_0x2dbaf30, L_0x2dbb090, C4<1>, C4<1>; +L_0x2dbaec0 .delay 1 (30000,30000,30000) L_0x2dbaec0/d; +v0x2bfe030_0 .net *"_s0", 0 0, L_0x2dbaf30; 1 drivers +v0x2bfe110_0 .net *"_s1", 0 0, L_0x2dbb090; 1 drivers +S_0x2bfe1f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfe400 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dbb1f0/d .functor AND 1, L_0x2dbb2b0, L_0x2dbb410, C4<1>, C4<1>; +L_0x2dbb1f0 .delay 1 (30000,30000,30000) L_0x2dbb1f0/d; +v0x2bfe4c0_0 .net *"_s0", 0 0, L_0x2dbb2b0; 1 drivers +v0x2bfe5a0_0 .net *"_s1", 0 0, L_0x2dbb410; 1 drivers +S_0x2bfe680 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2bfc3e0; + .timescale -9 -12; +P_0x2bfe890 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dbb180/d .functor AND 1, L_0x2dbb8c0, L_0x2dbbab0, C4<1>, C4<1>; +L_0x2dbb180 .delay 1 (30000,30000,30000) L_0x2dbb180/d; +v0x2bfe950_0 .net *"_s0", 0 0, L_0x2dbb8c0; 1 drivers +v0x2bfea30_0 .net *"_s1", 0 0, L_0x2dbbab0; 1 drivers +S_0x2bff5f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2bfc1c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12d0790/d .functor OR 1, L_0x12d0850, L_0x12d0a00, C4<0>, C4<0>; -L_0x12d0790 .delay 1 (30000,30000,30000) L_0x12d0790/d; -v0x110e520_0 .net *"_s10", 0 0, L_0x12d0850; 1 drivers -v0x110e600_0 .net *"_s12", 0 0, L_0x12d0a00; 1 drivers -v0x110e6e0_0 .net "in", 7 0, L_0x12ce790; alias, 1 drivers -v0x110e7b0_0 .net "ors", 1 0, L_0x12d05b0; 1 drivers -v0x110e870_0 .net "out", 0 0, L_0x12d0790; alias, 1 drivers -L_0x12cf980 .part L_0x12ce790, 0, 4; -L_0x12d05b0 .concat8 [ 1 1 0 0], L_0x12cf670, L_0x12d02a0; -L_0x12d06f0 .part L_0x12ce790, 4, 4; -L_0x12d0850 .part L_0x12d05b0, 0, 1; -L_0x12d0a00 .part L_0x12d05b0, 1, 1; -S_0x110cb90 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x110c9d0; +L_0x2dbd500/d .functor OR 1, L_0x2dbd5c0, L_0x2dbd770, C4<0>, C4<0>; +L_0x2dbd500 .delay 1 (30000,30000,30000) L_0x2dbd500/d; +v0x2c01140_0 .net *"_s10", 0 0, L_0x2dbd5c0; 1 drivers +v0x2c01220_0 .net *"_s12", 0 0, L_0x2dbd770; 1 drivers +v0x2c01300_0 .net "in", 7 0, L_0x2dbb500; alias, 1 drivers +v0x2c013d0_0 .net "ors", 1 0, L_0x2dbd320; 1 drivers +v0x2c01490_0 .net "out", 0 0, L_0x2dbd500; alias, 1 drivers +L_0x2dbc6f0 .part L_0x2dbb500, 0, 4; +L_0x2dbd320 .concat8 [ 1 1 0 0], L_0x2dbc3e0, L_0x2dbd010; +L_0x2dbd460 .part L_0x2dbb500, 4, 4; +L_0x2dbd5c0 .part L_0x2dbd320, 0, 1; +L_0x2dbd770 .part L_0x2dbd320, 1, 1; +S_0x2bff7b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2bff5f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12cee30/d .functor OR 1, L_0x12ceef0, L_0x12cf050, C4<0>, C4<0>; -L_0x12cee30 .delay 1 (30000,30000,30000) L_0x12cee30/d; -L_0x12cf280/d .functor OR 1, L_0x12cf390, L_0x12cf4f0, C4<0>, C4<0>; -L_0x12cf280 .delay 1 (30000,30000,30000) L_0x12cf280/d; -L_0x12cf670/d .functor OR 1, L_0x12cf6e0, L_0x12cf890, C4<0>, C4<0>; -L_0x12cf670 .delay 1 (30000,30000,30000) L_0x12cf670/d; -v0x110cde0_0 .net *"_s0", 0 0, L_0x12cee30; 1 drivers -v0x110cee0_0 .net *"_s10", 0 0, L_0x12cf390; 1 drivers -v0x110cfc0_0 .net *"_s12", 0 0, L_0x12cf4f0; 1 drivers -v0x110d080_0 .net *"_s14", 0 0, L_0x12cf6e0; 1 drivers -v0x110d160_0 .net *"_s16", 0 0, L_0x12cf890; 1 drivers -v0x110d290_0 .net *"_s3", 0 0, L_0x12ceef0; 1 drivers -v0x110d370_0 .net *"_s5", 0 0, L_0x12cf050; 1 drivers -v0x110d450_0 .net *"_s6", 0 0, L_0x12cf280; 1 drivers -v0x110d530_0 .net "in", 3 0, L_0x12cf980; 1 drivers -v0x110d6a0_0 .net "ors", 1 0, L_0x12cf190; 1 drivers -v0x110d780_0 .net "out", 0 0, L_0x12cf670; 1 drivers -L_0x12ceef0 .part L_0x12cf980, 0, 1; -L_0x12cf050 .part L_0x12cf980, 1, 1; -L_0x12cf190 .concat8 [ 1 1 0 0], L_0x12cee30, L_0x12cf280; -L_0x12cf390 .part L_0x12cf980, 2, 1; -L_0x12cf4f0 .part L_0x12cf980, 3, 1; -L_0x12cf6e0 .part L_0x12cf190, 0, 1; -L_0x12cf890 .part L_0x12cf190, 1, 1; -S_0x110d8a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x110c9d0; +L_0x2dbbba0/d .functor OR 1, L_0x2dbbc60, L_0x2dbbdc0, C4<0>, C4<0>; +L_0x2dbbba0 .delay 1 (30000,30000,30000) L_0x2dbbba0/d; +L_0x2dbbff0/d .functor OR 1, L_0x2dbc100, L_0x2dbc260, C4<0>, C4<0>; +L_0x2dbbff0 .delay 1 (30000,30000,30000) L_0x2dbbff0/d; +L_0x2dbc3e0/d .functor OR 1, L_0x2dbc450, L_0x2dbc600, C4<0>, C4<0>; +L_0x2dbc3e0 .delay 1 (30000,30000,30000) L_0x2dbc3e0/d; +v0x2bffa00_0 .net *"_s0", 0 0, L_0x2dbbba0; 1 drivers +v0x2bffb00_0 .net *"_s10", 0 0, L_0x2dbc100; 1 drivers +v0x2bffbe0_0 .net *"_s12", 0 0, L_0x2dbc260; 1 drivers +v0x2bffca0_0 .net *"_s14", 0 0, L_0x2dbc450; 1 drivers +v0x2bffd80_0 .net *"_s16", 0 0, L_0x2dbc600; 1 drivers +v0x2bffeb0_0 .net *"_s3", 0 0, L_0x2dbbc60; 1 drivers +v0x2bfff90_0 .net *"_s5", 0 0, L_0x2dbbdc0; 1 drivers +v0x2c00070_0 .net *"_s6", 0 0, L_0x2dbbff0; 1 drivers +v0x2c00150_0 .net "in", 3 0, L_0x2dbc6f0; 1 drivers +v0x2c002c0_0 .net "ors", 1 0, L_0x2dbbf00; 1 drivers +v0x2c003a0_0 .net "out", 0 0, L_0x2dbc3e0; 1 drivers +L_0x2dbbc60 .part L_0x2dbc6f0, 0, 1; +L_0x2dbbdc0 .part L_0x2dbc6f0, 1, 1; +L_0x2dbbf00 .concat8 [ 1 1 0 0], L_0x2dbbba0, L_0x2dbbff0; +L_0x2dbc100 .part L_0x2dbc6f0, 2, 1; +L_0x2dbc260 .part L_0x2dbc6f0, 3, 1; +L_0x2dbc450 .part L_0x2dbbf00, 0, 1; +L_0x2dbc600 .part L_0x2dbbf00, 1, 1; +S_0x2c004c0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2bff5f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12cfab0/d .functor OR 1, L_0x12cfb20, L_0x12cfc80, C4<0>, C4<0>; -L_0x12cfab0 .delay 1 (30000,30000,30000) L_0x12cfab0/d; -L_0x12cfeb0/d .functor OR 1, L_0x12cffc0, L_0x12d0120, C4<0>, C4<0>; -L_0x12cfeb0 .delay 1 (30000,30000,30000) L_0x12cfeb0/d; -L_0x12d02a0/d .functor OR 1, L_0x12d0310, L_0x12d04c0, C4<0>, C4<0>; -L_0x12d02a0 .delay 1 (30000,30000,30000) L_0x12d02a0/d; -v0x110da60_0 .net *"_s0", 0 0, L_0x12cfab0; 1 drivers -v0x110db60_0 .net *"_s10", 0 0, L_0x12cffc0; 1 drivers -v0x110dc40_0 .net *"_s12", 0 0, L_0x12d0120; 1 drivers -v0x110dd00_0 .net *"_s14", 0 0, L_0x12d0310; 1 drivers -v0x110dde0_0 .net *"_s16", 0 0, L_0x12d04c0; 1 drivers -v0x110df10_0 .net *"_s3", 0 0, L_0x12cfb20; 1 drivers -v0x110dff0_0 .net *"_s5", 0 0, L_0x12cfc80; 1 drivers -v0x110e0d0_0 .net *"_s6", 0 0, L_0x12cfeb0; 1 drivers -v0x110e1b0_0 .net "in", 3 0, L_0x12d06f0; 1 drivers -v0x110e320_0 .net "ors", 1 0, L_0x12cfdc0; 1 drivers -v0x110e400_0 .net "out", 0 0, L_0x12d02a0; 1 drivers -L_0x12cfb20 .part L_0x12d06f0, 0, 1; -L_0x12cfc80 .part L_0x12d06f0, 1, 1; -L_0x12cfdc0 .concat8 [ 1 1 0 0], L_0x12cfab0, L_0x12cfeb0; -L_0x12cffc0 .part L_0x12d06f0, 2, 1; -L_0x12d0120 .part L_0x12d06f0, 3, 1; -L_0x12d0310 .part L_0x12cfdc0, 0, 1; -L_0x12d04c0 .part L_0x12cfdc0, 1, 1; -S_0x110ed10 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1107e40; +L_0x2dbc820/d .functor OR 1, L_0x2dbc890, L_0x2dbc9f0, C4<0>, C4<0>; +L_0x2dbc820 .delay 1 (30000,30000,30000) L_0x2dbc820/d; +L_0x2dbcc20/d .functor OR 1, L_0x2dbcd30, L_0x2dbce90, C4<0>, C4<0>; +L_0x2dbcc20 .delay 1 (30000,30000,30000) L_0x2dbcc20/d; +L_0x2dbd010/d .functor OR 1, L_0x2dbd080, L_0x2dbd230, C4<0>, C4<0>; +L_0x2dbd010 .delay 1 (30000,30000,30000) L_0x2dbd010/d; +v0x2c00680_0 .net *"_s0", 0 0, L_0x2dbc820; 1 drivers +v0x2c00780_0 .net *"_s10", 0 0, L_0x2dbcd30; 1 drivers +v0x2c00860_0 .net *"_s12", 0 0, L_0x2dbce90; 1 drivers +v0x2c00920_0 .net *"_s14", 0 0, L_0x2dbd080; 1 drivers +v0x2c00a00_0 .net *"_s16", 0 0, L_0x2dbd230; 1 drivers +v0x2c00b30_0 .net *"_s3", 0 0, L_0x2dbc890; 1 drivers +v0x2c00c10_0 .net *"_s5", 0 0, L_0x2dbc9f0; 1 drivers +v0x2c00cf0_0 .net *"_s6", 0 0, L_0x2dbcc20; 1 drivers +v0x2c00dd0_0 .net "in", 3 0, L_0x2dbd460; 1 drivers +v0x2c00f40_0 .net "ors", 1 0, L_0x2dbcb30; 1 drivers +v0x2c01020_0 .net "out", 0 0, L_0x2dbd010; 1 drivers +L_0x2dbc890 .part L_0x2dbd460, 0, 1; +L_0x2dbc9f0 .part L_0x2dbd460, 1, 1; +L_0x2dbcb30 .concat8 [ 1 1 0 0], L_0x2dbc820, L_0x2dbcc20; +L_0x2dbcd30 .part L_0x2dbd460, 2, 1; +L_0x2dbce90 .part L_0x2dbd460, 3, 1; +L_0x2dbd080 .part L_0x2dbcb30, 0, 1; +L_0x2dbd230 .part L_0x2dbcb30, 1, 1; +S_0x2c01930 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2bfaa60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1134140_0 .net "ands", 7 0, L_0x12cacc0; 1 drivers -v0x1134250_0 .net "in", 7 0, L_0x12c9200; alias, 1 drivers -v0x1134310_0 .net "out", 0 0, L_0x12cccc0; alias, 1 drivers -v0x11343e0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x110ef60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x110ed10; +v0x2c06d60_0 .net "ands", 7 0, L_0x2db7ac0; 1 drivers +v0x2c06e70_0 .net "in", 7 0, L_0x2db5a30; alias, 1 drivers +v0x2c06f30_0 .net "out", 0 0, L_0x2db9ac0; alias, 1 drivers +v0x2c07000_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c01b80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c01930; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11116a0_0 .net "A", 7 0, L_0x12c9200; alias, 1 drivers -v0x11117a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1111860_0 .net *"_s0", 0 0, L_0x12c9590; 1 drivers -v0x1111920_0 .net *"_s12", 0 0, L_0x12c9f50; 1 drivers -v0x1111a00_0 .net *"_s16", 0 0, L_0x12ca2b0; 1 drivers -v0x1111b30_0 .net *"_s20", 0 0, L_0x12ca680; 1 drivers -v0x1111c10_0 .net *"_s24", 0 0, L_0x12ca9b0; 1 drivers -v0x1111cf0_0 .net *"_s28", 0 0, L_0x12ca940; 1 drivers -v0x1111dd0_0 .net *"_s4", 0 0, L_0x12c9930; 1 drivers -v0x1111f40_0 .net *"_s8", 0 0, L_0x12c9c40; 1 drivers -v0x1112020_0 .net "out", 7 0, L_0x12cacc0; alias, 1 drivers -L_0x12c96a0 .part L_0x12c9200, 0, 1; -L_0x12c9890 .part v0x12010b0_0, 0, 1; -L_0x12c99f0 .part L_0x12c9200, 1, 1; -L_0x12c9b50 .part v0x12010b0_0, 1, 1; -L_0x12c9d00 .part L_0x12c9200, 2, 1; -L_0x12c9e60 .part v0x12010b0_0, 2, 1; -L_0x12ca010 .part L_0x12c9200, 3, 1; -L_0x12ca170 .part v0x12010b0_0, 3, 1; -L_0x12ca370 .part L_0x12c9200, 4, 1; -L_0x12ca5e0 .part v0x12010b0_0, 4, 1; -L_0x12ca6f0 .part L_0x12c9200, 5, 1; -L_0x12ca850 .part v0x12010b0_0, 5, 1; -L_0x12caa70 .part L_0x12c9200, 6, 1; -L_0x12cabd0 .part v0x12010b0_0, 6, 1; -LS_0x12cacc0_0_0 .concat8 [ 1 1 1 1], L_0x12c9590, L_0x12c9930, L_0x12c9c40, L_0x12c9f50; -LS_0x12cacc0_0_4 .concat8 [ 1 1 1 1], L_0x12ca2b0, L_0x12ca680, L_0x12ca9b0, L_0x12ca940; -L_0x12cacc0 .concat8 [ 4 4 0 0], LS_0x12cacc0_0_0, LS_0x12cacc0_0_4; -L_0x12cb080 .part L_0x12c9200, 7, 1; -L_0x12cb270 .part v0x12010b0_0, 7, 1; -S_0x110f1a0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x110f3b0 .param/l "i" 0 4 54, +C4<00>; -L_0x12c9590/d .functor AND 1, L_0x12c96a0, L_0x12c9890, C4<1>, C4<1>; -L_0x12c9590 .delay 1 (30000,30000,30000) L_0x12c9590/d; -v0x110f490_0 .net *"_s0", 0 0, L_0x12c96a0; 1 drivers -v0x110f570_0 .net *"_s1", 0 0, L_0x12c9890; 1 drivers -S_0x110f650 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x110f860 .param/l "i" 0 4 54, +C4<01>; -L_0x12c9930/d .functor AND 1, L_0x12c99f0, L_0x12c9b50, C4<1>, C4<1>; -L_0x12c9930 .delay 1 (30000,30000,30000) L_0x12c9930/d; -v0x110f920_0 .net *"_s0", 0 0, L_0x12c99f0; 1 drivers -v0x110fa00_0 .net *"_s1", 0 0, L_0x12c9b50; 1 drivers -S_0x110fae0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x110fd20 .param/l "i" 0 4 54, +C4<010>; -L_0x12c9c40/d .functor AND 1, L_0x12c9d00, L_0x12c9e60, C4<1>, C4<1>; -L_0x12c9c40 .delay 1 (30000,30000,30000) L_0x12c9c40/d; -v0x110fdc0_0 .net *"_s0", 0 0, L_0x12c9d00; 1 drivers -v0x110fea0_0 .net *"_s1", 0 0, L_0x12c9e60; 1 drivers -S_0x110ff80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x1110190 .param/l "i" 0 4 54, +C4<011>; -L_0x12c9f50/d .functor AND 1, L_0x12ca010, L_0x12ca170, C4<1>, C4<1>; -L_0x12c9f50 .delay 1 (30000,30000,30000) L_0x12c9f50/d; -v0x1110250_0 .net *"_s0", 0 0, L_0x12ca010; 1 drivers -v0x1110330_0 .net *"_s1", 0 0, L_0x12ca170; 1 drivers -S_0x1110410 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x1110670 .param/l "i" 0 4 54, +C4<0100>; -L_0x12ca2b0/d .functor AND 1, L_0x12ca370, L_0x12ca5e0, C4<1>, C4<1>; -L_0x12ca2b0 .delay 1 (30000,30000,30000) L_0x12ca2b0/d; -v0x1110730_0 .net *"_s0", 0 0, L_0x12ca370; 1 drivers -v0x1110810_0 .net *"_s1", 0 0, L_0x12ca5e0; 1 drivers -S_0x11108f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x1110b00 .param/l "i" 0 4 54, +C4<0101>; -L_0x12ca680/d .functor AND 1, L_0x12ca6f0, L_0x12ca850, C4<1>, C4<1>; -L_0x12ca680 .delay 1 (30000,30000,30000) L_0x12ca680/d; -v0x1110bc0_0 .net *"_s0", 0 0, L_0x12ca6f0; 1 drivers -v0x1110ca0_0 .net *"_s1", 0 0, L_0x12ca850; 1 drivers -S_0x1110d80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x1110f90 .param/l "i" 0 4 54, +C4<0110>; -L_0x12ca9b0/d .functor AND 1, L_0x12caa70, L_0x12cabd0, C4<1>, C4<1>; -L_0x12ca9b0 .delay 1 (30000,30000,30000) L_0x12ca9b0/d; -v0x1111050_0 .net *"_s0", 0 0, L_0x12caa70; 1 drivers -v0x1111130_0 .net *"_s1", 0 0, L_0x12cabd0; 1 drivers -S_0x1111210 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x110ef60; - .timescale -9 -12; -P_0x1111420 .param/l "i" 0 4 54, +C4<0111>; -L_0x12ca940/d .functor AND 1, L_0x12cb080, L_0x12cb270, C4<1>, C4<1>; -L_0x12ca940 .delay 1 (30000,30000,30000) L_0x12ca940/d; -v0x11114e0_0 .net *"_s0", 0 0, L_0x12cb080; 1 drivers -v0x11115c0_0 .net *"_s1", 0 0, L_0x12cb270; 1 drivers -S_0x1112180 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x110ed10; +v0x2c042c0_0 .net "A", 7 0, L_0x2db5a30; alias, 1 drivers +v0x2c043c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c04480_0 .net *"_s0", 0 0, L_0x2db62b0; 1 drivers +v0x2c04540_0 .net *"_s12", 0 0, L_0x2db6c70; 1 drivers +v0x2c04620_0 .net *"_s16", 0 0, L_0x2db6fd0; 1 drivers +v0x2c04750_0 .net *"_s20", 0 0, L_0x2db7400; 1 drivers +v0x2c04830_0 .net *"_s24", 0 0, L_0x2db7730; 1 drivers +v0x2c04910_0 .net *"_s28", 0 0, L_0x2db76c0; 1 drivers +v0x2c049f0_0 .net *"_s4", 0 0, L_0x2db6650; 1 drivers +v0x2c04b60_0 .net *"_s8", 0 0, L_0x2db6960; 1 drivers +v0x2c04c40_0 .net "out", 7 0, L_0x2db7ac0; alias, 1 drivers +L_0x2db63c0 .part L_0x2db5a30, 0, 1; +L_0x2db65b0 .part v0x2cdd2e0_0, 0, 1; +L_0x2db6710 .part L_0x2db5a30, 1, 1; +L_0x2db6870 .part v0x2cdd2e0_0, 1, 1; +L_0x2db6a20 .part L_0x2db5a30, 2, 1; +L_0x2db6b80 .part v0x2cdd2e0_0, 2, 1; +L_0x2db6d30 .part L_0x2db5a30, 3, 1; +L_0x2db6e90 .part v0x2cdd2e0_0, 3, 1; +L_0x2db7090 .part L_0x2db5a30, 4, 1; +L_0x2db7300 .part v0x2cdd2e0_0, 4, 1; +L_0x2db7470 .part L_0x2db5a30, 5, 1; +L_0x2db75d0 .part v0x2cdd2e0_0, 5, 1; +L_0x2db77f0 .part L_0x2db5a30, 6, 1; +L_0x2db7950 .part v0x2cdd2e0_0, 6, 1; +LS_0x2db7ac0_0_0 .concat8 [ 1 1 1 1], L_0x2db62b0, L_0x2db6650, L_0x2db6960, L_0x2db6c70; +LS_0x2db7ac0_0_4 .concat8 [ 1 1 1 1], L_0x2db6fd0, L_0x2db7400, L_0x2db7730, L_0x2db76c0; +L_0x2db7ac0 .concat8 [ 4 4 0 0], LS_0x2db7ac0_0_0, LS_0x2db7ac0_0_4; +L_0x2db7e80 .part L_0x2db5a30, 7, 1; +L_0x2db8070 .part v0x2cdd2e0_0, 7, 1; +S_0x2c01dc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c01fd0 .param/l "i" 0 4 54, +C4<00>; +L_0x2db62b0/d .functor AND 1, L_0x2db63c0, L_0x2db65b0, C4<1>, C4<1>; +L_0x2db62b0 .delay 1 (30000,30000,30000) L_0x2db62b0/d; +v0x2c020b0_0 .net *"_s0", 0 0, L_0x2db63c0; 1 drivers +v0x2c02190_0 .net *"_s1", 0 0, L_0x2db65b0; 1 drivers +S_0x2c02270 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c02480 .param/l "i" 0 4 54, +C4<01>; +L_0x2db6650/d .functor AND 1, L_0x2db6710, L_0x2db6870, C4<1>, C4<1>; +L_0x2db6650 .delay 1 (30000,30000,30000) L_0x2db6650/d; +v0x2c02540_0 .net *"_s0", 0 0, L_0x2db6710; 1 drivers +v0x2c02620_0 .net *"_s1", 0 0, L_0x2db6870; 1 drivers +S_0x2c02700 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c02940 .param/l "i" 0 4 54, +C4<010>; +L_0x2db6960/d .functor AND 1, L_0x2db6a20, L_0x2db6b80, C4<1>, C4<1>; +L_0x2db6960 .delay 1 (30000,30000,30000) L_0x2db6960/d; +v0x2c029e0_0 .net *"_s0", 0 0, L_0x2db6a20; 1 drivers +v0x2c02ac0_0 .net *"_s1", 0 0, L_0x2db6b80; 1 drivers +S_0x2c02ba0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c02db0 .param/l "i" 0 4 54, +C4<011>; +L_0x2db6c70/d .functor AND 1, L_0x2db6d30, L_0x2db6e90, C4<1>, C4<1>; +L_0x2db6c70 .delay 1 (30000,30000,30000) L_0x2db6c70/d; +v0x2c02e70_0 .net *"_s0", 0 0, L_0x2db6d30; 1 drivers +v0x2c02f50_0 .net *"_s1", 0 0, L_0x2db6e90; 1 drivers +S_0x2c03030 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c03290 .param/l "i" 0 4 54, +C4<0100>; +L_0x2db6fd0/d .functor AND 1, L_0x2db7090, L_0x2db7300, C4<1>, C4<1>; +L_0x2db6fd0 .delay 1 (30000,30000,30000) L_0x2db6fd0/d; +v0x2c03350_0 .net *"_s0", 0 0, L_0x2db7090; 1 drivers +v0x2c03430_0 .net *"_s1", 0 0, L_0x2db7300; 1 drivers +S_0x2c03510 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c03720 .param/l "i" 0 4 54, +C4<0101>; +L_0x2db7400/d .functor AND 1, L_0x2db7470, L_0x2db75d0, C4<1>, C4<1>; +L_0x2db7400 .delay 1 (30000,30000,30000) L_0x2db7400/d; +v0x2c037e0_0 .net *"_s0", 0 0, L_0x2db7470; 1 drivers +v0x2c038c0_0 .net *"_s1", 0 0, L_0x2db75d0; 1 drivers +S_0x2c039a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c03bb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2db7730/d .functor AND 1, L_0x2db77f0, L_0x2db7950, C4<1>, C4<1>; +L_0x2db7730 .delay 1 (30000,30000,30000) L_0x2db7730/d; +v0x2c03c70_0 .net *"_s0", 0 0, L_0x2db77f0; 1 drivers +v0x2c03d50_0 .net *"_s1", 0 0, L_0x2db7950; 1 drivers +S_0x2c03e30 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c01b80; + .timescale -9 -12; +P_0x2c04040 .param/l "i" 0 4 54, +C4<0111>; +L_0x2db76c0/d .functor AND 1, L_0x2db7e80, L_0x2db8070, C4<1>, C4<1>; +L_0x2db76c0 .delay 1 (30000,30000,30000) L_0x2db76c0/d; +v0x2c04100_0 .net *"_s0", 0 0, L_0x2db7e80; 1 drivers +v0x2c041e0_0 .net *"_s1", 0 0, L_0x2db8070; 1 drivers +S_0x2c04da0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c01930; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12cccc0/d .functor OR 1, L_0x12ccd80, L_0x12ccf30, C4<0>, C4<0>; -L_0x12cccc0 .delay 1 (30000,30000,30000) L_0x12cccc0/d; -v0x1133cd0_0 .net *"_s10", 0 0, L_0x12ccd80; 1 drivers -v0x1133db0_0 .net *"_s12", 0 0, L_0x12ccf30; 1 drivers -v0x1133e90_0 .net "in", 7 0, L_0x12cacc0; alias, 1 drivers -v0x1133f60_0 .net "ors", 1 0, L_0x12ccae0; 1 drivers -v0x1134020_0 .net "out", 0 0, L_0x12cccc0; alias, 1 drivers -L_0x12cbeb0 .part L_0x12cacc0, 0, 4; -L_0x12ccae0 .concat8 [ 1 1 0 0], L_0x12cbba0, L_0x12cc7d0; -L_0x12ccc20 .part L_0x12cacc0, 4, 4; -L_0x12ccd80 .part L_0x12ccae0, 0, 1; -L_0x12ccf30 .part L_0x12ccae0, 1, 1; -S_0x1112340 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1112180; +L_0x2db9ac0/d .functor OR 1, L_0x2db9b80, L_0x2db9d30, C4<0>, C4<0>; +L_0x2db9ac0 .delay 1 (30000,30000,30000) L_0x2db9ac0/d; +v0x2c068f0_0 .net *"_s10", 0 0, L_0x2db9b80; 1 drivers +v0x2c069d0_0 .net *"_s12", 0 0, L_0x2db9d30; 1 drivers +v0x2c06ab0_0 .net "in", 7 0, L_0x2db7ac0; alias, 1 drivers +v0x2c06b80_0 .net "ors", 1 0, L_0x2db98e0; 1 drivers +v0x2c06c40_0 .net "out", 0 0, L_0x2db9ac0; alias, 1 drivers +L_0x2db8cb0 .part L_0x2db7ac0, 0, 4; +L_0x2db98e0 .concat8 [ 1 1 0 0], L_0x2db89a0, L_0x2db95d0; +L_0x2db9a20 .part L_0x2db7ac0, 4, 4; +L_0x2db9b80 .part L_0x2db98e0, 0, 1; +L_0x2db9d30 .part L_0x2db98e0, 1, 1; +S_0x2c04f60 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c04da0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12cb360/d .functor OR 1, L_0x12cb420, L_0x12cb580, C4<0>, C4<0>; -L_0x12cb360 .delay 1 (30000,30000,30000) L_0x12cb360/d; -L_0x12cb7b0/d .functor OR 1, L_0x12cb8c0, L_0x12cba20, C4<0>, C4<0>; -L_0x12cb7b0 .delay 1 (30000,30000,30000) L_0x12cb7b0/d; -L_0x12cbba0/d .functor OR 1, L_0x12cbc10, L_0x12cbdc0, C4<0>, C4<0>; -L_0x12cbba0 .delay 1 (30000,30000,30000) L_0x12cbba0/d; -v0x1112590_0 .net *"_s0", 0 0, L_0x12cb360; 1 drivers -v0x1112690_0 .net *"_s10", 0 0, L_0x12cb8c0; 1 drivers -v0x1112770_0 .net *"_s12", 0 0, L_0x12cba20; 1 drivers -v0x1112830_0 .net *"_s14", 0 0, L_0x12cbc10; 1 drivers -v0x1132910_0 .net *"_s16", 0 0, L_0x12cbdc0; 1 drivers -v0x1132a40_0 .net *"_s3", 0 0, L_0x12cb420; 1 drivers -v0x1132b20_0 .net *"_s5", 0 0, L_0x12cb580; 1 drivers -v0x1132c00_0 .net *"_s6", 0 0, L_0x12cb7b0; 1 drivers -v0x1132ce0_0 .net "in", 3 0, L_0x12cbeb0; 1 drivers -v0x1132e50_0 .net "ors", 1 0, L_0x12cb6c0; 1 drivers -v0x1132f30_0 .net "out", 0 0, L_0x12cbba0; 1 drivers -L_0x12cb420 .part L_0x12cbeb0, 0, 1; -L_0x12cb580 .part L_0x12cbeb0, 1, 1; -L_0x12cb6c0 .concat8 [ 1 1 0 0], L_0x12cb360, L_0x12cb7b0; -L_0x12cb8c0 .part L_0x12cbeb0, 2, 1; -L_0x12cba20 .part L_0x12cbeb0, 3, 1; -L_0x12cbc10 .part L_0x12cb6c0, 0, 1; -L_0x12cbdc0 .part L_0x12cb6c0, 1, 1; -S_0x1133050 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1112180; +L_0x2db8160/d .functor OR 1, L_0x2db8220, L_0x2db8380, C4<0>, C4<0>; +L_0x2db8160 .delay 1 (30000,30000,30000) L_0x2db8160/d; +L_0x2db85b0/d .functor OR 1, L_0x2db86c0, L_0x2db8820, C4<0>, C4<0>; +L_0x2db85b0 .delay 1 (30000,30000,30000) L_0x2db85b0/d; +L_0x2db89a0/d .functor OR 1, L_0x2db8a10, L_0x2db8bc0, C4<0>, C4<0>; +L_0x2db89a0 .delay 1 (30000,30000,30000) L_0x2db89a0/d; +v0x2c051b0_0 .net *"_s0", 0 0, L_0x2db8160; 1 drivers +v0x2c052b0_0 .net *"_s10", 0 0, L_0x2db86c0; 1 drivers +v0x2c05390_0 .net *"_s12", 0 0, L_0x2db8820; 1 drivers +v0x2c05450_0 .net *"_s14", 0 0, L_0x2db8a10; 1 drivers +v0x2c05530_0 .net *"_s16", 0 0, L_0x2db8bc0; 1 drivers +v0x2c05660_0 .net *"_s3", 0 0, L_0x2db8220; 1 drivers +v0x2c05740_0 .net *"_s5", 0 0, L_0x2db8380; 1 drivers +v0x2c05820_0 .net *"_s6", 0 0, L_0x2db85b0; 1 drivers +v0x2c05900_0 .net "in", 3 0, L_0x2db8cb0; 1 drivers +v0x2c05a70_0 .net "ors", 1 0, L_0x2db84c0; 1 drivers +v0x2c05b50_0 .net "out", 0 0, L_0x2db89a0; 1 drivers +L_0x2db8220 .part L_0x2db8cb0, 0, 1; +L_0x2db8380 .part L_0x2db8cb0, 1, 1; +L_0x2db84c0 .concat8 [ 1 1 0 0], L_0x2db8160, L_0x2db85b0; +L_0x2db86c0 .part L_0x2db8cb0, 2, 1; +L_0x2db8820 .part L_0x2db8cb0, 3, 1; +L_0x2db8a10 .part L_0x2db84c0, 0, 1; +L_0x2db8bc0 .part L_0x2db84c0, 1, 1; +S_0x2c05c70 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c04da0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12cbfe0/d .functor OR 1, L_0x12cc050, L_0x12cc1b0, C4<0>, C4<0>; -L_0x12cbfe0 .delay 1 (30000,30000,30000) L_0x12cbfe0/d; -L_0x12cc3e0/d .functor OR 1, L_0x12cc4f0, L_0x12cc650, C4<0>, C4<0>; -L_0x12cc3e0 .delay 1 (30000,30000,30000) L_0x12cc3e0/d; -L_0x12cc7d0/d .functor OR 1, L_0x12cc840, L_0x12cc9f0, C4<0>, C4<0>; -L_0x12cc7d0 .delay 1 (30000,30000,30000) L_0x12cc7d0/d; -v0x1133210_0 .net *"_s0", 0 0, L_0x12cbfe0; 1 drivers -v0x1133310_0 .net *"_s10", 0 0, L_0x12cc4f0; 1 drivers -v0x11333f0_0 .net *"_s12", 0 0, L_0x12cc650; 1 drivers -v0x11334b0_0 .net *"_s14", 0 0, L_0x12cc840; 1 drivers -v0x1133590_0 .net *"_s16", 0 0, L_0x12cc9f0; 1 drivers -v0x11336c0_0 .net *"_s3", 0 0, L_0x12cc050; 1 drivers -v0x11337a0_0 .net *"_s5", 0 0, L_0x12cc1b0; 1 drivers -v0x1133880_0 .net *"_s6", 0 0, L_0x12cc3e0; 1 drivers -v0x1133960_0 .net "in", 3 0, L_0x12ccc20; 1 drivers -v0x1133ad0_0 .net "ors", 1 0, L_0x12cc2f0; 1 drivers -v0x1133bb0_0 .net "out", 0 0, L_0x12cc7d0; 1 drivers -L_0x12cc050 .part L_0x12ccc20, 0, 1; -L_0x12cc1b0 .part L_0x12ccc20, 1, 1; -L_0x12cc2f0 .concat8 [ 1 1 0 0], L_0x12cbfe0, L_0x12cc3e0; -L_0x12cc4f0 .part L_0x12ccc20, 2, 1; -L_0x12cc650 .part L_0x12ccc20, 3, 1; -L_0x12cc840 .part L_0x12cc2f0, 0, 1; -L_0x12cc9f0 .part L_0x12cc2f0, 1, 1; -S_0x11344c0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1107e40; +L_0x2db8de0/d .functor OR 1, L_0x2db8e50, L_0x2db8fb0, C4<0>, C4<0>; +L_0x2db8de0 .delay 1 (30000,30000,30000) L_0x2db8de0/d; +L_0x2db91e0/d .functor OR 1, L_0x2db92f0, L_0x2db9450, C4<0>, C4<0>; +L_0x2db91e0 .delay 1 (30000,30000,30000) L_0x2db91e0/d; +L_0x2db95d0/d .functor OR 1, L_0x2db9640, L_0x2db97f0, C4<0>, C4<0>; +L_0x2db95d0 .delay 1 (30000,30000,30000) L_0x2db95d0/d; +v0x2c05e30_0 .net *"_s0", 0 0, L_0x2db8de0; 1 drivers +v0x2c05f30_0 .net *"_s10", 0 0, L_0x2db92f0; 1 drivers +v0x2c06010_0 .net *"_s12", 0 0, L_0x2db9450; 1 drivers +v0x2c060d0_0 .net *"_s14", 0 0, L_0x2db9640; 1 drivers +v0x2c061b0_0 .net *"_s16", 0 0, L_0x2db97f0; 1 drivers +v0x2c062e0_0 .net *"_s3", 0 0, L_0x2db8e50; 1 drivers +v0x2c063c0_0 .net *"_s5", 0 0, L_0x2db8fb0; 1 drivers +v0x2c064a0_0 .net *"_s6", 0 0, L_0x2db91e0; 1 drivers +v0x2c06580_0 .net "in", 3 0, L_0x2db9a20; 1 drivers +v0x2c066f0_0 .net "ors", 1 0, L_0x2db90f0; 1 drivers +v0x2c067d0_0 .net "out", 0 0, L_0x2db95d0; 1 drivers +L_0x2db8e50 .part L_0x2db9a20, 0, 1; +L_0x2db8fb0 .part L_0x2db9a20, 1, 1; +L_0x2db90f0 .concat8 [ 1 1 0 0], L_0x2db8de0, L_0x2db91e0; +L_0x2db92f0 .part L_0x2db9a20, 2, 1; +L_0x2db9450 .part L_0x2db9a20, 3, 1; +L_0x2db9640 .part L_0x2db90f0, 0, 1; +L_0x2db97f0 .part L_0x2db90f0, 1, 1; +S_0x2c070e0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2bfaa60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -11270,80 +11923,80 @@ S_0x11344c0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1107e40; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12c8570/d .functor XNOR 1, L_0x12d0bf0, L_0x12d0d50, C4<0>, C4<0>; -L_0x12c8570 .delay 1 (20000,20000,20000) L_0x12c8570/d; -L_0x12c87e0/d .functor AND 1, L_0x12d0bf0, L_0x12c7460, C4<1>, C4<1>; -L_0x12c87e0 .delay 1 (30000,30000,30000) L_0x12c87e0/d; -L_0x12c8850/d .functor AND 1, L_0x12c8570, L_0x12c7070, C4<1>, C4<1>; -L_0x12c8850 .delay 1 (30000,30000,30000) L_0x12c8850/d; -L_0x12c89b0/d .functor OR 1, L_0x12c8850, L_0x12c87e0, C4<0>, C4<0>; -L_0x12c89b0 .delay 1 (30000,30000,30000) L_0x12c89b0/d; -v0x1134770_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers -v0x1134860_0 .net "a_", 0 0, L_0x12c7300; alias, 1 drivers -v0x1134920_0 .net "b", 0 0, L_0x12d0d50; alias, 1 drivers -v0x1134a10_0 .net "b_", 0 0, L_0x12c7460; alias, 1 drivers -v0x1134ab0_0 .net "carryin", 0 0, L_0x12c7070; alias, 1 drivers -v0x1134bf0_0 .net "eq", 0 0, L_0x12c8570; 1 drivers -v0x1134cb0_0 .net "lt", 0 0, L_0x12c87e0; 1 drivers -v0x1134d70_0 .net "out", 0 0, L_0x12c89b0; 1 drivers -v0x1134e30_0 .net "w0", 0 0, L_0x12c8850; 1 drivers -S_0x1135080 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1107e40; +L_0x2db4870/d .functor XNOR 1, L_0x2dbd960, L_0x2dbdac0, C4<0>, C4<0>; +L_0x2db4870 .delay 1 (20000,20000,20000) L_0x2db4870/d; +L_0x2db49f0/d .functor AND 1, L_0x2dbd960, L_0x2db35b0, C4<1>, C4<1>; +L_0x2db49f0 .delay 1 (30000,30000,30000) L_0x2db49f0/d; +L_0x2db4b50/d .functor AND 1, L_0x2db4870, L_0x2db3260, C4<1>, C4<1>; +L_0x2db4b50 .delay 1 (30000,30000,30000) L_0x2db4b50/d; +L_0x2db4c60/d .functor OR 1, L_0x2db4b50, L_0x2db49f0, C4<0>, C4<0>; +L_0x2db4c60 .delay 1 (30000,30000,30000) L_0x2db4c60/d; +v0x2c07390_0 .net "a", 0 0, L_0x2dbd960; alias, 1 drivers +v0x2c07480_0 .net "a_", 0 0, L_0x2db34a0; alias, 1 drivers +v0x2c07540_0 .net "b", 0 0, L_0x2dbdac0; alias, 1 drivers +v0x2c07630_0 .net "b_", 0 0, L_0x2db35b0; alias, 1 drivers +v0x2c076d0_0 .net "carryin", 0 0, L_0x2db3260; alias, 1 drivers +v0x2c07810_0 .net "eq", 0 0, L_0x2db4870; 1 drivers +v0x2c078d0_0 .net "lt", 0 0, L_0x2db49f0; 1 drivers +v0x2c07990_0 .net "out", 0 0, L_0x2db4c60; 1 drivers +v0x2c07a50_0 .net "w0", 0 0, L_0x2db4b50; 1 drivers +S_0x2c07ca0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2bfaa60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12c8350/d .functor OR 1, L_0x12c7e50, L_0x11362e0, C4<0>, C4<0>; -L_0x12c8350 .delay 1 (30000,30000,30000) L_0x12c8350/d; -v0x1135e70_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers -v0x1135fc0_0 .net "b", 0 0, L_0x12c7460; alias, 1 drivers -v0x1136080_0 .net "c1", 0 0, L_0x12c7e50; 1 drivers -v0x1136120_0 .net "c2", 0 0, L_0x11362e0; 1 drivers -v0x11361f0_0 .net "carryin", 0 0, L_0x12c7070; alias, 1 drivers -v0x1136370_0 .net "carryout", 0 0, L_0x12c8350; 1 drivers -v0x1136410_0 .net "s1", 0 0, L_0x12c7d90; 1 drivers -v0x11364b0_0 .net "sum", 0 0, L_0x12c7fb0; 1 drivers -S_0x11352d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1135080; +L_0x2db4450/d .functor OR 1, L_0x2db3fa0, L_0x2c08f00, C4<0>, C4<0>; +L_0x2db4450 .delay 1 (30000,30000,30000) L_0x2db4450/d; +v0x2c08a90_0 .net "a", 0 0, L_0x2dbd960; alias, 1 drivers +v0x2c08be0_0 .net "b", 0 0, L_0x2db35b0; alias, 1 drivers +v0x2c08ca0_0 .net "c1", 0 0, L_0x2db3fa0; 1 drivers +v0x2c08d40_0 .net "c2", 0 0, L_0x2c08f00; 1 drivers +v0x2c08e10_0 .net "carryin", 0 0, L_0x2db3260; alias, 1 drivers +v0x2c08f90_0 .net "carryout", 0 0, L_0x2db4450; 1 drivers +v0x2c09030_0 .net "s1", 0 0, L_0x2db3ee0; 1 drivers +v0x2c090d0_0 .net "sum", 0 0, L_0x2db4100; 1 drivers +S_0x2c07ef0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c07ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12c7d90/d .functor XOR 1, L_0x12d0bf0, L_0x12c7460, C4<0>, C4<0>; -L_0x12c7d90 .delay 1 (30000,30000,30000) L_0x12c7d90/d; -L_0x12c7e50/d .functor AND 1, L_0x12d0bf0, L_0x12c7460, C4<1>, C4<1>; -L_0x12c7e50 .delay 1 (30000,30000,30000) L_0x12c7e50/d; -v0x1135530_0 .net "a", 0 0, L_0x12d0bf0; alias, 1 drivers -v0x11355f0_0 .net "b", 0 0, L_0x12c7460; alias, 1 drivers -v0x11356b0_0 .net "carryout", 0 0, L_0x12c7e50; alias, 1 drivers -v0x1135750_0 .net "sum", 0 0, L_0x12c7d90; alias, 1 drivers -S_0x1135880 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1135080; +L_0x2db3ee0/d .functor XOR 1, L_0x2dbd960, L_0x2db35b0, C4<0>, C4<0>; +L_0x2db3ee0 .delay 1 (30000,30000,30000) L_0x2db3ee0/d; +L_0x2db3fa0/d .functor AND 1, L_0x2dbd960, L_0x2db35b0, C4<1>, C4<1>; +L_0x2db3fa0 .delay 1 (30000,30000,30000) L_0x2db3fa0/d; +v0x2c08150_0 .net "a", 0 0, L_0x2dbd960; alias, 1 drivers +v0x2c08210_0 .net "b", 0 0, L_0x2db35b0; alias, 1 drivers +v0x2c082d0_0 .net "carryout", 0 0, L_0x2db3fa0; alias, 1 drivers +v0x2c08370_0 .net "sum", 0 0, L_0x2db3ee0; alias, 1 drivers +S_0x2c084a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c07ca0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12c7fb0/d .functor XOR 1, L_0x12c7d90, L_0x12c7070, C4<0>, C4<0>; -L_0x12c7fb0 .delay 1 (30000,30000,30000) L_0x12c7fb0/d; -L_0x11362e0/d .functor AND 1, L_0x12c7d90, L_0x12c7070, C4<1>, C4<1>; -L_0x11362e0 .delay 1 (30000,30000,30000) L_0x11362e0/d; -v0x1135ae0_0 .net "a", 0 0, L_0x12c7d90; alias, 1 drivers -v0x1135bb0_0 .net "b", 0 0, L_0x12c7070; alias, 1 drivers -v0x1135c50_0 .net "carryout", 0 0, L_0x11362e0; alias, 1 drivers -v0x1135d20_0 .net "sum", 0 0, L_0x12c7fb0; alias, 1 drivers -S_0x11378d0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1107b70; - .timescale -9 -12; -L_0x2b0ab3d06698 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d066e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12d0c90/d .functor OR 1, L_0x2b0ab3d06698, L_0x2b0ab3d066e0, C4<0>, C4<0>; -L_0x12d0c90 .delay 1 (30000,30000,30000) L_0x12d0c90/d; -v0x1137ac0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06698; 1 drivers -v0x1137ba0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d066e0; 1 drivers -S_0x1137c80 .scope generate, "alu_slices[21]" "alu_slices[21]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1137e90 .param/l "i" 0 3 41, +C4<010101>; -S_0x1137f50 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1137c80; +L_0x2db4100/d .functor XOR 1, L_0x2db3ee0, L_0x2db3260, C4<0>, C4<0>; +L_0x2db4100 .delay 1 (30000,30000,30000) L_0x2db4100/d; +L_0x2c08f00/d .functor AND 1, L_0x2db3ee0, L_0x2db3260, C4<1>, C4<1>; +L_0x2c08f00 .delay 1 (30000,30000,30000) L_0x2c08f00/d; +v0x2c08700_0 .net "a", 0 0, L_0x2db3ee0; alias, 1 drivers +v0x2c087d0_0 .net "b", 0 0, L_0x2db3260; alias, 1 drivers +v0x2c08870_0 .net "carryout", 0 0, L_0x2c08f00; alias, 1 drivers +v0x2c08940_0 .net "sum", 0 0, L_0x2db4100; alias, 1 drivers +S_0x2c0b160 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2bfa790; + .timescale -9 -12; +L_0x2ac6110bb1a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb1f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2db3a60/d .functor OR 1, L_0x2ac6110bb1a8, L_0x2ac6110bb1f0, C4<0>, C4<0>; +L_0x2db3a60 .delay 1 (30000,30000,30000) L_0x2db3a60/d; +v0x2c0b350_0 .net/2u *"_s0", 0 0, L_0x2ac6110bb1a8; 1 drivers +v0x2c0b430_0 .net/2u *"_s2", 0 0, L_0x2ac6110bb1f0; 1 drivers +S_0x2c0b510 .scope generate, "alu_slices[21]" "alu_slices[21]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c0b720 .param/l "i" 0 3 39, +C4<010101>; +S_0x2c0b7e0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c0b510; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -11352,445 +12005,476 @@ S_0x1137f50 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1137c80; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12d0ff0/d .functor NOT 1, L_0x123cb70, C4<0>, C4<0>, C4<0>; -L_0x12d0ff0 .delay 1 (10000,10000,10000) L_0x12d0ff0/d; -L_0x12d1100/d .functor NOT 1, L_0x123ccd0, C4<0>, C4<0>, C4<0>; -L_0x12d1100 .delay 1 (10000,10000,10000) L_0x12d1100/d; -L_0x12d2150/d .functor XOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; -L_0x12d2150 .delay 1 (30000,30000,30000) L_0x12d2150/d; -L_0x2b0ab3d06728 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06770 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12d2800/d .functor OR 1, L_0x2b0ab3d06728, L_0x2b0ab3d06770, C4<0>, C4<0>; -L_0x12d2800 .delay 1 (30000,30000,30000) L_0x12d2800/d; -L_0x12d2a00/d .functor AND 1, L_0x123cb70, L_0x123ccd0, C4<1>, C4<1>; -L_0x12d2a00 .delay 1 (30000,30000,30000) L_0x12d2a00/d; -L_0x12d2ac0/d .functor NAND 1, L_0x123cb70, L_0x123ccd0, C4<1>, C4<1>; -L_0x12d2ac0 .delay 1 (20000,20000,20000) L_0x12d2ac0/d; -L_0x12d2c20/d .functor XOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; -L_0x12d2c20 .delay 1 (20000,20000,20000) L_0x12d2c20/d; -L_0x12d30d0/d .functor OR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; -L_0x12d30d0 .delay 1 (30000,30000,30000) L_0x12d30d0/d; -L_0x123ca70/d .functor NOT 1, L_0x12d6850, C4<0>, C4<0>, C4<0>; -L_0x123ca70 .delay 1 (10000,10000,10000) L_0x123ca70/d; -v0x1146680_0 .net "A", 0 0, L_0x123cb70; 1 drivers -v0x1146740_0 .net "A_", 0 0, L_0x12d0ff0; 1 drivers -v0x1146800_0 .net "B", 0 0, L_0x123ccd0; 1 drivers -v0x11468d0_0 .net "B_", 0 0, L_0x12d1100; 1 drivers -v0x1146970_0 .net *"_s12", 0 0, L_0x12d2800; 1 drivers -v0x1146a60_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06728; 1 drivers -v0x1146b20_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06770; 1 drivers -v0x1146c00_0 .net *"_s18", 0 0, L_0x12d2a00; 1 drivers -v0x1146ce0_0 .net *"_s20", 0 0, L_0x12d2ac0; 1 drivers -v0x1146e50_0 .net *"_s22", 0 0, L_0x12d2c20; 1 drivers -v0x1146f30_0 .net *"_s24", 0 0, L_0x12d30d0; 1 drivers -o0x2b0ab3cd7258 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1147010_0 name=_s30 -o0x2b0ab3cd7288 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x11470f0_0 name=_s32 -v0x11471d0_0 .net *"_s8", 0 0, L_0x12d2150; 1 drivers -v0x11472b0_0 .net "carryin", 0 0, L_0x123cd70; 1 drivers -v0x1147350_0 .net "carryout", 0 0, L_0x123c710; 1 drivers -v0x11473f0_0 .net "carryouts", 7 0, L_0x1355230; 1 drivers -v0x11475a0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1147640_0 .net "result", 0 0, L_0x12d6850; 1 drivers -v0x1147730_0 .net "results", 7 0, L_0x12d2ea0; 1 drivers -v0x1147840_0 .net "zero", 0 0, L_0x123ca70; 1 drivers -LS_0x12d2ea0_0_0 .concat8 [ 1 1 1 1], L_0x12d1620, L_0x12d1c50, L_0x12d2150, L_0x12d2800; -LS_0x12d2ea0_0_4 .concat8 [ 1 1 1 1], L_0x12d2a00, L_0x12d2ac0, L_0x12d2c20, L_0x12d30d0; -L_0x12d2ea0 .concat8 [ 4 4 0 0], LS_0x12d2ea0_0_0, LS_0x12d2ea0_0_4; -LS_0x1355230_0_0 .concat [ 1 1 1 1], L_0x12d18d0, L_0x12d1ff0, o0x2b0ab3cd7258, L_0x12d2650; -LS_0x1355230_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd7288; -L_0x1355230 .concat [ 4 4 0 0], LS_0x1355230_0_0, LS_0x1355230_0_4; -S_0x11381d0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1137f50; +L_0x2dbdd60/d .functor NOT 1, L_0x2d1da00, C4<0>, C4<0>, C4<0>; +L_0x2dbdd60 .delay 1 (10000,10000,10000) L_0x2dbdd60/d; +L_0x2dbde20/d .functor NOT 1, L_0x2d1daa0, C4<0>, C4<0>, C4<0>; +L_0x2dbde20 .delay 1 (10000,10000,10000) L_0x2dbde20/d; +L_0x2dbee70/d .functor XOR 1, L_0x2d1da00, L_0x2d1daa0, C4<0>, C4<0>; +L_0x2dbee70 .delay 1 (30000,30000,30000) L_0x2dbee70/d; +L_0x2ac6110bb238 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb280 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dbef30/d .functor OR 1, L_0x2ac6110bb238, L_0x2ac6110bb280, C4<0>, C4<0>; +L_0x2dbef30 .delay 1 (30000,30000,30000) L_0x2dbef30/d; +L_0x2ac6110bb2c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb310 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dbf6d0/d .functor OR 1, L_0x2ac6110bb2c8, L_0x2ac6110bb310, C4<0>, C4<0>; +L_0x2dbf6d0 .delay 1 (30000,30000,30000) L_0x2dbf6d0/d; +L_0x2dbf8d0/d .functor AND 1, L_0x2d1da00, L_0x2d1daa0, C4<1>, C4<1>; +L_0x2dbf8d0 .delay 1 (30000,30000,30000) L_0x2dbf8d0/d; +L_0x2ac6110bb358 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb3a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dbf990/d .functor OR 1, L_0x2ac6110bb358, L_0x2ac6110bb3a0, C4<0>, C4<0>; +L_0x2dbf990 .delay 1 (30000,30000,30000) L_0x2dbf990/d; +L_0x2dbfb90/d .functor NAND 1, L_0x2d1da00, L_0x2d1daa0, C4<1>, C4<1>; +L_0x2dbfb90 .delay 1 (20000,20000,20000) L_0x2dbfb90/d; +L_0x2ac6110bb3e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb430 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dbfca0/d .functor OR 1, L_0x2ac6110bb3e8, L_0x2ac6110bb430, C4<0>, C4<0>; +L_0x2dbfca0 .delay 1 (30000,30000,30000) L_0x2dbfca0/d; +L_0x2dbfe50/d .functor NOR 1, L_0x2d1da00, L_0x2d1daa0, C4<0>, C4<0>; +L_0x2dbfe50 .delay 1 (20000,20000,20000) L_0x2dbfe50/d; +L_0x2ac6110bb478 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb4c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dbe2d0/d .functor OR 1, L_0x2ac6110bb478, L_0x2ac6110bb4c0, C4<0>, C4<0>; +L_0x2dbe2d0 .delay 1 (30000,30000,30000) L_0x2dbe2d0/d; +L_0x2dc04b0/d .functor OR 1, L_0x2d1da00, L_0x2d1daa0, C4<0>, C4<0>; +L_0x2dc04b0 .delay 1 (30000,30000,30000) L_0x2dc04b0/d; +L_0x2ac6110bb508 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb550 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dc09a0/d .functor OR 1, L_0x2ac6110bb508, L_0x2ac6110bb550, C4<0>, C4<0>; +L_0x2dc09a0 .delay 1 (30000,30000,30000) L_0x2dc09a0/d; +L_0x2d1d7a0/d .functor NOT 1, L_0x2dc4300, C4<0>, C4<0>, C4<0>; +L_0x2d1d7a0 .delay 1 (10000,10000,10000) L_0x2d1d7a0/d; +v0x2c19f10_0 .net "A", 0 0, L_0x2d1da00; 1 drivers +v0x2c19fd0_0 .net "A_", 0 0, L_0x2dbdd60; 1 drivers +v0x2c1a090_0 .net "B", 0 0, L_0x2d1daa0; 1 drivers +v0x2c1a160_0 .net "B_", 0 0, L_0x2dbde20; 1 drivers +v0x2c1a200_0 .net *"_s11", 0 0, L_0x2dbef30; 1 drivers +v0x2c1a2f0_0 .net/2s *"_s13", 0 0, L_0x2ac6110bb238; 1 drivers +v0x2c1a3b0_0 .net/2s *"_s15", 0 0, L_0x2ac6110bb280; 1 drivers +v0x2c1a490_0 .net *"_s19", 0 0, L_0x2dbf6d0; 1 drivers +v0x2c1a570_0 .net/2s *"_s21", 0 0, L_0x2ac6110bb2c8; 1 drivers +v0x2c1a6e0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bb310; 1 drivers +v0x2c1a7c0_0 .net *"_s25", 0 0, L_0x2dbf8d0; 1 drivers +v0x2c1a8a0_0 .net *"_s28", 0 0, L_0x2dbf990; 1 drivers +v0x2c1a980_0 .net/2s *"_s30", 0 0, L_0x2ac6110bb358; 1 drivers +v0x2c1aa60_0 .net/2s *"_s32", 0 0, L_0x2ac6110bb3a0; 1 drivers +v0x2c1ab40_0 .net *"_s34", 0 0, L_0x2dbfb90; 1 drivers +v0x2c1ac20_0 .net *"_s37", 0 0, L_0x2dbfca0; 1 drivers +v0x2c1ad00_0 .net/2s *"_s39", 0 0, L_0x2ac6110bb3e8; 1 drivers +v0x2c1aeb0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bb430; 1 drivers +v0x2c1af50_0 .net *"_s43", 0 0, L_0x2dbfe50; 1 drivers +v0x2c1b030_0 .net *"_s46", 0 0, L_0x2dbe2d0; 1 drivers +v0x2c1b110_0 .net/2s *"_s48", 0 0, L_0x2ac6110bb478; 1 drivers +v0x2c1b1f0_0 .net/2s *"_s50", 0 0, L_0x2ac6110bb4c0; 1 drivers +v0x2c1b2d0_0 .net *"_s52", 0 0, L_0x2dc04b0; 1 drivers +v0x2c1b3b0_0 .net *"_s56", 0 0, L_0x2dc09a0; 1 drivers +v0x2c1b490_0 .net/2s *"_s59", 0 0, L_0x2ac6110bb508; 1 drivers +v0x2c1b570_0 .net/2s *"_s61", 0 0, L_0x2ac6110bb550; 1 drivers +v0x2c1b650_0 .net *"_s8", 0 0, L_0x2dbee70; 1 drivers +v0x2c1b730_0 .net "carryin", 0 0, L_0x2d1db40; 1 drivers +v0x2c1b7d0_0 .net "carryout", 0 0, L_0x2d1d440; 1 drivers +v0x2c1b870_0 .net "carryouts", 7 0, L_0x2dc0630; 1 drivers +v0x2c1b980_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c1ba40_0 .net "result", 0 0, L_0x2dc4300; 1 drivers +v0x2c1bb30_0 .net "results", 7 0, L_0x2dc0280; 1 drivers +v0x2c1ae10_0 .net "zero", 0 0, L_0x2d1d7a0; 1 drivers +LS_0x2dc0280_0_0 .concat8 [ 1 1 1 1], L_0x2dbe340, L_0x2dbe970, L_0x2dbee70, L_0x2dbf6d0; +LS_0x2dc0280_0_4 .concat8 [ 1 1 1 1], L_0x2dbf8d0, L_0x2dbfb90, L_0x2dbfe50, L_0x2dc04b0; +L_0x2dc0280 .concat8 [ 4 4 0 0], LS_0x2dc0280_0_0, LS_0x2dc0280_0_4; +LS_0x2dc0630_0_0 .concat8 [ 1 1 1 1], L_0x2dbe5f0, L_0x2dbed10, L_0x2dbef30, L_0x2dbf520; +LS_0x2dc0630_0_4 .concat8 [ 1 1 1 1], L_0x2dbf990, L_0x2dbfca0, L_0x2dbe2d0, L_0x2dc09a0; +L_0x2dc0630 .concat8 [ 4 4 0 0], LS_0x2dc0630_0_0, LS_0x2dc0630_0_4; +S_0x2c0ba60 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c0b7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12d18d0/d .functor OR 1, L_0x12d13b0, L_0x12d1770, C4<0>, C4<0>; -L_0x12d18d0 .delay 1 (30000,30000,30000) L_0x12d18d0/d; -v0x1139000_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers -v0x11390c0_0 .net "b", 0 0, L_0x123ccd0; alias, 1 drivers -v0x1139190_0 .net "c1", 0 0, L_0x12d13b0; 1 drivers -v0x1139290_0 .net "c2", 0 0, L_0x12d1770; 1 drivers -v0x1139360_0 .net "carryin", 0 0, L_0x123cd70; alias, 1 drivers -v0x1139450_0 .net "carryout", 0 0, L_0x12d18d0; 1 drivers -v0x11394f0_0 .net "s1", 0 0, L_0x12d12f0; 1 drivers -v0x11395e0_0 .net "sum", 0 0, L_0x12d1620; 1 drivers -S_0x1138440 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11381d0; +L_0x2dbe5f0/d .functor OR 1, L_0x2dbe0d0, L_0x2dbe490, C4<0>, C4<0>; +L_0x2dbe5f0 .delay 1 (30000,30000,30000) L_0x2dbe5f0/d; +v0x2c0c890_0 .net "a", 0 0, L_0x2d1da00; alias, 1 drivers +v0x2c0c950_0 .net "b", 0 0, L_0x2d1daa0; alias, 1 drivers +v0x2c0ca20_0 .net "c1", 0 0, L_0x2dbe0d0; 1 drivers +v0x2c0cb20_0 .net "c2", 0 0, L_0x2dbe490; 1 drivers +v0x2c0cbf0_0 .net "carryin", 0 0, L_0x2d1db40; alias, 1 drivers +v0x2c0cce0_0 .net "carryout", 0 0, L_0x2dbe5f0; 1 drivers +v0x2c0cd80_0 .net "s1", 0 0, L_0x2dbe010; 1 drivers +v0x2c0ce70_0 .net "sum", 0 0, L_0x2dbe340; 1 drivers +S_0x2c0bcd0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c0ba60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12d12f0/d .functor XOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; -L_0x12d12f0 .delay 1 (30000,30000,30000) L_0x12d12f0/d; -L_0x12d13b0/d .functor AND 1, L_0x123cb70, L_0x123ccd0, C4<1>, C4<1>; -L_0x12d13b0 .delay 1 (30000,30000,30000) L_0x12d13b0/d; -v0x11386a0_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers -v0x1138780_0 .net "b", 0 0, L_0x123ccd0; alias, 1 drivers -v0x1138840_0 .net "carryout", 0 0, L_0x12d13b0; alias, 1 drivers -v0x11388e0_0 .net "sum", 0 0, L_0x12d12f0; alias, 1 drivers -S_0x1138a20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11381d0; +L_0x2dbe010/d .functor XOR 1, L_0x2d1da00, L_0x2d1daa0, C4<0>, C4<0>; +L_0x2dbe010 .delay 1 (30000,30000,30000) L_0x2dbe010/d; +L_0x2dbe0d0/d .functor AND 1, L_0x2d1da00, L_0x2d1daa0, C4<1>, C4<1>; +L_0x2dbe0d0 .delay 1 (30000,30000,30000) L_0x2dbe0d0/d; +v0x2c0bf30_0 .net "a", 0 0, L_0x2d1da00; alias, 1 drivers +v0x2c0c010_0 .net "b", 0 0, L_0x2d1daa0; alias, 1 drivers +v0x2c0c0d0_0 .net "carryout", 0 0, L_0x2dbe0d0; alias, 1 drivers +v0x2c0c170_0 .net "sum", 0 0, L_0x2dbe010; alias, 1 drivers +S_0x2c0c2b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c0ba60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12d1620/d .functor XOR 1, L_0x12d12f0, L_0x123cd70, C4<0>, C4<0>; -L_0x12d1620 .delay 1 (30000,30000,30000) L_0x12d1620/d; -L_0x12d1770/d .functor AND 1, L_0x12d12f0, L_0x123cd70, C4<1>, C4<1>; -L_0x12d1770 .delay 1 (30000,30000,30000) L_0x12d1770/d; -v0x1138c80_0 .net "a", 0 0, L_0x12d12f0; alias, 1 drivers -v0x1138d20_0 .net "b", 0 0, L_0x123cd70; alias, 1 drivers -v0x1138dc0_0 .net "carryout", 0 0, L_0x12d1770; alias, 1 drivers -v0x1138e90_0 .net "sum", 0 0, L_0x12d1620; alias, 1 drivers -S_0x11396b0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1137f50; +L_0x2dbe340/d .functor XOR 1, L_0x2dbe010, L_0x2d1db40, C4<0>, C4<0>; +L_0x2dbe340 .delay 1 (30000,30000,30000) L_0x2dbe340/d; +L_0x2dbe490/d .functor AND 1, L_0x2dbe010, L_0x2d1db40, C4<1>, C4<1>; +L_0x2dbe490 .delay 1 (30000,30000,30000) L_0x2dbe490/d; +v0x2c0c510_0 .net "a", 0 0, L_0x2dbe010; alias, 1 drivers +v0x2c0c5b0_0 .net "b", 0 0, L_0x2d1db40; alias, 1 drivers +v0x2c0c650_0 .net "carryout", 0 0, L_0x2dbe490; alias, 1 drivers +v0x2c0c720_0 .net "sum", 0 0, L_0x2dbe340; alias, 1 drivers +S_0x2c0cf40 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c0b7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x113eaa0_0 .net "ands", 7 0, L_0x12d8370; 1 drivers -v0x113ebb0_0 .net "in", 7 0, L_0x1355230; alias, 1 drivers -v0x113ec70_0 .net "out", 0 0, L_0x123c710; alias, 1 drivers -v0x113ed40_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11398d0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11396b0; +v0x2c12330_0 .net "ands", 7 0, L_0x2dc5d40; 1 drivers +v0x2c12440_0 .net "in", 7 0, L_0x2dc0630; alias, 1 drivers +v0x2c12500_0 .net "out", 0 0, L_0x2d1d440; alias, 1 drivers +v0x2c125d0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c0d160 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c0cf40; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x113c000_0 .net "A", 7 0, L_0x1355230; alias, 1 drivers -v0x113c100_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x113c1c0_0 .net *"_s0", 0 0, L_0x12d6bb0; 1 drivers -v0x113c280_0 .net *"_s12", 0 0, L_0x12d7520; 1 drivers -v0x113c360_0 .net *"_s16", 0 0, L_0x12d7880; 1 drivers -v0x113c490_0 .net *"_s20", 0 0, L_0x12d7bf0; 1 drivers -v0x113c570_0 .net *"_s24", 0 0, L_0x12d7fe0; 1 drivers -v0x113c650_0 .net *"_s28", 0 0, L_0x12d7f70; 1 drivers -v0x113c730_0 .net *"_s4", 0 0, L_0x12d6ec0; 1 drivers -v0x113c8a0_0 .net *"_s8", 0 0, L_0x12d7210; 1 drivers -v0x113c980_0 .net "out", 7 0, L_0x12d8370; alias, 1 drivers -L_0x12d6c70 .part L_0x1355230, 0, 1; -L_0x12d6dd0 .part v0x12010b0_0, 0, 1; -L_0x12d6f80 .part L_0x1355230, 1, 1; -L_0x12d7170 .part v0x12010b0_0, 1, 1; -L_0x12d72d0 .part L_0x1355230, 2, 1; -L_0x12d7430 .part v0x12010b0_0, 2, 1; -L_0x12d75e0 .part L_0x1355230, 3, 1; -L_0x12d7740 .part v0x12010b0_0, 3, 1; -L_0x12d7940 .part L_0x1355230, 4, 1; -L_0x12d7aa0 .part v0x12010b0_0, 4, 1; -L_0x12d7c60 .part L_0x1355230, 5, 1; -L_0x12d7ed0 .part v0x12010b0_0, 5, 1; -L_0x12d80a0 .part L_0x1355230, 6, 1; -L_0x12d8200 .part v0x12010b0_0, 6, 1; -LS_0x12d8370_0_0 .concat8 [ 1 1 1 1], L_0x12d6bb0, L_0x12d6ec0, L_0x12d7210, L_0x12d7520; -LS_0x12d8370_0_4 .concat8 [ 1 1 1 1], L_0x12d7880, L_0x12d7bf0, L_0x12d7fe0, L_0x12d7f70; -L_0x12d8370 .concat8 [ 4 4 0 0], LS_0x12d8370_0_0, LS_0x12d8370_0_4; -L_0x12d8730 .part L_0x1355230, 7, 1; -L_0x12d8920 .part v0x12010b0_0, 7, 1; -S_0x1139b30 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x1139d40 .param/l "i" 0 4 54, +C4<00>; -L_0x12d6bb0/d .functor AND 1, L_0x12d6c70, L_0x12d6dd0, C4<1>, C4<1>; -L_0x12d6bb0 .delay 1 (30000,30000,30000) L_0x12d6bb0/d; -v0x1139e20_0 .net *"_s0", 0 0, L_0x12d6c70; 1 drivers -v0x1139f00_0 .net *"_s1", 0 0, L_0x12d6dd0; 1 drivers -S_0x1139fe0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113a1f0 .param/l "i" 0 4 54, +C4<01>; -L_0x12d6ec0/d .functor AND 1, L_0x12d6f80, L_0x12d7170, C4<1>, C4<1>; -L_0x12d6ec0 .delay 1 (30000,30000,30000) L_0x12d6ec0/d; -v0x113a2b0_0 .net *"_s0", 0 0, L_0x12d6f80; 1 drivers -v0x113a390_0 .net *"_s1", 0 0, L_0x12d7170; 1 drivers -S_0x113a470 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113a680 .param/l "i" 0 4 54, +C4<010>; -L_0x12d7210/d .functor AND 1, L_0x12d72d0, L_0x12d7430, C4<1>, C4<1>; -L_0x12d7210 .delay 1 (30000,30000,30000) L_0x12d7210/d; -v0x113a720_0 .net *"_s0", 0 0, L_0x12d72d0; 1 drivers -v0x113a800_0 .net *"_s1", 0 0, L_0x12d7430; 1 drivers -S_0x113a8e0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113aaf0 .param/l "i" 0 4 54, +C4<011>; -L_0x12d7520/d .functor AND 1, L_0x12d75e0, L_0x12d7740, C4<1>, C4<1>; -L_0x12d7520 .delay 1 (30000,30000,30000) L_0x12d7520/d; -v0x113abb0_0 .net *"_s0", 0 0, L_0x12d75e0; 1 drivers -v0x113ac90_0 .net *"_s1", 0 0, L_0x12d7740; 1 drivers -S_0x113ad70 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113afd0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12d7880/d .functor AND 1, L_0x12d7940, L_0x12d7aa0, C4<1>, C4<1>; -L_0x12d7880 .delay 1 (30000,30000,30000) L_0x12d7880/d; -v0x113b090_0 .net *"_s0", 0 0, L_0x12d7940; 1 drivers -v0x113b170_0 .net *"_s1", 0 0, L_0x12d7aa0; 1 drivers -S_0x113b250 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113b460 .param/l "i" 0 4 54, +C4<0101>; -L_0x12d7bf0/d .functor AND 1, L_0x12d7c60, L_0x12d7ed0, C4<1>, C4<1>; -L_0x12d7bf0 .delay 1 (30000,30000,30000) L_0x12d7bf0/d; -v0x113b520_0 .net *"_s0", 0 0, L_0x12d7c60; 1 drivers -v0x113b600_0 .net *"_s1", 0 0, L_0x12d7ed0; 1 drivers -S_0x113b6e0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113b8f0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12d7fe0/d .functor AND 1, L_0x12d80a0, L_0x12d8200, C4<1>, C4<1>; -L_0x12d7fe0 .delay 1 (30000,30000,30000) L_0x12d7fe0/d; -v0x113b9b0_0 .net *"_s0", 0 0, L_0x12d80a0; 1 drivers -v0x113ba90_0 .net *"_s1", 0 0, L_0x12d8200; 1 drivers -S_0x113bb70 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11398d0; - .timescale -9 -12; -P_0x113bd80 .param/l "i" 0 4 54, +C4<0111>; -L_0x12d7f70/d .functor AND 1, L_0x12d8730, L_0x12d8920, C4<1>, C4<1>; -L_0x12d7f70 .delay 1 (30000,30000,30000) L_0x12d7f70/d; -v0x113be40_0 .net *"_s0", 0 0, L_0x12d8730; 1 drivers -v0x113bf20_0 .net *"_s1", 0 0, L_0x12d8920; 1 drivers -S_0x113cae0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11396b0; +v0x2c0f890_0 .net "A", 7 0, L_0x2dc0630; alias, 1 drivers +v0x2c0f990_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c0fa50_0 .net *"_s0", 0 0, L_0x2dc4660; 1 drivers +v0x2c0fb10_0 .net *"_s12", 0 0, L_0x2dc4fd0; 1 drivers +v0x2c0fbf0_0 .net *"_s16", 0 0, L_0x2dc5330; 1 drivers +v0x2c0fd20_0 .net *"_s20", 0 0, L_0x2dc5700; 1 drivers +v0x2c0fe00_0 .net *"_s24", 0 0, L_0x2dc5a30; 1 drivers +v0x2c0fee0_0 .net *"_s28", 0 0, L_0x2dc59c0; 1 drivers +v0x2c0ffc0_0 .net *"_s4", 0 0, L_0x2dc49b0; 1 drivers +v0x2c10130_0 .net *"_s8", 0 0, L_0x2dc4cc0; 1 drivers +v0x2c10210_0 .net "out", 7 0, L_0x2dc5d40; alias, 1 drivers +L_0x2dc4720 .part L_0x2dc0630, 0, 1; +L_0x2dc4910 .part v0x2cdd2e0_0, 0, 1; +L_0x2dc4a70 .part L_0x2dc0630, 1, 1; +L_0x2dc4bd0 .part v0x2cdd2e0_0, 1, 1; +L_0x2dc4d80 .part L_0x2dc0630, 2, 1; +L_0x2dc4ee0 .part v0x2cdd2e0_0, 2, 1; +L_0x2dc5090 .part L_0x2dc0630, 3, 1; +L_0x2dc51f0 .part v0x2cdd2e0_0, 3, 1; +L_0x2dc53f0 .part L_0x2dc0630, 4, 1; +L_0x2dc5660 .part v0x2cdd2e0_0, 4, 1; +L_0x2dc5770 .part L_0x2dc0630, 5, 1; +L_0x2dc58d0 .part v0x2cdd2e0_0, 5, 1; +L_0x2dc5af0 .part L_0x2dc0630, 6, 1; +L_0x2dc5c50 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dc5d40_0_0 .concat8 [ 1 1 1 1], L_0x2dc4660, L_0x2dc49b0, L_0x2dc4cc0, L_0x2dc4fd0; +LS_0x2dc5d40_0_4 .concat8 [ 1 1 1 1], L_0x2dc5330, L_0x2dc5700, L_0x2dc5a30, L_0x2dc59c0; +L_0x2dc5d40 .concat8 [ 4 4 0 0], LS_0x2dc5d40_0_0, LS_0x2dc5d40_0_4; +L_0x2dc6100 .part L_0x2dc0630, 7, 1; +L_0x2dc62f0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c0d3c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0d5d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2dc4660/d .functor AND 1, L_0x2dc4720, L_0x2dc4910, C4<1>, C4<1>; +L_0x2dc4660 .delay 1 (30000,30000,30000) L_0x2dc4660/d; +v0x2c0d6b0_0 .net *"_s0", 0 0, L_0x2dc4720; 1 drivers +v0x2c0d790_0 .net *"_s1", 0 0, L_0x2dc4910; 1 drivers +S_0x2c0d870 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0da80 .param/l "i" 0 4 54, +C4<01>; +L_0x2dc49b0/d .functor AND 1, L_0x2dc4a70, L_0x2dc4bd0, C4<1>, C4<1>; +L_0x2dc49b0 .delay 1 (30000,30000,30000) L_0x2dc49b0/d; +v0x2c0db40_0 .net *"_s0", 0 0, L_0x2dc4a70; 1 drivers +v0x2c0dc20_0 .net *"_s1", 0 0, L_0x2dc4bd0; 1 drivers +S_0x2c0dd00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0df10 .param/l "i" 0 4 54, +C4<010>; +L_0x2dc4cc0/d .functor AND 1, L_0x2dc4d80, L_0x2dc4ee0, C4<1>, C4<1>; +L_0x2dc4cc0 .delay 1 (30000,30000,30000) L_0x2dc4cc0/d; +v0x2c0dfb0_0 .net *"_s0", 0 0, L_0x2dc4d80; 1 drivers +v0x2c0e090_0 .net *"_s1", 0 0, L_0x2dc4ee0; 1 drivers +S_0x2c0e170 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0e380 .param/l "i" 0 4 54, +C4<011>; +L_0x2dc4fd0/d .functor AND 1, L_0x2dc5090, L_0x2dc51f0, C4<1>, C4<1>; +L_0x2dc4fd0 .delay 1 (30000,30000,30000) L_0x2dc4fd0/d; +v0x2c0e440_0 .net *"_s0", 0 0, L_0x2dc5090; 1 drivers +v0x2c0e520_0 .net *"_s1", 0 0, L_0x2dc51f0; 1 drivers +S_0x2c0e600 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0e860 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dc5330/d .functor AND 1, L_0x2dc53f0, L_0x2dc5660, C4<1>, C4<1>; +L_0x2dc5330 .delay 1 (30000,30000,30000) L_0x2dc5330/d; +v0x2c0e920_0 .net *"_s0", 0 0, L_0x2dc53f0; 1 drivers +v0x2c0ea00_0 .net *"_s1", 0 0, L_0x2dc5660; 1 drivers +S_0x2c0eae0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0ecf0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dc5700/d .functor AND 1, L_0x2dc5770, L_0x2dc58d0, C4<1>, C4<1>; +L_0x2dc5700 .delay 1 (30000,30000,30000) L_0x2dc5700/d; +v0x2c0edb0_0 .net *"_s0", 0 0, L_0x2dc5770; 1 drivers +v0x2c0ee90_0 .net *"_s1", 0 0, L_0x2dc58d0; 1 drivers +S_0x2c0ef70 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0f180 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dc5a30/d .functor AND 1, L_0x2dc5af0, L_0x2dc5c50, C4<1>, C4<1>; +L_0x2dc5a30 .delay 1 (30000,30000,30000) L_0x2dc5a30/d; +v0x2c0f240_0 .net *"_s0", 0 0, L_0x2dc5af0; 1 drivers +v0x2c0f320_0 .net *"_s1", 0 0, L_0x2dc5c50; 1 drivers +S_0x2c0f400 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c0d160; + .timescale -9 -12; +P_0x2c0f610 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dc59c0/d .functor AND 1, L_0x2dc6100, L_0x2dc62f0, C4<1>, C4<1>; +L_0x2dc59c0 .delay 1 (30000,30000,30000) L_0x2dc59c0/d; +v0x2c0f6d0_0 .net *"_s0", 0 0, L_0x2dc6100; 1 drivers +v0x2c0f7b0_0 .net *"_s1", 0 0, L_0x2dc62f0; 1 drivers +S_0x2c10370 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c0cf40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x123c710/d .functor OR 1, L_0x123c7d0, L_0x123c980, C4<0>, C4<0>; -L_0x123c710 .delay 1 (30000,30000,30000) L_0x123c710/d; -v0x113e630_0 .net *"_s10", 0 0, L_0x123c7d0; 1 drivers -v0x113e710_0 .net *"_s12", 0 0, L_0x123c980; 1 drivers -v0x113e7f0_0 .net "in", 7 0, L_0x12d8370; alias, 1 drivers -v0x113e8c0_0 .net "ors", 1 0, L_0x123c530; 1 drivers -v0x113e980_0 .net "out", 0 0, L_0x123c710; alias, 1 drivers -L_0x123b8d0 .part L_0x12d8370, 0, 4; -L_0x123c530 .concat8 [ 1 1 0 0], L_0x123b5c0, L_0x123c1f0; -L_0x123c670 .part L_0x12d8370, 4, 4; -L_0x123c7d0 .part L_0x123c530, 0, 1; -L_0x123c980 .part L_0x123c530, 1, 1; -S_0x113cca0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x113cae0; +L_0x2d1d440/d .functor OR 1, L_0x2d1d500, L_0x2d1d6b0, C4<0>, C4<0>; +L_0x2d1d440 .delay 1 (30000,30000,30000) L_0x2d1d440/d; +v0x2c11ec0_0 .net *"_s10", 0 0, L_0x2d1d500; 1 drivers +v0x2c11fa0_0 .net *"_s12", 0 0, L_0x2d1d6b0; 1 drivers +v0x2c12080_0 .net "in", 7 0, L_0x2dc5d40; alias, 1 drivers +v0x2c12150_0 .net "ors", 1 0, L_0x2d1d260; 1 drivers +v0x2c12210_0 .net "out", 0 0, L_0x2d1d440; alias, 1 drivers +L_0x2d1c630 .part L_0x2dc5d40, 0, 4; +L_0x2d1d260 .concat8 [ 1 1 0 0], L_0x2d1c320, L_0x2d1cf50; +L_0x2d1d3a0 .part L_0x2dc5d40, 4, 4; +L_0x2d1d500 .part L_0x2d1d260, 0, 1; +L_0x2d1d6b0 .part L_0x2d1d260, 1, 1; +S_0x2c10530 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c10370; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12d82f0/d .functor OR 1, L_0x123ae40, L_0x123afa0, C4<0>, C4<0>; -L_0x12d82f0 .delay 1 (30000,30000,30000) L_0x12d82f0/d; -L_0x123b1d0/d .functor OR 1, L_0x123b2e0, L_0x123b440, C4<0>, C4<0>; -L_0x123b1d0 .delay 1 (30000,30000,30000) L_0x123b1d0/d; -L_0x123b5c0/d .functor OR 1, L_0x123b630, L_0x123b7e0, C4<0>, C4<0>; -L_0x123b5c0 .delay 1 (30000,30000,30000) L_0x123b5c0/d; -v0x113cef0_0 .net *"_s0", 0 0, L_0x12d82f0; 1 drivers -v0x113cff0_0 .net *"_s10", 0 0, L_0x123b2e0; 1 drivers -v0x113d0d0_0 .net *"_s12", 0 0, L_0x123b440; 1 drivers -v0x113d190_0 .net *"_s14", 0 0, L_0x123b630; 1 drivers -v0x113d270_0 .net *"_s16", 0 0, L_0x123b7e0; 1 drivers -v0x113d3a0_0 .net *"_s3", 0 0, L_0x123ae40; 1 drivers -v0x113d480_0 .net *"_s5", 0 0, L_0x123afa0; 1 drivers -v0x113d560_0 .net *"_s6", 0 0, L_0x123b1d0; 1 drivers -v0x113d640_0 .net "in", 3 0, L_0x123b8d0; 1 drivers -v0x113d7b0_0 .net "ors", 1 0, L_0x123b0e0; 1 drivers -v0x113d890_0 .net "out", 0 0, L_0x123b5c0; 1 drivers -L_0x123ae40 .part L_0x123b8d0, 0, 1; -L_0x123afa0 .part L_0x123b8d0, 1, 1; -L_0x123b0e0 .concat8 [ 1 1 0 0], L_0x12d82f0, L_0x123b1d0; -L_0x123b2e0 .part L_0x123b8d0, 2, 1; -L_0x123b440 .part L_0x123b8d0, 3, 1; -L_0x123b630 .part L_0x123b0e0, 0, 1; -L_0x123b7e0 .part L_0x123b0e0, 1, 1; -S_0x113d9b0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x113cae0; +L_0x2dc2280/d .functor OR 1, L_0x2d1bc10, L_0x2d1bd70, C4<0>, C4<0>; +L_0x2dc2280 .delay 1 (30000,30000,30000) L_0x2dc2280/d; +L_0x2d1bcb0/d .functor OR 1, L_0x2d1c040, L_0x2d1c1a0, C4<0>, C4<0>; +L_0x2d1bcb0 .delay 1 (30000,30000,30000) L_0x2d1bcb0/d; +L_0x2d1c320/d .functor OR 1, L_0x2d1c390, L_0x2d1c540, C4<0>, C4<0>; +L_0x2d1c320 .delay 1 (30000,30000,30000) L_0x2d1c320/d; +v0x2c10780_0 .net *"_s0", 0 0, L_0x2dc2280; 1 drivers +v0x2c10880_0 .net *"_s10", 0 0, L_0x2d1c040; 1 drivers +v0x2c10960_0 .net *"_s12", 0 0, L_0x2d1c1a0; 1 drivers +v0x2c10a20_0 .net *"_s14", 0 0, L_0x2d1c390; 1 drivers +v0x2c10b00_0 .net *"_s16", 0 0, L_0x2d1c540; 1 drivers +v0x2c10c30_0 .net *"_s3", 0 0, L_0x2d1bc10; 1 drivers +v0x2c10d10_0 .net *"_s5", 0 0, L_0x2d1bd70; 1 drivers +v0x2c10df0_0 .net *"_s6", 0 0, L_0x2d1bcb0; 1 drivers +v0x2c10ed0_0 .net "in", 3 0, L_0x2d1c630; 1 drivers +v0x2c11040_0 .net "ors", 1 0, L_0x2d1beb0; 1 drivers +v0x2c11120_0 .net "out", 0 0, L_0x2d1c320; 1 drivers +L_0x2d1bc10 .part L_0x2d1c630, 0, 1; +L_0x2d1bd70 .part L_0x2d1c630, 1, 1; +L_0x2d1beb0 .concat8 [ 1 1 0 0], L_0x2dc2280, L_0x2d1bcb0; +L_0x2d1c040 .part L_0x2d1c630, 2, 1; +L_0x2d1c1a0 .part L_0x2d1c630, 3, 1; +L_0x2d1c390 .part L_0x2d1beb0, 0, 1; +L_0x2d1c540 .part L_0x2d1beb0, 1, 1; +S_0x2c11240 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c10370; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x123ba00/d .functor OR 1, L_0x123ba70, L_0x123bbd0, C4<0>, C4<0>; -L_0x123ba00 .delay 1 (30000,30000,30000) L_0x123ba00/d; -L_0x123be00/d .functor OR 1, L_0x123bf10, L_0x123c070, C4<0>, C4<0>; -L_0x123be00 .delay 1 (30000,30000,30000) L_0x123be00/d; -L_0x123c1f0/d .functor OR 1, L_0x123c290, L_0x123c440, C4<0>, C4<0>; -L_0x123c1f0 .delay 1 (30000,30000,30000) L_0x123c1f0/d; -v0x113db70_0 .net *"_s0", 0 0, L_0x123ba00; 1 drivers -v0x113dc70_0 .net *"_s10", 0 0, L_0x123bf10; 1 drivers -v0x113dd50_0 .net *"_s12", 0 0, L_0x123c070; 1 drivers -v0x113de10_0 .net *"_s14", 0 0, L_0x123c290; 1 drivers -v0x113def0_0 .net *"_s16", 0 0, L_0x123c440; 1 drivers -v0x113e020_0 .net *"_s3", 0 0, L_0x123ba70; 1 drivers -v0x113e100_0 .net *"_s5", 0 0, L_0x123bbd0; 1 drivers -v0x113e1e0_0 .net *"_s6", 0 0, L_0x123be00; 1 drivers -v0x113e2c0_0 .net "in", 3 0, L_0x123c670; 1 drivers -v0x113e430_0 .net "ors", 1 0, L_0x123bd10; 1 drivers -v0x113e510_0 .net "out", 0 0, L_0x123c1f0; 1 drivers -L_0x123ba70 .part L_0x123c670, 0, 1; -L_0x123bbd0 .part L_0x123c670, 1, 1; -L_0x123bd10 .concat8 [ 1 1 0 0], L_0x123ba00, L_0x123be00; -L_0x123bf10 .part L_0x123c670, 2, 1; -L_0x123c070 .part L_0x123c670, 3, 1; -L_0x123c290 .part L_0x123bd10, 0, 1; -L_0x123c440 .part L_0x123bd10, 1, 1; -S_0x113ee20 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1137f50; +L_0x2d1c760/d .functor OR 1, L_0x2d1c7d0, L_0x2d1c930, C4<0>, C4<0>; +L_0x2d1c760 .delay 1 (30000,30000,30000) L_0x2d1c760/d; +L_0x2d1cb60/d .functor OR 1, L_0x2d1cc70, L_0x2d1cdd0, C4<0>, C4<0>; +L_0x2d1cb60 .delay 1 (30000,30000,30000) L_0x2d1cb60/d; +L_0x2d1cf50/d .functor OR 1, L_0x2d1cfc0, L_0x2d1d170, C4<0>, C4<0>; +L_0x2d1cf50 .delay 1 (30000,30000,30000) L_0x2d1cf50/d; +v0x2c11400_0 .net *"_s0", 0 0, L_0x2d1c760; 1 drivers +v0x2c11500_0 .net *"_s10", 0 0, L_0x2d1cc70; 1 drivers +v0x2c115e0_0 .net *"_s12", 0 0, L_0x2d1cdd0; 1 drivers +v0x2c116a0_0 .net *"_s14", 0 0, L_0x2d1cfc0; 1 drivers +v0x2c11780_0 .net *"_s16", 0 0, L_0x2d1d170; 1 drivers +v0x2c118b0_0 .net *"_s3", 0 0, L_0x2d1c7d0; 1 drivers +v0x2c11990_0 .net *"_s5", 0 0, L_0x2d1c930; 1 drivers +v0x2c11a70_0 .net *"_s6", 0 0, L_0x2d1cb60; 1 drivers +v0x2c11b50_0 .net "in", 3 0, L_0x2d1d3a0; 1 drivers +v0x2c11cc0_0 .net "ors", 1 0, L_0x2d1ca70; 1 drivers +v0x2c11da0_0 .net "out", 0 0, L_0x2d1cf50; 1 drivers +L_0x2d1c7d0 .part L_0x2d1d3a0, 0, 1; +L_0x2d1c930 .part L_0x2d1d3a0, 1, 1; +L_0x2d1ca70 .concat8 [ 1 1 0 0], L_0x2d1c760, L_0x2d1cb60; +L_0x2d1cc70 .part L_0x2d1d3a0, 2, 1; +L_0x2d1cdd0 .part L_0x2d1d3a0, 3, 1; +L_0x2d1cfc0 .part L_0x2d1ca70, 0, 1; +L_0x2d1d170 .part L_0x2d1ca70, 1, 1; +S_0x2c126b0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c0b7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1144250_0 .net "ands", 7 0, L_0x12d4960; 1 drivers -v0x1144360_0 .net "in", 7 0, L_0x12d2ea0; alias, 1 drivers -v0x1144420_0 .net "out", 0 0, L_0x12d6850; alias, 1 drivers -v0x11444f0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x113f070 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x113ee20; +v0x2c17ae0_0 .net "ands", 7 0, L_0x2dc2300; 1 drivers +v0x2c17bf0_0 .net "in", 7 0, L_0x2dc0280; alias, 1 drivers +v0x2c17cb0_0 .net "out", 0 0, L_0x2dc4300; alias, 1 drivers +v0x2c17d80_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c12900 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c126b0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11417b0_0 .net "A", 7 0, L_0x12d2ea0; alias, 1 drivers -v0x11418b0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1141970_0 .net *"_s0", 0 0, L_0x12d3230; 1 drivers -v0x1141a30_0 .net *"_s12", 0 0, L_0x12d3bf0; 1 drivers -v0x1141b10_0 .net *"_s16", 0 0, L_0x12d3f50; 1 drivers -v0x1141c40_0 .net *"_s20", 0 0, L_0x12d4320; 1 drivers -v0x1141d20_0 .net *"_s24", 0 0, L_0x12d4650; 1 drivers -v0x1141e00_0 .net *"_s28", 0 0, L_0x12d45e0; 1 drivers -v0x1141ee0_0 .net *"_s4", 0 0, L_0x12d35d0; 1 drivers -v0x1142050_0 .net *"_s8", 0 0, L_0x12d38e0; 1 drivers -v0x1142130_0 .net "out", 7 0, L_0x12d4960; alias, 1 drivers -L_0x12d3340 .part L_0x12d2ea0, 0, 1; -L_0x12d3530 .part v0x12010b0_0, 0, 1; -L_0x12d3690 .part L_0x12d2ea0, 1, 1; -L_0x12d37f0 .part v0x12010b0_0, 1, 1; -L_0x12d39a0 .part L_0x12d2ea0, 2, 1; -L_0x12d3b00 .part v0x12010b0_0, 2, 1; -L_0x12d3cb0 .part L_0x12d2ea0, 3, 1; -L_0x12d3e10 .part v0x12010b0_0, 3, 1; -L_0x12d4010 .part L_0x12d2ea0, 4, 1; -L_0x12d4280 .part v0x12010b0_0, 4, 1; -L_0x12d4390 .part L_0x12d2ea0, 5, 1; -L_0x12d44f0 .part v0x12010b0_0, 5, 1; -L_0x12d4710 .part L_0x12d2ea0, 6, 1; -L_0x12d4870 .part v0x12010b0_0, 6, 1; -LS_0x12d4960_0_0 .concat8 [ 1 1 1 1], L_0x12d3230, L_0x12d35d0, L_0x12d38e0, L_0x12d3bf0; -LS_0x12d4960_0_4 .concat8 [ 1 1 1 1], L_0x12d3f50, L_0x12d4320, L_0x12d4650, L_0x12d45e0; -L_0x12d4960 .concat8 [ 4 4 0 0], LS_0x12d4960_0_0, LS_0x12d4960_0_4; -L_0x12d4d20 .part L_0x12d2ea0, 7, 1; -L_0x12d4f10 .part v0x12010b0_0, 7, 1; -S_0x113f2b0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x113f4c0 .param/l "i" 0 4 54, +C4<00>; -L_0x12d3230/d .functor AND 1, L_0x12d3340, L_0x12d3530, C4<1>, C4<1>; -L_0x12d3230 .delay 1 (30000,30000,30000) L_0x12d3230/d; -v0x113f5a0_0 .net *"_s0", 0 0, L_0x12d3340; 1 drivers -v0x113f680_0 .net *"_s1", 0 0, L_0x12d3530; 1 drivers -S_0x113f760 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x113f970 .param/l "i" 0 4 54, +C4<01>; -L_0x12d35d0/d .functor AND 1, L_0x12d3690, L_0x12d37f0, C4<1>, C4<1>; -L_0x12d35d0 .delay 1 (30000,30000,30000) L_0x12d35d0/d; -v0x113fa30_0 .net *"_s0", 0 0, L_0x12d3690; 1 drivers -v0x113fb10_0 .net *"_s1", 0 0, L_0x12d37f0; 1 drivers -S_0x113fbf0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x113fe30 .param/l "i" 0 4 54, +C4<010>; -L_0x12d38e0/d .functor AND 1, L_0x12d39a0, L_0x12d3b00, C4<1>, C4<1>; -L_0x12d38e0 .delay 1 (30000,30000,30000) L_0x12d38e0/d; -v0x113fed0_0 .net *"_s0", 0 0, L_0x12d39a0; 1 drivers -v0x113ffb0_0 .net *"_s1", 0 0, L_0x12d3b00; 1 drivers -S_0x1140090 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x11402a0 .param/l "i" 0 4 54, +C4<011>; -L_0x12d3bf0/d .functor AND 1, L_0x12d3cb0, L_0x12d3e10, C4<1>, C4<1>; -L_0x12d3bf0 .delay 1 (30000,30000,30000) L_0x12d3bf0/d; -v0x1140360_0 .net *"_s0", 0 0, L_0x12d3cb0; 1 drivers -v0x1140440_0 .net *"_s1", 0 0, L_0x12d3e10; 1 drivers -S_0x1140520 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x1140780 .param/l "i" 0 4 54, +C4<0100>; -L_0x12d3f50/d .functor AND 1, L_0x12d4010, L_0x12d4280, C4<1>, C4<1>; -L_0x12d3f50 .delay 1 (30000,30000,30000) L_0x12d3f50/d; -v0x1140840_0 .net *"_s0", 0 0, L_0x12d4010; 1 drivers -v0x1140920_0 .net *"_s1", 0 0, L_0x12d4280; 1 drivers -S_0x1140a00 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x1140c10 .param/l "i" 0 4 54, +C4<0101>; -L_0x12d4320/d .functor AND 1, L_0x12d4390, L_0x12d44f0, C4<1>, C4<1>; -L_0x12d4320 .delay 1 (30000,30000,30000) L_0x12d4320/d; -v0x1140cd0_0 .net *"_s0", 0 0, L_0x12d4390; 1 drivers -v0x1140db0_0 .net *"_s1", 0 0, L_0x12d44f0; 1 drivers -S_0x1140e90 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x11410a0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12d4650/d .functor AND 1, L_0x12d4710, L_0x12d4870, C4<1>, C4<1>; -L_0x12d4650 .delay 1 (30000,30000,30000) L_0x12d4650/d; -v0x1141160_0 .net *"_s0", 0 0, L_0x12d4710; 1 drivers -v0x1141240_0 .net *"_s1", 0 0, L_0x12d4870; 1 drivers -S_0x1141320 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x113f070; - .timescale -9 -12; -P_0x1141530 .param/l "i" 0 4 54, +C4<0111>; -L_0x12d45e0/d .functor AND 1, L_0x12d4d20, L_0x12d4f10, C4<1>, C4<1>; -L_0x12d45e0 .delay 1 (30000,30000,30000) L_0x12d45e0/d; -v0x11415f0_0 .net *"_s0", 0 0, L_0x12d4d20; 1 drivers -v0x11416d0_0 .net *"_s1", 0 0, L_0x12d4f10; 1 drivers -S_0x1142290 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x113ee20; +v0x2c15040_0 .net "A", 7 0, L_0x2dc0280; alias, 1 drivers +v0x2c15140_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c15200_0 .net *"_s0", 0 0, L_0x2dc0b50; 1 drivers +v0x2c152c0_0 .net *"_s12", 0 0, L_0x2dc1510; 1 drivers +v0x2c153a0_0 .net *"_s16", 0 0, L_0x2dc1870; 1 drivers +v0x2c154d0_0 .net *"_s20", 0 0, L_0x2dc1c40; 1 drivers +v0x2c155b0_0 .net *"_s24", 0 0, L_0x2dc1f70; 1 drivers +v0x2c15690_0 .net *"_s28", 0 0, L_0x2dc1f00; 1 drivers +v0x2c15770_0 .net *"_s4", 0 0, L_0x2dc0ef0; 1 drivers +v0x2c158e0_0 .net *"_s8", 0 0, L_0x2dc1200; 1 drivers +v0x2c159c0_0 .net "out", 7 0, L_0x2dc2300; alias, 1 drivers +L_0x2dc0c60 .part L_0x2dc0280, 0, 1; +L_0x2dc0e50 .part v0x2cdd2e0_0, 0, 1; +L_0x2dc0fb0 .part L_0x2dc0280, 1, 1; +L_0x2dc1110 .part v0x2cdd2e0_0, 1, 1; +L_0x2dc12c0 .part L_0x2dc0280, 2, 1; +L_0x2dc1420 .part v0x2cdd2e0_0, 2, 1; +L_0x2dc15d0 .part L_0x2dc0280, 3, 1; +L_0x2dc1730 .part v0x2cdd2e0_0, 3, 1; +L_0x2dc1930 .part L_0x2dc0280, 4, 1; +L_0x2dc1ba0 .part v0x2cdd2e0_0, 4, 1; +L_0x2dc1cb0 .part L_0x2dc0280, 5, 1; +L_0x2dc1e10 .part v0x2cdd2e0_0, 5, 1; +L_0x2dc2030 .part L_0x2dc0280, 6, 1; +L_0x2dc2190 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dc2300_0_0 .concat8 [ 1 1 1 1], L_0x2dc0b50, L_0x2dc0ef0, L_0x2dc1200, L_0x2dc1510; +LS_0x2dc2300_0_4 .concat8 [ 1 1 1 1], L_0x2dc1870, L_0x2dc1c40, L_0x2dc1f70, L_0x2dc1f00; +L_0x2dc2300 .concat8 [ 4 4 0 0], LS_0x2dc2300_0_0, LS_0x2dc2300_0_4; +L_0x2dc26c0 .part L_0x2dc0280, 7, 1; +L_0x2dc28b0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c12b40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c12d50 .param/l "i" 0 4 54, +C4<00>; +L_0x2dc0b50/d .functor AND 1, L_0x2dc0c60, L_0x2dc0e50, C4<1>, C4<1>; +L_0x2dc0b50 .delay 1 (30000,30000,30000) L_0x2dc0b50/d; +v0x2c12e30_0 .net *"_s0", 0 0, L_0x2dc0c60; 1 drivers +v0x2c12f10_0 .net *"_s1", 0 0, L_0x2dc0e50; 1 drivers +S_0x2c12ff0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c13200 .param/l "i" 0 4 54, +C4<01>; +L_0x2dc0ef0/d .functor AND 1, L_0x2dc0fb0, L_0x2dc1110, C4<1>, C4<1>; +L_0x2dc0ef0 .delay 1 (30000,30000,30000) L_0x2dc0ef0/d; +v0x2c132c0_0 .net *"_s0", 0 0, L_0x2dc0fb0; 1 drivers +v0x2c133a0_0 .net *"_s1", 0 0, L_0x2dc1110; 1 drivers +S_0x2c13480 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c136c0 .param/l "i" 0 4 54, +C4<010>; +L_0x2dc1200/d .functor AND 1, L_0x2dc12c0, L_0x2dc1420, C4<1>, C4<1>; +L_0x2dc1200 .delay 1 (30000,30000,30000) L_0x2dc1200/d; +v0x2c13760_0 .net *"_s0", 0 0, L_0x2dc12c0; 1 drivers +v0x2c13840_0 .net *"_s1", 0 0, L_0x2dc1420; 1 drivers +S_0x2c13920 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c13b30 .param/l "i" 0 4 54, +C4<011>; +L_0x2dc1510/d .functor AND 1, L_0x2dc15d0, L_0x2dc1730, C4<1>, C4<1>; +L_0x2dc1510 .delay 1 (30000,30000,30000) L_0x2dc1510/d; +v0x2c13bf0_0 .net *"_s0", 0 0, L_0x2dc15d0; 1 drivers +v0x2c13cd0_0 .net *"_s1", 0 0, L_0x2dc1730; 1 drivers +S_0x2c13db0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c14010 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dc1870/d .functor AND 1, L_0x2dc1930, L_0x2dc1ba0, C4<1>, C4<1>; +L_0x2dc1870 .delay 1 (30000,30000,30000) L_0x2dc1870/d; +v0x2c140d0_0 .net *"_s0", 0 0, L_0x2dc1930; 1 drivers +v0x2c141b0_0 .net *"_s1", 0 0, L_0x2dc1ba0; 1 drivers +S_0x2c14290 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c144a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dc1c40/d .functor AND 1, L_0x2dc1cb0, L_0x2dc1e10, C4<1>, C4<1>; +L_0x2dc1c40 .delay 1 (30000,30000,30000) L_0x2dc1c40/d; +v0x2c14560_0 .net *"_s0", 0 0, L_0x2dc1cb0; 1 drivers +v0x2c14640_0 .net *"_s1", 0 0, L_0x2dc1e10; 1 drivers +S_0x2c14720 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c14930 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dc1f70/d .functor AND 1, L_0x2dc2030, L_0x2dc2190, C4<1>, C4<1>; +L_0x2dc1f70 .delay 1 (30000,30000,30000) L_0x2dc1f70/d; +v0x2c149f0_0 .net *"_s0", 0 0, L_0x2dc2030; 1 drivers +v0x2c14ad0_0 .net *"_s1", 0 0, L_0x2dc2190; 1 drivers +S_0x2c14bb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c12900; + .timescale -9 -12; +P_0x2c14dc0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dc1f00/d .functor AND 1, L_0x2dc26c0, L_0x2dc28b0, C4<1>, C4<1>; +L_0x2dc1f00 .delay 1 (30000,30000,30000) L_0x2dc1f00/d; +v0x2c14e80_0 .net *"_s0", 0 0, L_0x2dc26c0; 1 drivers +v0x2c14f60_0 .net *"_s1", 0 0, L_0x2dc28b0; 1 drivers +S_0x2c15b20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c126b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12d6850/d .functor OR 1, L_0x12d6910, L_0x12d6ac0, C4<0>, C4<0>; -L_0x12d6850 .delay 1 (30000,30000,30000) L_0x12d6850/d; -v0x1143de0_0 .net *"_s10", 0 0, L_0x12d6910; 1 drivers -v0x1143ec0_0 .net *"_s12", 0 0, L_0x12d6ac0; 1 drivers -v0x1143fa0_0 .net "in", 7 0, L_0x12d4960; alias, 1 drivers -v0x1144070_0 .net "ors", 1 0, L_0x12d6670; 1 drivers -v0x1144130_0 .net "out", 0 0, L_0x12d6850; alias, 1 drivers -L_0x12d5a40 .part L_0x12d4960, 0, 4; -L_0x12d6670 .concat8 [ 1 1 0 0], L_0x12d5730, L_0x12d6360; -L_0x12d67b0 .part L_0x12d4960, 4, 4; -L_0x12d6910 .part L_0x12d6670, 0, 1; -L_0x12d6ac0 .part L_0x12d6670, 1, 1; -S_0x1142450 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1142290; +L_0x2dc4300/d .functor OR 1, L_0x2dc43c0, L_0x2dc4570, C4<0>, C4<0>; +L_0x2dc4300 .delay 1 (30000,30000,30000) L_0x2dc4300/d; +v0x2c17670_0 .net *"_s10", 0 0, L_0x2dc43c0; 1 drivers +v0x2c17750_0 .net *"_s12", 0 0, L_0x2dc4570; 1 drivers +v0x2c17830_0 .net "in", 7 0, L_0x2dc2300; alias, 1 drivers +v0x2c17900_0 .net "ors", 1 0, L_0x2dc4120; 1 drivers +v0x2c179c0_0 .net "out", 0 0, L_0x2dc4300; alias, 1 drivers +L_0x2dc34f0 .part L_0x2dc2300, 0, 4; +L_0x2dc4120 .concat8 [ 1 1 0 0], L_0x2dc31e0, L_0x2dc3e10; +L_0x2dc4260 .part L_0x2dc2300, 4, 4; +L_0x2dc43c0 .part L_0x2dc4120, 0, 1; +L_0x2dc4570 .part L_0x2dc4120, 1, 1; +S_0x2c15ce0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c15b20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12c0ff0/d .functor OR 1, L_0x12d4fb0, L_0x12d5110, C4<0>, C4<0>; -L_0x12c0ff0 .delay 1 (30000,30000,30000) L_0x12c0ff0/d; -L_0x12d5340/d .functor OR 1, L_0x12d5450, L_0x12d55b0, C4<0>, C4<0>; -L_0x12d5340 .delay 1 (30000,30000,30000) L_0x12d5340/d; -L_0x12d5730/d .functor OR 1, L_0x12d57a0, L_0x12d5950, C4<0>, C4<0>; -L_0x12d5730 .delay 1 (30000,30000,30000) L_0x12d5730/d; -v0x11426a0_0 .net *"_s0", 0 0, L_0x12c0ff0; 1 drivers -v0x11427a0_0 .net *"_s10", 0 0, L_0x12d5450; 1 drivers -v0x1142880_0 .net *"_s12", 0 0, L_0x12d55b0; 1 drivers -v0x1142940_0 .net *"_s14", 0 0, L_0x12d57a0; 1 drivers -v0x1142a20_0 .net *"_s16", 0 0, L_0x12d5950; 1 drivers -v0x1142b50_0 .net *"_s3", 0 0, L_0x12d4fb0; 1 drivers -v0x1142c30_0 .net *"_s5", 0 0, L_0x12d5110; 1 drivers -v0x1142d10_0 .net *"_s6", 0 0, L_0x12d5340; 1 drivers -v0x1142df0_0 .net "in", 3 0, L_0x12d5a40; 1 drivers -v0x1142f60_0 .net "ors", 1 0, L_0x12d5250; 1 drivers -v0x1143040_0 .net "out", 0 0, L_0x12d5730; 1 drivers -L_0x12d4fb0 .part L_0x12d5a40, 0, 1; -L_0x12d5110 .part L_0x12d5a40, 1, 1; -L_0x12d5250 .concat8 [ 1 1 0 0], L_0x12c0ff0, L_0x12d5340; -L_0x12d5450 .part L_0x12d5a40, 2, 1; -L_0x12d55b0 .part L_0x12d5a40, 3, 1; -L_0x12d57a0 .part L_0x12d5250, 0, 1; -L_0x12d5950 .part L_0x12d5250, 1, 1; -S_0x1143160 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1142290; +L_0x2dc29a0/d .functor OR 1, L_0x2dc2a60, L_0x2dc2bc0, C4<0>, C4<0>; +L_0x2dc29a0 .delay 1 (30000,30000,30000) L_0x2dc29a0/d; +L_0x2dc2df0/d .functor OR 1, L_0x2dc2f00, L_0x2dc3060, C4<0>, C4<0>; +L_0x2dc2df0 .delay 1 (30000,30000,30000) L_0x2dc2df0/d; +L_0x2dc31e0/d .functor OR 1, L_0x2dc3250, L_0x2dc3400, C4<0>, C4<0>; +L_0x2dc31e0 .delay 1 (30000,30000,30000) L_0x2dc31e0/d; +v0x2c15f30_0 .net *"_s0", 0 0, L_0x2dc29a0; 1 drivers +v0x2c16030_0 .net *"_s10", 0 0, L_0x2dc2f00; 1 drivers +v0x2c16110_0 .net *"_s12", 0 0, L_0x2dc3060; 1 drivers +v0x2c161d0_0 .net *"_s14", 0 0, L_0x2dc3250; 1 drivers +v0x2c162b0_0 .net *"_s16", 0 0, L_0x2dc3400; 1 drivers +v0x2c163e0_0 .net *"_s3", 0 0, L_0x2dc2a60; 1 drivers +v0x2c164c0_0 .net *"_s5", 0 0, L_0x2dc2bc0; 1 drivers +v0x2c165a0_0 .net *"_s6", 0 0, L_0x2dc2df0; 1 drivers +v0x2c16680_0 .net "in", 3 0, L_0x2dc34f0; 1 drivers +v0x2c167f0_0 .net "ors", 1 0, L_0x2dc2d00; 1 drivers +v0x2c168d0_0 .net "out", 0 0, L_0x2dc31e0; 1 drivers +L_0x2dc2a60 .part L_0x2dc34f0, 0, 1; +L_0x2dc2bc0 .part L_0x2dc34f0, 1, 1; +L_0x2dc2d00 .concat8 [ 1 1 0 0], L_0x2dc29a0, L_0x2dc2df0; +L_0x2dc2f00 .part L_0x2dc34f0, 2, 1; +L_0x2dc3060 .part L_0x2dc34f0, 3, 1; +L_0x2dc3250 .part L_0x2dc2d00, 0, 1; +L_0x2dc3400 .part L_0x2dc2d00, 1, 1; +S_0x2c169f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c15b20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12d5b70/d .functor OR 1, L_0x12d5be0, L_0x12d5d40, C4<0>, C4<0>; -L_0x12d5b70 .delay 1 (30000,30000,30000) L_0x12d5b70/d; -L_0x12d5f70/d .functor OR 1, L_0x12d6080, L_0x12d61e0, C4<0>, C4<0>; -L_0x12d5f70 .delay 1 (30000,30000,30000) L_0x12d5f70/d; -L_0x12d6360/d .functor OR 1, L_0x12d63d0, L_0x12d6580, C4<0>, C4<0>; -L_0x12d6360 .delay 1 (30000,30000,30000) L_0x12d6360/d; -v0x1143320_0 .net *"_s0", 0 0, L_0x12d5b70; 1 drivers -v0x1143420_0 .net *"_s10", 0 0, L_0x12d6080; 1 drivers -v0x1143500_0 .net *"_s12", 0 0, L_0x12d61e0; 1 drivers -v0x11435c0_0 .net *"_s14", 0 0, L_0x12d63d0; 1 drivers -v0x11436a0_0 .net *"_s16", 0 0, L_0x12d6580; 1 drivers -v0x11437d0_0 .net *"_s3", 0 0, L_0x12d5be0; 1 drivers -v0x11438b0_0 .net *"_s5", 0 0, L_0x12d5d40; 1 drivers -v0x1143990_0 .net *"_s6", 0 0, L_0x12d5f70; 1 drivers -v0x1143a70_0 .net "in", 3 0, L_0x12d67b0; 1 drivers -v0x1143be0_0 .net "ors", 1 0, L_0x12d5e80; 1 drivers -v0x1143cc0_0 .net "out", 0 0, L_0x12d6360; 1 drivers -L_0x12d5be0 .part L_0x12d67b0, 0, 1; -L_0x12d5d40 .part L_0x12d67b0, 1, 1; -L_0x12d5e80 .concat8 [ 1 1 0 0], L_0x12d5b70, L_0x12d5f70; -L_0x12d6080 .part L_0x12d67b0, 2, 1; -L_0x12d61e0 .part L_0x12d67b0, 3, 1; -L_0x12d63d0 .part L_0x12d5e80, 0, 1; -L_0x12d6580 .part L_0x12d5e80, 1, 1; -S_0x11445d0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1137f50; +L_0x2dc3620/d .functor OR 1, L_0x2dc3690, L_0x2dc37f0, C4<0>, C4<0>; +L_0x2dc3620 .delay 1 (30000,30000,30000) L_0x2dc3620/d; +L_0x2dc3a20/d .functor OR 1, L_0x2dc3b30, L_0x2dc3c90, C4<0>, C4<0>; +L_0x2dc3a20 .delay 1 (30000,30000,30000) L_0x2dc3a20/d; +L_0x2dc3e10/d .functor OR 1, L_0x2dc3e80, L_0x2dc4030, C4<0>, C4<0>; +L_0x2dc3e10 .delay 1 (30000,30000,30000) L_0x2dc3e10/d; +v0x2c16bb0_0 .net *"_s0", 0 0, L_0x2dc3620; 1 drivers +v0x2c16cb0_0 .net *"_s10", 0 0, L_0x2dc3b30; 1 drivers +v0x2c16d90_0 .net *"_s12", 0 0, L_0x2dc3c90; 1 drivers +v0x2c16e50_0 .net *"_s14", 0 0, L_0x2dc3e80; 1 drivers +v0x2c16f30_0 .net *"_s16", 0 0, L_0x2dc4030; 1 drivers +v0x2c17060_0 .net *"_s3", 0 0, L_0x2dc3690; 1 drivers +v0x2c17140_0 .net *"_s5", 0 0, L_0x2dc37f0; 1 drivers +v0x2c17220_0 .net *"_s6", 0 0, L_0x2dc3a20; 1 drivers +v0x2c17300_0 .net "in", 3 0, L_0x2dc4260; 1 drivers +v0x2c17470_0 .net "ors", 1 0, L_0x2dc3930; 1 drivers +v0x2c17550_0 .net "out", 0 0, L_0x2dc3e10; 1 drivers +L_0x2dc3690 .part L_0x2dc4260, 0, 1; +L_0x2dc37f0 .part L_0x2dc4260, 1, 1; +L_0x2dc3930 .concat8 [ 1 1 0 0], L_0x2dc3620, L_0x2dc3a20; +L_0x2dc3b30 .part L_0x2dc4260, 2, 1; +L_0x2dc3c90 .part L_0x2dc4260, 3, 1; +L_0x2dc3e80 .part L_0x2dc3930, 0, 1; +L_0x2dc4030 .part L_0x2dc3930, 1, 1; +S_0x2c17e60 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c0b7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -11798,80 +12482,80 @@ S_0x11445d0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1137f50; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12d2210/d .functor XNOR 1, L_0x123cb70, L_0x123ccd0, C4<0>, C4<0>; -L_0x12d2210 .delay 1 (20000,20000,20000) L_0x12d2210/d; -L_0x12d2480/d .functor AND 1, L_0x123cb70, L_0x12d1100, C4<1>, C4<1>; -L_0x12d2480 .delay 1 (30000,30000,30000) L_0x12d2480/d; -L_0x12d24f0/d .functor AND 1, L_0x12d2210, L_0x123cd70, C4<1>, C4<1>; -L_0x12d24f0 .delay 1 (30000,30000,30000) L_0x12d24f0/d; -L_0x12d2650/d .functor OR 1, L_0x12d24f0, L_0x12d2480, C4<0>, C4<0>; -L_0x12d2650 .delay 1 (30000,30000,30000) L_0x12d2650/d; -v0x1144880_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers -v0x1144970_0 .net "a_", 0 0, L_0x12d0ff0; alias, 1 drivers -v0x1144a30_0 .net "b", 0 0, L_0x123ccd0; alias, 1 drivers -v0x1144b20_0 .net "b_", 0 0, L_0x12d1100; alias, 1 drivers -v0x1144bc0_0 .net "carryin", 0 0, L_0x123cd70; alias, 1 drivers -v0x1144d00_0 .net "eq", 0 0, L_0x12d2210; 1 drivers -v0x1144dc0_0 .net "lt", 0 0, L_0x12d2480; 1 drivers -v0x1144e80_0 .net "out", 0 0, L_0x12d2650; 1 drivers -v0x1144f40_0 .net "w0", 0 0, L_0x12d24f0; 1 drivers -S_0x1145190 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1137f50; +L_0x2dbf130/d .functor XNOR 1, L_0x2d1da00, L_0x2d1daa0, C4<0>, C4<0>; +L_0x2dbf130 .delay 1 (20000,20000,20000) L_0x2dbf130/d; +L_0x2dbf2b0/d .functor AND 1, L_0x2d1da00, L_0x2dbde20, C4<1>, C4<1>; +L_0x2dbf2b0 .delay 1 (30000,30000,30000) L_0x2dbf2b0/d; +L_0x2dbf410/d .functor AND 1, L_0x2dbf130, L_0x2d1db40, C4<1>, C4<1>; +L_0x2dbf410 .delay 1 (30000,30000,30000) L_0x2dbf410/d; +L_0x2dbf520/d .functor OR 1, L_0x2dbf410, L_0x2dbf2b0, C4<0>, C4<0>; +L_0x2dbf520 .delay 1 (30000,30000,30000) L_0x2dbf520/d; +v0x2c18110_0 .net "a", 0 0, L_0x2d1da00; alias, 1 drivers +v0x2c18200_0 .net "a_", 0 0, L_0x2dbdd60; alias, 1 drivers +v0x2c182c0_0 .net "b", 0 0, L_0x2d1daa0; alias, 1 drivers +v0x2c183b0_0 .net "b_", 0 0, L_0x2dbde20; alias, 1 drivers +v0x2c18450_0 .net "carryin", 0 0, L_0x2d1db40; alias, 1 drivers +v0x2c18590_0 .net "eq", 0 0, L_0x2dbf130; 1 drivers +v0x2c18650_0 .net "lt", 0 0, L_0x2dbf2b0; 1 drivers +v0x2c18710_0 .net "out", 0 0, L_0x2dbf520; 1 drivers +v0x2c187d0_0 .net "w0", 0 0, L_0x2dbf410; 1 drivers +S_0x2c18a20 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c0b7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12d1ff0/d .functor OR 1, L_0x12d1af0, L_0x11463f0, C4<0>, C4<0>; -L_0x12d1ff0 .delay 1 (30000,30000,30000) L_0x12d1ff0/d; -v0x1145f80_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers -v0x11460d0_0 .net "b", 0 0, L_0x12d1100; alias, 1 drivers -v0x1146190_0 .net "c1", 0 0, L_0x12d1af0; 1 drivers -v0x1146230_0 .net "c2", 0 0, L_0x11463f0; 1 drivers -v0x1146300_0 .net "carryin", 0 0, L_0x123cd70; alias, 1 drivers -v0x1146480_0 .net "carryout", 0 0, L_0x12d1ff0; 1 drivers -v0x1146520_0 .net "s1", 0 0, L_0x12d1a30; 1 drivers -v0x11465c0_0 .net "sum", 0 0, L_0x12d1c50; 1 drivers -S_0x11453e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1145190; +L_0x2dbed10/d .functor OR 1, L_0x2dbe810, L_0x2c19c80, C4<0>, C4<0>; +L_0x2dbed10 .delay 1 (30000,30000,30000) L_0x2dbed10/d; +v0x2c19810_0 .net "a", 0 0, L_0x2d1da00; alias, 1 drivers +v0x2c19960_0 .net "b", 0 0, L_0x2dbde20; alias, 1 drivers +v0x2c19a20_0 .net "c1", 0 0, L_0x2dbe810; 1 drivers +v0x2c19ac0_0 .net "c2", 0 0, L_0x2c19c80; 1 drivers +v0x2c19b90_0 .net "carryin", 0 0, L_0x2d1db40; alias, 1 drivers +v0x2c19d10_0 .net "carryout", 0 0, L_0x2dbed10; 1 drivers +v0x2c19db0_0 .net "s1", 0 0, L_0x2dbe750; 1 drivers +v0x2c19e50_0 .net "sum", 0 0, L_0x2dbe970; 1 drivers +S_0x2c18c70 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c18a20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12d1a30/d .functor XOR 1, L_0x123cb70, L_0x12d1100, C4<0>, C4<0>; -L_0x12d1a30 .delay 1 (30000,30000,30000) L_0x12d1a30/d; -L_0x12d1af0/d .functor AND 1, L_0x123cb70, L_0x12d1100, C4<1>, C4<1>; -L_0x12d1af0 .delay 1 (30000,30000,30000) L_0x12d1af0/d; -v0x1145640_0 .net "a", 0 0, L_0x123cb70; alias, 1 drivers -v0x1145700_0 .net "b", 0 0, L_0x12d1100; alias, 1 drivers -v0x11457c0_0 .net "carryout", 0 0, L_0x12d1af0; alias, 1 drivers -v0x1145860_0 .net "sum", 0 0, L_0x12d1a30; alias, 1 drivers -S_0x1145990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1145190; +L_0x2dbe750/d .functor XOR 1, L_0x2d1da00, L_0x2dbde20, C4<0>, C4<0>; +L_0x2dbe750 .delay 1 (30000,30000,30000) L_0x2dbe750/d; +L_0x2dbe810/d .functor AND 1, L_0x2d1da00, L_0x2dbde20, C4<1>, C4<1>; +L_0x2dbe810 .delay 1 (30000,30000,30000) L_0x2dbe810/d; +v0x2c18ed0_0 .net "a", 0 0, L_0x2d1da00; alias, 1 drivers +v0x2c18f90_0 .net "b", 0 0, L_0x2dbde20; alias, 1 drivers +v0x2c19050_0 .net "carryout", 0 0, L_0x2dbe810; alias, 1 drivers +v0x2c190f0_0 .net "sum", 0 0, L_0x2dbe750; alias, 1 drivers +S_0x2c19220 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c18a20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12d1c50/d .functor XOR 1, L_0x12d1a30, L_0x123cd70, C4<0>, C4<0>; -L_0x12d1c50 .delay 1 (30000,30000,30000) L_0x12d1c50/d; -L_0x11463f0/d .functor AND 1, L_0x12d1a30, L_0x123cd70, C4<1>, C4<1>; -L_0x11463f0 .delay 1 (30000,30000,30000) L_0x11463f0/d; -v0x1145bf0_0 .net "a", 0 0, L_0x12d1a30; alias, 1 drivers -v0x1145cc0_0 .net "b", 0 0, L_0x123cd70; alias, 1 drivers -v0x1145d60_0 .net "carryout", 0 0, L_0x11463f0; alias, 1 drivers -v0x1145e30_0 .net "sum", 0 0, L_0x12d1c50; alias, 1 drivers -S_0x11479e0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1137c80; - .timescale -9 -12; -L_0x2b0ab3d067b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06800 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x123cc10/d .functor OR 1, L_0x2b0ab3d067b8, L_0x2b0ab3d06800, C4<0>, C4<0>; -L_0x123cc10 .delay 1 (30000,30000,30000) L_0x123cc10/d; -v0x1147bd0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d067b8; 1 drivers -v0x1147cb0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06800; 1 drivers -S_0x1147d90 .scope generate, "alu_slices[22]" "alu_slices[22]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1147fa0 .param/l "i" 0 3 41, +C4<010110>; -S_0x1148060 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1147d90; +L_0x2dbe970/d .functor XOR 1, L_0x2dbe750, L_0x2d1db40, C4<0>, C4<0>; +L_0x2dbe970 .delay 1 (30000,30000,30000) L_0x2dbe970/d; +L_0x2c19c80/d .functor AND 1, L_0x2dbe750, L_0x2d1db40, C4<1>, C4<1>; +L_0x2c19c80 .delay 1 (30000,30000,30000) L_0x2c19c80/d; +v0x2c19480_0 .net "a", 0 0, L_0x2dbe750; alias, 1 drivers +v0x2c19550_0 .net "b", 0 0, L_0x2d1db40; alias, 1 drivers +v0x2c195f0_0 .net "carryout", 0 0, L_0x2c19c80; alias, 1 drivers +v0x2c196c0_0 .net "sum", 0 0, L_0x2dbe970; alias, 1 drivers +S_0x2c1bee0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c0b510; + .timescale -9 -12; +L_0x2ac6110bb598 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb5e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dc05c0/d .functor OR 1, L_0x2ac6110bb598, L_0x2ac6110bb5e0, C4<0>, C4<0>; +L_0x2dc05c0 .delay 1 (30000,30000,30000) L_0x2dc05c0/d; +v0x2c1c0d0_0 .net/2u *"_s0", 0 0, L_0x2ac6110bb598; 1 drivers +v0x2c1c1b0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bb5e0; 1 drivers +S_0x2c1c290 .scope generate, "alu_slices[22]" "alu_slices[22]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c1c4a0 .param/l "i" 0 3 39, +C4<010110>; +S_0x2c1c560 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c1c290; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -11880,445 +12564,476 @@ S_0x1148060 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1147d90; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12d0e90/d .functor NOT 1, L_0x12e6510, C4<0>, C4<0>, C4<0>; -L_0x12d0e90 .delay 1 (10000,10000,10000) L_0x12d0e90/d; -L_0x12dcc90/d .functor NOT 1, L_0x12e6670, C4<0>, C4<0>, C4<0>; -L_0x12dcc90 .delay 1 (10000,10000,10000) L_0x12dcc90/d; -L_0x12ddc90/d .functor XOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; -L_0x12ddc90 .delay 1 (30000,30000,30000) L_0x12ddc90/d; -L_0x2b0ab3d06848 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06890 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12de340/d .functor OR 1, L_0x2b0ab3d06848, L_0x2b0ab3d06890, C4<0>, C4<0>; -L_0x12de340 .delay 1 (30000,30000,30000) L_0x12de340/d; -L_0x12de540/d .functor AND 1, L_0x12e6510, L_0x12e6670, C4<1>, C4<1>; -L_0x12de540 .delay 1 (30000,30000,30000) L_0x12de540/d; -L_0x12de600/d .functor NAND 1, L_0x12e6510, L_0x12e6670, C4<1>, C4<1>; -L_0x12de600 .delay 1 (20000,20000,20000) L_0x12de600/d; -L_0x12de760/d .functor XOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; -L_0x12de760 .delay 1 (20000,20000,20000) L_0x12de760/d; -L_0x12dec10/d .functor OR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; -L_0x12dec10 .delay 1 (30000,30000,30000) L_0x12dec10/d; -L_0x12e6410/d .functor NOT 1, L_0x12e25b0, C4<0>, C4<0>, C4<0>; -L_0x12e6410 .delay 1 (10000,10000,10000) L_0x12e6410/d; -v0x1156790_0 .net "A", 0 0, L_0x12e6510; 1 drivers -v0x1156850_0 .net "A_", 0 0, L_0x12d0e90; 1 drivers -v0x1156910_0 .net "B", 0 0, L_0x12e6670; 1 drivers -v0x11569e0_0 .net "B_", 0 0, L_0x12dcc90; 1 drivers -v0x1156a80_0 .net *"_s12", 0 0, L_0x12de340; 1 drivers -v0x1156b70_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06848; 1 drivers -v0x1156c30_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06890; 1 drivers -v0x1156d10_0 .net *"_s18", 0 0, L_0x12de540; 1 drivers -v0x1156df0_0 .net *"_s20", 0 0, L_0x12de600; 1 drivers -v0x1156f60_0 .net *"_s22", 0 0, L_0x12de760; 1 drivers -v0x1157040_0 .net *"_s24", 0 0, L_0x12dec10; 1 drivers -o0x2b0ab3cd97a8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1157120_0 name=_s30 -o0x2b0ab3cd97d8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1157200_0 name=_s32 -v0x11572e0_0 .net *"_s8", 0 0, L_0x12ddc90; 1 drivers -v0x11573c0_0 .net "carryin", 0 0, L_0x12dca20; 1 drivers -v0x1157460_0 .net "carryout", 0 0, L_0x12e60b0; 1 drivers -v0x1157500_0 .net "carryouts", 7 0, L_0x1355400; 1 drivers -v0x11576b0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1157750_0 .net "result", 0 0, L_0x12e25b0; 1 drivers -v0x1157840_0 .net "results", 7 0, L_0x12de9e0; 1 drivers -v0x1157950_0 .net "zero", 0 0, L_0x12e6410; 1 drivers -LS_0x12de9e0_0_0 .concat8 [ 1 1 1 1], L_0x12dd1b0, L_0x12dd7e0, L_0x12ddc90, L_0x12de340; -LS_0x12de9e0_0_4 .concat8 [ 1 1 1 1], L_0x12de540, L_0x12de600, L_0x12de760, L_0x12dec10; -L_0x12de9e0 .concat8 [ 4 4 0 0], LS_0x12de9e0_0_0, LS_0x12de9e0_0_4; -LS_0x1355400_0_0 .concat [ 1 1 1 1], L_0x12dd460, L_0x12ddb30, o0x2b0ab3cd97a8, L_0x12de190; -LS_0x1355400_0_4 .concat [ 4 0 0 0], o0x2b0ab3cd97d8; -L_0x1355400 .concat [ 4 4 0 0], LS_0x1355400_0_0, LS_0x1355400_0_4; -S_0x11482e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1148060; +L_0x2dbdb60/d .functor NOT 1, L_0x2dd4a10, C4<0>, C4<0>, C4<0>; +L_0x2dbdb60 .delay 1 (10000,10000,10000) L_0x2dbdb60/d; +L_0x2dca610/d .functor NOT 1, L_0x2dd4b70, C4<0>, C4<0>, C4<0>; +L_0x2dca610 .delay 1 (10000,10000,10000) L_0x2dca610/d; +L_0x2dcb660/d .functor XOR 1, L_0x2dd4a10, L_0x2dd4b70, C4<0>, C4<0>; +L_0x2dcb660 .delay 1 (30000,30000,30000) L_0x2dcb660/d; +L_0x2ac6110bb628 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb670 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcb720/d .functor OR 1, L_0x2ac6110bb628, L_0x2ac6110bb670, C4<0>, C4<0>; +L_0x2dcb720 .delay 1 (30000,30000,30000) L_0x2dcb720/d; +L_0x2ac6110bb6b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb700 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcbec0/d .functor OR 1, L_0x2ac6110bb6b8, L_0x2ac6110bb700, C4<0>, C4<0>; +L_0x2dcbec0 .delay 1 (30000,30000,30000) L_0x2dcbec0/d; +L_0x2dcc0c0/d .functor AND 1, L_0x2dd4a10, L_0x2dd4b70, C4<1>, C4<1>; +L_0x2dcc0c0 .delay 1 (30000,30000,30000) L_0x2dcc0c0/d; +L_0x2ac6110bb748 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb790 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcc180/d .functor OR 1, L_0x2ac6110bb748, L_0x2ac6110bb790, C4<0>, C4<0>; +L_0x2dcc180 .delay 1 (30000,30000,30000) L_0x2dcc180/d; +L_0x2dcc380/d .functor NAND 1, L_0x2dd4a10, L_0x2dd4b70, C4<1>, C4<1>; +L_0x2dcc380 .delay 1 (20000,20000,20000) L_0x2dcc380/d; +L_0x2ac6110bb7d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb820 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcc490/d .functor OR 1, L_0x2ac6110bb7d8, L_0x2ac6110bb820, C4<0>, C4<0>; +L_0x2dcc490 .delay 1 (30000,30000,30000) L_0x2dcc490/d; +L_0x2dcc640/d .functor NOR 1, L_0x2dd4a10, L_0x2dd4b70, C4<0>, C4<0>; +L_0x2dcc640 .delay 1 (20000,20000,20000) L_0x2dcc640/d; +L_0x2ac6110bb868 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb8b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcc910/d .functor OR 1, L_0x2ac6110bb868, L_0x2ac6110bb8b0, C4<0>, C4<0>; +L_0x2dcc910 .delay 1 (30000,30000,30000) L_0x2dcc910/d; +L_0x2dccd10/d .functor OR 1, L_0x2dd4a10, L_0x2dd4b70, C4<0>, C4<0>; +L_0x2dccd10 .delay 1 (30000,30000,30000) L_0x2dccd10/d; +L_0x2ac6110bb8f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb940 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcd1b0/d .functor OR 1, L_0x2ac6110bb8f8, L_0x2ac6110bb940, C4<0>, C4<0>; +L_0x2dcd1b0 .delay 1 (30000,30000,30000) L_0x2dcd1b0/d; +L_0x2dd4910/d .functor NOT 1, L_0x2dd0b70, C4<0>, C4<0>, C4<0>; +L_0x2dd4910 .delay 1 (10000,10000,10000) L_0x2dd4910/d; +v0x2c2ac90_0 .net "A", 0 0, L_0x2dd4a10; 1 drivers +v0x2c2ad50_0 .net "A_", 0 0, L_0x2dbdb60; 1 drivers +v0x2c2ae10_0 .net "B", 0 0, L_0x2dd4b70; 1 drivers +v0x2c2aee0_0 .net "B_", 0 0, L_0x2dca610; 1 drivers +v0x2c2af80_0 .net *"_s11", 0 0, L_0x2dcb720; 1 drivers +v0x2c2b070_0 .net/2s *"_s13", 0 0, L_0x2ac6110bb628; 1 drivers +v0x2c2b130_0 .net/2s *"_s15", 0 0, L_0x2ac6110bb670; 1 drivers +v0x2c2b210_0 .net *"_s19", 0 0, L_0x2dcbec0; 1 drivers +v0x2c2b2f0_0 .net/2s *"_s21", 0 0, L_0x2ac6110bb6b8; 1 drivers +v0x2c2b460_0 .net/2s *"_s23", 0 0, L_0x2ac6110bb700; 1 drivers +v0x2c2b540_0 .net *"_s25", 0 0, L_0x2dcc0c0; 1 drivers +v0x2c2b620_0 .net *"_s28", 0 0, L_0x2dcc180; 1 drivers +v0x2c2b700_0 .net/2s *"_s30", 0 0, L_0x2ac6110bb748; 1 drivers +v0x2c2b7e0_0 .net/2s *"_s32", 0 0, L_0x2ac6110bb790; 1 drivers +v0x2c2b8c0_0 .net *"_s34", 0 0, L_0x2dcc380; 1 drivers +v0x2c2b9a0_0 .net *"_s37", 0 0, L_0x2dcc490; 1 drivers +v0x2c2ba80_0 .net/2s *"_s39", 0 0, L_0x2ac6110bb7d8; 1 drivers +v0x2c2bc30_0 .net/2s *"_s41", 0 0, L_0x2ac6110bb820; 1 drivers +v0x2c2bcd0_0 .net *"_s43", 0 0, L_0x2dcc640; 1 drivers +v0x2c2bdb0_0 .net *"_s46", 0 0, L_0x2dcc910; 1 drivers +v0x2c2be90_0 .net/2s *"_s48", 0 0, L_0x2ac6110bb868; 1 drivers +v0x2c2bf70_0 .net/2s *"_s50", 0 0, L_0x2ac6110bb8b0; 1 drivers +v0x2c2c050_0 .net *"_s52", 0 0, L_0x2dccd10; 1 drivers +v0x2c2c130_0 .net *"_s56", 0 0, L_0x2dcd1b0; 1 drivers +v0x2c2c210_0 .net/2s *"_s59", 0 0, L_0x2ac6110bb8f8; 1 drivers +v0x2c2c2f0_0 .net/2s *"_s61", 0 0, L_0x2ac6110bb940; 1 drivers +v0x2c2c3d0_0 .net *"_s8", 0 0, L_0x2dcb660; 1 drivers +v0x2c2c4b0_0 .net "carryin", 0 0, L_0x2dca3f0; 1 drivers +v0x2c2c550_0 .net "carryout", 0 0, L_0x2dd45b0; 1 drivers +v0x2c2c5f0_0 .net "carryouts", 7 0, L_0x2dcce20; 1 drivers +v0x2c2c700_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c2c7c0_0 .net "result", 0 0, L_0x2dd0b70; 1 drivers +v0x2c2c8b0_0 .net "results", 7 0, L_0x2dccae0; 1 drivers +v0x2c2bb90_0 .net "zero", 0 0, L_0x2dd4910; 1 drivers +LS_0x2dccae0_0_0 .concat8 [ 1 1 1 1], L_0x2dcab30, L_0x2dcb160, L_0x2dcb660, L_0x2dcbec0; +LS_0x2dccae0_0_4 .concat8 [ 1 1 1 1], L_0x2dcc0c0, L_0x2dcc380, L_0x2dcc640, L_0x2dccd10; +L_0x2dccae0 .concat8 [ 4 4 0 0], LS_0x2dccae0_0_0, LS_0x2dccae0_0_4; +LS_0x2dcce20_0_0 .concat8 [ 1 1 1 1], L_0x2dcade0, L_0x2dcb500, L_0x2dcb720, L_0x2dcbd10; +LS_0x2dcce20_0_4 .concat8 [ 1 1 1 1], L_0x2dcc180, L_0x2dcc490, L_0x2dcc910, L_0x2dcd1b0; +L_0x2dcce20 .concat8 [ 4 4 0 0], LS_0x2dcce20_0_0, LS_0x2dcce20_0_4; +S_0x2c1c7e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c1c560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12dd460/d .functor OR 1, L_0x12dcf40, L_0x12dd300, C4<0>, C4<0>; -L_0x12dd460 .delay 1 (30000,30000,30000) L_0x12dd460/d; -v0x1149110_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers -v0x11491d0_0 .net "b", 0 0, L_0x12e6670; alias, 1 drivers -v0x11492a0_0 .net "c1", 0 0, L_0x12dcf40; 1 drivers -v0x11493a0_0 .net "c2", 0 0, L_0x12dd300; 1 drivers -v0x1149470_0 .net "carryin", 0 0, L_0x12dca20; alias, 1 drivers -v0x1149560_0 .net "carryout", 0 0, L_0x12dd460; 1 drivers -v0x1149600_0 .net "s1", 0 0, L_0x12dce80; 1 drivers -v0x11496f0_0 .net "sum", 0 0, L_0x12dd1b0; 1 drivers -S_0x1148550 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11482e0; +L_0x2dcade0/d .functor OR 1, L_0x2dca8c0, L_0x2dcac80, C4<0>, C4<0>; +L_0x2dcade0 .delay 1 (30000,30000,30000) L_0x2dcade0/d; +v0x2c1d610_0 .net "a", 0 0, L_0x2dd4a10; alias, 1 drivers +v0x2c1d6d0_0 .net "b", 0 0, L_0x2dd4b70; alias, 1 drivers +v0x2c1d7a0_0 .net "c1", 0 0, L_0x2dca8c0; 1 drivers +v0x2c1d8a0_0 .net "c2", 0 0, L_0x2dcac80; 1 drivers +v0x2c1d970_0 .net "carryin", 0 0, L_0x2dca3f0; alias, 1 drivers +v0x2c1da60_0 .net "carryout", 0 0, L_0x2dcade0; 1 drivers +v0x2c1db00_0 .net "s1", 0 0, L_0x2dca800; 1 drivers +v0x2c1dbf0_0 .net "sum", 0 0, L_0x2dcab30; 1 drivers +S_0x2c1ca50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c1c7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12dce80/d .functor XOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; -L_0x12dce80 .delay 1 (30000,30000,30000) L_0x12dce80/d; -L_0x12dcf40/d .functor AND 1, L_0x12e6510, L_0x12e6670, C4<1>, C4<1>; -L_0x12dcf40 .delay 1 (30000,30000,30000) L_0x12dcf40/d; -v0x11487b0_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers -v0x1148890_0 .net "b", 0 0, L_0x12e6670; alias, 1 drivers -v0x1148950_0 .net "carryout", 0 0, L_0x12dcf40; alias, 1 drivers -v0x11489f0_0 .net "sum", 0 0, L_0x12dce80; alias, 1 drivers -S_0x1148b30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11482e0; +L_0x2dca800/d .functor XOR 1, L_0x2dd4a10, L_0x2dd4b70, C4<0>, C4<0>; +L_0x2dca800 .delay 1 (30000,30000,30000) L_0x2dca800/d; +L_0x2dca8c0/d .functor AND 1, L_0x2dd4a10, L_0x2dd4b70, C4<1>, C4<1>; +L_0x2dca8c0 .delay 1 (30000,30000,30000) L_0x2dca8c0/d; +v0x2c1ccb0_0 .net "a", 0 0, L_0x2dd4a10; alias, 1 drivers +v0x2c1cd90_0 .net "b", 0 0, L_0x2dd4b70; alias, 1 drivers +v0x2c1ce50_0 .net "carryout", 0 0, L_0x2dca8c0; alias, 1 drivers +v0x2c1cef0_0 .net "sum", 0 0, L_0x2dca800; alias, 1 drivers +S_0x2c1d030 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c1c7e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12dd1b0/d .functor XOR 1, L_0x12dce80, L_0x12dca20, C4<0>, C4<0>; -L_0x12dd1b0 .delay 1 (30000,30000,30000) L_0x12dd1b0/d; -L_0x12dd300/d .functor AND 1, L_0x12dce80, L_0x12dca20, C4<1>, C4<1>; -L_0x12dd300 .delay 1 (30000,30000,30000) L_0x12dd300/d; -v0x1148d90_0 .net "a", 0 0, L_0x12dce80; alias, 1 drivers -v0x1148e30_0 .net "b", 0 0, L_0x12dca20; alias, 1 drivers -v0x1148ed0_0 .net "carryout", 0 0, L_0x12dd300; alias, 1 drivers -v0x1148fa0_0 .net "sum", 0 0, L_0x12dd1b0; alias, 1 drivers -S_0x11497c0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1148060; +L_0x2dcab30/d .functor XOR 1, L_0x2dca800, L_0x2dca3f0, C4<0>, C4<0>; +L_0x2dcab30 .delay 1 (30000,30000,30000) L_0x2dcab30/d; +L_0x2dcac80/d .functor AND 1, L_0x2dca800, L_0x2dca3f0, C4<1>, C4<1>; +L_0x2dcac80 .delay 1 (30000,30000,30000) L_0x2dcac80/d; +v0x2c1d290_0 .net "a", 0 0, L_0x2dca800; alias, 1 drivers +v0x2c1d330_0 .net "b", 0 0, L_0x2dca3f0; alias, 1 drivers +v0x2c1d3d0_0 .net "carryout", 0 0, L_0x2dcac80; alias, 1 drivers +v0x2c1d4a0_0 .net "sum", 0 0, L_0x2dcab30; alias, 1 drivers +S_0x2c1dcc0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c1c560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x114ebb0_0 .net "ands", 7 0, L_0x12e40b0; 1 drivers -v0x114ecc0_0 .net "in", 7 0, L_0x1355400; alias, 1 drivers -v0x114ed80_0 .net "out", 0 0, L_0x12e60b0; alias, 1 drivers -v0x114ee50_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11499e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11497c0; +v0x2c230b0_0 .net "ands", 7 0, L_0x2dd25b0; 1 drivers +v0x2c231c0_0 .net "in", 7 0, L_0x2dcce20; alias, 1 drivers +v0x2c23280_0 .net "out", 0 0, L_0x2dd45b0; alias, 1 drivers +v0x2c23350_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c1dee0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c1dcc0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x114c110_0 .net "A", 7 0, L_0x1355400; alias, 1 drivers -v0x114c210_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x114c2d0_0 .net *"_s0", 0 0, L_0x12e2910; 1 drivers -v0x114c390_0 .net *"_s12", 0 0, L_0x12e32e0; 1 drivers -v0x114c470_0 .net *"_s16", 0 0, L_0x12e3640; 1 drivers -v0x114c5a0_0 .net *"_s20", 0 0, L_0x12e3980; 1 drivers -v0x114c680_0 .net *"_s24", 0 0, L_0x12e3da0; 1 drivers -v0x114c760_0 .net *"_s28", 0 0, L_0x12e3d30; 1 drivers -v0x114c840_0 .net *"_s4", 0 0, L_0x12e2c20; 1 drivers -v0x114c9b0_0 .net *"_s8", 0 0, L_0x12e2f70; 1 drivers -v0x114ca90_0 .net "out", 7 0, L_0x12e40b0; alias, 1 drivers -L_0x12e29d0 .part L_0x1355400, 0, 1; -L_0x12e2b30 .part v0x12010b0_0, 0, 1; -L_0x12e2ce0 .part L_0x1355400, 1, 1; -L_0x12e2ed0 .part v0x12010b0_0, 1, 1; -L_0x12e3090 .part L_0x1355400, 2, 1; -L_0x12e31f0 .part v0x12010b0_0, 2, 1; -L_0x12e33a0 .part L_0x1355400, 3, 1; -L_0x12e3500 .part v0x12010b0_0, 3, 1; -L_0x12e3730 .part L_0x1355400, 4, 1; -L_0x12e3890 .part v0x12010b0_0, 4, 1; -L_0x12e3a20 .part L_0x1355400, 5, 1; -L_0x12e3c90 .part v0x12010b0_0, 5, 1; -L_0x12e3e60 .part L_0x1355400, 6, 1; -L_0x12e3fc0 .part v0x12010b0_0, 6, 1; -LS_0x12e40b0_0_0 .concat8 [ 1 1 1 1], L_0x12e2910, L_0x12e2c20, L_0x12e2f70, L_0x12e32e0; -LS_0x12e40b0_0_4 .concat8 [ 1 1 1 1], L_0x12e3640, L_0x12e3980, L_0x12e3da0, L_0x12e3d30; -L_0x12e40b0 .concat8 [ 4 4 0 0], LS_0x12e40b0_0_0, LS_0x12e40b0_0_4; -L_0x12e4470 .part L_0x1355400, 7, 1; -L_0x12e4660 .part v0x12010b0_0, 7, 1; -S_0x1149c40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x1149e50 .param/l "i" 0 4 54, +C4<00>; -L_0x12e2910/d .functor AND 1, L_0x12e29d0, L_0x12e2b30, C4<1>, C4<1>; -L_0x12e2910 .delay 1 (30000,30000,30000) L_0x12e2910/d; -v0x1149f30_0 .net *"_s0", 0 0, L_0x12e29d0; 1 drivers -v0x114a010_0 .net *"_s1", 0 0, L_0x12e2b30; 1 drivers -S_0x114a0f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114a300 .param/l "i" 0 4 54, +C4<01>; -L_0x12e2c20/d .functor AND 1, L_0x12e2ce0, L_0x12e2ed0, C4<1>, C4<1>; -L_0x12e2c20 .delay 1 (30000,30000,30000) L_0x12e2c20/d; -v0x114a3c0_0 .net *"_s0", 0 0, L_0x12e2ce0; 1 drivers -v0x114a4a0_0 .net *"_s1", 0 0, L_0x12e2ed0; 1 drivers -S_0x114a580 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114a790 .param/l "i" 0 4 54, +C4<010>; -L_0x12e2f70/d .functor AND 1, L_0x12e3090, L_0x12e31f0, C4<1>, C4<1>; -L_0x12e2f70 .delay 1 (30000,30000,30000) L_0x12e2f70/d; -v0x114a830_0 .net *"_s0", 0 0, L_0x12e3090; 1 drivers -v0x114a910_0 .net *"_s1", 0 0, L_0x12e31f0; 1 drivers -S_0x114a9f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114ac00 .param/l "i" 0 4 54, +C4<011>; -L_0x12e32e0/d .functor AND 1, L_0x12e33a0, L_0x12e3500, C4<1>, C4<1>; -L_0x12e32e0 .delay 1 (30000,30000,30000) L_0x12e32e0/d; -v0x114acc0_0 .net *"_s0", 0 0, L_0x12e33a0; 1 drivers -v0x114ada0_0 .net *"_s1", 0 0, L_0x12e3500; 1 drivers -S_0x114ae80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114b0e0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12e3640/d .functor AND 1, L_0x12e3730, L_0x12e3890, C4<1>, C4<1>; -L_0x12e3640 .delay 1 (30000,30000,30000) L_0x12e3640/d; -v0x114b1a0_0 .net *"_s0", 0 0, L_0x12e3730; 1 drivers -v0x114b280_0 .net *"_s1", 0 0, L_0x12e3890; 1 drivers -S_0x114b360 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114b570 .param/l "i" 0 4 54, +C4<0101>; -L_0x12e3980/d .functor AND 1, L_0x12e3a20, L_0x12e3c90, C4<1>, C4<1>; -L_0x12e3980 .delay 1 (30000,30000,30000) L_0x12e3980/d; -v0x114b630_0 .net *"_s0", 0 0, L_0x12e3a20; 1 drivers -v0x114b710_0 .net *"_s1", 0 0, L_0x12e3c90; 1 drivers -S_0x114b7f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114ba00 .param/l "i" 0 4 54, +C4<0110>; -L_0x12e3da0/d .functor AND 1, L_0x12e3e60, L_0x12e3fc0, C4<1>, C4<1>; -L_0x12e3da0 .delay 1 (30000,30000,30000) L_0x12e3da0/d; -v0x114bac0_0 .net *"_s0", 0 0, L_0x12e3e60; 1 drivers -v0x114bba0_0 .net *"_s1", 0 0, L_0x12e3fc0; 1 drivers -S_0x114bc80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11499e0; - .timescale -9 -12; -P_0x114be90 .param/l "i" 0 4 54, +C4<0111>; -L_0x12e3d30/d .functor AND 1, L_0x12e4470, L_0x12e4660, C4<1>, C4<1>; -L_0x12e3d30 .delay 1 (30000,30000,30000) L_0x12e3d30/d; -v0x114bf50_0 .net *"_s0", 0 0, L_0x12e4470; 1 drivers -v0x114c030_0 .net *"_s1", 0 0, L_0x12e4660; 1 drivers -S_0x114cbf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11497c0; +v0x2c20610_0 .net "A", 7 0, L_0x2dcce20; alias, 1 drivers +v0x2c20710_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c207d0_0 .net *"_s0", 0 0, L_0x2dd0ed0; 1 drivers +v0x2c20890_0 .net *"_s12", 0 0, L_0x2dd1840; 1 drivers +v0x2c20970_0 .net *"_s16", 0 0, L_0x2dd1ba0; 1 drivers +v0x2c20aa0_0 .net *"_s20", 0 0, L_0x2dd1f70; 1 drivers +v0x2c20b80_0 .net *"_s24", 0 0, L_0x2dd22a0; 1 drivers +v0x2c20c60_0 .net *"_s28", 0 0, L_0x2dd2230; 1 drivers +v0x2c20d40_0 .net *"_s4", 0 0, L_0x2dd1220; 1 drivers +v0x2c20eb0_0 .net *"_s8", 0 0, L_0x2dd1530; 1 drivers +v0x2c20f90_0 .net "out", 7 0, L_0x2dd25b0; alias, 1 drivers +L_0x2dd0f90 .part L_0x2dcce20, 0, 1; +L_0x2dd1180 .part v0x2cdd2e0_0, 0, 1; +L_0x2dd12e0 .part L_0x2dcce20, 1, 1; +L_0x2dd1440 .part v0x2cdd2e0_0, 1, 1; +L_0x2dd15f0 .part L_0x2dcce20, 2, 1; +L_0x2dd1750 .part v0x2cdd2e0_0, 2, 1; +L_0x2dd1900 .part L_0x2dcce20, 3, 1; +L_0x2dd1a60 .part v0x2cdd2e0_0, 3, 1; +L_0x2dd1c60 .part L_0x2dcce20, 4, 1; +L_0x2dd1ed0 .part v0x2cdd2e0_0, 4, 1; +L_0x2dd1fe0 .part L_0x2dcce20, 5, 1; +L_0x2dd2140 .part v0x2cdd2e0_0, 5, 1; +L_0x2dd2360 .part L_0x2dcce20, 6, 1; +L_0x2dd24c0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dd25b0_0_0 .concat8 [ 1 1 1 1], L_0x2dd0ed0, L_0x2dd1220, L_0x2dd1530, L_0x2dd1840; +LS_0x2dd25b0_0_4 .concat8 [ 1 1 1 1], L_0x2dd1ba0, L_0x2dd1f70, L_0x2dd22a0, L_0x2dd2230; +L_0x2dd25b0 .concat8 [ 4 4 0 0], LS_0x2dd25b0_0_0, LS_0x2dd25b0_0_4; +L_0x2dd2970 .part L_0x2dcce20, 7, 1; +L_0x2dd2b60 .part v0x2cdd2e0_0, 7, 1; +S_0x2c1e140 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1e350 .param/l "i" 0 4 54, +C4<00>; +L_0x2dd0ed0/d .functor AND 1, L_0x2dd0f90, L_0x2dd1180, C4<1>, C4<1>; +L_0x2dd0ed0 .delay 1 (30000,30000,30000) L_0x2dd0ed0/d; +v0x2c1e430_0 .net *"_s0", 0 0, L_0x2dd0f90; 1 drivers +v0x2c1e510_0 .net *"_s1", 0 0, L_0x2dd1180; 1 drivers +S_0x2c1e5f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1e800 .param/l "i" 0 4 54, +C4<01>; +L_0x2dd1220/d .functor AND 1, L_0x2dd12e0, L_0x2dd1440, C4<1>, C4<1>; +L_0x2dd1220 .delay 1 (30000,30000,30000) L_0x2dd1220/d; +v0x2c1e8c0_0 .net *"_s0", 0 0, L_0x2dd12e0; 1 drivers +v0x2c1e9a0_0 .net *"_s1", 0 0, L_0x2dd1440; 1 drivers +S_0x2c1ea80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1ec90 .param/l "i" 0 4 54, +C4<010>; +L_0x2dd1530/d .functor AND 1, L_0x2dd15f0, L_0x2dd1750, C4<1>, C4<1>; +L_0x2dd1530 .delay 1 (30000,30000,30000) L_0x2dd1530/d; +v0x2c1ed30_0 .net *"_s0", 0 0, L_0x2dd15f0; 1 drivers +v0x2c1ee10_0 .net *"_s1", 0 0, L_0x2dd1750; 1 drivers +S_0x2c1eef0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1f100 .param/l "i" 0 4 54, +C4<011>; +L_0x2dd1840/d .functor AND 1, L_0x2dd1900, L_0x2dd1a60, C4<1>, C4<1>; +L_0x2dd1840 .delay 1 (30000,30000,30000) L_0x2dd1840/d; +v0x2c1f1c0_0 .net *"_s0", 0 0, L_0x2dd1900; 1 drivers +v0x2c1f2a0_0 .net *"_s1", 0 0, L_0x2dd1a60; 1 drivers +S_0x2c1f380 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1f5e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dd1ba0/d .functor AND 1, L_0x2dd1c60, L_0x2dd1ed0, C4<1>, C4<1>; +L_0x2dd1ba0 .delay 1 (30000,30000,30000) L_0x2dd1ba0/d; +v0x2c1f6a0_0 .net *"_s0", 0 0, L_0x2dd1c60; 1 drivers +v0x2c1f780_0 .net *"_s1", 0 0, L_0x2dd1ed0; 1 drivers +S_0x2c1f860 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1fa70 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dd1f70/d .functor AND 1, L_0x2dd1fe0, L_0x2dd2140, C4<1>, C4<1>; +L_0x2dd1f70 .delay 1 (30000,30000,30000) L_0x2dd1f70/d; +v0x2c1fb30_0 .net *"_s0", 0 0, L_0x2dd1fe0; 1 drivers +v0x2c1fc10_0 .net *"_s1", 0 0, L_0x2dd2140; 1 drivers +S_0x2c1fcf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c1ff00 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dd22a0/d .functor AND 1, L_0x2dd2360, L_0x2dd24c0, C4<1>, C4<1>; +L_0x2dd22a0 .delay 1 (30000,30000,30000) L_0x2dd22a0/d; +v0x2c1ffc0_0 .net *"_s0", 0 0, L_0x2dd2360; 1 drivers +v0x2c200a0_0 .net *"_s1", 0 0, L_0x2dd24c0; 1 drivers +S_0x2c20180 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c1dee0; + .timescale -9 -12; +P_0x2c20390 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dd2230/d .functor AND 1, L_0x2dd2970, L_0x2dd2b60, C4<1>, C4<1>; +L_0x2dd2230 .delay 1 (30000,30000,30000) L_0x2dd2230/d; +v0x2c20450_0 .net *"_s0", 0 0, L_0x2dd2970; 1 drivers +v0x2c20530_0 .net *"_s1", 0 0, L_0x2dd2b60; 1 drivers +S_0x2c210f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c1dcc0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12e60b0/d .functor OR 1, L_0x12e6170, L_0x12e6320, C4<0>, C4<0>; -L_0x12e60b0 .delay 1 (30000,30000,30000) L_0x12e60b0/d; -v0x114e740_0 .net *"_s10", 0 0, L_0x12e6170; 1 drivers -v0x114e820_0 .net *"_s12", 0 0, L_0x12e6320; 1 drivers -v0x114e900_0 .net "in", 7 0, L_0x12e40b0; alias, 1 drivers -v0x114e9d0_0 .net "ors", 1 0, L_0x12e5ed0; 1 drivers -v0x114ea90_0 .net "out", 0 0, L_0x12e60b0; alias, 1 drivers -L_0x12e52a0 .part L_0x12e40b0, 0, 4; -L_0x12e5ed0 .concat8 [ 1 1 0 0], L_0x12e4f90, L_0x12e5bc0; -L_0x12e6010 .part L_0x12e40b0, 4, 4; -L_0x12e6170 .part L_0x12e5ed0, 0, 1; -L_0x12e6320 .part L_0x12e5ed0, 1, 1; -S_0x114cdb0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x114cbf0; +L_0x2dd45b0/d .functor OR 1, L_0x2dd4670, L_0x2dd4820, C4<0>, C4<0>; +L_0x2dd45b0 .delay 1 (30000,30000,30000) L_0x2dd45b0/d; +v0x2c22c40_0 .net *"_s10", 0 0, L_0x2dd4670; 1 drivers +v0x2c22d20_0 .net *"_s12", 0 0, L_0x2dd4820; 1 drivers +v0x2c22e00_0 .net "in", 7 0, L_0x2dd25b0; alias, 1 drivers +v0x2c22ed0_0 .net "ors", 1 0, L_0x2dd43d0; 1 drivers +v0x2c22f90_0 .net "out", 0 0, L_0x2dd45b0; alias, 1 drivers +L_0x2dd37a0 .part L_0x2dd25b0, 0, 4; +L_0x2dd43d0 .concat8 [ 1 1 0 0], L_0x2dd3490, L_0x2dd40c0; +L_0x2dd4510 .part L_0x2dd25b0, 4, 4; +L_0x2dd4670 .part L_0x2dd43d0, 0, 1; +L_0x2dd4820 .part L_0x2dd43d0, 1, 1; +S_0x2c212b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c210f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12e4750/d .functor OR 1, L_0x12e4810, L_0x12e4970, C4<0>, C4<0>; -L_0x12e4750 .delay 1 (30000,30000,30000) L_0x12e4750/d; -L_0x12e4ba0/d .functor OR 1, L_0x12e4cb0, L_0x12e4e10, C4<0>, C4<0>; -L_0x12e4ba0 .delay 1 (30000,30000,30000) L_0x12e4ba0/d; -L_0x12e4f90/d .functor OR 1, L_0x12e5000, L_0x12e51b0, C4<0>, C4<0>; -L_0x12e4f90 .delay 1 (30000,30000,30000) L_0x12e4f90/d; -v0x114d000_0 .net *"_s0", 0 0, L_0x12e4750; 1 drivers -v0x114d100_0 .net *"_s10", 0 0, L_0x12e4cb0; 1 drivers -v0x114d1e0_0 .net *"_s12", 0 0, L_0x12e4e10; 1 drivers -v0x114d2a0_0 .net *"_s14", 0 0, L_0x12e5000; 1 drivers -v0x114d380_0 .net *"_s16", 0 0, L_0x12e51b0; 1 drivers -v0x114d4b0_0 .net *"_s3", 0 0, L_0x12e4810; 1 drivers -v0x114d590_0 .net *"_s5", 0 0, L_0x12e4970; 1 drivers -v0x114d670_0 .net *"_s6", 0 0, L_0x12e4ba0; 1 drivers -v0x114d750_0 .net "in", 3 0, L_0x12e52a0; 1 drivers -v0x114d8c0_0 .net "ors", 1 0, L_0x12e4ab0; 1 drivers -v0x114d9a0_0 .net "out", 0 0, L_0x12e4f90; 1 drivers -L_0x12e4810 .part L_0x12e52a0, 0, 1; -L_0x12e4970 .part L_0x12e52a0, 1, 1; -L_0x12e4ab0 .concat8 [ 1 1 0 0], L_0x12e4750, L_0x12e4ba0; -L_0x12e4cb0 .part L_0x12e52a0, 2, 1; -L_0x12e4e10 .part L_0x12e52a0, 3, 1; -L_0x12e5000 .part L_0x12e4ab0, 0, 1; -L_0x12e51b0 .part L_0x12e4ab0, 1, 1; -S_0x114dac0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x114cbf0; +L_0x2dd2c50/d .functor OR 1, L_0x2dd2d10, L_0x2dd2e70, C4<0>, C4<0>; +L_0x2dd2c50 .delay 1 (30000,30000,30000) L_0x2dd2c50/d; +L_0x2dd30a0/d .functor OR 1, L_0x2dd31b0, L_0x2dd3310, C4<0>, C4<0>; +L_0x2dd30a0 .delay 1 (30000,30000,30000) L_0x2dd30a0/d; +L_0x2dd3490/d .functor OR 1, L_0x2dd3500, L_0x2dd36b0, C4<0>, C4<0>; +L_0x2dd3490 .delay 1 (30000,30000,30000) L_0x2dd3490/d; +v0x2c21500_0 .net *"_s0", 0 0, L_0x2dd2c50; 1 drivers +v0x2c21600_0 .net *"_s10", 0 0, L_0x2dd31b0; 1 drivers +v0x2c216e0_0 .net *"_s12", 0 0, L_0x2dd3310; 1 drivers +v0x2c217a0_0 .net *"_s14", 0 0, L_0x2dd3500; 1 drivers +v0x2c21880_0 .net *"_s16", 0 0, L_0x2dd36b0; 1 drivers +v0x2c219b0_0 .net *"_s3", 0 0, L_0x2dd2d10; 1 drivers +v0x2c21a90_0 .net *"_s5", 0 0, L_0x2dd2e70; 1 drivers +v0x2c21b70_0 .net *"_s6", 0 0, L_0x2dd30a0; 1 drivers +v0x2c21c50_0 .net "in", 3 0, L_0x2dd37a0; 1 drivers +v0x2c21dc0_0 .net "ors", 1 0, L_0x2dd2fb0; 1 drivers +v0x2c21ea0_0 .net "out", 0 0, L_0x2dd3490; 1 drivers +L_0x2dd2d10 .part L_0x2dd37a0, 0, 1; +L_0x2dd2e70 .part L_0x2dd37a0, 1, 1; +L_0x2dd2fb0 .concat8 [ 1 1 0 0], L_0x2dd2c50, L_0x2dd30a0; +L_0x2dd31b0 .part L_0x2dd37a0, 2, 1; +L_0x2dd3310 .part L_0x2dd37a0, 3, 1; +L_0x2dd3500 .part L_0x2dd2fb0, 0, 1; +L_0x2dd36b0 .part L_0x2dd2fb0, 1, 1; +S_0x2c21fc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c210f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12e53d0/d .functor OR 1, L_0x12e5440, L_0x12e55a0, C4<0>, C4<0>; -L_0x12e53d0 .delay 1 (30000,30000,30000) L_0x12e53d0/d; -L_0x12e57d0/d .functor OR 1, L_0x12e58e0, L_0x12e5a40, C4<0>, C4<0>; -L_0x12e57d0 .delay 1 (30000,30000,30000) L_0x12e57d0/d; -L_0x12e5bc0/d .functor OR 1, L_0x12e5c30, L_0x12e5de0, C4<0>, C4<0>; -L_0x12e5bc0 .delay 1 (30000,30000,30000) L_0x12e5bc0/d; -v0x114dc80_0 .net *"_s0", 0 0, L_0x12e53d0; 1 drivers -v0x114dd80_0 .net *"_s10", 0 0, L_0x12e58e0; 1 drivers -v0x114de60_0 .net *"_s12", 0 0, L_0x12e5a40; 1 drivers -v0x114df20_0 .net *"_s14", 0 0, L_0x12e5c30; 1 drivers -v0x114e000_0 .net *"_s16", 0 0, L_0x12e5de0; 1 drivers -v0x114e130_0 .net *"_s3", 0 0, L_0x12e5440; 1 drivers -v0x114e210_0 .net *"_s5", 0 0, L_0x12e55a0; 1 drivers -v0x114e2f0_0 .net *"_s6", 0 0, L_0x12e57d0; 1 drivers -v0x114e3d0_0 .net "in", 3 0, L_0x12e6010; 1 drivers -v0x114e540_0 .net "ors", 1 0, L_0x12e56e0; 1 drivers -v0x114e620_0 .net "out", 0 0, L_0x12e5bc0; 1 drivers -L_0x12e5440 .part L_0x12e6010, 0, 1; -L_0x12e55a0 .part L_0x12e6010, 1, 1; -L_0x12e56e0 .concat8 [ 1 1 0 0], L_0x12e53d0, L_0x12e57d0; -L_0x12e58e0 .part L_0x12e6010, 2, 1; -L_0x12e5a40 .part L_0x12e6010, 3, 1; -L_0x12e5c30 .part L_0x12e56e0, 0, 1; -L_0x12e5de0 .part L_0x12e56e0, 1, 1; -S_0x114ef30 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1148060; +L_0x2dd38d0/d .functor OR 1, L_0x2dd3940, L_0x2dd3aa0, C4<0>, C4<0>; +L_0x2dd38d0 .delay 1 (30000,30000,30000) L_0x2dd38d0/d; +L_0x2dd3cd0/d .functor OR 1, L_0x2dd3de0, L_0x2dd3f40, C4<0>, C4<0>; +L_0x2dd3cd0 .delay 1 (30000,30000,30000) L_0x2dd3cd0/d; +L_0x2dd40c0/d .functor OR 1, L_0x2dd4130, L_0x2dd42e0, C4<0>, C4<0>; +L_0x2dd40c0 .delay 1 (30000,30000,30000) L_0x2dd40c0/d; +v0x2c22180_0 .net *"_s0", 0 0, L_0x2dd38d0; 1 drivers +v0x2c22280_0 .net *"_s10", 0 0, L_0x2dd3de0; 1 drivers +v0x2c22360_0 .net *"_s12", 0 0, L_0x2dd3f40; 1 drivers +v0x2c22420_0 .net *"_s14", 0 0, L_0x2dd4130; 1 drivers +v0x2c22500_0 .net *"_s16", 0 0, L_0x2dd42e0; 1 drivers +v0x2c22630_0 .net *"_s3", 0 0, L_0x2dd3940; 1 drivers +v0x2c22710_0 .net *"_s5", 0 0, L_0x2dd3aa0; 1 drivers +v0x2c227f0_0 .net *"_s6", 0 0, L_0x2dd3cd0; 1 drivers +v0x2c228d0_0 .net "in", 3 0, L_0x2dd4510; 1 drivers +v0x2c22a40_0 .net "ors", 1 0, L_0x2dd3be0; 1 drivers +v0x2c22b20_0 .net "out", 0 0, L_0x2dd40c0; 1 drivers +L_0x2dd3940 .part L_0x2dd4510, 0, 1; +L_0x2dd3aa0 .part L_0x2dd4510, 1, 1; +L_0x2dd3be0 .concat8 [ 1 1 0 0], L_0x2dd38d0, L_0x2dd3cd0; +L_0x2dd3de0 .part L_0x2dd4510, 2, 1; +L_0x2dd3f40 .part L_0x2dd4510, 3, 1; +L_0x2dd4130 .part L_0x2dd3be0, 0, 1; +L_0x2dd42e0 .part L_0x2dd3be0, 1, 1; +S_0x2c23430 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c1c560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1154360_0 .net "ands", 7 0, L_0x12e0580; 1 drivers -v0x1154470_0 .net "in", 7 0, L_0x12de9e0; alias, 1 drivers -v0x1154530_0 .net "out", 0 0, L_0x12e25b0; alias, 1 drivers -v0x1154600_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x114f180 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x114ef30; +v0x2c28860_0 .net "ands", 7 0, L_0x2dceb70; 1 drivers +v0x2c28970_0 .net "in", 7 0, L_0x2dccae0; alias, 1 drivers +v0x2c28a30_0 .net "out", 0 0, L_0x2dd0b70; alias, 1 drivers +v0x2c28b00_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c23680 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c23430; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11518c0_0 .net "A", 7 0, L_0x12de9e0; alias, 1 drivers -v0x11519c0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1151a80_0 .net *"_s0", 0 0, L_0x12ded70; 1 drivers -v0x1151b40_0 .net *"_s12", 0 0, L_0x12df730; 1 drivers -v0x1151c20_0 .net *"_s16", 0 0, L_0x12dfa90; 1 drivers -v0x1151d50_0 .net *"_s20", 0 0, L_0x12dfec0; 1 drivers -v0x1151e30_0 .net *"_s24", 0 0, L_0x12e01f0; 1 drivers -v0x1151f10_0 .net *"_s28", 0 0, L_0x12e0180; 1 drivers -v0x1151ff0_0 .net *"_s4", 0 0, L_0x12df110; 1 drivers -v0x1152160_0 .net *"_s8", 0 0, L_0x12df420; 1 drivers -v0x1152240_0 .net "out", 7 0, L_0x12e0580; alias, 1 drivers -L_0x12dee80 .part L_0x12de9e0, 0, 1; -L_0x12df070 .part v0x12010b0_0, 0, 1; -L_0x12df1d0 .part L_0x12de9e0, 1, 1; -L_0x12df330 .part v0x12010b0_0, 1, 1; -L_0x12df4e0 .part L_0x12de9e0, 2, 1; -L_0x12df640 .part v0x12010b0_0, 2, 1; -L_0x12df7f0 .part L_0x12de9e0, 3, 1; -L_0x12df950 .part v0x12010b0_0, 3, 1; -L_0x12dfb50 .part L_0x12de9e0, 4, 1; -L_0x12dfdc0 .part v0x12010b0_0, 4, 1; -L_0x12dff30 .part L_0x12de9e0, 5, 1; -L_0x12e0090 .part v0x12010b0_0, 5, 1; -L_0x12e02b0 .part L_0x12de9e0, 6, 1; -L_0x12e0410 .part v0x12010b0_0, 6, 1; -LS_0x12e0580_0_0 .concat8 [ 1 1 1 1], L_0x12ded70, L_0x12df110, L_0x12df420, L_0x12df730; -LS_0x12e0580_0_4 .concat8 [ 1 1 1 1], L_0x12dfa90, L_0x12dfec0, L_0x12e01f0, L_0x12e0180; -L_0x12e0580 .concat8 [ 4 4 0 0], LS_0x12e0580_0_0, LS_0x12e0580_0_4; -L_0x12e0940 .part L_0x12de9e0, 7, 1; -L_0x12e0b30 .part v0x12010b0_0, 7, 1; -S_0x114f3c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x114f5d0 .param/l "i" 0 4 54, +C4<00>; -L_0x12ded70/d .functor AND 1, L_0x12dee80, L_0x12df070, C4<1>, C4<1>; -L_0x12ded70 .delay 1 (30000,30000,30000) L_0x12ded70/d; -v0x114f6b0_0 .net *"_s0", 0 0, L_0x12dee80; 1 drivers -v0x114f790_0 .net *"_s1", 0 0, L_0x12df070; 1 drivers -S_0x114f870 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x114fa80 .param/l "i" 0 4 54, +C4<01>; -L_0x12df110/d .functor AND 1, L_0x12df1d0, L_0x12df330, C4<1>, C4<1>; -L_0x12df110 .delay 1 (30000,30000,30000) L_0x12df110/d; -v0x114fb40_0 .net *"_s0", 0 0, L_0x12df1d0; 1 drivers -v0x114fc20_0 .net *"_s1", 0 0, L_0x12df330; 1 drivers -S_0x114fd00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x114ff40 .param/l "i" 0 4 54, +C4<010>; -L_0x12df420/d .functor AND 1, L_0x12df4e0, L_0x12df640, C4<1>, C4<1>; -L_0x12df420 .delay 1 (30000,30000,30000) L_0x12df420/d; -v0x114ffe0_0 .net *"_s0", 0 0, L_0x12df4e0; 1 drivers -v0x11500c0_0 .net *"_s1", 0 0, L_0x12df640; 1 drivers -S_0x11501a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x11503b0 .param/l "i" 0 4 54, +C4<011>; -L_0x12df730/d .functor AND 1, L_0x12df7f0, L_0x12df950, C4<1>, C4<1>; -L_0x12df730 .delay 1 (30000,30000,30000) L_0x12df730/d; -v0x1150470_0 .net *"_s0", 0 0, L_0x12df7f0; 1 drivers -v0x1150550_0 .net *"_s1", 0 0, L_0x12df950; 1 drivers -S_0x1150630 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x1150890 .param/l "i" 0 4 54, +C4<0100>; -L_0x12dfa90/d .functor AND 1, L_0x12dfb50, L_0x12dfdc0, C4<1>, C4<1>; -L_0x12dfa90 .delay 1 (30000,30000,30000) L_0x12dfa90/d; -v0x1150950_0 .net *"_s0", 0 0, L_0x12dfb50; 1 drivers -v0x1150a30_0 .net *"_s1", 0 0, L_0x12dfdc0; 1 drivers -S_0x1150b10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x1150d20 .param/l "i" 0 4 54, +C4<0101>; -L_0x12dfec0/d .functor AND 1, L_0x12dff30, L_0x12e0090, C4<1>, C4<1>; -L_0x12dfec0 .delay 1 (30000,30000,30000) L_0x12dfec0/d; -v0x1150de0_0 .net *"_s0", 0 0, L_0x12dff30; 1 drivers -v0x1150ec0_0 .net *"_s1", 0 0, L_0x12e0090; 1 drivers -S_0x1150fa0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x11511b0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12e01f0/d .functor AND 1, L_0x12e02b0, L_0x12e0410, C4<1>, C4<1>; -L_0x12e01f0 .delay 1 (30000,30000,30000) L_0x12e01f0/d; -v0x1151270_0 .net *"_s0", 0 0, L_0x12e02b0; 1 drivers -v0x1151350_0 .net *"_s1", 0 0, L_0x12e0410; 1 drivers -S_0x1151430 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x114f180; - .timescale -9 -12; -P_0x1151640 .param/l "i" 0 4 54, +C4<0111>; -L_0x12e0180/d .functor AND 1, L_0x12e0940, L_0x12e0b30, C4<1>, C4<1>; -L_0x12e0180 .delay 1 (30000,30000,30000) L_0x12e0180/d; -v0x1151700_0 .net *"_s0", 0 0, L_0x12e0940; 1 drivers -v0x11517e0_0 .net *"_s1", 0 0, L_0x12e0b30; 1 drivers -S_0x11523a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x114ef30; +v0x2c25dc0_0 .net "A", 7 0, L_0x2dccae0; alias, 1 drivers +v0x2c25ec0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c25f80_0 .net *"_s0", 0 0, L_0x2dcd360; 1 drivers +v0x2c26040_0 .net *"_s12", 0 0, L_0x2dcdd20; 1 drivers +v0x2c26120_0 .net *"_s16", 0 0, L_0x2dce080; 1 drivers +v0x2c26250_0 .net *"_s20", 0 0, L_0x2dce4b0; 1 drivers +v0x2c26330_0 .net *"_s24", 0 0, L_0x2dce7e0; 1 drivers +v0x2c26410_0 .net *"_s28", 0 0, L_0x2dce770; 1 drivers +v0x2c264f0_0 .net *"_s4", 0 0, L_0x2dcd700; 1 drivers +v0x2c26660_0 .net *"_s8", 0 0, L_0x2dcda10; 1 drivers +v0x2c26740_0 .net "out", 7 0, L_0x2dceb70; alias, 1 drivers +L_0x2dcd470 .part L_0x2dccae0, 0, 1; +L_0x2dcd660 .part v0x2cdd2e0_0, 0, 1; +L_0x2dcd7c0 .part L_0x2dccae0, 1, 1; +L_0x2dcd920 .part v0x2cdd2e0_0, 1, 1; +L_0x2dcdad0 .part L_0x2dccae0, 2, 1; +L_0x2dcdc30 .part v0x2cdd2e0_0, 2, 1; +L_0x2dcdde0 .part L_0x2dccae0, 3, 1; +L_0x2dcdf40 .part v0x2cdd2e0_0, 3, 1; +L_0x2dce140 .part L_0x2dccae0, 4, 1; +L_0x2dce3b0 .part v0x2cdd2e0_0, 4, 1; +L_0x2dce520 .part L_0x2dccae0, 5, 1; +L_0x2dce680 .part v0x2cdd2e0_0, 5, 1; +L_0x2dce8a0 .part L_0x2dccae0, 6, 1; +L_0x2dcea00 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dceb70_0_0 .concat8 [ 1 1 1 1], L_0x2dcd360, L_0x2dcd700, L_0x2dcda10, L_0x2dcdd20; +LS_0x2dceb70_0_4 .concat8 [ 1 1 1 1], L_0x2dce080, L_0x2dce4b0, L_0x2dce7e0, L_0x2dce770; +L_0x2dceb70 .concat8 [ 4 4 0 0], LS_0x2dceb70_0_0, LS_0x2dceb70_0_4; +L_0x2dcef30 .part L_0x2dccae0, 7, 1; +L_0x2dcf120 .part v0x2cdd2e0_0, 7, 1; +S_0x2c238c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c23ad0 .param/l "i" 0 4 54, +C4<00>; +L_0x2dcd360/d .functor AND 1, L_0x2dcd470, L_0x2dcd660, C4<1>, C4<1>; +L_0x2dcd360 .delay 1 (30000,30000,30000) L_0x2dcd360/d; +v0x2c23bb0_0 .net *"_s0", 0 0, L_0x2dcd470; 1 drivers +v0x2c23c90_0 .net *"_s1", 0 0, L_0x2dcd660; 1 drivers +S_0x2c23d70 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c23f80 .param/l "i" 0 4 54, +C4<01>; +L_0x2dcd700/d .functor AND 1, L_0x2dcd7c0, L_0x2dcd920, C4<1>, C4<1>; +L_0x2dcd700 .delay 1 (30000,30000,30000) L_0x2dcd700/d; +v0x2c24040_0 .net *"_s0", 0 0, L_0x2dcd7c0; 1 drivers +v0x2c24120_0 .net *"_s1", 0 0, L_0x2dcd920; 1 drivers +S_0x2c24200 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c24440 .param/l "i" 0 4 54, +C4<010>; +L_0x2dcda10/d .functor AND 1, L_0x2dcdad0, L_0x2dcdc30, C4<1>, C4<1>; +L_0x2dcda10 .delay 1 (30000,30000,30000) L_0x2dcda10/d; +v0x2c244e0_0 .net *"_s0", 0 0, L_0x2dcdad0; 1 drivers +v0x2c245c0_0 .net *"_s1", 0 0, L_0x2dcdc30; 1 drivers +S_0x2c246a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c248b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2dcdd20/d .functor AND 1, L_0x2dcdde0, L_0x2dcdf40, C4<1>, C4<1>; +L_0x2dcdd20 .delay 1 (30000,30000,30000) L_0x2dcdd20/d; +v0x2c24970_0 .net *"_s0", 0 0, L_0x2dcdde0; 1 drivers +v0x2c24a50_0 .net *"_s1", 0 0, L_0x2dcdf40; 1 drivers +S_0x2c24b30 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c24d90 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dce080/d .functor AND 1, L_0x2dce140, L_0x2dce3b0, C4<1>, C4<1>; +L_0x2dce080 .delay 1 (30000,30000,30000) L_0x2dce080/d; +v0x2c24e50_0 .net *"_s0", 0 0, L_0x2dce140; 1 drivers +v0x2c24f30_0 .net *"_s1", 0 0, L_0x2dce3b0; 1 drivers +S_0x2c25010 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c25220 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dce4b0/d .functor AND 1, L_0x2dce520, L_0x2dce680, C4<1>, C4<1>; +L_0x2dce4b0 .delay 1 (30000,30000,30000) L_0x2dce4b0/d; +v0x2c252e0_0 .net *"_s0", 0 0, L_0x2dce520; 1 drivers +v0x2c253c0_0 .net *"_s1", 0 0, L_0x2dce680; 1 drivers +S_0x2c254a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c256b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dce7e0/d .functor AND 1, L_0x2dce8a0, L_0x2dcea00, C4<1>, C4<1>; +L_0x2dce7e0 .delay 1 (30000,30000,30000) L_0x2dce7e0/d; +v0x2c25770_0 .net *"_s0", 0 0, L_0x2dce8a0; 1 drivers +v0x2c25850_0 .net *"_s1", 0 0, L_0x2dcea00; 1 drivers +S_0x2c25930 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c23680; + .timescale -9 -12; +P_0x2c25b40 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dce770/d .functor AND 1, L_0x2dcef30, L_0x2dcf120, C4<1>, C4<1>; +L_0x2dce770 .delay 1 (30000,30000,30000) L_0x2dce770/d; +v0x2c25c00_0 .net *"_s0", 0 0, L_0x2dcef30; 1 drivers +v0x2c25ce0_0 .net *"_s1", 0 0, L_0x2dcf120; 1 drivers +S_0x2c268a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c23430; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12e25b0/d .functor OR 1, L_0x12e2670, L_0x12e2820, C4<0>, C4<0>; -L_0x12e25b0 .delay 1 (30000,30000,30000) L_0x12e25b0/d; -v0x1153ef0_0 .net *"_s10", 0 0, L_0x12e2670; 1 drivers -v0x1153fd0_0 .net *"_s12", 0 0, L_0x12e2820; 1 drivers -v0x11540b0_0 .net "in", 7 0, L_0x12e0580; alias, 1 drivers -v0x1154180_0 .net "ors", 1 0, L_0x12e23d0; 1 drivers -v0x1154240_0 .net "out", 0 0, L_0x12e25b0; alias, 1 drivers -L_0x12e1770 .part L_0x12e0580, 0, 4; -L_0x12e23d0 .concat8 [ 1 1 0 0], L_0x12e1460, L_0x12e2090; -L_0x12e2510 .part L_0x12e0580, 4, 4; -L_0x12e2670 .part L_0x12e23d0, 0, 1; -L_0x12e2820 .part L_0x12e23d0, 1, 1; -S_0x1152560 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11523a0; +L_0x2dd0b70/d .functor OR 1, L_0x2dd0c30, L_0x2dd0de0, C4<0>, C4<0>; +L_0x2dd0b70 .delay 1 (30000,30000,30000) L_0x2dd0b70/d; +v0x2c283f0_0 .net *"_s10", 0 0, L_0x2dd0c30; 1 drivers +v0x2c284d0_0 .net *"_s12", 0 0, L_0x2dd0de0; 1 drivers +v0x2c285b0_0 .net "in", 7 0, L_0x2dceb70; alias, 1 drivers +v0x2c28680_0 .net "ors", 1 0, L_0x2dd0990; 1 drivers +v0x2c28740_0 .net "out", 0 0, L_0x2dd0b70; alias, 1 drivers +L_0x2dcfd60 .part L_0x2dceb70, 0, 4; +L_0x2dd0990 .concat8 [ 1 1 0 0], L_0x2dcfa50, L_0x2dd0680; +L_0x2dd0ad0 .part L_0x2dceb70, 4, 4; +L_0x2dd0c30 .part L_0x2dd0990, 0, 1; +L_0x2dd0de0 .part L_0x2dd0990, 1, 1; +S_0x2c26a60 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c268a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12e0c20/d .functor OR 1, L_0x12e0ce0, L_0x12e0e40, C4<0>, C4<0>; -L_0x12e0c20 .delay 1 (30000,30000,30000) L_0x12e0c20/d; -L_0x12e1070/d .functor OR 1, L_0x12e1180, L_0x12e12e0, C4<0>, C4<0>; -L_0x12e1070 .delay 1 (30000,30000,30000) L_0x12e1070/d; -L_0x12e1460/d .functor OR 1, L_0x12e14d0, L_0x12e1680, C4<0>, C4<0>; -L_0x12e1460 .delay 1 (30000,30000,30000) L_0x12e1460/d; -v0x11527b0_0 .net *"_s0", 0 0, L_0x12e0c20; 1 drivers -v0x11528b0_0 .net *"_s10", 0 0, L_0x12e1180; 1 drivers -v0x1152990_0 .net *"_s12", 0 0, L_0x12e12e0; 1 drivers -v0x1152a50_0 .net *"_s14", 0 0, L_0x12e14d0; 1 drivers -v0x1152b30_0 .net *"_s16", 0 0, L_0x12e1680; 1 drivers -v0x1152c60_0 .net *"_s3", 0 0, L_0x12e0ce0; 1 drivers -v0x1152d40_0 .net *"_s5", 0 0, L_0x12e0e40; 1 drivers -v0x1152e20_0 .net *"_s6", 0 0, L_0x12e1070; 1 drivers -v0x1152f00_0 .net "in", 3 0, L_0x12e1770; 1 drivers -v0x1153070_0 .net "ors", 1 0, L_0x12e0f80; 1 drivers -v0x1153150_0 .net "out", 0 0, L_0x12e1460; 1 drivers -L_0x12e0ce0 .part L_0x12e1770, 0, 1; -L_0x12e0e40 .part L_0x12e1770, 1, 1; -L_0x12e0f80 .concat8 [ 1 1 0 0], L_0x12e0c20, L_0x12e1070; -L_0x12e1180 .part L_0x12e1770, 2, 1; -L_0x12e12e0 .part L_0x12e1770, 3, 1; -L_0x12e14d0 .part L_0x12e0f80, 0, 1; -L_0x12e1680 .part L_0x12e0f80, 1, 1; -S_0x1153270 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11523a0; +L_0x2dcf210/d .functor OR 1, L_0x2dcf2d0, L_0x2dcf430, C4<0>, C4<0>; +L_0x2dcf210 .delay 1 (30000,30000,30000) L_0x2dcf210/d; +L_0x2dcf660/d .functor OR 1, L_0x2dcf770, L_0x2dcf8d0, C4<0>, C4<0>; +L_0x2dcf660 .delay 1 (30000,30000,30000) L_0x2dcf660/d; +L_0x2dcfa50/d .functor OR 1, L_0x2dcfac0, L_0x2dcfc70, C4<0>, C4<0>; +L_0x2dcfa50 .delay 1 (30000,30000,30000) L_0x2dcfa50/d; +v0x2c26cb0_0 .net *"_s0", 0 0, L_0x2dcf210; 1 drivers +v0x2c26db0_0 .net *"_s10", 0 0, L_0x2dcf770; 1 drivers +v0x2c26e90_0 .net *"_s12", 0 0, L_0x2dcf8d0; 1 drivers +v0x2c26f50_0 .net *"_s14", 0 0, L_0x2dcfac0; 1 drivers +v0x2c27030_0 .net *"_s16", 0 0, L_0x2dcfc70; 1 drivers +v0x2c27160_0 .net *"_s3", 0 0, L_0x2dcf2d0; 1 drivers +v0x2c27240_0 .net *"_s5", 0 0, L_0x2dcf430; 1 drivers +v0x2c27320_0 .net *"_s6", 0 0, L_0x2dcf660; 1 drivers +v0x2c27400_0 .net "in", 3 0, L_0x2dcfd60; 1 drivers +v0x2c27570_0 .net "ors", 1 0, L_0x2dcf570; 1 drivers +v0x2c27650_0 .net "out", 0 0, L_0x2dcfa50; 1 drivers +L_0x2dcf2d0 .part L_0x2dcfd60, 0, 1; +L_0x2dcf430 .part L_0x2dcfd60, 1, 1; +L_0x2dcf570 .concat8 [ 1 1 0 0], L_0x2dcf210, L_0x2dcf660; +L_0x2dcf770 .part L_0x2dcfd60, 2, 1; +L_0x2dcf8d0 .part L_0x2dcfd60, 3, 1; +L_0x2dcfac0 .part L_0x2dcf570, 0, 1; +L_0x2dcfc70 .part L_0x2dcf570, 1, 1; +S_0x2c27770 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c268a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12e18a0/d .functor OR 1, L_0x12e1910, L_0x12e1a70, C4<0>, C4<0>; -L_0x12e18a0 .delay 1 (30000,30000,30000) L_0x12e18a0/d; -L_0x12e1ca0/d .functor OR 1, L_0x12e1db0, L_0x12e1f10, C4<0>, C4<0>; -L_0x12e1ca0 .delay 1 (30000,30000,30000) L_0x12e1ca0/d; -L_0x12e2090/d .functor OR 1, L_0x12e2130, L_0x12e22e0, C4<0>, C4<0>; -L_0x12e2090 .delay 1 (30000,30000,30000) L_0x12e2090/d; -v0x1153430_0 .net *"_s0", 0 0, L_0x12e18a0; 1 drivers -v0x1153530_0 .net *"_s10", 0 0, L_0x12e1db0; 1 drivers -v0x1153610_0 .net *"_s12", 0 0, L_0x12e1f10; 1 drivers -v0x11536d0_0 .net *"_s14", 0 0, L_0x12e2130; 1 drivers -v0x11537b0_0 .net *"_s16", 0 0, L_0x12e22e0; 1 drivers -v0x11538e0_0 .net *"_s3", 0 0, L_0x12e1910; 1 drivers -v0x11539c0_0 .net *"_s5", 0 0, L_0x12e1a70; 1 drivers -v0x1153aa0_0 .net *"_s6", 0 0, L_0x12e1ca0; 1 drivers -v0x1153b80_0 .net "in", 3 0, L_0x12e2510; 1 drivers -v0x1153cf0_0 .net "ors", 1 0, L_0x12e1bb0; 1 drivers -v0x1153dd0_0 .net "out", 0 0, L_0x12e2090; 1 drivers -L_0x12e1910 .part L_0x12e2510, 0, 1; -L_0x12e1a70 .part L_0x12e2510, 1, 1; -L_0x12e1bb0 .concat8 [ 1 1 0 0], L_0x12e18a0, L_0x12e1ca0; -L_0x12e1db0 .part L_0x12e2510, 2, 1; -L_0x12e1f10 .part L_0x12e2510, 3, 1; -L_0x12e2130 .part L_0x12e1bb0, 0, 1; -L_0x12e22e0 .part L_0x12e1bb0, 1, 1; -S_0x11546e0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1148060; +L_0x2dcfe90/d .functor OR 1, L_0x2dcff00, L_0x2dd0060, C4<0>, C4<0>; +L_0x2dcfe90 .delay 1 (30000,30000,30000) L_0x2dcfe90/d; +L_0x2dd0290/d .functor OR 1, L_0x2dd03a0, L_0x2dd0500, C4<0>, C4<0>; +L_0x2dd0290 .delay 1 (30000,30000,30000) L_0x2dd0290/d; +L_0x2dd0680/d .functor OR 1, L_0x2dd06f0, L_0x2dd08a0, C4<0>, C4<0>; +L_0x2dd0680 .delay 1 (30000,30000,30000) L_0x2dd0680/d; +v0x2c27930_0 .net *"_s0", 0 0, L_0x2dcfe90; 1 drivers +v0x2c27a30_0 .net *"_s10", 0 0, L_0x2dd03a0; 1 drivers +v0x2c27b10_0 .net *"_s12", 0 0, L_0x2dd0500; 1 drivers +v0x2c27bd0_0 .net *"_s14", 0 0, L_0x2dd06f0; 1 drivers +v0x2c27cb0_0 .net *"_s16", 0 0, L_0x2dd08a0; 1 drivers +v0x2c27de0_0 .net *"_s3", 0 0, L_0x2dcff00; 1 drivers +v0x2c27ec0_0 .net *"_s5", 0 0, L_0x2dd0060; 1 drivers +v0x2c27fa0_0 .net *"_s6", 0 0, L_0x2dd0290; 1 drivers +v0x2c28080_0 .net "in", 3 0, L_0x2dd0ad0; 1 drivers +v0x2c281f0_0 .net "ors", 1 0, L_0x2dd01a0; 1 drivers +v0x2c282d0_0 .net "out", 0 0, L_0x2dd0680; 1 drivers +L_0x2dcff00 .part L_0x2dd0ad0, 0, 1; +L_0x2dd0060 .part L_0x2dd0ad0, 1, 1; +L_0x2dd01a0 .concat8 [ 1 1 0 0], L_0x2dcfe90, L_0x2dd0290; +L_0x2dd03a0 .part L_0x2dd0ad0, 2, 1; +L_0x2dd0500 .part L_0x2dd0ad0, 3, 1; +L_0x2dd06f0 .part L_0x2dd01a0, 0, 1; +L_0x2dd08a0 .part L_0x2dd01a0, 1, 1; +S_0x2c28be0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c1c560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -12326,80 +13041,80 @@ S_0x11546e0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1148060; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12ddd50/d .functor XNOR 1, L_0x12e6510, L_0x12e6670, C4<0>, C4<0>; -L_0x12ddd50 .delay 1 (20000,20000,20000) L_0x12ddd50/d; -L_0x12ddfc0/d .functor AND 1, L_0x12e6510, L_0x12dcc90, C4<1>, C4<1>; -L_0x12ddfc0 .delay 1 (30000,30000,30000) L_0x12ddfc0/d; -L_0x12de030/d .functor AND 1, L_0x12ddd50, L_0x12dca20, C4<1>, C4<1>; -L_0x12de030 .delay 1 (30000,30000,30000) L_0x12de030/d; -L_0x12de190/d .functor OR 1, L_0x12de030, L_0x12ddfc0, C4<0>, C4<0>; -L_0x12de190 .delay 1 (30000,30000,30000) L_0x12de190/d; -v0x1154990_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers -v0x1154a80_0 .net "a_", 0 0, L_0x12d0e90; alias, 1 drivers -v0x1154b40_0 .net "b", 0 0, L_0x12e6670; alias, 1 drivers -v0x1154c30_0 .net "b_", 0 0, L_0x12dcc90; alias, 1 drivers -v0x1154cd0_0 .net "carryin", 0 0, L_0x12dca20; alias, 1 drivers -v0x1154e10_0 .net "eq", 0 0, L_0x12ddd50; 1 drivers -v0x1154ed0_0 .net "lt", 0 0, L_0x12ddfc0; 1 drivers -v0x1154f90_0 .net "out", 0 0, L_0x12de190; 1 drivers -v0x1155050_0 .net "w0", 0 0, L_0x12de030; 1 drivers -S_0x11552a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1148060; +L_0x2dcb920/d .functor XNOR 1, L_0x2dd4a10, L_0x2dd4b70, C4<0>, C4<0>; +L_0x2dcb920 .delay 1 (20000,20000,20000) L_0x2dcb920/d; +L_0x2dcbaa0/d .functor AND 1, L_0x2dd4a10, L_0x2dca610, C4<1>, C4<1>; +L_0x2dcbaa0 .delay 1 (30000,30000,30000) L_0x2dcbaa0/d; +L_0x2dcbc00/d .functor AND 1, L_0x2dcb920, L_0x2dca3f0, C4<1>, C4<1>; +L_0x2dcbc00 .delay 1 (30000,30000,30000) L_0x2dcbc00/d; +L_0x2dcbd10/d .functor OR 1, L_0x2dcbc00, L_0x2dcbaa0, C4<0>, C4<0>; +L_0x2dcbd10 .delay 1 (30000,30000,30000) L_0x2dcbd10/d; +v0x2c28e90_0 .net "a", 0 0, L_0x2dd4a10; alias, 1 drivers +v0x2c28f80_0 .net "a_", 0 0, L_0x2dbdb60; alias, 1 drivers +v0x2c29040_0 .net "b", 0 0, L_0x2dd4b70; alias, 1 drivers +v0x2c29130_0 .net "b_", 0 0, L_0x2dca610; alias, 1 drivers +v0x2c291d0_0 .net "carryin", 0 0, L_0x2dca3f0; alias, 1 drivers +v0x2c29310_0 .net "eq", 0 0, L_0x2dcb920; 1 drivers +v0x2c293d0_0 .net "lt", 0 0, L_0x2dcbaa0; 1 drivers +v0x2c29490_0 .net "out", 0 0, L_0x2dcbd10; 1 drivers +v0x2c29550_0 .net "w0", 0 0, L_0x2dcbc00; 1 drivers +S_0x2c297a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c1c560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12ddb30/d .functor OR 1, L_0x12dd680, L_0x1156500, C4<0>, C4<0>; -L_0x12ddb30 .delay 1 (30000,30000,30000) L_0x12ddb30/d; -v0x1156090_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers -v0x11561e0_0 .net "b", 0 0, L_0x12dcc90; alias, 1 drivers -v0x11562a0_0 .net "c1", 0 0, L_0x12dd680; 1 drivers -v0x1156340_0 .net "c2", 0 0, L_0x1156500; 1 drivers -v0x1156410_0 .net "carryin", 0 0, L_0x12dca20; alias, 1 drivers -v0x1156590_0 .net "carryout", 0 0, L_0x12ddb30; 1 drivers -v0x1156630_0 .net "s1", 0 0, L_0x12dd5c0; 1 drivers -v0x11566d0_0 .net "sum", 0 0, L_0x12dd7e0; 1 drivers -S_0x11554f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11552a0; +L_0x2dcb500/d .functor OR 1, L_0x2dcb000, L_0x2c2aa00, C4<0>, C4<0>; +L_0x2dcb500 .delay 1 (30000,30000,30000) L_0x2dcb500/d; +v0x2c2a590_0 .net "a", 0 0, L_0x2dd4a10; alias, 1 drivers +v0x2c2a6e0_0 .net "b", 0 0, L_0x2dca610; alias, 1 drivers +v0x2c2a7a0_0 .net "c1", 0 0, L_0x2dcb000; 1 drivers +v0x2c2a840_0 .net "c2", 0 0, L_0x2c2aa00; 1 drivers +v0x2c2a910_0 .net "carryin", 0 0, L_0x2dca3f0; alias, 1 drivers +v0x2c2aa90_0 .net "carryout", 0 0, L_0x2dcb500; 1 drivers +v0x2c2ab30_0 .net "s1", 0 0, L_0x2dcaf40; 1 drivers +v0x2c2abd0_0 .net "sum", 0 0, L_0x2dcb160; 1 drivers +S_0x2c299f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c297a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12dd5c0/d .functor XOR 1, L_0x12e6510, L_0x12dcc90, C4<0>, C4<0>; -L_0x12dd5c0 .delay 1 (30000,30000,30000) L_0x12dd5c0/d; -L_0x12dd680/d .functor AND 1, L_0x12e6510, L_0x12dcc90, C4<1>, C4<1>; -L_0x12dd680 .delay 1 (30000,30000,30000) L_0x12dd680/d; -v0x1155750_0 .net "a", 0 0, L_0x12e6510; alias, 1 drivers -v0x1155810_0 .net "b", 0 0, L_0x12dcc90; alias, 1 drivers -v0x11558d0_0 .net "carryout", 0 0, L_0x12dd680; alias, 1 drivers -v0x1155970_0 .net "sum", 0 0, L_0x12dd5c0; alias, 1 drivers -S_0x1155aa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11552a0; +L_0x2dcaf40/d .functor XOR 1, L_0x2dd4a10, L_0x2dca610, C4<0>, C4<0>; +L_0x2dcaf40 .delay 1 (30000,30000,30000) L_0x2dcaf40/d; +L_0x2dcb000/d .functor AND 1, L_0x2dd4a10, L_0x2dca610, C4<1>, C4<1>; +L_0x2dcb000 .delay 1 (30000,30000,30000) L_0x2dcb000/d; +v0x2c29c50_0 .net "a", 0 0, L_0x2dd4a10; alias, 1 drivers +v0x2c29d10_0 .net "b", 0 0, L_0x2dca610; alias, 1 drivers +v0x2c29dd0_0 .net "carryout", 0 0, L_0x2dcb000; alias, 1 drivers +v0x2c29e70_0 .net "sum", 0 0, L_0x2dcaf40; alias, 1 drivers +S_0x2c29fa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c297a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12dd7e0/d .functor XOR 1, L_0x12dd5c0, L_0x12dca20, C4<0>, C4<0>; -L_0x12dd7e0 .delay 1 (30000,30000,30000) L_0x12dd7e0/d; -L_0x1156500/d .functor AND 1, L_0x12dd5c0, L_0x12dca20, C4<1>, C4<1>; -L_0x1156500 .delay 1 (30000,30000,30000) L_0x1156500/d; -v0x1155d00_0 .net "a", 0 0, L_0x12dd5c0; alias, 1 drivers -v0x1155dd0_0 .net "b", 0 0, L_0x12dca20; alias, 1 drivers -v0x1155e70_0 .net "carryout", 0 0, L_0x1156500; alias, 1 drivers -v0x1155f40_0 .net "sum", 0 0, L_0x12dd7e0; alias, 1 drivers -S_0x1157af0 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1147d90; - .timescale -9 -12; -L_0x2b0ab3d068d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06920 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12e65b0/d .functor OR 1, L_0x2b0ab3d068d8, L_0x2b0ab3d06920, C4<0>, C4<0>; -L_0x12e65b0 .delay 1 (30000,30000,30000) L_0x12e65b0/d; -v0x1157ce0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d068d8; 1 drivers -v0x1157dc0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06920; 1 drivers -S_0x1157ea0 .scope generate, "alu_slices[23]" "alu_slices[23]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11580b0 .param/l "i" 0 3 41, +C4<010111>; -S_0x1158170 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1157ea0; +L_0x2dcb160/d .functor XOR 1, L_0x2dcaf40, L_0x2dca3f0, C4<0>, C4<0>; +L_0x2dcb160 .delay 1 (30000,30000,30000) L_0x2dcb160/d; +L_0x2c2aa00/d .functor AND 1, L_0x2dcaf40, L_0x2dca3f0, C4<1>, C4<1>; +L_0x2c2aa00 .delay 1 (30000,30000,30000) L_0x2c2aa00/d; +v0x2c2a200_0 .net "a", 0 0, L_0x2dcaf40; alias, 1 drivers +v0x2c2a2d0_0 .net "b", 0 0, L_0x2dca3f0; alias, 1 drivers +v0x2c2a370_0 .net "carryout", 0 0, L_0x2c2aa00; alias, 1 drivers +v0x2c2a440_0 .net "sum", 0 0, L_0x2dcb160; alias, 1 drivers +S_0x2c2cc60 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c1c290; + .timescale -9 -12; +L_0x2ac6110bb988 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bb9d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dcaac0/d .functor OR 1, L_0x2ac6110bb988, L_0x2ac6110bb9d0, C4<0>, C4<0>; +L_0x2dcaac0 .delay 1 (30000,30000,30000) L_0x2dcaac0/d; +v0x2c2ce50_0 .net/2u *"_s0", 0 0, L_0x2ac6110bb988; 1 drivers +v0x2c2cf30_0 .net/2u *"_s2", 0 0, L_0x2ac6110bb9d0; 1 drivers +S_0x2c2d010 .scope generate, "alu_slices[23]" "alu_slices[23]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c2d220 .param/l "i" 0 3 39, +C4<010111>; +S_0x2c2d2e0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c2d010; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -12408,445 +13123,476 @@ S_0x1158170 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1157ea0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12dcbb0/d .functor NOT 1, L_0x12f0130, C4<0>, C4<0>, C4<0>; -L_0x12dcbb0 .delay 1 (10000,10000,10000) L_0x12dcbb0/d; -L_0x12e6a30/d .functor NOT 1, L_0x12e6710, C4<0>, C4<0>, C4<0>; -L_0x12e6a30 .delay 1 (10000,10000,10000) L_0x12e6a30/d; -L_0x12e7a80/d .functor XOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; -L_0x12e7a80 .delay 1 (30000,30000,30000) L_0x12e7a80/d; -L_0x2b0ab3d06968 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d069b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12e8130/d .functor OR 1, L_0x2b0ab3d06968, L_0x2b0ab3d069b0, C4<0>, C4<0>; -L_0x12e8130 .delay 1 (30000,30000,30000) L_0x12e8130/d; -L_0x12e8330/d .functor AND 1, L_0x12f0130, L_0x12e6710, C4<1>, C4<1>; -L_0x12e8330 .delay 1 (30000,30000,30000) L_0x12e8330/d; -L_0x12e83f0/d .functor NAND 1, L_0x12f0130, L_0x12e6710, C4<1>, C4<1>; -L_0x12e83f0 .delay 1 (20000,20000,20000) L_0x12e83f0/d; -L_0x12e8550/d .functor XOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; -L_0x12e8550 .delay 1 (20000,20000,20000) L_0x12e8550/d; -L_0x12e8a00/d .functor OR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; -L_0x12e8a00 .delay 1 (30000,30000,30000) L_0x12e8a00/d; -L_0x12f0030/d .functor NOT 1, L_0x12ec290, C4<0>, C4<0>, C4<0>; -L_0x12f0030 .delay 1 (10000,10000,10000) L_0x12f0030/d; -v0x11668a0_0 .net "A", 0 0, L_0x12f0130; 1 drivers -v0x1166960_0 .net "A_", 0 0, L_0x12dcbb0; 1 drivers -v0x1166a20_0 .net "B", 0 0, L_0x12e6710; 1 drivers -v0x1166af0_0 .net "B_", 0 0, L_0x12e6a30; 1 drivers -v0x1166b90_0 .net *"_s12", 0 0, L_0x12e8130; 1 drivers -v0x1166c80_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06968; 1 drivers -v0x1166d40_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d069b0; 1 drivers -v0x1166e20_0 .net *"_s18", 0 0, L_0x12e8330; 1 drivers -v0x1166f00_0 .net *"_s20", 0 0, L_0x12e83f0; 1 drivers -v0x1167070_0 .net *"_s22", 0 0, L_0x12e8550; 1 drivers -v0x1167150_0 .net *"_s24", 0 0, L_0x12e8a00; 1 drivers -o0x2b0ab3cdbcf8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1167230_0 name=_s30 -o0x2b0ab3cdbd28 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1167310_0 name=_s32 -v0x11673f0_0 .net *"_s8", 0 0, L_0x12e7a80; 1 drivers -v0x11674d0_0 .net "carryin", 0 0, L_0x12e67b0; 1 drivers -v0x1167570_0 .net "carryout", 0 0, L_0x12efcd0; 1 drivers -v0x1167610_0 .net "carryouts", 7 0, L_0x13555d0; 1 drivers -v0x11677c0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1167860_0 .net "result", 0 0, L_0x12ec290; 1 drivers -v0x1167950_0 .net "results", 7 0, L_0x12e87d0; 1 drivers -v0x1167a60_0 .net "zero", 0 0, L_0x12f0030; 1 drivers -LS_0x12e87d0_0_0 .concat8 [ 1 1 1 1], L_0x12e6f50, L_0x12e7580, L_0x12e7a80, L_0x12e8130; -LS_0x12e87d0_0_4 .concat8 [ 1 1 1 1], L_0x12e8330, L_0x12e83f0, L_0x12e8550, L_0x12e8a00; -L_0x12e87d0 .concat8 [ 4 4 0 0], LS_0x12e87d0_0_0, LS_0x12e87d0_0_4; -LS_0x13555d0_0_0 .concat [ 1 1 1 1], L_0x12e7200, L_0x12e7920, o0x2b0ab3cdbcf8, L_0x12e7f80; -LS_0x13555d0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cdbd28; -L_0x13555d0 .concat [ 4 4 0 0], LS_0x13555d0_0_0, LS_0x13555d0_0_4; -S_0x11583f0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1158170; +L_0x2dca580/d .functor NOT 1, L_0x2ddf240, C4<0>, C4<0>, C4<0>; +L_0x2dca580 .delay 1 (10000,10000,10000) L_0x2dca580/d; +L_0x2dd4ee0/d .functor NOT 1, L_0x2dd4c10, C4<0>, C4<0>, C4<0>; +L_0x2dd4ee0 .delay 1 (10000,10000,10000) L_0x2dd4ee0/d; +L_0x2dd5e90/d .functor XOR 1, L_0x2ddf240, L_0x2dd4c10, C4<0>, C4<0>; +L_0x2dd5e90 .delay 1 (30000,30000,30000) L_0x2dd5e90/d; +L_0x2ac6110bba18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bba60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd5f50/d .functor OR 1, L_0x2ac6110bba18, L_0x2ac6110bba60, C4<0>, C4<0>; +L_0x2dd5f50 .delay 1 (30000,30000,30000) L_0x2dd5f50/d; +L_0x2ac6110bbaa8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbaf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd66f0/d .functor OR 1, L_0x2ac6110bbaa8, L_0x2ac6110bbaf0, C4<0>, C4<0>; +L_0x2dd66f0 .delay 1 (30000,30000,30000) L_0x2dd66f0/d; +L_0x2dd68f0/d .functor AND 1, L_0x2ddf240, L_0x2dd4c10, C4<1>, C4<1>; +L_0x2dd68f0 .delay 1 (30000,30000,30000) L_0x2dd68f0/d; +L_0x2ac6110bbb38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbb80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd69b0/d .functor OR 1, L_0x2ac6110bbb38, L_0x2ac6110bbb80, C4<0>, C4<0>; +L_0x2dd69b0 .delay 1 (30000,30000,30000) L_0x2dd69b0/d; +L_0x2dd6bb0/d .functor NAND 1, L_0x2ddf240, L_0x2dd4c10, C4<1>, C4<1>; +L_0x2dd6bb0 .delay 1 (20000,20000,20000) L_0x2dd6bb0/d; +L_0x2ac6110bbbc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbc10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd6cc0/d .functor OR 1, L_0x2ac6110bbbc8, L_0x2ac6110bbc10, C4<0>, C4<0>; +L_0x2dd6cc0 .delay 1 (30000,30000,30000) L_0x2dd6cc0/d; +L_0x2dd6e70/d .functor NOR 1, L_0x2ddf240, L_0x2dd4c10, C4<0>, C4<0>; +L_0x2dd6e70 .delay 1 (20000,20000,20000) L_0x2dd6e70/d; +L_0x2ac6110bbc58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbca0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd7140/d .functor OR 1, L_0x2ac6110bbc58, L_0x2ac6110bbca0, C4<0>, C4<0>; +L_0x2dd7140 .delay 1 (30000,30000,30000) L_0x2dd7140/d; +L_0x2dd7540/d .functor OR 1, L_0x2ddf240, L_0x2dd4c10, C4<0>, C4<0>; +L_0x2dd7540 .delay 1 (30000,30000,30000) L_0x2dd7540/d; +L_0x2ac6110bbce8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbd30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd79e0/d .functor OR 1, L_0x2ac6110bbce8, L_0x2ac6110bbd30, C4<0>, C4<0>; +L_0x2dd79e0 .delay 1 (30000,30000,30000) L_0x2dd79e0/d; +L_0x2ddf140/d .functor NOT 1, L_0x2ddb3a0, C4<0>, C4<0>, C4<0>; +L_0x2ddf140 .delay 1 (10000,10000,10000) L_0x2ddf140/d; +v0x2c3ba10_0 .net "A", 0 0, L_0x2ddf240; 1 drivers +v0x2c3bad0_0 .net "A_", 0 0, L_0x2dca580; 1 drivers +v0x2c3bb90_0 .net "B", 0 0, L_0x2dd4c10; 1 drivers +v0x2c3bc60_0 .net "B_", 0 0, L_0x2dd4ee0; 1 drivers +v0x2c3bd00_0 .net *"_s11", 0 0, L_0x2dd5f50; 1 drivers +v0x2c3bdf0_0 .net/2s *"_s13", 0 0, L_0x2ac6110bba18; 1 drivers +v0x2c3beb0_0 .net/2s *"_s15", 0 0, L_0x2ac6110bba60; 1 drivers +v0x2c3bf90_0 .net *"_s19", 0 0, L_0x2dd66f0; 1 drivers +v0x2c3c070_0 .net/2s *"_s21", 0 0, L_0x2ac6110bbaa8; 1 drivers +v0x2c3c1e0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bbaf0; 1 drivers +v0x2c3c2c0_0 .net *"_s25", 0 0, L_0x2dd68f0; 1 drivers +v0x2c3c3a0_0 .net *"_s28", 0 0, L_0x2dd69b0; 1 drivers +v0x2c3c480_0 .net/2s *"_s30", 0 0, L_0x2ac6110bbb38; 1 drivers +v0x2c3c560_0 .net/2s *"_s32", 0 0, L_0x2ac6110bbb80; 1 drivers +v0x2c3c640_0 .net *"_s34", 0 0, L_0x2dd6bb0; 1 drivers +v0x2c3c720_0 .net *"_s37", 0 0, L_0x2dd6cc0; 1 drivers +v0x2c3c800_0 .net/2s *"_s39", 0 0, L_0x2ac6110bbbc8; 1 drivers +v0x2c3c9b0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bbc10; 1 drivers +v0x2c3ca50_0 .net *"_s43", 0 0, L_0x2dd6e70; 1 drivers +v0x2c3cb30_0 .net *"_s46", 0 0, L_0x2dd7140; 1 drivers +v0x2c3cc10_0 .net/2s *"_s48", 0 0, L_0x2ac6110bbc58; 1 drivers +v0x2c3ccf0_0 .net/2s *"_s50", 0 0, L_0x2ac6110bbca0; 1 drivers +v0x2c3cdd0_0 .net *"_s52", 0 0, L_0x2dd7540; 1 drivers +v0x2c3ceb0_0 .net *"_s56", 0 0, L_0x2dd79e0; 1 drivers +v0x2c3cf90_0 .net/2s *"_s59", 0 0, L_0x2ac6110bbce8; 1 drivers +v0x2c3d070_0 .net/2s *"_s61", 0 0, L_0x2ac6110bbd30; 1 drivers +v0x2c3d150_0 .net *"_s8", 0 0, L_0x2dd5e90; 1 drivers +v0x2c3d230_0 .net "carryin", 0 0, L_0x2dd4cb0; 1 drivers +v0x2c3d2d0_0 .net "carryout", 0 0, L_0x2ddede0; 1 drivers +v0x2c3d370_0 .net "carryouts", 7 0, L_0x2dd7650; 1 drivers +v0x2c3d480_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c3d540_0 .net "result", 0 0, L_0x2ddb3a0; 1 drivers +v0x2c3d630_0 .net "results", 7 0, L_0x2dd7310; 1 drivers +v0x2c3c910_0 .net "zero", 0 0, L_0x2ddf140; 1 drivers +LS_0x2dd7310_0_0 .concat8 [ 1 1 1 1], L_0x2dd53b0, L_0x2dd59e0, L_0x2dd5e90, L_0x2dd66f0; +LS_0x2dd7310_0_4 .concat8 [ 1 1 1 1], L_0x2dd68f0, L_0x2dd6bb0, L_0x2dd6e70, L_0x2dd7540; +L_0x2dd7310 .concat8 [ 4 4 0 0], LS_0x2dd7310_0_0, LS_0x2dd7310_0_4; +LS_0x2dd7650_0_0 .concat8 [ 1 1 1 1], L_0x2dd5660, L_0x2dd5d30, L_0x2dd5f50, L_0x2dd6540; +LS_0x2dd7650_0_4 .concat8 [ 1 1 1 1], L_0x2dd69b0, L_0x2dd6cc0, L_0x2dd7140, L_0x2dd79e0; +L_0x2dd7650 .concat8 [ 4 4 0 0], LS_0x2dd7650_0_0, LS_0x2dd7650_0_4; +S_0x2c2d560 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c2d2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12e7200/d .functor OR 1, L_0x12e6ce0, L_0x12e70a0, C4<0>, C4<0>; -L_0x12e7200 .delay 1 (30000,30000,30000) L_0x12e7200/d; -v0x1159220_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers -v0x11592e0_0 .net "b", 0 0, L_0x12e6710; alias, 1 drivers -v0x11593b0_0 .net "c1", 0 0, L_0x12e6ce0; 1 drivers -v0x11594b0_0 .net "c2", 0 0, L_0x12e70a0; 1 drivers -v0x1159580_0 .net "carryin", 0 0, L_0x12e67b0; alias, 1 drivers -v0x1159670_0 .net "carryout", 0 0, L_0x12e7200; 1 drivers -v0x1159710_0 .net "s1", 0 0, L_0x12e6c20; 1 drivers -v0x1159800_0 .net "sum", 0 0, L_0x12e6f50; 1 drivers -S_0x1158660 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11583f0; +L_0x2dd5660/d .functor OR 1, L_0x2dd5140, L_0x2dd5500, C4<0>, C4<0>; +L_0x2dd5660 .delay 1 (30000,30000,30000) L_0x2dd5660/d; +v0x2c2e390_0 .net "a", 0 0, L_0x2ddf240; alias, 1 drivers +v0x2c2e450_0 .net "b", 0 0, L_0x2dd4c10; alias, 1 drivers +v0x2c2e520_0 .net "c1", 0 0, L_0x2dd5140; 1 drivers +v0x2c2e620_0 .net "c2", 0 0, L_0x2dd5500; 1 drivers +v0x2c2e6f0_0 .net "carryin", 0 0, L_0x2dd4cb0; alias, 1 drivers +v0x2c2e7e0_0 .net "carryout", 0 0, L_0x2dd5660; 1 drivers +v0x2c2e880_0 .net "s1", 0 0, L_0x2dd50d0; 1 drivers +v0x2c2e970_0 .net "sum", 0 0, L_0x2dd53b0; 1 drivers +S_0x2c2d7d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c2d560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12e6c20/d .functor XOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; -L_0x12e6c20 .delay 1 (30000,30000,30000) L_0x12e6c20/d; -L_0x12e6ce0/d .functor AND 1, L_0x12f0130, L_0x12e6710, C4<1>, C4<1>; -L_0x12e6ce0 .delay 1 (30000,30000,30000) L_0x12e6ce0/d; -v0x11588c0_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers -v0x11589a0_0 .net "b", 0 0, L_0x12e6710; alias, 1 drivers -v0x1158a60_0 .net "carryout", 0 0, L_0x12e6ce0; alias, 1 drivers -v0x1158b00_0 .net "sum", 0 0, L_0x12e6c20; alias, 1 drivers -S_0x1158c40 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11583f0; +L_0x2dd50d0/d .functor XOR 1, L_0x2ddf240, L_0x2dd4c10, C4<0>, C4<0>; +L_0x2dd50d0 .delay 1 (30000,30000,30000) L_0x2dd50d0/d; +L_0x2dd5140/d .functor AND 1, L_0x2ddf240, L_0x2dd4c10, C4<1>, C4<1>; +L_0x2dd5140 .delay 1 (30000,30000,30000) L_0x2dd5140/d; +v0x2c2da30_0 .net "a", 0 0, L_0x2ddf240; alias, 1 drivers +v0x2c2db10_0 .net "b", 0 0, L_0x2dd4c10; alias, 1 drivers +v0x2c2dbd0_0 .net "carryout", 0 0, L_0x2dd5140; alias, 1 drivers +v0x2c2dc70_0 .net "sum", 0 0, L_0x2dd50d0; alias, 1 drivers +S_0x2c2ddb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c2d560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12e6f50/d .functor XOR 1, L_0x12e6c20, L_0x12e67b0, C4<0>, C4<0>; -L_0x12e6f50 .delay 1 (30000,30000,30000) L_0x12e6f50/d; -L_0x12e70a0/d .functor AND 1, L_0x12e6c20, L_0x12e67b0, C4<1>, C4<1>; -L_0x12e70a0 .delay 1 (30000,30000,30000) L_0x12e70a0/d; -v0x1158ea0_0 .net "a", 0 0, L_0x12e6c20; alias, 1 drivers -v0x1158f40_0 .net "b", 0 0, L_0x12e67b0; alias, 1 drivers -v0x1158fe0_0 .net "carryout", 0 0, L_0x12e70a0; alias, 1 drivers -v0x11590b0_0 .net "sum", 0 0, L_0x12e6f50; alias, 1 drivers -S_0x11598d0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1158170; +L_0x2dd53b0/d .functor XOR 1, L_0x2dd50d0, L_0x2dd4cb0, C4<0>, C4<0>; +L_0x2dd53b0 .delay 1 (30000,30000,30000) L_0x2dd53b0/d; +L_0x2dd5500/d .functor AND 1, L_0x2dd50d0, L_0x2dd4cb0, C4<1>, C4<1>; +L_0x2dd5500 .delay 1 (30000,30000,30000) L_0x2dd5500/d; +v0x2c2e010_0 .net "a", 0 0, L_0x2dd50d0; alias, 1 drivers +v0x2c2e0b0_0 .net "b", 0 0, L_0x2dd4cb0; alias, 1 drivers +v0x2c2e150_0 .net "carryout", 0 0, L_0x2dd5500; alias, 1 drivers +v0x2c2e220_0 .net "sum", 0 0, L_0x2dd53b0; alias, 1 drivers +S_0x2c2ea40 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c2d2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x115ecc0_0 .net "ands", 7 0, L_0x12edcd0; 1 drivers -v0x115edd0_0 .net "in", 7 0, L_0x13555d0; alias, 1 drivers -v0x115ee90_0 .net "out", 0 0, L_0x12efcd0; alias, 1 drivers -v0x115ef60_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1159af0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11598d0; +v0x2c33e30_0 .net "ands", 7 0, L_0x2ddcde0; 1 drivers +v0x2c33f40_0 .net "in", 7 0, L_0x2dd7650; alias, 1 drivers +v0x2c34000_0 .net "out", 0 0, L_0x2ddede0; alias, 1 drivers +v0x2c340d0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c2ec60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c2ea40; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x115c220_0 .net "A", 7 0, L_0x13555d0; alias, 1 drivers -v0x115c320_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x115c3e0_0 .net *"_s0", 0 0, L_0x12ec5f0; 1 drivers -v0x115c4a0_0 .net *"_s12", 0 0, L_0x12ecf60; 1 drivers -v0x115c580_0 .net *"_s16", 0 0, L_0x12ed2c0; 1 drivers -v0x115c6b0_0 .net *"_s20", 0 0, L_0x12ed5d0; 1 drivers -v0x115c790_0 .net *"_s24", 0 0, L_0x12ed9c0; 1 drivers -v0x115c870_0 .net *"_s28", 0 0, L_0x12ed950; 1 drivers -v0x115c950_0 .net *"_s4", 0 0, L_0x12ec900; 1 drivers -v0x115cac0_0 .net *"_s8", 0 0, L_0x12ecc50; 1 drivers -v0x115cba0_0 .net "out", 7 0, L_0x12edcd0; alias, 1 drivers -L_0x12ec6b0 .part L_0x13555d0, 0, 1; -L_0x12ec810 .part v0x12010b0_0, 0, 1; -L_0x12ec9c0 .part L_0x13555d0, 1, 1; -L_0x12ecbb0 .part v0x12010b0_0, 1, 1; -L_0x12ecd10 .part L_0x13555d0, 2, 1; -L_0x12ece70 .part v0x12010b0_0, 2, 1; -L_0x12ed020 .part L_0x13555d0, 3, 1; -L_0x12ed180 .part v0x12010b0_0, 3, 1; -L_0x12ed380 .part L_0x13555d0, 4, 1; -L_0x12ed4e0 .part v0x12010b0_0, 4, 1; -L_0x12ed640 .part L_0x13555d0, 5, 1; -L_0x12ed8b0 .part v0x12010b0_0, 5, 1; -L_0x12eda80 .part L_0x13555d0, 6, 1; -L_0x12edbe0 .part v0x12010b0_0, 6, 1; -LS_0x12edcd0_0_0 .concat8 [ 1 1 1 1], L_0x12ec5f0, L_0x12ec900, L_0x12ecc50, L_0x12ecf60; -LS_0x12edcd0_0_4 .concat8 [ 1 1 1 1], L_0x12ed2c0, L_0x12ed5d0, L_0x12ed9c0, L_0x12ed950; -L_0x12edcd0 .concat8 [ 4 4 0 0], LS_0x12edcd0_0_0, LS_0x12edcd0_0_4; -L_0x12ee090 .part L_0x13555d0, 7, 1; -L_0x12ee280 .part v0x12010b0_0, 7, 1; -S_0x1159d50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x1159f60 .param/l "i" 0 4 54, +C4<00>; -L_0x12ec5f0/d .functor AND 1, L_0x12ec6b0, L_0x12ec810, C4<1>, C4<1>; -L_0x12ec5f0 .delay 1 (30000,30000,30000) L_0x12ec5f0/d; -v0x115a040_0 .net *"_s0", 0 0, L_0x12ec6b0; 1 drivers -v0x115a120_0 .net *"_s1", 0 0, L_0x12ec810; 1 drivers -S_0x115a200 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115a410 .param/l "i" 0 4 54, +C4<01>; -L_0x12ec900/d .functor AND 1, L_0x12ec9c0, L_0x12ecbb0, C4<1>, C4<1>; -L_0x12ec900 .delay 1 (30000,30000,30000) L_0x12ec900/d; -v0x115a4d0_0 .net *"_s0", 0 0, L_0x12ec9c0; 1 drivers -v0x115a5b0_0 .net *"_s1", 0 0, L_0x12ecbb0; 1 drivers -S_0x115a690 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115a8a0 .param/l "i" 0 4 54, +C4<010>; -L_0x12ecc50/d .functor AND 1, L_0x12ecd10, L_0x12ece70, C4<1>, C4<1>; -L_0x12ecc50 .delay 1 (30000,30000,30000) L_0x12ecc50/d; -v0x115a940_0 .net *"_s0", 0 0, L_0x12ecd10; 1 drivers -v0x115aa20_0 .net *"_s1", 0 0, L_0x12ece70; 1 drivers -S_0x115ab00 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115ad10 .param/l "i" 0 4 54, +C4<011>; -L_0x12ecf60/d .functor AND 1, L_0x12ed020, L_0x12ed180, C4<1>, C4<1>; -L_0x12ecf60 .delay 1 (30000,30000,30000) L_0x12ecf60/d; -v0x115add0_0 .net *"_s0", 0 0, L_0x12ed020; 1 drivers -v0x115aeb0_0 .net *"_s1", 0 0, L_0x12ed180; 1 drivers -S_0x115af90 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115b1f0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12ed2c0/d .functor AND 1, L_0x12ed380, L_0x12ed4e0, C4<1>, C4<1>; -L_0x12ed2c0 .delay 1 (30000,30000,30000) L_0x12ed2c0/d; -v0x115b2b0_0 .net *"_s0", 0 0, L_0x12ed380; 1 drivers -v0x115b390_0 .net *"_s1", 0 0, L_0x12ed4e0; 1 drivers -S_0x115b470 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115b680 .param/l "i" 0 4 54, +C4<0101>; -L_0x12ed5d0/d .functor AND 1, L_0x12ed640, L_0x12ed8b0, C4<1>, C4<1>; -L_0x12ed5d0 .delay 1 (30000,30000,30000) L_0x12ed5d0/d; -v0x115b740_0 .net *"_s0", 0 0, L_0x12ed640; 1 drivers -v0x115b820_0 .net *"_s1", 0 0, L_0x12ed8b0; 1 drivers -S_0x115b900 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115bb10 .param/l "i" 0 4 54, +C4<0110>; -L_0x12ed9c0/d .functor AND 1, L_0x12eda80, L_0x12edbe0, C4<1>, C4<1>; -L_0x12ed9c0 .delay 1 (30000,30000,30000) L_0x12ed9c0/d; -v0x115bbd0_0 .net *"_s0", 0 0, L_0x12eda80; 1 drivers -v0x115bcb0_0 .net *"_s1", 0 0, L_0x12edbe0; 1 drivers -S_0x115bd90 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1159af0; - .timescale -9 -12; -P_0x115bfa0 .param/l "i" 0 4 54, +C4<0111>; -L_0x12ed950/d .functor AND 1, L_0x12ee090, L_0x12ee280, C4<1>, C4<1>; -L_0x12ed950 .delay 1 (30000,30000,30000) L_0x12ed950/d; -v0x115c060_0 .net *"_s0", 0 0, L_0x12ee090; 1 drivers -v0x115c140_0 .net *"_s1", 0 0, L_0x12ee280; 1 drivers -S_0x115cd00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11598d0; +v0x2c31390_0 .net "A", 7 0, L_0x2dd7650; alias, 1 drivers +v0x2c31490_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c31550_0 .net *"_s0", 0 0, L_0x2ddb700; 1 drivers +v0x2c31610_0 .net *"_s12", 0 0, L_0x2ddc070; 1 drivers +v0x2c316f0_0 .net *"_s16", 0 0, L_0x2ddc3d0; 1 drivers +v0x2c31820_0 .net *"_s20", 0 0, L_0x2ddc7a0; 1 drivers +v0x2c31900_0 .net *"_s24", 0 0, L_0x2ddcad0; 1 drivers +v0x2c319e0_0 .net *"_s28", 0 0, L_0x2ddca60; 1 drivers +v0x2c31ac0_0 .net *"_s4", 0 0, L_0x2ddba50; 1 drivers +v0x2c31c30_0 .net *"_s8", 0 0, L_0x2ddbd60; 1 drivers +v0x2c31d10_0 .net "out", 7 0, L_0x2ddcde0; alias, 1 drivers +L_0x2ddb7c0 .part L_0x2dd7650, 0, 1; +L_0x2ddb9b0 .part v0x2cdd2e0_0, 0, 1; +L_0x2ddbb10 .part L_0x2dd7650, 1, 1; +L_0x2ddbc70 .part v0x2cdd2e0_0, 1, 1; +L_0x2ddbe20 .part L_0x2dd7650, 2, 1; +L_0x2ddbf80 .part v0x2cdd2e0_0, 2, 1; +L_0x2ddc130 .part L_0x2dd7650, 3, 1; +L_0x2ddc290 .part v0x2cdd2e0_0, 3, 1; +L_0x2ddc490 .part L_0x2dd7650, 4, 1; +L_0x2ddc700 .part v0x2cdd2e0_0, 4, 1; +L_0x2ddc810 .part L_0x2dd7650, 5, 1; +L_0x2ddc970 .part v0x2cdd2e0_0, 5, 1; +L_0x2ddcb90 .part L_0x2dd7650, 6, 1; +L_0x2ddccf0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2ddcde0_0_0 .concat8 [ 1 1 1 1], L_0x2ddb700, L_0x2ddba50, L_0x2ddbd60, L_0x2ddc070; +LS_0x2ddcde0_0_4 .concat8 [ 1 1 1 1], L_0x2ddc3d0, L_0x2ddc7a0, L_0x2ddcad0, L_0x2ddca60; +L_0x2ddcde0 .concat8 [ 4 4 0 0], LS_0x2ddcde0_0_0, LS_0x2ddcde0_0_4; +L_0x2ddd1a0 .part L_0x2dd7650, 7, 1; +L_0x2ddd390 .part v0x2cdd2e0_0, 7, 1; +S_0x2c2eec0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c2f0d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2ddb700/d .functor AND 1, L_0x2ddb7c0, L_0x2ddb9b0, C4<1>, C4<1>; +L_0x2ddb700 .delay 1 (30000,30000,30000) L_0x2ddb700/d; +v0x2c2f1b0_0 .net *"_s0", 0 0, L_0x2ddb7c0; 1 drivers +v0x2c2f290_0 .net *"_s1", 0 0, L_0x2ddb9b0; 1 drivers +S_0x2c2f370 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c2f580 .param/l "i" 0 4 54, +C4<01>; +L_0x2ddba50/d .functor AND 1, L_0x2ddbb10, L_0x2ddbc70, C4<1>, C4<1>; +L_0x2ddba50 .delay 1 (30000,30000,30000) L_0x2ddba50/d; +v0x2c2f640_0 .net *"_s0", 0 0, L_0x2ddbb10; 1 drivers +v0x2c2f720_0 .net *"_s1", 0 0, L_0x2ddbc70; 1 drivers +S_0x2c2f800 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c2fa10 .param/l "i" 0 4 54, +C4<010>; +L_0x2ddbd60/d .functor AND 1, L_0x2ddbe20, L_0x2ddbf80, C4<1>, C4<1>; +L_0x2ddbd60 .delay 1 (30000,30000,30000) L_0x2ddbd60/d; +v0x2c2fab0_0 .net *"_s0", 0 0, L_0x2ddbe20; 1 drivers +v0x2c2fb90_0 .net *"_s1", 0 0, L_0x2ddbf80; 1 drivers +S_0x2c2fc70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c2fe80 .param/l "i" 0 4 54, +C4<011>; +L_0x2ddc070/d .functor AND 1, L_0x2ddc130, L_0x2ddc290, C4<1>, C4<1>; +L_0x2ddc070 .delay 1 (30000,30000,30000) L_0x2ddc070/d; +v0x2c2ff40_0 .net *"_s0", 0 0, L_0x2ddc130; 1 drivers +v0x2c30020_0 .net *"_s1", 0 0, L_0x2ddc290; 1 drivers +S_0x2c30100 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c30360 .param/l "i" 0 4 54, +C4<0100>; +L_0x2ddc3d0/d .functor AND 1, L_0x2ddc490, L_0x2ddc700, C4<1>, C4<1>; +L_0x2ddc3d0 .delay 1 (30000,30000,30000) L_0x2ddc3d0/d; +v0x2c30420_0 .net *"_s0", 0 0, L_0x2ddc490; 1 drivers +v0x2c30500_0 .net *"_s1", 0 0, L_0x2ddc700; 1 drivers +S_0x2c305e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c307f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2ddc7a0/d .functor AND 1, L_0x2ddc810, L_0x2ddc970, C4<1>, C4<1>; +L_0x2ddc7a0 .delay 1 (30000,30000,30000) L_0x2ddc7a0/d; +v0x2c308b0_0 .net *"_s0", 0 0, L_0x2ddc810; 1 drivers +v0x2c30990_0 .net *"_s1", 0 0, L_0x2ddc970; 1 drivers +S_0x2c30a70 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c30c80 .param/l "i" 0 4 54, +C4<0110>; +L_0x2ddcad0/d .functor AND 1, L_0x2ddcb90, L_0x2ddccf0, C4<1>, C4<1>; +L_0x2ddcad0 .delay 1 (30000,30000,30000) L_0x2ddcad0/d; +v0x2c30d40_0 .net *"_s0", 0 0, L_0x2ddcb90; 1 drivers +v0x2c30e20_0 .net *"_s1", 0 0, L_0x2ddccf0; 1 drivers +S_0x2c30f00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c2ec60; + .timescale -9 -12; +P_0x2c31110 .param/l "i" 0 4 54, +C4<0111>; +L_0x2ddca60/d .functor AND 1, L_0x2ddd1a0, L_0x2ddd390, C4<1>, C4<1>; +L_0x2ddca60 .delay 1 (30000,30000,30000) L_0x2ddca60/d; +v0x2c311d0_0 .net *"_s0", 0 0, L_0x2ddd1a0; 1 drivers +v0x2c312b0_0 .net *"_s1", 0 0, L_0x2ddd390; 1 drivers +S_0x2c31e70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c2ea40; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12efcd0/d .functor OR 1, L_0x12efd90, L_0x12eff40, C4<0>, C4<0>; -L_0x12efcd0 .delay 1 (30000,30000,30000) L_0x12efcd0/d; -v0x115e850_0 .net *"_s10", 0 0, L_0x12efd90; 1 drivers -v0x115e930_0 .net *"_s12", 0 0, L_0x12eff40; 1 drivers -v0x115ea10_0 .net "in", 7 0, L_0x12edcd0; alias, 1 drivers -v0x115eae0_0 .net "ors", 1 0, L_0x12efaf0; 1 drivers -v0x115eba0_0 .net "out", 0 0, L_0x12efcd0; alias, 1 drivers -L_0x12eeec0 .part L_0x12edcd0, 0, 4; -L_0x12efaf0 .concat8 [ 1 1 0 0], L_0x12eebb0, L_0x12ef7e0; -L_0x12efc30 .part L_0x12edcd0, 4, 4; -L_0x12efd90 .part L_0x12efaf0, 0, 1; -L_0x12eff40 .part L_0x12efaf0, 1, 1; -S_0x115cec0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x115cd00; +L_0x2ddede0/d .functor OR 1, L_0x2ddeea0, L_0x2ddf050, C4<0>, C4<0>; +L_0x2ddede0 .delay 1 (30000,30000,30000) L_0x2ddede0/d; +v0x2c339c0_0 .net *"_s10", 0 0, L_0x2ddeea0; 1 drivers +v0x2c33aa0_0 .net *"_s12", 0 0, L_0x2ddf050; 1 drivers +v0x2c33b80_0 .net "in", 7 0, L_0x2ddcde0; alias, 1 drivers +v0x2c33c50_0 .net "ors", 1 0, L_0x2ddec00; 1 drivers +v0x2c33d10_0 .net "out", 0 0, L_0x2ddede0; alias, 1 drivers +L_0x2dddfd0 .part L_0x2ddcde0, 0, 4; +L_0x2ddec00 .concat8 [ 1 1 0 0], L_0x2dddcc0, L_0x2dde8f0; +L_0x2dded40 .part L_0x2ddcde0, 4, 4; +L_0x2ddeea0 .part L_0x2ddec00, 0, 1; +L_0x2ddf050 .part L_0x2ddec00, 1, 1; +S_0x2c32030 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c31e70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12ee370/d .functor OR 1, L_0x12ee430, L_0x12ee590, C4<0>, C4<0>; -L_0x12ee370 .delay 1 (30000,30000,30000) L_0x12ee370/d; -L_0x12ee7c0/d .functor OR 1, L_0x12ee8d0, L_0x12eea30, C4<0>, C4<0>; -L_0x12ee7c0 .delay 1 (30000,30000,30000) L_0x12ee7c0/d; -L_0x12eebb0/d .functor OR 1, L_0x12eec20, L_0x12eedd0, C4<0>, C4<0>; -L_0x12eebb0 .delay 1 (30000,30000,30000) L_0x12eebb0/d; -v0x115d110_0 .net *"_s0", 0 0, L_0x12ee370; 1 drivers -v0x115d210_0 .net *"_s10", 0 0, L_0x12ee8d0; 1 drivers -v0x115d2f0_0 .net *"_s12", 0 0, L_0x12eea30; 1 drivers -v0x115d3b0_0 .net *"_s14", 0 0, L_0x12eec20; 1 drivers -v0x115d490_0 .net *"_s16", 0 0, L_0x12eedd0; 1 drivers -v0x115d5c0_0 .net *"_s3", 0 0, L_0x12ee430; 1 drivers -v0x115d6a0_0 .net *"_s5", 0 0, L_0x12ee590; 1 drivers -v0x115d780_0 .net *"_s6", 0 0, L_0x12ee7c0; 1 drivers -v0x115d860_0 .net "in", 3 0, L_0x12eeec0; 1 drivers -v0x115d9d0_0 .net "ors", 1 0, L_0x12ee6d0; 1 drivers -v0x115dab0_0 .net "out", 0 0, L_0x12eebb0; 1 drivers -L_0x12ee430 .part L_0x12eeec0, 0, 1; -L_0x12ee590 .part L_0x12eeec0, 1, 1; -L_0x12ee6d0 .concat8 [ 1 1 0 0], L_0x12ee370, L_0x12ee7c0; -L_0x12ee8d0 .part L_0x12eeec0, 2, 1; -L_0x12eea30 .part L_0x12eeec0, 3, 1; -L_0x12eec20 .part L_0x12ee6d0, 0, 1; -L_0x12eedd0 .part L_0x12ee6d0, 1, 1; -S_0x115dbd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x115cd00; +L_0x2ddd480/d .functor OR 1, L_0x2ddd540, L_0x2ddd6a0, C4<0>, C4<0>; +L_0x2ddd480 .delay 1 (30000,30000,30000) L_0x2ddd480/d; +L_0x2ddd8d0/d .functor OR 1, L_0x2ddd9e0, L_0x2dddb40, C4<0>, C4<0>; +L_0x2ddd8d0 .delay 1 (30000,30000,30000) L_0x2ddd8d0/d; +L_0x2dddcc0/d .functor OR 1, L_0x2dddd30, L_0x2dddee0, C4<0>, C4<0>; +L_0x2dddcc0 .delay 1 (30000,30000,30000) L_0x2dddcc0/d; +v0x2c32280_0 .net *"_s0", 0 0, L_0x2ddd480; 1 drivers +v0x2c32380_0 .net *"_s10", 0 0, L_0x2ddd9e0; 1 drivers +v0x2c32460_0 .net *"_s12", 0 0, L_0x2dddb40; 1 drivers +v0x2c32520_0 .net *"_s14", 0 0, L_0x2dddd30; 1 drivers +v0x2c32600_0 .net *"_s16", 0 0, L_0x2dddee0; 1 drivers +v0x2c32730_0 .net *"_s3", 0 0, L_0x2ddd540; 1 drivers +v0x2c32810_0 .net *"_s5", 0 0, L_0x2ddd6a0; 1 drivers +v0x2c328f0_0 .net *"_s6", 0 0, L_0x2ddd8d0; 1 drivers +v0x2c329d0_0 .net "in", 3 0, L_0x2dddfd0; 1 drivers +v0x2c32b40_0 .net "ors", 1 0, L_0x2ddd7e0; 1 drivers +v0x2c32c20_0 .net "out", 0 0, L_0x2dddcc0; 1 drivers +L_0x2ddd540 .part L_0x2dddfd0, 0, 1; +L_0x2ddd6a0 .part L_0x2dddfd0, 1, 1; +L_0x2ddd7e0 .concat8 [ 1 1 0 0], L_0x2ddd480, L_0x2ddd8d0; +L_0x2ddd9e0 .part L_0x2dddfd0, 2, 1; +L_0x2dddb40 .part L_0x2dddfd0, 3, 1; +L_0x2dddd30 .part L_0x2ddd7e0, 0, 1; +L_0x2dddee0 .part L_0x2ddd7e0, 1, 1; +S_0x2c32d40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c31e70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12eeff0/d .functor OR 1, L_0x12ef060, L_0x12ef1c0, C4<0>, C4<0>; -L_0x12eeff0 .delay 1 (30000,30000,30000) L_0x12eeff0/d; -L_0x12ef3f0/d .functor OR 1, L_0x12ef500, L_0x12ef660, C4<0>, C4<0>; -L_0x12ef3f0 .delay 1 (30000,30000,30000) L_0x12ef3f0/d; -L_0x12ef7e0/d .functor OR 1, L_0x12ef850, L_0x12efa00, C4<0>, C4<0>; -L_0x12ef7e0 .delay 1 (30000,30000,30000) L_0x12ef7e0/d; -v0x115dd90_0 .net *"_s0", 0 0, L_0x12eeff0; 1 drivers -v0x115de90_0 .net *"_s10", 0 0, L_0x12ef500; 1 drivers -v0x115df70_0 .net *"_s12", 0 0, L_0x12ef660; 1 drivers -v0x115e030_0 .net *"_s14", 0 0, L_0x12ef850; 1 drivers -v0x115e110_0 .net *"_s16", 0 0, L_0x12efa00; 1 drivers -v0x115e240_0 .net *"_s3", 0 0, L_0x12ef060; 1 drivers -v0x115e320_0 .net *"_s5", 0 0, L_0x12ef1c0; 1 drivers -v0x115e400_0 .net *"_s6", 0 0, L_0x12ef3f0; 1 drivers -v0x115e4e0_0 .net "in", 3 0, L_0x12efc30; 1 drivers -v0x115e650_0 .net "ors", 1 0, L_0x12ef300; 1 drivers -v0x115e730_0 .net "out", 0 0, L_0x12ef7e0; 1 drivers -L_0x12ef060 .part L_0x12efc30, 0, 1; -L_0x12ef1c0 .part L_0x12efc30, 1, 1; -L_0x12ef300 .concat8 [ 1 1 0 0], L_0x12eeff0, L_0x12ef3f0; -L_0x12ef500 .part L_0x12efc30, 2, 1; -L_0x12ef660 .part L_0x12efc30, 3, 1; -L_0x12ef850 .part L_0x12ef300, 0, 1; -L_0x12efa00 .part L_0x12ef300, 1, 1; -S_0x115f040 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1158170; +L_0x2dde100/d .functor OR 1, L_0x2dde170, L_0x2dde2d0, C4<0>, C4<0>; +L_0x2dde100 .delay 1 (30000,30000,30000) L_0x2dde100/d; +L_0x2dde500/d .functor OR 1, L_0x2dde610, L_0x2dde770, C4<0>, C4<0>; +L_0x2dde500 .delay 1 (30000,30000,30000) L_0x2dde500/d; +L_0x2dde8f0/d .functor OR 1, L_0x2dde960, L_0x2ddeb10, C4<0>, C4<0>; +L_0x2dde8f0 .delay 1 (30000,30000,30000) L_0x2dde8f0/d; +v0x2c32f00_0 .net *"_s0", 0 0, L_0x2dde100; 1 drivers +v0x2c33000_0 .net *"_s10", 0 0, L_0x2dde610; 1 drivers +v0x2c330e0_0 .net *"_s12", 0 0, L_0x2dde770; 1 drivers +v0x2c331a0_0 .net *"_s14", 0 0, L_0x2dde960; 1 drivers +v0x2c33280_0 .net *"_s16", 0 0, L_0x2ddeb10; 1 drivers +v0x2c333b0_0 .net *"_s3", 0 0, L_0x2dde170; 1 drivers +v0x2c33490_0 .net *"_s5", 0 0, L_0x2dde2d0; 1 drivers +v0x2c33570_0 .net *"_s6", 0 0, L_0x2dde500; 1 drivers +v0x2c33650_0 .net "in", 3 0, L_0x2dded40; 1 drivers +v0x2c337c0_0 .net "ors", 1 0, L_0x2dde410; 1 drivers +v0x2c338a0_0 .net "out", 0 0, L_0x2dde8f0; 1 drivers +L_0x2dde170 .part L_0x2dded40, 0, 1; +L_0x2dde2d0 .part L_0x2dded40, 1, 1; +L_0x2dde410 .concat8 [ 1 1 0 0], L_0x2dde100, L_0x2dde500; +L_0x2dde610 .part L_0x2dded40, 2, 1; +L_0x2dde770 .part L_0x2dded40, 3, 1; +L_0x2dde960 .part L_0x2dde410, 0, 1; +L_0x2ddeb10 .part L_0x2dde410, 1, 1; +S_0x2c341b0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c2d2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1164470_0 .net "ands", 7 0, L_0x12ea290; 1 drivers -v0x1164580_0 .net "in", 7 0, L_0x12e87d0; alias, 1 drivers -v0x1164640_0 .net "out", 0 0, L_0x12ec290; alias, 1 drivers -v0x1164710_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x115f290 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x115f040; +v0x2c395e0_0 .net "ands", 7 0, L_0x2dd93a0; 1 drivers +v0x2c396f0_0 .net "in", 7 0, L_0x2dd7310; alias, 1 drivers +v0x2c397b0_0 .net "out", 0 0, L_0x2ddb3a0; alias, 1 drivers +v0x2c39880_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c34400 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c341b0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11619d0_0 .net "A", 7 0, L_0x12e87d0; alias, 1 drivers -v0x1161ad0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1161b90_0 .net *"_s0", 0 0, L_0x12e8b60; 1 drivers -v0x1161c50_0 .net *"_s12", 0 0, L_0x12e9520; 1 drivers -v0x1161d30_0 .net *"_s16", 0 0, L_0x12e9880; 1 drivers -v0x1161e60_0 .net *"_s20", 0 0, L_0x12e9c50; 1 drivers -v0x1161f40_0 .net *"_s24", 0 0, L_0x12e9f80; 1 drivers -v0x1162020_0 .net *"_s28", 0 0, L_0x12e9f10; 1 drivers -v0x1162100_0 .net *"_s4", 0 0, L_0x12e8f00; 1 drivers -v0x1162270_0 .net *"_s8", 0 0, L_0x12e9210; 1 drivers -v0x1162350_0 .net "out", 7 0, L_0x12ea290; alias, 1 drivers -L_0x12e8c70 .part L_0x12e87d0, 0, 1; -L_0x12e8e60 .part v0x12010b0_0, 0, 1; -L_0x12e8fc0 .part L_0x12e87d0, 1, 1; -L_0x12e9120 .part v0x12010b0_0, 1, 1; -L_0x12e92d0 .part L_0x12e87d0, 2, 1; -L_0x12e9430 .part v0x12010b0_0, 2, 1; -L_0x12e95e0 .part L_0x12e87d0, 3, 1; -L_0x12e9740 .part v0x12010b0_0, 3, 1; -L_0x12e9940 .part L_0x12e87d0, 4, 1; -L_0x12e9bb0 .part v0x12010b0_0, 4, 1; -L_0x12e9cc0 .part L_0x12e87d0, 5, 1; -L_0x12e9e20 .part v0x12010b0_0, 5, 1; -L_0x12ea040 .part L_0x12e87d0, 6, 1; -L_0x12ea1a0 .part v0x12010b0_0, 6, 1; -LS_0x12ea290_0_0 .concat8 [ 1 1 1 1], L_0x12e8b60, L_0x12e8f00, L_0x12e9210, L_0x12e9520; -LS_0x12ea290_0_4 .concat8 [ 1 1 1 1], L_0x12e9880, L_0x12e9c50, L_0x12e9f80, L_0x12e9f10; -L_0x12ea290 .concat8 [ 4 4 0 0], LS_0x12ea290_0_0, LS_0x12ea290_0_4; -L_0x12ea650 .part L_0x12e87d0, 7, 1; -L_0x12ea840 .part v0x12010b0_0, 7, 1; -S_0x115f4d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x115f6e0 .param/l "i" 0 4 54, +C4<00>; -L_0x12e8b60/d .functor AND 1, L_0x12e8c70, L_0x12e8e60, C4<1>, C4<1>; -L_0x12e8b60 .delay 1 (30000,30000,30000) L_0x12e8b60/d; -v0x115f7c0_0 .net *"_s0", 0 0, L_0x12e8c70; 1 drivers -v0x115f8a0_0 .net *"_s1", 0 0, L_0x12e8e60; 1 drivers -S_0x115f980 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x115fb90 .param/l "i" 0 4 54, +C4<01>; -L_0x12e8f00/d .functor AND 1, L_0x12e8fc0, L_0x12e9120, C4<1>, C4<1>; -L_0x12e8f00 .delay 1 (30000,30000,30000) L_0x12e8f00/d; -v0x115fc50_0 .net *"_s0", 0 0, L_0x12e8fc0; 1 drivers -v0x115fd30_0 .net *"_s1", 0 0, L_0x12e9120; 1 drivers -S_0x115fe10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x1160050 .param/l "i" 0 4 54, +C4<010>; -L_0x12e9210/d .functor AND 1, L_0x12e92d0, L_0x12e9430, C4<1>, C4<1>; -L_0x12e9210 .delay 1 (30000,30000,30000) L_0x12e9210/d; -v0x11600f0_0 .net *"_s0", 0 0, L_0x12e92d0; 1 drivers -v0x11601d0_0 .net *"_s1", 0 0, L_0x12e9430; 1 drivers -S_0x11602b0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x11604c0 .param/l "i" 0 4 54, +C4<011>; -L_0x12e9520/d .functor AND 1, L_0x12e95e0, L_0x12e9740, C4<1>, C4<1>; -L_0x12e9520 .delay 1 (30000,30000,30000) L_0x12e9520/d; -v0x1160580_0 .net *"_s0", 0 0, L_0x12e95e0; 1 drivers -v0x1160660_0 .net *"_s1", 0 0, L_0x12e9740; 1 drivers -S_0x1160740 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x11609a0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12e9880/d .functor AND 1, L_0x12e9940, L_0x12e9bb0, C4<1>, C4<1>; -L_0x12e9880 .delay 1 (30000,30000,30000) L_0x12e9880/d; -v0x1160a60_0 .net *"_s0", 0 0, L_0x12e9940; 1 drivers -v0x1160b40_0 .net *"_s1", 0 0, L_0x12e9bb0; 1 drivers -S_0x1160c20 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x1160e30 .param/l "i" 0 4 54, +C4<0101>; -L_0x12e9c50/d .functor AND 1, L_0x12e9cc0, L_0x12e9e20, C4<1>, C4<1>; -L_0x12e9c50 .delay 1 (30000,30000,30000) L_0x12e9c50/d; -v0x1160ef0_0 .net *"_s0", 0 0, L_0x12e9cc0; 1 drivers -v0x1160fd0_0 .net *"_s1", 0 0, L_0x12e9e20; 1 drivers -S_0x11610b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x11612c0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12e9f80/d .functor AND 1, L_0x12ea040, L_0x12ea1a0, C4<1>, C4<1>; -L_0x12e9f80 .delay 1 (30000,30000,30000) L_0x12e9f80/d; -v0x1161380_0 .net *"_s0", 0 0, L_0x12ea040; 1 drivers -v0x1161460_0 .net *"_s1", 0 0, L_0x12ea1a0; 1 drivers -S_0x1161540 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x115f290; - .timescale -9 -12; -P_0x1161750 .param/l "i" 0 4 54, +C4<0111>; -L_0x12e9f10/d .functor AND 1, L_0x12ea650, L_0x12ea840, C4<1>, C4<1>; -L_0x12e9f10 .delay 1 (30000,30000,30000) L_0x12e9f10/d; -v0x1161810_0 .net *"_s0", 0 0, L_0x12ea650; 1 drivers -v0x11618f0_0 .net *"_s1", 0 0, L_0x12ea840; 1 drivers -S_0x11624b0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x115f040; +v0x2c36b40_0 .net "A", 7 0, L_0x2dd7310; alias, 1 drivers +v0x2c36c40_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c36d00_0 .net *"_s0", 0 0, L_0x2dd7b90; 1 drivers +v0x2c36dc0_0 .net *"_s12", 0 0, L_0x2dd8550; 1 drivers +v0x2c36ea0_0 .net *"_s16", 0 0, L_0x2dd88b0; 1 drivers +v0x2c36fd0_0 .net *"_s20", 0 0, L_0x2dd8ce0; 1 drivers +v0x2c370b0_0 .net *"_s24", 0 0, L_0x2dd9010; 1 drivers +v0x2c37190_0 .net *"_s28", 0 0, L_0x2dd8fa0; 1 drivers +v0x2c37270_0 .net *"_s4", 0 0, L_0x2dd7f30; 1 drivers +v0x2c373e0_0 .net *"_s8", 0 0, L_0x2dd8240; 1 drivers +v0x2c374c0_0 .net "out", 7 0, L_0x2dd93a0; alias, 1 drivers +L_0x2dd7ca0 .part L_0x2dd7310, 0, 1; +L_0x2dd7e90 .part v0x2cdd2e0_0, 0, 1; +L_0x2dd7ff0 .part L_0x2dd7310, 1, 1; +L_0x2dd8150 .part v0x2cdd2e0_0, 1, 1; +L_0x2dd8300 .part L_0x2dd7310, 2, 1; +L_0x2dd8460 .part v0x2cdd2e0_0, 2, 1; +L_0x2dd8610 .part L_0x2dd7310, 3, 1; +L_0x2dd8770 .part v0x2cdd2e0_0, 3, 1; +L_0x2dd8970 .part L_0x2dd7310, 4, 1; +L_0x2dd8be0 .part v0x2cdd2e0_0, 4, 1; +L_0x2dd8d50 .part L_0x2dd7310, 5, 1; +L_0x2dd8eb0 .part v0x2cdd2e0_0, 5, 1; +L_0x2dd90d0 .part L_0x2dd7310, 6, 1; +L_0x2dd9230 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dd93a0_0_0 .concat8 [ 1 1 1 1], L_0x2dd7b90, L_0x2dd7f30, L_0x2dd8240, L_0x2dd8550; +LS_0x2dd93a0_0_4 .concat8 [ 1 1 1 1], L_0x2dd88b0, L_0x2dd8ce0, L_0x2dd9010, L_0x2dd8fa0; +L_0x2dd93a0 .concat8 [ 4 4 0 0], LS_0x2dd93a0_0_0, LS_0x2dd93a0_0_4; +L_0x2dd9760 .part L_0x2dd7310, 7, 1; +L_0x2dd9950 .part v0x2cdd2e0_0, 7, 1; +S_0x2c34640 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c34850 .param/l "i" 0 4 54, +C4<00>; +L_0x2dd7b90/d .functor AND 1, L_0x2dd7ca0, L_0x2dd7e90, C4<1>, C4<1>; +L_0x2dd7b90 .delay 1 (30000,30000,30000) L_0x2dd7b90/d; +v0x2c34930_0 .net *"_s0", 0 0, L_0x2dd7ca0; 1 drivers +v0x2c34a10_0 .net *"_s1", 0 0, L_0x2dd7e90; 1 drivers +S_0x2c34af0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c34d00 .param/l "i" 0 4 54, +C4<01>; +L_0x2dd7f30/d .functor AND 1, L_0x2dd7ff0, L_0x2dd8150, C4<1>, C4<1>; +L_0x2dd7f30 .delay 1 (30000,30000,30000) L_0x2dd7f30/d; +v0x2c34dc0_0 .net *"_s0", 0 0, L_0x2dd7ff0; 1 drivers +v0x2c34ea0_0 .net *"_s1", 0 0, L_0x2dd8150; 1 drivers +S_0x2c34f80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c351c0 .param/l "i" 0 4 54, +C4<010>; +L_0x2dd8240/d .functor AND 1, L_0x2dd8300, L_0x2dd8460, C4<1>, C4<1>; +L_0x2dd8240 .delay 1 (30000,30000,30000) L_0x2dd8240/d; +v0x2c35260_0 .net *"_s0", 0 0, L_0x2dd8300; 1 drivers +v0x2c35340_0 .net *"_s1", 0 0, L_0x2dd8460; 1 drivers +S_0x2c35420 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c35630 .param/l "i" 0 4 54, +C4<011>; +L_0x2dd8550/d .functor AND 1, L_0x2dd8610, L_0x2dd8770, C4<1>, C4<1>; +L_0x2dd8550 .delay 1 (30000,30000,30000) L_0x2dd8550/d; +v0x2c356f0_0 .net *"_s0", 0 0, L_0x2dd8610; 1 drivers +v0x2c357d0_0 .net *"_s1", 0 0, L_0x2dd8770; 1 drivers +S_0x2c358b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c35b10 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dd88b0/d .functor AND 1, L_0x2dd8970, L_0x2dd8be0, C4<1>, C4<1>; +L_0x2dd88b0 .delay 1 (30000,30000,30000) L_0x2dd88b0/d; +v0x2c35bd0_0 .net *"_s0", 0 0, L_0x2dd8970; 1 drivers +v0x2c35cb0_0 .net *"_s1", 0 0, L_0x2dd8be0; 1 drivers +S_0x2c35d90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c35fa0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dd8ce0/d .functor AND 1, L_0x2dd8d50, L_0x2dd8eb0, C4<1>, C4<1>; +L_0x2dd8ce0 .delay 1 (30000,30000,30000) L_0x2dd8ce0/d; +v0x2c36060_0 .net *"_s0", 0 0, L_0x2dd8d50; 1 drivers +v0x2c36140_0 .net *"_s1", 0 0, L_0x2dd8eb0; 1 drivers +S_0x2c36220 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c36430 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dd9010/d .functor AND 1, L_0x2dd90d0, L_0x2dd9230, C4<1>, C4<1>; +L_0x2dd9010 .delay 1 (30000,30000,30000) L_0x2dd9010/d; +v0x2c364f0_0 .net *"_s0", 0 0, L_0x2dd90d0; 1 drivers +v0x2c365d0_0 .net *"_s1", 0 0, L_0x2dd9230; 1 drivers +S_0x2c366b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c34400; + .timescale -9 -12; +P_0x2c368c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dd8fa0/d .functor AND 1, L_0x2dd9760, L_0x2dd9950, C4<1>, C4<1>; +L_0x2dd8fa0 .delay 1 (30000,30000,30000) L_0x2dd8fa0/d; +v0x2c36980_0 .net *"_s0", 0 0, L_0x2dd9760; 1 drivers +v0x2c36a60_0 .net *"_s1", 0 0, L_0x2dd9950; 1 drivers +S_0x2c37620 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c341b0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12ec290/d .functor OR 1, L_0x12ec350, L_0x12ec500, C4<0>, C4<0>; -L_0x12ec290 .delay 1 (30000,30000,30000) L_0x12ec290/d; -v0x1164000_0 .net *"_s10", 0 0, L_0x12ec350; 1 drivers -v0x11640e0_0 .net *"_s12", 0 0, L_0x12ec500; 1 drivers -v0x11641c0_0 .net "in", 7 0, L_0x12ea290; alias, 1 drivers -v0x1164290_0 .net "ors", 1 0, L_0x12ec0b0; 1 drivers -v0x1164350_0 .net "out", 0 0, L_0x12ec290; alias, 1 drivers -L_0x12eb480 .part L_0x12ea290, 0, 4; -L_0x12ec0b0 .concat8 [ 1 1 0 0], L_0x12eb170, L_0x12ebda0; -L_0x12ec1f0 .part L_0x12ea290, 4, 4; -L_0x12ec350 .part L_0x12ec0b0, 0, 1; -L_0x12ec500 .part L_0x12ec0b0, 1, 1; -S_0x1162670 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11624b0; +L_0x2ddb3a0/d .functor OR 1, L_0x2ddb460, L_0x2ddb610, C4<0>, C4<0>; +L_0x2ddb3a0 .delay 1 (30000,30000,30000) L_0x2ddb3a0/d; +v0x2c39170_0 .net *"_s10", 0 0, L_0x2ddb460; 1 drivers +v0x2c39250_0 .net *"_s12", 0 0, L_0x2ddb610; 1 drivers +v0x2c39330_0 .net "in", 7 0, L_0x2dd93a0; alias, 1 drivers +v0x2c39400_0 .net "ors", 1 0, L_0x2ddb1c0; 1 drivers +v0x2c394c0_0 .net "out", 0 0, L_0x2ddb3a0; alias, 1 drivers +L_0x2dda590 .part L_0x2dd93a0, 0, 4; +L_0x2ddb1c0 .concat8 [ 1 1 0 0], L_0x2dda280, L_0x2ddaeb0; +L_0x2ddb300 .part L_0x2dd93a0, 4, 4; +L_0x2ddb460 .part L_0x2ddb1c0, 0, 1; +L_0x2ddb610 .part L_0x2ddb1c0, 1, 1; +S_0x2c377e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c37620; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12ea930/d .functor OR 1, L_0x12ea9f0, L_0x12eab50, C4<0>, C4<0>; -L_0x12ea930 .delay 1 (30000,30000,30000) L_0x12ea930/d; -L_0x12ead80/d .functor OR 1, L_0x12eae90, L_0x12eaff0, C4<0>, C4<0>; -L_0x12ead80 .delay 1 (30000,30000,30000) L_0x12ead80/d; -L_0x12eb170/d .functor OR 1, L_0x12eb1e0, L_0x12eb390, C4<0>, C4<0>; -L_0x12eb170 .delay 1 (30000,30000,30000) L_0x12eb170/d; -v0x11628c0_0 .net *"_s0", 0 0, L_0x12ea930; 1 drivers -v0x11629c0_0 .net *"_s10", 0 0, L_0x12eae90; 1 drivers -v0x1162aa0_0 .net *"_s12", 0 0, L_0x12eaff0; 1 drivers -v0x1162b60_0 .net *"_s14", 0 0, L_0x12eb1e0; 1 drivers -v0x1162c40_0 .net *"_s16", 0 0, L_0x12eb390; 1 drivers -v0x1162d70_0 .net *"_s3", 0 0, L_0x12ea9f0; 1 drivers -v0x1162e50_0 .net *"_s5", 0 0, L_0x12eab50; 1 drivers -v0x1162f30_0 .net *"_s6", 0 0, L_0x12ead80; 1 drivers -v0x1163010_0 .net "in", 3 0, L_0x12eb480; 1 drivers -v0x1163180_0 .net "ors", 1 0, L_0x12eac90; 1 drivers -v0x1163260_0 .net "out", 0 0, L_0x12eb170; 1 drivers -L_0x12ea9f0 .part L_0x12eb480, 0, 1; -L_0x12eab50 .part L_0x12eb480, 1, 1; -L_0x12eac90 .concat8 [ 1 1 0 0], L_0x12ea930, L_0x12ead80; -L_0x12eae90 .part L_0x12eb480, 2, 1; -L_0x12eaff0 .part L_0x12eb480, 3, 1; -L_0x12eb1e0 .part L_0x12eac90, 0, 1; -L_0x12eb390 .part L_0x12eac90, 1, 1; -S_0x1163380 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11624b0; +L_0x2dd9a40/d .functor OR 1, L_0x2dd9b00, L_0x2dd9c60, C4<0>, C4<0>; +L_0x2dd9a40 .delay 1 (30000,30000,30000) L_0x2dd9a40/d; +L_0x2dd9e90/d .functor OR 1, L_0x2dd9fa0, L_0x2dda100, C4<0>, C4<0>; +L_0x2dd9e90 .delay 1 (30000,30000,30000) L_0x2dd9e90/d; +L_0x2dda280/d .functor OR 1, L_0x2dda2f0, L_0x2dda4a0, C4<0>, C4<0>; +L_0x2dda280 .delay 1 (30000,30000,30000) L_0x2dda280/d; +v0x2c37a30_0 .net *"_s0", 0 0, L_0x2dd9a40; 1 drivers +v0x2c37b30_0 .net *"_s10", 0 0, L_0x2dd9fa0; 1 drivers +v0x2c37c10_0 .net *"_s12", 0 0, L_0x2dda100; 1 drivers +v0x2c37cd0_0 .net *"_s14", 0 0, L_0x2dda2f0; 1 drivers +v0x2c37db0_0 .net *"_s16", 0 0, L_0x2dda4a0; 1 drivers +v0x2c37ee0_0 .net *"_s3", 0 0, L_0x2dd9b00; 1 drivers +v0x2c37fc0_0 .net *"_s5", 0 0, L_0x2dd9c60; 1 drivers +v0x2c380a0_0 .net *"_s6", 0 0, L_0x2dd9e90; 1 drivers +v0x2c38180_0 .net "in", 3 0, L_0x2dda590; 1 drivers +v0x2c382f0_0 .net "ors", 1 0, L_0x2dd9da0; 1 drivers +v0x2c383d0_0 .net "out", 0 0, L_0x2dda280; 1 drivers +L_0x2dd9b00 .part L_0x2dda590, 0, 1; +L_0x2dd9c60 .part L_0x2dda590, 1, 1; +L_0x2dd9da0 .concat8 [ 1 1 0 0], L_0x2dd9a40, L_0x2dd9e90; +L_0x2dd9fa0 .part L_0x2dda590, 2, 1; +L_0x2dda100 .part L_0x2dda590, 3, 1; +L_0x2dda2f0 .part L_0x2dd9da0, 0, 1; +L_0x2dda4a0 .part L_0x2dd9da0, 1, 1; +S_0x2c384f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c37620; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12eb5b0/d .functor OR 1, L_0x12eb620, L_0x12eb780, C4<0>, C4<0>; -L_0x12eb5b0 .delay 1 (30000,30000,30000) L_0x12eb5b0/d; -L_0x12eb9b0/d .functor OR 1, L_0x12ebac0, L_0x12ebc20, C4<0>, C4<0>; -L_0x12eb9b0 .delay 1 (30000,30000,30000) L_0x12eb9b0/d; -L_0x12ebda0/d .functor OR 1, L_0x12ebe10, L_0x12ebfc0, C4<0>, C4<0>; -L_0x12ebda0 .delay 1 (30000,30000,30000) L_0x12ebda0/d; -v0x1163540_0 .net *"_s0", 0 0, L_0x12eb5b0; 1 drivers -v0x1163640_0 .net *"_s10", 0 0, L_0x12ebac0; 1 drivers -v0x1163720_0 .net *"_s12", 0 0, L_0x12ebc20; 1 drivers -v0x11637e0_0 .net *"_s14", 0 0, L_0x12ebe10; 1 drivers -v0x11638c0_0 .net *"_s16", 0 0, L_0x12ebfc0; 1 drivers -v0x11639f0_0 .net *"_s3", 0 0, L_0x12eb620; 1 drivers -v0x1163ad0_0 .net *"_s5", 0 0, L_0x12eb780; 1 drivers -v0x1163bb0_0 .net *"_s6", 0 0, L_0x12eb9b0; 1 drivers -v0x1163c90_0 .net "in", 3 0, L_0x12ec1f0; 1 drivers -v0x1163e00_0 .net "ors", 1 0, L_0x12eb8c0; 1 drivers -v0x1163ee0_0 .net "out", 0 0, L_0x12ebda0; 1 drivers -L_0x12eb620 .part L_0x12ec1f0, 0, 1; -L_0x12eb780 .part L_0x12ec1f0, 1, 1; -L_0x12eb8c0 .concat8 [ 1 1 0 0], L_0x12eb5b0, L_0x12eb9b0; -L_0x12ebac0 .part L_0x12ec1f0, 2, 1; -L_0x12ebc20 .part L_0x12ec1f0, 3, 1; -L_0x12ebe10 .part L_0x12eb8c0, 0, 1; -L_0x12ebfc0 .part L_0x12eb8c0, 1, 1; -S_0x11647f0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1158170; +L_0x2dda6c0/d .functor OR 1, L_0x2dda730, L_0x2dda890, C4<0>, C4<0>; +L_0x2dda6c0 .delay 1 (30000,30000,30000) L_0x2dda6c0/d; +L_0x2ddaac0/d .functor OR 1, L_0x2ddabd0, L_0x2ddad30, C4<0>, C4<0>; +L_0x2ddaac0 .delay 1 (30000,30000,30000) L_0x2ddaac0/d; +L_0x2ddaeb0/d .functor OR 1, L_0x2ddaf20, L_0x2ddb0d0, C4<0>, C4<0>; +L_0x2ddaeb0 .delay 1 (30000,30000,30000) L_0x2ddaeb0/d; +v0x2c386b0_0 .net *"_s0", 0 0, L_0x2dda6c0; 1 drivers +v0x2c387b0_0 .net *"_s10", 0 0, L_0x2ddabd0; 1 drivers +v0x2c38890_0 .net *"_s12", 0 0, L_0x2ddad30; 1 drivers +v0x2c38950_0 .net *"_s14", 0 0, L_0x2ddaf20; 1 drivers +v0x2c38a30_0 .net *"_s16", 0 0, L_0x2ddb0d0; 1 drivers +v0x2c38b60_0 .net *"_s3", 0 0, L_0x2dda730; 1 drivers +v0x2c38c40_0 .net *"_s5", 0 0, L_0x2dda890; 1 drivers +v0x2c38d20_0 .net *"_s6", 0 0, L_0x2ddaac0; 1 drivers +v0x2c38e00_0 .net "in", 3 0, L_0x2ddb300; 1 drivers +v0x2c38f70_0 .net "ors", 1 0, L_0x2dda9d0; 1 drivers +v0x2c39050_0 .net "out", 0 0, L_0x2ddaeb0; 1 drivers +L_0x2dda730 .part L_0x2ddb300, 0, 1; +L_0x2dda890 .part L_0x2ddb300, 1, 1; +L_0x2dda9d0 .concat8 [ 1 1 0 0], L_0x2dda6c0, L_0x2ddaac0; +L_0x2ddabd0 .part L_0x2ddb300, 2, 1; +L_0x2ddad30 .part L_0x2ddb300, 3, 1; +L_0x2ddaf20 .part L_0x2dda9d0, 0, 1; +L_0x2ddb0d0 .part L_0x2dda9d0, 1, 1; +S_0x2c39960 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c2d2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -12854,80 +13600,80 @@ S_0x11647f0 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1158170; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12e7b40/d .functor XNOR 1, L_0x12f0130, L_0x12e6710, C4<0>, C4<0>; -L_0x12e7b40 .delay 1 (20000,20000,20000) L_0x12e7b40/d; -L_0x12e7db0/d .functor AND 1, L_0x12f0130, L_0x12e6a30, C4<1>, C4<1>; -L_0x12e7db0 .delay 1 (30000,30000,30000) L_0x12e7db0/d; -L_0x12e7e20/d .functor AND 1, L_0x12e7b40, L_0x12e67b0, C4<1>, C4<1>; -L_0x12e7e20 .delay 1 (30000,30000,30000) L_0x12e7e20/d; -L_0x12e7f80/d .functor OR 1, L_0x12e7e20, L_0x12e7db0, C4<0>, C4<0>; -L_0x12e7f80 .delay 1 (30000,30000,30000) L_0x12e7f80/d; -v0x1164aa0_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers -v0x1164b90_0 .net "a_", 0 0, L_0x12dcbb0; alias, 1 drivers -v0x1164c50_0 .net "b", 0 0, L_0x12e6710; alias, 1 drivers -v0x1164d40_0 .net "b_", 0 0, L_0x12e6a30; alias, 1 drivers -v0x1164de0_0 .net "carryin", 0 0, L_0x12e67b0; alias, 1 drivers -v0x1164f20_0 .net "eq", 0 0, L_0x12e7b40; 1 drivers -v0x1164fe0_0 .net "lt", 0 0, L_0x12e7db0; 1 drivers -v0x11650a0_0 .net "out", 0 0, L_0x12e7f80; 1 drivers -v0x1165160_0 .net "w0", 0 0, L_0x12e7e20; 1 drivers -S_0x11653b0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1158170; +L_0x2dd6150/d .functor XNOR 1, L_0x2ddf240, L_0x2dd4c10, C4<0>, C4<0>; +L_0x2dd6150 .delay 1 (20000,20000,20000) L_0x2dd6150/d; +L_0x2dd62d0/d .functor AND 1, L_0x2ddf240, L_0x2dd4ee0, C4<1>, C4<1>; +L_0x2dd62d0 .delay 1 (30000,30000,30000) L_0x2dd62d0/d; +L_0x2dd6430/d .functor AND 1, L_0x2dd6150, L_0x2dd4cb0, C4<1>, C4<1>; +L_0x2dd6430 .delay 1 (30000,30000,30000) L_0x2dd6430/d; +L_0x2dd6540/d .functor OR 1, L_0x2dd6430, L_0x2dd62d0, C4<0>, C4<0>; +L_0x2dd6540 .delay 1 (30000,30000,30000) L_0x2dd6540/d; +v0x2c39c10_0 .net "a", 0 0, L_0x2ddf240; alias, 1 drivers +v0x2c39d00_0 .net "a_", 0 0, L_0x2dca580; alias, 1 drivers +v0x2c39dc0_0 .net "b", 0 0, L_0x2dd4c10; alias, 1 drivers +v0x2c39eb0_0 .net "b_", 0 0, L_0x2dd4ee0; alias, 1 drivers +v0x2c39f50_0 .net "carryin", 0 0, L_0x2dd4cb0; alias, 1 drivers +v0x2c3a090_0 .net "eq", 0 0, L_0x2dd6150; 1 drivers +v0x2c3a150_0 .net "lt", 0 0, L_0x2dd62d0; 1 drivers +v0x2c3a210_0 .net "out", 0 0, L_0x2dd6540; 1 drivers +v0x2c3a2d0_0 .net "w0", 0 0, L_0x2dd6430; 1 drivers +S_0x2c3a520 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c2d2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12e7920/d .functor OR 1, L_0x12e7420, L_0x1166610, C4<0>, C4<0>; -L_0x12e7920 .delay 1 (30000,30000,30000) L_0x12e7920/d; -v0x11661a0_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers -v0x11662f0_0 .net "b", 0 0, L_0x12e6a30; alias, 1 drivers -v0x11663b0_0 .net "c1", 0 0, L_0x12e7420; 1 drivers -v0x1166450_0 .net "c2", 0 0, L_0x1166610; 1 drivers -v0x1166520_0 .net "carryin", 0 0, L_0x12e67b0; alias, 1 drivers -v0x11666a0_0 .net "carryout", 0 0, L_0x12e7920; 1 drivers -v0x1166740_0 .net "s1", 0 0, L_0x12e7360; 1 drivers -v0x11667e0_0 .net "sum", 0 0, L_0x12e7580; 1 drivers -S_0x1165600 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11653b0; +L_0x2dd5d30/d .functor OR 1, L_0x2dd5880, L_0x2c3b780, C4<0>, C4<0>; +L_0x2dd5d30 .delay 1 (30000,30000,30000) L_0x2dd5d30/d; +v0x2c3b310_0 .net "a", 0 0, L_0x2ddf240; alias, 1 drivers +v0x2c3b460_0 .net "b", 0 0, L_0x2dd4ee0; alias, 1 drivers +v0x2c3b520_0 .net "c1", 0 0, L_0x2dd5880; 1 drivers +v0x2c3b5c0_0 .net "c2", 0 0, L_0x2c3b780; 1 drivers +v0x2c3b690_0 .net "carryin", 0 0, L_0x2dd4cb0; alias, 1 drivers +v0x2c3b810_0 .net "carryout", 0 0, L_0x2dd5d30; 1 drivers +v0x2c3b8b0_0 .net "s1", 0 0, L_0x2dd57c0; 1 drivers +v0x2c3b950_0 .net "sum", 0 0, L_0x2dd59e0; 1 drivers +S_0x2c3a770 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c3a520; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12e7360/d .functor XOR 1, L_0x12f0130, L_0x12e6a30, C4<0>, C4<0>; -L_0x12e7360 .delay 1 (30000,30000,30000) L_0x12e7360/d; -L_0x12e7420/d .functor AND 1, L_0x12f0130, L_0x12e6a30, C4<1>, C4<1>; -L_0x12e7420 .delay 1 (30000,30000,30000) L_0x12e7420/d; -v0x1165860_0 .net "a", 0 0, L_0x12f0130; alias, 1 drivers -v0x1165920_0 .net "b", 0 0, L_0x12e6a30; alias, 1 drivers -v0x11659e0_0 .net "carryout", 0 0, L_0x12e7420; alias, 1 drivers -v0x1165a80_0 .net "sum", 0 0, L_0x12e7360; alias, 1 drivers -S_0x1165bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11653b0; +L_0x2dd57c0/d .functor XOR 1, L_0x2ddf240, L_0x2dd4ee0, C4<0>, C4<0>; +L_0x2dd57c0 .delay 1 (30000,30000,30000) L_0x2dd57c0/d; +L_0x2dd5880/d .functor AND 1, L_0x2ddf240, L_0x2dd4ee0, C4<1>, C4<1>; +L_0x2dd5880 .delay 1 (30000,30000,30000) L_0x2dd5880/d; +v0x2c3a9d0_0 .net "a", 0 0, L_0x2ddf240; alias, 1 drivers +v0x2c3aa90_0 .net "b", 0 0, L_0x2dd4ee0; alias, 1 drivers +v0x2c3ab50_0 .net "carryout", 0 0, L_0x2dd5880; alias, 1 drivers +v0x2c3abf0_0 .net "sum", 0 0, L_0x2dd57c0; alias, 1 drivers +S_0x2c3ad20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c3a520; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12e7580/d .functor XOR 1, L_0x12e7360, L_0x12e67b0, C4<0>, C4<0>; -L_0x12e7580 .delay 1 (30000,30000,30000) L_0x12e7580/d; -L_0x1166610/d .functor AND 1, L_0x12e7360, L_0x12e67b0, C4<1>, C4<1>; -L_0x1166610 .delay 1 (30000,30000,30000) L_0x1166610/d; -v0x1165e10_0 .net "a", 0 0, L_0x12e7360; alias, 1 drivers -v0x1165ee0_0 .net "b", 0 0, L_0x12e67b0; alias, 1 drivers -v0x1165f80_0 .net "carryout", 0 0, L_0x1166610; alias, 1 drivers -v0x1166050_0 .net "sum", 0 0, L_0x12e7580; alias, 1 drivers -S_0x1167c00 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1157ea0; - .timescale -9 -12; -L_0x2b0ab3d069f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06a40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12f01d0/d .functor OR 1, L_0x2b0ab3d069f8, L_0x2b0ab3d06a40, C4<0>, C4<0>; -L_0x12f01d0 .delay 1 (30000,30000,30000) L_0x12f01d0/d; -v0x1167df0_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d069f8; 1 drivers -v0x1167ed0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06a40; 1 drivers -S_0x1167fb0 .scope generate, "alu_slices[24]" "alu_slices[24]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11681c0 .param/l "i" 0 3 41, +C4<011000>; -S_0x1168280 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1167fb0; +L_0x2dd59e0/d .functor XOR 1, L_0x2dd57c0, L_0x2dd4cb0, C4<0>, C4<0>; +L_0x2dd59e0 .delay 1 (30000,30000,30000) L_0x2dd59e0/d; +L_0x2c3b780/d .functor AND 1, L_0x2dd57c0, L_0x2dd4cb0, C4<1>, C4<1>; +L_0x2c3b780 .delay 1 (30000,30000,30000) L_0x2c3b780/d; +v0x2c3af80_0 .net "a", 0 0, L_0x2dd57c0; alias, 1 drivers +v0x2c3b050_0 .net "b", 0 0, L_0x2dd4cb0; alias, 1 drivers +v0x2c3b0f0_0 .net "carryout", 0 0, L_0x2c3b780; alias, 1 drivers +v0x2c3b1c0_0 .net "sum", 0 0, L_0x2dd59e0; alias, 1 drivers +S_0x2c3d9e0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c2d010; + .timescale -9 -12; +L_0x2ac6110bbd78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbdc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dd5340/d .functor OR 1, L_0x2ac6110bbd78, L_0x2ac6110bbdc0, C4<0>, C4<0>; +L_0x2dd5340 .delay 1 (30000,30000,30000) L_0x2dd5340/d; +v0x2c3dbd0_0 .net/2u *"_s0", 0 0, L_0x2ac6110bbd78; 1 drivers +v0x2c3dcb0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bbdc0; 1 drivers +S_0x2c3dd90 .scope generate, "alu_slices[24]" "alu_slices[24]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c3dfa0 .param/l "i" 0 3 39, +C4<011000>; +S_0x2c3e060 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c3dd90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -12936,445 +13682,476 @@ S_0x1168280 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1167fb0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12f0530/d .functor NOT 1, L_0x12f9d60, C4<0>, C4<0>, C4<0>; -L_0x12f0530 .delay 1 (10000,10000,10000) L_0x12f0530/d; -L_0x12f0640/d .functor NOT 1, L_0x12f9ec0, C4<0>, C4<0>, C4<0>; -L_0x12f0640 .delay 1 (10000,10000,10000) L_0x12f0640/d; -L_0x12f1690/d .functor XOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; -L_0x12f1690 .delay 1 (30000,30000,30000) L_0x12f1690/d; -L_0x2b0ab3d06a88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06ad0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12f1d40/d .functor OR 1, L_0x2b0ab3d06a88, L_0x2b0ab3d06ad0, C4<0>, C4<0>; -L_0x12f1d40 .delay 1 (30000,30000,30000) L_0x12f1d40/d; -L_0x12f1f40/d .functor AND 1, L_0x12f9d60, L_0x12f9ec0, C4<1>, C4<1>; -L_0x12f1f40 .delay 1 (30000,30000,30000) L_0x12f1f40/d; -L_0x12f2000/d .functor NAND 1, L_0x12f9d60, L_0x12f9ec0, C4<1>, C4<1>; -L_0x12f2000 .delay 1 (20000,20000,20000) L_0x12f2000/d; -L_0x12f2160/d .functor XOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; -L_0x12f2160 .delay 1 (20000,20000,20000) L_0x12f2160/d; -L_0x12f2610/d .functor OR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; -L_0x12f2610 .delay 1 (30000,30000,30000) L_0x12f2610/d; -L_0x12f9c60/d .functor NOT 1, L_0x12f5ea0, C4<0>, C4<0>, C4<0>; -L_0x12f9c60 .delay 1 (10000,10000,10000) L_0x12f9c60/d; -v0x11769b0_0 .net "A", 0 0, L_0x12f9d60; 1 drivers -v0x1176a70_0 .net "A_", 0 0, L_0x12f0530; 1 drivers -v0x1176b30_0 .net "B", 0 0, L_0x12f9ec0; 1 drivers -v0x1176c00_0 .net "B_", 0 0, L_0x12f0640; 1 drivers -v0x1176ca0_0 .net *"_s12", 0 0, L_0x12f1d40; 1 drivers -v0x1176d90_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06a88; 1 drivers -v0x1176e50_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06ad0; 1 drivers -v0x1176f30_0 .net *"_s18", 0 0, L_0x12f1f40; 1 drivers -v0x1177010_0 .net *"_s20", 0 0, L_0x12f2000; 1 drivers -v0x1177180_0 .net *"_s22", 0 0, L_0x12f2160; 1 drivers -v0x1177260_0 .net *"_s24", 0 0, L_0x12f2610; 1 drivers -o0x2b0ab3cde248 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1177340_0 name=_s30 -o0x2b0ab3cde278 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1177420_0 name=_s32 -v0x1177500_0 .net *"_s8", 0 0, L_0x12f1690; 1 drivers -v0x11775e0_0 .net "carryin", 0 0, L_0x12f0290; 1 drivers -v0x1177680_0 .net "carryout", 0 0, L_0x12f9900; 1 drivers -v0x1177720_0 .net "carryouts", 7 0, L_0x13557a0; 1 drivers -v0x11778d0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1177970_0 .net "result", 0 0, L_0x12f5ea0; 1 drivers -v0x1177a60_0 .net "results", 7 0, L_0x12f23e0; 1 drivers -v0x1177b70_0 .net "zero", 0 0, L_0x12f9c60; 1 drivers -LS_0x12f23e0_0_0 .concat8 [ 1 1 1 1], L_0x12f0b60, L_0x12f1190, L_0x12f1690, L_0x12f1d40; -LS_0x12f23e0_0_4 .concat8 [ 1 1 1 1], L_0x12f1f40, L_0x12f2000, L_0x12f2160, L_0x12f2610; -L_0x12f23e0 .concat8 [ 4 4 0 0], LS_0x12f23e0_0_0, LS_0x12f23e0_0_4; -LS_0x13557a0_0_0 .concat [ 1 1 1 1], L_0x12f0e10, L_0x12f1530, o0x2b0ab3cde248, L_0x12f1b90; -LS_0x13557a0_0_4 .concat [ 4 0 0 0], o0x2b0ab3cde278; -L_0x13557a0 .concat [ 4 4 0 0], LS_0x13557a0_0_0, LS_0x13557a0_0_4; -S_0x1168500 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1168280; +L_0x2ddf5f0/d .functor NOT 1, L_0x2de9a80, C4<0>, C4<0>, C4<0>; +L_0x2ddf5f0 .delay 1 (10000,10000,10000) L_0x2ddf5f0/d; +L_0x2ddf700/d .functor NOT 1, L_0x2de9be0, C4<0>, C4<0>, C4<0>; +L_0x2ddf700 .delay 1 (10000,10000,10000) L_0x2ddf700/d; +L_0x2de0750/d .functor XOR 1, L_0x2de9a80, L_0x2de9be0, C4<0>, C4<0>; +L_0x2de0750 .delay 1 (30000,30000,30000) L_0x2de0750/d; +L_0x2ac6110bbe08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbe50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2de0810/d .functor OR 1, L_0x2ac6110bbe08, L_0x2ac6110bbe50, C4<0>, C4<0>; +L_0x2de0810 .delay 1 (30000,30000,30000) L_0x2de0810/d; +L_0x2ac6110bbe98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbee0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2de0fb0/d .functor OR 1, L_0x2ac6110bbe98, L_0x2ac6110bbee0, C4<0>, C4<0>; +L_0x2de0fb0 .delay 1 (30000,30000,30000) L_0x2de0fb0/d; +L_0x2de11b0/d .functor AND 1, L_0x2de9a80, L_0x2de9be0, C4<1>, C4<1>; +L_0x2de11b0 .delay 1 (30000,30000,30000) L_0x2de11b0/d; +L_0x2ac6110bbf28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bbf70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2de1270/d .functor OR 1, L_0x2ac6110bbf28, L_0x2ac6110bbf70, C4<0>, C4<0>; +L_0x2de1270 .delay 1 (30000,30000,30000) L_0x2de1270/d; +L_0x2de1470/d .functor NAND 1, L_0x2de9a80, L_0x2de9be0, C4<1>, C4<1>; +L_0x2de1470 .delay 1 (20000,20000,20000) L_0x2de1470/d; +L_0x2ac6110bbfb8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc000 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2de1580/d .functor OR 1, L_0x2ac6110bbfb8, L_0x2ac6110bc000, C4<0>, C4<0>; +L_0x2de1580 .delay 1 (30000,30000,30000) L_0x2de1580/d; +L_0x2de1730/d .functor NOR 1, L_0x2de9a80, L_0x2de9be0, C4<0>, C4<0>; +L_0x2de1730 .delay 1 (20000,20000,20000) L_0x2de1730/d; +L_0x2ac6110bc048 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc090 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ddfbb0/d .functor OR 1, L_0x2ac6110bc048, L_0x2ac6110bc090, C4<0>, C4<0>; +L_0x2ddfbb0 .delay 1 (30000,30000,30000) L_0x2ddfbb0/d; +L_0x2de1d90/d .functor OR 1, L_0x2de9a80, L_0x2de9be0, C4<0>, C4<0>; +L_0x2de1d90 .delay 1 (30000,30000,30000) L_0x2de1d90/d; +L_0x2ac6110bc0d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc120 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2de2280/d .functor OR 1, L_0x2ac6110bc0d8, L_0x2ac6110bc120, C4<0>, C4<0>; +L_0x2de2280 .delay 1 (30000,30000,30000) L_0x2de2280/d; +L_0x2de9980/d .functor NOT 1, L_0x2de5be0, C4<0>, C4<0>, C4<0>; +L_0x2de9980 .delay 1 (10000,10000,10000) L_0x2de9980/d; +v0x2c4c790_0 .net "A", 0 0, L_0x2de9a80; 1 drivers +v0x2c4c850_0 .net "A_", 0 0, L_0x2ddf5f0; 1 drivers +v0x2c4c910_0 .net "B", 0 0, L_0x2de9be0; 1 drivers +v0x2c4c9e0_0 .net "B_", 0 0, L_0x2ddf700; 1 drivers +v0x2c4ca80_0 .net *"_s11", 0 0, L_0x2de0810; 1 drivers +v0x2c4cb70_0 .net/2s *"_s13", 0 0, L_0x2ac6110bbe08; 1 drivers +v0x2c4cc30_0 .net/2s *"_s15", 0 0, L_0x2ac6110bbe50; 1 drivers +v0x2c4cd10_0 .net *"_s19", 0 0, L_0x2de0fb0; 1 drivers +v0x2c4cdf0_0 .net/2s *"_s21", 0 0, L_0x2ac6110bbe98; 1 drivers +v0x2c4cf60_0 .net/2s *"_s23", 0 0, L_0x2ac6110bbee0; 1 drivers +v0x2c4d040_0 .net *"_s25", 0 0, L_0x2de11b0; 1 drivers +v0x2c4d120_0 .net *"_s28", 0 0, L_0x2de1270; 1 drivers +v0x2c4d200_0 .net/2s *"_s30", 0 0, L_0x2ac6110bbf28; 1 drivers +v0x2c4d2e0_0 .net/2s *"_s32", 0 0, L_0x2ac6110bbf70; 1 drivers +v0x2c4d3c0_0 .net *"_s34", 0 0, L_0x2de1470; 1 drivers +v0x2c4d4a0_0 .net *"_s37", 0 0, L_0x2de1580; 1 drivers +v0x2c4d580_0 .net/2s *"_s39", 0 0, L_0x2ac6110bbfb8; 1 drivers +v0x2c4d730_0 .net/2s *"_s41", 0 0, L_0x2ac6110bc000; 1 drivers +v0x2c4d7d0_0 .net *"_s43", 0 0, L_0x2de1730; 1 drivers +v0x2c4d8b0_0 .net *"_s46", 0 0, L_0x2ddfbb0; 1 drivers +v0x2c4d990_0 .net/2s *"_s48", 0 0, L_0x2ac6110bc048; 1 drivers +v0x2c4da70_0 .net/2s *"_s50", 0 0, L_0x2ac6110bc090; 1 drivers +v0x2c4db50_0 .net *"_s52", 0 0, L_0x2de1d90; 1 drivers +v0x2c4dc30_0 .net *"_s56", 0 0, L_0x2de2280; 1 drivers +v0x2c4dd10_0 .net/2s *"_s59", 0 0, L_0x2ac6110bc0d8; 1 drivers +v0x2c4ddf0_0 .net/2s *"_s61", 0 0, L_0x2ac6110bc120; 1 drivers +v0x2c4ded0_0 .net *"_s8", 0 0, L_0x2de0750; 1 drivers +v0x2c4dfb0_0 .net "carryin", 0 0, L_0x2ddf3a0; 1 drivers +v0x2c4e050_0 .net "carryout", 0 0, L_0x2de9620; 1 drivers +v0x2c4e0f0_0 .net "carryouts", 7 0, L_0x2de1f10; 1 drivers +v0x2c4e200_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c4e2c0_0 .net "result", 0 0, L_0x2de5be0; 1 drivers +v0x2c4e3b0_0 .net "results", 7 0, L_0x2de1b60; 1 drivers +v0x2c4d690_0 .net "zero", 0 0, L_0x2de9980; 1 drivers +LS_0x2de1b60_0_0 .concat8 [ 1 1 1 1], L_0x2ddfc20, L_0x2de0250, L_0x2de0750, L_0x2de0fb0; +LS_0x2de1b60_0_4 .concat8 [ 1 1 1 1], L_0x2de11b0, L_0x2de1470, L_0x2de1730, L_0x2de1d90; +L_0x2de1b60 .concat8 [ 4 4 0 0], LS_0x2de1b60_0_0, LS_0x2de1b60_0_4; +LS_0x2de1f10_0_0 .concat8 [ 1 1 1 1], L_0x2ddfed0, L_0x2de05f0, L_0x2de0810, L_0x2de0e00; +LS_0x2de1f10_0_4 .concat8 [ 1 1 1 1], L_0x2de1270, L_0x2de1580, L_0x2ddfbb0, L_0x2de2280; +L_0x2de1f10 .concat8 [ 4 4 0 0], LS_0x2de1f10_0_0, LS_0x2de1f10_0_4; +S_0x2c3e2e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c3e060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12f0e10/d .functor OR 1, L_0x12f08f0, L_0x12f0cb0, C4<0>, C4<0>; -L_0x12f0e10 .delay 1 (30000,30000,30000) L_0x12f0e10/d; -v0x1169330_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers -v0x11693f0_0 .net "b", 0 0, L_0x12f9ec0; alias, 1 drivers -v0x11694c0_0 .net "c1", 0 0, L_0x12f08f0; 1 drivers -v0x11695c0_0 .net "c2", 0 0, L_0x12f0cb0; 1 drivers -v0x1169690_0 .net "carryin", 0 0, L_0x12f0290; alias, 1 drivers -v0x1169780_0 .net "carryout", 0 0, L_0x12f0e10; 1 drivers -v0x1169820_0 .net "s1", 0 0, L_0x12f0830; 1 drivers -v0x1169910_0 .net "sum", 0 0, L_0x12f0b60; 1 drivers -S_0x1168770 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1168500; +L_0x2ddfed0/d .functor OR 1, L_0x2ddf9b0, L_0x2ddfd70, C4<0>, C4<0>; +L_0x2ddfed0 .delay 1 (30000,30000,30000) L_0x2ddfed0/d; +v0x2c3f110_0 .net "a", 0 0, L_0x2de9a80; alias, 1 drivers +v0x2c3f1d0_0 .net "b", 0 0, L_0x2de9be0; alias, 1 drivers +v0x2c3f2a0_0 .net "c1", 0 0, L_0x2ddf9b0; 1 drivers +v0x2c3f3a0_0 .net "c2", 0 0, L_0x2ddfd70; 1 drivers +v0x2c3f470_0 .net "carryin", 0 0, L_0x2ddf3a0; alias, 1 drivers +v0x2c3f560_0 .net "carryout", 0 0, L_0x2ddfed0; 1 drivers +v0x2c3f600_0 .net "s1", 0 0, L_0x2ddf8f0; 1 drivers +v0x2c3f6f0_0 .net "sum", 0 0, L_0x2ddfc20; 1 drivers +S_0x2c3e550 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c3e2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12f0830/d .functor XOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; -L_0x12f0830 .delay 1 (30000,30000,30000) L_0x12f0830/d; -L_0x12f08f0/d .functor AND 1, L_0x12f9d60, L_0x12f9ec0, C4<1>, C4<1>; -L_0x12f08f0 .delay 1 (30000,30000,30000) L_0x12f08f0/d; -v0x11689d0_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers -v0x1168ab0_0 .net "b", 0 0, L_0x12f9ec0; alias, 1 drivers -v0x1168b70_0 .net "carryout", 0 0, L_0x12f08f0; alias, 1 drivers -v0x1168c10_0 .net "sum", 0 0, L_0x12f0830; alias, 1 drivers -S_0x1168d50 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1168500; +L_0x2ddf8f0/d .functor XOR 1, L_0x2de9a80, L_0x2de9be0, C4<0>, C4<0>; +L_0x2ddf8f0 .delay 1 (30000,30000,30000) L_0x2ddf8f0/d; +L_0x2ddf9b0/d .functor AND 1, L_0x2de9a80, L_0x2de9be0, C4<1>, C4<1>; +L_0x2ddf9b0 .delay 1 (30000,30000,30000) L_0x2ddf9b0/d; +v0x2c3e7b0_0 .net "a", 0 0, L_0x2de9a80; alias, 1 drivers +v0x2c3e890_0 .net "b", 0 0, L_0x2de9be0; alias, 1 drivers +v0x2c3e950_0 .net "carryout", 0 0, L_0x2ddf9b0; alias, 1 drivers +v0x2c3e9f0_0 .net "sum", 0 0, L_0x2ddf8f0; alias, 1 drivers +S_0x2c3eb30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c3e2e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12f0b60/d .functor XOR 1, L_0x12f0830, L_0x12f0290, C4<0>, C4<0>; -L_0x12f0b60 .delay 1 (30000,30000,30000) L_0x12f0b60/d; -L_0x12f0cb0/d .functor AND 1, L_0x12f0830, L_0x12f0290, C4<1>, C4<1>; -L_0x12f0cb0 .delay 1 (30000,30000,30000) L_0x12f0cb0/d; -v0x1168fb0_0 .net "a", 0 0, L_0x12f0830; alias, 1 drivers -v0x1169050_0 .net "b", 0 0, L_0x12f0290; alias, 1 drivers -v0x11690f0_0 .net "carryout", 0 0, L_0x12f0cb0; alias, 1 drivers -v0x11691c0_0 .net "sum", 0 0, L_0x12f0b60; alias, 1 drivers -S_0x11699e0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1168280; +L_0x2ddfc20/d .functor XOR 1, L_0x2ddf8f0, L_0x2ddf3a0, C4<0>, C4<0>; +L_0x2ddfc20 .delay 1 (30000,30000,30000) L_0x2ddfc20/d; +L_0x2ddfd70/d .functor AND 1, L_0x2ddf8f0, L_0x2ddf3a0, C4<1>, C4<1>; +L_0x2ddfd70 .delay 1 (30000,30000,30000) L_0x2ddfd70/d; +v0x2c3ed90_0 .net "a", 0 0, L_0x2ddf8f0; alias, 1 drivers +v0x2c3ee30_0 .net "b", 0 0, L_0x2ddf3a0; alias, 1 drivers +v0x2c3eed0_0 .net "carryout", 0 0, L_0x2ddfd70; alias, 1 drivers +v0x2c3efa0_0 .net "sum", 0 0, L_0x2ddfc20; alias, 1 drivers +S_0x2c3f7c0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c3e060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x116edd0_0 .net "ands", 7 0, L_0x12f7900; 1 drivers -v0x116eee0_0 .net "in", 7 0, L_0x13557a0; alias, 1 drivers -v0x116efa0_0 .net "out", 0 0, L_0x12f9900; alias, 1 drivers -v0x116f070_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1169c00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11699e0; +v0x2c44bb0_0 .net "ands", 7 0, L_0x2de7620; 1 drivers +v0x2c44cc0_0 .net "in", 7 0, L_0x2de1f10; alias, 1 drivers +v0x2c44d80_0 .net "out", 0 0, L_0x2de9620; alias, 1 drivers +v0x2c44e50_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c3f9e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c3f7c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x116c330_0 .net "A", 7 0, L_0x13557a0; alias, 1 drivers -v0x116c430_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x116c4f0_0 .net *"_s0", 0 0, L_0x12f6140; 1 drivers -v0x116c5b0_0 .net *"_s12", 0 0, L_0x12f6ab0; 1 drivers -v0x116c690_0 .net *"_s16", 0 0, L_0x12f6e10; 1 drivers -v0x116c7c0_0 .net *"_s20", 0 0, L_0x12f7180; 1 drivers -v0x116c8a0_0 .net *"_s24", 0 0, L_0x12f7570; 1 drivers -v0x116c980_0 .net *"_s28", 0 0, L_0x12f7500; 1 drivers -v0x116ca60_0 .net *"_s4", 0 0, L_0x12f6450; 1 drivers -v0x116cbd0_0 .net *"_s8", 0 0, L_0x12f67a0; 1 drivers -v0x116ccb0_0 .net "out", 7 0, L_0x12f7900; alias, 1 drivers -L_0x12f6200 .part L_0x13557a0, 0, 1; -L_0x12f6360 .part v0x12010b0_0, 0, 1; -L_0x12f6510 .part L_0x13557a0, 1, 1; -L_0x12f6700 .part v0x12010b0_0, 1, 1; -L_0x12f6860 .part L_0x13557a0, 2, 1; -L_0x12f69c0 .part v0x12010b0_0, 2, 1; -L_0x12f6b70 .part L_0x13557a0, 3, 1; -L_0x12f6cd0 .part v0x12010b0_0, 3, 1; -L_0x12f6ed0 .part L_0x13557a0, 4, 1; -L_0x12f7030 .part v0x12010b0_0, 4, 1; -L_0x12f71f0 .part L_0x13557a0, 5, 1; -L_0x12f7460 .part v0x12010b0_0, 5, 1; -L_0x12f7630 .part L_0x13557a0, 6, 1; -L_0x12f7790 .part v0x12010b0_0, 6, 1; -LS_0x12f7900_0_0 .concat8 [ 1 1 1 1], L_0x12f6140, L_0x12f6450, L_0x12f67a0, L_0x12f6ab0; -LS_0x12f7900_0_4 .concat8 [ 1 1 1 1], L_0x12f6e10, L_0x12f7180, L_0x12f7570, L_0x12f7500; -L_0x12f7900 .concat8 [ 4 4 0 0], LS_0x12f7900_0_0, LS_0x12f7900_0_4; -L_0x12f7cc0 .part L_0x13557a0, 7, 1; -L_0x12f7eb0 .part v0x12010b0_0, 7, 1; -S_0x1169e60 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116a070 .param/l "i" 0 4 54, +C4<00>; -L_0x12f6140/d .functor AND 1, L_0x12f6200, L_0x12f6360, C4<1>, C4<1>; -L_0x12f6140 .delay 1 (30000,30000,30000) L_0x12f6140/d; -v0x116a150_0 .net *"_s0", 0 0, L_0x12f6200; 1 drivers -v0x116a230_0 .net *"_s1", 0 0, L_0x12f6360; 1 drivers -S_0x116a310 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116a520 .param/l "i" 0 4 54, +C4<01>; -L_0x12f6450/d .functor AND 1, L_0x12f6510, L_0x12f6700, C4<1>, C4<1>; -L_0x12f6450 .delay 1 (30000,30000,30000) L_0x12f6450/d; -v0x116a5e0_0 .net *"_s0", 0 0, L_0x12f6510; 1 drivers -v0x116a6c0_0 .net *"_s1", 0 0, L_0x12f6700; 1 drivers -S_0x116a7a0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116a9b0 .param/l "i" 0 4 54, +C4<010>; -L_0x12f67a0/d .functor AND 1, L_0x12f6860, L_0x12f69c0, C4<1>, C4<1>; -L_0x12f67a0 .delay 1 (30000,30000,30000) L_0x12f67a0/d; -v0x116aa50_0 .net *"_s0", 0 0, L_0x12f6860; 1 drivers -v0x116ab30_0 .net *"_s1", 0 0, L_0x12f69c0; 1 drivers -S_0x116ac10 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116ae20 .param/l "i" 0 4 54, +C4<011>; -L_0x12f6ab0/d .functor AND 1, L_0x12f6b70, L_0x12f6cd0, C4<1>, C4<1>; -L_0x12f6ab0 .delay 1 (30000,30000,30000) L_0x12f6ab0/d; -v0x116aee0_0 .net *"_s0", 0 0, L_0x12f6b70; 1 drivers -v0x116afc0_0 .net *"_s1", 0 0, L_0x12f6cd0; 1 drivers -S_0x116b0a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116b300 .param/l "i" 0 4 54, +C4<0100>; -L_0x12f6e10/d .functor AND 1, L_0x12f6ed0, L_0x12f7030, C4<1>, C4<1>; -L_0x12f6e10 .delay 1 (30000,30000,30000) L_0x12f6e10/d; -v0x116b3c0_0 .net *"_s0", 0 0, L_0x12f6ed0; 1 drivers -v0x116b4a0_0 .net *"_s1", 0 0, L_0x12f7030; 1 drivers -S_0x116b580 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116b790 .param/l "i" 0 4 54, +C4<0101>; -L_0x12f7180/d .functor AND 1, L_0x12f71f0, L_0x12f7460, C4<1>, C4<1>; -L_0x12f7180 .delay 1 (30000,30000,30000) L_0x12f7180/d; -v0x116b850_0 .net *"_s0", 0 0, L_0x12f71f0; 1 drivers -v0x116b930_0 .net *"_s1", 0 0, L_0x12f7460; 1 drivers -S_0x116ba10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116bc20 .param/l "i" 0 4 54, +C4<0110>; -L_0x12f7570/d .functor AND 1, L_0x12f7630, L_0x12f7790, C4<1>, C4<1>; -L_0x12f7570 .delay 1 (30000,30000,30000) L_0x12f7570/d; -v0x116bce0_0 .net *"_s0", 0 0, L_0x12f7630; 1 drivers -v0x116bdc0_0 .net *"_s1", 0 0, L_0x12f7790; 1 drivers -S_0x116bea0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1169c00; - .timescale -9 -12; -P_0x116c090 .param/l "i" 0 4 54, +C4<0111>; -L_0x12f7500/d .functor AND 1, L_0x12f7cc0, L_0x12f7eb0, C4<1>, C4<1>; -L_0x12f7500 .delay 1 (30000,30000,30000) L_0x12f7500/d; -v0x116c170_0 .net *"_s0", 0 0, L_0x12f7cc0; 1 drivers -v0x116c250_0 .net *"_s1", 0 0, L_0x12f7eb0; 1 drivers -S_0x116ce10 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11699e0; +v0x2c42110_0 .net "A", 7 0, L_0x2de1f10; alias, 1 drivers +v0x2c42210_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c422d0_0 .net *"_s0", 0 0, L_0x2de5f40; 1 drivers +v0x2c42390_0 .net *"_s12", 0 0, L_0x2de68b0; 1 drivers +v0x2c42470_0 .net *"_s16", 0 0, L_0x2de6c10; 1 drivers +v0x2c425a0_0 .net *"_s20", 0 0, L_0x2de6fe0; 1 drivers +v0x2c42680_0 .net *"_s24", 0 0, L_0x2de7310; 1 drivers +v0x2c42760_0 .net *"_s28", 0 0, L_0x2de72a0; 1 drivers +v0x2c42840_0 .net *"_s4", 0 0, L_0x2de6290; 1 drivers +v0x2c429b0_0 .net *"_s8", 0 0, L_0x2de65a0; 1 drivers +v0x2c42a90_0 .net "out", 7 0, L_0x2de7620; alias, 1 drivers +L_0x2de6000 .part L_0x2de1f10, 0, 1; +L_0x2de61f0 .part v0x2cdd2e0_0, 0, 1; +L_0x2de6350 .part L_0x2de1f10, 1, 1; +L_0x2de64b0 .part v0x2cdd2e0_0, 1, 1; +L_0x2de6660 .part L_0x2de1f10, 2, 1; +L_0x2de67c0 .part v0x2cdd2e0_0, 2, 1; +L_0x2de6970 .part L_0x2de1f10, 3, 1; +L_0x2de6ad0 .part v0x2cdd2e0_0, 3, 1; +L_0x2de6cd0 .part L_0x2de1f10, 4, 1; +L_0x2de6f40 .part v0x2cdd2e0_0, 4, 1; +L_0x2de7050 .part L_0x2de1f10, 5, 1; +L_0x2de71b0 .part v0x2cdd2e0_0, 5, 1; +L_0x2de73d0 .part L_0x2de1f10, 6, 1; +L_0x2de7530 .part v0x2cdd2e0_0, 6, 1; +LS_0x2de7620_0_0 .concat8 [ 1 1 1 1], L_0x2de5f40, L_0x2de6290, L_0x2de65a0, L_0x2de68b0; +LS_0x2de7620_0_4 .concat8 [ 1 1 1 1], L_0x2de6c10, L_0x2de6fe0, L_0x2de7310, L_0x2de72a0; +L_0x2de7620 .concat8 [ 4 4 0 0], LS_0x2de7620_0_0, LS_0x2de7620_0_4; +L_0x2de79e0 .part L_0x2de1f10, 7, 1; +L_0x2de7bd0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c3fc40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c3fe50 .param/l "i" 0 4 54, +C4<00>; +L_0x2de5f40/d .functor AND 1, L_0x2de6000, L_0x2de61f0, C4<1>, C4<1>; +L_0x2de5f40 .delay 1 (30000,30000,30000) L_0x2de5f40/d; +v0x2c3ff30_0 .net *"_s0", 0 0, L_0x2de6000; 1 drivers +v0x2c40010_0 .net *"_s1", 0 0, L_0x2de61f0; 1 drivers +S_0x2c400f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c40300 .param/l "i" 0 4 54, +C4<01>; +L_0x2de6290/d .functor AND 1, L_0x2de6350, L_0x2de64b0, C4<1>, C4<1>; +L_0x2de6290 .delay 1 (30000,30000,30000) L_0x2de6290/d; +v0x2c403c0_0 .net *"_s0", 0 0, L_0x2de6350; 1 drivers +v0x2c404a0_0 .net *"_s1", 0 0, L_0x2de64b0; 1 drivers +S_0x2c40580 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c40790 .param/l "i" 0 4 54, +C4<010>; +L_0x2de65a0/d .functor AND 1, L_0x2de6660, L_0x2de67c0, C4<1>, C4<1>; +L_0x2de65a0 .delay 1 (30000,30000,30000) L_0x2de65a0/d; +v0x2c40830_0 .net *"_s0", 0 0, L_0x2de6660; 1 drivers +v0x2c40910_0 .net *"_s1", 0 0, L_0x2de67c0; 1 drivers +S_0x2c409f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c40c00 .param/l "i" 0 4 54, +C4<011>; +L_0x2de68b0/d .functor AND 1, L_0x2de6970, L_0x2de6ad0, C4<1>, C4<1>; +L_0x2de68b0 .delay 1 (30000,30000,30000) L_0x2de68b0/d; +v0x2c40cc0_0 .net *"_s0", 0 0, L_0x2de6970; 1 drivers +v0x2c40da0_0 .net *"_s1", 0 0, L_0x2de6ad0; 1 drivers +S_0x2c40e80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c410e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2de6c10/d .functor AND 1, L_0x2de6cd0, L_0x2de6f40, C4<1>, C4<1>; +L_0x2de6c10 .delay 1 (30000,30000,30000) L_0x2de6c10/d; +v0x2c411a0_0 .net *"_s0", 0 0, L_0x2de6cd0; 1 drivers +v0x2c41280_0 .net *"_s1", 0 0, L_0x2de6f40; 1 drivers +S_0x2c41360 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c41570 .param/l "i" 0 4 54, +C4<0101>; +L_0x2de6fe0/d .functor AND 1, L_0x2de7050, L_0x2de71b0, C4<1>, C4<1>; +L_0x2de6fe0 .delay 1 (30000,30000,30000) L_0x2de6fe0/d; +v0x2c41630_0 .net *"_s0", 0 0, L_0x2de7050; 1 drivers +v0x2c41710_0 .net *"_s1", 0 0, L_0x2de71b0; 1 drivers +S_0x2c417f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c41a00 .param/l "i" 0 4 54, +C4<0110>; +L_0x2de7310/d .functor AND 1, L_0x2de73d0, L_0x2de7530, C4<1>, C4<1>; +L_0x2de7310 .delay 1 (30000,30000,30000) L_0x2de7310/d; +v0x2c41ac0_0 .net *"_s0", 0 0, L_0x2de73d0; 1 drivers +v0x2c41ba0_0 .net *"_s1", 0 0, L_0x2de7530; 1 drivers +S_0x2c41c80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c3f9e0; + .timescale -9 -12; +P_0x2c41e90 .param/l "i" 0 4 54, +C4<0111>; +L_0x2de72a0/d .functor AND 1, L_0x2de79e0, L_0x2de7bd0, C4<1>, C4<1>; +L_0x2de72a0 .delay 1 (30000,30000,30000) L_0x2de72a0/d; +v0x2c41f50_0 .net *"_s0", 0 0, L_0x2de79e0; 1 drivers +v0x2c42030_0 .net *"_s1", 0 0, L_0x2de7bd0; 1 drivers +S_0x2c42bf0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c3f7c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12f9900/d .functor OR 1, L_0x12f99c0, L_0x12f9b70, C4<0>, C4<0>; -L_0x12f9900 .delay 1 (30000,30000,30000) L_0x12f9900/d; -v0x116e960_0 .net *"_s10", 0 0, L_0x12f99c0; 1 drivers -v0x116ea40_0 .net *"_s12", 0 0, L_0x12f9b70; 1 drivers -v0x116eb20_0 .net "in", 7 0, L_0x12f7900; alias, 1 drivers -v0x116ebf0_0 .net "ors", 1 0, L_0x12f9720; 1 drivers -v0x116ecb0_0 .net "out", 0 0, L_0x12f9900; alias, 1 drivers -L_0x12f8af0 .part L_0x12f7900, 0, 4; -L_0x12f9720 .concat8 [ 1 1 0 0], L_0x12f87e0, L_0x12f9410; -L_0x12f9860 .part L_0x12f7900, 4, 4; -L_0x12f99c0 .part L_0x12f9720, 0, 1; -L_0x12f9b70 .part L_0x12f9720, 1, 1; -S_0x116cfd0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x116ce10; +L_0x2de9620/d .functor OR 1, L_0x2de96e0, L_0x2de9890, C4<0>, C4<0>; +L_0x2de9620 .delay 1 (30000,30000,30000) L_0x2de9620/d; +v0x2c44740_0 .net *"_s10", 0 0, L_0x2de96e0; 1 drivers +v0x2c44820_0 .net *"_s12", 0 0, L_0x2de9890; 1 drivers +v0x2c44900_0 .net "in", 7 0, L_0x2de7620; alias, 1 drivers +v0x2c449d0_0 .net "ors", 1 0, L_0x2de9440; 1 drivers +v0x2c44a90_0 .net "out", 0 0, L_0x2de9620; alias, 1 drivers +L_0x2de8810 .part L_0x2de7620, 0, 4; +L_0x2de9440 .concat8 [ 1 1 0 0], L_0x2de8500, L_0x2de9130; +L_0x2de9580 .part L_0x2de7620, 4, 4; +L_0x2de96e0 .part L_0x2de9440, 0, 1; +L_0x2de9890 .part L_0x2de9440, 1, 1; +S_0x2c42db0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c42bf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12f7fa0/d .functor OR 1, L_0x12f8060, L_0x12f81c0, C4<0>, C4<0>; -L_0x12f7fa0 .delay 1 (30000,30000,30000) L_0x12f7fa0/d; -L_0x12f83f0/d .functor OR 1, L_0x12f8500, L_0x12f8660, C4<0>, C4<0>; -L_0x12f83f0 .delay 1 (30000,30000,30000) L_0x12f83f0/d; -L_0x12f87e0/d .functor OR 1, L_0x12f8850, L_0x12f8a00, C4<0>, C4<0>; -L_0x12f87e0 .delay 1 (30000,30000,30000) L_0x12f87e0/d; -v0x116d220_0 .net *"_s0", 0 0, L_0x12f7fa0; 1 drivers -v0x116d320_0 .net *"_s10", 0 0, L_0x12f8500; 1 drivers -v0x116d400_0 .net *"_s12", 0 0, L_0x12f8660; 1 drivers -v0x116d4c0_0 .net *"_s14", 0 0, L_0x12f8850; 1 drivers -v0x116d5a0_0 .net *"_s16", 0 0, L_0x12f8a00; 1 drivers -v0x116d6d0_0 .net *"_s3", 0 0, L_0x12f8060; 1 drivers -v0x116d7b0_0 .net *"_s5", 0 0, L_0x12f81c0; 1 drivers -v0x116d890_0 .net *"_s6", 0 0, L_0x12f83f0; 1 drivers -v0x116d970_0 .net "in", 3 0, L_0x12f8af0; 1 drivers -v0x116dae0_0 .net "ors", 1 0, L_0x12f8300; 1 drivers -v0x116dbc0_0 .net "out", 0 0, L_0x12f87e0; 1 drivers -L_0x12f8060 .part L_0x12f8af0, 0, 1; -L_0x12f81c0 .part L_0x12f8af0, 1, 1; -L_0x12f8300 .concat8 [ 1 1 0 0], L_0x12f7fa0, L_0x12f83f0; -L_0x12f8500 .part L_0x12f8af0, 2, 1; -L_0x12f8660 .part L_0x12f8af0, 3, 1; -L_0x12f8850 .part L_0x12f8300, 0, 1; -L_0x12f8a00 .part L_0x12f8300, 1, 1; -S_0x116dce0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x116ce10; +L_0x2de7cc0/d .functor OR 1, L_0x2de7d80, L_0x2de7ee0, C4<0>, C4<0>; +L_0x2de7cc0 .delay 1 (30000,30000,30000) L_0x2de7cc0/d; +L_0x2de8110/d .functor OR 1, L_0x2de8220, L_0x2de8380, C4<0>, C4<0>; +L_0x2de8110 .delay 1 (30000,30000,30000) L_0x2de8110/d; +L_0x2de8500/d .functor OR 1, L_0x2de8570, L_0x2de8720, C4<0>, C4<0>; +L_0x2de8500 .delay 1 (30000,30000,30000) L_0x2de8500/d; +v0x2c43000_0 .net *"_s0", 0 0, L_0x2de7cc0; 1 drivers +v0x2c43100_0 .net *"_s10", 0 0, L_0x2de8220; 1 drivers +v0x2c431e0_0 .net *"_s12", 0 0, L_0x2de8380; 1 drivers +v0x2c432a0_0 .net *"_s14", 0 0, L_0x2de8570; 1 drivers +v0x2c43380_0 .net *"_s16", 0 0, L_0x2de8720; 1 drivers +v0x2c434b0_0 .net *"_s3", 0 0, L_0x2de7d80; 1 drivers +v0x2c43590_0 .net *"_s5", 0 0, L_0x2de7ee0; 1 drivers +v0x2c43670_0 .net *"_s6", 0 0, L_0x2de8110; 1 drivers +v0x2c43750_0 .net "in", 3 0, L_0x2de8810; 1 drivers +v0x2c438c0_0 .net "ors", 1 0, L_0x2de8020; 1 drivers +v0x2c439a0_0 .net "out", 0 0, L_0x2de8500; 1 drivers +L_0x2de7d80 .part L_0x2de8810, 0, 1; +L_0x2de7ee0 .part L_0x2de8810, 1, 1; +L_0x2de8020 .concat8 [ 1 1 0 0], L_0x2de7cc0, L_0x2de8110; +L_0x2de8220 .part L_0x2de8810, 2, 1; +L_0x2de8380 .part L_0x2de8810, 3, 1; +L_0x2de8570 .part L_0x2de8020, 0, 1; +L_0x2de8720 .part L_0x2de8020, 1, 1; +S_0x2c43ac0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c42bf0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12f8c20/d .functor OR 1, L_0x12f8c90, L_0x12f8df0, C4<0>, C4<0>; -L_0x12f8c20 .delay 1 (30000,30000,30000) L_0x12f8c20/d; -L_0x12f9020/d .functor OR 1, L_0x12f9130, L_0x12f9290, C4<0>, C4<0>; -L_0x12f9020 .delay 1 (30000,30000,30000) L_0x12f9020/d; -L_0x12f9410/d .functor OR 1, L_0x12f9480, L_0x12f9630, C4<0>, C4<0>; -L_0x12f9410 .delay 1 (30000,30000,30000) L_0x12f9410/d; -v0x116dea0_0 .net *"_s0", 0 0, L_0x12f8c20; 1 drivers -v0x116dfa0_0 .net *"_s10", 0 0, L_0x12f9130; 1 drivers -v0x116e080_0 .net *"_s12", 0 0, L_0x12f9290; 1 drivers -v0x116e140_0 .net *"_s14", 0 0, L_0x12f9480; 1 drivers -v0x116e220_0 .net *"_s16", 0 0, L_0x12f9630; 1 drivers -v0x116e350_0 .net *"_s3", 0 0, L_0x12f8c90; 1 drivers -v0x116e430_0 .net *"_s5", 0 0, L_0x12f8df0; 1 drivers -v0x116e510_0 .net *"_s6", 0 0, L_0x12f9020; 1 drivers -v0x116e5f0_0 .net "in", 3 0, L_0x12f9860; 1 drivers -v0x116e760_0 .net "ors", 1 0, L_0x12f8f30; 1 drivers -v0x116e840_0 .net "out", 0 0, L_0x12f9410; 1 drivers -L_0x12f8c90 .part L_0x12f9860, 0, 1; -L_0x12f8df0 .part L_0x12f9860, 1, 1; -L_0x12f8f30 .concat8 [ 1 1 0 0], L_0x12f8c20, L_0x12f9020; -L_0x12f9130 .part L_0x12f9860, 2, 1; -L_0x12f9290 .part L_0x12f9860, 3, 1; -L_0x12f9480 .part L_0x12f8f30, 0, 1; -L_0x12f9630 .part L_0x12f8f30, 1, 1; -S_0x116f150 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1168280; +L_0x2de8940/d .functor OR 1, L_0x2de89b0, L_0x2de8b10, C4<0>, C4<0>; +L_0x2de8940 .delay 1 (30000,30000,30000) L_0x2de8940/d; +L_0x2de8d40/d .functor OR 1, L_0x2de8e50, L_0x2de8fb0, C4<0>, C4<0>; +L_0x2de8d40 .delay 1 (30000,30000,30000) L_0x2de8d40/d; +L_0x2de9130/d .functor OR 1, L_0x2de91a0, L_0x2de9350, C4<0>, C4<0>; +L_0x2de9130 .delay 1 (30000,30000,30000) L_0x2de9130/d; +v0x2c43c80_0 .net *"_s0", 0 0, L_0x2de8940; 1 drivers +v0x2c43d80_0 .net *"_s10", 0 0, L_0x2de8e50; 1 drivers +v0x2c43e60_0 .net *"_s12", 0 0, L_0x2de8fb0; 1 drivers +v0x2c43f20_0 .net *"_s14", 0 0, L_0x2de91a0; 1 drivers +v0x2c44000_0 .net *"_s16", 0 0, L_0x2de9350; 1 drivers +v0x2c44130_0 .net *"_s3", 0 0, L_0x2de89b0; 1 drivers +v0x2c44210_0 .net *"_s5", 0 0, L_0x2de8b10; 1 drivers +v0x2c442f0_0 .net *"_s6", 0 0, L_0x2de8d40; 1 drivers +v0x2c443d0_0 .net "in", 3 0, L_0x2de9580; 1 drivers +v0x2c44540_0 .net "ors", 1 0, L_0x2de8c50; 1 drivers +v0x2c44620_0 .net "out", 0 0, L_0x2de9130; 1 drivers +L_0x2de89b0 .part L_0x2de9580, 0, 1; +L_0x2de8b10 .part L_0x2de9580, 1, 1; +L_0x2de8c50 .concat8 [ 1 1 0 0], L_0x2de8940, L_0x2de8d40; +L_0x2de8e50 .part L_0x2de9580, 2, 1; +L_0x2de8fb0 .part L_0x2de9580, 3, 1; +L_0x2de91a0 .part L_0x2de8c50, 0, 1; +L_0x2de9350 .part L_0x2de8c50, 1, 1; +S_0x2c44f30 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c3e060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1174580_0 .net "ands", 7 0, L_0x12f3ea0; 1 drivers -v0x1174690_0 .net "in", 7 0, L_0x12f23e0; alias, 1 drivers -v0x1174750_0 .net "out", 0 0, L_0x12f5ea0; alias, 1 drivers -v0x1174820_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x116f3a0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x116f150; +v0x2c4a360_0 .net "ands", 7 0, L_0x2de3be0; 1 drivers +v0x2c4a470_0 .net "in", 7 0, L_0x2de1b60; alias, 1 drivers +v0x2c4a530_0 .net "out", 0 0, L_0x2de5be0; alias, 1 drivers +v0x2c4a600_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c45180 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c44f30; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1171ae0_0 .net "A", 7 0, L_0x12f23e0; alias, 1 drivers -v0x1171be0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1171ca0_0 .net *"_s0", 0 0, L_0x12f2770; 1 drivers -v0x1171d60_0 .net *"_s12", 0 0, L_0x12f3130; 1 drivers -v0x1171e40_0 .net *"_s16", 0 0, L_0x12f3490; 1 drivers -v0x1171f70_0 .net *"_s20", 0 0, L_0x12f3860; 1 drivers -v0x1172050_0 .net *"_s24", 0 0, L_0x12f3b90; 1 drivers -v0x1172130_0 .net *"_s28", 0 0, L_0x12f3b20; 1 drivers -v0x1172210_0 .net *"_s4", 0 0, L_0x12f2b10; 1 drivers -v0x1172380_0 .net *"_s8", 0 0, L_0x12f2e20; 1 drivers -v0x1172460_0 .net "out", 7 0, L_0x12f3ea0; alias, 1 drivers -L_0x12f2880 .part L_0x12f23e0, 0, 1; -L_0x12f2a70 .part v0x12010b0_0, 0, 1; -L_0x12f2bd0 .part L_0x12f23e0, 1, 1; -L_0x12f2d30 .part v0x12010b0_0, 1, 1; -L_0x12f2ee0 .part L_0x12f23e0, 2, 1; -L_0x12f3040 .part v0x12010b0_0, 2, 1; -L_0x12f31f0 .part L_0x12f23e0, 3, 1; -L_0x12f3350 .part v0x12010b0_0, 3, 1; -L_0x12f3550 .part L_0x12f23e0, 4, 1; -L_0x12f37c0 .part v0x12010b0_0, 4, 1; -L_0x12f38d0 .part L_0x12f23e0, 5, 1; -L_0x12f3a30 .part v0x12010b0_0, 5, 1; -L_0x12f3c50 .part L_0x12f23e0, 6, 1; -L_0x12f3db0 .part v0x12010b0_0, 6, 1; -LS_0x12f3ea0_0_0 .concat8 [ 1 1 1 1], L_0x12f2770, L_0x12f2b10, L_0x12f2e20, L_0x12f3130; -LS_0x12f3ea0_0_4 .concat8 [ 1 1 1 1], L_0x12f3490, L_0x12f3860, L_0x12f3b90, L_0x12f3b20; -L_0x12f3ea0 .concat8 [ 4 4 0 0], LS_0x12f3ea0_0_0, LS_0x12f3ea0_0_4; -L_0x12f4260 .part L_0x12f23e0, 7, 1; -L_0x12f4450 .part v0x12010b0_0, 7, 1; -S_0x116f5e0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x116f7f0 .param/l "i" 0 4 54, +C4<00>; -L_0x12f2770/d .functor AND 1, L_0x12f2880, L_0x12f2a70, C4<1>, C4<1>; -L_0x12f2770 .delay 1 (30000,30000,30000) L_0x12f2770/d; -v0x116f8d0_0 .net *"_s0", 0 0, L_0x12f2880; 1 drivers -v0x116f9b0_0 .net *"_s1", 0 0, L_0x12f2a70; 1 drivers -S_0x116fa90 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x116fca0 .param/l "i" 0 4 54, +C4<01>; -L_0x12f2b10/d .functor AND 1, L_0x12f2bd0, L_0x12f2d30, C4<1>, C4<1>; -L_0x12f2b10 .delay 1 (30000,30000,30000) L_0x12f2b10/d; -v0x116fd60_0 .net *"_s0", 0 0, L_0x12f2bd0; 1 drivers -v0x116fe40_0 .net *"_s1", 0 0, L_0x12f2d30; 1 drivers -S_0x116ff20 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x1170160 .param/l "i" 0 4 54, +C4<010>; -L_0x12f2e20/d .functor AND 1, L_0x12f2ee0, L_0x12f3040, C4<1>, C4<1>; -L_0x12f2e20 .delay 1 (30000,30000,30000) L_0x12f2e20/d; -v0x1170200_0 .net *"_s0", 0 0, L_0x12f2ee0; 1 drivers -v0x11702e0_0 .net *"_s1", 0 0, L_0x12f3040; 1 drivers -S_0x11703c0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x11705d0 .param/l "i" 0 4 54, +C4<011>; -L_0x12f3130/d .functor AND 1, L_0x12f31f0, L_0x12f3350, C4<1>, C4<1>; -L_0x12f3130 .delay 1 (30000,30000,30000) L_0x12f3130/d; -v0x1170690_0 .net *"_s0", 0 0, L_0x12f31f0; 1 drivers -v0x1170770_0 .net *"_s1", 0 0, L_0x12f3350; 1 drivers -S_0x1170850 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x1170ab0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12f3490/d .functor AND 1, L_0x12f3550, L_0x12f37c0, C4<1>, C4<1>; -L_0x12f3490 .delay 1 (30000,30000,30000) L_0x12f3490/d; -v0x1170b70_0 .net *"_s0", 0 0, L_0x12f3550; 1 drivers -v0x1170c50_0 .net *"_s1", 0 0, L_0x12f37c0; 1 drivers -S_0x1170d30 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x1170f40 .param/l "i" 0 4 54, +C4<0101>; -L_0x12f3860/d .functor AND 1, L_0x12f38d0, L_0x12f3a30, C4<1>, C4<1>; -L_0x12f3860 .delay 1 (30000,30000,30000) L_0x12f3860/d; -v0x1171000_0 .net *"_s0", 0 0, L_0x12f38d0; 1 drivers -v0x11710e0_0 .net *"_s1", 0 0, L_0x12f3a30; 1 drivers -S_0x11711c0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x11713d0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12f3b90/d .functor AND 1, L_0x12f3c50, L_0x12f3db0, C4<1>, C4<1>; -L_0x12f3b90 .delay 1 (30000,30000,30000) L_0x12f3b90/d; -v0x1171490_0 .net *"_s0", 0 0, L_0x12f3c50; 1 drivers -v0x1171570_0 .net *"_s1", 0 0, L_0x12f3db0; 1 drivers -S_0x1171650 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x116f3a0; - .timescale -9 -12; -P_0x1171860 .param/l "i" 0 4 54, +C4<0111>; -L_0x12f3b20/d .functor AND 1, L_0x12f4260, L_0x12f4450, C4<1>, C4<1>; -L_0x12f3b20 .delay 1 (30000,30000,30000) L_0x12f3b20/d; -v0x1171920_0 .net *"_s0", 0 0, L_0x12f4260; 1 drivers -v0x1171a00_0 .net *"_s1", 0 0, L_0x12f4450; 1 drivers -S_0x11725c0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x116f150; +v0x2c478c0_0 .net "A", 7 0, L_0x2de1b60; alias, 1 drivers +v0x2c479c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c47a80_0 .net *"_s0", 0 0, L_0x2de2430; 1 drivers +v0x2c47b40_0 .net *"_s12", 0 0, L_0x2de2df0; 1 drivers +v0x2c47c20_0 .net *"_s16", 0 0, L_0x2de3150; 1 drivers +v0x2c47d50_0 .net *"_s20", 0 0, L_0x2de3520; 1 drivers +v0x2c47e30_0 .net *"_s24", 0 0, L_0x2de3850; 1 drivers +v0x2c47f10_0 .net *"_s28", 0 0, L_0x2de37e0; 1 drivers +v0x2c47ff0_0 .net *"_s4", 0 0, L_0x2de27d0; 1 drivers +v0x2c48160_0 .net *"_s8", 0 0, L_0x2de2ae0; 1 drivers +v0x2c48240_0 .net "out", 7 0, L_0x2de3be0; alias, 1 drivers +L_0x2de2540 .part L_0x2de1b60, 0, 1; +L_0x2de2730 .part v0x2cdd2e0_0, 0, 1; +L_0x2de2890 .part L_0x2de1b60, 1, 1; +L_0x2de29f0 .part v0x2cdd2e0_0, 1, 1; +L_0x2de2ba0 .part L_0x2de1b60, 2, 1; +L_0x2de2d00 .part v0x2cdd2e0_0, 2, 1; +L_0x2de2eb0 .part L_0x2de1b60, 3, 1; +L_0x2de3010 .part v0x2cdd2e0_0, 3, 1; +L_0x2de3210 .part L_0x2de1b60, 4, 1; +L_0x2de3480 .part v0x2cdd2e0_0, 4, 1; +L_0x2de3590 .part L_0x2de1b60, 5, 1; +L_0x2de36f0 .part v0x2cdd2e0_0, 5, 1; +L_0x2de3910 .part L_0x2de1b60, 6, 1; +L_0x2de3a70 .part v0x2cdd2e0_0, 6, 1; +LS_0x2de3be0_0_0 .concat8 [ 1 1 1 1], L_0x2de2430, L_0x2de27d0, L_0x2de2ae0, L_0x2de2df0; +LS_0x2de3be0_0_4 .concat8 [ 1 1 1 1], L_0x2de3150, L_0x2de3520, L_0x2de3850, L_0x2de37e0; +L_0x2de3be0 .concat8 [ 4 4 0 0], LS_0x2de3be0_0_0, LS_0x2de3be0_0_4; +L_0x2de3fa0 .part L_0x2de1b60, 7, 1; +L_0x2de4190 .part v0x2cdd2e0_0, 7, 1; +S_0x2c453c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c455d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2de2430/d .functor AND 1, L_0x2de2540, L_0x2de2730, C4<1>, C4<1>; +L_0x2de2430 .delay 1 (30000,30000,30000) L_0x2de2430/d; +v0x2c456b0_0 .net *"_s0", 0 0, L_0x2de2540; 1 drivers +v0x2c45790_0 .net *"_s1", 0 0, L_0x2de2730; 1 drivers +S_0x2c45870 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c45a80 .param/l "i" 0 4 54, +C4<01>; +L_0x2de27d0/d .functor AND 1, L_0x2de2890, L_0x2de29f0, C4<1>, C4<1>; +L_0x2de27d0 .delay 1 (30000,30000,30000) L_0x2de27d0/d; +v0x2c45b40_0 .net *"_s0", 0 0, L_0x2de2890; 1 drivers +v0x2c45c20_0 .net *"_s1", 0 0, L_0x2de29f0; 1 drivers +S_0x2c45d00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c45f40 .param/l "i" 0 4 54, +C4<010>; +L_0x2de2ae0/d .functor AND 1, L_0x2de2ba0, L_0x2de2d00, C4<1>, C4<1>; +L_0x2de2ae0 .delay 1 (30000,30000,30000) L_0x2de2ae0/d; +v0x2c45fe0_0 .net *"_s0", 0 0, L_0x2de2ba0; 1 drivers +v0x2c460c0_0 .net *"_s1", 0 0, L_0x2de2d00; 1 drivers +S_0x2c461a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c463b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2de2df0/d .functor AND 1, L_0x2de2eb0, L_0x2de3010, C4<1>, C4<1>; +L_0x2de2df0 .delay 1 (30000,30000,30000) L_0x2de2df0/d; +v0x2c46470_0 .net *"_s0", 0 0, L_0x2de2eb0; 1 drivers +v0x2c46550_0 .net *"_s1", 0 0, L_0x2de3010; 1 drivers +S_0x2c46630 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c46890 .param/l "i" 0 4 54, +C4<0100>; +L_0x2de3150/d .functor AND 1, L_0x2de3210, L_0x2de3480, C4<1>, C4<1>; +L_0x2de3150 .delay 1 (30000,30000,30000) L_0x2de3150/d; +v0x2c46950_0 .net *"_s0", 0 0, L_0x2de3210; 1 drivers +v0x2c46a30_0 .net *"_s1", 0 0, L_0x2de3480; 1 drivers +S_0x2c46b10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c46d20 .param/l "i" 0 4 54, +C4<0101>; +L_0x2de3520/d .functor AND 1, L_0x2de3590, L_0x2de36f0, C4<1>, C4<1>; +L_0x2de3520 .delay 1 (30000,30000,30000) L_0x2de3520/d; +v0x2c46de0_0 .net *"_s0", 0 0, L_0x2de3590; 1 drivers +v0x2c46ec0_0 .net *"_s1", 0 0, L_0x2de36f0; 1 drivers +S_0x2c46fa0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c471b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2de3850/d .functor AND 1, L_0x2de3910, L_0x2de3a70, C4<1>, C4<1>; +L_0x2de3850 .delay 1 (30000,30000,30000) L_0x2de3850/d; +v0x2c47270_0 .net *"_s0", 0 0, L_0x2de3910; 1 drivers +v0x2c47350_0 .net *"_s1", 0 0, L_0x2de3a70; 1 drivers +S_0x2c47430 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c45180; + .timescale -9 -12; +P_0x2c47640 .param/l "i" 0 4 54, +C4<0111>; +L_0x2de37e0/d .functor AND 1, L_0x2de3fa0, L_0x2de4190, C4<1>, C4<1>; +L_0x2de37e0 .delay 1 (30000,30000,30000) L_0x2de37e0/d; +v0x2c47700_0 .net *"_s0", 0 0, L_0x2de3fa0; 1 drivers +v0x2c477e0_0 .net *"_s1", 0 0, L_0x2de4190; 1 drivers +S_0x2c483a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c44f30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12f5ea0/d .functor OR 1, L_0x12f5f60, L_0x12f6050, C4<0>, C4<0>; -L_0x12f5ea0 .delay 1 (30000,30000,30000) L_0x12f5ea0/d; -v0x1174110_0 .net *"_s10", 0 0, L_0x12f5f60; 1 drivers -v0x11741f0_0 .net *"_s12", 0 0, L_0x12f6050; 1 drivers -v0x11742d0_0 .net "in", 7 0, L_0x12f3ea0; alias, 1 drivers -v0x11743a0_0 .net "ors", 1 0, L_0x12f5cc0; 1 drivers -v0x1174460_0 .net "out", 0 0, L_0x12f5ea0; alias, 1 drivers -L_0x12f5090 .part L_0x12f3ea0, 0, 4; -L_0x12f5cc0 .concat8 [ 1 1 0 0], L_0x12f4d80, L_0x12f59b0; -L_0x12f5e00 .part L_0x12f3ea0, 4, 4; -L_0x12f5f60 .part L_0x12f5cc0, 0, 1; -L_0x12f6050 .part L_0x12f5cc0, 1, 1; -S_0x1172780 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11725c0; +L_0x2de5be0/d .functor OR 1, L_0x2de5ca0, L_0x2de5e50, C4<0>, C4<0>; +L_0x2de5be0 .delay 1 (30000,30000,30000) L_0x2de5be0/d; +v0x2c49ef0_0 .net *"_s10", 0 0, L_0x2de5ca0; 1 drivers +v0x2c49fd0_0 .net *"_s12", 0 0, L_0x2de5e50; 1 drivers +v0x2c4a0b0_0 .net "in", 7 0, L_0x2de3be0; alias, 1 drivers +v0x2c4a180_0 .net "ors", 1 0, L_0x2de5a00; 1 drivers +v0x2c4a240_0 .net "out", 0 0, L_0x2de5be0; alias, 1 drivers +L_0x2de4dd0 .part L_0x2de3be0, 0, 4; +L_0x2de5a00 .concat8 [ 1 1 0 0], L_0x2de4ac0, L_0x2de56f0; +L_0x2de5b40 .part L_0x2de3be0, 4, 4; +L_0x2de5ca0 .part L_0x2de5a00, 0, 1; +L_0x2de5e50 .part L_0x2de5a00, 1, 1; +S_0x2c48560 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c483a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12f4540/d .functor OR 1, L_0x12f4600, L_0x12f4760, C4<0>, C4<0>; -L_0x12f4540 .delay 1 (30000,30000,30000) L_0x12f4540/d; -L_0x12f4990/d .functor OR 1, L_0x12f4aa0, L_0x12f4c00, C4<0>, C4<0>; -L_0x12f4990 .delay 1 (30000,30000,30000) L_0x12f4990/d; -L_0x12f4d80/d .functor OR 1, L_0x12f4df0, L_0x12f4fa0, C4<0>, C4<0>; -L_0x12f4d80 .delay 1 (30000,30000,30000) L_0x12f4d80/d; -v0x11729d0_0 .net *"_s0", 0 0, L_0x12f4540; 1 drivers -v0x1172ad0_0 .net *"_s10", 0 0, L_0x12f4aa0; 1 drivers -v0x1172bb0_0 .net *"_s12", 0 0, L_0x12f4c00; 1 drivers -v0x1172c70_0 .net *"_s14", 0 0, L_0x12f4df0; 1 drivers -v0x1172d50_0 .net *"_s16", 0 0, L_0x12f4fa0; 1 drivers -v0x1172e80_0 .net *"_s3", 0 0, L_0x12f4600; 1 drivers -v0x1172f60_0 .net *"_s5", 0 0, L_0x12f4760; 1 drivers -v0x1173040_0 .net *"_s6", 0 0, L_0x12f4990; 1 drivers -v0x1173120_0 .net "in", 3 0, L_0x12f5090; 1 drivers -v0x1173290_0 .net "ors", 1 0, L_0x12f48a0; 1 drivers -v0x1173370_0 .net "out", 0 0, L_0x12f4d80; 1 drivers -L_0x12f4600 .part L_0x12f5090, 0, 1; -L_0x12f4760 .part L_0x12f5090, 1, 1; -L_0x12f48a0 .concat8 [ 1 1 0 0], L_0x12f4540, L_0x12f4990; -L_0x12f4aa0 .part L_0x12f5090, 2, 1; -L_0x12f4c00 .part L_0x12f5090, 3, 1; -L_0x12f4df0 .part L_0x12f48a0, 0, 1; -L_0x12f4fa0 .part L_0x12f48a0, 1, 1; -S_0x1173490 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11725c0; +L_0x2de4280/d .functor OR 1, L_0x2de4340, L_0x2de44a0, C4<0>, C4<0>; +L_0x2de4280 .delay 1 (30000,30000,30000) L_0x2de4280/d; +L_0x2de46d0/d .functor OR 1, L_0x2de47e0, L_0x2de4940, C4<0>, C4<0>; +L_0x2de46d0 .delay 1 (30000,30000,30000) L_0x2de46d0/d; +L_0x2de4ac0/d .functor OR 1, L_0x2de4b30, L_0x2de4ce0, C4<0>, C4<0>; +L_0x2de4ac0 .delay 1 (30000,30000,30000) L_0x2de4ac0/d; +v0x2c487b0_0 .net *"_s0", 0 0, L_0x2de4280; 1 drivers +v0x2c488b0_0 .net *"_s10", 0 0, L_0x2de47e0; 1 drivers +v0x2c48990_0 .net *"_s12", 0 0, L_0x2de4940; 1 drivers +v0x2c48a50_0 .net *"_s14", 0 0, L_0x2de4b30; 1 drivers +v0x2c48b30_0 .net *"_s16", 0 0, L_0x2de4ce0; 1 drivers +v0x2c48c60_0 .net *"_s3", 0 0, L_0x2de4340; 1 drivers +v0x2c48d40_0 .net *"_s5", 0 0, L_0x2de44a0; 1 drivers +v0x2c48e20_0 .net *"_s6", 0 0, L_0x2de46d0; 1 drivers +v0x2c48f00_0 .net "in", 3 0, L_0x2de4dd0; 1 drivers +v0x2c49070_0 .net "ors", 1 0, L_0x2de45e0; 1 drivers +v0x2c49150_0 .net "out", 0 0, L_0x2de4ac0; 1 drivers +L_0x2de4340 .part L_0x2de4dd0, 0, 1; +L_0x2de44a0 .part L_0x2de4dd0, 1, 1; +L_0x2de45e0 .concat8 [ 1 1 0 0], L_0x2de4280, L_0x2de46d0; +L_0x2de47e0 .part L_0x2de4dd0, 2, 1; +L_0x2de4940 .part L_0x2de4dd0, 3, 1; +L_0x2de4b30 .part L_0x2de45e0, 0, 1; +L_0x2de4ce0 .part L_0x2de45e0, 1, 1; +S_0x2c49270 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c483a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12f51c0/d .functor OR 1, L_0x12f5230, L_0x12f5390, C4<0>, C4<0>; -L_0x12f51c0 .delay 1 (30000,30000,30000) L_0x12f51c0/d; -L_0x12f55c0/d .functor OR 1, L_0x12f56d0, L_0x12f5830, C4<0>, C4<0>; -L_0x12f55c0 .delay 1 (30000,30000,30000) L_0x12f55c0/d; -L_0x12f59b0/d .functor OR 1, L_0x12f5a20, L_0x12f5bd0, C4<0>, C4<0>; -L_0x12f59b0 .delay 1 (30000,30000,30000) L_0x12f59b0/d; -v0x1173650_0 .net *"_s0", 0 0, L_0x12f51c0; 1 drivers -v0x1173750_0 .net *"_s10", 0 0, L_0x12f56d0; 1 drivers -v0x1173830_0 .net *"_s12", 0 0, L_0x12f5830; 1 drivers -v0x11738f0_0 .net *"_s14", 0 0, L_0x12f5a20; 1 drivers -v0x11739d0_0 .net *"_s16", 0 0, L_0x12f5bd0; 1 drivers -v0x1173b00_0 .net *"_s3", 0 0, L_0x12f5230; 1 drivers -v0x1173be0_0 .net *"_s5", 0 0, L_0x12f5390; 1 drivers -v0x1173cc0_0 .net *"_s6", 0 0, L_0x12f55c0; 1 drivers -v0x1173da0_0 .net "in", 3 0, L_0x12f5e00; 1 drivers -v0x1173f10_0 .net "ors", 1 0, L_0x12f54d0; 1 drivers -v0x1173ff0_0 .net "out", 0 0, L_0x12f59b0; 1 drivers -L_0x12f5230 .part L_0x12f5e00, 0, 1; -L_0x12f5390 .part L_0x12f5e00, 1, 1; -L_0x12f54d0 .concat8 [ 1 1 0 0], L_0x12f51c0, L_0x12f55c0; -L_0x12f56d0 .part L_0x12f5e00, 2, 1; -L_0x12f5830 .part L_0x12f5e00, 3, 1; -L_0x12f5a20 .part L_0x12f54d0, 0, 1; -L_0x12f5bd0 .part L_0x12f54d0, 1, 1; -S_0x1174900 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1168280; +L_0x2de4f00/d .functor OR 1, L_0x2de4f70, L_0x2de50d0, C4<0>, C4<0>; +L_0x2de4f00 .delay 1 (30000,30000,30000) L_0x2de4f00/d; +L_0x2de5300/d .functor OR 1, L_0x2de5410, L_0x2de5570, C4<0>, C4<0>; +L_0x2de5300 .delay 1 (30000,30000,30000) L_0x2de5300/d; +L_0x2de56f0/d .functor OR 1, L_0x2de5760, L_0x2de5910, C4<0>, C4<0>; +L_0x2de56f0 .delay 1 (30000,30000,30000) L_0x2de56f0/d; +v0x2c49430_0 .net *"_s0", 0 0, L_0x2de4f00; 1 drivers +v0x2c49530_0 .net *"_s10", 0 0, L_0x2de5410; 1 drivers +v0x2c49610_0 .net *"_s12", 0 0, L_0x2de5570; 1 drivers +v0x2c496d0_0 .net *"_s14", 0 0, L_0x2de5760; 1 drivers +v0x2c497b0_0 .net *"_s16", 0 0, L_0x2de5910; 1 drivers +v0x2c498e0_0 .net *"_s3", 0 0, L_0x2de4f70; 1 drivers +v0x2c499c0_0 .net *"_s5", 0 0, L_0x2de50d0; 1 drivers +v0x2c49aa0_0 .net *"_s6", 0 0, L_0x2de5300; 1 drivers +v0x2c49b80_0 .net "in", 3 0, L_0x2de5b40; 1 drivers +v0x2c49cf0_0 .net "ors", 1 0, L_0x2de5210; 1 drivers +v0x2c49dd0_0 .net "out", 0 0, L_0x2de56f0; 1 drivers +L_0x2de4f70 .part L_0x2de5b40, 0, 1; +L_0x2de50d0 .part L_0x2de5b40, 1, 1; +L_0x2de5210 .concat8 [ 1 1 0 0], L_0x2de4f00, L_0x2de5300; +L_0x2de5410 .part L_0x2de5b40, 2, 1; +L_0x2de5570 .part L_0x2de5b40, 3, 1; +L_0x2de5760 .part L_0x2de5210, 0, 1; +L_0x2de5910 .part L_0x2de5210, 1, 1; +S_0x2c4a6e0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c3e060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -13382,80 +14159,80 @@ S_0x1174900 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1168280; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12f1750/d .functor XNOR 1, L_0x12f9d60, L_0x12f9ec0, C4<0>, C4<0>; -L_0x12f1750 .delay 1 (20000,20000,20000) L_0x12f1750/d; -L_0x12f19c0/d .functor AND 1, L_0x12f9d60, L_0x12f0640, C4<1>, C4<1>; -L_0x12f19c0 .delay 1 (30000,30000,30000) L_0x12f19c0/d; -L_0x12f1a30/d .functor AND 1, L_0x12f1750, L_0x12f0290, C4<1>, C4<1>; -L_0x12f1a30 .delay 1 (30000,30000,30000) L_0x12f1a30/d; -L_0x12f1b90/d .functor OR 1, L_0x12f1a30, L_0x12f19c0, C4<0>, C4<0>; -L_0x12f1b90 .delay 1 (30000,30000,30000) L_0x12f1b90/d; -v0x1174bb0_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers -v0x1174ca0_0 .net "a_", 0 0, L_0x12f0530; alias, 1 drivers -v0x1174d60_0 .net "b", 0 0, L_0x12f9ec0; alias, 1 drivers -v0x1174e50_0 .net "b_", 0 0, L_0x12f0640; alias, 1 drivers -v0x1174ef0_0 .net "carryin", 0 0, L_0x12f0290; alias, 1 drivers -v0x1175030_0 .net "eq", 0 0, L_0x12f1750; 1 drivers -v0x11750f0_0 .net "lt", 0 0, L_0x12f19c0; 1 drivers -v0x11751b0_0 .net "out", 0 0, L_0x12f1b90; 1 drivers -v0x1175270_0 .net "w0", 0 0, L_0x12f1a30; 1 drivers -S_0x11754c0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1168280; +L_0x2de0a10/d .functor XNOR 1, L_0x2de9a80, L_0x2de9be0, C4<0>, C4<0>; +L_0x2de0a10 .delay 1 (20000,20000,20000) L_0x2de0a10/d; +L_0x2de0b90/d .functor AND 1, L_0x2de9a80, L_0x2ddf700, C4<1>, C4<1>; +L_0x2de0b90 .delay 1 (30000,30000,30000) L_0x2de0b90/d; +L_0x2de0cf0/d .functor AND 1, L_0x2de0a10, L_0x2ddf3a0, C4<1>, C4<1>; +L_0x2de0cf0 .delay 1 (30000,30000,30000) L_0x2de0cf0/d; +L_0x2de0e00/d .functor OR 1, L_0x2de0cf0, L_0x2de0b90, C4<0>, C4<0>; +L_0x2de0e00 .delay 1 (30000,30000,30000) L_0x2de0e00/d; +v0x2c4a990_0 .net "a", 0 0, L_0x2de9a80; alias, 1 drivers +v0x2c4aa80_0 .net "a_", 0 0, L_0x2ddf5f0; alias, 1 drivers +v0x2c4ab40_0 .net "b", 0 0, L_0x2de9be0; alias, 1 drivers +v0x2c4ac30_0 .net "b_", 0 0, L_0x2ddf700; alias, 1 drivers +v0x2c4acd0_0 .net "carryin", 0 0, L_0x2ddf3a0; alias, 1 drivers +v0x2c4ae10_0 .net "eq", 0 0, L_0x2de0a10; 1 drivers +v0x2c4aed0_0 .net "lt", 0 0, L_0x2de0b90; 1 drivers +v0x2c4af90_0 .net "out", 0 0, L_0x2de0e00; 1 drivers +v0x2c4b050_0 .net "w0", 0 0, L_0x2de0cf0; 1 drivers +S_0x2c4b2a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c3e060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12f1530/d .functor OR 1, L_0x12f1030, L_0x1176720, C4<0>, C4<0>; -L_0x12f1530 .delay 1 (30000,30000,30000) L_0x12f1530/d; -v0x11762b0_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers -v0x1176400_0 .net "b", 0 0, L_0x12f0640; alias, 1 drivers -v0x11764c0_0 .net "c1", 0 0, L_0x12f1030; 1 drivers -v0x1176560_0 .net "c2", 0 0, L_0x1176720; 1 drivers -v0x1176630_0 .net "carryin", 0 0, L_0x12f0290; alias, 1 drivers -v0x11767b0_0 .net "carryout", 0 0, L_0x12f1530; 1 drivers -v0x1176850_0 .net "s1", 0 0, L_0x12f0f70; 1 drivers -v0x11768f0_0 .net "sum", 0 0, L_0x12f1190; 1 drivers -S_0x1175710 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11754c0; +L_0x2de05f0/d .functor OR 1, L_0x2de00f0, L_0x2c4c500, C4<0>, C4<0>; +L_0x2de05f0 .delay 1 (30000,30000,30000) L_0x2de05f0/d; +v0x2c4c090_0 .net "a", 0 0, L_0x2de9a80; alias, 1 drivers +v0x2c4c1e0_0 .net "b", 0 0, L_0x2ddf700; alias, 1 drivers +v0x2c4c2a0_0 .net "c1", 0 0, L_0x2de00f0; 1 drivers +v0x2c4c340_0 .net "c2", 0 0, L_0x2c4c500; 1 drivers +v0x2c4c410_0 .net "carryin", 0 0, L_0x2ddf3a0; alias, 1 drivers +v0x2c4c590_0 .net "carryout", 0 0, L_0x2de05f0; 1 drivers +v0x2c4c630_0 .net "s1", 0 0, L_0x2de0030; 1 drivers +v0x2c4c6d0_0 .net "sum", 0 0, L_0x2de0250; 1 drivers +S_0x2c4b4f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c4b2a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12f0f70/d .functor XOR 1, L_0x12f9d60, L_0x12f0640, C4<0>, C4<0>; -L_0x12f0f70 .delay 1 (30000,30000,30000) L_0x12f0f70/d; -L_0x12f1030/d .functor AND 1, L_0x12f9d60, L_0x12f0640, C4<1>, C4<1>; -L_0x12f1030 .delay 1 (30000,30000,30000) L_0x12f1030/d; -v0x1175970_0 .net "a", 0 0, L_0x12f9d60; alias, 1 drivers -v0x1175a30_0 .net "b", 0 0, L_0x12f0640; alias, 1 drivers -v0x1175af0_0 .net "carryout", 0 0, L_0x12f1030; alias, 1 drivers -v0x1175b90_0 .net "sum", 0 0, L_0x12f0f70; alias, 1 drivers -S_0x1175cc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11754c0; +L_0x2de0030/d .functor XOR 1, L_0x2de9a80, L_0x2ddf700, C4<0>, C4<0>; +L_0x2de0030 .delay 1 (30000,30000,30000) L_0x2de0030/d; +L_0x2de00f0/d .functor AND 1, L_0x2de9a80, L_0x2ddf700, C4<1>, C4<1>; +L_0x2de00f0 .delay 1 (30000,30000,30000) L_0x2de00f0/d; +v0x2c4b750_0 .net "a", 0 0, L_0x2de9a80; alias, 1 drivers +v0x2c4b810_0 .net "b", 0 0, L_0x2ddf700; alias, 1 drivers +v0x2c4b8d0_0 .net "carryout", 0 0, L_0x2de00f0; alias, 1 drivers +v0x2c4b970_0 .net "sum", 0 0, L_0x2de0030; alias, 1 drivers +S_0x2c4baa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c4b2a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12f1190/d .functor XOR 1, L_0x12f0f70, L_0x12f0290, C4<0>, C4<0>; -L_0x12f1190 .delay 1 (30000,30000,30000) L_0x12f1190/d; -L_0x1176720/d .functor AND 1, L_0x12f0f70, L_0x12f0290, C4<1>, C4<1>; -L_0x1176720 .delay 1 (30000,30000,30000) L_0x1176720/d; -v0x1175f20_0 .net "a", 0 0, L_0x12f0f70; alias, 1 drivers -v0x1175ff0_0 .net "b", 0 0, L_0x12f0290; alias, 1 drivers -v0x1176090_0 .net "carryout", 0 0, L_0x1176720; alias, 1 drivers -v0x1176160_0 .net "sum", 0 0, L_0x12f1190; alias, 1 drivers -S_0x1177d10 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1167fb0; - .timescale -9 -12; -L_0x2b0ab3d06b18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06b60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12f9e00/d .functor OR 1, L_0x2b0ab3d06b18, L_0x2b0ab3d06b60, C4<0>, C4<0>; -L_0x12f9e00 .delay 1 (30000,30000,30000) L_0x12f9e00/d; -v0x1177f00_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06b18; 1 drivers -v0x1177fe0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06b60; 1 drivers -S_0x11780c0 .scope generate, "alu_slices[25]" "alu_slices[25]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11782d0 .param/l "i" 0 3 41, +C4<011001>; -S_0x1178390 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11780c0; +L_0x2de0250/d .functor XOR 1, L_0x2de0030, L_0x2ddf3a0, C4<0>, C4<0>; +L_0x2de0250 .delay 1 (30000,30000,30000) L_0x2de0250/d; +L_0x2c4c500/d .functor AND 1, L_0x2de0030, L_0x2ddf3a0, C4<1>, C4<1>; +L_0x2c4c500 .delay 1 (30000,30000,30000) L_0x2c4c500/d; +v0x2c4bd00_0 .net "a", 0 0, L_0x2de0030; alias, 1 drivers +v0x2c4bdd0_0 .net "b", 0 0, L_0x2ddf3a0; alias, 1 drivers +v0x2c4be70_0 .net "carryout", 0 0, L_0x2c4c500; alias, 1 drivers +v0x2c4bf40_0 .net "sum", 0 0, L_0x2de0250; alias, 1 drivers +S_0x2c4e760 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c3dd90; + .timescale -9 -12; +L_0x2ac6110bc168 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc1b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2de1ea0/d .functor OR 1, L_0x2ac6110bc168, L_0x2ac6110bc1b0, C4<0>, C4<0>; +L_0x2de1ea0 .delay 1 (30000,30000,30000) L_0x2de1ea0/d; +v0x2c4e950_0 .net/2u *"_s0", 0 0, L_0x2ac6110bc168; 1 drivers +v0x2c4ea30_0 .net/2u *"_s2", 0 0, L_0x2ac6110bc1b0; 1 drivers +S_0x2c4eb10 .scope generate, "alu_slices[25]" "alu_slices[25]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c4ed20 .param/l "i" 0 3 39, +C4<011001>; +S_0x2c4ede0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c4eb10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -13464,445 +14241,476 @@ S_0x1178390 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11780c0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12f0420/d .functor NOT 1, L_0x13039c0, C4<0>, C4<0>, C4<0>; -L_0x12f0420 .delay 1 (10000,10000,10000) L_0x12f0420/d; -L_0x12fa260/d .functor NOT 1, L_0x12f9f60, C4<0>, C4<0>, C4<0>; -L_0x12fa260 .delay 1 (10000,10000,10000) L_0x12fa260/d; -L_0x12fb1a0/d .functor XOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; -L_0x12fb1a0 .delay 1 (30000,30000,30000) L_0x12fb1a0/d; -L_0x2b0ab3d06ba8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06bf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x12fb850/d .functor OR 1, L_0x2b0ab3d06ba8, L_0x2b0ab3d06bf0, C4<0>, C4<0>; -L_0x12fb850 .delay 1 (30000,30000,30000) L_0x12fb850/d; -L_0x12fba50/d .functor AND 1, L_0x13039c0, L_0x12f9f60, C4<1>, C4<1>; -L_0x12fba50 .delay 1 (30000,30000,30000) L_0x12fba50/d; -L_0x12fbb10/d .functor NAND 1, L_0x13039c0, L_0x12f9f60, C4<1>, C4<1>; -L_0x12fbb10 .delay 1 (20000,20000,20000) L_0x12fbb10/d; -L_0x12fbc70/d .functor XOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; -L_0x12fbc70 .delay 1 (20000,20000,20000) L_0x12fbc70/d; -L_0x12fc120/d .functor OR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; -L_0x12fc120 .delay 1 (30000,30000,30000) L_0x12fc120/d; -L_0x13038c0/d .functor NOT 1, L_0x12ffa90, C4<0>, C4<0>, C4<0>; -L_0x13038c0 .delay 1 (10000,10000,10000) L_0x13038c0/d; -v0x11872c0_0 .net "A", 0 0, L_0x13039c0; 1 drivers -v0x1187380_0 .net "A_", 0 0, L_0x12f0420; 1 drivers -v0x1187440_0 .net "B", 0 0, L_0x12f9f60; 1 drivers -v0x1187510_0 .net "B_", 0 0, L_0x12fa260; 1 drivers -v0x11875b0_0 .net *"_s12", 0 0, L_0x12fb850; 1 drivers -v0x11876a0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06ba8; 1 drivers -v0x1187760_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06bf0; 1 drivers -v0x1187840_0 .net *"_s18", 0 0, L_0x12fba50; 1 drivers -v0x1187920_0 .net *"_s20", 0 0, L_0x12fbb10; 1 drivers -v0x1187a90_0 .net *"_s22", 0 0, L_0x12fbc70; 1 drivers -v0x1187b70_0 .net *"_s24", 0 0, L_0x12fc120; 1 drivers -o0x2b0ab3ce0798 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1187c50_0 name=_s30 -o0x2b0ab3ce07c8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1187d30_0 name=_s32 -v0x1187e10_0 .net *"_s8", 0 0, L_0x12fb1a0; 1 drivers -v0x1187ef0_0 .net "carryin", 0 0, L_0x12fa000; 1 drivers -v0x1187f90_0 .net "carryout", 0 0, L_0x1303560; 1 drivers -v0x1188030_0 .net "carryouts", 7 0, L_0x1355970; 1 drivers -v0x11881e0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1188280_0 .net "result", 0 0, L_0x12ffa90; 1 drivers -v0x1188370_0 .net "results", 7 0, L_0x12fbef0; 1 drivers -v0x1188480_0 .net "zero", 0 0, L_0x13038c0; 1 drivers -LS_0x12fbef0_0_0 .concat8 [ 1 1 1 1], L_0x12fa6c0, L_0x12facf0, L_0x12fb1a0, L_0x12fb850; -LS_0x12fbef0_0_4 .concat8 [ 1 1 1 1], L_0x12fba50, L_0x12fbb10, L_0x12fbc70, L_0x12fc120; -L_0x12fbef0 .concat8 [ 4 4 0 0], LS_0x12fbef0_0_0, LS_0x12fbef0_0_4; -LS_0x1355970_0_0 .concat [ 1 1 1 1], L_0x12fa970, L_0x12fb040, o0x2b0ab3ce0798, L_0x12fb6a0; -LS_0x1355970_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce07c8; -L_0x1355970 .concat [ 4 4 0 0], LS_0x1355970_0_0, LS_0x1355970_0_4; -S_0x1178610 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1178390; +L_0x2ddf4e0/d .functor NOT 1, L_0x2df4250, C4<0>, C4<0>, C4<0>; +L_0x2ddf4e0 .delay 1 (10000,10000,10000) L_0x2ddf4e0/d; +L_0x2de9f30/d .functor NOT 1, L_0x2de9c80, C4<0>, C4<0>, C4<0>; +L_0x2de9f30 .delay 1 (10000,10000,10000) L_0x2de9f30/d; +L_0x2deaf80/d .functor XOR 1, L_0x2df4250, L_0x2de9c80, C4<0>, C4<0>; +L_0x2deaf80 .delay 1 (30000,30000,30000) L_0x2deaf80/d; +L_0x2ac6110bc1f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc240 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2deb040/d .functor OR 1, L_0x2ac6110bc1f8, L_0x2ac6110bc240, C4<0>, C4<0>; +L_0x2deb040 .delay 1 (30000,30000,30000) L_0x2deb040/d; +L_0x2ac6110bc288 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc2d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2deb7e0/d .functor OR 1, L_0x2ac6110bc288, L_0x2ac6110bc2d0, C4<0>, C4<0>; +L_0x2deb7e0 .delay 1 (30000,30000,30000) L_0x2deb7e0/d; +L_0x2deb9e0/d .functor AND 1, L_0x2df4250, L_0x2de9c80, C4<1>, C4<1>; +L_0x2deb9e0 .delay 1 (30000,30000,30000) L_0x2deb9e0/d; +L_0x2ac6110bc318 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc360 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2debaa0/d .functor OR 1, L_0x2ac6110bc318, L_0x2ac6110bc360, C4<0>, C4<0>; +L_0x2debaa0 .delay 1 (30000,30000,30000) L_0x2debaa0/d; +L_0x2debca0/d .functor NAND 1, L_0x2df4250, L_0x2de9c80, C4<1>, C4<1>; +L_0x2debca0 .delay 1 (20000,20000,20000) L_0x2debca0/d; +L_0x2ac6110bc3a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc3f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2debdb0/d .functor OR 1, L_0x2ac6110bc3a8, L_0x2ac6110bc3f0, C4<0>, C4<0>; +L_0x2debdb0 .delay 1 (30000,30000,30000) L_0x2debdb0/d; +L_0x2debf60/d .functor NOR 1, L_0x2df4250, L_0x2de9c80, C4<0>, C4<0>; +L_0x2debf60 .delay 1 (20000,20000,20000) L_0x2debf60/d; +L_0x2ac6110bc438 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc480 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dea3e0/d .functor OR 1, L_0x2ac6110bc438, L_0x2ac6110bc480, C4<0>, C4<0>; +L_0x2dea3e0 .delay 1 (30000,30000,30000) L_0x2dea3e0/d; +L_0x2dec5c0/d .functor OR 1, L_0x2df4250, L_0x2de9c80, C4<0>, C4<0>; +L_0x2dec5c0 .delay 1 (30000,30000,30000) L_0x2dec5c0/d; +L_0x2ac6110bc4c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc510 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2decab0/d .functor OR 1, L_0x2ac6110bc4c8, L_0x2ac6110bc510, C4<0>, C4<0>; +L_0x2decab0 .delay 1 (30000,30000,30000) L_0x2decab0/d; +L_0x2df4150/d .functor NOT 1, L_0x2df03b0, C4<0>, C4<0>, C4<0>; +L_0x2df4150 .delay 1 (10000,10000,10000) L_0x2df4150/d; +v0x2c5dd10_0 .net "A", 0 0, L_0x2df4250; 1 drivers +v0x2c5ddd0_0 .net "A_", 0 0, L_0x2ddf4e0; 1 drivers +v0x2c5de90_0 .net "B", 0 0, L_0x2de9c80; 1 drivers +v0x2c5df60_0 .net "B_", 0 0, L_0x2de9f30; 1 drivers +v0x2c5e000_0 .net *"_s11", 0 0, L_0x2deb040; 1 drivers +v0x2c5e0f0_0 .net/2s *"_s13", 0 0, L_0x2ac6110bc1f8; 1 drivers +v0x2c5e1b0_0 .net/2s *"_s15", 0 0, L_0x2ac6110bc240; 1 drivers +v0x2c5e290_0 .net *"_s19", 0 0, L_0x2deb7e0; 1 drivers +v0x2c5e370_0 .net/2s *"_s21", 0 0, L_0x2ac6110bc288; 1 drivers +v0x2c5e4e0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bc2d0; 1 drivers +v0x2c5e5c0_0 .net *"_s25", 0 0, L_0x2deb9e0; 1 drivers +v0x2c5e6a0_0 .net *"_s28", 0 0, L_0x2debaa0; 1 drivers +v0x2c5e780_0 .net/2s *"_s30", 0 0, L_0x2ac6110bc318; 1 drivers +v0x2c5e860_0 .net/2s *"_s32", 0 0, L_0x2ac6110bc360; 1 drivers +v0x2c5e940_0 .net *"_s34", 0 0, L_0x2debca0; 1 drivers +v0x2c5ea20_0 .net *"_s37", 0 0, L_0x2debdb0; 1 drivers +v0x2c5eb00_0 .net/2s *"_s39", 0 0, L_0x2ac6110bc3a8; 1 drivers +v0x2c5ecb0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bc3f0; 1 drivers +v0x2c5ed50_0 .net *"_s43", 0 0, L_0x2debf60; 1 drivers +v0x2c5ee30_0 .net *"_s46", 0 0, L_0x2dea3e0; 1 drivers +v0x2c5ef10_0 .net/2s *"_s48", 0 0, L_0x2ac6110bc438; 1 drivers +v0x2c5eff0_0 .net/2s *"_s50", 0 0, L_0x2ac6110bc480; 1 drivers +v0x2c5f0d0_0 .net *"_s52", 0 0, L_0x2dec5c0; 1 drivers +v0x2c5f1b0_0 .net *"_s56", 0 0, L_0x2decab0; 1 drivers +v0x2c5f290_0 .net/2s *"_s59", 0 0, L_0x2ac6110bc4c8; 1 drivers +v0x2c5f370_0 .net/2s *"_s61", 0 0, L_0x2ac6110bc510; 1 drivers +v0x2c5f450_0 .net *"_s8", 0 0, L_0x2deaf80; 1 drivers +v0x2c5f530_0 .net "carryin", 0 0, L_0x2de9d20; 1 drivers +v0x2c5f5d0_0 .net "carryout", 0 0, L_0x2df3df0; 1 drivers +v0x2c5f670_0 .net "carryouts", 7 0, L_0x2dec740; 1 drivers +v0x2c5f780_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c5f840_0 .net "result", 0 0, L_0x2df03b0; 1 drivers +v0x2c5f930_0 .net "results", 7 0, L_0x2dec390; 1 drivers +v0x2c5ec10_0 .net "zero", 0 0, L_0x2df4150; 1 drivers +LS_0x2dec390_0_0 .concat8 [ 1 1 1 1], L_0x2dea450, L_0x2deaa80, L_0x2deaf80, L_0x2deb7e0; +LS_0x2dec390_0_4 .concat8 [ 1 1 1 1], L_0x2deb9e0, L_0x2debca0, L_0x2debf60, L_0x2dec5c0; +L_0x2dec390 .concat8 [ 4 4 0 0], LS_0x2dec390_0_0, LS_0x2dec390_0_4; +LS_0x2dec740_0_0 .concat8 [ 1 1 1 1], L_0x2dea700, L_0x2deae20, L_0x2deb040, L_0x2deb630; +LS_0x2dec740_0_4 .concat8 [ 1 1 1 1], L_0x2debaa0, L_0x2debdb0, L_0x2dea3e0, L_0x2decab0; +L_0x2dec740 .concat8 [ 4 4 0 0], LS_0x2dec740_0_0, LS_0x2dec740_0_4; +S_0x2c4f060 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c4ede0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12fa970/d .functor OR 1, L_0x12fa450, L_0x12fa810, C4<0>, C4<0>; -L_0x12fa970 .delay 1 (30000,30000,30000) L_0x12fa970/d; -v0x1179440_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers -v0x1179500_0 .net "b", 0 0, L_0x12f9f60; alias, 1 drivers -v0x11795d0_0 .net "c1", 0 0, L_0x12fa450; 1 drivers -v0x11796d0_0 .net "c2", 0 0, L_0x12fa810; 1 drivers -v0x11797a0_0 .net "carryin", 0 0, L_0x12fa000; alias, 1 drivers -v0x1179890_0 .net "carryout", 0 0, L_0x12fa970; 1 drivers -v0x1179930_0 .net "s1", 0 0, L_0x12f7880; 1 drivers -v0x1179a20_0 .net "sum", 0 0, L_0x12fa6c0; 1 drivers -S_0x1178880 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1178610; +L_0x2dea700/d .functor OR 1, L_0x2dea1e0, L_0x2dea5a0, C4<0>, C4<0>; +L_0x2dea700 .delay 1 (30000,30000,30000) L_0x2dea700/d; +v0x2c4fe90_0 .net "a", 0 0, L_0x2df4250; alias, 1 drivers +v0x2c4ff50_0 .net "b", 0 0, L_0x2de9c80; alias, 1 drivers +v0x2c50020_0 .net "c1", 0 0, L_0x2dea1e0; 1 drivers +v0x2c50120_0 .net "c2", 0 0, L_0x2dea5a0; 1 drivers +v0x2c501f0_0 .net "carryin", 0 0, L_0x2de9d20; alias, 1 drivers +v0x2c502e0_0 .net "carryout", 0 0, L_0x2dea700; 1 drivers +v0x2c50380_0 .net "s1", 0 0, L_0x2dea120; 1 drivers +v0x2c50470_0 .net "sum", 0 0, L_0x2dea450; 1 drivers +S_0x2c4f2d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c4f060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12f7880/d .functor XOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; -L_0x12f7880 .delay 1 (30000,30000,30000) L_0x12f7880/d; -L_0x12fa450/d .functor AND 1, L_0x13039c0, L_0x12f9f60, C4<1>, C4<1>; -L_0x12fa450 .delay 1 (30000,30000,30000) L_0x12fa450/d; -v0x1178ae0_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers -v0x1178bc0_0 .net "b", 0 0, L_0x12f9f60; alias, 1 drivers -v0x1178c80_0 .net "carryout", 0 0, L_0x12fa450; alias, 1 drivers -v0x1178d20_0 .net "sum", 0 0, L_0x12f7880; alias, 1 drivers -S_0x1178e60 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1178610; +L_0x2dea120/d .functor XOR 1, L_0x2df4250, L_0x2de9c80, C4<0>, C4<0>; +L_0x2dea120 .delay 1 (30000,30000,30000) L_0x2dea120/d; +L_0x2dea1e0/d .functor AND 1, L_0x2df4250, L_0x2de9c80, C4<1>, C4<1>; +L_0x2dea1e0 .delay 1 (30000,30000,30000) L_0x2dea1e0/d; +v0x2c4f530_0 .net "a", 0 0, L_0x2df4250; alias, 1 drivers +v0x2c4f610_0 .net "b", 0 0, L_0x2de9c80; alias, 1 drivers +v0x2c4f6d0_0 .net "carryout", 0 0, L_0x2dea1e0; alias, 1 drivers +v0x2c4f770_0 .net "sum", 0 0, L_0x2dea120; alias, 1 drivers +S_0x2c4f8b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c4f060; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12fa6c0/d .functor XOR 1, L_0x12f7880, L_0x12fa000, C4<0>, C4<0>; -L_0x12fa6c0 .delay 1 (30000,30000,30000) L_0x12fa6c0/d; -L_0x12fa810/d .functor AND 1, L_0x12f7880, L_0x12fa000, C4<1>, C4<1>; -L_0x12fa810 .delay 1 (30000,30000,30000) L_0x12fa810/d; -v0x11790c0_0 .net "a", 0 0, L_0x12f7880; alias, 1 drivers -v0x1179160_0 .net "b", 0 0, L_0x12fa000; alias, 1 drivers -v0x1179200_0 .net "carryout", 0 0, L_0x12fa810; alias, 1 drivers -v0x11792d0_0 .net "sum", 0 0, L_0x12fa6c0; alias, 1 drivers -S_0x1179af0 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1178390; +L_0x2dea450/d .functor XOR 1, L_0x2dea120, L_0x2de9d20, C4<0>, C4<0>; +L_0x2dea450 .delay 1 (30000,30000,30000) L_0x2dea450/d; +L_0x2dea5a0/d .functor AND 1, L_0x2dea120, L_0x2de9d20, C4<1>, C4<1>; +L_0x2dea5a0 .delay 1 (30000,30000,30000) L_0x2dea5a0/d; +v0x2c4fb10_0 .net "a", 0 0, L_0x2dea120; alias, 1 drivers +v0x2c4fbb0_0 .net "b", 0 0, L_0x2de9d20; alias, 1 drivers +v0x2c4fc50_0 .net "carryout", 0 0, L_0x2dea5a0; alias, 1 drivers +v0x2c4fd20_0 .net "sum", 0 0, L_0x2dea450; alias, 1 drivers +S_0x2c50540 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c4ede0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x117eee0_0 .net "ands", 7 0, L_0x1301560; 1 drivers -v0x117eff0_0 .net "in", 7 0, L_0x1355970; alias, 1 drivers -v0x117f0b0_0 .net "out", 0 0, L_0x1303560; alias, 1 drivers -v0x117f180_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x1179d10 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x1179af0; +v0x2c55930_0 .net "ands", 7 0, L_0x2df1df0; 1 drivers +v0x2c55a40_0 .net "in", 7 0, L_0x2dec740; alias, 1 drivers +v0x2c55b00_0 .net "out", 0 0, L_0x2df3df0; alias, 1 drivers +v0x2c55bd0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c50760 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c50540; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x117c440_0 .net "A", 7 0, L_0x1355970; alias, 1 drivers -v0x117c540_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x117c600_0 .net *"_s0", 0 0, L_0x12ffdf0; 1 drivers -v0x117c6c0_0 .net *"_s12", 0 0, L_0x1300760; 1 drivers -v0x117c7a0_0 .net *"_s16", 0 0, L_0x1300ac0; 1 drivers -v0x117c8d0_0 .net *"_s20", 0 0, L_0x1300e30; 1 drivers -v0x117c9b0_0 .net *"_s24", 0 0, L_0x1301250; 1 drivers -v0x117ca90_0 .net *"_s28", 0 0, L_0x13011e0; 1 drivers -v0x117cb70_0 .net *"_s4", 0 0, L_0x1300100; 1 drivers -v0x117cce0_0 .net *"_s8", 0 0, L_0x1300450; 1 drivers -v0x117cdc0_0 .net "out", 7 0, L_0x1301560; alias, 1 drivers -L_0x12ffeb0 .part L_0x1355970, 0, 1; -L_0x1300010 .part v0x12010b0_0, 0, 1; -L_0x13001c0 .part L_0x1355970, 1, 1; -L_0x13003b0 .part v0x12010b0_0, 1, 1; -L_0x1300510 .part L_0x1355970, 2, 1; -L_0x1300670 .part v0x12010b0_0, 2, 1; -L_0x1300820 .part L_0x1355970, 3, 1; -L_0x1300980 .part v0x12010b0_0, 3, 1; -L_0x1300be0 .part L_0x1355970, 4, 1; -L_0x1300d40 .part v0x12010b0_0, 4, 1; -L_0x1300ed0 .part L_0x1355970, 5, 1; -L_0x1301140 .part v0x12010b0_0, 5, 1; -L_0x1301310 .part L_0x1355970, 6, 1; -L_0x1301470 .part v0x12010b0_0, 6, 1; -LS_0x1301560_0_0 .concat8 [ 1 1 1 1], L_0x12ffdf0, L_0x1300100, L_0x1300450, L_0x1300760; -LS_0x1301560_0_4 .concat8 [ 1 1 1 1], L_0x1300ac0, L_0x1300e30, L_0x1301250, L_0x13011e0; -L_0x1301560 .concat8 [ 4 4 0 0], LS_0x1301560_0_0, LS_0x1301560_0_4; -L_0x1301920 .part L_0x1355970, 7, 1; -L_0x1301b10 .part v0x12010b0_0, 7, 1; -S_0x1179f70 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117a180 .param/l "i" 0 4 54, +C4<00>; -L_0x12ffdf0/d .functor AND 1, L_0x12ffeb0, L_0x1300010, C4<1>, C4<1>; -L_0x12ffdf0 .delay 1 (30000,30000,30000) L_0x12ffdf0/d; -v0x117a260_0 .net *"_s0", 0 0, L_0x12ffeb0; 1 drivers -v0x117a340_0 .net *"_s1", 0 0, L_0x1300010; 1 drivers -S_0x117a420 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117a630 .param/l "i" 0 4 54, +C4<01>; -L_0x1300100/d .functor AND 1, L_0x13001c0, L_0x13003b0, C4<1>, C4<1>; -L_0x1300100 .delay 1 (30000,30000,30000) L_0x1300100/d; -v0x117a6f0_0 .net *"_s0", 0 0, L_0x13001c0; 1 drivers -v0x117a7d0_0 .net *"_s1", 0 0, L_0x13003b0; 1 drivers -S_0x117a8b0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117aac0 .param/l "i" 0 4 54, +C4<010>; -L_0x1300450/d .functor AND 1, L_0x1300510, L_0x1300670, C4<1>, C4<1>; -L_0x1300450 .delay 1 (30000,30000,30000) L_0x1300450/d; -v0x117ab60_0 .net *"_s0", 0 0, L_0x1300510; 1 drivers -v0x117ac40_0 .net *"_s1", 0 0, L_0x1300670; 1 drivers -S_0x117ad20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117af30 .param/l "i" 0 4 54, +C4<011>; -L_0x1300760/d .functor AND 1, L_0x1300820, L_0x1300980, C4<1>, C4<1>; -L_0x1300760 .delay 1 (30000,30000,30000) L_0x1300760/d; -v0x117aff0_0 .net *"_s0", 0 0, L_0x1300820; 1 drivers -v0x117b0d0_0 .net *"_s1", 0 0, L_0x1300980; 1 drivers -S_0x117b1b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117b410 .param/l "i" 0 4 54, +C4<0100>; -L_0x1300ac0/d .functor AND 1, L_0x1300be0, L_0x1300d40, C4<1>, C4<1>; -L_0x1300ac0 .delay 1 (30000,30000,30000) L_0x1300ac0/d; -v0x117b4d0_0 .net *"_s0", 0 0, L_0x1300be0; 1 drivers -v0x117b5b0_0 .net *"_s1", 0 0, L_0x1300d40; 1 drivers -S_0x117b690 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117b8a0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1300e30/d .functor AND 1, L_0x1300ed0, L_0x1301140, C4<1>, C4<1>; -L_0x1300e30 .delay 1 (30000,30000,30000) L_0x1300e30/d; -v0x117b960_0 .net *"_s0", 0 0, L_0x1300ed0; 1 drivers -v0x117ba40_0 .net *"_s1", 0 0, L_0x1301140; 1 drivers -S_0x117bb20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117bd30 .param/l "i" 0 4 54, +C4<0110>; -L_0x1301250/d .functor AND 1, L_0x1301310, L_0x1301470, C4<1>, C4<1>; -L_0x1301250 .delay 1 (30000,30000,30000) L_0x1301250/d; -v0x117bdf0_0 .net *"_s0", 0 0, L_0x1301310; 1 drivers -v0x117bed0_0 .net *"_s1", 0 0, L_0x1301470; 1 drivers -S_0x117bfb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x1179d10; - .timescale -9 -12; -P_0x117c1c0 .param/l "i" 0 4 54, +C4<0111>; -L_0x13011e0/d .functor AND 1, L_0x1301920, L_0x1301b10, C4<1>, C4<1>; -L_0x13011e0 .delay 1 (30000,30000,30000) L_0x13011e0/d; -v0x117c280_0 .net *"_s0", 0 0, L_0x1301920; 1 drivers -v0x117c360_0 .net *"_s1", 0 0, L_0x1301b10; 1 drivers -S_0x117cf20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x1179af0; +v0x2c52e90_0 .net "A", 7 0, L_0x2dec740; alias, 1 drivers +v0x2c52f90_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c53050_0 .net *"_s0", 0 0, L_0x2df0710; 1 drivers +v0x2c53110_0 .net *"_s12", 0 0, L_0x2df1080; 1 drivers +v0x2c531f0_0 .net *"_s16", 0 0, L_0x2df13e0; 1 drivers +v0x2c53320_0 .net *"_s20", 0 0, L_0x2df17b0; 1 drivers +v0x2c53400_0 .net *"_s24", 0 0, L_0x2df1ae0; 1 drivers +v0x2c534e0_0 .net *"_s28", 0 0, L_0x2df1a70; 1 drivers +v0x2c535c0_0 .net *"_s4", 0 0, L_0x2df0a60; 1 drivers +v0x2c53730_0 .net *"_s8", 0 0, L_0x2df0d70; 1 drivers +v0x2c53810_0 .net "out", 7 0, L_0x2df1df0; alias, 1 drivers +L_0x2df07d0 .part L_0x2dec740, 0, 1; +L_0x2df09c0 .part v0x2cdd2e0_0, 0, 1; +L_0x2df0b20 .part L_0x2dec740, 1, 1; +L_0x2df0c80 .part v0x2cdd2e0_0, 1, 1; +L_0x2df0e30 .part L_0x2dec740, 2, 1; +L_0x2df0f90 .part v0x2cdd2e0_0, 2, 1; +L_0x2df1140 .part L_0x2dec740, 3, 1; +L_0x2df12a0 .part v0x2cdd2e0_0, 3, 1; +L_0x2df14a0 .part L_0x2dec740, 4, 1; +L_0x2df1710 .part v0x2cdd2e0_0, 4, 1; +L_0x2df1820 .part L_0x2dec740, 5, 1; +L_0x2df1980 .part v0x2cdd2e0_0, 5, 1; +L_0x2df1ba0 .part L_0x2dec740, 6, 1; +L_0x2df1d00 .part v0x2cdd2e0_0, 6, 1; +LS_0x2df1df0_0_0 .concat8 [ 1 1 1 1], L_0x2df0710, L_0x2df0a60, L_0x2df0d70, L_0x2df1080; +LS_0x2df1df0_0_4 .concat8 [ 1 1 1 1], L_0x2df13e0, L_0x2df17b0, L_0x2df1ae0, L_0x2df1a70; +L_0x2df1df0 .concat8 [ 4 4 0 0], LS_0x2df1df0_0_0, LS_0x2df1df0_0_4; +L_0x2df21b0 .part L_0x2dec740, 7, 1; +L_0x2df23a0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c509c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c50bd0 .param/l "i" 0 4 54, +C4<00>; +L_0x2df0710/d .functor AND 1, L_0x2df07d0, L_0x2df09c0, C4<1>, C4<1>; +L_0x2df0710 .delay 1 (30000,30000,30000) L_0x2df0710/d; +v0x2c50cb0_0 .net *"_s0", 0 0, L_0x2df07d0; 1 drivers +v0x2c50d90_0 .net *"_s1", 0 0, L_0x2df09c0; 1 drivers +S_0x2c50e70 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c51080 .param/l "i" 0 4 54, +C4<01>; +L_0x2df0a60/d .functor AND 1, L_0x2df0b20, L_0x2df0c80, C4<1>, C4<1>; +L_0x2df0a60 .delay 1 (30000,30000,30000) L_0x2df0a60/d; +v0x2c51140_0 .net *"_s0", 0 0, L_0x2df0b20; 1 drivers +v0x2c51220_0 .net *"_s1", 0 0, L_0x2df0c80; 1 drivers +S_0x2c51300 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c51510 .param/l "i" 0 4 54, +C4<010>; +L_0x2df0d70/d .functor AND 1, L_0x2df0e30, L_0x2df0f90, C4<1>, C4<1>; +L_0x2df0d70 .delay 1 (30000,30000,30000) L_0x2df0d70/d; +v0x2c515b0_0 .net *"_s0", 0 0, L_0x2df0e30; 1 drivers +v0x2c51690_0 .net *"_s1", 0 0, L_0x2df0f90; 1 drivers +S_0x2c51770 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c51980 .param/l "i" 0 4 54, +C4<011>; +L_0x2df1080/d .functor AND 1, L_0x2df1140, L_0x2df12a0, C4<1>, C4<1>; +L_0x2df1080 .delay 1 (30000,30000,30000) L_0x2df1080/d; +v0x2c51a40_0 .net *"_s0", 0 0, L_0x2df1140; 1 drivers +v0x2c51b20_0 .net *"_s1", 0 0, L_0x2df12a0; 1 drivers +S_0x2c51c00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c51e60 .param/l "i" 0 4 54, +C4<0100>; +L_0x2df13e0/d .functor AND 1, L_0x2df14a0, L_0x2df1710, C4<1>, C4<1>; +L_0x2df13e0 .delay 1 (30000,30000,30000) L_0x2df13e0/d; +v0x2c51f20_0 .net *"_s0", 0 0, L_0x2df14a0; 1 drivers +v0x2c52000_0 .net *"_s1", 0 0, L_0x2df1710; 1 drivers +S_0x2c520e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c522f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2df17b0/d .functor AND 1, L_0x2df1820, L_0x2df1980, C4<1>, C4<1>; +L_0x2df17b0 .delay 1 (30000,30000,30000) L_0x2df17b0/d; +v0x2c523b0_0 .net *"_s0", 0 0, L_0x2df1820; 1 drivers +v0x2c52490_0 .net *"_s1", 0 0, L_0x2df1980; 1 drivers +S_0x2c52570 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c52780 .param/l "i" 0 4 54, +C4<0110>; +L_0x2df1ae0/d .functor AND 1, L_0x2df1ba0, L_0x2df1d00, C4<1>, C4<1>; +L_0x2df1ae0 .delay 1 (30000,30000,30000) L_0x2df1ae0/d; +v0x2c52840_0 .net *"_s0", 0 0, L_0x2df1ba0; 1 drivers +v0x2c52920_0 .net *"_s1", 0 0, L_0x2df1d00; 1 drivers +S_0x2c52a00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c50760; + .timescale -9 -12; +P_0x2c52c10 .param/l "i" 0 4 54, +C4<0111>; +L_0x2df1a70/d .functor AND 1, L_0x2df21b0, L_0x2df23a0, C4<1>, C4<1>; +L_0x2df1a70 .delay 1 (30000,30000,30000) L_0x2df1a70/d; +v0x2c52cd0_0 .net *"_s0", 0 0, L_0x2df21b0; 1 drivers +v0x2c52db0_0 .net *"_s1", 0 0, L_0x2df23a0; 1 drivers +S_0x2c53970 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c50540; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1303560/d .functor OR 1, L_0x1303620, L_0x13037d0, C4<0>, C4<0>; -L_0x1303560 .delay 1 (30000,30000,30000) L_0x1303560/d; -v0x117ea70_0 .net *"_s10", 0 0, L_0x1303620; 1 drivers -v0x117eb50_0 .net *"_s12", 0 0, L_0x13037d0; 1 drivers -v0x117ec30_0 .net "in", 7 0, L_0x1301560; alias, 1 drivers -v0x117ed00_0 .net "ors", 1 0, L_0x1303380; 1 drivers -v0x117edc0_0 .net "out", 0 0, L_0x1303560; alias, 1 drivers -L_0x1302750 .part L_0x1301560, 0, 4; -L_0x1303380 .concat8 [ 1 1 0 0], L_0x1302440, L_0x1303070; -L_0x13034c0 .part L_0x1301560, 4, 4; -L_0x1303620 .part L_0x1303380, 0, 1; -L_0x13037d0 .part L_0x1303380, 1, 1; -S_0x117d0e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x117cf20; +L_0x2df3df0/d .functor OR 1, L_0x2df3eb0, L_0x2df4060, C4<0>, C4<0>; +L_0x2df3df0 .delay 1 (30000,30000,30000) L_0x2df3df0/d; +v0x2c554c0_0 .net *"_s10", 0 0, L_0x2df3eb0; 1 drivers +v0x2c555a0_0 .net *"_s12", 0 0, L_0x2df4060; 1 drivers +v0x2c55680_0 .net "in", 7 0, L_0x2df1df0; alias, 1 drivers +v0x2c55750_0 .net "ors", 1 0, L_0x2df3c10; 1 drivers +v0x2c55810_0 .net "out", 0 0, L_0x2df3df0; alias, 1 drivers +L_0x2df2fe0 .part L_0x2df1df0, 0, 4; +L_0x2df3c10 .concat8 [ 1 1 0 0], L_0x2df2cd0, L_0x2df3900; +L_0x2df3d50 .part L_0x2df1df0, 4, 4; +L_0x2df3eb0 .part L_0x2df3c10, 0, 1; +L_0x2df4060 .part L_0x2df3c10, 1, 1; +S_0x2c53b30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c53970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1301c00/d .functor OR 1, L_0x1301cc0, L_0x1301e20, C4<0>, C4<0>; -L_0x1301c00 .delay 1 (30000,30000,30000) L_0x1301c00/d; -L_0x1302050/d .functor OR 1, L_0x1302160, L_0x13022c0, C4<0>, C4<0>; -L_0x1302050 .delay 1 (30000,30000,30000) L_0x1302050/d; -L_0x1302440/d .functor OR 1, L_0x13024b0, L_0x1302660, C4<0>, C4<0>; -L_0x1302440 .delay 1 (30000,30000,30000) L_0x1302440/d; -v0x117d330_0 .net *"_s0", 0 0, L_0x1301c00; 1 drivers -v0x117d430_0 .net *"_s10", 0 0, L_0x1302160; 1 drivers -v0x117d510_0 .net *"_s12", 0 0, L_0x13022c0; 1 drivers -v0x117d5d0_0 .net *"_s14", 0 0, L_0x13024b0; 1 drivers -v0x117d6b0_0 .net *"_s16", 0 0, L_0x1302660; 1 drivers -v0x117d7e0_0 .net *"_s3", 0 0, L_0x1301cc0; 1 drivers -v0x117d8c0_0 .net *"_s5", 0 0, L_0x1301e20; 1 drivers -v0x117d9a0_0 .net *"_s6", 0 0, L_0x1302050; 1 drivers -v0x117da80_0 .net "in", 3 0, L_0x1302750; 1 drivers -v0x117dbf0_0 .net "ors", 1 0, L_0x1301f60; 1 drivers -v0x117dcd0_0 .net "out", 0 0, L_0x1302440; 1 drivers -L_0x1301cc0 .part L_0x1302750, 0, 1; -L_0x1301e20 .part L_0x1302750, 1, 1; -L_0x1301f60 .concat8 [ 1 1 0 0], L_0x1301c00, L_0x1302050; -L_0x1302160 .part L_0x1302750, 2, 1; -L_0x13022c0 .part L_0x1302750, 3, 1; -L_0x13024b0 .part L_0x1301f60, 0, 1; -L_0x1302660 .part L_0x1301f60, 1, 1; -S_0x117ddf0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x117cf20; +L_0x2df2490/d .functor OR 1, L_0x2df2550, L_0x2df26b0, C4<0>, C4<0>; +L_0x2df2490 .delay 1 (30000,30000,30000) L_0x2df2490/d; +L_0x2df28e0/d .functor OR 1, L_0x2df29f0, L_0x2df2b50, C4<0>, C4<0>; +L_0x2df28e0 .delay 1 (30000,30000,30000) L_0x2df28e0/d; +L_0x2df2cd0/d .functor OR 1, L_0x2df2d40, L_0x2df2ef0, C4<0>, C4<0>; +L_0x2df2cd0 .delay 1 (30000,30000,30000) L_0x2df2cd0/d; +v0x2c53d80_0 .net *"_s0", 0 0, L_0x2df2490; 1 drivers +v0x2c53e80_0 .net *"_s10", 0 0, L_0x2df29f0; 1 drivers +v0x2c53f60_0 .net *"_s12", 0 0, L_0x2df2b50; 1 drivers +v0x2c54020_0 .net *"_s14", 0 0, L_0x2df2d40; 1 drivers +v0x2c54100_0 .net *"_s16", 0 0, L_0x2df2ef0; 1 drivers +v0x2c54230_0 .net *"_s3", 0 0, L_0x2df2550; 1 drivers +v0x2c54310_0 .net *"_s5", 0 0, L_0x2df26b0; 1 drivers +v0x2c543f0_0 .net *"_s6", 0 0, L_0x2df28e0; 1 drivers +v0x2c544d0_0 .net "in", 3 0, L_0x2df2fe0; 1 drivers +v0x2c54640_0 .net "ors", 1 0, L_0x2df27f0; 1 drivers +v0x2c54720_0 .net "out", 0 0, L_0x2df2cd0; 1 drivers +L_0x2df2550 .part L_0x2df2fe0, 0, 1; +L_0x2df26b0 .part L_0x2df2fe0, 1, 1; +L_0x2df27f0 .concat8 [ 1 1 0 0], L_0x2df2490, L_0x2df28e0; +L_0x2df29f0 .part L_0x2df2fe0, 2, 1; +L_0x2df2b50 .part L_0x2df2fe0, 3, 1; +L_0x2df2d40 .part L_0x2df27f0, 0, 1; +L_0x2df2ef0 .part L_0x2df27f0, 1, 1; +S_0x2c54840 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c53970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1302880/d .functor OR 1, L_0x13028f0, L_0x1302a50, C4<0>, C4<0>; -L_0x1302880 .delay 1 (30000,30000,30000) L_0x1302880/d; -L_0x1302c80/d .functor OR 1, L_0x1302d90, L_0x1302ef0, C4<0>, C4<0>; -L_0x1302c80 .delay 1 (30000,30000,30000) L_0x1302c80/d; -L_0x1303070/d .functor OR 1, L_0x13030e0, L_0x1303290, C4<0>, C4<0>; -L_0x1303070 .delay 1 (30000,30000,30000) L_0x1303070/d; -v0x117dfb0_0 .net *"_s0", 0 0, L_0x1302880; 1 drivers -v0x117e0b0_0 .net *"_s10", 0 0, L_0x1302d90; 1 drivers -v0x117e190_0 .net *"_s12", 0 0, L_0x1302ef0; 1 drivers -v0x117e250_0 .net *"_s14", 0 0, L_0x13030e0; 1 drivers -v0x117e330_0 .net *"_s16", 0 0, L_0x1303290; 1 drivers -v0x117e460_0 .net *"_s3", 0 0, L_0x13028f0; 1 drivers -v0x117e540_0 .net *"_s5", 0 0, L_0x1302a50; 1 drivers -v0x117e620_0 .net *"_s6", 0 0, L_0x1302c80; 1 drivers -v0x117e700_0 .net "in", 3 0, L_0x13034c0; 1 drivers -v0x117e870_0 .net "ors", 1 0, L_0x1302b90; 1 drivers -v0x117e950_0 .net "out", 0 0, L_0x1303070; 1 drivers -L_0x13028f0 .part L_0x13034c0, 0, 1; -L_0x1302a50 .part L_0x13034c0, 1, 1; -L_0x1302b90 .concat8 [ 1 1 0 0], L_0x1302880, L_0x1302c80; -L_0x1302d90 .part L_0x13034c0, 2, 1; -L_0x1302ef0 .part L_0x13034c0, 3, 1; -L_0x13030e0 .part L_0x1302b90, 0, 1; -L_0x1303290 .part L_0x1302b90, 1, 1; -S_0x117f260 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1178390; +L_0x2df3110/d .functor OR 1, L_0x2df3180, L_0x2df32e0, C4<0>, C4<0>; +L_0x2df3110 .delay 1 (30000,30000,30000) L_0x2df3110/d; +L_0x2df3510/d .functor OR 1, L_0x2df3620, L_0x2df3780, C4<0>, C4<0>; +L_0x2df3510 .delay 1 (30000,30000,30000) L_0x2df3510/d; +L_0x2df3900/d .functor OR 1, L_0x2df3970, L_0x2df3b20, C4<0>, C4<0>; +L_0x2df3900 .delay 1 (30000,30000,30000) L_0x2df3900/d; +v0x2c54a00_0 .net *"_s0", 0 0, L_0x2df3110; 1 drivers +v0x2c54b00_0 .net *"_s10", 0 0, L_0x2df3620; 1 drivers +v0x2c54be0_0 .net *"_s12", 0 0, L_0x2df3780; 1 drivers +v0x2c54ca0_0 .net *"_s14", 0 0, L_0x2df3970; 1 drivers +v0x2c54d80_0 .net *"_s16", 0 0, L_0x2df3b20; 1 drivers +v0x2c54eb0_0 .net *"_s3", 0 0, L_0x2df3180; 1 drivers +v0x2c54f90_0 .net *"_s5", 0 0, L_0x2df32e0; 1 drivers +v0x2c55070_0 .net *"_s6", 0 0, L_0x2df3510; 1 drivers +v0x2c55150_0 .net "in", 3 0, L_0x2df3d50; 1 drivers +v0x2c552c0_0 .net "ors", 1 0, L_0x2df3420; 1 drivers +v0x2c553a0_0 .net "out", 0 0, L_0x2df3900; 1 drivers +L_0x2df3180 .part L_0x2df3d50, 0, 1; +L_0x2df32e0 .part L_0x2df3d50, 1, 1; +L_0x2df3420 .concat8 [ 1 1 0 0], L_0x2df3110, L_0x2df3510; +L_0x2df3620 .part L_0x2df3d50, 2, 1; +L_0x2df3780 .part L_0x2df3d50, 3, 1; +L_0x2df3970 .part L_0x2df3420, 0, 1; +L_0x2df3b20 .part L_0x2df3420, 1, 1; +S_0x2c55cb0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c4ede0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1184690_0 .net "ands", 7 0, L_0x12fda90; 1 drivers -v0x11847a0_0 .net "in", 7 0, L_0x12fbef0; alias, 1 drivers -v0x1184860_0 .net "out", 0 0, L_0x12ffa90; alias, 1 drivers -v0x1184930_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x117f4b0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x117f260; +v0x2c5b0e0_0 .net "ands", 7 0, L_0x2dee3b0; 1 drivers +v0x2c5b1f0_0 .net "in", 7 0, L_0x2dec390; alias, 1 drivers +v0x2c5b2b0_0 .net "out", 0 0, L_0x2df03b0; alias, 1 drivers +v0x2c5b380_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c55f00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c55cb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1181bf0_0 .net "A", 7 0, L_0x12fbef0; alias, 1 drivers -v0x1181cf0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1181db0_0 .net *"_s0", 0 0, L_0x12fc280; 1 drivers -v0x1181e70_0 .net *"_s12", 0 0, L_0x12fcc40; 1 drivers -v0x1181f50_0 .net *"_s16", 0 0, L_0x12fcfa0; 1 drivers -v0x1182080_0 .net *"_s20", 0 0, L_0x12fd3d0; 1 drivers -v0x1182160_0 .net *"_s24", 0 0, L_0x12fd700; 1 drivers -v0x1182240_0 .net *"_s28", 0 0, L_0x12fd690; 1 drivers -v0x1182320_0 .net *"_s4", 0 0, L_0x12fc620; 1 drivers -v0x1182490_0 .net *"_s8", 0 0, L_0x12fc930; 1 drivers -v0x1182570_0 .net "out", 7 0, L_0x12fda90; alias, 1 drivers -L_0x12fc390 .part L_0x12fbef0, 0, 1; -L_0x12fc580 .part v0x12010b0_0, 0, 1; -L_0x12fc6e0 .part L_0x12fbef0, 1, 1; -L_0x12fc840 .part v0x12010b0_0, 1, 1; -L_0x12fc9f0 .part L_0x12fbef0, 2, 1; -L_0x12fcb50 .part v0x12010b0_0, 2, 1; -L_0x12fcd00 .part L_0x12fbef0, 3, 1; -L_0x12fce60 .part v0x12010b0_0, 3, 1; -L_0x12fd060 .part L_0x12fbef0, 4, 1; -L_0x12fd2d0 .part v0x12010b0_0, 4, 1; -L_0x12fd440 .part L_0x12fbef0, 5, 1; -L_0x12fd5a0 .part v0x12010b0_0, 5, 1; -L_0x12fd7c0 .part L_0x12fbef0, 6, 1; -L_0x12fd920 .part v0x12010b0_0, 6, 1; -LS_0x12fda90_0_0 .concat8 [ 1 1 1 1], L_0x12fc280, L_0x12fc620, L_0x12fc930, L_0x12fcc40; -LS_0x12fda90_0_4 .concat8 [ 1 1 1 1], L_0x12fcfa0, L_0x12fd3d0, L_0x12fd700, L_0x12fd690; -L_0x12fda90 .concat8 [ 4 4 0 0], LS_0x12fda90_0_0, LS_0x12fda90_0_4; -L_0x12fde50 .part L_0x12fbef0, 7, 1; -L_0x12fe040 .part v0x12010b0_0, 7, 1; -S_0x117f6f0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x117f900 .param/l "i" 0 4 54, +C4<00>; -L_0x12fc280/d .functor AND 1, L_0x12fc390, L_0x12fc580, C4<1>, C4<1>; -L_0x12fc280 .delay 1 (30000,30000,30000) L_0x12fc280/d; -v0x117f9e0_0 .net *"_s0", 0 0, L_0x12fc390; 1 drivers -v0x117fac0_0 .net *"_s1", 0 0, L_0x12fc580; 1 drivers -S_0x117fba0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x117fdb0 .param/l "i" 0 4 54, +C4<01>; -L_0x12fc620/d .functor AND 1, L_0x12fc6e0, L_0x12fc840, C4<1>, C4<1>; -L_0x12fc620 .delay 1 (30000,30000,30000) L_0x12fc620/d; -v0x117fe70_0 .net *"_s0", 0 0, L_0x12fc6e0; 1 drivers -v0x117ff50_0 .net *"_s1", 0 0, L_0x12fc840; 1 drivers -S_0x1180030 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x1180270 .param/l "i" 0 4 54, +C4<010>; -L_0x12fc930/d .functor AND 1, L_0x12fc9f0, L_0x12fcb50, C4<1>, C4<1>; -L_0x12fc930 .delay 1 (30000,30000,30000) L_0x12fc930/d; -v0x1180310_0 .net *"_s0", 0 0, L_0x12fc9f0; 1 drivers -v0x11803f0_0 .net *"_s1", 0 0, L_0x12fcb50; 1 drivers -S_0x11804d0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x11806e0 .param/l "i" 0 4 54, +C4<011>; -L_0x12fcc40/d .functor AND 1, L_0x12fcd00, L_0x12fce60, C4<1>, C4<1>; -L_0x12fcc40 .delay 1 (30000,30000,30000) L_0x12fcc40/d; -v0x11807a0_0 .net *"_s0", 0 0, L_0x12fcd00; 1 drivers -v0x1180880_0 .net *"_s1", 0 0, L_0x12fce60; 1 drivers -S_0x1180960 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x1180bc0 .param/l "i" 0 4 54, +C4<0100>; -L_0x12fcfa0/d .functor AND 1, L_0x12fd060, L_0x12fd2d0, C4<1>, C4<1>; -L_0x12fcfa0 .delay 1 (30000,30000,30000) L_0x12fcfa0/d; -v0x1180c80_0 .net *"_s0", 0 0, L_0x12fd060; 1 drivers -v0x1180d60_0 .net *"_s1", 0 0, L_0x12fd2d0; 1 drivers -S_0x1180e40 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x1181050 .param/l "i" 0 4 54, +C4<0101>; -L_0x12fd3d0/d .functor AND 1, L_0x12fd440, L_0x12fd5a0, C4<1>, C4<1>; -L_0x12fd3d0 .delay 1 (30000,30000,30000) L_0x12fd3d0/d; -v0x1181110_0 .net *"_s0", 0 0, L_0x12fd440; 1 drivers -v0x11811f0_0 .net *"_s1", 0 0, L_0x12fd5a0; 1 drivers -S_0x11812d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x11814e0 .param/l "i" 0 4 54, +C4<0110>; -L_0x12fd700/d .functor AND 1, L_0x12fd7c0, L_0x12fd920, C4<1>, C4<1>; -L_0x12fd700 .delay 1 (30000,30000,30000) L_0x12fd700/d; -v0x11815a0_0 .net *"_s0", 0 0, L_0x12fd7c0; 1 drivers -v0x1181680_0 .net *"_s1", 0 0, L_0x12fd920; 1 drivers -S_0x1181760 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x117f4b0; - .timescale -9 -12; -P_0x1181970 .param/l "i" 0 4 54, +C4<0111>; -L_0x12fd690/d .functor AND 1, L_0x12fde50, L_0x12fe040, C4<1>, C4<1>; -L_0x12fd690 .delay 1 (30000,30000,30000) L_0x12fd690/d; -v0x1181a30_0 .net *"_s0", 0 0, L_0x12fde50; 1 drivers -v0x1181b10_0 .net *"_s1", 0 0, L_0x12fe040; 1 drivers -S_0x11826d0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x117f260; +v0x2c58640_0 .net "A", 7 0, L_0x2dec390; alias, 1 drivers +v0x2c58740_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c58800_0 .net *"_s0", 0 0, L_0x2decc60; 1 drivers +v0x2c588c0_0 .net *"_s12", 0 0, L_0x2ded560; 1 drivers +v0x2c589a0_0 .net *"_s16", 0 0, L_0x2ded8c0; 1 drivers +v0x2c58ad0_0 .net *"_s20", 0 0, L_0x2dedcf0; 1 drivers +v0x2c58bb0_0 .net *"_s24", 0 0, L_0x2dee020; 1 drivers +v0x2c58c90_0 .net *"_s28", 0 0, L_0x2dedfb0; 1 drivers +v0x2c58d70_0 .net *"_s4", 0 0, L_0x2ded000; 1 drivers +v0x2c58ee0_0 .net *"_s8", 0 0, L_0x2ded250; 1 drivers +v0x2c58fc0_0 .net "out", 7 0, L_0x2dee3b0; alias, 1 drivers +L_0x2decd70 .part L_0x2dec390, 0, 1; +L_0x2decf60 .part v0x2cdd2e0_0, 0, 1; +L_0x2ded070 .part L_0x2dec390, 1, 1; +L_0x2ded160 .part v0x2cdd2e0_0, 1, 1; +L_0x2ded310 .part L_0x2dec390, 2, 1; +L_0x2ded470 .part v0x2cdd2e0_0, 2, 1; +L_0x2ded620 .part L_0x2dec390, 3, 1; +L_0x2ded780 .part v0x2cdd2e0_0, 3, 1; +L_0x2ded980 .part L_0x2dec390, 4, 1; +L_0x2dedbf0 .part v0x2cdd2e0_0, 4, 1; +L_0x2dedd60 .part L_0x2dec390, 5, 1; +L_0x2dedec0 .part v0x2cdd2e0_0, 5, 1; +L_0x2dee0e0 .part L_0x2dec390, 6, 1; +L_0x2dee240 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dee3b0_0_0 .concat8 [ 1 1 1 1], L_0x2decc60, L_0x2ded000, L_0x2ded250, L_0x2ded560; +LS_0x2dee3b0_0_4 .concat8 [ 1 1 1 1], L_0x2ded8c0, L_0x2dedcf0, L_0x2dee020, L_0x2dedfb0; +L_0x2dee3b0 .concat8 [ 4 4 0 0], LS_0x2dee3b0_0_0, LS_0x2dee3b0_0_4; +L_0x2dee770 .part L_0x2dec390, 7, 1; +L_0x2dee960 .part v0x2cdd2e0_0, 7, 1; +S_0x2c56140 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c56350 .param/l "i" 0 4 54, +C4<00>; +L_0x2decc60/d .functor AND 1, L_0x2decd70, L_0x2decf60, C4<1>, C4<1>; +L_0x2decc60 .delay 1 (30000,30000,30000) L_0x2decc60/d; +v0x2c56430_0 .net *"_s0", 0 0, L_0x2decd70; 1 drivers +v0x2c56510_0 .net *"_s1", 0 0, L_0x2decf60; 1 drivers +S_0x2c565f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c56800 .param/l "i" 0 4 54, +C4<01>; +L_0x2ded000/d .functor AND 1, L_0x2ded070, L_0x2ded160, C4<1>, C4<1>; +L_0x2ded000 .delay 1 (30000,30000,30000) L_0x2ded000/d; +v0x2c568c0_0 .net *"_s0", 0 0, L_0x2ded070; 1 drivers +v0x2c569a0_0 .net *"_s1", 0 0, L_0x2ded160; 1 drivers +S_0x2c56a80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c56cc0 .param/l "i" 0 4 54, +C4<010>; +L_0x2ded250/d .functor AND 1, L_0x2ded310, L_0x2ded470, C4<1>, C4<1>; +L_0x2ded250 .delay 1 (30000,30000,30000) L_0x2ded250/d; +v0x2c56d60_0 .net *"_s0", 0 0, L_0x2ded310; 1 drivers +v0x2c56e40_0 .net *"_s1", 0 0, L_0x2ded470; 1 drivers +S_0x2c56f20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c57130 .param/l "i" 0 4 54, +C4<011>; +L_0x2ded560/d .functor AND 1, L_0x2ded620, L_0x2ded780, C4<1>, C4<1>; +L_0x2ded560 .delay 1 (30000,30000,30000) L_0x2ded560/d; +v0x2c571f0_0 .net *"_s0", 0 0, L_0x2ded620; 1 drivers +v0x2c572d0_0 .net *"_s1", 0 0, L_0x2ded780; 1 drivers +S_0x2c573b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c57610 .param/l "i" 0 4 54, +C4<0100>; +L_0x2ded8c0/d .functor AND 1, L_0x2ded980, L_0x2dedbf0, C4<1>, C4<1>; +L_0x2ded8c0 .delay 1 (30000,30000,30000) L_0x2ded8c0/d; +v0x2c576d0_0 .net *"_s0", 0 0, L_0x2ded980; 1 drivers +v0x2c577b0_0 .net *"_s1", 0 0, L_0x2dedbf0; 1 drivers +S_0x2c57890 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c57aa0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dedcf0/d .functor AND 1, L_0x2dedd60, L_0x2dedec0, C4<1>, C4<1>; +L_0x2dedcf0 .delay 1 (30000,30000,30000) L_0x2dedcf0/d; +v0x2c57b60_0 .net *"_s0", 0 0, L_0x2dedd60; 1 drivers +v0x2c57c40_0 .net *"_s1", 0 0, L_0x2dedec0; 1 drivers +S_0x2c57d20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c57f30 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dee020/d .functor AND 1, L_0x2dee0e0, L_0x2dee240, C4<1>, C4<1>; +L_0x2dee020 .delay 1 (30000,30000,30000) L_0x2dee020/d; +v0x2c57ff0_0 .net *"_s0", 0 0, L_0x2dee0e0; 1 drivers +v0x2c580d0_0 .net *"_s1", 0 0, L_0x2dee240; 1 drivers +S_0x2c581b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c55f00; + .timescale -9 -12; +P_0x2c583c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dedfb0/d .functor AND 1, L_0x2dee770, L_0x2dee960, C4<1>, C4<1>; +L_0x2dedfb0 .delay 1 (30000,30000,30000) L_0x2dedfb0/d; +v0x2c58480_0 .net *"_s0", 0 0, L_0x2dee770; 1 drivers +v0x2c58560_0 .net *"_s1", 0 0, L_0x2dee960; 1 drivers +S_0x2c59120 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c55cb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x12ffa90/d .functor OR 1, L_0x12ffb50, L_0x12ffd00, C4<0>, C4<0>; -L_0x12ffa90 .delay 1 (30000,30000,30000) L_0x12ffa90/d; -v0x1184220_0 .net *"_s10", 0 0, L_0x12ffb50; 1 drivers -v0x1184300_0 .net *"_s12", 0 0, L_0x12ffd00; 1 drivers -v0x11843e0_0 .net "in", 7 0, L_0x12fda90; alias, 1 drivers -v0x11844b0_0 .net "ors", 1 0, L_0x12ff8b0; 1 drivers -v0x1184570_0 .net "out", 0 0, L_0x12ffa90; alias, 1 drivers -L_0x12fec80 .part L_0x12fda90, 0, 4; -L_0x12ff8b0 .concat8 [ 1 1 0 0], L_0x12fe970, L_0x12ff5a0; -L_0x12ff9f0 .part L_0x12fda90, 4, 4; -L_0x12ffb50 .part L_0x12ff8b0, 0, 1; -L_0x12ffd00 .part L_0x12ff8b0, 1, 1; -S_0x1182890 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11826d0; +L_0x2df03b0/d .functor OR 1, L_0x2df0470, L_0x2df0620, C4<0>, C4<0>; +L_0x2df03b0 .delay 1 (30000,30000,30000) L_0x2df03b0/d; +v0x2c5ac70_0 .net *"_s10", 0 0, L_0x2df0470; 1 drivers +v0x2c5ad50_0 .net *"_s12", 0 0, L_0x2df0620; 1 drivers +v0x2c5ae30_0 .net "in", 7 0, L_0x2dee3b0; alias, 1 drivers +v0x2c5af00_0 .net "ors", 1 0, L_0x2df01d0; 1 drivers +v0x2c5afc0_0 .net "out", 0 0, L_0x2df03b0; alias, 1 drivers +L_0x2def5a0 .part L_0x2dee3b0, 0, 4; +L_0x2df01d0 .concat8 [ 1 1 0 0], L_0x2def290, L_0x2defec0; +L_0x2df0310 .part L_0x2dee3b0, 4, 4; +L_0x2df0470 .part L_0x2df01d0, 0, 1; +L_0x2df0620 .part L_0x2df01d0, 1, 1; +S_0x2c592e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c59120; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12fe130/d .functor OR 1, L_0x12fe1f0, L_0x12fe350, C4<0>, C4<0>; -L_0x12fe130 .delay 1 (30000,30000,30000) L_0x12fe130/d; -L_0x12fe580/d .functor OR 1, L_0x12fe690, L_0x12fe7f0, C4<0>, C4<0>; -L_0x12fe580 .delay 1 (30000,30000,30000) L_0x12fe580/d; -L_0x12fe970/d .functor OR 1, L_0x12fe9e0, L_0x12feb90, C4<0>, C4<0>; -L_0x12fe970 .delay 1 (30000,30000,30000) L_0x12fe970/d; -v0x1182ae0_0 .net *"_s0", 0 0, L_0x12fe130; 1 drivers -v0x1182be0_0 .net *"_s10", 0 0, L_0x12fe690; 1 drivers -v0x1182cc0_0 .net *"_s12", 0 0, L_0x12fe7f0; 1 drivers -v0x1182d80_0 .net *"_s14", 0 0, L_0x12fe9e0; 1 drivers -v0x1182e60_0 .net *"_s16", 0 0, L_0x12feb90; 1 drivers -v0x1182f90_0 .net *"_s3", 0 0, L_0x12fe1f0; 1 drivers -v0x1183070_0 .net *"_s5", 0 0, L_0x12fe350; 1 drivers -v0x1183150_0 .net *"_s6", 0 0, L_0x12fe580; 1 drivers -v0x1183230_0 .net "in", 3 0, L_0x12fec80; 1 drivers -v0x11833a0_0 .net "ors", 1 0, L_0x12fe490; 1 drivers -v0x1183480_0 .net "out", 0 0, L_0x12fe970; 1 drivers -L_0x12fe1f0 .part L_0x12fec80, 0, 1; -L_0x12fe350 .part L_0x12fec80, 1, 1; -L_0x12fe490 .concat8 [ 1 1 0 0], L_0x12fe130, L_0x12fe580; -L_0x12fe690 .part L_0x12fec80, 2, 1; -L_0x12fe7f0 .part L_0x12fec80, 3, 1; -L_0x12fe9e0 .part L_0x12fe490, 0, 1; -L_0x12feb90 .part L_0x12fe490, 1, 1; -S_0x11835a0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11826d0; +L_0x2deea50/d .functor OR 1, L_0x2deeb10, L_0x2deec70, C4<0>, C4<0>; +L_0x2deea50 .delay 1 (30000,30000,30000) L_0x2deea50/d; +L_0x2deeea0/d .functor OR 1, L_0x2deefb0, L_0x2def110, C4<0>, C4<0>; +L_0x2deeea0 .delay 1 (30000,30000,30000) L_0x2deeea0/d; +L_0x2def290/d .functor OR 1, L_0x2def300, L_0x2def4b0, C4<0>, C4<0>; +L_0x2def290 .delay 1 (30000,30000,30000) L_0x2def290/d; +v0x2c59530_0 .net *"_s0", 0 0, L_0x2deea50; 1 drivers +v0x2c59630_0 .net *"_s10", 0 0, L_0x2deefb0; 1 drivers +v0x2c59710_0 .net *"_s12", 0 0, L_0x2def110; 1 drivers +v0x2c597d0_0 .net *"_s14", 0 0, L_0x2def300; 1 drivers +v0x2c598b0_0 .net *"_s16", 0 0, L_0x2def4b0; 1 drivers +v0x2c599e0_0 .net *"_s3", 0 0, L_0x2deeb10; 1 drivers +v0x2c59ac0_0 .net *"_s5", 0 0, L_0x2deec70; 1 drivers +v0x2c59ba0_0 .net *"_s6", 0 0, L_0x2deeea0; 1 drivers +v0x2c59c80_0 .net "in", 3 0, L_0x2def5a0; 1 drivers +v0x2c59df0_0 .net "ors", 1 0, L_0x2deedb0; 1 drivers +v0x2c59ed0_0 .net "out", 0 0, L_0x2def290; 1 drivers +L_0x2deeb10 .part L_0x2def5a0, 0, 1; +L_0x2deec70 .part L_0x2def5a0, 1, 1; +L_0x2deedb0 .concat8 [ 1 1 0 0], L_0x2deea50, L_0x2deeea0; +L_0x2deefb0 .part L_0x2def5a0, 2, 1; +L_0x2def110 .part L_0x2def5a0, 3, 1; +L_0x2def300 .part L_0x2deedb0, 0, 1; +L_0x2def4b0 .part L_0x2deedb0, 1, 1; +S_0x2c59ff0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c59120; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x12fedb0/d .functor OR 1, L_0x12fee20, L_0x12fef80, C4<0>, C4<0>; -L_0x12fedb0 .delay 1 (30000,30000,30000) L_0x12fedb0/d; -L_0x12ff1b0/d .functor OR 1, L_0x12ff2c0, L_0x12ff420, C4<0>, C4<0>; -L_0x12ff1b0 .delay 1 (30000,30000,30000) L_0x12ff1b0/d; -L_0x12ff5a0/d .functor OR 1, L_0x12ff610, L_0x12ff7c0, C4<0>, C4<0>; -L_0x12ff5a0 .delay 1 (30000,30000,30000) L_0x12ff5a0/d; -v0x1183760_0 .net *"_s0", 0 0, L_0x12fedb0; 1 drivers -v0x1183860_0 .net *"_s10", 0 0, L_0x12ff2c0; 1 drivers -v0x1183940_0 .net *"_s12", 0 0, L_0x12ff420; 1 drivers -v0x1183a00_0 .net *"_s14", 0 0, L_0x12ff610; 1 drivers -v0x1183ae0_0 .net *"_s16", 0 0, L_0x12ff7c0; 1 drivers -v0x1183c10_0 .net *"_s3", 0 0, L_0x12fee20; 1 drivers -v0x1183cf0_0 .net *"_s5", 0 0, L_0x12fef80; 1 drivers -v0x1183dd0_0 .net *"_s6", 0 0, L_0x12ff1b0; 1 drivers -v0x1183eb0_0 .net "in", 3 0, L_0x12ff9f0; 1 drivers -v0x1184020_0 .net "ors", 1 0, L_0x12ff0c0; 1 drivers -v0x1184100_0 .net "out", 0 0, L_0x12ff5a0; 1 drivers -L_0x12fee20 .part L_0x12ff9f0, 0, 1; -L_0x12fef80 .part L_0x12ff9f0, 1, 1; -L_0x12ff0c0 .concat8 [ 1 1 0 0], L_0x12fedb0, L_0x12ff1b0; -L_0x12ff2c0 .part L_0x12ff9f0, 2, 1; -L_0x12ff420 .part L_0x12ff9f0, 3, 1; -L_0x12ff610 .part L_0x12ff0c0, 0, 1; -L_0x12ff7c0 .part L_0x12ff0c0, 1, 1; -S_0x1096810 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1178390; +L_0x2def6d0/d .functor OR 1, L_0x2def740, L_0x2def8a0, C4<0>, C4<0>; +L_0x2def6d0 .delay 1 (30000,30000,30000) L_0x2def6d0/d; +L_0x2defad0/d .functor OR 1, L_0x2defbe0, L_0x2defd40, C4<0>, C4<0>; +L_0x2defad0 .delay 1 (30000,30000,30000) L_0x2defad0/d; +L_0x2defec0/d .functor OR 1, L_0x2deff30, L_0x2df00e0, C4<0>, C4<0>; +L_0x2defec0 .delay 1 (30000,30000,30000) L_0x2defec0/d; +v0x2c5a1b0_0 .net *"_s0", 0 0, L_0x2def6d0; 1 drivers +v0x2c5a2b0_0 .net *"_s10", 0 0, L_0x2defbe0; 1 drivers +v0x2c5a390_0 .net *"_s12", 0 0, L_0x2defd40; 1 drivers +v0x2c5a450_0 .net *"_s14", 0 0, L_0x2deff30; 1 drivers +v0x2c5a530_0 .net *"_s16", 0 0, L_0x2df00e0; 1 drivers +v0x2c5a660_0 .net *"_s3", 0 0, L_0x2def740; 1 drivers +v0x2c5a740_0 .net *"_s5", 0 0, L_0x2def8a0; 1 drivers +v0x2c5a820_0 .net *"_s6", 0 0, L_0x2defad0; 1 drivers +v0x2c5a900_0 .net "in", 3 0, L_0x2df0310; 1 drivers +v0x2c5aa70_0 .net "ors", 1 0, L_0x2def9e0; 1 drivers +v0x2c5ab50_0 .net "out", 0 0, L_0x2defec0; 1 drivers +L_0x2def740 .part L_0x2df0310, 0, 1; +L_0x2def8a0 .part L_0x2df0310, 1, 1; +L_0x2def9e0 .concat8 [ 1 1 0 0], L_0x2def6d0, L_0x2defad0; +L_0x2defbe0 .part L_0x2df0310, 2, 1; +L_0x2defd40 .part L_0x2df0310, 3, 1; +L_0x2deff30 .part L_0x2def9e0, 0, 1; +L_0x2df00e0 .part L_0x2def9e0, 1, 1; +S_0x2b63c30 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c4ede0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -13910,80 +14718,80 @@ S_0x1096810 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1178390; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x12fb260/d .functor XNOR 1, L_0x13039c0, L_0x12f9f60, C4<0>, C4<0>; -L_0x12fb260 .delay 1 (20000,20000,20000) L_0x12fb260/d; -L_0x12fb4d0/d .functor AND 1, L_0x13039c0, L_0x12fa260, C4<1>, C4<1>; -L_0x12fb4d0 .delay 1 (30000,30000,30000) L_0x12fb4d0/d; -L_0x12fb540/d .functor AND 1, L_0x12fb260, L_0x12fa000, C4<1>, C4<1>; -L_0x12fb540 .delay 1 (30000,30000,30000) L_0x12fb540/d; -L_0x12fb6a0/d .functor OR 1, L_0x12fb540, L_0x12fb4d0, C4<0>, C4<0>; -L_0x12fb6a0 .delay 1 (30000,30000,30000) L_0x12fb6a0/d; -v0x1096ac0_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers -v0x1096bb0_0 .net "a_", 0 0, L_0x12f0420; alias, 1 drivers -v0x1096c70_0 .net "b", 0 0, L_0x12f9f60; alias, 1 drivers -v0x1096d60_0 .net "b_", 0 0, L_0x12fa260; alias, 1 drivers -v0x1096e00_0 .net "carryin", 0 0, L_0x12fa000; alias, 1 drivers -v0x1096f40_0 .net "eq", 0 0, L_0x12fb260; 1 drivers -v0x1185a00_0 .net "lt", 0 0, L_0x12fb4d0; 1 drivers -v0x1185ac0_0 .net "out", 0 0, L_0x12fb6a0; 1 drivers -v0x1185b80_0 .net "w0", 0 0, L_0x12fb540; 1 drivers -S_0x1185dd0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1178390; +L_0x2deb240/d .functor XNOR 1, L_0x2df4250, L_0x2de9c80, C4<0>, C4<0>; +L_0x2deb240 .delay 1 (20000,20000,20000) L_0x2deb240/d; +L_0x2deb3c0/d .functor AND 1, L_0x2df4250, L_0x2de9f30, C4<1>, C4<1>; +L_0x2deb3c0 .delay 1 (30000,30000,30000) L_0x2deb3c0/d; +L_0x2deb520/d .functor AND 1, L_0x2deb240, L_0x2de9d20, C4<1>, C4<1>; +L_0x2deb520 .delay 1 (30000,30000,30000) L_0x2deb520/d; +L_0x2deb630/d .functor OR 1, L_0x2deb520, L_0x2deb3c0, C4<0>, C4<0>; +L_0x2deb630 .delay 1 (30000,30000,30000) L_0x2deb630/d; +v0x2b63ee0_0 .net "a", 0 0, L_0x2df4250; alias, 1 drivers +v0x2b63fd0_0 .net "a_", 0 0, L_0x2ddf4e0; alias, 1 drivers +v0x2b64090_0 .net "b", 0 0, L_0x2de9c80; alias, 1 drivers +v0x2b64180_0 .net "b_", 0 0, L_0x2de9f30; alias, 1 drivers +v0x2b64220_0 .net "carryin", 0 0, L_0x2de9d20; alias, 1 drivers +v0x2b64360_0 .net "eq", 0 0, L_0x2deb240; 1 drivers +v0x2c5c450_0 .net "lt", 0 0, L_0x2deb3c0; 1 drivers +v0x2c5c510_0 .net "out", 0 0, L_0x2deb630; 1 drivers +v0x2c5c5d0_0 .net "w0", 0 0, L_0x2deb520; 1 drivers +S_0x2c5c820 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c4ede0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x12fb040/d .functor OR 1, L_0x12fab90, L_0x1187030, C4<0>, C4<0>; -L_0x12fb040 .delay 1 (30000,30000,30000) L_0x12fb040/d; -v0x1186bc0_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers -v0x1186d10_0 .net "b", 0 0, L_0x12fa260; alias, 1 drivers -v0x1186dd0_0 .net "c1", 0 0, L_0x12fab90; 1 drivers -v0x1186e70_0 .net "c2", 0 0, L_0x1187030; 1 drivers -v0x1186f40_0 .net "carryin", 0 0, L_0x12fa000; alias, 1 drivers -v0x11870c0_0 .net "carryout", 0 0, L_0x12fb040; 1 drivers -v0x1187160_0 .net "s1", 0 0, L_0x12faad0; 1 drivers -v0x1187200_0 .net "sum", 0 0, L_0x12facf0; 1 drivers -S_0x1186020 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1185dd0; +L_0x2deae20/d .functor OR 1, L_0x2dea920, L_0x2c5da80, C4<0>, C4<0>; +L_0x2deae20 .delay 1 (30000,30000,30000) L_0x2deae20/d; +v0x2c5d610_0 .net "a", 0 0, L_0x2df4250; alias, 1 drivers +v0x2c5d760_0 .net "b", 0 0, L_0x2de9f30; alias, 1 drivers +v0x2c5d820_0 .net "c1", 0 0, L_0x2dea920; 1 drivers +v0x2c5d8c0_0 .net "c2", 0 0, L_0x2c5da80; 1 drivers +v0x2c5d990_0 .net "carryin", 0 0, L_0x2de9d20; alias, 1 drivers +v0x2c5db10_0 .net "carryout", 0 0, L_0x2deae20; 1 drivers +v0x2c5dbb0_0 .net "s1", 0 0, L_0x2dea860; 1 drivers +v0x2c5dc50_0 .net "sum", 0 0, L_0x2deaa80; 1 drivers +S_0x2c5ca70 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c5c820; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12faad0/d .functor XOR 1, L_0x13039c0, L_0x12fa260, C4<0>, C4<0>; -L_0x12faad0 .delay 1 (30000,30000,30000) L_0x12faad0/d; -L_0x12fab90/d .functor AND 1, L_0x13039c0, L_0x12fa260, C4<1>, C4<1>; -L_0x12fab90 .delay 1 (30000,30000,30000) L_0x12fab90/d; -v0x1186280_0 .net "a", 0 0, L_0x13039c0; alias, 1 drivers -v0x1186340_0 .net "b", 0 0, L_0x12fa260; alias, 1 drivers -v0x1186400_0 .net "carryout", 0 0, L_0x12fab90; alias, 1 drivers -v0x11864a0_0 .net "sum", 0 0, L_0x12faad0; alias, 1 drivers -S_0x11865d0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1185dd0; +L_0x2dea860/d .functor XOR 1, L_0x2df4250, L_0x2de9f30, C4<0>, C4<0>; +L_0x2dea860 .delay 1 (30000,30000,30000) L_0x2dea860/d; +L_0x2dea920/d .functor AND 1, L_0x2df4250, L_0x2de9f30, C4<1>, C4<1>; +L_0x2dea920 .delay 1 (30000,30000,30000) L_0x2dea920/d; +v0x2c5ccd0_0 .net "a", 0 0, L_0x2df4250; alias, 1 drivers +v0x2c5cd90_0 .net "b", 0 0, L_0x2de9f30; alias, 1 drivers +v0x2c5ce50_0 .net "carryout", 0 0, L_0x2dea920; alias, 1 drivers +v0x2c5cef0_0 .net "sum", 0 0, L_0x2dea860; alias, 1 drivers +S_0x2c5d020 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c5c820; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x12facf0/d .functor XOR 1, L_0x12faad0, L_0x12fa000, C4<0>, C4<0>; -L_0x12facf0 .delay 1 (30000,30000,30000) L_0x12facf0/d; -L_0x1187030/d .functor AND 1, L_0x12faad0, L_0x12fa000, C4<1>, C4<1>; -L_0x1187030 .delay 1 (30000,30000,30000) L_0x1187030/d; -v0x1186830_0 .net "a", 0 0, L_0x12faad0; alias, 1 drivers -v0x1186900_0 .net "b", 0 0, L_0x12fa000; alias, 1 drivers -v0x11869a0_0 .net "carryout", 0 0, L_0x1187030; alias, 1 drivers -v0x1186a70_0 .net "sum", 0 0, L_0x12facf0; alias, 1 drivers -S_0x1188620 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11780c0; - .timescale -9 -12; -L_0x2b0ab3d06c38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06c80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1303a60/d .functor OR 1, L_0x2b0ab3d06c38, L_0x2b0ab3d06c80, C4<0>, C4<0>; -L_0x1303a60 .delay 1 (30000,30000,30000) L_0x1303a60/d; -v0x1188810_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06c38; 1 drivers -v0x11888f0_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06c80; 1 drivers -S_0x11889d0 .scope generate, "alu_slices[26]" "alu_slices[26]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1188be0 .param/l "i" 0 3 41, +C4<011010>; -S_0x1188ca0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11889d0; +L_0x2deaa80/d .functor XOR 1, L_0x2dea860, L_0x2de9d20, C4<0>, C4<0>; +L_0x2deaa80 .delay 1 (30000,30000,30000) L_0x2deaa80/d; +L_0x2c5da80/d .functor AND 1, L_0x2dea860, L_0x2de9d20, C4<1>, C4<1>; +L_0x2c5da80 .delay 1 (30000,30000,30000) L_0x2c5da80/d; +v0x2c5d280_0 .net "a", 0 0, L_0x2dea860; alias, 1 drivers +v0x2c5d350_0 .net "b", 0 0, L_0x2de9d20; alias, 1 drivers +v0x2c5d3f0_0 .net "carryout", 0 0, L_0x2c5da80; alias, 1 drivers +v0x2c5d4c0_0 .net "sum", 0 0, L_0x2deaa80; alias, 1 drivers +S_0x2c5fce0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c4eb10; + .timescale -9 -12; +L_0x2ac6110bc558 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc5a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dec6d0/d .functor OR 1, L_0x2ac6110bc558, L_0x2ac6110bc5a0, C4<0>, C4<0>; +L_0x2dec6d0 .delay 1 (30000,30000,30000) L_0x2dec6d0/d; +v0x2c5fed0_0 .net/2u *"_s0", 0 0, L_0x2ac6110bc558; 1 drivers +v0x2c5ffb0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bc5a0; 1 drivers +S_0x2c60090 .scope generate, "alu_slices[26]" "alu_slices[26]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c602a0 .param/l "i" 0 3 39, +C4<011010>; +S_0x2c60360 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c60090; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -13992,445 +14800,476 @@ S_0x1188ca0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11889d0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x12fa140/d .functor NOT 1, L_0x130d610, C4<0>, C4<0>, C4<0>; -L_0x12fa140 .delay 1 (10000,10000,10000) L_0x12fa140/d; -L_0x1303df0/d .functor NOT 1, L_0x130d770, C4<0>, C4<0>, C4<0>; -L_0x1303df0 .delay 1 (10000,10000,10000) L_0x1303df0/d; -L_0x1304df0/d .functor XOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; -L_0x1304df0 .delay 1 (30000,30000,30000) L_0x1304df0/d; -L_0x2b0ab3d06cc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06d10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x13054a0/d .functor OR 1, L_0x2b0ab3d06cc8, L_0x2b0ab3d06d10, C4<0>, C4<0>; -L_0x13054a0 .delay 1 (30000,30000,30000) L_0x13054a0/d; -L_0x13056a0/d .functor AND 1, L_0x130d610, L_0x130d770, C4<1>, C4<1>; -L_0x13056a0 .delay 1 (30000,30000,30000) L_0x13056a0/d; -L_0x1305760/d .functor NAND 1, L_0x130d610, L_0x130d770, C4<1>, C4<1>; -L_0x1305760 .delay 1 (20000,20000,20000) L_0x1305760/d; -L_0x13058c0/d .functor XOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; -L_0x13058c0 .delay 1 (20000,20000,20000) L_0x13058c0/d; -L_0x1305d70/d .functor OR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; -L_0x1305d70 .delay 1 (30000,30000,30000) L_0x1305d70/d; -L_0x130d510/d .functor NOT 1, L_0x13096e0, C4<0>, C4<0>, C4<0>; -L_0x130d510 .delay 1 (10000,10000,10000) L_0x130d510/d; -v0x11973d0_0 .net "A", 0 0, L_0x130d610; 1 drivers -v0x1197490_0 .net "A_", 0 0, L_0x12fa140; 1 drivers -v0x1197550_0 .net "B", 0 0, L_0x130d770; 1 drivers -v0x1197620_0 .net "B_", 0 0, L_0x1303df0; 1 drivers -v0x11976c0_0 .net *"_s12", 0 0, L_0x13054a0; 1 drivers -v0x11977b0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06cc8; 1 drivers -v0x1197870_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06d10; 1 drivers -v0x1197950_0 .net *"_s18", 0 0, L_0x13056a0; 1 drivers -v0x1197a30_0 .net *"_s20", 0 0, L_0x1305760; 1 drivers -v0x1197ba0_0 .net *"_s22", 0 0, L_0x13058c0; 1 drivers -v0x1197c80_0 .net *"_s24", 0 0, L_0x1305d70; 1 drivers -o0x2b0ab3ce2ce8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x1197d60_0 name=_s30 -o0x2b0ab3ce2d18 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x1197e40_0 name=_s32 -v0x1197f20_0 .net *"_s8", 0 0, L_0x1304df0; 1 drivers -v0x1198000_0 .net "carryin", 0 0, L_0x1303b20; 1 drivers -v0x11980a0_0 .net "carryout", 0 0, L_0x130d1b0; 1 drivers -v0x1198140_0 .net "carryouts", 7 0, L_0x1355b40; 1 drivers -v0x11982f0_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x1198390_0 .net "result", 0 0, L_0x13096e0; 1 drivers -v0x1198480_0 .net "results", 7 0, L_0x1305b40; 1 drivers -v0x1198590_0 .net "zero", 0 0, L_0x130d510; 1 drivers -LS_0x1305b40_0_0 .concat8 [ 1 1 1 1], L_0x1304310, L_0x1304940, L_0x1304df0, L_0x13054a0; -LS_0x1305b40_0_4 .concat8 [ 1 1 1 1], L_0x13056a0, L_0x1305760, L_0x13058c0, L_0x1305d70; -L_0x1305b40 .concat8 [ 4 4 0 0], LS_0x1305b40_0_0, LS_0x1305b40_0_4; -LS_0x1355b40_0_0 .concat [ 1 1 1 1], L_0x13045c0, L_0x1304c90, o0x2b0ab3ce2ce8, L_0x13052f0; -LS_0x1355b40_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce2d18; -L_0x1355b40 .concat [ 4 4 0 0], LS_0x1355b40_0_0, LS_0x1355b40_0_4; -S_0x1188f20 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1188ca0; +L_0x2de9e60/d .functor NOT 1, L_0x2dfea80, C4<0>, C4<0>, C4<0>; +L_0x2de9e60 .delay 1 (10000,10000,10000) L_0x2de9e60/d; +L_0x2df46d0/d .functor NOT 1, L_0x2dfebe0, C4<0>, C4<0>, C4<0>; +L_0x2df46d0 .delay 1 (10000,10000,10000) L_0x2df46d0/d; +L_0x2df56d0/d .functor XOR 1, L_0x2dfea80, L_0x2dfebe0, C4<0>, C4<0>; +L_0x2df56d0 .delay 1 (30000,30000,30000) L_0x2df56d0/d; +L_0x2ac6110bc5e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc630 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df5790/d .functor OR 1, L_0x2ac6110bc5e8, L_0x2ac6110bc630, C4<0>, C4<0>; +L_0x2df5790 .delay 1 (30000,30000,30000) L_0x2df5790/d; +L_0x2ac6110bc678 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc6c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df5f30/d .functor OR 1, L_0x2ac6110bc678, L_0x2ac6110bc6c0, C4<0>, C4<0>; +L_0x2df5f30 .delay 1 (30000,30000,30000) L_0x2df5f30/d; +L_0x2df6130/d .functor AND 1, L_0x2dfea80, L_0x2dfebe0, C4<1>, C4<1>; +L_0x2df6130 .delay 1 (30000,30000,30000) L_0x2df6130/d; +L_0x2ac6110bc708 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc750 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df61f0/d .functor OR 1, L_0x2ac6110bc708, L_0x2ac6110bc750, C4<0>, C4<0>; +L_0x2df61f0 .delay 1 (30000,30000,30000) L_0x2df61f0/d; +L_0x2df63f0/d .functor NAND 1, L_0x2dfea80, L_0x2dfebe0, C4<1>, C4<1>; +L_0x2df63f0 .delay 1 (20000,20000,20000) L_0x2df63f0/d; +L_0x2ac6110bc798 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc7e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df6500/d .functor OR 1, L_0x2ac6110bc798, L_0x2ac6110bc7e0, C4<0>, C4<0>; +L_0x2df6500 .delay 1 (30000,30000,30000) L_0x2df6500/d; +L_0x2df66b0/d .functor NOR 1, L_0x2dfea80, L_0x2dfebe0, C4<0>, C4<0>; +L_0x2df66b0 .delay 1 (20000,20000,20000) L_0x2df66b0/d; +L_0x2ac6110bc828 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc870 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df6980/d .functor OR 1, L_0x2ac6110bc828, L_0x2ac6110bc870, C4<0>, C4<0>; +L_0x2df6980 .delay 1 (30000,30000,30000) L_0x2df6980/d; +L_0x2df6d80/d .functor OR 1, L_0x2dfea80, L_0x2dfebe0, C4<0>, C4<0>; +L_0x2df6d80 .delay 1 (30000,30000,30000) L_0x2df6d80/d; +L_0x2ac6110bc8b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc900 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df7220/d .functor OR 1, L_0x2ac6110bc8b8, L_0x2ac6110bc900, C4<0>, C4<0>; +L_0x2df7220 .delay 1 (30000,30000,30000) L_0x2df7220/d; +L_0x2dfe980/d .functor NOT 1, L_0x2dfabe0, C4<0>, C4<0>, C4<0>; +L_0x2dfe980 .delay 1 (10000,10000,10000) L_0x2dfe980/d; +v0x2c6ea90_0 .net "A", 0 0, L_0x2dfea80; 1 drivers +v0x2c6eb50_0 .net "A_", 0 0, L_0x2de9e60; 1 drivers +v0x2c6ec10_0 .net "B", 0 0, L_0x2dfebe0; 1 drivers +v0x2c6ece0_0 .net "B_", 0 0, L_0x2df46d0; 1 drivers +v0x2c6ed80_0 .net *"_s11", 0 0, L_0x2df5790; 1 drivers +v0x2c6ee70_0 .net/2s *"_s13", 0 0, L_0x2ac6110bc5e8; 1 drivers +v0x2c6ef30_0 .net/2s *"_s15", 0 0, L_0x2ac6110bc630; 1 drivers +v0x2c6f010_0 .net *"_s19", 0 0, L_0x2df5f30; 1 drivers +v0x2c6f0f0_0 .net/2s *"_s21", 0 0, L_0x2ac6110bc678; 1 drivers +v0x2c6f260_0 .net/2s *"_s23", 0 0, L_0x2ac6110bc6c0; 1 drivers +v0x2c6f340_0 .net *"_s25", 0 0, L_0x2df6130; 1 drivers +v0x2c6f420_0 .net *"_s28", 0 0, L_0x2df61f0; 1 drivers +v0x2c6f500_0 .net/2s *"_s30", 0 0, L_0x2ac6110bc708; 1 drivers +v0x2c6f5e0_0 .net/2s *"_s32", 0 0, L_0x2ac6110bc750; 1 drivers +v0x2c6f6c0_0 .net *"_s34", 0 0, L_0x2df63f0; 1 drivers +v0x2c6f7a0_0 .net *"_s37", 0 0, L_0x2df6500; 1 drivers +v0x2c6f880_0 .net/2s *"_s39", 0 0, L_0x2ac6110bc798; 1 drivers +v0x2c6fa30_0 .net/2s *"_s41", 0 0, L_0x2ac6110bc7e0; 1 drivers +v0x2c6fad0_0 .net *"_s43", 0 0, L_0x2df66b0; 1 drivers +v0x2c6fbb0_0 .net *"_s46", 0 0, L_0x2df6980; 1 drivers +v0x2c6fc90_0 .net/2s *"_s48", 0 0, L_0x2ac6110bc828; 1 drivers +v0x2c6fd70_0 .net/2s *"_s50", 0 0, L_0x2ac6110bc870; 1 drivers +v0x2c6fe50_0 .net *"_s52", 0 0, L_0x2df6d80; 1 drivers +v0x2c6ff30_0 .net *"_s56", 0 0, L_0x2df7220; 1 drivers +v0x2c70010_0 .net/2s *"_s59", 0 0, L_0x2ac6110bc8b8; 1 drivers +v0x2c700f0_0 .net/2s *"_s61", 0 0, L_0x2ac6110bc900; 1 drivers +v0x2c701d0_0 .net *"_s8", 0 0, L_0x2df56d0; 1 drivers +v0x2c702b0_0 .net "carryin", 0 0, L_0x2df43b0; 1 drivers +v0x2c70350_0 .net "carryout", 0 0, L_0x2dfe620; 1 drivers +v0x2c703f0_0 .net "carryouts", 7 0, L_0x2df6e90; 1 drivers +v0x2c70500_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c705c0_0 .net "result", 0 0, L_0x2dfabe0; 1 drivers +v0x2c706b0_0 .net "results", 7 0, L_0x2df6b50; 1 drivers +v0x2c6f990_0 .net "zero", 0 0, L_0x2dfe980; 1 drivers +LS_0x2df6b50_0_0 .concat8 [ 1 1 1 1], L_0x2df4bf0, L_0x2df5220, L_0x2df56d0, L_0x2df5f30; +LS_0x2df6b50_0_4 .concat8 [ 1 1 1 1], L_0x2df6130, L_0x2df63f0, L_0x2df66b0, L_0x2df6d80; +L_0x2df6b50 .concat8 [ 4 4 0 0], LS_0x2df6b50_0_0, LS_0x2df6b50_0_4; +LS_0x2df6e90_0_0 .concat8 [ 1 1 1 1], L_0x2df4ea0, L_0x2df5570, L_0x2df5790, L_0x2df5d80; +LS_0x2df6e90_0_4 .concat8 [ 1 1 1 1], L_0x2df61f0, L_0x2df6500, L_0x2df6980, L_0x2df7220; +L_0x2df6e90 .concat8 [ 4 4 0 0], LS_0x2df6e90_0_0, LS_0x2df6e90_0_4; +S_0x2c605e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c60360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x13045c0/d .functor OR 1, L_0x13040a0, L_0x1304460, C4<0>, C4<0>; -L_0x13045c0 .delay 1 (30000,30000,30000) L_0x13045c0/d; -v0x1189d50_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers -v0x1189e10_0 .net "b", 0 0, L_0x130d770; alias, 1 drivers -v0x1189ee0_0 .net "c1", 0 0, L_0x13040a0; 1 drivers -v0x1189fe0_0 .net "c2", 0 0, L_0x1304460; 1 drivers -v0x118a0b0_0 .net "carryin", 0 0, L_0x1303b20; alias, 1 drivers -v0x118a1a0_0 .net "carryout", 0 0, L_0x13045c0; 1 drivers -v0x118a240_0 .net "s1", 0 0, L_0x1303fe0; 1 drivers -v0x118a330_0 .net "sum", 0 0, L_0x1304310; 1 drivers -S_0x1189190 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1188f20; +L_0x2df4ea0/d .functor OR 1, L_0x2df4980, L_0x2df4d40, C4<0>, C4<0>; +L_0x2df4ea0 .delay 1 (30000,30000,30000) L_0x2df4ea0/d; +v0x2c61410_0 .net "a", 0 0, L_0x2dfea80; alias, 1 drivers +v0x2c614d0_0 .net "b", 0 0, L_0x2dfebe0; alias, 1 drivers +v0x2c615a0_0 .net "c1", 0 0, L_0x2df4980; 1 drivers +v0x2c616a0_0 .net "c2", 0 0, L_0x2df4d40; 1 drivers +v0x2c61770_0 .net "carryin", 0 0, L_0x2df43b0; alias, 1 drivers +v0x2c61860_0 .net "carryout", 0 0, L_0x2df4ea0; 1 drivers +v0x2c61900_0 .net "s1", 0 0, L_0x2df48c0; 1 drivers +v0x2c619f0_0 .net "sum", 0 0, L_0x2df4bf0; 1 drivers +S_0x2c60850 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c605e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1303fe0/d .functor XOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; -L_0x1303fe0 .delay 1 (30000,30000,30000) L_0x1303fe0/d; -L_0x13040a0/d .functor AND 1, L_0x130d610, L_0x130d770, C4<1>, C4<1>; -L_0x13040a0 .delay 1 (30000,30000,30000) L_0x13040a0/d; -v0x11893f0_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers -v0x11894d0_0 .net "b", 0 0, L_0x130d770; alias, 1 drivers -v0x1189590_0 .net "carryout", 0 0, L_0x13040a0; alias, 1 drivers -v0x1189630_0 .net "sum", 0 0, L_0x1303fe0; alias, 1 drivers -S_0x1189770 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1188f20; +L_0x2df48c0/d .functor XOR 1, L_0x2dfea80, L_0x2dfebe0, C4<0>, C4<0>; +L_0x2df48c0 .delay 1 (30000,30000,30000) L_0x2df48c0/d; +L_0x2df4980/d .functor AND 1, L_0x2dfea80, L_0x2dfebe0, C4<1>, C4<1>; +L_0x2df4980 .delay 1 (30000,30000,30000) L_0x2df4980/d; +v0x2c60ab0_0 .net "a", 0 0, L_0x2dfea80; alias, 1 drivers +v0x2c60b90_0 .net "b", 0 0, L_0x2dfebe0; alias, 1 drivers +v0x2c60c50_0 .net "carryout", 0 0, L_0x2df4980; alias, 1 drivers +v0x2c60cf0_0 .net "sum", 0 0, L_0x2df48c0; alias, 1 drivers +S_0x2c60e30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c605e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1304310/d .functor XOR 1, L_0x1303fe0, L_0x1303b20, C4<0>, C4<0>; -L_0x1304310 .delay 1 (30000,30000,30000) L_0x1304310/d; -L_0x1304460/d .functor AND 1, L_0x1303fe0, L_0x1303b20, C4<1>, C4<1>; -L_0x1304460 .delay 1 (30000,30000,30000) L_0x1304460/d; -v0x11899d0_0 .net "a", 0 0, L_0x1303fe0; alias, 1 drivers -v0x1189a70_0 .net "b", 0 0, L_0x1303b20; alias, 1 drivers -v0x1189b10_0 .net "carryout", 0 0, L_0x1304460; alias, 1 drivers -v0x1189be0_0 .net "sum", 0 0, L_0x1304310; alias, 1 drivers -S_0x118a400 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1188ca0; +L_0x2df4bf0/d .functor XOR 1, L_0x2df48c0, L_0x2df43b0, C4<0>, C4<0>; +L_0x2df4bf0 .delay 1 (30000,30000,30000) L_0x2df4bf0/d; +L_0x2df4d40/d .functor AND 1, L_0x2df48c0, L_0x2df43b0, C4<1>, C4<1>; +L_0x2df4d40 .delay 1 (30000,30000,30000) L_0x2df4d40/d; +v0x2c61090_0 .net "a", 0 0, L_0x2df48c0; alias, 1 drivers +v0x2c61130_0 .net "b", 0 0, L_0x2df43b0; alias, 1 drivers +v0x2c611d0_0 .net "carryout", 0 0, L_0x2df4d40; alias, 1 drivers +v0x2c612a0_0 .net "sum", 0 0, L_0x2df4bf0; alias, 1 drivers +S_0x2c61ac0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c60360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x118f7f0_0 .net "ands", 7 0, L_0x130b1b0; 1 drivers -v0x118f900_0 .net "in", 7 0, L_0x1355b40; alias, 1 drivers -v0x118f9c0_0 .net "out", 0 0, L_0x130d1b0; alias, 1 drivers -v0x118fa90_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x118a620 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x118a400; +v0x2c66eb0_0 .net "ands", 7 0, L_0x2dfc620; 1 drivers +v0x2c66fc0_0 .net "in", 7 0, L_0x2df6e90; alias, 1 drivers +v0x2c67080_0 .net "out", 0 0, L_0x2dfe620; alias, 1 drivers +v0x2c67150_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c61ce0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c61ac0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x118cd50_0 .net "A", 7 0, L_0x1355b40; alias, 1 drivers -v0x118ce50_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x118cf10_0 .net *"_s0", 0 0, L_0x1309a40; 1 drivers -v0x118cfd0_0 .net *"_s12", 0 0, L_0x130a3b0; 1 drivers -v0x118d0b0_0 .net *"_s16", 0 0, L_0x130a710; 1 drivers -v0x118d1e0_0 .net *"_s20", 0 0, L_0x130aa80; 1 drivers -v0x118d2c0_0 .net *"_s24", 0 0, L_0x130aea0; 1 drivers -v0x118d3a0_0 .net *"_s28", 0 0, L_0x130ae30; 1 drivers -v0x118d480_0 .net *"_s4", 0 0, L_0x1309d50; 1 drivers -v0x118d5f0_0 .net *"_s8", 0 0, L_0x130a0a0; 1 drivers -v0x118d6d0_0 .net "out", 7 0, L_0x130b1b0; alias, 1 drivers -L_0x1309b00 .part L_0x1355b40, 0, 1; -L_0x1309c60 .part v0x12010b0_0, 0, 1; -L_0x1309e10 .part L_0x1355b40, 1, 1; -L_0x130a000 .part v0x12010b0_0, 1, 1; -L_0x130a160 .part L_0x1355b40, 2, 1; -L_0x130a2c0 .part v0x12010b0_0, 2, 1; -L_0x130a470 .part L_0x1355b40, 3, 1; -L_0x130a5d0 .part v0x12010b0_0, 3, 1; -L_0x130a830 .part L_0x1355b40, 4, 1; -L_0x130a990 .part v0x12010b0_0, 4, 1; -L_0x130ab20 .part L_0x1355b40, 5, 1; -L_0x130ad90 .part v0x12010b0_0, 5, 1; -L_0x130af60 .part L_0x1355b40, 6, 1; -L_0x130b0c0 .part v0x12010b0_0, 6, 1; -LS_0x130b1b0_0_0 .concat8 [ 1 1 1 1], L_0x1309a40, L_0x1309d50, L_0x130a0a0, L_0x130a3b0; -LS_0x130b1b0_0_4 .concat8 [ 1 1 1 1], L_0x130a710, L_0x130aa80, L_0x130aea0, L_0x130ae30; -L_0x130b1b0 .concat8 [ 4 4 0 0], LS_0x130b1b0_0_0, LS_0x130b1b0_0_4; -L_0x130b570 .part L_0x1355b40, 7, 1; -L_0x130b760 .part v0x12010b0_0, 7, 1; -S_0x118a880 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118aa90 .param/l "i" 0 4 54, +C4<00>; -L_0x1309a40/d .functor AND 1, L_0x1309b00, L_0x1309c60, C4<1>, C4<1>; -L_0x1309a40 .delay 1 (30000,30000,30000) L_0x1309a40/d; -v0x118ab70_0 .net *"_s0", 0 0, L_0x1309b00; 1 drivers -v0x118ac50_0 .net *"_s1", 0 0, L_0x1309c60; 1 drivers -S_0x118ad30 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118af40 .param/l "i" 0 4 54, +C4<01>; -L_0x1309d50/d .functor AND 1, L_0x1309e10, L_0x130a000, C4<1>, C4<1>; -L_0x1309d50 .delay 1 (30000,30000,30000) L_0x1309d50/d; -v0x118b000_0 .net *"_s0", 0 0, L_0x1309e10; 1 drivers -v0x118b0e0_0 .net *"_s1", 0 0, L_0x130a000; 1 drivers -S_0x118b1c0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118b3d0 .param/l "i" 0 4 54, +C4<010>; -L_0x130a0a0/d .functor AND 1, L_0x130a160, L_0x130a2c0, C4<1>, C4<1>; -L_0x130a0a0 .delay 1 (30000,30000,30000) L_0x130a0a0/d; -v0x118b470_0 .net *"_s0", 0 0, L_0x130a160; 1 drivers -v0x118b550_0 .net *"_s1", 0 0, L_0x130a2c0; 1 drivers -S_0x118b630 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118b840 .param/l "i" 0 4 54, +C4<011>; -L_0x130a3b0/d .functor AND 1, L_0x130a470, L_0x130a5d0, C4<1>, C4<1>; -L_0x130a3b0 .delay 1 (30000,30000,30000) L_0x130a3b0/d; -v0x118b900_0 .net *"_s0", 0 0, L_0x130a470; 1 drivers -v0x118b9e0_0 .net *"_s1", 0 0, L_0x130a5d0; 1 drivers -S_0x118bac0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118bd20 .param/l "i" 0 4 54, +C4<0100>; -L_0x130a710/d .functor AND 1, L_0x130a830, L_0x130a990, C4<1>, C4<1>; -L_0x130a710 .delay 1 (30000,30000,30000) L_0x130a710/d; -v0x118bde0_0 .net *"_s0", 0 0, L_0x130a830; 1 drivers -v0x118bec0_0 .net *"_s1", 0 0, L_0x130a990; 1 drivers -S_0x118bfa0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118c1b0 .param/l "i" 0 4 54, +C4<0101>; -L_0x130aa80/d .functor AND 1, L_0x130ab20, L_0x130ad90, C4<1>, C4<1>; -L_0x130aa80 .delay 1 (30000,30000,30000) L_0x130aa80/d; -v0x118c270_0 .net *"_s0", 0 0, L_0x130ab20; 1 drivers -v0x118c350_0 .net *"_s1", 0 0, L_0x130ad90; 1 drivers -S_0x118c430 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118c640 .param/l "i" 0 4 54, +C4<0110>; -L_0x130aea0/d .functor AND 1, L_0x130af60, L_0x130b0c0, C4<1>, C4<1>; -L_0x130aea0 .delay 1 (30000,30000,30000) L_0x130aea0/d; -v0x118c700_0 .net *"_s0", 0 0, L_0x130af60; 1 drivers -v0x118c7e0_0 .net *"_s1", 0 0, L_0x130b0c0; 1 drivers -S_0x118c8c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x118a620; - .timescale -9 -12; -P_0x118cad0 .param/l "i" 0 4 54, +C4<0111>; -L_0x130ae30/d .functor AND 1, L_0x130b570, L_0x130b760, C4<1>, C4<1>; -L_0x130ae30 .delay 1 (30000,30000,30000) L_0x130ae30/d; -v0x118cb90_0 .net *"_s0", 0 0, L_0x130b570; 1 drivers -v0x118cc70_0 .net *"_s1", 0 0, L_0x130b760; 1 drivers -S_0x118d830 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x118a400; +v0x2c64410_0 .net "A", 7 0, L_0x2df6e90; alias, 1 drivers +v0x2c64510_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c645d0_0 .net *"_s0", 0 0, L_0x2dfaf40; 1 drivers +v0x2c64690_0 .net *"_s12", 0 0, L_0x2dfb8b0; 1 drivers +v0x2c64770_0 .net *"_s16", 0 0, L_0x2dfbc10; 1 drivers +v0x2c648a0_0 .net *"_s20", 0 0, L_0x2dfbfe0; 1 drivers +v0x2c64980_0 .net *"_s24", 0 0, L_0x2dfc310; 1 drivers +v0x2c64a60_0 .net *"_s28", 0 0, L_0x2dfc2a0; 1 drivers +v0x2c64b40_0 .net *"_s4", 0 0, L_0x2dfb290; 1 drivers +v0x2c64cb0_0 .net *"_s8", 0 0, L_0x2dfb5a0; 1 drivers +v0x2c64d90_0 .net "out", 7 0, L_0x2dfc620; alias, 1 drivers +L_0x2dfb000 .part L_0x2df6e90, 0, 1; +L_0x2dfb1f0 .part v0x2cdd2e0_0, 0, 1; +L_0x2dfb350 .part L_0x2df6e90, 1, 1; +L_0x2dfb4b0 .part v0x2cdd2e0_0, 1, 1; +L_0x2dfb660 .part L_0x2df6e90, 2, 1; +L_0x2dfb7c0 .part v0x2cdd2e0_0, 2, 1; +L_0x2dfb970 .part L_0x2df6e90, 3, 1; +L_0x2dfbad0 .part v0x2cdd2e0_0, 3, 1; +L_0x2dfbcd0 .part L_0x2df6e90, 4, 1; +L_0x2dfbf40 .part v0x2cdd2e0_0, 4, 1; +L_0x2dfc050 .part L_0x2df6e90, 5, 1; +L_0x2dfc1b0 .part v0x2cdd2e0_0, 5, 1; +L_0x2dfc3d0 .part L_0x2df6e90, 6, 1; +L_0x2dfc530 .part v0x2cdd2e0_0, 6, 1; +LS_0x2dfc620_0_0 .concat8 [ 1 1 1 1], L_0x2dfaf40, L_0x2dfb290, L_0x2dfb5a0, L_0x2dfb8b0; +LS_0x2dfc620_0_4 .concat8 [ 1 1 1 1], L_0x2dfbc10, L_0x2dfbfe0, L_0x2dfc310, L_0x2dfc2a0; +L_0x2dfc620 .concat8 [ 4 4 0 0], LS_0x2dfc620_0_0, LS_0x2dfc620_0_4; +L_0x2dfc9e0 .part L_0x2df6e90, 7, 1; +L_0x2dfcbd0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c61f40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c62150 .param/l "i" 0 4 54, +C4<00>; +L_0x2dfaf40/d .functor AND 1, L_0x2dfb000, L_0x2dfb1f0, C4<1>, C4<1>; +L_0x2dfaf40 .delay 1 (30000,30000,30000) L_0x2dfaf40/d; +v0x2c62230_0 .net *"_s0", 0 0, L_0x2dfb000; 1 drivers +v0x2c62310_0 .net *"_s1", 0 0, L_0x2dfb1f0; 1 drivers +S_0x2c623f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c62600 .param/l "i" 0 4 54, +C4<01>; +L_0x2dfb290/d .functor AND 1, L_0x2dfb350, L_0x2dfb4b0, C4<1>, C4<1>; +L_0x2dfb290 .delay 1 (30000,30000,30000) L_0x2dfb290/d; +v0x2c626c0_0 .net *"_s0", 0 0, L_0x2dfb350; 1 drivers +v0x2c627a0_0 .net *"_s1", 0 0, L_0x2dfb4b0; 1 drivers +S_0x2c62880 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c62a90 .param/l "i" 0 4 54, +C4<010>; +L_0x2dfb5a0/d .functor AND 1, L_0x2dfb660, L_0x2dfb7c0, C4<1>, C4<1>; +L_0x2dfb5a0 .delay 1 (30000,30000,30000) L_0x2dfb5a0/d; +v0x2c62b30_0 .net *"_s0", 0 0, L_0x2dfb660; 1 drivers +v0x2c62c10_0 .net *"_s1", 0 0, L_0x2dfb7c0; 1 drivers +S_0x2c62cf0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c62f00 .param/l "i" 0 4 54, +C4<011>; +L_0x2dfb8b0/d .functor AND 1, L_0x2dfb970, L_0x2dfbad0, C4<1>, C4<1>; +L_0x2dfb8b0 .delay 1 (30000,30000,30000) L_0x2dfb8b0/d; +v0x2c62fc0_0 .net *"_s0", 0 0, L_0x2dfb970; 1 drivers +v0x2c630a0_0 .net *"_s1", 0 0, L_0x2dfbad0; 1 drivers +S_0x2c63180 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c633e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2dfbc10/d .functor AND 1, L_0x2dfbcd0, L_0x2dfbf40, C4<1>, C4<1>; +L_0x2dfbc10 .delay 1 (30000,30000,30000) L_0x2dfbc10/d; +v0x2c634a0_0 .net *"_s0", 0 0, L_0x2dfbcd0; 1 drivers +v0x2c63580_0 .net *"_s1", 0 0, L_0x2dfbf40; 1 drivers +S_0x2c63660 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c63870 .param/l "i" 0 4 54, +C4<0101>; +L_0x2dfbfe0/d .functor AND 1, L_0x2dfc050, L_0x2dfc1b0, C4<1>, C4<1>; +L_0x2dfbfe0 .delay 1 (30000,30000,30000) L_0x2dfbfe0/d; +v0x2c63930_0 .net *"_s0", 0 0, L_0x2dfc050; 1 drivers +v0x2c63a10_0 .net *"_s1", 0 0, L_0x2dfc1b0; 1 drivers +S_0x2c63af0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c63d00 .param/l "i" 0 4 54, +C4<0110>; +L_0x2dfc310/d .functor AND 1, L_0x2dfc3d0, L_0x2dfc530, C4<1>, C4<1>; +L_0x2dfc310 .delay 1 (30000,30000,30000) L_0x2dfc310/d; +v0x2c63dc0_0 .net *"_s0", 0 0, L_0x2dfc3d0; 1 drivers +v0x2c63ea0_0 .net *"_s1", 0 0, L_0x2dfc530; 1 drivers +S_0x2c63f80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c61ce0; + .timescale -9 -12; +P_0x2c64190 .param/l "i" 0 4 54, +C4<0111>; +L_0x2dfc2a0/d .functor AND 1, L_0x2dfc9e0, L_0x2dfcbd0, C4<1>, C4<1>; +L_0x2dfc2a0 .delay 1 (30000,30000,30000) L_0x2dfc2a0/d; +v0x2c64250_0 .net *"_s0", 0 0, L_0x2dfc9e0; 1 drivers +v0x2c64330_0 .net *"_s1", 0 0, L_0x2dfcbd0; 1 drivers +S_0x2c64ef0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c61ac0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x130d1b0/d .functor OR 1, L_0x130d270, L_0x130d420, C4<0>, C4<0>; -L_0x130d1b0 .delay 1 (30000,30000,30000) L_0x130d1b0/d; -v0x118f380_0 .net *"_s10", 0 0, L_0x130d270; 1 drivers -v0x118f460_0 .net *"_s12", 0 0, L_0x130d420; 1 drivers -v0x118f540_0 .net "in", 7 0, L_0x130b1b0; alias, 1 drivers -v0x118f610_0 .net "ors", 1 0, L_0x130cfd0; 1 drivers -v0x118f6d0_0 .net "out", 0 0, L_0x130d1b0; alias, 1 drivers -L_0x130c3a0 .part L_0x130b1b0, 0, 4; -L_0x130cfd0 .concat8 [ 1 1 0 0], L_0x130c090, L_0x130ccc0; -L_0x130d110 .part L_0x130b1b0, 4, 4; -L_0x130d270 .part L_0x130cfd0, 0, 1; -L_0x130d420 .part L_0x130cfd0, 1, 1; -S_0x118d9f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x118d830; +L_0x2dfe620/d .functor OR 1, L_0x2dfe6e0, L_0x2dfe890, C4<0>, C4<0>; +L_0x2dfe620 .delay 1 (30000,30000,30000) L_0x2dfe620/d; +v0x2c66a70_0 .net *"_s10", 0 0, L_0x2dfe6e0; 1 drivers +v0x2c66b50_0 .net *"_s12", 0 0, L_0x2dfe890; 1 drivers +v0x2c66c30_0 .net "in", 7 0, L_0x2dfc620; alias, 1 drivers +v0x2c66cd0_0 .net "ors", 1 0, L_0x2dfe440; 1 drivers +v0x2c66d90_0 .net "out", 0 0, L_0x2dfe620; alias, 1 drivers +L_0x2dfd810 .part L_0x2dfc620, 0, 4; +L_0x2dfe440 .concat8 [ 1 1 0 0], L_0x2dfd500, L_0x2dfe130; +L_0x2dfe580 .part L_0x2dfc620, 4, 4; +L_0x2dfe6e0 .part L_0x2dfe440, 0, 1; +L_0x2dfe890 .part L_0x2dfe440, 1, 1; +S_0x2c650b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c64ef0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x130b850/d .functor OR 1, L_0x130b910, L_0x130ba70, C4<0>, C4<0>; -L_0x130b850 .delay 1 (30000,30000,30000) L_0x130b850/d; -L_0x130bca0/d .functor OR 1, L_0x130bdb0, L_0x130bf10, C4<0>, C4<0>; -L_0x130bca0 .delay 1 (30000,30000,30000) L_0x130bca0/d; -L_0x130c090/d .functor OR 1, L_0x130c100, L_0x130c2b0, C4<0>, C4<0>; -L_0x130c090 .delay 1 (30000,30000,30000) L_0x130c090/d; -v0x118dc40_0 .net *"_s0", 0 0, L_0x130b850; 1 drivers -v0x118dd40_0 .net *"_s10", 0 0, L_0x130bdb0; 1 drivers -v0x118de20_0 .net *"_s12", 0 0, L_0x130bf10; 1 drivers -v0x118dee0_0 .net *"_s14", 0 0, L_0x130c100; 1 drivers -v0x118dfc0_0 .net *"_s16", 0 0, L_0x130c2b0; 1 drivers -v0x118e0f0_0 .net *"_s3", 0 0, L_0x130b910; 1 drivers -v0x118e1d0_0 .net *"_s5", 0 0, L_0x130ba70; 1 drivers -v0x118e2b0_0 .net *"_s6", 0 0, L_0x130bca0; 1 drivers -v0x118e390_0 .net "in", 3 0, L_0x130c3a0; 1 drivers -v0x118e500_0 .net "ors", 1 0, L_0x130bbb0; 1 drivers -v0x118e5e0_0 .net "out", 0 0, L_0x130c090; 1 drivers -L_0x130b910 .part L_0x130c3a0, 0, 1; -L_0x130ba70 .part L_0x130c3a0, 1, 1; -L_0x130bbb0 .concat8 [ 1 1 0 0], L_0x130b850, L_0x130bca0; -L_0x130bdb0 .part L_0x130c3a0, 2, 1; -L_0x130bf10 .part L_0x130c3a0, 3, 1; -L_0x130c100 .part L_0x130bbb0, 0, 1; -L_0x130c2b0 .part L_0x130bbb0, 1, 1; -S_0x118e700 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x118d830; +L_0x2dfccc0/d .functor OR 1, L_0x2dfcd80, L_0x2dfcee0, C4<0>, C4<0>; +L_0x2dfccc0 .delay 1 (30000,30000,30000) L_0x2dfccc0/d; +L_0x2dfd110/d .functor OR 1, L_0x2dfd220, L_0x2dfd380, C4<0>, C4<0>; +L_0x2dfd110 .delay 1 (30000,30000,30000) L_0x2dfd110/d; +L_0x2dfd500/d .functor OR 1, L_0x2dfd570, L_0x2dfd720, C4<0>, C4<0>; +L_0x2dfd500 .delay 1 (30000,30000,30000) L_0x2dfd500/d; +v0x2c652e0_0 .net *"_s0", 0 0, L_0x2dfccc0; 1 drivers +v0x2c653e0_0 .net *"_s10", 0 0, L_0x2dfd220; 1 drivers +v0x2c654c0_0 .net *"_s12", 0 0, L_0x2dfd380; 1 drivers +v0x2c655b0_0 .net *"_s14", 0 0, L_0x2dfd570; 1 drivers +v0x2c65690_0 .net *"_s16", 0 0, L_0x2dfd720; 1 drivers +v0x2c657c0_0 .net *"_s3", 0 0, L_0x2dfcd80; 1 drivers +v0x2c658a0_0 .net *"_s5", 0 0, L_0x2dfcee0; 1 drivers +v0x2c65980_0 .net *"_s6", 0 0, L_0x2dfd110; 1 drivers +v0x2c65a60_0 .net "in", 3 0, L_0x2dfd810; 1 drivers +v0x2c65bd0_0 .net "ors", 1 0, L_0x2dfd020; 1 drivers +v0x2c65cb0_0 .net "out", 0 0, L_0x2dfd500; 1 drivers +L_0x2dfcd80 .part L_0x2dfd810, 0, 1; +L_0x2dfcee0 .part L_0x2dfd810, 1, 1; +L_0x2dfd020 .concat8 [ 1 1 0 0], L_0x2dfccc0, L_0x2dfd110; +L_0x2dfd220 .part L_0x2dfd810, 2, 1; +L_0x2dfd380 .part L_0x2dfd810, 3, 1; +L_0x2dfd570 .part L_0x2dfd020, 0, 1; +L_0x2dfd720 .part L_0x2dfd020, 1, 1; +S_0x2c65dd0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c64ef0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x130c4d0/d .functor OR 1, L_0x130c540, L_0x130c6a0, C4<0>, C4<0>; -L_0x130c4d0 .delay 1 (30000,30000,30000) L_0x130c4d0/d; -L_0x130c8d0/d .functor OR 1, L_0x130c9e0, L_0x130cb40, C4<0>, C4<0>; -L_0x130c8d0 .delay 1 (30000,30000,30000) L_0x130c8d0/d; -L_0x130ccc0/d .functor OR 1, L_0x130cd30, L_0x130cee0, C4<0>, C4<0>; -L_0x130ccc0 .delay 1 (30000,30000,30000) L_0x130ccc0/d; -v0x118e8c0_0 .net *"_s0", 0 0, L_0x130c4d0; 1 drivers -v0x118e9c0_0 .net *"_s10", 0 0, L_0x130c9e0; 1 drivers -v0x118eaa0_0 .net *"_s12", 0 0, L_0x130cb40; 1 drivers -v0x118eb60_0 .net *"_s14", 0 0, L_0x130cd30; 1 drivers -v0x118ec40_0 .net *"_s16", 0 0, L_0x130cee0; 1 drivers -v0x118ed70_0 .net *"_s3", 0 0, L_0x130c540; 1 drivers -v0x118ee50_0 .net *"_s5", 0 0, L_0x130c6a0; 1 drivers -v0x118ef30_0 .net *"_s6", 0 0, L_0x130c8d0; 1 drivers -v0x118f010_0 .net "in", 3 0, L_0x130d110; 1 drivers -v0x118f180_0 .net "ors", 1 0, L_0x130c7e0; 1 drivers -v0x118f260_0 .net "out", 0 0, L_0x130ccc0; 1 drivers -L_0x130c540 .part L_0x130d110, 0, 1; -L_0x130c6a0 .part L_0x130d110, 1, 1; -L_0x130c7e0 .concat8 [ 1 1 0 0], L_0x130c4d0, L_0x130c8d0; -L_0x130c9e0 .part L_0x130d110, 2, 1; -L_0x130cb40 .part L_0x130d110, 3, 1; -L_0x130cd30 .part L_0x130c7e0, 0, 1; -L_0x130cee0 .part L_0x130c7e0, 1, 1; -S_0x118fb70 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1188ca0; +L_0x2dfd940/d .functor OR 1, L_0x2dfd9b0, L_0x2dfdb10, C4<0>, C4<0>; +L_0x2dfd940 .delay 1 (30000,30000,30000) L_0x2dfd940/d; +L_0x2dfdd40/d .functor OR 1, L_0x2dfde50, L_0x2dfdfb0, C4<0>, C4<0>; +L_0x2dfdd40 .delay 1 (30000,30000,30000) L_0x2dfdd40/d; +L_0x2dfe130/d .functor OR 1, L_0x2dfe1a0, L_0x2dfe350, C4<0>, C4<0>; +L_0x2dfe130 .delay 1 (30000,30000,30000) L_0x2dfe130/d; +v0x2c65fb0_0 .net *"_s0", 0 0, L_0x2dfd940; 1 drivers +v0x2c660b0_0 .net *"_s10", 0 0, L_0x2dfde50; 1 drivers +v0x2c66190_0 .net *"_s12", 0 0, L_0x2dfdfb0; 1 drivers +v0x2c66250_0 .net *"_s14", 0 0, L_0x2dfe1a0; 1 drivers +v0x2c66330_0 .net *"_s16", 0 0, L_0x2dfe350; 1 drivers +v0x2c66460_0 .net *"_s3", 0 0, L_0x2dfd9b0; 1 drivers +v0x2c66540_0 .net *"_s5", 0 0, L_0x2dfdb10; 1 drivers +v0x2c66620_0 .net *"_s6", 0 0, L_0x2dfdd40; 1 drivers +v0x2c66700_0 .net "in", 3 0, L_0x2dfe580; 1 drivers +v0x2c66870_0 .net "ors", 1 0, L_0x2dfdc50; 1 drivers +v0x2c66950_0 .net "out", 0 0, L_0x2dfe130; 1 drivers +L_0x2dfd9b0 .part L_0x2dfe580, 0, 1; +L_0x2dfdb10 .part L_0x2dfe580, 1, 1; +L_0x2dfdc50 .concat8 [ 1 1 0 0], L_0x2dfd940, L_0x2dfdd40; +L_0x2dfde50 .part L_0x2dfe580, 2, 1; +L_0x2dfdfb0 .part L_0x2dfe580, 3, 1; +L_0x2dfe1a0 .part L_0x2dfdc50, 0, 1; +L_0x2dfe350 .part L_0x2dfdc50, 1, 1; +S_0x2c67230 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c60360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x1194fa0_0 .net "ands", 7 0, L_0x13076e0; 1 drivers -v0x11950b0_0 .net "in", 7 0, L_0x1305b40; alias, 1 drivers -v0x1195170_0 .net "out", 0 0, L_0x13096e0; alias, 1 drivers -v0x1195240_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x118fdc0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x118fb70; +v0x2c6c660_0 .net "ands", 7 0, L_0x2df8be0; 1 drivers +v0x2c6c770_0 .net "in", 7 0, L_0x2df6b50; alias, 1 drivers +v0x2c6c830_0 .net "out", 0 0, L_0x2dfabe0; alias, 1 drivers +v0x2c6c900_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c67480 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c67230; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x1192500_0 .net "A", 7 0, L_0x1305b40; alias, 1 drivers -v0x1192600_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11926c0_0 .net *"_s0", 0 0, L_0x1305ed0; 1 drivers -v0x1192780_0 .net *"_s12", 0 0, L_0x1306890; 1 drivers -v0x1192860_0 .net *"_s16", 0 0, L_0x1306bf0; 1 drivers -v0x1192990_0 .net *"_s20", 0 0, L_0x1307020; 1 drivers -v0x1192a70_0 .net *"_s24", 0 0, L_0x1307350; 1 drivers -v0x1192b50_0 .net *"_s28", 0 0, L_0x13072e0; 1 drivers -v0x1192c30_0 .net *"_s4", 0 0, L_0x1306270; 1 drivers -v0x1192da0_0 .net *"_s8", 0 0, L_0x1306580; 1 drivers -v0x1192e80_0 .net "out", 7 0, L_0x13076e0; alias, 1 drivers -L_0x1305fe0 .part L_0x1305b40, 0, 1; -L_0x13061d0 .part v0x12010b0_0, 0, 1; -L_0x1306330 .part L_0x1305b40, 1, 1; -L_0x1306490 .part v0x12010b0_0, 1, 1; -L_0x1306640 .part L_0x1305b40, 2, 1; -L_0x13067a0 .part v0x12010b0_0, 2, 1; -L_0x1306950 .part L_0x1305b40, 3, 1; -L_0x1306ab0 .part v0x12010b0_0, 3, 1; -L_0x1306cb0 .part L_0x1305b40, 4, 1; -L_0x1306f20 .part v0x12010b0_0, 4, 1; -L_0x1307090 .part L_0x1305b40, 5, 1; -L_0x13071f0 .part v0x12010b0_0, 5, 1; -L_0x1307410 .part L_0x1305b40, 6, 1; -L_0x1307570 .part v0x12010b0_0, 6, 1; -LS_0x13076e0_0_0 .concat8 [ 1 1 1 1], L_0x1305ed0, L_0x1306270, L_0x1306580, L_0x1306890; -LS_0x13076e0_0_4 .concat8 [ 1 1 1 1], L_0x1306bf0, L_0x1307020, L_0x1307350, L_0x13072e0; -L_0x13076e0 .concat8 [ 4 4 0 0], LS_0x13076e0_0_0, LS_0x13076e0_0_4; -L_0x1307aa0 .part L_0x1305b40, 7, 1; -L_0x1307c90 .part v0x12010b0_0, 7, 1; -S_0x1190000 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x1190210 .param/l "i" 0 4 54, +C4<00>; -L_0x1305ed0/d .functor AND 1, L_0x1305fe0, L_0x13061d0, C4<1>, C4<1>; -L_0x1305ed0 .delay 1 (30000,30000,30000) L_0x1305ed0/d; -v0x11902f0_0 .net *"_s0", 0 0, L_0x1305fe0; 1 drivers -v0x11903d0_0 .net *"_s1", 0 0, L_0x13061d0; 1 drivers -S_0x11904b0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x11906c0 .param/l "i" 0 4 54, +C4<01>; -L_0x1306270/d .functor AND 1, L_0x1306330, L_0x1306490, C4<1>, C4<1>; -L_0x1306270 .delay 1 (30000,30000,30000) L_0x1306270/d; -v0x1190780_0 .net *"_s0", 0 0, L_0x1306330; 1 drivers -v0x1190860_0 .net *"_s1", 0 0, L_0x1306490; 1 drivers -S_0x1190940 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x1190b80 .param/l "i" 0 4 54, +C4<010>; -L_0x1306580/d .functor AND 1, L_0x1306640, L_0x13067a0, C4<1>, C4<1>; -L_0x1306580 .delay 1 (30000,30000,30000) L_0x1306580/d; -v0x1190c20_0 .net *"_s0", 0 0, L_0x1306640; 1 drivers -v0x1190d00_0 .net *"_s1", 0 0, L_0x13067a0; 1 drivers -S_0x1190de0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x1190ff0 .param/l "i" 0 4 54, +C4<011>; -L_0x1306890/d .functor AND 1, L_0x1306950, L_0x1306ab0, C4<1>, C4<1>; -L_0x1306890 .delay 1 (30000,30000,30000) L_0x1306890/d; -v0x11910b0_0 .net *"_s0", 0 0, L_0x1306950; 1 drivers -v0x1191190_0 .net *"_s1", 0 0, L_0x1306ab0; 1 drivers -S_0x1191270 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x11914d0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1306bf0/d .functor AND 1, L_0x1306cb0, L_0x1306f20, C4<1>, C4<1>; -L_0x1306bf0 .delay 1 (30000,30000,30000) L_0x1306bf0/d; -v0x1191590_0 .net *"_s0", 0 0, L_0x1306cb0; 1 drivers -v0x1191670_0 .net *"_s1", 0 0, L_0x1306f20; 1 drivers -S_0x1191750 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x1191960 .param/l "i" 0 4 54, +C4<0101>; -L_0x1307020/d .functor AND 1, L_0x1307090, L_0x13071f0, C4<1>, C4<1>; -L_0x1307020 .delay 1 (30000,30000,30000) L_0x1307020/d; -v0x1191a20_0 .net *"_s0", 0 0, L_0x1307090; 1 drivers -v0x1191b00_0 .net *"_s1", 0 0, L_0x13071f0; 1 drivers -S_0x1191be0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x1191df0 .param/l "i" 0 4 54, +C4<0110>; -L_0x1307350/d .functor AND 1, L_0x1307410, L_0x1307570, C4<1>, C4<1>; -L_0x1307350 .delay 1 (30000,30000,30000) L_0x1307350/d; -v0x1191eb0_0 .net *"_s0", 0 0, L_0x1307410; 1 drivers -v0x1191f90_0 .net *"_s1", 0 0, L_0x1307570; 1 drivers -S_0x1192070 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x118fdc0; - .timescale -9 -12; -P_0x1192280 .param/l "i" 0 4 54, +C4<0111>; -L_0x13072e0/d .functor AND 1, L_0x1307aa0, L_0x1307c90, C4<1>, C4<1>; -L_0x13072e0 .delay 1 (30000,30000,30000) L_0x13072e0/d; -v0x1192340_0 .net *"_s0", 0 0, L_0x1307aa0; 1 drivers -v0x1192420_0 .net *"_s1", 0 0, L_0x1307c90; 1 drivers -S_0x1192fe0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x118fb70; +v0x2c69bc0_0 .net "A", 7 0, L_0x2df6b50; alias, 1 drivers +v0x2c69cc0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c69d80_0 .net *"_s0", 0 0, L_0x2df73d0; 1 drivers +v0x2c69e40_0 .net *"_s12", 0 0, L_0x2df7d90; 1 drivers +v0x2c69f20_0 .net *"_s16", 0 0, L_0x2df80f0; 1 drivers +v0x2c6a050_0 .net *"_s20", 0 0, L_0x2df8520; 1 drivers +v0x2c6a130_0 .net *"_s24", 0 0, L_0x2df8850; 1 drivers +v0x2c6a210_0 .net *"_s28", 0 0, L_0x2df87e0; 1 drivers +v0x2c6a2f0_0 .net *"_s4", 0 0, L_0x2df7770; 1 drivers +v0x2c6a460_0 .net *"_s8", 0 0, L_0x2df7a80; 1 drivers +v0x2c6a540_0 .net "out", 7 0, L_0x2df8be0; alias, 1 drivers +L_0x2df74e0 .part L_0x2df6b50, 0, 1; +L_0x2df76d0 .part v0x2cdd2e0_0, 0, 1; +L_0x2df7830 .part L_0x2df6b50, 1, 1; +L_0x2df7990 .part v0x2cdd2e0_0, 1, 1; +L_0x2df7b40 .part L_0x2df6b50, 2, 1; +L_0x2df7ca0 .part v0x2cdd2e0_0, 2, 1; +L_0x2df7e50 .part L_0x2df6b50, 3, 1; +L_0x2df7fb0 .part v0x2cdd2e0_0, 3, 1; +L_0x2df81b0 .part L_0x2df6b50, 4, 1; +L_0x2df8420 .part v0x2cdd2e0_0, 4, 1; +L_0x2df8590 .part L_0x2df6b50, 5, 1; +L_0x2df86f0 .part v0x2cdd2e0_0, 5, 1; +L_0x2df8910 .part L_0x2df6b50, 6, 1; +L_0x2df8a70 .part v0x2cdd2e0_0, 6, 1; +LS_0x2df8be0_0_0 .concat8 [ 1 1 1 1], L_0x2df73d0, L_0x2df7770, L_0x2df7a80, L_0x2df7d90; +LS_0x2df8be0_0_4 .concat8 [ 1 1 1 1], L_0x2df80f0, L_0x2df8520, L_0x2df8850, L_0x2df87e0; +L_0x2df8be0 .concat8 [ 4 4 0 0], LS_0x2df8be0_0_0, LS_0x2df8be0_0_4; +L_0x2df8fa0 .part L_0x2df6b50, 7, 1; +L_0x2df9190 .part v0x2cdd2e0_0, 7, 1; +S_0x2c676c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c678d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2df73d0/d .functor AND 1, L_0x2df74e0, L_0x2df76d0, C4<1>, C4<1>; +L_0x2df73d0 .delay 1 (30000,30000,30000) L_0x2df73d0/d; +v0x2c679b0_0 .net *"_s0", 0 0, L_0x2df74e0; 1 drivers +v0x2c67a90_0 .net *"_s1", 0 0, L_0x2df76d0; 1 drivers +S_0x2c67b70 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c67d80 .param/l "i" 0 4 54, +C4<01>; +L_0x2df7770/d .functor AND 1, L_0x2df7830, L_0x2df7990, C4<1>, C4<1>; +L_0x2df7770 .delay 1 (30000,30000,30000) L_0x2df7770/d; +v0x2c67e40_0 .net *"_s0", 0 0, L_0x2df7830; 1 drivers +v0x2c67f20_0 .net *"_s1", 0 0, L_0x2df7990; 1 drivers +S_0x2c68000 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c68240 .param/l "i" 0 4 54, +C4<010>; +L_0x2df7a80/d .functor AND 1, L_0x2df7b40, L_0x2df7ca0, C4<1>, C4<1>; +L_0x2df7a80 .delay 1 (30000,30000,30000) L_0x2df7a80/d; +v0x2c682e0_0 .net *"_s0", 0 0, L_0x2df7b40; 1 drivers +v0x2c683c0_0 .net *"_s1", 0 0, L_0x2df7ca0; 1 drivers +S_0x2c684a0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c686b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2df7d90/d .functor AND 1, L_0x2df7e50, L_0x2df7fb0, C4<1>, C4<1>; +L_0x2df7d90 .delay 1 (30000,30000,30000) L_0x2df7d90/d; +v0x2c68770_0 .net *"_s0", 0 0, L_0x2df7e50; 1 drivers +v0x2c68850_0 .net *"_s1", 0 0, L_0x2df7fb0; 1 drivers +S_0x2c68930 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c68b90 .param/l "i" 0 4 54, +C4<0100>; +L_0x2df80f0/d .functor AND 1, L_0x2df81b0, L_0x2df8420, C4<1>, C4<1>; +L_0x2df80f0 .delay 1 (30000,30000,30000) L_0x2df80f0/d; +v0x2c68c50_0 .net *"_s0", 0 0, L_0x2df81b0; 1 drivers +v0x2c68d30_0 .net *"_s1", 0 0, L_0x2df8420; 1 drivers +S_0x2c68e10 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c69020 .param/l "i" 0 4 54, +C4<0101>; +L_0x2df8520/d .functor AND 1, L_0x2df8590, L_0x2df86f0, C4<1>, C4<1>; +L_0x2df8520 .delay 1 (30000,30000,30000) L_0x2df8520/d; +v0x2c690e0_0 .net *"_s0", 0 0, L_0x2df8590; 1 drivers +v0x2c691c0_0 .net *"_s1", 0 0, L_0x2df86f0; 1 drivers +S_0x2c692a0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c694b0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2df8850/d .functor AND 1, L_0x2df8910, L_0x2df8a70, C4<1>, C4<1>; +L_0x2df8850 .delay 1 (30000,30000,30000) L_0x2df8850/d; +v0x2c69570_0 .net *"_s0", 0 0, L_0x2df8910; 1 drivers +v0x2c69650_0 .net *"_s1", 0 0, L_0x2df8a70; 1 drivers +S_0x2c69730 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c67480; + .timescale -9 -12; +P_0x2c69940 .param/l "i" 0 4 54, +C4<0111>; +L_0x2df87e0/d .functor AND 1, L_0x2df8fa0, L_0x2df9190, C4<1>, C4<1>; +L_0x2df87e0 .delay 1 (30000,30000,30000) L_0x2df87e0/d; +v0x2c69a00_0 .net *"_s0", 0 0, L_0x2df8fa0; 1 drivers +v0x2c69ae0_0 .net *"_s1", 0 0, L_0x2df9190; 1 drivers +S_0x2c6a6a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c67230; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x13096e0/d .functor OR 1, L_0x13097a0, L_0x1309950, C4<0>, C4<0>; -L_0x13096e0 .delay 1 (30000,30000,30000) L_0x13096e0/d; -v0x1194b30_0 .net *"_s10", 0 0, L_0x13097a0; 1 drivers -v0x1194c10_0 .net *"_s12", 0 0, L_0x1309950; 1 drivers -v0x1194cf0_0 .net "in", 7 0, L_0x13076e0; alias, 1 drivers -v0x1194dc0_0 .net "ors", 1 0, L_0x1309500; 1 drivers -v0x1194e80_0 .net "out", 0 0, L_0x13096e0; alias, 1 drivers -L_0x13088d0 .part L_0x13076e0, 0, 4; -L_0x1309500 .concat8 [ 1 1 0 0], L_0x13085c0, L_0x13091f0; -L_0x1309640 .part L_0x13076e0, 4, 4; -L_0x13097a0 .part L_0x1309500, 0, 1; -L_0x1309950 .part L_0x1309500, 1, 1; -S_0x11931a0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x1192fe0; +L_0x2dfabe0/d .functor OR 1, L_0x2dfaca0, L_0x2dfae50, C4<0>, C4<0>; +L_0x2dfabe0 .delay 1 (30000,30000,30000) L_0x2dfabe0/d; +v0x2c6c1f0_0 .net *"_s10", 0 0, L_0x2dfaca0; 1 drivers +v0x2c6c2d0_0 .net *"_s12", 0 0, L_0x2dfae50; 1 drivers +v0x2c6c3b0_0 .net "in", 7 0, L_0x2df8be0; alias, 1 drivers +v0x2c6c480_0 .net "ors", 1 0, L_0x2dfaa00; 1 drivers +v0x2c6c540_0 .net "out", 0 0, L_0x2dfabe0; alias, 1 drivers +L_0x2df9dd0 .part L_0x2df8be0, 0, 4; +L_0x2dfaa00 .concat8 [ 1 1 0 0], L_0x2df9ac0, L_0x2dfa6f0; +L_0x2dfab40 .part L_0x2df8be0, 4, 4; +L_0x2dfaca0 .part L_0x2dfaa00, 0, 1; +L_0x2dfae50 .part L_0x2dfaa00, 1, 1; +S_0x2c6a860 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c6a6a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1307d80/d .functor OR 1, L_0x1307e40, L_0x1307fa0, C4<0>, C4<0>; -L_0x1307d80 .delay 1 (30000,30000,30000) L_0x1307d80/d; -L_0x13081d0/d .functor OR 1, L_0x13082e0, L_0x1308440, C4<0>, C4<0>; -L_0x13081d0 .delay 1 (30000,30000,30000) L_0x13081d0/d; -L_0x13085c0/d .functor OR 1, L_0x1308630, L_0x13087e0, C4<0>, C4<0>; -L_0x13085c0 .delay 1 (30000,30000,30000) L_0x13085c0/d; -v0x11933f0_0 .net *"_s0", 0 0, L_0x1307d80; 1 drivers -v0x11934f0_0 .net *"_s10", 0 0, L_0x13082e0; 1 drivers -v0x11935d0_0 .net *"_s12", 0 0, L_0x1308440; 1 drivers -v0x1193690_0 .net *"_s14", 0 0, L_0x1308630; 1 drivers -v0x1193770_0 .net *"_s16", 0 0, L_0x13087e0; 1 drivers -v0x11938a0_0 .net *"_s3", 0 0, L_0x1307e40; 1 drivers -v0x1193980_0 .net *"_s5", 0 0, L_0x1307fa0; 1 drivers -v0x1193a60_0 .net *"_s6", 0 0, L_0x13081d0; 1 drivers -v0x1193b40_0 .net "in", 3 0, L_0x13088d0; 1 drivers -v0x1193cb0_0 .net "ors", 1 0, L_0x13080e0; 1 drivers -v0x1193d90_0 .net "out", 0 0, L_0x13085c0; 1 drivers -L_0x1307e40 .part L_0x13088d0, 0, 1; -L_0x1307fa0 .part L_0x13088d0, 1, 1; -L_0x13080e0 .concat8 [ 1 1 0 0], L_0x1307d80, L_0x13081d0; -L_0x13082e0 .part L_0x13088d0, 2, 1; -L_0x1308440 .part L_0x13088d0, 3, 1; -L_0x1308630 .part L_0x13080e0, 0, 1; -L_0x13087e0 .part L_0x13080e0, 1, 1; -S_0x1193eb0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x1192fe0; +L_0x2df9280/d .functor OR 1, L_0x2df9340, L_0x2df94a0, C4<0>, C4<0>; +L_0x2df9280 .delay 1 (30000,30000,30000) L_0x2df9280/d; +L_0x2df96d0/d .functor OR 1, L_0x2df97e0, L_0x2df9940, C4<0>, C4<0>; +L_0x2df96d0 .delay 1 (30000,30000,30000) L_0x2df96d0/d; +L_0x2df9ac0/d .functor OR 1, L_0x2df9b30, L_0x2df9ce0, C4<0>, C4<0>; +L_0x2df9ac0 .delay 1 (30000,30000,30000) L_0x2df9ac0/d; +v0x2c6aab0_0 .net *"_s0", 0 0, L_0x2df9280; 1 drivers +v0x2c6abb0_0 .net *"_s10", 0 0, L_0x2df97e0; 1 drivers +v0x2c6ac90_0 .net *"_s12", 0 0, L_0x2df9940; 1 drivers +v0x2c6ad50_0 .net *"_s14", 0 0, L_0x2df9b30; 1 drivers +v0x2c6ae30_0 .net *"_s16", 0 0, L_0x2df9ce0; 1 drivers +v0x2c6af60_0 .net *"_s3", 0 0, L_0x2df9340; 1 drivers +v0x2c6b040_0 .net *"_s5", 0 0, L_0x2df94a0; 1 drivers +v0x2c6b120_0 .net *"_s6", 0 0, L_0x2df96d0; 1 drivers +v0x2c6b200_0 .net "in", 3 0, L_0x2df9dd0; 1 drivers +v0x2c6b370_0 .net "ors", 1 0, L_0x2df95e0; 1 drivers +v0x2c6b450_0 .net "out", 0 0, L_0x2df9ac0; 1 drivers +L_0x2df9340 .part L_0x2df9dd0, 0, 1; +L_0x2df94a0 .part L_0x2df9dd0, 1, 1; +L_0x2df95e0 .concat8 [ 1 1 0 0], L_0x2df9280, L_0x2df96d0; +L_0x2df97e0 .part L_0x2df9dd0, 2, 1; +L_0x2df9940 .part L_0x2df9dd0, 3, 1; +L_0x2df9b30 .part L_0x2df95e0, 0, 1; +L_0x2df9ce0 .part L_0x2df95e0, 1, 1; +S_0x2c6b570 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c6a6a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1308a00/d .functor OR 1, L_0x1308a70, L_0x1308bd0, C4<0>, C4<0>; -L_0x1308a00 .delay 1 (30000,30000,30000) L_0x1308a00/d; -L_0x1308e00/d .functor OR 1, L_0x1308f10, L_0x1309070, C4<0>, C4<0>; -L_0x1308e00 .delay 1 (30000,30000,30000) L_0x1308e00/d; -L_0x13091f0/d .functor OR 1, L_0x1309260, L_0x1309410, C4<0>, C4<0>; -L_0x13091f0 .delay 1 (30000,30000,30000) L_0x13091f0/d; -v0x1194070_0 .net *"_s0", 0 0, L_0x1308a00; 1 drivers -v0x1194170_0 .net *"_s10", 0 0, L_0x1308f10; 1 drivers -v0x1194250_0 .net *"_s12", 0 0, L_0x1309070; 1 drivers -v0x1194310_0 .net *"_s14", 0 0, L_0x1309260; 1 drivers -v0x11943f0_0 .net *"_s16", 0 0, L_0x1309410; 1 drivers -v0x1194520_0 .net *"_s3", 0 0, L_0x1308a70; 1 drivers -v0x1194600_0 .net *"_s5", 0 0, L_0x1308bd0; 1 drivers -v0x11946e0_0 .net *"_s6", 0 0, L_0x1308e00; 1 drivers -v0x11947c0_0 .net "in", 3 0, L_0x1309640; 1 drivers -v0x1194930_0 .net "ors", 1 0, L_0x1308d10; 1 drivers -v0x1194a10_0 .net "out", 0 0, L_0x13091f0; 1 drivers -L_0x1308a70 .part L_0x1309640, 0, 1; -L_0x1308bd0 .part L_0x1309640, 1, 1; -L_0x1308d10 .concat8 [ 1 1 0 0], L_0x1308a00, L_0x1308e00; -L_0x1308f10 .part L_0x1309640, 2, 1; -L_0x1309070 .part L_0x1309640, 3, 1; -L_0x1309260 .part L_0x1308d10, 0, 1; -L_0x1309410 .part L_0x1308d10, 1, 1; -S_0x1195320 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1188ca0; +L_0x2df9f00/d .functor OR 1, L_0x2df9f70, L_0x2dfa0d0, C4<0>, C4<0>; +L_0x2df9f00 .delay 1 (30000,30000,30000) L_0x2df9f00/d; +L_0x2dfa300/d .functor OR 1, L_0x2dfa410, L_0x2dfa570, C4<0>, C4<0>; +L_0x2dfa300 .delay 1 (30000,30000,30000) L_0x2dfa300/d; +L_0x2dfa6f0/d .functor OR 1, L_0x2dfa760, L_0x2dfa910, C4<0>, C4<0>; +L_0x2dfa6f0 .delay 1 (30000,30000,30000) L_0x2dfa6f0/d; +v0x2c6b730_0 .net *"_s0", 0 0, L_0x2df9f00; 1 drivers +v0x2c6b830_0 .net *"_s10", 0 0, L_0x2dfa410; 1 drivers +v0x2c6b910_0 .net *"_s12", 0 0, L_0x2dfa570; 1 drivers +v0x2c6b9d0_0 .net *"_s14", 0 0, L_0x2dfa760; 1 drivers +v0x2c6bab0_0 .net *"_s16", 0 0, L_0x2dfa910; 1 drivers +v0x2c6bbe0_0 .net *"_s3", 0 0, L_0x2df9f70; 1 drivers +v0x2c6bcc0_0 .net *"_s5", 0 0, L_0x2dfa0d0; 1 drivers +v0x2c6bda0_0 .net *"_s6", 0 0, L_0x2dfa300; 1 drivers +v0x2c6be80_0 .net "in", 3 0, L_0x2dfab40; 1 drivers +v0x2c6bff0_0 .net "ors", 1 0, L_0x2dfa210; 1 drivers +v0x2c6c0d0_0 .net "out", 0 0, L_0x2dfa6f0; 1 drivers +L_0x2df9f70 .part L_0x2dfab40, 0, 1; +L_0x2dfa0d0 .part L_0x2dfab40, 1, 1; +L_0x2dfa210 .concat8 [ 1 1 0 0], L_0x2df9f00, L_0x2dfa300; +L_0x2dfa410 .part L_0x2dfab40, 2, 1; +L_0x2dfa570 .part L_0x2dfab40, 3, 1; +L_0x2dfa760 .part L_0x2dfa210, 0, 1; +L_0x2dfa910 .part L_0x2dfa210, 1, 1; +S_0x2c6c9e0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c60360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -14438,80 +15277,80 @@ S_0x1195320 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1188ca0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1304eb0/d .functor XNOR 1, L_0x130d610, L_0x130d770, C4<0>, C4<0>; -L_0x1304eb0 .delay 1 (20000,20000,20000) L_0x1304eb0/d; -L_0x1305120/d .functor AND 1, L_0x130d610, L_0x1303df0, C4<1>, C4<1>; -L_0x1305120 .delay 1 (30000,30000,30000) L_0x1305120/d; -L_0x1305190/d .functor AND 1, L_0x1304eb0, L_0x1303b20, C4<1>, C4<1>; -L_0x1305190 .delay 1 (30000,30000,30000) L_0x1305190/d; -L_0x13052f0/d .functor OR 1, L_0x1305190, L_0x1305120, C4<0>, C4<0>; -L_0x13052f0 .delay 1 (30000,30000,30000) L_0x13052f0/d; -v0x11955d0_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers -v0x11956c0_0 .net "a_", 0 0, L_0x12fa140; alias, 1 drivers -v0x1195780_0 .net "b", 0 0, L_0x130d770; alias, 1 drivers -v0x1195870_0 .net "b_", 0 0, L_0x1303df0; alias, 1 drivers -v0x1195910_0 .net "carryin", 0 0, L_0x1303b20; alias, 1 drivers -v0x1195a50_0 .net "eq", 0 0, L_0x1304eb0; 1 drivers -v0x1195b10_0 .net "lt", 0 0, L_0x1305120; 1 drivers -v0x1195bd0_0 .net "out", 0 0, L_0x13052f0; 1 drivers -v0x1195c90_0 .net "w0", 0 0, L_0x1305190; 1 drivers -S_0x1195ee0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1188ca0; +L_0x2df5990/d .functor XNOR 1, L_0x2dfea80, L_0x2dfebe0, C4<0>, C4<0>; +L_0x2df5990 .delay 1 (20000,20000,20000) L_0x2df5990/d; +L_0x2df5b10/d .functor AND 1, L_0x2dfea80, L_0x2df46d0, C4<1>, C4<1>; +L_0x2df5b10 .delay 1 (30000,30000,30000) L_0x2df5b10/d; +L_0x2df5c70/d .functor AND 1, L_0x2df5990, L_0x2df43b0, C4<1>, C4<1>; +L_0x2df5c70 .delay 1 (30000,30000,30000) L_0x2df5c70/d; +L_0x2df5d80/d .functor OR 1, L_0x2df5c70, L_0x2df5b10, C4<0>, C4<0>; +L_0x2df5d80 .delay 1 (30000,30000,30000) L_0x2df5d80/d; +v0x2c6cc90_0 .net "a", 0 0, L_0x2dfea80; alias, 1 drivers +v0x2c6cd80_0 .net "a_", 0 0, L_0x2de9e60; alias, 1 drivers +v0x2c6ce40_0 .net "b", 0 0, L_0x2dfebe0; alias, 1 drivers +v0x2c6cf30_0 .net "b_", 0 0, L_0x2df46d0; alias, 1 drivers +v0x2c6cfd0_0 .net "carryin", 0 0, L_0x2df43b0; alias, 1 drivers +v0x2c6d110_0 .net "eq", 0 0, L_0x2df5990; 1 drivers +v0x2c6d1d0_0 .net "lt", 0 0, L_0x2df5b10; 1 drivers +v0x2c6d290_0 .net "out", 0 0, L_0x2df5d80; 1 drivers +v0x2c6d350_0 .net "w0", 0 0, L_0x2df5c70; 1 drivers +S_0x2c6d5a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c60360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1304c90/d .functor OR 1, L_0x13047e0, L_0x1197140, C4<0>, C4<0>; -L_0x1304c90 .delay 1 (30000,30000,30000) L_0x1304c90/d; -v0x1196cd0_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers -v0x1196e20_0 .net "b", 0 0, L_0x1303df0; alias, 1 drivers -v0x1196ee0_0 .net "c1", 0 0, L_0x13047e0; 1 drivers -v0x1196f80_0 .net "c2", 0 0, L_0x1197140; 1 drivers -v0x1197050_0 .net "carryin", 0 0, L_0x1303b20; alias, 1 drivers -v0x11971d0_0 .net "carryout", 0 0, L_0x1304c90; 1 drivers -v0x1197270_0 .net "s1", 0 0, L_0x1304720; 1 drivers -v0x1197310_0 .net "sum", 0 0, L_0x1304940; 1 drivers -S_0x1196130 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1195ee0; +L_0x2df5570/d .functor OR 1, L_0x2df50c0, L_0x2c6e800, C4<0>, C4<0>; +L_0x2df5570 .delay 1 (30000,30000,30000) L_0x2df5570/d; +v0x2c6e390_0 .net "a", 0 0, L_0x2dfea80; alias, 1 drivers +v0x2c6e4e0_0 .net "b", 0 0, L_0x2df46d0; alias, 1 drivers +v0x2c6e5a0_0 .net "c1", 0 0, L_0x2df50c0; 1 drivers +v0x2c6e640_0 .net "c2", 0 0, L_0x2c6e800; 1 drivers +v0x2c6e710_0 .net "carryin", 0 0, L_0x2df43b0; alias, 1 drivers +v0x2c6e890_0 .net "carryout", 0 0, L_0x2df5570; 1 drivers +v0x2c6e930_0 .net "s1", 0 0, L_0x2df5000; 1 drivers +v0x2c6e9d0_0 .net "sum", 0 0, L_0x2df5220; 1 drivers +S_0x2c6d7f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c6d5a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1304720/d .functor XOR 1, L_0x130d610, L_0x1303df0, C4<0>, C4<0>; -L_0x1304720 .delay 1 (30000,30000,30000) L_0x1304720/d; -L_0x13047e0/d .functor AND 1, L_0x130d610, L_0x1303df0, C4<1>, C4<1>; -L_0x13047e0 .delay 1 (30000,30000,30000) L_0x13047e0/d; -v0x1196390_0 .net "a", 0 0, L_0x130d610; alias, 1 drivers -v0x1196450_0 .net "b", 0 0, L_0x1303df0; alias, 1 drivers -v0x1196510_0 .net "carryout", 0 0, L_0x13047e0; alias, 1 drivers -v0x11965b0_0 .net "sum", 0 0, L_0x1304720; alias, 1 drivers -S_0x11966e0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1195ee0; +L_0x2df5000/d .functor XOR 1, L_0x2dfea80, L_0x2df46d0, C4<0>, C4<0>; +L_0x2df5000 .delay 1 (30000,30000,30000) L_0x2df5000/d; +L_0x2df50c0/d .functor AND 1, L_0x2dfea80, L_0x2df46d0, C4<1>, C4<1>; +L_0x2df50c0 .delay 1 (30000,30000,30000) L_0x2df50c0/d; +v0x2c6da50_0 .net "a", 0 0, L_0x2dfea80; alias, 1 drivers +v0x2c6db10_0 .net "b", 0 0, L_0x2df46d0; alias, 1 drivers +v0x2c6dbd0_0 .net "carryout", 0 0, L_0x2df50c0; alias, 1 drivers +v0x2c6dc70_0 .net "sum", 0 0, L_0x2df5000; alias, 1 drivers +S_0x2c6dda0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c6d5a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1304940/d .functor XOR 1, L_0x1304720, L_0x1303b20, C4<0>, C4<0>; -L_0x1304940 .delay 1 (30000,30000,30000) L_0x1304940/d; -L_0x1197140/d .functor AND 1, L_0x1304720, L_0x1303b20, C4<1>, C4<1>; -L_0x1197140 .delay 1 (30000,30000,30000) L_0x1197140/d; -v0x1196940_0 .net "a", 0 0, L_0x1304720; alias, 1 drivers -v0x1196a10_0 .net "b", 0 0, L_0x1303b20; alias, 1 drivers -v0x1196ab0_0 .net "carryout", 0 0, L_0x1197140; alias, 1 drivers -v0x1196b80_0 .net "sum", 0 0, L_0x1304940; alias, 1 drivers -S_0x1198730 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11889d0; - .timescale -9 -12; -L_0x2b0ab3d06d58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06da0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x130d6b0/d .functor OR 1, L_0x2b0ab3d06d58, L_0x2b0ab3d06da0, C4<0>, C4<0>; -L_0x130d6b0 .delay 1 (30000,30000,30000) L_0x130d6b0/d; -v0x1198920_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06d58; 1 drivers -v0x1198a00_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06da0; 1 drivers -S_0x1198ae0 .scope generate, "alu_slices[27]" "alu_slices[27]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x1198cf0 .param/l "i" 0 3 41, +C4<011011>; -S_0x1198db0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1198ae0; +L_0x2df5220/d .functor XOR 1, L_0x2df5000, L_0x2df43b0, C4<0>, C4<0>; +L_0x2df5220 .delay 1 (30000,30000,30000) L_0x2df5220/d; +L_0x2c6e800/d .functor AND 1, L_0x2df5000, L_0x2df43b0, C4<1>, C4<1>; +L_0x2c6e800 .delay 1 (30000,30000,30000) L_0x2c6e800/d; +v0x2c6e000_0 .net "a", 0 0, L_0x2df5000; alias, 1 drivers +v0x2c6e0d0_0 .net "b", 0 0, L_0x2df43b0; alias, 1 drivers +v0x2c6e170_0 .net "carryout", 0 0, L_0x2c6e800; alias, 1 drivers +v0x2c6e240_0 .net "sum", 0 0, L_0x2df5220; alias, 1 drivers +S_0x2c70a60 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c60090; + .timescale -9 -12; +L_0x2ac6110bc948 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bc990 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2df4b80/d .functor OR 1, L_0x2ac6110bc948, L_0x2ac6110bc990, C4<0>, C4<0>; +L_0x2df4b80 .delay 1 (30000,30000,30000) L_0x2df4b80/d; +v0x2c70c50_0 .net/2u *"_s0", 0 0, L_0x2ac6110bc948; 1 drivers +v0x2c70d30_0 .net/2u *"_s2", 0 0, L_0x2ac6110bc990; 1 drivers +S_0x2c70e10 .scope generate, "alu_slices[27]" "alu_slices[27]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c71020 .param/l "i" 0 3 39, +C4<011011>; +S_0x2c710e0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c70e10; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -14520,445 +15359,476 @@ S_0x1198db0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x1198ae0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1303cb0/d .functor NOT 1, L_0x1317160, C4<0>, C4<0>, C4<0>; -L_0x1303cb0 .delay 1 (10000,10000,10000) L_0x1303cb0/d; -L_0x130db40/d .functor NOT 1, L_0x130d810, C4<0>, C4<0>, C4<0>; -L_0x130db40 .delay 1 (10000,10000,10000) L_0x130db40/d; -L_0x130eb90/d .functor XOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; -L_0x130eb90 .delay 1 (30000,30000,30000) L_0x130eb90/d; -L_0x2b0ab3d06de8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06e30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x130f240/d .functor OR 1, L_0x2b0ab3d06de8, L_0x2b0ab3d06e30, C4<0>, C4<0>; -L_0x130f240 .delay 1 (30000,30000,30000) L_0x130f240/d; -L_0x130f440/d .functor AND 1, L_0x1317160, L_0x130d810, C4<1>, C4<1>; -L_0x130f440 .delay 1 (30000,30000,30000) L_0x130f440/d; -L_0x130f500/d .functor NAND 1, L_0x1317160, L_0x130d810, C4<1>, C4<1>; -L_0x130f500 .delay 1 (20000,20000,20000) L_0x130f500/d; -L_0x130f660/d .functor XOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; -L_0x130f660 .delay 1 (20000,20000,20000) L_0x130f660/d; -L_0x130fb10/d .functor OR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; -L_0x130fb10 .delay 1 (30000,30000,30000) L_0x130fb10/d; -L_0x1317060/d .functor NOT 1, L_0x13133a0, C4<0>, C4<0>, C4<0>; -L_0x1317060 .delay 1 (10000,10000,10000) L_0x1317060/d; -v0x11a74e0_0 .net "A", 0 0, L_0x1317160; 1 drivers -v0x11a75a0_0 .net "A_", 0 0, L_0x1303cb0; 1 drivers -v0x11a7660_0 .net "B", 0 0, L_0x130d810; 1 drivers -v0x11a7730_0 .net "B_", 0 0, L_0x130db40; 1 drivers -v0x11a77d0_0 .net *"_s12", 0 0, L_0x130f240; 1 drivers -v0x11a78c0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06de8; 1 drivers -v0x11a7980_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06e30; 1 drivers -v0x11a7a60_0 .net *"_s18", 0 0, L_0x130f440; 1 drivers -v0x11a7b40_0 .net *"_s20", 0 0, L_0x130f500; 1 drivers -v0x11a7cb0_0 .net *"_s22", 0 0, L_0x130f660; 1 drivers -v0x11a7d90_0 .net *"_s24", 0 0, L_0x130fb10; 1 drivers -o0x2b0ab3ce5238 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x11a7e70_0 name=_s30 -o0x2b0ab3ce5268 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x11a7f50_0 name=_s32 -v0x11a8030_0 .net *"_s8", 0 0, L_0x130eb90; 1 drivers -v0x11a8110_0 .net "carryin", 0 0, L_0x130d8b0; 1 drivers -v0x11a81b0_0 .net "carryout", 0 0, L_0x1316d00; 1 drivers -v0x11a8250_0 .net "carryouts", 7 0, L_0x1355d10; 1 drivers -v0x11a8400_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11a84a0_0 .net "result", 0 0, L_0x13133a0; 1 drivers -v0x11a8590_0 .net "results", 7 0, L_0x130f8e0; 1 drivers -v0x11a86a0_0 .net "zero", 0 0, L_0x1317060; 1 drivers -LS_0x130f8e0_0_0 .concat8 [ 1 1 1 1], L_0x130e060, L_0x130e690, L_0x130eb90, L_0x130f240; -LS_0x130f8e0_0_4 .concat8 [ 1 1 1 1], L_0x130f440, L_0x130f500, L_0x130f660, L_0x130fb10; -L_0x130f8e0 .concat8 [ 4 4 0 0], LS_0x130f8e0_0_0, LS_0x130f8e0_0_4; -LS_0x1355d10_0_0 .concat [ 1 1 1 1], L_0x130e310, L_0x130ea30, o0x2b0ab3ce5238, L_0x130f090; -LS_0x1355d10_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce5268; -L_0x1355d10 .concat [ 4 4 0 0], LS_0x1355d10_0_0, LS_0x1355d10_0_4; -S_0x1199030 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x1198db0; +L_0x2df44f0/d .functor NOT 1, L_0x2e092e0, C4<0>, C4<0>, C4<0>; +L_0x2df44f0 .delay 1 (10000,10000,10000) L_0x2df44f0/d; +L_0x2dfef60/d .functor NOT 1, L_0x2dfec80, C4<0>, C4<0>, C4<0>; +L_0x2dfef60 .delay 1 (10000,10000,10000) L_0x2dfef60/d; +L_0x2dfffb0/d .functor XOR 1, L_0x2e092e0, L_0x2dfec80, C4<0>, C4<0>; +L_0x2dfffb0 .delay 1 (30000,30000,30000) L_0x2dfffb0/d; +L_0x2ac6110bc9d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bca20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e00070/d .functor OR 1, L_0x2ac6110bc9d8, L_0x2ac6110bca20, C4<0>, C4<0>; +L_0x2e00070 .delay 1 (30000,30000,30000) L_0x2e00070/d; +L_0x2ac6110bca68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcab0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e00810/d .functor OR 1, L_0x2ac6110bca68, L_0x2ac6110bcab0, C4<0>, C4<0>; +L_0x2e00810 .delay 1 (30000,30000,30000) L_0x2e00810/d; +L_0x2e00a10/d .functor AND 1, L_0x2e092e0, L_0x2dfec80, C4<1>, C4<1>; +L_0x2e00a10 .delay 1 (30000,30000,30000) L_0x2e00a10/d; +L_0x2ac6110bcaf8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcb40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e00ad0/d .functor OR 1, L_0x2ac6110bcaf8, L_0x2ac6110bcb40, C4<0>, C4<0>; +L_0x2e00ad0 .delay 1 (30000,30000,30000) L_0x2e00ad0/d; +L_0x2e00cd0/d .functor NAND 1, L_0x2e092e0, L_0x2dfec80, C4<1>, C4<1>; +L_0x2e00cd0 .delay 1 (20000,20000,20000) L_0x2e00cd0/d; +L_0x2ac6110bcb88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcbd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e00de0/d .functor OR 1, L_0x2ac6110bcb88, L_0x2ac6110bcbd0, C4<0>, C4<0>; +L_0x2e00de0 .delay 1 (30000,30000,30000) L_0x2e00de0/d; +L_0x2e00f90/d .functor NOR 1, L_0x2e092e0, L_0x2dfec80, C4<0>, C4<0>; +L_0x2e00f90 .delay 1 (20000,20000,20000) L_0x2e00f90/d; +L_0x2ac6110bcc18 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcc60 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2dff410/d .functor OR 1, L_0x2ac6110bcc18, L_0x2ac6110bcc60, C4<0>, C4<0>; +L_0x2dff410 .delay 1 (30000,30000,30000) L_0x2dff410/d; +L_0x2e015f0/d .functor OR 1, L_0x2e092e0, L_0x2dfec80, C4<0>, C4<0>; +L_0x2e015f0 .delay 1 (30000,30000,30000) L_0x2e015f0/d; +L_0x2ac6110bcca8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bccf0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e01ae0/d .functor OR 1, L_0x2ac6110bcca8, L_0x2ac6110bccf0, C4<0>, C4<0>; +L_0x2e01ae0 .delay 1 (30000,30000,30000) L_0x2e01ae0/d; +L_0x2e091e0/d .functor NOT 1, L_0x2e05440, C4<0>, C4<0>, C4<0>; +L_0x2e091e0 .delay 1 (10000,10000,10000) L_0x2e091e0/d; +v0x2c7f810_0 .net "A", 0 0, L_0x2e092e0; 1 drivers +v0x2c7f8d0_0 .net "A_", 0 0, L_0x2df44f0; 1 drivers +v0x2c7f990_0 .net "B", 0 0, L_0x2dfec80; 1 drivers +v0x2c7fa60_0 .net "B_", 0 0, L_0x2dfef60; 1 drivers +v0x2c7fb00_0 .net *"_s11", 0 0, L_0x2e00070; 1 drivers +v0x2c7fbf0_0 .net/2s *"_s13", 0 0, L_0x2ac6110bc9d8; 1 drivers +v0x2c7fcb0_0 .net/2s *"_s15", 0 0, L_0x2ac6110bca20; 1 drivers +v0x2c7fd90_0 .net *"_s19", 0 0, L_0x2e00810; 1 drivers +v0x2c7fe70_0 .net/2s *"_s21", 0 0, L_0x2ac6110bca68; 1 drivers +v0x2c7ffe0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bcab0; 1 drivers +v0x2c800c0_0 .net *"_s25", 0 0, L_0x2e00a10; 1 drivers +v0x2c801a0_0 .net *"_s28", 0 0, L_0x2e00ad0; 1 drivers +v0x2c80280_0 .net/2s *"_s30", 0 0, L_0x2ac6110bcaf8; 1 drivers +v0x2c80360_0 .net/2s *"_s32", 0 0, L_0x2ac6110bcb40; 1 drivers +v0x2c80440_0 .net *"_s34", 0 0, L_0x2e00cd0; 1 drivers +v0x2c80520_0 .net *"_s37", 0 0, L_0x2e00de0; 1 drivers +v0x2c80600_0 .net/2s *"_s39", 0 0, L_0x2ac6110bcb88; 1 drivers +v0x2c807b0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bcbd0; 1 drivers +v0x2c80850_0 .net *"_s43", 0 0, L_0x2e00f90; 1 drivers +v0x2c80930_0 .net *"_s46", 0 0, L_0x2dff410; 1 drivers +v0x2c80a10_0 .net/2s *"_s48", 0 0, L_0x2ac6110bcc18; 1 drivers +v0x2c80af0_0 .net/2s *"_s50", 0 0, L_0x2ac6110bcc60; 1 drivers +v0x2c80bd0_0 .net *"_s52", 0 0, L_0x2e015f0; 1 drivers +v0x2c80cb0_0 .net *"_s56", 0 0, L_0x2e01ae0; 1 drivers +v0x2c80d90_0 .net/2s *"_s59", 0 0, L_0x2ac6110bcca8; 1 drivers +v0x2c80e70_0 .net/2s *"_s61", 0 0, L_0x2ac6110bccf0; 1 drivers +v0x2c80f50_0 .net *"_s8", 0 0, L_0x2dfffb0; 1 drivers +v0x2c81030_0 .net "carryin", 0 0, L_0x2dfed20; 1 drivers +v0x2c810d0_0 .net "carryout", 0 0, L_0x2e08e80; 1 drivers +v0x2c81170_0 .net "carryouts", 7 0, L_0x2e01770; 1 drivers +v0x2c81280_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c81340_0 .net "result", 0 0, L_0x2e05440; 1 drivers +v0x2c81430_0 .net "results", 7 0, L_0x2e013c0; 1 drivers +v0x2c80710_0 .net "zero", 0 0, L_0x2e091e0; 1 drivers +LS_0x2e013c0_0_0 .concat8 [ 1 1 1 1], L_0x2dff480, L_0x2dffab0, L_0x2dfffb0, L_0x2e00810; +LS_0x2e013c0_0_4 .concat8 [ 1 1 1 1], L_0x2e00a10, L_0x2e00cd0, L_0x2e00f90, L_0x2e015f0; +L_0x2e013c0 .concat8 [ 4 4 0 0], LS_0x2e013c0_0_0, LS_0x2e013c0_0_4; +LS_0x2e01770_0_0 .concat8 [ 1 1 1 1], L_0x2dff730, L_0x2dffe50, L_0x2e00070, L_0x2e00660; +LS_0x2e01770_0_4 .concat8 [ 1 1 1 1], L_0x2e00ad0, L_0x2e00de0, L_0x2dff410, L_0x2e01ae0; +L_0x2e01770 .concat8 [ 4 4 0 0], LS_0x2e01770_0_0, LS_0x2e01770_0_4; +S_0x2c71360 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c710e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x130e310/d .functor OR 1, L_0x130ddf0, L_0x130e1b0, C4<0>, C4<0>; -L_0x130e310 .delay 1 (30000,30000,30000) L_0x130e310/d; -v0x1199e60_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers -v0x1199f20_0 .net "b", 0 0, L_0x130d810; alias, 1 drivers -v0x1199ff0_0 .net "c1", 0 0, L_0x130ddf0; 1 drivers -v0x119a0f0_0 .net "c2", 0 0, L_0x130e1b0; 1 drivers -v0x119a1c0_0 .net "carryin", 0 0, L_0x130d8b0; alias, 1 drivers -v0x119a2b0_0 .net "carryout", 0 0, L_0x130e310; 1 drivers -v0x119a350_0 .net "s1", 0 0, L_0x130dd30; 1 drivers -v0x119a440_0 .net "sum", 0 0, L_0x130e060; 1 drivers -S_0x11992a0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x1199030; +L_0x2dff730/d .functor OR 1, L_0x2dff210, L_0x2dff5d0, C4<0>, C4<0>; +L_0x2dff730 .delay 1 (30000,30000,30000) L_0x2dff730/d; +v0x2c72190_0 .net "a", 0 0, L_0x2e092e0; alias, 1 drivers +v0x2c72250_0 .net "b", 0 0, L_0x2dfec80; alias, 1 drivers +v0x2c72320_0 .net "c1", 0 0, L_0x2dff210; 1 drivers +v0x2c72420_0 .net "c2", 0 0, L_0x2dff5d0; 1 drivers +v0x2c724f0_0 .net "carryin", 0 0, L_0x2dfed20; alias, 1 drivers +v0x2c725e0_0 .net "carryout", 0 0, L_0x2dff730; 1 drivers +v0x2c72680_0 .net "s1", 0 0, L_0x2dff150; 1 drivers +v0x2c72770_0 .net "sum", 0 0, L_0x2dff480; 1 drivers +S_0x2c715d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c71360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x130dd30/d .functor XOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; -L_0x130dd30 .delay 1 (30000,30000,30000) L_0x130dd30/d; -L_0x130ddf0/d .functor AND 1, L_0x1317160, L_0x130d810, C4<1>, C4<1>; -L_0x130ddf0 .delay 1 (30000,30000,30000) L_0x130ddf0/d; -v0x1199500_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers -v0x11995e0_0 .net "b", 0 0, L_0x130d810; alias, 1 drivers -v0x11996a0_0 .net "carryout", 0 0, L_0x130ddf0; alias, 1 drivers -v0x1199740_0 .net "sum", 0 0, L_0x130dd30; alias, 1 drivers -S_0x1199880 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x1199030; +L_0x2dff150/d .functor XOR 1, L_0x2e092e0, L_0x2dfec80, C4<0>, C4<0>; +L_0x2dff150 .delay 1 (30000,30000,30000) L_0x2dff150/d; +L_0x2dff210/d .functor AND 1, L_0x2e092e0, L_0x2dfec80, C4<1>, C4<1>; +L_0x2dff210 .delay 1 (30000,30000,30000) L_0x2dff210/d; +v0x2c71830_0 .net "a", 0 0, L_0x2e092e0; alias, 1 drivers +v0x2c71910_0 .net "b", 0 0, L_0x2dfec80; alias, 1 drivers +v0x2c719d0_0 .net "carryout", 0 0, L_0x2dff210; alias, 1 drivers +v0x2c71a70_0 .net "sum", 0 0, L_0x2dff150; alias, 1 drivers +S_0x2c71bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c71360; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x130e060/d .functor XOR 1, L_0x130dd30, L_0x130d8b0, C4<0>, C4<0>; -L_0x130e060 .delay 1 (30000,30000,30000) L_0x130e060/d; -L_0x130e1b0/d .functor AND 1, L_0x130dd30, L_0x130d8b0, C4<1>, C4<1>; -L_0x130e1b0 .delay 1 (30000,30000,30000) L_0x130e1b0/d; -v0x1199ae0_0 .net "a", 0 0, L_0x130dd30; alias, 1 drivers -v0x1199b80_0 .net "b", 0 0, L_0x130d8b0; alias, 1 drivers -v0x1199c20_0 .net "carryout", 0 0, L_0x130e1b0; alias, 1 drivers -v0x1199cf0_0 .net "sum", 0 0, L_0x130e060; alias, 1 drivers -S_0x119a510 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x1198db0; +L_0x2dff480/d .functor XOR 1, L_0x2dff150, L_0x2dfed20, C4<0>, C4<0>; +L_0x2dff480 .delay 1 (30000,30000,30000) L_0x2dff480/d; +L_0x2dff5d0/d .functor AND 1, L_0x2dff150, L_0x2dfed20, C4<1>, C4<1>; +L_0x2dff5d0 .delay 1 (30000,30000,30000) L_0x2dff5d0/d; +v0x2c71e10_0 .net "a", 0 0, L_0x2dff150; alias, 1 drivers +v0x2c71eb0_0 .net "b", 0 0, L_0x2dfed20; alias, 1 drivers +v0x2c71f50_0 .net "carryout", 0 0, L_0x2dff5d0; alias, 1 drivers +v0x2c72020_0 .net "sum", 0 0, L_0x2dff480; alias, 1 drivers +S_0x2c72840 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c710e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x119f900_0 .net "ands", 7 0, L_0x1314de0; 1 drivers -v0x119fa10_0 .net "in", 7 0, L_0x1355d10; alias, 1 drivers -v0x119fad0_0 .net "out", 0 0, L_0x1316d00; alias, 1 drivers -v0x119fba0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x119a730 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x119a510; +v0x2c77c30_0 .net "ands", 7 0, L_0x2e06e80; 1 drivers +v0x2c77d40_0 .net "in", 7 0, L_0x2e01770; alias, 1 drivers +v0x2c77e00_0 .net "out", 0 0, L_0x2e08e80; alias, 1 drivers +v0x2c77ed0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c72a60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c72840; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x119ce60_0 .net "A", 7 0, L_0x1355d10; alias, 1 drivers -v0x119cf60_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x119d020_0 .net *"_s0", 0 0, L_0x1313700; 1 drivers -v0x119d0e0_0 .net *"_s12", 0 0, L_0x1314070; 1 drivers -v0x119d1c0_0 .net *"_s16", 0 0, L_0x13143d0; 1 drivers -v0x119d2f0_0 .net *"_s20", 0 0, L_0x13146e0; 1 drivers -v0x119d3d0_0 .net *"_s24", 0 0, L_0x1314ad0; 1 drivers -v0x119d4b0_0 .net *"_s28", 0 0, L_0x1314a60; 1 drivers -v0x119d590_0 .net *"_s4", 0 0, L_0x1313a10; 1 drivers -v0x119d700_0 .net *"_s8", 0 0, L_0x1313d60; 1 drivers -v0x119d7e0_0 .net "out", 7 0, L_0x1314de0; alias, 1 drivers -L_0x13137c0 .part L_0x1355d10, 0, 1; -L_0x1313920 .part v0x12010b0_0, 0, 1; -L_0x1313ad0 .part L_0x1355d10, 1, 1; -L_0x1313cc0 .part v0x12010b0_0, 1, 1; -L_0x1313e20 .part L_0x1355d10, 2, 1; -L_0x1313f80 .part v0x12010b0_0, 2, 1; -L_0x1314130 .part L_0x1355d10, 3, 1; -L_0x1314290 .part v0x12010b0_0, 3, 1; -L_0x1314490 .part L_0x1355d10, 4, 1; -L_0x13145f0 .part v0x12010b0_0, 4, 1; -L_0x1314750 .part L_0x1355d10, 5, 1; -L_0x13149c0 .part v0x12010b0_0, 5, 1; -L_0x1314b90 .part L_0x1355d10, 6, 1; -L_0x1314cf0 .part v0x12010b0_0, 6, 1; -LS_0x1314de0_0_0 .concat8 [ 1 1 1 1], L_0x1313700, L_0x1313a10, L_0x1313d60, L_0x1314070; -LS_0x1314de0_0_4 .concat8 [ 1 1 1 1], L_0x13143d0, L_0x13146e0, L_0x1314ad0, L_0x1314a60; -L_0x1314de0 .concat8 [ 4 4 0 0], LS_0x1314de0_0_0, LS_0x1314de0_0_4; -L_0x13151a0 .part L_0x1355d10, 7, 1; -L_0x1315390 .part v0x12010b0_0, 7, 1; -S_0x119a990 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119aba0 .param/l "i" 0 4 54, +C4<00>; -L_0x1313700/d .functor AND 1, L_0x13137c0, L_0x1313920, C4<1>, C4<1>; -L_0x1313700 .delay 1 (30000,30000,30000) L_0x1313700/d; -v0x119ac80_0 .net *"_s0", 0 0, L_0x13137c0; 1 drivers -v0x119ad60_0 .net *"_s1", 0 0, L_0x1313920; 1 drivers -S_0x119ae40 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119b050 .param/l "i" 0 4 54, +C4<01>; -L_0x1313a10/d .functor AND 1, L_0x1313ad0, L_0x1313cc0, C4<1>, C4<1>; -L_0x1313a10 .delay 1 (30000,30000,30000) L_0x1313a10/d; -v0x119b110_0 .net *"_s0", 0 0, L_0x1313ad0; 1 drivers -v0x119b1f0_0 .net *"_s1", 0 0, L_0x1313cc0; 1 drivers -S_0x119b2d0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119b4e0 .param/l "i" 0 4 54, +C4<010>; -L_0x1313d60/d .functor AND 1, L_0x1313e20, L_0x1313f80, C4<1>, C4<1>; -L_0x1313d60 .delay 1 (30000,30000,30000) L_0x1313d60/d; -v0x119b580_0 .net *"_s0", 0 0, L_0x1313e20; 1 drivers -v0x119b660_0 .net *"_s1", 0 0, L_0x1313f80; 1 drivers -S_0x119b740 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119b950 .param/l "i" 0 4 54, +C4<011>; -L_0x1314070/d .functor AND 1, L_0x1314130, L_0x1314290, C4<1>, C4<1>; -L_0x1314070 .delay 1 (30000,30000,30000) L_0x1314070/d; -v0x119ba10_0 .net *"_s0", 0 0, L_0x1314130; 1 drivers -v0x119baf0_0 .net *"_s1", 0 0, L_0x1314290; 1 drivers -S_0x119bbd0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119be30 .param/l "i" 0 4 54, +C4<0100>; -L_0x13143d0/d .functor AND 1, L_0x1314490, L_0x13145f0, C4<1>, C4<1>; -L_0x13143d0 .delay 1 (30000,30000,30000) L_0x13143d0/d; -v0x119bef0_0 .net *"_s0", 0 0, L_0x1314490; 1 drivers -v0x119bfd0_0 .net *"_s1", 0 0, L_0x13145f0; 1 drivers -S_0x119c0b0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119c2c0 .param/l "i" 0 4 54, +C4<0101>; -L_0x13146e0/d .functor AND 1, L_0x1314750, L_0x13149c0, C4<1>, C4<1>; -L_0x13146e0 .delay 1 (30000,30000,30000) L_0x13146e0/d; -v0x119c380_0 .net *"_s0", 0 0, L_0x1314750; 1 drivers -v0x119c460_0 .net *"_s1", 0 0, L_0x13149c0; 1 drivers -S_0x119c540 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119c750 .param/l "i" 0 4 54, +C4<0110>; -L_0x1314ad0/d .functor AND 1, L_0x1314b90, L_0x1314cf0, C4<1>, C4<1>; -L_0x1314ad0 .delay 1 (30000,30000,30000) L_0x1314ad0/d; -v0x119c810_0 .net *"_s0", 0 0, L_0x1314b90; 1 drivers -v0x119c8f0_0 .net *"_s1", 0 0, L_0x1314cf0; 1 drivers -S_0x119c9d0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x119a730; - .timescale -9 -12; -P_0x119cbe0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1314a60/d .functor AND 1, L_0x13151a0, L_0x1315390, C4<1>, C4<1>; -L_0x1314a60 .delay 1 (30000,30000,30000) L_0x1314a60/d; -v0x119cca0_0 .net *"_s0", 0 0, L_0x13151a0; 1 drivers -v0x119cd80_0 .net *"_s1", 0 0, L_0x1315390; 1 drivers -S_0x119d940 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x119a510; +v0x2c75190_0 .net "A", 7 0, L_0x2e01770; alias, 1 drivers +v0x2c75290_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c75350_0 .net *"_s0", 0 0, L_0x2e057a0; 1 drivers +v0x2c75410_0 .net *"_s12", 0 0, L_0x2e06110; 1 drivers +v0x2c754f0_0 .net *"_s16", 0 0, L_0x2e06470; 1 drivers +v0x2c75620_0 .net *"_s20", 0 0, L_0x2e06840; 1 drivers +v0x2c75700_0 .net *"_s24", 0 0, L_0x2e06b70; 1 drivers +v0x2c757e0_0 .net *"_s28", 0 0, L_0x2e06b00; 1 drivers +v0x2c758c0_0 .net *"_s4", 0 0, L_0x2e05af0; 1 drivers +v0x2c75a30_0 .net *"_s8", 0 0, L_0x2e05e00; 1 drivers +v0x2c75b10_0 .net "out", 7 0, L_0x2e06e80; alias, 1 drivers +L_0x2e05860 .part L_0x2e01770, 0, 1; +L_0x2e05a50 .part v0x2cdd2e0_0, 0, 1; +L_0x2e05bb0 .part L_0x2e01770, 1, 1; +L_0x2e05d10 .part v0x2cdd2e0_0, 1, 1; +L_0x2e05ec0 .part L_0x2e01770, 2, 1; +L_0x2e06020 .part v0x2cdd2e0_0, 2, 1; +L_0x2e061d0 .part L_0x2e01770, 3, 1; +L_0x2e06330 .part v0x2cdd2e0_0, 3, 1; +L_0x2e06530 .part L_0x2e01770, 4, 1; +L_0x2e067a0 .part v0x2cdd2e0_0, 4, 1; +L_0x2e068b0 .part L_0x2e01770, 5, 1; +L_0x2e06a10 .part v0x2cdd2e0_0, 5, 1; +L_0x2e06c30 .part L_0x2e01770, 6, 1; +L_0x2e06d90 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e06e80_0_0 .concat8 [ 1 1 1 1], L_0x2e057a0, L_0x2e05af0, L_0x2e05e00, L_0x2e06110; +LS_0x2e06e80_0_4 .concat8 [ 1 1 1 1], L_0x2e06470, L_0x2e06840, L_0x2e06b70, L_0x2e06b00; +L_0x2e06e80 .concat8 [ 4 4 0 0], LS_0x2e06e80_0_0, LS_0x2e06e80_0_4; +L_0x2e07240 .part L_0x2e01770, 7, 1; +L_0x2e07430 .part v0x2cdd2e0_0, 7, 1; +S_0x2c72cc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c72ed0 .param/l "i" 0 4 54, +C4<00>; +L_0x2e057a0/d .functor AND 1, L_0x2e05860, L_0x2e05a50, C4<1>, C4<1>; +L_0x2e057a0 .delay 1 (30000,30000,30000) L_0x2e057a0/d; +v0x2c72fb0_0 .net *"_s0", 0 0, L_0x2e05860; 1 drivers +v0x2c73090_0 .net *"_s1", 0 0, L_0x2e05a50; 1 drivers +S_0x2c73170 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c73380 .param/l "i" 0 4 54, +C4<01>; +L_0x2e05af0/d .functor AND 1, L_0x2e05bb0, L_0x2e05d10, C4<1>, C4<1>; +L_0x2e05af0 .delay 1 (30000,30000,30000) L_0x2e05af0/d; +v0x2c73440_0 .net *"_s0", 0 0, L_0x2e05bb0; 1 drivers +v0x2c73520_0 .net *"_s1", 0 0, L_0x2e05d10; 1 drivers +S_0x2c73600 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c73810 .param/l "i" 0 4 54, +C4<010>; +L_0x2e05e00/d .functor AND 1, L_0x2e05ec0, L_0x2e06020, C4<1>, C4<1>; +L_0x2e05e00 .delay 1 (30000,30000,30000) L_0x2e05e00/d; +v0x2c738b0_0 .net *"_s0", 0 0, L_0x2e05ec0; 1 drivers +v0x2c73990_0 .net *"_s1", 0 0, L_0x2e06020; 1 drivers +S_0x2c73a70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c73c80 .param/l "i" 0 4 54, +C4<011>; +L_0x2e06110/d .functor AND 1, L_0x2e061d0, L_0x2e06330, C4<1>, C4<1>; +L_0x2e06110 .delay 1 (30000,30000,30000) L_0x2e06110/d; +v0x2c73d40_0 .net *"_s0", 0 0, L_0x2e061d0; 1 drivers +v0x2c73e20_0 .net *"_s1", 0 0, L_0x2e06330; 1 drivers +S_0x2c73f00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c74160 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e06470/d .functor AND 1, L_0x2e06530, L_0x2e067a0, C4<1>, C4<1>; +L_0x2e06470 .delay 1 (30000,30000,30000) L_0x2e06470/d; +v0x2c74220_0 .net *"_s0", 0 0, L_0x2e06530; 1 drivers +v0x2c74300_0 .net *"_s1", 0 0, L_0x2e067a0; 1 drivers +S_0x2c743e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c745f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e06840/d .functor AND 1, L_0x2e068b0, L_0x2e06a10, C4<1>, C4<1>; +L_0x2e06840 .delay 1 (30000,30000,30000) L_0x2e06840/d; +v0x2c746b0_0 .net *"_s0", 0 0, L_0x2e068b0; 1 drivers +v0x2c74790_0 .net *"_s1", 0 0, L_0x2e06a10; 1 drivers +S_0x2c74870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c74a80 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e06b70/d .functor AND 1, L_0x2e06c30, L_0x2e06d90, C4<1>, C4<1>; +L_0x2e06b70 .delay 1 (30000,30000,30000) L_0x2e06b70/d; +v0x2c74b40_0 .net *"_s0", 0 0, L_0x2e06c30; 1 drivers +v0x2c74c20_0 .net *"_s1", 0 0, L_0x2e06d90; 1 drivers +S_0x2c74d00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c72a60; + .timescale -9 -12; +P_0x2c74f10 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e06b00/d .functor AND 1, L_0x2e07240, L_0x2e07430, C4<1>, C4<1>; +L_0x2e06b00 .delay 1 (30000,30000,30000) L_0x2e06b00/d; +v0x2c74fd0_0 .net *"_s0", 0 0, L_0x2e07240; 1 drivers +v0x2c750b0_0 .net *"_s1", 0 0, L_0x2e07430; 1 drivers +S_0x2c75c70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c72840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1316d00/d .functor OR 1, L_0x1316dc0, L_0x1316f70, C4<0>, C4<0>; -L_0x1316d00 .delay 1 (30000,30000,30000) L_0x1316d00/d; -v0x119f490_0 .net *"_s10", 0 0, L_0x1316dc0; 1 drivers -v0x119f570_0 .net *"_s12", 0 0, L_0x1316f70; 1 drivers -v0x119f650_0 .net "in", 7 0, L_0x1314de0; alias, 1 drivers -v0x119f720_0 .net "ors", 1 0, L_0x1316b20; 1 drivers -v0x119f7e0_0 .net "out", 0 0, L_0x1316d00; alias, 1 drivers -L_0x1315fd0 .part L_0x1314de0, 0, 4; -L_0x1316b20 .concat8 [ 1 1 0 0], L_0x1315cc0, L_0x1316810; -L_0x1316c60 .part L_0x1314de0, 4, 4; -L_0x1316dc0 .part L_0x1316b20, 0, 1; -L_0x1316f70 .part L_0x1316b20, 1, 1; -S_0x119db00 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x119d940; +L_0x2e08e80/d .functor OR 1, L_0x2e08f40, L_0x2e090f0, C4<0>, C4<0>; +L_0x2e08e80 .delay 1 (30000,30000,30000) L_0x2e08e80/d; +v0x2c777c0_0 .net *"_s10", 0 0, L_0x2e08f40; 1 drivers +v0x2c778a0_0 .net *"_s12", 0 0, L_0x2e090f0; 1 drivers +v0x2c77980_0 .net "in", 7 0, L_0x2e06e80; alias, 1 drivers +v0x2c77a50_0 .net "ors", 1 0, L_0x2e08ca0; 1 drivers +v0x2c77b10_0 .net "out", 0 0, L_0x2e08e80; alias, 1 drivers +L_0x2e08070 .part L_0x2e06e80, 0, 4; +L_0x2e08ca0 .concat8 [ 1 1 0 0], L_0x2e07d60, L_0x2e08990; +L_0x2e08de0 .part L_0x2e06e80, 4, 4; +L_0x2e08f40 .part L_0x2e08ca0, 0, 1; +L_0x2e090f0 .part L_0x2e08ca0, 1, 1; +S_0x2c75e30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c75c70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1315480/d .functor OR 1, L_0x1315540, L_0x13156a0, C4<0>, C4<0>; -L_0x1315480 .delay 1 (30000,30000,30000) L_0x1315480/d; -L_0x13158d0/d .functor OR 1, L_0x13159e0, L_0x1315b40, C4<0>, C4<0>; -L_0x13158d0 .delay 1 (30000,30000,30000) L_0x13158d0/d; -L_0x1315cc0/d .functor OR 1, L_0x1315d30, L_0x1315ee0, C4<0>, C4<0>; -L_0x1315cc0 .delay 1 (30000,30000,30000) L_0x1315cc0/d; -v0x119dd50_0 .net *"_s0", 0 0, L_0x1315480; 1 drivers -v0x119de50_0 .net *"_s10", 0 0, L_0x13159e0; 1 drivers -v0x119df30_0 .net *"_s12", 0 0, L_0x1315b40; 1 drivers -v0x119dff0_0 .net *"_s14", 0 0, L_0x1315d30; 1 drivers -v0x119e0d0_0 .net *"_s16", 0 0, L_0x1315ee0; 1 drivers -v0x119e200_0 .net *"_s3", 0 0, L_0x1315540; 1 drivers -v0x119e2e0_0 .net *"_s5", 0 0, L_0x13156a0; 1 drivers -v0x119e3c0_0 .net *"_s6", 0 0, L_0x13158d0; 1 drivers -v0x119e4a0_0 .net "in", 3 0, L_0x1315fd0; 1 drivers -v0x119e610_0 .net "ors", 1 0, L_0x13157e0; 1 drivers -v0x119e6f0_0 .net "out", 0 0, L_0x1315cc0; 1 drivers -L_0x1315540 .part L_0x1315fd0, 0, 1; -L_0x13156a0 .part L_0x1315fd0, 1, 1; -L_0x13157e0 .concat8 [ 1 1 0 0], L_0x1315480, L_0x13158d0; -L_0x13159e0 .part L_0x1315fd0, 2, 1; -L_0x1315b40 .part L_0x1315fd0, 3, 1; -L_0x1315d30 .part L_0x13157e0, 0, 1; -L_0x1315ee0 .part L_0x13157e0, 1, 1; -S_0x119e810 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x119d940; +L_0x2e07520/d .functor OR 1, L_0x2e075e0, L_0x2e07740, C4<0>, C4<0>; +L_0x2e07520 .delay 1 (30000,30000,30000) L_0x2e07520/d; +L_0x2e07970/d .functor OR 1, L_0x2e07a80, L_0x2e07be0, C4<0>, C4<0>; +L_0x2e07970 .delay 1 (30000,30000,30000) L_0x2e07970/d; +L_0x2e07d60/d .functor OR 1, L_0x2e07dd0, L_0x2e07f80, C4<0>, C4<0>; +L_0x2e07d60 .delay 1 (30000,30000,30000) L_0x2e07d60/d; +v0x2c76080_0 .net *"_s0", 0 0, L_0x2e07520; 1 drivers +v0x2c76180_0 .net *"_s10", 0 0, L_0x2e07a80; 1 drivers +v0x2c76260_0 .net *"_s12", 0 0, L_0x2e07be0; 1 drivers +v0x2c76320_0 .net *"_s14", 0 0, L_0x2e07dd0; 1 drivers +v0x2c76400_0 .net *"_s16", 0 0, L_0x2e07f80; 1 drivers +v0x2c76530_0 .net *"_s3", 0 0, L_0x2e075e0; 1 drivers +v0x2c76610_0 .net *"_s5", 0 0, L_0x2e07740; 1 drivers +v0x2c766f0_0 .net *"_s6", 0 0, L_0x2e07970; 1 drivers +v0x2c767d0_0 .net "in", 3 0, L_0x2e08070; 1 drivers +v0x2c76940_0 .net "ors", 1 0, L_0x2e07880; 1 drivers +v0x2c76a20_0 .net "out", 0 0, L_0x2e07d60; 1 drivers +L_0x2e075e0 .part L_0x2e08070, 0, 1; +L_0x2e07740 .part L_0x2e08070, 1, 1; +L_0x2e07880 .concat8 [ 1 1 0 0], L_0x2e07520, L_0x2e07970; +L_0x2e07a80 .part L_0x2e08070, 2, 1; +L_0x2e07be0 .part L_0x2e08070, 3, 1; +L_0x2e07dd0 .part L_0x2e07880, 0, 1; +L_0x2e07f80 .part L_0x2e07880, 1, 1; +S_0x2c76b40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c75c70; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1307660/d .functor OR 1, L_0x1316100, L_0x13161f0, C4<0>, C4<0>; -L_0x1307660 .delay 1 (30000,30000,30000) L_0x1307660/d; -L_0x1316420/d .functor OR 1, L_0x1316530, L_0x1316690, C4<0>, C4<0>; -L_0x1316420 .delay 1 (30000,30000,30000) L_0x1316420/d; -L_0x1316810/d .functor OR 1, L_0x1316880, L_0x1316a30, C4<0>, C4<0>; -L_0x1316810 .delay 1 (30000,30000,30000) L_0x1316810/d; -v0x119e9d0_0 .net *"_s0", 0 0, L_0x1307660; 1 drivers -v0x119ead0_0 .net *"_s10", 0 0, L_0x1316530; 1 drivers -v0x119ebb0_0 .net *"_s12", 0 0, L_0x1316690; 1 drivers -v0x119ec70_0 .net *"_s14", 0 0, L_0x1316880; 1 drivers -v0x119ed50_0 .net *"_s16", 0 0, L_0x1316a30; 1 drivers -v0x119ee80_0 .net *"_s3", 0 0, L_0x1316100; 1 drivers -v0x119ef60_0 .net *"_s5", 0 0, L_0x13161f0; 1 drivers -v0x119f040_0 .net *"_s6", 0 0, L_0x1316420; 1 drivers -v0x119f120_0 .net "in", 3 0, L_0x1316c60; 1 drivers -v0x119f290_0 .net "ors", 1 0, L_0x1316330; 1 drivers -v0x119f370_0 .net "out", 0 0, L_0x1316810; 1 drivers -L_0x1316100 .part L_0x1316c60, 0, 1; -L_0x13161f0 .part L_0x1316c60, 1, 1; -L_0x1316330 .concat8 [ 1 1 0 0], L_0x1307660, L_0x1316420; -L_0x1316530 .part L_0x1316c60, 2, 1; -L_0x1316690 .part L_0x1316c60, 3, 1; -L_0x1316880 .part L_0x1316330, 0, 1; -L_0x1316a30 .part L_0x1316330, 1, 1; -S_0x119fc80 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x1198db0; +L_0x2e081a0/d .functor OR 1, L_0x2e08210, L_0x2e08370, C4<0>, C4<0>; +L_0x2e081a0 .delay 1 (30000,30000,30000) L_0x2e081a0/d; +L_0x2e085a0/d .functor OR 1, L_0x2e086b0, L_0x2e08810, C4<0>, C4<0>; +L_0x2e085a0 .delay 1 (30000,30000,30000) L_0x2e085a0/d; +L_0x2e08990/d .functor OR 1, L_0x2e08a00, L_0x2e08bb0, C4<0>, C4<0>; +L_0x2e08990 .delay 1 (30000,30000,30000) L_0x2e08990/d; +v0x2c76d00_0 .net *"_s0", 0 0, L_0x2e081a0; 1 drivers +v0x2c76e00_0 .net *"_s10", 0 0, L_0x2e086b0; 1 drivers +v0x2c76ee0_0 .net *"_s12", 0 0, L_0x2e08810; 1 drivers +v0x2c76fa0_0 .net *"_s14", 0 0, L_0x2e08a00; 1 drivers +v0x2c77080_0 .net *"_s16", 0 0, L_0x2e08bb0; 1 drivers +v0x2c771b0_0 .net *"_s3", 0 0, L_0x2e08210; 1 drivers +v0x2c77290_0 .net *"_s5", 0 0, L_0x2e08370; 1 drivers +v0x2c77370_0 .net *"_s6", 0 0, L_0x2e085a0; 1 drivers +v0x2c77450_0 .net "in", 3 0, L_0x2e08de0; 1 drivers +v0x2c775c0_0 .net "ors", 1 0, L_0x2e084b0; 1 drivers +v0x2c776a0_0 .net "out", 0 0, L_0x2e08990; 1 drivers +L_0x2e08210 .part L_0x2e08de0, 0, 1; +L_0x2e08370 .part L_0x2e08de0, 1, 1; +L_0x2e084b0 .concat8 [ 1 1 0 0], L_0x2e081a0, L_0x2e085a0; +L_0x2e086b0 .part L_0x2e08de0, 2, 1; +L_0x2e08810 .part L_0x2e08de0, 3, 1; +L_0x2e08a00 .part L_0x2e084b0, 0, 1; +L_0x2e08bb0 .part L_0x2e084b0, 1, 1; +S_0x2c77fb0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c710e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11a50b0_0 .net "ands", 7 0, L_0x13113a0; 1 drivers -v0x11a51c0_0 .net "in", 7 0, L_0x130f8e0; alias, 1 drivers -v0x11a5280_0 .net "out", 0 0, L_0x13133a0; alias, 1 drivers -v0x11a5350_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x119fed0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x119fc80; +v0x2c7d3e0_0 .net "ands", 7 0, L_0x2e03440; 1 drivers +v0x2c7d4f0_0 .net "in", 7 0, L_0x2e013c0; alias, 1 drivers +v0x2c7d5b0_0 .net "out", 0 0, L_0x2e05440; alias, 1 drivers +v0x2c7d680_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c78200 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c77fb0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11a2610_0 .net "A", 7 0, L_0x130f8e0; alias, 1 drivers -v0x11a2710_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11a27d0_0 .net *"_s0", 0 0, L_0x130fc70; 1 drivers -v0x11a2890_0 .net *"_s12", 0 0, L_0x1310630; 1 drivers -v0x11a2970_0 .net *"_s16", 0 0, L_0x1310990; 1 drivers -v0x11a2aa0_0 .net *"_s20", 0 0, L_0x1310d60; 1 drivers -v0x11a2b80_0 .net *"_s24", 0 0, L_0x1311090; 1 drivers -v0x11a2c60_0 .net *"_s28", 0 0, L_0x1311020; 1 drivers -v0x11a2d40_0 .net *"_s4", 0 0, L_0x1310010; 1 drivers -v0x11a2eb0_0 .net *"_s8", 0 0, L_0x1310320; 1 drivers -v0x11a2f90_0 .net "out", 7 0, L_0x13113a0; alias, 1 drivers -L_0x130fd80 .part L_0x130f8e0, 0, 1; -L_0x130ff70 .part v0x12010b0_0, 0, 1; -L_0x13100d0 .part L_0x130f8e0, 1, 1; -L_0x1310230 .part v0x12010b0_0, 1, 1; -L_0x13103e0 .part L_0x130f8e0, 2, 1; -L_0x1310540 .part v0x12010b0_0, 2, 1; -L_0x13106f0 .part L_0x130f8e0, 3, 1; -L_0x1310850 .part v0x12010b0_0, 3, 1; -L_0x1310a50 .part L_0x130f8e0, 4, 1; -L_0x1310cc0 .part v0x12010b0_0, 4, 1; -L_0x1310dd0 .part L_0x130f8e0, 5, 1; -L_0x1310f30 .part v0x12010b0_0, 5, 1; -L_0x1311150 .part L_0x130f8e0, 6, 1; -L_0x13112b0 .part v0x12010b0_0, 6, 1; -LS_0x13113a0_0_0 .concat8 [ 1 1 1 1], L_0x130fc70, L_0x1310010, L_0x1310320, L_0x1310630; -LS_0x13113a0_0_4 .concat8 [ 1 1 1 1], L_0x1310990, L_0x1310d60, L_0x1311090, L_0x1311020; -L_0x13113a0 .concat8 [ 4 4 0 0], LS_0x13113a0_0_0, LS_0x13113a0_0_4; -L_0x1311760 .part L_0x130f8e0, 7, 1; -L_0x1311950 .part v0x12010b0_0, 7, 1; -S_0x11a0110 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a0320 .param/l "i" 0 4 54, +C4<00>; -L_0x130fc70/d .functor AND 1, L_0x130fd80, L_0x130ff70, C4<1>, C4<1>; -L_0x130fc70 .delay 1 (30000,30000,30000) L_0x130fc70/d; -v0x11a0400_0 .net *"_s0", 0 0, L_0x130fd80; 1 drivers -v0x11a04e0_0 .net *"_s1", 0 0, L_0x130ff70; 1 drivers -S_0x11a05c0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a07d0 .param/l "i" 0 4 54, +C4<01>; -L_0x1310010/d .functor AND 1, L_0x13100d0, L_0x1310230, C4<1>, C4<1>; -L_0x1310010 .delay 1 (30000,30000,30000) L_0x1310010/d; -v0x11a0890_0 .net *"_s0", 0 0, L_0x13100d0; 1 drivers -v0x11a0970_0 .net *"_s1", 0 0, L_0x1310230; 1 drivers -S_0x11a0a50 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a0c90 .param/l "i" 0 4 54, +C4<010>; -L_0x1310320/d .functor AND 1, L_0x13103e0, L_0x1310540, C4<1>, C4<1>; -L_0x1310320 .delay 1 (30000,30000,30000) L_0x1310320/d; -v0x11a0d30_0 .net *"_s0", 0 0, L_0x13103e0; 1 drivers -v0x11a0e10_0 .net *"_s1", 0 0, L_0x1310540; 1 drivers -S_0x11a0ef0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a1100 .param/l "i" 0 4 54, +C4<011>; -L_0x1310630/d .functor AND 1, L_0x13106f0, L_0x1310850, C4<1>, C4<1>; -L_0x1310630 .delay 1 (30000,30000,30000) L_0x1310630/d; -v0x11a11c0_0 .net *"_s0", 0 0, L_0x13106f0; 1 drivers -v0x11a12a0_0 .net *"_s1", 0 0, L_0x1310850; 1 drivers -S_0x11a1380 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a15e0 .param/l "i" 0 4 54, +C4<0100>; -L_0x1310990/d .functor AND 1, L_0x1310a50, L_0x1310cc0, C4<1>, C4<1>; -L_0x1310990 .delay 1 (30000,30000,30000) L_0x1310990/d; -v0x11a16a0_0 .net *"_s0", 0 0, L_0x1310a50; 1 drivers -v0x11a1780_0 .net *"_s1", 0 0, L_0x1310cc0; 1 drivers -S_0x11a1860 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a1a70 .param/l "i" 0 4 54, +C4<0101>; -L_0x1310d60/d .functor AND 1, L_0x1310dd0, L_0x1310f30, C4<1>, C4<1>; -L_0x1310d60 .delay 1 (30000,30000,30000) L_0x1310d60/d; -v0x11a1b30_0 .net *"_s0", 0 0, L_0x1310dd0; 1 drivers -v0x11a1c10_0 .net *"_s1", 0 0, L_0x1310f30; 1 drivers -S_0x11a1cf0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a1f00 .param/l "i" 0 4 54, +C4<0110>; -L_0x1311090/d .functor AND 1, L_0x1311150, L_0x13112b0, C4<1>, C4<1>; -L_0x1311090 .delay 1 (30000,30000,30000) L_0x1311090/d; -v0x11a1fc0_0 .net *"_s0", 0 0, L_0x1311150; 1 drivers -v0x11a20a0_0 .net *"_s1", 0 0, L_0x13112b0; 1 drivers -S_0x11a2180 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x119fed0; - .timescale -9 -12; -P_0x11a2390 .param/l "i" 0 4 54, +C4<0111>; -L_0x1311020/d .functor AND 1, L_0x1311760, L_0x1311950, C4<1>, C4<1>; -L_0x1311020 .delay 1 (30000,30000,30000) L_0x1311020/d; -v0x11a2450_0 .net *"_s0", 0 0, L_0x1311760; 1 drivers -v0x11a2530_0 .net *"_s1", 0 0, L_0x1311950; 1 drivers -S_0x11a30f0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x119fc80; +v0x2c7a940_0 .net "A", 7 0, L_0x2e013c0; alias, 1 drivers +v0x2c7aa40_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c7ab00_0 .net *"_s0", 0 0, L_0x2e01c90; 1 drivers +v0x2c7abc0_0 .net *"_s12", 0 0, L_0x2e02650; 1 drivers +v0x2c7aca0_0 .net *"_s16", 0 0, L_0x2e029b0; 1 drivers +v0x2c7add0_0 .net *"_s20", 0 0, L_0x2e02d80; 1 drivers +v0x2c7aeb0_0 .net *"_s24", 0 0, L_0x2e030b0; 1 drivers +v0x2c7af90_0 .net *"_s28", 0 0, L_0x2e03040; 1 drivers +v0x2c7b070_0 .net *"_s4", 0 0, L_0x2e02030; 1 drivers +v0x2c7b1e0_0 .net *"_s8", 0 0, L_0x2e02340; 1 drivers +v0x2c7b2c0_0 .net "out", 7 0, L_0x2e03440; alias, 1 drivers +L_0x2e01da0 .part L_0x2e013c0, 0, 1; +L_0x2e01f90 .part v0x2cdd2e0_0, 0, 1; +L_0x2e020f0 .part L_0x2e013c0, 1, 1; +L_0x2e02250 .part v0x2cdd2e0_0, 1, 1; +L_0x2e02400 .part L_0x2e013c0, 2, 1; +L_0x2e02560 .part v0x2cdd2e0_0, 2, 1; +L_0x2e02710 .part L_0x2e013c0, 3, 1; +L_0x2e02870 .part v0x2cdd2e0_0, 3, 1; +L_0x2e02a70 .part L_0x2e013c0, 4, 1; +L_0x2e02ce0 .part v0x2cdd2e0_0, 4, 1; +L_0x2e02df0 .part L_0x2e013c0, 5, 1; +L_0x2e02f50 .part v0x2cdd2e0_0, 5, 1; +L_0x2e03170 .part L_0x2e013c0, 6, 1; +L_0x2e032d0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e03440_0_0 .concat8 [ 1 1 1 1], L_0x2e01c90, L_0x2e02030, L_0x2e02340, L_0x2e02650; +LS_0x2e03440_0_4 .concat8 [ 1 1 1 1], L_0x2e029b0, L_0x2e02d80, L_0x2e030b0, L_0x2e03040; +L_0x2e03440 .concat8 [ 4 4 0 0], LS_0x2e03440_0_0, LS_0x2e03440_0_4; +L_0x2e03800 .part L_0x2e013c0, 7, 1; +L_0x2e039f0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c78440 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c78650 .param/l "i" 0 4 54, +C4<00>; +L_0x2e01c90/d .functor AND 1, L_0x2e01da0, L_0x2e01f90, C4<1>, C4<1>; +L_0x2e01c90 .delay 1 (30000,30000,30000) L_0x2e01c90/d; +v0x2c78730_0 .net *"_s0", 0 0, L_0x2e01da0; 1 drivers +v0x2c78810_0 .net *"_s1", 0 0, L_0x2e01f90; 1 drivers +S_0x2c788f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c78b00 .param/l "i" 0 4 54, +C4<01>; +L_0x2e02030/d .functor AND 1, L_0x2e020f0, L_0x2e02250, C4<1>, C4<1>; +L_0x2e02030 .delay 1 (30000,30000,30000) L_0x2e02030/d; +v0x2c78bc0_0 .net *"_s0", 0 0, L_0x2e020f0; 1 drivers +v0x2c78ca0_0 .net *"_s1", 0 0, L_0x2e02250; 1 drivers +S_0x2c78d80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c78fc0 .param/l "i" 0 4 54, +C4<010>; +L_0x2e02340/d .functor AND 1, L_0x2e02400, L_0x2e02560, C4<1>, C4<1>; +L_0x2e02340 .delay 1 (30000,30000,30000) L_0x2e02340/d; +v0x2c79060_0 .net *"_s0", 0 0, L_0x2e02400; 1 drivers +v0x2c79140_0 .net *"_s1", 0 0, L_0x2e02560; 1 drivers +S_0x2c79220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c79430 .param/l "i" 0 4 54, +C4<011>; +L_0x2e02650/d .functor AND 1, L_0x2e02710, L_0x2e02870, C4<1>, C4<1>; +L_0x2e02650 .delay 1 (30000,30000,30000) L_0x2e02650/d; +v0x2c794f0_0 .net *"_s0", 0 0, L_0x2e02710; 1 drivers +v0x2c795d0_0 .net *"_s1", 0 0, L_0x2e02870; 1 drivers +S_0x2c796b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c79910 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e029b0/d .functor AND 1, L_0x2e02a70, L_0x2e02ce0, C4<1>, C4<1>; +L_0x2e029b0 .delay 1 (30000,30000,30000) L_0x2e029b0/d; +v0x2c799d0_0 .net *"_s0", 0 0, L_0x2e02a70; 1 drivers +v0x2c79ab0_0 .net *"_s1", 0 0, L_0x2e02ce0; 1 drivers +S_0x2c79b90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c79da0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e02d80/d .functor AND 1, L_0x2e02df0, L_0x2e02f50, C4<1>, C4<1>; +L_0x2e02d80 .delay 1 (30000,30000,30000) L_0x2e02d80/d; +v0x2c79e60_0 .net *"_s0", 0 0, L_0x2e02df0; 1 drivers +v0x2c79f40_0 .net *"_s1", 0 0, L_0x2e02f50; 1 drivers +S_0x2c7a020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c7a230 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e030b0/d .functor AND 1, L_0x2e03170, L_0x2e032d0, C4<1>, C4<1>; +L_0x2e030b0 .delay 1 (30000,30000,30000) L_0x2e030b0/d; +v0x2c7a2f0_0 .net *"_s0", 0 0, L_0x2e03170; 1 drivers +v0x2c7a3d0_0 .net *"_s1", 0 0, L_0x2e032d0; 1 drivers +S_0x2c7a4b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c78200; + .timescale -9 -12; +P_0x2c7a6c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e03040/d .functor AND 1, L_0x2e03800, L_0x2e039f0, C4<1>, C4<1>; +L_0x2e03040 .delay 1 (30000,30000,30000) L_0x2e03040/d; +v0x2c7a780_0 .net *"_s0", 0 0, L_0x2e03800; 1 drivers +v0x2c7a860_0 .net *"_s1", 0 0, L_0x2e039f0; 1 drivers +S_0x2c7b420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c77fb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x13133a0/d .functor OR 1, L_0x1313460, L_0x1313610, C4<0>, C4<0>; -L_0x13133a0 .delay 1 (30000,30000,30000) L_0x13133a0/d; -v0x11a4c40_0 .net *"_s10", 0 0, L_0x1313460; 1 drivers -v0x11a4d20_0 .net *"_s12", 0 0, L_0x1313610; 1 drivers -v0x11a4e00_0 .net "in", 7 0, L_0x13113a0; alias, 1 drivers -v0x11a4ed0_0 .net "ors", 1 0, L_0x13131c0; 1 drivers -v0x11a4f90_0 .net "out", 0 0, L_0x13133a0; alias, 1 drivers -L_0x1312590 .part L_0x13113a0, 0, 4; -L_0x13131c0 .concat8 [ 1 1 0 0], L_0x1312280, L_0x1312eb0; -L_0x1313300 .part L_0x13113a0, 4, 4; -L_0x1313460 .part L_0x13131c0, 0, 1; -L_0x1313610 .part L_0x13131c0, 1, 1; -S_0x11a32b0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11a30f0; +L_0x2e05440/d .functor OR 1, L_0x2e05500, L_0x2e056b0, C4<0>, C4<0>; +L_0x2e05440 .delay 1 (30000,30000,30000) L_0x2e05440/d; +v0x2c7cf70_0 .net *"_s10", 0 0, L_0x2e05500; 1 drivers +v0x2c7d050_0 .net *"_s12", 0 0, L_0x2e056b0; 1 drivers +v0x2c7d130_0 .net "in", 7 0, L_0x2e03440; alias, 1 drivers +v0x2c7d200_0 .net "ors", 1 0, L_0x2e05260; 1 drivers +v0x2c7d2c0_0 .net "out", 0 0, L_0x2e05440; alias, 1 drivers +L_0x2e04630 .part L_0x2e03440, 0, 4; +L_0x2e05260 .concat8 [ 1 1 0 0], L_0x2e04320, L_0x2e04f50; +L_0x2e053a0 .part L_0x2e03440, 4, 4; +L_0x2e05500 .part L_0x2e05260, 0, 1; +L_0x2e056b0 .part L_0x2e05260, 1, 1; +S_0x2c7b5e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c7b420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1311a40/d .functor OR 1, L_0x1311b00, L_0x1311c60, C4<0>, C4<0>; -L_0x1311a40 .delay 1 (30000,30000,30000) L_0x1311a40/d; -L_0x1311e90/d .functor OR 1, L_0x1311fa0, L_0x1312100, C4<0>, C4<0>; -L_0x1311e90 .delay 1 (30000,30000,30000) L_0x1311e90/d; -L_0x1312280/d .functor OR 1, L_0x13122f0, L_0x13124a0, C4<0>, C4<0>; -L_0x1312280 .delay 1 (30000,30000,30000) L_0x1312280/d; -v0x11a3500_0 .net *"_s0", 0 0, L_0x1311a40; 1 drivers -v0x11a3600_0 .net *"_s10", 0 0, L_0x1311fa0; 1 drivers -v0x11a36e0_0 .net *"_s12", 0 0, L_0x1312100; 1 drivers -v0x11a37a0_0 .net *"_s14", 0 0, L_0x13122f0; 1 drivers -v0x11a3880_0 .net *"_s16", 0 0, L_0x13124a0; 1 drivers -v0x11a39b0_0 .net *"_s3", 0 0, L_0x1311b00; 1 drivers -v0x11a3a90_0 .net *"_s5", 0 0, L_0x1311c60; 1 drivers -v0x11a3b70_0 .net *"_s6", 0 0, L_0x1311e90; 1 drivers -v0x11a3c50_0 .net "in", 3 0, L_0x1312590; 1 drivers -v0x11a3dc0_0 .net "ors", 1 0, L_0x1311da0; 1 drivers -v0x11a3ea0_0 .net "out", 0 0, L_0x1312280; 1 drivers -L_0x1311b00 .part L_0x1312590, 0, 1; -L_0x1311c60 .part L_0x1312590, 1, 1; -L_0x1311da0 .concat8 [ 1 1 0 0], L_0x1311a40, L_0x1311e90; -L_0x1311fa0 .part L_0x1312590, 2, 1; -L_0x1312100 .part L_0x1312590, 3, 1; -L_0x13122f0 .part L_0x1311da0, 0, 1; -L_0x13124a0 .part L_0x1311da0, 1, 1; -S_0x11a3fc0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11a30f0; +L_0x2e03ae0/d .functor OR 1, L_0x2e03ba0, L_0x2e03d00, C4<0>, C4<0>; +L_0x2e03ae0 .delay 1 (30000,30000,30000) L_0x2e03ae0/d; +L_0x2e03f30/d .functor OR 1, L_0x2e04040, L_0x2e041a0, C4<0>, C4<0>; +L_0x2e03f30 .delay 1 (30000,30000,30000) L_0x2e03f30/d; +L_0x2e04320/d .functor OR 1, L_0x2e04390, L_0x2e04540, C4<0>, C4<0>; +L_0x2e04320 .delay 1 (30000,30000,30000) L_0x2e04320/d; +v0x2c7b830_0 .net *"_s0", 0 0, L_0x2e03ae0; 1 drivers +v0x2c7b930_0 .net *"_s10", 0 0, L_0x2e04040; 1 drivers +v0x2c7ba10_0 .net *"_s12", 0 0, L_0x2e041a0; 1 drivers +v0x2c7bad0_0 .net *"_s14", 0 0, L_0x2e04390; 1 drivers +v0x2c7bbb0_0 .net *"_s16", 0 0, L_0x2e04540; 1 drivers +v0x2c7bce0_0 .net *"_s3", 0 0, L_0x2e03ba0; 1 drivers +v0x2c7bdc0_0 .net *"_s5", 0 0, L_0x2e03d00; 1 drivers +v0x2c7bea0_0 .net *"_s6", 0 0, L_0x2e03f30; 1 drivers +v0x2c7bf80_0 .net "in", 3 0, L_0x2e04630; 1 drivers +v0x2c7c0f0_0 .net "ors", 1 0, L_0x2e03e40; 1 drivers +v0x2c7c1d0_0 .net "out", 0 0, L_0x2e04320; 1 drivers +L_0x2e03ba0 .part L_0x2e04630, 0, 1; +L_0x2e03d00 .part L_0x2e04630, 1, 1; +L_0x2e03e40 .concat8 [ 1 1 0 0], L_0x2e03ae0, L_0x2e03f30; +L_0x2e04040 .part L_0x2e04630, 2, 1; +L_0x2e041a0 .part L_0x2e04630, 3, 1; +L_0x2e04390 .part L_0x2e03e40, 0, 1; +L_0x2e04540 .part L_0x2e03e40, 1, 1; +S_0x2c7c2f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c7b420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x13126c0/d .functor OR 1, L_0x1312730, L_0x1312890, C4<0>, C4<0>; -L_0x13126c0 .delay 1 (30000,30000,30000) L_0x13126c0/d; -L_0x1312ac0/d .functor OR 1, L_0x1312bd0, L_0x1312d30, C4<0>, C4<0>; -L_0x1312ac0 .delay 1 (30000,30000,30000) L_0x1312ac0/d; -L_0x1312eb0/d .functor OR 1, L_0x1312f20, L_0x13130d0, C4<0>, C4<0>; -L_0x1312eb0 .delay 1 (30000,30000,30000) L_0x1312eb0/d; -v0x11a4180_0 .net *"_s0", 0 0, L_0x13126c0; 1 drivers -v0x11a4280_0 .net *"_s10", 0 0, L_0x1312bd0; 1 drivers -v0x11a4360_0 .net *"_s12", 0 0, L_0x1312d30; 1 drivers -v0x11a4420_0 .net *"_s14", 0 0, L_0x1312f20; 1 drivers -v0x11a4500_0 .net *"_s16", 0 0, L_0x13130d0; 1 drivers -v0x11a4630_0 .net *"_s3", 0 0, L_0x1312730; 1 drivers -v0x11a4710_0 .net *"_s5", 0 0, L_0x1312890; 1 drivers -v0x11a47f0_0 .net *"_s6", 0 0, L_0x1312ac0; 1 drivers -v0x11a48d0_0 .net "in", 3 0, L_0x1313300; 1 drivers -v0x11a4a40_0 .net "ors", 1 0, L_0x13129d0; 1 drivers -v0x11a4b20_0 .net "out", 0 0, L_0x1312eb0; 1 drivers -L_0x1312730 .part L_0x1313300, 0, 1; -L_0x1312890 .part L_0x1313300, 1, 1; -L_0x13129d0 .concat8 [ 1 1 0 0], L_0x13126c0, L_0x1312ac0; -L_0x1312bd0 .part L_0x1313300, 2, 1; -L_0x1312d30 .part L_0x1313300, 3, 1; -L_0x1312f20 .part L_0x13129d0, 0, 1; -L_0x13130d0 .part L_0x13129d0, 1, 1; -S_0x11a5430 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1198db0; +L_0x2e04760/d .functor OR 1, L_0x2e047d0, L_0x2e04930, C4<0>, C4<0>; +L_0x2e04760 .delay 1 (30000,30000,30000) L_0x2e04760/d; +L_0x2e04b60/d .functor OR 1, L_0x2e04c70, L_0x2e04dd0, C4<0>, C4<0>; +L_0x2e04b60 .delay 1 (30000,30000,30000) L_0x2e04b60/d; +L_0x2e04f50/d .functor OR 1, L_0x2e04fc0, L_0x2e05170, C4<0>, C4<0>; +L_0x2e04f50 .delay 1 (30000,30000,30000) L_0x2e04f50/d; +v0x2c7c4b0_0 .net *"_s0", 0 0, L_0x2e04760; 1 drivers +v0x2c7c5b0_0 .net *"_s10", 0 0, L_0x2e04c70; 1 drivers +v0x2c7c690_0 .net *"_s12", 0 0, L_0x2e04dd0; 1 drivers +v0x2c7c750_0 .net *"_s14", 0 0, L_0x2e04fc0; 1 drivers +v0x2c7c830_0 .net *"_s16", 0 0, L_0x2e05170; 1 drivers +v0x2c7c960_0 .net *"_s3", 0 0, L_0x2e047d0; 1 drivers +v0x2c7ca40_0 .net *"_s5", 0 0, L_0x2e04930; 1 drivers +v0x2c7cb20_0 .net *"_s6", 0 0, L_0x2e04b60; 1 drivers +v0x2c7cc00_0 .net "in", 3 0, L_0x2e053a0; 1 drivers +v0x2c7cd70_0 .net "ors", 1 0, L_0x2e04a70; 1 drivers +v0x2c7ce50_0 .net "out", 0 0, L_0x2e04f50; 1 drivers +L_0x2e047d0 .part L_0x2e053a0, 0, 1; +L_0x2e04930 .part L_0x2e053a0, 1, 1; +L_0x2e04a70 .concat8 [ 1 1 0 0], L_0x2e04760, L_0x2e04b60; +L_0x2e04c70 .part L_0x2e053a0, 2, 1; +L_0x2e04dd0 .part L_0x2e053a0, 3, 1; +L_0x2e04fc0 .part L_0x2e04a70, 0, 1; +L_0x2e05170 .part L_0x2e04a70, 1, 1; +S_0x2c7d760 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c710e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -14966,80 +15836,80 @@ S_0x11a5430 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x1198db0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x130ec50/d .functor XNOR 1, L_0x1317160, L_0x130d810, C4<0>, C4<0>; -L_0x130ec50 .delay 1 (20000,20000,20000) L_0x130ec50/d; -L_0x130eec0/d .functor AND 1, L_0x1317160, L_0x130db40, C4<1>, C4<1>; -L_0x130eec0 .delay 1 (30000,30000,30000) L_0x130eec0/d; -L_0x130ef30/d .functor AND 1, L_0x130ec50, L_0x130d8b0, C4<1>, C4<1>; -L_0x130ef30 .delay 1 (30000,30000,30000) L_0x130ef30/d; -L_0x130f090/d .functor OR 1, L_0x130ef30, L_0x130eec0, C4<0>, C4<0>; -L_0x130f090 .delay 1 (30000,30000,30000) L_0x130f090/d; -v0x11a56e0_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers -v0x11a57d0_0 .net "a_", 0 0, L_0x1303cb0; alias, 1 drivers -v0x11a5890_0 .net "b", 0 0, L_0x130d810; alias, 1 drivers -v0x11a5980_0 .net "b_", 0 0, L_0x130db40; alias, 1 drivers -v0x11a5a20_0 .net "carryin", 0 0, L_0x130d8b0; alias, 1 drivers -v0x11a5b60_0 .net "eq", 0 0, L_0x130ec50; 1 drivers -v0x11a5c20_0 .net "lt", 0 0, L_0x130eec0; 1 drivers -v0x11a5ce0_0 .net "out", 0 0, L_0x130f090; 1 drivers -v0x11a5da0_0 .net "w0", 0 0, L_0x130ef30; 1 drivers -S_0x11a5ff0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x1198db0; +L_0x2e00270/d .functor XNOR 1, L_0x2e092e0, L_0x2dfec80, C4<0>, C4<0>; +L_0x2e00270 .delay 1 (20000,20000,20000) L_0x2e00270/d; +L_0x2e003f0/d .functor AND 1, L_0x2e092e0, L_0x2dfef60, C4<1>, C4<1>; +L_0x2e003f0 .delay 1 (30000,30000,30000) L_0x2e003f0/d; +L_0x2e00550/d .functor AND 1, L_0x2e00270, L_0x2dfed20, C4<1>, C4<1>; +L_0x2e00550 .delay 1 (30000,30000,30000) L_0x2e00550/d; +L_0x2e00660/d .functor OR 1, L_0x2e00550, L_0x2e003f0, C4<0>, C4<0>; +L_0x2e00660 .delay 1 (30000,30000,30000) L_0x2e00660/d; +v0x2c7da10_0 .net "a", 0 0, L_0x2e092e0; alias, 1 drivers +v0x2c7db00_0 .net "a_", 0 0, L_0x2df44f0; alias, 1 drivers +v0x2c7dbc0_0 .net "b", 0 0, L_0x2dfec80; alias, 1 drivers +v0x2c7dcb0_0 .net "b_", 0 0, L_0x2dfef60; alias, 1 drivers +v0x2c7dd50_0 .net "carryin", 0 0, L_0x2dfed20; alias, 1 drivers +v0x2c7de90_0 .net "eq", 0 0, L_0x2e00270; 1 drivers +v0x2c7df50_0 .net "lt", 0 0, L_0x2e003f0; 1 drivers +v0x2c7e010_0 .net "out", 0 0, L_0x2e00660; 1 drivers +v0x2c7e0d0_0 .net "w0", 0 0, L_0x2e00550; 1 drivers +S_0x2c7e320 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c710e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x130ea30/d .functor OR 1, L_0x130e530, L_0x11a7250, C4<0>, C4<0>; -L_0x130ea30 .delay 1 (30000,30000,30000) L_0x130ea30/d; -v0x11a6de0_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers -v0x11a6f30_0 .net "b", 0 0, L_0x130db40; alias, 1 drivers -v0x11a6ff0_0 .net "c1", 0 0, L_0x130e530; 1 drivers -v0x11a7090_0 .net "c2", 0 0, L_0x11a7250; 1 drivers -v0x11a7160_0 .net "carryin", 0 0, L_0x130d8b0; alias, 1 drivers -v0x11a72e0_0 .net "carryout", 0 0, L_0x130ea30; 1 drivers -v0x11a7380_0 .net "s1", 0 0, L_0x130e470; 1 drivers -v0x11a7420_0 .net "sum", 0 0, L_0x130e690; 1 drivers -S_0x11a6240 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11a5ff0; +L_0x2dffe50/d .functor OR 1, L_0x2dff950, L_0x2c7f580, C4<0>, C4<0>; +L_0x2dffe50 .delay 1 (30000,30000,30000) L_0x2dffe50/d; +v0x2c7f110_0 .net "a", 0 0, L_0x2e092e0; alias, 1 drivers +v0x2c7f260_0 .net "b", 0 0, L_0x2dfef60; alias, 1 drivers +v0x2c7f320_0 .net "c1", 0 0, L_0x2dff950; 1 drivers +v0x2c7f3c0_0 .net "c2", 0 0, L_0x2c7f580; 1 drivers +v0x2c7f490_0 .net "carryin", 0 0, L_0x2dfed20; alias, 1 drivers +v0x2c7f610_0 .net "carryout", 0 0, L_0x2dffe50; 1 drivers +v0x2c7f6b0_0 .net "s1", 0 0, L_0x2dff890; 1 drivers +v0x2c7f750_0 .net "sum", 0 0, L_0x2dffab0; 1 drivers +S_0x2c7e570 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c7e320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x130e470/d .functor XOR 1, L_0x1317160, L_0x130db40, C4<0>, C4<0>; -L_0x130e470 .delay 1 (30000,30000,30000) L_0x130e470/d; -L_0x130e530/d .functor AND 1, L_0x1317160, L_0x130db40, C4<1>, C4<1>; -L_0x130e530 .delay 1 (30000,30000,30000) L_0x130e530/d; -v0x11a64a0_0 .net "a", 0 0, L_0x1317160; alias, 1 drivers -v0x11a6560_0 .net "b", 0 0, L_0x130db40; alias, 1 drivers -v0x11a6620_0 .net "carryout", 0 0, L_0x130e530; alias, 1 drivers -v0x11a66c0_0 .net "sum", 0 0, L_0x130e470; alias, 1 drivers -S_0x11a67f0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11a5ff0; +L_0x2dff890/d .functor XOR 1, L_0x2e092e0, L_0x2dfef60, C4<0>, C4<0>; +L_0x2dff890 .delay 1 (30000,30000,30000) L_0x2dff890/d; +L_0x2dff950/d .functor AND 1, L_0x2e092e0, L_0x2dfef60, C4<1>, C4<1>; +L_0x2dff950 .delay 1 (30000,30000,30000) L_0x2dff950/d; +v0x2c7e7d0_0 .net "a", 0 0, L_0x2e092e0; alias, 1 drivers +v0x2c7e890_0 .net "b", 0 0, L_0x2dfef60; alias, 1 drivers +v0x2c7e950_0 .net "carryout", 0 0, L_0x2dff950; alias, 1 drivers +v0x2c7e9f0_0 .net "sum", 0 0, L_0x2dff890; alias, 1 drivers +S_0x2c7eb20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c7e320; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x130e690/d .functor XOR 1, L_0x130e470, L_0x130d8b0, C4<0>, C4<0>; -L_0x130e690 .delay 1 (30000,30000,30000) L_0x130e690/d; -L_0x11a7250/d .functor AND 1, L_0x130e470, L_0x130d8b0, C4<1>, C4<1>; -L_0x11a7250 .delay 1 (30000,30000,30000) L_0x11a7250/d; -v0x11a6a50_0 .net "a", 0 0, L_0x130e470; alias, 1 drivers -v0x11a6b20_0 .net "b", 0 0, L_0x130d8b0; alias, 1 drivers -v0x11a6bc0_0 .net "carryout", 0 0, L_0x11a7250; alias, 1 drivers -v0x11a6c90_0 .net "sum", 0 0, L_0x130e690; alias, 1 drivers -S_0x11a8840 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x1198ae0; - .timescale -9 -12; -L_0x2b0ab3d06e78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06ec0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1317200/d .functor OR 1, L_0x2b0ab3d06e78, L_0x2b0ab3d06ec0, C4<0>, C4<0>; -L_0x1317200 .delay 1 (30000,30000,30000) L_0x1317200/d; -v0x11a8a30_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06e78; 1 drivers -v0x11a8b10_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06ec0; 1 drivers -S_0x11a8bf0 .scope generate, "alu_slices[28]" "alu_slices[28]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11a8e00 .param/l "i" 0 3 41, +C4<011100>; -S_0x11a8ec0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11a8bf0; +L_0x2dffab0/d .functor XOR 1, L_0x2dff890, L_0x2dfed20, C4<0>, C4<0>; +L_0x2dffab0 .delay 1 (30000,30000,30000) L_0x2dffab0/d; +L_0x2c7f580/d .functor AND 1, L_0x2dff890, L_0x2dfed20, C4<1>, C4<1>; +L_0x2c7f580 .delay 1 (30000,30000,30000) L_0x2c7f580/d; +v0x2c7ed80_0 .net "a", 0 0, L_0x2dff890; alias, 1 drivers +v0x2c7ee50_0 .net "b", 0 0, L_0x2dfed20; alias, 1 drivers +v0x2c7eef0_0 .net "carryout", 0 0, L_0x2c7f580; alias, 1 drivers +v0x2c7efc0_0 .net "sum", 0 0, L_0x2dffab0; alias, 1 drivers +S_0x2c817e0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c70e10; + .timescale -9 -12; +L_0x2ac6110bcd38 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcd80 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e01700/d .functor OR 1, L_0x2ac6110bcd38, L_0x2ac6110bcd80, C4<0>, C4<0>; +L_0x2e01700 .delay 1 (30000,30000,30000) L_0x2e01700/d; +v0x2c819d0_0 .net/2u *"_s0", 0 0, L_0x2ac6110bcd38; 1 drivers +v0x2c81ab0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bcd80; 1 drivers +S_0x2c81b90 .scope generate, "alu_slices[28]" "alu_slices[28]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c81da0 .param/l "i" 0 3 39, +C4<011100>; +S_0x2c81e60 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c81b90; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -15048,445 +15918,476 @@ S_0x11a8ec0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11a8bf0; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1317570/d .functor NOT 1, L_0x1320ea0, C4<0>, C4<0>, C4<0>; -L_0x1317570 .delay 1 (10000,10000,10000) L_0x1317570/d; -L_0x1317680/d .functor NOT 1, L_0x1321000, C4<0>, C4<0>, C4<0>; -L_0x1317680 .delay 1 (10000,10000,10000) L_0x1317680/d; -L_0x1318680/d .functor XOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; -L_0x1318680 .delay 1 (30000,30000,30000) L_0x1318680/d; -L_0x2b0ab3d06f08 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06f50 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1318d30/d .functor OR 1, L_0x2b0ab3d06f08, L_0x2b0ab3d06f50, C4<0>, C4<0>; -L_0x1318d30 .delay 1 (30000,30000,30000) L_0x1318d30/d; -L_0x1318f30/d .functor AND 1, L_0x1320ea0, L_0x1321000, C4<1>, C4<1>; -L_0x1318f30 .delay 1 (30000,30000,30000) L_0x1318f30/d; -L_0x1318ff0/d .functor NAND 1, L_0x1320ea0, L_0x1321000, C4<1>, C4<1>; -L_0x1318ff0 .delay 1 (20000,20000,20000) L_0x1318ff0/d; -L_0x1319150/d .functor XOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; -L_0x1319150 .delay 1 (20000,20000,20000) L_0x1319150/d; -L_0x1319600/d .functor OR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; -L_0x1319600 .delay 1 (30000,30000,30000) L_0x1319600/d; -L_0x1320da0/d .functor NOT 1, L_0x131cf70, C4<0>, C4<0>, C4<0>; -L_0x1320da0 .delay 1 (10000,10000,10000) L_0x1320da0/d; -v0x11b75f0_0 .net "A", 0 0, L_0x1320ea0; 1 drivers -v0x11b76b0_0 .net "A_", 0 0, L_0x1317570; 1 drivers -v0x11b7770_0 .net "B", 0 0, L_0x1321000; 1 drivers -v0x11b7840_0 .net "B_", 0 0, L_0x1317680; 1 drivers -v0x11b78e0_0 .net *"_s12", 0 0, L_0x1318d30; 1 drivers -v0x11b79d0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d06f08; 1 drivers -v0x11b7a90_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d06f50; 1 drivers -v0x11b7b70_0 .net *"_s18", 0 0, L_0x1318f30; 1 drivers -v0x11b7c50_0 .net *"_s20", 0 0, L_0x1318ff0; 1 drivers -v0x11b7dc0_0 .net *"_s22", 0 0, L_0x1319150; 1 drivers -v0x11b7ea0_0 .net *"_s24", 0 0, L_0x1319600; 1 drivers -o0x2b0ab3ce7788 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x11b7f80_0 name=_s30 -o0x2b0ab3ce77b8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x11b8060_0 name=_s32 -v0x11b8140_0 .net *"_s8", 0 0, L_0x1318680; 1 drivers -v0x11b8220_0 .net "carryin", 0 0, L_0x13172c0; 1 drivers -v0x11b82c0_0 .net "carryout", 0 0, L_0x1320a40; 1 drivers -v0x11b8360_0 .net "carryouts", 7 0, L_0x1355ee0; 1 drivers -v0x11b8510_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11b85b0_0 .net "result", 0 0, L_0x131cf70; 1 drivers -v0x11b86a0_0 .net "results", 7 0, L_0x13193d0; 1 drivers -v0x11b87b0_0 .net "zero", 0 0, L_0x1320da0; 1 drivers -LS_0x13193d0_0_0 .concat8 [ 1 1 1 1], L_0x1317ba0, L_0x13181d0, L_0x1318680, L_0x1318d30; -LS_0x13193d0_0_4 .concat8 [ 1 1 1 1], L_0x1318f30, L_0x1318ff0, L_0x1319150, L_0x1319600; -L_0x13193d0 .concat8 [ 4 4 0 0], LS_0x13193d0_0_0, LS_0x13193d0_0_4; -LS_0x1355ee0_0_0 .concat [ 1 1 1 1], L_0x1317e50, L_0x1318520, o0x2b0ab3ce7788, L_0x1318b80; -LS_0x1355ee0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce77b8; -L_0x1355ee0 .concat [ 4 4 0 0], LS_0x1355ee0_0_0, LS_0x1355ee0_0_4; -S_0x11a9140 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11a8ec0; +L_0x2e096f0/d .functor NOT 1, L_0x2e13af0, C4<0>, C4<0>, C4<0>; +L_0x2e096f0 .delay 1 (10000,10000,10000) L_0x2e096f0/d; +L_0x2e097b0/d .functor NOT 1, L_0x2e13c50, C4<0>, C4<0>, C4<0>; +L_0x2e097b0 .delay 1 (10000,10000,10000) L_0x2e097b0/d; +L_0x2e0a800/d .functor XOR 1, L_0x2e13af0, L_0x2e13c50, C4<0>, C4<0>; +L_0x2e0a800 .delay 1 (30000,30000,30000) L_0x2e0a800/d; +L_0x2ac6110bcdc8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bce10 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e0a8c0/d .functor OR 1, L_0x2ac6110bcdc8, L_0x2ac6110bce10, C4<0>, C4<0>; +L_0x2e0a8c0 .delay 1 (30000,30000,30000) L_0x2e0a8c0/d; +L_0x2ac6110bce58 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcea0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e0b060/d .functor OR 1, L_0x2ac6110bce58, L_0x2ac6110bcea0, C4<0>, C4<0>; +L_0x2e0b060 .delay 1 (30000,30000,30000) L_0x2e0b060/d; +L_0x2e0b260/d .functor AND 1, L_0x2e13af0, L_0x2e13c50, C4<1>, C4<1>; +L_0x2e0b260 .delay 1 (30000,30000,30000) L_0x2e0b260/d; +L_0x2ac6110bcee8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcf30 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e0b320/d .functor OR 1, L_0x2ac6110bcee8, L_0x2ac6110bcf30, C4<0>, C4<0>; +L_0x2e0b320 .delay 1 (30000,30000,30000) L_0x2e0b320/d; +L_0x2e0b520/d .functor NAND 1, L_0x2e13af0, L_0x2e13c50, C4<1>, C4<1>; +L_0x2e0b520 .delay 1 (20000,20000,20000) L_0x2e0b520/d; +L_0x2ac6110bcf78 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bcfc0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e0b630/d .functor OR 1, L_0x2ac6110bcf78, L_0x2ac6110bcfc0, C4<0>, C4<0>; +L_0x2e0b630 .delay 1 (30000,30000,30000) L_0x2e0b630/d; +L_0x2e0b7e0/d .functor NOR 1, L_0x2e13af0, L_0x2e13c50, C4<0>, C4<0>; +L_0x2e0b7e0 .delay 1 (20000,20000,20000) L_0x2e0b7e0/d; +L_0x2ac6110bd008 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd050 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e09c60/d .functor OR 1, L_0x2ac6110bd008, L_0x2ac6110bd050, C4<0>, C4<0>; +L_0x2e09c60 .delay 1 (30000,30000,30000) L_0x2e09c60/d; +L_0x2e0be40/d .functor OR 1, L_0x2e13af0, L_0x2e13c50, C4<0>, C4<0>; +L_0x2e0be40 .delay 1 (30000,30000,30000) L_0x2e0be40/d; +L_0x2ac6110bd098 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd0e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e0c330/d .functor OR 1, L_0x2ac6110bd098, L_0x2ac6110bd0e0, C4<0>, C4<0>; +L_0x2e0c330 .delay 1 (30000,30000,30000) L_0x2e0c330/d; +L_0x2e139f0/d .functor NOT 1, L_0x2e0fbf0, C4<0>, C4<0>, C4<0>; +L_0x2e139f0 .delay 1 (10000,10000,10000) L_0x2e139f0/d; +v0x2c90590_0 .net "A", 0 0, L_0x2e13af0; 1 drivers +v0x2c90650_0 .net "A_", 0 0, L_0x2e096f0; 1 drivers +v0x2c90710_0 .net "B", 0 0, L_0x2e13c50; 1 drivers +v0x2c907e0_0 .net "B_", 0 0, L_0x2e097b0; 1 drivers +v0x2c90880_0 .net *"_s11", 0 0, L_0x2e0a8c0; 1 drivers +v0x2c90970_0 .net/2s *"_s13", 0 0, L_0x2ac6110bcdc8; 1 drivers +v0x2c90a30_0 .net/2s *"_s15", 0 0, L_0x2ac6110bce10; 1 drivers +v0x2c90b10_0 .net *"_s19", 0 0, L_0x2e0b060; 1 drivers +v0x2c90bf0_0 .net/2s *"_s21", 0 0, L_0x2ac6110bce58; 1 drivers +v0x2c90d60_0 .net/2s *"_s23", 0 0, L_0x2ac6110bcea0; 1 drivers +v0x2c90e40_0 .net *"_s25", 0 0, L_0x2e0b260; 1 drivers +v0x2c90f20_0 .net *"_s28", 0 0, L_0x2e0b320; 1 drivers +v0x2c91000_0 .net/2s *"_s30", 0 0, L_0x2ac6110bcee8; 1 drivers +v0x2c910e0_0 .net/2s *"_s32", 0 0, L_0x2ac6110bcf30; 1 drivers +v0x2c911c0_0 .net *"_s34", 0 0, L_0x2e0b520; 1 drivers +v0x2c912a0_0 .net *"_s37", 0 0, L_0x2e0b630; 1 drivers +v0x2c91380_0 .net/2s *"_s39", 0 0, L_0x2ac6110bcf78; 1 drivers +v0x2c91530_0 .net/2s *"_s41", 0 0, L_0x2ac6110bcfc0; 1 drivers +v0x2c915d0_0 .net *"_s43", 0 0, L_0x2e0b7e0; 1 drivers +v0x2c916b0_0 .net *"_s46", 0 0, L_0x2e09c60; 1 drivers +v0x2c91790_0 .net/2s *"_s48", 0 0, L_0x2ac6110bd008; 1 drivers +v0x2c91870_0 .net/2s *"_s50", 0 0, L_0x2ac6110bd050; 1 drivers +v0x2c91950_0 .net *"_s52", 0 0, L_0x2e0be40; 1 drivers +v0x2c91a30_0 .net *"_s56", 0 0, L_0x2e0c330; 1 drivers +v0x2c91b10_0 .net/2s *"_s59", 0 0, L_0x2ac6110bd098; 1 drivers +v0x2c91bf0_0 .net/2s *"_s61", 0 0, L_0x2ac6110bd0e0; 1 drivers +v0x2c91cd0_0 .net *"_s8", 0 0, L_0x2e0a800; 1 drivers +v0x2c91db0_0 .net "carryin", 0 0, L_0x2e09440; 1 drivers +v0x2c91e50_0 .net "carryout", 0 0, L_0x2e13690; 1 drivers +v0x2c91ef0_0 .net "carryouts", 7 0, L_0x2e0bfc0; 1 drivers +v0x2c92000_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c920c0_0 .net "result", 0 0, L_0x2e0fbf0; 1 drivers +v0x2c921b0_0 .net "results", 7 0, L_0x2e0bc10; 1 drivers +v0x2c91490_0 .net "zero", 0 0, L_0x2e139f0; 1 drivers +LS_0x2e0bc10_0_0 .concat8 [ 1 1 1 1], L_0x2e09cd0, L_0x2e0a300, L_0x2e0a800, L_0x2e0b060; +LS_0x2e0bc10_0_4 .concat8 [ 1 1 1 1], L_0x2e0b260, L_0x2e0b520, L_0x2e0b7e0, L_0x2e0be40; +L_0x2e0bc10 .concat8 [ 4 4 0 0], LS_0x2e0bc10_0_0, LS_0x2e0bc10_0_4; +LS_0x2e0bfc0_0_0 .concat8 [ 1 1 1 1], L_0x2e09f80, L_0x2e0a6a0, L_0x2e0a8c0, L_0x2e0aeb0; +LS_0x2e0bfc0_0_4 .concat8 [ 1 1 1 1], L_0x2e0b320, L_0x2e0b630, L_0x2e09c60, L_0x2e0c330; +L_0x2e0bfc0 .concat8 [ 4 4 0 0], LS_0x2e0bfc0_0_0, LS_0x2e0bfc0_0_4; +S_0x2c820e0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c81e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1317e50/d .functor OR 1, L_0x1317930, L_0x1317cf0, C4<0>, C4<0>; -L_0x1317e50 .delay 1 (30000,30000,30000) L_0x1317e50/d; -v0x11a9f70_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers -v0x11aa030_0 .net "b", 0 0, L_0x1321000; alias, 1 drivers -v0x11aa100_0 .net "c1", 0 0, L_0x1317930; 1 drivers -v0x11aa200_0 .net "c2", 0 0, L_0x1317cf0; 1 drivers -v0x11aa2d0_0 .net "carryin", 0 0, L_0x13172c0; alias, 1 drivers -v0x11aa3c0_0 .net "carryout", 0 0, L_0x1317e50; 1 drivers -v0x11aa460_0 .net "s1", 0 0, L_0x1317870; 1 drivers -v0x11aa550_0 .net "sum", 0 0, L_0x1317ba0; 1 drivers -S_0x11a93b0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11a9140; +L_0x2e09f80/d .functor OR 1, L_0x2e09a60, L_0x2e09e20, C4<0>, C4<0>; +L_0x2e09f80 .delay 1 (30000,30000,30000) L_0x2e09f80/d; +v0x2c82f10_0 .net "a", 0 0, L_0x2e13af0; alias, 1 drivers +v0x2c82fd0_0 .net "b", 0 0, L_0x2e13c50; alias, 1 drivers +v0x2c830a0_0 .net "c1", 0 0, L_0x2e09a60; 1 drivers +v0x2c831a0_0 .net "c2", 0 0, L_0x2e09e20; 1 drivers +v0x2c83270_0 .net "carryin", 0 0, L_0x2e09440; alias, 1 drivers +v0x2c83360_0 .net "carryout", 0 0, L_0x2e09f80; 1 drivers +v0x2c83400_0 .net "s1", 0 0, L_0x2e099a0; 1 drivers +v0x2c834f0_0 .net "sum", 0 0, L_0x2e09cd0; 1 drivers +S_0x2c82350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c820e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1317870/d .functor XOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; -L_0x1317870 .delay 1 (30000,30000,30000) L_0x1317870/d; -L_0x1317930/d .functor AND 1, L_0x1320ea0, L_0x1321000, C4<1>, C4<1>; -L_0x1317930 .delay 1 (30000,30000,30000) L_0x1317930/d; -v0x11a9610_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers -v0x11a96f0_0 .net "b", 0 0, L_0x1321000; alias, 1 drivers -v0x11a97b0_0 .net "carryout", 0 0, L_0x1317930; alias, 1 drivers -v0x11a9850_0 .net "sum", 0 0, L_0x1317870; alias, 1 drivers -S_0x11a9990 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11a9140; +L_0x2e099a0/d .functor XOR 1, L_0x2e13af0, L_0x2e13c50, C4<0>, C4<0>; +L_0x2e099a0 .delay 1 (30000,30000,30000) L_0x2e099a0/d; +L_0x2e09a60/d .functor AND 1, L_0x2e13af0, L_0x2e13c50, C4<1>, C4<1>; +L_0x2e09a60 .delay 1 (30000,30000,30000) L_0x2e09a60/d; +v0x2c825b0_0 .net "a", 0 0, L_0x2e13af0; alias, 1 drivers +v0x2c82690_0 .net "b", 0 0, L_0x2e13c50; alias, 1 drivers +v0x2c82750_0 .net "carryout", 0 0, L_0x2e09a60; alias, 1 drivers +v0x2c827f0_0 .net "sum", 0 0, L_0x2e099a0; alias, 1 drivers +S_0x2c82930 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c820e0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1317ba0/d .functor XOR 1, L_0x1317870, L_0x13172c0, C4<0>, C4<0>; -L_0x1317ba0 .delay 1 (30000,30000,30000) L_0x1317ba0/d; -L_0x1317cf0/d .functor AND 1, L_0x1317870, L_0x13172c0, C4<1>, C4<1>; -L_0x1317cf0 .delay 1 (30000,30000,30000) L_0x1317cf0/d; -v0x11a9bf0_0 .net "a", 0 0, L_0x1317870; alias, 1 drivers -v0x11a9c90_0 .net "b", 0 0, L_0x13172c0; alias, 1 drivers -v0x11a9d30_0 .net "carryout", 0 0, L_0x1317cf0; alias, 1 drivers -v0x11a9e00_0 .net "sum", 0 0, L_0x1317ba0; alias, 1 drivers -S_0x11aa620 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11a8ec0; +L_0x2e09cd0/d .functor XOR 1, L_0x2e099a0, L_0x2e09440, C4<0>, C4<0>; +L_0x2e09cd0 .delay 1 (30000,30000,30000) L_0x2e09cd0/d; +L_0x2e09e20/d .functor AND 1, L_0x2e099a0, L_0x2e09440, C4<1>, C4<1>; +L_0x2e09e20 .delay 1 (30000,30000,30000) L_0x2e09e20/d; +v0x2c82b90_0 .net "a", 0 0, L_0x2e099a0; alias, 1 drivers +v0x2c82c30_0 .net "b", 0 0, L_0x2e09440; alias, 1 drivers +v0x2c82cd0_0 .net "carryout", 0 0, L_0x2e09e20; alias, 1 drivers +v0x2c82da0_0 .net "sum", 0 0, L_0x2e09cd0; alias, 1 drivers +S_0x2c835c0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c81e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11afa10_0 .net "ands", 7 0, L_0x131ea40; 1 drivers -v0x11afb20_0 .net "in", 7 0, L_0x1355ee0; alias, 1 drivers -v0x11afbe0_0 .net "out", 0 0, L_0x1320a40; alias, 1 drivers -v0x11afcb0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11aa840 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11aa620; +v0x2c889c0_0 .net "ands", 7 0, L_0x2e11690; 1 drivers +v0x2c88ad0_0 .net "in", 7 0, L_0x2e0bfc0; alias, 1 drivers +v0x2c88b90_0 .net "out", 0 0, L_0x2e13690; alias, 1 drivers +v0x2c88c30_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c837e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c835c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11acf70_0 .net "A", 7 0, L_0x1355ee0; alias, 1 drivers -v0x11ad070_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11ad130_0 .net *"_s0", 0 0, L_0x131d2d0; 1 drivers -v0x11ad1f0_0 .net *"_s12", 0 0, L_0x131dc40; 1 drivers -v0x11ad2d0_0 .net *"_s16", 0 0, L_0x131dfa0; 1 drivers -v0x11ad400_0 .net *"_s20", 0 0, L_0x131e310; 1 drivers -v0x11ad4e0_0 .net *"_s24", 0 0, L_0x131e730; 1 drivers -v0x11ad5c0_0 .net *"_s28", 0 0, L_0x131e6c0; 1 drivers -v0x11ad6a0_0 .net *"_s4", 0 0, L_0x131d5e0; 1 drivers -v0x11ad810_0 .net *"_s8", 0 0, L_0x131d930; 1 drivers -v0x11ad8f0_0 .net "out", 7 0, L_0x131ea40; alias, 1 drivers -L_0x131d390 .part L_0x1355ee0, 0, 1; -L_0x131d4f0 .part v0x12010b0_0, 0, 1; -L_0x131d6a0 .part L_0x1355ee0, 1, 1; -L_0x131d890 .part v0x12010b0_0, 1, 1; -L_0x131d9f0 .part L_0x1355ee0, 2, 1; -L_0x131db50 .part v0x12010b0_0, 2, 1; -L_0x131dd00 .part L_0x1355ee0, 3, 1; -L_0x131de60 .part v0x12010b0_0, 3, 1; -L_0x131e0c0 .part L_0x1355ee0, 4, 1; -L_0x131e220 .part v0x12010b0_0, 4, 1; -L_0x131e3b0 .part L_0x1355ee0, 5, 1; -L_0x131e620 .part v0x12010b0_0, 5, 1; -L_0x131e7f0 .part L_0x1355ee0, 6, 1; -L_0x131e950 .part v0x12010b0_0, 6, 1; -LS_0x131ea40_0_0 .concat8 [ 1 1 1 1], L_0x131d2d0, L_0x131d5e0, L_0x131d930, L_0x131dc40; -LS_0x131ea40_0_4 .concat8 [ 1 1 1 1], L_0x131dfa0, L_0x131e310, L_0x131e730, L_0x131e6c0; -L_0x131ea40 .concat8 [ 4 4 0 0], LS_0x131ea40_0_0, LS_0x131ea40_0_4; -L_0x131ee00 .part L_0x1355ee0, 7, 1; -L_0x131eff0 .part v0x12010b0_0, 7, 1; -S_0x11aaaa0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11aacb0 .param/l "i" 0 4 54, +C4<00>; -L_0x131d2d0/d .functor AND 1, L_0x131d390, L_0x131d4f0, C4<1>, C4<1>; -L_0x131d2d0 .delay 1 (30000,30000,30000) L_0x131d2d0/d; -v0x11aad90_0 .net *"_s0", 0 0, L_0x131d390; 1 drivers -v0x11aae70_0 .net *"_s1", 0 0, L_0x131d4f0; 1 drivers -S_0x11aaf50 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11ab160 .param/l "i" 0 4 54, +C4<01>; -L_0x131d5e0/d .functor AND 1, L_0x131d6a0, L_0x131d890, C4<1>, C4<1>; -L_0x131d5e0 .delay 1 (30000,30000,30000) L_0x131d5e0/d; -v0x11ab220_0 .net *"_s0", 0 0, L_0x131d6a0; 1 drivers -v0x11ab300_0 .net *"_s1", 0 0, L_0x131d890; 1 drivers -S_0x11ab3e0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11ab5f0 .param/l "i" 0 4 54, +C4<010>; -L_0x131d930/d .functor AND 1, L_0x131d9f0, L_0x131db50, C4<1>, C4<1>; -L_0x131d930 .delay 1 (30000,30000,30000) L_0x131d930/d; -v0x11ab690_0 .net *"_s0", 0 0, L_0x131d9f0; 1 drivers -v0x11ab770_0 .net *"_s1", 0 0, L_0x131db50; 1 drivers -S_0x11ab850 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11aba60 .param/l "i" 0 4 54, +C4<011>; -L_0x131dc40/d .functor AND 1, L_0x131dd00, L_0x131de60, C4<1>, C4<1>; -L_0x131dc40 .delay 1 (30000,30000,30000) L_0x131dc40/d; -v0x11abb20_0 .net *"_s0", 0 0, L_0x131dd00; 1 drivers -v0x11abc00_0 .net *"_s1", 0 0, L_0x131de60; 1 drivers -S_0x11abce0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11abf40 .param/l "i" 0 4 54, +C4<0100>; -L_0x131dfa0/d .functor AND 1, L_0x131e0c0, L_0x131e220, C4<1>, C4<1>; -L_0x131dfa0 .delay 1 (30000,30000,30000) L_0x131dfa0/d; -v0x11ac000_0 .net *"_s0", 0 0, L_0x131e0c0; 1 drivers -v0x11ac0e0_0 .net *"_s1", 0 0, L_0x131e220; 1 drivers -S_0x11ac1c0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11ac3d0 .param/l "i" 0 4 54, +C4<0101>; -L_0x131e310/d .functor AND 1, L_0x131e3b0, L_0x131e620, C4<1>, C4<1>; -L_0x131e310 .delay 1 (30000,30000,30000) L_0x131e310/d; -v0x11ac490_0 .net *"_s0", 0 0, L_0x131e3b0; 1 drivers -v0x11ac570_0 .net *"_s1", 0 0, L_0x131e620; 1 drivers -S_0x11ac650 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11ac860 .param/l "i" 0 4 54, +C4<0110>; -L_0x131e730/d .functor AND 1, L_0x131e7f0, L_0x131e950, C4<1>, C4<1>; -L_0x131e730 .delay 1 (30000,30000,30000) L_0x131e730/d; -v0x11ac920_0 .net *"_s0", 0 0, L_0x131e7f0; 1 drivers -v0x11aca00_0 .net *"_s1", 0 0, L_0x131e950; 1 drivers -S_0x11acae0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11aa840; - .timescale -9 -12; -P_0x11accf0 .param/l "i" 0 4 54, +C4<0111>; -L_0x131e6c0/d .functor AND 1, L_0x131ee00, L_0x131eff0, C4<1>, C4<1>; -L_0x131e6c0 .delay 1 (30000,30000,30000) L_0x131e6c0/d; -v0x11acdb0_0 .net *"_s0", 0 0, L_0x131ee00; 1 drivers -v0x11ace90_0 .net *"_s1", 0 0, L_0x131eff0; 1 drivers -S_0x11ada50 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11aa620; +v0x2c85f10_0 .net "A", 7 0, L_0x2e0bfc0; alias, 1 drivers +v0x2c85ff0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c860b0_0 .net *"_s0", 0 0, L_0x2e0ff50; 1 drivers +v0x2c861a0_0 .net *"_s12", 0 0, L_0x2e108c0; 1 drivers +v0x2c86280_0 .net *"_s16", 0 0, L_0x2e10c20; 1 drivers +v0x2c863b0_0 .net *"_s20", 0 0, L_0x2e11050; 1 drivers +v0x2c86490_0 .net *"_s24", 0 0, L_0x2e11380; 1 drivers +v0x2c86570_0 .net *"_s28", 0 0, L_0x2e11310; 1 drivers +v0x2c86650_0 .net *"_s4", 0 0, L_0x2e102a0; 1 drivers +v0x2c867c0_0 .net *"_s8", 0 0, L_0x2e105b0; 1 drivers +v0x2c868a0_0 .net "out", 7 0, L_0x2e11690; alias, 1 drivers +L_0x2e10010 .part L_0x2e0bfc0, 0, 1; +L_0x2e10200 .part v0x2cdd2e0_0, 0, 1; +L_0x2e10360 .part L_0x2e0bfc0, 1, 1; +L_0x2e104c0 .part v0x2cdd2e0_0, 1, 1; +L_0x2e10670 .part L_0x2e0bfc0, 2, 1; +L_0x2e107d0 .part v0x2cdd2e0_0, 2, 1; +L_0x2e10980 .part L_0x2e0bfc0, 3, 1; +L_0x2e10ae0 .part v0x2cdd2e0_0, 3, 1; +L_0x2e10ce0 .part L_0x2e0bfc0, 4, 1; +L_0x2e10f50 .part v0x2cdd2e0_0, 4, 1; +L_0x2e110c0 .part L_0x2e0bfc0, 5, 1; +L_0x2e11220 .part v0x2cdd2e0_0, 5, 1; +L_0x2e11440 .part L_0x2e0bfc0, 6, 1; +L_0x2e115a0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e11690_0_0 .concat8 [ 1 1 1 1], L_0x2e0ff50, L_0x2e102a0, L_0x2e105b0, L_0x2e108c0; +LS_0x2e11690_0_4 .concat8 [ 1 1 1 1], L_0x2e10c20, L_0x2e11050, L_0x2e11380, L_0x2e11310; +L_0x2e11690 .concat8 [ 4 4 0 0], LS_0x2e11690_0_0, LS_0x2e11690_0_4; +L_0x2e11a50 .part L_0x2e0bfc0, 7, 1; +L_0x2e11c40 .part v0x2cdd2e0_0, 7, 1; +S_0x2c83a40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c83c50 .param/l "i" 0 4 54, +C4<00>; +L_0x2e0ff50/d .functor AND 1, L_0x2e10010, L_0x2e10200, C4<1>, C4<1>; +L_0x2e0ff50 .delay 1 (30000,30000,30000) L_0x2e0ff50/d; +v0x2c83d30_0 .net *"_s0", 0 0, L_0x2e10010; 1 drivers +v0x2c83e10_0 .net *"_s1", 0 0, L_0x2e10200; 1 drivers +S_0x2c83ef0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c84100 .param/l "i" 0 4 54, +C4<01>; +L_0x2e102a0/d .functor AND 1, L_0x2e10360, L_0x2e104c0, C4<1>, C4<1>; +L_0x2e102a0 .delay 1 (30000,30000,30000) L_0x2e102a0/d; +v0x2c841c0_0 .net *"_s0", 0 0, L_0x2e10360; 1 drivers +v0x2c842a0_0 .net *"_s1", 0 0, L_0x2e104c0; 1 drivers +S_0x2c84380 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c84590 .param/l "i" 0 4 54, +C4<010>; +L_0x2e105b0/d .functor AND 1, L_0x2e10670, L_0x2e107d0, C4<1>, C4<1>; +L_0x2e105b0 .delay 1 (30000,30000,30000) L_0x2e105b0/d; +v0x2c84630_0 .net *"_s0", 0 0, L_0x2e10670; 1 drivers +v0x2c84710_0 .net *"_s1", 0 0, L_0x2e107d0; 1 drivers +S_0x2c847f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c84a00 .param/l "i" 0 4 54, +C4<011>; +L_0x2e108c0/d .functor AND 1, L_0x2e10980, L_0x2e10ae0, C4<1>, C4<1>; +L_0x2e108c0 .delay 1 (30000,30000,30000) L_0x2e108c0/d; +v0x2c84ac0_0 .net *"_s0", 0 0, L_0x2e10980; 1 drivers +v0x2c84ba0_0 .net *"_s1", 0 0, L_0x2e10ae0; 1 drivers +S_0x2c84c80 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c84ee0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e10c20/d .functor AND 1, L_0x2e10ce0, L_0x2e10f50, C4<1>, C4<1>; +L_0x2e10c20 .delay 1 (30000,30000,30000) L_0x2e10c20/d; +v0x2c84fa0_0 .net *"_s0", 0 0, L_0x2e10ce0; 1 drivers +v0x2c85080_0 .net *"_s1", 0 0, L_0x2e10f50; 1 drivers +S_0x2c85160 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c85370 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e11050/d .functor AND 1, L_0x2e110c0, L_0x2e11220, C4<1>, C4<1>; +L_0x2e11050 .delay 1 (30000,30000,30000) L_0x2e11050/d; +v0x2c85430_0 .net *"_s0", 0 0, L_0x2e110c0; 1 drivers +v0x2c85510_0 .net *"_s1", 0 0, L_0x2e11220; 1 drivers +S_0x2c855f0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c85800 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e11380/d .functor AND 1, L_0x2e11440, L_0x2e115a0, C4<1>, C4<1>; +L_0x2e11380 .delay 1 (30000,30000,30000) L_0x2e11380/d; +v0x2c858c0_0 .net *"_s0", 0 0, L_0x2e11440; 1 drivers +v0x2c859a0_0 .net *"_s1", 0 0, L_0x2e115a0; 1 drivers +S_0x2c85a80 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c837e0; + .timescale -9 -12; +P_0x2c85c90 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e11310/d .functor AND 1, L_0x2e11a50, L_0x2e11c40, C4<1>, C4<1>; +L_0x2e11310 .delay 1 (30000,30000,30000) L_0x2e11310/d; +v0x2c85d50_0 .net *"_s0", 0 0, L_0x2e11a50; 1 drivers +v0x2c85e30_0 .net *"_s1", 0 0, L_0x2e11c40; 1 drivers +S_0x2c86a00 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c835c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1320a40/d .functor OR 1, L_0x1320b00, L_0x1320cb0, C4<0>, C4<0>; -L_0x1320a40 .delay 1 (30000,30000,30000) L_0x1320a40/d; -v0x11af5d0_0 .net *"_s10", 0 0, L_0x1320b00; 1 drivers -v0x11af6b0_0 .net *"_s12", 0 0, L_0x1320cb0; 1 drivers -v0x11af790_0 .net "in", 7 0, L_0x131ea40; alias, 1 drivers -v0x11af830_0 .net "ors", 1 0, L_0x1320860; 1 drivers -v0x11af8f0_0 .net "out", 0 0, L_0x1320a40; alias, 1 drivers -L_0x131fc30 .part L_0x131ea40, 0, 4; -L_0x1320860 .concat8 [ 1 1 0 0], L_0x131f920, L_0x1320550; -L_0x13209a0 .part L_0x131ea40, 4, 4; -L_0x1320b00 .part L_0x1320860, 0, 1; -L_0x1320cb0 .part L_0x1320860, 1, 1; -S_0x11adc10 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11ada50; +L_0x2e13690/d .functor OR 1, L_0x2e13750, L_0x2e13900, C4<0>, C4<0>; +L_0x2e13690 .delay 1 (30000,30000,30000) L_0x2e13690/d; +v0x2c88550_0 .net *"_s10", 0 0, L_0x2e13750; 1 drivers +v0x2c88630_0 .net *"_s12", 0 0, L_0x2e13900; 1 drivers +v0x2c88710_0 .net "in", 7 0, L_0x2e11690; alias, 1 drivers +v0x2c887e0_0 .net "ors", 1 0, L_0x2e134b0; 1 drivers +v0x2c888a0_0 .net "out", 0 0, L_0x2e13690; alias, 1 drivers +L_0x2e12880 .part L_0x2e11690, 0, 4; +L_0x2e134b0 .concat8 [ 1 1 0 0], L_0x2e12570, L_0x2e131a0; +L_0x2e135f0 .part L_0x2e11690, 4, 4; +L_0x2e13750 .part L_0x2e134b0, 0, 1; +L_0x2e13900 .part L_0x2e134b0, 1, 1; +S_0x2c86bc0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c86a00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x131f0e0/d .functor OR 1, L_0x131f1a0, L_0x131f300, C4<0>, C4<0>; -L_0x131f0e0 .delay 1 (30000,30000,30000) L_0x131f0e0/d; -L_0x131f530/d .functor OR 1, L_0x131f640, L_0x131f7a0, C4<0>, C4<0>; -L_0x131f530 .delay 1 (30000,30000,30000) L_0x131f530/d; -L_0x131f920/d .functor OR 1, L_0x131f990, L_0x131fb40, C4<0>, C4<0>; -L_0x131f920 .delay 1 (30000,30000,30000) L_0x131f920/d; -v0x11ade60_0 .net *"_s0", 0 0, L_0x131f0e0; 1 drivers -v0x11adf60_0 .net *"_s10", 0 0, L_0x131f640; 1 drivers -v0x11ae020_0 .net *"_s12", 0 0, L_0x131f7a0; 1 drivers -v0x11ae130_0 .net *"_s14", 0 0, L_0x131f990; 1 drivers -v0x11ae210_0 .net *"_s16", 0 0, L_0x131fb40; 1 drivers -v0x11ae340_0 .net *"_s3", 0 0, L_0x131f1a0; 1 drivers -v0x11ae420_0 .net *"_s5", 0 0, L_0x131f300; 1 drivers -v0x11ae500_0 .net *"_s6", 0 0, L_0x131f530; 1 drivers -v0x11ae5e0_0 .net "in", 3 0, L_0x131fc30; 1 drivers -v0x11ae750_0 .net "ors", 1 0, L_0x131f440; 1 drivers -v0x11ae830_0 .net "out", 0 0, L_0x131f920; 1 drivers -L_0x131f1a0 .part L_0x131fc30, 0, 1; -L_0x131f300 .part L_0x131fc30, 1, 1; -L_0x131f440 .concat8 [ 1 1 0 0], L_0x131f0e0, L_0x131f530; -L_0x131f640 .part L_0x131fc30, 2, 1; -L_0x131f7a0 .part L_0x131fc30, 3, 1; -L_0x131f990 .part L_0x131f440, 0, 1; -L_0x131fb40 .part L_0x131f440, 1, 1; -S_0x11ae950 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11ada50; +L_0x2e11d30/d .functor OR 1, L_0x2e11df0, L_0x2e11f50, C4<0>, C4<0>; +L_0x2e11d30 .delay 1 (30000,30000,30000) L_0x2e11d30/d; +L_0x2e12180/d .functor OR 1, L_0x2e12290, L_0x2e123f0, C4<0>, C4<0>; +L_0x2e12180 .delay 1 (30000,30000,30000) L_0x2e12180/d; +L_0x2e12570/d .functor OR 1, L_0x2e125e0, L_0x2e12790, C4<0>, C4<0>; +L_0x2e12570 .delay 1 (30000,30000,30000) L_0x2e12570/d; +v0x2c86e10_0 .net *"_s0", 0 0, L_0x2e11d30; 1 drivers +v0x2c86f10_0 .net *"_s10", 0 0, L_0x2e12290; 1 drivers +v0x2c86ff0_0 .net *"_s12", 0 0, L_0x2e123f0; 1 drivers +v0x2c870b0_0 .net *"_s14", 0 0, L_0x2e125e0; 1 drivers +v0x2c87190_0 .net *"_s16", 0 0, L_0x2e12790; 1 drivers +v0x2c872c0_0 .net *"_s3", 0 0, L_0x2e11df0; 1 drivers +v0x2c873a0_0 .net *"_s5", 0 0, L_0x2e11f50; 1 drivers +v0x2c87480_0 .net *"_s6", 0 0, L_0x2e12180; 1 drivers +v0x2c87560_0 .net "in", 3 0, L_0x2e12880; 1 drivers +v0x2c876d0_0 .net "ors", 1 0, L_0x2e12090; 1 drivers +v0x2c877b0_0 .net "out", 0 0, L_0x2e12570; 1 drivers +L_0x2e11df0 .part L_0x2e12880, 0, 1; +L_0x2e11f50 .part L_0x2e12880, 1, 1; +L_0x2e12090 .concat8 [ 1 1 0 0], L_0x2e11d30, L_0x2e12180; +L_0x2e12290 .part L_0x2e12880, 2, 1; +L_0x2e123f0 .part L_0x2e12880, 3, 1; +L_0x2e125e0 .part L_0x2e12090, 0, 1; +L_0x2e12790 .part L_0x2e12090, 1, 1; +S_0x2c878d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c86a00; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x131fd60/d .functor OR 1, L_0x131fdd0, L_0x131ff30, C4<0>, C4<0>; -L_0x131fd60 .delay 1 (30000,30000,30000) L_0x131fd60/d; -L_0x1320160/d .functor OR 1, L_0x1320270, L_0x13203d0, C4<0>, C4<0>; -L_0x1320160 .delay 1 (30000,30000,30000) L_0x1320160/d; -L_0x1320550/d .functor OR 1, L_0x13205c0, L_0x1320770, C4<0>, C4<0>; -L_0x1320550 .delay 1 (30000,30000,30000) L_0x1320550/d; -v0x11aeb10_0 .net *"_s0", 0 0, L_0x131fd60; 1 drivers -v0x11aec10_0 .net *"_s10", 0 0, L_0x1320270; 1 drivers -v0x11aecf0_0 .net *"_s12", 0 0, L_0x13203d0; 1 drivers -v0x11aedb0_0 .net *"_s14", 0 0, L_0x13205c0; 1 drivers -v0x11aee90_0 .net *"_s16", 0 0, L_0x1320770; 1 drivers -v0x11aefc0_0 .net *"_s3", 0 0, L_0x131fdd0; 1 drivers -v0x11af0a0_0 .net *"_s5", 0 0, L_0x131ff30; 1 drivers -v0x11af180_0 .net *"_s6", 0 0, L_0x1320160; 1 drivers -v0x11af260_0 .net "in", 3 0, L_0x13209a0; 1 drivers -v0x11af3d0_0 .net "ors", 1 0, L_0x1320070; 1 drivers -v0x11af4b0_0 .net "out", 0 0, L_0x1320550; 1 drivers -L_0x131fdd0 .part L_0x13209a0, 0, 1; -L_0x131ff30 .part L_0x13209a0, 1, 1; -L_0x1320070 .concat8 [ 1 1 0 0], L_0x131fd60, L_0x1320160; -L_0x1320270 .part L_0x13209a0, 2, 1; -L_0x13203d0 .part L_0x13209a0, 3, 1; -L_0x13205c0 .part L_0x1320070, 0, 1; -L_0x1320770 .part L_0x1320070, 1, 1; -S_0x11afd90 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11a8ec0; +L_0x2e129b0/d .functor OR 1, L_0x2e12a20, L_0x2e12b80, C4<0>, C4<0>; +L_0x2e129b0 .delay 1 (30000,30000,30000) L_0x2e129b0/d; +L_0x2e12db0/d .functor OR 1, L_0x2e12ec0, L_0x2e13020, C4<0>, C4<0>; +L_0x2e12db0 .delay 1 (30000,30000,30000) L_0x2e12db0/d; +L_0x2e131a0/d .functor OR 1, L_0x2e13210, L_0x2e133c0, C4<0>, C4<0>; +L_0x2e131a0 .delay 1 (30000,30000,30000) L_0x2e131a0/d; +v0x2c87a90_0 .net *"_s0", 0 0, L_0x2e129b0; 1 drivers +v0x2c87b90_0 .net *"_s10", 0 0, L_0x2e12ec0; 1 drivers +v0x2c87c70_0 .net *"_s12", 0 0, L_0x2e13020; 1 drivers +v0x2c87d30_0 .net *"_s14", 0 0, L_0x2e13210; 1 drivers +v0x2c87e10_0 .net *"_s16", 0 0, L_0x2e133c0; 1 drivers +v0x2c87f40_0 .net *"_s3", 0 0, L_0x2e12a20; 1 drivers +v0x2c88020_0 .net *"_s5", 0 0, L_0x2e12b80; 1 drivers +v0x2c88100_0 .net *"_s6", 0 0, L_0x2e12db0; 1 drivers +v0x2c881e0_0 .net "in", 3 0, L_0x2e135f0; 1 drivers +v0x2c88350_0 .net "ors", 1 0, L_0x2e12cc0; 1 drivers +v0x2c88430_0 .net "out", 0 0, L_0x2e131a0; 1 drivers +L_0x2e12a20 .part L_0x2e135f0, 0, 1; +L_0x2e12b80 .part L_0x2e135f0, 1, 1; +L_0x2e12cc0 .concat8 [ 1 1 0 0], L_0x2e129b0, L_0x2e12db0; +L_0x2e12ec0 .part L_0x2e135f0, 2, 1; +L_0x2e13020 .part L_0x2e135f0, 3, 1; +L_0x2e13210 .part L_0x2e12cc0, 0, 1; +L_0x2e133c0 .part L_0x2e12cc0, 1, 1; +S_0x2c88d30 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c81e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11b51c0_0 .net "ands", 7 0, L_0x131af70; 1 drivers -v0x11b52d0_0 .net "in", 7 0, L_0x13193d0; alias, 1 drivers -v0x11b5390_0 .net "out", 0 0, L_0x131cf70; alias, 1 drivers -v0x11b5460_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11affe0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11afd90; +v0x2c8e160_0 .net "ands", 7 0, L_0x2e0dc90; 1 drivers +v0x2c8e270_0 .net "in", 7 0, L_0x2e0bc10; alias, 1 drivers +v0x2c8e330_0 .net "out", 0 0, L_0x2e0fbf0; alias, 1 drivers +v0x2c8e400_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c88f80 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c88d30; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11b2720_0 .net "A", 7 0, L_0x13193d0; alias, 1 drivers -v0x11b2820_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11b28e0_0 .net *"_s0", 0 0, L_0x1319760; 1 drivers -v0x11b29a0_0 .net *"_s12", 0 0, L_0x131a120; 1 drivers -v0x11b2a80_0 .net *"_s16", 0 0, L_0x131a480; 1 drivers -v0x11b2bb0_0 .net *"_s20", 0 0, L_0x131a8b0; 1 drivers -v0x11b2c90_0 .net *"_s24", 0 0, L_0x131abe0; 1 drivers -v0x11b2d70_0 .net *"_s28", 0 0, L_0x131ab70; 1 drivers -v0x11b2e50_0 .net *"_s4", 0 0, L_0x1319b00; 1 drivers -v0x11b2fc0_0 .net *"_s8", 0 0, L_0x1319e10; 1 drivers -v0x11b30a0_0 .net "out", 7 0, L_0x131af70; alias, 1 drivers -L_0x1319870 .part L_0x13193d0, 0, 1; -L_0x1319a60 .part v0x12010b0_0, 0, 1; -L_0x1319bc0 .part L_0x13193d0, 1, 1; -L_0x1319d20 .part v0x12010b0_0, 1, 1; -L_0x1319ed0 .part L_0x13193d0, 2, 1; -L_0x131a030 .part v0x12010b0_0, 2, 1; -L_0x131a1e0 .part L_0x13193d0, 3, 1; -L_0x131a340 .part v0x12010b0_0, 3, 1; -L_0x131a540 .part L_0x13193d0, 4, 1; -L_0x131a7b0 .part v0x12010b0_0, 4, 1; -L_0x131a920 .part L_0x13193d0, 5, 1; -L_0x131aa80 .part v0x12010b0_0, 5, 1; -L_0x131aca0 .part L_0x13193d0, 6, 1; -L_0x131ae00 .part v0x12010b0_0, 6, 1; -LS_0x131af70_0_0 .concat8 [ 1 1 1 1], L_0x1319760, L_0x1319b00, L_0x1319e10, L_0x131a120; -LS_0x131af70_0_4 .concat8 [ 1 1 1 1], L_0x131a480, L_0x131a8b0, L_0x131abe0, L_0x131ab70; -L_0x131af70 .concat8 [ 4 4 0 0], LS_0x131af70_0_0, LS_0x131af70_0_4; -L_0x131b330 .part L_0x13193d0, 7, 1; -L_0x131b520 .part v0x12010b0_0, 7, 1; -S_0x11b0220 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b0430 .param/l "i" 0 4 54, +C4<00>; -L_0x1319760/d .functor AND 1, L_0x1319870, L_0x1319a60, C4<1>, C4<1>; -L_0x1319760 .delay 1 (30000,30000,30000) L_0x1319760/d; -v0x11b0510_0 .net *"_s0", 0 0, L_0x1319870; 1 drivers -v0x11b05f0_0 .net *"_s1", 0 0, L_0x1319a60; 1 drivers -S_0x11b06d0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b08e0 .param/l "i" 0 4 54, +C4<01>; -L_0x1319b00/d .functor AND 1, L_0x1319bc0, L_0x1319d20, C4<1>, C4<1>; -L_0x1319b00 .delay 1 (30000,30000,30000) L_0x1319b00/d; -v0x11b09a0_0 .net *"_s0", 0 0, L_0x1319bc0; 1 drivers -v0x11b0a80_0 .net *"_s1", 0 0, L_0x1319d20; 1 drivers -S_0x11b0b60 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b0da0 .param/l "i" 0 4 54, +C4<010>; -L_0x1319e10/d .functor AND 1, L_0x1319ed0, L_0x131a030, C4<1>, C4<1>; -L_0x1319e10 .delay 1 (30000,30000,30000) L_0x1319e10/d; -v0x11b0e40_0 .net *"_s0", 0 0, L_0x1319ed0; 1 drivers -v0x11b0f20_0 .net *"_s1", 0 0, L_0x131a030; 1 drivers -S_0x11b1000 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b1210 .param/l "i" 0 4 54, +C4<011>; -L_0x131a120/d .functor AND 1, L_0x131a1e0, L_0x131a340, C4<1>, C4<1>; -L_0x131a120 .delay 1 (30000,30000,30000) L_0x131a120/d; -v0x11b12d0_0 .net *"_s0", 0 0, L_0x131a1e0; 1 drivers -v0x11b13b0_0 .net *"_s1", 0 0, L_0x131a340; 1 drivers -S_0x11b1490 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b16f0 .param/l "i" 0 4 54, +C4<0100>; -L_0x131a480/d .functor AND 1, L_0x131a540, L_0x131a7b0, C4<1>, C4<1>; -L_0x131a480 .delay 1 (30000,30000,30000) L_0x131a480/d; -v0x11b17b0_0 .net *"_s0", 0 0, L_0x131a540; 1 drivers -v0x11b1890_0 .net *"_s1", 0 0, L_0x131a7b0; 1 drivers -S_0x11b1970 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b1b80 .param/l "i" 0 4 54, +C4<0101>; -L_0x131a8b0/d .functor AND 1, L_0x131a920, L_0x131aa80, C4<1>, C4<1>; -L_0x131a8b0 .delay 1 (30000,30000,30000) L_0x131a8b0/d; -v0x11b1c40_0 .net *"_s0", 0 0, L_0x131a920; 1 drivers -v0x11b1d20_0 .net *"_s1", 0 0, L_0x131aa80; 1 drivers -S_0x11b1e00 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b2010 .param/l "i" 0 4 54, +C4<0110>; -L_0x131abe0/d .functor AND 1, L_0x131aca0, L_0x131ae00, C4<1>, C4<1>; -L_0x131abe0 .delay 1 (30000,30000,30000) L_0x131abe0/d; -v0x11b20d0_0 .net *"_s0", 0 0, L_0x131aca0; 1 drivers -v0x11b21b0_0 .net *"_s1", 0 0, L_0x131ae00; 1 drivers -S_0x11b2290 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11affe0; - .timescale -9 -12; -P_0x11b24a0 .param/l "i" 0 4 54, +C4<0111>; -L_0x131ab70/d .functor AND 1, L_0x131b330, L_0x131b520, C4<1>, C4<1>; -L_0x131ab70 .delay 1 (30000,30000,30000) L_0x131ab70/d; -v0x11b2560_0 .net *"_s0", 0 0, L_0x131b330; 1 drivers -v0x11b2640_0 .net *"_s1", 0 0, L_0x131b520; 1 drivers -S_0x11b3200 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11afd90; +v0x2c8b6c0_0 .net "A", 7 0, L_0x2e0bc10; alias, 1 drivers +v0x2c8b7c0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c8b880_0 .net *"_s0", 0 0, L_0x2e0c4e0; 1 drivers +v0x2c8b940_0 .net *"_s12", 0 0, L_0x2e0cea0; 1 drivers +v0x2c8ba20_0 .net *"_s16", 0 0, L_0x2e0d200; 1 drivers +v0x2c8bb50_0 .net *"_s20", 0 0, L_0x2e0d5d0; 1 drivers +v0x2c8bc30_0 .net *"_s24", 0 0, L_0x2e0d900; 1 drivers +v0x2c8bd10_0 .net *"_s28", 0 0, L_0x2e0d890; 1 drivers +v0x2c8bdf0_0 .net *"_s4", 0 0, L_0x2e0c880; 1 drivers +v0x2c8bf60_0 .net *"_s8", 0 0, L_0x2e0cb90; 1 drivers +v0x2c8c040_0 .net "out", 7 0, L_0x2e0dc90; alias, 1 drivers +L_0x2e0c5f0 .part L_0x2e0bc10, 0, 1; +L_0x2e0c7e0 .part v0x2cdd2e0_0, 0, 1; +L_0x2e0c940 .part L_0x2e0bc10, 1, 1; +L_0x2e0caa0 .part v0x2cdd2e0_0, 1, 1; +L_0x2e0cc50 .part L_0x2e0bc10, 2, 1; +L_0x2e0cdb0 .part v0x2cdd2e0_0, 2, 1; +L_0x2e0cf60 .part L_0x2e0bc10, 3, 1; +L_0x2e0d0c0 .part v0x2cdd2e0_0, 3, 1; +L_0x2e0d2c0 .part L_0x2e0bc10, 4, 1; +L_0x2e0d530 .part v0x2cdd2e0_0, 4, 1; +L_0x2e0d640 .part L_0x2e0bc10, 5, 1; +L_0x2e0d7a0 .part v0x2cdd2e0_0, 5, 1; +L_0x2e0d9c0 .part L_0x2e0bc10, 6, 1; +L_0x2e0db20 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e0dc90_0_0 .concat8 [ 1 1 1 1], L_0x2e0c4e0, L_0x2e0c880, L_0x2e0cb90, L_0x2e0cea0; +LS_0x2e0dc90_0_4 .concat8 [ 1 1 1 1], L_0x2e0d200, L_0x2e0d5d0, L_0x2e0d900, L_0x2e0d890; +L_0x2e0dc90 .concat8 [ 4 4 0 0], LS_0x2e0dc90_0_0, LS_0x2e0dc90_0_4; +L_0x2e0dfb0 .part L_0x2e0bc10, 7, 1; +L_0x2e0e1a0 .part v0x2cdd2e0_0, 7, 1; +S_0x2c891c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c893d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2e0c4e0/d .functor AND 1, L_0x2e0c5f0, L_0x2e0c7e0, C4<1>, C4<1>; +L_0x2e0c4e0 .delay 1 (30000,30000,30000) L_0x2e0c4e0/d; +v0x2c894b0_0 .net *"_s0", 0 0, L_0x2e0c5f0; 1 drivers +v0x2c89590_0 .net *"_s1", 0 0, L_0x2e0c7e0; 1 drivers +S_0x2c89670 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c89880 .param/l "i" 0 4 54, +C4<01>; +L_0x2e0c880/d .functor AND 1, L_0x2e0c940, L_0x2e0caa0, C4<1>, C4<1>; +L_0x2e0c880 .delay 1 (30000,30000,30000) L_0x2e0c880/d; +v0x2c89940_0 .net *"_s0", 0 0, L_0x2e0c940; 1 drivers +v0x2c89a20_0 .net *"_s1", 0 0, L_0x2e0caa0; 1 drivers +S_0x2c89b00 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c89d40 .param/l "i" 0 4 54, +C4<010>; +L_0x2e0cb90/d .functor AND 1, L_0x2e0cc50, L_0x2e0cdb0, C4<1>, C4<1>; +L_0x2e0cb90 .delay 1 (30000,30000,30000) L_0x2e0cb90/d; +v0x2c89de0_0 .net *"_s0", 0 0, L_0x2e0cc50; 1 drivers +v0x2c89ec0_0 .net *"_s1", 0 0, L_0x2e0cdb0; 1 drivers +S_0x2c89fa0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c8a1b0 .param/l "i" 0 4 54, +C4<011>; +L_0x2e0cea0/d .functor AND 1, L_0x2e0cf60, L_0x2e0d0c0, C4<1>, C4<1>; +L_0x2e0cea0 .delay 1 (30000,30000,30000) L_0x2e0cea0/d; +v0x2c8a270_0 .net *"_s0", 0 0, L_0x2e0cf60; 1 drivers +v0x2c8a350_0 .net *"_s1", 0 0, L_0x2e0d0c0; 1 drivers +S_0x2c8a430 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c8a690 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e0d200/d .functor AND 1, L_0x2e0d2c0, L_0x2e0d530, C4<1>, C4<1>; +L_0x2e0d200 .delay 1 (30000,30000,30000) L_0x2e0d200/d; +v0x2c8a750_0 .net *"_s0", 0 0, L_0x2e0d2c0; 1 drivers +v0x2c8a830_0 .net *"_s1", 0 0, L_0x2e0d530; 1 drivers +S_0x2c8a910 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c8ab20 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e0d5d0/d .functor AND 1, L_0x2e0d640, L_0x2e0d7a0, C4<1>, C4<1>; +L_0x2e0d5d0 .delay 1 (30000,30000,30000) L_0x2e0d5d0/d; +v0x2c8abe0_0 .net *"_s0", 0 0, L_0x2e0d640; 1 drivers +v0x2c8acc0_0 .net *"_s1", 0 0, L_0x2e0d7a0; 1 drivers +S_0x2c8ada0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c8afb0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e0d900/d .functor AND 1, L_0x2e0d9c0, L_0x2e0db20, C4<1>, C4<1>; +L_0x2e0d900 .delay 1 (30000,30000,30000) L_0x2e0d900/d; +v0x2c8b070_0 .net *"_s0", 0 0, L_0x2e0d9c0; 1 drivers +v0x2c8b150_0 .net *"_s1", 0 0, L_0x2e0db20; 1 drivers +S_0x2c8b230 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c88f80; + .timescale -9 -12; +P_0x2c8b440 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e0d890/d .functor AND 1, L_0x2e0dfb0, L_0x2e0e1a0, C4<1>, C4<1>; +L_0x2e0d890 .delay 1 (30000,30000,30000) L_0x2e0d890/d; +v0x2c8b500_0 .net *"_s0", 0 0, L_0x2e0dfb0; 1 drivers +v0x2c8b5e0_0 .net *"_s1", 0 0, L_0x2e0e1a0; 1 drivers +S_0x2c8c1a0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c88d30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x131cf70/d .functor OR 1, L_0x131d030, L_0x131d1e0, C4<0>, C4<0>; -L_0x131cf70 .delay 1 (30000,30000,30000) L_0x131cf70/d; -v0x11b4d50_0 .net *"_s10", 0 0, L_0x131d030; 1 drivers -v0x11b4e30_0 .net *"_s12", 0 0, L_0x131d1e0; 1 drivers -v0x11b4f10_0 .net "in", 7 0, L_0x131af70; alias, 1 drivers -v0x11b4fe0_0 .net "ors", 1 0, L_0x131cd90; 1 drivers -v0x11b50a0_0 .net "out", 0 0, L_0x131cf70; alias, 1 drivers -L_0x131c160 .part L_0x131af70, 0, 4; -L_0x131cd90 .concat8 [ 1 1 0 0], L_0x131be50, L_0x131ca80; -L_0x131ced0 .part L_0x131af70, 4, 4; -L_0x131d030 .part L_0x131cd90, 0, 1; -L_0x131d1e0 .part L_0x131cd90, 1, 1; -S_0x11b33c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11b3200; +L_0x2e0fbf0/d .functor OR 1, L_0x2e0fcb0, L_0x2e0fe60, C4<0>, C4<0>; +L_0x2e0fbf0 .delay 1 (30000,30000,30000) L_0x2e0fbf0/d; +v0x2c8dcf0_0 .net *"_s10", 0 0, L_0x2e0fcb0; 1 drivers +v0x2c8ddd0_0 .net *"_s12", 0 0, L_0x2e0fe60; 1 drivers +v0x2c8deb0_0 .net "in", 7 0, L_0x2e0dc90; alias, 1 drivers +v0x2c8df80_0 .net "ors", 1 0, L_0x2e0fa10; 1 drivers +v0x2c8e040_0 .net "out", 0 0, L_0x2e0fbf0; alias, 1 drivers +L_0x2e0ede0 .part L_0x2e0dc90, 0, 4; +L_0x2e0fa10 .concat8 [ 1 1 0 0], L_0x2e0ead0, L_0x2e0f700; +L_0x2e0fb50 .part L_0x2e0dc90, 4, 4; +L_0x2e0fcb0 .part L_0x2e0fa10, 0, 1; +L_0x2e0fe60 .part L_0x2e0fa10, 1, 1; +S_0x2c8c360 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c8c1a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x131b610/d .functor OR 1, L_0x131b6d0, L_0x131b830, C4<0>, C4<0>; -L_0x131b610 .delay 1 (30000,30000,30000) L_0x131b610/d; -L_0x131ba60/d .functor OR 1, L_0x131bb70, L_0x131bcd0, C4<0>, C4<0>; -L_0x131ba60 .delay 1 (30000,30000,30000) L_0x131ba60/d; -L_0x131be50/d .functor OR 1, L_0x131bec0, L_0x131c070, C4<0>, C4<0>; -L_0x131be50 .delay 1 (30000,30000,30000) L_0x131be50/d; -v0x11b3610_0 .net *"_s0", 0 0, L_0x131b610; 1 drivers -v0x11b3710_0 .net *"_s10", 0 0, L_0x131bb70; 1 drivers -v0x11b37f0_0 .net *"_s12", 0 0, L_0x131bcd0; 1 drivers -v0x11b38b0_0 .net *"_s14", 0 0, L_0x131bec0; 1 drivers -v0x11b3990_0 .net *"_s16", 0 0, L_0x131c070; 1 drivers -v0x11b3ac0_0 .net *"_s3", 0 0, L_0x131b6d0; 1 drivers -v0x11b3ba0_0 .net *"_s5", 0 0, L_0x131b830; 1 drivers -v0x11b3c80_0 .net *"_s6", 0 0, L_0x131ba60; 1 drivers -v0x11b3d60_0 .net "in", 3 0, L_0x131c160; 1 drivers -v0x11b3ed0_0 .net "ors", 1 0, L_0x131b970; 1 drivers -v0x11b3fb0_0 .net "out", 0 0, L_0x131be50; 1 drivers -L_0x131b6d0 .part L_0x131c160, 0, 1; -L_0x131b830 .part L_0x131c160, 1, 1; -L_0x131b970 .concat8 [ 1 1 0 0], L_0x131b610, L_0x131ba60; -L_0x131bb70 .part L_0x131c160, 2, 1; -L_0x131bcd0 .part L_0x131c160, 3, 1; -L_0x131bec0 .part L_0x131b970, 0, 1; -L_0x131c070 .part L_0x131b970, 1, 1; -S_0x11b40d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11b3200; +L_0x2e0e290/d .functor OR 1, L_0x2e0e350, L_0x2e0e4b0, C4<0>, C4<0>; +L_0x2e0e290 .delay 1 (30000,30000,30000) L_0x2e0e290/d; +L_0x2e0e6e0/d .functor OR 1, L_0x2e0e7f0, L_0x2e0e950, C4<0>, C4<0>; +L_0x2e0e6e0 .delay 1 (30000,30000,30000) L_0x2e0e6e0/d; +L_0x2e0ead0/d .functor OR 1, L_0x2e0eb40, L_0x2e0ecf0, C4<0>, C4<0>; +L_0x2e0ead0 .delay 1 (30000,30000,30000) L_0x2e0ead0/d; +v0x2c8c5b0_0 .net *"_s0", 0 0, L_0x2e0e290; 1 drivers +v0x2c8c6b0_0 .net *"_s10", 0 0, L_0x2e0e7f0; 1 drivers +v0x2c8c790_0 .net *"_s12", 0 0, L_0x2e0e950; 1 drivers +v0x2c8c850_0 .net *"_s14", 0 0, L_0x2e0eb40; 1 drivers +v0x2c8c930_0 .net *"_s16", 0 0, L_0x2e0ecf0; 1 drivers +v0x2c8ca60_0 .net *"_s3", 0 0, L_0x2e0e350; 1 drivers +v0x2c8cb40_0 .net *"_s5", 0 0, L_0x2e0e4b0; 1 drivers +v0x2c8cc20_0 .net *"_s6", 0 0, L_0x2e0e6e0; 1 drivers +v0x2c8cd00_0 .net "in", 3 0, L_0x2e0ede0; 1 drivers +v0x2c8ce70_0 .net "ors", 1 0, L_0x2e0e5f0; 1 drivers +v0x2c8cf50_0 .net "out", 0 0, L_0x2e0ead0; 1 drivers +L_0x2e0e350 .part L_0x2e0ede0, 0, 1; +L_0x2e0e4b0 .part L_0x2e0ede0, 1, 1; +L_0x2e0e5f0 .concat8 [ 1 1 0 0], L_0x2e0e290, L_0x2e0e6e0; +L_0x2e0e7f0 .part L_0x2e0ede0, 2, 1; +L_0x2e0e950 .part L_0x2e0ede0, 3, 1; +L_0x2e0eb40 .part L_0x2e0e5f0, 0, 1; +L_0x2e0ecf0 .part L_0x2e0e5f0, 1, 1; +S_0x2c8d070 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c8c1a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x131c290/d .functor OR 1, L_0x131c300, L_0x131c460, C4<0>, C4<0>; -L_0x131c290 .delay 1 (30000,30000,30000) L_0x131c290/d; -L_0x131c690/d .functor OR 1, L_0x131c7a0, L_0x131c900, C4<0>, C4<0>; -L_0x131c690 .delay 1 (30000,30000,30000) L_0x131c690/d; -L_0x131ca80/d .functor OR 1, L_0x131caf0, L_0x131cca0, C4<0>, C4<0>; -L_0x131ca80 .delay 1 (30000,30000,30000) L_0x131ca80/d; -v0x11b4290_0 .net *"_s0", 0 0, L_0x131c290; 1 drivers -v0x11b4390_0 .net *"_s10", 0 0, L_0x131c7a0; 1 drivers -v0x11b4470_0 .net *"_s12", 0 0, L_0x131c900; 1 drivers -v0x11b4530_0 .net *"_s14", 0 0, L_0x131caf0; 1 drivers -v0x11b4610_0 .net *"_s16", 0 0, L_0x131cca0; 1 drivers -v0x11b4740_0 .net *"_s3", 0 0, L_0x131c300; 1 drivers -v0x11b4820_0 .net *"_s5", 0 0, L_0x131c460; 1 drivers -v0x11b4900_0 .net *"_s6", 0 0, L_0x131c690; 1 drivers -v0x11b49e0_0 .net "in", 3 0, L_0x131ced0; 1 drivers -v0x11b4b50_0 .net "ors", 1 0, L_0x131c5a0; 1 drivers -v0x11b4c30_0 .net "out", 0 0, L_0x131ca80; 1 drivers -L_0x131c300 .part L_0x131ced0, 0, 1; -L_0x131c460 .part L_0x131ced0, 1, 1; -L_0x131c5a0 .concat8 [ 1 1 0 0], L_0x131c290, L_0x131c690; -L_0x131c7a0 .part L_0x131ced0, 2, 1; -L_0x131c900 .part L_0x131ced0, 3, 1; -L_0x131caf0 .part L_0x131c5a0, 0, 1; -L_0x131cca0 .part L_0x131c5a0, 1, 1; -S_0x11b5540 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11a8ec0; +L_0x2e0ef10/d .functor OR 1, L_0x2e0ef80, L_0x2e0f0e0, C4<0>, C4<0>; +L_0x2e0ef10 .delay 1 (30000,30000,30000) L_0x2e0ef10/d; +L_0x2e0f310/d .functor OR 1, L_0x2e0f420, L_0x2e0f580, C4<0>, C4<0>; +L_0x2e0f310 .delay 1 (30000,30000,30000) L_0x2e0f310/d; +L_0x2e0f700/d .functor OR 1, L_0x2e0f770, L_0x2e0f920, C4<0>, C4<0>; +L_0x2e0f700 .delay 1 (30000,30000,30000) L_0x2e0f700/d; +v0x2c8d230_0 .net *"_s0", 0 0, L_0x2e0ef10; 1 drivers +v0x2c8d330_0 .net *"_s10", 0 0, L_0x2e0f420; 1 drivers +v0x2c8d410_0 .net *"_s12", 0 0, L_0x2e0f580; 1 drivers +v0x2c8d4d0_0 .net *"_s14", 0 0, L_0x2e0f770; 1 drivers +v0x2c8d5b0_0 .net *"_s16", 0 0, L_0x2e0f920; 1 drivers +v0x2c8d6e0_0 .net *"_s3", 0 0, L_0x2e0ef80; 1 drivers +v0x2c8d7c0_0 .net *"_s5", 0 0, L_0x2e0f0e0; 1 drivers +v0x2c8d8a0_0 .net *"_s6", 0 0, L_0x2e0f310; 1 drivers +v0x2c8d980_0 .net "in", 3 0, L_0x2e0fb50; 1 drivers +v0x2c8daf0_0 .net "ors", 1 0, L_0x2e0f220; 1 drivers +v0x2c8dbd0_0 .net "out", 0 0, L_0x2e0f700; 1 drivers +L_0x2e0ef80 .part L_0x2e0fb50, 0, 1; +L_0x2e0f0e0 .part L_0x2e0fb50, 1, 1; +L_0x2e0f220 .concat8 [ 1 1 0 0], L_0x2e0ef10, L_0x2e0f310; +L_0x2e0f420 .part L_0x2e0fb50, 2, 1; +L_0x2e0f580 .part L_0x2e0fb50, 3, 1; +L_0x2e0f770 .part L_0x2e0f220, 0, 1; +L_0x2e0f920 .part L_0x2e0f220, 1, 1; +S_0x2c8e4e0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c81e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -15494,80 +16395,80 @@ S_0x11b5540 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11a8ec0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1318740/d .functor XNOR 1, L_0x1320ea0, L_0x1321000, C4<0>, C4<0>; -L_0x1318740 .delay 1 (20000,20000,20000) L_0x1318740/d; -L_0x13189b0/d .functor AND 1, L_0x1320ea0, L_0x1317680, C4<1>, C4<1>; -L_0x13189b0 .delay 1 (30000,30000,30000) L_0x13189b0/d; -L_0x1318a20/d .functor AND 1, L_0x1318740, L_0x13172c0, C4<1>, C4<1>; -L_0x1318a20 .delay 1 (30000,30000,30000) L_0x1318a20/d; -L_0x1318b80/d .functor OR 1, L_0x1318a20, L_0x13189b0, C4<0>, C4<0>; -L_0x1318b80 .delay 1 (30000,30000,30000) L_0x1318b80/d; -v0x11b57f0_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers -v0x11b58e0_0 .net "a_", 0 0, L_0x1317570; alias, 1 drivers -v0x11b59a0_0 .net "b", 0 0, L_0x1321000; alias, 1 drivers -v0x11b5a90_0 .net "b_", 0 0, L_0x1317680; alias, 1 drivers -v0x11b5b30_0 .net "carryin", 0 0, L_0x13172c0; alias, 1 drivers -v0x11b5c70_0 .net "eq", 0 0, L_0x1318740; 1 drivers -v0x11b5d30_0 .net "lt", 0 0, L_0x13189b0; 1 drivers -v0x11b5df0_0 .net "out", 0 0, L_0x1318b80; 1 drivers -v0x11b5eb0_0 .net "w0", 0 0, L_0x1318a20; 1 drivers -S_0x11b6100 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11a8ec0; +L_0x2e0aac0/d .functor XNOR 1, L_0x2e13af0, L_0x2e13c50, C4<0>, C4<0>; +L_0x2e0aac0 .delay 1 (20000,20000,20000) L_0x2e0aac0/d; +L_0x2e0ac40/d .functor AND 1, L_0x2e13af0, L_0x2e097b0, C4<1>, C4<1>; +L_0x2e0ac40 .delay 1 (30000,30000,30000) L_0x2e0ac40/d; +L_0x2e0ada0/d .functor AND 1, L_0x2e0aac0, L_0x2e09440, C4<1>, C4<1>; +L_0x2e0ada0 .delay 1 (30000,30000,30000) L_0x2e0ada0/d; +L_0x2e0aeb0/d .functor OR 1, L_0x2e0ada0, L_0x2e0ac40, C4<0>, C4<0>; +L_0x2e0aeb0 .delay 1 (30000,30000,30000) L_0x2e0aeb0/d; +v0x2c8e790_0 .net "a", 0 0, L_0x2e13af0; alias, 1 drivers +v0x2c8e880_0 .net "a_", 0 0, L_0x2e096f0; alias, 1 drivers +v0x2c8e940_0 .net "b", 0 0, L_0x2e13c50; alias, 1 drivers +v0x2c8ea30_0 .net "b_", 0 0, L_0x2e097b0; alias, 1 drivers +v0x2c8ead0_0 .net "carryin", 0 0, L_0x2e09440; alias, 1 drivers +v0x2c8ec10_0 .net "eq", 0 0, L_0x2e0aac0; 1 drivers +v0x2c8ecd0_0 .net "lt", 0 0, L_0x2e0ac40; 1 drivers +v0x2c8ed90_0 .net "out", 0 0, L_0x2e0aeb0; 1 drivers +v0x2c8ee50_0 .net "w0", 0 0, L_0x2e0ada0; 1 drivers +S_0x2c8f0a0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c81e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1318520/d .functor OR 1, L_0x1318070, L_0x11b7360, C4<0>, C4<0>; -L_0x1318520 .delay 1 (30000,30000,30000) L_0x1318520/d; -v0x11b6ef0_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers -v0x11b7040_0 .net "b", 0 0, L_0x1317680; alias, 1 drivers -v0x11b7100_0 .net "c1", 0 0, L_0x1318070; 1 drivers -v0x11b71a0_0 .net "c2", 0 0, L_0x11b7360; 1 drivers -v0x11b7270_0 .net "carryin", 0 0, L_0x13172c0; alias, 1 drivers -v0x11b73f0_0 .net "carryout", 0 0, L_0x1318520; 1 drivers -v0x11b7490_0 .net "s1", 0 0, L_0x1317fb0; 1 drivers -v0x11b7530_0 .net "sum", 0 0, L_0x13181d0; 1 drivers -S_0x11b6350 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11b6100; +L_0x2e0a6a0/d .functor OR 1, L_0x2e0a1a0, L_0x2c90300, C4<0>, C4<0>; +L_0x2e0a6a0 .delay 1 (30000,30000,30000) L_0x2e0a6a0/d; +v0x2c8fe90_0 .net "a", 0 0, L_0x2e13af0; alias, 1 drivers +v0x2c8ffe0_0 .net "b", 0 0, L_0x2e097b0; alias, 1 drivers +v0x2c900a0_0 .net "c1", 0 0, L_0x2e0a1a0; 1 drivers +v0x2c90140_0 .net "c2", 0 0, L_0x2c90300; 1 drivers +v0x2c90210_0 .net "carryin", 0 0, L_0x2e09440; alias, 1 drivers +v0x2c90390_0 .net "carryout", 0 0, L_0x2e0a6a0; 1 drivers +v0x2c90430_0 .net "s1", 0 0, L_0x2e0a0e0; 1 drivers +v0x2c904d0_0 .net "sum", 0 0, L_0x2e0a300; 1 drivers +S_0x2c8f2f0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c8f0a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1317fb0/d .functor XOR 1, L_0x1320ea0, L_0x1317680, C4<0>, C4<0>; -L_0x1317fb0 .delay 1 (30000,30000,30000) L_0x1317fb0/d; -L_0x1318070/d .functor AND 1, L_0x1320ea0, L_0x1317680, C4<1>, C4<1>; -L_0x1318070 .delay 1 (30000,30000,30000) L_0x1318070/d; -v0x11b65b0_0 .net "a", 0 0, L_0x1320ea0; alias, 1 drivers -v0x11b6670_0 .net "b", 0 0, L_0x1317680; alias, 1 drivers -v0x11b6730_0 .net "carryout", 0 0, L_0x1318070; alias, 1 drivers -v0x11b67d0_0 .net "sum", 0 0, L_0x1317fb0; alias, 1 drivers -S_0x11b6900 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11b6100; +L_0x2e0a0e0/d .functor XOR 1, L_0x2e13af0, L_0x2e097b0, C4<0>, C4<0>; +L_0x2e0a0e0 .delay 1 (30000,30000,30000) L_0x2e0a0e0/d; +L_0x2e0a1a0/d .functor AND 1, L_0x2e13af0, L_0x2e097b0, C4<1>, C4<1>; +L_0x2e0a1a0 .delay 1 (30000,30000,30000) L_0x2e0a1a0/d; +v0x2c8f550_0 .net "a", 0 0, L_0x2e13af0; alias, 1 drivers +v0x2c8f610_0 .net "b", 0 0, L_0x2e097b0; alias, 1 drivers +v0x2c8f6d0_0 .net "carryout", 0 0, L_0x2e0a1a0; alias, 1 drivers +v0x2c8f770_0 .net "sum", 0 0, L_0x2e0a0e0; alias, 1 drivers +S_0x2c8f8a0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c8f0a0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x13181d0/d .functor XOR 1, L_0x1317fb0, L_0x13172c0, C4<0>, C4<0>; -L_0x13181d0 .delay 1 (30000,30000,30000) L_0x13181d0/d; -L_0x11b7360/d .functor AND 1, L_0x1317fb0, L_0x13172c0, C4<1>, C4<1>; -L_0x11b7360 .delay 1 (30000,30000,30000) L_0x11b7360/d; -v0x11b6b60_0 .net "a", 0 0, L_0x1317fb0; alias, 1 drivers -v0x11b6c30_0 .net "b", 0 0, L_0x13172c0; alias, 1 drivers -v0x11b6cd0_0 .net "carryout", 0 0, L_0x11b7360; alias, 1 drivers -v0x11b6da0_0 .net "sum", 0 0, L_0x13181d0; alias, 1 drivers -S_0x11b8950 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11a8bf0; - .timescale -9 -12; -L_0x2b0ab3d06f98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d06fe0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1320f40/d .functor OR 1, L_0x2b0ab3d06f98, L_0x2b0ab3d06fe0, C4<0>, C4<0>; -L_0x1320f40 .delay 1 (30000,30000,30000) L_0x1320f40/d; -v0x11b8b40_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d06f98; 1 drivers -v0x11b8c20_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d06fe0; 1 drivers -S_0x11b8d00 .scope generate, "alu_slices[29]" "alu_slices[29]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11b8f10 .param/l "i" 0 3 41, +C4<011101>; -S_0x11b8fd0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11b8d00; +L_0x2e0a300/d .functor XOR 1, L_0x2e0a0e0, L_0x2e09440, C4<0>, C4<0>; +L_0x2e0a300 .delay 1 (30000,30000,30000) L_0x2e0a300/d; +L_0x2c90300/d .functor AND 1, L_0x2e0a0e0, L_0x2e09440, C4<1>, C4<1>; +L_0x2c90300 .delay 1 (30000,30000,30000) L_0x2c90300/d; +v0x2c8fb00_0 .net "a", 0 0, L_0x2e0a0e0; alias, 1 drivers +v0x2c8fbd0_0 .net "b", 0 0, L_0x2e09440; alias, 1 drivers +v0x2c8fc70_0 .net "carryout", 0 0, L_0x2c90300; alias, 1 drivers +v0x2c8fd40_0 .net "sum", 0 0, L_0x2e0a300; alias, 1 drivers +S_0x2c92560 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c81b90; + .timescale -9 -12; +L_0x2ac6110bd128 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd170 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e0bf50/d .functor OR 1, L_0x2ac6110bd128, L_0x2ac6110bd170, C4<0>, C4<0>; +L_0x2e0bf50 .delay 1 (30000,30000,30000) L_0x2e0bf50/d; +v0x2c92750_0 .net/2u *"_s0", 0 0, L_0x2ac6110bd128; 1 drivers +v0x2c92830_0 .net/2u *"_s2", 0 0, L_0x2ac6110bd170; 1 drivers +S_0x2c92910 .scope generate, "alu_slices[29]" "alu_slices[29]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2c92b20 .param/l "i" 0 3 39, +C4<011101>; +S_0x2c92be0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2c92910; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -15576,445 +16477,476 @@ S_0x11b8fd0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11b8d00; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1317400/d .functor NOT 1, L_0x132ab70, C4<0>, C4<0>, C4<0>; -L_0x1317400 .delay 1 (10000,10000,10000) L_0x1317400/d; -L_0x13213b0/d .functor NOT 1, L_0x13210a0, C4<0>, C4<0>, C4<0>; -L_0x13213b0 .delay 1 (10000,10000,10000) L_0x13213b0/d; -L_0x13222a0/d .functor XOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; -L_0x13222a0 .delay 1 (30000,30000,30000) L_0x13222a0/d; -L_0x2b0ab3d07028 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d07070 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1322950/d .functor OR 1, L_0x2b0ab3d07028, L_0x2b0ab3d07070, C4<0>, C4<0>; -L_0x1322950 .delay 1 (30000,30000,30000) L_0x1322950/d; -L_0x1322b50/d .functor AND 1, L_0x132ab70, L_0x13210a0, C4<1>, C4<1>; -L_0x1322b50 .delay 1 (30000,30000,30000) L_0x1322b50/d; -L_0x1322c60/d .functor NAND 1, L_0x132ab70, L_0x13210a0, C4<1>, C4<1>; -L_0x1322c60 .delay 1 (20000,20000,20000) L_0x1322c60/d; -L_0x1322dc0/d .functor XOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; -L_0x1322dc0 .delay 1 (20000,20000,20000) L_0x1322dc0/d; -L_0x1323270/d .functor OR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; -L_0x1323270 .delay 1 (30000,30000,30000) L_0x1323270/d; -L_0x132aa70/d .functor NOT 1, L_0x1326c10, C4<0>, C4<0>, C4<0>; -L_0x132aa70 .delay 1 (10000,10000,10000) L_0x132aa70/d; -v0x11c7700_0 .net "A", 0 0, L_0x132ab70; 1 drivers -v0x11c77c0_0 .net "A_", 0 0, L_0x1317400; 1 drivers -v0x11c7880_0 .net "B", 0 0, L_0x13210a0; 1 drivers -v0x11c7950_0 .net "B_", 0 0, L_0x13213b0; 1 drivers -v0x11c79f0_0 .net *"_s12", 0 0, L_0x1322950; 1 drivers -v0x11c7ae0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d07028; 1 drivers -v0x11c7ba0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d07070; 1 drivers -v0x11c7c80_0 .net *"_s18", 0 0, L_0x1322b50; 1 drivers -v0x11c7d60_0 .net *"_s20", 0 0, L_0x1322c60; 1 drivers -v0x11c7ed0_0 .net *"_s22", 0 0, L_0x1322dc0; 1 drivers -v0x11c7fb0_0 .net *"_s24", 0 0, L_0x1323270; 1 drivers -o0x2b0ab3ce9cd8 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x11c8090_0 name=_s30 -o0x2b0ab3ce9d08 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x11c8170_0 name=_s32 -v0x11c8250_0 .net *"_s8", 0 0, L_0x13222a0; 1 drivers -v0x11c8330_0 .net "carryin", 0 0, L_0x1321140; 1 drivers -v0x11c83d0_0 .net "carryout", 0 0, L_0x132a710; 1 drivers -v0x11c8470_0 .net "carryouts", 7 0, L_0x13560b0; 1 drivers -v0x11c8620_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11c86c0_0 .net "result", 0 0, L_0x1326c10; 1 drivers -v0x11c87b0_0 .net "results", 7 0, L_0x1323040; 1 drivers -v0x11c88c0_0 .net "zero", 0 0, L_0x132aa70; 1 drivers -LS_0x1323040_0_0 .concat8 [ 1 1 1 1], L_0x1321770, L_0x1321df0, L_0x13222a0, L_0x1322950; -LS_0x1323040_0_4 .concat8 [ 1 1 1 1], L_0x1322b50, L_0x1322c60, L_0x1322dc0, L_0x1323270; -L_0x1323040 .concat8 [ 4 4 0 0], LS_0x1323040_0_0, LS_0x1323040_0_4; -LS_0x13560b0_0_0 .concat [ 1 1 1 1], L_0x1321a70, L_0x1322140, o0x2b0ab3ce9cd8, L_0x13227a0; -LS_0x13560b0_0_4 .concat [ 4 0 0 0], o0x2b0ab3ce9d08; -L_0x13560b0 .concat [ 4 4 0 0], LS_0x13560b0_0_0, LS_0x13560b0_0_4; -S_0x11b9250 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11b8fd0; +L_0x2e09530/d .functor NOT 1, L_0x2e1e310, C4<0>, C4<0>, C4<0>; +L_0x2e09530 .delay 1 (10000,10000,10000) L_0x2e09530/d; +L_0x2e13fb0/d .functor NOT 1, L_0x2e13cf0, C4<0>, C4<0>, C4<0>; +L_0x2e13fb0 .delay 1 (10000,10000,10000) L_0x2e13fb0/d; +L_0x2e14f60/d .functor XOR 1, L_0x2e1e310, L_0x2e13cf0, C4<0>, C4<0>; +L_0x2e14f60 .delay 1 (30000,30000,30000) L_0x2e14f60/d; +L_0x2ac6110bd1b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd200 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e15020/d .functor OR 1, L_0x2ac6110bd1b8, L_0x2ac6110bd200, C4<0>, C4<0>; +L_0x2e15020 .delay 1 (30000,30000,30000) L_0x2e15020/d; +L_0x2ac6110bd248 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd290 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e157c0/d .functor OR 1, L_0x2ac6110bd248, L_0x2ac6110bd290, C4<0>, C4<0>; +L_0x2e157c0 .delay 1 (30000,30000,30000) L_0x2e157c0/d; +L_0x2e159c0/d .functor AND 1, L_0x2e1e310, L_0x2e13cf0, C4<1>, C4<1>; +L_0x2e159c0 .delay 1 (30000,30000,30000) L_0x2e159c0/d; +L_0x2ac6110bd2d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd320 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e15a80/d .functor OR 1, L_0x2ac6110bd2d8, L_0x2ac6110bd320, C4<0>, C4<0>; +L_0x2e15a80 .delay 1 (30000,30000,30000) L_0x2e15a80/d; +L_0x2e15c80/d .functor NAND 1, L_0x2e1e310, L_0x2e13cf0, C4<1>, C4<1>; +L_0x2e15c80 .delay 1 (20000,20000,20000) L_0x2e15c80/d; +L_0x2ac6110bd368 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd3b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e15d90/d .functor OR 1, L_0x2ac6110bd368, L_0x2ac6110bd3b0, C4<0>, C4<0>; +L_0x2e15d90 .delay 1 (30000,30000,30000) L_0x2e15d90/d; +L_0x2e15f40/d .functor NOR 1, L_0x2e1e310, L_0x2e13cf0, C4<0>, C4<0>; +L_0x2e15f40 .delay 1 (20000,20000,20000) L_0x2e15f40/d; +L_0x2ac6110bd3f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd440 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e16210/d .functor OR 1, L_0x2ac6110bd3f8, L_0x2ac6110bd440, C4<0>, C4<0>; +L_0x2e16210 .delay 1 (30000,30000,30000) L_0x2e16210/d; +L_0x2e16610/d .functor OR 1, L_0x2e1e310, L_0x2e13cf0, C4<0>, C4<0>; +L_0x2e16610 .delay 1 (30000,30000,30000) L_0x2e16610/d; +L_0x2ac6110bd488 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd4d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e16ab0/d .functor OR 1, L_0x2ac6110bd488, L_0x2ac6110bd4d0, C4<0>, C4<0>; +L_0x2e16ab0 .delay 1 (30000,30000,30000) L_0x2e16ab0/d; +L_0x2e1e210/d .functor NOT 1, L_0x2e1a470, C4<0>, C4<0>, C4<0>; +L_0x2e1e210 .delay 1 (10000,10000,10000) L_0x2e1e210/d; +v0x2ca1310_0 .net "A", 0 0, L_0x2e1e310; 1 drivers +v0x2ca13d0_0 .net "A_", 0 0, L_0x2e09530; 1 drivers +v0x2ca1490_0 .net "B", 0 0, L_0x2e13cf0; 1 drivers +v0x2ca1560_0 .net "B_", 0 0, L_0x2e13fb0; 1 drivers +v0x2ca1600_0 .net *"_s11", 0 0, L_0x2e15020; 1 drivers +v0x2ca16f0_0 .net/2s *"_s13", 0 0, L_0x2ac6110bd1b8; 1 drivers +v0x2ca17b0_0 .net/2s *"_s15", 0 0, L_0x2ac6110bd200; 1 drivers +v0x2ca1890_0 .net *"_s19", 0 0, L_0x2e157c0; 1 drivers +v0x2ca1970_0 .net/2s *"_s21", 0 0, L_0x2ac6110bd248; 1 drivers +v0x2ca1ae0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bd290; 1 drivers +v0x2ca1bc0_0 .net *"_s25", 0 0, L_0x2e159c0; 1 drivers +v0x2ca1ca0_0 .net *"_s28", 0 0, L_0x2e15a80; 1 drivers +v0x2ca1d80_0 .net/2s *"_s30", 0 0, L_0x2ac6110bd2d8; 1 drivers +v0x2ca1e60_0 .net/2s *"_s32", 0 0, L_0x2ac6110bd320; 1 drivers +v0x2ca1f40_0 .net *"_s34", 0 0, L_0x2e15c80; 1 drivers +v0x2ca2020_0 .net *"_s37", 0 0, L_0x2e15d90; 1 drivers +v0x2ca2100_0 .net/2s *"_s39", 0 0, L_0x2ac6110bd368; 1 drivers +v0x2ca22b0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bd3b0; 1 drivers +v0x2ca2350_0 .net *"_s43", 0 0, L_0x2e15f40; 1 drivers +v0x2ca2430_0 .net *"_s46", 0 0, L_0x2e16210; 1 drivers +v0x2ca2510_0 .net/2s *"_s48", 0 0, L_0x2ac6110bd3f8; 1 drivers +v0x2ca25f0_0 .net/2s *"_s50", 0 0, L_0x2ac6110bd440; 1 drivers +v0x2ca26d0_0 .net *"_s52", 0 0, L_0x2e16610; 1 drivers +v0x2ca27b0_0 .net *"_s56", 0 0, L_0x2e16ab0; 1 drivers +v0x2ca2890_0 .net/2s *"_s59", 0 0, L_0x2ac6110bd488; 1 drivers +v0x2ca2970_0 .net/2s *"_s61", 0 0, L_0x2ac6110bd4d0; 1 drivers +v0x2ca2a50_0 .net *"_s8", 0 0, L_0x2e14f60; 1 drivers +v0x2ca2b30_0 .net "carryin", 0 0, L_0x2e13d90; 1 drivers +v0x2ca2bd0_0 .net "carryout", 0 0, L_0x2e1deb0; 1 drivers +v0x2ca2c70_0 .net "carryouts", 7 0, L_0x2e16720; 1 drivers +v0x2ca2d80_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ca2e40_0 .net "result", 0 0, L_0x2e1a470; 1 drivers +v0x2ca2f30_0 .net "results", 7 0, L_0x2e163e0; 1 drivers +v0x2ca2210_0 .net "zero", 0 0, L_0x2e1e210; 1 drivers +LS_0x2e163e0_0_0 .concat8 [ 1 1 1 1], L_0x2e14480, L_0x2e14ab0, L_0x2e14f60, L_0x2e157c0; +LS_0x2e163e0_0_4 .concat8 [ 1 1 1 1], L_0x2e159c0, L_0x2e15c80, L_0x2e15f40, L_0x2e16610; +L_0x2e163e0 .concat8 [ 4 4 0 0], LS_0x2e163e0_0_0, LS_0x2e163e0_0_4; +LS_0x2e16720_0_0 .concat8 [ 1 1 1 1], L_0x2e14730, L_0x2e14e00, L_0x2e15020, L_0x2e15610; +LS_0x2e16720_0_4 .concat8 [ 1 1 1 1], L_0x2e15a80, L_0x2e15d90, L_0x2e16210, L_0x2e16ab0; +L_0x2e16720 .concat8 [ 4 4 0 0], LS_0x2e16720_0_0, LS_0x2e16720_0_4; +S_0x2c92e60 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2c92be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1321a70/d .functor OR 1, L_0x13215a0, L_0x1321960, C4<0>, C4<0>; -L_0x1321a70 .delay 1 (30000,30000,30000) L_0x1321a70/d; -v0x11ba080_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers -v0x11ba140_0 .net "b", 0 0, L_0x13210a0; alias, 1 drivers -v0x11ba210_0 .net "c1", 0 0, L_0x13215a0; 1 drivers -v0x11ba310_0 .net "c2", 0 0, L_0x1321960; 1 drivers -v0x11ba3e0_0 .net "carryin", 0 0, L_0x1321140; alias, 1 drivers -v0x11ba4d0_0 .net "carryout", 0 0, L_0x1321a70; 1 drivers -v0x11ba570_0 .net "s1", 0 0, L_0x131aef0; 1 drivers -v0x11ba660_0 .net "sum", 0 0, L_0x1321770; 1 drivers -S_0x11b94c0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11b9250; +L_0x2e14730/d .functor OR 1, L_0x2e14210, L_0x2e145d0, C4<0>, C4<0>; +L_0x2e14730 .delay 1 (30000,30000,30000) L_0x2e14730/d; +v0x2c93c90_0 .net "a", 0 0, L_0x2e1e310; alias, 1 drivers +v0x2c93d50_0 .net "b", 0 0, L_0x2e13cf0; alias, 1 drivers +v0x2c93e20_0 .net "c1", 0 0, L_0x2e14210; 1 drivers +v0x2c93f20_0 .net "c2", 0 0, L_0x2e145d0; 1 drivers +v0x2c93ff0_0 .net "carryin", 0 0, L_0x2e13d90; alias, 1 drivers +v0x2c940e0_0 .net "carryout", 0 0, L_0x2e14730; 1 drivers +v0x2c94180_0 .net "s1", 0 0, L_0x2e141a0; 1 drivers +v0x2c94270_0 .net "sum", 0 0, L_0x2e14480; 1 drivers +S_0x2c930d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c92e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x131aef0/d .functor XOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; -L_0x131aef0 .delay 1 (30000,30000,30000) L_0x131aef0/d; -L_0x13215a0/d .functor AND 1, L_0x132ab70, L_0x13210a0, C4<1>, C4<1>; -L_0x13215a0 .delay 1 (30000,30000,30000) L_0x13215a0/d; -v0x11b9720_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers -v0x11b9800_0 .net "b", 0 0, L_0x13210a0; alias, 1 drivers -v0x11b98c0_0 .net "carryout", 0 0, L_0x13215a0; alias, 1 drivers -v0x11b9960_0 .net "sum", 0 0, L_0x131aef0; alias, 1 drivers -S_0x11b9aa0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11b9250; +L_0x2e141a0/d .functor XOR 1, L_0x2e1e310, L_0x2e13cf0, C4<0>, C4<0>; +L_0x2e141a0 .delay 1 (30000,30000,30000) L_0x2e141a0/d; +L_0x2e14210/d .functor AND 1, L_0x2e1e310, L_0x2e13cf0, C4<1>, C4<1>; +L_0x2e14210 .delay 1 (30000,30000,30000) L_0x2e14210/d; +v0x2c93330_0 .net "a", 0 0, L_0x2e1e310; alias, 1 drivers +v0x2c93410_0 .net "b", 0 0, L_0x2e13cf0; alias, 1 drivers +v0x2c934d0_0 .net "carryout", 0 0, L_0x2e14210; alias, 1 drivers +v0x2c93570_0 .net "sum", 0 0, L_0x2e141a0; alias, 1 drivers +S_0x2c936b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c92e60; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1321770/d .functor XOR 1, L_0x131aef0, L_0x1321140, C4<0>, C4<0>; -L_0x1321770 .delay 1 (30000,30000,30000) L_0x1321770/d; -L_0x1321960/d .functor AND 1, L_0x131aef0, L_0x1321140, C4<1>, C4<1>; -L_0x1321960 .delay 1 (30000,30000,30000) L_0x1321960/d; -v0x11b9d00_0 .net "a", 0 0, L_0x131aef0; alias, 1 drivers -v0x11b9da0_0 .net "b", 0 0, L_0x1321140; alias, 1 drivers -v0x11b9e40_0 .net "carryout", 0 0, L_0x1321960; alias, 1 drivers -v0x11b9f10_0 .net "sum", 0 0, L_0x1321770; alias, 1 drivers -S_0x11ba730 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11b8fd0; +L_0x2e14480/d .functor XOR 1, L_0x2e141a0, L_0x2e13d90, C4<0>, C4<0>; +L_0x2e14480 .delay 1 (30000,30000,30000) L_0x2e14480/d; +L_0x2e145d0/d .functor AND 1, L_0x2e141a0, L_0x2e13d90, C4<1>, C4<1>; +L_0x2e145d0 .delay 1 (30000,30000,30000) L_0x2e145d0/d; +v0x2c93910_0 .net "a", 0 0, L_0x2e141a0; alias, 1 drivers +v0x2c939b0_0 .net "b", 0 0, L_0x2e13d90; alias, 1 drivers +v0x2c93a50_0 .net "carryout", 0 0, L_0x2e145d0; alias, 1 drivers +v0x2c93b20_0 .net "sum", 0 0, L_0x2e14480; alias, 1 drivers +S_0x2c94340 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2c92be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11bfb20_0 .net "ands", 7 0, L_0x1328710; 1 drivers -v0x11bfc30_0 .net "in", 7 0, L_0x13560b0; alias, 1 drivers -v0x11bfcf0_0 .net "out", 0 0, L_0x132a710; alias, 1 drivers -v0x11bfdc0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11ba950 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11ba730; +v0x2c99730_0 .net "ands", 7 0, L_0x2e1beb0; 1 drivers +v0x2c99840_0 .net "in", 7 0, L_0x2e16720; alias, 1 drivers +v0x2c99900_0 .net "out", 0 0, L_0x2e1deb0; alias, 1 drivers +v0x2c999d0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c94560 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c94340; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11bd080_0 .net "A", 7 0, L_0x13560b0; alias, 1 drivers -v0x11bd180_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11bd240_0 .net *"_s0", 0 0, L_0x1326f70; 1 drivers -v0x11bd300_0 .net *"_s12", 0 0, L_0x1327940; 1 drivers -v0x11bd3e0_0 .net *"_s16", 0 0, L_0x1327ca0; 1 drivers -v0x11bd510_0 .net *"_s20", 0 0, L_0x1327fe0; 1 drivers -v0x11bd5f0_0 .net *"_s24", 0 0, L_0x1328400; 1 drivers -v0x11bd6d0_0 .net *"_s28", 0 0, L_0x1328390; 1 drivers -v0x11bd7b0_0 .net *"_s4", 0 0, L_0x1327280; 1 drivers -v0x11bd920_0 .net *"_s8", 0 0, L_0x13275d0; 1 drivers -v0x11bda00_0 .net "out", 7 0, L_0x1328710; alias, 1 drivers -L_0x1327030 .part L_0x13560b0, 0, 1; -L_0x1327190 .part v0x12010b0_0, 0, 1; -L_0x1327340 .part L_0x13560b0, 1, 1; -L_0x1327530 .part v0x12010b0_0, 1, 1; -L_0x13276f0 .part L_0x13560b0, 2, 1; -L_0x1327850 .part v0x12010b0_0, 2, 1; -L_0x1327a00 .part L_0x13560b0, 3, 1; -L_0x1327b60 .part v0x12010b0_0, 3, 1; -L_0x1327d90 .part L_0x13560b0, 4, 1; -L_0x1327ef0 .part v0x12010b0_0, 4, 1; -L_0x1328080 .part L_0x13560b0, 5, 1; -L_0x13282f0 .part v0x12010b0_0, 5, 1; -L_0x13284c0 .part L_0x13560b0, 6, 1; -L_0x1328620 .part v0x12010b0_0, 6, 1; -LS_0x1328710_0_0 .concat8 [ 1 1 1 1], L_0x1326f70, L_0x1327280, L_0x13275d0, L_0x1327940; -LS_0x1328710_0_4 .concat8 [ 1 1 1 1], L_0x1327ca0, L_0x1327fe0, L_0x1328400, L_0x1328390; -L_0x1328710 .concat8 [ 4 4 0 0], LS_0x1328710_0_0, LS_0x1328710_0_4; -L_0x1328ad0 .part L_0x13560b0, 7, 1; -L_0x1328cc0 .part v0x12010b0_0, 7, 1; -S_0x11babb0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11badc0 .param/l "i" 0 4 54, +C4<00>; -L_0x1326f70/d .functor AND 1, L_0x1327030, L_0x1327190, C4<1>, C4<1>; -L_0x1326f70 .delay 1 (30000,30000,30000) L_0x1326f70/d; -v0x11baea0_0 .net *"_s0", 0 0, L_0x1327030; 1 drivers -v0x11baf80_0 .net *"_s1", 0 0, L_0x1327190; 1 drivers -S_0x11bb060 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bb270 .param/l "i" 0 4 54, +C4<01>; -L_0x1327280/d .functor AND 1, L_0x1327340, L_0x1327530, C4<1>, C4<1>; -L_0x1327280 .delay 1 (30000,30000,30000) L_0x1327280/d; -v0x11bb330_0 .net *"_s0", 0 0, L_0x1327340; 1 drivers -v0x11bb410_0 .net *"_s1", 0 0, L_0x1327530; 1 drivers -S_0x11bb4f0 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bb700 .param/l "i" 0 4 54, +C4<010>; -L_0x13275d0/d .functor AND 1, L_0x13276f0, L_0x1327850, C4<1>, C4<1>; -L_0x13275d0 .delay 1 (30000,30000,30000) L_0x13275d0/d; -v0x11bb7a0_0 .net *"_s0", 0 0, L_0x13276f0; 1 drivers -v0x11bb880_0 .net *"_s1", 0 0, L_0x1327850; 1 drivers -S_0x11bb960 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bbb70 .param/l "i" 0 4 54, +C4<011>; -L_0x1327940/d .functor AND 1, L_0x1327a00, L_0x1327b60, C4<1>, C4<1>; -L_0x1327940 .delay 1 (30000,30000,30000) L_0x1327940/d; -v0x11bbc30_0 .net *"_s0", 0 0, L_0x1327a00; 1 drivers -v0x11bbd10_0 .net *"_s1", 0 0, L_0x1327b60; 1 drivers -S_0x11bbdf0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bc050 .param/l "i" 0 4 54, +C4<0100>; -L_0x1327ca0/d .functor AND 1, L_0x1327d90, L_0x1327ef0, C4<1>, C4<1>; -L_0x1327ca0 .delay 1 (30000,30000,30000) L_0x1327ca0/d; -v0x11bc110_0 .net *"_s0", 0 0, L_0x1327d90; 1 drivers -v0x11bc1f0_0 .net *"_s1", 0 0, L_0x1327ef0; 1 drivers -S_0x11bc2d0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bc4e0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1327fe0/d .functor AND 1, L_0x1328080, L_0x13282f0, C4<1>, C4<1>; -L_0x1327fe0 .delay 1 (30000,30000,30000) L_0x1327fe0/d; -v0x11bc5a0_0 .net *"_s0", 0 0, L_0x1328080; 1 drivers -v0x11bc680_0 .net *"_s1", 0 0, L_0x13282f0; 1 drivers -S_0x11bc760 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bc970 .param/l "i" 0 4 54, +C4<0110>; -L_0x1328400/d .functor AND 1, L_0x13284c0, L_0x1328620, C4<1>, C4<1>; -L_0x1328400 .delay 1 (30000,30000,30000) L_0x1328400/d; -v0x11bca30_0 .net *"_s0", 0 0, L_0x13284c0; 1 drivers -v0x11bcb10_0 .net *"_s1", 0 0, L_0x1328620; 1 drivers -S_0x11bcbf0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11ba950; - .timescale -9 -12; -P_0x11bce00 .param/l "i" 0 4 54, +C4<0111>; -L_0x1328390/d .functor AND 1, L_0x1328ad0, L_0x1328cc0, C4<1>, C4<1>; -L_0x1328390 .delay 1 (30000,30000,30000) L_0x1328390/d; -v0x11bcec0_0 .net *"_s0", 0 0, L_0x1328ad0; 1 drivers -v0x11bcfa0_0 .net *"_s1", 0 0, L_0x1328cc0; 1 drivers -S_0x11bdb60 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11ba730; +v0x2c96c90_0 .net "A", 7 0, L_0x2e16720; alias, 1 drivers +v0x2c96d90_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c96e50_0 .net *"_s0", 0 0, L_0x2e1a7d0; 1 drivers +v0x2c96f10_0 .net *"_s12", 0 0, L_0x2e1b140; 1 drivers +v0x2c96ff0_0 .net *"_s16", 0 0, L_0x2e1b4a0; 1 drivers +v0x2c97120_0 .net *"_s20", 0 0, L_0x2e1b870; 1 drivers +v0x2c97200_0 .net *"_s24", 0 0, L_0x2e1bba0; 1 drivers +v0x2c972e0_0 .net *"_s28", 0 0, L_0x2e1bb30; 1 drivers +v0x2c973c0_0 .net *"_s4", 0 0, L_0x2e1ab20; 1 drivers +v0x2c97530_0 .net *"_s8", 0 0, L_0x2e1ae30; 1 drivers +v0x2c97610_0 .net "out", 7 0, L_0x2e1beb0; alias, 1 drivers +L_0x2e1a890 .part L_0x2e16720, 0, 1; +L_0x2e1aa80 .part v0x2cdd2e0_0, 0, 1; +L_0x2e1abe0 .part L_0x2e16720, 1, 1; +L_0x2e1ad40 .part v0x2cdd2e0_0, 1, 1; +L_0x2e1aef0 .part L_0x2e16720, 2, 1; +L_0x2e1b050 .part v0x2cdd2e0_0, 2, 1; +L_0x2e1b200 .part L_0x2e16720, 3, 1; +L_0x2e1b360 .part v0x2cdd2e0_0, 3, 1; +L_0x2e1b560 .part L_0x2e16720, 4, 1; +L_0x2e1b7d0 .part v0x2cdd2e0_0, 4, 1; +L_0x2e1b8e0 .part L_0x2e16720, 5, 1; +L_0x2e1ba40 .part v0x2cdd2e0_0, 5, 1; +L_0x2e1bc60 .part L_0x2e16720, 6, 1; +L_0x2e1bdc0 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e1beb0_0_0 .concat8 [ 1 1 1 1], L_0x2e1a7d0, L_0x2e1ab20, L_0x2e1ae30, L_0x2e1b140; +LS_0x2e1beb0_0_4 .concat8 [ 1 1 1 1], L_0x2e1b4a0, L_0x2e1b870, L_0x2e1bba0, L_0x2e1bb30; +L_0x2e1beb0 .concat8 [ 4 4 0 0], LS_0x2e1beb0_0_0, LS_0x2e1beb0_0_4; +L_0x2e1c270 .part L_0x2e16720, 7, 1; +L_0x2e1c460 .part v0x2cdd2e0_0, 7, 1; +S_0x2c947c0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c949d0 .param/l "i" 0 4 54, +C4<00>; +L_0x2e1a7d0/d .functor AND 1, L_0x2e1a890, L_0x2e1aa80, C4<1>, C4<1>; +L_0x2e1a7d0 .delay 1 (30000,30000,30000) L_0x2e1a7d0/d; +v0x2c94ab0_0 .net *"_s0", 0 0, L_0x2e1a890; 1 drivers +v0x2c94b90_0 .net *"_s1", 0 0, L_0x2e1aa80; 1 drivers +S_0x2c94c70 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c94e80 .param/l "i" 0 4 54, +C4<01>; +L_0x2e1ab20/d .functor AND 1, L_0x2e1abe0, L_0x2e1ad40, C4<1>, C4<1>; +L_0x2e1ab20 .delay 1 (30000,30000,30000) L_0x2e1ab20/d; +v0x2c94f40_0 .net *"_s0", 0 0, L_0x2e1abe0; 1 drivers +v0x2c95020_0 .net *"_s1", 0 0, L_0x2e1ad40; 1 drivers +S_0x2c95100 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c95310 .param/l "i" 0 4 54, +C4<010>; +L_0x2e1ae30/d .functor AND 1, L_0x2e1aef0, L_0x2e1b050, C4<1>, C4<1>; +L_0x2e1ae30 .delay 1 (30000,30000,30000) L_0x2e1ae30/d; +v0x2c953b0_0 .net *"_s0", 0 0, L_0x2e1aef0; 1 drivers +v0x2c95490_0 .net *"_s1", 0 0, L_0x2e1b050; 1 drivers +S_0x2c95570 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c95780 .param/l "i" 0 4 54, +C4<011>; +L_0x2e1b140/d .functor AND 1, L_0x2e1b200, L_0x2e1b360, C4<1>, C4<1>; +L_0x2e1b140 .delay 1 (30000,30000,30000) L_0x2e1b140/d; +v0x2c95840_0 .net *"_s0", 0 0, L_0x2e1b200; 1 drivers +v0x2c95920_0 .net *"_s1", 0 0, L_0x2e1b360; 1 drivers +S_0x2c95a00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c95c60 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e1b4a0/d .functor AND 1, L_0x2e1b560, L_0x2e1b7d0, C4<1>, C4<1>; +L_0x2e1b4a0 .delay 1 (30000,30000,30000) L_0x2e1b4a0/d; +v0x2c95d20_0 .net *"_s0", 0 0, L_0x2e1b560; 1 drivers +v0x2c95e00_0 .net *"_s1", 0 0, L_0x2e1b7d0; 1 drivers +S_0x2c95ee0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c960f0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e1b870/d .functor AND 1, L_0x2e1b8e0, L_0x2e1ba40, C4<1>, C4<1>; +L_0x2e1b870 .delay 1 (30000,30000,30000) L_0x2e1b870/d; +v0x2c961b0_0 .net *"_s0", 0 0, L_0x2e1b8e0; 1 drivers +v0x2c96290_0 .net *"_s1", 0 0, L_0x2e1ba40; 1 drivers +S_0x2c96370 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c96580 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e1bba0/d .functor AND 1, L_0x2e1bc60, L_0x2e1bdc0, C4<1>, C4<1>; +L_0x2e1bba0 .delay 1 (30000,30000,30000) L_0x2e1bba0/d; +v0x2c96640_0 .net *"_s0", 0 0, L_0x2e1bc60; 1 drivers +v0x2c96720_0 .net *"_s1", 0 0, L_0x2e1bdc0; 1 drivers +S_0x2c96800 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c94560; + .timescale -9 -12; +P_0x2c96a10 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e1bb30/d .functor AND 1, L_0x2e1c270, L_0x2e1c460, C4<1>, C4<1>; +L_0x2e1bb30 .delay 1 (30000,30000,30000) L_0x2e1bb30/d; +v0x2c96ad0_0 .net *"_s0", 0 0, L_0x2e1c270; 1 drivers +v0x2c96bb0_0 .net *"_s1", 0 0, L_0x2e1c460; 1 drivers +S_0x2c97770 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c94340; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x132a710/d .functor OR 1, L_0x132a7d0, L_0x132a980, C4<0>, C4<0>; -L_0x132a710 .delay 1 (30000,30000,30000) L_0x132a710/d; -v0x11bf6b0_0 .net *"_s10", 0 0, L_0x132a7d0; 1 drivers -v0x11bf790_0 .net *"_s12", 0 0, L_0x132a980; 1 drivers -v0x11bf870_0 .net "in", 7 0, L_0x1328710; alias, 1 drivers -v0x11bf940_0 .net "ors", 1 0, L_0x132a530; 1 drivers -v0x11bfa00_0 .net "out", 0 0, L_0x132a710; alias, 1 drivers -L_0x1329900 .part L_0x1328710, 0, 4; -L_0x132a530 .concat8 [ 1 1 0 0], L_0x13295f0, L_0x132a220; -L_0x132a670 .part L_0x1328710, 4, 4; -L_0x132a7d0 .part L_0x132a530, 0, 1; -L_0x132a980 .part L_0x132a530, 1, 1; -S_0x11bdd20 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11bdb60; +L_0x2e1deb0/d .functor OR 1, L_0x2e1df70, L_0x2e1e120, C4<0>, C4<0>; +L_0x2e1deb0 .delay 1 (30000,30000,30000) L_0x2e1deb0/d; +v0x2c992c0_0 .net *"_s10", 0 0, L_0x2e1df70; 1 drivers +v0x2c993a0_0 .net *"_s12", 0 0, L_0x2e1e120; 1 drivers +v0x2c99480_0 .net "in", 7 0, L_0x2e1beb0; alias, 1 drivers +v0x2c99550_0 .net "ors", 1 0, L_0x2e1dcd0; 1 drivers +v0x2c99610_0 .net "out", 0 0, L_0x2e1deb0; alias, 1 drivers +L_0x2e1d0a0 .part L_0x2e1beb0, 0, 4; +L_0x2e1dcd0 .concat8 [ 1 1 0 0], L_0x2e1cd90, L_0x2e1d9c0; +L_0x2e1de10 .part L_0x2e1beb0, 4, 4; +L_0x2e1df70 .part L_0x2e1dcd0, 0, 1; +L_0x2e1e120 .part L_0x2e1dcd0, 1, 1; +S_0x2c97930 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c97770; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1328db0/d .functor OR 1, L_0x1328e70, L_0x1328fd0, C4<0>, C4<0>; -L_0x1328db0 .delay 1 (30000,30000,30000) L_0x1328db0/d; -L_0x1329200/d .functor OR 1, L_0x1329310, L_0x1329470, C4<0>, C4<0>; -L_0x1329200 .delay 1 (30000,30000,30000) L_0x1329200/d; -L_0x13295f0/d .functor OR 1, L_0x1329660, L_0x1329810, C4<0>, C4<0>; -L_0x13295f0 .delay 1 (30000,30000,30000) L_0x13295f0/d; -v0x11bdf70_0 .net *"_s0", 0 0, L_0x1328db0; 1 drivers -v0x11be070_0 .net *"_s10", 0 0, L_0x1329310; 1 drivers -v0x11be150_0 .net *"_s12", 0 0, L_0x1329470; 1 drivers -v0x11be210_0 .net *"_s14", 0 0, L_0x1329660; 1 drivers -v0x11be2f0_0 .net *"_s16", 0 0, L_0x1329810; 1 drivers -v0x11be420_0 .net *"_s3", 0 0, L_0x1328e70; 1 drivers -v0x11be500_0 .net *"_s5", 0 0, L_0x1328fd0; 1 drivers -v0x11be5e0_0 .net *"_s6", 0 0, L_0x1329200; 1 drivers -v0x11be6c0_0 .net "in", 3 0, L_0x1329900; 1 drivers -v0x11be830_0 .net "ors", 1 0, L_0x1329110; 1 drivers -v0x11be910_0 .net "out", 0 0, L_0x13295f0; 1 drivers -L_0x1328e70 .part L_0x1329900, 0, 1; -L_0x1328fd0 .part L_0x1329900, 1, 1; -L_0x1329110 .concat8 [ 1 1 0 0], L_0x1328db0, L_0x1329200; -L_0x1329310 .part L_0x1329900, 2, 1; -L_0x1329470 .part L_0x1329900, 3, 1; -L_0x1329660 .part L_0x1329110, 0, 1; -L_0x1329810 .part L_0x1329110, 1, 1; -S_0x11bea30 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11bdb60; +L_0x2e1c550/d .functor OR 1, L_0x2e1c610, L_0x2e1c770, C4<0>, C4<0>; +L_0x2e1c550 .delay 1 (30000,30000,30000) L_0x2e1c550/d; +L_0x2e1c9a0/d .functor OR 1, L_0x2e1cab0, L_0x2e1cc10, C4<0>, C4<0>; +L_0x2e1c9a0 .delay 1 (30000,30000,30000) L_0x2e1c9a0/d; +L_0x2e1cd90/d .functor OR 1, L_0x2e1ce00, L_0x2e1cfb0, C4<0>, C4<0>; +L_0x2e1cd90 .delay 1 (30000,30000,30000) L_0x2e1cd90/d; +v0x2c97b80_0 .net *"_s0", 0 0, L_0x2e1c550; 1 drivers +v0x2c97c80_0 .net *"_s10", 0 0, L_0x2e1cab0; 1 drivers +v0x2c97d60_0 .net *"_s12", 0 0, L_0x2e1cc10; 1 drivers +v0x2c97e20_0 .net *"_s14", 0 0, L_0x2e1ce00; 1 drivers +v0x2c97f00_0 .net *"_s16", 0 0, L_0x2e1cfb0; 1 drivers +v0x2c98030_0 .net *"_s3", 0 0, L_0x2e1c610; 1 drivers +v0x2c98110_0 .net *"_s5", 0 0, L_0x2e1c770; 1 drivers +v0x2c981f0_0 .net *"_s6", 0 0, L_0x2e1c9a0; 1 drivers +v0x2c982d0_0 .net "in", 3 0, L_0x2e1d0a0; 1 drivers +v0x2c98440_0 .net "ors", 1 0, L_0x2e1c8b0; 1 drivers +v0x2c98520_0 .net "out", 0 0, L_0x2e1cd90; 1 drivers +L_0x2e1c610 .part L_0x2e1d0a0, 0, 1; +L_0x2e1c770 .part L_0x2e1d0a0, 1, 1; +L_0x2e1c8b0 .concat8 [ 1 1 0 0], L_0x2e1c550, L_0x2e1c9a0; +L_0x2e1cab0 .part L_0x2e1d0a0, 2, 1; +L_0x2e1cc10 .part L_0x2e1d0a0, 3, 1; +L_0x2e1ce00 .part L_0x2e1c8b0, 0, 1; +L_0x2e1cfb0 .part L_0x2e1c8b0, 1, 1; +S_0x2c98640 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c97770; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1329a30/d .functor OR 1, L_0x1329aa0, L_0x1329c00, C4<0>, C4<0>; -L_0x1329a30 .delay 1 (30000,30000,30000) L_0x1329a30/d; -L_0x1329e30/d .functor OR 1, L_0x1329f40, L_0x132a0a0, C4<0>, C4<0>; -L_0x1329e30 .delay 1 (30000,30000,30000) L_0x1329e30/d; -L_0x132a220/d .functor OR 1, L_0x132a290, L_0x132a440, C4<0>, C4<0>; -L_0x132a220 .delay 1 (30000,30000,30000) L_0x132a220/d; -v0x11bebf0_0 .net *"_s0", 0 0, L_0x1329a30; 1 drivers -v0x11becf0_0 .net *"_s10", 0 0, L_0x1329f40; 1 drivers -v0x11bedd0_0 .net *"_s12", 0 0, L_0x132a0a0; 1 drivers -v0x11bee90_0 .net *"_s14", 0 0, L_0x132a290; 1 drivers -v0x11bef70_0 .net *"_s16", 0 0, L_0x132a440; 1 drivers -v0x11bf0a0_0 .net *"_s3", 0 0, L_0x1329aa0; 1 drivers -v0x11bf180_0 .net *"_s5", 0 0, L_0x1329c00; 1 drivers -v0x11bf260_0 .net *"_s6", 0 0, L_0x1329e30; 1 drivers -v0x11bf340_0 .net "in", 3 0, L_0x132a670; 1 drivers -v0x11bf4b0_0 .net "ors", 1 0, L_0x1329d40; 1 drivers -v0x11bf590_0 .net "out", 0 0, L_0x132a220; 1 drivers -L_0x1329aa0 .part L_0x132a670, 0, 1; -L_0x1329c00 .part L_0x132a670, 1, 1; -L_0x1329d40 .concat8 [ 1 1 0 0], L_0x1329a30, L_0x1329e30; -L_0x1329f40 .part L_0x132a670, 2, 1; -L_0x132a0a0 .part L_0x132a670, 3, 1; -L_0x132a290 .part L_0x1329d40, 0, 1; -L_0x132a440 .part L_0x1329d40, 1, 1; -S_0x11bfea0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11b8fd0; +L_0x2e1d1d0/d .functor OR 1, L_0x2e1d240, L_0x2e1d3a0, C4<0>, C4<0>; +L_0x2e1d1d0 .delay 1 (30000,30000,30000) L_0x2e1d1d0/d; +L_0x2e1d5d0/d .functor OR 1, L_0x2e1d6e0, L_0x2e1d840, C4<0>, C4<0>; +L_0x2e1d5d0 .delay 1 (30000,30000,30000) L_0x2e1d5d0/d; +L_0x2e1d9c0/d .functor OR 1, L_0x2e1da30, L_0x2e1dbe0, C4<0>, C4<0>; +L_0x2e1d9c0 .delay 1 (30000,30000,30000) L_0x2e1d9c0/d; +v0x2c98800_0 .net *"_s0", 0 0, L_0x2e1d1d0; 1 drivers +v0x2c98900_0 .net *"_s10", 0 0, L_0x2e1d6e0; 1 drivers +v0x2c989e0_0 .net *"_s12", 0 0, L_0x2e1d840; 1 drivers +v0x2c98aa0_0 .net *"_s14", 0 0, L_0x2e1da30; 1 drivers +v0x2c98b80_0 .net *"_s16", 0 0, L_0x2e1dbe0; 1 drivers +v0x2c98cb0_0 .net *"_s3", 0 0, L_0x2e1d240; 1 drivers +v0x2c98d90_0 .net *"_s5", 0 0, L_0x2e1d3a0; 1 drivers +v0x2c98e70_0 .net *"_s6", 0 0, L_0x2e1d5d0; 1 drivers +v0x2c98f50_0 .net "in", 3 0, L_0x2e1de10; 1 drivers +v0x2c990c0_0 .net "ors", 1 0, L_0x2e1d4e0; 1 drivers +v0x2c991a0_0 .net "out", 0 0, L_0x2e1d9c0; 1 drivers +L_0x2e1d240 .part L_0x2e1de10, 0, 1; +L_0x2e1d3a0 .part L_0x2e1de10, 1, 1; +L_0x2e1d4e0 .concat8 [ 1 1 0 0], L_0x2e1d1d0, L_0x2e1d5d0; +L_0x2e1d6e0 .part L_0x2e1de10, 2, 1; +L_0x2e1d840 .part L_0x2e1de10, 3, 1; +L_0x2e1da30 .part L_0x2e1d4e0, 0, 1; +L_0x2e1dbe0 .part L_0x2e1d4e0, 1, 1; +S_0x2c99ab0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2c92be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11c52d0_0 .net "ands", 7 0, L_0x1324be0; 1 drivers -v0x11c53e0_0 .net "in", 7 0, L_0x1323040; alias, 1 drivers -v0x11c54a0_0 .net "out", 0 0, L_0x1326c10; alias, 1 drivers -v0x11c5570_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11c00f0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11bfea0; +v0x2c9eee0_0 .net "ands", 7 0, L_0x2e18470; 1 drivers +v0x2c9eff0_0 .net "in", 7 0, L_0x2e163e0; alias, 1 drivers +v0x2c9f0b0_0 .net "out", 0 0, L_0x2e1a470; alias, 1 drivers +v0x2c9f180_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2c99d00 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2c99ab0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11c2830_0 .net "A", 7 0, L_0x1323040; alias, 1 drivers -v0x11c2930_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11c29f0_0 .net *"_s0", 0 0, L_0x13233d0; 1 drivers -v0x11c2ab0_0 .net *"_s12", 0 0, L_0x1323d90; 1 drivers -v0x11c2b90_0 .net *"_s16", 0 0, L_0x13240f0; 1 drivers -v0x11c2cc0_0 .net *"_s20", 0 0, L_0x1324520; 1 drivers -v0x11c2da0_0 .net *"_s24", 0 0, L_0x1324850; 1 drivers -v0x11c2e80_0 .net *"_s28", 0 0, L_0x13247e0; 1 drivers -v0x11c2f60_0 .net *"_s4", 0 0, L_0x1323770; 1 drivers -v0x11c30d0_0 .net *"_s8", 0 0, L_0x1323a80; 1 drivers -v0x11c31b0_0 .net "out", 7 0, L_0x1324be0; alias, 1 drivers -L_0x13234e0 .part L_0x1323040, 0, 1; -L_0x13236d0 .part v0x12010b0_0, 0, 1; -L_0x1323830 .part L_0x1323040, 1, 1; -L_0x1323990 .part v0x12010b0_0, 1, 1; -L_0x1323b40 .part L_0x1323040, 2, 1; -L_0x1323ca0 .part v0x12010b0_0, 2, 1; -L_0x1323e50 .part L_0x1323040, 3, 1; -L_0x1323fb0 .part v0x12010b0_0, 3, 1; -L_0x13241b0 .part L_0x1323040, 4, 1; -L_0x1324420 .part v0x12010b0_0, 4, 1; -L_0x1324590 .part L_0x1323040, 5, 1; -L_0x13246f0 .part v0x12010b0_0, 5, 1; -L_0x1324910 .part L_0x1323040, 6, 1; -L_0x1324a70 .part v0x12010b0_0, 6, 1; -LS_0x1324be0_0_0 .concat8 [ 1 1 1 1], L_0x13233d0, L_0x1323770, L_0x1323a80, L_0x1323d90; -LS_0x1324be0_0_4 .concat8 [ 1 1 1 1], L_0x13240f0, L_0x1324520, L_0x1324850, L_0x13247e0; -L_0x1324be0 .concat8 [ 4 4 0 0], LS_0x1324be0_0_0, LS_0x1324be0_0_4; -L_0x1324fa0 .part L_0x1323040, 7, 1; -L_0x1325190 .part v0x12010b0_0, 7, 1; -S_0x11c0330 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c0540 .param/l "i" 0 4 54, +C4<00>; -L_0x13233d0/d .functor AND 1, L_0x13234e0, L_0x13236d0, C4<1>, C4<1>; -L_0x13233d0 .delay 1 (30000,30000,30000) L_0x13233d0/d; -v0x11c0620_0 .net *"_s0", 0 0, L_0x13234e0; 1 drivers -v0x11c0700_0 .net *"_s1", 0 0, L_0x13236d0; 1 drivers -S_0x11c07e0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c09f0 .param/l "i" 0 4 54, +C4<01>; -L_0x1323770/d .functor AND 1, L_0x1323830, L_0x1323990, C4<1>, C4<1>; -L_0x1323770 .delay 1 (30000,30000,30000) L_0x1323770/d; -v0x11c0ab0_0 .net *"_s0", 0 0, L_0x1323830; 1 drivers -v0x11c0b90_0 .net *"_s1", 0 0, L_0x1323990; 1 drivers -S_0x11c0c70 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c0eb0 .param/l "i" 0 4 54, +C4<010>; -L_0x1323a80/d .functor AND 1, L_0x1323b40, L_0x1323ca0, C4<1>, C4<1>; -L_0x1323a80 .delay 1 (30000,30000,30000) L_0x1323a80/d; -v0x11c0f50_0 .net *"_s0", 0 0, L_0x1323b40; 1 drivers -v0x11c1030_0 .net *"_s1", 0 0, L_0x1323ca0; 1 drivers -S_0x11c1110 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c1320 .param/l "i" 0 4 54, +C4<011>; -L_0x1323d90/d .functor AND 1, L_0x1323e50, L_0x1323fb0, C4<1>, C4<1>; -L_0x1323d90 .delay 1 (30000,30000,30000) L_0x1323d90/d; -v0x11c13e0_0 .net *"_s0", 0 0, L_0x1323e50; 1 drivers -v0x11c14c0_0 .net *"_s1", 0 0, L_0x1323fb0; 1 drivers -S_0x11c15a0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c1800 .param/l "i" 0 4 54, +C4<0100>; -L_0x13240f0/d .functor AND 1, L_0x13241b0, L_0x1324420, C4<1>, C4<1>; -L_0x13240f0 .delay 1 (30000,30000,30000) L_0x13240f0/d; -v0x11c18c0_0 .net *"_s0", 0 0, L_0x13241b0; 1 drivers -v0x11c19a0_0 .net *"_s1", 0 0, L_0x1324420; 1 drivers -S_0x11c1a80 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c1c90 .param/l "i" 0 4 54, +C4<0101>; -L_0x1324520/d .functor AND 1, L_0x1324590, L_0x13246f0, C4<1>, C4<1>; -L_0x1324520 .delay 1 (30000,30000,30000) L_0x1324520/d; -v0x11c1d50_0 .net *"_s0", 0 0, L_0x1324590; 1 drivers -v0x11c1e30_0 .net *"_s1", 0 0, L_0x13246f0; 1 drivers -S_0x11c1f10 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c2120 .param/l "i" 0 4 54, +C4<0110>; -L_0x1324850/d .functor AND 1, L_0x1324910, L_0x1324a70, C4<1>, C4<1>; -L_0x1324850 .delay 1 (30000,30000,30000) L_0x1324850/d; -v0x11c21e0_0 .net *"_s0", 0 0, L_0x1324910; 1 drivers -v0x11c22c0_0 .net *"_s1", 0 0, L_0x1324a70; 1 drivers -S_0x11c23a0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11c00f0; - .timescale -9 -12; -P_0x11c25b0 .param/l "i" 0 4 54, +C4<0111>; -L_0x13247e0/d .functor AND 1, L_0x1324fa0, L_0x1325190, C4<1>, C4<1>; -L_0x13247e0 .delay 1 (30000,30000,30000) L_0x13247e0/d; -v0x11c2670_0 .net *"_s0", 0 0, L_0x1324fa0; 1 drivers -v0x11c2750_0 .net *"_s1", 0 0, L_0x1325190; 1 drivers -S_0x11c3310 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11bfea0; +v0x2c9c440_0 .net "A", 7 0, L_0x2e163e0; alias, 1 drivers +v0x2c9c540_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2c9c600_0 .net *"_s0", 0 0, L_0x2e16c60; 1 drivers +v0x2c9c6c0_0 .net *"_s12", 0 0, L_0x2e17620; 1 drivers +v0x2c9c7a0_0 .net *"_s16", 0 0, L_0x2e17980; 1 drivers +v0x2c9c8d0_0 .net *"_s20", 0 0, L_0x2e17db0; 1 drivers +v0x2c9c9b0_0 .net *"_s24", 0 0, L_0x2e180e0; 1 drivers +v0x2c9ca90_0 .net *"_s28", 0 0, L_0x2e18070; 1 drivers +v0x2c9cb70_0 .net *"_s4", 0 0, L_0x2e17000; 1 drivers +v0x2c9cce0_0 .net *"_s8", 0 0, L_0x2e17310; 1 drivers +v0x2c9cdc0_0 .net "out", 7 0, L_0x2e18470; alias, 1 drivers +L_0x2e16d70 .part L_0x2e163e0, 0, 1; +L_0x2e16f60 .part v0x2cdd2e0_0, 0, 1; +L_0x2e170c0 .part L_0x2e163e0, 1, 1; +L_0x2e17220 .part v0x2cdd2e0_0, 1, 1; +L_0x2e173d0 .part L_0x2e163e0, 2, 1; +L_0x2e17530 .part v0x2cdd2e0_0, 2, 1; +L_0x2e176e0 .part L_0x2e163e0, 3, 1; +L_0x2e17840 .part v0x2cdd2e0_0, 3, 1; +L_0x2e17a40 .part L_0x2e163e0, 4, 1; +L_0x2e17cb0 .part v0x2cdd2e0_0, 4, 1; +L_0x2e17e20 .part L_0x2e163e0, 5, 1; +L_0x2e17f80 .part v0x2cdd2e0_0, 5, 1; +L_0x2e181a0 .part L_0x2e163e0, 6, 1; +L_0x2e18300 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e18470_0_0 .concat8 [ 1 1 1 1], L_0x2e16c60, L_0x2e17000, L_0x2e17310, L_0x2e17620; +LS_0x2e18470_0_4 .concat8 [ 1 1 1 1], L_0x2e17980, L_0x2e17db0, L_0x2e180e0, L_0x2e18070; +L_0x2e18470 .concat8 [ 4 4 0 0], LS_0x2e18470_0_0, LS_0x2e18470_0_4; +L_0x2e18830 .part L_0x2e163e0, 7, 1; +L_0x2e18a20 .part v0x2cdd2e0_0, 7, 1; +S_0x2c99f40 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9a150 .param/l "i" 0 4 54, +C4<00>; +L_0x2e16c60/d .functor AND 1, L_0x2e16d70, L_0x2e16f60, C4<1>, C4<1>; +L_0x2e16c60 .delay 1 (30000,30000,30000) L_0x2e16c60/d; +v0x2c9a230_0 .net *"_s0", 0 0, L_0x2e16d70; 1 drivers +v0x2c9a310_0 .net *"_s1", 0 0, L_0x2e16f60; 1 drivers +S_0x2c9a3f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9a600 .param/l "i" 0 4 54, +C4<01>; +L_0x2e17000/d .functor AND 1, L_0x2e170c0, L_0x2e17220, C4<1>, C4<1>; +L_0x2e17000 .delay 1 (30000,30000,30000) L_0x2e17000/d; +v0x2c9a6c0_0 .net *"_s0", 0 0, L_0x2e170c0; 1 drivers +v0x2c9a7a0_0 .net *"_s1", 0 0, L_0x2e17220; 1 drivers +S_0x2c9a880 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9aac0 .param/l "i" 0 4 54, +C4<010>; +L_0x2e17310/d .functor AND 1, L_0x2e173d0, L_0x2e17530, C4<1>, C4<1>; +L_0x2e17310 .delay 1 (30000,30000,30000) L_0x2e17310/d; +v0x2c9ab60_0 .net *"_s0", 0 0, L_0x2e173d0; 1 drivers +v0x2c9ac40_0 .net *"_s1", 0 0, L_0x2e17530; 1 drivers +S_0x2c9ad20 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9af30 .param/l "i" 0 4 54, +C4<011>; +L_0x2e17620/d .functor AND 1, L_0x2e176e0, L_0x2e17840, C4<1>, C4<1>; +L_0x2e17620 .delay 1 (30000,30000,30000) L_0x2e17620/d; +v0x2c9aff0_0 .net *"_s0", 0 0, L_0x2e176e0; 1 drivers +v0x2c9b0d0_0 .net *"_s1", 0 0, L_0x2e17840; 1 drivers +S_0x2c9b1b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9b410 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e17980/d .functor AND 1, L_0x2e17a40, L_0x2e17cb0, C4<1>, C4<1>; +L_0x2e17980 .delay 1 (30000,30000,30000) L_0x2e17980/d; +v0x2c9b4d0_0 .net *"_s0", 0 0, L_0x2e17a40; 1 drivers +v0x2c9b5b0_0 .net *"_s1", 0 0, L_0x2e17cb0; 1 drivers +S_0x2c9b690 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9b8a0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e17db0/d .functor AND 1, L_0x2e17e20, L_0x2e17f80, C4<1>, C4<1>; +L_0x2e17db0 .delay 1 (30000,30000,30000) L_0x2e17db0/d; +v0x2c9b960_0 .net *"_s0", 0 0, L_0x2e17e20; 1 drivers +v0x2c9ba40_0 .net *"_s1", 0 0, L_0x2e17f80; 1 drivers +S_0x2c9bb20 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9bd30 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e180e0/d .functor AND 1, L_0x2e181a0, L_0x2e18300, C4<1>, C4<1>; +L_0x2e180e0 .delay 1 (30000,30000,30000) L_0x2e180e0/d; +v0x2c9bdf0_0 .net *"_s0", 0 0, L_0x2e181a0; 1 drivers +v0x2c9bed0_0 .net *"_s1", 0 0, L_0x2e18300; 1 drivers +S_0x2c9bfb0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2c99d00; + .timescale -9 -12; +P_0x2c9c1c0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e18070/d .functor AND 1, L_0x2e18830, L_0x2e18a20, C4<1>, C4<1>; +L_0x2e18070 .delay 1 (30000,30000,30000) L_0x2e18070/d; +v0x2c9c280_0 .net *"_s0", 0 0, L_0x2e18830; 1 drivers +v0x2c9c360_0 .net *"_s1", 0 0, L_0x2e18a20; 1 drivers +S_0x2c9cf20 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2c99ab0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1326c10/d .functor OR 1, L_0x1326cd0, L_0x1326e80, C4<0>, C4<0>; -L_0x1326c10 .delay 1 (30000,30000,30000) L_0x1326c10/d; -v0x11c4e60_0 .net *"_s10", 0 0, L_0x1326cd0; 1 drivers -v0x11c4f40_0 .net *"_s12", 0 0, L_0x1326e80; 1 drivers -v0x11c5020_0 .net "in", 7 0, L_0x1324be0; alias, 1 drivers -v0x11c50f0_0 .net "ors", 1 0, L_0x1326a30; 1 drivers -v0x11c51b0_0 .net "out", 0 0, L_0x1326c10; alias, 1 drivers -L_0x1325dd0 .part L_0x1324be0, 0, 4; -L_0x1326a30 .concat8 [ 1 1 0 0], L_0x1325ac0, L_0x13266f0; -L_0x1326b70 .part L_0x1324be0, 4, 4; -L_0x1326cd0 .part L_0x1326a30, 0, 1; -L_0x1326e80 .part L_0x1326a30, 1, 1; -S_0x11c34d0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11c3310; +L_0x2e1a470/d .functor OR 1, L_0x2e1a530, L_0x2e1a6e0, C4<0>, C4<0>; +L_0x2e1a470 .delay 1 (30000,30000,30000) L_0x2e1a470/d; +v0x2c9ea70_0 .net *"_s10", 0 0, L_0x2e1a530; 1 drivers +v0x2c9eb50_0 .net *"_s12", 0 0, L_0x2e1a6e0; 1 drivers +v0x2c9ec30_0 .net "in", 7 0, L_0x2e18470; alias, 1 drivers +v0x2c9ed00_0 .net "ors", 1 0, L_0x2e1a290; 1 drivers +v0x2c9edc0_0 .net "out", 0 0, L_0x2e1a470; alias, 1 drivers +L_0x2e19660 .part L_0x2e18470, 0, 4; +L_0x2e1a290 .concat8 [ 1 1 0 0], L_0x2e19350, L_0x2e19f80; +L_0x2e1a3d0 .part L_0x2e18470, 4, 4; +L_0x2e1a530 .part L_0x2e1a290, 0, 1; +L_0x2e1a6e0 .part L_0x2e1a290, 1, 1; +S_0x2c9d0e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2c9cf20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1325280/d .functor OR 1, L_0x1325340, L_0x13254a0, C4<0>, C4<0>; -L_0x1325280 .delay 1 (30000,30000,30000) L_0x1325280/d; -L_0x13256d0/d .functor OR 1, L_0x13257e0, L_0x1325940, C4<0>, C4<0>; -L_0x13256d0 .delay 1 (30000,30000,30000) L_0x13256d0/d; -L_0x1325ac0/d .functor OR 1, L_0x1325b30, L_0x1325ce0, C4<0>, C4<0>; -L_0x1325ac0 .delay 1 (30000,30000,30000) L_0x1325ac0/d; -v0x11c3720_0 .net *"_s0", 0 0, L_0x1325280; 1 drivers -v0x11c3820_0 .net *"_s10", 0 0, L_0x13257e0; 1 drivers -v0x11c3900_0 .net *"_s12", 0 0, L_0x1325940; 1 drivers -v0x11c39c0_0 .net *"_s14", 0 0, L_0x1325b30; 1 drivers -v0x11c3aa0_0 .net *"_s16", 0 0, L_0x1325ce0; 1 drivers -v0x11c3bd0_0 .net *"_s3", 0 0, L_0x1325340; 1 drivers -v0x11c3cb0_0 .net *"_s5", 0 0, L_0x13254a0; 1 drivers -v0x11c3d90_0 .net *"_s6", 0 0, L_0x13256d0; 1 drivers -v0x11c3e70_0 .net "in", 3 0, L_0x1325dd0; 1 drivers -v0x11c3fe0_0 .net "ors", 1 0, L_0x13255e0; 1 drivers -v0x11c40c0_0 .net "out", 0 0, L_0x1325ac0; 1 drivers -L_0x1325340 .part L_0x1325dd0, 0, 1; -L_0x13254a0 .part L_0x1325dd0, 1, 1; -L_0x13255e0 .concat8 [ 1 1 0 0], L_0x1325280, L_0x13256d0; -L_0x13257e0 .part L_0x1325dd0, 2, 1; -L_0x1325940 .part L_0x1325dd0, 3, 1; -L_0x1325b30 .part L_0x13255e0, 0, 1; -L_0x1325ce0 .part L_0x13255e0, 1, 1; -S_0x11c41e0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11c3310; +L_0x2e18b10/d .functor OR 1, L_0x2e18bd0, L_0x2e18d30, C4<0>, C4<0>; +L_0x2e18b10 .delay 1 (30000,30000,30000) L_0x2e18b10/d; +L_0x2e18f60/d .functor OR 1, L_0x2e19070, L_0x2e191d0, C4<0>, C4<0>; +L_0x2e18f60 .delay 1 (30000,30000,30000) L_0x2e18f60/d; +L_0x2e19350/d .functor OR 1, L_0x2e193c0, L_0x2e19570, C4<0>, C4<0>; +L_0x2e19350 .delay 1 (30000,30000,30000) L_0x2e19350/d; +v0x2c9d330_0 .net *"_s0", 0 0, L_0x2e18b10; 1 drivers +v0x2c9d430_0 .net *"_s10", 0 0, L_0x2e19070; 1 drivers +v0x2c9d510_0 .net *"_s12", 0 0, L_0x2e191d0; 1 drivers +v0x2c9d5d0_0 .net *"_s14", 0 0, L_0x2e193c0; 1 drivers +v0x2c9d6b0_0 .net *"_s16", 0 0, L_0x2e19570; 1 drivers +v0x2c9d7e0_0 .net *"_s3", 0 0, L_0x2e18bd0; 1 drivers +v0x2c9d8c0_0 .net *"_s5", 0 0, L_0x2e18d30; 1 drivers +v0x2c9d9a0_0 .net *"_s6", 0 0, L_0x2e18f60; 1 drivers +v0x2c9da80_0 .net "in", 3 0, L_0x2e19660; 1 drivers +v0x2c9dbf0_0 .net "ors", 1 0, L_0x2e18e70; 1 drivers +v0x2c9dcd0_0 .net "out", 0 0, L_0x2e19350; 1 drivers +L_0x2e18bd0 .part L_0x2e19660, 0, 1; +L_0x2e18d30 .part L_0x2e19660, 1, 1; +L_0x2e18e70 .concat8 [ 1 1 0 0], L_0x2e18b10, L_0x2e18f60; +L_0x2e19070 .part L_0x2e19660, 2, 1; +L_0x2e191d0 .part L_0x2e19660, 3, 1; +L_0x2e193c0 .part L_0x2e18e70, 0, 1; +L_0x2e19570 .part L_0x2e18e70, 1, 1; +S_0x2c9ddf0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2c9cf20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1325f00/d .functor OR 1, L_0x1325f70, L_0x13260d0, C4<0>, C4<0>; -L_0x1325f00 .delay 1 (30000,30000,30000) L_0x1325f00/d; -L_0x1326300/d .functor OR 1, L_0x1326410, L_0x1326570, C4<0>, C4<0>; -L_0x1326300 .delay 1 (30000,30000,30000) L_0x1326300/d; -L_0x13266f0/d .functor OR 1, L_0x1326790, L_0x1326940, C4<0>, C4<0>; -L_0x13266f0 .delay 1 (30000,30000,30000) L_0x13266f0/d; -v0x11c43a0_0 .net *"_s0", 0 0, L_0x1325f00; 1 drivers -v0x11c44a0_0 .net *"_s10", 0 0, L_0x1326410; 1 drivers -v0x11c4580_0 .net *"_s12", 0 0, L_0x1326570; 1 drivers -v0x11c4640_0 .net *"_s14", 0 0, L_0x1326790; 1 drivers -v0x11c4720_0 .net *"_s16", 0 0, L_0x1326940; 1 drivers -v0x11c4850_0 .net *"_s3", 0 0, L_0x1325f70; 1 drivers -v0x11c4930_0 .net *"_s5", 0 0, L_0x13260d0; 1 drivers -v0x11c4a10_0 .net *"_s6", 0 0, L_0x1326300; 1 drivers -v0x11c4af0_0 .net "in", 3 0, L_0x1326b70; 1 drivers -v0x11c4c60_0 .net "ors", 1 0, L_0x1326210; 1 drivers -v0x11c4d40_0 .net "out", 0 0, L_0x13266f0; 1 drivers -L_0x1325f70 .part L_0x1326b70, 0, 1; -L_0x13260d0 .part L_0x1326b70, 1, 1; -L_0x1326210 .concat8 [ 1 1 0 0], L_0x1325f00, L_0x1326300; -L_0x1326410 .part L_0x1326b70, 2, 1; -L_0x1326570 .part L_0x1326b70, 3, 1; -L_0x1326790 .part L_0x1326210, 0, 1; -L_0x1326940 .part L_0x1326210, 1, 1; -S_0x11c5650 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11b8fd0; +L_0x2e19790/d .functor OR 1, L_0x2e19800, L_0x2e19960, C4<0>, C4<0>; +L_0x2e19790 .delay 1 (30000,30000,30000) L_0x2e19790/d; +L_0x2e19b90/d .functor OR 1, L_0x2e19ca0, L_0x2e19e00, C4<0>, C4<0>; +L_0x2e19b90 .delay 1 (30000,30000,30000) L_0x2e19b90/d; +L_0x2e19f80/d .functor OR 1, L_0x2e19ff0, L_0x2e1a1a0, C4<0>, C4<0>; +L_0x2e19f80 .delay 1 (30000,30000,30000) L_0x2e19f80/d; +v0x2c9dfb0_0 .net *"_s0", 0 0, L_0x2e19790; 1 drivers +v0x2c9e0b0_0 .net *"_s10", 0 0, L_0x2e19ca0; 1 drivers +v0x2c9e190_0 .net *"_s12", 0 0, L_0x2e19e00; 1 drivers +v0x2c9e250_0 .net *"_s14", 0 0, L_0x2e19ff0; 1 drivers +v0x2c9e330_0 .net *"_s16", 0 0, L_0x2e1a1a0; 1 drivers +v0x2c9e460_0 .net *"_s3", 0 0, L_0x2e19800; 1 drivers +v0x2c9e540_0 .net *"_s5", 0 0, L_0x2e19960; 1 drivers +v0x2c9e620_0 .net *"_s6", 0 0, L_0x2e19b90; 1 drivers +v0x2c9e700_0 .net "in", 3 0, L_0x2e1a3d0; 1 drivers +v0x2c9e870_0 .net "ors", 1 0, L_0x2e19aa0; 1 drivers +v0x2c9e950_0 .net "out", 0 0, L_0x2e19f80; 1 drivers +L_0x2e19800 .part L_0x2e1a3d0, 0, 1; +L_0x2e19960 .part L_0x2e1a3d0, 1, 1; +L_0x2e19aa0 .concat8 [ 1 1 0 0], L_0x2e19790, L_0x2e19b90; +L_0x2e19ca0 .part L_0x2e1a3d0, 2, 1; +L_0x2e19e00 .part L_0x2e1a3d0, 3, 1; +L_0x2e19ff0 .part L_0x2e19aa0, 0, 1; +L_0x2e1a1a0 .part L_0x2e19aa0, 1, 1; +S_0x2c9f260 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2c92be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -16022,80 +16954,80 @@ S_0x11c5650 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11b8fd0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1322360/d .functor XNOR 1, L_0x132ab70, L_0x13210a0, C4<0>, C4<0>; -L_0x1322360 .delay 1 (20000,20000,20000) L_0x1322360/d; -L_0x13225d0/d .functor AND 1, L_0x132ab70, L_0x13213b0, C4<1>, C4<1>; -L_0x13225d0 .delay 1 (30000,30000,30000) L_0x13225d0/d; -L_0x1322640/d .functor AND 1, L_0x1322360, L_0x1321140, C4<1>, C4<1>; -L_0x1322640 .delay 1 (30000,30000,30000) L_0x1322640/d; -L_0x13227a0/d .functor OR 1, L_0x1322640, L_0x13225d0, C4<0>, C4<0>; -L_0x13227a0 .delay 1 (30000,30000,30000) L_0x13227a0/d; -v0x11c5900_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers -v0x11c59f0_0 .net "a_", 0 0, L_0x1317400; alias, 1 drivers -v0x11c5ab0_0 .net "b", 0 0, L_0x13210a0; alias, 1 drivers -v0x11c5ba0_0 .net "b_", 0 0, L_0x13213b0; alias, 1 drivers -v0x11c5c40_0 .net "carryin", 0 0, L_0x1321140; alias, 1 drivers -v0x11c5d80_0 .net "eq", 0 0, L_0x1322360; 1 drivers -v0x11c5e40_0 .net "lt", 0 0, L_0x13225d0; 1 drivers -v0x11c5f00_0 .net "out", 0 0, L_0x13227a0; 1 drivers -v0x11c5fc0_0 .net "w0", 0 0, L_0x1322640; 1 drivers -S_0x11c6210 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11b8fd0; +L_0x2e15220/d .functor XNOR 1, L_0x2e1e310, L_0x2e13cf0, C4<0>, C4<0>; +L_0x2e15220 .delay 1 (20000,20000,20000) L_0x2e15220/d; +L_0x2e153a0/d .functor AND 1, L_0x2e1e310, L_0x2e13fb0, C4<1>, C4<1>; +L_0x2e153a0 .delay 1 (30000,30000,30000) L_0x2e153a0/d; +L_0x2e15500/d .functor AND 1, L_0x2e15220, L_0x2e13d90, C4<1>, C4<1>; +L_0x2e15500 .delay 1 (30000,30000,30000) L_0x2e15500/d; +L_0x2e15610/d .functor OR 1, L_0x2e15500, L_0x2e153a0, C4<0>, C4<0>; +L_0x2e15610 .delay 1 (30000,30000,30000) L_0x2e15610/d; +v0x2c9f510_0 .net "a", 0 0, L_0x2e1e310; alias, 1 drivers +v0x2c9f600_0 .net "a_", 0 0, L_0x2e09530; alias, 1 drivers +v0x2c9f6c0_0 .net "b", 0 0, L_0x2e13cf0; alias, 1 drivers +v0x2c9f7b0_0 .net "b_", 0 0, L_0x2e13fb0; alias, 1 drivers +v0x2c9f850_0 .net "carryin", 0 0, L_0x2e13d90; alias, 1 drivers +v0x2c9f990_0 .net "eq", 0 0, L_0x2e15220; 1 drivers +v0x2c9fa50_0 .net "lt", 0 0, L_0x2e153a0; 1 drivers +v0x2c9fb10_0 .net "out", 0 0, L_0x2e15610; 1 drivers +v0x2c9fbd0_0 .net "w0", 0 0, L_0x2e15500; 1 drivers +S_0x2c9fe20 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2c92be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1322140/d .functor OR 1, L_0x1321c90, L_0x11c7470, C4<0>, C4<0>; -L_0x1322140 .delay 1 (30000,30000,30000) L_0x1322140/d; -v0x11c7000_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers -v0x11c7150_0 .net "b", 0 0, L_0x13213b0; alias, 1 drivers -v0x11c7210_0 .net "c1", 0 0, L_0x1321c90; 1 drivers -v0x11c72b0_0 .net "c2", 0 0, L_0x11c7470; 1 drivers -v0x11c7380_0 .net "carryin", 0 0, L_0x1321140; alias, 1 drivers -v0x11c7500_0 .net "carryout", 0 0, L_0x1322140; 1 drivers -v0x11c75a0_0 .net "s1", 0 0, L_0x1321bd0; 1 drivers -v0x11c7640_0 .net "sum", 0 0, L_0x1321df0; 1 drivers -S_0x11c6460 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11c6210; +L_0x2e14e00/d .functor OR 1, L_0x2e14950, L_0x2ca1080, C4<0>, C4<0>; +L_0x2e14e00 .delay 1 (30000,30000,30000) L_0x2e14e00/d; +v0x2ca0c10_0 .net "a", 0 0, L_0x2e1e310; alias, 1 drivers +v0x2ca0d60_0 .net "b", 0 0, L_0x2e13fb0; alias, 1 drivers +v0x2ca0e20_0 .net "c1", 0 0, L_0x2e14950; 1 drivers +v0x2ca0ec0_0 .net "c2", 0 0, L_0x2ca1080; 1 drivers +v0x2ca0f90_0 .net "carryin", 0 0, L_0x2e13d90; alias, 1 drivers +v0x2ca1110_0 .net "carryout", 0 0, L_0x2e14e00; 1 drivers +v0x2ca11b0_0 .net "s1", 0 0, L_0x2e14890; 1 drivers +v0x2ca1250_0 .net "sum", 0 0, L_0x2e14ab0; 1 drivers +S_0x2ca0070 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2c9fe20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1321bd0/d .functor XOR 1, L_0x132ab70, L_0x13213b0, C4<0>, C4<0>; -L_0x1321bd0 .delay 1 (30000,30000,30000) L_0x1321bd0/d; -L_0x1321c90/d .functor AND 1, L_0x132ab70, L_0x13213b0, C4<1>, C4<1>; -L_0x1321c90 .delay 1 (30000,30000,30000) L_0x1321c90/d; -v0x11c66c0_0 .net "a", 0 0, L_0x132ab70; alias, 1 drivers -v0x11c6780_0 .net "b", 0 0, L_0x13213b0; alias, 1 drivers -v0x11c6840_0 .net "carryout", 0 0, L_0x1321c90; alias, 1 drivers -v0x11c68e0_0 .net "sum", 0 0, L_0x1321bd0; alias, 1 drivers -S_0x11c6a10 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11c6210; +L_0x2e14890/d .functor XOR 1, L_0x2e1e310, L_0x2e13fb0, C4<0>, C4<0>; +L_0x2e14890 .delay 1 (30000,30000,30000) L_0x2e14890/d; +L_0x2e14950/d .functor AND 1, L_0x2e1e310, L_0x2e13fb0, C4<1>, C4<1>; +L_0x2e14950 .delay 1 (30000,30000,30000) L_0x2e14950/d; +v0x2ca02d0_0 .net "a", 0 0, L_0x2e1e310; alias, 1 drivers +v0x2ca0390_0 .net "b", 0 0, L_0x2e13fb0; alias, 1 drivers +v0x2ca0450_0 .net "carryout", 0 0, L_0x2e14950; alias, 1 drivers +v0x2ca04f0_0 .net "sum", 0 0, L_0x2e14890; alias, 1 drivers +S_0x2ca0620 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2c9fe20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1321df0/d .functor XOR 1, L_0x1321bd0, L_0x1321140, C4<0>, C4<0>; -L_0x1321df0 .delay 1 (30000,30000,30000) L_0x1321df0/d; -L_0x11c7470/d .functor AND 1, L_0x1321bd0, L_0x1321140, C4<1>, C4<1>; -L_0x11c7470 .delay 1 (30000,30000,30000) L_0x11c7470/d; -v0x11c6c70_0 .net "a", 0 0, L_0x1321bd0; alias, 1 drivers -v0x11c6d40_0 .net "b", 0 0, L_0x1321140; alias, 1 drivers -v0x11c6de0_0 .net "carryout", 0 0, L_0x11c7470; alias, 1 drivers -v0x11c6eb0_0 .net "sum", 0 0, L_0x1321df0; alias, 1 drivers -S_0x11c8a60 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11b8d00; - .timescale -9 -12; -L_0x2b0ab3d070b8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d07100 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x132ac10/d .functor OR 1, L_0x2b0ab3d070b8, L_0x2b0ab3d07100, C4<0>, C4<0>; -L_0x132ac10 .delay 1 (30000,30000,30000) L_0x132ac10/d; -v0x11c8c50_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d070b8; 1 drivers -v0x11c8d30_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d07100; 1 drivers -S_0x11c8e10 .scope generate, "alu_slices[30]" "alu_slices[30]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11c9020 .param/l "i" 0 3 41, +C4<011110>; -S_0x11c90e0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11c8e10; +L_0x2e14ab0/d .functor XOR 1, L_0x2e14890, L_0x2e13d90, C4<0>, C4<0>; +L_0x2e14ab0 .delay 1 (30000,30000,30000) L_0x2e14ab0/d; +L_0x2ca1080/d .functor AND 1, L_0x2e14890, L_0x2e13d90, C4<1>, C4<1>; +L_0x2ca1080 .delay 1 (30000,30000,30000) L_0x2ca1080/d; +v0x2ca0880_0 .net "a", 0 0, L_0x2e14890; alias, 1 drivers +v0x2ca0950_0 .net "b", 0 0, L_0x2e13d90; alias, 1 drivers +v0x2ca09f0_0 .net "carryout", 0 0, L_0x2ca1080; alias, 1 drivers +v0x2ca0ac0_0 .net "sum", 0 0, L_0x2e14ab0; alias, 1 drivers +S_0x2ca32e0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2c92910; + .timescale -9 -12; +L_0x2ac6110bd518 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd560 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e14410/d .functor OR 1, L_0x2ac6110bd518, L_0x2ac6110bd560, C4<0>, C4<0>; +L_0x2e14410 .delay 1 (30000,30000,30000) L_0x2e14410/d; +v0x2ca34d0_0 .net/2u *"_s0", 0 0, L_0x2ac6110bd518; 1 drivers +v0x2ca35b0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bd560; 1 drivers +S_0x2ca3690 .scope generate, "alu_slices[30]" "alu_slices[30]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2ca38a0 .param/l "i" 0 3 39, +C4<011110>; +S_0x2ca3960 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2ca3690; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -16104,445 +17036,476 @@ S_0x11c90e0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11c8e10; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x13212d0/d .functor NOT 1, L_0x13347a0, C4<0>, C4<0>, C4<0>; -L_0x13212d0 .delay 1 (10000,10000,10000) L_0x13212d0/d; -L_0x132b0a0/d .functor NOT 1, L_0x1295ce0, C4<0>, C4<0>, C4<0>; -L_0x132b0a0 .delay 1 (10000,10000,10000) L_0x132b0a0/d; -L_0x132c0f0/d .functor XOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; -L_0x132c0f0 .delay 1 (30000,30000,30000) L_0x132c0f0/d; -L_0x2b0ab3d07148 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d07190 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x132c7a0/d .functor OR 1, L_0x2b0ab3d07148, L_0x2b0ab3d07190, C4<0>, C4<0>; -L_0x132c7a0 .delay 1 (30000,30000,30000) L_0x132c7a0/d; -L_0x132c9a0/d .functor AND 1, L_0x13347a0, L_0x1295ce0, C4<1>, C4<1>; -L_0x132c9a0 .delay 1 (30000,30000,30000) L_0x132c9a0/d; -L_0x132ca60/d .functor NAND 1, L_0x13347a0, L_0x1295ce0, C4<1>, C4<1>; -L_0x132ca60 .delay 1 (20000,20000,20000) L_0x132ca60/d; -L_0x132cbc0/d .functor XOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; -L_0x132cbc0 .delay 1 (20000,20000,20000) L_0x132cbc0/d; -L_0x132d070/d .functor OR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; -L_0x132d070 .delay 1 (30000,30000,30000) L_0x132d070/d; -L_0x13346a0/d .functor NOT 1, L_0x1330900, C4<0>, C4<0>, C4<0>; -L_0x13346a0 .delay 1 (10000,10000,10000) L_0x13346a0/d; -v0x11d7810_0 .net "A", 0 0, L_0x13347a0; 1 drivers -v0x11d78d0_0 .net "A_", 0 0, L_0x13212d0; 1 drivers -v0x11d7990_0 .net "B", 0 0, L_0x1295ce0; 1 drivers -v0x11d7a60_0 .net "B_", 0 0, L_0x132b0a0; 1 drivers -v0x11d7b00_0 .net *"_s12", 0 0, L_0x132c7a0; 1 drivers -v0x11d7bf0_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d07148; 1 drivers -v0x11d7cb0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d07190; 1 drivers -v0x11d7d90_0 .net *"_s18", 0 0, L_0x132c9a0; 1 drivers -v0x11d7e70_0 .net *"_s20", 0 0, L_0x132ca60; 1 drivers -v0x11d7fe0_0 .net *"_s22", 0 0, L_0x132cbc0; 1 drivers -v0x11d80c0_0 .net *"_s24", 0 0, L_0x132d070; 1 drivers -o0x2b0ab3cec228 .functor BUFZ 1, C4; HiZ drive -; Elide local net with no drivers, v0x11d81a0_0 name=_s30 -o0x2b0ab3cec258 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x11d8280_0 name=_s32 -v0x11d8360_0 .net *"_s8", 0 0, L_0x132c0f0; 1 drivers -v0x11d8440_0 .net "carryin", 0 0, L_0x132acd0; 1 drivers -v0x11d84e0_0 .net "carryout", 0 0, L_0x1334340; 1 drivers -v0x11d8580_0 .net "carryouts", 7 0, L_0x1356280; 1 drivers -v0x11d8730_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11d87d0_0 .net "result", 0 0, L_0x1330900; 1 drivers -v0x11d88c0_0 .net "results", 7 0, L_0x132ce40; 1 drivers -v0x11d89d0_0 .net "zero", 0 0, L_0x13346a0; 1 drivers -LS_0x132ce40_0_0 .concat8 [ 1 1 1 1], L_0x132b5c0, L_0x132bbf0, L_0x132c0f0, L_0x132c7a0; -LS_0x132ce40_0_4 .concat8 [ 1 1 1 1], L_0x132c9a0, L_0x132ca60, L_0x132cbc0, L_0x132d070; -L_0x132ce40 .concat8 [ 4 4 0 0], LS_0x132ce40_0_0, LS_0x132ce40_0_4; -LS_0x1356280_0_0 .concat [ 1 1 1 1], L_0x132b870, L_0x132bf90, o0x2b0ab3cec228, L_0x132c5f0; -LS_0x1356280_0_4 .concat [ 4 0 0 0], o0x2b0ab3cec258; -L_0x1356280 .concat [ 4 4 0 0], LS_0x1356280_0_0, LS_0x1356280_0_4; -S_0x11c9360 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11c90e0; +L_0x2e13f20/d .functor NOT 1, L_0x2e28ba0, C4<0>, C4<0>, C4<0>; +L_0x2e13f20 .delay 1 (10000,10000,10000) L_0x2e13f20/d; +L_0x2e1e7f0/d .functor NOT 1, L_0x2d7dcf0, C4<0>, C4<0>, C4<0>; +L_0x2e1e7f0 .delay 1 (10000,10000,10000) L_0x2e1e7f0/d; +L_0x2e1f7f0/d .functor XOR 1, L_0x2e28ba0, L_0x2d7dcf0, C4<0>, C4<0>; +L_0x2e1f7f0 .delay 1 (30000,30000,30000) L_0x2e1f7f0/d; +L_0x2ac6110bd5a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd5f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e1f8b0/d .functor OR 1, L_0x2ac6110bd5a8, L_0x2ac6110bd5f0, C4<0>, C4<0>; +L_0x2e1f8b0 .delay 1 (30000,30000,30000) L_0x2e1f8b0/d; +L_0x2ac6110bd638 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd680 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e20050/d .functor OR 1, L_0x2ac6110bd638, L_0x2ac6110bd680, C4<0>, C4<0>; +L_0x2e20050 .delay 1 (30000,30000,30000) L_0x2e20050/d; +L_0x2e20250/d .functor AND 1, L_0x2e28ba0, L_0x2d7dcf0, C4<1>, C4<1>; +L_0x2e20250 .delay 1 (30000,30000,30000) L_0x2e20250/d; +L_0x2ac6110bd6c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd710 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e20310/d .functor OR 1, L_0x2ac6110bd6c8, L_0x2ac6110bd710, C4<0>, C4<0>; +L_0x2e20310 .delay 1 (30000,30000,30000) L_0x2e20310/d; +L_0x2e20510/d .functor NAND 1, L_0x2e28ba0, L_0x2d7dcf0, C4<1>, C4<1>; +L_0x2e20510 .delay 1 (20000,20000,20000) L_0x2e20510/d; +L_0x2ac6110bd758 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd7a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e20620/d .functor OR 1, L_0x2ac6110bd758, L_0x2ac6110bd7a0, C4<0>, C4<0>; +L_0x2e20620 .delay 1 (30000,30000,30000) L_0x2e20620/d; +L_0x2e207d0/d .functor NOR 1, L_0x2e28ba0, L_0x2d7dcf0, C4<0>, C4<0>; +L_0x2e207d0 .delay 1 (20000,20000,20000) L_0x2e207d0/d; +L_0x2ac6110bd7e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd830 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e20aa0/d .functor OR 1, L_0x2ac6110bd7e8, L_0x2ac6110bd830, C4<0>, C4<0>; +L_0x2e20aa0 .delay 1 (30000,30000,30000) L_0x2e20aa0/d; +L_0x2e20ea0/d .functor OR 1, L_0x2e28ba0, L_0x2d7dcf0, C4<0>, C4<0>; +L_0x2e20ea0 .delay 1 (30000,30000,30000) L_0x2e20ea0/d; +L_0x2ac6110bd878 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd8c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e21340/d .functor OR 1, L_0x2ac6110bd878, L_0x2ac6110bd8c0, C4<0>, C4<0>; +L_0x2e21340 .delay 1 (30000,30000,30000) L_0x2e21340/d; +L_0x2e28aa0/d .functor NOT 1, L_0x2e24d00, C4<0>, C4<0>, C4<0>; +L_0x2e28aa0 .delay 1 (10000,10000,10000) L_0x2e28aa0/d; +v0x2cb20a0_0 .net "A", 0 0, L_0x2e28ba0; 1 drivers +v0x2cb2160_0 .net "A_", 0 0, L_0x2e13f20; 1 drivers +v0x2cb2220_0 .net "B", 0 0, L_0x2d7dcf0; 1 drivers +v0x2cb22f0_0 .net "B_", 0 0, L_0x2e1e7f0; 1 drivers +v0x2cb2390_0 .net *"_s11", 0 0, L_0x2e1f8b0; 1 drivers +v0x2cb2480_0 .net/2s *"_s13", 0 0, L_0x2ac6110bd5a8; 1 drivers +v0x2cb2540_0 .net/2s *"_s15", 0 0, L_0x2ac6110bd5f0; 1 drivers +v0x2cb2620_0 .net *"_s19", 0 0, L_0x2e20050; 1 drivers +v0x2cb2700_0 .net/2s *"_s21", 0 0, L_0x2ac6110bd638; 1 drivers +v0x2cb2870_0 .net/2s *"_s23", 0 0, L_0x2ac6110bd680; 1 drivers +v0x2cb2950_0 .net *"_s25", 0 0, L_0x2e20250; 1 drivers +v0x2cb2a30_0 .net *"_s28", 0 0, L_0x2e20310; 1 drivers +v0x2cb2b10_0 .net/2s *"_s30", 0 0, L_0x2ac6110bd6c8; 1 drivers +v0x2cb2bf0_0 .net/2s *"_s32", 0 0, L_0x2ac6110bd710; 1 drivers +v0x2cb2cd0_0 .net *"_s34", 0 0, L_0x2e20510; 1 drivers +v0x2cb2db0_0 .net *"_s37", 0 0, L_0x2e20620; 1 drivers +v0x2cb2e90_0 .net/2s *"_s39", 0 0, L_0x2ac6110bd758; 1 drivers +v0x2cb3040_0 .net/2s *"_s41", 0 0, L_0x2ac6110bd7a0; 1 drivers +v0x2cb30e0_0 .net *"_s43", 0 0, L_0x2e207d0; 1 drivers +v0x2cb31c0_0 .net *"_s46", 0 0, L_0x2e20aa0; 1 drivers +v0x2cb32a0_0 .net/2s *"_s48", 0 0, L_0x2ac6110bd7e8; 1 drivers +v0x2cb3380_0 .net/2s *"_s50", 0 0, L_0x2ac6110bd830; 1 drivers +v0x2cb3460_0 .net *"_s52", 0 0, L_0x2e20ea0; 1 drivers +v0x2cb3540_0 .net *"_s56", 0 0, L_0x2e21340; 1 drivers +v0x2cb3620_0 .net/2s *"_s59", 0 0, L_0x2ac6110bd878; 1 drivers +v0x2cb3700_0 .net/2s *"_s61", 0 0, L_0x2ac6110bd8c0; 1 drivers +v0x2cb37e0_0 .net *"_s8", 0 0, L_0x2e1f7f0; 1 drivers +v0x2cb38c0_0 .net "carryin", 0 0, L_0x2e1e470; 1 drivers +v0x2cb3960_0 .net "carryout", 0 0, L_0x2e28740; 1 drivers +v0x2cb3a00_0 .net "carryouts", 7 0, L_0x2e20fb0; 1 drivers +v0x2cb3b10_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2cb3bd0_0 .net "result", 0 0, L_0x2e24d00; 1 drivers +v0x2cb3cc0_0 .net "results", 7 0, L_0x2e20c70; 1 drivers +v0x2cb2fa0_0 .net "zero", 0 0, L_0x2e28aa0; 1 drivers +LS_0x2e20c70_0_0 .concat8 [ 1 1 1 1], L_0x2e1ecc0, L_0x2e1f2f0, L_0x2e1f7f0, L_0x2e20050; +LS_0x2e20c70_0_4 .concat8 [ 1 1 1 1], L_0x2e20250, L_0x2e20510, L_0x2e207d0, L_0x2e20ea0; +L_0x2e20c70 .concat8 [ 4 4 0 0], LS_0x2e20c70_0_0, LS_0x2e20c70_0_4; +LS_0x2e20fb0_0_0 .concat8 [ 1 1 1 1], L_0x2e1ef70, L_0x2e1f690, L_0x2e1f8b0, L_0x2e1fea0; +LS_0x2e20fb0_0_4 .concat8 [ 1 1 1 1], L_0x2e20310, L_0x2e20620, L_0x2e20aa0, L_0x2e21340; +L_0x2e20fb0 .concat8 [ 4 4 0 0], LS_0x2e20fb0_0_0, LS_0x2e20fb0_0_4; +S_0x2ca3be0 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2ca3960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x132b870/d .functor OR 1, L_0x132b350, L_0x132b710, C4<0>, C4<0>; -L_0x132b870 .delay 1 (30000,30000,30000) L_0x132b870/d; -v0x11ca190_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers -v0x11ca250_0 .net "b", 0 0, L_0x1295ce0; alias, 1 drivers -v0x11ca320_0 .net "c1", 0 0, L_0x132b350; 1 drivers -v0x11ca420_0 .net "c2", 0 0, L_0x132b710; 1 drivers -v0x11ca4f0_0 .net "carryin", 0 0, L_0x132acd0; alias, 1 drivers -v0x11ca5e0_0 .net "carryout", 0 0, L_0x132b870; 1 drivers -v0x11ca680_0 .net "s1", 0 0, L_0x132b290; 1 drivers -v0x11ca770_0 .net "sum", 0 0, L_0x132b5c0; 1 drivers -S_0x11c95d0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11c9360; +L_0x2e1ef70/d .functor OR 1, L_0x2e1ea50, L_0x2e1ee10, C4<0>, C4<0>; +L_0x2e1ef70 .delay 1 (30000,30000,30000) L_0x2e1ef70/d; +v0x2ca4a10_0 .net "a", 0 0, L_0x2e28ba0; alias, 1 drivers +v0x2ca4ad0_0 .net "b", 0 0, L_0x2d7dcf0; alias, 1 drivers +v0x2ca4ba0_0 .net "c1", 0 0, L_0x2e1ea50; 1 drivers +v0x2ca4ca0_0 .net "c2", 0 0, L_0x2e1ee10; 1 drivers +v0x2ca4d70_0 .net "carryin", 0 0, L_0x2e1e470; alias, 1 drivers +v0x2ca4e60_0 .net "carryout", 0 0, L_0x2e1ef70; 1 drivers +v0x2ca4f00_0 .net "s1", 0 0, L_0x2e1e9e0; 1 drivers +v0x2ca4ff0_0 .net "sum", 0 0, L_0x2e1ecc0; 1 drivers +S_0x2ca3e50 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2ca3be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x132b290/d .functor XOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; -L_0x132b290 .delay 1 (30000,30000,30000) L_0x132b290/d; -L_0x132b350/d .functor AND 1, L_0x13347a0, L_0x1295ce0, C4<1>, C4<1>; -L_0x132b350 .delay 1 (30000,30000,30000) L_0x132b350/d; -v0x11c9830_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers -v0x11c9910_0 .net "b", 0 0, L_0x1295ce0; alias, 1 drivers -v0x11c99d0_0 .net "carryout", 0 0, L_0x132b350; alias, 1 drivers -v0x11c9a70_0 .net "sum", 0 0, L_0x132b290; alias, 1 drivers -S_0x11c9bb0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11c9360; +L_0x2e1e9e0/d .functor XOR 1, L_0x2e28ba0, L_0x2d7dcf0, C4<0>, C4<0>; +L_0x2e1e9e0 .delay 1 (30000,30000,30000) L_0x2e1e9e0/d; +L_0x2e1ea50/d .functor AND 1, L_0x2e28ba0, L_0x2d7dcf0, C4<1>, C4<1>; +L_0x2e1ea50 .delay 1 (30000,30000,30000) L_0x2e1ea50/d; +v0x2ca40b0_0 .net "a", 0 0, L_0x2e28ba0; alias, 1 drivers +v0x2ca4190_0 .net "b", 0 0, L_0x2d7dcf0; alias, 1 drivers +v0x2ca4250_0 .net "carryout", 0 0, L_0x2e1ea50; alias, 1 drivers +v0x2ca42f0_0 .net "sum", 0 0, L_0x2e1e9e0; alias, 1 drivers +S_0x2ca4430 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2ca3be0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x132b5c0/d .functor XOR 1, L_0x132b290, L_0x132acd0, C4<0>, C4<0>; -L_0x132b5c0 .delay 1 (30000,30000,30000) L_0x132b5c0/d; -L_0x132b710/d .functor AND 1, L_0x132b290, L_0x132acd0, C4<1>, C4<1>; -L_0x132b710 .delay 1 (30000,30000,30000) L_0x132b710/d; -v0x11c9e10_0 .net "a", 0 0, L_0x132b290; alias, 1 drivers -v0x11c9eb0_0 .net "b", 0 0, L_0x132acd0; alias, 1 drivers -v0x11c9f50_0 .net "carryout", 0 0, L_0x132b710; alias, 1 drivers -v0x11ca020_0 .net "sum", 0 0, L_0x132b5c0; alias, 1 drivers -S_0x11ca840 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11c90e0; +L_0x2e1ecc0/d .functor XOR 1, L_0x2e1e9e0, L_0x2e1e470, C4<0>, C4<0>; +L_0x2e1ecc0 .delay 1 (30000,30000,30000) L_0x2e1ecc0/d; +L_0x2e1ee10/d .functor AND 1, L_0x2e1e9e0, L_0x2e1e470, C4<1>, C4<1>; +L_0x2e1ee10 .delay 1 (30000,30000,30000) L_0x2e1ee10/d; +v0x2ca4690_0 .net "a", 0 0, L_0x2e1e9e0; alias, 1 drivers +v0x2ca4730_0 .net "b", 0 0, L_0x2e1e470; alias, 1 drivers +v0x2ca47d0_0 .net "carryout", 0 0, L_0x2e1ee10; alias, 1 drivers +v0x2ca48a0_0 .net "sum", 0 0, L_0x2e1ecc0; alias, 1 drivers +S_0x2ca50c0 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2ca3960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11cfc30_0 .net "ands", 7 0, L_0x1332340; 1 drivers -v0x11cfd40_0 .net "in", 7 0, L_0x1356280; alias, 1 drivers -v0x11cfe00_0 .net "out", 0 0, L_0x1334340; alias, 1 drivers -v0x11cfed0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11caa60 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11ca840; +v0x2caa4c0_0 .net "ands", 7 0, L_0x2e26740; 1 drivers +v0x2caa5d0_0 .net "in", 7 0, L_0x2e20fb0; alias, 1 drivers +v0x2caa690_0 .net "out", 0 0, L_0x2e28740; alias, 1 drivers +v0x2caa760_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2ca52e0 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2ca50c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11cd190_0 .net "A", 7 0, L_0x1356280; alias, 1 drivers -v0x11cd290_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11cd350_0 .net *"_s0", 0 0, L_0x1330c60; 1 drivers -v0x11cd410_0 .net *"_s12", 0 0, L_0x13315d0; 1 drivers -v0x11cd4f0_0 .net *"_s16", 0 0, L_0x1331930; 1 drivers -v0x11cd620_0 .net *"_s20", 0 0, L_0x1331c40; 1 drivers -v0x11cd700_0 .net *"_s24", 0 0, L_0x1332030; 1 drivers -v0x11cd7e0_0 .net *"_s28", 0 0, L_0x1331fc0; 1 drivers -v0x11cd8c0_0 .net *"_s4", 0 0, L_0x1330f70; 1 drivers -v0x11cda30_0 .net *"_s8", 0 0, L_0x13312c0; 1 drivers -v0x11cdb10_0 .net "out", 7 0, L_0x1332340; alias, 1 drivers -L_0x1330d20 .part L_0x1356280, 0, 1; -L_0x1330e80 .part v0x12010b0_0, 0, 1; -L_0x1331030 .part L_0x1356280, 1, 1; -L_0x1331220 .part v0x12010b0_0, 1, 1; -L_0x1331380 .part L_0x1356280, 2, 1; -L_0x13314e0 .part v0x12010b0_0, 2, 1; -L_0x1331690 .part L_0x1356280, 3, 1; -L_0x13317f0 .part v0x12010b0_0, 3, 1; -L_0x13319f0 .part L_0x1356280, 4, 1; -L_0x1331b50 .part v0x12010b0_0, 4, 1; -L_0x1331cb0 .part L_0x1356280, 5, 1; -L_0x1331f20 .part v0x12010b0_0, 5, 1; -L_0x13320f0 .part L_0x1356280, 6, 1; -L_0x1332250 .part v0x12010b0_0, 6, 1; -LS_0x1332340_0_0 .concat8 [ 1 1 1 1], L_0x1330c60, L_0x1330f70, L_0x13312c0, L_0x13315d0; -LS_0x1332340_0_4 .concat8 [ 1 1 1 1], L_0x1331930, L_0x1331c40, L_0x1332030, L_0x1331fc0; -L_0x1332340 .concat8 [ 4 4 0 0], LS_0x1332340_0_0, LS_0x1332340_0_4; -L_0x1332700 .part L_0x1356280, 7, 1; -L_0x13328f0 .part v0x12010b0_0, 7, 1; -S_0x11cacc0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11caed0 .param/l "i" 0 4 54, +C4<00>; -L_0x1330c60/d .functor AND 1, L_0x1330d20, L_0x1330e80, C4<1>, C4<1>; -L_0x1330c60 .delay 1 (30000,30000,30000) L_0x1330c60/d; -v0x11cafb0_0 .net *"_s0", 0 0, L_0x1330d20; 1 drivers -v0x11cb090_0 .net *"_s1", 0 0, L_0x1330e80; 1 drivers -S_0x11cb170 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11cb380 .param/l "i" 0 4 54, +C4<01>; -L_0x1330f70/d .functor AND 1, L_0x1331030, L_0x1331220, C4<1>, C4<1>; -L_0x1330f70 .delay 1 (30000,30000,30000) L_0x1330f70/d; -v0x11cb440_0 .net *"_s0", 0 0, L_0x1331030; 1 drivers -v0x11cb520_0 .net *"_s1", 0 0, L_0x1331220; 1 drivers -S_0x11cb600 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11cb810 .param/l "i" 0 4 54, +C4<010>; -L_0x13312c0/d .functor AND 1, L_0x1331380, L_0x13314e0, C4<1>, C4<1>; -L_0x13312c0 .delay 1 (30000,30000,30000) L_0x13312c0/d; -v0x11cb8b0_0 .net *"_s0", 0 0, L_0x1331380; 1 drivers -v0x11cb990_0 .net *"_s1", 0 0, L_0x13314e0; 1 drivers -S_0x11cba70 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11cbc80 .param/l "i" 0 4 54, +C4<011>; -L_0x13315d0/d .functor AND 1, L_0x1331690, L_0x13317f0, C4<1>, C4<1>; -L_0x13315d0 .delay 1 (30000,30000,30000) L_0x13315d0/d; -v0x11cbd40_0 .net *"_s0", 0 0, L_0x1331690; 1 drivers -v0x11cbe20_0 .net *"_s1", 0 0, L_0x13317f0; 1 drivers -S_0x11cbf00 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11cc160 .param/l "i" 0 4 54, +C4<0100>; -L_0x1331930/d .functor AND 1, L_0x13319f0, L_0x1331b50, C4<1>, C4<1>; -L_0x1331930 .delay 1 (30000,30000,30000) L_0x1331930/d; -v0x11cc220_0 .net *"_s0", 0 0, L_0x13319f0; 1 drivers -v0x11cc300_0 .net *"_s1", 0 0, L_0x1331b50; 1 drivers -S_0x11cc3e0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11cc5f0 .param/l "i" 0 4 54, +C4<0101>; -L_0x1331c40/d .functor AND 1, L_0x1331cb0, L_0x1331f20, C4<1>, C4<1>; -L_0x1331c40 .delay 1 (30000,30000,30000) L_0x1331c40/d; -v0x11cc6b0_0 .net *"_s0", 0 0, L_0x1331cb0; 1 drivers -v0x11cc790_0 .net *"_s1", 0 0, L_0x1331f20; 1 drivers -S_0x11cc870 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11cca80 .param/l "i" 0 4 54, +C4<0110>; -L_0x1332030/d .functor AND 1, L_0x13320f0, L_0x1332250, C4<1>, C4<1>; -L_0x1332030 .delay 1 (30000,30000,30000) L_0x1332030/d; -v0x11ccb40_0 .net *"_s0", 0 0, L_0x13320f0; 1 drivers -v0x11ccc20_0 .net *"_s1", 0 0, L_0x1332250; 1 drivers -S_0x11ccd00 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11caa60; - .timescale -9 -12; -P_0x11ccf10 .param/l "i" 0 4 54, +C4<0111>; -L_0x1331fc0/d .functor AND 1, L_0x1332700, L_0x13328f0, C4<1>, C4<1>; -L_0x1331fc0 .delay 1 (30000,30000,30000) L_0x1331fc0/d; -v0x11ccfd0_0 .net *"_s0", 0 0, L_0x1332700; 1 drivers -v0x11cd0b0_0 .net *"_s1", 0 0, L_0x13328f0; 1 drivers -S_0x11cdc70 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11ca840; +v0x2ca79f0_0 .net "A", 7 0, L_0x2e20fb0; alias, 1 drivers +v0x2ca7af0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2ca7bb0_0 .net *"_s0", 0 0, L_0x2e25060; 1 drivers +v0x2ca7ca0_0 .net *"_s12", 0 0, L_0x2e259d0; 1 drivers +v0x2ca7d80_0 .net *"_s16", 0 0, L_0x2e25d30; 1 drivers +v0x2ca7eb0_0 .net *"_s20", 0 0, L_0x2e26100; 1 drivers +v0x2ca7f90_0 .net *"_s24", 0 0, L_0x2e26430; 1 drivers +v0x2ca8070_0 .net *"_s28", 0 0, L_0x2e263c0; 1 drivers +v0x2ca8150_0 .net *"_s4", 0 0, L_0x2e253b0; 1 drivers +v0x2ca82c0_0 .net *"_s8", 0 0, L_0x2e256c0; 1 drivers +v0x2ca83a0_0 .net "out", 7 0, L_0x2e26740; alias, 1 drivers +L_0x2e25120 .part L_0x2e20fb0, 0, 1; +L_0x2e25310 .part v0x2cdd2e0_0, 0, 1; +L_0x2e25470 .part L_0x2e20fb0, 1, 1; +L_0x2e255d0 .part v0x2cdd2e0_0, 1, 1; +L_0x2e25780 .part L_0x2e20fb0, 2, 1; +L_0x2e258e0 .part v0x2cdd2e0_0, 2, 1; +L_0x2e25a90 .part L_0x2e20fb0, 3, 1; +L_0x2e25bf0 .part v0x2cdd2e0_0, 3, 1; +L_0x2e25df0 .part L_0x2e20fb0, 4, 1; +L_0x2e26060 .part v0x2cdd2e0_0, 4, 1; +L_0x2e26170 .part L_0x2e20fb0, 5, 1; +L_0x2e262d0 .part v0x2cdd2e0_0, 5, 1; +L_0x2e264f0 .part L_0x2e20fb0, 6, 1; +L_0x2e26650 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e26740_0_0 .concat8 [ 1 1 1 1], L_0x2e25060, L_0x2e253b0, L_0x2e256c0, L_0x2e259d0; +LS_0x2e26740_0_4 .concat8 [ 1 1 1 1], L_0x2e25d30, L_0x2e26100, L_0x2e26430, L_0x2e263c0; +L_0x2e26740 .concat8 [ 4 4 0 0], LS_0x2e26740_0_0, LS_0x2e26740_0_4; +L_0x2e26b00 .part L_0x2e20fb0, 7, 1; +L_0x2e26cf0 .part v0x2cdd2e0_0, 7, 1; +S_0x2ca5540 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca5750 .param/l "i" 0 4 54, +C4<00>; +L_0x2e25060/d .functor AND 1, L_0x2e25120, L_0x2e25310, C4<1>, C4<1>; +L_0x2e25060 .delay 1 (30000,30000,30000) L_0x2e25060/d; +v0x2ca5830_0 .net *"_s0", 0 0, L_0x2e25120; 1 drivers +v0x2ca5910_0 .net *"_s1", 0 0, L_0x2e25310; 1 drivers +S_0x2ca59f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca5c00 .param/l "i" 0 4 54, +C4<01>; +L_0x2e253b0/d .functor AND 1, L_0x2e25470, L_0x2e255d0, C4<1>, C4<1>; +L_0x2e253b0 .delay 1 (30000,30000,30000) L_0x2e253b0/d; +v0x2ca5cc0_0 .net *"_s0", 0 0, L_0x2e25470; 1 drivers +v0x2ca5da0_0 .net *"_s1", 0 0, L_0x2e255d0; 1 drivers +S_0x2ca5e80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca6090 .param/l "i" 0 4 54, +C4<010>; +L_0x2e256c0/d .functor AND 1, L_0x2e25780, L_0x2e258e0, C4<1>, C4<1>; +L_0x2e256c0 .delay 1 (30000,30000,30000) L_0x2e256c0/d; +v0x2ca6130_0 .net *"_s0", 0 0, L_0x2e25780; 1 drivers +v0x2ca6210_0 .net *"_s1", 0 0, L_0x2e258e0; 1 drivers +S_0x2ca62f0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca6500 .param/l "i" 0 4 54, +C4<011>; +L_0x2e259d0/d .functor AND 1, L_0x2e25a90, L_0x2e25bf0, C4<1>, C4<1>; +L_0x2e259d0 .delay 1 (30000,30000,30000) L_0x2e259d0/d; +v0x2ca65c0_0 .net *"_s0", 0 0, L_0x2e25a90; 1 drivers +v0x2ca66a0_0 .net *"_s1", 0 0, L_0x2e25bf0; 1 drivers +S_0x2ca6780 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca69e0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e25d30/d .functor AND 1, L_0x2e25df0, L_0x2e26060, C4<1>, C4<1>; +L_0x2e25d30 .delay 1 (30000,30000,30000) L_0x2e25d30/d; +v0x2ca6aa0_0 .net *"_s0", 0 0, L_0x2e25df0; 1 drivers +v0x2ca6b80_0 .net *"_s1", 0 0, L_0x2e26060; 1 drivers +S_0x2ca6c60 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca6e70 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e26100/d .functor AND 1, L_0x2e26170, L_0x2e262d0, C4<1>, C4<1>; +L_0x2e26100 .delay 1 (30000,30000,30000) L_0x2e26100/d; +v0x2ca6f30_0 .net *"_s0", 0 0, L_0x2e26170; 1 drivers +v0x2ca6ff0_0 .net *"_s1", 0 0, L_0x2e262d0; 1 drivers +S_0x2ca70d0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca72e0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e26430/d .functor AND 1, L_0x2e264f0, L_0x2e26650, C4<1>, C4<1>; +L_0x2e26430 .delay 1 (30000,30000,30000) L_0x2e26430/d; +v0x2ca73a0_0 .net *"_s0", 0 0, L_0x2e264f0; 1 drivers +v0x2ca7480_0 .net *"_s1", 0 0, L_0x2e26650; 1 drivers +S_0x2ca7560 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2ca52e0; + .timescale -9 -12; +P_0x2ca7770 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e263c0/d .functor AND 1, L_0x2e26b00, L_0x2e26cf0, C4<1>, C4<1>; +L_0x2e263c0 .delay 1 (30000,30000,30000) L_0x2e263c0/d; +v0x2ca7830_0 .net *"_s0", 0 0, L_0x2e26b00; 1 drivers +v0x2ca7910_0 .net *"_s1", 0 0, L_0x2e26cf0; 1 drivers +S_0x2ca8500 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2ca50c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1334340/d .functor OR 1, L_0x1334400, L_0x13345b0, C4<0>, C4<0>; -L_0x1334340 .delay 1 (30000,30000,30000) L_0x1334340/d; -v0x11cf7c0_0 .net *"_s10", 0 0, L_0x1334400; 1 drivers -v0x11cf8a0_0 .net *"_s12", 0 0, L_0x13345b0; 1 drivers -v0x11cf980_0 .net "in", 7 0, L_0x1332340; alias, 1 drivers -v0x11cfa50_0 .net "ors", 1 0, L_0x1334160; 1 drivers -v0x11cfb10_0 .net "out", 0 0, L_0x1334340; alias, 1 drivers -L_0x1333530 .part L_0x1332340, 0, 4; -L_0x1334160 .concat8 [ 1 1 0 0], L_0x1333220, L_0x1333e50; -L_0x13342a0 .part L_0x1332340, 4, 4; -L_0x1334400 .part L_0x1334160, 0, 1; -L_0x13345b0 .part L_0x1334160, 1, 1; -S_0x11cde30 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11cdc70; +L_0x2e28740/d .functor OR 1, L_0x2e28800, L_0x2e289b0, C4<0>, C4<0>; +L_0x2e28740 .delay 1 (30000,30000,30000) L_0x2e28740/d; +v0x2caa050_0 .net *"_s10", 0 0, L_0x2e28800; 1 drivers +v0x2caa130_0 .net *"_s12", 0 0, L_0x2e289b0; 1 drivers +v0x2caa210_0 .net "in", 7 0, L_0x2e26740; alias, 1 drivers +v0x2caa2e0_0 .net "ors", 1 0, L_0x2e28560; 1 drivers +v0x2caa3a0_0 .net "out", 0 0, L_0x2e28740; alias, 1 drivers +L_0x2e27930 .part L_0x2e26740, 0, 4; +L_0x2e28560 .concat8 [ 1 1 0 0], L_0x2e27620, L_0x2e28250; +L_0x2e286a0 .part L_0x2e26740, 4, 4; +L_0x2e28800 .part L_0x2e28560, 0, 1; +L_0x2e289b0 .part L_0x2e28560, 1, 1; +S_0x2ca86c0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2ca8500; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x13329e0/d .functor OR 1, L_0x1332aa0, L_0x1332c00, C4<0>, C4<0>; -L_0x13329e0 .delay 1 (30000,30000,30000) L_0x13329e0/d; -L_0x1332e30/d .functor OR 1, L_0x1332f40, L_0x13330a0, C4<0>, C4<0>; -L_0x1332e30 .delay 1 (30000,30000,30000) L_0x1332e30/d; -L_0x1333220/d .functor OR 1, L_0x1333290, L_0x1333440, C4<0>, C4<0>; -L_0x1333220 .delay 1 (30000,30000,30000) L_0x1333220/d; -v0x11ce080_0 .net *"_s0", 0 0, L_0x13329e0; 1 drivers -v0x11ce180_0 .net *"_s10", 0 0, L_0x1332f40; 1 drivers -v0x11ce260_0 .net *"_s12", 0 0, L_0x13330a0; 1 drivers -v0x11ce320_0 .net *"_s14", 0 0, L_0x1333290; 1 drivers -v0x11ce400_0 .net *"_s16", 0 0, L_0x1333440; 1 drivers -v0x11ce530_0 .net *"_s3", 0 0, L_0x1332aa0; 1 drivers -v0x11ce610_0 .net *"_s5", 0 0, L_0x1332c00; 1 drivers -v0x11ce6f0_0 .net *"_s6", 0 0, L_0x1332e30; 1 drivers -v0x11ce7d0_0 .net "in", 3 0, L_0x1333530; 1 drivers -v0x11ce940_0 .net "ors", 1 0, L_0x1332d40; 1 drivers -v0x11cea20_0 .net "out", 0 0, L_0x1333220; 1 drivers -L_0x1332aa0 .part L_0x1333530, 0, 1; -L_0x1332c00 .part L_0x1333530, 1, 1; -L_0x1332d40 .concat8 [ 1 1 0 0], L_0x13329e0, L_0x1332e30; -L_0x1332f40 .part L_0x1333530, 2, 1; -L_0x13330a0 .part L_0x1333530, 3, 1; -L_0x1333290 .part L_0x1332d40, 0, 1; -L_0x1333440 .part L_0x1332d40, 1, 1; -S_0x11ceb40 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11cdc70; +L_0x2e26de0/d .functor OR 1, L_0x2e26ea0, L_0x2e27000, C4<0>, C4<0>; +L_0x2e26de0 .delay 1 (30000,30000,30000) L_0x2e26de0/d; +L_0x2e27230/d .functor OR 1, L_0x2e27340, L_0x2e274a0, C4<0>, C4<0>; +L_0x2e27230 .delay 1 (30000,30000,30000) L_0x2e27230/d; +L_0x2e27620/d .functor OR 1, L_0x2e27690, L_0x2e27840, C4<0>, C4<0>; +L_0x2e27620 .delay 1 (30000,30000,30000) L_0x2e27620/d; +v0x2ca8910_0 .net *"_s0", 0 0, L_0x2e26de0; 1 drivers +v0x2ca8a10_0 .net *"_s10", 0 0, L_0x2e27340; 1 drivers +v0x2ca8af0_0 .net *"_s12", 0 0, L_0x2e274a0; 1 drivers +v0x2ca8bb0_0 .net *"_s14", 0 0, L_0x2e27690; 1 drivers +v0x2ca8c90_0 .net *"_s16", 0 0, L_0x2e27840; 1 drivers +v0x2ca8dc0_0 .net *"_s3", 0 0, L_0x2e26ea0; 1 drivers +v0x2ca8ea0_0 .net *"_s5", 0 0, L_0x2e27000; 1 drivers +v0x2ca8f80_0 .net *"_s6", 0 0, L_0x2e27230; 1 drivers +v0x2ca9060_0 .net "in", 3 0, L_0x2e27930; 1 drivers +v0x2ca91d0_0 .net "ors", 1 0, L_0x2e27140; 1 drivers +v0x2ca92b0_0 .net "out", 0 0, L_0x2e27620; 1 drivers +L_0x2e26ea0 .part L_0x2e27930, 0, 1; +L_0x2e27000 .part L_0x2e27930, 1, 1; +L_0x2e27140 .concat8 [ 1 1 0 0], L_0x2e26de0, L_0x2e27230; +L_0x2e27340 .part L_0x2e27930, 2, 1; +L_0x2e274a0 .part L_0x2e27930, 3, 1; +L_0x2e27690 .part L_0x2e27140, 0, 1; +L_0x2e27840 .part L_0x2e27140, 1, 1; +S_0x2ca93d0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2ca8500; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1333660/d .functor OR 1, L_0x13336d0, L_0x1333830, C4<0>, C4<0>; -L_0x1333660 .delay 1 (30000,30000,30000) L_0x1333660/d; -L_0x1333a60/d .functor OR 1, L_0x1333b70, L_0x1333cd0, C4<0>, C4<0>; -L_0x1333a60 .delay 1 (30000,30000,30000) L_0x1333a60/d; -L_0x1333e50/d .functor OR 1, L_0x1333ec0, L_0x1334070, C4<0>, C4<0>; -L_0x1333e50 .delay 1 (30000,30000,30000) L_0x1333e50/d; -v0x11ced00_0 .net *"_s0", 0 0, L_0x1333660; 1 drivers -v0x11cee00_0 .net *"_s10", 0 0, L_0x1333b70; 1 drivers -v0x11ceee0_0 .net *"_s12", 0 0, L_0x1333cd0; 1 drivers -v0x11cefa0_0 .net *"_s14", 0 0, L_0x1333ec0; 1 drivers -v0x11cf080_0 .net *"_s16", 0 0, L_0x1334070; 1 drivers -v0x11cf1b0_0 .net *"_s3", 0 0, L_0x13336d0; 1 drivers -v0x11cf290_0 .net *"_s5", 0 0, L_0x1333830; 1 drivers -v0x11cf370_0 .net *"_s6", 0 0, L_0x1333a60; 1 drivers -v0x11cf450_0 .net "in", 3 0, L_0x13342a0; 1 drivers -v0x11cf5c0_0 .net "ors", 1 0, L_0x1333970; 1 drivers -v0x11cf6a0_0 .net "out", 0 0, L_0x1333e50; 1 drivers -L_0x13336d0 .part L_0x13342a0, 0, 1; -L_0x1333830 .part L_0x13342a0, 1, 1; -L_0x1333970 .concat8 [ 1 1 0 0], L_0x1333660, L_0x1333a60; -L_0x1333b70 .part L_0x13342a0, 2, 1; -L_0x1333cd0 .part L_0x13342a0, 3, 1; -L_0x1333ec0 .part L_0x1333970, 0, 1; -L_0x1334070 .part L_0x1333970, 1, 1; -S_0x11cffb0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11c90e0; +L_0x2e27a60/d .functor OR 1, L_0x2e27ad0, L_0x2e27c30, C4<0>, C4<0>; +L_0x2e27a60 .delay 1 (30000,30000,30000) L_0x2e27a60/d; +L_0x2e27e60/d .functor OR 1, L_0x2e27f70, L_0x2e280d0, C4<0>, C4<0>; +L_0x2e27e60 .delay 1 (30000,30000,30000) L_0x2e27e60/d; +L_0x2e28250/d .functor OR 1, L_0x2e282c0, L_0x2e28470, C4<0>, C4<0>; +L_0x2e28250 .delay 1 (30000,30000,30000) L_0x2e28250/d; +v0x2ca9590_0 .net *"_s0", 0 0, L_0x2e27a60; 1 drivers +v0x2ca9690_0 .net *"_s10", 0 0, L_0x2e27f70; 1 drivers +v0x2ca9770_0 .net *"_s12", 0 0, L_0x2e280d0; 1 drivers +v0x2ca9830_0 .net *"_s14", 0 0, L_0x2e282c0; 1 drivers +v0x2ca9910_0 .net *"_s16", 0 0, L_0x2e28470; 1 drivers +v0x2ca9a40_0 .net *"_s3", 0 0, L_0x2e27ad0; 1 drivers +v0x2ca9b20_0 .net *"_s5", 0 0, L_0x2e27c30; 1 drivers +v0x2ca9c00_0 .net *"_s6", 0 0, L_0x2e27e60; 1 drivers +v0x2ca9ce0_0 .net "in", 3 0, L_0x2e286a0; 1 drivers +v0x2ca9e50_0 .net "ors", 1 0, L_0x2e27d70; 1 drivers +v0x2ca9f30_0 .net "out", 0 0, L_0x2e28250; 1 drivers +L_0x2e27ad0 .part L_0x2e286a0, 0, 1; +L_0x2e27c30 .part L_0x2e286a0, 1, 1; +L_0x2e27d70 .concat8 [ 1 1 0 0], L_0x2e27a60, L_0x2e27e60; +L_0x2e27f70 .part L_0x2e286a0, 2, 1; +L_0x2e280d0 .part L_0x2e286a0, 3, 1; +L_0x2e282c0 .part L_0x2e27d70, 0, 1; +L_0x2e28470 .part L_0x2e27d70, 1, 1; +S_0x2caa840 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2ca3960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11d53e0_0 .net "ands", 7 0, L_0x132e900; 1 drivers -v0x11d54f0_0 .net "in", 7 0, L_0x132ce40; alias, 1 drivers -v0x11d55b0_0 .net "out", 0 0, L_0x1330900; alias, 1 drivers -v0x11d5680_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11d0200 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11cffb0; +v0x2cafc70_0 .net "ands", 7 0, L_0x2e22d00; 1 drivers +v0x2cafd80_0 .net "in", 7 0, L_0x2e20c70; alias, 1 drivers +v0x2cafe40_0 .net "out", 0 0, L_0x2e24d00; alias, 1 drivers +v0x2caff10_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2caaa90 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2caa840; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11d2940_0 .net "A", 7 0, L_0x132ce40; alias, 1 drivers -v0x11d2a40_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11d2b00_0 .net *"_s0", 0 0, L_0x132d1d0; 1 drivers -v0x11d2bc0_0 .net *"_s12", 0 0, L_0x132db90; 1 drivers -v0x11d2ca0_0 .net *"_s16", 0 0, L_0x132def0; 1 drivers -v0x11d2dd0_0 .net *"_s20", 0 0, L_0x132e2c0; 1 drivers -v0x11d2eb0_0 .net *"_s24", 0 0, L_0x132e5f0; 1 drivers -v0x11d2f90_0 .net *"_s28", 0 0, L_0x132e580; 1 drivers -v0x11d3070_0 .net *"_s4", 0 0, L_0x132d570; 1 drivers -v0x11d31e0_0 .net *"_s8", 0 0, L_0x132d880; 1 drivers -v0x11d32c0_0 .net "out", 7 0, L_0x132e900; alias, 1 drivers -L_0x132d2e0 .part L_0x132ce40, 0, 1; -L_0x132d4d0 .part v0x12010b0_0, 0, 1; -L_0x132d630 .part L_0x132ce40, 1, 1; -L_0x132d790 .part v0x12010b0_0, 1, 1; -L_0x132d940 .part L_0x132ce40, 2, 1; -L_0x132daa0 .part v0x12010b0_0, 2, 1; -L_0x132dc50 .part L_0x132ce40, 3, 1; -L_0x132ddb0 .part v0x12010b0_0, 3, 1; -L_0x132dfb0 .part L_0x132ce40, 4, 1; -L_0x132e220 .part v0x12010b0_0, 4, 1; -L_0x132e330 .part L_0x132ce40, 5, 1; -L_0x132e490 .part v0x12010b0_0, 5, 1; -L_0x132e6b0 .part L_0x132ce40, 6, 1; -L_0x132e810 .part v0x12010b0_0, 6, 1; -LS_0x132e900_0_0 .concat8 [ 1 1 1 1], L_0x132d1d0, L_0x132d570, L_0x132d880, L_0x132db90; -LS_0x132e900_0_4 .concat8 [ 1 1 1 1], L_0x132def0, L_0x132e2c0, L_0x132e5f0, L_0x132e580; -L_0x132e900 .concat8 [ 4 4 0 0], LS_0x132e900_0_0, LS_0x132e900_0_4; -L_0x132ecc0 .part L_0x132ce40, 7, 1; -L_0x132eeb0 .part v0x12010b0_0, 7, 1; -S_0x11d0440 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d0650 .param/l "i" 0 4 54, +C4<00>; -L_0x132d1d0/d .functor AND 1, L_0x132d2e0, L_0x132d4d0, C4<1>, C4<1>; -L_0x132d1d0 .delay 1 (30000,30000,30000) L_0x132d1d0/d; -v0x11d0730_0 .net *"_s0", 0 0, L_0x132d2e0; 1 drivers -v0x11d0810_0 .net *"_s1", 0 0, L_0x132d4d0; 1 drivers -S_0x11d08f0 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d0b00 .param/l "i" 0 4 54, +C4<01>; -L_0x132d570/d .functor AND 1, L_0x132d630, L_0x132d790, C4<1>, C4<1>; -L_0x132d570 .delay 1 (30000,30000,30000) L_0x132d570/d; -v0x11d0bc0_0 .net *"_s0", 0 0, L_0x132d630; 1 drivers -v0x11d0ca0_0 .net *"_s1", 0 0, L_0x132d790; 1 drivers -S_0x11d0d80 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d0fc0 .param/l "i" 0 4 54, +C4<010>; -L_0x132d880/d .functor AND 1, L_0x132d940, L_0x132daa0, C4<1>, C4<1>; -L_0x132d880 .delay 1 (30000,30000,30000) L_0x132d880/d; -v0x11d1060_0 .net *"_s0", 0 0, L_0x132d940; 1 drivers -v0x11d1140_0 .net *"_s1", 0 0, L_0x132daa0; 1 drivers -S_0x11d1220 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d1430 .param/l "i" 0 4 54, +C4<011>; -L_0x132db90/d .functor AND 1, L_0x132dc50, L_0x132ddb0, C4<1>, C4<1>; -L_0x132db90 .delay 1 (30000,30000,30000) L_0x132db90/d; -v0x11d14f0_0 .net *"_s0", 0 0, L_0x132dc50; 1 drivers -v0x11d15d0_0 .net *"_s1", 0 0, L_0x132ddb0; 1 drivers -S_0x11d16b0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d1910 .param/l "i" 0 4 54, +C4<0100>; -L_0x132def0/d .functor AND 1, L_0x132dfb0, L_0x132e220, C4<1>, C4<1>; -L_0x132def0 .delay 1 (30000,30000,30000) L_0x132def0/d; -v0x11d19d0_0 .net *"_s0", 0 0, L_0x132dfb0; 1 drivers -v0x11d1ab0_0 .net *"_s1", 0 0, L_0x132e220; 1 drivers -S_0x11d1b90 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d1da0 .param/l "i" 0 4 54, +C4<0101>; -L_0x132e2c0/d .functor AND 1, L_0x132e330, L_0x132e490, C4<1>, C4<1>; -L_0x132e2c0 .delay 1 (30000,30000,30000) L_0x132e2c0/d; -v0x11d1e60_0 .net *"_s0", 0 0, L_0x132e330; 1 drivers -v0x11d1f40_0 .net *"_s1", 0 0, L_0x132e490; 1 drivers -S_0x11d2020 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d2230 .param/l "i" 0 4 54, +C4<0110>; -L_0x132e5f0/d .functor AND 1, L_0x132e6b0, L_0x132e810, C4<1>, C4<1>; -L_0x132e5f0 .delay 1 (30000,30000,30000) L_0x132e5f0/d; -v0x11d22f0_0 .net *"_s0", 0 0, L_0x132e6b0; 1 drivers -v0x11d23d0_0 .net *"_s1", 0 0, L_0x132e810; 1 drivers -S_0x11d24b0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11d0200; - .timescale -9 -12; -P_0x11d26c0 .param/l "i" 0 4 54, +C4<0111>; -L_0x132e580/d .functor AND 1, L_0x132ecc0, L_0x132eeb0, C4<1>, C4<1>; -L_0x132e580 .delay 1 (30000,30000,30000) L_0x132e580/d; -v0x11d2780_0 .net *"_s0", 0 0, L_0x132ecc0; 1 drivers -v0x11d2860_0 .net *"_s1", 0 0, L_0x132eeb0; 1 drivers -S_0x11d3420 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11cffb0; +v0x2cad1d0_0 .net "A", 7 0, L_0x2e20c70; alias, 1 drivers +v0x2cad2d0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2cad390_0 .net *"_s0", 0 0, L_0x2e214f0; 1 drivers +v0x2cad450_0 .net *"_s12", 0 0, L_0x2e21eb0; 1 drivers +v0x2cad530_0 .net *"_s16", 0 0, L_0x2e22210; 1 drivers +v0x2cad660_0 .net *"_s20", 0 0, L_0x2e22640; 1 drivers +v0x2cad740_0 .net *"_s24", 0 0, L_0x2e22970; 1 drivers +v0x2cad820_0 .net *"_s28", 0 0, L_0x2e22900; 1 drivers +v0x2cad900_0 .net *"_s4", 0 0, L_0x2e21890; 1 drivers +v0x2cada70_0 .net *"_s8", 0 0, L_0x2e21ba0; 1 drivers +v0x2cadb50_0 .net "out", 7 0, L_0x2e22d00; alias, 1 drivers +L_0x2e21600 .part L_0x2e20c70, 0, 1; +L_0x2e217f0 .part v0x2cdd2e0_0, 0, 1; +L_0x2e21950 .part L_0x2e20c70, 1, 1; +L_0x2e21ab0 .part v0x2cdd2e0_0, 1, 1; +L_0x2e21c60 .part L_0x2e20c70, 2, 1; +L_0x2e21dc0 .part v0x2cdd2e0_0, 2, 1; +L_0x2e21f70 .part L_0x2e20c70, 3, 1; +L_0x2e220d0 .part v0x2cdd2e0_0, 3, 1; +L_0x2e222d0 .part L_0x2e20c70, 4, 1; +L_0x2e22540 .part v0x2cdd2e0_0, 4, 1; +L_0x2e226b0 .part L_0x2e20c70, 5, 1; +L_0x2e22810 .part v0x2cdd2e0_0, 5, 1; +L_0x2e22a30 .part L_0x2e20c70, 6, 1; +L_0x2e22b90 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e22d00_0_0 .concat8 [ 1 1 1 1], L_0x2e214f0, L_0x2e21890, L_0x2e21ba0, L_0x2e21eb0; +LS_0x2e22d00_0_4 .concat8 [ 1 1 1 1], L_0x2e22210, L_0x2e22640, L_0x2e22970, L_0x2e22900; +L_0x2e22d00 .concat8 [ 4 4 0 0], LS_0x2e22d00_0_0, LS_0x2e22d00_0_4; +L_0x2e230c0 .part L_0x2e20c70, 7, 1; +L_0x2e232b0 .part v0x2cdd2e0_0, 7, 1; +S_0x2caacd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2caaee0 .param/l "i" 0 4 54, +C4<00>; +L_0x2e214f0/d .functor AND 1, L_0x2e21600, L_0x2e217f0, C4<1>, C4<1>; +L_0x2e214f0 .delay 1 (30000,30000,30000) L_0x2e214f0/d; +v0x2caafc0_0 .net *"_s0", 0 0, L_0x2e21600; 1 drivers +v0x2cab0a0_0 .net *"_s1", 0 0, L_0x2e217f0; 1 drivers +S_0x2cab180 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cab390 .param/l "i" 0 4 54, +C4<01>; +L_0x2e21890/d .functor AND 1, L_0x2e21950, L_0x2e21ab0, C4<1>, C4<1>; +L_0x2e21890 .delay 1 (30000,30000,30000) L_0x2e21890/d; +v0x2cab450_0 .net *"_s0", 0 0, L_0x2e21950; 1 drivers +v0x2cab530_0 .net *"_s1", 0 0, L_0x2e21ab0; 1 drivers +S_0x2cab610 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cab850 .param/l "i" 0 4 54, +C4<010>; +L_0x2e21ba0/d .functor AND 1, L_0x2e21c60, L_0x2e21dc0, C4<1>, C4<1>; +L_0x2e21ba0 .delay 1 (30000,30000,30000) L_0x2e21ba0/d; +v0x2cab8f0_0 .net *"_s0", 0 0, L_0x2e21c60; 1 drivers +v0x2cab9d0_0 .net *"_s1", 0 0, L_0x2e21dc0; 1 drivers +S_0x2cabab0 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cabcc0 .param/l "i" 0 4 54, +C4<011>; +L_0x2e21eb0/d .functor AND 1, L_0x2e21f70, L_0x2e220d0, C4<1>, C4<1>; +L_0x2e21eb0 .delay 1 (30000,30000,30000) L_0x2e21eb0/d; +v0x2cabd80_0 .net *"_s0", 0 0, L_0x2e21f70; 1 drivers +v0x2cabe60_0 .net *"_s1", 0 0, L_0x2e220d0; 1 drivers +S_0x2cabf40 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cac1a0 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e22210/d .functor AND 1, L_0x2e222d0, L_0x2e22540, C4<1>, C4<1>; +L_0x2e22210 .delay 1 (30000,30000,30000) L_0x2e22210/d; +v0x2cac260_0 .net *"_s0", 0 0, L_0x2e222d0; 1 drivers +v0x2cac340_0 .net *"_s1", 0 0, L_0x2e22540; 1 drivers +S_0x2cac420 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cac630 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e22640/d .functor AND 1, L_0x2e226b0, L_0x2e22810, C4<1>, C4<1>; +L_0x2e22640 .delay 1 (30000,30000,30000) L_0x2e22640/d; +v0x2cac6f0_0 .net *"_s0", 0 0, L_0x2e226b0; 1 drivers +v0x2cac7d0_0 .net *"_s1", 0 0, L_0x2e22810; 1 drivers +S_0x2cac8b0 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cacac0 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e22970/d .functor AND 1, L_0x2e22a30, L_0x2e22b90, C4<1>, C4<1>; +L_0x2e22970 .delay 1 (30000,30000,30000) L_0x2e22970/d; +v0x2cacb80_0 .net *"_s0", 0 0, L_0x2e22a30; 1 drivers +v0x2cacc60_0 .net *"_s1", 0 0, L_0x2e22b90; 1 drivers +S_0x2cacd40 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2caaa90; + .timescale -9 -12; +P_0x2cacf50 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e22900/d .functor AND 1, L_0x2e230c0, L_0x2e232b0, C4<1>, C4<1>; +L_0x2e22900 .delay 1 (30000,30000,30000) L_0x2e22900/d; +v0x2cad010_0 .net *"_s0", 0 0, L_0x2e230c0; 1 drivers +v0x2cad0f0_0 .net *"_s1", 0 0, L_0x2e232b0; 1 drivers +S_0x2cadcb0 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2caa840; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1330900/d .functor OR 1, L_0x13309c0, L_0x1330b70, C4<0>, C4<0>; -L_0x1330900 .delay 1 (30000,30000,30000) L_0x1330900/d; -v0x11d4f70_0 .net *"_s10", 0 0, L_0x13309c0; 1 drivers -v0x11d5050_0 .net *"_s12", 0 0, L_0x1330b70; 1 drivers -v0x11d5130_0 .net "in", 7 0, L_0x132e900; alias, 1 drivers -v0x11d5200_0 .net "ors", 1 0, L_0x1330720; 1 drivers -v0x11d52c0_0 .net "out", 0 0, L_0x1330900; alias, 1 drivers -L_0x132faf0 .part L_0x132e900, 0, 4; -L_0x1330720 .concat8 [ 1 1 0 0], L_0x132f7e0, L_0x1330410; -L_0x1330860 .part L_0x132e900, 4, 4; -L_0x13309c0 .part L_0x1330720, 0, 1; -L_0x1330b70 .part L_0x1330720, 1, 1; -S_0x11d35e0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11d3420; +L_0x2e24d00/d .functor OR 1, L_0x2e24dc0, L_0x2e24f70, C4<0>, C4<0>; +L_0x2e24d00 .delay 1 (30000,30000,30000) L_0x2e24d00/d; +v0x2caf800_0 .net *"_s10", 0 0, L_0x2e24dc0; 1 drivers +v0x2caf8e0_0 .net *"_s12", 0 0, L_0x2e24f70; 1 drivers +v0x2caf9c0_0 .net "in", 7 0, L_0x2e22d00; alias, 1 drivers +v0x2cafa90_0 .net "ors", 1 0, L_0x2e24b20; 1 drivers +v0x2cafb50_0 .net "out", 0 0, L_0x2e24d00; alias, 1 drivers +L_0x2e23ef0 .part L_0x2e22d00, 0, 4; +L_0x2e24b20 .concat8 [ 1 1 0 0], L_0x2e23be0, L_0x2e24810; +L_0x2e24c60 .part L_0x2e22d00, 4, 4; +L_0x2e24dc0 .part L_0x2e24b20, 0, 1; +L_0x2e24f70 .part L_0x2e24b20, 1, 1; +S_0x2cade70 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2cadcb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x132efa0/d .functor OR 1, L_0x132f060, L_0x132f1c0, C4<0>, C4<0>; -L_0x132efa0 .delay 1 (30000,30000,30000) L_0x132efa0/d; -L_0x132f3f0/d .functor OR 1, L_0x132f500, L_0x132f660, C4<0>, C4<0>; -L_0x132f3f0 .delay 1 (30000,30000,30000) L_0x132f3f0/d; -L_0x132f7e0/d .functor OR 1, L_0x132f850, L_0x132fa00, C4<0>, C4<0>; -L_0x132f7e0 .delay 1 (30000,30000,30000) L_0x132f7e0/d; -v0x11d3830_0 .net *"_s0", 0 0, L_0x132efa0; 1 drivers -v0x11d3930_0 .net *"_s10", 0 0, L_0x132f500; 1 drivers -v0x11d3a10_0 .net *"_s12", 0 0, L_0x132f660; 1 drivers -v0x11d3ad0_0 .net *"_s14", 0 0, L_0x132f850; 1 drivers -v0x11d3bb0_0 .net *"_s16", 0 0, L_0x132fa00; 1 drivers -v0x11d3ce0_0 .net *"_s3", 0 0, L_0x132f060; 1 drivers -v0x11d3dc0_0 .net *"_s5", 0 0, L_0x132f1c0; 1 drivers -v0x11d3ea0_0 .net *"_s6", 0 0, L_0x132f3f0; 1 drivers -v0x11d3f80_0 .net "in", 3 0, L_0x132faf0; 1 drivers -v0x11d40f0_0 .net "ors", 1 0, L_0x132f300; 1 drivers -v0x11d41d0_0 .net "out", 0 0, L_0x132f7e0; 1 drivers -L_0x132f060 .part L_0x132faf0, 0, 1; -L_0x132f1c0 .part L_0x132faf0, 1, 1; -L_0x132f300 .concat8 [ 1 1 0 0], L_0x132efa0, L_0x132f3f0; -L_0x132f500 .part L_0x132faf0, 2, 1; -L_0x132f660 .part L_0x132faf0, 3, 1; -L_0x132f850 .part L_0x132f300, 0, 1; -L_0x132fa00 .part L_0x132f300, 1, 1; -S_0x11d42f0 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11d3420; +L_0x2e233a0/d .functor OR 1, L_0x2e23460, L_0x2e235c0, C4<0>, C4<0>; +L_0x2e233a0 .delay 1 (30000,30000,30000) L_0x2e233a0/d; +L_0x2e237f0/d .functor OR 1, L_0x2e23900, L_0x2e23a60, C4<0>, C4<0>; +L_0x2e237f0 .delay 1 (30000,30000,30000) L_0x2e237f0/d; +L_0x2e23be0/d .functor OR 1, L_0x2e23c50, L_0x2e23e00, C4<0>, C4<0>; +L_0x2e23be0 .delay 1 (30000,30000,30000) L_0x2e23be0/d; +v0x2cae0c0_0 .net *"_s0", 0 0, L_0x2e233a0; 1 drivers +v0x2cae1c0_0 .net *"_s10", 0 0, L_0x2e23900; 1 drivers +v0x2cae2a0_0 .net *"_s12", 0 0, L_0x2e23a60; 1 drivers +v0x2cae360_0 .net *"_s14", 0 0, L_0x2e23c50; 1 drivers +v0x2cae440_0 .net *"_s16", 0 0, L_0x2e23e00; 1 drivers +v0x2cae570_0 .net *"_s3", 0 0, L_0x2e23460; 1 drivers +v0x2cae650_0 .net *"_s5", 0 0, L_0x2e235c0; 1 drivers +v0x2cae730_0 .net *"_s6", 0 0, L_0x2e237f0; 1 drivers +v0x2cae810_0 .net "in", 3 0, L_0x2e23ef0; 1 drivers +v0x2cae980_0 .net "ors", 1 0, L_0x2e23700; 1 drivers +v0x2caea60_0 .net "out", 0 0, L_0x2e23be0; 1 drivers +L_0x2e23460 .part L_0x2e23ef0, 0, 1; +L_0x2e235c0 .part L_0x2e23ef0, 1, 1; +L_0x2e23700 .concat8 [ 1 1 0 0], L_0x2e233a0, L_0x2e237f0; +L_0x2e23900 .part L_0x2e23ef0, 2, 1; +L_0x2e23a60 .part L_0x2e23ef0, 3, 1; +L_0x2e23c50 .part L_0x2e23700, 0, 1; +L_0x2e23e00 .part L_0x2e23700, 1, 1; +S_0x2caeb80 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2cadcb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x132fc20/d .functor OR 1, L_0x132fc90, L_0x132fdf0, C4<0>, C4<0>; -L_0x132fc20 .delay 1 (30000,30000,30000) L_0x132fc20/d; -L_0x1330020/d .functor OR 1, L_0x1330130, L_0x1330290, C4<0>, C4<0>; -L_0x1330020 .delay 1 (30000,30000,30000) L_0x1330020/d; -L_0x1330410/d .functor OR 1, L_0x1330480, L_0x1330630, C4<0>, C4<0>; -L_0x1330410 .delay 1 (30000,30000,30000) L_0x1330410/d; -v0x11d44b0_0 .net *"_s0", 0 0, L_0x132fc20; 1 drivers -v0x11d45b0_0 .net *"_s10", 0 0, L_0x1330130; 1 drivers -v0x11d4690_0 .net *"_s12", 0 0, L_0x1330290; 1 drivers -v0x11d4750_0 .net *"_s14", 0 0, L_0x1330480; 1 drivers -v0x11d4830_0 .net *"_s16", 0 0, L_0x1330630; 1 drivers -v0x11d4960_0 .net *"_s3", 0 0, L_0x132fc90; 1 drivers -v0x11d4a40_0 .net *"_s5", 0 0, L_0x132fdf0; 1 drivers -v0x11d4b20_0 .net *"_s6", 0 0, L_0x1330020; 1 drivers -v0x11d4c00_0 .net "in", 3 0, L_0x1330860; 1 drivers -v0x11d4d70_0 .net "ors", 1 0, L_0x132ff30; 1 drivers -v0x11d4e50_0 .net "out", 0 0, L_0x1330410; 1 drivers -L_0x132fc90 .part L_0x1330860, 0, 1; -L_0x132fdf0 .part L_0x1330860, 1, 1; -L_0x132ff30 .concat8 [ 1 1 0 0], L_0x132fc20, L_0x1330020; -L_0x1330130 .part L_0x1330860, 2, 1; -L_0x1330290 .part L_0x1330860, 3, 1; -L_0x1330480 .part L_0x132ff30, 0, 1; -L_0x1330630 .part L_0x132ff30, 1, 1; -S_0x11d5760 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11c90e0; +L_0x2e24020/d .functor OR 1, L_0x2e24090, L_0x2e241f0, C4<0>, C4<0>; +L_0x2e24020 .delay 1 (30000,30000,30000) L_0x2e24020/d; +L_0x2e24420/d .functor OR 1, L_0x2e24530, L_0x2e24690, C4<0>, C4<0>; +L_0x2e24420 .delay 1 (30000,30000,30000) L_0x2e24420/d; +L_0x2e24810/d .functor OR 1, L_0x2e24880, L_0x2e24a30, C4<0>, C4<0>; +L_0x2e24810 .delay 1 (30000,30000,30000) L_0x2e24810/d; +v0x2caed40_0 .net *"_s0", 0 0, L_0x2e24020; 1 drivers +v0x2caee40_0 .net *"_s10", 0 0, L_0x2e24530; 1 drivers +v0x2caef20_0 .net *"_s12", 0 0, L_0x2e24690; 1 drivers +v0x2caefe0_0 .net *"_s14", 0 0, L_0x2e24880; 1 drivers +v0x2caf0c0_0 .net *"_s16", 0 0, L_0x2e24a30; 1 drivers +v0x2caf1f0_0 .net *"_s3", 0 0, L_0x2e24090; 1 drivers +v0x2caf2d0_0 .net *"_s5", 0 0, L_0x2e241f0; 1 drivers +v0x2caf3b0_0 .net *"_s6", 0 0, L_0x2e24420; 1 drivers +v0x2caf490_0 .net "in", 3 0, L_0x2e24c60; 1 drivers +v0x2caf600_0 .net "ors", 1 0, L_0x2e24330; 1 drivers +v0x2caf6e0_0 .net "out", 0 0, L_0x2e24810; 1 drivers +L_0x2e24090 .part L_0x2e24c60, 0, 1; +L_0x2e241f0 .part L_0x2e24c60, 1, 1; +L_0x2e24330 .concat8 [ 1 1 0 0], L_0x2e24020, L_0x2e24420; +L_0x2e24530 .part L_0x2e24c60, 2, 1; +L_0x2e24690 .part L_0x2e24c60, 3, 1; +L_0x2e24880 .part L_0x2e24330, 0, 1; +L_0x2e24a30 .part L_0x2e24330, 1, 1; +S_0x2cafff0 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2ca3960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -16550,80 +17513,80 @@ S_0x11d5760 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11c90e0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x132c1b0/d .functor XNOR 1, L_0x13347a0, L_0x1295ce0, C4<0>, C4<0>; -L_0x132c1b0 .delay 1 (20000,20000,20000) L_0x132c1b0/d; -L_0x132c420/d .functor AND 1, L_0x13347a0, L_0x132b0a0, C4<1>, C4<1>; -L_0x132c420 .delay 1 (30000,30000,30000) L_0x132c420/d; -L_0x132c490/d .functor AND 1, L_0x132c1b0, L_0x132acd0, C4<1>, C4<1>; -L_0x132c490 .delay 1 (30000,30000,30000) L_0x132c490/d; -L_0x132c5f0/d .functor OR 1, L_0x132c490, L_0x132c420, C4<0>, C4<0>; -L_0x132c5f0 .delay 1 (30000,30000,30000) L_0x132c5f0/d; -v0x11d5a10_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers -v0x11d5b00_0 .net "a_", 0 0, L_0x13212d0; alias, 1 drivers -v0x11d5bc0_0 .net "b", 0 0, L_0x1295ce0; alias, 1 drivers -v0x11d5cb0_0 .net "b_", 0 0, L_0x132b0a0; alias, 1 drivers -v0x11d5d50_0 .net "carryin", 0 0, L_0x132acd0; alias, 1 drivers -v0x11d5e90_0 .net "eq", 0 0, L_0x132c1b0; 1 drivers -v0x11d5f50_0 .net "lt", 0 0, L_0x132c420; 1 drivers -v0x11d6010_0 .net "out", 0 0, L_0x132c5f0; 1 drivers -v0x11d60d0_0 .net "w0", 0 0, L_0x132c490; 1 drivers -S_0x11d6320 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11c90e0; +L_0x2e1fab0/d .functor XNOR 1, L_0x2e28ba0, L_0x2d7dcf0, C4<0>, C4<0>; +L_0x2e1fab0 .delay 1 (20000,20000,20000) L_0x2e1fab0/d; +L_0x2e1fc30/d .functor AND 1, L_0x2e28ba0, L_0x2e1e7f0, C4<1>, C4<1>; +L_0x2e1fc30 .delay 1 (30000,30000,30000) L_0x2e1fc30/d; +L_0x2e1fd90/d .functor AND 1, L_0x2e1fab0, L_0x2e1e470, C4<1>, C4<1>; +L_0x2e1fd90 .delay 1 (30000,30000,30000) L_0x2e1fd90/d; +L_0x2e1fea0/d .functor OR 1, L_0x2e1fd90, L_0x2e1fc30, C4<0>, C4<0>; +L_0x2e1fea0 .delay 1 (30000,30000,30000) L_0x2e1fea0/d; +v0x2cb02a0_0 .net "a", 0 0, L_0x2e28ba0; alias, 1 drivers +v0x2cb0390_0 .net "a_", 0 0, L_0x2e13f20; alias, 1 drivers +v0x2cb0450_0 .net "b", 0 0, L_0x2d7dcf0; alias, 1 drivers +v0x2cb0540_0 .net "b_", 0 0, L_0x2e1e7f0; alias, 1 drivers +v0x2cb05e0_0 .net "carryin", 0 0, L_0x2e1e470; alias, 1 drivers +v0x2cb0720_0 .net "eq", 0 0, L_0x2e1fab0; 1 drivers +v0x2cb07e0_0 .net "lt", 0 0, L_0x2e1fc30; 1 drivers +v0x2cb08a0_0 .net "out", 0 0, L_0x2e1fea0; 1 drivers +v0x2cb0960_0 .net "w0", 0 0, L_0x2e1fd90; 1 drivers +S_0x2cb0bb0 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2ca3960; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x132bf90/d .functor OR 1, L_0x132ba90, L_0x11d7580, C4<0>, C4<0>; -L_0x132bf90 .delay 1 (30000,30000,30000) L_0x132bf90/d; -v0x11d7110_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers -v0x11d7260_0 .net "b", 0 0, L_0x132b0a0; alias, 1 drivers -v0x11d7320_0 .net "c1", 0 0, L_0x132ba90; 1 drivers -v0x11d73c0_0 .net "c2", 0 0, L_0x11d7580; 1 drivers -v0x11d7490_0 .net "carryin", 0 0, L_0x132acd0; alias, 1 drivers -v0x11d7610_0 .net "carryout", 0 0, L_0x132bf90; 1 drivers -v0x11d76b0_0 .net "s1", 0 0, L_0x132b9d0; 1 drivers -v0x11d7750_0 .net "sum", 0 0, L_0x132bbf0; 1 drivers -S_0x11d6570 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11d6320; +L_0x2e1f690/d .functor OR 1, L_0x2e1f190, L_0x2cb1e10, C4<0>, C4<0>; +L_0x2e1f690 .delay 1 (30000,30000,30000) L_0x2e1f690/d; +v0x2cb19a0_0 .net "a", 0 0, L_0x2e28ba0; alias, 1 drivers +v0x2cb1af0_0 .net "b", 0 0, L_0x2e1e7f0; alias, 1 drivers +v0x2cb1bb0_0 .net "c1", 0 0, L_0x2e1f190; 1 drivers +v0x2cb1c50_0 .net "c2", 0 0, L_0x2cb1e10; 1 drivers +v0x2cb1d20_0 .net "carryin", 0 0, L_0x2e1e470; alias, 1 drivers +v0x2cb1ea0_0 .net "carryout", 0 0, L_0x2e1f690; 1 drivers +v0x2cb1f40_0 .net "s1", 0 0, L_0x2e1f0d0; 1 drivers +v0x2cb1fe0_0 .net "sum", 0 0, L_0x2e1f2f0; 1 drivers +S_0x2cb0e00 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2cb0bb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x132b9d0/d .functor XOR 1, L_0x13347a0, L_0x132b0a0, C4<0>, C4<0>; -L_0x132b9d0 .delay 1 (30000,30000,30000) L_0x132b9d0/d; -L_0x132ba90/d .functor AND 1, L_0x13347a0, L_0x132b0a0, C4<1>, C4<1>; -L_0x132ba90 .delay 1 (30000,30000,30000) L_0x132ba90/d; -v0x11d67d0_0 .net "a", 0 0, L_0x13347a0; alias, 1 drivers -v0x11d6890_0 .net "b", 0 0, L_0x132b0a0; alias, 1 drivers -v0x11d6950_0 .net "carryout", 0 0, L_0x132ba90; alias, 1 drivers -v0x11d69f0_0 .net "sum", 0 0, L_0x132b9d0; alias, 1 drivers -S_0x11d6b20 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11d6320; +L_0x2e1f0d0/d .functor XOR 1, L_0x2e28ba0, L_0x2e1e7f0, C4<0>, C4<0>; +L_0x2e1f0d0 .delay 1 (30000,30000,30000) L_0x2e1f0d0/d; +L_0x2e1f190/d .functor AND 1, L_0x2e28ba0, L_0x2e1e7f0, C4<1>, C4<1>; +L_0x2e1f190 .delay 1 (30000,30000,30000) L_0x2e1f190/d; +v0x2cb1060_0 .net "a", 0 0, L_0x2e28ba0; alias, 1 drivers +v0x2cb1120_0 .net "b", 0 0, L_0x2e1e7f0; alias, 1 drivers +v0x2cb11e0_0 .net "carryout", 0 0, L_0x2e1f190; alias, 1 drivers +v0x2cb1280_0 .net "sum", 0 0, L_0x2e1f0d0; alias, 1 drivers +S_0x2cb13b0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2cb0bb0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x132bbf0/d .functor XOR 1, L_0x132b9d0, L_0x132acd0, C4<0>, C4<0>; -L_0x132bbf0 .delay 1 (30000,30000,30000) L_0x132bbf0/d; -L_0x11d7580/d .functor AND 1, L_0x132b9d0, L_0x132acd0, C4<1>, C4<1>; -L_0x11d7580 .delay 1 (30000,30000,30000) L_0x11d7580/d; -v0x11d6d80_0 .net "a", 0 0, L_0x132b9d0; alias, 1 drivers -v0x11d6e50_0 .net "b", 0 0, L_0x132acd0; alias, 1 drivers -v0x11d6ef0_0 .net "carryout", 0 0, L_0x11d7580; alias, 1 drivers -v0x11d6fc0_0 .net "sum", 0 0, L_0x132bbf0; alias, 1 drivers -S_0x11d8b70 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11c8e10; - .timescale -9 -12; -L_0x2b0ab3d071d8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d07220 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1334840/d .functor OR 1, L_0x2b0ab3d071d8, L_0x2b0ab3d07220, C4<0>, C4<0>; -L_0x1334840 .delay 1 (30000,30000,30000) L_0x1334840/d; -v0x11d8d60_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d071d8; 1 drivers -v0x11d8e40_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d07220; 1 drivers -S_0x11d8f20 .scope generate, "alu_slices[31]" "alu_slices[31]" 3 41, 3 41 0, S_0xf2fc10; - .timescale -9 -12; -P_0x11d9130 .param/l "i" 0 3 41, +C4<011111>; -S_0x11d91f0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11d8f20; +L_0x2e1f2f0/d .functor XOR 1, L_0x2e1f0d0, L_0x2e1e470, C4<0>, C4<0>; +L_0x2e1f2f0 .delay 1 (30000,30000,30000) L_0x2e1f2f0/d; +L_0x2cb1e10/d .functor AND 1, L_0x2e1f0d0, L_0x2e1e470, C4<1>, C4<1>; +L_0x2cb1e10 .delay 1 (30000,30000,30000) L_0x2cb1e10/d; +v0x2cb1610_0 .net "a", 0 0, L_0x2e1f0d0; alias, 1 drivers +v0x2cb16e0_0 .net "b", 0 0, L_0x2e1e470; alias, 1 drivers +v0x2cb1780_0 .net "carryout", 0 0, L_0x2cb1e10; alias, 1 drivers +v0x2cb1850_0 .net "sum", 0 0, L_0x2e1f2f0; alias, 1 drivers +S_0x2cb4070 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2ca3690; + .timescale -9 -12; +L_0x2ac6110bd908 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd950 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e28c40/d .functor OR 1, L_0x2ac6110bd908, L_0x2ac6110bd950, C4<0>, C4<0>; +L_0x2e28c40 .delay 1 (30000,30000,30000) L_0x2e28c40/d; +v0x2cb4260_0 .net/2u *"_s0", 0 0, L_0x2ac6110bd908; 1 drivers +v0x2cb4340_0 .net/2u *"_s2", 0 0, L_0x2ac6110bd950; 1 drivers +S_0x2cb4420 .scope generate, "alu_slices[31]" "alu_slices[31]" 3 39, 3 39 0, S_0x26b20c0; + .timescale -9 -12; +P_0x2cb4630 .param/l "i" 0 3 39, +C4<011111>; +S_0x2cb46f0 .scope module, "alu1_inst" "alu1" 3 40, 4 142 0, S_0x2cb4420; .timescale -9 -12; .port_info 0 /OUTPUT 1 "result" .port_info 1 /OUTPUT 1 "carryout" @@ -16632,445 +17595,476 @@ S_0x11d91f0 .scope module, "alu1_inst" "alu1" 3 42, 4 142 0, S_0x11d8f20; .port_info 4 /INPUT 1 "B" .port_info 5 /INPUT 1 "carryin" .port_info 6 /INPUT 8 "command" -L_0x1296070/d .functor NOT 1, L_0x133f6b0, C4<0>, C4<0>, C4<0>; -L_0x1296070 .delay 1 (10000,10000,10000) L_0x1296070/d; -L_0x132ae60/d .functor NOT 1, L_0x133eaa0, C4<0>, C4<0>, C4<0>; -L_0x132ae60 .delay 1 (10000,10000,10000) L_0x132ae60/d; -L_0x13360a0/d .functor XOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; -L_0x13360a0 .delay 1 (30000,30000,30000) L_0x13360a0/d; -L_0x2b0ab3d07268 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d072b0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1336750/d .functor OR 1, L_0x2b0ab3d07268, L_0x2b0ab3d072b0, C4<0>, C4<0>; -L_0x1336750 .delay 1 (30000,30000,30000) L_0x1336750/d; -L_0x1336950/d .functor AND 1, L_0x133f6b0, L_0x133eaa0, C4<1>, C4<1>; -L_0x1336950 .delay 1 (30000,30000,30000) L_0x1336950/d; -L_0x1336a10/d .functor NAND 1, L_0x133f6b0, L_0x133eaa0, C4<1>, C4<1>; -L_0x1336a10 .delay 1 (20000,20000,20000) L_0x1336a10/d; -L_0x1336b70/d .functor XOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; -L_0x1336b70 .delay 1 (20000,20000,20000) L_0x1336b70/d; -L_0x1337020/d .functor OR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; -L_0x1337020 .delay 1 (30000,30000,30000) L_0x1337020/d; -L_0x133e730/d .functor NOT 1, L_0x133a990, C4<0>, C4<0>, C4<0>; -L_0x133e730 .delay 1 (10000,10000,10000) L_0x133e730/d; -v0x11e7920_0 .net "A", 0 0, L_0x133f6b0; 1 drivers -v0x11e79e0_0 .net "A_", 0 0, L_0x1296070; 1 drivers -v0x11e7aa0_0 .net "B", 0 0, L_0x133eaa0; 1 drivers -v0x11e7b70_0 .net "B_", 0 0, L_0x132ae60; 1 drivers -v0x11e7c10_0 .net *"_s12", 0 0, L_0x1336750; 1 drivers -v0x11e7d00_0 .net/2s *"_s14", 0 0, L_0x2b0ab3d07268; 1 drivers -v0x11e7dc0_0 .net/2s *"_s16", 0 0, L_0x2b0ab3d072b0; 1 drivers -v0x11e7ea0_0 .net *"_s18", 0 0, L_0x1336950; 1 drivers -v0x11e7f80_0 .net *"_s20", 0 0, L_0x1336a10; 1 drivers -v0x11e80f0_0 .net *"_s22", 0 0, L_0x1336b70; 1 drivers -v0x11e81d0_0 .net *"_s24", 0 0, L_0x1337020; 1 drivers -L_0x2b0ab3d07388 .functor BUFT 1, C4, C4<0>, C4<0>, C4<0>; -v0x11e82b0_0 .net *"_s30", 0 0, L_0x2b0ab3d07388; 1 drivers -o0x2b0ab3cee7a8 .functor BUFZ 4, C4; HiZ drive -; Elide local net with no drivers, v0x11e8390_0 name=_s32 -v0x11e8470_0 .net *"_s8", 0 0, L_0x13360a0; 1 drivers -v0x11e8550_0 .net "carryin", 0 0, L_0x133eb40; 1 drivers -v0x11e85f0_0 .net "carryout", 0 0, L_0x133e3d0; 1 drivers -v0x11e8690_0 .net "carryouts", 7 0, L_0x1356450; 1 drivers -v0x11e8840_0 .net "command", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11e88e0_0 .net "result", 0 0, L_0x133a990; 1 drivers -v0x11e89d0_0 .net "results", 7 0, L_0x1336df0; 1 drivers -v0x11e8ae0_0 .net "zero", 0 0, L_0x133e730; 1 drivers -LS_0x1336df0_0_0 .concat8 [ 1 1 1 1], L_0x1335570, L_0x1335ba0, L_0x13360a0, L_0x1336750; -LS_0x1336df0_0_4 .concat8 [ 1 1 1 1], L_0x1336950, L_0x1336a10, L_0x1336b70, L_0x1337020; -L_0x1336df0 .concat8 [ 4 4 0 0], LS_0x1336df0_0_0, LS_0x1336df0_0_4; -LS_0x1356450_0_0 .concat [ 1 1 1 1], L_0x1335820, L_0x1335f40, L_0x2b0ab3d07388, L_0x13365a0; -LS_0x1356450_0_4 .concat [ 4 0 0 0], o0x2b0ab3cee7a8; -L_0x1356450 .concat [ 4 4 0 0], LS_0x1356450_0_0, LS_0x1356450_0_4; -S_0x11d9470 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x11d91f0; +L_0x2e1ec50/d .functor NOT 1, L_0x2e346b0, C4<0>, C4<0>, C4<0>; +L_0x2e1ec50 .delay 1 (10000,10000,10000) L_0x2e1ec50/d; +L_0x2e1e560/d .functor NOT 1, L_0x2e33aa0, C4<0>, C4<0>, C4<0>; +L_0x2e1e560 .delay 1 (10000,10000,10000) L_0x2e1e560/d; +L_0x2e2a460/d .functor XOR 1, L_0x2e346b0, L_0x2e33aa0, C4<0>, C4<0>; +L_0x2e2a460 .delay 1 (30000,30000,30000) L_0x2e2a460/d; +L_0x2ac6110bd998 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bd9e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e2a520/d .functor OR 1, L_0x2ac6110bd998, L_0x2ac6110bd9e0, C4<0>, C4<0>; +L_0x2e2a520 .delay 1 (30000,30000,30000) L_0x2e2a520/d; +L_0x2ac6110bda28 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bda70 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e2acc0/d .functor OR 1, L_0x2ac6110bda28, L_0x2ac6110bda70, C4<0>, C4<0>; +L_0x2e2acc0 .delay 1 (30000,30000,30000) L_0x2e2acc0/d; +L_0x2e2aec0/d .functor AND 1, L_0x2e346b0, L_0x2e33aa0, C4<1>, C4<1>; +L_0x2e2aec0 .delay 1 (30000,30000,30000) L_0x2e2aec0/d; +L_0x2ac6110bdab8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bdb00 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e2af80/d .functor OR 1, L_0x2ac6110bdab8, L_0x2ac6110bdb00, C4<0>, C4<0>; +L_0x2e2af80 .delay 1 (30000,30000,30000) L_0x2e2af80/d; +L_0x2e2b180/d .functor NAND 1, L_0x2e346b0, L_0x2e33aa0, C4<1>, C4<1>; +L_0x2e2b180 .delay 1 (20000,20000,20000) L_0x2e2b180/d; +L_0x2ac6110bdb48 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bdb90 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e2b290/d .functor OR 1, L_0x2ac6110bdb48, L_0x2ac6110bdb90, C4<0>, C4<0>; +L_0x2e2b290 .delay 1 (30000,30000,30000) L_0x2e2b290/d; +L_0x2e2b440/d .functor NOR 1, L_0x2e346b0, L_0x2e33aa0, C4<0>, C4<0>; +L_0x2e2b440 .delay 1 (20000,20000,20000) L_0x2e2b440/d; +L_0x2ac6110bdbd8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bdc20 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e2b710/d .functor OR 1, L_0x2ac6110bdbd8, L_0x2ac6110bdc20, C4<0>, C4<0>; +L_0x2e2b710 .delay 1 (30000,30000,30000) L_0x2e2b710/d; +L_0x2e2bb10/d .functor OR 1, L_0x2e346b0, L_0x2e33aa0, C4<0>, C4<0>; +L_0x2e2bb10 .delay 1 (30000,30000,30000) L_0x2e2bb10/d; +L_0x2ac6110bdc68 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bdcb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e2bfb0/d .functor OR 1, L_0x2ac6110bdc68, L_0x2ac6110bdcb0, C4<0>, C4<0>; +L_0x2e2bfb0 .delay 1 (30000,30000,30000) L_0x2e2bfb0/d; +L_0x2e33730/d .functor NOT 1, L_0x2e2f8b0, C4<0>, C4<0>, C4<0>; +L_0x2e33730 .delay 1 (10000,10000,10000) L_0x2e33730/d; +v0x2cc2e20_0 .net "A", 0 0, L_0x2e346b0; 1 drivers +v0x2cc2ee0_0 .net "A_", 0 0, L_0x2e1ec50; 1 drivers +v0x2cc2fa0_0 .net "B", 0 0, L_0x2e33aa0; 1 drivers +v0x2cc3070_0 .net "B_", 0 0, L_0x2e1e560; 1 drivers +v0x2cc3110_0 .net *"_s11", 0 0, L_0x2e2a520; 1 drivers +v0x2cc3200_0 .net/2s *"_s13", 0 0, L_0x2ac6110bd998; 1 drivers +v0x2cc32c0_0 .net/2s *"_s15", 0 0, L_0x2ac6110bd9e0; 1 drivers +v0x2cc33a0_0 .net *"_s19", 0 0, L_0x2e2acc0; 1 drivers +v0x2cc3480_0 .net/2s *"_s21", 0 0, L_0x2ac6110bda28; 1 drivers +v0x2cc35f0_0 .net/2s *"_s23", 0 0, L_0x2ac6110bda70; 1 drivers +v0x2cc36d0_0 .net *"_s25", 0 0, L_0x2e2aec0; 1 drivers +v0x2cc37b0_0 .net *"_s28", 0 0, L_0x2e2af80; 1 drivers +v0x2cc3890_0 .net/2s *"_s30", 0 0, L_0x2ac6110bdab8; 1 drivers +v0x2cc3970_0 .net/2s *"_s32", 0 0, L_0x2ac6110bdb00; 1 drivers +v0x2cc3a50_0 .net *"_s34", 0 0, L_0x2e2b180; 1 drivers +v0x2cc3b30_0 .net *"_s37", 0 0, L_0x2e2b290; 1 drivers +v0x2cc3c10_0 .net/2s *"_s39", 0 0, L_0x2ac6110bdb48; 1 drivers +v0x2cc3dc0_0 .net/2s *"_s41", 0 0, L_0x2ac6110bdb90; 1 drivers +v0x2cc3e60_0 .net *"_s43", 0 0, L_0x2e2b440; 1 drivers +v0x2cc3f40_0 .net *"_s46", 0 0, L_0x2e2b710; 1 drivers +v0x2cc4020_0 .net/2s *"_s48", 0 0, L_0x2ac6110bdbd8; 1 drivers +v0x2cc4100_0 .net/2s *"_s50", 0 0, L_0x2ac6110bdc20; 1 drivers +v0x2cc41e0_0 .net *"_s52", 0 0, L_0x2e2bb10; 1 drivers +v0x2cc42c0_0 .net *"_s56", 0 0, L_0x2e2bfb0; 1 drivers +v0x2cc43a0_0 .net/2s *"_s59", 0 0, L_0x2ac6110bdc68; 1 drivers +v0x2cc4480_0 .net/2s *"_s61", 0 0, L_0x2ac6110bdcb0; 1 drivers +v0x2cc4560_0 .net *"_s8", 0 0, L_0x2e2a460; 1 drivers +v0x2cc4640_0 .net "carryin", 0 0, L_0x2e33b40; 1 drivers +v0x2cc46e0_0 .net "carryout", 0 0, L_0x2e333d0; 1 drivers +v0x2cc4780_0 .net "carryouts", 7 0, L_0x2e2bc20; 1 drivers +v0x2cc4890_0 .net "command", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2cc4950_0 .net "result", 0 0, L_0x2e2f8b0; 1 drivers +v0x2cc4a40_0 .net "results", 7 0, L_0x2e2b8e0; 1 drivers +v0x2cc3d20_0 .net "zero", 0 0, L_0x2e33730; 1 drivers +LS_0x2e2b8e0_0_0 .concat8 [ 1 1 1 1], L_0x2e29930, L_0x2e29f60, L_0x2e2a460, L_0x2e2acc0; +LS_0x2e2b8e0_0_4 .concat8 [ 1 1 1 1], L_0x2e2aec0, L_0x2e2b180, L_0x2e2b440, L_0x2e2bb10; +L_0x2e2b8e0 .concat8 [ 4 4 0 0], LS_0x2e2b8e0_0_0, LS_0x2e2b8e0_0_4; +LS_0x2e2bc20_0_0 .concat8 [ 1 1 1 1], L_0x2e29be0, L_0x2e2a300, L_0x2e2a520, L_0x2e2ab10; +LS_0x2e2bc20_0_4 .concat8 [ 1 1 1 1], L_0x2e2af80, L_0x2e2b290, L_0x2e2b710, L_0x2e2bfb0; +L_0x2e2bc20 .concat8 [ 4 4 0 0], LS_0x2e2bc20_0_0, LS_0x2e2bc20_0_4; +S_0x2cb4970 .scope module, "adder" "fullAdder" 4 157, 4 85 0, S_0x2cb46f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1335820/d .functor OR 1, L_0x1335300, L_0x13356c0, C4<0>, C4<0>; -L_0x1335820 .delay 1 (30000,30000,30000) L_0x1335820/d; -v0x11da2a0_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers -v0x11da360_0 .net "b", 0 0, L_0x133eaa0; alias, 1 drivers -v0x11da430_0 .net "c1", 0 0, L_0x1335300; 1 drivers -v0x11da530_0 .net "c2", 0 0, L_0x13356c0; 1 drivers -v0x11da600_0 .net "carryin", 0 0, L_0x133eb40; alias, 1 drivers -v0x11da6f0_0 .net "carryout", 0 0, L_0x1335820; 1 drivers -v0x11da790_0 .net "s1", 0 0, L_0x1335240; 1 drivers -v0x11da880_0 .net "sum", 0 0, L_0x1335570; 1 drivers -S_0x11d96e0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11d9470; +L_0x2e29be0/d .functor OR 1, L_0x2e296c0, L_0x2e29a80, C4<0>, C4<0>; +L_0x2e29be0 .delay 1 (30000,30000,30000) L_0x2e29be0/d; +v0x2cb57a0_0 .net "a", 0 0, L_0x2e346b0; alias, 1 drivers +v0x2cb5860_0 .net "b", 0 0, L_0x2e33aa0; alias, 1 drivers +v0x2cb5930_0 .net "c1", 0 0, L_0x2e296c0; 1 drivers +v0x2cb5a30_0 .net "c2", 0 0, L_0x2e29a80; 1 drivers +v0x2cb5b00_0 .net "carryin", 0 0, L_0x2e33b40; alias, 1 drivers +v0x2cb5bf0_0 .net "carryout", 0 0, L_0x2e29be0; 1 drivers +v0x2cb5c90_0 .net "s1", 0 0, L_0x2e29600; 1 drivers +v0x2cb5d80_0 .net "sum", 0 0, L_0x2e29930; 1 drivers +S_0x2cb4be0 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2cb4970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1335240/d .functor XOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; -L_0x1335240 .delay 1 (30000,30000,30000) L_0x1335240/d; -L_0x1335300/d .functor AND 1, L_0x133f6b0, L_0x133eaa0, C4<1>, C4<1>; -L_0x1335300 .delay 1 (30000,30000,30000) L_0x1335300/d; -v0x11d9940_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers -v0x11d9a20_0 .net "b", 0 0, L_0x133eaa0; alias, 1 drivers -v0x11d9ae0_0 .net "carryout", 0 0, L_0x1335300; alias, 1 drivers -v0x11d9b80_0 .net "sum", 0 0, L_0x1335240; alias, 1 drivers -S_0x11d9cc0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11d9470; +L_0x2e29600/d .functor XOR 1, L_0x2e346b0, L_0x2e33aa0, C4<0>, C4<0>; +L_0x2e29600 .delay 1 (30000,30000,30000) L_0x2e29600/d; +L_0x2e296c0/d .functor AND 1, L_0x2e346b0, L_0x2e33aa0, C4<1>, C4<1>; +L_0x2e296c0 .delay 1 (30000,30000,30000) L_0x2e296c0/d; +v0x2cb4e40_0 .net "a", 0 0, L_0x2e346b0; alias, 1 drivers +v0x2cb4f20_0 .net "b", 0 0, L_0x2e33aa0; alias, 1 drivers +v0x2cb4fe0_0 .net "carryout", 0 0, L_0x2e296c0; alias, 1 drivers +v0x2cb5080_0 .net "sum", 0 0, L_0x2e29600; alias, 1 drivers +S_0x2cb51c0 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2cb4970; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1335570/d .functor XOR 1, L_0x1335240, L_0x133eb40, C4<0>, C4<0>; -L_0x1335570 .delay 1 (30000,30000,30000) L_0x1335570/d; -L_0x13356c0/d .functor AND 1, L_0x1335240, L_0x133eb40, C4<1>, C4<1>; -L_0x13356c0 .delay 1 (30000,30000,30000) L_0x13356c0/d; -v0x11d9f20_0 .net "a", 0 0, L_0x1335240; alias, 1 drivers -v0x11d9fc0_0 .net "b", 0 0, L_0x133eb40; alias, 1 drivers -v0x11da060_0 .net "carryout", 0 0, L_0x13356c0; alias, 1 drivers -v0x11da130_0 .net "sum", 0 0, L_0x1335570; alias, 1 drivers -S_0x11da950 .scope module, "cMux" "unaryMultiplexor" 4 171, 4 69 0, S_0x11d91f0; +L_0x2e29930/d .functor XOR 1, L_0x2e29600, L_0x2e33b40, C4<0>, C4<0>; +L_0x2e29930 .delay 1 (30000,30000,30000) L_0x2e29930/d; +L_0x2e29a80/d .functor AND 1, L_0x2e29600, L_0x2e33b40, C4<1>, C4<1>; +L_0x2e29a80 .delay 1 (30000,30000,30000) L_0x2e29a80/d; +v0x2cb5420_0 .net "a", 0 0, L_0x2e29600; alias, 1 drivers +v0x2cb54c0_0 .net "b", 0 0, L_0x2e33b40; alias, 1 drivers +v0x2cb5560_0 .net "carryout", 0 0, L_0x2e29a80; alias, 1 drivers +v0x2cb5630_0 .net "sum", 0 0, L_0x2e29930; alias, 1 drivers +S_0x2cb5e50 .scope module, "cMux" "unaryMultiplexor" 4 176, 4 69 0, S_0x2cb46f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11dfd40_0 .net "ands", 7 0, L_0x133c3d0; 1 drivers -v0x11dfe50_0 .net "in", 7 0, L_0x1356450; alias, 1 drivers -v0x11dff10_0 .net "out", 0 0, L_0x133e3d0; alias, 1 drivers -v0x11dffe0_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11dab70 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11da950; +v0x2cbb240_0 .net "ands", 7 0, L_0x2e313d0; 1 drivers +v0x2cbb350_0 .net "in", 7 0, L_0x2e2bc20; alias, 1 drivers +v0x2cbb410_0 .net "out", 0 0, L_0x2e333d0; alias, 1 drivers +v0x2cbb4e0_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2cb6070 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2cb5e50; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11dd2a0_0 .net "A", 7 0, L_0x1356450; alias, 1 drivers -v0x11dd3a0_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11dd460_0 .net *"_s0", 0 0, L_0x133acf0; 1 drivers -v0x11dd520_0 .net *"_s12", 0 0, L_0x133b660; 1 drivers -v0x11dd600_0 .net *"_s16", 0 0, L_0x133b9c0; 1 drivers -v0x11dd730_0 .net *"_s20", 0 0, L_0x133bcd0; 1 drivers -v0x11dd810_0 .net *"_s24", 0 0, L_0x133c0c0; 1 drivers -v0x11dd8f0_0 .net *"_s28", 0 0, L_0x133c050; 1 drivers -v0x11dd9d0_0 .net *"_s4", 0 0, L_0x133b000; 1 drivers -v0x11ddb40_0 .net *"_s8", 0 0, L_0x133b350; 1 drivers -v0x11ddc20_0 .net "out", 7 0, L_0x133c3d0; alias, 1 drivers -L_0x133adb0 .part L_0x1356450, 0, 1; -L_0x133af10 .part v0x12010b0_0, 0, 1; -L_0x133b0c0 .part L_0x1356450, 1, 1; -L_0x133b2b0 .part v0x12010b0_0, 1, 1; -L_0x133b410 .part L_0x1356450, 2, 1; -L_0x133b570 .part v0x12010b0_0, 2, 1; -L_0x133b720 .part L_0x1356450, 3, 1; -L_0x133b880 .part v0x12010b0_0, 3, 1; -L_0x133ba80 .part L_0x1356450, 4, 1; -L_0x133bbe0 .part v0x12010b0_0, 4, 1; -L_0x133bd40 .part L_0x1356450, 5, 1; -L_0x133bfb0 .part v0x12010b0_0, 5, 1; -L_0x133c180 .part L_0x1356450, 6, 1; -L_0x133c2e0 .part v0x12010b0_0, 6, 1; -LS_0x133c3d0_0_0 .concat8 [ 1 1 1 1], L_0x133acf0, L_0x133b000, L_0x133b350, L_0x133b660; -LS_0x133c3d0_0_4 .concat8 [ 1 1 1 1], L_0x133b9c0, L_0x133bcd0, L_0x133c0c0, L_0x133c050; -L_0x133c3d0 .concat8 [ 4 4 0 0], LS_0x133c3d0_0_0, LS_0x133c3d0_0_4; -L_0x133c790 .part L_0x1356450, 7, 1; -L_0x133c980 .part v0x12010b0_0, 7, 1; -S_0x11dadd0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11dafe0 .param/l "i" 0 4 54, +C4<00>; -L_0x133acf0/d .functor AND 1, L_0x133adb0, L_0x133af10, C4<1>, C4<1>; -L_0x133acf0 .delay 1 (30000,30000,30000) L_0x133acf0/d; -v0x11db0c0_0 .net *"_s0", 0 0, L_0x133adb0; 1 drivers -v0x11db1a0_0 .net *"_s1", 0 0, L_0x133af10; 1 drivers -S_0x11db280 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11db490 .param/l "i" 0 4 54, +C4<01>; -L_0x133b000/d .functor AND 1, L_0x133b0c0, L_0x133b2b0, C4<1>, C4<1>; -L_0x133b000 .delay 1 (30000,30000,30000) L_0x133b000/d; -v0x11db550_0 .net *"_s0", 0 0, L_0x133b0c0; 1 drivers -v0x11db630_0 .net *"_s1", 0 0, L_0x133b2b0; 1 drivers -S_0x11db710 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11db920 .param/l "i" 0 4 54, +C4<010>; -L_0x133b350/d .functor AND 1, L_0x133b410, L_0x133b570, C4<1>, C4<1>; -L_0x133b350 .delay 1 (30000,30000,30000) L_0x133b350/d; -v0x11db9c0_0 .net *"_s0", 0 0, L_0x133b410; 1 drivers -v0x11dbaa0_0 .net *"_s1", 0 0, L_0x133b570; 1 drivers -S_0x11dbb80 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11dbd90 .param/l "i" 0 4 54, +C4<011>; -L_0x133b660/d .functor AND 1, L_0x133b720, L_0x133b880, C4<1>, C4<1>; -L_0x133b660 .delay 1 (30000,30000,30000) L_0x133b660/d; -v0x11dbe50_0 .net *"_s0", 0 0, L_0x133b720; 1 drivers -v0x11dbf30_0 .net *"_s1", 0 0, L_0x133b880; 1 drivers -S_0x11dc010 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11dc270 .param/l "i" 0 4 54, +C4<0100>; -L_0x133b9c0/d .functor AND 1, L_0x133ba80, L_0x133bbe0, C4<1>, C4<1>; -L_0x133b9c0 .delay 1 (30000,30000,30000) L_0x133b9c0/d; -v0x11dc330_0 .net *"_s0", 0 0, L_0x133ba80; 1 drivers -v0x11dc410_0 .net *"_s1", 0 0, L_0x133bbe0; 1 drivers -S_0x11dc4f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11dc700 .param/l "i" 0 4 54, +C4<0101>; -L_0x133bcd0/d .functor AND 1, L_0x133bd40, L_0x133bfb0, C4<1>, C4<1>; -L_0x133bcd0 .delay 1 (30000,30000,30000) L_0x133bcd0/d; -v0x11dc7c0_0 .net *"_s0", 0 0, L_0x133bd40; 1 drivers -v0x11dc8a0_0 .net *"_s1", 0 0, L_0x133bfb0; 1 drivers -S_0x11dc980 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11dcb90 .param/l "i" 0 4 54, +C4<0110>; -L_0x133c0c0/d .functor AND 1, L_0x133c180, L_0x133c2e0, C4<1>, C4<1>; -L_0x133c0c0 .delay 1 (30000,30000,30000) L_0x133c0c0/d; -v0x11dcc50_0 .net *"_s0", 0 0, L_0x133c180; 1 drivers -v0x11dcd30_0 .net *"_s1", 0 0, L_0x133c2e0; 1 drivers -S_0x11dce10 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11dab70; - .timescale -9 -12; -P_0x11dd020 .param/l "i" 0 4 54, +C4<0111>; -L_0x133c050/d .functor AND 1, L_0x133c790, L_0x133c980, C4<1>, C4<1>; -L_0x133c050 .delay 1 (30000,30000,30000) L_0x133c050/d; -v0x11dd0e0_0 .net *"_s0", 0 0, L_0x133c790; 1 drivers -v0x11dd1c0_0 .net *"_s1", 0 0, L_0x133c980; 1 drivers -S_0x11ddd80 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11da950; +v0x2cb87a0_0 .net "A", 7 0, L_0x2e2bc20; alias, 1 drivers +v0x2cb88a0_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2cb8960_0 .net *"_s0", 0 0, L_0x2e2fc10; 1 drivers +v0x2cb8a20_0 .net *"_s12", 0 0, L_0x2e30580; 1 drivers +v0x2cb8b00_0 .net *"_s16", 0 0, L_0x2e308e0; 1 drivers +v0x2cb8c30_0 .net *"_s20", 0 0, L_0x2e30d10; 1 drivers +v0x2cb8d10_0 .net *"_s24", 0 0, L_0x2e31040; 1 drivers +v0x2cb8df0_0 .net *"_s28", 0 0, L_0x2e30fd0; 1 drivers +v0x2cb8ed0_0 .net *"_s4", 0 0, L_0x2e2ff60; 1 drivers +v0x2cb9040_0 .net *"_s8", 0 0, L_0x2e30270; 1 drivers +v0x2cb9120_0 .net "out", 7 0, L_0x2e313d0; alias, 1 drivers +L_0x2e2fcd0 .part L_0x2e2bc20, 0, 1; +L_0x2e2fec0 .part v0x2cdd2e0_0, 0, 1; +L_0x2e30020 .part L_0x2e2bc20, 1, 1; +L_0x2e30180 .part v0x2cdd2e0_0, 1, 1; +L_0x2e30330 .part L_0x2e2bc20, 2, 1; +L_0x2e30490 .part v0x2cdd2e0_0, 2, 1; +L_0x2e30640 .part L_0x2e2bc20, 3, 1; +L_0x2e307a0 .part v0x2cdd2e0_0, 3, 1; +L_0x2e309a0 .part L_0x2e2bc20, 4, 1; +L_0x2e30c10 .part v0x2cdd2e0_0, 4, 1; +L_0x2e30d80 .part L_0x2e2bc20, 5, 1; +L_0x2e30ee0 .part v0x2cdd2e0_0, 5, 1; +L_0x2e31100 .part L_0x2e2bc20, 6, 1; +L_0x2e31260 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e313d0_0_0 .concat8 [ 1 1 1 1], L_0x2e2fc10, L_0x2e2ff60, L_0x2e30270, L_0x2e30580; +LS_0x2e313d0_0_4 .concat8 [ 1 1 1 1], L_0x2e308e0, L_0x2e30d10, L_0x2e31040, L_0x2e30fd0; +L_0x2e313d0 .concat8 [ 4 4 0 0], LS_0x2e313d0_0_0, LS_0x2e313d0_0_4; +L_0x2e31790 .part L_0x2e2bc20, 7, 1; +L_0x2e31980 .part v0x2cdd2e0_0, 7, 1; +S_0x2cb62d0 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb64e0 .param/l "i" 0 4 54, +C4<00>; +L_0x2e2fc10/d .functor AND 1, L_0x2e2fcd0, L_0x2e2fec0, C4<1>, C4<1>; +L_0x2e2fc10 .delay 1 (30000,30000,30000) L_0x2e2fc10/d; +v0x2cb65c0_0 .net *"_s0", 0 0, L_0x2e2fcd0; 1 drivers +v0x2cb66a0_0 .net *"_s1", 0 0, L_0x2e2fec0; 1 drivers +S_0x2cb6780 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb6990 .param/l "i" 0 4 54, +C4<01>; +L_0x2e2ff60/d .functor AND 1, L_0x2e30020, L_0x2e30180, C4<1>, C4<1>; +L_0x2e2ff60 .delay 1 (30000,30000,30000) L_0x2e2ff60/d; +v0x2cb6a50_0 .net *"_s0", 0 0, L_0x2e30020; 1 drivers +v0x2cb6b30_0 .net *"_s1", 0 0, L_0x2e30180; 1 drivers +S_0x2cb6c10 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb6e20 .param/l "i" 0 4 54, +C4<010>; +L_0x2e30270/d .functor AND 1, L_0x2e30330, L_0x2e30490, C4<1>, C4<1>; +L_0x2e30270 .delay 1 (30000,30000,30000) L_0x2e30270/d; +v0x2cb6ec0_0 .net *"_s0", 0 0, L_0x2e30330; 1 drivers +v0x2cb6fa0_0 .net *"_s1", 0 0, L_0x2e30490; 1 drivers +S_0x2cb7080 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb7290 .param/l "i" 0 4 54, +C4<011>; +L_0x2e30580/d .functor AND 1, L_0x2e30640, L_0x2e307a0, C4<1>, C4<1>; +L_0x2e30580 .delay 1 (30000,30000,30000) L_0x2e30580/d; +v0x2cb7350_0 .net *"_s0", 0 0, L_0x2e30640; 1 drivers +v0x2cb7430_0 .net *"_s1", 0 0, L_0x2e307a0; 1 drivers +S_0x2cb7510 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb7770 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e308e0/d .functor AND 1, L_0x2e309a0, L_0x2e30c10, C4<1>, C4<1>; +L_0x2e308e0 .delay 1 (30000,30000,30000) L_0x2e308e0/d; +v0x2cb7830_0 .net *"_s0", 0 0, L_0x2e309a0; 1 drivers +v0x2cb7910_0 .net *"_s1", 0 0, L_0x2e30c10; 1 drivers +S_0x2cb79f0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb7c00 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e30d10/d .functor AND 1, L_0x2e30d80, L_0x2e30ee0, C4<1>, C4<1>; +L_0x2e30d10 .delay 1 (30000,30000,30000) L_0x2e30d10/d; +v0x2cb7cc0_0 .net *"_s0", 0 0, L_0x2e30d80; 1 drivers +v0x2cb7da0_0 .net *"_s1", 0 0, L_0x2e30ee0; 1 drivers +S_0x2cb7e80 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb8090 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e31040/d .functor AND 1, L_0x2e31100, L_0x2e31260, C4<1>, C4<1>; +L_0x2e31040 .delay 1 (30000,30000,30000) L_0x2e31040/d; +v0x2cb8150_0 .net *"_s0", 0 0, L_0x2e31100; 1 drivers +v0x2cb8230_0 .net *"_s1", 0 0, L_0x2e31260; 1 drivers +S_0x2cb8310 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2cb6070; + .timescale -9 -12; +P_0x2cb8520 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e30fd0/d .functor AND 1, L_0x2e31790, L_0x2e31980, C4<1>, C4<1>; +L_0x2e30fd0 .delay 1 (30000,30000,30000) L_0x2e30fd0/d; +v0x2cb85e0_0 .net *"_s0", 0 0, L_0x2e31790; 1 drivers +v0x2cb86c0_0 .net *"_s1", 0 0, L_0x2e31980; 1 drivers +S_0x2cb9280 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2cb5e50; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x133e3d0/d .functor OR 1, L_0x133e490, L_0x133e640, C4<0>, C4<0>; -L_0x133e3d0 .delay 1 (30000,30000,30000) L_0x133e3d0/d; -v0x11df8d0_0 .net *"_s10", 0 0, L_0x133e490; 1 drivers -v0x11df9b0_0 .net *"_s12", 0 0, L_0x133e640; 1 drivers -v0x11dfa90_0 .net "in", 7 0, L_0x133c3d0; alias, 1 drivers -v0x11dfb60_0 .net "ors", 1 0, L_0x133e1f0; 1 drivers -v0x11dfc20_0 .net "out", 0 0, L_0x133e3d0; alias, 1 drivers -L_0x133d5c0 .part L_0x133c3d0, 0, 4; -L_0x133e1f0 .concat8 [ 1 1 0 0], L_0x133d2b0, L_0x133dee0; -L_0x133e330 .part L_0x133c3d0, 4, 4; -L_0x133e490 .part L_0x133e1f0, 0, 1; -L_0x133e640 .part L_0x133e1f0, 1, 1; -S_0x11ddf40 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11ddd80; +L_0x2e333d0/d .functor OR 1, L_0x2e33490, L_0x2e33640, C4<0>, C4<0>; +L_0x2e333d0 .delay 1 (30000,30000,30000) L_0x2e333d0/d; +v0x2cbadd0_0 .net *"_s10", 0 0, L_0x2e33490; 1 drivers +v0x2cbaeb0_0 .net *"_s12", 0 0, L_0x2e33640; 1 drivers +v0x2cbaf90_0 .net "in", 7 0, L_0x2e313d0; alias, 1 drivers +v0x2cbb060_0 .net "ors", 1 0, L_0x2e331f0; 1 drivers +v0x2cbb120_0 .net "out", 0 0, L_0x2e333d0; alias, 1 drivers +L_0x2e325c0 .part L_0x2e313d0, 0, 4; +L_0x2e331f0 .concat8 [ 1 1 0 0], L_0x2e322b0, L_0x2e32ee0; +L_0x2e33330 .part L_0x2e313d0, 4, 4; +L_0x2e33490 .part L_0x2e331f0, 0, 1; +L_0x2e33640 .part L_0x2e331f0, 1, 1; +S_0x2cb9440 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2cb9280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x133ca70/d .functor OR 1, L_0x133cb30, L_0x133cc90, C4<0>, C4<0>; -L_0x133ca70 .delay 1 (30000,30000,30000) L_0x133ca70/d; -L_0x133cec0/d .functor OR 1, L_0x133cfd0, L_0x133d130, C4<0>, C4<0>; -L_0x133cec0 .delay 1 (30000,30000,30000) L_0x133cec0/d; -L_0x133d2b0/d .functor OR 1, L_0x133d320, L_0x133d4d0, C4<0>, C4<0>; -L_0x133d2b0 .delay 1 (30000,30000,30000) L_0x133d2b0/d; -v0x11de190_0 .net *"_s0", 0 0, L_0x133ca70; 1 drivers -v0x11de290_0 .net *"_s10", 0 0, L_0x133cfd0; 1 drivers -v0x11de370_0 .net *"_s12", 0 0, L_0x133d130; 1 drivers -v0x11de430_0 .net *"_s14", 0 0, L_0x133d320; 1 drivers -v0x11de510_0 .net *"_s16", 0 0, L_0x133d4d0; 1 drivers -v0x11de640_0 .net *"_s3", 0 0, L_0x133cb30; 1 drivers -v0x11de720_0 .net *"_s5", 0 0, L_0x133cc90; 1 drivers -v0x11de800_0 .net *"_s6", 0 0, L_0x133cec0; 1 drivers -v0x11de8e0_0 .net "in", 3 0, L_0x133d5c0; 1 drivers -v0x11dea50_0 .net "ors", 1 0, L_0x133cdd0; 1 drivers -v0x11deb30_0 .net "out", 0 0, L_0x133d2b0; 1 drivers -L_0x133cb30 .part L_0x133d5c0, 0, 1; -L_0x133cc90 .part L_0x133d5c0, 1, 1; -L_0x133cdd0 .concat8 [ 1 1 0 0], L_0x133ca70, L_0x133cec0; -L_0x133cfd0 .part L_0x133d5c0, 2, 1; -L_0x133d130 .part L_0x133d5c0, 3, 1; -L_0x133d320 .part L_0x133cdd0, 0, 1; -L_0x133d4d0 .part L_0x133cdd0, 1, 1; -S_0x11dec50 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11ddd80; +L_0x2e31a70/d .functor OR 1, L_0x2e31b30, L_0x2e31c90, C4<0>, C4<0>; +L_0x2e31a70 .delay 1 (30000,30000,30000) L_0x2e31a70/d; +L_0x2e31ec0/d .functor OR 1, L_0x2e31fd0, L_0x2e32130, C4<0>, C4<0>; +L_0x2e31ec0 .delay 1 (30000,30000,30000) L_0x2e31ec0/d; +L_0x2e322b0/d .functor OR 1, L_0x2e32320, L_0x2e324d0, C4<0>, C4<0>; +L_0x2e322b0 .delay 1 (30000,30000,30000) L_0x2e322b0/d; +v0x2cb9690_0 .net *"_s0", 0 0, L_0x2e31a70; 1 drivers +v0x2cb9790_0 .net *"_s10", 0 0, L_0x2e31fd0; 1 drivers +v0x2cb9870_0 .net *"_s12", 0 0, L_0x2e32130; 1 drivers +v0x2cb9930_0 .net *"_s14", 0 0, L_0x2e32320; 1 drivers +v0x2cb9a10_0 .net *"_s16", 0 0, L_0x2e324d0; 1 drivers +v0x2cb9b40_0 .net *"_s3", 0 0, L_0x2e31b30; 1 drivers +v0x2cb9c20_0 .net *"_s5", 0 0, L_0x2e31c90; 1 drivers +v0x2cb9d00_0 .net *"_s6", 0 0, L_0x2e31ec0; 1 drivers +v0x2cb9de0_0 .net "in", 3 0, L_0x2e325c0; 1 drivers +v0x2cb9f50_0 .net "ors", 1 0, L_0x2e31dd0; 1 drivers +v0x2cba030_0 .net "out", 0 0, L_0x2e322b0; 1 drivers +L_0x2e31b30 .part L_0x2e325c0, 0, 1; +L_0x2e31c90 .part L_0x2e325c0, 1, 1; +L_0x2e31dd0 .concat8 [ 1 1 0 0], L_0x2e31a70, L_0x2e31ec0; +L_0x2e31fd0 .part L_0x2e325c0, 2, 1; +L_0x2e32130 .part L_0x2e325c0, 3, 1; +L_0x2e32320 .part L_0x2e31dd0, 0, 1; +L_0x2e324d0 .part L_0x2e31dd0, 1, 1; +S_0x2cba150 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2cb9280; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x133d6f0/d .functor OR 1, L_0x133d760, L_0x133d8c0, C4<0>, C4<0>; -L_0x133d6f0 .delay 1 (30000,30000,30000) L_0x133d6f0/d; -L_0x133daf0/d .functor OR 1, L_0x133dc00, L_0x133dd60, C4<0>, C4<0>; -L_0x133daf0 .delay 1 (30000,30000,30000) L_0x133daf0/d; -L_0x133dee0/d .functor OR 1, L_0x133df50, L_0x133e100, C4<0>, C4<0>; -L_0x133dee0 .delay 1 (30000,30000,30000) L_0x133dee0/d; -v0x11dee10_0 .net *"_s0", 0 0, L_0x133d6f0; 1 drivers -v0x11def10_0 .net *"_s10", 0 0, L_0x133dc00; 1 drivers -v0x11deff0_0 .net *"_s12", 0 0, L_0x133dd60; 1 drivers -v0x11df0b0_0 .net *"_s14", 0 0, L_0x133df50; 1 drivers -v0x11df190_0 .net *"_s16", 0 0, L_0x133e100; 1 drivers -v0x11df2c0_0 .net *"_s3", 0 0, L_0x133d760; 1 drivers -v0x11df3a0_0 .net *"_s5", 0 0, L_0x133d8c0; 1 drivers -v0x11df480_0 .net *"_s6", 0 0, L_0x133daf0; 1 drivers -v0x11df560_0 .net "in", 3 0, L_0x133e330; 1 drivers -v0x11df6d0_0 .net "ors", 1 0, L_0x133da00; 1 drivers -v0x11df7b0_0 .net "out", 0 0, L_0x133dee0; 1 drivers -L_0x133d760 .part L_0x133e330, 0, 1; -L_0x133d8c0 .part L_0x133e330, 1, 1; -L_0x133da00 .concat8 [ 1 1 0 0], L_0x133d6f0, L_0x133daf0; -L_0x133dc00 .part L_0x133e330, 2, 1; -L_0x133dd60 .part L_0x133e330, 3, 1; -L_0x133df50 .part L_0x133da00, 0, 1; -L_0x133e100 .part L_0x133da00, 1, 1; -S_0x11e00c0 .scope module, "resMux" "unaryMultiplexor" 4 170, 4 69 0, S_0x11d91f0; +L_0x2e326f0/d .functor OR 1, L_0x2e32760, L_0x2e328c0, C4<0>, C4<0>; +L_0x2e326f0 .delay 1 (30000,30000,30000) L_0x2e326f0/d; +L_0x2e32af0/d .functor OR 1, L_0x2e32c00, L_0x2e32d60, C4<0>, C4<0>; +L_0x2e32af0 .delay 1 (30000,30000,30000) L_0x2e32af0/d; +L_0x2e32ee0/d .functor OR 1, L_0x2e32f50, L_0x2e33100, C4<0>, C4<0>; +L_0x2e32ee0 .delay 1 (30000,30000,30000) L_0x2e32ee0/d; +v0x2cba310_0 .net *"_s0", 0 0, L_0x2e326f0; 1 drivers +v0x2cba410_0 .net *"_s10", 0 0, L_0x2e32c00; 1 drivers +v0x2cba4f0_0 .net *"_s12", 0 0, L_0x2e32d60; 1 drivers +v0x2cba5b0_0 .net *"_s14", 0 0, L_0x2e32f50; 1 drivers +v0x2cba690_0 .net *"_s16", 0 0, L_0x2e33100; 1 drivers +v0x2cba7c0_0 .net *"_s3", 0 0, L_0x2e32760; 1 drivers +v0x2cba8a0_0 .net *"_s5", 0 0, L_0x2e328c0; 1 drivers +v0x2cba980_0 .net *"_s6", 0 0, L_0x2e32af0; 1 drivers +v0x2cbaa60_0 .net "in", 3 0, L_0x2e33330; 1 drivers +v0x2cbabd0_0 .net "ors", 1 0, L_0x2e32a00; 1 drivers +v0x2cbacb0_0 .net "out", 0 0, L_0x2e32ee0; 1 drivers +L_0x2e32760 .part L_0x2e33330, 0, 1; +L_0x2e328c0 .part L_0x2e33330, 1, 1; +L_0x2e32a00 .concat8 [ 1 1 0 0], L_0x2e326f0, L_0x2e32af0; +L_0x2e32c00 .part L_0x2e33330, 2, 1; +L_0x2e32d60 .part L_0x2e33330, 3, 1; +L_0x2e32f50 .part L_0x2e32a00, 0, 1; +L_0x2e33100 .part L_0x2e32a00, 1, 1; +S_0x2cbb5c0 .scope module, "resMux" "unaryMultiplexor" 4 175, 4 69 0, S_0x2cb46f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" .port_info 2 /INPUT 8 "sel" -v0x11e54f0_0 .net "ands", 7 0, L_0x1338990; 1 drivers -v0x11e5600_0 .net "in", 7 0, L_0x1336df0; alias, 1 drivers -v0x11e56c0_0 .net "out", 0 0, L_0x133a990; alias, 1 drivers -v0x11e5790_0 .net "sel", 7 0, v0x12010b0_0; alias, 1 drivers -S_0x11e0310 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x11e00c0; +v0x2cc09f0_0 .net "ands", 7 0, L_0x2e2d970; 1 drivers +v0x2cc0b00_0 .net "in", 7 0, L_0x2e2b8e0; alias, 1 drivers +v0x2cc0bc0_0 .net "out", 0 0, L_0x2e2f8b0; alias, 1 drivers +v0x2cc0c90_0 .net "sel", 7 0, v0x2cdd2e0_0; alias, 1 drivers +S_0x2cbb810 .scope module, "andP" "and8P" 4 71, 4 51 0, S_0x2cbb5c0; .timescale -9 -12; .port_info 0 /OUTPUT 8 "out" .port_info 1 /INPUT 8 "A" .port_info 2 /INPUT 8 "B" -v0x11e2a50_0 .net "A", 7 0, L_0x1336df0; alias, 1 drivers -v0x11e2b50_0 .net "B", 7 0, v0x12010b0_0; alias, 1 drivers -v0x11e2c10_0 .net *"_s0", 0 0, L_0x1337180; 1 drivers -v0x11e2cd0_0 .net *"_s12", 0 0, L_0x1337b40; 1 drivers -v0x11e2db0_0 .net *"_s16", 0 0, L_0x1337ea0; 1 drivers -v0x11e2ee0_0 .net *"_s20", 0 0, L_0x13382d0; 1 drivers -v0x11e2fc0_0 .net *"_s24", 0 0, L_0x1338600; 1 drivers -v0x11e30a0_0 .net *"_s28", 0 0, L_0x1338590; 1 drivers -v0x11e3180_0 .net *"_s4", 0 0, L_0x1337520; 1 drivers -v0x11e32f0_0 .net *"_s8", 0 0, L_0x1337830; 1 drivers -v0x11e33d0_0 .net "out", 7 0, L_0x1338990; alias, 1 drivers -L_0x1337290 .part L_0x1336df0, 0, 1; -L_0x1337480 .part v0x12010b0_0, 0, 1; -L_0x13375e0 .part L_0x1336df0, 1, 1; -L_0x1337740 .part v0x12010b0_0, 1, 1; -L_0x13378f0 .part L_0x1336df0, 2, 1; -L_0x1337a50 .part v0x12010b0_0, 2, 1; -L_0x1337c00 .part L_0x1336df0, 3, 1; -L_0x1337d60 .part v0x12010b0_0, 3, 1; -L_0x1337f60 .part L_0x1336df0, 4, 1; -L_0x13381d0 .part v0x12010b0_0, 4, 1; -L_0x1338340 .part L_0x1336df0, 5, 1; -L_0x13384a0 .part v0x12010b0_0, 5, 1; -L_0x13386c0 .part L_0x1336df0, 6, 1; -L_0x1338820 .part v0x12010b0_0, 6, 1; -LS_0x1338990_0_0 .concat8 [ 1 1 1 1], L_0x1337180, L_0x1337520, L_0x1337830, L_0x1337b40; -LS_0x1338990_0_4 .concat8 [ 1 1 1 1], L_0x1337ea0, L_0x13382d0, L_0x1338600, L_0x1338590; -L_0x1338990 .concat8 [ 4 4 0 0], LS_0x1338990_0_0, LS_0x1338990_0_4; -L_0x1338d50 .part L_0x1336df0, 7, 1; -L_0x1338f40 .part v0x12010b0_0, 7, 1; -S_0x11e0550 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e0760 .param/l "i" 0 4 54, +C4<00>; -L_0x1337180/d .functor AND 1, L_0x1337290, L_0x1337480, C4<1>, C4<1>; -L_0x1337180 .delay 1 (30000,30000,30000) L_0x1337180/d; -v0x11e0840_0 .net *"_s0", 0 0, L_0x1337290; 1 drivers -v0x11e0920_0 .net *"_s1", 0 0, L_0x1337480; 1 drivers -S_0x11e0a00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e0c10 .param/l "i" 0 4 54, +C4<01>; -L_0x1337520/d .functor AND 1, L_0x13375e0, L_0x1337740, C4<1>, C4<1>; -L_0x1337520 .delay 1 (30000,30000,30000) L_0x1337520/d; -v0x11e0cd0_0 .net *"_s0", 0 0, L_0x13375e0; 1 drivers -v0x11e0db0_0 .net *"_s1", 0 0, L_0x1337740; 1 drivers -S_0x11e0e90 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e10d0 .param/l "i" 0 4 54, +C4<010>; -L_0x1337830/d .functor AND 1, L_0x13378f0, L_0x1337a50, C4<1>, C4<1>; -L_0x1337830 .delay 1 (30000,30000,30000) L_0x1337830/d; -v0x11e1170_0 .net *"_s0", 0 0, L_0x13378f0; 1 drivers -v0x11e1250_0 .net *"_s1", 0 0, L_0x1337a50; 1 drivers -S_0x11e1330 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e1540 .param/l "i" 0 4 54, +C4<011>; -L_0x1337b40/d .functor AND 1, L_0x1337c00, L_0x1337d60, C4<1>, C4<1>; -L_0x1337b40 .delay 1 (30000,30000,30000) L_0x1337b40/d; -v0x11e1600_0 .net *"_s0", 0 0, L_0x1337c00; 1 drivers -v0x11e16e0_0 .net *"_s1", 0 0, L_0x1337d60; 1 drivers -S_0x11e17c0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e1a20 .param/l "i" 0 4 54, +C4<0100>; -L_0x1337ea0/d .functor AND 1, L_0x1337f60, L_0x13381d0, C4<1>, C4<1>; -L_0x1337ea0 .delay 1 (30000,30000,30000) L_0x1337ea0/d; -v0x11e1ae0_0 .net *"_s0", 0 0, L_0x1337f60; 1 drivers -v0x11e1bc0_0 .net *"_s1", 0 0, L_0x13381d0; 1 drivers -S_0x11e1ca0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e1eb0 .param/l "i" 0 4 54, +C4<0101>; -L_0x13382d0/d .functor AND 1, L_0x1338340, L_0x13384a0, C4<1>, C4<1>; -L_0x13382d0 .delay 1 (30000,30000,30000) L_0x13382d0/d; -v0x11e1f70_0 .net *"_s0", 0 0, L_0x1338340; 1 drivers -v0x11e2050_0 .net *"_s1", 0 0, L_0x13384a0; 1 drivers -S_0x11e2130 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e2340 .param/l "i" 0 4 54, +C4<0110>; -L_0x1338600/d .functor AND 1, L_0x13386c0, L_0x1338820, C4<1>, C4<1>; -L_0x1338600 .delay 1 (30000,30000,30000) L_0x1338600/d; -v0x11e2400_0 .net *"_s0", 0 0, L_0x13386c0; 1 drivers -v0x11e24e0_0 .net *"_s1", 0 0, L_0x1338820; 1 drivers -S_0x11e25c0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x11e0310; - .timescale -9 -12; -P_0x11e27d0 .param/l "i" 0 4 54, +C4<0111>; -L_0x1338590/d .functor AND 1, L_0x1338d50, L_0x1338f40, C4<1>, C4<1>; -L_0x1338590 .delay 1 (30000,30000,30000) L_0x1338590/d; -v0x11e2890_0 .net *"_s0", 0 0, L_0x1338d50; 1 drivers -v0x11e2970_0 .net *"_s1", 0 0, L_0x1338f40; 1 drivers -S_0x11e3530 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x11e00c0; +v0x2cbdf50_0 .net "A", 7 0, L_0x2e2b8e0; alias, 1 drivers +v0x2cbe050_0 .net "B", 7 0, v0x2cdd2e0_0; alias, 1 drivers +v0x2cbe110_0 .net *"_s0", 0 0, L_0x2e2c160; 1 drivers +v0x2cbe1d0_0 .net *"_s12", 0 0, L_0x2e2cb20; 1 drivers +v0x2cbe2b0_0 .net *"_s16", 0 0, L_0x2e2ce80; 1 drivers +v0x2cbe3e0_0 .net *"_s20", 0 0, L_0x2e2d2b0; 1 drivers +v0x2cbe4c0_0 .net *"_s24", 0 0, L_0x2e2d5e0; 1 drivers +v0x2cbe5a0_0 .net *"_s28", 0 0, L_0x2e2d570; 1 drivers +v0x2cbe680_0 .net *"_s4", 0 0, L_0x2e2c500; 1 drivers +v0x2cbe7f0_0 .net *"_s8", 0 0, L_0x2e2c810; 1 drivers +v0x2cbe8d0_0 .net "out", 7 0, L_0x2e2d970; alias, 1 drivers +L_0x2e2c270 .part L_0x2e2b8e0, 0, 1; +L_0x2e2c460 .part v0x2cdd2e0_0, 0, 1; +L_0x2e2c5c0 .part L_0x2e2b8e0, 1, 1; +L_0x2e2c720 .part v0x2cdd2e0_0, 1, 1; +L_0x2e2c8d0 .part L_0x2e2b8e0, 2, 1; +L_0x2e2ca30 .part v0x2cdd2e0_0, 2, 1; +L_0x2e2cbe0 .part L_0x2e2b8e0, 3, 1; +L_0x2e2cd40 .part v0x2cdd2e0_0, 3, 1; +L_0x2e2cf40 .part L_0x2e2b8e0, 4, 1; +L_0x2e2d1b0 .part v0x2cdd2e0_0, 4, 1; +L_0x2e2d320 .part L_0x2e2b8e0, 5, 1; +L_0x2e2d480 .part v0x2cdd2e0_0, 5, 1; +L_0x2e2d6a0 .part L_0x2e2b8e0, 6, 1; +L_0x2e2d800 .part v0x2cdd2e0_0, 6, 1; +LS_0x2e2d970_0_0 .concat8 [ 1 1 1 1], L_0x2e2c160, L_0x2e2c500, L_0x2e2c810, L_0x2e2cb20; +LS_0x2e2d970_0_4 .concat8 [ 1 1 1 1], L_0x2e2ce80, L_0x2e2d2b0, L_0x2e2d5e0, L_0x2e2d570; +L_0x2e2d970 .concat8 [ 4 4 0 0], LS_0x2e2d970_0_0, LS_0x2e2d970_0_4; +L_0x2e2dd30 .part L_0x2e2b8e0, 7, 1; +L_0x2e2df20 .part v0x2cdd2e0_0, 7, 1; +S_0x2cbba50 .scope generate, "and_slces[0]" "and_slces[0]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbbc60 .param/l "i" 0 4 54, +C4<00>; +L_0x2e2c160/d .functor AND 1, L_0x2e2c270, L_0x2e2c460, C4<1>, C4<1>; +L_0x2e2c160 .delay 1 (30000,30000,30000) L_0x2e2c160/d; +v0x2cbbd40_0 .net *"_s0", 0 0, L_0x2e2c270; 1 drivers +v0x2cbbe20_0 .net *"_s1", 0 0, L_0x2e2c460; 1 drivers +S_0x2cbbf00 .scope generate, "and_slces[1]" "and_slces[1]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbc110 .param/l "i" 0 4 54, +C4<01>; +L_0x2e2c500/d .functor AND 1, L_0x2e2c5c0, L_0x2e2c720, C4<1>, C4<1>; +L_0x2e2c500 .delay 1 (30000,30000,30000) L_0x2e2c500/d; +v0x2cbc1d0_0 .net *"_s0", 0 0, L_0x2e2c5c0; 1 drivers +v0x2cbc2b0_0 .net *"_s1", 0 0, L_0x2e2c720; 1 drivers +S_0x2cbc390 .scope generate, "and_slces[2]" "and_slces[2]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbc5d0 .param/l "i" 0 4 54, +C4<010>; +L_0x2e2c810/d .functor AND 1, L_0x2e2c8d0, L_0x2e2ca30, C4<1>, C4<1>; +L_0x2e2c810 .delay 1 (30000,30000,30000) L_0x2e2c810/d; +v0x2cbc670_0 .net *"_s0", 0 0, L_0x2e2c8d0; 1 drivers +v0x2cbc750_0 .net *"_s1", 0 0, L_0x2e2ca30; 1 drivers +S_0x2cbc830 .scope generate, "and_slces[3]" "and_slces[3]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbca40 .param/l "i" 0 4 54, +C4<011>; +L_0x2e2cb20/d .functor AND 1, L_0x2e2cbe0, L_0x2e2cd40, C4<1>, C4<1>; +L_0x2e2cb20 .delay 1 (30000,30000,30000) L_0x2e2cb20/d; +v0x2cbcb00_0 .net *"_s0", 0 0, L_0x2e2cbe0; 1 drivers +v0x2cbcbe0_0 .net *"_s1", 0 0, L_0x2e2cd40; 1 drivers +S_0x2cbccc0 .scope generate, "and_slces[4]" "and_slces[4]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbcf20 .param/l "i" 0 4 54, +C4<0100>; +L_0x2e2ce80/d .functor AND 1, L_0x2e2cf40, L_0x2e2d1b0, C4<1>, C4<1>; +L_0x2e2ce80 .delay 1 (30000,30000,30000) L_0x2e2ce80/d; +v0x2cbcfe0_0 .net *"_s0", 0 0, L_0x2e2cf40; 1 drivers +v0x2cbd0c0_0 .net *"_s1", 0 0, L_0x2e2d1b0; 1 drivers +S_0x2cbd1a0 .scope generate, "and_slces[5]" "and_slces[5]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbd3b0 .param/l "i" 0 4 54, +C4<0101>; +L_0x2e2d2b0/d .functor AND 1, L_0x2e2d320, L_0x2e2d480, C4<1>, C4<1>; +L_0x2e2d2b0 .delay 1 (30000,30000,30000) L_0x2e2d2b0/d; +v0x2cbd470_0 .net *"_s0", 0 0, L_0x2e2d320; 1 drivers +v0x2cbd550_0 .net *"_s1", 0 0, L_0x2e2d480; 1 drivers +S_0x2cbd630 .scope generate, "and_slces[6]" "and_slces[6]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbd840 .param/l "i" 0 4 54, +C4<0110>; +L_0x2e2d5e0/d .functor AND 1, L_0x2e2d6a0, L_0x2e2d800, C4<1>, C4<1>; +L_0x2e2d5e0 .delay 1 (30000,30000,30000) L_0x2e2d5e0/d; +v0x2cbd900_0 .net *"_s0", 0 0, L_0x2e2d6a0; 1 drivers +v0x2cbd9e0_0 .net *"_s1", 0 0, L_0x2e2d800; 1 drivers +S_0x2cbdac0 .scope generate, "and_slces[7]" "and_slces[7]" 4 54, 4 54 0, S_0x2cbb810; + .timescale -9 -12; +P_0x2cbdcd0 .param/l "i" 0 4 54, +C4<0111>; +L_0x2e2d570/d .functor AND 1, L_0x2e2dd30, L_0x2e2df20, C4<1>, C4<1>; +L_0x2e2d570 .delay 1 (30000,30000,30000) L_0x2e2d570/d; +v0x2cbdd90_0 .net *"_s0", 0 0, L_0x2e2dd30; 1 drivers +v0x2cbde70_0 .net *"_s1", 0 0, L_0x2e2df20; 1 drivers +S_0x2cbea30 .scope module, "ors" "or8" 4 72, 4 16 0, S_0x2cbb5c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x133a990/d .functor OR 1, L_0x133aa50, L_0x133ac00, C4<0>, C4<0>; -L_0x133a990 .delay 1 (30000,30000,30000) L_0x133a990/d; -v0x11e5080_0 .net *"_s10", 0 0, L_0x133aa50; 1 drivers -v0x11e5160_0 .net *"_s12", 0 0, L_0x133ac00; 1 drivers -v0x11e5240_0 .net "in", 7 0, L_0x1338990; alias, 1 drivers -v0x11e5310_0 .net "ors", 1 0, L_0x133a7b0; 1 drivers -v0x11e53d0_0 .net "out", 0 0, L_0x133a990; alias, 1 drivers -L_0x1339b80 .part L_0x1338990, 0, 4; -L_0x133a7b0 .concat8 [ 1 1 0 0], L_0x1339870, L_0x133a4a0; -L_0x133a8f0 .part L_0x1338990, 4, 4; -L_0x133aa50 .part L_0x133a7b0, 0, 1; -L_0x133ac00 .part L_0x133a7b0, 1, 1; -S_0x11e36f0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x11e3530; +L_0x2e2f8b0/d .functor OR 1, L_0x2e2f970, L_0x2e2fb20, C4<0>, C4<0>; +L_0x2e2f8b0 .delay 1 (30000,30000,30000) L_0x2e2f8b0/d; +v0x2cc0580_0 .net *"_s10", 0 0, L_0x2e2f970; 1 drivers +v0x2cc0660_0 .net *"_s12", 0 0, L_0x2e2fb20; 1 drivers +v0x2cc0740_0 .net "in", 7 0, L_0x2e2d970; alias, 1 drivers +v0x2cc0810_0 .net "ors", 1 0, L_0x2e2f6d0; 1 drivers +v0x2cc08d0_0 .net "out", 0 0, L_0x2e2f8b0; alias, 1 drivers +L_0x2e2eb60 .part L_0x2e2d970, 0, 4; +L_0x2e2f6d0 .concat8 [ 1 1 0 0], L_0x2e2e850, L_0x2e2f3c0; +L_0x2e2f810 .part L_0x2e2d970, 4, 4; +L_0x2e2f970 .part L_0x2e2f6d0, 0, 1; +L_0x2e2fb20 .part L_0x2e2f6d0, 1, 1; +S_0x2cbebf0 .scope module, "or_1" "or4" 4 18, 4 9 0, S_0x2cbea30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1339030/d .functor OR 1, L_0x13390f0, L_0x1339250, C4<0>, C4<0>; -L_0x1339030 .delay 1 (30000,30000,30000) L_0x1339030/d; -L_0x1339480/d .functor OR 1, L_0x1339590, L_0x13396f0, C4<0>, C4<0>; -L_0x1339480 .delay 1 (30000,30000,30000) L_0x1339480/d; -L_0x1339870/d .functor OR 1, L_0x13398e0, L_0x1339a90, C4<0>, C4<0>; -L_0x1339870 .delay 1 (30000,30000,30000) L_0x1339870/d; -v0x11e3940_0 .net *"_s0", 0 0, L_0x1339030; 1 drivers -v0x11e3a40_0 .net *"_s10", 0 0, L_0x1339590; 1 drivers -v0x11e3b20_0 .net *"_s12", 0 0, L_0x13396f0; 1 drivers -v0x11e3be0_0 .net *"_s14", 0 0, L_0x13398e0; 1 drivers -v0x11e3cc0_0 .net *"_s16", 0 0, L_0x1339a90; 1 drivers -v0x11e3df0_0 .net *"_s3", 0 0, L_0x13390f0; 1 drivers -v0x11e3ed0_0 .net *"_s5", 0 0, L_0x1339250; 1 drivers -v0x11e3fb0_0 .net *"_s6", 0 0, L_0x1339480; 1 drivers -v0x11e4090_0 .net "in", 3 0, L_0x1339b80; 1 drivers -v0x11e4200_0 .net "ors", 1 0, L_0x1339390; 1 drivers -v0x11e42e0_0 .net "out", 0 0, L_0x1339870; 1 drivers -L_0x13390f0 .part L_0x1339b80, 0, 1; -L_0x1339250 .part L_0x1339b80, 1, 1; -L_0x1339390 .concat8 [ 1 1 0 0], L_0x1339030, L_0x1339480; -L_0x1339590 .part L_0x1339b80, 2, 1; -L_0x13396f0 .part L_0x1339b80, 3, 1; -L_0x13398e0 .part L_0x1339390, 0, 1; -L_0x1339a90 .part L_0x1339390, 1, 1; -S_0x11e4400 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x11e3530; +L_0x2e2e010/d .functor OR 1, L_0x2e2e0d0, L_0x2e2e230, C4<0>, C4<0>; +L_0x2e2e010 .delay 1 (30000,30000,30000) L_0x2e2e010/d; +L_0x2e2e460/d .functor OR 1, L_0x2e2e570, L_0x2e2e6d0, C4<0>, C4<0>; +L_0x2e2e460 .delay 1 (30000,30000,30000) L_0x2e2e460/d; +L_0x2e2e850/d .functor OR 1, L_0x2e2e8c0, L_0x2e2ea70, C4<0>, C4<0>; +L_0x2e2e850 .delay 1 (30000,30000,30000) L_0x2e2e850/d; +v0x2cbee40_0 .net *"_s0", 0 0, L_0x2e2e010; 1 drivers +v0x2cbef40_0 .net *"_s10", 0 0, L_0x2e2e570; 1 drivers +v0x2cbf020_0 .net *"_s12", 0 0, L_0x2e2e6d0; 1 drivers +v0x2cbf0e0_0 .net *"_s14", 0 0, L_0x2e2e8c0; 1 drivers +v0x2cbf1c0_0 .net *"_s16", 0 0, L_0x2e2ea70; 1 drivers +v0x2cbf2f0_0 .net *"_s3", 0 0, L_0x2e2e0d0; 1 drivers +v0x2cbf3d0_0 .net *"_s5", 0 0, L_0x2e2e230; 1 drivers +v0x2cbf4b0_0 .net *"_s6", 0 0, L_0x2e2e460; 1 drivers +v0x2cbf590_0 .net "in", 3 0, L_0x2e2eb60; 1 drivers +v0x2cbf700_0 .net "ors", 1 0, L_0x2e2e370; 1 drivers +v0x2cbf7e0_0 .net "out", 0 0, L_0x2e2e850; 1 drivers +L_0x2e2e0d0 .part L_0x2e2eb60, 0, 1; +L_0x2e2e230 .part L_0x2e2eb60, 1, 1; +L_0x2e2e370 .concat8 [ 1 1 0 0], L_0x2e2e010, L_0x2e2e460; +L_0x2e2e570 .part L_0x2e2eb60, 2, 1; +L_0x2e2e6d0 .part L_0x2e2eb60, 3, 1; +L_0x2e2e8c0 .part L_0x2e2e370, 0, 1; +L_0x2e2ea70 .part L_0x2e2e370, 1, 1; +S_0x2cbf900 .scope module, "or_2" "or4" 4 19, 4 9 0, S_0x2cbea30; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1339cb0/d .functor OR 1, L_0x1339d20, L_0x1339e80, C4<0>, C4<0>; -L_0x1339cb0 .delay 1 (30000,30000,30000) L_0x1339cb0/d; -L_0x133a0b0/d .functor OR 1, L_0x133a1c0, L_0x133a320, C4<0>, C4<0>; -L_0x133a0b0 .delay 1 (30000,30000,30000) L_0x133a0b0/d; -L_0x133a4a0/d .functor OR 1, L_0x133a510, L_0x133a6c0, C4<0>, C4<0>; -L_0x133a4a0 .delay 1 (30000,30000,30000) L_0x133a4a0/d; -v0x11e45c0_0 .net *"_s0", 0 0, L_0x1339cb0; 1 drivers -v0x11e46c0_0 .net *"_s10", 0 0, L_0x133a1c0; 1 drivers -v0x11e47a0_0 .net *"_s12", 0 0, L_0x133a320; 1 drivers -v0x11e4860_0 .net *"_s14", 0 0, L_0x133a510; 1 drivers -v0x11e4940_0 .net *"_s16", 0 0, L_0x133a6c0; 1 drivers -v0x11e4a70_0 .net *"_s3", 0 0, L_0x1339d20; 1 drivers -v0x11e4b50_0 .net *"_s5", 0 0, L_0x1339e80; 1 drivers -v0x11e4c30_0 .net *"_s6", 0 0, L_0x133a0b0; 1 drivers -v0x11e4d10_0 .net "in", 3 0, L_0x133a8f0; 1 drivers -v0x11e4e80_0 .net "ors", 1 0, L_0x1339fc0; 1 drivers -v0x11e4f60_0 .net "out", 0 0, L_0x133a4a0; 1 drivers -L_0x1339d20 .part L_0x133a8f0, 0, 1; -L_0x1339e80 .part L_0x133a8f0, 1, 1; -L_0x1339fc0 .concat8 [ 1 1 0 0], L_0x1339cb0, L_0x133a0b0; -L_0x133a1c0 .part L_0x133a8f0, 2, 1; -L_0x133a320 .part L_0x133a8f0, 3, 1; -L_0x133a510 .part L_0x1339fc0, 0, 1; -L_0x133a6c0 .part L_0x1339fc0, 1, 1; -S_0x11e5870 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11d91f0; +L_0x2e2ec90/d .functor OR 1, L_0x2e2ed00, L_0x2e2ee60, C4<0>, C4<0>; +L_0x2e2ec90 .delay 1 (30000,30000,30000) L_0x2e2ec90/d; +L_0x2e2d8f0/d .functor OR 1, L_0x2e2f0e0, L_0x2e2f240, C4<0>, C4<0>; +L_0x2e2d8f0 .delay 1 (30000,30000,30000) L_0x2e2d8f0/d; +L_0x2e2f3c0/d .functor OR 1, L_0x2e2f430, L_0x2e2f5e0, C4<0>, C4<0>; +L_0x2e2f3c0 .delay 1 (30000,30000,30000) L_0x2e2f3c0/d; +v0x2cbfac0_0 .net *"_s0", 0 0, L_0x2e2ec90; 1 drivers +v0x2cbfbc0_0 .net *"_s10", 0 0, L_0x2e2f0e0; 1 drivers +v0x2cbfca0_0 .net *"_s12", 0 0, L_0x2e2f240; 1 drivers +v0x2cbfd60_0 .net *"_s14", 0 0, L_0x2e2f430; 1 drivers +v0x2cbfe40_0 .net *"_s16", 0 0, L_0x2e2f5e0; 1 drivers +v0x2cbff70_0 .net *"_s3", 0 0, L_0x2e2ed00; 1 drivers +v0x2cc0050_0 .net *"_s5", 0 0, L_0x2e2ee60; 1 drivers +v0x2cc0130_0 .net *"_s6", 0 0, L_0x2e2d8f0; 1 drivers +v0x2cc0210_0 .net "in", 3 0, L_0x2e2f810; 1 drivers +v0x2cc0380_0 .net "ors", 1 0, L_0x2e2efa0; 1 drivers +v0x2cc0460_0 .net "out", 0 0, L_0x2e2f3c0; 1 drivers +L_0x2e2ed00 .part L_0x2e2f810, 0, 1; +L_0x2e2ee60 .part L_0x2e2f810, 1, 1; +L_0x2e2efa0 .concat8 [ 1 1 0 0], L_0x2e2ec90, L_0x2e2d8f0; +L_0x2e2f0e0 .part L_0x2e2f810, 2, 1; +L_0x2e2f240 .part L_0x2e2f810, 3, 1; +L_0x2e2f430 .part L_0x2e2efa0, 0, 1; +L_0x2e2f5e0 .part L_0x2e2efa0, 1, 1; +S_0x2cc0d70 .scope module, "sltGate" "slt" 4 164, 4 101 0, S_0x2cb46f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "carryin" @@ -17078,776 +18072,776 @@ S_0x11e5870 .scope module, "sltGate" "slt" 4 163, 4 101 0, S_0x11d91f0; .port_info 3 /INPUT 1 "a_" .port_info 4 /INPUT 1 "b" .port_info 5 /INPUT 1 "b_" -L_0x1336160/d .functor XNOR 1, L_0x133f6b0, L_0x133eaa0, C4<0>, C4<0>; -L_0x1336160 .delay 1 (20000,20000,20000) L_0x1336160/d; -L_0x13363d0/d .functor AND 1, L_0x133f6b0, L_0x132ae60, C4<1>, C4<1>; -L_0x13363d0 .delay 1 (30000,30000,30000) L_0x13363d0/d; -L_0x1336440/d .functor AND 1, L_0x1336160, L_0x133eb40, C4<1>, C4<1>; -L_0x1336440 .delay 1 (30000,30000,30000) L_0x1336440/d; -L_0x13365a0/d .functor OR 1, L_0x1336440, L_0x13363d0, C4<0>, C4<0>; -L_0x13365a0 .delay 1 (30000,30000,30000) L_0x13365a0/d; -v0x11e5b20_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers -v0x11e5c10_0 .net "a_", 0 0, L_0x1296070; alias, 1 drivers -v0x11e5cd0_0 .net "b", 0 0, L_0x133eaa0; alias, 1 drivers -v0x11e5dc0_0 .net "b_", 0 0, L_0x132ae60; alias, 1 drivers -v0x11e5e60_0 .net "carryin", 0 0, L_0x133eb40; alias, 1 drivers -v0x11e5fa0_0 .net "eq", 0 0, L_0x1336160; 1 drivers -v0x11e6060_0 .net "lt", 0 0, L_0x13363d0; 1 drivers -v0x11e6120_0 .net "out", 0 0, L_0x13365a0; 1 drivers -v0x11e61e0_0 .net "w0", 0 0, L_0x1336440; 1 drivers -S_0x11e6430 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x11d91f0; +L_0x2e2a720/d .functor XNOR 1, L_0x2e346b0, L_0x2e33aa0, C4<0>, C4<0>; +L_0x2e2a720 .delay 1 (20000,20000,20000) L_0x2e2a720/d; +L_0x2e2a8a0/d .functor AND 1, L_0x2e346b0, L_0x2e1e560, C4<1>, C4<1>; +L_0x2e2a8a0 .delay 1 (30000,30000,30000) L_0x2e2a8a0/d; +L_0x2e2aa00/d .functor AND 1, L_0x2e2a720, L_0x2e33b40, C4<1>, C4<1>; +L_0x2e2aa00 .delay 1 (30000,30000,30000) L_0x2e2aa00/d; +L_0x2e2ab10/d .functor OR 1, L_0x2e2aa00, L_0x2e2a8a0, C4<0>, C4<0>; +L_0x2e2ab10 .delay 1 (30000,30000,30000) L_0x2e2ab10/d; +v0x2cc1020_0 .net "a", 0 0, L_0x2e346b0; alias, 1 drivers +v0x2cc1110_0 .net "a_", 0 0, L_0x2e1ec50; alias, 1 drivers +v0x2cc11d0_0 .net "b", 0 0, L_0x2e33aa0; alias, 1 drivers +v0x2cc12c0_0 .net "b_", 0 0, L_0x2e1e560; alias, 1 drivers +v0x2cc1360_0 .net "carryin", 0 0, L_0x2e33b40; alias, 1 drivers +v0x2cc14a0_0 .net "eq", 0 0, L_0x2e2a720; 1 drivers +v0x2cc1560_0 .net "lt", 0 0, L_0x2e2a8a0; 1 drivers +v0x2cc1620_0 .net "out", 0 0, L_0x2e2ab10; 1 drivers +v0x2cc16e0_0 .net "w0", 0 0, L_0x2e2aa00; 1 drivers +S_0x2cc1930 .scope module, "sub" "fullAdder" 4 158, 4 85 0, S_0x2cb46f0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" .port_info 4 /INPUT 1 "carryin" -L_0x1335f40/d .functor OR 1, L_0x1335a40, L_0x11e7690, C4<0>, C4<0>; -L_0x1335f40 .delay 1 (30000,30000,30000) L_0x1335f40/d; -v0x11e7220_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers -v0x11e7370_0 .net "b", 0 0, L_0x132ae60; alias, 1 drivers -v0x11e7430_0 .net "c1", 0 0, L_0x1335a40; 1 drivers -v0x11e74d0_0 .net "c2", 0 0, L_0x11e7690; 1 drivers -v0x11e75a0_0 .net "carryin", 0 0, L_0x133eb40; alias, 1 drivers -v0x11e7720_0 .net "carryout", 0 0, L_0x1335f40; 1 drivers -v0x11e77c0_0 .net "s1", 0 0, L_0x1335980; 1 drivers -v0x11e7860_0 .net "sum", 0 0, L_0x1335ba0; 1 drivers -S_0x11e6680 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x11e6430; +L_0x2e2a300/d .functor OR 1, L_0x2e29e00, L_0x2cc2b90, C4<0>, C4<0>; +L_0x2e2a300 .delay 1 (30000,30000,30000) L_0x2e2a300/d; +v0x2cc2720_0 .net "a", 0 0, L_0x2e346b0; alias, 1 drivers +v0x2cc2870_0 .net "b", 0 0, L_0x2e1e560; alias, 1 drivers +v0x2cc2930_0 .net "c1", 0 0, L_0x2e29e00; 1 drivers +v0x2cc29d0_0 .net "c2", 0 0, L_0x2cc2b90; 1 drivers +v0x2cc2aa0_0 .net "carryin", 0 0, L_0x2e33b40; alias, 1 drivers +v0x2cc2c20_0 .net "carryout", 0 0, L_0x2e2a300; 1 drivers +v0x2cc2cc0_0 .net "s1", 0 0, L_0x2e29d40; 1 drivers +v0x2cc2d60_0 .net "sum", 0 0, L_0x2e29f60; 1 drivers +S_0x2cc1b80 .scope module, "a1" "halfAdder" 4 96, 4 75 0, S_0x2cc1930; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1335980/d .functor XOR 1, L_0x133f6b0, L_0x132ae60, C4<0>, C4<0>; -L_0x1335980 .delay 1 (30000,30000,30000) L_0x1335980/d; -L_0x1335a40/d .functor AND 1, L_0x133f6b0, L_0x132ae60, C4<1>, C4<1>; -L_0x1335a40 .delay 1 (30000,30000,30000) L_0x1335a40/d; -v0x11e68e0_0 .net "a", 0 0, L_0x133f6b0; alias, 1 drivers -v0x11e69a0_0 .net "b", 0 0, L_0x132ae60; alias, 1 drivers -v0x11e6a60_0 .net "carryout", 0 0, L_0x1335a40; alias, 1 drivers -v0x11e6b00_0 .net "sum", 0 0, L_0x1335980; alias, 1 drivers -S_0x11e6c30 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x11e6430; +L_0x2e29d40/d .functor XOR 1, L_0x2e346b0, L_0x2e1e560, C4<0>, C4<0>; +L_0x2e29d40 .delay 1 (30000,30000,30000) L_0x2e29d40/d; +L_0x2e29e00/d .functor AND 1, L_0x2e346b0, L_0x2e1e560, C4<1>, C4<1>; +L_0x2e29e00 .delay 1 (30000,30000,30000) L_0x2e29e00/d; +v0x2cc1de0_0 .net "a", 0 0, L_0x2e346b0; alias, 1 drivers +v0x2cc1ea0_0 .net "b", 0 0, L_0x2e1e560; alias, 1 drivers +v0x2cc1f60_0 .net "carryout", 0 0, L_0x2e29e00; alias, 1 drivers +v0x2cc2000_0 .net "sum", 0 0, L_0x2e29d40; alias, 1 drivers +S_0x2cc2130 .scope module, "a2" "halfAdder" 4 97, 4 75 0, S_0x2cc1930; .timescale -9 -12; .port_info 0 /OUTPUT 1 "sum" .port_info 1 /OUTPUT 1 "carryout" .port_info 2 /INPUT 1 "a" .port_info 3 /INPUT 1 "b" -L_0x1335ba0/d .functor XOR 1, L_0x1335980, L_0x133eb40, C4<0>, C4<0>; -L_0x1335ba0 .delay 1 (30000,30000,30000) L_0x1335ba0/d; -L_0x11e7690/d .functor AND 1, L_0x1335980, L_0x133eb40, C4<1>, C4<1>; -L_0x11e7690 .delay 1 (30000,30000,30000) L_0x11e7690/d; -v0x11e6e90_0 .net "a", 0 0, L_0x1335980; alias, 1 drivers -v0x11e6f60_0 .net "b", 0 0, L_0x133eb40; alias, 1 drivers -v0x11e7000_0 .net "carryout", 0 0, L_0x11e7690; alias, 1 drivers -v0x11e70d0_0 .net "sum", 0 0, L_0x1335ba0; alias, 1 drivers -S_0x11e8c80 .scope generate, "genblk2" "genblk2" 3 51, 3 51 0, S_0x11d8f20; - .timescale -9 -12; -L_0x2b0ab3d072f8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x2b0ab3d07340 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -L_0x1338910/d .functor OR 1, L_0x2b0ab3d072f8, L_0x2b0ab3d07340, C4<0>, C4<0>; -L_0x1338910 .delay 1 (30000,30000,30000) L_0x1338910/d; -v0x11e8e70_0 .net/2u *"_s0", 0 0, L_0x2b0ab3d072f8; 1 drivers -v0x11e8f50_0 .net/2u *"_s2", 0 0, L_0x2b0ab3d07340; 1 drivers -S_0x11e9030 .scope module, "overflowMux" "mux1" 3 68, 4 122 0, S_0xf2fc10; +L_0x2e29f60/d .functor XOR 1, L_0x2e29d40, L_0x2e33b40, C4<0>, C4<0>; +L_0x2e29f60 .delay 1 (30000,30000,30000) L_0x2e29f60/d; +L_0x2cc2b90/d .functor AND 1, L_0x2e29d40, L_0x2e33b40, C4<1>, C4<1>; +L_0x2cc2b90 .delay 1 (30000,30000,30000) L_0x2cc2b90/d; +v0x2cc2390_0 .net "a", 0 0, L_0x2e29d40; alias, 1 drivers +v0x2cc2460_0 .net "b", 0 0, L_0x2e33b40; alias, 1 drivers +v0x2cc2500_0 .net "carryout", 0 0, L_0x2cc2b90; alias, 1 drivers +v0x2cc25d0_0 .net "sum", 0 0, L_0x2e29f60; alias, 1 drivers +S_0x2cc4df0 .scope generate, "genblk2" "genblk2" 3 49, 3 49 0, S_0x2cb4420; + .timescale -9 -12; +L_0x2ac6110bdcf8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2ac6110bdd40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x2e298c0/d .functor OR 1, L_0x2ac6110bdcf8, L_0x2ac6110bdd40, C4<0>, C4<0>; +L_0x2e298c0 .delay 1 (30000,30000,30000) L_0x2e298c0/d; +v0x2cc4fe0_0 .net/2u *"_s0", 0 0, L_0x2ac6110bdcf8; 1 drivers +v0x2cc50c0_0 .net/2u *"_s2", 0 0, L_0x2ac6110bdd40; 1 drivers +S_0x2cc51a0 .scope module, "overflowMux" "mux1" 3 67, 4 122 0, S_0x26b20c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 1 "a" .port_info 2 /INPUT 1 "b" .port_info 3 /INPUT 1 "s" -L_0x13495d0/d .functor NOT 1, L_0x1349e60, C4<0>, C4<0>, C4<0>; -L_0x13495d0 .delay 1 (10000,10000,10000) L_0x13495d0/d; -L_0x1349470/d .functor AND 1, L_0x1349360, L_0x13495d0, C4<1>, C4<1>; -L_0x1349470 .delay 1 (30000,30000,30000) L_0x1349470/d; -L_0x1349ab0/d .functor AND 1, L_0x13410d0, L_0x1349e60, C4<1>, C4<1>; -L_0x1349ab0 .delay 1 (30000,30000,30000) L_0x1349ab0/d; -L_0x1349c60/d .functor OR 1, L_0x1349470, L_0x1349ab0, C4<0>, C4<0>; -L_0x1349c60 .delay 1 (30000,30000,30000) L_0x1349c60/d; -v0x10c78a0_0 .net "a", 0 0, L_0x1349360; alias, 1 drivers -v0x11e9450_0 .net "b", 0 0, L_0x13410d0; alias, 1 drivers -v0x11e9510_0 .net "out", 0 0, L_0x1349c60; alias, 1 drivers -v0x11e95b0_0 .net "s", 0 0, L_0x1349e60; 1 drivers -v0x11e9670_0 .net "s_", 0 0, L_0x13495d0; 1 drivers -v0x11e9780_0 .net "w0", 0 0, L_0x1349470; 1 drivers -v0x11e9840_0 .net "w1", 0 0, L_0x1349ab0; 1 drivers -S_0x11e9980 .scope module, "resultOr" "or32P" 3 76, 4 60 0, S_0xf2fc10; +L_0x2e3e110/d .functor NOT 1, L_0x2e3eba0, C4<0>, C4<0>, C4<0>; +L_0x2e3e110 .delay 1 (10000,10000,10000) L_0x2e3e110/d; +L_0x2e3e1d0/d .functor AND 1, L_0x2e361c0, L_0x2e3e110, C4<1>, C4<1>; +L_0x2e3e1d0 .delay 1 (30000,30000,30000) L_0x2e3e1d0/d; +L_0x2e3e330/d .functor AND 1, L_0x2e3dea0, L_0x2e3eba0, C4<1>, C4<1>; +L_0x2e3e330 .delay 1 (30000,30000,30000) L_0x2e3e330/d; +L_0x2e3e9a0/d .functor OR 1, L_0x2e3e1d0, L_0x2e3e330, C4<0>, C4<0>; +L_0x2e3e9a0 .delay 1 (30000,30000,30000) L_0x2e3e9a0/d; +v0x2b97380_0 .net "a", 0 0, L_0x2e361c0; alias, 1 drivers +v0x2cc55c0_0 .net "b", 0 0, L_0x2e3dea0; alias, 1 drivers +v0x2cc5680_0 .net "out", 0 0, L_0x2e3e9a0; alias, 1 drivers +v0x2cc5720_0 .net "s", 0 0, L_0x2e3eba0; 1 drivers +v0x2cc57e0_0 .net "s_", 0 0, L_0x2e3e110; 1 drivers +v0x2cc58f0_0 .net "w0", 0 0, L_0x2e3e1d0; 1 drivers +v0x2cc59b0_0 .net "w1", 0 0, L_0x2e3e330; 1 drivers +S_0x2cc5af0 .scope module, "resultOr" "or32P" 3 76, 4 60 0, S_0x26b20c0; .timescale -9 -12; .port_info 0 /OUTPUT 32 "out" .port_info 1 /INPUT 32 "A" .port_info 2 /INPUT 32 "B" -v0x11f2e10_0 .net "A", 31 0, L_0x133e830; alias, 1 drivers -v0x11f2f10_0 .net "B", 31 0, L_0x134a800; alias, 1 drivers -v0x11f2ff0_0 .net *"_s0", 0 0, L_0x134a370; 1 drivers -v0x11f30e0_0 .net *"_s100", 0 0, L_0x13505f0; 1 drivers -v0x11f31c0_0 .net *"_s104", 0 0, L_0x1350910; 1 drivers -v0x11f32f0_0 .net *"_s108", 0 0, L_0x1350c40; 1 drivers -v0x11f33d0_0 .net *"_s112", 0 0, L_0x1350f80; 1 drivers -v0x11f34b0_0 .net *"_s116", 0 0, L_0x1351280; 1 drivers -v0x11f3590_0 .net *"_s12", 0 0, L_0x134bfd0; 1 drivers -v0x11f3700_0 .net *"_s120", 0 0, L_0x134e690; 1 drivers -v0x11f37e0_0 .net *"_s124", 0 0, L_0x1352bd0; 1 drivers -v0x11f38c0_0 .net *"_s16", 0 0, L_0x134c330; 1 drivers -v0x11f39a0_0 .net *"_s20", 0 0, L_0x134c6a0; 1 drivers -v0x11f3a80_0 .net *"_s24", 0 0, L_0x134cb30; 1 drivers -v0x11f3b60_0 .net *"_s28", 0 0, L_0x134ce40; 1 drivers -v0x11f3c40_0 .net *"_s32", 0 0, L_0x134d150; 1 drivers -v0x11f3d20_0 .net *"_s36", 0 0, L_0x134bc80; 1 drivers -v0x11f3ed0_0 .net *"_s4", 0 0, L_0x134b930; 1 drivers -v0x11f3f70_0 .net *"_s40", 0 0, L_0x134d460; 1 drivers -v0x11f4050_0 .net *"_s44", 0 0, L_0x134d7a0; 1 drivers -v0x11f4130_0 .net *"_s48", 0 0, L_0x134daf0; 1 drivers -v0x11f4210_0 .net *"_s52", 0 0, L_0x134de50; 1 drivers -v0x11f42f0_0 .net *"_s56", 0 0, L_0x134e170; 1 drivers -v0x11f43d0_0 .net *"_s60", 0 0, L_0x134ea20; 1 drivers -v0x11f44b0_0 .net *"_s64", 0 0, L_0x134ed30; 1 drivers -v0x11f4590_0 .net *"_s68", 0 0, L_0x134ca20; 1 drivers -v0x11f4670_0 .net *"_s72", 0 0, L_0x134f040; 1 drivers -v0x11f4750_0 .net *"_s76", 0 0, L_0x134f340; 1 drivers -v0x11f4830_0 .net *"_s8", 0 0, L_0x134bd10; 1 drivers -v0x11f4910_0 .net *"_s80", 0 0, L_0x134f650; 1 drivers -v0x11f49f0_0 .net *"_s84", 0 0, L_0x134f970; 1 drivers -v0x11f4ad0_0 .net *"_s88", 0 0, L_0x134fca0; 1 drivers -v0x11f4bb0_0 .net *"_s92", 0 0, L_0x134ffe0; 1 drivers -v0x11f3e00_0 .net *"_s96", 0 0, L_0x13502e0; 1 drivers -v0x11f4e80_0 .net "out", 31 0, L_0x134e4a0; alias, 1 drivers -L_0x134b6e0 .part L_0x133e830, 0, 1; -L_0x134b840 .part L_0x134a800, 0, 1; -L_0x134b9f0 .part L_0x133e830, 1, 1; -L_0x134bbe0 .part L_0x134a800, 1, 1; -L_0x134bd80 .part L_0x133e830, 2, 1; -L_0x134bee0 .part L_0x134a800, 2, 1; -L_0x134c090 .part L_0x133e830, 3, 1; -L_0x134c1f0 .part L_0x134a800, 3, 1; -L_0x134c3f0 .part L_0x133e830, 4, 1; -L_0x134c550 .part L_0x134a800, 4, 1; -L_0x134c710 .part L_0x133e830, 5, 1; -L_0x134c980 .part L_0x134a800, 5, 1; -L_0x134cbf0 .part L_0x133e830, 6, 1; -L_0x134cd50 .part L_0x134a800, 6, 1; -L_0x134cf00 .part L_0x133e830, 7, 1; -L_0x134d060 .part L_0x134a800, 7, 1; -L_0x134d210 .part L_0x133e830, 8, 1; -L_0x134d370 .part L_0x134a800, 8, 1; -L_0x134d550 .part L_0x133e830, 9, 1; -L_0x134d6b0 .part L_0x134a800, 9, 1; -L_0x134d8a0 .part L_0x133e830, 10, 1; -L_0x134da00 .part L_0x134a800, 10, 1; -L_0x134dc00 .part L_0x133e830, 11, 1; -L_0x134dd60 .part L_0x134a800, 11, 1; -L_0x134df20 .part L_0x133e830, 12, 1; -L_0x134e080 .part L_0x134a800, 12, 1; -L_0x134e250 .part L_0x133e830, 13, 1; -L_0x134c870 .part L_0x134a800, 13, 1; -L_0x134e7d0 .part L_0x133e830, 14, 1; -L_0x134e930 .part L_0x134a800, 14, 1; -L_0x134eae0 .part L_0x133e830, 15, 1; -L_0x134ec40 .part L_0x134a800, 15, 1; -L_0x134edf0 .part L_0x133e830, 16, 1; -L_0x134ef50 .part L_0x134a800, 16, 1; -L_0x134f160 .part L_0x133e830, 17, 1; -L_0x134f250 .part L_0x134a800, 17, 1; -L_0x134f470 .part L_0x133e830, 18, 1; -L_0x134f560 .part L_0x134a800, 18, 1; -L_0x134f790 .part L_0x133e830, 19, 1; -L_0x134f880 .part L_0x134a800, 19, 1; -L_0x134fac0 .part L_0x133e830, 20, 1; -L_0x134fbb0 .part L_0x134a800, 20, 1; -L_0x134fe00 .part L_0x133e830, 21, 1; -L_0x134fef0 .part L_0x134a800, 21, 1; -L_0x1350150 .part L_0x133e830, 22, 1; -L_0x13501f0 .part L_0x134a800, 22, 1; -L_0x1350460 .part L_0x133e830, 23, 1; -L_0x1350500 .part L_0x134a800, 23, 1; -L_0x1350780 .part L_0x133e830, 24, 1; -L_0x1350820 .part L_0x134a800, 24, 1; -L_0x1350ab0 .part L_0x133e830, 25, 1; -L_0x1350b50 .part L_0x134a800, 25, 1; -L_0x1350df0 .part L_0x133e830, 26, 1; -L_0x1350e90 .part L_0x134a800, 26, 1; -L_0x1350d50 .part L_0x133e830, 27, 1; -L_0x1351190 .part L_0x134a800, 27, 1; -L_0x1351090 .part L_0x133e830, 28, 1; -L_0x13514a0 .part L_0x134a800, 28, 1; -L_0x1351340 .part L_0x133e830, 29, 1; -L_0x134e3b0 .part L_0x134a800, 29, 1; -L_0x1351590 .part L_0x133e830, 30, 1; -L_0x1351fe0 .part L_0x134a800, 30, 1; -LS_0x134e4a0_0_0 .concat8 [ 1 1 1 1], L_0x134a370, L_0x134b930, L_0x134bd10, L_0x134bfd0; -LS_0x134e4a0_0_4 .concat8 [ 1 1 1 1], L_0x134c330, L_0x134c6a0, L_0x134cb30, L_0x134ce40; -LS_0x134e4a0_0_8 .concat8 [ 1 1 1 1], L_0x134d150, L_0x134bc80, L_0x134d460, L_0x134d7a0; -LS_0x134e4a0_0_12 .concat8 [ 1 1 1 1], L_0x134daf0, L_0x134de50, L_0x134e170, L_0x134ea20; -LS_0x134e4a0_0_16 .concat8 [ 1 1 1 1], L_0x134ed30, L_0x134ca20, L_0x134f040, L_0x134f340; -LS_0x134e4a0_0_20 .concat8 [ 1 1 1 1], L_0x134f650, L_0x134f970, L_0x134fca0, L_0x134ffe0; -LS_0x134e4a0_0_24 .concat8 [ 1 1 1 1], L_0x13502e0, L_0x13505f0, L_0x1350910, L_0x1350c40; -LS_0x134e4a0_0_28 .concat8 [ 1 1 1 1], L_0x1350f80, L_0x1351280, L_0x134e690, L_0x1352bd0; -LS_0x134e4a0_1_0 .concat8 [ 4 4 4 4], LS_0x134e4a0_0_0, LS_0x134e4a0_0_4, LS_0x134e4a0_0_8, LS_0x134e4a0_0_12; -LS_0x134e4a0_1_4 .concat8 [ 4 4 4 4], LS_0x134e4a0_0_16, LS_0x134e4a0_0_20, LS_0x134e4a0_0_24, LS_0x134e4a0_0_28; -L_0x134e4a0 .concat8 [ 16 16 0 0], LS_0x134e4a0_1_0, LS_0x134e4a0_1_4; -L_0x1352ce0 .part L_0x133e830, 31, 1; -L_0x1352080 .part L_0x134a800, 31, 1; -S_0x11e9bc0 .scope generate, "or_slces[0]" "or_slces[0]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11e9dd0 .param/l "i" 0 4 63, +C4<00>; -L_0x134a370/d .functor OR 1, L_0x134b6e0, L_0x134b840, C4<0>, C4<0>; -L_0x134a370 .delay 1 (30000,30000,30000) L_0x134a370/d; -v0x11e9eb0_0 .net *"_s0", 0 0, L_0x134b6e0; 1 drivers -v0x11e9f90_0 .net *"_s1", 0 0, L_0x134b840; 1 drivers -S_0x11ea070 .scope generate, "or_slces[1]" "or_slces[1]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ea280 .param/l "i" 0 4 63, +C4<01>; -L_0x134b930/d .functor OR 1, L_0x134b9f0, L_0x134bbe0, C4<0>, C4<0>; -L_0x134b930 .delay 1 (30000,30000,30000) L_0x134b930/d; -v0x11ea340_0 .net *"_s0", 0 0, L_0x134b9f0; 1 drivers -v0x11ea420_0 .net *"_s1", 0 0, L_0x134bbe0; 1 drivers -S_0x11ea500 .scope generate, "or_slces[2]" "or_slces[2]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ea710 .param/l "i" 0 4 63, +C4<010>; -L_0x134bd10/d .functor OR 1, L_0x134bd80, L_0x134bee0, C4<0>, C4<0>; -L_0x134bd10 .delay 1 (30000,30000,30000) L_0x134bd10/d; -v0x11ea7b0_0 .net *"_s0", 0 0, L_0x134bd80; 1 drivers -v0x11ea890_0 .net *"_s1", 0 0, L_0x134bee0; 1 drivers -S_0x11ea970 .scope generate, "or_slces[3]" "or_slces[3]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11eab80 .param/l "i" 0 4 63, +C4<011>; -L_0x134bfd0/d .functor OR 1, L_0x134c090, L_0x134c1f0, C4<0>, C4<0>; -L_0x134bfd0 .delay 1 (30000,30000,30000) L_0x134bfd0/d; -v0x11eac40_0 .net *"_s0", 0 0, L_0x134c090; 1 drivers -v0x11ead20_0 .net *"_s1", 0 0, L_0x134c1f0; 1 drivers -S_0x11eae00 .scope generate, "or_slces[4]" "or_slces[4]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11eb060 .param/l "i" 0 4 63, +C4<0100>; -L_0x134c330/d .functor OR 1, L_0x134c3f0, L_0x134c550, C4<0>, C4<0>; -L_0x134c330 .delay 1 (30000,30000,30000) L_0x134c330/d; -v0x11eb120_0 .net *"_s0", 0 0, L_0x134c3f0; 1 drivers -v0x11eb200_0 .net *"_s1", 0 0, L_0x134c550; 1 drivers -S_0x11eb2e0 .scope generate, "or_slces[5]" "or_slces[5]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11eb4f0 .param/l "i" 0 4 63, +C4<0101>; -L_0x134c6a0/d .functor OR 1, L_0x134c710, L_0x134c980, C4<0>, C4<0>; -L_0x134c6a0 .delay 1 (30000,30000,30000) L_0x134c6a0/d; -v0x11eb5b0_0 .net *"_s0", 0 0, L_0x134c710; 1 drivers -v0x11eb690_0 .net *"_s1", 0 0, L_0x134c980; 1 drivers -S_0x11eb770 .scope generate, "or_slces[6]" "or_slces[6]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11eb980 .param/l "i" 0 4 63, +C4<0110>; -L_0x134cb30/d .functor OR 1, L_0x134cbf0, L_0x134cd50, C4<0>, C4<0>; -L_0x134cb30 .delay 1 (30000,30000,30000) L_0x134cb30/d; -v0x11eba40_0 .net *"_s0", 0 0, L_0x134cbf0; 1 drivers -v0x11ebb20_0 .net *"_s1", 0 0, L_0x134cd50; 1 drivers -S_0x11ebc00 .scope generate, "or_slces[7]" "or_slces[7]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ebe10 .param/l "i" 0 4 63, +C4<0111>; -L_0x134ce40/d .functor OR 1, L_0x134cf00, L_0x134d060, C4<0>, C4<0>; -L_0x134ce40 .delay 1 (30000,30000,30000) L_0x134ce40/d; -v0x11ebed0_0 .net *"_s0", 0 0, L_0x134cf00; 1 drivers -v0x11ebfb0_0 .net *"_s1", 0 0, L_0x134d060; 1 drivers -S_0x11ec090 .scope generate, "or_slces[8]" "or_slces[8]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11eb010 .param/l "i" 0 4 63, +C4<01000>; -L_0x134d150/d .functor OR 1, L_0x134d210, L_0x134d370, C4<0>, C4<0>; -L_0x134d150 .delay 1 (30000,30000,30000) L_0x134d150/d; -v0x11ec3a0_0 .net *"_s0", 0 0, L_0x134d210; 1 drivers -v0x11ec480_0 .net *"_s1", 0 0, L_0x134d370; 1 drivers -S_0x11ec560 .scope generate, "or_slces[9]" "or_slces[9]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ec770 .param/l "i" 0 4 63, +C4<01001>; -L_0x134bc80/d .functor OR 1, L_0x134d550, L_0x134d6b0, C4<0>, C4<0>; -L_0x134bc80 .delay 1 (30000,30000,30000) L_0x134bc80/d; -v0x11ec830_0 .net *"_s0", 0 0, L_0x134d550; 1 drivers -v0x11ec910_0 .net *"_s1", 0 0, L_0x134d6b0; 1 drivers -S_0x11ec9f0 .scope generate, "or_slces[10]" "or_slces[10]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ecc00 .param/l "i" 0 4 63, +C4<01010>; -L_0x134d460/d .functor OR 1, L_0x134d8a0, L_0x134da00, C4<0>, C4<0>; -L_0x134d460 .delay 1 (30000,30000,30000) L_0x134d460/d; -v0x11eccc0_0 .net *"_s0", 0 0, L_0x134d8a0; 1 drivers -v0x11ecda0_0 .net *"_s1", 0 0, L_0x134da00; 1 drivers -S_0x11ece80 .scope generate, "or_slces[11]" "or_slces[11]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ed090 .param/l "i" 0 4 63, +C4<01011>; -L_0x134d7a0/d .functor OR 1, L_0x134dc00, L_0x134dd60, C4<0>, C4<0>; -L_0x134d7a0 .delay 1 (30000,30000,30000) L_0x134d7a0/d; -v0x11ed150_0 .net *"_s0", 0 0, L_0x134dc00; 1 drivers -v0x11ed230_0 .net *"_s1", 0 0, L_0x134dd60; 1 drivers -S_0x11ed310 .scope generate, "or_slces[12]" "or_slces[12]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ed520 .param/l "i" 0 4 63, +C4<01100>; -L_0x134daf0/d .functor OR 1, L_0x134df20, L_0x134e080, C4<0>, C4<0>; -L_0x134daf0 .delay 1 (30000,30000,30000) L_0x134daf0/d; -v0x11ed5e0_0 .net *"_s0", 0 0, L_0x134df20; 1 drivers -v0x11ed6c0_0 .net *"_s1", 0 0, L_0x134e080; 1 drivers -S_0x11ed7a0 .scope generate, "or_slces[13]" "or_slces[13]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ed9b0 .param/l "i" 0 4 63, +C4<01101>; -L_0x134de50/d .functor OR 1, L_0x134e250, L_0x134c870, C4<0>, C4<0>; -L_0x134de50 .delay 1 (30000,30000,30000) L_0x134de50/d; -v0x11eda70_0 .net *"_s0", 0 0, L_0x134e250; 1 drivers -v0x11edb50_0 .net *"_s1", 0 0, L_0x134c870; 1 drivers -S_0x11edc30 .scope generate, "or_slces[14]" "or_slces[14]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ede40 .param/l "i" 0 4 63, +C4<01110>; -L_0x134e170/d .functor OR 1, L_0x134e7d0, L_0x134e930, C4<0>, C4<0>; -L_0x134e170 .delay 1 (30000,30000,30000) L_0x134e170/d; -v0x11edf00_0 .net *"_s0", 0 0, L_0x134e7d0; 1 drivers -v0x11edfe0_0 .net *"_s1", 0 0, L_0x134e930; 1 drivers -S_0x11ee0c0 .scope generate, "or_slces[15]" "or_slces[15]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ee2d0 .param/l "i" 0 4 63, +C4<01111>; -L_0x134ea20/d .functor OR 1, L_0x134eae0, L_0x134ec40, C4<0>, C4<0>; -L_0x134ea20 .delay 1 (30000,30000,30000) L_0x134ea20/d; -v0x11ee390_0 .net *"_s0", 0 0, L_0x134eae0; 1 drivers -v0x11ee470_0 .net *"_s1", 0 0, L_0x134ec40; 1 drivers -S_0x11ee550 .scope generate, "or_slces[16]" "or_slces[16]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ec2a0 .param/l "i" 0 4 63, +C4<010000>; -L_0x134ed30/d .functor OR 1, L_0x134edf0, L_0x134ef50, C4<0>, C4<0>; -L_0x134ed30 .delay 1 (30000,30000,30000) L_0x134ed30/d; -v0x11ee8c0_0 .net *"_s0", 0 0, L_0x134edf0; 1 drivers -v0x11ee980_0 .net *"_s1", 0 0, L_0x134ef50; 1 drivers -S_0x11eea60 .scope generate, "or_slces[17]" "or_slces[17]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11eec70 .param/l "i" 0 4 63, +C4<010001>; -L_0x134ca20/d .functor OR 1, L_0x134f160, L_0x134f250, C4<0>, C4<0>; -L_0x134ca20 .delay 1 (30000,30000,30000) L_0x134ca20/d; -v0x11eed30_0 .net *"_s0", 0 0, L_0x134f160; 1 drivers -v0x11eee10_0 .net *"_s1", 0 0, L_0x134f250; 1 drivers -S_0x11eeef0 .scope generate, "or_slces[18]" "or_slces[18]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ef100 .param/l "i" 0 4 63, +C4<010010>; -L_0x134f040/d .functor OR 1, L_0x134f470, L_0x134f560, C4<0>, C4<0>; -L_0x134f040 .delay 1 (30000,30000,30000) L_0x134f040/d; -v0x11ef1c0_0 .net *"_s0", 0 0, L_0x134f470; 1 drivers -v0x11ef2a0_0 .net *"_s1", 0 0, L_0x134f560; 1 drivers -S_0x11ef380 .scope generate, "or_slces[19]" "or_slces[19]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11ef590 .param/l "i" 0 4 63, +C4<010011>; -L_0x134f340/d .functor OR 1, L_0x134f790, L_0x134f880, C4<0>, C4<0>; -L_0x134f340 .delay 1 (30000,30000,30000) L_0x134f340/d; -v0x11ef650_0 .net *"_s0", 0 0, L_0x134f790; 1 drivers -v0x11ef730_0 .net *"_s1", 0 0, L_0x134f880; 1 drivers -S_0x11ef810 .scope generate, "or_slces[20]" "or_slces[20]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11efa20 .param/l "i" 0 4 63, +C4<010100>; -L_0x134f650/d .functor OR 1, L_0x134fac0, L_0x134fbb0, C4<0>, C4<0>; -L_0x134f650 .delay 1 (30000,30000,30000) L_0x134f650/d; -v0x11efae0_0 .net *"_s0", 0 0, L_0x134fac0; 1 drivers -v0x11efbc0_0 .net *"_s1", 0 0, L_0x134fbb0; 1 drivers -S_0x11efca0 .scope generate, "or_slces[21]" "or_slces[21]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11efeb0 .param/l "i" 0 4 63, +C4<010101>; -L_0x134f970/d .functor OR 1, L_0x134fe00, L_0x134fef0, C4<0>, C4<0>; -L_0x134f970 .delay 1 (30000,30000,30000) L_0x134f970/d; -v0x11eff70_0 .net *"_s0", 0 0, L_0x134fe00; 1 drivers -v0x11f0010_0 .net *"_s1", 0 0, L_0x134fef0; 1 drivers -S_0x11f00b0 .scope generate, "or_slces[22]" "or_slces[22]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f0280 .param/l "i" 0 4 63, +C4<010110>; -L_0x134fca0/d .functor OR 1, L_0x1350150, L_0x13501f0, C4<0>, C4<0>; -L_0x134fca0 .delay 1 (30000,30000,30000) L_0x134fca0/d; -v0x11f0340_0 .net *"_s0", 0 0, L_0x1350150; 1 drivers -v0x11f0420_0 .net *"_s1", 0 0, L_0x13501f0; 1 drivers -S_0x11f0500 .scope generate, "or_slces[23]" "or_slces[23]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f0710 .param/l "i" 0 4 63, +C4<010111>; -L_0x134ffe0/d .functor OR 1, L_0x1350460, L_0x1350500, C4<0>, C4<0>; -L_0x134ffe0 .delay 1 (30000,30000,30000) L_0x134ffe0/d; -v0x11f07d0_0 .net *"_s0", 0 0, L_0x1350460; 1 drivers -v0x11f08b0_0 .net *"_s1", 0 0, L_0x1350500; 1 drivers -S_0x11f0990 .scope generate, "or_slces[24]" "or_slces[24]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f0ba0 .param/l "i" 0 4 63, +C4<011000>; -L_0x13502e0/d .functor OR 1, L_0x1350780, L_0x1350820, C4<0>, C4<0>; -L_0x13502e0 .delay 1 (30000,30000,30000) L_0x13502e0/d; -v0x11f0c60_0 .net *"_s0", 0 0, L_0x1350780; 1 drivers -v0x11f0d40_0 .net *"_s1", 0 0, L_0x1350820; 1 drivers -S_0x11f0e20 .scope generate, "or_slces[25]" "or_slces[25]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f1030 .param/l "i" 0 4 63, +C4<011001>; -L_0x13505f0/d .functor OR 1, L_0x1350ab0, L_0x1350b50, C4<0>, C4<0>; -L_0x13505f0 .delay 1 (30000,30000,30000) L_0x13505f0/d; -v0x11f10f0_0 .net *"_s0", 0 0, L_0x1350ab0; 1 drivers -v0x11f11d0_0 .net *"_s1", 0 0, L_0x1350b50; 1 drivers -S_0x11f12b0 .scope generate, "or_slces[26]" "or_slces[26]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f14c0 .param/l "i" 0 4 63, +C4<011010>; -L_0x1350910/d .functor OR 1, L_0x1350df0, L_0x1350e90, C4<0>, C4<0>; -L_0x1350910 .delay 1 (30000,30000,30000) L_0x1350910/d; -v0x11f1580_0 .net *"_s0", 0 0, L_0x1350df0; 1 drivers -v0x11f1660_0 .net *"_s1", 0 0, L_0x1350e90; 1 drivers -S_0x11f1740 .scope generate, "or_slces[27]" "or_slces[27]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f1950 .param/l "i" 0 4 63, +C4<011011>; -L_0x1350c40/d .functor OR 1, L_0x1350d50, L_0x1351190, C4<0>, C4<0>; -L_0x1350c40 .delay 1 (30000,30000,30000) L_0x1350c40/d; -v0x11f1a10_0 .net *"_s0", 0 0, L_0x1350d50; 1 drivers -v0x11f1af0_0 .net *"_s1", 0 0, L_0x1351190; 1 drivers -S_0x11f1bd0 .scope generate, "or_slces[28]" "or_slces[28]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f1de0 .param/l "i" 0 4 63, +C4<011100>; -L_0x1350f80/d .functor OR 1, L_0x1351090, L_0x13514a0, C4<0>, C4<0>; -L_0x1350f80 .delay 1 (30000,30000,30000) L_0x1350f80/d; -v0x11f1ea0_0 .net *"_s0", 0 0, L_0x1351090; 1 drivers -v0x11f1f80_0 .net *"_s1", 0 0, L_0x13514a0; 1 drivers -S_0x11f2060 .scope generate, "or_slces[29]" "or_slces[29]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f2270 .param/l "i" 0 4 63, +C4<011101>; -L_0x1351280/d .functor OR 1, L_0x1351340, L_0x134e3b0, C4<0>, C4<0>; -L_0x1351280 .delay 1 (30000,30000,30000) L_0x1351280/d; -v0x11f2330_0 .net *"_s0", 0 0, L_0x1351340; 1 drivers -v0x11f2410_0 .net *"_s1", 0 0, L_0x134e3b0; 1 drivers -S_0x11f24f0 .scope generate, "or_slces[30]" "or_slces[30]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f2700 .param/l "i" 0 4 63, +C4<011110>; -L_0x134e690/d .functor OR 1, L_0x1351590, L_0x1351fe0, C4<0>, C4<0>; -L_0x134e690 .delay 1 (30000,30000,30000) L_0x134e690/d; -v0x11f27c0_0 .net *"_s0", 0 0, L_0x1351590; 1 drivers -v0x11f28a0_0 .net *"_s1", 0 0, L_0x1351fe0; 1 drivers -S_0x11f2980 .scope generate, "or_slces[31]" "or_slces[31]" 4 63, 4 63 0, S_0x11e9980; - .timescale -9 -12; -P_0x11f2b90 .param/l "i" 0 4 63, +C4<011111>; -L_0x1352bd0/d .functor OR 1, L_0x1352ce0, L_0x1352080, C4<0>, C4<0>; -L_0x1352bd0 .delay 1 (30000,30000,30000) L_0x1352bd0/d; -v0x11f2c50_0 .net *"_s0", 0 0, L_0x1352ce0; 1 drivers -v0x11f2d30_0 .net *"_s1", 0 0, L_0x1352080; 1 drivers -S_0x11f4fe0 .scope module, "zeroout" "and32" 3 63, 4 44 0, S_0xf2fc10; +v0x2ccef80_0 .net "A", 31 0, L_0x2e33830; alias, 1 drivers +v0x2ccf080_0 .net "B", 31 0, L_0x2e3f4f0; alias, 1 drivers +v0x2ccf160_0 .net *"_s0", 0 0, L_0x2e3f0b0; 1 drivers +v0x2ccf250_0 .net *"_s100", 0 0, L_0x2e452e0; 1 drivers +v0x2ccf330_0 .net *"_s104", 0 0, L_0x2e45600; 1 drivers +v0x2ccf460_0 .net *"_s108", 0 0, L_0x2e45930; 1 drivers +v0x2ccf540_0 .net *"_s112", 0 0, L_0x2e45c70; 1 drivers +v0x2ccf620_0 .net *"_s116", 0 0, L_0x2e45f70; 1 drivers +v0x2ccf700_0 .net *"_s12", 0 0, L_0x2e40cc0; 1 drivers +v0x2ccf870_0 .net *"_s120", 0 0, L_0x2e43380; 1 drivers +v0x2ccf950_0 .net *"_s124", 0 0, L_0x2e478c0; 1 drivers +v0x2ccfa30_0 .net *"_s16", 0 0, L_0x2e41020; 1 drivers +v0x2ccfb10_0 .net *"_s20", 0 0, L_0x2e41390; 1 drivers +v0x2ccfbf0_0 .net *"_s24", 0 0, L_0x2e41820; 1 drivers +v0x2ccfcd0_0 .net *"_s28", 0 0, L_0x2e41b30; 1 drivers +v0x2ccfdb0_0 .net *"_s32", 0 0, L_0x2e41e40; 1 drivers +v0x2ccfe90_0 .net *"_s36", 0 0, L_0x2e40970; 1 drivers +v0x2cd0040_0 .net *"_s4", 0 0, L_0x2e40620; 1 drivers +v0x2cd00e0_0 .net *"_s40", 0 0, L_0x2e42150; 1 drivers +v0x2cd01c0_0 .net *"_s44", 0 0, L_0x2e42490; 1 drivers +v0x2cd02a0_0 .net *"_s48", 0 0, L_0x2e427e0; 1 drivers +v0x2cd0380_0 .net *"_s52", 0 0, L_0x2e42b40; 1 drivers +v0x2cd0460_0 .net *"_s56", 0 0, L_0x2e42e60; 1 drivers +v0x2cd0540_0 .net *"_s60", 0 0, L_0x2e43710; 1 drivers +v0x2cd0620_0 .net *"_s64", 0 0, L_0x2e43a20; 1 drivers +v0x2cd0700_0 .net *"_s68", 0 0, L_0x2e41710; 1 drivers +v0x2cd07e0_0 .net *"_s72", 0 0, L_0x2e43d30; 1 drivers +v0x2cd08c0_0 .net *"_s76", 0 0, L_0x2e44030; 1 drivers +v0x2cd09a0_0 .net *"_s8", 0 0, L_0x2e40a00; 1 drivers +v0x2cd0a80_0 .net *"_s80", 0 0, L_0x2e44340; 1 drivers +v0x2cd0b60_0 .net *"_s84", 0 0, L_0x2e44660; 1 drivers +v0x2cd0c40_0 .net *"_s88", 0 0, L_0x2e44990; 1 drivers +v0x2cd0d20_0 .net *"_s92", 0 0, L_0x2e44cd0; 1 drivers +v0x2ccff70_0 .net *"_s96", 0 0, L_0x2e44fd0; 1 drivers +v0x2cd0ff0_0 .net "out", 31 0, L_0x2e43190; alias, 1 drivers +L_0x2e403d0 .part L_0x2e33830, 0, 1; +L_0x2e40530 .part L_0x2e3f4f0, 0, 1; +L_0x2e406e0 .part L_0x2e33830, 1, 1; +L_0x2e408d0 .part L_0x2e3f4f0, 1, 1; +L_0x2e40a70 .part L_0x2e33830, 2, 1; +L_0x2e40bd0 .part L_0x2e3f4f0, 2, 1; +L_0x2e40d80 .part L_0x2e33830, 3, 1; +L_0x2e40ee0 .part L_0x2e3f4f0, 3, 1; +L_0x2e410e0 .part L_0x2e33830, 4, 1; +L_0x2e41240 .part L_0x2e3f4f0, 4, 1; +L_0x2e41400 .part L_0x2e33830, 5, 1; +L_0x2e41670 .part L_0x2e3f4f0, 5, 1; +L_0x2e418e0 .part L_0x2e33830, 6, 1; +L_0x2e41a40 .part L_0x2e3f4f0, 6, 1; +L_0x2e41bf0 .part L_0x2e33830, 7, 1; +L_0x2e41d50 .part L_0x2e3f4f0, 7, 1; +L_0x2e41f00 .part L_0x2e33830, 8, 1; +L_0x2e42060 .part L_0x2e3f4f0, 8, 1; +L_0x2e42240 .part L_0x2e33830, 9, 1; +L_0x2e423a0 .part L_0x2e3f4f0, 9, 1; +L_0x2e42590 .part L_0x2e33830, 10, 1; +L_0x2e426f0 .part L_0x2e3f4f0, 10, 1; +L_0x2e428f0 .part L_0x2e33830, 11, 1; +L_0x2e42a50 .part L_0x2e3f4f0, 11, 1; +L_0x2e42c10 .part L_0x2e33830, 12, 1; +L_0x2e42d70 .part L_0x2e3f4f0, 12, 1; +L_0x2e42f40 .part L_0x2e33830, 13, 1; +L_0x2e41560 .part L_0x2e3f4f0, 13, 1; +L_0x2e434c0 .part L_0x2e33830, 14, 1; +L_0x2e43620 .part L_0x2e3f4f0, 14, 1; +L_0x2e437d0 .part L_0x2e33830, 15, 1; +L_0x2e43930 .part L_0x2e3f4f0, 15, 1; +L_0x2e43ae0 .part L_0x2e33830, 16, 1; +L_0x2e43c40 .part L_0x2e3f4f0, 16, 1; +L_0x2e43e50 .part L_0x2e33830, 17, 1; +L_0x2e43f40 .part L_0x2e3f4f0, 17, 1; +L_0x2e44160 .part L_0x2e33830, 18, 1; +L_0x2e44250 .part L_0x2e3f4f0, 18, 1; +L_0x2e44480 .part L_0x2e33830, 19, 1; +L_0x2e44570 .part L_0x2e3f4f0, 19, 1; +L_0x2e447b0 .part L_0x2e33830, 20, 1; +L_0x2e448a0 .part L_0x2e3f4f0, 20, 1; +L_0x2e44af0 .part L_0x2e33830, 21, 1; +L_0x2e44be0 .part L_0x2e3f4f0, 21, 1; +L_0x2e44e40 .part L_0x2e33830, 22, 1; +L_0x2e44ee0 .part L_0x2e3f4f0, 22, 1; +L_0x2e45150 .part L_0x2e33830, 23, 1; +L_0x2e451f0 .part L_0x2e3f4f0, 23, 1; +L_0x2e45470 .part L_0x2e33830, 24, 1; +L_0x2e45510 .part L_0x2e3f4f0, 24, 1; +L_0x2e457a0 .part L_0x2e33830, 25, 1; +L_0x2e45840 .part L_0x2e3f4f0, 25, 1; +L_0x2e45ae0 .part L_0x2e33830, 26, 1; +L_0x2e45b80 .part L_0x2e3f4f0, 26, 1; +L_0x2e45a40 .part L_0x2e33830, 27, 1; +L_0x2e45e80 .part L_0x2e3f4f0, 27, 1; +L_0x2e45d80 .part L_0x2e33830, 28, 1; +L_0x2e46190 .part L_0x2e3f4f0, 28, 1; +L_0x2e46030 .part L_0x2e33830, 29, 1; +L_0x2e430a0 .part L_0x2e3f4f0, 29, 1; +L_0x2e46280 .part L_0x2e33830, 30, 1; +L_0x2e46cd0 .part L_0x2e3f4f0, 30, 1; +LS_0x2e43190_0_0 .concat8 [ 1 1 1 1], L_0x2e3f0b0, L_0x2e40620, L_0x2e40a00, L_0x2e40cc0; +LS_0x2e43190_0_4 .concat8 [ 1 1 1 1], L_0x2e41020, L_0x2e41390, L_0x2e41820, L_0x2e41b30; +LS_0x2e43190_0_8 .concat8 [ 1 1 1 1], L_0x2e41e40, L_0x2e40970, L_0x2e42150, L_0x2e42490; +LS_0x2e43190_0_12 .concat8 [ 1 1 1 1], L_0x2e427e0, L_0x2e42b40, L_0x2e42e60, L_0x2e43710; +LS_0x2e43190_0_16 .concat8 [ 1 1 1 1], L_0x2e43a20, L_0x2e41710, L_0x2e43d30, L_0x2e44030; +LS_0x2e43190_0_20 .concat8 [ 1 1 1 1], L_0x2e44340, L_0x2e44660, L_0x2e44990, L_0x2e44cd0; +LS_0x2e43190_0_24 .concat8 [ 1 1 1 1], L_0x2e44fd0, L_0x2e452e0, L_0x2e45600, L_0x2e45930; +LS_0x2e43190_0_28 .concat8 [ 1 1 1 1], L_0x2e45c70, L_0x2e45f70, L_0x2e43380, L_0x2e478c0; +LS_0x2e43190_1_0 .concat8 [ 4 4 4 4], LS_0x2e43190_0_0, LS_0x2e43190_0_4, LS_0x2e43190_0_8, LS_0x2e43190_0_12; +LS_0x2e43190_1_4 .concat8 [ 4 4 4 4], LS_0x2e43190_0_16, LS_0x2e43190_0_20, LS_0x2e43190_0_24, LS_0x2e43190_0_28; +L_0x2e43190 .concat8 [ 16 16 0 0], LS_0x2e43190_1_0, LS_0x2e43190_1_4; +L_0x2e479d0 .part L_0x2e33830, 31, 1; +L_0x2e46d70 .part L_0x2e3f4f0, 31, 1; +S_0x2cc5d30 .scope generate, "or_slces[0]" "or_slces[0]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc5f40 .param/l "i" 0 4 63, +C4<00>; +L_0x2e3f0b0/d .functor OR 1, L_0x2e403d0, L_0x2e40530, C4<0>, C4<0>; +L_0x2e3f0b0 .delay 1 (30000,30000,30000) L_0x2e3f0b0/d; +v0x2cc6020_0 .net *"_s0", 0 0, L_0x2e403d0; 1 drivers +v0x2cc6100_0 .net *"_s1", 0 0, L_0x2e40530; 1 drivers +S_0x2cc61e0 .scope generate, "or_slces[1]" "or_slces[1]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc63f0 .param/l "i" 0 4 63, +C4<01>; +L_0x2e40620/d .functor OR 1, L_0x2e406e0, L_0x2e408d0, C4<0>, C4<0>; +L_0x2e40620 .delay 1 (30000,30000,30000) L_0x2e40620/d; +v0x2cc64b0_0 .net *"_s0", 0 0, L_0x2e406e0; 1 drivers +v0x2cc6590_0 .net *"_s1", 0 0, L_0x2e408d0; 1 drivers +S_0x2cc6670 .scope generate, "or_slces[2]" "or_slces[2]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc6880 .param/l "i" 0 4 63, +C4<010>; +L_0x2e40a00/d .functor OR 1, L_0x2e40a70, L_0x2e40bd0, C4<0>, C4<0>; +L_0x2e40a00 .delay 1 (30000,30000,30000) L_0x2e40a00/d; +v0x2cc6920_0 .net *"_s0", 0 0, L_0x2e40a70; 1 drivers +v0x2cc6a00_0 .net *"_s1", 0 0, L_0x2e40bd0; 1 drivers +S_0x2cc6ae0 .scope generate, "or_slces[3]" "or_slces[3]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc6cf0 .param/l "i" 0 4 63, +C4<011>; +L_0x2e40cc0/d .functor OR 1, L_0x2e40d80, L_0x2e40ee0, C4<0>, C4<0>; +L_0x2e40cc0 .delay 1 (30000,30000,30000) L_0x2e40cc0/d; +v0x2cc6db0_0 .net *"_s0", 0 0, L_0x2e40d80; 1 drivers +v0x2cc6e90_0 .net *"_s1", 0 0, L_0x2e40ee0; 1 drivers +S_0x2cc6f70 .scope generate, "or_slces[4]" "or_slces[4]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc71d0 .param/l "i" 0 4 63, +C4<0100>; +L_0x2e41020/d .functor OR 1, L_0x2e410e0, L_0x2e41240, C4<0>, C4<0>; +L_0x2e41020 .delay 1 (30000,30000,30000) L_0x2e41020/d; +v0x2cc7290_0 .net *"_s0", 0 0, L_0x2e410e0; 1 drivers +v0x2cc7370_0 .net *"_s1", 0 0, L_0x2e41240; 1 drivers +S_0x2cc7450 .scope generate, "or_slces[5]" "or_slces[5]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc7660 .param/l "i" 0 4 63, +C4<0101>; +L_0x2e41390/d .functor OR 1, L_0x2e41400, L_0x2e41670, C4<0>, C4<0>; +L_0x2e41390 .delay 1 (30000,30000,30000) L_0x2e41390/d; +v0x2cc7720_0 .net *"_s0", 0 0, L_0x2e41400; 1 drivers +v0x2cc7800_0 .net *"_s1", 0 0, L_0x2e41670; 1 drivers +S_0x2cc78e0 .scope generate, "or_slces[6]" "or_slces[6]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc7af0 .param/l "i" 0 4 63, +C4<0110>; +L_0x2e41820/d .functor OR 1, L_0x2e418e0, L_0x2e41a40, C4<0>, C4<0>; +L_0x2e41820 .delay 1 (30000,30000,30000) L_0x2e41820/d; +v0x2cc7bb0_0 .net *"_s0", 0 0, L_0x2e418e0; 1 drivers +v0x2cc7c90_0 .net *"_s1", 0 0, L_0x2e41a40; 1 drivers +S_0x2cc7d70 .scope generate, "or_slces[7]" "or_slces[7]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc7f80 .param/l "i" 0 4 63, +C4<0111>; +L_0x2e41b30/d .functor OR 1, L_0x2e41bf0, L_0x2e41d50, C4<0>, C4<0>; +L_0x2e41b30 .delay 1 (30000,30000,30000) L_0x2e41b30/d; +v0x2cc8020_0 .net *"_s0", 0 0, L_0x2e41bf0; 1 drivers +v0x2cc80c0_0 .net *"_s1", 0 0, L_0x2e41d50; 1 drivers +S_0x2cc8160 .scope generate, "or_slces[8]" "or_slces[8]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc7180 .param/l "i" 0 4 63, +C4<01000>; +L_0x2e41e40/d .functor OR 1, L_0x2e41f00, L_0x2e42060, C4<0>, C4<0>; +L_0x2e41e40 .delay 1 (30000,30000,30000) L_0x2e41e40/d; +v0x2cc8450_0 .net *"_s0", 0 0, L_0x2e41f00; 1 drivers +v0x2cc8530_0 .net *"_s1", 0 0, L_0x2e42060; 1 drivers +S_0x2cc8610 .scope generate, "or_slces[9]" "or_slces[9]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc8820 .param/l "i" 0 4 63, +C4<01001>; +L_0x2e40970/d .functor OR 1, L_0x2e42240, L_0x2e423a0, C4<0>, C4<0>; +L_0x2e40970 .delay 1 (30000,30000,30000) L_0x2e40970/d; +v0x2cc88e0_0 .net *"_s0", 0 0, L_0x2e42240; 1 drivers +v0x2cc89c0_0 .net *"_s1", 0 0, L_0x2e423a0; 1 drivers +S_0x2cc8aa0 .scope generate, "or_slces[10]" "or_slces[10]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc8cb0 .param/l "i" 0 4 63, +C4<01010>; +L_0x2e42150/d .functor OR 1, L_0x2e42590, L_0x2e426f0, C4<0>, C4<0>; +L_0x2e42150 .delay 1 (30000,30000,30000) L_0x2e42150/d; +v0x2cc8d70_0 .net *"_s0", 0 0, L_0x2e42590; 1 drivers +v0x2cc8e50_0 .net *"_s1", 0 0, L_0x2e426f0; 1 drivers +S_0x2cc8f30 .scope generate, "or_slces[11]" "or_slces[11]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc9140 .param/l "i" 0 4 63, +C4<01011>; +L_0x2e42490/d .functor OR 1, L_0x2e428f0, L_0x2e42a50, C4<0>, C4<0>; +L_0x2e42490 .delay 1 (30000,30000,30000) L_0x2e42490/d; +v0x2cc9200_0 .net *"_s0", 0 0, L_0x2e428f0; 1 drivers +v0x2cc92e0_0 .net *"_s1", 0 0, L_0x2e42a50; 1 drivers +S_0x2cc93c0 .scope generate, "or_slces[12]" "or_slces[12]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc95d0 .param/l "i" 0 4 63, +C4<01100>; +L_0x2e427e0/d .functor OR 1, L_0x2e42c10, L_0x2e42d70, C4<0>, C4<0>; +L_0x2e427e0 .delay 1 (30000,30000,30000) L_0x2e427e0/d; +v0x2cc9690_0 .net *"_s0", 0 0, L_0x2e42c10; 1 drivers +v0x2cc9770_0 .net *"_s1", 0 0, L_0x2e42d70; 1 drivers +S_0x2cc9850 .scope generate, "or_slces[13]" "or_slces[13]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc9a60 .param/l "i" 0 4 63, +C4<01101>; +L_0x2e42b40/d .functor OR 1, L_0x2e42f40, L_0x2e41560, C4<0>, C4<0>; +L_0x2e42b40 .delay 1 (30000,30000,30000) L_0x2e42b40/d; +v0x2cc9b20_0 .net *"_s0", 0 0, L_0x2e42f40; 1 drivers +v0x2cc9c00_0 .net *"_s1", 0 0, L_0x2e41560; 1 drivers +S_0x2cc9ce0 .scope generate, "or_slces[14]" "or_slces[14]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc9ef0 .param/l "i" 0 4 63, +C4<01110>; +L_0x2e42e60/d .functor OR 1, L_0x2e434c0, L_0x2e43620, C4<0>, C4<0>; +L_0x2e42e60 .delay 1 (30000,30000,30000) L_0x2e42e60/d; +v0x2cc9fb0_0 .net *"_s0", 0 0, L_0x2e434c0; 1 drivers +v0x2cca090_0 .net *"_s1", 0 0, L_0x2e43620; 1 drivers +S_0x2cca170 .scope generate, "or_slces[15]" "or_slces[15]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cca380 .param/l "i" 0 4 63, +C4<01111>; +L_0x2e43710/d .functor OR 1, L_0x2e437d0, L_0x2e43930, C4<0>, C4<0>; +L_0x2e43710 .delay 1 (30000,30000,30000) L_0x2e43710/d; +v0x2cca440_0 .net *"_s0", 0 0, L_0x2e437d0; 1 drivers +v0x2cca520_0 .net *"_s1", 0 0, L_0x2e43930; 1 drivers +S_0x2cca600 .scope generate, "or_slces[16]" "or_slces[16]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cc8350 .param/l "i" 0 4 63, +C4<010000>; +L_0x2e43a20/d .functor OR 1, L_0x2e43ae0, L_0x2e43c40, C4<0>, C4<0>; +L_0x2e43a20 .delay 1 (30000,30000,30000) L_0x2e43a20/d; +v0x2cca970_0 .net *"_s0", 0 0, L_0x2e43ae0; 1 drivers +v0x2ccaa30_0 .net *"_s1", 0 0, L_0x2e43c40; 1 drivers +S_0x2ccab10 .scope generate, "or_slces[17]" "or_slces[17]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccad20 .param/l "i" 0 4 63, +C4<010001>; +L_0x2e41710/d .functor OR 1, L_0x2e43e50, L_0x2e43f40, C4<0>, C4<0>; +L_0x2e41710 .delay 1 (30000,30000,30000) L_0x2e41710/d; +v0x2ccade0_0 .net *"_s0", 0 0, L_0x2e43e50; 1 drivers +v0x2ccaec0_0 .net *"_s1", 0 0, L_0x2e43f40; 1 drivers +S_0x2ccafa0 .scope generate, "or_slces[18]" "or_slces[18]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccb1b0 .param/l "i" 0 4 63, +C4<010010>; +L_0x2e43d30/d .functor OR 1, L_0x2e44160, L_0x2e44250, C4<0>, C4<0>; +L_0x2e43d30 .delay 1 (30000,30000,30000) L_0x2e43d30/d; +v0x2ccb270_0 .net *"_s0", 0 0, L_0x2e44160; 1 drivers +v0x2ccb350_0 .net *"_s1", 0 0, L_0x2e44250; 1 drivers +S_0x2ccb430 .scope generate, "or_slces[19]" "or_slces[19]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccb640 .param/l "i" 0 4 63, +C4<010011>; +L_0x2e44030/d .functor OR 1, L_0x2e44480, L_0x2e44570, C4<0>, C4<0>; +L_0x2e44030 .delay 1 (30000,30000,30000) L_0x2e44030/d; +v0x2ccb700_0 .net *"_s0", 0 0, L_0x2e44480; 1 drivers +v0x2ccb7e0_0 .net *"_s1", 0 0, L_0x2e44570; 1 drivers +S_0x2ccb8c0 .scope generate, "or_slces[20]" "or_slces[20]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccbad0 .param/l "i" 0 4 63, +C4<010100>; +L_0x2e44340/d .functor OR 1, L_0x2e447b0, L_0x2e448a0, C4<0>, C4<0>; +L_0x2e44340 .delay 1 (30000,30000,30000) L_0x2e44340/d; +v0x2ccbb90_0 .net *"_s0", 0 0, L_0x2e447b0; 1 drivers +v0x2ccbc70_0 .net *"_s1", 0 0, L_0x2e448a0; 1 drivers +S_0x2ccbd50 .scope generate, "or_slces[21]" "or_slces[21]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccbf60 .param/l "i" 0 4 63, +C4<010101>; +L_0x2e44660/d .functor OR 1, L_0x2e44af0, L_0x2e44be0, C4<0>, C4<0>; +L_0x2e44660 .delay 1 (30000,30000,30000) L_0x2e44660/d; +v0x2ccc020_0 .net *"_s0", 0 0, L_0x2e44af0; 1 drivers +v0x2ccc100_0 .net *"_s1", 0 0, L_0x2e44be0; 1 drivers +S_0x2ccc1e0 .scope generate, "or_slces[22]" "or_slces[22]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccc3f0 .param/l "i" 0 4 63, +C4<010110>; +L_0x2e44990/d .functor OR 1, L_0x2e44e40, L_0x2e44ee0, C4<0>, C4<0>; +L_0x2e44990 .delay 1 (30000,30000,30000) L_0x2e44990/d; +v0x2ccc4b0_0 .net *"_s0", 0 0, L_0x2e44e40; 1 drivers +v0x2ccc590_0 .net *"_s1", 0 0, L_0x2e44ee0; 1 drivers +S_0x2ccc670 .scope generate, "or_slces[23]" "or_slces[23]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccc880 .param/l "i" 0 4 63, +C4<010111>; +L_0x2e44cd0/d .functor OR 1, L_0x2e45150, L_0x2e451f0, C4<0>, C4<0>; +L_0x2e44cd0 .delay 1 (30000,30000,30000) L_0x2e44cd0/d; +v0x2ccc940_0 .net *"_s0", 0 0, L_0x2e45150; 1 drivers +v0x2ccca20_0 .net *"_s1", 0 0, L_0x2e451f0; 1 drivers +S_0x2cccb00 .scope generate, "or_slces[24]" "or_slces[24]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cccd10 .param/l "i" 0 4 63, +C4<011000>; +L_0x2e44fd0/d .functor OR 1, L_0x2e45470, L_0x2e45510, C4<0>, C4<0>; +L_0x2e44fd0 .delay 1 (30000,30000,30000) L_0x2e44fd0/d; +v0x2cccdd0_0 .net *"_s0", 0 0, L_0x2e45470; 1 drivers +v0x2ccceb0_0 .net *"_s1", 0 0, L_0x2e45510; 1 drivers +S_0x2cccf90 .scope generate, "or_slces[25]" "or_slces[25]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccd1a0 .param/l "i" 0 4 63, +C4<011001>; +L_0x2e452e0/d .functor OR 1, L_0x2e457a0, L_0x2e45840, C4<0>, C4<0>; +L_0x2e452e0 .delay 1 (30000,30000,30000) L_0x2e452e0/d; +v0x2ccd260_0 .net *"_s0", 0 0, L_0x2e457a0; 1 drivers +v0x2ccd340_0 .net *"_s1", 0 0, L_0x2e45840; 1 drivers +S_0x2ccd420 .scope generate, "or_slces[26]" "or_slces[26]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccd630 .param/l "i" 0 4 63, +C4<011010>; +L_0x2e45600/d .functor OR 1, L_0x2e45ae0, L_0x2e45b80, C4<0>, C4<0>; +L_0x2e45600 .delay 1 (30000,30000,30000) L_0x2e45600/d; +v0x2ccd6f0_0 .net *"_s0", 0 0, L_0x2e45ae0; 1 drivers +v0x2ccd7d0_0 .net *"_s1", 0 0, L_0x2e45b80; 1 drivers +S_0x2ccd8b0 .scope generate, "or_slces[27]" "or_slces[27]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccdac0 .param/l "i" 0 4 63, +C4<011011>; +L_0x2e45930/d .functor OR 1, L_0x2e45a40, L_0x2e45e80, C4<0>, C4<0>; +L_0x2e45930 .delay 1 (30000,30000,30000) L_0x2e45930/d; +v0x2ccdb80_0 .net *"_s0", 0 0, L_0x2e45a40; 1 drivers +v0x2ccdc60_0 .net *"_s1", 0 0, L_0x2e45e80; 1 drivers +S_0x2ccdd40 .scope generate, "or_slces[28]" "or_slces[28]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2ccdf50 .param/l "i" 0 4 63, +C4<011100>; +L_0x2e45c70/d .functor OR 1, L_0x2e45d80, L_0x2e46190, C4<0>, C4<0>; +L_0x2e45c70 .delay 1 (30000,30000,30000) L_0x2e45c70/d; +v0x2cce010_0 .net *"_s0", 0 0, L_0x2e45d80; 1 drivers +v0x2cce0f0_0 .net *"_s1", 0 0, L_0x2e46190; 1 drivers +S_0x2cce1d0 .scope generate, "or_slces[29]" "or_slces[29]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cce3e0 .param/l "i" 0 4 63, +C4<011101>; +L_0x2e45f70/d .functor OR 1, L_0x2e46030, L_0x2e430a0, C4<0>, C4<0>; +L_0x2e45f70 .delay 1 (30000,30000,30000) L_0x2e45f70/d; +v0x2cce4a0_0 .net *"_s0", 0 0, L_0x2e46030; 1 drivers +v0x2cce580_0 .net *"_s1", 0 0, L_0x2e430a0; 1 drivers +S_0x2cce660 .scope generate, "or_slces[30]" "or_slces[30]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cce870 .param/l "i" 0 4 63, +C4<011110>; +L_0x2e43380/d .functor OR 1, L_0x2e46280, L_0x2e46cd0, C4<0>, C4<0>; +L_0x2e43380 .delay 1 (30000,30000,30000) L_0x2e43380/d; +v0x2cce930_0 .net *"_s0", 0 0, L_0x2e46280; 1 drivers +v0x2ccea10_0 .net *"_s1", 0 0, L_0x2e46cd0; 1 drivers +S_0x2cceaf0 .scope generate, "or_slces[31]" "or_slces[31]" 4 63, 4 63 0, S_0x2cc5af0; + .timescale -9 -12; +P_0x2cced00 .param/l "i" 0 4 63, +C4<011111>; +L_0x2e478c0/d .functor OR 1, L_0x2e479d0, L_0x2e46d70, C4<0>, C4<0>; +L_0x2e478c0 .delay 1 (30000,30000,30000) L_0x2e478c0/d; +v0x2ccedc0_0 .net *"_s0", 0 0, L_0x2e479d0; 1 drivers +v0x2cceea0_0 .net *"_s1", 0 0, L_0x2e46d70; 1 drivers +S_0x2cd1150 .scope module, "zeroout" "and32" 3 61, 4 44 0, S_0x26b20c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 32 "in" -L_0x1348e30/d .functor AND 1, L_0x1348ea0, L_0x1349050, C4<1>, C4<1>; -L_0x1348e30 .delay 1 (30000,30000,30000) L_0x1348e30/d; -v0x11fe0a0_0 .net *"_s10", 0 0, L_0x1348ea0; 1 drivers -v0x11fe180_0 .net *"_s12", 0 0, L_0x1349050; 1 drivers -v0x11fe260_0 .net "ands", 1 0, L_0x1348bc0; 1 drivers -v0x11fe320_0 .net "in", 31 0, L_0x1295d80; alias, 1 drivers -v0x11fe400_0 .net "out", 0 0, L_0x1348e30; alias, 1 drivers -L_0x1344b50 .part L_0x1295d80, 0, 16; -L_0x1348bc0 .concat8 [ 1 1 0 0], L_0x13447f0, L_0x1348860; -L_0x1348d00 .part L_0x1295d80, 16, 16; -L_0x1348ea0 .part L_0x1348bc0, 0, 1; -L_0x1349050 .part L_0x1348bc0, 1, 1; -S_0x11f51a0 .scope module, "and_1" "and16" 4 46, 4 37 0, S_0x11f4fe0; +L_0x2e3db90/d .functor AND 1, L_0x2e3dc00, L_0x2e3ddb0, C4<1>, C4<1>; +L_0x2e3db90 .delay 1 (30000,30000,30000) L_0x2e3db90/d; +v0x2cda210_0 .net *"_s10", 0 0, L_0x2e3dc00; 1 drivers +v0x2cda2f0_0 .net *"_s12", 0 0, L_0x2e3ddb0; 1 drivers +v0x2cda3d0_0 .net "ands", 1 0, L_0x2e3d920; 1 drivers +v0x2cda490_0 .net "in", 31 0, L_0x2d7dd90; alias, 1 drivers +v0x2cda570_0 .net "out", 0 0, L_0x2e3db90; alias, 1 drivers +L_0x2e398b0 .part L_0x2d7dd90, 0, 16; +L_0x2e3d920 .concat8 [ 1 1 0 0], L_0x2e39550, L_0x2e3d5c0; +L_0x2e3da60 .part L_0x2d7dd90, 16, 16; +L_0x2e3dc00 .part L_0x2e3d920, 0, 1; +L_0x2e3ddb0 .part L_0x2e3d920, 1, 1; +S_0x2cd1310 .scope module, "and_1" "and16" 4 46, 4 37 0, S_0x2cd1150; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 16 "in" -L_0x13447f0/d .functor AND 1, L_0x13448b0, L_0x1344a60, C4<1>, C4<1>; -L_0x13447f0 .delay 1 (30000,30000,30000) L_0x13447f0/d; -v0x11f9470_0 .net *"_s10", 0 0, L_0x13448b0; 1 drivers -v0x11f9550_0 .net *"_s12", 0 0, L_0x1344a60; 1 drivers -v0x11f9630_0 .net "ands", 1 0, L_0x13445c0; 1 drivers -v0x11f96f0_0 .net "in", 15 0, L_0x1344b50; 1 drivers -v0x11f97d0_0 .net "out", 0 0, L_0x13447f0; 1 drivers -L_0x1342850 .part L_0x1344b50, 0, 8; -L_0x13445c0 .concat8 [ 1 1 0 0], L_0x13424f0, L_0x1344260; -L_0x1344700 .part L_0x1344b50, 8, 8; -L_0x13448b0 .part L_0x13445c0, 0, 1; -L_0x1344a60 .part L_0x13445c0, 1, 1; -S_0x11f53f0 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x11f51a0; +L_0x2e39550/d .functor AND 1, L_0x2e39610, L_0x2e397c0, C4<1>, C4<1>; +L_0x2e39550 .delay 1 (30000,30000,30000) L_0x2e39550/d; +v0x2cd55e0_0 .net *"_s10", 0 0, L_0x2e39610; 1 drivers +v0x2cd56c0_0 .net *"_s12", 0 0, L_0x2e397c0; 1 drivers +v0x2cd57a0_0 .net "ands", 1 0, L_0x2e39320; 1 drivers +v0x2cd5860_0 .net "in", 15 0, L_0x2e398b0; 1 drivers +v0x2cd5940_0 .net "out", 0 0, L_0x2e39550; 1 drivers +L_0x2e375b0 .part L_0x2e398b0, 0, 8; +L_0x2e39320 .concat8 [ 1 1 0 0], L_0x2e37250, L_0x2e38fc0; +L_0x2e39460 .part L_0x2e398b0, 8, 8; +L_0x2e39610 .part L_0x2e39320, 0, 1; +L_0x2e397c0 .part L_0x2e39320, 1, 1; +S_0x2cd1560 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x2cd1310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x13424f0/d .functor AND 1, L_0x13425b0, L_0x1342760, C4<1>, C4<1>; -L_0x13424f0 .delay 1 (30000,30000,30000) L_0x13424f0/d; -v0x11f6fd0_0 .net *"_s10", 0 0, L_0x13425b0; 1 drivers -v0x11f70b0_0 .net *"_s12", 0 0, L_0x1342760; 1 drivers -v0x11f7190_0 .net "ands", 1 0, L_0x13422c0; 1 drivers -v0x11f7250_0 .net "in", 7 0, L_0x1342850; 1 drivers -v0x11f7330_0 .net "out", 0 0, L_0x13424f0; 1 drivers -L_0x1341970 .part L_0x1342850, 0, 4; -L_0x13422c0 .concat8 [ 1 1 0 0], L_0x13417c0, L_0x1341fb0; -L_0x1342400 .part L_0x1342850, 4, 4; -L_0x13425b0 .part L_0x13422c0, 0, 1; -L_0x1342760 .part L_0x13422c0, 1, 1; -S_0x11f5640 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11f53f0; +L_0x2e37250/d .functor AND 1, L_0x2e37310, L_0x2e374c0, C4<1>, C4<1>; +L_0x2e37250 .delay 1 (30000,30000,30000) L_0x2e37250/d; +v0x2cd3140_0 .net *"_s10", 0 0, L_0x2e37310; 1 drivers +v0x2cd3220_0 .net *"_s12", 0 0, L_0x2e374c0; 1 drivers +v0x2cd3300_0 .net "ands", 1 0, L_0x2e370c0; 1 drivers +v0x2cd33c0_0 .net "in", 7 0, L_0x2e375b0; 1 drivers +v0x2cd34a0_0 .net "out", 0 0, L_0x2e37250; 1 drivers +L_0x2e369e0 .part L_0x2e375b0, 0, 4; +L_0x2e370c0 .concat8 [ 1 1 0 0], L_0x2e36830, L_0x2e36f10; +L_0x2e37160 .part L_0x2e375b0, 4, 4; +L_0x2e37310 .part L_0x2e370c0, 0, 1; +L_0x2e374c0 .part L_0x2e370c0, 1, 1; +S_0x2cd17b0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x2cd1560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x13400c0/d .functor AND 1, L_0x1341410, L_0x13414b0, C4<1>, C4<1>; -L_0x13400c0 .delay 1 (30000,30000,30000) L_0x13400c0/d; -L_0x129fec0/d .functor AND 1, L_0x13415f0, L_0x1341690, C4<1>, C4<1>; -L_0x129fec0 .delay 1 (30000,30000,30000) L_0x129fec0/d; -L_0x13417c0/d .functor AND 1, L_0x1341830, L_0x13418d0, C4<1>, C4<1>; -L_0x13417c0 .delay 1 (30000,30000,30000) L_0x13417c0/d; -v0x11f5890_0 .net *"_s0", 0 0, L_0x13400c0; 1 drivers -v0x11f5990_0 .net *"_s10", 0 0, L_0x13415f0; 1 drivers -v0x11f5a70_0 .net *"_s12", 0 0, L_0x1341690; 1 drivers -v0x11f5b30_0 .net *"_s14", 0 0, L_0x1341830; 1 drivers -v0x11f5c10_0 .net *"_s16", 0 0, L_0x13418d0; 1 drivers -v0x11f5d40_0 .net *"_s3", 0 0, L_0x1341410; 1 drivers -v0x11f5e20_0 .net *"_s5", 0 0, L_0x13414b0; 1 drivers -v0x11f5f00_0 .net *"_s6", 0 0, L_0x129fec0; 1 drivers -v0x11f5fe0_0 .net "ands", 1 0, L_0x1341550; 1 drivers -v0x11f6150_0 .net "in", 3 0, L_0x1341970; 1 drivers -v0x11f6230_0 .net "out", 0 0, L_0x13417c0; 1 drivers -L_0x1341410 .part L_0x1341970, 0, 1; -L_0x13414b0 .part L_0x1341970, 1, 1; -L_0x1341550 .concat8 [ 1 1 0 0], L_0x13400c0, L_0x129fec0; -L_0x13415f0 .part L_0x1341970, 2, 1; -L_0x1341690 .part L_0x1341970, 3, 1; -L_0x1341830 .part L_0x1341550, 0, 1; -L_0x13418d0 .part L_0x1341550, 1, 1; -S_0x11f6350 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11f53f0; +L_0x2e350c0/d .functor AND 1, L_0x2e36410, L_0x2e364b0, C4<1>, C4<1>; +L_0x2e350c0 .delay 1 (30000,30000,30000) L_0x2e350c0/d; +L_0x2e365f0/d .functor AND 1, L_0x2e36660, L_0x2e36700, C4<1>, C4<1>; +L_0x2e365f0 .delay 1 (30000,30000,30000) L_0x2e365f0/d; +L_0x2e36830/d .functor AND 1, L_0x2e368a0, L_0x2e36940, C4<1>, C4<1>; +L_0x2e36830 .delay 1 (30000,30000,30000) L_0x2e36830/d; +v0x2cd1a00_0 .net *"_s0", 0 0, L_0x2e350c0; 1 drivers +v0x2cd1b00_0 .net *"_s10", 0 0, L_0x2e36660; 1 drivers +v0x2cd1be0_0 .net *"_s12", 0 0, L_0x2e36700; 1 drivers +v0x2cd1ca0_0 .net *"_s14", 0 0, L_0x2e368a0; 1 drivers +v0x2cd1d80_0 .net *"_s16", 0 0, L_0x2e36940; 1 drivers +v0x2cd1eb0_0 .net *"_s3", 0 0, L_0x2e36410; 1 drivers +v0x2cd1f90_0 .net *"_s5", 0 0, L_0x2e364b0; 1 drivers +v0x2cd2070_0 .net *"_s6", 0 0, L_0x2e365f0; 1 drivers +v0x2cd2150_0 .net "ands", 1 0, L_0x2e36550; 1 drivers +v0x2cd22c0_0 .net "in", 3 0, L_0x2e369e0; 1 drivers +v0x2cd23a0_0 .net "out", 0 0, L_0x2e36830; 1 drivers +L_0x2e36410 .part L_0x2e369e0, 0, 1; +L_0x2e364b0 .part L_0x2e369e0, 1, 1; +L_0x2e36550 .concat8 [ 1 1 0 0], L_0x2e350c0, L_0x2e365f0; +L_0x2e36660 .part L_0x2e369e0, 2, 1; +L_0x2e36700 .part L_0x2e369e0, 3, 1; +L_0x2e368a0 .part L_0x2e36550, 0, 1; +L_0x2e36940 .part L_0x2e36550, 1, 1; +S_0x2cd24c0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x2cd1560; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1341a10/d .functor AND 1, L_0x1341a80, L_0x1341b20, C4<1>, C4<1>; -L_0x1341a10 .delay 1 (30000,30000,30000) L_0x1341a10/d; -L_0x1341c60/d .functor AND 1, L_0x1341cd0, L_0x1341e30, C4<1>, C4<1>; -L_0x1341c60 .delay 1 (30000,30000,30000) L_0x1341c60/d; -L_0x1341fb0/d .functor AND 1, L_0x1342020, L_0x13421d0, C4<1>, C4<1>; -L_0x1341fb0 .delay 1 (30000,30000,30000) L_0x1341fb0/d; -v0x11f6510_0 .net *"_s0", 0 0, L_0x1341a10; 1 drivers -v0x11f6610_0 .net *"_s10", 0 0, L_0x1341cd0; 1 drivers -v0x11f66f0_0 .net *"_s12", 0 0, L_0x1341e30; 1 drivers -v0x11f67b0_0 .net *"_s14", 0 0, L_0x1342020; 1 drivers -v0x11f6890_0 .net *"_s16", 0 0, L_0x13421d0; 1 drivers -v0x11f69c0_0 .net *"_s3", 0 0, L_0x1341a80; 1 drivers -v0x11f6aa0_0 .net *"_s5", 0 0, L_0x1341b20; 1 drivers -v0x11f6b80_0 .net *"_s6", 0 0, L_0x1341c60; 1 drivers -v0x11f6c60_0 .net "ands", 1 0, L_0x1341bc0; 1 drivers -v0x11f6dd0_0 .net "in", 3 0, L_0x1342400; 1 drivers -v0x11f6eb0_0 .net "out", 0 0, L_0x1341fb0; 1 drivers -L_0x1341a80 .part L_0x1342400, 0, 1; -L_0x1341b20 .part L_0x1342400, 1, 1; -L_0x1341bc0 .concat8 [ 1 1 0 0], L_0x1341a10, L_0x1341c60; -L_0x1341cd0 .part L_0x1342400, 2, 1; -L_0x1341e30 .part L_0x1342400, 3, 1; -L_0x1342020 .part L_0x1341bc0, 0, 1; -L_0x13421d0 .part L_0x1341bc0, 1, 1; -S_0x11f7450 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x11f51a0; +L_0x2e36a80/d .functor AND 1, L_0x2e36af0, L_0x2e36b90, C4<1>, C4<1>; +L_0x2e36a80 .delay 1 (30000,30000,30000) L_0x2e36a80/d; +L_0x2e36cd0/d .functor AND 1, L_0x2e36d40, L_0x2e36de0, C4<1>, C4<1>; +L_0x2e36cd0 .delay 1 (30000,30000,30000) L_0x2e36cd0/d; +L_0x2e36f10/d .functor AND 1, L_0x2e36f80, L_0x2e37020, C4<1>, C4<1>; +L_0x2e36f10 .delay 1 (30000,30000,30000) L_0x2e36f10/d; +v0x2cd2680_0 .net *"_s0", 0 0, L_0x2e36a80; 1 drivers +v0x2cd2780_0 .net *"_s10", 0 0, L_0x2e36d40; 1 drivers +v0x2cd2860_0 .net *"_s12", 0 0, L_0x2e36de0; 1 drivers +v0x2cd2920_0 .net *"_s14", 0 0, L_0x2e36f80; 1 drivers +v0x2cd2a00_0 .net *"_s16", 0 0, L_0x2e37020; 1 drivers +v0x2cd2b30_0 .net *"_s3", 0 0, L_0x2e36af0; 1 drivers +v0x2cd2c10_0 .net *"_s5", 0 0, L_0x2e36b90; 1 drivers +v0x2cd2cf0_0 .net *"_s6", 0 0, L_0x2e36cd0; 1 drivers +v0x2cd2dd0_0 .net "ands", 1 0, L_0x2e36c30; 1 drivers +v0x2cd2f40_0 .net "in", 3 0, L_0x2e37160; 1 drivers +v0x2cd3020_0 .net "out", 0 0, L_0x2e36f10; 1 drivers +L_0x2e36af0 .part L_0x2e37160, 0, 1; +L_0x2e36b90 .part L_0x2e37160, 1, 1; +L_0x2e36c30 .concat8 [ 1 1 0 0], L_0x2e36a80, L_0x2e36cd0; +L_0x2e36d40 .part L_0x2e37160, 2, 1; +L_0x2e36de0 .part L_0x2e37160, 3, 1; +L_0x2e36f80 .part L_0x2e36c30, 0, 1; +L_0x2e37020 .part L_0x2e36c30, 1, 1; +S_0x2cd35c0 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x2cd1310; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1344260/d .functor AND 1, L_0x1344320, L_0x13444d0, C4<1>, C4<1>; -L_0x1344260 .delay 1 (30000,30000,30000) L_0x1344260/d; -v0x11f8ff0_0 .net *"_s10", 0 0, L_0x1344320; 1 drivers -v0x11f90d0_0 .net *"_s12", 0 0, L_0x13444d0; 1 drivers -v0x11f91b0_0 .net "ands", 1 0, L_0x1344030; 1 drivers -v0x11f9270_0 .net "in", 7 0, L_0x1344700; 1 drivers -v0x11f9350_0 .net "out", 0 0, L_0x1344260; 1 drivers -L_0x1343440 .part L_0x1344700, 0, 4; -L_0x1344030 .concat8 [ 1 1 0 0], L_0x1343130, L_0x1343d20; -L_0x1344170 .part L_0x1344700, 4, 4; -L_0x1344320 .part L_0x1344030, 0, 1; -L_0x13444d0 .part L_0x1344030, 1, 1; -S_0x11f7660 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11f7450; +L_0x2e38fc0/d .functor AND 1, L_0x2e39080, L_0x2e39230, C4<1>, C4<1>; +L_0x2e38fc0 .delay 1 (30000,30000,30000) L_0x2e38fc0/d; +v0x2cd5160_0 .net *"_s10", 0 0, L_0x2e39080; 1 drivers +v0x2cd5240_0 .net *"_s12", 0 0, L_0x2e39230; 1 drivers +v0x2cd5320_0 .net "ands", 1 0, L_0x2e38d90; 1 drivers +v0x2cd53e0_0 .net "in", 7 0, L_0x2e39460; 1 drivers +v0x2cd54c0_0 .net "out", 0 0, L_0x2e38fc0; 1 drivers +L_0x2e381a0 .part L_0x2e39460, 0, 4; +L_0x2e38d90 .concat8 [ 1 1 0 0], L_0x2e37e90, L_0x2e38a80; +L_0x2e38ed0 .part L_0x2e39460, 4, 4; +L_0x2e39080 .part L_0x2e38d90, 0, 1; +L_0x2e39230 .part L_0x2e38d90, 1, 1; +S_0x2cd37d0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x2cd35c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x13428f0/d .functor AND 1, L_0x13429b0, L_0x1342b10, C4<1>, C4<1>; -L_0x13428f0 .delay 1 (30000,30000,30000) L_0x13428f0/d; -L_0x1342d40/d .functor AND 1, L_0x1342e50, L_0x1342fb0, C4<1>, C4<1>; -L_0x1342d40 .delay 1 (30000,30000,30000) L_0x1342d40/d; -L_0x1343130/d .functor AND 1, L_0x13431a0, L_0x1343350, C4<1>, C4<1>; -L_0x1343130 .delay 1 (30000,30000,30000) L_0x1343130/d; -v0x11f78b0_0 .net *"_s0", 0 0, L_0x13428f0; 1 drivers -v0x11f79b0_0 .net *"_s10", 0 0, L_0x1342e50; 1 drivers -v0x11f7a90_0 .net *"_s12", 0 0, L_0x1342fb0; 1 drivers -v0x11f7b50_0 .net *"_s14", 0 0, L_0x13431a0; 1 drivers -v0x11f7c30_0 .net *"_s16", 0 0, L_0x1343350; 1 drivers -v0x11f7d60_0 .net *"_s3", 0 0, L_0x13429b0; 1 drivers -v0x11f7e40_0 .net *"_s5", 0 0, L_0x1342b10; 1 drivers -v0x11f7f20_0 .net *"_s6", 0 0, L_0x1342d40; 1 drivers -v0x11f8000_0 .net "ands", 1 0, L_0x1342c50; 1 drivers -v0x11f8170_0 .net "in", 3 0, L_0x1343440; 1 drivers -v0x11f8250_0 .net "out", 0 0, L_0x1343130; 1 drivers -L_0x13429b0 .part L_0x1343440, 0, 1; -L_0x1342b10 .part L_0x1343440, 1, 1; -L_0x1342c50 .concat8 [ 1 1 0 0], L_0x13428f0, L_0x1342d40; -L_0x1342e50 .part L_0x1343440, 2, 1; -L_0x1342fb0 .part L_0x1343440, 3, 1; -L_0x13431a0 .part L_0x1342c50, 0, 1; -L_0x1343350 .part L_0x1342c50, 1, 1; -S_0x11f8370 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11f7450; +L_0x2e37650/d .functor AND 1, L_0x2e37710, L_0x2e37870, C4<1>, C4<1>; +L_0x2e37650 .delay 1 (30000,30000,30000) L_0x2e37650/d; +L_0x2e37aa0/d .functor AND 1, L_0x2e37bb0, L_0x2e37d10, C4<1>, C4<1>; +L_0x2e37aa0 .delay 1 (30000,30000,30000) L_0x2e37aa0/d; +L_0x2e37e90/d .functor AND 1, L_0x2e37f00, L_0x2e380b0, C4<1>, C4<1>; +L_0x2e37e90 .delay 1 (30000,30000,30000) L_0x2e37e90/d; +v0x2cd3a20_0 .net *"_s0", 0 0, L_0x2e37650; 1 drivers +v0x2cd3b20_0 .net *"_s10", 0 0, L_0x2e37bb0; 1 drivers +v0x2cd3c00_0 .net *"_s12", 0 0, L_0x2e37d10; 1 drivers +v0x2cd3cc0_0 .net *"_s14", 0 0, L_0x2e37f00; 1 drivers +v0x2cd3da0_0 .net *"_s16", 0 0, L_0x2e380b0; 1 drivers +v0x2cd3ed0_0 .net *"_s3", 0 0, L_0x2e37710; 1 drivers +v0x2cd3fb0_0 .net *"_s5", 0 0, L_0x2e37870; 1 drivers +v0x2cd4090_0 .net *"_s6", 0 0, L_0x2e37aa0; 1 drivers +v0x2cd4170_0 .net "ands", 1 0, L_0x2e379b0; 1 drivers +v0x2cd42e0_0 .net "in", 3 0, L_0x2e381a0; 1 drivers +v0x2cd43c0_0 .net "out", 0 0, L_0x2e37e90; 1 drivers +L_0x2e37710 .part L_0x2e381a0, 0, 1; +L_0x2e37870 .part L_0x2e381a0, 1, 1; +L_0x2e379b0 .concat8 [ 1 1 0 0], L_0x2e37650, L_0x2e37aa0; +L_0x2e37bb0 .part L_0x2e381a0, 2, 1; +L_0x2e37d10 .part L_0x2e381a0, 3, 1; +L_0x2e37f00 .part L_0x2e379b0, 0, 1; +L_0x2e380b0 .part L_0x2e379b0, 1, 1; +S_0x2cd44e0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x2cd35c0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x13434e0/d .functor AND 1, L_0x13435a0, L_0x1343700, C4<1>, C4<1>; -L_0x13434e0 .delay 1 (30000,30000,30000) L_0x13434e0/d; -L_0x1343930/d .functor AND 1, L_0x1343a40, L_0x1343ba0, C4<1>, C4<1>; -L_0x1343930 .delay 1 (30000,30000,30000) L_0x1343930/d; -L_0x1343d20/d .functor AND 1, L_0x1343d90, L_0x1343f40, C4<1>, C4<1>; -L_0x1343d20 .delay 1 (30000,30000,30000) L_0x1343d20/d; -v0x11f8530_0 .net *"_s0", 0 0, L_0x13434e0; 1 drivers -v0x11f8630_0 .net *"_s10", 0 0, L_0x1343a40; 1 drivers -v0x11f8710_0 .net *"_s12", 0 0, L_0x1343ba0; 1 drivers -v0x11f87d0_0 .net *"_s14", 0 0, L_0x1343d90; 1 drivers -v0x11f88b0_0 .net *"_s16", 0 0, L_0x1343f40; 1 drivers -v0x11f89e0_0 .net *"_s3", 0 0, L_0x13435a0; 1 drivers -v0x11f8ac0_0 .net *"_s5", 0 0, L_0x1343700; 1 drivers -v0x11f8ba0_0 .net *"_s6", 0 0, L_0x1343930; 1 drivers -v0x11f8c80_0 .net "ands", 1 0, L_0x1343840; 1 drivers -v0x11f8df0_0 .net "in", 3 0, L_0x1344170; 1 drivers -v0x11f8ed0_0 .net "out", 0 0, L_0x1343d20; 1 drivers -L_0x13435a0 .part L_0x1344170, 0, 1; -L_0x1343700 .part L_0x1344170, 1, 1; -L_0x1343840 .concat8 [ 1 1 0 0], L_0x13434e0, L_0x1343930; -L_0x1343a40 .part L_0x1344170, 2, 1; -L_0x1343ba0 .part L_0x1344170, 3, 1; -L_0x1343d90 .part L_0x1343840, 0, 1; -L_0x1343f40 .part L_0x1343840, 1, 1; -S_0x11f9940 .scope module, "and_2" "and16" 4 47, 4 37 0, S_0x11f4fe0; +L_0x2e38240/d .functor AND 1, L_0x2e38300, L_0x2e38460, C4<1>, C4<1>; +L_0x2e38240 .delay 1 (30000,30000,30000) L_0x2e38240/d; +L_0x2e38690/d .functor AND 1, L_0x2e387a0, L_0x2e38900, C4<1>, C4<1>; +L_0x2e38690 .delay 1 (30000,30000,30000) L_0x2e38690/d; +L_0x2e38a80/d .functor AND 1, L_0x2e38af0, L_0x2e38ca0, C4<1>, C4<1>; +L_0x2e38a80 .delay 1 (30000,30000,30000) L_0x2e38a80/d; +v0x2cd46a0_0 .net *"_s0", 0 0, L_0x2e38240; 1 drivers +v0x2cd47a0_0 .net *"_s10", 0 0, L_0x2e387a0; 1 drivers +v0x2cd4880_0 .net *"_s12", 0 0, L_0x2e38900; 1 drivers +v0x2cd4940_0 .net *"_s14", 0 0, L_0x2e38af0; 1 drivers +v0x2cd4a20_0 .net *"_s16", 0 0, L_0x2e38ca0; 1 drivers +v0x2cd4b50_0 .net *"_s3", 0 0, L_0x2e38300; 1 drivers +v0x2cd4c30_0 .net *"_s5", 0 0, L_0x2e38460; 1 drivers +v0x2cd4d10_0 .net *"_s6", 0 0, L_0x2e38690; 1 drivers +v0x2cd4df0_0 .net "ands", 1 0, L_0x2e385a0; 1 drivers +v0x2cd4f60_0 .net "in", 3 0, L_0x2e38ed0; 1 drivers +v0x2cd5040_0 .net "out", 0 0, L_0x2e38a80; 1 drivers +L_0x2e38300 .part L_0x2e38ed0, 0, 1; +L_0x2e38460 .part L_0x2e38ed0, 1, 1; +L_0x2e385a0 .concat8 [ 1 1 0 0], L_0x2e38240, L_0x2e38690; +L_0x2e387a0 .part L_0x2e38ed0, 2, 1; +L_0x2e38900 .part L_0x2e38ed0, 3, 1; +L_0x2e38af0 .part L_0x2e385a0, 0, 1; +L_0x2e38ca0 .part L_0x2e385a0, 1, 1; +S_0x2cd5ab0 .scope module, "and_2" "and16" 4 47, 4 37 0, S_0x2cd1150; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 16 "in" -L_0x1348860/d .functor AND 1, L_0x1348920, L_0x1348ad0, C4<1>, C4<1>; -L_0x1348860 .delay 1 (30000,30000,30000) L_0x1348860/d; -v0x11fdbd0_0 .net *"_s10", 0 0, L_0x1348920; 1 drivers -v0x11fdcb0_0 .net *"_s12", 0 0, L_0x1348ad0; 1 drivers -v0x11fdd90_0 .net "ands", 1 0, L_0x1348630; 1 drivers -v0x11fde50_0 .net "in", 15 0, L_0x1348d00; 1 drivers -v0x11fdf30_0 .net "out", 0 0, L_0x1348860; 1 drivers -L_0x13468c0 .part L_0x1348d00, 0, 8; -L_0x1348630 .concat8 [ 1 1 0 0], L_0x1346560, L_0x13482d0; -L_0x1348770 .part L_0x1348d00, 8, 8; -L_0x1348920 .part L_0x1348630, 0, 1; -L_0x1348ad0 .part L_0x1348630, 1, 1; -S_0x11f9b50 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x11f9940; +L_0x2e3d5c0/d .functor AND 1, L_0x2e3d680, L_0x2e3d830, C4<1>, C4<1>; +L_0x2e3d5c0 .delay 1 (30000,30000,30000) L_0x2e3d5c0/d; +v0x2cd9d40_0 .net *"_s10", 0 0, L_0x2e3d680; 1 drivers +v0x2cd9e20_0 .net *"_s12", 0 0, L_0x2e3d830; 1 drivers +v0x2cd9f00_0 .net "ands", 1 0, L_0x2e3d390; 1 drivers +v0x2cd9fc0_0 .net "in", 15 0, L_0x2e3da60; 1 drivers +v0x2cda0a0_0 .net "out", 0 0, L_0x2e3d5c0; 1 drivers +L_0x2e3b620 .part L_0x2e3da60, 0, 8; +L_0x2e3d390 .concat8 [ 1 1 0 0], L_0x2e3b2c0, L_0x2e3d030; +L_0x2e3d4d0 .part L_0x2e3da60, 8, 8; +L_0x2e3d680 .part L_0x2e3d390, 0, 1; +L_0x2e3d830 .part L_0x2e3d390, 1, 1; +S_0x2cd5cc0 .scope module, "and_1" "and8" 4 39, 4 30 0, S_0x2cd5ab0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x1346560/d .functor AND 1, L_0x1346620, L_0x13467d0, C4<1>, C4<1>; -L_0x1346560 .delay 1 (30000,30000,30000) L_0x1346560/d; -v0x11fb730_0 .net *"_s10", 0 0, L_0x1346620; 1 drivers -v0x11fb810_0 .net *"_s12", 0 0, L_0x13467d0; 1 drivers -v0x11fb8f0_0 .net "ands", 1 0, L_0x1346330; 1 drivers -v0x11fb9b0_0 .net "in", 7 0, L_0x13468c0; 1 drivers -v0x11fba90_0 .net "out", 0 0, L_0x1346560; 1 drivers -L_0x1345740 .part L_0x13468c0, 0, 4; -L_0x1346330 .concat8 [ 1 1 0 0], L_0x1345430, L_0x1346020; -L_0x1346470 .part L_0x13468c0, 4, 4; -L_0x1346620 .part L_0x1346330, 0, 1; -L_0x13467d0 .part L_0x1346330, 1, 1; -S_0x11f9da0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11f9b50; +L_0x2e3b2c0/d .functor AND 1, L_0x2e3b380, L_0x2e3b530, C4<1>, C4<1>; +L_0x2e3b2c0 .delay 1 (30000,30000,30000) L_0x2e3b2c0/d; +v0x2cd78a0_0 .net *"_s10", 0 0, L_0x2e3b380; 1 drivers +v0x2cd7980_0 .net *"_s12", 0 0, L_0x2e3b530; 1 drivers +v0x2cd7a60_0 .net "ands", 1 0, L_0x2e3b090; 1 drivers +v0x2cd7b20_0 .net "in", 7 0, L_0x2e3b620; 1 drivers +v0x2cd7c00_0 .net "out", 0 0, L_0x2e3b2c0; 1 drivers +L_0x2e3a4a0 .part L_0x2e3b620, 0, 4; +L_0x2e3b090 .concat8 [ 1 1 0 0], L_0x2e3a190, L_0x2e3ad80; +L_0x2e3b1d0 .part L_0x2e3b620, 4, 4; +L_0x2e3b380 .part L_0x2e3b090, 0, 1; +L_0x2e3b530 .part L_0x2e3b090, 1, 1; +S_0x2cd5f10 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x2cd5cc0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1344bf0/d .functor AND 1, L_0x1344cb0, L_0x1344e10, C4<1>, C4<1>; -L_0x1344bf0 .delay 1 (30000,30000,30000) L_0x1344bf0/d; -L_0x1345040/d .functor AND 1, L_0x1345150, L_0x13452b0, C4<1>, C4<1>; -L_0x1345040 .delay 1 (30000,30000,30000) L_0x1345040/d; -L_0x1345430/d .functor AND 1, L_0x13454a0, L_0x1345650, C4<1>, C4<1>; -L_0x1345430 .delay 1 (30000,30000,30000) L_0x1345430/d; -v0x11f9ff0_0 .net *"_s0", 0 0, L_0x1344bf0; 1 drivers -v0x11fa0f0_0 .net *"_s10", 0 0, L_0x1345150; 1 drivers -v0x11fa1d0_0 .net *"_s12", 0 0, L_0x13452b0; 1 drivers -v0x11fa290_0 .net *"_s14", 0 0, L_0x13454a0; 1 drivers -v0x11fa370_0 .net *"_s16", 0 0, L_0x1345650; 1 drivers -v0x11fa4a0_0 .net *"_s3", 0 0, L_0x1344cb0; 1 drivers -v0x11fa580_0 .net *"_s5", 0 0, L_0x1344e10; 1 drivers -v0x11fa660_0 .net *"_s6", 0 0, L_0x1345040; 1 drivers -v0x11fa740_0 .net "ands", 1 0, L_0x1344f50; 1 drivers -v0x11fa8b0_0 .net "in", 3 0, L_0x1345740; 1 drivers -v0x11fa990_0 .net "out", 0 0, L_0x1345430; 1 drivers -L_0x1344cb0 .part L_0x1345740, 0, 1; -L_0x1344e10 .part L_0x1345740, 1, 1; -L_0x1344f50 .concat8 [ 1 1 0 0], L_0x1344bf0, L_0x1345040; -L_0x1345150 .part L_0x1345740, 2, 1; -L_0x13452b0 .part L_0x1345740, 3, 1; -L_0x13454a0 .part L_0x1344f50, 0, 1; -L_0x1345650 .part L_0x1344f50, 1, 1; -S_0x11faab0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11f9b50; +L_0x2e39950/d .functor AND 1, L_0x2e39a10, L_0x2e39b70, C4<1>, C4<1>; +L_0x2e39950 .delay 1 (30000,30000,30000) L_0x2e39950/d; +L_0x2e39da0/d .functor AND 1, L_0x2e39eb0, L_0x2e3a010, C4<1>, C4<1>; +L_0x2e39da0 .delay 1 (30000,30000,30000) L_0x2e39da0/d; +L_0x2e3a190/d .functor AND 1, L_0x2e3a200, L_0x2e3a3b0, C4<1>, C4<1>; +L_0x2e3a190 .delay 1 (30000,30000,30000) L_0x2e3a190/d; +v0x2cd6160_0 .net *"_s0", 0 0, L_0x2e39950; 1 drivers +v0x2cd6260_0 .net *"_s10", 0 0, L_0x2e39eb0; 1 drivers +v0x2cd6340_0 .net *"_s12", 0 0, L_0x2e3a010; 1 drivers +v0x2cd6400_0 .net *"_s14", 0 0, L_0x2e3a200; 1 drivers +v0x2cd64e0_0 .net *"_s16", 0 0, L_0x2e3a3b0; 1 drivers +v0x2cd6610_0 .net *"_s3", 0 0, L_0x2e39a10; 1 drivers +v0x2cd66f0_0 .net *"_s5", 0 0, L_0x2e39b70; 1 drivers +v0x2cd67d0_0 .net *"_s6", 0 0, L_0x2e39da0; 1 drivers +v0x2cd68b0_0 .net "ands", 1 0, L_0x2e39cb0; 1 drivers +v0x2cd6a20_0 .net "in", 3 0, L_0x2e3a4a0; 1 drivers +v0x2cd6b00_0 .net "out", 0 0, L_0x2e3a190; 1 drivers +L_0x2e39a10 .part L_0x2e3a4a0, 0, 1; +L_0x2e39b70 .part L_0x2e3a4a0, 1, 1; +L_0x2e39cb0 .concat8 [ 1 1 0 0], L_0x2e39950, L_0x2e39da0; +L_0x2e39eb0 .part L_0x2e3a4a0, 2, 1; +L_0x2e3a010 .part L_0x2e3a4a0, 3, 1; +L_0x2e3a200 .part L_0x2e39cb0, 0, 1; +L_0x2e3a3b0 .part L_0x2e39cb0, 1, 1; +S_0x2cd6c20 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x2cd5cc0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x13457e0/d .functor AND 1, L_0x13458a0, L_0x1345a00, C4<1>, C4<1>; -L_0x13457e0 .delay 1 (30000,30000,30000) L_0x13457e0/d; -L_0x1345c30/d .functor AND 1, L_0x1345d40, L_0x1345ea0, C4<1>, C4<1>; -L_0x1345c30 .delay 1 (30000,30000,30000) L_0x1345c30/d; -L_0x1346020/d .functor AND 1, L_0x1346090, L_0x1346240, C4<1>, C4<1>; -L_0x1346020 .delay 1 (30000,30000,30000) L_0x1346020/d; -v0x11fac70_0 .net *"_s0", 0 0, L_0x13457e0; 1 drivers -v0x11fad70_0 .net *"_s10", 0 0, L_0x1345d40; 1 drivers -v0x11fae50_0 .net *"_s12", 0 0, L_0x1345ea0; 1 drivers -v0x11faf10_0 .net *"_s14", 0 0, L_0x1346090; 1 drivers -v0x11faff0_0 .net *"_s16", 0 0, L_0x1346240; 1 drivers -v0x11fb120_0 .net *"_s3", 0 0, L_0x13458a0; 1 drivers -v0x11fb200_0 .net *"_s5", 0 0, L_0x1345a00; 1 drivers -v0x11fb2e0_0 .net *"_s6", 0 0, L_0x1345c30; 1 drivers -v0x11fb3c0_0 .net "ands", 1 0, L_0x1345b40; 1 drivers -v0x11fb530_0 .net "in", 3 0, L_0x1346470; 1 drivers -v0x11fb610_0 .net "out", 0 0, L_0x1346020; 1 drivers -L_0x13458a0 .part L_0x1346470, 0, 1; -L_0x1345a00 .part L_0x1346470, 1, 1; -L_0x1345b40 .concat8 [ 1 1 0 0], L_0x13457e0, L_0x1345c30; -L_0x1345d40 .part L_0x1346470, 2, 1; -L_0x1345ea0 .part L_0x1346470, 3, 1; -L_0x1346090 .part L_0x1345b40, 0, 1; -L_0x1346240 .part L_0x1345b40, 1, 1; -S_0x11fbbb0 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x11f9940; +L_0x2e3a540/d .functor AND 1, L_0x2e3a600, L_0x2e3a760, C4<1>, C4<1>; +L_0x2e3a540 .delay 1 (30000,30000,30000) L_0x2e3a540/d; +L_0x2e3a990/d .functor AND 1, L_0x2e3aaa0, L_0x2e3ac00, C4<1>, C4<1>; +L_0x2e3a990 .delay 1 (30000,30000,30000) L_0x2e3a990/d; +L_0x2e3ad80/d .functor AND 1, L_0x2e3adf0, L_0x2e3afa0, C4<1>, C4<1>; +L_0x2e3ad80 .delay 1 (30000,30000,30000) L_0x2e3ad80/d; +v0x2cd6de0_0 .net *"_s0", 0 0, L_0x2e3a540; 1 drivers +v0x2cd6ee0_0 .net *"_s10", 0 0, L_0x2e3aaa0; 1 drivers +v0x2cd6fc0_0 .net *"_s12", 0 0, L_0x2e3ac00; 1 drivers +v0x2cd7080_0 .net *"_s14", 0 0, L_0x2e3adf0; 1 drivers +v0x2cd7160_0 .net *"_s16", 0 0, L_0x2e3afa0; 1 drivers +v0x2cd7290_0 .net *"_s3", 0 0, L_0x2e3a600; 1 drivers +v0x2cd7370_0 .net *"_s5", 0 0, L_0x2e3a760; 1 drivers +v0x2cd7450_0 .net *"_s6", 0 0, L_0x2e3a990; 1 drivers +v0x2cd7530_0 .net "ands", 1 0, L_0x2e3a8a0; 1 drivers +v0x2cd76a0_0 .net "in", 3 0, L_0x2e3b1d0; 1 drivers +v0x2cd7780_0 .net "out", 0 0, L_0x2e3ad80; 1 drivers +L_0x2e3a600 .part L_0x2e3b1d0, 0, 1; +L_0x2e3a760 .part L_0x2e3b1d0, 1, 1; +L_0x2e3a8a0 .concat8 [ 1 1 0 0], L_0x2e3a540, L_0x2e3a990; +L_0x2e3aaa0 .part L_0x2e3b1d0, 2, 1; +L_0x2e3ac00 .part L_0x2e3b1d0, 3, 1; +L_0x2e3adf0 .part L_0x2e3a8a0, 0, 1; +L_0x2e3afa0 .part L_0x2e3a8a0, 1, 1; +S_0x2cd7d20 .scope module, "and_2" "and8" 4 40, 4 30 0, S_0x2cd5ab0; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 8 "in" -L_0x13482d0/d .functor AND 1, L_0x1348390, L_0x1348540, C4<1>, C4<1>; -L_0x13482d0 .delay 1 (30000,30000,30000) L_0x13482d0/d; -v0x11fd750_0 .net *"_s10", 0 0, L_0x1348390; 1 drivers -v0x11fd830_0 .net *"_s12", 0 0, L_0x1348540; 1 drivers -v0x11fd910_0 .net "ands", 1 0, L_0x13480a0; 1 drivers -v0x11fd9d0_0 .net "in", 7 0, L_0x1348770; 1 drivers -v0x11fdab0_0 .net "out", 0 0, L_0x13482d0; 1 drivers -L_0x13474b0 .part L_0x1348770, 0, 4; -L_0x13480a0 .concat8 [ 1 1 0 0], L_0x13471a0, L_0x1347d90; -L_0x13481e0 .part L_0x1348770, 4, 4; -L_0x1348390 .part L_0x13480a0, 0, 1; -L_0x1348540 .part L_0x13480a0, 1, 1; -S_0x11fbdc0 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x11fbbb0; +L_0x2e3d030/d .functor AND 1, L_0x2e3d0f0, L_0x2e3d2a0, C4<1>, C4<1>; +L_0x2e3d030 .delay 1 (30000,30000,30000) L_0x2e3d030/d; +v0x2cd98c0_0 .net *"_s10", 0 0, L_0x2e3d0f0; 1 drivers +v0x2cd99a0_0 .net *"_s12", 0 0, L_0x2e3d2a0; 1 drivers +v0x2cd9a80_0 .net "ands", 1 0, L_0x2e3ce00; 1 drivers +v0x2cd9b40_0 .net "in", 7 0, L_0x2e3d4d0; 1 drivers +v0x2cd9c20_0 .net "out", 0 0, L_0x2e3d030; 1 drivers +L_0x2e3c210 .part L_0x2e3d4d0, 0, 4; +L_0x2e3ce00 .concat8 [ 1 1 0 0], L_0x2e3bf00, L_0x2e3caf0; +L_0x2e3cf40 .part L_0x2e3d4d0, 4, 4; +L_0x2e3d0f0 .part L_0x2e3ce00, 0, 1; +L_0x2e3d2a0 .part L_0x2e3ce00, 1, 1; +S_0x2cd7f30 .scope module, "and_1" "and4" 4 32, 4 23 0, S_0x2cd7d20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1346960/d .functor AND 1, L_0x1346a20, L_0x1346b80, C4<1>, C4<1>; -L_0x1346960 .delay 1 (30000,30000,30000) L_0x1346960/d; -L_0x1346db0/d .functor AND 1, L_0x1346ec0, L_0x1347020, C4<1>, C4<1>; -L_0x1346db0 .delay 1 (30000,30000,30000) L_0x1346db0/d; -L_0x13471a0/d .functor AND 1, L_0x1347210, L_0x13473c0, C4<1>, C4<1>; -L_0x13471a0 .delay 1 (30000,30000,30000) L_0x13471a0/d; -v0x11fc010_0 .net *"_s0", 0 0, L_0x1346960; 1 drivers -v0x11fc110_0 .net *"_s10", 0 0, L_0x1346ec0; 1 drivers -v0x11fc1f0_0 .net *"_s12", 0 0, L_0x1347020; 1 drivers -v0x11fc2b0_0 .net *"_s14", 0 0, L_0x1347210; 1 drivers -v0x11fc390_0 .net *"_s16", 0 0, L_0x13473c0; 1 drivers -v0x11fc4c0_0 .net *"_s3", 0 0, L_0x1346a20; 1 drivers -v0x11fc5a0_0 .net *"_s5", 0 0, L_0x1346b80; 1 drivers -v0x11fc680_0 .net *"_s6", 0 0, L_0x1346db0; 1 drivers -v0x11fc760_0 .net "ands", 1 0, L_0x1346cc0; 1 drivers -v0x11fc8d0_0 .net "in", 3 0, L_0x13474b0; 1 drivers -v0x11fc9b0_0 .net "out", 0 0, L_0x13471a0; 1 drivers -L_0x1346a20 .part L_0x13474b0, 0, 1; -L_0x1346b80 .part L_0x13474b0, 1, 1; -L_0x1346cc0 .concat8 [ 1 1 0 0], L_0x1346960, L_0x1346db0; -L_0x1346ec0 .part L_0x13474b0, 2, 1; -L_0x1347020 .part L_0x13474b0, 3, 1; -L_0x1347210 .part L_0x1346cc0, 0, 1; -L_0x13473c0 .part L_0x1346cc0, 1, 1; -S_0x11fcad0 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x11fbbb0; +L_0x2e3b6c0/d .functor AND 1, L_0x2e3b780, L_0x2e3b8e0, C4<1>, C4<1>; +L_0x2e3b6c0 .delay 1 (30000,30000,30000) L_0x2e3b6c0/d; +L_0x2e3bb10/d .functor AND 1, L_0x2e3bc20, L_0x2e3bd80, C4<1>, C4<1>; +L_0x2e3bb10 .delay 1 (30000,30000,30000) L_0x2e3bb10/d; +L_0x2e3bf00/d .functor AND 1, L_0x2e3bf70, L_0x2e3c120, C4<1>, C4<1>; +L_0x2e3bf00 .delay 1 (30000,30000,30000) L_0x2e3bf00/d; +v0x2cd8180_0 .net *"_s0", 0 0, L_0x2e3b6c0; 1 drivers +v0x2cd8280_0 .net *"_s10", 0 0, L_0x2e3bc20; 1 drivers +v0x2cd8360_0 .net *"_s12", 0 0, L_0x2e3bd80; 1 drivers +v0x2cd8420_0 .net *"_s14", 0 0, L_0x2e3bf70; 1 drivers +v0x2cd8500_0 .net *"_s16", 0 0, L_0x2e3c120; 1 drivers +v0x2cd8630_0 .net *"_s3", 0 0, L_0x2e3b780; 1 drivers +v0x2cd8710_0 .net *"_s5", 0 0, L_0x2e3b8e0; 1 drivers +v0x2cd87f0_0 .net *"_s6", 0 0, L_0x2e3bb10; 1 drivers +v0x2cd88d0_0 .net "ands", 1 0, L_0x2e3ba20; 1 drivers +v0x2cd8a40_0 .net "in", 3 0, L_0x2e3c210; 1 drivers +v0x2cd8b20_0 .net "out", 0 0, L_0x2e3bf00; 1 drivers +L_0x2e3b780 .part L_0x2e3c210, 0, 1; +L_0x2e3b8e0 .part L_0x2e3c210, 1, 1; +L_0x2e3ba20 .concat8 [ 1 1 0 0], L_0x2e3b6c0, L_0x2e3bb10; +L_0x2e3bc20 .part L_0x2e3c210, 2, 1; +L_0x2e3bd80 .part L_0x2e3c210, 3, 1; +L_0x2e3bf70 .part L_0x2e3ba20, 0, 1; +L_0x2e3c120 .part L_0x2e3ba20, 1, 1; +S_0x2cd8c40 .scope module, "and_2" "and4" 4 33, 4 23 0, S_0x2cd7d20; .timescale -9 -12; .port_info 0 /OUTPUT 1 "out" .port_info 1 /INPUT 4 "in" -L_0x1347550/d .functor AND 1, L_0x1347610, L_0x1347770, C4<1>, C4<1>; -L_0x1347550 .delay 1 (30000,30000,30000) L_0x1347550/d; -L_0x13479a0/d .functor AND 1, L_0x1347ab0, L_0x1347c10, C4<1>, C4<1>; -L_0x13479a0 .delay 1 (30000,30000,30000) L_0x13479a0/d; -L_0x1347d90/d .functor AND 1, L_0x1347e00, L_0x1347fb0, C4<1>, C4<1>; -L_0x1347d90 .delay 1 (30000,30000,30000) L_0x1347d90/d; -v0x11fcc90_0 .net *"_s0", 0 0, L_0x1347550; 1 drivers -v0x11fcd90_0 .net *"_s10", 0 0, L_0x1347ab0; 1 drivers -v0x11fce70_0 .net *"_s12", 0 0, L_0x1347c10; 1 drivers -v0x11fcf30_0 .net *"_s14", 0 0, L_0x1347e00; 1 drivers -v0x11fd010_0 .net *"_s16", 0 0, L_0x1347fb0; 1 drivers -v0x11fd140_0 .net *"_s3", 0 0, L_0x1347610; 1 drivers -v0x11fd220_0 .net *"_s5", 0 0, L_0x1347770; 1 drivers -v0x11fd300_0 .net *"_s6", 0 0, L_0x13479a0; 1 drivers -v0x11fd3e0_0 .net "ands", 1 0, L_0x13478b0; 1 drivers -v0x11fd550_0 .net "in", 3 0, L_0x13481e0; 1 drivers -v0x11fd630_0 .net "out", 0 0, L_0x1347d90; 1 drivers -L_0x1347610 .part L_0x13481e0, 0, 1; -L_0x1347770 .part L_0x13481e0, 1, 1; -L_0x13478b0 .concat8 [ 1 1 0 0], L_0x1347550, L_0x13479a0; -L_0x1347ab0 .part L_0x13481e0, 2, 1; -L_0x1347c10 .part L_0x13481e0, 3, 1; -L_0x1347e00 .part L_0x13478b0, 0, 1; -L_0x1347fb0 .part L_0x13478b0, 1, 1; - .scope S_0xf2fc10; +L_0x2e3c2b0/d .functor AND 1, L_0x2e3c370, L_0x2e3c4d0, C4<1>, C4<1>; +L_0x2e3c2b0 .delay 1 (30000,30000,30000) L_0x2e3c2b0/d; +L_0x2e3c700/d .functor AND 1, L_0x2e3c810, L_0x2e3c970, C4<1>, C4<1>; +L_0x2e3c700 .delay 1 (30000,30000,30000) L_0x2e3c700/d; +L_0x2e3caf0/d .functor AND 1, L_0x2e3cb60, L_0x2e3cd10, C4<1>, C4<1>; +L_0x2e3caf0 .delay 1 (30000,30000,30000) L_0x2e3caf0/d; +v0x2cd8e00_0 .net *"_s0", 0 0, L_0x2e3c2b0; 1 drivers +v0x2cd8f00_0 .net *"_s10", 0 0, L_0x2e3c810; 1 drivers +v0x2cd8fe0_0 .net *"_s12", 0 0, L_0x2e3c970; 1 drivers +v0x2cd90a0_0 .net *"_s14", 0 0, L_0x2e3cb60; 1 drivers +v0x2cd9180_0 .net *"_s16", 0 0, L_0x2e3cd10; 1 drivers +v0x2cd92b0_0 .net *"_s3", 0 0, L_0x2e3c370; 1 drivers +v0x2cd9390_0 .net *"_s5", 0 0, L_0x2e3c4d0; 1 drivers +v0x2cd9470_0 .net *"_s6", 0 0, L_0x2e3c700; 1 drivers +v0x2cd9550_0 .net "ands", 1 0, L_0x2e3c610; 1 drivers +v0x2cd96c0_0 .net "in", 3 0, L_0x2e3cf40; 1 drivers +v0x2cd97a0_0 .net "out", 0 0, L_0x2e3caf0; 1 drivers +L_0x2e3c370 .part L_0x2e3cf40, 0, 1; +L_0x2e3c4d0 .part L_0x2e3cf40, 1, 1; +L_0x2e3c610 .concat8 [ 1 1 0 0], L_0x2e3c2b0, L_0x2e3c700; +L_0x2e3c810 .part L_0x2e3cf40, 2, 1; +L_0x2e3c970 .part L_0x2e3cf40, 3, 1; +L_0x2e3cb60 .part L_0x2e3c610, 0, 1; +L_0x2e3cd10 .part L_0x2e3c610, 1, 1; + .scope S_0x26b20c0; T_0 ; - %wait E_0xfc9f50; - %load/vec4 v0x1200fd0_0; + %wait E_0x2a83c80; + %load/vec4 v0x2cdd200_0; %dup/vec4; %pushi/vec4 0, 0, 3; %cmp/u; @@ -17883,50 +18877,350 @@ T_0 ; %jmp T_0.8; T_0.0 ; %pushi/vec4 1, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.1 ; %pushi/vec4 2, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.2 ; %pushi/vec4 4, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.3 ; %pushi/vec4 8, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.4 ; %pushi/vec4 16, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.5 ; %pushi/vec4 32, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.6 ; %pushi/vec4 64, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.7 ; %pushi/vec4 128, 0, 8; - %store/vec4 v0x12010b0_0, 0, 8; + %store/vec4 v0x2cdd2e0_0, 0, 8; %jmp T_0.8; T_0.8 ; %pop/vec4 1; %jmp T_0; .thread T_0, $push; - .scope S_0xf510b0; + .scope S_0x26fb580; T_1 ; + %vpi_call 2 17 "$dumpfile", "alu.vcd" {0 0 0}; + %vpi_call 2 18 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x26fb580 {0 0 0}; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 4294967292, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %cmpi/ne 0, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x2cde300_0; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x2cde490_0; + %nor/r; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.0, 8; + %vpi_call 2 24 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.0 ; + %pushi/vec4 2147483647, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %cmpi/ne 0, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x2cde300_0; + %nor/r; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x2cde490_0; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.2, 8; + %vpi_call 2 29 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 31'b0001000000000000000000000000000 {0 0 0}; +T_1.2 ; + %pushi/vec4 1, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 4, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %cmpi/ne 0, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x2cde300_0; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x2cde490_0; + %nor/r; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.4, 8; + %vpi_call 2 37 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.4 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 1, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %cmpi/ne 2147483647, 0, 32; + %flag_mov 8, 4; + %load/vec4 v0x2cde300_0; + %nor/r; + %flag_set/vec4 9; + %flag_or 9, 8; + %load/vec4 v0x2cde490_0; + %flag_set/vec4 8; + %flag_or 8, 9; + %jmp/0xz T_1.6, 8; + %vpi_call 2 42 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 31'b1111111111111111111111111111111 {0 0 0}; +T_1.6 ; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %xor; + %cmp/ne; + %jmp/0xz T_1.8, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %xor; + %vpi_call 2 50 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.8 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %xor; + %cmp/ne; + %jmp/0xz T_1.10, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %xor; + %vpi_call 2 55 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.10 ; %pushi/vec4 3, 0, 3; - %store/vec4 v0x1202000_0, 0, 3; - %pushi/vec4 4294967294, 0, 32; - %store/vec4 v0x1201d20_0, 0, 32; - %pushi/vec4 4294967295, 0, 32; - %store/vec4 v0x1201e30_0, 0, 32; - %delay 1410065408, 2; - %vpi_call 2 19 "$display", "%d %d %d %b", v0x1201d20_0, v0x1201e30_0, v0x1202170_0, v0x12020d0_0 {0 0 0}; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 4294967288, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 4294967280, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.12, 8; + %vpi_call 2 63 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.12 ; + %pushi/vec4 8, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 16, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.14, 4; + %vpi_call 2 68 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 32'sb00000000000000000000000000000001 {0 0 0}; +T_1.14 ; + %pushi/vec4 8, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 4294967280, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.16, 8; + %vpi_call 2 73 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 32'sb00000000000000000000000000000000 {0 0 0}; +T_1.16 ; + %pushi/vec4 4294967288, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 16, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.18, 4; + %vpi_call 2 78 "$display", "FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, 32'sb00000000000000000000000000000001 {0 0 0}; +T_1.18 ; + %pushi/vec4 4, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %cmp/e; + %flag_get/vec4 4; + %inv; + %pad/u 32; + %load/vec4 v0x2cde060_0; + %and; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.20, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %and; + %vpi_call 2 86 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.20 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %cmp/e; + %flag_get/vec4 4; + %inv; + %pad/u 32; + %load/vec4 v0x2cde060_0; + %and; + %cmpi/ne 0, 0, 32; + %jmp/0xz T_1.22, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %and; + %vpi_call 2 91 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.22 ; + %pushi/vec4 5, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %and; + %inv; + %cmp/ne; + %jmp/0xz T_1.24, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %and; + %inv; + %vpi_call 2 99 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.24 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %and; + %inv; + %cmp/ne; + %jmp/0xz T_1.26, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %and; + %inv; + %vpi_call 2 104 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.26 ; + %pushi/vec4 6, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %inv; + %cmp/ne; + %jmp/0xz T_1.28, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %inv; + %vpi_call 2 112 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.28 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %inv; + %cmp/ne; + %jmp/0xz T_1.30, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %inv; + %vpi_call 2 117 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.30 ; + %pushi/vec4 7, 0, 3; + %store/vec4 v0x2cde230_0, 0, 3; + %pushi/vec4 9, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 10, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %cmp/ne; + %jmp/0xz T_1.32, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %vpi_call 2 125 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.32 ; + %pushi/vec4 0, 0, 32; + %store/vec4 v0x2cddf50_0, 0, 32; + %pushi/vec4 15, 0, 32; + %store/vec4 v0x2cde060_0, 0, 32; + %delay 1000000000, 0; + %load/vec4 v0x2cde3a0_0; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %cmp/ne; + %jmp/0xz T_1.34, 4; + %load/vec4 v0x2cddf50_0; + %load/vec4 v0x2cde060_0; + %or; + %vpi_call 2 130 "$display", "FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", v0x2cddf50_0, v0x2cde060_0, v0x2cde3a0_0, v0x2cde230_0, v0x2cde300_0, v0x2cde490_0, v0x2cde130_0, S<0,vec4,s32> {1 0 0}; +T_1.34 ; %end; .thread T_1; # The file index is used to find the file name in the following table. diff --git a/alu.t.v b/alu.t.v index ca4a7bc..1ec393e 100644 --- a/alu.t.v +++ b/alu.t.v @@ -28,7 +28,7 @@ module testALU(); if (result != 31'h80000000 || !overflow || zero) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 31'h8000000); end - + //Subtraction tests command = 3'd1; a = 4; @@ -41,20 +41,20 @@ module testALU(); if (result != 31'h7fffffff || !overflow || zero) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 31'h7fffffff); end - + //XOR tests command = 3'd2; a = 4'b1001; b = 4'b1010; #1000000 - if (result != a^b) begin + if (result != (a^b)) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, a^b); end a = 4'b0000; b = 4'b1111; #1000000 - if (result != a^b) begin + if (result != (a^b)) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, a^b); end - + //SLT tests command = 3'd3; a = -8; @@ -77,7 +77,7 @@ module testALU(); if (result) begin $display("FAIL %d %d %d |cmd: %d |ovf: %d |0: %d |co: %d |des: %d", a, b, result, command, overflow, zero, carryout, 1); end - + //AND tests command = 3'd4; a = 4'b1001; @@ -90,7 +90,7 @@ module testALU(); if (result != a&b) begin $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, a&b); end - + //AND tests command = 3'd5; a = 4'b1001; @@ -103,7 +103,7 @@ module testALU(); if (result != ~(a&b)) begin $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a&b)); end - + //NOR tests command = 3'd6; a = 4'b1001; @@ -116,7 +116,7 @@ module testALU(); if (result != ~(a|b)) begin $display("FAIL %b %b %b |cmd: %d |ovf: %d |0: %d |co: %d |des: %b", a, b, result, command, overflow, zero, carryout, ~(a|b)); end - + //OR tests command = 3'd7; a = 4'b1001; diff --git a/alu.v b/alu.v index b6c4a99..b71f972 100644 --- a/alu.v +++ b/alu.v @@ -23,14 +23,14 @@ input[2:0] command reg[7:0] commandslice; always @(command) begin case (command) - 0: begin commandslice = 1<<0; end - 1: begin commandslice = 1<<1; end - 2: begin commandslice = 1<<2; end - 3: begin commandslice = 1<<3; end - 4: begin commandslice = 1<<4; end - 5: begin commandslice = 1<<5; end - 6: begin commandslice = 1<<6; end - 7: begin commandslice = 1<<7; end + 0: begin commandslice = 8'd1<<0; end + 1: begin commandslice = 8'd1<<1; end + 2: begin commandslice = 8'd1<<2; end + 3: begin commandslice = 8'd1<<3; end + 4: begin commandslice = 8'd1<<4; end + 5: begin commandslice = 8'd1<<5; end + 6: begin commandslice = 8'd1<<6; end + 7: begin commandslice = 8'd1<<7; end endcase end @@ -56,25 +56,23 @@ input[2:0] command `OR subflag(carryinbus[0], commandslice[1], commandslice[1]); //set carryout to the lest carry bit //this or gate is also a wire - `OR carryor(carryoutint, carryinbus[32], carryinbus[32]); + `OR carryor(carryout, carryinbus[32], carryinbus[32]); //and all the zero outputs to get the zero output and32 zeroout(zero, zerobus); + //it's nice to know these + `XNOR sameSignXNOR(sameSigns, operandA[31], operandB[31]); + `NOT differentSignNOT(mixedSigns, sameSigns); //calculate overflow `XOR overflowXor(possibleOverflow, result[31], carryout); - `XNOR overflowXnorAdd(sameSigns, operandA[31], operandB[31]); - `NOT overflowNot(mixedSigns, sameSigns); mux1 overflowMux(overFlowPossible, mixedSigns, sameSigns, commandslice[0]); `OR addSubOr(addOrSub, commandslice[0], commandslice[1]); `AND overflowAnd(overflowPre, possibleOverflow, overFlowPossible); - `AND overflowOut(overflow, overflowPre, addOrSub); + `AND overflowOut(overflow, overflowPre, adOrSub); + //handle the slt stuff `XOR sltOut(sltPre, carryout, mixedSigns); `AND sltOut2(overrideBus[0], sltPre, commandslice[3]); or32P resultOr(result, resultBus, overrideBus); - //flag enabling - `OR addorsub(flagsEnable, commandslice[0], commandslice[1]); - `AND overflowand(overflow, overflowint, flagsEnable); - `AND carryoutand(carryout, carryoutint, flagsEnable); endmodule diff --git a/alu.vcd b/alu.vcd new file mode 100644 index 0000000..77ef3d5 --- /dev/null +++ b/alu.vcd @@ -0,0 +1,58895 @@ +$date + Fri Oct 13 01:39:04 2017 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module testALU $end +$var wire 1 ! zero $end +$var wire 32 " result [31:0] $end +$var wire 1 # overflow $end +$var wire 1 $ carryout $end +$var reg 32 % a [31:0] $end +$var reg 32 & b [31:0] $end +$var reg 3 ' command [2:0] $end +$scope module dut $end +$var wire 1 ( adOrSub $end +$var wire 1 ) addOrSub $end +$var wire 1 $ carryout $end +$var wire 3 * command [2:0] $end +$var wire 1 + mixedSigns $end +$var wire 32 , operandA [31:0] $end +$var wire 32 - operandB [31:0] $end +$var wire 1 # overflow $end +$var wire 1 . overflowPre $end +$var wire 1 / possibleOverflow $end +$var wire 1 0 sameSigns $end +$var wire 1 1 sltPre $end +$var wire 32 2 zerobus [31:0] $end +$var wire 1 ! zero $end +$var wire 32 3 resultBus [31:0] $end +$var wire 32 4 result [31:0] $end +$var wire 32 5 overrideBus [31:0] $end +$var wire 1 6 overFlowPossible $end +$var wire 33 7 carryinbus [32:0] $end +$var reg 8 8 commandslice [7:0] $end +$scope begin alu_slices[0] $end +$scope module alu1_inst $end +$var wire 1 9 A $end +$var wire 1 : A_ $end +$var wire 1 ; B $end +$var wire 1 < B_ $end +$var wire 1 = carryin $end +$var wire 8 > command [7:0] $end +$var wire 1 ? zero $end +$var wire 8 @ results [7:0] $end +$var wire 1 A result $end +$var wire 8 B carryouts [7:0] $end +$var wire 1 C carryout $end +$scope module adder $end +$var wire 1 9 a $end +$var wire 1 ; b $end +$var wire 1 = carryin $end +$var wire 1 D carryout $end +$var wire 1 E sum $end +$var wire 1 F s1 $end +$var wire 1 G c2 $end +$var wire 1 H c1 $end +$scope module a1 $end +$var wire 1 9 a $end +$var wire 1 ; b $end +$var wire 1 H carryout $end +$var wire 1 F sum $end +$upscope $end +$scope module a2 $end +$var wire 1 F a $end +$var wire 1 = b $end +$var wire 1 G carryout $end +$var wire 1 E sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 I in [7:0] $end +$var wire 8 J sel [7:0] $end +$var wire 1 C out $end +$var wire 8 K ands [7:0] $end +$scope module andP $end +$var wire 8 L A [7:0] $end +$var wire 8 M B [7:0] $end +$var wire 8 N out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 O in [7:0] $end +$var wire 1 C out $end +$var wire 2 P ors [1:0] $end +$scope module or_1 $end +$var wire 4 Q in [3:0] $end +$var wire 1 R out $end +$var wire 2 S ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 T in [3:0] $end +$var wire 1 U out $end +$var wire 2 V ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 W in [7:0] $end +$var wire 8 X sel [7:0] $end +$var wire 1 A out $end +$var wire 8 Y ands [7:0] $end +$scope module andP $end +$var wire 8 Z A [7:0] $end +$var wire 8 [ B [7:0] $end +$var wire 8 \ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ] in [7:0] $end +$var wire 1 A out $end +$var wire 2 ^ ors [1:0] $end +$scope module or_1 $end +$var wire 4 _ in [3:0] $end +$var wire 1 ` out $end +$var wire 2 a ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 b in [3:0] $end +$var wire 1 c out $end +$var wire 2 d ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 9 a $end +$var wire 1 : a_ $end +$var wire 1 ; b $end +$var wire 1 < b_ $end +$var wire 1 = carryin $end +$var wire 1 e eq $end +$var wire 1 f lt $end +$var wire 1 g out $end +$var wire 1 h w0 $end +$upscope $end +$scope module sub $end +$var wire 1 9 a $end +$var wire 1 < b $end +$var wire 1 = carryin $end +$var wire 1 i carryout $end +$var wire 1 j sum $end +$var wire 1 k s1 $end +$var wire 1 l c2 $end +$var wire 1 m c1 $end +$scope module a1 $end +$var wire 1 9 a $end +$var wire 1 < b $end +$var wire 1 m carryout $end +$var wire 1 k sum $end +$upscope $end +$scope module a2 $end +$var wire 1 k a $end +$var wire 1 = b $end +$var wire 1 l carryout $end +$var wire 1 j sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[1] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 n A $end +$var wire 1 o A_ $end +$var wire 1 p B $end +$var wire 1 q B_ $end +$var wire 1 r carryin $end +$var wire 8 s command [7:0] $end +$var wire 1 t zero $end +$var wire 8 u results [7:0] $end +$var wire 1 v result $end +$var wire 8 w carryouts [7:0] $end +$var wire 1 x carryout $end +$scope module adder $end +$var wire 1 n a $end +$var wire 1 p b $end +$var wire 1 r carryin $end +$var wire 1 y carryout $end +$var wire 1 z sum $end +$var wire 1 { s1 $end +$var wire 1 | c2 $end +$var wire 1 } c1 $end +$scope module a1 $end +$var wire 1 n a $end +$var wire 1 p b $end +$var wire 1 } carryout $end +$var wire 1 { sum $end +$upscope $end +$scope module a2 $end +$var wire 1 { a $end +$var wire 1 r b $end +$var wire 1 | carryout $end +$var wire 1 z sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 ~ in [7:0] $end +$var wire 8 !" sel [7:0] $end +$var wire 1 x out $end +$var wire 8 "" ands [7:0] $end +$scope module andP $end +$var wire 8 #" A [7:0] $end +$var wire 8 $" B [7:0] $end +$var wire 8 %" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 &" in [7:0] $end +$var wire 1 x out $end +$var wire 2 '" ors [1:0] $end +$scope module or_1 $end +$var wire 4 (" in [3:0] $end +$var wire 1 )" out $end +$var wire 2 *" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 +" in [3:0] $end +$var wire 1 ," out $end +$var wire 2 -" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 ." in [7:0] $end +$var wire 8 /" sel [7:0] $end +$var wire 1 v out $end +$var wire 8 0" ands [7:0] $end +$scope module andP $end +$var wire 8 1" A [7:0] $end +$var wire 8 2" B [7:0] $end +$var wire 8 3" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 4" in [7:0] $end +$var wire 1 v out $end +$var wire 2 5" ors [1:0] $end +$scope module or_1 $end +$var wire 4 6" in [3:0] $end +$var wire 1 7" out $end +$var wire 2 8" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 9" in [3:0] $end +$var wire 1 :" out $end +$var wire 2 ;" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 n a $end +$var wire 1 o a_ $end +$var wire 1 p b $end +$var wire 1 q b_ $end +$var wire 1 r carryin $end +$var wire 1 <" eq $end +$var wire 1 =" lt $end +$var wire 1 >" out $end +$var wire 1 ?" w0 $end +$upscope $end +$scope module sub $end +$var wire 1 n a $end +$var wire 1 q b $end +$var wire 1 r carryin $end +$var wire 1 @" carryout $end +$var wire 1 A" sum $end +$var wire 1 B" s1 $end +$var wire 1 C" c2 $end +$var wire 1 D" c1 $end +$scope module a1 $end +$var wire 1 n a $end +$var wire 1 q b $end +$var wire 1 D" carryout $end +$var wire 1 B" sum $end +$upscope $end +$scope module a2 $end +$var wire 1 B" a $end +$var wire 1 r b $end +$var wire 1 C" carryout $end +$var wire 1 A" sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[2] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 E" A $end +$var wire 1 F" A_ $end +$var wire 1 G" B $end +$var wire 1 H" B_ $end +$var wire 1 I" carryin $end +$var wire 8 J" command [7:0] $end +$var wire 1 K" zero $end +$var wire 8 L" results [7:0] $end +$var wire 1 M" result $end +$var wire 8 N" carryouts [7:0] $end +$var wire 1 O" carryout $end +$scope module adder $end +$var wire 1 E" a $end +$var wire 1 G" b $end +$var wire 1 I" carryin $end +$var wire 1 P" carryout $end +$var wire 1 Q" sum $end +$var wire 1 R" s1 $end +$var wire 1 S" c2 $end +$var wire 1 T" c1 $end +$scope module a1 $end +$var wire 1 E" a $end +$var wire 1 G" b $end +$var wire 1 T" carryout $end +$var wire 1 R" sum $end +$upscope $end +$scope module a2 $end +$var wire 1 R" a $end +$var wire 1 I" b $end +$var wire 1 S" carryout $end +$var wire 1 Q" sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 U" in [7:0] $end +$var wire 8 V" sel [7:0] $end +$var wire 1 O" out $end +$var wire 8 W" ands [7:0] $end +$scope module andP $end +$var wire 8 X" A [7:0] $end +$var wire 8 Y" B [7:0] $end +$var wire 8 Z" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 [" in [7:0] $end +$var wire 1 O" out $end +$var wire 2 \" ors [1:0] $end +$scope module or_1 $end +$var wire 4 ]" in [3:0] $end +$var wire 1 ^" out $end +$var wire 2 _" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 `" in [3:0] $end +$var wire 1 a" out $end +$var wire 2 b" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 c" in [7:0] $end +$var wire 8 d" sel [7:0] $end +$var wire 1 M" out $end +$var wire 8 e" ands [7:0] $end +$scope module andP $end +$var wire 8 f" A [7:0] $end +$var wire 8 g" B [7:0] $end +$var wire 8 h" out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 i" in [7:0] $end +$var wire 1 M" out $end +$var wire 2 j" ors [1:0] $end +$scope module or_1 $end +$var wire 4 k" in [3:0] $end +$var wire 1 l" out $end +$var wire 2 m" ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 n" in [3:0] $end +$var wire 1 o" out $end +$var wire 2 p" ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 E" a $end +$var wire 1 F" a_ $end +$var wire 1 G" b $end +$var wire 1 H" b_ $end +$var wire 1 I" carryin $end +$var wire 1 q" eq $end +$var wire 1 r" lt $end +$var wire 1 s" out $end +$var wire 1 t" w0 $end +$upscope $end +$scope module sub $end +$var wire 1 E" a $end +$var wire 1 H" b $end +$var wire 1 I" carryin $end +$var wire 1 u" carryout $end +$var wire 1 v" sum $end +$var wire 1 w" s1 $end +$var wire 1 x" c2 $end +$var wire 1 y" c1 $end +$scope module a1 $end +$var wire 1 E" a $end +$var wire 1 H" b $end +$var wire 1 y" carryout $end +$var wire 1 w" sum $end +$upscope $end +$scope module a2 $end +$var wire 1 w" a $end +$var wire 1 I" b $end +$var wire 1 x" carryout $end +$var wire 1 v" sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[3] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 z" A $end +$var wire 1 {" A_ $end +$var wire 1 |" B $end +$var wire 1 }" B_ $end +$var wire 1 ~" carryin $end +$var wire 8 !# command [7:0] $end +$var wire 1 "# zero $end +$var wire 8 ## results [7:0] $end +$var wire 1 $# result $end +$var wire 8 %# carryouts [7:0] $end +$var wire 1 &# carryout $end +$scope module adder $end +$var wire 1 z" a $end +$var wire 1 |" b $end +$var wire 1 ~" carryin $end +$var wire 1 '# carryout $end +$var wire 1 (# sum $end +$var wire 1 )# s1 $end +$var wire 1 *# c2 $end +$var wire 1 +# c1 $end +$scope module a1 $end +$var wire 1 z" a $end +$var wire 1 |" b $end +$var wire 1 +# carryout $end +$var wire 1 )# sum $end +$upscope $end +$scope module a2 $end +$var wire 1 )# a $end +$var wire 1 ~" b $end +$var wire 1 *# carryout $end +$var wire 1 (# sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 ,# in [7:0] $end +$var wire 8 -# sel [7:0] $end +$var wire 1 &# out $end +$var wire 8 .# ands [7:0] $end +$scope module andP $end +$var wire 8 /# A [7:0] $end +$var wire 8 0# B [7:0] $end +$var wire 8 1# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 2# in [7:0] $end +$var wire 1 &# out $end +$var wire 2 3# ors [1:0] $end +$scope module or_1 $end +$var wire 4 4# in [3:0] $end +$var wire 1 5# out $end +$var wire 2 6# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 7# in [3:0] $end +$var wire 1 8# out $end +$var wire 2 9# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 :# in [7:0] $end +$var wire 8 ;# sel [7:0] $end +$var wire 1 $# out $end +$var wire 8 <# ands [7:0] $end +$scope module andP $end +$var wire 8 =# A [7:0] $end +$var wire 8 ># B [7:0] $end +$var wire 8 ?# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 @# in [7:0] $end +$var wire 1 $# out $end +$var wire 2 A# ors [1:0] $end +$scope module or_1 $end +$var wire 4 B# in [3:0] $end +$var wire 1 C# out $end +$var wire 2 D# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 E# in [3:0] $end +$var wire 1 F# out $end +$var wire 2 G# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 z" a $end +$var wire 1 {" a_ $end +$var wire 1 |" b $end +$var wire 1 }" b_ $end +$var wire 1 ~" carryin $end +$var wire 1 H# eq $end +$var wire 1 I# lt $end +$var wire 1 J# out $end +$var wire 1 K# w0 $end +$upscope $end +$scope module sub $end +$var wire 1 z" a $end +$var wire 1 }" b $end +$var wire 1 ~" carryin $end +$var wire 1 L# carryout $end +$var wire 1 M# sum $end +$var wire 1 N# s1 $end +$var wire 1 O# c2 $end +$var wire 1 P# c1 $end +$scope module a1 $end +$var wire 1 z" a $end +$var wire 1 }" b $end +$var wire 1 P# carryout $end +$var wire 1 N# sum $end +$upscope $end +$scope module a2 $end +$var wire 1 N# a $end +$var wire 1 ~" b $end +$var wire 1 O# carryout $end +$var wire 1 M# sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[4] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 Q# A $end +$var wire 1 R# A_ $end +$var wire 1 S# B $end +$var wire 1 T# B_ $end +$var wire 1 U# carryin $end +$var wire 8 V# command [7:0] $end +$var wire 1 W# zero $end +$var wire 8 X# results [7:0] $end +$var wire 1 Y# result $end +$var wire 8 Z# carryouts [7:0] $end +$var wire 1 [# carryout $end +$scope module adder $end +$var wire 1 Q# a $end +$var wire 1 S# b $end +$var wire 1 U# carryin $end +$var wire 1 \# carryout $end +$var wire 1 ]# sum $end +$var wire 1 ^# s1 $end +$var wire 1 _# c2 $end +$var wire 1 `# c1 $end +$scope module a1 $end +$var wire 1 Q# a $end +$var wire 1 S# b $end +$var wire 1 `# carryout $end +$var wire 1 ^# sum $end +$upscope $end +$scope module a2 $end +$var wire 1 ^# a $end +$var wire 1 U# b $end +$var wire 1 _# carryout $end +$var wire 1 ]# sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 a# in [7:0] $end +$var wire 8 b# sel [7:0] $end +$var wire 1 [# out $end +$var wire 8 c# ands [7:0] $end +$scope module andP $end +$var wire 8 d# A [7:0] $end +$var wire 8 e# B [7:0] $end +$var wire 8 f# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 g# in [7:0] $end +$var wire 1 [# out $end +$var wire 2 h# ors [1:0] $end +$scope module or_1 $end +$var wire 4 i# in [3:0] $end +$var wire 1 j# out $end +$var wire 2 k# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 l# in [3:0] $end +$var wire 1 m# out $end +$var wire 2 n# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 o# in [7:0] $end +$var wire 8 p# sel [7:0] $end +$var wire 1 Y# out $end +$var wire 8 q# ands [7:0] $end +$scope module andP $end +$var wire 8 r# A [7:0] $end +$var wire 8 s# B [7:0] $end +$var wire 8 t# out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 u# in [7:0] $end +$var wire 1 Y# out $end +$var wire 2 v# ors [1:0] $end +$scope module or_1 $end +$var wire 4 w# in [3:0] $end +$var wire 1 x# out $end +$var wire 2 y# ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 z# in [3:0] $end +$var wire 1 {# out $end +$var wire 2 |# ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 Q# a $end +$var wire 1 R# a_ $end +$var wire 1 S# b $end +$var wire 1 T# b_ $end +$var wire 1 U# carryin $end +$var wire 1 }# eq $end +$var wire 1 ~# lt $end +$var wire 1 !$ out $end +$var wire 1 "$ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 Q# a $end +$var wire 1 T# b $end +$var wire 1 U# carryin $end +$var wire 1 #$ carryout $end +$var wire 1 $$ sum $end +$var wire 1 %$ s1 $end +$var wire 1 &$ c2 $end +$var wire 1 '$ c1 $end +$scope module a1 $end +$var wire 1 Q# a $end +$var wire 1 T# b $end +$var wire 1 '$ carryout $end +$var wire 1 %$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 %$ a $end +$var wire 1 U# b $end +$var wire 1 &$ carryout $end +$var wire 1 $$ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[5] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 ($ A $end +$var wire 1 )$ A_ $end +$var wire 1 *$ B $end +$var wire 1 +$ B_ $end +$var wire 1 ,$ carryin $end +$var wire 8 -$ command [7:0] $end +$var wire 1 .$ zero $end +$var wire 8 /$ results [7:0] $end +$var wire 1 0$ result $end +$var wire 8 1$ carryouts [7:0] $end +$var wire 1 2$ carryout $end +$scope module adder $end +$var wire 1 ($ a $end +$var wire 1 *$ b $end +$var wire 1 ,$ carryin $end +$var wire 1 3$ carryout $end +$var wire 1 4$ sum $end +$var wire 1 5$ s1 $end +$var wire 1 6$ c2 $end +$var wire 1 7$ c1 $end +$scope module a1 $end +$var wire 1 ($ a $end +$var wire 1 *$ b $end +$var wire 1 7$ carryout $end +$var wire 1 5$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 5$ a $end +$var wire 1 ,$ b $end +$var wire 1 6$ carryout $end +$var wire 1 4$ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 8$ in [7:0] $end +$var wire 8 9$ sel [7:0] $end +$var wire 1 2$ out $end +$var wire 8 :$ ands [7:0] $end +$scope module andP $end +$var wire 8 ;$ A [7:0] $end +$var wire 8 <$ B [7:0] $end +$var wire 8 =$ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 >$ in [7:0] $end +$var wire 1 2$ out $end +$var wire 2 ?$ ors [1:0] $end +$scope module or_1 $end +$var wire 4 @$ in [3:0] $end +$var wire 1 A$ out $end +$var wire 2 B$ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 C$ in [3:0] $end +$var wire 1 D$ out $end +$var wire 2 E$ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 F$ in [7:0] $end +$var wire 8 G$ sel [7:0] $end +$var wire 1 0$ out $end +$var wire 8 H$ ands [7:0] $end +$scope module andP $end +$var wire 8 I$ A [7:0] $end +$var wire 8 J$ B [7:0] $end +$var wire 8 K$ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 L$ in [7:0] $end +$var wire 1 0$ out $end +$var wire 2 M$ ors [1:0] $end +$scope module or_1 $end +$var wire 4 N$ in [3:0] $end +$var wire 1 O$ out $end +$var wire 2 P$ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 Q$ in [3:0] $end +$var wire 1 R$ out $end +$var wire 2 S$ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 ($ a $end +$var wire 1 )$ a_ $end +$var wire 1 *$ b $end +$var wire 1 +$ b_ $end +$var wire 1 ,$ carryin $end +$var wire 1 T$ eq $end +$var wire 1 U$ lt $end +$var wire 1 V$ out $end +$var wire 1 W$ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 ($ a $end +$var wire 1 +$ b $end +$var wire 1 ,$ carryin $end +$var wire 1 X$ carryout $end +$var wire 1 Y$ sum $end +$var wire 1 Z$ s1 $end +$var wire 1 [$ c2 $end +$var wire 1 \$ c1 $end +$scope module a1 $end +$var wire 1 ($ a $end +$var wire 1 +$ b $end +$var wire 1 \$ carryout $end +$var wire 1 Z$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 Z$ a $end +$var wire 1 ,$ b $end +$var wire 1 [$ carryout $end +$var wire 1 Y$ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[6] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 ]$ A $end +$var wire 1 ^$ A_ $end +$var wire 1 _$ B $end +$var wire 1 `$ B_ $end +$var wire 1 a$ carryin $end +$var wire 8 b$ command [7:0] $end +$var wire 1 c$ zero $end +$var wire 8 d$ results [7:0] $end +$var wire 1 e$ result $end +$var wire 8 f$ carryouts [7:0] $end +$var wire 1 g$ carryout $end +$scope module adder $end +$var wire 1 ]$ a $end +$var wire 1 _$ b $end +$var wire 1 a$ carryin $end +$var wire 1 h$ carryout $end +$var wire 1 i$ sum $end +$var wire 1 j$ s1 $end +$var wire 1 k$ c2 $end +$var wire 1 l$ c1 $end +$scope module a1 $end +$var wire 1 ]$ a $end +$var wire 1 _$ b $end +$var wire 1 l$ carryout $end +$var wire 1 j$ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 j$ a $end +$var wire 1 a$ b $end +$var wire 1 k$ carryout $end +$var wire 1 i$ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 m$ in [7:0] $end +$var wire 8 n$ sel [7:0] $end +$var wire 1 g$ out $end +$var wire 8 o$ ands [7:0] $end +$scope module andP $end +$var wire 8 p$ A [7:0] $end +$var wire 8 q$ B [7:0] $end +$var wire 8 r$ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 s$ in [7:0] $end +$var wire 1 g$ out $end +$var wire 2 t$ ors [1:0] $end +$scope module or_1 $end +$var wire 4 u$ in [3:0] $end +$var wire 1 v$ out $end +$var wire 2 w$ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 x$ in [3:0] $end +$var wire 1 y$ out $end +$var wire 2 z$ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 {$ in [7:0] $end +$var wire 8 |$ sel [7:0] $end +$var wire 1 e$ out $end +$var wire 8 }$ ands [7:0] $end +$scope module andP $end +$var wire 8 ~$ A [7:0] $end +$var wire 8 !% B [7:0] $end +$var wire 8 "% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 #% in [7:0] $end +$var wire 1 e$ out $end +$var wire 2 $% ors [1:0] $end +$scope module or_1 $end +$var wire 4 %% in [3:0] $end +$var wire 1 &% out $end +$var wire 2 '% ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 (% in [3:0] $end +$var wire 1 )% out $end +$var wire 2 *% ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 ]$ a $end +$var wire 1 ^$ a_ $end +$var wire 1 _$ b $end +$var wire 1 `$ b_ $end +$var wire 1 a$ carryin $end +$var wire 1 +% eq $end +$var wire 1 ,% lt $end +$var wire 1 -% out $end +$var wire 1 .% w0 $end +$upscope $end +$scope module sub $end +$var wire 1 ]$ a $end +$var wire 1 `$ b $end +$var wire 1 a$ carryin $end +$var wire 1 /% carryout $end +$var wire 1 0% sum $end +$var wire 1 1% s1 $end +$var wire 1 2% c2 $end +$var wire 1 3% c1 $end +$scope module a1 $end +$var wire 1 ]$ a $end +$var wire 1 `$ b $end +$var wire 1 3% carryout $end +$var wire 1 1% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 1% a $end +$var wire 1 a$ b $end +$var wire 1 2% carryout $end +$var wire 1 0% sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[7] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 4% A $end +$var wire 1 5% A_ $end +$var wire 1 6% B $end +$var wire 1 7% B_ $end +$var wire 1 8% carryin $end +$var wire 8 9% command [7:0] $end +$var wire 1 :% zero $end +$var wire 8 ;% results [7:0] $end +$var wire 1 <% result $end +$var wire 8 =% carryouts [7:0] $end +$var wire 1 >% carryout $end +$scope module adder $end +$var wire 1 4% a $end +$var wire 1 6% b $end +$var wire 1 8% carryin $end +$var wire 1 ?% carryout $end +$var wire 1 @% sum $end +$var wire 1 A% s1 $end +$var wire 1 B% c2 $end +$var wire 1 C% c1 $end +$scope module a1 $end +$var wire 1 4% a $end +$var wire 1 6% b $end +$var wire 1 C% carryout $end +$var wire 1 A% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 A% a $end +$var wire 1 8% b $end +$var wire 1 B% carryout $end +$var wire 1 @% sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 D% in [7:0] $end +$var wire 8 E% sel [7:0] $end +$var wire 1 >% out $end +$var wire 8 F% ands [7:0] $end +$scope module andP $end +$var wire 8 G% A [7:0] $end +$var wire 8 H% B [7:0] $end +$var wire 8 I% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 J% in [7:0] $end +$var wire 1 >% out $end +$var wire 2 K% ors [1:0] $end +$scope module or_1 $end +$var wire 4 L% in [3:0] $end +$var wire 1 M% out $end +$var wire 2 N% ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 O% in [3:0] $end +$var wire 1 P% out $end +$var wire 2 Q% ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 R% in [7:0] $end +$var wire 8 S% sel [7:0] $end +$var wire 1 <% out $end +$var wire 8 T% ands [7:0] $end +$scope module andP $end +$var wire 8 U% A [7:0] $end +$var wire 8 V% B [7:0] $end +$var wire 8 W% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 X% in [7:0] $end +$var wire 1 <% out $end +$var wire 2 Y% ors [1:0] $end +$scope module or_1 $end +$var wire 4 Z% in [3:0] $end +$var wire 1 [% out $end +$var wire 2 \% ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ]% in [3:0] $end +$var wire 1 ^% out $end +$var wire 2 _% ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 4% a $end +$var wire 1 5% a_ $end +$var wire 1 6% b $end +$var wire 1 7% b_ $end +$var wire 1 8% carryin $end +$var wire 1 `% eq $end +$var wire 1 a% lt $end +$var wire 1 b% out $end +$var wire 1 c% w0 $end +$upscope $end +$scope module sub $end +$var wire 1 4% a $end +$var wire 1 7% b $end +$var wire 1 8% carryin $end +$var wire 1 d% carryout $end +$var wire 1 e% sum $end +$var wire 1 f% s1 $end +$var wire 1 g% c2 $end +$var wire 1 h% c1 $end +$scope module a1 $end +$var wire 1 4% a $end +$var wire 1 7% b $end +$var wire 1 h% carryout $end +$var wire 1 f% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 f% a $end +$var wire 1 8% b $end +$var wire 1 g% carryout $end +$var wire 1 e% sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[8] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 i% A $end +$var wire 1 j% A_ $end +$var wire 1 k% B $end +$var wire 1 l% B_ $end +$var wire 1 m% carryin $end +$var wire 8 n% command [7:0] $end +$var wire 1 o% zero $end +$var wire 8 p% results [7:0] $end +$var wire 1 q% result $end +$var wire 8 r% carryouts [7:0] $end +$var wire 1 s% carryout $end +$scope module adder $end +$var wire 1 i% a $end +$var wire 1 k% b $end +$var wire 1 m% carryin $end +$var wire 1 t% carryout $end +$var wire 1 u% sum $end +$var wire 1 v% s1 $end +$var wire 1 w% c2 $end +$var wire 1 x% c1 $end +$scope module a1 $end +$var wire 1 i% a $end +$var wire 1 k% b $end +$var wire 1 x% carryout $end +$var wire 1 v% sum $end +$upscope $end +$scope module a2 $end +$var wire 1 v% a $end +$var wire 1 m% b $end +$var wire 1 w% carryout $end +$var wire 1 u% sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 y% in [7:0] $end +$var wire 8 z% sel [7:0] $end +$var wire 1 s% out $end +$var wire 8 {% ands [7:0] $end +$scope module andP $end +$var wire 8 |% A [7:0] $end +$var wire 8 }% B [7:0] $end +$var wire 8 ~% out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 !& in [7:0] $end +$var wire 1 s% out $end +$var wire 2 "& ors [1:0] $end +$scope module or_1 $end +$var wire 4 #& in [3:0] $end +$var wire 1 $& out $end +$var wire 2 %& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 && in [3:0] $end +$var wire 1 '& out $end +$var wire 2 (& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 )& in [7:0] $end +$var wire 8 *& sel [7:0] $end +$var wire 1 q% out $end +$var wire 8 +& ands [7:0] $end +$scope module andP $end +$var wire 8 ,& A [7:0] $end +$var wire 8 -& B [7:0] $end +$var wire 8 .& out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 /& in [7:0] $end +$var wire 1 q% out $end +$var wire 2 0& ors [1:0] $end +$scope module or_1 $end +$var wire 4 1& in [3:0] $end +$var wire 1 2& out $end +$var wire 2 3& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 4& in [3:0] $end +$var wire 1 5& out $end +$var wire 2 6& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 i% a $end +$var wire 1 j% a_ $end +$var wire 1 k% b $end +$var wire 1 l% b_ $end +$var wire 1 m% carryin $end +$var wire 1 7& eq $end +$var wire 1 8& lt $end +$var wire 1 9& out $end +$var wire 1 :& w0 $end +$upscope $end +$scope module sub $end +$var wire 1 i% a $end +$var wire 1 l% b $end +$var wire 1 m% carryin $end +$var wire 1 ;& carryout $end +$var wire 1 <& sum $end +$var wire 1 =& s1 $end +$var wire 1 >& c2 $end +$var wire 1 ?& c1 $end +$scope module a1 $end +$var wire 1 i% a $end +$var wire 1 l% b $end +$var wire 1 ?& carryout $end +$var wire 1 =& sum $end +$upscope $end +$scope module a2 $end +$var wire 1 =& a $end +$var wire 1 m% b $end +$var wire 1 >& carryout $end +$var wire 1 <& sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[9] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 @& A $end +$var wire 1 A& A_ $end +$var wire 1 B& B $end +$var wire 1 C& B_ $end +$var wire 1 D& carryin $end +$var wire 8 E& command [7:0] $end +$var wire 1 F& zero $end +$var wire 8 G& results [7:0] $end +$var wire 1 H& result $end +$var wire 8 I& carryouts [7:0] $end +$var wire 1 J& carryout $end +$scope module adder $end +$var wire 1 @& a $end +$var wire 1 B& b $end +$var wire 1 D& carryin $end +$var wire 1 K& carryout $end +$var wire 1 L& sum $end +$var wire 1 M& s1 $end +$var wire 1 N& c2 $end +$var wire 1 O& c1 $end +$scope module a1 $end +$var wire 1 @& a $end +$var wire 1 B& b $end +$var wire 1 O& carryout $end +$var wire 1 M& sum $end +$upscope $end +$scope module a2 $end +$var wire 1 M& a $end +$var wire 1 D& b $end +$var wire 1 N& carryout $end +$var wire 1 L& sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 P& in [7:0] $end +$var wire 8 Q& sel [7:0] $end +$var wire 1 J& out $end +$var wire 8 R& ands [7:0] $end +$scope module andP $end +$var wire 8 S& A [7:0] $end +$var wire 8 T& B [7:0] $end +$var wire 8 U& out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 V& in [7:0] $end +$var wire 1 J& out $end +$var wire 2 W& ors [1:0] $end +$scope module or_1 $end +$var wire 4 X& in [3:0] $end +$var wire 1 Y& out $end +$var wire 2 Z& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 [& in [3:0] $end +$var wire 1 \& out $end +$var wire 2 ]& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 ^& in [7:0] $end +$var wire 8 _& sel [7:0] $end +$var wire 1 H& out $end +$var wire 8 `& ands [7:0] $end +$scope module andP $end +$var wire 8 a& A [7:0] $end +$var wire 8 b& B [7:0] $end +$var wire 8 c& out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 d& in [7:0] $end +$var wire 1 H& out $end +$var wire 2 e& ors [1:0] $end +$scope module or_1 $end +$var wire 4 f& in [3:0] $end +$var wire 1 g& out $end +$var wire 2 h& ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 i& in [3:0] $end +$var wire 1 j& out $end +$var wire 2 k& ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 @& a $end +$var wire 1 A& a_ $end +$var wire 1 B& b $end +$var wire 1 C& b_ $end +$var wire 1 D& carryin $end +$var wire 1 l& eq $end +$var wire 1 m& lt $end +$var wire 1 n& out $end +$var wire 1 o& w0 $end +$upscope $end +$scope module sub $end +$var wire 1 @& a $end +$var wire 1 C& b $end +$var wire 1 D& carryin $end +$var wire 1 p& carryout $end +$var wire 1 q& sum $end +$var wire 1 r& s1 $end +$var wire 1 s& c2 $end +$var wire 1 t& c1 $end +$scope module a1 $end +$var wire 1 @& a $end +$var wire 1 C& b $end +$var wire 1 t& carryout $end +$var wire 1 r& sum $end +$upscope $end +$scope module a2 $end +$var wire 1 r& a $end +$var wire 1 D& b $end +$var wire 1 s& carryout $end +$var wire 1 q& sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[10] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 u& A $end +$var wire 1 v& A_ $end +$var wire 1 w& B $end +$var wire 1 x& B_ $end +$var wire 1 y& carryin $end +$var wire 8 z& command [7:0] $end +$var wire 1 {& zero $end +$var wire 8 |& results [7:0] $end +$var wire 1 }& result $end +$var wire 8 ~& carryouts [7:0] $end +$var wire 1 !' carryout $end +$scope module adder $end +$var wire 1 u& a $end +$var wire 1 w& b $end +$var wire 1 y& carryin $end +$var wire 1 "' carryout $end +$var wire 1 #' sum $end +$var wire 1 $' s1 $end +$var wire 1 %' c2 $end +$var wire 1 &' c1 $end +$scope module a1 $end +$var wire 1 u& a $end +$var wire 1 w& b $end +$var wire 1 &' carryout $end +$var wire 1 $' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 $' a $end +$var wire 1 y& b $end +$var wire 1 %' carryout $end +$var wire 1 #' sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 '' in [7:0] $end +$var wire 8 (' sel [7:0] $end +$var wire 1 !' out $end +$var wire 8 )' ands [7:0] $end +$scope module andP $end +$var wire 8 *' A [7:0] $end +$var wire 8 +' B [7:0] $end +$var wire 8 ,' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 -' in [7:0] $end +$var wire 1 !' out $end +$var wire 2 .' ors [1:0] $end +$scope module or_1 $end +$var wire 4 /' in [3:0] $end +$var wire 1 0' out $end +$var wire 2 1' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 2' in [3:0] $end +$var wire 1 3' out $end +$var wire 2 4' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 5' in [7:0] $end +$var wire 8 6' sel [7:0] $end +$var wire 1 }& out $end +$var wire 8 7' ands [7:0] $end +$scope module andP $end +$var wire 8 8' A [7:0] $end +$var wire 8 9' B [7:0] $end +$var wire 8 :' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ;' in [7:0] $end +$var wire 1 }& out $end +$var wire 2 <' ors [1:0] $end +$scope module or_1 $end +$var wire 4 =' in [3:0] $end +$var wire 1 >' out $end +$var wire 2 ?' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 @' in [3:0] $end +$var wire 1 A' out $end +$var wire 2 B' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 u& a $end +$var wire 1 v& a_ $end +$var wire 1 w& b $end +$var wire 1 x& b_ $end +$var wire 1 y& carryin $end +$var wire 1 C' eq $end +$var wire 1 D' lt $end +$var wire 1 E' out $end +$var wire 1 F' w0 $end +$upscope $end +$scope module sub $end +$var wire 1 u& a $end +$var wire 1 x& b $end +$var wire 1 y& carryin $end +$var wire 1 G' carryout $end +$var wire 1 H' sum $end +$var wire 1 I' s1 $end +$var wire 1 J' c2 $end +$var wire 1 K' c1 $end +$scope module a1 $end +$var wire 1 u& a $end +$var wire 1 x& b $end +$var wire 1 K' carryout $end +$var wire 1 I' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 I' a $end +$var wire 1 y& b $end +$var wire 1 J' carryout $end +$var wire 1 H' sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[11] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 L' A $end +$var wire 1 M' A_ $end +$var wire 1 N' B $end +$var wire 1 O' B_ $end +$var wire 1 P' carryin $end +$var wire 8 Q' command [7:0] $end +$var wire 1 R' zero $end +$var wire 8 S' results [7:0] $end +$var wire 1 T' result $end +$var wire 8 U' carryouts [7:0] $end +$var wire 1 V' carryout $end +$scope module adder $end +$var wire 1 L' a $end +$var wire 1 N' b $end +$var wire 1 P' carryin $end +$var wire 1 W' carryout $end +$var wire 1 X' sum $end +$var wire 1 Y' s1 $end +$var wire 1 Z' c2 $end +$var wire 1 [' c1 $end +$scope module a1 $end +$var wire 1 L' a $end +$var wire 1 N' b $end +$var wire 1 [' carryout $end +$var wire 1 Y' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 Y' a $end +$var wire 1 P' b $end +$var wire 1 Z' carryout $end +$var wire 1 X' sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 \' in [7:0] $end +$var wire 8 ]' sel [7:0] $end +$var wire 1 V' out $end +$var wire 8 ^' ands [7:0] $end +$scope module andP $end +$var wire 8 _' A [7:0] $end +$var wire 8 `' B [7:0] $end +$var wire 8 a' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 b' in [7:0] $end +$var wire 1 V' out $end +$var wire 2 c' ors [1:0] $end +$scope module or_1 $end +$var wire 4 d' in [3:0] $end +$var wire 1 e' out $end +$var wire 2 f' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 g' in [3:0] $end +$var wire 1 h' out $end +$var wire 2 i' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 j' in [7:0] $end +$var wire 8 k' sel [7:0] $end +$var wire 1 T' out $end +$var wire 8 l' ands [7:0] $end +$scope module andP $end +$var wire 8 m' A [7:0] $end +$var wire 8 n' B [7:0] $end +$var wire 8 o' out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 p' in [7:0] $end +$var wire 1 T' out $end +$var wire 2 q' ors [1:0] $end +$scope module or_1 $end +$var wire 4 r' in [3:0] $end +$var wire 1 s' out $end +$var wire 2 t' ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 u' in [3:0] $end +$var wire 1 v' out $end +$var wire 2 w' ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 L' a $end +$var wire 1 M' a_ $end +$var wire 1 N' b $end +$var wire 1 O' b_ $end +$var wire 1 P' carryin $end +$var wire 1 x' eq $end +$var wire 1 y' lt $end +$var wire 1 z' out $end +$var wire 1 {' w0 $end +$upscope $end +$scope module sub $end +$var wire 1 L' a $end +$var wire 1 O' b $end +$var wire 1 P' carryin $end +$var wire 1 |' carryout $end +$var wire 1 }' sum $end +$var wire 1 ~' s1 $end +$var wire 1 !( c2 $end +$var wire 1 "( c1 $end +$scope module a1 $end +$var wire 1 L' a $end +$var wire 1 O' b $end +$var wire 1 "( carryout $end +$var wire 1 ~' sum $end +$upscope $end +$scope module a2 $end +$var wire 1 ~' a $end +$var wire 1 P' b $end +$var wire 1 !( carryout $end +$var wire 1 }' sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[12] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 #( A $end +$var wire 1 $( A_ $end +$var wire 1 %( B $end +$var wire 1 &( B_ $end +$var wire 1 '( carryin $end +$var wire 8 (( command [7:0] $end +$var wire 1 )( zero $end +$var wire 8 *( results [7:0] $end +$var wire 1 +( result $end +$var wire 8 ,( carryouts [7:0] $end +$var wire 1 -( carryout $end +$scope module adder $end +$var wire 1 #( a $end +$var wire 1 %( b $end +$var wire 1 '( carryin $end +$var wire 1 .( carryout $end +$var wire 1 /( sum $end +$var wire 1 0( s1 $end +$var wire 1 1( c2 $end +$var wire 1 2( c1 $end +$scope module a1 $end +$var wire 1 #( a $end +$var wire 1 %( b $end +$var wire 1 2( carryout $end +$var wire 1 0( sum $end +$upscope $end +$scope module a2 $end +$var wire 1 0( a $end +$var wire 1 '( b $end +$var wire 1 1( carryout $end +$var wire 1 /( sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 3( in [7:0] $end +$var wire 8 4( sel [7:0] $end +$var wire 1 -( out $end +$var wire 8 5( ands [7:0] $end +$scope module andP $end +$var wire 8 6( A [7:0] $end +$var wire 8 7( B [7:0] $end +$var wire 8 8( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 9( in [7:0] $end +$var wire 1 -( out $end +$var wire 2 :( ors [1:0] $end +$scope module or_1 $end +$var wire 4 ;( in [3:0] $end +$var wire 1 <( out $end +$var wire 2 =( ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 >( in [3:0] $end +$var wire 1 ?( out $end +$var wire 2 @( ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 A( in [7:0] $end +$var wire 8 B( sel [7:0] $end +$var wire 1 +( out $end +$var wire 8 C( ands [7:0] $end +$scope module andP $end +$var wire 8 D( A [7:0] $end +$var wire 8 E( B [7:0] $end +$var wire 8 F( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 G( in [7:0] $end +$var wire 1 +( out $end +$var wire 2 H( ors [1:0] $end +$scope module or_1 $end +$var wire 4 I( in [3:0] $end +$var wire 1 J( out $end +$var wire 2 K( ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 L( in [3:0] $end +$var wire 1 M( out $end +$var wire 2 N( ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 #( a $end +$var wire 1 $( a_ $end +$var wire 1 %( b $end +$var wire 1 &( b_ $end +$var wire 1 '( carryin $end +$var wire 1 O( eq $end +$var wire 1 P( lt $end +$var wire 1 Q( out $end +$var wire 1 R( w0 $end +$upscope $end +$scope module sub $end +$var wire 1 #( a $end +$var wire 1 &( b $end +$var wire 1 '( carryin $end +$var wire 1 S( carryout $end +$var wire 1 T( sum $end +$var wire 1 U( s1 $end +$var wire 1 V( c2 $end +$var wire 1 W( c1 $end +$scope module a1 $end +$var wire 1 #( a $end +$var wire 1 &( b $end +$var wire 1 W( carryout $end +$var wire 1 U( sum $end +$upscope $end +$scope module a2 $end +$var wire 1 U( a $end +$var wire 1 '( b $end +$var wire 1 V( carryout $end +$var wire 1 T( sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[13] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 X( A $end +$var wire 1 Y( A_ $end +$var wire 1 Z( B $end +$var wire 1 [( B_ $end +$var wire 1 \( carryin $end +$var wire 8 ]( command [7:0] $end +$var wire 1 ^( zero $end +$var wire 8 _( results [7:0] $end +$var wire 1 `( result $end +$var wire 8 a( carryouts [7:0] $end +$var wire 1 b( carryout $end +$scope module adder $end +$var wire 1 X( a $end +$var wire 1 Z( b $end +$var wire 1 \( carryin $end +$var wire 1 c( carryout $end +$var wire 1 d( sum $end +$var wire 1 e( s1 $end +$var wire 1 f( c2 $end +$var wire 1 g( c1 $end +$scope module a1 $end +$var wire 1 X( a $end +$var wire 1 Z( b $end +$var wire 1 g( carryout $end +$var wire 1 e( sum $end +$upscope $end +$scope module a2 $end +$var wire 1 e( a $end +$var wire 1 \( b $end +$var wire 1 f( carryout $end +$var wire 1 d( sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 h( in [7:0] $end +$var wire 8 i( sel [7:0] $end +$var wire 1 b( out $end +$var wire 8 j( ands [7:0] $end +$scope module andP $end +$var wire 8 k( A [7:0] $end +$var wire 8 l( B [7:0] $end +$var wire 8 m( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 n( in [7:0] $end +$var wire 1 b( out $end +$var wire 2 o( ors [1:0] $end +$scope module or_1 $end +$var wire 4 p( in [3:0] $end +$var wire 1 q( out $end +$var wire 2 r( ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 s( in [3:0] $end +$var wire 1 t( out $end +$var wire 2 u( ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 v( in [7:0] $end +$var wire 8 w( sel [7:0] $end +$var wire 1 `( out $end +$var wire 8 x( ands [7:0] $end +$scope module andP $end +$var wire 8 y( A [7:0] $end +$var wire 8 z( B [7:0] $end +$var wire 8 {( out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 |( in [7:0] $end +$var wire 1 `( out $end +$var wire 2 }( ors [1:0] $end +$scope module or_1 $end +$var wire 4 ~( in [3:0] $end +$var wire 1 !) out $end +$var wire 2 ") ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 #) in [3:0] $end +$var wire 1 $) out $end +$var wire 2 %) ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 X( a $end +$var wire 1 Y( a_ $end +$var wire 1 Z( b $end +$var wire 1 [( b_ $end +$var wire 1 \( carryin $end +$var wire 1 &) eq $end +$var wire 1 ') lt $end +$var wire 1 () out $end +$var wire 1 )) w0 $end +$upscope $end +$scope module sub $end +$var wire 1 X( a $end +$var wire 1 [( b $end +$var wire 1 \( carryin $end +$var wire 1 *) carryout $end +$var wire 1 +) sum $end +$var wire 1 ,) s1 $end +$var wire 1 -) c2 $end +$var wire 1 .) c1 $end +$scope module a1 $end +$var wire 1 X( a $end +$var wire 1 [( b $end +$var wire 1 .) carryout $end +$var wire 1 ,) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 ,) a $end +$var wire 1 \( b $end +$var wire 1 -) carryout $end +$var wire 1 +) sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[14] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 /) A $end +$var wire 1 0) A_ $end +$var wire 1 1) B $end +$var wire 1 2) B_ $end +$var wire 1 3) carryin $end +$var wire 8 4) command [7:0] $end +$var wire 1 5) zero $end +$var wire 8 6) results [7:0] $end +$var wire 1 7) result $end +$var wire 8 8) carryouts [7:0] $end +$var wire 1 9) carryout $end +$scope module adder $end +$var wire 1 /) a $end +$var wire 1 1) b $end +$var wire 1 3) carryin $end +$var wire 1 :) carryout $end +$var wire 1 ;) sum $end +$var wire 1 <) s1 $end +$var wire 1 =) c2 $end +$var wire 1 >) c1 $end +$scope module a1 $end +$var wire 1 /) a $end +$var wire 1 1) b $end +$var wire 1 >) carryout $end +$var wire 1 <) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 <) a $end +$var wire 1 3) b $end +$var wire 1 =) carryout $end +$var wire 1 ;) sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 ?) in [7:0] $end +$var wire 8 @) sel [7:0] $end +$var wire 1 9) out $end +$var wire 8 A) ands [7:0] $end +$scope module andP $end +$var wire 8 B) A [7:0] $end +$var wire 8 C) B [7:0] $end +$var wire 8 D) out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 E) in [7:0] $end +$var wire 1 9) out $end +$var wire 2 F) ors [1:0] $end +$scope module or_1 $end +$var wire 4 G) in [3:0] $end +$var wire 1 H) out $end +$var wire 2 I) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 J) in [3:0] $end +$var wire 1 K) out $end +$var wire 2 L) ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 M) in [7:0] $end +$var wire 8 N) sel [7:0] $end +$var wire 1 7) out $end +$var wire 8 O) ands [7:0] $end +$scope module andP $end +$var wire 8 P) A [7:0] $end +$var wire 8 Q) B [7:0] $end +$var wire 8 R) out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 S) in [7:0] $end +$var wire 1 7) out $end +$var wire 2 T) ors [1:0] $end +$scope module or_1 $end +$var wire 4 U) in [3:0] $end +$var wire 1 V) out $end +$var wire 2 W) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 X) in [3:0] $end +$var wire 1 Y) out $end +$var wire 2 Z) ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 /) a $end +$var wire 1 0) a_ $end +$var wire 1 1) b $end +$var wire 1 2) b_ $end +$var wire 1 3) carryin $end +$var wire 1 [) eq $end +$var wire 1 \) lt $end +$var wire 1 ]) out $end +$var wire 1 ^) w0 $end +$upscope $end +$scope module sub $end +$var wire 1 /) a $end +$var wire 1 2) b $end +$var wire 1 3) carryin $end +$var wire 1 _) carryout $end +$var wire 1 `) sum $end +$var wire 1 a) s1 $end +$var wire 1 b) c2 $end +$var wire 1 c) c1 $end +$scope module a1 $end +$var wire 1 /) a $end +$var wire 1 2) b $end +$var wire 1 c) carryout $end +$var wire 1 a) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 a) a $end +$var wire 1 3) b $end +$var wire 1 b) carryout $end +$var wire 1 `) sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[15] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 d) A $end +$var wire 1 e) A_ $end +$var wire 1 f) B $end +$var wire 1 g) B_ $end +$var wire 1 h) carryin $end +$var wire 8 i) command [7:0] $end +$var wire 1 j) zero $end +$var wire 8 k) results [7:0] $end +$var wire 1 l) result $end +$var wire 8 m) carryouts [7:0] $end +$var wire 1 n) carryout $end +$scope module adder $end +$var wire 1 d) a $end +$var wire 1 f) b $end +$var wire 1 h) carryin $end +$var wire 1 o) carryout $end +$var wire 1 p) sum $end +$var wire 1 q) s1 $end +$var wire 1 r) c2 $end +$var wire 1 s) c1 $end +$scope module a1 $end +$var wire 1 d) a $end +$var wire 1 f) b $end +$var wire 1 s) carryout $end +$var wire 1 q) sum $end +$upscope $end +$scope module a2 $end +$var wire 1 q) a $end +$var wire 1 h) b $end +$var wire 1 r) carryout $end +$var wire 1 p) sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 t) in [7:0] $end +$var wire 8 u) sel [7:0] $end +$var wire 1 n) out $end +$var wire 8 v) ands [7:0] $end +$scope module andP $end +$var wire 8 w) A [7:0] $end +$var wire 8 x) B [7:0] $end +$var wire 8 y) out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 z) in [7:0] $end +$var wire 1 n) out $end +$var wire 2 {) ors [1:0] $end +$scope module or_1 $end +$var wire 4 |) in [3:0] $end +$var wire 1 }) out $end +$var wire 2 ~) ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 !* in [3:0] $end +$var wire 1 "* out $end +$var wire 2 #* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 $* in [7:0] $end +$var wire 8 %* sel [7:0] $end +$var wire 1 l) out $end +$var wire 8 &* ands [7:0] $end +$scope module andP $end +$var wire 8 '* A [7:0] $end +$var wire 8 (* B [7:0] $end +$var wire 8 )* out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ** in [7:0] $end +$var wire 1 l) out $end +$var wire 2 +* ors [1:0] $end +$scope module or_1 $end +$var wire 4 ,* in [3:0] $end +$var wire 1 -* out $end +$var wire 2 .* ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 /* in [3:0] $end +$var wire 1 0* out $end +$var wire 2 1* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 d) a $end +$var wire 1 e) a_ $end +$var wire 1 f) b $end +$var wire 1 g) b_ $end +$var wire 1 h) carryin $end +$var wire 1 2* eq $end +$var wire 1 3* lt $end +$var wire 1 4* out $end +$var wire 1 5* w0 $end +$upscope $end +$scope module sub $end +$var wire 1 d) a $end +$var wire 1 g) b $end +$var wire 1 h) carryin $end +$var wire 1 6* carryout $end +$var wire 1 7* sum $end +$var wire 1 8* s1 $end +$var wire 1 9* c2 $end +$var wire 1 :* c1 $end +$scope module a1 $end +$var wire 1 d) a $end +$var wire 1 g) b $end +$var wire 1 :* carryout $end +$var wire 1 8* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 8* a $end +$var wire 1 h) b $end +$var wire 1 9* carryout $end +$var wire 1 7* sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[16] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 ;* A $end +$var wire 1 <* A_ $end +$var wire 1 =* B $end +$var wire 1 >* B_ $end +$var wire 1 ?* carryin $end +$var wire 8 @* command [7:0] $end +$var wire 1 A* zero $end +$var wire 8 B* results [7:0] $end +$var wire 1 C* result $end +$var wire 8 D* carryouts [7:0] $end +$var wire 1 E* carryout $end +$scope module adder $end +$var wire 1 ;* a $end +$var wire 1 =* b $end +$var wire 1 ?* carryin $end +$var wire 1 F* carryout $end +$var wire 1 G* sum $end +$var wire 1 H* s1 $end +$var wire 1 I* c2 $end +$var wire 1 J* c1 $end +$scope module a1 $end +$var wire 1 ;* a $end +$var wire 1 =* b $end +$var wire 1 J* carryout $end +$var wire 1 H* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 H* a $end +$var wire 1 ?* b $end +$var wire 1 I* carryout $end +$var wire 1 G* sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 K* in [7:0] $end +$var wire 8 L* sel [7:0] $end +$var wire 1 E* out $end +$var wire 8 M* ands [7:0] $end +$scope module andP $end +$var wire 8 N* A [7:0] $end +$var wire 8 O* B [7:0] $end +$var wire 8 P* out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 Q* in [7:0] $end +$var wire 1 E* out $end +$var wire 2 R* ors [1:0] $end +$scope module or_1 $end +$var wire 4 S* in [3:0] $end +$var wire 1 T* out $end +$var wire 2 U* ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 V* in [3:0] $end +$var wire 1 W* out $end +$var wire 2 X* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 Y* in [7:0] $end +$var wire 8 Z* sel [7:0] $end +$var wire 1 C* out $end +$var wire 8 [* ands [7:0] $end +$scope module andP $end +$var wire 8 \* A [7:0] $end +$var wire 8 ]* B [7:0] $end +$var wire 8 ^* out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 _* in [7:0] $end +$var wire 1 C* out $end +$var wire 2 `* ors [1:0] $end +$scope module or_1 $end +$var wire 4 a* in [3:0] $end +$var wire 1 b* out $end +$var wire 2 c* ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 d* in [3:0] $end +$var wire 1 e* out $end +$var wire 2 f* ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 ;* a $end +$var wire 1 <* a_ $end +$var wire 1 =* b $end +$var wire 1 >* b_ $end +$var wire 1 ?* carryin $end +$var wire 1 g* eq $end +$var wire 1 h* lt $end +$var wire 1 i* out $end +$var wire 1 j* w0 $end +$upscope $end +$scope module sub $end +$var wire 1 ;* a $end +$var wire 1 >* b $end +$var wire 1 ?* carryin $end +$var wire 1 k* carryout $end +$var wire 1 l* sum $end +$var wire 1 m* s1 $end +$var wire 1 n* c2 $end +$var wire 1 o* c1 $end +$scope module a1 $end +$var wire 1 ;* a $end +$var wire 1 >* b $end +$var wire 1 o* carryout $end +$var wire 1 m* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 m* a $end +$var wire 1 ?* b $end +$var wire 1 n* carryout $end +$var wire 1 l* sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[17] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 p* A $end +$var wire 1 q* A_ $end +$var wire 1 r* B $end +$var wire 1 s* B_ $end +$var wire 1 t* carryin $end +$var wire 8 u* command [7:0] $end +$var wire 1 v* zero $end +$var wire 8 w* results [7:0] $end +$var wire 1 x* result $end +$var wire 8 y* carryouts [7:0] $end +$var wire 1 z* carryout $end +$scope module adder $end +$var wire 1 p* a $end +$var wire 1 r* b $end +$var wire 1 t* carryin $end +$var wire 1 {* carryout $end +$var wire 1 |* sum $end +$var wire 1 }* s1 $end +$var wire 1 ~* c2 $end +$var wire 1 !+ c1 $end +$scope module a1 $end +$var wire 1 p* a $end +$var wire 1 r* b $end +$var wire 1 !+ carryout $end +$var wire 1 }* sum $end +$upscope $end +$scope module a2 $end +$var wire 1 }* a $end +$var wire 1 t* b $end +$var wire 1 ~* carryout $end +$var wire 1 |* sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 "+ in [7:0] $end +$var wire 8 #+ sel [7:0] $end +$var wire 1 z* out $end +$var wire 8 $+ ands [7:0] $end +$scope module andP $end +$var wire 8 %+ A [7:0] $end +$var wire 8 &+ B [7:0] $end +$var wire 8 '+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 (+ in [7:0] $end +$var wire 1 z* out $end +$var wire 2 )+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 *+ in [3:0] $end +$var wire 1 ++ out $end +$var wire 2 ,+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 -+ in [3:0] $end +$var wire 1 .+ out $end +$var wire 2 /+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 0+ in [7:0] $end +$var wire 8 1+ sel [7:0] $end +$var wire 1 x* out $end +$var wire 8 2+ ands [7:0] $end +$scope module andP $end +$var wire 8 3+ A [7:0] $end +$var wire 8 4+ B [7:0] $end +$var wire 8 5+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 6+ in [7:0] $end +$var wire 1 x* out $end +$var wire 2 7+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 8+ in [3:0] $end +$var wire 1 9+ out $end +$var wire 2 :+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ;+ in [3:0] $end +$var wire 1 <+ out $end +$var wire 2 =+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 p* a $end +$var wire 1 q* a_ $end +$var wire 1 r* b $end +$var wire 1 s* b_ $end +$var wire 1 t* carryin $end +$var wire 1 >+ eq $end +$var wire 1 ?+ lt $end +$var wire 1 @+ out $end +$var wire 1 A+ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 p* a $end +$var wire 1 s* b $end +$var wire 1 t* carryin $end +$var wire 1 B+ carryout $end +$var wire 1 C+ sum $end +$var wire 1 D+ s1 $end +$var wire 1 E+ c2 $end +$var wire 1 F+ c1 $end +$scope module a1 $end +$var wire 1 p* a $end +$var wire 1 s* b $end +$var wire 1 F+ carryout $end +$var wire 1 D+ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 D+ a $end +$var wire 1 t* b $end +$var wire 1 E+ carryout $end +$var wire 1 C+ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[18] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 G+ A $end +$var wire 1 H+ A_ $end +$var wire 1 I+ B $end +$var wire 1 J+ B_ $end +$var wire 1 K+ carryin $end +$var wire 8 L+ command [7:0] $end +$var wire 1 M+ zero $end +$var wire 8 N+ results [7:0] $end +$var wire 1 O+ result $end +$var wire 8 P+ carryouts [7:0] $end +$var wire 1 Q+ carryout $end +$scope module adder $end +$var wire 1 G+ a $end +$var wire 1 I+ b $end +$var wire 1 K+ carryin $end +$var wire 1 R+ carryout $end +$var wire 1 S+ sum $end +$var wire 1 T+ s1 $end +$var wire 1 U+ c2 $end +$var wire 1 V+ c1 $end +$scope module a1 $end +$var wire 1 G+ a $end +$var wire 1 I+ b $end +$var wire 1 V+ carryout $end +$var wire 1 T+ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 T+ a $end +$var wire 1 K+ b $end +$var wire 1 U+ carryout $end +$var wire 1 S+ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 W+ in [7:0] $end +$var wire 8 X+ sel [7:0] $end +$var wire 1 Q+ out $end +$var wire 8 Y+ ands [7:0] $end +$scope module andP $end +$var wire 8 Z+ A [7:0] $end +$var wire 8 [+ B [7:0] $end +$var wire 8 \+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ]+ in [7:0] $end +$var wire 1 Q+ out $end +$var wire 2 ^+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 _+ in [3:0] $end +$var wire 1 `+ out $end +$var wire 2 a+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 b+ in [3:0] $end +$var wire 1 c+ out $end +$var wire 2 d+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 e+ in [7:0] $end +$var wire 8 f+ sel [7:0] $end +$var wire 1 O+ out $end +$var wire 8 g+ ands [7:0] $end +$scope module andP $end +$var wire 8 h+ A [7:0] $end +$var wire 8 i+ B [7:0] $end +$var wire 8 j+ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 k+ in [7:0] $end +$var wire 1 O+ out $end +$var wire 2 l+ ors [1:0] $end +$scope module or_1 $end +$var wire 4 m+ in [3:0] $end +$var wire 1 n+ out $end +$var wire 2 o+ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 p+ in [3:0] $end +$var wire 1 q+ out $end +$var wire 2 r+ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 G+ a $end +$var wire 1 H+ a_ $end +$var wire 1 I+ b $end +$var wire 1 J+ b_ $end +$var wire 1 K+ carryin $end +$var wire 1 s+ eq $end +$var wire 1 t+ lt $end +$var wire 1 u+ out $end +$var wire 1 v+ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 G+ a $end +$var wire 1 J+ b $end +$var wire 1 K+ carryin $end +$var wire 1 w+ carryout $end +$var wire 1 x+ sum $end +$var wire 1 y+ s1 $end +$var wire 1 z+ c2 $end +$var wire 1 {+ c1 $end +$scope module a1 $end +$var wire 1 G+ a $end +$var wire 1 J+ b $end +$var wire 1 {+ carryout $end +$var wire 1 y+ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 y+ a $end +$var wire 1 K+ b $end +$var wire 1 z+ carryout $end +$var wire 1 x+ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[19] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 |+ A $end +$var wire 1 }+ A_ $end +$var wire 1 ~+ B $end +$var wire 1 !, B_ $end +$var wire 1 ", carryin $end +$var wire 8 #, command [7:0] $end +$var wire 1 $, zero $end +$var wire 8 %, results [7:0] $end +$var wire 1 &, result $end +$var wire 8 ', carryouts [7:0] $end +$var wire 1 (, carryout $end +$scope module adder $end +$var wire 1 |+ a $end +$var wire 1 ~+ b $end +$var wire 1 ", carryin $end +$var wire 1 ), carryout $end +$var wire 1 *, sum $end +$var wire 1 +, s1 $end +$var wire 1 ,, c2 $end +$var wire 1 -, c1 $end +$scope module a1 $end +$var wire 1 |+ a $end +$var wire 1 ~+ b $end +$var wire 1 -, carryout $end +$var wire 1 +, sum $end +$upscope $end +$scope module a2 $end +$var wire 1 +, a $end +$var wire 1 ", b $end +$var wire 1 ,, carryout $end +$var wire 1 *, sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 ., in [7:0] $end +$var wire 8 /, sel [7:0] $end +$var wire 1 (, out $end +$var wire 8 0, ands [7:0] $end +$scope module andP $end +$var wire 8 1, A [7:0] $end +$var wire 8 2, B [7:0] $end +$var wire 8 3, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 4, in [7:0] $end +$var wire 1 (, out $end +$var wire 2 5, ors [1:0] $end +$scope module or_1 $end +$var wire 4 6, in [3:0] $end +$var wire 1 7, out $end +$var wire 2 8, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 9, in [3:0] $end +$var wire 1 :, out $end +$var wire 2 ;, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 <, in [7:0] $end +$var wire 8 =, sel [7:0] $end +$var wire 1 &, out $end +$var wire 8 >, ands [7:0] $end +$scope module andP $end +$var wire 8 ?, A [7:0] $end +$var wire 8 @, B [7:0] $end +$var wire 8 A, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 B, in [7:0] $end +$var wire 1 &, out $end +$var wire 2 C, ors [1:0] $end +$scope module or_1 $end +$var wire 4 D, in [3:0] $end +$var wire 1 E, out $end +$var wire 2 F, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 G, in [3:0] $end +$var wire 1 H, out $end +$var wire 2 I, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 |+ a $end +$var wire 1 }+ a_ $end +$var wire 1 ~+ b $end +$var wire 1 !, b_ $end +$var wire 1 ", carryin $end +$var wire 1 J, eq $end +$var wire 1 K, lt $end +$var wire 1 L, out $end +$var wire 1 M, w0 $end +$upscope $end +$scope module sub $end +$var wire 1 |+ a $end +$var wire 1 !, b $end +$var wire 1 ", carryin $end +$var wire 1 N, carryout $end +$var wire 1 O, sum $end +$var wire 1 P, s1 $end +$var wire 1 Q, c2 $end +$var wire 1 R, c1 $end +$scope module a1 $end +$var wire 1 |+ a $end +$var wire 1 !, b $end +$var wire 1 R, carryout $end +$var wire 1 P, sum $end +$upscope $end +$scope module a2 $end +$var wire 1 P, a $end +$var wire 1 ", b $end +$var wire 1 Q, carryout $end +$var wire 1 O, sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[20] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 S, A $end +$var wire 1 T, A_ $end +$var wire 1 U, B $end +$var wire 1 V, B_ $end +$var wire 1 W, carryin $end +$var wire 8 X, command [7:0] $end +$var wire 1 Y, zero $end +$var wire 8 Z, results [7:0] $end +$var wire 1 [, result $end +$var wire 8 \, carryouts [7:0] $end +$var wire 1 ], carryout $end +$scope module adder $end +$var wire 1 S, a $end +$var wire 1 U, b $end +$var wire 1 W, carryin $end +$var wire 1 ^, carryout $end +$var wire 1 _, sum $end +$var wire 1 `, s1 $end +$var wire 1 a, c2 $end +$var wire 1 b, c1 $end +$scope module a1 $end +$var wire 1 S, a $end +$var wire 1 U, b $end +$var wire 1 b, carryout $end +$var wire 1 `, sum $end +$upscope $end +$scope module a2 $end +$var wire 1 `, a $end +$var wire 1 W, b $end +$var wire 1 a, carryout $end +$var wire 1 _, sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 c, in [7:0] $end +$var wire 8 d, sel [7:0] $end +$var wire 1 ], out $end +$var wire 8 e, ands [7:0] $end +$scope module andP $end +$var wire 8 f, A [7:0] $end +$var wire 8 g, B [7:0] $end +$var wire 8 h, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 i, in [7:0] $end +$var wire 1 ], out $end +$var wire 2 j, ors [1:0] $end +$scope module or_1 $end +$var wire 4 k, in [3:0] $end +$var wire 1 l, out $end +$var wire 2 m, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 n, in [3:0] $end +$var wire 1 o, out $end +$var wire 2 p, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 q, in [7:0] $end +$var wire 8 r, sel [7:0] $end +$var wire 1 [, out $end +$var wire 8 s, ands [7:0] $end +$scope module andP $end +$var wire 8 t, A [7:0] $end +$var wire 8 u, B [7:0] $end +$var wire 8 v, out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 w, in [7:0] $end +$var wire 1 [, out $end +$var wire 2 x, ors [1:0] $end +$scope module or_1 $end +$var wire 4 y, in [3:0] $end +$var wire 1 z, out $end +$var wire 2 {, ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 |, in [3:0] $end +$var wire 1 }, out $end +$var wire 2 ~, ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 S, a $end +$var wire 1 T, a_ $end +$var wire 1 U, b $end +$var wire 1 V, b_ $end +$var wire 1 W, carryin $end +$var wire 1 !- eq $end +$var wire 1 "- lt $end +$var wire 1 #- out $end +$var wire 1 $- w0 $end +$upscope $end +$scope module sub $end +$var wire 1 S, a $end +$var wire 1 V, b $end +$var wire 1 W, carryin $end +$var wire 1 %- carryout $end +$var wire 1 &- sum $end +$var wire 1 '- s1 $end +$var wire 1 (- c2 $end +$var wire 1 )- c1 $end +$scope module a1 $end +$var wire 1 S, a $end +$var wire 1 V, b $end +$var wire 1 )- carryout $end +$var wire 1 '- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 '- a $end +$var wire 1 W, b $end +$var wire 1 (- carryout $end +$var wire 1 &- sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[21] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 *- A $end +$var wire 1 +- A_ $end +$var wire 1 ,- B $end +$var wire 1 -- B_ $end +$var wire 1 .- carryin $end +$var wire 8 /- command [7:0] $end +$var wire 1 0- zero $end +$var wire 8 1- results [7:0] $end +$var wire 1 2- result $end +$var wire 8 3- carryouts [7:0] $end +$var wire 1 4- carryout $end +$scope module adder $end +$var wire 1 *- a $end +$var wire 1 ,- b $end +$var wire 1 .- carryin $end +$var wire 1 5- carryout $end +$var wire 1 6- sum $end +$var wire 1 7- s1 $end +$var wire 1 8- c2 $end +$var wire 1 9- c1 $end +$scope module a1 $end +$var wire 1 *- a $end +$var wire 1 ,- b $end +$var wire 1 9- carryout $end +$var wire 1 7- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 7- a $end +$var wire 1 .- b $end +$var wire 1 8- carryout $end +$var wire 1 6- sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 :- in [7:0] $end +$var wire 8 ;- sel [7:0] $end +$var wire 1 4- out $end +$var wire 8 <- ands [7:0] $end +$scope module andP $end +$var wire 8 =- A [7:0] $end +$var wire 8 >- B [7:0] $end +$var wire 8 ?- out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 @- in [7:0] $end +$var wire 1 4- out $end +$var wire 2 A- ors [1:0] $end +$scope module or_1 $end +$var wire 4 B- in [3:0] $end +$var wire 1 C- out $end +$var wire 2 D- ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 E- in [3:0] $end +$var wire 1 F- out $end +$var wire 2 G- ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 H- in [7:0] $end +$var wire 8 I- sel [7:0] $end +$var wire 1 2- out $end +$var wire 8 J- ands [7:0] $end +$scope module andP $end +$var wire 8 K- A [7:0] $end +$var wire 8 L- B [7:0] $end +$var wire 8 M- out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 N- in [7:0] $end +$var wire 1 2- out $end +$var wire 2 O- ors [1:0] $end +$scope module or_1 $end +$var wire 4 P- in [3:0] $end +$var wire 1 Q- out $end +$var wire 2 R- ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 S- in [3:0] $end +$var wire 1 T- out $end +$var wire 2 U- ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 *- a $end +$var wire 1 +- a_ $end +$var wire 1 ,- b $end +$var wire 1 -- b_ $end +$var wire 1 .- carryin $end +$var wire 1 V- eq $end +$var wire 1 W- lt $end +$var wire 1 X- out $end +$var wire 1 Y- w0 $end +$upscope $end +$scope module sub $end +$var wire 1 *- a $end +$var wire 1 -- b $end +$var wire 1 .- carryin $end +$var wire 1 Z- carryout $end +$var wire 1 [- sum $end +$var wire 1 \- s1 $end +$var wire 1 ]- c2 $end +$var wire 1 ^- c1 $end +$scope module a1 $end +$var wire 1 *- a $end +$var wire 1 -- b $end +$var wire 1 ^- carryout $end +$var wire 1 \- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 \- a $end +$var wire 1 .- b $end +$var wire 1 ]- carryout $end +$var wire 1 [- sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[22] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 _- A $end +$var wire 1 `- A_ $end +$var wire 1 a- B $end +$var wire 1 b- B_ $end +$var wire 1 c- carryin $end +$var wire 8 d- command [7:0] $end +$var wire 1 e- zero $end +$var wire 8 f- results [7:0] $end +$var wire 1 g- result $end +$var wire 8 h- carryouts [7:0] $end +$var wire 1 i- carryout $end +$scope module adder $end +$var wire 1 _- a $end +$var wire 1 a- b $end +$var wire 1 c- carryin $end +$var wire 1 j- carryout $end +$var wire 1 k- sum $end +$var wire 1 l- s1 $end +$var wire 1 m- c2 $end +$var wire 1 n- c1 $end +$scope module a1 $end +$var wire 1 _- a $end +$var wire 1 a- b $end +$var wire 1 n- carryout $end +$var wire 1 l- sum $end +$upscope $end +$scope module a2 $end +$var wire 1 l- a $end +$var wire 1 c- b $end +$var wire 1 m- carryout $end +$var wire 1 k- sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 o- in [7:0] $end +$var wire 8 p- sel [7:0] $end +$var wire 1 i- out $end +$var wire 8 q- ands [7:0] $end +$scope module andP $end +$var wire 8 r- A [7:0] $end +$var wire 8 s- B [7:0] $end +$var wire 8 t- out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 u- in [7:0] $end +$var wire 1 i- out $end +$var wire 2 v- ors [1:0] $end +$scope module or_1 $end +$var wire 4 w- in [3:0] $end +$var wire 1 x- out $end +$var wire 2 y- ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 z- in [3:0] $end +$var wire 1 {- out $end +$var wire 2 |- ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 }- in [7:0] $end +$var wire 8 ~- sel [7:0] $end +$var wire 1 g- out $end +$var wire 8 !. ands [7:0] $end +$scope module andP $end +$var wire 8 ". A [7:0] $end +$var wire 8 #. B [7:0] $end +$var wire 8 $. out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 %. in [7:0] $end +$var wire 1 g- out $end +$var wire 2 &. ors [1:0] $end +$scope module or_1 $end +$var wire 4 '. in [3:0] $end +$var wire 1 (. out $end +$var wire 2 ). ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 *. in [3:0] $end +$var wire 1 +. out $end +$var wire 2 ,. ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 _- a $end +$var wire 1 `- a_ $end +$var wire 1 a- b $end +$var wire 1 b- b_ $end +$var wire 1 c- carryin $end +$var wire 1 -. eq $end +$var wire 1 .. lt $end +$var wire 1 /. out $end +$var wire 1 0. w0 $end +$upscope $end +$scope module sub $end +$var wire 1 _- a $end +$var wire 1 b- b $end +$var wire 1 c- carryin $end +$var wire 1 1. carryout $end +$var wire 1 2. sum $end +$var wire 1 3. s1 $end +$var wire 1 4. c2 $end +$var wire 1 5. c1 $end +$scope module a1 $end +$var wire 1 _- a $end +$var wire 1 b- b $end +$var wire 1 5. carryout $end +$var wire 1 3. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 3. a $end +$var wire 1 c- b $end +$var wire 1 4. carryout $end +$var wire 1 2. sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[23] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 6. A $end +$var wire 1 7. A_ $end +$var wire 1 8. B $end +$var wire 1 9. B_ $end +$var wire 1 :. carryin $end +$var wire 8 ;. command [7:0] $end +$var wire 1 <. zero $end +$var wire 8 =. results [7:0] $end +$var wire 1 >. result $end +$var wire 8 ?. carryouts [7:0] $end +$var wire 1 @. carryout $end +$scope module adder $end +$var wire 1 6. a $end +$var wire 1 8. b $end +$var wire 1 :. carryin $end +$var wire 1 A. carryout $end +$var wire 1 B. sum $end +$var wire 1 C. s1 $end +$var wire 1 D. c2 $end +$var wire 1 E. c1 $end +$scope module a1 $end +$var wire 1 6. a $end +$var wire 1 8. b $end +$var wire 1 E. carryout $end +$var wire 1 C. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 C. a $end +$var wire 1 :. b $end +$var wire 1 D. carryout $end +$var wire 1 B. sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 F. in [7:0] $end +$var wire 8 G. sel [7:0] $end +$var wire 1 @. out $end +$var wire 8 H. ands [7:0] $end +$scope module andP $end +$var wire 8 I. A [7:0] $end +$var wire 8 J. B [7:0] $end +$var wire 8 K. out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 L. in [7:0] $end +$var wire 1 @. out $end +$var wire 2 M. ors [1:0] $end +$scope module or_1 $end +$var wire 4 N. in [3:0] $end +$var wire 1 O. out $end +$var wire 2 P. ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 Q. in [3:0] $end +$var wire 1 R. out $end +$var wire 2 S. ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 T. in [7:0] $end +$var wire 8 U. sel [7:0] $end +$var wire 1 >. out $end +$var wire 8 V. ands [7:0] $end +$scope module andP $end +$var wire 8 W. A [7:0] $end +$var wire 8 X. B [7:0] $end +$var wire 8 Y. out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 Z. in [7:0] $end +$var wire 1 >. out $end +$var wire 2 [. ors [1:0] $end +$scope module or_1 $end +$var wire 4 \. in [3:0] $end +$var wire 1 ]. out $end +$var wire 2 ^. ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 _. in [3:0] $end +$var wire 1 `. out $end +$var wire 2 a. ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 6. a $end +$var wire 1 7. a_ $end +$var wire 1 8. b $end +$var wire 1 9. b_ $end +$var wire 1 :. carryin $end +$var wire 1 b. eq $end +$var wire 1 c. lt $end +$var wire 1 d. out $end +$var wire 1 e. w0 $end +$upscope $end +$scope module sub $end +$var wire 1 6. a $end +$var wire 1 9. b $end +$var wire 1 :. carryin $end +$var wire 1 f. carryout $end +$var wire 1 g. sum $end +$var wire 1 h. s1 $end +$var wire 1 i. c2 $end +$var wire 1 j. c1 $end +$scope module a1 $end +$var wire 1 6. a $end +$var wire 1 9. b $end +$var wire 1 j. carryout $end +$var wire 1 h. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 h. a $end +$var wire 1 :. b $end +$var wire 1 i. carryout $end +$var wire 1 g. sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[24] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 k. A $end +$var wire 1 l. A_ $end +$var wire 1 m. B $end +$var wire 1 n. B_ $end +$var wire 1 o. carryin $end +$var wire 8 p. command [7:0] $end +$var wire 1 q. zero $end +$var wire 8 r. results [7:0] $end +$var wire 1 s. result $end +$var wire 8 t. carryouts [7:0] $end +$var wire 1 u. carryout $end +$scope module adder $end +$var wire 1 k. a $end +$var wire 1 m. b $end +$var wire 1 o. carryin $end +$var wire 1 v. carryout $end +$var wire 1 w. sum $end +$var wire 1 x. s1 $end +$var wire 1 y. c2 $end +$var wire 1 z. c1 $end +$scope module a1 $end +$var wire 1 k. a $end +$var wire 1 m. b $end +$var wire 1 z. carryout $end +$var wire 1 x. sum $end +$upscope $end +$scope module a2 $end +$var wire 1 x. a $end +$var wire 1 o. b $end +$var wire 1 y. carryout $end +$var wire 1 w. sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 {. in [7:0] $end +$var wire 8 |. sel [7:0] $end +$var wire 1 u. out $end +$var wire 8 }. ands [7:0] $end +$scope module andP $end +$var wire 8 ~. A [7:0] $end +$var wire 8 !/ B [7:0] $end +$var wire 8 "/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 #/ in [7:0] $end +$var wire 1 u. out $end +$var wire 2 $/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 %/ in [3:0] $end +$var wire 1 &/ out $end +$var wire 2 '/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 (/ in [3:0] $end +$var wire 1 )/ out $end +$var wire 2 */ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 +/ in [7:0] $end +$var wire 8 ,/ sel [7:0] $end +$var wire 1 s. out $end +$var wire 8 -/ ands [7:0] $end +$scope module andP $end +$var wire 8 ./ A [7:0] $end +$var wire 8 // B [7:0] $end +$var wire 8 0/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 1/ in [7:0] $end +$var wire 1 s. out $end +$var wire 2 2/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 3/ in [3:0] $end +$var wire 1 4/ out $end +$var wire 2 5/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 6/ in [3:0] $end +$var wire 1 7/ out $end +$var wire 2 8/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 k. a $end +$var wire 1 l. a_ $end +$var wire 1 m. b $end +$var wire 1 n. b_ $end +$var wire 1 o. carryin $end +$var wire 1 9/ eq $end +$var wire 1 :/ lt $end +$var wire 1 ;/ out $end +$var wire 1 / sum $end +$var wire 1 ?/ s1 $end +$var wire 1 @/ c2 $end +$var wire 1 A/ c1 $end +$scope module a1 $end +$var wire 1 k. a $end +$var wire 1 n. b $end +$var wire 1 A/ carryout $end +$var wire 1 ?/ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 ?/ a $end +$var wire 1 o. b $end +$var wire 1 @/ carryout $end +$var wire 1 >/ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[25] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 B/ A $end +$var wire 1 C/ A_ $end +$var wire 1 D/ B $end +$var wire 1 E/ B_ $end +$var wire 1 F/ carryin $end +$var wire 8 G/ command [7:0] $end +$var wire 1 H/ zero $end +$var wire 8 I/ results [7:0] $end +$var wire 1 J/ result $end +$var wire 8 K/ carryouts [7:0] $end +$var wire 1 L/ carryout $end +$scope module adder $end +$var wire 1 B/ a $end +$var wire 1 D/ b $end +$var wire 1 F/ carryin $end +$var wire 1 M/ carryout $end +$var wire 1 N/ sum $end +$var wire 1 O/ s1 $end +$var wire 1 P/ c2 $end +$var wire 1 Q/ c1 $end +$scope module a1 $end +$var wire 1 B/ a $end +$var wire 1 D/ b $end +$var wire 1 Q/ carryout $end +$var wire 1 O/ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 O/ a $end +$var wire 1 F/ b $end +$var wire 1 P/ carryout $end +$var wire 1 N/ sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 R/ in [7:0] $end +$var wire 8 S/ sel [7:0] $end +$var wire 1 L/ out $end +$var wire 8 T/ ands [7:0] $end +$scope module andP $end +$var wire 8 U/ A [7:0] $end +$var wire 8 V/ B [7:0] $end +$var wire 8 W/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 X/ in [7:0] $end +$var wire 1 L/ out $end +$var wire 2 Y/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 Z/ in [3:0] $end +$var wire 1 [/ out $end +$var wire 2 \/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 ]/ in [3:0] $end +$var wire 1 ^/ out $end +$var wire 2 _/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 `/ in [7:0] $end +$var wire 8 a/ sel [7:0] $end +$var wire 1 J/ out $end +$var wire 8 b/ ands [7:0] $end +$scope module andP $end +$var wire 8 c/ A [7:0] $end +$var wire 8 d/ B [7:0] $end +$var wire 8 e/ out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 f/ in [7:0] $end +$var wire 1 J/ out $end +$var wire 2 g/ ors [1:0] $end +$scope module or_1 $end +$var wire 4 h/ in [3:0] $end +$var wire 1 i/ out $end +$var wire 2 j/ ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 k/ in [3:0] $end +$var wire 1 l/ out $end +$var wire 2 m/ ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 B/ a $end +$var wire 1 C/ a_ $end +$var wire 1 D/ b $end +$var wire 1 E/ b_ $end +$var wire 1 F/ carryin $end +$var wire 1 n/ eq $end +$var wire 1 o/ lt $end +$var wire 1 p/ out $end +$var wire 1 q/ w0 $end +$upscope $end +$scope module sub $end +$var wire 1 B/ a $end +$var wire 1 E/ b $end +$var wire 1 F/ carryin $end +$var wire 1 r/ carryout $end +$var wire 1 s/ sum $end +$var wire 1 t/ s1 $end +$var wire 1 u/ c2 $end +$var wire 1 v/ c1 $end +$scope module a1 $end +$var wire 1 B/ a $end +$var wire 1 E/ b $end +$var wire 1 v/ carryout $end +$var wire 1 t/ sum $end +$upscope $end +$scope module a2 $end +$var wire 1 t/ a $end +$var wire 1 F/ b $end +$var wire 1 u/ carryout $end +$var wire 1 s/ sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[26] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 w/ A $end +$var wire 1 x/ A_ $end +$var wire 1 y/ B $end +$var wire 1 z/ B_ $end +$var wire 1 {/ carryin $end +$var wire 8 |/ command [7:0] $end +$var wire 1 }/ zero $end +$var wire 8 ~/ results [7:0] $end +$var wire 1 !0 result $end +$var wire 8 "0 carryouts [7:0] $end +$var wire 1 #0 carryout $end +$scope module adder $end +$var wire 1 w/ a $end +$var wire 1 y/ b $end +$var wire 1 {/ carryin $end +$var wire 1 $0 carryout $end +$var wire 1 %0 sum $end +$var wire 1 &0 s1 $end +$var wire 1 '0 c2 $end +$var wire 1 (0 c1 $end +$scope module a1 $end +$var wire 1 w/ a $end +$var wire 1 y/ b $end +$var wire 1 (0 carryout $end +$var wire 1 &0 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 &0 a $end +$var wire 1 {/ b $end +$var wire 1 '0 carryout $end +$var wire 1 %0 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 )0 in [7:0] $end +$var wire 8 *0 sel [7:0] $end +$var wire 1 #0 out $end +$var wire 8 +0 ands [7:0] $end +$scope module andP $end +$var wire 8 ,0 A [7:0] $end +$var wire 8 -0 B [7:0] $end +$var wire 8 .0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 /0 in [7:0] $end +$var wire 1 #0 out $end +$var wire 2 00 ors [1:0] $end +$scope module or_1 $end +$var wire 4 10 in [3:0] $end +$var wire 1 20 out $end +$var wire 2 30 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 40 in [3:0] $end +$var wire 1 50 out $end +$var wire 2 60 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 70 in [7:0] $end +$var wire 8 80 sel [7:0] $end +$var wire 1 !0 out $end +$var wire 8 90 ands [7:0] $end +$scope module andP $end +$var wire 8 :0 A [7:0] $end +$var wire 8 ;0 B [7:0] $end +$var wire 8 <0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 =0 in [7:0] $end +$var wire 1 !0 out $end +$var wire 2 >0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 ?0 in [3:0] $end +$var wire 1 @0 out $end +$var wire 2 A0 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 B0 in [3:0] $end +$var wire 1 C0 out $end +$var wire 2 D0 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 w/ a $end +$var wire 1 x/ a_ $end +$var wire 1 y/ b $end +$var wire 1 z/ b_ $end +$var wire 1 {/ carryin $end +$var wire 1 E0 eq $end +$var wire 1 F0 lt $end +$var wire 1 G0 out $end +$var wire 1 H0 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 w/ a $end +$var wire 1 z/ b $end +$var wire 1 {/ carryin $end +$var wire 1 I0 carryout $end +$var wire 1 J0 sum $end +$var wire 1 K0 s1 $end +$var wire 1 L0 c2 $end +$var wire 1 M0 c1 $end +$scope module a1 $end +$var wire 1 w/ a $end +$var wire 1 z/ b $end +$var wire 1 M0 carryout $end +$var wire 1 K0 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 K0 a $end +$var wire 1 {/ b $end +$var wire 1 L0 carryout $end +$var wire 1 J0 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[27] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 N0 A $end +$var wire 1 O0 A_ $end +$var wire 1 P0 B $end +$var wire 1 Q0 B_ $end +$var wire 1 R0 carryin $end +$var wire 8 S0 command [7:0] $end +$var wire 1 T0 zero $end +$var wire 8 U0 results [7:0] $end +$var wire 1 V0 result $end +$var wire 8 W0 carryouts [7:0] $end +$var wire 1 X0 carryout $end +$scope module adder $end +$var wire 1 N0 a $end +$var wire 1 P0 b $end +$var wire 1 R0 carryin $end +$var wire 1 Y0 carryout $end +$var wire 1 Z0 sum $end +$var wire 1 [0 s1 $end +$var wire 1 \0 c2 $end +$var wire 1 ]0 c1 $end +$scope module a1 $end +$var wire 1 N0 a $end +$var wire 1 P0 b $end +$var wire 1 ]0 carryout $end +$var wire 1 [0 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 [0 a $end +$var wire 1 R0 b $end +$var wire 1 \0 carryout $end +$var wire 1 Z0 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 ^0 in [7:0] $end +$var wire 8 _0 sel [7:0] $end +$var wire 1 X0 out $end +$var wire 8 `0 ands [7:0] $end +$scope module andP $end +$var wire 8 a0 A [7:0] $end +$var wire 8 b0 B [7:0] $end +$var wire 8 c0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 d0 in [7:0] $end +$var wire 1 X0 out $end +$var wire 2 e0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 f0 in [3:0] $end +$var wire 1 g0 out $end +$var wire 2 h0 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 i0 in [3:0] $end +$var wire 1 j0 out $end +$var wire 2 k0 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 l0 in [7:0] $end +$var wire 8 m0 sel [7:0] $end +$var wire 1 V0 out $end +$var wire 8 n0 ands [7:0] $end +$scope module andP $end +$var wire 8 o0 A [7:0] $end +$var wire 8 p0 B [7:0] $end +$var wire 8 q0 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 r0 in [7:0] $end +$var wire 1 V0 out $end +$var wire 2 s0 ors [1:0] $end +$scope module or_1 $end +$var wire 4 t0 in [3:0] $end +$var wire 1 u0 out $end +$var wire 2 v0 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 w0 in [3:0] $end +$var wire 1 x0 out $end +$var wire 2 y0 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 N0 a $end +$var wire 1 O0 a_ $end +$var wire 1 P0 b $end +$var wire 1 Q0 b_ $end +$var wire 1 R0 carryin $end +$var wire 1 z0 eq $end +$var wire 1 {0 lt $end +$var wire 1 |0 out $end +$var wire 1 }0 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 N0 a $end +$var wire 1 Q0 b $end +$var wire 1 R0 carryin $end +$var wire 1 ~0 carryout $end +$var wire 1 !1 sum $end +$var wire 1 "1 s1 $end +$var wire 1 #1 c2 $end +$var wire 1 $1 c1 $end +$scope module a1 $end +$var wire 1 N0 a $end +$var wire 1 Q0 b $end +$var wire 1 $1 carryout $end +$var wire 1 "1 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 "1 a $end +$var wire 1 R0 b $end +$var wire 1 #1 carryout $end +$var wire 1 !1 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[28] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 %1 A $end +$var wire 1 &1 A_ $end +$var wire 1 '1 B $end +$var wire 1 (1 B_ $end +$var wire 1 )1 carryin $end +$var wire 8 *1 command [7:0] $end +$var wire 1 +1 zero $end +$var wire 8 ,1 results [7:0] $end +$var wire 1 -1 result $end +$var wire 8 .1 carryouts [7:0] $end +$var wire 1 /1 carryout $end +$scope module adder $end +$var wire 1 %1 a $end +$var wire 1 '1 b $end +$var wire 1 )1 carryin $end +$var wire 1 01 carryout $end +$var wire 1 11 sum $end +$var wire 1 21 s1 $end +$var wire 1 31 c2 $end +$var wire 1 41 c1 $end +$scope module a1 $end +$var wire 1 %1 a $end +$var wire 1 '1 b $end +$var wire 1 41 carryout $end +$var wire 1 21 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 21 a $end +$var wire 1 )1 b $end +$var wire 1 31 carryout $end +$var wire 1 11 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 51 in [7:0] $end +$var wire 8 61 sel [7:0] $end +$var wire 1 /1 out $end +$var wire 8 71 ands [7:0] $end +$scope module andP $end +$var wire 8 81 A [7:0] $end +$var wire 8 91 B [7:0] $end +$var wire 8 :1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ;1 in [7:0] $end +$var wire 1 /1 out $end +$var wire 2 <1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 =1 in [3:0] $end +$var wire 1 >1 out $end +$var wire 2 ?1 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 @1 in [3:0] $end +$var wire 1 A1 out $end +$var wire 2 B1 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 C1 in [7:0] $end +$var wire 8 D1 sel [7:0] $end +$var wire 1 -1 out $end +$var wire 8 E1 ands [7:0] $end +$scope module andP $end +$var wire 8 F1 A [7:0] $end +$var wire 8 G1 B [7:0] $end +$var wire 8 H1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 I1 in [7:0] $end +$var wire 1 -1 out $end +$var wire 2 J1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 K1 in [3:0] $end +$var wire 1 L1 out $end +$var wire 2 M1 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 N1 in [3:0] $end +$var wire 1 O1 out $end +$var wire 2 P1 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 %1 a $end +$var wire 1 &1 a_ $end +$var wire 1 '1 b $end +$var wire 1 (1 b_ $end +$var wire 1 )1 carryin $end +$var wire 1 Q1 eq $end +$var wire 1 R1 lt $end +$var wire 1 S1 out $end +$var wire 1 T1 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 %1 a $end +$var wire 1 (1 b $end +$var wire 1 )1 carryin $end +$var wire 1 U1 carryout $end +$var wire 1 V1 sum $end +$var wire 1 W1 s1 $end +$var wire 1 X1 c2 $end +$var wire 1 Y1 c1 $end +$scope module a1 $end +$var wire 1 %1 a $end +$var wire 1 (1 b $end +$var wire 1 Y1 carryout $end +$var wire 1 W1 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 W1 a $end +$var wire 1 )1 b $end +$var wire 1 X1 carryout $end +$var wire 1 V1 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[29] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 Z1 A $end +$var wire 1 [1 A_ $end +$var wire 1 \1 B $end +$var wire 1 ]1 B_ $end +$var wire 1 ^1 carryin $end +$var wire 8 _1 command [7:0] $end +$var wire 1 `1 zero $end +$var wire 8 a1 results [7:0] $end +$var wire 1 b1 result $end +$var wire 8 c1 carryouts [7:0] $end +$var wire 1 d1 carryout $end +$scope module adder $end +$var wire 1 Z1 a $end +$var wire 1 \1 b $end +$var wire 1 ^1 carryin $end +$var wire 1 e1 carryout $end +$var wire 1 f1 sum $end +$var wire 1 g1 s1 $end +$var wire 1 h1 c2 $end +$var wire 1 i1 c1 $end +$scope module a1 $end +$var wire 1 Z1 a $end +$var wire 1 \1 b $end +$var wire 1 i1 carryout $end +$var wire 1 g1 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 g1 a $end +$var wire 1 ^1 b $end +$var wire 1 h1 carryout $end +$var wire 1 f1 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 j1 in [7:0] $end +$var wire 8 k1 sel [7:0] $end +$var wire 1 d1 out $end +$var wire 8 l1 ands [7:0] $end +$scope module andP $end +$var wire 8 m1 A [7:0] $end +$var wire 8 n1 B [7:0] $end +$var wire 8 o1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 p1 in [7:0] $end +$var wire 1 d1 out $end +$var wire 2 q1 ors [1:0] $end +$scope module or_1 $end +$var wire 4 r1 in [3:0] $end +$var wire 1 s1 out $end +$var wire 2 t1 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 u1 in [3:0] $end +$var wire 1 v1 out $end +$var wire 2 w1 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 x1 in [7:0] $end +$var wire 8 y1 sel [7:0] $end +$var wire 1 b1 out $end +$var wire 8 z1 ands [7:0] $end +$scope module andP $end +$var wire 8 {1 A [7:0] $end +$var wire 8 |1 B [7:0] $end +$var wire 8 }1 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ~1 in [7:0] $end +$var wire 1 b1 out $end +$var wire 2 !2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 "2 in [3:0] $end +$var wire 1 #2 out $end +$var wire 2 $2 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 %2 in [3:0] $end +$var wire 1 &2 out $end +$var wire 2 '2 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 Z1 a $end +$var wire 1 [1 a_ $end +$var wire 1 \1 b $end +$var wire 1 ]1 b_ $end +$var wire 1 ^1 carryin $end +$var wire 1 (2 eq $end +$var wire 1 )2 lt $end +$var wire 1 *2 out $end +$var wire 1 +2 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 Z1 a $end +$var wire 1 ]1 b $end +$var wire 1 ^1 carryin $end +$var wire 1 ,2 carryout $end +$var wire 1 -2 sum $end +$var wire 1 .2 s1 $end +$var wire 1 /2 c2 $end +$var wire 1 02 c1 $end +$scope module a1 $end +$var wire 1 Z1 a $end +$var wire 1 ]1 b $end +$var wire 1 02 carryout $end +$var wire 1 .2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 .2 a $end +$var wire 1 ^1 b $end +$var wire 1 /2 carryout $end +$var wire 1 -2 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[30] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 12 A $end +$var wire 1 22 A_ $end +$var wire 1 32 B $end +$var wire 1 42 B_ $end +$var wire 1 52 carryin $end +$var wire 8 62 command [7:0] $end +$var wire 1 72 zero $end +$var wire 8 82 results [7:0] $end +$var wire 1 92 result $end +$var wire 8 :2 carryouts [7:0] $end +$var wire 1 ;2 carryout $end +$scope module adder $end +$var wire 1 12 a $end +$var wire 1 32 b $end +$var wire 1 52 carryin $end +$var wire 1 <2 carryout $end +$var wire 1 =2 sum $end +$var wire 1 >2 s1 $end +$var wire 1 ?2 c2 $end +$var wire 1 @2 c1 $end +$scope module a1 $end +$var wire 1 12 a $end +$var wire 1 32 b $end +$var wire 1 @2 carryout $end +$var wire 1 >2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 >2 a $end +$var wire 1 52 b $end +$var wire 1 ?2 carryout $end +$var wire 1 =2 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 A2 in [7:0] $end +$var wire 8 B2 sel [7:0] $end +$var wire 1 ;2 out $end +$var wire 8 C2 ands [7:0] $end +$scope module andP $end +$var wire 8 D2 A [7:0] $end +$var wire 8 E2 B [7:0] $end +$var wire 8 F2 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 G2 in [7:0] $end +$var wire 1 ;2 out $end +$var wire 2 H2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 I2 in [3:0] $end +$var wire 1 J2 out $end +$var wire 2 K2 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 L2 in [3:0] $end +$var wire 1 M2 out $end +$var wire 2 N2 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 O2 in [7:0] $end +$var wire 8 P2 sel [7:0] $end +$var wire 1 92 out $end +$var wire 8 Q2 ands [7:0] $end +$scope module andP $end +$var wire 8 R2 A [7:0] $end +$var wire 8 S2 B [7:0] $end +$var wire 8 T2 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 U2 in [7:0] $end +$var wire 1 92 out $end +$var wire 2 V2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 W2 in [3:0] $end +$var wire 1 X2 out $end +$var wire 2 Y2 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 Z2 in [3:0] $end +$var wire 1 [2 out $end +$var wire 2 \2 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 12 a $end +$var wire 1 22 a_ $end +$var wire 1 32 b $end +$var wire 1 42 b_ $end +$var wire 1 52 carryin $end +$var wire 1 ]2 eq $end +$var wire 1 ^2 lt $end +$var wire 1 _2 out $end +$var wire 1 `2 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 12 a $end +$var wire 1 42 b $end +$var wire 1 52 carryin $end +$var wire 1 a2 carryout $end +$var wire 1 b2 sum $end +$var wire 1 c2 s1 $end +$var wire 1 d2 c2 $end +$var wire 1 e2 c1 $end +$scope module a1 $end +$var wire 1 12 a $end +$var wire 1 42 b $end +$var wire 1 e2 carryout $end +$var wire 1 c2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 c2 a $end +$var wire 1 52 b $end +$var wire 1 d2 carryout $end +$var wire 1 b2 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope begin alu_slices[31] $end +$scope begin genblk2 $end +$upscope $end +$scope module alu1_inst $end +$var wire 1 f2 A $end +$var wire 1 g2 A_ $end +$var wire 1 h2 B $end +$var wire 1 i2 B_ $end +$var wire 1 j2 carryin $end +$var wire 8 k2 command [7:0] $end +$var wire 1 l2 zero $end +$var wire 8 m2 results [7:0] $end +$var wire 1 n2 result $end +$var wire 8 o2 carryouts [7:0] $end +$var wire 1 p2 carryout $end +$scope module adder $end +$var wire 1 f2 a $end +$var wire 1 h2 b $end +$var wire 1 j2 carryin $end +$var wire 1 q2 carryout $end +$var wire 1 r2 sum $end +$var wire 1 s2 s1 $end +$var wire 1 t2 c2 $end +$var wire 1 u2 c1 $end +$scope module a1 $end +$var wire 1 f2 a $end +$var wire 1 h2 b $end +$var wire 1 u2 carryout $end +$var wire 1 s2 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 s2 a $end +$var wire 1 j2 b $end +$var wire 1 t2 carryout $end +$var wire 1 r2 sum $end +$upscope $end +$upscope $end +$scope module cMux $end +$var wire 8 v2 in [7:0] $end +$var wire 8 w2 sel [7:0] $end +$var wire 1 p2 out $end +$var wire 8 x2 ands [7:0] $end +$scope module andP $end +$var wire 8 y2 A [7:0] $end +$var wire 8 z2 B [7:0] $end +$var wire 8 {2 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 |2 in [7:0] $end +$var wire 1 p2 out $end +$var wire 2 }2 ors [1:0] $end +$scope module or_1 $end +$var wire 4 ~2 in [3:0] $end +$var wire 1 !3 out $end +$var wire 2 "3 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 #3 in [3:0] $end +$var wire 1 $3 out $end +$var wire 2 %3 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module resMux $end +$var wire 8 &3 in [7:0] $end +$var wire 8 '3 sel [7:0] $end +$var wire 1 n2 out $end +$var wire 8 (3 ands [7:0] $end +$scope module andP $end +$var wire 8 )3 A [7:0] $end +$var wire 8 *3 B [7:0] $end +$var wire 8 +3 out [7:0] $end +$scope begin and_slces[0] $end +$upscope $end +$scope begin and_slces[1] $end +$upscope $end +$scope begin and_slces[2] $end +$upscope $end +$scope begin and_slces[3] $end +$upscope $end +$scope begin and_slces[4] $end +$upscope $end +$scope begin and_slces[5] $end +$upscope $end +$scope begin and_slces[6] $end +$upscope $end +$scope begin and_slces[7] $end +$upscope $end +$upscope $end +$scope module ors $end +$var wire 8 ,3 in [7:0] $end +$var wire 1 n2 out $end +$var wire 2 -3 ors [1:0] $end +$scope module or_1 $end +$var wire 4 .3 in [3:0] $end +$var wire 1 /3 out $end +$var wire 2 03 ors [1:0] $end +$upscope $end +$scope module or_2 $end +$var wire 4 13 in [3:0] $end +$var wire 1 23 out $end +$var wire 2 33 ors [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module sltGate $end +$var wire 1 f2 a $end +$var wire 1 g2 a_ $end +$var wire 1 h2 b $end +$var wire 1 i2 b_ $end +$var wire 1 j2 carryin $end +$var wire 1 43 eq $end +$var wire 1 53 lt $end +$var wire 1 63 out $end +$var wire 1 73 w0 $end +$upscope $end +$scope module sub $end +$var wire 1 f2 a $end +$var wire 1 i2 b $end +$var wire 1 j2 carryin $end +$var wire 1 83 carryout $end +$var wire 1 93 sum $end +$var wire 1 :3 s1 $end +$var wire 1 ;3 c2 $end +$var wire 1 <3 c1 $end +$scope module a1 $end +$var wire 1 f2 a $end +$var wire 1 i2 b $end +$var wire 1 <3 carryout $end +$var wire 1 :3 sum $end +$upscope $end +$scope module a2 $end +$var wire 1 :3 a $end +$var wire 1 j2 b $end +$var wire 1 ;3 carryout $end +$var wire 1 93 sum $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module overflowMux $end +$var wire 1 + a $end +$var wire 1 0 b $end +$var wire 1 6 out $end +$var wire 1 =3 s $end +$var wire 1 >3 s_ $end +$var wire 1 ?3 w0 $end +$var wire 1 @3 w1 $end +$upscope $end +$scope module resultOr $end +$var wire 32 A3 A [31:0] $end +$var wire 32 B3 B [31:0] $end +$var wire 32 C3 out [31:0] $end +$scope begin or_slces[0] $end +$upscope $end +$scope begin or_slces[1] $end +$upscope $end +$scope begin or_slces[2] $end +$upscope $end +$scope begin or_slces[3] $end +$upscope $end +$scope begin or_slces[4] $end +$upscope $end +$scope begin or_slces[5] $end +$upscope $end +$scope begin or_slces[6] $end +$upscope $end +$scope begin or_slces[7] $end +$upscope $end +$scope begin or_slces[8] $end +$upscope $end +$scope begin or_slces[9] $end +$upscope $end +$scope begin or_slces[10] $end +$upscope $end +$scope begin or_slces[11] $end +$upscope $end +$scope begin or_slces[12] $end +$upscope $end +$scope begin or_slces[13] $end +$upscope $end +$scope begin or_slces[14] $end +$upscope $end +$scope begin or_slces[15] $end +$upscope $end +$scope begin or_slces[16] $end +$upscope $end +$scope begin or_slces[17] $end +$upscope $end +$scope begin or_slces[18] $end +$upscope $end +$scope begin or_slces[19] $end +$upscope $end +$scope begin or_slces[20] $end +$upscope $end +$scope begin or_slces[21] $end +$upscope $end +$scope begin or_slces[22] $end +$upscope $end +$scope begin or_slces[23] $end +$upscope $end +$scope begin or_slces[24] $end +$upscope $end +$scope begin or_slces[25] $end +$upscope $end +$scope begin or_slces[26] $end +$upscope $end +$scope begin or_slces[27] $end +$upscope $end +$scope begin or_slces[28] $end +$upscope $end +$scope begin or_slces[29] $end +$upscope $end +$scope begin or_slces[30] $end +$upscope $end +$scope begin or_slces[31] $end +$upscope $end +$upscope $end +$scope module zeroout $end +$var wire 32 D3 in [31:0] $end +$var wire 1 ! out $end +$var wire 2 E3 ands [1:0] $end +$scope module and_1 $end +$var wire 16 F3 in [15:0] $end +$var wire 1 G3 out $end +$var wire 2 H3 ands [1:0] $end +$scope module and_1 $end +$var wire 8 I3 in [7:0] $end +$var wire 1 J3 out $end +$var wire 2 K3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 L3 in [3:0] $end +$var wire 1 M3 out $end +$var wire 2 N3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 O3 in [3:0] $end +$var wire 1 P3 out $end +$var wire 2 Q3 ands [1:0] $end +$upscope $end +$upscope $end +$scope module and_2 $end +$var wire 8 R3 in [7:0] $end +$var wire 1 S3 out $end +$var wire 2 T3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 U3 in [3:0] $end +$var wire 1 V3 out $end +$var wire 2 W3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 X3 in [3:0] $end +$var wire 1 Y3 out $end +$var wire 2 Z3 ands [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module and_2 $end +$var wire 16 [3 in [15:0] $end +$var wire 1 \3 out $end +$var wire 2 ]3 ands [1:0] $end +$scope module and_1 $end +$var wire 8 ^3 in [7:0] $end +$var wire 1 _3 out $end +$var wire 2 `3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 a3 in [3:0] $end +$var wire 1 b3 out $end +$var wire 2 c3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 d3 in [3:0] $end +$var wire 1 e3 out $end +$var wire 2 f3 ands [1:0] $end +$upscope $end +$upscope $end +$scope module and_2 $end +$var wire 8 g3 in [7:0] $end +$var wire 1 h3 out $end +$var wire 2 i3 ands [1:0] $end +$scope module and_1 $end +$var wire 4 j3 in [3:0] $end +$var wire 1 k3 out $end +$var wire 2 l3 ands [1:0] $end +$upscope $end +$scope module and_2 $end +$var wire 4 m3 in [3:0] $end +$var wire 1 n3 out $end +$var wire 2 o3 ands [1:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +bx o3 +xn3 +bx m3 +bx l3 +xk3 +bx j3 +bx i3 +xh3 +bx g3 +bx f3 +xe3 +bx d3 +bx c3 +xb3 +bx a3 +bx `3 +x_3 +bx ^3 +bx ]3 +x\3 +bx [3 +bx Z3 +xY3 +bx X3 +bx W3 +xV3 +bx U3 +bx T3 +xS3 +bx R3 +bx Q3 +xP3 +bx O3 +bx N3 +xM3 +bx L3 +bx K3 +xJ3 +bx I3 +bx H3 +xG3 +bx F3 +bx E3 +bx D3 +bx C3 +bx B3 +bx A3 +x@3 +x?3 +x>3 +1=3 +x<3 +x;3 +x:3 +x93 +x83 +x73 +x63 +x53 +x43 +bx 33 +x23 +bx 13 +bx 03 +x/3 +bx .3 +bx -3 +bx ,3 +bx +3 +b1 *3 +bx )3 +bx (3 +b1 '3 +bx &3 +bx %3 +x$3 +bx #3 +bx "3 +x!3 +bx ~2 +bx }2 +bx |2 +bx {2 +b1 z2 +bx y2 +bx x2 +b1 w2 +bx v2 +xu2 +xt2 +xs2 +xr2 +xq2 +xp2 +bx o2 +xn2 +bx m2 +xl2 +b1 k2 +xj2 +xi2 +0h2 +xg2 +1f2 +xe2 +xd2 +xc2 +xb2 +xa2 +x`2 +x_2 +x^2 +x]2 +bx \2 +x[2 +bx Z2 +bx Y2 +xX2 +bx W2 +bx V2 +bx U2 +bx T2 +b1 S2 +bx R2 +bx Q2 +b1 P2 +bx O2 +bx N2 +xM2 +bx L2 +bx K2 +xJ2 +bx I2 +bx H2 +bx G2 +bx F2 +b1 E2 +bx D2 +bx C2 +b1 B2 +bx A2 +x@2 +x?2 +x>2 +x=2 +x<2 +x;2 +bx :2 +x92 +bx 82 +x72 +b1 62 +x52 +x42 +032 +x22 +112 +x02 +x/2 +x.2 +x-2 +x,2 +x+2 +x*2 +x)2 +x(2 +bx '2 +x&2 +bx %2 +bx $2 +x#2 +bx "2 +bx !2 +bx ~1 +bx }1 +b1 |1 +bx {1 +bx z1 +b1 y1 +bx x1 +bx w1 +xv1 +bx u1 +bx t1 +xs1 +bx r1 +bx q1 +bx p1 +bx o1 +b1 n1 +bx m1 +bx l1 +b1 k1 +bx j1 +xi1 +xh1 +xg1 +xf1 +xe1 +xd1 +bx c1 +xb1 +bx a1 +x`1 +b1 _1 +x^1 +x]1 +0\1 +x[1 +1Z1 +xY1 +xX1 +xW1 +xV1 +xU1 +xT1 +xS1 +xR1 +xQ1 +bx P1 +xO1 +bx N1 +bx M1 +xL1 +bx K1 +bx J1 +bx I1 +bx H1 +b1 G1 +bx F1 +bx E1 +b1 D1 +bx C1 +bx B1 +xA1 +bx @1 +bx ?1 +x>1 +bx =1 +bx <1 +bx ;1 +bx :1 +b1 91 +bx 81 +bx 71 +b1 61 +bx 51 +x41 +x31 +x21 +x11 +x01 +x/1 +bx .1 +x-1 +bx ,1 +x+1 +b1 *1 +x)1 +x(1 +0'1 +x&1 +1%1 +x$1 +x#1 +x"1 +x!1 +x~0 +x}0 +x|0 +x{0 +xz0 +bx y0 +xx0 +bx w0 +bx v0 +xu0 +bx t0 +bx s0 +bx r0 +bx q0 +b1 p0 +bx o0 +bx n0 +b1 m0 +bx l0 +bx k0 +xj0 +bx i0 +bx h0 +xg0 +bx f0 +bx e0 +bx d0 +bx c0 +b1 b0 +bx a0 +bx `0 +b1 _0 +bx ^0 +x]0 +x\0 +x[0 +xZ0 +xY0 +xX0 +bx W0 +xV0 +bx U0 +xT0 +b1 S0 +xR0 +xQ0 +0P0 +xO0 +1N0 +xM0 +xL0 +xK0 +xJ0 +xI0 +xH0 +xG0 +xF0 +xE0 +bx D0 +xC0 +bx B0 +bx A0 +x@0 +bx ?0 +bx >0 +bx =0 +bx <0 +b1 ;0 +bx :0 +bx 90 +b1 80 +bx 70 +bx 60 +x50 +bx 40 +bx 30 +x20 +bx 10 +bx 00 +bx /0 +bx .0 +b1 -0 +bx ,0 +bx +0 +b1 *0 +bx )0 +x(0 +x'0 +x&0 +x%0 +x$0 +x#0 +bx "0 +x!0 +bx ~/ +x}/ +b1 |/ +x{/ +xz/ +0y/ +xx/ +1w/ +xv/ +xu/ +xt/ +xs/ +xr/ +xq/ +xp/ +xo/ +xn/ +bx m/ +xl/ +bx k/ +bx j/ +xi/ +bx h/ +bx g/ +bx f/ +bx e/ +b1 d/ +bx c/ +bx b/ +b1 a/ +bx `/ +bx _/ +x^/ +bx ]/ +bx \/ +x[/ +bx Z/ +bx Y/ +bx X/ +bx W/ +b1 V/ +bx U/ +bx T/ +b1 S/ +bx R/ +xQ/ +xP/ +xO/ +xN/ +xM/ +xL/ +bx K/ +xJ/ +bx I/ +xH/ +b1 G/ +xF/ +xE/ +0D/ +xC/ +1B/ +xA/ +x@/ +x?/ +x>/ +x=/ +x. +bx =. +x<. +b1 ;. +x:. +x9. +08. +x7. +16. +x5. +x4. +x3. +x2. +x1. +x0. +x/. +x.. +x-. +bx ,. +x+. +bx *. +bx ). +x(. +bx '. +bx &. +bx %. +bx $. +b1 #. +bx ". +bx !. +b1 ~- +bx }- +bx |- +x{- +bx z- +bx y- +xx- +bx w- +bx v- +bx u- +bx t- +b1 s- +bx r- +bx q- +b1 p- +bx o- +xn- +xm- +xl- +xk- +xj- +xi- +bx h- +xg- +bx f- +xe- +b1 d- +xc- +xb- +0a- +x`- +1_- +x^- +x]- +x\- +x[- +xZ- +xY- +xX- +xW- +xV- +bx U- +xT- +bx S- +bx R- +xQ- +bx P- +bx O- +bx N- +bx M- +b1 L- +bx K- +bx J- +b1 I- +bx H- +bx G- +xF- +bx E- +bx D- +xC- +bx B- +bx A- +bx @- +bx ?- +b1 >- +bx =- +bx <- +b1 ;- +bx :- +x9- +x8- +x7- +x6- +x5- +x4- +bx 3- +x2- +bx 1- +x0- +b1 /- +x.- +x-- +0,- +x+- +1*- +x)- +x(- +x'- +x&- +x%- +x$- +x#- +x"- +x!- +bx ~, +x}, +bx |, +bx {, +xz, +bx y, +bx x, +bx w, +bx v, +b1 u, +bx t, +bx s, +b1 r, +bx q, +bx p, +xo, +bx n, +bx m, +xl, +bx k, +bx j, +bx i, +bx h, +b1 g, +bx f, +bx e, +b1 d, +bx c, +xb, +xa, +x`, +x_, +x^, +x], +bx \, +x[, +bx Z, +xY, +b1 X, +xW, +xV, +0U, +xT, +1S, +xR, +xQ, +xP, +xO, +xN, +xM, +xL, +xK, +xJ, +bx I, +xH, +bx G, +bx F, +xE, +bx D, +bx C, +bx B, +bx A, +b1 @, +bx ?, +bx >, +b1 =, +bx <, +bx ;, +x:, +bx 9, +bx 8, +x7, +bx 6, +bx 5, +bx 4, +bx 3, +b1 2, +bx 1, +bx 0, +b1 /, +bx ., +x-, +x,, +x+, +x*, +x), +x(, +bx ', +x&, +bx %, +x$, +b1 #, +x", +x!, +0~+ +x}+ +1|+ +x{+ +xz+ +xy+ +xx+ +xw+ +xv+ +xu+ +xt+ +xs+ +bx r+ +xq+ +bx p+ +bx o+ +xn+ +bx m+ +bx l+ +bx k+ +bx j+ +b1 i+ +bx h+ +bx g+ +b1 f+ +bx e+ +bx d+ +xc+ +bx b+ +bx a+ +x`+ +bx _+ +bx ^+ +bx ]+ +bx \+ +b1 [+ +bx Z+ +bx Y+ +b1 X+ +bx W+ +xV+ +xU+ +xT+ +xS+ +xR+ +xQ+ +bx P+ +xO+ +bx N+ +xM+ +b1 L+ +xK+ +xJ+ +0I+ +xH+ +1G+ +xF+ +xE+ +xD+ +xC+ +xB+ +xA+ +x@+ +x?+ +x>+ +bx =+ +x<+ +bx ;+ +bx :+ +x9+ +bx 8+ +bx 7+ +bx 6+ +bx 5+ +b1 4+ +bx 3+ +bx 2+ +b1 1+ +bx 0+ +bx /+ +x.+ +bx -+ +bx ,+ +x++ +bx *+ +bx )+ +bx (+ +bx '+ +b1 &+ +bx %+ +bx $+ +b1 #+ +bx "+ +x!+ +x~* +x}* +x|* +x{* +xz* +bx y* +xx* +bx w* +xv* +b1 u* +xt* +xs* +0r* +xq* +1p* +xo* +xn* +xm* +xl* +xk* +xj* +xi* +xh* +xg* +bx f* +xe* +bx d* +bx c* +xb* +bx a* +bx `* +bx _* +bx ^* +b1 ]* +bx \* +bx [* +b1 Z* +bx Y* +bx X* +xW* +bx V* +bx U* +xT* +bx S* +bx R* +bx Q* +bx P* +b1 O* +bx N* +bx M* +b1 L* +bx K* +xJ* +xI* +xH* +xG* +xF* +xE* +bx D* +xC* +bx B* +xA* +b1 @* +x?* +x>* +0=* +x<* +1;* +x:* +x9* +x8* +x7* +x6* +x5* +x4* +x3* +x2* +bx 1* +x0* +bx /* +bx .* +x-* +bx ,* +bx +* +bx ** +bx )* +b1 (* +bx '* +bx &* +b1 %* +bx $* +bx #* +x"* +bx !* +bx ~) +x}) +bx |) +bx {) +bx z) +bx y) +b1 x) +bx w) +bx v) +b1 u) +bx t) +xs) +xr) +xq) +xp) +xo) +xn) +bx m) +xl) +bx k) +xj) +b1 i) +xh) +xg) +0f) +xe) +1d) +xc) +xb) +xa) +x`) +x_) +x^) +x]) +x\) +x[) +bx Z) +xY) +bx X) +bx W) +xV) +bx U) +bx T) +bx S) +bx R) +b1 Q) +bx P) +bx O) +b1 N) +bx M) +bx L) +xK) +bx J) +bx I) +xH) +bx G) +bx F) +bx E) +bx D) +b1 C) +bx B) +bx A) +b1 @) +bx ?) +x>) +x=) +x<) +x;) +x:) +x9) +bx 8) +x7) +bx 6) +x5) +b1 4) +x3) +x2) +01) +x0) +1/) +x.) +x-) +x,) +x+) +x*) +x)) +x() +x') +x&) +bx %) +x$) +bx #) +bx ") +x!) +bx ~( +bx }( +bx |( +bx {( +b1 z( +bx y( +bx x( +b1 w( +bx v( +bx u( +xt( +bx s( +bx r( +xq( +bx p( +bx o( +bx n( +bx m( +b1 l( +bx k( +bx j( +b1 i( +bx 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,/ +b1000000 // +b1000000 G/ +b1000000 S/ +b1000000 V/ +b1000000 a/ +b1000000 d/ +b1000000 |/ +b1000000 *0 +b1000000 -0 +b1000000 80 +b1000000 ;0 +b1000000 S0 +b1000000 _0 +b1000000 b0 +b1000000 m0 +b1000000 p0 +b1000000 *1 +b1000000 61 +b1000000 91 +b1000000 D1 +b1000000 G1 +b1000000 _1 +b1000000 k1 +b1000000 n1 +b1000000 y1 +b1000000 |1 +b1000000 62 +b1000000 B2 +b1000000 E2 +b1000000 P2 +b1000000 S2 +b1000000 k2 +b1000000 w2 +b1000000 z2 +b1000000 '3 +b1000000 *3 +b1010 & +b1010 - +b1001 % +b1001 , +b110 ' +b110 * +#14000010000 +1< +1H" +0: +0{" +#14000020000 +b11100101 L" +b11100101 c" +b11100101 f" +1q" +b10000101 ## +b10000101 :# +b10000101 =# +1H# +#14000030000 +b0 b +b0 9" +b0 n" +b0 E# +b100 z# +b100 Q$ +b100 (% +b100 ]% +b100 4& +b100 i& +b100 @' +b100 u' +b100 L( +b100 #) +b100 X) +b100 /* +b100 d* +b100 ;+ +b100 p+ +b100 G, +b100 |, +b100 S- +b100 *. +b100 _. +b100 6/ +b100 k/ +b100 B0 +b100 w0 +b100 N1 +b100 %2 +b100 Z2 +b100 13 +b0 Y +b0 \ +b0 ] +b0 0" +b0 3" +b0 4" +b0 e" +b0 h" +b0 i" +b0 <# +b0 ?# +b0 @# +b1000000 q# +b1000000 t# +b1000000 u# +b1000000 H$ +b1000000 K$ +b1000000 L$ +b1000000 }$ +b1000000 "% +b1000000 #% +b1000000 T% +b1000000 W% +b1000000 X% +b1000000 +& +b1000000 .& +b1000000 /& +b1000000 `& +b1000000 c& +b1000000 d& +b1000000 7' +b1000000 :' +b1000000 ;' +b1000000 l' +b1000000 o' +b1000000 p' +b1000000 C( +b1000000 F( +b1000000 G( +b1000000 x( +b1000000 {( +b1000000 |( +b1000000 O) +b1000000 R) +b1000000 S) +b1000000 &* +b1000000 )* +b1000000 ** +b1000000 [* +b1000000 ^* +b1000000 _* +b1000000 2+ +b1000000 5+ +b1000000 6+ +b1000000 g+ +b1000000 j+ +b1000000 k+ +b1000000 >, +b1000000 A, +b1000000 B, +b1000000 s, +b1000000 v, +b1000000 w, +b1000000 J- +b1000000 M- +b1000000 N- +b1000000 !. +b1000000 $. +b1000000 %. +b1000000 V. +b1000000 Y. +b1000000 Z. +b1000000 -/ +b1000000 0/ +b1000000 1/ +b1000000 b/ +b1000000 e/ +b1000000 f/ +b1000000 90 +b1000000 <0 +b1000000 =0 +b1000000 n0 +b1000000 q0 +b1000000 r0 +b1000000 E1 +b1000000 H1 +b1000000 I1 +b1000000 z1 +b1000000 }1 +b1000000 ~1 +b1000000 Q2 +b1000000 T2 +b1000000 U2 +b1000000 (3 +b1000000 +3 +b1000000 ,3 +b1100001 L" +b1100001 c" +b1100001 f" +0R" +b10010001 ## +b10010001 :# +b10010001 =# +0)# +1+# +1N# +#14000040000 +1f +1m +1w" +#14000050000 +b100 n" +b1000000 e" +b1000000 h" +b1000000 i" +#14000060000 +b0 d +b0 ;" +b0 p" +b0 G# +b10 |# +b10 S$ +b10 *% +b10 _% +b10 6& +b10 k& +b10 B' +b10 w' +b10 N( +b10 %) +b10 Z) +b10 1* +b10 f* +b10 =+ +b10 r+ +b10 I, +b10 ~, +b10 U- +b10 ,. +b10 a. +b10 8/ +b10 m/ +b10 D0 +b10 y0 +b10 P1 +b10 '2 +b10 \2 +b10 33 +b1100000 L" +b1100000 c" +b1100000 f" +0Q" +0(# +b1 %# +b1 ,# +b1 /# +1'# +b10010010 ## +b10010010 :# +b10010010 =# +1M# +#14000070000 +1g +b1010 B +b1010 I +b1010 L +1i +b1100010 L" +b1100010 c" +b1100010 f" +1v" +#14000080000 +b10 p" +#14000090000 +b0 ^ +0c +b0 5" +0:" +b0 A# +0F# +#14000120000 +0A +0v +b11111111111111111111111111110100 3 +b11111111111111111111111111110100 A3 +0$# +#14000130000 +b1011 L3 +b1011 I3 +b1011 F3 +1? +1t +b1011 2 +b1011 D3 +1"# +#14000150000 +b11111111111111111111111111110100 " +b11111111111111111111111111110100 4 +b11111111111111111111111111110100 C3 +#14000160000 +b1 N3 +#15000000000 +1; +1G" +09 +0z" +b1111 & +b1111 - +b0 % +b0 , +#15000010000 +0< +0H" +1: +1{" +#15000020000 +b100010 L" +b100010 c" +b100010 f" +0q" +b10110010 ## +b10110010 :# +b10110010 =# +0H# +#15000030000 +b10100110 L" +b10100110 c" +b10100110 f" +1R" +0f +0m +b10100110 ## +b10100110 :# +b10100110 =# +1)# +0+# +0N# +#15000040000 +0w" +#15000050000 +b0 n" +b0 e" +b0 h" +b0 i" +#15000060000 +b10100111 L" +b10100111 c" +b10100111 f" +1Q" +0g +b0 B +b0 I +b0 L +0i +1(# +b0 %# +b0 ,# +b0 /# +0'# +b10100101 ## +b10100101 :# +b10100101 =# +0M# +#15000070000 +b10100101 L" +b10100101 c" +b10100101 f" +0v" +#15000080000 +b0 p" +#15000110000 +b0 j" +0o" +#15000140000 +b11111111111111111111111111110000 3 +b11111111111111111111111111110000 A3 +0M" +#15000150000 +b1111 L3 +b1111 I3 +b1111 F3 +b1111 2 +b1111 D3 +1K" +#15000170000 +b11111111111111111111111111110000 " +b11111111111111111111111111110000 4 +b11111111111111111111111111110000 C3 +#15000180000 +b11 N3 +#15000210000 +b1 K3 +1M3 +#16000000000 +0; +0G" +19 +1z" +b10000000 8 +b10000000 > +b10000000 J +b10000000 M +b10000000 X +b10000000 [ +b10000000 s +b10000000 !" +b10000000 $" +b10000000 /" +b10000000 2" +b10000000 J" +b10000000 V" +b10000000 Y" +b10000000 d" +b10000000 g" +b10000000 !# +b10000000 -# +b10000000 0# +b10000000 ;# +b10000000 ># +b10000000 V# +b10000000 b# +b10000000 e# +b10000000 p# +b10000000 s# +b10000000 -$ +b10000000 9$ +b10000000 <$ +b10000000 G$ +b10000000 J$ +b10000000 b$ +b10000000 n$ +b10000000 q$ +b10000000 |$ +b10000000 !% +b10000000 9% +b10000000 E% +b10000000 H% +b10000000 S% +b10000000 V% +b10000000 n% +b10000000 z% +b10000000 }% +b10000000 *& +b10000000 -& +b10000000 E& +b10000000 Q& +b10000000 T& +b10000000 _& +b10000000 b& +b10000000 z& +b10000000 (' +b10000000 +' +b10000000 6' +b10000000 9' +b10000000 Q' +b10000000 ]' +b10000000 `' +b10000000 k' +b10000000 n' +b10000000 (( +b10000000 4( +b10000000 7( +b10000000 B( +b10000000 E( +b10000000 ]( +b10000000 i( +b10000000 l( +b10000000 w( +b10000000 z( +b10000000 4) +b10000000 @) +b10000000 C) +b10000000 N) +b10000000 Q) +b10000000 i) +b10000000 u) +b10000000 x) +b10000000 %* +b10000000 (* +b10000000 @* +b10000000 L* +b10000000 O* +b10000000 Z* +b10000000 ]* +b10000000 u* +b10000000 #+ +b10000000 &+ +b10000000 1+ +b10000000 4+ +b10000000 L+ +b10000000 X+ +b10000000 [+ +b10000000 f+ +b10000000 i+ +b10000000 #, +b10000000 /, +b10000000 2, +b10000000 =, +b10000000 @, +b10000000 X, +b10000000 d, +b10000000 g, +b10000000 r, +b10000000 u, +b10000000 /- +b10000000 ;- +b10000000 >- +b10000000 I- +b10000000 L- +b10000000 d- +b10000000 p- +b10000000 s- +b10000000 ~- +b10000000 #. +b10000000 ;. +b10000000 G. +b10000000 J. +b10000000 U. +b10000000 X. +b10000000 p. +b10000000 |. +b10000000 !/ +b10000000 ,/ +b10000000 // +b10000000 G/ +b10000000 S/ +b10000000 V/ +b10000000 a/ +b10000000 d/ +b10000000 |/ +b10000000 *0 +b10000000 -0 +b10000000 80 +b10000000 ;0 +b10000000 S0 +b10000000 _0 +b10000000 b0 +b10000000 m0 +b10000000 p0 +b10000000 *1 +b10000000 61 +b10000000 91 +b10000000 D1 +b10000000 G1 +b10000000 _1 +b10000000 k1 +b10000000 n1 +b10000000 y1 +b10000000 |1 +b10000000 62 +b10000000 B2 +b10000000 E2 +b10000000 P2 +b10000000 S2 +b10000000 k2 +b10000000 w2 +b10000000 z2 +b10000000 '3 +b10000000 *3 +b1010 & +b1010 - +b1001 % +b1001 , +b111 ' +b111 * +#16000010000 +1< +1H" +0: +0{" +#16000020000 +b11100101 L" +b11100101 c" +b11100101 f" +1q" +b10000101 ## +b10000101 :# +b10000101 =# +1H# +#16000030000 +b1000 b +b1000 9" +b1000 n" +b1000 E# +b0 z# +b0 Q$ +b0 (% +b0 ]% +b0 4& +b0 i& +b0 @' +b0 u' +b0 L( +b0 #) +b0 X) +b0 /* +b0 d* +b0 ;+ +b0 p+ +b0 G, +b0 |, +b0 S- +b0 *. +b0 _. +b0 6/ +b0 k/ +b0 B0 +b0 w0 +b0 N1 +b0 %2 +b0 Z2 +b0 13 +b10000000 Y +b10000000 \ +b10000000 ] +b10000000 0" +b10000000 3" +b10000000 4" +b10000000 e" +b10000000 h" +b10000000 i" +b10000000 <# +b10000000 ?# +b10000000 @# +b0 q# +b0 t# +b0 u# +b0 H$ +b0 K$ +b0 L$ +b0 }$ +b0 "% +b0 #% +b0 T% +b0 W% +b0 X% +b0 +& +b0 .& +b0 /& +b0 `& +b0 c& +b0 d& +b0 7' +b0 :' +b0 ;' +b0 l' +b0 o' +b0 p' +b0 C( +b0 F( +b0 G( +b0 x( +b0 {( +b0 |( +b0 O) +b0 R) +b0 S) +b0 &* +b0 )* +b0 ** +b0 [* +b0 ^* +b0 _* +b0 2+ +b0 5+ +b0 6+ +b0 g+ +b0 j+ +b0 k+ +b0 >, +b0 A, +b0 B, +b0 s, +b0 v, +b0 w, +b0 J- +b0 M- +b0 N- +b0 !. +b0 $. +b0 %. +b0 V. +b0 Y. +b0 Z. +b0 -/ +b0 0/ +b0 1/ +b0 b/ +b0 e/ +b0 f/ +b0 90 +b0 <0 +b0 =0 +b0 n0 +b0 q0 +b0 r0 +b0 E1 +b0 H1 +b0 I1 +b0 z1 +b0 }1 +b0 ~1 +b0 Q2 +b0 T2 +b0 U2 +b0 (3 +b0 +3 +b0 ,3 +b1100001 L" +b1100001 c" +b1100001 f" +0R" +b10010001 ## +b10010001 :# +b10010001 =# +0)# +1+# +1N# +#16000040000 +1f +1m +1w" +#16000060000 +b0 n" +b10 d +b10 ;" +b10 p" +b10 G# +b0 |# +b0 S$ +b0 *% +b0 _% +b0 6& +b0 k& +b0 B' +b0 w' +b0 N( +b0 %) +b0 Z) +b0 1* +b0 f* +b0 =+ +b0 r+ +b0 I, +b0 ~, +b0 U- +b0 ,. +b0 a. +b0 8/ +b0 m/ +b0 D0 +b0 y0 +b0 P1 +b0 '2 +b0 \2 +b0 33 +b0 e" +b0 h" +b0 i" +b1100000 L" +b1100000 c" +b1100000 f" +0Q" +0(# +b1 %# +b1 ,# +b1 /# +1'# +b10010010 ## +b10010010 :# +b10010010 =# +1M# +#16000070000 +1g +b1010 B +b1010 I +b1010 L +1i +b1100010 L" +b1100010 c" +b1100010 f" +1v" +#16000090000 +b0 p" +b10 ^ +1c +b10 5" +1:" +b10 j" +1o" +b10 A# +1F# +b0 v# +0{# +b0 M$ +0R$ +b0 $% +0)% +b0 Y% +0^% +b0 0& +05& +b0 e& +0j& +b0 <' +0A' +b0 q' +0v' +b0 H( +0M( +b0 }( +0$) +b0 T) +0Y) +b0 +* +00* +b0 `* +0e* +b0 7+ +0<+ +b0 l+ +0q+ +b0 C, +0H, +b0 x, +0}, +b0 O- +0T- +b0 &. +0+. +b0 [. +0`. +b0 2/ +07/ +b0 g/ +0l/ +b0 >0 +0C0 +b0 s0 +0x0 +b0 J1 +0O1 +b0 !2 +0&2 +b0 V2 +0[2 +b0 -3 +023 +#16000120000 +b0 j" +0o" +1A +1v +1M" +1$# +0Y# +00$ +0e$ +0<% +0q% +0H& +0}& +0T' +0+( +0`( +07) +0l) +0C* +0x* +0O+ +0&, +0[, +02- +0g- +0>. +0s. +0J/ +0!0 +0V0 +0-1 +0b1 +092 +b1111 3 +b1111 A3 +0n2 +#16000130000 +b0 L3 +b1111 O3 +b1111 U3 +b1111 X3 +b1111 a3 +b1111 d3 +b1111 j3 +b1111 m3 +b11110000 I3 +b11111111 R3 +b11111111 ^3 +b11111111 g3 +b1111111111110000 F3 +b1111111111111111 [3 +0? +0t +0K" +0"# +1W# +1.$ +1c$ +1:% +1o% +1F& +1{& +1R' +1)( +1^( +15) +1j) +1A* +1v* +1M+ +1$, +1Y, +10- +1e- +1<. +1q. +1H/ +1}/ +1T0 +1+1 +1`1 +172 +b11111111111111111111111111110000 2 +b11111111111111111111111111110000 D3 +1l2 +#16000150000 +b1011 3 +b1011 A3 +0M" +b1111 " +b1111 4 +b1111 C3 +#16000160000 +b100 L3 +b11110100 I3 +b1111111111110100 F3 +b11111111111111111111111111110100 2 +b11111111111111111111111111110100 D3 +1K" +b0 N3 +b11 Q3 +b11 W3 +b11 Z3 +b11 c3 +b11 f3 +b11 l3 +b11 o3 +#16000180000 +b1011 " +b1011 4 +b1011 C3 +0/ +#16000190000 +0M3 +b10 K3 +1P3 +1V3 +b11 T3 +1Y3 +1b3 +b11 `3 +1e3 +1k3 +b11 i3 +1n3 +#16000220000 +b10 H3 +1S3 +1_3 +b11 ]3 +1h3 +#16000250000 +b10 E3 +1\3 +#17000000000 +1; +1G" +09 +0z" +b1111 & +b1111 - +b0 % +b0 , +#17000010000 +0< +0H" +1: +1{" +#17000020000 +b100010 L" +b100010 c" +b100010 f" +0q" +b10110010 ## +b10110010 :# +b10110010 =# +0H# +#17000030000 +b10100110 L" +b10100110 c" +b10100110 f" +1R" +0f +0m +b10100110 ## +b10100110 :# +b10100110 =# +1)# +0+# +0N# +#17000040000 +0w" +#17000060000 +b1000 n" +b10000000 e" +b10000000 h" +b10000000 i" +b10100111 L" +b10100111 c" +b10100111 f" +1Q" +0g +b0 B +b0 I +b0 L +0i +1(# +b0 %# +b0 ,# +b0 /# +0'# +b10100101 ## +b10100101 :# +b10100101 =# +0M# +#17000070000 +b10100101 L" +b10100101 c" +b10100101 f" +0v" +#17000090000 +b10 p" +#17000120000 +b10 j" +1o" +#17000150000 +b1111 3 +b1111 A3 +1M" +#17000160000 +b0 L3 +b11110000 I3 +b1111111111110000 F3 +b11111111111111111111111111110000 2 +b11111111111111111111111111110000 D3 +0K" +#17000180000 +b1111 " +b1111 4 +b1111 C3 +#18000000000 diff --git a/alu1.v b/alu1.v index 0b15701..afab236 100644 --- a/alu1.v +++ b/alu1.v @@ -3,7 +3,7 @@ `define AND and #30 `define NOT not #10 `define XNOR xnor #20 -`define NOR xor #20 +`define NOR nor #20 `define NAND nand #20 module or4(output out, input[3:0] in); @@ -157,6 +157,7 @@ wire A_, B_; fullAdder adder(results[0], carryouts[0], A, B, carryin); fullAdder sub(results[1], carryouts[1], A, B_, carryin); `XOR xorGate(results[2], A, B); +`OR(carryouts[2], 0, 0); //slt is odd. Only the first bit is ever set, but it depends //on the lest bit. The actual result is handled later, //in the full ALU @@ -164,9 +165,13 @@ slt sltGate(carryouts[3], carryin, A, A_, B, B_); `OR falseGate(results[3], 0, 0); `AND andGate(results[4], A, B); +`OR(carryouts[4], 0, 0); `NAND nandGate(results[5], A, B); +`OR(carryouts[5], 0, 0); `NOR norGate(results[6], A, B); +`OR(carryouts[6], 0, 0); `OR orGate(results[7], A, B); +`OR(carryouts[7], 0, 0); unaryMultiplexor resMux(result, results, command); unaryMultiplexor cMux(carryout, carryouts, command); `NOT(zero, result); From b6c613375df4198b06c253063640222e2d7afd57 Mon Sep 17 00:00:00 2001 From: Tobias Shapinsky Date: Fri, 13 Oct 2017 02:01:45 -0400 Subject: [PATCH 22/26] added timing images --- AND.PNG | Bin 0 -> 12749 bytes NAND.PNG | Bin 0 -> 13148 bytes NOR.PNG | Bin 0 -> 13207 bytes OR.PNG | Bin 0 -> 12529 bytes SLT.PNG | Bin 0 -> 14449 bytes Subtraction.PNG | Bin 0 -> 17716 bytes XOR.PNG | Bin 0 -> 13518 bytes addition.PNG | Bin 0 -> 17548 bytes 8 files changed, 0 insertions(+), 0 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zlP#!|{quD92k-*3lxT(q^&synSHlf% zLw;t5SVNi^CA=174mBUUvGxmM$|wpesXERKlw({y-8mUMU!YwE({VHOs<2h% z<^YLp>b`Xvk0)aI_QtefWOK)hhbbb(r&et~A~GIwh`RrPjSAvt1#bG{@p*2J&28X; zVQzcy=XfV=%s1Gbl|j1iq-{=eC`B@foEwS4tf!Upg3p@q0Z{T0gGy$>yPYjPfKX{d z{nCYY>-7UTlm|>`k!Y~C?x&mKS;nMCm{hhJC1q*TtbZ_PL}j*`EbiV{-0HGHAHGKV zUa`>%{hk}}sy_AV|HidH_4yrSKG-k)t7re!(I01h6#G~A{)eOg-P?y6#^Yh_5!TX$ z1fi$Jv!CBiFNXpa-U%_A+Y{qfR{oN z(f#_fDaG;@UZJ+=uX)3C_x_{s^mk_HYxGs<_es)U|AdDROtu&JJNoNqqAL(}|J~4m zXl`=F|teg6-^AiHw_ literal 0 HcmV?d00001 From 5eb332d710fc9a256bd7fd0408829b2ecd1023e8 Mon Sep 17 00:00:00 2001 From: Henry Rachootin Date: Fri, 13 Oct 2017 02:07:28 -0400 Subject: [PATCH 23/26] slkdkhf --- Writeup.md | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Writeup.md b/Writeup.md index 175d8cf..2750c59 100644 --- a/Writeup.md +++ b/Writeup.md @@ -2,11 +2,19 @@ Going into this lab we knew the bigget decision to be made for the ALU would be whether to implement it through a bit slice method or individualy via several independent logic circuits through a decoder. In the end we decided to use a bit slice because it is much easier to define dynamically and in the end should result in a more compact design. ### Bit Slice +We broke up the alu into a bit sliced implementation. Basically we made a bunch of one bit ALUs and strung their carryouts to the next ALUs carryin. The bit slices accepted their opcodes in unary instead of binary, meaning that they had eight wires, one for each opcode, one of which would be high at a time. The meant we needed only one decoder, but we had to invent a unary multiplexer to output the result. + +Only three of the opcodes use carry functionality: add, sub, and slt. ### SLT +Our bit sliced SLT uses carryin and carryout to compare numbers without addition or subtraction. It's Basically a recursive compare algorithm. Ignoring sign for now, if the last bit of A is greater than the last bit of B, A is greater than B. If it is less, A is not greater than B. If they are equal, then you move on to the next bit, and compare them. By sending the result up the carry chain when the nth bit of A matches the nth bit of B, we get a bit by bit comparison of A and B, which doesn't even always need to wait for the carry to go all the way through. By passing a 0 to the first carry in, we get SLT. If we passed a 1 to the first carry in, we would have LTE. + +Finally, we just set the first bit of the result to the value of carryout. This is done outside of the bit slice. + +This implemenation is always wrong if the signs of the operands are different, so we just negate the output if that is the case. ### ALU -The first thing that the ALU does when it recieves information (op A, op B, command) is expand the command from a 3 bit binary bus to a 7 bit one-hot bus. This operation if not implemented in the top level of the ALU would be required in each ALU sliced bit individually, so in this case implementing it once for the top level gives a 32 fold gate reduction. +The first thing that the ALU does when it recieves information (op A, op B, command) is expand the command from a 3 bit binary bus to a 7 bit one-hot bus. This operation if not implemented in the top level of the ALU would be required in each ALU sliced bit individually, so in this case implementing it once for the top level gives a 32 fold gate reduction. #### Subtraction In the case of subtraction the LSB of the carryin bus is flipped to a 1 and each individual bit of the B operand is flipped by the 1 bit ALU slices which then do single bit addition, resulting in a subtraction action. @@ -15,10 +23,13 @@ In the case of subtraction the LSB of the carryin bus is flipped to a 1 and each In the case of addition each the LSB of the carryin bus is left empty and the carryout of each 1 bit ALU slice is connected to the carryin of the next bit, with the final connected to an AND gate to enable the carryout flag. ## Test Results +After some difficulties with post processing, we got our tests to pass. We weren't sure if carryout and zero were flags that should not be set for other operands beside ADD and SUB, so we didn't test that. + ### Test Choice +We chose tests that would cover edge cases for the difficult operands: overflow and underflow for subtraction and addition, and all the +/- permutations for SLT. We also chose some more standard tests for each operator. + ### Test Driven Development Catches Bugs -We waited until after writing the ALU to begin writing comprehensive test cases. After writing just two test cases we were able to find and fix two -### Discovered Tests +We waited until after writing the ALU to begin writing comprehensive test cases. After writing just two test cases we were able to find and fix two bugs in post-processing. We were incorrectly diagnosing overflow on subtraction, because the signs must not match for overflow to occur in subtraction. We also found a typo where we were XORin instead of ORing. ## Timing From 2bcfdc46380c0d257f402db4fb8b430e69db9e84 Mon Sep 17 00:00:00 2001 From: TShapinsky Date: Fri, 13 Oct 2017 02:14:03 -0400 Subject: [PATCH 24/26] added timing images --- Writeup.md | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Writeup.md b/Writeup.md index 2750c59..d054bfb 100644 --- a/Writeup.md +++ b/Writeup.md @@ -32,6 +32,21 @@ We chose tests that would cover edge cases for the difficult operands: overflow We waited until after writing the ALU to begin writing comprehensive test cases. After writing just two test cases we were able to find and fix two bugs in post-processing. We were incorrectly diagnosing overflow on subtraction, because the signs must not match for overflow to occur in subtraction. We also found a typo where we were XORin instead of ORing. ## Timing - +### Addition +![add](https://github.com/TShapinsky/Lab1/blob/master/addition.PNG?raw=true) +### Subtraction +![sub](https://github.com/TShapinsky/Lab1/blob/master/Subtraction.PNG?raw=true) +### XOR +![xor](https://github.com/TShapinsky/Lab1/blob/master/XOR.PNG?raw=true) +### SLT +![slt](https://github.com/TShapinsky/Lab1/blob/master/SLT.PNG?raw=true) +### AND +![and](https://github.com/TShapinsky/Lab1/blob/master/AND.PNG?raw=true) +### NAND +![nand](https://github.com/TShapinsky/Lab1/blob/master/NAND.PNG?raw=true) +### NOR +![nor](https://github.com/TShapinsky/Lab1/blob/master/NOR.PNG?raw=true) +### OR +![or](https://github.com/TShapinsky/Lab1/blob/master/OR.PNG?raw=true) ## Work Plan Reflection Writing the implementation happened fairly quickly in about the time we predicted, however the act of gathering information and creating visuals for the final write up turned out to be more time intensive than we had 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