diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..f47cb20
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*.out
diff --git a/README.md b/README.md
index 4384391..a09bdd0 100644
--- a/README.md
+++ b/README.md
@@ -1,165 +1,5 @@
 # CompArch Lab 1: Arithmetic Logic Unit
 
-**Work plan due:** Wed. October 4
+#### Jonah Spear and David Papp
 
-**Lab due:** Thu. October 12
-
-
-This lab assignment creates the first component of your processor: the ALU.  Additionally, it will help you understand the timing constraints of your designs.
-
-You will work in groups of 2-3. You may shuffle teams from the first lab if you so choose. 
-
-## Specification ##
-
-The ALU you will implement is a subset of the standard MIPS ALU. The number of operations supported has been reduced, but otherwise we are emulating that standard.
-
-<img src="https://e38023e2-a-62cb3a1a-s-sites.googlegroups.com/site/ca15fall/resources/alu.png" width="200" alt="ALU diagram">
-
-
-| Operation	| Result 		| Sets flags?	| ALU Control 	|
-|-----------|---------------|---------------|---------------|
-| ADD		| `R=A+B`		| Yes			| `b000`		|
-| SUB		| `R=A-B`		| Yes			| `b001`		|
-| XOR		| `R=A^B`		| No			| `b010`		|
-| SLT		| `R=(A<B)?1:0`	| No			| `b011`		|
-| AND		| `R=A&B`		| No			| `b100`		|
-| NAND		| `R=~(A&B)`	| No			| `b101`		|
-| NOR		| `R=~(A|B)`	| No			| `b110`		|
-| OR		| `R=A|B`		| No			| `b111`		|
-
-
-Each group will construct ALUs with identical behaviors, but the internal structures will vary based on the design decisions you each make.
-
-The ALU must be implemented in `alu.v`, and its top-level module must have the following definition:
-
-```verilog
-module ALU
-(
-output[31:0]  result,
-output        carryout,
-output        zero,
-output        overflow,
-input[31:0]   operandA,
-input[31:0]   operandB,
-input[2:0]    command
-);
-	// Your code here
-endmodule
-```
-
-## Work Plan ##
-
-Draft a work plan for this lab.  Break down the lab in to small portions, and for each portion predict how long it will take (in hours) and when it will be done by (date).  You will be comparing your predictions to reality later.
-
-**Submit this plan by Wednesday, October 4** by pushing `work_plan.txt` to GitHub.
-
-## Deliverables ##
-
-### Verilog ###
-Construct an ALU that implements the specification above.  We recommend that you use a "Bitslice + Control Logic LUT" approach to designing your ALU.
-
-You must use structural Verilog (basic gates and modules wired together) for your ALU, with the exception of the Control Logic LUT.  You may use behavioral Verilog to describe this Look Up Table (see the Notes section below for details).
-
-You may freely reuse code created for previous labs and homeworks.  **Be sure to redo the timing!**
-
-#### Gate Delays ####
-
-In order to be slightly more accurate, we will model gate delay as proportional to the number of inputs in the gate.  Standardize on 10 units per input.  Therefore, an inverter has delay 10, a 32-input NAND gate has delay 320.  The basic gates are NAND, NOR, NOT. Gates such as AND, OR, etc all have "hidden" inverters that must be accounted for in your propagation delays.
-
-#### Documentation ####
-Code legibility and commenting matter! The key is to make sure that your code is "inheritable" – another designer should be able to understand what you were up to without re-inventing it. Use block comments at the top of your modules, and occasional comments within modules where appropriate to describe interesting details.  
-
-
-### Test Benches ###
-Construct a (set of) test bench(es) for your ALU and submodules as appropriate.  It is highly recommended that you create the tests before you create the ALU. Your top-level test harness must be in `alu.t.v` and instantiate the ALU module from `alu.v`.
-
-Be intelligent in your selection of your test cases. Making use of the hierarchy of your design will allow you to avoid exhaustive testing. Strive to make your test cases self-checking - detect and report errors, rather than forcing you to compare manually against expected behavior.
-
-
-### Report ###
-In this lab your team is designing the ALU subsystem. Write a report to the project manager in charge of the entire CPU demonstrating that your ALU design is complete, correct, and ready to be included in the CPU.
-
-#### Implementation ####
-
-Discuss any interesting design choices you made along the way.
-
-Include block diagrams of your ALU at an appropriate level of detail: the top-level diagram above is too abstract to say anything about your particular design, while a single figure with every AND gate and wire would be unintelligible. Use your hierarchy and organization to show the important pieces. If you took a Bitslice approach, you should show a single bit and how they fit together.
-
-#### Test Results ####
-For each ALU operation, include the following in your report:
-
-1. A written description of what tests you chose, and why you chose them.  This should be roughly a couple sentences per operation.
-1. Specific instances where your test bench caught a flaw in your design.
-1. As your ALU design evolves, you may find that new test cases should be added to your test bench.  This is a good thing.  When this happens, record specifically why these tests were added. 
-
-
-#### Timing Analysis ####
-Provide the worst case propagation delay for each of the operations of the ALU.  This can be calculated or simulated (preferably both).  Note: the propagation delay for some operations may depend heavily on your choice of operands.
-
-#### Work Plan Reflection ####
-Compare how long each unit work actually took to how long you predicted it would take.  This will help you better schedule future labs.
-
-
-## Submission ##
-Push your files to your team GitHub repository (the one listed on the team formation spreadsheet), and submit a pull request back to the course repository. It should include the following:
-
-1. Work plan (due 10/4)
-1. Report, as a self-contained PDF or MarkDown file
-1. ALU Verilog, with the specified top-level module in `alu.v`
-1. Test benches, including top-level `alu.t.v`
-1. Any scripts used for testing, commented or with a separate `README` on how to run everything and what to expect as output 
-
-
-## Hints/Notes ##
-
-### Define ###
-You can use the define syntax to make your code cleaner.  For example, consider labeling your ALU commands with defines:
-
-```verilog
-`define ADD  3'd0
-`define SUB  3'd1
-`define XOR  3'd2
-`define SLT  3'd3
-`define AND  3'd4
-`define NAND 3'd5
-`define NOR  3'd6
-`define OR   3'd7
-```
-
-### Control Logic LUT ###
-
-A useful approach for implementing complex systems in a CPU is to separate the datapath (regular, possibly bit-sliced) from the control (irregular). You may choose to implement the control logic in your ALU as a Look Up Table. One way to implement this in (behavioral) Verilog is below:
-
-```verilog
-module ALUcontrolLUT
-(
-output reg[2:0] 	muxindex,
-output reg	invertB,
-output reg	othercontrolsignal,
-...
-input[2:0]	ALUcommand
-)
-
-  always @(ALUcommand) begin
-    case (ALUcommand)
-      `ADD:  begin muxindex = 0; invertB=0; othercontrolsignal = ?; end    
-      `SUB:  begin muxindex = 0; invertB=1; othercontrolsignal = ?; end
-      `XOR:  begin muxindex = 1; invertB=0; othercontrolsignal = ?; end    
-      `SLT:  begin muxindex = 2; invertB=?; othercontrolsignal = ?; end
-      `AND:  begin muxindex = 3; invertB=?; othercontrolsignal = ?; end    
-      `NAND: begin muxindex = 3; invertB=?; othercontrolsignal = ?; end
-      `NOR:  begin muxindex = ?; invertB=?; othercontrolsignal = ?; end    
-      `OR:   begin muxindex = ?; invertB=?; othercontrolsignal = ?; end
-    endcase
-  end
-endmodule
-```
-
-An advantage of this syntax is that it explicitly states what each control signal does for each command.
-
-To add additional control signals: modify the module definition, add the corresponding `output reg` lines, and add the state of the lines in each case. Be careful to set each control signal in each case.  If you accidentally omit one, it will generate latches that you don’t want to implement the behavior that you don’t want.
-
-### Overflow ###
-Only ADD and SUB emit overflow signals per the MIPS specification.  The basic Boolean operations do not emit an overflow signal for obvious reasons, and during these operations that wire is always `false`.
-
-The SLT operation is a bit weird here.  To calculate SLT you do need to determine whether or not there was an overflow.  However, in SLT this signal is not propagated outside of the ALU.  This is because the processor interprets the overflow signal as an "emergency" situation and begins an exception handling process.  Overflows generated during SLT are expected and are not emergencies.
+The purpose of this lab is to implement a 32-bit ALU in Verilog. [For lab writeup see here.](https://docs.google.com/document/d/1hVpe1RlciXp57nrlVHNf2zgQpX9TBWAB4SeN_-JxTkc/edit?usp=sharing)
diff --git a/adder1bit.v b/adder1bit.v
new file mode 100644
index 0000000..d8cad02
--- /dev/null
+++ b/adder1bit.v
@@ -0,0 +1,27 @@
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
+module Adder1bit
+(
+    output sum,
+    output carryout,
+    input a,
+    input b,
+    input carryin
+);
+    wire aandb, aorb;
+    wire s, _carryin;
+    wire outputIfCarryin, outputIf_Carryin;
+    `XOR(s, a, b);
+    `XOR(sum, s, carryin);
+    `AND(aandb, a, b);
+    `OR(aorb, a, b);
+    `NOT(_carryin, carryin);
+    `AND(outputIfCarryin, aandb, _carryin);
+    `AND(outputIf_Carryin, aorb, carryin);
+    `OR(carryout, outputIfCarryin, outputIf_Carryin);
+endmodule
diff --git a/adder4bit.vcd b/adder4bit.vcd
new file mode 100644
index 0000000..c152fdc
--- /dev/null
+++ b/adder4bit.vcd
@@ -0,0 +1,15587 @@
+$date
+	Wed Oct 11 15:50:02 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testALU $end
+$var wire 1 ! cout $end
+$var wire 32 " out [31:0] $end
+$var wire 1 # overflow $end
+$var wire 1 $ zero $end
+$var reg 32 % a [31:0] $end
+$var reg 32 & b [31:0] $end
+$var reg 3 ' op [2:0] $end
+$var integer 32 ( passed_tests [31:0] $end
+$var integer 32 ) tests [31:0] $end
+$scope function test $end
+$var reg 1 * show_extras $end
+$var integer 32 + test [31:0] $end
+$var integer 32 , test_case [31:0] $end
+$upscope $end
+$scope module alu $end
+$var wire 1 ! carryout $end
+$var wire 3 - command [2:0] $end
+$var wire 32 . cout [31:0] $end
+$var wire 32 / operandA [31:0] $end
+$var wire 32 0 operandB [31:0] $end
+$var wire 1 # overflow $end
+$var wire 8 1 resMux0 [7:0] $end
+$var wire 8 2 resMux1 [7:0] $end
+$var wire 8 3 resMux10 [7:0] $end
+$var wire 8 4 resMux11 [7:0] $end
+$var wire 8 5 resMux12 [7:0] $end
+$var wire 8 6 resMux13 [7:0] $end
+$var wire 8 7 resMux14 [7:0] $end
+$var wire 8 8 resMux15 [7:0] $end
+$var wire 8 9 resMux16 [7:0] $end
+$var wire 8 : resMux17 [7:0] $end
+$var wire 8 ; resMux18 [7:0] $end
+$var wire 8 < resMux19 [7:0] $end
+$var wire 8 = resMux2 [7:0] $end
+$var wire 8 > resMux20 [7:0] $end
+$var wire 8 ? resMux21 [7:0] $end
+$var wire 8 @ resMux22 [7:0] $end
+$var wire 8 A resMux23 [7:0] $end
+$var wire 8 B resMux24 [7:0] $end
+$var wire 8 C resMux25 [7:0] $end
+$var wire 8 D resMux26 [7:0] $end
+$var wire 8 E resMux27 [7:0] $end
+$var wire 8 F resMux28 [7:0] $end
+$var wire 8 G resMux29 [7:0] $end
+$var wire 8 H resMux3 [7:0] $end
+$var wire 8 I resMux30 [7:0] $end
+$var wire 8 J resMux31 [7:0] $end
+$var wire 8 K resMux4 [7:0] $end
+$var wire 8 L resMux5 [7:0] $end
+$var wire 8 M resMux6 [7:0] $end
+$var wire 8 N resMux7 [7:0] $end
+$var wire 8 O resMux8 [7:0] $end
+$var wire 8 P resMux9 [7:0] $end
+$var wire 32 Q res_premux [31:0] $end
+$var wire 32 R result [31:0] $end
+$var wire 1 S temp $end
+$var wire 1 $ zero $end
+$scope module a1 $end
+$var wire 1 T a $end
+$var wire 1 U b $end
+$var wire 1 V cin $end
+$var wire 1 W cout $end
+$var wire 1 X cout_ADD $end
+$var wire 1 Y cout_SLT $end
+$var wire 1 Z cout_SUB $end
+$var wire 8 [ muxCout [7:0] $end
+$var wire 8 \ muxRes [7:0] $end
+$var wire 3 ] op [2:0] $end
+$var wire 1 ^ out $end
+$var wire 1 _ res_ADD $end
+$var wire 1 ` res_AND $end
+$var wire 1 a res_NAND $end
+$var wire 1 b res_NOR $end
+$var wire 1 c res_OR $end
+$var wire 1 d res_SLT $end
+$var wire 1 e res_SUB $end
+$var wire 1 f res_XOR $end
+$scope module adder $end
+$var wire 1 g _carryin $end
+$var wire 1 T a $end
+$var wire 1 h aandb $end
+$var wire 1 i aorb $end
+$var wire 1 U b $end
+$var wire 1 V carryin $end
+$var wire 1 X carryout $end
+$var wire 1 j outputIfCarryin $end
+$var wire 1 k outputIf_Carryin $end
+$var wire 1 l s $end
+$var wire 1 _ sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 T a $end
+$var wire 1 m axorb $end
+$var wire 1 U b $end
+$var wire 1 V borrowin $end
+$var wire 1 Z borrowout $end
+$var wire 1 e diff $end
+$var wire 1 n nota $end
+$var wire 1 o notaandb $end
+$var wire 1 p notaxorb $end
+$var wire 1 q notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 T a $end
+$var wire 1 r axorb $end
+$var wire 1 U b $end
+$var wire 1 V borrowin $end
+$var wire 1 Y borrowout $end
+$var wire 1 d diff $end
+$var wire 1 s nota $end
+$var wire 1 t notaandb $end
+$var wire 1 u notaxorb $end
+$var wire 1 v notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 w address [2:0] $end
+$var wire 8 x inputs [7:0] $end
+$var wire 1 ^ out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 y address [2:0] $end
+$var wire 8 z inputs [7:0] $end
+$var wire 1 W out $end
+$upscope $end
+$upscope $end
+$scope module a2 $end
+$var wire 1 { a $end
+$var wire 1 | b $end
+$var wire 1 } cin $end
+$var wire 1 ~ cout $end
+$var wire 1 !" cout_ADD $end
+$var wire 1 "" cout_SLT $end
+$var wire 1 #" cout_SUB $end
+$var wire 8 $" muxCout [7:0] $end
+$var wire 8 %" muxRes [7:0] $end
+$var wire 3 &" op [2:0] $end
+$var wire 1 '" out $end
+$var wire 1 (" res_ADD $end
+$var wire 1 )" res_AND $end
+$var wire 1 *" res_NAND $end
+$var wire 1 +" res_NOR $end
+$var wire 1 ," res_OR $end
+$var wire 1 -" res_SLT $end
+$var wire 1 ." res_SUB $end
+$var wire 1 /" res_XOR $end
+$scope module adder $end
+$var wire 1 0" _carryin $end
+$var wire 1 { a $end
+$var wire 1 1" aandb $end
+$var wire 1 2" aorb $end
+$var wire 1 | b $end
+$var wire 1 } carryin $end
+$var wire 1 !" carryout $end
+$var wire 1 3" outputIfCarryin $end
+$var wire 1 4" outputIf_Carryin $end
+$var wire 1 5" s $end
+$var wire 1 (" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 { a $end
+$var wire 1 6" axorb $end
+$var wire 1 | b $end
+$var wire 1 } borrowin $end
+$var wire 1 #" borrowout $end
+$var wire 1 ." diff $end
+$var wire 1 7" nota $end
+$var wire 1 8" notaandb $end
+$var wire 1 9" notaxorb $end
+$var wire 1 :" notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 { a $end
+$var wire 1 ;" axorb $end
+$var wire 1 | b $end
+$var wire 1 } borrowin $end
+$var wire 1 "" borrowout $end
+$var wire 1 -" diff $end
+$var wire 1 <" nota $end
+$var wire 1 =" notaandb $end
+$var wire 1 >" notaxorb $end
+$var wire 1 ?" notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 @" address [2:0] $end
+$var wire 8 A" inputs [7:0] $end
+$var wire 1 '" out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 B" address [2:0] $end
+$var wire 8 C" inputs [7:0] $end
+$var wire 1 ~ out $end
+$upscope $end
+$upscope $end
+$scope module a3 $end
+$var wire 1 D" a $end
+$var wire 1 E" b $end
+$var wire 1 F" cin $end
+$var wire 1 G" cout $end
+$var wire 1 H" cout_ADD $end
+$var wire 1 I" cout_SLT $end
+$var wire 1 J" cout_SUB $end
+$var wire 8 K" muxCout [7:0] $end
+$var wire 8 L" muxRes [7:0] $end
+$var wire 3 M" op [2:0] $end
+$var wire 1 N" out $end
+$var wire 1 O" res_ADD $end
+$var wire 1 P" res_AND $end
+$var wire 1 Q" res_NAND $end
+$var wire 1 R" res_NOR $end
+$var wire 1 S" res_OR $end
+$var wire 1 T" res_SLT $end
+$var wire 1 U" res_SUB $end
+$var wire 1 V" res_XOR $end
+$scope module adder $end
+$var wire 1 W" _carryin $end
+$var wire 1 D" a $end
+$var wire 1 X" aandb $end
+$var wire 1 Y" aorb $end
+$var wire 1 E" b $end
+$var wire 1 F" carryin $end
+$var wire 1 H" carryout $end
+$var wire 1 Z" outputIfCarryin $end
+$var wire 1 [" outputIf_Carryin $end
+$var wire 1 \" s $end
+$var wire 1 O" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 D" a $end
+$var wire 1 ]" axorb $end
+$var wire 1 E" b $end
+$var wire 1 F" borrowin $end
+$var wire 1 J" borrowout $end
+$var wire 1 U" diff $end
+$var wire 1 ^" nota $end
+$var wire 1 _" notaandb $end
+$var wire 1 `" notaxorb $end
+$var wire 1 a" notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 D" a $end
+$var wire 1 b" axorb $end
+$var wire 1 E" b $end
+$var wire 1 F" borrowin $end
+$var wire 1 I" borrowout $end
+$var wire 1 T" diff $end
+$var wire 1 c" nota $end
+$var wire 1 d" notaandb $end
+$var wire 1 e" notaxorb $end
+$var wire 1 f" notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 g" address [2:0] $end
+$var wire 8 h" inputs [7:0] $end
+$var wire 1 N" out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 i" address [2:0] $end
+$var wire 8 j" inputs [7:0] $end
+$var wire 1 G" out $end
+$upscope $end
+$upscope $end
+$scope module a4 $end
+$var wire 1 k" a $end
+$var wire 1 l" b $end
+$var wire 1 m" cin $end
+$var wire 1 n" cout $end
+$var wire 1 o" cout_ADD $end
+$var wire 1 p" cout_SLT $end
+$var wire 1 q" cout_SUB $end
+$var wire 8 r" muxCout [7:0] $end
+$var wire 8 s" muxRes [7:0] $end
+$var wire 3 t" op [2:0] $end
+$var wire 1 u" out $end
+$var wire 1 v" res_ADD $end
+$var wire 1 w" res_AND $end
+$var wire 1 x" res_NAND $end
+$var wire 1 y" res_NOR $end
+$var wire 1 z" res_OR $end
+$var wire 1 {" res_SLT $end
+$var wire 1 |" res_SUB $end
+$var wire 1 }" res_XOR $end
+$scope module adder $end
+$var wire 1 ~" _carryin $end
+$var wire 1 k" a $end
+$var wire 1 !# aandb $end
+$var wire 1 "# aorb $end
+$var wire 1 l" b $end
+$var wire 1 m" carryin $end
+$var wire 1 o" carryout $end
+$var wire 1 ## outputIfCarryin $end
+$var wire 1 $# outputIf_Carryin $end
+$var wire 1 %# s $end
+$var wire 1 v" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 k" a $end
+$var wire 1 &# axorb $end
+$var wire 1 l" b $end
+$var wire 1 m" borrowin $end
+$var wire 1 q" borrowout $end
+$var wire 1 |" diff $end
+$var wire 1 '# nota $end
+$var wire 1 (# notaandb $end
+$var wire 1 )# notaxorb $end
+$var wire 1 *# notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 k" a $end
+$var wire 1 +# axorb $end
+$var wire 1 l" b $end
+$var wire 1 m" borrowin $end
+$var wire 1 p" borrowout $end
+$var wire 1 {" diff $end
+$var wire 1 ,# nota $end
+$var wire 1 -# notaandb $end
+$var wire 1 .# notaxorb $end
+$var wire 1 /# notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 0# address [2:0] $end
+$var wire 8 1# inputs [7:0] $end
+$var wire 1 u" out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 2# address [2:0] $end
+$var wire 8 3# inputs [7:0] $end
+$var wire 1 n" out $end
+$upscope $end
+$upscope $end
+$scope module a5 $end
+$var wire 1 4# a $end
+$var wire 1 5# b $end
+$var wire 1 6# cin $end
+$var wire 1 7# cout $end
+$var wire 1 8# cout_ADD $end
+$var wire 1 9# cout_SLT $end
+$var wire 1 :# cout_SUB $end
+$var wire 8 ;# muxCout [7:0] $end
+$var wire 8 <# muxRes [7:0] $end
+$var wire 3 =# op [2:0] $end
+$var wire 1 ># out $end
+$var wire 1 ?# res_ADD $end
+$var wire 1 @# res_AND $end
+$var wire 1 A# res_NAND $end
+$var wire 1 B# res_NOR $end
+$var wire 1 C# res_OR $end
+$var wire 1 D# res_SLT $end
+$var wire 1 E# res_SUB $end
+$var wire 1 F# res_XOR $end
+$scope module adder $end
+$var wire 1 G# _carryin $end
+$var wire 1 4# a $end
+$var wire 1 H# aandb $end
+$var wire 1 I# aorb $end
+$var wire 1 5# b $end
+$var wire 1 6# carryin $end
+$var wire 1 8# carryout $end
+$var wire 1 J# outputIfCarryin $end
+$var wire 1 K# outputIf_Carryin $end
+$var wire 1 L# s $end
+$var wire 1 ?# sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 4# a $end
+$var wire 1 M# axorb $end
+$var wire 1 5# b $end
+$var wire 1 6# borrowin $end
+$var wire 1 :# borrowout $end
+$var wire 1 E# diff $end
+$var wire 1 N# nota $end
+$var wire 1 O# notaandb $end
+$var wire 1 P# notaxorb $end
+$var wire 1 Q# notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 4# a $end
+$var wire 1 R# axorb $end
+$var wire 1 5# b $end
+$var wire 1 6# borrowin $end
+$var wire 1 9# borrowout $end
+$var wire 1 D# diff $end
+$var wire 1 S# nota $end
+$var wire 1 T# notaandb $end
+$var wire 1 U# notaxorb $end
+$var wire 1 V# notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
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+$var wire 1 P/ out $end
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+$var wire 1 V/ out $end
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+$var wire 1 _/ out $end
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+$var wire 1 b/ out $end
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+$var wire 8 m/ inputs [7:0] $end
+$var wire 1 n/ out $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0n/
+b0 m/
+b0 l/
+0k/
+b0 j/
+b0 i/
+0h/
+b0 g/
+b0 f/
+0e/
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+b0 a/
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+0_/
+b0 ^/
+b0 ]/
+0\/
+b0 [/
+b0 Z/
+0Y/
+b0 X/
+b0 W/
+0V/
+b0 U/
+b0 T/
+0S/
+b0 R/
+b0 Q/
+0P/
+b0 O/
+b0 N/
+1M/
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+1j&
+1g&
+1k&
+0l&
+1p&
+0q&
+1-'
+0)'
+1*'
+b10101111 #'
+b10101111 ?'
+13'
+10'
+14'
+05'
+19'
+0:'
+1T'
+0P'
+1Q'
+b10101111 J'
+b10101111 f'
+1Z'
+1W'
+1['
+0\'
+1`'
+0a'
+1{'
+0w'
+1x'
+b10101111 q'
+b10101111 /(
+1#(
+1~'
+1$(
+0%(
+1)(
+0*(
+1`.
+1e.
+0A,
+1H.
+1{
+1D"
+1k"
+14#
+1[#
+1$$
+1K$
+1r$
+1;%
+1b%
+1+&
+1R&
+1y&
+1B'
+1i'
+0G.
+b10000000000000000000000000000000 &
+b10000000000000000000000000000000 0
+b1111111111111111 %
+b1111111111111111 /
+b11011 (
+b11011 )
+#28000000
+b11100 (
+b11100 )
diff --git a/alu.t.v b/alu.t.v
new file mode 100644
index 0000000..1ac50e2
--- /dev/null
+++ b/alu.t.v
@@ -0,0 +1,188 @@
+// 1 Bit alu test bench
+`timescale 1 ns / 1 ps
+`include "alu.v"
+
+module testALU ();
+  wire[31:0] out;
+  wire       zero, overflow, cout;
+  reg[31:0]  a, b;
+  reg[2:0]   op;
+
+  integer passed_tests = 0;
+  integer tests = 0;
+
+  ALU alu (out,cout,zero,overflow,a,b,op);
+
+  function integer test;
+    input test_case;
+    integer test_case;
+    input show_extras;
+    begin
+      if (test_case) begin
+        test = 1;
+        $display("Passed test with:");
+      end
+      else begin
+        test = 0;
+        $display("Failed test with:");
+      end
+      $display("a:   %b", a);
+      $display("b:   %b", b);
+      $display("out: %b", out);
+      if (show_extras) begin
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+      end
+    end
+  endfunction
+
+
+  initial begin
+    $dumpfile("alu.vcd");
+    $dumpvars;
+
+    // Test Add
+    $display("\nAddition");
+    $display("-----------------------------------------------------------------");
+    op=3'b000;
+    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 0), 1);
+
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 0), 1);
+
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 1), 1);
+
+    // Overflow
+    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 1), 1);
+
+    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 1), 1);
+
+    // Test Subtract
+    $display("Subtraction");
+    $display("-----------------------------------------------------------------");
+    op=3'b001;
+    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0) && (cout == 0), 1);
+
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0) && (cout == 0), 1);
+
+    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0), 1);
+
+    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0), 1);
+
+    a=32'b01000000000000000000000000000000; b=32'b10000000000010101010000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 1), 1);
+
+    a=32'b10000000000000000000000000000000; b=32'b01000000000010101010000000000001;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 1), 1);
+
+    // Test XOR
+    $display("\nXOR");
+    $display("-----------------------------------------------------------------");
+    op=3'b010;
+    $display("op: %b", op);
+    a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test((a ^ b) == out, 0);
+
+    // Test SLT
+    $display("\nSLT");
+    $display("-----------------------------------------------------------------");
+    op=3'b011;
+    $display("op: %b", op);
+    // SLT(a,b) = 1 where a<b
+    a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#2000
+    tests = tests + 1;
+
+    passed_tests = passed_tests + test(out == 1, 1);
+    // SLT(a,b) = 0 where a>b
+    a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+
+    // SLT(a,b) = 1 where a(is negative)<b(is positive)
+    a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+    // SLT(a,b) = 0 where a(is positive)>b(is negative)
+    a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#2000
+    tests = tests + 1;
+
+    passed_tests = passed_tests + test(out == 0, 1);
+    // SLT(a,b) = 1 where a(is negative)>b(is negative)
+    a=32'b10000000000000000000000000001000; b=32'b10000000000000000000001000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+
+    // SLT(a,b) = 1 where a(is negative)>b(is negative)
+    a=32'b10000000000000000000000000001000; b=32'b00000000001000000000000000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+
+    // small pos / large pos = 1
+    a=32'b00000000000000000000000000001000; b=32'b01110000001000000000000000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+    // large pos / small pos = 0
+    a=32'b01110000000000000000000000001000; b=32'b00000000001000000000000000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+    // equal positives = 0
+    a=32'b01110000000000000000000000001000; b=32'b01110000000000000000000000000000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+
+    // small neg / large neg = 0
+    a=32'b11111111000000000000000000001000; b=32'b10000000000000000000000000000111;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+    // large neg / small neg = 1
+    a=32'b10000000000000000000000000000111; b=32'b11111111000000000000000000001000;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+    // equal negatives = 0
+    a=32'b10000000000000000000000000000111; b=32'b10000000000000000000000000000111;#2000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+
+    // positive overflow: large pos / large neg : 0
+    a=32'b01000000000000000000000000000001; b=32'b10000000000000000000000000010000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+    // negative overflow: large neg / large pos : 1
+    a=32'b10000000000000000000000000000001; b=32'b00000100000000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+
+    a=32'b00000000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+
+    a=32'b00100000000000000000000000000001; b=32'b10000000000000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+
+    a=32'b10000000000000000000000000000000; b=32'b01111111111111111111111111111111;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+    $display("%2d/%2d Test Cases Passed", passed_tests, tests);
+
+    end
+endmodule
diff --git a/alu.v b/alu.v
new file mode 100644
index 0000000..cfff904
--- /dev/null
+++ b/alu.v
@@ -0,0 +1,140 @@
+// ALU is a 32-Bit arithmetic logic unit
+// It performs the following operations:
+// b000 -> ADD
+// b001 -> SUB
+// b010 -> XOR
+// b011 -> SLT
+// b100 -> AND
+// b101 -> NAND
+// b110 -> NOR
+// b111 -> OR
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
+`include "alu1bit.v"
+
+module ALU
+(
+  output[31:0]  result,
+  output        carryout,
+  output        zero,
+  output        overflow,
+  input[31:0]   operandA,
+  input[31:0]   operandB,
+  input[2:0]    command
+);
+
+  wire[31:0] cout;
+  wire[31:0] res_premux;
+  ALU1bit a1(res_premux[0], cout[0], operandA[0], operandB[0], 0, command);
+  ALU1bit a2(res_premux[1], cout[1], operandA[1], operandB[1], cout[0], command);
+  ALU1bit a3(res_premux[2], cout[2], operandA[2], operandB[2], cout[1], command);
+  ALU1bit a4(res_premux[3], cout[3], operandA[3], operandB[3], cout[2], command);
+  ALU1bit a5(res_premux[4], cout[4], operandA[4], operandB[4], cout[3], command);
+  ALU1bit a6(res_premux[5], cout[5], operandA[5], operandB[5], cout[4], command);
+  ALU1bit a7(res_premux[6], cout[6], operandA[6], operandB[6], cout[5], command);
+  ALU1bit a8(res_premux[7], cout[7], operandA[7], operandB[7], cout[6], command);
+  ALU1bit a9(res_premux[8], cout[8], operandA[8], operandB[8], cout[7], command);
+  ALU1bit a10(res_premux[9], cout[9], operandA[9], operandB[9], cout[8], command);
+  ALU1bit a11(res_premux[10], cout[10], operandA[10], operandB[10], cout[9], command);
+  ALU1bit a12(res_premux[11], cout[11], operandA[11], operandB[11], cout[10], command);
+  ALU1bit a13(res_premux[12], cout[12], operandA[12], operandB[12], cout[11], command);
+  ALU1bit a14(res_premux[13], cout[13], operandA[13], operandB[13], cout[12], command);
+  ALU1bit a15(res_premux[14], cout[14], operandA[14], operandB[14], cout[13], command);
+  ALU1bit a16(res_premux[15], cout[15], operandA[15], operandB[15], cout[14], command);
+  ALU1bit a17(res_premux[16], cout[16], operandA[16], operandB[16], cout[15], command);
+  ALU1bit a18(res_premux[17], cout[17], operandA[17], operandB[17], cout[16], command);
+  ALU1bit a19(res_premux[18], cout[18], operandA[18], operandB[18], cout[17], command);
+  ALU1bit a20(res_premux[19], cout[19], operandA[19], operandB[19], cout[18], command);
+  ALU1bit a21(res_premux[20], cout[20], operandA[20], operandB[20], cout[19], command);
+  ALU1bit a22(res_premux[21], cout[21], operandA[21], operandB[21], cout[20], command);
+  ALU1bit a23(res_premux[22], cout[22], operandA[22], operandB[22], cout[21], command);
+  ALU1bit a24(res_premux[23], cout[23], operandA[23], operandB[23], cout[22], command);
+  ALU1bit a25(res_premux[24], cout[24], operandA[24], operandB[24], cout[23], command);
+  ALU1bit a26(res_premux[25], cout[25], operandA[25], operandB[25], cout[24], command);
+  ALU1bit a27(res_premux[26], cout[26], operandA[26], operandB[26], cout[25], command);
+  ALU1bit a28(res_premux[27], cout[27], operandA[27], operandB[27], cout[26], command);
+  ALU1bit a29(res_premux[28], cout[28], operandA[28], operandB[28], cout[27], command);
+  ALU1bit a30(res_premux[29], cout[29], operandA[29], operandB[29], cout[28], command);
+  ALU1bit a31(res_premux[30], cout[30], operandA[30], operandB[30], cout[29], command);
+  ALU1bit a32(res_premux[31], carryout, operandA[31], operandB[31], cout[30], command);
+  `XOR(overflow, carryout, cout[30]);
+
+  // We're using subtraction for SLT. We have to handle additional cases
+  // for the cases where we have overflow.
+  wire temp;
+  `XOR(temp, res_premux[31], overflow);
+
+  // This mux is necessary for handling the SLT, since the desired result of the SLT 
+  // is very different from the actual output from our ALU.
+  // We could have used a MUX of size 2, but that would have required conversion
+  // of the SLT command.
+  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], temp, res_premux[0], res_premux[0], res_premux[0]};
+  MUX3bit mux0(result[0], command, resMux0);
+  wire[7:0] resMux1 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b0, res_premux[1], res_premux[1], res_premux[1]};
+  MUX3bit mux1(result[1], command, resMux1);
+  wire[7:0] resMux2 = {res_premux[2], res_premux[2], res_premux[2], res_premux[2], 1'b0, res_premux[2], res_premux[2], res_premux[2]};
+  MUX3bit mux2(result[2], command, resMux2);
+  wire[7:0] resMux3 = {res_premux[3], res_premux[3], res_premux[3], res_premux[3], 1'b0, res_premux[3], res_premux[3], res_premux[3]};
+  MUX3bit mux3(result[3], command, resMux3);
+  wire[7:0] resMux4 = {res_premux[4], res_premux[4], res_premux[4], res_premux[4], 1'b0, res_premux[4], res_premux[4], res_premux[4]};
+  MUX3bit mux4(result[4], command, resMux4);
+  wire[7:0] resMux5 = {res_premux[5], res_premux[5], res_premux[5], res_premux[5], 1'b0, res_premux[5], res_premux[5], res_premux[5]};
+  MUX3bit mux5(result[5], command, resMux5);
+  wire[7:0] resMux6 = {res_premux[6], res_premux[6], res_premux[6], res_premux[6], 1'b0, res_premux[6], res_premux[6], res_premux[6]};
+  MUX3bit mux6(result[6], command, resMux6);
+  wire[7:0] resMux7 = {res_premux[7], res_premux[7], res_premux[7], res_premux[7], 1'b0, res_premux[7], res_premux[7], res_premux[7]};
+  MUX3bit mux7(result[7], command, resMux7);
+  wire[7:0] resMux8 = {res_premux[8], res_premux[8], res_premux[8], res_premux[8], 1'b0, res_premux[8], res_premux[8], res_premux[8]};
+  MUX3bit mux8(result[8], command, resMux8);
+  wire[7:0] resMux9 = {res_premux[9], res_premux[9], res_premux[9], res_premux[9], 1'b0, res_premux[9], res_premux[9], res_premux[9]};
+  MUX3bit mux9(result[9], command, resMux9);
+  wire[7:0] resMux10 = {res_premux[10], res_premux[10], res_premux[10], res_premux[10], 1'b0, res_premux[10], res_premux[10], res_premux[10]};
+  MUX3bit mux10(result[10], command, resMux10);
+  wire[7:0] resMux11 = {res_premux[11], res_premux[11], res_premux[11], res_premux[11], 1'b0, res_premux[11], res_premux[11], res_premux[11]};
+  MUX3bit mux11(result[11], command, resMux11);
+  wire[7:0] resMux12 = {res_premux[12], res_premux[12], res_premux[12], res_premux[12], 1'b0, res_premux[12], res_premux[12], res_premux[12]};
+  MUX3bit mux12(result[12], command, resMux12);
+  wire[7:0] resMux13 = {res_premux[13], res_premux[13], res_premux[13], res_premux[13], 1'b0, res_premux[13], res_premux[13], res_premux[13]};
+  MUX3bit mux13(result[13], command, resMux13);
+  wire[7:0] resMux14 = {res_premux[14], res_premux[14], res_premux[14], res_premux[14], 1'b0, res_premux[14], res_premux[14], res_premux[14]};
+  MUX3bit mux14(result[14], command, resMux14);
+  wire[7:0] resMux15 = {res_premux[15], res_premux[15], res_premux[15], res_premux[15], 1'b0, res_premux[15], res_premux[15], res_premux[15]};
+  MUX3bit mux15(result[15], command, resMux15);
+  wire[7:0] resMux16 = {res_premux[16], res_premux[16], res_premux[16], res_premux[16], 1'b0, res_premux[16], res_premux[16], res_premux[16]};
+  MUX3bit mux16(result[16], command, resMux16);
+  wire[7:0] resMux17 = {res_premux[17], res_premux[17], res_premux[17], res_premux[17], 1'b0, res_premux[17], res_premux[17], res_premux[17]};
+  MUX3bit mux17(result[17], command, resMux17);
+  wire[7:0] resMux18 = {res_premux[18], res_premux[18], res_premux[18], res_premux[18], 1'b0, res_premux[18], res_premux[18], res_premux[18]};
+  MUX3bit mux18(result[18], command, resMux18);
+  wire[7:0] resMux19 = {res_premux[19], res_premux[19], res_premux[19], res_premux[19], 1'b0, res_premux[19], res_premux[19], res_premux[19]};
+  MUX3bit mux19(result[19], command, resMux19);
+  wire[7:0] resMux20 = {res_premux[20], res_premux[20], res_premux[20], res_premux[20], 1'b0, res_premux[20], res_premux[20], res_premux[20]};
+  MUX3bit mux20(result[20], command, resMux20);
+  wire[7:0] resMux21 = {res_premux[21], res_premux[21], res_premux[21], res_premux[21], 1'b0, res_premux[21], res_premux[21], res_premux[21]};
+  MUX3bit mux21(result[21], command, resMux21);
+  wire[7:0] resMux22 = {res_premux[22], res_premux[22], res_premux[22], res_premux[22], 1'b0, res_premux[22], res_premux[22], res_premux[22]};
+  MUX3bit mux22(result[22], command, resMux22);
+  wire[7:0] resMux23 = {res_premux[23], res_premux[23], res_premux[23], res_premux[23], 1'b0, res_premux[23], res_premux[23], res_premux[23]};
+  MUX3bit mux23(result[23], command, resMux23);
+  wire[7:0] resMux24 = {res_premux[24], res_premux[24], res_premux[24], res_premux[24], 1'b0, res_premux[24], res_premux[24], res_premux[24]};
+  MUX3bit mux24(result[24], command, resMux24);
+  wire[7:0] resMux25 = {res_premux[25], res_premux[25], res_premux[25], res_premux[25], 1'b0, res_premux[25], res_premux[25], res_premux[25]};
+  MUX3bit mux25(result[25], command, resMux25);
+  wire[7:0] resMux26 = {res_premux[26], res_premux[26], res_premux[26], res_premux[26], 1'b0, res_premux[26], res_premux[26], res_premux[26]};
+  MUX3bit mux26(result[26], command, resMux26);
+  wire[7:0] resMux27 = {res_premux[27], res_premux[27], res_premux[27], res_premux[27], 1'b0, res_premux[27], res_premux[27], res_premux[27]};
+  MUX3bit mux27(result[27], command, resMux27);
+  wire[7:0] resMux28 = {res_premux[28], res_premux[28], res_premux[28], res_premux[28], 1'b0, res_premux[28], res_premux[28], res_premux[28]};
+  MUX3bit mux28(result[28], command, resMux28);
+  wire[7:0] resMux29 = {res_premux[29], res_premux[29], res_premux[29], res_premux[29], 1'b0, res_premux[29], res_premux[29], res_premux[29]};
+  MUX3bit mux29(result[29], command, resMux29);
+  wire[7:0] resMux30 = {res_premux[30], res_premux[30], res_premux[30], res_premux[30], 1'b0, res_premux[30], res_premux[30], res_premux[30]};
+  MUX3bit mux30(result[30], command, resMux30);
+  wire[7:0] resMux31 = {res_premux[31], res_premux[31], res_premux[31], res_premux[31], 1'b0, res_premux[31], res_premux[31], res_premux[31]};
+  MUX3bit mux31(result[31], command, resMux31);
+endmodule
diff --git a/alu.vcd b/alu.vcd
new file mode 100644
index 0000000..ba6d7b3
--- /dev/null
+++ b/alu.vcd
@@ -0,0 +1,23762 @@
+$date
+	Wed Oct 11 16:32:49 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testALU $end
+$var wire 1 ! cout $end
+$var wire 32 " out [31:0] $end
+$var wire 1 # overflow $end
+$var wire 1 $ zero $end
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diff --git a/alu1bit.t.v b/alu1bit.t.v
new file mode 100644
index 0000000..4591a50
--- /dev/null
+++ b/alu1bit.t.v
@@ -0,0 +1,209 @@
+// 1 Bit alu test bench
+`timescale 1 ns / 1 ps
+`include "alu1bit.v"
+
+module testALU1bit ();
+  wire     out, cout;
+  reg      a, b, cin;
+  reg[2:0] op;
+
+  integer i, j;
+  integer passed_tests = 0;
+  integer tests = 0;
+
+  ALU1bit alu (out,cout,a,b,cin,op);
+
+  initial begin
+
+    // Test ADD
+    $display("ADD:");
+    op=3'b000;
+    // without cin
+    cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a + b) == out) & ((a & b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout); end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a ~^ b) == out) & ((a | b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test SUB
+    $display("SUB:");
+    op=3'b001;
+    // without cin
+    cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a - b) == out) & ((a < b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a ~^ b) == out) & ((a <= b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+
+    // Test XOR
+    $display("XOR:");
+    op=3'b010; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if ((a ^ b) == out) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    //Test SLT
+    $display("SLT:");
+    op=3'b001;
+    // without cin
+    cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a - b) == out) & ((a < b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a ~^ b) == out) & ((a <= b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test AND
+    $display("AND:");
+    op=3'b100; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if ((a & b) == out) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test NAND
+    $display("NAND:");
+    op=3'b101; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (~(a&b) == out) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test NOR
+    $display("NOR:");
+    op=3'b110; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if ((a ~| b) == out) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test OR
+    $display("OR:");
+    op=3'b111; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if ((a|b) == out) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    $display("                  op   a  b cin|out cout ");
+
+    $display("%2d/%2d Test Cases Passed", passed_tests, tests);
+
+    end
+endmodule
diff --git a/alu1bit.v b/alu1bit.v
new file mode 100644
index 0000000..b1602dc
--- /dev/null
+++ b/alu1bit.v
@@ -0,0 +1,73 @@
+// ALU1bit is a 1-Bit arithmetic logic unit
+// It performs the following operations:
+// b000 -> ADD
+// b001 -> SUB
+// b010 -> XOR
+// b011 -> SLT
+// b100 -> AND
+// b101 -> NAND
+// b110 -> NOR
+// b111 -> OR
+
+`include "mux3bit.v"
+`include "adder1bit.v"
+`include "subtractor1bit.v"
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
+
+module ALU1bit
+(
+  output      out,
+  output      cout,
+  input       a,
+  input       b,
+  input       cin,
+  input[2:0]  op
+);
+	// Add
+	wire res_ADD;
+	wire cout_ADD;
+	Adder1bit adder(res_ADD, cout_ADD, a, b, cin);
+
+	// Subtract
+	wire res_SUB;
+	wire cout_SUB;
+	Subtractor1bit subtractor(res_SUB, cout_SUB, a, b, cin);
+
+	// Xor
+	wire res_XOR;
+	`XOR(res_XOR, a, b);
+
+	// SLT
+	wire res_SLT;
+	wire cout_SLT;
+	Subtractor1bit slt(res_SLT, cout_SLT, a, b, cin);
+
+	// And
+	wire res_AND;
+	`AND(res_AND, a, b);
+
+	// Nand
+	wire res_NAND;
+	`NAND(res_NAND, a, b);
+
+	// Nor
+	wire res_NOR;
+	`NOR(res_NOR, a, b);
+
+	// Or
+	wire res_OR;
+	`OR(res_OR, a, b);
+
+	// Use a behavioral mux to select operation
+	wire[7:0] muxRes = {res_OR, res_NOR, res_NAND, res_AND, res_SLT, res_XOR, res_SUB, res_ADD};
+	wire[7:0] muxCout = {1'b0, 1'b0, 1'b0, 1'b0, cout_SLT, 1'b0, cout_SUB, cout_ADD};
+	MUX3bit mux1(out, op, muxRes);
+	MUX3bit mux2(cout, op, muxCout);
+
+endmodule
diff --git a/mux3bit.t.v b/mux3bit.t.v
new file mode 100644
index 0000000..0dc67c9
--- /dev/null
+++ b/mux3bit.t.v
@@ -0,0 +1,26 @@
+// Multiplexer testbench
+`timescale 1 ns / 1 ps
+`include "mux3bit.v"
+
+module testMultiplexer ();
+  reg[2:0] address;
+  reg[7:0] inputs;
+  wire out;
+
+  //behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
+  MUX3bit mux(out, address, inputs);
+
+  initial begin
+    $display("address | inputs   | Out | Expected Output");
+    inputs=8'b00000001;address=3'b000; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000100;address=3'b010; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b10000000;address=3'b111; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b01000000;address=3'b110; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000000;address=3'b100; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b0);
+  end
+endmodule
diff --git a/mux3bit.v b/mux3bit.v
new file mode 100644
index 0000000..f8c5a20
--- /dev/null
+++ b/mux3bit.v
@@ -0,0 +1,8 @@
+module MUX3bit
+(
+    output out,
+    input[2:0] address,
+    input[7:0] inputs
+);
+    assign out = inputs[address];
+endmodule
diff --git a/muxTest.t.v b/muxTest.t.v
new file mode 100644
index 0000000..7dd39ea
--- /dev/null
+++ b/muxTest.t.v
@@ -0,0 +1,26 @@
+// Multiplexer testbench
+`timescale 1 ns / 1 ps
+`include "alu1bit.v"
+
+module testMultiplexer ();
+  reg[2:0] address;
+  reg[7:0] inputs;
+  wire out;
+
+  //behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
+  behavioralMultiplexer mux(out, address, inputs);
+
+  initial begin
+    $display("address | inputs   | Out | Expected Output");
+    inputs=8'b00000001;address=3'b000; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000100;address=3'b010; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b10000000;address=3'b111; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b01000000;address=3'b110; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000000;address=3'b100; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b0);
+  end
+endmodule
diff --git a/subtractor1bit.v b/subtractor1bit.v
new file mode 100644
index 0000000..a08ad11
--- /dev/null
+++ b/subtractor1bit.v
@@ -0,0 +1,25 @@
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
+module Subtractor1bit
+(
+    output diff,
+    output borrowout,
+    input a,
+    input b,
+    input borrowin
+);
+    wire axorb;
+    `XOR(axorb, a, b);
+    `XOR(diff, axorb, borrowin);
+    wire nota, noteaandb, notaxorb, notaxorbandborrowin;
+    `NOT(nota, a);
+    `AND(notaandb, nota, b);
+    `NOT(notaxorb, axorb);
+    `AND(notaxorbandborrowin, notaxorb, borrowin);
+    `OR(borrowout, notaandb, notaxorbandborrowin);
+endmodule