From add0bd085fdc1a0c4286f3277262066849e4b5e1 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Fri, 6 Oct 2017 09:50:21 -0400
Subject: [PATCH 01/52] Initial Commit

---
 .gitignore |  1 +
 alu.v      | 25 +++++++++++++++++++++++++
 alu1bit.v  | 23 +++++++++++++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 alu.v
 create mode 100644 alu1bit.v

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..f47cb20
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*.out
diff --git a/alu.v b/alu.v
new file mode 100644
index 0000000..de280cd
--- /dev/null
+++ b/alu.v
@@ -0,0 +1,25 @@
+// ALU is a 32-Bit arithmetic logic unit
+// It performs the following operations:
+// b000 -> ADD
+// b001 -> SUB
+// b010 -> XOR
+// b011 -> SLT
+// b100 -> AND
+// b101 -> NAND
+
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+
+module ALU
+(
+  output[31:0]  result,
+  output        carryout,
+  output        zero,
+  output        overflow,
+  input[31:0]   operandA,
+  input[31:0]   operandB,
+  input[2:0]    command
+);
+  // Your code here
+endmodule
diff --git a/alu1bit.v b/alu1bit.v
new file mode 100644
index 0000000..9a204d8
--- /dev/null
+++ b/alu1bit.v
@@ -0,0 +1,23 @@
+// ALU1bit is a 31-Bit arithmetic logic unit
+// It performs the following operations:
+// b000 -> ADD
+// b001 -> SUB
+// b010 -> XOR
+// b011 -> SLT
+// b100 -> AND
+// b101 -> NAND
+
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+
+module ALU
+(
+  output      result,
+  output      carryout,
+  input       operandA,
+  input       operandB,
+  input[2:0]  command
+);
+  // Your code here
+endmodule

From d709332e8c0f2429163bc8101f8097091d58f8fd Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Fri, 6 Oct 2017 10:22:15 -0400
Subject: [PATCH 02/52] created first tests, not working for some reason

---
 alu1bit.t.v | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 alu1bit.v   | 15 ++++++++-------
 2 files changed, 60 insertions(+), 7 deletions(-)
 create mode 100644 alu1bit.t.v

diff --git a/alu1bit.t.v b/alu1bit.t.v
new file mode 100644
index 0000000..7a3bf51
--- /dev/null
+++ b/alu1bit.t.v
@@ -0,0 +1,52 @@
+// 1 Bit alu test bench
+`timescale 1 ns / 1 ps
+`include "alu1bit.v"
+
+module testALU1bit ();
+  wire     out, cout;
+  reg      a, b, cin;
+  reg[2:0] op;
+
+  ALU1bit alu (out,cout,a,b,cin,op);
+  initial begin
+    // $dumpfile("../resources/mux.vcd");
+    // $dumpvars;
+
+    // Test ADD
+    op=3'b000;
+    // without cin
+    cin = 0;
+    // 0 + 0 = 0
+    // 0 + 1 = 1
+    // 1 + 0 = 1
+    //
+    // addr1=0;in0=0;in1=0;in2=0;in3=0; #1000
+    // if ()
+
+    // Test XOR
+    op=3'b010; cin = 0;
+    // 0 xor 0 = 0
+    a=0;b=0; #1000
+    if (cout != 0) begin
+        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    end
+    // 0 xor 1 = 1
+    a=0;b=1; #1000
+    if (cout != 1) begin
+        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    end
+    // 1 xor 0 = 1
+    a=1;b=0; #1000
+    if (cout != 1) begin
+        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    end
+    // 1 xor 1 = 0
+    a=1;b=1; #1000
+    if (cout != 0) begin
+        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    end
+
+    // Test next op...
+
+    end
+endmodule
diff --git a/alu1bit.v b/alu1bit.v
index 9a204d8..66c7622 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -1,4 +1,4 @@
-// ALU1bit is a 31-Bit arithmetic logic unit
+// ALU1bit is a 1-Bit arithmetic logic unit
 // It performs the following operations:
 // b000 -> ADD
 // b001 -> SUB
@@ -11,13 +11,14 @@
 `define OR or #30
 `define NOT not #10
 
-module ALU
+module ALU1bit
 (
-  output      result,
-  output      carryout,
-  input       operandA,
-  input       operandB,
-  input[2:0]  command
+  output      out,
+  output      cout,
+  input       a,
+  input       b,
+  input       cin,
+  input[2:0]  op
 );
   // Your code here
 endmodule

From 902eaa2c095b3e56f09d5c230d4fd9c32537a3b3 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 14:49:41 -0400
Subject: [PATCH 03/52] in middle of loop

---
 alu1bit.t.v | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 7a3bf51..09b1267 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -9,6 +9,7 @@ module testALU1bit ();
 
   ALU1bit alu (out,cout,a,b,cin,op);
   initial begin
+
     // $dumpfile("../resources/mux.vcd");
     // $dumpvars;
 
@@ -27,7 +28,14 @@ module testALU1bit ();
     op=3'b010; cin = 0;
     // 0 xor 0 = 0
     a=0;b=0; #1000
-    if (cout != 0) begin
+    integer i = 0
+    for (integer i=0; i<2; i = i + 1) begin
+        $display("asdf");
+    end
+    if (cout == 0) begin
+        $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    end
+    else begin
         $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
     end
     // 0 xor 1 = 1

From ee0bb2fe07908fa558bb89328ac6a8355c417162 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 15:08:17 -0400
Subject: [PATCH 04/52] Got xor part of test appartus workign

---
 alu1bit.t.v | 39 ++++++++++++---------------------------
 1 file changed, 12 insertions(+), 27 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 09b1267..09ac0a0 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -4,8 +4,9 @@
 
 module testALU1bit ();
   wire     out, cout;
-  reg      a, b, cin;
+  reg     a, b, cin;
   reg[2:0] op;
+  integer i, j;
 
   ALU1bit alu (out,cout,a,b,cin,op);
   initial begin
@@ -26,32 +27,16 @@ module testALU1bit ();
 
     // Test XOR
     op=3'b010; cin = 0;
-    // 0 xor 0 = 0
-    a=0;b=0; #1000
-    integer i = 0
-    for (integer i=0; i<2; i = i + 1) begin
-        $display("asdf");
-    end
-    if (cout == 0) begin
-        $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-    end
-    else begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-    end
-    // 0 xor 1 = 1
-    a=0;b=1; #1000
-    if (cout != 1) begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-    end
-    // 1 xor 0 = 1
-    a=1;b=0; #1000
-    if (cout != 1) begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-    end
-    // 1 xor 1 = 0
-    a=1;b=1; #1000
-    if (cout != 0) begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a = i;b=j;#1000
+            if (a ^ b == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
 
     // Test next op...

From c8a5385d2353f02b18a6b0f024ddc62c62e9bbd9 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 15:19:46 -0400
Subject: [PATCH 05/52] Finished adding logical tests

---
 alu.v       |  2 ++
 alu1bit.t.v | 70 ++++++++++++++++++++++++++++++++++++++++++++---------
 alu1bit.v   |  2 ++
 3 files changed, 63 insertions(+), 11 deletions(-)

diff --git a/alu.v b/alu.v
index de280cd..f27da96 100644
--- a/alu.v
+++ b/alu.v
@@ -6,6 +6,8 @@
 // b011 -> SLT
 // b100 -> AND
 // b101 -> NAND
+// b110 -> NOR
+// b111 -> OR
 
 `define AND and #30
 `define OR or #30
diff --git a/alu1bit.t.v b/alu1bit.t.v
index 09ac0a0..9f870b4 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -11,25 +11,16 @@ module testALU1bit ();
   ALU1bit alu (out,cout,a,b,cin,op);
   initial begin
 
-    // $dumpfile("../resources/mux.vcd");
-    // $dumpvars;
-
     // Test ADD
     op=3'b000;
     // without cin
     cin = 0;
-    // 0 + 0 = 0
-    // 0 + 1 = 1
-    // 1 + 0 = 1
-    //
-    // addr1=0;in0=0;in1=0;in2=0;in3=0; #1000
-    // if ()
 
     // Test XOR
     op=3'b010; cin = 0;
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
-            a = i;b=j;#1000
+            a=i;b=j;#1000
             if (a ^ b == out) begin
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -39,7 +30,64 @@ module testALU1bit ();
         end
     end
 
-    // Test next op...
+    // Test SLT
+    // TOOD: SLT tests
+
+    // Test AND
+    op=3'b100; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (a & b == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test NAND
+    op=3'b101; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (~(a&b) == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test NOR
+    op=3'b110; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (~(a|b) == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+    // Test OR
+    op=3'b111; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (a|b == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
 
     end
 endmodule
diff --git a/alu1bit.v b/alu1bit.v
index 66c7622..f8910a2 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -6,6 +6,8 @@
 // b011 -> SLT
 // b100 -> AND
 // b101 -> NAND
+// b110 -> NOR
+// b111 -> OR
 
 `define AND and #30
 `define OR or #30

From 39223ac978ed9d18b3eb58aabb27737abfdab6fb Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 15:32:25 -0400
Subject: [PATCH 06/52] finished adder tests

---
 alu1bit.t.v | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 9f870b4..b31c373 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -15,6 +15,30 @@ module testALU1bit ();
     op=3'b000;
     // without cin
     cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a + b == out) & (a & b == cout)) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a ^ b == out) & (a | b == cout)) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
 
     // Test XOR
     op=3'b010; cin = 0;
@@ -66,7 +90,7 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
-            if (~(a|b) == out) begin
+            if (a ~| b == out) begin
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin

From 6d6e664632586182f673fe12f9e224946be0224c Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 15:38:36 -0400
Subject: [PATCH 07/52] finished subtractor tests

---
 alu1bit.t.v | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index b31c373..d7956a1 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -40,6 +40,36 @@ module testALU1bit ();
         end
     end
 
+    // Test SUB
+    op=3'b001;
+    // without cin
+    cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a - b == out) & (a < b == cout)) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a ~^ b == out) & (a > b == cout)) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+
+
     // Test XOR
     op=3'b010; cin = 0;
     for (i=0; i<2; i=i+1) begin

From 9ca0f1ea57bcb506b7b08ef44fcbca71b3717b54 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 15:41:27 -0400
Subject: [PATCH 08/52] started counting # of passed tests

---
 alu1bit.t.v | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index d7956a1..3a7934d 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -7,6 +7,7 @@ module testALU1bit ();
   reg     a, b, cin;
   reg[2:0] op;
   integer i, j;
+  integer passed_tests;
 
   ALU1bit alu (out,cout,a,b,cin,op);
   initial begin
@@ -19,7 +20,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             if ((a + b == out) & (a & b == cout)) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -32,7 +33,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             if ((a ^ b == out) & (a | b == cout)) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -48,7 +49,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             if ((a - b == out) & (a < b == cout)) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -61,7 +62,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             if ((a ~^ b == out) & (a > b == cout)) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -76,7 +77,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             if (a ^ b == out) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);

From 6ee81ae707423b7bcaffb6d30eb61392f21fba38 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 17:36:23 -0400
Subject: [PATCH 09/52] show number of failing tests

---
 alu1bit.t.v | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 3a7934d..bf2d330 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -4,12 +4,15 @@
 
 module testALU1bit ();
   wire     out, cout;
-  reg     a, b, cin;
+  reg      a, b, cin;
   reg[2:0] op;
+
   integer i, j;
-  integer passed_tests;
+  integer passed_tests = 0;
+  integer tests = 0;
 
   ALU1bit alu (out,cout,a,b,cin,op);
+
   initial begin
 
     // Test ADD
@@ -19,6 +22,7 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if ((a + b == out) & (a & b == cout)) begin
                 passed_tests = passed_tests + 1;
             end
@@ -32,6 +36,7 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if ((a ^ b == out) & (a | b == cout)) begin
                 passed_tests = passed_tests + 1;
             end
@@ -48,6 +53,7 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if ((a - b == out) & (a < b == cout)) begin
                 passed_tests = passed_tests + 1;
             end
@@ -61,6 +67,7 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if ((a ~^ b == out) & (a > b == cout)) begin
                 passed_tests = passed_tests + 1;
             end
@@ -76,6 +83,7 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if (a ^ b == out) begin
                 passed_tests = passed_tests + 1;
             end
@@ -93,8 +101,9 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if (a & b == out) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -107,8 +116,9 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if (~(a&b) == out) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -121,8 +131,9 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if (a ~| b == out) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -135,8 +146,9 @@ module testALU1bit ();
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
+            tests = tests + 1;
             if (a|b == out) begin
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                passed_tests = passed_tests + 1;
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -144,5 +156,7 @@ module testALU1bit ();
         end
     end
 
+    $display("%2d/%2d Test Cases Passed", passed_tests, tests);
+
     end
 endmodule

From 021fab724dba56798ee9ff36cfb30316419aeadf Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 17:40:21 -0400
Subject: [PATCH 10/52] mux test

---
 alu         | 478 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 alu.v       |  35 +++-
 alu1bit.t.v | 158 +++++++++++++----
 alu1bit.v   |  60 ++++++-
 muxTest     | 101 +++++++++++
 muxTest.t.v |  24 +++
 6 files changed, 819 insertions(+), 37 deletions(-)
 create mode 100755 alu
 create mode 100755 muxTest
 create mode 100644 muxTest.t.v

diff --git a/alu b/alu
new file mode 100755
index 0000000..1421a82
--- /dev/null
+++ b/alu
@@ -0,0 +1,478 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.7 " "(v0_9_7)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x1008e10 .scope module, "testALU1bit" "testALU1bit" 2 5;
+ .timescale -9 -12;
+v0x1051f90_0 .var "a", 0 0;
+v0x1052010_0 .var "b", 0 0;
+v0x10520e0_0 .var "cin", 0 0;
+v0x10521b0_0 .net "cout", 0 0, L_0x1052ac0; 1 drivers
+v0x1052280_0 .var/i "i", 31 0;
+v0x1052300_0 .var/i "j", 31 0;
+v0x10523a0_0 .var "op", 2 0;
+RS_0x7f68d506f078 .resolv tri, L_0x1052600, L_0x10531e0, C4<z>, C4<z>;
+v0x1052470_0 .net8 "out", 0 0, RS_0x7f68d506f078; 2 drivers
+v0x1052540_0 .var/i "passed_tests", 31 0;
+S_0xfe3690 .scope module, "alu" "ALU1bit" 2 12, 3 14, S_0x1008e10;
+ .timescale -9 -12;
+L_0x1052c10 .functor XOR 1, v0x1051f90_0, v0x1052010_0, C4<0>, C4<0>;
+L_0x1052c70 .functor AND 1, v0x1051f90_0, v0x1052010_0, C4<1>, C4<1>;
+L_0x1052cf0 .functor NAND 1, v0x1051f90_0, v0x1052010_0, C4<1>, C4<1>;
+v0x1051510_0 .net *"_s3", 5 0, L_0x1052790; 1 drivers
+v0x10515b0_0 .net *"_s8", 1 0, C4<00>; 1 drivers
+v0x1051650_0 .net "a", 0 0, v0x1051f90_0; 1 drivers
+v0x1051700_0 .net "b", 0 0, v0x1052010_0; 1 drivers
+v0x10517e0_0 .net "cin", 0 0, v0x10520e0_0; 1 drivers
+v0x1051890_0 .alias "cout", 0 0, v0x10521b0_0;
+v0x1051910_0 .net "muxIn", 7 0, L_0x1053010; 1 drivers
+v0x10519c0_0 .net "op", 2 0, v0x10523a0_0; 1 drivers
+v0x1051a70_0 .alias "out", 0 0, v0x1052470_0;
+v0x1051b40_0 .net "res_ADD", 0 0, C4<z>; 0 drivers
+v0x1051c20_0 .net "res_AND", 0 0, L_0x1052c70; 1 drivers
+v0x1051ca0_0 .net "res_NAND", 0 0, L_0x1052cf0; 1 drivers
+v0x1051d90_0 .net "res_SLT", 0 0, C4<z>; 0 drivers
+v0x1051e10_0 .net "res_SUB", 0 0, C4<z>; 0 drivers
+v0x1051f10_0 .net "res_XOR", 0 0, L_0x1052c10; 1 drivers
+LS_0x1052790_0_0 .concat [ 1 1 1 1], L_0x1052cf0, L_0x1052c70, L_0x1052c10, C4<z>;
+LS_0x1052790_0_4 .concat [ 1 1 0 0], C4<z>, C4<z>;
+L_0x1052790 .concat [ 4 2 0 0], LS_0x1052790_0_0, LS_0x1052790_0_4;
+L_0x1053010 .concat [ 6 2 0 0], L_0x1052790, C4<00>;
+S_0x1050c40 .scope module, "adder" "FullAdder1Bit" 3 25, 3 63, S_0xfe3690;
+ .timescale -9 -12;
+L_0x1051bc0 .functor XOR 1, v0x1051f90_0, v0x1052010_0, C4<0>, C4<0>;
+L_0x1052600 .functor XOR 1, L_0x1051bc0, v0x10520e0_0, C4<0>, C4<0>;
+L_0x1052710 .functor AND 1, v0x1051f90_0, v0x1052010_0, C4<1>, C4<1>;
+L_0x10528b0 .functor OR 1, v0x1051f90_0, v0x1052010_0, C4<0>, C4<0>;
+L_0x1052910 .functor NOT 1, v0x10520e0_0, C4<0>, C4<0>, C4<0>;
+L_0x1052a00 .functor AND 1, L_0x1052710, L_0x1052910, C4<1>, C4<1>;
+L_0x1052a60 .functor AND 1, L_0x10528b0, v0x10520e0_0, C4<1>, C4<1>;
+L_0x1052ac0 .functor OR 1, L_0x1052a00, L_0x1052a60, C4<0>, C4<0>;
+v0x1050d30_0 .net "_carryin", 0 0, L_0x1052910; 1 drivers
+v0x1050df0_0 .alias "a", 0 0, v0x1051650_0;
+v0x1050e90_0 .net "aandb", 0 0, L_0x1052710; 1 drivers
+v0x1050f30_0 .net "aorb", 0 0, L_0x10528b0; 1 drivers
+v0x1050fe0_0 .alias "b", 0 0, v0x1051700_0;
+v0x1051080_0 .alias "carryin", 0 0, v0x10517e0_0;
+v0x1051160_0 .alias "carryout", 0 0, v0x10521b0_0;
+v0x1051200_0 .net "outputIfCarryin", 0 0, L_0x1052a00; 1 drivers
+v0x10512f0_0 .net "outputIf_Carryin", 0 0, L_0x1052a60; 1 drivers
+v0x1051390_0 .net "s", 0 0, L_0x1051bc0; 1 drivers
+v0x1051490_0 .alias "sum", 0 0, v0x1052470_0;
+S_0xfe3780 .scope module, "mux" "behavioralMultiplexer" 3 47, 3 53, S_0xfe3690;
+ .timescale -9 -12;
+v0xfe3870_0 .alias "address", 2 0, v0x10519c0_0;
+v0x1050b00_0 .alias "inputs", 7 0, v0x1051910_0;
+v0x1050ba0_0 .alias "out", 0 0, v0x1052470_0;
+L_0x10531e0 .part/v L_0x1053010, v0x10523a0_0, 1;
+    .scope S_0x1008e10;
+T_0 ;
+    %set/v v0x10523a0_0, 0, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.0 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.1, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.2 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.3, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %add 8, 9, 1;
+    %load/v 9, v0x1052470_0, 1;
+    %cmp/u 8, 9, 1;
+    %mov 8, 4, 1;
+    %load/v 9, v0x1051f90_0, 1;
+    %load/v 10, v0x1052010_0, 1;
+    %load/v 11, v0x10521b0_0, 1;
+    %cmp/u 10, 11, 1;
+    %mov 10, 4, 1;
+    %and 9, 10, 1;
+    %and 8, 9, 1;
+    %jmp/0xz  T_0.4, 8;
+    %load/v 8, v0x1052540_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1052540_0, 8, 32;
+    %jmp T_0.5;
+T_0.4 ;
+    %vpi_call 2 26 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.5 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.2;
+T_0.3 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.0;
+T_0.1 ;
+    %set/v v0x10520e0_0, 1, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.6 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.7, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.8 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.9, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1052470_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %xor 8, 9, 1;
+    %load/v 9, v0x1051f90_0, 1;
+    %load/v 10, v0x1052010_0, 1;
+    %load/v 11, v0x10521b0_0, 1;
+    %cmp/u 10, 11, 1;
+    %mov 10, 4, 1;
+    %or 9, 10, 1;
+    %and 8, 9, 1;
+    %jmp/0xz  T_0.10, 8;
+    %load/v 8, v0x1052540_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1052540_0, 8, 32;
+    %jmp T_0.11;
+T_0.10 ;
+    %vpi_call 2 39 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.11 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.8;
+T_0.9 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.6;
+T_0.7 ;
+    %movi 8, 1, 3;
+    %set/v v0x10523a0_0, 8, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.12 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.13, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.14 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.15, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %sub 8, 9, 1;
+    %load/v 9, v0x1052470_0, 1;
+    %cmp/u 8, 9, 1;
+    %mov 8, 4, 1;
+    %load/v 9, v0x1051f90_0, 1;
+    %load/v 10, v0x1052010_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 5, 1;
+    %load/v 10, v0x10521b0_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %and 8, 9, 1;
+    %jmp/0xz  T_0.16, 8;
+    %load/v 8, v0x1052540_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1052540_0, 8, 32;
+    %jmp T_0.17;
+T_0.16 ;
+    %vpi_call 2 55 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.17 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.14;
+T_0.15 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.12;
+T_0.13 ;
+    %set/v v0x10520e0_0, 1, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.18 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.19, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.20 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.21, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1052470_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %xnor 8, 9, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1051f90_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 5, 1;
+    %load/v 10, v0x10521b0_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %and 8, 9, 1;
+    %jmp/0xz  T_0.22, 8;
+    %load/v 8, v0x1052540_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1052540_0, 8, 32;
+    %jmp T_0.23;
+T_0.22 ;
+    %vpi_call 2 68 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.23 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.20;
+T_0.21 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.18;
+T_0.19 ;
+    %movi 8, 2, 3;
+    %set/v v0x10523a0_0, 8, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.24 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.25, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.26 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.27, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1052470_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %xor 8, 9, 1;
+    %jmp/0xz  T_0.28, 8;
+    %load/v 8, v0x1052540_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1052540_0, 8, 32;
+    %jmp T_0.29;
+T_0.28 ;
+    %vpi_call 2 83 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.29 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.26;
+T_0.27 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.24;
+T_0.25 ;
+    %movi 8, 4, 3;
+    %set/v v0x10523a0_0, 8, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.30 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.31, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.32 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.33, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1052470_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %and 8, 9, 1;
+    %jmp/0xz  T_0.34, 8;
+    %vpi_call 2 97 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+    %jmp T_0.35;
+T_0.34 ;
+    %vpi_call 2 100 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.35 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.32;
+T_0.33 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.30;
+T_0.31 ;
+    %movi 8, 5, 3;
+    %set/v v0x10523a0_0, 8, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.36 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.37, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.38 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.39, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %and 8, 9, 1;
+    %inv 8, 1;
+    %load/v 9, v0x1052470_0, 1;
+    %cmp/u 8, 9, 1;
+    %jmp/0xz  T_0.40, 4;
+    %vpi_call 2 111 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+    %jmp T_0.41;
+T_0.40 ;
+    %vpi_call 2 114 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.41 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.38;
+T_0.39 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.36;
+T_0.37 ;
+    %movi 8, 6, 3;
+    %set/v v0x10523a0_0, 8, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.42 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.43, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.44 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.45, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1052470_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %nor 8, 9, 1;
+    %jmp/0xz  T_0.46, 8;
+    %vpi_call 2 125 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+    %jmp T_0.47;
+T_0.46 ;
+    %vpi_call 2 128 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.47 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.44;
+T_0.45 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.42;
+T_0.43 ;
+    %set/v v0x10523a0_0, 1, 3;
+    %set/v v0x10520e0_0, 0, 1;
+    %set/v v0x1052280_0, 0, 32;
+T_0.48 ;
+    %load/v 8, v0x1052280_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.49, 5;
+    %set/v v0x1052300_0, 0, 32;
+T_0.50 ;
+    %load/v 8, v0x1052300_0, 32;
+   %cmpi/s 8, 2, 32;
+    %jmp/0xz T_0.51, 5;
+    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1051f90_0, 8, 1;
+    %load/v 8, v0x1052300_0, 32;
+    %set/v v0x1052010_0, 8, 1;
+    %delay 1000000, 0;
+    %load/v 8, v0x1051f90_0, 1;
+    %load/v 9, v0x1052010_0, 1;
+    %load/v 10, v0x1052470_0, 1;
+    %cmp/u 9, 10, 1;
+    %mov 9, 4, 1;
+    %or 8, 9, 1;
+    %jmp/0xz  T_0.52, 8;
+    %vpi_call 2 139 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+    %jmp T_0.53;
+T_0.52 ;
+    %vpi_call 2 142 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
+T_0.53 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052300_0, 32;
+    %set/v v0x1052300_0, 8, 32;
+    %jmp T_0.50;
+T_0.51 ;
+    %ix/load 0, 1, 0;
+    %load/vp0/s 8, v0x1052280_0, 32;
+    %set/v v0x1052280_0, 8, 32;
+    %jmp T_0.48;
+T_0.49 ;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "alu1bit.t.v";
+    "./alu1bit.v";
diff --git a/alu.v b/alu.v
index de280cd..61803c4 100644
--- a/alu.v
+++ b/alu.v
@@ -21,5 +21,38 @@ module ALU
   input[31:0]   operandB,
   input[2:0]    command
 );
-  // Your code here
+ 	
+  // supose we're jsut doing Addition for now
+  initial begin
+  	for (index = 0; index < 32; index = index + 1)
+  	FullAdder1Bit(result[index], carryout, operandA[index], operandB[index], carryout);
+  end
+  // TODO: XOR(overflow, carryout, )
+
+
+  // ALU1bit alu()
+  // not sure how to use this yet
 endmodule
+
+
+module ALUcontrolLUT
+(
+output reg[2:0] 	muxindex,
+output reg	invertB,
+output reg	othercontrolsignal,
+input[2:0]	ALUcommand
+)
+
+  always @(ALUcommand) begin
+    case (ALUcommand)
+      `ADD:  begin muxindex = 0; invertB=0; othercontrolsignal = ?; end    
+      `SUB:  begin muxindex = 0; invertB=1; othercontrolsignal = ?; end
+      `XOR:  begin muxindex = 1; invertB=0; othercontrolsignal = ?; end    
+      `SLT:  begin muxindex = 2; invertB=?; othercontrolsignal = ?; end
+      `AND:  begin muxindex = 3; invertB=0; othercontrolsignal = ?; end    
+      `NAND: begin muxindex = 3; invertB=0; othercontrolsignal = ?; end
+      `NOR:  begin muxindex = ?; invertB=0; othercontrolsignal = ?; end    
+      `OR:   begin muxindex = ?; invertB=0; othercontrolsignal = ?; end
+    endcase
+  end
+endmodule
\ No newline at end of file
diff --git a/alu1bit.t.v b/alu1bit.t.v
index 09b1267..bace719 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -4,57 +4,145 @@
 
 module testALU1bit ();
   wire     out, cout;
-  reg      a, b, cin;
+  reg     a, b, cin;
   reg[2:0] op;
+  integer i, j;
+  integer passed_tests;
 
   ALU1bit alu (out,cout,a,b,cin,op);
   initial begin
 
-    // $dumpfile("../resources/mux.vcd");
-    // $dumpvars;
-
     // Test ADD
     op=3'b000;
     // without cin
     cin = 0;
-    // 0 + 0 = 0
-    // 0 + 1 = 1
-    // 1 + 0 = 1
-    //
-    // addr1=0;in0=0;in1=0;in2=0;in3=0; #1000
-    // if ()
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a + b == out) & (a & b == cout)) begin
+                passed_tests = passed_tests + 1;
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a ^ b == out) & (a | b == cout)) begin
+                passed_tests = passed_tests + 1;
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
 
-    // Test XOR
-    op=3'b010; cin = 0;
-    // 0 xor 0 = 0
-    a=0;b=0; #1000
-    integer i = 0
-    for (integer i=0; i<2; i = i + 1) begin
-        $display("asdf");
+    // Test SUB
+    op=3'b001;
+    // without cin
+    cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a - b == out) & (a < b == cout)) begin
+                passed_tests = passed_tests + 1;
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
-    if (cout == 0) begin
-        $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if ((a ~^ b == out) & (a > b == cout)) begin
+                passed_tests = passed_tests + 1;
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
-    else begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+
+
+    // Test XOR
+    op=3'b010; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (a ^ b == out) begin
+                passed_tests = passed_tests + 1;
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
-    // 0 xor 1 = 1
-    a=0;b=1; #1000
-    if (cout != 1) begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+
+    // Test SLT
+    // TOOD: SLT tests
+
+    // Test AND
+    op=3'b100; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (a & b == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
-    // 1 xor 0 = 1
-    a=1;b=0; #1000
-    if (cout != 1) begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+
+    // Test NAND
+    op=3'b101; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (~(a&b) == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
-    // 1 xor 1 = 0
-    a=1;b=1; #1000
-    if (cout != 0) begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+
+    // Test NOR
+    op=3'b110; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (a ~| b == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
     end
 
-    // Test next op...
+    // Test OR
+    op=3'b111; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            if (a|b == out) begin
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
 
     end
-endmodule
+endmodule
\ No newline at end of file
diff --git a/alu1bit.v b/alu1bit.v
index 66c7622..f326833 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -20,5 +20,63 @@ module ALU1bit
   input       cin,
   input[2:0]  op
 );
-  // Your code here
+	wire res_ADD;
+	// Add
+	FullAdder1Bit adder(out, cout, a, b, cin);
+
+	// Subtract
+	wire res_SUB;
+
+	// Xor
+	wire res_XOR;
+	xor(res_XOR, a, b);
+
+	// SLT
+	wire  res_SLT;
+
+	// And
+	wire res_AND;
+	and(res_AND, a, b);
+
+	// Nand
+	wire res_NAND;
+	nand(res_NAND, a, b);
+
+	// Use a behavioral mux to select operation
+	wire[7:0] muxIn = {res_ADD, res_SUB, res_SLT, res_XOR, res_AND, res_NAND, 1'b0, 1'b0};
+	behavioralMultiplexer mux(out, op, muxIn);
+
+endmodule
+  
+
+
+module behavioralMultiplexer
+(
+    output out,
+    input[2:0] address,
+    input[7:0] inputs
+);
+    assign out = inputs[address];
+endmodule
+
+
+module FullAdder1Bit
+(
+    output sum,
+    output carryout,
+    input a,
+    input b,
+    input carryin
+);
+    wire aandb, aorb;
+    wire s, _carryin;
+    wire outputIfCarryin, outputIf_Carryin;
+    xor(s, a, b);
+    xor(sum, s, carryin);
+    and(aandb, a, b);
+    or(aorb, a, b);
+    not(_carryin, carryin);
+    and(outputIfCarryin, aandb, _carryin);
+    and(outputIf_Carryin, aorb, carryin);
+    or(carryout, outputIfCarryin, outputIf_Carryin);
 endmodule
diff --git a/muxTest b/muxTest
new file mode 100755
index 0000000..766898b
--- /dev/null
+++ b/muxTest
@@ -0,0 +1,101 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.7 " "(v0_9_7)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x19af0e0 .scope module, "ALU1bit" "ALU1bit" 2 14;
+ .timescale -9 -12;
+L_0x19d9d70 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
+L_0x19d9dd0 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
+L_0x19d9e50 .functor NAND 1, C4<z>, C4<z>, C4<1>, C4<1>;
+v0x19d8740_0 .net *"_s3", 0 0, C4<0>; 1 drivers
+v0x19d87e0_0 .net *"_s5", 0 0, C4<0>; 1 drivers
+v0x19d8880_0 .net "a", 0 0, C4<z>; 0 drivers
+v0x19d8930_0 .net "b", 0 0, C4<z>; 0 drivers
+v0x19d8a10_0 .net "cin", 0 0, C4<z>; 0 drivers
+v0x19d8ac0_0 .net "cout", 0 0, L_0x19d9c20; 1 drivers
+v0x19d8b40_0 .net "muxIn", 7 0, L_0x19d9ef0; 1 drivers
+v0x19d8bf0_0 .net "op", 2 0, C4<zzz>; 0 drivers
+RS_0x7ff07d21c078 .resolv tri, L_0x19d9710, L_0x19da1c0, C4<z>, C4<z>;
+v0x19d8ca0_0 .net8 "out", 0 0, RS_0x7ff07d21c078; 2 drivers
+v0x19d8d70_0 .net "res_ADD", 0 0, C4<z>; 0 drivers
+v0x19d8e50_0 .net "res_AND", 0 0, L_0x19d9dd0; 1 drivers
+v0x19d8ed0_0 .net "res_NAND", 0 0, L_0x19d9e50; 1 drivers
+v0x19d8fc0_0 .net "res_SLT", 0 0, C4<z>; 0 drivers
+v0x19d9040_0 .net "res_SUB", 0 0, C4<z>; 0 drivers
+v0x19d9140_0 .net "res_XOR", 0 0, L_0x19d9d70; 1 drivers
+LS_0x19d9ef0_0_0 .concat [ 1 1 1 1], C4<0>, C4<0>, L_0x19d9e50, L_0x19d9dd0;
+LS_0x19d9ef0_0_4 .concat [ 1 1 1 1], L_0x19d9d70, C4<z>, C4<z>, C4<z>;
+L_0x19d9ef0 .concat [ 4 4 0 0], LS_0x19d9ef0_0_0, LS_0x19d9ef0_0_4;
+S_0x19d7e70 .scope module, "adder" "FullAdder1Bit" 2 25, 2 63, S_0x19af0e0;
+ .timescale -9 -12;
+L_0x19d8df0 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
+L_0x19d9710 .functor XOR 1, L_0x19d8df0, C4<z>, C4<0>, C4<0>;
+L_0x19d9810 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
+L_0x19d9870 .functor OR 1, C4<z>, C4<z>, C4<0>, C4<0>;
+L_0x19d99f0 .functor NOT 1, C4<z>, C4<0>, C4<0>, C4<0>;
+L_0x19d9a50 .functor AND 1, L_0x19d9810, L_0x19d99f0, C4<1>, C4<1>;
+L_0x19d9ae0 .functor AND 1, L_0x19d9870, C4<z>, C4<1>, C4<1>;
+L_0x19d9c20 .functor OR 1, L_0x19d9a50, L_0x19d9ae0, C4<0>, C4<0>;
+v0x19d7f60_0 .net "_carryin", 0 0, L_0x19d99f0; 1 drivers
+v0x19d8020_0 .alias "a", 0 0, v0x19d8880_0;
+v0x19d80c0_0 .net "aandb", 0 0, L_0x19d9810; 1 drivers
+v0x19d8160_0 .net "aorb", 0 0, L_0x19d9870; 1 drivers
+v0x19d8210_0 .alias "b", 0 0, v0x19d8930_0;
+v0x19d82b0_0 .alias "carryin", 0 0, v0x19d8a10_0;
+v0x19d8390_0 .alias "carryout", 0 0, v0x19d8ac0_0;
+v0x19d8430_0 .net "outputIfCarryin", 0 0, L_0x19d9a50; 1 drivers
+v0x19d8520_0 .net "outputIf_Carryin", 0 0, L_0x19d9ae0; 1 drivers
+v0x19d85c0_0 .net "s", 0 0, L_0x19d8df0; 1 drivers
+v0x19d86c0_0 .alias "sum", 0 0, v0x19d8ca0_0;
+S_0x1989690 .scope module, "mux" "behavioralMultiplexer" 2 47, 2 53, S_0x19af0e0;
+ .timescale -9 -12;
+v0x1989780_0 .alias "address", 2 0, v0x19d8bf0_0;
+v0x19d7d30_0 .alias "inputs", 7 0, v0x19d8b40_0;
+v0x19d7dd0_0 .alias "out", 0 0, v0x19d8ca0_0;
+L_0x19da1c0 .part/v L_0x19d9ef0, C4<zzz>, 1;
+S_0x19aed30 .scope module, "testMultiplexer" "testMultiplexer" 3 5;
+ .timescale -9 -12;
+v0x19d9490_0 .var "address", 2 0;
+v0x19d9530_0 .var "inputs", 7 0;
+v0x19d95e0_0 .net "out", 0 0, L_0x19da2f0; 1 drivers
+S_0x19d91c0 .scope module, "mux" "behavioralMultiplexer" 3 11, 2 53, S_0x19aed30;
+ .timescale -9 -12;
+v0x19d92b0_0 .net "address", 2 0, v0x19d9490_0; 1 drivers
+v0x19d9350_0 .net "inputs", 7 0, v0x19d9530_0; 1 drivers
+v0x19d93f0_0 .alias "out", 0 0, v0x19d95e0_0;
+L_0x19da2f0 .part/v v0x19d9530_0, v0x19d9490_0, 1;
+    .scope S_0x19aed30;
+T_0 ;
+    %vpi_call 3 14 "$display", "address | inputs   | Out | Expected Output";
+    %movi 8, 1, 8;
+    %set/v v0x19d9530_0, 8, 8;
+    %set/v v0x19d9490_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 3 16 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
+    %movi 8, 4, 8;
+    %set/v v0x19d9530_0, 8, 8;
+    %movi 8, 2, 3;
+    %set/v v0x19d9490_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 3 18 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
+    %movi 8, 128, 8;
+    %set/v v0x19d9530_0, 8, 8;
+    %set/v v0x19d9490_0, 1, 3;
+    %delay 1000000, 0;
+    %vpi_call 3 20 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
+    %movi 8, 64, 8;
+    %set/v v0x19d9530_0, 8, 8;
+    %movi 8, 6, 3;
+    %set/v v0x19d9490_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 3 22 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "./alu1bit.v";
+    "muxTest.t.v";
diff --git a/muxTest.t.v b/muxTest.t.v
new file mode 100644
index 0000000..5382567
--- /dev/null
+++ b/muxTest.t.v
@@ -0,0 +1,24 @@
+// Multiplexer testbench
+`timescale 1 ns / 1 ps
+`include "alu1bit.v"
+
+module testMultiplexer ();
+  reg[2:0] address;
+  reg[7:0] inputs;
+  wire out;
+
+  //behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
+  behavioralMultiplexer mux(out, address, inputs);
+
+  initial begin
+    $display("address | inputs   | Out | Expected Output");
+    inputs=8'b00000001;address=3'b000; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    inputs=8'b00000100;address=3'b010; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    inputs=8'b10000000;address=3'b111; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    inputs=8'b01000000;address=3'b110; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+  end
+endmodule

From 362615fd3ba5bddf3b31e4bbee4d2e17b231d808 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 17:42:52 -0400
Subject: [PATCH 11/52] show passing tests

---
 alu1bit.t.v | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index bf2d330..4968fca 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -86,6 +86,7 @@ module testALU1bit ();
             tests = tests + 1;
             if (a ^ b == out) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -94,7 +95,20 @@ module testALU1bit ();
     end
 
     // Test SLT
-    // TOOD: SLT tests
+    op=3'b011; cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (a ^ b == out) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+        end
+    end
 
     // Test AND
     op=3'b100; cin = 0;
@@ -104,6 +118,7 @@ module testALU1bit ();
             tests = tests + 1;
             if (a & b == out) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -119,6 +134,7 @@ module testALU1bit ();
             tests = tests + 1;
             if (~(a&b) == out) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -134,6 +150,7 @@ module testALU1bit ();
             tests = tests + 1;
             if (a ~| b == out) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
@@ -149,6 +166,7 @@ module testALU1bit ();
             tests = tests + 1;
             if (a|b == out) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
                 $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);

From 440ab743af672c1158d672ae4c1e6d7947cad1c4 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 17:48:04 -0400
Subject: [PATCH 12/52] add better headings for tests

---
 alu1bit.t.v | 57 ++++++++++++++++++++++++++++++++---------------------
 1 file changed, 34 insertions(+), 23 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 4968fca..55b515a 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -16,6 +16,7 @@ module testALU1bit ();
   initial begin
 
     // Test ADD
+    $display("ADD:");
     op=3'b000;
     // without cin
     cin = 0;
@@ -25,9 +26,10 @@ module testALU1bit ();
             tests = tests + 1;
             if ((a + b == out) & (a & b == cout)) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
@@ -39,14 +41,16 @@ module testALU1bit ();
             tests = tests + 1;
             if ((a ^ b == out) & (a | b == cout)) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
 
     // Test SUB
+    $display("SUB:");
     op=3'b001;
     // without cin
     cin = 0;
@@ -56,9 +60,10 @@ module testALU1bit ();
             tests = tests + 1;
             if ((a - b == out) & (a < b == cout)) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
@@ -70,15 +75,17 @@ module testALU1bit ();
             tests = tests + 1;
             if ((a ~^ b == out) & (a > b == cout)) begin
                 passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
 
 
     // Test XOR
+    $display("XOR:");
     op=3'b010; cin = 0;
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
@@ -89,28 +96,29 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
 
     // Test SLT
-    op=3'b011; cin = 0;
-    for (i=0; i<2; i=i+1) begin
-        for (j=0; j<2; j=j+1) begin
-            a=i;b=j;#1000
-            tests = tests + 1;
-            if (a ^ b == out) begin
-                passed_tests = passed_tests + 1;
-                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-            end
-            else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-            end
-        end
-    end
+    // op=3'b011; cin = 0;
+    // for (i=0; i<2; i=i+1) begin
+    //     for (j=0; j<2; j=j+1) begin
+    //         a=i;b=j;#1000
+    //         tests = tests + 1;
+    //         if (a ^ b == out) begin
+    //             passed_tests = passed_tests + 1;
+    //             $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    //         end
+    //         else begin
+    //             $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    //         end
+    //     end
+    // end
 
     // Test AND
+    $display("AND:");
     op=3'b100; cin = 0;
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
@@ -121,12 +129,13 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
 
     // Test NAND
+    $display("NAND:");
     op=3'b101; cin = 0;
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
@@ -137,12 +146,13 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
 
     // Test NOR
+    $display("NOR:");
     op=3'b110; cin = 0;
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
@@ -153,12 +163,13 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end
 
     // Test OR
+    $display("OR:");
     op=3'b111; cin = 0;
     for (i=0; i<2; i=i+1) begin
         for (j=0; j<2; j=j+1) begin
@@ -169,7 +180,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
         end
     end

From 2db7967ccc1caf2830df2035ba3355f8b4bc9a5f Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 17:52:13 -0400
Subject: [PATCH 13/52] add start to end of failing tests instead of beginning

---
 alu1bit.t.v | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 55b515a..14ae6d8 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -29,8 +29,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-            end
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout); end
         end
     end
     // with cin
@@ -44,7 +43,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -63,7 +62,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -78,7 +77,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -96,7 +95,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -112,7 +111,7 @@ module testALU1bit ();
     //             $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
     //         end
     //         else begin
-    //             $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+    //             $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
     //         end
     //     end
     // end
@@ -129,7 +128,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -146,7 +145,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -163,7 +162,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end
@@ -180,7 +179,7 @@ module testALU1bit ();
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
             else begin
-                $display("*Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
             end
         end
     end

From 40cfc7c800e997f979a001907300840536dcf288 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 17:53:35 -0400
Subject: [PATCH 14/52] muxtest, 1bit

---
 alu1bit.v   | 11 +++++++++--
 muxTest.t.v |  2 ++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/alu1bit.v b/alu1bit.v
index acfc42c..5ec0a77 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -44,10 +44,17 @@ module ALU1bit
 	wire res_NAND;
 	nand(res_NAND, a, b);
 
+	// Nor
+	wire res_NOR;
+	nor(res_NOR, a, b);
+
+	// Or
+	wire res_OR;
+	or(res_OR, a, b);
+
 	// Use a behavioral mux to select operation
-	wire[7:0] muxIn = {res_ADD, res_SUB, res_SLT, res_XOR, res_AND, res_NAND, 1'b0, 1'b0};
+	wire[7:0] muxIn = {res_ADD, res_SUB, res_XOR, res_SLT, res_AND, res_NAND, res_NOR, res_OR};
 	behavioralMultiplexer mux(out, op, muxIn);
-
 endmodule
   
 
diff --git a/muxTest.t.v b/muxTest.t.v
index 5382567..9fc98d3 100644
--- a/muxTest.t.v
+++ b/muxTest.t.v
@@ -20,5 +20,7 @@ module testMultiplexer ();
     $display("%b     | %b | %b   | %b", address, inputs, out, 1);
     inputs=8'b01000000;address=3'b110; #1000
     $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    inputs=8'b00000000;address=3'b110; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
   end
 endmodule

From f444ad223a93fdca7d639a41cc99f9471c8da71f Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 17:59:21 -0400
Subject: [PATCH 15/52] fixed test bug

---
 alu1bit.t.v | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index e086705..3af3cb5 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -24,7 +24,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if ((a + b == out) & (a & b == cout)) begin
+            if (((a + b) == out) & ((a & b) == cout)) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -38,7 +38,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if ((a ^ b == out) & (a | b == cout)) begin
+            if (((a ^ b) == out) & ((a | b) == cout)) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -57,7 +57,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if ((a - b == out) & (a < b == cout)) begin
+            if (((a - b) == out) & ((a < b) == cout)) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -72,7 +72,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if ((a ~^ b == out) & (a > b == cout)) begin
+            if (((a ~^ b) == out) & ((a > b) == cout)) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -90,7 +90,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if (a ^ b == out) begin
+            if ((a ^ b) == out) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -123,7 +123,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if (a & b == out) begin
+            if ((a & b) == out) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -157,7 +157,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if (a ~| b == out) begin
+            if ((a ~| b) == out) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -174,7 +174,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if (a|b == out) begin
+            if ((a|b) == out) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end
@@ -187,4 +187,4 @@ module testALU1bit ();
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 
     end
-endmodule
\ No newline at end of file
+endmodule

From 2503416de5d4e99b1178a87e2f99152043d09660 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 17:59:43 -0400
Subject: [PATCH 16/52] none

---
 alu         | 771 ++++++++++++++++++++++++++++------------------------
 alu1bit.v   |   4 +
 muxTest.t.v |  12 +-
 3 files changed, 426 insertions(+), 361 deletions(-)

diff --git a/alu b/alu
index 1421a82..a94a866 100755
--- a/alu
+++ b/alu
@@ -4,472 +4,533 @@
 :vpi_module "system";
 :vpi_module "v2005_math";
 :vpi_module "va_math";
-S_0x1008e10 .scope module, "testALU1bit" "testALU1bit" 2 5;
+S_0x1c4bf70 .scope module, "testALU1bit" "testALU1bit" 2 5;
  .timescale -9 -12;
-v0x1051f90_0 .var "a", 0 0;
-v0x1052010_0 .var "b", 0 0;
-v0x10520e0_0 .var "cin", 0 0;
-v0x10521b0_0 .net "cout", 0 0, L_0x1052ac0; 1 drivers
-v0x1052280_0 .var/i "i", 31 0;
-v0x1052300_0 .var/i "j", 31 0;
-v0x10523a0_0 .var "op", 2 0;
-RS_0x7f68d506f078 .resolv tri, L_0x1052600, L_0x10531e0, C4<z>, C4<z>;
-v0x1052470_0 .net8 "out", 0 0, RS_0x7f68d506f078; 2 drivers
-v0x1052540_0 .var/i "passed_tests", 31 0;
-S_0xfe3690 .scope module, "alu" "ALU1bit" 2 12, 3 14, S_0x1008e10;
+v0x1c971b0_0 .var "a", 0 0;
+v0x1c97250_0 .var "b", 0 0;
+v0x1c97320_0 .var "cin", 0 0;
+v0x1c973f0_0 .net "cout", 0 0, L_0x1c97e00; 1 drivers
+v0x1c974c0_0 .var/i "i", 31 0;
+v0x1c97540_0 .var/i "j", 31 0;
+v0x1c975e0_0 .var "op", 2 0;
+RS_0x7ff5e641d078 .resolv tri, L_0x1c97940, L_0x1c984e0, C4<z>, C4<z>;
+v0x1c976b0_0 .net8 "out", 0 0, RS_0x7ff5e641d078; 2 drivers
+v0x1c97780_0 .var/i "passed_tests", 31 0;
+v0x1c97820_0 .var/i "tests", 31 0;
+S_0x1c76ae0 .scope module, "alu" "ALU1bit" 2 14, 3 16, S_0x1c4bf70;
  .timescale -9 -12;
-L_0x1052c10 .functor XOR 1, v0x1051f90_0, v0x1052010_0, C4<0>, C4<0>;
-L_0x1052c70 .functor AND 1, v0x1051f90_0, v0x1052010_0, C4<1>, C4<1>;
-L_0x1052cf0 .functor NAND 1, v0x1051f90_0, v0x1052010_0, C4<1>, C4<1>;
-v0x1051510_0 .net *"_s3", 5 0, L_0x1052790; 1 drivers
-v0x10515b0_0 .net *"_s8", 1 0, C4<00>; 1 drivers
-v0x1051650_0 .net "a", 0 0, v0x1051f90_0; 1 drivers
-v0x1051700_0 .net "b", 0 0, v0x1052010_0; 1 drivers
-v0x10517e0_0 .net "cin", 0 0, v0x10520e0_0; 1 drivers
-v0x1051890_0 .alias "cout", 0 0, v0x10521b0_0;
-v0x1051910_0 .net "muxIn", 7 0, L_0x1053010; 1 drivers
-v0x10519c0_0 .net "op", 2 0, v0x10523a0_0; 1 drivers
-v0x1051a70_0 .alias "out", 0 0, v0x1052470_0;
-v0x1051b40_0 .net "res_ADD", 0 0, C4<z>; 0 drivers
-v0x1051c20_0 .net "res_AND", 0 0, L_0x1052c70; 1 drivers
-v0x1051ca0_0 .net "res_NAND", 0 0, L_0x1052cf0; 1 drivers
-v0x1051d90_0 .net "res_SLT", 0 0, C4<z>; 0 drivers
-v0x1051e10_0 .net "res_SUB", 0 0, C4<z>; 0 drivers
-v0x1051f10_0 .net "res_XOR", 0 0, L_0x1052c10; 1 drivers
-LS_0x1052790_0_0 .concat [ 1 1 1 1], L_0x1052cf0, L_0x1052c70, L_0x1052c10, C4<z>;
-LS_0x1052790_0_4 .concat [ 1 1 0 0], C4<z>, C4<z>;
-L_0x1052790 .concat [ 4 2 0 0], LS_0x1052790_0_0, LS_0x1052790_0_4;
-L_0x1053010 .concat [ 6 2 0 0], L_0x1052790, C4<00>;
-S_0x1050c40 .scope module, "adder" "FullAdder1Bit" 3 25, 3 63, S_0xfe3690;
+L_0x1c97f00 .functor XOR 1, v0x1c971b0_0, v0x1c97250_0, C4<0>, C4<0>;
+L_0x1c97f60 .functor AND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
+L_0x1c97fe0 .functor NAND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
+L_0x1c97ad0 .functor NAND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
+L_0x1c97b30 .functor NAND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
+v0x1c96750_0 .net "a", 0 0, v0x1c971b0_0; 1 drivers
+v0x1c96800_0 .net "b", 0 0, v0x1c97250_0; 1 drivers
+v0x1c968b0_0 .net "cin", 0 0, v0x1c97320_0; 1 drivers
+v0x1c96960_0 .alias "cout", 0 0, v0x1c973f0_0;
+v0x1c96a40_0 .net "muxIn", 7 0, L_0x1c98260; 1 drivers
+v0x1c96af0_0 .net "op", 2 0, v0x1c975e0_0; 1 drivers
+v0x1c96b70_0 .alias "out", 0 0, v0x1c976b0_0;
+v0x1c96bf0_0 .net "res_ADD", 0 0, C4<z>; 0 drivers
+v0x1c96cc0_0 .net "res_AND", 0 0, L_0x1c97f60; 1 drivers
+v0x1c96d40_0 .net "res_NAND", 0 0, L_0x1c97fe0; 1 drivers
+v0x1c96e20_0 .net "res_NOR", 0 0, L_0x1c97ad0; 1 drivers
+v0x1c96ea0_0 .net "res_OR", 0 0, L_0x1c97b30; 1 drivers
+v0x1c96f90_0 .net "res_SLT", 0 0, C4<z>; 0 drivers
+v0x1c97010_0 .net "res_SUB", 0 0, C4<z>; 0 drivers
+v0x1c97110_0 .net "res_XOR", 0 0, L_0x1c97f00; 1 drivers
+LS_0x1c98260_0_0 .concat [ 1 1 1 1], L_0x1c97b30, L_0x1c97ad0, L_0x1c97fe0, L_0x1c97f60;
+LS_0x1c98260_0_4 .concat [ 1 1 1 1], L_0x1c97f00, C4<z>, C4<z>, C4<z>;
+L_0x1c98260 .concat [ 4 4 0 0], LS_0x1c98260_0_0, LS_0x1c98260_0_4;
+S_0x1c95e80 .scope module, "adder" "FullAdder1Bit" 3 27, 3 73, S_0x1c76ae0;
  .timescale -9 -12;
-L_0x1051bc0 .functor XOR 1, v0x1051f90_0, v0x1052010_0, C4<0>, C4<0>;
-L_0x1052600 .functor XOR 1, L_0x1051bc0, v0x10520e0_0, C4<0>, C4<0>;
-L_0x1052710 .functor AND 1, v0x1051f90_0, v0x1052010_0, C4<1>, C4<1>;
-L_0x10528b0 .functor OR 1, v0x1051f90_0, v0x1052010_0, C4<0>, C4<0>;
-L_0x1052910 .functor NOT 1, v0x10520e0_0, C4<0>, C4<0>, C4<0>;
-L_0x1052a00 .functor AND 1, L_0x1052710, L_0x1052910, C4<1>, C4<1>;
-L_0x1052a60 .functor AND 1, L_0x10528b0, v0x10520e0_0, C4<1>, C4<1>;
-L_0x1052ac0 .functor OR 1, L_0x1052a00, L_0x1052a60, C4<0>, C4<0>;
-v0x1050d30_0 .net "_carryin", 0 0, L_0x1052910; 1 drivers
-v0x1050df0_0 .alias "a", 0 0, v0x1051650_0;
-v0x1050e90_0 .net "aandb", 0 0, L_0x1052710; 1 drivers
-v0x1050f30_0 .net "aorb", 0 0, L_0x10528b0; 1 drivers
-v0x1050fe0_0 .alias "b", 0 0, v0x1051700_0;
-v0x1051080_0 .alias "carryin", 0 0, v0x10517e0_0;
-v0x1051160_0 .alias "carryout", 0 0, v0x10521b0_0;
-v0x1051200_0 .net "outputIfCarryin", 0 0, L_0x1052a00; 1 drivers
-v0x10512f0_0 .net "outputIf_Carryin", 0 0, L_0x1052a60; 1 drivers
-v0x1051390_0 .net "s", 0 0, L_0x1051bc0; 1 drivers
-v0x1051490_0 .alias "sum", 0 0, v0x1052470_0;
-S_0xfe3780 .scope module, "mux" "behavioralMultiplexer" 3 47, 3 53, S_0xfe3690;
+L_0x1c978c0 .functor XOR 1, v0x1c971b0_0, v0x1c97250_0, C4<0>, C4<0>;
+L_0x1c97940 .functor XOR 1, L_0x1c978c0, v0x1c97320_0, C4<0>, C4<0>;
+L_0x1c97a50 .functor AND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
+L_0x1c97bf0 .functor OR 1, v0x1c971b0_0, v0x1c97250_0, C4<0>, C4<0>;
+L_0x1c97c50 .functor NOT 1, v0x1c97320_0, C4<0>, C4<0>, C4<0>;
+L_0x1c97d40 .functor AND 1, L_0x1c97a50, L_0x1c97c50, C4<1>, C4<1>;
+L_0x1c97da0 .functor AND 1, L_0x1c97bf0, v0x1c97320_0, C4<1>, C4<1>;
+L_0x1c97e00 .functor OR 1, L_0x1c97d40, L_0x1c97da0, C4<0>, C4<0>;
+v0x1c95f70_0 .net "_carryin", 0 0, L_0x1c97c50; 1 drivers
+v0x1c96030_0 .alias "a", 0 0, v0x1c96750_0;
+v0x1c960d0_0 .net "aandb", 0 0, L_0x1c97a50; 1 drivers
+v0x1c96170_0 .net "aorb", 0 0, L_0x1c97bf0; 1 drivers
+v0x1c96220_0 .alias "b", 0 0, v0x1c96800_0;
+v0x1c962c0_0 .alias "carryin", 0 0, v0x1c968b0_0;
+v0x1c963a0_0 .alias "carryout", 0 0, v0x1c973f0_0;
+v0x1c96440_0 .net "outputIfCarryin", 0 0, L_0x1c97d40; 1 drivers
+v0x1c96530_0 .net "outputIf_Carryin", 0 0, L_0x1c97da0; 1 drivers
+v0x1c965d0_0 .net "s", 0 0, L_0x1c978c0; 1 drivers
+v0x1c966d0_0 .alias "sum", 0 0, v0x1c976b0_0;
+S_0x1c26690 .scope module, "mux" "behavioralMultiplexer" 3 57, 3 63, S_0x1c76ae0;
  .timescale -9 -12;
-v0xfe3870_0 .alias "address", 2 0, v0x10519c0_0;
-v0x1050b00_0 .alias "inputs", 7 0, v0x1051910_0;
-v0x1050ba0_0 .alias "out", 0 0, v0x1052470_0;
-L_0x10531e0 .part/v L_0x1053010, v0x10523a0_0, 1;
-    .scope S_0x1008e10;
+v0x1c76bd0_0 .alias "address", 2 0, v0x1c96af0_0;
+v0x1c95d40_0 .alias "inputs", 7 0, v0x1c96a40_0;
+v0x1c95de0_0 .alias "out", 0 0, v0x1c976b0_0;
+L_0x1c984e0 .part/v L_0x1c98260, v0x1c975e0_0, 1;
+    .scope S_0x1c4bf70;
 T_0 ;
-    %set/v v0x10523a0_0, 0, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.0 ;
-    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1c97780_0, 0, 32;
+    %end;
+    .thread T_0;
+    .scope S_0x1c4bf70;
+T_1 ;
+    %set/v v0x1c97820_0, 0, 32;
+    %end;
+    .thread T_1;
+    .scope S_0x1c4bf70;
+T_2 ;
+    %set/v v0x1c975e0_0, 0, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.0 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.1, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.2 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.1, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.2 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.3, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.3, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
     %add 8, 9, 1;
-    %load/v 9, v0x1052470_0, 1;
+    %load/v 9, v0x1c976b0_0, 1;
     %cmp/u 8, 9, 1;
     %mov 8, 4, 1;
-    %load/v 9, v0x1051f90_0, 1;
-    %load/v 10, v0x1052010_0, 1;
-    %load/v 11, v0x10521b0_0, 1;
+    %load/v 9, v0x1c971b0_0, 1;
+    %load/v 10, v0x1c97250_0, 1;
+    %load/v 11, v0x1c973f0_0, 1;
     %cmp/u 10, 11, 1;
     %mov 10, 4, 1;
     %and 9, 10, 1;
     %and 8, 9, 1;
-    %jmp/0xz  T_0.4, 8;
-    %load/v 8, v0x1052540_0, 32;
+    %jmp/0xz  T_2.4, 8;
+    %load/v 8, v0x1c97780_0, 32;
     %mov 40, 39, 1;
     %addi 8, 1, 33;
-    %set/v v0x1052540_0, 8, 32;
-    %jmp T_0.5;
-T_0.4 ;
-    %vpi_call 2 26 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.5 ;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.5;
+T_2.4 ;
+    %vpi_call 2 30 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.5 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.2;
-T_0.3 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.2;
+T_2.3 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.0;
-T_0.1 ;
-    %set/v v0x10520e0_0, 1, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.6 ;
-    %load/v 8, v0x1052280_0, 32;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.0;
+T_2.1 ;
+    %set/v v0x1c97320_0, 1, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.6 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.7, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.8 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.7, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.8 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.9, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.9, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1052470_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c976b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %xor 8, 9, 1;
-    %load/v 9, v0x1051f90_0, 1;
-    %load/v 10, v0x1052010_0, 1;
-    %load/v 11, v0x10521b0_0, 1;
+    %load/v 9, v0x1c971b0_0, 1;
+    %load/v 10, v0x1c97250_0, 1;
+    %load/v 11, v0x1c973f0_0, 1;
     %cmp/u 10, 11, 1;
     %mov 10, 4, 1;
     %or 9, 10, 1;
     %and 8, 9, 1;
-    %jmp/0xz  T_0.10, 8;
-    %load/v 8, v0x1052540_0, 32;
+    %jmp/0xz  T_2.10, 8;
+    %load/v 8, v0x1c97780_0, 32;
     %mov 40, 39, 1;
     %addi 8, 1, 33;
-    %set/v v0x1052540_0, 8, 32;
-    %jmp T_0.11;
-T_0.10 ;
-    %vpi_call 2 39 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.11 ;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.11;
+T_2.10 ;
+    %vpi_call 2 44 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.11 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.8;
-T_0.9 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.8;
+T_2.9 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.6;
-T_0.7 ;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.6;
+T_2.7 ;
     %movi 8, 1, 3;
-    %set/v v0x10523a0_0, 8, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.12 ;
-    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1c975e0_0, 8, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.12 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.13, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.14 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.13, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.14 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.15, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.15, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
     %sub 8, 9, 1;
-    %load/v 9, v0x1052470_0, 1;
+    %load/v 9, v0x1c976b0_0, 1;
     %cmp/u 8, 9, 1;
     %mov 8, 4, 1;
-    %load/v 9, v0x1051f90_0, 1;
-    %load/v 10, v0x1052010_0, 1;
+    %load/v 9, v0x1c971b0_0, 1;
+    %load/v 10, v0x1c97250_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 5, 1;
-    %load/v 10, v0x10521b0_0, 1;
+    %load/v 10, v0x1c973f0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %and 8, 9, 1;
-    %jmp/0xz  T_0.16, 8;
-    %load/v 8, v0x1052540_0, 32;
+    %jmp/0xz  T_2.16, 8;
+    %load/v 8, v0x1c97780_0, 32;
     %mov 40, 39, 1;
     %addi 8, 1, 33;
-    %set/v v0x1052540_0, 8, 32;
-    %jmp T_0.17;
-T_0.16 ;
-    %vpi_call 2 55 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.17 ;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.17;
+T_2.16 ;
+    %vpi_call 2 61 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.17 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.14;
-T_0.15 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.14;
+T_2.15 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.12;
-T_0.13 ;
-    %set/v v0x10520e0_0, 1, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.18 ;
-    %load/v 8, v0x1052280_0, 32;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.12;
+T_2.13 ;
+    %set/v v0x1c97320_0, 1, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.18 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.19, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.20 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.19, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.20 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.21, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.21, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1052470_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c976b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %xnor 8, 9, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1051f90_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c971b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 5, 1;
-    %load/v 10, v0x10521b0_0, 1;
+    %load/v 10, v0x1c973f0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %and 8, 9, 1;
-    %jmp/0xz  T_0.22, 8;
-    %load/v 8, v0x1052540_0, 32;
+    %jmp/0xz  T_2.22, 8;
+    %load/v 8, v0x1c97780_0, 32;
     %mov 40, 39, 1;
     %addi 8, 1, 33;
-    %set/v v0x1052540_0, 8, 32;
-    %jmp T_0.23;
-T_0.22 ;
-    %vpi_call 2 68 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.23 ;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.23;
+T_2.22 ;
+    %vpi_call 2 75 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.23 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.20;
-T_0.21 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.20;
+T_2.21 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.18;
-T_0.19 ;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.18;
+T_2.19 ;
     %movi 8, 2, 3;
-    %set/v v0x10523a0_0, 8, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.24 ;
-    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1c975e0_0, 8, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.24 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.25, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.26 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.25, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.26 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.27, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.27, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1052470_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c976b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %xor 8, 9, 1;
-    %jmp/0xz  T_0.28, 8;
-    %load/v 8, v0x1052540_0, 32;
+    %jmp/0xz  T_2.28, 8;
+    %load/v 8, v0x1c97780_0, 32;
     %mov 40, 39, 1;
     %addi 8, 1, 33;
-    %set/v v0x1052540_0, 8, 32;
-    %jmp T_0.29;
-T_0.28 ;
-    %vpi_call 2 83 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.29 ;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.29;
+T_2.28 ;
+    %vpi_call 2 91 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.29 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.26;
-T_0.27 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.26;
+T_2.27 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.24;
-T_0.25 ;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.24;
+T_2.25 ;
     %movi 8, 4, 3;
-    %set/v v0x10523a0_0, 8, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.30 ;
-    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1c975e0_0, 8, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.30 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.31, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.32 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.31, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.32 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.33, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.33, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1052470_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c976b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %and 8, 9, 1;
-    %jmp/0xz  T_0.34, 8;
-    %vpi_call 2 97 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-    %jmp T_0.35;
-T_0.34 ;
-    %vpi_call 2 100 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.35 ;
+    %jmp/0xz  T_2.34, 8;
+    %load/v 8, v0x1c97780_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.35;
+T_2.34 ;
+    %vpi_call 2 109 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.35 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.32;
-T_0.33 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.32;
+T_2.33 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.30;
-T_0.31 ;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.30;
+T_2.31 ;
     %movi 8, 5, 3;
-    %set/v v0x10523a0_0, 8, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.36 ;
-    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1c975e0_0, 8, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.36 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.37, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.38 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.37, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.38 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.39, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.39, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
     %and 8, 9, 1;
     %inv 8, 1;
-    %load/v 9, v0x1052470_0, 1;
+    %load/v 9, v0x1c976b0_0, 1;
     %cmp/u 8, 9, 1;
-    %jmp/0xz  T_0.40, 4;
-    %vpi_call 2 111 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-    %jmp T_0.41;
-T_0.40 ;
-    %vpi_call 2 114 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.41 ;
+    %jmp/0xz  T_2.40, 4;
+    %load/v 8, v0x1c97780_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.41;
+T_2.40 ;
+    %vpi_call 2 124 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.41 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.38;
-T_0.39 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.38;
+T_2.39 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.36;
-T_0.37 ;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.36;
+T_2.37 ;
     %movi 8, 6, 3;
-    %set/v v0x10523a0_0, 8, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.42 ;
-    %load/v 8, v0x1052280_0, 32;
+    %set/v v0x1c975e0_0, 8, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.42 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.43, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.44 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.43, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.44 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.45, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.45, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1052470_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c976b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %nor 8, 9, 1;
-    %jmp/0xz  T_0.46, 8;
-    %vpi_call 2 125 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-    %jmp T_0.47;
-T_0.46 ;
-    %vpi_call 2 128 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.47 ;
+    %jmp/0xz  T_2.46, 8;
+    %load/v 8, v0x1c97780_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.47;
+T_2.46 ;
+    %vpi_call 2 139 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.47 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.44;
-T_0.45 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.44;
+T_2.45 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.42;
-T_0.43 ;
-    %set/v v0x10523a0_0, 1, 3;
-    %set/v v0x10520e0_0, 0, 1;
-    %set/v v0x1052280_0, 0, 32;
-T_0.48 ;
-    %load/v 8, v0x1052280_0, 32;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.42;
+T_2.43 ;
+    %set/v v0x1c975e0_0, 1, 3;
+    %set/v v0x1c97320_0, 0, 1;
+    %set/v v0x1c974c0_0, 0, 32;
+T_2.48 ;
+    %load/v 8, v0x1c974c0_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.49, 5;
-    %set/v v0x1052300_0, 0, 32;
-T_0.50 ;
-    %load/v 8, v0x1052300_0, 32;
+    %jmp/0xz T_2.49, 5;
+    %set/v v0x1c97540_0, 0, 32;
+T_2.50 ;
+    %load/v 8, v0x1c97540_0, 32;
    %cmpi/s 8, 2, 32;
-    %jmp/0xz T_0.51, 5;
-    %load/v 8, v0x1052280_0, 32;
-    %set/v v0x1051f90_0, 8, 1;
-    %load/v 8, v0x1052300_0, 32;
-    %set/v v0x1052010_0, 8, 1;
+    %jmp/0xz T_2.51, 5;
+    %load/v 8, v0x1c974c0_0, 32;
+    %set/v v0x1c971b0_0, 8, 1;
+    %load/v 8, v0x1c97540_0, 32;
+    %set/v v0x1c97250_0, 8, 1;
     %delay 1000000, 0;
-    %load/v 8, v0x1051f90_0, 1;
-    %load/v 9, v0x1052010_0, 1;
-    %load/v 10, v0x1052470_0, 1;
+    %load/v 8, v0x1c97820_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97820_0, 8, 32;
+    %load/v 8, v0x1c971b0_0, 1;
+    %load/v 9, v0x1c97250_0, 1;
+    %load/v 10, v0x1c976b0_0, 1;
     %cmp/u 9, 10, 1;
     %mov 9, 4, 1;
     %or 8, 9, 1;
-    %jmp/0xz  T_0.52, 8;
-    %vpi_call 2 139 "$display", "Passed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-    %jmp T_0.53;
-T_0.52 ;
-    %vpi_call 2 142 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x10523a0_0, v0x1051f90_0, v0x1052010_0, v0x10520e0_0, v0x1052470_0, v0x10521b0_0;
-T_0.53 ;
+    %jmp/0xz  T_2.52, 8;
+    %load/v 8, v0x1c97780_0, 32;
+    %mov 40, 39, 1;
+    %addi 8, 1, 33;
+    %set/v v0x1c97780_0, 8, 32;
+    %jmp T_2.53;
+T_2.52 ;
+    %vpi_call 2 154 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
+T_2.53 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052300_0, 32;
-    %set/v v0x1052300_0, 8, 32;
-    %jmp T_0.50;
-T_0.51 ;
+    %load/vp0/s 8, v0x1c97540_0, 32;
+    %set/v v0x1c97540_0, 8, 32;
+    %jmp T_2.50;
+T_2.51 ;
     %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1052280_0, 32;
-    %set/v v0x1052280_0, 8, 32;
-    %jmp T_0.48;
-T_0.49 ;
+    %load/vp0/s 8, v0x1c974c0_0, 32;
+    %set/v v0x1c974c0_0, 8, 32;
+    %jmp T_2.48;
+T_2.49 ;
+    %vpi_call 2 159 "$display", "%2d/%2d Test Cases Passed", v0x1c97780_0, v0x1c97820_0;
     %end;
-    .thread T_0;
+    .thread T_2;
 # The file index is used to find the file name in the following table.
 :file_names 4;
     "N/A";
diff --git a/alu1bit.v b/alu1bit.v
index 5ec0a77..bde6627 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -55,10 +55,12 @@ module ALU1bit
 	// Use a behavioral mux to select operation
 	wire[7:0] muxIn = {res_ADD, res_SUB, res_XOR, res_SLT, res_AND, res_NAND, res_NOR, res_OR};
 	behavioralMultiplexer mux(out, op, muxIn);
+
 endmodule
   
 
 
+
 module behavioralMultiplexer
 (
     output out,
@@ -69,6 +71,8 @@ module behavioralMultiplexer
 endmodule
 
 
+
+
 module FullAdder1Bit
 (
     output sum,
diff --git a/muxTest.t.v b/muxTest.t.v
index 9fc98d3..7dd39ea 100644
--- a/muxTest.t.v
+++ b/muxTest.t.v
@@ -13,14 +13,14 @@ module testMultiplexer ();
   initial begin
     $display("address | inputs   | Out | Expected Output");
     inputs=8'b00000001;address=3'b000; #1000
-    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
     inputs=8'b00000100;address=3'b010; #1000
-    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
     inputs=8'b10000000;address=3'b111; #1000
-    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
     inputs=8'b01000000;address=3'b110; #1000
-    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
-    inputs=8'b00000000;address=3'b110; #1000
-    $display("%b     | %b | %b   | %b", address, inputs, out, 1);
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000000;address=3'b100; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b0);
   end
 endmodule

From 06fea069bd71e3ab5394e2148aa09ca1f154fb26 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:07:00 -0400
Subject: [PATCH 17/52] add label to truth table

---
 alu1bit.t.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 3af3cb5..833ae32 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -183,6 +183,7 @@ module testALU1bit ();
             end
         end
     end
+    $display("                  op   a  b cin|out cout ");
 
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 

From b70541eb661e1277157ebb9b54dd5b3e8eb9042e Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 18:10:30 -0400
Subject: [PATCH 18/52] cout mux

---
 alu1bit.v | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/alu1bit.v b/alu1bit.v
index bde6627..e87649c 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -23,18 +23,21 @@ module ALU1bit
   input[2:0]  op
 );
 	wire res_ADD;
+	wire cout_ADD;
 	// Add
-	FullAdder1Bit adder(out, cout, a, b, cin);
+	FullAdder1Bit adder(res_ADD, cout_ADD, a, b, cin);
 
 	// Subtract
 	wire res_SUB;
+	wire cout_SUB;
 
 	// Xor
 	wire res_XOR;
 	xor(res_XOR, a, b);
 
 	// SLT
-	wire  res_SLT;
+	wire res_SLT;
+	wire cout_SLT;
 
 	// And
 	wire res_AND;
@@ -53,8 +56,10 @@ module ALU1bit
 	or(res_OR, a, b);
 
 	// Use a behavioral mux to select operation
-	wire[7:0] muxIn = {res_ADD, res_SUB, res_XOR, res_SLT, res_AND, res_NAND, res_NOR, res_OR};
-	behavioralMultiplexer mux(out, op, muxIn);
+	wire[7:0] muxRes = {res_OR, res_NOR, res_NAND, res_AND, res_SLT, res_XOR, res_SUB, res_ADD};
+	wire[2:0] muxCout = {cout_SLT, cout_SUB, cout_ADD};
+	behavioralMultiplexer mux1(out, op, muxRes);
+	behavioralMultiplexer mux2(cout, op, muxCout);
 
 endmodule
   

From 4e59c758dfc67fa511c4155d18d4e6c056d7d668 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:12:03 -0400
Subject: [PATCH 19/52] make adder tests pass

---
 alu1bit.t.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 833ae32..a932530 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -38,7 +38,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if (((a ^ b) == out) & ((a | b) == cout)) begin
+            if (((a ~^ b) == out) & ((a | b) == cout)) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end

From 202fb192afc53059eb795aa8122c7ff36fe7e059 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:22:37 -0400
Subject: [PATCH 20/52] move mux into its own file

---
 alu1bit.v                  |  16 ++----
 muxTest.t.v => mux3bit.t.v |   4 +-
 mux3bit.v                  |   8 +++
 muxTest                    | 101 -------------------------------------
 4 files changed, 15 insertions(+), 114 deletions(-)
 rename muxTest.t.v => mux3bit.t.v (92%)
 create mode 100644 mux3bit.v
 delete mode 100755 muxTest

diff --git a/alu1bit.v b/alu1bit.v
index e87649c..5ad6478 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -9,6 +9,7 @@
 // b110 -> NOR
 // b111 -> OR
 
+`include "mux3bit.v"
 `define AND and #30
 `define OR or #30
 `define NOT not #10
@@ -58,22 +59,15 @@ module ALU1bit
 	// Use a behavioral mux to select operation
 	wire[7:0] muxRes = {res_OR, res_NOR, res_NAND, res_AND, res_SLT, res_XOR, res_SUB, res_ADD};
 	wire[2:0] muxCout = {cout_SLT, cout_SUB, cout_ADD};
-	behavioralMultiplexer mux1(out, op, muxRes);
-	behavioralMultiplexer mux2(cout, op, muxCout);
+	MUX3bit mux1(out, op, muxRes);
+	MUX3bit mux2(cout, op, muxCout);
 
 endmodule
-  
 
 
 
-module behavioralMultiplexer
-(
-    output out,
-    input[2:0] address,
-    input[7:0] inputs
-);
-    assign out = inputs[address];
-endmodule
+
+
 
 
 
diff --git a/muxTest.t.v b/mux3bit.t.v
similarity index 92%
rename from muxTest.t.v
rename to mux3bit.t.v
index 7dd39ea..0dc67c9 100644
--- a/muxTest.t.v
+++ b/mux3bit.t.v
@@ -1,6 +1,6 @@
 // Multiplexer testbench
 `timescale 1 ns / 1 ps
-`include "alu1bit.v"
+`include "mux3bit.v"
 
 module testMultiplexer ();
   reg[2:0] address;
@@ -8,7 +8,7 @@ module testMultiplexer ();
   wire out;
 
   //behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
-  behavioralMultiplexer mux(out, address, inputs);
+  MUX3bit mux(out, address, inputs);
 
   initial begin
     $display("address | inputs   | Out | Expected Output");
diff --git a/mux3bit.v b/mux3bit.v
new file mode 100644
index 0000000..f8c5a20
--- /dev/null
+++ b/mux3bit.v
@@ -0,0 +1,8 @@
+module MUX3bit
+(
+    output out,
+    input[2:0] address,
+    input[7:0] inputs
+);
+    assign out = inputs[address];
+endmodule
diff --git a/muxTest b/muxTest
deleted file mode 100755
index 766898b..0000000
--- a/muxTest
+++ /dev/null
@@ -1,101 +0,0 @@
-#! /usr/bin/vvp
-:ivl_version "0.9.7 " "(v0_9_7)";
-:vpi_time_precision - 12;
-:vpi_module "system";
-:vpi_module "v2005_math";
-:vpi_module "va_math";
-S_0x19af0e0 .scope module, "ALU1bit" "ALU1bit" 2 14;
- .timescale -9 -12;
-L_0x19d9d70 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
-L_0x19d9dd0 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
-L_0x19d9e50 .functor NAND 1, C4<z>, C4<z>, C4<1>, C4<1>;
-v0x19d8740_0 .net *"_s3", 0 0, C4<0>; 1 drivers
-v0x19d87e0_0 .net *"_s5", 0 0, C4<0>; 1 drivers
-v0x19d8880_0 .net "a", 0 0, C4<z>; 0 drivers
-v0x19d8930_0 .net "b", 0 0, C4<z>; 0 drivers
-v0x19d8a10_0 .net "cin", 0 0, C4<z>; 0 drivers
-v0x19d8ac0_0 .net "cout", 0 0, L_0x19d9c20; 1 drivers
-v0x19d8b40_0 .net "muxIn", 7 0, L_0x19d9ef0; 1 drivers
-v0x19d8bf0_0 .net "op", 2 0, C4<zzz>; 0 drivers
-RS_0x7ff07d21c078 .resolv tri, L_0x19d9710, L_0x19da1c0, C4<z>, C4<z>;
-v0x19d8ca0_0 .net8 "out", 0 0, RS_0x7ff07d21c078; 2 drivers
-v0x19d8d70_0 .net "res_ADD", 0 0, C4<z>; 0 drivers
-v0x19d8e50_0 .net "res_AND", 0 0, L_0x19d9dd0; 1 drivers
-v0x19d8ed0_0 .net "res_NAND", 0 0, L_0x19d9e50; 1 drivers
-v0x19d8fc0_0 .net "res_SLT", 0 0, C4<z>; 0 drivers
-v0x19d9040_0 .net "res_SUB", 0 0, C4<z>; 0 drivers
-v0x19d9140_0 .net "res_XOR", 0 0, L_0x19d9d70; 1 drivers
-LS_0x19d9ef0_0_0 .concat [ 1 1 1 1], C4<0>, C4<0>, L_0x19d9e50, L_0x19d9dd0;
-LS_0x19d9ef0_0_4 .concat [ 1 1 1 1], L_0x19d9d70, C4<z>, C4<z>, C4<z>;
-L_0x19d9ef0 .concat [ 4 4 0 0], LS_0x19d9ef0_0_0, LS_0x19d9ef0_0_4;
-S_0x19d7e70 .scope module, "adder" "FullAdder1Bit" 2 25, 2 63, S_0x19af0e0;
- .timescale -9 -12;
-L_0x19d8df0 .functor XOR 1, C4<z>, C4<z>, C4<0>, C4<0>;
-L_0x19d9710 .functor XOR 1, L_0x19d8df0, C4<z>, C4<0>, C4<0>;
-L_0x19d9810 .functor AND 1, C4<z>, C4<z>, C4<1>, C4<1>;
-L_0x19d9870 .functor OR 1, C4<z>, C4<z>, C4<0>, C4<0>;
-L_0x19d99f0 .functor NOT 1, C4<z>, C4<0>, C4<0>, C4<0>;
-L_0x19d9a50 .functor AND 1, L_0x19d9810, L_0x19d99f0, C4<1>, C4<1>;
-L_0x19d9ae0 .functor AND 1, L_0x19d9870, C4<z>, C4<1>, C4<1>;
-L_0x19d9c20 .functor OR 1, L_0x19d9a50, L_0x19d9ae0, C4<0>, C4<0>;
-v0x19d7f60_0 .net "_carryin", 0 0, L_0x19d99f0; 1 drivers
-v0x19d8020_0 .alias "a", 0 0, v0x19d8880_0;
-v0x19d80c0_0 .net "aandb", 0 0, L_0x19d9810; 1 drivers
-v0x19d8160_0 .net "aorb", 0 0, L_0x19d9870; 1 drivers
-v0x19d8210_0 .alias "b", 0 0, v0x19d8930_0;
-v0x19d82b0_0 .alias "carryin", 0 0, v0x19d8a10_0;
-v0x19d8390_0 .alias "carryout", 0 0, v0x19d8ac0_0;
-v0x19d8430_0 .net "outputIfCarryin", 0 0, L_0x19d9a50; 1 drivers
-v0x19d8520_0 .net "outputIf_Carryin", 0 0, L_0x19d9ae0; 1 drivers
-v0x19d85c0_0 .net "s", 0 0, L_0x19d8df0; 1 drivers
-v0x19d86c0_0 .alias "sum", 0 0, v0x19d8ca0_0;
-S_0x1989690 .scope module, "mux" "behavioralMultiplexer" 2 47, 2 53, S_0x19af0e0;
- .timescale -9 -12;
-v0x1989780_0 .alias "address", 2 0, v0x19d8bf0_0;
-v0x19d7d30_0 .alias "inputs", 7 0, v0x19d8b40_0;
-v0x19d7dd0_0 .alias "out", 0 0, v0x19d8ca0_0;
-L_0x19da1c0 .part/v L_0x19d9ef0, C4<zzz>, 1;
-S_0x19aed30 .scope module, "testMultiplexer" "testMultiplexer" 3 5;
- .timescale -9 -12;
-v0x19d9490_0 .var "address", 2 0;
-v0x19d9530_0 .var "inputs", 7 0;
-v0x19d95e0_0 .net "out", 0 0, L_0x19da2f0; 1 drivers
-S_0x19d91c0 .scope module, "mux" "behavioralMultiplexer" 3 11, 2 53, S_0x19aed30;
- .timescale -9 -12;
-v0x19d92b0_0 .net "address", 2 0, v0x19d9490_0; 1 drivers
-v0x19d9350_0 .net "inputs", 7 0, v0x19d9530_0; 1 drivers
-v0x19d93f0_0 .alias "out", 0 0, v0x19d95e0_0;
-L_0x19da2f0 .part/v v0x19d9530_0, v0x19d9490_0, 1;
-    .scope S_0x19aed30;
-T_0 ;
-    %vpi_call 3 14 "$display", "address | inputs   | Out | Expected Output";
-    %movi 8, 1, 8;
-    %set/v v0x19d9530_0, 8, 8;
-    %set/v v0x19d9490_0, 0, 3;
-    %delay 1000000, 0;
-    %vpi_call 3 16 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
-    %movi 8, 4, 8;
-    %set/v v0x19d9530_0, 8, 8;
-    %movi 8, 2, 3;
-    %set/v v0x19d9490_0, 8, 3;
-    %delay 1000000, 0;
-    %vpi_call 3 18 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
-    %movi 8, 128, 8;
-    %set/v v0x19d9530_0, 8, 8;
-    %set/v v0x19d9490_0, 1, 3;
-    %delay 1000000, 0;
-    %vpi_call 3 20 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
-    %movi 8, 64, 8;
-    %set/v v0x19d9530_0, 8, 8;
-    %movi 8, 6, 3;
-    %set/v v0x19d9490_0, 8, 3;
-    %delay 1000000, 0;
-    %vpi_call 3 22 "$display", "%b     | %b | %b   | %b", v0x19d9490_0, v0x19d9530_0, v0x19d95e0_0, 2'sb01;
-    %end;
-    .thread T_0;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "./alu1bit.v";
-    "muxTest.t.v";

From f02acaab45fdca8ff57db58711689d1e71ed60d2 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:24:40 -0400
Subject: [PATCH 21/52] move adder into its own file

---
 adder1bit.v | 20 ++++++++++++++++++++
 alu1bit.v   | 32 ++------------------------------
 2 files changed, 22 insertions(+), 30 deletions(-)
 create mode 100644 adder1bit.v

diff --git a/adder1bit.v b/adder1bit.v
new file mode 100644
index 0000000..361801e
--- /dev/null
+++ b/adder1bit.v
@@ -0,0 +1,20 @@
+module Adder1bit
+(
+    output sum,
+    output carryout,
+    input a,
+    input b,
+    input carryin
+);
+    wire aandb, aorb;
+    wire s, _carryin;
+    wire outputIfCarryin, outputIf_Carryin;
+    xor(s, a, b);
+    xor(sum, s, carryin);
+    and(aandb, a, b);
+    or(aorb, a, b);
+    not(_carryin, carryin);
+    and(outputIfCarryin, aandb, _carryin);
+    and(outputIf_Carryin, aorb, carryin);
+    or(carryout, outputIfCarryin, outputIf_Carryin);
+endmodule
diff --git a/alu1bit.v b/alu1bit.v
index 5ad6478..51e634d 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -10,6 +10,7 @@
 // b111 -> OR
 
 `include "mux3bit.v"
+`include "adder1bit.v"
 `define AND and #30
 `define OR or #30
 `define NOT not #10
@@ -26,7 +27,7 @@ module ALU1bit
 	wire res_ADD;
 	wire cout_ADD;
 	// Add
-	FullAdder1Bit adder(res_ADD, cout_ADD, a, b, cin);
+	Adder1bit adder(res_ADD, cout_ADD, a, b, cin);
 
 	// Subtract
 	wire res_SUB;
@@ -63,32 +64,3 @@ module ALU1bit
 	MUX3bit mux2(cout, op, muxCout);
 
 endmodule
-
-
-
-
-
-
-
-
-
-module FullAdder1Bit
-(
-    output sum,
-    output carryout,
-    input a,
-    input b,
-    input carryin
-);
-    wire aandb, aorb;
-    wire s, _carryin;
-    wire outputIfCarryin, outputIf_Carryin;
-    xor(s, a, b);
-    xor(sum, s, carryin);
-    and(aandb, a, b);
-    or(aorb, a, b);
-    not(_carryin, carryin);
-    and(outputIfCarryin, aandb, _carryin);
-    and(outputIf_Carryin, aorb, carryin);
-    or(carryout, outputIfCarryin, outputIf_Carryin);
-endmodule

From 9f495e658b143d9315b6c2d03ab663b87d1c6eb2 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 18:25:08 -0400
Subject: [PATCH 22/52] created subtractor1bit

---
 alu1bit.v | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/alu1bit.v b/alu1bit.v
index e87649c..18f3c58 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -30,6 +30,7 @@ module ALU1bit
 	// Subtract
 	wire res_SUB;
 	wire cout_SUB;
+	FullSubtractor1Bit subtractor(res_SUB, cout_SUB, a, b, cin);
 
 	// Xor
 	wire res_XOR;
@@ -98,3 +99,22 @@ module FullAdder1Bit
     and(outputIf_Carryin, aorb, carryin);
     or(carryout, outputIfCarryin, outputIf_Carryin);
 endmodule
+
+module FullSubtractor1Bit
+(
+    output diff,
+    output borrowout,
+    input a,
+    input b,
+    input borrowin
+);
+    wire axorb;
+    xor(axorb, a, b);
+    xor(diff, axorb, borrowin);
+    wire nota, noteaandb, notaxorb, notaxorbandborrowin;
+    not(nota, a);
+    and(notaandb, nota, b);
+    not(notaxorb, axorb);
+    and(notaxorbandborrowin, notaxorb, borrowin);
+    or(borrowout, notaandb, notaxorbandborrowin);
+endmodule
\ No newline at end of file

From d92ea2b3348c17bdc78ceee97f520ac6e1339001 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:28:19 -0400
Subject: [PATCH 23/52] fix subtractor tests

---
 alu1bit.t.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index a932530..525494c 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -72,7 +72,7 @@ module testALU1bit ();
         for (j=0; j<2; j=j+1) begin
             a=i;b=j;#1000
             tests = tests + 1;
-            if (((a ~^ b) == out) & ((a > b) == cout)) begin
+            if (((a ~^ b) == out) & ((a <= b) == cout)) begin
                 passed_tests = passed_tests + 1;
                 $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
             end

From 8de3ea699b45000a74290ce0d3c9c95259afc4ff Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 18:29:23 -0400
Subject: [PATCH 24/52] alu

---
 alu.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/alu.v b/alu.v
index f1a6b39..d821048 100644
--- a/alu.v
+++ b/alu.v
@@ -25,10 +25,11 @@ module ALU
 );
  	
   // supose we're jsut doing Addition for now
+  /*wire[31:0] cout;
   initial begin
   	for (index = 0; index < 32; index = index + 1)
-  	FullAdder1Bit(result[index], carryout, operandA[index], operandB[index], carryout);
-  end
+  		//ALU1bit(result[index], cout[index], operandA[index], operandB[index], cin //(result[index], carryout, operandA[index], operandB[index], carryout);
+  end*/
   // TODO: XOR(overflow, carryout, )
 
 

From fcb0bf8296fcbc251f91fa2631d84d913c56ce91 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 18:33:24 -0400
Subject: [PATCH 25/52] fixed cout for xor

---
 alu1bit.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/alu1bit.v b/alu1bit.v
index 7ccf91f..3e4c23f 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -60,7 +60,7 @@ module ALU1bit
 
 	// Use a behavioral mux to select operation
 	wire[7:0] muxRes = {res_OR, res_NOR, res_NAND, res_AND, res_SLT, res_XOR, res_SUB, res_ADD};
-	wire[2:0] muxCout = {cout_SLT, cout_SUB, cout_ADD};
+	wire[7:0] muxCout = {1'b0, 1'b0, 1'b0, 1'b0, cout_SLT, 1'b0, cout_SUB, cout_ADD};
 	MUX3bit mux1(out, op, muxRes);
 	MUX3bit mux2(cout, op, muxCout);
 

From f8781702d6590d21849f6d43a4aa712550e2e581 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:39:28 -0400
Subject: [PATCH 26/52] move subtractor into its own file

---
 alu1bit.v        | 22 ++--------------------
 subtractor1bit.v | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+), 20 deletions(-)
 create mode 100644 subtractor1bit.v

diff --git a/alu1bit.v b/alu1bit.v
index 3e4c23f..7848b51 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -11,6 +11,7 @@
 
 `include "mux3bit.v"
 `include "adder1bit.v"
+`include "subtractor1bit.v"
 `define AND and #30
 `define OR or #30
 `define NOT not #10
@@ -32,7 +33,7 @@ module ALU1bit
 	// Subtract
 	wire res_SUB;
 	wire cout_SUB;
-	FullSubtractor1Bit subtractor(res_SUB, cout_SUB, a, b, cin);
+	Subtractor1bit subtractor(res_SUB, cout_SUB, a, b, cin);
 
 	// Xor
 	wire res_XOR;
@@ -65,22 +66,3 @@ module ALU1bit
 	MUX3bit mux2(cout, op, muxCout);
 
 endmodule
-
-module FullSubtractor1Bit
-(
-    output diff,
-    output borrowout,
-    input a,
-    input b,
-    input borrowin
-);
-    wire axorb;
-    xor(axorb, a, b);
-    xor(diff, axorb, borrowin);
-    wire nota, noteaandb, notaxorb, notaxorbandborrowin;
-    not(nota, a);
-    and(notaandb, nota, b);
-    not(notaxorb, axorb);
-    and(notaxorbandborrowin, notaxorb, borrowin);
-    or(borrowout, notaandb, notaxorbandborrowin);
-endmodule
\ No newline at end of file
diff --git a/subtractor1bit.v b/subtractor1bit.v
new file mode 100644
index 0000000..84d2b86
--- /dev/null
+++ b/subtractor1bit.v
@@ -0,0 +1,18 @@
+module Subtractor1bit
+(
+    output diff,
+    output borrowout,
+    input a,
+    input b,
+    input borrowin
+);
+    wire axorb;
+    xor(axorb, a, b);
+    xor(diff, axorb, borrowin);
+    wire nota, noteaandb, notaxorb, notaxorbandborrowin;
+    not(nota, a);
+    and(notaandb, nota, b);
+    not(notaxorb, axorb);
+    and(notaxorbandborrowin, notaxorb, borrowin);
+    or(borrowout, notaandb, notaxorbandborrowin);
+endmodule

From 14f4ea847db1deb941631f9eeff97fee7f60a5db Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:42:23 -0400
Subject: [PATCH 27/52] add test cases for slt

---
 alu1bit.t.v | 48 +++++++++++++++++++++++++++++++++---------------
 1 file changed, 33 insertions(+), 15 deletions(-)

diff --git a/alu1bit.t.v b/alu1bit.t.v
index 525494c..4591a50 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -100,21 +100,39 @@ module testALU1bit ();
         end
     end
 
-    // Test SLT
-    // op=3'b011; cin = 0;
-    // for (i=0; i<2; i=i+1) begin
-    //     for (j=0; j<2; j=j+1) begin
-    //         a=i;b=j;#1000
-    //         tests = tests + 1;
-    //         if (a ^ b == out) begin
-    //             passed_tests = passed_tests + 1;
-    //             $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-    //         end
-    //         else begin
-    //             $display("Failed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
-    //         end
-    //     end
-    // end
+    //Test SLT
+    $display("SLT:");
+    op=3'b001;
+    // without cin
+    cin = 0;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a - b) == out) & ((a < b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
+    // with cin
+    cin = 1;
+    for (i=0; i<2; i=i+1) begin
+        for (j=0; j<2; j=j+1) begin
+            a=i;b=j;#1000
+            tests = tests + 1;
+            if (((a ~^ b) == out) & ((a <= b) == cout)) begin
+                passed_tests = passed_tests + 1;
+                $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, cin, out, cout);
+            end
+            else begin
+                $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, cin, out, cout);
+            end
+        end
+    end
 
     // Test AND
     $display("AND:");

From 6a90f8820dd16299f3f6f6aea0d56e195bb37a6b Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Mon, 9 Oct 2017 18:57:22 -0400
Subject: [PATCH 28/52] alu work

---
 alu.v       | 66 +++++++++++++++++++++++++++--------------------------
 alu1bit.t.v |  1 +
 alu1bit.v   |  1 +
 3 files changed, 36 insertions(+), 32 deletions(-)

diff --git a/alu.v b/alu.v
index d821048..74aa9ce 100644
--- a/alu.v
+++ b/alu.v
@@ -25,37 +25,39 @@ module ALU
 );
  	
   // supose we're jsut doing Addition for now
-  /*wire[31:0] cout;
-  initial begin
-  	for (index = 0; index < 32; index = index + 1)
-  		//ALU1bit(result[index], cout[index], operandA[index], operandB[index], cin //(result[index], carryout, operandA[index], operandB[index], carryout);
-  end*/
-  // TODO: XOR(overflow, carryout, )
+  wire[31:0] cout=0;
+  ALU1bit a1(result[0], cout[0], operandA[0], operandB[0], 0, op);
+  ALU1bit a2(result[1], cout[1], operandA[1], operandB[1], cout[0], op);
+  ALU1bit a3(result[2], cout[2], operandA[2], operandB[2], cout[1], op);
+  ALU1bit a4(result[3], cout[3], operandA[3], operandB[3], cout[2], op);
+  ALU1bit a5(result[4], cout[4], operandA[4], operandB[4], cout[3], op);
+  ALU1bit a6(result[5], cout[5], operandA[5], operandB[5], cout[4], op);
+  ALU1bit a7(result[6], cout[6], operandA[6], operandB[6], cout[5], op);
+  ALU1bit a8(result[7], cout[7], operandA[7], operandB[7], cout[6], op);
+  ALU1bit a9(result[8], cout[8], operandA[8], operandB[8], cout[7], op);
+  ALU1bit a10(result[9], cout[9], operandA[9], operandB[9], cout[8], op);
+  ALU1bit a11(result[10], cout[10], operandA[10], operandB[10], cout[9], op);
+  ALU1bit a12(result[11], cout[11], operandA[11], operandB[11], cout[10], op);
+  ALU1bit a13(result[12], cout[12], operandA[12], operandB[12], cout[11], op);
+  ALU1bit a14(result[13], cout[13], operandA[13], operandB[13], cout[12], op);
+  ALU1bit a15(result[14], cout[14], operandA[14], operandB[14], cout[13], op);
+  ALU1bit a16(result[15], cout[15], operandA[15], operandB[15], cout[14], op);
+  ALU1bit a17(result[16], cout[16], operandA[16], operandB[16], cout[15], op);
+  ALU1bit a18(result[17], cout[17], operandA[17], operandB[17], cout[16], op);
+  ALU1bit a19(result[18], cout[18], operandA[18], operandB[18], cout[17], op);
+  ALU1bit a20(result[19], cout[19], operandA[19], operandB[19], cout[18], op);
+  ALU1bit a21(result[20], cout[20], operandA[20], operandB[20], cout[19], op);
+  ALU1bit a22(result[21], cout[21], operandA[21], operandB[21], cout[20], op);
+  ALU1bit a23(result[22], cout[22], operandA[22], operandB[22], cout[21], op);
+  ALU1bit a24(result[23], cout[23], operandA[23], operandB[23], cout[22], op);
+  ALU1bit a25(result[24], cout[24], operandA[24], operandB[24], cout[23], op);
+  ALU1bit a26(result[25], cout[25], operandA[25], operandB[25], cout[24], op);
+  ALU1bit a27(result[26], cout[26], operandA[26], operandB[26], cout[25], op);
+  ALU1bit a28(result[27], cout[27], operandA[27], operandB[27], cout[26], op);
+  ALU1bit a29(result[28], cout[28], operandA[28], operandB[28], cout[27], op);
+  ALU1bit a30(result[29], cout[29], operandA[29], operandB[29], cout[28], op);
+  ALU1bit a31(result[30], cout[30], operandA[30], operandB[30], cout[29], op);
+  ALU1bit a32(result[31], carryout, operandA[31], operandB[31], cout[30], op);
+  xor(overflow, carryout, cout[30]);
 
-
-  // ALU1bit alu()
-  // not sure how to use this yet
-endmodule
-
-
-module ALUcontrolLUT
-(
-output reg[2:0] 	muxindex,
-output reg	invertB,
-output reg	othercontrolsignal,
-input[2:0]	ALUcommand
-)
-
-  always @(ALUcommand) begin
-    case (ALUcommand)
-      `ADD:  begin muxindex = 0; invertB=0; othercontrolsignal = ?; end    
-      `SUB:  begin muxindex = 0; invertB=1; othercontrolsignal = ?; end
-      `XOR:  begin muxindex = 1; invertB=0; othercontrolsignal = ?; end    
-      `SLT:  begin muxindex = 2; invertB=?; othercontrolsignal = ?; end
-      `AND:  begin muxindex = 3; invertB=0; othercontrolsignal = ?; end    
-      `NAND: begin muxindex = 3; invertB=0; othercontrolsignal = ?; end
-      `NOR:  begin muxindex = ?; invertB=0; othercontrolsignal = ?; end    
-      `OR:   begin muxindex = ?; invertB=0; othercontrolsignal = ?; end
-    endcase
-  end
 endmodule
\ No newline at end of file
diff --git a/alu1bit.t.v b/alu1bit.t.v
index 525494c..fbd3014 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -1,6 +1,7 @@
 // 1 Bit alu test bench
 `timescale 1 ns / 1 ps
 `include "alu1bit.v"
+`include "alu.v"
 
 module testALU1bit ();
   wire     out, cout;
diff --git a/alu1bit.v b/alu1bit.v
index 3e4c23f..64390ce 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -41,6 +41,7 @@ module ALU1bit
 	// SLT
 	wire res_SLT;
 	wire cout_SLT;
+	FullSubtractor1Bit slt(res_SUB, cout_SLT, a, b, cin);
 
 	// And
 	wire res_AND;

From 696836fab095ad8d4ecc2887a3b8994f697cb8d2 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 18:57:33 -0400
Subject: [PATCH 29/52] add initial alu test

---
 alu     | 539 --------------------------------------------------------
 alu.t.v |  35 ++++
 2 files changed, 35 insertions(+), 539 deletions(-)
 delete mode 100755 alu
 create mode 100644 alu.t.v

diff --git a/alu b/alu
deleted file mode 100755
index a94a866..0000000
--- a/alu
+++ /dev/null
@@ -1,539 +0,0 @@
-#! /usr/bin/vvp
-:ivl_version "0.9.7 " "(v0_9_7)";
-:vpi_time_precision - 12;
-:vpi_module "system";
-:vpi_module "v2005_math";
-:vpi_module "va_math";
-S_0x1c4bf70 .scope module, "testALU1bit" "testALU1bit" 2 5;
- .timescale -9 -12;
-v0x1c971b0_0 .var "a", 0 0;
-v0x1c97250_0 .var "b", 0 0;
-v0x1c97320_0 .var "cin", 0 0;
-v0x1c973f0_0 .net "cout", 0 0, L_0x1c97e00; 1 drivers
-v0x1c974c0_0 .var/i "i", 31 0;
-v0x1c97540_0 .var/i "j", 31 0;
-v0x1c975e0_0 .var "op", 2 0;
-RS_0x7ff5e641d078 .resolv tri, L_0x1c97940, L_0x1c984e0, C4<z>, C4<z>;
-v0x1c976b0_0 .net8 "out", 0 0, RS_0x7ff5e641d078; 2 drivers
-v0x1c97780_0 .var/i "passed_tests", 31 0;
-v0x1c97820_0 .var/i "tests", 31 0;
-S_0x1c76ae0 .scope module, "alu" "ALU1bit" 2 14, 3 16, S_0x1c4bf70;
- .timescale -9 -12;
-L_0x1c97f00 .functor XOR 1, v0x1c971b0_0, v0x1c97250_0, C4<0>, C4<0>;
-L_0x1c97f60 .functor AND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
-L_0x1c97fe0 .functor NAND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
-L_0x1c97ad0 .functor NAND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
-L_0x1c97b30 .functor NAND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
-v0x1c96750_0 .net "a", 0 0, v0x1c971b0_0; 1 drivers
-v0x1c96800_0 .net "b", 0 0, v0x1c97250_0; 1 drivers
-v0x1c968b0_0 .net "cin", 0 0, v0x1c97320_0; 1 drivers
-v0x1c96960_0 .alias "cout", 0 0, v0x1c973f0_0;
-v0x1c96a40_0 .net "muxIn", 7 0, L_0x1c98260; 1 drivers
-v0x1c96af0_0 .net "op", 2 0, v0x1c975e0_0; 1 drivers
-v0x1c96b70_0 .alias "out", 0 0, v0x1c976b0_0;
-v0x1c96bf0_0 .net "res_ADD", 0 0, C4<z>; 0 drivers
-v0x1c96cc0_0 .net "res_AND", 0 0, L_0x1c97f60; 1 drivers
-v0x1c96d40_0 .net "res_NAND", 0 0, L_0x1c97fe0; 1 drivers
-v0x1c96e20_0 .net "res_NOR", 0 0, L_0x1c97ad0; 1 drivers
-v0x1c96ea0_0 .net "res_OR", 0 0, L_0x1c97b30; 1 drivers
-v0x1c96f90_0 .net "res_SLT", 0 0, C4<z>; 0 drivers
-v0x1c97010_0 .net "res_SUB", 0 0, C4<z>; 0 drivers
-v0x1c97110_0 .net "res_XOR", 0 0, L_0x1c97f00; 1 drivers
-LS_0x1c98260_0_0 .concat [ 1 1 1 1], L_0x1c97b30, L_0x1c97ad0, L_0x1c97fe0, L_0x1c97f60;
-LS_0x1c98260_0_4 .concat [ 1 1 1 1], L_0x1c97f00, C4<z>, C4<z>, C4<z>;
-L_0x1c98260 .concat [ 4 4 0 0], LS_0x1c98260_0_0, LS_0x1c98260_0_4;
-S_0x1c95e80 .scope module, "adder" "FullAdder1Bit" 3 27, 3 73, S_0x1c76ae0;
- .timescale -9 -12;
-L_0x1c978c0 .functor XOR 1, v0x1c971b0_0, v0x1c97250_0, C4<0>, C4<0>;
-L_0x1c97940 .functor XOR 1, L_0x1c978c0, v0x1c97320_0, C4<0>, C4<0>;
-L_0x1c97a50 .functor AND 1, v0x1c971b0_0, v0x1c97250_0, C4<1>, C4<1>;
-L_0x1c97bf0 .functor OR 1, v0x1c971b0_0, v0x1c97250_0, C4<0>, C4<0>;
-L_0x1c97c50 .functor NOT 1, v0x1c97320_0, C4<0>, C4<0>, C4<0>;
-L_0x1c97d40 .functor AND 1, L_0x1c97a50, L_0x1c97c50, C4<1>, C4<1>;
-L_0x1c97da0 .functor AND 1, L_0x1c97bf0, v0x1c97320_0, C4<1>, C4<1>;
-L_0x1c97e00 .functor OR 1, L_0x1c97d40, L_0x1c97da0, C4<0>, C4<0>;
-v0x1c95f70_0 .net "_carryin", 0 0, L_0x1c97c50; 1 drivers
-v0x1c96030_0 .alias "a", 0 0, v0x1c96750_0;
-v0x1c960d0_0 .net "aandb", 0 0, L_0x1c97a50; 1 drivers
-v0x1c96170_0 .net "aorb", 0 0, L_0x1c97bf0; 1 drivers
-v0x1c96220_0 .alias "b", 0 0, v0x1c96800_0;
-v0x1c962c0_0 .alias "carryin", 0 0, v0x1c968b0_0;
-v0x1c963a0_0 .alias "carryout", 0 0, v0x1c973f0_0;
-v0x1c96440_0 .net "outputIfCarryin", 0 0, L_0x1c97d40; 1 drivers
-v0x1c96530_0 .net "outputIf_Carryin", 0 0, L_0x1c97da0; 1 drivers
-v0x1c965d0_0 .net "s", 0 0, L_0x1c978c0; 1 drivers
-v0x1c966d0_0 .alias "sum", 0 0, v0x1c976b0_0;
-S_0x1c26690 .scope module, "mux" "behavioralMultiplexer" 3 57, 3 63, S_0x1c76ae0;
- .timescale -9 -12;
-v0x1c76bd0_0 .alias "address", 2 0, v0x1c96af0_0;
-v0x1c95d40_0 .alias "inputs", 7 0, v0x1c96a40_0;
-v0x1c95de0_0 .alias "out", 0 0, v0x1c976b0_0;
-L_0x1c984e0 .part/v L_0x1c98260, v0x1c975e0_0, 1;
-    .scope S_0x1c4bf70;
-T_0 ;
-    %set/v v0x1c97780_0, 0, 32;
-    %end;
-    .thread T_0;
-    .scope S_0x1c4bf70;
-T_1 ;
-    %set/v v0x1c97820_0, 0, 32;
-    %end;
-    .thread T_1;
-    .scope S_0x1c4bf70;
-T_2 ;
-    %set/v v0x1c975e0_0, 0, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.0 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.1, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.2 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.3, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %add 8, 9, 1;
-    %load/v 9, v0x1c976b0_0, 1;
-    %cmp/u 8, 9, 1;
-    %mov 8, 4, 1;
-    %load/v 9, v0x1c971b0_0, 1;
-    %load/v 10, v0x1c97250_0, 1;
-    %load/v 11, v0x1c973f0_0, 1;
-    %cmp/u 10, 11, 1;
-    %mov 10, 4, 1;
-    %and 9, 10, 1;
-    %and 8, 9, 1;
-    %jmp/0xz  T_2.4, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.5;
-T_2.4 ;
-    %vpi_call 2 30 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.5 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.2;
-T_2.3 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.0;
-T_2.1 ;
-    %set/v v0x1c97320_0, 1, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.6 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.7, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.8 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.9, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c976b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %xor 8, 9, 1;
-    %load/v 9, v0x1c971b0_0, 1;
-    %load/v 10, v0x1c97250_0, 1;
-    %load/v 11, v0x1c973f0_0, 1;
-    %cmp/u 10, 11, 1;
-    %mov 10, 4, 1;
-    %or 9, 10, 1;
-    %and 8, 9, 1;
-    %jmp/0xz  T_2.10, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.11;
-T_2.10 ;
-    %vpi_call 2 44 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.11 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.8;
-T_2.9 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.6;
-T_2.7 ;
-    %movi 8, 1, 3;
-    %set/v v0x1c975e0_0, 8, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.12 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.13, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.14 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.15, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %sub 8, 9, 1;
-    %load/v 9, v0x1c976b0_0, 1;
-    %cmp/u 8, 9, 1;
-    %mov 8, 4, 1;
-    %load/v 9, v0x1c971b0_0, 1;
-    %load/v 10, v0x1c97250_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 5, 1;
-    %load/v 10, v0x1c973f0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %and 8, 9, 1;
-    %jmp/0xz  T_2.16, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.17;
-T_2.16 ;
-    %vpi_call 2 61 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.17 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.14;
-T_2.15 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.12;
-T_2.13 ;
-    %set/v v0x1c97320_0, 1, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.18 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.19, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.20 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.21, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c976b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %xnor 8, 9, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c971b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 5, 1;
-    %load/v 10, v0x1c973f0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %and 8, 9, 1;
-    %jmp/0xz  T_2.22, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.23;
-T_2.22 ;
-    %vpi_call 2 75 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.23 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.20;
-T_2.21 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.18;
-T_2.19 ;
-    %movi 8, 2, 3;
-    %set/v v0x1c975e0_0, 8, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.24 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.25, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.26 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.27, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c976b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %xor 8, 9, 1;
-    %jmp/0xz  T_2.28, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.29;
-T_2.28 ;
-    %vpi_call 2 91 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.29 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.26;
-T_2.27 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.24;
-T_2.25 ;
-    %movi 8, 4, 3;
-    %set/v v0x1c975e0_0, 8, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.30 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.31, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.32 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.33, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c976b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %and 8, 9, 1;
-    %jmp/0xz  T_2.34, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.35;
-T_2.34 ;
-    %vpi_call 2 109 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.35 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.32;
-T_2.33 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.30;
-T_2.31 ;
-    %movi 8, 5, 3;
-    %set/v v0x1c975e0_0, 8, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.36 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.37, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.38 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.39, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %and 8, 9, 1;
-    %inv 8, 1;
-    %load/v 9, v0x1c976b0_0, 1;
-    %cmp/u 8, 9, 1;
-    %jmp/0xz  T_2.40, 4;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.41;
-T_2.40 ;
-    %vpi_call 2 124 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.41 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.38;
-T_2.39 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.36;
-T_2.37 ;
-    %movi 8, 6, 3;
-    %set/v v0x1c975e0_0, 8, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.42 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.43, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.44 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.45, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c976b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %nor 8, 9, 1;
-    %jmp/0xz  T_2.46, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.47;
-T_2.46 ;
-    %vpi_call 2 139 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.47 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.44;
-T_2.45 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.42;
-T_2.43 ;
-    %set/v v0x1c975e0_0, 1, 3;
-    %set/v v0x1c97320_0, 0, 1;
-    %set/v v0x1c974c0_0, 0, 32;
-T_2.48 ;
-    %load/v 8, v0x1c974c0_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.49, 5;
-    %set/v v0x1c97540_0, 0, 32;
-T_2.50 ;
-    %load/v 8, v0x1c97540_0, 32;
-   %cmpi/s 8, 2, 32;
-    %jmp/0xz T_2.51, 5;
-    %load/v 8, v0x1c974c0_0, 32;
-    %set/v v0x1c971b0_0, 8, 1;
-    %load/v 8, v0x1c97540_0, 32;
-    %set/v v0x1c97250_0, 8, 1;
-    %delay 1000000, 0;
-    %load/v 8, v0x1c97820_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97820_0, 8, 32;
-    %load/v 8, v0x1c971b0_0, 1;
-    %load/v 9, v0x1c97250_0, 1;
-    %load/v 10, v0x1c976b0_0, 1;
-    %cmp/u 9, 10, 1;
-    %mov 9, 4, 1;
-    %or 8, 9, 1;
-    %jmp/0xz  T_2.52, 8;
-    %load/v 8, v0x1c97780_0, 32;
-    %mov 40, 39, 1;
-    %addi 8, 1, 33;
-    %set/v v0x1c97780_0, 8, 32;
-    %jmp T_2.53;
-T_2.52 ;
-    %vpi_call 2 154 "$display", "Failed test with: %b  %b  %b  %b | %b  %b", v0x1c975e0_0, v0x1c971b0_0, v0x1c97250_0, v0x1c97320_0, v0x1c976b0_0, v0x1c973f0_0;
-T_2.53 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c97540_0, 32;
-    %set/v v0x1c97540_0, 8, 32;
-    %jmp T_2.50;
-T_2.51 ;
-    %ix/load 0, 1, 0;
-    %load/vp0/s 8, v0x1c974c0_0, 32;
-    %set/v v0x1c974c0_0, 8, 32;
-    %jmp T_2.48;
-T_2.49 ;
-    %vpi_call 2 159 "$display", "%2d/%2d Test Cases Passed", v0x1c97780_0, v0x1c97820_0;
-    %end;
-    .thread T_2;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "alu1bit.t.v";
-    "./alu1bit.v";
diff --git a/alu.t.v b/alu.t.v
new file mode 100644
index 0000000..afe24e7
--- /dev/null
+++ b/alu.t.v
@@ -0,0 +1,35 @@
+// 1 Bit alu test bench
+`timescale 1 ns / 1 ps
+`include "alu.v"
+
+module testALU ();
+  wire[31:0] out, a, b;
+  reg        zero, overflow, cout;
+  reg[2:0]   op;
+
+  integer passed_tests = 0;
+  integer tests = 0;
+
+  ALU alu (out,cout,zero,overflow,a,b,op);
+
+  initial begin
+
+
+    // Test XOR
+    op=3'b010
+    a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000000;#1000
+    tests = tests + 1;
+    $display("                  op   a  b cin|out cout ");
+    if ((a ^ b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, out, cout);
+    end
+    else begin
+        $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, out, cout);
+    end
+
+
+    $display("%2d/%2d Test Cases Passed", passed_tests, tests);
+
+    end
+endmodule

From 7104aad938fe5ed4807676eb2b420412b6159803 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 19:02:02 -0400
Subject: [PATCH 30/52] integrated initial alu code

---
 alu.t.v   | 6 +++---
 alu.v     | 5 +++--
 alu1bit.v | 2 +-
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index afe24e7..13f608c 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -16,16 +16,16 @@ module testALU ();
 
 
     // Test XOR
-    op=3'b010
+    op=3'b010;
     a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000000;#1000
     tests = tests + 1;
     $display("                  op   a  b cin|out cout ");
     if ((a ^ b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with: %b  %b  %b  %b | %b  %b", op, a, b, out, cout);
+        $display("Passed test with: %b  %b  %b | %b  %b", op, a, b, out, cout);
     end
     else begin
-        $display("Failed test with: %b  %b  %b  %b | %b  %b*", op, a, b, out, cout);
+        $display("Failed test with: %b  %b  %b | %b  %b*", op, a, b, out, cout);
     end
 
 
diff --git a/alu.v b/alu.v
index 74aa9ce..9881a36 100644
--- a/alu.v
+++ b/alu.v
@@ -9,6 +9,7 @@
 // b110 -> NOR
 // b111 -> OR
 
+`include "alu1bit.v"
 `define AND and #30
 `define OR or #30
 `define NOT not #10
@@ -23,7 +24,7 @@ module ALU
   input[31:0]   operandB,
   input[2:0]    command
 );
- 	
+
   // supose we're jsut doing Addition for now
   wire[31:0] cout=0;
   ALU1bit a1(result[0], cout[0], operandA[0], operandB[0], 0, op);
@@ -60,4 +61,4 @@ module ALU
   ALU1bit a32(result[31], carryout, operandA[31], operandB[31], cout[30], op);
   xor(overflow, carryout, cout[30]);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/alu1bit.v b/alu1bit.v
index 3322fb5..d6f9f00 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -42,7 +42,7 @@ module ALU1bit
 	// SLT
 	wire res_SLT;
 	wire cout_SLT;
-	FullSubtractor1Bit slt(res_SUB, cout_SLT, a, b, cin);
+	Subtractor1bit slt(res_SUB, cout_SLT, a, b, cin);
 
 	// And
 	wire res_AND;

From 040f39c36a171571834686369e257c018ec64e02 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 19:07:51 -0400
Subject: [PATCH 31/52] fixed issue where we used op instead of command

---
 alu.v | 64 +++++++++++++++++++++++++++++------------------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/alu.v b/alu.v
index 9881a36..fa5d759 100644
--- a/alu.v
+++ b/alu.v
@@ -27,38 +27,38 @@ module ALU
 
   // supose we're jsut doing Addition for now
   wire[31:0] cout=0;
-  ALU1bit a1(result[0], cout[0], operandA[0], operandB[0], 0, op);
-  ALU1bit a2(result[1], cout[1], operandA[1], operandB[1], cout[0], op);
-  ALU1bit a3(result[2], cout[2], operandA[2], operandB[2], cout[1], op);
-  ALU1bit a4(result[3], cout[3], operandA[3], operandB[3], cout[2], op);
-  ALU1bit a5(result[4], cout[4], operandA[4], operandB[4], cout[3], op);
-  ALU1bit a6(result[5], cout[5], operandA[5], operandB[5], cout[4], op);
-  ALU1bit a7(result[6], cout[6], operandA[6], operandB[6], cout[5], op);
-  ALU1bit a8(result[7], cout[7], operandA[7], operandB[7], cout[6], op);
-  ALU1bit a9(result[8], cout[8], operandA[8], operandB[8], cout[7], op);
-  ALU1bit a10(result[9], cout[9], operandA[9], operandB[9], cout[8], op);
-  ALU1bit a11(result[10], cout[10], operandA[10], operandB[10], cout[9], op);
-  ALU1bit a12(result[11], cout[11], operandA[11], operandB[11], cout[10], op);
-  ALU1bit a13(result[12], cout[12], operandA[12], operandB[12], cout[11], op);
-  ALU1bit a14(result[13], cout[13], operandA[13], operandB[13], cout[12], op);
-  ALU1bit a15(result[14], cout[14], operandA[14], operandB[14], cout[13], op);
-  ALU1bit a16(result[15], cout[15], operandA[15], operandB[15], cout[14], op);
-  ALU1bit a17(result[16], cout[16], operandA[16], operandB[16], cout[15], op);
-  ALU1bit a18(result[17], cout[17], operandA[17], operandB[17], cout[16], op);
-  ALU1bit a19(result[18], cout[18], operandA[18], operandB[18], cout[17], op);
-  ALU1bit a20(result[19], cout[19], operandA[19], operandB[19], cout[18], op);
-  ALU1bit a21(result[20], cout[20], operandA[20], operandB[20], cout[19], op);
-  ALU1bit a22(result[21], cout[21], operandA[21], operandB[21], cout[20], op);
-  ALU1bit a23(result[22], cout[22], operandA[22], operandB[22], cout[21], op);
-  ALU1bit a24(result[23], cout[23], operandA[23], operandB[23], cout[22], op);
-  ALU1bit a25(result[24], cout[24], operandA[24], operandB[24], cout[23], op);
-  ALU1bit a26(result[25], cout[25], operandA[25], operandB[25], cout[24], op);
-  ALU1bit a27(result[26], cout[26], operandA[26], operandB[26], cout[25], op);
-  ALU1bit a28(result[27], cout[27], operandA[27], operandB[27], cout[26], op);
-  ALU1bit a29(result[28], cout[28], operandA[28], operandB[28], cout[27], op);
-  ALU1bit a30(result[29], cout[29], operandA[29], operandB[29], cout[28], op);
-  ALU1bit a31(result[30], cout[30], operandA[30], operandB[30], cout[29], op);
-  ALU1bit a32(result[31], carryout, operandA[31], operandB[31], cout[30], op);
+  ALU1bit a1(result[0], cout[0], operandA[0], operandB[0], 0, command);
+  ALU1bit a2(result[1], cout[1], operandA[1], operandB[1], cout[0], command);
+  ALU1bit a3(result[2], cout[2], operandA[2], operandB[2], cout[1], command);
+  ALU1bit a4(result[3], cout[3], operandA[3], operandB[3], cout[2], command);
+  ALU1bit a5(result[4], cout[4], operandA[4], operandB[4], cout[3], command);
+  ALU1bit a6(result[5], cout[5], operandA[5], operandB[5], cout[4], command);
+  ALU1bit a7(result[6], cout[6], operandA[6], operandB[6], cout[5], command);
+  ALU1bit a8(result[7], cout[7], operandA[7], operandB[7], cout[6], command);
+  ALU1bit a9(result[8], cout[8], operandA[8], operandB[8], cout[7], command);
+  ALU1bit a10(result[9], cout[9], operandA[9], operandB[9], cout[8], command);
+  ALU1bit a11(result[10], cout[10], operandA[10], operandB[10], cout[9], command);
+  ALU1bit a12(result[11], cout[11], operandA[11], operandB[11], cout[10], command);
+  ALU1bit a13(result[12], cout[12], operandA[12], operandB[12], cout[11], command);
+  ALU1bit a14(result[13], cout[13], operandA[13], operandB[13], cout[12], command);
+  ALU1bit a15(result[14], cout[14], operandA[14], operandB[14], cout[13], command);
+  ALU1bit a16(result[15], cout[15], operandA[15], operandB[15], cout[14], command);
+  ALU1bit a17(result[16], cout[16], operandA[16], operandB[16], cout[15], command);
+  ALU1bit a18(result[17], cout[17], operandA[17], operandB[17], cout[16], command);
+  ALU1bit a19(result[18], cout[18], operandA[18], operandB[18], cout[17], command);
+  ALU1bit a20(result[19], cout[19], operandA[19], operandB[19], cout[18], command);
+  ALU1bit a21(result[20], cout[20], operandA[20], operandB[20], cout[19], command);
+  ALU1bit a22(result[21], cout[21], operandA[21], operandB[21], cout[20], command);
+  ALU1bit a23(result[22], cout[22], operandA[22], operandB[22], cout[21], command);
+  ALU1bit a24(result[23], cout[23], operandA[23], operandB[23], cout[22], command);
+  ALU1bit a25(result[24], cout[24], operandA[24], operandB[24], cout[23], command);
+  ALU1bit a26(result[25], cout[25], operandA[25], operandB[25], cout[24], command);
+  ALU1bit a27(result[26], cout[26], operandA[26], operandB[26], cout[25], command);
+  ALU1bit a28(result[27], cout[27], operandA[27], operandB[27], cout[26], command);
+  ALU1bit a29(result[28], cout[28], operandA[28], operandB[28], cout[27], command);
+  ALU1bit a30(result[29], cout[29], operandA[29], operandB[29], cout[28], command);
+  ALU1bit a31(result[30], cout[30], operandA[30], operandB[30], cout[29], command);
+  ALU1bit a32(result[31], carryout, operandA[31], operandB[31], cout[30], command);
   xor(overflow, carryout, cout[30]);
 
 endmodule

From 6842860bb7a1c058d65faa077b4d1325de339045 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 19:10:23 -0400
Subject: [PATCH 32/52] fixed wire err

---
 alu.t.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index 13f608c..eb1beea 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -3,8 +3,9 @@
 `include "alu.v"
 
 module testALU ();
-  wire[31:0] out, a, b;
-  reg        zero, overflow, cout;
+  wire[31:0] out;
+  wire       zero, overflow, cout;
+  reg[31:0]  a, b;
   reg[2:0]   op;
 
   integer passed_tests = 0;

From f74d23e204dabe4205d5ce11cc5967243591e831 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Mon, 9 Oct 2017 19:17:43 -0400
Subject: [PATCH 33/52] added an slt case

---
 alu.t.v | 30 ++++++++++++++++++++++++++----
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index eb1beea..c3af76a 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -18,15 +18,37 @@ module testALU ();
 
     // Test XOR
     op=3'b010;
-    a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000000;#1000
+    a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#1000
     tests = tests + 1;
-    $display("                  op   a  b cin|out cout ");
     if ((a ^ b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with: %b  %b  %b | %b  %b", op, a, b, out, cout);
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
     end
     else begin
-        $display("Failed test with: %b  %b  %b | %b  %b*", op, a, b, out, cout);
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+    end
+    // Test SLT
+    op=3'b011;
+    a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
+    tests = tests + 1;
+    if ((a < b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
     end
 
 

From 4d71756a8817b71ac1052cc242e0dfc30ab40356 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 09:58:02 -0400
Subject: [PATCH 34/52] made testing code a bit simpler

---
 alu.t.v | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index c3af76a..bcbb8ff 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -23,16 +23,14 @@ module testALU ();
     if ((a ^ b) == out) begin
         passed_tests = passed_tests + 1;
         $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
     end
     else begin
         $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
     end
+    $display("a:   %b", a);
+    $display("b:   %b", b);
+    $display("out: %b", out);
+    
     // Test SLT
     op=3'b011;
     a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
@@ -40,16 +38,13 @@ module testALU ();
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
         $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
     end
     else begin
         $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
     end
+    $display("a:   %b", a);
+    $display("b:   %b", b);
+    $display("out: %b", out);
 
 
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);

From 4c0fcb15f5252d852bd41ca87018a23aef5df3f5 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 10:12:19 -0400
Subject: [PATCH 35/52] added more slt tests

---
 alu.t.v | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/alu.t.v b/alu.t.v
index bcbb8ff..d27fc2f 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -30,9 +30,10 @@ module testALU ();
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
-    
+
     // Test SLT
     op=3'b011;
+    // SLT(a,b) = 1 where a<b
     a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
     if ((a < b) == out) begin
@@ -45,6 +46,58 @@ module testALU ();
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
+    // SLT(a,b) = 0 where a>b
+    a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
+    tests = tests + 1;
+    if ((a < b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+    end
+    $display("a:   %b", a);
+    $display("b:   %b", b);
+    $display("out: %b", out);
+    // SLT(a,b) = 1 where a(is negative)<b(is positive)
+    a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
+    tests = tests + 1;
+    if ((a < b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+    end
+    $display("a:   %b", a);
+    $display("b:   %b", b);
+    $display("out: %b", out);
+    // SLT(a,b) = 0 where a(is positive)>b(is negative)
+    a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
+    tests = tests + 1;
+    if ((a < b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+    end
+    $display("a:   %b", a);
+    $display("b:   %b", b);
+    $display("out: %b", out);
+    // SLT(a,b) = 1 where a(is negative)>b(is negative)
+    a=32'b10000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
+    tests = tests + 1;
+    if ((a < b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+    end
+    $display("a:   %b", a);
+    $display("b:   %b", b);
+    $display("out: %b", out);
 
 
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);

From 7871db87e0e0737881e2215576fb334c28d4ad06 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Tue, 10 Oct 2017 10:12:25 -0400
Subject: [PATCH 36/52] adding test cases

---
 alu.t.v       | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++
 alu.v         |  2 +-
 alu1bit.v     |  2 +-
 mux32to1by1.v | 37 +++++++++++++++++++++++++++++++
 4 files changed, 99 insertions(+), 2 deletions(-)
 create mode 100644 mux32to1by1.v

diff --git a/alu.t.v b/alu.t.v
index c3af76a..069dfc6 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -16,7 +16,67 @@ module testALU ();
   initial begin
 
 
+
+    // Test Add
+    $display("Addition");
+    $display("-----------------------------------------------------------------");
+    op=3'b000;
+    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
+    tests = tests + 1;
+    if ((a + b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+    end
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
+    tests = tests + 1;
+    if ((a + b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+    end
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000001;#1000
+    tests = tests + 1;
+    if ((a + b) == out) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+    end
+
+
     // Test XOR
+    $display("XOR");
+    $display("-----------------------------------------------------------------");
     op=3'b010;
     a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#1000
     tests = tests + 1;
diff --git a/alu.v b/alu.v
index fa5d759..04b7b44 100644
--- a/alu.v
+++ b/alu.v
@@ -26,7 +26,7 @@ module ALU
 );
 
   // supose we're jsut doing Addition for now
-  wire[31:0] cout=0;
+  wire[31:0] cout;
   ALU1bit a1(result[0], cout[0], operandA[0], operandB[0], 0, command);
   ALU1bit a2(result[1], cout[1], operandA[1], operandB[1], cout[0], command);
   ALU1bit a3(result[2], cout[2], operandA[2], operandB[2], cout[1], command);
diff --git a/alu1bit.v b/alu1bit.v
index d6f9f00..31d059d 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -25,9 +25,9 @@ module ALU1bit
   input       cin,
   input[2:0]  op
 );
+	// Add
 	wire res_ADD;
 	wire cout_ADD;
-	// Add
 	Adder1bit adder(res_ADD, cout_ADD, a, b, cin);
 
 	// Subtract
diff --git a/mux32to1by1.v b/mux32to1by1.v
new file mode 100644
index 0000000..a2d40da
--- /dev/null
+++ b/mux32to1by1.v
@@ -0,0 +1,37 @@
+// 32 bit mux
+module mux32to1by1
+(
+output      out,
+input[4:0]  address,
+input[31:0] inputs
+);
+  assign out = inputs[address];
+endmodule
+
+
+// 32x32bit mux
+module mux32to1by32
+(
+output[31:0]  out,
+input[4:0]    address,
+input[31:0]   inputs
+);
+
+  wire[31:0] mux[31:0];			// Create a 2D array of wires
+  assign mux[0] = inputs[0];		// Connect the sources of the array
+  for (i=0;i<32;i=i+1) begin
+  	mux[i]=inputs[i];
+  end
+  assign out = mux[address];	// Connect the output of the array
+endmodule
+
+
+// 32 bit decoder
+module decoder1to32
+(
+output[31:0]  out,
+input         enable,
+input[4:0]    address
+);
+    assign out = enable<<address; 
+endmodule
\ No newline at end of file

From 5a0de31772befe79c7430af2ab89df421c7c8e7b Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 10:18:05 -0400
Subject: [PATCH 37/52] display op first for some tests

---
 alu.t.v | 32 ++++++++++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index 79371c2..7d4a3e5 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -18,7 +18,7 @@ module testALU ();
 
 
     // Test Add
-    $display("Addition");
+    $display("\nAddition");
     $display("-----------------------------------------------------------------");
     op=3'b000;
     a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
@@ -75,33 +75,37 @@ module testALU ();
 
 
     // Test XOR
-    $display("XOR");
+    $display("\nXOR");
     $display("-----------------------------------------------------------------");
     op=3'b010;
+    $display("op: %b", op);
     a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#1000
     tests = tests + 1;
     if ((a ^ b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
+        $display("Passed test with:");
     end
     else begin
-        $display("Failed test with op: %b", op);
+        $display("Failed test with:");
     end
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
 
     // Test SLT
+    $display("\nSLT");
+    $display("-----------------------------------------------------------------");
     op=3'b011;
+    $display("op: %b", op);
     // SLT(a,b) = 1 where a<b
     a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
+        $display("Passed test with:");
     end
     else begin
-        $display("Failed test with op: %b", op);
+        $display("Failed test with:");
     end
     $display("a:   %b", a);
     $display("b:   %b", b);
@@ -111,10 +115,10 @@ module testALU ();
     tests = tests + 1;
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
+        $display("Passed test with:");
     end
     else begin
-        $display("Failed test with op: %b", op);
+        $display("Failed test with:");
     end
     $display("a:   %b", a);
     $display("b:   %b", b);
@@ -124,10 +128,10 @@ module testALU ();
     tests = tests + 1;
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
+        $display("Passed test with:");
     end
     else begin
-        $display("Failed test with op: %b", op);
+        $display("Failed test with:");
     end
     $display("a:   %b", a);
     $display("b:   %b", b);
@@ -137,10 +141,10 @@ module testALU ();
     tests = tests + 1;
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
+        $display("Passed test with:");
     end
     else begin
-        $display("Failed test with op: %b", op);
+        $display("Failed test with:");
     end
     $display("a:   %b", a);
     $display("b:   %b", b);
@@ -150,10 +154,10 @@ module testALU ();
     tests = tests + 1;
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
+        $display("Passed test with:");
     end
     else begin
-        $display("Failed test with op: %b", op);
+        $display("Failed test with:");
     end
     $display("a:   %b", a);
     $display("b:   %b", b);

From 58280075175a80248cd058a1f5598e2ae27aea07 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 10:44:28 -0400
Subject: [PATCH 38/52] made test case into function

---
 alu.t.v | 91 ++++++++++++++++++---------------------------------------
 1 file changed, 29 insertions(+), 62 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index 7d4a3e5..3cac1e1 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -13,9 +13,31 @@ module testALU ();
 
   ALU alu (out,cout,zero,overflow,a,b,op);
 
-  initial begin
+  function integer test;
+    input test_case;
+    integer test_case;
+    input show_extras;
+    begin
+      if (test_case) begin
+        test = 1;
+        $display("Passed test with:");
+      end
+      else begin
+        test = 0;
+        $display("Failed test with:");
+      end
+      $display("a:   %b", a);
+      $display("b:   %b", b);
+      $display("out: %b", out);
+      if (show_extras) begin
+        $display("Cout: %b, Overflow: %b", cout, overflow);
+      end
+    end
+  endfunction
 
 
+  initial begin
+
 
     // Test Add
     $display("\nAddition");
@@ -81,16 +103,7 @@ module testALU ();
     $display("op: %b", op);
     a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#1000
     tests = tests + 1;
-    if ((a ^ b) == out) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with:");
-    end
-    else begin
-        $display("Failed test with:");
-    end
-    $display("a:   %b", a);
-    $display("b:   %b", b);
-    $display("out: %b", out);
+    passed_tests = passed_tests + test((a ^ b) == out, 0);
 
     // Test SLT
     $display("\nSLT");
@@ -100,69 +113,23 @@ module testALU ();
     // SLT(a,b) = 1 where a<b
     a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
-    if ((a < b) == out) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with:");
-    end
-    else begin
-        $display("Failed test with:");
-    end
-    $display("a:   %b", a);
-    $display("b:   %b", b);
-    $display("out: %b", out);
+    passed_tests = passed_tests + test((a < b) == out, 0);
     // SLT(a,b) = 0 where a>b
     a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
-    if ((a < b) == out) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with:");
-    end
-    else begin
-        $display("Failed test with:");
-    end
-    $display("a:   %b", a);
-    $display("b:   %b", b);
-    $display("out: %b", out);
+    passed_tests = passed_tests + test((a < b) == out, 0);
     // SLT(a,b) = 1 where a(is negative)<b(is positive)
     a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
-    if ((a < b) == out) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with:");
-    end
-    else begin
-        $display("Failed test with:");
-    end
-    $display("a:   %b", a);
-    $display("b:   %b", b);
-    $display("out: %b", out);
+    passed_tests = passed_tests + test((a < b) == out, 0);
     // SLT(a,b) = 0 where a(is positive)>b(is negative)
     a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
     tests = tests + 1;
-    if ((a < b) == out) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with:");
-    end
-    else begin
-        $display("Failed test with:");
-    end
-    $display("a:   %b", a);
-    $display("b:   %b", b);
-    $display("out: %b", out);
+    passed_tests = passed_tests + test((a < b) == out, 0);
     // SLT(a,b) = 1 where a(is negative)>b(is negative)
     a=32'b10000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
     tests = tests + 1;
-    if ((a < b) == out) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with:");
-    end
-    else begin
-        $display("Failed test with:");
-    end
-    $display("a:   %b", a);
-    $display("b:   %b", b);
-    $display("out: %b", out);
-
+    passed_tests = passed_tests + test((a < b) == out, 0);
 
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 

From ee7ab4f8e711d5dfc39a09752f697bd83728fc81 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Tue, 10 Oct 2017 10:46:00 -0400
Subject: [PATCH 39/52] add/sub test cases

---
 alu.t.v | 145 ++++++++++++++++++++++++++++++++++++++++++++++++++++----
 alu.v   |   2 +-
 2 files changed, 137 insertions(+), 10 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index a893974..f7afd9c 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -23,56 +23,181 @@ module testALU ();
     op=3'b000;
     a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
     tests = tests + 1;
-    if ((a + b) == out) begin
+    if (((a + b) == out) && (overflow == 0) && (cout == 0)) begin
         passed_tests = passed_tests + 1;
         $display("Passed test with op: %b", op);
         $display("a:   %b", a);
         $display("b:   %b", b);
         $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b", cout, overflow);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
     end
     else begin
         $display("Failed test with op: %b", op);
         $display("a:   %b", a);
         $display("b:   %b", b);
         $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b", cout, overflow);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
     end
     a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
     tests = tests + 1;
-    if ((a + b) == out) begin
+    if (((a + b) == out) && (overflow == 0) && (cout == 0)) begin
         passed_tests = passed_tests + 1;
         $display("Passed test with op: %b", op);
         $display("a:   %b", a);
         $display("b:   %b", b);
         $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b", cout, overflow);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
     end
     else begin
         $display("Failed test with op: %b", op);
         $display("a:   %b", a);
         $display("b:   %b", b);
         $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b", cout, overflow);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
     end
     a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000001;#1000
     tests = tests + 1;
-    if ((a + b) == out) begin
+    if (((a + b) == out) && (overflow == 0) && (cout == 1)) begin
         passed_tests = passed_tests + 1;
         $display("Passed test with op: %b", op);
         $display("a:   %b", a);
         $display("b:   %b", b);
         $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b", cout, overflow);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
     end
     else begin
         $display("Failed test with op: %b", op);
         $display("a:   %b", a);
         $display("b:   %b", b);
         $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b", cout, overflow);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    // Overflow
+    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#1000
+    tests = tests + 1;
+    if (((a + b) == out) && (overflow == 1)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#1000
+    tests = tests + 1;
+    if (((a + b) == out) && (overflow == 1)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+
+    // Test Add
+    $display("Subtraction");
+    $display("-----------------------------------------------------------------");
+    op=3'b001;
+    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
+    tests = tests + 1;
+    if (((a - b) == out) && (overflow == 0) && (cout == 0)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
+    tests = tests + 1;
+    if (((a - b) == out) && (overflow == 0) && (cout == 0)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#1000
+    tests = tests + 1;
+    if (((a - b) == out) && (overflow == 0)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#1000
+    tests = tests + 1;
+    if (((a - b) == out) && (overflow == 0)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
     end
 
+    a=32'b01000000000000000000000000000000; b=32'b10000000000010101010000000000001;#1000
+    tests = tests + 1;
+    if (((a - b) == out) && (overflow == 1)) begin
+        passed_tests = passed_tests + 1;
+        $display("Passed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
+    else begin
+        $display("Failed test with op: %b", op);
+        $display("a:   %b", a);
+        $display("b:   %b", b);
+        $display("out: %b", out);
+        $display("Cout: %b, Overflow: %b\n", cout, overflow);
+    end
 
     // Test XOR
     $display("XOR");
@@ -95,6 +220,8 @@ module testALU ();
     op=3'b011;
     a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
+    $display("Expected: %b ", (a < b));
+    $display("Expected: %b ", (b < a));
     if ((a < b) == out) begin
         passed_tests = passed_tests + 1;
         $display("Passed test with op: %b", op);
diff --git a/alu.v b/alu.v
index 04b7b44..7289eda 100644
--- a/alu.v
+++ b/alu.v
@@ -59,6 +59,6 @@ module ALU
   ALU1bit a30(result[29], cout[29], operandA[29], operandB[29], cout[28], command);
   ALU1bit a31(result[30], cout[30], operandA[30], operandB[30], cout[29], command);
   ALU1bit a32(result[31], carryout, operandA[31], operandB[31], cout[30], command);
-  xor(overflow, carryout, cout[30]);
+  xor(overflow, carryout, cout[30]); 
 
 endmodule

From 2114d05c6fa86e4712ff3bb2b609b2d9ee6b56ac Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 18:28:24 -0400
Subject: [PATCH 40/52] refactor all tests

---
 alu.t.v | 169 ++++++--------------------------------------------------
 1 file changed, 18 insertions(+), 151 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index 758076b..a9e7cff 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -45,181 +45,48 @@ module testALU ();
     op=3'b000;
     a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
     tests = tests + 1;
-    if (((a + b) == out) && (overflow == 0) && (cout == 0)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 0), 1);
+
     a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
     tests = tests + 1;
-    if (((a + b) == out) && (overflow == 0) && (cout == 0)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 0), 1);
+
     a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000001;#1000
     tests = tests + 1;
-    if (((a + b) == out) && (overflow == 0) && (cout == 1)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 1), 1);
+
     // Overflow
     a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#1000
     tests = tests + 1;
-    if (((a + b) == out) && (overflow == 1)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 1), 1);
+
     a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#1000
     tests = tests + 1;
-    if (((a + b) == out) && (overflow == 1)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a + b) == out) && (overflow == 1), 1);
 
-    // Test Add
+    // Test Subtract
     $display("Subtraction");
     $display("-----------------------------------------------------------------");
     op=3'b001;
     a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
     tests = tests + 1;
-    if (((a - b) == out) && (overflow == 0) && (cout == 0)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0) && (cout == 0), 1);
+
     a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
     tests = tests + 1;
-    if (((a - b) == out) && (overflow == 0) && (cout == 0)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0) && (cout == 0), 1);
+
     a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#1000
     tests = tests + 1;
-    if (((a - b) == out) && (overflow == 0)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0), 1);
+
     a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#1000
     tests = tests + 1;
-    if (((a - b) == out) && (overflow == 0)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0), 1);
 
     a=32'b01000000000000000000000000000000; b=32'b10000000000010101010000000000001;#1000
     tests = tests + 1;
-    if (((a - b) == out) && (overflow == 1)) begin
-        passed_tests = passed_tests + 1;
-        $display("Passed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
-    else begin
-        $display("Failed test with op: %b", op);
-        $display("a:   %b", a);
-        $display("b:   %b", b);
-        $display("out: %b", out);
-        $display("Cout: %b, Overflow: %b\n", cout, overflow);
-    end
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 1), 1);
 
     // Test XOR
     $display("\nXOR");

From 28eaba5db6a725644bb6c5bc9824bb5492f686f3 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Tue, 10 Oct 2017 18:28:42 -0400
Subject: [PATCH 41/52] not sure

---
 alu.t.v   | 4 ++++
 alu.v     | 7 ++++++-
 alu1bit.v | 2 +-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index 89a59de..1ae6505 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -237,6 +237,7 @@ module testALU ();
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
+    $display("Cout: %b, Overflow: %b\n", cout, overflow);
     // SLT(a,b) = 0 where a>b
     a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
@@ -250,6 +251,7 @@ module testALU ();
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
+    $display("Cout: %b, Overflow: %b\n", cout, overflow);
     // SLT(a,b) = 1 where a(is negative)<b(is positive)
     a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
@@ -276,6 +278,7 @@ module testALU ();
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
+    $display("Cout: %b, Overflow: %b\n", cout, overflow);
     // SLT(a,b) = 1 where a(is negative)>b(is negative)
     a=32'b10000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
     tests = tests + 1;
@@ -289,6 +292,7 @@ module testALU ();
     $display("a:   %b", a);
     $display("b:   %b", b);
     $display("out: %b", out);
+    $display("Cout: %b, Overflow: %b\n", cout, overflow);
 
 
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
diff --git a/alu.v b/alu.v
index 7289eda..82cb917 100644
--- a/alu.v
+++ b/alu.v
@@ -59,6 +59,11 @@ module ALU
   ALU1bit a30(result[29], cout[29], operandA[29], operandB[29], cout[28], command);
   ALU1bit a31(result[30], cout[30], operandA[30], operandB[30], cout[29], command);
   ALU1bit a32(result[31], carryout, operandA[31], operandB[31], cout[30], command);
-  xor(overflow, carryout, cout[30]); 
+  xor(overflow, carryout, cout[30]);
+
+  //wire[31:0] res_STL;
+  //assign res_STL[0] = result[31];
+  //wire[7:0] muxRes[31:0] = {result, result, result, result, res_STL, result, result, result};
+  //MUX3bit mux(result, op, muxRes);
 
 endmodule
diff --git a/alu1bit.v b/alu1bit.v
index 31d059d..ff32924 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -42,7 +42,7 @@ module ALU1bit
 	// SLT
 	wire res_SLT;
 	wire cout_SLT;
-	Subtractor1bit slt(res_SUB, cout_SLT, a, b, cin);
+	Subtractor1bit slt(res_SLT, cout_SLT, a, b, cin);
 
 	// And
 	wire res_AND;

From fae07facc1c91713683836b4dc0cda22b43fd0c1 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 18:49:37 -0400
Subject: [PATCH 42/52] added high 16 mux cases

---
 alu.v | 48 ++++++++++++++++++++++++++++++++++++------------
 1 file changed, 36 insertions(+), 12 deletions(-)

diff --git a/alu.v b/alu.v
index d5013b0..409d5f7 100644
--- a/alu.v
+++ b/alu.v
@@ -62,18 +62,42 @@ module ALU
   ALU1bit a32(res_premux[31], carryout, operandA[31], operandB[31], cout[30], command);
   xor(overflow, carryout, cout[30]);
 
-  
+
   wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], res_premux[31], res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b1, res_premux[1], res_premux[1], res_premux[1]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
+  MUX3bit mux0(result[0], command, resMux0);
+  wire[7:0] resMux1 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b0, res_premux[1], res_premux[1], res_premux[1]};
+  MUX3bit mux1(result[0], command, resMux1);
 
+  wire[7:0] resMux16 = {res_premux[16], res_premux[16], res_premux[16], res_premux[16], 1'b0, res_premux[16], res_premux[16], res_premux[16]};
+  MUX3bit mux16(result[16], command, resMux16);
+  wire[7:0] resMux17 = {res_premux[17], res_premux[17], res_premux[17], res_premux[17], 1'b0, res_premux[17], res_premux[17], res_premux[17]};
+  MUX3bit mux17(result[17], command, resMux17);
+  wire[7:0] resMux18 = {res_premux[18], res_premux[18], res_premux[18], res_premux[18], 1'b0, res_premux[18], res_premux[18], res_premux[18]};
+  MUX3bit mux18(result[18], command, resMux18);
+  wire[7:0] resMux19 = {res_premux[19], res_premux[19], res_premux[19], res_premux[19], 1'b0, res_premux[19], res_premux[19], res_premux[19]};
+  MUX3bit mux19(result[19], command, resMux19);
+  wire[7:0] resMux20 = {res_premux[20], res_premux[20], res_premux[20], res_premux[20], 1'b0, res_premux[20], res_premux[20], res_premux[20]};
+  MUX3bit mux20(result[20], command, resMux20);
+  wire[7:0] resMux21 = {res_premux[21], res_premux[21], res_premux[21], res_premux[21], 1'b0, res_premux[21], res_premux[21], res_premux[21]};
+  MUX3bit mux21(result[21], command, resMux21);
+  wire[7:0] resMux22 = {res_premux[22], res_premux[22], res_premux[22], res_premux[22], 1'b0, res_premux[22], res_premux[22], res_premux[22]};
+  MUX3bit mux22(result[22], command, resMux22);
+  wire[7:0] resMux23 = {res_premux[23], res_premux[23], res_premux[23], res_premux[23], 1'b0, res_premux[23], res_premux[23], res_premux[23]};
+  MUX3bit mux23(result[23], command, resMux23);
+  wire[7:0] resMux24 = {res_premux[24], res_premux[24], res_premux[24], res_premux[24], 1'b0, res_premux[24], res_premux[24], res_premux[24]};
+  MUX3bit mux24(result[24], command, resMux24);
+  wire[7:0] resMux25 = {res_premux[25], res_premux[25], res_premux[25], res_premux[25], 1'b0, res_premux[25], res_premux[25], res_premux[25]};
+  MUX3bit mux25(result[25], command, resMux25);
+  wire[7:0] resMux26 = {res_premux[26], res_premux[26], res_premux[26], res_premux[26], 1'b0, res_premux[26], res_premux[26], res_premux[26]};
+  MUX3bit mux26(result[26], command, resMux26);
+  wire[7:0] resMux27 = {res_premux[27], res_premux[27], res_premux[27], res_premux[27], 1'b0, res_premux[27], res_premux[27], res_premux[27]};
+  MUX3bit mux27(result[27], command, resMux27);
+  wire[7:0] resMux28 = {res_premux[28], res_premux[28], res_premux[28], res_premux[28], 1'b0, res_premux[28], res_premux[28], res_premux[28]};
+  MUX3bit mux28(result[28], command, resMux28);
+  wire[7:0] resMux29 = {res_premux[29], res_premux[29], res_premux[29], res_premux[29], 1'b0, res_premux[29], res_premux[29], res_premux[29]};
+  MUX3bit mux29(result[29], command, resMux29);
+  wire[7:0] resMux30 = {res_premux[30], res_premux[30], res_premux[30], res_premux[30], 1'b0, res_premux[30], res_premux[30], res_premux[30]};
+  MUX3bit mux30(result[30], command, resMux30);
+  wire[7:0] resMux31 = {res_premux[31], res_premux[31], res_premux[31], res_premux[31], 1'b0, res_premux[31], res_premux[31], res_premux[31]};
+  MUX3bit mux31(result[31], command, resMux31);
 endmodule

From 1a49543418b5684ca566d287e14a6a430978027a Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Tue, 10 Oct 2017 18:49:46 -0400
Subject: [PATCH 43/52] ps

---
 alu.v | 48 +++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 37 insertions(+), 11 deletions(-)

diff --git a/alu.v b/alu.v
index d5013b0..3fd7936 100644
--- a/alu.v
+++ b/alu.v
@@ -64,16 +64,42 @@ module ALU
 
   
   wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], res_premux[31], res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b1, res_premux[1], res_premux[1], res_premux[1]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], 1'b0, res_premux[0], res_premux[0], res_premux[0]};
-  MUX3bit mux0(result[0], op, resMux0);
+  MUX3bit mux0(result[0], command, resMux0);
+  wire[7:0] resMux1 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b0, res_premux[1], res_premux[1], res_premux[1]};
+  MUX3bit mux1(result[1], command, resMux1);
+  wire[7:0] resMux2 = {res_premux[2], res_premux[2], res_premux[2], res_premux[2], 1'b0, res_premux[2], res_premux[2], res_premux[2]};
+  MUX3bit mux2(result[2], command, resMux2);
+  wire[7:0] resMux3 = {res_premux[3], res_premux[3], res_premux[3], res_premux[3], 1'b0, res_premux[3], res_premux[3], res_premux[3]};
+  MUX3bit mux3(result[3], command, resMux3);
+  wire[7:0] resMux4 = {res_premux[4], res_premux[4], res_premux[4], res_premux[4], 1'b0, res_premux[4], res_premux[4], res_premux[4]};
+  MUX3bit mux4(result[4], command, resMux4);
+
+
+  wire[7:0] resMux5 = {res_premux[5], res_premux[5], res_premux[5], res_premux[5], 1'b0, res_premux[5], res_premux[5], res_premux[5]};
+  MUX3bit mux5(result[5], command, resMux5);
+  wire[7:0] resMux6 = {res_premux[6], res_premux[6], res_premux[6], res_premux[6], 1'b0, res_premux[6], res_premux[6], res_premux[6]};
+  MUX3bit mux6(result[6], command, resMux6);
+  wire[7:0] resMux7 = {res_premux[7], res_premux[7], res_premux[7], res_premux[7], 1'b0, res_premux[7], res_premux[7], res_premux[7]};
+  MUX3bit mux7(result[7], command, resMux7);
+  wire[7:0] resMux8 = {res_premux[8], res_premux[8], res_premux[8], res_premux[8], 1'b0, res_premux[8], res_premux[8], res_premux[8]};
+  MUX3bit mux8(result[8], command, resMux8);
+
+  wire[7:0] resMux9 = {res_premux[9], res_premux[9], res_premux[9], res_premux[9], 1'b0, res_premux[9], res_premux[9], res_premux[9]};
+  MUX3bit mux9(result[9], command, resMux9);
+  wire[7:0] resMux10 = {res_premux[10], res_premux[10], res_premux[10], res_premux[10], 1'b0, res_premux[10], res_premux[10], res_premux[10]};
+  MUX3bit mux10(result[10], command, resMux10);
+  wire[7:0] resMux11 = {res_premux[11], res_premux[11], res_premux[11], res_premux[11], 1'b0, res_premux[11], res_premux[11], res_premux[11]};
+  MUX3bit mux11(result[11], command, resMux11);
+  wire[7:0] resMux12 = {res_premux[12], res_premux[12], res_premux[12], res_premux[12], 1'b0, res_premux[12], res_premux[12], res_premux[12]};
+  MUX3bit mux12(result[12], command, resMux12);
+
+  wire[7:0] resMux13 = {res_premux[13], res_premux[13], res_premux[13], res_premux[13], 1'b0, res_premux[13], res_premux[13], res_premux[13]};
+  MUX3bit mux13(result[13], command, resMux13);
+  wire[7:0] resMux14 = {res_premux[14], res_premux[14], res_premux[14], res_premux[14], 1'b0, res_premux[14], res_premux[14], res_premux[14]};
+  MUX3bit mux14(result[14], command, resMux14);
+  wire[7:0] resMux15 = {res_premux[15], res_premux[15], res_premux[15], res_premux[15], 1'b0, res_premux[15], res_premux[15], res_premux[15]};
+  MUX3bit mux15(result[15], command, resMux15);
+  wire[7:0] resMux16 = {res_premux[16], res_premux[16], res_premux[16], res_premux[16], 1'b0, res_premux[16], res_premux[16], res_premux[16]};
+  MUX3bit mux16(result[16], command, resMux16);
 
 endmodule

From 150b432779e5a689edb9cd0cb092cfc5c51de08a Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 18:53:55 -0400
Subject: [PATCH 44/52] Fixed broken test case

---
 alu.t.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/alu.t.v b/alu.t.v
index 8b091d4..e15439d 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -115,7 +115,7 @@ module testALU ();
     // SLT(a,b) = 1 where a(is negative)<b(is positive)
     a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
-    passed_tests = passed_tests + test((a < b) == out, 1);
+    passed_tests = passed_tests + test(out == 1, 1);
     // SLT(a,b) = 0 where a(is positive)>b(is negative)
     a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
     tests = tests + 1;

From 77d0b13235ca820f74154878dd213bf537c40b2c Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Tue, 10 Oct 2017 19:08:46 -0400
Subject: [PATCH 45/52] ps

---
 alu.t.v | 29 ++++++++++++++++++++++++-----
 alu.v   |  5 +++--
 2 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index e15439d..57e6e66 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -106,11 +106,11 @@ module testALU ();
     a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
 
-    passed_tests = passed_tests + test((a < b) == out, 1);
+    passed_tests = passed_tests + test(out == 1, 1);
     // SLT(a,b) = 0 where a>b
     a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
     tests = tests + 1;
-    passed_tests = passed_tests + test((a < b) == out, 1);
+    passed_tests = passed_tests + test(out == 0, 1);
 
     // SLT(a,b) = 1 where a(is negative)<b(is positive)
     a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
@@ -120,12 +120,31 @@ module testALU ();
     a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
     tests = tests + 1;
 
-    passed_tests = passed_tests + test((a < b) == out, 1);
+    passed_tests = passed_tests + test(out == 0, 1);
+    // SLT(a,b) = 1 where a(is negative)>b(is negative)
+    a=32'b10000000000000000000000000001000; b=32'b10000000000000000000001000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+
     // SLT(a,b) = 1 where a(is negative)>b(is negative)
-    a=32'b00000000000000000000000000001000; b=32'b00000000000000000000001000000000;#1000
+    a=32'b10000000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
     tests = tests + 1;
-    passed_tests = passed_tests + test((a < b) == out, 1);
+    passed_tests = passed_tests + test(out == 1, 1);
 
+    // small pos / large pos = 1
+    // large pos / small pos = 0
+    // equal positives = 0
+
+    // small neg / large neg = 0
+    // large neg / small neg = 1
+    // equal negatives = 0
+
+    // positive overflow: large pos / large neg : 0
+    // negative overflow: large neg / large pos : 1
+
+    a=32'b00000000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 
     end
diff --git a/alu.v b/alu.v
index b51e530..a14ef33 100644
--- a/alu.v
+++ b/alu.v
@@ -62,8 +62,9 @@ module ALU
   ALU1bit a32(res_premux[31], carryout, operandA[31], operandB[31], cout[30], command);
   xor(overflow, carryout, cout[30]);
 
-
-  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], res_premux[31], res_premux[0], res_premux[0], res_premux[0]};
+  wire temp;
+  xor(temp, res_premux[31], overflow);
+  wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], temp, res_premux[0], res_premux[0], res_premux[0]};
   MUX3bit mux0(result[0], command, resMux0);
   wire[7:0] resMux1 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b0, res_premux[1], res_premux[1], res_premux[1]};
   MUX3bit mux1(result[1], command, resMux1);

From b2a01d1efdf070dd0478d919a6fde80bfc1203c5 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 19:13:01 -0400
Subject: [PATCH 46/52] added more slt test cases

---
 alu.t.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/alu.t.v b/alu.t.v
index 57e6e66..1e56154 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -132,12 +132,30 @@ module testALU ();
     passed_tests = passed_tests + test(out == 1, 1);
 
     // small pos / large pos = 1
+    a=32'b00000000000000000000000000001000; b=32'b01110000001000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
     // large pos / small pos = 0
+    a=32'b01110000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
     // equal positives = 0
+    a=32'b01110000000000000000000000001000; b=32'b01110000000000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
 
     // small neg / large neg = 0
+    a=32'b11111111000000000000000000001000; b=32'b10000000000000000000000000000111;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
     // large neg / small neg = 1
+    a=32'b10000000000000000000000000000111; b=32'b11111111000000000000000000001000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
     // equal negatives = 0
+    a=32'b10000000000000000000000000000111; b=32'b10000000000000000000000000000111;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
 
     // positive overflow: large pos / large neg : 0
     // negative overflow: large neg / large pos : 1

From b9ae29cebc7544bc3309baf99901f80abda886f3 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Tue, 10 Oct 2017 19:13:23 -0400
Subject: [PATCH 47/52] new test

---
 alu.t.v | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/alu.t.v b/alu.t.v
index 57e6e66..6bcbeaa 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -140,11 +140,15 @@ module testALU ();
     // equal negatives = 0
 
     // positive overflow: large pos / large neg : 0
+    a=32'b01000000000000000000000000000001; b=32'b10000000000000000000000000010000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
     // negative overflow: large neg / large pos : 1
-
-    a=32'b00000000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    a=32'b10000000000000000000000000000001; b=32'b00000100000000000000000000000000;#1000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
+
+
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 
     end

From 0eee28752049208535617a9e9c5ac128758bb572 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Tue, 10 Oct 2017 19:32:12 -0400
Subject: [PATCH 48/52] add realistic timing

---
 adder1bit.v      | 23 +++++++++++++++--------
 alu.t.v          | 48 ++++++++++++++++++++++++------------------------
 alu.v            |  3 ---
 alu1bit.t.v      |  1 -
 alu1bit.v        | 14 +++++++++-----
 mux32to1by1.v    | 37 -------------------------------------
 subtractor1bit.v | 21 ++++++++++++++-------
 7 files changed, 62 insertions(+), 85 deletions(-)
 delete mode 100644 mux32to1by1.v

diff --git a/adder1bit.v b/adder1bit.v
index 361801e..d8cad02 100644
--- a/adder1bit.v
+++ b/adder1bit.v
@@ -1,3 +1,10 @@
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
 module Adder1bit
 (
     output sum,
@@ -9,12 +16,12 @@ module Adder1bit
     wire aandb, aorb;
     wire s, _carryin;
     wire outputIfCarryin, outputIf_Carryin;
-    xor(s, a, b);
-    xor(sum, s, carryin);
-    and(aandb, a, b);
-    or(aorb, a, b);
-    not(_carryin, carryin);
-    and(outputIfCarryin, aandb, _carryin);
-    and(outputIf_Carryin, aorb, carryin);
-    or(carryout, outputIfCarryin, outputIf_Carryin);
+    `XOR(s, a, b);
+    `XOR(sum, s, carryin);
+    `AND(aandb, a, b);
+    `OR(aorb, a, b);
+    `NOT(_carryin, carryin);
+    `AND(outputIfCarryin, aandb, _carryin);
+    `AND(outputIf_Carryin, aorb, carryin);
+    `OR(carryout, outputIfCarryin, outputIf_Carryin);
 endmodule
diff --git a/alu.t.v b/alu.t.v
index 1e56154..aae050f 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -43,24 +43,24 @@ module testALU ();
     $display("\nAddition");
     $display("-----------------------------------------------------------------");
     op=3'b000;
-    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
+    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 0), 1);
 
-    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 0), 1);
 
-    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000001;#1000
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a + b) == out) && (overflow == 0) && (cout == 1), 1);
 
     // Overflow
-    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#1000
+    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a + b) == out) && (overflow == 1), 1);
 
-    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#1000
+    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a + b) == out) && (overflow == 1), 1);
 
@@ -68,23 +68,23 @@ module testALU ();
     $display("Subtraction");
     $display("-----------------------------------------------------------------");
     op=3'b001;
-    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#1000
+    a=32'b00000000000011111111111111111111; b=32'b0000000000000000000000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0) && (cout == 0), 1);
 
-    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#1000
+    a=32'b11111111111111111111111111111111; b=32'b0000000000000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0) && (cout == 0), 1);
 
-    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#1000
+    a=32'b10110000000000000000000000000000; b=32'b11000000000000000000000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0), 1);
 
-    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#1000
+    a=32'b10000000000000001100011010101100; b=32'b11000000000010101010000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a - b) == out) && (overflow == 0), 1);
 
-    a=32'b01000000000000000000000000000000; b=32'b10000000000010101010000000000001;#1000
+    a=32'b01000000000000000000000000000000; b=32'b10000000000010101010000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(((a - b) == out) && (overflow == 1), 1);
 
@@ -93,7 +93,7 @@ module testALU ();
     $display("-----------------------------------------------------------------");
     op=3'b010;
     $display("op: %b", op);
-    a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#1000
+    a=32'b00000000000000000000000000000000; b=32'b00000000000000000000000000000001;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test((a ^ b) == out, 0);
 
@@ -103,64 +103,64 @@ module testALU ();
     op=3'b011;
     $display("op: %b", op);
     // SLT(a,b) = 1 where a<b
-    a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#1000
+    a=32'b00000000000000000000000000000001; b=32'b00000000000000000000000000000010;#2000
     tests = tests + 1;
 
     passed_tests = passed_tests + test(out == 1, 1);
     // SLT(a,b) = 0 where a>b
-    a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
+    a=32'b00000000000000000000000000001000; b=32'b00000000000000000000000000000010;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 0, 1);
 
     // SLT(a,b) = 1 where a(is negative)<b(is positive)
-    a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#1000
+    a=32'b10000000000000000000000000001000; b=32'b00000000000000000000000000000010;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
     // SLT(a,b) = 0 where a(is positive)>b(is negative)
-    a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#1000
+    a=32'b00000000000000000000000000001000; b=32'b10000000000000000000000000000010;#2000
     tests = tests + 1;
 
     passed_tests = passed_tests + test(out == 0, 1);
     // SLT(a,b) = 1 where a(is negative)>b(is negative)
-    a=32'b10000000000000000000000000001000; b=32'b10000000000000000000001000000000;#1000
+    a=32'b10000000000000000000000000001000; b=32'b10000000000000000000001000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
 
     // SLT(a,b) = 1 where a(is negative)>b(is negative)
-    a=32'b10000000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    a=32'b10000000000000000000000000001000; b=32'b00000000001000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
 
     // small pos / large pos = 1
-    a=32'b00000000000000000000000000001000; b=32'b01110000001000000000000000000000;#1000
+    a=32'b00000000000000000000000000001000; b=32'b01110000001000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
     // large pos / small pos = 0
-    a=32'b01110000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    a=32'b01110000000000000000000000001000; b=32'b00000000001000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 0, 1);
     // equal positives = 0
-    a=32'b01110000000000000000000000001000; b=32'b01110000000000000000000000000000;#1000
+    a=32'b01110000000000000000000000001000; b=32'b01110000000000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 0, 1);
 
     // small neg / large neg = 0
-    a=32'b11111111000000000000000000001000; b=32'b10000000000000000000000000000111;#1000
+    a=32'b11111111000000000000000000001000; b=32'b10000000000000000000000000000111;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 0, 1);
     // large neg / small neg = 1
-    a=32'b10000000000000000000000000000111; b=32'b11111111000000000000000000001000;#1000
+    a=32'b10000000000000000000000000000111; b=32'b11111111000000000000000000001000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
     // equal negatives = 0
-    a=32'b10000000000000000000000000000111; b=32'b10000000000000000000000000000111;#1000
+    a=32'b10000000000000000000000000000111; b=32'b10000000000000000000000000000111;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 0, 1);
 
     // positive overflow: large pos / large neg : 0
     // negative overflow: large neg / large pos : 1
 
-    a=32'b00000000000000000000000000001000; b=32'b00000000001000000000000000000000;#1000
+    a=32'b00000000000000000000000000001000; b=32'b00000000001000000000000000000000;#2000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
diff --git a/alu.v b/alu.v
index a14ef33..1c7c11b 100644
--- a/alu.v
+++ b/alu.v
@@ -10,9 +10,6 @@
 // b111 -> OR
 
 `include "alu1bit.v"
-`define AND and #30
-`define OR or #30
-`define NOT not #10
 
 module ALU
 (
diff --git a/alu1bit.t.v b/alu1bit.t.v
index 65d005e..4591a50 100644
--- a/alu1bit.t.v
+++ b/alu1bit.t.v
@@ -1,7 +1,6 @@
 // 1 Bit alu test bench
 `timescale 1 ns / 1 ps
 `include "alu1bit.v"
-`include "alu.v"
 
 module testALU1bit ();
   wire     out, cout;
diff --git a/alu1bit.v b/alu1bit.v
index ff32924..b1602dc 100644
--- a/alu1bit.v
+++ b/alu1bit.v
@@ -15,6 +15,10 @@
 `define AND and #30
 `define OR or #30
 `define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
 
 module ALU1bit
 (
@@ -37,7 +41,7 @@ module ALU1bit
 
 	// Xor
 	wire res_XOR;
-	xor(res_XOR, a, b);
+	`XOR(res_XOR, a, b);
 
 	// SLT
 	wire res_SLT;
@@ -46,19 +50,19 @@ module ALU1bit
 
 	// And
 	wire res_AND;
-	and(res_AND, a, b);
+	`AND(res_AND, a, b);
 
 	// Nand
 	wire res_NAND;
-	nand(res_NAND, a, b);
+	`NAND(res_NAND, a, b);
 
 	// Nor
 	wire res_NOR;
-	nor(res_NOR, a, b);
+	`NOR(res_NOR, a, b);
 
 	// Or
 	wire res_OR;
-	or(res_OR, a, b);
+	`OR(res_OR, a, b);
 
 	// Use a behavioral mux to select operation
 	wire[7:0] muxRes = {res_OR, res_NOR, res_NAND, res_AND, res_SLT, res_XOR, res_SUB, res_ADD};
diff --git a/mux32to1by1.v b/mux32to1by1.v
deleted file mode 100644
index a2d40da..0000000
--- a/mux32to1by1.v
+++ /dev/null
@@ -1,37 +0,0 @@
-// 32 bit mux
-module mux32to1by1
-(
-output      out,
-input[4:0]  address,
-input[31:0] inputs
-);
-  assign out = inputs[address];
-endmodule
-
-
-// 32x32bit mux
-module mux32to1by32
-(
-output[31:0]  out,
-input[4:0]    address,
-input[31:0]   inputs
-);
-
-  wire[31:0] mux[31:0];			// Create a 2D array of wires
-  assign mux[0] = inputs[0];		// Connect the sources of the array
-  for (i=0;i<32;i=i+1) begin
-  	mux[i]=inputs[i];
-  end
-  assign out = mux[address];	// Connect the output of the array
-endmodule
-
-
-// 32 bit decoder
-module decoder1to32
-(
-output[31:0]  out,
-input         enable,
-input[4:0]    address
-);
-    assign out = enable<<address; 
-endmodule
\ No newline at end of file
diff --git a/subtractor1bit.v b/subtractor1bit.v
index 84d2b86..a08ad11 100644
--- a/subtractor1bit.v
+++ b/subtractor1bit.v
@@ -1,3 +1,10 @@
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
+
 module Subtractor1bit
 (
     output diff,
@@ -7,12 +14,12 @@ module Subtractor1bit
     input borrowin
 );
     wire axorb;
-    xor(axorb, a, b);
-    xor(diff, axorb, borrowin);
+    `XOR(axorb, a, b);
+    `XOR(diff, axorb, borrowin);
     wire nota, noteaandb, notaxorb, notaxorbandborrowin;
-    not(nota, a);
-    and(notaandb, nota, b);
-    not(notaxorb, axorb);
-    and(notaxorbandborrowin, notaxorb, borrowin);
-    or(borrowout, notaandb, notaxorbandborrowin);
+    `NOT(nota, a);
+    `AND(notaandb, nota, b);
+    `NOT(notaxorb, axorb);
+    `AND(notaxorbandborrowin, notaxorb, borrowin);
+    `OR(borrowout, notaandb, notaxorbandborrowin);
 endmodule

From 1f0899218de6d8473a4c6057458b96685c527584 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Wed, 11 Oct 2017 12:52:12 -0400
Subject: [PATCH 49/52] comments and more test cases

---
 alu.t.v | 12 ++++++++++++
 alu.v   |  8 +++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/alu.t.v b/alu.t.v
index c7199d2..f245ba5 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -88,6 +88,10 @@ module testALU ();
     tests = tests + 1;
     passed_tests = passed_tests + test(((a - b) == out) && (overflow == 1), 1);
 
+    a=32'b10000000000000000000000000000000; b=32'b01000000000010101010000000000001;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(((a - b) == out) && (overflow == 1), 1);
+
     // Test XOR
     $display("\nXOR");
     $display("-----------------------------------------------------------------");
@@ -166,6 +170,14 @@ module testALU ();
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
 
+    a=32'b10000000000000000000000000000001; b=32'b00000100000000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
+
+    a=32'b0010000000000000000-000000000001; b=32'b10000000000000000000000000000000;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 0, 1);
+
 
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 
diff --git a/alu.v b/alu.v
index a14ef33..0e821b4 100644
--- a/alu.v
+++ b/alu.v
@@ -25,7 +25,6 @@ module ALU
   input[2:0]    command
 );
 
-  // supose we're jsut doing Addition for now
   wire[31:0] cout;
   wire[31:0] res_premux;
   ALU1bit a1(res_premux[0], cout[0], operandA[0], operandB[0], 0, command);
@@ -62,8 +61,15 @@ module ALU
   ALU1bit a32(res_premux[31], carryout, operandA[31], operandB[31], cout[30], command);
   xor(overflow, carryout, cout[30]);
 
+  // We're using subtraction for SLT. We have to handle additional cases
+  // for the cases where we have overflow.
   wire temp;
   xor(temp, res_premux[31], overflow);
+
+  // This mux is necessary for handling the SLT, since the desired result of the SLT 
+  // is very different from the actual output from our ALU.
+  // We could have used a MUX of size 2, but that would have required conversion
+  // of the SLT command.
   wire[7:0] resMux0 = {res_premux[0], res_premux[0], res_premux[0], res_premux[0], temp, res_premux[0], res_premux[0], res_premux[0]};
   MUX3bit mux0(result[0], command, resMux0);
   wire[7:0] resMux1 = {res_premux[1], res_premux[1], res_premux[1], res_premux[1], 1'b0, res_premux[1], res_premux[1], res_premux[1]};

From 4d8b6d3653451dc4b3594c06f8af93531c8a55a6 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Wed, 11 Oct 2017 16:11:11 -0400
Subject: [PATCH 50/52] gtkwave

---
 adder4bit.vcd | 15587 ++++++++++++++++++++++++++++++++++++++++++++++++
 alu.t.v       |     3 +-
 alu.vcd       | 15587 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 31176 insertions(+), 1 deletion(-)
 create mode 100644 adder4bit.vcd
 create mode 100644 alu.vcd

diff --git a/adder4bit.vcd b/adder4bit.vcd
new file mode 100644
index 0000000..c152fdc
--- /dev/null
+++ b/adder4bit.vcd
@@ -0,0 +1,15587 @@
+$date
+	Wed Oct 11 15:50:02 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testALU $end
+$var wire 1 ! cout $end
+$var wire 32 " out [31:0] $end
+$var wire 1 # overflow $end
+$var wire 1 $ zero $end
+$var reg 32 % a [31:0] $end
+$var reg 32 & b [31:0] $end
+$var reg 3 ' op [2:0] $end
+$var integer 32 ( passed_tests [31:0] $end
+$var integer 32 ) tests [31:0] $end
+$scope function test $end
+$var reg 1 * show_extras $end
+$var integer 32 + test [31:0] $end
+$var integer 32 , test_case [31:0] $end
+$upscope $end
+$scope module alu $end
+$var wire 1 ! carryout $end
+$var wire 3 - command [2:0] $end
+$var wire 32 . cout [31:0] $end
+$var wire 32 / operandA [31:0] $end
+$var wire 32 0 operandB [31:0] $end
+$var wire 1 # overflow $end
+$var wire 8 1 resMux0 [7:0] $end
+$var wire 8 2 resMux1 [7:0] $end
+$var wire 8 3 resMux10 [7:0] $end
+$var wire 8 4 resMux11 [7:0] $end
+$var wire 8 5 resMux12 [7:0] $end
+$var wire 8 6 resMux13 [7:0] $end
+$var wire 8 7 resMux14 [7:0] $end
+$var wire 8 8 resMux15 [7:0] $end
+$var wire 8 9 resMux16 [7:0] $end
+$var wire 8 : resMux17 [7:0] $end
+$var wire 8 ; resMux18 [7:0] $end
+$var wire 8 < resMux19 [7:0] $end
+$var wire 8 = resMux2 [7:0] $end
+$var wire 8 > resMux20 [7:0] $end
+$var wire 8 ? resMux21 [7:0] $end
+$var wire 8 @ resMux22 [7:0] $end
+$var wire 8 A resMux23 [7:0] $end
+$var wire 8 B resMux24 [7:0] $end
+$var wire 8 C resMux25 [7:0] $end
+$var wire 8 D resMux26 [7:0] $end
+$var wire 8 E resMux27 [7:0] $end
+$var wire 8 F resMux28 [7:0] $end
+$var wire 8 G resMux29 [7:0] $end
+$var wire 8 H resMux3 [7:0] $end
+$var wire 8 I resMux30 [7:0] $end
+$var wire 8 J resMux31 [7:0] $end
+$var wire 8 K resMux4 [7:0] $end
+$var wire 8 L resMux5 [7:0] $end
+$var wire 8 M resMux6 [7:0] $end
+$var wire 8 N resMux7 [7:0] $end
+$var wire 8 O resMux8 [7:0] $end
+$var wire 8 P resMux9 [7:0] $end
+$var wire 32 Q res_premux [31:0] $end
+$var wire 32 R result [31:0] $end
+$var wire 1 S temp $end
+$var wire 1 $ zero $end
+$scope module a1 $end
+$var wire 1 T a $end
+$var wire 1 U b $end
+$var wire 1 V cin $end
+$var wire 1 W cout $end
+$var wire 1 X cout_ADD $end
+$var wire 1 Y cout_SLT $end
+$var wire 1 Z cout_SUB $end
+$var wire 8 [ muxCout [7:0] $end
+$var wire 8 \ muxRes [7:0] $end
+$var wire 3 ] op [2:0] $end
+$var wire 1 ^ out $end
+$var wire 1 _ res_ADD $end
+$var wire 1 ` res_AND $end
+$var wire 1 a res_NAND $end
+$var wire 1 b res_NOR $end
+$var wire 1 c res_OR $end
+$var wire 1 d res_SLT $end
+$var wire 1 e res_SUB $end
+$var wire 1 f res_XOR $end
+$scope module adder $end
+$var wire 1 g _carryin $end
+$var wire 1 T a $end
+$var wire 1 h aandb $end
+$var wire 1 i aorb $end
+$var wire 1 U b $end
+$var wire 1 V carryin $end
+$var wire 1 X carryout $end
+$var wire 1 j outputIfCarryin $end
+$var wire 1 k outputIf_Carryin $end
+$var wire 1 l s $end
+$var wire 1 _ sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 T a $end
+$var wire 1 m axorb $end
+$var wire 1 U b $end
+$var wire 1 V borrowin $end
+$var wire 1 Z borrowout $end
+$var wire 1 e diff $end
+$var wire 1 n nota $end
+$var wire 1 o notaandb $end
+$var wire 1 p notaxorb $end
+$var wire 1 q notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 T a $end
+$var wire 1 r axorb $end
+$var wire 1 U b $end
+$var wire 1 V borrowin $end
+$var wire 1 Y borrowout $end
+$var wire 1 d diff $end
+$var wire 1 s nota $end
+$var wire 1 t notaandb $end
+$var wire 1 u notaxorb $end
+$var wire 1 v notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 w address [2:0] $end
+$var wire 8 x inputs [7:0] $end
+$var wire 1 ^ out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 y address [2:0] $end
+$var wire 8 z inputs [7:0] $end
+$var wire 1 W out $end
+$upscope $end
+$upscope $end
+$scope module a2 $end
+$var wire 1 { a $end
+$var wire 1 | b $end
+$var wire 1 } cin $end
+$var wire 1 ~ cout $end
+$var wire 1 !" cout_ADD $end
+$var wire 1 "" cout_SLT $end
+$var wire 1 #" cout_SUB $end
+$var wire 8 $" muxCout [7:0] $end
+$var wire 8 %" muxRes [7:0] $end
+$var wire 3 &" op [2:0] $end
+$var wire 1 '" out $end
+$var wire 1 (" res_ADD $end
+$var wire 1 )" res_AND $end
+$var wire 1 *" res_NAND $end
+$var wire 1 +" res_NOR $end
+$var wire 1 ," res_OR $end
+$var wire 1 -" res_SLT $end
+$var wire 1 ." res_SUB $end
+$var wire 1 /" res_XOR $end
+$scope module adder $end
+$var wire 1 0" _carryin $end
+$var wire 1 { a $end
+$var wire 1 1" aandb $end
+$var wire 1 2" aorb $end
+$var wire 1 | b $end
+$var wire 1 } carryin $end
+$var wire 1 !" carryout $end
+$var wire 1 3" outputIfCarryin $end
+$var wire 1 4" outputIf_Carryin $end
+$var wire 1 5" s $end
+$var wire 1 (" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 { a $end
+$var wire 1 6" axorb $end
+$var wire 1 | b $end
+$var wire 1 } borrowin $end
+$var wire 1 #" borrowout $end
+$var wire 1 ." diff $end
+$var wire 1 7" nota $end
+$var wire 1 8" notaandb $end
+$var wire 1 9" notaxorb $end
+$var wire 1 :" notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 { a $end
+$var wire 1 ;" axorb $end
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+b11011 )
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+b11100 )
diff --git a/alu.t.v b/alu.t.v
index f245ba5..be2e109 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -37,7 +37,8 @@ module testALU ();
 
 
   initial begin
-
+    $dumpfile("alu.vcd");
+    $dumpvars;
 
     // Test Add
     $display("\nAddition");
diff --git a/alu.vcd b/alu.vcd
new file mode 100644
index 0000000..3125b35
--- /dev/null
+++ b/alu.vcd
@@ -0,0 +1,15587 @@
+$date
+	Wed Oct 11 15:51:17 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module testALU $end
+$var wire 1 ! cout $end
+$var wire 32 " out [31:0] $end
+$var wire 1 # overflow $end
+$var wire 1 $ zero $end
+$var reg 32 % a [31:0] $end
+$var reg 32 & b [31:0] $end
+$var reg 3 ' op [2:0] $end
+$var integer 32 ( passed_tests [31:0] $end
+$var integer 32 ) tests [31:0] $end
+$scope function test $end
+$var reg 1 * show_extras $end
+$var integer 32 + test [31:0] $end
+$var integer 32 , test_case [31:0] $end
+$upscope $end
+$scope module alu $end
+$var wire 1 ! carryout $end
+$var wire 3 - command [2:0] $end
+$var wire 32 . cout [31:0] $end
+$var wire 32 / operandA [31:0] $end
+$var wire 32 0 operandB [31:0] $end
+$var wire 1 # overflow $end
+$var wire 8 1 resMux0 [7:0] $end
+$var wire 8 2 resMux1 [7:0] $end
+$var wire 8 3 resMux10 [7:0] $end
+$var wire 8 4 resMux11 [7:0] $end
+$var wire 8 5 resMux12 [7:0] $end
+$var wire 8 6 resMux13 [7:0] $end
+$var wire 8 7 resMux14 [7:0] $end
+$var wire 8 8 resMux15 [7:0] $end
+$var wire 8 9 resMux16 [7:0] $end
+$var wire 8 : resMux17 [7:0] $end
+$var wire 8 ; resMux18 [7:0] $end
+$var wire 8 < resMux19 [7:0] $end
+$var wire 8 = resMux2 [7:0] $end
+$var wire 8 > resMux20 [7:0] $end
+$var wire 8 ? resMux21 [7:0] $end
+$var wire 8 @ resMux22 [7:0] $end
+$var wire 8 A resMux23 [7:0] $end
+$var wire 8 B resMux24 [7:0] $end
+$var wire 8 C resMux25 [7:0] $end
+$var wire 8 D resMux26 [7:0] $end
+$var wire 8 E resMux27 [7:0] $end
+$var wire 8 F resMux28 [7:0] $end
+$var wire 8 G resMux29 [7:0] $end
+$var wire 8 H resMux3 [7:0] $end
+$var wire 8 I resMux30 [7:0] $end
+$var wire 8 J resMux31 [7:0] $end
+$var wire 8 K resMux4 [7:0] $end
+$var wire 8 L resMux5 [7:0] $end
+$var wire 8 M resMux6 [7:0] $end
+$var wire 8 N resMux7 [7:0] $end
+$var wire 8 O resMux8 [7:0] $end
+$var wire 8 P resMux9 [7:0] $end
+$var wire 32 Q res_premux [31:0] $end
+$var wire 32 R result [31:0] $end
+$var wire 1 S temp $end
+$var wire 1 $ zero $end
+$scope module a1 $end
+$var wire 1 T a $end
+$var wire 1 U b $end
+$var wire 1 V cin $end
+$var wire 1 W cout $end
+$var wire 1 X cout_ADD $end
+$var wire 1 Y cout_SLT $end
+$var wire 1 Z cout_SUB $end
+$var wire 8 [ muxCout [7:0] $end
+$var wire 8 \ muxRes [7:0] $end
+$var wire 3 ] op [2:0] $end
+$var wire 1 ^ out $end
+$var wire 1 _ res_ADD $end
+$var wire 1 ` res_AND $end
+$var wire 1 a res_NAND $end
+$var wire 1 b res_NOR $end
+$var wire 1 c res_OR $end
+$var wire 1 d res_SLT $end
+$var wire 1 e res_SUB $end
+$var wire 1 f res_XOR $end
+$scope module adder $end
+$var wire 1 g _carryin $end
+$var wire 1 T a $end
+$var wire 1 h aandb $end
+$var wire 1 i aorb $end
+$var wire 1 U b $end
+$var wire 1 V carryin $end
+$var wire 1 X carryout $end
+$var wire 1 j outputIfCarryin $end
+$var wire 1 k outputIf_Carryin $end
+$var wire 1 l s $end
+$var wire 1 _ sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 T a $end
+$var wire 1 m axorb $end
+$var wire 1 U b $end
+$var wire 1 V borrowin $end
+$var wire 1 Z borrowout $end
+$var wire 1 e diff $end
+$var wire 1 n nota $end
+$var wire 1 o notaandb $end
+$var wire 1 p notaxorb $end
+$var wire 1 q notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 T a $end
+$var wire 1 r axorb $end
+$var wire 1 U b $end
+$var wire 1 V borrowin $end
+$var wire 1 Y borrowout $end
+$var wire 1 d diff $end
+$var wire 1 s nota $end
+$var wire 1 t notaandb $end
+$var wire 1 u notaxorb $end
+$var wire 1 v notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 w address [2:0] $end
+$var wire 8 x inputs [7:0] $end
+$var wire 1 ^ out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 y address [2:0] $end
+$var wire 8 z inputs [7:0] $end
+$var wire 1 W out $end
+$upscope $end
+$upscope $end
+$scope module a2 $end
+$var wire 1 { a $end
+$var wire 1 | b $end
+$var wire 1 } cin $end
+$var wire 1 ~ cout $end
+$var wire 1 !" cout_ADD $end
+$var wire 1 "" cout_SLT $end
+$var wire 1 #" cout_SUB $end
+$var wire 8 $" muxCout [7:0] $end
+$var wire 8 %" muxRes [7:0] $end
+$var wire 3 &" op [2:0] $end
+$var wire 1 '" out $end
+$var wire 1 (" res_ADD $end
+$var wire 1 )" res_AND $end
+$var wire 1 *" res_NAND $end
+$var wire 1 +" res_NOR $end
+$var wire 1 ," res_OR $end
+$var wire 1 -" res_SLT $end
+$var wire 1 ." res_SUB $end
+$var wire 1 /" res_XOR $end
+$scope module adder $end
+$var wire 1 0" _carryin $end
+$var wire 1 { a $end
+$var wire 1 1" aandb $end
+$var wire 1 2" aorb $end
+$var wire 1 | b $end
+$var wire 1 } carryin $end
+$var wire 1 !" carryout $end
+$var wire 1 3" outputIfCarryin $end
+$var wire 1 4" outputIf_Carryin $end
+$var wire 1 5" s $end
+$var wire 1 (" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 { a $end
+$var wire 1 6" axorb $end
+$var wire 1 | b $end
+$var wire 1 } borrowin $end
+$var wire 1 #" borrowout $end
+$var wire 1 ." diff $end
+$var wire 1 7" nota $end
+$var wire 1 8" notaandb $end
+$var wire 1 9" notaxorb $end
+$var wire 1 :" notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 { a $end
+$var wire 1 ;" axorb $end
+$var wire 1 | b $end
+$var wire 1 } borrowin $end
+$var wire 1 "" borrowout $end
+$var wire 1 -" diff $end
+$var wire 1 <" nota $end
+$var wire 1 =" notaandb $end
+$var wire 1 >" notaxorb $end
+$var wire 1 ?" notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 @" address [2:0] $end
+$var wire 8 A" inputs [7:0] $end
+$var wire 1 '" out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 B" address [2:0] $end
+$var wire 8 C" inputs [7:0] $end
+$var wire 1 ~ out $end
+$upscope $end
+$upscope $end
+$scope module a3 $end
+$var wire 1 D" a $end
+$var wire 1 E" b $end
+$var wire 1 F" cin $end
+$var wire 1 G" cout $end
+$var wire 1 H" cout_ADD $end
+$var wire 1 I" cout_SLT $end
+$var wire 1 J" cout_SUB $end
+$var wire 8 K" muxCout [7:0] $end
+$var wire 8 L" muxRes [7:0] $end
+$var wire 3 M" op [2:0] $end
+$var wire 1 N" out $end
+$var wire 1 O" res_ADD $end
+$var wire 1 P" res_AND $end
+$var wire 1 Q" res_NAND $end
+$var wire 1 R" res_NOR $end
+$var wire 1 S" res_OR $end
+$var wire 1 T" res_SLT $end
+$var wire 1 U" res_SUB $end
+$var wire 1 V" res_XOR $end
+$scope module adder $end
+$var wire 1 W" _carryin $end
+$var wire 1 D" a $end
+$var wire 1 X" aandb $end
+$var wire 1 Y" aorb $end
+$var wire 1 E" b $end
+$var wire 1 F" carryin $end
+$var wire 1 H" carryout $end
+$var wire 1 Z" outputIfCarryin $end
+$var wire 1 [" outputIf_Carryin $end
+$var wire 1 \" s $end
+$var wire 1 O" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 D" a $end
+$var wire 1 ]" axorb $end
+$var wire 1 E" b $end
+$var wire 1 F" borrowin $end
+$var wire 1 J" borrowout $end
+$var wire 1 U" diff $end
+$var wire 1 ^" nota $end
+$var wire 1 _" notaandb $end
+$var wire 1 `" notaxorb $end
+$var wire 1 a" notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 D" a $end
+$var wire 1 b" axorb $end
+$var wire 1 E" b $end
+$var wire 1 F" borrowin $end
+$var wire 1 I" borrowout $end
+$var wire 1 T" diff $end
+$var wire 1 c" nota $end
+$var wire 1 d" notaandb $end
+$var wire 1 e" notaxorb $end
+$var wire 1 f" notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 g" address [2:0] $end
+$var wire 8 h" inputs [7:0] $end
+$var wire 1 N" out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 i" address [2:0] $end
+$var wire 8 j" inputs [7:0] $end
+$var wire 1 G" out $end
+$upscope $end
+$upscope $end
+$scope module a4 $end
+$var wire 1 k" a $end
+$var wire 1 l" b $end
+$var wire 1 m" cin $end
+$var wire 1 n" cout $end
+$var wire 1 o" cout_ADD $end
+$var wire 1 p" cout_SLT $end
+$var wire 1 q" cout_SUB $end
+$var wire 8 r" muxCout [7:0] $end
+$var wire 8 s" muxRes [7:0] $end
+$var wire 3 t" op [2:0] $end
+$var wire 1 u" out $end
+$var wire 1 v" res_ADD $end
+$var wire 1 w" res_AND $end
+$var wire 1 x" res_NAND $end
+$var wire 1 y" res_NOR $end
+$var wire 1 z" res_OR $end
+$var wire 1 {" res_SLT $end
+$var wire 1 |" res_SUB $end
+$var wire 1 }" res_XOR $end
+$scope module adder $end
+$var wire 1 ~" _carryin $end
+$var wire 1 k" a $end
+$var wire 1 !# aandb $end
+$var wire 1 "# aorb $end
+$var wire 1 l" b $end
+$var wire 1 m" carryin $end
+$var wire 1 o" carryout $end
+$var wire 1 ## outputIfCarryin $end
+$var wire 1 $# outputIf_Carryin $end
+$var wire 1 %# s $end
+$var wire 1 v" sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 k" a $end
+$var wire 1 &# axorb $end
+$var wire 1 l" b $end
+$var wire 1 m" borrowin $end
+$var wire 1 q" borrowout $end
+$var wire 1 |" diff $end
+$var wire 1 '# nota $end
+$var wire 1 (# notaandb $end
+$var wire 1 )# notaxorb $end
+$var wire 1 *# notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 k" a $end
+$var wire 1 +# axorb $end
+$var wire 1 l" b $end
+$var wire 1 m" borrowin $end
+$var wire 1 p" borrowout $end
+$var wire 1 {" diff $end
+$var wire 1 ,# nota $end
+$var wire 1 -# notaandb $end
+$var wire 1 .# notaxorb $end
+$var wire 1 /# notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 0# address [2:0] $end
+$var wire 8 1# inputs [7:0] $end
+$var wire 1 u" out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 2# address [2:0] $end
+$var wire 8 3# inputs [7:0] $end
+$var wire 1 n" out $end
+$upscope $end
+$upscope $end
+$scope module a5 $end
+$var wire 1 4# a $end
+$var wire 1 5# b $end
+$var wire 1 6# cin $end
+$var wire 1 7# cout $end
+$var wire 1 8# cout_ADD $end
+$var wire 1 9# cout_SLT $end
+$var wire 1 :# cout_SUB $end
+$var wire 8 ;# muxCout [7:0] $end
+$var wire 8 <# muxRes [7:0] $end
+$var wire 3 =# op [2:0] $end
+$var wire 1 ># out $end
+$var wire 1 ?# res_ADD $end
+$var wire 1 @# res_AND $end
+$var wire 1 A# res_NAND $end
+$var wire 1 B# res_NOR $end
+$var wire 1 C# res_OR $end
+$var wire 1 D# res_SLT $end
+$var wire 1 E# res_SUB $end
+$var wire 1 F# res_XOR $end
+$scope module adder $end
+$var wire 1 G# _carryin $end
+$var wire 1 4# a $end
+$var wire 1 H# aandb $end
+$var wire 1 I# aorb $end
+$var wire 1 5# b $end
+$var wire 1 6# carryin $end
+$var wire 1 8# carryout $end
+$var wire 1 J# outputIfCarryin $end
+$var wire 1 K# outputIf_Carryin $end
+$var wire 1 L# s $end
+$var wire 1 ?# sum $end
+$upscope $end
+$scope module subtractor $end
+$var wire 1 4# a $end
+$var wire 1 M# axorb $end
+$var wire 1 5# b $end
+$var wire 1 6# borrowin $end
+$var wire 1 :# borrowout $end
+$var wire 1 E# diff $end
+$var wire 1 N# nota $end
+$var wire 1 O# notaandb $end
+$var wire 1 P# notaxorb $end
+$var wire 1 Q# notaxorbandborrowin $end
+$upscope $end
+$scope module slt $end
+$var wire 1 4# a $end
+$var wire 1 R# axorb $end
+$var wire 1 5# b $end
+$var wire 1 6# borrowin $end
+$var wire 1 9# borrowout $end
+$var wire 1 D# diff $end
+$var wire 1 S# nota $end
+$var wire 1 T# notaandb $end
+$var wire 1 U# notaxorb $end
+$var wire 1 V# notaxorbandborrowin $end
+$upscope $end
+$scope module mux1 $end
+$var wire 3 W# address [2:0] $end
+$var wire 8 X# inputs [7:0] $end
+$var wire 1 ># out $end
+$upscope $end
+$scope module mux2 $end
+$var wire 3 Y# address [2:0] $end
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+$var wire 1 P/ out $end
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+$var wire 1 V/ out $end
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+$var wire 8 m/ inputs [7:0] $end
+$var wire 1 n/ out $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0n/
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+0k/
+b0 j/
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+0h/
+b0 g/
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+0Y/
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+0V/
+b0 U/
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+0S/
+b0 R/
+b0 Q/
+0P/
+b0 O/
+b0 N/
+1M/
+b11110111 L/
+b0 K/
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+b0 H/
+0G/
+b0 F/
+b0 E/
+0D/
+b0 C/
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From 9e9337ece78493a63d56c84be0eed1b00cc20178 Mon Sep 17 00:00:00 2001
From: dpapp <david.papp@students.olin.edu>
Date: Wed, 11 Oct 2017 16:39:35 -0400
Subject: [PATCH 51/52] gate delays

---
 alu.t.v     |     6 +-
 alu.v       |    10 +-
 alu.vcd     | 33371 +++++++++++++++++++++++++++++++-------------------
 muxTest.t.v |    26 +
 4 files changed, 20811 insertions(+), 12602 deletions(-)
 create mode 100644 muxTest.t.v

diff --git a/alu.t.v b/alu.t.v
index a4c7065..1ac50e2 100644
--- a/alu.t.v
+++ b/alu.t.v
@@ -175,11 +175,13 @@ module testALU ();
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 1, 1);
 
-    a=32'b0010000000000000000-000000000001; b=32'b10000000000000000000000000000000;#1000
+    a=32'b00100000000000000000000000000001; b=32'b10000000000000000000000000000000;#1000
     tests = tests + 1;
     passed_tests = passed_tests + test(out == 0, 1);
 
-
+    a=32'b10000000000000000000000000000000; b=32'b01111111111111111111111111111111;#1000
+    tests = tests + 1;
+    passed_tests = passed_tests + test(out == 1, 1);
     $display("%2d/%2d Test Cases Passed", passed_tests, tests);
 
     end
diff --git a/alu.v b/alu.v
index 13a9876..cfff904 100644
--- a/alu.v
+++ b/alu.v
@@ -8,6 +8,12 @@
 // b101 -> NAND
 // b110 -> NOR
 // b111 -> OR
+`define AND and #30
+`define OR or #30
+`define NOT not #10
+`define XOR xor #30
+`define NOR nor #20
+`define NAND nand #20
 
 `include "alu1bit.v"
 
@@ -56,12 +62,12 @@ module ALU
   ALU1bit a30(res_premux[29], cout[29], operandA[29], operandB[29], cout[28], command);
   ALU1bit a31(res_premux[30], cout[30], operandA[30], operandB[30], cout[29], command);
   ALU1bit a32(res_premux[31], carryout, operandA[31], operandB[31], cout[30], command);
-  xor(overflow, carryout, cout[30]);
+  `XOR(overflow, carryout, cout[30]);
 
   // We're using subtraction for SLT. We have to handle additional cases
   // for the cases where we have overflow.
   wire temp;
-  xor(temp, res_premux[31], overflow);
+  `XOR(temp, res_premux[31], overflow);
 
   // This mux is necessary for handling the SLT, since the desired result of the SLT 
   // is very different from the actual output from our ALU.
diff --git a/alu.vcd b/alu.vcd
index 3125b35..ba6d7b3 100644
--- a/alu.vcd
+++ b/alu.vcd
@@ -1,5 +1,5 @@
 $date
-	Wed Oct 11 15:51:17 2017
+	Wed Oct 11 16:32:49 2017
 $end
 $version
 	Icarus Verilog
@@ -2406,1387 +2406,1387 @@ $upscope $end
 $enddefinitions $end
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diff --git a/muxTest.t.v b/muxTest.t.v
new file mode 100644
index 0000000..7dd39ea
--- /dev/null
+++ b/muxTest.t.v
@@ -0,0 +1,26 @@
+// Multiplexer testbench
+`timescale 1 ns / 1 ps
+`include "alu1bit.v"
+
+module testMultiplexer ();
+  reg[2:0] address;
+  reg[7:0] inputs;
+  wire out;
+
+  //behavioralMultiplexer mux(out, addr0, addr1, in0, in1, in2, in3);
+  behavioralMultiplexer mux(out, address, inputs);
+
+  initial begin
+    $display("address | inputs   | Out | Expected Output");
+    inputs=8'b00000001;address=3'b000; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000100;address=3'b010; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b10000000;address=3'b111; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b01000000;address=3'b110; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b1);
+    inputs=8'b00000000;address=3'b100; #1000
+    $display("%b     | %b | %b   | %b", address, inputs, out, 1'b0);
+  end
+endmodule

From a158c87d59b03e96b938464b9916b5a0cbb21ab1 Mon Sep 17 00:00:00 2001
From: Jonah Spear <Jonahspear512@gmail.com>
Date: Wed, 11 Oct 2017 18:32:21 -0400
Subject: [PATCH 52/52] Update README.md

---
 README.md | 164 +-----------------------------------------------------
 1 file changed, 2 insertions(+), 162 deletions(-)

diff --git a/README.md b/README.md
index 4384391..a09bdd0 100644
--- a/README.md
+++ b/README.md
@@ -1,165 +1,5 @@
 # CompArch Lab 1: Arithmetic Logic Unit
 
-**Work plan due:** Wed. October 4
+#### Jonah Spear and David Papp
 
-**Lab due:** Thu. October 12
-
-
-This lab assignment creates the first component of your processor: the ALU.  Additionally, it will help you understand the timing constraints of your designs.
-
-You will work in groups of 2-3. You may shuffle teams from the first lab if you so choose. 
-
-## Specification ##
-
-The ALU you will implement is a subset of the standard MIPS ALU. The number of operations supported has been reduced, but otherwise we are emulating that standard.
-
-<img src="https://e38023e2-a-62cb3a1a-s-sites.googlegroups.com/site/ca15fall/resources/alu.png" width="200" alt="ALU diagram">
-
-
-| Operation	| Result 		| Sets flags?	| ALU Control 	|
-|-----------|---------------|---------------|---------------|
-| ADD		| `R=A+B`		| Yes			| `b000`		|
-| SUB		| `R=A-B`		| Yes			| `b001`		|
-| XOR		| `R=A^B`		| No			| `b010`		|
-| SLT		| `R=(A<B)?1:0`	| No			| `b011`		|
-| AND		| `R=A&B`		| No			| `b100`		|
-| NAND		| `R=~(A&B)`	| No			| `b101`		|
-| NOR		| `R=~(A|B)`	| No			| `b110`		|
-| OR		| `R=A|B`		| No			| `b111`		|
-
-
-Each group will construct ALUs with identical behaviors, but the internal structures will vary based on the design decisions you each make.
-
-The ALU must be implemented in `alu.v`, and its top-level module must have the following definition:
-
-```verilog
-module ALU
-(
-output[31:0]  result,
-output        carryout,
-output        zero,
-output        overflow,
-input[31:0]   operandA,
-input[31:0]   operandB,
-input[2:0]    command
-);
-	// Your code here
-endmodule
-```
-
-## Work Plan ##
-
-Draft a work plan for this lab.  Break down the lab in to small portions, and for each portion predict how long it will take (in hours) and when it will be done by (date).  You will be comparing your predictions to reality later.
-
-**Submit this plan by Wednesday, October 4** by pushing `work_plan.txt` to GitHub.
-
-## Deliverables ##
-
-### Verilog ###
-Construct an ALU that implements the specification above.  We recommend that you use a "Bitslice + Control Logic LUT" approach to designing your ALU.
-
-You must use structural Verilog (basic gates and modules wired together) for your ALU, with the exception of the Control Logic LUT.  You may use behavioral Verilog to describe this Look Up Table (see the Notes section below for details).
-
-You may freely reuse code created for previous labs and homeworks.  **Be sure to redo the timing!**
-
-#### Gate Delays ####
-
-In order to be slightly more accurate, we will model gate delay as proportional to the number of inputs in the gate.  Standardize on 10 units per input.  Therefore, an inverter has delay 10, a 32-input NAND gate has delay 320.  The basic gates are NAND, NOR, NOT. Gates such as AND, OR, etc all have "hidden" inverters that must be accounted for in your propagation delays.
-
-#### Documentation ####
-Code legibility and commenting matter! The key is to make sure that your code is "inheritable" – another designer should be able to understand what you were up to without re-inventing it. Use block comments at the top of your modules, and occasional comments within modules where appropriate to describe interesting details.  
-
-
-### Test Benches ###
-Construct a (set of) test bench(es) for your ALU and submodules as appropriate.  It is highly recommended that you create the tests before you create the ALU. Your top-level test harness must be in `alu.t.v` and instantiate the ALU module from `alu.v`.
-
-Be intelligent in your selection of your test cases. Making use of the hierarchy of your design will allow you to avoid exhaustive testing. Strive to make your test cases self-checking - detect and report errors, rather than forcing you to compare manually against expected behavior.
-
-
-### Report ###
-In this lab your team is designing the ALU subsystem. Write a report to the project manager in charge of the entire CPU demonstrating that your ALU design is complete, correct, and ready to be included in the CPU.
-
-#### Implementation ####
-
-Discuss any interesting design choices you made along the way.
-
-Include block diagrams of your ALU at an appropriate level of detail: the top-level diagram above is too abstract to say anything about your particular design, while a single figure with every AND gate and wire would be unintelligible. Use your hierarchy and organization to show the important pieces. If you took a Bitslice approach, you should show a single bit and how they fit together.
-
-#### Test Results ####
-For each ALU operation, include the following in your report:
-
-1. A written description of what tests you chose, and why you chose them.  This should be roughly a couple sentences per operation.
-1. Specific instances where your test bench caught a flaw in your design.
-1. As your ALU design evolves, you may find that new test cases should be added to your test bench.  This is a good thing.  When this happens, record specifically why these tests were added. 
-
-
-#### Timing Analysis ####
-Provide the worst case propagation delay for each of the operations of the ALU.  This can be calculated or simulated (preferably both).  Note: the propagation delay for some operations may depend heavily on your choice of operands.
-
-#### Work Plan Reflection ####
-Compare how long each unit work actually took to how long you predicted it would take.  This will help you better schedule future labs.
-
-
-## Submission ##
-Push your files to your team GitHub repository (the one listed on the team formation spreadsheet), and submit a pull request back to the course repository. It should include the following:
-
-1. Work plan (due 10/4)
-1. Report, as a self-contained PDF or MarkDown file
-1. ALU Verilog, with the specified top-level module in `alu.v`
-1. Test benches, including top-level `alu.t.v`
-1. Any scripts used for testing, commented or with a separate `README` on how to run everything and what to expect as output 
-
-
-## Hints/Notes ##
-
-### Define ###
-You can use the define syntax to make your code cleaner.  For example, consider labeling your ALU commands with defines:
-
-```verilog
-`define ADD  3'd0
-`define SUB  3'd1
-`define XOR  3'd2
-`define SLT  3'd3
-`define AND  3'd4
-`define NAND 3'd5
-`define NOR  3'd6
-`define OR   3'd7
-```
-
-### Control Logic LUT ###
-
-A useful approach for implementing complex systems in a CPU is to separate the datapath (regular, possibly bit-sliced) from the control (irregular). You may choose to implement the control logic in your ALU as a Look Up Table. One way to implement this in (behavioral) Verilog is below:
-
-```verilog
-module ALUcontrolLUT
-(
-output reg[2:0] 	muxindex,
-output reg	invertB,
-output reg	othercontrolsignal,
-...
-input[2:0]	ALUcommand
-)
-
-  always @(ALUcommand) begin
-    case (ALUcommand)
-      `ADD:  begin muxindex = 0; invertB=0; othercontrolsignal = ?; end    
-      `SUB:  begin muxindex = 0; invertB=1; othercontrolsignal = ?; end
-      `XOR:  begin muxindex = 1; invertB=0; othercontrolsignal = ?; end    
-      `SLT:  begin muxindex = 2; invertB=?; othercontrolsignal = ?; end
-      `AND:  begin muxindex = 3; invertB=?; othercontrolsignal = ?; end    
-      `NAND: begin muxindex = 3; invertB=?; othercontrolsignal = ?; end
-      `NOR:  begin muxindex = ?; invertB=?; othercontrolsignal = ?; end    
-      `OR:   begin muxindex = ?; invertB=?; othercontrolsignal = ?; end
-    endcase
-  end
-endmodule
-```
-
-An advantage of this syntax is that it explicitly states what each control signal does for each command.
-
-To add additional control signals: modify the module definition, add the corresponding `output reg` lines, and add the state of the lines in each case. Be careful to set each control signal in each case.  If you accidentally omit one, it will generate latches that you don’t want to implement the behavior that you don’t want.
-
-### Overflow ###
-Only ADD and SUB emit overflow signals per the MIPS specification.  The basic Boolean operations do not emit an overflow signal for obvious reasons, and during these operations that wire is always `false`.
-
-The SLT operation is a bit weird here.  To calculate SLT you do need to determine whether or not there was an overflow.  However, in SLT this signal is not propagated outside of the ALU.  This is because the processor interprets the overflow signal as an "emergency" situation and begins an exception handling process.  Overflows generated during SLT are expected and are not emergencies.
+The purpose of this lab is to implement a 32-bit ALU in Verilog. [For lab writeup see here.](https://docs.google.com/document/d/1hVpe1RlciXp57nrlVHNf2zgQpX9TBWAB4SeN_-JxTkc/edit?usp=sharing)