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+$date
+	Tue Oct 10 22:34:16 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
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+$var wire 1 # AllZeros2 $end
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+$var wire 32 % OneBitFinalOut [31:0] $end
+$var wire 32 & OneBitFinalOut2 [31:0] $end
+$var wire 32 ' OrNorXorOut [31:0] $end
+$var wire 32 ( SLTSum [31:0] $end
+$var wire 1 ) SLTflag $end
+$var wire 1 * SLTflag1 $end
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+$var wire 1 , carryout $end
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+$var wire 1 . overflow $end
+$var wire 1 / overflow2 $end
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+$var reg 32 2 B [31:0] $end
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+$var wire 1 bT in0 $end
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+$var wire 1 iT S1 $end
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+$var wire 1 TV in1 $end
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+$var wire 1 mV in1 $end
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diff --git a/OriginalTesting.t.v b/OriginalTesting.t.v
new file mode 100644
index 0000000..d4f68d2
--- /dev/null
+++ b/OriginalTesting.t.v
@@ -0,0 +1,128 @@
+
+module testMultiplexer ();
+wire AndNandOut;
+reg A, B;
+reg[2:0] Command;
+//reg S;
+wire OneBitFinalOut;
+wire AddSubSLTSum, carryout, subtract; //overflow, 
+reg carryin;
+wire OrNorXorOut;
+
+	//wire muxout;
+    //reg S0, S1;
+    //reg in0, in1, in2, in3;
+
+	wire Cmd0Start;
+	wire Cmd1Start; 
+	
+	wire nB;
+	wire BornB;
+	wire AxorB;
+	wire AandB;
+	wire CINandAxorB;
+
+	wire AnorB;
+	wire AorB;
+	wire AnandB;
+	wire nXor;
+	wire XorNor;
+
+	MiddleAddSubSLT testadd(AddSubSLTSum, carryout, subtract, A, B, Command, carryin);
+
+    AndNand newpotato(AndNandOut, A, B, Command); 
+
+	OrNorXor ortest(OrNorXorOut, A, B, Command);
+
+	Bitslice yukongoldpotato(OneBitFinalOut, AddSubSLTSum, carryout, OrNorXorOut, AndNandOut, subtract, A, B, Command, carryin);
+
+
+//FourInMux arbitrarypotato(muxout, S0, S1, in0, in1, in2, in3);
+
+initial begin
+
+// just the adder - proper behavior
+	$display("Adder/Subtractor");
+    $display("A B| Command |  Output | Expected Output");
+    A=1;B=1;Command=3'b000; carryin = 0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=1;B=1;Command=3'b001; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+
+// testing subtraction
+	$display("One Bitslice Adder/Subtractor");
+    $display("A B| Command |Out|ExOut|Carryout");
+    A=1;B=1;Command=3'b000; carryin=0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, OneBitFinalOut,  carryout);
+    A=1;B=0;Command=3'b000; carryin=0; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, OneBitFinalOut,  carryout);
+    A=0;B=0;Command=3'b000; carryin=0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, OneBitFinalOut,  carryout);
+
+    A=1;B=1;Command=3'b001; carryin=1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, OneBitFinalOut,  carryout);
+    A=1;B=0;Command=3'b001; carryin=1; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, OneBitFinalOut,  carryout);
+    A=0;B=0;Command=3'b001; carryin=1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, OneBitFinalOut,  carryout);
+
+
+    //$display("A B| Command |  Output | Expected Output- pure sadness");
+    //S0 = 1; S1 = 0; in0 = 1; in1 = 1; in2 = 0; in3 = 0; #1000 
+    //$display("%b  %b | %b %b %b %b |  %b | 1", S0, S1, in0, in1, in2, in3, muxout);
+
+// testing addition
+    $display("A B| Command |  Output | Expected Output-sadness|Carryout");
+    A=1;B=1;Command=3'b000; carryin=0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, OneBitFinalOut,  carryout);
+    A=1;B=0;Command=3'b000; carryin=0; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, OneBitFinalOut,  carryout);
+    A=0;B=0;Command=3'b000; carryin=0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, OneBitFinalOut,  carryout);
+
+
+// Exhaustively testing AND/NAND 
+    $display("A B| Command | command0 Output | Expected Output - AND TESTS");
+    A=1;B=1;Command=3'b000; #1000 
+    $display("%b  %b |   %b |  %b  %b | 1", A, B, Command, Command[0], AndNandOut);
+    A=1;B=1;Command=3'b001; #1000 
+    $display("%b  %b |   %b |  %b  %b | 0", A, B, Command, Command[1], AndNandOut);
+    A=0;B=1;Command=3'b000; #1000 
+    $display("%b  %b |   %b |  %b  %b | 0", A, B, Command, Command[0], AndNandOut);
+    A=1;B=0;Command=3'b001; #1000 
+    $display("%b  %b |   %b |  %b  %b | 1", A, B, Command, Command[1], AndNandOut);
+
+
+// Exhaustively testing OR/NOR/XOR
+    $display("A B | Command | Output | Expected Output - OR TESTS");
+	A=1; B=1; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 1 - OR TEST", A, B, Command, OrNorXorOut);
+	A=1; B=0; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 1 - OR TEST", A, B, Command, OrNorXorOut);
+	A=0; B=1; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 1 - OR TEST", A, B, Command, OrNorXorOut);
+	A=0; B=0; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 0 - OR TEST", A, B, Command, OrNorXorOut);
+
+
+	A=1; B=1; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 0 - NOR TEST", A, B, Command, OrNorXorOut);
+	A=1; B=0; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 0 - NOR TEST", A, B, Command, OrNorXorOut);
+	A=0; B=1; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 0 - NOR TEST", A, B, Command, OrNorXorOut);
+	A=0; B=0; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 1 - NOR TEST", A, B, Command, OrNorXorOut);
+
+	A=1; B=1; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 0 - XOR TEST", A, B, Command, OrNorXorOut);
+	A=1; B=0; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 1 - XOR TEST", A, B, Command, OrNorXorOut);
+	A=0; B=1; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 1 - XOR TEST", A, B, Command, OrNorXorOut);
+	A=0; B=0; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 0 - XOR TEST", A, B, Command, OrNorXorOut);
+
+    end
+
+endmodule
diff --git a/README.md b/README.md
deleted file mode 100644
index f6202d8..0000000
--- a/README.md
+++ /dev/null
@@ -1,165 +0,0 @@
-# CompArch Lab 1: Arithmetic Logic Unit
-
-**Work plan due:** Wed. October 4
-
-**Lab due:** Thu. October 12
-
-
-This lab assignment creates the first component of your processor: the ALU.  Additionally, it will help you understand the timing constraints of your designs.
-
-You will work in groups of 2-3. You may shuffle teams from the first lab if you so choose. 
-
-## Specification ##
-
-The ALU you will implement is a subset of the standard MIPS ALU. The number of operations supported has been reduced, but otherwise we are emulating that standard.
-
-<img src="https://e38023e2-a-62cb3a1a-s-sites.googlegroups.com/site/ca15fall/resources/alu.png" width="200" alt="ALU diagram">
-
-
-| Operation	| Result 		| Sets flags?	| ALU Control 	|
-|-----------|---------------|---------------|---------------|
-| ADD		| `R=A+B`		| Yes			| `b000`		|
-| SUB		| `R=A-B`		| Yes			| `b001`		|
-| XOR		| `R=A^B`		| No			| `b010`		|
-| SLT		| `R=(A<B)?1:0`	| No			| `b011`		|
-| AND		| `R=A&B`		| No			| `b100`		|
-| NAND		| `R=~(A&B)`	| No			| `b101`		|
-| NOR		| `R=~(A\|B)`	| No			| `b110`		|
-| OR		| `R=A\|B`		| No			| `b111`		|
-
-
-Each group will construct ALUs with identical behaviors, but the internal structures will vary based on the design decisions you each make.
-
-The ALU must be implemented in `alu.v`, and its top-level module must have the following definition:
-
-```verilog
-module ALU
-(
-output[31:0]  result,
-output        carryout,
-output        zero,
-output        overflow,
-input[31:0]   operandA,
-input[31:0]   operandB,
-input[2:0]    command
-);
-	// Your code here
-endmodule
-```
-
-## Work Plan ##
-
-Draft a work plan for this lab.  Break down the lab in to small portions, and for each portion predict how long it will take (in hours) and when it will be done by (date).  You will be comparing your predictions to reality later.
-
-**Submit this plan by Wednesday, October 4** by pushing `work_plan.txt` to GitHub.
-
-## Deliverables ##
-
-### Verilog ###
-Construct an ALU that implements the specification above.  We recommend that you use a "Bitslice + Control Logic LUT" approach to designing your ALU.
-
-You must use structural Verilog (basic gates and modules wired together) for your ALU, with the exception of the Control Logic LUT.  You may use behavioral Verilog to describe this Look Up Table (see the Notes section below for details).
-
-You may freely reuse code created for previous labs and homeworks.  **Be sure to redo the timing!**
-
-#### Gate Delays ####
-
-In order to be slightly more accurate, we will model gate delay as proportional to the number of inputs in the gate.  Standardize on 10 units per input.  Therefore, an inverter has delay 10, a 32-input NAND gate has delay 320.  The basic gates are NAND, NOR, NOT. Gates such as AND, OR, etc all have "hidden" inverters that must be accounted for in your propagation delays.
-
-#### Documentation ####
-Code legibility and commenting matter! The key is to make sure that your code is "inheritable" – another designer should be able to understand what you were up to without re-inventing it. Use block comments at the top of your modules, and occasional comments within modules where appropriate to describe interesting details.  
-
-
-### Test Benches ###
-Construct a (set of) test bench(es) for your ALU and submodules as appropriate.  It is highly recommended that you create the tests before you create the ALU. Your top-level test harness must be in `alu.t.v` and instantiate the ALU module from `alu.v`.
-
-Be intelligent in your selection of your test cases. Making use of the hierarchy of your design will allow you to avoid exhaustive testing. Strive to make your test cases self-checking - detect and report errors, rather than forcing you to compare manually against expected behavior.
-
-
-### Report ###
-In this lab your team is designing the ALU subsystem. Write a report to the project manager in charge of the entire CPU demonstrating that your ALU design is complete, correct, and ready to be included in the CPU.
-
-#### Implementation ####
-
-Discuss any interesting design choices you made along the way.
-
-Include block diagrams of your ALU at an appropriate level of detail: the top-level diagram above is too abstract to say anything about your particular design, while a single figure with every AND gate and wire would be unintelligible. Use your hierarchy and organization to show the important pieces. If you took a Bitslice approach, you should show a single bit and how they fit together.
-
-#### Test Results ####
-For each ALU operation, include the following in your report:
-
-1. A written description of what tests you chose, and why you chose them.  This should be roughly a couple sentences per operation.
-1. Specific instances where your test bench caught a flaw in your design.
-1. As your ALU design evolves, you may find that new test cases should be added to your test bench.  This is a good thing.  When this happens, record specifically why these tests were added. 
-
-
-#### Timing Analysis ####
-Provide the worst case propagation delay for each of the operations of the ALU.  This can be calculated or simulated (preferably both).  Note: the propagation delay for some operations may depend heavily on your choice of operands.
-
-#### Work Plan Reflection ####
-Compare how long each unit work actually took to how long you predicted it would take.  This will help you better schedule future labs.
-
-
-## Submission ##
-Push your files to your team GitHub repository (the one listed on the team formation spreadsheet), and submit a pull request back to the course repository. It should include the following:
-
-1. Work plan (due 10/4)
-1. Report, as a self-contained PDF or MarkDown file
-1. ALU Verilog, with the specified top-level module in `alu.v`
-1. Test benches, including top-level `alu.t.v`
-1. Any scripts used for testing, commented or with a separate `README` on how to run everything and what to expect as output 
-
-
-## Hints/Notes ##
-
-### Define ###
-You can use the define syntax to make your code cleaner.  For example, consider labeling your ALU commands with defines:
-
-```verilog
-`define ADD  3'd0
-`define SUB  3'd1
-`define XOR  3'd2
-`define SLT  3'd3
-`define AND  3'd4
-`define NAND 3'd5
-`define NOR  3'd6
-`define OR   3'd7
-```
-
-### Control Logic LUT ###
-
-A useful approach for implementing complex systems in a CPU is to separate the datapath (regular, possibly bit-sliced) from the control (irregular). You may choose to implement the control logic in your ALU as a Look Up Table. One way to implement this in (behavioral) Verilog is below:
-
-```verilog
-module ALUcontrolLUT
-(
-output reg[2:0] 	muxindex,
-output reg	invertB,
-output reg	othercontrolsignal,
-...
-input[2:0]	ALUcommand
-)
-
-  always @(ALUcommand) begin
-    case (ALUcommand)
-      `ADD:  begin muxindex = 0; invertB=0; othercontrolsignal = ?; end    
-      `SUB:  begin muxindex = 0; invertB=1; othercontrolsignal = ?; end
-      `XOR:  begin muxindex = 1; invertB=0; othercontrolsignal = ?; end    
-      `SLT:  begin muxindex = 2; invertB=?; othercontrolsignal = ?; end
-      `AND:  begin muxindex = 3; invertB=?; othercontrolsignal = ?; end    
-      `NAND: begin muxindex = 3; invertB=?; othercontrolsignal = ?; end
-      `NOR:  begin muxindex = ?; invertB=?; othercontrolsignal = ?; end    
-      `OR:   begin muxindex = ?; invertB=?; othercontrolsignal = ?; end
-    endcase
-  end
-endmodule
-```
-
-An advantage of this syntax is that it explicitly states what each control signal does for each command.
-
-To add additional control signals: modify the module definition, add the corresponding `output reg` lines, and add the state of the lines in each case. Be careful to set each control signal in each case.  If you accidentally omit one, it will generate latches that you don’t want to implement the behavior that you don’t want.
-
-### Overflow ###
-Only ADD and SUB emit overflow signals per the MIPS specification.  The basic Boolean operations do not emit an overflow signal for obvious reasons, and during these operations that wire is always `false`.
-
-The SLT operation is a bit weird here.  To calculate SLT you do need to determine whether or not there was an overflow.  However, in SLT this signal is not propagated outside of the ALU.  This is because the processor interprets the overflow signal as an "emergency" situation and begins an exception handling process.  Overflows generated during SLT are expected and are not emergencies.
diff --git a/SmallALU.vcd b/SmallALU.vcd
new file mode 100644
index 0000000..20369c7
--- /dev/null
+++ b/SmallALU.vcd
@@ -0,0 +1,7467 @@
+$date
+	Tue Oct 10 14:53:02 2017
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module Bitslice32 $end
+$var wire 32 ! A [31:0] $end
+$var wire 32 " AddSubSLTSum [31:0] $end
+$var wire 1 # AllZeros $end
+$var wire 32 $ AndNandOut [31:0] $end
+$var wire 32 % B [31:0] $end
+$var wire 32 & Cmd0Start [31:0] $end
+$var wire 32 ' Cmd1Start [31:0] $end
+$var wire 3 ( Command [2:0] $end
+$var wire 32 ) OneBitFinalOut [31:0] $end
+$var wire 32 * OrNorXorOut [31:0] $end
+$var wire 1 + SLTflag $end
+$var wire 32 , ZeroFlag [31:0] $end
+$var wire 32 - carryin [31:0] $end
+$var wire 1 . carryout $end
+$var wire 1 / overflow $end
+$var wire 32 0 subtract [31:0] $end
+$var wire 1 1 yeszero $end
+$scope module trial $end
+$var wire 32 2 A [31:0] $end
+$var wire 32 3 AddSubSLTSum [31:0] $end
+$var wire 32 4 B [31:0] $end
+$var wire 32 5 CarryoutWire [31:0] $end
+$var wire 3 6 Command [2:0] $end
+$var wire 1 7 Res0OF1 $end
+$var wire 1 8 Res1OF0 $end
+$var wire 1 + SLTflag $end
+$var wire 1 9 SLTflag0 $end
+$var wire 1 : SLTflag1 $end
+$var wire 1 ; SLTon $end
+$var wire 32 < carryin [31:0] $end
+$var wire 1 . carryout $end
+$var wire 1 = nAddSubSLTSum $end
+$var wire 1 > nOF $end
+$var wire 1 / overflow $end
+$var wire 32 ? subtract [31:0] $end
+$scope module attempt2 $end
+$var wire 1 @ A $end
+$var wire 1 A AandB $end
+$var wire 1 B AddSubSLTSum $end
+$var wire 1 C AxorB $end
+$var wire 1 D B $end
+$var wire 1 E BornB $end
+$var wire 1 F CINandAxorB $end
+$var wire 3 G Command [2:0] $end
+$var wire 1 H carryin $end
+$var wire 1 I carryout $end
+$var wire 1 J nB $end
+$var wire 1 K nCmd2 $end
+$var wire 1 L subtract $end
+$scope module mux0 $end
+$var wire 1 M S $end
+$var wire 1 D in0 $end
+$var wire 1 J in1 $end
+$var wire 1 N nS $end
+$var wire 1 O out0 $end
+$var wire 1 P out1 $end
+$var wire 1 E outfinal $end
+$upscope $end
+$upscope $end
+$scope begin addbits[1] $end
+$scope module attempt $end
+$var wire 1 Q A $end
+$var wire 1 R AandB $end
+$var wire 1 S AddSubSLTSum $end
+$var wire 1 T AxorB $end
+$var wire 1 U B $end
+$var wire 1 V BornB $end
+$var wire 1 W CINandAxorB $end
+$var wire 3 X Command [2:0] $end
+$var wire 1 Y carryin $end
+$var wire 1 Z carryout $end
+$var wire 1 [ nB $end
+$var wire 1 \ nCmd2 $end
+$var wire 1 ] subtract $end
+$scope module mux0 $end
+$var wire 1 ^ S $end
+$var wire 1 U in0 $end
+$var wire 1 [ in1 $end
+$var wire 1 _ nS $end
+$var wire 1 ` out0 $end
+$var wire 1 a out1 $end
+$var wire 1 V outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[2] $end
+$scope module attempt $end
+$var wire 1 b A $end
+$var wire 1 c AandB $end
+$var wire 1 d AddSubSLTSum $end
+$var wire 1 e AxorB $end
+$var wire 1 f B $end
+$var wire 1 g BornB $end
+$var wire 1 h CINandAxorB $end
+$var wire 3 i Command [2:0] $end
+$var wire 1 j carryin $end
+$var wire 1 k carryout $end
+$var wire 1 l nB $end
+$var wire 1 m nCmd2 $end
+$var wire 1 n subtract $end
+$scope module mux0 $end
+$var wire 1 o S $end
+$var wire 1 f in0 $end
+$var wire 1 l in1 $end
+$var wire 1 p nS $end
+$var wire 1 q out0 $end
+$var wire 1 r out1 $end
+$var wire 1 g outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[3] $end
+$scope module attempt $end
+$var wire 1 s A $end
+$var wire 1 t AandB $end
+$var wire 1 u AddSubSLTSum $end
+$var wire 1 v AxorB $end
+$var wire 1 w B $end
+$var wire 1 x BornB $end
+$var wire 1 y CINandAxorB $end
+$var wire 3 z Command [2:0] $end
+$var wire 1 { carryin $end
+$var wire 1 | carryout $end
+$var wire 1 } nB $end
+$var wire 1 ~ nCmd2 $end
+$var wire 1 !" subtract $end
+$scope module mux0 $end
+$var wire 1 "" S $end
+$var wire 1 w in0 $end
+$var wire 1 } in1 $end
+$var wire 1 #" nS $end
+$var wire 1 $" out0 $end
+$var wire 1 %" out1 $end
+$var wire 1 x outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[4] $end
+$scope module attempt $end
+$var wire 1 &" A $end
+$var wire 1 '" AandB $end
+$var wire 1 (" AddSubSLTSum $end
+$var wire 1 )" AxorB $end
+$var wire 1 *" B $end
+$var wire 1 +" BornB $end
+$var wire 1 ," CINandAxorB $end
+$var wire 3 -" Command [2:0] $end
+$var wire 1 ." carryin $end
+$var wire 1 /" carryout $end
+$var wire 1 0" nB $end
+$var wire 1 1" nCmd2 $end
+$var wire 1 2" subtract $end
+$scope module mux0 $end
+$var wire 1 3" S $end
+$var wire 1 *" in0 $end
+$var wire 1 0" in1 $end
+$var wire 1 4" nS $end
+$var wire 1 5" out0 $end
+$var wire 1 6" out1 $end
+$var wire 1 +" outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[5] $end
+$scope module attempt $end
+$var wire 1 7" A $end
+$var wire 1 8" AandB $end
+$var wire 1 9" AddSubSLTSum $end
+$var wire 1 :" AxorB $end
+$var wire 1 ;" B $end
+$var wire 1 <" BornB $end
+$var wire 1 =" CINandAxorB $end
+$var wire 3 >" Command [2:0] $end
+$var wire 1 ?" carryin $end
+$var wire 1 @" carryout $end
+$var wire 1 A" nB $end
+$var wire 1 B" nCmd2 $end
+$var wire 1 C" subtract $end
+$scope module mux0 $end
+$var wire 1 D" S $end
+$var wire 1 ;" in0 $end
+$var wire 1 A" in1 $end
+$var wire 1 E" nS $end
+$var wire 1 F" out0 $end
+$var wire 1 G" out1 $end
+$var wire 1 <" outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[6] $end
+$scope module attempt $end
+$var wire 1 H" A $end
+$var wire 1 I" AandB $end
+$var wire 1 J" AddSubSLTSum $end
+$var wire 1 K" AxorB $end
+$var wire 1 L" B $end
+$var wire 1 M" BornB $end
+$var wire 1 N" CINandAxorB $end
+$var wire 3 O" Command [2:0] $end
+$var wire 1 P" carryin $end
+$var wire 1 Q" carryout $end
+$var wire 1 R" nB $end
+$var wire 1 S" nCmd2 $end
+$var wire 1 T" subtract $end
+$scope module mux0 $end
+$var wire 1 U" S $end
+$var wire 1 L" in0 $end
+$var wire 1 R" in1 $end
+$var wire 1 V" nS $end
+$var wire 1 W" out0 $end
+$var wire 1 X" out1 $end
+$var wire 1 M" outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[7] $end
+$scope module attempt $end
+$var wire 1 Y" A $end
+$var wire 1 Z" AandB $end
+$var wire 1 [" AddSubSLTSum $end
+$var wire 1 \" AxorB $end
+$var wire 1 ]" B $end
+$var wire 1 ^" BornB $end
+$var wire 1 _" CINandAxorB $end
+$var wire 3 `" Command [2:0] $end
+$var wire 1 a" carryin $end
+$var wire 1 b" carryout $end
+$var wire 1 c" nB $end
+$var wire 1 d" nCmd2 $end
+$var wire 1 e" subtract $end
+$scope module mux0 $end
+$var wire 1 f" S $end
+$var wire 1 ]" in0 $end
+$var wire 1 c" in1 $end
+$var wire 1 g" nS $end
+$var wire 1 h" out0 $end
+$var wire 1 i" out1 $end
+$var wire 1 ^" outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[8] $end
+$scope module attempt $end
+$var wire 1 j" A $end
+$var wire 1 k" AandB $end
+$var wire 1 l" AddSubSLTSum $end
+$var wire 1 m" AxorB $end
+$var wire 1 n" B $end
+$var wire 1 o" BornB $end
+$var wire 1 p" CINandAxorB $end
+$var wire 3 q" Command [2:0] $end
+$var wire 1 r" carryin $end
+$var wire 1 s" carryout $end
+$var wire 1 t" nB $end
+$var wire 1 u" nCmd2 $end
+$var wire 1 v" subtract $end
+$scope module mux0 $end
+$var wire 1 w" S $end
+$var wire 1 n" in0 $end
+$var wire 1 t" in1 $end
+$var wire 1 x" nS $end
+$var wire 1 y" out0 $end
+$var wire 1 z" out1 $end
+$var wire 1 o" outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[9] $end
+$scope module attempt $end
+$var wire 1 {" A $end
+$var wire 1 |" AandB $end
+$var wire 1 }" AddSubSLTSum $end
+$var wire 1 ~" AxorB $end
+$var wire 1 !# B $end
+$var wire 1 "# BornB $end
+$var wire 1 ## CINandAxorB $end
+$var wire 3 $# Command [2:0] $end
+$var wire 1 %# carryin $end
+$var wire 1 &# carryout $end
+$var wire 1 '# nB $end
+$var wire 1 (# nCmd2 $end
+$var wire 1 )# subtract $end
+$scope module mux0 $end
+$var wire 1 *# S $end
+$var wire 1 !# in0 $end
+$var wire 1 '# in1 $end
+$var wire 1 +# nS $end
+$var wire 1 ,# out0 $end
+$var wire 1 -# out1 $end
+$var wire 1 "# outfinal $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope begin addbits[10] $end
+$scope module attempt $end
+$var wire 1 .# A $end
+$var wire 1 /# AandB $end
+$var wire 1 0# AddSubSLTSum $end
+$var wire 1 1# AxorB $end
+$var wire 1 2# B $end
+$var wire 1 3# BornB $end
+$var wire 1 4# CINandAxorB $end
+$var wire 3 5# Command [2:0] $end
+$var wire 1 6# carryin $end
+$var wire 1 7# carryout $end
+$var wire 1 8# nB $end
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diff --git a/alu.v b/alu.v
new file mode 100644
index 0000000..3ec7989
--- /dev/null
+++ b/alu.v
@@ -0,0 +1,372 @@
+`define AND and #20     // nand with nor is 20 
+`define NAND nand #10   // base is 10
+`define NOT not #10     // not base is 10
+`define OR or #20       // nor with not is 20
+`define NOR nor #10     // base is 10 
+`define XOR xor #40     // and with or is 40
+
+
+// This module is the same as the BitSlice32 module at the very end. We wrote BitSlice32 before ALU, and we only created ALU at the end as the cleanest version of our work.
+module ALU
+(
+output[31:0]  result, // OneBitFinalOut
+output        carryout,
+output        zero, //AllZeros
+output        overflow,
+input[31:0]   operandA, // A
+input[31:0]   operandB, // B
+input[2:0]    command //Command
+);
+
+	parameter size = 32;
+	wire [size-1:0] Cmd0Start;
+    	wire [size-1:0] Cmd1Start; 
+    	wire [size-1:0] CarryoutWire;
+	wire yeszero;
+	wire [size-1:0] NewVal; 
+	wire [size-1:0] SLTSum;
+	wire [size-1:0] ZeroFlag;
+	wire [size-1:0] carryin;
+	wire [size-1:0] subtract;
+	wire SLTflag;
+	wire [size-1:0] AndNandOut;
+	wire [size-1:0] OrNorXorOut;
+	wire [size-1:0] AddSubSLTSum;
+ 
+	SLT32 test(SLTSum, carryout, overflow, SLTflag, subtract, operandA, operandB, command, carryin);
+	AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, subtract, operandA, operandB, command, carryin);
+	AndNand32 trial1(AndNandOut, operandA, operandB, command);
+	OrNorXor32 trial2(OrNorXorOut, operandA, operandB, command);
+     
+	FourInMux ZeroMux0case(Cmd0Start[0], command[0], command[1], AddSubSLTSum[0], AddSubSLTSum[0], OrNorXorOut[0], SLTSum[0]);	 			
+	FourInMux OneMux0case(Cmd1Start[0], command[0], command[1], AndNandOut[0], AndNandOut[0], OrNorXorOut[0], OrNorXorOut[0]);
+	TwoInMux TwoMux0case(result[0], command[2], Cmd0Start[0], Cmd1Start[0]);
+	`AND setZerothZero(ZeroFlag[0], result[0], result[0]);	
+           
+	genvar i; 
+	generate 
+    	for (i=1; i<size; i=i+1)
+        	begin: muxbits
+            	FourInMux ZeroMux(Cmd0Start[i], command[0], command[1], AddSubSLTSum[i], AddSubSLTSum[i], OrNorXorOut[i], SLTSum[i]);	 			
+				FourInMux OneMux(Cmd1Start[i], command[0], command[1], AndNandOut[i], AndNandOut[i], OrNorXorOut[i], OrNorXorOut[i]);
+                TwoInMux TwoMux(result[i], command[2], Cmd0Start[i], Cmd1Start[i]);
+
+		`OR zeroflagtest(ZeroFlag[i], ZeroFlag[i-1], result[i]);     
+		end        
+    endgenerate 
+
+
+	// the "zeros" flag depends on the final answer. It is only triggered when the final result is all zeros
+	`NOT invzeroflag(yeszero, ZeroFlag[size-1]);
+	`AND setzeros(zero, yeszero, yeszero);
+
+endmodule
+
+
+
+
+module TwoInMux // this module is a two input mux that takes in two inputs (in0 and in1) and uses switch S to pick the value for outfinal
+(
+    output outfinal,
+    input S,
+    input in0, in1
+);   
+    wire nS; 
+    wire out0; 
+    wire out1; 
+
+    `NOT Sinv(nS, S);   
+    `AND andgate1(out0, in0, nS);
+    `AND andgate3(out1, in1, S);
+    `OR orgate(outfinal, out0, out1);
+endmodule
+
+module FourInMux // this module is a four input mux that takes in four inputs (in0, in1, in2, and in3) and uses switches S0 and S1 to pick the value for out
+(
+    output out,
+    input S0, S1,
+    input in0, in1, in2, in3
+);
+    wire nS0; 
+    wire nS1; 
+
+    wire out0; 
+    wire out1; 
+    wire out2; 
+    wire out3; 
+
+    `NOT S0inv(nS0, S0);
+    `NOT S1inv(nS1, S1);
+    `NAND n0(out0, nS0, nS1, in0);
+    `NAND n1(out1, S0,  nS1, in1);
+    `NAND n2(out2, nS0, S1, in2);
+    `NAND n3(out3, S0,  S1, in3);
+
+    `NAND addthem(out, out0, out1, out2, out3);
+endmodule
+
+module AndNand // Uses Command[0] to determine whether and or nand is chosen
+(
+output AndNandOut, 
+input A, B, 
+input[2:0] Command
+);
+
+	wire AnandB;
+	wire AandB;
+
+	`NAND n0(AnandB, A, B);
+	`NOT Ainv(AandB, AnandB);
+	TwoInMux potato(AndNandOut, Command[0], AandB, AnandB);    // order to follow out,S,in0, in1
+
+endmodule
+
+module OrNorXor
+(
+output OrNorXorOut, // uses both Command[0] and Command[2] to determine whether Or, Nor, or Xor is used
+input A, B,
+input[2:0] Command
+);
+	wire AnorB;
+	wire AorB;
+	wire AnandB;
+	wire nXor;
+	wire AxorB;
+	wire XorNor;
+
+	`NOR nor0(AnorB, A, B);
+    `NOT n0(AorB, AnorB);
+    `NAND and0(AnandB, A, B);
+    `NAND and1(nXor, AnandB, AorB);
+    `NOT n1(AxorB, nXor);
+
+    TwoInMux mux0(XorNor, Command[2], AxorB, AnorB);
+    TwoInMux mux1(OrNorXorOut, Command[0], XorNor, AorB);
+endmodule
+
+// this module calculates addition, subtraction, and SLT based on which command is selected. SLT happens when A<B, or when A-B < 0. SLT is only calculated with the most significant bit, so it is not used in this smaller module. We use the adder/subtractor like we discussed in class
+module MiddleAddSubSLT 
+(
+output AddSubSLTSum, carryout, //overflow is only calculated for the most significant bit, while this is a generic adder/subtractor
+output subtract, 
+input A, B,
+input[2:0] Command, 
+input carryin  
+);
+	wire nB;
+	wire BornB;
+    wire AxorB;
+    wire AandB;
+    wire CINandAxorB;
+    wire nCmd2;
+                
+	`NOT Binv(nB, B);
+    TwoInMux mux0(BornB, Command[0], B, nB); 
+    `NOT n0(nCmd2, Command[2]);
+    `AND subtractchoose(subtract, Command[0], nCmd2); 
+    `XOR XOR1(AxorB, A, BornB); 
+    `XOR XOR2(AddSubSLTSum, AxorB, carryin); 
+    `AND AND1(AandB, A, BornB); 
+    `AND AND2(CINandAxorB, AxorB, carryin);
+    `OR OR1(carryout, AandB, CINandAxorB); 
+endmodule
+
+// this module creates a 32-bit AND/NAND module
+module AndNand32
+(
+output [size-1:0] AndNandOut, 
+input [size-1:0] A,
+input [size-1:0] B, 
+input[2:0] Command
+);
+	parameter size = 32; // set the parameter size to whatever length you want
+	wire AnandB;
+	wire AandB;
+
+	AndNand attempt2(AndNandOut[0], A[0], B[0], Command); // set the zeroth condition. This is only important for the ADD/SUB/SLT functions, but we do it for all for consistency
+
+	genvar i; 
+	generate 
+    	for (i=1; i<size; i=i+1)
+        	begin: andbits
+            AndNand attempt(AndNandOut[i], A[i], B[i], Command); 
+            end        
+    endgenerate     
+endmodule
+
+// this module creates a 32-bit OR/NOR/XOR module
+module OrNorXor32
+(
+output [size-1:0] OrNorXorOut,
+input [size-1:0] A,
+input [size-1:0] B,
+input[2:0] Command
+);
+	parameter size = 32; // set the parameter size to whatever length you want
+	wire AnorB;
+	wire AorB;
+	wire AnandB;
+	wire nXor;
+	wire AxorB;
+	wire XorNor;
+
+	OrNorXor attempt2(OrNorXorOut[0], A[0], B[0], Command); // set the zeroth condition. This is only important for the ADD/SUB/SLT module, but we do it for all for consistency
+
+	genvar i; 
+    generate 
+    	for (i=1; i<size; i=i+1)
+        	begin: orbits
+            OrNorXor attempt(OrNorXorOut[i], A[i], B[i], Command); 
+            end        
+        endgenerate 
+endmodule
+
+
+// this module creates a 32-bit ADD/SUB module. We originally tried to combine ADD, SUB, and SLT since the three are connected, but SLT proved too tricky to include with ADD & SUB, so we moved it down to SLT32. 
+module AddSubSLT32
+(
+output [size-1:0]AddSubSLTSum, 
+output carryout,      
+output overflow, 
+output [size-1:0]subtract, 
+input [size-1:0] A, B, 
+input [2:0] Command,
+input [size-1:0]carryin  // we think this doesn't do anything but don't want to break everything
+);
+    wire [size-1:0] CarryoutWire; // this is used to internally connect each of the 32 bitslices
+	MiddleAddSubSLT attempt2(AddSubSLTSum[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]);
+      
+	genvar i; 
+	parameter size = 32; 
+	generate 
+    	for (i=1; i<size; i=i+1)
+        	begin: addbits
+            MiddleAddSubSLT attempt(AddSubSLTSum[i], CarryoutWire[i], subtract[i], A[i], B[i], Command, CarryoutWire[i-1]); 
+            end        
+    endgenerate 
+
+	
+	//set final carryout value - this will be used for calculating overflow and SLT
+	`OR finalcarryout(carryout, CarryoutWire[size-1], 0);
+
+	// check for overflow - does the final carryin = final carryout?
+	`XOR overflowcheck(overflow, carryout, CarryoutWire[size-2]);
+endmodule
+
+// this module creates a 32-bit SLT module
+module SLT32
+(
+output [size-1:0]SLTSum, 
+output carryout,      
+output overflow, 
+output SLTflag,
+output [size-1:0]subtract, 
+input [size-1:0] A, B, 
+input [2:0] Command,
+input [size-1:0]carryin  // we think this doesn't do anything but don't want to break everything
+);
+    wire [size-1:0] CarryoutWire; // this is used to internally connect each of the 32 bitslices
+    wire [size-1:0] NewVal; // this is used to internally connect each of the 32 bitslices
+	wire [size-1:0]AddSubSLTSum; 
+	wire SLTon;
+	wire nOF;
+	wire nAddSubSLTSum;
+	wire Res1OF0;
+	wire Res0OF1;
+	wire SLTflag0;
+	wire SLTflag1;
+	wire nCmd2;
+               
+    `NOT n0(nCmd2, Command[2]);
+
+// we do weird things where we do subtraction to produce NewVal, then assign either NewVal or 0 to AddSubSLTSum (since if SLT is triggered, every bit except maybe the least significant will be 0), and then determine whether A<B at the very end, when we set the least significant bit to 0 or 1 depending 
+
+	`AND sltcheck0(SLTon, Command[0], Command[1], nCmd2);
+    MiddleAddSubSLT attempt2(NewVal[0], CarryoutWire[0], subtract[0], A[0], B[0], Command, subtract[0]);
+     TwoInMux setSLTresult(AddSubSLTSum[0], SLTon, NewVal[0], 0);
+
+	genvar i; 
+	parameter size = 32; 
+	generate 
+    	for (i=1; i<size; i=i+1)
+        	begin: sltbits
+            MiddleAddSubSLT attempt(NewVal[i], CarryoutWire[i], subtract[i], A[i], B[i], Command, CarryoutWire[i-1]); 
+			TwoInMux setSLTres2(AddSubSLTSum[i], SLTon, NewVal[i], 0);
+			TwoInMux setSLTres3(SLTSum[i], SLTon, AddSubSLTSum[i], AddSubSLTSum[i]);	
+            end        
+    endgenerate 
+	
+	//set final carryout value - this will be used for calculating overflow and SLT
+	`OR finalcarryout(carryout, CarryoutWire[size-1], 0);
+
+	// check for overflow - does the final carryin = final carryout?
+	`XOR overflowcheck(overflow, carryout, CarryoutWire[size-2]);
+
+	// check whether A < B
+	`NOT invOF(nOF, overflow);
+	`NOT invAddSub(nAddSubSLTSum, AddSubSLTSum[size-1]); 
+	`AND sltint0(Res1OF0, nOF, NewVal[size-1]);
+	`AND sltint1(Res0OF1, overflow, nAddSubSLTSum);
+	`AND sltint2(SLTflag0, Res1OF0, SLTon);
+	`AND sltint3(SLTflag1, Res0OF1, SLTon);
+	`OR sltcheck1(SLTflag, SLTflag0, SLTflag1);
+     TwoInMux FinalSLT(SLTSum[0], SLTflag, AddSubSLTSum[0], SLTflag);
+
+endmodule
+
+// this module combines the 32 bit ADD/SUB, the 32 bit SLT, 32 bit OR/NOR/XOR, and the 32 bit AND/NAND
+// We do this by using a series of final multiplexers to get the correct result based on what Command is calling for
+module Bitslice32
+(
+output  [size-1:0] OneBitFinalOut, 
+output  [size-1:0]AddSubSLTSum, 
+output  [size-1:0]SLTSum, 
+output carryout, 
+output overflow, 
+output SLTflag,
+output  [size-1:0] OrNorXorOut,
+output  [size-1:0] AndNandOut,
+output  [size-1:0] subtract,
+output [size-1:0] ZeroFlag,
+output AllZeros,
+input  [size-1:0] A, 
+input  [size-1:0] B, 
+input[2:0] Command,
+input [size-1:0]carryin // don't think this does anything but don't want to break it!
+);
+	parameter size = 32;
+	wire [size-1:0] Cmd0Start;
+    wire [size-1:0] Cmd1Start; 
+    wire [size-1:0] CarryoutWire;
+	wire yeszero;
+wire [size-1:0] NewVal; 
+ 
+	SLT32 test(SLTSum, carryout, overflow, SLTflag, subtract, A, B, Command, carryin);
+	AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, subtract, A, B, Command, carryin);
+	AndNand32 trial1(AndNandOut, A, B, Command);
+	OrNorXor32 trial2(OrNorXorOut, A, B, Command);
+     
+	FourInMux ZeroMux0case(Cmd0Start[0], Command[0], Command[1], AddSubSLTSum[0], AddSubSLTSum[0], OrNorXorOut[0], SLTSum[0]);	 			
+	FourInMux OneMux0case(Cmd1Start[0], Command[0], Command[1], AndNandOut[0], AndNandOut[0], OrNorXorOut[0], OrNorXorOut[0]);
+	TwoInMux TwoMux0case(OneBitFinalOut[0], Command[2], Cmd0Start[0], Cmd1Start[0]);
+	`AND setZerothZero(ZeroFlag[0], OneBitFinalOut[0], OneBitFinalOut[0]);	
+           
+	genvar i; 
+	generate 
+    	for (i=1; i<size; i=i+1)
+        	begin: muxbits
+            	FourInMux ZeroMux(Cmd0Start[i], Command[0], Command[1], AddSubSLTSum[i], AddSubSLTSum[i], OrNorXorOut[i], SLTSum[i]);	 			
+				FourInMux OneMux(Cmd1Start[i], Command[0], Command[1], AndNandOut[i], AndNandOut[i], OrNorXorOut[i], OrNorXorOut[i]);
+                TwoInMux TwoMux(OneBitFinalOut[i], Command[2], Cmd0Start[i], Cmd1Start[i]);
+
+		`OR zeroflagtest(ZeroFlag[i], ZeroFlag[i-1], OneBitFinalOut[i]);     
+		end        
+    endgenerate 
+
+
+	// the "zeros" flag depends on the final answer. It is only triggered when the final result is all zeros
+	`NOT invzeroflag(yeszero, ZeroFlag[size-1]);
+	`AND setzeros(AllZeros, yeszero, yeszero);
+
+endmodule 
+
diff --git a/test b/test
new file mode 100755
index 0000000..afdebe3
--- /dev/null
+++ b/test
@@ -0,0 +1,33135 @@
+#! /usr/bin/vvp
+:ivl_version "0.9.7 " "(v0_9_7)";
+:vpi_time_precision - 12;
+:vpi_module "system";
+:vpi_module "v2005_math";
+:vpi_module "va_math";
+S_0x22efd20 .scope module, "test32Adder" "test32Adder" 2 126;
+ .timescale -9 -12;
+P_0x1d31a18 .param/l "size" 2 127, +C4<0100000>;
+v0x295fe90_0 .var "A", 31 0;
+RS_0x7f507e9ad5c8/0/0 .resolv tri, L_0x29618c0, L_0x2962e40, L_0x2964550, L_0x2965bd0;
+RS_0x7f507e9ad5c8/0/4 .resolv tri, L_0x2967170, L_0x2968720, L_0x2969c40, L_0x296b160;
+RS_0x7f507e9ad5c8/0/8 .resolv tri, L_0x296c770, L_0x296dc80, L_0x296f190, L_0x2970790;
+RS_0x7f507e9ad5c8/0/12 .resolv tri, L_0x2971c50, L_0x2973130, L_0x29745a0, L_0x2975a20;
+RS_0x7f507e9ad5c8/0/16 .resolv tri, L_0x29770e0, L_0x2978550, L_0x2979e50, L_0x297b220;
+RS_0x7f507e9ad5c8/0/20 .resolv tri, L_0x297c6a0, L_0x297dbb0, L_0x297ef70, L_0x2980450;
+RS_0x7f507e9ad5c8/0/24 .resolv tri, L_0x2981940, L_0x2982e20, L_0x2984300, L_0x29859d0;
+RS_0x7f507e9ad5c8/0/28 .resolv tri, L_0x2986ec0, L_0x29885c0, L_0x2989ab0, L_0x298afa0;
+RS_0x7f507e9ad5c8/0/32 .resolv tri, L_0x2aa88d0, L_0x2aa9e10, L_0x2aab350, L_0x2aac950;
+RS_0x7f507e9ad5c8/0/36 .resolv tri, L_0x2aadef0, L_0x2aaf420, L_0x2ab0940, L_0x2ab1e60;
+RS_0x7f507e9ad5c8/0/40 .resolv tri, L_0x2ab3470, L_0x2ab4980, L_0x2ab5e90, L_0x2ab73a0;
+RS_0x7f507e9ad5c8/0/44 .resolv tri, L_0x2ab88a0, L_0x2ab9db0, L_0x2abb2c0, L_0x2abc6f0;
+RS_0x7f507e9ad5c8/0/48 .resolv tri, L_0x2abddb0, L_0x2abf220, L_0x2ac06d0, L_0x2ac1aa0;
+RS_0x7f507e9ad5c8/0/52 .resolv tri, L_0x2ac2e60, L_0x2ac4370, L_0x2ac5730, L_0x2ac6b70;
+RS_0x7f507e9ad5c8/0/56 .resolv tri, L_0x2ac8830, L_0x2ac9d10, L_0x2997ec0, L_0x29993f0;
+RS_0x7f507e9ad5c8/0/60 .resolv tri, L_0x299a8d0, L_0x2ad3100, L_0x2ad4540, L_0x2ad6280;
+RS_0x7f507e9ad5c8/1/0 .resolv tri, RS_0x7f507e9ad5c8/0/0, RS_0x7f507e9ad5c8/0/4, RS_0x7f507e9ad5c8/0/8, RS_0x7f507e9ad5c8/0/12;
+RS_0x7f507e9ad5c8/1/4 .resolv tri, RS_0x7f507e9ad5c8/0/16, RS_0x7f507e9ad5c8/0/20, RS_0x7f507e9ad5c8/0/24, RS_0x7f507e9ad5c8/0/28;
+RS_0x7f507e9ad5c8/1/8 .resolv tri, RS_0x7f507e9ad5c8/0/32, RS_0x7f507e9ad5c8/0/36, RS_0x7f507e9ad5c8/0/40, RS_0x7f507e9ad5c8/0/44;
+RS_0x7f507e9ad5c8/1/12 .resolv tri, RS_0x7f507e9ad5c8/0/48, RS_0x7f507e9ad5c8/0/52, RS_0x7f507e9ad5c8/0/56, RS_0x7f507e9ad5c8/0/60;
+RS_0x7f507e9ad5c8 .resolv tri, RS_0x7f507e9ad5c8/1/0, RS_0x7f507e9ad5c8/1/4, RS_0x7f507e9ad5c8/1/8, RS_0x7f507e9ad5c8/1/12;
+v0x295ff30_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9ad5c8; 64 drivers
+v0x295ffb0_0 .net "AllZeros", 0 0, L_0x2a25810; 1 drivers
+v0x2960030_0 .net "AllZeros2", 0 0, L_0x2c148b0; 1 drivers
+RS_0x7f507e9a6998/0/0 .resolv tri, L_0x29d55b0, L_0x29d72e0, L_0x29d7d50, L_0x29d87b0;
+RS_0x7f507e9a6998/0/4 .resolv tri, L_0x29d9220, L_0x29d9d80, L_0x29da7f0, L_0x29db250;
+RS_0x7f507e9a6998/0/8 .resolv tri, L_0x29dbcd0, L_0x29dc740, L_0x29dd1b0, L_0x29ddc20;
+RS_0x7f507e9a6998/0/12 .resolv tri, L_0x29de6a0, L_0x29df210, L_0x29dfc80, L_0x29e06f0;
+RS_0x7f507e9a6998/0/16 .resolv tri, L_0x29e1170, L_0x29e1bd0, L_0x29e2650, L_0x29e30b0;
+RS_0x7f507e9a6998/0/20 .resolv tri, L_0x29e3b20, L_0x29e4590, L_0x29e5010, L_0x29e5a70;
+RS_0x7f507e9a6998/0/24 .resolv tri, L_0x29e64e0, L_0x29e6f40, L_0x29e79b0, L_0x29e8420;
+RS_0x7f507e9a6998/0/28 .resolv tri, L_0x29e8ea0, L_0x29e9a60, L_0x29ea410, L_0x29eadc0;
+RS_0x7f507e9a6998/0/32 .resolv tri, L_0x2ad6970, L_0x2ad8130, L_0x2ad8ba0, L_0x2ad9600;
+RS_0x7f507e9a6998/0/36 .resolv tri, L_0x2ada070, L_0x2adab40, L_0x2adb640, L_0x2adc0a0;
+RS_0x7f507e9a6998/0/40 .resolv tri, L_0x2adcb20, L_0x2add3f0, L_0x2addda0, L_0x2ade750;
+RS_0x7f507e9a6998/0/44 .resolv tri, L_0x2adf1d0, L_0x2adfc30, L_0x2ae06a0, L_0x2ae1110;
+RS_0x7f507e9a6998/0/48 .resolv tri, L_0x2ae1b90, L_0x2ae25f0, L_0x2ae3070, L_0x2ae3ad0;
+RS_0x7f507e9a6998/0/52 .resolv tri, L_0x2ae4540, L_0x2ae4fb0, L_0x2ae5a30, L_0x2ae6490;
+RS_0x7f507e9a6998/0/56 .resolv tri, L_0x2ae6f00, L_0x2ae7960, L_0x2ae83d0, L_0x2ae8e40;
+RS_0x7f507e9a6998/0/60 .resolv tri, L_0x2ae98c0, L_0x2aea320, L_0x2aead90, L_0x2aec010;
+RS_0x7f507e9a6998/1/0 .resolv tri, RS_0x7f507e9a6998/0/0, RS_0x7f507e9a6998/0/4, RS_0x7f507e9a6998/0/8, RS_0x7f507e9a6998/0/12;
+RS_0x7f507e9a6998/1/4 .resolv tri, RS_0x7f507e9a6998/0/16, RS_0x7f507e9a6998/0/20, RS_0x7f507e9a6998/0/24, RS_0x7f507e9a6998/0/28;
+RS_0x7f507e9a6998/1/8 .resolv tri, RS_0x7f507e9a6998/0/32, RS_0x7f507e9a6998/0/36, RS_0x7f507e9a6998/0/40, RS_0x7f507e9a6998/0/44;
+RS_0x7f507e9a6998/1/12 .resolv tri, RS_0x7f507e9a6998/0/48, RS_0x7f507e9a6998/0/52, RS_0x7f507e9a6998/0/56, RS_0x7f507e9a6998/0/60;
+RS_0x7f507e9a6998 .resolv tri, RS_0x7f507e9a6998/1/0, RS_0x7f507e9a6998/1/4, RS_0x7f507e9a6998/1/8, RS_0x7f507e9a6998/1/12;
+v0x2960110_0 .net8 "AndNandOut", 31 0, RS_0x7f507e9a6998; 64 drivers
+v0x2960190_0 .var "B", 31 0;
+v0x2960210_0 .var "Command", 2 0;
+RS_0x7f507e9b8fc8/0/0 .resolv tri, L_0x2a13d10, L_0x2a16700, L_0x2a19020, L_0x2a1b8b0;
+RS_0x7f507e9b8fc8/0/4 .resolv tri, L_0x2a1e380, L_0x2a20c00, L_0x2a22df0, L_0x2a25b80;
+RS_0x7f507e9b8fc8/0/8 .resolv tri, L_0x2a287f0, L_0x2a0e150, L_0x2a2dbd0, L_0x2a30380;
+RS_0x7f507e9b8fc8/0/12 .resolv tri, L_0x2a32b70, L_0x2a353a0, L_0x2a369f0, L_0x2a39c30;
+RS_0x7f507e9b8fc8/0/16 .resolv tri, L_0x2a3cf20, L_0x2a3f4f0, L_0x2a42060, L_0x2a44820;
+RS_0x7f507e9b8fc8/0/20 .resolv tri, L_0x2a46db0, L_0x2a49350, L_0x2a4b310, L_0x2a4d770;
+RS_0x7f507e9b8fc8/0/24 .resolv tri, L_0x2a505f0, L_0x2a52c10, L_0x2a55190, L_0x2a577a0;
+RS_0x7f507e9b8fc8/0/28 .resolv tri, L_0x2a5a170, L_0x2a5db60, L_0x2a2b1f0, L_0x2b15ad0;
+RS_0x7f507e9b8fc8/1/0 .resolv tri, RS_0x7f507e9b8fc8/0/0, RS_0x7f507e9b8fc8/0/4, RS_0x7f507e9b8fc8/0/8, RS_0x7f507e9b8fc8/0/12;
+RS_0x7f507e9b8fc8/1/4 .resolv tri, RS_0x7f507e9b8fc8/0/16, RS_0x7f507e9b8fc8/0/20, RS_0x7f507e9b8fc8/0/24, RS_0x7f507e9b8fc8/0/28;
+RS_0x7f507e9b8fc8 .resolv tri, RS_0x7f507e9b8fc8/1/0, RS_0x7f507e9b8fc8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2960290_0 .net8 "OneBitFinalOut", 31 0, RS_0x7f507e9b8fc8; 32 drivers
+RS_0x7f507e9f0b38/0/0 .resolv tri, L_0x2b196d0, L_0x2b1c090, L_0x2b1ea60, L_0x2b21190;
+RS_0x7f507e9f0b38/0/4 .resolv tri, L_0x2b237b0, L_0x2b264d0, L_0x2b284c0, L_0x2b2b410;
+RS_0x7f507e9f0b38/0/8 .resolv tri, L_0x2b2dee0, L_0x2b305e0, L_0x2b326c0, L_0x2b35640;
+RS_0x7f507e9f0b38/0/12 .resolv tri, L_0x2b37e90, L_0x2b3a6b0, L_0x2b3cf60, L_0x2b3fb50;
+RS_0x7f507e9f0b38/0/16 .resolv tri, L_0x2b41820, L_0x2b44360, L_0x2b46d90, L_0x2b49550;
+RS_0x7f507e9f0b38/0/20 .resolv tri, L_0x2b4b730, L_0x2b4e660, L_0x2b506d0, L_0x2b54750;
+RS_0x7f507e9f0b38/0/24 .resolv tri, L_0x2b55e40, L_0x2b58640, L_0x2b5ad30, L_0x2b5d580;
+RS_0x7f507e9f0b38/0/28 .resolv tri, L_0x2b5fdd0, L_0x2b63a50, L_0x2b64480, L_0x2b4c8d0;
+RS_0x7f507e9f0b38/1/0 .resolv tri, RS_0x7f507e9f0b38/0/0, RS_0x7f507e9f0b38/0/4, RS_0x7f507e9f0b38/0/8, RS_0x7f507e9f0b38/0/12;
+RS_0x7f507e9f0b38/1/4 .resolv tri, RS_0x7f507e9f0b38/0/16, RS_0x7f507e9f0b38/0/20, RS_0x7f507e9f0b38/0/24, RS_0x7f507e9f0b38/0/28;
+RS_0x7f507e9f0b38 .resolv tri, RS_0x7f507e9f0b38/1/0, RS_0x7f507e9f0b38/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2960310_0 .net8 "OneBitFinalOut2", 31 0, RS_0x7f507e9f0b38; 32 drivers
+RS_0x7f507e9a3368/0/0 .resolv tri, L_0x29ebfa0, L_0x29ed0e0, L_0x29ee260, L_0x29ef550;
+RS_0x7f507e9a3368/0/4 .resolv tri, L_0x29f0850, L_0x29f1c40, L_0x29f2f40, L_0x29f4230;
+RS_0x7f507e9a3368/0/8 .resolv tri, L_0x29f5540, L_0x29f6720, L_0x29f78e0, L_0x29f8bd0;
+RS_0x7f507e9a3368/0/12 .resolv tri, L_0x29f9ef0, L_0x29fb300, L_0x29fc600, L_0x29fd8f0;
+RS_0x7f507e9a3368/0/16 .resolv tri, L_0x29fec00, L_0x29ffef0, L_0x2a02200, L_0x2a033c0;
+RS_0x7f507e9a3368/0/20 .resolv tri, L_0x2a046d0, L_0x2a059c0, L_0x2a06cc0, L_0x2a07f80;
+RS_0x7f507e9a3368/0/24 .resolv tri, L_0x2a09280, L_0x2a0a570, L_0x2a0b880, L_0x2a0cb80;
+RS_0x7f507e9a3368/0/28 .resolv tri, L_0x2a0de80, L_0x2a0f240, L_0x2a10550, L_0x2a11840;
+RS_0x7f507e9a3368/0/32 .resolv tri, L_0x2aed1f0, L_0x2aee2f0, L_0x2aef450, L_0x2af0740;
+RS_0x7f507e9a3368/0/36 .resolv tri, L_0x2af1a40, L_0x2af2da0, L_0x2af4130, L_0x2af5420;
+RS_0x7f507e9a3368/0/40 .resolv tri, L_0x2af6730, L_0x2af7a30, L_0x2af8d30, L_0x2afa020;
+RS_0x7f507e9a3368/0/44 .resolv tri, L_0x2afb340, L_0x2afc640, L_0x2afd940, L_0x2afea20;
+RS_0x7f507e9a3368/0/48 .resolv tri, L_0x2affc30, L_0x2b00f20, L_0x2a011b0, L_0x2b054d0;
+RS_0x7f507e9a3368/0/52 .resolv tri, L_0x2b067e0, L_0x2b07ad0, L_0x2b08dd0, L_0x2b0a0d0;
+RS_0x7f507e9a3368/0/56 .resolv tri, L_0x2b0b3d0, L_0x2b0c6c0, L_0x2b0d9f0, L_0x2b0ecf0;
+RS_0x7f507e9a3368/0/60 .resolv tri, L_0x2b0fff0, L_0x2b112e0, L_0x2b125f0, L_0x2b13900;
+RS_0x7f507e9a3368/1/0 .resolv tri, RS_0x7f507e9a3368/0/0, RS_0x7f507e9a3368/0/4, RS_0x7f507e9a3368/0/8, RS_0x7f507e9a3368/0/12;
+RS_0x7f507e9a3368/1/4 .resolv tri, RS_0x7f507e9a3368/0/16, RS_0x7f507e9a3368/0/20, RS_0x7f507e9a3368/0/24, RS_0x7f507e9a3368/0/28;
+RS_0x7f507e9a3368/1/8 .resolv tri, RS_0x7f507e9a3368/0/32, RS_0x7f507e9a3368/0/36, RS_0x7f507e9a3368/0/40, RS_0x7f507e9a3368/0/44;
+RS_0x7f507e9a3368/1/12 .resolv tri, RS_0x7f507e9a3368/0/48, RS_0x7f507e9a3368/0/52, RS_0x7f507e9a3368/0/56, RS_0x7f507e9a3368/0/60;
+RS_0x7f507e9a3368 .resolv tri, RS_0x7f507e9a3368/1/0, RS_0x7f507e9a3368/1/4, RS_0x7f507e9a3368/1/8, RS_0x7f507e9a3368/1/12;
+v0x29603c0_0 .net8 "OrNorXorOut", 31 0, RS_0x7f507e9a3368; 64 drivers
+RS_0x7f507e9b8c98/0/0 .resolv tri, L_0x298e080, L_0x2990460, L_0x2992620, L_0x29948c0;
+RS_0x7f507e9b8c98/0/4 .resolv tri, L_0x2996b20, L_0x2892a70, L_0x299d060, L_0x299f440;
+RS_0x7f507e9b8c98/0/8 .resolv tri, L_0x29a1630, L_0x29a3800, L_0x29a59e0, L_0x29a7da0;
+RS_0x7f507e9b8c98/0/12 .resolv tri, L_0x29aa050, L_0x29ac2e0, L_0x29ae5d0, L_0x29b0af0;
+RS_0x7f507e9b8c98/0/16 .resolv tri, L_0x29b1f90, L_0x29b48c0, L_0x298d620, L_0x29b99d0;
+RS_0x7f507e9b8c98/0/20 .resolv tri, L_0x29bbc70, L_0x29bd990, L_0x29c0440, L_0x29c2500;
+RS_0x7f507e9b8c98/0/24 .resolv tri, L_0x29c4810, L_0x29c6500, L_0x29c97d0, L_0x29cb9b0;
+RS_0x7f507e9b8c98/0/28 .resolv tri, L_0x29cdba0, L_0x29cff90, L_0x29d2180, L_0x29d5e90;
+RS_0x7f507e9b8c98/0/32 .resolv tri, L_0x2a632c0, L_0x2a65500, L_0x2a67580, L_0x2a697f0;
+RS_0x7f507e9b8c98/0/36 .resolv tri, L_0x2a6b8c0, L_0x2a6daa0, L_0x2a6fbd0, L_0x2a71ef0;
+RS_0x7f507e9b8c98/0/40 .resolv tri, L_0x2a740e0, L_0x2a76340, L_0x2a784f0, L_0x2a7a7e0;
+RS_0x7f507e9b8c98/0/44 .resolv tri, L_0x2a7c900, L_0x2a7ea90, L_0x2a80cf0, L_0x2a83250;
+RS_0x7f507e9b8c98/0/48 .resolv tri, L_0x2a846f0, L_0x2a87ed0, L_0x2a89760, L_0x2a871e0;
+RS_0x7f507e9b8c98/0/52 .resolv tri, L_0x2a8db40, L_0x2a8f910, L_0x2a922f0, L_0x2a94650;
+RS_0x7f507e9b8c98/0/56 .resolv tri, L_0x2a966a0, L_0x2a99180, L_0x2a9b350, L_0x2a9d570;
+RS_0x7f507e9b8c98/0/60 .resolv tri, L_0x2a9f720, L_0x2aa1920, L_0x2aa3ad0, L_0x2aa7720;
+RS_0x7f507e9b8c98/1/0 .resolv tri, RS_0x7f507e9b8c98/0/0, RS_0x7f507e9b8c98/0/4, RS_0x7f507e9b8c98/0/8, RS_0x7f507e9b8c98/0/12;
+RS_0x7f507e9b8c98/1/4 .resolv tri, RS_0x7f507e9b8c98/0/16, RS_0x7f507e9b8c98/0/20, RS_0x7f507e9b8c98/0/24, RS_0x7f507e9b8c98/0/28;
+RS_0x7f507e9b8c98/1/8 .resolv tri, RS_0x7f507e9b8c98/0/32, RS_0x7f507e9b8c98/0/36, RS_0x7f507e9b8c98/0/40, RS_0x7f507e9b8c98/0/44;
+RS_0x7f507e9b8c98/1/12 .resolv tri, RS_0x7f507e9b8c98/0/48, RS_0x7f507e9b8c98/0/52, RS_0x7f507e9b8c98/0/56, RS_0x7f507e9b8c98/0/60;
+RS_0x7f507e9b8c98 .resolv tri, RS_0x7f507e9b8c98/1/0, RS_0x7f507e9b8c98/1/4, RS_0x7f507e9b8c98/1/8, RS_0x7f507e9b8c98/1/12;
+v0x2960440_0 .net8 "SLTSum", 31 0, RS_0x7f507e9b8c98; 64 drivers
+v0x29604c0_0 .net "SLTflag", 0 0, L_0x2a828d0; 1 drivers
+v0x2960640_0 .net "SLTflag1", 0 0, L_0x29d5990; 1 drivers
+RS_0x7f507e9b8ff8/0/0 .resolv tri, L_0x2a14250, L_0x2a16bd0, L_0x2a19160, L_0x2a1bb70;
+RS_0x7f507e9b8ff8/0/4 .resolv tri, L_0x2a1df80, L_0x2a205c0, L_0x2a23200, L_0x2a1ba40;
+RS_0x7f507e9b8ff8/0/8 .resolv tri, L_0x2a28000, L_0x2a2a8d0, L_0x2a2d3e0, L_0x2a2fd70;
+RS_0x7f507e9b8ff8/0/12 .resolv tri, L_0x2a32370, L_0x2a34d20, L_0x2a36d10, L_0x2a3abb0;
+RS_0x7f507e9b8ff8/0/16 .resolv tri, L_0x2a3d4f0, L_0x2a40880, L_0x2a423d0, L_0x2a44b40;
+RS_0x7f507e9b8ff8/0/20 .resolv tri, L_0x2a470d0, L_0x2a49670, L_0x2a4b630, L_0x2a4da90;
+RS_0x7f507e9b8ff8/0/24 .resolv tri, L_0x2a50910, L_0x2a52f30, L_0x2a554b0, L_0x2a57ac0;
+RS_0x7f507e9b8ff8/0/28 .resolv tri, L_0x2a5a490, L_0x2a5c650, L_0x2a2b510, L_0x2a3b060;
+RS_0x7f507e9b8ff8/1/0 .resolv tri, RS_0x7f507e9b8ff8/0/0, RS_0x7f507e9b8ff8/0/4, RS_0x7f507e9b8ff8/0/8, RS_0x7f507e9b8ff8/0/12;
+RS_0x7f507e9b8ff8/1/4 .resolv tri, RS_0x7f507e9b8ff8/0/16, RS_0x7f507e9b8ff8/0/20, RS_0x7f507e9b8ff8/0/24, RS_0x7f507e9b8ff8/0/28;
+RS_0x7f507e9b8ff8 .resolv tri, RS_0x7f507e9b8ff8/1/0, RS_0x7f507e9b8ff8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x29606c0_0 .net8 "ZeroFlag", 31 0, RS_0x7f507e9b8ff8; 32 drivers
+v0x29607f0_0 .var "carryin", 31 0;
+RS_0x7f507e9ad6e8 .resolv tri, L_0x2989ff0, L_0x29d2c20, L_0x2a82310, L_0x2ad5950;
+v0x2960870_0 .net8 "carryout", 0 0, RS_0x7f507e9ad6e8; 4 drivers
+RS_0x7f507e9e4bc8 .resolv tri, L_0x2b886f0, L_0x2bd6820, C4<z>, C4<z>;
+v0x2960740_0 .net8 "carryout2", 0 0, RS_0x7f507e9e4bc8; 2 drivers
+RS_0x7f507e9ad718 .resolv tri, L_0x298a1c0, L_0x29d4420, L_0x2aa45c0, L_0x2abcea0;
+v0x2960980_0 .net8 "overflow", 0 0, RS_0x7f507e9ad718; 4 drivers
+RS_0x7f507e9e4bf8 .resolv tri, L_0x2bab990, L_0x2bc33a0, C4<z>, C4<z>;
+v0x29608f0_0 .net8 "overflow2", 0 0, RS_0x7f507e9e4bf8; 2 drivers
+RS_0x7f507e9ad748/0/0 .resolv tri, L_0x2961b00, L_0x2963070, L_0x29647b0, L_0x2964c60;
+RS_0x7f507e9ad748/0/4 .resolv tri, L_0x2966250, L_0x2967800, L_0x2968d00, L_0x296a1f0;
+RS_0x7f507e9ad748/0/8 .resolv tri, L_0x296b980, L_0x296ccd0, L_0x296e210, L_0x296f780;
+RS_0x7f507e9ad748/0/12 .resolv tri, L_0x2970cf0, L_0x29722f0, L_0x29736e0, L_0x2974b80;
+RS_0x7f507e9ad748/0/16 .resolv tri, L_0x29763b0, L_0x2977690, L_0x2979600, L_0x297a030;
+RS_0x7f507e9ad748/0/20 .resolv tri, L_0x297b400, L_0x297c880, L_0x297dd90, L_0x297f150;
+RS_0x7f507e9ad748/0/24 .resolv tri, L_0x2980630, L_0x2981b20, L_0x2983000, L_0x2984b20;
+RS_0x7f507e9ad748/0/28 .resolv tri, L_0x2971e30, L_0x2987370, L_0x29887a0, L_0x2989c90;
+RS_0x7f507e9ad748/0/32 .resolv tri, L_0x298cf00, L_0x298f5d0, L_0x29906f0, L_0x2993a80;
+RS_0x7f507e9ad748/0/36 .resolv tri, L_0x2994b60, L_0x2996e60, L_0x2892b10, L_0x299d2e0;
+RS_0x7f507e9ad748/0/40 .resolv tri, L_0x299f4e0, L_0x29a18b0, L_0x29a38a0, L_0x29a6070;
+RS_0x7f507e9ad748/0/44 .resolv tri, L_0x29a7e40, L_0x29aa3f0, L_0x29ac380, L_0x29ae850;
+RS_0x7f507e9ad748/0/48 .resolv tri, L_0x29b0b90, L_0x29b3650, L_0x29b5e90, L_0x29b7d30;
+RS_0x7f507e9ad748/0/52 .resolv tri, L_0x29ba550, L_0x29bc0c0, L_0x29be8d0, L_0x29c0890;
+RS_0x7f507e9ad748/0/56 .resolv tri, L_0x29c28f0, L_0x29c4c80, L_0x29c7440, L_0x29c9a50;
+RS_0x7f507e9ad748/0/60 .resolv tri, L_0x29cba50, L_0x29ce140, L_0x29d0030, L_0x29d2310;
+RS_0x7f507e9ad748/0/64 .resolv tri, L_0x2a5fce0, L_0x2a646d0, L_0x2a65790, L_0x2a689c0;
+RS_0x7f507e9ad748/0/68 .resolv tri, L_0x2a69a90, L_0x2a6bb40, L_0x2a6db40, L_0x2a6fe50;
+RS_0x7f507e9ad748/0/72 .resolv tri, L_0x2a71f90, L_0x2a74360, L_0x2a763e0, L_0x2a78b80;
+RS_0x7f507e9ad748/0/76 .resolv tri, L_0x2a7a880, L_0x2a7cb80, L_0x2a7eb30, L_0x2a80f20;
+RS_0x7f507e9ad748/0/80 .resolv tri, L_0x2a832f0, L_0x2a85db0, L_0x2a87f70, L_0x2a89ca0;
+RS_0x7f507e9ad748/0/84 .resolv tri, L_0x2a8c500, L_0x2a8e050, L_0x2a90850, L_0x2a92810;
+RS_0x7f507e9ad748/0/88 .resolv tri, L_0x2a94860, L_0x2a96bf0, L_0x2a99220, L_0x2a9b5d0;
+RS_0x7f507e9ad748/0/92 .resolv tri, L_0x2a9d610, L_0x2a9f9a0, L_0x2aa19c0, L_0x2aa3c60;
+RS_0x7f507e9ad748/0/96 .resolv tri, L_0x2aa8ad0, L_0x2aaa040, L_0x2aab5b0, L_0x2aab9a0;
+RS_0x7f507e9ad748/0/100 .resolv tri, L_0x2aacfd0, L_0x2aae4c0, L_0x2aafa00, L_0x2ab0ef0;
+RS_0x7f507e9ad748/0/104 .resolv tri, L_0x2ab2680, L_0x2ab39d0, L_0x2ab4f10, L_0x2ab6450;
+RS_0x7f507e9ad748/0/108 .resolv tri, L_0x2ab7900, L_0x2ab8e20, L_0x2aba360, L_0x2abb8a0;
+RS_0x7f507e9ad748/0/112 .resolv tri, L_0x2abd080, L_0x2abe360, L_0x2abf800, L_0x2ac08b0;
+RS_0x7f507e9ad748/0/116 .resolv tri, L_0x2ac1c80, L_0x2ac3040, L_0x2ac4550, L_0x2ac5910;
+RS_0x7f507e9ad748/0/120 .resolv tri, L_0x29c6c30, L_0x2ac8a10, L_0x2ac9ef0, L_0x29980a0;
+RS_0x7f507e9ad748/0/124 .resolv tri, L_0x29995d0, L_0x299aab0, L_0x2a374c0, L_0x2ad55f0;
+RS_0x7f507e9ad748/1/0 .resolv tri, RS_0x7f507e9ad748/0/0, RS_0x7f507e9ad748/0/4, RS_0x7f507e9ad748/0/8, RS_0x7f507e9ad748/0/12;
+RS_0x7f507e9ad748/1/4 .resolv tri, RS_0x7f507e9ad748/0/16, RS_0x7f507e9ad748/0/20, RS_0x7f507e9ad748/0/24, RS_0x7f507e9ad748/0/28;
+RS_0x7f507e9ad748/1/8 .resolv tri, RS_0x7f507e9ad748/0/32, RS_0x7f507e9ad748/0/36, RS_0x7f507e9ad748/0/40, RS_0x7f507e9ad748/0/44;
+RS_0x7f507e9ad748/1/12 .resolv tri, RS_0x7f507e9ad748/0/48, RS_0x7f507e9ad748/0/52, RS_0x7f507e9ad748/0/56, RS_0x7f507e9ad748/0/60;
+RS_0x7f507e9ad748/1/16 .resolv tri, RS_0x7f507e9ad748/0/64, RS_0x7f507e9ad748/0/68, RS_0x7f507e9ad748/0/72, RS_0x7f507e9ad748/0/76;
+RS_0x7f507e9ad748/1/20 .resolv tri, RS_0x7f507e9ad748/0/80, RS_0x7f507e9ad748/0/84, RS_0x7f507e9ad748/0/88, RS_0x7f507e9ad748/0/92;
+RS_0x7f507e9ad748/1/24 .resolv tri, RS_0x7f507e9ad748/0/96, RS_0x7f507e9ad748/0/100, RS_0x7f507e9ad748/0/104, RS_0x7f507e9ad748/0/108;
+RS_0x7f507e9ad748/1/28 .resolv tri, RS_0x7f507e9ad748/0/112, RS_0x7f507e9ad748/0/116, RS_0x7f507e9ad748/0/120, RS_0x7f507e9ad748/0/124;
+RS_0x7f507e9ad748/2/0 .resolv tri, RS_0x7f507e9ad748/1/0, RS_0x7f507e9ad748/1/4, RS_0x7f507e9ad748/1/8, RS_0x7f507e9ad748/1/12;
+RS_0x7f507e9ad748/2/4 .resolv tri, RS_0x7f507e9ad748/1/16, RS_0x7f507e9ad748/1/20, RS_0x7f507e9ad748/1/24, RS_0x7f507e9ad748/1/28;
+RS_0x7f507e9ad748 .resolv tri, RS_0x7f507e9ad748/2/0, RS_0x7f507e9ad748/2/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2960aa0_0 .net8 "subtract", 31 0, RS_0x7f507e9ad748; 128 drivers
+S_0x293c2e0 .scope module, "trial" "AddSubSLT32" 2 154, 3 267, S_0x22efd20;
+ .timescale -9 -12;
+P_0x293a9d8 .param/l "size" 3 281, +C4<0100000>;
+L_0x2989ff0/d .functor OR 1, L_0x298a070, C4<0>, C4<0>, C4<0>;
+L_0x2989ff0 .delay (20000,20000,20000) L_0x2989ff0/d;
+L_0x298a1c0/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x2976030, C4<0>, C4<0>;
+L_0x298a1c0 .delay (40000,40000,40000) L_0x298a1c0/d;
+v0x295f580_0 .net "A", 31 0, v0x295fe90_0; 1 drivers
+v0x295f620_0 .alias "AddSubSLTSum", 31 0, v0x295ff30_0;
+v0x295f6a0_0 .net "B", 31 0, v0x2960190_0; 1 drivers
+RS_0x7f507e974678/0/0 .resolv tri, L_0x2961a10, L_0x2962f30, L_0x2964640, L_0x2965cc0;
+RS_0x7f507e974678/0/4 .resolv tri, L_0x2967320, L_0x2968810, L_0x2969d30, L_0x296b250;
+RS_0x7f507e974678/0/8 .resolv tri, L_0x296c860, L_0x296dd70, L_0x296f280, L_0x2970880;
+RS_0x7f507e974678/0/12 .resolv tri, L_0x2967260, L_0x2973220, L_0x2974690, L_0x2975b10;
+RS_0x7f507e974678/0/16 .resolv tri, L_0x29771d0, L_0x2978640, L_0x2979f40, L_0x297b310;
+RS_0x7f507e974678/0/20 .resolv tri, L_0x297c790, L_0x297dca0, L_0x297f060, L_0x2980540;
+RS_0x7f507e974678/0/24 .resolv tri, L_0x2981a30, L_0x2982f10, L_0x29843f0, L_0x2985ac0;
+RS_0x7f507e974678/0/28 .resolv tri, L_0x2971d40, L_0x29886b0, L_0x2989ba0, L_0x298b090;
+RS_0x7f507e974678/1/0 .resolv tri, RS_0x7f507e974678/0/0, RS_0x7f507e974678/0/4, RS_0x7f507e974678/0/8, RS_0x7f507e974678/0/12;
+RS_0x7f507e974678/1/4 .resolv tri, RS_0x7f507e974678/0/16, RS_0x7f507e974678/0/20, RS_0x7f507e974678/0/24, RS_0x7f507e974678/0/28;
+RS_0x7f507e974678 .resolv tri, RS_0x7f507e974678/1/0, RS_0x7f507e974678/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x295f720_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e974678; 32 drivers
+v0x295f7a0_0 .net "Command", 2 0, v0x2960210_0; 1 drivers
+v0x295f820_0 .net *"_s292", 0 0, L_0x298a070; 1 drivers
+v0x295f8c0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers
+v0x295f960_0 .net *"_s296", 0 0, L_0x2976030; 1 drivers
+v0x295fa50_0 .net "carryin", 31 0, v0x29607f0_0; 1 drivers
+v0x295fb60_0 .alias "carryout", 0 0, v0x2960870_0;
+v0x295fc70_0 .alias "overflow", 0 0, v0x2960980_0;
+v0x295fd80_0 .alias "subtract", 31 0, v0x2960aa0_0;
+L_0x29618c0 .part/pv L_0x29613b0, 1, 1, 32;
+L_0x2961a10 .part/pv L_0x2961760, 1, 1, 32;
+L_0x2961b00 .part/pv L_0x29610b0, 1, 1, 32;
+L_0x2961bf0 .part v0x295fe90_0, 1, 1;
+L_0x2961c90 .part v0x2960190_0, 1, 1;
+L_0x2961dc0 .part RS_0x7f507e974678, 0, 1;
+L_0x2962e40 .part/pv L_0x2962990, 2, 1, 32;
+L_0x2962f30 .part/pv L_0x2962ce0, 2, 1, 32;
+L_0x2963070 .part/pv L_0x29626c0, 2, 1, 32;
+L_0x2963160 .part v0x295fe90_0, 2, 1;
+L_0x289f010 .part v0x2960190_0, 2, 1;
+L_0x289f160 .part RS_0x7f507e974678, 1, 1;
+L_0x2964550 .part/pv L_0x2964080, 3, 1, 32;
+L_0x2964640 .part/pv L_0x29643f0, 3, 1, 32;
+L_0x29647b0 .part/pv L_0x2963db0, 3, 1, 32;
+L_0x2964960 .part v0x295fe90_0, 3, 1;
+L_0x2964a90 .part v0x2960190_0, 3, 1;
+L_0x2964bc0 .part RS_0x7f507e974678, 2, 1;
+L_0x2965bd0 .part/pv L_0x2965720, 4, 1, 32;
+L_0x2965cc0 .part/pv L_0x2965a70, 4, 1, 32;
+L_0x2964c60 .part/pv L_0x2965450, 4, 1, 32;
+L_0x2965eb0 .part v0x295fe90_0, 4, 1;
+L_0x2965db0 .part v0x2960190_0, 4, 1;
+L_0x29660a0 .part RS_0x7f507e974678, 3, 1;
+L_0x2967170 .part/pv L_0x2966cc0, 5, 1, 32;
+L_0x2967320 .part/pv L_0x2967010, 5, 1, 32;
+L_0x2966250 .part/pv L_0x29669f0, 5, 1, 32;
+L_0x2967540 .part v0x295fe90_0, 5, 1;
+L_0x2967410 .part v0x2960190_0, 5, 1;
+L_0x2967760 .part RS_0x7f507e974678, 4, 1;
+L_0x2968720 .part/pv L_0x2968250, 6, 1, 32;
+L_0x2968810 .part/pv L_0x29685c0, 6, 1, 32;
+L_0x2967800 .part/pv L_0x2967f80, 6, 1, 32;
+L_0x2968a10 .part v0x295fe90_0, 6, 1;
+L_0x2968900 .part v0x2960190_0, 6, 1;
+L_0x2968c60 .part RS_0x7f507e974678, 5, 1;
+L_0x2969c40 .part/pv L_0x2969790, 7, 1, 32;
+L_0x2969d30 .part/pv L_0x2969ae0, 7, 1, 32;
+L_0x2968d00 .part/pv L_0x29694c0, 7, 1, 32;
+L_0x2969f60 .part v0x295fe90_0, 7, 1;
+L_0x2969e20 .part v0x2960190_0, 7, 1;
+L_0x296a150 .part RS_0x7f507e974678, 6, 1;
+L_0x296b160 .part/pv L_0x296acb0, 8, 1, 32;
+L_0x296b250 .part/pv L_0x296b000, 8, 1, 32;
+L_0x296a1f0 .part/pv L_0x296a9e0, 8, 1, 32;
+L_0x296b4b0 .part v0x295fe90_0, 8, 1;
+L_0x296b340 .part v0x2960190_0, 8, 1;
+L_0x296b6d0 .part RS_0x7f507e974678, 7, 1;
+L_0x296c770 .part/pv L_0x296c2c0, 9, 1, 32;
+L_0x296c860 .part/pv L_0x296c610, 9, 1, 32;
+L_0x296b980 .part/pv L_0x296bff0, 9, 1, 32;
+L_0x296ba70 .part v0x295fe90_0, 9, 1;
+L_0x296cb00 .part v0x2960190_0, 9, 1;
+L_0x296cc30 .part RS_0x7f507e974678, 8, 1;
+L_0x296dc80 .part/pv L_0x296d7d0, 10, 1, 32;
+L_0x296dd70 .part/pv L_0x296db20, 10, 1, 32;
+L_0x296ccd0 .part/pv L_0x296d500, 10, 1, 32;
+L_0x296cdc0 .part v0x295fe90_0, 10, 1;
+L_0x296e040 .part v0x2960190_0, 10, 1;
+L_0x296e170 .part RS_0x7f507e974678, 9, 1;
+L_0x296f190 .part/pv L_0x296ece0, 11, 1, 32;
+L_0x296f280 .part/pv L_0x296f030, 11, 1, 32;
+L_0x296e210 .part/pv L_0x296ea10, 11, 1, 32;
+L_0x29648a0 .part v0x295fe90_0, 11, 1;
+L_0x296e2b0 .part v0x2960190_0, 11, 1;
+L_0x296f370 .part RS_0x7f507e974678, 10, 1;
+L_0x2970790 .part/pv L_0x29702e0, 12, 1, 32;
+L_0x2970880 .part/pv L_0x2970630, 12, 1, 32;
+L_0x296f780 .part/pv L_0x2970010, 12, 1, 32;
+L_0x296f870 .part v0x295fe90_0, 12, 1;
+L_0x2970bb0 .part v0x2960190_0, 12, 1;
+L_0x2970c50 .part RS_0x7f507e974678, 11, 1;
+L_0x2971c50 .part/pv L_0x29717a0, 13, 1, 32;
+L_0x2967260 .part/pv L_0x2971af0, 13, 1, 32;
+L_0x2970cf0 .part/pv L_0x29714d0, 13, 1, 32;
+L_0x2970de0 .part v0x295fe90_0, 13, 1;
+L_0x2970e80 .part v0x2960190_0, 13, 1;
+L_0x2972250 .part RS_0x7f507e974678, 12, 1;
+L_0x2973130 .part/pv L_0x2972ca0, 14, 1, 32;
+L_0x2973220 .part/pv L_0x2972ff0, 14, 1, 32;
+L_0x29722f0 .part/pv L_0x29729d0, 14, 1, 32;
+L_0x29723e0 .part v0x295fe90_0, 14, 1;
+L_0x2972480 .part v0x2960190_0, 14, 1;
+L_0x2973640 .part RS_0x7f507e974678, 13, 1;
+L_0x29745a0 .part/pv L_0x2974110, 15, 1, 32;
+L_0x2974690 .part/pv L_0x2974460, 15, 1, 32;
+L_0x29736e0 .part/pv L_0x2973e40, 15, 1, 32;
+L_0x29737d0 .part v0x295fe90_0, 15, 1;
+L_0x2973870 .part v0x2960190_0, 15, 1;
+L_0x2974ae0 .part RS_0x7f507e974678, 14, 1;
+L_0x2975a20 .part/pv L_0x2975590, 16, 1, 32;
+L_0x2975b10 .part/pv L_0x29758e0, 16, 1, 32;
+L_0x2974b80 .part/pv L_0x29752c0, 16, 1, 32;
+L_0x2974c70 .part v0x295fe90_0, 16, 1;
+L_0x2974d10 .part v0x2960190_0, 16, 1;
+L_0x2975f00 .part RS_0x7f507e974678, 15, 1;
+L_0x29770e0 .part/pv L_0x2976c50, 17, 1, 32;
+L_0x29771d0 .part/pv L_0x2976fa0, 17, 1, 32;
+L_0x29763b0 .part/pv L_0x2976980, 17, 1, 32;
+L_0x29764a0 .part v0x295fe90_0, 17, 1;
+L_0x2976540 .part v0x2960190_0, 17, 1;
+L_0x29775f0 .part RS_0x7f507e974678, 16, 1;
+L_0x2978550 .part/pv L_0x29780c0, 18, 1, 32;
+L_0x2978640 .part/pv L_0x2978410, 18, 1, 32;
+L_0x2977690 .part/pv L_0x2977df0, 18, 1, 32;
+L_0x2977780 .part v0x295fe90_0, 18, 1;
+L_0x2977820 .part v0x2960190_0, 18, 1;
+L_0x2963200 .part RS_0x7f507e974678, 17, 1;
+L_0x2979e50 .part/pv L_0x29799c0, 19, 1, 32;
+L_0x2979f40 .part/pv L_0x2979d10, 19, 1, 32;
+L_0x2979600 .part/pv L_0x2978f70, 19, 1, 32;
+L_0x29796f0 .part v0x295fe90_0, 19, 1;
+L_0x2979790 .part v0x2960190_0, 19, 1;
+L_0x29798c0 .part RS_0x7f507e974678, 18, 1;
+L_0x297b220 .part/pv L_0x297ad90, 20, 1, 32;
+L_0x297b310 .part/pv L_0x297b0e0, 20, 1, 32;
+L_0x297a030 .part/pv L_0x297aac0, 20, 1, 32;
+L_0x297a120 .part v0x295fe90_0, 20, 1;
+L_0x297a1c0 .part v0x2960190_0, 20, 1;
+L_0x297a2f0 .part RS_0x7f507e974678, 19, 1;
+L_0x297c6a0 .part/pv L_0x297c1d0, 21, 1, 32;
+L_0x297c790 .part/pv L_0x297c540, 21, 1, 32;
+L_0x297b400 .part/pv L_0x297bf00, 21, 1, 32;
+L_0x297b4f0 .part v0x295fe90_0, 21, 1;
+L_0x297b590 .part v0x2960190_0, 21, 1;
+L_0x297b6c0 .part RS_0x7f507e974678, 20, 1;
+L_0x297dbb0 .part/pv L_0x297d700, 22, 1, 32;
+L_0x297dca0 .part/pv L_0x297da50, 22, 1, 32;
+L_0x297c880 .part/pv L_0x297d430, 22, 1, 32;
+L_0x297c970 .part v0x295fe90_0, 22, 1;
+L_0x297ca10 .part v0x2960190_0, 22, 1;
+L_0x297cb40 .part RS_0x7f507e974678, 21, 1;
+L_0x297ef70 .part/pv L_0x297eae0, 23, 1, 32;
+L_0x297f060 .part/pv L_0x297ee30, 23, 1, 32;
+L_0x297dd90 .part/pv L_0x297e810, 23, 1, 32;
+L_0x297de80 .part v0x295fe90_0, 23, 1;
+L_0x297df20 .part v0x2960190_0, 23, 1;
+L_0x297e050 .part RS_0x7f507e974678, 22, 1;
+L_0x2980450 .part/pv L_0x297ff20, 24, 1, 32;
+L_0x2980540 .part/pv L_0x29802f0, 24, 1, 32;
+L_0x297f150 .part/pv L_0x297fc50, 24, 1, 32;
+L_0x297f240 .part v0x295fe90_0, 24, 1;
+L_0x297f2e0 .part v0x2960190_0, 24, 1;
+L_0x297f410 .part RS_0x7f507e974678, 23, 1;
+L_0x2981940 .part/pv L_0x2981410, 25, 1, 32;
+L_0x2981a30 .part/pv L_0x29817e0, 25, 1, 32;
+L_0x2980630 .part/pv L_0x2981140, 25, 1, 32;
+L_0x2980720 .part v0x295fe90_0, 25, 1;
+L_0x29807c0 .part v0x2960190_0, 25, 1;
+L_0x29808f0 .part RS_0x7f507e974678, 24, 1;
+L_0x2982e20 .part/pv L_0x29828f0, 26, 1, 32;
+L_0x2982f10 .part/pv L_0x2982cc0, 26, 1, 32;
+L_0x2981b20 .part/pv L_0x2982620, 26, 1, 32;
+L_0x2981c10 .part v0x295fe90_0, 26, 1;
+L_0x2981cb0 .part v0x2960190_0, 26, 1;
+L_0x2981de0 .part RS_0x7f507e974678, 25, 1;
+L_0x2984300 .part/pv L_0x2983dd0, 27, 1, 32;
+L_0x29843f0 .part/pv L_0x29841a0, 27, 1, 32;
+L_0x2983000 .part/pv L_0x2983b00, 27, 1, 32;
+L_0x296f5c0 .part v0x295fe90_0, 27, 1;
+L_0x296f660 .part v0x2960190_0, 27, 1;
+L_0x2984a80 .part RS_0x7f507e974678, 26, 1;
+L_0x29859d0 .part/pv L_0x2985540, 28, 1, 32;
+L_0x2985ac0 .part/pv L_0x2985890, 28, 1, 32;
+L_0x2984b20 .part/pv L_0x2985270, 28, 1, 32;
+L_0x2984c10 .part v0x295fe90_0, 28, 1;
+L_0x2984cb0 .part v0x2960190_0, 28, 1;
+L_0x2984de0 .part RS_0x7f507e974678, 27, 1;
+L_0x2986ec0 .part/pv L_0x29869b0, 29, 1, 32;
+L_0x2971d40 .part/pv L_0x2986d60, 29, 1, 32;
+L_0x2971e30 .part/pv L_0x29866b0, 29, 1, 32;
+L_0x2985c00 .part v0x295fe90_0, 29, 1;
+L_0x2985ca0 .part v0x2960190_0, 29, 1;
+L_0x2985dd0 .part RS_0x7f507e974678, 28, 1;
+L_0x29885c0 .part/pv L_0x29880b0, 30, 1, 32;
+L_0x29886b0 .part/pv L_0x2988460, 30, 1, 32;
+L_0x2987370 .part/pv L_0x2987de0, 30, 1, 32;
+L_0x2987460 .part v0x295fe90_0, 30, 1;
+L_0x2987500 .part v0x2960190_0, 30, 1;
+L_0x2987630 .part RS_0x7f507e974678, 29, 1;
+L_0x2989ab0 .part/pv L_0x29895a0, 31, 1, 32;
+L_0x2989ba0 .part/pv L_0x2989950, 31, 1, 32;
+L_0x29887a0 .part/pv L_0x29892a0, 31, 1, 32;
+L_0x2988890 .part v0x295fe90_0, 31, 1;
+L_0x2988930 .part v0x2960190_0, 31, 1;
+L_0x2988a60 .part RS_0x7f507e974678, 30, 1;
+L_0x298afa0 .part/pv L_0x298aa90, 0, 1, 32;
+L_0x298b090 .part/pv L_0x298ae40, 0, 1, 32;
+L_0x2989c90 .part/pv L_0x298a7c0, 0, 1, 32;
+L_0x2989d80 .part v0x295fe90_0, 0, 1;
+L_0x2989e20 .part v0x2960190_0, 0, 1;
+L_0x2989f50 .part RS_0x7f507e9ad748, 0, 1;
+L_0x298a070 .part RS_0x7f507e974678, 31, 1;
+L_0x2976030 .part RS_0x7f507e974678, 30, 1;
+S_0x295e570 .scope module, "attempt2" "MiddleAddSubSLT" 3 278, 3 189, S_0x293c2e0;
+ .timescale -9 -12;
+L_0x2988b00/d .functor NOT 1, L_0x2989e20, C4<0>, C4<0>, C4<0>;
+L_0x2988b00 .delay (10000,10000,10000) L_0x2988b00/d;
+L_0x298a680/d .functor NOT 1, L_0x298a720, C4<0>, C4<0>, C4<0>;
+L_0x298a680 .delay (10000,10000,10000) L_0x298a680/d;
+L_0x298a7c0/d .functor AND 1, L_0x298a900, L_0x298a680, C4<1>, C4<1>;
+L_0x298a7c0 .delay (20000,20000,20000) L_0x298a7c0/d;
+L_0x298a9a0/d .functor XOR 1, L_0x2989d80, L_0x298a450, C4<0>, C4<0>;
+L_0x298a9a0 .delay (40000,40000,40000) L_0x298a9a0/d;
+L_0x298aa90/d .functor XOR 1, L_0x298a9a0, L_0x2989f50, C4<0>, C4<0>;
+L_0x298aa90 .delay (40000,40000,40000) L_0x298aa90/d;
+L_0x298abb0/d .functor AND 1, L_0x2989d80, L_0x298a450, C4<1>, C4<1>;
+L_0x298abb0 .delay (20000,20000,20000) L_0x298abb0/d;
+L_0x298ad50/d .functor AND 1, L_0x298a9a0, L_0x2989f50, C4<1>, C4<1>;
+L_0x298ad50 .delay (20000,20000,20000) L_0x298ad50/d;
+L_0x298ae40/d .functor OR 1, L_0x298abb0, L_0x298ad50, C4<0>, C4<0>;
+L_0x298ae40 .delay (20000,20000,20000) L_0x298ae40/d;
+v0x295ebe0_0 .net "A", 0 0, L_0x2989d80; 1 drivers
+v0x295eca0_0 .net "AandB", 0 0, L_0x298abb0; 1 drivers
+v0x295ed40_0 .net "AddSubSLTSum", 0 0, L_0x298aa90; 1 drivers
+v0x295ede0_0 .net "AxorB", 0 0, L_0x298a9a0; 1 drivers
+v0x295ee60_0 .net "B", 0 0, L_0x2989e20; 1 drivers
+v0x295ef10_0 .net "BornB", 0 0, L_0x298a450; 1 drivers
+v0x295efd0_0 .net "CINandAxorB", 0 0, L_0x298ad50; 1 drivers
+v0x295f050_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x295f0d0_0 .net *"_s3", 0 0, L_0x298a720; 1 drivers
+v0x295f150_0 .net *"_s5", 0 0, L_0x298a900; 1 drivers
+v0x295f1f0_0 .net "carryin", 0 0, L_0x2989f50; 1 drivers
+v0x295f290_0 .net "carryout", 0 0, L_0x298ae40; 1 drivers
+v0x295f330_0 .net "nB", 0 0, L_0x2988b00; 1 drivers
+v0x295f3e0_0 .net "nCmd2", 0 0, L_0x298a680; 1 drivers
+v0x295f4e0_0 .net "subtract", 0 0, L_0x298a7c0; 1 drivers
+L_0x298a5e0 .part v0x2960210_0, 0, 1;
+L_0x298a720 .part v0x2960210_0, 2, 1;
+L_0x298a900 .part v0x2960210_0, 0, 1;
+S_0x295e660 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295e570;
+ .timescale -9 -12;
+L_0x2988c60/d .functor NOT 1, L_0x298a5e0, C4<0>, C4<0>, C4<0>;
+L_0x2988c60 .delay (10000,10000,10000) L_0x2988c60/d;
+L_0x298a270/d .functor AND 1, L_0x2989e20, L_0x2988c60, C4<1>, C4<1>;
+L_0x298a270 .delay (20000,20000,20000) L_0x298a270/d;
+L_0x298a360/d .functor AND 1, L_0x2988b00, L_0x298a5e0, C4<1>, C4<1>;
+L_0x298a360 .delay (20000,20000,20000) L_0x298a360/d;
+L_0x298a450/d .functor OR 1, L_0x298a270, L_0x298a360, C4<0>, C4<0>;
+L_0x298a450 .delay (20000,20000,20000) L_0x298a450/d;
+v0x295e750_0 .net "S", 0 0, L_0x298a5e0; 1 drivers
+v0x295e810_0 .alias "in0", 0 0, v0x295ee60_0;
+v0x295e8b0_0 .alias "in1", 0 0, v0x295f330_0;
+v0x295e950_0 .net "nS", 0 0, L_0x2988c60; 1 drivers
+v0x295ea00_0 .net "out0", 0 0, L_0x298a270; 1 drivers
+v0x295eaa0_0 .net "out1", 0 0, L_0x298a360; 1 drivers
+v0x295eb40_0 .alias "outfinal", 0 0, v0x295ef10_0;
+S_0x295d3d0 .scope generate, "addbits[1]" "addbits[1]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x295cde8 .param/l "i" 3 283, +C4<01>;
+S_0x295d540 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x295d3d0;
+ .timescale -9 -12;
+L_0x2951f80/d .functor NOT 1, L_0x2961c90, C4<0>, C4<0>, C4<0>;
+L_0x2951f80 .delay (10000,10000,10000) L_0x2951f80/d;
+L_0x2960f50/d .functor NOT 1, L_0x2961010, C4<0>, C4<0>, C4<0>;
+L_0x2960f50 .delay (10000,10000,10000) L_0x2960f50/d;
+L_0x29610b0/d .functor AND 1, L_0x29611f0, L_0x2960f50, C4<1>, C4<1>;
+L_0x29610b0 .delay (20000,20000,20000) L_0x29610b0/d;
+L_0x2961290/d .functor XOR 1, L_0x2961bf0, L_0x2960ce0, C4<0>, C4<0>;
+L_0x2961290 .delay (40000,40000,40000) L_0x2961290/d;
+L_0x29613b0/d .functor XOR 1, L_0x2961290, L_0x2961dc0, C4<0>, C4<0>;
+L_0x29613b0 .delay (40000,40000,40000) L_0x29613b0/d;
+L_0x29614d0/d .functor AND 1, L_0x2961bf0, L_0x2960ce0, C4<1>, C4<1>;
+L_0x29614d0 .delay (20000,20000,20000) L_0x29614d0/d;
+L_0x2961670/d .functor AND 1, L_0x2961290, L_0x2961dc0, C4<1>, C4<1>;
+L_0x2961670 .delay (20000,20000,20000) L_0x2961670/d;
+L_0x2961760/d .functor OR 1, L_0x29614d0, L_0x2961670, C4<0>, C4<0>;
+L_0x2961760 .delay (20000,20000,20000) L_0x2961760/d;
+v0x295dbd0_0 .net "A", 0 0, L_0x2961bf0; 1 drivers
+v0x295dc90_0 .net "AandB", 0 0, L_0x29614d0; 1 drivers
+v0x295dd30_0 .net "AddSubSLTSum", 0 0, L_0x29613b0; 1 drivers
+v0x295ddd0_0 .net "AxorB", 0 0, L_0x2961290; 1 drivers
+v0x295de50_0 .net "B", 0 0, L_0x2961c90; 1 drivers
+v0x295df00_0 .net "BornB", 0 0, L_0x2960ce0; 1 drivers
+v0x295dfc0_0 .net "CINandAxorB", 0 0, L_0x2961670; 1 drivers
+v0x295e040_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x295e0c0_0 .net *"_s3", 0 0, L_0x2961010; 1 drivers
+v0x295e140_0 .net *"_s5", 0 0, L_0x29611f0; 1 drivers
+v0x295e1e0_0 .net "carryin", 0 0, L_0x2961dc0; 1 drivers
+v0x295e280_0 .net "carryout", 0 0, L_0x2961760; 1 drivers
+v0x295e320_0 .net "nB", 0 0, L_0x2951f80; 1 drivers
+v0x295e3d0_0 .net "nCmd2", 0 0, L_0x2960f50; 1 drivers
+v0x295e4d0_0 .net "subtract", 0 0, L_0x29610b0; 1 drivers
+L_0x2960eb0 .part v0x2960210_0, 0, 1;
+L_0x2961010 .part v0x2960210_0, 2, 1;
+L_0x29611f0 .part v0x2960210_0, 0, 1;
+S_0x295d630 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295d540;
+ .timescale -9 -12;
+L_0x28a1f90/d .functor NOT 1, L_0x2960eb0, C4<0>, C4<0>, C4<0>;
+L_0x28a1f90 .delay (10000,10000,10000) L_0x28a1f90/d;
+L_0x2960a40/d .functor AND 1, L_0x2961c90, L_0x28a1f90, C4<1>, C4<1>;
+L_0x2960a40 .delay (20000,20000,20000) L_0x2960a40/d;
+L_0x2960c40/d .functor AND 1, L_0x2951f80, L_0x2960eb0, C4<1>, C4<1>;
+L_0x2960c40 .delay (20000,20000,20000) L_0x2960c40/d;
+L_0x2960ce0/d .functor OR 1, L_0x2960a40, L_0x2960c40, C4<0>, C4<0>;
+L_0x2960ce0 .delay (20000,20000,20000) L_0x2960ce0/d;
+v0x295d720_0 .net "S", 0 0, L_0x2960eb0; 1 drivers
+v0x295d7c0_0 .alias "in0", 0 0, v0x295de50_0;
+v0x295d860_0 .alias "in1", 0 0, v0x295e320_0;
+v0x295d900_0 .net "nS", 0 0, L_0x28a1f90; 1 drivers
+v0x295d9b0_0 .net "out0", 0 0, L_0x2960a40; 1 drivers
+v0x295da50_0 .net "out1", 0 0, L_0x2960c40; 1 drivers
+v0x295db30_0 .alias "outfinal", 0 0, v0x295df00_0;
+S_0x295c230 .scope generate, "addbits[2]" "addbits[2]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x295bc48 .param/l "i" 3 283, +C4<010>;
+S_0x295c3a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x295c230;
+ .timescale -9 -12;
+L_0x2961e60/d .functor NOT 1, L_0x289f010, C4<0>, C4<0>, C4<0>;
+L_0x2961e60 .delay (10000,10000,10000) L_0x2961e60/d;
+L_0x2962560/d .functor NOT 1, L_0x2962620, C4<0>, C4<0>, C4<0>;
+L_0x2962560 .delay (10000,10000,10000) L_0x2962560/d;
+L_0x29626c0/d .functor AND 1, L_0x2962800, L_0x2962560, C4<1>, C4<1>;
+L_0x29626c0 .delay (20000,20000,20000) L_0x29626c0/d;
+L_0x29628a0/d .functor XOR 1, L_0x2963160, L_0x29622f0, C4<0>, C4<0>;
+L_0x29628a0 .delay (40000,40000,40000) L_0x29628a0/d;
+L_0x2962990/d .functor XOR 1, L_0x29628a0, L_0x289f160, C4<0>, C4<0>;
+L_0x2962990 .delay (40000,40000,40000) L_0x2962990/d;
+L_0x2962a80/d .functor AND 1, L_0x2963160, L_0x29622f0, C4<1>, C4<1>;
+L_0x2962a80 .delay (20000,20000,20000) L_0x2962a80/d;
+L_0x2962bf0/d .functor AND 1, L_0x29628a0, L_0x289f160, C4<1>, C4<1>;
+L_0x2962bf0 .delay (20000,20000,20000) L_0x2962bf0/d;
+L_0x2962ce0/d .functor OR 1, L_0x2962a80, L_0x2962bf0, C4<0>, C4<0>;
+L_0x2962ce0 .delay (20000,20000,20000) L_0x2962ce0/d;
+v0x295ca30_0 .net "A", 0 0, L_0x2963160; 1 drivers
+v0x295caf0_0 .net "AandB", 0 0, L_0x2962a80; 1 drivers
+v0x295cb90_0 .net "AddSubSLTSum", 0 0, L_0x2962990; 1 drivers
+v0x295cc30_0 .net "AxorB", 0 0, L_0x29628a0; 1 drivers
+v0x295ccb0_0 .net "B", 0 0, L_0x289f010; 1 drivers
+v0x295cd60_0 .net "BornB", 0 0, L_0x29622f0; 1 drivers
+v0x295ce20_0 .net "CINandAxorB", 0 0, L_0x2962bf0; 1 drivers
+v0x295cea0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x295cf20_0 .net *"_s3", 0 0, L_0x2962620; 1 drivers
+v0x295cfa0_0 .net *"_s5", 0 0, L_0x2962800; 1 drivers
+v0x295d040_0 .net "carryin", 0 0, L_0x289f160; 1 drivers
+v0x295d0e0_0 .net "carryout", 0 0, L_0x2962ce0; 1 drivers
+v0x295d180_0 .net "nB", 0 0, L_0x2961e60; 1 drivers
+v0x295d230_0 .net "nCmd2", 0 0, L_0x2962560; 1 drivers
+v0x295d330_0 .net "subtract", 0 0, L_0x29626c0; 1 drivers
+L_0x29624c0 .part v0x2960210_0, 0, 1;
+L_0x2962620 .part v0x2960210_0, 2, 1;
+L_0x2962800 .part v0x2960210_0, 0, 1;
+S_0x295c490 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295c3a0;
+ .timescale -9 -12;
+L_0x2962010/d .functor NOT 1, L_0x29624c0, C4<0>, C4<0>, C4<0>;
+L_0x2962010 .delay (10000,10000,10000) L_0x2962010/d;
+L_0x29620d0/d .functor AND 1, L_0x289f010, L_0x2962010, C4<1>, C4<1>;
+L_0x29620d0 .delay (20000,20000,20000) L_0x29620d0/d;
+L_0x29621e0/d .functor AND 1, L_0x2961e60, L_0x29624c0, C4<1>, C4<1>;
+L_0x29621e0 .delay (20000,20000,20000) L_0x29621e0/d;
+L_0x29622f0/d .functor OR 1, L_0x29620d0, L_0x29621e0, C4<0>, C4<0>;
+L_0x29622f0 .delay (20000,20000,20000) L_0x29622f0/d;
+v0x295c580_0 .net "S", 0 0, L_0x29624c0; 1 drivers
+v0x295c620_0 .alias "in0", 0 0, v0x295ccb0_0;
+v0x295c6c0_0 .alias "in1", 0 0, v0x295d180_0;
+v0x295c760_0 .net "nS", 0 0, L_0x2962010; 1 drivers
+v0x295c810_0 .net "out0", 0 0, L_0x29620d0; 1 drivers
+v0x295c8b0_0 .net "out1", 0 0, L_0x29621e0; 1 drivers
+v0x295c990_0 .alias "outfinal", 0 0, v0x295cd60_0;
+S_0x295b090 .scope generate, "addbits[3]" "addbits[3]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x295aaa8 .param/l "i" 3 283, +C4<011>;
+S_0x295b200 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x295b090;
+ .timescale -9 -12;
+L_0x289efb0/d .functor NOT 1, L_0x2964a90, C4<0>, C4<0>, C4<0>;
+L_0x289efb0 .delay (10000,10000,10000) L_0x289efb0/d;
+L_0x2963c50/d .functor NOT 1, L_0x2963d10, C4<0>, C4<0>, C4<0>;
+L_0x2963c50 .delay (10000,10000,10000) L_0x2963c50/d;
+L_0x2963db0/d .functor AND 1, L_0x2963ef0, L_0x2963c50, C4<1>, C4<1>;
+L_0x2963db0 .delay (20000,20000,20000) L_0x2963db0/d;
+L_0x2963f90/d .functor XOR 1, L_0x2964960, L_0x29639e0, C4<0>, C4<0>;
+L_0x2963f90 .delay (40000,40000,40000) L_0x2963f90/d;
+L_0x2964080/d .functor XOR 1, L_0x2963f90, L_0x2964bc0, C4<0>, C4<0>;
+L_0x2964080 .delay (40000,40000,40000) L_0x2964080/d;
+L_0x2964170/d .functor AND 1, L_0x2964960, L_0x29639e0, C4<1>, C4<1>;
+L_0x2964170 .delay (20000,20000,20000) L_0x2964170/d;
+L_0x29642e0/d .functor AND 1, L_0x2963f90, L_0x2964bc0, C4<1>, C4<1>;
+L_0x29642e0 .delay (20000,20000,20000) L_0x29642e0/d;
+L_0x29643f0/d .functor OR 1, L_0x2964170, L_0x29642e0, C4<0>, C4<0>;
+L_0x29643f0 .delay (20000,20000,20000) L_0x29643f0/d;
+v0x295b890_0 .net "A", 0 0, L_0x2964960; 1 drivers
+v0x295b950_0 .net "AandB", 0 0, L_0x2964170; 1 drivers
+v0x295b9f0_0 .net "AddSubSLTSum", 0 0, L_0x2964080; 1 drivers
+v0x295ba90_0 .net "AxorB", 0 0, L_0x2963f90; 1 drivers
+v0x295bb10_0 .net "B", 0 0, L_0x2964a90; 1 drivers
+v0x295bbc0_0 .net "BornB", 0 0, L_0x29639e0; 1 drivers
+v0x295bc80_0 .net "CINandAxorB", 0 0, L_0x29642e0; 1 drivers
+v0x295bd00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x295bd80_0 .net *"_s3", 0 0, L_0x2963d10; 1 drivers
+v0x295be00_0 .net *"_s5", 0 0, L_0x2963ef0; 1 drivers
+v0x295bea0_0 .net "carryin", 0 0, L_0x2964bc0; 1 drivers
+v0x295bf40_0 .net "carryout", 0 0, L_0x29643f0; 1 drivers
+v0x295bfe0_0 .net "nB", 0 0, L_0x289efb0; 1 drivers
+v0x295c090_0 .net "nCmd2", 0 0, L_0x2963c50; 1 drivers
+v0x295c190_0 .net "subtract", 0 0, L_0x2963db0; 1 drivers
+L_0x2963bb0 .part v0x2960210_0, 0, 1;
+L_0x2963d10 .part v0x2960210_0, 2, 1;
+L_0x2963ef0 .part v0x2960210_0, 0, 1;
+S_0x295b2f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295b200;
+ .timescale -9 -12;
+L_0x2963740/d .functor NOT 1, L_0x2963bb0, C4<0>, C4<0>, C4<0>;
+L_0x2963740 .delay (10000,10000,10000) L_0x2963740/d;
+L_0x29637c0/d .functor AND 1, L_0x2964a90, L_0x2963740, C4<1>, C4<1>;
+L_0x29637c0 .delay (20000,20000,20000) L_0x29637c0/d;
+L_0x29638d0/d .functor AND 1, L_0x289efb0, L_0x2963bb0, C4<1>, C4<1>;
+L_0x29638d0 .delay (20000,20000,20000) L_0x29638d0/d;
+L_0x29639e0/d .functor OR 1, L_0x29637c0, L_0x29638d0, C4<0>, C4<0>;
+L_0x29639e0 .delay (20000,20000,20000) L_0x29639e0/d;
+v0x295b3e0_0 .net "S", 0 0, L_0x2963bb0; 1 drivers
+v0x295b480_0 .alias "in0", 0 0, v0x295bb10_0;
+v0x295b520_0 .alias "in1", 0 0, v0x295bfe0_0;
+v0x295b5c0_0 .net "nS", 0 0, L_0x2963740; 1 drivers
+v0x295b670_0 .net "out0", 0 0, L_0x29637c0; 1 drivers
+v0x295b710_0 .net "out1", 0 0, L_0x29638d0; 1 drivers
+v0x295b7f0_0 .alias "outfinal", 0 0, v0x295bbc0_0;
+S_0x2959ef0 .scope generate, "addbits[4]" "addbits[4]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2959908 .param/l "i" 3 283, +C4<0100>;
+S_0x295a060 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2959ef0;
+ .timescale -9 -12;
+L_0x2964a00/d .functor NOT 1, L_0x2965db0, C4<0>, C4<0>, C4<0>;
+L_0x2964a00 .delay (10000,10000,10000) L_0x2964a00/d;
+L_0x29652f0/d .functor NOT 1, L_0x29653b0, C4<0>, C4<0>, C4<0>;
+L_0x29652f0 .delay (10000,10000,10000) L_0x29652f0/d;
+L_0x2965450/d .functor AND 1, L_0x2965590, L_0x29652f0, C4<1>, C4<1>;
+L_0x2965450 .delay (20000,20000,20000) L_0x2965450/d;
+L_0x2965630/d .functor XOR 1, L_0x2965eb0, L_0x2965080, C4<0>, C4<0>;
+L_0x2965630 .delay (40000,40000,40000) L_0x2965630/d;
+L_0x2965720/d .functor XOR 1, L_0x2965630, L_0x29660a0, C4<0>, C4<0>;
+L_0x2965720 .delay (40000,40000,40000) L_0x2965720/d;
+L_0x2965810/d .functor AND 1, L_0x2965eb0, L_0x2965080, C4<1>, C4<1>;
+L_0x2965810 .delay (20000,20000,20000) L_0x2965810/d;
+L_0x2965980/d .functor AND 1, L_0x2965630, L_0x29660a0, C4<1>, C4<1>;
+L_0x2965980 .delay (20000,20000,20000) L_0x2965980/d;
+L_0x2965a70/d .functor OR 1, L_0x2965810, L_0x2965980, C4<0>, C4<0>;
+L_0x2965a70 .delay (20000,20000,20000) L_0x2965a70/d;
+v0x295a6f0_0 .net "A", 0 0, L_0x2965eb0; 1 drivers
+v0x295a7b0_0 .net "AandB", 0 0, L_0x2965810; 1 drivers
+v0x295a850_0 .net "AddSubSLTSum", 0 0, L_0x2965720; 1 drivers
+v0x295a8f0_0 .net "AxorB", 0 0, L_0x2965630; 1 drivers
+v0x295a970_0 .net "B", 0 0, L_0x2965db0; 1 drivers
+v0x295aa20_0 .net "BornB", 0 0, L_0x2965080; 1 drivers
+v0x295aae0_0 .net "CINandAxorB", 0 0, L_0x2965980; 1 drivers
+v0x295ab60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x295abe0_0 .net *"_s3", 0 0, L_0x29653b0; 1 drivers
+v0x295ac60_0 .net *"_s5", 0 0, L_0x2965590; 1 drivers
+v0x295ad00_0 .net "carryin", 0 0, L_0x29660a0; 1 drivers
+v0x295ada0_0 .net "carryout", 0 0, L_0x2965a70; 1 drivers
+v0x295ae40_0 .net "nB", 0 0, L_0x2964a00; 1 drivers
+v0x295aef0_0 .net "nCmd2", 0 0, L_0x29652f0; 1 drivers
+v0x295aff0_0 .net "subtract", 0 0, L_0x2965450; 1 drivers
+L_0x2965250 .part v0x2960210_0, 0, 1;
+L_0x29653b0 .part v0x2960210_0, 2, 1;
+L_0x2965590 .part v0x2960210_0, 0, 1;
+S_0x295a150 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x295a060;
+ .timescale -9 -12;
+L_0x2964da0/d .functor NOT 1, L_0x2965250, C4<0>, C4<0>, C4<0>;
+L_0x2964da0 .delay (10000,10000,10000) L_0x2964da0/d;
+L_0x2964e60/d .functor AND 1, L_0x2965db0, L_0x2964da0, C4<1>, C4<1>;
+L_0x2964e60 .delay (20000,20000,20000) L_0x2964e60/d;
+L_0x2964f70/d .functor AND 1, L_0x2964a00, L_0x2965250, C4<1>, C4<1>;
+L_0x2964f70 .delay (20000,20000,20000) L_0x2964f70/d;
+L_0x2965080/d .functor OR 1, L_0x2964e60, L_0x2964f70, C4<0>, C4<0>;
+L_0x2965080 .delay (20000,20000,20000) L_0x2965080/d;
+v0x295a240_0 .net "S", 0 0, L_0x2965250; 1 drivers
+v0x295a2e0_0 .alias "in0", 0 0, v0x295a970_0;
+v0x295a380_0 .alias "in1", 0 0, v0x295ae40_0;
+v0x295a420_0 .net "nS", 0 0, L_0x2964da0; 1 drivers
+v0x295a4d0_0 .net "out0", 0 0, L_0x2964e60; 1 drivers
+v0x295a570_0 .net "out1", 0 0, L_0x2964f70; 1 drivers
+v0x295a650_0 .alias "outfinal", 0 0, v0x295aa20_0;
+S_0x2958d50 .scope generate, "addbits[5]" "addbits[5]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2958768 .param/l "i" 3 283, +C4<0101>;
+S_0x2958ec0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2958d50;
+ .timescale -9 -12;
+L_0x29636b0/d .functor NOT 1, L_0x2967410, C4<0>, C4<0>, C4<0>;
+L_0x29636b0 .delay (10000,10000,10000) L_0x29636b0/d;
+L_0x2966890/d .functor NOT 1, L_0x2966950, C4<0>, C4<0>, C4<0>;
+L_0x2966890 .delay (10000,10000,10000) L_0x2966890/d;
+L_0x29669f0/d .functor AND 1, L_0x2966b30, L_0x2966890, C4<1>, C4<1>;
+L_0x29669f0 .delay (20000,20000,20000) L_0x29669f0/d;
+L_0x2966bd0/d .functor XOR 1, L_0x2967540, L_0x2966620, C4<0>, C4<0>;
+L_0x2966bd0 .delay (40000,40000,40000) L_0x2966bd0/d;
+L_0x2966cc0/d .functor XOR 1, L_0x2966bd0, L_0x2967760, C4<0>, C4<0>;
+L_0x2966cc0 .delay (40000,40000,40000) L_0x2966cc0/d;
+L_0x2966db0/d .functor AND 1, L_0x2967540, L_0x2966620, C4<1>, C4<1>;
+L_0x2966db0 .delay (20000,20000,20000) L_0x2966db0/d;
+L_0x2966f20/d .functor AND 1, L_0x2966bd0, L_0x2967760, C4<1>, C4<1>;
+L_0x2966f20 .delay (20000,20000,20000) L_0x2966f20/d;
+L_0x2967010/d .functor OR 1, L_0x2966db0, L_0x2966f20, C4<0>, C4<0>;
+L_0x2967010 .delay (20000,20000,20000) L_0x2967010/d;
+v0x2959550_0 .net "A", 0 0, L_0x2967540; 1 drivers
+v0x2959610_0 .net "AandB", 0 0, L_0x2966db0; 1 drivers
+v0x29596b0_0 .net "AddSubSLTSum", 0 0, L_0x2966cc0; 1 drivers
+v0x2959750_0 .net "AxorB", 0 0, L_0x2966bd0; 1 drivers
+v0x29597d0_0 .net "B", 0 0, L_0x2967410; 1 drivers
+v0x2959880_0 .net "BornB", 0 0, L_0x2966620; 1 drivers
+v0x2959940_0 .net "CINandAxorB", 0 0, L_0x2966f20; 1 drivers
+v0x29599c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2959a40_0 .net *"_s3", 0 0, L_0x2966950; 1 drivers
+v0x2959ac0_0 .net *"_s5", 0 0, L_0x2966b30; 1 drivers
+v0x2959b60_0 .net "carryin", 0 0, L_0x2967760; 1 drivers
+v0x2959c00_0 .net "carryout", 0 0, L_0x2967010; 1 drivers
+v0x2959ca0_0 .net "nB", 0 0, L_0x29636b0; 1 drivers
+v0x2959d50_0 .net "nCmd2", 0 0, L_0x2966890; 1 drivers
+v0x2959e50_0 .net "subtract", 0 0, L_0x29669f0; 1 drivers
+L_0x29667f0 .part v0x2960210_0, 0, 1;
+L_0x2966950 .part v0x2960210_0, 2, 1;
+L_0x2966b30 .part v0x2960210_0, 0, 1;
+S_0x2958fb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2958ec0;
+ .timescale -9 -12;
+L_0x2966340/d .functor NOT 1, L_0x29667f0, C4<0>, C4<0>, C4<0>;
+L_0x2966340 .delay (10000,10000,10000) L_0x2966340/d;
+L_0x2966400/d .functor AND 1, L_0x2967410, L_0x2966340, C4<1>, C4<1>;
+L_0x2966400 .delay (20000,20000,20000) L_0x2966400/d;
+L_0x2966510/d .functor AND 1, L_0x29636b0, L_0x29667f0, C4<1>, C4<1>;
+L_0x2966510 .delay (20000,20000,20000) L_0x2966510/d;
+L_0x2966620/d .functor OR 1, L_0x2966400, L_0x2966510, C4<0>, C4<0>;
+L_0x2966620 .delay (20000,20000,20000) L_0x2966620/d;
+v0x29590a0_0 .net "S", 0 0, L_0x29667f0; 1 drivers
+v0x2959140_0 .alias "in0", 0 0, v0x29597d0_0;
+v0x29591e0_0 .alias "in1", 0 0, v0x2959ca0_0;
+v0x2959280_0 .net "nS", 0 0, L_0x2966340; 1 drivers
+v0x2959330_0 .net "out0", 0 0, L_0x2966400; 1 drivers
+v0x29593d0_0 .net "out1", 0 0, L_0x2966510; 1 drivers
+v0x29594b0_0 .alias "outfinal", 0 0, v0x2959880_0;
+S_0x2957bb0 .scope generate, "addbits[6]" "addbits[6]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x29575c8 .param/l "i" 3 283, +C4<0110>;
+S_0x2957d20 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2957bb0;
+ .timescale -9 -12;
+L_0x29675e0/d .functor NOT 1, L_0x2968900, C4<0>, C4<0>, C4<0>;
+L_0x29675e0 .delay (10000,10000,10000) L_0x29675e0/d;
+L_0x2967e20/d .functor NOT 1, L_0x2967ee0, C4<0>, C4<0>, C4<0>;
+L_0x2967e20 .delay (10000,10000,10000) L_0x2967e20/d;
+L_0x2967f80/d .functor AND 1, L_0x29680c0, L_0x2967e20, C4<1>, C4<1>;
+L_0x2967f80 .delay (20000,20000,20000) L_0x2967f80/d;
+L_0x2968160/d .functor XOR 1, L_0x2968a10, L_0x2967bb0, C4<0>, C4<0>;
+L_0x2968160 .delay (40000,40000,40000) L_0x2968160/d;
+L_0x2968250/d .functor XOR 1, L_0x2968160, L_0x2968c60, C4<0>, C4<0>;
+L_0x2968250 .delay (40000,40000,40000) L_0x2968250/d;
+L_0x2968340/d .functor AND 1, L_0x2968a10, L_0x2967bb0, C4<1>, C4<1>;
+L_0x2968340 .delay (20000,20000,20000) L_0x2968340/d;
+L_0x29684b0/d .functor AND 1, L_0x2968160, L_0x2968c60, C4<1>, C4<1>;
+L_0x29684b0 .delay (20000,20000,20000) L_0x29684b0/d;
+L_0x29685c0/d .functor OR 1, L_0x2968340, L_0x29684b0, C4<0>, C4<0>;
+L_0x29685c0 .delay (20000,20000,20000) L_0x29685c0/d;
+v0x29583b0_0 .net "A", 0 0, L_0x2968a10; 1 drivers
+v0x2958470_0 .net "AandB", 0 0, L_0x2968340; 1 drivers
+v0x2958510_0 .net "AddSubSLTSum", 0 0, L_0x2968250; 1 drivers
+v0x29585b0_0 .net "AxorB", 0 0, L_0x2968160; 1 drivers
+v0x2958630_0 .net "B", 0 0, L_0x2968900; 1 drivers
+v0x29586e0_0 .net "BornB", 0 0, L_0x2967bb0; 1 drivers
+v0x29587a0_0 .net "CINandAxorB", 0 0, L_0x29684b0; 1 drivers
+v0x2958820_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x29588a0_0 .net *"_s3", 0 0, L_0x2967ee0; 1 drivers
+v0x2958920_0 .net *"_s5", 0 0, L_0x29680c0; 1 drivers
+v0x29589c0_0 .net "carryin", 0 0, L_0x2968c60; 1 drivers
+v0x2958a60_0 .net "carryout", 0 0, L_0x29685c0; 1 drivers
+v0x2958b00_0 .net "nB", 0 0, L_0x29675e0; 1 drivers
+v0x2958bb0_0 .net "nCmd2", 0 0, L_0x2967e20; 1 drivers
+v0x2958cb0_0 .net "subtract", 0 0, L_0x2967f80; 1 drivers
+L_0x2967d80 .part v0x2960210_0, 0, 1;
+L_0x2967ee0 .part v0x2960210_0, 2, 1;
+L_0x29680c0 .part v0x2960210_0, 0, 1;
+S_0x2957e10 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2957d20;
+ .timescale -9 -12;
+L_0x2967950/d .functor NOT 1, L_0x2967d80, C4<0>, C4<0>, C4<0>;
+L_0x2967950 .delay (10000,10000,10000) L_0x2967950/d;
+L_0x29679b0/d .functor AND 1, L_0x2968900, L_0x2967950, C4<1>, C4<1>;
+L_0x29679b0 .delay (20000,20000,20000) L_0x29679b0/d;
+L_0x2967aa0/d .functor AND 1, L_0x29675e0, L_0x2967d80, C4<1>, C4<1>;
+L_0x2967aa0 .delay (20000,20000,20000) L_0x2967aa0/d;
+L_0x2967bb0/d .functor OR 1, L_0x29679b0, L_0x2967aa0, C4<0>, C4<0>;
+L_0x2967bb0 .delay (20000,20000,20000) L_0x2967bb0/d;
+v0x2957f00_0 .net "S", 0 0, L_0x2967d80; 1 drivers
+v0x2957fa0_0 .alias "in0", 0 0, v0x2958630_0;
+v0x2958040_0 .alias "in1", 0 0, v0x2958b00_0;
+v0x29580e0_0 .net "nS", 0 0, L_0x2967950; 1 drivers
+v0x2958190_0 .net "out0", 0 0, L_0x29679b0; 1 drivers
+v0x2958230_0 .net "out1", 0 0, L_0x2967aa0; 1 drivers
+v0x2958310_0 .alias "outfinal", 0 0, v0x29586e0_0;
+S_0x2956a10 .scope generate, "addbits[7]" "addbits[7]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2956428 .param/l "i" 3 283, +C4<0111>;
+S_0x2956b80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2956a10;
+ .timescale -9 -12;
+L_0x29689a0/d .functor NOT 1, L_0x2969e20, C4<0>, C4<0>, C4<0>;
+L_0x29689a0 .delay (10000,10000,10000) L_0x29689a0/d;
+L_0x2969360/d .functor NOT 1, L_0x2969420, C4<0>, C4<0>, C4<0>;
+L_0x2969360 .delay (10000,10000,10000) L_0x2969360/d;
+L_0x29694c0/d .functor AND 1, L_0x2969600, L_0x2969360, C4<1>, C4<1>;
+L_0x29694c0 .delay (20000,20000,20000) L_0x29694c0/d;
+L_0x29696a0/d .functor XOR 1, L_0x2969f60, L_0x29690f0, C4<0>, C4<0>;
+L_0x29696a0 .delay (40000,40000,40000) L_0x29696a0/d;
+L_0x2969790/d .functor XOR 1, L_0x29696a0, L_0x296a150, C4<0>, C4<0>;
+L_0x2969790 .delay (40000,40000,40000) L_0x2969790/d;
+L_0x2969880/d .functor AND 1, L_0x2969f60, L_0x29690f0, C4<1>, C4<1>;
+L_0x2969880 .delay (20000,20000,20000) L_0x2969880/d;
+L_0x29699f0/d .functor AND 1, L_0x29696a0, L_0x296a150, C4<1>, C4<1>;
+L_0x29699f0 .delay (20000,20000,20000) L_0x29699f0/d;
+L_0x2969ae0/d .functor OR 1, L_0x2969880, L_0x29699f0, C4<0>, C4<0>;
+L_0x2969ae0 .delay (20000,20000,20000) L_0x2969ae0/d;
+v0x2957210_0 .net "A", 0 0, L_0x2969f60; 1 drivers
+v0x29572d0_0 .net "AandB", 0 0, L_0x2969880; 1 drivers
+v0x2957370_0 .net "AddSubSLTSum", 0 0, L_0x2969790; 1 drivers
+v0x2957410_0 .net "AxorB", 0 0, L_0x29696a0; 1 drivers
+v0x2957490_0 .net "B", 0 0, L_0x2969e20; 1 drivers
+v0x2957540_0 .net "BornB", 0 0, L_0x29690f0; 1 drivers
+v0x2957600_0 .net "CINandAxorB", 0 0, L_0x29699f0; 1 drivers
+v0x2957680_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2957700_0 .net *"_s3", 0 0, L_0x2969420; 1 drivers
+v0x2957780_0 .net *"_s5", 0 0, L_0x2969600; 1 drivers
+v0x2957820_0 .net "carryin", 0 0, L_0x296a150; 1 drivers
+v0x29578c0_0 .net "carryout", 0 0, L_0x2969ae0; 1 drivers
+v0x2957960_0 .net "nB", 0 0, L_0x29689a0; 1 drivers
+v0x2957a10_0 .net "nCmd2", 0 0, L_0x2969360; 1 drivers
+v0x2957b10_0 .net "subtract", 0 0, L_0x29694c0; 1 drivers
+L_0x29692c0 .part v0x2960210_0, 0, 1;
+L_0x2969420 .part v0x2960210_0, 2, 1;
+L_0x2969600 .part v0x2960210_0, 0, 1;
+S_0x2956c70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2956b80;
+ .timescale -9 -12;
+L_0x2968e30/d .functor NOT 1, L_0x29692c0, C4<0>, C4<0>, C4<0>;
+L_0x2968e30 .delay (10000,10000,10000) L_0x2968e30/d;
+L_0x2968ed0/d .functor AND 1, L_0x2969e20, L_0x2968e30, C4<1>, C4<1>;
+L_0x2968ed0 .delay (20000,20000,20000) L_0x2968ed0/d;
+L_0x2968fe0/d .functor AND 1, L_0x29689a0, L_0x29692c0, C4<1>, C4<1>;
+L_0x2968fe0 .delay (20000,20000,20000) L_0x2968fe0/d;
+L_0x29690f0/d .functor OR 1, L_0x2968ed0, L_0x2968fe0, C4<0>, C4<0>;
+L_0x29690f0 .delay (20000,20000,20000) L_0x29690f0/d;
+v0x2956d60_0 .net "S", 0 0, L_0x29692c0; 1 drivers
+v0x2956e00_0 .alias "in0", 0 0, v0x2957490_0;
+v0x2956ea0_0 .alias "in1", 0 0, v0x2957960_0;
+v0x2956f40_0 .net "nS", 0 0, L_0x2968e30; 1 drivers
+v0x2956ff0_0 .net "out0", 0 0, L_0x2968ed0; 1 drivers
+v0x2957090_0 .net "out1", 0 0, L_0x2968fe0; 1 drivers
+v0x2957170_0 .alias "outfinal", 0 0, v0x2957540_0;
+S_0x2955870 .scope generate, "addbits[8]" "addbits[8]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2955288 .param/l "i" 3 283, +C4<01000>;
+S_0x29559e0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2955870;
+ .timescale -9 -12;
+L_0x296a000/d .functor NOT 1, L_0x296b340, C4<0>, C4<0>, C4<0>;
+L_0x296a000 .delay (10000,10000,10000) L_0x296a000/d;
+L_0x296a880/d .functor NOT 1, L_0x296a940, C4<0>, C4<0>, C4<0>;
+L_0x296a880 .delay (10000,10000,10000) L_0x296a880/d;
+L_0x296a9e0/d .functor AND 1, L_0x296ab20, L_0x296a880, C4<1>, C4<1>;
+L_0x296a9e0 .delay (20000,20000,20000) L_0x296a9e0/d;
+L_0x296abc0/d .functor XOR 1, L_0x296b4b0, L_0x296a610, C4<0>, C4<0>;
+L_0x296abc0 .delay (40000,40000,40000) L_0x296abc0/d;
+L_0x296acb0/d .functor XOR 1, L_0x296abc0, L_0x296b6d0, C4<0>, C4<0>;
+L_0x296acb0 .delay (40000,40000,40000) L_0x296acb0/d;
+L_0x296ada0/d .functor AND 1, L_0x296b4b0, L_0x296a610, C4<1>, C4<1>;
+L_0x296ada0 .delay (20000,20000,20000) L_0x296ada0/d;
+L_0x296af10/d .functor AND 1, L_0x296abc0, L_0x296b6d0, C4<1>, C4<1>;
+L_0x296af10 .delay (20000,20000,20000) L_0x296af10/d;
+L_0x296b000/d .functor OR 1, L_0x296ada0, L_0x296af10, C4<0>, C4<0>;
+L_0x296b000 .delay (20000,20000,20000) L_0x296b000/d;
+v0x2956070_0 .net "A", 0 0, L_0x296b4b0; 1 drivers
+v0x2956130_0 .net "AandB", 0 0, L_0x296ada0; 1 drivers
+v0x29561d0_0 .net "AddSubSLTSum", 0 0, L_0x296acb0; 1 drivers
+v0x2956270_0 .net "AxorB", 0 0, L_0x296abc0; 1 drivers
+v0x29562f0_0 .net "B", 0 0, L_0x296b340; 1 drivers
+v0x29563a0_0 .net "BornB", 0 0, L_0x296a610; 1 drivers
+v0x2956460_0 .net "CINandAxorB", 0 0, L_0x296af10; 1 drivers
+v0x29564e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2956560_0 .net *"_s3", 0 0, L_0x296a940; 1 drivers
+v0x29565e0_0 .net *"_s5", 0 0, L_0x296ab20; 1 drivers
+v0x2956680_0 .net "carryin", 0 0, L_0x296b6d0; 1 drivers
+v0x2956720_0 .net "carryout", 0 0, L_0x296b000; 1 drivers
+v0x29567c0_0 .net "nB", 0 0, L_0x296a000; 1 drivers
+v0x2956870_0 .net "nCmd2", 0 0, L_0x296a880; 1 drivers
+v0x2956970_0 .net "subtract", 0 0, L_0x296a9e0; 1 drivers
+L_0x296a7e0 .part v0x2960210_0, 0, 1;
+L_0x296a940 .part v0x2960210_0, 2, 1;
+L_0x296ab20 .part v0x2960210_0, 0, 1;
+S_0x2955ad0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29559e0;
+ .timescale -9 -12;
+L_0x296a350/d .functor NOT 1, L_0x296a7e0, C4<0>, C4<0>, C4<0>;
+L_0x296a350 .delay (10000,10000,10000) L_0x296a350/d;
+L_0x296a3f0/d .functor AND 1, L_0x296b340, L_0x296a350, C4<1>, C4<1>;
+L_0x296a3f0 .delay (20000,20000,20000) L_0x296a3f0/d;
+L_0x296a500/d .functor AND 1, L_0x296a000, L_0x296a7e0, C4<1>, C4<1>;
+L_0x296a500 .delay (20000,20000,20000) L_0x296a500/d;
+L_0x296a610/d .functor OR 1, L_0x296a3f0, L_0x296a500, C4<0>, C4<0>;
+L_0x296a610 .delay (20000,20000,20000) L_0x296a610/d;
+v0x2955bc0_0 .net "S", 0 0, L_0x296a7e0; 1 drivers
+v0x2955c60_0 .alias "in0", 0 0, v0x29562f0_0;
+v0x2955d00_0 .alias "in1", 0 0, v0x29567c0_0;
+v0x2955da0_0 .net "nS", 0 0, L_0x296a350; 1 drivers
+v0x2955e50_0 .net "out0", 0 0, L_0x296a3f0; 1 drivers
+v0x2955ef0_0 .net "out1", 0 0, L_0x296a500; 1 drivers
+v0x2955fd0_0 .alias "outfinal", 0 0, v0x29563a0_0;
+S_0x29546d0 .scope generate, "addbits[9]" "addbits[9]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x29540e8 .param/l "i" 3 283, +C4<01001>;
+S_0x2954840 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x29546d0;
+ .timescale -9 -12;
+L_0x296a2e0/d .functor NOT 1, L_0x296cb00, C4<0>, C4<0>, C4<0>;
+L_0x296a2e0 .delay (10000,10000,10000) L_0x296a2e0/d;
+L_0x296be90/d .functor NOT 1, L_0x296bf50, C4<0>, C4<0>, C4<0>;
+L_0x296be90 .delay (10000,10000,10000) L_0x296be90/d;
+L_0x296bff0/d .functor AND 1, L_0x296c130, L_0x296be90, C4<1>, C4<1>;
+L_0x296bff0 .delay (20000,20000,20000) L_0x296bff0/d;
+L_0x296c1d0/d .functor XOR 1, L_0x296ba70, L_0x296bc20, C4<0>, C4<0>;
+L_0x296c1d0 .delay (40000,40000,40000) L_0x296c1d0/d;
+L_0x296c2c0/d .functor XOR 1, L_0x296c1d0, L_0x296cc30, C4<0>, C4<0>;
+L_0x296c2c0 .delay (40000,40000,40000) L_0x296c2c0/d;
+L_0x296c3b0/d .functor AND 1, L_0x296ba70, L_0x296bc20, C4<1>, C4<1>;
+L_0x296c3b0 .delay (20000,20000,20000) L_0x296c3b0/d;
+L_0x296c520/d .functor AND 1, L_0x296c1d0, L_0x296cc30, C4<1>, C4<1>;
+L_0x296c520 .delay (20000,20000,20000) L_0x296c520/d;
+L_0x296c610/d .functor OR 1, L_0x296c3b0, L_0x296c520, C4<0>, C4<0>;
+L_0x296c610 .delay (20000,20000,20000) L_0x296c610/d;
+v0x2954ed0_0 .net "A", 0 0, L_0x296ba70; 1 drivers
+v0x2954f90_0 .net "AandB", 0 0, L_0x296c3b0; 1 drivers
+v0x2955030_0 .net "AddSubSLTSum", 0 0, L_0x296c2c0; 1 drivers
+v0x29550d0_0 .net "AxorB", 0 0, L_0x296c1d0; 1 drivers
+v0x2955150_0 .net "B", 0 0, L_0x296cb00; 1 drivers
+v0x2955200_0 .net "BornB", 0 0, L_0x296bc20; 1 drivers
+v0x29552c0_0 .net "CINandAxorB", 0 0, L_0x296c520; 1 drivers
+v0x2955340_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x29553c0_0 .net *"_s3", 0 0, L_0x296bf50; 1 drivers
+v0x2955440_0 .net *"_s5", 0 0, L_0x296c130; 1 drivers
+v0x29554e0_0 .net "carryin", 0 0, L_0x296cc30; 1 drivers
+v0x2955580_0 .net "carryout", 0 0, L_0x296c610; 1 drivers
+v0x2955620_0 .net "nB", 0 0, L_0x296a2e0; 1 drivers
+v0x29556d0_0 .net "nCmd2", 0 0, L_0x296be90; 1 drivers
+v0x29557d0_0 .net "subtract", 0 0, L_0x296bff0; 1 drivers
+L_0x296bdf0 .part v0x2960210_0, 0, 1;
+L_0x296bf50 .part v0x2960210_0, 2, 1;
+L_0x296c130 .part v0x2960210_0, 0, 1;
+S_0x2954930 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2954840;
+ .timescale -9 -12;
+L_0x296b550/d .functor NOT 1, L_0x296bdf0, C4<0>, C4<0>, C4<0>;
+L_0x296b550 .delay (10000,10000,10000) L_0x296b550/d;
+L_0x296b610/d .functor AND 1, L_0x296cb00, L_0x296b550, C4<1>, C4<1>;
+L_0x296b610 .delay (20000,20000,20000) L_0x296b610/d;
+L_0x296bb10/d .functor AND 1, L_0x296a2e0, L_0x296bdf0, C4<1>, C4<1>;
+L_0x296bb10 .delay (20000,20000,20000) L_0x296bb10/d;
+L_0x296bc20/d .functor OR 1, L_0x296b610, L_0x296bb10, C4<0>, C4<0>;
+L_0x296bc20 .delay (20000,20000,20000) L_0x296bc20/d;
+v0x2954a20_0 .net "S", 0 0, L_0x296bdf0; 1 drivers
+v0x2954ac0_0 .alias "in0", 0 0, v0x2955150_0;
+v0x2954b60_0 .alias "in1", 0 0, v0x2955620_0;
+v0x2954c00_0 .net "nS", 0 0, L_0x296b550; 1 drivers
+v0x2954cb0_0 .net "out0", 0 0, L_0x296b610; 1 drivers
+v0x2954d50_0 .net "out1", 0 0, L_0x296bb10; 1 drivers
+v0x2954e30_0 .alias "outfinal", 0 0, v0x2955200_0;
+S_0x2953530 .scope generate, "addbits[10]" "addbits[10]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2952f48 .param/l "i" 3 283, +C4<01010>;
+S_0x29536a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2953530;
+ .timescale -9 -12;
+L_0x296c950/d .functor NOT 1, L_0x296e040, C4<0>, C4<0>, C4<0>;
+L_0x296c950 .delay (10000,10000,10000) L_0x296c950/d;
+L_0x296d3a0/d .functor NOT 1, L_0x296d460, C4<0>, C4<0>, C4<0>;
+L_0x296d3a0 .delay (10000,10000,10000) L_0x296d3a0/d;
+L_0x296d500/d .functor AND 1, L_0x296d640, L_0x296d3a0, C4<1>, C4<1>;
+L_0x296d500 .delay (20000,20000,20000) L_0x296d500/d;
+L_0x296d6e0/d .functor XOR 1, L_0x296cdc0, L_0x296d130, C4<0>, C4<0>;
+L_0x296d6e0 .delay (40000,40000,40000) L_0x296d6e0/d;
+L_0x296d7d0/d .functor XOR 1, L_0x296d6e0, L_0x296e170, C4<0>, C4<0>;
+L_0x296d7d0 .delay (40000,40000,40000) L_0x296d7d0/d;
+L_0x296d8c0/d .functor AND 1, L_0x296cdc0, L_0x296d130, C4<1>, C4<1>;
+L_0x296d8c0 .delay (20000,20000,20000) L_0x296d8c0/d;
+L_0x296da30/d .functor AND 1, L_0x296d6e0, L_0x296e170, C4<1>, C4<1>;
+L_0x296da30 .delay (20000,20000,20000) L_0x296da30/d;
+L_0x296db20/d .functor OR 1, L_0x296d8c0, L_0x296da30, C4<0>, C4<0>;
+L_0x296db20 .delay (20000,20000,20000) L_0x296db20/d;
+v0x2953d30_0 .net "A", 0 0, L_0x296cdc0; 1 drivers
+v0x2953df0_0 .net "AandB", 0 0, L_0x296d8c0; 1 drivers
+v0x2953e90_0 .net "AddSubSLTSum", 0 0, L_0x296d7d0; 1 drivers
+v0x2953f30_0 .net "AxorB", 0 0, L_0x296d6e0; 1 drivers
+v0x2953fb0_0 .net "B", 0 0, L_0x296e040; 1 drivers
+v0x2954060_0 .net "BornB", 0 0, L_0x296d130; 1 drivers
+v0x2954120_0 .net "CINandAxorB", 0 0, L_0x296da30; 1 drivers
+v0x29541a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2954220_0 .net *"_s3", 0 0, L_0x296d460; 1 drivers
+v0x29542a0_0 .net *"_s5", 0 0, L_0x296d640; 1 drivers
+v0x2954340_0 .net "carryin", 0 0, L_0x296e170; 1 drivers
+v0x29543e0_0 .net "carryout", 0 0, L_0x296db20; 1 drivers
+v0x2954480_0 .net "nB", 0 0, L_0x296c950; 1 drivers
+v0x2954530_0 .net "nCmd2", 0 0, L_0x296d3a0; 1 drivers
+v0x2954630_0 .net "subtract", 0 0, L_0x296d500; 1 drivers
+L_0x296d300 .part v0x2960210_0, 0, 1;
+L_0x296d460 .part v0x2960210_0, 2, 1;
+L_0x296d640 .part v0x2960210_0, 0, 1;
+S_0x2953790 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29536a0;
+ .timescale -9 -12;
+L_0x296ce90/d .functor NOT 1, L_0x296d300, C4<0>, C4<0>, C4<0>;
+L_0x296ce90 .delay (10000,10000,10000) L_0x296ce90/d;
+L_0x296cf30/d .functor AND 1, L_0x296e040, L_0x296ce90, C4<1>, C4<1>;
+L_0x296cf30 .delay (20000,20000,20000) L_0x296cf30/d;
+L_0x296d020/d .functor AND 1, L_0x296c950, L_0x296d300, C4<1>, C4<1>;
+L_0x296d020 .delay (20000,20000,20000) L_0x296d020/d;
+L_0x296d130/d .functor OR 1, L_0x296cf30, L_0x296d020, C4<0>, C4<0>;
+L_0x296d130 .delay (20000,20000,20000) L_0x296d130/d;
+v0x2953880_0 .net "S", 0 0, L_0x296d300; 1 drivers
+v0x2953920_0 .alias "in0", 0 0, v0x2953fb0_0;
+v0x29539c0_0 .alias "in1", 0 0, v0x2954480_0;
+v0x2953a60_0 .net "nS", 0 0, L_0x296ce90; 1 drivers
+v0x2953b10_0 .net "out0", 0 0, L_0x296cf30; 1 drivers
+v0x2953bb0_0 .net "out1", 0 0, L_0x296d020; 1 drivers
+v0x2953c90_0 .alias "outfinal", 0 0, v0x2954060_0;
+S_0x2952390 .scope generate, "addbits[11]" "addbits[11]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2951cf8 .param/l "i" 3 283, +C4<01011>;
+S_0x2952500 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2952390;
+ .timescale -9 -12;
+L_0x296de60/d .functor NOT 1, L_0x296e2b0, C4<0>, C4<0>, C4<0>;
+L_0x296de60 .delay (10000,10000,10000) L_0x296de60/d;
+L_0x296e8b0/d .functor NOT 1, L_0x296e970, C4<0>, C4<0>, C4<0>;
+L_0x296e8b0 .delay (10000,10000,10000) L_0x296e8b0/d;
+L_0x296ea10/d .functor AND 1, L_0x296eb50, L_0x296e8b0, C4<1>, C4<1>;
+L_0x296ea10 .delay (20000,20000,20000) L_0x296ea10/d;
+L_0x296ebf0/d .functor XOR 1, L_0x29648a0, L_0x296e640, C4<0>, C4<0>;
+L_0x296ebf0 .delay (40000,40000,40000) L_0x296ebf0/d;
+L_0x296ece0/d .functor XOR 1, L_0x296ebf0, L_0x296f370, C4<0>, C4<0>;
+L_0x296ece0 .delay (40000,40000,40000) L_0x296ece0/d;
+L_0x296edd0/d .functor AND 1, L_0x29648a0, L_0x296e640, C4<1>, C4<1>;
+L_0x296edd0 .delay (20000,20000,20000) L_0x296edd0/d;
+L_0x296ef40/d .functor AND 1, L_0x296ebf0, L_0x296f370, C4<1>, C4<1>;
+L_0x296ef40 .delay (20000,20000,20000) L_0x296ef40/d;
+L_0x296f030/d .functor OR 1, L_0x296edd0, L_0x296ef40, C4<0>, C4<0>;
+L_0x296f030 .delay (20000,20000,20000) L_0x296f030/d;
+v0x2952b90_0 .net "A", 0 0, L_0x29648a0; 1 drivers
+v0x2952c50_0 .net "AandB", 0 0, L_0x296edd0; 1 drivers
+v0x2952cf0_0 .net "AddSubSLTSum", 0 0, L_0x296ece0; 1 drivers
+v0x2952d90_0 .net "AxorB", 0 0, L_0x296ebf0; 1 drivers
+v0x2952e10_0 .net "B", 0 0, L_0x296e2b0; 1 drivers
+v0x2952ec0_0 .net "BornB", 0 0, L_0x296e640; 1 drivers
+v0x2952f80_0 .net "CINandAxorB", 0 0, L_0x296ef40; 1 drivers
+v0x2953000_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2953080_0 .net *"_s3", 0 0, L_0x296e970; 1 drivers
+v0x2953100_0 .net *"_s5", 0 0, L_0x296eb50; 1 drivers
+v0x29531a0_0 .net "carryin", 0 0, L_0x296f370; 1 drivers
+v0x2953240_0 .net "carryout", 0 0, L_0x296f030; 1 drivers
+v0x29532e0_0 .net "nB", 0 0, L_0x296de60; 1 drivers
+v0x2953390_0 .net "nCmd2", 0 0, L_0x296e8b0; 1 drivers
+v0x2953490_0 .net "subtract", 0 0, L_0x296ea10; 1 drivers
+L_0x296e810 .part v0x2960210_0, 0, 1;
+L_0x296e970 .part v0x2960210_0, 2, 1;
+L_0x296eb50 .part v0x2960210_0, 0, 1;
+S_0x29525f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2952500;
+ .timescale -9 -12;
+L_0x296dfc0/d .functor NOT 1, L_0x296e810, C4<0>, C4<0>, C4<0>;
+L_0x296dfc0 .delay (10000,10000,10000) L_0x296dfc0/d;
+L_0x296e440/d .functor AND 1, L_0x296e2b0, L_0x296dfc0, C4<1>, C4<1>;
+L_0x296e440 .delay (20000,20000,20000) L_0x296e440/d;
+L_0x296e530/d .functor AND 1, L_0x296de60, L_0x296e810, C4<1>, C4<1>;
+L_0x296e530 .delay (20000,20000,20000) L_0x296e530/d;
+L_0x296e640/d .functor OR 1, L_0x296e440, L_0x296e530, C4<0>, C4<0>;
+L_0x296e640 .delay (20000,20000,20000) L_0x296e640/d;
+v0x29526e0_0 .net "S", 0 0, L_0x296e810; 1 drivers
+v0x2952780_0 .alias "in0", 0 0, v0x2952e10_0;
+v0x2952820_0 .alias "in1", 0 0, v0x29532e0_0;
+v0x29528c0_0 .net "nS", 0 0, L_0x296dfc0; 1 drivers
+v0x2952970_0 .net "out0", 0 0, L_0x296e440; 1 drivers
+v0x2952a10_0 .net "out1", 0 0, L_0x296e530; 1 drivers
+v0x2952af0_0 .alias "outfinal", 0 0, v0x2952ec0_0;
+S_0x2951180 .scope generate, "addbits[12]" "addbits[12]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2920138 .param/l "i" 3 283, +C4<01100>;
+S_0x29512b0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2951180;
+ .timescale -9 -12;
+L_0x296f410/d .functor NOT 1, L_0x2970bb0, C4<0>, C4<0>, C4<0>;
+L_0x296f410 .delay (10000,10000,10000) L_0x296f410/d;
+L_0x296feb0/d .functor NOT 1, L_0x296ff70, C4<0>, C4<0>, C4<0>;
+L_0x296feb0 .delay (10000,10000,10000) L_0x296feb0/d;
+L_0x2970010/d .functor AND 1, L_0x2970150, L_0x296feb0, C4<1>, C4<1>;
+L_0x2970010 .delay (20000,20000,20000) L_0x2970010/d;
+L_0x29701f0/d .functor XOR 1, L_0x296f870, L_0x296fc40, C4<0>, C4<0>;
+L_0x29701f0 .delay (40000,40000,40000) L_0x29701f0/d;
+L_0x29702e0/d .functor XOR 1, L_0x29701f0, L_0x2970c50, C4<0>, C4<0>;
+L_0x29702e0 .delay (40000,40000,40000) L_0x29702e0/d;
+L_0x29703d0/d .functor AND 1, L_0x296f870, L_0x296fc40, C4<1>, C4<1>;
+L_0x29703d0 .delay (20000,20000,20000) L_0x29703d0/d;
+L_0x2970540/d .functor AND 1, L_0x29701f0, L_0x2970c50, C4<1>, C4<1>;
+L_0x2970540 .delay (20000,20000,20000) L_0x2970540/d;
+L_0x2970630/d .functor OR 1, L_0x29703d0, L_0x2970540, C4<0>, C4<0>;
+L_0x2970630 .delay (20000,20000,20000) L_0x2970630/d;
+v0x2951940_0 .net "A", 0 0, L_0x296f870; 1 drivers
+v0x2951a00_0 .net "AandB", 0 0, L_0x29703d0; 1 drivers
+v0x2951aa0_0 .net "AddSubSLTSum", 0 0, L_0x29702e0; 1 drivers
+v0x2951b40_0 .net "AxorB", 0 0, L_0x29701f0; 1 drivers
+v0x2951bc0_0 .net "B", 0 0, L_0x2970bb0; 1 drivers
+v0x2951c70_0 .net "BornB", 0 0, L_0x296fc40; 1 drivers
+v0x2951d30_0 .net "CINandAxorB", 0 0, L_0x2970540; 1 drivers
+v0x2951db0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2951e80_0 .net *"_s3", 0 0, L_0x296ff70; 1 drivers
+v0x2951f00_0 .net *"_s5", 0 0, L_0x2970150; 1 drivers
+v0x2952000_0 .net "carryin", 0 0, L_0x2970c50; 1 drivers
+v0x29520a0_0 .net "carryout", 0 0, L_0x2970630; 1 drivers
+v0x2952140_0 .net "nB", 0 0, L_0x296f410; 1 drivers
+v0x29521f0_0 .net "nCmd2", 0 0, L_0x296feb0; 1 drivers
+v0x29522f0_0 .net "subtract", 0 0, L_0x2970010; 1 drivers
+L_0x296fe10 .part v0x2960210_0, 0, 1;
+L_0x296ff70 .part v0x2960210_0, 2, 1;
+L_0x2970150 .part v0x2960210_0, 0, 1;
+S_0x29513a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29512b0;
+ .timescale -9 -12;
+L_0x296f9a0/d .functor NOT 1, L_0x296fe10, C4<0>, C4<0>, C4<0>;
+L_0x296f9a0 .delay (10000,10000,10000) L_0x296f9a0/d;
+L_0x296fa40/d .functor AND 1, L_0x2970bb0, L_0x296f9a0, C4<1>, C4<1>;
+L_0x296fa40 .delay (20000,20000,20000) L_0x296fa40/d;
+L_0x296fb30/d .functor AND 1, L_0x296f410, L_0x296fe10, C4<1>, C4<1>;
+L_0x296fb30 .delay (20000,20000,20000) L_0x296fb30/d;
+L_0x296fc40/d .functor OR 1, L_0x296fa40, L_0x296fb30, C4<0>, C4<0>;
+L_0x296fc40 .delay (20000,20000,20000) L_0x296fc40/d;
+v0x2951490_0 .net "S", 0 0, L_0x296fe10; 1 drivers
+v0x2951530_0 .alias "in0", 0 0, v0x2951bc0_0;
+v0x29515d0_0 .alias "in1", 0 0, v0x2952140_0;
+v0x2951670_0 .net "nS", 0 0, L_0x296f9a0; 1 drivers
+v0x2951720_0 .net "out0", 0 0, L_0x296fa40; 1 drivers
+v0x29517c0_0 .net "out1", 0 0, L_0x296fb30; 1 drivers
+v0x29518a0_0 .alias "outfinal", 0 0, v0x2951c70_0;
+S_0x2950030 .scope generate, "addbits[13]" "addbits[13]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x294fa48 .param/l "i" 3 283, +C4<01101>;
+S_0x29501a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2950030;
+ .timescale -9 -12;
+L_0x2970970/d .functor NOT 1, L_0x2970e80, C4<0>, C4<0>, C4<0>;
+L_0x2970970 .delay (10000,10000,10000) L_0x2970970/d;
+L_0x2971370/d .functor NOT 1, L_0x2971430, C4<0>, C4<0>, C4<0>;
+L_0x2971370 .delay (10000,10000,10000) L_0x2971370/d;
+L_0x29714d0/d .functor AND 1, L_0x2971610, L_0x2971370, C4<1>, C4<1>;
+L_0x29714d0 .delay (20000,20000,20000) L_0x29714d0/d;
+L_0x29716b0/d .functor XOR 1, L_0x2970de0, L_0x2971100, C4<0>, C4<0>;
+L_0x29716b0 .delay (40000,40000,40000) L_0x29716b0/d;
+L_0x29717a0/d .functor XOR 1, L_0x29716b0, L_0x2972250, C4<0>, C4<0>;
+L_0x29717a0 .delay (40000,40000,40000) L_0x29717a0/d;
+L_0x2971890/d .functor AND 1, L_0x2970de0, L_0x2971100, C4<1>, C4<1>;
+L_0x2971890 .delay (20000,20000,20000) L_0x2971890/d;
+L_0x2971a00/d .functor AND 1, L_0x29716b0, L_0x2972250, C4<1>, C4<1>;
+L_0x2971a00 .delay (20000,20000,20000) L_0x2971a00/d;
+L_0x2971af0/d .functor OR 1, L_0x2971890, L_0x2971a00, C4<0>, C4<0>;
+L_0x2971af0 .delay (20000,20000,20000) L_0x2971af0/d;
+v0x2950830_0 .net "A", 0 0, L_0x2970de0; 1 drivers
+v0x29508f0_0 .net "AandB", 0 0, L_0x2971890; 1 drivers
+v0x2950990_0 .net "AddSubSLTSum", 0 0, L_0x29717a0; 1 drivers
+v0x2950a30_0 .net "AxorB", 0 0, L_0x29716b0; 1 drivers
+v0x2950ab0_0 .net "B", 0 0, L_0x2970e80; 1 drivers
+v0x2950b60_0 .net "BornB", 0 0, L_0x2971100; 1 drivers
+v0x2950c20_0 .net "CINandAxorB", 0 0, L_0x2971a00; 1 drivers
+v0x2950ca0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2950d20_0 .net *"_s3", 0 0, L_0x2971430; 1 drivers
+v0x2950da0_0 .net *"_s5", 0 0, L_0x2971610; 1 drivers
+v0x2950e40_0 .net "carryin", 0 0, L_0x2972250; 1 drivers
+v0x2950ee0_0 .net "carryout", 0 0, L_0x2971af0; 1 drivers
+v0x2950f80_0 .net "nB", 0 0, L_0x2970970; 1 drivers
+v0x2951000_0 .net "nCmd2", 0 0, L_0x2971370; 1 drivers
+v0x2951100_0 .net "subtract", 0 0, L_0x29714d0; 1 drivers
+L_0x29712d0 .part v0x2960210_0, 0, 1;
+L_0x2971430 .part v0x2960210_0, 2, 1;
+L_0x2971610 .part v0x2960210_0, 0, 1;
+S_0x2950290 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29501a0;
+ .timescale -9 -12;
+L_0x2970ad0/d .functor NOT 1, L_0x29712d0, C4<0>, C4<0>, C4<0>;
+L_0x2970ad0 .delay (10000,10000,10000) L_0x2970ad0/d;
+L_0x2970b50/d .functor AND 1, L_0x2970e80, L_0x2970ad0, C4<1>, C4<1>;
+L_0x2970b50 .delay (20000,20000,20000) L_0x2970b50/d;
+L_0x2970ff0/d .functor AND 1, L_0x2970970, L_0x29712d0, C4<1>, C4<1>;
+L_0x2970ff0 .delay (20000,20000,20000) L_0x2970ff0/d;
+L_0x2971100/d .functor OR 1, L_0x2970b50, L_0x2970ff0, C4<0>, C4<0>;
+L_0x2971100 .delay (20000,20000,20000) L_0x2971100/d;
+v0x2950380_0 .net "S", 0 0, L_0x29712d0; 1 drivers
+v0x2950420_0 .alias "in0", 0 0, v0x2950ab0_0;
+v0x29504c0_0 .alias "in1", 0 0, v0x2950f80_0;
+v0x2950560_0 .net "nS", 0 0, L_0x2970ad0; 1 drivers
+v0x2950610_0 .net "out0", 0 0, L_0x2970b50; 1 drivers
+v0x29506b0_0 .net "out1", 0 0, L_0x2970ff0; 1 drivers
+v0x2950790_0 .alias "outfinal", 0 0, v0x2950b60_0;
+S_0x294ee90 .scope generate, "addbits[14]" "addbits[14]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x294e8a8 .param/l "i" 3 283, +C4<01110>;
+S_0x294f000 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294ee90;
+ .timescale -9 -12;
+L_0x2960540/d .functor NOT 1, L_0x2972480, C4<0>, C4<0>, C4<0>;
+L_0x2960540 .delay (10000,10000,10000) L_0x2960540/d;
+L_0x2972890/d .functor NOT 1, L_0x2972930, C4<0>, C4<0>, C4<0>;
+L_0x2972890 .delay (10000,10000,10000) L_0x2972890/d;
+L_0x29729d0/d .functor AND 1, L_0x2972b10, L_0x2972890, C4<1>, C4<1>;
+L_0x29729d0 .delay (20000,20000,20000) L_0x29729d0/d;
+L_0x2972bb0/d .functor XOR 1, L_0x29723e0, L_0x2972660, C4<0>, C4<0>;
+L_0x2972bb0 .delay (40000,40000,40000) L_0x2972bb0/d;
+L_0x2972ca0/d .functor XOR 1, L_0x2972bb0, L_0x2973640, C4<0>, C4<0>;
+L_0x2972ca0 .delay (40000,40000,40000) L_0x2972ca0/d;
+L_0x2972d90/d .functor AND 1, L_0x29723e0, L_0x2972660, C4<1>, C4<1>;
+L_0x2972d90 .delay (20000,20000,20000) L_0x2972d90/d;
+L_0x2972f00/d .functor AND 1, L_0x2972bb0, L_0x2973640, C4<1>, C4<1>;
+L_0x2972f00 .delay (20000,20000,20000) L_0x2972f00/d;
+L_0x2972ff0/d .functor OR 1, L_0x2972d90, L_0x2972f00, C4<0>, C4<0>;
+L_0x2972ff0 .delay (20000,20000,20000) L_0x2972ff0/d;
+v0x294f690_0 .net "A", 0 0, L_0x29723e0; 1 drivers
+v0x294f750_0 .net "AandB", 0 0, L_0x2972d90; 1 drivers
+v0x294f7f0_0 .net "AddSubSLTSum", 0 0, L_0x2972ca0; 1 drivers
+v0x294f890_0 .net "AxorB", 0 0, L_0x2972bb0; 1 drivers
+v0x294f910_0 .net "B", 0 0, L_0x2972480; 1 drivers
+v0x294f9c0_0 .net "BornB", 0 0, L_0x2972660; 1 drivers
+v0x294fa80_0 .net "CINandAxorB", 0 0, L_0x2972f00; 1 drivers
+v0x294fb00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x294fb80_0 .net *"_s3", 0 0, L_0x2972930; 1 drivers
+v0x294fc00_0 .net *"_s5", 0 0, L_0x2972b10; 1 drivers
+v0x294fca0_0 .net "carryin", 0 0, L_0x2973640; 1 drivers
+v0x294fd40_0 .net "carryout", 0 0, L_0x2972ff0; 1 drivers
+v0x294fde0_0 .net "nB", 0 0, L_0x2960540; 1 drivers
+v0x294fe90_0 .net "nCmd2", 0 0, L_0x2972890; 1 drivers
+v0x294ff90_0 .net "subtract", 0 0, L_0x29729d0; 1 drivers
+L_0x29727f0 .part v0x2960210_0, 0, 1;
+L_0x2972930 .part v0x2960210_0, 2, 1;
+L_0x2972b10 .part v0x2960210_0, 0, 1;
+S_0x294f0f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294f000;
+ .timescale -9 -12;
+L_0x2971fc0/d .functor NOT 1, L_0x29727f0, C4<0>, C4<0>, C4<0>;
+L_0x2971fc0 .delay (10000,10000,10000) L_0x2971fc0/d;
+L_0x2972080/d .functor AND 1, L_0x2972480, L_0x2971fc0, C4<1>, C4<1>;
+L_0x2972080 .delay (20000,20000,20000) L_0x2972080/d;
+L_0x2972570/d .functor AND 1, L_0x2960540, L_0x29727f0, C4<1>, C4<1>;
+L_0x2972570 .delay (20000,20000,20000) L_0x2972570/d;
+L_0x2972660/d .functor OR 1, L_0x2972080, L_0x2972570, C4<0>, C4<0>;
+L_0x2972660 .delay (20000,20000,20000) L_0x2972660/d;
+v0x294f1e0_0 .net "S", 0 0, L_0x29727f0; 1 drivers
+v0x294f280_0 .alias "in0", 0 0, v0x294f910_0;
+v0x294f320_0 .alias "in1", 0 0, v0x294fde0_0;
+v0x294f3c0_0 .net "nS", 0 0, L_0x2971fc0; 1 drivers
+v0x294f470_0 .net "out0", 0 0, L_0x2972080; 1 drivers
+v0x294f510_0 .net "out1", 0 0, L_0x2972570; 1 drivers
+v0x294f5f0_0 .alias "outfinal", 0 0, v0x294f9c0_0;
+S_0x294dcf0 .scope generate, "addbits[15]" "addbits[15]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x294d708 .param/l "i" 3 283, +C4<01111>;
+S_0x294de60 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294dcf0;
+ .timescale -9 -12;
+L_0x2973310/d .functor NOT 1, L_0x2973870, C4<0>, C4<0>, C4<0>;
+L_0x2973310 .delay (10000,10000,10000) L_0x2973310/d;
+L_0x2973d00/d .functor NOT 1, L_0x2973da0, C4<0>, C4<0>, C4<0>;
+L_0x2973d00 .delay (10000,10000,10000) L_0x2973d00/d;
+L_0x2973e40/d .functor AND 1, L_0x2973f80, L_0x2973d00, C4<1>, C4<1>;
+L_0x2973e40 .delay (20000,20000,20000) L_0x2973e40/d;
+L_0x2974020/d .functor XOR 1, L_0x29737d0, L_0x2973ad0, C4<0>, C4<0>;
+L_0x2974020 .delay (40000,40000,40000) L_0x2974020/d;
+L_0x2974110/d .functor XOR 1, L_0x2974020, L_0x2974ae0, C4<0>, C4<0>;
+L_0x2974110 .delay (40000,40000,40000) L_0x2974110/d;
+L_0x2974200/d .functor AND 1, L_0x29737d0, L_0x2973ad0, C4<1>, C4<1>;
+L_0x2974200 .delay (20000,20000,20000) L_0x2974200/d;
+L_0x2974370/d .functor AND 1, L_0x2974020, L_0x2974ae0, C4<1>, C4<1>;
+L_0x2974370 .delay (20000,20000,20000) L_0x2974370/d;
+L_0x2974460/d .functor OR 1, L_0x2974200, L_0x2974370, C4<0>, C4<0>;
+L_0x2974460 .delay (20000,20000,20000) L_0x2974460/d;
+v0x294e4f0_0 .net "A", 0 0, L_0x29737d0; 1 drivers
+v0x294e5b0_0 .net "AandB", 0 0, L_0x2974200; 1 drivers
+v0x294e650_0 .net "AddSubSLTSum", 0 0, L_0x2974110; 1 drivers
+v0x294e6f0_0 .net "AxorB", 0 0, L_0x2974020; 1 drivers
+v0x294e770_0 .net "B", 0 0, L_0x2973870; 1 drivers
+v0x294e820_0 .net "BornB", 0 0, L_0x2973ad0; 1 drivers
+v0x294e8e0_0 .net "CINandAxorB", 0 0, L_0x2974370; 1 drivers
+v0x294e960_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x294e9e0_0 .net *"_s3", 0 0, L_0x2973da0; 1 drivers
+v0x294ea60_0 .net *"_s5", 0 0, L_0x2973f80; 1 drivers
+v0x294eb00_0 .net "carryin", 0 0, L_0x2974ae0; 1 drivers
+v0x294eba0_0 .net "carryout", 0 0, L_0x2974460; 1 drivers
+v0x294ec40_0 .net "nB", 0 0, L_0x2973310; 1 drivers
+v0x294ecf0_0 .net "nCmd2", 0 0, L_0x2973d00; 1 drivers
+v0x294edf0_0 .net "subtract", 0 0, L_0x2973e40; 1 drivers
+L_0x2973c60 .part v0x2960210_0, 0, 1;
+L_0x2973da0 .part v0x2960210_0, 2, 1;
+L_0x2973f80 .part v0x2960210_0, 0, 1;
+S_0x294df50 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294de60;
+ .timescale -9 -12;
+L_0x2973420/d .functor NOT 1, L_0x2973c60, C4<0>, C4<0>, C4<0>;
+L_0x2973420 .delay (10000,10000,10000) L_0x2973420/d;
+L_0x29734e0/d .functor AND 1, L_0x2973870, L_0x2973420, C4<1>, C4<1>;
+L_0x29734e0 .delay (20000,20000,20000) L_0x29734e0/d;
+L_0x29739e0/d .functor AND 1, L_0x2973310, L_0x2973c60, C4<1>, C4<1>;
+L_0x29739e0 .delay (20000,20000,20000) L_0x29739e0/d;
+L_0x2973ad0/d .functor OR 1, L_0x29734e0, L_0x29739e0, C4<0>, C4<0>;
+L_0x2973ad0 .delay (20000,20000,20000) L_0x2973ad0/d;
+v0x294e040_0 .net "S", 0 0, L_0x2973c60; 1 drivers
+v0x294e0e0_0 .alias "in0", 0 0, v0x294e770_0;
+v0x294e180_0 .alias "in1", 0 0, v0x294ec40_0;
+v0x294e220_0 .net "nS", 0 0, L_0x2973420; 1 drivers
+v0x294e2d0_0 .net "out0", 0 0, L_0x29734e0; 1 drivers
+v0x294e370_0 .net "out1", 0 0, L_0x29739e0; 1 drivers
+v0x294e450_0 .alias "outfinal", 0 0, v0x294e820_0;
+S_0x294cb50 .scope generate, "addbits[16]" "addbits[16]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x294c568 .param/l "i" 3 283, +C4<010000>;
+S_0x294ccc0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294cb50;
+ .timescale -9 -12;
+L_0x2973910/d .functor NOT 1, L_0x2974d10, C4<0>, C4<0>, C4<0>;
+L_0x2973910 .delay (10000,10000,10000) L_0x2973910/d;
+L_0x2975180/d .functor NOT 1, L_0x2975220, C4<0>, C4<0>, C4<0>;
+L_0x2975180 .delay (10000,10000,10000) L_0x2975180/d;
+L_0x29752c0/d .functor AND 1, L_0x2975400, L_0x2975180, C4<1>, C4<1>;
+L_0x29752c0 .delay (20000,20000,20000) L_0x29752c0/d;
+L_0x29754a0/d .functor XOR 1, L_0x2974c70, L_0x2974f50, C4<0>, C4<0>;
+L_0x29754a0 .delay (40000,40000,40000) L_0x29754a0/d;
+L_0x2975590/d .functor XOR 1, L_0x29754a0, L_0x2975f00, C4<0>, C4<0>;
+L_0x2975590 .delay (40000,40000,40000) L_0x2975590/d;
+L_0x2975680/d .functor AND 1, L_0x2974c70, L_0x2974f50, C4<1>, C4<1>;
+L_0x2975680 .delay (20000,20000,20000) L_0x2975680/d;
+L_0x29757f0/d .functor AND 1, L_0x29754a0, L_0x2975f00, C4<1>, C4<1>;
+L_0x29757f0 .delay (20000,20000,20000) L_0x29757f0/d;
+L_0x29758e0/d .functor OR 1, L_0x2975680, L_0x29757f0, C4<0>, C4<0>;
+L_0x29758e0 .delay (20000,20000,20000) L_0x29758e0/d;
+v0x294d350_0 .net "A", 0 0, L_0x2974c70; 1 drivers
+v0x294d410_0 .net "AandB", 0 0, L_0x2975680; 1 drivers
+v0x294d4b0_0 .net "AddSubSLTSum", 0 0, L_0x2975590; 1 drivers
+v0x294d550_0 .net "AxorB", 0 0, L_0x29754a0; 1 drivers
+v0x294d5d0_0 .net "B", 0 0, L_0x2974d10; 1 drivers
+v0x294d680_0 .net "BornB", 0 0, L_0x2974f50; 1 drivers
+v0x294d740_0 .net "CINandAxorB", 0 0, L_0x29757f0; 1 drivers
+v0x294d7c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x294d840_0 .net *"_s3", 0 0, L_0x2975220; 1 drivers
+v0x294d8c0_0 .net *"_s5", 0 0, L_0x2975400; 1 drivers
+v0x294d960_0 .net "carryin", 0 0, L_0x2975f00; 1 drivers
+v0x294da00_0 .net "carryout", 0 0, L_0x29758e0; 1 drivers
+v0x294daa0_0 .net "nB", 0 0, L_0x2973910; 1 drivers
+v0x294db50_0 .net "nCmd2", 0 0, L_0x2975180; 1 drivers
+v0x294dc50_0 .net "subtract", 0 0, L_0x29752c0; 1 drivers
+L_0x29750e0 .part v0x2960210_0, 0, 1;
+L_0x2975220 .part v0x2960210_0, 2, 1;
+L_0x2975400 .part v0x2960210_0, 0, 1;
+S_0x294cdb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294ccc0;
+ .timescale -9 -12;
+L_0x2974860/d .functor NOT 1, L_0x29750e0, C4<0>, C4<0>, C4<0>;
+L_0x2974860 .delay (10000,10000,10000) L_0x2974860/d;
+L_0x2974920/d .functor AND 1, L_0x2974d10, L_0x2974860, C4<1>, C4<1>;
+L_0x2974920 .delay (20000,20000,20000) L_0x2974920/d;
+L_0x2974e60/d .functor AND 1, L_0x2973910, L_0x29750e0, C4<1>, C4<1>;
+L_0x2974e60 .delay (20000,20000,20000) L_0x2974e60/d;
+L_0x2974f50/d .functor OR 1, L_0x2974920, L_0x2974e60, C4<0>, C4<0>;
+L_0x2974f50 .delay (20000,20000,20000) L_0x2974f50/d;
+v0x294cea0_0 .net "S", 0 0, L_0x29750e0; 1 drivers
+v0x294cf40_0 .alias "in0", 0 0, v0x294d5d0_0;
+v0x294cfe0_0 .alias "in1", 0 0, v0x294daa0_0;
+v0x294d080_0 .net "nS", 0 0, L_0x2974860; 1 drivers
+v0x294d130_0 .net "out0", 0 0, L_0x2974920; 1 drivers
+v0x294d1d0_0 .net "out1", 0 0, L_0x2974e60; 1 drivers
+v0x294d2b0_0 .alias "outfinal", 0 0, v0x294d680_0;
+S_0x294b9b0 .scope generate, "addbits[17]" "addbits[17]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x294b3c8 .param/l "i" 3 283, +C4<010001>;
+S_0x294bb20 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294b9b0;
+ .timescale -9 -12;
+L_0x296b770/d .functor NOT 1, L_0x2976540, C4<0>, C4<0>, C4<0>;
+L_0x296b770 .delay (10000,10000,10000) L_0x296b770/d;
+L_0x2976840/d .functor NOT 1, L_0x29768e0, C4<0>, C4<0>, C4<0>;
+L_0x2976840 .delay (10000,10000,10000) L_0x2976840/d;
+L_0x2976980/d .functor AND 1, L_0x2976ac0, L_0x2976840, C4<1>, C4<1>;
+L_0x2976980 .delay (20000,20000,20000) L_0x2976980/d;
+L_0x2976b60/d .functor XOR 1, L_0x29764a0, L_0x2975e20, C4<0>, C4<0>;
+L_0x2976b60 .delay (40000,40000,40000) L_0x2976b60/d;
+L_0x2976c50/d .functor XOR 1, L_0x2976b60, L_0x29775f0, C4<0>, C4<0>;
+L_0x2976c50 .delay (40000,40000,40000) L_0x2976c50/d;
+L_0x2976d40/d .functor AND 1, L_0x29764a0, L_0x2975e20, C4<1>, C4<1>;
+L_0x2976d40 .delay (20000,20000,20000) L_0x2976d40/d;
+L_0x2976eb0/d .functor AND 1, L_0x2976b60, L_0x29775f0, C4<1>, C4<1>;
+L_0x2976eb0 .delay (20000,20000,20000) L_0x2976eb0/d;
+L_0x2976fa0/d .functor OR 1, L_0x2976d40, L_0x2976eb0, C4<0>, C4<0>;
+L_0x2976fa0 .delay (20000,20000,20000) L_0x2976fa0/d;
+v0x294c1b0_0 .net "A", 0 0, L_0x29764a0; 1 drivers
+v0x294c270_0 .net "AandB", 0 0, L_0x2976d40; 1 drivers
+v0x294c310_0 .net "AddSubSLTSum", 0 0, L_0x2976c50; 1 drivers
+v0x294c3b0_0 .net "AxorB", 0 0, L_0x2976b60; 1 drivers
+v0x294c430_0 .net "B", 0 0, L_0x2976540; 1 drivers
+v0x294c4e0_0 .net "BornB", 0 0, L_0x2975e20; 1 drivers
+v0x294c5a0_0 .net "CINandAxorB", 0 0, L_0x2976eb0; 1 drivers
+v0x294c620_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x294c6a0_0 .net *"_s3", 0 0, L_0x29768e0; 1 drivers
+v0x294c720_0 .net *"_s5", 0 0, L_0x2976ac0; 1 drivers
+v0x294c7c0_0 .net "carryin", 0 0, L_0x29775f0; 1 drivers
+v0x294c860_0 .net "carryout", 0 0, L_0x2976fa0; 1 drivers
+v0x294c900_0 .net "nB", 0 0, L_0x296b770; 1 drivers
+v0x294c9b0_0 .net "nCmd2", 0 0, L_0x2976840; 1 drivers
+v0x294cab0_0 .net "subtract", 0 0, L_0x2976980; 1 drivers
+L_0x29767a0 .part v0x2960210_0, 0, 1;
+L_0x29768e0 .part v0x2960210_0, 2, 1;
+L_0x2976ac0 .part v0x2960210_0, 0, 1;
+S_0x294bc10 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294bb20;
+ .timescale -9 -12;
+L_0x296b8b0/d .functor NOT 1, L_0x29767a0, C4<0>, C4<0>, C4<0>;
+L_0x296b8b0 .delay (10000,10000,10000) L_0x296b8b0/d;
+L_0x2975c00/d .functor AND 1, L_0x2976540, L_0x296b8b0, C4<1>, C4<1>;
+L_0x2975c00 .delay (20000,20000,20000) L_0x2975c00/d;
+L_0x2975d10/d .functor AND 1, L_0x296b770, L_0x29767a0, C4<1>, C4<1>;
+L_0x2975d10 .delay (20000,20000,20000) L_0x2975d10/d;
+L_0x2975e20/d .functor OR 1, L_0x2975c00, L_0x2975d10, C4<0>, C4<0>;
+L_0x2975e20 .delay (20000,20000,20000) L_0x2975e20/d;
+v0x294bd00_0 .net "S", 0 0, L_0x29767a0; 1 drivers
+v0x294bda0_0 .alias "in0", 0 0, v0x294c430_0;
+v0x294be40_0 .alias "in1", 0 0, v0x294c900_0;
+v0x294bee0_0 .net "nS", 0 0, L_0x296b8b0; 1 drivers
+v0x294bf90_0 .net "out0", 0 0, L_0x2975c00; 1 drivers
+v0x294c030_0 .net "out1", 0 0, L_0x2975d10; 1 drivers
+v0x294c110_0 .alias "outfinal", 0 0, v0x294c4e0_0;
+S_0x294a810 .scope generate, "addbits[18]" "addbits[18]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x294a228 .param/l "i" 3 283, +C4<010010>;
+S_0x294a980 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x294a810;
+ .timescale -9 -12;
+L_0x29772c0/d .functor NOT 1, L_0x2977820, C4<0>, C4<0>, C4<0>;
+L_0x29772c0 .delay (10000,10000,10000) L_0x29772c0/d;
+L_0x2977cb0/d .functor NOT 1, L_0x2977d50, C4<0>, C4<0>, C4<0>;
+L_0x2977cb0 .delay (10000,10000,10000) L_0x2977cb0/d;
+L_0x2977df0/d .functor AND 1, L_0x2977f30, L_0x2977cb0, C4<1>, C4<1>;
+L_0x2977df0 .delay (20000,20000,20000) L_0x2977df0/d;
+L_0x2977fd0/d .functor XOR 1, L_0x2977780, L_0x2977a80, C4<0>, C4<0>;
+L_0x2977fd0 .delay (40000,40000,40000) L_0x2977fd0/d;
+L_0x29780c0/d .functor XOR 1, L_0x2977fd0, L_0x2963200, C4<0>, C4<0>;
+L_0x29780c0 .delay (40000,40000,40000) L_0x29780c0/d;
+L_0x29781b0/d .functor AND 1, L_0x2977780, L_0x2977a80, C4<1>, C4<1>;
+L_0x29781b0 .delay (20000,20000,20000) L_0x29781b0/d;
+L_0x2978320/d .functor AND 1, L_0x2977fd0, L_0x2963200, C4<1>, C4<1>;
+L_0x2978320 .delay (20000,20000,20000) L_0x2978320/d;
+L_0x2978410/d .functor OR 1, L_0x29781b0, L_0x2978320, C4<0>, C4<0>;
+L_0x2978410 .delay (20000,20000,20000) L_0x2978410/d;
+v0x294b010_0 .net "A", 0 0, L_0x2977780; 1 drivers
+v0x294b0d0_0 .net "AandB", 0 0, L_0x29781b0; 1 drivers
+v0x294b170_0 .net "AddSubSLTSum", 0 0, L_0x29780c0; 1 drivers
+v0x294b210_0 .net "AxorB", 0 0, L_0x2977fd0; 1 drivers
+v0x294b290_0 .net "B", 0 0, L_0x2977820; 1 drivers
+v0x294b340_0 .net "BornB", 0 0, L_0x2977a80; 1 drivers
+v0x294b400_0 .net "CINandAxorB", 0 0, L_0x2978320; 1 drivers
+v0x294b480_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x294b500_0 .net *"_s3", 0 0, L_0x2977d50; 1 drivers
+v0x294b580_0 .net *"_s5", 0 0, L_0x2977f30; 1 drivers
+v0x294b620_0 .net "carryin", 0 0, L_0x2963200; 1 drivers
+v0x294b6c0_0 .net "carryout", 0 0, L_0x2978410; 1 drivers
+v0x294b760_0 .net "nB", 0 0, L_0x29772c0; 1 drivers
+v0x294b810_0 .net "nCmd2", 0 0, L_0x2977cb0; 1 drivers
+v0x294b910_0 .net "subtract", 0 0, L_0x2977df0; 1 drivers
+L_0x2977c10 .part v0x2960210_0, 0, 1;
+L_0x2977d50 .part v0x2960210_0, 2, 1;
+L_0x2977f30 .part v0x2960210_0, 0, 1;
+S_0x294aa70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x294a980;
+ .timescale -9 -12;
+L_0x29773d0/d .functor NOT 1, L_0x2977c10, C4<0>, C4<0>, C4<0>;
+L_0x29773d0 .delay (10000,10000,10000) L_0x29773d0/d;
+L_0x2977490/d .functor AND 1, L_0x2977820, L_0x29773d0, C4<1>, C4<1>;
+L_0x2977490 .delay (20000,20000,20000) L_0x2977490/d;
+L_0x29779d0/d .functor AND 1, L_0x29772c0, L_0x2977c10, C4<1>, C4<1>;
+L_0x29779d0 .delay (20000,20000,20000) L_0x29779d0/d;
+L_0x2977a80/d .functor OR 1, L_0x2977490, L_0x29779d0, C4<0>, C4<0>;
+L_0x2977a80 .delay (20000,20000,20000) L_0x2977a80/d;
+v0x294ab60_0 .net "S", 0 0, L_0x2977c10; 1 drivers
+v0x294ac00_0 .alias "in0", 0 0, v0x294b290_0;
+v0x294aca0_0 .alias "in1", 0 0, v0x294b760_0;
+v0x294ad40_0 .net "nS", 0 0, L_0x29773d0; 1 drivers
+v0x294adf0_0 .net "out0", 0 0, L_0x2977490; 1 drivers
+v0x294ae90_0 .net "out1", 0 0, L_0x29779d0; 1 drivers
+v0x294af70_0 .alias "outfinal", 0 0, v0x294b340_0;
+S_0x2949670 .scope generate, "addbits[19]" "addbits[19]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2949088 .param/l "i" 3 283, +C4<010011>;
+S_0x29497e0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2949670;
+ .timescale -9 -12;
+L_0x2977950/d .functor NOT 1, L_0x2979790, C4<0>, C4<0>, C4<0>;
+L_0x2977950 .delay (10000,10000,10000) L_0x2977950/d;
+L_0x29789f0/d .functor NOT 1, L_0x2978ed0, C4<0>, C4<0>, C4<0>;
+L_0x29789f0 .delay (10000,10000,10000) L_0x29789f0/d;
+L_0x2978f70/d .functor AND 1, L_0x29790b0, L_0x29789f0, C4<1>, C4<1>;
+L_0x2978f70 .delay (20000,20000,20000) L_0x2978f70/d;
+L_0x2979150/d .functor XOR 1, L_0x29796f0, L_0x2978780, C4<0>, C4<0>;
+L_0x2979150 .delay (40000,40000,40000) L_0x2979150/d;
+L_0x29799c0/d .functor XOR 1, L_0x2979150, L_0x29798c0, C4<0>, C4<0>;
+L_0x29799c0 .delay (40000,40000,40000) L_0x29799c0/d;
+L_0x2979ab0/d .functor AND 1, L_0x29796f0, L_0x2978780, C4<1>, C4<1>;
+L_0x2979ab0 .delay (20000,20000,20000) L_0x2979ab0/d;
+L_0x2979c20/d .functor AND 1, L_0x2979150, L_0x29798c0, C4<1>, C4<1>;
+L_0x2979c20 .delay (20000,20000,20000) L_0x2979c20/d;
+L_0x2979d10/d .functor OR 1, L_0x2979ab0, L_0x2979c20, C4<0>, C4<0>;
+L_0x2979d10 .delay (20000,20000,20000) L_0x2979d10/d;
+v0x2949e70_0 .net "A", 0 0, L_0x29796f0; 1 drivers
+v0x2949f30_0 .net "AandB", 0 0, L_0x2979ab0; 1 drivers
+v0x2949fd0_0 .net "AddSubSLTSum", 0 0, L_0x29799c0; 1 drivers
+v0x294a070_0 .net "AxorB", 0 0, L_0x2979150; 1 drivers
+v0x294a0f0_0 .net "B", 0 0, L_0x2979790; 1 drivers
+v0x294a1a0_0 .net "BornB", 0 0, L_0x2978780; 1 drivers
+v0x294a260_0 .net "CINandAxorB", 0 0, L_0x2979c20; 1 drivers
+v0x294a2e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x294a360_0 .net *"_s3", 0 0, L_0x2978ed0; 1 drivers
+v0x294a3e0_0 .net *"_s5", 0 0, L_0x29790b0; 1 drivers
+v0x294a480_0 .net "carryin", 0 0, L_0x29798c0; 1 drivers
+v0x294a520_0 .net "carryout", 0 0, L_0x2979d10; 1 drivers
+v0x294a5c0_0 .net "nB", 0 0, L_0x2977950; 1 drivers
+v0x294a670_0 .net "nCmd2", 0 0, L_0x29789f0; 1 drivers
+v0x294a770_0 .net "subtract", 0 0, L_0x2978f70; 1 drivers
+L_0x2978950 .part v0x2960210_0, 0, 1;
+L_0x2978ed0 .part v0x2960210_0, 2, 1;
+L_0x29790b0 .part v0x2960210_0, 0, 1;
+S_0x29498d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29497e0;
+ .timescale -9 -12;
+L_0x2963380/d .functor NOT 1, L_0x2978950, C4<0>, C4<0>, C4<0>;
+L_0x2963380 .delay (10000,10000,10000) L_0x2963380/d;
+L_0x29634e0/d .functor AND 1, L_0x2979790, L_0x2963380, C4<1>, C4<1>;
+L_0x29634e0 .delay (20000,20000,20000) L_0x29634e0/d;
+L_0x29635f0/d .functor AND 1, L_0x2977950, L_0x2978950, C4<1>, C4<1>;
+L_0x29635f0 .delay (20000,20000,20000) L_0x29635f0/d;
+L_0x2978780/d .functor OR 1, L_0x29634e0, L_0x29635f0, C4<0>, C4<0>;
+L_0x2978780 .delay (20000,20000,20000) L_0x2978780/d;
+v0x29499c0_0 .net "S", 0 0, L_0x2978950; 1 drivers
+v0x2949a60_0 .alias "in0", 0 0, v0x294a0f0_0;
+v0x2949b00_0 .alias "in1", 0 0, v0x294a5c0_0;
+v0x2949ba0_0 .net "nS", 0 0, L_0x2963380; 1 drivers
+v0x2949c50_0 .net "out0", 0 0, L_0x29634e0; 1 drivers
+v0x2949cf0_0 .net "out1", 0 0, L_0x29635f0; 1 drivers
+v0x2949dd0_0 .alias "outfinal", 0 0, v0x294a1a0_0;
+S_0x29484d0 .scope generate, "addbits[20]" "addbits[20]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2947ee8 .param/l "i" 3 283, +C4<010100>;
+S_0x2948640 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x29484d0;
+ .timescale -9 -12;
+L_0x297a3d0/d .functor NOT 1, L_0x297a1c0, C4<0>, C4<0>, C4<0>;
+L_0x297a3d0 .delay (10000,10000,10000) L_0x297a3d0/d;
+L_0x297a980/d .functor NOT 1, L_0x297aa20, C4<0>, C4<0>, C4<0>;
+L_0x297a980 .delay (10000,10000,10000) L_0x297a980/d;
+L_0x297aac0/d .functor AND 1, L_0x297ac00, L_0x297a980, C4<1>, C4<1>;
+L_0x297aac0 .delay (20000,20000,20000) L_0x297aac0/d;
+L_0x297aca0/d .functor XOR 1, L_0x297a120, L_0x297a750, C4<0>, C4<0>;
+L_0x297aca0 .delay (40000,40000,40000) L_0x297aca0/d;
+L_0x297ad90/d .functor XOR 1, L_0x297aca0, L_0x297a2f0, C4<0>, C4<0>;
+L_0x297ad90 .delay (40000,40000,40000) L_0x297ad90/d;
+L_0x297ae80/d .functor AND 1, L_0x297a120, L_0x297a750, C4<1>, C4<1>;
+L_0x297ae80 .delay (20000,20000,20000) L_0x297ae80/d;
+L_0x297aff0/d .functor AND 1, L_0x297aca0, L_0x297a2f0, C4<1>, C4<1>;
+L_0x297aff0 .delay (20000,20000,20000) L_0x297aff0/d;
+L_0x297b0e0/d .functor OR 1, L_0x297ae80, L_0x297aff0, C4<0>, C4<0>;
+L_0x297b0e0 .delay (20000,20000,20000) L_0x297b0e0/d;
+v0x2948cd0_0 .net "A", 0 0, L_0x297a120; 1 drivers
+v0x2948d90_0 .net "AandB", 0 0, L_0x297ae80; 1 drivers
+v0x2948e30_0 .net "AddSubSLTSum", 0 0, L_0x297ad90; 1 drivers
+v0x2948ed0_0 .net "AxorB", 0 0, L_0x297aca0; 1 drivers
+v0x2948f50_0 .net "B", 0 0, L_0x297a1c0; 1 drivers
+v0x2949000_0 .net "BornB", 0 0, L_0x297a750; 1 drivers
+v0x29490c0_0 .net "CINandAxorB", 0 0, L_0x297aff0; 1 drivers
+v0x2949140_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x29491c0_0 .net *"_s3", 0 0, L_0x297aa20; 1 drivers
+v0x2949240_0 .net *"_s5", 0 0, L_0x297ac00; 1 drivers
+v0x29492e0_0 .net "carryin", 0 0, L_0x297a2f0; 1 drivers
+v0x2949380_0 .net "carryout", 0 0, L_0x297b0e0; 1 drivers
+v0x2949420_0 .net "nB", 0 0, L_0x297a3d0; 1 drivers
+v0x29494d0_0 .net "nCmd2", 0 0, L_0x297a980; 1 drivers
+v0x29495d0_0 .net "subtract", 0 0, L_0x297aac0; 1 drivers
+L_0x297a8e0 .part v0x2960210_0, 0, 1;
+L_0x297aa20 .part v0x2960210_0, 2, 1;
+L_0x297ac00 .part v0x2960210_0, 0, 1;
+S_0x2948730 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2948640;
+ .timescale -9 -12;
+L_0x297a4d0/d .functor NOT 1, L_0x297a8e0, C4<0>, C4<0>, C4<0>;
+L_0x297a4d0 .delay (10000,10000,10000) L_0x297a4d0/d;
+L_0x297a570/d .functor AND 1, L_0x297a1c0, L_0x297a4d0, C4<1>, C4<1>;
+L_0x297a570 .delay (20000,20000,20000) L_0x297a570/d;
+L_0x297a660/d .functor AND 1, L_0x297a3d0, L_0x297a8e0, C4<1>, C4<1>;
+L_0x297a660 .delay (20000,20000,20000) L_0x297a660/d;
+L_0x297a750/d .functor OR 1, L_0x297a570, L_0x297a660, C4<0>, C4<0>;
+L_0x297a750 .delay (20000,20000,20000) L_0x297a750/d;
+v0x2948820_0 .net "S", 0 0, L_0x297a8e0; 1 drivers
+v0x29488c0_0 .alias "in0", 0 0, v0x2948f50_0;
+v0x2948960_0 .alias "in1", 0 0, v0x2949420_0;
+v0x2948a00_0 .net "nS", 0 0, L_0x297a4d0; 1 drivers
+v0x2948ab0_0 .net "out0", 0 0, L_0x297a570; 1 drivers
+v0x2948b50_0 .net "out1", 0 0, L_0x297a660; 1 drivers
+v0x2948c30_0 .alias "outfinal", 0 0, v0x2949000_0;
+S_0x2947330 .scope generate, "addbits[21]" "addbits[21]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2946d48 .param/l "i" 3 283, +C4<010101>;
+S_0x29474a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2947330;
+ .timescale -9 -12;
+L_0x297b7d0/d .functor NOT 1, L_0x297b590, C4<0>, C4<0>, C4<0>;
+L_0x297b7d0 .delay (10000,10000,10000) L_0x297b7d0/d;
+L_0x297bda0/d .functor NOT 1, L_0x297be60, C4<0>, C4<0>, C4<0>;
+L_0x297bda0 .delay (10000,10000,10000) L_0x297bda0/d;
+L_0x297bf00/d .functor AND 1, L_0x297c040, L_0x297bda0, C4<1>, C4<1>;
+L_0x297bf00 .delay (20000,20000,20000) L_0x297bf00/d;
+L_0x297c0e0/d .functor XOR 1, L_0x297b4f0, L_0x297bb30, C4<0>, C4<0>;
+L_0x297c0e0 .delay (40000,40000,40000) L_0x297c0e0/d;
+L_0x297c1d0/d .functor XOR 1, L_0x297c0e0, L_0x297b6c0, C4<0>, C4<0>;
+L_0x297c1d0 .delay (40000,40000,40000) L_0x297c1d0/d;
+L_0x297c2c0/d .functor AND 1, L_0x297b4f0, L_0x297bb30, C4<1>, C4<1>;
+L_0x297c2c0 .delay (20000,20000,20000) L_0x297c2c0/d;
+L_0x297c430/d .functor AND 1, L_0x297c0e0, L_0x297b6c0, C4<1>, C4<1>;
+L_0x297c430 .delay (20000,20000,20000) L_0x297c430/d;
+L_0x297c540/d .functor OR 1, L_0x297c2c0, L_0x297c430, C4<0>, C4<0>;
+L_0x297c540 .delay (20000,20000,20000) L_0x297c540/d;
+v0x2947b30_0 .net "A", 0 0, L_0x297b4f0; 1 drivers
+v0x2947bf0_0 .net "AandB", 0 0, L_0x297c2c0; 1 drivers
+v0x2947c90_0 .net "AddSubSLTSum", 0 0, L_0x297c1d0; 1 drivers
+v0x2947d30_0 .net "AxorB", 0 0, L_0x297c0e0; 1 drivers
+v0x2947db0_0 .net "B", 0 0, L_0x297b590; 1 drivers
+v0x2947e60_0 .net "BornB", 0 0, L_0x297bb30; 1 drivers
+v0x2947f20_0 .net "CINandAxorB", 0 0, L_0x297c430; 1 drivers
+v0x2947fa0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2948020_0 .net *"_s3", 0 0, L_0x297be60; 1 drivers
+v0x29480a0_0 .net *"_s5", 0 0, L_0x297c040; 1 drivers
+v0x2948140_0 .net "carryin", 0 0, L_0x297b6c0; 1 drivers
+v0x29481e0_0 .net "carryout", 0 0, L_0x297c540; 1 drivers
+v0x2948280_0 .net "nB", 0 0, L_0x297b7d0; 1 drivers
+v0x2948330_0 .net "nCmd2", 0 0, L_0x297bda0; 1 drivers
+v0x2948430_0 .net "subtract", 0 0, L_0x297bf00; 1 drivers
+L_0x297bd00 .part v0x2960210_0, 0, 1;
+L_0x297be60 .part v0x2960210_0, 2, 1;
+L_0x297c040 .part v0x2960210_0, 0, 1;
+S_0x2947590 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29474a0;
+ .timescale -9 -12;
+L_0x297b8d0/d .functor NOT 1, L_0x297bd00, C4<0>, C4<0>, C4<0>;
+L_0x297b8d0 .delay (10000,10000,10000) L_0x297b8d0/d;
+L_0x297b930/d .functor AND 1, L_0x297b590, L_0x297b8d0, C4<1>, C4<1>;
+L_0x297b930 .delay (20000,20000,20000) L_0x297b930/d;
+L_0x297ba20/d .functor AND 1, L_0x297b7d0, L_0x297bd00, C4<1>, C4<1>;
+L_0x297ba20 .delay (20000,20000,20000) L_0x297ba20/d;
+L_0x297bb30/d .functor OR 1, L_0x297b930, L_0x297ba20, C4<0>, C4<0>;
+L_0x297bb30 .delay (20000,20000,20000) L_0x297bb30/d;
+v0x2947680_0 .net "S", 0 0, L_0x297bd00; 1 drivers
+v0x2947720_0 .alias "in0", 0 0, v0x2947db0_0;
+v0x29477c0_0 .alias "in1", 0 0, v0x2948280_0;
+v0x2947860_0 .net "nS", 0 0, L_0x297b8d0; 1 drivers
+v0x2947910_0 .net "out0", 0 0, L_0x297b930; 1 drivers
+v0x29479b0_0 .net "out1", 0 0, L_0x297ba20; 1 drivers
+v0x2947a90_0 .alias "outfinal", 0 0, v0x2947e60_0;
+S_0x2946190 .scope generate, "addbits[22]" "addbits[22]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2945ba8 .param/l "i" 3 283, +C4<010110>;
+S_0x2946300 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2946190;
+ .timescale -9 -12;
+L_0x297b760/d .functor NOT 1, L_0x297ca10, C4<0>, C4<0>, C4<0>;
+L_0x297b760 .delay (10000,10000,10000) L_0x297b760/d;
+L_0x297d2d0/d .functor NOT 1, L_0x297d390, C4<0>, C4<0>, C4<0>;
+L_0x297d2d0 .delay (10000,10000,10000) L_0x297d2d0/d;
+L_0x297d430/d .functor AND 1, L_0x297d570, L_0x297d2d0, C4<1>, C4<1>;
+L_0x297d430 .delay (20000,20000,20000) L_0x297d430/d;
+L_0x297d610/d .functor XOR 1, L_0x297c970, L_0x297d060, C4<0>, C4<0>;
+L_0x297d610 .delay (40000,40000,40000) L_0x297d610/d;
+L_0x297d700/d .functor XOR 1, L_0x297d610, L_0x297cb40, C4<0>, C4<0>;
+L_0x297d700 .delay (40000,40000,40000) L_0x297d700/d;
+L_0x297d7f0/d .functor AND 1, L_0x297c970, L_0x297d060, C4<1>, C4<1>;
+L_0x297d7f0 .delay (20000,20000,20000) L_0x297d7f0/d;
+L_0x297d960/d .functor AND 1, L_0x297d610, L_0x297cb40, C4<1>, C4<1>;
+L_0x297d960 .delay (20000,20000,20000) L_0x297d960/d;
+L_0x297da50/d .functor OR 1, L_0x297d7f0, L_0x297d960, C4<0>, C4<0>;
+L_0x297da50 .delay (20000,20000,20000) L_0x297da50/d;
+v0x2946990_0 .net "A", 0 0, L_0x297c970; 1 drivers
+v0x2946a50_0 .net "AandB", 0 0, L_0x297d7f0; 1 drivers
+v0x2946af0_0 .net "AddSubSLTSum", 0 0, L_0x297d700; 1 drivers
+v0x2946b90_0 .net "AxorB", 0 0, L_0x297d610; 1 drivers
+v0x2946c10_0 .net "B", 0 0, L_0x297ca10; 1 drivers
+v0x2946cc0_0 .net "BornB", 0 0, L_0x297d060; 1 drivers
+v0x2946d80_0 .net "CINandAxorB", 0 0, L_0x297d960; 1 drivers
+v0x2946e00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2946e80_0 .net *"_s3", 0 0, L_0x297d390; 1 drivers
+v0x2946f00_0 .net *"_s5", 0 0, L_0x297d570; 1 drivers
+v0x2946fa0_0 .net "carryin", 0 0, L_0x297cb40; 1 drivers
+v0x2947040_0 .net "carryout", 0 0, L_0x297da50; 1 drivers
+v0x29470e0_0 .net "nB", 0 0, L_0x297b760; 1 drivers
+v0x2947190_0 .net "nCmd2", 0 0, L_0x297d2d0; 1 drivers
+v0x2947290_0 .net "subtract", 0 0, L_0x297d430; 1 drivers
+L_0x297d230 .part v0x2960210_0, 0, 1;
+L_0x297d390 .part v0x2960210_0, 2, 1;
+L_0x297d570 .part v0x2960210_0, 0, 1;
+S_0x29463f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2946300;
+ .timescale -9 -12;
+L_0x297cd80/d .functor NOT 1, L_0x297d230, C4<0>, C4<0>, C4<0>;
+L_0x297cd80 .delay (10000,10000,10000) L_0x297cd80/d;
+L_0x297ce40/d .functor AND 1, L_0x297ca10, L_0x297cd80, C4<1>, C4<1>;
+L_0x297ce40 .delay (20000,20000,20000) L_0x297ce40/d;
+L_0x297cf50/d .functor AND 1, L_0x297b760, L_0x297d230, C4<1>, C4<1>;
+L_0x297cf50 .delay (20000,20000,20000) L_0x297cf50/d;
+L_0x297d060/d .functor OR 1, L_0x297ce40, L_0x297cf50, C4<0>, C4<0>;
+L_0x297d060 .delay (20000,20000,20000) L_0x297d060/d;
+v0x29464e0_0 .net "S", 0 0, L_0x297d230; 1 drivers
+v0x2946580_0 .alias "in0", 0 0, v0x2946c10_0;
+v0x2946620_0 .alias "in1", 0 0, v0x29470e0_0;
+v0x29466c0_0 .net "nS", 0 0, L_0x297cd80; 1 drivers
+v0x2946770_0 .net "out0", 0 0, L_0x297ce40; 1 drivers
+v0x2946810_0 .net "out1", 0 0, L_0x297cf50; 1 drivers
+v0x29468f0_0 .alias "outfinal", 0 0, v0x2946cc0_0;
+S_0x2944ff0 .scope generate, "addbits[23]" "addbits[23]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2944a08 .param/l "i" 3 283, +C4<010111>;
+S_0x2945160 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2944ff0;
+ .timescale -9 -12;
+L_0x297cbe0/d .functor NOT 1, L_0x297df20, C4<0>, C4<0>, C4<0>;
+L_0x297cbe0 .delay (10000,10000,10000) L_0x297cbe0/d;
+L_0x297e6d0/d .functor NOT 1, L_0x297e770, C4<0>, C4<0>, C4<0>;
+L_0x297e6d0 .delay (10000,10000,10000) L_0x297e6d0/d;
+L_0x297e810/d .functor AND 1, L_0x297e950, L_0x297e6d0, C4<1>, C4<1>;
+L_0x297e810 .delay (20000,20000,20000) L_0x297e810/d;
+L_0x297e9f0/d .functor XOR 1, L_0x297de80, L_0x297e4a0, C4<0>, C4<0>;
+L_0x297e9f0 .delay (40000,40000,40000) L_0x297e9f0/d;
+L_0x297eae0/d .functor XOR 1, L_0x297e9f0, L_0x297e050, C4<0>, C4<0>;
+L_0x297eae0 .delay (40000,40000,40000) L_0x297eae0/d;
+L_0x297ebd0/d .functor AND 1, L_0x297de80, L_0x297e4a0, C4<1>, C4<1>;
+L_0x297ebd0 .delay (20000,20000,20000) L_0x297ebd0/d;
+L_0x297ed40/d .functor AND 1, L_0x297e9f0, L_0x297e050, C4<1>, C4<1>;
+L_0x297ed40 .delay (20000,20000,20000) L_0x297ed40/d;
+L_0x297ee30/d .functor OR 1, L_0x297ebd0, L_0x297ed40, C4<0>, C4<0>;
+L_0x297ee30 .delay (20000,20000,20000) L_0x297ee30/d;
+v0x29457f0_0 .net "A", 0 0, L_0x297de80; 1 drivers
+v0x29458b0_0 .net "AandB", 0 0, L_0x297ebd0; 1 drivers
+v0x2945950_0 .net "AddSubSLTSum", 0 0, L_0x297eae0; 1 drivers
+v0x29459f0_0 .net "AxorB", 0 0, L_0x297e9f0; 1 drivers
+v0x2945a70_0 .net "B", 0 0, L_0x297df20; 1 drivers
+v0x2945b20_0 .net "BornB", 0 0, L_0x297e4a0; 1 drivers
+v0x2945be0_0 .net "CINandAxorB", 0 0, L_0x297ed40; 1 drivers
+v0x2945c60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2945ce0_0 .net *"_s3", 0 0, L_0x297e770; 1 drivers
+v0x2945d60_0 .net *"_s5", 0 0, L_0x297e950; 1 drivers
+v0x2945e00_0 .net "carryin", 0 0, L_0x297e050; 1 drivers
+v0x2945ea0_0 .net "carryout", 0 0, L_0x297ee30; 1 drivers
+v0x2945f40_0 .net "nB", 0 0, L_0x297cbe0; 1 drivers
+v0x2945ff0_0 .net "nCmd2", 0 0, L_0x297e6d0; 1 drivers
+v0x29460f0_0 .net "subtract", 0 0, L_0x297e810; 1 drivers
+L_0x297e630 .part v0x2960210_0, 0, 1;
+L_0x297e770 .part v0x2960210_0, 2, 1;
+L_0x297e950 .part v0x2960210_0, 0, 1;
+S_0x2945250 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2945160;
+ .timescale -9 -12;
+L_0x297e260/d .functor NOT 1, L_0x297e630, C4<0>, C4<0>, C4<0>;
+L_0x297e260 .delay (10000,10000,10000) L_0x297e260/d;
+L_0x297e2c0/d .functor AND 1, L_0x297df20, L_0x297e260, C4<1>, C4<1>;
+L_0x297e2c0 .delay (20000,20000,20000) L_0x297e2c0/d;
+L_0x297e3b0/d .functor AND 1, L_0x297cbe0, L_0x297e630, C4<1>, C4<1>;
+L_0x297e3b0 .delay (20000,20000,20000) L_0x297e3b0/d;
+L_0x297e4a0/d .functor OR 1, L_0x297e2c0, L_0x297e3b0, C4<0>, C4<0>;
+L_0x297e4a0 .delay (20000,20000,20000) L_0x297e4a0/d;
+v0x2945340_0 .net "S", 0 0, L_0x297e630; 1 drivers
+v0x29453e0_0 .alias "in0", 0 0, v0x2945a70_0;
+v0x2945480_0 .alias "in1", 0 0, v0x2945f40_0;
+v0x2945520_0 .net "nS", 0 0, L_0x297e260; 1 drivers
+v0x29455d0_0 .net "out0", 0 0, L_0x297e2c0; 1 drivers
+v0x2945670_0 .net "out1", 0 0, L_0x297e3b0; 1 drivers
+v0x2945750_0 .alias "outfinal", 0 0, v0x2945b20_0;
+S_0x2943e50 .scope generate, "addbits[24]" "addbits[24]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2943868 .param/l "i" 3 283, +C4<011000>;
+S_0x2943fc0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2943e50;
+ .timescale -9 -12;
+L_0x297e0f0/d .functor NOT 1, L_0x297f2e0, C4<0>, C4<0>, C4<0>;
+L_0x297e0f0 .delay (10000,10000,10000) L_0x297e0f0/d;
+L_0x297faf0/d .functor NOT 1, L_0x297fbb0, C4<0>, C4<0>, C4<0>;
+L_0x297faf0 .delay (10000,10000,10000) L_0x297faf0/d;
+L_0x297fc50/d .functor AND 1, L_0x297fd90, L_0x297faf0, C4<1>, C4<1>;
+L_0x297fc50 .delay (20000,20000,20000) L_0x297fc50/d;
+L_0x297fe30/d .functor XOR 1, L_0x297f240, L_0x297f880, C4<0>, C4<0>;
+L_0x297fe30 .delay (40000,40000,40000) L_0x297fe30/d;
+L_0x297ff20/d .functor XOR 1, L_0x297fe30, L_0x297f410, C4<0>, C4<0>;
+L_0x297ff20 .delay (40000,40000,40000) L_0x297ff20/d;
+L_0x2980040/d .functor AND 1, L_0x297f240, L_0x297f880, C4<1>, C4<1>;
+L_0x2980040 .delay (20000,20000,20000) L_0x2980040/d;
+L_0x29801e0/d .functor AND 1, L_0x297fe30, L_0x297f410, C4<1>, C4<1>;
+L_0x29801e0 .delay (20000,20000,20000) L_0x29801e0/d;
+L_0x29802f0/d .functor OR 1, L_0x2980040, L_0x29801e0, C4<0>, C4<0>;
+L_0x29802f0 .delay (20000,20000,20000) L_0x29802f0/d;
+v0x2944650_0 .net "A", 0 0, L_0x297f240; 1 drivers
+v0x2944710_0 .net "AandB", 0 0, L_0x2980040; 1 drivers
+v0x29447b0_0 .net "AddSubSLTSum", 0 0, L_0x297ff20; 1 drivers
+v0x2944850_0 .net "AxorB", 0 0, L_0x297fe30; 1 drivers
+v0x29448d0_0 .net "B", 0 0, L_0x297f2e0; 1 drivers
+v0x2944980_0 .net "BornB", 0 0, L_0x297f880; 1 drivers
+v0x2944a40_0 .net "CINandAxorB", 0 0, L_0x29801e0; 1 drivers
+v0x2944ac0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2944b40_0 .net *"_s3", 0 0, L_0x297fbb0; 1 drivers
+v0x2944bc0_0 .net *"_s5", 0 0, L_0x297fd90; 1 drivers
+v0x2944c60_0 .net "carryin", 0 0, L_0x297f410; 1 drivers
+v0x2944d00_0 .net "carryout", 0 0, L_0x29802f0; 1 drivers
+v0x2944da0_0 .net "nB", 0 0, L_0x297e0f0; 1 drivers
+v0x2944e50_0 .net "nCmd2", 0 0, L_0x297faf0; 1 drivers
+v0x2944f50_0 .net "subtract", 0 0, L_0x297fc50; 1 drivers
+L_0x297fa50 .part v0x2960210_0, 0, 1;
+L_0x297fbb0 .part v0x2960210_0, 2, 1;
+L_0x297fd90 .part v0x2960210_0, 0, 1;
+S_0x29440b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2943fc0;
+ .timescale -9 -12;
+L_0x297f600/d .functor NOT 1, L_0x297fa50, C4<0>, C4<0>, C4<0>;
+L_0x297f600 .delay (10000,10000,10000) L_0x297f600/d;
+L_0x297f6a0/d .functor AND 1, L_0x297f2e0, L_0x297f600, C4<1>, C4<1>;
+L_0x297f6a0 .delay (20000,20000,20000) L_0x297f6a0/d;
+L_0x297f790/d .functor AND 1, L_0x297e0f0, L_0x297fa50, C4<1>, C4<1>;
+L_0x297f790 .delay (20000,20000,20000) L_0x297f790/d;
+L_0x297f880/d .functor OR 1, L_0x297f6a0, L_0x297f790, C4<0>, C4<0>;
+L_0x297f880 .delay (20000,20000,20000) L_0x297f880/d;
+v0x29441a0_0 .net "S", 0 0, L_0x297fa50; 1 drivers
+v0x2944240_0 .alias "in0", 0 0, v0x29448d0_0;
+v0x29442e0_0 .alias "in1", 0 0, v0x2944da0_0;
+v0x2944380_0 .net "nS", 0 0, L_0x297f600; 1 drivers
+v0x2944430_0 .net "out0", 0 0, L_0x297f6a0; 1 drivers
+v0x29444d0_0 .net "out1", 0 0, L_0x297f790; 1 drivers
+v0x29445b0_0 .alias "outfinal", 0 0, v0x2944980_0;
+S_0x2942cb0 .scope generate, "addbits[25]" "addbits[25]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x29426c8 .param/l "i" 3 283, +C4<011001>;
+S_0x2942e20 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2942cb0;
+ .timescale -9 -12;
+L_0x297f4b0/d .functor NOT 1, L_0x29807c0, C4<0>, C4<0>, C4<0>;
+L_0x297f4b0 .delay (10000,10000,10000) L_0x297f4b0/d;
+L_0x2980fe0/d .functor NOT 1, L_0x29810a0, C4<0>, C4<0>, C4<0>;
+L_0x2980fe0 .delay (10000,10000,10000) L_0x2980fe0/d;
+L_0x2981140/d .functor AND 1, L_0x2981280, L_0x2980fe0, C4<1>, C4<1>;
+L_0x2981140 .delay (20000,20000,20000) L_0x2981140/d;
+L_0x2981320/d .functor XOR 1, L_0x2980720, L_0x2980d90, C4<0>, C4<0>;
+L_0x2981320 .delay (40000,40000,40000) L_0x2981320/d;
+L_0x2981410/d .functor XOR 1, L_0x2981320, L_0x29808f0, C4<0>, C4<0>;
+L_0x2981410 .delay (40000,40000,40000) L_0x2981410/d;
+L_0x2981530/d .functor AND 1, L_0x2980720, L_0x2980d90, C4<1>, C4<1>;
+L_0x2981530 .delay (20000,20000,20000) L_0x2981530/d;
+L_0x29816d0/d .functor AND 1, L_0x2981320, L_0x29808f0, C4<1>, C4<1>;
+L_0x29816d0 .delay (20000,20000,20000) L_0x29816d0/d;
+L_0x29817e0/d .functor OR 1, L_0x2981530, L_0x29816d0, C4<0>, C4<0>;
+L_0x29817e0 .delay (20000,20000,20000) L_0x29817e0/d;
+v0x29434b0_0 .net "A", 0 0, L_0x2980720; 1 drivers
+v0x2943570_0 .net "AandB", 0 0, L_0x2981530; 1 drivers
+v0x2943610_0 .net "AddSubSLTSum", 0 0, L_0x2981410; 1 drivers
+v0x29436b0_0 .net "AxorB", 0 0, L_0x2981320; 1 drivers
+v0x2943730_0 .net "B", 0 0, L_0x29807c0; 1 drivers
+v0x29437e0_0 .net "BornB", 0 0, L_0x2980d90; 1 drivers
+v0x29438a0_0 .net "CINandAxorB", 0 0, L_0x29816d0; 1 drivers
+v0x2943920_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x29439a0_0 .net *"_s3", 0 0, L_0x29810a0; 1 drivers
+v0x2943a20_0 .net *"_s5", 0 0, L_0x2981280; 1 drivers
+v0x2943ac0_0 .net "carryin", 0 0, L_0x29808f0; 1 drivers
+v0x2943b60_0 .net "carryout", 0 0, L_0x29817e0; 1 drivers
+v0x2943c00_0 .net "nB", 0 0, L_0x297f4b0; 1 drivers
+v0x2943cb0_0 .net "nCmd2", 0 0, L_0x2980fe0; 1 drivers
+v0x2943db0_0 .net "subtract", 0 0, L_0x2981140; 1 drivers
+L_0x2980f40 .part v0x2960210_0, 0, 1;
+L_0x29810a0 .part v0x2960210_0, 2, 1;
+L_0x2981280 .part v0x2960210_0, 0, 1;
+S_0x2942f10 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2942e20;
+ .timescale -9 -12;
+L_0x2980b10/d .functor NOT 1, L_0x2980f40, C4<0>, C4<0>, C4<0>;
+L_0x2980b10 .delay (10000,10000,10000) L_0x2980b10/d;
+L_0x2980bb0/d .functor AND 1, L_0x29807c0, L_0x2980b10, C4<1>, C4<1>;
+L_0x2980bb0 .delay (20000,20000,20000) L_0x2980bb0/d;
+L_0x2980ca0/d .functor AND 1, L_0x297f4b0, L_0x2980f40, C4<1>, C4<1>;
+L_0x2980ca0 .delay (20000,20000,20000) L_0x2980ca0/d;
+L_0x2980d90/d .functor OR 1, L_0x2980bb0, L_0x2980ca0, C4<0>, C4<0>;
+L_0x2980d90 .delay (20000,20000,20000) L_0x2980d90/d;
+v0x2943000_0 .net "S", 0 0, L_0x2980f40; 1 drivers
+v0x29430a0_0 .alias "in0", 0 0, v0x2943730_0;
+v0x2943140_0 .alias "in1", 0 0, v0x2943c00_0;
+v0x29431e0_0 .net "nS", 0 0, L_0x2980b10; 1 drivers
+v0x2943290_0 .net "out0", 0 0, L_0x2980bb0; 1 drivers
+v0x2943330_0 .net "out1", 0 0, L_0x2980ca0; 1 drivers
+v0x2943410_0 .alias "outfinal", 0 0, v0x29437e0_0;
+S_0x2941b10 .scope generate, "addbits[26]" "addbits[26]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2941528 .param/l "i" 3 283, +C4<011010>;
+S_0x2941c80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2941b10;
+ .timescale -9 -12;
+L_0x2980990/d .functor NOT 1, L_0x2981cb0, C4<0>, C4<0>, C4<0>;
+L_0x2980990 .delay (10000,10000,10000) L_0x2980990/d;
+L_0x29824c0/d .functor NOT 1, L_0x2982580, C4<0>, C4<0>, C4<0>;
+L_0x29824c0 .delay (10000,10000,10000) L_0x29824c0/d;
+L_0x2982620/d .functor AND 1, L_0x2982760, L_0x29824c0, C4<1>, C4<1>;
+L_0x2982620 .delay (20000,20000,20000) L_0x2982620/d;
+L_0x2982800/d .functor XOR 1, L_0x2981c10, L_0x2982250, C4<0>, C4<0>;
+L_0x2982800 .delay (40000,40000,40000) L_0x2982800/d;
+L_0x29828f0/d .functor XOR 1, L_0x2982800, L_0x2981de0, C4<0>, C4<0>;
+L_0x29828f0 .delay (40000,40000,40000) L_0x29828f0/d;
+L_0x2982a10/d .functor AND 1, L_0x2981c10, L_0x2982250, C4<1>, C4<1>;
+L_0x2982a10 .delay (20000,20000,20000) L_0x2982a10/d;
+L_0x2982bb0/d .functor AND 1, L_0x2982800, L_0x2981de0, C4<1>, C4<1>;
+L_0x2982bb0 .delay (20000,20000,20000) L_0x2982bb0/d;
+L_0x2982cc0/d .functor OR 1, L_0x2982a10, L_0x2982bb0, C4<0>, C4<0>;
+L_0x2982cc0 .delay (20000,20000,20000) L_0x2982cc0/d;
+v0x2942310_0 .net "A", 0 0, L_0x2981c10; 1 drivers
+v0x29423d0_0 .net "AandB", 0 0, L_0x2982a10; 1 drivers
+v0x2942470_0 .net "AddSubSLTSum", 0 0, L_0x29828f0; 1 drivers
+v0x2942510_0 .net "AxorB", 0 0, L_0x2982800; 1 drivers
+v0x2942590_0 .net "B", 0 0, L_0x2981cb0; 1 drivers
+v0x2942640_0 .net "BornB", 0 0, L_0x2982250; 1 drivers
+v0x2942700_0 .net "CINandAxorB", 0 0, L_0x2982bb0; 1 drivers
+v0x2942780_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2942800_0 .net *"_s3", 0 0, L_0x2982580; 1 drivers
+v0x2942880_0 .net *"_s5", 0 0, L_0x2982760; 1 drivers
+v0x2942920_0 .net "carryin", 0 0, L_0x2981de0; 1 drivers
+v0x29429c0_0 .net "carryout", 0 0, L_0x2982cc0; 1 drivers
+v0x2942a60_0 .net "nB", 0 0, L_0x2980990; 1 drivers
+v0x2942b10_0 .net "nCmd2", 0 0, L_0x29824c0; 1 drivers
+v0x2942c10_0 .net "subtract", 0 0, L_0x2982620; 1 drivers
+L_0x2982420 .part v0x2960210_0, 0, 1;
+L_0x2982580 .part v0x2960210_0, 2, 1;
+L_0x2982760 .part v0x2960210_0, 0, 1;
+S_0x2941d70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2941c80;
+ .timescale -9 -12;
+L_0x2980a60/d .functor NOT 1, L_0x2982420, C4<0>, C4<0>, C4<0>;
+L_0x2980a60 .delay (10000,10000,10000) L_0x2980a60/d;
+L_0x2982070/d .functor AND 1, L_0x2981cb0, L_0x2980a60, C4<1>, C4<1>;
+L_0x2982070 .delay (20000,20000,20000) L_0x2982070/d;
+L_0x2982160/d .functor AND 1, L_0x2980990, L_0x2982420, C4<1>, C4<1>;
+L_0x2982160 .delay (20000,20000,20000) L_0x2982160/d;
+L_0x2982250/d .functor OR 1, L_0x2982070, L_0x2982160, C4<0>, C4<0>;
+L_0x2982250 .delay (20000,20000,20000) L_0x2982250/d;
+v0x2941e60_0 .net "S", 0 0, L_0x2982420; 1 drivers
+v0x2941f00_0 .alias "in0", 0 0, v0x2942590_0;
+v0x2941fa0_0 .alias "in1", 0 0, v0x2942a60_0;
+v0x2942040_0 .net "nS", 0 0, L_0x2980a60; 1 drivers
+v0x29420f0_0 .net "out0", 0 0, L_0x2982070; 1 drivers
+v0x2942190_0 .net "out1", 0 0, L_0x2982160; 1 drivers
+v0x2942270_0 .alias "outfinal", 0 0, v0x2942640_0;
+S_0x2940970 .scope generate, "addbits[27]" "addbits[27]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x2940388 .param/l "i" 3 283, +C4<011011>;
+S_0x2940ae0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2940970;
+ .timescale -9 -12;
+L_0x2981e80/d .functor NOT 1, L_0x296f660, C4<0>, C4<0>, C4<0>;
+L_0x2981e80 .delay (10000,10000,10000) L_0x2981e80/d;
+L_0x29839a0/d .functor NOT 1, L_0x2983a60, C4<0>, C4<0>, C4<0>;
+L_0x29839a0 .delay (10000,10000,10000) L_0x29839a0/d;
+L_0x2983b00/d .functor AND 1, L_0x2983c40, L_0x29839a0, C4<1>, C4<1>;
+L_0x2983b00 .delay (20000,20000,20000) L_0x2983b00/d;
+L_0x2983ce0/d .functor XOR 1, L_0x296f5c0, L_0x2983730, C4<0>, C4<0>;
+L_0x2983ce0 .delay (40000,40000,40000) L_0x2983ce0/d;
+L_0x2983dd0/d .functor XOR 1, L_0x2983ce0, L_0x2984a80, C4<0>, C4<0>;
+L_0x2983dd0 .delay (40000,40000,40000) L_0x2983dd0/d;
+L_0x2983ef0/d .functor AND 1, L_0x296f5c0, L_0x2983730, C4<1>, C4<1>;
+L_0x2983ef0 .delay (20000,20000,20000) L_0x2983ef0/d;
+L_0x2984090/d .functor AND 1, L_0x2983ce0, L_0x2984a80, C4<1>, C4<1>;
+L_0x2984090 .delay (20000,20000,20000) L_0x2984090/d;
+L_0x29841a0/d .functor OR 1, L_0x2983ef0, L_0x2984090, C4<0>, C4<0>;
+L_0x29841a0 .delay (20000,20000,20000) L_0x29841a0/d;
+v0x2941170_0 .net "A", 0 0, L_0x296f5c0; 1 drivers
+v0x2941230_0 .net "AandB", 0 0, L_0x2983ef0; 1 drivers
+v0x29412d0_0 .net "AddSubSLTSum", 0 0, L_0x2983dd0; 1 drivers
+v0x2941370_0 .net "AxorB", 0 0, L_0x2983ce0; 1 drivers
+v0x29413f0_0 .net "B", 0 0, L_0x296f660; 1 drivers
+v0x29414a0_0 .net "BornB", 0 0, L_0x2983730; 1 drivers
+v0x2941560_0 .net "CINandAxorB", 0 0, L_0x2984090; 1 drivers
+v0x29415e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2941660_0 .net *"_s3", 0 0, L_0x2983a60; 1 drivers
+v0x29416e0_0 .net *"_s5", 0 0, L_0x2983c40; 1 drivers
+v0x2941780_0 .net "carryin", 0 0, L_0x2984a80; 1 drivers
+v0x2941820_0 .net "carryout", 0 0, L_0x29841a0; 1 drivers
+v0x29418c0_0 .net "nB", 0 0, L_0x2981e80; 1 drivers
+v0x2941970_0 .net "nCmd2", 0 0, L_0x29839a0; 1 drivers
+v0x2941a70_0 .net "subtract", 0 0, L_0x2983b00; 1 drivers
+L_0x2983900 .part v0x2960210_0, 0, 1;
+L_0x2983a60 .part v0x2960210_0, 2, 1;
+L_0x2983c40 .part v0x2960210_0, 0, 1;
+S_0x2940bd0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2940ae0;
+ .timescale -9 -12;
+L_0x29834f0/d .functor NOT 1, L_0x2983900, C4<0>, C4<0>, C4<0>;
+L_0x29834f0 .delay (10000,10000,10000) L_0x29834f0/d;
+L_0x2983550/d .functor AND 1, L_0x296f660, L_0x29834f0, C4<1>, C4<1>;
+L_0x2983550 .delay (20000,20000,20000) L_0x2983550/d;
+L_0x2983640/d .functor AND 1, L_0x2981e80, L_0x2983900, C4<1>, C4<1>;
+L_0x2983640 .delay (20000,20000,20000) L_0x2983640/d;
+L_0x2983730/d .functor OR 1, L_0x2983550, L_0x2983640, C4<0>, C4<0>;
+L_0x2983730 .delay (20000,20000,20000) L_0x2983730/d;
+v0x2940cc0_0 .net "S", 0 0, L_0x2983900; 1 drivers
+v0x2940d60_0 .alias "in0", 0 0, v0x29413f0_0;
+v0x2940e00_0 .alias "in1", 0 0, v0x29418c0_0;
+v0x2940ea0_0 .net "nS", 0 0, L_0x29834f0; 1 drivers
+v0x2940f50_0 .net "out0", 0 0, L_0x2983550; 1 drivers
+v0x2940ff0_0 .net "out1", 0 0, L_0x2983640; 1 drivers
+v0x29410d0_0 .alias "outfinal", 0 0, v0x29414a0_0;
+S_0x293f7d0 .scope generate, "addbits[28]" "addbits[28]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x293f1e8 .param/l "i" 3 283, +C4<011100>;
+S_0x293f940 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293f7d0;
+ .timescale -9 -12;
+L_0x296f700/d .functor NOT 1, L_0x2984cb0, C4<0>, C4<0>, C4<0>;
+L_0x296f700 .delay (10000,10000,10000) L_0x296f700/d;
+L_0x2985130/d .functor NOT 1, L_0x29851d0, C4<0>, C4<0>, C4<0>;
+L_0x2985130 .delay (10000,10000,10000) L_0x2985130/d;
+L_0x2985270/d .functor AND 1, L_0x29853b0, L_0x2985130, C4<1>, C4<1>;
+L_0x2985270 .delay (20000,20000,20000) L_0x2985270/d;
+L_0x2985450/d .functor XOR 1, L_0x2984c10, L_0x2984860, C4<0>, C4<0>;
+L_0x2985450 .delay (40000,40000,40000) L_0x2985450/d;
+L_0x2985540/d .functor XOR 1, L_0x2985450, L_0x2984de0, C4<0>, C4<0>;
+L_0x2985540 .delay (40000,40000,40000) L_0x2985540/d;
+L_0x2985630/d .functor AND 1, L_0x2984c10, L_0x2984860, C4<1>, C4<1>;
+L_0x2985630 .delay (20000,20000,20000) L_0x2985630/d;
+L_0x29857a0/d .functor AND 1, L_0x2985450, L_0x2984de0, C4<1>, C4<1>;
+L_0x29857a0 .delay (20000,20000,20000) L_0x29857a0/d;
+L_0x2985890/d .functor OR 1, L_0x2985630, L_0x29857a0, C4<0>, C4<0>;
+L_0x2985890 .delay (20000,20000,20000) L_0x2985890/d;
+v0x293ffd0_0 .net "A", 0 0, L_0x2984c10; 1 drivers
+v0x2940090_0 .net "AandB", 0 0, L_0x2985630; 1 drivers
+v0x2940130_0 .net "AddSubSLTSum", 0 0, L_0x2985540; 1 drivers
+v0x29401d0_0 .net "AxorB", 0 0, L_0x2985450; 1 drivers
+v0x2940250_0 .net "B", 0 0, L_0x2984cb0; 1 drivers
+v0x2940300_0 .net "BornB", 0 0, L_0x2984860; 1 drivers
+v0x29403c0_0 .net "CINandAxorB", 0 0, L_0x29857a0; 1 drivers
+v0x2940440_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x29404c0_0 .net *"_s3", 0 0, L_0x29851d0; 1 drivers
+v0x2940540_0 .net *"_s5", 0 0, L_0x29853b0; 1 drivers
+v0x29405e0_0 .net "carryin", 0 0, L_0x2984de0; 1 drivers
+v0x2940680_0 .net "carryout", 0 0, L_0x2985890; 1 drivers
+v0x2940720_0 .net "nB", 0 0, L_0x296f700; 1 drivers
+v0x29407d0_0 .net "nCmd2", 0 0, L_0x2985130; 1 drivers
+v0x29408d0_0 .net "subtract", 0 0, L_0x2985270; 1 drivers
+L_0x2985090 .part v0x2960210_0, 0, 1;
+L_0x29851d0 .part v0x2960210_0, 2, 1;
+L_0x29853b0 .part v0x2960210_0, 0, 1;
+S_0x293fa30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293f940;
+ .timescale -9 -12;
+L_0x29845c0/d .functor NOT 1, L_0x2985090, C4<0>, C4<0>, C4<0>;
+L_0x29845c0 .delay (10000,10000,10000) L_0x29845c0/d;
+L_0x2984640/d .functor AND 1, L_0x2984cb0, L_0x29845c0, C4<1>, C4<1>;
+L_0x2984640 .delay (20000,20000,20000) L_0x2984640/d;
+L_0x2984750/d .functor AND 1, L_0x296f700, L_0x2985090, C4<1>, C4<1>;
+L_0x2984750 .delay (20000,20000,20000) L_0x2984750/d;
+L_0x2984860/d .functor OR 1, L_0x2984640, L_0x2984750, C4<0>, C4<0>;
+L_0x2984860 .delay (20000,20000,20000) L_0x2984860/d;
+v0x293fb20_0 .net "S", 0 0, L_0x2985090; 1 drivers
+v0x293fbc0_0 .alias "in0", 0 0, v0x2940250_0;
+v0x293fc60_0 .alias "in1", 0 0, v0x2940720_0;
+v0x293fd00_0 .net "nS", 0 0, L_0x29845c0; 1 drivers
+v0x293fdb0_0 .net "out0", 0 0, L_0x2984640; 1 drivers
+v0x293fe50_0 .net "out1", 0 0, L_0x2984750; 1 drivers
+v0x293ff30_0 .alias "outfinal", 0 0, v0x2940300_0;
+S_0x293e630 .scope generate, "addbits[29]" "addbits[29]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x293e048 .param/l "i" 3 283, +C4<011101>;
+S_0x293e7a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293e630;
+ .timescale -9 -12;
+L_0x2984e80/d .functor NOT 1, L_0x2985ca0, C4<0>, C4<0>, C4<0>;
+L_0x2984e80 .delay (10000,10000,10000) L_0x2984e80/d;
+L_0x2986550/d .functor NOT 1, L_0x2986610, C4<0>, C4<0>, C4<0>;
+L_0x2986550 .delay (10000,10000,10000) L_0x2986550/d;
+L_0x29866b0/d .functor AND 1, L_0x29867f0, L_0x2986550, C4<1>, C4<1>;
+L_0x29866b0 .delay (20000,20000,20000) L_0x29866b0/d;
+L_0x2986890/d .functor XOR 1, L_0x2985c00, L_0x2986320, C4<0>, C4<0>;
+L_0x2986890 .delay (40000,40000,40000) L_0x2986890/d;
+L_0x29869b0/d .functor XOR 1, L_0x2986890, L_0x2985dd0, C4<0>, C4<0>;
+L_0x29869b0 .delay (40000,40000,40000) L_0x29869b0/d;
+L_0x2986ad0/d .functor AND 1, L_0x2985c00, L_0x2986320, C4<1>, C4<1>;
+L_0x2986ad0 .delay (20000,20000,20000) L_0x2986ad0/d;
+L_0x2986c70/d .functor AND 1, L_0x2986890, L_0x2985dd0, C4<1>, C4<1>;
+L_0x2986c70 .delay (20000,20000,20000) L_0x2986c70/d;
+L_0x2986d60/d .functor OR 1, L_0x2986ad0, L_0x2986c70, C4<0>, C4<0>;
+L_0x2986d60 .delay (20000,20000,20000) L_0x2986d60/d;
+v0x293ee30_0 .net "A", 0 0, L_0x2985c00; 1 drivers
+v0x293eef0_0 .net "AandB", 0 0, L_0x2986ad0; 1 drivers
+v0x293ef90_0 .net "AddSubSLTSum", 0 0, L_0x29869b0; 1 drivers
+v0x293f030_0 .net "AxorB", 0 0, L_0x2986890; 1 drivers
+v0x293f0b0_0 .net "B", 0 0, L_0x2985ca0; 1 drivers
+v0x293f160_0 .net "BornB", 0 0, L_0x2986320; 1 drivers
+v0x293f220_0 .net "CINandAxorB", 0 0, L_0x2986c70; 1 drivers
+v0x293f2a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x293f320_0 .net *"_s3", 0 0, L_0x2986610; 1 drivers
+v0x293f3a0_0 .net *"_s5", 0 0, L_0x29867f0; 1 drivers
+v0x293f440_0 .net "carryin", 0 0, L_0x2985dd0; 1 drivers
+v0x293f4e0_0 .net "carryout", 0 0, L_0x2986d60; 1 drivers
+v0x293f580_0 .net "nB", 0 0, L_0x2984e80; 1 drivers
+v0x293f630_0 .net "nCmd2", 0 0, L_0x2986550; 1 drivers
+v0x293f730_0 .net "subtract", 0 0, L_0x29866b0; 1 drivers
+L_0x29864b0 .part v0x2960210_0, 0, 1;
+L_0x2986610 .part v0x2960210_0, 2, 1;
+L_0x29867f0 .part v0x2960210_0, 0, 1;
+S_0x293e890 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293e7a0;
+ .timescale -9 -12;
+L_0x2984fe0/d .functor NOT 1, L_0x29864b0, C4<0>, C4<0>, C4<0>;
+L_0x2984fe0 .delay (10000,10000,10000) L_0x2984fe0/d;
+L_0x2986140/d .functor AND 1, L_0x2985ca0, L_0x2984fe0, C4<1>, C4<1>;
+L_0x2986140 .delay (20000,20000,20000) L_0x2986140/d;
+L_0x2986230/d .functor AND 1, L_0x2984e80, L_0x29864b0, C4<1>, C4<1>;
+L_0x2986230 .delay (20000,20000,20000) L_0x2986230/d;
+L_0x2986320/d .functor OR 1, L_0x2986140, L_0x2986230, C4<0>, C4<0>;
+L_0x2986320 .delay (20000,20000,20000) L_0x2986320/d;
+v0x293e980_0 .net "S", 0 0, L_0x29864b0; 1 drivers
+v0x293ea20_0 .alias "in0", 0 0, v0x293f0b0_0;
+v0x293eac0_0 .alias "in1", 0 0, v0x293f580_0;
+v0x293eb60_0 .net "nS", 0 0, L_0x2984fe0; 1 drivers
+v0x293ec10_0 .net "out0", 0 0, L_0x2986140; 1 drivers
+v0x293ecb0_0 .net "out1", 0 0, L_0x2986230; 1 drivers
+v0x293ed90_0 .alias "outfinal", 0 0, v0x293f160_0;
+S_0x293d490 .scope generate, "addbits[30]" "addbits[30]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x293ce88 .param/l "i" 3 283, +C4<011110>;
+S_0x293d600 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293d490;
+ .timescale -9 -12;
+L_0x2985e70/d .functor NOT 1, L_0x2987500, C4<0>, C4<0>, C4<0>;
+L_0x2985e70 .delay (10000,10000,10000) L_0x2985e70/d;
+L_0x2987ca0/d .functor NOT 1, L_0x2987d40, C4<0>, C4<0>, C4<0>;
+L_0x2987ca0 .delay (10000,10000,10000) L_0x2987ca0/d;
+L_0x2987de0/d .functor AND 1, L_0x2987f20, L_0x2987ca0, C4<1>, C4<1>;
+L_0x2987de0 .delay (20000,20000,20000) L_0x2987de0/d;
+L_0x2987fc0/d .functor XOR 1, L_0x2987460, L_0x2987a70, C4<0>, C4<0>;
+L_0x2987fc0 .delay (40000,40000,40000) L_0x2987fc0/d;
+L_0x29880b0/d .functor XOR 1, L_0x2987fc0, L_0x2987630, C4<0>, C4<0>;
+L_0x29880b0 .delay (40000,40000,40000) L_0x29880b0/d;
+L_0x29881d0/d .functor AND 1, L_0x2987460, L_0x2987a70, C4<1>, C4<1>;
+L_0x29881d0 .delay (20000,20000,20000) L_0x29881d0/d;
+L_0x2988370/d .functor AND 1, L_0x2987fc0, L_0x2987630, C4<1>, C4<1>;
+L_0x2988370 .delay (20000,20000,20000) L_0x2988370/d;
+L_0x2988460/d .functor OR 1, L_0x29881d0, L_0x2988370, C4<0>, C4<0>;
+L_0x2988460 .delay (20000,20000,20000) L_0x2988460/d;
+v0x293dc90_0 .net "A", 0 0, L_0x2987460; 1 drivers
+v0x293dd50_0 .net "AandB", 0 0, L_0x29881d0; 1 drivers
+v0x293ddf0_0 .net "AddSubSLTSum", 0 0, L_0x29880b0; 1 drivers
+v0x293de90_0 .net "AxorB", 0 0, L_0x2987fc0; 1 drivers
+v0x293df10_0 .net "B", 0 0, L_0x2987500; 1 drivers
+v0x293dfc0_0 .net "BornB", 0 0, L_0x2987a70; 1 drivers
+v0x293e080_0 .net "CINandAxorB", 0 0, L_0x2988370; 1 drivers
+v0x293e100_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x293e180_0 .net *"_s3", 0 0, L_0x2987d40; 1 drivers
+v0x293e200_0 .net *"_s5", 0 0, L_0x2987f20; 1 drivers
+v0x293e2a0_0 .net "carryin", 0 0, L_0x2987630; 1 drivers
+v0x293e340_0 .net "carryout", 0 0, L_0x2988460; 1 drivers
+v0x293e3e0_0 .net "nB", 0 0, L_0x2985e70; 1 drivers
+v0x293e490_0 .net "nCmd2", 0 0, L_0x2987ca0; 1 drivers
+v0x293e590_0 .net "subtract", 0 0, L_0x2987de0; 1 drivers
+L_0x2987c00 .part v0x2960210_0, 0, 1;
+L_0x2987d40 .part v0x2960210_0, 2, 1;
+L_0x2987f20 .part v0x2960210_0, 0, 1;
+S_0x293d6f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293d600;
+ .timescale -9 -12;
+L_0x2985fd0/d .functor NOT 1, L_0x2987c00, C4<0>, C4<0>, C4<0>;
+L_0x2985fd0 .delay (10000,10000,10000) L_0x2985fd0/d;
+L_0x2986090/d .functor AND 1, L_0x2987500, L_0x2985fd0, C4<1>, C4<1>;
+L_0x2986090 .delay (20000,20000,20000) L_0x2986090/d;
+L_0x2987980/d .functor AND 1, L_0x2985e70, L_0x2987c00, C4<1>, C4<1>;
+L_0x2987980 .delay (20000,20000,20000) L_0x2987980/d;
+L_0x2987a70/d .functor OR 1, L_0x2986090, L_0x2987980, C4<0>, C4<0>;
+L_0x2987a70 .delay (20000,20000,20000) L_0x2987a70/d;
+v0x293d7e0_0 .net "S", 0 0, L_0x2987c00; 1 drivers
+v0x293d880_0 .alias "in0", 0 0, v0x293df10_0;
+v0x293d920_0 .alias "in1", 0 0, v0x293e3e0_0;
+v0x293d9c0_0 .net "nS", 0 0, L_0x2985fd0; 1 drivers
+v0x293da70_0 .net "out0", 0 0, L_0x2986090; 1 drivers
+v0x293db10_0 .net "out1", 0 0, L_0x2987980; 1 drivers
+v0x293dbf0_0 .alias "outfinal", 0 0, v0x293dfc0_0;
+S_0x293c3d0 .scope generate, "addbits[31]" "addbits[31]" 3 283, 3 283, S_0x293c2e0;
+ .timescale -9 -12;
+P_0x293c098 .param/l "i" 3 283, +C4<011111>;
+S_0x293c4c0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x293c3d0;
+ .timescale -9 -12;
+L_0x29876d0/d .functor NOT 1, L_0x2988930, C4<0>, C4<0>, C4<0>;
+L_0x29876d0 .delay (10000,10000,10000) L_0x29876d0/d;
+L_0x2989160/d .functor NOT 1, L_0x2989200, C4<0>, C4<0>, C4<0>;
+L_0x2989160 .delay (10000,10000,10000) L_0x2989160/d;
+L_0x29892a0/d .functor AND 1, L_0x29893e0, L_0x2989160, C4<1>, C4<1>;
+L_0x29892a0 .delay (20000,20000,20000) L_0x29892a0/d;
+L_0x2989480/d .functor XOR 1, L_0x2988890, L_0x2988f30, C4<0>, C4<0>;
+L_0x2989480 .delay (40000,40000,40000) L_0x2989480/d;
+L_0x29895a0/d .functor XOR 1, L_0x2989480, L_0x2988a60, C4<0>, C4<0>;
+L_0x29895a0 .delay (40000,40000,40000) L_0x29895a0/d;
+L_0x29896c0/d .functor AND 1, L_0x2988890, L_0x2988f30, C4<1>, C4<1>;
+L_0x29896c0 .delay (20000,20000,20000) L_0x29896c0/d;
+L_0x2989860/d .functor AND 1, L_0x2989480, L_0x2988a60, C4<1>, C4<1>;
+L_0x2989860 .delay (20000,20000,20000) L_0x2989860/d;
+L_0x2989950/d .functor OR 1, L_0x29896c0, L_0x2989860, C4<0>, C4<0>;
+L_0x2989950 .delay (20000,20000,20000) L_0x2989950/d;
+v0x293cb00_0 .net "A", 0 0, L_0x2988890; 1 drivers
+v0x293cbc0_0 .net "AandB", 0 0, L_0x29896c0; 1 drivers
+v0x293cc60_0 .net "AddSubSLTSum", 0 0, L_0x29895a0; 1 drivers
+v0x293cd00_0 .net "AxorB", 0 0, L_0x2989480; 1 drivers
+v0x293cd80_0 .net "B", 0 0, L_0x2988930; 1 drivers
+v0x293ce00_0 .net "BornB", 0 0, L_0x2988f30; 1 drivers
+v0x293cec0_0 .net "CINandAxorB", 0 0, L_0x2989860; 1 drivers
+v0x293cf40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x293d010_0 .net *"_s3", 0 0, L_0x2989200; 1 drivers
+v0x293d090_0 .net *"_s5", 0 0, L_0x29893e0; 1 drivers
+v0x293d130_0 .net "carryin", 0 0, L_0x2988a60; 1 drivers
+v0x293d1d0_0 .net "carryout", 0 0, L_0x2989950; 1 drivers
+v0x293d270_0 .net "nB", 0 0, L_0x29876d0; 1 drivers
+v0x293d2f0_0 .net "nCmd2", 0 0, L_0x2989160; 1 drivers
+v0x293d3f0_0 .net "subtract", 0 0, L_0x29892a0; 1 drivers
+L_0x29890c0 .part v0x2960210_0, 0, 1;
+L_0x2989200 .part v0x2960210_0, 2, 1;
+L_0x29893e0 .part v0x2960210_0, 0, 1;
+S_0x293c5b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x293c4c0;
+ .timescale -9 -12;
+L_0x2987830/d .functor NOT 1, L_0x29890c0, C4<0>, C4<0>, C4<0>;
+L_0x2987830 .delay (10000,10000,10000) L_0x2987830/d;
+L_0x2988d50/d .functor AND 1, L_0x2988930, L_0x2987830, C4<1>, C4<1>;
+L_0x2988d50 .delay (20000,20000,20000) L_0x2988d50/d;
+L_0x2988e40/d .functor AND 1, L_0x29876d0, L_0x29890c0, C4<1>, C4<1>;
+L_0x2988e40 .delay (20000,20000,20000) L_0x2988e40/d;
+L_0x2988f30/d .functor OR 1, L_0x2988d50, L_0x2988e40, C4<0>, C4<0>;
+L_0x2988f30 .delay (20000,20000,20000) L_0x2988f30/d;
+v0x293c6a0_0 .net "S", 0 0, L_0x29890c0; 1 drivers
+v0x293c720_0 .alias "in0", 0 0, v0x293cd80_0;
+v0x293c7c0_0 .alias "in1", 0 0, v0x293d270_0;
+v0x293c860_0 .net "nS", 0 0, L_0x2987830; 1 drivers
+v0x293c8e0_0 .net "out0", 0 0, L_0x2988d50; 1 drivers
+v0x293c980_0 .net "out1", 0 0, L_0x2988e40; 1 drivers
+v0x293ca60_0 .alias "outfinal", 0 0, v0x293ce00_0;
+S_0x28e1a50 .scope module, "test2" "SLT32" 2 156, 3 298, S_0x22efd20;
+ .timescale -9 -12;
+P_0x28e1b48 .param/l "size" 3 330, +C4<0100000>;
+L_0x29d14b0/d .functor NOT 1, L_0x29d15e0, C4<0>, C4<0>, C4<0>;
+L_0x29d14b0 .delay (10000,10000,10000) L_0x29d14b0/d;
+L_0x29d1680/d .functor AND 1, L_0x29d17c0, L_0x29d1860, L_0x29d14b0, C4<1>;
+L_0x29d1680 .delay (20000,20000,20000) L_0x29d1680/d;
+L_0x29d2c20/d .functor OR 1, L_0x29af990, C4<0>, C4<0>, C4<0>;
+L_0x29d2c20 .delay (20000,20000,20000) L_0x29d2c20/d;
+L_0x29d4420/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x29d0940, C4<0>, C4<0>;
+L_0x29d4420 .delay (40000,40000,40000) L_0x29d4420/d;
+L_0x29d09e0/d .functor NOT 1, RS_0x7f507e9ad718, C4<0>, C4<0>, C4<0>;
+L_0x29d09e0 .delay (10000,10000,10000) L_0x29d09e0/d;
+L_0x295fcf0/d .functor NOT 1, L_0x29afbc0, C4<0>, C4<0>, C4<0>;
+L_0x295fcf0 .delay (10000,10000,10000) L_0x295fcf0/d;
+L_0x29afc60/d .functor AND 1, L_0x29d09e0, L_0x29afe50, C4<1>, C4<1>;
+L_0x29afc60 .delay (20000,20000,20000) L_0x29afc60/d;
+L_0x29afef0/d .functor AND 1, RS_0x7f507e9ad718, L_0x295fcf0, C4<1>, C4<1>;
+L_0x29afef0 .delay (20000,20000,20000) L_0x29afef0/d;
+L_0x29b0030/d .functor AND 1, L_0x29afc60, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b0030 .delay (20000,20000,20000) L_0x29b0030/d;
+L_0x29b0150/d .functor AND 1, L_0x29afef0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b0150 .delay (20000,20000,20000) L_0x29b0150/d;
+L_0x29d5990/d .functor OR 1, L_0x29b0030, L_0x29b0150, C4<0>, C4<0>;
+L_0x29d5990 .delay (20000,20000,20000) L_0x29d5990/d;
+v0x293afc0_0 .alias "A", 31 0, v0x295f580_0;
+RS_0x7f507e96d718/0/0 .resolv tri, L_0x298dad0, L_0x298fdb0, L_0x2992010, L_0x2994200;
+RS_0x7f507e96d718/0/4 .resolv tri, L_0x29964c0, L_0x2892350, L_0x299ca40, L_0x299ed10;
+RS_0x7f507e96d718/0/8 .resolv tri, L_0x29a0ff0, L_0x29a31d0, L_0x29a53a0, L_0x29a7770;
+RS_0x7f507e96d718/0/12 .resolv tri, L_0x29a9970, L_0x29abc90, L_0x29aded0, L_0x29b02b0;
+RS_0x7f507e96d718/0/16 .resolv tri, L_0x298d400, L_0x2979420, L_0x29b7ab0, L_0x29b9c90;
+RS_0x7f507e96d718/0/20 .resolv tri, L_0x29bbe40, L_0x29be020, L_0x29befc0, L_0x29c2800;
+RS_0x7f507e96d718/0/24 .resolv tri, L_0x29c2fe0, L_0x29c4f90, L_0x29c7b30, L_0x29ca140;
+RS_0x7f507e96d718/0/28 .resolv tri, L_0x29cc140, L_0x29ce830, L_0x29d0720, L_0x29d2a00;
+RS_0x7f507e96d718/1/0 .resolv tri, RS_0x7f507e96d718/0/0, RS_0x7f507e96d718/0/4, RS_0x7f507e96d718/0/8, RS_0x7f507e96d718/0/12;
+RS_0x7f507e96d718/1/4 .resolv tri, RS_0x7f507e96d718/0/16, RS_0x7f507e96d718/0/20, RS_0x7f507e96d718/0/24, RS_0x7f507e96d718/0/28;
+RS_0x7f507e96d718 .resolv tri, RS_0x7f507e96d718/1/0, RS_0x7f507e96d718/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x293b060_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e96d718; 32 drivers
+v0x293b100_0 .alias "B", 31 0, v0x295f6a0_0;
+RS_0x7f507e96d748/0/0 .resolv tri, L_0x298ce10, L_0x298f4e0, L_0x29917f0, L_0x29928c0;
+RS_0x7f507e96d748/0/4 .resolv tri, L_0x2995c60, L_0x2996d70, L_0x299c200, L_0x299d1f0;
+RS_0x7f507e96d748/0/8 .resolv tri, L_0x29a07d0, L_0x29a17c0, L_0x29a4b90, L_0x29a5f80;
+RS_0x7f507e96d748/0/12 .resolv tri, L_0x29a9150, L_0x29aa300, L_0x29ad6a0, L_0x29ae760;
+RS_0x7f507e96d748/0/16 .resolv tri, L_0x29b1ea0, L_0x29b3560, L_0x29b7270, L_0x29b7c40;
+RS_0x7f507e96d748/0/20 .resolv tri, L_0x29bb630, L_0x29bbfd0, L_0x29bfdf0, L_0x29c07a0;
+RS_0x7f507e96d748/0/24 .resolv tri, L_0x29c41d0, L_0x29c4b90, L_0x29c8960, L_0x29c9960;
+RS_0x7f507e96d748/0/28 .resolv tri, L_0x29ccd50, L_0x29ce050, L_0x29d1320, L_0x29d39b0;
+RS_0x7f507e96d748/1/0 .resolv tri, RS_0x7f507e96d748/0/0, RS_0x7f507e96d748/0/4, RS_0x7f507e96d748/0/8, RS_0x7f507e96d748/0/12;
+RS_0x7f507e96d748/1/4 .resolv tri, RS_0x7f507e96d748/0/16, RS_0x7f507e96d748/0/20, RS_0x7f507e96d748/0/24, RS_0x7f507e96d748/0/28;
+RS_0x7f507e96d748 .resolv tri, RS_0x7f507e96d748/1/0, RS_0x7f507e96d748/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x293b180_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e96d748; 32 drivers
+v0x293b230_0 .alias "Command", 2 0, v0x295f7a0_0;
+RS_0x7f507e96d778/0/0 .resolv tri, L_0x298cd20, L_0x298f380, L_0x2991700, L_0x2993870;
+RS_0x7f507e96d778/0/4 .resolv tri, L_0x2995b70, L_0x2891a20, L_0x299c110, L_0x299e300;
+RS_0x7f507e96d778/0/8 .resolv tri, L_0x29a06e0, L_0x29a28d0, L_0x29a4aa0, L_0x29a6e70;
+RS_0x7f507e96d778/0/12 .resolv tri, L_0x29a9060, L_0x29ab390, L_0x29ad5b0, L_0x29af7b0;
+RS_0x7f507e96d778/0/16 .resolv tri, L_0x29b1db0, L_0x29b4780, L_0x29b7180, L_0x29b9360;
+RS_0x7f507e96d778/0/20 .resolv tri, L_0x29bb540, L_0x29bd720, L_0x29bfd00, L_0x29c1ef0;
+RS_0x7f507e96d778/0/24 .resolv tri, L_0x29c40e0, L_0x29c6290, L_0x29c8870, L_0x29caa60;
+RS_0x7f507e96d778/0/28 .resolv tri, L_0x29ccc60, L_0x29cf070, L_0x29d1230, L_0x29d38c0;
+RS_0x7f507e96d778/1/0 .resolv tri, RS_0x7f507e96d778/0/0, RS_0x7f507e96d778/0/4, RS_0x7f507e96d778/0/8, RS_0x7f507e96d778/0/12;
+RS_0x7f507e96d778/1/4 .resolv tri, RS_0x7f507e96d778/0/16, RS_0x7f507e96d778/0/20, RS_0x7f507e96d778/0/24, RS_0x7f507e96d778/0/28;
+RS_0x7f507e96d778 .resolv tri, RS_0x7f507e96d778/1/0, RS_0x7f507e96d778/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x293b2b0_0 .net8 "NewVal", 31 0, RS_0x7f507e96d778; 32 drivers
+v0x293b350_0 .net "Res0OF1", 0 0, L_0x29afef0; 1 drivers
+v0x293b3f0_0 .net "Res1OF0", 0 0, L_0x29afc60; 1 drivers
+v0x293b490_0 .alias "SLTSum", 31 0, v0x2960440_0;
+v0x293b560_0 .alias "SLTflag", 0 0, v0x2960640_0;
+v0x293b5e0_0 .net "SLTflag0", 0 0, L_0x29b0030; 1 drivers
+v0x293b680_0 .net "SLTflag1", 0 0, L_0x29b0150; 1 drivers
+v0x293b720_0 .net "SLTon", 0 0, L_0x29d1680; 1 drivers
+v0x293b7a0_0 .net *"_s497", 0 0, L_0x29d15e0; 1 drivers
+v0x293b8c0_0 .net *"_s499", 0 0, L_0x29d17c0; 1 drivers
+v0x293b960_0 .net *"_s501", 0 0, L_0x29d1860; 1 drivers
+v0x293b820_0 .net *"_s521", 0 0, L_0x29af990; 1 drivers
+v0x293bab0_0 .net/s *"_s522", 0 0, C4<0>; 1 drivers
+v0x293bbd0_0 .net *"_s525", 0 0, L_0x29d0940; 1 drivers
+v0x293bc50_0 .net *"_s527", 0 0, L_0x29afbc0; 1 drivers
+v0x293bb30_0 .net *"_s529", 0 0, L_0x29afe50; 1 drivers
+v0x293bd80_0 .alias "carryin", 31 0, v0x295fa50_0;
+v0x293bcd0_0 .alias "carryout", 0 0, v0x2960870_0;
+v0x293bec0_0 .net "nAddSubSLTSum", 0 0, L_0x295fcf0; 1 drivers
+v0x293be00_0 .net "nCmd2", 0 0, L_0x29d14b0; 1 drivers
+v0x293c010_0 .net "nOF", 0 0, L_0x29d09e0; 1 drivers
+v0x293bf40_0 .alias "overflow", 0 0, v0x2960980_0;
+v0x293c170_0 .alias "subtract", 31 0, v0x2960aa0_0;
+L_0x298cd20 .part/pv L_0x298c890, 1, 1, 32;
+L_0x298ce10 .part/pv L_0x298cbe0, 1, 1, 32;
+L_0x298cf00 .part/pv L_0x298c5c0, 1, 1, 32;
+L_0x298cff0 .part v0x295fe90_0, 1, 1;
+L_0x298d090 .part v0x2960190_0, 1, 1;
+L_0x298d1c0 .part RS_0x7f507e96d748, 0, 1;
+L_0x298dad0 .part/pv L_0x291ec30, 1, 1, 32;
+L_0x298db70 .part RS_0x7f507e96d778, 1, 1;
+L_0x298e080 .part/pv L_0x298df40, 1, 1, 32;
+L_0x298e1b0 .part RS_0x7f507e96d718, 1, 1;
+L_0x298e300 .part RS_0x7f507e96d718, 1, 1;
+L_0x298f380 .part/pv L_0x298eeb0, 2, 1, 32;
+L_0x298f4e0 .part/pv L_0x298f220, 2, 1, 32;
+L_0x298f5d0 .part/pv L_0x298ebe0, 2, 1, 32;
+L_0x298f740 .part v0x295fe90_0, 2, 1;
+L_0x298f7e0 .part v0x2960190_0, 2, 1;
+L_0x298f9a0 .part RS_0x7f507e96d748, 1, 1;
+L_0x298fdb0 .part/pv L_0x298fc70, 2, 1, 32;
+L_0x298ff80 .part RS_0x7f507e96d778, 2, 1;
+L_0x2990460 .part/pv L_0x2990320, 2, 1, 32;
+L_0x298fee0 .part RS_0x7f507e96d718, 2, 1;
+L_0x2990600 .part RS_0x7f507e96d718, 2, 1;
+L_0x2991700 .part/pv L_0x2991250, 3, 1, 32;
+L_0x29917f0 .part/pv L_0x29915a0, 3, 1, 32;
+L_0x29906f0 .part/pv L_0x2990f80, 3, 1, 32;
+L_0x2991a00 .part v0x295fe90_0, 3, 1;
+L_0x29918e0 .part v0x2960190_0, 3, 1;
+L_0x2991c10 .part RS_0x7f507e96d748, 2, 1;
+L_0x2992010 .part/pv L_0x2991ed0, 3, 1, 32;
+L_0x29920b0 .part RS_0x7f507e96d778, 3, 1;
+L_0x2992620 .part/pv L_0x29924e0, 3, 1, 32;
+L_0x29926c0 .part RS_0x7f507e96d718, 3, 1;
+L_0x29921a0 .part RS_0x7f507e96d718, 3, 1;
+L_0x2993870 .part/pv L_0x29933e0, 4, 1, 32;
+L_0x29928c0 .part/pv L_0x2993730, 4, 1, 32;
+L_0x2993a80 .part/pv L_0x2993110, 4, 1, 32;
+L_0x2993960 .part v0x295fe90_0, 4, 1;
+L_0x2993ca0 .part v0x2960190_0, 4, 1;
+L_0x2993b70 .part RS_0x7f507e96d748, 3, 1;
+L_0x2994200 .part/pv L_0x29940c0, 4, 1, 32;
+L_0x2993dd0 .part RS_0x7f507e96d778, 4, 1;
+L_0x29948c0 .part/pv L_0x2994780, 4, 1, 32;
+L_0x29942a0 .part RS_0x7f507e96d718, 4, 1;
+L_0x2994ac0 .part RS_0x7f507e96d718, 4, 1;
+L_0x2995b70 .part/pv L_0x29956c0, 5, 1, 32;
+L_0x2995c60 .part/pv L_0x2995a10, 5, 1, 32;
+L_0x2994b60 .part/pv L_0x29953f0, 5, 1, 32;
+L_0x2995ed0 .part v0x295fe90_0, 5, 1;
+L_0x2995d50 .part v0x2960190_0, 5, 1;
+L_0x2996100 .part RS_0x7f507e96d748, 4, 1;
+L_0x29964c0 .part/pv L_0x2996380, 5, 1, 32;
+L_0x2996560 .part RS_0x7f507e96d778, 5, 1;
+L_0x2996b20 .part/pv L_0x29969e0, 5, 1, 32;
+L_0x2996cd0 .part RS_0x7f507e96d718, 5, 1;
+L_0x2996650 .part RS_0x7f507e96d718, 5, 1;
+L_0x2891a20 .part/pv L_0x2891550, 6, 1, 32;
+L_0x2996d70 .part/pv L_0x28918a0, 6, 1, 32;
+L_0x2996e60 .part/pv L_0x29976c0, 6, 1, 32;
+L_0x2891b10 .part v0x295fe90_0, 6, 1;
+L_0x2891bb0 .part v0x2960190_0, 6, 1;
+L_0x2891f20 .part RS_0x7f507e96d748, 5, 1;
+L_0x2892350 .part/pv L_0x2892210, 6, 1, 32;
+L_0x29927b0 .part RS_0x7f507e96d778, 6, 1;
+L_0x2892a70 .part/pv L_0x2892930, 6, 1, 32;
+L_0x2892600 .part RS_0x7f507e96d718, 6, 1;
+L_0x28926f0 .part RS_0x7f507e96d718, 6, 1;
+L_0x299c110 .part/pv L_0x299bc80, 7, 1, 32;
+L_0x299c200 .part/pv L_0x299bfd0, 7, 1, 32;
+L_0x2892b10 .part/pv L_0x299b9b0, 7, 1, 32;
+L_0x2892c00 .part v0x295fe90_0, 7, 1;
+L_0x299c530 .part v0x2960190_0, 7, 1;
+L_0x299c5d0 .part RS_0x7f507e96d748, 6, 1;
+L_0x299ca40 .part/pv L_0x299c900, 7, 1, 32;
+L_0x299cae0 .part RS_0x7f507e96d778, 7, 1;
+L_0x299d060 .part/pv L_0x299cf20, 7, 1, 32;
+L_0x299d100 .part RS_0x7f507e96d718, 7, 1;
+L_0x299cbd0 .part RS_0x7f507e96d718, 7, 1;
+L_0x299e300 .part/pv L_0x299de50, 8, 1, 32;
+L_0x299d1f0 .part/pv L_0x299e1a0, 8, 1, 32;
+L_0x299d2e0 .part/pv L_0x299db80, 8, 1, 32;
+L_0x299e680 .part v0x295fe90_0, 8, 1;
+L_0x299e720 .part v0x2960190_0, 8, 1;
+L_0x299e3f0 .part RS_0x7f507e96d748, 7, 1;
+L_0x299ed10 .part/pv L_0x299e5e0, 8, 1, 32;
+L_0x299e7c0 .part RS_0x7f507e96d778, 8, 1;
+L_0x299f440 .part/pv L_0x299f300, 8, 1, 32;
+L_0x299edb0 .part RS_0x7f507e96d718, 8, 1;
+L_0x299eea0 .part RS_0x7f507e96d718, 8, 1;
+L_0x29a06e0 .part/pv L_0x29a0230, 9, 1, 32;
+L_0x29a07d0 .part/pv L_0x29a0580, 9, 1, 32;
+L_0x299f4e0 .part/pv L_0x299ff60, 9, 1, 32;
+L_0x299f5d0 .part v0x295fe90_0, 9, 1;
+L_0x299f670 .part v0x2960190_0, 9, 1;
+L_0x29a0bb0 .part RS_0x7f507e96d748, 8, 1;
+L_0x29a0ff0 .part/pv L_0x29a0b10, 9, 1, 32;
+L_0x29a1090 .part RS_0x7f507e96d778, 9, 1;
+L_0x29a1630 .part/pv L_0x29a14f0, 9, 1, 32;
+L_0x29a16d0 .part RS_0x7f507e96d718, 9, 1;
+L_0x29a1180 .part RS_0x7f507e96d718, 9, 1;
+L_0x29a28d0 .part/pv L_0x29a2420, 10, 1, 32;
+L_0x29a17c0 .part/pv L_0x29a2770, 10, 1, 32;
+L_0x29a18b0 .part/pv L_0x29a2150, 10, 1, 32;
+L_0x29a19a0 .part v0x295fe90_0, 10, 1;
+L_0x29a1a40 .part v0x2960190_0, 10, 1;
+L_0x29a29c0 .part RS_0x7f507e96d748, 9, 1;
+L_0x29a31d0 .part/pv L_0x29a30e0, 10, 1, 32;
+L_0x29a2d90 .part RS_0x7f507e96d778, 10, 1;
+L_0x29a3800 .part/pv L_0x29a36c0, 10, 1, 32;
+L_0x29a3270 .part RS_0x7f507e96d718, 10, 1;
+L_0x29a3360 .part RS_0x7f507e96d718, 10, 1;
+L_0x29a4aa0 .part/pv L_0x29a45f0, 11, 1, 32;
+L_0x29a4b90 .part/pv L_0x29a4940, 11, 1, 32;
+L_0x29a38a0 .part/pv L_0x29a4320, 11, 1, 32;
+L_0x29a3990 .part v0x295fe90_0, 11, 1;
+L_0x29a3a30 .part v0x2960190_0, 11, 1;
+L_0x29a3b60 .part RS_0x7f507e96d748, 10, 1;
+L_0x29a53a0 .part/pv L_0x29a5260, 11, 1, 32;
+L_0x29a5440 .part RS_0x7f507e96d778, 11, 1;
+L_0x29a59e0 .part/pv L_0x29a58f0, 11, 1, 32;
+L_0x29a5a80 .part RS_0x7f507e96d718, 11, 1;
+L_0x28923f0 .part RS_0x7f507e96d718, 11, 1;
+L_0x29a6e70 .part/pv L_0x29a6990, 12, 1, 32;
+L_0x29a5f80 .part/pv L_0x29a6d10, 12, 1, 32;
+L_0x29a6070 .part/pv L_0x29a66c0, 12, 1, 32;
+L_0x29a6160 .part v0x295fe90_0, 12, 1;
+L_0x29a6200 .part v0x2960190_0, 12, 1;
+L_0x29a7360 .part RS_0x7f507e96d748, 11, 1;
+L_0x29a7770 .part/pv L_0x29a7630, 12, 1, 32;
+L_0x29a6f60 .part RS_0x7f507e96d778, 12, 1;
+L_0x29a7da0 .part/pv L_0x29a7c60, 12, 1, 32;
+L_0x29a7810 .part RS_0x7f507e96d718, 12, 1;
+L_0x29a7900 .part RS_0x7f507e96d718, 12, 1;
+L_0x29a9060 .part/pv L_0x29a8b50, 13, 1, 32;
+L_0x29a9150 .part/pv L_0x29a8f00, 13, 1, 32;
+L_0x29a7e40 .part/pv L_0x29a8880, 13, 1, 32;
+L_0x29a7f30 .part v0x295fe90_0, 13, 1;
+L_0x29a7fd0 .part v0x2960190_0, 13, 1;
+L_0x29a8100 .part RS_0x7f507e96d748, 12, 1;
+L_0x29a9970 .part/pv L_0x29a9830, 13, 1, 32;
+L_0x29a9a10 .part RS_0x7f507e96d778, 13, 1;
+L_0x29aa050 .part/pv L_0x29a9610, 13, 1, 32;
+L_0x2996bc0 .part RS_0x7f507e96d718, 13, 1;
+L_0x29a9b00 .part RS_0x7f507e96d718, 13, 1;
+L_0x29ab390 .part/pv L_0x29aae80, 14, 1, 32;
+L_0x29aa300 .part/pv L_0x29ab230, 14, 1, 32;
+L_0x29aa3f0 .part/pv L_0x29aab80, 14, 1, 32;
+L_0x29aa4e0 .part v0x295fe90_0, 14, 1;
+L_0x29aa580 .part v0x2960190_0, 14, 1;
+L_0x29aa6b0 .part RS_0x7f507e96d748, 13, 1;
+L_0x29abc90 .part/pv L_0x29abb20, 14, 1, 32;
+L_0x29ab480 .part RS_0x7f507e96d778, 14, 1;
+L_0x29ac2e0 .part/pv L_0x29ac1f0, 14, 1, 32;
+L_0x29abd30 .part RS_0x7f507e96d718, 14, 1;
+L_0x29abe20 .part RS_0x7f507e96d718, 14, 1;
+L_0x29ad5b0 .part/pv L_0x29ad0a0, 15, 1, 32;
+L_0x29ad6a0 .part/pv L_0x29ad450, 15, 1, 32;
+L_0x29ac380 .part/pv L_0x29acdd0, 15, 1, 32;
+L_0x29ac470 .part v0x295fe90_0, 15, 1;
+L_0x29ac510 .part v0x2960190_0, 15, 1;
+L_0x29ac640 .part RS_0x7f507e96d748, 14, 1;
+L_0x29aded0 .part/pv L_0x29add90, 15, 1, 32;
+L_0x29adf70 .part RS_0x7f507e96d778, 15, 1;
+L_0x29ae5d0 .part/pv L_0x29adb70, 15, 1, 32;
+L_0x29ae670 .part RS_0x7f507e96d718, 15, 1;
+L_0x29ae060 .part RS_0x7f507e96d718, 15, 1;
+L_0x29af7b0 .part/pv L_0x29af2d0, 16, 1, 32;
+L_0x29ae760 .part/pv L_0x29af650, 16, 1, 32;
+L_0x29ae850 .part/pv L_0x29af000, 16, 1, 32;
+L_0x29ae940 .part v0x295fe90_0, 16, 1;
+L_0x29ae9e0 .part v0x2960190_0, 16, 1;
+L_0x29aeb10 .part RS_0x7f507e96d748, 15, 1;
+L_0x29b02b0 .part/pv L_0x299ebd0, 16, 1, 32;
+L_0x29af8a0 .part RS_0x7f507e96d778, 16, 1;
+L_0x29b0af0 .part/pv L_0x29b09b0, 16, 1, 32;
+L_0x29b0350 .part RS_0x7f507e96d718, 16, 1;
+L_0x29b0440 .part RS_0x7f507e96d718, 16, 1;
+L_0x29b1db0 .part/pv L_0x29b18a0, 17, 1, 32;
+L_0x29b1ea0 .part/pv L_0x29b1c50, 17, 1, 32;
+L_0x29b0b90 .part/pv L_0x29b15d0, 17, 1, 32;
+L_0x29b0c80 .part v0x295fe90_0, 17, 1;
+L_0x29b0d20 .part v0x2960190_0, 17, 1;
+L_0x29b0e50 .part RS_0x7f507e96d748, 16, 1;
+L_0x298d400 .part/pv L_0x298d2c0, 17, 1, 32;
+L_0x298d4a0 .part RS_0x7f507e96d778, 17, 1;
+L_0x29b1f90 .part/pv L_0x298d9a0, 17, 1, 32;
+L_0x29b2030 .part RS_0x7f507e96d718, 17, 1;
+L_0x29b2120 .part RS_0x7f507e96d718, 17, 1;
+L_0x29b4780 .part/pv L_0x29b42d0, 18, 1, 32;
+L_0x29b3560 .part/pv L_0x29b4620, 18, 1, 32;
+L_0x29b3650 .part/pv L_0x29b4000, 18, 1, 32;
+L_0x29b3740 .part v0x295fe90_0, 18, 1;
+L_0x29b37e0 .part v0x2960190_0, 18, 1;
+L_0x29b3910 .part RS_0x7f507e96d748, 17, 1;
+L_0x2979420 .part/pv L_0x29792e0, 18, 1, 32;
+L_0x29794c0 .part RS_0x7f507e96d778, 18, 1;
+L_0x29b48c0 .part/pv L_0x2978d90, 18, 1, 32;
+L_0x29b4960 .part RS_0x7f507e96d718, 18, 1;
+L_0x29b4a50 .part RS_0x7f507e96d718, 18, 1;
+L_0x29b7180 .part/pv L_0x29b6cd0, 19, 1, 32;
+L_0x29b7270 .part/pv L_0x29b7020, 19, 1, 32;
+L_0x29b5e90 .part/pv L_0x29b6a00, 19, 1, 32;
+L_0x29b5f80 .part v0x295fe90_0, 19, 1;
+L_0x29b6020 .part v0x2960190_0, 19, 1;
+L_0x29b6150 .part RS_0x7f507e96d748, 18, 1;
+L_0x29b7ab0 .part/pv L_0x29b6440, 19, 1, 32;
+L_0x29b7b50 .part RS_0x7f507e96d778, 19, 1;
+L_0x298d620 .part/pv L_0x29b7760, 19, 1, 32;
+L_0x29b78a0 .part RS_0x7f507e96d718, 19, 1;
+L_0x29b82d0 .part RS_0x7f507e96d718, 19, 1;
+L_0x29b9360 .part/pv L_0x29b8eb0, 20, 1, 32;
+L_0x29b7c40 .part/pv L_0x29b9200, 20, 1, 32;
+L_0x29b7d30 .part/pv L_0x29b8be0, 20, 1, 32;
+L_0x29b7e20 .part v0x295fe90_0, 20, 1;
+L_0x29b7ec0 .part v0x2960190_0, 20, 1;
+L_0x29b7ff0 .part RS_0x7f507e96d748, 19, 1;
+L_0x29b9c90 .part/pv L_0x29b9b50, 20, 1, 32;
+L_0x29b9450 .part RS_0x7f507e96d778, 20, 1;
+L_0x29b99d0 .part/pv L_0x29b9890, 20, 1, 32;
+L_0x29b9a70 .part RS_0x7f507e96d718, 20, 1;
+L_0x29ba460 .part RS_0x7f507e96d718, 20, 1;
+L_0x29bb540 .part/pv L_0x29bb090, 21, 1, 32;
+L_0x29bb630 .part/pv L_0x29bb3e0, 21, 1, 32;
+L_0x29ba550 .part/pv L_0x29badc0, 21, 1, 32;
+L_0x29ba640 .part v0x295fe90_0, 21, 1;
+L_0x29ba6e0 .part v0x2960190_0, 21, 1;
+L_0x29ba810 .part RS_0x7f507e96d748, 20, 1;
+L_0x29bbe40 .part/pv L_0x29bab00, 21, 1, 32;
+L_0x29bbee0 .part RS_0x7f507e96d778, 21, 1;
+L_0x29bbc70 .part/pv L_0x29bbb30, 21, 1, 32;
+L_0x29bbd10 .part RS_0x7f507e96d718, 21, 1;
+L_0x29b73f0 .part RS_0x7f507e96d718, 21, 1;
+L_0x29bd720 .part/pv L_0x29bd270, 22, 1, 32;
+L_0x29bbfd0 .part/pv L_0x29bd5c0, 22, 1, 32;
+L_0x29bc0c0 .part/pv L_0x29bcfa0, 22, 1, 32;
+L_0x29bc1b0 .part v0x295fe90_0, 22, 1;
+L_0x29bc250 .part v0x2960190_0, 22, 1;
+L_0x29bc380 .part RS_0x7f507e96d748, 21, 1;
+L_0x29be020 .part/pv L_0x29bc670, 22, 1, 32;
+L_0x29a5b70 .part RS_0x7f507e96d778, 22, 1;
+L_0x29bd990 .part/pv L_0x29bd850, 22, 1, 32;
+L_0x29bda30 .part RS_0x7f507e96d718, 22, 1;
+L_0x29bdb20 .part RS_0x7f507e96d718, 22, 1;
+L_0x29bfd00 .part/pv L_0x29bf850, 23, 1, 32;
+L_0x29bfdf0 .part/pv L_0x29bfba0, 23, 1, 32;
+L_0x29be8d0 .part/pv L_0x29bf580, 23, 1, 32;
+L_0x29be9c0 .part v0x295fe90_0, 23, 1;
+L_0x29bea60 .part v0x2960190_0, 23, 1;
+L_0x29beb90 .part RS_0x7f507e96d748, 22, 1;
+L_0x29befc0 .part/pv L_0x29bee80, 23, 1, 32;
+L_0x29c06b0 .part RS_0x7f507e96d778, 23, 1;
+L_0x29c0440 .part/pv L_0x29c0300, 23, 1, 32;
+L_0x29c04e0 .part RS_0x7f507e96d718, 23, 1;
+L_0x29c05d0 .part RS_0x7f507e96d718, 23, 1;
+L_0x29c1ef0 .part/pv L_0x29c1a40, 24, 1, 32;
+L_0x29c07a0 .part/pv L_0x29c1d90, 24, 1, 32;
+L_0x29c0890 .part/pv L_0x29c1770, 24, 1, 32;
+L_0x29c0980 .part v0x295fe90_0, 24, 1;
+L_0x29c0a20 .part v0x2960190_0, 24, 1;
+L_0x29c0b50 .part RS_0x7f507e96d748, 23, 1;
+L_0x29c2800 .part/pv L_0x29c0e40, 24, 1, 32;
+L_0x29c1fe0 .part RS_0x7f507e96d778, 24, 1;
+L_0x29c2500 .part/pv L_0x29c23c0, 24, 1, 32;
+L_0x29c25a0 .part RS_0x7f507e96d718, 24, 1;
+L_0x29c2690 .part RS_0x7f507e96d718, 24, 1;
+L_0x29c40e0 .part/pv L_0x29c3c10, 25, 1, 32;
+L_0x29c41d0 .part/pv L_0x29c3f80, 25, 1, 32;
+L_0x29c28f0 .part/pv L_0x29c3940, 25, 1, 32;
+L_0x29c29e0 .part v0x295fe90_0, 25, 1;
+L_0x29c2a80 .part v0x2960190_0, 25, 1;
+L_0x29c2bb0 .part RS_0x7f507e96d748, 24, 1;
+L_0x29c2fe0 .part/pv L_0x29c2ea0, 25, 1, 32;
+L_0x29c3080 .part RS_0x7f507e96d778, 25, 1;
+L_0x29c4810 .part/pv L_0x29c46d0, 25, 1, 32;
+L_0x29c48b0 .part RS_0x7f507e96d718, 25, 1;
+L_0x29c49a0 .part RS_0x7f507e96d718, 25, 1;
+L_0x29c6290 .part/pv L_0x29c5de0, 26, 1, 32;
+L_0x29c4b90 .part/pv L_0x29c6130, 26, 1, 32;
+L_0x29c4c80 .part/pv L_0x29c5b10, 26, 1, 32;
+L_0x29830f0 .part v0x295fe90_0, 26, 1;
+L_0x2983190 .part v0x2960190_0, 26, 1;
+L_0x29832c0 .part RS_0x7f507e96d748, 25, 1;
+L_0x29c4f90 .part/pv L_0x29c4e50, 26, 1, 32;
+L_0x29c5030 .part RS_0x7f507e96d778, 26, 1;
+L_0x29c6500 .part/pv L_0x29c63c0, 26, 1, 32;
+L_0x29c65a0 .part RS_0x7f507e96d718, 26, 1;
+L_0x29c6690 .part RS_0x7f507e96d718, 26, 1;
+L_0x29c8870 .part/pv L_0x29c83c0, 27, 1, 32;
+L_0x29c8960 .part/pv L_0x29c8710, 27, 1, 32;
+L_0x29c7440 .part/pv L_0x29c80f0, 27, 1, 32;
+L_0x29c7530 .part v0x295fe90_0, 27, 1;
+L_0x29c75d0 .part v0x2960190_0, 27, 1;
+L_0x29c7700 .part RS_0x7f507e96d748, 26, 1;
+L_0x29c7b30 .part/pv L_0x29c79f0, 27, 1, 32;
+L_0x29c7bd0 .part RS_0x7f507e96d778, 27, 1;
+L_0x29c97d0 .part/pv L_0x29c9660, 27, 1, 32;
+L_0x29c9870 .part RS_0x7f507e96d718, 27, 1;
+L_0x29c8a50 .part RS_0x7f507e96d718, 27, 1;
+L_0x29caa60 .part/pv L_0x29ca5d0, 28, 1, 32;
+L_0x29c9960 .part/pv L_0x29ca920, 28, 1, 32;
+L_0x29c9a50 .part/pv L_0x29ca350, 28, 1, 32;
+L_0x29c9b40 .part v0x295fe90_0, 28, 1;
+L_0x29c9be0 .part v0x2960190_0, 28, 1;
+L_0x29c9d10 .part RS_0x7f507e96d748, 27, 1;
+L_0x29ca140 .part/pv L_0x29ca000, 28, 1, 32;
+L_0x29ca1e0 .part RS_0x7f507e96d778, 28, 1;
+L_0x29cb9b0 .part/pv L_0x29cb840, 28, 1, 32;
+L_0x29cab50 .part RS_0x7f507e96d718, 28, 1;
+L_0x29cac40 .part RS_0x7f507e96d718, 28, 1;
+L_0x29ccc60 .part/pv L_0x29cc7b0, 29, 1, 32;
+L_0x29ccd50 .part/pv L_0x29ccb00, 29, 1, 32;
+L_0x29cba50 .part/pv L_0x29cc4e0, 29, 1, 32;
+L_0x29cbb40 .part v0x295fe90_0, 29, 1;
+L_0x29cbbe0 .part v0x2960190_0, 29, 1;
+L_0x29cbd10 .part RS_0x7f507e96d748, 28, 1;
+L_0x29cc140 .part/pv L_0x29cc000, 29, 1, 32;
+L_0x29cc1e0 .part RS_0x7f507e96d778, 29, 1;
+L_0x29cdba0 .part/pv L_0x29cda60, 29, 1, 32;
+L_0x29aa0f0 .part RS_0x7f507e96d718, 29, 1;
+L_0x29aa1e0 .part RS_0x7f507e96d718, 29, 1;
+L_0x29cf070 .part/pv L_0x29cebe0, 30, 1, 32;
+L_0x29ce050 .part/pv L_0x29cef30, 30, 1, 32;
+L_0x29ce140 .part/pv L_0x29cd6c0, 30, 1, 32;
+L_0x29ce230 .part v0x295fe90_0, 30, 1;
+L_0x29ce2d0 .part v0x2960190_0, 30, 1;
+L_0x29ce400 .part RS_0x7f507e96d748, 29, 1;
+L_0x29ce830 .part/pv L_0x29ce6f0, 30, 1, 32;
+L_0x29ce8d0 .part RS_0x7f507e96d778, 30, 1;
+L_0x29cff90 .part/pv L_0x29cfe20, 30, 1, 32;
+L_0x29cf160 .part RS_0x7f507e96d718, 30, 1;
+L_0x29cf250 .part RS_0x7f507e96d718, 30, 1;
+L_0x29d1230 .part/pv L_0x29d0da0, 31, 1, 32;
+L_0x29d1320 .part/pv L_0x29d10f0, 31, 1, 32;
+L_0x29d0030 .part/pv L_0x29cfb40, 31, 1, 32;
+L_0x29d0120 .part v0x295fe90_0, 31, 1;
+L_0x29d01c0 .part v0x2960190_0, 31, 1;
+L_0x29d02f0 .part RS_0x7f507e96d748, 30, 1;
+L_0x29d0720 .part/pv L_0x29d05e0, 31, 1, 32;
+L_0x29d07c0 .part RS_0x7f507e96d778, 31, 1;
+L_0x29d2180 .part/pv L_0x29d2040, 31, 1, 32;
+L_0x29d2220 .part RS_0x7f507e96d718, 31, 1;
+L_0x29d1410 .part RS_0x7f507e96d718, 31, 1;
+L_0x29d15e0 .part v0x2960210_0, 2, 1;
+L_0x29d17c0 .part v0x2960210_0, 0, 1;
+L_0x29d1860 .part v0x2960210_0, 1, 1;
+L_0x29d38c0 .part/pv L_0x29d33e0, 0, 1, 32;
+L_0x29d39b0 .part/pv L_0x29d3760, 0, 1, 32;
+L_0x29d2310 .part/pv L_0x29d3110, 0, 1, 32;
+L_0x29d2400 .part v0x295fe90_0, 0, 1;
+L_0x29d24a0 .part v0x2960190_0, 0, 1;
+L_0x29d25d0 .part RS_0x7f507e9ad748, 0, 1;
+L_0x29d2a00 .part/pv L_0x29d28c0, 0, 1, 32;
+L_0x29d2aa0 .part RS_0x7f507e96d778, 0, 1;
+L_0x29af990 .part RS_0x7f507e96d748, 31, 1;
+L_0x29d0940 .part RS_0x7f507e96d748, 30, 1;
+L_0x29afbc0 .part RS_0x7f507e96d718, 31, 1;
+L_0x29afe50 .part RS_0x7f507e96d778, 31, 1;
+L_0x29d5e90 .part/pv L_0x29d5d30, 0, 1, 32;
+L_0x29d5f30 .part RS_0x7f507e96d718, 0, 1;
+S_0x2939fa0 .scope module, "attempt2" "MiddleAddSubSLT" 3 326, 3 189, S_0x28e1a50;
+ .timescale -9 -12;
+L_0x29d1950/d .functor NOT 1, L_0x29d24a0, C4<0>, C4<0>, C4<0>;
+L_0x29d1950 .delay (10000,10000,10000) L_0x29d1950/d;
+L_0x29d2fb0/d .functor NOT 1, L_0x29d3070, C4<0>, C4<0>, C4<0>;
+L_0x29d2fb0 .delay (10000,10000,10000) L_0x29d2fb0/d;
+L_0x29d3110/d .functor AND 1, L_0x29d3250, L_0x29d2fb0, C4<1>, C4<1>;
+L_0x29d3110 .delay (20000,20000,20000) L_0x29d3110/d;
+L_0x29d32f0/d .functor XOR 1, L_0x29d2400, L_0x29d1e00, C4<0>, C4<0>;
+L_0x29d32f0 .delay (40000,40000,40000) L_0x29d32f0/d;
+L_0x29d33e0/d .functor XOR 1, L_0x29d32f0, L_0x29d25d0, C4<0>, C4<0>;
+L_0x29d33e0 .delay (40000,40000,40000) L_0x29d33e0/d;
+L_0x29d34d0/d .functor AND 1, L_0x29d2400, L_0x29d1e00, C4<1>, C4<1>;
+L_0x29d34d0 .delay (20000,20000,20000) L_0x29d34d0/d;
+L_0x29d3670/d .functor AND 1, L_0x29d32f0, L_0x29d25d0, C4<1>, C4<1>;
+L_0x29d3670 .delay (20000,20000,20000) L_0x29d3670/d;
+L_0x29d3760/d .functor OR 1, L_0x29d34d0, L_0x29d3670, C4<0>, C4<0>;
+L_0x29d3760 .delay (20000,20000,20000) L_0x29d3760/d;
+v0x293a620_0 .net "A", 0 0, L_0x29d2400; 1 drivers
+v0x293a6e0_0 .net "AandB", 0 0, L_0x29d34d0; 1 drivers
+v0x293a780_0 .net "AddSubSLTSum", 0 0, L_0x29d33e0; 1 drivers
+v0x293a820_0 .net "AxorB", 0 0, L_0x29d32f0; 1 drivers
+v0x293a8a0_0 .net "B", 0 0, L_0x29d24a0; 1 drivers
+v0x293a950_0 .net "BornB", 0 0, L_0x29d1e00; 1 drivers
+v0x293aa10_0 .net "CINandAxorB", 0 0, L_0x29d3670; 1 drivers
+v0x293aa90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x293ab10_0 .net *"_s3", 0 0, L_0x29d3070; 1 drivers
+v0x293ab90_0 .net *"_s5", 0 0, L_0x29d3250; 1 drivers
+v0x293ac30_0 .net "carryin", 0 0, L_0x29d25d0; 1 drivers
+v0x293acd0_0 .net "carryout", 0 0, L_0x29d3760; 1 drivers
+v0x293ad70_0 .net "nB", 0 0, L_0x29d1950; 1 drivers
+v0x293ae20_0 .net "nCmd2", 0 0, L_0x29d2fb0; 1 drivers
+v0x293af20_0 .net "subtract", 0 0, L_0x29d3110; 1 drivers
+L_0x29d2f10 .part v0x2960210_0, 0, 1;
+L_0x29d3070 .part v0x2960210_0, 2, 1;
+L_0x29d3250 .part v0x2960210_0, 0, 1;
+S_0x293a090 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2939fa0;
+ .timescale -9 -12;
+L_0x29d1b20/d .functor NOT 1, L_0x29d2f10, C4<0>, C4<0>, C4<0>;
+L_0x29d1b20 .delay (10000,10000,10000) L_0x29d1b20/d;
+L_0x29d1be0/d .functor AND 1, L_0x29d24a0, L_0x29d1b20, C4<1>, C4<1>;
+L_0x29d1be0 .delay (20000,20000,20000) L_0x29d1be0/d;
+L_0x29d1cf0/d .functor AND 1, L_0x29d1950, L_0x29d2f10, C4<1>, C4<1>;
+L_0x29d1cf0 .delay (20000,20000,20000) L_0x29d1cf0/d;
+L_0x29d1e00/d .functor OR 1, L_0x29d1be0, L_0x29d1cf0, C4<0>, C4<0>;
+L_0x29d1e00 .delay (20000,20000,20000) L_0x29d1e00/d;
+v0x293a180_0 .net "S", 0 0, L_0x29d2f10; 1 drivers
+v0x293a240_0 .alias "in0", 0 0, v0x293a8a0_0;
+v0x293a2e0_0 .alias "in1", 0 0, v0x293ad70_0;
+v0x293a380_0 .net "nS", 0 0, L_0x29d1b20; 1 drivers
+v0x293a400_0 .net "out0", 0 0, L_0x29d1be0; 1 drivers
+v0x293a4a0_0 .net "out1", 0 0, L_0x29d1cf0; 1 drivers
+v0x293a580_0 .alias "outfinal", 0 0, v0x293a950_0;
+S_0x2939a30 .scope module, "setSLTresult" "TwoInMux" 3 327, 3 109, S_0x28e1a50;
+ .timescale -9 -12;
+L_0x29d2670/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29d2670 .delay (10000,10000,10000) L_0x29d2670/d;
+L_0x29d2710/d .functor AND 1, L_0x29d2aa0, L_0x29d2670, C4<1>, C4<1>;
+L_0x29d2710 .delay (20000,20000,20000) L_0x29d2710/d;
+L_0x29d2820/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29d2820 .delay (20000,20000,20000) L_0x29d2820/d;
+L_0x29d28c0/d .functor OR 1, L_0x29d2710, L_0x29d2820, C4<0>, C4<0>;
+L_0x29d28c0 .delay (20000,20000,20000) L_0x29d28c0/d;
+v0x2939b20_0 .alias "S", 0 0, v0x293b720_0;
+v0x2939bc0_0 .net "in0", 0 0, L_0x29d2aa0; 1 drivers
+v0x2939c60_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2939d00_0 .net "nS", 0 0, L_0x29d2670; 1 drivers
+v0x2939d80_0 .net "out0", 0 0, L_0x29d2710; 1 drivers
+v0x2939e20_0 .net "out1", 0 0, L_0x29d2820; 1 drivers
+v0x2939f00_0 .net "outfinal", 0 0, L_0x29d28c0; 1 drivers
+S_0x29394c0 .scope module, "FinalSLT" "TwoInMux" 3 354, 3 109, S_0x28e1a50;
+ .timescale -9 -12;
+L_0x29d5ac0/d .functor NOT 1, L_0x29d5990, C4<0>, C4<0>, C4<0>;
+L_0x29d5ac0 .delay (10000,10000,10000) L_0x29d5ac0/d;
+L_0x29d5b80/d .functor AND 1, L_0x29d5f30, L_0x29d5ac0, C4<1>, C4<1>;
+L_0x29d5b80 .delay (20000,20000,20000) L_0x29d5b80/d;
+L_0x29d5c90/d .functor AND 1, L_0x29d5990, L_0x29d5990, C4<1>, C4<1>;
+L_0x29d5c90 .delay (20000,20000,20000) L_0x29d5c90/d;
+L_0x29d5d30/d .functor OR 1, L_0x29d5b80, L_0x29d5c90, C4<0>, C4<0>;
+L_0x29d5d30 .delay (20000,20000,20000) L_0x29d5d30/d;
+v0x29395b0_0 .alias "S", 0 0, v0x2960640_0;
+v0x2939670_0 .net "in0", 0 0, L_0x29d5f30; 1 drivers
+v0x2939710_0 .alias "in1", 0 0, v0x2960640_0;
+v0x29397c0_0 .net "nS", 0 0, L_0x29d5ac0; 1 drivers
+v0x2939870_0 .net "out0", 0 0, L_0x29d5b80; 1 drivers
+v0x29398f0_0 .net "out1", 0 0, L_0x29d5c90; 1 drivers
+v0x2939990_0 .net "outfinal", 0 0, L_0x29d5d30; 1 drivers
+S_0x2937840 .scope generate, "sltbits[1]" "sltbits[1]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2937258 .param/l "i" 3 332, +C4<01>;
+S_0x29384a0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2937840;
+ .timescale -9 -12;
+L_0x29760d0/d .functor NOT 1, L_0x298d090, C4<0>, C4<0>, C4<0>;
+L_0x29760d0 .delay (10000,10000,10000) L_0x29760d0/d;
+L_0x298b610/d .functor NOT 1, L_0x298b6d0, C4<0>, C4<0>, C4<0>;
+L_0x298b610 .delay (10000,10000,10000) L_0x298b610/d;
+L_0x298c5c0/d .functor AND 1, L_0x298c700, L_0x298b610, C4<1>, C4<1>;
+L_0x298c5c0 .delay (20000,20000,20000) L_0x298c5c0/d;
+L_0x298c7a0/d .functor XOR 1, L_0x298cff0, L_0x298b3a0, C4<0>, C4<0>;
+L_0x298c7a0 .delay (40000,40000,40000) L_0x298c7a0/d;
+L_0x298c890/d .functor XOR 1, L_0x298c7a0, L_0x298d1c0, C4<0>, C4<0>;
+L_0x298c890 .delay (40000,40000,40000) L_0x298c890/d;
+L_0x298c980/d .functor AND 1, L_0x298cff0, L_0x298b3a0, C4<1>, C4<1>;
+L_0x298c980 .delay (20000,20000,20000) L_0x298c980/d;
+L_0x298caf0/d .functor AND 1, L_0x298c7a0, L_0x298d1c0, C4<1>, C4<1>;
+L_0x298caf0 .delay (20000,20000,20000) L_0x298caf0/d;
+L_0x298cbe0/d .functor OR 1, L_0x298c980, L_0x298caf0, C4<0>, C4<0>;
+L_0x298cbe0 .delay (20000,20000,20000) L_0x298cbe0/d;
+v0x2938b20_0 .net "A", 0 0, L_0x298cff0; 1 drivers
+v0x2938be0_0 .net "AandB", 0 0, L_0x298c980; 1 drivers
+v0x2938c80_0 .net "AddSubSLTSum", 0 0, L_0x298c890; 1 drivers
+v0x2938d20_0 .net "AxorB", 0 0, L_0x298c7a0; 1 drivers
+v0x2938da0_0 .net "B", 0 0, L_0x298d090; 1 drivers
+v0x2938e50_0 .net "BornB", 0 0, L_0x298b3a0; 1 drivers
+v0x2938f10_0 .net "CINandAxorB", 0 0, L_0x298caf0; 1 drivers
+v0x2938f90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2939010_0 .net *"_s3", 0 0, L_0x298b6d0; 1 drivers
+v0x2939090_0 .net *"_s5", 0 0, L_0x298c700; 1 drivers
+v0x2939130_0 .net "carryin", 0 0, L_0x298d1c0; 1 drivers
+v0x29391d0_0 .net "carryout", 0 0, L_0x298cbe0; 1 drivers
+v0x2939270_0 .net "nB", 0 0, L_0x29760d0; 1 drivers
+v0x2939320_0 .net "nCmd2", 0 0, L_0x298b610; 1 drivers
+v0x2939420_0 .net "subtract", 0 0, L_0x298c5c0; 1 drivers
+L_0x298b570 .part v0x2960210_0, 0, 1;
+L_0x298b6d0 .part v0x2960210_0, 2, 1;
+L_0x298c700 .part v0x2960210_0, 0, 1;
+S_0x2938590 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29384a0;
+ .timescale -9 -12;
+L_0x29762c0/d .functor NOT 1, L_0x298b570, C4<0>, C4<0>, C4<0>;
+L_0x29762c0 .delay (10000,10000,10000) L_0x29762c0/d;
+L_0x298b180/d .functor AND 1, L_0x298d090, L_0x29762c0, C4<1>, C4<1>;
+L_0x298b180 .delay (20000,20000,20000) L_0x298b180/d;
+L_0x298b290/d .functor AND 1, L_0x29760d0, L_0x298b570, C4<1>, C4<1>;
+L_0x298b290 .delay (20000,20000,20000) L_0x298b290/d;
+L_0x298b3a0/d .functor OR 1, L_0x298b180, L_0x298b290, C4<0>, C4<0>;
+L_0x298b3a0 .delay (20000,20000,20000) L_0x298b3a0/d;
+v0x2938680_0 .net "S", 0 0, L_0x298b570; 1 drivers
+v0x2938740_0 .alias "in0", 0 0, v0x2938da0_0;
+v0x29387e0_0 .alias "in1", 0 0, v0x2939270_0;
+v0x2938880_0 .net "nS", 0 0, L_0x29762c0; 1 drivers
+v0x2938900_0 .net "out0", 0 0, L_0x298b180; 1 drivers
+v0x29389a0_0 .net "out1", 0 0, L_0x298b290; 1 drivers
+v0x2938a80_0 .alias "outfinal", 0 0, v0x2938e50_0;
+S_0x2937f30 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2937840;
+ .timescale -9 -12;
+L_0x298d260/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x298d260 .delay (10000,10000,10000) L_0x298d260/d;
+L_0x291ea80/d .functor AND 1, L_0x298db70, L_0x298d260, C4<1>, C4<1>;
+L_0x291ea80 .delay (20000,20000,20000) L_0x291ea80/d;
+L_0x291eb90/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x291eb90 .delay (20000,20000,20000) L_0x291eb90/d;
+L_0x291ec30/d .functor OR 1, L_0x291ea80, L_0x291eb90, C4<0>, C4<0>;
+L_0x291ec30 .delay (20000,20000,20000) L_0x291ec30/d;
+v0x2938020_0 .alias "S", 0 0, v0x293b720_0;
+v0x29380c0_0 .net "in0", 0 0, L_0x298db70; 1 drivers
+v0x2938160_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2938200_0 .net "nS", 0 0, L_0x298d260; 1 drivers
+v0x2938280_0 .net "out0", 0 0, L_0x291ea80; 1 drivers
+v0x2938320_0 .net "out1", 0 0, L_0x291eb90; 1 drivers
+v0x2938400_0 .net "outfinal", 0 0, L_0x291ec30; 1 drivers
+S_0x29379b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2937840;
+ .timescale -9 -12;
+L_0x298dd00/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x298dd00 .delay (10000,10000,10000) L_0x298dd00/d;
+L_0x298ddb0/d .functor AND 1, L_0x298e1b0, L_0x298dd00, C4<1>, C4<1>;
+L_0x298ddb0 .delay (20000,20000,20000) L_0x298ddb0/d;
+L_0x298dea0/d .functor AND 1, L_0x298e300, L_0x29d1680, C4<1>, C4<1>;
+L_0x298dea0 .delay (20000,20000,20000) L_0x298dea0/d;
+L_0x298df40/d .functor OR 1, L_0x298ddb0, L_0x298dea0, C4<0>, C4<0>;
+L_0x298df40 .delay (20000,20000,20000) L_0x298df40/d;
+v0x2937aa0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2937b20_0 .net "in0", 0 0, L_0x298e1b0; 1 drivers
+v0x2937bc0_0 .net "in1", 0 0, L_0x298e300; 1 drivers
+v0x2937c60_0 .net "nS", 0 0, L_0x298dd00; 1 drivers
+v0x2937d10_0 .net "out0", 0 0, L_0x298ddb0; 1 drivers
+v0x2937db0_0 .net "out1", 0 0, L_0x298dea0; 1 drivers
+v0x2937e90_0 .net "outfinal", 0 0, L_0x298df40; 1 drivers
+S_0x2935bc0 .scope generate, "sltbits[2]" "sltbits[2]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x29355d8 .param/l "i" 3 332, +C4<010>;
+S_0x2936820 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2935bc0;
+ .timescale -9 -12;
+L_0x298e3a0/d .functor NOT 1, L_0x298f7e0, C4<0>, C4<0>, C4<0>;
+L_0x298e3a0 .delay (10000,10000,10000) L_0x298e3a0/d;
+L_0x298ea80/d .functor NOT 1, L_0x298eb40, C4<0>, C4<0>, C4<0>;
+L_0x298ea80 .delay (10000,10000,10000) L_0x298ea80/d;
+L_0x298ebe0/d .functor AND 1, L_0x298ed20, L_0x298ea80, C4<1>, C4<1>;
+L_0x298ebe0 .delay (20000,20000,20000) L_0x298ebe0/d;
+L_0x298edc0/d .functor XOR 1, L_0x298f740, L_0x298e810, C4<0>, C4<0>;
+L_0x298edc0 .delay (40000,40000,40000) L_0x298edc0/d;
+L_0x298eeb0/d .functor XOR 1, L_0x298edc0, L_0x298f9a0, C4<0>, C4<0>;
+L_0x298eeb0 .delay (40000,40000,40000) L_0x298eeb0/d;
+L_0x298efa0/d .functor AND 1, L_0x298f740, L_0x298e810, C4<1>, C4<1>;
+L_0x298efa0 .delay (20000,20000,20000) L_0x298efa0/d;
+L_0x298f110/d .functor AND 1, L_0x298edc0, L_0x298f9a0, C4<1>, C4<1>;
+L_0x298f110 .delay (20000,20000,20000) L_0x298f110/d;
+L_0x298f220/d .functor OR 1, L_0x298efa0, L_0x298f110, C4<0>, C4<0>;
+L_0x298f220 .delay (20000,20000,20000) L_0x298f220/d;
+v0x2936ea0_0 .net "A", 0 0, L_0x298f740; 1 drivers
+v0x2936f60_0 .net "AandB", 0 0, L_0x298efa0; 1 drivers
+v0x2937000_0 .net "AddSubSLTSum", 0 0, L_0x298eeb0; 1 drivers
+v0x29370a0_0 .net "AxorB", 0 0, L_0x298edc0; 1 drivers
+v0x2937120_0 .net "B", 0 0, L_0x298f7e0; 1 drivers
+v0x29371d0_0 .net "BornB", 0 0, L_0x298e810; 1 drivers
+v0x2937290_0 .net "CINandAxorB", 0 0, L_0x298f110; 1 drivers
+v0x2937310_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2937390_0 .net *"_s3", 0 0, L_0x298eb40; 1 drivers
+v0x2937410_0 .net *"_s5", 0 0, L_0x298ed20; 1 drivers
+v0x29374b0_0 .net "carryin", 0 0, L_0x298f9a0; 1 drivers
+v0x2937550_0 .net "carryout", 0 0, L_0x298f220; 1 drivers
+v0x29375f0_0 .net "nB", 0 0, L_0x298e3a0; 1 drivers
+v0x29376a0_0 .net "nCmd2", 0 0, L_0x298ea80; 1 drivers
+v0x29377a0_0 .net "subtract", 0 0, L_0x298ebe0; 1 drivers
+L_0x298e9e0 .part v0x2960210_0, 0, 1;
+L_0x298eb40 .part v0x2960210_0, 2, 1;
+L_0x298ed20 .part v0x2960210_0, 0, 1;
+S_0x2936910 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2936820;
+ .timescale -9 -12;
+L_0x298e530/d .functor NOT 1, L_0x298e9e0, C4<0>, C4<0>, C4<0>;
+L_0x298e530 .delay (10000,10000,10000) L_0x298e530/d;
+L_0x298e5f0/d .functor AND 1, L_0x298f7e0, L_0x298e530, C4<1>, C4<1>;
+L_0x298e5f0 .delay (20000,20000,20000) L_0x298e5f0/d;
+L_0x298e700/d .functor AND 1, L_0x298e3a0, L_0x298e9e0, C4<1>, C4<1>;
+L_0x298e700 .delay (20000,20000,20000) L_0x298e700/d;
+L_0x298e810/d .functor OR 1, L_0x298e5f0, L_0x298e700, C4<0>, C4<0>;
+L_0x298e810 .delay (20000,20000,20000) L_0x298e810/d;
+v0x2936a00_0 .net "S", 0 0, L_0x298e9e0; 1 drivers
+v0x2936ac0_0 .alias "in0", 0 0, v0x2937120_0;
+v0x2936b60_0 .alias "in1", 0 0, v0x29375f0_0;
+v0x2936c00_0 .net "nS", 0 0, L_0x298e530; 1 drivers
+v0x2936c80_0 .net "out0", 0 0, L_0x298e5f0; 1 drivers
+v0x2936d20_0 .net "out1", 0 0, L_0x298e700; 1 drivers
+v0x2936e00_0 .alias "outfinal", 0 0, v0x29371d0_0;
+S_0x29362b0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2935bc0;
+ .timescale -9 -12;
+L_0x298e2a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x298e2a0 .delay (10000,10000,10000) L_0x298e2a0/d;
+L_0x298fb10/d .functor AND 1, L_0x298ff80, L_0x298e2a0, C4<1>, C4<1>;
+L_0x298fb10 .delay (20000,20000,20000) L_0x298fb10/d;
+L_0x298fbd0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x298fbd0 .delay (20000,20000,20000) L_0x298fbd0/d;
+L_0x298fc70/d .functor OR 1, L_0x298fb10, L_0x298fbd0, C4<0>, C4<0>;
+L_0x298fc70 .delay (20000,20000,20000) L_0x298fc70/d;
+v0x29363a0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2936440_0 .net "in0", 0 0, L_0x298ff80; 1 drivers
+v0x29364e0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2936580_0 .net "nS", 0 0, L_0x298e2a0; 1 drivers
+v0x2936600_0 .net "out0", 0 0, L_0x298fb10; 1 drivers
+v0x29366a0_0 .net "out1", 0 0, L_0x298fbd0; 1 drivers
+v0x2936780_0 .net "outfinal", 0 0, L_0x298fc70; 1 drivers
+S_0x2935d30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2935bc0;
+ .timescale -9 -12;
+L_0x2990060/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2990060 .delay (10000,10000,10000) L_0x2990060/d;
+L_0x2990170/d .functor AND 1, L_0x298fee0, L_0x2990060, C4<1>, C4<1>;
+L_0x2990170 .delay (20000,20000,20000) L_0x2990170/d;
+L_0x2990280/d .functor AND 1, L_0x2990600, L_0x29d1680, C4<1>, C4<1>;
+L_0x2990280 .delay (20000,20000,20000) L_0x2990280/d;
+L_0x2990320/d .functor OR 1, L_0x2990170, L_0x2990280, C4<0>, C4<0>;
+L_0x2990320 .delay (20000,20000,20000) L_0x2990320/d;
+v0x2935e20_0 .alias "S", 0 0, v0x293b720_0;
+v0x2935ea0_0 .net "in0", 0 0, L_0x298fee0; 1 drivers
+v0x2935f40_0 .net "in1", 0 0, L_0x2990600; 1 drivers
+v0x2935fe0_0 .net "nS", 0 0, L_0x2990060; 1 drivers
+v0x2936090_0 .net "out0", 0 0, L_0x2990170; 1 drivers
+v0x2936130_0 .net "out1", 0 0, L_0x2990280; 1 drivers
+v0x2936210_0 .net "outfinal", 0 0, L_0x2990320; 1 drivers
+S_0x2933f40 .scope generate, "sltbits[3]" "sltbits[3]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2933958 .param/l "i" 3 332, +C4<011>;
+S_0x2934ba0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2933f40;
+ .timescale -9 -12;
+L_0x2990500/d .functor NOT 1, L_0x29918e0, C4<0>, C4<0>, C4<0>;
+L_0x2990500 .delay (10000,10000,10000) L_0x2990500/d;
+L_0x2990e20/d .functor NOT 1, L_0x2990ee0, C4<0>, C4<0>, C4<0>;
+L_0x2990e20 .delay (10000,10000,10000) L_0x2990e20/d;
+L_0x2990f80/d .functor AND 1, L_0x29910c0, L_0x2990e20, C4<1>, C4<1>;
+L_0x2990f80 .delay (20000,20000,20000) L_0x2990f80/d;
+L_0x2991160/d .functor XOR 1, L_0x2991a00, L_0x2990bb0, C4<0>, C4<0>;
+L_0x2991160 .delay (40000,40000,40000) L_0x2991160/d;
+L_0x2991250/d .functor XOR 1, L_0x2991160, L_0x2991c10, C4<0>, C4<0>;
+L_0x2991250 .delay (40000,40000,40000) L_0x2991250/d;
+L_0x2991340/d .functor AND 1, L_0x2991a00, L_0x2990bb0, C4<1>, C4<1>;
+L_0x2991340 .delay (20000,20000,20000) L_0x2991340/d;
+L_0x29914b0/d .functor AND 1, L_0x2991160, L_0x2991c10, C4<1>, C4<1>;
+L_0x29914b0 .delay (20000,20000,20000) L_0x29914b0/d;
+L_0x29915a0/d .functor OR 1, L_0x2991340, L_0x29914b0, C4<0>, C4<0>;
+L_0x29915a0 .delay (20000,20000,20000) L_0x29915a0/d;
+v0x2935220_0 .net "A", 0 0, L_0x2991a00; 1 drivers
+v0x29352e0_0 .net "AandB", 0 0, L_0x2991340; 1 drivers
+v0x2935380_0 .net "AddSubSLTSum", 0 0, L_0x2991250; 1 drivers
+v0x2935420_0 .net "AxorB", 0 0, L_0x2991160; 1 drivers
+v0x29354a0_0 .net "B", 0 0, L_0x29918e0; 1 drivers
+v0x2935550_0 .net "BornB", 0 0, L_0x2990bb0; 1 drivers
+v0x2935610_0 .net "CINandAxorB", 0 0, L_0x29914b0; 1 drivers
+v0x2935690_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2935710_0 .net *"_s3", 0 0, L_0x2990ee0; 1 drivers
+v0x2935790_0 .net *"_s5", 0 0, L_0x29910c0; 1 drivers
+v0x2935830_0 .net "carryin", 0 0, L_0x2991c10; 1 drivers
+v0x29358d0_0 .net "carryout", 0 0, L_0x29915a0; 1 drivers
+v0x2935970_0 .net "nB", 0 0, L_0x2990500; 1 drivers
+v0x2935a20_0 .net "nCmd2", 0 0, L_0x2990e20; 1 drivers
+v0x2935b20_0 .net "subtract", 0 0, L_0x2990f80; 1 drivers
+L_0x2990d80 .part v0x2960210_0, 0, 1;
+L_0x2990ee0 .part v0x2960210_0, 2, 1;
+L_0x29910c0 .part v0x2960210_0, 0, 1;
+S_0x2934c90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2934ba0;
+ .timescale -9 -12;
+L_0x29908d0/d .functor NOT 1, L_0x2990d80, C4<0>, C4<0>, C4<0>;
+L_0x29908d0 .delay (10000,10000,10000) L_0x29908d0/d;
+L_0x2990990/d .functor AND 1, L_0x29918e0, L_0x29908d0, C4<1>, C4<1>;
+L_0x2990990 .delay (20000,20000,20000) L_0x2990990/d;
+L_0x2990aa0/d .functor AND 1, L_0x2990500, L_0x2990d80, C4<1>, C4<1>;
+L_0x2990aa0 .delay (20000,20000,20000) L_0x2990aa0/d;
+L_0x2990bb0/d .functor OR 1, L_0x2990990, L_0x2990aa0, C4<0>, C4<0>;
+L_0x2990bb0 .delay (20000,20000,20000) L_0x2990bb0/d;
+v0x2934d80_0 .net "S", 0 0, L_0x2990d80; 1 drivers
+v0x2934e40_0 .alias "in0", 0 0, v0x29354a0_0;
+v0x2934ee0_0 .alias "in1", 0 0, v0x2935970_0;
+v0x2934f80_0 .net "nS", 0 0, L_0x29908d0; 1 drivers
+v0x2935000_0 .net "out0", 0 0, L_0x2990990; 1 drivers
+v0x29350a0_0 .net "out1", 0 0, L_0x2990aa0; 1 drivers
+v0x2935180_0 .alias "outfinal", 0 0, v0x2935550_0;
+S_0x2934630 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2933f40;
+ .timescale -9 -12;
+L_0x2991aa0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2991aa0 .delay (10000,10000,10000) L_0x2991aa0/d;
+L_0x2991b20/d .functor AND 1, L_0x29920b0, L_0x2991aa0, C4<1>, C4<1>;
+L_0x2991b20 .delay (20000,20000,20000) L_0x2991b20/d;
+L_0x2991e30/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x2991e30 .delay (20000,20000,20000) L_0x2991e30/d;
+L_0x2991ed0/d .functor OR 1, L_0x2991b20, L_0x2991e30, C4<0>, C4<0>;
+L_0x2991ed0 .delay (20000,20000,20000) L_0x2991ed0/d;
+v0x2934720_0 .alias "S", 0 0, v0x293b720_0;
+v0x29347c0_0 .net "in0", 0 0, L_0x29920b0; 1 drivers
+v0x2934860_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2934900_0 .net "nS", 0 0, L_0x2991aa0; 1 drivers
+v0x2934980_0 .net "out0", 0 0, L_0x2991b20; 1 drivers
+v0x2934a20_0 .net "out1", 0 0, L_0x2991e30; 1 drivers
+v0x2934b00_0 .net "outfinal", 0 0, L_0x2991ed0; 1 drivers
+S_0x29340b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2933f40;
+ .timescale -9 -12;
+L_0x2991d40/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2991d40 .delay (10000,10000,10000) L_0x2991d40/d;
+L_0x2992330/d .functor AND 1, L_0x29926c0, L_0x2991d40, C4<1>, C4<1>;
+L_0x2992330 .delay (20000,20000,20000) L_0x2992330/d;
+L_0x2992440/d .functor AND 1, L_0x29921a0, L_0x29d1680, C4<1>, C4<1>;
+L_0x2992440 .delay (20000,20000,20000) L_0x2992440/d;
+L_0x29924e0/d .functor OR 1, L_0x2992330, L_0x2992440, C4<0>, C4<0>;
+L_0x29924e0 .delay (20000,20000,20000) L_0x29924e0/d;
+v0x29341a0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2934220_0 .net "in0", 0 0, L_0x29926c0; 1 drivers
+v0x29342c0_0 .net "in1", 0 0, L_0x29921a0; 1 drivers
+v0x2934360_0 .net "nS", 0 0, L_0x2991d40; 1 drivers
+v0x2934410_0 .net "out0", 0 0, L_0x2992330; 1 drivers
+v0x29344b0_0 .net "out1", 0 0, L_0x2992440; 1 drivers
+v0x2934590_0 .net "outfinal", 0 0, L_0x29924e0; 1 drivers
+S_0x29322c0 .scope generate, "sltbits[4]" "sltbits[4]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2931cd8 .param/l "i" 3 332, +C4<0100>;
+S_0x2932f20 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x29322c0;
+ .timescale -9 -12;
+L_0x298fe50/d .functor NOT 1, L_0x2993ca0, C4<0>, C4<0>, C4<0>;
+L_0x298fe50 .delay (10000,10000,10000) L_0x298fe50/d;
+L_0x298f470/d .functor NOT 1, L_0x2993070, C4<0>, C4<0>, C4<0>;
+L_0x298f470 .delay (10000,10000,10000) L_0x298f470/d;
+L_0x2993110/d .functor AND 1, L_0x2993250, L_0x298f470, C4<1>, C4<1>;
+L_0x2993110 .delay (20000,20000,20000) L_0x2993110/d;
+L_0x29932f0/d .functor XOR 1, L_0x2993960, L_0x2992e00, C4<0>, C4<0>;
+L_0x29932f0 .delay (40000,40000,40000) L_0x29932f0/d;
+L_0x29933e0/d .functor XOR 1, L_0x29932f0, L_0x2993b70, C4<0>, C4<0>;
+L_0x29933e0 .delay (40000,40000,40000) L_0x29933e0/d;
+L_0x29934d0/d .functor AND 1, L_0x2993960, L_0x2992e00, C4<1>, C4<1>;
+L_0x29934d0 .delay (20000,20000,20000) L_0x29934d0/d;
+L_0x2993640/d .functor AND 1, L_0x29932f0, L_0x2993b70, C4<1>, C4<1>;
+L_0x2993640 .delay (20000,20000,20000) L_0x2993640/d;
+L_0x2993730/d .functor OR 1, L_0x29934d0, L_0x2993640, C4<0>, C4<0>;
+L_0x2993730 .delay (20000,20000,20000) L_0x2993730/d;
+v0x29335a0_0 .net "A", 0 0, L_0x2993960; 1 drivers
+v0x2933660_0 .net "AandB", 0 0, L_0x29934d0; 1 drivers
+v0x2933700_0 .net "AddSubSLTSum", 0 0, L_0x29933e0; 1 drivers
+v0x29337a0_0 .net "AxorB", 0 0, L_0x29932f0; 1 drivers
+v0x2933820_0 .net "B", 0 0, L_0x2993ca0; 1 drivers
+v0x29338d0_0 .net "BornB", 0 0, L_0x2992e00; 1 drivers
+v0x2933990_0 .net "CINandAxorB", 0 0, L_0x2993640; 1 drivers
+v0x2933a10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2933a90_0 .net *"_s3", 0 0, L_0x2993070; 1 drivers
+v0x2933b10_0 .net *"_s5", 0 0, L_0x2993250; 1 drivers
+v0x2933bb0_0 .net "carryin", 0 0, L_0x2993b70; 1 drivers
+v0x2933c50_0 .net "carryout", 0 0, L_0x2993730; 1 drivers
+v0x2933cf0_0 .net "nB", 0 0, L_0x298fe50; 1 drivers
+v0x2933da0_0 .net "nCmd2", 0 0, L_0x298f470; 1 drivers
+v0x2933ea0_0 .net "subtract", 0 0, L_0x2993110; 1 drivers
+L_0x2992fd0 .part v0x2960210_0, 0, 1;
+L_0x2993070 .part v0x2960210_0, 2, 1;
+L_0x2993250 .part v0x2960210_0, 0, 1;
+S_0x2933010 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2932f20;
+ .timescale -9 -12;
+L_0x2992b20/d .functor NOT 1, L_0x2992fd0, C4<0>, C4<0>, C4<0>;
+L_0x2992b20 .delay (10000,10000,10000) L_0x2992b20/d;
+L_0x2992be0/d .functor AND 1, L_0x2993ca0, L_0x2992b20, C4<1>, C4<1>;
+L_0x2992be0 .delay (20000,20000,20000) L_0x2992be0/d;
+L_0x2992cf0/d .functor AND 1, L_0x298fe50, L_0x2992fd0, C4<1>, C4<1>;
+L_0x2992cf0 .delay (20000,20000,20000) L_0x2992cf0/d;
+L_0x2992e00/d .functor OR 1, L_0x2992be0, L_0x2992cf0, C4<0>, C4<0>;
+L_0x2992e00 .delay (20000,20000,20000) L_0x2992e00/d;
+v0x2933100_0 .net "S", 0 0, L_0x2992fd0; 1 drivers
+v0x29331c0_0 .alias "in0", 0 0, v0x2933820_0;
+v0x2933260_0 .alias "in1", 0 0, v0x2933cf0_0;
+v0x2933300_0 .net "nS", 0 0, L_0x2992b20; 1 drivers
+v0x2933380_0 .net "out0", 0 0, L_0x2992be0; 1 drivers
+v0x2933420_0 .net "out1", 0 0, L_0x2992cf0; 1 drivers
+v0x2933500_0 .alias "outfinal", 0 0, v0x29338d0_0;
+S_0x29329b0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x29322c0;
+ .timescale -9 -12;
+L_0x2993a00/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2993a00 .delay (10000,10000,10000) L_0x2993a00/d;
+L_0x2993c10/d .functor AND 1, L_0x2993dd0, L_0x2993a00, C4<1>, C4<1>;
+L_0x2993c10 .delay (20000,20000,20000) L_0x2993c10/d;
+L_0x2994020/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x2994020 .delay (20000,20000,20000) L_0x2994020/d;
+L_0x29940c0/d .functor OR 1, L_0x2993c10, L_0x2994020, C4<0>, C4<0>;
+L_0x29940c0 .delay (20000,20000,20000) L_0x29940c0/d;
+v0x2932aa0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2932b40_0 .net "in0", 0 0, L_0x2993dd0; 1 drivers
+v0x2932be0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2932c80_0 .net "nS", 0 0, L_0x2993a00; 1 drivers
+v0x2932d00_0 .net "out0", 0 0, L_0x2993c10; 1 drivers
+v0x2932da0_0 .net "out1", 0 0, L_0x2994020; 1 drivers
+v0x2932e80_0 .net "outfinal", 0 0, L_0x29940c0; 1 drivers
+S_0x2932430 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x29322c0;
+ .timescale -9 -12;
+L_0x2994500/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2994500 .delay (10000,10000,10000) L_0x2994500/d;
+L_0x29945d0/d .functor AND 1, L_0x29942a0, L_0x2994500, C4<1>, C4<1>;
+L_0x29945d0 .delay (20000,20000,20000) L_0x29945d0/d;
+L_0x29946e0/d .functor AND 1, L_0x2994ac0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29946e0 .delay (20000,20000,20000) L_0x29946e0/d;
+L_0x2994780/d .functor OR 1, L_0x29945d0, L_0x29946e0, C4<0>, C4<0>;
+L_0x2994780 .delay (20000,20000,20000) L_0x2994780/d;
+v0x2932520_0 .alias "S", 0 0, v0x293b720_0;
+v0x29325a0_0 .net "in0", 0 0, L_0x29942a0; 1 drivers
+v0x2932640_0 .net "in1", 0 0, L_0x2994ac0; 1 drivers
+v0x29326e0_0 .net "nS", 0 0, L_0x2994500; 1 drivers
+v0x2932790_0 .net "out0", 0 0, L_0x29945d0; 1 drivers
+v0x2932830_0 .net "out1", 0 0, L_0x29946e0; 1 drivers
+v0x2932910_0 .net "outfinal", 0 0, L_0x2994780; 1 drivers
+S_0x2930600 .scope generate, "sltbits[5]" "sltbits[5]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x29306f8 .param/l "i" 3 332, +C4<0101>;
+S_0x29312a0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2930600;
+ .timescale -9 -12;
+L_0x2994960/d .functor NOT 1, L_0x2995d50, C4<0>, C4<0>, C4<0>;
+L_0x2994960 .delay (10000,10000,10000) L_0x2994960/d;
+L_0x2995290/d .functor NOT 1, L_0x2995350, C4<0>, C4<0>, C4<0>;
+L_0x2995290 .delay (10000,10000,10000) L_0x2995290/d;
+L_0x29953f0/d .functor AND 1, L_0x2995530, L_0x2995290, C4<1>, C4<1>;
+L_0x29953f0 .delay (20000,20000,20000) L_0x29953f0/d;
+L_0x29955d0/d .functor XOR 1, L_0x2995ed0, L_0x2995020, C4<0>, C4<0>;
+L_0x29955d0 .delay (40000,40000,40000) L_0x29955d0/d;
+L_0x29956c0/d .functor XOR 1, L_0x29955d0, L_0x2996100, C4<0>, C4<0>;
+L_0x29956c0 .delay (40000,40000,40000) L_0x29956c0/d;
+L_0x29957b0/d .functor AND 1, L_0x2995ed0, L_0x2995020, C4<1>, C4<1>;
+L_0x29957b0 .delay (20000,20000,20000) L_0x29957b0/d;
+L_0x2995920/d .functor AND 1, L_0x29955d0, L_0x2996100, C4<1>, C4<1>;
+L_0x2995920 .delay (20000,20000,20000) L_0x2995920/d;
+L_0x2995a10/d .functor OR 1, L_0x29957b0, L_0x2995920, C4<0>, C4<0>;
+L_0x2995a10 .delay (20000,20000,20000) L_0x2995a10/d;
+v0x2931920_0 .net "A", 0 0, L_0x2995ed0; 1 drivers
+v0x29319e0_0 .net "AandB", 0 0, L_0x29957b0; 1 drivers
+v0x2931a80_0 .net "AddSubSLTSum", 0 0, L_0x29956c0; 1 drivers
+v0x2931b20_0 .net "AxorB", 0 0, L_0x29955d0; 1 drivers
+v0x2931ba0_0 .net "B", 0 0, L_0x2995d50; 1 drivers
+v0x2931c50_0 .net "BornB", 0 0, L_0x2995020; 1 drivers
+v0x2931d10_0 .net "CINandAxorB", 0 0, L_0x2995920; 1 drivers
+v0x2931d90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2931e10_0 .net *"_s3", 0 0, L_0x2995350; 1 drivers
+v0x2931e90_0 .net *"_s5", 0 0, L_0x2995530; 1 drivers
+v0x2931f30_0 .net "carryin", 0 0, L_0x2996100; 1 drivers
+v0x2931fd0_0 .net "carryout", 0 0, L_0x2995a10; 1 drivers
+v0x2932070_0 .net "nB", 0 0, L_0x2994960; 1 drivers
+v0x2932120_0 .net "nCmd2", 0 0, L_0x2995290; 1 drivers
+v0x2932220_0 .net "subtract", 0 0, L_0x29953f0; 1 drivers
+L_0x29951f0 .part v0x2960210_0, 0, 1;
+L_0x2995350 .part v0x2960210_0, 2, 1;
+L_0x2995530 .part v0x2960210_0, 0, 1;
+S_0x2931390 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29312a0;
+ .timescale -9 -12;
+L_0x2994d40/d .functor NOT 1, L_0x29951f0, C4<0>, C4<0>, C4<0>;
+L_0x2994d40 .delay (10000,10000,10000) L_0x2994d40/d;
+L_0x2994e00/d .functor AND 1, L_0x2995d50, L_0x2994d40, C4<1>, C4<1>;
+L_0x2994e00 .delay (20000,20000,20000) L_0x2994e00/d;
+L_0x2994f10/d .functor AND 1, L_0x2994960, L_0x29951f0, C4<1>, C4<1>;
+L_0x2994f10 .delay (20000,20000,20000) L_0x2994f10/d;
+L_0x2995020/d .functor OR 1, L_0x2994e00, L_0x2994f10, C4<0>, C4<0>;
+L_0x2995020 .delay (20000,20000,20000) L_0x2995020/d;
+v0x2931480_0 .net "S", 0 0, L_0x29951f0; 1 drivers
+v0x2931540_0 .alias "in0", 0 0, v0x2931ba0_0;
+v0x29315e0_0 .alias "in1", 0 0, v0x2932070_0;
+v0x2931680_0 .net "nS", 0 0, L_0x2994d40; 1 drivers
+v0x2931700_0 .net "out0", 0 0, L_0x2994e00; 1 drivers
+v0x29317a0_0 .net "out1", 0 0, L_0x2994f10; 1 drivers
+v0x2931880_0 .alias "outfinal", 0 0, v0x2931c50_0;
+S_0x2930d30 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2930600;
+ .timescale -9 -12;
+L_0x2994c50/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2994c50 .delay (10000,10000,10000) L_0x2994c50/d;
+L_0x2995f70/d .functor AND 1, L_0x2996560, L_0x2994c50, C4<1>, C4<1>;
+L_0x2995f70 .delay (20000,20000,20000) L_0x2995f70/d;
+L_0x2996080/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x2996080 .delay (20000,20000,20000) L_0x2996080/d;
+L_0x2996380/d .functor OR 1, L_0x2995f70, L_0x2996080, C4<0>, C4<0>;
+L_0x2996380 .delay (20000,20000,20000) L_0x2996380/d;
+v0x2930e20_0 .alias "S", 0 0, v0x293b720_0;
+v0x2930ec0_0 .net "in0", 0 0, L_0x2996560; 1 drivers
+v0x2930f60_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2931000_0 .net "nS", 0 0, L_0x2994c50; 1 drivers
+v0x2931080_0 .net "out0", 0 0, L_0x2995f70; 1 drivers
+v0x2931120_0 .net "out1", 0 0, L_0x2996080; 1 drivers
+v0x2931200_0 .net "outfinal", 0 0, L_0x2996380; 1 drivers
+S_0x29307b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2930600;
+ .timescale -9 -12;
+L_0x2996270/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2996270 .delay (10000,10000,10000) L_0x2996270/d;
+L_0x2996850/d .functor AND 1, L_0x2996cd0, L_0x2996270, C4<1>, C4<1>;
+L_0x2996850 .delay (20000,20000,20000) L_0x2996850/d;
+L_0x2996940/d .functor AND 1, L_0x2996650, L_0x29d1680, C4<1>, C4<1>;
+L_0x2996940 .delay (20000,20000,20000) L_0x2996940/d;
+L_0x29969e0/d .functor OR 1, L_0x2996850, L_0x2996940, C4<0>, C4<0>;
+L_0x29969e0 .delay (20000,20000,20000) L_0x29969e0/d;
+v0x29308a0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2930920_0 .net "in0", 0 0, L_0x2996cd0; 1 drivers
+v0x29309c0_0 .net "in1", 0 0, L_0x2996650; 1 drivers
+v0x2930a60_0 .net "nS", 0 0, L_0x2996270; 1 drivers
+v0x2930b10_0 .net "out0", 0 0, L_0x2996850; 1 drivers
+v0x2930bb0_0 .net "out1", 0 0, L_0x2996940; 1 drivers
+v0x2930c90_0 .net "outfinal", 0 0, L_0x29969e0; 1 drivers
+S_0x292e9b0 .scope generate, "sltbits[6]" "sltbits[6]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x292e3c8 .param/l "i" 3 332, +C4<0110>;
+S_0x292f610 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x292e9b0;
+ .timescale -9 -12;
+L_0x2996740/d .functor NOT 1, L_0x2891bb0, C4<0>, C4<0>, C4<0>;
+L_0x2996740 .delay (10000,10000,10000) L_0x2996740/d;
+L_0x2997560/d .functor NOT 1, L_0x2997620, C4<0>, C4<0>, C4<0>;
+L_0x2997560 .delay (10000,10000,10000) L_0x2997560/d;
+L_0x29976c0/d .functor AND 1, L_0x2997800, L_0x2997560, C4<1>, C4<1>;
+L_0x29976c0 .delay (20000,20000,20000) L_0x29976c0/d;
+L_0x2891460/d .functor XOR 1, L_0x2891b10, L_0x29972f0, C4<0>, C4<0>;
+L_0x2891460 .delay (40000,40000,40000) L_0x2891460/d;
+L_0x2891550/d .functor XOR 1, L_0x2891460, L_0x2891f20, C4<0>, C4<0>;
+L_0x2891550 .delay (40000,40000,40000) L_0x2891550/d;
+L_0x2891640/d .functor AND 1, L_0x2891b10, L_0x29972f0, C4<1>, C4<1>;
+L_0x2891640 .delay (20000,20000,20000) L_0x2891640/d;
+L_0x28917b0/d .functor AND 1, L_0x2891460, L_0x2891f20, C4<1>, C4<1>;
+L_0x28917b0 .delay (20000,20000,20000) L_0x28917b0/d;
+L_0x28918a0/d .functor OR 1, L_0x2891640, L_0x28917b0, C4<0>, C4<0>;
+L_0x28918a0 .delay (20000,20000,20000) L_0x28918a0/d;
+v0x292fc90_0 .net "A", 0 0, L_0x2891b10; 1 drivers
+v0x292fd50_0 .net "AandB", 0 0, L_0x2891640; 1 drivers
+v0x292fdf0_0 .net "AddSubSLTSum", 0 0, L_0x2891550; 1 drivers
+v0x292fe90_0 .net "AxorB", 0 0, L_0x2891460; 1 drivers
+v0x292ff10_0 .net "B", 0 0, L_0x2891bb0; 1 drivers
+v0x292ffc0_0 .net "BornB", 0 0, L_0x29972f0; 1 drivers
+v0x2930040_0 .net "CINandAxorB", 0 0, L_0x28917b0; 1 drivers
+v0x29300c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2930140_0 .net *"_s3", 0 0, L_0x2997620; 1 drivers
+v0x29301c0_0 .net *"_s5", 0 0, L_0x2997800; 1 drivers
+v0x2930240_0 .net "carryin", 0 0, L_0x2891f20; 1 drivers
+v0x29302c0_0 .net "carryout", 0 0, L_0x28918a0; 1 drivers
+v0x29303b0_0 .net "nB", 0 0, L_0x2996740; 1 drivers
+v0x2930460_0 .net "nCmd2", 0 0, L_0x2997560; 1 drivers
+v0x2930560_0 .net "subtract", 0 0, L_0x29976c0; 1 drivers
+L_0x29974c0 .part v0x2960210_0, 0, 1;
+L_0x2997620 .part v0x2960210_0, 2, 1;
+L_0x2997800 .part v0x2960210_0, 0, 1;
+S_0x292f700 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292f610;
+ .timescale -9 -12;
+L_0x2997010/d .functor NOT 1, L_0x29974c0, C4<0>, C4<0>, C4<0>;
+L_0x2997010 .delay (10000,10000,10000) L_0x2997010/d;
+L_0x29970d0/d .functor AND 1, L_0x2891bb0, L_0x2997010, C4<1>, C4<1>;
+L_0x29970d0 .delay (20000,20000,20000) L_0x29970d0/d;
+L_0x29971e0/d .functor AND 1, L_0x2996740, L_0x29974c0, C4<1>, C4<1>;
+L_0x29971e0 .delay (20000,20000,20000) L_0x29971e0/d;
+L_0x29972f0/d .functor OR 1, L_0x29970d0, L_0x29971e0, C4<0>, C4<0>;
+L_0x29972f0 .delay (20000,20000,20000) L_0x29972f0/d;
+v0x292f7f0_0 .net "S", 0 0, L_0x29974c0; 1 drivers
+v0x292f8b0_0 .alias "in0", 0 0, v0x292ff10_0;
+v0x292f950_0 .alias "in1", 0 0, v0x29303b0_0;
+v0x292f9f0_0 .net "nS", 0 0, L_0x2997010; 1 drivers
+v0x292fa70_0 .net "out0", 0 0, L_0x29970d0; 1 drivers
+v0x292fb10_0 .net "out1", 0 0, L_0x29971e0; 1 drivers
+v0x292fbf0_0 .alias "outfinal", 0 0, v0x292ffc0_0;
+S_0x292f0a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x292e9b0;
+ .timescale -9 -12;
+L_0x2891fc0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2891fc0 .delay (10000,10000,10000) L_0x2891fc0/d;
+L_0x2892060/d .functor AND 1, L_0x29927b0, L_0x2891fc0, C4<1>, C4<1>;
+L_0x2892060 .delay (20000,20000,20000) L_0x2892060/d;
+L_0x2892170/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x2892170 .delay (20000,20000,20000) L_0x2892170/d;
+L_0x2892210/d .functor OR 1, L_0x2892060, L_0x2892170, C4<0>, C4<0>;
+L_0x2892210 .delay (20000,20000,20000) L_0x2892210/d;
+v0x292f190_0 .alias "S", 0 0, v0x293b720_0;
+v0x292f230_0 .net "in0", 0 0, L_0x29927b0; 1 drivers
+v0x292f2d0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x292f370_0 .net "nS", 0 0, L_0x2891fc0; 1 drivers
+v0x292f3f0_0 .net "out0", 0 0, L_0x2892060; 1 drivers
+v0x292f490_0 .net "out1", 0 0, L_0x2892170; 1 drivers
+v0x292f570_0 .net "outfinal", 0 0, L_0x2892210; 1 drivers
+S_0x292eb20 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x292e9b0;
+ .timescale -9 -12;
+L_0x2891dc0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2891dc0 .delay (10000,10000,10000) L_0x2891dc0/d;
+L_0x2891eb0/d .functor AND 1, L_0x2892600, L_0x2891dc0, C4<1>, C4<1>;
+L_0x2891eb0 .delay (20000,20000,20000) L_0x2891eb0/d;
+L_0x2892890/d .functor AND 1, L_0x28926f0, L_0x29d1680, C4<1>, C4<1>;
+L_0x2892890 .delay (20000,20000,20000) L_0x2892890/d;
+L_0x2892930/d .functor OR 1, L_0x2891eb0, L_0x2892890, C4<0>, C4<0>;
+L_0x2892930 .delay (20000,20000,20000) L_0x2892930/d;
+v0x292ec10_0 .alias "S", 0 0, v0x293b720_0;
+v0x292ec90_0 .net "in0", 0 0, L_0x2892600; 1 drivers
+v0x292ed30_0 .net "in1", 0 0, L_0x28926f0; 1 drivers
+v0x292edd0_0 .net "nS", 0 0, L_0x2891dc0; 1 drivers
+v0x292ee80_0 .net "out0", 0 0, L_0x2891eb0; 1 drivers
+v0x292ef20_0 .net "out1", 0 0, L_0x2892890; 1 drivers
+v0x292f000_0 .net "outfinal", 0 0, L_0x2892930; 1 drivers
+S_0x292cd30 .scope generate, "sltbits[7]" "sltbits[7]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x292c748 .param/l "i" 3 332, +C4<0111>;
+S_0x292d990 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x292cd30;
+ .timescale -9 -12;
+L_0x2892d30/d .functor NOT 1, L_0x299c530, C4<0>, C4<0>, C4<0>;
+L_0x2892d30 .delay (10000,10000,10000) L_0x2892d30/d;
+L_0x299b8b0/d .functor NOT 1, L_0x299b910, C4<0>, C4<0>, C4<0>;
+L_0x299b8b0 .delay (10000,10000,10000) L_0x299b8b0/d;
+L_0x299b9b0/d .functor AND 1, L_0x299baf0, L_0x299b8b0, C4<1>, C4<1>;
+L_0x299b9b0 .delay (20000,20000,20000) L_0x299b9b0/d;
+L_0x299bb90/d .functor XOR 1, L_0x2892c00, L_0x28931c0, C4<0>, C4<0>;
+L_0x299bb90 .delay (40000,40000,40000) L_0x299bb90/d;
+L_0x299bc80/d .functor XOR 1, L_0x299bb90, L_0x299c5d0, C4<0>, C4<0>;
+L_0x299bc80 .delay (40000,40000,40000) L_0x299bc80/d;
+L_0x299bd70/d .functor AND 1, L_0x2892c00, L_0x28931c0, C4<1>, C4<1>;
+L_0x299bd70 .delay (20000,20000,20000) L_0x299bd70/d;
+L_0x299bee0/d .functor AND 1, L_0x299bb90, L_0x299c5d0, C4<1>, C4<1>;
+L_0x299bee0 .delay (20000,20000,20000) L_0x299bee0/d;
+L_0x299bfd0/d .functor OR 1, L_0x299bd70, L_0x299bee0, C4<0>, C4<0>;
+L_0x299bfd0 .delay (20000,20000,20000) L_0x299bfd0/d;
+v0x292e010_0 .net "A", 0 0, L_0x2892c00; 1 drivers
+v0x292e0d0_0 .net "AandB", 0 0, L_0x299bd70; 1 drivers
+v0x292e170_0 .net "AddSubSLTSum", 0 0, L_0x299bc80; 1 drivers
+v0x292e210_0 .net "AxorB", 0 0, L_0x299bb90; 1 drivers
+v0x292e290_0 .net "B", 0 0, L_0x299c530; 1 drivers
+v0x292e340_0 .net "BornB", 0 0, L_0x28931c0; 1 drivers
+v0x292e400_0 .net "CINandAxorB", 0 0, L_0x299bee0; 1 drivers
+v0x292e480_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x292e500_0 .net *"_s3", 0 0, L_0x299b910; 1 drivers
+v0x292e580_0 .net *"_s5", 0 0, L_0x299baf0; 1 drivers
+v0x292e620_0 .net "carryin", 0 0, L_0x299c5d0; 1 drivers
+v0x292e6c0_0 .net "carryout", 0 0, L_0x299bfd0; 1 drivers
+v0x292e760_0 .net "nB", 0 0, L_0x2892d30; 1 drivers
+v0x292e810_0 .net "nCmd2", 0 0, L_0x299b8b0; 1 drivers
+v0x292e910_0 .net "subtract", 0 0, L_0x299b9b0; 1 drivers
+L_0x2893390 .part v0x2960210_0, 0, 1;
+L_0x299b910 .part v0x2960210_0, 2, 1;
+L_0x299baf0 .part v0x2960210_0, 0, 1;
+S_0x292da80 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292d990;
+ .timescale -9 -12;
+L_0x2892ee0/d .functor NOT 1, L_0x2893390, C4<0>, C4<0>, C4<0>;
+L_0x2892ee0 .delay (10000,10000,10000) L_0x2892ee0/d;
+L_0x2892fa0/d .functor AND 1, L_0x299c530, L_0x2892ee0, C4<1>, C4<1>;
+L_0x2892fa0 .delay (20000,20000,20000) L_0x2892fa0/d;
+L_0x28930b0/d .functor AND 1, L_0x2892d30, L_0x2893390, C4<1>, C4<1>;
+L_0x28930b0 .delay (20000,20000,20000) L_0x28930b0/d;
+L_0x28931c0/d .functor OR 1, L_0x2892fa0, L_0x28930b0, C4<0>, C4<0>;
+L_0x28931c0 .delay (20000,20000,20000) L_0x28931c0/d;
+v0x292db70_0 .net "S", 0 0, L_0x2893390; 1 drivers
+v0x292dc30_0 .alias "in0", 0 0, v0x292e290_0;
+v0x292dcd0_0 .alias "in1", 0 0, v0x292e760_0;
+v0x292dd70_0 .net "nS", 0 0, L_0x2892ee0; 1 drivers
+v0x292ddf0_0 .net "out0", 0 0, L_0x2892fa0; 1 drivers
+v0x292de90_0 .net "out1", 0 0, L_0x28930b0; 1 drivers
+v0x292df70_0 .alias "outfinal", 0 0, v0x292e340_0;
+S_0x292d420 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x292cd30;
+ .timescale -9 -12;
+L_0x299c2f0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x299c2f0 .delay (10000,10000,10000) L_0x299c2f0/d;
+L_0x299c390/d .functor AND 1, L_0x299cae0, L_0x299c2f0, C4<1>, C4<1>;
+L_0x299c390 .delay (20000,20000,20000) L_0x299c390/d;
+L_0x299c4a0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x299c4a0 .delay (20000,20000,20000) L_0x299c4a0/d;
+L_0x299c900/d .functor OR 1, L_0x299c390, L_0x299c4a0, C4<0>, C4<0>;
+L_0x299c900 .delay (20000,20000,20000) L_0x299c900/d;
+v0x292d510_0 .alias "S", 0 0, v0x293b720_0;
+v0x292d5b0_0 .net "in0", 0 0, L_0x299cae0; 1 drivers
+v0x292d650_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x292d6f0_0 .net "nS", 0 0, L_0x299c2f0; 1 drivers
+v0x292d770_0 .net "out0", 0 0, L_0x299c390; 1 drivers
+v0x292d810_0 .net "out1", 0 0, L_0x299c4a0; 1 drivers
+v0x292d8f0_0 .net "outfinal", 0 0, L_0x299c900; 1 drivers
+S_0x292cea0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x292cd30;
+ .timescale -9 -12;
+L_0x299c750/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x299c750 .delay (10000,10000,10000) L_0x299c750/d;
+L_0x299c820/d .functor AND 1, L_0x299d100, L_0x299c750, C4<1>, C4<1>;
+L_0x299c820 .delay (20000,20000,20000) L_0x299c820/d;
+L_0x299ce80/d .functor AND 1, L_0x299cbd0, L_0x29d1680, C4<1>, C4<1>;
+L_0x299ce80 .delay (20000,20000,20000) L_0x299ce80/d;
+L_0x299cf20/d .functor OR 1, L_0x299c820, L_0x299ce80, C4<0>, C4<0>;
+L_0x299cf20 .delay (20000,20000,20000) L_0x299cf20/d;
+v0x292cf90_0 .alias "S", 0 0, v0x293b720_0;
+v0x292d010_0 .net "in0", 0 0, L_0x299d100; 1 drivers
+v0x292d0b0_0 .net "in1", 0 0, L_0x299cbd0; 1 drivers
+v0x292d150_0 .net "nS", 0 0, L_0x299c750; 1 drivers
+v0x292d200_0 .net "out0", 0 0, L_0x299c820; 1 drivers
+v0x292d2a0_0 .net "out1", 0 0, L_0x299ce80; 1 drivers
+v0x292d380_0 .net "outfinal", 0 0, L_0x299cf20; 1 drivers
+S_0x292b0b0 .scope generate, "sltbits[8]" "sltbits[8]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x292aac8 .param/l "i" 3 332, +C4<01000>;
+S_0x292bd10 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x292b0b0;
+ .timescale -9 -12;
+L_0x299ccc0/d .functor NOT 1, L_0x299e720, C4<0>, C4<0>, C4<0>;
+L_0x299ccc0 .delay (10000,10000,10000) L_0x299ccc0/d;
+L_0x299da20/d .functor NOT 1, L_0x299dae0, C4<0>, C4<0>, C4<0>;
+L_0x299da20 .delay (10000,10000,10000) L_0x299da20/d;
+L_0x299db80/d .functor AND 1, L_0x299dcc0, L_0x299da20, C4<1>, C4<1>;
+L_0x299db80 .delay (20000,20000,20000) L_0x299db80/d;
+L_0x299dd60/d .functor XOR 1, L_0x299e680, L_0x299d7b0, C4<0>, C4<0>;
+L_0x299dd60 .delay (40000,40000,40000) L_0x299dd60/d;
+L_0x299de50/d .functor XOR 1, L_0x299dd60, L_0x299e3f0, C4<0>, C4<0>;
+L_0x299de50 .delay (40000,40000,40000) L_0x299de50/d;
+L_0x299df40/d .functor AND 1, L_0x299e680, L_0x299d7b0, C4<1>, C4<1>;
+L_0x299df40 .delay (20000,20000,20000) L_0x299df40/d;
+L_0x299e0b0/d .functor AND 1, L_0x299dd60, L_0x299e3f0, C4<1>, C4<1>;
+L_0x299e0b0 .delay (20000,20000,20000) L_0x299e0b0/d;
+L_0x299e1a0/d .functor OR 1, L_0x299df40, L_0x299e0b0, C4<0>, C4<0>;
+L_0x299e1a0 .delay (20000,20000,20000) L_0x299e1a0/d;
+v0x292c390_0 .net "A", 0 0, L_0x299e680; 1 drivers
+v0x292c450_0 .net "AandB", 0 0, L_0x299df40; 1 drivers
+v0x292c4f0_0 .net "AddSubSLTSum", 0 0, L_0x299de50; 1 drivers
+v0x292c590_0 .net "AxorB", 0 0, L_0x299dd60; 1 drivers
+v0x292c610_0 .net "B", 0 0, L_0x299e720; 1 drivers
+v0x292c6c0_0 .net "BornB", 0 0, L_0x299d7b0; 1 drivers
+v0x292c780_0 .net "CINandAxorB", 0 0, L_0x299e0b0; 1 drivers
+v0x292c800_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x292c880_0 .net *"_s3", 0 0, L_0x299dae0; 1 drivers
+v0x292c900_0 .net *"_s5", 0 0, L_0x299dcc0; 1 drivers
+v0x292c9a0_0 .net "carryin", 0 0, L_0x299e3f0; 1 drivers
+v0x292ca40_0 .net "carryout", 0 0, L_0x299e1a0; 1 drivers
+v0x292cae0_0 .net "nB", 0 0, L_0x299ccc0; 1 drivers
+v0x292cb90_0 .net "nCmd2", 0 0, L_0x299da20; 1 drivers
+v0x292cc90_0 .net "subtract", 0 0, L_0x299db80; 1 drivers
+L_0x299d980 .part v0x2960210_0, 0, 1;
+L_0x299dae0 .part v0x2960210_0, 2, 1;
+L_0x299dcc0 .part v0x2960210_0, 0, 1;
+S_0x292be00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292bd10;
+ .timescale -9 -12;
+L_0x299d4d0/d .functor NOT 1, L_0x299d980, C4<0>, C4<0>, C4<0>;
+L_0x299d4d0 .delay (10000,10000,10000) L_0x299d4d0/d;
+L_0x299d590/d .functor AND 1, L_0x299e720, L_0x299d4d0, C4<1>, C4<1>;
+L_0x299d590 .delay (20000,20000,20000) L_0x299d590/d;
+L_0x299d6a0/d .functor AND 1, L_0x299ccc0, L_0x299d980, C4<1>, C4<1>;
+L_0x299d6a0 .delay (20000,20000,20000) L_0x299d6a0/d;
+L_0x299d7b0/d .functor OR 1, L_0x299d590, L_0x299d6a0, C4<0>, C4<0>;
+L_0x299d7b0 .delay (20000,20000,20000) L_0x299d7b0/d;
+v0x292bef0_0 .net "S", 0 0, L_0x299d980; 1 drivers
+v0x292bfb0_0 .alias "in0", 0 0, v0x292c610_0;
+v0x292c050_0 .alias "in1", 0 0, v0x292cae0_0;
+v0x292c0f0_0 .net "nS", 0 0, L_0x299d4d0; 1 drivers
+v0x292c170_0 .net "out0", 0 0, L_0x299d590; 1 drivers
+v0x292c210_0 .net "out1", 0 0, L_0x299d6a0; 1 drivers
+v0x292c2f0_0 .alias "outfinal", 0 0, v0x292c6c0_0;
+S_0x292b7a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x292b0b0;
+ .timescale -9 -12;
+L_0x2993f10/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2993f10 .delay (10000,10000,10000) L_0x2993f10/d;
+L_0x2993fb0/d .functor AND 1, L_0x299e7c0, L_0x2993f10, C4<1>, C4<1>;
+L_0x2993fb0 .delay (20000,20000,20000) L_0x2993fb0/d;
+L_0x299e540/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x299e540 .delay (20000,20000,20000) L_0x299e540/d;
+L_0x299e5e0/d .functor OR 1, L_0x2993fb0, L_0x299e540, C4<0>, C4<0>;
+L_0x299e5e0 .delay (20000,20000,20000) L_0x299e5e0/d;
+v0x292b890_0 .alias "S", 0 0, v0x293b720_0;
+v0x292b930_0 .net "in0", 0 0, L_0x299e7c0; 1 drivers
+v0x292b9d0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x292ba70_0 .net "nS", 0 0, L_0x2993f10; 1 drivers
+v0x292baf0_0 .net "out0", 0 0, L_0x2993fb0; 1 drivers
+v0x292bb90_0 .net "out1", 0 0, L_0x299e540; 1 drivers
+v0x292bc70_0 .net "outfinal", 0 0, L_0x299e5e0; 1 drivers
+S_0x292b220 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x292b0b0;
+ .timescale -9 -12;
+L_0x2994480/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2994480 .delay (10000,10000,10000) L_0x2994480/d;
+L_0x299e940/d .functor AND 1, L_0x299edb0, L_0x2994480, C4<1>, C4<1>;
+L_0x299e940 .delay (20000,20000,20000) L_0x299e940/d;
+L_0x299ea00/d .functor AND 1, L_0x299eea0, L_0x29d1680, C4<1>, C4<1>;
+L_0x299ea00 .delay (20000,20000,20000) L_0x299ea00/d;
+L_0x299f300/d .functor OR 1, L_0x299e940, L_0x299ea00, C4<0>, C4<0>;
+L_0x299f300 .delay (20000,20000,20000) L_0x299f300/d;
+v0x292b310_0 .alias "S", 0 0, v0x293b720_0;
+v0x292b390_0 .net "in0", 0 0, L_0x299edb0; 1 drivers
+v0x292b430_0 .net "in1", 0 0, L_0x299eea0; 1 drivers
+v0x292b4d0_0 .net "nS", 0 0, L_0x2994480; 1 drivers
+v0x292b580_0 .net "out0", 0 0, L_0x299e940; 1 drivers
+v0x292b620_0 .net "out1", 0 0, L_0x299ea00; 1 drivers
+v0x292b700_0 .net "outfinal", 0 0, L_0x299f300; 1 drivers
+S_0x2929430 .scope generate, "sltbits[9]" "sltbits[9]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2928e48 .param/l "i" 3 332, +C4<01001>;
+S_0x292a090 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2929430;
+ .timescale -9 -12;
+L_0x299ef90/d .functor NOT 1, L_0x299f670, C4<0>, C4<0>, C4<0>;
+L_0x299ef90 .delay (10000,10000,10000) L_0x299ef90/d;
+L_0x299fe00/d .functor NOT 1, L_0x299fec0, C4<0>, C4<0>, C4<0>;
+L_0x299fe00 .delay (10000,10000,10000) L_0x299fe00/d;
+L_0x299ff60/d .functor AND 1, L_0x29a00a0, L_0x299fe00, C4<1>, C4<1>;
+L_0x299ff60 .delay (20000,20000,20000) L_0x299ff60/d;
+L_0x29a0140/d .functor XOR 1, L_0x299f5d0, L_0x299fb90, C4<0>, C4<0>;
+L_0x29a0140 .delay (40000,40000,40000) L_0x29a0140/d;
+L_0x29a0230/d .functor XOR 1, L_0x29a0140, L_0x29a0bb0, C4<0>, C4<0>;
+L_0x29a0230 .delay (40000,40000,40000) L_0x29a0230/d;
+L_0x29a0320/d .functor AND 1, L_0x299f5d0, L_0x299fb90, C4<1>, C4<1>;
+L_0x29a0320 .delay (20000,20000,20000) L_0x29a0320/d;
+L_0x29a0490/d .functor AND 1, L_0x29a0140, L_0x29a0bb0, C4<1>, C4<1>;
+L_0x29a0490 .delay (20000,20000,20000) L_0x29a0490/d;
+L_0x29a0580/d .functor OR 1, L_0x29a0320, L_0x29a0490, C4<0>, C4<0>;
+L_0x29a0580 .delay (20000,20000,20000) L_0x29a0580/d;
+v0x292a710_0 .net "A", 0 0, L_0x299f5d0; 1 drivers
+v0x292a7d0_0 .net "AandB", 0 0, L_0x29a0320; 1 drivers
+v0x292a870_0 .net "AddSubSLTSum", 0 0, L_0x29a0230; 1 drivers
+v0x292a910_0 .net "AxorB", 0 0, L_0x29a0140; 1 drivers
+v0x292a990_0 .net "B", 0 0, L_0x299f670; 1 drivers
+v0x292aa40_0 .net "BornB", 0 0, L_0x299fb90; 1 drivers
+v0x292ab00_0 .net "CINandAxorB", 0 0, L_0x29a0490; 1 drivers
+v0x292ab80_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x292ac00_0 .net *"_s3", 0 0, L_0x299fec0; 1 drivers
+v0x292ac80_0 .net *"_s5", 0 0, L_0x29a00a0; 1 drivers
+v0x292ad20_0 .net "carryin", 0 0, L_0x29a0bb0; 1 drivers
+v0x292adc0_0 .net "carryout", 0 0, L_0x29a0580; 1 drivers
+v0x292ae60_0 .net "nB", 0 0, L_0x299ef90; 1 drivers
+v0x292af10_0 .net "nCmd2", 0 0, L_0x299fe00; 1 drivers
+v0x292b010_0 .net "subtract", 0 0, L_0x299ff60; 1 drivers
+L_0x299fd60 .part v0x2960210_0, 0, 1;
+L_0x299fec0 .part v0x2960210_0, 2, 1;
+L_0x29a00a0 .part v0x2960210_0, 0, 1;
+S_0x292a180 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x292a090;
+ .timescale -9 -12;
+L_0x299f8b0/d .functor NOT 1, L_0x299fd60, C4<0>, C4<0>, C4<0>;
+L_0x299f8b0 .delay (10000,10000,10000) L_0x299f8b0/d;
+L_0x299f970/d .functor AND 1, L_0x299f670, L_0x299f8b0, C4<1>, C4<1>;
+L_0x299f970 .delay (20000,20000,20000) L_0x299f970/d;
+L_0x299fa80/d .functor AND 1, L_0x299ef90, L_0x299fd60, C4<1>, C4<1>;
+L_0x299fa80 .delay (20000,20000,20000) L_0x299fa80/d;
+L_0x299fb90/d .functor OR 1, L_0x299f970, L_0x299fa80, C4<0>, C4<0>;
+L_0x299fb90 .delay (20000,20000,20000) L_0x299fb90/d;
+v0x292a270_0 .net "S", 0 0, L_0x299fd60; 1 drivers
+v0x292a330_0 .alias "in0", 0 0, v0x292a990_0;
+v0x292a3d0_0 .alias "in1", 0 0, v0x292ae60_0;
+v0x292a470_0 .net "nS", 0 0, L_0x299f8b0; 1 drivers
+v0x292a4f0_0 .net "out0", 0 0, L_0x299f970; 1 drivers
+v0x292a590_0 .net "out1", 0 0, L_0x299fa80; 1 drivers
+v0x292a670_0 .alias "outfinal", 0 0, v0x292aa40_0;
+S_0x2929b20 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2929430;
+ .timescale -9 -12;
+L_0x29a08c0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a08c0 .delay (10000,10000,10000) L_0x29a08c0/d;
+L_0x29a0960/d .functor AND 1, L_0x29a1090, L_0x29a08c0, C4<1>, C4<1>;
+L_0x29a0960 .delay (20000,20000,20000) L_0x29a0960/d;
+L_0x29a0a70/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a0a70 .delay (20000,20000,20000) L_0x29a0a70/d;
+L_0x29a0b10/d .functor OR 1, L_0x29a0960, L_0x29a0a70, C4<0>, C4<0>;
+L_0x29a0b10 .delay (20000,20000,20000) L_0x29a0b10/d;
+v0x2929c10_0 .alias "S", 0 0, v0x293b720_0;
+v0x2929cb0_0 .net "in0", 0 0, L_0x29a1090; 1 drivers
+v0x2929d50_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2929df0_0 .net "nS", 0 0, L_0x29a08c0; 1 drivers
+v0x2929e70_0 .net "out0", 0 0, L_0x29a0960; 1 drivers
+v0x2929f10_0 .net "out1", 0 0, L_0x29a0a70; 1 drivers
+v0x2929ff0_0 .net "outfinal", 0 0, L_0x29a0b10; 1 drivers
+S_0x29295a0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2929430;
+ .timescale -9 -12;
+L_0x29a0d40/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a0d40 .delay (10000,10000,10000) L_0x29a0d40/d;
+L_0x29a0e00/d .functor AND 1, L_0x29a16d0, L_0x29a0d40, C4<1>, C4<1>;
+L_0x29a0e00 .delay (20000,20000,20000) L_0x29a0e00/d;
+L_0x29a1490/d .functor AND 1, L_0x29a1180, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a1490 .delay (20000,20000,20000) L_0x29a1490/d;
+L_0x29a14f0/d .functor OR 1, L_0x29a0e00, L_0x29a1490, C4<0>, C4<0>;
+L_0x29a14f0 .delay (20000,20000,20000) L_0x29a14f0/d;
+v0x2929690_0 .alias "S", 0 0, v0x293b720_0;
+v0x2929710_0 .net "in0", 0 0, L_0x29a16d0; 1 drivers
+v0x29297b0_0 .net "in1", 0 0, L_0x29a1180; 1 drivers
+v0x2929850_0 .net "nS", 0 0, L_0x29a0d40; 1 drivers
+v0x2929900_0 .net "out0", 0 0, L_0x29a0e00; 1 drivers
+v0x29299a0_0 .net "out1", 0 0, L_0x29a1490; 1 drivers
+v0x2929a80_0 .net "outfinal", 0 0, L_0x29a14f0; 1 drivers
+S_0x29277b0 .scope generate, "sltbits[10]" "sltbits[10]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x29271c8 .param/l "i" 3 332, +C4<01010>;
+S_0x2928410 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x29277b0;
+ .timescale -9 -12;
+L_0x29a1270/d .functor NOT 1, L_0x29a1a40, C4<0>, C4<0>, C4<0>;
+L_0x29a1270 .delay (10000,10000,10000) L_0x29a1270/d;
+L_0x29a1ff0/d .functor NOT 1, L_0x29a20b0, C4<0>, C4<0>, C4<0>;
+L_0x29a1ff0 .delay (10000,10000,10000) L_0x29a1ff0/d;
+L_0x29a2150/d .functor AND 1, L_0x29a2290, L_0x29a1ff0, C4<1>, C4<1>;
+L_0x29a2150 .delay (20000,20000,20000) L_0x29a2150/d;
+L_0x29a2330/d .functor XOR 1, L_0x29a19a0, L_0x29a1d80, C4<0>, C4<0>;
+L_0x29a2330 .delay (40000,40000,40000) L_0x29a2330/d;
+L_0x29a2420/d .functor XOR 1, L_0x29a2330, L_0x29a29c0, C4<0>, C4<0>;
+L_0x29a2420 .delay (40000,40000,40000) L_0x29a2420/d;
+L_0x29a2510/d .functor AND 1, L_0x29a19a0, L_0x29a1d80, C4<1>, C4<1>;
+L_0x29a2510 .delay (20000,20000,20000) L_0x29a2510/d;
+L_0x29a2680/d .functor AND 1, L_0x29a2330, L_0x29a29c0, C4<1>, C4<1>;
+L_0x29a2680 .delay (20000,20000,20000) L_0x29a2680/d;
+L_0x29a2770/d .functor OR 1, L_0x29a2510, L_0x29a2680, C4<0>, C4<0>;
+L_0x29a2770 .delay (20000,20000,20000) L_0x29a2770/d;
+v0x2928a90_0 .net "A", 0 0, L_0x29a19a0; 1 drivers
+v0x2928b50_0 .net "AandB", 0 0, L_0x29a2510; 1 drivers
+v0x2928bf0_0 .net "AddSubSLTSum", 0 0, L_0x29a2420; 1 drivers
+v0x2928c90_0 .net "AxorB", 0 0, L_0x29a2330; 1 drivers
+v0x2928d10_0 .net "B", 0 0, L_0x29a1a40; 1 drivers
+v0x2928dc0_0 .net "BornB", 0 0, L_0x29a1d80; 1 drivers
+v0x2928e80_0 .net "CINandAxorB", 0 0, L_0x29a2680; 1 drivers
+v0x2928f00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2928f80_0 .net *"_s3", 0 0, L_0x29a20b0; 1 drivers
+v0x2929000_0 .net *"_s5", 0 0, L_0x29a2290; 1 drivers
+v0x29290a0_0 .net "carryin", 0 0, L_0x29a29c0; 1 drivers
+v0x2929140_0 .net "carryout", 0 0, L_0x29a2770; 1 drivers
+v0x29291e0_0 .net "nB", 0 0, L_0x29a1270; 1 drivers
+v0x2929290_0 .net "nCmd2", 0 0, L_0x29a1ff0; 1 drivers
+v0x2929390_0 .net "subtract", 0 0, L_0x29a2150; 1 drivers
+L_0x29a1f50 .part v0x2960210_0, 0, 1;
+L_0x29a20b0 .part v0x2960210_0, 2, 1;
+L_0x29a2290 .part v0x2960210_0, 0, 1;
+S_0x2928500 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2928410;
+ .timescale -9 -12;
+L_0x29a1ae0/d .functor NOT 1, L_0x29a1f50, C4<0>, C4<0>, C4<0>;
+L_0x29a1ae0 .delay (10000,10000,10000) L_0x29a1ae0/d;
+L_0x29a1b80/d .functor AND 1, L_0x29a1a40, L_0x29a1ae0, C4<1>, C4<1>;
+L_0x29a1b80 .delay (20000,20000,20000) L_0x29a1b80/d;
+L_0x29a1c70/d .functor AND 1, L_0x29a1270, L_0x29a1f50, C4<1>, C4<1>;
+L_0x29a1c70 .delay (20000,20000,20000) L_0x29a1c70/d;
+L_0x29a1d80/d .functor OR 1, L_0x29a1b80, L_0x29a1c70, C4<0>, C4<0>;
+L_0x29a1d80 .delay (20000,20000,20000) L_0x29a1d80/d;
+v0x29285f0_0 .net "S", 0 0, L_0x29a1f50; 1 drivers
+v0x29286b0_0 .alias "in0", 0 0, v0x2928d10_0;
+v0x2928750_0 .alias "in1", 0 0, v0x29291e0_0;
+v0x29287f0_0 .net "nS", 0 0, L_0x29a1ae0; 1 drivers
+v0x2928870_0 .net "out0", 0 0, L_0x29a1b80; 1 drivers
+v0x2928910_0 .net "out1", 0 0, L_0x29a1c70; 1 drivers
+v0x29289f0_0 .alias "outfinal", 0 0, v0x2928dc0_0;
+S_0x2927ea0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x29277b0;
+ .timescale -9 -12;
+L_0x29a2a60/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a2a60 .delay (10000,10000,10000) L_0x29a2a60/d;
+L_0x29a2b00/d .functor AND 1, L_0x29a2d90, L_0x29a2a60, C4<1>, C4<1>;
+L_0x29a2b00 .delay (20000,20000,20000) L_0x29a2b00/d;
+L_0x29a2c10/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a2c10 .delay (20000,20000,20000) L_0x29a2c10/d;
+L_0x29a30e0/d .functor OR 1, L_0x29a2b00, L_0x29a2c10, C4<0>, C4<0>;
+L_0x29a30e0 .delay (20000,20000,20000) L_0x29a30e0/d;
+v0x2927f90_0 .alias "S", 0 0, v0x293b720_0;
+v0x2928030_0 .net "in0", 0 0, L_0x29a2d90; 1 drivers
+v0x29280d0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2928170_0 .net "nS", 0 0, L_0x29a2a60; 1 drivers
+v0x29281f0_0 .net "out0", 0 0, L_0x29a2b00; 1 drivers
+v0x2928290_0 .net "out1", 0 0, L_0x29a2c10; 1 drivers
+v0x2928370_0 .net "outfinal", 0 0, L_0x29a30e0; 1 drivers
+S_0x2927920 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x29277b0;
+ .timescale -9 -12;
+L_0x29a2f10/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a2f10 .delay (10000,10000,10000) L_0x29a2f10/d;
+L_0x29a3020/d .functor AND 1, L_0x29a3270, L_0x29a2f10, C4<1>, C4<1>;
+L_0x29a3020 .delay (20000,20000,20000) L_0x29a3020/d;
+L_0x29a3620/d .functor AND 1, L_0x29a3360, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a3620 .delay (20000,20000,20000) L_0x29a3620/d;
+L_0x29a36c0/d .functor OR 1, L_0x29a3020, L_0x29a3620, C4<0>, C4<0>;
+L_0x29a36c0 .delay (20000,20000,20000) L_0x29a36c0/d;
+v0x2927a10_0 .alias "S", 0 0, v0x293b720_0;
+v0x2927a90_0 .net "in0", 0 0, L_0x29a3270; 1 drivers
+v0x2927b30_0 .net "in1", 0 0, L_0x29a3360; 1 drivers
+v0x2927bd0_0 .net "nS", 0 0, L_0x29a2f10; 1 drivers
+v0x2927c80_0 .net "out0", 0 0, L_0x29a3020; 1 drivers
+v0x2927d20_0 .net "out1", 0 0, L_0x29a3620; 1 drivers
+v0x2927e00_0 .net "outfinal", 0 0, L_0x29a36c0; 1 drivers
+S_0x2925b30 .scope generate, "sltbits[11]" "sltbits[11]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2925548 .param/l "i" 3 332, +C4<01011>;
+S_0x2926790 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2925b30;
+ .timescale -9 -12;
+L_0x29a3450/d .functor NOT 1, L_0x29a3a30, C4<0>, C4<0>, C4<0>;
+L_0x29a3450 .delay (10000,10000,10000) L_0x29a3450/d;
+L_0x29a41c0/d .functor NOT 1, L_0x29a4280, C4<0>, C4<0>, C4<0>;
+L_0x29a41c0 .delay (10000,10000,10000) L_0x29a41c0/d;
+L_0x29a4320/d .functor AND 1, L_0x29a4460, L_0x29a41c0, C4<1>, C4<1>;
+L_0x29a4320 .delay (20000,20000,20000) L_0x29a4320/d;
+L_0x29a4500/d .functor XOR 1, L_0x29a3990, L_0x29a3f50, C4<0>, C4<0>;
+L_0x29a4500 .delay (40000,40000,40000) L_0x29a4500/d;
+L_0x29a45f0/d .functor XOR 1, L_0x29a4500, L_0x29a3b60, C4<0>, C4<0>;
+L_0x29a45f0 .delay (40000,40000,40000) L_0x29a45f0/d;
+L_0x29a46e0/d .functor AND 1, L_0x29a3990, L_0x29a3f50, C4<1>, C4<1>;
+L_0x29a46e0 .delay (20000,20000,20000) L_0x29a46e0/d;
+L_0x29a4850/d .functor AND 1, L_0x29a4500, L_0x29a3b60, C4<1>, C4<1>;
+L_0x29a4850 .delay (20000,20000,20000) L_0x29a4850/d;
+L_0x29a4940/d .functor OR 1, L_0x29a46e0, L_0x29a4850, C4<0>, C4<0>;
+L_0x29a4940 .delay (20000,20000,20000) L_0x29a4940/d;
+v0x2926e10_0 .net "A", 0 0, L_0x29a3990; 1 drivers
+v0x2926ed0_0 .net "AandB", 0 0, L_0x29a46e0; 1 drivers
+v0x2926f70_0 .net "AddSubSLTSum", 0 0, L_0x29a45f0; 1 drivers
+v0x2927010_0 .net "AxorB", 0 0, L_0x29a4500; 1 drivers
+v0x2927090_0 .net "B", 0 0, L_0x29a3a30; 1 drivers
+v0x2927140_0 .net "BornB", 0 0, L_0x29a3f50; 1 drivers
+v0x2927200_0 .net "CINandAxorB", 0 0, L_0x29a4850; 1 drivers
+v0x2927280_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2927300_0 .net *"_s3", 0 0, L_0x29a4280; 1 drivers
+v0x2927380_0 .net *"_s5", 0 0, L_0x29a4460; 1 drivers
+v0x2927420_0 .net "carryin", 0 0, L_0x29a3b60; 1 drivers
+v0x29274c0_0 .net "carryout", 0 0, L_0x29a4940; 1 drivers
+v0x2927560_0 .net "nB", 0 0, L_0x29a3450; 1 drivers
+v0x2927610_0 .net "nCmd2", 0 0, L_0x29a41c0; 1 drivers
+v0x2927710_0 .net "subtract", 0 0, L_0x29a4320; 1 drivers
+L_0x29a4120 .part v0x2960210_0, 0, 1;
+L_0x29a4280 .part v0x2960210_0, 2, 1;
+L_0x29a4460 .part v0x2960210_0, 0, 1;
+S_0x2926880 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2926790;
+ .timescale -9 -12;
+L_0x29a3c70/d .functor NOT 1, L_0x29a4120, C4<0>, C4<0>, C4<0>;
+L_0x29a3c70 .delay (10000,10000,10000) L_0x29a3c70/d;
+L_0x29a3d30/d .functor AND 1, L_0x29a3a30, L_0x29a3c70, C4<1>, C4<1>;
+L_0x29a3d30 .delay (20000,20000,20000) L_0x29a3d30/d;
+L_0x29a3e40/d .functor AND 1, L_0x29a3450, L_0x29a4120, C4<1>, C4<1>;
+L_0x29a3e40 .delay (20000,20000,20000) L_0x29a3e40/d;
+L_0x29a3f50/d .functor OR 1, L_0x29a3d30, L_0x29a3e40, C4<0>, C4<0>;
+L_0x29a3f50 .delay (20000,20000,20000) L_0x29a3f50/d;
+v0x2926970_0 .net "S", 0 0, L_0x29a4120; 1 drivers
+v0x2926a30_0 .alias "in0", 0 0, v0x2927090_0;
+v0x2926ad0_0 .alias "in1", 0 0, v0x2927560_0;
+v0x2926b70_0 .net "nS", 0 0, L_0x29a3c70; 1 drivers
+v0x2926bf0_0 .net "out0", 0 0, L_0x29a3d30; 1 drivers
+v0x2926c90_0 .net "out1", 0 0, L_0x29a3e40; 1 drivers
+v0x2926d70_0 .alias "outfinal", 0 0, v0x2927140_0;
+S_0x2926220 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2925b30;
+ .timescale -9 -12;
+L_0x29a5030/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a5030 .delay (10000,10000,10000) L_0x29a5030/d;
+L_0x29a50b0/d .functor AND 1, L_0x29a5440, L_0x29a5030, C4<1>, C4<1>;
+L_0x29a50b0 .delay (20000,20000,20000) L_0x29a50b0/d;
+L_0x29a51c0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a51c0 .delay (20000,20000,20000) L_0x29a51c0/d;
+L_0x29a5260/d .functor OR 1, L_0x29a50b0, L_0x29a51c0, C4<0>, C4<0>;
+L_0x29a5260 .delay (20000,20000,20000) L_0x29a5260/d;
+v0x2926310_0 .alias "S", 0 0, v0x293b720_0;
+v0x29263b0_0 .net "in0", 0 0, L_0x29a5440; 1 drivers
+v0x2926450_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x29264f0_0 .net "nS", 0 0, L_0x29a5030; 1 drivers
+v0x2926570_0 .net "out0", 0 0, L_0x29a50b0; 1 drivers
+v0x2926610_0 .net "out1", 0 0, L_0x29a51c0; 1 drivers
+v0x29266f0_0 .net "outfinal", 0 0, L_0x29a5260; 1 drivers
+S_0x2925ca0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2925b30;
+ .timescale -9 -12;
+L_0x29a0ce0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a0ce0 .delay (10000,10000,10000) L_0x29a0ce0/d;
+L_0x29a4e30/d .functor AND 1, L_0x29a5a80, L_0x29a0ce0, C4<1>, C4<1>;
+L_0x29a4e30 .delay (20000,20000,20000) L_0x29a4e30/d;
+L_0x29a4f40/d .functor AND 1, L_0x28923f0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a4f40 .delay (20000,20000,20000) L_0x29a4f40/d;
+L_0x29a58f0/d .functor OR 1, L_0x29a4e30, L_0x29a4f40, C4<0>, C4<0>;
+L_0x29a58f0 .delay (20000,20000,20000) L_0x29a58f0/d;
+v0x2925d90_0 .alias "S", 0 0, v0x293b720_0;
+v0x2925e10_0 .net "in0", 0 0, L_0x29a5a80; 1 drivers
+v0x2925eb0_0 .net "in1", 0 0, L_0x28923f0; 1 drivers
+v0x2925f50_0 .net "nS", 0 0, L_0x29a0ce0; 1 drivers
+v0x2926000_0 .net "out0", 0 0, L_0x29a4e30; 1 drivers
+v0x29260a0_0 .net "out1", 0 0, L_0x29a4f40; 1 drivers
+v0x2926180_0 .net "outfinal", 0 0, L_0x29a58f0; 1 drivers
+S_0x2923eb0 .scope generate, "sltbits[12]" "sltbits[12]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x29238c8 .param/l "i" 3 332, +C4<01100>;
+S_0x2924b10 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2923eb0;
+ .timescale -9 -12;
+L_0x28924e0/d .functor NOT 1, L_0x29a6200, C4<0>, C4<0>, C4<0>;
+L_0x28924e0 .delay (10000,10000,10000) L_0x28924e0/d;
+L_0x29a6580/d .functor NOT 1, L_0x29a6620, C4<0>, C4<0>, C4<0>;
+L_0x29a6580 .delay (10000,10000,10000) L_0x29a6580/d;
+L_0x29a66c0/d .functor AND 1, L_0x29a6800, L_0x29a6580, C4<1>, C4<1>;
+L_0x29a66c0 .delay (20000,20000,20000) L_0x29a66c0/d;
+L_0x29a68a0/d .functor XOR 1, L_0x29a6160, L_0x29a6350, C4<0>, C4<0>;
+L_0x29a68a0 .delay (40000,40000,40000) L_0x29a68a0/d;
+L_0x29a6990/d .functor XOR 1, L_0x29a68a0, L_0x29a7360, C4<0>, C4<0>;
+L_0x29a6990 .delay (40000,40000,40000) L_0x29a6990/d;
+L_0x29a6a80/d .functor AND 1, L_0x29a6160, L_0x29a6350, C4<1>, C4<1>;
+L_0x29a6a80 .delay (20000,20000,20000) L_0x29a6a80/d;
+L_0x29a6c20/d .functor AND 1, L_0x29a68a0, L_0x29a7360, C4<1>, C4<1>;
+L_0x29a6c20 .delay (20000,20000,20000) L_0x29a6c20/d;
+L_0x29a6d10/d .functor OR 1, L_0x29a6a80, L_0x29a6c20, C4<0>, C4<0>;
+L_0x29a6d10 .delay (20000,20000,20000) L_0x29a6d10/d;
+v0x2925190_0 .net "A", 0 0, L_0x29a6160; 1 drivers
+v0x2925250_0 .net "AandB", 0 0, L_0x29a6a80; 1 drivers
+v0x29252f0_0 .net "AddSubSLTSum", 0 0, L_0x29a6990; 1 drivers
+v0x2925390_0 .net "AxorB", 0 0, L_0x29a68a0; 1 drivers
+v0x2925410_0 .net "B", 0 0, L_0x29a6200; 1 drivers
+v0x29254c0_0 .net "BornB", 0 0, L_0x29a6350; 1 drivers
+v0x2925580_0 .net "CINandAxorB", 0 0, L_0x29a6c20; 1 drivers
+v0x2925600_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2925680_0 .net *"_s3", 0 0, L_0x29a6620; 1 drivers
+v0x2925700_0 .net *"_s5", 0 0, L_0x29a6800; 1 drivers
+v0x29257a0_0 .net "carryin", 0 0, L_0x29a7360; 1 drivers
+v0x2925840_0 .net "carryout", 0 0, L_0x29a6d10; 1 drivers
+v0x29258e0_0 .net "nB", 0 0, L_0x28924e0; 1 drivers
+v0x2925990_0 .net "nCmd2", 0 0, L_0x29a6580; 1 drivers
+v0x2925a90_0 .net "subtract", 0 0, L_0x29a66c0; 1 drivers
+L_0x29a64e0 .part v0x2960210_0, 0, 1;
+L_0x29a6620 .part v0x2960210_0, 2, 1;
+L_0x29a6800 .part v0x2960210_0, 0, 1;
+S_0x2924c00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2924b10;
+ .timescale -9 -12;
+L_0x29a55e0/d .functor NOT 1, L_0x29a64e0, C4<0>, C4<0>, C4<0>;
+L_0x29a55e0 .delay (10000,10000,10000) L_0x29a55e0/d;
+L_0x29a56a0/d .functor AND 1, L_0x29a6200, L_0x29a55e0, C4<1>, C4<1>;
+L_0x29a56a0 .delay (20000,20000,20000) L_0x29a56a0/d;
+L_0x29a57b0/d .functor AND 1, L_0x28924e0, L_0x29a64e0, C4<1>, C4<1>;
+L_0x29a57b0 .delay (20000,20000,20000) L_0x29a57b0/d;
+L_0x29a6350/d .functor OR 1, L_0x29a56a0, L_0x29a57b0, C4<0>, C4<0>;
+L_0x29a6350 .delay (20000,20000,20000) L_0x29a6350/d;
+v0x2924cf0_0 .net "S", 0 0, L_0x29a64e0; 1 drivers
+v0x2924db0_0 .alias "in0", 0 0, v0x2925410_0;
+v0x2924e50_0 .alias "in1", 0 0, v0x29258e0_0;
+v0x2924ef0_0 .net "nS", 0 0, L_0x29a55e0; 1 drivers
+v0x2924f70_0 .net "out0", 0 0, L_0x29a56a0; 1 drivers
+v0x2925010_0 .net "out1", 0 0, L_0x29a57b0; 1 drivers
+v0x29250f0_0 .alias "outfinal", 0 0, v0x29254c0_0;
+S_0x29245a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2923eb0;
+ .timescale -9 -12;
+L_0x29a7400/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a7400 .delay (10000,10000,10000) L_0x29a7400/d;
+L_0x29a7480/d .functor AND 1, L_0x29a6f60, L_0x29a7400, C4<1>, C4<1>;
+L_0x29a7480 .delay (20000,20000,20000) L_0x29a7480/d;
+L_0x29a7590/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a7590 .delay (20000,20000,20000) L_0x29a7590/d;
+L_0x29a7630/d .functor OR 1, L_0x29a7480, L_0x29a7590, C4<0>, C4<0>;
+L_0x29a7630 .delay (20000,20000,20000) L_0x29a7630/d;
+v0x2924690_0 .alias "S", 0 0, v0x293b720_0;
+v0x2924730_0 .net "in0", 0 0, L_0x29a6f60; 1 drivers
+v0x29247d0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2924870_0 .net "nS", 0 0, L_0x29a7400; 1 drivers
+v0x29248f0_0 .net "out0", 0 0, L_0x29a7480; 1 drivers
+v0x2924990_0 .net "out1", 0 0, L_0x29a7590; 1 drivers
+v0x2924a70_0 .net "outfinal", 0 0, L_0x29a7630; 1 drivers
+S_0x2924020 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2923eb0;
+ .timescale -9 -12;
+L_0x29a70e0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a70e0 .delay (10000,10000,10000) L_0x29a70e0/d;
+L_0x29a71f0/d .functor AND 1, L_0x29a7810, L_0x29a70e0, C4<1>, C4<1>;
+L_0x29a71f0 .delay (20000,20000,20000) L_0x29a71f0/d;
+L_0x29a7300/d .functor AND 1, L_0x29a7900, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a7300 .delay (20000,20000,20000) L_0x29a7300/d;
+L_0x29a7c60/d .functor OR 1, L_0x29a71f0, L_0x29a7300, C4<0>, C4<0>;
+L_0x29a7c60 .delay (20000,20000,20000) L_0x29a7c60/d;
+v0x2924110_0 .alias "S", 0 0, v0x293b720_0;
+v0x2924190_0 .net "in0", 0 0, L_0x29a7810; 1 drivers
+v0x2924230_0 .net "in1", 0 0, L_0x29a7900; 1 drivers
+v0x29242d0_0 .net "nS", 0 0, L_0x29a70e0; 1 drivers
+v0x2924380_0 .net "out0", 0 0, L_0x29a71f0; 1 drivers
+v0x2924420_0 .net "out1", 0 0, L_0x29a7300; 1 drivers
+v0x2924500_0 .net "outfinal", 0 0, L_0x29a7c60; 1 drivers
+S_0x2922230 .scope generate, "sltbits[13]" "sltbits[13]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2921c48 .param/l "i" 3 332, +C4<01101>;
+S_0x2922e90 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2922230;
+ .timescale -9 -12;
+L_0x29a79f0/d .functor NOT 1, L_0x29a7fd0, C4<0>, C4<0>, C4<0>;
+L_0x29a79f0 .delay (10000,10000,10000) L_0x29a79f0/d;
+L_0x29a8720/d .functor NOT 1, L_0x29a87e0, C4<0>, C4<0>, C4<0>;
+L_0x29a8720 .delay (10000,10000,10000) L_0x29a8720/d;
+L_0x29a8880/d .functor AND 1, L_0x29a89c0, L_0x29a8720, C4<1>, C4<1>;
+L_0x29a8880 .delay (20000,20000,20000) L_0x29a8880/d;
+L_0x29a8a60/d .functor XOR 1, L_0x29a7f30, L_0x29a84b0, C4<0>, C4<0>;
+L_0x29a8a60 .delay (40000,40000,40000) L_0x29a8a60/d;
+L_0x29a8b50/d .functor XOR 1, L_0x29a8a60, L_0x29a8100, C4<0>, C4<0>;
+L_0x29a8b50 .delay (40000,40000,40000) L_0x29a8b50/d;
+L_0x29a8c70/d .functor AND 1, L_0x29a7f30, L_0x29a84b0, C4<1>, C4<1>;
+L_0x29a8c70 .delay (20000,20000,20000) L_0x29a8c70/d;
+L_0x29a8e10/d .functor AND 1, L_0x29a8a60, L_0x29a8100, C4<1>, C4<1>;
+L_0x29a8e10 .delay (20000,20000,20000) L_0x29a8e10/d;
+L_0x29a8f00/d .functor OR 1, L_0x29a8c70, L_0x29a8e10, C4<0>, C4<0>;
+L_0x29a8f00 .delay (20000,20000,20000) L_0x29a8f00/d;
+v0x2923510_0 .net "A", 0 0, L_0x29a7f30; 1 drivers
+v0x29235d0_0 .net "AandB", 0 0, L_0x29a8c70; 1 drivers
+v0x2923670_0 .net "AddSubSLTSum", 0 0, L_0x29a8b50; 1 drivers
+v0x2923710_0 .net "AxorB", 0 0, L_0x29a8a60; 1 drivers
+v0x2923790_0 .net "B", 0 0, L_0x29a7fd0; 1 drivers
+v0x2923840_0 .net "BornB", 0 0, L_0x29a84b0; 1 drivers
+v0x2923900_0 .net "CINandAxorB", 0 0, L_0x29a8e10; 1 drivers
+v0x2923980_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2923a00_0 .net *"_s3", 0 0, L_0x29a87e0; 1 drivers
+v0x2923a80_0 .net *"_s5", 0 0, L_0x29a89c0; 1 drivers
+v0x2923b20_0 .net "carryin", 0 0, L_0x29a8100; 1 drivers
+v0x2923bc0_0 .net "carryout", 0 0, L_0x29a8f00; 1 drivers
+v0x2923c60_0 .net "nB", 0 0, L_0x29a79f0; 1 drivers
+v0x2923d10_0 .net "nCmd2", 0 0, L_0x29a8720; 1 drivers
+v0x2923e10_0 .net "subtract", 0 0, L_0x29a8880; 1 drivers
+L_0x29a8680 .part v0x2960210_0, 0, 1;
+L_0x29a87e0 .part v0x2960210_0, 2, 1;
+L_0x29a89c0 .part v0x2960210_0, 0, 1;
+S_0x2922f80 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2922e90;
+ .timescale -9 -12;
+L_0x29a7bc0/d .functor NOT 1, L_0x29a8680, C4<0>, C4<0>, C4<0>;
+L_0x29a7bc0 .delay (10000,10000,10000) L_0x29a7bc0/d;
+L_0x29a82b0/d .functor AND 1, L_0x29a7fd0, L_0x29a7bc0, C4<1>, C4<1>;
+L_0x29a82b0 .delay (20000,20000,20000) L_0x29a82b0/d;
+L_0x29a83a0/d .functor AND 1, L_0x29a79f0, L_0x29a8680, C4<1>, C4<1>;
+L_0x29a83a0 .delay (20000,20000,20000) L_0x29a83a0/d;
+L_0x29a84b0/d .functor OR 1, L_0x29a82b0, L_0x29a83a0, C4<0>, C4<0>;
+L_0x29a84b0 .delay (20000,20000,20000) L_0x29a84b0/d;
+v0x2923070_0 .net "S", 0 0, L_0x29a8680; 1 drivers
+v0x2923130_0 .alias "in0", 0 0, v0x2923790_0;
+v0x29231d0_0 .alias "in1", 0 0, v0x2923c60_0;
+v0x2923270_0 .net "nS", 0 0, L_0x29a7bc0; 1 drivers
+v0x29232f0_0 .net "out0", 0 0, L_0x29a82b0; 1 drivers
+v0x2923390_0 .net "out1", 0 0, L_0x29a83a0; 1 drivers
+v0x2923470_0 .alias "outfinal", 0 0, v0x2923840_0;
+S_0x2922920 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2922230;
+ .timescale -9 -12;
+L_0x29a81a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a81a0 .delay (10000,10000,10000) L_0x29a81a0/d;
+L_0x29a96a0/d .functor AND 1, L_0x29a9a10, L_0x29a81a0, C4<1>, C4<1>;
+L_0x29a96a0 .delay (20000,20000,20000) L_0x29a96a0/d;
+L_0x29a9790/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a9790 .delay (20000,20000,20000) L_0x29a9790/d;
+L_0x29a9830/d .functor OR 1, L_0x29a96a0, L_0x29a9790, C4<0>, C4<0>;
+L_0x29a9830 .delay (20000,20000,20000) L_0x29a9830/d;
+v0x2922a10_0 .alias "S", 0 0, v0x293b720_0;
+v0x2922ab0_0 .net "in0", 0 0, L_0x29a9a10; 1 drivers
+v0x2922b50_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2922bf0_0 .net "nS", 0 0, L_0x29a81a0; 1 drivers
+v0x2922c70_0 .net "out0", 0 0, L_0x29a96a0; 1 drivers
+v0x2922d10_0 .net "out1", 0 0, L_0x29a9790; 1 drivers
+v0x2922df0_0 .net "outfinal", 0 0, L_0x29a9830; 1 drivers
+S_0x29223a0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2922230;
+ .timescale -9 -12;
+L_0x29a9350/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a9350 .delay (10000,10000,10000) L_0x29a9350/d;
+L_0x29a9460/d .functor AND 1, L_0x2996bc0, L_0x29a9350, C4<1>, C4<1>;
+L_0x29a9460 .delay (20000,20000,20000) L_0x29a9460/d;
+L_0x29a9570/d .functor AND 1, L_0x29a9b00, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a9570 .delay (20000,20000,20000) L_0x29a9570/d;
+L_0x29a9610/d .functor OR 1, L_0x29a9460, L_0x29a9570, C4<0>, C4<0>;
+L_0x29a9610 .delay (20000,20000,20000) L_0x29a9610/d;
+v0x2922490_0 .alias "S", 0 0, v0x293b720_0;
+v0x2922510_0 .net "in0", 0 0, L_0x2996bc0; 1 drivers
+v0x29225b0_0 .net "in1", 0 0, L_0x29a9b00; 1 drivers
+v0x2922650_0 .net "nS", 0 0, L_0x29a9350; 1 drivers
+v0x2922700_0 .net "out0", 0 0, L_0x29a9460; 1 drivers
+v0x29227a0_0 .net "out1", 0 0, L_0x29a9570; 1 drivers
+v0x2922880_0 .net "outfinal", 0 0, L_0x29a9610; 1 drivers
+S_0x29205b0 .scope generate, "sltbits[14]" "sltbits[14]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x291fea8 .param/l "i" 3 332, +C4<01110>;
+S_0x2921210 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x29205b0;
+ .timescale -9 -12;
+L_0x29a9bf0/d .functor NOT 1, L_0x29aa580, C4<0>, C4<0>, C4<0>;
+L_0x29a9bf0 .delay (10000,10000,10000) L_0x29a9bf0/d;
+L_0x29aaa40/d .functor NOT 1, L_0x29aaae0, C4<0>, C4<0>, C4<0>;
+L_0x29aaa40 .delay (10000,10000,10000) L_0x29aaa40/d;
+L_0x29aab80/d .functor AND 1, L_0x29aacc0, L_0x29aaa40, C4<1>, C4<1>;
+L_0x29aab80 .delay (20000,20000,20000) L_0x29aab80/d;
+L_0x29aad60/d .functor XOR 1, L_0x29aa4e0, L_0x29aa810, C4<0>, C4<0>;
+L_0x29aad60 .delay (40000,40000,40000) L_0x29aad60/d;
+L_0x29aae80/d .functor XOR 1, L_0x29aad60, L_0x29aa6b0, C4<0>, C4<0>;
+L_0x29aae80 .delay (40000,40000,40000) L_0x29aae80/d;
+L_0x29aafa0/d .functor AND 1, L_0x29aa4e0, L_0x29aa810, C4<1>, C4<1>;
+L_0x29aafa0 .delay (20000,20000,20000) L_0x29aafa0/d;
+L_0x29ab140/d .functor AND 1, L_0x29aad60, L_0x29aa6b0, C4<1>, C4<1>;
+L_0x29ab140 .delay (20000,20000,20000) L_0x29ab140/d;
+L_0x29ab230/d .functor OR 1, L_0x29aafa0, L_0x29ab140, C4<0>, C4<0>;
+L_0x29ab230 .delay (20000,20000,20000) L_0x29ab230/d;
+v0x2921890_0 .net "A", 0 0, L_0x29aa4e0; 1 drivers
+v0x2921950_0 .net "AandB", 0 0, L_0x29aafa0; 1 drivers
+v0x29219f0_0 .net "AddSubSLTSum", 0 0, L_0x29aae80; 1 drivers
+v0x2921a90_0 .net "AxorB", 0 0, L_0x29aad60; 1 drivers
+v0x2921b10_0 .net "B", 0 0, L_0x29aa580; 1 drivers
+v0x2921bc0_0 .net "BornB", 0 0, L_0x29aa810; 1 drivers
+v0x2921c80_0 .net "CINandAxorB", 0 0, L_0x29ab140; 1 drivers
+v0x2921d00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2921d80_0 .net *"_s3", 0 0, L_0x29aaae0; 1 drivers
+v0x2921e00_0 .net *"_s5", 0 0, L_0x29aacc0; 1 drivers
+v0x2921ea0_0 .net "carryin", 0 0, L_0x29aa6b0; 1 drivers
+v0x2921f40_0 .net "carryout", 0 0, L_0x29ab230; 1 drivers
+v0x2921fe0_0 .net "nB", 0 0, L_0x29a9bf0; 1 drivers
+v0x2922090_0 .net "nCmd2", 0 0, L_0x29aaa40; 1 drivers
+v0x2922190_0 .net "subtract", 0 0, L_0x29aab80; 1 drivers
+L_0x29aa9a0 .part v0x2960210_0, 0, 1;
+L_0x29aaae0 .part v0x2960210_0, 2, 1;
+L_0x29aacc0 .part v0x2960210_0, 0, 1;
+S_0x2921300 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2921210;
+ .timescale -9 -12;
+L_0x29a9da0/d .functor NOT 1, L_0x29aa9a0, C4<0>, C4<0>, C4<0>;
+L_0x29a9da0 .delay (10000,10000,10000) L_0x29a9da0/d;
+L_0x29a9e60/d .functor AND 1, L_0x29aa580, L_0x29a9da0, C4<1>, C4<1>;
+L_0x29a9e60 .delay (20000,20000,20000) L_0x29a9e60/d;
+L_0x29a4d10/d .functor AND 1, L_0x29a9bf0, L_0x29aa9a0, C4<1>, C4<1>;
+L_0x29a4d10 .delay (20000,20000,20000) L_0x29a4d10/d;
+L_0x29aa810/d .functor OR 1, L_0x29a9e60, L_0x29a4d10, C4<0>, C4<0>;
+L_0x29aa810 .delay (20000,20000,20000) L_0x29aa810/d;
+v0x29213f0_0 .net "S", 0 0, L_0x29aa9a0; 1 drivers
+v0x29214b0_0 .alias "in0", 0 0, v0x2921b10_0;
+v0x2921550_0 .alias "in1", 0 0, v0x2921fe0_0;
+v0x29215f0_0 .net "nS", 0 0, L_0x29a9da0; 1 drivers
+v0x2921670_0 .net "out0", 0 0, L_0x29a9e60; 1 drivers
+v0x2921710_0 .net "out1", 0 0, L_0x29a4d10; 1 drivers
+v0x29217f0_0 .alias "outfinal", 0 0, v0x2921bc0_0;
+S_0x2920ca0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x29205b0;
+ .timescale -9 -12;
+L_0x29ab930/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29ab930 .delay (10000,10000,10000) L_0x29ab930/d;
+L_0x29ab990/d .functor AND 1, L_0x29ab480, L_0x29ab930, C4<1>, C4<1>;
+L_0x29ab990 .delay (20000,20000,20000) L_0x29ab990/d;
+L_0x29aba80/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29aba80 .delay (20000,20000,20000) L_0x29aba80/d;
+L_0x29abb20/d .functor OR 1, L_0x29ab990, L_0x29aba80, C4<0>, C4<0>;
+L_0x29abb20 .delay (20000,20000,20000) L_0x29abb20/d;
+v0x2920d90_0 .alias "S", 0 0, v0x293b720_0;
+v0x2920e30_0 .net "in0", 0 0, L_0x29ab480; 1 drivers
+v0x2920ed0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2920f70_0 .net "nS", 0 0, L_0x29ab930; 1 drivers
+v0x2920ff0_0 .net "out0", 0 0, L_0x29ab990; 1 drivers
+v0x2921090_0 .net "out1", 0 0, L_0x29aba80; 1 drivers
+v0x2921170_0 .net "outfinal", 0 0, L_0x29abb20; 1 drivers
+S_0x2920720 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x29205b0;
+ .timescale -9 -12;
+L_0x29ab600/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29ab600 .delay (10000,10000,10000) L_0x29ab600/d;
+L_0x29ab730/d .functor AND 1, L_0x29abd30, L_0x29ab600, C4<1>, C4<1>;
+L_0x29ab730 .delay (20000,20000,20000) L_0x29ab730/d;
+L_0x29ab840/d .functor AND 1, L_0x29abe20, L_0x29d1680, C4<1>, C4<1>;
+L_0x29ab840 .delay (20000,20000,20000) L_0x29ab840/d;
+L_0x29ac1f0/d .functor OR 1, L_0x29ab730, L_0x29ab840, C4<0>, C4<0>;
+L_0x29ac1f0 .delay (20000,20000,20000) L_0x29ac1f0/d;
+v0x2920810_0 .alias "S", 0 0, v0x293b720_0;
+v0x2920890_0 .net "in0", 0 0, L_0x29abd30; 1 drivers
+v0x2920930_0 .net "in1", 0 0, L_0x29abe20; 1 drivers
+v0x29209d0_0 .net "nS", 0 0, L_0x29ab600; 1 drivers
+v0x2920a80_0 .net "out0", 0 0, L_0x29ab730; 1 drivers
+v0x2920b20_0 .net "out1", 0 0, L_0x29ab840; 1 drivers
+v0x2920c00_0 .net "outfinal", 0 0, L_0x29ac1f0; 1 drivers
+S_0x291e710 .scope generate, "sltbits[15]" "sltbits[15]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x291e128 .param/l "i" 3 332, +C4<01111>;
+S_0x291f470 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x291e710;
+ .timescale -9 -12;
+L_0x29abf10/d .functor NOT 1, L_0x29ac510, C4<0>, C4<0>, C4<0>;
+L_0x29abf10 .delay (10000,10000,10000) L_0x29abf10/d;
+L_0x29acc70/d .functor NOT 1, L_0x29acd30, C4<0>, C4<0>, C4<0>;
+L_0x29acc70 .delay (10000,10000,10000) L_0x29acc70/d;
+L_0x29acdd0/d .functor AND 1, L_0x29acf10, L_0x29acc70, C4<1>, C4<1>;
+L_0x29acdd0 .delay (20000,20000,20000) L_0x29acdd0/d;
+L_0x29acfb0/d .functor XOR 1, L_0x29ac470, L_0x29aca00, C4<0>, C4<0>;
+L_0x29acfb0 .delay (40000,40000,40000) L_0x29acfb0/d;
+L_0x29ad0a0/d .functor XOR 1, L_0x29acfb0, L_0x29ac640, C4<0>, C4<0>;
+L_0x29ad0a0 .delay (40000,40000,40000) L_0x29ad0a0/d;
+L_0x29ad1c0/d .functor AND 1, L_0x29ac470, L_0x29aca00, C4<1>, C4<1>;
+L_0x29ad1c0 .delay (20000,20000,20000) L_0x29ad1c0/d;
+L_0x29ad360/d .functor AND 1, L_0x29acfb0, L_0x29ac640, C4<1>, C4<1>;
+L_0x29ad360 .delay (20000,20000,20000) L_0x29ad360/d;
+L_0x29ad450/d .functor OR 1, L_0x29ad1c0, L_0x29ad360, C4<0>, C4<0>;
+L_0x29ad450 .delay (20000,20000,20000) L_0x29ad450/d;
+v0x291faf0_0 .net "A", 0 0, L_0x29ac470; 1 drivers
+v0x291fbb0_0 .net "AandB", 0 0, L_0x29ad1c0; 1 drivers
+v0x291fc50_0 .net "AddSubSLTSum", 0 0, L_0x29ad0a0; 1 drivers
+v0x291fcf0_0 .net "AxorB", 0 0, L_0x29acfb0; 1 drivers
+v0x291fd70_0 .net "B", 0 0, L_0x29ac510; 1 drivers
+v0x291fe20_0 .net "BornB", 0 0, L_0x29aca00; 1 drivers
+v0x291fee0_0 .net "CINandAxorB", 0 0, L_0x29ad360; 1 drivers
+v0x291ff60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2920030_0 .net *"_s3", 0 0, L_0x29acd30; 1 drivers
+v0x29200b0_0 .net *"_s5", 0 0, L_0x29acf10; 1 drivers
+v0x29201b0_0 .net "carryin", 0 0, L_0x29ac640; 1 drivers
+v0x2920250_0 .net "carryout", 0 0, L_0x29ad450; 1 drivers
+v0x2920360_0 .net "nB", 0 0, L_0x29abf10; 1 drivers
+v0x2920410_0 .net "nCmd2", 0 0, L_0x29acc70; 1 drivers
+v0x2920510_0 .net "subtract", 0 0, L_0x29acdd0; 1 drivers
+L_0x29acbd0 .part v0x2960210_0, 0, 1;
+L_0x29acd30 .part v0x2960210_0, 2, 1;
+L_0x29acf10 .part v0x2960210_0, 0, 1;
+S_0x291f560 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x291f470;
+ .timescale -9 -12;
+L_0x29ac0e0/d .functor NOT 1, L_0x29acbd0, C4<0>, C4<0>, C4<0>;
+L_0x29ac0e0 .delay (10000,10000,10000) L_0x29ac0e0/d;
+L_0x29ac860/d .functor AND 1, L_0x29ac510, L_0x29ac0e0, C4<1>, C4<1>;
+L_0x29ac860 .delay (20000,20000,20000) L_0x29ac860/d;
+L_0x29ac910/d .functor AND 1, L_0x29abf10, L_0x29acbd0, C4<1>, C4<1>;
+L_0x29ac910 .delay (20000,20000,20000) L_0x29ac910/d;
+L_0x29aca00/d .functor OR 1, L_0x29ac860, L_0x29ac910, C4<0>, C4<0>;
+L_0x29aca00 .delay (20000,20000,20000) L_0x29aca00/d;
+v0x291f650_0 .net "S", 0 0, L_0x29acbd0; 1 drivers
+v0x291f710_0 .alias "in0", 0 0, v0x291fd70_0;
+v0x291f7b0_0 .alias "in1", 0 0, v0x2920360_0;
+v0x291f850_0 .net "nS", 0 0, L_0x29ac0e0; 1 drivers
+v0x291f8d0_0 .net "out0", 0 0, L_0x29ac860; 1 drivers
+v0x291f970_0 .net "out1", 0 0, L_0x29ac910; 1 drivers
+v0x291fa50_0 .alias "outfinal", 0 0, v0x291fe20_0;
+S_0x291ef80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x291e710;
+ .timescale -9 -12;
+L_0x29ac6e0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29ac6e0 .delay (10000,10000,10000) L_0x29ac6e0/d;
+L_0x29ac780/d .functor AND 1, L_0x29adf70, L_0x29ac6e0, C4<1>, C4<1>;
+L_0x29ac780 .delay (20000,20000,20000) L_0x29ac780/d;
+L_0x29adcf0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29adcf0 .delay (20000,20000,20000) L_0x29adcf0/d;
+L_0x29add90/d .functor OR 1, L_0x29ac780, L_0x29adcf0, C4<0>, C4<0>;
+L_0x29add90 .delay (20000,20000,20000) L_0x29add90/d;
+v0x291f070_0 .alias "S", 0 0, v0x293b720_0;
+v0x291f0f0_0 .net "in0", 0 0, L_0x29adf70; 1 drivers
+v0x291f170_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x291f1f0_0 .net "nS", 0 0, L_0x29ac6e0; 1 drivers
+v0x291f270_0 .net "out0", 0 0, L_0x29ac780; 1 drivers
+v0x291f2f0_0 .net "out1", 0 0, L_0x29adcf0; 1 drivers
+v0x291f3d0_0 .net "outfinal", 0 0, L_0x29add90; 1 drivers
+S_0x291e880 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x291e710;
+ .timescale -9 -12;
+L_0x29ad8b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29ad8b0 .delay (10000,10000,10000) L_0x29ad8b0/d;
+L_0x29ad9c0/d .functor AND 1, L_0x29ae670, L_0x29ad8b0, C4<1>, C4<1>;
+L_0x29ad9c0 .delay (20000,20000,20000) L_0x29ad9c0/d;
+L_0x29adad0/d .functor AND 1, L_0x29ae060, L_0x29d1680, C4<1>, C4<1>;
+L_0x29adad0 .delay (20000,20000,20000) L_0x29adad0/d;
+L_0x29adb70/d .functor OR 1, L_0x29ad9c0, L_0x29adad0, C4<0>, C4<0>;
+L_0x29adb70 .delay (20000,20000,20000) L_0x29adb70/d;
+v0x291e970_0 .alias "S", 0 0, v0x293b720_0;
+v0x28f04c0_0 .net "in0", 0 0, L_0x29ae670; 1 drivers
+v0x28f0560_0 .net "in1", 0 0, L_0x29ae060; 1 drivers
+v0x28f0600_0 .net "nS", 0 0, L_0x29ad8b0; 1 drivers
+v0x291ee00_0 .net "out0", 0 0, L_0x29ad9c0; 1 drivers
+v0x291ee80_0 .net "out1", 0 0, L_0x29adad0; 1 drivers
+v0x291ef00_0 .net "outfinal", 0 0, L_0x29adb70; 1 drivers
+S_0x291ca90 .scope generate, "sltbits[16]" "sltbits[16]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x291c4a8 .param/l "i" 3 332, +C4<010000>;
+S_0x291d6f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x291ca90;
+ .timescale -9 -12;
+L_0x29ae150/d .functor NOT 1, L_0x29ae9e0, C4<0>, C4<0>, C4<0>;
+L_0x29ae150 .delay (10000,10000,10000) L_0x29ae150/d;
+L_0x29aeec0/d .functor NOT 1, L_0x29aef60, C4<0>, C4<0>, C4<0>;
+L_0x29aeec0 .delay (10000,10000,10000) L_0x29aeec0/d;
+L_0x29af000/d .functor AND 1, L_0x29af140, L_0x29aeec0, C4<1>, C4<1>;
+L_0x29af000 .delay (20000,20000,20000) L_0x29af000/d;
+L_0x29af1e0/d .functor XOR 1, L_0x29ae940, L_0x29aec90, C4<0>, C4<0>;
+L_0x29af1e0 .delay (40000,40000,40000) L_0x29af1e0/d;
+L_0x29af2d0/d .functor XOR 1, L_0x29af1e0, L_0x29aeb10, C4<0>, C4<0>;
+L_0x29af2d0 .delay (40000,40000,40000) L_0x29af2d0/d;
+L_0x29af3c0/d .functor AND 1, L_0x29ae940, L_0x29aec90, C4<1>, C4<1>;
+L_0x29af3c0 .delay (20000,20000,20000) L_0x29af3c0/d;
+L_0x29af560/d .functor AND 1, L_0x29af1e0, L_0x29aeb10, C4<1>, C4<1>;
+L_0x29af560 .delay (20000,20000,20000) L_0x29af560/d;
+L_0x29af650/d .functor OR 1, L_0x29af3c0, L_0x29af560, C4<0>, C4<0>;
+L_0x29af650 .delay (20000,20000,20000) L_0x29af650/d;
+v0x291dd70_0 .net "A", 0 0, L_0x29ae940; 1 drivers
+v0x291de30_0 .net "AandB", 0 0, L_0x29af3c0; 1 drivers
+v0x291ded0_0 .net "AddSubSLTSum", 0 0, L_0x29af2d0; 1 drivers
+v0x291df70_0 .net "AxorB", 0 0, L_0x29af1e0; 1 drivers
+v0x291dff0_0 .net "B", 0 0, L_0x29ae9e0; 1 drivers
+v0x291e0a0_0 .net "BornB", 0 0, L_0x29aec90; 1 drivers
+v0x291e160_0 .net "CINandAxorB", 0 0, L_0x29af560; 1 drivers
+v0x291e1e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x291e260_0 .net *"_s3", 0 0, L_0x29aef60; 1 drivers
+v0x291e2e0_0 .net *"_s5", 0 0, L_0x29af140; 1 drivers
+v0x291e380_0 .net "carryin", 0 0, L_0x29aeb10; 1 drivers
+v0x291e420_0 .net "carryout", 0 0, L_0x29af650; 1 drivers
+v0x291e4c0_0 .net "nB", 0 0, L_0x29ae150; 1 drivers
+v0x291e570_0 .net "nCmd2", 0 0, L_0x29aeec0; 1 drivers
+v0x291e670_0 .net "subtract", 0 0, L_0x29af000; 1 drivers
+L_0x29aee20 .part v0x2960210_0, 0, 1;
+L_0x29aef60 .part v0x2960210_0, 2, 1;
+L_0x29af140 .part v0x2960210_0, 0, 1;
+S_0x291d7e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x291d6f0;
+ .timescale -9 -12;
+L_0x29ae2e0/d .functor NOT 1, L_0x29aee20, C4<0>, C4<0>, C4<0>;
+L_0x29ae2e0 .delay (10000,10000,10000) L_0x29ae2e0/d;
+L_0x29ae3a0/d .functor AND 1, L_0x29ae9e0, L_0x29ae2e0, C4<1>, C4<1>;
+L_0x29ae3a0 .delay (20000,20000,20000) L_0x29ae3a0/d;
+L_0x29ae4b0/d .functor AND 1, L_0x29ae150, L_0x29aee20, C4<1>, C4<1>;
+L_0x29ae4b0 .delay (20000,20000,20000) L_0x29ae4b0/d;
+L_0x29aec90/d .functor OR 1, L_0x29ae3a0, L_0x29ae4b0, C4<0>, C4<0>;
+L_0x29aec90 .delay (20000,20000,20000) L_0x29aec90/d;
+v0x291d8d0_0 .net "S", 0 0, L_0x29aee20; 1 drivers
+v0x291d990_0 .alias "in0", 0 0, v0x291dff0_0;
+v0x291da30_0 .alias "in1", 0 0, v0x291e4c0_0;
+v0x291dad0_0 .net "nS", 0 0, L_0x29ae2e0; 1 drivers
+v0x291db50_0 .net "out0", 0 0, L_0x29ae3a0; 1 drivers
+v0x291dbf0_0 .net "out1", 0 0, L_0x29ae4b0; 1 drivers
+v0x291dcd0_0 .alias "outfinal", 0 0, v0x291e0a0_0;
+S_0x291d180 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x291ca90;
+ .timescale -9 -12;
+L_0x29aebb0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29aebb0 .delay (10000,10000,10000) L_0x29aebb0/d;
+L_0x299ea60/d .functor AND 1, L_0x29af8a0, L_0x29aebb0, C4<1>, C4<1>;
+L_0x299ea60 .delay (20000,20000,20000) L_0x299ea60/d;
+L_0x299eb30/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x299eb30 .delay (20000,20000,20000) L_0x299eb30/d;
+L_0x299ebd0/d .functor OR 1, L_0x299ea60, L_0x299eb30, C4<0>, C4<0>;
+L_0x299ebd0 .delay (20000,20000,20000) L_0x299ebd0/d;
+v0x291d270_0 .alias "S", 0 0, v0x293b720_0;
+v0x291d310_0 .net "in0", 0 0, L_0x29af8a0; 1 drivers
+v0x291d3b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x291d450_0 .net "nS", 0 0, L_0x29aebb0; 1 drivers
+v0x291d4d0_0 .net "out0", 0 0, L_0x299ea60; 1 drivers
+v0x291d570_0 .net "out1", 0 0, L_0x299eb30; 1 drivers
+v0x291d650_0 .net "outfinal", 0 0, L_0x299ebd0; 1 drivers
+S_0x291cc00 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x291ca90;
+ .timescale -9 -12;
+L_0x299f0b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x299f0b0 .delay (10000,10000,10000) L_0x299f0b0/d;
+L_0x299f1a0/d .functor AND 1, L_0x29b0350, L_0x299f0b0, C4<1>, C4<1>;
+L_0x299f1a0 .delay (20000,20000,20000) L_0x299f1a0/d;
+L_0x29b0910/d .functor AND 1, L_0x29b0440, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b0910 .delay (20000,20000,20000) L_0x29b0910/d;
+L_0x29b09b0/d .functor OR 1, L_0x299f1a0, L_0x29b0910, C4<0>, C4<0>;
+L_0x29b09b0 .delay (20000,20000,20000) L_0x29b09b0/d;
+v0x291ccf0_0 .alias "S", 0 0, v0x293b720_0;
+v0x291cd70_0 .net "in0", 0 0, L_0x29b0350; 1 drivers
+v0x291ce10_0 .net "in1", 0 0, L_0x29b0440; 1 drivers
+v0x291ceb0_0 .net "nS", 0 0, L_0x299f0b0; 1 drivers
+v0x291cf60_0 .net "out0", 0 0, L_0x299f1a0; 1 drivers
+v0x291d000_0 .net "out1", 0 0, L_0x29b0910; 1 drivers
+v0x291d0e0_0 .net "outfinal", 0 0, L_0x29b09b0; 1 drivers
+S_0x291ae10 .scope generate, "sltbits[17]" "sltbits[17]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x291a828 .param/l "i" 3 332, +C4<010001>;
+S_0x291ba70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x291ae10;
+ .timescale -9 -12;
+L_0x29b0530/d .functor NOT 1, L_0x29b0d20, C4<0>, C4<0>, C4<0>;
+L_0x29b0530 .delay (10000,10000,10000) L_0x29b0530/d;
+L_0x29b1470/d .functor NOT 1, L_0x29b1530, C4<0>, C4<0>, C4<0>;
+L_0x29b1470 .delay (10000,10000,10000) L_0x29b1470/d;
+L_0x29b15d0/d .functor AND 1, L_0x29b1710, L_0x29b1470, C4<1>, C4<1>;
+L_0x29b15d0 .delay (20000,20000,20000) L_0x29b15d0/d;
+L_0x29b17b0/d .functor XOR 1, L_0x29b0c80, L_0x29b1220, C4<0>, C4<0>;
+L_0x29b17b0 .delay (40000,40000,40000) L_0x29b17b0/d;
+L_0x29b18a0/d .functor XOR 1, L_0x29b17b0, L_0x29b0e50, C4<0>, C4<0>;
+L_0x29b18a0 .delay (40000,40000,40000) L_0x29b18a0/d;
+L_0x29b19c0/d .functor AND 1, L_0x29b0c80, L_0x29b1220, C4<1>, C4<1>;
+L_0x29b19c0 .delay (20000,20000,20000) L_0x29b19c0/d;
+L_0x29b1b60/d .functor AND 1, L_0x29b17b0, L_0x29b0e50, C4<1>, C4<1>;
+L_0x29b1b60 .delay (20000,20000,20000) L_0x29b1b60/d;
+L_0x29b1c50/d .functor OR 1, L_0x29b19c0, L_0x29b1b60, C4<0>, C4<0>;
+L_0x29b1c50 .delay (20000,20000,20000) L_0x29b1c50/d;
+v0x291c0f0_0 .net "A", 0 0, L_0x29b0c80; 1 drivers
+v0x291c1b0_0 .net "AandB", 0 0, L_0x29b19c0; 1 drivers
+v0x291c250_0 .net "AddSubSLTSum", 0 0, L_0x29b18a0; 1 drivers
+v0x291c2f0_0 .net "AxorB", 0 0, L_0x29b17b0; 1 drivers
+v0x291c370_0 .net "B", 0 0, L_0x29b0d20; 1 drivers
+v0x291c420_0 .net "BornB", 0 0, L_0x29b1220; 1 drivers
+v0x291c4e0_0 .net "CINandAxorB", 0 0, L_0x29b1b60; 1 drivers
+v0x291c560_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x291c5e0_0 .net *"_s3", 0 0, L_0x29b1530; 1 drivers
+v0x291c660_0 .net *"_s5", 0 0, L_0x29b1710; 1 drivers
+v0x291c700_0 .net "carryin", 0 0, L_0x29b0e50; 1 drivers
+v0x291c7a0_0 .net "carryout", 0 0, L_0x29b1c50; 1 drivers
+v0x291c840_0 .net "nB", 0 0, L_0x29b0530; 1 drivers
+v0x291c8f0_0 .net "nCmd2", 0 0, L_0x29b1470; 1 drivers
+v0x291c9f0_0 .net "subtract", 0 0, L_0x29b15d0; 1 drivers
+L_0x29b13d0 .part v0x2960210_0, 0, 1;
+L_0x29b1530 .part v0x2960210_0, 2, 1;
+L_0x29b1710 .part v0x2960210_0, 0, 1;
+S_0x291bb60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x291ba70;
+ .timescale -9 -12;
+L_0x29b0700/d .functor NOT 1, L_0x29b13d0, C4<0>, C4<0>, C4<0>;
+L_0x29b0700 .delay (10000,10000,10000) L_0x29b0700/d;
+L_0x29b07c0/d .functor AND 1, L_0x29b0d20, L_0x29b0700, C4<1>, C4<1>;
+L_0x29b07c0 .delay (20000,20000,20000) L_0x29b07c0/d;
+L_0x29b1170/d .functor AND 1, L_0x29b0530, L_0x29b13d0, C4<1>, C4<1>;
+L_0x29b1170 .delay (20000,20000,20000) L_0x29b1170/d;
+L_0x29b1220/d .functor OR 1, L_0x29b07c0, L_0x29b1170, C4<0>, C4<0>;
+L_0x29b1220 .delay (20000,20000,20000) L_0x29b1220/d;
+v0x291bc50_0 .net "S", 0 0, L_0x29b13d0; 1 drivers
+v0x291bd10_0 .alias "in0", 0 0, v0x291c370_0;
+v0x291bdb0_0 .alias "in1", 0 0, v0x291c840_0;
+v0x291be50_0 .net "nS", 0 0, L_0x29b0700; 1 drivers
+v0x291bed0_0 .net "out0", 0 0, L_0x29b07c0; 1 drivers
+v0x291bf70_0 .net "out1", 0 0, L_0x29b1170; 1 drivers
+v0x291c050_0 .alias "outfinal", 0 0, v0x291c420_0;
+S_0x291b500 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x291ae10;
+ .timescale -9 -12;
+L_0x29b0ef0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29b0ef0 .delay (10000,10000,10000) L_0x29b0ef0/d;
+L_0x29b0f70/d .functor AND 1, L_0x298d4a0, L_0x29b0ef0, C4<1>, C4<1>;
+L_0x29b0f70 .delay (20000,20000,20000) L_0x29b0f70/d;
+L_0x29b1080/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b1080 .delay (20000,20000,20000) L_0x29b1080/d;
+L_0x298d2c0/d .functor OR 1, L_0x29b0f70, L_0x29b1080, C4<0>, C4<0>;
+L_0x298d2c0 .delay (20000,20000,20000) L_0x298d2c0/d;
+v0x291b5f0_0 .alias "S", 0 0, v0x293b720_0;
+v0x291b690_0 .net "in0", 0 0, L_0x298d4a0; 1 drivers
+v0x291b730_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x291b7d0_0 .net "nS", 0 0, L_0x29b0ef0; 1 drivers
+v0x291b850_0 .net "out0", 0 0, L_0x29b0f70; 1 drivers
+v0x291b8f0_0 .net "out1", 0 0, L_0x29b1080; 1 drivers
+v0x291b9d0_0 .net "outfinal", 0 0, L_0x298d2c0; 1 drivers
+S_0x291af80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x291ae10;
+ .timescale -9 -12;
+L_0x298d6c0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x298d6c0 .delay (10000,10000,10000) L_0x298d6c0/d;
+L_0x298d7f0/d .functor AND 1, L_0x29b2030, L_0x298d6c0, C4<1>, C4<1>;
+L_0x298d7f0 .delay (20000,20000,20000) L_0x298d7f0/d;
+L_0x298d900/d .functor AND 1, L_0x29b2120, L_0x29d1680, C4<1>, C4<1>;
+L_0x298d900 .delay (20000,20000,20000) L_0x298d900/d;
+L_0x298d9a0/d .functor OR 1, L_0x298d7f0, L_0x298d900, C4<0>, C4<0>;
+L_0x298d9a0 .delay (20000,20000,20000) L_0x298d9a0/d;
+v0x291b070_0 .alias "S", 0 0, v0x293b720_0;
+v0x291b0f0_0 .net "in0", 0 0, L_0x29b2030; 1 drivers
+v0x291b190_0 .net "in1", 0 0, L_0x29b2120; 1 drivers
+v0x291b230_0 .net "nS", 0 0, L_0x298d6c0; 1 drivers
+v0x291b2e0_0 .net "out0", 0 0, L_0x298d7f0; 1 drivers
+v0x291b380_0 .net "out1", 0 0, L_0x298d900; 1 drivers
+v0x291b460_0 .net "outfinal", 0 0, L_0x298d9a0; 1 drivers
+S_0x2919190 .scope generate, "sltbits[18]" "sltbits[18]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2918ba8 .param/l "i" 3 332, +C4<010010>;
+S_0x2919df0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2919190;
+ .timescale -9 -12;
+L_0x29b2210/d .functor NOT 1, L_0x29b37e0, C4<0>, C4<0>, C4<0>;
+L_0x29b2210 .delay (10000,10000,10000) L_0x29b2210/d;
+L_0x29b3ea0/d .functor NOT 1, L_0x29b3f60, C4<0>, C4<0>, C4<0>;
+L_0x29b3ea0 .delay (10000,10000,10000) L_0x29b3ea0/d;
+L_0x29b4000/d .functor AND 1, L_0x29b4140, L_0x29b3ea0, C4<1>, C4<1>;
+L_0x29b4000 .delay (20000,20000,20000) L_0x29b4000/d;
+L_0x29b41e0/d .functor XOR 1, L_0x29b3740, L_0x29b3c30, C4<0>, C4<0>;
+L_0x29b41e0 .delay (40000,40000,40000) L_0x29b41e0/d;
+L_0x29b42d0/d .functor XOR 1, L_0x29b41e0, L_0x29b3910, C4<0>, C4<0>;
+L_0x29b42d0 .delay (40000,40000,40000) L_0x29b42d0/d;
+L_0x29b43c0/d .functor AND 1, L_0x29b3740, L_0x29b3c30, C4<1>, C4<1>;
+L_0x29b43c0 .delay (20000,20000,20000) L_0x29b43c0/d;
+L_0x29b4530/d .functor AND 1, L_0x29b41e0, L_0x29b3910, C4<1>, C4<1>;
+L_0x29b4530 .delay (20000,20000,20000) L_0x29b4530/d;
+L_0x29b4620/d .functor OR 1, L_0x29b43c0, L_0x29b4530, C4<0>, C4<0>;
+L_0x29b4620 .delay (20000,20000,20000) L_0x29b4620/d;
+v0x291a470_0 .net "A", 0 0, L_0x29b3740; 1 drivers
+v0x291a530_0 .net "AandB", 0 0, L_0x29b43c0; 1 drivers
+v0x291a5d0_0 .net "AddSubSLTSum", 0 0, L_0x29b42d0; 1 drivers
+v0x291a670_0 .net "AxorB", 0 0, L_0x29b41e0; 1 drivers
+v0x291a6f0_0 .net "B", 0 0, L_0x29b37e0; 1 drivers
+v0x291a7a0_0 .net "BornB", 0 0, L_0x29b3c30; 1 drivers
+v0x291a860_0 .net "CINandAxorB", 0 0, L_0x29b4530; 1 drivers
+v0x291a8e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x291a960_0 .net *"_s3", 0 0, L_0x29b3f60; 1 drivers
+v0x291a9e0_0 .net *"_s5", 0 0, L_0x29b4140; 1 drivers
+v0x291aa80_0 .net "carryin", 0 0, L_0x29b3910; 1 drivers
+v0x291ab20_0 .net "carryout", 0 0, L_0x29b4620; 1 drivers
+v0x291abc0_0 .net "nB", 0 0, L_0x29b2210; 1 drivers
+v0x291ac70_0 .net "nCmd2", 0 0, L_0x29b3ea0; 1 drivers
+v0x291ad70_0 .net "subtract", 0 0, L_0x29b4000; 1 drivers
+L_0x29b3e00 .part v0x2960210_0, 0, 1;
+L_0x29b3f60 .part v0x2960210_0, 2, 1;
+L_0x29b4140 .part v0x2960210_0, 0, 1;
+S_0x2919ee0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2919df0;
+ .timescale -9 -12;
+L_0x29b23a0/d .functor NOT 1, L_0x29b3e00, C4<0>, C4<0>, C4<0>;
+L_0x29b23a0 .delay (10000,10000,10000) L_0x29b23a0/d;
+L_0x29b2420/d .functor AND 1, L_0x29b37e0, L_0x29b23a0, C4<1>, C4<1>;
+L_0x29b2420 .delay (20000,20000,20000) L_0x29b2420/d;
+L_0x29b3b40/d .functor AND 1, L_0x29b2210, L_0x29b3e00, C4<1>, C4<1>;
+L_0x29b3b40 .delay (20000,20000,20000) L_0x29b3b40/d;
+L_0x29b3c30/d .functor OR 1, L_0x29b2420, L_0x29b3b40, C4<0>, C4<0>;
+L_0x29b3c30 .delay (20000,20000,20000) L_0x29b3c30/d;
+v0x2919fd0_0 .net "S", 0 0, L_0x29b3e00; 1 drivers
+v0x291a090_0 .alias "in0", 0 0, v0x291a6f0_0;
+v0x291a130_0 .alias "in1", 0 0, v0x291abc0_0;
+v0x291a1d0_0 .net "nS", 0 0, L_0x29b23a0; 1 drivers
+v0x291a250_0 .net "out0", 0 0, L_0x29b2420; 1 drivers
+v0x291a2f0_0 .net "out1", 0 0, L_0x29b3b40; 1 drivers
+v0x291a3d0_0 .alias "outfinal", 0 0, v0x291a7a0_0;
+S_0x2919880 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2919190;
+ .timescale -9 -12;
+L_0x29b39b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29b39b0 .delay (10000,10000,10000) L_0x29b39b0/d;
+L_0x29b3a50/d .functor AND 1, L_0x29794c0, L_0x29b39b0, C4<1>, C4<1>;
+L_0x29b3a50 .delay (20000,20000,20000) L_0x29b3a50/d;
+L_0x2979240/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x2979240 .delay (20000,20000,20000) L_0x2979240/d;
+L_0x29792e0/d .functor OR 1, L_0x29b3a50, L_0x2979240, C4<0>, C4<0>;
+L_0x29792e0 .delay (20000,20000,20000) L_0x29792e0/d;
+v0x2919970_0 .alias "S", 0 0, v0x293b720_0;
+v0x2919a10_0 .net "in0", 0 0, L_0x29794c0; 1 drivers
+v0x2919ab0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2919b50_0 .net "nS", 0 0, L_0x29b39b0; 1 drivers
+v0x2919bd0_0 .net "out0", 0 0, L_0x29b3a50; 1 drivers
+v0x2919c70_0 .net "out1", 0 0, L_0x2979240; 1 drivers
+v0x2919d50_0 .net "outfinal", 0 0, L_0x29792e0; 1 drivers
+S_0x2919300 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2919190;
+ .timescale -9 -12;
+L_0x2978ad0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2978ad0 .delay (10000,10000,10000) L_0x2978ad0/d;
+L_0x2978be0/d .functor AND 1, L_0x29b4960, L_0x2978ad0, C4<1>, C4<1>;
+L_0x2978be0 .delay (20000,20000,20000) L_0x2978be0/d;
+L_0x2978cf0/d .functor AND 1, L_0x29b4a50, L_0x29d1680, C4<1>, C4<1>;
+L_0x2978cf0 .delay (20000,20000,20000) L_0x2978cf0/d;
+L_0x2978d90/d .functor OR 1, L_0x2978be0, L_0x2978cf0, C4<0>, C4<0>;
+L_0x2978d90 .delay (20000,20000,20000) L_0x2978d90/d;
+v0x29193f0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2919470_0 .net "in0", 0 0, L_0x29b4960; 1 drivers
+v0x2919510_0 .net "in1", 0 0, L_0x29b4a50; 1 drivers
+v0x29195b0_0 .net "nS", 0 0, L_0x2978ad0; 1 drivers
+v0x2919660_0 .net "out0", 0 0, L_0x2978be0; 1 drivers
+v0x2919700_0 .net "out1", 0 0, L_0x2978cf0; 1 drivers
+v0x29197e0_0 .net "outfinal", 0 0, L_0x2978d90; 1 drivers
+S_0x2917510 .scope generate, "sltbits[19]" "sltbits[19]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2916f28 .param/l "i" 3 332, +C4<010011>;
+S_0x2918170 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2917510;
+ .timescale -9 -12;
+L_0x29b4b40/d .functor NOT 1, L_0x29b6020, C4<0>, C4<0>, C4<0>;
+L_0x29b4b40 .delay (10000,10000,10000) L_0x29b4b40/d;
+L_0x29b68a0/d .functor NOT 1, L_0x29b6960, C4<0>, C4<0>, C4<0>;
+L_0x29b68a0 .delay (10000,10000,10000) L_0x29b68a0/d;
+L_0x29b6a00/d .functor AND 1, L_0x29b6b40, L_0x29b68a0, C4<1>, C4<1>;
+L_0x29b6a00 .delay (20000,20000,20000) L_0x29b6a00/d;
+L_0x29b6be0/d .functor XOR 1, L_0x29b5f80, L_0x29b6630, C4<0>, C4<0>;
+L_0x29b6be0 .delay (40000,40000,40000) L_0x29b6be0/d;
+L_0x29b6cd0/d .functor XOR 1, L_0x29b6be0, L_0x29b6150, C4<0>, C4<0>;
+L_0x29b6cd0 .delay (40000,40000,40000) L_0x29b6cd0/d;
+L_0x29b6dc0/d .functor AND 1, L_0x29b5f80, L_0x29b6630, C4<1>, C4<1>;
+L_0x29b6dc0 .delay (20000,20000,20000) L_0x29b6dc0/d;
+L_0x29b6f30/d .functor AND 1, L_0x29b6be0, L_0x29b6150, C4<1>, C4<1>;
+L_0x29b6f30 .delay (20000,20000,20000) L_0x29b6f30/d;
+L_0x29b7020/d .functor OR 1, L_0x29b6dc0, L_0x29b6f30, C4<0>, C4<0>;
+L_0x29b7020 .delay (20000,20000,20000) L_0x29b7020/d;
+v0x29187f0_0 .net "A", 0 0, L_0x29b5f80; 1 drivers
+v0x29188b0_0 .net "AandB", 0 0, L_0x29b6dc0; 1 drivers
+v0x2918950_0 .net "AddSubSLTSum", 0 0, L_0x29b6cd0; 1 drivers
+v0x29189f0_0 .net "AxorB", 0 0, L_0x29b6be0; 1 drivers
+v0x2918a70_0 .net "B", 0 0, L_0x29b6020; 1 drivers
+v0x2918b20_0 .net "BornB", 0 0, L_0x29b6630; 1 drivers
+v0x2918be0_0 .net "CINandAxorB", 0 0, L_0x29b6f30; 1 drivers
+v0x2918c60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2918ce0_0 .net *"_s3", 0 0, L_0x29b6960; 1 drivers
+v0x2918d60_0 .net *"_s5", 0 0, L_0x29b6b40; 1 drivers
+v0x2918e00_0 .net "carryin", 0 0, L_0x29b6150; 1 drivers
+v0x2918ea0_0 .net "carryout", 0 0, L_0x29b7020; 1 drivers
+v0x2918f40_0 .net "nB", 0 0, L_0x29b4b40; 1 drivers
+v0x2918ff0_0 .net "nCmd2", 0 0, L_0x29b68a0; 1 drivers
+v0x29190f0_0 .net "subtract", 0 0, L_0x29b6a00; 1 drivers
+L_0x29b6800 .part v0x2960210_0, 0, 1;
+L_0x29b6960 .part v0x2960210_0, 2, 1;
+L_0x29b6b40 .part v0x2960210_0, 0, 1;
+S_0x2918260 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2918170;
+ .timescale -9 -12;
+L_0x29b4d10/d .functor NOT 1, L_0x29b6800, C4<0>, C4<0>, C4<0>;
+L_0x29b4d10 .delay (10000,10000,10000) L_0x29b4d10/d;
+L_0x29b4dd0/d .functor AND 1, L_0x29b6020, L_0x29b4d10, C4<1>, C4<1>;
+L_0x29b4dd0 .delay (20000,20000,20000) L_0x29b4dd0/d;
+L_0x29b6520/d .functor AND 1, L_0x29b4b40, L_0x29b6800, C4<1>, C4<1>;
+L_0x29b6520 .delay (20000,20000,20000) L_0x29b6520/d;
+L_0x29b6630/d .functor OR 1, L_0x29b4dd0, L_0x29b6520, C4<0>, C4<0>;
+L_0x29b6630 .delay (20000,20000,20000) L_0x29b6630/d;
+v0x2918350_0 .net "S", 0 0, L_0x29b6800; 1 drivers
+v0x2918410_0 .alias "in0", 0 0, v0x2918a70_0;
+v0x29184b0_0 .alias "in1", 0 0, v0x2918f40_0;
+v0x2918550_0 .net "nS", 0 0, L_0x29b4d10; 1 drivers
+v0x29185d0_0 .net "out0", 0 0, L_0x29b4dd0; 1 drivers
+v0x2918670_0 .net "out1", 0 0, L_0x29b6520; 1 drivers
+v0x2918750_0 .alias "outfinal", 0 0, v0x2918b20_0;
+S_0x2917c00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2917510;
+ .timescale -9 -12;
+L_0x29b61f0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29b61f0 .delay (10000,10000,10000) L_0x29b61f0/d;
+L_0x29b6290/d .functor AND 1, L_0x29b7b50, L_0x29b61f0, C4<1>, C4<1>;
+L_0x29b6290 .delay (20000,20000,20000) L_0x29b6290/d;
+L_0x29b63a0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b63a0 .delay (20000,20000,20000) L_0x29b63a0/d;
+L_0x29b6440/d .functor OR 1, L_0x29b6290, L_0x29b63a0, C4<0>, C4<0>;
+L_0x29b6440 .delay (20000,20000,20000) L_0x29b6440/d;
+v0x2917cf0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2917d90_0 .net "in0", 0 0, L_0x29b7b50; 1 drivers
+v0x2917e30_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2917ed0_0 .net "nS", 0 0, L_0x29b61f0; 1 drivers
+v0x2917f50_0 .net "out0", 0 0, L_0x29b6290; 1 drivers
+v0x2917ff0_0 .net "out1", 0 0, L_0x29b63a0; 1 drivers
+v0x29180d0_0 .net "outfinal", 0 0, L_0x29b6440; 1 drivers
+S_0x2917680 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2917510;
+ .timescale -9 -12;
+L_0x29b74a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29b74a0 .delay (10000,10000,10000) L_0x29b74a0/d;
+L_0x29b75b0/d .functor AND 1, L_0x29b78a0, L_0x29b74a0, C4<1>, C4<1>;
+L_0x29b75b0 .delay (20000,20000,20000) L_0x29b75b0/d;
+L_0x29b76c0/d .functor AND 1, L_0x29b82d0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b76c0 .delay (20000,20000,20000) L_0x29b76c0/d;
+L_0x29b7760/d .functor OR 1, L_0x29b75b0, L_0x29b76c0, C4<0>, C4<0>;
+L_0x29b7760 .delay (20000,20000,20000) L_0x29b7760/d;
+v0x2917770_0 .alias "S", 0 0, v0x293b720_0;
+v0x29177f0_0 .net "in0", 0 0, L_0x29b78a0; 1 drivers
+v0x2917890_0 .net "in1", 0 0, L_0x29b82d0; 1 drivers
+v0x2917930_0 .net "nS", 0 0, L_0x29b74a0; 1 drivers
+v0x29179e0_0 .net "out0", 0 0, L_0x29b75b0; 1 drivers
+v0x2917a80_0 .net "out1", 0 0, L_0x29b76c0; 1 drivers
+v0x2917b60_0 .net "outfinal", 0 0, L_0x29b7760; 1 drivers
+S_0x2915890 .scope generate, "sltbits[20]" "sltbits[20]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x29152a8 .param/l "i" 3 332, +C4<010100>;
+S_0x29164f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2915890;
+ .timescale -9 -12;
+L_0x29b83c0/d .functor NOT 1, L_0x29b7ec0, C4<0>, C4<0>, C4<0>;
+L_0x29b83c0 .delay (10000,10000,10000) L_0x29b83c0/d;
+L_0x29b8a80/d .functor NOT 1, L_0x29b8b40, C4<0>, C4<0>, C4<0>;
+L_0x29b8a80 .delay (10000,10000,10000) L_0x29b8a80/d;
+L_0x29b8be0/d .functor AND 1, L_0x29b8d20, L_0x29b8a80, C4<1>, C4<1>;
+L_0x29b8be0 .delay (20000,20000,20000) L_0x29b8be0/d;
+L_0x29b8dc0/d .functor XOR 1, L_0x29b7e20, L_0x29b8810, C4<0>, C4<0>;
+L_0x29b8dc0 .delay (40000,40000,40000) L_0x29b8dc0/d;
+L_0x29b8eb0/d .functor XOR 1, L_0x29b8dc0, L_0x29b7ff0, C4<0>, C4<0>;
+L_0x29b8eb0 .delay (40000,40000,40000) L_0x29b8eb0/d;
+L_0x29b8fa0/d .functor AND 1, L_0x29b7e20, L_0x29b8810, C4<1>, C4<1>;
+L_0x29b8fa0 .delay (20000,20000,20000) L_0x29b8fa0/d;
+L_0x29b9110/d .functor AND 1, L_0x29b8dc0, L_0x29b7ff0, C4<1>, C4<1>;
+L_0x29b9110 .delay (20000,20000,20000) L_0x29b9110/d;
+L_0x29b9200/d .functor OR 1, L_0x29b8fa0, L_0x29b9110, C4<0>, C4<0>;
+L_0x29b9200 .delay (20000,20000,20000) L_0x29b9200/d;
+v0x2916b70_0 .net "A", 0 0, L_0x29b7e20; 1 drivers
+v0x2916c30_0 .net "AandB", 0 0, L_0x29b8fa0; 1 drivers
+v0x2916cd0_0 .net "AddSubSLTSum", 0 0, L_0x29b8eb0; 1 drivers
+v0x2916d70_0 .net "AxorB", 0 0, L_0x29b8dc0; 1 drivers
+v0x2916df0_0 .net "B", 0 0, L_0x29b7ec0; 1 drivers
+v0x2916ea0_0 .net "BornB", 0 0, L_0x29b8810; 1 drivers
+v0x2916f60_0 .net "CINandAxorB", 0 0, L_0x29b9110; 1 drivers
+v0x2916fe0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2917060_0 .net *"_s3", 0 0, L_0x29b8b40; 1 drivers
+v0x29170e0_0 .net *"_s5", 0 0, L_0x29b8d20; 1 drivers
+v0x2917180_0 .net "carryin", 0 0, L_0x29b7ff0; 1 drivers
+v0x2917220_0 .net "carryout", 0 0, L_0x29b9200; 1 drivers
+v0x29172c0_0 .net "nB", 0 0, L_0x29b83c0; 1 drivers
+v0x2917370_0 .net "nCmd2", 0 0, L_0x29b8a80; 1 drivers
+v0x2917470_0 .net "subtract", 0 0, L_0x29b8be0; 1 drivers
+L_0x29b89e0 .part v0x2960210_0, 0, 1;
+L_0x29b8b40 .part v0x2960210_0, 2, 1;
+L_0x29b8d20 .part v0x2960210_0, 0, 1;
+S_0x29165e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x29164f0;
+ .timescale -9 -12;
+L_0x29b8530/d .functor NOT 1, L_0x29b89e0, C4<0>, C4<0>, C4<0>;
+L_0x29b8530 .delay (10000,10000,10000) L_0x29b8530/d;
+L_0x29b85f0/d .functor AND 1, L_0x29b7ec0, L_0x29b8530, C4<1>, C4<1>;
+L_0x29b85f0 .delay (20000,20000,20000) L_0x29b85f0/d;
+L_0x29b8700/d .functor AND 1, L_0x29b83c0, L_0x29b89e0, C4<1>, C4<1>;
+L_0x29b8700 .delay (20000,20000,20000) L_0x29b8700/d;
+L_0x29b8810/d .functor OR 1, L_0x29b85f0, L_0x29b8700, C4<0>, C4<0>;
+L_0x29b8810 .delay (20000,20000,20000) L_0x29b8810/d;
+v0x29166d0_0 .net "S", 0 0, L_0x29b89e0; 1 drivers
+v0x2916790_0 .alias "in0", 0 0, v0x2916df0_0;
+v0x2916830_0 .alias "in1", 0 0, v0x29172c0_0;
+v0x29168d0_0 .net "nS", 0 0, L_0x29b8530; 1 drivers
+v0x2916950_0 .net "out0", 0 0, L_0x29b85f0; 1 drivers
+v0x29169f0_0 .net "out1", 0 0, L_0x29b8700; 1 drivers
+v0x2916ad0_0 .alias "outfinal", 0 0, v0x2916ea0_0;
+S_0x2915f80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2915890;
+ .timescale -9 -12;
+L_0x29b8090/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29b8090 .delay (10000,10000,10000) L_0x29b8090/d;
+L_0x29b8130/d .functor AND 1, L_0x29b9450, L_0x29b8090, C4<1>, C4<1>;
+L_0x29b8130 .delay (20000,20000,20000) L_0x29b8130/d;
+L_0x29b8240/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b8240 .delay (20000,20000,20000) L_0x29b8240/d;
+L_0x29b9b50/d .functor OR 1, L_0x29b8130, L_0x29b8240, C4<0>, C4<0>;
+L_0x29b9b50 .delay (20000,20000,20000) L_0x29b9b50/d;
+v0x2916070_0 .alias "S", 0 0, v0x293b720_0;
+v0x2916110_0 .net "in0", 0 0, L_0x29b9450; 1 drivers
+v0x29161b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2916250_0 .net "nS", 0 0, L_0x29b8090; 1 drivers
+v0x29162d0_0 .net "out0", 0 0, L_0x29b8130; 1 drivers
+v0x2916370_0 .net "out1", 0 0, L_0x29b8240; 1 drivers
+v0x2916450_0 .net "outfinal", 0 0, L_0x29b9b50; 1 drivers
+S_0x2915a00 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2915890;
+ .timescale -9 -12;
+L_0x29b95d0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29b95d0 .delay (10000,10000,10000) L_0x29b95d0/d;
+L_0x29b96e0/d .functor AND 1, L_0x29b9a70, L_0x29b95d0, C4<1>, C4<1>;
+L_0x29b96e0 .delay (20000,20000,20000) L_0x29b96e0/d;
+L_0x29b97f0/d .functor AND 1, L_0x29ba460, L_0x29d1680, C4<1>, C4<1>;
+L_0x29b97f0 .delay (20000,20000,20000) L_0x29b97f0/d;
+L_0x29b9890/d .functor OR 1, L_0x29b96e0, L_0x29b97f0, C4<0>, C4<0>;
+L_0x29b9890 .delay (20000,20000,20000) L_0x29b9890/d;
+v0x2915af0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2915b70_0 .net "in0", 0 0, L_0x29b9a70; 1 drivers
+v0x2915c10_0 .net "in1", 0 0, L_0x29ba460; 1 drivers
+v0x2915cb0_0 .net "nS", 0 0, L_0x29b95d0; 1 drivers
+v0x2915d60_0 .net "out0", 0 0, L_0x29b96e0; 1 drivers
+v0x2915e00_0 .net "out1", 0 0, L_0x29b97f0; 1 drivers
+v0x2915ee0_0 .net "outfinal", 0 0, L_0x29b9890; 1 drivers
+S_0x2913c10 .scope generate, "sltbits[21]" "sltbits[21]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2913628 .param/l "i" 3 332, +C4<010101>;
+S_0x2914870 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2913c10;
+ .timescale -9 -12;
+L_0x29b9d30/d .functor NOT 1, L_0x29ba6e0, C4<0>, C4<0>, C4<0>;
+L_0x29b9d30 .delay (10000,10000,10000) L_0x29b9d30/d;
+L_0x29ba3b0/d .functor NOT 1, L_0x29bad20, C4<0>, C4<0>, C4<0>;
+L_0x29ba3b0 .delay (10000,10000,10000) L_0x29ba3b0/d;
+L_0x29badc0/d .functor AND 1, L_0x29baf00, L_0x29ba3b0, C4<1>, C4<1>;
+L_0x29badc0 .delay (20000,20000,20000) L_0x29badc0/d;
+L_0x29bafa0/d .functor XOR 1, L_0x29ba640, L_0x29ba1e0, C4<0>, C4<0>;
+L_0x29bafa0 .delay (40000,40000,40000) L_0x29bafa0/d;
+L_0x29bb090/d .functor XOR 1, L_0x29bafa0, L_0x29ba810, C4<0>, C4<0>;
+L_0x29bb090 .delay (40000,40000,40000) L_0x29bb090/d;
+L_0x29bb180/d .functor AND 1, L_0x29ba640, L_0x29ba1e0, C4<1>, C4<1>;
+L_0x29bb180 .delay (20000,20000,20000) L_0x29bb180/d;
+L_0x29bb2f0/d .functor AND 1, L_0x29bafa0, L_0x29ba810, C4<1>, C4<1>;
+L_0x29bb2f0 .delay (20000,20000,20000) L_0x29bb2f0/d;
+L_0x29bb3e0/d .functor OR 1, L_0x29bb180, L_0x29bb2f0, C4<0>, C4<0>;
+L_0x29bb3e0 .delay (20000,20000,20000) L_0x29bb3e0/d;
+v0x2914ef0_0 .net "A", 0 0, L_0x29ba640; 1 drivers
+v0x2914fb0_0 .net "AandB", 0 0, L_0x29bb180; 1 drivers
+v0x2915050_0 .net "AddSubSLTSum", 0 0, L_0x29bb090; 1 drivers
+v0x29150f0_0 .net "AxorB", 0 0, L_0x29bafa0; 1 drivers
+v0x2915170_0 .net "B", 0 0, L_0x29ba6e0; 1 drivers
+v0x2915220_0 .net "BornB", 0 0, L_0x29ba1e0; 1 drivers
+v0x29152e0_0 .net "CINandAxorB", 0 0, L_0x29bb2f0; 1 drivers
+v0x2915360_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x29153e0_0 .net *"_s3", 0 0, L_0x29bad20; 1 drivers
+v0x2915460_0 .net *"_s5", 0 0, L_0x29baf00; 1 drivers
+v0x2915500_0 .net "carryin", 0 0, L_0x29ba810; 1 drivers
+v0x29155a0_0 .net "carryout", 0 0, L_0x29bb3e0; 1 drivers
+v0x2915640_0 .net "nB", 0 0, L_0x29b9d30; 1 drivers
+v0x29156f0_0 .net "nCmd2", 0 0, L_0x29ba3b0; 1 drivers
+v0x29157f0_0 .net "subtract", 0 0, L_0x29badc0; 1 drivers
+L_0x29bac40 .part v0x2960210_0, 0, 1;
+L_0x29bad20 .part v0x2960210_0, 2, 1;
+L_0x29baf00 .part v0x2960210_0, 0, 1;
+S_0x2914960 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2914870;
+ .timescale -9 -12;
+L_0x29b9f00/d .functor NOT 1, L_0x29bac40, C4<0>, C4<0>, C4<0>;
+L_0x29b9f00 .delay (10000,10000,10000) L_0x29b9f00/d;
+L_0x29b9fc0/d .functor AND 1, L_0x29ba6e0, L_0x29b9f00, C4<1>, C4<1>;
+L_0x29b9fc0 .delay (20000,20000,20000) L_0x29b9fc0/d;
+L_0x29ba0d0/d .functor AND 1, L_0x29b9d30, L_0x29bac40, C4<1>, C4<1>;
+L_0x29ba0d0 .delay (20000,20000,20000) L_0x29ba0d0/d;
+L_0x29ba1e0/d .functor OR 1, L_0x29b9fc0, L_0x29ba0d0, C4<0>, C4<0>;
+L_0x29ba1e0 .delay (20000,20000,20000) L_0x29ba1e0/d;
+v0x2914a50_0 .net "S", 0 0, L_0x29bac40; 1 drivers
+v0x2914b10_0 .alias "in0", 0 0, v0x2915170_0;
+v0x2914bb0_0 .alias "in1", 0 0, v0x2915640_0;
+v0x2914c50_0 .net "nS", 0 0, L_0x29b9f00; 1 drivers
+v0x2914cd0_0 .net "out0", 0 0, L_0x29b9fc0; 1 drivers
+v0x2914d70_0 .net "out1", 0 0, L_0x29ba0d0; 1 drivers
+v0x2914e50_0 .alias "outfinal", 0 0, v0x2915220_0;
+S_0x2914300 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2913c10;
+ .timescale -9 -12;
+L_0x29ba8b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29ba8b0 .delay (10000,10000,10000) L_0x29ba8b0/d;
+L_0x29ba950/d .functor AND 1, L_0x29bbee0, L_0x29ba8b0, C4<1>, C4<1>;
+L_0x29ba950 .delay (20000,20000,20000) L_0x29ba950/d;
+L_0x29baa60/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29baa60 .delay (20000,20000,20000) L_0x29baa60/d;
+L_0x29bab00/d .functor OR 1, L_0x29ba950, L_0x29baa60, C4<0>, C4<0>;
+L_0x29bab00 .delay (20000,20000,20000) L_0x29bab00/d;
+v0x29143f0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2914490_0 .net "in0", 0 0, L_0x29bbee0; 1 drivers
+v0x2914530_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x29145d0_0 .net "nS", 0 0, L_0x29ba8b0; 1 drivers
+v0x2914650_0 .net "out0", 0 0, L_0x29ba950; 1 drivers
+v0x29146f0_0 .net "out1", 0 0, L_0x29baa60; 1 drivers
+v0x29147d0_0 .net "outfinal", 0 0, L_0x29bab00; 1 drivers
+S_0x2913d80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2913c10;
+ .timescale -9 -12;
+L_0x29bb870/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29bb870 .delay (10000,10000,10000) L_0x29bb870/d;
+L_0x29bb980/d .functor AND 1, L_0x29bbd10, L_0x29bb870, C4<1>, C4<1>;
+L_0x29bb980 .delay (20000,20000,20000) L_0x29bb980/d;
+L_0x29bba90/d .functor AND 1, L_0x29b73f0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29bba90 .delay (20000,20000,20000) L_0x29bba90/d;
+L_0x29bbb30/d .functor OR 1, L_0x29bb980, L_0x29bba90, C4<0>, C4<0>;
+L_0x29bbb30 .delay (20000,20000,20000) L_0x29bbb30/d;
+v0x2913e70_0 .alias "S", 0 0, v0x293b720_0;
+v0x2913ef0_0 .net "in0", 0 0, L_0x29bbd10; 1 drivers
+v0x2913f90_0 .net "in1", 0 0, L_0x29b73f0; 1 drivers
+v0x2914030_0 .net "nS", 0 0, L_0x29bb870; 1 drivers
+v0x29140e0_0 .net "out0", 0 0, L_0x29bb980; 1 drivers
+v0x2914180_0 .net "out1", 0 0, L_0x29bba90; 1 drivers
+v0x2914260_0 .net "outfinal", 0 0, L_0x29bbb30; 1 drivers
+S_0x2911f90 .scope generate, "sltbits[22]" "sltbits[22]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x2911888 .param/l "i" 3 332, +C4<010110>;
+S_0x2912bf0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2911f90;
+ .timescale -9 -12;
+L_0x29bc760/d .functor NOT 1, L_0x29bc250, C4<0>, C4<0>, C4<0>;
+L_0x29bc760 .delay (10000,10000,10000) L_0x29bc760/d;
+L_0x29bce40/d .functor NOT 1, L_0x29bcf00, C4<0>, C4<0>, C4<0>;
+L_0x29bce40 .delay (10000,10000,10000) L_0x29bce40/d;
+L_0x29bcfa0/d .functor AND 1, L_0x29bd0e0, L_0x29bce40, C4<1>, C4<1>;
+L_0x29bcfa0 .delay (20000,20000,20000) L_0x29bcfa0/d;
+L_0x29bd180/d .functor XOR 1, L_0x29bc1b0, L_0x29bcbd0, C4<0>, C4<0>;
+L_0x29bd180 .delay (40000,40000,40000) L_0x29bd180/d;
+L_0x29bd270/d .functor XOR 1, L_0x29bd180, L_0x29bc380, C4<0>, C4<0>;
+L_0x29bd270 .delay (40000,40000,40000) L_0x29bd270/d;
+L_0x29bd360/d .functor AND 1, L_0x29bc1b0, L_0x29bcbd0, C4<1>, C4<1>;
+L_0x29bd360 .delay (20000,20000,20000) L_0x29bd360/d;
+L_0x29bd4d0/d .functor AND 1, L_0x29bd180, L_0x29bc380, C4<1>, C4<1>;
+L_0x29bd4d0 .delay (20000,20000,20000) L_0x29bd4d0/d;
+L_0x29bd5c0/d .functor OR 1, L_0x29bd360, L_0x29bd4d0, C4<0>, C4<0>;
+L_0x29bd5c0 .delay (20000,20000,20000) L_0x29bd5c0/d;
+v0x2913270_0 .net "A", 0 0, L_0x29bc1b0; 1 drivers
+v0x2913330_0 .net "AandB", 0 0, L_0x29bd360; 1 drivers
+v0x29133d0_0 .net "AddSubSLTSum", 0 0, L_0x29bd270; 1 drivers
+v0x2913470_0 .net "AxorB", 0 0, L_0x29bd180; 1 drivers
+v0x29134f0_0 .net "B", 0 0, L_0x29bc250; 1 drivers
+v0x29135a0_0 .net "BornB", 0 0, L_0x29bcbd0; 1 drivers
+v0x2913660_0 .net "CINandAxorB", 0 0, L_0x29bd4d0; 1 drivers
+v0x29136e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2913760_0 .net *"_s3", 0 0, L_0x29bcf00; 1 drivers
+v0x29137e0_0 .net *"_s5", 0 0, L_0x29bd0e0; 1 drivers
+v0x2913880_0 .net "carryin", 0 0, L_0x29bc380; 1 drivers
+v0x2913920_0 .net "carryout", 0 0, L_0x29bd5c0; 1 drivers
+v0x29139c0_0 .net "nB", 0 0, L_0x29bc760; 1 drivers
+v0x2913a70_0 .net "nCmd2", 0 0, L_0x29bce40; 1 drivers
+v0x2913b70_0 .net "subtract", 0 0, L_0x29bcfa0; 1 drivers
+L_0x29bcda0 .part v0x2960210_0, 0, 1;
+L_0x29bcf00 .part v0x2960210_0, 2, 1;
+L_0x29bd0e0 .part v0x2960210_0, 0, 1;
+S_0x2912ce0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2912bf0;
+ .timescale -9 -12;
+L_0x29bc8f0/d .functor NOT 1, L_0x29bcda0, C4<0>, C4<0>, C4<0>;
+L_0x29bc8f0 .delay (10000,10000,10000) L_0x29bc8f0/d;
+L_0x29bc9b0/d .functor AND 1, L_0x29bc250, L_0x29bc8f0, C4<1>, C4<1>;
+L_0x29bc9b0 .delay (20000,20000,20000) L_0x29bc9b0/d;
+L_0x29bcac0/d .functor AND 1, L_0x29bc760, L_0x29bcda0, C4<1>, C4<1>;
+L_0x29bcac0 .delay (20000,20000,20000) L_0x29bcac0/d;
+L_0x29bcbd0/d .functor OR 1, L_0x29bc9b0, L_0x29bcac0, C4<0>, C4<0>;
+L_0x29bcbd0 .delay (20000,20000,20000) L_0x29bcbd0/d;
+v0x2912dd0_0 .net "S", 0 0, L_0x29bcda0; 1 drivers
+v0x2912e90_0 .alias "in0", 0 0, v0x29134f0_0;
+v0x2912f30_0 .alias "in1", 0 0, v0x29139c0_0;
+v0x2912fd0_0 .net "nS", 0 0, L_0x29bc8f0; 1 drivers
+v0x2913050_0 .net "out0", 0 0, L_0x29bc9b0; 1 drivers
+v0x29130f0_0 .net "out1", 0 0, L_0x29bcac0; 1 drivers
+v0x29131d0_0 .alias "outfinal", 0 0, v0x29135a0_0;
+S_0x2912680 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2911f90;
+ .timescale -9 -12;
+L_0x29bc420/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29bc420 .delay (10000,10000,10000) L_0x29bc420/d;
+L_0x29bc4c0/d .functor AND 1, L_0x29a5b70, L_0x29bc420, C4<1>, C4<1>;
+L_0x29bc4c0 .delay (20000,20000,20000) L_0x29bc4c0/d;
+L_0x29bc5d0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29bc5d0 .delay (20000,20000,20000) L_0x29bc5d0/d;
+L_0x29bc670/d .functor OR 1, L_0x29bc4c0, L_0x29bc5d0, C4<0>, C4<0>;
+L_0x29bc670 .delay (20000,20000,20000) L_0x29bc670/d;
+v0x2912770_0 .alias "S", 0 0, v0x293b720_0;
+v0x2912810_0 .net "in0", 0 0, L_0x29a5b70; 1 drivers
+v0x29128b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2912950_0 .net "nS", 0 0, L_0x29bc420; 1 drivers
+v0x29129d0_0 .net "out0", 0 0, L_0x29bc4c0; 1 drivers
+v0x2912a70_0 .net "out1", 0 0, L_0x29bc5d0; 1 drivers
+v0x2912b50_0 .net "outfinal", 0 0, L_0x29bc670; 1 drivers
+S_0x2912100 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2911f90;
+ .timescale -9 -12;
+L_0x29a5cf0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29a5cf0 .delay (10000,10000,10000) L_0x29a5cf0/d;
+L_0x29a5e00/d .functor AND 1, L_0x29bda30, L_0x29a5cf0, C4<1>, C4<1>;
+L_0x29a5e00 .delay (20000,20000,20000) L_0x29a5e00/d;
+L_0x29a5f10/d .functor AND 1, L_0x29bdb20, L_0x29d1680, C4<1>, C4<1>;
+L_0x29a5f10 .delay (20000,20000,20000) L_0x29a5f10/d;
+L_0x29bd850/d .functor OR 1, L_0x29a5e00, L_0x29a5f10, C4<0>, C4<0>;
+L_0x29bd850 .delay (20000,20000,20000) L_0x29bd850/d;
+v0x29121f0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2912270_0 .net "in0", 0 0, L_0x29bda30; 1 drivers
+v0x2912310_0 .net "in1", 0 0, L_0x29bdb20; 1 drivers
+v0x29123b0_0 .net "nS", 0 0, L_0x29a5cf0; 1 drivers
+v0x2912460_0 .net "out0", 0 0, L_0x29a5e00; 1 drivers
+v0x2912500_0 .net "out1", 0 0, L_0x29a5f10; 1 drivers
+v0x29125e0_0 .net "outfinal", 0 0, L_0x29bd850; 1 drivers
+S_0x28f01e0 .scope generate, "sltbits[23]" "sltbits[23]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28efbf8 .param/l "i" 3 332, +C4<010111>;
+S_0x2910e50 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28f01e0;
+ .timescale -9 -12;
+L_0x29bdc10/d .functor NOT 1, L_0x29bea60, C4<0>, C4<0>, C4<0>;
+L_0x29bdc10 .delay (10000,10000,10000) L_0x29bdc10/d;
+L_0x29bf420/d .functor NOT 1, L_0x29bf4e0, C4<0>, C4<0>, C4<0>;
+L_0x29bf420 .delay (10000,10000,10000) L_0x29bf420/d;
+L_0x29bf580/d .functor AND 1, L_0x29bf6c0, L_0x29bf420, C4<1>, C4<1>;
+L_0x29bf580 .delay (20000,20000,20000) L_0x29bf580/d;
+L_0x29bf760/d .functor XOR 1, L_0x29be9c0, L_0x29bf1b0, C4<0>, C4<0>;
+L_0x29bf760 .delay (40000,40000,40000) L_0x29bf760/d;
+L_0x29bf850/d .functor XOR 1, L_0x29bf760, L_0x29beb90, C4<0>, C4<0>;
+L_0x29bf850 .delay (40000,40000,40000) L_0x29bf850/d;
+L_0x29bf940/d .functor AND 1, L_0x29be9c0, L_0x29bf1b0, C4<1>, C4<1>;
+L_0x29bf940 .delay (20000,20000,20000) L_0x29bf940/d;
+L_0x29bfab0/d .functor AND 1, L_0x29bf760, L_0x29beb90, C4<1>, C4<1>;
+L_0x29bfab0 .delay (20000,20000,20000) L_0x29bfab0/d;
+L_0x29bfba0/d .functor OR 1, L_0x29bf940, L_0x29bfab0, C4<0>, C4<0>;
+L_0x29bfba0 .delay (20000,20000,20000) L_0x29bfba0/d;
+v0x29114d0_0 .net "A", 0 0, L_0x29be9c0; 1 drivers
+v0x2911590_0 .net "AandB", 0 0, L_0x29bf940; 1 drivers
+v0x2911630_0 .net "AddSubSLTSum", 0 0, L_0x29bf850; 1 drivers
+v0x29116d0_0 .net "AxorB", 0 0, L_0x29bf760; 1 drivers
+v0x2911750_0 .net "B", 0 0, L_0x29bea60; 1 drivers
+v0x2911800_0 .net "BornB", 0 0, L_0x29bf1b0; 1 drivers
+v0x29118c0_0 .net "CINandAxorB", 0 0, L_0x29bfab0; 1 drivers
+v0x2911940_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2911a10_0 .net *"_s3", 0 0, L_0x29bf4e0; 1 drivers
+v0x2911a90_0 .net *"_s5", 0 0, L_0x29bf6c0; 1 drivers
+v0x2911b90_0 .net "carryin", 0 0, L_0x29beb90; 1 drivers
+v0x2911c30_0 .net "carryout", 0 0, L_0x29bfba0; 1 drivers
+v0x2911d40_0 .net "nB", 0 0, L_0x29bdc10; 1 drivers
+v0x2911df0_0 .net "nCmd2", 0 0, L_0x29bf420; 1 drivers
+v0x2911ef0_0 .net "subtract", 0 0, L_0x29bf580; 1 drivers
+L_0x29bf380 .part v0x2960210_0, 0, 1;
+L_0x29bf4e0 .part v0x2960210_0, 2, 1;
+L_0x29bf6c0 .part v0x2960210_0, 0, 1;
+S_0x2910f40 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2910e50;
+ .timescale -9 -12;
+L_0x29bdde0/d .functor NOT 1, L_0x29bf380, C4<0>, C4<0>, C4<0>;
+L_0x29bdde0 .delay (10000,10000,10000) L_0x29bdde0/d;
+L_0x29bdea0/d .functor AND 1, L_0x29bea60, L_0x29bdde0, C4<1>, C4<1>;
+L_0x29bdea0 .delay (20000,20000,20000) L_0x29bdea0/d;
+L_0x29bf0c0/d .functor AND 1, L_0x29bdc10, L_0x29bf380, C4<1>, C4<1>;
+L_0x29bf0c0 .delay (20000,20000,20000) L_0x29bf0c0/d;
+L_0x29bf1b0/d .functor OR 1, L_0x29bdea0, L_0x29bf0c0, C4<0>, C4<0>;
+L_0x29bf1b0 .delay (20000,20000,20000) L_0x29bf1b0/d;
+v0x2911030_0 .net "S", 0 0, L_0x29bf380; 1 drivers
+v0x29110f0_0 .alias "in0", 0 0, v0x2911750_0;
+v0x2911190_0 .alias "in1", 0 0, v0x2911d40_0;
+v0x2911230_0 .net "nS", 0 0, L_0x29bdde0; 1 drivers
+v0x29112b0_0 .net "out0", 0 0, L_0x29bdea0; 1 drivers
+v0x2911350_0 .net "out1", 0 0, L_0x29bf0c0; 1 drivers
+v0x2911430_0 .alias "outfinal", 0 0, v0x2911800_0;
+S_0x29108e0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28f01e0;
+ .timescale -9 -12;
+L_0x29bec30/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29bec30 .delay (10000,10000,10000) L_0x29bec30/d;
+L_0x29becd0/d .functor AND 1, L_0x29c06b0, L_0x29bec30, C4<1>, C4<1>;
+L_0x29becd0 .delay (20000,20000,20000) L_0x29becd0/d;
+L_0x29bede0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29bede0 .delay (20000,20000,20000) L_0x29bede0/d;
+L_0x29bee80/d .functor OR 1, L_0x29becd0, L_0x29bede0, C4<0>, C4<0>;
+L_0x29bee80 .delay (20000,20000,20000) L_0x29bee80/d;
+v0x29109d0_0 .alias "S", 0 0, v0x293b720_0;
+v0x2910a70_0 .net "in0", 0 0, L_0x29c06b0; 1 drivers
+v0x2910b10_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2910bb0_0 .net "nS", 0 0, L_0x29bec30; 1 drivers
+v0x2910c30_0 .net "out0", 0 0, L_0x29becd0; 1 drivers
+v0x2910cd0_0 .net "out1", 0 0, L_0x29bede0; 1 drivers
+v0x2910db0_0 .net "outfinal", 0 0, L_0x29bee80; 1 drivers
+S_0x28f0350 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28f01e0;
+ .timescale -9 -12;
+L_0x29c0040/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c0040 .delay (10000,10000,10000) L_0x29c0040/d;
+L_0x29c0150/d .functor AND 1, L_0x29c04e0, L_0x29c0040, C4<1>, C4<1>;
+L_0x29c0150 .delay (20000,20000,20000) L_0x29c0150/d;
+L_0x29c0260/d .functor AND 1, L_0x29c05d0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c0260 .delay (20000,20000,20000) L_0x29c0260/d;
+L_0x29c0300/d .functor OR 1, L_0x29c0150, L_0x29c0260, C4<0>, C4<0>;
+L_0x29c0300 .delay (20000,20000,20000) L_0x29c0300/d;
+v0x28f0440_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e9270_0 .net "in0", 0 0, L_0x29c04e0; 1 drivers
+v0x2910570_0 .net "in1", 0 0, L_0x29c05d0; 1 drivers
+v0x2910610_0 .net "nS", 0 0, L_0x29c0040; 1 drivers
+v0x29106c0_0 .net "out0", 0 0, L_0x29c0150; 1 drivers
+v0x2910760_0 .net "out1", 0 0, L_0x29c0260; 1 drivers
+v0x2910840_0 .net "outfinal", 0 0, L_0x29c0300; 1 drivers
+S_0x28ee560 .scope generate, "sltbits[24]" "sltbits[24]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28edfb8 .param/l "i" 3 332, +C4<011000>;
+S_0x28ef1c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28ee560;
+ .timescale -9 -12;
+L_0x29bb800/d .functor NOT 1, L_0x29c0a20, C4<0>, C4<0>, C4<0>;
+L_0x29bb800 .delay (10000,10000,10000) L_0x29bb800/d;
+L_0x29c1610/d .functor NOT 1, L_0x29c16d0, C4<0>, C4<0>, C4<0>;
+L_0x29c1610 .delay (10000,10000,10000) L_0x29c1610/d;
+L_0x29c1770/d .functor AND 1, L_0x29c18b0, L_0x29c1610, C4<1>, C4<1>;
+L_0x29c1770 .delay (20000,20000,20000) L_0x29c1770/d;
+L_0x29c1950/d .functor XOR 1, L_0x29c0980, L_0x29c13a0, C4<0>, C4<0>;
+L_0x29c1950 .delay (40000,40000,40000) L_0x29c1950/d;
+L_0x29c1a40/d .functor XOR 1, L_0x29c1950, L_0x29c0b50, C4<0>, C4<0>;
+L_0x29c1a40 .delay (40000,40000,40000) L_0x29c1a40/d;
+L_0x29c1b30/d .functor AND 1, L_0x29c0980, L_0x29c13a0, C4<1>, C4<1>;
+L_0x29c1b30 .delay (20000,20000,20000) L_0x29c1b30/d;
+L_0x29c1ca0/d .functor AND 1, L_0x29c1950, L_0x29c0b50, C4<1>, C4<1>;
+L_0x29c1ca0 .delay (20000,20000,20000) L_0x29c1ca0/d;
+L_0x29c1d90/d .functor OR 1, L_0x29c1b30, L_0x29c1ca0, C4<0>, C4<0>;
+L_0x29c1d90 .delay (20000,20000,20000) L_0x29c1d90/d;
+v0x28ef840_0 .net "A", 0 0, L_0x29c0980; 1 drivers
+v0x28ef900_0 .net "AandB", 0 0, L_0x29c1b30; 1 drivers
+v0x28ef9a0_0 .net "AddSubSLTSum", 0 0, L_0x29c1a40; 1 drivers
+v0x28efa40_0 .net "AxorB", 0 0, L_0x29c1950; 1 drivers
+v0x28efac0_0 .net "B", 0 0, L_0x29c0a20; 1 drivers
+v0x28efb70_0 .net "BornB", 0 0, L_0x29c13a0; 1 drivers
+v0x28efc30_0 .net "CINandAxorB", 0 0, L_0x29c1ca0; 1 drivers
+v0x28efcb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28efd30_0 .net *"_s3", 0 0, L_0x29c16d0; 1 drivers
+v0x28efdb0_0 .net *"_s5", 0 0, L_0x29c18b0; 1 drivers
+v0x28efe50_0 .net "carryin", 0 0, L_0x29c0b50; 1 drivers
+v0x28efef0_0 .net "carryout", 0 0, L_0x29c1d90; 1 drivers
+v0x28eff90_0 .net "nB", 0 0, L_0x29bb800; 1 drivers
+v0x28f0040_0 .net "nCmd2", 0 0, L_0x29c1610; 1 drivers
+v0x28f0140_0 .net "subtract", 0 0, L_0x29c1770; 1 drivers
+L_0x29c1570 .part v0x2960210_0, 0, 1;
+L_0x29c16d0 .part v0x2960210_0, 2, 1;
+L_0x29c18b0 .part v0x2960210_0, 0, 1;
+S_0x28ef2b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28ef1c0;
+ .timescale -9 -12;
+L_0x29c10c0/d .functor NOT 1, L_0x29c1570, C4<0>, C4<0>, C4<0>;
+L_0x29c10c0 .delay (10000,10000,10000) L_0x29c10c0/d;
+L_0x29c1180/d .functor AND 1, L_0x29c0a20, L_0x29c10c0, C4<1>, C4<1>;
+L_0x29c1180 .delay (20000,20000,20000) L_0x29c1180/d;
+L_0x29c1290/d .functor AND 1, L_0x29bb800, L_0x29c1570, C4<1>, C4<1>;
+L_0x29c1290 .delay (20000,20000,20000) L_0x29c1290/d;
+L_0x29c13a0/d .functor OR 1, L_0x29c1180, L_0x29c1290, C4<0>, C4<0>;
+L_0x29c13a0 .delay (20000,20000,20000) L_0x29c13a0/d;
+v0x28ef3a0_0 .net "S", 0 0, L_0x29c1570; 1 drivers
+v0x28ef460_0 .alias "in0", 0 0, v0x28efac0_0;
+v0x28ef500_0 .alias "in1", 0 0, v0x28eff90_0;
+v0x28ef5a0_0 .net "nS", 0 0, L_0x29c10c0; 1 drivers
+v0x28ef620_0 .net "out0", 0 0, L_0x29c1180; 1 drivers
+v0x28ef6c0_0 .net "out1", 0 0, L_0x29c1290; 1 drivers
+v0x28ef7a0_0 .alias "outfinal", 0 0, v0x28efb70_0;
+S_0x28eec50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28ee560;
+ .timescale -9 -12;
+L_0x29c0bf0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c0bf0 .delay (10000,10000,10000) L_0x29c0bf0/d;
+L_0x29c0c90/d .functor AND 1, L_0x29c1fe0, L_0x29c0bf0, C4<1>, C4<1>;
+L_0x29c0c90 .delay (20000,20000,20000) L_0x29c0c90/d;
+L_0x29c0da0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c0da0 .delay (20000,20000,20000) L_0x29c0da0/d;
+L_0x29c0e40/d .functor OR 1, L_0x29c0c90, L_0x29c0da0, C4<0>, C4<0>;
+L_0x29c0e40 .delay (20000,20000,20000) L_0x29c0e40/d;
+v0x28eed40_0 .alias "S", 0 0, v0x293b720_0;
+v0x28eede0_0 .net "in0", 0 0, L_0x29c1fe0; 1 drivers
+v0x28eee80_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28eef20_0 .net "nS", 0 0, L_0x29c0bf0; 1 drivers
+v0x28eefa0_0 .net "out0", 0 0, L_0x29c0c90; 1 drivers
+v0x28ef040_0 .net "out1", 0 0, L_0x29c0da0; 1 drivers
+v0x28ef120_0 .net "outfinal", 0 0, L_0x29c0e40; 1 drivers
+S_0x28ee6d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28ee560;
+ .timescale -9 -12;
+L_0x29c0f30/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c0f30 .delay (10000,10000,10000) L_0x29c0f30/d;
+L_0x29c2210/d .functor AND 1, L_0x29c25a0, L_0x29c0f30, C4<1>, C4<1>;
+L_0x29c2210 .delay (20000,20000,20000) L_0x29c2210/d;
+L_0x29c2320/d .functor AND 1, L_0x29c2690, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c2320 .delay (20000,20000,20000) L_0x29c2320/d;
+L_0x29c23c0/d .functor OR 1, L_0x29c2210, L_0x29c2320, C4<0>, C4<0>;
+L_0x29c23c0 .delay (20000,20000,20000) L_0x29c23c0/d;
+v0x28ee7c0_0 .alias "S", 0 0, v0x293b720_0;
+v0x28ee840_0 .net "in0", 0 0, L_0x29c25a0; 1 drivers
+v0x28ee8e0_0 .net "in1", 0 0, L_0x29c2690; 1 drivers
+v0x28ee980_0 .net "nS", 0 0, L_0x29c0f30; 1 drivers
+v0x28eea30_0 .net "out0", 0 0, L_0x29c2210; 1 drivers
+v0x28eead0_0 .net "out1", 0 0, L_0x29c2320; 1 drivers
+v0x28eebb0_0 .net "outfinal", 0 0, L_0x29c23c0; 1 drivers
+S_0x28ec920 .scope generate, "sltbits[25]" "sltbits[25]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28ec338 .param/l "i" 3 332, +C4<011001>;
+S_0x28ed580 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28ec920;
+ .timescale -9 -12;
+L_0x29c2780/d .functor NOT 1, L_0x29c2a80, C4<0>, C4<0>, C4<0>;
+L_0x29c2780 .delay (10000,10000,10000) L_0x29c2780/d;
+L_0x29c37e0/d .functor NOT 1, L_0x29c38a0, C4<0>, C4<0>, C4<0>;
+L_0x29c37e0 .delay (10000,10000,10000) L_0x29c37e0/d;
+L_0x29c3940/d .functor AND 1, L_0x29c3a80, L_0x29c37e0, C4<1>, C4<1>;
+L_0x29c3940 .delay (20000,20000,20000) L_0x29c3940/d;
+L_0x29c3b20/d .functor XOR 1, L_0x29c29e0, L_0x29c3570, C4<0>, C4<0>;
+L_0x29c3b20 .delay (40000,40000,40000) L_0x29c3b20/d;
+L_0x29c3c10/d .functor XOR 1, L_0x29c3b20, L_0x29c2bb0, C4<0>, C4<0>;
+L_0x29c3c10 .delay (40000,40000,40000) L_0x29c3c10/d;
+L_0x29c3d00/d .functor AND 1, L_0x29c29e0, L_0x29c3570, C4<1>, C4<1>;
+L_0x29c3d00 .delay (20000,20000,20000) L_0x29c3d00/d;
+L_0x29c3e70/d .functor AND 1, L_0x29c3b20, L_0x29c2bb0, C4<1>, C4<1>;
+L_0x29c3e70 .delay (20000,20000,20000) L_0x29c3e70/d;
+L_0x29c3f80/d .functor OR 1, L_0x29c3d00, L_0x29c3e70, C4<0>, C4<0>;
+L_0x29c3f80 .delay (20000,20000,20000) L_0x29c3f80/d;
+v0x28edc00_0 .net "A", 0 0, L_0x29c29e0; 1 drivers
+v0x28edcc0_0 .net "AandB", 0 0, L_0x29c3d00; 1 drivers
+v0x28edd60_0 .net "AddSubSLTSum", 0 0, L_0x29c3c10; 1 drivers
+v0x28ede00_0 .net "AxorB", 0 0, L_0x29c3b20; 1 drivers
+v0x28ede80_0 .net "B", 0 0, L_0x29c2a80; 1 drivers
+v0x28edf30_0 .net "BornB", 0 0, L_0x29c3570; 1 drivers
+v0x28edff0_0 .net "CINandAxorB", 0 0, L_0x29c3e70; 1 drivers
+v0x28ee070_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28ee0f0_0 .net *"_s3", 0 0, L_0x29c38a0; 1 drivers
+v0x28ee170_0 .net *"_s5", 0 0, L_0x29c3a80; 1 drivers
+v0x28ee1f0_0 .net "carryin", 0 0, L_0x29c2bb0; 1 drivers
+v0x28ee270_0 .net "carryout", 0 0, L_0x29c3f80; 1 drivers
+v0x28ee310_0 .net "nB", 0 0, L_0x29c2780; 1 drivers
+v0x28ee3c0_0 .net "nCmd2", 0 0, L_0x29c37e0; 1 drivers
+v0x28ee4c0_0 .net "subtract", 0 0, L_0x29c3940; 1 drivers
+L_0x29c3740 .part v0x2960210_0, 0, 1;
+L_0x29c38a0 .part v0x2960210_0, 2, 1;
+L_0x29c3a80 .part v0x2960210_0, 0, 1;
+S_0x28ed670 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28ed580;
+ .timescale -9 -12;
+L_0x29c3290/d .functor NOT 1, L_0x29c3740, C4<0>, C4<0>, C4<0>;
+L_0x29c3290 .delay (10000,10000,10000) L_0x29c3290/d;
+L_0x29c3350/d .functor AND 1, L_0x29c2a80, L_0x29c3290, C4<1>, C4<1>;
+L_0x29c3350 .delay (20000,20000,20000) L_0x29c3350/d;
+L_0x29c3460/d .functor AND 1, L_0x29c2780, L_0x29c3740, C4<1>, C4<1>;
+L_0x29c3460 .delay (20000,20000,20000) L_0x29c3460/d;
+L_0x29c3570/d .functor OR 1, L_0x29c3350, L_0x29c3460, C4<0>, C4<0>;
+L_0x29c3570 .delay (20000,20000,20000) L_0x29c3570/d;
+v0x28ed760_0 .net "S", 0 0, L_0x29c3740; 1 drivers
+v0x28ed820_0 .alias "in0", 0 0, v0x28ede80_0;
+v0x28ed8c0_0 .alias "in1", 0 0, v0x28ee310_0;
+v0x28ed960_0 .net "nS", 0 0, L_0x29c3290; 1 drivers
+v0x28ed9e0_0 .net "out0", 0 0, L_0x29c3350; 1 drivers
+v0x28eda80_0 .net "out1", 0 0, L_0x29c3460; 1 drivers
+v0x28edb60_0 .alias "outfinal", 0 0, v0x28edf30_0;
+S_0x28ed010 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28ec920;
+ .timescale -9 -12;
+L_0x29c2c50/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c2c50 .delay (10000,10000,10000) L_0x29c2c50/d;
+L_0x29c2cf0/d .functor AND 1, L_0x29c3080, L_0x29c2c50, C4<1>, C4<1>;
+L_0x29c2cf0 .delay (20000,20000,20000) L_0x29c2cf0/d;
+L_0x29c2e00/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c2e00 .delay (20000,20000,20000) L_0x29c2e00/d;
+L_0x29c2ea0/d .functor OR 1, L_0x29c2cf0, L_0x29c2e00, C4<0>, C4<0>;
+L_0x29c2ea0 .delay (20000,20000,20000) L_0x29c2ea0/d;
+v0x28ed100_0 .alias "S", 0 0, v0x293b720_0;
+v0x28ed1a0_0 .net "in0", 0 0, L_0x29c3080; 1 drivers
+v0x28ed240_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28ed2e0_0 .net "nS", 0 0, L_0x29c2c50; 1 drivers
+v0x28ed360_0 .net "out0", 0 0, L_0x29c2cf0; 1 drivers
+v0x28ed400_0 .net "out1", 0 0, L_0x29c2e00; 1 drivers
+v0x28ed4e0_0 .net "outfinal", 0 0, L_0x29c2ea0; 1 drivers
+S_0x28eca90 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28ec920;
+ .timescale -9 -12;
+L_0x29c4430/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c4430 .delay (10000,10000,10000) L_0x29c4430/d;
+L_0x29c4520/d .functor AND 1, L_0x29c48b0, L_0x29c4430, C4<1>, C4<1>;
+L_0x29c4520 .delay (20000,20000,20000) L_0x29c4520/d;
+L_0x29c4630/d .functor AND 1, L_0x29c49a0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c4630 .delay (20000,20000,20000) L_0x29c4630/d;
+L_0x29c46d0/d .functor OR 1, L_0x29c4520, L_0x29c4630, C4<0>, C4<0>;
+L_0x29c46d0 .delay (20000,20000,20000) L_0x29c46d0/d;
+v0x28ecb80_0 .alias "S", 0 0, v0x293b720_0;
+v0x28ecc00_0 .net "in0", 0 0, L_0x29c48b0; 1 drivers
+v0x28ecca0_0 .net "in1", 0 0, L_0x29c49a0; 1 drivers
+v0x28ecd40_0 .net "nS", 0 0, L_0x29c4430; 1 drivers
+v0x28ecdf0_0 .net "out0", 0 0, L_0x29c4520; 1 drivers
+v0x28ece90_0 .net "out1", 0 0, L_0x29c4630; 1 drivers
+v0x28ecf70_0 .net "outfinal", 0 0, L_0x29c46d0; 1 drivers
+S_0x28eaca0 .scope generate, "sltbits[26]" "sltbits[26]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28ea6b8 .param/l "i" 3 332, +C4<011010>;
+S_0x28eb900 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28eaca0;
+ .timescale -9 -12;
+L_0x29c4a90/d .functor NOT 1, L_0x2983190, C4<0>, C4<0>, C4<0>;
+L_0x29c4a90 .delay (10000,10000,10000) L_0x29c4a90/d;
+L_0x29c59b0/d .functor NOT 1, L_0x29c5a70, C4<0>, C4<0>, C4<0>;
+L_0x29c59b0 .delay (10000,10000,10000) L_0x29c59b0/d;
+L_0x29c5b10/d .functor AND 1, L_0x29c5c50, L_0x29c59b0, C4<1>, C4<1>;
+L_0x29c5b10 .delay (20000,20000,20000) L_0x29c5b10/d;
+L_0x29c5cf0/d .functor XOR 1, L_0x29830f0, L_0x29c5740, C4<0>, C4<0>;
+L_0x29c5cf0 .delay (40000,40000,40000) L_0x29c5cf0/d;
+L_0x29c5de0/d .functor XOR 1, L_0x29c5cf0, L_0x29832c0, C4<0>, C4<0>;
+L_0x29c5de0 .delay (40000,40000,40000) L_0x29c5de0/d;
+L_0x29c5ed0/d .functor AND 1, L_0x29830f0, L_0x29c5740, C4<1>, C4<1>;
+L_0x29c5ed0 .delay (20000,20000,20000) L_0x29c5ed0/d;
+L_0x29c6040/d .functor AND 1, L_0x29c5cf0, L_0x29832c0, C4<1>, C4<1>;
+L_0x29c6040 .delay (20000,20000,20000) L_0x29c6040/d;
+L_0x29c6130/d .functor OR 1, L_0x29c5ed0, L_0x29c6040, C4<0>, C4<0>;
+L_0x29c6130 .delay (20000,20000,20000) L_0x29c6130/d;
+v0x28ebf80_0 .net "A", 0 0, L_0x29830f0; 1 drivers
+v0x28ec040_0 .net "AandB", 0 0, L_0x29c5ed0; 1 drivers
+v0x28ec0e0_0 .net "AddSubSLTSum", 0 0, L_0x29c5de0; 1 drivers
+v0x28ec180_0 .net "AxorB", 0 0, L_0x29c5cf0; 1 drivers
+v0x28ec200_0 .net "B", 0 0, L_0x2983190; 1 drivers
+v0x28ec2b0_0 .net "BornB", 0 0, L_0x29c5740; 1 drivers
+v0x28ec370_0 .net "CINandAxorB", 0 0, L_0x29c6040; 1 drivers
+v0x28ec3f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28ec470_0 .net *"_s3", 0 0, L_0x29c5a70; 1 drivers
+v0x28ec4f0_0 .net *"_s5", 0 0, L_0x29c5c50; 1 drivers
+v0x28ec590_0 .net "carryin", 0 0, L_0x29832c0; 1 drivers
+v0x28ec630_0 .net "carryout", 0 0, L_0x29c6130; 1 drivers
+v0x28ec6d0_0 .net "nB", 0 0, L_0x29c4a90; 1 drivers
+v0x28ec780_0 .net "nCmd2", 0 0, L_0x29c59b0; 1 drivers
+v0x28ec880_0 .net "subtract", 0 0, L_0x29c5b10; 1 drivers
+L_0x29c5910 .part v0x2960210_0, 0, 1;
+L_0x29c5a70 .part v0x2960210_0, 2, 1;
+L_0x29c5c50 .part v0x2960210_0, 0, 1;
+S_0x28eb9f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28eb900;
+ .timescale -9 -12;
+L_0x29c5480/d .functor NOT 1, L_0x29c5910, C4<0>, C4<0>, C4<0>;
+L_0x29c5480 .delay (10000,10000,10000) L_0x29c5480/d;
+L_0x29c5520/d .functor AND 1, L_0x2983190, L_0x29c5480, C4<1>, C4<1>;
+L_0x29c5520 .delay (20000,20000,20000) L_0x29c5520/d;
+L_0x29c5630/d .functor AND 1, L_0x29c4a90, L_0x29c5910, C4<1>, C4<1>;
+L_0x29c5630 .delay (20000,20000,20000) L_0x29c5630/d;
+L_0x29c5740/d .functor OR 1, L_0x29c5520, L_0x29c5630, C4<0>, C4<0>;
+L_0x29c5740 .delay (20000,20000,20000) L_0x29c5740/d;
+v0x28ebae0_0 .net "S", 0 0, L_0x29c5910; 1 drivers
+v0x28ebba0_0 .alias "in0", 0 0, v0x28ec200_0;
+v0x28ebc40_0 .alias "in1", 0 0, v0x28ec6d0_0;
+v0x28ebce0_0 .net "nS", 0 0, L_0x29c5480; 1 drivers
+v0x28ebd60_0 .net "out0", 0 0, L_0x29c5520; 1 drivers
+v0x28ebe00_0 .net "out1", 0 0, L_0x29c5630; 1 drivers
+v0x28ebee0_0 .alias "outfinal", 0 0, v0x28ec2b0_0;
+S_0x28eb390 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28eaca0;
+ .timescale -9 -12;
+L_0x2983360/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x2983360 .delay (10000,10000,10000) L_0x2983360/d;
+L_0x2983400/d .functor AND 1, L_0x29c5030, L_0x2983360, C4<1>, C4<1>;
+L_0x2983400 .delay (20000,20000,20000) L_0x2983400/d;
+L_0x29c4db0/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c4db0 .delay (20000,20000,20000) L_0x29c4db0/d;
+L_0x29c4e50/d .functor OR 1, L_0x2983400, L_0x29c4db0, C4<0>, C4<0>;
+L_0x29c4e50 .delay (20000,20000,20000) L_0x29c4e50/d;
+v0x28eb480_0 .alias "S", 0 0, v0x293b720_0;
+v0x28eb520_0 .net "in0", 0 0, L_0x29c5030; 1 drivers
+v0x28eb5c0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28eb660_0 .net "nS", 0 0, L_0x2983360; 1 drivers
+v0x28eb6e0_0 .net "out0", 0 0, L_0x2983400; 1 drivers
+v0x28eb780_0 .net "out1", 0 0, L_0x29c4db0; 1 drivers
+v0x28eb860_0 .net "outfinal", 0 0, L_0x29c4e50; 1 drivers
+S_0x28eae10 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28eaca0;
+ .timescale -9 -12;
+L_0x29c51b0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c51b0 .delay (10000,10000,10000) L_0x29c51b0/d;
+L_0x29c52c0/d .functor AND 1, L_0x29c65a0, L_0x29c51b0, C4<1>, C4<1>;
+L_0x29c52c0 .delay (20000,20000,20000) L_0x29c52c0/d;
+L_0x29c53d0/d .functor AND 1, L_0x29c6690, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c53d0 .delay (20000,20000,20000) L_0x29c53d0/d;
+L_0x29c63c0/d .functor OR 1, L_0x29c52c0, L_0x29c53d0, C4<0>, C4<0>;
+L_0x29c63c0 .delay (20000,20000,20000) L_0x29c63c0/d;
+v0x28eaf00_0 .alias "S", 0 0, v0x293b720_0;
+v0x28eaf80_0 .net "in0", 0 0, L_0x29c65a0; 1 drivers
+v0x28eb020_0 .net "in1", 0 0, L_0x29c6690; 1 drivers
+v0x28eb0c0_0 .net "nS", 0 0, L_0x29c51b0; 1 drivers
+v0x28eb170_0 .net "out0", 0 0, L_0x29c52c0; 1 drivers
+v0x28eb210_0 .net "out1", 0 0, L_0x29c53d0; 1 drivers
+v0x28eb2f0_0 .net "outfinal", 0 0, L_0x29c63c0; 1 drivers
+S_0x28e8f90 .scope generate, "sltbits[27]" "sltbits[27]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28e89a8 .param/l "i" 3 332, +C4<011011>;
+S_0x28e9c80 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e8f90;
+ .timescale -9 -12;
+L_0x29c6780/d .functor NOT 1, L_0x29c75d0, C4<0>, C4<0>, C4<0>;
+L_0x29c6780 .delay (10000,10000,10000) L_0x29c6780/d;
+L_0x29c7f90/d .functor NOT 1, L_0x29c8050, C4<0>, C4<0>, C4<0>;
+L_0x29c7f90 .delay (10000,10000,10000) L_0x29c7f90/d;
+L_0x29c80f0/d .functor AND 1, L_0x29c8230, L_0x29c7f90, C4<1>, C4<1>;
+L_0x29c80f0 .delay (20000,20000,20000) L_0x29c80f0/d;
+L_0x29c82d0/d .functor XOR 1, L_0x29c7530, L_0x29c7d40, C4<0>, C4<0>;
+L_0x29c82d0 .delay (40000,40000,40000) L_0x29c82d0/d;
+L_0x29c83c0/d .functor XOR 1, L_0x29c82d0, L_0x29c7700, C4<0>, C4<0>;
+L_0x29c83c0 .delay (40000,40000,40000) L_0x29c83c0/d;
+L_0x29c84b0/d .functor AND 1, L_0x29c7530, L_0x29c7d40, C4<1>, C4<1>;
+L_0x29c84b0 .delay (20000,20000,20000) L_0x29c84b0/d;
+L_0x29c8620/d .functor AND 1, L_0x29c82d0, L_0x29c7700, C4<1>, C4<1>;
+L_0x29c8620 .delay (20000,20000,20000) L_0x29c8620/d;
+L_0x29c8710/d .functor OR 1, L_0x29c84b0, L_0x29c8620, C4<0>, C4<0>;
+L_0x29c8710 .delay (20000,20000,20000) L_0x29c8710/d;
+v0x28ea300_0 .net "A", 0 0, L_0x29c7530; 1 drivers
+v0x28ea3c0_0 .net "AandB", 0 0, L_0x29c84b0; 1 drivers
+v0x28ea460_0 .net "AddSubSLTSum", 0 0, L_0x29c83c0; 1 drivers
+v0x28ea500_0 .net "AxorB", 0 0, L_0x29c82d0; 1 drivers
+v0x28ea580_0 .net "B", 0 0, L_0x29c75d0; 1 drivers
+v0x28ea630_0 .net "BornB", 0 0, L_0x29c7d40; 1 drivers
+v0x28ea6f0_0 .net "CINandAxorB", 0 0, L_0x29c8620; 1 drivers
+v0x28ea770_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28ea7f0_0 .net *"_s3", 0 0, L_0x29c8050; 1 drivers
+v0x28ea870_0 .net *"_s5", 0 0, L_0x29c8230; 1 drivers
+v0x28ea910_0 .net "carryin", 0 0, L_0x29c7700; 1 drivers
+v0x28ea9b0_0 .net "carryout", 0 0, L_0x29c8710; 1 drivers
+v0x28eaa50_0 .net "nB", 0 0, L_0x29c6780; 1 drivers
+v0x28eab00_0 .net "nCmd2", 0 0, L_0x29c7f90; 1 drivers
+v0x28eac00_0 .net "subtract", 0 0, L_0x29c80f0; 1 drivers
+L_0x29c7ef0 .part v0x2960210_0, 0, 1;
+L_0x29c8050 .part v0x2960210_0, 2, 1;
+L_0x29c8230 .part v0x2960210_0, 0, 1;
+S_0x28e9d70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e9c80;
+ .timescale -9 -12;
+L_0x29c6950/d .functor NOT 1, L_0x29c7ef0, C4<0>, C4<0>, C4<0>;
+L_0x29c6950 .delay (10000,10000,10000) L_0x29c6950/d;
+L_0x29c6a10/d .functor AND 1, L_0x29c75d0, L_0x29c6950, C4<1>, C4<1>;
+L_0x29c6a10 .delay (20000,20000,20000) L_0x29c6a10/d;
+L_0x29c6b20/d .functor AND 1, L_0x29c6780, L_0x29c7ef0, C4<1>, C4<1>;
+L_0x29c6b20 .delay (20000,20000,20000) L_0x29c6b20/d;
+L_0x29c7d40/d .functor OR 1, L_0x29c6a10, L_0x29c6b20, C4<0>, C4<0>;
+L_0x29c7d40 .delay (20000,20000,20000) L_0x29c7d40/d;
+v0x28e9e60_0 .net "S", 0 0, L_0x29c7ef0; 1 drivers
+v0x28e9f20_0 .alias "in0", 0 0, v0x28ea580_0;
+v0x28e9fc0_0 .alias "in1", 0 0, v0x28eaa50_0;
+v0x28ea060_0 .net "nS", 0 0, L_0x29c6950; 1 drivers
+v0x28ea0e0_0 .net "out0", 0 0, L_0x29c6a10; 1 drivers
+v0x28ea180_0 .net "out1", 0 0, L_0x29c6b20; 1 drivers
+v0x28ea260_0 .alias "outfinal", 0 0, v0x28ea630_0;
+S_0x28e9710 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e8f90;
+ .timescale -9 -12;
+L_0x29c77a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c77a0 .delay (10000,10000,10000) L_0x29c77a0/d;
+L_0x29c7840/d .functor AND 1, L_0x29c7bd0, L_0x29c77a0, C4<1>, C4<1>;
+L_0x29c7840 .delay (20000,20000,20000) L_0x29c7840/d;
+L_0x29c7950/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c7950 .delay (20000,20000,20000) L_0x29c7950/d;
+L_0x29c79f0/d .functor OR 1, L_0x29c7840, L_0x29c7950, C4<0>, C4<0>;
+L_0x29c79f0 .delay (20000,20000,20000) L_0x29c79f0/d;
+v0x28e9800_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e98a0_0 .net "in0", 0 0, L_0x29c7bd0; 1 drivers
+v0x28e9940_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28e99e0_0 .net "nS", 0 0, L_0x29c77a0; 1 drivers
+v0x28e9a60_0 .net "out0", 0 0, L_0x29c7840; 1 drivers
+v0x28e9b00_0 .net "out1", 0 0, L_0x29c7950; 1 drivers
+v0x28e9be0_0 .net "outfinal", 0 0, L_0x29c79f0; 1 drivers
+S_0x28e9100 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e8f90;
+ .timescale -9 -12;
+L_0x29c4350/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c4350 .delay (10000,10000,10000) L_0x29c4350/d;
+L_0x29c94d0/d .functor AND 1, L_0x29c9870, L_0x29c4350, C4<1>, C4<1>;
+L_0x29c94d0 .delay (20000,20000,20000) L_0x29c94d0/d;
+L_0x29c95c0/d .functor AND 1, L_0x29c8a50, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c95c0 .delay (20000,20000,20000) L_0x29c95c0/d;
+L_0x29c9660/d .functor OR 1, L_0x29c94d0, L_0x29c95c0, C4<0>, C4<0>;
+L_0x29c9660 .delay (20000,20000,20000) L_0x29c9660/d;
+v0x28e91f0_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e58e0_0 .net "in0", 0 0, L_0x29c9870; 1 drivers
+v0x28e93a0_0 .net "in1", 0 0, L_0x29c8a50; 1 drivers
+v0x28e9440_0 .net "nS", 0 0, L_0x29c4350; 1 drivers
+v0x28e94f0_0 .net "out0", 0 0, L_0x29c94d0; 1 drivers
+v0x28e9590_0 .net "out1", 0 0, L_0x29c95c0; 1 drivers
+v0x28e9670_0 .net "outfinal", 0 0, L_0x29c9660; 1 drivers
+S_0x28e7310 .scope generate, "sltbits[28]" "sltbits[28]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28e6d28 .param/l "i" 3 332, +C4<011100>;
+S_0x28e7f70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e7310;
+ .timescale -9 -12;
+L_0x29c8b40/d .functor NOT 1, L_0x29c9be0, C4<0>, C4<0>, C4<0>;
+L_0x29c8b40 .delay (10000,10000,10000) L_0x29c8b40/d;
+L_0x29c9280/d .functor NOT 1, L_0x29ca2b0, C4<0>, C4<0>, C4<0>;
+L_0x29c9280 .delay (10000,10000,10000) L_0x29c9280/d;
+L_0x29ca350/d .functor AND 1, L_0x29ca440, L_0x29c9280, C4<1>, C4<1>;
+L_0x29ca350 .delay (20000,20000,20000) L_0x29ca350/d;
+L_0x29ca4e0/d .functor XOR 1, L_0x29c9b40, L_0x29c9010, C4<0>, C4<0>;
+L_0x29ca4e0 .delay (40000,40000,40000) L_0x29ca4e0/d;
+L_0x29ca5d0/d .functor XOR 1, L_0x29ca4e0, L_0x29c9d10, C4<0>, C4<0>;
+L_0x29ca5d0 .delay (40000,40000,40000) L_0x29ca5d0/d;
+L_0x29ca6c0/d .functor AND 1, L_0x29c9b40, L_0x29c9010, C4<1>, C4<1>;
+L_0x29ca6c0 .delay (20000,20000,20000) L_0x29ca6c0/d;
+L_0x29ca830/d .functor AND 1, L_0x29ca4e0, L_0x29c9d10, C4<1>, C4<1>;
+L_0x29ca830 .delay (20000,20000,20000) L_0x29ca830/d;
+L_0x29ca920/d .functor OR 1, L_0x29ca6c0, L_0x29ca830, C4<0>, C4<0>;
+L_0x29ca920 .delay (20000,20000,20000) L_0x29ca920/d;
+v0x28e85f0_0 .net "A", 0 0, L_0x29c9b40; 1 drivers
+v0x28e86b0_0 .net "AandB", 0 0, L_0x29ca6c0; 1 drivers
+v0x28e8750_0 .net "AddSubSLTSum", 0 0, L_0x29ca5d0; 1 drivers
+v0x28e87f0_0 .net "AxorB", 0 0, L_0x29ca4e0; 1 drivers
+v0x28e8870_0 .net "B", 0 0, L_0x29c9be0; 1 drivers
+v0x28e8920_0 .net "BornB", 0 0, L_0x29c9010; 1 drivers
+v0x28e89e0_0 .net "CINandAxorB", 0 0, L_0x29ca830; 1 drivers
+v0x28e8a60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28e8ae0_0 .net *"_s3", 0 0, L_0x29ca2b0; 1 drivers
+v0x28e8b60_0 .net *"_s5", 0 0, L_0x29ca440; 1 drivers
+v0x28e8c00_0 .net "carryin", 0 0, L_0x29c9d10; 1 drivers
+v0x28e8ca0_0 .net "carryout", 0 0, L_0x29ca920; 1 drivers
+v0x28e8d40_0 .net "nB", 0 0, L_0x29c8b40; 1 drivers
+v0x28e8df0_0 .net "nCmd2", 0 0, L_0x29c9280; 1 drivers
+v0x28e8ef0_0 .net "subtract", 0 0, L_0x29ca350; 1 drivers
+L_0x29c91e0 .part v0x2960210_0, 0, 1;
+L_0x29ca2b0 .part v0x2960210_0, 2, 1;
+L_0x29ca440 .part v0x2960210_0, 0, 1;
+S_0x28e8060 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e7f70;
+ .timescale -9 -12;
+L_0x29c8d30/d .functor NOT 1, L_0x29c91e0, C4<0>, C4<0>, C4<0>;
+L_0x29c8d30 .delay (10000,10000,10000) L_0x29c8d30/d;
+L_0x29c8df0/d .functor AND 1, L_0x29c9be0, L_0x29c8d30, C4<1>, C4<1>;
+L_0x29c8df0 .delay (20000,20000,20000) L_0x29c8df0/d;
+L_0x29c8f00/d .functor AND 1, L_0x29c8b40, L_0x29c91e0, C4<1>, C4<1>;
+L_0x29c8f00 .delay (20000,20000,20000) L_0x29c8f00/d;
+L_0x29c9010/d .functor OR 1, L_0x29c8df0, L_0x29c8f00, C4<0>, C4<0>;
+L_0x29c9010 .delay (20000,20000,20000) L_0x29c9010/d;
+v0x28e8150_0 .net "S", 0 0, L_0x29c91e0; 1 drivers
+v0x28e8210_0 .alias "in0", 0 0, v0x28e8870_0;
+v0x28e82b0_0 .alias "in1", 0 0, v0x28e8d40_0;
+v0x28e8350_0 .net "nS", 0 0, L_0x29c8d30; 1 drivers
+v0x28e83d0_0 .net "out0", 0 0, L_0x29c8df0; 1 drivers
+v0x28e8470_0 .net "out1", 0 0, L_0x29c8f00; 1 drivers
+v0x28e8550_0 .alias "outfinal", 0 0, v0x28e8920_0;
+S_0x28e7a00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e7310;
+ .timescale -9 -12;
+L_0x29c9db0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29c9db0 .delay (10000,10000,10000) L_0x29c9db0/d;
+L_0x29c9e50/d .functor AND 1, L_0x29ca1e0, L_0x29c9db0, C4<1>, C4<1>;
+L_0x29c9e50 .delay (20000,20000,20000) L_0x29c9e50/d;
+L_0x29c9f60/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29c9f60 .delay (20000,20000,20000) L_0x29c9f60/d;
+L_0x29ca000/d .functor OR 1, L_0x29c9e50, L_0x29c9f60, C4<0>, C4<0>;
+L_0x29ca000 .delay (20000,20000,20000) L_0x29ca000/d;
+v0x28e7af0_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e7b90_0 .net "in0", 0 0, L_0x29ca1e0; 1 drivers
+v0x28e7c30_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28e7cd0_0 .net "nS", 0 0, L_0x29c9db0; 1 drivers
+v0x28e7d50_0 .net "out0", 0 0, L_0x29c9e50; 1 drivers
+v0x28e7df0_0 .net "out1", 0 0, L_0x29c9f60; 1 drivers
+v0x28e7ed0_0 .net "outfinal", 0 0, L_0x29ca000; 1 drivers
+S_0x28e7480 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e7310;
+ .timescale -9 -12;
+L_0x29cb5c0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29cb5c0 .delay (10000,10000,10000) L_0x29cb5c0/d;
+L_0x29cb6b0/d .functor AND 1, L_0x29cab50, L_0x29cb5c0, C4<1>, C4<1>;
+L_0x29cb6b0 .delay (20000,20000,20000) L_0x29cb6b0/d;
+L_0x29cb7a0/d .functor AND 1, L_0x29cac40, L_0x29d1680, C4<1>, C4<1>;
+L_0x29cb7a0 .delay (20000,20000,20000) L_0x29cb7a0/d;
+L_0x29cb840/d .functor OR 1, L_0x29cb6b0, L_0x29cb7a0, C4<0>, C4<0>;
+L_0x29cb840 .delay (20000,20000,20000) L_0x29cb840/d;
+v0x28e7570_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e75f0_0 .net "in0", 0 0, L_0x29cab50; 1 drivers
+v0x28e7690_0 .net "in1", 0 0, L_0x29cac40; 1 drivers
+v0x28e7730_0 .net "nS", 0 0, L_0x29cb5c0; 1 drivers
+v0x28e77e0_0 .net "out0", 0 0, L_0x29cb6b0; 1 drivers
+v0x28e7880_0 .net "out1", 0 0, L_0x29cb7a0; 1 drivers
+v0x28e7960_0 .net "outfinal", 0 0, L_0x29cb840; 1 drivers
+S_0x28e5600 .scope generate, "sltbits[29]" "sltbits[29]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28e4fc8 .param/l "i" 3 332, +C4<011101>;
+S_0x28e62f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e5600;
+ .timescale -9 -12;
+L_0x29cad30/d .functor NOT 1, L_0x29cbbe0, C4<0>, C4<0>, C4<0>;
+L_0x29cad30 .delay (10000,10000,10000) L_0x29cad30/d;
+L_0x29cb470/d .functor NOT 1, L_0x29cc440, C4<0>, C4<0>, C4<0>;
+L_0x29cb470 .delay (10000,10000,10000) L_0x29cb470/d;
+L_0x29cc4e0/d .functor AND 1, L_0x29cc620, L_0x29cb470, C4<1>, C4<1>;
+L_0x29cc4e0 .delay (20000,20000,20000) L_0x29cc4e0/d;
+L_0x29cc6c0/d .functor XOR 1, L_0x29cbb40, L_0x29cb200, C4<0>, C4<0>;
+L_0x29cc6c0 .delay (40000,40000,40000) L_0x29cc6c0/d;
+L_0x29cc7b0/d .functor XOR 1, L_0x29cc6c0, L_0x29cbd10, C4<0>, C4<0>;
+L_0x29cc7b0 .delay (40000,40000,40000) L_0x29cc7b0/d;
+L_0x29cc8a0/d .functor AND 1, L_0x29cbb40, L_0x29cb200, C4<1>, C4<1>;
+L_0x29cc8a0 .delay (20000,20000,20000) L_0x29cc8a0/d;
+L_0x29cca10/d .functor AND 1, L_0x29cc6c0, L_0x29cbd10, C4<1>, C4<1>;
+L_0x29cca10 .delay (20000,20000,20000) L_0x29cca10/d;
+L_0x29ccb00/d .functor OR 1, L_0x29cc8a0, L_0x29cca10, C4<0>, C4<0>;
+L_0x29ccb00 .delay (20000,20000,20000) L_0x29ccb00/d;
+v0x28e6970_0 .net "A", 0 0, L_0x29cbb40; 1 drivers
+v0x28e6a30_0 .net "AandB", 0 0, L_0x29cc8a0; 1 drivers
+v0x28e6ad0_0 .net "AddSubSLTSum", 0 0, L_0x29cc7b0; 1 drivers
+v0x28e6b70_0 .net "AxorB", 0 0, L_0x29cc6c0; 1 drivers
+v0x28e6bf0_0 .net "B", 0 0, L_0x29cbbe0; 1 drivers
+v0x28e6ca0_0 .net "BornB", 0 0, L_0x29cb200; 1 drivers
+v0x28e6d60_0 .net "CINandAxorB", 0 0, L_0x29cca10; 1 drivers
+v0x28e6de0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28e6e60_0 .net *"_s3", 0 0, L_0x29cc440; 1 drivers
+v0x28e6ee0_0 .net *"_s5", 0 0, L_0x29cc620; 1 drivers
+v0x28e6f80_0 .net "carryin", 0 0, L_0x29cbd10; 1 drivers
+v0x28e7020_0 .net "carryout", 0 0, L_0x29ccb00; 1 drivers
+v0x28e70c0_0 .net "nB", 0 0, L_0x29cad30; 1 drivers
+v0x28e7170_0 .net "nCmd2", 0 0, L_0x29cb470; 1 drivers
+v0x28e7270_0 .net "subtract", 0 0, L_0x29cc4e0; 1 drivers
+L_0x29cb3d0 .part v0x2960210_0, 0, 1;
+L_0x29cc440 .part v0x2960210_0, 2, 1;
+L_0x29cc620 .part v0x2960210_0, 0, 1;
+S_0x28e63e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e62f0;
+ .timescale -9 -12;
+L_0x29caf20/d .functor NOT 1, L_0x29cb3d0, C4<0>, C4<0>, C4<0>;
+L_0x29caf20 .delay (10000,10000,10000) L_0x29caf20/d;
+L_0x29cafe0/d .functor AND 1, L_0x29cbbe0, L_0x29caf20, C4<1>, C4<1>;
+L_0x29cafe0 .delay (20000,20000,20000) L_0x29cafe0/d;
+L_0x29cb0f0/d .functor AND 1, L_0x29cad30, L_0x29cb3d0, C4<1>, C4<1>;
+L_0x29cb0f0 .delay (20000,20000,20000) L_0x29cb0f0/d;
+L_0x29cb200/d .functor OR 1, L_0x29cafe0, L_0x29cb0f0, C4<0>, C4<0>;
+L_0x29cb200 .delay (20000,20000,20000) L_0x29cb200/d;
+v0x28e64d0_0 .net "S", 0 0, L_0x29cb3d0; 1 drivers
+v0x28e6590_0 .alias "in0", 0 0, v0x28e6bf0_0;
+v0x28e6630_0 .alias "in1", 0 0, v0x28e70c0_0;
+v0x28e66d0_0 .net "nS", 0 0, L_0x29caf20; 1 drivers
+v0x28e6750_0 .net "out0", 0 0, L_0x29cafe0; 1 drivers
+v0x28e67f0_0 .net "out1", 0 0, L_0x29cb0f0; 1 drivers
+v0x28e68d0_0 .alias "outfinal", 0 0, v0x28e6ca0_0;
+S_0x28e5d80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e5600;
+ .timescale -9 -12;
+L_0x29cbdb0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29cbdb0 .delay (10000,10000,10000) L_0x29cbdb0/d;
+L_0x29cbe50/d .functor AND 1, L_0x29cc1e0, L_0x29cbdb0, C4<1>, C4<1>;
+L_0x29cbe50 .delay (20000,20000,20000) L_0x29cbe50/d;
+L_0x29cbf60/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29cbf60 .delay (20000,20000,20000) L_0x29cbf60/d;
+L_0x29cc000/d .functor OR 1, L_0x29cbe50, L_0x29cbf60, C4<0>, C4<0>;
+L_0x29cc000 .delay (20000,20000,20000) L_0x29cc000/d;
+v0x28e5e70_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e5f10_0 .net "in0", 0 0, L_0x29cc1e0; 1 drivers
+v0x28e5fb0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28e6050_0 .net "nS", 0 0, L_0x29cbdb0; 1 drivers
+v0x28e60d0_0 .net "out0", 0 0, L_0x29cbe50; 1 drivers
+v0x28e6170_0 .net "out1", 0 0, L_0x29cbf60; 1 drivers
+v0x28e6250_0 .net "outfinal", 0 0, L_0x29cc000; 1 drivers
+S_0x28e5770 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e5600;
+ .timescale -9 -12;
+L_0x29cc360/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29cc360 .delay (10000,10000,10000) L_0x29cc360/d;
+L_0x29c9450/d .functor AND 1, L_0x29aa0f0, L_0x29cc360, C4<1>, C4<1>;
+L_0x29c9450 .delay (20000,20000,20000) L_0x29c9450/d;
+L_0x29cd9c0/d .functor AND 1, L_0x29aa1e0, L_0x29d1680, C4<1>, C4<1>;
+L_0x29cd9c0 .delay (20000,20000,20000) L_0x29cd9c0/d;
+L_0x29cda60/d .functor OR 1, L_0x29c9450, L_0x29cd9c0, C4<0>, C4<0>;
+L_0x29cda60 .delay (20000,20000,20000) L_0x29cda60/d;
+v0x28e5860_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e5970_0 .net "in0", 0 0, L_0x29aa0f0; 1 drivers
+v0x28e5a10_0 .net "in1", 0 0, L_0x29aa1e0; 1 drivers
+v0x28e5ab0_0 .net "nS", 0 0, L_0x29cc360; 1 drivers
+v0x28e5b60_0 .net "out0", 0 0, L_0x29c9450; 1 drivers
+v0x28e5c00_0 .net "out1", 0 0, L_0x29cd9c0; 1 drivers
+v0x28e5ce0_0 .net "outfinal", 0 0, L_0x29cda60; 1 drivers
+S_0x28e3960 .scope generate, "sltbits[30]" "sltbits[30]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28e3258 .param/l "i" 3 332, +C4<011110>;
+S_0x28e4590 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e3960;
+ .timescale -9 -12;
+L_0x29cce40/d .functor NOT 1, L_0x29ce2d0, C4<0>, C4<0>, C4<0>;
+L_0x29cce40 .delay (10000,10000,10000) L_0x29cce40/d;
+L_0x29cd560/d .functor NOT 1, L_0x29cd620, C4<0>, C4<0>, C4<0>;
+L_0x29cd560 .delay (10000,10000,10000) L_0x29cd560/d;
+L_0x29cd6c0/d .functor AND 1, L_0x29cea50, L_0x29cd560, C4<1>, C4<1>;
+L_0x29cd6c0 .delay (20000,20000,20000) L_0x29cd6c0/d;
+L_0x29ceaf0/d .functor XOR 1, L_0x29ce230, L_0x29cd2f0, C4<0>, C4<0>;
+L_0x29ceaf0 .delay (40000,40000,40000) L_0x29ceaf0/d;
+L_0x29cebe0/d .functor XOR 1, L_0x29ceaf0, L_0x29ce400, C4<0>, C4<0>;
+L_0x29cebe0 .delay (40000,40000,40000) L_0x29cebe0/d;
+L_0x29cecd0/d .functor AND 1, L_0x29ce230, L_0x29cd2f0, C4<1>, C4<1>;
+L_0x29cecd0 .delay (20000,20000,20000) L_0x29cecd0/d;
+L_0x29cee40/d .functor AND 1, L_0x29ceaf0, L_0x29ce400, C4<1>, C4<1>;
+L_0x29cee40 .delay (20000,20000,20000) L_0x29cee40/d;
+L_0x29cef30/d .functor OR 1, L_0x29cecd0, L_0x29cee40, C4<0>, C4<0>;
+L_0x29cef30 .delay (20000,20000,20000) L_0x29cef30/d;
+v0x28e4c10_0 .net "A", 0 0, L_0x29ce230; 1 drivers
+v0x28e4cd0_0 .net "AandB", 0 0, L_0x29cecd0; 1 drivers
+v0x28e4d70_0 .net "AddSubSLTSum", 0 0, L_0x29cebe0; 1 drivers
+v0x28e4e10_0 .net "AxorB", 0 0, L_0x29ceaf0; 1 drivers
+v0x28e4e90_0 .net "B", 0 0, L_0x29ce2d0; 1 drivers
+v0x28e4f40_0 .net "BornB", 0 0, L_0x29cd2f0; 1 drivers
+v0x28e5000_0 .net "CINandAxorB", 0 0, L_0x29cee40; 1 drivers
+v0x28e5080_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28e5150_0 .net *"_s3", 0 0, L_0x29cd620; 1 drivers
+v0x28e51d0_0 .net *"_s5", 0 0, L_0x29cea50; 1 drivers
+v0x28e5270_0 .net "carryin", 0 0, L_0x29ce400; 1 drivers
+v0x28e5310_0 .net "carryout", 0 0, L_0x29cef30; 1 drivers
+v0x28e53b0_0 .net "nB", 0 0, L_0x29cce40; 1 drivers
+v0x28e5460_0 .net "nCmd2", 0 0, L_0x29cd560; 1 drivers
+v0x28e5560_0 .net "subtract", 0 0, L_0x29cd6c0; 1 drivers
+L_0x29cd4c0 .part v0x2960210_0, 0, 1;
+L_0x29cd620 .part v0x2960210_0, 2, 1;
+L_0x29cea50 .part v0x2960210_0, 0, 1;
+S_0x28e4680 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e4590;
+ .timescale -9 -12;
+L_0x29cd010/d .functor NOT 1, L_0x29cd4c0, C4<0>, C4<0>, C4<0>;
+L_0x29cd010 .delay (10000,10000,10000) L_0x29cd010/d;
+L_0x29cd0d0/d .functor AND 1, L_0x29ce2d0, L_0x29cd010, C4<1>, C4<1>;
+L_0x29cd0d0 .delay (20000,20000,20000) L_0x29cd0d0/d;
+L_0x29cd1e0/d .functor AND 1, L_0x29cce40, L_0x29cd4c0, C4<1>, C4<1>;
+L_0x29cd1e0 .delay (20000,20000,20000) L_0x29cd1e0/d;
+L_0x29cd2f0/d .functor OR 1, L_0x29cd0d0, L_0x29cd1e0, C4<0>, C4<0>;
+L_0x29cd2f0 .delay (20000,20000,20000) L_0x29cd2f0/d;
+v0x28e4770_0 .net "S", 0 0, L_0x29cd4c0; 1 drivers
+v0x28e4830_0 .alias "in0", 0 0, v0x28e4e90_0;
+v0x28e48d0_0 .alias "in1", 0 0, v0x28e53b0_0;
+v0x28e4970_0 .net "nS", 0 0, L_0x29cd010; 1 drivers
+v0x28e49f0_0 .net "out0", 0 0, L_0x29cd0d0; 1 drivers
+v0x28e4a90_0 .net "out1", 0 0, L_0x29cd1e0; 1 drivers
+v0x28e4b70_0 .alias "outfinal", 0 0, v0x28e4f40_0;
+S_0x28e4020 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e3960;
+ .timescale -9 -12;
+L_0x29ce4a0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29ce4a0 .delay (10000,10000,10000) L_0x29ce4a0/d;
+L_0x29ce540/d .functor AND 1, L_0x29ce8d0, L_0x29ce4a0, C4<1>, C4<1>;
+L_0x29ce540 .delay (20000,20000,20000) L_0x29ce540/d;
+L_0x29ce650/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29ce650 .delay (20000,20000,20000) L_0x29ce650/d;
+L_0x29ce6f0/d .functor OR 1, L_0x29ce540, L_0x29ce650, C4<0>, C4<0>;
+L_0x29ce6f0 .delay (20000,20000,20000) L_0x29ce6f0/d;
+v0x28e4110_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e41b0_0 .net "in0", 0 0, L_0x29ce8d0; 1 drivers
+v0x28e4250_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28e42f0_0 .net "nS", 0 0, L_0x29ce4a0; 1 drivers
+v0x28e4370_0 .net "out0", 0 0, L_0x29ce540; 1 drivers
+v0x28e4410_0 .net "out1", 0 0, L_0x29ce650; 1 drivers
+v0x28e44f0_0 .net "outfinal", 0 0, L_0x29ce6f0; 1 drivers
+S_0x28e3ad0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e3960;
+ .timescale -9 -12;
+L_0x29cfba0/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29cfba0 .delay (10000,10000,10000) L_0x29cfba0/d;
+L_0x29cfc90/d .functor AND 1, L_0x29cf160, L_0x29cfba0, C4<1>, C4<1>;
+L_0x29cfc90 .delay (20000,20000,20000) L_0x29cfc90/d;
+L_0x29cfd80/d .functor AND 1, L_0x29cf250, L_0x29d1680, C4<1>, C4<1>;
+L_0x29cfd80 .delay (20000,20000,20000) L_0x29cfd80/d;
+L_0x29cfe20/d .functor OR 1, L_0x29cfc90, L_0x29cfd80, C4<0>, C4<0>;
+L_0x29cfe20 .delay (20000,20000,20000) L_0x29cfe20/d;
+v0x28e3bc0_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e3c40_0 .net "in0", 0 0, L_0x29cf160; 1 drivers
+v0x28e3ce0_0 .net "in1", 0 0, L_0x29cf250; 1 drivers
+v0x28e3d80_0 .net "nS", 0 0, L_0x29cfba0; 1 drivers
+v0x28e3e00_0 .net "out0", 0 0, L_0x29cfc90; 1 drivers
+v0x28e3ea0_0 .net "out1", 0 0, L_0x29cfd80; 1 drivers
+v0x28e3f80_0 .net "outfinal", 0 0, L_0x29cfe20; 1 drivers
+S_0x28e1bc0 .scope generate, "sltbits[31]" "sltbits[31]" 3 332, 3 332, S_0x28e1a50;
+ .timescale -9 -12;
+P_0x28e1cb8 .param/l "i" 3 332, +C4<011111>;
+S_0x28e2820 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28e1bc0;
+ .timescale -9 -12;
+L_0x29cf340/d .functor NOT 1, L_0x29d01c0, C4<0>, C4<0>, C4<0>;
+L_0x29cf340 .delay (10000,10000,10000) L_0x29cf340/d;
+L_0x29cfa80/d .functor NOT 1, L_0x29d0a90, C4<0>, C4<0>, C4<0>;
+L_0x29cfa80 .delay (10000,10000,10000) L_0x29cfa80/d;
+L_0x29cfb40/d .functor AND 1, L_0x29d0c10, L_0x29cfa80, C4<1>, C4<1>;
+L_0x29cfb40 .delay (20000,20000,20000) L_0x29cfb40/d;
+L_0x29d0cb0/d .functor XOR 1, L_0x29d0120, L_0x29cf810, C4<0>, C4<0>;
+L_0x29d0cb0 .delay (40000,40000,40000) L_0x29d0cb0/d;
+L_0x29d0da0/d .functor XOR 1, L_0x29d0cb0, L_0x29d02f0, C4<0>, C4<0>;
+L_0x29d0da0 .delay (40000,40000,40000) L_0x29d0da0/d;
+L_0x29d0e90/d .functor AND 1, L_0x29d0120, L_0x29cf810, C4<1>, C4<1>;
+L_0x29d0e90 .delay (20000,20000,20000) L_0x29d0e90/d;
+L_0x29d1000/d .functor AND 1, L_0x29d0cb0, L_0x29d02f0, C4<1>, C4<1>;
+L_0x29d1000 .delay (20000,20000,20000) L_0x29d1000/d;
+L_0x29d10f0/d .functor OR 1, L_0x29d0e90, L_0x29d1000, C4<0>, C4<0>;
+L_0x29d10f0 .delay (20000,20000,20000) L_0x29d10f0/d;
+v0x28e2ea0_0 .net "A", 0 0, L_0x29d0120; 1 drivers
+v0x28e2f60_0 .net "AandB", 0 0, L_0x29d0e90; 1 drivers
+v0x28e3000_0 .net "AddSubSLTSum", 0 0, L_0x29d0da0; 1 drivers
+v0x28e30a0_0 .net "AxorB", 0 0, L_0x29d0cb0; 1 drivers
+v0x28e3120_0 .net "B", 0 0, L_0x29d01c0; 1 drivers
+v0x28e31d0_0 .net "BornB", 0 0, L_0x29cf810; 1 drivers
+v0x28e3290_0 .net "CINandAxorB", 0 0, L_0x29d1000; 1 drivers
+v0x28e3310_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28e33e0_0 .net *"_s3", 0 0, L_0x29d0a90; 1 drivers
+v0x28e3460_0 .net *"_s5", 0 0, L_0x29d0c10; 1 drivers
+v0x28e3560_0 .net "carryin", 0 0, L_0x29d02f0; 1 drivers
+v0x28e3600_0 .net "carryout", 0 0, L_0x29d10f0; 1 drivers
+v0x28e3710_0 .net "nB", 0 0, L_0x29cf340; 1 drivers
+v0x28e37c0_0 .net "nCmd2", 0 0, L_0x29cfa80; 1 drivers
+v0x28e38c0_0 .net "subtract", 0 0, L_0x29cfb40; 1 drivers
+L_0x29cf9e0 .part v0x2960210_0, 0, 1;
+L_0x29d0a90 .part v0x2960210_0, 2, 1;
+L_0x29d0c10 .part v0x2960210_0, 0, 1;
+S_0x28e2910 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28e2820;
+ .timescale -9 -12;
+L_0x29cf530/d .functor NOT 1, L_0x29cf9e0, C4<0>, C4<0>, C4<0>;
+L_0x29cf530 .delay (10000,10000,10000) L_0x29cf530/d;
+L_0x29cf5f0/d .functor AND 1, L_0x29d01c0, L_0x29cf530, C4<1>, C4<1>;
+L_0x29cf5f0 .delay (20000,20000,20000) L_0x29cf5f0/d;
+L_0x29cf700/d .functor AND 1, L_0x29cf340, L_0x29cf9e0, C4<1>, C4<1>;
+L_0x29cf700 .delay (20000,20000,20000) L_0x29cf700/d;
+L_0x29cf810/d .functor OR 1, L_0x29cf5f0, L_0x29cf700, C4<0>, C4<0>;
+L_0x29cf810 .delay (20000,20000,20000) L_0x29cf810/d;
+v0x28e2a00_0 .net "S", 0 0, L_0x29cf9e0; 1 drivers
+v0x28e2ac0_0 .alias "in0", 0 0, v0x28e3120_0;
+v0x28e2b60_0 .alias "in1", 0 0, v0x28e3710_0;
+v0x28e2c00_0 .net "nS", 0 0, L_0x29cf530; 1 drivers
+v0x28e2c80_0 .net "out0", 0 0, L_0x29cf5f0; 1 drivers
+v0x28e2d20_0 .net "out1", 0 0, L_0x29cf700; 1 drivers
+v0x28e2e00_0 .alias "outfinal", 0 0, v0x28e31d0_0;
+S_0x28e22a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28e1bc0;
+ .timescale -9 -12;
+L_0x29d0390/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29d0390 .delay (10000,10000,10000) L_0x29d0390/d;
+L_0x29d0430/d .functor AND 1, L_0x29d07c0, L_0x29d0390, C4<1>, C4<1>;
+L_0x29d0430 .delay (20000,20000,20000) L_0x29d0430/d;
+L_0x29d0540/d .functor AND 1, C4<0>, L_0x29d1680, C4<1>, C4<1>;
+L_0x29d0540 .delay (20000,20000,20000) L_0x29d0540/d;
+L_0x29d05e0/d .functor OR 1, L_0x29d0430, L_0x29d0540, C4<0>, C4<0>;
+L_0x29d05e0 .delay (20000,20000,20000) L_0x29d05e0/d;
+v0x28e2390_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e2430_0 .net "in0", 0 0, L_0x29d07c0; 1 drivers
+v0x28e24b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28e2550_0 .net "nS", 0 0, L_0x29d0390; 1 drivers
+v0x28e2600_0 .net "out0", 0 0, L_0x29d0430; 1 drivers
+v0x28e26a0_0 .net "out1", 0 0, L_0x29d0540; 1 drivers
+v0x28e2780_0 .net "outfinal", 0 0, L_0x29d05e0; 1 drivers
+S_0x28e1d30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28e1bc0;
+ .timescale -9 -12;
+L_0x29cd830/d .functor NOT 1, L_0x29d1680, C4<0>, C4<0>, C4<0>;
+L_0x29cd830 .delay (10000,10000,10000) L_0x29cd830/d;
+L_0x29d1eb0/d .functor AND 1, L_0x29d2220, L_0x29cd830, C4<1>, C4<1>;
+L_0x29d1eb0 .delay (20000,20000,20000) L_0x29d1eb0/d;
+L_0x29d1fa0/d .functor AND 1, L_0x29d1410, L_0x29d1680, C4<1>, C4<1>;
+L_0x29d1fa0 .delay (20000,20000,20000) L_0x29d1fa0/d;
+L_0x29d2040/d .functor OR 1, L_0x29d1eb0, L_0x29d1fa0, C4<0>, C4<0>;
+L_0x29d2040 .delay (20000,20000,20000) L_0x29d2040/d;
+v0x28e1e20_0 .alias "S", 0 0, v0x293b720_0;
+v0x28e1ec0_0 .net "in0", 0 0, L_0x29d2220; 1 drivers
+v0x28e1f60_0 .net "in1", 0 0, L_0x29d1410; 1 drivers
+v0x28e2000_0 .net "nS", 0 0, L_0x29cd830; 1 drivers
+v0x28e2080_0 .net "out0", 0 0, L_0x29d1eb0; 1 drivers
+v0x28e2120_0 .net "out1", 0 0, L_0x29d1fa0; 1 drivers
+v0x28e2200_0 .net "outfinal", 0 0, L_0x29d2040; 1 drivers
+S_0x28ca040 .scope module, "trial1" "AndNand32" 2 158, 3 216, S_0x22efd20;
+ .timescale -9 -12;
+P_0x28c9b58 .param/l "size" 3 223, +C4<0100000>;
+v0x28e1800_0 .alias "A", 31 0, v0x295f580_0;
+v0x28e1880_0 .alias "AndNandOut", 31 0, v0x2960110_0;
+v0x28e1950_0 .alias "B", 31 0, v0x295f6a0_0;
+v0x28e19d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d55b0 .part/pv L_0x29d5340, 1, 1, 32;
+L_0x29d5700 .part v0x295fe90_0, 1, 1;
+L_0x29d57a0 .part v0x2960190_0, 1, 1;
+L_0x29d72e0 .part/pv L_0x29d7070, 2, 1, 32;
+L_0x29d7380 .part v0x295fe90_0, 2, 1;
+L_0x29d7420 .part v0x2960190_0, 2, 1;
+L_0x29d7d50 .part/pv L_0x29d7ae0, 3, 1, 32;
+L_0x29d7df0 .part v0x295fe90_0, 3, 1;
+L_0x29d7ee0 .part v0x2960190_0, 3, 1;
+L_0x29d87b0 .part/pv L_0x29d8540, 4, 1, 32;
+L_0x29d88b0 .part v0x295fe90_0, 4, 1;
+L_0x29d8950 .part v0x2960190_0, 4, 1;
+L_0x29d9220 .part/pv L_0x29d8fb0, 5, 1, 32;
+L_0x29d93d0 .part v0x295fe90_0, 5, 1;
+L_0x29d9470 .part v0x2960190_0, 5, 1;
+L_0x29d9d80 .part/pv L_0x29d9b10, 6, 1, 32;
+L_0x29d9e20 .part v0x295fe90_0, 6, 1;
+L_0x29d9ec0 .part v0x2960190_0, 6, 1;
+L_0x29da7f0 .part/pv L_0x29da580, 7, 1, 32;
+L_0x29da890 .part v0x295fe90_0, 7, 1;
+L_0x29d9fb0 .part v0x2960190_0, 7, 1;
+L_0x29db250 .part/pv L_0x29dafe0, 8, 1, 32;
+L_0x29da930 .part v0x295fe90_0, 8, 1;
+L_0x29db3b0 .part v0x2960190_0, 8, 1;
+L_0x29dbcd0 .part/pv L_0x29dba60, 9, 1, 32;
+L_0x29dbd70 .part v0x295fe90_0, 9, 1;
+L_0x29db4a0 .part v0x2960190_0, 9, 1;
+L_0x29dc740 .part/pv L_0x29dc4d0, 10, 1, 32;
+L_0x29dbe10 .part v0x295fe90_0, 10, 1;
+L_0x29dc8d0 .part v0x2960190_0, 10, 1;
+L_0x29dd1b0 .part/pv L_0x29dcf40, 11, 1, 32;
+L_0x29dd250 .part v0x295fe90_0, 11, 1;
+L_0x29dc9c0 .part v0x2960190_0, 11, 1;
+L_0x29ddc20 .part/pv L_0x29dd9b0, 12, 1, 32;
+L_0x29dd2f0 .part v0x295fe90_0, 12, 1;
+L_0x29ddde0 .part v0x2960190_0, 12, 1;
+L_0x29de6a0 .part/pv L_0x29de430, 13, 1, 32;
+L_0x29d92c0 .part v0x295fe90_0, 13, 1;
+L_0x29dde80 .part v0x2960190_0, 13, 1;
+L_0x29df210 .part/pv L_0x29defa0, 14, 1, 32;
+L_0x29de950 .part v0x295fe90_0, 14, 1;
+L_0x29de9f0 .part v0x2960190_0, 14, 1;
+L_0x29dfc80 .part/pv L_0x29dfa10, 15, 1, 32;
+L_0x29dfd20 .part v0x295fe90_0, 15, 1;
+L_0x29df450 .part v0x2960190_0, 15, 1;
+L_0x29e06f0 .part/pv L_0x29e0480, 16, 1, 32;
+L_0x29dfdc0 .part v0x295fe90_0, 16, 1;
+L_0x29dfe60 .part v0x2960190_0, 16, 1;
+L_0x29e1170 .part/pv L_0x29e0f00, 17, 1, 32;
+L_0x29e1210 .part v0x295fe90_0, 17, 1;
+L_0x29e0960 .part v0x2960190_0, 17, 1;
+L_0x29e1bd0 .part/pv L_0x29e1960, 18, 1, 32;
+L_0x29e12b0 .part v0x295fe90_0, 18, 1;
+L_0x29e1350 .part v0x2960190_0, 18, 1;
+L_0x29e2650 .part/pv L_0x29e23e0, 19, 1, 32;
+L_0x29e26f0 .part v0x295fe90_0, 19, 1;
+L_0x29e1c70 .part v0x2960190_0, 19, 1;
+L_0x29e30b0 .part/pv L_0x29e2e40, 20, 1, 32;
+L_0x29e2790 .part v0x295fe90_0, 20, 1;
+L_0x29e2830 .part v0x2960190_0, 20, 1;
+L_0x29e3b20 .part/pv L_0x29e38b0, 21, 1, 32;
+L_0x29e3bc0 .part v0x295fe90_0, 21, 1;
+L_0x29e3150 .part v0x2960190_0, 21, 1;
+L_0x29e4590 .part/pv L_0x29e4320, 22, 1, 32;
+L_0x29e3c60 .part v0x295fe90_0, 22, 1;
+L_0x29e3d00 .part v0x2960190_0, 22, 1;
+L_0x29e5010 .part/pv L_0x29e4da0, 23, 1, 32;
+L_0x29e50b0 .part v0x295fe90_0, 23, 1;
+L_0x29e4630 .part v0x2960190_0, 23, 1;
+L_0x29e5a70 .part/pv L_0x29e5800, 24, 1, 32;
+L_0x29e5150 .part v0x295fe90_0, 24, 1;
+L_0x29e51f0 .part v0x2960190_0, 24, 1;
+L_0x29e64e0 .part/pv L_0x29e6270, 25, 1, 32;
+L_0x29e6580 .part v0x295fe90_0, 25, 1;
+L_0x29e5b10 .part v0x2960190_0, 25, 1;
+L_0x29e6f40 .part/pv L_0x29e6cd0, 26, 1, 32;
+L_0x29e6620 .part v0x295fe90_0, 26, 1;
+L_0x29e66c0 .part v0x2960190_0, 26, 1;
+L_0x29e79b0 .part/pv L_0x29e7740, 27, 1, 32;
+L_0x29e7a50 .part v0x295fe90_0, 27, 1;
+L_0x29e6fe0 .part v0x2960190_0, 27, 1;
+L_0x29e8420 .part/pv L_0x29e81b0, 28, 1, 32;
+L_0x29e7af0 .part v0x295fe90_0, 28, 1;
+L_0x29e7b90 .part v0x2960190_0, 28, 1;
+L_0x29e8ea0 .part/pv L_0x29e8c30, 29, 1, 32;
+L_0x29de740 .part v0x295fe90_0, 29, 1;
+L_0x29de7e0 .part v0x2960190_0, 29, 1;
+L_0x29e9a60 .part/pv L_0x29e9830, 30, 1, 32;
+L_0x29e9350 .part v0x295fe90_0, 30, 1;
+L_0x29e93f0 .part v0x2960190_0, 30, 1;
+L_0x29ea410 .part/pv L_0x29ea1e0, 31, 1, 32;
+L_0x29ea4b0 .part v0x295fe90_0, 31, 1;
+L_0x29e9b00 .part v0x2960190_0, 31, 1;
+L_0x29eadc0 .part/pv L_0x29eab90, 0, 1, 32;
+L_0x29ea550 .part v0x295fe90_0, 0, 1;
+L_0x29ea5f0 .part v0x2960190_0, 0, 1;
+S_0x28e0dd0 .scope module, "attempt2" "AndNand" 3 227, 3 149, S_0x28ca040;
+ .timescale -9 -12;
+L_0x29e9bf0/d .functor NAND 1, L_0x29ea550, L_0x29ea5f0, C4<1>, C4<1>;
+L_0x29e9bf0 .delay (10000,10000,10000) L_0x29e9bf0/d;
+L_0x29e9d50/d .functor NOT 1, L_0x29e9bf0, C4<0>, C4<0>, C4<0>;
+L_0x29e9d50 .delay (10000,10000,10000) L_0x29e9d50/d;
+v0x28e13f0_0 .net "A", 0 0, L_0x29ea550; 1 drivers
+v0x28e14b0_0 .net "AandB", 0 0, L_0x29e9d50; 1 drivers
+v0x28e1530_0 .net "AnandB", 0 0, L_0x29e9bf0; 1 drivers
+v0x28e15e0_0 .net "AndNandOut", 0 0, L_0x29eab90; 1 drivers
+v0x28e16c0_0 .net "B", 0 0, L_0x29ea5f0; 1 drivers
+v0x28e1740_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29ead20 .part v0x2960210_0, 0, 1;
+S_0x28e0ec0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28e0dd0;
+ .timescale -9 -12;
+L_0x29ea8d0/d .functor NOT 1, L_0x29ead20, C4<0>, C4<0>, C4<0>;
+L_0x29ea8d0 .delay (10000,10000,10000) L_0x29ea8d0/d;
+L_0x29ea970/d .functor AND 1, L_0x29e9d50, L_0x29ea8d0, C4<1>, C4<1>;
+L_0x29ea970 .delay (20000,20000,20000) L_0x29ea970/d;
+L_0x29eaa60/d .functor AND 1, L_0x29e9bf0, L_0x29ead20, C4<1>, C4<1>;
+L_0x29eaa60 .delay (20000,20000,20000) L_0x29eaa60/d;
+L_0x29eab90/d .functor OR 1, L_0x29ea970, L_0x29eaa60, C4<0>, C4<0>;
+L_0x29eab90 .delay (20000,20000,20000) L_0x29eab90/d;
+v0x28e0fb0_0 .net "S", 0 0, L_0x29ead20; 1 drivers
+v0x28e1030_0 .alias "in0", 0 0, v0x28e14b0_0;
+v0x28e10b0_0 .alias "in1", 0 0, v0x28e1530_0;
+v0x28e1150_0 .net "nS", 0 0, L_0x29ea8d0; 1 drivers
+v0x28e11d0_0 .net "out0", 0 0, L_0x29ea970; 1 drivers
+v0x28e1270_0 .net "out1", 0 0, L_0x29eaa60; 1 drivers
+v0x28e1350_0 .alias "outfinal", 0 0, v0x28e15e0_0;
+S_0x28e0210 .scope generate, "andbits[1]" "andbits[1]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28e0308 .param/l "i" 3 231, +C4<01>;
+S_0x28e0380 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28e0210;
+ .timescale -9 -12;
+L_0x29d4db0/d .functor NAND 1, L_0x29d5700, L_0x29d57a0, C4<1>, C4<1>;
+L_0x29d4db0 .delay (10000,10000,10000) L_0x29d4db0/d;
+L_0x29d4ef0/d .functor NOT 1, L_0x29d4db0, C4<0>, C4<0>, C4<0>;
+L_0x29d4ef0 .delay (10000,10000,10000) L_0x29d4ef0/d;
+v0x28e09c0_0 .net "A", 0 0, L_0x29d5700; 1 drivers
+v0x28e0a80_0 .net "AandB", 0 0, L_0x29d4ef0; 1 drivers
+v0x28e0b00_0 .net "AnandB", 0 0, L_0x29d4db0; 1 drivers
+v0x28e0bb0_0 .net "AndNandOut", 0 0, L_0x29d5340; 1 drivers
+v0x28e0c90_0 .net "B", 0 0, L_0x29d57a0; 1 drivers
+v0x28e0d10_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d5510 .part v0x2960210_0, 0, 1;
+S_0x28e0470 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28e0380;
+ .timescale -9 -12;
+L_0x29d5020/d .functor NOT 1, L_0x29d5510, C4<0>, C4<0>, C4<0>;
+L_0x29d5020 .delay (10000,10000,10000) L_0x29d5020/d;
+L_0x29d50e0/d .functor AND 1, L_0x29d4ef0, L_0x29d5020, C4<1>, C4<1>;
+L_0x29d50e0 .delay (20000,20000,20000) L_0x29d50e0/d;
+L_0x29d51f0/d .functor AND 1, L_0x29d4db0, L_0x29d5510, C4<1>, C4<1>;
+L_0x29d51f0 .delay (20000,20000,20000) L_0x29d51f0/d;
+L_0x29d5340/d .functor OR 1, L_0x29d50e0, L_0x29d51f0, C4<0>, C4<0>;
+L_0x29d5340 .delay (20000,20000,20000) L_0x29d5340/d;
+v0x28e0560_0 .net "S", 0 0, L_0x29d5510; 1 drivers
+v0x28e05e0_0 .alias "in0", 0 0, v0x28e0a80_0;
+v0x28e0680_0 .alias "in1", 0 0, v0x28e0b00_0;
+v0x28e0720_0 .net "nS", 0 0, L_0x29d5020; 1 drivers
+v0x28e07a0_0 .net "out0", 0 0, L_0x29d50e0; 1 drivers
+v0x28e0840_0 .net "out1", 0 0, L_0x29d51f0; 1 drivers
+v0x28e0920_0 .alias "outfinal", 0 0, v0x28e0bb0_0;
+S_0x28df650 .scope generate, "andbits[2]" "andbits[2]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28df748 .param/l "i" 3 231, +C4<010>;
+S_0x28df7c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28df650;
+ .timescale -9 -12;
+L_0x29d5840/d .functor NAND 1, L_0x29d7380, L_0x29d7420, C4<1>, C4<1>;
+L_0x29d5840 .delay (10000,10000,10000) L_0x29d5840/d;
+L_0x29d6c40/d .functor NOT 1, L_0x29d5840, C4<0>, C4<0>, C4<0>;
+L_0x29d6c40 .delay (10000,10000,10000) L_0x29d6c40/d;
+v0x28dfe00_0 .net "A", 0 0, L_0x29d7380; 1 drivers
+v0x28dfec0_0 .net "AandB", 0 0, L_0x29d6c40; 1 drivers
+v0x28dff40_0 .net "AnandB", 0 0, L_0x29d5840; 1 drivers
+v0x28dfff0_0 .net "AndNandOut", 0 0, L_0x29d7070; 1 drivers
+v0x28e00d0_0 .net "B", 0 0, L_0x29d7420; 1 drivers
+v0x28e0150_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d7240 .part v0x2960210_0, 0, 1;
+S_0x28df8b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28df7c0;
+ .timescale -9 -12;
+L_0x29d6d50/d .functor NOT 1, L_0x29d7240, C4<0>, C4<0>, C4<0>;
+L_0x29d6d50 .delay (10000,10000,10000) L_0x29d6d50/d;
+L_0x29d6e10/d .functor AND 1, L_0x29d6c40, L_0x29d6d50, C4<1>, C4<1>;
+L_0x29d6e10 .delay (20000,20000,20000) L_0x29d6e10/d;
+L_0x29d6f20/d .functor AND 1, L_0x29d5840, L_0x29d7240, C4<1>, C4<1>;
+L_0x29d6f20 .delay (20000,20000,20000) L_0x29d6f20/d;
+L_0x29d7070/d .functor OR 1, L_0x29d6e10, L_0x29d6f20, C4<0>, C4<0>;
+L_0x29d7070 .delay (20000,20000,20000) L_0x29d7070/d;
+v0x28df9a0_0 .net "S", 0 0, L_0x29d7240; 1 drivers
+v0x28dfa20_0 .alias "in0", 0 0, v0x28dfec0_0;
+v0x28dfac0_0 .alias "in1", 0 0, v0x28dff40_0;
+v0x28dfb60_0 .net "nS", 0 0, L_0x29d6d50; 1 drivers
+v0x28dfbe0_0 .net "out0", 0 0, L_0x29d6e10; 1 drivers
+v0x28dfc80_0 .net "out1", 0 0, L_0x29d6f20; 1 drivers
+v0x28dfd60_0 .alias "outfinal", 0 0, v0x28dfff0_0;
+S_0x28dea90 .scope generate, "andbits[3]" "andbits[3]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28deb88 .param/l "i" 3 231, +C4<011>;
+S_0x28dec00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dea90;
+ .timescale -9 -12;
+L_0x29d7550/d .functor NAND 1, L_0x29d7df0, L_0x29d7ee0, C4<1>, C4<1>;
+L_0x29d7550 .delay (10000,10000,10000) L_0x29d7550/d;
+L_0x29d7690/d .functor NOT 1, L_0x29d7550, C4<0>, C4<0>, C4<0>;
+L_0x29d7690 .delay (10000,10000,10000) L_0x29d7690/d;
+v0x28df240_0 .net "A", 0 0, L_0x29d7df0; 1 drivers
+v0x28df300_0 .net "AandB", 0 0, L_0x29d7690; 1 drivers
+v0x28df380_0 .net "AnandB", 0 0, L_0x29d7550; 1 drivers
+v0x28df430_0 .net "AndNandOut", 0 0, L_0x29d7ae0; 1 drivers
+v0x28df510_0 .net "B", 0 0, L_0x29d7ee0; 1 drivers
+v0x28df590_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d7cb0 .part v0x2960210_0, 0, 1;
+S_0x28decf0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dec00;
+ .timescale -9 -12;
+L_0x29d77c0/d .functor NOT 1, L_0x29d7cb0, C4<0>, C4<0>, C4<0>;
+L_0x29d77c0 .delay (10000,10000,10000) L_0x29d77c0/d;
+L_0x29d7880/d .functor AND 1, L_0x29d7690, L_0x29d77c0, C4<1>, C4<1>;
+L_0x29d7880 .delay (20000,20000,20000) L_0x29d7880/d;
+L_0x29d7990/d .functor AND 1, L_0x29d7550, L_0x29d7cb0, C4<1>, C4<1>;
+L_0x29d7990 .delay (20000,20000,20000) L_0x29d7990/d;
+L_0x29d7ae0/d .functor OR 1, L_0x29d7880, L_0x29d7990, C4<0>, C4<0>;
+L_0x29d7ae0 .delay (20000,20000,20000) L_0x29d7ae0/d;
+v0x28dede0_0 .net "S", 0 0, L_0x29d7cb0; 1 drivers
+v0x28dee60_0 .alias "in0", 0 0, v0x28df300_0;
+v0x28def00_0 .alias "in1", 0 0, v0x28df380_0;
+v0x28defa0_0 .net "nS", 0 0, L_0x29d77c0; 1 drivers
+v0x28df020_0 .net "out0", 0 0, L_0x29d7880; 1 drivers
+v0x28df0c0_0 .net "out1", 0 0, L_0x29d7990; 1 drivers
+v0x28df1a0_0 .alias "outfinal", 0 0, v0x28df430_0;
+S_0x28dded0 .scope generate, "andbits[4]" "andbits[4]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28ddfc8 .param/l "i" 3 231, +C4<0100>;
+S_0x28de040 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dded0;
+ .timescale -9 -12;
+L_0x29d7fd0/d .functor NAND 1, L_0x29d88b0, L_0x29d8950, C4<1>, C4<1>;
+L_0x29d7fd0 .delay (10000,10000,10000) L_0x29d7fd0/d;
+L_0x29d80f0/d .functor NOT 1, L_0x29d7fd0, C4<0>, C4<0>, C4<0>;
+L_0x29d80f0 .delay (10000,10000,10000) L_0x29d80f0/d;
+v0x28de680_0 .net "A", 0 0, L_0x29d88b0; 1 drivers
+v0x28de740_0 .net "AandB", 0 0, L_0x29d80f0; 1 drivers
+v0x28de7c0_0 .net "AnandB", 0 0, L_0x29d7fd0; 1 drivers
+v0x28de870_0 .net "AndNandOut", 0 0, L_0x29d8540; 1 drivers
+v0x28de950_0 .net "B", 0 0, L_0x29d8950; 1 drivers
+v0x28de9d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d8710 .part v0x2960210_0, 0, 1;
+S_0x28de130 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28de040;
+ .timescale -9 -12;
+L_0x29d8220/d .functor NOT 1, L_0x29d8710, C4<0>, C4<0>, C4<0>;
+L_0x29d8220 .delay (10000,10000,10000) L_0x29d8220/d;
+L_0x29d82e0/d .functor AND 1, L_0x29d80f0, L_0x29d8220, C4<1>, C4<1>;
+L_0x29d82e0 .delay (20000,20000,20000) L_0x29d82e0/d;
+L_0x29d83f0/d .functor AND 1, L_0x29d7fd0, L_0x29d8710, C4<1>, C4<1>;
+L_0x29d83f0 .delay (20000,20000,20000) L_0x29d83f0/d;
+L_0x29d8540/d .functor OR 1, L_0x29d82e0, L_0x29d83f0, C4<0>, C4<0>;
+L_0x29d8540 .delay (20000,20000,20000) L_0x29d8540/d;
+v0x28de220_0 .net "S", 0 0, L_0x29d8710; 1 drivers
+v0x28de2a0_0 .alias "in0", 0 0, v0x28de740_0;
+v0x28de340_0 .alias "in1", 0 0, v0x28de7c0_0;
+v0x28de3e0_0 .net "nS", 0 0, L_0x29d8220; 1 drivers
+v0x28de460_0 .net "out0", 0 0, L_0x29d82e0; 1 drivers
+v0x28de500_0 .net "out1", 0 0, L_0x29d83f0; 1 drivers
+v0x28de5e0_0 .alias "outfinal", 0 0, v0x28de870_0;
+S_0x28dd310 .scope generate, "andbits[5]" "andbits[5]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28dd408 .param/l "i" 3 231, +C4<0101>;
+S_0x28dd480 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dd310;
+ .timescale -9 -12;
+L_0x29d8850/d .functor NAND 1, L_0x29d93d0, L_0x29d9470, C4<1>, C4<1>;
+L_0x29d8850 .delay (10000,10000,10000) L_0x29d8850/d;
+L_0x29d8b60/d .functor NOT 1, L_0x29d8850, C4<0>, C4<0>, C4<0>;
+L_0x29d8b60 .delay (10000,10000,10000) L_0x29d8b60/d;
+v0x28ddac0_0 .net "A", 0 0, L_0x29d93d0; 1 drivers
+v0x28ddb80_0 .net "AandB", 0 0, L_0x29d8b60; 1 drivers
+v0x28ddc00_0 .net "AnandB", 0 0, L_0x29d8850; 1 drivers
+v0x28ddcb0_0 .net "AndNandOut", 0 0, L_0x29d8fb0; 1 drivers
+v0x28ddd90_0 .net "B", 0 0, L_0x29d9470; 1 drivers
+v0x28dde10_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d9180 .part v0x2960210_0, 0, 1;
+S_0x28dd570 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dd480;
+ .timescale -9 -12;
+L_0x29d8c90/d .functor NOT 1, L_0x29d9180, C4<0>, C4<0>, C4<0>;
+L_0x29d8c90 .delay (10000,10000,10000) L_0x29d8c90/d;
+L_0x29d8d50/d .functor AND 1, L_0x29d8b60, L_0x29d8c90, C4<1>, C4<1>;
+L_0x29d8d50 .delay (20000,20000,20000) L_0x29d8d50/d;
+L_0x29d8e60/d .functor AND 1, L_0x29d8850, L_0x29d9180, C4<1>, C4<1>;
+L_0x29d8e60 .delay (20000,20000,20000) L_0x29d8e60/d;
+L_0x29d8fb0/d .functor OR 1, L_0x29d8d50, L_0x29d8e60, C4<0>, C4<0>;
+L_0x29d8fb0 .delay (20000,20000,20000) L_0x29d8fb0/d;
+v0x28dd660_0 .net "S", 0 0, L_0x29d9180; 1 drivers
+v0x28dd6e0_0 .alias "in0", 0 0, v0x28ddb80_0;
+v0x28dd780_0 .alias "in1", 0 0, v0x28ddc00_0;
+v0x28dd820_0 .net "nS", 0 0, L_0x29d8c90; 1 drivers
+v0x28dd8a0_0 .net "out0", 0 0, L_0x29d8d50; 1 drivers
+v0x28dd940_0 .net "out1", 0 0, L_0x29d8e60; 1 drivers
+v0x28dda20_0 .alias "outfinal", 0 0, v0x28ddcb0_0;
+S_0x28dc750 .scope generate, "andbits[6]" "andbits[6]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28dc848 .param/l "i" 3 231, +C4<0110>;
+S_0x28dc8c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dc750;
+ .timescale -9 -12;
+L_0x29d9560/d .functor NAND 1, L_0x29d9e20, L_0x29d9ec0, C4<1>, C4<1>;
+L_0x29d9560 .delay (10000,10000,10000) L_0x29d9560/d;
+L_0x29d96c0/d .functor NOT 1, L_0x29d9560, C4<0>, C4<0>, C4<0>;
+L_0x29d96c0 .delay (10000,10000,10000) L_0x29d96c0/d;
+v0x28dcf00_0 .net "A", 0 0, L_0x29d9e20; 1 drivers
+v0x28dcfc0_0 .net "AandB", 0 0, L_0x29d96c0; 1 drivers
+v0x28dd040_0 .net "AnandB", 0 0, L_0x29d9560; 1 drivers
+v0x28dd0f0_0 .net "AndNandOut", 0 0, L_0x29d9b10; 1 drivers
+v0x28dd1d0_0 .net "B", 0 0, L_0x29d9ec0; 1 drivers
+v0x28dd250_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29d9ce0 .part v0x2960210_0, 0, 1;
+S_0x28dc9b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dc8c0;
+ .timescale -9 -12;
+L_0x29d97f0/d .functor NOT 1, L_0x29d9ce0, C4<0>, C4<0>, C4<0>;
+L_0x29d97f0 .delay (10000,10000,10000) L_0x29d97f0/d;
+L_0x29d98b0/d .functor AND 1, L_0x29d96c0, L_0x29d97f0, C4<1>, C4<1>;
+L_0x29d98b0 .delay (20000,20000,20000) L_0x29d98b0/d;
+L_0x29d99c0/d .functor AND 1, L_0x29d9560, L_0x29d9ce0, C4<1>, C4<1>;
+L_0x29d99c0 .delay (20000,20000,20000) L_0x29d99c0/d;
+L_0x29d9b10/d .functor OR 1, L_0x29d98b0, L_0x29d99c0, C4<0>, C4<0>;
+L_0x29d9b10 .delay (20000,20000,20000) L_0x29d9b10/d;
+v0x28dcaa0_0 .net "S", 0 0, L_0x29d9ce0; 1 drivers
+v0x28dcb20_0 .alias "in0", 0 0, v0x28dcfc0_0;
+v0x28dcbc0_0 .alias "in1", 0 0, v0x28dd040_0;
+v0x28dcc60_0 .net "nS", 0 0, L_0x29d97f0; 1 drivers
+v0x28dcce0_0 .net "out0", 0 0, L_0x29d98b0; 1 drivers
+v0x28dcd80_0 .net "out1", 0 0, L_0x29d99c0; 1 drivers
+v0x28dce60_0 .alias "outfinal", 0 0, v0x28dd0f0_0;
+S_0x28dbb90 .scope generate, "andbits[7]" "andbits[7]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28dbc88 .param/l "i" 3 231, +C4<0111>;
+S_0x28dbd00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dbb90;
+ .timescale -9 -12;
+L_0x29d5650/d .functor NAND 1, L_0x29da890, L_0x29d9fb0, C4<1>, C4<1>;
+L_0x29d5650 .delay (10000,10000,10000) L_0x29d5650/d;
+L_0x29da130/d .functor NOT 1, L_0x29d5650, C4<0>, C4<0>, C4<0>;
+L_0x29da130 .delay (10000,10000,10000) L_0x29da130/d;
+v0x28dc340_0 .net "A", 0 0, L_0x29da890; 1 drivers
+v0x28dc400_0 .net "AandB", 0 0, L_0x29da130; 1 drivers
+v0x28dc480_0 .net "AnandB", 0 0, L_0x29d5650; 1 drivers
+v0x28dc530_0 .net "AndNandOut", 0 0, L_0x29da580; 1 drivers
+v0x28dc610_0 .net "B", 0 0, L_0x29d9fb0; 1 drivers
+v0x28dc690_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29da750 .part v0x2960210_0, 0, 1;
+S_0x28dbdf0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28dbd00;
+ .timescale -9 -12;
+L_0x29da260/d .functor NOT 1, L_0x29da750, C4<0>, C4<0>, C4<0>;
+L_0x29da260 .delay (10000,10000,10000) L_0x29da260/d;
+L_0x29da320/d .functor AND 1, L_0x29da130, L_0x29da260, C4<1>, C4<1>;
+L_0x29da320 .delay (20000,20000,20000) L_0x29da320/d;
+L_0x29da430/d .functor AND 1, L_0x29d5650, L_0x29da750, C4<1>, C4<1>;
+L_0x29da430 .delay (20000,20000,20000) L_0x29da430/d;
+L_0x29da580/d .functor OR 1, L_0x29da320, L_0x29da430, C4<0>, C4<0>;
+L_0x29da580 .delay (20000,20000,20000) L_0x29da580/d;
+v0x28dbee0_0 .net "S", 0 0, L_0x29da750; 1 drivers
+v0x28dbf60_0 .alias "in0", 0 0, v0x28dc400_0;
+v0x28dc000_0 .alias "in1", 0 0, v0x28dc480_0;
+v0x28dc0a0_0 .net "nS", 0 0, L_0x29da260; 1 drivers
+v0x28dc120_0 .net "out0", 0 0, L_0x29da320; 1 drivers
+v0x28dc1c0_0 .net "out1", 0 0, L_0x29da430; 1 drivers
+v0x28dc2a0_0 .alias "outfinal", 0 0, v0x28dc530_0;
+S_0x28dafd0 .scope generate, "andbits[8]" "andbits[8]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28db0c8 .param/l "i" 3 231, +C4<01000>;
+S_0x28db140 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28dafd0;
+ .timescale -9 -12;
+L_0x29daa30/d .functor NAND 1, L_0x29da930, L_0x29db3b0, C4<1>, C4<1>;
+L_0x29daa30 .delay (10000,10000,10000) L_0x29daa30/d;
+L_0x29dab90/d .functor NOT 1, L_0x29daa30, C4<0>, C4<0>, C4<0>;
+L_0x29dab90 .delay (10000,10000,10000) L_0x29dab90/d;
+v0x28db780_0 .net "A", 0 0, L_0x29da930; 1 drivers
+v0x28db840_0 .net "AandB", 0 0, L_0x29dab90; 1 drivers
+v0x28db8c0_0 .net "AnandB", 0 0, L_0x29daa30; 1 drivers
+v0x28db970_0 .net "AndNandOut", 0 0, L_0x29dafe0; 1 drivers
+v0x28dba50_0 .net "B", 0 0, L_0x29db3b0; 1 drivers
+v0x28dbad0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29db1b0 .part v0x2960210_0, 0, 1;
+S_0x28db230 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28db140;
+ .timescale -9 -12;
+L_0x29dacc0/d .functor NOT 1, L_0x29db1b0, C4<0>, C4<0>, C4<0>;
+L_0x29dacc0 .delay (10000,10000,10000) L_0x29dacc0/d;
+L_0x29dad80/d .functor AND 1, L_0x29dab90, L_0x29dacc0, C4<1>, C4<1>;
+L_0x29dad80 .delay (20000,20000,20000) L_0x29dad80/d;
+L_0x29dae90/d .functor AND 1, L_0x29daa30, L_0x29db1b0, C4<1>, C4<1>;
+L_0x29dae90 .delay (20000,20000,20000) L_0x29dae90/d;
+L_0x29dafe0/d .functor OR 1, L_0x29dad80, L_0x29dae90, C4<0>, C4<0>;
+L_0x29dafe0 .delay (20000,20000,20000) L_0x29dafe0/d;
+v0x28db320_0 .net "S", 0 0, L_0x29db1b0; 1 drivers
+v0x28db3a0_0 .alias "in0", 0 0, v0x28db840_0;
+v0x28db440_0 .alias "in1", 0 0, v0x28db8c0_0;
+v0x28db4e0_0 .net "nS", 0 0, L_0x29dacc0; 1 drivers
+v0x28db560_0 .net "out0", 0 0, L_0x29dad80; 1 drivers
+v0x28db600_0 .net "out1", 0 0, L_0x29dae90; 1 drivers
+v0x28db6e0_0 .alias "outfinal", 0 0, v0x28db970_0;
+S_0x28da410 .scope generate, "andbits[9]" "andbits[9]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28da508 .param/l "i" 3 231, +C4<01001>;
+S_0x28da580 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28da410;
+ .timescale -9 -12;
+L_0x29db2f0/d .functor NAND 1, L_0x29dbd70, L_0x29db4a0, C4<1>, C4<1>;
+L_0x29db2f0 .delay (10000,10000,10000) L_0x29db2f0/d;
+L_0x29db610/d .functor NOT 1, L_0x29db2f0, C4<0>, C4<0>, C4<0>;
+L_0x29db610 .delay (10000,10000,10000) L_0x29db610/d;
+v0x28dabc0_0 .net "A", 0 0, L_0x29dbd70; 1 drivers
+v0x28dac80_0 .net "AandB", 0 0, L_0x29db610; 1 drivers
+v0x28dad00_0 .net "AnandB", 0 0, L_0x29db2f0; 1 drivers
+v0x28dadb0_0 .net "AndNandOut", 0 0, L_0x29dba60; 1 drivers
+v0x28dae90_0 .net "B", 0 0, L_0x29db4a0; 1 drivers
+v0x28daf10_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29dbc30 .part v0x2960210_0, 0, 1;
+S_0x28da670 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28da580;
+ .timescale -9 -12;
+L_0x29db740/d .functor NOT 1, L_0x29dbc30, C4<0>, C4<0>, C4<0>;
+L_0x29db740 .delay (10000,10000,10000) L_0x29db740/d;
+L_0x29db800/d .functor AND 1, L_0x29db610, L_0x29db740, C4<1>, C4<1>;
+L_0x29db800 .delay (20000,20000,20000) L_0x29db800/d;
+L_0x29db910/d .functor AND 1, L_0x29db2f0, L_0x29dbc30, C4<1>, C4<1>;
+L_0x29db910 .delay (20000,20000,20000) L_0x29db910/d;
+L_0x29dba60/d .functor OR 1, L_0x29db800, L_0x29db910, C4<0>, C4<0>;
+L_0x29dba60 .delay (20000,20000,20000) L_0x29dba60/d;
+v0x28da760_0 .net "S", 0 0, L_0x29dbc30; 1 drivers
+v0x28da7e0_0 .alias "in0", 0 0, v0x28dac80_0;
+v0x28da880_0 .alias "in1", 0 0, v0x28dad00_0;
+v0x28da920_0 .net "nS", 0 0, L_0x29db740; 1 drivers
+v0x28da9a0_0 .net "out0", 0 0, L_0x29db800; 1 drivers
+v0x28daa40_0 .net "out1", 0 0, L_0x29db910; 1 drivers
+v0x28dab20_0 .alias "outfinal", 0 0, v0x28dadb0_0;
+S_0x28d9850 .scope generate, "andbits[10]" "andbits[10]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d9948 .param/l "i" 3 231, +C4<01010>;
+S_0x28d99c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d9850;
+ .timescale -9 -12;
+L_0x29dbf40/d .functor NAND 1, L_0x29dbe10, L_0x29dc8d0, C4<1>, C4<1>;
+L_0x29dbf40 .delay (10000,10000,10000) L_0x29dbf40/d;
+L_0x29dc080/d .functor NOT 1, L_0x29dbf40, C4<0>, C4<0>, C4<0>;
+L_0x29dc080 .delay (10000,10000,10000) L_0x29dc080/d;
+v0x28da000_0 .net "A", 0 0, L_0x29dbe10; 1 drivers
+v0x28da0c0_0 .net "AandB", 0 0, L_0x29dc080; 1 drivers
+v0x28da140_0 .net "AnandB", 0 0, L_0x29dbf40; 1 drivers
+v0x28da1f0_0 .net "AndNandOut", 0 0, L_0x29dc4d0; 1 drivers
+v0x28da2d0_0 .net "B", 0 0, L_0x29dc8d0; 1 drivers
+v0x28da350_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29dc6a0 .part v0x2960210_0, 0, 1;
+S_0x28d9ab0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d99c0;
+ .timescale -9 -12;
+L_0x29dc1b0/d .functor NOT 1, L_0x29dc6a0, C4<0>, C4<0>, C4<0>;
+L_0x29dc1b0 .delay (10000,10000,10000) L_0x29dc1b0/d;
+L_0x29dc270/d .functor AND 1, L_0x29dc080, L_0x29dc1b0, C4<1>, C4<1>;
+L_0x29dc270 .delay (20000,20000,20000) L_0x29dc270/d;
+L_0x29dc380/d .functor AND 1, L_0x29dbf40, L_0x29dc6a0, C4<1>, C4<1>;
+L_0x29dc380 .delay (20000,20000,20000) L_0x29dc380/d;
+L_0x29dc4d0/d .functor OR 1, L_0x29dc270, L_0x29dc380, C4<0>, C4<0>;
+L_0x29dc4d0 .delay (20000,20000,20000) L_0x29dc4d0/d;
+v0x28d9ba0_0 .net "S", 0 0, L_0x29dc6a0; 1 drivers
+v0x28d9c20_0 .alias "in0", 0 0, v0x28da0c0_0;
+v0x28d9cc0_0 .alias "in1", 0 0, v0x28da140_0;
+v0x28d9d60_0 .net "nS", 0 0, L_0x29dc1b0; 1 drivers
+v0x28d9de0_0 .net "out0", 0 0, L_0x29dc270; 1 drivers
+v0x28d9e80_0 .net "out1", 0 0, L_0x29dc380; 1 drivers
+v0x28d9f60_0 .alias "outfinal", 0 0, v0x28da1f0_0;
+S_0x28d8c90 .scope generate, "andbits[11]" "andbits[11]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d8d88 .param/l "i" 3 231, +C4<01011>;
+S_0x28d8e00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d8c90;
+ .timescale -9 -12;
+L_0x29dc7e0/d .functor NAND 1, L_0x29dd250, L_0x29dc9c0, C4<1>, C4<1>;
+L_0x29dc7e0 .delay (10000,10000,10000) L_0x29dc7e0/d;
+L_0x29dcb10/d .functor NOT 1, L_0x29dc7e0, C4<0>, C4<0>, C4<0>;
+L_0x29dcb10 .delay (10000,10000,10000) L_0x29dcb10/d;
+v0x28d9440_0 .net "A", 0 0, L_0x29dd250; 1 drivers
+v0x28d9500_0 .net "AandB", 0 0, L_0x29dcb10; 1 drivers
+v0x28d9580_0 .net "AnandB", 0 0, L_0x29dc7e0; 1 drivers
+v0x28d9630_0 .net "AndNandOut", 0 0, L_0x29dcf40; 1 drivers
+v0x28d9710_0 .net "B", 0 0, L_0x29dc9c0; 1 drivers
+v0x28d9790_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29dd110 .part v0x2960210_0, 0, 1;
+S_0x28d8ef0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d8e00;
+ .timescale -9 -12;
+L_0x29dcc20/d .functor NOT 1, L_0x29dd110, C4<0>, C4<0>, C4<0>;
+L_0x29dcc20 .delay (10000,10000,10000) L_0x29dcc20/d;
+L_0x29dcce0/d .functor AND 1, L_0x29dcb10, L_0x29dcc20, C4<1>, C4<1>;
+L_0x29dcce0 .delay (20000,20000,20000) L_0x29dcce0/d;
+L_0x29dcdf0/d .functor AND 1, L_0x29dc7e0, L_0x29dd110, C4<1>, C4<1>;
+L_0x29dcdf0 .delay (20000,20000,20000) L_0x29dcdf0/d;
+L_0x29dcf40/d .functor OR 1, L_0x29dcce0, L_0x29dcdf0, C4<0>, C4<0>;
+L_0x29dcf40 .delay (20000,20000,20000) L_0x29dcf40/d;
+v0x28d8fe0_0 .net "S", 0 0, L_0x29dd110; 1 drivers
+v0x28d9060_0 .alias "in0", 0 0, v0x28d9500_0;
+v0x28d9100_0 .alias "in1", 0 0, v0x28d9580_0;
+v0x28d91a0_0 .net "nS", 0 0, L_0x29dcc20; 1 drivers
+v0x28d9220_0 .net "out0", 0 0, L_0x29dcce0; 1 drivers
+v0x28d92c0_0 .net "out1", 0 0, L_0x29dcdf0; 1 drivers
+v0x28d93a0_0 .alias "outfinal", 0 0, v0x28d9630_0;
+S_0x28d80d0 .scope generate, "andbits[12]" "andbits[12]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d81c8 .param/l "i" 3 231, +C4<01100>;
+S_0x28d8240 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d80d0;
+ .timescale -9 -12;
+L_0x29dd400/d .functor NAND 1, L_0x29dd2f0, L_0x29ddde0, C4<1>, C4<1>;
+L_0x29dd400 .delay (10000,10000,10000) L_0x29dd400/d;
+L_0x29dd560/d .functor NOT 1, L_0x29dd400, C4<0>, C4<0>, C4<0>;
+L_0x29dd560 .delay (10000,10000,10000) L_0x29dd560/d;
+v0x28d8880_0 .net "A", 0 0, L_0x29dd2f0; 1 drivers
+v0x28d8940_0 .net "AandB", 0 0, L_0x29dd560; 1 drivers
+v0x28d89c0_0 .net "AnandB", 0 0, L_0x29dd400; 1 drivers
+v0x28d8a70_0 .net "AndNandOut", 0 0, L_0x29dd9b0; 1 drivers
+v0x28d8b50_0 .net "B", 0 0, L_0x29ddde0; 1 drivers
+v0x28d8bd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29ddb80 .part v0x2960210_0, 0, 1;
+S_0x28d8330 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d8240;
+ .timescale -9 -12;
+L_0x29dd690/d .functor NOT 1, L_0x29ddb80, C4<0>, C4<0>, C4<0>;
+L_0x29dd690 .delay (10000,10000,10000) L_0x29dd690/d;
+L_0x29dd750/d .functor AND 1, L_0x29dd560, L_0x29dd690, C4<1>, C4<1>;
+L_0x29dd750 .delay (20000,20000,20000) L_0x29dd750/d;
+L_0x29dd860/d .functor AND 1, L_0x29dd400, L_0x29ddb80, C4<1>, C4<1>;
+L_0x29dd860 .delay (20000,20000,20000) L_0x29dd860/d;
+L_0x29dd9b0/d .functor OR 1, L_0x29dd750, L_0x29dd860, C4<0>, C4<0>;
+L_0x29dd9b0 .delay (20000,20000,20000) L_0x29dd9b0/d;
+v0x28d8420_0 .net "S", 0 0, L_0x29ddb80; 1 drivers
+v0x28d84a0_0 .alias "in0", 0 0, v0x28d8940_0;
+v0x28d8540_0 .alias "in1", 0 0, v0x28d89c0_0;
+v0x28d85e0_0 .net "nS", 0 0, L_0x29dd690; 1 drivers
+v0x28d8660_0 .net "out0", 0 0, L_0x29dd750; 1 drivers
+v0x28d8700_0 .net "out1", 0 0, L_0x29dd860; 1 drivers
+v0x28d87e0_0 .alias "outfinal", 0 0, v0x28d8a70_0;
+S_0x28d7510 .scope generate, "andbits[13]" "andbits[13]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d7608 .param/l "i" 3 231, +C4<01101>;
+S_0x28d7680 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d7510;
+ .timescale -9 -12;
+L_0x29ddcc0/d .functor NAND 1, L_0x29d92c0, L_0x29dde80, C4<1>, C4<1>;
+L_0x29ddcc0 .delay (10000,10000,10000) L_0x29ddcc0/d;
+L_0x29de000/d .functor NOT 1, L_0x29ddcc0, C4<0>, C4<0>, C4<0>;
+L_0x29de000 .delay (10000,10000,10000) L_0x29de000/d;
+v0x28d7cc0_0 .net "A", 0 0, L_0x29d92c0; 1 drivers
+v0x28d7d80_0 .net "AandB", 0 0, L_0x29de000; 1 drivers
+v0x28d7e00_0 .net "AnandB", 0 0, L_0x29ddcc0; 1 drivers
+v0x28d7eb0_0 .net "AndNandOut", 0 0, L_0x29de430; 1 drivers
+v0x28d7f90_0 .net "B", 0 0, L_0x29dde80; 1 drivers
+v0x28d8010_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29de600 .part v0x2960210_0, 0, 1;
+S_0x28d7770 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d7680;
+ .timescale -9 -12;
+L_0x29de110/d .functor NOT 1, L_0x29de600, C4<0>, C4<0>, C4<0>;
+L_0x29de110 .delay (10000,10000,10000) L_0x29de110/d;
+L_0x29de1d0/d .functor AND 1, L_0x29de000, L_0x29de110, C4<1>, C4<1>;
+L_0x29de1d0 .delay (20000,20000,20000) L_0x29de1d0/d;
+L_0x29de2e0/d .functor AND 1, L_0x29ddcc0, L_0x29de600, C4<1>, C4<1>;
+L_0x29de2e0 .delay (20000,20000,20000) L_0x29de2e0/d;
+L_0x29de430/d .functor OR 1, L_0x29de1d0, L_0x29de2e0, C4<0>, C4<0>;
+L_0x29de430 .delay (20000,20000,20000) L_0x29de430/d;
+v0x28d7860_0 .net "S", 0 0, L_0x29de600; 1 drivers
+v0x28d78e0_0 .alias "in0", 0 0, v0x28d7d80_0;
+v0x28d7980_0 .alias "in1", 0 0, v0x28d7e00_0;
+v0x28d7a20_0 .net "nS", 0 0, L_0x29de110; 1 drivers
+v0x28d7aa0_0 .net "out0", 0 0, L_0x29de1d0; 1 drivers
+v0x28d7b40_0 .net "out1", 0 0, L_0x29de2e0; 1 drivers
+v0x28d7c20_0 .alias "outfinal", 0 0, v0x28d7eb0_0;
+S_0x28d6950 .scope generate, "andbits[14]" "andbits[14]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d6a48 .param/l "i" 3 231, +C4<01110>;
+S_0x28d6ac0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d6950;
+ .timescale -9 -12;
+L_0x29d9360/d .functor NAND 1, L_0x29de950, L_0x29de9f0, C4<1>, C4<1>;
+L_0x29d9360 .delay (10000,10000,10000) L_0x29d9360/d;
+L_0x29deb70/d .functor NOT 1, L_0x29d9360, C4<0>, C4<0>, C4<0>;
+L_0x29deb70 .delay (10000,10000,10000) L_0x29deb70/d;
+v0x28d7100_0 .net "A", 0 0, L_0x29de950; 1 drivers
+v0x28d71c0_0 .net "AandB", 0 0, L_0x29deb70; 1 drivers
+v0x28d7240_0 .net "AnandB", 0 0, L_0x29d9360; 1 drivers
+v0x28d72f0_0 .net "AndNandOut", 0 0, L_0x29defa0; 1 drivers
+v0x28d73d0_0 .net "B", 0 0, L_0x29de9f0; 1 drivers
+v0x28d7450_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29df170 .part v0x2960210_0, 0, 1;
+S_0x28d6bb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d6ac0;
+ .timescale -9 -12;
+L_0x29dec80/d .functor NOT 1, L_0x29df170, C4<0>, C4<0>, C4<0>;
+L_0x29dec80 .delay (10000,10000,10000) L_0x29dec80/d;
+L_0x29ded40/d .functor AND 1, L_0x29deb70, L_0x29dec80, C4<1>, C4<1>;
+L_0x29ded40 .delay (20000,20000,20000) L_0x29ded40/d;
+L_0x29dee50/d .functor AND 1, L_0x29d9360, L_0x29df170, C4<1>, C4<1>;
+L_0x29dee50 .delay (20000,20000,20000) L_0x29dee50/d;
+L_0x29defa0/d .functor OR 1, L_0x29ded40, L_0x29dee50, C4<0>, C4<0>;
+L_0x29defa0 .delay (20000,20000,20000) L_0x29defa0/d;
+v0x28d6ca0_0 .net "S", 0 0, L_0x29df170; 1 drivers
+v0x28d6d20_0 .alias "in0", 0 0, v0x28d71c0_0;
+v0x28d6dc0_0 .alias "in1", 0 0, v0x28d7240_0;
+v0x28d6e60_0 .net "nS", 0 0, L_0x29dec80; 1 drivers
+v0x28d6ee0_0 .net "out0", 0 0, L_0x29ded40; 1 drivers
+v0x28d6f80_0 .net "out1", 0 0, L_0x29dee50; 1 drivers
+v0x28d7060_0 .alias "outfinal", 0 0, v0x28d72f0_0;
+S_0x28d5d90 .scope generate, "andbits[15]" "andbits[15]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d5e88 .param/l "i" 3 231, +C4<01111>;
+S_0x28d5f00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d5d90;
+ .timescale -9 -12;
+L_0x29df2b0/d .functor NAND 1, L_0x29dfd20, L_0x29df450, C4<1>, C4<1>;
+L_0x29df2b0 .delay (10000,10000,10000) L_0x29df2b0/d;
+L_0x29df600/d .functor NOT 1, L_0x29df2b0, C4<0>, C4<0>, C4<0>;
+L_0x29df600 .delay (10000,10000,10000) L_0x29df600/d;
+v0x28d6540_0 .net "A", 0 0, L_0x29dfd20; 1 drivers
+v0x28d6600_0 .net "AandB", 0 0, L_0x29df600; 1 drivers
+v0x28d6680_0 .net "AnandB", 0 0, L_0x29df2b0; 1 drivers
+v0x28d6730_0 .net "AndNandOut", 0 0, L_0x29dfa10; 1 drivers
+v0x28d6810_0 .net "B", 0 0, L_0x29df450; 1 drivers
+v0x28d6890_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29dfbe0 .part v0x2960210_0, 0, 1;
+S_0x28d5ff0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d5f00;
+ .timescale -9 -12;
+L_0x29df6f0/d .functor NOT 1, L_0x29dfbe0, C4<0>, C4<0>, C4<0>;
+L_0x29df6f0 .delay (10000,10000,10000) L_0x29df6f0/d;
+L_0x29df7b0/d .functor AND 1, L_0x29df600, L_0x29df6f0, C4<1>, C4<1>;
+L_0x29df7b0 .delay (20000,20000,20000) L_0x29df7b0/d;
+L_0x29df8c0/d .functor AND 1, L_0x29df2b0, L_0x29dfbe0, C4<1>, C4<1>;
+L_0x29df8c0 .delay (20000,20000,20000) L_0x29df8c0/d;
+L_0x29dfa10/d .functor OR 1, L_0x29df7b0, L_0x29df8c0, C4<0>, C4<0>;
+L_0x29dfa10 .delay (20000,20000,20000) L_0x29dfa10/d;
+v0x28d60e0_0 .net "S", 0 0, L_0x29dfbe0; 1 drivers
+v0x28d6160_0 .alias "in0", 0 0, v0x28d6600_0;
+v0x28d6200_0 .alias "in1", 0 0, v0x28d6680_0;
+v0x28d62a0_0 .net "nS", 0 0, L_0x29df6f0; 1 drivers
+v0x28d6320_0 .net "out0", 0 0, L_0x29df7b0; 1 drivers
+v0x28d63c0_0 .net "out1", 0 0, L_0x29df8c0; 1 drivers
+v0x28d64a0_0 .alias "outfinal", 0 0, v0x28d6730_0;
+S_0x28d51d0 .scope generate, "andbits[16]" "andbits[16]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d52c8 .param/l "i" 3 231, +C4<010000>;
+S_0x28d5340 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d51d0;
+ .timescale -9 -12;
+L_0x29df540/d .functor NAND 1, L_0x29dfdc0, L_0x29dfe60, C4<1>, C4<1>;
+L_0x29df540 .delay (10000,10000,10000) L_0x29df540/d;
+L_0x29e0030/d .functor NOT 1, L_0x29df540, C4<0>, C4<0>, C4<0>;
+L_0x29e0030 .delay (10000,10000,10000) L_0x29e0030/d;
+v0x28d5980_0 .net "A", 0 0, L_0x29dfdc0; 1 drivers
+v0x28d5a40_0 .net "AandB", 0 0, L_0x29e0030; 1 drivers
+v0x28d5ac0_0 .net "AnandB", 0 0, L_0x29df540; 1 drivers
+v0x28d5b70_0 .net "AndNandOut", 0 0, L_0x29e0480; 1 drivers
+v0x28d5c50_0 .net "B", 0 0, L_0x29dfe60; 1 drivers
+v0x28d5cd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e0650 .part v0x2960210_0, 0, 1;
+S_0x28d5430 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d5340;
+ .timescale -9 -12;
+L_0x29e0160/d .functor NOT 1, L_0x29e0650, C4<0>, C4<0>, C4<0>;
+L_0x29e0160 .delay (10000,10000,10000) L_0x29e0160/d;
+L_0x29e0220/d .functor AND 1, L_0x29e0030, L_0x29e0160, C4<1>, C4<1>;
+L_0x29e0220 .delay (20000,20000,20000) L_0x29e0220/d;
+L_0x29e0330/d .functor AND 1, L_0x29df540, L_0x29e0650, C4<1>, C4<1>;
+L_0x29e0330 .delay (20000,20000,20000) L_0x29e0330/d;
+L_0x29e0480/d .functor OR 1, L_0x29e0220, L_0x29e0330, C4<0>, C4<0>;
+L_0x29e0480 .delay (20000,20000,20000) L_0x29e0480/d;
+v0x28d5520_0 .net "S", 0 0, L_0x29e0650; 1 drivers
+v0x28d55a0_0 .alias "in0", 0 0, v0x28d5a40_0;
+v0x28d5640_0 .alias "in1", 0 0, v0x28d5ac0_0;
+v0x28d56e0_0 .net "nS", 0 0, L_0x29e0160; 1 drivers
+v0x28d5760_0 .net "out0", 0 0, L_0x29e0220; 1 drivers
+v0x28d5800_0 .net "out1", 0 0, L_0x29e0330; 1 drivers
+v0x28d58e0_0 .alias "outfinal", 0 0, v0x28d5b70_0;
+S_0x28d4610 .scope generate, "andbits[17]" "andbits[17]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d4708 .param/l "i" 3 231, +C4<010001>;
+S_0x28d4780 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d4610;
+ .timescale -9 -12;
+L_0x29e0790/d .functor NAND 1, L_0x29e1210, L_0x29e0960, C4<1>, C4<1>;
+L_0x29e0790 .delay (10000,10000,10000) L_0x29e0790/d;
+L_0x29e0af0/d .functor NOT 1, L_0x29e0790, C4<0>, C4<0>, C4<0>;
+L_0x29e0af0 .delay (10000,10000,10000) L_0x29e0af0/d;
+v0x28d4dc0_0 .net "A", 0 0, L_0x29e1210; 1 drivers
+v0x28d4e80_0 .net "AandB", 0 0, L_0x29e0af0; 1 drivers
+v0x28d4f00_0 .net "AnandB", 0 0, L_0x29e0790; 1 drivers
+v0x28d4fb0_0 .net "AndNandOut", 0 0, L_0x29e0f00; 1 drivers
+v0x28d5090_0 .net "B", 0 0, L_0x29e0960; 1 drivers
+v0x28d5110_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e10d0 .part v0x2960210_0, 0, 1;
+S_0x28d4870 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d4780;
+ .timescale -9 -12;
+L_0x29e0be0/d .functor NOT 1, L_0x29e10d0, C4<0>, C4<0>, C4<0>;
+L_0x29e0be0 .delay (10000,10000,10000) L_0x29e0be0/d;
+L_0x29e0ca0/d .functor AND 1, L_0x29e0af0, L_0x29e0be0, C4<1>, C4<1>;
+L_0x29e0ca0 .delay (20000,20000,20000) L_0x29e0ca0/d;
+L_0x29e0db0/d .functor AND 1, L_0x29e0790, L_0x29e10d0, C4<1>, C4<1>;
+L_0x29e0db0 .delay (20000,20000,20000) L_0x29e0db0/d;
+L_0x29e0f00/d .functor OR 1, L_0x29e0ca0, L_0x29e0db0, C4<0>, C4<0>;
+L_0x29e0f00 .delay (20000,20000,20000) L_0x29e0f00/d;
+v0x28d4960_0 .net "S", 0 0, L_0x29e10d0; 1 drivers
+v0x28d49e0_0 .alias "in0", 0 0, v0x28d4e80_0;
+v0x28d4a80_0 .alias "in1", 0 0, v0x28d4f00_0;
+v0x28d4b20_0 .net "nS", 0 0, L_0x29e0be0; 1 drivers
+v0x28d4ba0_0 .net "out0", 0 0, L_0x29e0ca0; 1 drivers
+v0x28d4c40_0 .net "out1", 0 0, L_0x29e0db0; 1 drivers
+v0x28d4d20_0 .alias "outfinal", 0 0, v0x28d4fb0_0;
+S_0x28d3a50 .scope generate, "andbits[18]" "andbits[18]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d3b48 .param/l "i" 3 231, +C4<010010>;
+S_0x28d3bc0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d3a50;
+ .timescale -9 -12;
+L_0x29e0a50/d .functor NAND 1, L_0x29e12b0, L_0x29e1350, C4<1>, C4<1>;
+L_0x29e0a50 .delay (10000,10000,10000) L_0x29e0a50/d;
+L_0x29e1530/d .functor NOT 1, L_0x29e0a50, C4<0>, C4<0>, C4<0>;
+L_0x29e1530 .delay (10000,10000,10000) L_0x29e1530/d;
+v0x28d4200_0 .net "A", 0 0, L_0x29e12b0; 1 drivers
+v0x28d42c0_0 .net "AandB", 0 0, L_0x29e1530; 1 drivers
+v0x28d4340_0 .net "AnandB", 0 0, L_0x29e0a50; 1 drivers
+v0x28d43f0_0 .net "AndNandOut", 0 0, L_0x29e1960; 1 drivers
+v0x28d44d0_0 .net "B", 0 0, L_0x29e1350; 1 drivers
+v0x28d4550_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e1b30 .part v0x2960210_0, 0, 1;
+S_0x28d3cb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d3bc0;
+ .timescale -9 -12;
+L_0x29e1640/d .functor NOT 1, L_0x29e1b30, C4<0>, C4<0>, C4<0>;
+L_0x29e1640 .delay (10000,10000,10000) L_0x29e1640/d;
+L_0x29e1700/d .functor AND 1, L_0x29e1530, L_0x29e1640, C4<1>, C4<1>;
+L_0x29e1700 .delay (20000,20000,20000) L_0x29e1700/d;
+L_0x29e1810/d .functor AND 1, L_0x29e0a50, L_0x29e1b30, C4<1>, C4<1>;
+L_0x29e1810 .delay (20000,20000,20000) L_0x29e1810/d;
+L_0x29e1960/d .functor OR 1, L_0x29e1700, L_0x29e1810, C4<0>, C4<0>;
+L_0x29e1960 .delay (20000,20000,20000) L_0x29e1960/d;
+v0x28d3da0_0 .net "S", 0 0, L_0x29e1b30; 1 drivers
+v0x28d3e20_0 .alias "in0", 0 0, v0x28d42c0_0;
+v0x28d3ec0_0 .alias "in1", 0 0, v0x28d4340_0;
+v0x28d3f60_0 .net "nS", 0 0, L_0x29e1640; 1 drivers
+v0x28d3fe0_0 .net "out0", 0 0, L_0x29e1700; 1 drivers
+v0x28d4080_0 .net "out1", 0 0, L_0x29e1810; 1 drivers
+v0x28d4160_0 .alias "outfinal", 0 0, v0x28d43f0_0;
+S_0x28d2e90 .scope generate, "andbits[19]" "andbits[19]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d2f88 .param/l "i" 3 231, +C4<010011>;
+S_0x28d3000 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d2e90;
+ .timescale -9 -12;
+L_0x29e1e30/d .functor NAND 1, L_0x29e26f0, L_0x29e1c70, C4<1>, C4<1>;
+L_0x29e1e30 .delay (10000,10000,10000) L_0x29e1e30/d;
+L_0x29e1f90/d .functor NOT 1, L_0x29e1e30, C4<0>, C4<0>, C4<0>;
+L_0x29e1f90 .delay (10000,10000,10000) L_0x29e1f90/d;
+v0x28d3640_0 .net "A", 0 0, L_0x29e26f0; 1 drivers
+v0x28d3700_0 .net "AandB", 0 0, L_0x29e1f90; 1 drivers
+v0x28d3780_0 .net "AnandB", 0 0, L_0x29e1e30; 1 drivers
+v0x28d3830_0 .net "AndNandOut", 0 0, L_0x29e23e0; 1 drivers
+v0x28d3910_0 .net "B", 0 0, L_0x29e1c70; 1 drivers
+v0x28d3990_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e25b0 .part v0x2960210_0, 0, 1;
+S_0x28d30f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d3000;
+ .timescale -9 -12;
+L_0x29e20c0/d .functor NOT 1, L_0x29e25b0, C4<0>, C4<0>, C4<0>;
+L_0x29e20c0 .delay (10000,10000,10000) L_0x29e20c0/d;
+L_0x29e2180/d .functor AND 1, L_0x29e1f90, L_0x29e20c0, C4<1>, C4<1>;
+L_0x29e2180 .delay (20000,20000,20000) L_0x29e2180/d;
+L_0x29e2290/d .functor AND 1, L_0x29e1e30, L_0x29e25b0, C4<1>, C4<1>;
+L_0x29e2290 .delay (20000,20000,20000) L_0x29e2290/d;
+L_0x29e23e0/d .functor OR 1, L_0x29e2180, L_0x29e2290, C4<0>, C4<0>;
+L_0x29e23e0 .delay (20000,20000,20000) L_0x29e23e0/d;
+v0x28d31e0_0 .net "S", 0 0, L_0x29e25b0; 1 drivers
+v0x28d3260_0 .alias "in0", 0 0, v0x28d3700_0;
+v0x28d3300_0 .alias "in1", 0 0, v0x28d3780_0;
+v0x28d33a0_0 .net "nS", 0 0, L_0x29e20c0; 1 drivers
+v0x28d3420_0 .net "out0", 0 0, L_0x29e2180; 1 drivers
+v0x28d34c0_0 .net "out1", 0 0, L_0x29e2290; 1 drivers
+v0x28d35a0_0 .alias "outfinal", 0 0, v0x28d3830_0;
+S_0x28d22d0 .scope generate, "andbits[20]" "andbits[20]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d23c8 .param/l "i" 3 231, +C4<010100>;
+S_0x28d2440 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d22d0;
+ .timescale -9 -12;
+L_0x29e1d60/d .functor NAND 1, L_0x29e2790, L_0x29e2830, C4<1>, C4<1>;
+L_0x29e1d60 .delay (10000,10000,10000) L_0x29e1d60/d;
+L_0x29e29f0/d .functor NOT 1, L_0x29e1d60, C4<0>, C4<0>, C4<0>;
+L_0x29e29f0 .delay (10000,10000,10000) L_0x29e29f0/d;
+v0x28d2a80_0 .net "A", 0 0, L_0x29e2790; 1 drivers
+v0x28d2b40_0 .net "AandB", 0 0, L_0x29e29f0; 1 drivers
+v0x28d2bc0_0 .net "AnandB", 0 0, L_0x29e1d60; 1 drivers
+v0x28d2c70_0 .net "AndNandOut", 0 0, L_0x29e2e40; 1 drivers
+v0x28d2d50_0 .net "B", 0 0, L_0x29e2830; 1 drivers
+v0x28d2dd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e3010 .part v0x2960210_0, 0, 1;
+S_0x28d2530 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d2440;
+ .timescale -9 -12;
+L_0x29e2b20/d .functor NOT 1, L_0x29e3010, C4<0>, C4<0>, C4<0>;
+L_0x29e2b20 .delay (10000,10000,10000) L_0x29e2b20/d;
+L_0x29e2be0/d .functor AND 1, L_0x29e29f0, L_0x29e2b20, C4<1>, C4<1>;
+L_0x29e2be0 .delay (20000,20000,20000) L_0x29e2be0/d;
+L_0x29e2cf0/d .functor AND 1, L_0x29e1d60, L_0x29e3010, C4<1>, C4<1>;
+L_0x29e2cf0 .delay (20000,20000,20000) L_0x29e2cf0/d;
+L_0x29e2e40/d .functor OR 1, L_0x29e2be0, L_0x29e2cf0, C4<0>, C4<0>;
+L_0x29e2e40 .delay (20000,20000,20000) L_0x29e2e40/d;
+v0x28d2620_0 .net "S", 0 0, L_0x29e3010; 1 drivers
+v0x28d26a0_0 .alias "in0", 0 0, v0x28d2b40_0;
+v0x28d2740_0 .alias "in1", 0 0, v0x28d2bc0_0;
+v0x28d27e0_0 .net "nS", 0 0, L_0x29e2b20; 1 drivers
+v0x28d2860_0 .net "out0", 0 0, L_0x29e2be0; 1 drivers
+v0x28d2900_0 .net "out1", 0 0, L_0x29e2cf0; 1 drivers
+v0x28d29e0_0 .alias "outfinal", 0 0, v0x28d2c70_0;
+S_0x28d1710 .scope generate, "andbits[21]" "andbits[21]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d1808 .param/l "i" 3 231, +C4<010101>;
+S_0x28d1880 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d1710;
+ .timescale -9 -12;
+L_0x29e3340/d .functor NAND 1, L_0x29e3bc0, L_0x29e3150, C4<1>, C4<1>;
+L_0x29e3340 .delay (10000,10000,10000) L_0x29e3340/d;
+L_0x29e3480/d .functor NOT 1, L_0x29e3340, C4<0>, C4<0>, C4<0>;
+L_0x29e3480 .delay (10000,10000,10000) L_0x29e3480/d;
+v0x28d1ec0_0 .net "A", 0 0, L_0x29e3bc0; 1 drivers
+v0x28d1f80_0 .net "AandB", 0 0, L_0x29e3480; 1 drivers
+v0x28d2000_0 .net "AnandB", 0 0, L_0x29e3340; 1 drivers
+v0x28d20b0_0 .net "AndNandOut", 0 0, L_0x29e38b0; 1 drivers
+v0x28d2190_0 .net "B", 0 0, L_0x29e3150; 1 drivers
+v0x28d2210_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e3a80 .part v0x2960210_0, 0, 1;
+S_0x28d1970 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d1880;
+ .timescale -9 -12;
+L_0x29e3590/d .functor NOT 1, L_0x29e3a80, C4<0>, C4<0>, C4<0>;
+L_0x29e3590 .delay (10000,10000,10000) L_0x29e3590/d;
+L_0x29e3650/d .functor AND 1, L_0x29e3480, L_0x29e3590, C4<1>, C4<1>;
+L_0x29e3650 .delay (20000,20000,20000) L_0x29e3650/d;
+L_0x29e3760/d .functor AND 1, L_0x29e3340, L_0x29e3a80, C4<1>, C4<1>;
+L_0x29e3760 .delay (20000,20000,20000) L_0x29e3760/d;
+L_0x29e38b0/d .functor OR 1, L_0x29e3650, L_0x29e3760, C4<0>, C4<0>;
+L_0x29e38b0 .delay (20000,20000,20000) L_0x29e38b0/d;
+v0x28d1a60_0 .net "S", 0 0, L_0x29e3a80; 1 drivers
+v0x28d1ae0_0 .alias "in0", 0 0, v0x28d1f80_0;
+v0x28d1b80_0 .alias "in1", 0 0, v0x28d2000_0;
+v0x28d1c20_0 .net "nS", 0 0, L_0x29e3590; 1 drivers
+v0x28d1ca0_0 .net "out0", 0 0, L_0x29e3650; 1 drivers
+v0x28d1d40_0 .net "out1", 0 0, L_0x29e3760; 1 drivers
+v0x28d1e20_0 .alias "outfinal", 0 0, v0x28d20b0_0;
+S_0x28d0b50 .scope generate, "andbits[22]" "andbits[22]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d0c48 .param/l "i" 3 231, +C4<010110>;
+S_0x28d0cc0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28d0b50;
+ .timescale -9 -12;
+L_0x29e3240/d .functor NAND 1, L_0x29e3c60, L_0x29e3d00, C4<1>, C4<1>;
+L_0x29e3240 .delay (10000,10000,10000) L_0x29e3240/d;
+L_0x29e3ef0/d .functor NOT 1, L_0x29e3240, C4<0>, C4<0>, C4<0>;
+L_0x29e3ef0 .delay (10000,10000,10000) L_0x29e3ef0/d;
+v0x28d1300_0 .net "A", 0 0, L_0x29e3c60; 1 drivers
+v0x28d13c0_0 .net "AandB", 0 0, L_0x29e3ef0; 1 drivers
+v0x28d1440_0 .net "AnandB", 0 0, L_0x29e3240; 1 drivers
+v0x28d14f0_0 .net "AndNandOut", 0 0, L_0x29e4320; 1 drivers
+v0x28d15d0_0 .net "B", 0 0, L_0x29e3d00; 1 drivers
+v0x28d1650_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e44f0 .part v0x2960210_0, 0, 1;
+S_0x28d0db0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d0cc0;
+ .timescale -9 -12;
+L_0x29e4000/d .functor NOT 1, L_0x29e44f0, C4<0>, C4<0>, C4<0>;
+L_0x29e4000 .delay (10000,10000,10000) L_0x29e4000/d;
+L_0x29e40c0/d .functor AND 1, L_0x29e3ef0, L_0x29e4000, C4<1>, C4<1>;
+L_0x29e40c0 .delay (20000,20000,20000) L_0x29e40c0/d;
+L_0x29e41d0/d .functor AND 1, L_0x29e3240, L_0x29e44f0, C4<1>, C4<1>;
+L_0x29e41d0 .delay (20000,20000,20000) L_0x29e41d0/d;
+L_0x29e4320/d .functor OR 1, L_0x29e40c0, L_0x29e41d0, C4<0>, C4<0>;
+L_0x29e4320 .delay (20000,20000,20000) L_0x29e4320/d;
+v0x28d0ea0_0 .net "S", 0 0, L_0x29e44f0; 1 drivers
+v0x28d0f20_0 .alias "in0", 0 0, v0x28d13c0_0;
+v0x28d0fc0_0 .alias "in1", 0 0, v0x28d1440_0;
+v0x28d1060_0 .net "nS", 0 0, L_0x29e4000; 1 drivers
+v0x28d10e0_0 .net "out0", 0 0, L_0x29e40c0; 1 drivers
+v0x28d1180_0 .net "out1", 0 0, L_0x29e41d0; 1 drivers
+v0x28d1260_0 .alias "outfinal", 0 0, v0x28d14f0_0;
+S_0x28cff90 .scope generate, "andbits[23]" "andbits[23]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28d0088 .param/l "i" 3 231, +C4<010111>;
+S_0x28d0100 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cff90;
+ .timescale -9 -12;
+L_0x29e3df0/d .functor NAND 1, L_0x29e50b0, L_0x29e4630, C4<1>, C4<1>;
+L_0x29e3df0 .delay (10000,10000,10000) L_0x29e3df0/d;
+L_0x29e4950/d .functor NOT 1, L_0x29e3df0, C4<0>, C4<0>, C4<0>;
+L_0x29e4950 .delay (10000,10000,10000) L_0x29e4950/d;
+v0x28d0740_0 .net "A", 0 0, L_0x29e50b0; 1 drivers
+v0x28d0800_0 .net "AandB", 0 0, L_0x29e4950; 1 drivers
+v0x28d0880_0 .net "AnandB", 0 0, L_0x29e3df0; 1 drivers
+v0x28d0930_0 .net "AndNandOut", 0 0, L_0x29e4da0; 1 drivers
+v0x28d0a10_0 .net "B", 0 0, L_0x29e4630; 1 drivers
+v0x28d0a90_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e4f70 .part v0x2960210_0, 0, 1;
+S_0x28d01f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28d0100;
+ .timescale -9 -12;
+L_0x29e4a80/d .functor NOT 1, L_0x29e4f70, C4<0>, C4<0>, C4<0>;
+L_0x29e4a80 .delay (10000,10000,10000) L_0x29e4a80/d;
+L_0x29e4b40/d .functor AND 1, L_0x29e4950, L_0x29e4a80, C4<1>, C4<1>;
+L_0x29e4b40 .delay (20000,20000,20000) L_0x29e4b40/d;
+L_0x29e4c50/d .functor AND 1, L_0x29e3df0, L_0x29e4f70, C4<1>, C4<1>;
+L_0x29e4c50 .delay (20000,20000,20000) L_0x29e4c50/d;
+L_0x29e4da0/d .functor OR 1, L_0x29e4b40, L_0x29e4c50, C4<0>, C4<0>;
+L_0x29e4da0 .delay (20000,20000,20000) L_0x29e4da0/d;
+v0x28d02e0_0 .net "S", 0 0, L_0x29e4f70; 1 drivers
+v0x28d0360_0 .alias "in0", 0 0, v0x28d0800_0;
+v0x28d0400_0 .alias "in1", 0 0, v0x28d0880_0;
+v0x28d04a0_0 .net "nS", 0 0, L_0x29e4a80; 1 drivers
+v0x28d0520_0 .net "out0", 0 0, L_0x29e4b40; 1 drivers
+v0x28d05c0_0 .net "out1", 0 0, L_0x29e4c50; 1 drivers
+v0x28d06a0_0 .alias "outfinal", 0 0, v0x28d0930_0;
+S_0x28cf3d0 .scope generate, "andbits[24]" "andbits[24]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28cf4c8 .param/l "i" 3 231, +C4<011000>;
+S_0x28cf540 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cf3d0;
+ .timescale -9 -12;
+L_0x29e4720/d .functor NAND 1, L_0x29e5150, L_0x29e51f0, C4<1>, C4<1>;
+L_0x29e4720 .delay (10000,10000,10000) L_0x29e4720/d;
+L_0x29e53d0/d .functor NOT 1, L_0x29e4720, C4<0>, C4<0>, C4<0>;
+L_0x29e53d0 .delay (10000,10000,10000) L_0x29e53d0/d;
+v0x28cfb80_0 .net "A", 0 0, L_0x29e5150; 1 drivers
+v0x28cfc40_0 .net "AandB", 0 0, L_0x29e53d0; 1 drivers
+v0x28cfcc0_0 .net "AnandB", 0 0, L_0x29e4720; 1 drivers
+v0x28cfd70_0 .net "AndNandOut", 0 0, L_0x29e5800; 1 drivers
+v0x28cfe50_0 .net "B", 0 0, L_0x29e51f0; 1 drivers
+v0x28cfed0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e59d0 .part v0x2960210_0, 0, 1;
+S_0x28cf630 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cf540;
+ .timescale -9 -12;
+L_0x29e54e0/d .functor NOT 1, L_0x29e59d0, C4<0>, C4<0>, C4<0>;
+L_0x29e54e0 .delay (10000,10000,10000) L_0x29e54e0/d;
+L_0x29e55a0/d .functor AND 1, L_0x29e53d0, L_0x29e54e0, C4<1>, C4<1>;
+L_0x29e55a0 .delay (20000,20000,20000) L_0x29e55a0/d;
+L_0x29e56b0/d .functor AND 1, L_0x29e4720, L_0x29e59d0, C4<1>, C4<1>;
+L_0x29e56b0 .delay (20000,20000,20000) L_0x29e56b0/d;
+L_0x29e5800/d .functor OR 1, L_0x29e55a0, L_0x29e56b0, C4<0>, C4<0>;
+L_0x29e5800 .delay (20000,20000,20000) L_0x29e5800/d;
+v0x28cf720_0 .net "S", 0 0, L_0x29e59d0; 1 drivers
+v0x28cf7a0_0 .alias "in0", 0 0, v0x28cfc40_0;
+v0x28cf840_0 .alias "in1", 0 0, v0x28cfcc0_0;
+v0x28cf8e0_0 .net "nS", 0 0, L_0x29e54e0; 1 drivers
+v0x28cf960_0 .net "out0", 0 0, L_0x29e55a0; 1 drivers
+v0x28cfa00_0 .net "out1", 0 0, L_0x29e56b0; 1 drivers
+v0x28cfae0_0 .alias "outfinal", 0 0, v0x28cfd70_0;
+S_0x28ce810 .scope generate, "andbits[25]" "andbits[25]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28ce908 .param/l "i" 3 231, +C4<011001>;
+S_0x28ce980 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28ce810;
+ .timescale -9 -12;
+L_0x29e52e0/d .functor NAND 1, L_0x29e6580, L_0x29e5b10, C4<1>, C4<1>;
+L_0x29e52e0 .delay (10000,10000,10000) L_0x29e52e0/d;
+L_0x29e5e40/d .functor NOT 1, L_0x29e52e0, C4<0>, C4<0>, C4<0>;
+L_0x29e5e40 .delay (10000,10000,10000) L_0x29e5e40/d;
+v0x28cefc0_0 .net "A", 0 0, L_0x29e6580; 1 drivers
+v0x28cf080_0 .net "AandB", 0 0, L_0x29e5e40; 1 drivers
+v0x28cf100_0 .net "AnandB", 0 0, L_0x29e52e0; 1 drivers
+v0x28cf1b0_0 .net "AndNandOut", 0 0, L_0x29e6270; 1 drivers
+v0x28cf290_0 .net "B", 0 0, L_0x29e5b10; 1 drivers
+v0x28cf310_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e6440 .part v0x2960210_0, 0, 1;
+S_0x28cea70 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28ce980;
+ .timescale -9 -12;
+L_0x29e5f50/d .functor NOT 1, L_0x29e6440, C4<0>, C4<0>, C4<0>;
+L_0x29e5f50 .delay (10000,10000,10000) L_0x29e5f50/d;
+L_0x29e6010/d .functor AND 1, L_0x29e5e40, L_0x29e5f50, C4<1>, C4<1>;
+L_0x29e6010 .delay (20000,20000,20000) L_0x29e6010/d;
+L_0x29e6120/d .functor AND 1, L_0x29e52e0, L_0x29e6440, C4<1>, C4<1>;
+L_0x29e6120 .delay (20000,20000,20000) L_0x29e6120/d;
+L_0x29e6270/d .functor OR 1, L_0x29e6010, L_0x29e6120, C4<0>, C4<0>;
+L_0x29e6270 .delay (20000,20000,20000) L_0x29e6270/d;
+v0x28ceb60_0 .net "S", 0 0, L_0x29e6440; 1 drivers
+v0x28cebe0_0 .alias "in0", 0 0, v0x28cf080_0;
+v0x28cec80_0 .alias "in1", 0 0, v0x28cf100_0;
+v0x28ced20_0 .net "nS", 0 0, L_0x29e5f50; 1 drivers
+v0x28ceda0_0 .net "out0", 0 0, L_0x29e6010; 1 drivers
+v0x28cee40_0 .net "out1", 0 0, L_0x29e6120; 1 drivers
+v0x28cef20_0 .alias "outfinal", 0 0, v0x28cf1b0_0;
+S_0x28cdc50 .scope generate, "andbits[26]" "andbits[26]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28cdd48 .param/l "i" 3 231, +C4<011010>;
+S_0x28cddc0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cdc50;
+ .timescale -9 -12;
+L_0x29e5c00/d .functor NAND 1, L_0x29e6620, L_0x29e66c0, C4<1>, C4<1>;
+L_0x29e5c00 .delay (10000,10000,10000) L_0x29e5c00/d;
+L_0x29e6880/d .functor NOT 1, L_0x29e5c00, C4<0>, C4<0>, C4<0>;
+L_0x29e6880 .delay (10000,10000,10000) L_0x29e6880/d;
+v0x28ce400_0 .net "A", 0 0, L_0x29e6620; 1 drivers
+v0x28ce4c0_0 .net "AandB", 0 0, L_0x29e6880; 1 drivers
+v0x28ce540_0 .net "AnandB", 0 0, L_0x29e5c00; 1 drivers
+v0x28ce5f0_0 .net "AndNandOut", 0 0, L_0x29e6cd0; 1 drivers
+v0x28ce6d0_0 .net "B", 0 0, L_0x29e66c0; 1 drivers
+v0x28ce750_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e6ea0 .part v0x2960210_0, 0, 1;
+S_0x28cdeb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cddc0;
+ .timescale -9 -12;
+L_0x29e69b0/d .functor NOT 1, L_0x29e6ea0, C4<0>, C4<0>, C4<0>;
+L_0x29e69b0 .delay (10000,10000,10000) L_0x29e69b0/d;
+L_0x29e6a70/d .functor AND 1, L_0x29e6880, L_0x29e69b0, C4<1>, C4<1>;
+L_0x29e6a70 .delay (20000,20000,20000) L_0x29e6a70/d;
+L_0x29e6b80/d .functor AND 1, L_0x29e5c00, L_0x29e6ea0, C4<1>, C4<1>;
+L_0x29e6b80 .delay (20000,20000,20000) L_0x29e6b80/d;
+L_0x29e6cd0/d .functor OR 1, L_0x29e6a70, L_0x29e6b80, C4<0>, C4<0>;
+L_0x29e6cd0 .delay (20000,20000,20000) L_0x29e6cd0/d;
+v0x28cdfa0_0 .net "S", 0 0, L_0x29e6ea0; 1 drivers
+v0x28ce020_0 .alias "in0", 0 0, v0x28ce4c0_0;
+v0x28ce0c0_0 .alias "in1", 0 0, v0x28ce540_0;
+v0x28ce160_0 .net "nS", 0 0, L_0x29e69b0; 1 drivers
+v0x28ce1e0_0 .net "out0", 0 0, L_0x29e6a70; 1 drivers
+v0x28ce280_0 .net "out1", 0 0, L_0x29e6b80; 1 drivers
+v0x28ce360_0 .alias "outfinal", 0 0, v0x28ce5f0_0;
+S_0x28cd090 .scope generate, "andbits[27]" "andbits[27]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28cd188 .param/l "i" 3 231, +C4<011011>;
+S_0x28cd200 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cd090;
+ .timescale -9 -12;
+L_0x29e67b0/d .functor NAND 1, L_0x29e7a50, L_0x29e6fe0, C4<1>, C4<1>;
+L_0x29e67b0 .delay (10000,10000,10000) L_0x29e67b0/d;
+L_0x29e72f0/d .functor NOT 1, L_0x29e67b0, C4<0>, C4<0>, C4<0>;
+L_0x29e72f0 .delay (10000,10000,10000) L_0x29e72f0/d;
+v0x28cd840_0 .net "A", 0 0, L_0x29e7a50; 1 drivers
+v0x28cd900_0 .net "AandB", 0 0, L_0x29e72f0; 1 drivers
+v0x28cd980_0 .net "AnandB", 0 0, L_0x29e67b0; 1 drivers
+v0x28cda30_0 .net "AndNandOut", 0 0, L_0x29e7740; 1 drivers
+v0x28cdb10_0 .net "B", 0 0, L_0x29e6fe0; 1 drivers
+v0x28cdb90_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e7910 .part v0x2960210_0, 0, 1;
+S_0x28cd2f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cd200;
+ .timescale -9 -12;
+L_0x29e7420/d .functor NOT 1, L_0x29e7910, C4<0>, C4<0>, C4<0>;
+L_0x29e7420 .delay (10000,10000,10000) L_0x29e7420/d;
+L_0x29e74e0/d .functor AND 1, L_0x29e72f0, L_0x29e7420, C4<1>, C4<1>;
+L_0x29e74e0 .delay (20000,20000,20000) L_0x29e74e0/d;
+L_0x29e75f0/d .functor AND 1, L_0x29e67b0, L_0x29e7910, C4<1>, C4<1>;
+L_0x29e75f0 .delay (20000,20000,20000) L_0x29e75f0/d;
+L_0x29e7740/d .functor OR 1, L_0x29e74e0, L_0x29e75f0, C4<0>, C4<0>;
+L_0x29e7740 .delay (20000,20000,20000) L_0x29e7740/d;
+v0x28cd3e0_0 .net "S", 0 0, L_0x29e7910; 1 drivers
+v0x28cd460_0 .alias "in0", 0 0, v0x28cd900_0;
+v0x28cd500_0 .alias "in1", 0 0, v0x28cd980_0;
+v0x28cd5a0_0 .net "nS", 0 0, L_0x29e7420; 1 drivers
+v0x28cd620_0 .net "out0", 0 0, L_0x29e74e0; 1 drivers
+v0x28cd6c0_0 .net "out1", 0 0, L_0x29e75f0; 1 drivers
+v0x28cd7a0_0 .alias "outfinal", 0 0, v0x28cda30_0;
+S_0x28cc4d0 .scope generate, "andbits[28]" "andbits[28]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28cc5c8 .param/l "i" 3 231, +C4<011100>;
+S_0x28cc640 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cc4d0;
+ .timescale -9 -12;
+L_0x29e70d0/d .functor NAND 1, L_0x29e7af0, L_0x29e7b90, C4<1>, C4<1>;
+L_0x29e70d0 .delay (10000,10000,10000) L_0x29e70d0/d;
+L_0x29e7d80/d .functor NOT 1, L_0x29e70d0, C4<0>, C4<0>, C4<0>;
+L_0x29e7d80 .delay (10000,10000,10000) L_0x29e7d80/d;
+v0x28ccc80_0 .net "A", 0 0, L_0x29e7af0; 1 drivers
+v0x28ccd40_0 .net "AandB", 0 0, L_0x29e7d80; 1 drivers
+v0x28ccdc0_0 .net "AnandB", 0 0, L_0x29e70d0; 1 drivers
+v0x28cce70_0 .net "AndNandOut", 0 0, L_0x29e81b0; 1 drivers
+v0x28ccf50_0 .net "B", 0 0, L_0x29e7b90; 1 drivers
+v0x28ccfd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e8380 .part v0x2960210_0, 0, 1;
+S_0x28cc730 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cc640;
+ .timescale -9 -12;
+L_0x29e7e90/d .functor NOT 1, L_0x29e8380, C4<0>, C4<0>, C4<0>;
+L_0x29e7e90 .delay (10000,10000,10000) L_0x29e7e90/d;
+L_0x29e7f50/d .functor AND 1, L_0x29e7d80, L_0x29e7e90, C4<1>, C4<1>;
+L_0x29e7f50 .delay (20000,20000,20000) L_0x29e7f50/d;
+L_0x29e8060/d .functor AND 1, L_0x29e70d0, L_0x29e8380, C4<1>, C4<1>;
+L_0x29e8060 .delay (20000,20000,20000) L_0x29e8060/d;
+L_0x29e81b0/d .functor OR 1, L_0x29e7f50, L_0x29e8060, C4<0>, C4<0>;
+L_0x29e81b0 .delay (20000,20000,20000) L_0x29e81b0/d;
+v0x28cc820_0 .net "S", 0 0, L_0x29e8380; 1 drivers
+v0x28cc8a0_0 .alias "in0", 0 0, v0x28ccd40_0;
+v0x28cc940_0 .alias "in1", 0 0, v0x28ccdc0_0;
+v0x28cc9e0_0 .net "nS", 0 0, L_0x29e7e90; 1 drivers
+v0x28cca60_0 .net "out0", 0 0, L_0x29e7f50; 1 drivers
+v0x28ccb00_0 .net "out1", 0 0, L_0x29e8060; 1 drivers
+v0x28ccbe0_0 .alias "outfinal", 0 0, v0x28cce70_0;
+S_0x28cb910 .scope generate, "andbits[29]" "andbits[29]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28cba08 .param/l "i" 3 231, +C4<011101>;
+S_0x28cba80 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cb910;
+ .timescale -9 -12;
+L_0x29e7c80/d .functor NAND 1, L_0x29de740, L_0x29de7e0, C4<1>, C4<1>;
+L_0x29e7c80 .delay (10000,10000,10000) L_0x29e7c80/d;
+L_0x29e8800/d .functor NOT 1, L_0x29e7c80, C4<0>, C4<0>, C4<0>;
+L_0x29e8800 .delay (10000,10000,10000) L_0x29e8800/d;
+v0x28cc0c0_0 .net "A", 0 0, L_0x29de740; 1 drivers
+v0x28cc180_0 .net "AandB", 0 0, L_0x29e8800; 1 drivers
+v0x28cc200_0 .net "AnandB", 0 0, L_0x29e7c80; 1 drivers
+v0x28cc2b0_0 .net "AndNandOut", 0 0, L_0x29e8c30; 1 drivers
+v0x28cc390_0 .net "B", 0 0, L_0x29de7e0; 1 drivers
+v0x28cc410_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e8e00 .part v0x2960210_0, 0, 1;
+S_0x28cbb70 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28cba80;
+ .timescale -9 -12;
+L_0x29e8910/d .functor NOT 1, L_0x29e8e00, C4<0>, C4<0>, C4<0>;
+L_0x29e8910 .delay (10000,10000,10000) L_0x29e8910/d;
+L_0x29e89d0/d .functor AND 1, L_0x29e8800, L_0x29e8910, C4<1>, C4<1>;
+L_0x29e89d0 .delay (20000,20000,20000) L_0x29e89d0/d;
+L_0x29e8ae0/d .functor AND 1, L_0x29e7c80, L_0x29e8e00, C4<1>, C4<1>;
+L_0x29e8ae0 .delay (20000,20000,20000) L_0x29e8ae0/d;
+L_0x29e8c30/d .functor OR 1, L_0x29e89d0, L_0x29e8ae0, C4<0>, C4<0>;
+L_0x29e8c30 .delay (20000,20000,20000) L_0x29e8c30/d;
+v0x28cbc60_0 .net "S", 0 0, L_0x29e8e00; 1 drivers
+v0x28cbce0_0 .alias "in0", 0 0, v0x28cc180_0;
+v0x28cbd80_0 .alias "in1", 0 0, v0x28cc200_0;
+v0x28cbe20_0 .net "nS", 0 0, L_0x29e8910; 1 drivers
+v0x28cbea0_0 .net "out0", 0 0, L_0x29e89d0; 1 drivers
+v0x28cbf40_0 .net "out1", 0 0, L_0x29e8ae0; 1 drivers
+v0x28cc020_0 .alias "outfinal", 0 0, v0x28cc2b0_0;
+S_0x28cad50 .scope generate, "andbits[30]" "andbits[30]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28cae48 .param/l "i" 3 231, +C4<011110>;
+S_0x28caec0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28cad50;
+ .timescale -9 -12;
+L_0x29d89f0/d .functor NAND 1, L_0x29e9350, L_0x29e93f0, C4<1>, C4<1>;
+L_0x29d89f0 .delay (10000,10000,10000) L_0x29d89f0/d;
+L_0x29e8550/d .functor NOT 1, L_0x29d89f0, C4<0>, C4<0>, C4<0>;
+L_0x29e8550 .delay (10000,10000,10000) L_0x29e8550/d;
+v0x28cb500_0 .net "A", 0 0, L_0x29e9350; 1 drivers
+v0x28cb5c0_0 .net "AandB", 0 0, L_0x29e8550; 1 drivers
+v0x28cb640_0 .net "AnandB", 0 0, L_0x29d89f0; 1 drivers
+v0x28cb6f0_0 .net "AndNandOut", 0 0, L_0x29e9830; 1 drivers
+v0x28cb7d0_0 .net "B", 0 0, L_0x29e93f0; 1 drivers
+v0x28cb850_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29e99c0 .part v0x2960210_0, 0, 1;
+S_0x28cafb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28caec0;
+ .timescale -9 -12;
+L_0x29e8680/d .functor NOT 1, L_0x29e99c0, C4<0>, C4<0>, C4<0>;
+L_0x29e8680 .delay (10000,10000,10000) L_0x29e8680/d;
+L_0x29e9610/d .functor AND 1, L_0x29e8550, L_0x29e8680, C4<1>, C4<1>;
+L_0x29e9610 .delay (20000,20000,20000) L_0x29e9610/d;
+L_0x29e9700/d .functor AND 1, L_0x29d89f0, L_0x29e99c0, C4<1>, C4<1>;
+L_0x29e9700 .delay (20000,20000,20000) L_0x29e9700/d;
+L_0x29e9830/d .functor OR 1, L_0x29e9610, L_0x29e9700, C4<0>, C4<0>;
+L_0x29e9830 .delay (20000,20000,20000) L_0x29e9830/d;
+v0x28cb0a0_0 .net "S", 0 0, L_0x29e99c0; 1 drivers
+v0x28cb120_0 .alias "in0", 0 0, v0x28cb5c0_0;
+v0x28cb1c0_0 .alias "in1", 0 0, v0x28cb640_0;
+v0x28cb260_0 .net "nS", 0 0, L_0x29e8680; 1 drivers
+v0x28cb2e0_0 .net "out0", 0 0, L_0x29e9610; 1 drivers
+v0x28cb380_0 .net "out1", 0 0, L_0x29e9700; 1 drivers
+v0x28cb460_0 .alias "outfinal", 0 0, v0x28cb6f0_0;
+S_0x28ca170 .scope generate, "andbits[31]" "andbits[31]" 3 231, 3 231, S_0x28ca040;
+ .timescale -9 -12;
+P_0x28ca268 .param/l "i" 3 231, +C4<011111>;
+S_0x28ca2e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28ca170;
+ .timescale -9 -12;
+L_0x29e94e0/d .functor NAND 1, L_0x29ea4b0, L_0x29e9b00, C4<1>, C4<1>;
+L_0x29e94e0 .delay (10000,10000,10000) L_0x29e94e0/d;
+L_0x29e9e30/d .functor NOT 1, L_0x29e94e0, C4<0>, C4<0>, C4<0>;
+L_0x29e9e30 .delay (10000,10000,10000) L_0x29e9e30/d;
+v0x28ca940_0 .net "A", 0 0, L_0x29ea4b0; 1 drivers
+v0x28caa00_0 .net "AandB", 0 0, L_0x29e9e30; 1 drivers
+v0x28caa80_0 .net "AnandB", 0 0, L_0x29e94e0; 1 drivers
+v0x28cab30_0 .net "AndNandOut", 0 0, L_0x29ea1e0; 1 drivers
+v0x28cac10_0 .net "B", 0 0, L_0x29e9b00; 1 drivers
+v0x28cac90_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x29ea370 .part v0x2960210_0, 0, 1;
+S_0x28ca3d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28ca2e0;
+ .timescale -9 -12;
+L_0x29e9f20/d .functor NOT 1, L_0x29ea370, C4<0>, C4<0>, C4<0>;
+L_0x29e9f20 .delay (10000,10000,10000) L_0x29e9f20/d;
+L_0x29e9fc0/d .functor AND 1, L_0x29e9e30, L_0x29e9f20, C4<1>, C4<1>;
+L_0x29e9fc0 .delay (20000,20000,20000) L_0x29e9fc0/d;
+L_0x29ea0b0/d .functor AND 1, L_0x29e94e0, L_0x29ea370, C4<1>, C4<1>;
+L_0x29ea0b0 .delay (20000,20000,20000) L_0x29ea0b0/d;
+L_0x29ea1e0/d .functor OR 1, L_0x29e9fc0, L_0x29ea0b0, C4<0>, C4<0>;
+L_0x29ea1e0 .delay (20000,20000,20000) L_0x29ea1e0/d;
+v0x28ca4c0_0 .net "S", 0 0, L_0x29ea370; 1 drivers
+v0x28ca560_0 .alias "in0", 0 0, v0x28caa00_0;
+v0x28ca600_0 .alias "in1", 0 0, v0x28caa80_0;
+v0x28ca6a0_0 .net "nS", 0 0, L_0x29e9f20; 1 drivers
+v0x28ca720_0 .net "out0", 0 0, L_0x29e9fc0; 1 drivers
+v0x28ca7c0_0 .net "out1", 0 0, L_0x29ea0b0; 1 drivers
+v0x28ca8a0_0 .alias "outfinal", 0 0, v0x28cab30_0;
+S_0x28a2590 .scope module, "trial2" "OrNorXor32" 2 160, 3 239, S_0x22efd20;
+ .timescale -9 -12;
+P_0x289fec8 .param/l "size" 3 246, +C4<0100000>;
+v0x28c9e40_0 .alias "A", 31 0, v0x295f580_0;
+v0x28c9ec0_0 .alias "B", 31 0, v0x295f6a0_0;
+v0x28c9f40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c9fc0_0 .alias "OrNorXorOut", 31 0, v0x29603c0_0;
+L_0x29ebfa0 .part/pv L_0x29ebd70, 1, 1, 32;
+L_0x29ec0d0 .part v0x295fe90_0, 1, 1;
+L_0x29ec170 .part v0x2960190_0, 1, 1;
+L_0x29ed0e0 .part/pv L_0x29eceb0, 2, 1, 32;
+L_0x29ed180 .part v0x295fe90_0, 2, 1;
+L_0x29ed220 .part v0x2960190_0, 2, 1;
+L_0x29ee260 .part/pv L_0x29edff0, 3, 1, 32;
+L_0x29ee300 .part v0x295fe90_0, 3, 1;
+L_0x29ee3a0 .part v0x2960190_0, 3, 1;
+L_0x29ef550 .part/pv L_0x29ef2e0, 4, 1, 32;
+L_0x29ef650 .part v0x295fe90_0, 4, 1;
+L_0x29ef6f0 .part v0x2960190_0, 4, 1;
+L_0x29f0850 .part/pv L_0x29f05e0, 5, 1, 32;
+L_0x29f0a00 .part v0x295fe90_0, 5, 1;
+L_0x29f0aa0 .part v0x2960190_0, 5, 1;
+L_0x29f1c40 .part/pv L_0x29f19d0, 6, 1, 32;
+L_0x29f1ce0 .part v0x295fe90_0, 6, 1;
+L_0x29f1d80 .part v0x2960190_0, 6, 1;
+L_0x29f2f40 .part/pv L_0x29f2cd0, 7, 1, 32;
+L_0x29f2fe0 .part v0x295fe90_0, 7, 1;
+L_0x29f1e20 .part v0x2960190_0, 7, 1;
+L_0x29f4230 .part/pv L_0x29f3fc0, 8, 1, 32;
+L_0x29f3080 .part v0x295fe90_0, 8, 1;
+L_0x29f4390 .part v0x2960190_0, 8, 1;
+L_0x29f5540 .part/pv L_0x29f52d0, 9, 1, 32;
+L_0x29f55e0 .part v0x295fe90_0, 9, 1;
+L_0x29f4430 .part v0x2960190_0, 9, 1;
+L_0x29f6720 .part/pv L_0x29f64f0, 10, 1, 32;
+L_0x29f5680 .part v0x295fe90_0, 10, 1;
+L_0x29f68b0 .part v0x2960190_0, 10, 1;
+L_0x29f78e0 .part/pv L_0x29f7670, 11, 1, 32;
+L_0x29f7980 .part v0x295fe90_0, 11, 1;
+L_0x29f6950 .part v0x2960190_0, 11, 1;
+L_0x29f8bd0 .part/pv L_0x29f8960, 12, 1, 32;
+L_0x29f7a20 .part v0x295fe90_0, 12, 1;
+L_0x29f8d90 .part v0x2960190_0, 12, 1;
+L_0x29f9ef0 .part/pv L_0x29f9c80, 13, 1, 32;
+L_0x29f08f0 .part v0x295fe90_0, 13, 1;
+L_0x29f8e30 .part v0x2960190_0, 13, 1;
+L_0x29fb300 .part/pv L_0x29fb090, 14, 1, 32;
+L_0x29fa1a0 .part v0x295fe90_0, 14, 1;
+L_0x29fa240 .part v0x2960190_0, 14, 1;
+L_0x29fc600 .part/pv L_0x29fc390, 15, 1, 32;
+L_0x29fc6a0 .part v0x295fe90_0, 15, 1;
+L_0x29fb3a0 .part v0x2960190_0, 15, 1;
+L_0x29fd8f0 .part/pv L_0x29fd680, 16, 1, 32;
+L_0x29fc740 .part v0x295fe90_0, 16, 1;
+L_0x29fc7e0 .part v0x2960190_0, 16, 1;
+L_0x29fec00 .part/pv L_0x29fe990, 17, 1, 32;
+L_0x29feca0 .part v0x295fe90_0, 17, 1;
+L_0x29fd990 .part v0x2960190_0, 17, 1;
+L_0x29ffef0 .part/pv L_0x29ffc80, 18, 1, 32;
+L_0x29fed40 .part v0x295fe90_0, 18, 1;
+L_0x29fede0 .part v0x2960190_0, 18, 1;
+L_0x2a02200 .part/pv L_0x29b5c70, 19, 1, 32;
+L_0x2a022a0 .part v0x295fe90_0, 19, 1;
+L_0x29b4e70 .part v0x2960190_0, 19, 1;
+L_0x2a033c0 .part/pv L_0x2a03150, 20, 1, 32;
+L_0x2a02340 .part v0x295fe90_0, 20, 1;
+L_0x2a023e0 .part v0x2960190_0, 20, 1;
+L_0x2a046d0 .part/pv L_0x2a04460, 21, 1, 32;
+L_0x2a04770 .part v0x295fe90_0, 21, 1;
+L_0x2a03460 .part v0x2960190_0, 21, 1;
+L_0x2a059c0 .part/pv L_0x2a05750, 22, 1, 32;
+L_0x2a04810 .part v0x295fe90_0, 22, 1;
+L_0x2a048b0 .part v0x2960190_0, 22, 1;
+L_0x2a06cc0 .part/pv L_0x2a06a50, 23, 1, 32;
+L_0x2a06d60 .part v0x295fe90_0, 23, 1;
+L_0x2a05a60 .part v0x2960190_0, 23, 1;
+L_0x2a07f80 .part/pv L_0x2a07d10, 24, 1, 32;
+L_0x2a06e00 .part v0x295fe90_0, 24, 1;
+L_0x2a06ea0 .part v0x2960190_0, 24, 1;
+L_0x2a09280 .part/pv L_0x2a09010, 25, 1, 32;
+L_0x2a09320 .part v0x295fe90_0, 25, 1;
+L_0x2a08020 .part v0x2960190_0, 25, 1;
+L_0x2a0a570 .part/pv L_0x2a0a300, 26, 1, 32;
+L_0x2a093c0 .part v0x295fe90_0, 26, 1;
+L_0x2a09460 .part v0x2960190_0, 26, 1;
+L_0x2a0b880 .part/pv L_0x2a0b610, 27, 1, 32;
+L_0x2a0b920 .part v0x295fe90_0, 27, 1;
+L_0x2a0a610 .part v0x2960190_0, 27, 1;
+L_0x2a0cb80 .part/pv L_0x2a0c910, 28, 1, 32;
+L_0x2a0b9c0 .part v0x295fe90_0, 28, 1;
+L_0x2a0ba60 .part v0x2960190_0, 28, 1;
+L_0x2a0de80 .part/pv L_0x2a0dc10, 29, 1, 32;
+L_0x29f9f90 .part v0x295fe90_0, 29, 1;
+L_0x29fa030 .part v0x2960190_0, 29, 1;
+L_0x2a0f240 .part/pv L_0x2a0f010, 30, 1, 32;
+L_0x2a0e330 .part v0x295fe90_0, 30, 1;
+L_0x2a0e3d0 .part v0x2960190_0, 30, 1;
+L_0x2a10550 .part/pv L_0x2a102e0, 31, 1, 32;
+L_0x2a105f0 .part v0x295fe90_0, 31, 1;
+L_0x2a0f2e0 .part v0x2960190_0, 31, 1;
+L_0x2a11840 .part/pv L_0x2a115d0, 0, 1, 32;
+L_0x2a10690 .part v0x295fe90_0, 0, 1;
+L_0x2a10730 .part v0x2960190_0, 0, 1;
+S_0x28c8c00 .scope module, "attempt2" "OrNorXor" 3 254, 3 165, S_0x28a2590;
+ .timescale -9 -12;
+L_0x2a0f380/d .functor NOR 1, L_0x2a10690, L_0x2a10730, C4<0>, C4<0>;
+L_0x2a0f380 .delay (10000,10000,10000) L_0x2a0f380/d;
+L_0x2a0f470/d .functor NOT 1, L_0x2a0f380, C4<0>, C4<0>, C4<0>;
+L_0x2a0f470 .delay (10000,10000,10000) L_0x2a0f470/d;
+L_0x2a10980/d .functor NAND 1, L_0x2a10690, L_0x2a10730, C4<1>, C4<1>;
+L_0x2a10980 .delay (10000,10000,10000) L_0x2a10980/d;
+L_0x2a10ac0/d .functor NAND 1, L_0x2a10980, L_0x2a0f470, C4<1>, C4<1>;
+L_0x2a10ac0 .delay (10000,10000,10000) L_0x2a10ac0/d;
+L_0x2a10bd0/d .functor NOT 1, L_0x2a10ac0, C4<0>, C4<0>, C4<0>;
+L_0x2a10bd0 .delay (10000,10000,10000) L_0x2a10bd0/d;
+v0x28c9750_0 .net "A", 0 0, L_0x2a10690; 1 drivers
+v0x28c97f0_0 .net "AnandB", 0 0, L_0x2a10980; 1 drivers
+v0x28c9890_0 .net "AnorB", 0 0, L_0x2a0f380; 1 drivers
+v0x28c9940_0 .net "AorB", 0 0, L_0x2a0f470; 1 drivers
+v0x28c9a20_0 .net "AxorB", 0 0, L_0x2a10bd0; 1 drivers
+v0x28c9ad0_0 .net "B", 0 0, L_0x2a10730; 1 drivers
+v0x28c9b90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c9c10_0 .net "OrNorXorOut", 0 0, L_0x2a115d0; 1 drivers
+v0x28c9c90_0 .net "XorNor", 0 0, L_0x2a11050; 1 drivers
+v0x28c9d60_0 .net "nXor", 0 0, L_0x2a10ac0; 1 drivers
+L_0x2a111d0 .part v0x2960210_0, 2, 1;
+L_0x2a117a0 .part v0x2960210_0, 0, 1;
+S_0x28c91e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c8c00;
+ .timescale -9 -12;
+L_0x2a10d30/d .functor NOT 1, L_0x2a111d0, C4<0>, C4<0>, C4<0>;
+L_0x2a10d30 .delay (10000,10000,10000) L_0x2a10d30/d;
+L_0x2a10df0/d .functor AND 1, L_0x2a10bd0, L_0x2a10d30, C4<1>, C4<1>;
+L_0x2a10df0 .delay (20000,20000,20000) L_0x2a10df0/d;
+L_0x2a10f00/d .functor AND 1, L_0x2a0f380, L_0x2a111d0, C4<1>, C4<1>;
+L_0x2a10f00 .delay (20000,20000,20000) L_0x2a10f00/d;
+L_0x2a11050/d .functor OR 1, L_0x2a10df0, L_0x2a10f00, C4<0>, C4<0>;
+L_0x2a11050 .delay (20000,20000,20000) L_0x2a11050/d;
+v0x28c92d0_0 .net "S", 0 0, L_0x2a111d0; 1 drivers
+v0x28c9390_0 .alias "in0", 0 0, v0x28c9a20_0;
+v0x28c9430_0 .alias "in1", 0 0, v0x28c9890_0;
+v0x28c94d0_0 .net "nS", 0 0, L_0x2a10d30; 1 drivers
+v0x28c9550_0 .net "out0", 0 0, L_0x2a10df0; 1 drivers
+v0x28c95f0_0 .net "out1", 0 0, L_0x2a10f00; 1 drivers
+v0x28c96d0_0 .alias "outfinal", 0 0, v0x28c9c90_0;
+S_0x28c8cf0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c8c00;
+ .timescale -9 -12;
+L_0x2a11270/d .functor NOT 1, L_0x2a117a0, C4<0>, C4<0>, C4<0>;
+L_0x2a11270 .delay (10000,10000,10000) L_0x2a11270/d;
+L_0x2a11330/d .functor AND 1, L_0x2a11050, L_0x2a11270, C4<1>, C4<1>;
+L_0x2a11330 .delay (20000,20000,20000) L_0x2a11330/d;
+L_0x2a11480/d .functor AND 1, L_0x2a0f470, L_0x2a117a0, C4<1>, C4<1>;
+L_0x2a11480 .delay (20000,20000,20000) L_0x2a11480/d;
+L_0x2a115d0/d .functor OR 1, L_0x2a11330, L_0x2a11480, C4<0>, C4<0>;
+L_0x2a115d0 .delay (20000,20000,20000) L_0x2a115d0/d;
+v0x28c8de0_0 .net "S", 0 0, L_0x2a117a0; 1 drivers
+v0x28c8e60_0 .alias "in0", 0 0, v0x28c9c90_0;
+v0x28c8ee0_0 .alias "in1", 0 0, v0x28c9940_0;
+v0x28c8f80_0 .net "nS", 0 0, L_0x2a11270; 1 drivers
+v0x28c9000_0 .net "out0", 0 0, L_0x2a11330; 1 drivers
+v0x28c90a0_0 .net "out1", 0 0, L_0x2a11480; 1 drivers
+v0x28c9140_0 .alias "outfinal", 0 0, v0x28c9c10_0;
+S_0x28c7830 .scope generate, "orbits[1]" "orbits[1]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28c7548 .param/l "i" 3 258, +C4<01>;
+S_0x28c7960 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c7830;
+ .timescale -9 -12;
+L_0x29ea6e0/d .functor NOR 1, L_0x29ec0d0, L_0x29ec170, C4<0>, C4<0>;
+L_0x29ea6e0 .delay (10000,10000,10000) L_0x29ea6e0/d;
+L_0x29eb170/d .functor NOT 1, L_0x29ea6e0, C4<0>, C4<0>, C4<0>;
+L_0x29eb170 .delay (10000,10000,10000) L_0x29eb170/d;
+L_0x29eb260/d .functor NAND 1, L_0x29ec0d0, L_0x29ec170, C4<1>, C4<1>;
+L_0x29eb260 .delay (10000,10000,10000) L_0x29eb260/d;
+L_0x29eb3a0/d .functor NAND 1, L_0x29eb260, L_0x29eb170, C4<1>, C4<1>;
+L_0x29eb3a0 .delay (10000,10000,10000) L_0x29eb3a0/d;
+L_0x29eb490/d .functor NOT 1, L_0x29eb3a0, C4<0>, C4<0>, C4<0>;
+L_0x29eb490 .delay (10000,10000,10000) L_0x29eb490/d;
+v0x28c8510_0 .net "A", 0 0, L_0x29ec0d0; 1 drivers
+v0x28c85b0_0 .net "AnandB", 0 0, L_0x29eb260; 1 drivers
+v0x28c8650_0 .net "AnorB", 0 0, L_0x29ea6e0; 1 drivers
+v0x28c8700_0 .net "AorB", 0 0, L_0x29eb170; 1 drivers
+v0x28c87e0_0 .net "AxorB", 0 0, L_0x29eb490; 1 drivers
+v0x28c8890_0 .net "B", 0 0, L_0x29ec170; 1 drivers
+v0x28c8950_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c89d0_0 .net "OrNorXorOut", 0 0, L_0x29ebd70; 1 drivers
+v0x28c8a50_0 .net "XorNor", 0 0, L_0x29eb890; 1 drivers
+v0x28c8b20_0 .net "nXor", 0 0, L_0x29eb3a0; 1 drivers
+L_0x29eb9d0 .part v0x2960210_0, 2, 1;
+L_0x29ebf00 .part v0x2960210_0, 0, 1;
+S_0x28c7fa0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c7960;
+ .timescale -9 -12;
+L_0x29eb5d0/d .functor NOT 1, L_0x29eb9d0, C4<0>, C4<0>, C4<0>;
+L_0x29eb5d0 .delay (10000,10000,10000) L_0x29eb5d0/d;
+L_0x29eb670/d .functor AND 1, L_0x29eb490, L_0x29eb5d0, C4<1>, C4<1>;
+L_0x29eb670 .delay (20000,20000,20000) L_0x29eb670/d;
+L_0x29eb760/d .functor AND 1, L_0x29ea6e0, L_0x29eb9d0, C4<1>, C4<1>;
+L_0x29eb760 .delay (20000,20000,20000) L_0x29eb760/d;
+L_0x29eb890/d .functor OR 1, L_0x29eb670, L_0x29eb760, C4<0>, C4<0>;
+L_0x29eb890 .delay (20000,20000,20000) L_0x29eb890/d;
+v0x28c8090_0 .net "S", 0 0, L_0x29eb9d0; 1 drivers
+v0x28c8150_0 .alias "in0", 0 0, v0x28c87e0_0;
+v0x28c81f0_0 .alias "in1", 0 0, v0x28c8650_0;
+v0x28c8290_0 .net "nS", 0 0, L_0x29eb5d0; 1 drivers
+v0x28c8310_0 .net "out0", 0 0, L_0x29eb670; 1 drivers
+v0x28c83b0_0 .net "out1", 0 0, L_0x29eb760; 1 drivers
+v0x28c8490_0 .alias "outfinal", 0 0, v0x28c8a50_0;
+S_0x28c7a50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c7960;
+ .timescale -9 -12;
+L_0x29eba70/d .functor NOT 1, L_0x29ebf00, C4<0>, C4<0>, C4<0>;
+L_0x29eba70 .delay (10000,10000,10000) L_0x29eba70/d;
+L_0x29ebb10/d .functor AND 1, L_0x29eb890, L_0x29eba70, C4<1>, C4<1>;
+L_0x29ebb10 .delay (20000,20000,20000) L_0x29ebb10/d;
+L_0x29ebc40/d .functor AND 1, L_0x29eb170, L_0x29ebf00, C4<1>, C4<1>;
+L_0x29ebc40 .delay (20000,20000,20000) L_0x29ebc40/d;
+L_0x29ebd70/d .functor OR 1, L_0x29ebb10, L_0x29ebc40, C4<0>, C4<0>;
+L_0x29ebd70 .delay (20000,20000,20000) L_0x29ebd70/d;
+v0x28c7b40_0 .net "S", 0 0, L_0x29ebf00; 1 drivers
+v0x28c7bc0_0 .alias "in0", 0 0, v0x28c8a50_0;
+v0x28c7c60_0 .alias "in1", 0 0, v0x28c8700_0;
+v0x28c7d00_0 .net "nS", 0 0, L_0x29eba70; 1 drivers
+v0x28c7d80_0 .net "out0", 0 0, L_0x29ebb10; 1 drivers
+v0x28c7e20_0 .net "out1", 0 0, L_0x29ebc40; 1 drivers
+v0x28c7f00_0 .alias "outfinal", 0 0, v0x28c89d0_0;
+S_0x28c6460 .scope generate, "orbits[2]" "orbits[2]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28c6178 .param/l "i" 3 258, +C4<010>;
+S_0x28c6590 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c6460;
+ .timescale -9 -12;
+L_0x29ec210/d .functor NOR 1, L_0x29ed180, L_0x29ed220, C4<0>, C4<0>;
+L_0x29ec210 .delay (10000,10000,10000) L_0x29ec210/d;
+L_0x29ec2b0/d .functor NOT 1, L_0x29ec210, C4<0>, C4<0>, C4<0>;
+L_0x29ec2b0 .delay (10000,10000,10000) L_0x29ec2b0/d;
+L_0x29ec3a0/d .functor NAND 1, L_0x29ed180, L_0x29ed220, C4<1>, C4<1>;
+L_0x29ec3a0 .delay (10000,10000,10000) L_0x29ec3a0/d;
+L_0x29ec4e0/d .functor NAND 1, L_0x29ec3a0, L_0x29ec2b0, C4<1>, C4<1>;
+L_0x29ec4e0 .delay (10000,10000,10000) L_0x29ec4e0/d;
+L_0x29ec5d0/d .functor NOT 1, L_0x29ec4e0, C4<0>, C4<0>, C4<0>;
+L_0x29ec5d0 .delay (10000,10000,10000) L_0x29ec5d0/d;
+v0x28c7140_0 .net "A", 0 0, L_0x29ed180; 1 drivers
+v0x28c71e0_0 .net "AnandB", 0 0, L_0x29ec3a0; 1 drivers
+v0x28c7280_0 .net "AnorB", 0 0, L_0x29ec210; 1 drivers
+v0x28c7330_0 .net "AorB", 0 0, L_0x29ec2b0; 1 drivers
+v0x28c7410_0 .net "AxorB", 0 0, L_0x29ec5d0; 1 drivers
+v0x28c74c0_0 .net "B", 0 0, L_0x29ed220; 1 drivers
+v0x28c7580_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c7600_0 .net "OrNorXorOut", 0 0, L_0x29eceb0; 1 drivers
+v0x28c7680_0 .net "XorNor", 0 0, L_0x29ec9d0; 1 drivers
+v0x28c7750_0 .net "nXor", 0 0, L_0x29ec4e0; 1 drivers
+L_0x29ecb10 .part v0x2960210_0, 2, 1;
+L_0x29ed040 .part v0x2960210_0, 0, 1;
+S_0x28c6bd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c6590;
+ .timescale -9 -12;
+L_0x29ec710/d .functor NOT 1, L_0x29ecb10, C4<0>, C4<0>, C4<0>;
+L_0x29ec710 .delay (10000,10000,10000) L_0x29ec710/d;
+L_0x29ec7b0/d .functor AND 1, L_0x29ec5d0, L_0x29ec710, C4<1>, C4<1>;
+L_0x29ec7b0 .delay (20000,20000,20000) L_0x29ec7b0/d;
+L_0x29ec8a0/d .functor AND 1, L_0x29ec210, L_0x29ecb10, C4<1>, C4<1>;
+L_0x29ec8a0 .delay (20000,20000,20000) L_0x29ec8a0/d;
+L_0x29ec9d0/d .functor OR 1, L_0x29ec7b0, L_0x29ec8a0, C4<0>, C4<0>;
+L_0x29ec9d0 .delay (20000,20000,20000) L_0x29ec9d0/d;
+v0x28c6cc0_0 .net "S", 0 0, L_0x29ecb10; 1 drivers
+v0x28c6d80_0 .alias "in0", 0 0, v0x28c7410_0;
+v0x28c6e20_0 .alias "in1", 0 0, v0x28c7280_0;
+v0x28c6ec0_0 .net "nS", 0 0, L_0x29ec710; 1 drivers
+v0x28c6f40_0 .net "out0", 0 0, L_0x29ec7b0; 1 drivers
+v0x28c6fe0_0 .net "out1", 0 0, L_0x29ec8a0; 1 drivers
+v0x28c70c0_0 .alias "outfinal", 0 0, v0x28c7680_0;
+S_0x28c6680 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c6590;
+ .timescale -9 -12;
+L_0x29ecbb0/d .functor NOT 1, L_0x29ed040, C4<0>, C4<0>, C4<0>;
+L_0x29ecbb0 .delay (10000,10000,10000) L_0x29ecbb0/d;
+L_0x29ecc50/d .functor AND 1, L_0x29ec9d0, L_0x29ecbb0, C4<1>, C4<1>;
+L_0x29ecc50 .delay (20000,20000,20000) L_0x29ecc50/d;
+L_0x29ecd80/d .functor AND 1, L_0x29ec2b0, L_0x29ed040, C4<1>, C4<1>;
+L_0x29ecd80 .delay (20000,20000,20000) L_0x29ecd80/d;
+L_0x29eceb0/d .functor OR 1, L_0x29ecc50, L_0x29ecd80, C4<0>, C4<0>;
+L_0x29eceb0 .delay (20000,20000,20000) L_0x29eceb0/d;
+v0x28c6770_0 .net "S", 0 0, L_0x29ed040; 1 drivers
+v0x28c67f0_0 .alias "in0", 0 0, v0x28c7680_0;
+v0x28c6890_0 .alias "in1", 0 0, v0x28c7330_0;
+v0x28c6930_0 .net "nS", 0 0, L_0x29ecbb0; 1 drivers
+v0x28c69b0_0 .net "out0", 0 0, L_0x29ecc50; 1 drivers
+v0x28c6a50_0 .net "out1", 0 0, L_0x29ecd80; 1 drivers
+v0x28c6b30_0 .alias "outfinal", 0 0, v0x28c7600_0;
+S_0x28c5090 .scope generate, "orbits[3]" "orbits[3]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28c4da8 .param/l "i" 3 258, +C4<011>;
+S_0x28c51c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c5090;
+ .timescale -9 -12;
+L_0x29ed300/d .functor NOR 1, L_0x29ee300, L_0x29ee3a0, C4<0>, C4<0>;
+L_0x29ed300 .delay (10000,10000,10000) L_0x29ed300/d;
+L_0x29ed3f0/d .functor NOT 1, L_0x29ed300, C4<0>, C4<0>, C4<0>;
+L_0x29ed3f0 .delay (10000,10000,10000) L_0x29ed3f0/d;
+L_0x29ed4e0/d .functor NAND 1, L_0x29ee300, L_0x29ee3a0, C4<1>, C4<1>;
+L_0x29ed4e0 .delay (10000,10000,10000) L_0x29ed4e0/d;
+L_0x29ed620/d .functor NAND 1, L_0x29ed4e0, L_0x29ed3f0, C4<1>, C4<1>;
+L_0x29ed620 .delay (10000,10000,10000) L_0x29ed620/d;
+L_0x29ed710/d .functor NOT 1, L_0x29ed620, C4<0>, C4<0>, C4<0>;
+L_0x29ed710 .delay (10000,10000,10000) L_0x29ed710/d;
+v0x28c5d70_0 .net "A", 0 0, L_0x29ee300; 1 drivers
+v0x28c5e10_0 .net "AnandB", 0 0, L_0x29ed4e0; 1 drivers
+v0x28c5eb0_0 .net "AnorB", 0 0, L_0x29ed300; 1 drivers
+v0x28c5f60_0 .net "AorB", 0 0, L_0x29ed3f0; 1 drivers
+v0x28c6040_0 .net "AxorB", 0 0, L_0x29ed710; 1 drivers
+v0x28c60f0_0 .net "B", 0 0, L_0x29ee3a0; 1 drivers
+v0x28c61b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c6230_0 .net "OrNorXorOut", 0 0, L_0x29edff0; 1 drivers
+v0x28c62b0_0 .net "XorNor", 0 0, L_0x29edb10; 1 drivers
+v0x28c6380_0 .net "nXor", 0 0, L_0x29ed620; 1 drivers
+L_0x29edc50 .part v0x2960210_0, 2, 1;
+L_0x29ee1c0 .part v0x2960210_0, 0, 1;
+S_0x28c5800 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c51c0;
+ .timescale -9 -12;
+L_0x29ed850/d .functor NOT 1, L_0x29edc50, C4<0>, C4<0>, C4<0>;
+L_0x29ed850 .delay (10000,10000,10000) L_0x29ed850/d;
+L_0x29ed8f0/d .functor AND 1, L_0x29ed710, L_0x29ed850, C4<1>, C4<1>;
+L_0x29ed8f0 .delay (20000,20000,20000) L_0x29ed8f0/d;
+L_0x29ed9e0/d .functor AND 1, L_0x29ed300, L_0x29edc50, C4<1>, C4<1>;
+L_0x29ed9e0 .delay (20000,20000,20000) L_0x29ed9e0/d;
+L_0x29edb10/d .functor OR 1, L_0x29ed8f0, L_0x29ed9e0, C4<0>, C4<0>;
+L_0x29edb10 .delay (20000,20000,20000) L_0x29edb10/d;
+v0x28c58f0_0 .net "S", 0 0, L_0x29edc50; 1 drivers
+v0x28c59b0_0 .alias "in0", 0 0, v0x28c6040_0;
+v0x28c5a50_0 .alias "in1", 0 0, v0x28c5eb0_0;
+v0x28c5af0_0 .net "nS", 0 0, L_0x29ed850; 1 drivers
+v0x28c5b70_0 .net "out0", 0 0, L_0x29ed8f0; 1 drivers
+v0x28c5c10_0 .net "out1", 0 0, L_0x29ed9e0; 1 drivers
+v0x28c5cf0_0 .alias "outfinal", 0 0, v0x28c62b0_0;
+S_0x28c52b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c51c0;
+ .timescale -9 -12;
+L_0x29edcf0/d .functor NOT 1, L_0x29ee1c0, C4<0>, C4<0>, C4<0>;
+L_0x29edcf0 .delay (10000,10000,10000) L_0x29edcf0/d;
+L_0x29edd90/d .functor AND 1, L_0x29edb10, L_0x29edcf0, C4<1>, C4<1>;
+L_0x29edd90 .delay (20000,20000,20000) L_0x29edd90/d;
+L_0x29edec0/d .functor AND 1, L_0x29ed3f0, L_0x29ee1c0, C4<1>, C4<1>;
+L_0x29edec0 .delay (20000,20000,20000) L_0x29edec0/d;
+L_0x29edff0/d .functor OR 1, L_0x29edd90, L_0x29edec0, C4<0>, C4<0>;
+L_0x29edff0 .delay (20000,20000,20000) L_0x29edff0/d;
+v0x28c53a0_0 .net "S", 0 0, L_0x29ee1c0; 1 drivers
+v0x28c5420_0 .alias "in0", 0 0, v0x28c62b0_0;
+v0x28c54c0_0 .alias "in1", 0 0, v0x28c5f60_0;
+v0x28c5560_0 .net "nS", 0 0, L_0x29edcf0; 1 drivers
+v0x28c55e0_0 .net "out0", 0 0, L_0x29edd90; 1 drivers
+v0x28c5680_0 .net "out1", 0 0, L_0x29edec0; 1 drivers
+v0x28c5760_0 .alias "outfinal", 0 0, v0x28c6230_0;
+S_0x28c3cc0 .scope generate, "orbits[4]" "orbits[4]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28c39d8 .param/l "i" 3 258, +C4<0100>;
+S_0x28c3df0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c3cc0;
+ .timescale -9 -12;
+L_0x29ee440/d .functor NOR 1, L_0x29ef650, L_0x29ef6f0, C4<0>, C4<0>;
+L_0x29ee440 .delay (10000,10000,10000) L_0x29ee440/d;
+L_0x29ee540/d .functor NOT 1, L_0x29ee440, C4<0>, C4<0>, C4<0>;
+L_0x29ee540 .delay (10000,10000,10000) L_0x29ee540/d;
+L_0x29ee670/d .functor NAND 1, L_0x29ef650, L_0x29ef6f0, C4<1>, C4<1>;
+L_0x29ee670 .delay (10000,10000,10000) L_0x29ee670/d;
+L_0x29ee7d0/d .functor NAND 1, L_0x29ee670, L_0x29ee540, C4<1>, C4<1>;
+L_0x29ee7d0 .delay (10000,10000,10000) L_0x29ee7d0/d;
+L_0x29ee8e0/d .functor NOT 1, L_0x29ee7d0, C4<0>, C4<0>, C4<0>;
+L_0x29ee8e0 .delay (10000,10000,10000) L_0x29ee8e0/d;
+v0x28c49a0_0 .net "A", 0 0, L_0x29ef650; 1 drivers
+v0x28c4a40_0 .net "AnandB", 0 0, L_0x29ee670; 1 drivers
+v0x28c4ae0_0 .net "AnorB", 0 0, L_0x29ee440; 1 drivers
+v0x28c4b90_0 .net "AorB", 0 0, L_0x29ee540; 1 drivers
+v0x28c4c70_0 .net "AxorB", 0 0, L_0x29ee8e0; 1 drivers
+v0x28c4d20_0 .net "B", 0 0, L_0x29ef6f0; 1 drivers
+v0x28c4de0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c4e60_0 .net "OrNorXorOut", 0 0, L_0x29ef2e0; 1 drivers
+v0x28c4ee0_0 .net "XorNor", 0 0, L_0x29eed60; 1 drivers
+v0x28c4fb0_0 .net "nXor", 0 0, L_0x29ee7d0; 1 drivers
+L_0x29eeee0 .part v0x2960210_0, 2, 1;
+L_0x29ef4b0 .part v0x2960210_0, 0, 1;
+S_0x28c4430 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c3df0;
+ .timescale -9 -12;
+L_0x29eea40/d .functor NOT 1, L_0x29eeee0, C4<0>, C4<0>, C4<0>;
+L_0x29eea40 .delay (10000,10000,10000) L_0x29eea40/d;
+L_0x29eeb00/d .functor AND 1, L_0x29ee8e0, L_0x29eea40, C4<1>, C4<1>;
+L_0x29eeb00 .delay (20000,20000,20000) L_0x29eeb00/d;
+L_0x29eec10/d .functor AND 1, L_0x29ee440, L_0x29eeee0, C4<1>, C4<1>;
+L_0x29eec10 .delay (20000,20000,20000) L_0x29eec10/d;
+L_0x29eed60/d .functor OR 1, L_0x29eeb00, L_0x29eec10, C4<0>, C4<0>;
+L_0x29eed60 .delay (20000,20000,20000) L_0x29eed60/d;
+v0x28c4520_0 .net "S", 0 0, L_0x29eeee0; 1 drivers
+v0x28c45e0_0 .alias "in0", 0 0, v0x28c4c70_0;
+v0x28c4680_0 .alias "in1", 0 0, v0x28c4ae0_0;
+v0x28c4720_0 .net "nS", 0 0, L_0x29eea40; 1 drivers
+v0x28c47a0_0 .net "out0", 0 0, L_0x29eeb00; 1 drivers
+v0x28c4840_0 .net "out1", 0 0, L_0x29eec10; 1 drivers
+v0x28c4920_0 .alias "outfinal", 0 0, v0x28c4ee0_0;
+S_0x28c3ee0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c3df0;
+ .timescale -9 -12;
+L_0x29eef80/d .functor NOT 1, L_0x29ef4b0, C4<0>, C4<0>, C4<0>;
+L_0x29eef80 .delay (10000,10000,10000) L_0x29eef80/d;
+L_0x29ef040/d .functor AND 1, L_0x29eed60, L_0x29eef80, C4<1>, C4<1>;
+L_0x29ef040 .delay (20000,20000,20000) L_0x29ef040/d;
+L_0x29ef190/d .functor AND 1, L_0x29ee540, L_0x29ef4b0, C4<1>, C4<1>;
+L_0x29ef190 .delay (20000,20000,20000) L_0x29ef190/d;
+L_0x29ef2e0/d .functor OR 1, L_0x29ef040, L_0x29ef190, C4<0>, C4<0>;
+L_0x29ef2e0 .delay (20000,20000,20000) L_0x29ef2e0/d;
+v0x28c3fd0_0 .net "S", 0 0, L_0x29ef4b0; 1 drivers
+v0x28c4050_0 .alias "in0", 0 0, v0x28c4ee0_0;
+v0x28c40f0_0 .alias "in1", 0 0, v0x28c4b90_0;
+v0x28c4190_0 .net "nS", 0 0, L_0x29eef80; 1 drivers
+v0x28c4210_0 .net "out0", 0 0, L_0x29ef040; 1 drivers
+v0x28c42b0_0 .net "out1", 0 0, L_0x29ef190; 1 drivers
+v0x28c4390_0 .alias "outfinal", 0 0, v0x28c4e60_0;
+S_0x28c28f0 .scope generate, "orbits[5]" "orbits[5]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28c2608 .param/l "i" 3 258, +C4<0101>;
+S_0x28c2a20 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c28f0;
+ .timescale -9 -12;
+L_0x29ef5f0/d .functor NOR 1, L_0x29f0a00, L_0x29f0aa0, C4<0>, C4<0>;
+L_0x29ef5f0 .delay (10000,10000,10000) L_0x29ef5f0/d;
+L_0x29ef840/d .functor NOT 1, L_0x29ef5f0, C4<0>, C4<0>, C4<0>;
+L_0x29ef840 .delay (10000,10000,10000) L_0x29ef840/d;
+L_0x29ef970/d .functor NAND 1, L_0x29f0a00, L_0x29f0aa0, C4<1>, C4<1>;
+L_0x29ef970 .delay (10000,10000,10000) L_0x29ef970/d;
+L_0x29efad0/d .functor NAND 1, L_0x29ef970, L_0x29ef840, C4<1>, C4<1>;
+L_0x29efad0 .delay (10000,10000,10000) L_0x29efad0/d;
+L_0x29efbe0/d .functor NOT 1, L_0x29efad0, C4<0>, C4<0>, C4<0>;
+L_0x29efbe0 .delay (10000,10000,10000) L_0x29efbe0/d;
+v0x28c35d0_0 .net "A", 0 0, L_0x29f0a00; 1 drivers
+v0x28c3670_0 .net "AnandB", 0 0, L_0x29ef970; 1 drivers
+v0x28c3710_0 .net "AnorB", 0 0, L_0x29ef5f0; 1 drivers
+v0x28c37c0_0 .net "AorB", 0 0, L_0x29ef840; 1 drivers
+v0x28c38a0_0 .net "AxorB", 0 0, L_0x29efbe0; 1 drivers
+v0x28c3950_0 .net "B", 0 0, L_0x29f0aa0; 1 drivers
+v0x28c3a10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c3a90_0 .net "OrNorXorOut", 0 0, L_0x29f05e0; 1 drivers
+v0x28c3b10_0 .net "XorNor", 0 0, L_0x29f0060; 1 drivers
+v0x28c3be0_0 .net "nXor", 0 0, L_0x29efad0; 1 drivers
+L_0x29f01e0 .part v0x2960210_0, 2, 1;
+L_0x29f07b0 .part v0x2960210_0, 0, 1;
+S_0x28c3060 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c2a20;
+ .timescale -9 -12;
+L_0x29efd40/d .functor NOT 1, L_0x29f01e0, C4<0>, C4<0>, C4<0>;
+L_0x29efd40 .delay (10000,10000,10000) L_0x29efd40/d;
+L_0x29efe00/d .functor AND 1, L_0x29efbe0, L_0x29efd40, C4<1>, C4<1>;
+L_0x29efe00 .delay (20000,20000,20000) L_0x29efe00/d;
+L_0x29eff10/d .functor AND 1, L_0x29ef5f0, L_0x29f01e0, C4<1>, C4<1>;
+L_0x29eff10 .delay (20000,20000,20000) L_0x29eff10/d;
+L_0x29f0060/d .functor OR 1, L_0x29efe00, L_0x29eff10, C4<0>, C4<0>;
+L_0x29f0060 .delay (20000,20000,20000) L_0x29f0060/d;
+v0x28c3150_0 .net "S", 0 0, L_0x29f01e0; 1 drivers
+v0x28c3210_0 .alias "in0", 0 0, v0x28c38a0_0;
+v0x28c32b0_0 .alias "in1", 0 0, v0x28c3710_0;
+v0x28c3350_0 .net "nS", 0 0, L_0x29efd40; 1 drivers
+v0x28c33d0_0 .net "out0", 0 0, L_0x29efe00; 1 drivers
+v0x28c3470_0 .net "out1", 0 0, L_0x29eff10; 1 drivers
+v0x28c3550_0 .alias "outfinal", 0 0, v0x28c3b10_0;
+S_0x28c2b10 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c2a20;
+ .timescale -9 -12;
+L_0x29f0280/d .functor NOT 1, L_0x29f07b0, C4<0>, C4<0>, C4<0>;
+L_0x29f0280 .delay (10000,10000,10000) L_0x29f0280/d;
+L_0x29f0340/d .functor AND 1, L_0x29f0060, L_0x29f0280, C4<1>, C4<1>;
+L_0x29f0340 .delay (20000,20000,20000) L_0x29f0340/d;
+L_0x29f0490/d .functor AND 1, L_0x29ef840, L_0x29f07b0, C4<1>, C4<1>;
+L_0x29f0490 .delay (20000,20000,20000) L_0x29f0490/d;
+L_0x29f05e0/d .functor OR 1, L_0x29f0340, L_0x29f0490, C4<0>, C4<0>;
+L_0x29f05e0 .delay (20000,20000,20000) L_0x29f05e0/d;
+v0x28c2c00_0 .net "S", 0 0, L_0x29f07b0; 1 drivers
+v0x28c2c80_0 .alias "in0", 0 0, v0x28c3b10_0;
+v0x28c2d20_0 .alias "in1", 0 0, v0x28c37c0_0;
+v0x28c2dc0_0 .net "nS", 0 0, L_0x29f0280; 1 drivers
+v0x28c2e40_0 .net "out0", 0 0, L_0x29f0340; 1 drivers
+v0x28c2ee0_0 .net "out1", 0 0, L_0x29f0490; 1 drivers
+v0x28c2fc0_0 .alias "outfinal", 0 0, v0x28c3a90_0;
+S_0x28c1520 .scope generate, "orbits[6]" "orbits[6]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28c1238 .param/l "i" 3 258, +C4<0110>;
+S_0x28c1650 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c1520;
+ .timescale -9 -12;
+L_0x29f0b40/d .functor NOR 1, L_0x29f1ce0, L_0x29f1d80, C4<0>, C4<0>;
+L_0x29f0b40 .delay (10000,10000,10000) L_0x29f0b40/d;
+L_0x29f0c30/d .functor NOT 1, L_0x29f0b40, C4<0>, C4<0>, C4<0>;
+L_0x29f0c30 .delay (10000,10000,10000) L_0x29f0c30/d;
+L_0x29f0d60/d .functor NAND 1, L_0x29f1ce0, L_0x29f1d80, C4<1>, C4<1>;
+L_0x29f0d60 .delay (10000,10000,10000) L_0x29f0d60/d;
+L_0x29f0ec0/d .functor NAND 1, L_0x29f0d60, L_0x29f0c30, C4<1>, C4<1>;
+L_0x29f0ec0 .delay (10000,10000,10000) L_0x29f0ec0/d;
+L_0x29f0fd0/d .functor NOT 1, L_0x29f0ec0, C4<0>, C4<0>, C4<0>;
+L_0x29f0fd0 .delay (10000,10000,10000) L_0x29f0fd0/d;
+v0x28c2200_0 .net "A", 0 0, L_0x29f1ce0; 1 drivers
+v0x28c22a0_0 .net "AnandB", 0 0, L_0x29f0d60; 1 drivers
+v0x28c2340_0 .net "AnorB", 0 0, L_0x29f0b40; 1 drivers
+v0x28c23f0_0 .net "AorB", 0 0, L_0x29f0c30; 1 drivers
+v0x28c24d0_0 .net "AxorB", 0 0, L_0x29f0fd0; 1 drivers
+v0x28c2580_0 .net "B", 0 0, L_0x29f1d80; 1 drivers
+v0x28c2640_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c26c0_0 .net "OrNorXorOut", 0 0, L_0x29f19d0; 1 drivers
+v0x28c2740_0 .net "XorNor", 0 0, L_0x29f1450; 1 drivers
+v0x28c2810_0 .net "nXor", 0 0, L_0x29f0ec0; 1 drivers
+L_0x29f15d0 .part v0x2960210_0, 2, 1;
+L_0x29f1ba0 .part v0x2960210_0, 0, 1;
+S_0x28c1c90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c1650;
+ .timescale -9 -12;
+L_0x29f1130/d .functor NOT 1, L_0x29f15d0, C4<0>, C4<0>, C4<0>;
+L_0x29f1130 .delay (10000,10000,10000) L_0x29f1130/d;
+L_0x29f11f0/d .functor AND 1, L_0x29f0fd0, L_0x29f1130, C4<1>, C4<1>;
+L_0x29f11f0 .delay (20000,20000,20000) L_0x29f11f0/d;
+L_0x29f1300/d .functor AND 1, L_0x29f0b40, L_0x29f15d0, C4<1>, C4<1>;
+L_0x29f1300 .delay (20000,20000,20000) L_0x29f1300/d;
+L_0x29f1450/d .functor OR 1, L_0x29f11f0, L_0x29f1300, C4<0>, C4<0>;
+L_0x29f1450 .delay (20000,20000,20000) L_0x29f1450/d;
+v0x28c1d80_0 .net "S", 0 0, L_0x29f15d0; 1 drivers
+v0x28c1e40_0 .alias "in0", 0 0, v0x28c24d0_0;
+v0x28c1ee0_0 .alias "in1", 0 0, v0x28c2340_0;
+v0x28c1f80_0 .net "nS", 0 0, L_0x29f1130; 1 drivers
+v0x28c2000_0 .net "out0", 0 0, L_0x29f11f0; 1 drivers
+v0x28c20a0_0 .net "out1", 0 0, L_0x29f1300; 1 drivers
+v0x28c2180_0 .alias "outfinal", 0 0, v0x28c2740_0;
+S_0x28c1740 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c1650;
+ .timescale -9 -12;
+L_0x29f1670/d .functor NOT 1, L_0x29f1ba0, C4<0>, C4<0>, C4<0>;
+L_0x29f1670 .delay (10000,10000,10000) L_0x29f1670/d;
+L_0x29f1730/d .functor AND 1, L_0x29f1450, L_0x29f1670, C4<1>, C4<1>;
+L_0x29f1730 .delay (20000,20000,20000) L_0x29f1730/d;
+L_0x29f1880/d .functor AND 1, L_0x29f0c30, L_0x29f1ba0, C4<1>, C4<1>;
+L_0x29f1880 .delay (20000,20000,20000) L_0x29f1880/d;
+L_0x29f19d0/d .functor OR 1, L_0x29f1730, L_0x29f1880, C4<0>, C4<0>;
+L_0x29f19d0 .delay (20000,20000,20000) L_0x29f19d0/d;
+v0x28c1830_0 .net "S", 0 0, L_0x29f1ba0; 1 drivers
+v0x28c18b0_0 .alias "in0", 0 0, v0x28c2740_0;
+v0x28c1950_0 .alias "in1", 0 0, v0x28c23f0_0;
+v0x28c19f0_0 .net "nS", 0 0, L_0x29f1670; 1 drivers
+v0x28c1a70_0 .net "out0", 0 0, L_0x29f1730; 1 drivers
+v0x28c1b10_0 .net "out1", 0 0, L_0x29f1880; 1 drivers
+v0x28c1bf0_0 .alias "outfinal", 0 0, v0x28c26c0_0;
+S_0x28c0150 .scope generate, "orbits[7]" "orbits[7]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28bfe68 .param/l "i" 3 258, +C4<0111>;
+S_0x28c0280 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28c0150;
+ .timescale -9 -12;
+L_0x29ec040/d .functor NOR 1, L_0x29f2fe0, L_0x29f1e20, C4<0>, C4<0>;
+L_0x29ec040 .delay (10000,10000,10000) L_0x29ec040/d;
+L_0x29f1f50/d .functor NOT 1, L_0x29ec040, C4<0>, C4<0>, C4<0>;
+L_0x29f1f50 .delay (10000,10000,10000) L_0x29f1f50/d;
+L_0x29f2060/d .functor NAND 1, L_0x29f2fe0, L_0x29f1e20, C4<1>, C4<1>;
+L_0x29f2060 .delay (10000,10000,10000) L_0x29f2060/d;
+L_0x29f21c0/d .functor NAND 1, L_0x29f2060, L_0x29f1f50, C4<1>, C4<1>;
+L_0x29f21c0 .delay (10000,10000,10000) L_0x29f21c0/d;
+L_0x29f22d0/d .functor NOT 1, L_0x29f21c0, C4<0>, C4<0>, C4<0>;
+L_0x29f22d0 .delay (10000,10000,10000) L_0x29f22d0/d;
+v0x28c0e30_0 .net "A", 0 0, L_0x29f2fe0; 1 drivers
+v0x28c0ed0_0 .net "AnandB", 0 0, L_0x29f2060; 1 drivers
+v0x28c0f70_0 .net "AnorB", 0 0, L_0x29ec040; 1 drivers
+v0x28c1020_0 .net "AorB", 0 0, L_0x29f1f50; 1 drivers
+v0x28c1100_0 .net "AxorB", 0 0, L_0x29f22d0; 1 drivers
+v0x28c11b0_0 .net "B", 0 0, L_0x29f1e20; 1 drivers
+v0x28c1270_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28c12f0_0 .net "OrNorXorOut", 0 0, L_0x29f2cd0; 1 drivers
+v0x28c1370_0 .net "XorNor", 0 0, L_0x29f2750; 1 drivers
+v0x28c1440_0 .net "nXor", 0 0, L_0x29f21c0; 1 drivers
+L_0x29f28d0 .part v0x2960210_0, 2, 1;
+L_0x29f2ea0 .part v0x2960210_0, 0, 1;
+S_0x28c08c0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28c0280;
+ .timescale -9 -12;
+L_0x29f2430/d .functor NOT 1, L_0x29f28d0, C4<0>, C4<0>, C4<0>;
+L_0x29f2430 .delay (10000,10000,10000) L_0x29f2430/d;
+L_0x29f24f0/d .functor AND 1, L_0x29f22d0, L_0x29f2430, C4<1>, C4<1>;
+L_0x29f24f0 .delay (20000,20000,20000) L_0x29f24f0/d;
+L_0x29f2600/d .functor AND 1, L_0x29ec040, L_0x29f28d0, C4<1>, C4<1>;
+L_0x29f2600 .delay (20000,20000,20000) L_0x29f2600/d;
+L_0x29f2750/d .functor OR 1, L_0x29f24f0, L_0x29f2600, C4<0>, C4<0>;
+L_0x29f2750 .delay (20000,20000,20000) L_0x29f2750/d;
+v0x28c09b0_0 .net "S", 0 0, L_0x29f28d0; 1 drivers
+v0x28c0a70_0 .alias "in0", 0 0, v0x28c1100_0;
+v0x28c0b10_0 .alias "in1", 0 0, v0x28c0f70_0;
+v0x28c0bb0_0 .net "nS", 0 0, L_0x29f2430; 1 drivers
+v0x28c0c30_0 .net "out0", 0 0, L_0x29f24f0; 1 drivers
+v0x28c0cd0_0 .net "out1", 0 0, L_0x29f2600; 1 drivers
+v0x28c0db0_0 .alias "outfinal", 0 0, v0x28c1370_0;
+S_0x28c0370 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28c0280;
+ .timescale -9 -12;
+L_0x29f2970/d .functor NOT 1, L_0x29f2ea0, C4<0>, C4<0>, C4<0>;
+L_0x29f2970 .delay (10000,10000,10000) L_0x29f2970/d;
+L_0x29f2a30/d .functor AND 1, L_0x29f2750, L_0x29f2970, C4<1>, C4<1>;
+L_0x29f2a30 .delay (20000,20000,20000) L_0x29f2a30/d;
+L_0x29f2b80/d .functor AND 1, L_0x29f1f50, L_0x29f2ea0, C4<1>, C4<1>;
+L_0x29f2b80 .delay (20000,20000,20000) L_0x29f2b80/d;
+L_0x29f2cd0/d .functor OR 1, L_0x29f2a30, L_0x29f2b80, C4<0>, C4<0>;
+L_0x29f2cd0 .delay (20000,20000,20000) L_0x29f2cd0/d;
+v0x28c0460_0 .net "S", 0 0, L_0x29f2ea0; 1 drivers
+v0x28c04e0_0 .alias "in0", 0 0, v0x28c1370_0;
+v0x28c0580_0 .alias "in1", 0 0, v0x28c1020_0;
+v0x28c0620_0 .net "nS", 0 0, L_0x29f2970; 1 drivers
+v0x28c06a0_0 .net "out0", 0 0, L_0x29f2a30; 1 drivers
+v0x28c0740_0 .net "out1", 0 0, L_0x29f2b80; 1 drivers
+v0x28c0820_0 .alias "outfinal", 0 0, v0x28c12f0_0;
+S_0x28bed80 .scope generate, "orbits[8]" "orbits[8]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28bea98 .param/l "i" 3 258, +C4<01000>;
+S_0x28beeb0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bed80;
+ .timescale -9 -12;
+L_0x29f3130/d .functor NOR 1, L_0x29f3080, L_0x29f4390, C4<0>, C4<0>;
+L_0x29f3130 .delay (10000,10000,10000) L_0x29f3130/d;
+L_0x29f3220/d .functor NOT 1, L_0x29f3130, C4<0>, C4<0>, C4<0>;
+L_0x29f3220 .delay (10000,10000,10000) L_0x29f3220/d;
+L_0x29f3350/d .functor NAND 1, L_0x29f3080, L_0x29f4390, C4<1>, C4<1>;
+L_0x29f3350 .delay (10000,10000,10000) L_0x29f3350/d;
+L_0x29f34b0/d .functor NAND 1, L_0x29f3350, L_0x29f3220, C4<1>, C4<1>;
+L_0x29f34b0 .delay (10000,10000,10000) L_0x29f34b0/d;
+L_0x29f35c0/d .functor NOT 1, L_0x29f34b0, C4<0>, C4<0>, C4<0>;
+L_0x29f35c0 .delay (10000,10000,10000) L_0x29f35c0/d;
+v0x28bfa60_0 .net "A", 0 0, L_0x29f3080; 1 drivers
+v0x28bfb00_0 .net "AnandB", 0 0, L_0x29f3350; 1 drivers
+v0x28bfba0_0 .net "AnorB", 0 0, L_0x29f3130; 1 drivers
+v0x28bfc50_0 .net "AorB", 0 0, L_0x29f3220; 1 drivers
+v0x28bfd30_0 .net "AxorB", 0 0, L_0x29f35c0; 1 drivers
+v0x28bfde0_0 .net "B", 0 0, L_0x29f4390; 1 drivers
+v0x28bfea0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28bff20_0 .net "OrNorXorOut", 0 0, L_0x29f3fc0; 1 drivers
+v0x28bffa0_0 .net "XorNor", 0 0, L_0x29f3a40; 1 drivers
+v0x28c0070_0 .net "nXor", 0 0, L_0x29f34b0; 1 drivers
+L_0x29f3bc0 .part v0x2960210_0, 2, 1;
+L_0x29f4190 .part v0x2960210_0, 0, 1;
+S_0x28bf4f0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28beeb0;
+ .timescale -9 -12;
+L_0x29f3720/d .functor NOT 1, L_0x29f3bc0, C4<0>, C4<0>, C4<0>;
+L_0x29f3720 .delay (10000,10000,10000) L_0x29f3720/d;
+L_0x29f37e0/d .functor AND 1, L_0x29f35c0, L_0x29f3720, C4<1>, C4<1>;
+L_0x29f37e0 .delay (20000,20000,20000) L_0x29f37e0/d;
+L_0x29f38f0/d .functor AND 1, L_0x29f3130, L_0x29f3bc0, C4<1>, C4<1>;
+L_0x29f38f0 .delay (20000,20000,20000) L_0x29f38f0/d;
+L_0x29f3a40/d .functor OR 1, L_0x29f37e0, L_0x29f38f0, C4<0>, C4<0>;
+L_0x29f3a40 .delay (20000,20000,20000) L_0x29f3a40/d;
+v0x28bf5e0_0 .net "S", 0 0, L_0x29f3bc0; 1 drivers
+v0x28bf6a0_0 .alias "in0", 0 0, v0x28bfd30_0;
+v0x28bf740_0 .alias "in1", 0 0, v0x28bfba0_0;
+v0x28bf7e0_0 .net "nS", 0 0, L_0x29f3720; 1 drivers
+v0x28bf860_0 .net "out0", 0 0, L_0x29f37e0; 1 drivers
+v0x28bf900_0 .net "out1", 0 0, L_0x29f38f0; 1 drivers
+v0x28bf9e0_0 .alias "outfinal", 0 0, v0x28bffa0_0;
+S_0x28befa0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28beeb0;
+ .timescale -9 -12;
+L_0x29f3c60/d .functor NOT 1, L_0x29f4190, C4<0>, C4<0>, C4<0>;
+L_0x29f3c60 .delay (10000,10000,10000) L_0x29f3c60/d;
+L_0x29f3d20/d .functor AND 1, L_0x29f3a40, L_0x29f3c60, C4<1>, C4<1>;
+L_0x29f3d20 .delay (20000,20000,20000) L_0x29f3d20/d;
+L_0x29f3e70/d .functor AND 1, L_0x29f3220, L_0x29f4190, C4<1>, C4<1>;
+L_0x29f3e70 .delay (20000,20000,20000) L_0x29f3e70/d;
+L_0x29f3fc0/d .functor OR 1, L_0x29f3d20, L_0x29f3e70, C4<0>, C4<0>;
+L_0x29f3fc0 .delay (20000,20000,20000) L_0x29f3fc0/d;
+v0x28bf090_0 .net "S", 0 0, L_0x29f4190; 1 drivers
+v0x28bf110_0 .alias "in0", 0 0, v0x28bffa0_0;
+v0x28bf1b0_0 .alias "in1", 0 0, v0x28bfc50_0;
+v0x28bf250_0 .net "nS", 0 0, L_0x29f3c60; 1 drivers
+v0x28bf2d0_0 .net "out0", 0 0, L_0x29f3d20; 1 drivers
+v0x28bf370_0 .net "out1", 0 0, L_0x29f3e70; 1 drivers
+v0x28bf450_0 .alias "outfinal", 0 0, v0x28bff20_0;
+S_0x28bd9b0 .scope generate, "orbits[9]" "orbits[9]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28bd6c8 .param/l "i" 3 258, +C4<01001>;
+S_0x28bdae0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bd9b0;
+ .timescale -9 -12;
+L_0x29f42d0/d .functor NOR 1, L_0x29f55e0, L_0x29f4430, C4<0>, C4<0>;
+L_0x29f42d0 .delay (10000,10000,10000) L_0x29f42d0/d;
+L_0x29f4550/d .functor NOT 1, L_0x29f42d0, C4<0>, C4<0>, C4<0>;
+L_0x29f4550 .delay (10000,10000,10000) L_0x29f4550/d;
+L_0x29f4660/d .functor NAND 1, L_0x29f55e0, L_0x29f4430, C4<1>, C4<1>;
+L_0x29f4660 .delay (10000,10000,10000) L_0x29f4660/d;
+L_0x29f47c0/d .functor NAND 1, L_0x29f4660, L_0x29f4550, C4<1>, C4<1>;
+L_0x29f47c0 .delay (10000,10000,10000) L_0x29f47c0/d;
+L_0x29f48d0/d .functor NOT 1, L_0x29f47c0, C4<0>, C4<0>, C4<0>;
+L_0x29f48d0 .delay (10000,10000,10000) L_0x29f48d0/d;
+v0x28be690_0 .net "A", 0 0, L_0x29f55e0; 1 drivers
+v0x28be730_0 .net "AnandB", 0 0, L_0x29f4660; 1 drivers
+v0x28be7d0_0 .net "AnorB", 0 0, L_0x29f42d0; 1 drivers
+v0x28be880_0 .net "AorB", 0 0, L_0x29f4550; 1 drivers
+v0x28be960_0 .net "AxorB", 0 0, L_0x29f48d0; 1 drivers
+v0x28bea10_0 .net "B", 0 0, L_0x29f4430; 1 drivers
+v0x28bead0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28beb50_0 .net "OrNorXorOut", 0 0, L_0x29f52d0; 1 drivers
+v0x28bebd0_0 .net "XorNor", 0 0, L_0x29f4d50; 1 drivers
+v0x28beca0_0 .net "nXor", 0 0, L_0x29f47c0; 1 drivers
+L_0x29f4ed0 .part v0x2960210_0, 2, 1;
+L_0x29f54a0 .part v0x2960210_0, 0, 1;
+S_0x28be120 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28bdae0;
+ .timescale -9 -12;
+L_0x29f4a30/d .functor NOT 1, L_0x29f4ed0, C4<0>, C4<0>, C4<0>;
+L_0x29f4a30 .delay (10000,10000,10000) L_0x29f4a30/d;
+L_0x29f4af0/d .functor AND 1, L_0x29f48d0, L_0x29f4a30, C4<1>, C4<1>;
+L_0x29f4af0 .delay (20000,20000,20000) L_0x29f4af0/d;
+L_0x29f4c00/d .functor AND 1, L_0x29f42d0, L_0x29f4ed0, C4<1>, C4<1>;
+L_0x29f4c00 .delay (20000,20000,20000) L_0x29f4c00/d;
+L_0x29f4d50/d .functor OR 1, L_0x29f4af0, L_0x29f4c00, C4<0>, C4<0>;
+L_0x29f4d50 .delay (20000,20000,20000) L_0x29f4d50/d;
+v0x28be210_0 .net "S", 0 0, L_0x29f4ed0; 1 drivers
+v0x28be2d0_0 .alias "in0", 0 0, v0x28be960_0;
+v0x28be370_0 .alias "in1", 0 0, v0x28be7d0_0;
+v0x28be410_0 .net "nS", 0 0, L_0x29f4a30; 1 drivers
+v0x28be490_0 .net "out0", 0 0, L_0x29f4af0; 1 drivers
+v0x28be530_0 .net "out1", 0 0, L_0x29f4c00; 1 drivers
+v0x28be610_0 .alias "outfinal", 0 0, v0x28bebd0_0;
+S_0x28bdbd0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28bdae0;
+ .timescale -9 -12;
+L_0x29f4f70/d .functor NOT 1, L_0x29f54a0, C4<0>, C4<0>, C4<0>;
+L_0x29f4f70 .delay (10000,10000,10000) L_0x29f4f70/d;
+L_0x29f5030/d .functor AND 1, L_0x29f4d50, L_0x29f4f70, C4<1>, C4<1>;
+L_0x29f5030 .delay (20000,20000,20000) L_0x29f5030/d;
+L_0x29f5180/d .functor AND 1, L_0x29f4550, L_0x29f54a0, C4<1>, C4<1>;
+L_0x29f5180 .delay (20000,20000,20000) L_0x29f5180/d;
+L_0x29f52d0/d .functor OR 1, L_0x29f5030, L_0x29f5180, C4<0>, C4<0>;
+L_0x29f52d0 .delay (20000,20000,20000) L_0x29f52d0/d;
+v0x28bdcc0_0 .net "S", 0 0, L_0x29f54a0; 1 drivers
+v0x28bdd40_0 .alias "in0", 0 0, v0x28bebd0_0;
+v0x28bdde0_0 .alias "in1", 0 0, v0x28be880_0;
+v0x28bde80_0 .net "nS", 0 0, L_0x29f4f70; 1 drivers
+v0x28bdf00_0 .net "out0", 0 0, L_0x29f5030; 1 drivers
+v0x28bdfa0_0 .net "out1", 0 0, L_0x29f5180; 1 drivers
+v0x28be080_0 .alias "outfinal", 0 0, v0x28beb50_0;
+S_0x28bc5e0 .scope generate, "orbits[10]" "orbits[10]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28bc2f8 .param/l "i" 3 258, +C4<01010>;
+S_0x28bc710 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bc5e0;
+ .timescale -9 -12;
+L_0x29f5760/d .functor NOR 1, L_0x29f5680, L_0x29f68b0, C4<0>, C4<0>;
+L_0x29f5760 .delay (10000,10000,10000) L_0x29f5760/d;
+L_0x29f5850/d .functor NOT 1, L_0x29f5760, C4<0>, C4<0>, C4<0>;
+L_0x29f5850 .delay (10000,10000,10000) L_0x29f5850/d;
+L_0x29f5960/d .functor NAND 1, L_0x29f5680, L_0x29f68b0, C4<1>, C4<1>;
+L_0x29f5960 .delay (10000,10000,10000) L_0x29f5960/d;
+L_0x29f5ac0/d .functor NAND 1, L_0x29f5960, L_0x29f5850, C4<1>, C4<1>;
+L_0x29f5ac0 .delay (10000,10000,10000) L_0x29f5ac0/d;
+L_0x29f5bd0/d .functor NOT 1, L_0x29f5ac0, C4<0>, C4<0>, C4<0>;
+L_0x29f5bd0 .delay (10000,10000,10000) L_0x29f5bd0/d;
+v0x28bd2c0_0 .net "A", 0 0, L_0x29f5680; 1 drivers
+v0x28bd360_0 .net "AnandB", 0 0, L_0x29f5960; 1 drivers
+v0x28bd400_0 .net "AnorB", 0 0, L_0x29f5760; 1 drivers
+v0x28bd4b0_0 .net "AorB", 0 0, L_0x29f5850; 1 drivers
+v0x28bd590_0 .net "AxorB", 0 0, L_0x29f5bd0; 1 drivers
+v0x28bd640_0 .net "B", 0 0, L_0x29f68b0; 1 drivers
+v0x28bd700_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28bd780_0 .net "OrNorXorOut", 0 0, L_0x29f64f0; 1 drivers
+v0x28bd800_0 .net "XorNor", 0 0, L_0x29f6010; 1 drivers
+v0x28bd8d0_0 .net "nXor", 0 0, L_0x29f5ac0; 1 drivers
+L_0x29f6150 .part v0x2960210_0, 2, 1;
+L_0x29f6680 .part v0x2960210_0, 0, 1;
+S_0x28bcd50 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28bc710;
+ .timescale -9 -12;
+L_0x29f5d30/d .functor NOT 1, L_0x29f6150, C4<0>, C4<0>, C4<0>;
+L_0x29f5d30 .delay (10000,10000,10000) L_0x29f5d30/d;
+L_0x29f5df0/d .functor AND 1, L_0x29f5bd0, L_0x29f5d30, C4<1>, C4<1>;
+L_0x29f5df0 .delay (20000,20000,20000) L_0x29f5df0/d;
+L_0x29f5f00/d .functor AND 1, L_0x29f5760, L_0x29f6150, C4<1>, C4<1>;
+L_0x29f5f00 .delay (20000,20000,20000) L_0x29f5f00/d;
+L_0x29f6010/d .functor OR 1, L_0x29f5df0, L_0x29f5f00, C4<0>, C4<0>;
+L_0x29f6010 .delay (20000,20000,20000) L_0x29f6010/d;
+v0x28bce40_0 .net "S", 0 0, L_0x29f6150; 1 drivers
+v0x28bcf00_0 .alias "in0", 0 0, v0x28bd590_0;
+v0x28bcfa0_0 .alias "in1", 0 0, v0x28bd400_0;
+v0x28bd040_0 .net "nS", 0 0, L_0x29f5d30; 1 drivers
+v0x28bd0c0_0 .net "out0", 0 0, L_0x29f5df0; 1 drivers
+v0x28bd160_0 .net "out1", 0 0, L_0x29f5f00; 1 drivers
+v0x28bd240_0 .alias "outfinal", 0 0, v0x28bd800_0;
+S_0x28bc800 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28bc710;
+ .timescale -9 -12;
+L_0x29f61f0/d .functor NOT 1, L_0x29f6680, C4<0>, C4<0>, C4<0>;
+L_0x29f61f0 .delay (10000,10000,10000) L_0x29f61f0/d;
+L_0x29f6290/d .functor AND 1, L_0x29f6010, L_0x29f61f0, C4<1>, C4<1>;
+L_0x29f6290 .delay (20000,20000,20000) L_0x29f6290/d;
+L_0x29f63c0/d .functor AND 1, L_0x29f5850, L_0x29f6680, C4<1>, C4<1>;
+L_0x29f63c0 .delay (20000,20000,20000) L_0x29f63c0/d;
+L_0x29f64f0/d .functor OR 1, L_0x29f6290, L_0x29f63c0, C4<0>, C4<0>;
+L_0x29f64f0 .delay (20000,20000,20000) L_0x29f64f0/d;
+v0x28bc8f0_0 .net "S", 0 0, L_0x29f6680; 1 drivers
+v0x28bc970_0 .alias "in0", 0 0, v0x28bd800_0;
+v0x28bca10_0 .alias "in1", 0 0, v0x28bd4b0_0;
+v0x28bcab0_0 .net "nS", 0 0, L_0x29f61f0; 1 drivers
+v0x28bcb30_0 .net "out0", 0 0, L_0x29f6290; 1 drivers
+v0x28bcbd0_0 .net "out1", 0 0, L_0x29f63c0; 1 drivers
+v0x28bccb0_0 .alias "outfinal", 0 0, v0x28bd780_0;
+S_0x28bb210 .scope generate, "orbits[11]" "orbits[11]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28baf28 .param/l "i" 3 258, +C4<01011>;
+S_0x28bb340 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28bb210;
+ .timescale -9 -12;
+L_0x29f67c0/d .functor NOR 1, L_0x29f7980, L_0x29f6950, C4<0>, C4<0>;
+L_0x29f67c0 .delay (10000,10000,10000) L_0x29f67c0/d;
+L_0x29f6a50/d .functor NOT 1, L_0x29f67c0, C4<0>, C4<0>, C4<0>;
+L_0x29f6a50 .delay (10000,10000,10000) L_0x29f6a50/d;
+L_0x29f6b00/d .functor NAND 1, L_0x29f7980, L_0x29f6950, C4<1>, C4<1>;
+L_0x29f6b00 .delay (10000,10000,10000) L_0x29f6b00/d;
+L_0x29f6c40/d .functor NAND 1, L_0x29f6b00, L_0x29f6a50, C4<1>, C4<1>;
+L_0x29f6c40 .delay (10000,10000,10000) L_0x29f6c40/d;
+L_0x29f6d30/d .functor NOT 1, L_0x29f6c40, C4<0>, C4<0>, C4<0>;
+L_0x29f6d30 .delay (10000,10000,10000) L_0x29f6d30/d;
+v0x28bbef0_0 .net "A", 0 0, L_0x29f7980; 1 drivers
+v0x28bbf90_0 .net "AnandB", 0 0, L_0x29f6b00; 1 drivers
+v0x28bc030_0 .net "AnorB", 0 0, L_0x29f67c0; 1 drivers
+v0x28bc0e0_0 .net "AorB", 0 0, L_0x29f6a50; 1 drivers
+v0x28bc1c0_0 .net "AxorB", 0 0, L_0x29f6d30; 1 drivers
+v0x28bc270_0 .net "B", 0 0, L_0x29f6950; 1 drivers
+v0x28bc330_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28bc3b0_0 .net "OrNorXorOut", 0 0, L_0x29f7670; 1 drivers
+v0x28bc430_0 .net "XorNor", 0 0, L_0x29f7130; 1 drivers
+v0x28bc500_0 .net "nXor", 0 0, L_0x29f6c40; 1 drivers
+L_0x29f7270 .part v0x2960210_0, 2, 1;
+L_0x29f7840 .part v0x2960210_0, 0, 1;
+S_0x28bb980 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28bb340;
+ .timescale -9 -12;
+L_0x29f6e70/d .functor NOT 1, L_0x29f7270, C4<0>, C4<0>, C4<0>;
+L_0x29f6e70 .delay (10000,10000,10000) L_0x29f6e70/d;
+L_0x29f6f10/d .functor AND 1, L_0x29f6d30, L_0x29f6e70, C4<1>, C4<1>;
+L_0x29f6f10 .delay (20000,20000,20000) L_0x29f6f10/d;
+L_0x29f7000/d .functor AND 1, L_0x29f67c0, L_0x29f7270, C4<1>, C4<1>;
+L_0x29f7000 .delay (20000,20000,20000) L_0x29f7000/d;
+L_0x29f7130/d .functor OR 1, L_0x29f6f10, L_0x29f7000, C4<0>, C4<0>;
+L_0x29f7130 .delay (20000,20000,20000) L_0x29f7130/d;
+v0x28bba70_0 .net "S", 0 0, L_0x29f7270; 1 drivers
+v0x28bbb30_0 .alias "in0", 0 0, v0x28bc1c0_0;
+v0x28bbbd0_0 .alias "in1", 0 0, v0x28bc030_0;
+v0x28bbc70_0 .net "nS", 0 0, L_0x29f6e70; 1 drivers
+v0x28bbcf0_0 .net "out0", 0 0, L_0x29f6f10; 1 drivers
+v0x28bbd90_0 .net "out1", 0 0, L_0x29f7000; 1 drivers
+v0x28bbe70_0 .alias "outfinal", 0 0, v0x28bc430_0;
+S_0x28bb430 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28bb340;
+ .timescale -9 -12;
+L_0x29f7310/d .functor NOT 1, L_0x29f7840, C4<0>, C4<0>, C4<0>;
+L_0x29f7310 .delay (10000,10000,10000) L_0x29f7310/d;
+L_0x29f73d0/d .functor AND 1, L_0x29f7130, L_0x29f7310, C4<1>, C4<1>;
+L_0x29f73d0 .delay (20000,20000,20000) L_0x29f73d0/d;
+L_0x29f7520/d .functor AND 1, L_0x29f6a50, L_0x29f7840, C4<1>, C4<1>;
+L_0x29f7520 .delay (20000,20000,20000) L_0x29f7520/d;
+L_0x29f7670/d .functor OR 1, L_0x29f73d0, L_0x29f7520, C4<0>, C4<0>;
+L_0x29f7670 .delay (20000,20000,20000) L_0x29f7670/d;
+v0x28bb520_0 .net "S", 0 0, L_0x29f7840; 1 drivers
+v0x28bb5a0_0 .alias "in0", 0 0, v0x28bc430_0;
+v0x28bb640_0 .alias "in1", 0 0, v0x28bc0e0_0;
+v0x28bb6e0_0 .net "nS", 0 0, L_0x29f7310; 1 drivers
+v0x28bb760_0 .net "out0", 0 0, L_0x29f73d0; 1 drivers
+v0x28bb800_0 .net "out1", 0 0, L_0x29f7520; 1 drivers
+v0x28bb8e0_0 .alias "outfinal", 0 0, v0x28bc3b0_0;
+S_0x28b9e40 .scope generate, "orbits[12]" "orbits[12]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b9b58 .param/l "i" 3 258, +C4<01100>;
+S_0x28b9f70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b9e40;
+ .timescale -9 -12;
+L_0x29f69f0/d .functor NOR 1, L_0x29f7a20, L_0x29f8d90, C4<0>, C4<0>;
+L_0x29f69f0 .delay (10000,10000,10000) L_0x29f69f0/d;
+L_0x29f7bc0/d .functor NOT 1, L_0x29f69f0, C4<0>, C4<0>, C4<0>;
+L_0x29f7bc0 .delay (10000,10000,10000) L_0x29f7bc0/d;
+L_0x29f7cf0/d .functor NAND 1, L_0x29f7a20, L_0x29f8d90, C4<1>, C4<1>;
+L_0x29f7cf0 .delay (10000,10000,10000) L_0x29f7cf0/d;
+L_0x29f7e50/d .functor NAND 1, L_0x29f7cf0, L_0x29f7bc0, C4<1>, C4<1>;
+L_0x29f7e50 .delay (10000,10000,10000) L_0x29f7e50/d;
+L_0x29f7f60/d .functor NOT 1, L_0x29f7e50, C4<0>, C4<0>, C4<0>;
+L_0x29f7f60 .delay (10000,10000,10000) L_0x29f7f60/d;
+v0x28bab20_0 .net "A", 0 0, L_0x29f7a20; 1 drivers
+v0x28babc0_0 .net "AnandB", 0 0, L_0x29f7cf0; 1 drivers
+v0x28bac60_0 .net "AnorB", 0 0, L_0x29f69f0; 1 drivers
+v0x28bad10_0 .net "AorB", 0 0, L_0x29f7bc0; 1 drivers
+v0x28badf0_0 .net "AxorB", 0 0, L_0x29f7f60; 1 drivers
+v0x28baea0_0 .net "B", 0 0, L_0x29f8d90; 1 drivers
+v0x28baf60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28bafe0_0 .net "OrNorXorOut", 0 0, L_0x29f8960; 1 drivers
+v0x28bb060_0 .net "XorNor", 0 0, L_0x29f83e0; 1 drivers
+v0x28bb130_0 .net "nXor", 0 0, L_0x29f7e50; 1 drivers
+L_0x29f8560 .part v0x2960210_0, 2, 1;
+L_0x29f8b30 .part v0x2960210_0, 0, 1;
+S_0x28ba5b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b9f70;
+ .timescale -9 -12;
+L_0x29f80c0/d .functor NOT 1, L_0x29f8560, C4<0>, C4<0>, C4<0>;
+L_0x29f80c0 .delay (10000,10000,10000) L_0x29f80c0/d;
+L_0x29f8180/d .functor AND 1, L_0x29f7f60, L_0x29f80c0, C4<1>, C4<1>;
+L_0x29f8180 .delay (20000,20000,20000) L_0x29f8180/d;
+L_0x29f8290/d .functor AND 1, L_0x29f69f0, L_0x29f8560, C4<1>, C4<1>;
+L_0x29f8290 .delay (20000,20000,20000) L_0x29f8290/d;
+L_0x29f83e0/d .functor OR 1, L_0x29f8180, L_0x29f8290, C4<0>, C4<0>;
+L_0x29f83e0 .delay (20000,20000,20000) L_0x29f83e0/d;
+v0x28ba6a0_0 .net "S", 0 0, L_0x29f8560; 1 drivers
+v0x28ba760_0 .alias "in0", 0 0, v0x28badf0_0;
+v0x28ba800_0 .alias "in1", 0 0, v0x28bac60_0;
+v0x28ba8a0_0 .net "nS", 0 0, L_0x29f80c0; 1 drivers
+v0x28ba920_0 .net "out0", 0 0, L_0x29f8180; 1 drivers
+v0x28ba9c0_0 .net "out1", 0 0, L_0x29f8290; 1 drivers
+v0x28baaa0_0 .alias "outfinal", 0 0, v0x28bb060_0;
+S_0x28ba060 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b9f70;
+ .timescale -9 -12;
+L_0x29f8600/d .functor NOT 1, L_0x29f8b30, C4<0>, C4<0>, C4<0>;
+L_0x29f8600 .delay (10000,10000,10000) L_0x29f8600/d;
+L_0x29f86c0/d .functor AND 1, L_0x29f83e0, L_0x29f8600, C4<1>, C4<1>;
+L_0x29f86c0 .delay (20000,20000,20000) L_0x29f86c0/d;
+L_0x29f8810/d .functor AND 1, L_0x29f7bc0, L_0x29f8b30, C4<1>, C4<1>;
+L_0x29f8810 .delay (20000,20000,20000) L_0x29f8810/d;
+L_0x29f8960/d .functor OR 1, L_0x29f86c0, L_0x29f8810, C4<0>, C4<0>;
+L_0x29f8960 .delay (20000,20000,20000) L_0x29f8960/d;
+v0x28ba150_0 .net "S", 0 0, L_0x29f8b30; 1 drivers
+v0x28ba1d0_0 .alias "in0", 0 0, v0x28bb060_0;
+v0x28ba270_0 .alias "in1", 0 0, v0x28bad10_0;
+v0x28ba310_0 .net "nS", 0 0, L_0x29f8600; 1 drivers
+v0x28ba390_0 .net "out0", 0 0, L_0x29f86c0; 1 drivers
+v0x28ba430_0 .net "out1", 0 0, L_0x29f8810; 1 drivers
+v0x28ba510_0 .alias "outfinal", 0 0, v0x28bafe0_0;
+S_0x28b8a70 .scope generate, "orbits[13]" "orbits[13]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b8788 .param/l "i" 3 258, +C4<01101>;
+S_0x28b8ba0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b8a70;
+ .timescale -9 -12;
+L_0x29f7ac0/d .functor NOR 1, L_0x29f08f0, L_0x29f8e30, C4<0>, C4<0>;
+L_0x29f7ac0 .delay (10000,10000,10000) L_0x29f7ac0/d;
+L_0x29f8d00/d .functor NOT 1, L_0x29f7ac0, C4<0>, C4<0>, C4<0>;
+L_0x29f8d00 .delay (10000,10000,10000) L_0x29f8d00/d;
+L_0x29f9010/d .functor NAND 1, L_0x29f08f0, L_0x29f8e30, C4<1>, C4<1>;
+L_0x29f9010 .delay (10000,10000,10000) L_0x29f9010/d;
+L_0x29f9170/d .functor NAND 1, L_0x29f9010, L_0x29f8d00, C4<1>, C4<1>;
+L_0x29f9170 .delay (10000,10000,10000) L_0x29f9170/d;
+L_0x29f9280/d .functor NOT 1, L_0x29f9170, C4<0>, C4<0>, C4<0>;
+L_0x29f9280 .delay (10000,10000,10000) L_0x29f9280/d;
+v0x28b9750_0 .net "A", 0 0, L_0x29f08f0; 1 drivers
+v0x28b97f0_0 .net "AnandB", 0 0, L_0x29f9010; 1 drivers
+v0x28b9890_0 .net "AnorB", 0 0, L_0x29f7ac0; 1 drivers
+v0x28b9940_0 .net "AorB", 0 0, L_0x29f8d00; 1 drivers
+v0x28b9a20_0 .net "AxorB", 0 0, L_0x29f9280; 1 drivers
+v0x28b9ad0_0 .net "B", 0 0, L_0x29f8e30; 1 drivers
+v0x28b9b90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b9c10_0 .net "OrNorXorOut", 0 0, L_0x29f9c80; 1 drivers
+v0x28b9c90_0 .net "XorNor", 0 0, L_0x29f9700; 1 drivers
+v0x28b9d60_0 .net "nXor", 0 0, L_0x29f9170; 1 drivers
+L_0x29f9880 .part v0x2960210_0, 2, 1;
+L_0x29f9e50 .part v0x2960210_0, 0, 1;
+S_0x28b91e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b8ba0;
+ .timescale -9 -12;
+L_0x29f93e0/d .functor NOT 1, L_0x29f9880, C4<0>, C4<0>, C4<0>;
+L_0x29f93e0 .delay (10000,10000,10000) L_0x29f93e0/d;
+L_0x29f94a0/d .functor AND 1, L_0x29f9280, L_0x29f93e0, C4<1>, C4<1>;
+L_0x29f94a0 .delay (20000,20000,20000) L_0x29f94a0/d;
+L_0x29f95b0/d .functor AND 1, L_0x29f7ac0, L_0x29f9880, C4<1>, C4<1>;
+L_0x29f95b0 .delay (20000,20000,20000) L_0x29f95b0/d;
+L_0x29f9700/d .functor OR 1, L_0x29f94a0, L_0x29f95b0, C4<0>, C4<0>;
+L_0x29f9700 .delay (20000,20000,20000) L_0x29f9700/d;
+v0x28b92d0_0 .net "S", 0 0, L_0x29f9880; 1 drivers
+v0x28b9390_0 .alias "in0", 0 0, v0x28b9a20_0;
+v0x28b9430_0 .alias "in1", 0 0, v0x28b9890_0;
+v0x28b94d0_0 .net "nS", 0 0, L_0x29f93e0; 1 drivers
+v0x28b9550_0 .net "out0", 0 0, L_0x29f94a0; 1 drivers
+v0x28b95f0_0 .net "out1", 0 0, L_0x29f95b0; 1 drivers
+v0x28b96d0_0 .alias "outfinal", 0 0, v0x28b9c90_0;
+S_0x28b8c90 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b8ba0;
+ .timescale -9 -12;
+L_0x29f9920/d .functor NOT 1, L_0x29f9e50, C4<0>, C4<0>, C4<0>;
+L_0x29f9920 .delay (10000,10000,10000) L_0x29f9920/d;
+L_0x29f99e0/d .functor AND 1, L_0x29f9700, L_0x29f9920, C4<1>, C4<1>;
+L_0x29f99e0 .delay (20000,20000,20000) L_0x29f99e0/d;
+L_0x29f9b30/d .functor AND 1, L_0x29f8d00, L_0x29f9e50, C4<1>, C4<1>;
+L_0x29f9b30 .delay (20000,20000,20000) L_0x29f9b30/d;
+L_0x29f9c80/d .functor OR 1, L_0x29f99e0, L_0x29f9b30, C4<0>, C4<0>;
+L_0x29f9c80 .delay (20000,20000,20000) L_0x29f9c80/d;
+v0x28b8d80_0 .net "S", 0 0, L_0x29f9e50; 1 drivers
+v0x28b8e00_0 .alias "in0", 0 0, v0x28b9c90_0;
+v0x28b8ea0_0 .alias "in1", 0 0, v0x28b9940_0;
+v0x28b8f40_0 .net "nS", 0 0, L_0x29f9920; 1 drivers
+v0x28b8fc0_0 .net "out0", 0 0, L_0x29f99e0; 1 drivers
+v0x28b9060_0 .net "out1", 0 0, L_0x29f9b30; 1 drivers
+v0x28b9140_0 .alias "outfinal", 0 0, v0x28b9c10_0;
+S_0x28b76a0 .scope generate, "orbits[14]" "orbits[14]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b73b8 .param/l "i" 3 258, +C4<01110>;
+S_0x28b77d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b76a0;
+ .timescale -9 -12;
+L_0x29f8ed0/d .functor NOR 1, L_0x29fa1a0, L_0x29fa240, C4<0>, C4<0>;
+L_0x29f8ed0 .delay (10000,10000,10000) L_0x29f8ed0/d;
+L_0x29fa330/d .functor NOT 1, L_0x29f8ed0, C4<0>, C4<0>, C4<0>;
+L_0x29fa330 .delay (10000,10000,10000) L_0x29fa330/d;
+L_0x29fa420/d .functor NAND 1, L_0x29fa1a0, L_0x29fa240, C4<1>, C4<1>;
+L_0x29fa420 .delay (10000,10000,10000) L_0x29fa420/d;
+L_0x29fa580/d .functor NAND 1, L_0x29fa420, L_0x29fa330, C4<1>, C4<1>;
+L_0x29fa580 .delay (10000,10000,10000) L_0x29fa580/d;
+L_0x29fa690/d .functor NOT 1, L_0x29fa580, C4<0>, C4<0>, C4<0>;
+L_0x29fa690 .delay (10000,10000,10000) L_0x29fa690/d;
+v0x28b8380_0 .net "A", 0 0, L_0x29fa1a0; 1 drivers
+v0x28b8420_0 .net "AnandB", 0 0, L_0x29fa420; 1 drivers
+v0x28b84c0_0 .net "AnorB", 0 0, L_0x29f8ed0; 1 drivers
+v0x28b8570_0 .net "AorB", 0 0, L_0x29fa330; 1 drivers
+v0x28b8650_0 .net "AxorB", 0 0, L_0x29fa690; 1 drivers
+v0x28b8700_0 .net "B", 0 0, L_0x29fa240; 1 drivers
+v0x28b87c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b8840_0 .net "OrNorXorOut", 0 0, L_0x29fb090; 1 drivers
+v0x28b88c0_0 .net "XorNor", 0 0, L_0x29fab10; 1 drivers
+v0x28b8990_0 .net "nXor", 0 0, L_0x29fa580; 1 drivers
+L_0x29fac90 .part v0x2960210_0, 2, 1;
+L_0x29fb260 .part v0x2960210_0, 0, 1;
+S_0x28b7e10 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b77d0;
+ .timescale -9 -12;
+L_0x29fa7f0/d .functor NOT 1, L_0x29fac90, C4<0>, C4<0>, C4<0>;
+L_0x29fa7f0 .delay (10000,10000,10000) L_0x29fa7f0/d;
+L_0x29fa8b0/d .functor AND 1, L_0x29fa690, L_0x29fa7f0, C4<1>, C4<1>;
+L_0x29fa8b0 .delay (20000,20000,20000) L_0x29fa8b0/d;
+L_0x29fa9c0/d .functor AND 1, L_0x29f8ed0, L_0x29fac90, C4<1>, C4<1>;
+L_0x29fa9c0 .delay (20000,20000,20000) L_0x29fa9c0/d;
+L_0x29fab10/d .functor OR 1, L_0x29fa8b0, L_0x29fa9c0, C4<0>, C4<0>;
+L_0x29fab10 .delay (20000,20000,20000) L_0x29fab10/d;
+v0x28b7f00_0 .net "S", 0 0, L_0x29fac90; 1 drivers
+v0x28b7fc0_0 .alias "in0", 0 0, v0x28b8650_0;
+v0x28b8060_0 .alias "in1", 0 0, v0x28b84c0_0;
+v0x28b8100_0 .net "nS", 0 0, L_0x29fa7f0; 1 drivers
+v0x28b8180_0 .net "out0", 0 0, L_0x29fa8b0; 1 drivers
+v0x28b8220_0 .net "out1", 0 0, L_0x29fa9c0; 1 drivers
+v0x28b8300_0 .alias "outfinal", 0 0, v0x28b88c0_0;
+S_0x28b78c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b77d0;
+ .timescale -9 -12;
+L_0x29fad30/d .functor NOT 1, L_0x29fb260, C4<0>, C4<0>, C4<0>;
+L_0x29fad30 .delay (10000,10000,10000) L_0x29fad30/d;
+L_0x29fadf0/d .functor AND 1, L_0x29fab10, L_0x29fad30, C4<1>, C4<1>;
+L_0x29fadf0 .delay (20000,20000,20000) L_0x29fadf0/d;
+L_0x29faf40/d .functor AND 1, L_0x29fa330, L_0x29fb260, C4<1>, C4<1>;
+L_0x29faf40 .delay (20000,20000,20000) L_0x29faf40/d;
+L_0x29fb090/d .functor OR 1, L_0x29fadf0, L_0x29faf40, C4<0>, C4<0>;
+L_0x29fb090 .delay (20000,20000,20000) L_0x29fb090/d;
+v0x28b79b0_0 .net "S", 0 0, L_0x29fb260; 1 drivers
+v0x28b7a30_0 .alias "in0", 0 0, v0x28b88c0_0;
+v0x28b7ad0_0 .alias "in1", 0 0, v0x28b8570_0;
+v0x28b7b70_0 .net "nS", 0 0, L_0x29fad30; 1 drivers
+v0x28b7bf0_0 .net "out0", 0 0, L_0x29fadf0; 1 drivers
+v0x28b7c90_0 .net "out1", 0 0, L_0x29faf40; 1 drivers
+v0x28b7d70_0 .alias "outfinal", 0 0, v0x28b8840_0;
+S_0x28b62d0 .scope generate, "orbits[15]" "orbits[15]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b5fe8 .param/l "i" 3 258, +C4<01111>;
+S_0x28b6400 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b62d0;
+ .timescale -9 -12;
+L_0x29fb500/d .functor NOR 1, L_0x29fc6a0, L_0x29fb3a0, C4<0>, C4<0>;
+L_0x29fb500 .delay (10000,10000,10000) L_0x29fb500/d;
+L_0x29fb5f0/d .functor NOT 1, L_0x29fb500, C4<0>, C4<0>, C4<0>;
+L_0x29fb5f0 .delay (10000,10000,10000) L_0x29fb5f0/d;
+L_0x29fb720/d .functor NAND 1, L_0x29fc6a0, L_0x29fb3a0, C4<1>, C4<1>;
+L_0x29fb720 .delay (10000,10000,10000) L_0x29fb720/d;
+L_0x29fb880/d .functor NAND 1, L_0x29fb720, L_0x29fb5f0, C4<1>, C4<1>;
+L_0x29fb880 .delay (10000,10000,10000) L_0x29fb880/d;
+L_0x29fb990/d .functor NOT 1, L_0x29fb880, C4<0>, C4<0>, C4<0>;
+L_0x29fb990 .delay (10000,10000,10000) L_0x29fb990/d;
+v0x28b6fb0_0 .net "A", 0 0, L_0x29fc6a0; 1 drivers
+v0x28b7050_0 .net "AnandB", 0 0, L_0x29fb720; 1 drivers
+v0x28b70f0_0 .net "AnorB", 0 0, L_0x29fb500; 1 drivers
+v0x28b71a0_0 .net "AorB", 0 0, L_0x29fb5f0; 1 drivers
+v0x28b7280_0 .net "AxorB", 0 0, L_0x29fb990; 1 drivers
+v0x28b7330_0 .net "B", 0 0, L_0x29fb3a0; 1 drivers
+v0x28b73f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b7470_0 .net "OrNorXorOut", 0 0, L_0x29fc390; 1 drivers
+v0x28b74f0_0 .net "XorNor", 0 0, L_0x29fbe10; 1 drivers
+v0x28b75c0_0 .net "nXor", 0 0, L_0x29fb880; 1 drivers
+L_0x29fbf90 .part v0x2960210_0, 2, 1;
+L_0x29fc560 .part v0x2960210_0, 0, 1;
+S_0x28b6a40 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b6400;
+ .timescale -9 -12;
+L_0x29fbaf0/d .functor NOT 1, L_0x29fbf90, C4<0>, C4<0>, C4<0>;
+L_0x29fbaf0 .delay (10000,10000,10000) L_0x29fbaf0/d;
+L_0x29fbbb0/d .functor AND 1, L_0x29fb990, L_0x29fbaf0, C4<1>, C4<1>;
+L_0x29fbbb0 .delay (20000,20000,20000) L_0x29fbbb0/d;
+L_0x29fbcc0/d .functor AND 1, L_0x29fb500, L_0x29fbf90, C4<1>, C4<1>;
+L_0x29fbcc0 .delay (20000,20000,20000) L_0x29fbcc0/d;
+L_0x29fbe10/d .functor OR 1, L_0x29fbbb0, L_0x29fbcc0, C4<0>, C4<0>;
+L_0x29fbe10 .delay (20000,20000,20000) L_0x29fbe10/d;
+v0x28b6b30_0 .net "S", 0 0, L_0x29fbf90; 1 drivers
+v0x28b6bf0_0 .alias "in0", 0 0, v0x28b7280_0;
+v0x28b6c90_0 .alias "in1", 0 0, v0x28b70f0_0;
+v0x28b6d30_0 .net "nS", 0 0, L_0x29fbaf0; 1 drivers
+v0x28b6db0_0 .net "out0", 0 0, L_0x29fbbb0; 1 drivers
+v0x28b6e50_0 .net "out1", 0 0, L_0x29fbcc0; 1 drivers
+v0x28b6f30_0 .alias "outfinal", 0 0, v0x28b74f0_0;
+S_0x28b64f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b6400;
+ .timescale -9 -12;
+L_0x29fc030/d .functor NOT 1, L_0x29fc560, C4<0>, C4<0>, C4<0>;
+L_0x29fc030 .delay (10000,10000,10000) L_0x29fc030/d;
+L_0x29fc0f0/d .functor AND 1, L_0x29fbe10, L_0x29fc030, C4<1>, C4<1>;
+L_0x29fc0f0 .delay (20000,20000,20000) L_0x29fc0f0/d;
+L_0x29fc240/d .functor AND 1, L_0x29fb5f0, L_0x29fc560, C4<1>, C4<1>;
+L_0x29fc240 .delay (20000,20000,20000) L_0x29fc240/d;
+L_0x29fc390/d .functor OR 1, L_0x29fc0f0, L_0x29fc240, C4<0>, C4<0>;
+L_0x29fc390 .delay (20000,20000,20000) L_0x29fc390/d;
+v0x28b65e0_0 .net "S", 0 0, L_0x29fc560; 1 drivers
+v0x28b6660_0 .alias "in0", 0 0, v0x28b74f0_0;
+v0x28b6700_0 .alias "in1", 0 0, v0x28b71a0_0;
+v0x28b67a0_0 .net "nS", 0 0, L_0x29fc030; 1 drivers
+v0x28b6820_0 .net "out0", 0 0, L_0x29fc0f0; 1 drivers
+v0x28b68c0_0 .net "out1", 0 0, L_0x29fc240; 1 drivers
+v0x28b69a0_0 .alias "outfinal", 0 0, v0x28b7470_0;
+S_0x28b4f00 .scope generate, "orbits[16]" "orbits[16]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b4c18 .param/l "i" 3 258, +C4<010000>;
+S_0x28b5030 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b4f00;
+ .timescale -9 -12;
+L_0x29fb440/d .functor NOR 1, L_0x29fc740, L_0x29fc7e0, C4<0>, C4<0>;
+L_0x29fb440 .delay (10000,10000,10000) L_0x29fb440/d;
+L_0x29fc900/d .functor NOT 1, L_0x29fb440, C4<0>, C4<0>, C4<0>;
+L_0x29fc900 .delay (10000,10000,10000) L_0x29fc900/d;
+L_0x29fca10/d .functor NAND 1, L_0x29fc740, L_0x29fc7e0, C4<1>, C4<1>;
+L_0x29fca10 .delay (10000,10000,10000) L_0x29fca10/d;
+L_0x29fcb70/d .functor NAND 1, L_0x29fca10, L_0x29fc900, C4<1>, C4<1>;
+L_0x29fcb70 .delay (10000,10000,10000) L_0x29fcb70/d;
+L_0x29fcc80/d .functor NOT 1, L_0x29fcb70, C4<0>, C4<0>, C4<0>;
+L_0x29fcc80 .delay (10000,10000,10000) L_0x29fcc80/d;
+v0x28b5be0_0 .net "A", 0 0, L_0x29fc740; 1 drivers
+v0x28b5c80_0 .net "AnandB", 0 0, L_0x29fca10; 1 drivers
+v0x28b5d20_0 .net "AnorB", 0 0, L_0x29fb440; 1 drivers
+v0x28b5dd0_0 .net "AorB", 0 0, L_0x29fc900; 1 drivers
+v0x28b5eb0_0 .net "AxorB", 0 0, L_0x29fcc80; 1 drivers
+v0x28b5f60_0 .net "B", 0 0, L_0x29fc7e0; 1 drivers
+v0x28b6020_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b60a0_0 .net "OrNorXorOut", 0 0, L_0x29fd680; 1 drivers
+v0x28b6120_0 .net "XorNor", 0 0, L_0x29fd100; 1 drivers
+v0x28b61f0_0 .net "nXor", 0 0, L_0x29fcb70; 1 drivers
+L_0x29fd280 .part v0x2960210_0, 2, 1;
+L_0x29fd850 .part v0x2960210_0, 0, 1;
+S_0x28b5670 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b5030;
+ .timescale -9 -12;
+L_0x29fcde0/d .functor NOT 1, L_0x29fd280, C4<0>, C4<0>, C4<0>;
+L_0x29fcde0 .delay (10000,10000,10000) L_0x29fcde0/d;
+L_0x29fcea0/d .functor AND 1, L_0x29fcc80, L_0x29fcde0, C4<1>, C4<1>;
+L_0x29fcea0 .delay (20000,20000,20000) L_0x29fcea0/d;
+L_0x29fcfb0/d .functor AND 1, L_0x29fb440, L_0x29fd280, C4<1>, C4<1>;
+L_0x29fcfb0 .delay (20000,20000,20000) L_0x29fcfb0/d;
+L_0x29fd100/d .functor OR 1, L_0x29fcea0, L_0x29fcfb0, C4<0>, C4<0>;
+L_0x29fd100 .delay (20000,20000,20000) L_0x29fd100/d;
+v0x28b5760_0 .net "S", 0 0, L_0x29fd280; 1 drivers
+v0x28b5820_0 .alias "in0", 0 0, v0x28b5eb0_0;
+v0x28b58c0_0 .alias "in1", 0 0, v0x28b5d20_0;
+v0x28b5960_0 .net "nS", 0 0, L_0x29fcde0; 1 drivers
+v0x28b59e0_0 .net "out0", 0 0, L_0x29fcea0; 1 drivers
+v0x28b5a80_0 .net "out1", 0 0, L_0x29fcfb0; 1 drivers
+v0x28b5b60_0 .alias "outfinal", 0 0, v0x28b6120_0;
+S_0x28b5120 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b5030;
+ .timescale -9 -12;
+L_0x29fd320/d .functor NOT 1, L_0x29fd850, C4<0>, C4<0>, C4<0>;
+L_0x29fd320 .delay (10000,10000,10000) L_0x29fd320/d;
+L_0x29fd3e0/d .functor AND 1, L_0x29fd100, L_0x29fd320, C4<1>, C4<1>;
+L_0x29fd3e0 .delay (20000,20000,20000) L_0x29fd3e0/d;
+L_0x29fd530/d .functor AND 1, L_0x29fc900, L_0x29fd850, C4<1>, C4<1>;
+L_0x29fd530 .delay (20000,20000,20000) L_0x29fd530/d;
+L_0x29fd680/d .functor OR 1, L_0x29fd3e0, L_0x29fd530, C4<0>, C4<0>;
+L_0x29fd680 .delay (20000,20000,20000) L_0x29fd680/d;
+v0x28b5210_0 .net "S", 0 0, L_0x29fd850; 1 drivers
+v0x28b5290_0 .alias "in0", 0 0, v0x28b6120_0;
+v0x28b5330_0 .alias "in1", 0 0, v0x28b5dd0_0;
+v0x28b53d0_0 .net "nS", 0 0, L_0x29fd320; 1 drivers
+v0x28b5450_0 .net "out0", 0 0, L_0x29fd3e0; 1 drivers
+v0x28b54f0_0 .net "out1", 0 0, L_0x29fd530; 1 drivers
+v0x28b55d0_0 .alias "outfinal", 0 0, v0x28b60a0_0;
+S_0x28b3b30 .scope generate, "orbits[17]" "orbits[17]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b3848 .param/l "i" 3 258, +C4<010001>;
+S_0x28b3c60 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b3b30;
+ .timescale -9 -12;
+L_0x29fdb20/d .functor NOR 1, L_0x29feca0, L_0x29fd990, C4<0>, C4<0>;
+L_0x29fdb20 .delay (10000,10000,10000) L_0x29fdb20/d;
+L_0x29fdc10/d .functor NOT 1, L_0x29fdb20, C4<0>, C4<0>, C4<0>;
+L_0x29fdc10 .delay (10000,10000,10000) L_0x29fdc10/d;
+L_0x29fdd20/d .functor NAND 1, L_0x29feca0, L_0x29fd990, C4<1>, C4<1>;
+L_0x29fdd20 .delay (10000,10000,10000) L_0x29fdd20/d;
+L_0x29fde80/d .functor NAND 1, L_0x29fdd20, L_0x29fdc10, C4<1>, C4<1>;
+L_0x29fde80 .delay (10000,10000,10000) L_0x29fde80/d;
+L_0x29fdf90/d .functor NOT 1, L_0x29fde80, C4<0>, C4<0>, C4<0>;
+L_0x29fdf90 .delay (10000,10000,10000) L_0x29fdf90/d;
+v0x28b4810_0 .net "A", 0 0, L_0x29feca0; 1 drivers
+v0x28b48b0_0 .net "AnandB", 0 0, L_0x29fdd20; 1 drivers
+v0x28b4950_0 .net "AnorB", 0 0, L_0x29fdb20; 1 drivers
+v0x28b4a00_0 .net "AorB", 0 0, L_0x29fdc10; 1 drivers
+v0x28b4ae0_0 .net "AxorB", 0 0, L_0x29fdf90; 1 drivers
+v0x28b4b90_0 .net "B", 0 0, L_0x29fd990; 1 drivers
+v0x28b4c50_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b4cd0_0 .net "OrNorXorOut", 0 0, L_0x29fe990; 1 drivers
+v0x28b4d50_0 .net "XorNor", 0 0, L_0x29fe410; 1 drivers
+v0x28b4e20_0 .net "nXor", 0 0, L_0x29fde80; 1 drivers
+L_0x29fe590 .part v0x2960210_0, 2, 1;
+L_0x29feb60 .part v0x2960210_0, 0, 1;
+S_0x28b42a0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b3c60;
+ .timescale -9 -12;
+L_0x29fe0f0/d .functor NOT 1, L_0x29fe590, C4<0>, C4<0>, C4<0>;
+L_0x29fe0f0 .delay (10000,10000,10000) L_0x29fe0f0/d;
+L_0x29fe1b0/d .functor AND 1, L_0x29fdf90, L_0x29fe0f0, C4<1>, C4<1>;
+L_0x29fe1b0 .delay (20000,20000,20000) L_0x29fe1b0/d;
+L_0x29fe2c0/d .functor AND 1, L_0x29fdb20, L_0x29fe590, C4<1>, C4<1>;
+L_0x29fe2c0 .delay (20000,20000,20000) L_0x29fe2c0/d;
+L_0x29fe410/d .functor OR 1, L_0x29fe1b0, L_0x29fe2c0, C4<0>, C4<0>;
+L_0x29fe410 .delay (20000,20000,20000) L_0x29fe410/d;
+v0x28b4390_0 .net "S", 0 0, L_0x29fe590; 1 drivers
+v0x28b4450_0 .alias "in0", 0 0, v0x28b4ae0_0;
+v0x28b44f0_0 .alias "in1", 0 0, v0x28b4950_0;
+v0x28b4590_0 .net "nS", 0 0, L_0x29fe0f0; 1 drivers
+v0x28b4610_0 .net "out0", 0 0, L_0x29fe1b0; 1 drivers
+v0x28b46b0_0 .net "out1", 0 0, L_0x29fe2c0; 1 drivers
+v0x28b4790_0 .alias "outfinal", 0 0, v0x28b4d50_0;
+S_0x28b3d50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b3c60;
+ .timescale -9 -12;
+L_0x29fe630/d .functor NOT 1, L_0x29feb60, C4<0>, C4<0>, C4<0>;
+L_0x29fe630 .delay (10000,10000,10000) L_0x29fe630/d;
+L_0x29fe6f0/d .functor AND 1, L_0x29fe410, L_0x29fe630, C4<1>, C4<1>;
+L_0x29fe6f0 .delay (20000,20000,20000) L_0x29fe6f0/d;
+L_0x29fe840/d .functor AND 1, L_0x29fdc10, L_0x29feb60, C4<1>, C4<1>;
+L_0x29fe840 .delay (20000,20000,20000) L_0x29fe840/d;
+L_0x29fe990/d .functor OR 1, L_0x29fe6f0, L_0x29fe840, C4<0>, C4<0>;
+L_0x29fe990 .delay (20000,20000,20000) L_0x29fe990/d;
+v0x28b3e40_0 .net "S", 0 0, L_0x29feb60; 1 drivers
+v0x28b3ec0_0 .alias "in0", 0 0, v0x28b4d50_0;
+v0x28b3f60_0 .alias "in1", 0 0, v0x28b4a00_0;
+v0x28b4000_0 .net "nS", 0 0, L_0x29fe630; 1 drivers
+v0x28b4080_0 .net "out0", 0 0, L_0x29fe6f0; 1 drivers
+v0x28b4120_0 .net "out1", 0 0, L_0x29fe840; 1 drivers
+v0x28b4200_0 .alias "outfinal", 0 0, v0x28b4cd0_0;
+S_0x28b2760 .scope generate, "orbits[18]" "orbits[18]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b2478 .param/l "i" 3 258, +C4<010010>;
+S_0x28b2890 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b2760;
+ .timescale -9 -12;
+L_0x29fda30/d .functor NOR 1, L_0x29fed40, L_0x29fede0, C4<0>, C4<0>;
+L_0x29fda30 .delay (10000,10000,10000) L_0x29fda30/d;
+L_0x29feee0/d .functor NOT 1, L_0x29fda30, C4<0>, C4<0>, C4<0>;
+L_0x29feee0 .delay (10000,10000,10000) L_0x29feee0/d;
+L_0x29ff010/d .functor NAND 1, L_0x29fed40, L_0x29fede0, C4<1>, C4<1>;
+L_0x29ff010 .delay (10000,10000,10000) L_0x29ff010/d;
+L_0x29ff170/d .functor NAND 1, L_0x29ff010, L_0x29feee0, C4<1>, C4<1>;
+L_0x29ff170 .delay (10000,10000,10000) L_0x29ff170/d;
+L_0x29ff280/d .functor NOT 1, L_0x29ff170, C4<0>, C4<0>, C4<0>;
+L_0x29ff280 .delay (10000,10000,10000) L_0x29ff280/d;
+v0x28b3440_0 .net "A", 0 0, L_0x29fed40; 1 drivers
+v0x28b34e0_0 .net "AnandB", 0 0, L_0x29ff010; 1 drivers
+v0x28b3580_0 .net "AnorB", 0 0, L_0x29fda30; 1 drivers
+v0x28b3630_0 .net "AorB", 0 0, L_0x29feee0; 1 drivers
+v0x28b3710_0 .net "AxorB", 0 0, L_0x29ff280; 1 drivers
+v0x28b37c0_0 .net "B", 0 0, L_0x29fede0; 1 drivers
+v0x28b3880_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b3900_0 .net "OrNorXorOut", 0 0, L_0x29ffc80; 1 drivers
+v0x28b3980_0 .net "XorNor", 0 0, L_0x29ff700; 1 drivers
+v0x28b3a50_0 .net "nXor", 0 0, L_0x29ff170; 1 drivers
+L_0x29ff880 .part v0x2960210_0, 2, 1;
+L_0x29ffe50 .part v0x2960210_0, 0, 1;
+S_0x28b2ed0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b2890;
+ .timescale -9 -12;
+L_0x29ff3e0/d .functor NOT 1, L_0x29ff880, C4<0>, C4<0>, C4<0>;
+L_0x29ff3e0 .delay (10000,10000,10000) L_0x29ff3e0/d;
+L_0x29ff4a0/d .functor AND 1, L_0x29ff280, L_0x29ff3e0, C4<1>, C4<1>;
+L_0x29ff4a0 .delay (20000,20000,20000) L_0x29ff4a0/d;
+L_0x29ff5b0/d .functor AND 1, L_0x29fda30, L_0x29ff880, C4<1>, C4<1>;
+L_0x29ff5b0 .delay (20000,20000,20000) L_0x29ff5b0/d;
+L_0x29ff700/d .functor OR 1, L_0x29ff4a0, L_0x29ff5b0, C4<0>, C4<0>;
+L_0x29ff700 .delay (20000,20000,20000) L_0x29ff700/d;
+v0x28b2fc0_0 .net "S", 0 0, L_0x29ff880; 1 drivers
+v0x28b3080_0 .alias "in0", 0 0, v0x28b3710_0;
+v0x28b3120_0 .alias "in1", 0 0, v0x28b3580_0;
+v0x28b31c0_0 .net "nS", 0 0, L_0x29ff3e0; 1 drivers
+v0x28b3240_0 .net "out0", 0 0, L_0x29ff4a0; 1 drivers
+v0x28b32e0_0 .net "out1", 0 0, L_0x29ff5b0; 1 drivers
+v0x28b33c0_0 .alias "outfinal", 0 0, v0x28b3980_0;
+S_0x28b2980 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b2890;
+ .timescale -9 -12;
+L_0x29ff920/d .functor NOT 1, L_0x29ffe50, C4<0>, C4<0>, C4<0>;
+L_0x29ff920 .delay (10000,10000,10000) L_0x29ff920/d;
+L_0x29ff9e0/d .functor AND 1, L_0x29ff700, L_0x29ff920, C4<1>, C4<1>;
+L_0x29ff9e0 .delay (20000,20000,20000) L_0x29ff9e0/d;
+L_0x29ffb30/d .functor AND 1, L_0x29feee0, L_0x29ffe50, C4<1>, C4<1>;
+L_0x29ffb30 .delay (20000,20000,20000) L_0x29ffb30/d;
+L_0x29ffc80/d .functor OR 1, L_0x29ff9e0, L_0x29ffb30, C4<0>, C4<0>;
+L_0x29ffc80 .delay (20000,20000,20000) L_0x29ffc80/d;
+v0x28b2a70_0 .net "S", 0 0, L_0x29ffe50; 1 drivers
+v0x28b2af0_0 .alias "in0", 0 0, v0x28b3980_0;
+v0x28b2b90_0 .alias "in1", 0 0, v0x28b3630_0;
+v0x28b2c30_0 .net "nS", 0 0, L_0x29ff920; 1 drivers
+v0x28b2cb0_0 .net "out0", 0 0, L_0x29ff9e0; 1 drivers
+v0x28b2d50_0 .net "out1", 0 0, L_0x29ffb30; 1 drivers
+v0x28b2e30_0 .alias "outfinal", 0 0, v0x28b3900_0;
+S_0x28b1390 .scope generate, "orbits[19]" "orbits[19]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28b10a8 .param/l "i" 3 258, +C4<010011>;
+S_0x28b14c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28b1390;
+ .timescale -9 -12;
+L_0x29fee80/d .functor NOR 1, L_0x2a022a0, L_0x29b4e70, C4<0>, C4<0>;
+L_0x29fee80 .delay (10000,10000,10000) L_0x29fee80/d;
+L_0x2a00020/d .functor NOT 1, L_0x29fee80, C4<0>, C4<0>, C4<0>;
+L_0x2a00020 .delay (10000,10000,10000) L_0x2a00020/d;
+L_0x2a000e0/d .functor NAND 1, L_0x2a022a0, L_0x29b4e70, C4<1>, C4<1>;
+L_0x2a000e0 .delay (10000,10000,10000) L_0x2a000e0/d;
+L_0x29b5160/d .functor NAND 1, L_0x2a000e0, L_0x2a00020, C4<1>, C4<1>;
+L_0x29b5160 .delay (10000,10000,10000) L_0x29b5160/d;
+L_0x29b5270/d .functor NOT 1, L_0x29b5160, C4<0>, C4<0>, C4<0>;
+L_0x29b5270 .delay (10000,10000,10000) L_0x29b5270/d;
+v0x28b2070_0 .net "A", 0 0, L_0x2a022a0; 1 drivers
+v0x28b2110_0 .net "AnandB", 0 0, L_0x2a000e0; 1 drivers
+v0x28b21b0_0 .net "AnorB", 0 0, L_0x29fee80; 1 drivers
+v0x28b2260_0 .net "AorB", 0 0, L_0x2a00020; 1 drivers
+v0x28b2340_0 .net "AxorB", 0 0, L_0x29b5270; 1 drivers
+v0x28b23f0_0 .net "B", 0 0, L_0x29b4e70; 1 drivers
+v0x28b24b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b2530_0 .net "OrNorXorOut", 0 0, L_0x29b5c70; 1 drivers
+v0x28b25b0_0 .net "XorNor", 0 0, L_0x29b56f0; 1 drivers
+v0x28b2680_0 .net "nXor", 0 0, L_0x29b5160; 1 drivers
+L_0x29b5870 .part v0x2960210_0, 2, 1;
+L_0x2a02160 .part v0x2960210_0, 0, 1;
+S_0x28b1b00 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b14c0;
+ .timescale -9 -12;
+L_0x29b53d0/d .functor NOT 1, L_0x29b5870, C4<0>, C4<0>, C4<0>;
+L_0x29b53d0 .delay (10000,10000,10000) L_0x29b53d0/d;
+L_0x29b5490/d .functor AND 1, L_0x29b5270, L_0x29b53d0, C4<1>, C4<1>;
+L_0x29b5490 .delay (20000,20000,20000) L_0x29b5490/d;
+L_0x29b55a0/d .functor AND 1, L_0x29fee80, L_0x29b5870, C4<1>, C4<1>;
+L_0x29b55a0 .delay (20000,20000,20000) L_0x29b55a0/d;
+L_0x29b56f0/d .functor OR 1, L_0x29b5490, L_0x29b55a0, C4<0>, C4<0>;
+L_0x29b56f0 .delay (20000,20000,20000) L_0x29b56f0/d;
+v0x28b1bf0_0 .net "S", 0 0, L_0x29b5870; 1 drivers
+v0x28b1cb0_0 .alias "in0", 0 0, v0x28b2340_0;
+v0x28b1d50_0 .alias "in1", 0 0, v0x28b21b0_0;
+v0x28b1df0_0 .net "nS", 0 0, L_0x29b53d0; 1 drivers
+v0x28b1e70_0 .net "out0", 0 0, L_0x29b5490; 1 drivers
+v0x28b1f10_0 .net "out1", 0 0, L_0x29b55a0; 1 drivers
+v0x28b1ff0_0 .alias "outfinal", 0 0, v0x28b25b0_0;
+S_0x28b15b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b14c0;
+ .timescale -9 -12;
+L_0x29b5910/d .functor NOT 1, L_0x2a02160, C4<0>, C4<0>, C4<0>;
+L_0x29b5910 .delay (10000,10000,10000) L_0x29b5910/d;
+L_0x29b59d0/d .functor AND 1, L_0x29b56f0, L_0x29b5910, C4<1>, C4<1>;
+L_0x29b59d0 .delay (20000,20000,20000) L_0x29b59d0/d;
+L_0x29b5b20/d .functor AND 1, L_0x2a00020, L_0x2a02160, C4<1>, C4<1>;
+L_0x29b5b20 .delay (20000,20000,20000) L_0x29b5b20/d;
+L_0x29b5c70/d .functor OR 1, L_0x29b59d0, L_0x29b5b20, C4<0>, C4<0>;
+L_0x29b5c70 .delay (20000,20000,20000) L_0x29b5c70/d;
+v0x28b16a0_0 .net "S", 0 0, L_0x2a02160; 1 drivers
+v0x28b1720_0 .alias "in0", 0 0, v0x28b25b0_0;
+v0x28b17c0_0 .alias "in1", 0 0, v0x28b2260_0;
+v0x28b1860_0 .net "nS", 0 0, L_0x29b5910; 1 drivers
+v0x28b18e0_0 .net "out0", 0 0, L_0x29b59d0; 1 drivers
+v0x28b1980_0 .net "out1", 0 0, L_0x29b5b20; 1 drivers
+v0x28b1a60_0 .alias "outfinal", 0 0, v0x28b2530_0;
+S_0x28affc0 .scope generate, "orbits[20]" "orbits[20]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28afcd8 .param/l "i" 3 258, +C4<010100>;
+S_0x28b00f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28affc0;
+ .timescale -9 -12;
+L_0x29b4f10/d .functor NOR 1, L_0x2a02340, L_0x2a023e0, C4<0>, C4<0>;
+L_0x29b4f10 .delay (10000,10000,10000) L_0x29b4f10/d;
+L_0x29b4fb0/d .functor NOT 1, L_0x29b4f10, C4<0>, C4<0>, C4<0>;
+L_0x29b4fb0 .delay (10000,10000,10000) L_0x29b4fb0/d;
+L_0x2a025a0/d .functor NAND 1, L_0x2a02340, L_0x2a023e0, C4<1>, C4<1>;
+L_0x2a025a0 .delay (10000,10000,10000) L_0x2a025a0/d;
+L_0x2a026e0/d .functor NAND 1, L_0x2a025a0, L_0x29b4fb0, C4<1>, C4<1>;
+L_0x2a026e0 .delay (10000,10000,10000) L_0x2a026e0/d;
+L_0x2a027d0/d .functor NOT 1, L_0x2a026e0, C4<0>, C4<0>, C4<0>;
+L_0x2a027d0 .delay (10000,10000,10000) L_0x2a027d0/d;
+v0x28b0ca0_0 .net "A", 0 0, L_0x2a02340; 1 drivers
+v0x28b0d40_0 .net "AnandB", 0 0, L_0x2a025a0; 1 drivers
+v0x28b0de0_0 .net "AnorB", 0 0, L_0x29b4f10; 1 drivers
+v0x28b0e90_0 .net "AorB", 0 0, L_0x29b4fb0; 1 drivers
+v0x28b0f70_0 .net "AxorB", 0 0, L_0x2a027d0; 1 drivers
+v0x28b1020_0 .net "B", 0 0, L_0x2a023e0; 1 drivers
+v0x28b10e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28b1160_0 .net "OrNorXorOut", 0 0, L_0x2a03150; 1 drivers
+v0x28b11e0_0 .net "XorNor", 0 0, L_0x2a02bd0; 1 drivers
+v0x28b12b0_0 .net "nXor", 0 0, L_0x2a026e0; 1 drivers
+L_0x2a02d50 .part v0x2960210_0, 2, 1;
+L_0x2a03320 .part v0x2960210_0, 0, 1;
+S_0x28b0730 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28b00f0;
+ .timescale -9 -12;
+L_0x2a02910/d .functor NOT 1, L_0x2a02d50, C4<0>, C4<0>, C4<0>;
+L_0x2a02910 .delay (10000,10000,10000) L_0x2a02910/d;
+L_0x2a029b0/d .functor AND 1, L_0x2a027d0, L_0x2a02910, C4<1>, C4<1>;
+L_0x2a029b0 .delay (20000,20000,20000) L_0x2a029b0/d;
+L_0x2a02aa0/d .functor AND 1, L_0x29b4f10, L_0x2a02d50, C4<1>, C4<1>;
+L_0x2a02aa0 .delay (20000,20000,20000) L_0x2a02aa0/d;
+L_0x2a02bd0/d .functor OR 1, L_0x2a029b0, L_0x2a02aa0, C4<0>, C4<0>;
+L_0x2a02bd0 .delay (20000,20000,20000) L_0x2a02bd0/d;
+v0x28b0820_0 .net "S", 0 0, L_0x2a02d50; 1 drivers
+v0x28b08e0_0 .alias "in0", 0 0, v0x28b0f70_0;
+v0x28b0980_0 .alias "in1", 0 0, v0x28b0de0_0;
+v0x28b0a20_0 .net "nS", 0 0, L_0x2a02910; 1 drivers
+v0x28b0aa0_0 .net "out0", 0 0, L_0x2a029b0; 1 drivers
+v0x28b0b40_0 .net "out1", 0 0, L_0x2a02aa0; 1 drivers
+v0x28b0c20_0 .alias "outfinal", 0 0, v0x28b11e0_0;
+S_0x28b01e0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28b00f0;
+ .timescale -9 -12;
+L_0x2a02df0/d .functor NOT 1, L_0x2a03320, C4<0>, C4<0>, C4<0>;
+L_0x2a02df0 .delay (10000,10000,10000) L_0x2a02df0/d;
+L_0x2a02eb0/d .functor AND 1, L_0x2a02bd0, L_0x2a02df0, C4<1>, C4<1>;
+L_0x2a02eb0 .delay (20000,20000,20000) L_0x2a02eb0/d;
+L_0x2a03000/d .functor AND 1, L_0x29b4fb0, L_0x2a03320, C4<1>, C4<1>;
+L_0x2a03000 .delay (20000,20000,20000) L_0x2a03000/d;
+L_0x2a03150/d .functor OR 1, L_0x2a02eb0, L_0x2a03000, C4<0>, C4<0>;
+L_0x2a03150 .delay (20000,20000,20000) L_0x2a03150/d;
+v0x28b02d0_0 .net "S", 0 0, L_0x2a03320; 1 drivers
+v0x28b0350_0 .alias "in0", 0 0, v0x28b11e0_0;
+v0x28b03f0_0 .alias "in1", 0 0, v0x28b0e90_0;
+v0x28b0490_0 .net "nS", 0 0, L_0x2a02df0; 1 drivers
+v0x28b0510_0 .net "out0", 0 0, L_0x2a02eb0; 1 drivers
+v0x28b05b0_0 .net "out1", 0 0, L_0x2a03000; 1 drivers
+v0x28b0690_0 .alias "outfinal", 0 0, v0x28b1160_0;
+S_0x28aebf0 .scope generate, "orbits[21]" "orbits[21]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28ae908 .param/l "i" 3 258, +C4<010101>;
+S_0x28aed20 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28aebf0;
+ .timescale -9 -12;
+L_0x2a02480/d .functor NOR 1, L_0x2a04770, L_0x2a03460, C4<0>, C4<0>;
+L_0x2a02480 .delay (10000,10000,10000) L_0x2a02480/d;
+L_0x2a036e0/d .functor NOT 1, L_0x2a02480, C4<0>, C4<0>, C4<0>;
+L_0x2a036e0 .delay (10000,10000,10000) L_0x2a036e0/d;
+L_0x2a037f0/d .functor NAND 1, L_0x2a04770, L_0x2a03460, C4<1>, C4<1>;
+L_0x2a037f0 .delay (10000,10000,10000) L_0x2a037f0/d;
+L_0x2a03950/d .functor NAND 1, L_0x2a037f0, L_0x2a036e0, C4<1>, C4<1>;
+L_0x2a03950 .delay (10000,10000,10000) L_0x2a03950/d;
+L_0x2a03a60/d .functor NOT 1, L_0x2a03950, C4<0>, C4<0>, C4<0>;
+L_0x2a03a60 .delay (10000,10000,10000) L_0x2a03a60/d;
+v0x28af8d0_0 .net "A", 0 0, L_0x2a04770; 1 drivers
+v0x28af970_0 .net "AnandB", 0 0, L_0x2a037f0; 1 drivers
+v0x28afa10_0 .net "AnorB", 0 0, L_0x2a02480; 1 drivers
+v0x28afac0_0 .net "AorB", 0 0, L_0x2a036e0; 1 drivers
+v0x28afba0_0 .net "AxorB", 0 0, L_0x2a03a60; 1 drivers
+v0x28afc50_0 .net "B", 0 0, L_0x2a03460; 1 drivers
+v0x28afd10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28afd90_0 .net "OrNorXorOut", 0 0, L_0x2a04460; 1 drivers
+v0x28afe10_0 .net "XorNor", 0 0, L_0x2a03ee0; 1 drivers
+v0x28afee0_0 .net "nXor", 0 0, L_0x2a03950; 1 drivers
+L_0x2a04060 .part v0x2960210_0, 2, 1;
+L_0x2a04630 .part v0x2960210_0, 0, 1;
+S_0x28af360 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28aed20;
+ .timescale -9 -12;
+L_0x2a03bc0/d .functor NOT 1, L_0x2a04060, C4<0>, C4<0>, C4<0>;
+L_0x2a03bc0 .delay (10000,10000,10000) L_0x2a03bc0/d;
+L_0x2a03c80/d .functor AND 1, L_0x2a03a60, L_0x2a03bc0, C4<1>, C4<1>;
+L_0x2a03c80 .delay (20000,20000,20000) L_0x2a03c80/d;
+L_0x2a03d90/d .functor AND 1, L_0x2a02480, L_0x2a04060, C4<1>, C4<1>;
+L_0x2a03d90 .delay (20000,20000,20000) L_0x2a03d90/d;
+L_0x2a03ee0/d .functor OR 1, L_0x2a03c80, L_0x2a03d90, C4<0>, C4<0>;
+L_0x2a03ee0 .delay (20000,20000,20000) L_0x2a03ee0/d;
+v0x28af450_0 .net "S", 0 0, L_0x2a04060; 1 drivers
+v0x28af510_0 .alias "in0", 0 0, v0x28afba0_0;
+v0x28af5b0_0 .alias "in1", 0 0, v0x28afa10_0;
+v0x28af650_0 .net "nS", 0 0, L_0x2a03bc0; 1 drivers
+v0x28af6d0_0 .net "out0", 0 0, L_0x2a03c80; 1 drivers
+v0x28af770_0 .net "out1", 0 0, L_0x2a03d90; 1 drivers
+v0x28af850_0 .alias "outfinal", 0 0, v0x28afe10_0;
+S_0x28aee10 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28aed20;
+ .timescale -9 -12;
+L_0x2a04100/d .functor NOT 1, L_0x2a04630, C4<0>, C4<0>, C4<0>;
+L_0x2a04100 .delay (10000,10000,10000) L_0x2a04100/d;
+L_0x2a041c0/d .functor AND 1, L_0x2a03ee0, L_0x2a04100, C4<1>, C4<1>;
+L_0x2a041c0 .delay (20000,20000,20000) L_0x2a041c0/d;
+L_0x2a04310/d .functor AND 1, L_0x2a036e0, L_0x2a04630, C4<1>, C4<1>;
+L_0x2a04310 .delay (20000,20000,20000) L_0x2a04310/d;
+L_0x2a04460/d .functor OR 1, L_0x2a041c0, L_0x2a04310, C4<0>, C4<0>;
+L_0x2a04460 .delay (20000,20000,20000) L_0x2a04460/d;
+v0x28aef00_0 .net "S", 0 0, L_0x2a04630; 1 drivers
+v0x28aef80_0 .alias "in0", 0 0, v0x28afe10_0;
+v0x28af020_0 .alias "in1", 0 0, v0x28afac0_0;
+v0x28af0c0_0 .net "nS", 0 0, L_0x2a04100; 1 drivers
+v0x28af140_0 .net "out0", 0 0, L_0x2a041c0; 1 drivers
+v0x28af1e0_0 .net "out1", 0 0, L_0x2a04310; 1 drivers
+v0x28af2c0_0 .alias "outfinal", 0 0, v0x28afd90_0;
+S_0x28ad820 .scope generate, "orbits[22]" "orbits[22]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28ad538 .param/l "i" 3 258, +C4<010110>;
+S_0x28ad950 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28ad820;
+ .timescale -9 -12;
+L_0x2a03500/d .functor NOR 1, L_0x2a04810, L_0x2a048b0, C4<0>, C4<0>;
+L_0x2a03500 .delay (10000,10000,10000) L_0x2a03500/d;
+L_0x2a035f0/d .functor NOT 1, L_0x2a03500, C4<0>, C4<0>, C4<0>;
+L_0x2a035f0 .delay (10000,10000,10000) L_0x2a035f0/d;
+L_0x2a04ae0/d .functor NAND 1, L_0x2a04810, L_0x2a048b0, C4<1>, C4<1>;
+L_0x2a04ae0 .delay (10000,10000,10000) L_0x2a04ae0/d;
+L_0x2a04c40/d .functor NAND 1, L_0x2a04ae0, L_0x2a035f0, C4<1>, C4<1>;
+L_0x2a04c40 .delay (10000,10000,10000) L_0x2a04c40/d;
+L_0x2a04d50/d .functor NOT 1, L_0x2a04c40, C4<0>, C4<0>, C4<0>;
+L_0x2a04d50 .delay (10000,10000,10000) L_0x2a04d50/d;
+v0x28ae500_0 .net "A", 0 0, L_0x2a04810; 1 drivers
+v0x28ae5a0_0 .net "AnandB", 0 0, L_0x2a04ae0; 1 drivers
+v0x28ae640_0 .net "AnorB", 0 0, L_0x2a03500; 1 drivers
+v0x28ae6f0_0 .net "AorB", 0 0, L_0x2a035f0; 1 drivers
+v0x28ae7d0_0 .net "AxorB", 0 0, L_0x2a04d50; 1 drivers
+v0x28ae880_0 .net "B", 0 0, L_0x2a048b0; 1 drivers
+v0x28ae940_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28ae9c0_0 .net "OrNorXorOut", 0 0, L_0x2a05750; 1 drivers
+v0x28aea40_0 .net "XorNor", 0 0, L_0x2a051d0; 1 drivers
+v0x28aeb10_0 .net "nXor", 0 0, L_0x2a04c40; 1 drivers
+L_0x2a05350 .part v0x2960210_0, 2, 1;
+L_0x2a05920 .part v0x2960210_0, 0, 1;
+S_0x28adf90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28ad950;
+ .timescale -9 -12;
+L_0x2a04eb0/d .functor NOT 1, L_0x2a05350, C4<0>, C4<0>, C4<0>;
+L_0x2a04eb0 .delay (10000,10000,10000) L_0x2a04eb0/d;
+L_0x2a04f70/d .functor AND 1, L_0x2a04d50, L_0x2a04eb0, C4<1>, C4<1>;
+L_0x2a04f70 .delay (20000,20000,20000) L_0x2a04f70/d;
+L_0x2a05080/d .functor AND 1, L_0x2a03500, L_0x2a05350, C4<1>, C4<1>;
+L_0x2a05080 .delay (20000,20000,20000) L_0x2a05080/d;
+L_0x2a051d0/d .functor OR 1, L_0x2a04f70, L_0x2a05080, C4<0>, C4<0>;
+L_0x2a051d0 .delay (20000,20000,20000) L_0x2a051d0/d;
+v0x28ae080_0 .net "S", 0 0, L_0x2a05350; 1 drivers
+v0x28ae140_0 .alias "in0", 0 0, v0x28ae7d0_0;
+v0x28ae1e0_0 .alias "in1", 0 0, v0x28ae640_0;
+v0x28ae280_0 .net "nS", 0 0, L_0x2a04eb0; 1 drivers
+v0x28ae300_0 .net "out0", 0 0, L_0x2a04f70; 1 drivers
+v0x28ae3a0_0 .net "out1", 0 0, L_0x2a05080; 1 drivers
+v0x28ae480_0 .alias "outfinal", 0 0, v0x28aea40_0;
+S_0x28ada40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28ad950;
+ .timescale -9 -12;
+L_0x2a053f0/d .functor NOT 1, L_0x2a05920, C4<0>, C4<0>, C4<0>;
+L_0x2a053f0 .delay (10000,10000,10000) L_0x2a053f0/d;
+L_0x2a054b0/d .functor AND 1, L_0x2a051d0, L_0x2a053f0, C4<1>, C4<1>;
+L_0x2a054b0 .delay (20000,20000,20000) L_0x2a054b0/d;
+L_0x2a05600/d .functor AND 1, L_0x2a035f0, L_0x2a05920, C4<1>, C4<1>;
+L_0x2a05600 .delay (20000,20000,20000) L_0x2a05600/d;
+L_0x2a05750/d .functor OR 1, L_0x2a054b0, L_0x2a05600, C4<0>, C4<0>;
+L_0x2a05750 .delay (20000,20000,20000) L_0x2a05750/d;
+v0x28adb30_0 .net "S", 0 0, L_0x2a05920; 1 drivers
+v0x28adbb0_0 .alias "in0", 0 0, v0x28aea40_0;
+v0x28adc50_0 .alias "in1", 0 0, v0x28ae6f0_0;
+v0x28adcf0_0 .net "nS", 0 0, L_0x2a053f0; 1 drivers
+v0x28add70_0 .net "out0", 0 0, L_0x2a054b0; 1 drivers
+v0x28ade10_0 .net "out1", 0 0, L_0x2a05600; 1 drivers
+v0x28adef0_0 .alias "outfinal", 0 0, v0x28ae9c0_0;
+S_0x28ac410 .scope generate, "orbits[23]" "orbits[23]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28ac508 .param/l "i" 3 258, +C4<010111>;
+S_0x28ac580 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28ac410;
+ .timescale -9 -12;
+L_0x2a04950/d .functor NOR 1, L_0x2a06d60, L_0x2a05a60, C4<0>, C4<0>;
+L_0x2a04950 .delay (10000,10000,10000) L_0x2a04950/d;
+L_0x2a05cd0/d .functor NOT 1, L_0x2a04950, C4<0>, C4<0>, C4<0>;
+L_0x2a05cd0 .delay (10000,10000,10000) L_0x2a05cd0/d;
+L_0x2a05de0/d .functor NAND 1, L_0x2a06d60, L_0x2a05a60, C4<1>, C4<1>;
+L_0x2a05de0 .delay (10000,10000,10000) L_0x2a05de0/d;
+L_0x2a05f40/d .functor NAND 1, L_0x2a05de0, L_0x2a05cd0, C4<1>, C4<1>;
+L_0x2a05f40 .delay (10000,10000,10000) L_0x2a05f40/d;
+L_0x2a06050/d .functor NOT 1, L_0x2a05f40, C4<0>, C4<0>, C4<0>;
+L_0x2a06050 .delay (10000,10000,10000) L_0x2a06050/d;
+v0x28ad130_0 .net "A", 0 0, L_0x2a06d60; 1 drivers
+v0x28ad1d0_0 .net "AnandB", 0 0, L_0x2a05de0; 1 drivers
+v0x28ad270_0 .net "AnorB", 0 0, L_0x2a04950; 1 drivers
+v0x28ad320_0 .net "AorB", 0 0, L_0x2a05cd0; 1 drivers
+v0x28ad400_0 .net "AxorB", 0 0, L_0x2a06050; 1 drivers
+v0x28ad4b0_0 .net "B", 0 0, L_0x2a05a60; 1 drivers
+v0x28ad570_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28ad5f0_0 .net "OrNorXorOut", 0 0, L_0x2a06a50; 1 drivers
+v0x28ad670_0 .net "XorNor", 0 0, L_0x2a064d0; 1 drivers
+v0x28ad740_0 .net "nXor", 0 0, L_0x2a05f40; 1 drivers
+L_0x2a06650 .part v0x2960210_0, 2, 1;
+L_0x2a06c20 .part v0x2960210_0, 0, 1;
+S_0x28acbc0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28ac580;
+ .timescale -9 -12;
+L_0x2a061b0/d .functor NOT 1, L_0x2a06650, C4<0>, C4<0>, C4<0>;
+L_0x2a061b0 .delay (10000,10000,10000) L_0x2a061b0/d;
+L_0x2a06270/d .functor AND 1, L_0x2a06050, L_0x2a061b0, C4<1>, C4<1>;
+L_0x2a06270 .delay (20000,20000,20000) L_0x2a06270/d;
+L_0x2a06380/d .functor AND 1, L_0x2a04950, L_0x2a06650, C4<1>, C4<1>;
+L_0x2a06380 .delay (20000,20000,20000) L_0x2a06380/d;
+L_0x2a064d0/d .functor OR 1, L_0x2a06270, L_0x2a06380, C4<0>, C4<0>;
+L_0x2a064d0 .delay (20000,20000,20000) L_0x2a064d0/d;
+v0x28accb0_0 .net "S", 0 0, L_0x2a06650; 1 drivers
+v0x28acd70_0 .alias "in0", 0 0, v0x28ad400_0;
+v0x28ace10_0 .alias "in1", 0 0, v0x28ad270_0;
+v0x28aceb0_0 .net "nS", 0 0, L_0x2a061b0; 1 drivers
+v0x28acf30_0 .net "out0", 0 0, L_0x2a06270; 1 drivers
+v0x28acfd0_0 .net "out1", 0 0, L_0x2a06380; 1 drivers
+v0x28ad0b0_0 .alias "outfinal", 0 0, v0x28ad670_0;
+S_0x28ac670 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28ac580;
+ .timescale -9 -12;
+L_0x2a066f0/d .functor NOT 1, L_0x2a06c20, C4<0>, C4<0>, C4<0>;
+L_0x2a066f0 .delay (10000,10000,10000) L_0x2a066f0/d;
+L_0x2a067b0/d .functor AND 1, L_0x2a064d0, L_0x2a066f0, C4<1>, C4<1>;
+L_0x2a067b0 .delay (20000,20000,20000) L_0x2a067b0/d;
+L_0x2a06900/d .functor AND 1, L_0x2a05cd0, L_0x2a06c20, C4<1>, C4<1>;
+L_0x2a06900 .delay (20000,20000,20000) L_0x2a06900/d;
+L_0x2a06a50/d .functor OR 1, L_0x2a067b0, L_0x2a06900, C4<0>, C4<0>;
+L_0x2a06a50 .delay (20000,20000,20000) L_0x2a06a50/d;
+v0x28ac760_0 .net "S", 0 0, L_0x2a06c20; 1 drivers
+v0x28ac7e0_0 .alias "in0", 0 0, v0x28ad670_0;
+v0x28ac880_0 .alias "in1", 0 0, v0x28ad320_0;
+v0x28ac920_0 .net "nS", 0 0, L_0x2a066f0; 1 drivers
+v0x28ac9a0_0 .net "out0", 0 0, L_0x2a067b0; 1 drivers
+v0x28aca40_0 .net "out1", 0 0, L_0x2a06900; 1 drivers
+v0x28acb20_0 .alias "outfinal", 0 0, v0x28ad5f0_0;
+S_0x28ab0e0 .scope generate, "orbits[24]" "orbits[24]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28aadf8 .param/l "i" 3 258, +C4<011000>;
+S_0x28ab210 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28ab0e0;
+ .timescale -9 -12;
+L_0x2a05b00/d .functor NOR 1, L_0x2a06e00, L_0x2a06ea0, C4<0>, C4<0>;
+L_0x2a05b00 .delay (10000,10000,10000) L_0x2a05b00/d;
+L_0x2a05bf0/d .functor NOT 1, L_0x2a05b00, C4<0>, C4<0>, C4<0>;
+L_0x2a05bf0 .delay (10000,10000,10000) L_0x2a05bf0/d;
+L_0x2a070e0/d .functor NAND 1, L_0x2a06e00, L_0x2a06ea0, C4<1>, C4<1>;
+L_0x2a070e0 .delay (10000,10000,10000) L_0x2a070e0/d;
+L_0x2a07240/d .functor NAND 1, L_0x2a070e0, L_0x2a05bf0, C4<1>, C4<1>;
+L_0x2a07240 .delay (10000,10000,10000) L_0x2a07240/d;
+L_0x2a07350/d .functor NOT 1, L_0x2a07240, C4<0>, C4<0>, C4<0>;
+L_0x2a07350 .delay (10000,10000,10000) L_0x2a07350/d;
+v0x28abdc0_0 .net "A", 0 0, L_0x2a06e00; 1 drivers
+v0x28abe60_0 .net "AnandB", 0 0, L_0x2a070e0; 1 drivers
+v0x28abf00_0 .net "AnorB", 0 0, L_0x2a05b00; 1 drivers
+v0x28abfb0_0 .net "AorB", 0 0, L_0x2a05bf0; 1 drivers
+v0x28ac030_0 .net "AxorB", 0 0, L_0x2a07350; 1 drivers
+v0x28ac0b0_0 .net "B", 0 0, L_0x2a06ea0; 1 drivers
+v0x28ac130_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28ac1b0_0 .net "OrNorXorOut", 0 0, L_0x2a07d10; 1 drivers
+v0x28ac260_0 .net "XorNor", 0 0, L_0x2a07790; 1 drivers
+v0x28ac330_0 .net "nXor", 0 0, L_0x2a07240; 1 drivers
+L_0x2a07910 .part v0x2960210_0, 2, 1;
+L_0x2a07ee0 .part v0x2960210_0, 0, 1;
+S_0x28ab850 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28ab210;
+ .timescale -9 -12;
+L_0x2a07470/d .functor NOT 1, L_0x2a07910, C4<0>, C4<0>, C4<0>;
+L_0x2a07470 .delay (10000,10000,10000) L_0x2a07470/d;
+L_0x2a07530/d .functor AND 1, L_0x2a07350, L_0x2a07470, C4<1>, C4<1>;
+L_0x2a07530 .delay (20000,20000,20000) L_0x2a07530/d;
+L_0x2a07640/d .functor AND 1, L_0x2a05b00, L_0x2a07910, C4<1>, C4<1>;
+L_0x2a07640 .delay (20000,20000,20000) L_0x2a07640/d;
+L_0x2a07790/d .functor OR 1, L_0x2a07530, L_0x2a07640, C4<0>, C4<0>;
+L_0x2a07790 .delay (20000,20000,20000) L_0x2a07790/d;
+v0x28ab940_0 .net "S", 0 0, L_0x2a07910; 1 drivers
+v0x28aba00_0 .alias "in0", 0 0, v0x28ac030_0;
+v0x28abaa0_0 .alias "in1", 0 0, v0x28abf00_0;
+v0x28abb40_0 .net "nS", 0 0, L_0x2a07470; 1 drivers
+v0x28abbc0_0 .net "out0", 0 0, L_0x2a07530; 1 drivers
+v0x28abc60_0 .net "out1", 0 0, L_0x2a07640; 1 drivers
+v0x28abd40_0 .alias "outfinal", 0 0, v0x28ac260_0;
+S_0x28ab300 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28ab210;
+ .timescale -9 -12;
+L_0x2a079b0/d .functor NOT 1, L_0x2a07ee0, C4<0>, C4<0>, C4<0>;
+L_0x2a079b0 .delay (10000,10000,10000) L_0x2a079b0/d;
+L_0x2a07a70/d .functor AND 1, L_0x2a07790, L_0x2a079b0, C4<1>, C4<1>;
+L_0x2a07a70 .delay (20000,20000,20000) L_0x2a07a70/d;
+L_0x2a07bc0/d .functor AND 1, L_0x2a05bf0, L_0x2a07ee0, C4<1>, C4<1>;
+L_0x2a07bc0 .delay (20000,20000,20000) L_0x2a07bc0/d;
+L_0x2a07d10/d .functor OR 1, L_0x2a07a70, L_0x2a07bc0, C4<0>, C4<0>;
+L_0x2a07d10 .delay (20000,20000,20000) L_0x2a07d10/d;
+v0x28ab3f0_0 .net "S", 0 0, L_0x2a07ee0; 1 drivers
+v0x28ab470_0 .alias "in0", 0 0, v0x28ac260_0;
+v0x28ab510_0 .alias "in1", 0 0, v0x28abfb0_0;
+v0x28ab5b0_0 .net "nS", 0 0, L_0x2a079b0; 1 drivers
+v0x28ab630_0 .net "out0", 0 0, L_0x2a07a70; 1 drivers
+v0x28ab6d0_0 .net "out1", 0 0, L_0x2a07bc0; 1 drivers
+v0x28ab7b0_0 .alias "outfinal", 0 0, v0x28ac1b0_0;
+S_0x28a9d10 .scope generate, "orbits[25]" "orbits[25]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a9a28 .param/l "i" 3 258, +C4<011001>;
+S_0x28a9e40 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a9d10;
+ .timescale -9 -12;
+L_0x2a06f40/d .functor NOR 1, L_0x2a09320, L_0x2a08020, C4<0>, C4<0>;
+L_0x2a06f40 .delay (10000,10000,10000) L_0x2a06f40/d;
+L_0x2a08270/d .functor NOT 1, L_0x2a06f40, C4<0>, C4<0>, C4<0>;
+L_0x2a08270 .delay (10000,10000,10000) L_0x2a08270/d;
+L_0x2a083a0/d .functor NAND 1, L_0x2a09320, L_0x2a08020, C4<1>, C4<1>;
+L_0x2a083a0 .delay (10000,10000,10000) L_0x2a083a0/d;
+L_0x2a08500/d .functor NAND 1, L_0x2a083a0, L_0x2a08270, C4<1>, C4<1>;
+L_0x2a08500 .delay (10000,10000,10000) L_0x2a08500/d;
+L_0x2a08610/d .functor NOT 1, L_0x2a08500, C4<0>, C4<0>, C4<0>;
+L_0x2a08610 .delay (10000,10000,10000) L_0x2a08610/d;
+v0x28aa9f0_0 .net "A", 0 0, L_0x2a09320; 1 drivers
+v0x28aaa90_0 .net "AnandB", 0 0, L_0x2a083a0; 1 drivers
+v0x28aab30_0 .net "AnorB", 0 0, L_0x2a06f40; 1 drivers
+v0x28aabe0_0 .net "AorB", 0 0, L_0x2a08270; 1 drivers
+v0x28aacc0_0 .net "AxorB", 0 0, L_0x2a08610; 1 drivers
+v0x28aad70_0 .net "B", 0 0, L_0x2a08020; 1 drivers
+v0x28aae30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28aaeb0_0 .net "OrNorXorOut", 0 0, L_0x2a09010; 1 drivers
+v0x28aaf30_0 .net "XorNor", 0 0, L_0x2a08a90; 1 drivers
+v0x28ab000_0 .net "nXor", 0 0, L_0x2a08500; 1 drivers
+L_0x2a08c10 .part v0x2960210_0, 2, 1;
+L_0x2a091e0 .part v0x2960210_0, 0, 1;
+S_0x28aa480 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a9e40;
+ .timescale -9 -12;
+L_0x2a08770/d .functor NOT 1, L_0x2a08c10, C4<0>, C4<0>, C4<0>;
+L_0x2a08770 .delay (10000,10000,10000) L_0x2a08770/d;
+L_0x2a08830/d .functor AND 1, L_0x2a08610, L_0x2a08770, C4<1>, C4<1>;
+L_0x2a08830 .delay (20000,20000,20000) L_0x2a08830/d;
+L_0x2a08940/d .functor AND 1, L_0x2a06f40, L_0x2a08c10, C4<1>, C4<1>;
+L_0x2a08940 .delay (20000,20000,20000) L_0x2a08940/d;
+L_0x2a08a90/d .functor OR 1, L_0x2a08830, L_0x2a08940, C4<0>, C4<0>;
+L_0x2a08a90 .delay (20000,20000,20000) L_0x2a08a90/d;
+v0x28aa570_0 .net "S", 0 0, L_0x2a08c10; 1 drivers
+v0x28aa630_0 .alias "in0", 0 0, v0x28aacc0_0;
+v0x28aa6d0_0 .alias "in1", 0 0, v0x28aab30_0;
+v0x28aa770_0 .net "nS", 0 0, L_0x2a08770; 1 drivers
+v0x28aa7f0_0 .net "out0", 0 0, L_0x2a08830; 1 drivers
+v0x28aa890_0 .net "out1", 0 0, L_0x2a08940; 1 drivers
+v0x28aa970_0 .alias "outfinal", 0 0, v0x28aaf30_0;
+S_0x28a9f30 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a9e40;
+ .timescale -9 -12;
+L_0x2a08cb0/d .functor NOT 1, L_0x2a091e0, C4<0>, C4<0>, C4<0>;
+L_0x2a08cb0 .delay (10000,10000,10000) L_0x2a08cb0/d;
+L_0x2a08d70/d .functor AND 1, L_0x2a08a90, L_0x2a08cb0, C4<1>, C4<1>;
+L_0x2a08d70 .delay (20000,20000,20000) L_0x2a08d70/d;
+L_0x2a08ec0/d .functor AND 1, L_0x2a08270, L_0x2a091e0, C4<1>, C4<1>;
+L_0x2a08ec0 .delay (20000,20000,20000) L_0x2a08ec0/d;
+L_0x2a09010/d .functor OR 1, L_0x2a08d70, L_0x2a08ec0, C4<0>, C4<0>;
+L_0x2a09010 .delay (20000,20000,20000) L_0x2a09010/d;
+v0x28aa020_0 .net "S", 0 0, L_0x2a091e0; 1 drivers
+v0x28aa0a0_0 .alias "in0", 0 0, v0x28aaf30_0;
+v0x28aa140_0 .alias "in1", 0 0, v0x28aabe0_0;
+v0x28aa1e0_0 .net "nS", 0 0, L_0x2a08cb0; 1 drivers
+v0x28aa260_0 .net "out0", 0 0, L_0x2a08d70; 1 drivers
+v0x28aa300_0 .net "out1", 0 0, L_0x2a08ec0; 1 drivers
+v0x28aa3e0_0 .alias "outfinal", 0 0, v0x28aaeb0_0;
+S_0x28a8940 .scope generate, "orbits[26]" "orbits[26]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a8658 .param/l "i" 3 258, +C4<011010>;
+S_0x28a8a70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a8940;
+ .timescale -9 -12;
+L_0x2a080c0/d .functor NOR 1, L_0x2a093c0, L_0x2a09460, C4<0>, C4<0>;
+L_0x2a080c0 .delay (10000,10000,10000) L_0x2a080c0/d;
+L_0x2a081b0/d .functor NOT 1, L_0x2a080c0, C4<0>, C4<0>, C4<0>;
+L_0x2a081b0 .delay (10000,10000,10000) L_0x2a081b0/d;
+L_0x2a09690/d .functor NAND 1, L_0x2a093c0, L_0x2a09460, C4<1>, C4<1>;
+L_0x2a09690 .delay (10000,10000,10000) L_0x2a09690/d;
+L_0x2a097f0/d .functor NAND 1, L_0x2a09690, L_0x2a081b0, C4<1>, C4<1>;
+L_0x2a097f0 .delay (10000,10000,10000) L_0x2a097f0/d;
+L_0x2a09900/d .functor NOT 1, L_0x2a097f0, C4<0>, C4<0>, C4<0>;
+L_0x2a09900 .delay (10000,10000,10000) L_0x2a09900/d;
+v0x28a9620_0 .net "A", 0 0, L_0x2a093c0; 1 drivers
+v0x28a96c0_0 .net "AnandB", 0 0, L_0x2a09690; 1 drivers
+v0x28a9760_0 .net "AnorB", 0 0, L_0x2a080c0; 1 drivers
+v0x28a9810_0 .net "AorB", 0 0, L_0x2a081b0; 1 drivers
+v0x28a98f0_0 .net "AxorB", 0 0, L_0x2a09900; 1 drivers
+v0x28a99a0_0 .net "B", 0 0, L_0x2a09460; 1 drivers
+v0x28a9a60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a9ae0_0 .net "OrNorXorOut", 0 0, L_0x2a0a300; 1 drivers
+v0x28a9b60_0 .net "XorNor", 0 0, L_0x2a09d80; 1 drivers
+v0x28a9c30_0 .net "nXor", 0 0, L_0x2a097f0; 1 drivers
+L_0x2a09f00 .part v0x2960210_0, 2, 1;
+L_0x2a0a4d0 .part v0x2960210_0, 0, 1;
+S_0x28a90b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a8a70;
+ .timescale -9 -12;
+L_0x2a09a60/d .functor NOT 1, L_0x2a09f00, C4<0>, C4<0>, C4<0>;
+L_0x2a09a60 .delay (10000,10000,10000) L_0x2a09a60/d;
+L_0x2a09b20/d .functor AND 1, L_0x2a09900, L_0x2a09a60, C4<1>, C4<1>;
+L_0x2a09b20 .delay (20000,20000,20000) L_0x2a09b20/d;
+L_0x2a09c30/d .functor AND 1, L_0x2a080c0, L_0x2a09f00, C4<1>, C4<1>;
+L_0x2a09c30 .delay (20000,20000,20000) L_0x2a09c30/d;
+L_0x2a09d80/d .functor OR 1, L_0x2a09b20, L_0x2a09c30, C4<0>, C4<0>;
+L_0x2a09d80 .delay (20000,20000,20000) L_0x2a09d80/d;
+v0x28a91a0_0 .net "S", 0 0, L_0x2a09f00; 1 drivers
+v0x28a9260_0 .alias "in0", 0 0, v0x28a98f0_0;
+v0x28a9300_0 .alias "in1", 0 0, v0x28a9760_0;
+v0x28a93a0_0 .net "nS", 0 0, L_0x2a09a60; 1 drivers
+v0x28a9420_0 .net "out0", 0 0, L_0x2a09b20; 1 drivers
+v0x28a94c0_0 .net "out1", 0 0, L_0x2a09c30; 1 drivers
+v0x28a95a0_0 .alias "outfinal", 0 0, v0x28a9b60_0;
+S_0x28a8b60 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a8a70;
+ .timescale -9 -12;
+L_0x2a09fa0/d .functor NOT 1, L_0x2a0a4d0, C4<0>, C4<0>, C4<0>;
+L_0x2a09fa0 .delay (10000,10000,10000) L_0x2a09fa0/d;
+L_0x2a0a060/d .functor AND 1, L_0x2a09d80, L_0x2a09fa0, C4<1>, C4<1>;
+L_0x2a0a060 .delay (20000,20000,20000) L_0x2a0a060/d;
+L_0x2a0a1b0/d .functor AND 1, L_0x2a081b0, L_0x2a0a4d0, C4<1>, C4<1>;
+L_0x2a0a1b0 .delay (20000,20000,20000) L_0x2a0a1b0/d;
+L_0x2a0a300/d .functor OR 1, L_0x2a0a060, L_0x2a0a1b0, C4<0>, C4<0>;
+L_0x2a0a300 .delay (20000,20000,20000) L_0x2a0a300/d;
+v0x28a8c50_0 .net "S", 0 0, L_0x2a0a4d0; 1 drivers
+v0x28a8cd0_0 .alias "in0", 0 0, v0x28a9b60_0;
+v0x28a8d70_0 .alias "in1", 0 0, v0x28a9810_0;
+v0x28a8e10_0 .net "nS", 0 0, L_0x2a09fa0; 1 drivers
+v0x28a8e90_0 .net "out0", 0 0, L_0x2a0a060; 1 drivers
+v0x28a8f30_0 .net "out1", 0 0, L_0x2a0a1b0; 1 drivers
+v0x28a9010_0 .alias "outfinal", 0 0, v0x28a9ae0_0;
+S_0x28a7570 .scope generate, "orbits[27]" "orbits[27]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a7288 .param/l "i" 3 258, +C4<011011>;
+S_0x28a76a0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a7570;
+ .timescale -9 -12;
+L_0x2a09500/d .functor NOR 1, L_0x2a0b920, L_0x2a0a610, C4<0>, C4<0>;
+L_0x2a09500 .delay (10000,10000,10000) L_0x2a09500/d;
+L_0x2a0a890/d .functor NOT 1, L_0x2a09500, C4<0>, C4<0>, C4<0>;
+L_0x2a0a890 .delay (10000,10000,10000) L_0x2a0a890/d;
+L_0x2a0a9a0/d .functor NAND 1, L_0x2a0b920, L_0x2a0a610, C4<1>, C4<1>;
+L_0x2a0a9a0 .delay (10000,10000,10000) L_0x2a0a9a0/d;
+L_0x2a0ab00/d .functor NAND 1, L_0x2a0a9a0, L_0x2a0a890, C4<1>, C4<1>;
+L_0x2a0ab00 .delay (10000,10000,10000) L_0x2a0ab00/d;
+L_0x2a0ac10/d .functor NOT 1, L_0x2a0ab00, C4<0>, C4<0>, C4<0>;
+L_0x2a0ac10 .delay (10000,10000,10000) L_0x2a0ac10/d;
+v0x28a8250_0 .net "A", 0 0, L_0x2a0b920; 1 drivers
+v0x28a82f0_0 .net "AnandB", 0 0, L_0x2a0a9a0; 1 drivers
+v0x28a8390_0 .net "AnorB", 0 0, L_0x2a09500; 1 drivers
+v0x28a8440_0 .net "AorB", 0 0, L_0x2a0a890; 1 drivers
+v0x28a8520_0 .net "AxorB", 0 0, L_0x2a0ac10; 1 drivers
+v0x28a85d0_0 .net "B", 0 0, L_0x2a0a610; 1 drivers
+v0x28a8690_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a8710_0 .net "OrNorXorOut", 0 0, L_0x2a0b610; 1 drivers
+v0x28a8790_0 .net "XorNor", 0 0, L_0x2a0b090; 1 drivers
+v0x28a8860_0 .net "nXor", 0 0, L_0x2a0ab00; 1 drivers
+L_0x2a0b210 .part v0x2960210_0, 2, 1;
+L_0x2a0b7e0 .part v0x2960210_0, 0, 1;
+S_0x28a7ce0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a76a0;
+ .timescale -9 -12;
+L_0x2a0ad70/d .functor NOT 1, L_0x2a0b210, C4<0>, C4<0>, C4<0>;
+L_0x2a0ad70 .delay (10000,10000,10000) L_0x2a0ad70/d;
+L_0x2a0ae30/d .functor AND 1, L_0x2a0ac10, L_0x2a0ad70, C4<1>, C4<1>;
+L_0x2a0ae30 .delay (20000,20000,20000) L_0x2a0ae30/d;
+L_0x2a0af40/d .functor AND 1, L_0x2a09500, L_0x2a0b210, C4<1>, C4<1>;
+L_0x2a0af40 .delay (20000,20000,20000) L_0x2a0af40/d;
+L_0x2a0b090/d .functor OR 1, L_0x2a0ae30, L_0x2a0af40, C4<0>, C4<0>;
+L_0x2a0b090 .delay (20000,20000,20000) L_0x2a0b090/d;
+v0x28a7dd0_0 .net "S", 0 0, L_0x2a0b210; 1 drivers
+v0x28a7e90_0 .alias "in0", 0 0, v0x28a8520_0;
+v0x28a7f30_0 .alias "in1", 0 0, v0x28a8390_0;
+v0x28a7fd0_0 .net "nS", 0 0, L_0x2a0ad70; 1 drivers
+v0x28a8050_0 .net "out0", 0 0, L_0x2a0ae30; 1 drivers
+v0x28a80f0_0 .net "out1", 0 0, L_0x2a0af40; 1 drivers
+v0x28a81d0_0 .alias "outfinal", 0 0, v0x28a8790_0;
+S_0x28a7790 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a76a0;
+ .timescale -9 -12;
+L_0x2a0b2b0/d .functor NOT 1, L_0x2a0b7e0, C4<0>, C4<0>, C4<0>;
+L_0x2a0b2b0 .delay (10000,10000,10000) L_0x2a0b2b0/d;
+L_0x2a0b370/d .functor AND 1, L_0x2a0b090, L_0x2a0b2b0, C4<1>, C4<1>;
+L_0x2a0b370 .delay (20000,20000,20000) L_0x2a0b370/d;
+L_0x2a0b4c0/d .functor AND 1, L_0x2a0a890, L_0x2a0b7e0, C4<1>, C4<1>;
+L_0x2a0b4c0 .delay (20000,20000,20000) L_0x2a0b4c0/d;
+L_0x2a0b610/d .functor OR 1, L_0x2a0b370, L_0x2a0b4c0, C4<0>, C4<0>;
+L_0x2a0b610 .delay (20000,20000,20000) L_0x2a0b610/d;
+v0x28a7880_0 .net "S", 0 0, L_0x2a0b7e0; 1 drivers
+v0x28a7900_0 .alias "in0", 0 0, v0x28a8790_0;
+v0x28a79a0_0 .alias "in1", 0 0, v0x28a8440_0;
+v0x28a7a40_0 .net "nS", 0 0, L_0x2a0b2b0; 1 drivers
+v0x28a7ac0_0 .net "out0", 0 0, L_0x2a0b370; 1 drivers
+v0x28a7b60_0 .net "out1", 0 0, L_0x2a0b4c0; 1 drivers
+v0x28a7c40_0 .alias "outfinal", 0 0, v0x28a8710_0;
+S_0x28a61a0 .scope generate, "orbits[28]" "orbits[28]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a5eb8 .param/l "i" 3 258, +C4<011100>;
+S_0x28a62d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a61a0;
+ .timescale -9 -12;
+L_0x2a0a6b0/d .functor NOR 1, L_0x2a0b9c0, L_0x2a0ba60, C4<0>, C4<0>;
+L_0x2a0a6b0 .delay (10000,10000,10000) L_0x2a0a6b0/d;
+L_0x2a0a7a0/d .functor NOT 1, L_0x2a0a6b0, C4<0>, C4<0>, C4<0>;
+L_0x2a0a7a0 .delay (10000,10000,10000) L_0x2a0a7a0/d;
+L_0x2a0bca0/d .functor NAND 1, L_0x2a0b9c0, L_0x2a0ba60, C4<1>, C4<1>;
+L_0x2a0bca0 .delay (10000,10000,10000) L_0x2a0bca0/d;
+L_0x2a0be00/d .functor NAND 1, L_0x2a0bca0, L_0x2a0a7a0, C4<1>, C4<1>;
+L_0x2a0be00 .delay (10000,10000,10000) L_0x2a0be00/d;
+L_0x2a0bf10/d .functor NOT 1, L_0x2a0be00, C4<0>, C4<0>, C4<0>;
+L_0x2a0bf10 .delay (10000,10000,10000) L_0x2a0bf10/d;
+v0x28a6e80_0 .net "A", 0 0, L_0x2a0b9c0; 1 drivers
+v0x28a6f20_0 .net "AnandB", 0 0, L_0x2a0bca0; 1 drivers
+v0x28a6fc0_0 .net "AnorB", 0 0, L_0x2a0a6b0; 1 drivers
+v0x28a7070_0 .net "AorB", 0 0, L_0x2a0a7a0; 1 drivers
+v0x28a7150_0 .net "AxorB", 0 0, L_0x2a0bf10; 1 drivers
+v0x28a7200_0 .net "B", 0 0, L_0x2a0ba60; 1 drivers
+v0x28a72c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a7340_0 .net "OrNorXorOut", 0 0, L_0x2a0c910; 1 drivers
+v0x28a73c0_0 .net "XorNor", 0 0, L_0x2a0c390; 1 drivers
+v0x28a7490_0 .net "nXor", 0 0, L_0x2a0be00; 1 drivers
+L_0x2a0c510 .part v0x2960210_0, 2, 1;
+L_0x2a0cae0 .part v0x2960210_0, 0, 1;
+S_0x28a6910 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a62d0;
+ .timescale -9 -12;
+L_0x2a0c070/d .functor NOT 1, L_0x2a0c510, C4<0>, C4<0>, C4<0>;
+L_0x2a0c070 .delay (10000,10000,10000) L_0x2a0c070/d;
+L_0x2a0c130/d .functor AND 1, L_0x2a0bf10, L_0x2a0c070, C4<1>, C4<1>;
+L_0x2a0c130 .delay (20000,20000,20000) L_0x2a0c130/d;
+L_0x2a0c240/d .functor AND 1, L_0x2a0a6b0, L_0x2a0c510, C4<1>, C4<1>;
+L_0x2a0c240 .delay (20000,20000,20000) L_0x2a0c240/d;
+L_0x2a0c390/d .functor OR 1, L_0x2a0c130, L_0x2a0c240, C4<0>, C4<0>;
+L_0x2a0c390 .delay (20000,20000,20000) L_0x2a0c390/d;
+v0x28a6a00_0 .net "S", 0 0, L_0x2a0c510; 1 drivers
+v0x28a6ac0_0 .alias "in0", 0 0, v0x28a7150_0;
+v0x28a6b60_0 .alias "in1", 0 0, v0x28a6fc0_0;
+v0x28a6c00_0 .net "nS", 0 0, L_0x2a0c070; 1 drivers
+v0x28a6c80_0 .net "out0", 0 0, L_0x2a0c130; 1 drivers
+v0x28a6d20_0 .net "out1", 0 0, L_0x2a0c240; 1 drivers
+v0x28a6e00_0 .alias "outfinal", 0 0, v0x28a73c0_0;
+S_0x28a63c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a62d0;
+ .timescale -9 -12;
+L_0x2a0c5b0/d .functor NOT 1, L_0x2a0cae0, C4<0>, C4<0>, C4<0>;
+L_0x2a0c5b0 .delay (10000,10000,10000) L_0x2a0c5b0/d;
+L_0x2a0c670/d .functor AND 1, L_0x2a0c390, L_0x2a0c5b0, C4<1>, C4<1>;
+L_0x2a0c670 .delay (20000,20000,20000) L_0x2a0c670/d;
+L_0x2a0c7c0/d .functor AND 1, L_0x2a0a7a0, L_0x2a0cae0, C4<1>, C4<1>;
+L_0x2a0c7c0 .delay (20000,20000,20000) L_0x2a0c7c0/d;
+L_0x2a0c910/d .functor OR 1, L_0x2a0c670, L_0x2a0c7c0, C4<0>, C4<0>;
+L_0x2a0c910 .delay (20000,20000,20000) L_0x2a0c910/d;
+v0x28a64b0_0 .net "S", 0 0, L_0x2a0cae0; 1 drivers
+v0x28a6530_0 .alias "in0", 0 0, v0x28a73c0_0;
+v0x28a65d0_0 .alias "in1", 0 0, v0x28a7070_0;
+v0x28a6670_0 .net "nS", 0 0, L_0x2a0c5b0; 1 drivers
+v0x28a66f0_0 .net "out0", 0 0, L_0x2a0c670; 1 drivers
+v0x28a6790_0 .net "out1", 0 0, L_0x2a0c7c0; 1 drivers
+v0x28a6870_0 .alias "outfinal", 0 0, v0x28a7340_0;
+S_0x28a4dd0 .scope generate, "orbits[29]" "orbits[29]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a4ae8 .param/l "i" 3 258, +C4<011101>;
+S_0x28a4f00 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a4dd0;
+ .timescale -9 -12;
+L_0x2a0bb00/d .functor NOR 1, L_0x29f9f90, L_0x29fa030, C4<0>, C4<0>;
+L_0x2a0bb00 .delay (10000,10000,10000) L_0x2a0bb00/d;
+L_0x2a0bbf0/d .functor NOT 1, L_0x2a0bb00, C4<0>, C4<0>, C4<0>;
+L_0x2a0bbf0 .delay (10000,10000,10000) L_0x2a0bbf0/d;
+L_0x2a0cfa0/d .functor NAND 1, L_0x29f9f90, L_0x29fa030, C4<1>, C4<1>;
+L_0x2a0cfa0 .delay (10000,10000,10000) L_0x2a0cfa0/d;
+L_0x2a0d100/d .functor NAND 1, L_0x2a0cfa0, L_0x2a0bbf0, C4<1>, C4<1>;
+L_0x2a0d100 .delay (10000,10000,10000) L_0x2a0d100/d;
+L_0x2a0d210/d .functor NOT 1, L_0x2a0d100, C4<0>, C4<0>, C4<0>;
+L_0x2a0d210 .delay (10000,10000,10000) L_0x2a0d210/d;
+v0x28a5ab0_0 .net "A", 0 0, L_0x29f9f90; 1 drivers
+v0x28a5b50_0 .net "AnandB", 0 0, L_0x2a0cfa0; 1 drivers
+v0x28a5bf0_0 .net "AnorB", 0 0, L_0x2a0bb00; 1 drivers
+v0x28a5ca0_0 .net "AorB", 0 0, L_0x2a0bbf0; 1 drivers
+v0x28a5d80_0 .net "AxorB", 0 0, L_0x2a0d210; 1 drivers
+v0x28a5e30_0 .net "B", 0 0, L_0x29fa030; 1 drivers
+v0x28a5ef0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a5f70_0 .net "OrNorXorOut", 0 0, L_0x2a0dc10; 1 drivers
+v0x28a5ff0_0 .net "XorNor", 0 0, L_0x2a0d690; 1 drivers
+v0x28a60c0_0 .net "nXor", 0 0, L_0x2a0d100; 1 drivers
+L_0x2a0d810 .part v0x2960210_0, 2, 1;
+L_0x2a0dde0 .part v0x2960210_0, 0, 1;
+S_0x28a5540 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a4f00;
+ .timescale -9 -12;
+L_0x2a0d370/d .functor NOT 1, L_0x2a0d810, C4<0>, C4<0>, C4<0>;
+L_0x2a0d370 .delay (10000,10000,10000) L_0x2a0d370/d;
+L_0x2a0d430/d .functor AND 1, L_0x2a0d210, L_0x2a0d370, C4<1>, C4<1>;
+L_0x2a0d430 .delay (20000,20000,20000) L_0x2a0d430/d;
+L_0x2a0d540/d .functor AND 1, L_0x2a0bb00, L_0x2a0d810, C4<1>, C4<1>;
+L_0x2a0d540 .delay (20000,20000,20000) L_0x2a0d540/d;
+L_0x2a0d690/d .functor OR 1, L_0x2a0d430, L_0x2a0d540, C4<0>, C4<0>;
+L_0x2a0d690 .delay (20000,20000,20000) L_0x2a0d690/d;
+v0x28a5630_0 .net "S", 0 0, L_0x2a0d810; 1 drivers
+v0x28a56f0_0 .alias "in0", 0 0, v0x28a5d80_0;
+v0x28a5790_0 .alias "in1", 0 0, v0x28a5bf0_0;
+v0x28a5830_0 .net "nS", 0 0, L_0x2a0d370; 1 drivers
+v0x28a58b0_0 .net "out0", 0 0, L_0x2a0d430; 1 drivers
+v0x28a5950_0 .net "out1", 0 0, L_0x2a0d540; 1 drivers
+v0x28a5a30_0 .alias "outfinal", 0 0, v0x28a5ff0_0;
+S_0x28a4ff0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a4f00;
+ .timescale -9 -12;
+L_0x2a0d8b0/d .functor NOT 1, L_0x2a0dde0, C4<0>, C4<0>, C4<0>;
+L_0x2a0d8b0 .delay (10000,10000,10000) L_0x2a0d8b0/d;
+L_0x2a0d970/d .functor AND 1, L_0x2a0d690, L_0x2a0d8b0, C4<1>, C4<1>;
+L_0x2a0d970 .delay (20000,20000,20000) L_0x2a0d970/d;
+L_0x2a0dac0/d .functor AND 1, L_0x2a0bbf0, L_0x2a0dde0, C4<1>, C4<1>;
+L_0x2a0dac0 .delay (20000,20000,20000) L_0x2a0dac0/d;
+L_0x2a0dc10/d .functor OR 1, L_0x2a0d970, L_0x2a0dac0, C4<0>, C4<0>;
+L_0x2a0dc10 .delay (20000,20000,20000) L_0x2a0dc10/d;
+v0x28a50e0_0 .net "S", 0 0, L_0x2a0dde0; 1 drivers
+v0x28a5160_0 .alias "in0", 0 0, v0x28a5ff0_0;
+v0x28a5200_0 .alias "in1", 0 0, v0x28a5ca0_0;
+v0x28a52a0_0 .net "nS", 0 0, L_0x2a0d8b0; 1 drivers
+v0x28a5320_0 .net "out0", 0 0, L_0x2a0d970; 1 drivers
+v0x28a53c0_0 .net "out1", 0 0, L_0x2a0dac0; 1 drivers
+v0x28a54a0_0 .alias "outfinal", 0 0, v0x28a5f70_0;
+S_0x28a3a00 .scope generate, "orbits[30]" "orbits[30]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a3728 .param/l "i" 3 258, +C4<011110>;
+S_0x28a3b30 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a3a00;
+ .timescale -9 -12;
+L_0x29fa0d0/d .functor NOR 1, L_0x2a0e330, L_0x2a0e3d0, C4<0>, C4<0>;
+L_0x29fa0d0 .delay (10000,10000,10000) L_0x29fa0d0/d;
+L_0x2a0cc70/d .functor NOT 1, L_0x29fa0d0, C4<0>, C4<0>, C4<0>;
+L_0x2a0cc70 .delay (10000,10000,10000) L_0x2a0cc70/d;
+L_0x2a0cda0/d .functor NAND 1, L_0x2a0e330, L_0x2a0e3d0, C4<1>, C4<1>;
+L_0x2a0cda0 .delay (10000,10000,10000) L_0x2a0cda0/d;
+L_0x2a0e640/d .functor NAND 1, L_0x2a0cda0, L_0x2a0cc70, C4<1>, C4<1>;
+L_0x2a0e640 .delay (10000,10000,10000) L_0x2a0e640/d;
+L_0x2a0e730/d .functor NOT 1, L_0x2a0e640, C4<0>, C4<0>, C4<0>;
+L_0x2a0e730 .delay (10000,10000,10000) L_0x2a0e730/d;
+v0x28a46e0_0 .net "A", 0 0, L_0x2a0e330; 1 drivers
+v0x28a4780_0 .net "AnandB", 0 0, L_0x2a0cda0; 1 drivers
+v0x28a4820_0 .net "AnorB", 0 0, L_0x29fa0d0; 1 drivers
+v0x28a48d0_0 .net "AorB", 0 0, L_0x2a0cc70; 1 drivers
+v0x28a49b0_0 .net "AxorB", 0 0, L_0x2a0e730; 1 drivers
+v0x28a4a60_0 .net "B", 0 0, L_0x2a0e3d0; 1 drivers
+v0x28a4b20_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a4ba0_0 .net "OrNorXorOut", 0 0, L_0x2a0f010; 1 drivers
+v0x28a4c20_0 .net "XorNor", 0 0, L_0x2a0eb30; 1 drivers
+v0x28a4cf0_0 .net "nXor", 0 0, L_0x2a0e640; 1 drivers
+L_0x2a0ec70 .part v0x2960210_0, 2, 1;
+L_0x2a0f1a0 .part v0x2960210_0, 0, 1;
+S_0x28a4170 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a3b30;
+ .timescale -9 -12;
+L_0x2a0e870/d .functor NOT 1, L_0x2a0ec70, C4<0>, C4<0>, C4<0>;
+L_0x2a0e870 .delay (10000,10000,10000) L_0x2a0e870/d;
+L_0x2a0e910/d .functor AND 1, L_0x2a0e730, L_0x2a0e870, C4<1>, C4<1>;
+L_0x2a0e910 .delay (20000,20000,20000) L_0x2a0e910/d;
+L_0x2a0ea00/d .functor AND 1, L_0x29fa0d0, L_0x2a0ec70, C4<1>, C4<1>;
+L_0x2a0ea00 .delay (20000,20000,20000) L_0x2a0ea00/d;
+L_0x2a0eb30/d .functor OR 1, L_0x2a0e910, L_0x2a0ea00, C4<0>, C4<0>;
+L_0x2a0eb30 .delay (20000,20000,20000) L_0x2a0eb30/d;
+v0x28a4260_0 .net "S", 0 0, L_0x2a0ec70; 1 drivers
+v0x28a4320_0 .alias "in0", 0 0, v0x28a49b0_0;
+v0x28a43c0_0 .alias "in1", 0 0, v0x28a4820_0;
+v0x28a4460_0 .net "nS", 0 0, L_0x2a0e870; 1 drivers
+v0x28a44e0_0 .net "out0", 0 0, L_0x2a0e910; 1 drivers
+v0x28a4580_0 .net "out1", 0 0, L_0x2a0ea00; 1 drivers
+v0x28a4660_0 .alias "outfinal", 0 0, v0x28a4c20_0;
+S_0x28a3c20 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a3b30;
+ .timescale -9 -12;
+L_0x2a0ed10/d .functor NOT 1, L_0x2a0f1a0, C4<0>, C4<0>, C4<0>;
+L_0x2a0ed10 .delay (10000,10000,10000) L_0x2a0ed10/d;
+L_0x2a0edb0/d .functor AND 1, L_0x2a0eb30, L_0x2a0ed10, C4<1>, C4<1>;
+L_0x2a0edb0 .delay (20000,20000,20000) L_0x2a0edb0/d;
+L_0x2a0eee0/d .functor AND 1, L_0x2a0cc70, L_0x2a0f1a0, C4<1>, C4<1>;
+L_0x2a0eee0 .delay (20000,20000,20000) L_0x2a0eee0/d;
+L_0x2a0f010/d .functor OR 1, L_0x2a0edb0, L_0x2a0eee0, C4<0>, C4<0>;
+L_0x2a0f010 .delay (20000,20000,20000) L_0x2a0f010/d;
+v0x28a3d10_0 .net "S", 0 0, L_0x2a0f1a0; 1 drivers
+v0x28a3d90_0 .alias "in0", 0 0, v0x28a4c20_0;
+v0x28a3e30_0 .alias "in1", 0 0, v0x28a48d0_0;
+v0x28a3ed0_0 .net "nS", 0 0, L_0x2a0ed10; 1 drivers
+v0x28a3f50_0 .net "out0", 0 0, L_0x2a0edb0; 1 drivers
+v0x28a3ff0_0 .net "out1", 0 0, L_0x2a0eee0; 1 drivers
+v0x28a40d0_0 .alias "outfinal", 0 0, v0x28a4ba0_0;
+S_0x28a2680 .scope generate, "orbits[31]" "orbits[31]" 3 258, 3 258, S_0x28a2590;
+ .timescale -9 -12;
+P_0x28a2208 .param/l "i" 3 258, +C4<011111>;
+S_0x28a27b0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28a2680;
+ .timescale -9 -12;
+L_0x2a0e470/d .functor NOR 1, L_0x2a105f0, L_0x2a0f2e0, C4<0>, C4<0>;
+L_0x2a0e470 .delay (10000,10000,10000) L_0x2a0e470/d;
+L_0x2a0e560/d .functor NOT 1, L_0x2a0e470, C4<0>, C4<0>, C4<0>;
+L_0x2a0e560 .delay (10000,10000,10000) L_0x2a0e560/d;
+L_0x2a0f670/d .functor NAND 1, L_0x2a105f0, L_0x2a0f2e0, C4<1>, C4<1>;
+L_0x2a0f670 .delay (10000,10000,10000) L_0x2a0f670/d;
+L_0x2a0f7d0/d .functor NAND 1, L_0x2a0f670, L_0x2a0e560, C4<1>, C4<1>;
+L_0x2a0f7d0 .delay (10000,10000,10000) L_0x2a0f7d0/d;
+L_0x2a0f8e0/d .functor NOT 1, L_0x2a0f7d0, C4<0>, C4<0>, C4<0>;
+L_0x2a0f8e0 .delay (10000,10000,10000) L_0x2a0f8e0/d;
+v0x28a3380_0 .net "A", 0 0, L_0x2a105f0; 1 drivers
+v0x28a3420_0 .net "AnandB", 0 0, L_0x2a0f670; 1 drivers
+v0x28a34c0_0 .net "AnorB", 0 0, L_0x2a0e470; 1 drivers
+v0x28a3540_0 .net "AorB", 0 0, L_0x2a0e560; 1 drivers
+v0x28a35f0_0 .net "AxorB", 0 0, L_0x2a0f8e0; 1 drivers
+v0x28a36a0_0 .net "B", 0 0, L_0x2a0f2e0; 1 drivers
+v0x28a3760_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a37e0_0 .net "OrNorXorOut", 0 0, L_0x2a102e0; 1 drivers
+v0x28a38b0_0 .net "XorNor", 0 0, L_0x2a0fd60; 1 drivers
+v0x28a3980_0 .net "nXor", 0 0, L_0x2a0f7d0; 1 drivers
+L_0x2a0fee0 .part v0x2960210_0, 2, 1;
+L_0x2a104b0 .part v0x2960210_0, 0, 1;
+S_0x28a2e10 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28a27b0;
+ .timescale -9 -12;
+L_0x2a0fa40/d .functor NOT 1, L_0x2a0fee0, C4<0>, C4<0>, C4<0>;
+L_0x2a0fa40 .delay (10000,10000,10000) L_0x2a0fa40/d;
+L_0x2a0fb00/d .functor AND 1, L_0x2a0f8e0, L_0x2a0fa40, C4<1>, C4<1>;
+L_0x2a0fb00 .delay (20000,20000,20000) L_0x2a0fb00/d;
+L_0x2a0fc10/d .functor AND 1, L_0x2a0e470, L_0x2a0fee0, C4<1>, C4<1>;
+L_0x2a0fc10 .delay (20000,20000,20000) L_0x2a0fc10/d;
+L_0x2a0fd60/d .functor OR 1, L_0x2a0fb00, L_0x2a0fc10, C4<0>, C4<0>;
+L_0x2a0fd60 .delay (20000,20000,20000) L_0x2a0fd60/d;
+v0x28a2f00_0 .net "S", 0 0, L_0x2a0fee0; 1 drivers
+v0x28a2fc0_0 .alias "in0", 0 0, v0x28a35f0_0;
+v0x28a3060_0 .alias "in1", 0 0, v0x28a34c0_0;
+v0x28a3100_0 .net "nS", 0 0, L_0x2a0fa40; 1 drivers
+v0x28a3180_0 .net "out0", 0 0, L_0x2a0fb00; 1 drivers
+v0x28a3220_0 .net "out1", 0 0, L_0x2a0fc10; 1 drivers
+v0x28a3300_0 .alias "outfinal", 0 0, v0x28a38b0_0;
+S_0x28a28a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28a27b0;
+ .timescale -9 -12;
+L_0x2a0ff80/d .functor NOT 1, L_0x2a104b0, C4<0>, C4<0>, C4<0>;
+L_0x2a0ff80 .delay (10000,10000,10000) L_0x2a0ff80/d;
+L_0x2a10040/d .functor AND 1, L_0x2a0fd60, L_0x2a0ff80, C4<1>, C4<1>;
+L_0x2a10040 .delay (20000,20000,20000) L_0x2a10040/d;
+L_0x2a10190/d .functor AND 1, L_0x2a0e560, L_0x2a104b0, C4<1>, C4<1>;
+L_0x2a10190 .delay (20000,20000,20000) L_0x2a10190/d;
+L_0x2a102e0/d .functor OR 1, L_0x2a10040, L_0x2a10190, C4<0>, C4<0>;
+L_0x2a102e0 .delay (20000,20000,20000) L_0x2a102e0/d;
+v0x28a2990_0 .net "S", 0 0, L_0x2a104b0; 1 drivers
+v0x28a2a30_0 .alias "in0", 0 0, v0x28a38b0_0;
+v0x28a2ad0_0 .alias "in1", 0 0, v0x28a3540_0;
+v0x28a2b70_0 .net "nS", 0 0, L_0x2a0ff80; 1 drivers
+v0x28a2bf0_0 .net "out0", 0 0, L_0x2a10040; 1 drivers
+v0x28a2c90_0 .net "out1", 0 0, L_0x2a10190; 1 drivers
+v0x28a2d70_0 .alias "outfinal", 0 0, v0x28a37e0_0;
+S_0x25e6a40 .scope module, "superalu" "Bitslice32" 2 162, 3 360, S_0x22efd20;
+ .timescale -9 -12;
+P_0x262f748 .param/l "size" 3 378, +C4<0100000>;
+L_0x2a3b100/d .functor AND 1, L_0x2a254f0, L_0x2a25590, C4<1>, C4<1>;
+L_0x2a3b100 .delay (20000,20000,20000) L_0x2a3b100/d;
+L_0x2a25680/d .functor NOT 1, L_0x2a25770, C4<0>, C4<0>, C4<0>;
+L_0x2a25680 .delay (10000,10000,10000) L_0x2a25680/d;
+L_0x2a25810/d .functor AND 1, L_0x2a25680, L_0x2a25680, C4<1>, C4<1>;
+L_0x2a25810 .delay (20000,20000,20000) L_0x2a25810/d;
+v0x28a00d0_0 .alias "A", 31 0, v0x295f580_0;
+v0x28a0320_0 .alias "AddSubSLTSum", 31 0, v0x295ff30_0;
+v0x28a03a0_0 .alias "AllZeros", 0 0, v0x295ffb0_0;
+v0x28a0420_0 .alias "AndNandOut", 31 0, v0x2960110_0;
+v0x28a04a0_0 .alias "B", 31 0, v0x295f6a0_0;
+RS_0x7f507e9b8f68/0/0 .resolv tri, L_0x2a12350, L_0x2a14d90, L_0x2a176b0, L_0x2a19f50;
+RS_0x7f507e9b8f68/0/4 .resolv tri, L_0x2a1ca10, L_0x2a1f2b0, L_0x2a21b30, L_0x2a243b0;
+RS_0x7f507e9b8f68/0/8 .resolv tri, L_0x2a26ed0, L_0x2a29720, L_0x2a2c300, L_0x2a2ea60;
+RS_0x7f507e9b8f68/0/12 .resolv tri, L_0x2a312b0, L_0x2a33a40, L_0x2a362a0, L_0x2a39330;
+RS_0x7f507e9b8f68/0/16 .resolv tri, L_0x2a3c3c0, L_0x2a3ebf0, L_0x2a41500, L_0x2a42f70;
+RS_0x7f507e9b8f68/0/20 .resolv tri, L_0x2a45510, L_0x2a48a90, L_0x2a4a1e0, L_0x2a4c7c0;
+RS_0x7f507e9b8f68/0/24 .resolv tri, L_0x2a4fe30, L_0x2a524e0, L_0x2a54bb0, L_0x2a57240;
+RS_0x7f507e9b8f68/0/28 .resolv tri, L_0x2a598b0, L_0x2a5c330, L_0x2a5d130, L_0x2b14240;
+RS_0x7f507e9b8f68/1/0 .resolv tri, RS_0x7f507e9b8f68/0/0, RS_0x7f507e9b8f68/0/4, RS_0x7f507e9b8f68/0/8, RS_0x7f507e9b8f68/0/12;
+RS_0x7f507e9b8f68/1/4 .resolv tri, RS_0x7f507e9b8f68/0/16, RS_0x7f507e9b8f68/0/20, RS_0x7f507e9b8f68/0/24, RS_0x7f507e9b8f68/0/28;
+RS_0x7f507e9b8f68 .resolv tri, RS_0x7f507e9b8f68/1/0, RS_0x7f507e9b8f68/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x28a0520_0 .net8 "Cmd0Start", 31 0, RS_0x7f507e9b8f68; 32 drivers
+RS_0x7f507e9b8f98/0/0 .resolv tri, L_0x2a13230, L_0x2a15c80, L_0x2a18560, L_0x2a1ae10;
+RS_0x7f507e9b8f98/0/4 .resolv tri, L_0x2a1d8c0, L_0x2a20170, L_0x2a229e0, L_0x2a251e0;
+RS_0x7f507e9b8f98/0/8 .resolv tri, L_0x2a27d80, L_0x2a2a5c0, L_0x2a2d160, L_0x2a2f920;
+RS_0x7f507e9b8f98/0/12 .resolv tri, L_0x2a32140, L_0x2a348d0, L_0x2a35ce0, L_0x2a3a1c0;
+RS_0x7f507e9b8f98/0/16 .resolv tri, L_0x2a3d270, L_0x2a3faf0, L_0x2a42330, L_0x2a43c20;
+RS_0x7f507e9b8f98/0/20 .resolv tri, L_0x2a46480, L_0x2a48570, L_0x2a4bec0, L_0x2a4e580;
+RS_0x7f507e9b8f98/0/24 .resolv tri, L_0x2a4f310, L_0x2a51db0, L_0x2a542a0, L_0x2a56ce0;
+RS_0x7f507e9b8f98/0/28 .resolv tri, L_0x2a59560, L_0x2a5bab0, L_0x2a5f760, L_0x2a62950;
+RS_0x7f507e9b8f98/1/0 .resolv tri, RS_0x7f507e9b8f98/0/0, RS_0x7f507e9b8f98/0/4, RS_0x7f507e9b8f98/0/8, RS_0x7f507e9b8f98/0/12;
+RS_0x7f507e9b8f98/1/4 .resolv tri, RS_0x7f507e9b8f98/0/16, RS_0x7f507e9b8f98/0/20, RS_0x7f507e9b8f98/0/24, RS_0x7f507e9b8f98/0/28;
+RS_0x7f507e9b8f98 .resolv tri, RS_0x7f507e9b8f98/1/0, RS_0x7f507e9b8f98/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x28a05a0_0 .net8 "Cmd1Start", 31 0, RS_0x7f507e9b8f98; 32 drivers
+v0x28a0620_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28a06f0_0 .alias "OneBitFinalOut", 31 0, v0x2960290_0;
+v0x28a0770_0 .alias "OrNorXorOut", 31 0, v0x29603c0_0;
+v0x28a07f0_0 .alias "SLTSum", 31 0, v0x2960440_0;
+v0x28a08a0_0 .alias "SLTflag", 0 0, v0x29604c0_0;
+v0x28a0920_0 .alias "ZeroFlag", 31 0, v0x29606c0_0;
+v0x28a09a0_0 .net *"_s121", 0 0, L_0x2a1e020; 1 drivers
+v0x28a0aa0_0 .net *"_s146", 0 0, L_0x2a20660; 1 drivers
+v0x28a0b20_0 .net *"_s171", 0 0, L_0x2a232a0; 1 drivers
+v0x28a0a20_0 .net *"_s196", 0 0, L_0x2a1bd80; 1 drivers
+v0x28a0c70_0 .net *"_s21", 0 0, L_0x2a142f0; 1 drivers
+v0x28a0d90_0 .net *"_s221", 0 0, L_0x2a280a0; 1 drivers
+v0x28a0e10_0 .net *"_s246", 0 0, L_0x2a2a970; 1 drivers
+v0x28a0cf0_0 .net *"_s271", 0 0, L_0x2a2d480; 1 drivers
+v0x28a0f40_0 .net *"_s296", 0 0, L_0x2a2fe10; 1 drivers
+v0x28a0e90_0 .net *"_s321", 0 0, L_0x2a32410; 1 drivers
+v0x28a1080_0 .net *"_s346", 0 0, L_0x2a34dc0; 1 drivers
+v0x28a0fe0_0 .net *"_s371", 0 0, L_0x2a375d0; 1 drivers
+v0x28a11d0_0 .net *"_s396", 0 0, L_0x2a39d70; 1 drivers
+v0x28a1120_0 .net *"_s421", 0 0, L_0x2a3d590; 1 drivers
+v0x28a1330_0 .net *"_s446", 0 0, L_0x2a3fcc0; 1 drivers
+v0x28a1270_0 .net *"_s46", 0 0, L_0x2a162d0; 1 drivers
+v0x28a14a0_0 .net *"_s471", 0 0, L_0x2a42470; 1 drivers
+v0x28a13b0_0 .net *"_s496", 0 0, L_0x2a44be0; 1 drivers
+v0x28a1620_0 .net *"_s521", 0 0, L_0x2a47170; 1 drivers
+v0x28a1520_0 .net *"_s546", 0 0, L_0x2a49710; 1 drivers
+v0x28a17b0_0 .net *"_s571", 0 0, L_0x2a4b6d0; 1 drivers
+v0x28a16a0_0 .net *"_s596", 0 0, L_0x2a4db30; 1 drivers
+v0x28a1950_0 .net *"_s621", 0 0, L_0x2a509b0; 1 drivers
+v0x28a1830_0 .net *"_s646", 0 0, L_0x2a52fd0; 1 drivers
+v0x28a18d0_0 .net *"_s671", 0 0, L_0x2a55550; 1 drivers
+v0x28a1b10_0 .net *"_s696", 0 0, L_0x2a57b60; 1 drivers
+v0x28a1b90_0 .net *"_s71", 0 0, L_0x2a19200; 1 drivers
+v0x28a19d0_0 .net *"_s721", 0 0, L_0x2a5a530; 1 drivers
+v0x28a1a70_0 .net *"_s746", 0 0, L_0x2a5c6f0; 1 drivers
+v0x28a1d70_0 .net *"_s771", 0 0, L_0x2a5e180; 1 drivers
+v0x28a1df0_0 .net *"_s811", 0 0, L_0x2a3b100; 1 drivers
+v0x28a1c10_0 .net *"_s814", 0 0, L_0x2a254f0; 1 drivers
+v0x28a1cb0_0 .net *"_s816", 0 0, L_0x2a25590; 1 drivers
+v0x28a1ff0_0 .net *"_s818", 0 0, L_0x2a25770; 1 drivers
+v0x28a2070_0 .net *"_s96", 0 0, L_0x2a16a00; 1 drivers
+v0x28a1e90_0 .alias "carryin", 31 0, v0x295fa50_0;
+v0x28a1f10_0 .alias "carryout", 0 0, v0x2960870_0;
+v0x28a2290_0 .alias "overflow", 0 0, v0x2960980_0;
+v0x28a2360_0 .alias "subtract", 31 0, v0x2960aa0_0;
+v0x28a2140_0 .net "yeszero", 0 0, L_0x2a25680; 1 drivers
+L_0x2a12350 .part/pv L_0x2a12140, 1, 1, 32;
+L_0x2a123f0 .part v0x2960210_0, 0, 1;
+L_0x2a12520 .part v0x2960210_0, 1, 1;
+L_0x2a12650 .part RS_0x7f507e9ad5c8, 1, 1;
+L_0x2a126f0 .part RS_0x7f507e9ad5c8, 1, 1;
+L_0x2a12790 .part RS_0x7f507e9a3368, 1, 1;
+L_0x2a128c0 .part RS_0x7f507e9b8c98, 1, 1;
+L_0x2a13230 .part/pv L_0x2a12ff0, 1, 1, 32;
+L_0x2a13320 .part v0x2960210_0, 0, 1;
+L_0x2a13450 .part v0x2960210_0, 1, 1;
+L_0x2a135e0 .part RS_0x7f507e9a6998, 1, 1;
+L_0x2a13680 .part RS_0x7f507e9a6998, 1, 1;
+L_0x2a13790 .part RS_0x7f507e9a3368, 1, 1;
+L_0x2a13830 .part RS_0x7f507e9a3368, 1, 1;
+L_0x2a13d10 .part/pv L_0x2a13bd0, 1, 1, 32;
+L_0x2a13e00 .part v0x2960210_0, 2, 1;
+L_0x2a13f30 .part RS_0x7f507e9b8f68, 1, 1;
+L_0x2a14070 .part RS_0x7f507e9b8f98, 1, 1;
+L_0x2a14250 .part/pv L_0x2a142f0, 1, 1, 32;
+L_0x2a143f0 .part RS_0x7f507e9b8ff8, 0, 1;
+L_0x2a141b0 .part RS_0x7f507e9b8fc8, 1, 1;
+L_0x2a14d90 .part/pv L_0x2a14b80, 2, 1, 32;
+L_0x2a14490 .part v0x2960210_0, 0, 1;
+L_0x2a14f80 .part v0x2960210_0, 1, 1;
+L_0x2a14e30 .part RS_0x7f507e9ad5c8, 2, 1;
+L_0x2a15180 .part RS_0x7f507e9ad5c8, 2, 1;
+L_0x2a150b0 .part RS_0x7f507e9a3368, 2, 1;
+L_0x2a15350 .part RS_0x7f507e9b8c98, 2, 1;
+L_0x2a15c80 .part/pv L_0x2a15a70, 2, 1, 32;
+L_0x2a15d20 .part v0x2960210_0, 0, 1;
+L_0x2a15440 .part v0x2960210_0, 1, 1;
+L_0x2a15fe0 .part RS_0x7f507e9a6998, 2, 1;
+L_0x2a15e50 .part RS_0x7f507e9a6998, 2, 1;
+L_0x2a16190 .part RS_0x7f507e9a3368, 2, 1;
+L_0x2a16080 .part RS_0x7f507e9a3368, 2, 1;
+L_0x2a16700 .part/pv L_0x2a165c0, 2, 1, 32;
+L_0x2a16230 .part v0x2960210_0, 2, 1;
+L_0x2a16960 .part RS_0x7f507e9b8f68, 2, 1;
+L_0x2a16830 .part RS_0x7f507e9b8f98, 2, 1;
+L_0x2a16bd0 .part/pv L_0x2a162d0, 2, 1, 32;
+L_0x2a16ad0 .part RS_0x7f507e9b8ff8, 1, 1;
+L_0x2a16e50 .part RS_0x7f507e9b8fc8, 2, 1;
+L_0x2a176b0 .part/pv L_0x2a174a0, 3, 1, 32;
+L_0x2a17750 .part v0x2960210_0, 0, 1;
+L_0x2a16ef0 .part v0x2960210_0, 1, 1;
+L_0x2a179f0 .part RS_0x7f507e9ad5c8, 3, 1;
+L_0x2a17880 .part RS_0x7f507e9ad5c8, 3, 1;
+L_0x2a17920 .part RS_0x7f507e9a3368, 3, 1;
+L_0x2a17a90 .part RS_0x7f507e9b8c98, 3, 1;
+L_0x2a18560 .part/pv L_0x2a18350, 3, 1, 32;
+L_0x2a17c60 .part v0x2960210_0, 0, 1;
+L_0x2a187a0 .part v0x2960210_0, 1, 1;
+L_0x2a18600 .part RS_0x7f507e9a6998, 3, 1;
+L_0x2a186a0 .part RS_0x7f507e9a6998, 3, 1;
+L_0x2a18a90 .part RS_0x7f507e9a3368, 3, 1;
+L_0x2a18b30 .part RS_0x7f507e9a3368, 3, 1;
+L_0x2a19020 .part/pv L_0x2a18ee0, 3, 1, 32;
+L_0x2a190c0 .part v0x2960210_0, 2, 1;
+L_0x2a18bd0 .part RS_0x7f507e9b8f68, 3, 1;
+L_0x2a18cc0 .part RS_0x7f507e9b8f98, 3, 1;
+L_0x2a19160 .part/pv L_0x2a19200, 3, 1, 32;
+L_0x2a19580 .part RS_0x7f507e9b8ff8, 2, 1;
+L_0x2a19390 .part RS_0x7f507e9b8fc8, 3, 1;
+L_0x2a19f50 .part/pv L_0x2a19d40, 4, 1, 32;
+L_0x2a19620 .part v0x2960210_0, 0, 1;
+L_0x2a19750 .part v0x2960210_0, 1, 1;
+L_0x2a19ff0 .part RS_0x7f507e9ad5c8, 4, 1;
+L_0x2a1a090 .part RS_0x7f507e9ad5c8, 4, 1;
+L_0x2a1a130 .part RS_0x7f507e9a3368, 4, 1;
+L_0x2a1a510 .part RS_0x7f507e9b8c98, 4, 1;
+L_0x2a1ae10 .part/pv L_0x2a1ac00, 4, 1, 32;
+L_0x2a1aeb0 .part v0x2960210_0, 0, 1;
+L_0x2a1a600 .part v0x2960210_0, 1, 1;
+L_0x2a1a730 .part RS_0x7f507e9a6998, 4, 1;
+L_0x2a1b240 .part RS_0x7f507e9a6998, 4, 1;
+L_0x2a1b2e0 .part RS_0x7f507e9a3368, 4, 1;
+L_0x2a1afe0 .part RS_0x7f507e9a3368, 4, 1;
+L_0x2a1b8b0 .part/pv L_0x2a1b770, 4, 1, 32;
+L_0x2a1b380 .part v0x2960210_0, 2, 1;
+L_0x2a1b420 .part RS_0x7f507e9b8f68, 4, 1;
+L_0x2a1b510 .part RS_0x7f507e9b8f98, 4, 1;
+L_0x2a1bb70 .part/pv L_0x2a16a00, 4, 1, 32;
+L_0x2a1bc10 .part RS_0x7f507e9b8ff8, 3, 1;
+L_0x2a1bdf0 .part RS_0x7f507e9b8fc8, 4, 1;
+L_0x2a1ca10 .part/pv L_0x2a1c800, 5, 1, 32;
+L_0x2a1cab0 .part v0x2960210_0, 0, 1;
+L_0x2a1c190 .part v0x2960210_0, 1, 1;
+L_0x2a1c2c0 .part RS_0x7f507e9ad5c8, 5, 1;
+L_0x2a1c360 .part RS_0x7f507e9ad5c8, 5, 1;
+L_0x2a1ceb0 .part RS_0x7f507e9a3368, 5, 1;
+L_0x2a1cbe0 .part RS_0x7f507e9b8c98, 5, 1;
+L_0x2a1d8c0 .part/pv L_0x2a1d6b0, 5, 1, 32;
+L_0x2a1cfa0 .part v0x2960210_0, 0, 1;
+L_0x2a1d0d0 .part v0x2960210_0, 1, 1;
+L_0x2a1dc60 .part RS_0x7f507e9a6998, 5, 1;
+L_0x2a1dd00 .part RS_0x7f507e9a6998, 5, 1;
+L_0x2a1d960 .part RS_0x7f507e9a3368, 5, 1;
+L_0x2a1da50 .part RS_0x7f507e9a3368, 5, 1;
+L_0x2a1e380 .part/pv L_0x2a1e240, 5, 1, 32;
+L_0x2a1e420 .part v0x2960210_0, 2, 1;
+L_0x2a1dda0 .part RS_0x7f507e9b8f68, 5, 1;
+L_0x2a1de90 .part RS_0x7f507e9b8f98, 5, 1;
+L_0x2a1df80 .part/pv L_0x2a1e020, 5, 1, 32;
+L_0x2a1e8a0 .part RS_0x7f507e9b8ff8, 4, 1;
+L_0x2a1e4c0 .part RS_0x7f507e9b8fc8, 5, 1;
+L_0x2a1f2b0 .part/pv L_0x2a1f0a0, 6, 1, 32;
+L_0x2a1e940 .part v0x2960210_0, 0, 1;
+L_0x2a1ea70 .part v0x2960210_0, 1, 1;
+L_0x2a1eba0 .part RS_0x7f507e9ad5c8, 6, 1;
+L_0x2a1f6c0 .part RS_0x7f507e9ad5c8, 6, 1;
+L_0x2a1f350 .part RS_0x7f507e9a3368, 6, 1;
+L_0x2a1f3f0 .part RS_0x7f507e9b8c98, 6, 1;
+L_0x2a20170 .part/pv L_0x2a1ff60, 6, 1, 32;
+L_0x2a20210 .part v0x2960210_0, 0, 1;
+L_0x2a1f760 .part v0x2960210_0, 1, 1;
+L_0x2a1f890 .part RS_0x7f507e9a6998, 6, 1;
+L_0x2a1f930 .part RS_0x7f507e9a6998, 6, 1;
+L_0x2a1f9d0 .part RS_0x7f507e9a3368, 6, 1;
+L_0x2a20700 .part RS_0x7f507e9a3368, 6, 1;
+L_0x2a20c00 .part/pv L_0x2a20ac0, 6, 1, 32;
+L_0x2a20340 .part v0x2960210_0, 2, 1;
+L_0x2a203e0 .part RS_0x7f507e9b8f68, 6, 1;
+L_0x2a204d0 .part RS_0x7f507e9b8f98, 6, 1;
+L_0x2a205c0 .part/pv L_0x2a20660, 6, 1, 32;
+L_0x2a21130 .part RS_0x7f507e9b8ff8, 5, 1;
+L_0x2a211d0 .part RS_0x7f507e9b8fc8, 6, 1;
+L_0x2a21b30 .part/pv L_0x2a21920, 7, 1, 32;
+L_0x2a21bd0 .part v0x2960210_0, 0, 1;
+L_0x2a212c0 .part v0x2960210_0, 1, 1;
+L_0x2a213f0 .part RS_0x7f507e9ad5c8, 7, 1;
+L_0x2a21490 .part RS_0x7f507e9ad5c8, 7, 1;
+L_0x2a21530 .part RS_0x7f507e9a3368, 7, 1;
+L_0x2a21620 .part RS_0x7f507e9b8c98, 7, 1;
+L_0x2a229e0 .part/pv L_0x2a227d0, 7, 1, 32;
+L_0x2a21d00 .part v0x2960210_0, 0, 1;
+L_0x2a21e30 .part v0x2960210_0, 1, 1;
+L_0x2a21f60 .part RS_0x7f507e9a6998, 7, 1;
+L_0x2a22000 .part RS_0x7f507e9a6998, 7, 1;
+L_0x2a22ee0 .part RS_0x7f507e9a3368, 7, 1;
+L_0x2a22f80 .part RS_0x7f507e9a3368, 7, 1;
+L_0x2a22df0 .part/pv L_0x2a22cb0, 7, 1, 32;
+L_0x2a234e0 .part v0x2960210_0, 2, 1;
+L_0x2a23070 .part RS_0x7f507e9b8f68, 7, 1;
+L_0x2a23110 .part RS_0x7f507e9b8f98, 7, 1;
+L_0x2a23200 .part/pv L_0x2a232a0, 7, 1, 32;
+L_0x2a233e0 .part RS_0x7f507e9b8ff8, 6, 1;
+L_0x2a23a20 .part RS_0x7f507e9b8fc8, 7, 1;
+L_0x2a243b0 .part/pv L_0x2a241a0, 8, 1, 32;
+L_0x2a23580 .part v0x2960210_0, 0, 1;
+L_0x2a236b0 .part v0x2960210_0, 1, 1;
+L_0x2a237e0 .part RS_0x7f507e9ad5c8, 8, 1;
+L_0x2a23880 .part RS_0x7f507e9ad5c8, 8, 1;
+L_0x2a23920 .part RS_0x7f507e9a3368, 8, 1;
+L_0x2a24920 .part RS_0x7f507e9b8c98, 8, 1;
+L_0x2a251e0 .part/pv L_0x2a24fd0, 8, 1, 32;
+L_0x2a25280 .part v0x2960210_0, 0, 1;
+L_0x2a24a10 .part v0x2960210_0, 1, 1;
+L_0x2a24b40 .part RS_0x7f507e9a6998, 8, 1;
+L_0x2a24be0 .part RS_0x7f507e9a6998, 8, 1;
+L_0x2a24c80 .part RS_0x7f507e9a3368, 8, 1;
+L_0x2a24d70 .part RS_0x7f507e9a3368, 8, 1;
+L_0x2a25b80 .part/pv L_0x2a25a40, 8, 1, 32;
+L_0x2a1b950 .part v0x2960210_0, 2, 1;
+L_0x2a253b0 .part RS_0x7f507e9b8f68, 8, 1;
+L_0x2a1bce0 .part RS_0x7f507e9b8f98, 8, 1;
+L_0x2a1ba40 .part/pv L_0x2a1bd80, 8, 1, 32;
+L_0x2a1c0d0 .part RS_0x7f507e9b8ff8, 7, 1;
+L_0x2a25e30 .part RS_0x7f507e9b8fc8, 8, 1;
+L_0x2a26ed0 .part/pv L_0x2a26cc0, 9, 1, 32;
+L_0x2a26f70 .part v0x2960210_0, 0, 1;
+L_0x2a26570 .part v0x2960210_0, 1, 1;
+L_0x2a266a0 .part RS_0x7f507e9ad5c8, 9, 1;
+L_0x2a26740 .part RS_0x7f507e9ad5c8, 9, 1;
+L_0x2a267e0 .part RS_0x7f507e9a3368, 9, 1;
+L_0x2a268d0 .part RS_0x7f507e9b8c98, 9, 1;
+L_0x2a27d80 .part/pv L_0x2a27b70, 9, 1, 32;
+L_0x2a270a0 .part v0x2960210_0, 0, 1;
+L_0x2a271d0 .part v0x2960210_0, 1, 1;
+L_0x2a27300 .part RS_0x7f507e9a6998, 9, 1;
+L_0x2a273a0 .part RS_0x7f507e9a6998, 9, 1;
+L_0x2a27440 .part RS_0x7f507e9a3368, 9, 1;
+L_0x2a27530 .part RS_0x7f507e9a3368, 9, 1;
+L_0x2a287f0 .part/pv L_0x2a286b0, 9, 1, 32;
+L_0x2a28890 .part v0x2960210_0, 2, 1;
+L_0x2a27e20 .part RS_0x7f507e9b8f68, 9, 1;
+L_0x2a27f10 .part RS_0x7f507e9b8f98, 9, 1;
+L_0x2a28000 .part/pv L_0x2a280a0, 9, 1, 32;
+L_0x2a281e0 .part RS_0x7f507e9b8ff8, 8, 1;
+L_0x2a28280 .part RS_0x7f507e9b8fc8, 9, 1;
+L_0x2a29720 .part/pv L_0x2a29510, 10, 1, 32;
+L_0x2a28930 .part v0x2960210_0, 0, 1;
+L_0x2a28a60 .part v0x2960210_0, 1, 1;
+L_0x2a28b90 .part RS_0x7f507e9ad5c8, 10, 1;
+L_0x2a28c30 .part RS_0x7f507e9ad5c8, 10, 1;
+L_0x2a28cd0 .part RS_0x7f507e9a3368, 10, 1;
+L_0x2a28dc0 .part RS_0x7f507e9b8c98, 10, 1;
+L_0x2a2a5c0 .part/pv L_0x2a2a3b0, 10, 1, 32;
+L_0x2a2a660 .part v0x2960210_0, 0, 1;
+L_0x2a297c0 .part v0x2960210_0, 1, 1;
+L_0x2a298f0 .part RS_0x7f507e9a6998, 10, 1;
+L_0x2a29990 .part RS_0x7f507e9a6998, 10, 1;
+L_0x2a29a30 .part RS_0x7f507e9a3368, 10, 1;
+L_0x2a29b20 .part RS_0x7f507e9a3368, 10, 1;
+L_0x2a0e150 .part/pv L_0x2a0e010, 10, 1, 32;
+L_0x2a0e1f0 .part v0x2960210_0, 2, 1;
+L_0x2a0e290 .part RS_0x7f507e9b8f68, 10, 1;
+L_0x2a2a7e0 .part RS_0x7f507e9b8f98, 10, 1;
+L_0x2a2a8d0 .part/pv L_0x2a2a970, 10, 1, 32;
+L_0x2a2aab0 .part RS_0x7f507e9b8ff8, 9, 1;
+L_0x2a2ab50 .part RS_0x7f507e9b8fc8, 10, 1;
+L_0x2a2c300 .part/pv L_0x2a2c0f0, 11, 1, 32;
+L_0x2a2c3a0 .part v0x2960210_0, 0, 1;
+L_0x2a2b5f0 .part v0x2960210_0, 1, 1;
+L_0x2a2b720 .part RS_0x7f507e9ad5c8, 11, 1;
+L_0x2a2b7c0 .part RS_0x7f507e9ad5c8, 11, 1;
+L_0x2a2b860 .part RS_0x7f507e9a3368, 11, 1;
+L_0x2a2b950 .part RS_0x7f507e9b8c98, 11, 1;
+L_0x2a2d160 .part/pv L_0x2a2cf50, 11, 1, 32;
+L_0x2a2c4d0 .part v0x2960210_0, 0, 1;
+L_0x2a2c600 .part v0x2960210_0, 1, 1;
+L_0x2a2c730 .part RS_0x7f507e9a6998, 11, 1;
+L_0x2a2c7d0 .part RS_0x7f507e9a6998, 11, 1;
+L_0x2a2c870 .part RS_0x7f507e9a3368, 11, 1;
+L_0x2a2c960 .part RS_0x7f507e9a3368, 11, 1;
+L_0x2a2dbd0 .part/pv L_0x2a2da90, 11, 1, 32;
+L_0x2a2dc70 .part v0x2960210_0, 2, 1;
+L_0x2a2d200 .part RS_0x7f507e9b8f68, 11, 1;
+L_0x2a2d2f0 .part RS_0x7f507e9b8f98, 11, 1;
+L_0x2a2d3e0 .part/pv L_0x2a2d480, 11, 1, 32;
+L_0x2a2d5c0 .part RS_0x7f507e9b8ff8, 10, 1;
+L_0x2a2d660 .part RS_0x7f507e9b8fc8, 11, 1;
+L_0x2a2ea60 .part/pv L_0x2a2e850, 12, 1, 32;
+L_0x2a2dd10 .part v0x2960210_0, 0, 1;
+L_0x2a2de40 .part v0x2960210_0, 1, 1;
+L_0x2a2df70 .part RS_0x7f507e9ad5c8, 12, 1;
+L_0x2a2e010 .part RS_0x7f507e9ad5c8, 12, 1;
+L_0x2a2e0b0 .part RS_0x7f507e9a3368, 12, 1;
+L_0x2a2e1a0 .part RS_0x7f507e9b8c98, 12, 1;
+L_0x2a2f920 .part/pv L_0x2a2f710, 12, 1, 32;
+L_0x2a2f9c0 .part v0x2960210_0, 0, 1;
+L_0x2a2eb00 .part v0x2960210_0, 1, 1;
+L_0x2a2ec30 .part RS_0x7f507e9a6998, 12, 1;
+L_0x2a2ecd0 .part RS_0x7f507e9a6998, 12, 1;
+L_0x2a2ed70 .part RS_0x7f507e9a3368, 12, 1;
+L_0x2a2ee60 .part RS_0x7f507e9a3368, 12, 1;
+L_0x2a30380 .part/pv L_0x2a2f220, 12, 1, 32;
+L_0x2a2faf0 .part v0x2960210_0, 2, 1;
+L_0x2a2fb90 .part RS_0x7f507e9b8f68, 12, 1;
+L_0x2a2fc80 .part RS_0x7f507e9b8f98, 12, 1;
+L_0x2a2fd70 .part/pv L_0x2a2fe10, 12, 1, 32;
+L_0x2a2ff50 .part RS_0x7f507e9b8ff8, 11, 1;
+L_0x2a2fff0 .part RS_0x7f507e9b8fc8, 12, 1;
+L_0x2a312b0 .part/pv L_0x2a310a0, 13, 1, 32;
+L_0x2a31350 .part v0x2960210_0, 0, 1;
+L_0x2a30420 .part v0x2960210_0, 1, 1;
+L_0x2a30550 .part RS_0x7f507e9ad5c8, 13, 1;
+L_0x2a305f0 .part RS_0x7f507e9ad5c8, 13, 1;
+L_0x2a30690 .part RS_0x7f507e9a3368, 13, 1;
+L_0x2a30780 .part RS_0x7f507e9b8c98, 13, 1;
+L_0x2a32140 .part/pv L_0x2a31f30, 13, 1, 32;
+L_0x2a31480 .part v0x2960210_0, 0, 1;
+L_0x2a315b0 .part v0x2960210_0, 1, 1;
+L_0x2a316e0 .part RS_0x7f507e9a6998, 13, 1;
+L_0x2a31780 .part RS_0x7f507e9a6998, 13, 1;
+L_0x2a31820 .part RS_0x7f507e9a3368, 13, 1;
+L_0x2a31910 .part RS_0x7f507e9a3368, 13, 1;
+L_0x2a32b70 .part/pv L_0x2a31c40, 13, 1, 32;
+L_0x2a32c10 .part v0x2960210_0, 2, 1;
+L_0x2a321e0 .part RS_0x7f507e9b8f68, 13, 1;
+L_0x2a32280 .part RS_0x7f507e9b8f98, 13, 1;
+L_0x2a32370 .part/pv L_0x2a32410, 13, 1, 32;
+L_0x2a32550 .part RS_0x7f507e9b8ff8, 12, 1;
+L_0x2a325f0 .part RS_0x7f507e9b8fc8, 13, 1;
+L_0x2a33a40 .part/pv L_0x2a33830, 14, 1, 32;
+L_0x2a32cb0 .part v0x2960210_0, 0, 1;
+L_0x2a32de0 .part v0x2960210_0, 1, 1;
+L_0x2a32f10 .part RS_0x7f507e9ad5c8, 14, 1;
+L_0x2a32fb0 .part RS_0x7f507e9ad5c8, 14, 1;
+L_0x2a33050 .part RS_0x7f507e9a3368, 14, 1;
+L_0x2a33140 .part RS_0x7f507e9b8c98, 14, 1;
+L_0x2a348d0 .part/pv L_0x2a346c0, 14, 1, 32;
+L_0x2a34970 .part v0x2960210_0, 0, 1;
+L_0x2a33ae0 .part v0x2960210_0, 1, 1;
+L_0x2a33c10 .part RS_0x7f507e9a6998, 14, 1;
+L_0x2a33cb0 .part RS_0x7f507e9a6998, 14, 1;
+L_0x2a33d50 .part RS_0x7f507e9a3368, 14, 1;
+L_0x2a33e40 .part RS_0x7f507e9a3368, 14, 1;
+L_0x2a353a0 .part/pv L_0x2a34200, 14, 1, 32;
+L_0x2a34aa0 .part v0x2960210_0, 2, 1;
+L_0x2a34b40 .part RS_0x7f507e9b8f68, 14, 1;
+L_0x2a34c30 .part RS_0x7f507e9b8f98, 14, 1;
+L_0x2a34d20 .part/pv L_0x2a34dc0, 14, 1, 32;
+L_0x2a34f00 .part RS_0x7f507e9b8ff8, 13, 1;
+L_0x2a34fa0 .part RS_0x7f507e9b8fc8, 14, 1;
+L_0x2a362a0 .part/pv L_0x2a36090, 15, 1, 32;
+L_0x2a36340 .part v0x2960210_0, 0, 1;
+L_0x2a35440 .part v0x2960210_0, 1, 1;
+L_0x2a35570 .part RS_0x7f507e9ad5c8, 15, 1;
+L_0x2986f60 .part RS_0x7f507e9ad5c8, 15, 1;
+L_0x2987000 .part RS_0x7f507e9a3368, 15, 1;
+L_0x29870f0 .part RS_0x7f507e9b8c98, 15, 1;
+L_0x2a35ce0 .part/pv L_0x2a35ad0, 15, 1, 32;
+L_0x2a36470 .part v0x2960210_0, 0, 1;
+L_0x2a365a0 .part v0x2960210_0, 1, 1;
+L_0x2a366d0 .part RS_0x7f507e9a6998, 15, 1;
+L_0x29e8f40 .part RS_0x7f507e9a6998, 15, 1;
+L_0x29e8fe0 .part RS_0x7f507e9a3368, 15, 1;
+L_0x29e90d0 .part RS_0x7f507e9a3368, 15, 1;
+L_0x2a369f0 .part/pv L_0x2a368b0, 15, 1, 32;
+L_0x2a36a90 .part v0x2960210_0, 2, 1;
+L_0x2a36b30 .part RS_0x7f507e9b8f68, 15, 1;
+L_0x2a36c20 .part RS_0x7f507e9b8f98, 15, 1;
+L_0x2a36d10 .part/pv L_0x2a375d0, 15, 1, 32;
+L_0x2a37710 .part RS_0x7f507e9b8ff8, 14, 1;
+L_0x2a377b0 .part RS_0x7f507e9b8fc8, 15, 1;
+L_0x2a39330 .part/pv L_0x2a39150, 16, 1, 32;
+L_0x2a38770 .part v0x2960210_0, 0, 1;
+L_0x2a388a0 .part v0x2960210_0, 1, 1;
+L_0x2a389d0 .part RS_0x7f507e9ad5c8, 16, 1;
+L_0x2a38a70 .part RS_0x7f507e9ad5c8, 16, 1;
+L_0x2a38b10 .part RS_0x7f507e9a3368, 16, 1;
+L_0x2a38c00 .part RS_0x7f507e9b8c98, 16, 1;
+L_0x2a3a1c0 .part/pv L_0x2a39fb0, 16, 1, 32;
+L_0x2a3a260 .part v0x2960210_0, 0, 1;
+L_0x2a393d0 .part v0x2960210_0, 1, 1;
+L_0x2a39500 .part RS_0x7f507e9a6998, 16, 1;
+L_0x2a395a0 .part RS_0x7f507e9a6998, 16, 1;
+L_0x2a39640 .part RS_0x7f507e9a3368, 16, 1;
+L_0x2a39730 .part RS_0x7f507e9a3368, 16, 1;
+L_0x2a39c30 .part/pv L_0x2a39af0, 16, 1, 32;
+L_0x2a39cd0 .part v0x2960210_0, 2, 1;
+L_0x2a25c20 .part RS_0x7f507e9b8f68, 16, 1;
+L_0x2a25d10 .part RS_0x7f507e9b8f98, 16, 1;
+L_0x2a3abb0 .part/pv L_0x2a39d70, 16, 1, 32;
+L_0x2a3ad30 .part RS_0x7f507e9b8ff8, 15, 1;
+L_0x2a26360 .part RS_0x7f507e9b8fc8, 16, 1;
+L_0x2a3c3c0 .part/pv L_0x2a3c1b0, 17, 1, 32;
+L_0x2a3c460 .part v0x2960210_0, 0, 1;
+L_0x2a3b1f0 .part v0x2960210_0, 1, 1;
+L_0x2a3b320 .part RS_0x7f507e9ad5c8, 17, 1;
+L_0x2a3b3c0 .part RS_0x7f507e9ad5c8, 17, 1;
+L_0x2a3b460 .part RS_0x7f507e9a3368, 17, 1;
+L_0x2a3b550 .part RS_0x7f507e9b8c98, 17, 1;
+L_0x2a3d270 .part/pv L_0x2a3d090, 17, 1, 32;
+L_0x2a3c590 .part v0x2960210_0, 0, 1;
+L_0x2a3c6c0 .part v0x2960210_0, 1, 1;
+L_0x2a3c7f0 .part RS_0x7f507e9a6998, 17, 1;
+L_0x2a3c890 .part RS_0x7f507e9a6998, 17, 1;
+L_0x2a3c930 .part RS_0x7f507e9a3368, 17, 1;
+L_0x2a3ca20 .part RS_0x7f507e9a3368, 17, 1;
+L_0x2a3cf20 .part/pv L_0x2a3cde0, 17, 1, 32;
+L_0x2a3de10 .part v0x2960210_0, 2, 1;
+L_0x2a3d310 .part RS_0x7f507e9b8f68, 17, 1;
+L_0x2a3d400 .part RS_0x7f507e9b8f98, 17, 1;
+L_0x2a3d4f0 .part/pv L_0x2a3d590, 17, 1, 32;
+L_0x2a3d6d0 .part RS_0x7f507e9b8ff8, 16, 1;
+L_0x2a3d770 .part RS_0x7f507e9b8fc8, 17, 1;
+L_0x2a3ebf0 .part/pv L_0x2a3ea20, 18, 1, 32;
+L_0x2a3deb0 .part v0x2960210_0, 0, 1;
+L_0x2a3dfe0 .part v0x2960210_0, 1, 1;
+L_0x2a3e110 .part RS_0x7f507e9ad5c8, 18, 1;
+L_0x2a3e1b0 .part RS_0x7f507e9ad5c8, 18, 1;
+L_0x2a3e250 .part RS_0x7f507e9a3368, 18, 1;
+L_0x2a3e340 .part RS_0x7f507e9b8c98, 18, 1;
+L_0x2a3faf0 .part/pv L_0x2a3f8e0, 18, 1, 32;
+L_0x2a3fb90 .part v0x2960210_0, 0, 1;
+L_0x2a3ec90 .part v0x2960210_0, 1, 1;
+L_0x2a3edc0 .part RS_0x7f507e9a6998, 18, 1;
+L_0x2a3ee60 .part RS_0x7f507e9a6998, 18, 1;
+L_0x2a3ef00 .part RS_0x7f507e9a3368, 18, 1;
+L_0x2a3eff0 .part RS_0x7f507e9a3368, 18, 1;
+L_0x2a3f4f0 .part/pv L_0x2a3f3b0, 18, 1, 32;
+L_0x2a3f590 .part v0x2960210_0, 2, 1;
+L_0x2a3f630 .part RS_0x7f507e9b8f68, 18, 1;
+L_0x2a3f720 .part RS_0x7f507e9b8f98, 18, 1;
+L_0x2a40880 .part/pv L_0x2a3fcc0, 18, 1, 32;
+L_0x2a3fe00 .part RS_0x7f507e9b8ff8, 17, 1;
+L_0x2a3fea0 .part RS_0x7f507e9b8fc8, 18, 1;
+L_0x2a41500 .part/pv L_0x2a40610, 19, 1, 32;
+L_0x2a415a0 .part v0x2960210_0, 0, 1;
+L_0x2a40920 .part v0x2960210_0, 1, 1;
+L_0x2a40a50 .part RS_0x7f507e9ad5c8, 19, 1;
+L_0x2a40af0 .part RS_0x7f507e9ad5c8, 19, 1;
+L_0x2a40b90 .part RS_0x7f507e9a3368, 19, 1;
+L_0x2a40c80 .part RS_0x7f507e9b8c98, 19, 1;
+L_0x2a42330 .part/pv L_0x2a41330, 19, 1, 32;
+L_0x2a416d0 .part v0x2960210_0, 0, 1;
+L_0x2a41800 .part v0x2960210_0, 1, 1;
+L_0x2a41930 .part RS_0x7f507e9a6998, 19, 1;
+L_0x2a419d0 .part RS_0x7f507e9a6998, 19, 1;
+L_0x2a41a70 .part RS_0x7f507e9a3368, 19, 1;
+L_0x2a41b60 .part RS_0x7f507e9a3368, 19, 1;
+L_0x2a42060 .part/pv L_0x2a41f20, 19, 1, 32;
+L_0x2a42100 .part v0x2960210_0, 2, 1;
+L_0x2a421a0 .part RS_0x7f507e9b8f68, 19, 1;
+L_0x2a43030 .part RS_0x7f507e9b8f98, 19, 1;
+L_0x2a423d0 .part/pv L_0x2a42470, 19, 1, 32;
+L_0x2a425b0 .part RS_0x7f507e9b8ff8, 18, 1;
+L_0x2a42650 .part RS_0x7f507e9b8fc8, 19, 1;
+L_0x2a42f70 .part/pv L_0x2a42d60, 20, 1, 32;
+L_0x2a43d60 .part v0x2960210_0, 0, 1;
+L_0x2a43e90 .part v0x2960210_0, 1, 1;
+L_0x2a430d0 .part RS_0x7f507e9ad5c8, 20, 1;
+L_0x2a43170 .part RS_0x7f507e9ad5c8, 20, 1;
+L_0x2a43210 .part RS_0x7f507e9a3368, 20, 1;
+L_0x2a43300 .part RS_0x7f507e9b8c98, 20, 1;
+L_0x2a43c20 .part/pv L_0x2a43a10, 20, 1, 32;
+L_0x2a43cc0 .part v0x2960210_0, 0, 1;
+L_0x2a43fc0 .part v0x2960210_0, 1, 1;
+L_0x2a440f0 .part RS_0x7f507e9a6998, 20, 1;
+L_0x2a44190 .part RS_0x7f507e9a6998, 20, 1;
+L_0x2a44230 .part RS_0x7f507e9a3368, 20, 1;
+L_0x2a44320 .part RS_0x7f507e9a3368, 20, 1;
+L_0x2a44820 .part/pv L_0x2a446e0, 20, 1, 32;
+L_0x2a448c0 .part v0x2960210_0, 2, 1;
+L_0x2a44960 .part RS_0x7f507e9b8f68, 20, 1;
+L_0x2a44a50 .part RS_0x7f507e9b8f98, 20, 1;
+L_0x2a44b40 .part/pv L_0x2a44be0, 20, 1, 32;
+L_0x2a45ad0 .part RS_0x7f507e9b8ff8, 19, 1;
+L_0x2a45b70 .part RS_0x7f507e9b8fc8, 20, 1;
+L_0x2a45510 .part/pv L_0x2a45300, 21, 1, 32;
+L_0x2a455b0 .part v0x2960210_0, 0, 1;
+L_0x2a456e0 .part v0x2960210_0, 1, 1;
+L_0x2a45810 .part RS_0x7f507e9ad5c8, 21, 1;
+L_0x2a458b0 .part RS_0x7f507e9ad5c8, 21, 1;
+L_0x2a45950 .part RS_0x7f507e9a3368, 21, 1;
+L_0x2a45c60 .part RS_0x7f507e9b8c98, 21, 1;
+L_0x2a46480 .part/pv L_0x2a462a0, 21, 1, 32;
+L_0x2a46520 .part v0x2960210_0, 0, 1;
+L_0x2a46650 .part v0x2960210_0, 1, 1;
+L_0x2a46780 .part RS_0x7f507e9a6998, 21, 1;
+L_0x2a46820 .part RS_0x7f507e9a6998, 21, 1;
+L_0x2a468c0 .part RS_0x7f507e9a3368, 21, 1;
+L_0x2a47790 .part RS_0x7f507e9a3368, 21, 1;
+L_0x2a46db0 .part/pv L_0x2a46c70, 21, 1, 32;
+L_0x2a46e50 .part v0x2960210_0, 2, 1;
+L_0x2a46ef0 .part RS_0x7f507e9b8f68, 21, 1;
+L_0x2a46fe0 .part RS_0x7f507e9b8f98, 21, 1;
+L_0x2a470d0 .part/pv L_0x2a47170, 21, 1, 32;
+L_0x2a472b0 .part RS_0x7f507e9b8ff8, 20, 1;
+L_0x2a47350 .part RS_0x7f507e9b8fc8, 21, 1;
+L_0x2a48a90 .part/pv L_0x2a488b0, 22, 1, 32;
+L_0x2a47880 .part v0x2960210_0, 0, 1;
+L_0x2a479b0 .part v0x2960210_0, 1, 1;
+L_0x2a47ae0 .part RS_0x7f507e9ad5c8, 22, 1;
+L_0x2a47b80 .part RS_0x7f507e9ad5c8, 22, 1;
+L_0x2a47c20 .part RS_0x7f507e9a3368, 22, 1;
+L_0x2a47d10 .part RS_0x7f507e9b8c98, 22, 1;
+L_0x2a48570 .part/pv L_0x2a48390, 22, 1, 32;
+L_0x2a49940 .part v0x2960210_0, 0, 1;
+L_0x2a48b30 .part v0x2960210_0, 1, 1;
+L_0x2a48c60 .part RS_0x7f507e9a6998, 22, 1;
+L_0x2a48d00 .part RS_0x7f507e9a6998, 22, 1;
+L_0x2a48da0 .part RS_0x7f507e9a3368, 22, 1;
+L_0x2a48e90 .part RS_0x7f507e9a3368, 22, 1;
+L_0x2a49350 .part/pv L_0x2a49210, 22, 1, 32;
+L_0x2a493f0 .part v0x2960210_0, 2, 1;
+L_0x2a49490 .part RS_0x7f507e9b8f68, 22, 1;
+L_0x2a49580 .part RS_0x7f507e9b8f98, 22, 1;
+L_0x2a49670 .part/pv L_0x2a49710, 22, 1, 32;
+L_0x2a49850 .part RS_0x7f507e9b8ff8, 21, 1;
+L_0x2a4a8e0 .part RS_0x7f507e9b8fc8, 22, 1;
+L_0x2a4a1e0 .part/pv L_0x2a4a000, 23, 1, 32;
+L_0x2a4a280 .part v0x2960210_0, 0, 1;
+L_0x2a4a3b0 .part v0x2960210_0, 1, 1;
+L_0x2a4a4e0 .part RS_0x7f507e9ad5c8, 23, 1;
+L_0x2a4a580 .part RS_0x7f507e9ad5c8, 23, 1;
+L_0x2a4a620 .part RS_0x7f507e9a3368, 23, 1;
+L_0x2a4a710 .part RS_0x7f507e9b8c98, 23, 1;
+L_0x2a4bec0 .part/pv L_0x2a4bce0, 23, 1, 32;
+L_0x2a4a980 .part v0x2960210_0, 0, 1;
+L_0x2a4aab0 .part v0x2960210_0, 1, 1;
+L_0x2a4abe0 .part RS_0x7f507e9a6998, 23, 1;
+L_0x2a4ac80 .part RS_0x7f507e9a6998, 23, 1;
+L_0x2a4ad20 .part RS_0x7f507e9a3368, 23, 1;
+L_0x2a4ae10 .part RS_0x7f507e9a3368, 23, 1;
+L_0x2a4b310 .part/pv L_0x2a4b1d0, 23, 1, 32;
+L_0x2a4b3b0 .part v0x2960210_0, 2, 1;
+L_0x2a4b450 .part RS_0x7f507e9b8f68, 23, 1;
+L_0x2a4b540 .part RS_0x7f507e9b8f98, 23, 1;
+L_0x2a4b630 .part/pv L_0x2a4b6d0, 23, 1, 32;
+L_0x2a4ce70 .part RS_0x7f507e9b8ff8, 22, 1;
+L_0x2a4bf60 .part RS_0x7f507e9b8fc8, 23, 1;
+L_0x2a4c7c0 .part/pv L_0x2a4c5e0, 24, 1, 32;
+L_0x2a4c860 .part v0x2960210_0, 0, 1;
+L_0x2a4c990 .part v0x2960210_0, 1, 1;
+L_0x2a4cac0 .part RS_0x7f507e9ad5c8, 24, 1;
+L_0x2a4cb60 .part RS_0x7f507e9ad5c8, 24, 1;
+L_0x2a4cc00 .part RS_0x7f507e9a3368, 24, 1;
+L_0x2a4ccf0 .part RS_0x7f507e9b8c98, 24, 1;
+L_0x2a4e580 .part/pv L_0x2a4e3a0, 24, 1, 32;
+L_0x2a4e620 .part v0x2960210_0, 0, 1;
+L_0x2a4cf10 .part v0x2960210_0, 1, 1;
+L_0x2a4d040 .part RS_0x7f507e9a6998, 24, 1;
+L_0x2a4d0e0 .part RS_0x7f507e9a6998, 24, 1;
+L_0x2a4d180 .part RS_0x7f507e9a3368, 24, 1;
+L_0x2a4d270 .part RS_0x7f507e9a3368, 24, 1;
+L_0x2a4d770 .part/pv L_0x2a4d630, 24, 1, 32;
+L_0x2a4d810 .part v0x2960210_0, 2, 1;
+L_0x2a4d8b0 .part RS_0x7f507e9b8f68, 24, 1;
+L_0x2a4d9a0 .part RS_0x7f507e9b8f98, 24, 1;
+L_0x2a4da90 .part/pv L_0x2a4db30, 24, 1, 32;
+L_0x2a4dc70 .part RS_0x7f507e9b8ff8, 23, 1;
+L_0x2a4dd10 .part RS_0x7f507e9b8fc8, 24, 1;
+L_0x2a4fe30 .part/pv L_0x2a4fc50, 25, 1, 32;
+L_0x2a4fed0 .part v0x2960210_0, 0, 1;
+L_0x2a4e750 .part v0x2960210_0, 1, 1;
+L_0x2a4e880 .part RS_0x7f507e9ad5c8, 25, 1;
+L_0x2a4e920 .part RS_0x7f507e9ad5c8, 25, 1;
+L_0x2a4e9c0 .part RS_0x7f507e9a3368, 25, 1;
+L_0x2a4eab0 .part RS_0x7f507e9b8c98, 25, 1;
+L_0x2a4f310 .part/pv L_0x2a4f130, 25, 1, 32;
+L_0x2a4f3b0 .part v0x2960210_0, 0, 1;
+L_0x2a4f4e0 .part v0x2960210_0, 1, 1;
+L_0x2a4f610 .part RS_0x7f507e9a6998, 25, 1;
+L_0x2a51020 .part RS_0x7f507e9a6998, 25, 1;
+L_0x2a50000 .part RS_0x7f507e9a3368, 25, 1;
+L_0x2a500f0 .part RS_0x7f507e9a3368, 25, 1;
+L_0x2a505f0 .part/pv L_0x2a504b0, 25, 1, 32;
+L_0x2a50690 .part v0x2960210_0, 2, 1;
+L_0x2a50730 .part RS_0x7f507e9b8f68, 25, 1;
+L_0x2a50820 .part RS_0x7f507e9b8f98, 25, 1;
+L_0x2a50910 .part/pv L_0x2a509b0, 25, 1, 32;
+L_0x2a50af0 .part RS_0x7f507e9b8ff8, 24, 1;
+L_0x2a50b90 .part RS_0x7f507e9b8fc8, 25, 1;
+L_0x2a524e0 .part/pv L_0x2a52300, 26, 1, 32;
+L_0x2a510c0 .part v0x2960210_0, 0, 1;
+L_0x2a511f0 .part v0x2960210_0, 1, 1;
+L_0x2a51320 .part RS_0x7f507e9ad5c8, 26, 1;
+L_0x2a513c0 .part RS_0x7f507e9ad5c8, 26, 1;
+L_0x2a51460 .part RS_0x7f507e9a3368, 26, 1;
+L_0x2a51550 .part RS_0x7f507e9b8c98, 26, 1;
+L_0x2a51db0 .part/pv L_0x2a51bd0, 26, 1, 32;
+L_0x2a51e50 .part v0x2960210_0, 0, 1;
+L_0x2a51f80 .part v0x2960210_0, 1, 1;
+L_0x2a53640 .part RS_0x7f507e9a6998, 26, 1;
+L_0x2a52580 .part RS_0x7f507e9a6998, 26, 1;
+L_0x2a52620 .part RS_0x7f507e9a3368, 26, 1;
+L_0x2a52710 .part RS_0x7f507e9a3368, 26, 1;
+L_0x2a52c10 .part/pv L_0x2a52ad0, 26, 1, 32;
+L_0x2a52cb0 .part v0x2960210_0, 2, 1;
+L_0x2a52d50 .part RS_0x7f507e9b8f68, 26, 1;
+L_0x2a52e40 .part RS_0x7f507e9b8f98, 26, 1;
+L_0x2a52f30 .part/pv L_0x2a52fd0, 26, 1, 32;
+L_0x2a53110 .part RS_0x7f507e9b8ff8, 25, 1;
+L_0x2a531b0 .part RS_0x7f507e9b8fc8, 26, 1;
+L_0x2a54bb0 .part/pv L_0x2a549d0, 27, 1, 32;
+L_0x2a54c50 .part v0x2960210_0, 0, 1;
+L_0x2a536e0 .part v0x2960210_0, 1, 1;
+L_0x2a53810 .part RS_0x7f507e9ad5c8, 27, 1;
+L_0x2a538b0 .part RS_0x7f507e9ad5c8, 27, 1;
+L_0x2a53950 .part RS_0x7f507e9a3368, 27, 1;
+L_0x2a53a40 .part RS_0x7f507e9b8c98, 27, 1;
+L_0x2a542a0 .part/pv L_0x2a540c0, 27, 1, 32;
+L_0x2a54340 .part v0x2960210_0, 0, 1;
+L_0x2a54470 .part v0x2960210_0, 1, 1;
+L_0x2a545a0 .part RS_0x7f507e9a6998, 27, 1;
+L_0x2a54640 .part RS_0x7f507e9a6998, 27, 1;
+L_0x2a546e0 .part RS_0x7f507e9a3368, 27, 1;
+L_0x2a55f00 .part RS_0x7f507e9a3368, 27, 1;
+L_0x2a55190 .part/pv L_0x2a55050, 27, 1, 32;
+L_0x2a55230 .part v0x2960210_0, 2, 1;
+L_0x2a552d0 .part RS_0x7f507e9b8f68, 27, 1;
+L_0x2a553c0 .part RS_0x7f507e9b8f98, 27, 1;
+L_0x2a554b0 .part/pv L_0x2a55550, 27, 1, 32;
+L_0x2a55690 .part RS_0x7f507e9b8ff8, 26, 1;
+L_0x2a55730 .part RS_0x7f507e9b8fc8, 27, 1;
+L_0x2a57240 .part/pv L_0x2a55db0, 28, 1, 32;
+L_0x2a55ff0 .part v0x2960210_0, 0, 1;
+L_0x2a56120 .part v0x2960210_0, 1, 1;
+L_0x2a56250 .part RS_0x7f507e9ad5c8, 28, 1;
+L_0x2a562f0 .part RS_0x7f507e9ad5c8, 28, 1;
+L_0x2a56390 .part RS_0x7f507e9a3368, 28, 1;
+L_0x2a56480 .part RS_0x7f507e9b8c98, 28, 1;
+L_0x2a56ce0 .part/pv L_0x2a56b00, 28, 1, 32;
+L_0x2a56d80 .part v0x2960210_0, 0, 1;
+L_0x2a56eb0 .part v0x2960210_0, 1, 1;
+L_0x2a56fe0 .part RS_0x7f507e9a6998, 28, 1;
+L_0x2a57080 .part RS_0x7f507e9a6998, 28, 1;
+L_0x2a58500 .part RS_0x7f507e9a3368, 28, 1;
+L_0x2a572e0 .part RS_0x7f507e9a3368, 28, 1;
+L_0x2a577a0 .part/pv L_0x2a57660, 28, 1, 32;
+L_0x2a57840 .part v0x2960210_0, 2, 1;
+L_0x2a578e0 .part RS_0x7f507e9b8f68, 28, 1;
+L_0x2a579d0 .part RS_0x7f507e9b8f98, 28, 1;
+L_0x2a57ac0 .part/pv L_0x2a57b60, 28, 1, 32;
+L_0x2a57ca0 .part RS_0x7f507e9b8ff8, 27, 1;
+L_0x2a57d40 .part RS_0x7f507e9b8fc8, 28, 1;
+L_0x2a598b0 .part/pv L_0x2a583c0, 29, 1, 32;
+L_0x2a59950 .part v0x2960210_0, 0, 1;
+L_0x2a585a0 .part v0x2960210_0, 1, 1;
+L_0x2a586d0 .part RS_0x7f507e9ad5c8, 29, 1;
+L_0x2a58770 .part RS_0x7f507e9ad5c8, 29, 1;
+L_0x2a58810 .part RS_0x7f507e9a3368, 29, 1;
+L_0x2a58900 .part RS_0x7f507e9b8c98, 29, 1;
+L_0x2a59560 .part/pv L_0x2a59380, 29, 1, 32;
+L_0x2a59600 .part v0x2960210_0, 0, 1;
+L_0x2a59730 .part v0x2960210_0, 1, 1;
+L_0x2a59a80 .part RS_0x7f507e9a6998, 29, 1;
+L_0x2a59b20 .part RS_0x7f507e9a6998, 29, 1;
+L_0x2a59bc0 .part RS_0x7f507e9a3368, 29, 1;
+L_0x2a59cb0 .part RS_0x7f507e9a3368, 29, 1;
+L_0x2a5a170 .part/pv L_0x2a5a030, 29, 1, 32;
+L_0x2a5a210 .part v0x2960210_0, 2, 1;
+L_0x2a5a2b0 .part RS_0x7f507e9b8f68, 29, 1;
+L_0x2a5a3a0 .part RS_0x7f507e9b8f98, 29, 1;
+L_0x2a5a490 .part/pv L_0x2a5a530, 29, 1, 32;
+L_0x2a5a670 .part RS_0x7f507e9b8ff8, 28, 1;
+L_0x2a5a710 .part RS_0x7f507e9b8fc8, 29, 1;
+L_0x2a5c330 .part/pv L_0x2a5c150, 30, 1, 32;
+L_0x2a5adc0 .part v0x2960210_0, 0, 1;
+L_0x2a5aef0 .part v0x2960210_0, 1, 1;
+L_0x2a5b020 .part RS_0x7f507e9ad5c8, 30, 1;
+L_0x2a5b0c0 .part RS_0x7f507e9ad5c8, 30, 1;
+L_0x2a5b160 .part RS_0x7f507e9a3368, 30, 1;
+L_0x2a5b250 .part RS_0x7f507e9b8c98, 30, 1;
+L_0x2a5bab0 .part/pv L_0x2a5b8d0, 30, 1, 32;
+L_0x2a5bb50 .part v0x2960210_0, 0, 1;
+L_0x2a5bc80 .part v0x2960210_0, 1, 1;
+L_0x2a5bdb0 .part RS_0x7f507e9a6998, 30, 1;
+L_0x2a5be50 .part RS_0x7f507e9a6998, 30, 1;
+L_0x2a5bef0 .part RS_0x7f507e9a3368, 30, 1;
+L_0x2a5bfe0 .part RS_0x7f507e9a3368, 30, 1;
+L_0x2a5db60 .part/pv L_0x2a5da20, 30, 1, 32;
+L_0x2a5c3d0 .part v0x2960210_0, 2, 1;
+L_0x2a5c470 .part RS_0x7f507e9b8f68, 30, 1;
+L_0x2a5c560 .part RS_0x7f507e9b8f98, 30, 1;
+L_0x2a5c650 .part/pv L_0x2a5c6f0, 30, 1, 32;
+L_0x2a5c830 .part RS_0x7f507e9b8ff8, 29, 1;
+L_0x2a5c8d0 .part RS_0x7f507e9b8fc8, 30, 1;
+L_0x2a5d130 .part/pv L_0x2a5cf50, 31, 1, 32;
+L_0x2a5d1d0 .part v0x2960210_0, 0, 1;
+L_0x2a5d300 .part v0x2960210_0, 1, 1;
+L_0x2a5d430 .part RS_0x7f507e9ad5c8, 31, 1;
+L_0x2a5d4d0 .part RS_0x7f507e9ad5c8, 31, 1;
+L_0x2a5d570 .part RS_0x7f507e9a3368, 31, 1;
+L_0x2a5d660 .part RS_0x7f507e9b8c98, 31, 1;
+L_0x2a5f760 .part/pv L_0x2a5f580, 31, 1, 32;
+L_0x2a5dc00 .part v0x2960210_0, 0, 1;
+L_0x2a5dd30 .part v0x2960210_0, 1, 1;
+L_0x2a5de60 .part RS_0x7f507e9a6998, 31, 1;
+L_0x2a5df00 .part RS_0x7f507e9a6998, 31, 1;
+L_0x2a5dfa0 .part RS_0x7f507e9a3368, 31, 1;
+L_0x2a5e090 .part RS_0x7f507e9a3368, 31, 1;
+L_0x2a2b1f0 .part/pv L_0x2a2b0b0, 31, 1, 32;
+L_0x2a2b290 .part v0x2960210_0, 2, 1;
+L_0x2a2b330 .part RS_0x7f507e9b8f68, 31, 1;
+L_0x2a2b420 .part RS_0x7f507e9b8f98, 31, 1;
+L_0x2a2b510 .part/pv L_0x2a5e180, 31, 1, 32;
+L_0x2a5e280 .part RS_0x7f507e9b8ff8, 30, 1;
+L_0x2a5e320 .part RS_0x7f507e9b8fc8, 31, 1;
+L_0x2b14240 .part/pv L_0x2b14060, 0, 1, 32;
+L_0x2a61c30 .part v0x2960210_0, 0, 1;
+L_0x2a61d60 .part v0x2960210_0, 1, 1;
+L_0x2a61e90 .part RS_0x7f507e9ad5c8, 0, 1;
+L_0x2a61f30 .part RS_0x7f507e9ad5c8, 0, 1;
+L_0x2a61fd0 .part RS_0x7f507e9a3368, 0, 1;
+L_0x2a620c0 .part RS_0x7f507e9b8c98, 0, 1;
+L_0x2a62950 .part/pv L_0x2a62740, 0, 1, 32;
+L_0x2a629f0 .part v0x2960210_0, 0, 1;
+L_0x2a62b20 .part v0x2960210_0, 1, 1;
+L_0x2a62c50 .part RS_0x7f507e9a6998, 0, 1;
+L_0x2a62cf0 .part RS_0x7f507e9a6998, 0, 1;
+L_0x2a62d90 .part RS_0x7f507e9a3368, 0, 1;
+L_0x2a62e80 .part RS_0x7f507e9a3368, 0, 1;
+L_0x2b15ad0 .part/pv L_0x2b15990, 0, 1, 32;
+L_0x2a3ade0 .part v0x2960210_0, 2, 1;
+L_0x2a3ae80 .part RS_0x7f507e9b8f68, 0, 1;
+L_0x2a3af70 .part RS_0x7f507e9b8f98, 0, 1;
+L_0x2a3b060 .part/pv L_0x2a3b100, 0, 1, 32;
+L_0x2a254f0 .part RS_0x7f507e9b8fc8, 0, 1;
+L_0x2a25590 .part RS_0x7f507e9b8fc8, 0, 1;
+L_0x2a25770 .part RS_0x7f507e9b8ff8, 31, 1;
+S_0x2864a60 .scope module, "test" "SLT32" 3 385, 3 298, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2863d28 .param/l "size" 3 330, +C4<0100000>;
+L_0x2aa2e90/d .functor NOT 1, L_0x2aa2f80, C4<0>, C4<0>, C4<0>;
+L_0x2aa2e90 .delay (10000,10000,10000) L_0x2aa2e90/d;
+L_0x2aa3020/d .functor AND 1, L_0x2aa3160, L_0x2aa3200, L_0x2aa2e90, C4<1>;
+L_0x2aa3020 .delay (20000,20000,20000) L_0x2aa3020/d;
+L_0x2a82310/d .functor OR 1, L_0x2a82400, C4<0>, C4<0>, C4<0>;
+L_0x2a82310 .delay (20000,20000,20000) L_0x2a82310/d;
+L_0x2aa45c0/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x2aa14e0, C4<0>, C4<0>;
+L_0x2aa45c0 .delay (40000,40000,40000) L_0x2aa45c0/d;
+L_0x2aa1580/d .functor NOT 1, RS_0x7f507e9ad718, C4<0>, C4<0>, C4<0>;
+L_0x2aa1580 .delay (10000,10000,10000) L_0x2aa1580/d;
+L_0x2aa46b0/d .functor NOT 1, L_0x2aa5c00, C4<0>, C4<0>, C4<0>;
+L_0x2aa46b0 .delay (10000,10000,10000) L_0x2aa46b0/d;
+L_0x2aa5ca0/d .functor AND 1, L_0x2aa1580, L_0x2aa5de0, C4<1>, C4<1>;
+L_0x2aa5ca0 .delay (20000,20000,20000) L_0x2aa5ca0/d;
+L_0x2aa5e80/d .functor AND 1, RS_0x7f507e9ad718, L_0x2aa46b0, C4<1>, C4<1>;
+L_0x2aa5e80 .delay (20000,20000,20000) L_0x2aa5e80/d;
+L_0x2a82640/d .functor AND 1, L_0x2aa5ca0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a82640 .delay (20000,20000,20000) L_0x2a82640/d;
+L_0x2a82760/d .functor AND 1, L_0x2aa5e80, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a82760 .delay (20000,20000,20000) L_0x2a82760/d;
+L_0x2a828d0/d .functor OR 1, L_0x2a82640, L_0x2a82760, C4<0>, C4<0>;
+L_0x2a828d0 .delay (20000,20000,20000) L_0x2a828d0/d;
+v0x289ef10_0 .alias "A", 31 0, v0x295f580_0;
+RS_0x7f507e9b8ba8/0/0 .resolv tri, L_0x2881940, L_0x2a64e50, L_0x2a66f90, L_0x2a69140;
+RS_0x7f507e9b8ba8/0/4 .resolv tri, L_0x2a6b2b0, L_0x2a6d320, L_0x2a6f570, L_0x2a717c0;
+RS_0x7f507e9b8ba8/0/8 .resolv tri, L_0x2a73aa0, L_0x2a75cd0, L_0x2a77ec0, L_0x2a7a150;
+RS_0x7f507e9b8ba8/0/12 .resolv tri, L_0x2a7c2b0, L_0x2a7e3f0, L_0x2a80640, L_0x2a82a10;
+RS_0x7f507e9b8ba8/0/16 .resolv tri, L_0x2a601e0, L_0x2a87810, L_0x2a89a20, L_0x2a8bbf0;
+RS_0x7f507e9b8ba8/0/20 .resolv tri, L_0x2a8ddd0, L_0x2a8ffa0, L_0x2a90f40, L_0x2a94770;
+RS_0x7f507e9b8ba8/0/24 .resolv tri, L_0x2a94f50, L_0x2a972e0, L_0x2a99910, L_0x2a9bcc0;
+RS_0x7f507e9b8ba8/0/28 .resolv tri, L_0x2a9dd00, L_0x2aa0090, L_0x2aa20b0, L_0x2aa4350;
+RS_0x7f507e9b8ba8/1/0 .resolv tri, RS_0x7f507e9b8ba8/0/0, RS_0x7f507e9b8ba8/0/4, RS_0x7f507e9b8ba8/0/8, RS_0x7f507e9b8ba8/0/12;
+RS_0x7f507e9b8ba8/1/4 .resolv tri, RS_0x7f507e9b8ba8/0/16, RS_0x7f507e9b8ba8/0/20, RS_0x7f507e9b8ba8/0/24, RS_0x7f507e9b8ba8/0/28;
+RS_0x7f507e9b8ba8 .resolv tri, RS_0x7f507e9b8ba8/1/0, RS_0x7f507e9b8ba8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2604180_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9b8ba8; 32 drivers
+v0x289f0e0_0 .alias "B", 31 0, v0x295f6a0_0;
+RS_0x7f507e9b8bd8/0/0 .resolv tri, L_0x2a5fbf0, L_0x2a645e0, L_0x2a66770, L_0x2a67820;
+RS_0x7f507e9b8bd8/0/4 .resolv tri, L_0x2a6aa90, L_0x2a6ba50, L_0x2a6ed30, L_0x2a6fd60;
+RS_0x7f507e9b8bd8/0/8 .resolv tri, L_0x2a73280, L_0x2a74270, L_0x2a776b0, L_0x2a78a90;
+RS_0x7f507e9b8bd8/0/12 .resolv tri, L_0x2a7ba90, L_0x2a7ca90, L_0x2a7fe10, L_0x2a80e30;
+RS_0x7f507e9b8bd8/0/16 .resolv tri, L_0x2a84600, L_0x2a85cc0, L_0x2a891e0, L_0x2a89bb0;
+RS_0x7f507e9b8bd8/0/20 .resolv tri, L_0x2a8d5c0, L_0x2a8df60, L_0x2a91d70, L_0x2a92720;
+RS_0x7f507e9b8bd8/0/24 .resolv tri, L_0x2a96140, L_0x2a96b00, L_0x2a9a4f0, L_0x2a9b4e0;
+RS_0x7f507e9b8bd8/0/28 .resolv tri, L_0x2a9e8f0, L_0x2a9f8b0, L_0x2aa2cb0, L_0x2aa5300;
+RS_0x7f507e9b8bd8/1/0 .resolv tri, RS_0x7f507e9b8bd8/0/0, RS_0x7f507e9b8bd8/0/4, RS_0x7f507e9b8bd8/0/8, RS_0x7f507e9b8bd8/0/12;
+RS_0x7f507e9b8bd8/1/4 .resolv tri, RS_0x7f507e9b8bd8/0/16, RS_0x7f507e9b8bd8/0/20, RS_0x7f507e9b8bd8/0/24, RS_0x7f507e9b8bd8/0/28;
+RS_0x7f507e9b8bd8 .resolv tri, RS_0x7f507e9b8bd8/1/0, RS_0x7f507e9b8bd8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x25ee970_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9b8bd8; 32 drivers
+v0x289f2a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+RS_0x7f507e9b8c08/0/0 .resolv tri, L_0x2a5fb00, L_0x2a64480, L_0x2a66680, L_0x2a687b0;
+RS_0x7f507e9b8c08/0/4 .resolv tri, L_0x2a6a9a0, L_0x2a6ca50, L_0x2a6ec40, L_0x2a70db0;
+RS_0x7f507e9b8c08/0/8 .resolv tri, L_0x2a73190, L_0x2a75380, L_0x2a775c0, L_0x2a79880;
+RS_0x7f507e9b8c08/0/12 .resolv tri, L_0x2a7b9a0, L_0x2a7daf0, L_0x2a7fd20, L_0x2a81f10;
+RS_0x7f507e9b8c08/0/16 .resolv tri, L_0x2a84510, L_0x2a86ee0, L_0x2a890f0, L_0x2a8b2c0;
+RS_0x7f507e9b8c08/0/20 .resolv tri, L_0x2a8d4d0, L_0x2a8f6a0, L_0x2a91c80, L_0x2a93e60;
+RS_0x7f507e9b8c08/0/24 .resolv tri, L_0x2a96050, L_0x2a98210, L_0x2a9a400, L_0x2a9c5e0;
+RS_0x7f507e9b8c08/0/28 .resolv tri, L_0x2a9e800, L_0x2aa09b0, L_0x2aa2bc0, L_0x2aa5210;
+RS_0x7f507e9b8c08/1/0 .resolv tri, RS_0x7f507e9b8c08/0/0, RS_0x7f507e9b8c08/0/4, RS_0x7f507e9b8c08/0/8, RS_0x7f507e9b8c08/0/12;
+RS_0x7f507e9b8c08/1/4 .resolv tri, RS_0x7f507e9b8c08/0/16, RS_0x7f507e9b8c08/0/20, RS_0x7f507e9b8c08/0/24, RS_0x7f507e9b8c08/0/28;
+RS_0x7f507e9b8c08 .resolv tri, RS_0x7f507e9b8c08/1/0, RS_0x7f507e9b8c08/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x289f320_0 .net8 "NewVal", 31 0, RS_0x7f507e9b8c08; 32 drivers
+v0x289f3c0_0 .net "Res0OF1", 0 0, L_0x2aa5e80; 1 drivers
+v0x289f460_0 .net "Res1OF0", 0 0, L_0x2aa5ca0; 1 drivers
+v0x289f500_0 .alias "SLTSum", 31 0, v0x2960440_0;
+v0x289f5a0_0 .alias "SLTflag", 0 0, v0x29604c0_0;
+v0x289f620_0 .net "SLTflag0", 0 0, L_0x2a82640; 1 drivers
+v0x289f6c0_0 .net "SLTflag1", 0 0, L_0x2a82760; 1 drivers
+v0x289f760_0 .net "SLTon", 0 0, L_0x2aa3020; 1 drivers
+v0x289f7e0_0 .net *"_s497", 0 0, L_0x2aa2f80; 1 drivers
+v0x289f900_0 .net *"_s499", 0 0, L_0x2aa3160; 1 drivers
+v0x289f9a0_0 .net *"_s501", 0 0, L_0x2aa3200; 1 drivers
+v0x289f860_0 .net *"_s521", 0 0, L_0x2a82400; 1 drivers
+v0x289faf0_0 .net/s *"_s522", 0 0, C4<0>; 1 drivers
+v0x289fc10_0 .net *"_s525", 0 0, L_0x2aa14e0; 1 drivers
+v0x289fc90_0 .net *"_s527", 0 0, L_0x2aa5c00; 1 drivers
+v0x289fb70_0 .net *"_s529", 0 0, L_0x2aa5de0; 1 drivers
+v0x289fdc0_0 .alias "carryin", 31 0, v0x295fa50_0;
+v0x289fd10_0 .alias "carryout", 0 0, v0x2960870_0;
+v0x289ff00_0 .net "nAddSubSLTSum", 0 0, L_0x2aa46b0; 1 drivers
+v0x289fe40_0 .net "nCmd2", 0 0, L_0x2aa2e90; 1 drivers
+v0x28a0050_0 .net "nOF", 0 0, L_0x2aa1580; 1 drivers
+v0x289ff80_0 .alias "overflow", 0 0, v0x2960980_0;
+v0x28a01b0_0 .alias "subtract", 31 0, v0x2960aa0_0;
+L_0x2a5fb00 .part/pv L_0x2a5ee60, 1, 1, 32;
+L_0x2a5fbf0 .part/pv L_0x2a5f9c0, 1, 1, 32;
+L_0x2a5fce0 .part/pv L_0x2a5eb90, 1, 1, 32;
+L_0x2a5fdd0 .part v0x295fe90_0, 1, 1;
+L_0x2a5fe70 .part v0x2960190_0, 1, 1;
+L_0x2a5ffa0 .part RS_0x7f507e9b8bd8, 0, 1;
+L_0x2881940 .part/pv L_0x2a60ad0, 1, 1, 32;
+L_0x2881a30 .part RS_0x7f507e9b8c08, 1, 1;
+L_0x2a632c0 .part/pv L_0x2a63180, 1, 1, 32;
+L_0x2a63360 .part RS_0x7f507e9b8ba8, 1, 1;
+L_0x2a63500 .part RS_0x7f507e9b8ba8, 1, 1;
+L_0x2a64480 .part/pv L_0x2a63ff0, 2, 1, 32;
+L_0x2a645e0 .part/pv L_0x2a64340, 2, 1, 32;
+L_0x2a646d0 .part/pv L_0x2a63d20, 2, 1, 32;
+L_0x2a64840 .part v0x295fe90_0, 2, 1;
+L_0x2a648e0 .part v0x2960190_0, 2, 1;
+L_0x2a64aa0 .part RS_0x7f507e9b8bd8, 1, 1;
+L_0x2a64e50 .part/pv L_0x2a64d10, 2, 1, 32;
+L_0x2a65020 .part RS_0x7f507e9b8c08, 2, 1;
+L_0x2a65500 .part/pv L_0x2a653c0, 2, 1, 32;
+L_0x2a64f80 .part RS_0x7f507e9b8ba8, 2, 1;
+L_0x2a656a0 .part RS_0x7f507e9b8ba8, 2, 1;
+L_0x2a66680 .part/pv L_0x2a661f0, 3, 1, 32;
+L_0x2a66770 .part/pv L_0x2a66540, 3, 1, 32;
+L_0x2a65790 .part/pv L_0x2a65f20, 3, 1, 32;
+L_0x2a66980 .part v0x295fe90_0, 3, 1;
+L_0x2a66860 .part v0x2960190_0, 3, 1;
+L_0x2a66b90 .part RS_0x7f507e9b8bd8, 2, 1;
+L_0x2a66f90 .part/pv L_0x2a66e50, 3, 1, 32;
+L_0x2a67030 .part RS_0x7f507e9b8c08, 3, 1;
+L_0x2a67580 .part/pv L_0x2a67440, 3, 1, 32;
+L_0x2a67620 .part RS_0x7f507e9b8ba8, 3, 1;
+L_0x2a67120 .part RS_0x7f507e9b8ba8, 3, 1;
+L_0x2a687b0 .part/pv L_0x2a68320, 4, 1, 32;
+L_0x2a67820 .part/pv L_0x2a68670, 4, 1, 32;
+L_0x2a689c0 .part/pv L_0x2a68050, 4, 1, 32;
+L_0x2a688a0 .part v0x295fe90_0, 4, 1;
+L_0x2a68be0 .part v0x2960190_0, 4, 1;
+L_0x2a68ab0 .part RS_0x7f507e9b8bd8, 3, 1;
+L_0x2a69140 .part/pv L_0x2a69000, 4, 1, 32;
+L_0x2a68d10 .part RS_0x7f507e9b8c08, 4, 1;
+L_0x2a697f0 .part/pv L_0x2a696b0, 4, 1, 32;
+L_0x2a691e0 .part RS_0x7f507e9b8ba8, 4, 1;
+L_0x2a699f0 .part RS_0x7f507e9b8ba8, 4, 1;
+L_0x2a6a9a0 .part/pv L_0x2a6a510, 5, 1, 32;
+L_0x2a6aa90 .part/pv L_0x2a6a860, 5, 1, 32;
+L_0x2a69a90 .part/pv L_0x2a6a240, 5, 1, 32;
+L_0x2a6ad00 .part v0x295fe90_0, 5, 1;
+L_0x2a6ab80 .part v0x2960190_0, 5, 1;
+L_0x2a6af30 .part RS_0x7f507e9b8bd8, 4, 1;
+L_0x2a6b2b0 .part/pv L_0x2a6b170, 5, 1, 32;
+L_0x2a6b350 .part RS_0x7f507e9b8c08, 5, 1;
+L_0x2a6b8c0 .part/pv L_0x2a6b780, 5, 1, 32;
+L_0x2a6b960 .part RS_0x7f507e9b8ba8, 5, 1;
+L_0x2a6b440 .part RS_0x7f507e9b8ba8, 5, 1;
+L_0x2a6ca50 .part/pv L_0x2a6c5c0, 6, 1, 32;
+L_0x2a6ba50 .part/pv L_0x2a6c910, 6, 1, 32;
+L_0x2a6bb40 .part/pv L_0x2a6c2f0, 6, 1, 32;
+L_0x2a6cb40 .part v0x295fe90_0, 6, 1;
+L_0x2a6cbe0 .part v0x2960190_0, 6, 1;
+L_0x2a6cf50 .part RS_0x7f507e9b8bd8, 5, 1;
+L_0x2a6d320 .part/pv L_0x2a6d1e0, 6, 1, 32;
+L_0x2a67710 .part RS_0x7f507e9b8c08, 6, 1;
+L_0x2a6daa0 .part/pv L_0x2a6d960, 6, 1, 32;
+L_0x2a6d5d0 .part RS_0x7f507e9b8ba8, 6, 1;
+L_0x2a6d6c0 .part RS_0x7f507e9b8ba8, 6, 1;
+L_0x2a6ec40 .part/pv L_0x2a6e7b0, 7, 1, 32;
+L_0x2a6ed30 .part/pv L_0x2a6eb00, 7, 1, 32;
+L_0x2a6db40 .part/pv L_0x2a6e4e0, 7, 1, 32;
+L_0x2a6dc30 .part v0x295fe90_0, 7, 1;
+L_0x2a6f060 .part v0x2960190_0, 7, 1;
+L_0x2a6f100 .part RS_0x7f507e9b8bd8, 6, 1;
+L_0x2a6f570 .part/pv L_0x2a6f430, 7, 1, 32;
+L_0x2a6f610 .part RS_0x7f507e9b8c08, 7, 1;
+L_0x2a6fbd0 .part/pv L_0x2a6fa90, 7, 1, 32;
+L_0x2a6fc70 .part RS_0x7f507e9b8ba8, 7, 1;
+L_0x2a6f700 .part RS_0x7f507e9b8ba8, 7, 1;
+L_0x2a70db0 .part/pv L_0x2a708e0, 8, 1, 32;
+L_0x2a6fd60 .part/pv L_0x2a70c50, 8, 1, 32;
+L_0x2a6fe50 .part/pv L_0x2a70610, 8, 1, 32;
+L_0x2a71130 .part v0x295fe90_0, 8, 1;
+L_0x2a711d0 .part v0x2960190_0, 8, 1;
+L_0x2a70ea0 .part RS_0x7f507e9b8bd8, 7, 1;
+L_0x2a717c0 .part/pv L_0x2a71090, 8, 1, 32;
+L_0x2a71270 .part RS_0x7f507e9b8c08, 8, 1;
+L_0x2a71ef0 .part/pv L_0x2a71db0, 8, 1, 32;
+L_0x2a71860 .part RS_0x7f507e9b8ba8, 8, 1;
+L_0x2a71950 .part RS_0x7f507e9b8ba8, 8, 1;
+L_0x2a73190 .part/pv L_0x2a72ce0, 9, 1, 32;
+L_0x2a73280 .part/pv L_0x2a73030, 9, 1, 32;
+L_0x2a71f90 .part/pv L_0x2a72a10, 9, 1, 32;
+L_0x2a72080 .part v0x295fe90_0, 9, 1;
+L_0x2a72120 .part v0x2960190_0, 9, 1;
+L_0x2a73660 .part RS_0x7f507e9b8bd8, 8, 1;
+L_0x2a73aa0 .part/pv L_0x2a735c0, 9, 1, 32;
+L_0x2a73b40 .part RS_0x7f507e9b8c08, 9, 1;
+L_0x2a740e0 .part/pv L_0x2a73fa0, 9, 1, 32;
+L_0x2a74180 .part RS_0x7f507e9b8ba8, 9, 1;
+L_0x2a73c30 .part RS_0x7f507e9b8ba8, 9, 1;
+L_0x2a75380 .part/pv L_0x2a74ed0, 10, 1, 32;
+L_0x2a74270 .part/pv L_0x2a75220, 10, 1, 32;
+L_0x2a74360 .part/pv L_0x2a74c00, 10, 1, 32;
+L_0x2a74450 .part v0x295fe90_0, 10, 1;
+L_0x2a744f0 .part v0x2960190_0, 10, 1;
+L_0x2a75470 .part RS_0x7f507e9b8bd8, 9, 1;
+L_0x2a75cd0 .part/pv L_0x2a75b90, 10, 1, 32;
+L_0x2a75840 .part RS_0x7f507e9b8c08, 10, 1;
+L_0x2a76340 .part/pv L_0x2a76200, 10, 1, 32;
+L_0x2a75d70 .part RS_0x7f507e9b8ba8, 10, 1;
+L_0x2a75e60 .part RS_0x7f507e9b8ba8, 10, 1;
+L_0x2a775c0 .part/pv L_0x2a770f0, 11, 1, 32;
+L_0x2a776b0 .part/pv L_0x2a77460, 11, 1, 32;
+L_0x2a763e0 .part/pv L_0x2a76e20, 11, 1, 32;
+L_0x2a764d0 .part v0x295fe90_0, 11, 1;
+L_0x2a76570 .part v0x2960190_0, 11, 1;
+L_0x2a766a0 .part RS_0x7f507e9b8bd8, 10, 1;
+L_0x2a77ec0 .part/pv L_0x2a77d80, 11, 1, 32;
+L_0x2a77f60 .part RS_0x7f507e9b8c08, 11, 1;
+L_0x2a784f0 .part/pv L_0x2a77af0, 11, 1, 32;
+L_0x2a78590 .part RS_0x7f507e9b8ba8, 11, 1;
+L_0x2a6d3c0 .part RS_0x7f507e9b8ba8, 11, 1;
+L_0x2a79880 .part/pv L_0x2a793f0, 12, 1, 32;
+L_0x2a78a90 .part/pv L_0x2a79740, 12, 1, 32;
+L_0x2a78b80 .part/pv L_0x2a79120, 12, 1, 32;
+L_0x2a78c70 .part v0x295fe90_0, 12, 1;
+L_0x2a78d10 .part v0x2960190_0, 12, 1;
+L_0x2a79d70 .part RS_0x7f507e9b8bd8, 11, 1;
+L_0x2a7a150 .part/pv L_0x2a7a010, 12, 1, 32;
+L_0x2a79970 .part RS_0x7f507e9b8c08, 12, 1;
+L_0x2a7a7e0 .part/pv L_0x2a7a6a0, 12, 1, 32;
+L_0x2a7a1f0 .part RS_0x7f507e9b8ba8, 12, 1;
+L_0x2a7a2e0 .part RS_0x7f507e9b8ba8, 12, 1;
+L_0x2a7b9a0 .part/pv L_0x2a7b510, 13, 1, 32;
+L_0x2a7ba90 .part/pv L_0x2a7b860, 13, 1, 32;
+L_0x2a7a880 .part/pv L_0x2a7b240, 13, 1, 32;
+L_0x2a7a970 .part v0x295fe90_0, 13, 1;
+L_0x2a7aa10 .part v0x2960190_0, 13, 1;
+L_0x2a7ab40 .part RS_0x7f507e9b8bd8, 12, 1;
+L_0x2a7c2b0 .part/pv L_0x2a7c170, 13, 1, 32;
+L_0x2a7c350 .part RS_0x7f507e9b8c08, 13, 1;
+L_0x2a7c900 .part/pv L_0x2a7bed0, 13, 1, 32;
+L_0x2a7c9a0 .part RS_0x7f507e9b8ba8, 13, 1;
+L_0x2a7c440 .part RS_0x7f507e9b8ba8, 13, 1;
+L_0x2a7daf0 .part/pv L_0x2a7d640, 14, 1, 32;
+L_0x2a7ca90 .part/pv L_0x2a7d990, 14, 1, 32;
+L_0x2a7cb80 .part/pv L_0x2a7d370, 14, 1, 32;
+L_0x2a7cc70 .part v0x295fe90_0, 14, 1;
+L_0x2a7cd10 .part v0x2960190_0, 14, 1;
+L_0x2a7ce40 .part RS_0x7f507e9b8bd8, 13, 1;
+L_0x2a7e3f0 .part/pv L_0x2a7e280, 14, 1, 32;
+L_0x2a7dbe0 .part RS_0x7f507e9b8c08, 14, 1;
+L_0x2a7ea90 .part/pv L_0x2a7e950, 14, 1, 32;
+L_0x2a7e490 .part RS_0x7f507e9b8ba8, 14, 1;
+L_0x2a7e530 .part RS_0x7f507e9b8ba8, 14, 1;
+L_0x2a7fd20 .part/pv L_0x2a7f810, 15, 1, 32;
+L_0x2a7fe10 .part/pv L_0x2a7fbc0, 15, 1, 32;
+L_0x2a7eb30 .part/pv L_0x2a7f540, 15, 1, 32;
+L_0x2a7ec20 .part v0x295fe90_0, 15, 1;
+L_0x2a7ecc0 .part v0x2960190_0, 15, 1;
+L_0x2a7edf0 .part RS_0x7f507e9b8bd8, 14, 1;
+L_0x2a80640 .part/pv L_0x2a80500, 15, 1, 32;
+L_0x2a806e0 .part RS_0x7f507e9b8c08, 15, 1;
+L_0x2a80cf0 .part/pv L_0x2a80250, 15, 1, 32;
+L_0x2a80d90 .part RS_0x7f507e9b8ba8, 15, 1;
+L_0x2a807d0 .part RS_0x7f507e9b8ba8, 15, 1;
+L_0x2a81f10 .part/pv L_0x2a81a30, 16, 1, 32;
+L_0x2a80e30 .part/pv L_0x2a81db0, 16, 1, 32;
+L_0x2a80f20 .part/pv L_0x2a81760, 16, 1, 32;
+L_0x2a81010 .part v0x295fe90_0, 16, 1;
+L_0x2a810b0 .part v0x2960190_0, 16, 1;
+L_0x2a811e0 .part RS_0x7f507e9b8bd8, 15, 1;
+L_0x2a82a10 .part/pv L_0x2a71680, 16, 1, 32;
+L_0x2a82000 .part RS_0x7f507e9b8c08, 16, 1;
+L_0x2a83250 .part/pv L_0x2a83110, 16, 1, 32;
+L_0x2a82ab0 .part RS_0x7f507e9b8ba8, 16, 1;
+L_0x2a82ba0 .part RS_0x7f507e9b8ba8, 16, 1;
+L_0x2a84510 .part/pv L_0x2a84000, 17, 1, 32;
+L_0x2a84600 .part/pv L_0x2a843b0, 17, 1, 32;
+L_0x2a832f0 .part/pv L_0x2a83d30, 17, 1, 32;
+L_0x2a833e0 .part v0x295fe90_0, 17, 1;
+L_0x2a83480 .part v0x2960190_0, 17, 1;
+L_0x2a835b0 .part RS_0x7f507e9b8bd8, 16, 1;
+L_0x2a601e0 .part/pv L_0x2a600a0, 17, 1, 32;
+L_0x2a60280 .part RS_0x7f507e9b8c08, 17, 1;
+L_0x2a846f0 .part/pv L_0x2a606e0, 17, 1, 32;
+L_0x2a84790 .part RS_0x7f507e9b8ba8, 17, 1;
+L_0x2a84880 .part RS_0x7f507e9b8ba8, 17, 1;
+L_0x2a86ee0 .part/pv L_0x2a86a30, 18, 1, 32;
+L_0x2a85cc0 .part/pv L_0x2a86d80, 18, 1, 32;
+L_0x2a85db0 .part/pv L_0x2a86760, 18, 1, 32;
+L_0x2a85ea0 .part v0x295fe90_0, 18, 1;
+L_0x2a85f40 .part v0x2960190_0, 18, 1;
+L_0x2a86070 .part RS_0x7f507e9b8bd8, 17, 1;
+L_0x2a87810 .part/pv L_0x2a876d0, 18, 1, 32;
+L_0x2a86fd0 .part RS_0x7f507e9b8c08, 18, 1;
+L_0x2a87ed0 .part/pv L_0x2a71b60, 18, 1, 32;
+L_0x2a878b0 .part RS_0x7f507e9b8ba8, 18, 1;
+L_0x2a879a0 .part RS_0x7f507e9b8ba8, 18, 1;
+L_0x2a890f0 .part/pv L_0x2a88be0, 19, 1, 32;
+L_0x2a891e0 .part/pv L_0x2a88f90, 19, 1, 32;
+L_0x2a87f70 .part/pv L_0x2a88910, 19, 1, 32;
+L_0x2a88060 .part v0x295fe90_0, 19, 1;
+L_0x2a88100 .part v0x2960190_0, 19, 1;
+L_0x2a88230 .part RS_0x7f507e9b8bd8, 18, 1;
+L_0x2a89a20 .part/pv L_0x2a88520, 19, 1, 32;
+L_0x2a89ac0 .part RS_0x7f507e9b8c08, 19, 1;
+L_0x2a89760 .part/pv L_0x2a89620, 19, 1, 32;
+L_0x2a89800 .part RS_0x7f507e9b8ba8, 19, 1;
+L_0x2a8a240 .part RS_0x7f507e9b8ba8, 19, 1;
+L_0x2a8b2c0 .part/pv L_0x2a8ae10, 20, 1, 32;
+L_0x2a89bb0 .part/pv L_0x2a8b160, 20, 1, 32;
+L_0x2a89ca0 .part/pv L_0x2a8ab40, 20, 1, 32;
+L_0x2a89d90 .part v0x295fe90_0, 20, 1;
+L_0x2a89e30 .part v0x2960190_0, 20, 1;
+L_0x2a89f60 .part RS_0x7f507e9b8bd8, 19, 1;
+L_0x2a8bbf0 .part/pv L_0x2a8bab0, 20, 1, 32;
+L_0x2a8b3b0 .part RS_0x7f507e9b8c08, 20, 1;
+L_0x2a871e0 .part/pv L_0x2a8b9b0, 20, 1, 32;
+L_0x2a8c370 .part RS_0x7f507e9b8ba8, 20, 1;
+L_0x2a8c410 .part RS_0x7f507e9b8ba8, 20, 1;
+L_0x2a8d4d0 .part/pv L_0x2a8d040, 21, 1, 32;
+L_0x2a8d5c0 .part/pv L_0x2a8d390, 21, 1, 32;
+L_0x2a8c500 .part/pv L_0x2a8cd70, 21, 1, 32;
+L_0x2a8c5f0 .part v0x295fe90_0, 21, 1;
+L_0x2a8c690 .part v0x2960190_0, 21, 1;
+L_0x2a8c7c0 .part RS_0x7f507e9b8bd8, 20, 1;
+L_0x2a8ddd0 .part/pv L_0x2a8cab0, 21, 1, 32;
+L_0x2a8de70 .part RS_0x7f507e9b8c08, 21, 1;
+L_0x2a8db40 .part/pv L_0x2a8da00, 21, 1, 32;
+L_0x2a8dbe0 .part RS_0x7f507e9b8ba8, 21, 1;
+L_0x2a8dcd0 .part RS_0x7f507e9b8ba8, 21, 1;
+L_0x2a8f6a0 .part/pv L_0x2a8f1f0, 22, 1, 32;
+L_0x2a8df60 .part/pv L_0x2a8f540, 22, 1, 32;
+L_0x2a8e050 .part/pv L_0x2a8ef20, 22, 1, 32;
+L_0x2a8e140 .part v0x295fe90_0, 22, 1;
+L_0x2a8e1e0 .part v0x2960190_0, 22, 1;
+L_0x2a8e310 .part RS_0x7f507e9b8bd8, 21, 1;
+L_0x2a8ffa0 .part/pv L_0x2a8e600, 22, 1, 32;
+L_0x2a78680 .part RS_0x7f507e9b8c08, 22, 1;
+L_0x2a8f910 .part/pv L_0x2a8f7d0, 22, 1, 32;
+L_0x2a8f9b0 .part RS_0x7f507e9b8ba8, 22, 1;
+L_0x2a8faa0 .part RS_0x7f507e9b8ba8, 22, 1;
+L_0x2a91c80 .part/pv L_0x2a917d0, 23, 1, 32;
+L_0x2a91d70 .part/pv L_0x2a91b20, 23, 1, 32;
+L_0x2a90850 .part/pv L_0x2a91500, 23, 1, 32;
+L_0x2a90940 .part v0x295fe90_0, 23, 1;
+L_0x2a909e0 .part v0x2960190_0, 23, 1;
+L_0x2a90b10 .part RS_0x7f507e9b8bd8, 22, 1;
+L_0x2a90f40 .part/pv L_0x2a90e00, 23, 1, 32;
+L_0x2a92630 .part RS_0x7f507e9b8c08, 23, 1;
+L_0x2a922f0 .part/pv L_0x2a921b0, 23, 1, 32;
+L_0x2a92390 .part RS_0x7f507e9b8ba8, 23, 1;
+L_0x2a92480 .part RS_0x7f507e9b8ba8, 23, 1;
+L_0x2a93e60 .part/pv L_0x2a939b0, 24, 1, 32;
+L_0x2a92720 .part/pv L_0x2a93d00, 24, 1, 32;
+L_0x2a92810 .part/pv L_0x2a936e0, 24, 1, 32;
+L_0x2a92900 .part v0x295fe90_0, 24, 1;
+L_0x2a929a0 .part v0x2960190_0, 24, 1;
+L_0x2a92ad0 .part RS_0x7f507e9b8bd8, 23, 1;
+L_0x2a94770 .part/pv L_0x2a92dc0, 24, 1, 32;
+L_0x2a93f50 .part RS_0x7f507e9b8c08, 24, 1;
+L_0x2a94650 .part/pv L_0x2a94510, 24, 1, 32;
+L_0x2a78800 .part RS_0x7f507e9b8ba8, 24, 1;
+L_0x2a788f0 .part RS_0x7f507e9b8ba8, 24, 1;
+L_0x2a96050 .part/pv L_0x2a95ba0, 25, 1, 32;
+L_0x2a96140 .part/pv L_0x2a95ef0, 25, 1, 32;
+L_0x2a94860 .part/pv L_0x2a958d0, 25, 1, 32;
+L_0x2a94950 .part v0x295fe90_0, 25, 1;
+L_0x2a949f0 .part v0x2960190_0, 25, 1;
+L_0x2a94b20 .part RS_0x7f507e9b8bd8, 24, 1;
+L_0x2a94f50 .part/pv L_0x2a94e10, 25, 1, 32;
+L_0x2a94ff0 .part RS_0x7f507e9b8c08, 25, 1;
+L_0x2a966a0 .part/pv L_0x2a96560, 25, 1, 32;
+L_0x2a96740 .part RS_0x7f507e9b8ba8, 25, 1;
+L_0x2a96830 .part RS_0x7f507e9b8ba8, 25, 1;
+L_0x2a98210 .part/pv L_0x2a97d60, 26, 1, 32;
+L_0x2a96b00 .part/pv L_0x2a980b0, 26, 1, 32;
+L_0x2a96bf0 .part/pv L_0x2a97a90, 26, 1, 32;
+L_0x2a96ce0 .part v0x295fe90_0, 26, 1;
+L_0x2a96d80 .part v0x2960190_0, 26, 1;
+L_0x2a96eb0 .part RS_0x7f507e9b8bd8, 25, 1;
+L_0x2a972e0 .part/pv L_0x2a971a0, 26, 1, 32;
+L_0x2a98be0 .part RS_0x7f507e9b8c08, 26, 1;
+L_0x2a99180 .part/pv L_0x2a99040, 26, 1, 32;
+L_0x2a98300 .part RS_0x7f507e9b8ba8, 26, 1;
+L_0x2a983f0 .part RS_0x7f507e9b8ba8, 26, 1;
+L_0x2a9a400 .part/pv L_0x2a99f70, 27, 1, 32;
+L_0x2a9a4f0 .part/pv L_0x2a9a2c0, 27, 1, 32;
+L_0x2a99220 .part/pv L_0x2a99ca0, 27, 1, 32;
+L_0x2a99310 .part v0x295fe90_0, 27, 1;
+L_0x2a993b0 .part v0x2960190_0, 27, 1;
+L_0x2a994e0 .part RS_0x7f507e9b8bd8, 26, 1;
+L_0x2a99910 .part/pv L_0x2a997d0, 27, 1, 32;
+L_0x2a999b0 .part RS_0x7f507e9b8c08, 27, 1;
+L_0x2a9b350 .part/pv L_0x2a9b1e0, 27, 1, 32;
+L_0x2a9b3f0 .part RS_0x7f507e9b8ba8, 27, 1;
+L_0x2a9a5e0 .part RS_0x7f507e9b8ba8, 27, 1;
+L_0x2a9c5e0 .part/pv L_0x2a9c150, 28, 1, 32;
+L_0x2a9b4e0 .part/pv L_0x2a9c4a0, 28, 1, 32;
+L_0x2a9b5d0 .part/pv L_0x2a9bed0, 28, 1, 32;
+L_0x2a9b6c0 .part v0x295fe90_0, 28, 1;
+L_0x2a9b760 .part v0x2960190_0, 28, 1;
+L_0x2a9b890 .part RS_0x7f507e9b8bd8, 27, 1;
+L_0x2a9bcc0 .part/pv L_0x2a9bb80, 28, 1, 32;
+L_0x2a9bd60 .part RS_0x7f507e9b8c08, 28, 1;
+L_0x2a9d570 .part/pv L_0x2a9d430, 28, 1, 32;
+L_0x2a9c6d0 .part RS_0x7f507e9b8ba8, 28, 1;
+L_0x2a9c7c0 .part RS_0x7f507e9b8ba8, 28, 1;
+L_0x2a9e800 .part/pv L_0x2a9e370, 29, 1, 32;
+L_0x2a9e8f0 .part/pv L_0x2a9e6c0, 29, 1, 32;
+L_0x2a9d610 .part/pv L_0x2a9e0a0, 29, 1, 32;
+L_0x2a9d700 .part v0x295fe90_0, 29, 1;
+L_0x2a9d7a0 .part v0x2960190_0, 29, 1;
+L_0x2a9d8d0 .part RS_0x7f507e9b8bd8, 28, 1;
+L_0x2a9dd00 .part/pv L_0x2a9dbc0, 29, 1, 32;
+L_0x2a9dda0 .part RS_0x7f507e9b8c08, 29, 1;
+L_0x2a9f720 .part/pv L_0x2a9f5b0, 29, 1, 32;
+L_0x2a9f7c0 .part RS_0x7f507e9b8ba8, 29, 1;
+L_0x2a9e9e0 .part RS_0x7f507e9b8ba8, 29, 1;
+L_0x2aa09b0 .part/pv L_0x2aa0520, 30, 1, 32;
+L_0x2a9f8b0 .part/pv L_0x2aa0870, 30, 1, 32;
+L_0x2a9f9a0 .part/pv L_0x2a9f370, 30, 1, 32;
+L_0x2a9fa90 .part v0x295fe90_0, 30, 1;
+L_0x2a9fb30 .part v0x2960190_0, 30, 1;
+L_0x2a9fc60 .part RS_0x7f507e9b8bd8, 29, 1;
+L_0x2aa0090 .part/pv L_0x2a9ff50, 30, 1, 32;
+L_0x2aa0130 .part RS_0x7f507e9b8c08, 30, 1;
+L_0x2aa1920 .part/pv L_0x2aa17e0, 30, 1, 32;
+L_0x2aa0aa0 .part RS_0x7f507e9b8ba8, 30, 1;
+L_0x2aa0b90 .part RS_0x7f507e9b8ba8, 30, 1;
+L_0x2aa2bc0 .part/pv L_0x2aa2730, 31, 1, 32;
+L_0x2aa2cb0 .part/pv L_0x2aa2a80, 31, 1, 32;
+L_0x2aa19c0 .part/pv L_0x2aa1460, 31, 1, 32;
+L_0x2aa1ab0 .part v0x295fe90_0, 31, 1;
+L_0x2aa1b50 .part v0x2960190_0, 31, 1;
+L_0x2aa1c80 .part RS_0x7f507e9b8bd8, 30, 1;
+L_0x2aa20b0 .part/pv L_0x2aa1f70, 31, 1, 32;
+L_0x2aa2150 .part RS_0x7f507e9b8c08, 31, 1;
+L_0x2aa3ad0 .part/pv L_0x2aa3990, 31, 1, 32;
+L_0x2aa3b70 .part RS_0x7f507e9b8ba8, 31, 1;
+L_0x2aa2da0 .part RS_0x7f507e9b8ba8, 31, 1;
+L_0x2aa2f80 .part v0x2960210_0, 2, 1;
+L_0x2aa3160 .part v0x2960210_0, 0, 1;
+L_0x2aa3200 .part v0x2960210_0, 1, 1;
+L_0x2aa5210 .part/pv L_0x2aa4d30, 0, 1, 32;
+L_0x2aa5300 .part/pv L_0x2aa50b0, 0, 1, 32;
+L_0x2aa3c60 .part/pv L_0x2aa4a60, 0, 1, 32;
+L_0x2aa3d50 .part v0x295fe90_0, 0, 1;
+L_0x2aa3df0 .part v0x2960190_0, 0, 1;
+L_0x2aa3f20 .part RS_0x7f507e9ad748, 0, 1;
+L_0x2aa4350 .part/pv L_0x2aa4210, 0, 1, 32;
+L_0x2aa43f0 .part RS_0x7f507e9b8c08, 0, 1;
+L_0x2a82400 .part RS_0x7f507e9b8bd8, 31, 1;
+L_0x2aa14e0 .part RS_0x7f507e9b8bd8, 30, 1;
+L_0x2aa5c00 .part RS_0x7f507e9b8ba8, 31, 1;
+L_0x2aa5de0 .part RS_0x7f507e9b8c08, 31, 1;
+L_0x2aa7720 .part/pv L_0x2aa75e0, 0, 1, 32;
+L_0x2aa77c0 .part RS_0x7f507e9b8ba8, 0, 1;
+S_0x289def0 .scope module, "attempt2" "MiddleAddSubSLT" 3 326, 3 189, S_0x2864a60;
+ .timescale -9 -12;
+L_0x2aa32f0/d .functor NOT 1, L_0x2aa3df0, C4<0>, C4<0>, C4<0>;
+L_0x2aa32f0 .delay (10000,10000,10000) L_0x2aa32f0/d;
+L_0x2aa4900/d .functor NOT 1, L_0x2aa49c0, C4<0>, C4<0>, C4<0>;
+L_0x2aa4900 .delay (10000,10000,10000) L_0x2aa4900/d;
+L_0x2aa4a60/d .functor AND 1, L_0x2aa4ba0, L_0x2aa4900, C4<1>, C4<1>;
+L_0x2aa4a60 .delay (20000,20000,20000) L_0x2aa4a60/d;
+L_0x2aa4c40/d .functor XOR 1, L_0x2aa3d50, L_0x2aa37a0, C4<0>, C4<0>;
+L_0x2aa4c40 .delay (40000,40000,40000) L_0x2aa4c40/d;
+L_0x2aa4d30/d .functor XOR 1, L_0x2aa4c40, L_0x2aa3f20, C4<0>, C4<0>;
+L_0x2aa4d30 .delay (40000,40000,40000) L_0x2aa4d30/d;
+L_0x2aa4e20/d .functor AND 1, L_0x2aa3d50, L_0x2aa37a0, C4<1>, C4<1>;
+L_0x2aa4e20 .delay (20000,20000,20000) L_0x2aa4e20/d;
+L_0x2aa4fc0/d .functor AND 1, L_0x2aa4c40, L_0x2aa3f20, C4<1>, C4<1>;
+L_0x2aa4fc0 .delay (20000,20000,20000) L_0x2aa4fc0/d;
+L_0x2aa50b0/d .functor OR 1, L_0x2aa4e20, L_0x2aa4fc0, C4<0>, C4<0>;
+L_0x2aa50b0 .delay (20000,20000,20000) L_0x2aa50b0/d;
+v0x289e570_0 .net "A", 0 0, L_0x2aa3d50; 1 drivers
+v0x289e630_0 .net "AandB", 0 0, L_0x2aa4e20; 1 drivers
+v0x289e6d0_0 .net "AddSubSLTSum", 0 0, L_0x2aa4d30; 1 drivers
+v0x289e770_0 .net "AxorB", 0 0, L_0x2aa4c40; 1 drivers
+v0x289e7f0_0 .net "B", 0 0, L_0x2aa3df0; 1 drivers
+v0x289e8a0_0 .net "BornB", 0 0, L_0x2aa37a0; 1 drivers
+v0x289e960_0 .net "CINandAxorB", 0 0, L_0x2aa4fc0; 1 drivers
+v0x289e9e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x289ea60_0 .net *"_s3", 0 0, L_0x2aa49c0; 1 drivers
+v0x289eae0_0 .net *"_s5", 0 0, L_0x2aa4ba0; 1 drivers
+v0x289eb80_0 .net "carryin", 0 0, L_0x2aa3f20; 1 drivers
+v0x289ec20_0 .net "carryout", 0 0, L_0x2aa50b0; 1 drivers
+v0x289ecc0_0 .net "nB", 0 0, L_0x2aa32f0; 1 drivers
+v0x289ed70_0 .net "nCmd2", 0 0, L_0x2aa4900; 1 drivers
+v0x289ee70_0 .net "subtract", 0 0, L_0x2aa4a60; 1 drivers
+L_0x2aa4860 .part v0x2960210_0, 0, 1;
+L_0x2aa49c0 .part v0x2960210_0, 2, 1;
+L_0x2aa4ba0 .part v0x2960210_0, 0, 1;
+S_0x289dfe0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x289def0;
+ .timescale -9 -12;
+L_0x2aa34c0/d .functor NOT 1, L_0x2aa4860, C4<0>, C4<0>, C4<0>;
+L_0x2aa34c0 .delay (10000,10000,10000) L_0x2aa34c0/d;
+L_0x2aa3580/d .functor AND 1, L_0x2aa3df0, L_0x2aa34c0, C4<1>, C4<1>;
+L_0x2aa3580 .delay (20000,20000,20000) L_0x2aa3580/d;
+L_0x2aa3690/d .functor AND 1, L_0x2aa32f0, L_0x2aa4860, C4<1>, C4<1>;
+L_0x2aa3690 .delay (20000,20000,20000) L_0x2aa3690/d;
+L_0x2aa37a0/d .functor OR 1, L_0x2aa3580, L_0x2aa3690, C4<0>, C4<0>;
+L_0x2aa37a0 .delay (20000,20000,20000) L_0x2aa37a0/d;
+v0x289e0d0_0 .net "S", 0 0, L_0x2aa4860; 1 drivers
+v0x289e190_0 .alias "in0", 0 0, v0x289e7f0_0;
+v0x289e230_0 .alias "in1", 0 0, v0x289ecc0_0;
+v0x289e2d0_0 .net "nS", 0 0, L_0x2aa34c0; 1 drivers
+v0x289e350_0 .net "out0", 0 0, L_0x2aa3580; 1 drivers
+v0x289e3f0_0 .net "out1", 0 0, L_0x2aa3690; 1 drivers
+v0x289e4d0_0 .alias "outfinal", 0 0, v0x289e8a0_0;
+S_0x289d980 .scope module, "setSLTresult" "TwoInMux" 3 327, 3 109, S_0x2864a60;
+ .timescale -9 -12;
+L_0x2aa3fc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2aa3fc0 .delay (10000,10000,10000) L_0x2aa3fc0/d;
+L_0x2aa4060/d .functor AND 1, L_0x2aa43f0, L_0x2aa3fc0, C4<1>, C4<1>;
+L_0x2aa4060 .delay (20000,20000,20000) L_0x2aa4060/d;
+L_0x2aa4170/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2aa4170 .delay (20000,20000,20000) L_0x2aa4170/d;
+L_0x2aa4210/d .functor OR 1, L_0x2aa4060, L_0x2aa4170, C4<0>, C4<0>;
+L_0x2aa4210 .delay (20000,20000,20000) L_0x2aa4210/d;
+v0x289da70_0 .alias "S", 0 0, v0x289f760_0;
+v0x289db10_0 .net "in0", 0 0, L_0x2aa43f0; 1 drivers
+v0x289dbb0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x289dc50_0 .net "nS", 0 0, L_0x2aa3fc0; 1 drivers
+v0x289dcd0_0 .net "out0", 0 0, L_0x2aa4060; 1 drivers
+v0x289dd70_0 .net "out1", 0 0, L_0x2aa4170; 1 drivers
+v0x289de50_0 .net "outfinal", 0 0, L_0x2aa4210; 1 drivers
+S_0x289d410 .scope module, "FinalSLT" "TwoInMux" 3 354, 3 109, S_0x2864a60;
+ .timescale -9 -12;
+L_0x2aa7280/d .functor NOT 1, L_0x2a828d0, C4<0>, C4<0>, C4<0>;
+L_0x2aa7280 .delay (10000,10000,10000) L_0x2aa7280/d;
+L_0x2aa7360/d .functor AND 1, L_0x2aa77c0, L_0x2aa7280, C4<1>, C4<1>;
+L_0x2aa7360 .delay (20000,20000,20000) L_0x2aa7360/d;
+L_0x2aa7470/d .functor AND 1, L_0x2a828d0, L_0x2a828d0, C4<1>, C4<1>;
+L_0x2aa7470 .delay (20000,20000,20000) L_0x2aa7470/d;
+L_0x2aa75e0/d .functor OR 1, L_0x2aa7360, L_0x2aa7470, C4<0>, C4<0>;
+L_0x2aa75e0 .delay (20000,20000,20000) L_0x2aa75e0/d;
+v0x289d500_0 .alias "S", 0 0, v0x29604c0_0;
+v0x289d5c0_0 .net "in0", 0 0, L_0x2aa77c0; 1 drivers
+v0x289d660_0 .alias "in1", 0 0, v0x29604c0_0;
+v0x289d710_0 .net "nS", 0 0, L_0x2aa7280; 1 drivers
+v0x289d7c0_0 .net "out0", 0 0, L_0x2aa7360; 1 drivers
+v0x289d840_0 .net "out1", 0 0, L_0x2aa7470; 1 drivers
+v0x289d8e0_0 .net "outfinal", 0 0, L_0x2aa75e0; 1 drivers
+S_0x289b790 .scope generate, "sltbits[1]" "sltbits[1]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x289b1a8 .param/l "i" 3 332, +C4<01>;
+S_0x289c3f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x289b790;
+ .timescale -9 -12;
+L_0x2a5e410/d .functor NOT 1, L_0x2a5fe70, C4<0>, C4<0>, C4<0>;
+L_0x2a5e410 .delay (10000,10000,10000) L_0x2a5e410/d;
+L_0x2a5ea50/d .functor NOT 1, L_0x2a5eaf0, C4<0>, C4<0>, C4<0>;
+L_0x2a5ea50 .delay (10000,10000,10000) L_0x2a5ea50/d;
+L_0x2a5eb90/d .functor AND 1, L_0x2a5ecd0, L_0x2a5ea50, C4<1>, C4<1>;
+L_0x2a5eb90 .delay (20000,20000,20000) L_0x2a5eb90/d;
+L_0x2a5ed70/d .functor XOR 1, L_0x2a5fdd0, L_0x2a5e820, C4<0>, C4<0>;
+L_0x2a5ed70 .delay (40000,40000,40000) L_0x2a5ed70/d;
+L_0x2a5ee60/d .functor XOR 1, L_0x2a5ed70, L_0x2a5ffa0, C4<0>, C4<0>;
+L_0x2a5ee60 .delay (40000,40000,40000) L_0x2a5ee60/d;
+L_0x2a5ef50/d .functor AND 1, L_0x2a5fdd0, L_0x2a5e820, C4<1>, C4<1>;
+L_0x2a5ef50 .delay (20000,20000,20000) L_0x2a5ef50/d;
+L_0x2a5f8d0/d .functor AND 1, L_0x2a5ed70, L_0x2a5ffa0, C4<1>, C4<1>;
+L_0x2a5f8d0 .delay (20000,20000,20000) L_0x2a5f8d0/d;
+L_0x2a5f9c0/d .functor OR 1, L_0x2a5ef50, L_0x2a5f8d0, C4<0>, C4<0>;
+L_0x2a5f9c0 .delay (20000,20000,20000) L_0x2a5f9c0/d;
+v0x289ca70_0 .net "A", 0 0, L_0x2a5fdd0; 1 drivers
+v0x289cb30_0 .net "AandB", 0 0, L_0x2a5ef50; 1 drivers
+v0x289cbd0_0 .net "AddSubSLTSum", 0 0, L_0x2a5ee60; 1 drivers
+v0x289cc70_0 .net "AxorB", 0 0, L_0x2a5ed70; 1 drivers
+v0x289ccf0_0 .net "B", 0 0, L_0x2a5fe70; 1 drivers
+v0x289cda0_0 .net "BornB", 0 0, L_0x2a5e820; 1 drivers
+v0x289ce60_0 .net "CINandAxorB", 0 0, L_0x2a5f8d0; 1 drivers
+v0x289cee0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x289cf60_0 .net *"_s3", 0 0, L_0x2a5eaf0; 1 drivers
+v0x289cfe0_0 .net *"_s5", 0 0, L_0x2a5ecd0; 1 drivers
+v0x289d080_0 .net "carryin", 0 0, L_0x2a5ffa0; 1 drivers
+v0x289d120_0 .net "carryout", 0 0, L_0x2a5f9c0; 1 drivers
+v0x289d1c0_0 .net "nB", 0 0, L_0x2a5e410; 1 drivers
+v0x289d270_0 .net "nCmd2", 0 0, L_0x2a5ea50; 1 drivers
+v0x289d370_0 .net "subtract", 0 0, L_0x2a5eb90; 1 drivers
+L_0x2a5e9b0 .part v0x2960210_0, 0, 1;
+L_0x2a5eaf0 .part v0x2960210_0, 2, 1;
+L_0x2a5ecd0 .part v0x2960210_0, 0, 1;
+S_0x289c4e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x289c3f0;
+ .timescale -9 -12;
+L_0x2a5e5a0/d .functor NOT 1, L_0x2a5e9b0, C4<0>, C4<0>, C4<0>;
+L_0x2a5e5a0 .delay (10000,10000,10000) L_0x2a5e5a0/d;
+L_0x2a5e640/d .functor AND 1, L_0x2a5fe70, L_0x2a5e5a0, C4<1>, C4<1>;
+L_0x2a5e640 .delay (20000,20000,20000) L_0x2a5e640/d;
+L_0x2a5e730/d .functor AND 1, L_0x2a5e410, L_0x2a5e9b0, C4<1>, C4<1>;
+L_0x2a5e730 .delay (20000,20000,20000) L_0x2a5e730/d;
+L_0x2a5e820/d .functor OR 1, L_0x2a5e640, L_0x2a5e730, C4<0>, C4<0>;
+L_0x2a5e820 .delay (20000,20000,20000) L_0x2a5e820/d;
+v0x289c5d0_0 .net "S", 0 0, L_0x2a5e9b0; 1 drivers
+v0x289c690_0 .alias "in0", 0 0, v0x289ccf0_0;
+v0x289c730_0 .alias "in1", 0 0, v0x289d1c0_0;
+v0x289c7d0_0 .net "nS", 0 0, L_0x2a5e5a0; 1 drivers
+v0x289c850_0 .net "out0", 0 0, L_0x2a5e640; 1 drivers
+v0x289c8f0_0 .net "out1", 0 0, L_0x2a5e730; 1 drivers
+v0x289c9d0_0 .alias "outfinal", 0 0, v0x289cda0_0;
+S_0x289be80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x289b790;
+ .timescale -9 -12;
+L_0x2a60040/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a60040 .delay (10000,10000,10000) L_0x2a60040/d;
+L_0x2a60940/d .functor AND 1, L_0x2881a30, L_0x2a60040, C4<1>, C4<1>;
+L_0x2a60940 .delay (20000,20000,20000) L_0x2a60940/d;
+L_0x2a60a30/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a60a30 .delay (20000,20000,20000) L_0x2a60a30/d;
+L_0x2a60ad0/d .functor OR 1, L_0x2a60940, L_0x2a60a30, C4<0>, C4<0>;
+L_0x2a60ad0 .delay (20000,20000,20000) L_0x2a60ad0/d;
+v0x289bf70_0 .alias "S", 0 0, v0x289f760_0;
+v0x289c010_0 .net "in0", 0 0, L_0x2881a30; 1 drivers
+v0x289c0b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x289c150_0 .net "nS", 0 0, L_0x2a60040; 1 drivers
+v0x289c1d0_0 .net "out0", 0 0, L_0x2a60940; 1 drivers
+v0x289c270_0 .net "out1", 0 0, L_0x2a60a30; 1 drivers
+v0x289c350_0 .net "outfinal", 0 0, L_0x2a60ad0; 1 drivers
+S_0x289b900 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x289b790;
+ .timescale -9 -12;
+L_0x2a60bc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a60bc0 .delay (10000,10000,10000) L_0x2a60bc0/d;
+L_0x2881ca0/d .functor AND 1, L_0x2a63360, L_0x2a60bc0, C4<1>, C4<1>;
+L_0x2881ca0 .delay (20000,20000,20000) L_0x2881ca0/d;
+L_0x2a630e0/d .functor AND 1, L_0x2a63500, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a630e0 .delay (20000,20000,20000) L_0x2a630e0/d;
+L_0x2a63180/d .functor OR 1, L_0x2881ca0, L_0x2a630e0, C4<0>, C4<0>;
+L_0x2a63180 .delay (20000,20000,20000) L_0x2a63180/d;
+v0x289b9f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x289ba70_0 .net "in0", 0 0, L_0x2a63360; 1 drivers
+v0x289bb10_0 .net "in1", 0 0, L_0x2a63500; 1 drivers
+v0x289bbb0_0 .net "nS", 0 0, L_0x2a60bc0; 1 drivers
+v0x289bc60_0 .net "out0", 0 0, L_0x2881ca0; 1 drivers
+v0x289bd00_0 .net "out1", 0 0, L_0x2a630e0; 1 drivers
+v0x289bde0_0 .net "outfinal", 0 0, L_0x2a63180; 1 drivers
+S_0x2899b10 .scope generate, "sltbits[2]" "sltbits[2]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2899528 .param/l "i" 3 332, +C4<010>;
+S_0x289a770 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2899b10;
+ .timescale -9 -12;
+L_0x2a635a0/d .functor NOT 1, L_0x2a648e0, C4<0>, C4<0>, C4<0>;
+L_0x2a635a0 .delay (10000,10000,10000) L_0x2a635a0/d;
+L_0x2a63be0/d .functor NOT 1, L_0x2a63c80, C4<0>, C4<0>, C4<0>;
+L_0x2a63be0 .delay (10000,10000,10000) L_0x2a63be0/d;
+L_0x2a63d20/d .functor AND 1, L_0x2a63e60, L_0x2a63be0, C4<1>, C4<1>;
+L_0x2a63d20 .delay (20000,20000,20000) L_0x2a63d20/d;
+L_0x2a63f00/d .functor XOR 1, L_0x2a64840, L_0x2a639b0, C4<0>, C4<0>;
+L_0x2a63f00 .delay (40000,40000,40000) L_0x2a63f00/d;
+L_0x2a63ff0/d .functor XOR 1, L_0x2a63f00, L_0x2a64aa0, C4<0>, C4<0>;
+L_0x2a63ff0 .delay (40000,40000,40000) L_0x2a63ff0/d;
+L_0x2a640e0/d .functor AND 1, L_0x2a64840, L_0x2a639b0, C4<1>, C4<1>;
+L_0x2a640e0 .delay (20000,20000,20000) L_0x2a640e0/d;
+L_0x2a64250/d .functor AND 1, L_0x2a63f00, L_0x2a64aa0, C4<1>, C4<1>;
+L_0x2a64250 .delay (20000,20000,20000) L_0x2a64250/d;
+L_0x2a64340/d .functor OR 1, L_0x2a640e0, L_0x2a64250, C4<0>, C4<0>;
+L_0x2a64340 .delay (20000,20000,20000) L_0x2a64340/d;
+v0x289adf0_0 .net "A", 0 0, L_0x2a64840; 1 drivers
+v0x289aeb0_0 .net "AandB", 0 0, L_0x2a640e0; 1 drivers
+v0x289af50_0 .net "AddSubSLTSum", 0 0, L_0x2a63ff0; 1 drivers
+v0x289aff0_0 .net "AxorB", 0 0, L_0x2a63f00; 1 drivers
+v0x289b070_0 .net "B", 0 0, L_0x2a648e0; 1 drivers
+v0x289b120_0 .net "BornB", 0 0, L_0x2a639b0; 1 drivers
+v0x289b1e0_0 .net "CINandAxorB", 0 0, L_0x2a64250; 1 drivers
+v0x289b260_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x289b2e0_0 .net *"_s3", 0 0, L_0x2a63c80; 1 drivers
+v0x289b360_0 .net *"_s5", 0 0, L_0x2a63e60; 1 drivers
+v0x289b400_0 .net "carryin", 0 0, L_0x2a64aa0; 1 drivers
+v0x289b4a0_0 .net "carryout", 0 0, L_0x2a64340; 1 drivers
+v0x289b540_0 .net "nB", 0 0, L_0x2a635a0; 1 drivers
+v0x289b5f0_0 .net "nCmd2", 0 0, L_0x2a63be0; 1 drivers
+v0x289b6f0_0 .net "subtract", 0 0, L_0x2a63d20; 1 drivers
+L_0x2a63b40 .part v0x2960210_0, 0, 1;
+L_0x2a63c80 .part v0x2960210_0, 2, 1;
+L_0x2a63e60 .part v0x2960210_0, 0, 1;
+S_0x289a860 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x289a770;
+ .timescale -9 -12;
+L_0x2a63730/d .functor NOT 1, L_0x2a63b40, C4<0>, C4<0>, C4<0>;
+L_0x2a63730 .delay (10000,10000,10000) L_0x2a63730/d;
+L_0x2a637d0/d .functor AND 1, L_0x2a648e0, L_0x2a63730, C4<1>, C4<1>;
+L_0x2a637d0 .delay (20000,20000,20000) L_0x2a637d0/d;
+L_0x2a638c0/d .functor AND 1, L_0x2a635a0, L_0x2a63b40, C4<1>, C4<1>;
+L_0x2a638c0 .delay (20000,20000,20000) L_0x2a638c0/d;
+L_0x2a639b0/d .functor OR 1, L_0x2a637d0, L_0x2a638c0, C4<0>, C4<0>;
+L_0x2a639b0 .delay (20000,20000,20000) L_0x2a639b0/d;
+v0x289a950_0 .net "S", 0 0, L_0x2a63b40; 1 drivers
+v0x289aa10_0 .alias "in0", 0 0, v0x289b070_0;
+v0x289aab0_0 .alias "in1", 0 0, v0x289b540_0;
+v0x289ab50_0 .net "nS", 0 0, L_0x2a63730; 1 drivers
+v0x289abd0_0 .net "out0", 0 0, L_0x2a637d0; 1 drivers
+v0x289ac70_0 .net "out1", 0 0, L_0x2a638c0; 1 drivers
+v0x289ad50_0 .alias "outfinal", 0 0, v0x289b120_0;
+S_0x289a200 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2899b10;
+ .timescale -9 -12;
+L_0x2a634a0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a634a0 .delay (10000,10000,10000) L_0x2a634a0/d;
+L_0x2a64bd0/d .functor AND 1, L_0x2a65020, L_0x2a634a0, C4<1>, C4<1>;
+L_0x2a64bd0 .delay (20000,20000,20000) L_0x2a64bd0/d;
+L_0x2a64c70/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a64c70 .delay (20000,20000,20000) L_0x2a64c70/d;
+L_0x2a64d10/d .functor OR 1, L_0x2a64bd0, L_0x2a64c70, C4<0>, C4<0>;
+L_0x2a64d10 .delay (20000,20000,20000) L_0x2a64d10/d;
+v0x289a2f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x289a390_0 .net "in0", 0 0, L_0x2a65020; 1 drivers
+v0x289a430_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x289a4d0_0 .net "nS", 0 0, L_0x2a634a0; 1 drivers
+v0x289a550_0 .net "out0", 0 0, L_0x2a64bd0; 1 drivers
+v0x289a5f0_0 .net "out1", 0 0, L_0x2a64c70; 1 drivers
+v0x289a6d0_0 .net "outfinal", 0 0, L_0x2a64d10; 1 drivers
+S_0x2899c80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2899b10;
+ .timescale -9 -12;
+L_0x29d4300/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x29d4300 .delay (10000,10000,10000) L_0x29d4300/d;
+L_0x2a65230/d .functor AND 1, L_0x2a64f80, L_0x29d4300, C4<1>, C4<1>;
+L_0x2a65230 .delay (20000,20000,20000) L_0x2a65230/d;
+L_0x2a65320/d .functor AND 1, L_0x2a656a0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a65320 .delay (20000,20000,20000) L_0x2a65320/d;
+L_0x2a653c0/d .functor OR 1, L_0x2a65230, L_0x2a65320, C4<0>, C4<0>;
+L_0x2a653c0 .delay (20000,20000,20000) L_0x2a653c0/d;
+v0x2899d70_0 .alias "S", 0 0, v0x289f760_0;
+v0x2899df0_0 .net "in0", 0 0, L_0x2a64f80; 1 drivers
+v0x2899e90_0 .net "in1", 0 0, L_0x2a656a0; 1 drivers
+v0x2899f30_0 .net "nS", 0 0, L_0x29d4300; 1 drivers
+v0x2899fe0_0 .net "out0", 0 0, L_0x2a65230; 1 drivers
+v0x289a080_0 .net "out1", 0 0, L_0x2a65320; 1 drivers
+v0x289a160_0 .net "outfinal", 0 0, L_0x2a653c0; 1 drivers
+S_0x2897e90 .scope generate, "sltbits[3]" "sltbits[3]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x28978a8 .param/l "i" 3 332, +C4<011>;
+S_0x2898af0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2897e90;
+ .timescale -9 -12;
+L_0x2a655a0/d .functor NOT 1, L_0x2a66860, C4<0>, C4<0>, C4<0>;
+L_0x2a655a0 .delay (10000,10000,10000) L_0x2a655a0/d;
+L_0x2a65de0/d .functor NOT 1, L_0x2a65e80, C4<0>, C4<0>, C4<0>;
+L_0x2a65de0 .delay (10000,10000,10000) L_0x2a65de0/d;
+L_0x2a65f20/d .functor AND 1, L_0x2a66060, L_0x2a65de0, C4<1>, C4<1>;
+L_0x2a65f20 .delay (20000,20000,20000) L_0x2a65f20/d;
+L_0x2a66100/d .functor XOR 1, L_0x2a66980, L_0x2a65bb0, C4<0>, C4<0>;
+L_0x2a66100 .delay (40000,40000,40000) L_0x2a66100/d;
+L_0x2a661f0/d .functor XOR 1, L_0x2a66100, L_0x2a66b90, C4<0>, C4<0>;
+L_0x2a661f0 .delay (40000,40000,40000) L_0x2a661f0/d;
+L_0x2a662e0/d .functor AND 1, L_0x2a66980, L_0x2a65bb0, C4<1>, C4<1>;
+L_0x2a662e0 .delay (20000,20000,20000) L_0x2a662e0/d;
+L_0x2a66450/d .functor AND 1, L_0x2a66100, L_0x2a66b90, C4<1>, C4<1>;
+L_0x2a66450 .delay (20000,20000,20000) L_0x2a66450/d;
+L_0x2a66540/d .functor OR 1, L_0x2a662e0, L_0x2a66450, C4<0>, C4<0>;
+L_0x2a66540 .delay (20000,20000,20000) L_0x2a66540/d;
+v0x2899170_0 .net "A", 0 0, L_0x2a66980; 1 drivers
+v0x2899230_0 .net "AandB", 0 0, L_0x2a662e0; 1 drivers
+v0x28992d0_0 .net "AddSubSLTSum", 0 0, L_0x2a661f0; 1 drivers
+v0x2899370_0 .net "AxorB", 0 0, L_0x2a66100; 1 drivers
+v0x28993f0_0 .net "B", 0 0, L_0x2a66860; 1 drivers
+v0x28994a0_0 .net "BornB", 0 0, L_0x2a65bb0; 1 drivers
+v0x2899560_0 .net "CINandAxorB", 0 0, L_0x2a66450; 1 drivers
+v0x28995e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2899660_0 .net *"_s3", 0 0, L_0x2a65e80; 1 drivers
+v0x28996e0_0 .net *"_s5", 0 0, L_0x2a66060; 1 drivers
+v0x2899780_0 .net "carryin", 0 0, L_0x2a66b90; 1 drivers
+v0x2899820_0 .net "carryout", 0 0, L_0x2a66540; 1 drivers
+v0x28998c0_0 .net "nB", 0 0, L_0x2a655a0; 1 drivers
+v0x2899970_0 .net "nCmd2", 0 0, L_0x2a65de0; 1 drivers
+v0x2899a70_0 .net "subtract", 0 0, L_0x2a65f20; 1 drivers
+L_0x2a65d40 .part v0x2960210_0, 0, 1;
+L_0x2a65e80 .part v0x2960210_0, 2, 1;
+L_0x2a66060 .part v0x2960210_0, 0, 1;
+S_0x2898be0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2898af0;
+ .timescale -9 -12;
+L_0x2a65930/d .functor NOT 1, L_0x2a65d40, C4<0>, C4<0>, C4<0>;
+L_0x2a65930 .delay (10000,10000,10000) L_0x2a65930/d;
+L_0x2a659d0/d .functor AND 1, L_0x2a66860, L_0x2a65930, C4<1>, C4<1>;
+L_0x2a659d0 .delay (20000,20000,20000) L_0x2a659d0/d;
+L_0x2a65ac0/d .functor AND 1, L_0x2a655a0, L_0x2a65d40, C4<1>, C4<1>;
+L_0x2a65ac0 .delay (20000,20000,20000) L_0x2a65ac0/d;
+L_0x2a65bb0/d .functor OR 1, L_0x2a659d0, L_0x2a65ac0, C4<0>, C4<0>;
+L_0x2a65bb0 .delay (20000,20000,20000) L_0x2a65bb0/d;
+v0x2898cd0_0 .net "S", 0 0, L_0x2a65d40; 1 drivers
+v0x2898d90_0 .alias "in0", 0 0, v0x28993f0_0;
+v0x2898e30_0 .alias "in1", 0 0, v0x28998c0_0;
+v0x2898ed0_0 .net "nS", 0 0, L_0x2a65930; 1 drivers
+v0x2898f50_0 .net "out0", 0 0, L_0x2a659d0; 1 drivers
+v0x2898ff0_0 .net "out1", 0 0, L_0x2a65ac0; 1 drivers
+v0x28990d0_0 .alias "outfinal", 0 0, v0x28994a0_0;
+S_0x2898580 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2897e90;
+ .timescale -9 -12;
+L_0x2a66a20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a66a20 .delay (10000,10000,10000) L_0x2a66a20/d;
+L_0x2a66aa0/d .functor AND 1, L_0x2a67030, L_0x2a66a20, C4<1>, C4<1>;
+L_0x2a66aa0 .delay (20000,20000,20000) L_0x2a66aa0/d;
+L_0x2a66db0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a66db0 .delay (20000,20000,20000) L_0x2a66db0/d;
+L_0x2a66e50/d .functor OR 1, L_0x2a66aa0, L_0x2a66db0, C4<0>, C4<0>;
+L_0x2a66e50 .delay (20000,20000,20000) L_0x2a66e50/d;
+v0x2898670_0 .alias "S", 0 0, v0x289f760_0;
+v0x2898710_0 .net "in0", 0 0, L_0x2a67030; 1 drivers
+v0x28987b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2898850_0 .net "nS", 0 0, L_0x2a66a20; 1 drivers
+v0x28988d0_0 .net "out0", 0 0, L_0x2a66aa0; 1 drivers
+v0x2898970_0 .net "out1", 0 0, L_0x2a66db0; 1 drivers
+v0x2898a50_0 .net "outfinal", 0 0, L_0x2a66e50; 1 drivers
+S_0x2898000 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2897e90;
+ .timescale -9 -12;
+L_0x2a66cc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a66cc0 .delay (10000,10000,10000) L_0x2a66cc0/d;
+L_0x2a672b0/d .functor AND 1, L_0x2a67620, L_0x2a66cc0, C4<1>, C4<1>;
+L_0x2a672b0 .delay (20000,20000,20000) L_0x2a672b0/d;
+L_0x2a673a0/d .functor AND 1, L_0x2a67120, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a673a0 .delay (20000,20000,20000) L_0x2a673a0/d;
+L_0x2a67440/d .functor OR 1, L_0x2a672b0, L_0x2a673a0, C4<0>, C4<0>;
+L_0x2a67440 .delay (20000,20000,20000) L_0x2a67440/d;
+v0x28980f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2898170_0 .net "in0", 0 0, L_0x2a67620; 1 drivers
+v0x2898210_0 .net "in1", 0 0, L_0x2a67120; 1 drivers
+v0x28982b0_0 .net "nS", 0 0, L_0x2a66cc0; 1 drivers
+v0x2898360_0 .net "out0", 0 0, L_0x2a672b0; 1 drivers
+v0x2898400_0 .net "out1", 0 0, L_0x2a673a0; 1 drivers
+v0x28984e0_0 .net "outfinal", 0 0, L_0x2a67440; 1 drivers
+S_0x2896210 .scope generate, "sltbits[4]" "sltbits[4]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2895c28 .param/l "i" 3 332, +C4<0100>;
+S_0x2896e70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2896210;
+ .timescale -9 -12;
+L_0x2a64ef0/d .functor NOT 1, L_0x2a68be0, C4<0>, C4<0>, C4<0>;
+L_0x2a64ef0 .delay (10000,10000,10000) L_0x2a64ef0/d;
+L_0x2a67f10/d .functor NOT 1, L_0x2a67fb0, C4<0>, C4<0>, C4<0>;
+L_0x2a67f10 .delay (10000,10000,10000) L_0x2a67f10/d;
+L_0x2a68050/d .functor AND 1, L_0x2a68190, L_0x2a67f10, C4<1>, C4<1>;
+L_0x2a68050 .delay (20000,20000,20000) L_0x2a68050/d;
+L_0x2a68230/d .functor XOR 1, L_0x2a688a0, L_0x2a67ce0, C4<0>, C4<0>;
+L_0x2a68230 .delay (40000,40000,40000) L_0x2a68230/d;
+L_0x2a68320/d .functor XOR 1, L_0x2a68230, L_0x2a68ab0, C4<0>, C4<0>;
+L_0x2a68320 .delay (40000,40000,40000) L_0x2a68320/d;
+L_0x2a68410/d .functor AND 1, L_0x2a688a0, L_0x2a67ce0, C4<1>, C4<1>;
+L_0x2a68410 .delay (20000,20000,20000) L_0x2a68410/d;
+L_0x2a68580/d .functor AND 1, L_0x2a68230, L_0x2a68ab0, C4<1>, C4<1>;
+L_0x2a68580 .delay (20000,20000,20000) L_0x2a68580/d;
+L_0x2a68670/d .functor OR 1, L_0x2a68410, L_0x2a68580, C4<0>, C4<0>;
+L_0x2a68670 .delay (20000,20000,20000) L_0x2a68670/d;
+v0x28974f0_0 .net "A", 0 0, L_0x2a688a0; 1 drivers
+v0x28975b0_0 .net "AandB", 0 0, L_0x2a68410; 1 drivers
+v0x2897650_0 .net "AddSubSLTSum", 0 0, L_0x2a68320; 1 drivers
+v0x28976f0_0 .net "AxorB", 0 0, L_0x2a68230; 1 drivers
+v0x2897770_0 .net "B", 0 0, L_0x2a68be0; 1 drivers
+v0x2897820_0 .net "BornB", 0 0, L_0x2a67ce0; 1 drivers
+v0x28978e0_0 .net "CINandAxorB", 0 0, L_0x2a68580; 1 drivers
+v0x2897960_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28979e0_0 .net *"_s3", 0 0, L_0x2a67fb0; 1 drivers
+v0x2897a60_0 .net *"_s5", 0 0, L_0x2a68190; 1 drivers
+v0x2897b00_0 .net "carryin", 0 0, L_0x2a68ab0; 1 drivers
+v0x2897ba0_0 .net "carryout", 0 0, L_0x2a68670; 1 drivers
+v0x2897c40_0 .net "nB", 0 0, L_0x2a64ef0; 1 drivers
+v0x2897cf0_0 .net "nCmd2", 0 0, L_0x2a67f10; 1 drivers
+v0x2897df0_0 .net "subtract", 0 0, L_0x2a68050; 1 drivers
+L_0x2a67e70 .part v0x2960210_0, 0, 1;
+L_0x2a67fb0 .part v0x2960210_0, 2, 1;
+L_0x2a68190 .part v0x2960210_0, 0, 1;
+S_0x2896f60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2896e70;
+ .timescale -9 -12;
+L_0x2a67a60/d .functor NOT 1, L_0x2a67e70, C4<0>, C4<0>, C4<0>;
+L_0x2a67a60 .delay (10000,10000,10000) L_0x2a67a60/d;
+L_0x2a67b00/d .functor AND 1, L_0x2a68be0, L_0x2a67a60, C4<1>, C4<1>;
+L_0x2a67b00 .delay (20000,20000,20000) L_0x2a67b00/d;
+L_0x2a67bf0/d .functor AND 1, L_0x2a64ef0, L_0x2a67e70, C4<1>, C4<1>;
+L_0x2a67bf0 .delay (20000,20000,20000) L_0x2a67bf0/d;
+L_0x2a67ce0/d .functor OR 1, L_0x2a67b00, L_0x2a67bf0, C4<0>, C4<0>;
+L_0x2a67ce0 .delay (20000,20000,20000) L_0x2a67ce0/d;
+v0x2897050_0 .net "S", 0 0, L_0x2a67e70; 1 drivers
+v0x2897110_0 .alias "in0", 0 0, v0x2897770_0;
+v0x28971b0_0 .alias "in1", 0 0, v0x2897c40_0;
+v0x2897250_0 .net "nS", 0 0, L_0x2a67a60; 1 drivers
+v0x28972d0_0 .net "out0", 0 0, L_0x2a67b00; 1 drivers
+v0x2897370_0 .net "out1", 0 0, L_0x2a67bf0; 1 drivers
+v0x2897450_0 .alias "outfinal", 0 0, v0x2897820_0;
+S_0x2896900 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2896210;
+ .timescale -9 -12;
+L_0x2a68940/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a68940 .delay (10000,10000,10000) L_0x2a68940/d;
+L_0x2a68b50/d .functor AND 1, L_0x2a68d10, L_0x2a68940, C4<1>, C4<1>;
+L_0x2a68b50 .delay (20000,20000,20000) L_0x2a68b50/d;
+L_0x2a68f60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a68f60 .delay (20000,20000,20000) L_0x2a68f60/d;
+L_0x2a69000/d .functor OR 1, L_0x2a68b50, L_0x2a68f60, C4<0>, C4<0>;
+L_0x2a69000 .delay (20000,20000,20000) L_0x2a69000/d;
+v0x28969f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2896a90_0 .net "in0", 0 0, L_0x2a68d10; 1 drivers
+v0x2896b30_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2896bd0_0 .net "nS", 0 0, L_0x2a68940; 1 drivers
+v0x2896c50_0 .net "out0", 0 0, L_0x2a68b50; 1 drivers
+v0x2896cf0_0 .net "out1", 0 0, L_0x2a68f60; 1 drivers
+v0x2896dd0_0 .net "outfinal", 0 0, L_0x2a69000; 1 drivers
+S_0x2896380 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2896210;
+ .timescale -9 -12;
+L_0x2a65100/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a65100 .delay (10000,10000,10000) L_0x2a65100/d;
+L_0x2a651d0/d .functor AND 1, L_0x2a691e0, L_0x2a65100, C4<1>, C4<1>;
+L_0x2a651d0 .delay (20000,20000,20000) L_0x2a651d0/d;
+L_0x2a69610/d .functor AND 1, L_0x2a699f0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a69610 .delay (20000,20000,20000) L_0x2a69610/d;
+L_0x2a696b0/d .functor OR 1, L_0x2a651d0, L_0x2a69610, C4<0>, C4<0>;
+L_0x2a696b0 .delay (20000,20000,20000) L_0x2a696b0/d;
+v0x2896470_0 .alias "S", 0 0, v0x289f760_0;
+v0x28964f0_0 .net "in0", 0 0, L_0x2a691e0; 1 drivers
+v0x2896590_0 .net "in1", 0 0, L_0x2a699f0; 1 drivers
+v0x2896630_0 .net "nS", 0 0, L_0x2a65100; 1 drivers
+v0x28966e0_0 .net "out0", 0 0, L_0x2a651d0; 1 drivers
+v0x2896780_0 .net "out1", 0 0, L_0x2a69610; 1 drivers
+v0x2896860_0 .net "outfinal", 0 0, L_0x2a696b0; 1 drivers
+S_0x2894590 .scope generate, "sltbits[5]" "sltbits[5]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2893fa8 .param/l "i" 3 332, +C4<0101>;
+S_0x28951f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2894590;
+ .timescale -9 -12;
+L_0x2a69890/d .functor NOT 1, L_0x2a6ab80, C4<0>, C4<0>, C4<0>;
+L_0x2a69890 .delay (10000,10000,10000) L_0x2a69890/d;
+L_0x2a6a100/d .functor NOT 1, L_0x2a6a1a0, C4<0>, C4<0>, C4<0>;
+L_0x2a6a100 .delay (10000,10000,10000) L_0x2a6a100/d;
+L_0x2a6a240/d .functor AND 1, L_0x2a6a380, L_0x2a6a100, C4<1>, C4<1>;
+L_0x2a6a240 .delay (20000,20000,20000) L_0x2a6a240/d;
+L_0x2a6a420/d .functor XOR 1, L_0x2a6ad00, L_0x2a69ed0, C4<0>, C4<0>;
+L_0x2a6a420 .delay (40000,40000,40000) L_0x2a6a420/d;
+L_0x2a6a510/d .functor XOR 1, L_0x2a6a420, L_0x2a6af30, C4<0>, C4<0>;
+L_0x2a6a510 .delay (40000,40000,40000) L_0x2a6a510/d;
+L_0x2a6a600/d .functor AND 1, L_0x2a6ad00, L_0x2a69ed0, C4<1>, C4<1>;
+L_0x2a6a600 .delay (20000,20000,20000) L_0x2a6a600/d;
+L_0x2a6a770/d .functor AND 1, L_0x2a6a420, L_0x2a6af30, C4<1>, C4<1>;
+L_0x2a6a770 .delay (20000,20000,20000) L_0x2a6a770/d;
+L_0x2a6a860/d .functor OR 1, L_0x2a6a600, L_0x2a6a770, C4<0>, C4<0>;
+L_0x2a6a860 .delay (20000,20000,20000) L_0x2a6a860/d;
+v0x2895870_0 .net "A", 0 0, L_0x2a6ad00; 1 drivers
+v0x2895930_0 .net "AandB", 0 0, L_0x2a6a600; 1 drivers
+v0x28959d0_0 .net "AddSubSLTSum", 0 0, L_0x2a6a510; 1 drivers
+v0x2895a70_0 .net "AxorB", 0 0, L_0x2a6a420; 1 drivers
+v0x2895af0_0 .net "B", 0 0, L_0x2a6ab80; 1 drivers
+v0x2895ba0_0 .net "BornB", 0 0, L_0x2a69ed0; 1 drivers
+v0x2895c60_0 .net "CINandAxorB", 0 0, L_0x2a6a770; 1 drivers
+v0x2895ce0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2895d60_0 .net *"_s3", 0 0, L_0x2a6a1a0; 1 drivers
+v0x2895de0_0 .net *"_s5", 0 0, L_0x2a6a380; 1 drivers
+v0x2895e80_0 .net "carryin", 0 0, L_0x2a6af30; 1 drivers
+v0x2895f20_0 .net "carryout", 0 0, L_0x2a6a860; 1 drivers
+v0x2895fc0_0 .net "nB", 0 0, L_0x2a69890; 1 drivers
+v0x2896070_0 .net "nCmd2", 0 0, L_0x2a6a100; 1 drivers
+v0x2896170_0 .net "subtract", 0 0, L_0x2a6a240; 1 drivers
+L_0x2a6a060 .part v0x2960210_0, 0, 1;
+L_0x2a6a1a0 .part v0x2960210_0, 2, 1;
+L_0x2a6a380 .part v0x2960210_0, 0, 1;
+S_0x28952e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28951f0;
+ .timescale -9 -12;
+L_0x2a69c50/d .functor NOT 1, L_0x2a6a060, C4<0>, C4<0>, C4<0>;
+L_0x2a69c50 .delay (10000,10000,10000) L_0x2a69c50/d;
+L_0x2a69cf0/d .functor AND 1, L_0x2a6ab80, L_0x2a69c50, C4<1>, C4<1>;
+L_0x2a69cf0 .delay (20000,20000,20000) L_0x2a69cf0/d;
+L_0x2a69de0/d .functor AND 1, L_0x2a69890, L_0x2a6a060, C4<1>, C4<1>;
+L_0x2a69de0 .delay (20000,20000,20000) L_0x2a69de0/d;
+L_0x2a69ed0/d .functor OR 1, L_0x2a69cf0, L_0x2a69de0, C4<0>, C4<0>;
+L_0x2a69ed0 .delay (20000,20000,20000) L_0x2a69ed0/d;
+v0x28953d0_0 .net "S", 0 0, L_0x2a6a060; 1 drivers
+v0x2895490_0 .alias "in0", 0 0, v0x2895af0_0;
+v0x2895530_0 .alias "in1", 0 0, v0x2895fc0_0;
+v0x28955d0_0 .net "nS", 0 0, L_0x2a69c50; 1 drivers
+v0x2895650_0 .net "out0", 0 0, L_0x2a69cf0; 1 drivers
+v0x28956f0_0 .net "out1", 0 0, L_0x2a69de0; 1 drivers
+v0x28957d0_0 .alias "outfinal", 0 0, v0x2895ba0_0;
+S_0x2894c80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2894590;
+ .timescale -9 -12;
+L_0x2a69b80/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a69b80 .delay (10000,10000,10000) L_0x2a69b80/d;
+L_0x2a6ada0/d .functor AND 1, L_0x2a6b350, L_0x2a69b80, C4<1>, C4<1>;
+L_0x2a6ada0 .delay (20000,20000,20000) L_0x2a6ada0/d;
+L_0x2a6ae60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a6ae60 .delay (20000,20000,20000) L_0x2a6ae60/d;
+L_0x2a6b170/d .functor OR 1, L_0x2a6ada0, L_0x2a6ae60, C4<0>, C4<0>;
+L_0x2a6b170 .delay (20000,20000,20000) L_0x2a6b170/d;
+v0x2894d70_0 .alias "S", 0 0, v0x289f760_0;
+v0x2894e10_0 .net "in0", 0 0, L_0x2a6b350; 1 drivers
+v0x2894eb0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2894f50_0 .net "nS", 0 0, L_0x2a69b80; 1 drivers
+v0x2894fd0_0 .net "out0", 0 0, L_0x2a6ada0; 1 drivers
+v0x2895070_0 .net "out1", 0 0, L_0x2a6ae60; 1 drivers
+v0x2895150_0 .net "outfinal", 0 0, L_0x2a6b170; 1 drivers
+S_0x2894700 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2894590;
+ .timescale -9 -12;
+L_0x2a6b060/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a6b060 .delay (10000,10000,10000) L_0x2a6b060/d;
+L_0x2a6b5f0/d .functor AND 1, L_0x2a6b960, L_0x2a6b060, C4<1>, C4<1>;
+L_0x2a6b5f0 .delay (20000,20000,20000) L_0x2a6b5f0/d;
+L_0x2a6b6e0/d .functor AND 1, L_0x2a6b440, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a6b6e0 .delay (20000,20000,20000) L_0x2a6b6e0/d;
+L_0x2a6b780/d .functor OR 1, L_0x2a6b5f0, L_0x2a6b6e0, C4<0>, C4<0>;
+L_0x2a6b780 .delay (20000,20000,20000) L_0x2a6b780/d;
+v0x28947f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2894870_0 .net "in0", 0 0, L_0x2a6b960; 1 drivers
+v0x2894910_0 .net "in1", 0 0, L_0x2a6b440; 1 drivers
+v0x28949b0_0 .net "nS", 0 0, L_0x2a6b060; 1 drivers
+v0x2894a60_0 .net "out0", 0 0, L_0x2a6b5f0; 1 drivers
+v0x2894b00_0 .net "out1", 0 0, L_0x2a6b6e0; 1 drivers
+v0x2894be0_0 .net "outfinal", 0 0, L_0x2a6b780; 1 drivers
+S_0x27f2140 .scope generate, "sltbits[6]" "sltbits[6]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2891328 .param/l "i" 3 332, +C4<0110>;
+S_0x2893570 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x27f2140;
+ .timescale -9 -12;
+L_0x2a6b530/d .functor NOT 1, L_0x2a6cbe0, C4<0>, C4<0>, C4<0>;
+L_0x2a6b530 .delay (10000,10000,10000) L_0x2a6b530/d;
+L_0x2a6c1b0/d .functor NOT 1, L_0x2a6c250, C4<0>, C4<0>, C4<0>;
+L_0x2a6c1b0 .delay (10000,10000,10000) L_0x2a6c1b0/d;
+L_0x2a6c2f0/d .functor AND 1, L_0x2a6c430, L_0x2a6c1b0, C4<1>, C4<1>;
+L_0x2a6c2f0 .delay (20000,20000,20000) L_0x2a6c2f0/d;
+L_0x2a6c4d0/d .functor XOR 1, L_0x2a6cb40, L_0x2a6bf80, C4<0>, C4<0>;
+L_0x2a6c4d0 .delay (40000,40000,40000) L_0x2a6c4d0/d;
+L_0x2a6c5c0/d .functor XOR 1, L_0x2a6c4d0, L_0x2a6cf50, C4<0>, C4<0>;
+L_0x2a6c5c0 .delay (40000,40000,40000) L_0x2a6c5c0/d;
+L_0x2a6c6b0/d .functor AND 1, L_0x2a6cb40, L_0x2a6bf80, C4<1>, C4<1>;
+L_0x2a6c6b0 .delay (20000,20000,20000) L_0x2a6c6b0/d;
+L_0x2a6c820/d .functor AND 1, L_0x2a6c4d0, L_0x2a6cf50, C4<1>, C4<1>;
+L_0x2a6c820 .delay (20000,20000,20000) L_0x2a6c820/d;
+L_0x2a6c910/d .functor OR 1, L_0x2a6c6b0, L_0x2a6c820, C4<0>, C4<0>;
+L_0x2a6c910 .delay (20000,20000,20000) L_0x2a6c910/d;
+v0x2893bf0_0 .net "A", 0 0, L_0x2a6cb40; 1 drivers
+v0x2893cb0_0 .net "AandB", 0 0, L_0x2a6c6b0; 1 drivers
+v0x2893d50_0 .net "AddSubSLTSum", 0 0, L_0x2a6c5c0; 1 drivers
+v0x2893df0_0 .net "AxorB", 0 0, L_0x2a6c4d0; 1 drivers
+v0x2893e70_0 .net "B", 0 0, L_0x2a6cbe0; 1 drivers
+v0x2893f20_0 .net "BornB", 0 0, L_0x2a6bf80; 1 drivers
+v0x2893fe0_0 .net "CINandAxorB", 0 0, L_0x2a6c820; 1 drivers
+v0x2894060_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28940e0_0 .net *"_s3", 0 0, L_0x2a6c250; 1 drivers
+v0x2894160_0 .net *"_s5", 0 0, L_0x2a6c430; 1 drivers
+v0x2894200_0 .net "carryin", 0 0, L_0x2a6cf50; 1 drivers
+v0x28942a0_0 .net "carryout", 0 0, L_0x2a6c910; 1 drivers
+v0x2894340_0 .net "nB", 0 0, L_0x2a6b530; 1 drivers
+v0x28943f0_0 .net "nCmd2", 0 0, L_0x2a6c1b0; 1 drivers
+v0x28944f0_0 .net "subtract", 0 0, L_0x2a6c2f0; 1 drivers
+L_0x2a6c110 .part v0x2960210_0, 0, 1;
+L_0x2a6c250 .part v0x2960210_0, 2, 1;
+L_0x2a6c430 .part v0x2960210_0, 0, 1;
+S_0x2893660 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2893570;
+ .timescale -9 -12;
+L_0x2a6bd00/d .functor NOT 1, L_0x2a6c110, C4<0>, C4<0>, C4<0>;
+L_0x2a6bd00 .delay (10000,10000,10000) L_0x2a6bd00/d;
+L_0x2a6bda0/d .functor AND 1, L_0x2a6cbe0, L_0x2a6bd00, C4<1>, C4<1>;
+L_0x2a6bda0 .delay (20000,20000,20000) L_0x2a6bda0/d;
+L_0x2a6be90/d .functor AND 1, L_0x2a6b530, L_0x2a6c110, C4<1>, C4<1>;
+L_0x2a6be90 .delay (20000,20000,20000) L_0x2a6be90/d;
+L_0x2a6bf80/d .functor OR 1, L_0x2a6bda0, L_0x2a6be90, C4<0>, C4<0>;
+L_0x2a6bf80 .delay (20000,20000,20000) L_0x2a6bf80/d;
+v0x2893750_0 .net "S", 0 0, L_0x2a6c110; 1 drivers
+v0x2893810_0 .alias "in0", 0 0, v0x2893e70_0;
+v0x28938b0_0 .alias "in1", 0 0, v0x2894340_0;
+v0x2893950_0 .net "nS", 0 0, L_0x2a6bd00; 1 drivers
+v0x28939d0_0 .net "out0", 0 0, L_0x2a6bda0; 1 drivers
+v0x2893a70_0 .net "out1", 0 0, L_0x2a6be90; 1 drivers
+v0x2893b50_0 .alias "outfinal", 0 0, v0x2893f20_0;
+S_0x27f2830 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x27f2140;
+ .timescale -9 -12;
+L_0x2a6cff0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a6cff0 .delay (10000,10000,10000) L_0x2a6cff0/d;
+L_0x2a6d050/d .functor AND 1, L_0x2a67710, L_0x2a6cff0, C4<1>, C4<1>;
+L_0x2a6d050 .delay (20000,20000,20000) L_0x2a6d050/d;
+L_0x2a6d140/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a6d140 .delay (20000,20000,20000) L_0x2a6d140/d;
+L_0x2a6d1e0/d .functor OR 1, L_0x2a6d050, L_0x2a6d140, C4<0>, C4<0>;
+L_0x2a6d1e0 .delay (20000,20000,20000) L_0x2a6d1e0/d;
+v0x27f2920_0 .alias "S", 0 0, v0x289f760_0;
+v0x27f29c0_0 .net "in0", 0 0, L_0x2a67710; 1 drivers
+v0x27f2a60_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x27f2b00_0 .net "nS", 0 0, L_0x2a6cff0; 1 drivers
+v0x27f2b80_0 .net "out0", 0 0, L_0x2a6d050; 1 drivers
+v0x27f2c20_0 .net "out1", 0 0, L_0x2a6d140; 1 drivers
+v0x28934d0_0 .net "outfinal", 0 0, L_0x2a6d1e0; 1 drivers
+S_0x27f22b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x27f2140;
+ .timescale -9 -12;
+L_0x2a69440/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a69440 .delay (10000,10000,10000) L_0x2a69440/d;
+L_0x2a6d7d0/d .functor AND 1, L_0x2a6d5d0, L_0x2a69440, C4<1>, C4<1>;
+L_0x2a6d7d0 .delay (20000,20000,20000) L_0x2a6d7d0/d;
+L_0x2a6d8c0/d .functor AND 1, L_0x2a6d6c0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a6d8c0 .delay (20000,20000,20000) L_0x2a6d8c0/d;
+L_0x2a6d960/d .functor OR 1, L_0x2a6d7d0, L_0x2a6d8c0, C4<0>, C4<0>;
+L_0x2a6d960 .delay (20000,20000,20000) L_0x2a6d960/d;
+v0x27f23a0_0 .alias "S", 0 0, v0x289f760_0;
+v0x27f2420_0 .net "in0", 0 0, L_0x2a6d5d0; 1 drivers
+v0x27f24c0_0 .net "in1", 0 0, L_0x2a6d6c0; 1 drivers
+v0x27f2560_0 .net "nS", 0 0, L_0x2a69440; 1 drivers
+v0x27f2610_0 .net "out0", 0 0, L_0x2a6d7d0; 1 drivers
+v0x27f26b0_0 .net "out1", 0 0, L_0x2a6d8c0; 1 drivers
+v0x27f2790_0 .net "outfinal", 0 0, L_0x2a6d960; 1 drivers
+S_0x288fc90 .scope generate, "sltbits[7]" "sltbits[7]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x288f6a8 .param/l "i" 3 332, +C4<0111>;
+S_0x28908f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288fc90;
+ .timescale -9 -12;
+L_0x2a6dd60/d .functor NOT 1, L_0x2a6f060, C4<0>, C4<0>, C4<0>;
+L_0x2a6dd60 .delay (10000,10000,10000) L_0x2a6dd60/d;
+L_0x2a6e3a0/d .functor NOT 1, L_0x2a6e440, C4<0>, C4<0>, C4<0>;
+L_0x2a6e3a0 .delay (10000,10000,10000) L_0x2a6e3a0/d;
+L_0x2a6e4e0/d .functor AND 1, L_0x2a6e620, L_0x2a6e3a0, C4<1>, C4<1>;
+L_0x2a6e4e0 .delay (20000,20000,20000) L_0x2a6e4e0/d;
+L_0x2a6e6c0/d .functor XOR 1, L_0x2a6dc30, L_0x2a6e170, C4<0>, C4<0>;
+L_0x2a6e6c0 .delay (40000,40000,40000) L_0x2a6e6c0/d;
+L_0x2a6e7b0/d .functor XOR 1, L_0x2a6e6c0, L_0x2a6f100, C4<0>, C4<0>;
+L_0x2a6e7b0 .delay (40000,40000,40000) L_0x2a6e7b0/d;
+L_0x2a6e8a0/d .functor AND 1, L_0x2a6dc30, L_0x2a6e170, C4<1>, C4<1>;
+L_0x2a6e8a0 .delay (20000,20000,20000) L_0x2a6e8a0/d;
+L_0x2a6ea10/d .functor AND 1, L_0x2a6e6c0, L_0x2a6f100, C4<1>, C4<1>;
+L_0x2a6ea10 .delay (20000,20000,20000) L_0x2a6ea10/d;
+L_0x2a6eb00/d .functor OR 1, L_0x2a6e8a0, L_0x2a6ea10, C4<0>, C4<0>;
+L_0x2a6eb00 .delay (20000,20000,20000) L_0x2a6eb00/d;
+v0x2890f70_0 .net "A", 0 0, L_0x2a6dc30; 1 drivers
+v0x2891030_0 .net "AandB", 0 0, L_0x2a6e8a0; 1 drivers
+v0x28910d0_0 .net "AddSubSLTSum", 0 0, L_0x2a6e7b0; 1 drivers
+v0x2891170_0 .net "AxorB", 0 0, L_0x2a6e6c0; 1 drivers
+v0x28911f0_0 .net "B", 0 0, L_0x2a6f060; 1 drivers
+v0x28912a0_0 .net "BornB", 0 0, L_0x2a6e170; 1 drivers
+v0x2891360_0 .net "CINandAxorB", 0 0, L_0x2a6ea10; 1 drivers
+v0x28913e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x27f1c90_0 .net *"_s3", 0 0, L_0x2a6e440; 1 drivers
+v0x27f1d10_0 .net *"_s5", 0 0, L_0x2a6e620; 1 drivers
+v0x27f1db0_0 .net "carryin", 0 0, L_0x2a6f100; 1 drivers
+v0x27f1e50_0 .net "carryout", 0 0, L_0x2a6eb00; 1 drivers
+v0x27f1ef0_0 .net "nB", 0 0, L_0x2a6dd60; 1 drivers
+v0x27f1fa0_0 .net "nCmd2", 0 0, L_0x2a6e3a0; 1 drivers
+v0x27f20a0_0 .net "subtract", 0 0, L_0x2a6e4e0; 1 drivers
+L_0x2a6e300 .part v0x2960210_0, 0, 1;
+L_0x2a6e440 .part v0x2960210_0, 2, 1;
+L_0x2a6e620 .part v0x2960210_0, 0, 1;
+S_0x28909e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28908f0;
+ .timescale -9 -12;
+L_0x2a6def0/d .functor NOT 1, L_0x2a6e300, C4<0>, C4<0>, C4<0>;
+L_0x2a6def0 .delay (10000,10000,10000) L_0x2a6def0/d;
+L_0x2a6df90/d .functor AND 1, L_0x2a6f060, L_0x2a6def0, C4<1>, C4<1>;
+L_0x2a6df90 .delay (20000,20000,20000) L_0x2a6df90/d;
+L_0x2a6e080/d .functor AND 1, L_0x2a6dd60, L_0x2a6e300, C4<1>, C4<1>;
+L_0x2a6e080 .delay (20000,20000,20000) L_0x2a6e080/d;
+L_0x2a6e170/d .functor OR 1, L_0x2a6df90, L_0x2a6e080, C4<0>, C4<0>;
+L_0x2a6e170 .delay (20000,20000,20000) L_0x2a6e170/d;
+v0x2890ad0_0 .net "S", 0 0, L_0x2a6e300; 1 drivers
+v0x2890b90_0 .alias "in0", 0 0, v0x28911f0_0;
+v0x2890c30_0 .alias "in1", 0 0, v0x27f1ef0_0;
+v0x2890cd0_0 .net "nS", 0 0, L_0x2a6def0; 1 drivers
+v0x2890d50_0 .net "out0", 0 0, L_0x2a6df90; 1 drivers
+v0x2890df0_0 .net "out1", 0 0, L_0x2a6e080; 1 drivers
+v0x2890ed0_0 .alias "outfinal", 0 0, v0x28912a0_0;
+S_0x2890380 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288fc90;
+ .timescale -9 -12;
+L_0x2a6ee20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a6ee20 .delay (10000,10000,10000) L_0x2a6ee20/d;
+L_0x2a6eec0/d .functor AND 1, L_0x2a6f610, L_0x2a6ee20, C4<1>, C4<1>;
+L_0x2a6eec0 .delay (20000,20000,20000) L_0x2a6eec0/d;
+L_0x2a6efd0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a6efd0 .delay (20000,20000,20000) L_0x2a6efd0/d;
+L_0x2a6f430/d .functor OR 1, L_0x2a6eec0, L_0x2a6efd0, C4<0>, C4<0>;
+L_0x2a6f430 .delay (20000,20000,20000) L_0x2a6f430/d;
+v0x2890470_0 .alias "S", 0 0, v0x289f760_0;
+v0x2890510_0 .net "in0", 0 0, L_0x2a6f610; 1 drivers
+v0x28905b0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2890650_0 .net "nS", 0 0, L_0x2a6ee20; 1 drivers
+v0x28906d0_0 .net "out0", 0 0, L_0x2a6eec0; 1 drivers
+v0x2890770_0 .net "out1", 0 0, L_0x2a6efd0; 1 drivers
+v0x2890850_0 .net "outfinal", 0 0, L_0x2a6f430; 1 drivers
+S_0x288fe00 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288fc90;
+ .timescale -9 -12;
+L_0x2a6f230/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a6f230 .delay (10000,10000,10000) L_0x2a6f230/d;
+L_0x2a6f340/d .functor AND 1, L_0x2a6fc70, L_0x2a6f230, C4<1>, C4<1>;
+L_0x2a6f340 .delay (20000,20000,20000) L_0x2a6f340/d;
+L_0x2a6f9f0/d .functor AND 1, L_0x2a6f700, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a6f9f0 .delay (20000,20000,20000) L_0x2a6f9f0/d;
+L_0x2a6fa90/d .functor OR 1, L_0x2a6f340, L_0x2a6f9f0, C4<0>, C4<0>;
+L_0x2a6fa90 .delay (20000,20000,20000) L_0x2a6fa90/d;
+v0x288fef0_0 .alias "S", 0 0, v0x289f760_0;
+v0x288ff70_0 .net "in0", 0 0, L_0x2a6fc70; 1 drivers
+v0x2890010_0 .net "in1", 0 0, L_0x2a6f700; 1 drivers
+v0x28900b0_0 .net "nS", 0 0, L_0x2a6f230; 1 drivers
+v0x2890160_0 .net "out0", 0 0, L_0x2a6f340; 1 drivers
+v0x2890200_0 .net "out1", 0 0, L_0x2a6f9f0; 1 drivers
+v0x28902e0_0 .net "outfinal", 0 0, L_0x2a6fa90; 1 drivers
+S_0x288e010 .scope generate, "sltbits[8]" "sltbits[8]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x288da28 .param/l "i" 3 332, +C4<01000>;
+S_0x288ec70 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288e010;
+ .timescale -9 -12;
+L_0x2a6f7f0/d .functor NOT 1, L_0x2a711d0, C4<0>, C4<0>, C4<0>;
+L_0x2a6f7f0 .delay (10000,10000,10000) L_0x2a6f7f0/d;
+L_0x2a704d0/d .functor NOT 1, L_0x2a70570, C4<0>, C4<0>, C4<0>;
+L_0x2a704d0 .delay (10000,10000,10000) L_0x2a704d0/d;
+L_0x2a70610/d .functor AND 1, L_0x2a70750, L_0x2a704d0, C4<1>, C4<1>;
+L_0x2a70610 .delay (20000,20000,20000) L_0x2a70610/d;
+L_0x2a707f0/d .functor XOR 1, L_0x2a71130, L_0x2a702a0, C4<0>, C4<0>;
+L_0x2a707f0 .delay (40000,40000,40000) L_0x2a707f0/d;
+L_0x2a708e0/d .functor XOR 1, L_0x2a707f0, L_0x2a70ea0, C4<0>, C4<0>;
+L_0x2a708e0 .delay (40000,40000,40000) L_0x2a708e0/d;
+L_0x2a709d0/d .functor AND 1, L_0x2a71130, L_0x2a702a0, C4<1>, C4<1>;
+L_0x2a709d0 .delay (20000,20000,20000) L_0x2a709d0/d;
+L_0x2a70b40/d .functor AND 1, L_0x2a707f0, L_0x2a70ea0, C4<1>, C4<1>;
+L_0x2a70b40 .delay (20000,20000,20000) L_0x2a70b40/d;
+L_0x2a70c50/d .functor OR 1, L_0x2a709d0, L_0x2a70b40, C4<0>, C4<0>;
+L_0x2a70c50 .delay (20000,20000,20000) L_0x2a70c50/d;
+v0x288f2f0_0 .net "A", 0 0, L_0x2a71130; 1 drivers
+v0x288f3b0_0 .net "AandB", 0 0, L_0x2a709d0; 1 drivers
+v0x288f450_0 .net "AddSubSLTSum", 0 0, L_0x2a708e0; 1 drivers
+v0x288f4f0_0 .net "AxorB", 0 0, L_0x2a707f0; 1 drivers
+v0x288f570_0 .net "B", 0 0, L_0x2a711d0; 1 drivers
+v0x288f620_0 .net "BornB", 0 0, L_0x2a702a0; 1 drivers
+v0x288f6e0_0 .net "CINandAxorB", 0 0, L_0x2a70b40; 1 drivers
+v0x288f760_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x288f7e0_0 .net *"_s3", 0 0, L_0x2a70570; 1 drivers
+v0x288f860_0 .net *"_s5", 0 0, L_0x2a70750; 1 drivers
+v0x288f900_0 .net "carryin", 0 0, L_0x2a70ea0; 1 drivers
+v0x288f9a0_0 .net "carryout", 0 0, L_0x2a70c50; 1 drivers
+v0x288fa40_0 .net "nB", 0 0, L_0x2a6f7f0; 1 drivers
+v0x288faf0_0 .net "nCmd2", 0 0, L_0x2a704d0; 1 drivers
+v0x288fbf0_0 .net "subtract", 0 0, L_0x2a70610; 1 drivers
+L_0x2a70430 .part v0x2960210_0, 0, 1;
+L_0x2a70570 .part v0x2960210_0, 2, 1;
+L_0x2a70750 .part v0x2960210_0, 0, 1;
+S_0x288ed60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x288ec70;
+ .timescale -9 -12;
+L_0x2a70020/d .functor NOT 1, L_0x2a70430, C4<0>, C4<0>, C4<0>;
+L_0x2a70020 .delay (10000,10000,10000) L_0x2a70020/d;
+L_0x2a700c0/d .functor AND 1, L_0x2a711d0, L_0x2a70020, C4<1>, C4<1>;
+L_0x2a700c0 .delay (20000,20000,20000) L_0x2a700c0/d;
+L_0x2a701b0/d .functor AND 1, L_0x2a6f7f0, L_0x2a70430, C4<1>, C4<1>;
+L_0x2a701b0 .delay (20000,20000,20000) L_0x2a701b0/d;
+L_0x2a702a0/d .functor OR 1, L_0x2a700c0, L_0x2a701b0, C4<0>, C4<0>;
+L_0x2a702a0 .delay (20000,20000,20000) L_0x2a702a0/d;
+v0x288ee50_0 .net "S", 0 0, L_0x2a70430; 1 drivers
+v0x288ef10_0 .alias "in0", 0 0, v0x288f570_0;
+v0x288efb0_0 .alias "in1", 0 0, v0x288fa40_0;
+v0x288f050_0 .net "nS", 0 0, L_0x2a70020; 1 drivers
+v0x288f0d0_0 .net "out0", 0 0, L_0x2a700c0; 1 drivers
+v0x288f170_0 .net "out1", 0 0, L_0x2a701b0; 1 drivers
+v0x288f250_0 .alias "outfinal", 0 0, v0x288f620_0;
+S_0x288e700 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288e010;
+ .timescale -9 -12;
+L_0x2a68e50/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a68e50 .delay (10000,10000,10000) L_0x2a68e50/d;
+L_0x2a68ef0/d .functor AND 1, L_0x2a71270, L_0x2a68e50, C4<1>, C4<1>;
+L_0x2a68ef0 .delay (20000,20000,20000) L_0x2a68ef0/d;
+L_0x2a70ff0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a70ff0 .delay (20000,20000,20000) L_0x2a70ff0/d;
+L_0x2a71090/d .functor OR 1, L_0x2a68ef0, L_0x2a70ff0, C4<0>, C4<0>;
+L_0x2a71090 .delay (20000,20000,20000) L_0x2a71090/d;
+v0x288e7f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x288e890_0 .net "in0", 0 0, L_0x2a71270; 1 drivers
+v0x288e930_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x288e9d0_0 .net "nS", 0 0, L_0x2a68e50; 1 drivers
+v0x288ea50_0 .net "out0", 0 0, L_0x2a68ef0; 1 drivers
+v0x288eaf0_0 .net "out1", 0 0, L_0x2a70ff0; 1 drivers
+v0x288ebd0_0 .net "outfinal", 0 0, L_0x2a71090; 1 drivers
+S_0x288e180 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288e010;
+ .timescale -9 -12;
+L_0x2a693c0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a693c0 .delay (10000,10000,10000) L_0x2a693c0/d;
+L_0x2a713f0/d .functor AND 1, L_0x2a71860, L_0x2a693c0, C4<1>, C4<1>;
+L_0x2a713f0 .delay (20000,20000,20000) L_0x2a713f0/d;
+L_0x2a714b0/d .functor AND 1, L_0x2a71950, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a714b0 .delay (20000,20000,20000) L_0x2a714b0/d;
+L_0x2a71db0/d .functor OR 1, L_0x2a713f0, L_0x2a714b0, C4<0>, C4<0>;
+L_0x2a71db0 .delay (20000,20000,20000) L_0x2a71db0/d;
+v0x288e270_0 .alias "S", 0 0, v0x289f760_0;
+v0x288e2f0_0 .net "in0", 0 0, L_0x2a71860; 1 drivers
+v0x288e390_0 .net "in1", 0 0, L_0x2a71950; 1 drivers
+v0x288e430_0 .net "nS", 0 0, L_0x2a693c0; 1 drivers
+v0x288e4e0_0 .net "out0", 0 0, L_0x2a713f0; 1 drivers
+v0x288e580_0 .net "out1", 0 0, L_0x2a714b0; 1 drivers
+v0x288e660_0 .net "outfinal", 0 0, L_0x2a71db0; 1 drivers
+S_0x288c390 .scope generate, "sltbits[9]" "sltbits[9]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x288bc88 .param/l "i" 3 332, +C4<01001>;
+S_0x288cff0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288c390;
+ .timescale -9 -12;
+L_0x2a71a40/d .functor NOT 1, L_0x2a72120, C4<0>, C4<0>, C4<0>;
+L_0x2a71a40 .delay (10000,10000,10000) L_0x2a71a40/d;
+L_0x2a728b0/d .functor NOT 1, L_0x2a72970, C4<0>, C4<0>, C4<0>;
+L_0x2a728b0 .delay (10000,10000,10000) L_0x2a728b0/d;
+L_0x2a72a10/d .functor AND 1, L_0x2a72b50, L_0x2a728b0, C4<1>, C4<1>;
+L_0x2a72a10 .delay (20000,20000,20000) L_0x2a72a10/d;
+L_0x2a72bf0/d .functor XOR 1, L_0x2a72080, L_0x2a72640, C4<0>, C4<0>;
+L_0x2a72bf0 .delay (40000,40000,40000) L_0x2a72bf0/d;
+L_0x2a72ce0/d .functor XOR 1, L_0x2a72bf0, L_0x2a73660, C4<0>, C4<0>;
+L_0x2a72ce0 .delay (40000,40000,40000) L_0x2a72ce0/d;
+L_0x2a72dd0/d .functor AND 1, L_0x2a72080, L_0x2a72640, C4<1>, C4<1>;
+L_0x2a72dd0 .delay (20000,20000,20000) L_0x2a72dd0/d;
+L_0x2a72f40/d .functor AND 1, L_0x2a72bf0, L_0x2a73660, C4<1>, C4<1>;
+L_0x2a72f40 .delay (20000,20000,20000) L_0x2a72f40/d;
+L_0x2a73030/d .functor OR 1, L_0x2a72dd0, L_0x2a72f40, C4<0>, C4<0>;
+L_0x2a73030 .delay (20000,20000,20000) L_0x2a73030/d;
+v0x288d670_0 .net "A", 0 0, L_0x2a72080; 1 drivers
+v0x288d730_0 .net "AandB", 0 0, L_0x2a72dd0; 1 drivers
+v0x288d7d0_0 .net "AddSubSLTSum", 0 0, L_0x2a72ce0; 1 drivers
+v0x288d870_0 .net "AxorB", 0 0, L_0x2a72bf0; 1 drivers
+v0x288d8f0_0 .net "B", 0 0, L_0x2a72120; 1 drivers
+v0x288d9a0_0 .net "BornB", 0 0, L_0x2a72640; 1 drivers
+v0x288da60_0 .net "CINandAxorB", 0 0, L_0x2a72f40; 1 drivers
+v0x288dae0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x288db60_0 .net *"_s3", 0 0, L_0x2a72970; 1 drivers
+v0x288dbe0_0 .net *"_s5", 0 0, L_0x2a72b50; 1 drivers
+v0x288dc80_0 .net "carryin", 0 0, L_0x2a73660; 1 drivers
+v0x288dd20_0 .net "carryout", 0 0, L_0x2a73030; 1 drivers
+v0x288ddc0_0 .net "nB", 0 0, L_0x2a71a40; 1 drivers
+v0x288de70_0 .net "nCmd2", 0 0, L_0x2a728b0; 1 drivers
+v0x288df70_0 .net "subtract", 0 0, L_0x2a72a10; 1 drivers
+L_0x2a72810 .part v0x2960210_0, 0, 1;
+L_0x2a72970 .part v0x2960210_0, 2, 1;
+L_0x2a72b50 .part v0x2960210_0, 0, 1;
+S_0x288d0e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x288cff0;
+ .timescale -9 -12;
+L_0x2a72360/d .functor NOT 1, L_0x2a72810, C4<0>, C4<0>, C4<0>;
+L_0x2a72360 .delay (10000,10000,10000) L_0x2a72360/d;
+L_0x2a72420/d .functor AND 1, L_0x2a72120, L_0x2a72360, C4<1>, C4<1>;
+L_0x2a72420 .delay (20000,20000,20000) L_0x2a72420/d;
+L_0x2a72530/d .functor AND 1, L_0x2a71a40, L_0x2a72810, C4<1>, C4<1>;
+L_0x2a72530 .delay (20000,20000,20000) L_0x2a72530/d;
+L_0x2a72640/d .functor OR 1, L_0x2a72420, L_0x2a72530, C4<0>, C4<0>;
+L_0x2a72640 .delay (20000,20000,20000) L_0x2a72640/d;
+v0x288d1d0_0 .net "S", 0 0, L_0x2a72810; 1 drivers
+v0x288d290_0 .alias "in0", 0 0, v0x288d8f0_0;
+v0x288d330_0 .alias "in1", 0 0, v0x288ddc0_0;
+v0x288d3d0_0 .net "nS", 0 0, L_0x2a72360; 1 drivers
+v0x288d450_0 .net "out0", 0 0, L_0x2a72420; 1 drivers
+v0x288d4f0_0 .net "out1", 0 0, L_0x2a72530; 1 drivers
+v0x288d5d0_0 .alias "outfinal", 0 0, v0x288d9a0_0;
+S_0x288ca80 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288c390;
+ .timescale -9 -12;
+L_0x2a73370/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a73370 .delay (10000,10000,10000) L_0x2a73370/d;
+L_0x2a73410/d .functor AND 1, L_0x2a73b40, L_0x2a73370, C4<1>, C4<1>;
+L_0x2a73410 .delay (20000,20000,20000) L_0x2a73410/d;
+L_0x2a73520/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a73520 .delay (20000,20000,20000) L_0x2a73520/d;
+L_0x2a735c0/d .functor OR 1, L_0x2a73410, L_0x2a73520, C4<0>, C4<0>;
+L_0x2a735c0 .delay (20000,20000,20000) L_0x2a735c0/d;
+v0x288cb70_0 .alias "S", 0 0, v0x289f760_0;
+v0x288cc10_0 .net "in0", 0 0, L_0x2a73b40; 1 drivers
+v0x288ccb0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x288cd50_0 .net "nS", 0 0, L_0x2a73370; 1 drivers
+v0x288cdd0_0 .net "out0", 0 0, L_0x2a73410; 1 drivers
+v0x288ce70_0 .net "out1", 0 0, L_0x2a73520; 1 drivers
+v0x288cf50_0 .net "outfinal", 0 0, L_0x2a735c0; 1 drivers
+S_0x288c500 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288c390;
+ .timescale -9 -12;
+L_0x2a73790/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a73790 .delay (10000,10000,10000) L_0x2a73790/d;
+L_0x2a738a0/d .functor AND 1, L_0x2a74180, L_0x2a73790, C4<1>, C4<1>;
+L_0x2a738a0 .delay (20000,20000,20000) L_0x2a738a0/d;
+L_0x2a73f40/d .functor AND 1, L_0x2a73c30, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a73f40 .delay (20000,20000,20000) L_0x2a73f40/d;
+L_0x2a73fa0/d .functor OR 1, L_0x2a738a0, L_0x2a73f40, C4<0>, C4<0>;
+L_0x2a73fa0 .delay (20000,20000,20000) L_0x2a73fa0/d;
+v0x288c5f0_0 .alias "S", 0 0, v0x289f760_0;
+v0x288c670_0 .net "in0", 0 0, L_0x2a74180; 1 drivers
+v0x288c710_0 .net "in1", 0 0, L_0x2a73c30; 1 drivers
+v0x288c7b0_0 .net "nS", 0 0, L_0x2a73790; 1 drivers
+v0x288c860_0 .net "out0", 0 0, L_0x2a738a0; 1 drivers
+v0x288c900_0 .net "out1", 0 0, L_0x2a73f40; 1 drivers
+v0x288c9e0_0 .net "outfinal", 0 0, L_0x2a73fa0; 1 drivers
+S_0x288a700 .scope generate, "sltbits[10]" "sltbits[10]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x288a118 .param/l "i" 3 332, +C4<01010>;
+S_0x288b280 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x288a700;
+ .timescale -9 -12;
+L_0x2a73d20/d .functor NOT 1, L_0x2a744f0, C4<0>, C4<0>, C4<0>;
+L_0x2a73d20 .delay (10000,10000,10000) L_0x2a73d20/d;
+L_0x2a74aa0/d .functor NOT 1, L_0x2a74b60, C4<0>, C4<0>, C4<0>;
+L_0x2a74aa0 .delay (10000,10000,10000) L_0x2a74aa0/d;
+L_0x2a74c00/d .functor AND 1, L_0x2a74d40, L_0x2a74aa0, C4<1>, C4<1>;
+L_0x2a74c00 .delay (20000,20000,20000) L_0x2a74c00/d;
+L_0x2a74de0/d .functor XOR 1, L_0x2a74450, L_0x2a74830, C4<0>, C4<0>;
+L_0x2a74de0 .delay (40000,40000,40000) L_0x2a74de0/d;
+L_0x2a74ed0/d .functor XOR 1, L_0x2a74de0, L_0x2a75470, C4<0>, C4<0>;
+L_0x2a74ed0 .delay (40000,40000,40000) L_0x2a74ed0/d;
+L_0x2a74fc0/d .functor AND 1, L_0x2a74450, L_0x2a74830, C4<1>, C4<1>;
+L_0x2a74fc0 .delay (20000,20000,20000) L_0x2a74fc0/d;
+L_0x2a75130/d .functor AND 1, L_0x2a74de0, L_0x2a75470, C4<1>, C4<1>;
+L_0x2a75130 .delay (20000,20000,20000) L_0x2a75130/d;
+L_0x2a75220/d .functor OR 1, L_0x2a74fc0, L_0x2a75130, C4<0>, C4<0>;
+L_0x2a75220 .delay (20000,20000,20000) L_0x2a75220/d;
+v0x288b900_0 .net "A", 0 0, L_0x2a74450; 1 drivers
+v0x288b9c0_0 .net "AandB", 0 0, L_0x2a74fc0; 1 drivers
+v0x288ba60_0 .net "AddSubSLTSum", 0 0, L_0x2a74ed0; 1 drivers
+v0x288bb00_0 .net "AxorB", 0 0, L_0x2a74de0; 1 drivers
+v0x288bb80_0 .net "B", 0 0, L_0x2a744f0; 1 drivers
+v0x288bc00_0 .net "BornB", 0 0, L_0x2a74830; 1 drivers
+v0x288bcc0_0 .net "CINandAxorB", 0 0, L_0x2a75130; 1 drivers
+v0x288bd40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x288be10_0 .net *"_s3", 0 0, L_0x2a74b60; 1 drivers
+v0x288be90_0 .net *"_s5", 0 0, L_0x2a74d40; 1 drivers
+v0x288bf90_0 .net "carryin", 0 0, L_0x2a75470; 1 drivers
+v0x288c030_0 .net "carryout", 0 0, L_0x2a75220; 1 drivers
+v0x288c140_0 .net "nB", 0 0, L_0x2a73d20; 1 drivers
+v0x288c1f0_0 .net "nCmd2", 0 0, L_0x2a74aa0; 1 drivers
+v0x288c2f0_0 .net "subtract", 0 0, L_0x2a74c00; 1 drivers
+L_0x2a74a00 .part v0x2960210_0, 0, 1;
+L_0x2a74b60 .part v0x2960210_0, 2, 1;
+L_0x2a74d40 .part v0x2960210_0, 0, 1;
+S_0x288b370 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x288b280;
+ .timescale -9 -12;
+L_0x2a74590/d .functor NOT 1, L_0x2a74a00, C4<0>, C4<0>, C4<0>;
+L_0x2a74590 .delay (10000,10000,10000) L_0x2a74590/d;
+L_0x2a74630/d .functor AND 1, L_0x2a744f0, L_0x2a74590, C4<1>, C4<1>;
+L_0x2a74630 .delay (20000,20000,20000) L_0x2a74630/d;
+L_0x2a74720/d .functor AND 1, L_0x2a73d20, L_0x2a74a00, C4<1>, C4<1>;
+L_0x2a74720 .delay (20000,20000,20000) L_0x2a74720/d;
+L_0x2a74830/d .functor OR 1, L_0x2a74630, L_0x2a74720, C4<0>, C4<0>;
+L_0x2a74830 .delay (20000,20000,20000) L_0x2a74830/d;
+v0x288b460_0 .net "S", 0 0, L_0x2a74a00; 1 drivers
+v0x288b500_0 .alias "in0", 0 0, v0x288bb80_0;
+v0x288b5a0_0 .alias "in1", 0 0, v0x288c140_0;
+v0x288b640_0 .net "nS", 0 0, L_0x2a74590; 1 drivers
+v0x288b6e0_0 .net "out0", 0 0, L_0x2a74630; 1 drivers
+v0x288b780_0 .net "out1", 0 0, L_0x2a74720; 1 drivers
+v0x288b860_0 .alias "outfinal", 0 0, v0x288bc00_0;
+S_0x288adf0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x288a700;
+ .timescale -9 -12;
+L_0x2a75510/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a75510 .delay (10000,10000,10000) L_0x2a75510/d;
+L_0x2a755b0/d .functor AND 1, L_0x2a75840, L_0x2a75510, C4<1>, C4<1>;
+L_0x2a755b0 .delay (20000,20000,20000) L_0x2a755b0/d;
+L_0x2a756c0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a756c0 .delay (20000,20000,20000) L_0x2a756c0/d;
+L_0x2a75b90/d .functor OR 1, L_0x2a755b0, L_0x2a756c0, C4<0>, C4<0>;
+L_0x2a75b90 .delay (20000,20000,20000) L_0x2a75b90/d;
+v0x288aee0_0 .alias "S", 0 0, v0x289f760_0;
+v0x288af80_0 .net "in0", 0 0, L_0x2a75840; 1 drivers
+v0x288b000_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x288b080_0 .net "nS", 0 0, L_0x2a75510; 1 drivers
+v0x288b100_0 .net "out0", 0 0, L_0x2a755b0; 1 drivers
+v0x288b180_0 .net "out1", 0 0, L_0x2a756c0; 1 drivers
+v0x288b200_0 .net "outfinal", 0 0, L_0x2a75b90; 1 drivers
+S_0x288a870 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x288a700;
+ .timescale -9 -12;
+L_0x2a75b30/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a75b30 .delay (10000,10000,10000) L_0x2a75b30/d;
+L_0x2a6cea0/d .functor AND 1, L_0x2a75d70, L_0x2a75b30, C4<1>, C4<1>;
+L_0x2a6cea0 .delay (20000,20000,20000) L_0x2a6cea0/d;
+L_0x2a76160/d .functor AND 1, L_0x2a75e60, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a76160 .delay (20000,20000,20000) L_0x2a76160/d;
+L_0x2a76200/d .functor OR 1, L_0x2a6cea0, L_0x2a76160, C4<0>, C4<0>;
+L_0x2a76200 .delay (20000,20000,20000) L_0x2a76200/d;
+v0x288a960_0 .alias "S", 0 0, v0x289f760_0;
+v0x288a9e0_0 .net "in0", 0 0, L_0x2a75d70; 1 drivers
+v0x288aa80_0 .net "in1", 0 0, L_0x2a75e60; 1 drivers
+v0x288ab20_0 .net "nS", 0 0, L_0x2a75b30; 1 drivers
+v0x288abd0_0 .net "out0", 0 0, L_0x2a6cea0; 1 drivers
+v0x288ac70_0 .net "out1", 0 0, L_0x2a76160; 1 drivers
+v0x288ad50_0 .net "outfinal", 0 0, L_0x2a76200; 1 drivers
+S_0x2888a80 .scope generate, "sltbits[11]" "sltbits[11]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2888498 .param/l "i" 3 332, +C4<01011>;
+S_0x28896e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2888a80;
+ .timescale -9 -12;
+L_0x2a75f50/d .functor NOT 1, L_0x2a76570, C4<0>, C4<0>, C4<0>;
+L_0x2a75f50 .delay (10000,10000,10000) L_0x2a75f50/d;
+L_0x2a76cc0/d .functor NOT 1, L_0x2a76d80, C4<0>, C4<0>, C4<0>;
+L_0x2a76cc0 .delay (10000,10000,10000) L_0x2a76cc0/d;
+L_0x2a76e20/d .functor AND 1, L_0x2a76f60, L_0x2a76cc0, C4<1>, C4<1>;
+L_0x2a76e20 .delay (20000,20000,20000) L_0x2a76e20/d;
+L_0x2a77000/d .functor XOR 1, L_0x2a764d0, L_0x2a76a50, C4<0>, C4<0>;
+L_0x2a77000 .delay (40000,40000,40000) L_0x2a77000/d;
+L_0x2a770f0/d .functor XOR 1, L_0x2a77000, L_0x2a766a0, C4<0>, C4<0>;
+L_0x2a770f0 .delay (40000,40000,40000) L_0x2a770f0/d;
+L_0x2a771e0/d .functor AND 1, L_0x2a764d0, L_0x2a76a50, C4<1>, C4<1>;
+L_0x2a771e0 .delay (20000,20000,20000) L_0x2a771e0/d;
+L_0x2a77350/d .functor AND 1, L_0x2a77000, L_0x2a766a0, C4<1>, C4<1>;
+L_0x2a77350 .delay (20000,20000,20000) L_0x2a77350/d;
+L_0x2a77460/d .functor OR 1, L_0x2a771e0, L_0x2a77350, C4<0>, C4<0>;
+L_0x2a77460 .delay (20000,20000,20000) L_0x2a77460/d;
+v0x2889d60_0 .net "A", 0 0, L_0x2a764d0; 1 drivers
+v0x2889e20_0 .net "AandB", 0 0, L_0x2a771e0; 1 drivers
+v0x2889ec0_0 .net "AddSubSLTSum", 0 0, L_0x2a770f0; 1 drivers
+v0x2889f60_0 .net "AxorB", 0 0, L_0x2a77000; 1 drivers
+v0x2889fe0_0 .net "B", 0 0, L_0x2a76570; 1 drivers
+v0x288a090_0 .net "BornB", 0 0, L_0x2a76a50; 1 drivers
+v0x288a150_0 .net "CINandAxorB", 0 0, L_0x2a77350; 1 drivers
+v0x288a1d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x288a250_0 .net *"_s3", 0 0, L_0x2a76d80; 1 drivers
+v0x288a2d0_0 .net *"_s5", 0 0, L_0x2a76f60; 1 drivers
+v0x288a370_0 .net "carryin", 0 0, L_0x2a766a0; 1 drivers
+v0x288a410_0 .net "carryout", 0 0, L_0x2a77460; 1 drivers
+v0x288a4b0_0 .net "nB", 0 0, L_0x2a75f50; 1 drivers
+v0x288a560_0 .net "nCmd2", 0 0, L_0x2a76cc0; 1 drivers
+v0x288a660_0 .net "subtract", 0 0, L_0x2a76e20; 1 drivers
+L_0x2a76c20 .part v0x2960210_0, 0, 1;
+L_0x2a76d80 .part v0x2960210_0, 2, 1;
+L_0x2a76f60 .part v0x2960210_0, 0, 1;
+S_0x28897d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28896e0;
+ .timescale -9 -12;
+L_0x2a767b0/d .functor NOT 1, L_0x2a76c20, C4<0>, C4<0>, C4<0>;
+L_0x2a767b0 .delay (10000,10000,10000) L_0x2a767b0/d;
+L_0x2a76850/d .functor AND 1, L_0x2a76570, L_0x2a767b0, C4<1>, C4<1>;
+L_0x2a76850 .delay (20000,20000,20000) L_0x2a76850/d;
+L_0x2a76940/d .functor AND 1, L_0x2a75f50, L_0x2a76c20, C4<1>, C4<1>;
+L_0x2a76940 .delay (20000,20000,20000) L_0x2a76940/d;
+L_0x2a76a50/d .functor OR 1, L_0x2a76850, L_0x2a76940, C4<0>, C4<0>;
+L_0x2a76a50 .delay (20000,20000,20000) L_0x2a76a50/d;
+v0x28898c0_0 .net "S", 0 0, L_0x2a76c20; 1 drivers
+v0x2889980_0 .alias "in0", 0 0, v0x2889fe0_0;
+v0x2889a20_0 .alias "in1", 0 0, v0x288a4b0_0;
+v0x2889ac0_0 .net "nS", 0 0, L_0x2a767b0; 1 drivers
+v0x2889b40_0 .net "out0", 0 0, L_0x2a76850; 1 drivers
+v0x2889be0_0 .net "out1", 0 0, L_0x2a76940; 1 drivers
+v0x2889cc0_0 .alias "outfinal", 0 0, v0x288a090_0;
+S_0x2889170 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2888a80;
+ .timescale -9 -12;
+L_0x2a77b50/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a77b50 .delay (10000,10000,10000) L_0x2a77b50/d;
+L_0x2a77bd0/d .functor AND 1, L_0x2a77f60, L_0x2a77b50, C4<1>, C4<1>;
+L_0x2a77bd0 .delay (20000,20000,20000) L_0x2a77bd0/d;
+L_0x2a77ce0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a77ce0 .delay (20000,20000,20000) L_0x2a77ce0/d;
+L_0x2a77d80/d .functor OR 1, L_0x2a77bd0, L_0x2a77ce0, C4<0>, C4<0>;
+L_0x2a77d80 .delay (20000,20000,20000) L_0x2a77d80/d;
+v0x2889260_0 .alias "S", 0 0, v0x289f760_0;
+v0x2889300_0 .net "in0", 0 0, L_0x2a77f60; 1 drivers
+v0x28893a0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2889440_0 .net "nS", 0 0, L_0x2a77b50; 1 drivers
+v0x28894c0_0 .net "out0", 0 0, L_0x2a77bd0; 1 drivers
+v0x2889560_0 .net "out1", 0 0, L_0x2a77ce0; 1 drivers
+v0x2889640_0 .net "outfinal", 0 0, L_0x2a77d80; 1 drivers
+S_0x2888bf0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2888a80;
+ .timescale -9 -12;
+L_0x2a77830/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a77830 .delay (10000,10000,10000) L_0x2a77830/d;
+L_0x2a77940/d .functor AND 1, L_0x2a78590, L_0x2a77830, C4<1>, C4<1>;
+L_0x2a77940 .delay (20000,20000,20000) L_0x2a77940/d;
+L_0x2a77a50/d .functor AND 1, L_0x2a6d3c0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a77a50 .delay (20000,20000,20000) L_0x2a77a50/d;
+L_0x2a77af0/d .functor OR 1, L_0x2a77940, L_0x2a77a50, C4<0>, C4<0>;
+L_0x2a77af0 .delay (20000,20000,20000) L_0x2a77af0/d;
+v0x2888ce0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2888d60_0 .net "in0", 0 0, L_0x2a78590; 1 drivers
+v0x2888e00_0 .net "in1", 0 0, L_0x2a6d3c0; 1 drivers
+v0x2888ea0_0 .net "nS", 0 0, L_0x2a77830; 1 drivers
+v0x2888f50_0 .net "out0", 0 0, L_0x2a77940; 1 drivers
+v0x2888ff0_0 .net "out1", 0 0, L_0x2a77a50; 1 drivers
+v0x28890d0_0 .net "outfinal", 0 0, L_0x2a77af0; 1 drivers
+S_0x2886e00 .scope generate, "sltbits[12]" "sltbits[12]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2886818 .param/l "i" 3 332, +C4<01100>;
+S_0x2887a60 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2886e00;
+ .timescale -9 -12;
+L_0x2a6d4b0/d .functor NOT 1, L_0x2a78d10, C4<0>, C4<0>, C4<0>;
+L_0x2a6d4b0 .delay (10000,10000,10000) L_0x2a6d4b0/d;
+L_0x2a78fe0/d .functor NOT 1, L_0x2a79080, C4<0>, C4<0>, C4<0>;
+L_0x2a78fe0 .delay (10000,10000,10000) L_0x2a78fe0/d;
+L_0x2a79120/d .functor AND 1, L_0x2a79260, L_0x2a78fe0, C4<1>, C4<1>;
+L_0x2a79120 .delay (20000,20000,20000) L_0x2a79120/d;
+L_0x2a79300/d .functor XOR 1, L_0x2a78c70, L_0x2a78330, C4<0>, C4<0>;
+L_0x2a79300 .delay (40000,40000,40000) L_0x2a79300/d;
+L_0x2a793f0/d .functor XOR 1, L_0x2a79300, L_0x2a79d70, C4<0>, C4<0>;
+L_0x2a793f0 .delay (40000,40000,40000) L_0x2a793f0/d;
+L_0x2a794e0/d .functor AND 1, L_0x2a78c70, L_0x2a78330, C4<1>, C4<1>;
+L_0x2a794e0 .delay (20000,20000,20000) L_0x2a794e0/d;
+L_0x2a79650/d .functor AND 1, L_0x2a79300, L_0x2a79d70, C4<1>, C4<1>;
+L_0x2a79650 .delay (20000,20000,20000) L_0x2a79650/d;
+L_0x2a79740/d .functor OR 1, L_0x2a794e0, L_0x2a79650, C4<0>, C4<0>;
+L_0x2a79740 .delay (20000,20000,20000) L_0x2a79740/d;
+v0x28880e0_0 .net "A", 0 0, L_0x2a78c70; 1 drivers
+v0x28881a0_0 .net "AandB", 0 0, L_0x2a794e0; 1 drivers
+v0x2888240_0 .net "AddSubSLTSum", 0 0, L_0x2a793f0; 1 drivers
+v0x28882e0_0 .net "AxorB", 0 0, L_0x2a79300; 1 drivers
+v0x2888360_0 .net "B", 0 0, L_0x2a78d10; 1 drivers
+v0x2888410_0 .net "BornB", 0 0, L_0x2a78330; 1 drivers
+v0x28884d0_0 .net "CINandAxorB", 0 0, L_0x2a79650; 1 drivers
+v0x2888550_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28885d0_0 .net *"_s3", 0 0, L_0x2a79080; 1 drivers
+v0x2888650_0 .net *"_s5", 0 0, L_0x2a79260; 1 drivers
+v0x28886f0_0 .net "carryin", 0 0, L_0x2a79d70; 1 drivers
+v0x2888790_0 .net "carryout", 0 0, L_0x2a79740; 1 drivers
+v0x2888830_0 .net "nB", 0 0, L_0x2a6d4b0; 1 drivers
+v0x28888e0_0 .net "nCmd2", 0 0, L_0x2a78fe0; 1 drivers
+v0x28889e0_0 .net "subtract", 0 0, L_0x2a79120; 1 drivers
+L_0x2a78f40 .part v0x2960210_0, 0, 1;
+L_0x2a79080 .part v0x2960210_0, 2, 1;
+L_0x2a79260 .part v0x2960210_0, 0, 1;
+S_0x2887b50 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2887a60;
+ .timescale -9 -12;
+L_0x2a78050/d .functor NOT 1, L_0x2a78f40, C4<0>, C4<0>, C4<0>;
+L_0x2a78050 .delay (10000,10000,10000) L_0x2a78050/d;
+L_0x2a78110/d .functor AND 1, L_0x2a78d10, L_0x2a78050, C4<1>, C4<1>;
+L_0x2a78110 .delay (20000,20000,20000) L_0x2a78110/d;
+L_0x2a78220/d .functor AND 1, L_0x2a6d4b0, L_0x2a78f40, C4<1>, C4<1>;
+L_0x2a78220 .delay (20000,20000,20000) L_0x2a78220/d;
+L_0x2a78330/d .functor OR 1, L_0x2a78110, L_0x2a78220, C4<0>, C4<0>;
+L_0x2a78330 .delay (20000,20000,20000) L_0x2a78330/d;
+v0x2887c40_0 .net "S", 0 0, L_0x2a78f40; 1 drivers
+v0x2887d00_0 .alias "in0", 0 0, v0x2888360_0;
+v0x2887da0_0 .alias "in1", 0 0, v0x2888830_0;
+v0x2887e40_0 .net "nS", 0 0, L_0x2a78050; 1 drivers
+v0x2887ec0_0 .net "out0", 0 0, L_0x2a78110; 1 drivers
+v0x2887f60_0 .net "out1", 0 0, L_0x2a78220; 1 drivers
+v0x2888040_0 .alias "outfinal", 0 0, v0x2888410_0;
+S_0x28874f0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2886e00;
+ .timescale -9 -12;
+L_0x2a79e10/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a79e10 .delay (10000,10000,10000) L_0x2a79e10/d;
+L_0x2a79e70/d .functor AND 1, L_0x2a79970, L_0x2a79e10, C4<1>, C4<1>;
+L_0x2a79e70 .delay (20000,20000,20000) L_0x2a79e70/d;
+L_0x2a79f60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a79f60 .delay (20000,20000,20000) L_0x2a79f60/d;
+L_0x2a7a010/d .functor OR 1, L_0x2a79e70, L_0x2a79f60, C4<0>, C4<0>;
+L_0x2a7a010 .delay (20000,20000,20000) L_0x2a7a010/d;
+v0x28875e0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2887680_0 .net "in0", 0 0, L_0x2a79970; 1 drivers
+v0x2887720_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28877c0_0 .net "nS", 0 0, L_0x2a79e10; 1 drivers
+v0x2887840_0 .net "out0", 0 0, L_0x2a79e70; 1 drivers
+v0x28878e0_0 .net "out1", 0 0, L_0x2a79f60; 1 drivers
+v0x28879c0_0 .net "outfinal", 0 0, L_0x2a7a010; 1 drivers
+S_0x2886f70 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2886e00;
+ .timescale -9 -12;
+L_0x2a79c70/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a79c70 .delay (10000,10000,10000) L_0x2a79c70/d;
+L_0x2a75a30/d .functor AND 1, L_0x2a7a1f0, L_0x2a79c70, C4<1>, C4<1>;
+L_0x2a75a30 .delay (20000,20000,20000) L_0x2a75a30/d;
+L_0x2a7a600/d .functor AND 1, L_0x2a7a2e0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a7a600 .delay (20000,20000,20000) L_0x2a7a600/d;
+L_0x2a7a6a0/d .functor OR 1, L_0x2a75a30, L_0x2a7a600, C4<0>, C4<0>;
+L_0x2a7a6a0 .delay (20000,20000,20000) L_0x2a7a6a0/d;
+v0x2887060_0 .alias "S", 0 0, v0x289f760_0;
+v0x28870e0_0 .net "in0", 0 0, L_0x2a7a1f0; 1 drivers
+v0x2887180_0 .net "in1", 0 0, L_0x2a7a2e0; 1 drivers
+v0x2887220_0 .net "nS", 0 0, L_0x2a79c70; 1 drivers
+v0x28872d0_0 .net "out0", 0 0, L_0x2a75a30; 1 drivers
+v0x2887370_0 .net "out1", 0 0, L_0x2a7a600; 1 drivers
+v0x2887450_0 .net "outfinal", 0 0, L_0x2a7a6a0; 1 drivers
+S_0x2885180 .scope generate, "sltbits[13]" "sltbits[13]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2884b98 .param/l "i" 3 332, +C4<01101>;
+S_0x2885de0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2885180;
+ .timescale -9 -12;
+L_0x2a7a3d0/d .functor NOT 1, L_0x2a7aa10, C4<0>, C4<0>, C4<0>;
+L_0x2a7a3d0 .delay (10000,10000,10000) L_0x2a7a3d0/d;
+L_0x2a7b100/d .functor NOT 1, L_0x2a7b1a0, C4<0>, C4<0>, C4<0>;
+L_0x2a7b100 .delay (10000,10000,10000) L_0x2a7b100/d;
+L_0x2a7b240/d .functor AND 1, L_0x2a7b380, L_0x2a7b100, C4<1>, C4<1>;
+L_0x2a7b240 .delay (20000,20000,20000) L_0x2a7b240/d;
+L_0x2a7b420/d .functor XOR 1, L_0x2a7a970, L_0x2a7aed0, C4<0>, C4<0>;
+L_0x2a7b420 .delay (40000,40000,40000) L_0x2a7b420/d;
+L_0x2a7b510/d .functor XOR 1, L_0x2a7b420, L_0x2a7ab40, C4<0>, C4<0>;
+L_0x2a7b510 .delay (40000,40000,40000) L_0x2a7b510/d;
+L_0x2a7b600/d .functor AND 1, L_0x2a7a970, L_0x2a7aed0, C4<1>, C4<1>;
+L_0x2a7b600 .delay (20000,20000,20000) L_0x2a7b600/d;
+L_0x2a7b770/d .functor AND 1, L_0x2a7b420, L_0x2a7ab40, C4<1>, C4<1>;
+L_0x2a7b770 .delay (20000,20000,20000) L_0x2a7b770/d;
+L_0x2a7b860/d .functor OR 1, L_0x2a7b600, L_0x2a7b770, C4<0>, C4<0>;
+L_0x2a7b860 .delay (20000,20000,20000) L_0x2a7b860/d;
+v0x2886460_0 .net "A", 0 0, L_0x2a7a970; 1 drivers
+v0x2886520_0 .net "AandB", 0 0, L_0x2a7b600; 1 drivers
+v0x28865c0_0 .net "AddSubSLTSum", 0 0, L_0x2a7b510; 1 drivers
+v0x2886660_0 .net "AxorB", 0 0, L_0x2a7b420; 1 drivers
+v0x28866e0_0 .net "B", 0 0, L_0x2a7aa10; 1 drivers
+v0x2886790_0 .net "BornB", 0 0, L_0x2a7aed0; 1 drivers
+v0x2886850_0 .net "CINandAxorB", 0 0, L_0x2a7b770; 1 drivers
+v0x28868d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2886950_0 .net *"_s3", 0 0, L_0x2a7b1a0; 1 drivers
+v0x28869d0_0 .net *"_s5", 0 0, L_0x2a7b380; 1 drivers
+v0x2886a70_0 .net "carryin", 0 0, L_0x2a7ab40; 1 drivers
+v0x2886b10_0 .net "carryout", 0 0, L_0x2a7b860; 1 drivers
+v0x2886bb0_0 .net "nB", 0 0, L_0x2a7a3d0; 1 drivers
+v0x2886c60_0 .net "nCmd2", 0 0, L_0x2a7b100; 1 drivers
+v0x2886d60_0 .net "subtract", 0 0, L_0x2a7b240; 1 drivers
+L_0x2a7b060 .part v0x2960210_0, 0, 1;
+L_0x2a7b1a0 .part v0x2960210_0, 2, 1;
+L_0x2a7b380 .part v0x2960210_0, 0, 1;
+S_0x2885ed0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2885de0;
+ .timescale -9 -12;
+L_0x2a7a5a0/d .functor NOT 1, L_0x2a7b060, C4<0>, C4<0>, C4<0>;
+L_0x2a7a5a0 .delay (10000,10000,10000) L_0x2a7a5a0/d;
+L_0x2a7acf0/d .functor AND 1, L_0x2a7aa10, L_0x2a7a5a0, C4<1>, C4<1>;
+L_0x2a7acf0 .delay (20000,20000,20000) L_0x2a7acf0/d;
+L_0x2a7ade0/d .functor AND 1, L_0x2a7a3d0, L_0x2a7b060, C4<1>, C4<1>;
+L_0x2a7ade0 .delay (20000,20000,20000) L_0x2a7ade0/d;
+L_0x2a7aed0/d .functor OR 1, L_0x2a7acf0, L_0x2a7ade0, C4<0>, C4<0>;
+L_0x2a7aed0 .delay (20000,20000,20000) L_0x2a7aed0/d;
+v0x2885fc0_0 .net "S", 0 0, L_0x2a7b060; 1 drivers
+v0x2886080_0 .alias "in0", 0 0, v0x28866e0_0;
+v0x2886120_0 .alias "in1", 0 0, v0x2886bb0_0;
+v0x28861c0_0 .net "nS", 0 0, L_0x2a7a5a0; 1 drivers
+v0x2886240_0 .net "out0", 0 0, L_0x2a7acf0; 1 drivers
+v0x28862e0_0 .net "out1", 0 0, L_0x2a7ade0; 1 drivers
+v0x28863c0_0 .alias "outfinal", 0 0, v0x2886790_0;
+S_0x2885870 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2885180;
+ .timescale -9 -12;
+L_0x2a7abe0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7abe0 .delay (10000,10000,10000) L_0x2a7abe0/d;
+L_0x2a7bfe0/d .functor AND 1, L_0x2a7c350, L_0x2a7abe0, C4<1>, C4<1>;
+L_0x2a7bfe0 .delay (20000,20000,20000) L_0x2a7bfe0/d;
+L_0x2a7c0d0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a7c0d0 .delay (20000,20000,20000) L_0x2a7c0d0/d;
+L_0x2a7c170/d .functor OR 1, L_0x2a7bfe0, L_0x2a7c0d0, C4<0>, C4<0>;
+L_0x2a7c170 .delay (20000,20000,20000) L_0x2a7c170/d;
+v0x2885960_0 .alias "S", 0 0, v0x289f760_0;
+v0x2885a00_0 .net "in0", 0 0, L_0x2a7c350; 1 drivers
+v0x2885aa0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2885b40_0 .net "nS", 0 0, L_0x2a7abe0; 1 drivers
+v0x2885bc0_0 .net "out0", 0 0, L_0x2a7bfe0; 1 drivers
+v0x2885c60_0 .net "out1", 0 0, L_0x2a7c0d0; 1 drivers
+v0x2885d40_0 .net "outfinal", 0 0, L_0x2a7c170; 1 drivers
+S_0x28852f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2885180;
+ .timescale -9 -12;
+L_0x2a7bc10/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7bc10 .delay (10000,10000,10000) L_0x2a7bc10/d;
+L_0x2a7bd20/d .functor AND 1, L_0x2a7c9a0, L_0x2a7bc10, C4<1>, C4<1>;
+L_0x2a7bd20 .delay (20000,20000,20000) L_0x2a7bd20/d;
+L_0x2a7be30/d .functor AND 1, L_0x2a7c440, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a7be30 .delay (20000,20000,20000) L_0x2a7be30/d;
+L_0x2a7bed0/d .functor OR 1, L_0x2a7bd20, L_0x2a7be30, C4<0>, C4<0>;
+L_0x2a7bed0 .delay (20000,20000,20000) L_0x2a7bed0/d;
+v0x28853e0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2885460_0 .net "in0", 0 0, L_0x2a7c9a0; 1 drivers
+v0x2885500_0 .net "in1", 0 0, L_0x2a7c440; 1 drivers
+v0x28855a0_0 .net "nS", 0 0, L_0x2a7bc10; 1 drivers
+v0x2885650_0 .net "out0", 0 0, L_0x2a7bd20; 1 drivers
+v0x28856f0_0 .net "out1", 0 0, L_0x2a7be30; 1 drivers
+v0x28857d0_0 .net "outfinal", 0 0, L_0x2a7bed0; 1 drivers
+S_0x2883500 .scope generate, "sltbits[14]" "sltbits[14]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2882df8 .param/l "i" 3 332, +C4<01110>;
+S_0x2884160 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2883500;
+ .timescale -9 -12;
+L_0x2a7c530/d .functor NOT 1, L_0x2a7cd10, C4<0>, C4<0>, C4<0>;
+L_0x2a7c530 .delay (10000,10000,10000) L_0x2a7c530/d;
+L_0x2a7d230/d .functor NOT 1, L_0x2a7d2d0, C4<0>, C4<0>, C4<0>;
+L_0x2a7d230 .delay (10000,10000,10000) L_0x2a7d230/d;
+L_0x2a7d370/d .functor AND 1, L_0x2a7d4b0, L_0x2a7d230, C4<1>, C4<1>;
+L_0x2a7d370 .delay (20000,20000,20000) L_0x2a7d370/d;
+L_0x2a7d550/d .functor XOR 1, L_0x2a7cc70, L_0x2a7d000, C4<0>, C4<0>;
+L_0x2a7d550 .delay (40000,40000,40000) L_0x2a7d550/d;
+L_0x2a7d640/d .functor XOR 1, L_0x2a7d550, L_0x2a7ce40, C4<0>, C4<0>;
+L_0x2a7d640 .delay (40000,40000,40000) L_0x2a7d640/d;
+L_0x2a7d730/d .functor AND 1, L_0x2a7cc70, L_0x2a7d000, C4<1>, C4<1>;
+L_0x2a7d730 .delay (20000,20000,20000) L_0x2a7d730/d;
+L_0x2a7d8a0/d .functor AND 1, L_0x2a7d550, L_0x2a7ce40, C4<1>, C4<1>;
+L_0x2a7d8a0 .delay (20000,20000,20000) L_0x2a7d8a0/d;
+L_0x2a7d990/d .functor OR 1, L_0x2a7d730, L_0x2a7d8a0, C4<0>, C4<0>;
+L_0x2a7d990 .delay (20000,20000,20000) L_0x2a7d990/d;
+v0x28847e0_0 .net "A", 0 0, L_0x2a7cc70; 1 drivers
+v0x28848a0_0 .net "AandB", 0 0, L_0x2a7d730; 1 drivers
+v0x2884940_0 .net "AddSubSLTSum", 0 0, L_0x2a7d640; 1 drivers
+v0x28849e0_0 .net "AxorB", 0 0, L_0x2a7d550; 1 drivers
+v0x2884a60_0 .net "B", 0 0, L_0x2a7cd10; 1 drivers
+v0x2884b10_0 .net "BornB", 0 0, L_0x2a7d000; 1 drivers
+v0x2884bd0_0 .net "CINandAxorB", 0 0, L_0x2a7d8a0; 1 drivers
+v0x2884c50_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2884cd0_0 .net *"_s3", 0 0, L_0x2a7d2d0; 1 drivers
+v0x2884d50_0 .net *"_s5", 0 0, L_0x2a7d4b0; 1 drivers
+v0x2884df0_0 .net "carryin", 0 0, L_0x2a7ce40; 1 drivers
+v0x2884e90_0 .net "carryout", 0 0, L_0x2a7d990; 1 drivers
+v0x2884f30_0 .net "nB", 0 0, L_0x2a7c530; 1 drivers
+v0x2884fe0_0 .net "nCmd2", 0 0, L_0x2a7d230; 1 drivers
+v0x28850e0_0 .net "subtract", 0 0, L_0x2a7d370; 1 drivers
+L_0x2a7d190 .part v0x2960210_0, 0, 1;
+L_0x2a7d2d0 .part v0x2960210_0, 2, 1;
+L_0x2a7d4b0 .part v0x2960210_0, 0, 1;
+S_0x2884250 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2884160;
+ .timescale -9 -12;
+L_0x2a7c6e0/d .functor NOT 1, L_0x2a7d190, C4<0>, C4<0>, C4<0>;
+L_0x2a7c6e0 .delay (10000,10000,10000) L_0x2a7c6e0/d;
+L_0x2a7c7a0/d .functor AND 1, L_0x2a7cd10, L_0x2a7c6e0, C4<1>, C4<1>;
+L_0x2a7c7a0 .delay (20000,20000,20000) L_0x2a7c7a0/d;
+L_0x2a7cf10/d .functor AND 1, L_0x2a7c530, L_0x2a7d190, C4<1>, C4<1>;
+L_0x2a7cf10 .delay (20000,20000,20000) L_0x2a7cf10/d;
+L_0x2a7d000/d .functor OR 1, L_0x2a7c7a0, L_0x2a7cf10, C4<0>, C4<0>;
+L_0x2a7d000 .delay (20000,20000,20000) L_0x2a7d000/d;
+v0x2884340_0 .net "S", 0 0, L_0x2a7d190; 1 drivers
+v0x2884400_0 .alias "in0", 0 0, v0x2884a60_0;
+v0x28844a0_0 .alias "in1", 0 0, v0x2884f30_0;
+v0x2884540_0 .net "nS", 0 0, L_0x2a7c6e0; 1 drivers
+v0x28845c0_0 .net "out0", 0 0, L_0x2a7c7a0; 1 drivers
+v0x2884660_0 .net "out1", 0 0, L_0x2a7cf10; 1 drivers
+v0x2884740_0 .alias "outfinal", 0 0, v0x2884b10_0;
+S_0x2883bf0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2883500;
+ .timescale -9 -12;
+L_0x2a7e090/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7e090 .delay (10000,10000,10000) L_0x2a7e090/d;
+L_0x2a7e0f0/d .functor AND 1, L_0x2a7dbe0, L_0x2a7e090, C4<1>, C4<1>;
+L_0x2a7e0f0 .delay (20000,20000,20000) L_0x2a7e0f0/d;
+L_0x2a7e1e0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a7e1e0 .delay (20000,20000,20000) L_0x2a7e1e0/d;
+L_0x2a7e280/d .functor OR 1, L_0x2a7e0f0, L_0x2a7e1e0, C4<0>, C4<0>;
+L_0x2a7e280 .delay (20000,20000,20000) L_0x2a7e280/d;
+v0x2883ce0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2883d80_0 .net "in0", 0 0, L_0x2a7dbe0; 1 drivers
+v0x2883e20_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2883ec0_0 .net "nS", 0 0, L_0x2a7e090; 1 drivers
+v0x2883f40_0 .net "out0", 0 0, L_0x2a7e0f0; 1 drivers
+v0x2883fe0_0 .net "out1", 0 0, L_0x2a7e1e0; 1 drivers
+v0x28840c0_0 .net "outfinal", 0 0, L_0x2a7e280; 1 drivers
+S_0x2883670 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2883500;
+ .timescale -9 -12;
+L_0x2a7def0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7def0 .delay (10000,10000,10000) L_0x2a7def0/d;
+L_0x2a7e020/d .functor AND 1, L_0x2a7e490, L_0x2a7def0, C4<1>, C4<1>;
+L_0x2a7e020 .delay (20000,20000,20000) L_0x2a7e020/d;
+L_0x2a79b80/d .functor AND 1, L_0x2a7e530, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a79b80 .delay (20000,20000,20000) L_0x2a79b80/d;
+L_0x2a7e950/d .functor OR 1, L_0x2a7e020, L_0x2a79b80, C4<0>, C4<0>;
+L_0x2a7e950 .delay (20000,20000,20000) L_0x2a7e950/d;
+v0x2883760_0 .alias "S", 0 0, v0x289f760_0;
+v0x28837e0_0 .net "in0", 0 0, L_0x2a7e490; 1 drivers
+v0x2883880_0 .net "in1", 0 0, L_0x2a7e530; 1 drivers
+v0x2883920_0 .net "nS", 0 0, L_0x2a7def0; 1 drivers
+v0x28839d0_0 .net "out0", 0 0, L_0x2a7e020; 1 drivers
+v0x2883a70_0 .net "out1", 0 0, L_0x2a79b80; 1 drivers
+v0x2883b50_0 .net "outfinal", 0 0, L_0x2a7e950; 1 drivers
+S_0x2881660 .scope generate, "sltbits[15]" "sltbits[15]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2881078 .param/l "i" 3 332, +C4<01111>;
+S_0x28823c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2881660;
+ .timescale -9 -12;
+L_0x2a7e620/d .functor NOT 1, L_0x2a7ecc0, C4<0>, C4<0>, C4<0>;
+L_0x2a7e620 .delay (10000,10000,10000) L_0x2a7e620/d;
+L_0x2a7f3e0/d .functor NOT 1, L_0x2a7f4a0, C4<0>, C4<0>, C4<0>;
+L_0x2a7f3e0 .delay (10000,10000,10000) L_0x2a7f3e0/d;
+L_0x2a7f540/d .functor AND 1, L_0x2a7f680, L_0x2a7f3e0, C4<1>, C4<1>;
+L_0x2a7f540 .delay (20000,20000,20000) L_0x2a7f540/d;
+L_0x2a7f720/d .functor XOR 1, L_0x2a7ec20, L_0x2a7f170, C4<0>, C4<0>;
+L_0x2a7f720 .delay (40000,40000,40000) L_0x2a7f720/d;
+L_0x2a7f810/d .functor XOR 1, L_0x2a7f720, L_0x2a7edf0, C4<0>, C4<0>;
+L_0x2a7f810 .delay (40000,40000,40000) L_0x2a7f810/d;
+L_0x2a7f930/d .functor AND 1, L_0x2a7ec20, L_0x2a7f170, C4<1>, C4<1>;
+L_0x2a7f930 .delay (20000,20000,20000) L_0x2a7f930/d;
+L_0x2a7fad0/d .functor AND 1, L_0x2a7f720, L_0x2a7edf0, C4<1>, C4<1>;
+L_0x2a7fad0 .delay (20000,20000,20000) L_0x2a7fad0/d;
+L_0x2a7fbc0/d .functor OR 1, L_0x2a7f930, L_0x2a7fad0, C4<0>, C4<0>;
+L_0x2a7fbc0 .delay (20000,20000,20000) L_0x2a7fbc0/d;
+v0x2882a40_0 .net "A", 0 0, L_0x2a7ec20; 1 drivers
+v0x2882b00_0 .net "AandB", 0 0, L_0x2a7f930; 1 drivers
+v0x2882ba0_0 .net "AddSubSLTSum", 0 0, L_0x2a7f810; 1 drivers
+v0x2882c40_0 .net "AxorB", 0 0, L_0x2a7f720; 1 drivers
+v0x2882cc0_0 .net "B", 0 0, L_0x2a7ecc0; 1 drivers
+v0x2882d70_0 .net "BornB", 0 0, L_0x2a7f170; 1 drivers
+v0x2882e30_0 .net "CINandAxorB", 0 0, L_0x2a7fad0; 1 drivers
+v0x2882eb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2882f80_0 .net *"_s3", 0 0, L_0x2a7f4a0; 1 drivers
+v0x2883000_0 .net *"_s5", 0 0, L_0x2a7f680; 1 drivers
+v0x2883100_0 .net "carryin", 0 0, L_0x2a7edf0; 1 drivers
+v0x28831a0_0 .net "carryout", 0 0, L_0x2a7fbc0; 1 drivers
+v0x28832b0_0 .net "nB", 0 0, L_0x2a7e620; 1 drivers
+v0x2883360_0 .net "nCmd2", 0 0, L_0x2a7f3e0; 1 drivers
+v0x2883460_0 .net "subtract", 0 0, L_0x2a7f540; 1 drivers
+L_0x2a7f340 .part v0x2960210_0, 0, 1;
+L_0x2a7f4a0 .part v0x2960210_0, 2, 1;
+L_0x2a7f680 .part v0x2960210_0, 0, 1;
+S_0x28824b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28823c0;
+ .timescale -9 -12;
+L_0x2a7e7f0/d .functor NOT 1, L_0x2a7f340, C4<0>, C4<0>, C4<0>;
+L_0x2a7e7f0 .delay (10000,10000,10000) L_0x2a7e7f0/d;
+L_0x2a7e8b0/d .functor AND 1, L_0x2a7ecc0, L_0x2a7e7f0, C4<1>, C4<1>;
+L_0x2a7e8b0 .delay (20000,20000,20000) L_0x2a7e8b0/d;
+L_0x2a7f060/d .functor AND 1, L_0x2a7e620, L_0x2a7f340, C4<1>, C4<1>;
+L_0x2a7f060 .delay (20000,20000,20000) L_0x2a7f060/d;
+L_0x2a7f170/d .functor OR 1, L_0x2a7e8b0, L_0x2a7f060, C4<0>, C4<0>;
+L_0x2a7f170 .delay (20000,20000,20000) L_0x2a7f170/d;
+v0x28825a0_0 .net "S", 0 0, L_0x2a7f340; 1 drivers
+v0x2882660_0 .alias "in0", 0 0, v0x2882cc0_0;
+v0x2882700_0 .alias "in1", 0 0, v0x28832b0_0;
+v0x28827a0_0 .net "nS", 0 0, L_0x2a7e7f0; 1 drivers
+v0x2882820_0 .net "out0", 0 0, L_0x2a7e8b0; 1 drivers
+v0x28828c0_0 .net "out1", 0 0, L_0x2a7f060; 1 drivers
+v0x28829a0_0 .alias "outfinal", 0 0, v0x2882d70_0;
+S_0x2881ed0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2881660;
+ .timescale -9 -12;
+L_0x2a7ee90/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7ee90 .delay (10000,10000,10000) L_0x2a7ee90/d;
+L_0x2a7ef30/d .functor AND 1, L_0x2a806e0, L_0x2a7ee90, C4<1>, C4<1>;
+L_0x2a7ef30 .delay (20000,20000,20000) L_0x2a7ef30/d;
+L_0x2a80460/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a80460 .delay (20000,20000,20000) L_0x2a80460/d;
+L_0x2a80500/d .functor OR 1, L_0x2a7ef30, L_0x2a80460, C4<0>, C4<0>;
+L_0x2a80500 .delay (20000,20000,20000) L_0x2a80500/d;
+v0x2881fc0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2882040_0 .net "in0", 0 0, L_0x2a806e0; 1 drivers
+v0x28820c0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2882140_0 .net "nS", 0 0, L_0x2a7ee90; 1 drivers
+v0x28821c0_0 .net "out0", 0 0, L_0x2a7ef30; 1 drivers
+v0x2882240_0 .net "out1", 0 0, L_0x2a80460; 1 drivers
+v0x2882320_0 .net "outfinal", 0 0, L_0x2a80500; 1 drivers
+S_0x28817d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2881660;
+ .timescale -9 -12;
+L_0x2a7ff90/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7ff90 .delay (10000,10000,10000) L_0x2a7ff90/d;
+L_0x2a800a0/d .functor AND 1, L_0x2a80d90, L_0x2a7ff90, C4<1>, C4<1>;
+L_0x2a800a0 .delay (20000,20000,20000) L_0x2a800a0/d;
+L_0x2a801b0/d .functor AND 1, L_0x2a807d0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a801b0 .delay (20000,20000,20000) L_0x2a801b0/d;
+L_0x2a80250/d .functor OR 1, L_0x2a800a0, L_0x2a801b0, C4<0>, C4<0>;
+L_0x2a80250 .delay (20000,20000,20000) L_0x2a80250/d;
+v0x28818c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2873440_0 .net "in0", 0 0, L_0x2a80d90; 1 drivers
+v0x28734e0_0 .net "in1", 0 0, L_0x2a807d0; 1 drivers
+v0x2873580_0 .net "nS", 0 0, L_0x2a7ff90; 1 drivers
+v0x2881d50_0 .net "out0", 0 0, L_0x2a800a0; 1 drivers
+v0x2881dd0_0 .net "out1", 0 0, L_0x2a801b0; 1 drivers
+v0x2881e50_0 .net "outfinal", 0 0, L_0x2a80250; 1 drivers
+S_0x287f9e0 .scope generate, "sltbits[16]" "sltbits[16]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x287f3f8 .param/l "i" 3 332, +C4<010000>;
+S_0x2880640 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287f9e0;
+ .timescale -9 -12;
+L_0x2a808c0/d .functor NOT 1, L_0x2a810b0, C4<0>, C4<0>, C4<0>;
+L_0x2a808c0 .delay (10000,10000,10000) L_0x2a808c0/d;
+L_0x2a81620/d .functor NOT 1, L_0x2a816c0, C4<0>, C4<0>, C4<0>;
+L_0x2a81620 .delay (10000,10000,10000) L_0x2a81620/d;
+L_0x2a81760/d .functor AND 1, L_0x2a818a0, L_0x2a81620, C4<1>, C4<1>;
+L_0x2a81760 .delay (20000,20000,20000) L_0x2a81760/d;
+L_0x2a81940/d .functor XOR 1, L_0x2a81010, L_0x2a813f0, C4<0>, C4<0>;
+L_0x2a81940 .delay (40000,40000,40000) L_0x2a81940/d;
+L_0x2a81a30/d .functor XOR 1, L_0x2a81940, L_0x2a811e0, C4<0>, C4<0>;
+L_0x2a81a30 .delay (40000,40000,40000) L_0x2a81a30/d;
+L_0x2a81b20/d .functor AND 1, L_0x2a81010, L_0x2a813f0, C4<1>, C4<1>;
+L_0x2a81b20 .delay (20000,20000,20000) L_0x2a81b20/d;
+L_0x2a81cc0/d .functor AND 1, L_0x2a81940, L_0x2a811e0, C4<1>, C4<1>;
+L_0x2a81cc0 .delay (20000,20000,20000) L_0x2a81cc0/d;
+L_0x2a81db0/d .functor OR 1, L_0x2a81b20, L_0x2a81cc0, C4<0>, C4<0>;
+L_0x2a81db0 .delay (20000,20000,20000) L_0x2a81db0/d;
+v0x2880cc0_0 .net "A", 0 0, L_0x2a81010; 1 drivers
+v0x2880d80_0 .net "AandB", 0 0, L_0x2a81b20; 1 drivers
+v0x2880e20_0 .net "AddSubSLTSum", 0 0, L_0x2a81a30; 1 drivers
+v0x2880ec0_0 .net "AxorB", 0 0, L_0x2a81940; 1 drivers
+v0x2880f40_0 .net "B", 0 0, L_0x2a810b0; 1 drivers
+v0x2880ff0_0 .net "BornB", 0 0, L_0x2a813f0; 1 drivers
+v0x28810b0_0 .net "CINandAxorB", 0 0, L_0x2a81cc0; 1 drivers
+v0x2881130_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28811b0_0 .net *"_s3", 0 0, L_0x2a816c0; 1 drivers
+v0x2881230_0 .net *"_s5", 0 0, L_0x2a818a0; 1 drivers
+v0x28812d0_0 .net "carryin", 0 0, L_0x2a811e0; 1 drivers
+v0x2881370_0 .net "carryout", 0 0, L_0x2a81db0; 1 drivers
+v0x2881410_0 .net "nB", 0 0, L_0x2a808c0; 1 drivers
+v0x28814c0_0 .net "nCmd2", 0 0, L_0x2a81620; 1 drivers
+v0x28815c0_0 .net "subtract", 0 0, L_0x2a81760; 1 drivers
+L_0x2a81580 .part v0x2960210_0, 0, 1;
+L_0x2a816c0 .part v0x2960210_0, 2, 1;
+L_0x2a818a0 .part v0x2960210_0, 0, 1;
+S_0x2880730 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2880640;
+ .timescale -9 -12;
+L_0x2a80a90/d .functor NOT 1, L_0x2a81580, C4<0>, C4<0>, C4<0>;
+L_0x2a80a90 .delay (10000,10000,10000) L_0x2a80a90/d;
+L_0x2a80b50/d .functor AND 1, L_0x2a810b0, L_0x2a80a90, C4<1>, C4<1>;
+L_0x2a80b50 .delay (20000,20000,20000) L_0x2a80b50/d;
+L_0x2a80c60/d .functor AND 1, L_0x2a808c0, L_0x2a81580, C4<1>, C4<1>;
+L_0x2a80c60 .delay (20000,20000,20000) L_0x2a80c60/d;
+L_0x2a813f0/d .functor OR 1, L_0x2a80b50, L_0x2a80c60, C4<0>, C4<0>;
+L_0x2a813f0 .delay (20000,20000,20000) L_0x2a813f0/d;
+v0x2880820_0 .net "S", 0 0, L_0x2a81580; 1 drivers
+v0x28808e0_0 .alias "in0", 0 0, v0x2880f40_0;
+v0x2880980_0 .alias "in1", 0 0, v0x2881410_0;
+v0x2880a20_0 .net "nS", 0 0, L_0x2a80a90; 1 drivers
+v0x2880aa0_0 .net "out0", 0 0, L_0x2a80b50; 1 drivers
+v0x2880b40_0 .net "out1", 0 0, L_0x2a80c60; 1 drivers
+v0x2880c20_0 .alias "outfinal", 0 0, v0x2880ff0_0;
+S_0x28800d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287f9e0;
+ .timescale -9 -12;
+L_0x2a81280/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a81280 .delay (10000,10000,10000) L_0x2a81280/d;
+L_0x2a71510/d .functor AND 1, L_0x2a82000, L_0x2a81280, C4<1>, C4<1>;
+L_0x2a71510 .delay (20000,20000,20000) L_0x2a71510/d;
+L_0x2a715e0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a715e0 .delay (20000,20000,20000) L_0x2a715e0/d;
+L_0x2a71680/d .functor OR 1, L_0x2a71510, L_0x2a715e0, C4<0>, C4<0>;
+L_0x2a71680 .delay (20000,20000,20000) L_0x2a71680/d;
+v0x28801c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2880260_0 .net "in0", 0 0, L_0x2a82000; 1 drivers
+v0x2880300_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28803a0_0 .net "nS", 0 0, L_0x2a81280; 1 drivers
+v0x2880420_0 .net "out0", 0 0, L_0x2a71510; 1 drivers
+v0x28804c0_0 .net "out1", 0 0, L_0x2a715e0; 1 drivers
+v0x28805a0_0 .net "outfinal", 0 0, L_0x2a71680; 1 drivers
+S_0x287fb50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287f9e0;
+ .timescale -9 -12;
+L_0x2a7dd60/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a7dd60 .delay (10000,10000,10000) L_0x2a7dd60/d;
+L_0x2a7de50/d .functor AND 1, L_0x2a82ab0, L_0x2a7dd60, C4<1>, C4<1>;
+L_0x2a7de50 .delay (20000,20000,20000) L_0x2a7de50/d;
+L_0x2a83070/d .functor AND 1, L_0x2a82ba0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a83070 .delay (20000,20000,20000) L_0x2a83070/d;
+L_0x2a83110/d .functor OR 1, L_0x2a7de50, L_0x2a83070, C4<0>, C4<0>;
+L_0x2a83110 .delay (20000,20000,20000) L_0x2a83110/d;
+v0x287fc40_0 .alias "S", 0 0, v0x289f760_0;
+v0x287fcc0_0 .net "in0", 0 0, L_0x2a82ab0; 1 drivers
+v0x287fd60_0 .net "in1", 0 0, L_0x2a82ba0; 1 drivers
+v0x287fe00_0 .net "nS", 0 0, L_0x2a7dd60; 1 drivers
+v0x287feb0_0 .net "out0", 0 0, L_0x2a7de50; 1 drivers
+v0x287ff50_0 .net "out1", 0 0, L_0x2a83070; 1 drivers
+v0x2880030_0 .net "outfinal", 0 0, L_0x2a83110; 1 drivers
+S_0x287dd60 .scope generate, "sltbits[17]" "sltbits[17]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x287d778 .param/l "i" 3 332, +C4<010001>;
+S_0x287e9c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287dd60;
+ .timescale -9 -12;
+L_0x2a82c90/d .functor NOT 1, L_0x2a83480, C4<0>, C4<0>, C4<0>;
+L_0x2a82c90 .delay (10000,10000,10000) L_0x2a82c90/d;
+L_0x2a83bd0/d .functor NOT 1, L_0x2a83c90, C4<0>, C4<0>, C4<0>;
+L_0x2a83bd0 .delay (10000,10000,10000) L_0x2a83bd0/d;
+L_0x2a83d30/d .functor AND 1, L_0x2a83e70, L_0x2a83bd0, C4<1>, C4<1>;
+L_0x2a83d30 .delay (20000,20000,20000) L_0x2a83d30/d;
+L_0x2a83f10/d .functor XOR 1, L_0x2a833e0, L_0x2a83980, C4<0>, C4<0>;
+L_0x2a83f10 .delay (40000,40000,40000) L_0x2a83f10/d;
+L_0x2a84000/d .functor XOR 1, L_0x2a83f10, L_0x2a835b0, C4<0>, C4<0>;
+L_0x2a84000 .delay (40000,40000,40000) L_0x2a84000/d;
+L_0x2a84120/d .functor AND 1, L_0x2a833e0, L_0x2a83980, C4<1>, C4<1>;
+L_0x2a84120 .delay (20000,20000,20000) L_0x2a84120/d;
+L_0x2a842c0/d .functor AND 1, L_0x2a83f10, L_0x2a835b0, C4<1>, C4<1>;
+L_0x2a842c0 .delay (20000,20000,20000) L_0x2a842c0/d;
+L_0x2a843b0/d .functor OR 1, L_0x2a84120, L_0x2a842c0, C4<0>, C4<0>;
+L_0x2a843b0 .delay (20000,20000,20000) L_0x2a843b0/d;
+v0x287f040_0 .net "A", 0 0, L_0x2a833e0; 1 drivers
+v0x287f100_0 .net "AandB", 0 0, L_0x2a84120; 1 drivers
+v0x287f1a0_0 .net "AddSubSLTSum", 0 0, L_0x2a84000; 1 drivers
+v0x287f240_0 .net "AxorB", 0 0, L_0x2a83f10; 1 drivers
+v0x287f2c0_0 .net "B", 0 0, L_0x2a83480; 1 drivers
+v0x287f370_0 .net "BornB", 0 0, L_0x2a83980; 1 drivers
+v0x287f430_0 .net "CINandAxorB", 0 0, L_0x2a842c0; 1 drivers
+v0x287f4b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x287f530_0 .net *"_s3", 0 0, L_0x2a83c90; 1 drivers
+v0x287f5b0_0 .net *"_s5", 0 0, L_0x2a83e70; 1 drivers
+v0x287f650_0 .net "carryin", 0 0, L_0x2a835b0; 1 drivers
+v0x287f6f0_0 .net "carryout", 0 0, L_0x2a843b0; 1 drivers
+v0x287f790_0 .net "nB", 0 0, L_0x2a82c90; 1 drivers
+v0x287f840_0 .net "nCmd2", 0 0, L_0x2a83bd0; 1 drivers
+v0x287f940_0 .net "subtract", 0 0, L_0x2a83d30; 1 drivers
+L_0x2a83b30 .part v0x2960210_0, 0, 1;
+L_0x2a83c90 .part v0x2960210_0, 2, 1;
+L_0x2a83e70 .part v0x2960210_0, 0, 1;
+S_0x287eab0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x287e9c0;
+ .timescale -9 -12;
+L_0x2a82e60/d .functor NOT 1, L_0x2a83b30, C4<0>, C4<0>, C4<0>;
+L_0x2a82e60 .delay (10000,10000,10000) L_0x2a82e60/d;
+L_0x2a82f20/d .functor AND 1, L_0x2a83480, L_0x2a82e60, C4<1>, C4<1>;
+L_0x2a82f20 .delay (20000,20000,20000) L_0x2a82f20/d;
+L_0x2a838d0/d .functor AND 1, L_0x2a82c90, L_0x2a83b30, C4<1>, C4<1>;
+L_0x2a838d0 .delay (20000,20000,20000) L_0x2a838d0/d;
+L_0x2a83980/d .functor OR 1, L_0x2a82f20, L_0x2a838d0, C4<0>, C4<0>;
+L_0x2a83980 .delay (20000,20000,20000) L_0x2a83980/d;
+v0x287eba0_0 .net "S", 0 0, L_0x2a83b30; 1 drivers
+v0x287ec60_0 .alias "in0", 0 0, v0x287f2c0_0;
+v0x287ed00_0 .alias "in1", 0 0, v0x287f790_0;
+v0x287eda0_0 .net "nS", 0 0, L_0x2a82e60; 1 drivers
+v0x287ee20_0 .net "out0", 0 0, L_0x2a82f20; 1 drivers
+v0x287eec0_0 .net "out1", 0 0, L_0x2a838d0; 1 drivers
+v0x287efa0_0 .alias "outfinal", 0 0, v0x287f370_0;
+S_0x287e450 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287dd60;
+ .timescale -9 -12;
+L_0x2a83650/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a83650 .delay (10000,10000,10000) L_0x2a83650/d;
+L_0x2a836d0/d .functor AND 1, L_0x2a60280, L_0x2a83650, C4<1>, C4<1>;
+L_0x2a836d0 .delay (20000,20000,20000) L_0x2a836d0/d;
+L_0x2a837e0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a837e0 .delay (20000,20000,20000) L_0x2a837e0/d;
+L_0x2a600a0/d .functor OR 1, L_0x2a836d0, L_0x2a837e0, C4<0>, C4<0>;
+L_0x2a600a0 .delay (20000,20000,20000) L_0x2a600a0/d;
+v0x287e540_0 .alias "S", 0 0, v0x289f760_0;
+v0x287e5e0_0 .net "in0", 0 0, L_0x2a60280; 1 drivers
+v0x287e680_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x287e720_0 .net "nS", 0 0, L_0x2a83650; 1 drivers
+v0x287e7a0_0 .net "out0", 0 0, L_0x2a836d0; 1 drivers
+v0x287e840_0 .net "out1", 0 0, L_0x2a837e0; 1 drivers
+v0x287e920_0 .net "outfinal", 0 0, L_0x2a600a0; 1 drivers
+S_0x287ded0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287dd60;
+ .timescale -9 -12;
+L_0x2a60400/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a60400 .delay (10000,10000,10000) L_0x2a60400/d;
+L_0x2a60530/d .functor AND 1, L_0x2a84790, L_0x2a60400, C4<1>, C4<1>;
+L_0x2a60530 .delay (20000,20000,20000) L_0x2a60530/d;
+L_0x2a60640/d .functor AND 1, L_0x2a84880, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a60640 .delay (20000,20000,20000) L_0x2a60640/d;
+L_0x2a606e0/d .functor OR 1, L_0x2a60530, L_0x2a60640, C4<0>, C4<0>;
+L_0x2a606e0 .delay (20000,20000,20000) L_0x2a606e0/d;
+v0x287dfc0_0 .alias "S", 0 0, v0x289f760_0;
+v0x287e040_0 .net "in0", 0 0, L_0x2a84790; 1 drivers
+v0x287e0e0_0 .net "in1", 0 0, L_0x2a84880; 1 drivers
+v0x287e180_0 .net "nS", 0 0, L_0x2a60400; 1 drivers
+v0x287e230_0 .net "out0", 0 0, L_0x2a60530; 1 drivers
+v0x287e2d0_0 .net "out1", 0 0, L_0x2a60640; 1 drivers
+v0x287e3b0_0 .net "outfinal", 0 0, L_0x2a606e0; 1 drivers
+S_0x287c0e0 .scope generate, "sltbits[18]" "sltbits[18]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x287baf8 .param/l "i" 3 332, +C4<010010>;
+S_0x287cd40 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287c0e0;
+ .timescale -9 -12;
+L_0x2a84970/d .functor NOT 1, L_0x2a85f40, C4<0>, C4<0>, C4<0>;
+L_0x2a84970 .delay (10000,10000,10000) L_0x2a84970/d;
+L_0x2a86600/d .functor NOT 1, L_0x2a866c0, C4<0>, C4<0>, C4<0>;
+L_0x2a86600 .delay (10000,10000,10000) L_0x2a86600/d;
+L_0x2a86760/d .functor AND 1, L_0x2a868a0, L_0x2a86600, C4<1>, C4<1>;
+L_0x2a86760 .delay (20000,20000,20000) L_0x2a86760/d;
+L_0x2a86940/d .functor XOR 1, L_0x2a85ea0, L_0x2a86390, C4<0>, C4<0>;
+L_0x2a86940 .delay (40000,40000,40000) L_0x2a86940/d;
+L_0x2a86a30/d .functor XOR 1, L_0x2a86940, L_0x2a86070, C4<0>, C4<0>;
+L_0x2a86a30 .delay (40000,40000,40000) L_0x2a86a30/d;
+L_0x2a86b20/d .functor AND 1, L_0x2a85ea0, L_0x2a86390, C4<1>, C4<1>;
+L_0x2a86b20 .delay (20000,20000,20000) L_0x2a86b20/d;
+L_0x2a86c90/d .functor AND 1, L_0x2a86940, L_0x2a86070, C4<1>, C4<1>;
+L_0x2a86c90 .delay (20000,20000,20000) L_0x2a86c90/d;
+L_0x2a86d80/d .functor OR 1, L_0x2a86b20, L_0x2a86c90, C4<0>, C4<0>;
+L_0x2a86d80 .delay (20000,20000,20000) L_0x2a86d80/d;
+v0x287d3c0_0 .net "A", 0 0, L_0x2a85ea0; 1 drivers
+v0x287d480_0 .net "AandB", 0 0, L_0x2a86b20; 1 drivers
+v0x287d520_0 .net "AddSubSLTSum", 0 0, L_0x2a86a30; 1 drivers
+v0x287d5c0_0 .net "AxorB", 0 0, L_0x2a86940; 1 drivers
+v0x287d640_0 .net "B", 0 0, L_0x2a85f40; 1 drivers
+v0x287d6f0_0 .net "BornB", 0 0, L_0x2a86390; 1 drivers
+v0x287d7b0_0 .net "CINandAxorB", 0 0, L_0x2a86c90; 1 drivers
+v0x287d830_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x287d8b0_0 .net *"_s3", 0 0, L_0x2a866c0; 1 drivers
+v0x287d930_0 .net *"_s5", 0 0, L_0x2a868a0; 1 drivers
+v0x287d9d0_0 .net "carryin", 0 0, L_0x2a86070; 1 drivers
+v0x287da70_0 .net "carryout", 0 0, L_0x2a86d80; 1 drivers
+v0x287db10_0 .net "nB", 0 0, L_0x2a84970; 1 drivers
+v0x287dbc0_0 .net "nCmd2", 0 0, L_0x2a86600; 1 drivers
+v0x287dcc0_0 .net "subtract", 0 0, L_0x2a86760; 1 drivers
+L_0x2a86560 .part v0x2960210_0, 0, 1;
+L_0x2a866c0 .part v0x2960210_0, 2, 1;
+L_0x2a868a0 .part v0x2960210_0, 0, 1;
+S_0x287ce30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x287cd40;
+ .timescale -9 -12;
+L_0x2a84b40/d .functor NOT 1, L_0x2a86560, C4<0>, C4<0>, C4<0>;
+L_0x2a84b40 .delay (10000,10000,10000) L_0x2a84b40/d;
+L_0x2a84c00/d .functor AND 1, L_0x2a85f40, L_0x2a84b40, C4<1>, C4<1>;
+L_0x2a84c00 .delay (20000,20000,20000) L_0x2a84c00/d;
+L_0x2a862a0/d .functor AND 1, L_0x2a84970, L_0x2a86560, C4<1>, C4<1>;
+L_0x2a862a0 .delay (20000,20000,20000) L_0x2a862a0/d;
+L_0x2a86390/d .functor OR 1, L_0x2a84c00, L_0x2a862a0, C4<0>, C4<0>;
+L_0x2a86390 .delay (20000,20000,20000) L_0x2a86390/d;
+v0x287cf20_0 .net "S", 0 0, L_0x2a86560; 1 drivers
+v0x287cfe0_0 .alias "in0", 0 0, v0x287d640_0;
+v0x287d080_0 .alias "in1", 0 0, v0x287db10_0;
+v0x287d120_0 .net "nS", 0 0, L_0x2a84b40; 1 drivers
+v0x287d1a0_0 .net "out0", 0 0, L_0x2a84c00; 1 drivers
+v0x287d240_0 .net "out1", 0 0, L_0x2a862a0; 1 drivers
+v0x287d320_0 .alias "outfinal", 0 0, v0x287d6f0_0;
+S_0x287c7d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287c0e0;
+ .timescale -9 -12;
+L_0x2a86110/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a86110 .delay (10000,10000,10000) L_0x2a86110/d;
+L_0x2a861b0/d .functor AND 1, L_0x2a86fd0, L_0x2a86110, C4<1>, C4<1>;
+L_0x2a861b0 .delay (20000,20000,20000) L_0x2a861b0/d;
+L_0x2a87630/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a87630 .delay (20000,20000,20000) L_0x2a87630/d;
+L_0x2a876d0/d .functor OR 1, L_0x2a861b0, L_0x2a87630, C4<0>, C4<0>;
+L_0x2a876d0 .delay (20000,20000,20000) L_0x2a876d0/d;
+v0x287c8c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x287c960_0 .net "in0", 0 0, L_0x2a86fd0; 1 drivers
+v0x287ca00_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x287caa0_0 .net "nS", 0 0, L_0x2a86110; 1 drivers
+v0x287cb20_0 .net "out0", 0 0, L_0x2a861b0; 1 drivers
+v0x287cbc0_0 .net "out1", 0 0, L_0x2a87630; 1 drivers
+v0x287cca0_0 .net "outfinal", 0 0, L_0x2a876d0; 1 drivers
+S_0x287c250 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287c0e0;
+ .timescale -9 -12;
+L_0x2a87300/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a87300 .delay (10000,10000,10000) L_0x2a87300/d;
+L_0x2a87410/d .functor AND 1, L_0x2a878b0, L_0x2a87300, C4<1>, C4<1>;
+L_0x2a87410 .delay (20000,20000,20000) L_0x2a87410/d;
+L_0x2a87520/d .functor AND 1, L_0x2a879a0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a87520 .delay (20000,20000,20000) L_0x2a87520/d;
+L_0x2a71b60/d .functor OR 1, L_0x2a87410, L_0x2a87520, C4<0>, C4<0>;
+L_0x2a71b60 .delay (20000,20000,20000) L_0x2a71b60/d;
+v0x287c340_0 .alias "S", 0 0, v0x289f760_0;
+v0x287c3c0_0 .net "in0", 0 0, L_0x2a878b0; 1 drivers
+v0x287c460_0 .net "in1", 0 0, L_0x2a879a0; 1 drivers
+v0x287c500_0 .net "nS", 0 0, L_0x2a87300; 1 drivers
+v0x287c5b0_0 .net "out0", 0 0, L_0x2a87410; 1 drivers
+v0x287c650_0 .net "out1", 0 0, L_0x2a87520; 1 drivers
+v0x287c730_0 .net "outfinal", 0 0, L_0x2a71b60; 1 drivers
+S_0x287a460 .scope generate, "sltbits[19]" "sltbits[19]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2879e78 .param/l "i" 3 332, +C4<010011>;
+S_0x287b0c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x287a460;
+ .timescale -9 -12;
+L_0x2a71ca0/d .functor NOT 1, L_0x2a88100, C4<0>, C4<0>, C4<0>;
+L_0x2a71ca0 .delay (10000,10000,10000) L_0x2a71ca0/d;
+L_0x2a887d0/d .functor NOT 1, L_0x2a88870, C4<0>, C4<0>, C4<0>;
+L_0x2a887d0 .delay (10000,10000,10000) L_0x2a887d0/d;
+L_0x2a88910/d .functor AND 1, L_0x2a88a50, L_0x2a887d0, C4<1>, C4<1>;
+L_0x2a88910 .delay (20000,20000,20000) L_0x2a88910/d;
+L_0x2a88af0/d .functor XOR 1, L_0x2a88060, L_0x2a87e70, C4<0>, C4<0>;
+L_0x2a88af0 .delay (40000,40000,40000) L_0x2a88af0/d;
+L_0x2a88be0/d .functor XOR 1, L_0x2a88af0, L_0x2a88230, C4<0>, C4<0>;
+L_0x2a88be0 .delay (40000,40000,40000) L_0x2a88be0/d;
+L_0x2a88d00/d .functor AND 1, L_0x2a88060, L_0x2a87e70, C4<1>, C4<1>;
+L_0x2a88d00 .delay (20000,20000,20000) L_0x2a88d00/d;
+L_0x2a88ea0/d .functor AND 1, L_0x2a88af0, L_0x2a88230, C4<1>, C4<1>;
+L_0x2a88ea0 .delay (20000,20000,20000) L_0x2a88ea0/d;
+L_0x2a88f90/d .functor OR 1, L_0x2a88d00, L_0x2a88ea0, C4<0>, C4<0>;
+L_0x2a88f90 .delay (20000,20000,20000) L_0x2a88f90/d;
+v0x287b740_0 .net "A", 0 0, L_0x2a88060; 1 drivers
+v0x287b800_0 .net "AandB", 0 0, L_0x2a88d00; 1 drivers
+v0x287b8a0_0 .net "AddSubSLTSum", 0 0, L_0x2a88be0; 1 drivers
+v0x287b940_0 .net "AxorB", 0 0, L_0x2a88af0; 1 drivers
+v0x287b9c0_0 .net "B", 0 0, L_0x2a88100; 1 drivers
+v0x287ba70_0 .net "BornB", 0 0, L_0x2a87e70; 1 drivers
+v0x287bb30_0 .net "CINandAxorB", 0 0, L_0x2a88ea0; 1 drivers
+v0x287bbb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x287bc30_0 .net *"_s3", 0 0, L_0x2a88870; 1 drivers
+v0x287bcb0_0 .net *"_s5", 0 0, L_0x2a88a50; 1 drivers
+v0x287bd50_0 .net "carryin", 0 0, L_0x2a88230; 1 drivers
+v0x287bdf0_0 .net "carryout", 0 0, L_0x2a88f90; 1 drivers
+v0x287be90_0 .net "nB", 0 0, L_0x2a71ca0; 1 drivers
+v0x287bf40_0 .net "nCmd2", 0 0, L_0x2a887d0; 1 drivers
+v0x287c040_0 .net "subtract", 0 0, L_0x2a88910; 1 drivers
+L_0x2a88730 .part v0x2960210_0, 0, 1;
+L_0x2a88870 .part v0x2960210_0, 2, 1;
+L_0x2a88a50 .part v0x2960210_0, 0, 1;
+S_0x287b1b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x287b0c0;
+ .timescale -9 -12;
+L_0x2a87be0/d .functor NOT 1, L_0x2a88730, C4<0>, C4<0>, C4<0>;
+L_0x2a87be0 .delay (10000,10000,10000) L_0x2a87be0/d;
+L_0x2a87ca0/d .functor AND 1, L_0x2a88100, L_0x2a87be0, C4<1>, C4<1>;
+L_0x2a87ca0 .delay (20000,20000,20000) L_0x2a87ca0/d;
+L_0x2a87db0/d .functor AND 1, L_0x2a71ca0, L_0x2a88730, C4<1>, C4<1>;
+L_0x2a87db0 .delay (20000,20000,20000) L_0x2a87db0/d;
+L_0x2a87e70/d .functor OR 1, L_0x2a87ca0, L_0x2a87db0, C4<0>, C4<0>;
+L_0x2a87e70 .delay (20000,20000,20000) L_0x2a87e70/d;
+v0x287b2a0_0 .net "S", 0 0, L_0x2a88730; 1 drivers
+v0x287b360_0 .alias "in0", 0 0, v0x287b9c0_0;
+v0x287b400_0 .alias "in1", 0 0, v0x287be90_0;
+v0x287b4a0_0 .net "nS", 0 0, L_0x2a87be0; 1 drivers
+v0x287b520_0 .net "out0", 0 0, L_0x2a87ca0; 1 drivers
+v0x287b5c0_0 .net "out1", 0 0, L_0x2a87db0; 1 drivers
+v0x287b6a0_0 .alias "outfinal", 0 0, v0x287ba70_0;
+S_0x287ab50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x287a460;
+ .timescale -9 -12;
+L_0x2a882d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a882d0 .delay (10000,10000,10000) L_0x2a882d0/d;
+L_0x2a88370/d .functor AND 1, L_0x2a89ac0, L_0x2a882d0, C4<1>, C4<1>;
+L_0x2a88370 .delay (20000,20000,20000) L_0x2a88370/d;
+L_0x2a88480/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a88480 .delay (20000,20000,20000) L_0x2a88480/d;
+L_0x2a88520/d .functor OR 1, L_0x2a88370, L_0x2a88480, C4<0>, C4<0>;
+L_0x2a88520 .delay (20000,20000,20000) L_0x2a88520/d;
+v0x287ac40_0 .alias "S", 0 0, v0x289f760_0;
+v0x287ace0_0 .net "in0", 0 0, L_0x2a89ac0; 1 drivers
+v0x287ad80_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x287ae20_0 .net "nS", 0 0, L_0x2a882d0; 1 drivers
+v0x287aea0_0 .net "out0", 0 0, L_0x2a88370; 1 drivers
+v0x287af40_0 .net "out1", 0 0, L_0x2a88480; 1 drivers
+v0x287b020_0 .net "outfinal", 0 0, L_0x2a88520; 1 drivers
+S_0x287a5d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x287a460;
+ .timescale -9 -12;
+L_0x2a89360/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a89360 .delay (10000,10000,10000) L_0x2a89360/d;
+L_0x2a89470/d .functor AND 1, L_0x2a89800, L_0x2a89360, C4<1>, C4<1>;
+L_0x2a89470 .delay (20000,20000,20000) L_0x2a89470/d;
+L_0x2a89580/d .functor AND 1, L_0x2a8a240, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a89580 .delay (20000,20000,20000) L_0x2a89580/d;
+L_0x2a89620/d .functor OR 1, L_0x2a89470, L_0x2a89580, C4<0>, C4<0>;
+L_0x2a89620 .delay (20000,20000,20000) L_0x2a89620/d;
+v0x287a6c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x287a740_0 .net "in0", 0 0, L_0x2a89800; 1 drivers
+v0x287a7e0_0 .net "in1", 0 0, L_0x2a8a240; 1 drivers
+v0x287a880_0 .net "nS", 0 0, L_0x2a89360; 1 drivers
+v0x287a930_0 .net "out0", 0 0, L_0x2a89470; 1 drivers
+v0x287a9d0_0 .net "out1", 0 0, L_0x2a89580; 1 drivers
+v0x287aab0_0 .net "outfinal", 0 0, L_0x2a89620; 1 drivers
+S_0x28787e0 .scope generate, "sltbits[20]" "sltbits[20]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x28781f8 .param/l "i" 3 332, +C4<010100>;
+S_0x2879440 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28787e0;
+ .timescale -9 -12;
+L_0x2a8a2e0/d .functor NOT 1, L_0x2a89e30, C4<0>, C4<0>, C4<0>;
+L_0x2a8a2e0 .delay (10000,10000,10000) L_0x2a8a2e0/d;
+L_0x2a8a9e0/d .functor NOT 1, L_0x2a8aaa0, C4<0>, C4<0>, C4<0>;
+L_0x2a8a9e0 .delay (10000,10000,10000) L_0x2a8a9e0/d;
+L_0x2a8ab40/d .functor AND 1, L_0x2a8ac80, L_0x2a8a9e0, C4<1>, C4<1>;
+L_0x2a8ab40 .delay (20000,20000,20000) L_0x2a8ab40/d;
+L_0x2a8ad20/d .functor XOR 1, L_0x2a89d90, L_0x2a8a770, C4<0>, C4<0>;
+L_0x2a8ad20 .delay (40000,40000,40000) L_0x2a8ad20/d;
+L_0x2a8ae10/d .functor XOR 1, L_0x2a8ad20, L_0x2a89f60, C4<0>, C4<0>;
+L_0x2a8ae10 .delay (40000,40000,40000) L_0x2a8ae10/d;
+L_0x2a8af00/d .functor AND 1, L_0x2a89d90, L_0x2a8a770, C4<1>, C4<1>;
+L_0x2a8af00 .delay (20000,20000,20000) L_0x2a8af00/d;
+L_0x2a8b070/d .functor AND 1, L_0x2a8ad20, L_0x2a89f60, C4<1>, C4<1>;
+L_0x2a8b070 .delay (20000,20000,20000) L_0x2a8b070/d;
+L_0x2a8b160/d .functor OR 1, L_0x2a8af00, L_0x2a8b070, C4<0>, C4<0>;
+L_0x2a8b160 .delay (20000,20000,20000) L_0x2a8b160/d;
+v0x2879ac0_0 .net "A", 0 0, L_0x2a89d90; 1 drivers
+v0x2879b80_0 .net "AandB", 0 0, L_0x2a8af00; 1 drivers
+v0x2879c20_0 .net "AddSubSLTSum", 0 0, L_0x2a8ae10; 1 drivers
+v0x2879cc0_0 .net "AxorB", 0 0, L_0x2a8ad20; 1 drivers
+v0x2879d40_0 .net "B", 0 0, L_0x2a89e30; 1 drivers
+v0x2879df0_0 .net "BornB", 0 0, L_0x2a8a770; 1 drivers
+v0x2879eb0_0 .net "CINandAxorB", 0 0, L_0x2a8b070; 1 drivers
+v0x2879f30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2879fb0_0 .net *"_s3", 0 0, L_0x2a8aaa0; 1 drivers
+v0x287a030_0 .net *"_s5", 0 0, L_0x2a8ac80; 1 drivers
+v0x287a0d0_0 .net "carryin", 0 0, L_0x2a89f60; 1 drivers
+v0x287a170_0 .net "carryout", 0 0, L_0x2a8b160; 1 drivers
+v0x287a210_0 .net "nB", 0 0, L_0x2a8a2e0; 1 drivers
+v0x287a2c0_0 .net "nCmd2", 0 0, L_0x2a8a9e0; 1 drivers
+v0x287a3c0_0 .net "subtract", 0 0, L_0x2a8ab40; 1 drivers
+L_0x2a8a940 .part v0x2960210_0, 0, 1;
+L_0x2a8aaa0 .part v0x2960210_0, 2, 1;
+L_0x2a8ac80 .part v0x2960210_0, 0, 1;
+S_0x2879530 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2879440;
+ .timescale -9 -12;
+L_0x2a8a490/d .functor NOT 1, L_0x2a8a940, C4<0>, C4<0>, C4<0>;
+L_0x2a8a490 .delay (10000,10000,10000) L_0x2a8a490/d;
+L_0x2a8a550/d .functor AND 1, L_0x2a89e30, L_0x2a8a490, C4<1>, C4<1>;
+L_0x2a8a550 .delay (20000,20000,20000) L_0x2a8a550/d;
+L_0x2a8a660/d .functor AND 1, L_0x2a8a2e0, L_0x2a8a940, C4<1>, C4<1>;
+L_0x2a8a660 .delay (20000,20000,20000) L_0x2a8a660/d;
+L_0x2a8a770/d .functor OR 1, L_0x2a8a550, L_0x2a8a660, C4<0>, C4<0>;
+L_0x2a8a770 .delay (20000,20000,20000) L_0x2a8a770/d;
+v0x2879620_0 .net "S", 0 0, L_0x2a8a940; 1 drivers
+v0x28796e0_0 .alias "in0", 0 0, v0x2879d40_0;
+v0x2879780_0 .alias "in1", 0 0, v0x287a210_0;
+v0x2879820_0 .net "nS", 0 0, L_0x2a8a490; 1 drivers
+v0x28798a0_0 .net "out0", 0 0, L_0x2a8a550; 1 drivers
+v0x2879940_0 .net "out1", 0 0, L_0x2a8a660; 1 drivers
+v0x2879a20_0 .alias "outfinal", 0 0, v0x2879df0_0;
+S_0x2878ed0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28787e0;
+ .timescale -9 -12;
+L_0x2a8a000/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a8a000 .delay (10000,10000,10000) L_0x2a8a000/d;
+L_0x2a8a0a0/d .functor AND 1, L_0x2a8b3b0, L_0x2a8a000, C4<1>, C4<1>;
+L_0x2a8a0a0 .delay (20000,20000,20000) L_0x2a8a0a0/d;
+L_0x2a8a1b0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a8a1b0 .delay (20000,20000,20000) L_0x2a8a1b0/d;
+L_0x2a8bab0/d .functor OR 1, L_0x2a8a0a0, L_0x2a8a1b0, C4<0>, C4<0>;
+L_0x2a8bab0 .delay (20000,20000,20000) L_0x2a8bab0/d;
+v0x2878fc0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2879060_0 .net "in0", 0 0, L_0x2a8b3b0; 1 drivers
+v0x2879100_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28791a0_0 .net "nS", 0 0, L_0x2a8a000; 1 drivers
+v0x2879220_0 .net "out0", 0 0, L_0x2a8a0a0; 1 drivers
+v0x28792c0_0 .net "out1", 0 0, L_0x2a8a1b0; 1 drivers
+v0x28793a0_0 .net "outfinal", 0 0, L_0x2a8bab0; 1 drivers
+S_0x2878950 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28787e0;
+ .timescale -9 -12;
+L_0x2a8b6f0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a8b6f0 .delay (10000,10000,10000) L_0x2a8b6f0/d;
+L_0x2a8b800/d .functor AND 1, L_0x2a8c370, L_0x2a8b6f0, C4<1>, C4<1>;
+L_0x2a8b800 .delay (20000,20000,20000) L_0x2a8b800/d;
+L_0x2a8b910/d .functor AND 1, L_0x2a8c410, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a8b910 .delay (20000,20000,20000) L_0x2a8b910/d;
+L_0x2a8b9b0/d .functor OR 1, L_0x2a8b800, L_0x2a8b910, C4<0>, C4<0>;
+L_0x2a8b9b0 .delay (20000,20000,20000) L_0x2a8b9b0/d;
+v0x2878a40_0 .alias "S", 0 0, v0x289f760_0;
+v0x2878ac0_0 .net "in0", 0 0, L_0x2a8c370; 1 drivers
+v0x2878b60_0 .net "in1", 0 0, L_0x2a8c410; 1 drivers
+v0x2878c00_0 .net "nS", 0 0, L_0x2a8b6f0; 1 drivers
+v0x2878cb0_0 .net "out0", 0 0, L_0x2a8b800; 1 drivers
+v0x2878d50_0 .net "out1", 0 0, L_0x2a8b910; 1 drivers
+v0x2878e30_0 .net "outfinal", 0 0, L_0x2a8b9b0; 1 drivers
+S_0x2876b60 .scope generate, "sltbits[21]" "sltbits[21]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2876578 .param/l "i" 3 332, +C4<010101>;
+S_0x28777c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2876b60;
+ .timescale -9 -12;
+L_0x2a8bc90/d .functor NOT 1, L_0x2a8c690, C4<0>, C4<0>, C4<0>;
+L_0x2a8bc90 .delay (10000,10000,10000) L_0x2a8bc90/d;
+L_0x2a8c310/d .functor NOT 1, L_0x2a8ccd0, C4<0>, C4<0>, C4<0>;
+L_0x2a8c310 .delay (10000,10000,10000) L_0x2a8c310/d;
+L_0x2a8cd70/d .functor AND 1, L_0x2a8ceb0, L_0x2a8c310, C4<1>, C4<1>;
+L_0x2a8cd70 .delay (20000,20000,20000) L_0x2a8cd70/d;
+L_0x2a8cf50/d .functor XOR 1, L_0x2a8c5f0, L_0x2a8c140, C4<0>, C4<0>;
+L_0x2a8cf50 .delay (40000,40000,40000) L_0x2a8cf50/d;
+L_0x2a8d040/d .functor XOR 1, L_0x2a8cf50, L_0x2a8c7c0, C4<0>, C4<0>;
+L_0x2a8d040 .delay (40000,40000,40000) L_0x2a8d040/d;
+L_0x2a8d130/d .functor AND 1, L_0x2a8c5f0, L_0x2a8c140, C4<1>, C4<1>;
+L_0x2a8d130 .delay (20000,20000,20000) L_0x2a8d130/d;
+L_0x2a8d2a0/d .functor AND 1, L_0x2a8cf50, L_0x2a8c7c0, C4<1>, C4<1>;
+L_0x2a8d2a0 .delay (20000,20000,20000) L_0x2a8d2a0/d;
+L_0x2a8d390/d .functor OR 1, L_0x2a8d130, L_0x2a8d2a0, C4<0>, C4<0>;
+L_0x2a8d390 .delay (20000,20000,20000) L_0x2a8d390/d;
+v0x2877e40_0 .net "A", 0 0, L_0x2a8c5f0; 1 drivers
+v0x2877f00_0 .net "AandB", 0 0, L_0x2a8d130; 1 drivers
+v0x2877fa0_0 .net "AddSubSLTSum", 0 0, L_0x2a8d040; 1 drivers
+v0x2878040_0 .net "AxorB", 0 0, L_0x2a8cf50; 1 drivers
+v0x28780c0_0 .net "B", 0 0, L_0x2a8c690; 1 drivers
+v0x2878170_0 .net "BornB", 0 0, L_0x2a8c140; 1 drivers
+v0x2878230_0 .net "CINandAxorB", 0 0, L_0x2a8d2a0; 1 drivers
+v0x28782b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2878330_0 .net *"_s3", 0 0, L_0x2a8ccd0; 1 drivers
+v0x28783b0_0 .net *"_s5", 0 0, L_0x2a8ceb0; 1 drivers
+v0x2878450_0 .net "carryin", 0 0, L_0x2a8c7c0; 1 drivers
+v0x28784f0_0 .net "carryout", 0 0, L_0x2a8d390; 1 drivers
+v0x2878590_0 .net "nB", 0 0, L_0x2a8bc90; 1 drivers
+v0x2878640_0 .net "nCmd2", 0 0, L_0x2a8c310; 1 drivers
+v0x2878740_0 .net "subtract", 0 0, L_0x2a8cd70; 1 drivers
+L_0x2a8cbf0 .part v0x2960210_0, 0, 1;
+L_0x2a8ccd0 .part v0x2960210_0, 2, 1;
+L_0x2a8ceb0 .part v0x2960210_0, 0, 1;
+S_0x28778b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28777c0;
+ .timescale -9 -12;
+L_0x2a8be60/d .functor NOT 1, L_0x2a8cbf0, C4<0>, C4<0>, C4<0>;
+L_0x2a8be60 .delay (10000,10000,10000) L_0x2a8be60/d;
+L_0x2a8bf20/d .functor AND 1, L_0x2a8c690, L_0x2a8be60, C4<1>, C4<1>;
+L_0x2a8bf20 .delay (20000,20000,20000) L_0x2a8bf20/d;
+L_0x2a8c030/d .functor AND 1, L_0x2a8bc90, L_0x2a8cbf0, C4<1>, C4<1>;
+L_0x2a8c030 .delay (20000,20000,20000) L_0x2a8c030/d;
+L_0x2a8c140/d .functor OR 1, L_0x2a8bf20, L_0x2a8c030, C4<0>, C4<0>;
+L_0x2a8c140 .delay (20000,20000,20000) L_0x2a8c140/d;
+v0x28779a0_0 .net "S", 0 0, L_0x2a8cbf0; 1 drivers
+v0x2877a60_0 .alias "in0", 0 0, v0x28780c0_0;
+v0x2877b00_0 .alias "in1", 0 0, v0x2878590_0;
+v0x2877ba0_0 .net "nS", 0 0, L_0x2a8be60; 1 drivers
+v0x2877c20_0 .net "out0", 0 0, L_0x2a8bf20; 1 drivers
+v0x2877cc0_0 .net "out1", 0 0, L_0x2a8c030; 1 drivers
+v0x2877da0_0 .alias "outfinal", 0 0, v0x2878170_0;
+S_0x2877250 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2876b60;
+ .timescale -9 -12;
+L_0x2a8c860/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a8c860 .delay (10000,10000,10000) L_0x2a8c860/d;
+L_0x2a8c900/d .functor AND 1, L_0x2a8de70, L_0x2a8c860, C4<1>, C4<1>;
+L_0x2a8c900 .delay (20000,20000,20000) L_0x2a8c900/d;
+L_0x2a8ca10/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a8ca10 .delay (20000,20000,20000) L_0x2a8ca10/d;
+L_0x2a8cab0/d .functor OR 1, L_0x2a8c900, L_0x2a8ca10, C4<0>, C4<0>;
+L_0x2a8cab0 .delay (20000,20000,20000) L_0x2a8cab0/d;
+v0x2877340_0 .alias "S", 0 0, v0x289f760_0;
+v0x28773e0_0 .net "in0", 0 0, L_0x2a8de70; 1 drivers
+v0x2877480_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2877520_0 .net "nS", 0 0, L_0x2a8c860; 1 drivers
+v0x28775a0_0 .net "out0", 0 0, L_0x2a8c900; 1 drivers
+v0x2877640_0 .net "out1", 0 0, L_0x2a8ca10; 1 drivers
+v0x2877720_0 .net "outfinal", 0 0, L_0x2a8cab0; 1 drivers
+S_0x2876cd0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2876b60;
+ .timescale -9 -12;
+L_0x2a8d740/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a8d740 .delay (10000,10000,10000) L_0x2a8d740/d;
+L_0x2a8d850/d .functor AND 1, L_0x2a8dbe0, L_0x2a8d740, C4<1>, C4<1>;
+L_0x2a8d850 .delay (20000,20000,20000) L_0x2a8d850/d;
+L_0x2a8d960/d .functor AND 1, L_0x2a8dcd0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a8d960 .delay (20000,20000,20000) L_0x2a8d960/d;
+L_0x2a8da00/d .functor OR 1, L_0x2a8d850, L_0x2a8d960, C4<0>, C4<0>;
+L_0x2a8da00 .delay (20000,20000,20000) L_0x2a8da00/d;
+v0x2876dc0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2876e40_0 .net "in0", 0 0, L_0x2a8dbe0; 1 drivers
+v0x2876ee0_0 .net "in1", 0 0, L_0x2a8dcd0; 1 drivers
+v0x2876f80_0 .net "nS", 0 0, L_0x2a8d740; 1 drivers
+v0x2877030_0 .net "out0", 0 0, L_0x2a8d850; 1 drivers
+v0x28770d0_0 .net "out1", 0 0, L_0x2a8d960; 1 drivers
+v0x28771b0_0 .net "outfinal", 0 0, L_0x2a8da00; 1 drivers
+S_0x2874ee0 .scope generate, "sltbits[22]" "sltbits[22]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x28748f8 .param/l "i" 3 332, +C4<010110>;
+S_0x2875b40 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2874ee0;
+ .timescale -9 -12;
+L_0x2a8e6a0/d .functor NOT 1, L_0x2a8e1e0, C4<0>, C4<0>, C4<0>;
+L_0x2a8e6a0 .delay (10000,10000,10000) L_0x2a8e6a0/d;
+L_0x2a8edc0/d .functor NOT 1, L_0x2a8ee80, C4<0>, C4<0>, C4<0>;
+L_0x2a8edc0 .delay (10000,10000,10000) L_0x2a8edc0/d;
+L_0x2a8ef20/d .functor AND 1, L_0x2a8f060, L_0x2a8edc0, C4<1>, C4<1>;
+L_0x2a8ef20 .delay (20000,20000,20000) L_0x2a8ef20/d;
+L_0x2a8f100/d .functor XOR 1, L_0x2a8e140, L_0x2a8eb50, C4<0>, C4<0>;
+L_0x2a8f100 .delay (40000,40000,40000) L_0x2a8f100/d;
+L_0x2a8f1f0/d .functor XOR 1, L_0x2a8f100, L_0x2a8e310, C4<0>, C4<0>;
+L_0x2a8f1f0 .delay (40000,40000,40000) L_0x2a8f1f0/d;
+L_0x2a8f2e0/d .functor AND 1, L_0x2a8e140, L_0x2a8eb50, C4<1>, C4<1>;
+L_0x2a8f2e0 .delay (20000,20000,20000) L_0x2a8f2e0/d;
+L_0x2a8f450/d .functor AND 1, L_0x2a8f100, L_0x2a8e310, C4<1>, C4<1>;
+L_0x2a8f450 .delay (20000,20000,20000) L_0x2a8f450/d;
+L_0x2a8f540/d .functor OR 1, L_0x2a8f2e0, L_0x2a8f450, C4<0>, C4<0>;
+L_0x2a8f540 .delay (20000,20000,20000) L_0x2a8f540/d;
+v0x28761c0_0 .net "A", 0 0, L_0x2a8e140; 1 drivers
+v0x2876280_0 .net "AandB", 0 0, L_0x2a8f2e0; 1 drivers
+v0x2876320_0 .net "AddSubSLTSum", 0 0, L_0x2a8f1f0; 1 drivers
+v0x28763c0_0 .net "AxorB", 0 0, L_0x2a8f100; 1 drivers
+v0x2876440_0 .net "B", 0 0, L_0x2a8e1e0; 1 drivers
+v0x28764f0_0 .net "BornB", 0 0, L_0x2a8eb50; 1 drivers
+v0x28765b0_0 .net "CINandAxorB", 0 0, L_0x2a8f450; 1 drivers
+v0x2876630_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28766b0_0 .net *"_s3", 0 0, L_0x2a8ee80; 1 drivers
+v0x2876730_0 .net *"_s5", 0 0, L_0x2a8f060; 1 drivers
+v0x28767d0_0 .net "carryin", 0 0, L_0x2a8e310; 1 drivers
+v0x2876870_0 .net "carryout", 0 0, L_0x2a8f540; 1 drivers
+v0x2876910_0 .net "nB", 0 0, L_0x2a8e6a0; 1 drivers
+v0x28769c0_0 .net "nCmd2", 0 0, L_0x2a8edc0; 1 drivers
+v0x2876ac0_0 .net "subtract", 0 0, L_0x2a8ef20; 1 drivers
+L_0x2a8ed20 .part v0x2960210_0, 0, 1;
+L_0x2a8ee80 .part v0x2960210_0, 2, 1;
+L_0x2a8f060 .part v0x2960210_0, 0, 1;
+S_0x2875c30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2875b40;
+ .timescale -9 -12;
+L_0x2a8e870/d .functor NOT 1, L_0x2a8ed20, C4<0>, C4<0>, C4<0>;
+L_0x2a8e870 .delay (10000,10000,10000) L_0x2a8e870/d;
+L_0x2a8e930/d .functor AND 1, L_0x2a8e1e0, L_0x2a8e870, C4<1>, C4<1>;
+L_0x2a8e930 .delay (20000,20000,20000) L_0x2a8e930/d;
+L_0x2a8ea40/d .functor AND 1, L_0x2a8e6a0, L_0x2a8ed20, C4<1>, C4<1>;
+L_0x2a8ea40 .delay (20000,20000,20000) L_0x2a8ea40/d;
+L_0x2a8eb50/d .functor OR 1, L_0x2a8e930, L_0x2a8ea40, C4<0>, C4<0>;
+L_0x2a8eb50 .delay (20000,20000,20000) L_0x2a8eb50/d;
+v0x2875d20_0 .net "S", 0 0, L_0x2a8ed20; 1 drivers
+v0x2875de0_0 .alias "in0", 0 0, v0x2876440_0;
+v0x2875e80_0 .alias "in1", 0 0, v0x2876910_0;
+v0x2875f20_0 .net "nS", 0 0, L_0x2a8e870; 1 drivers
+v0x2875fa0_0 .net "out0", 0 0, L_0x2a8e930; 1 drivers
+v0x2876040_0 .net "out1", 0 0, L_0x2a8ea40; 1 drivers
+v0x2876120_0 .alias "outfinal", 0 0, v0x28764f0_0;
+S_0x28755d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2874ee0;
+ .timescale -9 -12;
+L_0x2a8e3b0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a8e3b0 .delay (10000,10000,10000) L_0x2a8e3b0/d;
+L_0x2a8e450/d .functor AND 1, L_0x2a78680, L_0x2a8e3b0, C4<1>, C4<1>;
+L_0x2a8e450 .delay (20000,20000,20000) L_0x2a8e450/d;
+L_0x2a8e560/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a8e560 .delay (20000,20000,20000) L_0x2a8e560/d;
+L_0x2a8e600/d .functor OR 1, L_0x2a8e450, L_0x2a8e560, C4<0>, C4<0>;
+L_0x2a8e600 .delay (20000,20000,20000) L_0x2a8e600/d;
+v0x28756c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2875760_0 .net "in0", 0 0, L_0x2a78680; 1 drivers
+v0x2875800_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x28758a0_0 .net "nS", 0 0, L_0x2a8e3b0; 1 drivers
+v0x2875920_0 .net "out0", 0 0, L_0x2a8e450; 1 drivers
+v0x28759c0_0 .net "out1", 0 0, L_0x2a8e560; 1 drivers
+v0x2875aa0_0 .net "outfinal", 0 0, L_0x2a8e600; 1 drivers
+S_0x2875050 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2874ee0;
+ .timescale -9 -12;
+L_0x2a789d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a789d0 .delay (10000,10000,10000) L_0x2a789d0/d;
+L_0x2a8b580/d .functor AND 1, L_0x2a8f9b0, L_0x2a789d0, C4<1>, C4<1>;
+L_0x2a8b580 .delay (20000,20000,20000) L_0x2a8b580/d;
+L_0x2a8b690/d .functor AND 1, L_0x2a8faa0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a8b690 .delay (20000,20000,20000) L_0x2a8b690/d;
+L_0x2a8f7d0/d .functor OR 1, L_0x2a8b580, L_0x2a8b690, C4<0>, C4<0>;
+L_0x2a8f7d0 .delay (20000,20000,20000) L_0x2a8f7d0/d;
+v0x2875140_0 .alias "S", 0 0, v0x289f760_0;
+v0x28751c0_0 .net "in0", 0 0, L_0x2a8f9b0; 1 drivers
+v0x2875260_0 .net "in1", 0 0, L_0x2a8faa0; 1 drivers
+v0x2875300_0 .net "nS", 0 0, L_0x2a789d0; 1 drivers
+v0x28753b0_0 .net "out0", 0 0, L_0x2a8b580; 1 drivers
+v0x2875450_0 .net "out1", 0 0, L_0x2a8b690; 1 drivers
+v0x2875530_0 .net "outfinal", 0 0, L_0x2a8f7d0; 1 drivers
+S_0x2873160 .scope generate, "sltbits[23]" "sltbits[23]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2872b78 .param/l "i" 3 332, +C4<010111>;
+S_0x2873ec0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2873160;
+ .timescale -9 -12;
+L_0x2a8fb90/d .functor NOT 1, L_0x2a909e0, C4<0>, C4<0>, C4<0>;
+L_0x2a8fb90 .delay (10000,10000,10000) L_0x2a8fb90/d;
+L_0x2a913a0/d .functor NOT 1, L_0x2a91460, C4<0>, C4<0>, C4<0>;
+L_0x2a913a0 .delay (10000,10000,10000) L_0x2a913a0/d;
+L_0x2a91500/d .functor AND 1, L_0x2a91640, L_0x2a913a0, C4<1>, C4<1>;
+L_0x2a91500 .delay (20000,20000,20000) L_0x2a91500/d;
+L_0x2a916e0/d .functor XOR 1, L_0x2a90940, L_0x2a91130, C4<0>, C4<0>;
+L_0x2a916e0 .delay (40000,40000,40000) L_0x2a916e0/d;
+L_0x2a917d0/d .functor XOR 1, L_0x2a916e0, L_0x2a90b10, C4<0>, C4<0>;
+L_0x2a917d0 .delay (40000,40000,40000) L_0x2a917d0/d;
+L_0x2a918c0/d .functor AND 1, L_0x2a90940, L_0x2a91130, C4<1>, C4<1>;
+L_0x2a918c0 .delay (20000,20000,20000) L_0x2a918c0/d;
+L_0x2a91a30/d .functor AND 1, L_0x2a916e0, L_0x2a90b10, C4<1>, C4<1>;
+L_0x2a91a30 .delay (20000,20000,20000) L_0x2a91a30/d;
+L_0x2a91b20/d .functor OR 1, L_0x2a918c0, L_0x2a91a30, C4<0>, C4<0>;
+L_0x2a91b20 .delay (20000,20000,20000) L_0x2a91b20/d;
+v0x2874540_0 .net "A", 0 0, L_0x2a90940; 1 drivers
+v0x2874600_0 .net "AandB", 0 0, L_0x2a918c0; 1 drivers
+v0x28746a0_0 .net "AddSubSLTSum", 0 0, L_0x2a917d0; 1 drivers
+v0x2874740_0 .net "AxorB", 0 0, L_0x2a916e0; 1 drivers
+v0x28747c0_0 .net "B", 0 0, L_0x2a909e0; 1 drivers
+v0x2874870_0 .net "BornB", 0 0, L_0x2a91130; 1 drivers
+v0x2874930_0 .net "CINandAxorB", 0 0, L_0x2a91a30; 1 drivers
+v0x28749b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2874a30_0 .net *"_s3", 0 0, L_0x2a91460; 1 drivers
+v0x2874ab0_0 .net *"_s5", 0 0, L_0x2a91640; 1 drivers
+v0x2874b50_0 .net "carryin", 0 0, L_0x2a90b10; 1 drivers
+v0x2874bf0_0 .net "carryout", 0 0, L_0x2a91b20; 1 drivers
+v0x2874c90_0 .net "nB", 0 0, L_0x2a8fb90; 1 drivers
+v0x2874d40_0 .net "nCmd2", 0 0, L_0x2a913a0; 1 drivers
+v0x2874e40_0 .net "subtract", 0 0, L_0x2a91500; 1 drivers
+L_0x2a91300 .part v0x2960210_0, 0, 1;
+L_0x2a91460 .part v0x2960210_0, 2, 1;
+L_0x2a91640 .part v0x2960210_0, 0, 1;
+S_0x2873fb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2873ec0;
+ .timescale -9 -12;
+L_0x2a8fd60/d .functor NOT 1, L_0x2a91300, C4<0>, C4<0>, C4<0>;
+L_0x2a8fd60 .delay (10000,10000,10000) L_0x2a8fd60/d;
+L_0x2a8fe20/d .functor AND 1, L_0x2a909e0, L_0x2a8fd60, C4<1>, C4<1>;
+L_0x2a8fe20 .delay (20000,20000,20000) L_0x2a8fe20/d;
+L_0x2a91040/d .functor AND 1, L_0x2a8fb90, L_0x2a91300, C4<1>, C4<1>;
+L_0x2a91040 .delay (20000,20000,20000) L_0x2a91040/d;
+L_0x2a91130/d .functor OR 1, L_0x2a8fe20, L_0x2a91040, C4<0>, C4<0>;
+L_0x2a91130 .delay (20000,20000,20000) L_0x2a91130/d;
+v0x28740a0_0 .net "S", 0 0, L_0x2a91300; 1 drivers
+v0x2874160_0 .alias "in0", 0 0, v0x28747c0_0;
+v0x2874200_0 .alias "in1", 0 0, v0x2874c90_0;
+v0x28742a0_0 .net "nS", 0 0, L_0x2a8fd60; 1 drivers
+v0x2874320_0 .net "out0", 0 0, L_0x2a8fe20; 1 drivers
+v0x28743c0_0 .net "out1", 0 0, L_0x2a91040; 1 drivers
+v0x28744a0_0 .alias "outfinal", 0 0, v0x2874870_0;
+S_0x2873950 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2873160;
+ .timescale -9 -12;
+L_0x2a90bb0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a90bb0 .delay (10000,10000,10000) L_0x2a90bb0/d;
+L_0x2a90c50/d .functor AND 1, L_0x2a92630, L_0x2a90bb0, C4<1>, C4<1>;
+L_0x2a90c50 .delay (20000,20000,20000) L_0x2a90c50/d;
+L_0x2a90d60/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a90d60 .delay (20000,20000,20000) L_0x2a90d60/d;
+L_0x2a90e00/d .functor OR 1, L_0x2a90c50, L_0x2a90d60, C4<0>, C4<0>;
+L_0x2a90e00 .delay (20000,20000,20000) L_0x2a90e00/d;
+v0x2873a40_0 .alias "S", 0 0, v0x289f760_0;
+v0x2873ae0_0 .net "in0", 0 0, L_0x2a92630; 1 drivers
+v0x2873b80_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2873c20_0 .net "nS", 0 0, L_0x2a90bb0; 1 drivers
+v0x2873ca0_0 .net "out0", 0 0, L_0x2a90c50; 1 drivers
+v0x2873d40_0 .net "out1", 0 0, L_0x2a90d60; 1 drivers
+v0x2873e20_0 .net "outfinal", 0 0, L_0x2a90e00; 1 drivers
+S_0x28732d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2873160;
+ .timescale -9 -12;
+L_0x2a91ef0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a91ef0 .delay (10000,10000,10000) L_0x2a91ef0/d;
+L_0x2a92000/d .functor AND 1, L_0x2a92390, L_0x2a91ef0, C4<1>, C4<1>;
+L_0x2a92000 .delay (20000,20000,20000) L_0x2a92000/d;
+L_0x2a92110/d .functor AND 1, L_0x2a92480, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a92110 .delay (20000,20000,20000) L_0x2a92110/d;
+L_0x2a921b0/d .functor OR 1, L_0x2a92000, L_0x2a92110, C4<0>, C4<0>;
+L_0x2a921b0 .delay (20000,20000,20000) L_0x2a921b0/d;
+v0x28733c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x286c1b0_0 .net "in0", 0 0, L_0x2a92390; 1 drivers
+v0x2873650_0 .net "in1", 0 0, L_0x2a92480; 1 drivers
+v0x28736d0_0 .net "nS", 0 0, L_0x2a91ef0; 1 drivers
+v0x2873750_0 .net "out0", 0 0, L_0x2a92000; 1 drivers
+v0x28737d0_0 .net "out1", 0 0, L_0x2a92110; 1 drivers
+v0x28738b0_0 .net "outfinal", 0 0, L_0x2a921b0; 1 drivers
+S_0x28714e0 .scope generate, "sltbits[24]" "sltbits[24]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2870ef8 .param/l "i" 3 332, +C4<011000>;
+S_0x2872140 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28714e0;
+ .timescale -9 -12;
+L_0x2a92570/d .functor NOT 1, L_0x2a929a0, C4<0>, C4<0>, C4<0>;
+L_0x2a92570 .delay (10000,10000,10000) L_0x2a92570/d;
+L_0x2a93580/d .functor NOT 1, L_0x2a93640, C4<0>, C4<0>, C4<0>;
+L_0x2a93580 .delay (10000,10000,10000) L_0x2a93580/d;
+L_0x2a936e0/d .functor AND 1, L_0x2a93820, L_0x2a93580, C4<1>, C4<1>;
+L_0x2a936e0 .delay (20000,20000,20000) L_0x2a936e0/d;
+L_0x2a938c0/d .functor XOR 1, L_0x2a92900, L_0x2a93310, C4<0>, C4<0>;
+L_0x2a938c0 .delay (40000,40000,40000) L_0x2a938c0/d;
+L_0x2a939b0/d .functor XOR 1, L_0x2a938c0, L_0x2a92ad0, C4<0>, C4<0>;
+L_0x2a939b0 .delay (40000,40000,40000) L_0x2a939b0/d;
+L_0x2a93aa0/d .functor AND 1, L_0x2a92900, L_0x2a93310, C4<1>, C4<1>;
+L_0x2a93aa0 .delay (20000,20000,20000) L_0x2a93aa0/d;
+L_0x2a93c10/d .functor AND 1, L_0x2a938c0, L_0x2a92ad0, C4<1>, C4<1>;
+L_0x2a93c10 .delay (20000,20000,20000) L_0x2a93c10/d;
+L_0x2a93d00/d .functor OR 1, L_0x2a93aa0, L_0x2a93c10, C4<0>, C4<0>;
+L_0x2a93d00 .delay (20000,20000,20000) L_0x2a93d00/d;
+v0x28727c0_0 .net "A", 0 0, L_0x2a92900; 1 drivers
+v0x2872880_0 .net "AandB", 0 0, L_0x2a93aa0; 1 drivers
+v0x2872920_0 .net "AddSubSLTSum", 0 0, L_0x2a939b0; 1 drivers
+v0x28729c0_0 .net "AxorB", 0 0, L_0x2a938c0; 1 drivers
+v0x2872a40_0 .net "B", 0 0, L_0x2a929a0; 1 drivers
+v0x2872af0_0 .net "BornB", 0 0, L_0x2a93310; 1 drivers
+v0x2872bb0_0 .net "CINandAxorB", 0 0, L_0x2a93c10; 1 drivers
+v0x2872c30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2872cb0_0 .net *"_s3", 0 0, L_0x2a93640; 1 drivers
+v0x2872d30_0 .net *"_s5", 0 0, L_0x2a93820; 1 drivers
+v0x2872dd0_0 .net "carryin", 0 0, L_0x2a92ad0; 1 drivers
+v0x2872e70_0 .net "carryout", 0 0, L_0x2a93d00; 1 drivers
+v0x2872f10_0 .net "nB", 0 0, L_0x2a92570; 1 drivers
+v0x2872fc0_0 .net "nCmd2", 0 0, L_0x2a93580; 1 drivers
+v0x28730c0_0 .net "subtract", 0 0, L_0x2a936e0; 1 drivers
+L_0x2a934e0 .part v0x2960210_0, 0, 1;
+L_0x2a93640 .part v0x2960210_0, 2, 1;
+L_0x2a93820 .part v0x2960210_0, 0, 1;
+S_0x2872230 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2872140;
+ .timescale -9 -12;
+L_0x2a93030/d .functor NOT 1, L_0x2a934e0, C4<0>, C4<0>, C4<0>;
+L_0x2a93030 .delay (10000,10000,10000) L_0x2a93030/d;
+L_0x2a930f0/d .functor AND 1, L_0x2a929a0, L_0x2a93030, C4<1>, C4<1>;
+L_0x2a930f0 .delay (20000,20000,20000) L_0x2a930f0/d;
+L_0x2a93200/d .functor AND 1, L_0x2a92570, L_0x2a934e0, C4<1>, C4<1>;
+L_0x2a93200 .delay (20000,20000,20000) L_0x2a93200/d;
+L_0x2a93310/d .functor OR 1, L_0x2a930f0, L_0x2a93200, C4<0>, C4<0>;
+L_0x2a93310 .delay (20000,20000,20000) L_0x2a93310/d;
+v0x2872320_0 .net "S", 0 0, L_0x2a934e0; 1 drivers
+v0x28723e0_0 .alias "in0", 0 0, v0x2872a40_0;
+v0x2872480_0 .alias "in1", 0 0, v0x2872f10_0;
+v0x2872520_0 .net "nS", 0 0, L_0x2a93030; 1 drivers
+v0x28725a0_0 .net "out0", 0 0, L_0x2a930f0; 1 drivers
+v0x2872640_0 .net "out1", 0 0, L_0x2a93200; 1 drivers
+v0x2872720_0 .alias "outfinal", 0 0, v0x2872af0_0;
+S_0x2871bd0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28714e0;
+ .timescale -9 -12;
+L_0x2a92b70/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a92b70 .delay (10000,10000,10000) L_0x2a92b70/d;
+L_0x2a92c10/d .functor AND 1, L_0x2a93f50, L_0x2a92b70, C4<1>, C4<1>;
+L_0x2a92c10 .delay (20000,20000,20000) L_0x2a92c10/d;
+L_0x2a92d20/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a92d20 .delay (20000,20000,20000) L_0x2a92d20/d;
+L_0x2a92dc0/d .functor OR 1, L_0x2a92c10, L_0x2a92d20, C4<0>, C4<0>;
+L_0x2a92dc0 .delay (20000,20000,20000) L_0x2a92dc0/d;
+v0x2871cc0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2871d60_0 .net "in0", 0 0, L_0x2a93f50; 1 drivers
+v0x2871e00_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2871ea0_0 .net "nS", 0 0, L_0x2a92b70; 1 drivers
+v0x2871f20_0 .net "out0", 0 0, L_0x2a92c10; 1 drivers
+v0x2871fc0_0 .net "out1", 0 0, L_0x2a92d20; 1 drivers
+v0x28720a0_0 .net "outfinal", 0 0, L_0x2a92dc0; 1 drivers
+S_0x2871650 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28714e0;
+ .timescale -9 -12;
+L_0x2a92eb0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a92eb0 .delay (10000,10000,10000) L_0x2a92eb0/d;
+L_0x2a94360/d .functor AND 1, L_0x2a78800, L_0x2a92eb0, C4<1>, C4<1>;
+L_0x2a94360 .delay (20000,20000,20000) L_0x2a94360/d;
+L_0x2a94470/d .functor AND 1, L_0x2a788f0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a94470 .delay (20000,20000,20000) L_0x2a94470/d;
+L_0x2a94510/d .functor OR 1, L_0x2a94360, L_0x2a94470, C4<0>, C4<0>;
+L_0x2a94510 .delay (20000,20000,20000) L_0x2a94510/d;
+v0x2871740_0 .alias "S", 0 0, v0x289f760_0;
+v0x28717c0_0 .net "in0", 0 0, L_0x2a78800; 1 drivers
+v0x2871860_0 .net "in1", 0 0, L_0x2a788f0; 1 drivers
+v0x2871900_0 .net "nS", 0 0, L_0x2a92eb0; 1 drivers
+v0x28719b0_0 .net "out0", 0 0, L_0x2a94360; 1 drivers
+v0x2871a50_0 .net "out1", 0 0, L_0x2a94470; 1 drivers
+v0x2871b30_0 .net "outfinal", 0 0, L_0x2a94510; 1 drivers
+S_0x286f860 .scope generate, "sltbits[25]" "sltbits[25]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x286f278 .param/l "i" 3 332, +C4<011001>;
+S_0x28704c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286f860;
+ .timescale -9 -12;
+L_0x2a950b0/d .functor NOT 1, L_0x2a949f0, C4<0>, C4<0>, C4<0>;
+L_0x2a950b0 .delay (10000,10000,10000) L_0x2a950b0/d;
+L_0x2a95770/d .functor NOT 1, L_0x2a95830, C4<0>, C4<0>, C4<0>;
+L_0x2a95770 .delay (10000,10000,10000) L_0x2a95770/d;
+L_0x2a958d0/d .functor AND 1, L_0x2a95a10, L_0x2a95770, C4<1>, C4<1>;
+L_0x2a958d0 .delay (20000,20000,20000) L_0x2a958d0/d;
+L_0x2a95ab0/d .functor XOR 1, L_0x2a94950, L_0x2a95500, C4<0>, C4<0>;
+L_0x2a95ab0 .delay (40000,40000,40000) L_0x2a95ab0/d;
+L_0x2a95ba0/d .functor XOR 1, L_0x2a95ab0, L_0x2a94b20, C4<0>, C4<0>;
+L_0x2a95ba0 .delay (40000,40000,40000) L_0x2a95ba0/d;
+L_0x2a95c90/d .functor AND 1, L_0x2a94950, L_0x2a95500, C4<1>, C4<1>;
+L_0x2a95c90 .delay (20000,20000,20000) L_0x2a95c90/d;
+L_0x2a95e00/d .functor AND 1, L_0x2a95ab0, L_0x2a94b20, C4<1>, C4<1>;
+L_0x2a95e00 .delay (20000,20000,20000) L_0x2a95e00/d;
+L_0x2a95ef0/d .functor OR 1, L_0x2a95c90, L_0x2a95e00, C4<0>, C4<0>;
+L_0x2a95ef0 .delay (20000,20000,20000) L_0x2a95ef0/d;
+v0x2870b40_0 .net "A", 0 0, L_0x2a94950; 1 drivers
+v0x2870c00_0 .net "AandB", 0 0, L_0x2a95c90; 1 drivers
+v0x2870ca0_0 .net "AddSubSLTSum", 0 0, L_0x2a95ba0; 1 drivers
+v0x2870d40_0 .net "AxorB", 0 0, L_0x2a95ab0; 1 drivers
+v0x2870dc0_0 .net "B", 0 0, L_0x2a949f0; 1 drivers
+v0x2870e70_0 .net "BornB", 0 0, L_0x2a95500; 1 drivers
+v0x2870f30_0 .net "CINandAxorB", 0 0, L_0x2a95e00; 1 drivers
+v0x2870fb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2871030_0 .net *"_s3", 0 0, L_0x2a95830; 1 drivers
+v0x28710b0_0 .net *"_s5", 0 0, L_0x2a95a10; 1 drivers
+v0x2871150_0 .net "carryin", 0 0, L_0x2a94b20; 1 drivers
+v0x28711f0_0 .net "carryout", 0 0, L_0x2a95ef0; 1 drivers
+v0x2871290_0 .net "nB", 0 0, L_0x2a950b0; 1 drivers
+v0x2871340_0 .net "nCmd2", 0 0, L_0x2a95770; 1 drivers
+v0x2871440_0 .net "subtract", 0 0, L_0x2a958d0; 1 drivers
+L_0x2a956d0 .part v0x2960210_0, 0, 1;
+L_0x2a95830 .part v0x2960210_0, 2, 1;
+L_0x2a95a10 .part v0x2960210_0, 0, 1;
+S_0x28705b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28704c0;
+ .timescale -9 -12;
+L_0x2a95220/d .functor NOT 1, L_0x2a956d0, C4<0>, C4<0>, C4<0>;
+L_0x2a95220 .delay (10000,10000,10000) L_0x2a95220/d;
+L_0x2a952e0/d .functor AND 1, L_0x2a949f0, L_0x2a95220, C4<1>, C4<1>;
+L_0x2a952e0 .delay (20000,20000,20000) L_0x2a952e0/d;
+L_0x2a953f0/d .functor AND 1, L_0x2a950b0, L_0x2a956d0, C4<1>, C4<1>;
+L_0x2a953f0 .delay (20000,20000,20000) L_0x2a953f0/d;
+L_0x2a95500/d .functor OR 1, L_0x2a952e0, L_0x2a953f0, C4<0>, C4<0>;
+L_0x2a95500 .delay (20000,20000,20000) L_0x2a95500/d;
+v0x28706a0_0 .net "S", 0 0, L_0x2a956d0; 1 drivers
+v0x2870760_0 .alias "in0", 0 0, v0x2870dc0_0;
+v0x2870800_0 .alias "in1", 0 0, v0x2871290_0;
+v0x28708a0_0 .net "nS", 0 0, L_0x2a95220; 1 drivers
+v0x2870920_0 .net "out0", 0 0, L_0x2a952e0; 1 drivers
+v0x28709c0_0 .net "out1", 0 0, L_0x2a953f0; 1 drivers
+v0x2870aa0_0 .alias "outfinal", 0 0, v0x2870e70_0;
+S_0x286ff50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286f860;
+ .timescale -9 -12;
+L_0x2a94bc0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a94bc0 .delay (10000,10000,10000) L_0x2a94bc0/d;
+L_0x2a94c60/d .functor AND 1, L_0x2a94ff0, L_0x2a94bc0, C4<1>, C4<1>;
+L_0x2a94c60 .delay (20000,20000,20000) L_0x2a94c60/d;
+L_0x2a94d70/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a94d70 .delay (20000,20000,20000) L_0x2a94d70/d;
+L_0x2a94e10/d .functor OR 1, L_0x2a94c60, L_0x2a94d70, C4<0>, C4<0>;
+L_0x2a94e10 .delay (20000,20000,20000) L_0x2a94e10/d;
+v0x2870040_0 .alias "S", 0 0, v0x289f760_0;
+v0x28700e0_0 .net "in0", 0 0, L_0x2a94ff0; 1 drivers
+v0x2870180_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2870220_0 .net "nS", 0 0, L_0x2a94bc0; 1 drivers
+v0x28702a0_0 .net "out0", 0 0, L_0x2a94c60; 1 drivers
+v0x2870340_0 .net "out1", 0 0, L_0x2a94d70; 1 drivers
+v0x2870420_0 .net "outfinal", 0 0, L_0x2a94e10; 1 drivers
+S_0x286f9d0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286f860;
+ .timescale -9 -12;
+L_0x2a962c0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a962c0 .delay (10000,10000,10000) L_0x2a962c0/d;
+L_0x2a963b0/d .functor AND 1, L_0x2a96740, L_0x2a962c0, C4<1>, C4<1>;
+L_0x2a963b0 .delay (20000,20000,20000) L_0x2a963b0/d;
+L_0x2a964c0/d .functor AND 1, L_0x2a96830, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a964c0 .delay (20000,20000,20000) L_0x2a964c0/d;
+L_0x2a96560/d .functor OR 1, L_0x2a963b0, L_0x2a964c0, C4<0>, C4<0>;
+L_0x2a96560 .delay (20000,20000,20000) L_0x2a96560/d;
+v0x286fac0_0 .alias "S", 0 0, v0x289f760_0;
+v0x286fb40_0 .net "in0", 0 0, L_0x2a96740; 1 drivers
+v0x286fbe0_0 .net "in1", 0 0, L_0x2a96830; 1 drivers
+v0x286fc80_0 .net "nS", 0 0, L_0x2a962c0; 1 drivers
+v0x286fd30_0 .net "out0", 0 0, L_0x2a963b0; 1 drivers
+v0x286fdd0_0 .net "out1", 0 0, L_0x2a964c0; 1 drivers
+v0x286feb0_0 .net "outfinal", 0 0, L_0x2a96560; 1 drivers
+S_0x286dbe0 .scope generate, "sltbits[26]" "sltbits[26]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x286d5f8 .param/l "i" 3 332, +C4<011010>;
+S_0x286e840 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286dbe0;
+ .timescale -9 -12;
+L_0x2a96920/d .functor NOT 1, L_0x2a96d80, C4<0>, C4<0>, C4<0>;
+L_0x2a96920 .delay (10000,10000,10000) L_0x2a96920/d;
+L_0x2a97930/d .functor NOT 1, L_0x2a979f0, C4<0>, C4<0>, C4<0>;
+L_0x2a97930 .delay (10000,10000,10000) L_0x2a97930/d;
+L_0x2a97a90/d .functor AND 1, L_0x2a97bd0, L_0x2a97930, C4<1>, C4<1>;
+L_0x2a97a90 .delay (20000,20000,20000) L_0x2a97a90/d;
+L_0x2a97c70/d .functor XOR 1, L_0x2a96ce0, L_0x2a976c0, C4<0>, C4<0>;
+L_0x2a97c70 .delay (40000,40000,40000) L_0x2a97c70/d;
+L_0x2a97d60/d .functor XOR 1, L_0x2a97c70, L_0x2a96eb0, C4<0>, C4<0>;
+L_0x2a97d60 .delay (40000,40000,40000) L_0x2a97d60/d;
+L_0x2a97e50/d .functor AND 1, L_0x2a96ce0, L_0x2a976c0, C4<1>, C4<1>;
+L_0x2a97e50 .delay (20000,20000,20000) L_0x2a97e50/d;
+L_0x2a97fc0/d .functor AND 1, L_0x2a97c70, L_0x2a96eb0, C4<1>, C4<1>;
+L_0x2a97fc0 .delay (20000,20000,20000) L_0x2a97fc0/d;
+L_0x2a980b0/d .functor OR 1, L_0x2a97e50, L_0x2a97fc0, C4<0>, C4<0>;
+L_0x2a980b0 .delay (20000,20000,20000) L_0x2a980b0/d;
+v0x286eec0_0 .net "A", 0 0, L_0x2a96ce0; 1 drivers
+v0x286ef80_0 .net "AandB", 0 0, L_0x2a97e50; 1 drivers
+v0x286f020_0 .net "AddSubSLTSum", 0 0, L_0x2a97d60; 1 drivers
+v0x286f0c0_0 .net "AxorB", 0 0, L_0x2a97c70; 1 drivers
+v0x286f140_0 .net "B", 0 0, L_0x2a96d80; 1 drivers
+v0x286f1f0_0 .net "BornB", 0 0, L_0x2a976c0; 1 drivers
+v0x286f2b0_0 .net "CINandAxorB", 0 0, L_0x2a97fc0; 1 drivers
+v0x286f330_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x286f3b0_0 .net *"_s3", 0 0, L_0x2a979f0; 1 drivers
+v0x286f430_0 .net *"_s5", 0 0, L_0x2a97bd0; 1 drivers
+v0x286f4d0_0 .net "carryin", 0 0, L_0x2a96eb0; 1 drivers
+v0x286f570_0 .net "carryout", 0 0, L_0x2a980b0; 1 drivers
+v0x286f610_0 .net "nB", 0 0, L_0x2a96920; 1 drivers
+v0x286f6c0_0 .net "nCmd2", 0 0, L_0x2a97930; 1 drivers
+v0x286f7c0_0 .net "subtract", 0 0, L_0x2a97a90; 1 drivers
+L_0x2a97890 .part v0x2960210_0, 0, 1;
+L_0x2a979f0 .part v0x2960210_0, 2, 1;
+L_0x2a97bd0 .part v0x2960210_0, 0, 1;
+S_0x286e930 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x286e840;
+ .timescale -9 -12;
+L_0x2a973e0/d .functor NOT 1, L_0x2a97890, C4<0>, C4<0>, C4<0>;
+L_0x2a973e0 .delay (10000,10000,10000) L_0x2a973e0/d;
+L_0x2a974a0/d .functor AND 1, L_0x2a96d80, L_0x2a973e0, C4<1>, C4<1>;
+L_0x2a974a0 .delay (20000,20000,20000) L_0x2a974a0/d;
+L_0x2a975b0/d .functor AND 1, L_0x2a96920, L_0x2a97890, C4<1>, C4<1>;
+L_0x2a975b0 .delay (20000,20000,20000) L_0x2a975b0/d;
+L_0x2a976c0/d .functor OR 1, L_0x2a974a0, L_0x2a975b0, C4<0>, C4<0>;
+L_0x2a976c0 .delay (20000,20000,20000) L_0x2a976c0/d;
+v0x286ea20_0 .net "S", 0 0, L_0x2a97890; 1 drivers
+v0x286eae0_0 .alias "in0", 0 0, v0x286f140_0;
+v0x286eb80_0 .alias "in1", 0 0, v0x286f610_0;
+v0x286ec20_0 .net "nS", 0 0, L_0x2a973e0; 1 drivers
+v0x286eca0_0 .net "out0", 0 0, L_0x2a974a0; 1 drivers
+v0x286ed40_0 .net "out1", 0 0, L_0x2a975b0; 1 drivers
+v0x286ee20_0 .alias "outfinal", 0 0, v0x286f1f0_0;
+S_0x286e2d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286dbe0;
+ .timescale -9 -12;
+L_0x2a96f50/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a96f50 .delay (10000,10000,10000) L_0x2a96f50/d;
+L_0x2a96ff0/d .functor AND 1, L_0x2a98be0, L_0x2a96f50, C4<1>, C4<1>;
+L_0x2a96ff0 .delay (20000,20000,20000) L_0x2a96ff0/d;
+L_0x2a97100/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a97100 .delay (20000,20000,20000) L_0x2a97100/d;
+L_0x2a971a0/d .functor OR 1, L_0x2a96ff0, L_0x2a97100, C4<0>, C4<0>;
+L_0x2a971a0 .delay (20000,20000,20000) L_0x2a971a0/d;
+v0x286e3c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x286e460_0 .net "in0", 0 0, L_0x2a98be0; 1 drivers
+v0x286e500_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x286e5a0_0 .net "nS", 0 0, L_0x2a96f50; 1 drivers
+v0x286e620_0 .net "out0", 0 0, L_0x2a96ff0; 1 drivers
+v0x286e6c0_0 .net "out1", 0 0, L_0x2a97100; 1 drivers
+v0x286e7a0_0 .net "outfinal", 0 0, L_0x2a971a0; 1 drivers
+S_0x286dd50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286dbe0;
+ .timescale -9 -12;
+L_0x2a940d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a940d0 .delay (10000,10000,10000) L_0x2a940d0/d;
+L_0x2a941c0/d .functor AND 1, L_0x2a98300, L_0x2a940d0, C4<1>, C4<1>;
+L_0x2a941c0 .delay (20000,20000,20000) L_0x2a941c0/d;
+L_0x2a98fa0/d .functor AND 1, L_0x2a983f0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a98fa0 .delay (20000,20000,20000) L_0x2a98fa0/d;
+L_0x2a99040/d .functor OR 1, L_0x2a941c0, L_0x2a98fa0, C4<0>, C4<0>;
+L_0x2a99040 .delay (20000,20000,20000) L_0x2a99040/d;
+v0x286de40_0 .alias "S", 0 0, v0x289f760_0;
+v0x286dec0_0 .net "in0", 0 0, L_0x2a98300; 1 drivers
+v0x286df60_0 .net "in1", 0 0, L_0x2a983f0; 1 drivers
+v0x286e000_0 .net "nS", 0 0, L_0x2a940d0; 1 drivers
+v0x286e0b0_0 .net "out0", 0 0, L_0x2a941c0; 1 drivers
+v0x286e150_0 .net "out1", 0 0, L_0x2a98fa0; 1 drivers
+v0x286e230_0 .net "outfinal", 0 0, L_0x2a99040; 1 drivers
+S_0x286bed0 .scope generate, "sltbits[27]" "sltbits[27]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x286b898 .param/l "i" 3 332, +C4<011011>;
+S_0x286cbc0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286bed0;
+ .timescale -9 -12;
+L_0x2a984e0/d .functor NOT 1, L_0x2a993b0, C4<0>, C4<0>, C4<0>;
+L_0x2a984e0 .delay (10000,10000,10000) L_0x2a984e0/d;
+L_0x2a98b60/d .functor NOT 1, L_0x2a99c00, C4<0>, C4<0>, C4<0>;
+L_0x2a98b60 .delay (10000,10000,10000) L_0x2a98b60/d;
+L_0x2a99ca0/d .functor AND 1, L_0x2a99de0, L_0x2a98b60, C4<1>, C4<1>;
+L_0x2a99ca0 .delay (20000,20000,20000) L_0x2a99ca0/d;
+L_0x2a99e80/d .functor XOR 1, L_0x2a99310, L_0x2a98990, C4<0>, C4<0>;
+L_0x2a99e80 .delay (40000,40000,40000) L_0x2a99e80/d;
+L_0x2a99f70/d .functor XOR 1, L_0x2a99e80, L_0x2a994e0, C4<0>, C4<0>;
+L_0x2a99f70 .delay (40000,40000,40000) L_0x2a99f70/d;
+L_0x2a9a060/d .functor AND 1, L_0x2a99310, L_0x2a98990, C4<1>, C4<1>;
+L_0x2a9a060 .delay (20000,20000,20000) L_0x2a9a060/d;
+L_0x2a9a1d0/d .functor AND 1, L_0x2a99e80, L_0x2a994e0, C4<1>, C4<1>;
+L_0x2a9a1d0 .delay (20000,20000,20000) L_0x2a9a1d0/d;
+L_0x2a9a2c0/d .functor OR 1, L_0x2a9a060, L_0x2a9a1d0, C4<0>, C4<0>;
+L_0x2a9a2c0 .delay (20000,20000,20000) L_0x2a9a2c0/d;
+v0x286d240_0 .net "A", 0 0, L_0x2a99310; 1 drivers
+v0x286d300_0 .net "AandB", 0 0, L_0x2a9a060; 1 drivers
+v0x286d3a0_0 .net "AddSubSLTSum", 0 0, L_0x2a99f70; 1 drivers
+v0x286d440_0 .net "AxorB", 0 0, L_0x2a99e80; 1 drivers
+v0x286d4c0_0 .net "B", 0 0, L_0x2a993b0; 1 drivers
+v0x286d570_0 .net "BornB", 0 0, L_0x2a98990; 1 drivers
+v0x286d630_0 .net "CINandAxorB", 0 0, L_0x2a9a1d0; 1 drivers
+v0x286d6b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x286d730_0 .net *"_s3", 0 0, L_0x2a99c00; 1 drivers
+v0x286d7b0_0 .net *"_s5", 0 0, L_0x2a99de0; 1 drivers
+v0x286d850_0 .net "carryin", 0 0, L_0x2a994e0; 1 drivers
+v0x286d8f0_0 .net "carryout", 0 0, L_0x2a9a2c0; 1 drivers
+v0x286d990_0 .net "nB", 0 0, L_0x2a984e0; 1 drivers
+v0x286da40_0 .net "nCmd2", 0 0, L_0x2a98b60; 1 drivers
+v0x286db40_0 .net "subtract", 0 0, L_0x2a99ca0; 1 drivers
+L_0x2a99b20 .part v0x2960210_0, 0, 1;
+L_0x2a99c00 .part v0x2960210_0, 2, 1;
+L_0x2a99de0 .part v0x2960210_0, 0, 1;
+S_0x286ccb0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x286cbc0;
+ .timescale -9 -12;
+L_0x2a986b0/d .functor NOT 1, L_0x2a99b20, C4<0>, C4<0>, C4<0>;
+L_0x2a986b0 .delay (10000,10000,10000) L_0x2a986b0/d;
+L_0x2a98770/d .functor AND 1, L_0x2a993b0, L_0x2a986b0, C4<1>, C4<1>;
+L_0x2a98770 .delay (20000,20000,20000) L_0x2a98770/d;
+L_0x2a98880/d .functor AND 1, L_0x2a984e0, L_0x2a99b20, C4<1>, C4<1>;
+L_0x2a98880 .delay (20000,20000,20000) L_0x2a98880/d;
+L_0x2a98990/d .functor OR 1, L_0x2a98770, L_0x2a98880, C4<0>, C4<0>;
+L_0x2a98990 .delay (20000,20000,20000) L_0x2a98990/d;
+v0x286cda0_0 .net "S", 0 0, L_0x2a99b20; 1 drivers
+v0x286ce60_0 .alias "in0", 0 0, v0x286d4c0_0;
+v0x286cf00_0 .alias "in1", 0 0, v0x286d990_0;
+v0x286cfa0_0 .net "nS", 0 0, L_0x2a986b0; 1 drivers
+v0x286d020_0 .net "out0", 0 0, L_0x2a98770; 1 drivers
+v0x286d0c0_0 .net "out1", 0 0, L_0x2a98880; 1 drivers
+v0x286d1a0_0 .alias "outfinal", 0 0, v0x286d570_0;
+S_0x286c650 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286bed0;
+ .timescale -9 -12;
+L_0x2a99580/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a99580 .delay (10000,10000,10000) L_0x2a99580/d;
+L_0x2a99620/d .functor AND 1, L_0x2a999b0, L_0x2a99580, C4<1>, C4<1>;
+L_0x2a99620 .delay (20000,20000,20000) L_0x2a99620/d;
+L_0x2a99730/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a99730 .delay (20000,20000,20000) L_0x2a99730/d;
+L_0x2a997d0/d .functor OR 1, L_0x2a99620, L_0x2a99730, C4<0>, C4<0>;
+L_0x2a997d0 .delay (20000,20000,20000) L_0x2a997d0/d;
+v0x286c740_0 .alias "S", 0 0, v0x289f760_0;
+v0x286c7e0_0 .net "in0", 0 0, L_0x2a999b0; 1 drivers
+v0x286c880_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x286c920_0 .net "nS", 0 0, L_0x2a99580; 1 drivers
+v0x286c9a0_0 .net "out0", 0 0, L_0x2a99620; 1 drivers
+v0x286ca40_0 .net "out1", 0 0, L_0x2a99730; 1 drivers
+v0x286cb20_0 .net "outfinal", 0 0, L_0x2a997d0; 1 drivers
+S_0x286c040 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286bed0;
+ .timescale -9 -12;
+L_0x2a9af70/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a9af70 .delay (10000,10000,10000) L_0x2a9af70/d;
+L_0x2a9b020/d .functor AND 1, L_0x2a9b3f0, L_0x2a9af70, C4<1>, C4<1>;
+L_0x2a9b020 .delay (20000,20000,20000) L_0x2a9b020/d;
+L_0x2a9b110/d .functor AND 1, L_0x2a9a5e0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a9b110 .delay (20000,20000,20000) L_0x2a9b110/d;
+L_0x2a9b1e0/d .functor OR 1, L_0x2a9b020, L_0x2a9b110, C4<0>, C4<0>;
+L_0x2a9b1e0 .delay (20000,20000,20000) L_0x2a9b1e0/d;
+v0x286c130_0 .alias "S", 0 0, v0x289f760_0;
+v0x2868860_0 .net "in0", 0 0, L_0x2a9b3f0; 1 drivers
+v0x286c2e0_0 .net "in1", 0 0, L_0x2a9a5e0; 1 drivers
+v0x286c380_0 .net "nS", 0 0, L_0x2a9af70; 1 drivers
+v0x286c430_0 .net "out0", 0 0, L_0x2a9b020; 1 drivers
+v0x286c4d0_0 .net "out1", 0 0, L_0x2a9b110; 1 drivers
+v0x286c5b0_0 .net "outfinal", 0 0, L_0x2a9b1e0; 1 drivers
+S_0x286a220 .scope generate, "sltbits[28]" "sltbits[28]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2868088 .param/l "i" 3 332, +C4<011100>;
+S_0x286ae60 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x286a220;
+ .timescale -9 -12;
+L_0x2a9a6d0/d .functor NOT 1, L_0x2a9b760, C4<0>, C4<0>, C4<0>;
+L_0x2a9a6d0 .delay (10000,10000,10000) L_0x2a9a6d0/d;
+L_0x2a9ae10/d .functor NOT 1, L_0x2a9be30, C4<0>, C4<0>, C4<0>;
+L_0x2a9ae10 .delay (10000,10000,10000) L_0x2a9ae10/d;
+L_0x2a9bed0/d .functor AND 1, L_0x2a9bfc0, L_0x2a9ae10, C4<1>, C4<1>;
+L_0x2a9bed0 .delay (20000,20000,20000) L_0x2a9bed0/d;
+L_0x2a9c060/d .functor XOR 1, L_0x2a9b6c0, L_0x2a9aba0, C4<0>, C4<0>;
+L_0x2a9c060 .delay (40000,40000,40000) L_0x2a9c060/d;
+L_0x2a9c150/d .functor XOR 1, L_0x2a9c060, L_0x2a9b890, C4<0>, C4<0>;
+L_0x2a9c150 .delay (40000,40000,40000) L_0x2a9c150/d;
+L_0x2a9c240/d .functor AND 1, L_0x2a9b6c0, L_0x2a9aba0, C4<1>, C4<1>;
+L_0x2a9c240 .delay (20000,20000,20000) L_0x2a9c240/d;
+L_0x2a9c3b0/d .functor AND 1, L_0x2a9c060, L_0x2a9b890, C4<1>, C4<1>;
+L_0x2a9c3b0 .delay (20000,20000,20000) L_0x2a9c3b0/d;
+L_0x2a9c4a0/d .functor OR 1, L_0x2a9c240, L_0x2a9c3b0, C4<0>, C4<0>;
+L_0x2a9c4a0 .delay (20000,20000,20000) L_0x2a9c4a0/d;
+v0x286b4e0_0 .net "A", 0 0, L_0x2a9b6c0; 1 drivers
+v0x286b5a0_0 .net "AandB", 0 0, L_0x2a9c240; 1 drivers
+v0x286b640_0 .net "AddSubSLTSum", 0 0, L_0x2a9c150; 1 drivers
+v0x286b6e0_0 .net "AxorB", 0 0, L_0x2a9c060; 1 drivers
+v0x286b760_0 .net "B", 0 0, L_0x2a9b760; 1 drivers
+v0x286b810_0 .net "BornB", 0 0, L_0x2a9aba0; 1 drivers
+v0x286b8d0_0 .net "CINandAxorB", 0 0, L_0x2a9c3b0; 1 drivers
+v0x286b950_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x286ba20_0 .net *"_s3", 0 0, L_0x2a9be30; 1 drivers
+v0x286baa0_0 .net *"_s5", 0 0, L_0x2a9bfc0; 1 drivers
+v0x286bb40_0 .net "carryin", 0 0, L_0x2a9b890; 1 drivers
+v0x286bbe0_0 .net "carryout", 0 0, L_0x2a9c4a0; 1 drivers
+v0x286bc80_0 .net "nB", 0 0, L_0x2a9a6d0; 1 drivers
+v0x286bd30_0 .net "nCmd2", 0 0, L_0x2a9ae10; 1 drivers
+v0x286be30_0 .net "subtract", 0 0, L_0x2a9bed0; 1 drivers
+L_0x2a9ad70 .part v0x2960210_0, 0, 1;
+L_0x2a9be30 .part v0x2960210_0, 2, 1;
+L_0x2a9bfc0 .part v0x2960210_0, 0, 1;
+S_0x286af50 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x286ae60;
+ .timescale -9 -12;
+L_0x2a9a8c0/d .functor NOT 1, L_0x2a9ad70, C4<0>, C4<0>, C4<0>;
+L_0x2a9a8c0 .delay (10000,10000,10000) L_0x2a9a8c0/d;
+L_0x2a9a980/d .functor AND 1, L_0x2a9b760, L_0x2a9a8c0, C4<1>, C4<1>;
+L_0x2a9a980 .delay (20000,20000,20000) L_0x2a9a980/d;
+L_0x2a9aa90/d .functor AND 1, L_0x2a9a6d0, L_0x2a9ad70, C4<1>, C4<1>;
+L_0x2a9aa90 .delay (20000,20000,20000) L_0x2a9aa90/d;
+L_0x2a9aba0/d .functor OR 1, L_0x2a9a980, L_0x2a9aa90, C4<0>, C4<0>;
+L_0x2a9aba0 .delay (20000,20000,20000) L_0x2a9aba0/d;
+v0x286b040_0 .net "S", 0 0, L_0x2a9ad70; 1 drivers
+v0x286b100_0 .alias "in0", 0 0, v0x286b760_0;
+v0x286b1a0_0 .alias "in1", 0 0, v0x286bc80_0;
+v0x286b240_0 .net "nS", 0 0, L_0x2a9a8c0; 1 drivers
+v0x286b2c0_0 .net "out0", 0 0, L_0x2a9a980; 1 drivers
+v0x286b360_0 .net "out1", 0 0, L_0x2a9aa90; 1 drivers
+v0x286b440_0 .alias "outfinal", 0 0, v0x286b810_0;
+S_0x286a8f0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x286a220;
+ .timescale -9 -12;
+L_0x2a9b930/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a9b930 .delay (10000,10000,10000) L_0x2a9b930/d;
+L_0x2a9b9d0/d .functor AND 1, L_0x2a9bd60, L_0x2a9b930, C4<1>, C4<1>;
+L_0x2a9b9d0 .delay (20000,20000,20000) L_0x2a9b9d0/d;
+L_0x2a9bae0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a9bae0 .delay (20000,20000,20000) L_0x2a9bae0/d;
+L_0x2a9bb80/d .functor OR 1, L_0x2a9b9d0, L_0x2a9bae0, C4<0>, C4<0>;
+L_0x2a9bb80 .delay (20000,20000,20000) L_0x2a9bb80/d;
+v0x286a9e0_0 .alias "S", 0 0, v0x289f760_0;
+v0x286aa80_0 .net "in0", 0 0, L_0x2a9bd60; 1 drivers
+v0x286ab20_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x286abc0_0 .net "nS", 0 0, L_0x2a9b930; 1 drivers
+v0x286ac40_0 .net "out0", 0 0, L_0x2a9b9d0; 1 drivers
+v0x286ace0_0 .net "out1", 0 0, L_0x2a9bae0; 1 drivers
+v0x286adc0_0 .net "outfinal", 0 0, L_0x2a9bb80; 1 drivers
+S_0x286a370 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x286a220;
+ .timescale -9 -12;
+L_0x2a98d60/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a98d60 .delay (10000,10000,10000) L_0x2a98d60/d;
+L_0x2a98e70/d .functor AND 1, L_0x2a9c6d0, L_0x2a98d60, C4<1>, C4<1>;
+L_0x2a98e70 .delay (20000,20000,20000) L_0x2a98e70/d;
+L_0x2a9d390/d .functor AND 1, L_0x2a9c7c0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a9d390 .delay (20000,20000,20000) L_0x2a9d390/d;
+L_0x2a9d430/d .functor OR 1, L_0x2a98e70, L_0x2a9d390, C4<0>, C4<0>;
+L_0x2a9d430 .delay (20000,20000,20000) L_0x2a9d430/d;
+v0x286a460_0 .alias "S", 0 0, v0x289f760_0;
+v0x286a4e0_0 .net "in0", 0 0, L_0x2a9c6d0; 1 drivers
+v0x286a580_0 .net "in1", 0 0, L_0x2a9c7c0; 1 drivers
+v0x286a620_0 .net "nS", 0 0, L_0x2a98d60; 1 drivers
+v0x286a6d0_0 .net "out0", 0 0, L_0x2a98e70; 1 drivers
+v0x286a770_0 .net "out1", 0 0, L_0x2a9d390; 1 drivers
+v0x286a850_0 .net "outfinal", 0 0, L_0x2a9d430; 1 drivers
+S_0x2868580 .scope generate, "sltbits[29]" "sltbits[29]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2867f48 .param/l "i" 3 332, +C4<011101>;
+S_0x2869270 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2868580;
+ .timescale -9 -12;
+L_0x2a9c8b0/d .functor NOT 1, L_0x2a9d7a0, C4<0>, C4<0>, C4<0>;
+L_0x2a9c8b0 .delay (10000,10000,10000) L_0x2a9c8b0/d;
+L_0x2a9cfb0/d .functor NOT 1, L_0x2a9e000, C4<0>, C4<0>, C4<0>;
+L_0x2a9cfb0 .delay (10000,10000,10000) L_0x2a9cfb0/d;
+L_0x2a9e0a0/d .functor AND 1, L_0x2a9e1e0, L_0x2a9cfb0, C4<1>, C4<1>;
+L_0x2a9e0a0 .delay (20000,20000,20000) L_0x2a9e0a0/d;
+L_0x2a9e280/d .functor XOR 1, L_0x2a9d700, L_0x2a9cd40, C4<0>, C4<0>;
+L_0x2a9e280 .delay (40000,40000,40000) L_0x2a9e280/d;
+L_0x2a9e370/d .functor XOR 1, L_0x2a9e280, L_0x2a9d8d0, C4<0>, C4<0>;
+L_0x2a9e370 .delay (40000,40000,40000) L_0x2a9e370/d;
+L_0x2a9e460/d .functor AND 1, L_0x2a9d700, L_0x2a9cd40, C4<1>, C4<1>;
+L_0x2a9e460 .delay (20000,20000,20000) L_0x2a9e460/d;
+L_0x2a9e5d0/d .functor AND 1, L_0x2a9e280, L_0x2a9d8d0, C4<1>, C4<1>;
+L_0x2a9e5d0 .delay (20000,20000,20000) L_0x2a9e5d0/d;
+L_0x2a9e6c0/d .functor OR 1, L_0x2a9e460, L_0x2a9e5d0, C4<0>, C4<0>;
+L_0x2a9e6c0 .delay (20000,20000,20000) L_0x2a9e6c0/d;
+v0x28698f0_0 .net "A", 0 0, L_0x2a9d700; 1 drivers
+v0x28699b0_0 .net "AandB", 0 0, L_0x2a9e460; 1 drivers
+v0x2869a50_0 .net "AddSubSLTSum", 0 0, L_0x2a9e370; 1 drivers
+v0x2869af0_0 .net "AxorB", 0 0, L_0x2a9e280; 1 drivers
+v0x2869b70_0 .net "B", 0 0, L_0x2a9d7a0; 1 drivers
+v0x2869c20_0 .net "BornB", 0 0, L_0x2a9cd40; 1 drivers
+v0x2869ce0_0 .net "CINandAxorB", 0 0, L_0x2a9e5d0; 1 drivers
+v0x2869d60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2869de0_0 .net *"_s3", 0 0, L_0x2a9e000; 1 drivers
+v0x2869e60_0 .net *"_s5", 0 0, L_0x2a9e1e0; 1 drivers
+v0x2869f00_0 .net "carryin", 0 0, L_0x2a9d8d0; 1 drivers
+v0x2869fa0_0 .net "carryout", 0 0, L_0x2a9e6c0; 1 drivers
+v0x286a020_0 .net "nB", 0 0, L_0x2a9c8b0; 1 drivers
+v0x286a0a0_0 .net "nCmd2", 0 0, L_0x2a9cfb0; 1 drivers
+v0x286a1a0_0 .net "subtract", 0 0, L_0x2a9e0a0; 1 drivers
+L_0x2a9cf10 .part v0x2960210_0, 0, 1;
+L_0x2a9e000 .part v0x2960210_0, 2, 1;
+L_0x2a9e1e0 .part v0x2960210_0, 0, 1;
+S_0x2869360 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2869270;
+ .timescale -9 -12;
+L_0x2a9ca60/d .functor NOT 1, L_0x2a9cf10, C4<0>, C4<0>, C4<0>;
+L_0x2a9ca60 .delay (10000,10000,10000) L_0x2a9ca60/d;
+L_0x2a9cb20/d .functor AND 1, L_0x2a9d7a0, L_0x2a9ca60, C4<1>, C4<1>;
+L_0x2a9cb20 .delay (20000,20000,20000) L_0x2a9cb20/d;
+L_0x2a9cc30/d .functor AND 1, L_0x2a9c8b0, L_0x2a9cf10, C4<1>, C4<1>;
+L_0x2a9cc30 .delay (20000,20000,20000) L_0x2a9cc30/d;
+L_0x2a9cd40/d .functor OR 1, L_0x2a9cb20, L_0x2a9cc30, C4<0>, C4<0>;
+L_0x2a9cd40 .delay (20000,20000,20000) L_0x2a9cd40/d;
+v0x2869450_0 .net "S", 0 0, L_0x2a9cf10; 1 drivers
+v0x2869510_0 .alias "in0", 0 0, v0x2869b70_0;
+v0x28695b0_0 .alias "in1", 0 0, v0x286a020_0;
+v0x2869650_0 .net "nS", 0 0, L_0x2a9ca60; 1 drivers
+v0x28696d0_0 .net "out0", 0 0, L_0x2a9cb20; 1 drivers
+v0x2869770_0 .net "out1", 0 0, L_0x2a9cc30; 1 drivers
+v0x2869850_0 .alias "outfinal", 0 0, v0x2869c20_0;
+S_0x2868d00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2868580;
+ .timescale -9 -12;
+L_0x2a9d970/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a9d970 .delay (10000,10000,10000) L_0x2a9d970/d;
+L_0x2a9da10/d .functor AND 1, L_0x2a9dda0, L_0x2a9d970, C4<1>, C4<1>;
+L_0x2a9da10 .delay (20000,20000,20000) L_0x2a9da10/d;
+L_0x2a9db20/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a9db20 .delay (20000,20000,20000) L_0x2a9db20/d;
+L_0x2a9dbc0/d .functor OR 1, L_0x2a9da10, L_0x2a9db20, C4<0>, C4<0>;
+L_0x2a9dbc0 .delay (20000,20000,20000) L_0x2a9dbc0/d;
+v0x2868df0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2868e90_0 .net "in0", 0 0, L_0x2a9dda0; 1 drivers
+v0x2868f30_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2868fd0_0 .net "nS", 0 0, L_0x2a9d970; 1 drivers
+v0x2869050_0 .net "out0", 0 0, L_0x2a9da10; 1 drivers
+v0x28690f0_0 .net "out1", 0 0, L_0x2a9db20; 1 drivers
+v0x28691d0_0 .net "outfinal", 0 0, L_0x2a9dbc0; 1 drivers
+S_0x28686f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2868580;
+ .timescale -9 -12;
+L_0x2a9df20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a9df20 .delay (10000,10000,10000) L_0x2a9df20/d;
+L_0x2a9f420/d .functor AND 1, L_0x2a9f7c0, L_0x2a9df20, C4<1>, C4<1>;
+L_0x2a9f420 .delay (20000,20000,20000) L_0x2a9f420/d;
+L_0x2a9f510/d .functor AND 1, L_0x2a9e9e0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a9f510 .delay (20000,20000,20000) L_0x2a9f510/d;
+L_0x2a9f5b0/d .functor OR 1, L_0x2a9f420, L_0x2a9f510, C4<0>, C4<0>;
+L_0x2a9f5b0 .delay (20000,20000,20000) L_0x2a9f5b0/d;
+v0x28687e0_0 .alias "S", 0 0, v0x289f760_0;
+v0x28688f0_0 .net "in0", 0 0, L_0x2a9f7c0; 1 drivers
+v0x2868990_0 .net "in1", 0 0, L_0x2a9e9e0; 1 drivers
+v0x2868a30_0 .net "nS", 0 0, L_0x2a9df20; 1 drivers
+v0x2868ae0_0 .net "out0", 0 0, L_0x2a9f420; 1 drivers
+v0x2868b80_0 .net "out1", 0 0, L_0x2a9f510; 1 drivers
+v0x2868c60_0 .net "outfinal", 0 0, L_0x2a9f5b0; 1 drivers
+S_0x28668e0 .scope generate, "sltbits[30]" "sltbits[30]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2866288 .param/l "i" 3 332, +C4<011110>;
+S_0x2867510 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x28668e0;
+ .timescale -9 -12;
+L_0x2a9ead0/d .functor NOT 1, L_0x2a9fb30, C4<0>, C4<0>, C4<0>;
+L_0x2a9ead0 .delay (10000,10000,10000) L_0x2a9ead0/d;
+L_0x2a9f210/d .functor NOT 1, L_0x2a9f2d0, C4<0>, C4<0>, C4<0>;
+L_0x2a9f210 .delay (10000,10000,10000) L_0x2a9f210/d;
+L_0x2a9f370/d .functor AND 1, L_0x2aa0390, L_0x2a9f210, C4<1>, C4<1>;
+L_0x2a9f370 .delay (20000,20000,20000) L_0x2a9f370/d;
+L_0x2aa0430/d .functor XOR 1, L_0x2a9fa90, L_0x2a9efa0, C4<0>, C4<0>;
+L_0x2aa0430 .delay (40000,40000,40000) L_0x2aa0430/d;
+L_0x2aa0520/d .functor XOR 1, L_0x2aa0430, L_0x2a9fc60, C4<0>, C4<0>;
+L_0x2aa0520 .delay (40000,40000,40000) L_0x2aa0520/d;
+L_0x2aa0610/d .functor AND 1, L_0x2a9fa90, L_0x2a9efa0, C4<1>, C4<1>;
+L_0x2aa0610 .delay (20000,20000,20000) L_0x2aa0610/d;
+L_0x2aa0780/d .functor AND 1, L_0x2aa0430, L_0x2a9fc60, C4<1>, C4<1>;
+L_0x2aa0780 .delay (20000,20000,20000) L_0x2aa0780/d;
+L_0x2aa0870/d .functor OR 1, L_0x2aa0610, L_0x2aa0780, C4<0>, C4<0>;
+L_0x2aa0870 .delay (20000,20000,20000) L_0x2aa0870/d;
+v0x2867b90_0 .net "A", 0 0, L_0x2a9fa90; 1 drivers
+v0x2867c50_0 .net "AandB", 0 0, L_0x2aa0610; 1 drivers
+v0x2867cf0_0 .net "AddSubSLTSum", 0 0, L_0x2aa0520; 1 drivers
+v0x2867d90_0 .net "AxorB", 0 0, L_0x2aa0430; 1 drivers
+v0x2867e10_0 .net "B", 0 0, L_0x2a9fb30; 1 drivers
+v0x2867ec0_0 .net "BornB", 0 0, L_0x2a9efa0; 1 drivers
+v0x2867f80_0 .net "CINandAxorB", 0 0, L_0x2aa0780; 1 drivers
+v0x2868000_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28680d0_0 .net *"_s3", 0 0, L_0x2a9f2d0; 1 drivers
+v0x2868150_0 .net *"_s5", 0 0, L_0x2aa0390; 1 drivers
+v0x28681f0_0 .net "carryin", 0 0, L_0x2a9fc60; 1 drivers
+v0x2868290_0 .net "carryout", 0 0, L_0x2aa0870; 1 drivers
+v0x2868330_0 .net "nB", 0 0, L_0x2a9ead0; 1 drivers
+v0x28683e0_0 .net "nCmd2", 0 0, L_0x2a9f210; 1 drivers
+v0x28684e0_0 .net "subtract", 0 0, L_0x2a9f370; 1 drivers
+L_0x2a9f170 .part v0x2960210_0, 0, 1;
+L_0x2a9f2d0 .part v0x2960210_0, 2, 1;
+L_0x2aa0390 .part v0x2960210_0, 0, 1;
+S_0x2867600 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2867510;
+ .timescale -9 -12;
+L_0x2a9ecc0/d .functor NOT 1, L_0x2a9f170, C4<0>, C4<0>, C4<0>;
+L_0x2a9ecc0 .delay (10000,10000,10000) L_0x2a9ecc0/d;
+L_0x2a9ed80/d .functor AND 1, L_0x2a9fb30, L_0x2a9ecc0, C4<1>, C4<1>;
+L_0x2a9ed80 .delay (20000,20000,20000) L_0x2a9ed80/d;
+L_0x2a9ee90/d .functor AND 1, L_0x2a9ead0, L_0x2a9f170, C4<1>, C4<1>;
+L_0x2a9ee90 .delay (20000,20000,20000) L_0x2a9ee90/d;
+L_0x2a9efa0/d .functor OR 1, L_0x2a9ed80, L_0x2a9ee90, C4<0>, C4<0>;
+L_0x2a9efa0 .delay (20000,20000,20000) L_0x2a9efa0/d;
+v0x28676f0_0 .net "S", 0 0, L_0x2a9f170; 1 drivers
+v0x28677b0_0 .alias "in0", 0 0, v0x2867e10_0;
+v0x2867850_0 .alias "in1", 0 0, v0x2868330_0;
+v0x28678f0_0 .net "nS", 0 0, L_0x2a9ecc0; 1 drivers
+v0x2867970_0 .net "out0", 0 0, L_0x2a9ed80; 1 drivers
+v0x2867a10_0 .net "out1", 0 0, L_0x2a9ee90; 1 drivers
+v0x2867af0_0 .alias "outfinal", 0 0, v0x2867ec0_0;
+S_0x2866fa0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x28668e0;
+ .timescale -9 -12;
+L_0x2a9fd00/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a9fd00 .delay (10000,10000,10000) L_0x2a9fd00/d;
+L_0x2a9fda0/d .functor AND 1, L_0x2aa0130, L_0x2a9fd00, C4<1>, C4<1>;
+L_0x2a9fda0 .delay (20000,20000,20000) L_0x2a9fda0/d;
+L_0x2a9feb0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2a9feb0 .delay (20000,20000,20000) L_0x2a9feb0/d;
+L_0x2a9ff50/d .functor OR 1, L_0x2a9fda0, L_0x2a9feb0, C4<0>, C4<0>;
+L_0x2a9ff50 .delay (20000,20000,20000) L_0x2a9ff50/d;
+v0x2867090_0 .alias "S", 0 0, v0x289f760_0;
+v0x2867130_0 .net "in0", 0 0, L_0x2aa0130; 1 drivers
+v0x28671d0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2867270_0 .net "nS", 0 0, L_0x2a9fd00; 1 drivers
+v0x28672f0_0 .net "out0", 0 0, L_0x2a9fda0; 1 drivers
+v0x2867390_0 .net "out1", 0 0, L_0x2a9feb0; 1 drivers
+v0x2867470_0 .net "outfinal", 0 0, L_0x2a9ff50; 1 drivers
+S_0x2866a50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x28668e0;
+ .timescale -9 -12;
+L_0x2a9d140/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2a9d140 .delay (10000,10000,10000) L_0x2a9d140/d;
+L_0x2a9d250/d .functor AND 1, L_0x2aa0aa0, L_0x2a9d140, C4<1>, C4<1>;
+L_0x2a9d250 .delay (20000,20000,20000) L_0x2a9d250/d;
+L_0x2aa1740/d .functor AND 1, L_0x2aa0b90, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2aa1740 .delay (20000,20000,20000) L_0x2aa1740/d;
+L_0x2aa17e0/d .functor OR 1, L_0x2a9d250, L_0x2aa1740, C4<0>, C4<0>;
+L_0x2aa17e0 .delay (20000,20000,20000) L_0x2aa17e0/d;
+v0x2866b40_0 .alias "S", 0 0, v0x289f760_0;
+v0x2866bc0_0 .net "in0", 0 0, L_0x2aa0aa0; 1 drivers
+v0x2866c60_0 .net "in1", 0 0, L_0x2aa0b90; 1 drivers
+v0x2866d00_0 .net "nS", 0 0, L_0x2a9d140; 1 drivers
+v0x2866d80_0 .net "out0", 0 0, L_0x2a9d250; 1 drivers
+v0x2866e20_0 .net "out1", 0 0, L_0x2aa1740; 1 drivers
+v0x2866f00_0 .net "outfinal", 0 0, L_0x2aa17e0; 1 drivers
+S_0x2864bb0 .scope generate, "sltbits[31]" "sltbits[31]" 3 332, 3 332, S_0x2864a60;
+ .timescale -9 -12;
+P_0x2864ca8 .param/l "i" 3 332, +C4<011111>;
+S_0x2865850 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2864bb0;
+ .timescale -9 -12;
+L_0x2aa0c80/d .functor NOT 1, L_0x2aa1b50, C4<0>, C4<0>, C4<0>;
+L_0x2aa0c80 .delay (10000,10000,10000) L_0x2aa0c80/d;
+L_0x2aa13a0/d .functor NOT 1, L_0x2aa2420, C4<0>, C4<0>, C4<0>;
+L_0x2aa13a0 .delay (10000,10000,10000) L_0x2aa13a0/d;
+L_0x2aa1460/d .functor AND 1, L_0x2aa25a0, L_0x2aa13a0, C4<1>, C4<1>;
+L_0x2aa1460 .delay (20000,20000,20000) L_0x2aa1460/d;
+L_0x2aa2640/d .functor XOR 1, L_0x2aa1ab0, L_0x2aa1130, C4<0>, C4<0>;
+L_0x2aa2640 .delay (40000,40000,40000) L_0x2aa2640/d;
+L_0x2aa2730/d .functor XOR 1, L_0x2aa2640, L_0x2aa1c80, C4<0>, C4<0>;
+L_0x2aa2730 .delay (40000,40000,40000) L_0x2aa2730/d;
+L_0x2aa2820/d .functor AND 1, L_0x2aa1ab0, L_0x2aa1130, C4<1>, C4<1>;
+L_0x2aa2820 .delay (20000,20000,20000) L_0x2aa2820/d;
+L_0x2aa2990/d .functor AND 1, L_0x2aa2640, L_0x2aa1c80, C4<1>, C4<1>;
+L_0x2aa2990 .delay (20000,20000,20000) L_0x2aa2990/d;
+L_0x2aa2a80/d .functor OR 1, L_0x2aa2820, L_0x2aa2990, C4<0>, C4<0>;
+L_0x2aa2a80 .delay (20000,20000,20000) L_0x2aa2a80/d;
+v0x2865ed0_0 .net "A", 0 0, L_0x2aa1ab0; 1 drivers
+v0x2865f90_0 .net "AandB", 0 0, L_0x2aa2820; 1 drivers
+v0x2866030_0 .net "AddSubSLTSum", 0 0, L_0x2aa2730; 1 drivers
+v0x28660d0_0 .net "AxorB", 0 0, L_0x2aa2640; 1 drivers
+v0x2866150_0 .net "B", 0 0, L_0x2aa1b50; 1 drivers
+v0x2866200_0 .net "BornB", 0 0, L_0x2aa1130; 1 drivers
+v0x28662c0_0 .net "CINandAxorB", 0 0, L_0x2aa2990; 1 drivers
+v0x2866340_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28663c0_0 .net *"_s3", 0 0, L_0x2aa2420; 1 drivers
+v0x2866440_0 .net *"_s5", 0 0, L_0x2aa25a0; 1 drivers
+v0x28664e0_0 .net "carryin", 0 0, L_0x2aa1c80; 1 drivers
+v0x2866580_0 .net "carryout", 0 0, L_0x2aa2a80; 1 drivers
+v0x2866690_0 .net "nB", 0 0, L_0x2aa0c80; 1 drivers
+v0x2866740_0 .net "nCmd2", 0 0, L_0x2aa13a0; 1 drivers
+v0x2866840_0 .net "subtract", 0 0, L_0x2aa1460; 1 drivers
+L_0x2aa1300 .part v0x2960210_0, 0, 1;
+L_0x2aa2420 .part v0x2960210_0, 2, 1;
+L_0x2aa25a0 .part v0x2960210_0, 0, 1;
+S_0x2865940 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2865850;
+ .timescale -9 -12;
+L_0x2aa0e50/d .functor NOT 1, L_0x2aa1300, C4<0>, C4<0>, C4<0>;
+L_0x2aa0e50 .delay (10000,10000,10000) L_0x2aa0e50/d;
+L_0x2aa0f10/d .functor AND 1, L_0x2aa1b50, L_0x2aa0e50, C4<1>, C4<1>;
+L_0x2aa0f10 .delay (20000,20000,20000) L_0x2aa0f10/d;
+L_0x2aa1020/d .functor AND 1, L_0x2aa0c80, L_0x2aa1300, C4<1>, C4<1>;
+L_0x2aa1020 .delay (20000,20000,20000) L_0x2aa1020/d;
+L_0x2aa1130/d .functor OR 1, L_0x2aa0f10, L_0x2aa1020, C4<0>, C4<0>;
+L_0x2aa1130 .delay (20000,20000,20000) L_0x2aa1130/d;
+v0x2865a30_0 .net "S", 0 0, L_0x2aa1300; 1 drivers
+v0x2865af0_0 .alias "in0", 0 0, v0x2866150_0;
+v0x2865b90_0 .alias "in1", 0 0, v0x2866690_0;
+v0x2865c30_0 .net "nS", 0 0, L_0x2aa0e50; 1 drivers
+v0x2865cb0_0 .net "out0", 0 0, L_0x2aa0f10; 1 drivers
+v0x2865d50_0 .net "out1", 0 0, L_0x2aa1020; 1 drivers
+v0x2865e30_0 .alias "outfinal", 0 0, v0x2866200_0;
+S_0x28652d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2864bb0;
+ .timescale -9 -12;
+L_0x2aa1d20/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2aa1d20 .delay (10000,10000,10000) L_0x2aa1d20/d;
+L_0x2aa1dc0/d .functor AND 1, L_0x2aa2150, L_0x2aa1d20, C4<1>, C4<1>;
+L_0x2aa1dc0 .delay (20000,20000,20000) L_0x2aa1dc0/d;
+L_0x2aa1ed0/d .functor AND 1, C4<0>, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2aa1ed0 .delay (20000,20000,20000) L_0x2aa1ed0/d;
+L_0x2aa1f70/d .functor OR 1, L_0x2aa1dc0, L_0x2aa1ed0, C4<0>, C4<0>;
+L_0x2aa1f70 .delay (20000,20000,20000) L_0x2aa1f70/d;
+v0x28653c0_0 .alias "S", 0 0, v0x289f760_0;
+v0x2865460_0 .net "in0", 0 0, L_0x2aa2150; 1 drivers
+v0x28654e0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2865580_0 .net "nS", 0 0, L_0x2aa1d20; 1 drivers
+v0x2865630_0 .net "out0", 0 0, L_0x2aa1dc0; 1 drivers
+v0x28656d0_0 .net "out1", 0 0, L_0x2aa1ed0; 1 drivers
+v0x28657b0_0 .net "outfinal", 0 0, L_0x2aa1f70; 1 drivers
+S_0x2864d60 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2864bb0;
+ .timescale -9 -12;
+L_0x2aa22d0/d .functor NOT 1, L_0x2aa3020, C4<0>, C4<0>, C4<0>;
+L_0x2aa22d0 .delay (10000,10000,10000) L_0x2aa22d0/d;
+L_0x2aa3840/d .functor AND 1, L_0x2aa3b70, L_0x2aa22d0, C4<1>, C4<1>;
+L_0x2aa3840 .delay (20000,20000,20000) L_0x2aa3840/d;
+L_0x2aa38f0/d .functor AND 1, L_0x2aa2da0, L_0x2aa3020, C4<1>, C4<1>;
+L_0x2aa38f0 .delay (20000,20000,20000) L_0x2aa38f0/d;
+L_0x2aa3990/d .functor OR 1, L_0x2aa3840, L_0x2aa38f0, C4<0>, C4<0>;
+L_0x2aa3990 .delay (20000,20000,20000) L_0x2aa3990/d;
+v0x2864e50_0 .alias "S", 0 0, v0x289f760_0;
+v0x2864ef0_0 .net "in0", 0 0, L_0x2aa3b70; 1 drivers
+v0x2864f90_0 .net "in1", 0 0, L_0x2aa2da0; 1 drivers
+v0x2865030_0 .net "nS", 0 0, L_0x2aa22d0; 1 drivers
+v0x28650b0_0 .net "out0", 0 0, L_0x2aa3840; 1 drivers
+v0x2865150_0 .net "out1", 0 0, L_0x2aa38f0; 1 drivers
+v0x2865230_0 .net "outfinal", 0 0, L_0x2aa3990; 1 drivers
+S_0x2840e20 .scope module, "trial" "AddSubSLT32" 3 386, 3 267, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2840f18 .param/l "size" 3 281, +C4<0100000>;
+L_0x2ad5950/d .functor OR 1, L_0x2ad59d0, C4<0>, C4<0>, C4<0>;
+L_0x2ad5950 .delay (20000,20000,20000) L_0x2ad5950/d;
+L_0x2abcea0/d .functor XOR 1, RS_0x7f507e9ad6e8, L_0x2abcfb0, C4<0>, C4<0>;
+L_0x2abcea0 .delay (40000,40000,40000) L_0x2abcea0/d;
+v0x2864310_0 .alias "A", 31 0, v0x295f580_0;
+v0x28643b0_0 .alias "AddSubSLTSum", 31 0, v0x295ff30_0;
+v0x2864450_0 .alias "B", 31 0, v0x295f6a0_0;
+RS_0x7f507e9ad5f8/0/0 .resolv tri, L_0x2aa89e0, L_0x2aa9f00, L_0x2aab440, L_0x2aaca40;
+RS_0x7f507e9ad5f8/0/4 .resolv tri, L_0x2aadfe0, L_0x2aaf510, L_0x2ab0a30, L_0x2ab1f50;
+RS_0x7f507e9ad5f8/0/8 .resolv tri, L_0x2ab3560, L_0x2ab4a70, L_0x2ab5f80, L_0x2ab7490;
+RS_0x7f507e9ad5f8/0/12 .resolv tri, L_0x2ab8990, L_0x2ab9ea0, L_0x2abb3b0, L_0x2abc7e0;
+RS_0x7f507e9ad5f8/0/16 .resolv tri, L_0x2abdea0, L_0x2abf310, L_0x2ac07c0, L_0x2ac1b90;
+RS_0x7f507e9ad5f8/0/20 .resolv tri, L_0x2ac2f50, L_0x2ac4460, L_0x2ac5820, L_0x2ac6c60;
+RS_0x7f507e9ad5f8/0/24 .resolv tri, L_0x2ac8920, L_0x2ac9e00, L_0x2997fb0, L_0x29994e0;
+RS_0x7f507e9ad5f8/0/28 .resolv tri, L_0x299a9c0, L_0x2ad31f0, L_0x2a36e10, L_0x2ad6370;
+RS_0x7f507e9ad5f8/1/0 .resolv tri, RS_0x7f507e9ad5f8/0/0, RS_0x7f507e9ad5f8/0/4, RS_0x7f507e9ad5f8/0/8, RS_0x7f507e9ad5f8/0/12;
+RS_0x7f507e9ad5f8/1/4 .resolv tri, RS_0x7f507e9ad5f8/0/16, RS_0x7f507e9ad5f8/0/20, RS_0x7f507e9ad5f8/0/24, RS_0x7f507e9ad5f8/0/28;
+RS_0x7f507e9ad5f8 .resolv tri, RS_0x7f507e9ad5f8/1/0, RS_0x7f507e9ad5f8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x28644d0_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9ad5f8; 32 drivers
+v0x2864580_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2864600_0 .net *"_s292", 0 0, L_0x2ad59d0; 1 drivers
+v0x28646a0_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers
+v0x2864740_0 .net *"_s296", 0 0, L_0x2abcfb0; 1 drivers
+v0x28647e0_0 .alias "carryin", 31 0, v0x295fa50_0;
+v0x2864880_0 .alias "carryout", 0 0, v0x2960870_0;
+v0x2864920_0 .alias "overflow", 0 0, v0x2960980_0;
+v0x28649c0_0 .alias "subtract", 31 0, v0x2960aa0_0;
+L_0x2aa88d0 .part/pv L_0x2aa8440, 1, 1, 32;
+L_0x2aa89e0 .part/pv L_0x2aa8790, 1, 1, 32;
+L_0x2aa8ad0 .part/pv L_0x2aa6f80, 1, 1, 32;
+L_0x2aa8bc0 .part v0x295fe90_0, 1, 1;
+L_0x2aa8c60 .part v0x2960190_0, 1, 1;
+L_0x2aa8d90 .part RS_0x7f507e9ad5f8, 0, 1;
+L_0x2aa9e10 .part/pv L_0x2aa9960, 2, 1, 32;
+L_0x2aa9f00 .part/pv L_0x2aa9cb0, 2, 1, 32;
+L_0x2aaa040 .part/pv L_0x2aa9690, 2, 1, 32;
+L_0x2aaa130 .part v0x295fe90_0, 2, 1;
+L_0x2aaa230 .part v0x2960190_0, 2, 1;
+L_0x2aaa360 .part RS_0x7f507e9ad5f8, 1, 1;
+L_0x2aab350 .part/pv L_0x2aaaea0, 3, 1, 32;
+L_0x2aab440 .part/pv L_0x2aab1f0, 3, 1, 32;
+L_0x2aab5b0 .part/pv L_0x2aaabd0, 3, 1, 32;
+L_0x2aab6a0 .part v0x295fe90_0, 3, 1;
+L_0x2aab7d0 .part v0x2960190_0, 3, 1;
+L_0x2aab900 .part RS_0x7f507e9ad5f8, 2, 1;
+L_0x2aac950 .part/pv L_0x2aac4a0, 4, 1, 32;
+L_0x2aaca40 .part/pv L_0x2aac7f0, 4, 1, 32;
+L_0x2aab9a0 .part/pv L_0x2aac1d0, 4, 1, 32;
+L_0x2aacc30 .part v0x295fe90_0, 4, 1;
+L_0x2aacb30 .part v0x2960190_0, 4, 1;
+L_0x2aace20 .part RS_0x7f507e9ad5f8, 3, 1;
+L_0x2aadef0 .part/pv L_0x2aada40, 5, 1, 32;
+L_0x2aadfe0 .part/pv L_0x2aadd90, 5, 1, 32;
+L_0x2aacfd0 .part/pv L_0x2aad770, 5, 1, 32;
+L_0x2aae200 .part v0x295fe90_0, 5, 1;
+L_0x2aae0d0 .part v0x2960190_0, 5, 1;
+L_0x2aae420 .part RS_0x7f507e9ad5f8, 4, 1;
+L_0x2aaf420 .part/pv L_0x2aaef50, 6, 1, 32;
+L_0x2aaf510 .part/pv L_0x2aaf2c0, 6, 1, 32;
+L_0x2aae4c0 .part/pv L_0x2aaec80, 6, 1, 32;
+L_0x2aaf710 .part v0x295fe90_0, 6, 1;
+L_0x2aaf600 .part v0x2960190_0, 6, 1;
+L_0x2aaf960 .part RS_0x7f507e9ad5f8, 5, 1;
+L_0x2ab0940 .part/pv L_0x2ab0490, 7, 1, 32;
+L_0x2ab0a30 .part/pv L_0x2ab07e0, 7, 1, 32;
+L_0x2aafa00 .part/pv L_0x2ab01c0, 7, 1, 32;
+L_0x2ab0c60 .part v0x295fe90_0, 7, 1;
+L_0x2ab0b20 .part v0x2960190_0, 7, 1;
+L_0x2ab0e50 .part RS_0x7f507e9ad5f8, 6, 1;
+L_0x2ab1e60 .part/pv L_0x2ab19b0, 8, 1, 32;
+L_0x2ab1f50 .part/pv L_0x2ab1d00, 8, 1, 32;
+L_0x2ab0ef0 .part/pv L_0x2ab16e0, 8, 1, 32;
+L_0x2ab21b0 .part v0x295fe90_0, 8, 1;
+L_0x2ab2040 .part v0x2960190_0, 8, 1;
+L_0x2ab23d0 .part RS_0x7f507e9ad5f8, 7, 1;
+L_0x2ab3470 .part/pv L_0x2ab2fc0, 9, 1, 32;
+L_0x2ab3560 .part/pv L_0x2ab3310, 9, 1, 32;
+L_0x2ab2680 .part/pv L_0x2ab2cf0, 9, 1, 32;
+L_0x2ab2770 .part v0x295fe90_0, 9, 1;
+L_0x2ab3800 .part v0x2960190_0, 9, 1;
+L_0x2ab3930 .part RS_0x7f507e9ad5f8, 8, 1;
+L_0x2ab4980 .part/pv L_0x2ab44d0, 10, 1, 32;
+L_0x2ab4a70 .part/pv L_0x2ab4820, 10, 1, 32;
+L_0x2ab39d0 .part/pv L_0x2ab4200, 10, 1, 32;
+L_0x2ab3ac0 .part v0x295fe90_0, 10, 1;
+L_0x2ab4d40 .part v0x2960190_0, 10, 1;
+L_0x2ab4e70 .part RS_0x7f507e9ad5f8, 9, 1;
+L_0x2ab5e90 .part/pv L_0x2ab59e0, 11, 1, 32;
+L_0x2ab5f80 .part/pv L_0x2ab5d30, 11, 1, 32;
+L_0x2ab4f10 .part/pv L_0x2ab5710, 11, 1, 32;
+L_0x2ab5000 .part v0x295fe90_0, 11, 1;
+L_0x2ab6280 .part v0x2960190_0, 11, 1;
+L_0x2ab63b0 .part RS_0x7f507e9ad5f8, 10, 1;
+L_0x2ab73a0 .part/pv L_0x2ab6ef0, 12, 1, 32;
+L_0x2ab7490 .part/pv L_0x2ab7240, 12, 1, 32;
+L_0x2ab6450 .part/pv L_0x2ab6c20, 12, 1, 32;
+L_0x2ab6540 .part v0x295fe90_0, 12, 1;
+L_0x2ab77c0 .part v0x2960190_0, 12, 1;
+L_0x2ab7860 .part RS_0x7f507e9ad5f8, 11, 1;
+L_0x2ab88a0 .part/pv L_0x2ab83f0, 13, 1, 32;
+L_0x2ab8990 .part/pv L_0x2ab8740, 13, 1, 32;
+L_0x2ab7900 .part/pv L_0x2ab8120, 13, 1, 32;
+L_0x2ab79f0 .part v0x295fe90_0, 13, 1;
+L_0x2ab7a90 .part v0x2960190_0, 13, 1;
+L_0x2ab8d80 .part RS_0x7f507e9ad5f8, 12, 1;
+L_0x2ab9db0 .part/pv L_0x2ab9900, 14, 1, 32;
+L_0x2ab9ea0 .part/pv L_0x2ab9c50, 14, 1, 32;
+L_0x2ab8e20 .part/pv L_0x2ab9630, 14, 1, 32;
+L_0x2ab8f10 .part v0x295fe90_0, 14, 1;
+L_0x2ab8fb0 .part v0x2960190_0, 14, 1;
+L_0x2aba2c0 .part RS_0x7f507e9ad5f8, 13, 1;
+L_0x2abb2c0 .part/pv L_0x2abae10, 15, 1, 32;
+L_0x2abb3b0 .part/pv L_0x2abb160, 15, 1, 32;
+L_0x2aba360 .part/pv L_0x2abab40, 15, 1, 32;
+L_0x2aba450 .part v0x295fe90_0, 15, 1;
+L_0x2aba4f0 .part v0x2960190_0, 15, 1;
+L_0x2abb800 .part RS_0x7f507e9ad5f8, 14, 1;
+L_0x2abc6f0 .part/pv L_0x2abc260, 16, 1, 32;
+L_0x2abc7e0 .part/pv L_0x2abc5b0, 16, 1, 32;
+L_0x2abb8a0 .part/pv L_0x2aaa490, 16, 1, 32;
+L_0x2abb990 .part v0x295fe90_0, 16, 1;
+L_0x2abba30 .part v0x2960190_0, 16, 1;
+L_0x2abcbd0 .part RS_0x7f507e9ad5f8, 15, 1;
+L_0x2abddb0 .part/pv L_0x2abd920, 17, 1, 32;
+L_0x2abdea0 .part/pv L_0x2abdc70, 17, 1, 32;
+L_0x2abd080 .part/pv L_0x2abd650, 17, 1, 32;
+L_0x2abd170 .part v0x295fe90_0, 17, 1;
+L_0x2abd210 .part v0x2960190_0, 17, 1;
+L_0x2abe2c0 .part RS_0x7f507e9ad5f8, 16, 1;
+L_0x2abf220 .part/pv L_0x2abed90, 18, 1, 32;
+L_0x2abf310 .part/pv L_0x2abf0e0, 18, 1, 32;
+L_0x2abe360 .part/pv L_0x2abeac0, 18, 1, 32;
+L_0x2abe450 .part v0x295fe90_0, 18, 1;
+L_0x2abe4f0 .part v0x2960190_0, 18, 1;
+L_0x2abf760 .part RS_0x7f507e9ad5f8, 17, 1;
+L_0x2ac06d0 .part/pv L_0x2ac0240, 19, 1, 32;
+L_0x2ac07c0 .part/pv L_0x2ac0590, 19, 1, 32;
+L_0x2abf800 .part/pv L_0x2abff70, 19, 1, 32;
+L_0x2abf8f0 .part v0x295fe90_0, 19, 1;
+L_0x2abf990 .part v0x2960190_0, 19, 1;
+L_0x2abfac0 .part RS_0x7f507e9ad5f8, 18, 1;
+L_0x2ac1aa0 .part/pv L_0x2ac1610, 20, 1, 32;
+L_0x2ac1b90 .part/pv L_0x2ac1960, 20, 1, 32;
+L_0x2ac08b0 .part/pv L_0x2ac1340, 20, 1, 32;
+L_0x2ac09a0 .part v0x295fe90_0, 20, 1;
+L_0x2ac0a40 .part v0x2960190_0, 20, 1;
+L_0x2ac0b70 .part RS_0x7f507e9ad5f8, 19, 1;
+L_0x2ac2e60 .part/pv L_0x2ac29d0, 21, 1, 32;
+L_0x2ac2f50 .part/pv L_0x2ac2d20, 21, 1, 32;
+L_0x2ac1c80 .part/pv L_0x2ac2700, 21, 1, 32;
+L_0x2ac1d70 .part v0x295fe90_0, 21, 1;
+L_0x2ac1e10 .part v0x2960190_0, 21, 1;
+L_0x2ac1f40 .part RS_0x7f507e9ad5f8, 20, 1;
+L_0x2ac4370 .part/pv L_0x2ac3ec0, 22, 1, 32;
+L_0x2ac4460 .part/pv L_0x2ac4210, 22, 1, 32;
+L_0x2ac3040 .part/pv L_0x2ac3bf0, 22, 1, 32;
+L_0x2ac3130 .part v0x295fe90_0, 22, 1;
+L_0x2ac31d0 .part v0x2960190_0, 22, 1;
+L_0x2ac3300 .part RS_0x7f507e9ad5f8, 21, 1;
+L_0x2ac5730 .part/pv L_0x2ac52a0, 23, 1, 32;
+L_0x2ac5820 .part/pv L_0x2ac55f0, 23, 1, 32;
+L_0x2ac4550 .part/pv L_0x2ac4fd0, 23, 1, 32;
+L_0x2ac4640 .part v0x295fe90_0, 23, 1;
+L_0x2ac46e0 .part v0x2960190_0, 23, 1;
+L_0x2ac4810 .part RS_0x7f507e9ad5f8, 22, 1;
+L_0x2ac6b70 .part/pv L_0x2ac66a0, 24, 1, 32;
+L_0x2ac6c60 .part/pv L_0x2ac6a10, 24, 1, 32;
+L_0x2ac5910 .part/pv L_0x2ac63d0, 24, 1, 32;
+L_0x2ac5a00 .part v0x295fe90_0, 24, 1;
+L_0x2ac5aa0 .part v0x2960190_0, 24, 1;
+L_0x2ac5bd0 .part RS_0x7f507e9ad5f8, 23, 1;
+L_0x2ac8830 .part/pv L_0x2ac8360, 25, 1, 32;
+L_0x2ac8920 .part/pv L_0x2ac86d0, 25, 1, 32;
+L_0x29c6c30 .part/pv L_0x2ac7050, 25, 1, 32;
+L_0x29c6d20 .part v0x295fe90_0, 25, 1;
+L_0x29c6dc0 .part v0x2960190_0, 25, 1;
+L_0x29c6ef0 .part RS_0x7f507e9ad5f8, 24, 1;
+L_0x2ac9d10 .part/pv L_0x2ac97e0, 26, 1, 32;
+L_0x2ac9e00 .part/pv L_0x2ac9bb0, 26, 1, 32;
+L_0x2ac8a10 .part/pv L_0x2ac9510, 26, 1, 32;
+L_0x2ac8b00 .part v0x295fe90_0, 26, 1;
+L_0x2ac8ba0 .part v0x2960190_0, 26, 1;
+L_0x2ac8cd0 .part RS_0x7f507e9ad5f8, 25, 1;
+L_0x2997ec0 .part/pv L_0x2997990, 27, 1, 32;
+L_0x2997fb0 .part/pv L_0x2997d60, 27, 1, 32;
+L_0x2ac9ef0 .part/pv L_0x2aca9f0, 27, 1, 32;
+L_0x2ac9fe0 .part v0x295fe90_0, 27, 1;
+L_0x2aca080 .part v0x2960190_0, 27, 1;
+L_0x2aca1b0 .part RS_0x7f507e9ad5f8, 26, 1;
+L_0x29993f0 .part/pv L_0x2998f40, 28, 1, 32;
+L_0x29994e0 .part/pv L_0x2999290, 28, 1, 32;
+L_0x29980a0 .part/pv L_0x2998c70, 28, 1, 32;
+L_0x2998190 .part v0x295fe90_0, 28, 1;
+L_0x2998230 .part v0x2960190_0, 28, 1;
+L_0x2998360 .part RS_0x7f507e9ad5f8, 27, 1;
+L_0x299a8d0 .part/pv L_0x299a420, 29, 1, 32;
+L_0x299a9c0 .part/pv L_0x299a770, 29, 1, 32;
+L_0x29995d0 .part/pv L_0x299a150, 29, 1, 32;
+L_0x29996c0 .part v0x295fe90_0, 29, 1;
+L_0x2999760 .part v0x2960190_0, 29, 1;
+L_0x2999890 .part RS_0x7f507e9ad5f8, 28, 1;
+L_0x2ad3100 .part/pv L_0x2ad2c70, 30, 1, 32;
+L_0x2ad31f0 .part/pv L_0x2ad2fc0, 30, 1, 32;
+L_0x299aab0 .part/pv L_0x299b660, 30, 1, 32;
+L_0x299aba0 .part v0x295fe90_0, 30, 1;
+L_0x299ac40 .part v0x2960190_0, 30, 1;
+L_0x299ad70 .part RS_0x7f507e9ad5f8, 29, 1;
+L_0x2ad4540 .part/pv L_0x2ad40b0, 31, 1, 32;
+L_0x2a36e10 .part/pv L_0x2ad4400, 31, 1, 32;
+L_0x2a374c0 .part/pv L_0x2ad3de0, 31, 1, 32;
+L_0x2ad32e0 .part v0x295fe90_0, 31, 1;
+L_0x2ad3380 .part v0x2960190_0, 31, 1;
+L_0x2ad34b0 .part RS_0x7f507e9ad5f8, 30, 1;
+L_0x2ad6280 .part/pv L_0x2ad5df0, 0, 1, 32;
+L_0x2ad6370 .part/pv L_0x2ad6140, 0, 1, 32;
+L_0x2ad55f0 .part/pv L_0x2a373e0, 0, 1, 32;
+L_0x2ad56e0 .part v0x295fe90_0, 0, 1;
+L_0x2ad5780 .part v0x2960190_0, 0, 1;
+L_0x2ad58b0 .part RS_0x7f507e9ad748, 0, 1;
+L_0x2ad59d0 .part RS_0x7f507e9ad5f8, 31, 1;
+L_0x2abcfb0 .part RS_0x7f507e9ad5f8, 30, 1;
+S_0x2863300 .scope module, "attempt2" "MiddleAddSubSLT" 3 278, 3 189, S_0x2840e20;
+ .timescale -9 -12;
+L_0x2ad3550/d .functor NOT 1, L_0x2ad5780, C4<0>, C4<0>, C4<0>;
+L_0x2ad3550 .delay (10000,10000,10000) L_0x2ad3550/d;
+L_0x2a37280/d .functor NOT 1, L_0x2a37340, C4<0>, C4<0>, C4<0>;
+L_0x2a37280 .delay (10000,10000,10000) L_0x2a37280/d;
+L_0x2a373e0/d .functor AND 1, L_0x2ad5c60, L_0x2a37280, C4<1>, C4<1>;
+L_0x2a373e0 .delay (20000,20000,20000) L_0x2a373e0/d;
+L_0x2ad5d00/d .functor XOR 1, L_0x2ad56e0, L_0x2a37010, C4<0>, C4<0>;
+L_0x2ad5d00 .delay (40000,40000,40000) L_0x2ad5d00/d;
+L_0x2ad5df0/d .functor XOR 1, L_0x2ad5d00, L_0x2ad58b0, C4<0>, C4<0>;
+L_0x2ad5df0 .delay (40000,40000,40000) L_0x2ad5df0/d;
+L_0x2ad5ee0/d .functor AND 1, L_0x2ad56e0, L_0x2a37010, C4<1>, C4<1>;
+L_0x2ad5ee0 .delay (20000,20000,20000) L_0x2ad5ee0/d;
+L_0x2ad6050/d .functor AND 1, L_0x2ad5d00, L_0x2ad58b0, C4<1>, C4<1>;
+L_0x2ad6050 .delay (20000,20000,20000) L_0x2ad6050/d;
+L_0x2ad6140/d .functor OR 1, L_0x2ad5ee0, L_0x2ad6050, C4<0>, C4<0>;
+L_0x2ad6140 .delay (20000,20000,20000) L_0x2ad6140/d;
+v0x2863970_0 .net "A", 0 0, L_0x2ad56e0; 1 drivers
+v0x2863a30_0 .net "AandB", 0 0, L_0x2ad5ee0; 1 drivers
+v0x2863ad0_0 .net "AddSubSLTSum", 0 0, L_0x2ad5df0; 1 drivers
+v0x2863b70_0 .net "AxorB", 0 0, L_0x2ad5d00; 1 drivers
+v0x2863bf0_0 .net "B", 0 0, L_0x2ad5780; 1 drivers
+v0x2863ca0_0 .net "BornB", 0 0, L_0x2a37010; 1 drivers
+v0x2863d60_0 .net "CINandAxorB", 0 0, L_0x2ad6050; 1 drivers
+v0x2863de0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2863e60_0 .net *"_s3", 0 0, L_0x2a37340; 1 drivers
+v0x2863ee0_0 .net *"_s5", 0 0, L_0x2ad5c60; 1 drivers
+v0x2863f80_0 .net "carryin", 0 0, L_0x2ad58b0; 1 drivers
+v0x2864020_0 .net "carryout", 0 0, L_0x2ad6140; 1 drivers
+v0x28640c0_0 .net "nB", 0 0, L_0x2ad3550; 1 drivers
+v0x2864170_0 .net "nCmd2", 0 0, L_0x2a37280; 1 drivers
+v0x2864270_0 .net "subtract", 0 0, L_0x2a373e0; 1 drivers
+L_0x2a371e0 .part v0x2960210_0, 0, 1;
+L_0x2a37340 .part v0x2960210_0, 2, 1;
+L_0x2ad5c60 .part v0x2960210_0, 0, 1;
+S_0x28633f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2863300;
+ .timescale -9 -12;
+L_0x2ad3690/d .functor NOT 1, L_0x2a371e0, C4<0>, C4<0>, C4<0>;
+L_0x2ad3690 .delay (10000,10000,10000) L_0x2ad3690/d;
+L_0x2ad3750/d .functor AND 1, L_0x2ad5780, L_0x2ad3690, C4<1>, C4<1>;
+L_0x2ad3750 .delay (20000,20000,20000) L_0x2ad3750/d;
+L_0x2a36f00/d .functor AND 1, L_0x2ad3550, L_0x2a371e0, C4<1>, C4<1>;
+L_0x2a36f00 .delay (20000,20000,20000) L_0x2a36f00/d;
+L_0x2a37010/d .functor OR 1, L_0x2ad3750, L_0x2a36f00, C4<0>, C4<0>;
+L_0x2a37010 .delay (20000,20000,20000) L_0x2a37010/d;
+v0x28634e0_0 .net "S", 0 0, L_0x2a371e0; 1 drivers
+v0x28635a0_0 .alias "in0", 0 0, v0x2863bf0_0;
+v0x2863640_0 .alias "in1", 0 0, v0x28640c0_0;
+v0x28636e0_0 .net "nS", 0 0, L_0x2ad3690; 1 drivers
+v0x2863790_0 .net "out0", 0 0, L_0x2ad3750; 1 drivers
+v0x2863830_0 .net "out1", 0 0, L_0x2a36f00; 1 drivers
+v0x28638d0_0 .alias "outfinal", 0 0, v0x2863ca0_0;
+S_0x2862160 .scope generate, "addbits[1]" "addbits[1]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2861b78 .param/l "i" 3 283, +C4<01>;
+S_0x28622d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2862160;
+ .timescale -9 -12;
+L_0x2aa6700/d .functor NOT 1, L_0x2aa8c60, C4<0>, C4<0>, C4<0>;
+L_0x2aa6700 .delay (10000,10000,10000) L_0x2aa6700/d;
+L_0x2aa6e20/d .functor NOT 1, L_0x2aa6ee0, C4<0>, C4<0>, C4<0>;
+L_0x2aa6e20 .delay (10000,10000,10000) L_0x2aa6e20/d;
+L_0x2aa6f80/d .functor AND 1, L_0x2aa70c0, L_0x2aa6e20, C4<1>, C4<1>;
+L_0x2aa6f80 .delay (20000,20000,20000) L_0x2aa6f80/d;
+L_0x2aa7160/d .functor XOR 1, L_0x2aa8bc0, L_0x2aa6bb0, C4<0>, C4<0>;
+L_0x2aa7160 .delay (40000,40000,40000) L_0x2aa7160/d;
+L_0x2aa8440/d .functor XOR 1, L_0x2aa7160, L_0x2aa8d90, C4<0>, C4<0>;
+L_0x2aa8440 .delay (40000,40000,40000) L_0x2aa8440/d;
+L_0x2aa8530/d .functor AND 1, L_0x2aa8bc0, L_0x2aa6bb0, C4<1>, C4<1>;
+L_0x2aa8530 .delay (20000,20000,20000) L_0x2aa8530/d;
+L_0x2aa86a0/d .functor AND 1, L_0x2aa7160, L_0x2aa8d90, C4<1>, C4<1>;
+L_0x2aa86a0 .delay (20000,20000,20000) L_0x2aa86a0/d;
+L_0x2aa8790/d .functor OR 1, L_0x2aa8530, L_0x2aa86a0, C4<0>, C4<0>;
+L_0x2aa8790 .delay (20000,20000,20000) L_0x2aa8790/d;
+v0x2862960_0 .net "A", 0 0, L_0x2aa8bc0; 1 drivers
+v0x2862a20_0 .net "AandB", 0 0, L_0x2aa8530; 1 drivers
+v0x2862ac0_0 .net "AddSubSLTSum", 0 0, L_0x2aa8440; 1 drivers
+v0x2862b60_0 .net "AxorB", 0 0, L_0x2aa7160; 1 drivers
+v0x2862be0_0 .net "B", 0 0, L_0x2aa8c60; 1 drivers
+v0x2862c90_0 .net "BornB", 0 0, L_0x2aa6bb0; 1 drivers
+v0x2862d50_0 .net "CINandAxorB", 0 0, L_0x2aa86a0; 1 drivers
+v0x2862dd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2862e50_0 .net *"_s3", 0 0, L_0x2aa6ee0; 1 drivers
+v0x2862ed0_0 .net *"_s5", 0 0, L_0x2aa70c0; 1 drivers
+v0x2862f70_0 .net "carryin", 0 0, L_0x2aa8d90; 1 drivers
+v0x2863010_0 .net "carryout", 0 0, L_0x2aa8790; 1 drivers
+v0x28630b0_0 .net "nB", 0 0, L_0x2aa6700; 1 drivers
+v0x2863160_0 .net "nCmd2", 0 0, L_0x2aa6e20; 1 drivers
+v0x2863260_0 .net "subtract", 0 0, L_0x2aa6f80; 1 drivers
+L_0x2aa6d80 .part v0x2960210_0, 0, 1;
+L_0x2aa6ee0 .part v0x2960210_0, 2, 1;
+L_0x2aa70c0 .part v0x2960210_0, 0, 1;
+S_0x28623c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28622d0;
+ .timescale -9 -12;
+L_0x2aa68d0/d .functor NOT 1, L_0x2aa6d80, C4<0>, C4<0>, C4<0>;
+L_0x2aa68d0 .delay (10000,10000,10000) L_0x2aa68d0/d;
+L_0x2aa6990/d .functor AND 1, L_0x2aa8c60, L_0x2aa68d0, C4<1>, C4<1>;
+L_0x2aa6990 .delay (20000,20000,20000) L_0x2aa6990/d;
+L_0x2aa6aa0/d .functor AND 1, L_0x2aa6700, L_0x2aa6d80, C4<1>, C4<1>;
+L_0x2aa6aa0 .delay (20000,20000,20000) L_0x2aa6aa0/d;
+L_0x2aa6bb0/d .functor OR 1, L_0x2aa6990, L_0x2aa6aa0, C4<0>, C4<0>;
+L_0x2aa6bb0 .delay (20000,20000,20000) L_0x2aa6bb0/d;
+v0x28624b0_0 .net "S", 0 0, L_0x2aa6d80; 1 drivers
+v0x2862550_0 .alias "in0", 0 0, v0x2862be0_0;
+v0x28625f0_0 .alias "in1", 0 0, v0x28630b0_0;
+v0x2862690_0 .net "nS", 0 0, L_0x2aa68d0; 1 drivers
+v0x2862740_0 .net "out0", 0 0, L_0x2aa6990; 1 drivers
+v0x28627e0_0 .net "out1", 0 0, L_0x2aa6aa0; 1 drivers
+v0x28628c0_0 .alias "outfinal", 0 0, v0x2862c90_0;
+S_0x2860fc0 .scope generate, "addbits[2]" "addbits[2]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28609d8 .param/l "i" 3 283, +C4<010>;
+S_0x2861130 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2860fc0;
+ .timescale -9 -12;
+L_0x2aa8e30/d .functor NOT 1, L_0x2aaa230, C4<0>, C4<0>, C4<0>;
+L_0x2aa8e30 .delay (10000,10000,10000) L_0x2aa8e30/d;
+L_0x2aa9530/d .functor NOT 1, L_0x2aa95f0, C4<0>, C4<0>, C4<0>;
+L_0x2aa9530 .delay (10000,10000,10000) L_0x2aa9530/d;
+L_0x2aa9690/d .functor AND 1, L_0x2aa97d0, L_0x2aa9530, C4<1>, C4<1>;
+L_0x2aa9690 .delay (20000,20000,20000) L_0x2aa9690/d;
+L_0x2aa9870/d .functor XOR 1, L_0x2aaa130, L_0x2aa92c0, C4<0>, C4<0>;
+L_0x2aa9870 .delay (40000,40000,40000) L_0x2aa9870/d;
+L_0x2aa9960/d .functor XOR 1, L_0x2aa9870, L_0x2aaa360, C4<0>, C4<0>;
+L_0x2aa9960 .delay (40000,40000,40000) L_0x2aa9960/d;
+L_0x2aa9a50/d .functor AND 1, L_0x2aaa130, L_0x2aa92c0, C4<1>, C4<1>;
+L_0x2aa9a50 .delay (20000,20000,20000) L_0x2aa9a50/d;
+L_0x2aa9bc0/d .functor AND 1, L_0x2aa9870, L_0x2aaa360, C4<1>, C4<1>;
+L_0x2aa9bc0 .delay (20000,20000,20000) L_0x2aa9bc0/d;
+L_0x2aa9cb0/d .functor OR 1, L_0x2aa9a50, L_0x2aa9bc0, C4<0>, C4<0>;
+L_0x2aa9cb0 .delay (20000,20000,20000) L_0x2aa9cb0/d;
+v0x28617c0_0 .net "A", 0 0, L_0x2aaa130; 1 drivers
+v0x2861880_0 .net "AandB", 0 0, L_0x2aa9a50; 1 drivers
+v0x2861920_0 .net "AddSubSLTSum", 0 0, L_0x2aa9960; 1 drivers
+v0x28619c0_0 .net "AxorB", 0 0, L_0x2aa9870; 1 drivers
+v0x2861a40_0 .net "B", 0 0, L_0x2aaa230; 1 drivers
+v0x2861af0_0 .net "BornB", 0 0, L_0x2aa92c0; 1 drivers
+v0x2861bb0_0 .net "CINandAxorB", 0 0, L_0x2aa9bc0; 1 drivers
+v0x2861c30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2861cb0_0 .net *"_s3", 0 0, L_0x2aa95f0; 1 drivers
+v0x2861d30_0 .net *"_s5", 0 0, L_0x2aa97d0; 1 drivers
+v0x2861dd0_0 .net "carryin", 0 0, L_0x2aaa360; 1 drivers
+v0x2861e70_0 .net "carryout", 0 0, L_0x2aa9cb0; 1 drivers
+v0x2861f10_0 .net "nB", 0 0, L_0x2aa8e30; 1 drivers
+v0x2861fc0_0 .net "nCmd2", 0 0, L_0x2aa9530; 1 drivers
+v0x28620c0_0 .net "subtract", 0 0, L_0x2aa9690; 1 drivers
+L_0x2aa9490 .part v0x2960210_0, 0, 1;
+L_0x2aa95f0 .part v0x2960210_0, 2, 1;
+L_0x2aa97d0 .part v0x2960210_0, 0, 1;
+S_0x2861220 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2861130;
+ .timescale -9 -12;
+L_0x2aa8fe0/d .functor NOT 1, L_0x2aa9490, C4<0>, C4<0>, C4<0>;
+L_0x2aa8fe0 .delay (10000,10000,10000) L_0x2aa8fe0/d;
+L_0x2aa90a0/d .functor AND 1, L_0x2aaa230, L_0x2aa8fe0, C4<1>, C4<1>;
+L_0x2aa90a0 .delay (20000,20000,20000) L_0x2aa90a0/d;
+L_0x2aa91b0/d .functor AND 1, L_0x2aa8e30, L_0x2aa9490, C4<1>, C4<1>;
+L_0x2aa91b0 .delay (20000,20000,20000) L_0x2aa91b0/d;
+L_0x2aa92c0/d .functor OR 1, L_0x2aa90a0, L_0x2aa91b0, C4<0>, C4<0>;
+L_0x2aa92c0 .delay (20000,20000,20000) L_0x2aa92c0/d;
+v0x2861310_0 .net "S", 0 0, L_0x2aa9490; 1 drivers
+v0x28613b0_0 .alias "in0", 0 0, v0x2861a40_0;
+v0x2861450_0 .alias "in1", 0 0, v0x2861f10_0;
+v0x28614f0_0 .net "nS", 0 0, L_0x2aa8fe0; 1 drivers
+v0x28615a0_0 .net "out0", 0 0, L_0x2aa90a0; 1 drivers
+v0x2861640_0 .net "out1", 0 0, L_0x2aa91b0; 1 drivers
+v0x2861720_0 .alias "outfinal", 0 0, v0x2861af0_0;
+S_0x285fe20 .scope generate, "addbits[3]" "addbits[3]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x285f838 .param/l "i" 3 283, +C4<011>;
+S_0x285ff90 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285fe20;
+ .timescale -9 -12;
+L_0x2aaa1d0/d .functor NOT 1, L_0x2aab7d0, C4<0>, C4<0>, C4<0>;
+L_0x2aaa1d0 .delay (10000,10000,10000) L_0x2aaa1d0/d;
+L_0x2aaaa70/d .functor NOT 1, L_0x2aaab30, C4<0>, C4<0>, C4<0>;
+L_0x2aaaa70 .delay (10000,10000,10000) L_0x2aaaa70/d;
+L_0x2aaabd0/d .functor AND 1, L_0x2aaad10, L_0x2aaaa70, C4<1>, C4<1>;
+L_0x2aaabd0 .delay (20000,20000,20000) L_0x2aaabd0/d;
+L_0x2aaadb0/d .functor XOR 1, L_0x2aab6a0, L_0x2aaa800, C4<0>, C4<0>;
+L_0x2aaadb0 .delay (40000,40000,40000) L_0x2aaadb0/d;
+L_0x2aaaea0/d .functor XOR 1, L_0x2aaadb0, L_0x2aab900, C4<0>, C4<0>;
+L_0x2aaaea0 .delay (40000,40000,40000) L_0x2aaaea0/d;
+L_0x2aaaf90/d .functor AND 1, L_0x2aab6a0, L_0x2aaa800, C4<1>, C4<1>;
+L_0x2aaaf90 .delay (20000,20000,20000) L_0x2aaaf90/d;
+L_0x2aab100/d .functor AND 1, L_0x2aaadb0, L_0x2aab900, C4<1>, C4<1>;
+L_0x2aab100 .delay (20000,20000,20000) L_0x2aab100/d;
+L_0x2aab1f0/d .functor OR 1, L_0x2aaaf90, L_0x2aab100, C4<0>, C4<0>;
+L_0x2aab1f0 .delay (20000,20000,20000) L_0x2aab1f0/d;
+v0x2860620_0 .net "A", 0 0, L_0x2aab6a0; 1 drivers
+v0x28606e0_0 .net "AandB", 0 0, L_0x2aaaf90; 1 drivers
+v0x2860780_0 .net "AddSubSLTSum", 0 0, L_0x2aaaea0; 1 drivers
+v0x2860820_0 .net "AxorB", 0 0, L_0x2aaadb0; 1 drivers
+v0x28608a0_0 .net "B", 0 0, L_0x2aab7d0; 1 drivers
+v0x2860950_0 .net "BornB", 0 0, L_0x2aaa800; 1 drivers
+v0x2860a10_0 .net "CINandAxorB", 0 0, L_0x2aab100; 1 drivers
+v0x2860a90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2860b10_0 .net *"_s3", 0 0, L_0x2aaab30; 1 drivers
+v0x2860b90_0 .net *"_s5", 0 0, L_0x2aaad10; 1 drivers
+v0x2860c30_0 .net "carryin", 0 0, L_0x2aab900; 1 drivers
+v0x2860cd0_0 .net "carryout", 0 0, L_0x2aab1f0; 1 drivers
+v0x2860d70_0 .net "nB", 0 0, L_0x2aaa1d0; 1 drivers
+v0x2860e20_0 .net "nCmd2", 0 0, L_0x2aaaa70; 1 drivers
+v0x2860f20_0 .net "subtract", 0 0, L_0x2aaabd0; 1 drivers
+L_0x2aaa9d0 .part v0x2960210_0, 0, 1;
+L_0x2aaab30 .part v0x2960210_0, 2, 1;
+L_0x2aaad10 .part v0x2960210_0, 0, 1;
+S_0x2860080 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285ff90;
+ .timescale -9 -12;
+L_0x2aaa560/d .functor NOT 1, L_0x2aaa9d0, C4<0>, C4<0>, C4<0>;
+L_0x2aaa560 .delay (10000,10000,10000) L_0x2aaa560/d;
+L_0x2aaa5e0/d .functor AND 1, L_0x2aab7d0, L_0x2aaa560, C4<1>, C4<1>;
+L_0x2aaa5e0 .delay (20000,20000,20000) L_0x2aaa5e0/d;
+L_0x2aaa6f0/d .functor AND 1, L_0x2aaa1d0, L_0x2aaa9d0, C4<1>, C4<1>;
+L_0x2aaa6f0 .delay (20000,20000,20000) L_0x2aaa6f0/d;
+L_0x2aaa800/d .functor OR 1, L_0x2aaa5e0, L_0x2aaa6f0, C4<0>, C4<0>;
+L_0x2aaa800 .delay (20000,20000,20000) L_0x2aaa800/d;
+v0x2860170_0 .net "S", 0 0, L_0x2aaa9d0; 1 drivers
+v0x2860210_0 .alias "in0", 0 0, v0x28608a0_0;
+v0x28602b0_0 .alias "in1", 0 0, v0x2860d70_0;
+v0x2860350_0 .net "nS", 0 0, L_0x2aaa560; 1 drivers
+v0x2860400_0 .net "out0", 0 0, L_0x2aaa5e0; 1 drivers
+v0x28604a0_0 .net "out1", 0 0, L_0x2aaa6f0; 1 drivers
+v0x2860580_0 .alias "outfinal", 0 0, v0x2860950_0;
+S_0x285ec80 .scope generate, "addbits[4]" "addbits[4]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x285e698 .param/l "i" 3 283, +C4<0100>;
+S_0x285edf0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285ec80;
+ .timescale -9 -12;
+L_0x2aab740/d .functor NOT 1, L_0x2aacb30, C4<0>, C4<0>, C4<0>;
+L_0x2aab740 .delay (10000,10000,10000) L_0x2aab740/d;
+L_0x2aac070/d .functor NOT 1, L_0x2aac130, C4<0>, C4<0>, C4<0>;
+L_0x2aac070 .delay (10000,10000,10000) L_0x2aac070/d;
+L_0x2aac1d0/d .functor AND 1, L_0x2aac310, L_0x2aac070, C4<1>, C4<1>;
+L_0x2aac1d0 .delay (20000,20000,20000) L_0x2aac1d0/d;
+L_0x2aac3b0/d .functor XOR 1, L_0x2aacc30, L_0x2aabe00, C4<0>, C4<0>;
+L_0x2aac3b0 .delay (40000,40000,40000) L_0x2aac3b0/d;
+L_0x2aac4a0/d .functor XOR 1, L_0x2aac3b0, L_0x2aace20, C4<0>, C4<0>;
+L_0x2aac4a0 .delay (40000,40000,40000) L_0x2aac4a0/d;
+L_0x2aac590/d .functor AND 1, L_0x2aacc30, L_0x2aabe00, C4<1>, C4<1>;
+L_0x2aac590 .delay (20000,20000,20000) L_0x2aac590/d;
+L_0x2aac700/d .functor AND 1, L_0x2aac3b0, L_0x2aace20, C4<1>, C4<1>;
+L_0x2aac700 .delay (20000,20000,20000) L_0x2aac700/d;
+L_0x2aac7f0/d .functor OR 1, L_0x2aac590, L_0x2aac700, C4<0>, C4<0>;
+L_0x2aac7f0 .delay (20000,20000,20000) L_0x2aac7f0/d;
+v0x285f480_0 .net "A", 0 0, L_0x2aacc30; 1 drivers
+v0x285f540_0 .net "AandB", 0 0, L_0x2aac590; 1 drivers
+v0x285f5e0_0 .net "AddSubSLTSum", 0 0, L_0x2aac4a0; 1 drivers
+v0x285f680_0 .net "AxorB", 0 0, L_0x2aac3b0; 1 drivers
+v0x285f700_0 .net "B", 0 0, L_0x2aacb30; 1 drivers
+v0x285f7b0_0 .net "BornB", 0 0, L_0x2aabe00; 1 drivers
+v0x285f870_0 .net "CINandAxorB", 0 0, L_0x2aac700; 1 drivers
+v0x285f8f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x285f970_0 .net *"_s3", 0 0, L_0x2aac130; 1 drivers
+v0x285f9f0_0 .net *"_s5", 0 0, L_0x2aac310; 1 drivers
+v0x285fa90_0 .net "carryin", 0 0, L_0x2aace20; 1 drivers
+v0x285fb30_0 .net "carryout", 0 0, L_0x2aac7f0; 1 drivers
+v0x285fbd0_0 .net "nB", 0 0, L_0x2aab740; 1 drivers
+v0x285fc80_0 .net "nCmd2", 0 0, L_0x2aac070; 1 drivers
+v0x285fd80_0 .net "subtract", 0 0, L_0x2aac1d0; 1 drivers
+L_0x2aabfd0 .part v0x2960210_0, 0, 1;
+L_0x2aac130 .part v0x2960210_0, 2, 1;
+L_0x2aac310 .part v0x2960210_0, 0, 1;
+S_0x285eee0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285edf0;
+ .timescale -9 -12;
+L_0x2aabb20/d .functor NOT 1, L_0x2aabfd0, C4<0>, C4<0>, C4<0>;
+L_0x2aabb20 .delay (10000,10000,10000) L_0x2aabb20/d;
+L_0x2aabbe0/d .functor AND 1, L_0x2aacb30, L_0x2aabb20, C4<1>, C4<1>;
+L_0x2aabbe0 .delay (20000,20000,20000) L_0x2aabbe0/d;
+L_0x2aabcf0/d .functor AND 1, L_0x2aab740, L_0x2aabfd0, C4<1>, C4<1>;
+L_0x2aabcf0 .delay (20000,20000,20000) L_0x2aabcf0/d;
+L_0x2aabe00/d .functor OR 1, L_0x2aabbe0, L_0x2aabcf0, C4<0>, C4<0>;
+L_0x2aabe00 .delay (20000,20000,20000) L_0x2aabe00/d;
+v0x285efd0_0 .net "S", 0 0, L_0x2aabfd0; 1 drivers
+v0x285f070_0 .alias "in0", 0 0, v0x285f700_0;
+v0x285f110_0 .alias "in1", 0 0, v0x285fbd0_0;
+v0x285f1b0_0 .net "nS", 0 0, L_0x2aabb20; 1 drivers
+v0x285f260_0 .net "out0", 0 0, L_0x2aabbe0; 1 drivers
+v0x285f300_0 .net "out1", 0 0, L_0x2aabcf0; 1 drivers
+v0x285f3e0_0 .alias "outfinal", 0 0, v0x285f7b0_0;
+S_0x285dae0 .scope generate, "addbits[5]" "addbits[5]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x285d4f8 .param/l "i" 3 283, +C4<0101>;
+S_0x285dc50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285dae0;
+ .timescale -9 -12;
+L_0x2aaa400/d .functor NOT 1, L_0x2aae0d0, C4<0>, C4<0>, C4<0>;
+L_0x2aaa400 .delay (10000,10000,10000) L_0x2aaa400/d;
+L_0x2aad610/d .functor NOT 1, L_0x2aad6d0, C4<0>, C4<0>, C4<0>;
+L_0x2aad610 .delay (10000,10000,10000) L_0x2aad610/d;
+L_0x2aad770/d .functor AND 1, L_0x2aad8b0, L_0x2aad610, C4<1>, C4<1>;
+L_0x2aad770 .delay (20000,20000,20000) L_0x2aad770/d;
+L_0x2aad950/d .functor XOR 1, L_0x2aae200, L_0x2aad3a0, C4<0>, C4<0>;
+L_0x2aad950 .delay (40000,40000,40000) L_0x2aad950/d;
+L_0x2aada40/d .functor XOR 1, L_0x2aad950, L_0x2aae420, C4<0>, C4<0>;
+L_0x2aada40 .delay (40000,40000,40000) L_0x2aada40/d;
+L_0x2aadb30/d .functor AND 1, L_0x2aae200, L_0x2aad3a0, C4<1>, C4<1>;
+L_0x2aadb30 .delay (20000,20000,20000) L_0x2aadb30/d;
+L_0x2aadca0/d .functor AND 1, L_0x2aad950, L_0x2aae420, C4<1>, C4<1>;
+L_0x2aadca0 .delay (20000,20000,20000) L_0x2aadca0/d;
+L_0x2aadd90/d .functor OR 1, L_0x2aadb30, L_0x2aadca0, C4<0>, C4<0>;
+L_0x2aadd90 .delay (20000,20000,20000) L_0x2aadd90/d;
+v0x285e2e0_0 .net "A", 0 0, L_0x2aae200; 1 drivers
+v0x285e3a0_0 .net "AandB", 0 0, L_0x2aadb30; 1 drivers
+v0x285e440_0 .net "AddSubSLTSum", 0 0, L_0x2aada40; 1 drivers
+v0x285e4e0_0 .net "AxorB", 0 0, L_0x2aad950; 1 drivers
+v0x285e560_0 .net "B", 0 0, L_0x2aae0d0; 1 drivers
+v0x285e610_0 .net "BornB", 0 0, L_0x2aad3a0; 1 drivers
+v0x285e6d0_0 .net "CINandAxorB", 0 0, L_0x2aadca0; 1 drivers
+v0x285e750_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x285e7d0_0 .net *"_s3", 0 0, L_0x2aad6d0; 1 drivers
+v0x285e850_0 .net *"_s5", 0 0, L_0x2aad8b0; 1 drivers
+v0x285e8f0_0 .net "carryin", 0 0, L_0x2aae420; 1 drivers
+v0x285e990_0 .net "carryout", 0 0, L_0x2aadd90; 1 drivers
+v0x285ea30_0 .net "nB", 0 0, L_0x2aaa400; 1 drivers
+v0x285eae0_0 .net "nCmd2", 0 0, L_0x2aad610; 1 drivers
+v0x285ebe0_0 .net "subtract", 0 0, L_0x2aad770; 1 drivers
+L_0x2aad570 .part v0x2960210_0, 0, 1;
+L_0x2aad6d0 .part v0x2960210_0, 2, 1;
+L_0x2aad8b0 .part v0x2960210_0, 0, 1;
+S_0x285dd40 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285dc50;
+ .timescale -9 -12;
+L_0x2aad0c0/d .functor NOT 1, L_0x2aad570, C4<0>, C4<0>, C4<0>;
+L_0x2aad0c0 .delay (10000,10000,10000) L_0x2aad0c0/d;
+L_0x2aad180/d .functor AND 1, L_0x2aae0d0, L_0x2aad0c0, C4<1>, C4<1>;
+L_0x2aad180 .delay (20000,20000,20000) L_0x2aad180/d;
+L_0x2aad290/d .functor AND 1, L_0x2aaa400, L_0x2aad570, C4<1>, C4<1>;
+L_0x2aad290 .delay (20000,20000,20000) L_0x2aad290/d;
+L_0x2aad3a0/d .functor OR 1, L_0x2aad180, L_0x2aad290, C4<0>, C4<0>;
+L_0x2aad3a0 .delay (20000,20000,20000) L_0x2aad3a0/d;
+v0x285de30_0 .net "S", 0 0, L_0x2aad570; 1 drivers
+v0x285ded0_0 .alias "in0", 0 0, v0x285e560_0;
+v0x285df70_0 .alias "in1", 0 0, v0x285ea30_0;
+v0x285e010_0 .net "nS", 0 0, L_0x2aad0c0; 1 drivers
+v0x285e0c0_0 .net "out0", 0 0, L_0x2aad180; 1 drivers
+v0x285e160_0 .net "out1", 0 0, L_0x2aad290; 1 drivers
+v0x285e240_0 .alias "outfinal", 0 0, v0x285e610_0;
+S_0x285c940 .scope generate, "addbits[6]" "addbits[6]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x285c358 .param/l "i" 3 283, +C4<0110>;
+S_0x285cab0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285c940;
+ .timescale -9 -12;
+L_0x2aae2a0/d .functor NOT 1, L_0x2aaf600, C4<0>, C4<0>, C4<0>;
+L_0x2aae2a0 .delay (10000,10000,10000) L_0x2aae2a0/d;
+L_0x2aaeb20/d .functor NOT 1, L_0x2aaebe0, C4<0>, C4<0>, C4<0>;
+L_0x2aaeb20 .delay (10000,10000,10000) L_0x2aaeb20/d;
+L_0x2aaec80/d .functor AND 1, L_0x2aaedc0, L_0x2aaeb20, C4<1>, C4<1>;
+L_0x2aaec80 .delay (20000,20000,20000) L_0x2aaec80/d;
+L_0x2aaee60/d .functor XOR 1, L_0x2aaf710, L_0x2aae8b0, C4<0>, C4<0>;
+L_0x2aaee60 .delay (40000,40000,40000) L_0x2aaee60/d;
+L_0x2aaef50/d .functor XOR 1, L_0x2aaee60, L_0x2aaf960, C4<0>, C4<0>;
+L_0x2aaef50 .delay (40000,40000,40000) L_0x2aaef50/d;
+L_0x2aaf040/d .functor AND 1, L_0x2aaf710, L_0x2aae8b0, C4<1>, C4<1>;
+L_0x2aaf040 .delay (20000,20000,20000) L_0x2aaf040/d;
+L_0x2aaf1b0/d .functor AND 1, L_0x2aaee60, L_0x2aaf960, C4<1>, C4<1>;
+L_0x2aaf1b0 .delay (20000,20000,20000) L_0x2aaf1b0/d;
+L_0x2aaf2c0/d .functor OR 1, L_0x2aaf040, L_0x2aaf1b0, C4<0>, C4<0>;
+L_0x2aaf2c0 .delay (20000,20000,20000) L_0x2aaf2c0/d;
+v0x285d140_0 .net "A", 0 0, L_0x2aaf710; 1 drivers
+v0x285d200_0 .net "AandB", 0 0, L_0x2aaf040; 1 drivers
+v0x285d2a0_0 .net "AddSubSLTSum", 0 0, L_0x2aaef50; 1 drivers
+v0x285d340_0 .net "AxorB", 0 0, L_0x2aaee60; 1 drivers
+v0x285d3c0_0 .net "B", 0 0, L_0x2aaf600; 1 drivers
+v0x285d470_0 .net "BornB", 0 0, L_0x2aae8b0; 1 drivers
+v0x285d530_0 .net "CINandAxorB", 0 0, L_0x2aaf1b0; 1 drivers
+v0x285d5b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x285d630_0 .net *"_s3", 0 0, L_0x2aaebe0; 1 drivers
+v0x285d6b0_0 .net *"_s5", 0 0, L_0x2aaedc0; 1 drivers
+v0x285d750_0 .net "carryin", 0 0, L_0x2aaf960; 1 drivers
+v0x285d7f0_0 .net "carryout", 0 0, L_0x2aaf2c0; 1 drivers
+v0x285d890_0 .net "nB", 0 0, L_0x2aae2a0; 1 drivers
+v0x285d940_0 .net "nCmd2", 0 0, L_0x2aaeb20; 1 drivers
+v0x285da40_0 .net "subtract", 0 0, L_0x2aaec80; 1 drivers
+L_0x2aaea80 .part v0x2960210_0, 0, 1;
+L_0x2aaebe0 .part v0x2960210_0, 2, 1;
+L_0x2aaedc0 .part v0x2960210_0, 0, 1;
+S_0x285cba0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285cab0;
+ .timescale -9 -12;
+L_0x2aae610/d .functor NOT 1, L_0x2aaea80, C4<0>, C4<0>, C4<0>;
+L_0x2aae610 .delay (10000,10000,10000) L_0x2aae610/d;
+L_0x2aae6b0/d .functor AND 1, L_0x2aaf600, L_0x2aae610, C4<1>, C4<1>;
+L_0x2aae6b0 .delay (20000,20000,20000) L_0x2aae6b0/d;
+L_0x2aae7a0/d .functor AND 1, L_0x2aae2a0, L_0x2aaea80, C4<1>, C4<1>;
+L_0x2aae7a0 .delay (20000,20000,20000) L_0x2aae7a0/d;
+L_0x2aae8b0/d .functor OR 1, L_0x2aae6b0, L_0x2aae7a0, C4<0>, C4<0>;
+L_0x2aae8b0 .delay (20000,20000,20000) L_0x2aae8b0/d;
+v0x285cc90_0 .net "S", 0 0, L_0x2aaea80; 1 drivers
+v0x285cd30_0 .alias "in0", 0 0, v0x285d3c0_0;
+v0x285cdd0_0 .alias "in1", 0 0, v0x285d890_0;
+v0x285ce70_0 .net "nS", 0 0, L_0x2aae610; 1 drivers
+v0x285cf20_0 .net "out0", 0 0, L_0x2aae6b0; 1 drivers
+v0x285cfc0_0 .net "out1", 0 0, L_0x2aae7a0; 1 drivers
+v0x285d0a0_0 .alias "outfinal", 0 0, v0x285d470_0;
+S_0x285b7a0 .scope generate, "addbits[7]" "addbits[7]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x285b1b8 .param/l "i" 3 283, +C4<0111>;
+S_0x285b910 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285b7a0;
+ .timescale -9 -12;
+L_0x2aaf6a0/d .functor NOT 1, L_0x2ab0b20, C4<0>, C4<0>, C4<0>;
+L_0x2aaf6a0 .delay (10000,10000,10000) L_0x2aaf6a0/d;
+L_0x2ab0060/d .functor NOT 1, L_0x2ab0120, C4<0>, C4<0>, C4<0>;
+L_0x2ab0060 .delay (10000,10000,10000) L_0x2ab0060/d;
+L_0x2ab01c0/d .functor AND 1, L_0x2ab0300, L_0x2ab0060, C4<1>, C4<1>;
+L_0x2ab01c0 .delay (20000,20000,20000) L_0x2ab01c0/d;
+L_0x2ab03a0/d .functor XOR 1, L_0x2ab0c60, L_0x2aafdf0, C4<0>, C4<0>;
+L_0x2ab03a0 .delay (40000,40000,40000) L_0x2ab03a0/d;
+L_0x2ab0490/d .functor XOR 1, L_0x2ab03a0, L_0x2ab0e50, C4<0>, C4<0>;
+L_0x2ab0490 .delay (40000,40000,40000) L_0x2ab0490/d;
+L_0x2ab0580/d .functor AND 1, L_0x2ab0c60, L_0x2aafdf0, C4<1>, C4<1>;
+L_0x2ab0580 .delay (20000,20000,20000) L_0x2ab0580/d;
+L_0x2ab06f0/d .functor AND 1, L_0x2ab03a0, L_0x2ab0e50, C4<1>, C4<1>;
+L_0x2ab06f0 .delay (20000,20000,20000) L_0x2ab06f0/d;
+L_0x2ab07e0/d .functor OR 1, L_0x2ab0580, L_0x2ab06f0, C4<0>, C4<0>;
+L_0x2ab07e0 .delay (20000,20000,20000) L_0x2ab07e0/d;
+v0x285bfa0_0 .net "A", 0 0, L_0x2ab0c60; 1 drivers
+v0x285c060_0 .net "AandB", 0 0, L_0x2ab0580; 1 drivers
+v0x285c100_0 .net "AddSubSLTSum", 0 0, L_0x2ab0490; 1 drivers
+v0x285c1a0_0 .net "AxorB", 0 0, L_0x2ab03a0; 1 drivers
+v0x285c220_0 .net "B", 0 0, L_0x2ab0b20; 1 drivers
+v0x285c2d0_0 .net "BornB", 0 0, L_0x2aafdf0; 1 drivers
+v0x285c390_0 .net "CINandAxorB", 0 0, L_0x2ab06f0; 1 drivers
+v0x285c410_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x285c490_0 .net *"_s3", 0 0, L_0x2ab0120; 1 drivers
+v0x285c510_0 .net *"_s5", 0 0, L_0x2ab0300; 1 drivers
+v0x285c5b0_0 .net "carryin", 0 0, L_0x2ab0e50; 1 drivers
+v0x285c650_0 .net "carryout", 0 0, L_0x2ab07e0; 1 drivers
+v0x285c6f0_0 .net "nB", 0 0, L_0x2aaf6a0; 1 drivers
+v0x285c7a0_0 .net "nCmd2", 0 0, L_0x2ab0060; 1 drivers
+v0x285c8a0_0 .net "subtract", 0 0, L_0x2ab01c0; 1 drivers
+L_0x2aaffc0 .part v0x2960210_0, 0, 1;
+L_0x2ab0120 .part v0x2960210_0, 2, 1;
+L_0x2ab0300 .part v0x2960210_0, 0, 1;
+S_0x285ba00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285b910;
+ .timescale -9 -12;
+L_0x2aafb30/d .functor NOT 1, L_0x2aaffc0, C4<0>, C4<0>, C4<0>;
+L_0x2aafb30 .delay (10000,10000,10000) L_0x2aafb30/d;
+L_0x2aafbd0/d .functor AND 1, L_0x2ab0b20, L_0x2aafb30, C4<1>, C4<1>;
+L_0x2aafbd0 .delay (20000,20000,20000) L_0x2aafbd0/d;
+L_0x2aafce0/d .functor AND 1, L_0x2aaf6a0, L_0x2aaffc0, C4<1>, C4<1>;
+L_0x2aafce0 .delay (20000,20000,20000) L_0x2aafce0/d;
+L_0x2aafdf0/d .functor OR 1, L_0x2aafbd0, L_0x2aafce0, C4<0>, C4<0>;
+L_0x2aafdf0 .delay (20000,20000,20000) L_0x2aafdf0/d;
+v0x285baf0_0 .net "S", 0 0, L_0x2aaffc0; 1 drivers
+v0x285bb90_0 .alias "in0", 0 0, v0x285c220_0;
+v0x285bc30_0 .alias "in1", 0 0, v0x285c6f0_0;
+v0x285bcd0_0 .net "nS", 0 0, L_0x2aafb30; 1 drivers
+v0x285bd80_0 .net "out0", 0 0, L_0x2aafbd0; 1 drivers
+v0x285be20_0 .net "out1", 0 0, L_0x2aafce0; 1 drivers
+v0x285bf00_0 .alias "outfinal", 0 0, v0x285c2d0_0;
+S_0x285a600 .scope generate, "addbits[8]" "addbits[8]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x285a018 .param/l "i" 3 283, +C4<01000>;
+S_0x285a770 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x285a600;
+ .timescale -9 -12;
+L_0x2ab0d00/d .functor NOT 1, L_0x2ab2040, C4<0>, C4<0>, C4<0>;
+L_0x2ab0d00 .delay (10000,10000,10000) L_0x2ab0d00/d;
+L_0x2ab1580/d .functor NOT 1, L_0x2ab1640, C4<0>, C4<0>, C4<0>;
+L_0x2ab1580 .delay (10000,10000,10000) L_0x2ab1580/d;
+L_0x2ab16e0/d .functor AND 1, L_0x2ab1820, L_0x2ab1580, C4<1>, C4<1>;
+L_0x2ab16e0 .delay (20000,20000,20000) L_0x2ab16e0/d;
+L_0x2ab18c0/d .functor XOR 1, L_0x2ab21b0, L_0x2ab1310, C4<0>, C4<0>;
+L_0x2ab18c0 .delay (40000,40000,40000) L_0x2ab18c0/d;
+L_0x2ab19b0/d .functor XOR 1, L_0x2ab18c0, L_0x2ab23d0, C4<0>, C4<0>;
+L_0x2ab19b0 .delay (40000,40000,40000) L_0x2ab19b0/d;
+L_0x2ab1aa0/d .functor AND 1, L_0x2ab21b0, L_0x2ab1310, C4<1>, C4<1>;
+L_0x2ab1aa0 .delay (20000,20000,20000) L_0x2ab1aa0/d;
+L_0x2ab1c10/d .functor AND 1, L_0x2ab18c0, L_0x2ab23d0, C4<1>, C4<1>;
+L_0x2ab1c10 .delay (20000,20000,20000) L_0x2ab1c10/d;
+L_0x2ab1d00/d .functor OR 1, L_0x2ab1aa0, L_0x2ab1c10, C4<0>, C4<0>;
+L_0x2ab1d00 .delay (20000,20000,20000) L_0x2ab1d00/d;
+v0x285ae00_0 .net "A", 0 0, L_0x2ab21b0; 1 drivers
+v0x285aec0_0 .net "AandB", 0 0, L_0x2ab1aa0; 1 drivers
+v0x285af60_0 .net "AddSubSLTSum", 0 0, L_0x2ab19b0; 1 drivers
+v0x285b000_0 .net "AxorB", 0 0, L_0x2ab18c0; 1 drivers
+v0x285b080_0 .net "B", 0 0, L_0x2ab2040; 1 drivers
+v0x285b130_0 .net "BornB", 0 0, L_0x2ab1310; 1 drivers
+v0x285b1f0_0 .net "CINandAxorB", 0 0, L_0x2ab1c10; 1 drivers
+v0x285b270_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x285b2f0_0 .net *"_s3", 0 0, L_0x2ab1640; 1 drivers
+v0x285b370_0 .net *"_s5", 0 0, L_0x2ab1820; 1 drivers
+v0x285b410_0 .net "carryin", 0 0, L_0x2ab23d0; 1 drivers
+v0x285b4b0_0 .net "carryout", 0 0, L_0x2ab1d00; 1 drivers
+v0x285b550_0 .net "nB", 0 0, L_0x2ab0d00; 1 drivers
+v0x285b600_0 .net "nCmd2", 0 0, L_0x2ab1580; 1 drivers
+v0x285b700_0 .net "subtract", 0 0, L_0x2ab16e0; 1 drivers
+L_0x2ab14e0 .part v0x2960210_0, 0, 1;
+L_0x2ab1640 .part v0x2960210_0, 2, 1;
+L_0x2ab1820 .part v0x2960210_0, 0, 1;
+S_0x285a860 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x285a770;
+ .timescale -9 -12;
+L_0x2ab1050/d .functor NOT 1, L_0x2ab14e0, C4<0>, C4<0>, C4<0>;
+L_0x2ab1050 .delay (10000,10000,10000) L_0x2ab1050/d;
+L_0x2ab10f0/d .functor AND 1, L_0x2ab2040, L_0x2ab1050, C4<1>, C4<1>;
+L_0x2ab10f0 .delay (20000,20000,20000) L_0x2ab10f0/d;
+L_0x2ab1200/d .functor AND 1, L_0x2ab0d00, L_0x2ab14e0, C4<1>, C4<1>;
+L_0x2ab1200 .delay (20000,20000,20000) L_0x2ab1200/d;
+L_0x2ab1310/d .functor OR 1, L_0x2ab10f0, L_0x2ab1200, C4<0>, C4<0>;
+L_0x2ab1310 .delay (20000,20000,20000) L_0x2ab1310/d;
+v0x285a950_0 .net "S", 0 0, L_0x2ab14e0; 1 drivers
+v0x285a9f0_0 .alias "in0", 0 0, v0x285b080_0;
+v0x285aa90_0 .alias "in1", 0 0, v0x285b550_0;
+v0x285ab30_0 .net "nS", 0 0, L_0x2ab1050; 1 drivers
+v0x285abe0_0 .net "out0", 0 0, L_0x2ab10f0; 1 drivers
+v0x285ac80_0 .net "out1", 0 0, L_0x2ab1200; 1 drivers
+v0x285ad60_0 .alias "outfinal", 0 0, v0x285b130_0;
+S_0x2859460 .scope generate, "addbits[9]" "addbits[9]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2858e78 .param/l "i" 3 283, +C4<01001>;
+S_0x28595d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2859460;
+ .timescale -9 -12;
+L_0x2ab0fe0/d .functor NOT 1, L_0x2ab3800, C4<0>, C4<0>, C4<0>;
+L_0x2ab0fe0 .delay (10000,10000,10000) L_0x2ab0fe0/d;
+L_0x2ab2b90/d .functor NOT 1, L_0x2ab2c50, C4<0>, C4<0>, C4<0>;
+L_0x2ab2b90 .delay (10000,10000,10000) L_0x2ab2b90/d;
+L_0x2ab2cf0/d .functor AND 1, L_0x2ab2e30, L_0x2ab2b90, C4<1>, C4<1>;
+L_0x2ab2cf0 .delay (20000,20000,20000) L_0x2ab2cf0/d;
+L_0x2ab2ed0/d .functor XOR 1, L_0x2ab2770, L_0x2ab2920, C4<0>, C4<0>;
+L_0x2ab2ed0 .delay (40000,40000,40000) L_0x2ab2ed0/d;
+L_0x2ab2fc0/d .functor XOR 1, L_0x2ab2ed0, L_0x2ab3930, C4<0>, C4<0>;
+L_0x2ab2fc0 .delay (40000,40000,40000) L_0x2ab2fc0/d;
+L_0x2ab30b0/d .functor AND 1, L_0x2ab2770, L_0x2ab2920, C4<1>, C4<1>;
+L_0x2ab30b0 .delay (20000,20000,20000) L_0x2ab30b0/d;
+L_0x2ab3220/d .functor AND 1, L_0x2ab2ed0, L_0x2ab3930, C4<1>, C4<1>;
+L_0x2ab3220 .delay (20000,20000,20000) L_0x2ab3220/d;
+L_0x2ab3310/d .functor OR 1, L_0x2ab30b0, L_0x2ab3220, C4<0>, C4<0>;
+L_0x2ab3310 .delay (20000,20000,20000) L_0x2ab3310/d;
+v0x2859c60_0 .net "A", 0 0, L_0x2ab2770; 1 drivers
+v0x2859d20_0 .net "AandB", 0 0, L_0x2ab30b0; 1 drivers
+v0x2859dc0_0 .net "AddSubSLTSum", 0 0, L_0x2ab2fc0; 1 drivers
+v0x2859e60_0 .net "AxorB", 0 0, L_0x2ab2ed0; 1 drivers
+v0x2859ee0_0 .net "B", 0 0, L_0x2ab3800; 1 drivers
+v0x2859f90_0 .net "BornB", 0 0, L_0x2ab2920; 1 drivers
+v0x285a050_0 .net "CINandAxorB", 0 0, L_0x2ab3220; 1 drivers
+v0x285a0d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x285a150_0 .net *"_s3", 0 0, L_0x2ab2c50; 1 drivers
+v0x285a1d0_0 .net *"_s5", 0 0, L_0x2ab2e30; 1 drivers
+v0x285a270_0 .net "carryin", 0 0, L_0x2ab3930; 1 drivers
+v0x285a310_0 .net "carryout", 0 0, L_0x2ab3310; 1 drivers
+v0x285a3b0_0 .net "nB", 0 0, L_0x2ab0fe0; 1 drivers
+v0x285a460_0 .net "nCmd2", 0 0, L_0x2ab2b90; 1 drivers
+v0x285a560_0 .net "subtract", 0 0, L_0x2ab2cf0; 1 drivers
+L_0x2ab2af0 .part v0x2960210_0, 0, 1;
+L_0x2ab2c50 .part v0x2960210_0, 2, 1;
+L_0x2ab2e30 .part v0x2960210_0, 0, 1;
+S_0x28596c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28595d0;
+ .timescale -9 -12;
+L_0x2ab2250/d .functor NOT 1, L_0x2ab2af0, C4<0>, C4<0>, C4<0>;
+L_0x2ab2250 .delay (10000,10000,10000) L_0x2ab2250/d;
+L_0x2ab2310/d .functor AND 1, L_0x2ab3800, L_0x2ab2250, C4<1>, C4<1>;
+L_0x2ab2310 .delay (20000,20000,20000) L_0x2ab2310/d;
+L_0x2ab2810/d .functor AND 1, L_0x2ab0fe0, L_0x2ab2af0, C4<1>, C4<1>;
+L_0x2ab2810 .delay (20000,20000,20000) L_0x2ab2810/d;
+L_0x2ab2920/d .functor OR 1, L_0x2ab2310, L_0x2ab2810, C4<0>, C4<0>;
+L_0x2ab2920 .delay (20000,20000,20000) L_0x2ab2920/d;
+v0x28597b0_0 .net "S", 0 0, L_0x2ab2af0; 1 drivers
+v0x2859850_0 .alias "in0", 0 0, v0x2859ee0_0;
+v0x28598f0_0 .alias "in1", 0 0, v0x285a3b0_0;
+v0x2859990_0 .net "nS", 0 0, L_0x2ab2250; 1 drivers
+v0x2859a40_0 .net "out0", 0 0, L_0x2ab2310; 1 drivers
+v0x2859ae0_0 .net "out1", 0 0, L_0x2ab2810; 1 drivers
+v0x2859bc0_0 .alias "outfinal", 0 0, v0x2859f90_0;
+S_0x28582c0 .scope generate, "addbits[10]" "addbits[10]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2857cd8 .param/l "i" 3 283, +C4<01010>;
+S_0x2858430 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x28582c0;
+ .timescale -9 -12;
+L_0x2ab3650/d .functor NOT 1, L_0x2ab4d40, C4<0>, C4<0>, C4<0>;
+L_0x2ab3650 .delay (10000,10000,10000) L_0x2ab3650/d;
+L_0x2ab40a0/d .functor NOT 1, L_0x2ab4160, C4<0>, C4<0>, C4<0>;
+L_0x2ab40a0 .delay (10000,10000,10000) L_0x2ab40a0/d;
+L_0x2ab4200/d .functor AND 1, L_0x2ab4340, L_0x2ab40a0, C4<1>, C4<1>;
+L_0x2ab4200 .delay (20000,20000,20000) L_0x2ab4200/d;
+L_0x2ab43e0/d .functor XOR 1, L_0x2ab3ac0, L_0x2ab3e30, C4<0>, C4<0>;
+L_0x2ab43e0 .delay (40000,40000,40000) L_0x2ab43e0/d;
+L_0x2ab44d0/d .functor XOR 1, L_0x2ab43e0, L_0x2ab4e70, C4<0>, C4<0>;
+L_0x2ab44d0 .delay (40000,40000,40000) L_0x2ab44d0/d;
+L_0x2ab45c0/d .functor AND 1, L_0x2ab3ac0, L_0x2ab3e30, C4<1>, C4<1>;
+L_0x2ab45c0 .delay (20000,20000,20000) L_0x2ab45c0/d;
+L_0x2ab4730/d .functor AND 1, L_0x2ab43e0, L_0x2ab4e70, C4<1>, C4<1>;
+L_0x2ab4730 .delay (20000,20000,20000) L_0x2ab4730/d;
+L_0x2ab4820/d .functor OR 1, L_0x2ab45c0, L_0x2ab4730, C4<0>, C4<0>;
+L_0x2ab4820 .delay (20000,20000,20000) L_0x2ab4820/d;
+v0x2858ac0_0 .net "A", 0 0, L_0x2ab3ac0; 1 drivers
+v0x2858b80_0 .net "AandB", 0 0, L_0x2ab45c0; 1 drivers
+v0x2858c20_0 .net "AddSubSLTSum", 0 0, L_0x2ab44d0; 1 drivers
+v0x2858cc0_0 .net "AxorB", 0 0, L_0x2ab43e0; 1 drivers
+v0x2858d40_0 .net "B", 0 0, L_0x2ab4d40; 1 drivers
+v0x2858df0_0 .net "BornB", 0 0, L_0x2ab3e30; 1 drivers
+v0x2858eb0_0 .net "CINandAxorB", 0 0, L_0x2ab4730; 1 drivers
+v0x2858f30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2858fb0_0 .net *"_s3", 0 0, L_0x2ab4160; 1 drivers
+v0x2859030_0 .net *"_s5", 0 0, L_0x2ab4340; 1 drivers
+v0x28590d0_0 .net "carryin", 0 0, L_0x2ab4e70; 1 drivers
+v0x2859170_0 .net "carryout", 0 0, L_0x2ab4820; 1 drivers
+v0x2859210_0 .net "nB", 0 0, L_0x2ab3650; 1 drivers
+v0x28592c0_0 .net "nCmd2", 0 0, L_0x2ab40a0; 1 drivers
+v0x28593c0_0 .net "subtract", 0 0, L_0x2ab4200; 1 drivers
+L_0x2ab4000 .part v0x2960210_0, 0, 1;
+L_0x2ab4160 .part v0x2960210_0, 2, 1;
+L_0x2ab4340 .part v0x2960210_0, 0, 1;
+S_0x2858520 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2858430;
+ .timescale -9 -12;
+L_0x2ab3b90/d .functor NOT 1, L_0x2ab4000, C4<0>, C4<0>, C4<0>;
+L_0x2ab3b90 .delay (10000,10000,10000) L_0x2ab3b90/d;
+L_0x2ab3c30/d .functor AND 1, L_0x2ab4d40, L_0x2ab3b90, C4<1>, C4<1>;
+L_0x2ab3c30 .delay (20000,20000,20000) L_0x2ab3c30/d;
+L_0x2ab3d20/d .functor AND 1, L_0x2ab3650, L_0x2ab4000, C4<1>, C4<1>;
+L_0x2ab3d20 .delay (20000,20000,20000) L_0x2ab3d20/d;
+L_0x2ab3e30/d .functor OR 1, L_0x2ab3c30, L_0x2ab3d20, C4<0>, C4<0>;
+L_0x2ab3e30 .delay (20000,20000,20000) L_0x2ab3e30/d;
+v0x2858610_0 .net "S", 0 0, L_0x2ab4000; 1 drivers
+v0x28586b0_0 .alias "in0", 0 0, v0x2858d40_0;
+v0x2858750_0 .alias "in1", 0 0, v0x2859210_0;
+v0x28587f0_0 .net "nS", 0 0, L_0x2ab3b90; 1 drivers
+v0x28588a0_0 .net "out0", 0 0, L_0x2ab3c30; 1 drivers
+v0x2858940_0 .net "out1", 0 0, L_0x2ab3d20; 1 drivers
+v0x2858a20_0 .alias "outfinal", 0 0, v0x2858df0_0;
+S_0x2857120 .scope generate, "addbits[11]" "addbits[11]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2856b38 .param/l "i" 3 283, +C4<01011>;
+S_0x2857290 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2857120;
+ .timescale -9 -12;
+L_0x2ab4b60/d .functor NOT 1, L_0x2ab6280, C4<0>, C4<0>, C4<0>;
+L_0x2ab4b60 .delay (10000,10000,10000) L_0x2ab4b60/d;
+L_0x2ab55b0/d .functor NOT 1, L_0x2ab5670, C4<0>, C4<0>, C4<0>;
+L_0x2ab55b0 .delay (10000,10000,10000) L_0x2ab55b0/d;
+L_0x2ab5710/d .functor AND 1, L_0x2ab5850, L_0x2ab55b0, C4<1>, C4<1>;
+L_0x2ab5710 .delay (20000,20000,20000) L_0x2ab5710/d;
+L_0x2ab58f0/d .functor XOR 1, L_0x2ab5000, L_0x2ab5340, C4<0>, C4<0>;
+L_0x2ab58f0 .delay (40000,40000,40000) L_0x2ab58f0/d;
+L_0x2ab59e0/d .functor XOR 1, L_0x2ab58f0, L_0x2ab63b0, C4<0>, C4<0>;
+L_0x2ab59e0 .delay (40000,40000,40000) L_0x2ab59e0/d;
+L_0x2ab5ad0/d .functor AND 1, L_0x2ab5000, L_0x2ab5340, C4<1>, C4<1>;
+L_0x2ab5ad0 .delay (20000,20000,20000) L_0x2ab5ad0/d;
+L_0x2ab5c40/d .functor AND 1, L_0x2ab58f0, L_0x2ab63b0, C4<1>, C4<1>;
+L_0x2ab5c40 .delay (20000,20000,20000) L_0x2ab5c40/d;
+L_0x2ab5d30/d .functor OR 1, L_0x2ab5ad0, L_0x2ab5c40, C4<0>, C4<0>;
+L_0x2ab5d30 .delay (20000,20000,20000) L_0x2ab5d30/d;
+v0x2857920_0 .net "A", 0 0, L_0x2ab5000; 1 drivers
+v0x28579e0_0 .net "AandB", 0 0, L_0x2ab5ad0; 1 drivers
+v0x2857a80_0 .net "AddSubSLTSum", 0 0, L_0x2ab59e0; 1 drivers
+v0x2857b20_0 .net "AxorB", 0 0, L_0x2ab58f0; 1 drivers
+v0x2857ba0_0 .net "B", 0 0, L_0x2ab6280; 1 drivers
+v0x2857c50_0 .net "BornB", 0 0, L_0x2ab5340; 1 drivers
+v0x2857d10_0 .net "CINandAxorB", 0 0, L_0x2ab5c40; 1 drivers
+v0x2857d90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2857e10_0 .net *"_s3", 0 0, L_0x2ab5670; 1 drivers
+v0x2857e90_0 .net *"_s5", 0 0, L_0x2ab5850; 1 drivers
+v0x2857f30_0 .net "carryin", 0 0, L_0x2ab63b0; 1 drivers
+v0x2857fd0_0 .net "carryout", 0 0, L_0x2ab5d30; 1 drivers
+v0x2858070_0 .net "nB", 0 0, L_0x2ab4b60; 1 drivers
+v0x2858120_0 .net "nCmd2", 0 0, L_0x2ab55b0; 1 drivers
+v0x2858220_0 .net "subtract", 0 0, L_0x2ab5710; 1 drivers
+L_0x2ab5510 .part v0x2960210_0, 0, 1;
+L_0x2ab5670 .part v0x2960210_0, 2, 1;
+L_0x2ab5850 .part v0x2960210_0, 0, 1;
+S_0x2857380 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2857290;
+ .timescale -9 -12;
+L_0x2ab4cc0/d .functor NOT 1, L_0x2ab5510, C4<0>, C4<0>, C4<0>;
+L_0x2ab4cc0 .delay (10000,10000,10000) L_0x2ab4cc0/d;
+L_0x2ab5140/d .functor AND 1, L_0x2ab6280, L_0x2ab4cc0, C4<1>, C4<1>;
+L_0x2ab5140 .delay (20000,20000,20000) L_0x2ab5140/d;
+L_0x2ab5230/d .functor AND 1, L_0x2ab4b60, L_0x2ab5510, C4<1>, C4<1>;
+L_0x2ab5230 .delay (20000,20000,20000) L_0x2ab5230/d;
+L_0x2ab5340/d .functor OR 1, L_0x2ab5140, L_0x2ab5230, C4<0>, C4<0>;
+L_0x2ab5340 .delay (20000,20000,20000) L_0x2ab5340/d;
+v0x2857470_0 .net "S", 0 0, L_0x2ab5510; 1 drivers
+v0x2857510_0 .alias "in0", 0 0, v0x2857ba0_0;
+v0x28575b0_0 .alias "in1", 0 0, v0x2858070_0;
+v0x2857650_0 .net "nS", 0 0, L_0x2ab4cc0; 1 drivers
+v0x2857700_0 .net "out0", 0 0, L_0x2ab5140; 1 drivers
+v0x28577a0_0 .net "out1", 0 0, L_0x2ab5230; 1 drivers
+v0x2857880_0 .alias "outfinal", 0 0, v0x2857c50_0;
+S_0x2855f80 .scope generate, "addbits[12]" "addbits[12]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2855998 .param/l "i" 3 283, +C4<01100>;
+S_0x28560f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2855f80;
+ .timescale -9 -12;
+L_0x2ab50a0/d .functor NOT 1, L_0x2ab77c0, C4<0>, C4<0>, C4<0>;
+L_0x2ab50a0 .delay (10000,10000,10000) L_0x2ab50a0/d;
+L_0x2ab6ac0/d .functor NOT 1, L_0x2ab6b80, C4<0>, C4<0>, C4<0>;
+L_0x2ab6ac0 .delay (10000,10000,10000) L_0x2ab6ac0/d;
+L_0x2ab6c20/d .functor AND 1, L_0x2ab6d60, L_0x2ab6ac0, C4<1>, C4<1>;
+L_0x2ab6c20 .delay (20000,20000,20000) L_0x2ab6c20/d;
+L_0x2ab6e00/d .functor XOR 1, L_0x2ab6540, L_0x2ab6850, C4<0>, C4<0>;
+L_0x2ab6e00 .delay (40000,40000,40000) L_0x2ab6e00/d;
+L_0x2ab6ef0/d .functor XOR 1, L_0x2ab6e00, L_0x2ab7860, C4<0>, C4<0>;
+L_0x2ab6ef0 .delay (40000,40000,40000) L_0x2ab6ef0/d;
+L_0x2ab6fe0/d .functor AND 1, L_0x2ab6540, L_0x2ab6850, C4<1>, C4<1>;
+L_0x2ab6fe0 .delay (20000,20000,20000) L_0x2ab6fe0/d;
+L_0x2ab7150/d .functor AND 1, L_0x2ab6e00, L_0x2ab7860, C4<1>, C4<1>;
+L_0x2ab7150 .delay (20000,20000,20000) L_0x2ab7150/d;
+L_0x2ab7240/d .functor OR 1, L_0x2ab6fe0, L_0x2ab7150, C4<0>, C4<0>;
+L_0x2ab7240 .delay (20000,20000,20000) L_0x2ab7240/d;
+v0x2856780_0 .net "A", 0 0, L_0x2ab6540; 1 drivers
+v0x2856840_0 .net "AandB", 0 0, L_0x2ab6fe0; 1 drivers
+v0x28568e0_0 .net "AddSubSLTSum", 0 0, L_0x2ab6ef0; 1 drivers
+v0x2856980_0 .net "AxorB", 0 0, L_0x2ab6e00; 1 drivers
+v0x2856a00_0 .net "B", 0 0, L_0x2ab77c0; 1 drivers
+v0x2856ab0_0 .net "BornB", 0 0, L_0x2ab6850; 1 drivers
+v0x2856b70_0 .net "CINandAxorB", 0 0, L_0x2ab7150; 1 drivers
+v0x2856bf0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2856c70_0 .net *"_s3", 0 0, L_0x2ab6b80; 1 drivers
+v0x2856cf0_0 .net *"_s5", 0 0, L_0x2ab6d60; 1 drivers
+v0x2856d90_0 .net "carryin", 0 0, L_0x2ab7860; 1 drivers
+v0x2856e30_0 .net "carryout", 0 0, L_0x2ab7240; 1 drivers
+v0x2856ed0_0 .net "nB", 0 0, L_0x2ab50a0; 1 drivers
+v0x2856f80_0 .net "nCmd2", 0 0, L_0x2ab6ac0; 1 drivers
+v0x2857080_0 .net "subtract", 0 0, L_0x2ab6c20; 1 drivers
+L_0x2ab6a20 .part v0x2960210_0, 0, 1;
+L_0x2ab6b80 .part v0x2960210_0, 2, 1;
+L_0x2ab6d60 .part v0x2960210_0, 0, 1;
+S_0x28561e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28560f0;
+ .timescale -9 -12;
+L_0x2ab6170/d .functor NOT 1, L_0x2ab6a20, C4<0>, C4<0>, C4<0>;
+L_0x2ab6170 .delay (10000,10000,10000) L_0x2ab6170/d;
+L_0x2ab6670/d .functor AND 1, L_0x2ab77c0, L_0x2ab6170, C4<1>, C4<1>;
+L_0x2ab6670 .delay (20000,20000,20000) L_0x2ab6670/d;
+L_0x2ab6760/d .functor AND 1, L_0x2ab50a0, L_0x2ab6a20, C4<1>, C4<1>;
+L_0x2ab6760 .delay (20000,20000,20000) L_0x2ab6760/d;
+L_0x2ab6850/d .functor OR 1, L_0x2ab6670, L_0x2ab6760, C4<0>, C4<0>;
+L_0x2ab6850 .delay (20000,20000,20000) L_0x2ab6850/d;
+v0x28562d0_0 .net "S", 0 0, L_0x2ab6a20; 1 drivers
+v0x2856370_0 .alias "in0", 0 0, v0x2856a00_0;
+v0x2856410_0 .alias "in1", 0 0, v0x2856ed0_0;
+v0x28564b0_0 .net "nS", 0 0, L_0x2ab6170; 1 drivers
+v0x2856560_0 .net "out0", 0 0, L_0x2ab6670; 1 drivers
+v0x2856600_0 .net "out1", 0 0, L_0x2ab6760; 1 drivers
+v0x28566e0_0 .alias "outfinal", 0 0, v0x2856ab0_0;
+S_0x2854de0 .scope generate, "addbits[13]" "addbits[13]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28547f8 .param/l "i" 3 283, +C4<01101>;
+S_0x2854f50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2854de0;
+ .timescale -9 -12;
+L_0x2ab7580/d .functor NOT 1, L_0x2ab7a90, C4<0>, C4<0>, C4<0>;
+L_0x2ab7580 .delay (10000,10000,10000) L_0x2ab7580/d;
+L_0x2ab7fc0/d .functor NOT 1, L_0x2ab8080, C4<0>, C4<0>, C4<0>;
+L_0x2ab7fc0 .delay (10000,10000,10000) L_0x2ab7fc0/d;
+L_0x2ab8120/d .functor AND 1, L_0x2ab8260, L_0x2ab7fc0, C4<1>, C4<1>;
+L_0x2ab8120 .delay (20000,20000,20000) L_0x2ab8120/d;
+L_0x2ab8300/d .functor XOR 1, L_0x2ab79f0, L_0x2ab7d50, C4<0>, C4<0>;
+L_0x2ab8300 .delay (40000,40000,40000) L_0x2ab8300/d;
+L_0x2ab83f0/d .functor XOR 1, L_0x2ab8300, L_0x2ab8d80, C4<0>, C4<0>;
+L_0x2ab83f0 .delay (40000,40000,40000) L_0x2ab83f0/d;
+L_0x2ab84e0/d .functor AND 1, L_0x2ab79f0, L_0x2ab7d50, C4<1>, C4<1>;
+L_0x2ab84e0 .delay (20000,20000,20000) L_0x2ab84e0/d;
+L_0x2ab8650/d .functor AND 1, L_0x2ab8300, L_0x2ab8d80, C4<1>, C4<1>;
+L_0x2ab8650 .delay (20000,20000,20000) L_0x2ab8650/d;
+L_0x2ab8740/d .functor OR 1, L_0x2ab84e0, L_0x2ab8650, C4<0>, C4<0>;
+L_0x2ab8740 .delay (20000,20000,20000) L_0x2ab8740/d;
+v0x28555e0_0 .net "A", 0 0, L_0x2ab79f0; 1 drivers
+v0x28556a0_0 .net "AandB", 0 0, L_0x2ab84e0; 1 drivers
+v0x2855740_0 .net "AddSubSLTSum", 0 0, L_0x2ab83f0; 1 drivers
+v0x28557e0_0 .net "AxorB", 0 0, L_0x2ab8300; 1 drivers
+v0x2855860_0 .net "B", 0 0, L_0x2ab7a90; 1 drivers
+v0x2855910_0 .net "BornB", 0 0, L_0x2ab7d50; 1 drivers
+v0x28559d0_0 .net "CINandAxorB", 0 0, L_0x2ab8650; 1 drivers
+v0x2855a50_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2855ad0_0 .net *"_s3", 0 0, L_0x2ab8080; 1 drivers
+v0x2855b50_0 .net *"_s5", 0 0, L_0x2ab8260; 1 drivers
+v0x2855bf0_0 .net "carryin", 0 0, L_0x2ab8d80; 1 drivers
+v0x2855c90_0 .net "carryout", 0 0, L_0x2ab8740; 1 drivers
+v0x2855d30_0 .net "nB", 0 0, L_0x2ab7580; 1 drivers
+v0x2855de0_0 .net "nCmd2", 0 0, L_0x2ab7fc0; 1 drivers
+v0x2855ee0_0 .net "subtract", 0 0, L_0x2ab8120; 1 drivers
+L_0x2ab7f20 .part v0x2960210_0, 0, 1;
+L_0x2ab8080 .part v0x2960210_0, 2, 1;
+L_0x2ab8260 .part v0x2960210_0, 0, 1;
+S_0x2855040 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2854f50;
+ .timescale -9 -12;
+L_0x2ab76e0/d .functor NOT 1, L_0x2ab7f20, C4<0>, C4<0>, C4<0>;
+L_0x2ab76e0 .delay (10000,10000,10000) L_0x2ab76e0/d;
+L_0x2ab7b50/d .functor AND 1, L_0x2ab7a90, L_0x2ab76e0, C4<1>, C4<1>;
+L_0x2ab7b50 .delay (20000,20000,20000) L_0x2ab7b50/d;
+L_0x2ab7c40/d .functor AND 1, L_0x2ab7580, L_0x2ab7f20, C4<1>, C4<1>;
+L_0x2ab7c40 .delay (20000,20000,20000) L_0x2ab7c40/d;
+L_0x2ab7d50/d .functor OR 1, L_0x2ab7b50, L_0x2ab7c40, C4<0>, C4<0>;
+L_0x2ab7d50 .delay (20000,20000,20000) L_0x2ab7d50/d;
+v0x2855130_0 .net "S", 0 0, L_0x2ab7f20; 1 drivers
+v0x28551d0_0 .alias "in0", 0 0, v0x2855860_0;
+v0x2855270_0 .alias "in1", 0 0, v0x2855d30_0;
+v0x2855310_0 .net "nS", 0 0, L_0x2ab76e0; 1 drivers
+v0x28553c0_0 .net "out0", 0 0, L_0x2ab7b50; 1 drivers
+v0x2855460_0 .net "out1", 0 0, L_0x2ab7c40; 1 drivers
+v0x2855540_0 .alias "outfinal", 0 0, v0x2855910_0;
+S_0x2853c40 .scope generate, "addbits[14]" "addbits[14]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2853658 .param/l "i" 3 283, +C4<01110>;
+S_0x2853db0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2853c40;
+ .timescale -9 -12;
+L_0x2ab8a80/d .functor NOT 1, L_0x2ab8fb0, C4<0>, C4<0>, C4<0>;
+L_0x2ab8a80 .delay (10000,10000,10000) L_0x2ab8a80/d;
+L_0x2ab94d0/d .functor NOT 1, L_0x2ab9590, C4<0>, C4<0>, C4<0>;
+L_0x2ab94d0 .delay (10000,10000,10000) L_0x2ab94d0/d;
+L_0x2ab9630/d .functor AND 1, L_0x2ab9770, L_0x2ab94d0, C4<1>, C4<1>;
+L_0x2ab9630 .delay (20000,20000,20000) L_0x2ab9630/d;
+L_0x2ab9810/d .functor XOR 1, L_0x2ab8f10, L_0x2ab9260, C4<0>, C4<0>;
+L_0x2ab9810 .delay (40000,40000,40000) L_0x2ab9810/d;
+L_0x2ab9900/d .functor XOR 1, L_0x2ab9810, L_0x2aba2c0, C4<0>, C4<0>;
+L_0x2ab9900 .delay (40000,40000,40000) L_0x2ab9900/d;
+L_0x2ab99f0/d .functor AND 1, L_0x2ab8f10, L_0x2ab9260, C4<1>, C4<1>;
+L_0x2ab99f0 .delay (20000,20000,20000) L_0x2ab99f0/d;
+L_0x2ab9b60/d .functor AND 1, L_0x2ab9810, L_0x2aba2c0, C4<1>, C4<1>;
+L_0x2ab9b60 .delay (20000,20000,20000) L_0x2ab9b60/d;
+L_0x2ab9c50/d .functor OR 1, L_0x2ab99f0, L_0x2ab9b60, C4<0>, C4<0>;
+L_0x2ab9c50 .delay (20000,20000,20000) L_0x2ab9c50/d;
+v0x2854440_0 .net "A", 0 0, L_0x2ab8f10; 1 drivers
+v0x2854500_0 .net "AandB", 0 0, L_0x2ab99f0; 1 drivers
+v0x28545a0_0 .net "AddSubSLTSum", 0 0, L_0x2ab9900; 1 drivers
+v0x2854640_0 .net "AxorB", 0 0, L_0x2ab9810; 1 drivers
+v0x28546c0_0 .net "B", 0 0, L_0x2ab8fb0; 1 drivers
+v0x2854770_0 .net "BornB", 0 0, L_0x2ab9260; 1 drivers
+v0x2854830_0 .net "CINandAxorB", 0 0, L_0x2ab9b60; 1 drivers
+v0x28548b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2854930_0 .net *"_s3", 0 0, L_0x2ab9590; 1 drivers
+v0x28549b0_0 .net *"_s5", 0 0, L_0x2ab9770; 1 drivers
+v0x2854a50_0 .net "carryin", 0 0, L_0x2aba2c0; 1 drivers
+v0x2854af0_0 .net "carryout", 0 0, L_0x2ab9c50; 1 drivers
+v0x2854b90_0 .net "nB", 0 0, L_0x2ab8a80; 1 drivers
+v0x2854c40_0 .net "nCmd2", 0 0, L_0x2ab94d0; 1 drivers
+v0x2854d40_0 .net "subtract", 0 0, L_0x2ab9630; 1 drivers
+L_0x2ab9430 .part v0x2960210_0, 0, 1;
+L_0x2ab9590 .part v0x2960210_0, 2, 1;
+L_0x2ab9770 .part v0x2960210_0, 0, 1;
+S_0x2853ea0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2853db0;
+ .timescale -9 -12;
+L_0x2ab8bc0/d .functor NOT 1, L_0x2ab9430, C4<0>, C4<0>, C4<0>;
+L_0x2ab8bc0 .delay (10000,10000,10000) L_0x2ab8bc0/d;
+L_0x2ab8c80/d .functor AND 1, L_0x2ab8fb0, L_0x2ab8bc0, C4<1>, C4<1>;
+L_0x2ab8c80 .delay (20000,20000,20000) L_0x2ab8c80/d;
+L_0x2ab9150/d .functor AND 1, L_0x2ab8a80, L_0x2ab9430, C4<1>, C4<1>;
+L_0x2ab9150 .delay (20000,20000,20000) L_0x2ab9150/d;
+L_0x2ab9260/d .functor OR 1, L_0x2ab8c80, L_0x2ab9150, C4<0>, C4<0>;
+L_0x2ab9260 .delay (20000,20000,20000) L_0x2ab9260/d;
+v0x2853f90_0 .net "S", 0 0, L_0x2ab9430; 1 drivers
+v0x2854030_0 .alias "in0", 0 0, v0x28546c0_0;
+v0x28540d0_0 .alias "in1", 0 0, v0x2854b90_0;
+v0x2854170_0 .net "nS", 0 0, L_0x2ab8bc0; 1 drivers
+v0x2854220_0 .net "out0", 0 0, L_0x2ab8c80; 1 drivers
+v0x28542c0_0 .net "out1", 0 0, L_0x2ab9150; 1 drivers
+v0x28543a0_0 .alias "outfinal", 0 0, v0x2854770_0;
+S_0x2852aa0 .scope generate, "addbits[15]" "addbits[15]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28524b8 .param/l "i" 3 283, +C4<01111>;
+S_0x2852c10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2852aa0;
+ .timescale -9 -12;
+L_0x2ab9f90/d .functor NOT 1, L_0x2aba4f0, C4<0>, C4<0>, C4<0>;
+L_0x2ab9f90 .delay (10000,10000,10000) L_0x2ab9f90/d;
+L_0x2aba9e0/d .functor NOT 1, L_0x2abaaa0, C4<0>, C4<0>, C4<0>;
+L_0x2aba9e0 .delay (10000,10000,10000) L_0x2aba9e0/d;
+L_0x2abab40/d .functor AND 1, L_0x2abac80, L_0x2aba9e0, C4<1>, C4<1>;
+L_0x2abab40 .delay (20000,20000,20000) L_0x2abab40/d;
+L_0x2abad20/d .functor XOR 1, L_0x2aba450, L_0x2aba770, C4<0>, C4<0>;
+L_0x2abad20 .delay (40000,40000,40000) L_0x2abad20/d;
+L_0x2abae10/d .functor XOR 1, L_0x2abad20, L_0x2abb800, C4<0>, C4<0>;
+L_0x2abae10 .delay (40000,40000,40000) L_0x2abae10/d;
+L_0x2abaf00/d .functor AND 1, L_0x2aba450, L_0x2aba770, C4<1>, C4<1>;
+L_0x2abaf00 .delay (20000,20000,20000) L_0x2abaf00/d;
+L_0x2abb070/d .functor AND 1, L_0x2abad20, L_0x2abb800, C4<1>, C4<1>;
+L_0x2abb070 .delay (20000,20000,20000) L_0x2abb070/d;
+L_0x2abb160/d .functor OR 1, L_0x2abaf00, L_0x2abb070, C4<0>, C4<0>;
+L_0x2abb160 .delay (20000,20000,20000) L_0x2abb160/d;
+v0x28532a0_0 .net "A", 0 0, L_0x2aba450; 1 drivers
+v0x2853360_0 .net "AandB", 0 0, L_0x2abaf00; 1 drivers
+v0x2853400_0 .net "AddSubSLTSum", 0 0, L_0x2abae10; 1 drivers
+v0x28534a0_0 .net "AxorB", 0 0, L_0x2abad20; 1 drivers
+v0x2853520_0 .net "B", 0 0, L_0x2aba4f0; 1 drivers
+v0x28535d0_0 .net "BornB", 0 0, L_0x2aba770; 1 drivers
+v0x2853690_0 .net "CINandAxorB", 0 0, L_0x2abb070; 1 drivers
+v0x2853710_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2853790_0 .net *"_s3", 0 0, L_0x2abaaa0; 1 drivers
+v0x2853810_0 .net *"_s5", 0 0, L_0x2abac80; 1 drivers
+v0x28538b0_0 .net "carryin", 0 0, L_0x2abb800; 1 drivers
+v0x2853950_0 .net "carryout", 0 0, L_0x2abb160; 1 drivers
+v0x28539f0_0 .net "nB", 0 0, L_0x2ab9f90; 1 drivers
+v0x2853aa0_0 .net "nCmd2", 0 0, L_0x2aba9e0; 1 drivers
+v0x2853ba0_0 .net "subtract", 0 0, L_0x2abab40; 1 drivers
+L_0x2aba940 .part v0x2960210_0, 0, 1;
+L_0x2abaaa0 .part v0x2960210_0, 2, 1;
+L_0x2abac80 .part v0x2960210_0, 0, 1;
+S_0x2852d00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2852c10;
+ .timescale -9 -12;
+L_0x2aba0a0/d .functor NOT 1, L_0x2aba940, C4<0>, C4<0>, C4<0>;
+L_0x2aba0a0 .delay (10000,10000,10000) L_0x2aba0a0/d;
+L_0x2aba160/d .functor AND 1, L_0x2aba4f0, L_0x2aba0a0, C4<1>, C4<1>;
+L_0x2aba160 .delay (20000,20000,20000) L_0x2aba160/d;
+L_0x2aba660/d .functor AND 1, L_0x2ab9f90, L_0x2aba940, C4<1>, C4<1>;
+L_0x2aba660 .delay (20000,20000,20000) L_0x2aba660/d;
+L_0x2aba770/d .functor OR 1, L_0x2aba160, L_0x2aba660, C4<0>, C4<0>;
+L_0x2aba770 .delay (20000,20000,20000) L_0x2aba770/d;
+v0x2852df0_0 .net "S", 0 0, L_0x2aba940; 1 drivers
+v0x2852e90_0 .alias "in0", 0 0, v0x2853520_0;
+v0x2852f30_0 .alias "in1", 0 0, v0x28539f0_0;
+v0x2852fd0_0 .net "nS", 0 0, L_0x2aba0a0; 1 drivers
+v0x2853080_0 .net "out0", 0 0, L_0x2aba160; 1 drivers
+v0x2853120_0 .net "out1", 0 0, L_0x2aba660; 1 drivers
+v0x2853200_0 .alias "outfinal", 0 0, v0x28535d0_0;
+S_0x2851900 .scope generate, "addbits[16]" "addbits[16]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2851318 .param/l "i" 3 283, +C4<010000>;
+S_0x2851a70 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2851900;
+ .timescale -9 -12;
+L_0x2aba590/d .functor NOT 1, L_0x2abba30, C4<0>, C4<0>, C4<0>;
+L_0x2aba590 .delay (10000,10000,10000) L_0x2aba590/d;
+L_0x2abbee0/d .functor NOT 1, L_0x2abbfa0, C4<0>, C4<0>, C4<0>;
+L_0x2abbee0 .delay (10000,10000,10000) L_0x2abbee0/d;
+L_0x2aaa490/d .functor AND 1, L_0x2abc0d0, L_0x2abbee0, C4<1>, C4<1>;
+L_0x2aaa490 .delay (20000,20000,20000) L_0x2aaa490/d;
+L_0x2abc170/d .functor XOR 1, L_0x2abb990, L_0x2abbc70, C4<0>, C4<0>;
+L_0x2abc170 .delay (40000,40000,40000) L_0x2abc170/d;
+L_0x2abc260/d .functor XOR 1, L_0x2abc170, L_0x2abcbd0, C4<0>, C4<0>;
+L_0x2abc260 .delay (40000,40000,40000) L_0x2abc260/d;
+L_0x2abc350/d .functor AND 1, L_0x2abb990, L_0x2abbc70, C4<1>, C4<1>;
+L_0x2abc350 .delay (20000,20000,20000) L_0x2abc350/d;
+L_0x2abc4c0/d .functor AND 1, L_0x2abc170, L_0x2abcbd0, C4<1>, C4<1>;
+L_0x2abc4c0 .delay (20000,20000,20000) L_0x2abc4c0/d;
+L_0x2abc5b0/d .functor OR 1, L_0x2abc350, L_0x2abc4c0, C4<0>, C4<0>;
+L_0x2abc5b0 .delay (20000,20000,20000) L_0x2abc5b0/d;
+v0x2852100_0 .net "A", 0 0, L_0x2abb990; 1 drivers
+v0x28521c0_0 .net "AandB", 0 0, L_0x2abc350; 1 drivers
+v0x2852260_0 .net "AddSubSLTSum", 0 0, L_0x2abc260; 1 drivers
+v0x2852300_0 .net "AxorB", 0 0, L_0x2abc170; 1 drivers
+v0x2852380_0 .net "B", 0 0, L_0x2abba30; 1 drivers
+v0x2852430_0 .net "BornB", 0 0, L_0x2abbc70; 1 drivers
+v0x28524f0_0 .net "CINandAxorB", 0 0, L_0x2abc4c0; 1 drivers
+v0x2852570_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28525f0_0 .net *"_s3", 0 0, L_0x2abbfa0; 1 drivers
+v0x2852670_0 .net *"_s5", 0 0, L_0x2abc0d0; 1 drivers
+v0x2852710_0 .net "carryin", 0 0, L_0x2abcbd0; 1 drivers
+v0x28527b0_0 .net "carryout", 0 0, L_0x2abc5b0; 1 drivers
+v0x2852850_0 .net "nB", 0 0, L_0x2aba590; 1 drivers
+v0x2852900_0 .net "nCmd2", 0 0, L_0x2abbee0; 1 drivers
+v0x2852a00_0 .net "subtract", 0 0, L_0x2aaa490; 1 drivers
+L_0x2abbe40 .part v0x2960210_0, 0, 1;
+L_0x2abbfa0 .part v0x2960210_0, 2, 1;
+L_0x2abc0d0 .part v0x2960210_0, 0, 1;
+S_0x2851b60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2851a70;
+ .timescale -9 -12;
+L_0x2abb580/d .functor NOT 1, L_0x2abbe40, C4<0>, C4<0>, C4<0>;
+L_0x2abb580 .delay (10000,10000,10000) L_0x2abb580/d;
+L_0x2abb640/d .functor AND 1, L_0x2abba30, L_0x2abb580, C4<1>, C4<1>;
+L_0x2abb640 .delay (20000,20000,20000) L_0x2abb640/d;
+L_0x2abbb80/d .functor AND 1, L_0x2aba590, L_0x2abbe40, C4<1>, C4<1>;
+L_0x2abbb80 .delay (20000,20000,20000) L_0x2abbb80/d;
+L_0x2abbc70/d .functor OR 1, L_0x2abb640, L_0x2abbb80, C4<0>, C4<0>;
+L_0x2abbc70 .delay (20000,20000,20000) L_0x2abbc70/d;
+v0x2851c50_0 .net "S", 0 0, L_0x2abbe40; 1 drivers
+v0x2851cf0_0 .alias "in0", 0 0, v0x2852380_0;
+v0x2851d90_0 .alias "in1", 0 0, v0x2852850_0;
+v0x2851e30_0 .net "nS", 0 0, L_0x2abb580; 1 drivers
+v0x2851ee0_0 .net "out0", 0 0, L_0x2abb640; 1 drivers
+v0x2851f80_0 .net "out1", 0 0, L_0x2abbb80; 1 drivers
+v0x2852060_0 .alias "outfinal", 0 0, v0x2852430_0;
+S_0x2850760 .scope generate, "addbits[17]" "addbits[17]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2850178 .param/l "i" 3 283, +C4<010001>;
+S_0x28508d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2850760;
+ .timescale -9 -12;
+L_0x2ab2470/d .functor NOT 1, L_0x2abd210, C4<0>, C4<0>, C4<0>;
+L_0x2ab2470 .delay (10000,10000,10000) L_0x2ab2470/d;
+L_0x2abd510/d .functor NOT 1, L_0x2abd5b0, C4<0>, C4<0>, C4<0>;
+L_0x2abd510 .delay (10000,10000,10000) L_0x2abd510/d;
+L_0x2abd650/d .functor AND 1, L_0x2abd790, L_0x2abd510, C4<1>, C4<1>;
+L_0x2abd650 .delay (20000,20000,20000) L_0x2abd650/d;
+L_0x2abd830/d .functor XOR 1, L_0x2abd170, L_0x2abcaf0, C4<0>, C4<0>;
+L_0x2abd830 .delay (40000,40000,40000) L_0x2abd830/d;
+L_0x2abd920/d .functor XOR 1, L_0x2abd830, L_0x2abe2c0, C4<0>, C4<0>;
+L_0x2abd920 .delay (40000,40000,40000) L_0x2abd920/d;
+L_0x2abda10/d .functor AND 1, L_0x2abd170, L_0x2abcaf0, C4<1>, C4<1>;
+L_0x2abda10 .delay (20000,20000,20000) L_0x2abda10/d;
+L_0x2abdb80/d .functor AND 1, L_0x2abd830, L_0x2abe2c0, C4<1>, C4<1>;
+L_0x2abdb80 .delay (20000,20000,20000) L_0x2abdb80/d;
+L_0x2abdc70/d .functor OR 1, L_0x2abda10, L_0x2abdb80, C4<0>, C4<0>;
+L_0x2abdc70 .delay (20000,20000,20000) L_0x2abdc70/d;
+v0x2850f60_0 .net "A", 0 0, L_0x2abd170; 1 drivers
+v0x2851020_0 .net "AandB", 0 0, L_0x2abda10; 1 drivers
+v0x28510c0_0 .net "AddSubSLTSum", 0 0, L_0x2abd920; 1 drivers
+v0x2851160_0 .net "AxorB", 0 0, L_0x2abd830; 1 drivers
+v0x28511e0_0 .net "B", 0 0, L_0x2abd210; 1 drivers
+v0x2851290_0 .net "BornB", 0 0, L_0x2abcaf0; 1 drivers
+v0x2851350_0 .net "CINandAxorB", 0 0, L_0x2abdb80; 1 drivers
+v0x28513d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2851450_0 .net *"_s3", 0 0, L_0x2abd5b0; 1 drivers
+v0x28514d0_0 .net *"_s5", 0 0, L_0x2abd790; 1 drivers
+v0x2851570_0 .net "carryin", 0 0, L_0x2abe2c0; 1 drivers
+v0x2851610_0 .net "carryout", 0 0, L_0x2abdc70; 1 drivers
+v0x28516b0_0 .net "nB", 0 0, L_0x2ab2470; 1 drivers
+v0x2851760_0 .net "nCmd2", 0 0, L_0x2abd510; 1 drivers
+v0x2851860_0 .net "subtract", 0 0, L_0x2abd650; 1 drivers
+L_0x2abd470 .part v0x2960210_0, 0, 1;
+L_0x2abd5b0 .part v0x2960210_0, 2, 1;
+L_0x2abd790 .part v0x2960210_0, 0, 1;
+S_0x28509c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28508d0;
+ .timescale -9 -12;
+L_0x2ab25b0/d .functor NOT 1, L_0x2abd470, C4<0>, C4<0>, C4<0>;
+L_0x2ab25b0 .delay (10000,10000,10000) L_0x2ab25b0/d;
+L_0x2abc8d0/d .functor AND 1, L_0x2abd210, L_0x2ab25b0, C4<1>, C4<1>;
+L_0x2abc8d0 .delay (20000,20000,20000) L_0x2abc8d0/d;
+L_0x2abc9e0/d .functor AND 1, L_0x2ab2470, L_0x2abd470, C4<1>, C4<1>;
+L_0x2abc9e0 .delay (20000,20000,20000) L_0x2abc9e0/d;
+L_0x2abcaf0/d .functor OR 1, L_0x2abc8d0, L_0x2abc9e0, C4<0>, C4<0>;
+L_0x2abcaf0 .delay (20000,20000,20000) L_0x2abcaf0/d;
+v0x2850ab0_0 .net "S", 0 0, L_0x2abd470; 1 drivers
+v0x2850b50_0 .alias "in0", 0 0, v0x28511e0_0;
+v0x2850bf0_0 .alias "in1", 0 0, v0x28516b0_0;
+v0x2850c90_0 .net "nS", 0 0, L_0x2ab25b0; 1 drivers
+v0x2850d40_0 .net "out0", 0 0, L_0x2abc8d0; 1 drivers
+v0x2850de0_0 .net "out1", 0 0, L_0x2abc9e0; 1 drivers
+v0x2850ec0_0 .alias "outfinal", 0 0, v0x2851290_0;
+S_0x284f5c0 .scope generate, "addbits[18]" "addbits[18]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x284efd8 .param/l "i" 3 283, +C4<010010>;
+S_0x284f730 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284f5c0;
+ .timescale -9 -12;
+L_0x2abdf90/d .functor NOT 1, L_0x2abe4f0, C4<0>, C4<0>, C4<0>;
+L_0x2abdf90 .delay (10000,10000,10000) L_0x2abdf90/d;
+L_0x2abe980/d .functor NOT 1, L_0x2abea20, C4<0>, C4<0>, C4<0>;
+L_0x2abe980 .delay (10000,10000,10000) L_0x2abe980/d;
+L_0x2abeac0/d .functor AND 1, L_0x2abec00, L_0x2abe980, C4<1>, C4<1>;
+L_0x2abeac0 .delay (20000,20000,20000) L_0x2abeac0/d;
+L_0x2abeca0/d .functor XOR 1, L_0x2abe450, L_0x2abe750, C4<0>, C4<0>;
+L_0x2abeca0 .delay (40000,40000,40000) L_0x2abeca0/d;
+L_0x2abed90/d .functor XOR 1, L_0x2abeca0, L_0x2abf760, C4<0>, C4<0>;
+L_0x2abed90 .delay (40000,40000,40000) L_0x2abed90/d;
+L_0x2abee80/d .functor AND 1, L_0x2abe450, L_0x2abe750, C4<1>, C4<1>;
+L_0x2abee80 .delay (20000,20000,20000) L_0x2abee80/d;
+L_0x2abeff0/d .functor AND 1, L_0x2abeca0, L_0x2abf760, C4<1>, C4<1>;
+L_0x2abeff0 .delay (20000,20000,20000) L_0x2abeff0/d;
+L_0x2abf0e0/d .functor OR 1, L_0x2abee80, L_0x2abeff0, C4<0>, C4<0>;
+L_0x2abf0e0 .delay (20000,20000,20000) L_0x2abf0e0/d;
+v0x284fdc0_0 .net "A", 0 0, L_0x2abe450; 1 drivers
+v0x284fe80_0 .net "AandB", 0 0, L_0x2abee80; 1 drivers
+v0x284ff20_0 .net "AddSubSLTSum", 0 0, L_0x2abed90; 1 drivers
+v0x284ffc0_0 .net "AxorB", 0 0, L_0x2abeca0; 1 drivers
+v0x2850040_0 .net "B", 0 0, L_0x2abe4f0; 1 drivers
+v0x28500f0_0 .net "BornB", 0 0, L_0x2abe750; 1 drivers
+v0x28501b0_0 .net "CINandAxorB", 0 0, L_0x2abeff0; 1 drivers
+v0x2850230_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28502b0_0 .net *"_s3", 0 0, L_0x2abea20; 1 drivers
+v0x2850330_0 .net *"_s5", 0 0, L_0x2abec00; 1 drivers
+v0x28503d0_0 .net "carryin", 0 0, L_0x2abf760; 1 drivers
+v0x2850470_0 .net "carryout", 0 0, L_0x2abf0e0; 1 drivers
+v0x2850510_0 .net "nB", 0 0, L_0x2abdf90; 1 drivers
+v0x28505c0_0 .net "nCmd2", 0 0, L_0x2abe980; 1 drivers
+v0x28506c0_0 .net "subtract", 0 0, L_0x2abeac0; 1 drivers
+L_0x2abe8e0 .part v0x2960210_0, 0, 1;
+L_0x2abea20 .part v0x2960210_0, 2, 1;
+L_0x2abec00 .part v0x2960210_0, 0, 1;
+S_0x284f820 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284f730;
+ .timescale -9 -12;
+L_0x2abe0a0/d .functor NOT 1, L_0x2abe8e0, C4<0>, C4<0>, C4<0>;
+L_0x2abe0a0 .delay (10000,10000,10000) L_0x2abe0a0/d;
+L_0x2abe160/d .functor AND 1, L_0x2abe4f0, L_0x2abe0a0, C4<1>, C4<1>;
+L_0x2abe160 .delay (20000,20000,20000) L_0x2abe160/d;
+L_0x2abe6a0/d .functor AND 1, L_0x2abdf90, L_0x2abe8e0, C4<1>, C4<1>;
+L_0x2abe6a0 .delay (20000,20000,20000) L_0x2abe6a0/d;
+L_0x2abe750/d .functor OR 1, L_0x2abe160, L_0x2abe6a0, C4<0>, C4<0>;
+L_0x2abe750 .delay (20000,20000,20000) L_0x2abe750/d;
+v0x284f910_0 .net "S", 0 0, L_0x2abe8e0; 1 drivers
+v0x284f9b0_0 .alias "in0", 0 0, v0x2850040_0;
+v0x284fa50_0 .alias "in1", 0 0, v0x2850510_0;
+v0x284faf0_0 .net "nS", 0 0, L_0x2abe0a0; 1 drivers
+v0x284fba0_0 .net "out0", 0 0, L_0x2abe160; 1 drivers
+v0x284fc40_0 .net "out1", 0 0, L_0x2abe6a0; 1 drivers
+v0x284fd20_0 .alias "outfinal", 0 0, v0x28500f0_0;
+S_0x284e420 .scope generate, "addbits[19]" "addbits[19]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x284de38 .param/l "i" 3 283, +C4<010011>;
+S_0x284e590 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284e420;
+ .timescale -9 -12;
+L_0x2abe620/d .functor NOT 1, L_0x2abf990, C4<0>, C4<0>, C4<0>;
+L_0x2abe620 .delay (10000,10000,10000) L_0x2abe620/d;
+L_0x2abfe30/d .functor NOT 1, L_0x2abfed0, C4<0>, C4<0>, C4<0>;
+L_0x2abfe30 .delay (10000,10000,10000) L_0x2abfe30/d;
+L_0x2abff70/d .functor AND 1, L_0x2ac00b0, L_0x2abfe30, C4<1>, C4<1>;
+L_0x2abff70 .delay (20000,20000,20000) L_0x2abff70/d;
+L_0x2ac0150/d .functor XOR 1, L_0x2abf8f0, L_0x2abfc00, C4<0>, C4<0>;
+L_0x2ac0150 .delay (40000,40000,40000) L_0x2ac0150/d;
+L_0x2ac0240/d .functor XOR 1, L_0x2ac0150, L_0x2abfac0, C4<0>, C4<0>;
+L_0x2ac0240 .delay (40000,40000,40000) L_0x2ac0240/d;
+L_0x2ac0330/d .functor AND 1, L_0x2abf8f0, L_0x2abfc00, C4<1>, C4<1>;
+L_0x2ac0330 .delay (20000,20000,20000) L_0x2ac0330/d;
+L_0x2ac04a0/d .functor AND 1, L_0x2ac0150, L_0x2abfac0, C4<1>, C4<1>;
+L_0x2ac04a0 .delay (20000,20000,20000) L_0x2ac04a0/d;
+L_0x2ac0590/d .functor OR 1, L_0x2ac0330, L_0x2ac04a0, C4<0>, C4<0>;
+L_0x2ac0590 .delay (20000,20000,20000) L_0x2ac0590/d;
+v0x284ec20_0 .net "A", 0 0, L_0x2abf8f0; 1 drivers
+v0x284ece0_0 .net "AandB", 0 0, L_0x2ac0330; 1 drivers
+v0x284ed80_0 .net "AddSubSLTSum", 0 0, L_0x2ac0240; 1 drivers
+v0x284ee20_0 .net "AxorB", 0 0, L_0x2ac0150; 1 drivers
+v0x284eea0_0 .net "B", 0 0, L_0x2abf990; 1 drivers
+v0x284ef50_0 .net "BornB", 0 0, L_0x2abfc00; 1 drivers
+v0x284f010_0 .net "CINandAxorB", 0 0, L_0x2ac04a0; 1 drivers
+v0x284f090_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x284f110_0 .net *"_s3", 0 0, L_0x2abfed0; 1 drivers
+v0x284f190_0 .net *"_s5", 0 0, L_0x2ac00b0; 1 drivers
+v0x284f230_0 .net "carryin", 0 0, L_0x2abfac0; 1 drivers
+v0x284f2d0_0 .net "carryout", 0 0, L_0x2ac0590; 1 drivers
+v0x284f370_0 .net "nB", 0 0, L_0x2abe620; 1 drivers
+v0x284f420_0 .net "nCmd2", 0 0, L_0x2abfe30; 1 drivers
+v0x284f520_0 .net "subtract", 0 0, L_0x2abff70; 1 drivers
+L_0x2abfd90 .part v0x2960210_0, 0, 1;
+L_0x2abfed0 .part v0x2960210_0, 2, 1;
+L_0x2ac00b0 .part v0x2960210_0, 0, 1;
+S_0x284e680 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284e590;
+ .timescale -9 -12;
+L_0x2abf4e0/d .functor NOT 1, L_0x2abfd90, C4<0>, C4<0>, C4<0>;
+L_0x2abf4e0 .delay (10000,10000,10000) L_0x2abf4e0/d;
+L_0x2abf5a0/d .functor AND 1, L_0x2abf990, L_0x2abf4e0, C4<1>, C4<1>;
+L_0x2abf5a0 .delay (20000,20000,20000) L_0x2abf5a0/d;
+L_0x2abf6b0/d .functor AND 1, L_0x2abe620, L_0x2abfd90, C4<1>, C4<1>;
+L_0x2abf6b0 .delay (20000,20000,20000) L_0x2abf6b0/d;
+L_0x2abfc00/d .functor OR 1, L_0x2abf5a0, L_0x2abf6b0, C4<0>, C4<0>;
+L_0x2abfc00 .delay (20000,20000,20000) L_0x2abfc00/d;
+v0x284e770_0 .net "S", 0 0, L_0x2abfd90; 1 drivers
+v0x284e810_0 .alias "in0", 0 0, v0x284eea0_0;
+v0x284e8b0_0 .alias "in1", 0 0, v0x284f370_0;
+v0x284e950_0 .net "nS", 0 0, L_0x2abf4e0; 1 drivers
+v0x284ea00_0 .net "out0", 0 0, L_0x2abf5a0; 1 drivers
+v0x284eaa0_0 .net "out1", 0 0, L_0x2abf6b0; 1 drivers
+v0x284eb80_0 .alias "outfinal", 0 0, v0x284ef50_0;
+S_0x284d280 .scope generate, "addbits[20]" "addbits[20]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x284cc98 .param/l "i" 3 283, +C4<010100>;
+S_0x284d3f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284d280;
+ .timescale -9 -12;
+L_0x2ac0c50/d .functor NOT 1, L_0x2ac0a40, C4<0>, C4<0>, C4<0>;
+L_0x2ac0c50 .delay (10000,10000,10000) L_0x2ac0c50/d;
+L_0x2ac1200/d .functor NOT 1, L_0x2ac12a0, C4<0>, C4<0>, C4<0>;
+L_0x2ac1200 .delay (10000,10000,10000) L_0x2ac1200/d;
+L_0x2ac1340/d .functor AND 1, L_0x2ac1480, L_0x2ac1200, C4<1>, C4<1>;
+L_0x2ac1340 .delay (20000,20000,20000) L_0x2ac1340/d;
+L_0x2ac1520/d .functor XOR 1, L_0x2ac09a0, L_0x2ac0fd0, C4<0>, C4<0>;
+L_0x2ac1520 .delay (40000,40000,40000) L_0x2ac1520/d;
+L_0x2ac1610/d .functor XOR 1, L_0x2ac1520, L_0x2ac0b70, C4<0>, C4<0>;
+L_0x2ac1610 .delay (40000,40000,40000) L_0x2ac1610/d;
+L_0x2ac1700/d .functor AND 1, L_0x2ac09a0, L_0x2ac0fd0, C4<1>, C4<1>;
+L_0x2ac1700 .delay (20000,20000,20000) L_0x2ac1700/d;
+L_0x2ac1870/d .functor AND 1, L_0x2ac1520, L_0x2ac0b70, C4<1>, C4<1>;
+L_0x2ac1870 .delay (20000,20000,20000) L_0x2ac1870/d;
+L_0x2ac1960/d .functor OR 1, L_0x2ac1700, L_0x2ac1870, C4<0>, C4<0>;
+L_0x2ac1960 .delay (20000,20000,20000) L_0x2ac1960/d;
+v0x284da80_0 .net "A", 0 0, L_0x2ac09a0; 1 drivers
+v0x284db40_0 .net "AandB", 0 0, L_0x2ac1700; 1 drivers
+v0x284dbe0_0 .net "AddSubSLTSum", 0 0, L_0x2ac1610; 1 drivers
+v0x284dc80_0 .net "AxorB", 0 0, L_0x2ac1520; 1 drivers
+v0x284dd00_0 .net "B", 0 0, L_0x2ac0a40; 1 drivers
+v0x284ddb0_0 .net "BornB", 0 0, L_0x2ac0fd0; 1 drivers
+v0x284de70_0 .net "CINandAxorB", 0 0, L_0x2ac1870; 1 drivers
+v0x284def0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x284df70_0 .net *"_s3", 0 0, L_0x2ac12a0; 1 drivers
+v0x284dff0_0 .net *"_s5", 0 0, L_0x2ac1480; 1 drivers
+v0x284e090_0 .net "carryin", 0 0, L_0x2ac0b70; 1 drivers
+v0x284e130_0 .net "carryout", 0 0, L_0x2ac1960; 1 drivers
+v0x284e1d0_0 .net "nB", 0 0, L_0x2ac0c50; 1 drivers
+v0x284e280_0 .net "nCmd2", 0 0, L_0x2ac1200; 1 drivers
+v0x284e380_0 .net "subtract", 0 0, L_0x2ac1340; 1 drivers
+L_0x2ac1160 .part v0x2960210_0, 0, 1;
+L_0x2ac12a0 .part v0x2960210_0, 2, 1;
+L_0x2ac1480 .part v0x2960210_0, 0, 1;
+S_0x284d4e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284d3f0;
+ .timescale -9 -12;
+L_0x2ac0d50/d .functor NOT 1, L_0x2ac1160, C4<0>, C4<0>, C4<0>;
+L_0x2ac0d50 .delay (10000,10000,10000) L_0x2ac0d50/d;
+L_0x2ac0df0/d .functor AND 1, L_0x2ac0a40, L_0x2ac0d50, C4<1>, C4<1>;
+L_0x2ac0df0 .delay (20000,20000,20000) L_0x2ac0df0/d;
+L_0x2ac0ee0/d .functor AND 1, L_0x2ac0c50, L_0x2ac1160, C4<1>, C4<1>;
+L_0x2ac0ee0 .delay (20000,20000,20000) L_0x2ac0ee0/d;
+L_0x2ac0fd0/d .functor OR 1, L_0x2ac0df0, L_0x2ac0ee0, C4<0>, C4<0>;
+L_0x2ac0fd0 .delay (20000,20000,20000) L_0x2ac0fd0/d;
+v0x284d5d0_0 .net "S", 0 0, L_0x2ac1160; 1 drivers
+v0x284d670_0 .alias "in0", 0 0, v0x284dd00_0;
+v0x284d710_0 .alias "in1", 0 0, v0x284e1d0_0;
+v0x284d7b0_0 .net "nS", 0 0, L_0x2ac0d50; 1 drivers
+v0x284d860_0 .net "out0", 0 0, L_0x2ac0df0; 1 drivers
+v0x284d900_0 .net "out1", 0 0, L_0x2ac0ee0; 1 drivers
+v0x284d9e0_0 .alias "outfinal", 0 0, v0x284ddb0_0;
+S_0x284c0e0 .scope generate, "addbits[21]" "addbits[21]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x284baf8 .param/l "i" 3 283, +C4<010101>;
+S_0x284c250 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284c0e0;
+ .timescale -9 -12;
+L_0x2ac2050/d .functor NOT 1, L_0x2ac1e10, C4<0>, C4<0>, C4<0>;
+L_0x2ac2050 .delay (10000,10000,10000) L_0x2ac2050/d;
+L_0x2ac25c0/d .functor NOT 1, L_0x2ac2660, C4<0>, C4<0>, C4<0>;
+L_0x2ac25c0 .delay (10000,10000,10000) L_0x2ac25c0/d;
+L_0x2ac2700/d .functor AND 1, L_0x2ac2840, L_0x2ac25c0, C4<1>, C4<1>;
+L_0x2ac2700 .delay (20000,20000,20000) L_0x2ac2700/d;
+L_0x2ac28e0/d .functor XOR 1, L_0x2ac1d70, L_0x2ac2390, C4<0>, C4<0>;
+L_0x2ac28e0 .delay (40000,40000,40000) L_0x2ac28e0/d;
+L_0x2ac29d0/d .functor XOR 1, L_0x2ac28e0, L_0x2ac1f40, C4<0>, C4<0>;
+L_0x2ac29d0 .delay (40000,40000,40000) L_0x2ac29d0/d;
+L_0x2ac2ac0/d .functor AND 1, L_0x2ac1d70, L_0x2ac2390, C4<1>, C4<1>;
+L_0x2ac2ac0 .delay (20000,20000,20000) L_0x2ac2ac0/d;
+L_0x2ac2c30/d .functor AND 1, L_0x2ac28e0, L_0x2ac1f40, C4<1>, C4<1>;
+L_0x2ac2c30 .delay (20000,20000,20000) L_0x2ac2c30/d;
+L_0x2ac2d20/d .functor OR 1, L_0x2ac2ac0, L_0x2ac2c30, C4<0>, C4<0>;
+L_0x2ac2d20 .delay (20000,20000,20000) L_0x2ac2d20/d;
+v0x284c8e0_0 .net "A", 0 0, L_0x2ac1d70; 1 drivers
+v0x284c9a0_0 .net "AandB", 0 0, L_0x2ac2ac0; 1 drivers
+v0x284ca40_0 .net "AddSubSLTSum", 0 0, L_0x2ac29d0; 1 drivers
+v0x284cae0_0 .net "AxorB", 0 0, L_0x2ac28e0; 1 drivers
+v0x284cb60_0 .net "B", 0 0, L_0x2ac1e10; 1 drivers
+v0x284cc10_0 .net "BornB", 0 0, L_0x2ac2390; 1 drivers
+v0x284ccd0_0 .net "CINandAxorB", 0 0, L_0x2ac2c30; 1 drivers
+v0x284cd50_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x284cdd0_0 .net *"_s3", 0 0, L_0x2ac2660; 1 drivers
+v0x284ce50_0 .net *"_s5", 0 0, L_0x2ac2840; 1 drivers
+v0x284cef0_0 .net "carryin", 0 0, L_0x2ac1f40; 1 drivers
+v0x284cf90_0 .net "carryout", 0 0, L_0x2ac2d20; 1 drivers
+v0x284d030_0 .net "nB", 0 0, L_0x2ac2050; 1 drivers
+v0x284d0e0_0 .net "nCmd2", 0 0, L_0x2ac25c0; 1 drivers
+v0x284d1e0_0 .net "subtract", 0 0, L_0x2ac2700; 1 drivers
+L_0x2ac2520 .part v0x2960210_0, 0, 1;
+L_0x2ac2660 .part v0x2960210_0, 2, 1;
+L_0x2ac2840 .part v0x2960210_0, 0, 1;
+S_0x284c340 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284c250;
+ .timescale -9 -12;
+L_0x2ac2150/d .functor NOT 1, L_0x2ac2520, C4<0>, C4<0>, C4<0>;
+L_0x2ac2150 .delay (10000,10000,10000) L_0x2ac2150/d;
+L_0x2ac21b0/d .functor AND 1, L_0x2ac1e10, L_0x2ac2150, C4<1>, C4<1>;
+L_0x2ac21b0 .delay (20000,20000,20000) L_0x2ac21b0/d;
+L_0x2ac22a0/d .functor AND 1, L_0x2ac2050, L_0x2ac2520, C4<1>, C4<1>;
+L_0x2ac22a0 .delay (20000,20000,20000) L_0x2ac22a0/d;
+L_0x2ac2390/d .functor OR 1, L_0x2ac21b0, L_0x2ac22a0, C4<0>, C4<0>;
+L_0x2ac2390 .delay (20000,20000,20000) L_0x2ac2390/d;
+v0x284c430_0 .net "S", 0 0, L_0x2ac2520; 1 drivers
+v0x284c4d0_0 .alias "in0", 0 0, v0x284cb60_0;
+v0x284c570_0 .alias "in1", 0 0, v0x284d030_0;
+v0x284c610_0 .net "nS", 0 0, L_0x2ac2150; 1 drivers
+v0x284c6c0_0 .net "out0", 0 0, L_0x2ac21b0; 1 drivers
+v0x284c760_0 .net "out1", 0 0, L_0x2ac22a0; 1 drivers
+v0x284c840_0 .alias "outfinal", 0 0, v0x284cc10_0;
+S_0x284af40 .scope generate, "addbits[22]" "addbits[22]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x284a958 .param/l "i" 3 283, +C4<010110>;
+S_0x284b0b0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x284af40;
+ .timescale -9 -12;
+L_0x2ac1fe0/d .functor NOT 1, L_0x2ac31d0, C4<0>, C4<0>, C4<0>;
+L_0x2ac1fe0 .delay (10000,10000,10000) L_0x2ac1fe0/d;
+L_0x2ac3a90/d .functor NOT 1, L_0x2ac3b50, C4<0>, C4<0>, C4<0>;
+L_0x2ac3a90 .delay (10000,10000,10000) L_0x2ac3a90/d;
+L_0x2ac3bf0/d .functor AND 1, L_0x2ac3d30, L_0x2ac3a90, C4<1>, C4<1>;
+L_0x2ac3bf0 .delay (20000,20000,20000) L_0x2ac3bf0/d;
+L_0x2ac3dd0/d .functor XOR 1, L_0x2ac3130, L_0x2ac3820, C4<0>, C4<0>;
+L_0x2ac3dd0 .delay (40000,40000,40000) L_0x2ac3dd0/d;
+L_0x2ac3ec0/d .functor XOR 1, L_0x2ac3dd0, L_0x2ac3300, C4<0>, C4<0>;
+L_0x2ac3ec0 .delay (40000,40000,40000) L_0x2ac3ec0/d;
+L_0x2ac3fb0/d .functor AND 1, L_0x2ac3130, L_0x2ac3820, C4<1>, C4<1>;
+L_0x2ac3fb0 .delay (20000,20000,20000) L_0x2ac3fb0/d;
+L_0x2ac4120/d .functor AND 1, L_0x2ac3dd0, L_0x2ac3300, C4<1>, C4<1>;
+L_0x2ac4120 .delay (20000,20000,20000) L_0x2ac4120/d;
+L_0x2ac4210/d .functor OR 1, L_0x2ac3fb0, L_0x2ac4120, C4<0>, C4<0>;
+L_0x2ac4210 .delay (20000,20000,20000) L_0x2ac4210/d;
+v0x284b740_0 .net "A", 0 0, L_0x2ac3130; 1 drivers
+v0x284b800_0 .net "AandB", 0 0, L_0x2ac3fb0; 1 drivers
+v0x284b8a0_0 .net "AddSubSLTSum", 0 0, L_0x2ac3ec0; 1 drivers
+v0x284b940_0 .net "AxorB", 0 0, L_0x2ac3dd0; 1 drivers
+v0x284b9c0_0 .net "B", 0 0, L_0x2ac31d0; 1 drivers
+v0x284ba70_0 .net "BornB", 0 0, L_0x2ac3820; 1 drivers
+v0x284bb30_0 .net "CINandAxorB", 0 0, L_0x2ac4120; 1 drivers
+v0x284bbb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x284bc30_0 .net *"_s3", 0 0, L_0x2ac3b50; 1 drivers
+v0x284bcb0_0 .net *"_s5", 0 0, L_0x2ac3d30; 1 drivers
+v0x284bd50_0 .net "carryin", 0 0, L_0x2ac3300; 1 drivers
+v0x284bdf0_0 .net "carryout", 0 0, L_0x2ac4210; 1 drivers
+v0x284be90_0 .net "nB", 0 0, L_0x2ac1fe0; 1 drivers
+v0x284bf40_0 .net "nCmd2", 0 0, L_0x2ac3a90; 1 drivers
+v0x284c040_0 .net "subtract", 0 0, L_0x2ac3bf0; 1 drivers
+L_0x2ac39f0 .part v0x2960210_0, 0, 1;
+L_0x2ac3b50 .part v0x2960210_0, 2, 1;
+L_0x2ac3d30 .part v0x2960210_0, 0, 1;
+S_0x284b1a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x284b0b0;
+ .timescale -9 -12;
+L_0x2ac3540/d .functor NOT 1, L_0x2ac39f0, C4<0>, C4<0>, C4<0>;
+L_0x2ac3540 .delay (10000,10000,10000) L_0x2ac3540/d;
+L_0x2ac3600/d .functor AND 1, L_0x2ac31d0, L_0x2ac3540, C4<1>, C4<1>;
+L_0x2ac3600 .delay (20000,20000,20000) L_0x2ac3600/d;
+L_0x2ac3710/d .functor AND 1, L_0x2ac1fe0, L_0x2ac39f0, C4<1>, C4<1>;
+L_0x2ac3710 .delay (20000,20000,20000) L_0x2ac3710/d;
+L_0x2ac3820/d .functor OR 1, L_0x2ac3600, L_0x2ac3710, C4<0>, C4<0>;
+L_0x2ac3820 .delay (20000,20000,20000) L_0x2ac3820/d;
+v0x284b290_0 .net "S", 0 0, L_0x2ac39f0; 1 drivers
+v0x284b330_0 .alias "in0", 0 0, v0x284b9c0_0;
+v0x284b3d0_0 .alias "in1", 0 0, v0x284be90_0;
+v0x284b470_0 .net "nS", 0 0, L_0x2ac3540; 1 drivers
+v0x284b520_0 .net "out0", 0 0, L_0x2ac3600; 1 drivers
+v0x284b5c0_0 .net "out1", 0 0, L_0x2ac3710; 1 drivers
+v0x284b6a0_0 .alias "outfinal", 0 0, v0x284ba70_0;
+S_0x2849dd0 .scope generate, "addbits[23]" "addbits[23]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28496a8 .param/l "i" 3 283, +C4<010111>;
+S_0x2849f40 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2849dd0;
+ .timescale -9 -12;
+L_0x2ac33a0/d .functor NOT 1, L_0x2ac46e0, C4<0>, C4<0>, C4<0>;
+L_0x2ac33a0 .delay (10000,10000,10000) L_0x2ac33a0/d;
+L_0x2ac4e90/d .functor NOT 1, L_0x2ac4f30, C4<0>, C4<0>, C4<0>;
+L_0x2ac4e90 .delay (10000,10000,10000) L_0x2ac4e90/d;
+L_0x2ac4fd0/d .functor AND 1, L_0x2ac5110, L_0x2ac4e90, C4<1>, C4<1>;
+L_0x2ac4fd0 .delay (20000,20000,20000) L_0x2ac4fd0/d;
+L_0x2ac51b0/d .functor XOR 1, L_0x2ac4640, L_0x2ac4c60, C4<0>, C4<0>;
+L_0x2ac51b0 .delay (40000,40000,40000) L_0x2ac51b0/d;
+L_0x2ac52a0/d .functor XOR 1, L_0x2ac51b0, L_0x2ac4810, C4<0>, C4<0>;
+L_0x2ac52a0 .delay (40000,40000,40000) L_0x2ac52a0/d;
+L_0x2ac5390/d .functor AND 1, L_0x2ac4640, L_0x2ac4c60, C4<1>, C4<1>;
+L_0x2ac5390 .delay (20000,20000,20000) L_0x2ac5390/d;
+L_0x2ac5500/d .functor AND 1, L_0x2ac51b0, L_0x2ac4810, C4<1>, C4<1>;
+L_0x2ac5500 .delay (20000,20000,20000) L_0x2ac5500/d;
+L_0x2ac55f0/d .functor OR 1, L_0x2ac5390, L_0x2ac5500, C4<0>, C4<0>;
+L_0x2ac55f0 .delay (20000,20000,20000) L_0x2ac55f0/d;
+v0x284a5a0_0 .net "A", 0 0, L_0x2ac4640; 1 drivers
+v0x284a660_0 .net "AandB", 0 0, L_0x2ac5390; 1 drivers
+v0x284a700_0 .net "AddSubSLTSum", 0 0, L_0x2ac52a0; 1 drivers
+v0x284a7a0_0 .net "AxorB", 0 0, L_0x2ac51b0; 1 drivers
+v0x284a820_0 .net "B", 0 0, L_0x2ac46e0; 1 drivers
+v0x284a8d0_0 .net "BornB", 0 0, L_0x2ac4c60; 1 drivers
+v0x284a990_0 .net "CINandAxorB", 0 0, L_0x2ac5500; 1 drivers
+v0x284aa10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x284aa90_0 .net *"_s3", 0 0, L_0x2ac4f30; 1 drivers
+v0x284ab10_0 .net *"_s5", 0 0, L_0x2ac5110; 1 drivers
+v0x284abb0_0 .net "carryin", 0 0, L_0x2ac4810; 1 drivers
+v0x284ac50_0 .net "carryout", 0 0, L_0x2ac55f0; 1 drivers
+v0x284acf0_0 .net "nB", 0 0, L_0x2ac33a0; 1 drivers
+v0x284ada0_0 .net "nCmd2", 0 0, L_0x2ac4e90; 1 drivers
+v0x284aea0_0 .net "subtract", 0 0, L_0x2ac4fd0; 1 drivers
+L_0x2ac4df0 .part v0x2960210_0, 0, 1;
+L_0x2ac4f30 .part v0x2960210_0, 2, 1;
+L_0x2ac5110 .part v0x2960210_0, 0, 1;
+S_0x284a030 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2849f40;
+ .timescale -9 -12;
+L_0x2ac4a20/d .functor NOT 1, L_0x2ac4df0, C4<0>, C4<0>, C4<0>;
+L_0x2ac4a20 .delay (10000,10000,10000) L_0x2ac4a20/d;
+L_0x2ac4a80/d .functor AND 1, L_0x2ac46e0, L_0x2ac4a20, C4<1>, C4<1>;
+L_0x2ac4a80 .delay (20000,20000,20000) L_0x2ac4a80/d;
+L_0x2ac4b70/d .functor AND 1, L_0x2ac33a0, L_0x2ac4df0, C4<1>, C4<1>;
+L_0x2ac4b70 .delay (20000,20000,20000) L_0x2ac4b70/d;
+L_0x2ac4c60/d .functor OR 1, L_0x2ac4a80, L_0x2ac4b70, C4<0>, C4<0>;
+L_0x2ac4c60 .delay (20000,20000,20000) L_0x2ac4c60/d;
+v0x284a120_0 .net "S", 0 0, L_0x2ac4df0; 1 drivers
+v0x284a1c0_0 .alias "in0", 0 0, v0x284a820_0;
+v0x284a260_0 .alias "in1", 0 0, v0x284acf0_0;
+v0x284a300_0 .net "nS", 0 0, L_0x2ac4a20; 1 drivers
+v0x284a380_0 .net "out0", 0 0, L_0x2ac4a80; 1 drivers
+v0x284a420_0 .net "out1", 0 0, L_0x2ac4b70; 1 drivers
+v0x284a500_0 .alias "outfinal", 0 0, v0x284a8d0_0;
+S_0x2848be0 .scope generate, "addbits[24]" "addbits[24]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28485f8 .param/l "i" 3 283, +C4<011000>;
+S_0x2848d50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2848be0;
+ .timescale -9 -12;
+L_0x2ac48b0/d .functor NOT 1, L_0x2ac5aa0, C4<0>, C4<0>, C4<0>;
+L_0x2ac48b0 .delay (10000,10000,10000) L_0x2ac48b0/d;
+L_0x2ac6270/d .functor NOT 1, L_0x2ac6330, C4<0>, C4<0>, C4<0>;
+L_0x2ac6270 .delay (10000,10000,10000) L_0x2ac6270/d;
+L_0x2ac63d0/d .functor AND 1, L_0x2ac6510, L_0x2ac6270, C4<1>, C4<1>;
+L_0x2ac63d0 .delay (20000,20000,20000) L_0x2ac63d0/d;
+L_0x2ac65b0/d .functor XOR 1, L_0x2ac5a00, L_0x2ac6040, C4<0>, C4<0>;
+L_0x2ac65b0 .delay (40000,40000,40000) L_0x2ac65b0/d;
+L_0x2ac66a0/d .functor XOR 1, L_0x2ac65b0, L_0x2ac5bd0, C4<0>, C4<0>;
+L_0x2ac66a0 .delay (40000,40000,40000) L_0x2ac66a0/d;
+L_0x2ac6790/d .functor AND 1, L_0x2ac5a00, L_0x2ac6040, C4<1>, C4<1>;
+L_0x2ac6790 .delay (20000,20000,20000) L_0x2ac6790/d;
+L_0x2ac6900/d .functor AND 1, L_0x2ac65b0, L_0x2ac5bd0, C4<1>, C4<1>;
+L_0x2ac6900 .delay (20000,20000,20000) L_0x2ac6900/d;
+L_0x2ac6a10/d .functor OR 1, L_0x2ac6790, L_0x2ac6900, C4<0>, C4<0>;
+L_0x2ac6a10 .delay (20000,20000,20000) L_0x2ac6a10/d;
+v0x28492f0_0 .net "A", 0 0, L_0x2ac5a00; 1 drivers
+v0x28493b0_0 .net "AandB", 0 0, L_0x2ac6790; 1 drivers
+v0x2849450_0 .net "AddSubSLTSum", 0 0, L_0x2ac66a0; 1 drivers
+v0x28494f0_0 .net "AxorB", 0 0, L_0x2ac65b0; 1 drivers
+v0x2849570_0 .net "B", 0 0, L_0x2ac5aa0; 1 drivers
+v0x2849620_0 .net "BornB", 0 0, L_0x2ac6040; 1 drivers
+v0x28496e0_0 .net "CINandAxorB", 0 0, L_0x2ac6900; 1 drivers
+v0x2849760_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2849830_0 .net *"_s3", 0 0, L_0x2ac6330; 1 drivers
+v0x28498b0_0 .net *"_s5", 0 0, L_0x2ac6510; 1 drivers
+v0x28499b0_0 .net "carryin", 0 0, L_0x2ac5bd0; 1 drivers
+v0x2849a50_0 .net "carryout", 0 0, L_0x2ac6a10; 1 drivers
+v0x2849b60_0 .net "nB", 0 0, L_0x2ac48b0; 1 drivers
+v0x2849c10_0 .net "nCmd2", 0 0, L_0x2ac6270; 1 drivers
+v0x2849d30_0 .net "subtract", 0 0, L_0x2ac63d0; 1 drivers
+L_0x2ac61d0 .part v0x2960210_0, 0, 1;
+L_0x2ac6330 .part v0x2960210_0, 2, 1;
+L_0x2ac6510 .part v0x2960210_0, 0, 1;
+S_0x2848e40 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2848d50;
+ .timescale -9 -12;
+L_0x2ac5dc0/d .functor NOT 1, L_0x2ac61d0, C4<0>, C4<0>, C4<0>;
+L_0x2ac5dc0 .delay (10000,10000,10000) L_0x2ac5dc0/d;
+L_0x2ac5e60/d .functor AND 1, L_0x2ac5aa0, L_0x2ac5dc0, C4<1>, C4<1>;
+L_0x2ac5e60 .delay (20000,20000,20000) L_0x2ac5e60/d;
+L_0x2ac5f50/d .functor AND 1, L_0x2ac48b0, L_0x2ac61d0, C4<1>, C4<1>;
+L_0x2ac5f50 .delay (20000,20000,20000) L_0x2ac5f50/d;
+L_0x2ac6040/d .functor OR 1, L_0x2ac5e60, L_0x2ac5f50, C4<0>, C4<0>;
+L_0x2ac6040 .delay (20000,20000,20000) L_0x2ac6040/d;
+v0x2848f30_0 .net "S", 0 0, L_0x2ac61d0; 1 drivers
+v0x2848fd0_0 .alias "in0", 0 0, v0x2849570_0;
+v0x2849050_0 .alias "in1", 0 0, v0x2849b60_0;
+v0x28490d0_0 .net "nS", 0 0, L_0x2ac5dc0; 1 drivers
+v0x2849150_0 .net "out0", 0 0, L_0x2ac5e60; 1 drivers
+v0x28491d0_0 .net "out1", 0 0, L_0x2ac5f50; 1 drivers
+v0x2849250_0 .alias "outfinal", 0 0, v0x2849620_0;
+S_0x2847a40 .scope generate, "addbits[25]" "addbits[25]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2847458 .param/l "i" 3 283, +C4<011001>;
+S_0x2847bb0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2847a40;
+ .timescale -9 -12;
+L_0x2841da0/d .functor NOT 1, L_0x29c6dc0, C4<0>, C4<0>, C4<0>;
+L_0x2841da0 .delay (10000,10000,10000) L_0x2841da0/d;
+L_0x2ac6ef0/d .functor NOT 1, L_0x2ac6fb0, C4<0>, C4<0>, C4<0>;
+L_0x2ac6ef0 .delay (10000,10000,10000) L_0x2ac6ef0/d;
+L_0x2ac7050/d .functor AND 1, L_0x2ac81d0, L_0x2ac6ef0, C4<1>, C4<1>;
+L_0x2ac7050 .delay (20000,20000,20000) L_0x2ac7050/d;
+L_0x2ac8270/d .functor XOR 1, L_0x29c6d20, L_0x29c7360, C4<0>, C4<0>;
+L_0x2ac8270 .delay (40000,40000,40000) L_0x2ac8270/d;
+L_0x2ac8360/d .functor XOR 1, L_0x2ac8270, L_0x29c6ef0, C4<0>, C4<0>;
+L_0x2ac8360 .delay (40000,40000,40000) L_0x2ac8360/d;
+L_0x2ac8450/d .functor AND 1, L_0x29c6d20, L_0x29c7360, C4<1>, C4<1>;
+L_0x2ac8450 .delay (20000,20000,20000) L_0x2ac8450/d;
+L_0x2ac85c0/d .functor AND 1, L_0x2ac8270, L_0x29c6ef0, C4<1>, C4<1>;
+L_0x2ac85c0 .delay (20000,20000,20000) L_0x2ac85c0/d;
+L_0x2ac86d0/d .functor OR 1, L_0x2ac8450, L_0x2ac85c0, C4<0>, C4<0>;
+L_0x2ac86d0 .delay (20000,20000,20000) L_0x2ac86d0/d;
+v0x2848240_0 .net "A", 0 0, L_0x29c6d20; 1 drivers
+v0x2848300_0 .net "AandB", 0 0, L_0x2ac8450; 1 drivers
+v0x28483a0_0 .net "AddSubSLTSum", 0 0, L_0x2ac8360; 1 drivers
+v0x2848440_0 .net "AxorB", 0 0, L_0x2ac8270; 1 drivers
+v0x28484c0_0 .net "B", 0 0, L_0x29c6dc0; 1 drivers
+v0x2848570_0 .net "BornB", 0 0, L_0x29c7360; 1 drivers
+v0x2848630_0 .net "CINandAxorB", 0 0, L_0x2ac85c0; 1 drivers
+v0x28486b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2848730_0 .net *"_s3", 0 0, L_0x2ac6fb0; 1 drivers
+v0x28487b0_0 .net *"_s5", 0 0, L_0x2ac81d0; 1 drivers
+v0x2848850_0 .net "carryin", 0 0, L_0x29c6ef0; 1 drivers
+v0x28488f0_0 .net "carryout", 0 0, L_0x2ac86d0; 1 drivers
+v0x2848990_0 .net "nB", 0 0, L_0x2841da0; 1 drivers
+v0x2848a40_0 .net "nCmd2", 0 0, L_0x2ac6ef0; 1 drivers
+v0x2848b40_0 .net "subtract", 0 0, L_0x2ac7050; 1 drivers
+L_0x2ac6e50 .part v0x2960210_0, 0, 1;
+L_0x2ac6fb0 .part v0x2960210_0, 2, 1;
+L_0x2ac81d0 .part v0x2960210_0, 0, 1;
+S_0x2847ca0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2847bb0;
+ .timescale -9 -12;
+L_0x29c70c0/d .functor NOT 1, L_0x2ac6e50, C4<0>, C4<0>, C4<0>;
+L_0x29c70c0 .delay (10000,10000,10000) L_0x29c70c0/d;
+L_0x29c7140/d .functor AND 1, L_0x29c6dc0, L_0x29c70c0, C4<1>, C4<1>;
+L_0x29c7140 .delay (20000,20000,20000) L_0x29c7140/d;
+L_0x29c7250/d .functor AND 1, L_0x2841da0, L_0x2ac6e50, C4<1>, C4<1>;
+L_0x29c7250 .delay (20000,20000,20000) L_0x29c7250/d;
+L_0x29c7360/d .functor OR 1, L_0x29c7140, L_0x29c7250, C4<0>, C4<0>;
+L_0x29c7360 .delay (20000,20000,20000) L_0x29c7360/d;
+v0x2847d90_0 .net "S", 0 0, L_0x2ac6e50; 1 drivers
+v0x2847e30_0 .alias "in0", 0 0, v0x28484c0_0;
+v0x2847ed0_0 .alias "in1", 0 0, v0x2848990_0;
+v0x2847f70_0 .net "nS", 0 0, L_0x29c70c0; 1 drivers
+v0x2848020_0 .net "out0", 0 0, L_0x29c7140; 1 drivers
+v0x28480c0_0 .net "out1", 0 0, L_0x29c7250; 1 drivers
+v0x28481a0_0 .alias "outfinal", 0 0, v0x2848570_0;
+S_0x28468a0 .scope generate, "addbits[26]" "addbits[26]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28462b8 .param/l "i" 3 283, +C4<011010>;
+S_0x2846a10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x28468a0;
+ .timescale -9 -12;
+L_0x29c6f90/d .functor NOT 1, L_0x2ac8ba0, C4<0>, C4<0>, C4<0>;
+L_0x29c6f90 .delay (10000,10000,10000) L_0x29c6f90/d;
+L_0x2ac93b0/d .functor NOT 1, L_0x2ac9470, C4<0>, C4<0>, C4<0>;
+L_0x2ac93b0 .delay (10000,10000,10000) L_0x2ac93b0/d;
+L_0x2ac9510/d .functor AND 1, L_0x2ac9650, L_0x2ac93b0, C4<1>, C4<1>;
+L_0x2ac9510 .delay (20000,20000,20000) L_0x2ac9510/d;
+L_0x2ac96f0/d .functor XOR 1, L_0x2ac8b00, L_0x2ac9140, C4<0>, C4<0>;
+L_0x2ac96f0 .delay (40000,40000,40000) L_0x2ac96f0/d;
+L_0x2ac97e0/d .functor XOR 1, L_0x2ac96f0, L_0x2ac8cd0, C4<0>, C4<0>;
+L_0x2ac97e0 .delay (40000,40000,40000) L_0x2ac97e0/d;
+L_0x2ac9900/d .functor AND 1, L_0x2ac8b00, L_0x2ac9140, C4<1>, C4<1>;
+L_0x2ac9900 .delay (20000,20000,20000) L_0x2ac9900/d;
+L_0x2ac9aa0/d .functor AND 1, L_0x2ac96f0, L_0x2ac8cd0, C4<1>, C4<1>;
+L_0x2ac9aa0 .delay (20000,20000,20000) L_0x2ac9aa0/d;
+L_0x2ac9bb0/d .functor OR 1, L_0x2ac9900, L_0x2ac9aa0, C4<0>, C4<0>;
+L_0x2ac9bb0 .delay (20000,20000,20000) L_0x2ac9bb0/d;
+v0x28470a0_0 .net "A", 0 0, L_0x2ac8b00; 1 drivers
+v0x2847160_0 .net "AandB", 0 0, L_0x2ac9900; 1 drivers
+v0x2847200_0 .net "AddSubSLTSum", 0 0, L_0x2ac97e0; 1 drivers
+v0x28472a0_0 .net "AxorB", 0 0, L_0x2ac96f0; 1 drivers
+v0x2847320_0 .net "B", 0 0, L_0x2ac8ba0; 1 drivers
+v0x28473d0_0 .net "BornB", 0 0, L_0x2ac9140; 1 drivers
+v0x2847490_0 .net "CINandAxorB", 0 0, L_0x2ac9aa0; 1 drivers
+v0x2847510_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2847590_0 .net *"_s3", 0 0, L_0x2ac9470; 1 drivers
+v0x2847610_0 .net *"_s5", 0 0, L_0x2ac9650; 1 drivers
+v0x28476b0_0 .net "carryin", 0 0, L_0x2ac8cd0; 1 drivers
+v0x2847750_0 .net "carryout", 0 0, L_0x2ac9bb0; 1 drivers
+v0x28477f0_0 .net "nB", 0 0, L_0x29c6f90; 1 drivers
+v0x28478a0_0 .net "nCmd2", 0 0, L_0x2ac93b0; 1 drivers
+v0x28479a0_0 .net "subtract", 0 0, L_0x2ac9510; 1 drivers
+L_0x2ac9310 .part v0x2960210_0, 0, 1;
+L_0x2ac9470 .part v0x2960210_0, 2, 1;
+L_0x2ac9650 .part v0x2960210_0, 0, 1;
+S_0x2846b00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2846a10;
+ .timescale -9 -12;
+L_0x29c7060/d .functor NOT 1, L_0x2ac9310, C4<0>, C4<0>, C4<0>;
+L_0x29c7060 .delay (10000,10000,10000) L_0x29c7060/d;
+L_0x2ac8f60/d .functor AND 1, L_0x2ac8ba0, L_0x29c7060, C4<1>, C4<1>;
+L_0x2ac8f60 .delay (20000,20000,20000) L_0x2ac8f60/d;
+L_0x2ac9050/d .functor AND 1, L_0x29c6f90, L_0x2ac9310, C4<1>, C4<1>;
+L_0x2ac9050 .delay (20000,20000,20000) L_0x2ac9050/d;
+L_0x2ac9140/d .functor OR 1, L_0x2ac8f60, L_0x2ac9050, C4<0>, C4<0>;
+L_0x2ac9140 .delay (20000,20000,20000) L_0x2ac9140/d;
+v0x2846bf0_0 .net "S", 0 0, L_0x2ac9310; 1 drivers
+v0x2846c90_0 .alias "in0", 0 0, v0x2847320_0;
+v0x2846d30_0 .alias "in1", 0 0, v0x28477f0_0;
+v0x2846dd0_0 .net "nS", 0 0, L_0x29c7060; 1 drivers
+v0x2846e80_0 .net "out0", 0 0, L_0x2ac8f60; 1 drivers
+v0x2846f20_0 .net "out1", 0 0, L_0x2ac9050; 1 drivers
+v0x2847000_0 .alias "outfinal", 0 0, v0x28473d0_0;
+S_0x2845700 .scope generate, "addbits[27]" "addbits[27]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2845118 .param/l "i" 3 283, +C4<011011>;
+S_0x2845870 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2845700;
+ .timescale -9 -12;
+L_0x2ac8d70/d .functor NOT 1, L_0x2aca080, C4<0>, C4<0>, C4<0>;
+L_0x2ac8d70 .delay (10000,10000,10000) L_0x2ac8d70/d;
+L_0x2aca890/d .functor NOT 1, L_0x2aca950, C4<0>, C4<0>, C4<0>;
+L_0x2aca890 .delay (10000,10000,10000) L_0x2aca890/d;
+L_0x2aca9f0/d .functor AND 1, L_0x2acab30, L_0x2aca890, C4<1>, C4<1>;
+L_0x2aca9f0 .delay (20000,20000,20000) L_0x2aca9f0/d;
+L_0x29978a0/d .functor XOR 1, L_0x2ac9fe0, L_0x2aca620, C4<0>, C4<0>;
+L_0x29978a0 .delay (40000,40000,40000) L_0x29978a0/d;
+L_0x2997990/d .functor XOR 1, L_0x29978a0, L_0x2aca1b0, C4<0>, C4<0>;
+L_0x2997990 .delay (40000,40000,40000) L_0x2997990/d;
+L_0x2997ab0/d .functor AND 1, L_0x2ac9fe0, L_0x2aca620, C4<1>, C4<1>;
+L_0x2997ab0 .delay (20000,20000,20000) L_0x2997ab0/d;
+L_0x2997c50/d .functor AND 1, L_0x29978a0, L_0x2aca1b0, C4<1>, C4<1>;
+L_0x2997c50 .delay (20000,20000,20000) L_0x2997c50/d;
+L_0x2997d60/d .functor OR 1, L_0x2997ab0, L_0x2997c50, C4<0>, C4<0>;
+L_0x2997d60 .delay (20000,20000,20000) L_0x2997d60/d;
+v0x2845f00_0 .net "A", 0 0, L_0x2ac9fe0; 1 drivers
+v0x2845fc0_0 .net "AandB", 0 0, L_0x2997ab0; 1 drivers
+v0x2846060_0 .net "AddSubSLTSum", 0 0, L_0x2997990; 1 drivers
+v0x2846100_0 .net "AxorB", 0 0, L_0x29978a0; 1 drivers
+v0x2846180_0 .net "B", 0 0, L_0x2aca080; 1 drivers
+v0x2846230_0 .net "BornB", 0 0, L_0x2aca620; 1 drivers
+v0x28462f0_0 .net "CINandAxorB", 0 0, L_0x2997c50; 1 drivers
+v0x2846370_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28463f0_0 .net *"_s3", 0 0, L_0x2aca950; 1 drivers
+v0x2846470_0 .net *"_s5", 0 0, L_0x2acab30; 1 drivers
+v0x2846510_0 .net "carryin", 0 0, L_0x2aca1b0; 1 drivers
+v0x28465b0_0 .net "carryout", 0 0, L_0x2997d60; 1 drivers
+v0x2846650_0 .net "nB", 0 0, L_0x2ac8d70; 1 drivers
+v0x2846700_0 .net "nCmd2", 0 0, L_0x2aca890; 1 drivers
+v0x2846800_0 .net "subtract", 0 0, L_0x2aca9f0; 1 drivers
+L_0x2aca7f0 .part v0x2960210_0, 0, 1;
+L_0x2aca950 .part v0x2960210_0, 2, 1;
+L_0x2acab30 .part v0x2960210_0, 0, 1;
+S_0x2845960 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2845870;
+ .timescale -9 -12;
+L_0x2aca3e0/d .functor NOT 1, L_0x2aca7f0, C4<0>, C4<0>, C4<0>;
+L_0x2aca3e0 .delay (10000,10000,10000) L_0x2aca3e0/d;
+L_0x2aca440/d .functor AND 1, L_0x2aca080, L_0x2aca3e0, C4<1>, C4<1>;
+L_0x2aca440 .delay (20000,20000,20000) L_0x2aca440/d;
+L_0x2aca530/d .functor AND 1, L_0x2ac8d70, L_0x2aca7f0, C4<1>, C4<1>;
+L_0x2aca530 .delay (20000,20000,20000) L_0x2aca530/d;
+L_0x2aca620/d .functor OR 1, L_0x2aca440, L_0x2aca530, C4<0>, C4<0>;
+L_0x2aca620 .delay (20000,20000,20000) L_0x2aca620/d;
+v0x2845a50_0 .net "S", 0 0, L_0x2aca7f0; 1 drivers
+v0x2845af0_0 .alias "in0", 0 0, v0x2846180_0;
+v0x2845b90_0 .alias "in1", 0 0, v0x2846650_0;
+v0x2845c30_0 .net "nS", 0 0, L_0x2aca3e0; 1 drivers
+v0x2845ce0_0 .net "out0", 0 0, L_0x2aca440; 1 drivers
+v0x2845d80_0 .net "out1", 0 0, L_0x2aca530; 1 drivers
+v0x2845e60_0 .alias "outfinal", 0 0, v0x2846230_0;
+S_0x2844560 .scope generate, "addbits[28]" "addbits[28]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2843f78 .param/l "i" 3 283, +C4<011100>;
+S_0x28446d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2844560;
+ .timescale -9 -12;
+L_0x2aca250/d .functor NOT 1, L_0x2998230, C4<0>, C4<0>, C4<0>;
+L_0x2aca250 .delay (10000,10000,10000) L_0x2aca250/d;
+L_0x2998b10/d .functor NOT 1, L_0x2998bd0, C4<0>, C4<0>, C4<0>;
+L_0x2998b10 .delay (10000,10000,10000) L_0x2998b10/d;
+L_0x2998c70/d .functor AND 1, L_0x2998db0, L_0x2998b10, C4<1>, C4<1>;
+L_0x2998c70 .delay (20000,20000,20000) L_0x2998c70/d;
+L_0x2998e50/d .functor XOR 1, L_0x2998190, L_0x29988a0, C4<0>, C4<0>;
+L_0x2998e50 .delay (40000,40000,40000) L_0x2998e50/d;
+L_0x2998f40/d .functor XOR 1, L_0x2998e50, L_0x2998360, C4<0>, C4<0>;
+L_0x2998f40 .delay (40000,40000,40000) L_0x2998f40/d;
+L_0x2999030/d .functor AND 1, L_0x2998190, L_0x29988a0, C4<1>, C4<1>;
+L_0x2999030 .delay (20000,20000,20000) L_0x2999030/d;
+L_0x29991a0/d .functor AND 1, L_0x2998e50, L_0x2998360, C4<1>, C4<1>;
+L_0x29991a0 .delay (20000,20000,20000) L_0x29991a0/d;
+L_0x2999290/d .functor OR 1, L_0x2999030, L_0x29991a0, C4<0>, C4<0>;
+L_0x2999290 .delay (20000,20000,20000) L_0x2999290/d;
+v0x2844d60_0 .net "A", 0 0, L_0x2998190; 1 drivers
+v0x2844e20_0 .net "AandB", 0 0, L_0x2999030; 1 drivers
+v0x2844ec0_0 .net "AddSubSLTSum", 0 0, L_0x2998f40; 1 drivers
+v0x2844f60_0 .net "AxorB", 0 0, L_0x2998e50; 1 drivers
+v0x2844fe0_0 .net "B", 0 0, L_0x2998230; 1 drivers
+v0x2845090_0 .net "BornB", 0 0, L_0x29988a0; 1 drivers
+v0x2845150_0 .net "CINandAxorB", 0 0, L_0x29991a0; 1 drivers
+v0x28451d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2845250_0 .net *"_s3", 0 0, L_0x2998bd0; 1 drivers
+v0x28452d0_0 .net *"_s5", 0 0, L_0x2998db0; 1 drivers
+v0x2845370_0 .net "carryin", 0 0, L_0x2998360; 1 drivers
+v0x2845410_0 .net "carryout", 0 0, L_0x2999290; 1 drivers
+v0x28454b0_0 .net "nB", 0 0, L_0x2aca250; 1 drivers
+v0x2845560_0 .net "nCmd2", 0 0, L_0x2998b10; 1 drivers
+v0x2845660_0 .net "subtract", 0 0, L_0x2998c70; 1 drivers
+L_0x2998a70 .part v0x2960210_0, 0, 1;
+L_0x2998bd0 .part v0x2960210_0, 2, 1;
+L_0x2998db0 .part v0x2960210_0, 0, 1;
+S_0x28447c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x28446d0;
+ .timescale -9 -12;
+L_0x29985c0/d .functor NOT 1, L_0x2998a70, C4<0>, C4<0>, C4<0>;
+L_0x29985c0 .delay (10000,10000,10000) L_0x29985c0/d;
+L_0x2998680/d .functor AND 1, L_0x2998230, L_0x29985c0, C4<1>, C4<1>;
+L_0x2998680 .delay (20000,20000,20000) L_0x2998680/d;
+L_0x2998790/d .functor AND 1, L_0x2aca250, L_0x2998a70, C4<1>, C4<1>;
+L_0x2998790 .delay (20000,20000,20000) L_0x2998790/d;
+L_0x29988a0/d .functor OR 1, L_0x2998680, L_0x2998790, C4<0>, C4<0>;
+L_0x29988a0 .delay (20000,20000,20000) L_0x29988a0/d;
+v0x28448b0_0 .net "S", 0 0, L_0x2998a70; 1 drivers
+v0x2844950_0 .alias "in0", 0 0, v0x2844fe0_0;
+v0x28449f0_0 .alias "in1", 0 0, v0x28454b0_0;
+v0x2844a90_0 .net "nS", 0 0, L_0x29985c0; 1 drivers
+v0x2844b40_0 .net "out0", 0 0, L_0x2998680; 1 drivers
+v0x2844be0_0 .net "out1", 0 0, L_0x2998790; 1 drivers
+v0x2844cc0_0 .alias "outfinal", 0 0, v0x2845090_0;
+S_0x28433c0 .scope generate, "addbits[29]" "addbits[29]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2842dd8 .param/l "i" 3 283, +C4<011101>;
+S_0x2843530 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x28433c0;
+ .timescale -9 -12;
+L_0x2998400/d .functor NOT 1, L_0x2999760, C4<0>, C4<0>, C4<0>;
+L_0x2998400 .delay (10000,10000,10000) L_0x2998400/d;
+L_0x2999ff0/d .functor NOT 1, L_0x299a0b0, C4<0>, C4<0>, C4<0>;
+L_0x2999ff0 .delay (10000,10000,10000) L_0x2999ff0/d;
+L_0x299a150/d .functor AND 1, L_0x299a290, L_0x2999ff0, C4<1>, C4<1>;
+L_0x299a150 .delay (20000,20000,20000) L_0x299a150/d;
+L_0x299a330/d .functor XOR 1, L_0x29996c0, L_0x2999d80, C4<0>, C4<0>;
+L_0x299a330 .delay (40000,40000,40000) L_0x299a330/d;
+L_0x299a420/d .functor XOR 1, L_0x299a330, L_0x2999890, C4<0>, C4<0>;
+L_0x299a420 .delay (40000,40000,40000) L_0x299a420/d;
+L_0x299a510/d .functor AND 1, L_0x29996c0, L_0x2999d80, C4<1>, C4<1>;
+L_0x299a510 .delay (20000,20000,20000) L_0x299a510/d;
+L_0x299a680/d .functor AND 1, L_0x299a330, L_0x2999890, C4<1>, C4<1>;
+L_0x299a680 .delay (20000,20000,20000) L_0x299a680/d;
+L_0x299a770/d .functor OR 1, L_0x299a510, L_0x299a680, C4<0>, C4<0>;
+L_0x299a770 .delay (20000,20000,20000) L_0x299a770/d;
+v0x2843bc0_0 .net "A", 0 0, L_0x29996c0; 1 drivers
+v0x2843c80_0 .net "AandB", 0 0, L_0x299a510; 1 drivers
+v0x2843d20_0 .net "AddSubSLTSum", 0 0, L_0x299a420; 1 drivers
+v0x2843dc0_0 .net "AxorB", 0 0, L_0x299a330; 1 drivers
+v0x2843e40_0 .net "B", 0 0, L_0x2999760; 1 drivers
+v0x2843ef0_0 .net "BornB", 0 0, L_0x2999d80; 1 drivers
+v0x2843fb0_0 .net "CINandAxorB", 0 0, L_0x299a680; 1 drivers
+v0x2844030_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28440b0_0 .net *"_s3", 0 0, L_0x299a0b0; 1 drivers
+v0x2844130_0 .net *"_s5", 0 0, L_0x299a290; 1 drivers
+v0x28441d0_0 .net "carryin", 0 0, L_0x2999890; 1 drivers
+v0x2844270_0 .net "carryout", 0 0, L_0x299a770; 1 drivers
+v0x2844310_0 .net "nB", 0 0, L_0x2998400; 1 drivers
+v0x28443c0_0 .net "nCmd2", 0 0, L_0x2999ff0; 1 drivers
+v0x28444c0_0 .net "subtract", 0 0, L_0x299a150; 1 drivers
+L_0x2999f50 .part v0x2960210_0, 0, 1;
+L_0x299a0b0 .part v0x2960210_0, 2, 1;
+L_0x299a290 .part v0x2960210_0, 0, 1;
+S_0x2843620 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2843530;
+ .timescale -9 -12;
+L_0x2998560/d .functor NOT 1, L_0x2999f50, C4<0>, C4<0>, C4<0>;
+L_0x2998560 .delay (10000,10000,10000) L_0x2998560/d;
+L_0x2999b60/d .functor AND 1, L_0x2999760, L_0x2998560, C4<1>, C4<1>;
+L_0x2999b60 .delay (20000,20000,20000) L_0x2999b60/d;
+L_0x2999c70/d .functor AND 1, L_0x2998400, L_0x2999f50, C4<1>, C4<1>;
+L_0x2999c70 .delay (20000,20000,20000) L_0x2999c70/d;
+L_0x2999d80/d .functor OR 1, L_0x2999b60, L_0x2999c70, C4<0>, C4<0>;
+L_0x2999d80 .delay (20000,20000,20000) L_0x2999d80/d;
+v0x2843710_0 .net "S", 0 0, L_0x2999f50; 1 drivers
+v0x28437b0_0 .alias "in0", 0 0, v0x2843e40_0;
+v0x2843850_0 .alias "in1", 0 0, v0x2844310_0;
+v0x28438f0_0 .net "nS", 0 0, L_0x2998560; 1 drivers
+v0x28439a0_0 .net "out0", 0 0, L_0x2999b60; 1 drivers
+v0x2843a40_0 .net "out1", 0 0, L_0x2999c70; 1 drivers
+v0x2843b20_0 .alias "outfinal", 0 0, v0x2843ef0_0;
+S_0x2842220 .scope generate, "addbits[30]" "addbits[30]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x2841b68 .param/l "i" 3 283, +C4<011110>;
+S_0x2842390 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2842220;
+ .timescale -9 -12;
+L_0x2999930/d .functor NOT 1, L_0x299ac40, C4<0>, C4<0>, C4<0>;
+L_0x2999930 .delay (10000,10000,10000) L_0x2999930/d;
+L_0x299b500/d .functor NOT 1, L_0x299b5c0, C4<0>, C4<0>, C4<0>;
+L_0x299b500 .delay (10000,10000,10000) L_0x299b500/d;
+L_0x299b660/d .functor AND 1, L_0x299b7a0, L_0x299b500, C4<1>, C4<1>;
+L_0x299b660 .delay (20000,20000,20000) L_0x299b660/d;
+L_0x299b840/d .functor XOR 1, L_0x299aba0, L_0x299b290, C4<0>, C4<0>;
+L_0x299b840 .delay (40000,40000,40000) L_0x299b840/d;
+L_0x2ad2c70/d .functor XOR 1, L_0x299b840, L_0x299ad70, C4<0>, C4<0>;
+L_0x2ad2c70 .delay (40000,40000,40000) L_0x2ad2c70/d;
+L_0x2ad2d60/d .functor AND 1, L_0x299aba0, L_0x299b290, C4<1>, C4<1>;
+L_0x2ad2d60 .delay (20000,20000,20000) L_0x2ad2d60/d;
+L_0x2ad2ed0/d .functor AND 1, L_0x299b840, L_0x299ad70, C4<1>, C4<1>;
+L_0x2ad2ed0 .delay (20000,20000,20000) L_0x2ad2ed0/d;
+L_0x2ad2fc0/d .functor OR 1, L_0x2ad2d60, L_0x2ad2ed0, C4<0>, C4<0>;
+L_0x2ad2fc0 .delay (20000,20000,20000) L_0x2ad2fc0/d;
+v0x2842a20_0 .net "A", 0 0, L_0x299aba0; 1 drivers
+v0x2842ae0_0 .net "AandB", 0 0, L_0x2ad2d60; 1 drivers
+v0x2842b80_0 .net "AddSubSLTSum", 0 0, L_0x2ad2c70; 1 drivers
+v0x2842c20_0 .net "AxorB", 0 0, L_0x299b840; 1 drivers
+v0x2842ca0_0 .net "B", 0 0, L_0x299ac40; 1 drivers
+v0x2842d50_0 .net "BornB", 0 0, L_0x299b290; 1 drivers
+v0x2842e10_0 .net "CINandAxorB", 0 0, L_0x2ad2ed0; 1 drivers
+v0x2842e90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2842f10_0 .net *"_s3", 0 0, L_0x299b5c0; 1 drivers
+v0x2842f90_0 .net *"_s5", 0 0, L_0x299b7a0; 1 drivers
+v0x2843030_0 .net "carryin", 0 0, L_0x299ad70; 1 drivers
+v0x28430d0_0 .net "carryout", 0 0, L_0x2ad2fc0; 1 drivers
+v0x2843170_0 .net "nB", 0 0, L_0x2999930; 1 drivers
+v0x2843220_0 .net "nCmd2", 0 0, L_0x299b500; 1 drivers
+v0x2843320_0 .net "subtract", 0 0, L_0x299b660; 1 drivers
+L_0x299b460 .part v0x2960210_0, 0, 1;
+L_0x299b5c0 .part v0x2960210_0, 2, 1;
+L_0x299b7a0 .part v0x2960210_0, 0, 1;
+S_0x2842480 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2842390;
+ .timescale -9 -12;
+L_0x2999a90/d .functor NOT 1, L_0x299b460, C4<0>, C4<0>, C4<0>;
+L_0x2999a90 .delay (10000,10000,10000) L_0x2999a90/d;
+L_0x299b070/d .functor AND 1, L_0x299ac40, L_0x2999a90, C4<1>, C4<1>;
+L_0x299b070 .delay (20000,20000,20000) L_0x299b070/d;
+L_0x299b180/d .functor AND 1, L_0x2999930, L_0x299b460, C4<1>, C4<1>;
+L_0x299b180 .delay (20000,20000,20000) L_0x299b180/d;
+L_0x299b290/d .functor OR 1, L_0x299b070, L_0x299b180, C4<0>, C4<0>;
+L_0x299b290 .delay (20000,20000,20000) L_0x299b290/d;
+v0x2842570_0 .net "S", 0 0, L_0x299b460; 1 drivers
+v0x2842610_0 .alias "in0", 0 0, v0x2842ca0_0;
+v0x28426b0_0 .alias "in1", 0 0, v0x2843170_0;
+v0x2842750_0 .net "nS", 0 0, L_0x2999a90; 1 drivers
+v0x2842800_0 .net "out0", 0 0, L_0x299b070; 1 drivers
+v0x28428a0_0 .net "out1", 0 0, L_0x299b180; 1 drivers
+v0x2842980_0 .alias "outfinal", 0 0, v0x2842d50_0;
+S_0x2840fc0 .scope generate, "addbits[31]" "addbits[31]" 3 283, 3 283, S_0x2840e20;
+ .timescale -9 -12;
+P_0x28410b8 .param/l "i" 3 283, +C4<011111>;
+S_0x2841150 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2840fc0;
+ .timescale -9 -12;
+L_0x299ae10/d .functor NOT 1, L_0x2ad3380, C4<0>, C4<0>, C4<0>;
+L_0x299ae10 .delay (10000,10000,10000) L_0x299ae10/d;
+L_0x2ad3ca0/d .functor NOT 1, L_0x2ad3d40, C4<0>, C4<0>, C4<0>;
+L_0x2ad3ca0 .delay (10000,10000,10000) L_0x2ad3ca0/d;
+L_0x2ad3de0/d .functor AND 1, L_0x2ad3f20, L_0x2ad3ca0, C4<1>, C4<1>;
+L_0x2ad3de0 .delay (20000,20000,20000) L_0x2ad3de0/d;
+L_0x2ad3fc0/d .functor XOR 1, L_0x2ad32e0, L_0x2ad3a70, C4<0>, C4<0>;
+L_0x2ad3fc0 .delay (40000,40000,40000) L_0x2ad3fc0/d;
+L_0x2ad40b0/d .functor XOR 1, L_0x2ad3fc0, L_0x2ad34b0, C4<0>, C4<0>;
+L_0x2ad40b0 .delay (40000,40000,40000) L_0x2ad40b0/d;
+L_0x2ad41a0/d .functor AND 1, L_0x2ad32e0, L_0x2ad3a70, C4<1>, C4<1>;
+L_0x2ad41a0 .delay (20000,20000,20000) L_0x2ad41a0/d;
+L_0x2ad4310/d .functor AND 1, L_0x2ad3fc0, L_0x2ad34b0, C4<1>, C4<1>;
+L_0x2ad4310 .delay (20000,20000,20000) L_0x2ad4310/d;
+L_0x2ad4400/d .functor OR 1, L_0x2ad41a0, L_0x2ad4310, C4<0>, C4<0>;
+L_0x2ad4400 .delay (20000,20000,20000) L_0x2ad4400/d;
+v0x28417b0_0 .net "A", 0 0, L_0x2ad32e0; 1 drivers
+v0x2841870_0 .net "AandB", 0 0, L_0x2ad41a0; 1 drivers
+v0x2841910_0 .net "AddSubSLTSum", 0 0, L_0x2ad40b0; 1 drivers
+v0x28419b0_0 .net "AxorB", 0 0, L_0x2ad3fc0; 1 drivers
+v0x2841a30_0 .net "B", 0 0, L_0x2ad3380; 1 drivers
+v0x2841ae0_0 .net "BornB", 0 0, L_0x2ad3a70; 1 drivers
+v0x2841ba0_0 .net "CINandAxorB", 0 0, L_0x2ad4310; 1 drivers
+v0x2841c20_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2841ca0_0 .net *"_s3", 0 0, L_0x2ad3d40; 1 drivers
+v0x2841d20_0 .net *"_s5", 0 0, L_0x2ad3f20; 1 drivers
+v0x2841e20_0 .net "carryin", 0 0, L_0x2ad34b0; 1 drivers
+v0x2841ec0_0 .net "carryout", 0 0, L_0x2ad4400; 1 drivers
+v0x2841fd0_0 .net "nB", 0 0, L_0x299ae10; 1 drivers
+v0x2842080_0 .net "nCmd2", 0 0, L_0x2ad3ca0; 1 drivers
+v0x2842180_0 .net "subtract", 0 0, L_0x2ad3de0; 1 drivers
+L_0x2ad3c00 .part v0x2960210_0, 0, 1;
+L_0x2ad3d40 .part v0x2960210_0, 2, 1;
+L_0x2ad3f20 .part v0x2960210_0, 0, 1;
+S_0x2841240 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2841150;
+ .timescale -9 -12;
+L_0x299af70/d .functor NOT 1, L_0x2ad3c00, C4<0>, C4<0>, C4<0>;
+L_0x299af70 .delay (10000,10000,10000) L_0x299af70/d;
+L_0x2ad3890/d .functor AND 1, L_0x2ad3380, L_0x299af70, C4<1>, C4<1>;
+L_0x2ad3890 .delay (20000,20000,20000) L_0x2ad3890/d;
+L_0x2ad3980/d .functor AND 1, L_0x299ae10, L_0x2ad3c00, C4<1>, C4<1>;
+L_0x2ad3980 .delay (20000,20000,20000) L_0x2ad3980/d;
+L_0x2ad3a70/d .functor OR 1, L_0x2ad3890, L_0x2ad3980, C4<0>, C4<0>;
+L_0x2ad3a70 .delay (20000,20000,20000) L_0x2ad3a70/d;
+v0x2841330_0 .net "S", 0 0, L_0x2ad3c00; 1 drivers
+v0x28413d0_0 .alias "in0", 0 0, v0x2841a30_0;
+v0x2841470_0 .alias "in1", 0 0, v0x2841fd0_0;
+v0x2841510_0 .net "nS", 0 0, L_0x299af70; 1 drivers
+v0x2841590_0 .net "out0", 0 0, L_0x2ad3890; 1 drivers
+v0x2841630_0 .net "out1", 0 0, L_0x2ad3980; 1 drivers
+v0x2841710_0 .alias "outfinal", 0 0, v0x2841ae0_0;
+S_0x28293f0 .scope module, "trial1" "AndNand32" 3 387, 3 216, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2828eb8 .param/l "size" 3 223, +C4<0100000>;
+v0x2840c20_0 .alias "A", 31 0, v0x295f580_0;
+v0x2840ca0_0 .alias "AndNandOut", 31 0, v0x2960110_0;
+v0x2840d20_0 .alias "B", 31 0, v0x295f6a0_0;
+v0x2840da0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ad6970 .part/pv L_0x2ad6700, 1, 1, 32;
+L_0x2ad78a0 .part v0x295fe90_0, 1, 1;
+L_0x2ad7940 .part v0x2960190_0, 1, 1;
+L_0x2ad8130 .part/pv L_0x2ad7ee0, 2, 1, 32;
+L_0x2ad81d0 .part v0x295fe90_0, 2, 1;
+L_0x2ad8270 .part v0x2960190_0, 2, 1;
+L_0x2ad8ba0 .part/pv L_0x2ad8930, 3, 1, 32;
+L_0x2ad8c40 .part v0x295fe90_0, 3, 1;
+L_0x2ad8d30 .part v0x2960190_0, 3, 1;
+L_0x2ad9600 .part/pv L_0x2ad9390, 4, 1, 32;
+L_0x2ad9700 .part v0x295fe90_0, 4, 1;
+L_0x2ad97a0 .part v0x2960190_0, 4, 1;
+L_0x2ada070 .part/pv L_0x2ad9e00, 5, 1, 32;
+L_0x2ada110 .part v0x295fe90_0, 5, 1;
+L_0x2ada230 .part v0x2960190_0, 5, 1;
+L_0x2adab40 .part/pv L_0x2ada8d0, 6, 1, 32;
+L_0x2adac70 .part v0x295fe90_0, 6, 1;
+L_0x2adad10 .part v0x2960190_0, 6, 1;
+L_0x2adb640 .part/pv L_0x2adb3d0, 7, 1, 32;
+L_0x2adb6e0 .part v0x295fe90_0, 7, 1;
+L_0x2adae00 .part v0x2960190_0, 7, 1;
+L_0x2adc0a0 .part/pv L_0x2adbe30, 8, 1, 32;
+L_0x2adb780 .part v0x295fe90_0, 8, 1;
+L_0x2adc200 .part v0x2960190_0, 8, 1;
+L_0x2adcb20 .part/pv L_0x2adc8b0, 9, 1, 32;
+L_0x2adcbc0 .part v0x295fe90_0, 9, 1;
+L_0x2adc2f0 .part v0x2960190_0, 9, 1;
+L_0x2add3f0 .part/pv L_0x2add1c0, 10, 1, 32;
+L_0x2adcc60 .part v0x295fe90_0, 10, 1;
+L_0x2add580 .part v0x2960190_0, 10, 1;
+L_0x2addda0 .part/pv L_0x2addb70, 11, 1, 32;
+L_0x2adde40 .part v0x295fe90_0, 11, 1;
+L_0x2add670 .part v0x2960190_0, 11, 1;
+L_0x2ade750 .part/pv L_0x2ade4e0, 12, 1, 32;
+L_0x2addee0 .part v0x295fe90_0, 12, 1;
+L_0x2ade910 .part v0x2960190_0, 12, 1;
+L_0x2adf1d0 .part/pv L_0x2adef60, 13, 1, 32;
+L_0x2adf270 .part v0x295fe90_0, 13, 1;
+L_0x2ade9b0 .part v0x2960190_0, 13, 1;
+L_0x2adfc30 .part/pv L_0x2adf9c0, 14, 1, 32;
+L_0x2adf310 .part v0x295fe90_0, 14, 1;
+L_0x2adf3b0 .part v0x2960190_0, 14, 1;
+L_0x2ae06a0 .part/pv L_0x2ae0430, 15, 1, 32;
+L_0x2ae0740 .part v0x295fe90_0, 15, 1;
+L_0x2adfe70 .part v0x2960190_0, 15, 1;
+L_0x2ae1110 .part/pv L_0x2ae0ea0, 16, 1, 32;
+L_0x2ae07e0 .part v0x295fe90_0, 16, 1;
+L_0x2ae0880 .part v0x2960190_0, 16, 1;
+L_0x2ae1b90 .part/pv L_0x2ae1920, 17, 1, 32;
+L_0x2ae1c30 .part v0x295fe90_0, 17, 1;
+L_0x2ae1380 .part v0x2960190_0, 17, 1;
+L_0x2ae25f0 .part/pv L_0x2ae2380, 18, 1, 32;
+L_0x2ae1cd0 .part v0x295fe90_0, 18, 1;
+L_0x2ae1d70 .part v0x2960190_0, 18, 1;
+L_0x2ae3070 .part/pv L_0x2ae2e00, 19, 1, 32;
+L_0x2ae3110 .part v0x295fe90_0, 19, 1;
+L_0x2ae2690 .part v0x2960190_0, 19, 1;
+L_0x2ae3ad0 .part/pv L_0x2ae3860, 20, 1, 32;
+L_0x2ae31b0 .part v0x295fe90_0, 20, 1;
+L_0x2ae3250 .part v0x2960190_0, 20, 1;
+L_0x2ae4540 .part/pv L_0x2ae42d0, 21, 1, 32;
+L_0x2ae45e0 .part v0x295fe90_0, 21, 1;
+L_0x2ae3b70 .part v0x2960190_0, 21, 1;
+L_0x2ae4fb0 .part/pv L_0x2ae4d40, 22, 1, 32;
+L_0x2ae4680 .part v0x295fe90_0, 22, 1;
+L_0x2ae4720 .part v0x2960190_0, 22, 1;
+L_0x2ae5a30 .part/pv L_0x2ae57c0, 23, 1, 32;
+L_0x2ae5ad0 .part v0x295fe90_0, 23, 1;
+L_0x2ae5050 .part v0x2960190_0, 23, 1;
+L_0x2ae6490 .part/pv L_0x2ae6220, 24, 1, 32;
+L_0x2ae5b70 .part v0x295fe90_0, 24, 1;
+L_0x2ae5c10 .part v0x2960190_0, 24, 1;
+L_0x2ae6f00 .part/pv L_0x2ae6c90, 25, 1, 32;
+L_0x2ae6fa0 .part v0x295fe90_0, 25, 1;
+L_0x2ae6530 .part v0x2960190_0, 25, 1;
+L_0x2ae7960 .part/pv L_0x2ae76f0, 26, 1, 32;
+L_0x2ae7040 .part v0x295fe90_0, 26, 1;
+L_0x2ae70e0 .part v0x2960190_0, 26, 1;
+L_0x2ae83d0 .part/pv L_0x2ae8160, 27, 1, 32;
+L_0x2ae8470 .part v0x295fe90_0, 27, 1;
+L_0x2ae7a00 .part v0x2960190_0, 27, 1;
+L_0x2ae8e40 .part/pv L_0x2ae8bd0, 28, 1, 32;
+L_0x2ae8510 .part v0x295fe90_0, 28, 1;
+L_0x2ae85b0 .part v0x2960190_0, 28, 1;
+L_0x2ae98c0 .part/pv L_0x2ae9650, 29, 1, 32;
+L_0x2ae9960 .part v0x295fe90_0, 29, 1;
+L_0x2ae8ee0 .part v0x2960190_0, 29, 1;
+L_0x2aea320 .part/pv L_0x2aea0b0, 30, 1, 32;
+L_0x2ae9a00 .part v0x295fe90_0, 30, 1;
+L_0x2ae9aa0 .part v0x2960190_0, 30, 1;
+L_0x2aead90 .part/pv L_0x2aeab20, 31, 1, 32;
+L_0x2a37f60 .part v0x295fe90_0, 31, 1;
+L_0x2aea3c0 .part v0x2960190_0, 31, 1;
+L_0x2aec010 .part/pv L_0x2a386c0, 0, 1, 32;
+L_0x2a38000 .part v0x295fe90_0, 0, 1;
+L_0x2a380a0 .part v0x2960190_0, 0, 1;
+S_0x28401f0 .scope module, "attempt2" "AndNand" 3 227, 3 149, S_0x28293f0;
+ .timescale -9 -12;
+L_0x2aea4b0/d .functor NAND 1, L_0x2a38000, L_0x2a380a0, C4<1>, C4<1>;
+L_0x2aea4b0 .delay (10000,10000,10000) L_0x2aea4b0/d;
+L_0x2aea610/d .functor NOT 1, L_0x2aea4b0, C4<0>, C4<0>, C4<0>;
+L_0x2aea610 .delay (10000,10000,10000) L_0x2aea610/d;
+v0x2840810_0 .net "A", 0 0, L_0x2a38000; 1 drivers
+v0x28408d0_0 .net "AandB", 0 0, L_0x2aea610; 1 drivers
+v0x2840950_0 .net "AnandB", 0 0, L_0x2aea4b0; 1 drivers
+v0x2840a00_0 .net "AndNandOut", 0 0, L_0x2a386c0; 1 drivers
+v0x2840ae0_0 .net "B", 0 0, L_0x2a380a0; 1 drivers
+v0x2840b60_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2aebf70 .part v0x2960210_0, 0, 1;
+S_0x28402e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28401f0;
+ .timescale -9 -12;
+L_0x2a383a0/d .functor NOT 1, L_0x2aebf70, C4<0>, C4<0>, C4<0>;
+L_0x2a383a0 .delay (10000,10000,10000) L_0x2a383a0/d;
+L_0x2a38460/d .functor AND 1, L_0x2aea610, L_0x2a383a0, C4<1>, C4<1>;
+L_0x2a38460 .delay (20000,20000,20000) L_0x2a38460/d;
+L_0x2a38570/d .functor AND 1, L_0x2aea4b0, L_0x2aebf70, C4<1>, C4<1>;
+L_0x2a38570 .delay (20000,20000,20000) L_0x2a38570/d;
+L_0x2a386c0/d .functor OR 1, L_0x2a38460, L_0x2a38570, C4<0>, C4<0>;
+L_0x2a386c0 .delay (20000,20000,20000) L_0x2a386c0/d;
+v0x28403d0_0 .net "S", 0 0, L_0x2aebf70; 1 drivers
+v0x2840450_0 .alias "in0", 0 0, v0x28408d0_0;
+v0x28404d0_0 .alias "in1", 0 0, v0x2840950_0;
+v0x2840570_0 .net "nS", 0 0, L_0x2a383a0; 1 drivers
+v0x28405f0_0 .net "out0", 0 0, L_0x2a38460; 1 drivers
+v0x2840690_0 .net "out1", 0 0, L_0x2a38570; 1 drivers
+v0x2840770_0 .alias "outfinal", 0 0, v0x2840a00_0;
+S_0x283f630 .scope generate, "andbits[1]" "andbits[1]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283f728 .param/l "i" 3 231, +C4<01>;
+S_0x283f7a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283f630;
+ .timescale -9 -12;
+L_0x2ad5b00/d .functor NAND 1, L_0x2ad78a0, L_0x2ad7940, C4<1>, C4<1>;
+L_0x2ad5b00 .delay (10000,10000,10000) L_0x2ad5b00/d;
+L_0x2a82180/d .functor NOT 1, L_0x2ad5b00, C4<0>, C4<0>, C4<0>;
+L_0x2a82180 .delay (10000,10000,10000) L_0x2a82180/d;
+v0x283fde0_0 .net "A", 0 0, L_0x2ad78a0; 1 drivers
+v0x283fea0_0 .net "AandB", 0 0, L_0x2a82180; 1 drivers
+v0x283ff20_0 .net "AnandB", 0 0, L_0x2ad5b00; 1 drivers
+v0x283ffd0_0 .net "AndNandOut", 0 0, L_0x2ad6700; 1 drivers
+v0x28400b0_0 .net "B", 0 0, L_0x2ad7940; 1 drivers
+v0x2840130_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ad68d0 .part v0x2960210_0, 0, 1;
+S_0x283f890 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283f7a0;
+ .timescale -9 -12;
+L_0x2a822b0/d .functor NOT 1, L_0x2ad68d0, C4<0>, C4<0>, C4<0>;
+L_0x2a822b0 .delay (10000,10000,10000) L_0x2a822b0/d;
+L_0x2ad64a0/d .functor AND 1, L_0x2a82180, L_0x2a822b0, C4<1>, C4<1>;
+L_0x2ad64a0 .delay (20000,20000,20000) L_0x2ad64a0/d;
+L_0x2ad65b0/d .functor AND 1, L_0x2ad5b00, L_0x2ad68d0, C4<1>, C4<1>;
+L_0x2ad65b0 .delay (20000,20000,20000) L_0x2ad65b0/d;
+L_0x2ad6700/d .functor OR 1, L_0x2ad64a0, L_0x2ad65b0, C4<0>, C4<0>;
+L_0x2ad6700 .delay (20000,20000,20000) L_0x2ad6700/d;
+v0x283f980_0 .net "S", 0 0, L_0x2ad68d0; 1 drivers
+v0x283fa00_0 .alias "in0", 0 0, v0x283fea0_0;
+v0x283faa0_0 .alias "in1", 0 0, v0x283ff20_0;
+v0x283fb40_0 .net "nS", 0 0, L_0x2a822b0; 1 drivers
+v0x283fbc0_0 .net "out0", 0 0, L_0x2ad64a0; 1 drivers
+v0x283fc60_0 .net "out1", 0 0, L_0x2ad65b0; 1 drivers
+v0x283fd40_0 .alias "outfinal", 0 0, v0x283ffd0_0;
+S_0x283ea70 .scope generate, "andbits[2]" "andbits[2]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283eb68 .param/l "i" 3 231, +C4<010>;
+S_0x283ebe0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283ea70;
+ .timescale -9 -12;
+L_0x2ad7a30/d .functor NAND 1, L_0x2ad81d0, L_0x2ad8270, C4<1>, C4<1>;
+L_0x2ad7a30 .delay (10000,10000,10000) L_0x2ad7a30/d;
+L_0x2ad7b30/d .functor NOT 1, L_0x2ad7a30, C4<0>, C4<0>, C4<0>;
+L_0x2ad7b30 .delay (10000,10000,10000) L_0x2ad7b30/d;
+v0x283f220_0 .net "A", 0 0, L_0x2ad81d0; 1 drivers
+v0x283f2e0_0 .net "AandB", 0 0, L_0x2ad7b30; 1 drivers
+v0x283f360_0 .net "AnandB", 0 0, L_0x2ad7a30; 1 drivers
+v0x283f410_0 .net "AndNandOut", 0 0, L_0x2ad7ee0; 1 drivers
+v0x283f4f0_0 .net "B", 0 0, L_0x2ad8270; 1 drivers
+v0x283f570_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ad8090 .part v0x2960210_0, 0, 1;
+S_0x283ecd0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283ebe0;
+ .timescale -9 -12;
+L_0x2ad7c20/d .functor NOT 1, L_0x2ad8090, C4<0>, C4<0>, C4<0>;
+L_0x2ad7c20 .delay (10000,10000,10000) L_0x2ad7c20/d;
+L_0x2ad7cc0/d .functor AND 1, L_0x2ad7b30, L_0x2ad7c20, C4<1>, C4<1>;
+L_0x2ad7cc0 .delay (20000,20000,20000) L_0x2ad7cc0/d;
+L_0x2ad7db0/d .functor AND 1, L_0x2ad7a30, L_0x2ad8090, C4<1>, C4<1>;
+L_0x2ad7db0 .delay (20000,20000,20000) L_0x2ad7db0/d;
+L_0x2ad7ee0/d .functor OR 1, L_0x2ad7cc0, L_0x2ad7db0, C4<0>, C4<0>;
+L_0x2ad7ee0 .delay (20000,20000,20000) L_0x2ad7ee0/d;
+v0x283edc0_0 .net "S", 0 0, L_0x2ad8090; 1 drivers
+v0x283ee40_0 .alias "in0", 0 0, v0x283f2e0_0;
+v0x283eee0_0 .alias "in1", 0 0, v0x283f360_0;
+v0x283ef80_0 .net "nS", 0 0, L_0x2ad7c20; 1 drivers
+v0x283f000_0 .net "out0", 0 0, L_0x2ad7cc0; 1 drivers
+v0x283f0a0_0 .net "out1", 0 0, L_0x2ad7db0; 1 drivers
+v0x283f180_0 .alias "outfinal", 0 0, v0x283f410_0;
+S_0x283deb0 .scope generate, "andbits[3]" "andbits[3]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283dfa8 .param/l "i" 3 231, +C4<011>;
+S_0x283e020 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283deb0;
+ .timescale -9 -12;
+L_0x2ad83a0/d .functor NAND 1, L_0x2ad8c40, L_0x2ad8d30, C4<1>, C4<1>;
+L_0x2ad83a0 .delay (10000,10000,10000) L_0x2ad83a0/d;
+L_0x2ad84e0/d .functor NOT 1, L_0x2ad83a0, C4<0>, C4<0>, C4<0>;
+L_0x2ad84e0 .delay (10000,10000,10000) L_0x2ad84e0/d;
+v0x283e660_0 .net "A", 0 0, L_0x2ad8c40; 1 drivers
+v0x283e720_0 .net "AandB", 0 0, L_0x2ad84e0; 1 drivers
+v0x283e7a0_0 .net "AnandB", 0 0, L_0x2ad83a0; 1 drivers
+v0x283e850_0 .net "AndNandOut", 0 0, L_0x2ad8930; 1 drivers
+v0x283e930_0 .net "B", 0 0, L_0x2ad8d30; 1 drivers
+v0x283e9b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ad8b00 .part v0x2960210_0, 0, 1;
+S_0x283e110 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283e020;
+ .timescale -9 -12;
+L_0x2ad8610/d .functor NOT 1, L_0x2ad8b00, C4<0>, C4<0>, C4<0>;
+L_0x2ad8610 .delay (10000,10000,10000) L_0x2ad8610/d;
+L_0x2ad86d0/d .functor AND 1, L_0x2ad84e0, L_0x2ad8610, C4<1>, C4<1>;
+L_0x2ad86d0 .delay (20000,20000,20000) L_0x2ad86d0/d;
+L_0x2ad87e0/d .functor AND 1, L_0x2ad83a0, L_0x2ad8b00, C4<1>, C4<1>;
+L_0x2ad87e0 .delay (20000,20000,20000) L_0x2ad87e0/d;
+L_0x2ad8930/d .functor OR 1, L_0x2ad86d0, L_0x2ad87e0, C4<0>, C4<0>;
+L_0x2ad8930 .delay (20000,20000,20000) L_0x2ad8930/d;
+v0x283e200_0 .net "S", 0 0, L_0x2ad8b00; 1 drivers
+v0x283e280_0 .alias "in0", 0 0, v0x283e720_0;
+v0x283e320_0 .alias "in1", 0 0, v0x283e7a0_0;
+v0x283e3c0_0 .net "nS", 0 0, L_0x2ad8610; 1 drivers
+v0x283e440_0 .net "out0", 0 0, L_0x2ad86d0; 1 drivers
+v0x283e4e0_0 .net "out1", 0 0, L_0x2ad87e0; 1 drivers
+v0x283e5c0_0 .alias "outfinal", 0 0, v0x283e850_0;
+S_0x283d2f0 .scope generate, "andbits[4]" "andbits[4]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283d3e8 .param/l "i" 3 231, +C4<0100>;
+S_0x283d460 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283d2f0;
+ .timescale -9 -12;
+L_0x2ad8e20/d .functor NAND 1, L_0x2ad9700, L_0x2ad97a0, C4<1>, C4<1>;
+L_0x2ad8e20 .delay (10000,10000,10000) L_0x2ad8e20/d;
+L_0x2ad8f40/d .functor NOT 1, L_0x2ad8e20, C4<0>, C4<0>, C4<0>;
+L_0x2ad8f40 .delay (10000,10000,10000) L_0x2ad8f40/d;
+v0x283daa0_0 .net "A", 0 0, L_0x2ad9700; 1 drivers
+v0x283db60_0 .net "AandB", 0 0, L_0x2ad8f40; 1 drivers
+v0x283dbe0_0 .net "AnandB", 0 0, L_0x2ad8e20; 1 drivers
+v0x283dc90_0 .net "AndNandOut", 0 0, L_0x2ad9390; 1 drivers
+v0x283dd70_0 .net "B", 0 0, L_0x2ad97a0; 1 drivers
+v0x283ddf0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ad9560 .part v0x2960210_0, 0, 1;
+S_0x283d550 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283d460;
+ .timescale -9 -12;
+L_0x2ad9070/d .functor NOT 1, L_0x2ad9560, C4<0>, C4<0>, C4<0>;
+L_0x2ad9070 .delay (10000,10000,10000) L_0x2ad9070/d;
+L_0x2ad9130/d .functor AND 1, L_0x2ad8f40, L_0x2ad9070, C4<1>, C4<1>;
+L_0x2ad9130 .delay (20000,20000,20000) L_0x2ad9130/d;
+L_0x2ad9240/d .functor AND 1, L_0x2ad8e20, L_0x2ad9560, C4<1>, C4<1>;
+L_0x2ad9240 .delay (20000,20000,20000) L_0x2ad9240/d;
+L_0x2ad9390/d .functor OR 1, L_0x2ad9130, L_0x2ad9240, C4<0>, C4<0>;
+L_0x2ad9390 .delay (20000,20000,20000) L_0x2ad9390/d;
+v0x283d640_0 .net "S", 0 0, L_0x2ad9560; 1 drivers
+v0x283d6c0_0 .alias "in0", 0 0, v0x283db60_0;
+v0x283d760_0 .alias "in1", 0 0, v0x283dbe0_0;
+v0x283d800_0 .net "nS", 0 0, L_0x2ad9070; 1 drivers
+v0x283d880_0 .net "out0", 0 0, L_0x2ad9130; 1 drivers
+v0x283d920_0 .net "out1", 0 0, L_0x2ad9240; 1 drivers
+v0x283da00_0 .alias "outfinal", 0 0, v0x283dc90_0;
+S_0x283c730 .scope generate, "andbits[5]" "andbits[5]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283c828 .param/l "i" 3 231, +C4<0101>;
+S_0x283c8a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283c730;
+ .timescale -9 -12;
+L_0x2ad96a0/d .functor NAND 1, L_0x2ada110, L_0x2ada230, C4<1>, C4<1>;
+L_0x2ad96a0 .delay (10000,10000,10000) L_0x2ad96a0/d;
+L_0x2ad99b0/d .functor NOT 1, L_0x2ad96a0, C4<0>, C4<0>, C4<0>;
+L_0x2ad99b0 .delay (10000,10000,10000) L_0x2ad99b0/d;
+v0x283cee0_0 .net "A", 0 0, L_0x2ada110; 1 drivers
+v0x283cfa0_0 .net "AandB", 0 0, L_0x2ad99b0; 1 drivers
+v0x283d020_0 .net "AnandB", 0 0, L_0x2ad96a0; 1 drivers
+v0x283d0d0_0 .net "AndNandOut", 0 0, L_0x2ad9e00; 1 drivers
+v0x283d1b0_0 .net "B", 0 0, L_0x2ada230; 1 drivers
+v0x283d230_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ad9fd0 .part v0x2960210_0, 0, 1;
+S_0x283c990 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283c8a0;
+ .timescale -9 -12;
+L_0x2ad9ae0/d .functor NOT 1, L_0x2ad9fd0, C4<0>, C4<0>, C4<0>;
+L_0x2ad9ae0 .delay (10000,10000,10000) L_0x2ad9ae0/d;
+L_0x2ad9ba0/d .functor AND 1, L_0x2ad99b0, L_0x2ad9ae0, C4<1>, C4<1>;
+L_0x2ad9ba0 .delay (20000,20000,20000) L_0x2ad9ba0/d;
+L_0x2ad9cb0/d .functor AND 1, L_0x2ad96a0, L_0x2ad9fd0, C4<1>, C4<1>;
+L_0x2ad9cb0 .delay (20000,20000,20000) L_0x2ad9cb0/d;
+L_0x2ad9e00/d .functor OR 1, L_0x2ad9ba0, L_0x2ad9cb0, C4<0>, C4<0>;
+L_0x2ad9e00 .delay (20000,20000,20000) L_0x2ad9e00/d;
+v0x283ca80_0 .net "S", 0 0, L_0x2ad9fd0; 1 drivers
+v0x283cb00_0 .alias "in0", 0 0, v0x283cfa0_0;
+v0x283cba0_0 .alias "in1", 0 0, v0x283d020_0;
+v0x283cc40_0 .net "nS", 0 0, L_0x2ad9ae0; 1 drivers
+v0x283ccc0_0 .net "out0", 0 0, L_0x2ad9ba0; 1 drivers
+v0x283cd60_0 .net "out1", 0 0, L_0x2ad9cb0; 1 drivers
+v0x283ce40_0 .alias "outfinal", 0 0, v0x283d0d0_0;
+S_0x283bb70 .scope generate, "andbits[6]" "andbits[6]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283bc68 .param/l "i" 3 231, +C4<0110>;
+S_0x283bce0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283bb70;
+ .timescale -9 -12;
+L_0x2ada320/d .functor NAND 1, L_0x2adac70, L_0x2adad10, C4<1>, C4<1>;
+L_0x2ada320 .delay (10000,10000,10000) L_0x2ada320/d;
+L_0x2ada480/d .functor NOT 1, L_0x2ada320, C4<0>, C4<0>, C4<0>;
+L_0x2ada480 .delay (10000,10000,10000) L_0x2ada480/d;
+v0x283c320_0 .net "A", 0 0, L_0x2adac70; 1 drivers
+v0x283c3e0_0 .net "AandB", 0 0, L_0x2ada480; 1 drivers
+v0x283c460_0 .net "AnandB", 0 0, L_0x2ada320; 1 drivers
+v0x283c510_0 .net "AndNandOut", 0 0, L_0x2ada8d0; 1 drivers
+v0x283c5f0_0 .net "B", 0 0, L_0x2adad10; 1 drivers
+v0x283c670_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2adaaa0 .part v0x2960210_0, 0, 1;
+S_0x283bdd0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283bce0;
+ .timescale -9 -12;
+L_0x2ada5b0/d .functor NOT 1, L_0x2adaaa0, C4<0>, C4<0>, C4<0>;
+L_0x2ada5b0 .delay (10000,10000,10000) L_0x2ada5b0/d;
+L_0x2ada670/d .functor AND 1, L_0x2ada480, L_0x2ada5b0, C4<1>, C4<1>;
+L_0x2ada670 .delay (20000,20000,20000) L_0x2ada670/d;
+L_0x2ada780/d .functor AND 1, L_0x2ada320, L_0x2adaaa0, C4<1>, C4<1>;
+L_0x2ada780 .delay (20000,20000,20000) L_0x2ada780/d;
+L_0x2ada8d0/d .functor OR 1, L_0x2ada670, L_0x2ada780, C4<0>, C4<0>;
+L_0x2ada8d0 .delay (20000,20000,20000) L_0x2ada8d0/d;
+v0x283bec0_0 .net "S", 0 0, L_0x2adaaa0; 1 drivers
+v0x283bf40_0 .alias "in0", 0 0, v0x283c3e0_0;
+v0x283bfe0_0 .alias "in1", 0 0, v0x283c460_0;
+v0x283c080_0 .net "nS", 0 0, L_0x2ada5b0; 1 drivers
+v0x283c100_0 .net "out0", 0 0, L_0x2ada670; 1 drivers
+v0x283c1a0_0 .net "out1", 0 0, L_0x2ada780; 1 drivers
+v0x283c280_0 .alias "outfinal", 0 0, v0x283c510_0;
+S_0x283afb0 .scope generate, "andbits[7]" "andbits[7]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283b0a8 .param/l "i" 3 231, +C4<0111>;
+S_0x283b120 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283afb0;
+ .timescale -9 -12;
+L_0x2adabe0/d .functor NAND 1, L_0x2adb6e0, L_0x2adae00, C4<1>, C4<1>;
+L_0x2adabe0 .delay (10000,10000,10000) L_0x2adabe0/d;
+L_0x2adaf80/d .functor NOT 1, L_0x2adabe0, C4<0>, C4<0>, C4<0>;
+L_0x2adaf80 .delay (10000,10000,10000) L_0x2adaf80/d;
+v0x283b760_0 .net "A", 0 0, L_0x2adb6e0; 1 drivers
+v0x283b820_0 .net "AandB", 0 0, L_0x2adaf80; 1 drivers
+v0x283b8a0_0 .net "AnandB", 0 0, L_0x2adabe0; 1 drivers
+v0x283b950_0 .net "AndNandOut", 0 0, L_0x2adb3d0; 1 drivers
+v0x283ba30_0 .net "B", 0 0, L_0x2adae00; 1 drivers
+v0x283bab0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2adb5a0 .part v0x2960210_0, 0, 1;
+S_0x283b210 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283b120;
+ .timescale -9 -12;
+L_0x2adb0b0/d .functor NOT 1, L_0x2adb5a0, C4<0>, C4<0>, C4<0>;
+L_0x2adb0b0 .delay (10000,10000,10000) L_0x2adb0b0/d;
+L_0x2adb170/d .functor AND 1, L_0x2adaf80, L_0x2adb0b0, C4<1>, C4<1>;
+L_0x2adb170 .delay (20000,20000,20000) L_0x2adb170/d;
+L_0x2adb280/d .functor AND 1, L_0x2adabe0, L_0x2adb5a0, C4<1>, C4<1>;
+L_0x2adb280 .delay (20000,20000,20000) L_0x2adb280/d;
+L_0x2adb3d0/d .functor OR 1, L_0x2adb170, L_0x2adb280, C4<0>, C4<0>;
+L_0x2adb3d0 .delay (20000,20000,20000) L_0x2adb3d0/d;
+v0x283b300_0 .net "S", 0 0, L_0x2adb5a0; 1 drivers
+v0x283b380_0 .alias "in0", 0 0, v0x283b820_0;
+v0x283b420_0 .alias "in1", 0 0, v0x283b8a0_0;
+v0x283b4c0_0 .net "nS", 0 0, L_0x2adb0b0; 1 drivers
+v0x283b540_0 .net "out0", 0 0, L_0x2adb170; 1 drivers
+v0x283b5e0_0 .net "out1", 0 0, L_0x2adb280; 1 drivers
+v0x283b6c0_0 .alias "outfinal", 0 0, v0x283b950_0;
+S_0x283a3f0 .scope generate, "andbits[8]" "andbits[8]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x283a4e8 .param/l "i" 3 231, +C4<01000>;
+S_0x283a560 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x283a3f0;
+ .timescale -9 -12;
+L_0x2adb880/d .functor NAND 1, L_0x2adb780, L_0x2adc200, C4<1>, C4<1>;
+L_0x2adb880 .delay (10000,10000,10000) L_0x2adb880/d;
+L_0x2adb9e0/d .functor NOT 1, L_0x2adb880, C4<0>, C4<0>, C4<0>;
+L_0x2adb9e0 .delay (10000,10000,10000) L_0x2adb9e0/d;
+v0x283aba0_0 .net "A", 0 0, L_0x2adb780; 1 drivers
+v0x283ac60_0 .net "AandB", 0 0, L_0x2adb9e0; 1 drivers
+v0x283ace0_0 .net "AnandB", 0 0, L_0x2adb880; 1 drivers
+v0x283ad90_0 .net "AndNandOut", 0 0, L_0x2adbe30; 1 drivers
+v0x283ae70_0 .net "B", 0 0, L_0x2adc200; 1 drivers
+v0x283aef0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2adc000 .part v0x2960210_0, 0, 1;
+S_0x283a650 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x283a560;
+ .timescale -9 -12;
+L_0x2adbb10/d .functor NOT 1, L_0x2adc000, C4<0>, C4<0>, C4<0>;
+L_0x2adbb10 .delay (10000,10000,10000) L_0x2adbb10/d;
+L_0x2adbbd0/d .functor AND 1, L_0x2adb9e0, L_0x2adbb10, C4<1>, C4<1>;
+L_0x2adbbd0 .delay (20000,20000,20000) L_0x2adbbd0/d;
+L_0x2adbce0/d .functor AND 1, L_0x2adb880, L_0x2adc000, C4<1>, C4<1>;
+L_0x2adbce0 .delay (20000,20000,20000) L_0x2adbce0/d;
+L_0x2adbe30/d .functor OR 1, L_0x2adbbd0, L_0x2adbce0, C4<0>, C4<0>;
+L_0x2adbe30 .delay (20000,20000,20000) L_0x2adbe30/d;
+v0x283a740_0 .net "S", 0 0, L_0x2adc000; 1 drivers
+v0x283a7c0_0 .alias "in0", 0 0, v0x283ac60_0;
+v0x283a860_0 .alias "in1", 0 0, v0x283ace0_0;
+v0x283a900_0 .net "nS", 0 0, L_0x2adbb10; 1 drivers
+v0x283a980_0 .net "out0", 0 0, L_0x2adbbd0; 1 drivers
+v0x283aa20_0 .net "out1", 0 0, L_0x2adbce0; 1 drivers
+v0x283ab00_0 .alias "outfinal", 0 0, v0x283ad90_0;
+S_0x2839830 .scope generate, "andbits[9]" "andbits[9]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2839928 .param/l "i" 3 231, +C4<01001>;
+S_0x28399a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2839830;
+ .timescale -9 -12;
+L_0x2adc140/d .functor NAND 1, L_0x2adcbc0, L_0x2adc2f0, C4<1>, C4<1>;
+L_0x2adc140 .delay (10000,10000,10000) L_0x2adc140/d;
+L_0x2adc460/d .functor NOT 1, L_0x2adc140, C4<0>, C4<0>, C4<0>;
+L_0x2adc460 .delay (10000,10000,10000) L_0x2adc460/d;
+v0x2839fe0_0 .net "A", 0 0, L_0x2adcbc0; 1 drivers
+v0x283a0a0_0 .net "AandB", 0 0, L_0x2adc460; 1 drivers
+v0x283a120_0 .net "AnandB", 0 0, L_0x2adc140; 1 drivers
+v0x283a1d0_0 .net "AndNandOut", 0 0, L_0x2adc8b0; 1 drivers
+v0x283a2b0_0 .net "B", 0 0, L_0x2adc2f0; 1 drivers
+v0x283a330_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2adca80 .part v0x2960210_0, 0, 1;
+S_0x2839a90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28399a0;
+ .timescale -9 -12;
+L_0x2adc590/d .functor NOT 1, L_0x2adca80, C4<0>, C4<0>, C4<0>;
+L_0x2adc590 .delay (10000,10000,10000) L_0x2adc590/d;
+L_0x2adc650/d .functor AND 1, L_0x2adc460, L_0x2adc590, C4<1>, C4<1>;
+L_0x2adc650 .delay (20000,20000,20000) L_0x2adc650/d;
+L_0x2adc760/d .functor AND 1, L_0x2adc140, L_0x2adca80, C4<1>, C4<1>;
+L_0x2adc760 .delay (20000,20000,20000) L_0x2adc760/d;
+L_0x2adc8b0/d .functor OR 1, L_0x2adc650, L_0x2adc760, C4<0>, C4<0>;
+L_0x2adc8b0 .delay (20000,20000,20000) L_0x2adc8b0/d;
+v0x2839b80_0 .net "S", 0 0, L_0x2adca80; 1 drivers
+v0x2839c00_0 .alias "in0", 0 0, v0x283a0a0_0;
+v0x2839ca0_0 .alias "in1", 0 0, v0x283a120_0;
+v0x2839d40_0 .net "nS", 0 0, L_0x2adc590; 1 drivers
+v0x2839dc0_0 .net "out0", 0 0, L_0x2adc650; 1 drivers
+v0x2839e60_0 .net "out1", 0 0, L_0x2adc760; 1 drivers
+v0x2839f40_0 .alias "outfinal", 0 0, v0x283a1d0_0;
+S_0x2838c70 .scope generate, "andbits[10]" "andbits[10]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2838d68 .param/l "i" 3 231, +C4<01010>;
+S_0x2838de0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2838c70;
+ .timescale -9 -12;
+L_0x2adcd90/d .functor NAND 1, L_0x2adcc60, L_0x2add580, C4<1>, C4<1>;
+L_0x2adcd90 .delay (10000,10000,10000) L_0x2adcd90/d;
+L_0x2adced0/d .functor NOT 1, L_0x2adcd90, C4<0>, C4<0>, C4<0>;
+L_0x2adced0 .delay (10000,10000,10000) L_0x2adced0/d;
+v0x2839420_0 .net "A", 0 0, L_0x2adcc60; 1 drivers
+v0x28394e0_0 .net "AandB", 0 0, L_0x2adced0; 1 drivers
+v0x2839560_0 .net "AnandB", 0 0, L_0x2adcd90; 1 drivers
+v0x2839610_0 .net "AndNandOut", 0 0, L_0x2add1c0; 1 drivers
+v0x28396f0_0 .net "B", 0 0, L_0x2add580; 1 drivers
+v0x2839770_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2add350 .part v0x2960210_0, 0, 1;
+S_0x2838ed0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2838de0;
+ .timescale -9 -12;
+L_0x2ad9840/d .functor NOT 1, L_0x2add350, C4<0>, C4<0>, C4<0>;
+L_0x2ad9840 .delay (10000,10000,10000) L_0x2ad9840/d;
+L_0x2adcf90/d .functor AND 1, L_0x2adced0, L_0x2ad9840, C4<1>, C4<1>;
+L_0x2adcf90 .delay (20000,20000,20000) L_0x2adcf90/d;
+L_0x2add090/d .functor AND 1, L_0x2adcd90, L_0x2add350, C4<1>, C4<1>;
+L_0x2add090 .delay (20000,20000,20000) L_0x2add090/d;
+L_0x2add1c0/d .functor OR 1, L_0x2adcf90, L_0x2add090, C4<0>, C4<0>;
+L_0x2add1c0 .delay (20000,20000,20000) L_0x2add1c0/d;
+v0x2838fc0_0 .net "S", 0 0, L_0x2add350; 1 drivers
+v0x2839040_0 .alias "in0", 0 0, v0x28394e0_0;
+v0x28390e0_0 .alias "in1", 0 0, v0x2839560_0;
+v0x2839180_0 .net "nS", 0 0, L_0x2ad9840; 1 drivers
+v0x2839200_0 .net "out0", 0 0, L_0x2adcf90; 1 drivers
+v0x28392a0_0 .net "out1", 0 0, L_0x2add090; 1 drivers
+v0x2839380_0 .alias "outfinal", 0 0, v0x2839610_0;
+S_0x28380b0 .scope generate, "andbits[11]" "andbits[11]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x28381a8 .param/l "i" 3 231, +C4<01011>;
+S_0x2838220 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28380b0;
+ .timescale -9 -12;
+L_0x2add490/d .functor NAND 1, L_0x2adde40, L_0x2add670, C4<1>, C4<1>;
+L_0x2add490 .delay (10000,10000,10000) L_0x2add490/d;
+L_0x2add7c0/d .functor NOT 1, L_0x2add490, C4<0>, C4<0>, C4<0>;
+L_0x2add7c0 .delay (10000,10000,10000) L_0x2add7c0/d;
+v0x2838860_0 .net "A", 0 0, L_0x2adde40; 1 drivers
+v0x2838920_0 .net "AandB", 0 0, L_0x2add7c0; 1 drivers
+v0x28389a0_0 .net "AnandB", 0 0, L_0x2add490; 1 drivers
+v0x2838a50_0 .net "AndNandOut", 0 0, L_0x2addb70; 1 drivers
+v0x2838b30_0 .net "B", 0 0, L_0x2add670; 1 drivers
+v0x2838bb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2addd00 .part v0x2960210_0, 0, 1;
+S_0x2838310 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2838220;
+ .timescale -9 -12;
+L_0x2add8b0/d .functor NOT 1, L_0x2addd00, C4<0>, C4<0>, C4<0>;
+L_0x2add8b0 .delay (10000,10000,10000) L_0x2add8b0/d;
+L_0x2add950/d .functor AND 1, L_0x2add7c0, L_0x2add8b0, C4<1>, C4<1>;
+L_0x2add950 .delay (20000,20000,20000) L_0x2add950/d;
+L_0x2adda40/d .functor AND 1, L_0x2add490, L_0x2addd00, C4<1>, C4<1>;
+L_0x2adda40 .delay (20000,20000,20000) L_0x2adda40/d;
+L_0x2addb70/d .functor OR 1, L_0x2add950, L_0x2adda40, C4<0>, C4<0>;
+L_0x2addb70 .delay (20000,20000,20000) L_0x2addb70/d;
+v0x2838400_0 .net "S", 0 0, L_0x2addd00; 1 drivers
+v0x2838480_0 .alias "in0", 0 0, v0x2838920_0;
+v0x2838520_0 .alias "in1", 0 0, v0x28389a0_0;
+v0x28385c0_0 .net "nS", 0 0, L_0x2add8b0; 1 drivers
+v0x2838640_0 .net "out0", 0 0, L_0x2add950; 1 drivers
+v0x28386e0_0 .net "out1", 0 0, L_0x2adda40; 1 drivers
+v0x28387c0_0 .alias "outfinal", 0 0, v0x2838a50_0;
+S_0x28374f0 .scope generate, "andbits[12]" "andbits[12]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x28375e8 .param/l "i" 3 231, +C4<01100>;
+S_0x2837660 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28374f0;
+ .timescale -9 -12;
+L_0x2addff0/d .functor NAND 1, L_0x2addee0, L_0x2ade910, C4<1>, C4<1>;
+L_0x2addff0 .delay (10000,10000,10000) L_0x2addff0/d;
+L_0x2ade130/d .functor NOT 1, L_0x2addff0, C4<0>, C4<0>, C4<0>;
+L_0x2ade130 .delay (10000,10000,10000) L_0x2ade130/d;
+v0x2837ca0_0 .net "A", 0 0, L_0x2addee0; 1 drivers
+v0x2837d60_0 .net "AandB", 0 0, L_0x2ade130; 1 drivers
+v0x2837de0_0 .net "AnandB", 0 0, L_0x2addff0; 1 drivers
+v0x2837e90_0 .net "AndNandOut", 0 0, L_0x2ade4e0; 1 drivers
+v0x2837f70_0 .net "B", 0 0, L_0x2ade910; 1 drivers
+v0x2837ff0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ade6b0 .part v0x2960210_0, 0, 1;
+S_0x2837750 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2837660;
+ .timescale -9 -12;
+L_0x2ade220/d .functor NOT 1, L_0x2ade6b0, C4<0>, C4<0>, C4<0>;
+L_0x2ade220 .delay (10000,10000,10000) L_0x2ade220/d;
+L_0x2ade2c0/d .functor AND 1, L_0x2ade130, L_0x2ade220, C4<1>, C4<1>;
+L_0x2ade2c0 .delay (20000,20000,20000) L_0x2ade2c0/d;
+L_0x2ade3b0/d .functor AND 1, L_0x2addff0, L_0x2ade6b0, C4<1>, C4<1>;
+L_0x2ade3b0 .delay (20000,20000,20000) L_0x2ade3b0/d;
+L_0x2ade4e0/d .functor OR 1, L_0x2ade2c0, L_0x2ade3b0, C4<0>, C4<0>;
+L_0x2ade4e0 .delay (20000,20000,20000) L_0x2ade4e0/d;
+v0x2837840_0 .net "S", 0 0, L_0x2ade6b0; 1 drivers
+v0x28378c0_0 .alias "in0", 0 0, v0x2837d60_0;
+v0x2837960_0 .alias "in1", 0 0, v0x2837de0_0;
+v0x2837a00_0 .net "nS", 0 0, L_0x2ade220; 1 drivers
+v0x2837a80_0 .net "out0", 0 0, L_0x2ade2c0; 1 drivers
+v0x2837b20_0 .net "out1", 0 0, L_0x2ade3b0; 1 drivers
+v0x2837c00_0 .alias "outfinal", 0 0, v0x2837e90_0;
+S_0x2836930 .scope generate, "andbits[13]" "andbits[13]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2836a28 .param/l "i" 3 231, +C4<01101>;
+S_0x2836aa0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2836930;
+ .timescale -9 -12;
+L_0x2ade7f0/d .functor NAND 1, L_0x2adf270, L_0x2ade9b0, C4<1>, C4<1>;
+L_0x2ade7f0 .delay (10000,10000,10000) L_0x2ade7f0/d;
+L_0x2adeb30/d .functor NOT 1, L_0x2ade7f0, C4<0>, C4<0>, C4<0>;
+L_0x2adeb30 .delay (10000,10000,10000) L_0x2adeb30/d;
+v0x28370e0_0 .net "A", 0 0, L_0x2adf270; 1 drivers
+v0x28371a0_0 .net "AandB", 0 0, L_0x2adeb30; 1 drivers
+v0x2837220_0 .net "AnandB", 0 0, L_0x2ade7f0; 1 drivers
+v0x28372d0_0 .net "AndNandOut", 0 0, L_0x2adef60; 1 drivers
+v0x28373b0_0 .net "B", 0 0, L_0x2ade9b0; 1 drivers
+v0x2837430_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2adf130 .part v0x2960210_0, 0, 1;
+S_0x2836b90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2836aa0;
+ .timescale -9 -12;
+L_0x2adec40/d .functor NOT 1, L_0x2adf130, C4<0>, C4<0>, C4<0>;
+L_0x2adec40 .delay (10000,10000,10000) L_0x2adec40/d;
+L_0x2aded00/d .functor AND 1, L_0x2adeb30, L_0x2adec40, C4<1>, C4<1>;
+L_0x2aded00 .delay (20000,20000,20000) L_0x2aded00/d;
+L_0x2adee10/d .functor AND 1, L_0x2ade7f0, L_0x2adf130, C4<1>, C4<1>;
+L_0x2adee10 .delay (20000,20000,20000) L_0x2adee10/d;
+L_0x2adef60/d .functor OR 1, L_0x2aded00, L_0x2adee10, C4<0>, C4<0>;
+L_0x2adef60 .delay (20000,20000,20000) L_0x2adef60/d;
+v0x2836c80_0 .net "S", 0 0, L_0x2adf130; 1 drivers
+v0x2836d00_0 .alias "in0", 0 0, v0x28371a0_0;
+v0x2836da0_0 .alias "in1", 0 0, v0x2837220_0;
+v0x2836e40_0 .net "nS", 0 0, L_0x2adec40; 1 drivers
+v0x2836ec0_0 .net "out0", 0 0, L_0x2aded00; 1 drivers
+v0x2836f60_0 .net "out1", 0 0, L_0x2adee10; 1 drivers
+v0x2837040_0 .alias "outfinal", 0 0, v0x28372d0_0;
+S_0x2835d70 .scope generate, "andbits[14]" "andbits[14]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2835e68 .param/l "i" 3 231, +C4<01110>;
+S_0x2835ee0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2835d70;
+ .timescale -9 -12;
+L_0x2adf450/d .functor NAND 1, L_0x2adf310, L_0x2adf3b0, C4<1>, C4<1>;
+L_0x2adf450 .delay (10000,10000,10000) L_0x2adf450/d;
+L_0x2adf590/d .functor NOT 1, L_0x2adf450, C4<0>, C4<0>, C4<0>;
+L_0x2adf590 .delay (10000,10000,10000) L_0x2adf590/d;
+v0x2836520_0 .net "A", 0 0, L_0x2adf310; 1 drivers
+v0x28365e0_0 .net "AandB", 0 0, L_0x2adf590; 1 drivers
+v0x2836660_0 .net "AnandB", 0 0, L_0x2adf450; 1 drivers
+v0x2836710_0 .net "AndNandOut", 0 0, L_0x2adf9c0; 1 drivers
+v0x28367f0_0 .net "B", 0 0, L_0x2adf3b0; 1 drivers
+v0x2836870_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2adfb90 .part v0x2960210_0, 0, 1;
+S_0x2835fd0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2835ee0;
+ .timescale -9 -12;
+L_0x2adf6a0/d .functor NOT 1, L_0x2adfb90, C4<0>, C4<0>, C4<0>;
+L_0x2adf6a0 .delay (10000,10000,10000) L_0x2adf6a0/d;
+L_0x2adf760/d .functor AND 1, L_0x2adf590, L_0x2adf6a0, C4<1>, C4<1>;
+L_0x2adf760 .delay (20000,20000,20000) L_0x2adf760/d;
+L_0x2adf870/d .functor AND 1, L_0x2adf450, L_0x2adfb90, C4<1>, C4<1>;
+L_0x2adf870 .delay (20000,20000,20000) L_0x2adf870/d;
+L_0x2adf9c0/d .functor OR 1, L_0x2adf760, L_0x2adf870, C4<0>, C4<0>;
+L_0x2adf9c0 .delay (20000,20000,20000) L_0x2adf9c0/d;
+v0x28360c0_0 .net "S", 0 0, L_0x2adfb90; 1 drivers
+v0x2836140_0 .alias "in0", 0 0, v0x28365e0_0;
+v0x28361e0_0 .alias "in1", 0 0, v0x2836660_0;
+v0x2836280_0 .net "nS", 0 0, L_0x2adf6a0; 1 drivers
+v0x2836300_0 .net "out0", 0 0, L_0x2adf760; 1 drivers
+v0x28363a0_0 .net "out1", 0 0, L_0x2adf870; 1 drivers
+v0x2836480_0 .alias "outfinal", 0 0, v0x2836710_0;
+S_0x28351b0 .scope generate, "andbits[15]" "andbits[15]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x28352a8 .param/l "i" 3 231, +C4<01111>;
+S_0x2835320 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28351b0;
+ .timescale -9 -12;
+L_0x2adfcd0/d .functor NAND 1, L_0x2ae0740, L_0x2adfe70, C4<1>, C4<1>;
+L_0x2adfcd0 .delay (10000,10000,10000) L_0x2adfcd0/d;
+L_0x2ae0020/d .functor NOT 1, L_0x2adfcd0, C4<0>, C4<0>, C4<0>;
+L_0x2ae0020 .delay (10000,10000,10000) L_0x2ae0020/d;
+v0x2835960_0 .net "A", 0 0, L_0x2ae0740; 1 drivers
+v0x2835a20_0 .net "AandB", 0 0, L_0x2ae0020; 1 drivers
+v0x2835aa0_0 .net "AnandB", 0 0, L_0x2adfcd0; 1 drivers
+v0x2835b50_0 .net "AndNandOut", 0 0, L_0x2ae0430; 1 drivers
+v0x2835c30_0 .net "B", 0 0, L_0x2adfe70; 1 drivers
+v0x2835cb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae0600 .part v0x2960210_0, 0, 1;
+S_0x2835410 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2835320;
+ .timescale -9 -12;
+L_0x2ae0110/d .functor NOT 1, L_0x2ae0600, C4<0>, C4<0>, C4<0>;
+L_0x2ae0110 .delay (10000,10000,10000) L_0x2ae0110/d;
+L_0x2ae01d0/d .functor AND 1, L_0x2ae0020, L_0x2ae0110, C4<1>, C4<1>;
+L_0x2ae01d0 .delay (20000,20000,20000) L_0x2ae01d0/d;
+L_0x2ae02e0/d .functor AND 1, L_0x2adfcd0, L_0x2ae0600, C4<1>, C4<1>;
+L_0x2ae02e0 .delay (20000,20000,20000) L_0x2ae02e0/d;
+L_0x2ae0430/d .functor OR 1, L_0x2ae01d0, L_0x2ae02e0, C4<0>, C4<0>;
+L_0x2ae0430 .delay (20000,20000,20000) L_0x2ae0430/d;
+v0x2835500_0 .net "S", 0 0, L_0x2ae0600; 1 drivers
+v0x2835580_0 .alias "in0", 0 0, v0x2835a20_0;
+v0x2835620_0 .alias "in1", 0 0, v0x2835aa0_0;
+v0x28356c0_0 .net "nS", 0 0, L_0x2ae0110; 1 drivers
+v0x2835740_0 .net "out0", 0 0, L_0x2ae01d0; 1 drivers
+v0x28357e0_0 .net "out1", 0 0, L_0x2ae02e0; 1 drivers
+v0x28358c0_0 .alias "outfinal", 0 0, v0x2835b50_0;
+S_0x28345f0 .scope generate, "andbits[16]" "andbits[16]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x28346e8 .param/l "i" 3 231, +C4<010000>;
+S_0x2834760 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28345f0;
+ .timescale -9 -12;
+L_0x2adff60/d .functor NAND 1, L_0x2ae07e0, L_0x2ae0880, C4<1>, C4<1>;
+L_0x2adff60 .delay (10000,10000,10000) L_0x2adff60/d;
+L_0x2ae0a50/d .functor NOT 1, L_0x2adff60, C4<0>, C4<0>, C4<0>;
+L_0x2ae0a50 .delay (10000,10000,10000) L_0x2ae0a50/d;
+v0x2834da0_0 .net "A", 0 0, L_0x2ae07e0; 1 drivers
+v0x2834e60_0 .net "AandB", 0 0, L_0x2ae0a50; 1 drivers
+v0x2834ee0_0 .net "AnandB", 0 0, L_0x2adff60; 1 drivers
+v0x2834f90_0 .net "AndNandOut", 0 0, L_0x2ae0ea0; 1 drivers
+v0x2835070_0 .net "B", 0 0, L_0x2ae0880; 1 drivers
+v0x28350f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae1070 .part v0x2960210_0, 0, 1;
+S_0x2834850 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2834760;
+ .timescale -9 -12;
+L_0x2ae0b80/d .functor NOT 1, L_0x2ae1070, C4<0>, C4<0>, C4<0>;
+L_0x2ae0b80 .delay (10000,10000,10000) L_0x2ae0b80/d;
+L_0x2ae0c40/d .functor AND 1, L_0x2ae0a50, L_0x2ae0b80, C4<1>, C4<1>;
+L_0x2ae0c40 .delay (20000,20000,20000) L_0x2ae0c40/d;
+L_0x2ae0d50/d .functor AND 1, L_0x2adff60, L_0x2ae1070, C4<1>, C4<1>;
+L_0x2ae0d50 .delay (20000,20000,20000) L_0x2ae0d50/d;
+L_0x2ae0ea0/d .functor OR 1, L_0x2ae0c40, L_0x2ae0d50, C4<0>, C4<0>;
+L_0x2ae0ea0 .delay (20000,20000,20000) L_0x2ae0ea0/d;
+v0x2834940_0 .net "S", 0 0, L_0x2ae1070; 1 drivers
+v0x28349c0_0 .alias "in0", 0 0, v0x2834e60_0;
+v0x2834a60_0 .alias "in1", 0 0, v0x2834ee0_0;
+v0x2834b00_0 .net "nS", 0 0, L_0x2ae0b80; 1 drivers
+v0x2834b80_0 .net "out0", 0 0, L_0x2ae0c40; 1 drivers
+v0x2834c20_0 .net "out1", 0 0, L_0x2ae0d50; 1 drivers
+v0x2834d00_0 .alias "outfinal", 0 0, v0x2834f90_0;
+S_0x2833a30 .scope generate, "andbits[17]" "andbits[17]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2833b28 .param/l "i" 3 231, +C4<010001>;
+S_0x2833ba0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2833a30;
+ .timescale -9 -12;
+L_0x2ae11b0/d .functor NAND 1, L_0x2ae1c30, L_0x2ae1380, C4<1>, C4<1>;
+L_0x2ae11b0 .delay (10000,10000,10000) L_0x2ae11b0/d;
+L_0x2ae1510/d .functor NOT 1, L_0x2ae11b0, C4<0>, C4<0>, C4<0>;
+L_0x2ae1510 .delay (10000,10000,10000) L_0x2ae1510/d;
+v0x28341e0_0 .net "A", 0 0, L_0x2ae1c30; 1 drivers
+v0x28342a0_0 .net "AandB", 0 0, L_0x2ae1510; 1 drivers
+v0x2834320_0 .net "AnandB", 0 0, L_0x2ae11b0; 1 drivers
+v0x28343d0_0 .net "AndNandOut", 0 0, L_0x2ae1920; 1 drivers
+v0x28344b0_0 .net "B", 0 0, L_0x2ae1380; 1 drivers
+v0x2834530_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae1af0 .part v0x2960210_0, 0, 1;
+S_0x2833c90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2833ba0;
+ .timescale -9 -12;
+L_0x2ae1600/d .functor NOT 1, L_0x2ae1af0, C4<0>, C4<0>, C4<0>;
+L_0x2ae1600 .delay (10000,10000,10000) L_0x2ae1600/d;
+L_0x2ae16c0/d .functor AND 1, L_0x2ae1510, L_0x2ae1600, C4<1>, C4<1>;
+L_0x2ae16c0 .delay (20000,20000,20000) L_0x2ae16c0/d;
+L_0x2ae17d0/d .functor AND 1, L_0x2ae11b0, L_0x2ae1af0, C4<1>, C4<1>;
+L_0x2ae17d0 .delay (20000,20000,20000) L_0x2ae17d0/d;
+L_0x2ae1920/d .functor OR 1, L_0x2ae16c0, L_0x2ae17d0, C4<0>, C4<0>;
+L_0x2ae1920 .delay (20000,20000,20000) L_0x2ae1920/d;
+v0x2833d80_0 .net "S", 0 0, L_0x2ae1af0; 1 drivers
+v0x2833e00_0 .alias "in0", 0 0, v0x28342a0_0;
+v0x2833ea0_0 .alias "in1", 0 0, v0x2834320_0;
+v0x2833f40_0 .net "nS", 0 0, L_0x2ae1600; 1 drivers
+v0x2833fc0_0 .net "out0", 0 0, L_0x2ae16c0; 1 drivers
+v0x2834060_0 .net "out1", 0 0, L_0x2ae17d0; 1 drivers
+v0x2834140_0 .alias "outfinal", 0 0, v0x28343d0_0;
+S_0x2832e70 .scope generate, "andbits[18]" "andbits[18]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2832f68 .param/l "i" 3 231, +C4<010010>;
+S_0x2832fe0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2832e70;
+ .timescale -9 -12;
+L_0x2ae1470/d .functor NAND 1, L_0x2ae1cd0, L_0x2ae1d70, C4<1>, C4<1>;
+L_0x2ae1470 .delay (10000,10000,10000) L_0x2ae1470/d;
+L_0x2ae1f50/d .functor NOT 1, L_0x2ae1470, C4<0>, C4<0>, C4<0>;
+L_0x2ae1f50 .delay (10000,10000,10000) L_0x2ae1f50/d;
+v0x2833620_0 .net "A", 0 0, L_0x2ae1cd0; 1 drivers
+v0x28336e0_0 .net "AandB", 0 0, L_0x2ae1f50; 1 drivers
+v0x2833760_0 .net "AnandB", 0 0, L_0x2ae1470; 1 drivers
+v0x2833810_0 .net "AndNandOut", 0 0, L_0x2ae2380; 1 drivers
+v0x28338f0_0 .net "B", 0 0, L_0x2ae1d70; 1 drivers
+v0x2833970_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae2550 .part v0x2960210_0, 0, 1;
+S_0x28330d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2832fe0;
+ .timescale -9 -12;
+L_0x2ae2060/d .functor NOT 1, L_0x2ae2550, C4<0>, C4<0>, C4<0>;
+L_0x2ae2060 .delay (10000,10000,10000) L_0x2ae2060/d;
+L_0x2ae2120/d .functor AND 1, L_0x2ae1f50, L_0x2ae2060, C4<1>, C4<1>;
+L_0x2ae2120 .delay (20000,20000,20000) L_0x2ae2120/d;
+L_0x2ae2230/d .functor AND 1, L_0x2ae1470, L_0x2ae2550, C4<1>, C4<1>;
+L_0x2ae2230 .delay (20000,20000,20000) L_0x2ae2230/d;
+L_0x2ae2380/d .functor OR 1, L_0x2ae2120, L_0x2ae2230, C4<0>, C4<0>;
+L_0x2ae2380 .delay (20000,20000,20000) L_0x2ae2380/d;
+v0x28331c0_0 .net "S", 0 0, L_0x2ae2550; 1 drivers
+v0x2833240_0 .alias "in0", 0 0, v0x28336e0_0;
+v0x28332e0_0 .alias "in1", 0 0, v0x2833760_0;
+v0x2833380_0 .net "nS", 0 0, L_0x2ae2060; 1 drivers
+v0x2833400_0 .net "out0", 0 0, L_0x2ae2120; 1 drivers
+v0x28334a0_0 .net "out1", 0 0, L_0x2ae2230; 1 drivers
+v0x2833580_0 .alias "outfinal", 0 0, v0x2833810_0;
+S_0x28322b0 .scope generate, "andbits[19]" "andbits[19]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x28323a8 .param/l "i" 3 231, +C4<010011>;
+S_0x2832420 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28322b0;
+ .timescale -9 -12;
+L_0x2ae2850/d .functor NAND 1, L_0x2ae3110, L_0x2ae2690, C4<1>, C4<1>;
+L_0x2ae2850 .delay (10000,10000,10000) L_0x2ae2850/d;
+L_0x2ae29b0/d .functor NOT 1, L_0x2ae2850, C4<0>, C4<0>, C4<0>;
+L_0x2ae29b0 .delay (10000,10000,10000) L_0x2ae29b0/d;
+v0x2832a60_0 .net "A", 0 0, L_0x2ae3110; 1 drivers
+v0x2832b20_0 .net "AandB", 0 0, L_0x2ae29b0; 1 drivers
+v0x2832ba0_0 .net "AnandB", 0 0, L_0x2ae2850; 1 drivers
+v0x2832c50_0 .net "AndNandOut", 0 0, L_0x2ae2e00; 1 drivers
+v0x2832d30_0 .net "B", 0 0, L_0x2ae2690; 1 drivers
+v0x2832db0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae2fd0 .part v0x2960210_0, 0, 1;
+S_0x2832510 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2832420;
+ .timescale -9 -12;
+L_0x2ae2ae0/d .functor NOT 1, L_0x2ae2fd0, C4<0>, C4<0>, C4<0>;
+L_0x2ae2ae0 .delay (10000,10000,10000) L_0x2ae2ae0/d;
+L_0x2ae2ba0/d .functor AND 1, L_0x2ae29b0, L_0x2ae2ae0, C4<1>, C4<1>;
+L_0x2ae2ba0 .delay (20000,20000,20000) L_0x2ae2ba0/d;
+L_0x2ae2cb0/d .functor AND 1, L_0x2ae2850, L_0x2ae2fd0, C4<1>, C4<1>;
+L_0x2ae2cb0 .delay (20000,20000,20000) L_0x2ae2cb0/d;
+L_0x2ae2e00/d .functor OR 1, L_0x2ae2ba0, L_0x2ae2cb0, C4<0>, C4<0>;
+L_0x2ae2e00 .delay (20000,20000,20000) L_0x2ae2e00/d;
+v0x2832600_0 .net "S", 0 0, L_0x2ae2fd0; 1 drivers
+v0x2832680_0 .alias "in0", 0 0, v0x2832b20_0;
+v0x2832720_0 .alias "in1", 0 0, v0x2832ba0_0;
+v0x28327c0_0 .net "nS", 0 0, L_0x2ae2ae0; 1 drivers
+v0x2832840_0 .net "out0", 0 0, L_0x2ae2ba0; 1 drivers
+v0x28328e0_0 .net "out1", 0 0, L_0x2ae2cb0; 1 drivers
+v0x28329c0_0 .alias "outfinal", 0 0, v0x2832c50_0;
+S_0x28316f0 .scope generate, "andbits[20]" "andbits[20]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x28317e8 .param/l "i" 3 231, +C4<010100>;
+S_0x2831860 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x28316f0;
+ .timescale -9 -12;
+L_0x2ae2780/d .functor NAND 1, L_0x2ae31b0, L_0x2ae3250, C4<1>, C4<1>;
+L_0x2ae2780 .delay (10000,10000,10000) L_0x2ae2780/d;
+L_0x2ae3410/d .functor NOT 1, L_0x2ae2780, C4<0>, C4<0>, C4<0>;
+L_0x2ae3410 .delay (10000,10000,10000) L_0x2ae3410/d;
+v0x2831ea0_0 .net "A", 0 0, L_0x2ae31b0; 1 drivers
+v0x2831f60_0 .net "AandB", 0 0, L_0x2ae3410; 1 drivers
+v0x2831fe0_0 .net "AnandB", 0 0, L_0x2ae2780; 1 drivers
+v0x2832090_0 .net "AndNandOut", 0 0, L_0x2ae3860; 1 drivers
+v0x2832170_0 .net "B", 0 0, L_0x2ae3250; 1 drivers
+v0x28321f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae3a30 .part v0x2960210_0, 0, 1;
+S_0x2831950 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2831860;
+ .timescale -9 -12;
+L_0x2ae3540/d .functor NOT 1, L_0x2ae3a30, C4<0>, C4<0>, C4<0>;
+L_0x2ae3540 .delay (10000,10000,10000) L_0x2ae3540/d;
+L_0x2ae3600/d .functor AND 1, L_0x2ae3410, L_0x2ae3540, C4<1>, C4<1>;
+L_0x2ae3600 .delay (20000,20000,20000) L_0x2ae3600/d;
+L_0x2ae3710/d .functor AND 1, L_0x2ae2780, L_0x2ae3a30, C4<1>, C4<1>;
+L_0x2ae3710 .delay (20000,20000,20000) L_0x2ae3710/d;
+L_0x2ae3860/d .functor OR 1, L_0x2ae3600, L_0x2ae3710, C4<0>, C4<0>;
+L_0x2ae3860 .delay (20000,20000,20000) L_0x2ae3860/d;
+v0x2831a40_0 .net "S", 0 0, L_0x2ae3a30; 1 drivers
+v0x2831ac0_0 .alias "in0", 0 0, v0x2831f60_0;
+v0x2831b60_0 .alias "in1", 0 0, v0x2831fe0_0;
+v0x2831c00_0 .net "nS", 0 0, L_0x2ae3540; 1 drivers
+v0x2831c80_0 .net "out0", 0 0, L_0x2ae3600; 1 drivers
+v0x2831d20_0 .net "out1", 0 0, L_0x2ae3710; 1 drivers
+v0x2831e00_0 .alias "outfinal", 0 0, v0x2832090_0;
+S_0x2830b30 .scope generate, "andbits[21]" "andbits[21]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2830c28 .param/l "i" 3 231, +C4<010101>;
+S_0x2830ca0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2830b30;
+ .timescale -9 -12;
+L_0x2ae3d60/d .functor NAND 1, L_0x2ae45e0, L_0x2ae3b70, C4<1>, C4<1>;
+L_0x2ae3d60 .delay (10000,10000,10000) L_0x2ae3d60/d;
+L_0x2ae3ea0/d .functor NOT 1, L_0x2ae3d60, C4<0>, C4<0>, C4<0>;
+L_0x2ae3ea0 .delay (10000,10000,10000) L_0x2ae3ea0/d;
+v0x28312e0_0 .net "A", 0 0, L_0x2ae45e0; 1 drivers
+v0x28313a0_0 .net "AandB", 0 0, L_0x2ae3ea0; 1 drivers
+v0x2831420_0 .net "AnandB", 0 0, L_0x2ae3d60; 1 drivers
+v0x28314d0_0 .net "AndNandOut", 0 0, L_0x2ae42d0; 1 drivers
+v0x28315b0_0 .net "B", 0 0, L_0x2ae3b70; 1 drivers
+v0x2831630_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae44a0 .part v0x2960210_0, 0, 1;
+S_0x2830d90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2830ca0;
+ .timescale -9 -12;
+L_0x2ae3fb0/d .functor NOT 1, L_0x2ae44a0, C4<0>, C4<0>, C4<0>;
+L_0x2ae3fb0 .delay (10000,10000,10000) L_0x2ae3fb0/d;
+L_0x2ae4070/d .functor AND 1, L_0x2ae3ea0, L_0x2ae3fb0, C4<1>, C4<1>;
+L_0x2ae4070 .delay (20000,20000,20000) L_0x2ae4070/d;
+L_0x2ae4180/d .functor AND 1, L_0x2ae3d60, L_0x2ae44a0, C4<1>, C4<1>;
+L_0x2ae4180 .delay (20000,20000,20000) L_0x2ae4180/d;
+L_0x2ae42d0/d .functor OR 1, L_0x2ae4070, L_0x2ae4180, C4<0>, C4<0>;
+L_0x2ae42d0 .delay (20000,20000,20000) L_0x2ae42d0/d;
+v0x2830e80_0 .net "S", 0 0, L_0x2ae44a0; 1 drivers
+v0x2830f00_0 .alias "in0", 0 0, v0x28313a0_0;
+v0x2830fa0_0 .alias "in1", 0 0, v0x2831420_0;
+v0x2831040_0 .net "nS", 0 0, L_0x2ae3fb0; 1 drivers
+v0x28310c0_0 .net "out0", 0 0, L_0x2ae4070; 1 drivers
+v0x2831160_0 .net "out1", 0 0, L_0x2ae4180; 1 drivers
+v0x2831240_0 .alias "outfinal", 0 0, v0x28314d0_0;
+S_0x282ff70 .scope generate, "andbits[22]" "andbits[22]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2830068 .param/l "i" 3 231, +C4<010110>;
+S_0x28300e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282ff70;
+ .timescale -9 -12;
+L_0x2ae3c60/d .functor NAND 1, L_0x2ae4680, L_0x2ae4720, C4<1>, C4<1>;
+L_0x2ae3c60 .delay (10000,10000,10000) L_0x2ae3c60/d;
+L_0x2ae4910/d .functor NOT 1, L_0x2ae3c60, C4<0>, C4<0>, C4<0>;
+L_0x2ae4910 .delay (10000,10000,10000) L_0x2ae4910/d;
+v0x2830720_0 .net "A", 0 0, L_0x2ae4680; 1 drivers
+v0x28307e0_0 .net "AandB", 0 0, L_0x2ae4910; 1 drivers
+v0x2830860_0 .net "AnandB", 0 0, L_0x2ae3c60; 1 drivers
+v0x2830910_0 .net "AndNandOut", 0 0, L_0x2ae4d40; 1 drivers
+v0x28309f0_0 .net "B", 0 0, L_0x2ae4720; 1 drivers
+v0x2830a70_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae4f10 .part v0x2960210_0, 0, 1;
+S_0x28301d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x28300e0;
+ .timescale -9 -12;
+L_0x2ae4a20/d .functor NOT 1, L_0x2ae4f10, C4<0>, C4<0>, C4<0>;
+L_0x2ae4a20 .delay (10000,10000,10000) L_0x2ae4a20/d;
+L_0x2ae4ae0/d .functor AND 1, L_0x2ae4910, L_0x2ae4a20, C4<1>, C4<1>;
+L_0x2ae4ae0 .delay (20000,20000,20000) L_0x2ae4ae0/d;
+L_0x2ae4bf0/d .functor AND 1, L_0x2ae3c60, L_0x2ae4f10, C4<1>, C4<1>;
+L_0x2ae4bf0 .delay (20000,20000,20000) L_0x2ae4bf0/d;
+L_0x2ae4d40/d .functor OR 1, L_0x2ae4ae0, L_0x2ae4bf0, C4<0>, C4<0>;
+L_0x2ae4d40 .delay (20000,20000,20000) L_0x2ae4d40/d;
+v0x28302c0_0 .net "S", 0 0, L_0x2ae4f10; 1 drivers
+v0x2830340_0 .alias "in0", 0 0, v0x28307e0_0;
+v0x28303e0_0 .alias "in1", 0 0, v0x2830860_0;
+v0x2830480_0 .net "nS", 0 0, L_0x2ae4a20; 1 drivers
+v0x2830500_0 .net "out0", 0 0, L_0x2ae4ae0; 1 drivers
+v0x28305a0_0 .net "out1", 0 0, L_0x2ae4bf0; 1 drivers
+v0x2830680_0 .alias "outfinal", 0 0, v0x2830910_0;
+S_0x282f3b0 .scope generate, "andbits[23]" "andbits[23]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282f4a8 .param/l "i" 3 231, +C4<010111>;
+S_0x282f520 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282f3b0;
+ .timescale -9 -12;
+L_0x2ae4810/d .functor NAND 1, L_0x2ae5ad0, L_0x2ae5050, C4<1>, C4<1>;
+L_0x2ae4810 .delay (10000,10000,10000) L_0x2ae4810/d;
+L_0x2ae5370/d .functor NOT 1, L_0x2ae4810, C4<0>, C4<0>, C4<0>;
+L_0x2ae5370 .delay (10000,10000,10000) L_0x2ae5370/d;
+v0x282fb60_0 .net "A", 0 0, L_0x2ae5ad0; 1 drivers
+v0x282fc20_0 .net "AandB", 0 0, L_0x2ae5370; 1 drivers
+v0x282fca0_0 .net "AnandB", 0 0, L_0x2ae4810; 1 drivers
+v0x282fd50_0 .net "AndNandOut", 0 0, L_0x2ae57c0; 1 drivers
+v0x282fe30_0 .net "B", 0 0, L_0x2ae5050; 1 drivers
+v0x282feb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae5990 .part v0x2960210_0, 0, 1;
+S_0x282f610 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282f520;
+ .timescale -9 -12;
+L_0x2ae54a0/d .functor NOT 1, L_0x2ae5990, C4<0>, C4<0>, C4<0>;
+L_0x2ae54a0 .delay (10000,10000,10000) L_0x2ae54a0/d;
+L_0x2ae5560/d .functor AND 1, L_0x2ae5370, L_0x2ae54a0, C4<1>, C4<1>;
+L_0x2ae5560 .delay (20000,20000,20000) L_0x2ae5560/d;
+L_0x2ae5670/d .functor AND 1, L_0x2ae4810, L_0x2ae5990, C4<1>, C4<1>;
+L_0x2ae5670 .delay (20000,20000,20000) L_0x2ae5670/d;
+L_0x2ae57c0/d .functor OR 1, L_0x2ae5560, L_0x2ae5670, C4<0>, C4<0>;
+L_0x2ae57c0 .delay (20000,20000,20000) L_0x2ae57c0/d;
+v0x282f700_0 .net "S", 0 0, L_0x2ae5990; 1 drivers
+v0x282f780_0 .alias "in0", 0 0, v0x282fc20_0;
+v0x282f820_0 .alias "in1", 0 0, v0x282fca0_0;
+v0x282f8c0_0 .net "nS", 0 0, L_0x2ae54a0; 1 drivers
+v0x282f940_0 .net "out0", 0 0, L_0x2ae5560; 1 drivers
+v0x282f9e0_0 .net "out1", 0 0, L_0x2ae5670; 1 drivers
+v0x282fac0_0 .alias "outfinal", 0 0, v0x282fd50_0;
+S_0x282e7f0 .scope generate, "andbits[24]" "andbits[24]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282e8e8 .param/l "i" 3 231, +C4<011000>;
+S_0x282e960 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282e7f0;
+ .timescale -9 -12;
+L_0x2ae5140/d .functor NAND 1, L_0x2ae5b70, L_0x2ae5c10, C4<1>, C4<1>;
+L_0x2ae5140 .delay (10000,10000,10000) L_0x2ae5140/d;
+L_0x2ae5df0/d .functor NOT 1, L_0x2ae5140, C4<0>, C4<0>, C4<0>;
+L_0x2ae5df0 .delay (10000,10000,10000) L_0x2ae5df0/d;
+v0x282efa0_0 .net "A", 0 0, L_0x2ae5b70; 1 drivers
+v0x282f060_0 .net "AandB", 0 0, L_0x2ae5df0; 1 drivers
+v0x282f0e0_0 .net "AnandB", 0 0, L_0x2ae5140; 1 drivers
+v0x282f190_0 .net "AndNandOut", 0 0, L_0x2ae6220; 1 drivers
+v0x282f270_0 .net "B", 0 0, L_0x2ae5c10; 1 drivers
+v0x282f2f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae63f0 .part v0x2960210_0, 0, 1;
+S_0x282ea50 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282e960;
+ .timescale -9 -12;
+L_0x2ae5f00/d .functor NOT 1, L_0x2ae63f0, C4<0>, C4<0>, C4<0>;
+L_0x2ae5f00 .delay (10000,10000,10000) L_0x2ae5f00/d;
+L_0x2ae5fc0/d .functor AND 1, L_0x2ae5df0, L_0x2ae5f00, C4<1>, C4<1>;
+L_0x2ae5fc0 .delay (20000,20000,20000) L_0x2ae5fc0/d;
+L_0x2ae60d0/d .functor AND 1, L_0x2ae5140, L_0x2ae63f0, C4<1>, C4<1>;
+L_0x2ae60d0 .delay (20000,20000,20000) L_0x2ae60d0/d;
+L_0x2ae6220/d .functor OR 1, L_0x2ae5fc0, L_0x2ae60d0, C4<0>, C4<0>;
+L_0x2ae6220 .delay (20000,20000,20000) L_0x2ae6220/d;
+v0x282eb40_0 .net "S", 0 0, L_0x2ae63f0; 1 drivers
+v0x282ebc0_0 .alias "in0", 0 0, v0x282f060_0;
+v0x282ec60_0 .alias "in1", 0 0, v0x282f0e0_0;
+v0x282ed00_0 .net "nS", 0 0, L_0x2ae5f00; 1 drivers
+v0x282ed80_0 .net "out0", 0 0, L_0x2ae5fc0; 1 drivers
+v0x282ee20_0 .net "out1", 0 0, L_0x2ae60d0; 1 drivers
+v0x282ef00_0 .alias "outfinal", 0 0, v0x282f190_0;
+S_0x282dc30 .scope generate, "andbits[25]" "andbits[25]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282dd28 .param/l "i" 3 231, +C4<011001>;
+S_0x282dda0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282dc30;
+ .timescale -9 -12;
+L_0x2ae5d00/d .functor NAND 1, L_0x2ae6fa0, L_0x2ae6530, C4<1>, C4<1>;
+L_0x2ae5d00 .delay (10000,10000,10000) L_0x2ae5d00/d;
+L_0x2ae6860/d .functor NOT 1, L_0x2ae5d00, C4<0>, C4<0>, C4<0>;
+L_0x2ae6860 .delay (10000,10000,10000) L_0x2ae6860/d;
+v0x282e3e0_0 .net "A", 0 0, L_0x2ae6fa0; 1 drivers
+v0x282e4a0_0 .net "AandB", 0 0, L_0x2ae6860; 1 drivers
+v0x282e520_0 .net "AnandB", 0 0, L_0x2ae5d00; 1 drivers
+v0x282e5d0_0 .net "AndNandOut", 0 0, L_0x2ae6c90; 1 drivers
+v0x282e6b0_0 .net "B", 0 0, L_0x2ae6530; 1 drivers
+v0x282e730_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae6e60 .part v0x2960210_0, 0, 1;
+S_0x282de90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282dda0;
+ .timescale -9 -12;
+L_0x2ae6970/d .functor NOT 1, L_0x2ae6e60, C4<0>, C4<0>, C4<0>;
+L_0x2ae6970 .delay (10000,10000,10000) L_0x2ae6970/d;
+L_0x2ae6a30/d .functor AND 1, L_0x2ae6860, L_0x2ae6970, C4<1>, C4<1>;
+L_0x2ae6a30 .delay (20000,20000,20000) L_0x2ae6a30/d;
+L_0x2ae6b40/d .functor AND 1, L_0x2ae5d00, L_0x2ae6e60, C4<1>, C4<1>;
+L_0x2ae6b40 .delay (20000,20000,20000) L_0x2ae6b40/d;
+L_0x2ae6c90/d .functor OR 1, L_0x2ae6a30, L_0x2ae6b40, C4<0>, C4<0>;
+L_0x2ae6c90 .delay (20000,20000,20000) L_0x2ae6c90/d;
+v0x282df80_0 .net "S", 0 0, L_0x2ae6e60; 1 drivers
+v0x282e000_0 .alias "in0", 0 0, v0x282e4a0_0;
+v0x282e0a0_0 .alias "in1", 0 0, v0x282e520_0;
+v0x282e140_0 .net "nS", 0 0, L_0x2ae6970; 1 drivers
+v0x282e1c0_0 .net "out0", 0 0, L_0x2ae6a30; 1 drivers
+v0x282e260_0 .net "out1", 0 0, L_0x2ae6b40; 1 drivers
+v0x282e340_0 .alias "outfinal", 0 0, v0x282e5d0_0;
+S_0x282d070 .scope generate, "andbits[26]" "andbits[26]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282d168 .param/l "i" 3 231, +C4<011010>;
+S_0x282d1e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282d070;
+ .timescale -9 -12;
+L_0x2ae6620/d .functor NAND 1, L_0x2ae7040, L_0x2ae70e0, C4<1>, C4<1>;
+L_0x2ae6620 .delay (10000,10000,10000) L_0x2ae6620/d;
+L_0x2ae72a0/d .functor NOT 1, L_0x2ae6620, C4<0>, C4<0>, C4<0>;
+L_0x2ae72a0 .delay (10000,10000,10000) L_0x2ae72a0/d;
+v0x282d820_0 .net "A", 0 0, L_0x2ae7040; 1 drivers
+v0x282d8e0_0 .net "AandB", 0 0, L_0x2ae72a0; 1 drivers
+v0x282d960_0 .net "AnandB", 0 0, L_0x2ae6620; 1 drivers
+v0x282da10_0 .net "AndNandOut", 0 0, L_0x2ae76f0; 1 drivers
+v0x282daf0_0 .net "B", 0 0, L_0x2ae70e0; 1 drivers
+v0x282db70_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae78c0 .part v0x2960210_0, 0, 1;
+S_0x282d2d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282d1e0;
+ .timescale -9 -12;
+L_0x2ae73d0/d .functor NOT 1, L_0x2ae78c0, C4<0>, C4<0>, C4<0>;
+L_0x2ae73d0 .delay (10000,10000,10000) L_0x2ae73d0/d;
+L_0x2ae7490/d .functor AND 1, L_0x2ae72a0, L_0x2ae73d0, C4<1>, C4<1>;
+L_0x2ae7490 .delay (20000,20000,20000) L_0x2ae7490/d;
+L_0x2ae75a0/d .functor AND 1, L_0x2ae6620, L_0x2ae78c0, C4<1>, C4<1>;
+L_0x2ae75a0 .delay (20000,20000,20000) L_0x2ae75a0/d;
+L_0x2ae76f0/d .functor OR 1, L_0x2ae7490, L_0x2ae75a0, C4<0>, C4<0>;
+L_0x2ae76f0 .delay (20000,20000,20000) L_0x2ae76f0/d;
+v0x282d3c0_0 .net "S", 0 0, L_0x2ae78c0; 1 drivers
+v0x282d440_0 .alias "in0", 0 0, v0x282d8e0_0;
+v0x282d4e0_0 .alias "in1", 0 0, v0x282d960_0;
+v0x282d580_0 .net "nS", 0 0, L_0x2ae73d0; 1 drivers
+v0x282d600_0 .net "out0", 0 0, L_0x2ae7490; 1 drivers
+v0x282d6a0_0 .net "out1", 0 0, L_0x2ae75a0; 1 drivers
+v0x282d780_0 .alias "outfinal", 0 0, v0x282da10_0;
+S_0x282c4b0 .scope generate, "andbits[27]" "andbits[27]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282c5a8 .param/l "i" 3 231, +C4<011011>;
+S_0x282c620 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282c4b0;
+ .timescale -9 -12;
+L_0x2ae71d0/d .functor NAND 1, L_0x2ae8470, L_0x2ae7a00, C4<1>, C4<1>;
+L_0x2ae71d0 .delay (10000,10000,10000) L_0x2ae71d0/d;
+L_0x2ae7d10/d .functor NOT 1, L_0x2ae71d0, C4<0>, C4<0>, C4<0>;
+L_0x2ae7d10 .delay (10000,10000,10000) L_0x2ae7d10/d;
+v0x282cc60_0 .net "A", 0 0, L_0x2ae8470; 1 drivers
+v0x282cd20_0 .net "AandB", 0 0, L_0x2ae7d10; 1 drivers
+v0x282cda0_0 .net "AnandB", 0 0, L_0x2ae71d0; 1 drivers
+v0x282ce50_0 .net "AndNandOut", 0 0, L_0x2ae8160; 1 drivers
+v0x282cf30_0 .net "B", 0 0, L_0x2ae7a00; 1 drivers
+v0x282cfb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae8330 .part v0x2960210_0, 0, 1;
+S_0x282c710 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282c620;
+ .timescale -9 -12;
+L_0x2ae7e40/d .functor NOT 1, L_0x2ae8330, C4<0>, C4<0>, C4<0>;
+L_0x2ae7e40 .delay (10000,10000,10000) L_0x2ae7e40/d;
+L_0x2ae7f00/d .functor AND 1, L_0x2ae7d10, L_0x2ae7e40, C4<1>, C4<1>;
+L_0x2ae7f00 .delay (20000,20000,20000) L_0x2ae7f00/d;
+L_0x2ae8010/d .functor AND 1, L_0x2ae71d0, L_0x2ae8330, C4<1>, C4<1>;
+L_0x2ae8010 .delay (20000,20000,20000) L_0x2ae8010/d;
+L_0x2ae8160/d .functor OR 1, L_0x2ae7f00, L_0x2ae8010, C4<0>, C4<0>;
+L_0x2ae8160 .delay (20000,20000,20000) L_0x2ae8160/d;
+v0x282c800_0 .net "S", 0 0, L_0x2ae8330; 1 drivers
+v0x282c880_0 .alias "in0", 0 0, v0x282cd20_0;
+v0x282c920_0 .alias "in1", 0 0, v0x282cda0_0;
+v0x282c9c0_0 .net "nS", 0 0, L_0x2ae7e40; 1 drivers
+v0x282ca40_0 .net "out0", 0 0, L_0x2ae7f00; 1 drivers
+v0x282cae0_0 .net "out1", 0 0, L_0x2ae8010; 1 drivers
+v0x282cbc0_0 .alias "outfinal", 0 0, v0x282ce50_0;
+S_0x282b8f0 .scope generate, "andbits[28]" "andbits[28]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282b9e8 .param/l "i" 3 231, +C4<011100>;
+S_0x282ba60 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282b8f0;
+ .timescale -9 -12;
+L_0x2ae7af0/d .functor NAND 1, L_0x2ae8510, L_0x2ae85b0, C4<1>, C4<1>;
+L_0x2ae7af0 .delay (10000,10000,10000) L_0x2ae7af0/d;
+L_0x2ae87a0/d .functor NOT 1, L_0x2ae7af0, C4<0>, C4<0>, C4<0>;
+L_0x2ae87a0 .delay (10000,10000,10000) L_0x2ae87a0/d;
+v0x282c0a0_0 .net "A", 0 0, L_0x2ae8510; 1 drivers
+v0x282c160_0 .net "AandB", 0 0, L_0x2ae87a0; 1 drivers
+v0x282c1e0_0 .net "AnandB", 0 0, L_0x2ae7af0; 1 drivers
+v0x282c290_0 .net "AndNandOut", 0 0, L_0x2ae8bd0; 1 drivers
+v0x282c370_0 .net "B", 0 0, L_0x2ae85b0; 1 drivers
+v0x282c3f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae8da0 .part v0x2960210_0, 0, 1;
+S_0x282bb50 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282ba60;
+ .timescale -9 -12;
+L_0x2ae88b0/d .functor NOT 1, L_0x2ae8da0, C4<0>, C4<0>, C4<0>;
+L_0x2ae88b0 .delay (10000,10000,10000) L_0x2ae88b0/d;
+L_0x2ae8970/d .functor AND 1, L_0x2ae87a0, L_0x2ae88b0, C4<1>, C4<1>;
+L_0x2ae8970 .delay (20000,20000,20000) L_0x2ae8970/d;
+L_0x2ae8a80/d .functor AND 1, L_0x2ae7af0, L_0x2ae8da0, C4<1>, C4<1>;
+L_0x2ae8a80 .delay (20000,20000,20000) L_0x2ae8a80/d;
+L_0x2ae8bd0/d .functor OR 1, L_0x2ae8970, L_0x2ae8a80, C4<0>, C4<0>;
+L_0x2ae8bd0 .delay (20000,20000,20000) L_0x2ae8bd0/d;
+v0x282bc40_0 .net "S", 0 0, L_0x2ae8da0; 1 drivers
+v0x282bcc0_0 .alias "in0", 0 0, v0x282c160_0;
+v0x282bd60_0 .alias "in1", 0 0, v0x282c1e0_0;
+v0x282be00_0 .net "nS", 0 0, L_0x2ae88b0; 1 drivers
+v0x282be80_0 .net "out0", 0 0, L_0x2ae8970; 1 drivers
+v0x282bf20_0 .net "out1", 0 0, L_0x2ae8a80; 1 drivers
+v0x282c000_0 .alias "outfinal", 0 0, v0x282c290_0;
+S_0x282ad30 .scope generate, "andbits[29]" "andbits[29]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282ae28 .param/l "i" 3 231, +C4<011101>;
+S_0x282aea0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282ad30;
+ .timescale -9 -12;
+L_0x2ae86a0/d .functor NAND 1, L_0x2ae9960, L_0x2ae8ee0, C4<1>, C4<1>;
+L_0x2ae86a0 .delay (10000,10000,10000) L_0x2ae86a0/d;
+L_0x2ae9220/d .functor NOT 1, L_0x2ae86a0, C4<0>, C4<0>, C4<0>;
+L_0x2ae9220 .delay (10000,10000,10000) L_0x2ae9220/d;
+v0x282b4e0_0 .net "A", 0 0, L_0x2ae9960; 1 drivers
+v0x282b5a0_0 .net "AandB", 0 0, L_0x2ae9220; 1 drivers
+v0x282b620_0 .net "AnandB", 0 0, L_0x2ae86a0; 1 drivers
+v0x282b6d0_0 .net "AndNandOut", 0 0, L_0x2ae9650; 1 drivers
+v0x282b7b0_0 .net "B", 0 0, L_0x2ae8ee0; 1 drivers
+v0x282b830_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2ae9820 .part v0x2960210_0, 0, 1;
+S_0x282af90 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282aea0;
+ .timescale -9 -12;
+L_0x2ae9330/d .functor NOT 1, L_0x2ae9820, C4<0>, C4<0>, C4<0>;
+L_0x2ae9330 .delay (10000,10000,10000) L_0x2ae9330/d;
+L_0x2ae93f0/d .functor AND 1, L_0x2ae9220, L_0x2ae9330, C4<1>, C4<1>;
+L_0x2ae93f0 .delay (20000,20000,20000) L_0x2ae93f0/d;
+L_0x2ae9500/d .functor AND 1, L_0x2ae86a0, L_0x2ae9820, C4<1>, C4<1>;
+L_0x2ae9500 .delay (20000,20000,20000) L_0x2ae9500/d;
+L_0x2ae9650/d .functor OR 1, L_0x2ae93f0, L_0x2ae9500, C4<0>, C4<0>;
+L_0x2ae9650 .delay (20000,20000,20000) L_0x2ae9650/d;
+v0x282b080_0 .net "S", 0 0, L_0x2ae9820; 1 drivers
+v0x282b100_0 .alias "in0", 0 0, v0x282b5a0_0;
+v0x282b1a0_0 .alias "in1", 0 0, v0x282b620_0;
+v0x282b240_0 .net "nS", 0 0, L_0x2ae9330; 1 drivers
+v0x282b2c0_0 .net "out0", 0 0, L_0x2ae93f0; 1 drivers
+v0x282b360_0 .net "out1", 0 0, L_0x2ae9500; 1 drivers
+v0x282b440_0 .alias "outfinal", 0 0, v0x282b6d0_0;
+S_0x282a170 .scope generate, "andbits[30]" "andbits[30]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x282a268 .param/l "i" 3 231, +C4<011110>;
+S_0x282a2e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x282a170;
+ .timescale -9 -12;
+L_0x2ae8fd0/d .functor NAND 1, L_0x2ae9a00, L_0x2ae9aa0, C4<1>, C4<1>;
+L_0x2ae8fd0 .delay (10000,10000,10000) L_0x2ae8fd0/d;
+L_0x2ae9130/d .functor NOT 1, L_0x2ae8fd0, C4<0>, C4<0>, C4<0>;
+L_0x2ae9130 .delay (10000,10000,10000) L_0x2ae9130/d;
+v0x282a920_0 .net "A", 0 0, L_0x2ae9a00; 1 drivers
+v0x282a9e0_0 .net "AandB", 0 0, L_0x2ae9130; 1 drivers
+v0x282aa60_0 .net "AnandB", 0 0, L_0x2ae8fd0; 1 drivers
+v0x282ab10_0 .net "AndNandOut", 0 0, L_0x2aea0b0; 1 drivers
+v0x282abf0_0 .net "B", 0 0, L_0x2ae9aa0; 1 drivers
+v0x282ac70_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2aea280 .part v0x2960210_0, 0, 1;
+S_0x282a3d0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x282a2e0;
+ .timescale -9 -12;
+L_0x2ae9d90/d .functor NOT 1, L_0x2aea280, C4<0>, C4<0>, C4<0>;
+L_0x2ae9d90 .delay (10000,10000,10000) L_0x2ae9d90/d;
+L_0x2ae9e50/d .functor AND 1, L_0x2ae9130, L_0x2ae9d90, C4<1>, C4<1>;
+L_0x2ae9e50 .delay (20000,20000,20000) L_0x2ae9e50/d;
+L_0x2ae9f60/d .functor AND 1, L_0x2ae8fd0, L_0x2aea280, C4<1>, C4<1>;
+L_0x2ae9f60 .delay (20000,20000,20000) L_0x2ae9f60/d;
+L_0x2aea0b0/d .functor OR 1, L_0x2ae9e50, L_0x2ae9f60, C4<0>, C4<0>;
+L_0x2aea0b0 .delay (20000,20000,20000) L_0x2aea0b0/d;
+v0x282a4c0_0 .net "S", 0 0, L_0x2aea280; 1 drivers
+v0x282a540_0 .alias "in0", 0 0, v0x282a9e0_0;
+v0x282a5e0_0 .alias "in1", 0 0, v0x282aa60_0;
+v0x282a680_0 .net "nS", 0 0, L_0x2ae9d90; 1 drivers
+v0x282a700_0 .net "out0", 0 0, L_0x2ae9e50; 1 drivers
+v0x282a7a0_0 .net "out1", 0 0, L_0x2ae9f60; 1 drivers
+v0x282a880_0 .alias "outfinal", 0 0, v0x282ab10_0;
+S_0x2829550 .scope generate, "andbits[31]" "andbits[31]" 3 231, 3 231, S_0x28293f0;
+ .timescale -9 -12;
+P_0x2829648 .param/l "i" 3 231, +C4<011111>;
+S_0x2829700 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2829550;
+ .timescale -9 -12;
+L_0x2ae9b90/d .functor NAND 1, L_0x2a37f60, L_0x2aea3c0, C4<1>, C4<1>;
+L_0x2ae9b90 .delay (10000,10000,10000) L_0x2ae9b90/d;
+L_0x2aea6f0/d .functor NOT 1, L_0x2ae9b90, C4<0>, C4<0>, C4<0>;
+L_0x2aea6f0 .delay (10000,10000,10000) L_0x2aea6f0/d;
+v0x2829d60_0 .net "A", 0 0, L_0x2a37f60; 1 drivers
+v0x2829e20_0 .net "AandB", 0 0, L_0x2aea6f0; 1 drivers
+v0x2829ea0_0 .net "AnandB", 0 0, L_0x2ae9b90; 1 drivers
+v0x2829f50_0 .net "AndNandOut", 0 0, L_0x2aeab20; 1 drivers
+v0x282a030_0 .net "B", 0 0, L_0x2aea3c0; 1 drivers
+v0x282a0b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2aeacf0 .part v0x2960210_0, 0, 1;
+S_0x28297f0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2829700;
+ .timescale -9 -12;
+L_0x2aea800/d .functor NOT 1, L_0x2aeacf0, C4<0>, C4<0>, C4<0>;
+L_0x2aea800 .delay (10000,10000,10000) L_0x2aea800/d;
+L_0x2aea8c0/d .functor AND 1, L_0x2aea6f0, L_0x2aea800, C4<1>, C4<1>;
+L_0x2aea8c0 .delay (20000,20000,20000) L_0x2aea8c0/d;
+L_0x2aea9d0/d .functor AND 1, L_0x2ae9b90, L_0x2aeacf0, C4<1>, C4<1>;
+L_0x2aea9d0 .delay (20000,20000,20000) L_0x2aea9d0/d;
+L_0x2aeab20/d .functor OR 1, L_0x2aea8c0, L_0x2aea9d0, C4<0>, C4<0>;
+L_0x2aeab20 .delay (20000,20000,20000) L_0x2aeab20/d;
+v0x28298e0_0 .net "S", 0 0, L_0x2aeacf0; 1 drivers
+v0x2829980_0 .alias "in0", 0 0, v0x2829e20_0;
+v0x2829a20_0 .alias "in1", 0 0, v0x2829ea0_0;
+v0x2829ac0_0 .net "nS", 0 0, L_0x2aea800; 1 drivers
+v0x2829b40_0 .net "out0", 0 0, L_0x2aea8c0; 1 drivers
+v0x2829be0_0 .net "out1", 0 0, L_0x2aea9d0; 1 drivers
+v0x2829cc0_0 .alias "outfinal", 0 0, v0x2829f50_0;
+S_0x2801850 .scope module, "trial2" "OrNorXor32" 3 388, 3 239, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x28009a8 .param/l "size" 3 246, +C4<0100000>;
+v0x28291f0_0 .alias "A", 31 0, v0x295f580_0;
+v0x2829270_0 .alias "B", 31 0, v0x295f6a0_0;
+v0x28292f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2829370_0 .alias "OrNorXorOut", 31 0, v0x29603c0_0;
+L_0x2aed1f0 .part/pv L_0x2aecfc0, 1, 1, 32;
+L_0x2aed290 .part v0x295fe90_0, 1, 1;
+L_0x2aed330 .part v0x2960190_0, 1, 1;
+L_0x2aee2f0 .part/pv L_0x2aee0c0, 2, 1, 32;
+L_0x2aee390 .part v0x295fe90_0, 2, 1;
+L_0x2aee430 .part v0x2960190_0, 2, 1;
+L_0x2aef450 .part/pv L_0x2aef200, 3, 1, 32;
+L_0x2aef4f0 .part v0x295fe90_0, 3, 1;
+L_0x2aef590 .part v0x2960190_0, 3, 1;
+L_0x2af0740 .part/pv L_0x2af04d0, 4, 1, 32;
+L_0x2af0840 .part v0x295fe90_0, 4, 1;
+L_0x2af08e0 .part v0x2960190_0, 4, 1;
+L_0x2af1a40 .part/pv L_0x2af17d0, 5, 1, 32;
+L_0x2af1ae0 .part v0x295fe90_0, 5, 1;
+L_0x2af1c00 .part v0x2960190_0, 5, 1;
+L_0x2af2da0 .part/pv L_0x2af2b30, 6, 1, 32;
+L_0x2af2ed0 .part v0x295fe90_0, 6, 1;
+L_0x2af2f70 .part v0x2960190_0, 6, 1;
+L_0x2af4130 .part/pv L_0x2af3ec0, 7, 1, 32;
+L_0x2af41d0 .part v0x295fe90_0, 7, 1;
+L_0x2af3010 .part v0x2960190_0, 7, 1;
+L_0x2af5420 .part/pv L_0x2af51b0, 8, 1, 32;
+L_0x2af4270 .part v0x295fe90_0, 8, 1;
+L_0x2af5580 .part v0x2960190_0, 8, 1;
+L_0x2af6730 .part/pv L_0x2af64c0, 9, 1, 32;
+L_0x2af67d0 .part v0x295fe90_0, 9, 1;
+L_0x2af5620 .part v0x2960190_0, 9, 1;
+L_0x2af7a30 .part/pv L_0x2af77c0, 10, 1, 32;
+L_0x2af6870 .part v0x295fe90_0, 10, 1;
+L_0x2af7bc0 .part v0x2960190_0, 10, 1;
+L_0x2af8d30 .part/pv L_0x2af8ac0, 11, 1, 32;
+L_0x2af8dd0 .part v0x295fe90_0, 11, 1;
+L_0x2af7c60 .part v0x2960190_0, 11, 1;
+L_0x2afa020 .part/pv L_0x2af9db0, 12, 1, 32;
+L_0x2af8e70 .part v0x295fe90_0, 12, 1;
+L_0x2afa1e0 .part v0x2960190_0, 12, 1;
+L_0x2afb340 .part/pv L_0x2afb0d0, 13, 1, 32;
+L_0x2afb3e0 .part v0x295fe90_0, 13, 1;
+L_0x2afa280 .part v0x2960190_0, 13, 1;
+L_0x2afc640 .part/pv L_0x2afc3d0, 14, 1, 32;
+L_0x2afb480 .part v0x295fe90_0, 14, 1;
+L_0x2afb520 .part v0x2960190_0, 14, 1;
+L_0x2afd940 .part/pv L_0x2afd6d0, 15, 1, 32;
+L_0x2afd9e0 .part v0x295fe90_0, 15, 1;
+L_0x2afc6e0 .part v0x2960190_0, 15, 1;
+L_0x2afea20 .part/pv L_0x2afe7f0, 16, 1, 32;
+L_0x2afda80 .part v0x295fe90_0, 16, 1;
+L_0x2afdb20 .part v0x2960190_0, 16, 1;
+L_0x2affc30 .part/pv L_0x2aff9c0, 17, 1, 32;
+L_0x2affcd0 .part v0x295fe90_0, 17, 1;
+L_0x2afeac0 .part v0x2960190_0, 17, 1;
+L_0x2b00f20 .part/pv L_0x2b00cb0, 18, 1, 32;
+L_0x2affd70 .part v0x295fe90_0, 18, 1;
+L_0x2affe10 .part v0x2960190_0, 18, 1;
+L_0x2a011b0 .part/pv L_0x2a00f40, 19, 1, 32;
+L_0x2a01250 .part v0x295fe90_0, 19, 1;
+L_0x2a00140 .part v0x2960190_0, 19, 1;
+L_0x2b054d0 .part/pv L_0x2b05280, 20, 1, 32;
+L_0x2a012f0 .part v0x295fe90_0, 20, 1;
+L_0x2a01390 .part v0x2960190_0, 20, 1;
+L_0x2b067e0 .part/pv L_0x2b06570, 21, 1, 32;
+L_0x2b06880 .part v0x295fe90_0, 21, 1;
+L_0x2b05570 .part v0x2960190_0, 21, 1;
+L_0x2b07ad0 .part/pv L_0x2b07860, 22, 1, 32;
+L_0x2b06920 .part v0x295fe90_0, 22, 1;
+L_0x2b069c0 .part v0x2960190_0, 22, 1;
+L_0x2b08dd0 .part/pv L_0x2b08b60, 23, 1, 32;
+L_0x2b08e70 .part v0x295fe90_0, 23, 1;
+L_0x2b07b70 .part v0x2960190_0, 23, 1;
+L_0x2b0a0d0 .part/pv L_0x2b09e60, 24, 1, 32;
+L_0x2b08f10 .part v0x295fe90_0, 24, 1;
+L_0x2b08fb0 .part v0x2960190_0, 24, 1;
+L_0x2b0b3d0 .part/pv L_0x2b0b160, 25, 1, 32;
+L_0x2b0b470 .part v0x295fe90_0, 25, 1;
+L_0x2b0a170 .part v0x2960190_0, 25, 1;
+L_0x2b0c6c0 .part/pv L_0x2b0c450, 26, 1, 32;
+L_0x2b0b510 .part v0x295fe90_0, 26, 1;
+L_0x2b0b5b0 .part v0x2960190_0, 26, 1;
+L_0x2b0d9f0 .part/pv L_0x2b0d780, 27, 1, 32;
+L_0x2b0da90 .part v0x295fe90_0, 27, 1;
+L_0x2b0c760 .part v0x2960190_0, 27, 1;
+L_0x2b0ecf0 .part/pv L_0x2b0ea80, 28, 1, 32;
+L_0x2b0db30 .part v0x295fe90_0, 28, 1;
+L_0x2b0dbd0 .part v0x2960190_0, 28, 1;
+L_0x2b0fff0 .part/pv L_0x2b0fd80, 29, 1, 32;
+L_0x2b10090 .part v0x295fe90_0, 29, 1;
+L_0x2b0ed90 .part v0x2960190_0, 29, 1;
+L_0x2b112e0 .part/pv L_0x2b11070, 30, 1, 32;
+L_0x2b10130 .part v0x295fe90_0, 30, 1;
+L_0x2b101d0 .part v0x2960190_0, 30, 1;
+L_0x2b125f0 .part/pv L_0x2b12380, 31, 1, 32;
+L_0x2b12690 .part v0x295fe90_0, 31, 1;
+L_0x2b11380 .part v0x2960190_0, 31, 1;
+L_0x2b13900 .part/pv L_0x2b13690, 0, 1, 32;
+L_0x2b12730 .part v0x295fe90_0, 0, 1;
+L_0x2b127d0 .part v0x2960190_0, 0, 1;
+S_0x2827fc0 .scope module, "attempt2" "OrNorXor" 3 254, 3 165, S_0x2801850;
+ .timescale -9 -12;
+L_0x2b11420/d .functor NOR 1, L_0x2b12730, L_0x2b127d0, C4<0>, C4<0>;
+L_0x2b11420 .delay (10000,10000,10000) L_0x2b11420/d;
+L_0x2b11510/d .functor NOT 1, L_0x2b11420, C4<0>, C4<0>, C4<0>;
+L_0x2b11510 .delay (10000,10000,10000) L_0x2b11510/d;
+L_0x2b12a20/d .functor NAND 1, L_0x2b12730, L_0x2b127d0, C4<1>, C4<1>;
+L_0x2b12a20 .delay (10000,10000,10000) L_0x2b12a20/d;
+L_0x2b12b60/d .functor NAND 1, L_0x2b12a20, L_0x2b11510, C4<1>, C4<1>;
+L_0x2b12b60 .delay (10000,10000,10000) L_0x2b12b60/d;
+L_0x2b12c70/d .functor NOT 1, L_0x2b12b60, C4<0>, C4<0>, C4<0>;
+L_0x2b12c70 .delay (10000,10000,10000) L_0x2b12c70/d;
+v0x2828ae0_0 .net "A", 0 0, L_0x2b12730; 1 drivers
+v0x2828b80_0 .net "AnandB", 0 0, L_0x2b12a20; 1 drivers
+v0x2828c20_0 .net "AnorB", 0 0, L_0x2b11420; 1 drivers
+v0x2828cd0_0 .net "AorB", 0 0, L_0x2b11510; 1 drivers
+v0x2828db0_0 .net "AxorB", 0 0, L_0x2b12c70; 1 drivers
+v0x2828e30_0 .net "B", 0 0, L_0x2b127d0; 1 drivers
+v0x2828ef0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2828f70_0 .net "OrNorXorOut", 0 0, L_0x2b13690; 1 drivers
+v0x2829040_0 .net "XorNor", 0 0, L_0x2b130f0; 1 drivers
+v0x2829110_0 .net "nXor", 0 0, L_0x2b12b60; 1 drivers
+L_0x2b13270 .part v0x2960210_0, 2, 1;
+L_0x2b13860 .part v0x2960210_0, 0, 1;
+S_0x2828540 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2827fc0;
+ .timescale -9 -12;
+L_0x2b12dd0/d .functor NOT 1, L_0x2b13270, C4<0>, C4<0>, C4<0>;
+L_0x2b12dd0 .delay (10000,10000,10000) L_0x2b12dd0/d;
+L_0x2b12e90/d .functor AND 1, L_0x2b12c70, L_0x2b12dd0, C4<1>, C4<1>;
+L_0x2b12e90 .delay (20000,20000,20000) L_0x2b12e90/d;
+L_0x2b12fa0/d .functor AND 1, L_0x2b11420, L_0x2b13270, C4<1>, C4<1>;
+L_0x2b12fa0 .delay (20000,20000,20000) L_0x2b12fa0/d;
+L_0x2b130f0/d .functor OR 1, L_0x2b12e90, L_0x2b12fa0, C4<0>, C4<0>;
+L_0x2b130f0 .delay (20000,20000,20000) L_0x2b130f0/d;
+v0x2828630_0 .net "S", 0 0, L_0x2b13270; 1 drivers
+v0x28286f0_0 .alias "in0", 0 0, v0x2828db0_0;
+v0x2828790_0 .alias "in1", 0 0, v0x2828c20_0;
+v0x2828830_0 .net "nS", 0 0, L_0x2b12dd0; 1 drivers
+v0x28288e0_0 .net "out0", 0 0, L_0x2b12e90; 1 drivers
+v0x2828980_0 .net "out1", 0 0, L_0x2b12fa0; 1 drivers
+v0x2828a60_0 .alias "outfinal", 0 0, v0x2829040_0;
+S_0x28280b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2827fc0;
+ .timescale -9 -12;
+L_0x2b13310/d .functor NOT 1, L_0x2b13860, C4<0>, C4<0>, C4<0>;
+L_0x2b13310 .delay (10000,10000,10000) L_0x2b13310/d;
+L_0x2b133d0/d .functor AND 1, L_0x2b130f0, L_0x2b13310, C4<1>, C4<1>;
+L_0x2b133d0 .delay (20000,20000,20000) L_0x2b133d0/d;
+L_0x2b13520/d .functor AND 1, L_0x2b11510, L_0x2b13860, C4<1>, C4<1>;
+L_0x2b13520 .delay (20000,20000,20000) L_0x2b13520/d;
+L_0x2b13690/d .functor OR 1, L_0x2b133d0, L_0x2b13520, C4<0>, C4<0>;
+L_0x2b13690 .delay (20000,20000,20000) L_0x2b13690/d;
+v0x28281a0_0 .net "S", 0 0, L_0x2b13860; 1 drivers
+v0x2828220_0 .alias "in0", 0 0, v0x2829040_0;
+v0x28282a0_0 .alias "in1", 0 0, v0x2828cd0_0;
+v0x2828320_0 .net "nS", 0 0, L_0x2b13310; 1 drivers
+v0x28283a0_0 .net "out0", 0 0, L_0x2b133d0; 1 drivers
+v0x2828420_0 .net "out1", 0 0, L_0x2b13520; 1 drivers
+v0x28284a0_0 .alias "outfinal", 0 0, v0x2828f70_0;
+S_0x2826bf0 .scope generate, "orbits[1]" "orbits[1]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2826908 .param/l "i" 3 258, +C4<01>;
+S_0x2826d20 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2826bf0;
+ .timescale -9 -12;
+L_0x2a38190/d .functor NOR 1, L_0x2aed290, L_0x2aed330, C4<0>, C4<0>;
+L_0x2a38190 .delay (10000,10000,10000) L_0x2a38190/d;
+L_0x2aec3c0/d .functor NOT 1, L_0x2a38190, C4<0>, C4<0>, C4<0>;
+L_0x2aec3c0 .delay (10000,10000,10000) L_0x2aec3c0/d;
+L_0x2aec4b0/d .functor NAND 1, L_0x2aed290, L_0x2aed330, C4<1>, C4<1>;
+L_0x2aec4b0 .delay (10000,10000,10000) L_0x2aec4b0/d;
+L_0x2aec5f0/d .functor NAND 1, L_0x2aec4b0, L_0x2aec3c0, C4<1>, C4<1>;
+L_0x2aec5f0 .delay (10000,10000,10000) L_0x2aec5f0/d;
+L_0x2aec6e0/d .functor NOT 1, L_0x2aec5f0, C4<0>, C4<0>, C4<0>;
+L_0x2aec6e0 .delay (10000,10000,10000) L_0x2aec6e0/d;
+v0x28278d0_0 .net "A", 0 0, L_0x2aed290; 1 drivers
+v0x2827970_0 .net "AnandB", 0 0, L_0x2aec4b0; 1 drivers
+v0x2827a10_0 .net "AnorB", 0 0, L_0x2a38190; 1 drivers
+v0x2827ac0_0 .net "AorB", 0 0, L_0x2aec3c0; 1 drivers
+v0x2827ba0_0 .net "AxorB", 0 0, L_0x2aec6e0; 1 drivers
+v0x2827c50_0 .net "B", 0 0, L_0x2aed330; 1 drivers
+v0x2827d10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2827d90_0 .net "OrNorXorOut", 0 0, L_0x2aecfc0; 1 drivers
+v0x2827e10_0 .net "XorNor", 0 0, L_0x2aecae0; 1 drivers
+v0x2827ee0_0 .net "nXor", 0 0, L_0x2aec5f0; 1 drivers
+L_0x2aecc20 .part v0x2960210_0, 2, 1;
+L_0x2aed150 .part v0x2960210_0, 0, 1;
+S_0x2827360 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2826d20;
+ .timescale -9 -12;
+L_0x2aec820/d .functor NOT 1, L_0x2aecc20, C4<0>, C4<0>, C4<0>;
+L_0x2aec820 .delay (10000,10000,10000) L_0x2aec820/d;
+L_0x2aec8c0/d .functor AND 1, L_0x2aec6e0, L_0x2aec820, C4<1>, C4<1>;
+L_0x2aec8c0 .delay (20000,20000,20000) L_0x2aec8c0/d;
+L_0x2aec9b0/d .functor AND 1, L_0x2a38190, L_0x2aecc20, C4<1>, C4<1>;
+L_0x2aec9b0 .delay (20000,20000,20000) L_0x2aec9b0/d;
+L_0x2aecae0/d .functor OR 1, L_0x2aec8c0, L_0x2aec9b0, C4<0>, C4<0>;
+L_0x2aecae0 .delay (20000,20000,20000) L_0x2aecae0/d;
+v0x2827450_0 .net "S", 0 0, L_0x2aecc20; 1 drivers
+v0x2827510_0 .alias "in0", 0 0, v0x2827ba0_0;
+v0x28275b0_0 .alias "in1", 0 0, v0x2827a10_0;
+v0x2827650_0 .net "nS", 0 0, L_0x2aec820; 1 drivers
+v0x28276d0_0 .net "out0", 0 0, L_0x2aec8c0; 1 drivers
+v0x2827770_0 .net "out1", 0 0, L_0x2aec9b0; 1 drivers
+v0x2827850_0 .alias "outfinal", 0 0, v0x2827e10_0;
+S_0x2826e10 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2826d20;
+ .timescale -9 -12;
+L_0x2aeccc0/d .functor NOT 1, L_0x2aed150, C4<0>, C4<0>, C4<0>;
+L_0x2aeccc0 .delay (10000,10000,10000) L_0x2aeccc0/d;
+L_0x2aecd60/d .functor AND 1, L_0x2aecae0, L_0x2aeccc0, C4<1>, C4<1>;
+L_0x2aecd60 .delay (20000,20000,20000) L_0x2aecd60/d;
+L_0x2aece90/d .functor AND 1, L_0x2aec3c0, L_0x2aed150, C4<1>, C4<1>;
+L_0x2aece90 .delay (20000,20000,20000) L_0x2aece90/d;
+L_0x2aecfc0/d .functor OR 1, L_0x2aecd60, L_0x2aece90, C4<0>, C4<0>;
+L_0x2aecfc0 .delay (20000,20000,20000) L_0x2aecfc0/d;
+v0x2826f00_0 .net "S", 0 0, L_0x2aed150; 1 drivers
+v0x2826f80_0 .alias "in0", 0 0, v0x2827e10_0;
+v0x2827020_0 .alias "in1", 0 0, v0x2827ac0_0;
+v0x28270c0_0 .net "nS", 0 0, L_0x2aeccc0; 1 drivers
+v0x2827140_0 .net "out0", 0 0, L_0x2aecd60; 1 drivers
+v0x28271e0_0 .net "out1", 0 0, L_0x2aece90; 1 drivers
+v0x28272c0_0 .alias "outfinal", 0 0, v0x2827d90_0;
+S_0x2825820 .scope generate, "orbits[2]" "orbits[2]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2825538 .param/l "i" 3 258, +C4<010>;
+S_0x2825950 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2825820;
+ .timescale -9 -12;
+L_0x2aed3d0/d .functor NOR 1, L_0x2aee390, L_0x2aee430, C4<0>, C4<0>;
+L_0x2aed3d0 .delay (10000,10000,10000) L_0x2aed3d0/d;
+L_0x2aed4c0/d .functor NOT 1, L_0x2aed3d0, C4<0>, C4<0>, C4<0>;
+L_0x2aed4c0 .delay (10000,10000,10000) L_0x2aed4c0/d;
+L_0x2aed5b0/d .functor NAND 1, L_0x2aee390, L_0x2aee430, C4<1>, C4<1>;
+L_0x2aed5b0 .delay (10000,10000,10000) L_0x2aed5b0/d;
+L_0x2aed6f0/d .functor NAND 1, L_0x2aed5b0, L_0x2aed4c0, C4<1>, C4<1>;
+L_0x2aed6f0 .delay (10000,10000,10000) L_0x2aed6f0/d;
+L_0x2aed7e0/d .functor NOT 1, L_0x2aed6f0, C4<0>, C4<0>, C4<0>;
+L_0x2aed7e0 .delay (10000,10000,10000) L_0x2aed7e0/d;
+v0x2826500_0 .net "A", 0 0, L_0x2aee390; 1 drivers
+v0x28265a0_0 .net "AnandB", 0 0, L_0x2aed5b0; 1 drivers
+v0x2826640_0 .net "AnorB", 0 0, L_0x2aed3d0; 1 drivers
+v0x28266f0_0 .net "AorB", 0 0, L_0x2aed4c0; 1 drivers
+v0x28267d0_0 .net "AxorB", 0 0, L_0x2aed7e0; 1 drivers
+v0x2826880_0 .net "B", 0 0, L_0x2aee430; 1 drivers
+v0x2826940_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28269c0_0 .net "OrNorXorOut", 0 0, L_0x2aee0c0; 1 drivers
+v0x2826a40_0 .net "XorNor", 0 0, L_0x2aedbe0; 1 drivers
+v0x2826b10_0 .net "nXor", 0 0, L_0x2aed6f0; 1 drivers
+L_0x2aedd20 .part v0x2960210_0, 2, 1;
+L_0x2aee250 .part v0x2960210_0, 0, 1;
+S_0x2825f90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2825950;
+ .timescale -9 -12;
+L_0x2aed920/d .functor NOT 1, L_0x2aedd20, C4<0>, C4<0>, C4<0>;
+L_0x2aed920 .delay (10000,10000,10000) L_0x2aed920/d;
+L_0x2aed9c0/d .functor AND 1, L_0x2aed7e0, L_0x2aed920, C4<1>, C4<1>;
+L_0x2aed9c0 .delay (20000,20000,20000) L_0x2aed9c0/d;
+L_0x2aedab0/d .functor AND 1, L_0x2aed3d0, L_0x2aedd20, C4<1>, C4<1>;
+L_0x2aedab0 .delay (20000,20000,20000) L_0x2aedab0/d;
+L_0x2aedbe0/d .functor OR 1, L_0x2aed9c0, L_0x2aedab0, C4<0>, C4<0>;
+L_0x2aedbe0 .delay (20000,20000,20000) L_0x2aedbe0/d;
+v0x2826080_0 .net "S", 0 0, L_0x2aedd20; 1 drivers
+v0x2826140_0 .alias "in0", 0 0, v0x28267d0_0;
+v0x28261e0_0 .alias "in1", 0 0, v0x2826640_0;
+v0x2826280_0 .net "nS", 0 0, L_0x2aed920; 1 drivers
+v0x2826300_0 .net "out0", 0 0, L_0x2aed9c0; 1 drivers
+v0x28263a0_0 .net "out1", 0 0, L_0x2aedab0; 1 drivers
+v0x2826480_0 .alias "outfinal", 0 0, v0x2826a40_0;
+S_0x2825a40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2825950;
+ .timescale -9 -12;
+L_0x2aeddc0/d .functor NOT 1, L_0x2aee250, C4<0>, C4<0>, C4<0>;
+L_0x2aeddc0 .delay (10000,10000,10000) L_0x2aeddc0/d;
+L_0x2aede60/d .functor AND 1, L_0x2aedbe0, L_0x2aeddc0, C4<1>, C4<1>;
+L_0x2aede60 .delay (20000,20000,20000) L_0x2aede60/d;
+L_0x2aedf90/d .functor AND 1, L_0x2aed4c0, L_0x2aee250, C4<1>, C4<1>;
+L_0x2aedf90 .delay (20000,20000,20000) L_0x2aedf90/d;
+L_0x2aee0c0/d .functor OR 1, L_0x2aede60, L_0x2aedf90, C4<0>, C4<0>;
+L_0x2aee0c0 .delay (20000,20000,20000) L_0x2aee0c0/d;
+v0x2825b30_0 .net "S", 0 0, L_0x2aee250; 1 drivers
+v0x2825bb0_0 .alias "in0", 0 0, v0x2826a40_0;
+v0x2825c50_0 .alias "in1", 0 0, v0x28266f0_0;
+v0x2825cf0_0 .net "nS", 0 0, L_0x2aeddc0; 1 drivers
+v0x2825d70_0 .net "out0", 0 0, L_0x2aede60; 1 drivers
+v0x2825e10_0 .net "out1", 0 0, L_0x2aedf90; 1 drivers
+v0x2825ef0_0 .alias "outfinal", 0 0, v0x28269c0_0;
+S_0x2824450 .scope generate, "orbits[3]" "orbits[3]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2824168 .param/l "i" 3 258, +C4<011>;
+S_0x2824580 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2824450;
+ .timescale -9 -12;
+L_0x2aee510/d .functor NOR 1, L_0x2aef4f0, L_0x2aef590, C4<0>, C4<0>;
+L_0x2aee510 .delay (10000,10000,10000) L_0x2aee510/d;
+L_0x2aee600/d .functor NOT 1, L_0x2aee510, C4<0>, C4<0>, C4<0>;
+L_0x2aee600 .delay (10000,10000,10000) L_0x2aee600/d;
+L_0x2aee6f0/d .functor NAND 1, L_0x2aef4f0, L_0x2aef590, C4<1>, C4<1>;
+L_0x2aee6f0 .delay (10000,10000,10000) L_0x2aee6f0/d;
+L_0x2aee830/d .functor NAND 1, L_0x2aee6f0, L_0x2aee600, C4<1>, C4<1>;
+L_0x2aee830 .delay (10000,10000,10000) L_0x2aee830/d;
+L_0x2aee920/d .functor NOT 1, L_0x2aee830, C4<0>, C4<0>, C4<0>;
+L_0x2aee920 .delay (10000,10000,10000) L_0x2aee920/d;
+v0x2825130_0 .net "A", 0 0, L_0x2aef4f0; 1 drivers
+v0x28251d0_0 .net "AnandB", 0 0, L_0x2aee6f0; 1 drivers
+v0x2825270_0 .net "AnorB", 0 0, L_0x2aee510; 1 drivers
+v0x2825320_0 .net "AorB", 0 0, L_0x2aee600; 1 drivers
+v0x2825400_0 .net "AxorB", 0 0, L_0x2aee920; 1 drivers
+v0x28254b0_0 .net "B", 0 0, L_0x2aef590; 1 drivers
+v0x2825570_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28255f0_0 .net "OrNorXorOut", 0 0, L_0x2aef200; 1 drivers
+v0x2825670_0 .net "XorNor", 0 0, L_0x2aeed20; 1 drivers
+v0x2825740_0 .net "nXor", 0 0, L_0x2aee830; 1 drivers
+L_0x2aeee60 .part v0x2960210_0, 2, 1;
+L_0x2aef3b0 .part v0x2960210_0, 0, 1;
+S_0x2824bc0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2824580;
+ .timescale -9 -12;
+L_0x2aeea60/d .functor NOT 1, L_0x2aeee60, C4<0>, C4<0>, C4<0>;
+L_0x2aeea60 .delay (10000,10000,10000) L_0x2aeea60/d;
+L_0x2aeeb00/d .functor AND 1, L_0x2aee920, L_0x2aeea60, C4<1>, C4<1>;
+L_0x2aeeb00 .delay (20000,20000,20000) L_0x2aeeb00/d;
+L_0x2aeebf0/d .functor AND 1, L_0x2aee510, L_0x2aeee60, C4<1>, C4<1>;
+L_0x2aeebf0 .delay (20000,20000,20000) L_0x2aeebf0/d;
+L_0x2aeed20/d .functor OR 1, L_0x2aeeb00, L_0x2aeebf0, C4<0>, C4<0>;
+L_0x2aeed20 .delay (20000,20000,20000) L_0x2aeed20/d;
+v0x2824cb0_0 .net "S", 0 0, L_0x2aeee60; 1 drivers
+v0x2824d70_0 .alias "in0", 0 0, v0x2825400_0;
+v0x2824e10_0 .alias "in1", 0 0, v0x2825270_0;
+v0x2824eb0_0 .net "nS", 0 0, L_0x2aeea60; 1 drivers
+v0x2824f30_0 .net "out0", 0 0, L_0x2aeeb00; 1 drivers
+v0x2824fd0_0 .net "out1", 0 0, L_0x2aeebf0; 1 drivers
+v0x28250b0_0 .alias "outfinal", 0 0, v0x2825670_0;
+S_0x2824670 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2824580;
+ .timescale -9 -12;
+L_0x2aeef00/d .functor NOT 1, L_0x2aef3b0, C4<0>, C4<0>, C4<0>;
+L_0x2aeef00 .delay (10000,10000,10000) L_0x2aeef00/d;
+L_0x2aeefa0/d .functor AND 1, L_0x2aeed20, L_0x2aeef00, C4<1>, C4<1>;
+L_0x2aeefa0 .delay (20000,20000,20000) L_0x2aeefa0/d;
+L_0x2aef0d0/d .functor AND 1, L_0x2aee600, L_0x2aef3b0, C4<1>, C4<1>;
+L_0x2aef0d0 .delay (20000,20000,20000) L_0x2aef0d0/d;
+L_0x2aef200/d .functor OR 1, L_0x2aeefa0, L_0x2aef0d0, C4<0>, C4<0>;
+L_0x2aef200 .delay (20000,20000,20000) L_0x2aef200/d;
+v0x2824760_0 .net "S", 0 0, L_0x2aef3b0; 1 drivers
+v0x28247e0_0 .alias "in0", 0 0, v0x2825670_0;
+v0x2824880_0 .alias "in1", 0 0, v0x2825320_0;
+v0x2824920_0 .net "nS", 0 0, L_0x2aeef00; 1 drivers
+v0x28249a0_0 .net "out0", 0 0, L_0x2aeefa0; 1 drivers
+v0x2824a40_0 .net "out1", 0 0, L_0x2aef0d0; 1 drivers
+v0x2824b20_0 .alias "outfinal", 0 0, v0x28255f0_0;
+S_0x2823080 .scope generate, "orbits[4]" "orbits[4]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2822d98 .param/l "i" 3 258, +C4<0100>;
+S_0x28231b0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2823080;
+ .timescale -9 -12;
+L_0x2aef630/d .functor NOR 1, L_0x2af0840, L_0x2af08e0, C4<0>, C4<0>;
+L_0x2aef630 .delay (10000,10000,10000) L_0x2aef630/d;
+L_0x2aef730/d .functor NOT 1, L_0x2aef630, C4<0>, C4<0>, C4<0>;
+L_0x2aef730 .delay (10000,10000,10000) L_0x2aef730/d;
+L_0x2aef860/d .functor NAND 1, L_0x2af0840, L_0x2af08e0, C4<1>, C4<1>;
+L_0x2aef860 .delay (10000,10000,10000) L_0x2aef860/d;
+L_0x2aef9c0/d .functor NAND 1, L_0x2aef860, L_0x2aef730, C4<1>, C4<1>;
+L_0x2aef9c0 .delay (10000,10000,10000) L_0x2aef9c0/d;
+L_0x2aefad0/d .functor NOT 1, L_0x2aef9c0, C4<0>, C4<0>, C4<0>;
+L_0x2aefad0 .delay (10000,10000,10000) L_0x2aefad0/d;
+v0x2823d60_0 .net "A", 0 0, L_0x2af0840; 1 drivers
+v0x2823e00_0 .net "AnandB", 0 0, L_0x2aef860; 1 drivers
+v0x2823ea0_0 .net "AnorB", 0 0, L_0x2aef630; 1 drivers
+v0x2823f50_0 .net "AorB", 0 0, L_0x2aef730; 1 drivers
+v0x2824030_0 .net "AxorB", 0 0, L_0x2aefad0; 1 drivers
+v0x28240e0_0 .net "B", 0 0, L_0x2af08e0; 1 drivers
+v0x28241a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2824220_0 .net "OrNorXorOut", 0 0, L_0x2af04d0; 1 drivers
+v0x28242a0_0 .net "XorNor", 0 0, L_0x2aeff50; 1 drivers
+v0x2824370_0 .net "nXor", 0 0, L_0x2aef9c0; 1 drivers
+L_0x2af00d0 .part v0x2960210_0, 2, 1;
+L_0x2af06a0 .part v0x2960210_0, 0, 1;
+S_0x28237f0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28231b0;
+ .timescale -9 -12;
+L_0x2aefc30/d .functor NOT 1, L_0x2af00d0, C4<0>, C4<0>, C4<0>;
+L_0x2aefc30 .delay (10000,10000,10000) L_0x2aefc30/d;
+L_0x2aefcf0/d .functor AND 1, L_0x2aefad0, L_0x2aefc30, C4<1>, C4<1>;
+L_0x2aefcf0 .delay (20000,20000,20000) L_0x2aefcf0/d;
+L_0x2aefe00/d .functor AND 1, L_0x2aef630, L_0x2af00d0, C4<1>, C4<1>;
+L_0x2aefe00 .delay (20000,20000,20000) L_0x2aefe00/d;
+L_0x2aeff50/d .functor OR 1, L_0x2aefcf0, L_0x2aefe00, C4<0>, C4<0>;
+L_0x2aeff50 .delay (20000,20000,20000) L_0x2aeff50/d;
+v0x28238e0_0 .net "S", 0 0, L_0x2af00d0; 1 drivers
+v0x28239a0_0 .alias "in0", 0 0, v0x2824030_0;
+v0x2823a40_0 .alias "in1", 0 0, v0x2823ea0_0;
+v0x2823ae0_0 .net "nS", 0 0, L_0x2aefc30; 1 drivers
+v0x2823b60_0 .net "out0", 0 0, L_0x2aefcf0; 1 drivers
+v0x2823c00_0 .net "out1", 0 0, L_0x2aefe00; 1 drivers
+v0x2823ce0_0 .alias "outfinal", 0 0, v0x28242a0_0;
+S_0x28232a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28231b0;
+ .timescale -9 -12;
+L_0x2af0170/d .functor NOT 1, L_0x2af06a0, C4<0>, C4<0>, C4<0>;
+L_0x2af0170 .delay (10000,10000,10000) L_0x2af0170/d;
+L_0x2af0230/d .functor AND 1, L_0x2aeff50, L_0x2af0170, C4<1>, C4<1>;
+L_0x2af0230 .delay (20000,20000,20000) L_0x2af0230/d;
+L_0x2af0380/d .functor AND 1, L_0x2aef730, L_0x2af06a0, C4<1>, C4<1>;
+L_0x2af0380 .delay (20000,20000,20000) L_0x2af0380/d;
+L_0x2af04d0/d .functor OR 1, L_0x2af0230, L_0x2af0380, C4<0>, C4<0>;
+L_0x2af04d0 .delay (20000,20000,20000) L_0x2af04d0/d;
+v0x2823390_0 .net "S", 0 0, L_0x2af06a0; 1 drivers
+v0x2823410_0 .alias "in0", 0 0, v0x28242a0_0;
+v0x28234b0_0 .alias "in1", 0 0, v0x2823f50_0;
+v0x2823550_0 .net "nS", 0 0, L_0x2af0170; 1 drivers
+v0x28235d0_0 .net "out0", 0 0, L_0x2af0230; 1 drivers
+v0x2823670_0 .net "out1", 0 0, L_0x2af0380; 1 drivers
+v0x2823750_0 .alias "outfinal", 0 0, v0x2824220_0;
+S_0x2821cb0 .scope generate, "orbits[5]" "orbits[5]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x28219c8 .param/l "i" 3 258, +C4<0101>;
+S_0x2821de0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2821cb0;
+ .timescale -9 -12;
+L_0x2af07e0/d .functor NOR 1, L_0x2af1ae0, L_0x2af1c00, C4<0>, C4<0>;
+L_0x2af07e0 .delay (10000,10000,10000) L_0x2af07e0/d;
+L_0x2af0a30/d .functor NOT 1, L_0x2af07e0, C4<0>, C4<0>, C4<0>;
+L_0x2af0a30 .delay (10000,10000,10000) L_0x2af0a30/d;
+L_0x2af0b60/d .functor NAND 1, L_0x2af1ae0, L_0x2af1c00, C4<1>, C4<1>;
+L_0x2af0b60 .delay (10000,10000,10000) L_0x2af0b60/d;
+L_0x2af0cc0/d .functor NAND 1, L_0x2af0b60, L_0x2af0a30, C4<1>, C4<1>;
+L_0x2af0cc0 .delay (10000,10000,10000) L_0x2af0cc0/d;
+L_0x2af0dd0/d .functor NOT 1, L_0x2af0cc0, C4<0>, C4<0>, C4<0>;
+L_0x2af0dd0 .delay (10000,10000,10000) L_0x2af0dd0/d;
+v0x2822990_0 .net "A", 0 0, L_0x2af1ae0; 1 drivers
+v0x2822a30_0 .net "AnandB", 0 0, L_0x2af0b60; 1 drivers
+v0x2822ad0_0 .net "AnorB", 0 0, L_0x2af07e0; 1 drivers
+v0x2822b80_0 .net "AorB", 0 0, L_0x2af0a30; 1 drivers
+v0x2822c60_0 .net "AxorB", 0 0, L_0x2af0dd0; 1 drivers
+v0x2822d10_0 .net "B", 0 0, L_0x2af1c00; 1 drivers
+v0x2822dd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2822e50_0 .net "OrNorXorOut", 0 0, L_0x2af17d0; 1 drivers
+v0x2822ed0_0 .net "XorNor", 0 0, L_0x2af1250; 1 drivers
+v0x2822fa0_0 .net "nXor", 0 0, L_0x2af0cc0; 1 drivers
+L_0x2af13d0 .part v0x2960210_0, 2, 1;
+L_0x2af19a0 .part v0x2960210_0, 0, 1;
+S_0x2822420 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2821de0;
+ .timescale -9 -12;
+L_0x2af0f30/d .functor NOT 1, L_0x2af13d0, C4<0>, C4<0>, C4<0>;
+L_0x2af0f30 .delay (10000,10000,10000) L_0x2af0f30/d;
+L_0x2af0ff0/d .functor AND 1, L_0x2af0dd0, L_0x2af0f30, C4<1>, C4<1>;
+L_0x2af0ff0 .delay (20000,20000,20000) L_0x2af0ff0/d;
+L_0x2af1100/d .functor AND 1, L_0x2af07e0, L_0x2af13d0, C4<1>, C4<1>;
+L_0x2af1100 .delay (20000,20000,20000) L_0x2af1100/d;
+L_0x2af1250/d .functor OR 1, L_0x2af0ff0, L_0x2af1100, C4<0>, C4<0>;
+L_0x2af1250 .delay (20000,20000,20000) L_0x2af1250/d;
+v0x2822510_0 .net "S", 0 0, L_0x2af13d0; 1 drivers
+v0x28225d0_0 .alias "in0", 0 0, v0x2822c60_0;
+v0x2822670_0 .alias "in1", 0 0, v0x2822ad0_0;
+v0x2822710_0 .net "nS", 0 0, L_0x2af0f30; 1 drivers
+v0x2822790_0 .net "out0", 0 0, L_0x2af0ff0; 1 drivers
+v0x2822830_0 .net "out1", 0 0, L_0x2af1100; 1 drivers
+v0x2822910_0 .alias "outfinal", 0 0, v0x2822ed0_0;
+S_0x2821ed0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2821de0;
+ .timescale -9 -12;
+L_0x2af1470/d .functor NOT 1, L_0x2af19a0, C4<0>, C4<0>, C4<0>;
+L_0x2af1470 .delay (10000,10000,10000) L_0x2af1470/d;
+L_0x2af1530/d .functor AND 1, L_0x2af1250, L_0x2af1470, C4<1>, C4<1>;
+L_0x2af1530 .delay (20000,20000,20000) L_0x2af1530/d;
+L_0x2af1680/d .functor AND 1, L_0x2af0a30, L_0x2af19a0, C4<1>, C4<1>;
+L_0x2af1680 .delay (20000,20000,20000) L_0x2af1680/d;
+L_0x2af17d0/d .functor OR 1, L_0x2af1530, L_0x2af1680, C4<0>, C4<0>;
+L_0x2af17d0 .delay (20000,20000,20000) L_0x2af17d0/d;
+v0x2821fc0_0 .net "S", 0 0, L_0x2af19a0; 1 drivers
+v0x2822040_0 .alias "in0", 0 0, v0x2822ed0_0;
+v0x28220e0_0 .alias "in1", 0 0, v0x2822b80_0;
+v0x2822180_0 .net "nS", 0 0, L_0x2af1470; 1 drivers
+v0x2822200_0 .net "out0", 0 0, L_0x2af1530; 1 drivers
+v0x28222a0_0 .net "out1", 0 0, L_0x2af1680; 1 drivers
+v0x2822380_0 .alias "outfinal", 0 0, v0x2822e50_0;
+S_0x28208e0 .scope generate, "orbits[6]" "orbits[6]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x28205f8 .param/l "i" 3 258, +C4<0110>;
+S_0x2820a10 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28208e0;
+ .timescale -9 -12;
+L_0x2af1ca0/d .functor NOR 1, L_0x2af2ed0, L_0x2af2f70, C4<0>, C4<0>;
+L_0x2af1ca0 .delay (10000,10000,10000) L_0x2af1ca0/d;
+L_0x2af1d90/d .functor NOT 1, L_0x2af1ca0, C4<0>, C4<0>, C4<0>;
+L_0x2af1d90 .delay (10000,10000,10000) L_0x2af1d90/d;
+L_0x2af1ec0/d .functor NAND 1, L_0x2af2ed0, L_0x2af2f70, C4<1>, C4<1>;
+L_0x2af1ec0 .delay (10000,10000,10000) L_0x2af1ec0/d;
+L_0x2af2020/d .functor NAND 1, L_0x2af1ec0, L_0x2af1d90, C4<1>, C4<1>;
+L_0x2af2020 .delay (10000,10000,10000) L_0x2af2020/d;
+L_0x2af2130/d .functor NOT 1, L_0x2af2020, C4<0>, C4<0>, C4<0>;
+L_0x2af2130 .delay (10000,10000,10000) L_0x2af2130/d;
+v0x28215c0_0 .net "A", 0 0, L_0x2af2ed0; 1 drivers
+v0x2821660_0 .net "AnandB", 0 0, L_0x2af1ec0; 1 drivers
+v0x2821700_0 .net "AnorB", 0 0, L_0x2af1ca0; 1 drivers
+v0x28217b0_0 .net "AorB", 0 0, L_0x2af1d90; 1 drivers
+v0x2821890_0 .net "AxorB", 0 0, L_0x2af2130; 1 drivers
+v0x2821940_0 .net "B", 0 0, L_0x2af2f70; 1 drivers
+v0x2821a00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2821a80_0 .net "OrNorXorOut", 0 0, L_0x2af2b30; 1 drivers
+v0x2821b00_0 .net "XorNor", 0 0, L_0x2af25b0; 1 drivers
+v0x2821bd0_0 .net "nXor", 0 0, L_0x2af2020; 1 drivers
+L_0x2af2730 .part v0x2960210_0, 2, 1;
+L_0x2af2d00 .part v0x2960210_0, 0, 1;
+S_0x2821050 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2820a10;
+ .timescale -9 -12;
+L_0x2af2290/d .functor NOT 1, L_0x2af2730, C4<0>, C4<0>, C4<0>;
+L_0x2af2290 .delay (10000,10000,10000) L_0x2af2290/d;
+L_0x2af2350/d .functor AND 1, L_0x2af2130, L_0x2af2290, C4<1>, C4<1>;
+L_0x2af2350 .delay (20000,20000,20000) L_0x2af2350/d;
+L_0x2af2460/d .functor AND 1, L_0x2af1ca0, L_0x2af2730, C4<1>, C4<1>;
+L_0x2af2460 .delay (20000,20000,20000) L_0x2af2460/d;
+L_0x2af25b0/d .functor OR 1, L_0x2af2350, L_0x2af2460, C4<0>, C4<0>;
+L_0x2af25b0 .delay (20000,20000,20000) L_0x2af25b0/d;
+v0x2821140_0 .net "S", 0 0, L_0x2af2730; 1 drivers
+v0x2821200_0 .alias "in0", 0 0, v0x2821890_0;
+v0x28212a0_0 .alias "in1", 0 0, v0x2821700_0;
+v0x2821340_0 .net "nS", 0 0, L_0x2af2290; 1 drivers
+v0x28213c0_0 .net "out0", 0 0, L_0x2af2350; 1 drivers
+v0x2821460_0 .net "out1", 0 0, L_0x2af2460; 1 drivers
+v0x2821540_0 .alias "outfinal", 0 0, v0x2821b00_0;
+S_0x2820b00 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2820a10;
+ .timescale -9 -12;
+L_0x2af27d0/d .functor NOT 1, L_0x2af2d00, C4<0>, C4<0>, C4<0>;
+L_0x2af27d0 .delay (10000,10000,10000) L_0x2af27d0/d;
+L_0x2af2890/d .functor AND 1, L_0x2af25b0, L_0x2af27d0, C4<1>, C4<1>;
+L_0x2af2890 .delay (20000,20000,20000) L_0x2af2890/d;
+L_0x2af29e0/d .functor AND 1, L_0x2af1d90, L_0x2af2d00, C4<1>, C4<1>;
+L_0x2af29e0 .delay (20000,20000,20000) L_0x2af29e0/d;
+L_0x2af2b30/d .functor OR 1, L_0x2af2890, L_0x2af29e0, C4<0>, C4<0>;
+L_0x2af2b30 .delay (20000,20000,20000) L_0x2af2b30/d;
+v0x2820bf0_0 .net "S", 0 0, L_0x2af2d00; 1 drivers
+v0x2820c70_0 .alias "in0", 0 0, v0x2821b00_0;
+v0x2820d10_0 .alias "in1", 0 0, v0x28217b0_0;
+v0x2820db0_0 .net "nS", 0 0, L_0x2af27d0; 1 drivers
+v0x2820e30_0 .net "out0", 0 0, L_0x2af2890; 1 drivers
+v0x2820ed0_0 .net "out1", 0 0, L_0x2af29e0; 1 drivers
+v0x2820fb0_0 .alias "outfinal", 0 0, v0x2821a80_0;
+S_0x281f510 .scope generate, "orbits[7]" "orbits[7]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x281f228 .param/l "i" 3 258, +C4<0111>;
+S_0x281f640 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281f510;
+ .timescale -9 -12;
+L_0x2af2e40/d .functor NOR 1, L_0x2af41d0, L_0x2af3010, C4<0>, C4<0>;
+L_0x2af2e40 .delay (10000,10000,10000) L_0x2af2e40/d;
+L_0x2af3140/d .functor NOT 1, L_0x2af2e40, C4<0>, C4<0>, C4<0>;
+L_0x2af3140 .delay (10000,10000,10000) L_0x2af3140/d;
+L_0x2af3250/d .functor NAND 1, L_0x2af41d0, L_0x2af3010, C4<1>, C4<1>;
+L_0x2af3250 .delay (10000,10000,10000) L_0x2af3250/d;
+L_0x2af33b0/d .functor NAND 1, L_0x2af3250, L_0x2af3140, C4<1>, C4<1>;
+L_0x2af33b0 .delay (10000,10000,10000) L_0x2af33b0/d;
+L_0x2af34c0/d .functor NOT 1, L_0x2af33b0, C4<0>, C4<0>, C4<0>;
+L_0x2af34c0 .delay (10000,10000,10000) L_0x2af34c0/d;
+v0x28201f0_0 .net "A", 0 0, L_0x2af41d0; 1 drivers
+v0x2820290_0 .net "AnandB", 0 0, L_0x2af3250; 1 drivers
+v0x2820330_0 .net "AnorB", 0 0, L_0x2af2e40; 1 drivers
+v0x28203e0_0 .net "AorB", 0 0, L_0x2af3140; 1 drivers
+v0x28204c0_0 .net "AxorB", 0 0, L_0x2af34c0; 1 drivers
+v0x2820570_0 .net "B", 0 0, L_0x2af3010; 1 drivers
+v0x2820630_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28206b0_0 .net "OrNorXorOut", 0 0, L_0x2af3ec0; 1 drivers
+v0x2820730_0 .net "XorNor", 0 0, L_0x2af3940; 1 drivers
+v0x2820800_0 .net "nXor", 0 0, L_0x2af33b0; 1 drivers
+L_0x2af3ac0 .part v0x2960210_0, 2, 1;
+L_0x2af4090 .part v0x2960210_0, 0, 1;
+S_0x281fc80 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281f640;
+ .timescale -9 -12;
+L_0x2af3620/d .functor NOT 1, L_0x2af3ac0, C4<0>, C4<0>, C4<0>;
+L_0x2af3620 .delay (10000,10000,10000) L_0x2af3620/d;
+L_0x2af36e0/d .functor AND 1, L_0x2af34c0, L_0x2af3620, C4<1>, C4<1>;
+L_0x2af36e0 .delay (20000,20000,20000) L_0x2af36e0/d;
+L_0x2af37f0/d .functor AND 1, L_0x2af2e40, L_0x2af3ac0, C4<1>, C4<1>;
+L_0x2af37f0 .delay (20000,20000,20000) L_0x2af37f0/d;
+L_0x2af3940/d .functor OR 1, L_0x2af36e0, L_0x2af37f0, C4<0>, C4<0>;
+L_0x2af3940 .delay (20000,20000,20000) L_0x2af3940/d;
+v0x281fd70_0 .net "S", 0 0, L_0x2af3ac0; 1 drivers
+v0x281fe30_0 .alias "in0", 0 0, v0x28204c0_0;
+v0x281fed0_0 .alias "in1", 0 0, v0x2820330_0;
+v0x281ff70_0 .net "nS", 0 0, L_0x2af3620; 1 drivers
+v0x281fff0_0 .net "out0", 0 0, L_0x2af36e0; 1 drivers
+v0x2820090_0 .net "out1", 0 0, L_0x2af37f0; 1 drivers
+v0x2820170_0 .alias "outfinal", 0 0, v0x2820730_0;
+S_0x281f730 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281f640;
+ .timescale -9 -12;
+L_0x2af3b60/d .functor NOT 1, L_0x2af4090, C4<0>, C4<0>, C4<0>;
+L_0x2af3b60 .delay (10000,10000,10000) L_0x2af3b60/d;
+L_0x2af3c20/d .functor AND 1, L_0x2af3940, L_0x2af3b60, C4<1>, C4<1>;
+L_0x2af3c20 .delay (20000,20000,20000) L_0x2af3c20/d;
+L_0x2af3d70/d .functor AND 1, L_0x2af3140, L_0x2af4090, C4<1>, C4<1>;
+L_0x2af3d70 .delay (20000,20000,20000) L_0x2af3d70/d;
+L_0x2af3ec0/d .functor OR 1, L_0x2af3c20, L_0x2af3d70, C4<0>, C4<0>;
+L_0x2af3ec0 .delay (20000,20000,20000) L_0x2af3ec0/d;
+v0x281f820_0 .net "S", 0 0, L_0x2af4090; 1 drivers
+v0x281f8a0_0 .alias "in0", 0 0, v0x2820730_0;
+v0x281f940_0 .alias "in1", 0 0, v0x28203e0_0;
+v0x281f9e0_0 .net "nS", 0 0, L_0x2af3b60; 1 drivers
+v0x281fa60_0 .net "out0", 0 0, L_0x2af3c20; 1 drivers
+v0x281fb00_0 .net "out1", 0 0, L_0x2af3d70; 1 drivers
+v0x281fbe0_0 .alias "outfinal", 0 0, v0x28206b0_0;
+S_0x281e140 .scope generate, "orbits[8]" "orbits[8]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x281de58 .param/l "i" 3 258, +C4<01000>;
+S_0x281e270 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281e140;
+ .timescale -9 -12;
+L_0x2af4320/d .functor NOR 1, L_0x2af4270, L_0x2af5580, C4<0>, C4<0>;
+L_0x2af4320 .delay (10000,10000,10000) L_0x2af4320/d;
+L_0x2af4410/d .functor NOT 1, L_0x2af4320, C4<0>, C4<0>, C4<0>;
+L_0x2af4410 .delay (10000,10000,10000) L_0x2af4410/d;
+L_0x2af4540/d .functor NAND 1, L_0x2af4270, L_0x2af5580, C4<1>, C4<1>;
+L_0x2af4540 .delay (10000,10000,10000) L_0x2af4540/d;
+L_0x2af46a0/d .functor NAND 1, L_0x2af4540, L_0x2af4410, C4<1>, C4<1>;
+L_0x2af46a0 .delay (10000,10000,10000) L_0x2af46a0/d;
+L_0x2af47b0/d .functor NOT 1, L_0x2af46a0, C4<0>, C4<0>, C4<0>;
+L_0x2af47b0 .delay (10000,10000,10000) L_0x2af47b0/d;
+v0x281ee20_0 .net "A", 0 0, L_0x2af4270; 1 drivers
+v0x281eec0_0 .net "AnandB", 0 0, L_0x2af4540; 1 drivers
+v0x281ef60_0 .net "AnorB", 0 0, L_0x2af4320; 1 drivers
+v0x281f010_0 .net "AorB", 0 0, L_0x2af4410; 1 drivers
+v0x281f0f0_0 .net "AxorB", 0 0, L_0x2af47b0; 1 drivers
+v0x281f1a0_0 .net "B", 0 0, L_0x2af5580; 1 drivers
+v0x281f260_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x281f2e0_0 .net "OrNorXorOut", 0 0, L_0x2af51b0; 1 drivers
+v0x281f360_0 .net "XorNor", 0 0, L_0x2af4c30; 1 drivers
+v0x281f430_0 .net "nXor", 0 0, L_0x2af46a0; 1 drivers
+L_0x2af4db0 .part v0x2960210_0, 2, 1;
+L_0x2af5380 .part v0x2960210_0, 0, 1;
+S_0x281e8b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281e270;
+ .timescale -9 -12;
+L_0x2af4910/d .functor NOT 1, L_0x2af4db0, C4<0>, C4<0>, C4<0>;
+L_0x2af4910 .delay (10000,10000,10000) L_0x2af4910/d;
+L_0x2af49d0/d .functor AND 1, L_0x2af47b0, L_0x2af4910, C4<1>, C4<1>;
+L_0x2af49d0 .delay (20000,20000,20000) L_0x2af49d0/d;
+L_0x2af4ae0/d .functor AND 1, L_0x2af4320, L_0x2af4db0, C4<1>, C4<1>;
+L_0x2af4ae0 .delay (20000,20000,20000) L_0x2af4ae0/d;
+L_0x2af4c30/d .functor OR 1, L_0x2af49d0, L_0x2af4ae0, C4<0>, C4<0>;
+L_0x2af4c30 .delay (20000,20000,20000) L_0x2af4c30/d;
+v0x281e9a0_0 .net "S", 0 0, L_0x2af4db0; 1 drivers
+v0x281ea60_0 .alias "in0", 0 0, v0x281f0f0_0;
+v0x281eb00_0 .alias "in1", 0 0, v0x281ef60_0;
+v0x281eba0_0 .net "nS", 0 0, L_0x2af4910; 1 drivers
+v0x281ec20_0 .net "out0", 0 0, L_0x2af49d0; 1 drivers
+v0x281ecc0_0 .net "out1", 0 0, L_0x2af4ae0; 1 drivers
+v0x281eda0_0 .alias "outfinal", 0 0, v0x281f360_0;
+S_0x281e360 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281e270;
+ .timescale -9 -12;
+L_0x2af4e50/d .functor NOT 1, L_0x2af5380, C4<0>, C4<0>, C4<0>;
+L_0x2af4e50 .delay (10000,10000,10000) L_0x2af4e50/d;
+L_0x2af4f10/d .functor AND 1, L_0x2af4c30, L_0x2af4e50, C4<1>, C4<1>;
+L_0x2af4f10 .delay (20000,20000,20000) L_0x2af4f10/d;
+L_0x2af5060/d .functor AND 1, L_0x2af4410, L_0x2af5380, C4<1>, C4<1>;
+L_0x2af5060 .delay (20000,20000,20000) L_0x2af5060/d;
+L_0x2af51b0/d .functor OR 1, L_0x2af4f10, L_0x2af5060, C4<0>, C4<0>;
+L_0x2af51b0 .delay (20000,20000,20000) L_0x2af51b0/d;
+v0x281e450_0 .net "S", 0 0, L_0x2af5380; 1 drivers
+v0x281e4d0_0 .alias "in0", 0 0, v0x281f360_0;
+v0x281e570_0 .alias "in1", 0 0, v0x281f010_0;
+v0x281e610_0 .net "nS", 0 0, L_0x2af4e50; 1 drivers
+v0x281e690_0 .net "out0", 0 0, L_0x2af4f10; 1 drivers
+v0x281e730_0 .net "out1", 0 0, L_0x2af5060; 1 drivers
+v0x281e810_0 .alias "outfinal", 0 0, v0x281f2e0_0;
+S_0x281cd70 .scope generate, "orbits[9]" "orbits[9]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x281ca88 .param/l "i" 3 258, +C4<01001>;
+S_0x281cea0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281cd70;
+ .timescale -9 -12;
+L_0x2af54c0/d .functor NOR 1, L_0x2af67d0, L_0x2af5620, C4<0>, C4<0>;
+L_0x2af54c0 .delay (10000,10000,10000) L_0x2af54c0/d;
+L_0x2af5740/d .functor NOT 1, L_0x2af54c0, C4<0>, C4<0>, C4<0>;
+L_0x2af5740 .delay (10000,10000,10000) L_0x2af5740/d;
+L_0x2af5850/d .functor NAND 1, L_0x2af67d0, L_0x2af5620, C4<1>, C4<1>;
+L_0x2af5850 .delay (10000,10000,10000) L_0x2af5850/d;
+L_0x2af59b0/d .functor NAND 1, L_0x2af5850, L_0x2af5740, C4<1>, C4<1>;
+L_0x2af59b0 .delay (10000,10000,10000) L_0x2af59b0/d;
+L_0x2af5ac0/d .functor NOT 1, L_0x2af59b0, C4<0>, C4<0>, C4<0>;
+L_0x2af5ac0 .delay (10000,10000,10000) L_0x2af5ac0/d;
+v0x281da50_0 .net "A", 0 0, L_0x2af67d0; 1 drivers
+v0x281daf0_0 .net "AnandB", 0 0, L_0x2af5850; 1 drivers
+v0x281db90_0 .net "AnorB", 0 0, L_0x2af54c0; 1 drivers
+v0x281dc40_0 .net "AorB", 0 0, L_0x2af5740; 1 drivers
+v0x281dd20_0 .net "AxorB", 0 0, L_0x2af5ac0; 1 drivers
+v0x281ddd0_0 .net "B", 0 0, L_0x2af5620; 1 drivers
+v0x281de90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x281df10_0 .net "OrNorXorOut", 0 0, L_0x2af64c0; 1 drivers
+v0x281df90_0 .net "XorNor", 0 0, L_0x2af5f40; 1 drivers
+v0x281e060_0 .net "nXor", 0 0, L_0x2af59b0; 1 drivers
+L_0x2af60c0 .part v0x2960210_0, 2, 1;
+L_0x2af6690 .part v0x2960210_0, 0, 1;
+S_0x281d4e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281cea0;
+ .timescale -9 -12;
+L_0x2af5c20/d .functor NOT 1, L_0x2af60c0, C4<0>, C4<0>, C4<0>;
+L_0x2af5c20 .delay (10000,10000,10000) L_0x2af5c20/d;
+L_0x2af5ce0/d .functor AND 1, L_0x2af5ac0, L_0x2af5c20, C4<1>, C4<1>;
+L_0x2af5ce0 .delay (20000,20000,20000) L_0x2af5ce0/d;
+L_0x2af5df0/d .functor AND 1, L_0x2af54c0, L_0x2af60c0, C4<1>, C4<1>;
+L_0x2af5df0 .delay (20000,20000,20000) L_0x2af5df0/d;
+L_0x2af5f40/d .functor OR 1, L_0x2af5ce0, L_0x2af5df0, C4<0>, C4<0>;
+L_0x2af5f40 .delay (20000,20000,20000) L_0x2af5f40/d;
+v0x281d5d0_0 .net "S", 0 0, L_0x2af60c0; 1 drivers
+v0x281d690_0 .alias "in0", 0 0, v0x281dd20_0;
+v0x281d730_0 .alias "in1", 0 0, v0x281db90_0;
+v0x281d7d0_0 .net "nS", 0 0, L_0x2af5c20; 1 drivers
+v0x281d850_0 .net "out0", 0 0, L_0x2af5ce0; 1 drivers
+v0x281d8f0_0 .net "out1", 0 0, L_0x2af5df0; 1 drivers
+v0x281d9d0_0 .alias "outfinal", 0 0, v0x281df90_0;
+S_0x281cf90 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281cea0;
+ .timescale -9 -12;
+L_0x2af6160/d .functor NOT 1, L_0x2af6690, C4<0>, C4<0>, C4<0>;
+L_0x2af6160 .delay (10000,10000,10000) L_0x2af6160/d;
+L_0x2af6220/d .functor AND 1, L_0x2af5f40, L_0x2af6160, C4<1>, C4<1>;
+L_0x2af6220 .delay (20000,20000,20000) L_0x2af6220/d;
+L_0x2af6370/d .functor AND 1, L_0x2af5740, L_0x2af6690, C4<1>, C4<1>;
+L_0x2af6370 .delay (20000,20000,20000) L_0x2af6370/d;
+L_0x2af64c0/d .functor OR 1, L_0x2af6220, L_0x2af6370, C4<0>, C4<0>;
+L_0x2af64c0 .delay (20000,20000,20000) L_0x2af64c0/d;
+v0x281d080_0 .net "S", 0 0, L_0x2af6690; 1 drivers
+v0x281d100_0 .alias "in0", 0 0, v0x281df90_0;
+v0x281d1a0_0 .alias "in1", 0 0, v0x281dc40_0;
+v0x281d240_0 .net "nS", 0 0, L_0x2af6160; 1 drivers
+v0x281d2c0_0 .net "out0", 0 0, L_0x2af6220; 1 drivers
+v0x281d360_0 .net "out1", 0 0, L_0x2af6370; 1 drivers
+v0x281d440_0 .alias "outfinal", 0 0, v0x281df10_0;
+S_0x281b9a0 .scope generate, "orbits[10]" "orbits[10]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x281b6b8 .param/l "i" 3 258, +C4<01010>;
+S_0x281bad0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281b9a0;
+ .timescale -9 -12;
+L_0x2af6950/d .functor NOR 1, L_0x2af6870, L_0x2af7bc0, C4<0>, C4<0>;
+L_0x2af6950 .delay (10000,10000,10000) L_0x2af6950/d;
+L_0x2af6a40/d .functor NOT 1, L_0x2af6950, C4<0>, C4<0>, C4<0>;
+L_0x2af6a40 .delay (10000,10000,10000) L_0x2af6a40/d;
+L_0x2af6b50/d .functor NAND 1, L_0x2af6870, L_0x2af7bc0, C4<1>, C4<1>;
+L_0x2af6b50 .delay (10000,10000,10000) L_0x2af6b50/d;
+L_0x2af6cb0/d .functor NAND 1, L_0x2af6b50, L_0x2af6a40, C4<1>, C4<1>;
+L_0x2af6cb0 .delay (10000,10000,10000) L_0x2af6cb0/d;
+L_0x2af6dc0/d .functor NOT 1, L_0x2af6cb0, C4<0>, C4<0>, C4<0>;
+L_0x2af6dc0 .delay (10000,10000,10000) L_0x2af6dc0/d;
+v0x281c680_0 .net "A", 0 0, L_0x2af6870; 1 drivers
+v0x281c720_0 .net "AnandB", 0 0, L_0x2af6b50; 1 drivers
+v0x281c7c0_0 .net "AnorB", 0 0, L_0x2af6950; 1 drivers
+v0x281c870_0 .net "AorB", 0 0, L_0x2af6a40; 1 drivers
+v0x281c950_0 .net "AxorB", 0 0, L_0x2af6dc0; 1 drivers
+v0x281ca00_0 .net "B", 0 0, L_0x2af7bc0; 1 drivers
+v0x281cac0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x281cb40_0 .net "OrNorXorOut", 0 0, L_0x2af77c0; 1 drivers
+v0x281cbc0_0 .net "XorNor", 0 0, L_0x2af7240; 1 drivers
+v0x281cc90_0 .net "nXor", 0 0, L_0x2af6cb0; 1 drivers
+L_0x2af73c0 .part v0x2960210_0, 2, 1;
+L_0x2af7990 .part v0x2960210_0, 0, 1;
+S_0x281c110 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281bad0;
+ .timescale -9 -12;
+L_0x2af6f20/d .functor NOT 1, L_0x2af73c0, C4<0>, C4<0>, C4<0>;
+L_0x2af6f20 .delay (10000,10000,10000) L_0x2af6f20/d;
+L_0x2af6fe0/d .functor AND 1, L_0x2af6dc0, L_0x2af6f20, C4<1>, C4<1>;
+L_0x2af6fe0 .delay (20000,20000,20000) L_0x2af6fe0/d;
+L_0x2af70f0/d .functor AND 1, L_0x2af6950, L_0x2af73c0, C4<1>, C4<1>;
+L_0x2af70f0 .delay (20000,20000,20000) L_0x2af70f0/d;
+L_0x2af7240/d .functor OR 1, L_0x2af6fe0, L_0x2af70f0, C4<0>, C4<0>;
+L_0x2af7240 .delay (20000,20000,20000) L_0x2af7240/d;
+v0x281c200_0 .net "S", 0 0, L_0x2af73c0; 1 drivers
+v0x281c2c0_0 .alias "in0", 0 0, v0x281c950_0;
+v0x281c360_0 .alias "in1", 0 0, v0x281c7c0_0;
+v0x281c400_0 .net "nS", 0 0, L_0x2af6f20; 1 drivers
+v0x281c480_0 .net "out0", 0 0, L_0x2af6fe0; 1 drivers
+v0x281c520_0 .net "out1", 0 0, L_0x2af70f0; 1 drivers
+v0x281c600_0 .alias "outfinal", 0 0, v0x281cbc0_0;
+S_0x281bbc0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281bad0;
+ .timescale -9 -12;
+L_0x2af7460/d .functor NOT 1, L_0x2af7990, C4<0>, C4<0>, C4<0>;
+L_0x2af7460 .delay (10000,10000,10000) L_0x2af7460/d;
+L_0x2af7520/d .functor AND 1, L_0x2af7240, L_0x2af7460, C4<1>, C4<1>;
+L_0x2af7520 .delay (20000,20000,20000) L_0x2af7520/d;
+L_0x2af7670/d .functor AND 1, L_0x2af6a40, L_0x2af7990, C4<1>, C4<1>;
+L_0x2af7670 .delay (20000,20000,20000) L_0x2af7670/d;
+L_0x2af77c0/d .functor OR 1, L_0x2af7520, L_0x2af7670, C4<0>, C4<0>;
+L_0x2af77c0 .delay (20000,20000,20000) L_0x2af77c0/d;
+v0x281bcb0_0 .net "S", 0 0, L_0x2af7990; 1 drivers
+v0x281bd30_0 .alias "in0", 0 0, v0x281cbc0_0;
+v0x281bdd0_0 .alias "in1", 0 0, v0x281c870_0;
+v0x281be70_0 .net "nS", 0 0, L_0x2af7460; 1 drivers
+v0x281bef0_0 .net "out0", 0 0, L_0x2af7520; 1 drivers
+v0x281bf90_0 .net "out1", 0 0, L_0x2af7670; 1 drivers
+v0x281c070_0 .alias "outfinal", 0 0, v0x281cb40_0;
+S_0x281a5d0 .scope generate, "orbits[11]" "orbits[11]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x281a2e8 .param/l "i" 3 258, +C4<01011>;
+S_0x281a700 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x281a5d0;
+ .timescale -9 -12;
+L_0x2af7ad0/d .functor NOR 1, L_0x2af8dd0, L_0x2af7c60, C4<0>, C4<0>;
+L_0x2af7ad0 .delay (10000,10000,10000) L_0x2af7ad0/d;
+L_0x2af7d60/d .functor NOT 1, L_0x2af7ad0, C4<0>, C4<0>, C4<0>;
+L_0x2af7d60 .delay (10000,10000,10000) L_0x2af7d60/d;
+L_0x2af7e50/d .functor NAND 1, L_0x2af8dd0, L_0x2af7c60, C4<1>, C4<1>;
+L_0x2af7e50 .delay (10000,10000,10000) L_0x2af7e50/d;
+L_0x2af7fb0/d .functor NAND 1, L_0x2af7e50, L_0x2af7d60, C4<1>, C4<1>;
+L_0x2af7fb0 .delay (10000,10000,10000) L_0x2af7fb0/d;
+L_0x2af80c0/d .functor NOT 1, L_0x2af7fb0, C4<0>, C4<0>, C4<0>;
+L_0x2af80c0 .delay (10000,10000,10000) L_0x2af80c0/d;
+v0x281b2b0_0 .net "A", 0 0, L_0x2af8dd0; 1 drivers
+v0x281b350_0 .net "AnandB", 0 0, L_0x2af7e50; 1 drivers
+v0x281b3f0_0 .net "AnorB", 0 0, L_0x2af7ad0; 1 drivers
+v0x281b4a0_0 .net "AorB", 0 0, L_0x2af7d60; 1 drivers
+v0x281b580_0 .net "AxorB", 0 0, L_0x2af80c0; 1 drivers
+v0x281b630_0 .net "B", 0 0, L_0x2af7c60; 1 drivers
+v0x281b6f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x281b770_0 .net "OrNorXorOut", 0 0, L_0x2af8ac0; 1 drivers
+v0x281b7f0_0 .net "XorNor", 0 0, L_0x2af8540; 1 drivers
+v0x281b8c0_0 .net "nXor", 0 0, L_0x2af7fb0; 1 drivers
+L_0x2af86c0 .part v0x2960210_0, 2, 1;
+L_0x2af8c90 .part v0x2960210_0, 0, 1;
+S_0x281ad40 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x281a700;
+ .timescale -9 -12;
+L_0x2af8220/d .functor NOT 1, L_0x2af86c0, C4<0>, C4<0>, C4<0>;
+L_0x2af8220 .delay (10000,10000,10000) L_0x2af8220/d;
+L_0x2af82e0/d .functor AND 1, L_0x2af80c0, L_0x2af8220, C4<1>, C4<1>;
+L_0x2af82e0 .delay (20000,20000,20000) L_0x2af82e0/d;
+L_0x2af83f0/d .functor AND 1, L_0x2af7ad0, L_0x2af86c0, C4<1>, C4<1>;
+L_0x2af83f0 .delay (20000,20000,20000) L_0x2af83f0/d;
+L_0x2af8540/d .functor OR 1, L_0x2af82e0, L_0x2af83f0, C4<0>, C4<0>;
+L_0x2af8540 .delay (20000,20000,20000) L_0x2af8540/d;
+v0x281ae30_0 .net "S", 0 0, L_0x2af86c0; 1 drivers
+v0x281aef0_0 .alias "in0", 0 0, v0x281b580_0;
+v0x281af90_0 .alias "in1", 0 0, v0x281b3f0_0;
+v0x281b030_0 .net "nS", 0 0, L_0x2af8220; 1 drivers
+v0x281b0b0_0 .net "out0", 0 0, L_0x2af82e0; 1 drivers
+v0x281b150_0 .net "out1", 0 0, L_0x2af83f0; 1 drivers
+v0x281b230_0 .alias "outfinal", 0 0, v0x281b7f0_0;
+S_0x281a7f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x281a700;
+ .timescale -9 -12;
+L_0x2af8760/d .functor NOT 1, L_0x2af8c90, C4<0>, C4<0>, C4<0>;
+L_0x2af8760 .delay (10000,10000,10000) L_0x2af8760/d;
+L_0x2af8820/d .functor AND 1, L_0x2af8540, L_0x2af8760, C4<1>, C4<1>;
+L_0x2af8820 .delay (20000,20000,20000) L_0x2af8820/d;
+L_0x2af8970/d .functor AND 1, L_0x2af7d60, L_0x2af8c90, C4<1>, C4<1>;
+L_0x2af8970 .delay (20000,20000,20000) L_0x2af8970/d;
+L_0x2af8ac0/d .functor OR 1, L_0x2af8820, L_0x2af8970, C4<0>, C4<0>;
+L_0x2af8ac0 .delay (20000,20000,20000) L_0x2af8ac0/d;
+v0x281a8e0_0 .net "S", 0 0, L_0x2af8c90; 1 drivers
+v0x281a960_0 .alias "in0", 0 0, v0x281b7f0_0;
+v0x281aa00_0 .alias "in1", 0 0, v0x281b4a0_0;
+v0x281aaa0_0 .net "nS", 0 0, L_0x2af8760; 1 drivers
+v0x281ab20_0 .net "out0", 0 0, L_0x2af8820; 1 drivers
+v0x281abc0_0 .net "out1", 0 0, L_0x2af8970; 1 drivers
+v0x281aca0_0 .alias "outfinal", 0 0, v0x281b770_0;
+S_0x2819200 .scope generate, "orbits[12]" "orbits[12]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2818f18 .param/l "i" 3 258, +C4<01100>;
+S_0x2819330 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2819200;
+ .timescale -9 -12;
+L_0x2af7d00/d .functor NOR 1, L_0x2af8e70, L_0x2afa1e0, C4<0>, C4<0>;
+L_0x2af7d00 .delay (10000,10000,10000) L_0x2af7d00/d;
+L_0x2af9010/d .functor NOT 1, L_0x2af7d00, C4<0>, C4<0>, C4<0>;
+L_0x2af9010 .delay (10000,10000,10000) L_0x2af9010/d;
+L_0x2af9140/d .functor NAND 1, L_0x2af8e70, L_0x2afa1e0, C4<1>, C4<1>;
+L_0x2af9140 .delay (10000,10000,10000) L_0x2af9140/d;
+L_0x2af92a0/d .functor NAND 1, L_0x2af9140, L_0x2af9010, C4<1>, C4<1>;
+L_0x2af92a0 .delay (10000,10000,10000) L_0x2af92a0/d;
+L_0x2af93b0/d .functor NOT 1, L_0x2af92a0, C4<0>, C4<0>, C4<0>;
+L_0x2af93b0 .delay (10000,10000,10000) L_0x2af93b0/d;
+v0x2819ee0_0 .net "A", 0 0, L_0x2af8e70; 1 drivers
+v0x2819f80_0 .net "AnandB", 0 0, L_0x2af9140; 1 drivers
+v0x281a020_0 .net "AnorB", 0 0, L_0x2af7d00; 1 drivers
+v0x281a0d0_0 .net "AorB", 0 0, L_0x2af9010; 1 drivers
+v0x281a1b0_0 .net "AxorB", 0 0, L_0x2af93b0; 1 drivers
+v0x281a260_0 .net "B", 0 0, L_0x2afa1e0; 1 drivers
+v0x281a320_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x281a3a0_0 .net "OrNorXorOut", 0 0, L_0x2af9db0; 1 drivers
+v0x281a420_0 .net "XorNor", 0 0, L_0x2af9830; 1 drivers
+v0x281a4f0_0 .net "nXor", 0 0, L_0x2af92a0; 1 drivers
+L_0x2af99b0 .part v0x2960210_0, 2, 1;
+L_0x2af9f80 .part v0x2960210_0, 0, 1;
+S_0x2819970 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2819330;
+ .timescale -9 -12;
+L_0x2af9510/d .functor NOT 1, L_0x2af99b0, C4<0>, C4<0>, C4<0>;
+L_0x2af9510 .delay (10000,10000,10000) L_0x2af9510/d;
+L_0x2af95d0/d .functor AND 1, L_0x2af93b0, L_0x2af9510, C4<1>, C4<1>;
+L_0x2af95d0 .delay (20000,20000,20000) L_0x2af95d0/d;
+L_0x2af96e0/d .functor AND 1, L_0x2af7d00, L_0x2af99b0, C4<1>, C4<1>;
+L_0x2af96e0 .delay (20000,20000,20000) L_0x2af96e0/d;
+L_0x2af9830/d .functor OR 1, L_0x2af95d0, L_0x2af96e0, C4<0>, C4<0>;
+L_0x2af9830 .delay (20000,20000,20000) L_0x2af9830/d;
+v0x2819a60_0 .net "S", 0 0, L_0x2af99b0; 1 drivers
+v0x2819b20_0 .alias "in0", 0 0, v0x281a1b0_0;
+v0x2819bc0_0 .alias "in1", 0 0, v0x281a020_0;
+v0x2819c60_0 .net "nS", 0 0, L_0x2af9510; 1 drivers
+v0x2819ce0_0 .net "out0", 0 0, L_0x2af95d0; 1 drivers
+v0x2819d80_0 .net "out1", 0 0, L_0x2af96e0; 1 drivers
+v0x2819e60_0 .alias "outfinal", 0 0, v0x281a420_0;
+S_0x2819420 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2819330;
+ .timescale -9 -12;
+L_0x2af9a50/d .functor NOT 1, L_0x2af9f80, C4<0>, C4<0>, C4<0>;
+L_0x2af9a50 .delay (10000,10000,10000) L_0x2af9a50/d;
+L_0x2af9b10/d .functor AND 1, L_0x2af9830, L_0x2af9a50, C4<1>, C4<1>;
+L_0x2af9b10 .delay (20000,20000,20000) L_0x2af9b10/d;
+L_0x2af9c60/d .functor AND 1, L_0x2af9010, L_0x2af9f80, C4<1>, C4<1>;
+L_0x2af9c60 .delay (20000,20000,20000) L_0x2af9c60/d;
+L_0x2af9db0/d .functor OR 1, L_0x2af9b10, L_0x2af9c60, C4<0>, C4<0>;
+L_0x2af9db0 .delay (20000,20000,20000) L_0x2af9db0/d;
+v0x2819510_0 .net "S", 0 0, L_0x2af9f80; 1 drivers
+v0x2819590_0 .alias "in0", 0 0, v0x281a420_0;
+v0x2819630_0 .alias "in1", 0 0, v0x281a0d0_0;
+v0x28196d0_0 .net "nS", 0 0, L_0x2af9a50; 1 drivers
+v0x2819750_0 .net "out0", 0 0, L_0x2af9b10; 1 drivers
+v0x28197f0_0 .net "out1", 0 0, L_0x2af9c60; 1 drivers
+v0x28198d0_0 .alias "outfinal", 0 0, v0x281a3a0_0;
+S_0x2817e30 .scope generate, "orbits[13]" "orbits[13]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2817b48 .param/l "i" 3 258, +C4<01101>;
+S_0x2817f60 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2817e30;
+ .timescale -9 -12;
+L_0x2af8f10/d .functor NOR 1, L_0x2afb3e0, L_0x2afa280, C4<0>, C4<0>;
+L_0x2af8f10 .delay (10000,10000,10000) L_0x2af8f10/d;
+L_0x2afa150/d .functor NOT 1, L_0x2af8f10, C4<0>, C4<0>, C4<0>;
+L_0x2afa150 .delay (10000,10000,10000) L_0x2afa150/d;
+L_0x2afa460/d .functor NAND 1, L_0x2afb3e0, L_0x2afa280, C4<1>, C4<1>;
+L_0x2afa460 .delay (10000,10000,10000) L_0x2afa460/d;
+L_0x2afa5c0/d .functor NAND 1, L_0x2afa460, L_0x2afa150, C4<1>, C4<1>;
+L_0x2afa5c0 .delay (10000,10000,10000) L_0x2afa5c0/d;
+L_0x2afa6d0/d .functor NOT 1, L_0x2afa5c0, C4<0>, C4<0>, C4<0>;
+L_0x2afa6d0 .delay (10000,10000,10000) L_0x2afa6d0/d;
+v0x2818b10_0 .net "A", 0 0, L_0x2afb3e0; 1 drivers
+v0x2818bb0_0 .net "AnandB", 0 0, L_0x2afa460; 1 drivers
+v0x2818c50_0 .net "AnorB", 0 0, L_0x2af8f10; 1 drivers
+v0x2818d00_0 .net "AorB", 0 0, L_0x2afa150; 1 drivers
+v0x2818de0_0 .net "AxorB", 0 0, L_0x2afa6d0; 1 drivers
+v0x2818e90_0 .net "B", 0 0, L_0x2afa280; 1 drivers
+v0x2818f50_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2818fd0_0 .net "OrNorXorOut", 0 0, L_0x2afb0d0; 1 drivers
+v0x2819050_0 .net "XorNor", 0 0, L_0x2afab50; 1 drivers
+v0x2819120_0 .net "nXor", 0 0, L_0x2afa5c0; 1 drivers
+L_0x2afacd0 .part v0x2960210_0, 2, 1;
+L_0x2afb2a0 .part v0x2960210_0, 0, 1;
+S_0x28185a0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2817f60;
+ .timescale -9 -12;
+L_0x2afa830/d .functor NOT 1, L_0x2afacd0, C4<0>, C4<0>, C4<0>;
+L_0x2afa830 .delay (10000,10000,10000) L_0x2afa830/d;
+L_0x2afa8f0/d .functor AND 1, L_0x2afa6d0, L_0x2afa830, C4<1>, C4<1>;
+L_0x2afa8f0 .delay (20000,20000,20000) L_0x2afa8f0/d;
+L_0x2afaa00/d .functor AND 1, L_0x2af8f10, L_0x2afacd0, C4<1>, C4<1>;
+L_0x2afaa00 .delay (20000,20000,20000) L_0x2afaa00/d;
+L_0x2afab50/d .functor OR 1, L_0x2afa8f0, L_0x2afaa00, C4<0>, C4<0>;
+L_0x2afab50 .delay (20000,20000,20000) L_0x2afab50/d;
+v0x2818690_0 .net "S", 0 0, L_0x2afacd0; 1 drivers
+v0x2818750_0 .alias "in0", 0 0, v0x2818de0_0;
+v0x28187f0_0 .alias "in1", 0 0, v0x2818c50_0;
+v0x2818890_0 .net "nS", 0 0, L_0x2afa830; 1 drivers
+v0x2818910_0 .net "out0", 0 0, L_0x2afa8f0; 1 drivers
+v0x28189b0_0 .net "out1", 0 0, L_0x2afaa00; 1 drivers
+v0x2818a90_0 .alias "outfinal", 0 0, v0x2819050_0;
+S_0x2818050 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2817f60;
+ .timescale -9 -12;
+L_0x2afad70/d .functor NOT 1, L_0x2afb2a0, C4<0>, C4<0>, C4<0>;
+L_0x2afad70 .delay (10000,10000,10000) L_0x2afad70/d;
+L_0x2afae30/d .functor AND 1, L_0x2afab50, L_0x2afad70, C4<1>, C4<1>;
+L_0x2afae30 .delay (20000,20000,20000) L_0x2afae30/d;
+L_0x2afaf80/d .functor AND 1, L_0x2afa150, L_0x2afb2a0, C4<1>, C4<1>;
+L_0x2afaf80 .delay (20000,20000,20000) L_0x2afaf80/d;
+L_0x2afb0d0/d .functor OR 1, L_0x2afae30, L_0x2afaf80, C4<0>, C4<0>;
+L_0x2afb0d0 .delay (20000,20000,20000) L_0x2afb0d0/d;
+v0x2818140_0 .net "S", 0 0, L_0x2afb2a0; 1 drivers
+v0x28181c0_0 .alias "in0", 0 0, v0x2819050_0;
+v0x2818260_0 .alias "in1", 0 0, v0x2818d00_0;
+v0x2818300_0 .net "nS", 0 0, L_0x2afad70; 1 drivers
+v0x2818380_0 .net "out0", 0 0, L_0x2afae30; 1 drivers
+v0x2818420_0 .net "out1", 0 0, L_0x2afaf80; 1 drivers
+v0x2818500_0 .alias "outfinal", 0 0, v0x2818fd0_0;
+S_0x2816a60 .scope generate, "orbits[14]" "orbits[14]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2816778 .param/l "i" 3 258, +C4<01110>;
+S_0x2816b90 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2816a60;
+ .timescale -9 -12;
+L_0x2afa320/d .functor NOR 1, L_0x2afb480, L_0x2afb520, C4<0>, C4<0>;
+L_0x2afa320 .delay (10000,10000,10000) L_0x2afa320/d;
+L_0x2afb650/d .functor NOT 1, L_0x2afa320, C4<0>, C4<0>, C4<0>;
+L_0x2afb650 .delay (10000,10000,10000) L_0x2afb650/d;
+L_0x2afb760/d .functor NAND 1, L_0x2afb480, L_0x2afb520, C4<1>, C4<1>;
+L_0x2afb760 .delay (10000,10000,10000) L_0x2afb760/d;
+L_0x2afb8c0/d .functor NAND 1, L_0x2afb760, L_0x2afb650, C4<1>, C4<1>;
+L_0x2afb8c0 .delay (10000,10000,10000) L_0x2afb8c0/d;
+L_0x2afb9d0/d .functor NOT 1, L_0x2afb8c0, C4<0>, C4<0>, C4<0>;
+L_0x2afb9d0 .delay (10000,10000,10000) L_0x2afb9d0/d;
+v0x2817740_0 .net "A", 0 0, L_0x2afb480; 1 drivers
+v0x28177e0_0 .net "AnandB", 0 0, L_0x2afb760; 1 drivers
+v0x2817880_0 .net "AnorB", 0 0, L_0x2afa320; 1 drivers
+v0x2817930_0 .net "AorB", 0 0, L_0x2afb650; 1 drivers
+v0x2817a10_0 .net "AxorB", 0 0, L_0x2afb9d0; 1 drivers
+v0x2817ac0_0 .net "B", 0 0, L_0x2afb520; 1 drivers
+v0x2817b80_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2817c00_0 .net "OrNorXorOut", 0 0, L_0x2afc3d0; 1 drivers
+v0x2817c80_0 .net "XorNor", 0 0, L_0x2afbe50; 1 drivers
+v0x2817d50_0 .net "nXor", 0 0, L_0x2afb8c0; 1 drivers
+L_0x2afbfd0 .part v0x2960210_0, 2, 1;
+L_0x2afc5a0 .part v0x2960210_0, 0, 1;
+S_0x28171d0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2816b90;
+ .timescale -9 -12;
+L_0x2afbb30/d .functor NOT 1, L_0x2afbfd0, C4<0>, C4<0>, C4<0>;
+L_0x2afbb30 .delay (10000,10000,10000) L_0x2afbb30/d;
+L_0x2afbbf0/d .functor AND 1, L_0x2afb9d0, L_0x2afbb30, C4<1>, C4<1>;
+L_0x2afbbf0 .delay (20000,20000,20000) L_0x2afbbf0/d;
+L_0x2afbd00/d .functor AND 1, L_0x2afa320, L_0x2afbfd0, C4<1>, C4<1>;
+L_0x2afbd00 .delay (20000,20000,20000) L_0x2afbd00/d;
+L_0x2afbe50/d .functor OR 1, L_0x2afbbf0, L_0x2afbd00, C4<0>, C4<0>;
+L_0x2afbe50 .delay (20000,20000,20000) L_0x2afbe50/d;
+v0x28172c0_0 .net "S", 0 0, L_0x2afbfd0; 1 drivers
+v0x2817380_0 .alias "in0", 0 0, v0x2817a10_0;
+v0x2817420_0 .alias "in1", 0 0, v0x2817880_0;
+v0x28174c0_0 .net "nS", 0 0, L_0x2afbb30; 1 drivers
+v0x2817540_0 .net "out0", 0 0, L_0x2afbbf0; 1 drivers
+v0x28175e0_0 .net "out1", 0 0, L_0x2afbd00; 1 drivers
+v0x28176c0_0 .alias "outfinal", 0 0, v0x2817c80_0;
+S_0x2816c80 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2816b90;
+ .timescale -9 -12;
+L_0x2afc070/d .functor NOT 1, L_0x2afc5a0, C4<0>, C4<0>, C4<0>;
+L_0x2afc070 .delay (10000,10000,10000) L_0x2afc070/d;
+L_0x2afc130/d .functor AND 1, L_0x2afbe50, L_0x2afc070, C4<1>, C4<1>;
+L_0x2afc130 .delay (20000,20000,20000) L_0x2afc130/d;
+L_0x2afc280/d .functor AND 1, L_0x2afb650, L_0x2afc5a0, C4<1>, C4<1>;
+L_0x2afc280 .delay (20000,20000,20000) L_0x2afc280/d;
+L_0x2afc3d0/d .functor OR 1, L_0x2afc130, L_0x2afc280, C4<0>, C4<0>;
+L_0x2afc3d0 .delay (20000,20000,20000) L_0x2afc3d0/d;
+v0x2816d70_0 .net "S", 0 0, L_0x2afc5a0; 1 drivers
+v0x2816df0_0 .alias "in0", 0 0, v0x2817c80_0;
+v0x2816e90_0 .alias "in1", 0 0, v0x2817930_0;
+v0x2816f30_0 .net "nS", 0 0, L_0x2afc070; 1 drivers
+v0x2816fb0_0 .net "out0", 0 0, L_0x2afc130; 1 drivers
+v0x2817050_0 .net "out1", 0 0, L_0x2afc280; 1 drivers
+v0x2817130_0 .alias "outfinal", 0 0, v0x2817c00_0;
+S_0x2815690 .scope generate, "orbits[15]" "orbits[15]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x28153a8 .param/l "i" 3 258, +C4<01111>;
+S_0x28157c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2815690;
+ .timescale -9 -12;
+L_0x2afc840/d .functor NOR 1, L_0x2afd9e0, L_0x2afc6e0, C4<0>, C4<0>;
+L_0x2afc840 .delay (10000,10000,10000) L_0x2afc840/d;
+L_0x2afc930/d .functor NOT 1, L_0x2afc840, C4<0>, C4<0>, C4<0>;
+L_0x2afc930 .delay (10000,10000,10000) L_0x2afc930/d;
+L_0x2afca60/d .functor NAND 1, L_0x2afd9e0, L_0x2afc6e0, C4<1>, C4<1>;
+L_0x2afca60 .delay (10000,10000,10000) L_0x2afca60/d;
+L_0x2afcbc0/d .functor NAND 1, L_0x2afca60, L_0x2afc930, C4<1>, C4<1>;
+L_0x2afcbc0 .delay (10000,10000,10000) L_0x2afcbc0/d;
+L_0x2afccd0/d .functor NOT 1, L_0x2afcbc0, C4<0>, C4<0>, C4<0>;
+L_0x2afccd0 .delay (10000,10000,10000) L_0x2afccd0/d;
+v0x2816370_0 .net "A", 0 0, L_0x2afd9e0; 1 drivers
+v0x2816410_0 .net "AnandB", 0 0, L_0x2afca60; 1 drivers
+v0x28164b0_0 .net "AnorB", 0 0, L_0x2afc840; 1 drivers
+v0x2816560_0 .net "AorB", 0 0, L_0x2afc930; 1 drivers
+v0x2816640_0 .net "AxorB", 0 0, L_0x2afccd0; 1 drivers
+v0x28166f0_0 .net "B", 0 0, L_0x2afc6e0; 1 drivers
+v0x28167b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2816830_0 .net "OrNorXorOut", 0 0, L_0x2afd6d0; 1 drivers
+v0x28168b0_0 .net "XorNor", 0 0, L_0x2afd150; 1 drivers
+v0x2816980_0 .net "nXor", 0 0, L_0x2afcbc0; 1 drivers
+L_0x2afd2d0 .part v0x2960210_0, 2, 1;
+L_0x2afd8a0 .part v0x2960210_0, 0, 1;
+S_0x2815e00 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28157c0;
+ .timescale -9 -12;
+L_0x2afce30/d .functor NOT 1, L_0x2afd2d0, C4<0>, C4<0>, C4<0>;
+L_0x2afce30 .delay (10000,10000,10000) L_0x2afce30/d;
+L_0x2afcef0/d .functor AND 1, L_0x2afccd0, L_0x2afce30, C4<1>, C4<1>;
+L_0x2afcef0 .delay (20000,20000,20000) L_0x2afcef0/d;
+L_0x2afd000/d .functor AND 1, L_0x2afc840, L_0x2afd2d0, C4<1>, C4<1>;
+L_0x2afd000 .delay (20000,20000,20000) L_0x2afd000/d;
+L_0x2afd150/d .functor OR 1, L_0x2afcef0, L_0x2afd000, C4<0>, C4<0>;
+L_0x2afd150 .delay (20000,20000,20000) L_0x2afd150/d;
+v0x2815ef0_0 .net "S", 0 0, L_0x2afd2d0; 1 drivers
+v0x2815fb0_0 .alias "in0", 0 0, v0x2816640_0;
+v0x2816050_0 .alias "in1", 0 0, v0x28164b0_0;
+v0x28160f0_0 .net "nS", 0 0, L_0x2afce30; 1 drivers
+v0x2816170_0 .net "out0", 0 0, L_0x2afcef0; 1 drivers
+v0x2816210_0 .net "out1", 0 0, L_0x2afd000; 1 drivers
+v0x28162f0_0 .alias "outfinal", 0 0, v0x28168b0_0;
+S_0x28158b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28157c0;
+ .timescale -9 -12;
+L_0x2afd370/d .functor NOT 1, L_0x2afd8a0, C4<0>, C4<0>, C4<0>;
+L_0x2afd370 .delay (10000,10000,10000) L_0x2afd370/d;
+L_0x2afd430/d .functor AND 1, L_0x2afd150, L_0x2afd370, C4<1>, C4<1>;
+L_0x2afd430 .delay (20000,20000,20000) L_0x2afd430/d;
+L_0x2afd580/d .functor AND 1, L_0x2afc930, L_0x2afd8a0, C4<1>, C4<1>;
+L_0x2afd580 .delay (20000,20000,20000) L_0x2afd580/d;
+L_0x2afd6d0/d .functor OR 1, L_0x2afd430, L_0x2afd580, C4<0>, C4<0>;
+L_0x2afd6d0 .delay (20000,20000,20000) L_0x2afd6d0/d;
+v0x28159a0_0 .net "S", 0 0, L_0x2afd8a0; 1 drivers
+v0x2815a20_0 .alias "in0", 0 0, v0x28168b0_0;
+v0x2815ac0_0 .alias "in1", 0 0, v0x2816560_0;
+v0x2815b60_0 .net "nS", 0 0, L_0x2afd370; 1 drivers
+v0x2815be0_0 .net "out0", 0 0, L_0x2afd430; 1 drivers
+v0x2815c80_0 .net "out1", 0 0, L_0x2afd580; 1 drivers
+v0x2815d60_0 .alias "outfinal", 0 0, v0x2816830_0;
+S_0x28142c0 .scope generate, "orbits[16]" "orbits[16]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2813fd8 .param/l "i" 3 258, +C4<010000>;
+S_0x28143f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28142c0;
+ .timescale -9 -12;
+L_0x2afc780/d .functor NOR 1, L_0x2afda80, L_0x2afdb20, C4<0>, C4<0>;
+L_0x2afc780 .delay (10000,10000,10000) L_0x2afc780/d;
+L_0x2afdc40/d .functor NOT 1, L_0x2afc780, C4<0>, C4<0>, C4<0>;
+L_0x2afdc40 .delay (10000,10000,10000) L_0x2afdc40/d;
+L_0x2afdd50/d .functor NAND 1, L_0x2afda80, L_0x2afdb20, C4<1>, C4<1>;
+L_0x2afdd50 .delay (10000,10000,10000) L_0x2afdd50/d;
+L_0x2afdeb0/d .functor NAND 1, L_0x2afdd50, L_0x2afdc40, C4<1>, C4<1>;
+L_0x2afdeb0 .delay (10000,10000,10000) L_0x2afdeb0/d;
+L_0x2af0980/d .functor NOT 1, L_0x2afdeb0, C4<0>, C4<0>, C4<0>;
+L_0x2af0980 .delay (10000,10000,10000) L_0x2af0980/d;
+v0x2814fa0_0 .net "A", 0 0, L_0x2afda80; 1 drivers
+v0x2815040_0 .net "AnandB", 0 0, L_0x2afdd50; 1 drivers
+v0x28150e0_0 .net "AnorB", 0 0, L_0x2afc780; 1 drivers
+v0x2815190_0 .net "AorB", 0 0, L_0x2afdc40; 1 drivers
+v0x2815270_0 .net "AxorB", 0 0, L_0x2af0980; 1 drivers
+v0x2815320_0 .net "B", 0 0, L_0x2afdb20; 1 drivers
+v0x28153e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2815460_0 .net "OrNorXorOut", 0 0, L_0x2afe7f0; 1 drivers
+v0x28154e0_0 .net "XorNor", 0 0, L_0x2afe310; 1 drivers
+v0x28155b0_0 .net "nXor", 0 0, L_0x2afdeb0; 1 drivers
+L_0x2afe450 .part v0x2960210_0, 2, 1;
+L_0x2afe980 .part v0x2960210_0, 0, 1;
+S_0x2814a30 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28143f0;
+ .timescale -9 -12;
+L_0x2afe050/d .functor NOT 1, L_0x2afe450, C4<0>, C4<0>, C4<0>;
+L_0x2afe050 .delay (10000,10000,10000) L_0x2afe050/d;
+L_0x2afe0f0/d .functor AND 1, L_0x2af0980, L_0x2afe050, C4<1>, C4<1>;
+L_0x2afe0f0 .delay (20000,20000,20000) L_0x2afe0f0/d;
+L_0x2afe1e0/d .functor AND 1, L_0x2afc780, L_0x2afe450, C4<1>, C4<1>;
+L_0x2afe1e0 .delay (20000,20000,20000) L_0x2afe1e0/d;
+L_0x2afe310/d .functor OR 1, L_0x2afe0f0, L_0x2afe1e0, C4<0>, C4<0>;
+L_0x2afe310 .delay (20000,20000,20000) L_0x2afe310/d;
+v0x2814b20_0 .net "S", 0 0, L_0x2afe450; 1 drivers
+v0x2814be0_0 .alias "in0", 0 0, v0x2815270_0;
+v0x2814c80_0 .alias "in1", 0 0, v0x28150e0_0;
+v0x2814d20_0 .net "nS", 0 0, L_0x2afe050; 1 drivers
+v0x2814da0_0 .net "out0", 0 0, L_0x2afe0f0; 1 drivers
+v0x2814e40_0 .net "out1", 0 0, L_0x2afe1e0; 1 drivers
+v0x2814f20_0 .alias "outfinal", 0 0, v0x28154e0_0;
+S_0x28144e0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28143f0;
+ .timescale -9 -12;
+L_0x2afe4f0/d .functor NOT 1, L_0x2afe980, C4<0>, C4<0>, C4<0>;
+L_0x2afe4f0 .delay (10000,10000,10000) L_0x2afe4f0/d;
+L_0x2afe590/d .functor AND 1, L_0x2afe310, L_0x2afe4f0, C4<1>, C4<1>;
+L_0x2afe590 .delay (20000,20000,20000) L_0x2afe590/d;
+L_0x2afe6c0/d .functor AND 1, L_0x2afdc40, L_0x2afe980, C4<1>, C4<1>;
+L_0x2afe6c0 .delay (20000,20000,20000) L_0x2afe6c0/d;
+L_0x2afe7f0/d .functor OR 1, L_0x2afe590, L_0x2afe6c0, C4<0>, C4<0>;
+L_0x2afe7f0 .delay (20000,20000,20000) L_0x2afe7f0/d;
+v0x28145d0_0 .net "S", 0 0, L_0x2afe980; 1 drivers
+v0x2814650_0 .alias "in0", 0 0, v0x28154e0_0;
+v0x28146f0_0 .alias "in1", 0 0, v0x2815190_0;
+v0x2814790_0 .net "nS", 0 0, L_0x2afe4f0; 1 drivers
+v0x2814810_0 .net "out0", 0 0, L_0x2afe590; 1 drivers
+v0x28148b0_0 .net "out1", 0 0, L_0x2afe6c0; 1 drivers
+v0x2814990_0 .alias "outfinal", 0 0, v0x2815460_0;
+S_0x2812ef0 .scope generate, "orbits[17]" "orbits[17]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2812c08 .param/l "i" 3 258, +C4<010001>;
+S_0x2813020 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2812ef0;
+ .timescale -9 -12;
+L_0x2afec50/d .functor NOR 1, L_0x2affcd0, L_0x2afeac0, C4<0>, C4<0>;
+L_0x2afec50 .delay (10000,10000,10000) L_0x2afec50/d;
+L_0x2afed40/d .functor NOT 1, L_0x2afec50, C4<0>, C4<0>, C4<0>;
+L_0x2afed40 .delay (10000,10000,10000) L_0x2afed40/d;
+L_0x2afee30/d .functor NAND 1, L_0x2affcd0, L_0x2afeac0, C4<1>, C4<1>;
+L_0x2afee30 .delay (10000,10000,10000) L_0x2afee30/d;
+L_0x2afef70/d .functor NAND 1, L_0x2afee30, L_0x2afed40, C4<1>, C4<1>;
+L_0x2afef70 .delay (10000,10000,10000) L_0x2afef70/d;
+L_0x2aff060/d .functor NOT 1, L_0x2afef70, C4<0>, C4<0>, C4<0>;
+L_0x2aff060 .delay (10000,10000,10000) L_0x2aff060/d;
+v0x2813bd0_0 .net "A", 0 0, L_0x2affcd0; 1 drivers
+v0x2813c70_0 .net "AnandB", 0 0, L_0x2afee30; 1 drivers
+v0x2813d10_0 .net "AnorB", 0 0, L_0x2afec50; 1 drivers
+v0x2813dc0_0 .net "AorB", 0 0, L_0x2afed40; 1 drivers
+v0x2813ea0_0 .net "AxorB", 0 0, L_0x2aff060; 1 drivers
+v0x2813f50_0 .net "B", 0 0, L_0x2afeac0; 1 drivers
+v0x2814010_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2814090_0 .net "OrNorXorOut", 0 0, L_0x2aff9c0; 1 drivers
+v0x2814110_0 .net "XorNor", 0 0, L_0x2aff460; 1 drivers
+v0x28141e0_0 .net "nXor", 0 0, L_0x2afef70; 1 drivers
+L_0x2aff5c0 .part v0x2960210_0, 2, 1;
+L_0x2affb90 .part v0x2960210_0, 0, 1;
+S_0x2813660 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2813020;
+ .timescale -9 -12;
+L_0x2aff1a0/d .functor NOT 1, L_0x2aff5c0, C4<0>, C4<0>, C4<0>;
+L_0x2aff1a0 .delay (10000,10000,10000) L_0x2aff1a0/d;
+L_0x2aff240/d .functor AND 1, L_0x2aff060, L_0x2aff1a0, C4<1>, C4<1>;
+L_0x2aff240 .delay (20000,20000,20000) L_0x2aff240/d;
+L_0x2aff330/d .functor AND 1, L_0x2afec50, L_0x2aff5c0, C4<1>, C4<1>;
+L_0x2aff330 .delay (20000,20000,20000) L_0x2aff330/d;
+L_0x2aff460/d .functor OR 1, L_0x2aff240, L_0x2aff330, C4<0>, C4<0>;
+L_0x2aff460 .delay (20000,20000,20000) L_0x2aff460/d;
+v0x2813750_0 .net "S", 0 0, L_0x2aff5c0; 1 drivers
+v0x2813810_0 .alias "in0", 0 0, v0x2813ea0_0;
+v0x28138b0_0 .alias "in1", 0 0, v0x2813d10_0;
+v0x2813950_0 .net "nS", 0 0, L_0x2aff1a0; 1 drivers
+v0x28139d0_0 .net "out0", 0 0, L_0x2aff240; 1 drivers
+v0x2813a70_0 .net "out1", 0 0, L_0x2aff330; 1 drivers
+v0x2813b50_0 .alias "outfinal", 0 0, v0x2814110_0;
+S_0x2813110 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2813020;
+ .timescale -9 -12;
+L_0x2aff660/d .functor NOT 1, L_0x2affb90, C4<0>, C4<0>, C4<0>;
+L_0x2aff660 .delay (10000,10000,10000) L_0x2aff660/d;
+L_0x2aff720/d .functor AND 1, L_0x2aff460, L_0x2aff660, C4<1>, C4<1>;
+L_0x2aff720 .delay (20000,20000,20000) L_0x2aff720/d;
+L_0x2aff870/d .functor AND 1, L_0x2afed40, L_0x2affb90, C4<1>, C4<1>;
+L_0x2aff870 .delay (20000,20000,20000) L_0x2aff870/d;
+L_0x2aff9c0/d .functor OR 1, L_0x2aff720, L_0x2aff870, C4<0>, C4<0>;
+L_0x2aff9c0 .delay (20000,20000,20000) L_0x2aff9c0/d;
+v0x2813200_0 .net "S", 0 0, L_0x2affb90; 1 drivers
+v0x2813280_0 .alias "in0", 0 0, v0x2814110_0;
+v0x2813320_0 .alias "in1", 0 0, v0x2813dc0_0;
+v0x28133c0_0 .net "nS", 0 0, L_0x2aff660; 1 drivers
+v0x2813440_0 .net "out0", 0 0, L_0x2aff720; 1 drivers
+v0x28134e0_0 .net "out1", 0 0, L_0x2aff870; 1 drivers
+v0x28135c0_0 .alias "outfinal", 0 0, v0x2814090_0;
+S_0x2811b20 .scope generate, "orbits[18]" "orbits[18]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2811838 .param/l "i" 3 258, +C4<010010>;
+S_0x2811c50 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2811b20;
+ .timescale -9 -12;
+L_0x2afeb60/d .functor NOR 1, L_0x2affd70, L_0x2affe10, C4<0>, C4<0>;
+L_0x2afeb60 .delay (10000,10000,10000) L_0x2afeb60/d;
+L_0x2afff10/d .functor NOT 1, L_0x2afeb60, C4<0>, C4<0>, C4<0>;
+L_0x2afff10 .delay (10000,10000,10000) L_0x2afff10/d;
+L_0x2b00040/d .functor NAND 1, L_0x2affd70, L_0x2affe10, C4<1>, C4<1>;
+L_0x2b00040 .delay (10000,10000,10000) L_0x2b00040/d;
+L_0x2b001a0/d .functor NAND 1, L_0x2b00040, L_0x2afff10, C4<1>, C4<1>;
+L_0x2b001a0 .delay (10000,10000,10000) L_0x2b001a0/d;
+L_0x2b002b0/d .functor NOT 1, L_0x2b001a0, C4<0>, C4<0>, C4<0>;
+L_0x2b002b0 .delay (10000,10000,10000) L_0x2b002b0/d;
+v0x2812800_0 .net "A", 0 0, L_0x2affd70; 1 drivers
+v0x28128a0_0 .net "AnandB", 0 0, L_0x2b00040; 1 drivers
+v0x2812940_0 .net "AnorB", 0 0, L_0x2afeb60; 1 drivers
+v0x28129f0_0 .net "AorB", 0 0, L_0x2afff10; 1 drivers
+v0x2812ad0_0 .net "AxorB", 0 0, L_0x2b002b0; 1 drivers
+v0x2812b80_0 .net "B", 0 0, L_0x2affe10; 1 drivers
+v0x2812c40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2812cc0_0 .net "OrNorXorOut", 0 0, L_0x2b00cb0; 1 drivers
+v0x2812d40_0 .net "XorNor", 0 0, L_0x2b00730; 1 drivers
+v0x2812e10_0 .net "nXor", 0 0, L_0x2b001a0; 1 drivers
+L_0x2b008b0 .part v0x2960210_0, 2, 1;
+L_0x2b00e80 .part v0x2960210_0, 0, 1;
+S_0x2812290 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2811c50;
+ .timescale -9 -12;
+L_0x2b00410/d .functor NOT 1, L_0x2b008b0, C4<0>, C4<0>, C4<0>;
+L_0x2b00410 .delay (10000,10000,10000) L_0x2b00410/d;
+L_0x2b004d0/d .functor AND 1, L_0x2b002b0, L_0x2b00410, C4<1>, C4<1>;
+L_0x2b004d0 .delay (20000,20000,20000) L_0x2b004d0/d;
+L_0x2b005e0/d .functor AND 1, L_0x2afeb60, L_0x2b008b0, C4<1>, C4<1>;
+L_0x2b005e0 .delay (20000,20000,20000) L_0x2b005e0/d;
+L_0x2b00730/d .functor OR 1, L_0x2b004d0, L_0x2b005e0, C4<0>, C4<0>;
+L_0x2b00730 .delay (20000,20000,20000) L_0x2b00730/d;
+v0x2812380_0 .net "S", 0 0, L_0x2b008b0; 1 drivers
+v0x2812440_0 .alias "in0", 0 0, v0x2812ad0_0;
+v0x28124e0_0 .alias "in1", 0 0, v0x2812940_0;
+v0x2812580_0 .net "nS", 0 0, L_0x2b00410; 1 drivers
+v0x2812600_0 .net "out0", 0 0, L_0x2b004d0; 1 drivers
+v0x28126a0_0 .net "out1", 0 0, L_0x2b005e0; 1 drivers
+v0x2812780_0 .alias "outfinal", 0 0, v0x2812d40_0;
+S_0x2811d40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2811c50;
+ .timescale -9 -12;
+L_0x2b00950/d .functor NOT 1, L_0x2b00e80, C4<0>, C4<0>, C4<0>;
+L_0x2b00950 .delay (10000,10000,10000) L_0x2b00950/d;
+L_0x2b00a10/d .functor AND 1, L_0x2b00730, L_0x2b00950, C4<1>, C4<1>;
+L_0x2b00a10 .delay (20000,20000,20000) L_0x2b00a10/d;
+L_0x2b00b60/d .functor AND 1, L_0x2afff10, L_0x2b00e80, C4<1>, C4<1>;
+L_0x2b00b60 .delay (20000,20000,20000) L_0x2b00b60/d;
+L_0x2b00cb0/d .functor OR 1, L_0x2b00a10, L_0x2b00b60, C4<0>, C4<0>;
+L_0x2b00cb0 .delay (20000,20000,20000) L_0x2b00cb0/d;
+v0x2811e30_0 .net "S", 0 0, L_0x2b00e80; 1 drivers
+v0x2811eb0_0 .alias "in0", 0 0, v0x2812d40_0;
+v0x2811f50_0 .alias "in1", 0 0, v0x28129f0_0;
+v0x2811ff0_0 .net "nS", 0 0, L_0x2b00950; 1 drivers
+v0x2812070_0 .net "out0", 0 0, L_0x2b00a10; 1 drivers
+v0x2812110_0 .net "out1", 0 0, L_0x2b00b60; 1 drivers
+v0x28121f0_0 .alias "outfinal", 0 0, v0x2812cc0_0;
+S_0x2810750 .scope generate, "orbits[19]" "orbits[19]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2810468 .param/l "i" 3 258, +C4<010011>;
+S_0x2810880 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2810750;
+ .timescale -9 -12;
+L_0x2affeb0/d .functor NOR 1, L_0x2a01250, L_0x2a00140, C4<0>, C4<0>;
+L_0x2affeb0 .delay (10000,10000,10000) L_0x2affeb0/d;
+L_0x2b01050/d .functor NOT 1, L_0x2affeb0, C4<0>, C4<0>, C4<0>;
+L_0x2b01050 .delay (10000,10000,10000) L_0x2b01050/d;
+L_0x2b01110/d .functor NAND 1, L_0x2a01250, L_0x2a00140, C4<1>, C4<1>;
+L_0x2b01110 .delay (10000,10000,10000) L_0x2b01110/d;
+L_0x2a00430/d .functor NAND 1, L_0x2b01110, L_0x2b01050, C4<1>, C4<1>;
+L_0x2a00430 .delay (10000,10000,10000) L_0x2a00430/d;
+L_0x2a00540/d .functor NOT 1, L_0x2a00430, C4<0>, C4<0>, C4<0>;
+L_0x2a00540 .delay (10000,10000,10000) L_0x2a00540/d;
+v0x2811430_0 .net "A", 0 0, L_0x2a01250; 1 drivers
+v0x28114d0_0 .net "AnandB", 0 0, L_0x2b01110; 1 drivers
+v0x2811570_0 .net "AnorB", 0 0, L_0x2affeb0; 1 drivers
+v0x2811620_0 .net "AorB", 0 0, L_0x2b01050; 1 drivers
+v0x2811700_0 .net "AxorB", 0 0, L_0x2a00540; 1 drivers
+v0x28117b0_0 .net "B", 0 0, L_0x2a00140; 1 drivers
+v0x2811870_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28118f0_0 .net "OrNorXorOut", 0 0, L_0x2a00f40; 1 drivers
+v0x2811970_0 .net "XorNor", 0 0, L_0x2a009c0; 1 drivers
+v0x2811a40_0 .net "nXor", 0 0, L_0x2a00430; 1 drivers
+L_0x2a00b40 .part v0x2960210_0, 2, 1;
+L_0x2a01110 .part v0x2960210_0, 0, 1;
+S_0x2810ec0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2810880;
+ .timescale -9 -12;
+L_0x2a006a0/d .functor NOT 1, L_0x2a00b40, C4<0>, C4<0>, C4<0>;
+L_0x2a006a0 .delay (10000,10000,10000) L_0x2a006a0/d;
+L_0x2a00760/d .functor AND 1, L_0x2a00540, L_0x2a006a0, C4<1>, C4<1>;
+L_0x2a00760 .delay (20000,20000,20000) L_0x2a00760/d;
+L_0x2a00870/d .functor AND 1, L_0x2affeb0, L_0x2a00b40, C4<1>, C4<1>;
+L_0x2a00870 .delay (20000,20000,20000) L_0x2a00870/d;
+L_0x2a009c0/d .functor OR 1, L_0x2a00760, L_0x2a00870, C4<0>, C4<0>;
+L_0x2a009c0 .delay (20000,20000,20000) L_0x2a009c0/d;
+v0x2810fb0_0 .net "S", 0 0, L_0x2a00b40; 1 drivers
+v0x2811070_0 .alias "in0", 0 0, v0x2811700_0;
+v0x2811110_0 .alias "in1", 0 0, v0x2811570_0;
+v0x28111b0_0 .net "nS", 0 0, L_0x2a006a0; 1 drivers
+v0x2811230_0 .net "out0", 0 0, L_0x2a00760; 1 drivers
+v0x28112d0_0 .net "out1", 0 0, L_0x2a00870; 1 drivers
+v0x28113b0_0 .alias "outfinal", 0 0, v0x2811970_0;
+S_0x2810970 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2810880;
+ .timescale -9 -12;
+L_0x2a00be0/d .functor NOT 1, L_0x2a01110, C4<0>, C4<0>, C4<0>;
+L_0x2a00be0 .delay (10000,10000,10000) L_0x2a00be0/d;
+L_0x2a00ca0/d .functor AND 1, L_0x2a009c0, L_0x2a00be0, C4<1>, C4<1>;
+L_0x2a00ca0 .delay (20000,20000,20000) L_0x2a00ca0/d;
+L_0x2a00df0/d .functor AND 1, L_0x2b01050, L_0x2a01110, C4<1>, C4<1>;
+L_0x2a00df0 .delay (20000,20000,20000) L_0x2a00df0/d;
+L_0x2a00f40/d .functor OR 1, L_0x2a00ca0, L_0x2a00df0, C4<0>, C4<0>;
+L_0x2a00f40 .delay (20000,20000,20000) L_0x2a00f40/d;
+v0x2810a60_0 .net "S", 0 0, L_0x2a01110; 1 drivers
+v0x2810ae0_0 .alias "in0", 0 0, v0x2811970_0;
+v0x2810b80_0 .alias "in1", 0 0, v0x2811620_0;
+v0x2810c20_0 .net "nS", 0 0, L_0x2a00be0; 1 drivers
+v0x2810ca0_0 .net "out0", 0 0, L_0x2a00ca0; 1 drivers
+v0x2810d40_0 .net "out1", 0 0, L_0x2a00df0; 1 drivers
+v0x2810e20_0 .alias "outfinal", 0 0, v0x28118f0_0;
+S_0x280f380 .scope generate, "orbits[20]" "orbits[20]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x280f098 .param/l "i" 3 258, +C4<010100>;
+S_0x280f4b0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280f380;
+ .timescale -9 -12;
+L_0x2a001e0/d .functor NOR 1, L_0x2a012f0, L_0x2a01390, C4<0>, C4<0>;
+L_0x2a001e0 .delay (10000,10000,10000) L_0x2a001e0/d;
+L_0x2a014c0/d .functor NOT 1, L_0x2a001e0, C4<0>, C4<0>, C4<0>;
+L_0x2a014c0 .delay (10000,10000,10000) L_0x2a014c0/d;
+L_0x2a015f0/d .functor NAND 1, L_0x2a012f0, L_0x2a01390, C4<1>, C4<1>;
+L_0x2a015f0 .delay (10000,10000,10000) L_0x2a015f0/d;
+L_0x2a01750/d .functor NAND 1, L_0x2a015f0, L_0x2a014c0, C4<1>, C4<1>;
+L_0x2a01750 .delay (10000,10000,10000) L_0x2a01750/d;
+L_0x2a01860/d .functor NOT 1, L_0x2a01750, C4<0>, C4<0>, C4<0>;
+L_0x2a01860 .delay (10000,10000,10000) L_0x2a01860/d;
+v0x2810060_0 .net "A", 0 0, L_0x2a012f0; 1 drivers
+v0x2810100_0 .net "AnandB", 0 0, L_0x2a015f0; 1 drivers
+v0x28101a0_0 .net "AnorB", 0 0, L_0x2a001e0; 1 drivers
+v0x2810250_0 .net "AorB", 0 0, L_0x2a014c0; 1 drivers
+v0x2810330_0 .net "AxorB", 0 0, L_0x2a01860; 1 drivers
+v0x28103e0_0 .net "B", 0 0, L_0x2a01390; 1 drivers
+v0x28104a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2810520_0 .net "OrNorXorOut", 0 0, L_0x2b05280; 1 drivers
+v0x28105a0_0 .net "XorNor", 0 0, L_0x2a01ce0; 1 drivers
+v0x2810670_0 .net "nXor", 0 0, L_0x2a01750; 1 drivers
+L_0x2a01e60 .part v0x2960210_0, 2, 1;
+L_0x2b05430 .part v0x2960210_0, 0, 1;
+S_0x280faf0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280f4b0;
+ .timescale -9 -12;
+L_0x2a019c0/d .functor NOT 1, L_0x2a01e60, C4<0>, C4<0>, C4<0>;
+L_0x2a019c0 .delay (10000,10000,10000) L_0x2a019c0/d;
+L_0x2a01a80/d .functor AND 1, L_0x2a01860, L_0x2a019c0, C4<1>, C4<1>;
+L_0x2a01a80 .delay (20000,20000,20000) L_0x2a01a80/d;
+L_0x2a01b90/d .functor AND 1, L_0x2a001e0, L_0x2a01e60, C4<1>, C4<1>;
+L_0x2a01b90 .delay (20000,20000,20000) L_0x2a01b90/d;
+L_0x2a01ce0/d .functor OR 1, L_0x2a01a80, L_0x2a01b90, C4<0>, C4<0>;
+L_0x2a01ce0 .delay (20000,20000,20000) L_0x2a01ce0/d;
+v0x280fbe0_0 .net "S", 0 0, L_0x2a01e60; 1 drivers
+v0x280fca0_0 .alias "in0", 0 0, v0x2810330_0;
+v0x280fd40_0 .alias "in1", 0 0, v0x28101a0_0;
+v0x280fde0_0 .net "nS", 0 0, L_0x2a019c0; 1 drivers
+v0x280fe60_0 .net "out0", 0 0, L_0x2a01a80; 1 drivers
+v0x280ff00_0 .net "out1", 0 0, L_0x2a01b90; 1 drivers
+v0x280ffe0_0 .alias "outfinal", 0 0, v0x28105a0_0;
+S_0x280f5a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280f4b0;
+ .timescale -9 -12;
+L_0x2a01f00/d .functor NOT 1, L_0x2b05430, C4<0>, C4<0>, C4<0>;
+L_0x2a01f00 .delay (10000,10000,10000) L_0x2a01f00/d;
+L_0x2a01fc0/d .functor AND 1, L_0x2a01ce0, L_0x2a01f00, C4<1>, C4<1>;
+L_0x2a01fc0 .delay (20000,20000,20000) L_0x2a01fc0/d;
+L_0x2b05190/d .functor AND 1, L_0x2a014c0, L_0x2b05430, C4<1>, C4<1>;
+L_0x2b05190 .delay (20000,20000,20000) L_0x2b05190/d;
+L_0x2b05280/d .functor OR 1, L_0x2a01fc0, L_0x2b05190, C4<0>, C4<0>;
+L_0x2b05280 .delay (20000,20000,20000) L_0x2b05280/d;
+v0x280f690_0 .net "S", 0 0, L_0x2b05430; 1 drivers
+v0x280f710_0 .alias "in0", 0 0, v0x28105a0_0;
+v0x280f7b0_0 .alias "in1", 0 0, v0x2810250_0;
+v0x280f850_0 .net "nS", 0 0, L_0x2a01f00; 1 drivers
+v0x280f8d0_0 .net "out0", 0 0, L_0x2a01fc0; 1 drivers
+v0x280f970_0 .net "out1", 0 0, L_0x2b05190; 1 drivers
+v0x280fa50_0 .alias "outfinal", 0 0, v0x2810520_0;
+S_0x280dfb0 .scope generate, "orbits[21]" "orbits[21]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x280dcc8 .param/l "i" 3 258, +C4<010101>;
+S_0x280e0e0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280dfb0;
+ .timescale -9 -12;
+L_0x2a01430/d .functor NOR 1, L_0x2b06880, L_0x2b05570, C4<0>, C4<0>;
+L_0x2a01430 .delay (10000,10000,10000) L_0x2a01430/d;
+L_0x2b057f0/d .functor NOT 1, L_0x2a01430, C4<0>, C4<0>, C4<0>;
+L_0x2b057f0 .delay (10000,10000,10000) L_0x2b057f0/d;
+L_0x2b05900/d .functor NAND 1, L_0x2b06880, L_0x2b05570, C4<1>, C4<1>;
+L_0x2b05900 .delay (10000,10000,10000) L_0x2b05900/d;
+L_0x2b05a60/d .functor NAND 1, L_0x2b05900, L_0x2b057f0, C4<1>, C4<1>;
+L_0x2b05a60 .delay (10000,10000,10000) L_0x2b05a60/d;
+L_0x2b05b70/d .functor NOT 1, L_0x2b05a60, C4<0>, C4<0>, C4<0>;
+L_0x2b05b70 .delay (10000,10000,10000) L_0x2b05b70/d;
+v0x280ec90_0 .net "A", 0 0, L_0x2b06880; 1 drivers
+v0x280ed30_0 .net "AnandB", 0 0, L_0x2b05900; 1 drivers
+v0x280edd0_0 .net "AnorB", 0 0, L_0x2a01430; 1 drivers
+v0x280ee80_0 .net "AorB", 0 0, L_0x2b057f0; 1 drivers
+v0x280ef60_0 .net "AxorB", 0 0, L_0x2b05b70; 1 drivers
+v0x280f010_0 .net "B", 0 0, L_0x2b05570; 1 drivers
+v0x280f0d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x280f150_0 .net "OrNorXorOut", 0 0, L_0x2b06570; 1 drivers
+v0x280f1d0_0 .net "XorNor", 0 0, L_0x2b05ff0; 1 drivers
+v0x280f2a0_0 .net "nXor", 0 0, L_0x2b05a60; 1 drivers
+L_0x2b06170 .part v0x2960210_0, 2, 1;
+L_0x2b06740 .part v0x2960210_0, 0, 1;
+S_0x280e720 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280e0e0;
+ .timescale -9 -12;
+L_0x2b05cd0/d .functor NOT 1, L_0x2b06170, C4<0>, C4<0>, C4<0>;
+L_0x2b05cd0 .delay (10000,10000,10000) L_0x2b05cd0/d;
+L_0x2b05d90/d .functor AND 1, L_0x2b05b70, L_0x2b05cd0, C4<1>, C4<1>;
+L_0x2b05d90 .delay (20000,20000,20000) L_0x2b05d90/d;
+L_0x2b05ea0/d .functor AND 1, L_0x2a01430, L_0x2b06170, C4<1>, C4<1>;
+L_0x2b05ea0 .delay (20000,20000,20000) L_0x2b05ea0/d;
+L_0x2b05ff0/d .functor OR 1, L_0x2b05d90, L_0x2b05ea0, C4<0>, C4<0>;
+L_0x2b05ff0 .delay (20000,20000,20000) L_0x2b05ff0/d;
+v0x280e810_0 .net "S", 0 0, L_0x2b06170; 1 drivers
+v0x280e8d0_0 .alias "in0", 0 0, v0x280ef60_0;
+v0x280e970_0 .alias "in1", 0 0, v0x280edd0_0;
+v0x280ea10_0 .net "nS", 0 0, L_0x2b05cd0; 1 drivers
+v0x280ea90_0 .net "out0", 0 0, L_0x2b05d90; 1 drivers
+v0x280eb30_0 .net "out1", 0 0, L_0x2b05ea0; 1 drivers
+v0x280ec10_0 .alias "outfinal", 0 0, v0x280f1d0_0;
+S_0x280e1d0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280e0e0;
+ .timescale -9 -12;
+L_0x2b06210/d .functor NOT 1, L_0x2b06740, C4<0>, C4<0>, C4<0>;
+L_0x2b06210 .delay (10000,10000,10000) L_0x2b06210/d;
+L_0x2b062d0/d .functor AND 1, L_0x2b05ff0, L_0x2b06210, C4<1>, C4<1>;
+L_0x2b062d0 .delay (20000,20000,20000) L_0x2b062d0/d;
+L_0x2b06420/d .functor AND 1, L_0x2b057f0, L_0x2b06740, C4<1>, C4<1>;
+L_0x2b06420 .delay (20000,20000,20000) L_0x2b06420/d;
+L_0x2b06570/d .functor OR 1, L_0x2b062d0, L_0x2b06420, C4<0>, C4<0>;
+L_0x2b06570 .delay (20000,20000,20000) L_0x2b06570/d;
+v0x280e2c0_0 .net "S", 0 0, L_0x2b06740; 1 drivers
+v0x280e340_0 .alias "in0", 0 0, v0x280f1d0_0;
+v0x280e3e0_0 .alias "in1", 0 0, v0x280ee80_0;
+v0x280e480_0 .net "nS", 0 0, L_0x2b06210; 1 drivers
+v0x280e500_0 .net "out0", 0 0, L_0x2b062d0; 1 drivers
+v0x280e5a0_0 .net "out1", 0 0, L_0x2b06420; 1 drivers
+v0x280e680_0 .alias "outfinal", 0 0, v0x280f150_0;
+S_0x280cbe0 .scope generate, "orbits[22]" "orbits[22]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x280c8f8 .param/l "i" 3 258, +C4<010110>;
+S_0x280cd10 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280cbe0;
+ .timescale -9 -12;
+L_0x2b05610/d .functor NOR 1, L_0x2b06920, L_0x2b069c0, C4<0>, C4<0>;
+L_0x2b05610 .delay (10000,10000,10000) L_0x2b05610/d;
+L_0x2b05700/d .functor NOT 1, L_0x2b05610, C4<0>, C4<0>, C4<0>;
+L_0x2b05700 .delay (10000,10000,10000) L_0x2b05700/d;
+L_0x2b06bf0/d .functor NAND 1, L_0x2b06920, L_0x2b069c0, C4<1>, C4<1>;
+L_0x2b06bf0 .delay (10000,10000,10000) L_0x2b06bf0/d;
+L_0x2b06d50/d .functor NAND 1, L_0x2b06bf0, L_0x2b05700, C4<1>, C4<1>;
+L_0x2b06d50 .delay (10000,10000,10000) L_0x2b06d50/d;
+L_0x2b06e60/d .functor NOT 1, L_0x2b06d50, C4<0>, C4<0>, C4<0>;
+L_0x2b06e60 .delay (10000,10000,10000) L_0x2b06e60/d;
+v0x280d8c0_0 .net "A", 0 0, L_0x2b06920; 1 drivers
+v0x280d960_0 .net "AnandB", 0 0, L_0x2b06bf0; 1 drivers
+v0x280da00_0 .net "AnorB", 0 0, L_0x2b05610; 1 drivers
+v0x280dab0_0 .net "AorB", 0 0, L_0x2b05700; 1 drivers
+v0x280db90_0 .net "AxorB", 0 0, L_0x2b06e60; 1 drivers
+v0x280dc40_0 .net "B", 0 0, L_0x2b069c0; 1 drivers
+v0x280dd00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x280dd80_0 .net "OrNorXorOut", 0 0, L_0x2b07860; 1 drivers
+v0x280de00_0 .net "XorNor", 0 0, L_0x2b072e0; 1 drivers
+v0x280ded0_0 .net "nXor", 0 0, L_0x2b06d50; 1 drivers
+L_0x2b07460 .part v0x2960210_0, 2, 1;
+L_0x2b07a30 .part v0x2960210_0, 0, 1;
+S_0x280d350 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280cd10;
+ .timescale -9 -12;
+L_0x2b06fc0/d .functor NOT 1, L_0x2b07460, C4<0>, C4<0>, C4<0>;
+L_0x2b06fc0 .delay (10000,10000,10000) L_0x2b06fc0/d;
+L_0x2b07080/d .functor AND 1, L_0x2b06e60, L_0x2b06fc0, C4<1>, C4<1>;
+L_0x2b07080 .delay (20000,20000,20000) L_0x2b07080/d;
+L_0x2b07190/d .functor AND 1, L_0x2b05610, L_0x2b07460, C4<1>, C4<1>;
+L_0x2b07190 .delay (20000,20000,20000) L_0x2b07190/d;
+L_0x2b072e0/d .functor OR 1, L_0x2b07080, L_0x2b07190, C4<0>, C4<0>;
+L_0x2b072e0 .delay (20000,20000,20000) L_0x2b072e0/d;
+v0x280d440_0 .net "S", 0 0, L_0x2b07460; 1 drivers
+v0x280d500_0 .alias "in0", 0 0, v0x280db90_0;
+v0x280d5a0_0 .alias "in1", 0 0, v0x280da00_0;
+v0x280d640_0 .net "nS", 0 0, L_0x2b06fc0; 1 drivers
+v0x280d6c0_0 .net "out0", 0 0, L_0x2b07080; 1 drivers
+v0x280d760_0 .net "out1", 0 0, L_0x2b07190; 1 drivers
+v0x280d840_0 .alias "outfinal", 0 0, v0x280de00_0;
+S_0x280ce00 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280cd10;
+ .timescale -9 -12;
+L_0x2b07500/d .functor NOT 1, L_0x2b07a30, C4<0>, C4<0>, C4<0>;
+L_0x2b07500 .delay (10000,10000,10000) L_0x2b07500/d;
+L_0x2b075c0/d .functor AND 1, L_0x2b072e0, L_0x2b07500, C4<1>, C4<1>;
+L_0x2b075c0 .delay (20000,20000,20000) L_0x2b075c0/d;
+L_0x2b07710/d .functor AND 1, L_0x2b05700, L_0x2b07a30, C4<1>, C4<1>;
+L_0x2b07710 .delay (20000,20000,20000) L_0x2b07710/d;
+L_0x2b07860/d .functor OR 1, L_0x2b075c0, L_0x2b07710, C4<0>, C4<0>;
+L_0x2b07860 .delay (20000,20000,20000) L_0x2b07860/d;
+v0x280cef0_0 .net "S", 0 0, L_0x2b07a30; 1 drivers
+v0x280cf70_0 .alias "in0", 0 0, v0x280de00_0;
+v0x280d010_0 .alias "in1", 0 0, v0x280dab0_0;
+v0x280d0b0_0 .net "nS", 0 0, L_0x2b07500; 1 drivers
+v0x280d130_0 .net "out0", 0 0, L_0x2b075c0; 1 drivers
+v0x280d1d0_0 .net "out1", 0 0, L_0x2b07710; 1 drivers
+v0x280d2b0_0 .alias "outfinal", 0 0, v0x280dd80_0;
+S_0x280b810 .scope generate, "orbits[23]" "orbits[23]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x280b528 .param/l "i" 3 258, +C4<010111>;
+S_0x280b940 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280b810;
+ .timescale -9 -12;
+L_0x2b06a60/d .functor NOR 1, L_0x2b08e70, L_0x2b07b70, C4<0>, C4<0>;
+L_0x2b06a60 .delay (10000,10000,10000) L_0x2b06a60/d;
+L_0x2b07de0/d .functor NOT 1, L_0x2b06a60, C4<0>, C4<0>, C4<0>;
+L_0x2b07de0 .delay (10000,10000,10000) L_0x2b07de0/d;
+L_0x2b07ef0/d .functor NAND 1, L_0x2b08e70, L_0x2b07b70, C4<1>, C4<1>;
+L_0x2b07ef0 .delay (10000,10000,10000) L_0x2b07ef0/d;
+L_0x2b08050/d .functor NAND 1, L_0x2b07ef0, L_0x2b07de0, C4<1>, C4<1>;
+L_0x2b08050 .delay (10000,10000,10000) L_0x2b08050/d;
+L_0x2b08160/d .functor NOT 1, L_0x2b08050, C4<0>, C4<0>, C4<0>;
+L_0x2b08160 .delay (10000,10000,10000) L_0x2b08160/d;
+v0x280c4f0_0 .net "A", 0 0, L_0x2b08e70; 1 drivers
+v0x280c590_0 .net "AnandB", 0 0, L_0x2b07ef0; 1 drivers
+v0x280c630_0 .net "AnorB", 0 0, L_0x2b06a60; 1 drivers
+v0x280c6e0_0 .net "AorB", 0 0, L_0x2b07de0; 1 drivers
+v0x280c7c0_0 .net "AxorB", 0 0, L_0x2b08160; 1 drivers
+v0x280c870_0 .net "B", 0 0, L_0x2b07b70; 1 drivers
+v0x280c930_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x280c9b0_0 .net "OrNorXorOut", 0 0, L_0x2b08b60; 1 drivers
+v0x280ca30_0 .net "XorNor", 0 0, L_0x2b085e0; 1 drivers
+v0x280cb00_0 .net "nXor", 0 0, L_0x2b08050; 1 drivers
+L_0x2b08760 .part v0x2960210_0, 2, 1;
+L_0x2b08d30 .part v0x2960210_0, 0, 1;
+S_0x280bf80 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280b940;
+ .timescale -9 -12;
+L_0x2b082c0/d .functor NOT 1, L_0x2b08760, C4<0>, C4<0>, C4<0>;
+L_0x2b082c0 .delay (10000,10000,10000) L_0x2b082c0/d;
+L_0x2b08380/d .functor AND 1, L_0x2b08160, L_0x2b082c0, C4<1>, C4<1>;
+L_0x2b08380 .delay (20000,20000,20000) L_0x2b08380/d;
+L_0x2b08490/d .functor AND 1, L_0x2b06a60, L_0x2b08760, C4<1>, C4<1>;
+L_0x2b08490 .delay (20000,20000,20000) L_0x2b08490/d;
+L_0x2b085e0/d .functor OR 1, L_0x2b08380, L_0x2b08490, C4<0>, C4<0>;
+L_0x2b085e0 .delay (20000,20000,20000) L_0x2b085e0/d;
+v0x280c070_0 .net "S", 0 0, L_0x2b08760; 1 drivers
+v0x280c130_0 .alias "in0", 0 0, v0x280c7c0_0;
+v0x280c1d0_0 .alias "in1", 0 0, v0x280c630_0;
+v0x280c270_0 .net "nS", 0 0, L_0x2b082c0; 1 drivers
+v0x280c2f0_0 .net "out0", 0 0, L_0x2b08380; 1 drivers
+v0x280c390_0 .net "out1", 0 0, L_0x2b08490; 1 drivers
+v0x280c470_0 .alias "outfinal", 0 0, v0x280ca30_0;
+S_0x280ba30 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280b940;
+ .timescale -9 -12;
+L_0x2b08800/d .functor NOT 1, L_0x2b08d30, C4<0>, C4<0>, C4<0>;
+L_0x2b08800 .delay (10000,10000,10000) L_0x2b08800/d;
+L_0x2b088c0/d .functor AND 1, L_0x2b085e0, L_0x2b08800, C4<1>, C4<1>;
+L_0x2b088c0 .delay (20000,20000,20000) L_0x2b088c0/d;
+L_0x2b08a10/d .functor AND 1, L_0x2b07de0, L_0x2b08d30, C4<1>, C4<1>;
+L_0x2b08a10 .delay (20000,20000,20000) L_0x2b08a10/d;
+L_0x2b08b60/d .functor OR 1, L_0x2b088c0, L_0x2b08a10, C4<0>, C4<0>;
+L_0x2b08b60 .delay (20000,20000,20000) L_0x2b08b60/d;
+v0x280bb20_0 .net "S", 0 0, L_0x2b08d30; 1 drivers
+v0x280bba0_0 .alias "in0", 0 0, v0x280ca30_0;
+v0x280bc40_0 .alias "in1", 0 0, v0x280c6e0_0;
+v0x280bce0_0 .net "nS", 0 0, L_0x2b08800; 1 drivers
+v0x280bd60_0 .net "out0", 0 0, L_0x2b088c0; 1 drivers
+v0x280be00_0 .net "out1", 0 0, L_0x2b08a10; 1 drivers
+v0x280bee0_0 .alias "outfinal", 0 0, v0x280c9b0_0;
+S_0x280a440 .scope generate, "orbits[24]" "orbits[24]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x280a158 .param/l "i" 3 258, +C4<011000>;
+S_0x280a570 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x280a440;
+ .timescale -9 -12;
+L_0x2b07c10/d .functor NOR 1, L_0x2b08f10, L_0x2b08fb0, C4<0>, C4<0>;
+L_0x2b07c10 .delay (10000,10000,10000) L_0x2b07c10/d;
+L_0x2b07d00/d .functor NOT 1, L_0x2b07c10, C4<0>, C4<0>, C4<0>;
+L_0x2b07d00 .delay (10000,10000,10000) L_0x2b07d00/d;
+L_0x2b091f0/d .functor NAND 1, L_0x2b08f10, L_0x2b08fb0, C4<1>, C4<1>;
+L_0x2b091f0 .delay (10000,10000,10000) L_0x2b091f0/d;
+L_0x2b09350/d .functor NAND 1, L_0x2b091f0, L_0x2b07d00, C4<1>, C4<1>;
+L_0x2b09350 .delay (10000,10000,10000) L_0x2b09350/d;
+L_0x2b09460/d .functor NOT 1, L_0x2b09350, C4<0>, C4<0>, C4<0>;
+L_0x2b09460 .delay (10000,10000,10000) L_0x2b09460/d;
+v0x280b120_0 .net "A", 0 0, L_0x2b08f10; 1 drivers
+v0x280b1c0_0 .net "AnandB", 0 0, L_0x2b091f0; 1 drivers
+v0x280b260_0 .net "AnorB", 0 0, L_0x2b07c10; 1 drivers
+v0x280b310_0 .net "AorB", 0 0, L_0x2b07d00; 1 drivers
+v0x280b3f0_0 .net "AxorB", 0 0, L_0x2b09460; 1 drivers
+v0x280b4a0_0 .net "B", 0 0, L_0x2b08fb0; 1 drivers
+v0x280b560_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x280b5e0_0 .net "OrNorXorOut", 0 0, L_0x2b09e60; 1 drivers
+v0x280b660_0 .net "XorNor", 0 0, L_0x2b098e0; 1 drivers
+v0x280b730_0 .net "nXor", 0 0, L_0x2b09350; 1 drivers
+L_0x2b09a60 .part v0x2960210_0, 2, 1;
+L_0x2b0a030 .part v0x2960210_0, 0, 1;
+S_0x280abb0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x280a570;
+ .timescale -9 -12;
+L_0x2b095c0/d .functor NOT 1, L_0x2b09a60, C4<0>, C4<0>, C4<0>;
+L_0x2b095c0 .delay (10000,10000,10000) L_0x2b095c0/d;
+L_0x2b09680/d .functor AND 1, L_0x2b09460, L_0x2b095c0, C4<1>, C4<1>;
+L_0x2b09680 .delay (20000,20000,20000) L_0x2b09680/d;
+L_0x2b09790/d .functor AND 1, L_0x2b07c10, L_0x2b09a60, C4<1>, C4<1>;
+L_0x2b09790 .delay (20000,20000,20000) L_0x2b09790/d;
+L_0x2b098e0/d .functor OR 1, L_0x2b09680, L_0x2b09790, C4<0>, C4<0>;
+L_0x2b098e0 .delay (20000,20000,20000) L_0x2b098e0/d;
+v0x280aca0_0 .net "S", 0 0, L_0x2b09a60; 1 drivers
+v0x280ad60_0 .alias "in0", 0 0, v0x280b3f0_0;
+v0x280ae00_0 .alias "in1", 0 0, v0x280b260_0;
+v0x280aea0_0 .net "nS", 0 0, L_0x2b095c0; 1 drivers
+v0x280af20_0 .net "out0", 0 0, L_0x2b09680; 1 drivers
+v0x280afc0_0 .net "out1", 0 0, L_0x2b09790; 1 drivers
+v0x280b0a0_0 .alias "outfinal", 0 0, v0x280b660_0;
+S_0x280a660 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x280a570;
+ .timescale -9 -12;
+L_0x2b09b00/d .functor NOT 1, L_0x2b0a030, C4<0>, C4<0>, C4<0>;
+L_0x2b09b00 .delay (10000,10000,10000) L_0x2b09b00/d;
+L_0x2b09bc0/d .functor AND 1, L_0x2b098e0, L_0x2b09b00, C4<1>, C4<1>;
+L_0x2b09bc0 .delay (20000,20000,20000) L_0x2b09bc0/d;
+L_0x2b09d10/d .functor AND 1, L_0x2b07d00, L_0x2b0a030, C4<1>, C4<1>;
+L_0x2b09d10 .delay (20000,20000,20000) L_0x2b09d10/d;
+L_0x2b09e60/d .functor OR 1, L_0x2b09bc0, L_0x2b09d10, C4<0>, C4<0>;
+L_0x2b09e60 .delay (20000,20000,20000) L_0x2b09e60/d;
+v0x280a750_0 .net "S", 0 0, L_0x2b0a030; 1 drivers
+v0x280a7d0_0 .alias "in0", 0 0, v0x280b660_0;
+v0x280a870_0 .alias "in1", 0 0, v0x280b310_0;
+v0x280a910_0 .net "nS", 0 0, L_0x2b09b00; 1 drivers
+v0x280a990_0 .net "out0", 0 0, L_0x2b09bc0; 1 drivers
+v0x280aa30_0 .net "out1", 0 0, L_0x2b09d10; 1 drivers
+v0x280ab10_0 .alias "outfinal", 0 0, v0x280b5e0_0;
+S_0x2809070 .scope generate, "orbits[25]" "orbits[25]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2808d88 .param/l "i" 3 258, +C4<011001>;
+S_0x28091a0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2809070;
+ .timescale -9 -12;
+L_0x2b09050/d .functor NOR 1, L_0x2b0b470, L_0x2b0a170, C4<0>, C4<0>;
+L_0x2b09050 .delay (10000,10000,10000) L_0x2b09050/d;
+L_0x2b0a3c0/d .functor NOT 1, L_0x2b09050, C4<0>, C4<0>, C4<0>;
+L_0x2b0a3c0 .delay (10000,10000,10000) L_0x2b0a3c0/d;
+L_0x2b0a4f0/d .functor NAND 1, L_0x2b0b470, L_0x2b0a170, C4<1>, C4<1>;
+L_0x2b0a4f0 .delay (10000,10000,10000) L_0x2b0a4f0/d;
+L_0x2b0a650/d .functor NAND 1, L_0x2b0a4f0, L_0x2b0a3c0, C4<1>, C4<1>;
+L_0x2b0a650 .delay (10000,10000,10000) L_0x2b0a650/d;
+L_0x2b0a760/d .functor NOT 1, L_0x2b0a650, C4<0>, C4<0>, C4<0>;
+L_0x2b0a760 .delay (10000,10000,10000) L_0x2b0a760/d;
+v0x2809d50_0 .net "A", 0 0, L_0x2b0b470; 1 drivers
+v0x2809df0_0 .net "AnandB", 0 0, L_0x2b0a4f0; 1 drivers
+v0x2809e90_0 .net "AnorB", 0 0, L_0x2b09050; 1 drivers
+v0x2809f40_0 .net "AorB", 0 0, L_0x2b0a3c0; 1 drivers
+v0x280a020_0 .net "AxorB", 0 0, L_0x2b0a760; 1 drivers
+v0x280a0d0_0 .net "B", 0 0, L_0x2b0a170; 1 drivers
+v0x280a190_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x280a210_0 .net "OrNorXorOut", 0 0, L_0x2b0b160; 1 drivers
+v0x280a290_0 .net "XorNor", 0 0, L_0x2b0abe0; 1 drivers
+v0x280a360_0 .net "nXor", 0 0, L_0x2b0a650; 1 drivers
+L_0x2b0ad60 .part v0x2960210_0, 2, 1;
+L_0x2b0b330 .part v0x2960210_0, 0, 1;
+S_0x28097e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28091a0;
+ .timescale -9 -12;
+L_0x2b0a8c0/d .functor NOT 1, L_0x2b0ad60, C4<0>, C4<0>, C4<0>;
+L_0x2b0a8c0 .delay (10000,10000,10000) L_0x2b0a8c0/d;
+L_0x2b0a980/d .functor AND 1, L_0x2b0a760, L_0x2b0a8c0, C4<1>, C4<1>;
+L_0x2b0a980 .delay (20000,20000,20000) L_0x2b0a980/d;
+L_0x2b0aa90/d .functor AND 1, L_0x2b09050, L_0x2b0ad60, C4<1>, C4<1>;
+L_0x2b0aa90 .delay (20000,20000,20000) L_0x2b0aa90/d;
+L_0x2b0abe0/d .functor OR 1, L_0x2b0a980, L_0x2b0aa90, C4<0>, C4<0>;
+L_0x2b0abe0 .delay (20000,20000,20000) L_0x2b0abe0/d;
+v0x28098d0_0 .net "S", 0 0, L_0x2b0ad60; 1 drivers
+v0x2809990_0 .alias "in0", 0 0, v0x280a020_0;
+v0x2809a30_0 .alias "in1", 0 0, v0x2809e90_0;
+v0x2809ad0_0 .net "nS", 0 0, L_0x2b0a8c0; 1 drivers
+v0x2809b50_0 .net "out0", 0 0, L_0x2b0a980; 1 drivers
+v0x2809bf0_0 .net "out1", 0 0, L_0x2b0aa90; 1 drivers
+v0x2809cd0_0 .alias "outfinal", 0 0, v0x280a290_0;
+S_0x2809290 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28091a0;
+ .timescale -9 -12;
+L_0x2b0ae00/d .functor NOT 1, L_0x2b0b330, C4<0>, C4<0>, C4<0>;
+L_0x2b0ae00 .delay (10000,10000,10000) L_0x2b0ae00/d;
+L_0x2b0aec0/d .functor AND 1, L_0x2b0abe0, L_0x2b0ae00, C4<1>, C4<1>;
+L_0x2b0aec0 .delay (20000,20000,20000) L_0x2b0aec0/d;
+L_0x2b0b010/d .functor AND 1, L_0x2b0a3c0, L_0x2b0b330, C4<1>, C4<1>;
+L_0x2b0b010 .delay (20000,20000,20000) L_0x2b0b010/d;
+L_0x2b0b160/d .functor OR 1, L_0x2b0aec0, L_0x2b0b010, C4<0>, C4<0>;
+L_0x2b0b160 .delay (20000,20000,20000) L_0x2b0b160/d;
+v0x2809380_0 .net "S", 0 0, L_0x2b0b330; 1 drivers
+v0x2809400_0 .alias "in0", 0 0, v0x280a290_0;
+v0x28094a0_0 .alias "in1", 0 0, v0x2809f40_0;
+v0x2809540_0 .net "nS", 0 0, L_0x2b0ae00; 1 drivers
+v0x28095c0_0 .net "out0", 0 0, L_0x2b0aec0; 1 drivers
+v0x2809660_0 .net "out1", 0 0, L_0x2b0b010; 1 drivers
+v0x2809740_0 .alias "outfinal", 0 0, v0x280a210_0;
+S_0x2807cb0 .scope generate, "orbits[26]" "orbits[26]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2807978 .param/l "i" 3 258, +C4<011010>;
+S_0x2807de0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2807cb0;
+ .timescale -9 -12;
+L_0x2b0a210/d .functor NOR 1, L_0x2b0b510, L_0x2b0b5b0, C4<0>, C4<0>;
+L_0x2b0a210 .delay (10000,10000,10000) L_0x2b0a210/d;
+L_0x2b0a300/d .functor NOT 1, L_0x2b0a210, C4<0>, C4<0>, C4<0>;
+L_0x2b0a300 .delay (10000,10000,10000) L_0x2b0a300/d;
+L_0x2b0b7e0/d .functor NAND 1, L_0x2b0b510, L_0x2b0b5b0, C4<1>, C4<1>;
+L_0x2b0b7e0 .delay (10000,10000,10000) L_0x2b0b7e0/d;
+L_0x2b0b940/d .functor NAND 1, L_0x2b0b7e0, L_0x2b0a300, C4<1>, C4<1>;
+L_0x2b0b940 .delay (10000,10000,10000) L_0x2b0b940/d;
+L_0x2b0ba50/d .functor NOT 1, L_0x2b0b940, C4<0>, C4<0>, C4<0>;
+L_0x2b0ba50 .delay (10000,10000,10000) L_0x2b0ba50/d;
+v0x28089b0_0 .net "A", 0 0, L_0x2b0b510; 1 drivers
+v0x2808a50_0 .net "AnandB", 0 0, L_0x2b0b7e0; 1 drivers
+v0x2808af0_0 .net "AnorB", 0 0, L_0x2b0a210; 1 drivers
+v0x2808b70_0 .net "AorB", 0 0, L_0x2b0a300; 1 drivers
+v0x2808c50_0 .net "AxorB", 0 0, L_0x2b0ba50; 1 drivers
+v0x2808d00_0 .net "B", 0 0, L_0x2b0b5b0; 1 drivers
+v0x2808dc0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2808e40_0 .net "OrNorXorOut", 0 0, L_0x2b0c450; 1 drivers
+v0x2808ec0_0 .net "XorNor", 0 0, L_0x2b0bed0; 1 drivers
+v0x2808f90_0 .net "nXor", 0 0, L_0x2b0b940; 1 drivers
+L_0x2b0c050 .part v0x2960210_0, 2, 1;
+L_0x2b0c620 .part v0x2960210_0, 0, 1;
+S_0x2808440 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2807de0;
+ .timescale -9 -12;
+L_0x2b0bbb0/d .functor NOT 1, L_0x2b0c050, C4<0>, C4<0>, C4<0>;
+L_0x2b0bbb0 .delay (10000,10000,10000) L_0x2b0bbb0/d;
+L_0x2b0bc70/d .functor AND 1, L_0x2b0ba50, L_0x2b0bbb0, C4<1>, C4<1>;
+L_0x2b0bc70 .delay (20000,20000,20000) L_0x2b0bc70/d;
+L_0x2b0bd80/d .functor AND 1, L_0x2b0a210, L_0x2b0c050, C4<1>, C4<1>;
+L_0x2b0bd80 .delay (20000,20000,20000) L_0x2b0bd80/d;
+L_0x2b0bed0/d .functor OR 1, L_0x2b0bc70, L_0x2b0bd80, C4<0>, C4<0>;
+L_0x2b0bed0 .delay (20000,20000,20000) L_0x2b0bed0/d;
+v0x2808530_0 .net "S", 0 0, L_0x2b0c050; 1 drivers
+v0x28085f0_0 .alias "in0", 0 0, v0x2808c50_0;
+v0x2808690_0 .alias "in1", 0 0, v0x2808af0_0;
+v0x2808730_0 .net "nS", 0 0, L_0x2b0bbb0; 1 drivers
+v0x28087b0_0 .net "out0", 0 0, L_0x2b0bc70; 1 drivers
+v0x2808850_0 .net "out1", 0 0, L_0x2b0bd80; 1 drivers
+v0x2808930_0 .alias "outfinal", 0 0, v0x2808ec0_0;
+S_0x2807ed0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2807de0;
+ .timescale -9 -12;
+L_0x2b0c0f0/d .functor NOT 1, L_0x2b0c620, C4<0>, C4<0>, C4<0>;
+L_0x2b0c0f0 .delay (10000,10000,10000) L_0x2b0c0f0/d;
+L_0x2b0c1b0/d .functor AND 1, L_0x2b0bed0, L_0x2b0c0f0, C4<1>, C4<1>;
+L_0x2b0c1b0 .delay (20000,20000,20000) L_0x2b0c1b0/d;
+L_0x2b0c300/d .functor AND 1, L_0x2b0a300, L_0x2b0c620, C4<1>, C4<1>;
+L_0x2b0c300 .delay (20000,20000,20000) L_0x2b0c300/d;
+L_0x2b0c450/d .functor OR 1, L_0x2b0c1b0, L_0x2b0c300, C4<0>, C4<0>;
+L_0x2b0c450 .delay (20000,20000,20000) L_0x2b0c450/d;
+v0x2807fc0_0 .net "S", 0 0, L_0x2b0c620; 1 drivers
+v0x2808060_0 .alias "in0", 0 0, v0x2808ec0_0;
+v0x2808100_0 .alias "in1", 0 0, v0x2808b70_0;
+v0x28081a0_0 .net "nS", 0 0, L_0x2b0c0f0; 1 drivers
+v0x2808220_0 .net "out0", 0 0, L_0x2b0c1b0; 1 drivers
+v0x28082c0_0 .net "out1", 0 0, L_0x2b0c300; 1 drivers
+v0x28083a0_0 .alias "outfinal", 0 0, v0x2808e40_0;
+S_0x28068c0 .scope generate, "orbits[27]" "orbits[27]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x28065d8 .param/l "i" 3 258, +C4<011011>;
+S_0x28069f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28068c0;
+ .timescale -9 -12;
+L_0x2b0b650/d .functor NOR 1, L_0x2b0da90, L_0x2b0c760, C4<0>, C4<0>;
+L_0x2b0b650 .delay (10000,10000,10000) L_0x2b0b650/d;
+L_0x2b0c9e0/d .functor NOT 1, L_0x2b0b650, C4<0>, C4<0>, C4<0>;
+L_0x2b0c9e0 .delay (10000,10000,10000) L_0x2b0c9e0/d;
+L_0x2b0caf0/d .functor NAND 1, L_0x2b0da90, L_0x2b0c760, C4<1>, C4<1>;
+L_0x2b0caf0 .delay (10000,10000,10000) L_0x2b0caf0/d;
+L_0x2b0cc50/d .functor NAND 1, L_0x2b0caf0, L_0x2b0c9e0, C4<1>, C4<1>;
+L_0x2b0cc50 .delay (10000,10000,10000) L_0x2b0cc50/d;
+L_0x2b0cd60/d .functor NOT 1, L_0x2b0cc50, C4<0>, C4<0>, C4<0>;
+L_0x2b0cd60 .delay (10000,10000,10000) L_0x2b0cd60/d;
+v0x2807570_0 .net "A", 0 0, L_0x2b0da90; 1 drivers
+v0x2807610_0 .net "AnandB", 0 0, L_0x2b0caf0; 1 drivers
+v0x28076b0_0 .net "AnorB", 0 0, L_0x2b0b650; 1 drivers
+v0x2807760_0 .net "AorB", 0 0, L_0x2b0c9e0; 1 drivers
+v0x2807840_0 .net "AxorB", 0 0, L_0x2b0cd60; 1 drivers
+v0x28078f0_0 .net "B", 0 0, L_0x2b0c760; 1 drivers
+v0x28079b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2807a30_0 .net "OrNorXorOut", 0 0, L_0x2b0d780; 1 drivers
+v0x2807b00_0 .net "XorNor", 0 0, L_0x2b0d200; 1 drivers
+v0x2807bd0_0 .net "nXor", 0 0, L_0x2b0cc50; 1 drivers
+L_0x2b0d380 .part v0x2960210_0, 2, 1;
+L_0x2b0d950 .part v0x2960210_0, 0, 1;
+S_0x2807010 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x28069f0;
+ .timescale -9 -12;
+L_0x2b0cec0/d .functor NOT 1, L_0x2b0d380, C4<0>, C4<0>, C4<0>;
+L_0x2b0cec0 .delay (10000,10000,10000) L_0x2b0cec0/d;
+L_0x2b0cfa0/d .functor AND 1, L_0x2b0cd60, L_0x2b0cec0, C4<1>, C4<1>;
+L_0x2b0cfa0 .delay (20000,20000,20000) L_0x2b0cfa0/d;
+L_0x2b0d0b0/d .functor AND 1, L_0x2b0b650, L_0x2b0d380, C4<1>, C4<1>;
+L_0x2b0d0b0 .delay (20000,20000,20000) L_0x2b0d0b0/d;
+L_0x2b0d200/d .functor OR 1, L_0x2b0cfa0, L_0x2b0d0b0, C4<0>, C4<0>;
+L_0x2b0d200 .delay (20000,20000,20000) L_0x2b0d200/d;
+v0x2807100_0 .net "S", 0 0, L_0x2b0d380; 1 drivers
+v0x2807180_0 .alias "in0", 0 0, v0x2807840_0;
+v0x2807220_0 .alias "in1", 0 0, v0x28076b0_0;
+v0x28072c0_0 .net "nS", 0 0, L_0x2b0cec0; 1 drivers
+v0x2807370_0 .net "out0", 0 0, L_0x2b0cfa0; 1 drivers
+v0x2807410_0 .net "out1", 0 0, L_0x2b0d0b0; 1 drivers
+v0x28074f0_0 .alias "outfinal", 0 0, v0x2807b00_0;
+S_0x2806ae0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x28069f0;
+ .timescale -9 -12;
+L_0x2b0d420/d .functor NOT 1, L_0x2b0d950, C4<0>, C4<0>, C4<0>;
+L_0x2b0d420 .delay (10000,10000,10000) L_0x2b0d420/d;
+L_0x2b0d4e0/d .functor AND 1, L_0x2b0d200, L_0x2b0d420, C4<1>, C4<1>;
+L_0x2b0d4e0 .delay (20000,20000,20000) L_0x2b0d4e0/d;
+L_0x2b0d630/d .functor AND 1, L_0x2b0c9e0, L_0x2b0d950, C4<1>, C4<1>;
+L_0x2b0d630 .delay (20000,20000,20000) L_0x2b0d630/d;
+L_0x2b0d780/d .functor OR 1, L_0x2b0d4e0, L_0x2b0d630, C4<0>, C4<0>;
+L_0x2b0d780 .delay (20000,20000,20000) L_0x2b0d780/d;
+v0x2806bd0_0 .net "S", 0 0, L_0x2b0d950; 1 drivers
+v0x2806c50_0 .alias "in0", 0 0, v0x2807b00_0;
+v0x2806cf0_0 .alias "in1", 0 0, v0x2807760_0;
+v0x2806d90_0 .net "nS", 0 0, L_0x2b0d420; 1 drivers
+v0x2806e10_0 .net "out0", 0 0, L_0x2b0d4e0; 1 drivers
+v0x2806eb0_0 .net "out1", 0 0, L_0x2b0d630; 1 drivers
+v0x2806f90_0 .alias "outfinal", 0 0, v0x2807a30_0;
+S_0x28054f0 .scope generate, "orbits[28]" "orbits[28]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2805208 .param/l "i" 3 258, +C4<011100>;
+S_0x2805620 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28054f0;
+ .timescale -9 -12;
+L_0x2b0c800/d .functor NOR 1, L_0x2b0db30, L_0x2b0dbd0, C4<0>, C4<0>;
+L_0x2b0c800 .delay (10000,10000,10000) L_0x2b0c800/d;
+L_0x2b0c8f0/d .functor NOT 1, L_0x2b0c800, C4<0>, C4<0>, C4<0>;
+L_0x2b0c8f0 .delay (10000,10000,10000) L_0x2b0c8f0/d;
+L_0x2b0de10/d .functor NAND 1, L_0x2b0db30, L_0x2b0dbd0, C4<1>, C4<1>;
+L_0x2b0de10 .delay (10000,10000,10000) L_0x2b0de10/d;
+L_0x2b0df70/d .functor NAND 1, L_0x2b0de10, L_0x2b0c8f0, C4<1>, C4<1>;
+L_0x2b0df70 .delay (10000,10000,10000) L_0x2b0df70/d;
+L_0x2b0e080/d .functor NOT 1, L_0x2b0df70, C4<0>, C4<0>, C4<0>;
+L_0x2b0e080 .delay (10000,10000,10000) L_0x2b0e080/d;
+v0x28061d0_0 .net "A", 0 0, L_0x2b0db30; 1 drivers
+v0x2806270_0 .net "AnandB", 0 0, L_0x2b0de10; 1 drivers
+v0x2806310_0 .net "AnorB", 0 0, L_0x2b0c800; 1 drivers
+v0x28063c0_0 .net "AorB", 0 0, L_0x2b0c8f0; 1 drivers
+v0x28064a0_0 .net "AxorB", 0 0, L_0x2b0e080; 1 drivers
+v0x2806550_0 .net "B", 0 0, L_0x2b0dbd0; 1 drivers
+v0x2806610_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2806690_0 .net "OrNorXorOut", 0 0, L_0x2b0ea80; 1 drivers
+v0x2806710_0 .net "XorNor", 0 0, L_0x2b0e500; 1 drivers
+v0x28067e0_0 .net "nXor", 0 0, L_0x2b0df70; 1 drivers
+L_0x2b0e680 .part v0x2960210_0, 2, 1;
+L_0x2b0ec50 .part v0x2960210_0, 0, 1;
+S_0x2805c60 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2805620;
+ .timescale -9 -12;
+L_0x2b0e1e0/d .functor NOT 1, L_0x2b0e680, C4<0>, C4<0>, C4<0>;
+L_0x2b0e1e0 .delay (10000,10000,10000) L_0x2b0e1e0/d;
+L_0x2b0e2a0/d .functor AND 1, L_0x2b0e080, L_0x2b0e1e0, C4<1>, C4<1>;
+L_0x2b0e2a0 .delay (20000,20000,20000) L_0x2b0e2a0/d;
+L_0x2b0e3b0/d .functor AND 1, L_0x2b0c800, L_0x2b0e680, C4<1>, C4<1>;
+L_0x2b0e3b0 .delay (20000,20000,20000) L_0x2b0e3b0/d;
+L_0x2b0e500/d .functor OR 1, L_0x2b0e2a0, L_0x2b0e3b0, C4<0>, C4<0>;
+L_0x2b0e500 .delay (20000,20000,20000) L_0x2b0e500/d;
+v0x2805d50_0 .net "S", 0 0, L_0x2b0e680; 1 drivers
+v0x2805e10_0 .alias "in0", 0 0, v0x28064a0_0;
+v0x2805eb0_0 .alias "in1", 0 0, v0x2806310_0;
+v0x2805f50_0 .net "nS", 0 0, L_0x2b0e1e0; 1 drivers
+v0x2805fd0_0 .net "out0", 0 0, L_0x2b0e2a0; 1 drivers
+v0x2806070_0 .net "out1", 0 0, L_0x2b0e3b0; 1 drivers
+v0x2806150_0 .alias "outfinal", 0 0, v0x2806710_0;
+S_0x2805710 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2805620;
+ .timescale -9 -12;
+L_0x2b0e720/d .functor NOT 1, L_0x2b0ec50, C4<0>, C4<0>, C4<0>;
+L_0x2b0e720 .delay (10000,10000,10000) L_0x2b0e720/d;
+L_0x2b0e7e0/d .functor AND 1, L_0x2b0e500, L_0x2b0e720, C4<1>, C4<1>;
+L_0x2b0e7e0 .delay (20000,20000,20000) L_0x2b0e7e0/d;
+L_0x2b0e930/d .functor AND 1, L_0x2b0c8f0, L_0x2b0ec50, C4<1>, C4<1>;
+L_0x2b0e930 .delay (20000,20000,20000) L_0x2b0e930/d;
+L_0x2b0ea80/d .functor OR 1, L_0x2b0e7e0, L_0x2b0e930, C4<0>, C4<0>;
+L_0x2b0ea80 .delay (20000,20000,20000) L_0x2b0ea80/d;
+v0x2805800_0 .net "S", 0 0, L_0x2b0ec50; 1 drivers
+v0x2805880_0 .alias "in0", 0 0, v0x2806710_0;
+v0x2805920_0 .alias "in1", 0 0, v0x28063c0_0;
+v0x28059c0_0 .net "nS", 0 0, L_0x2b0e720; 1 drivers
+v0x2805a40_0 .net "out0", 0 0, L_0x2b0e7e0; 1 drivers
+v0x2805ae0_0 .net "out1", 0 0, L_0x2b0e930; 1 drivers
+v0x2805bc0_0 .alias "outfinal", 0 0, v0x2806690_0;
+S_0x2804120 .scope generate, "orbits[29]" "orbits[29]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2803e38 .param/l "i" 3 258, +C4<011101>;
+S_0x2804250 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2804120;
+ .timescale -9 -12;
+L_0x2b0dc70/d .functor NOR 1, L_0x2b10090, L_0x2b0ed90, C4<0>, C4<0>;
+L_0x2b0dc70 .delay (10000,10000,10000) L_0x2b0dc70/d;
+L_0x2b0dd60/d .functor NOT 1, L_0x2b0dc70, C4<0>, C4<0>, C4<0>;
+L_0x2b0dd60 .delay (10000,10000,10000) L_0x2b0dd60/d;
+L_0x2b0f110/d .functor NAND 1, L_0x2b10090, L_0x2b0ed90, C4<1>, C4<1>;
+L_0x2b0f110 .delay (10000,10000,10000) L_0x2b0f110/d;
+L_0x2b0f270/d .functor NAND 1, L_0x2b0f110, L_0x2b0dd60, C4<1>, C4<1>;
+L_0x2b0f270 .delay (10000,10000,10000) L_0x2b0f270/d;
+L_0x2b0f380/d .functor NOT 1, L_0x2b0f270, C4<0>, C4<0>, C4<0>;
+L_0x2b0f380 .delay (10000,10000,10000) L_0x2b0f380/d;
+v0x2804e00_0 .net "A", 0 0, L_0x2b10090; 1 drivers
+v0x2804ea0_0 .net "AnandB", 0 0, L_0x2b0f110; 1 drivers
+v0x2804f40_0 .net "AnorB", 0 0, L_0x2b0dc70; 1 drivers
+v0x2804ff0_0 .net "AorB", 0 0, L_0x2b0dd60; 1 drivers
+v0x28050d0_0 .net "AxorB", 0 0, L_0x2b0f380; 1 drivers
+v0x2805180_0 .net "B", 0 0, L_0x2b0ed90; 1 drivers
+v0x2805240_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x28052c0_0 .net "OrNorXorOut", 0 0, L_0x2b0fd80; 1 drivers
+v0x2805340_0 .net "XorNor", 0 0, L_0x2b0f800; 1 drivers
+v0x2805410_0 .net "nXor", 0 0, L_0x2b0f270; 1 drivers
+L_0x2b0f980 .part v0x2960210_0, 2, 1;
+L_0x2b0ff50 .part v0x2960210_0, 0, 1;
+S_0x2804890 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2804250;
+ .timescale -9 -12;
+L_0x2b0f4e0/d .functor NOT 1, L_0x2b0f980, C4<0>, C4<0>, C4<0>;
+L_0x2b0f4e0 .delay (10000,10000,10000) L_0x2b0f4e0/d;
+L_0x2b0f5a0/d .functor AND 1, L_0x2b0f380, L_0x2b0f4e0, C4<1>, C4<1>;
+L_0x2b0f5a0 .delay (20000,20000,20000) L_0x2b0f5a0/d;
+L_0x2b0f6b0/d .functor AND 1, L_0x2b0dc70, L_0x2b0f980, C4<1>, C4<1>;
+L_0x2b0f6b0 .delay (20000,20000,20000) L_0x2b0f6b0/d;
+L_0x2b0f800/d .functor OR 1, L_0x2b0f5a0, L_0x2b0f6b0, C4<0>, C4<0>;
+L_0x2b0f800 .delay (20000,20000,20000) L_0x2b0f800/d;
+v0x2804980_0 .net "S", 0 0, L_0x2b0f980; 1 drivers
+v0x2804a40_0 .alias "in0", 0 0, v0x28050d0_0;
+v0x2804ae0_0 .alias "in1", 0 0, v0x2804f40_0;
+v0x2804b80_0 .net "nS", 0 0, L_0x2b0f4e0; 1 drivers
+v0x2804c00_0 .net "out0", 0 0, L_0x2b0f5a0; 1 drivers
+v0x2804ca0_0 .net "out1", 0 0, L_0x2b0f6b0; 1 drivers
+v0x2804d80_0 .alias "outfinal", 0 0, v0x2805340_0;
+S_0x2804340 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2804250;
+ .timescale -9 -12;
+L_0x2b0fa20/d .functor NOT 1, L_0x2b0ff50, C4<0>, C4<0>, C4<0>;
+L_0x2b0fa20 .delay (10000,10000,10000) L_0x2b0fa20/d;
+L_0x2b0fae0/d .functor AND 1, L_0x2b0f800, L_0x2b0fa20, C4<1>, C4<1>;
+L_0x2b0fae0 .delay (20000,20000,20000) L_0x2b0fae0/d;
+L_0x2b0fc30/d .functor AND 1, L_0x2b0dd60, L_0x2b0ff50, C4<1>, C4<1>;
+L_0x2b0fc30 .delay (20000,20000,20000) L_0x2b0fc30/d;
+L_0x2b0fd80/d .functor OR 1, L_0x2b0fae0, L_0x2b0fc30, C4<0>, C4<0>;
+L_0x2b0fd80 .delay (20000,20000,20000) L_0x2b0fd80/d;
+v0x2804430_0 .net "S", 0 0, L_0x2b0ff50; 1 drivers
+v0x28044b0_0 .alias "in0", 0 0, v0x2805340_0;
+v0x2804550_0 .alias "in1", 0 0, v0x2804ff0_0;
+v0x28045f0_0 .net "nS", 0 0, L_0x2b0fa20; 1 drivers
+v0x2804670_0 .net "out0", 0 0, L_0x2b0fae0; 1 drivers
+v0x2804710_0 .net "out1", 0 0, L_0x2b0fc30; 1 drivers
+v0x28047f0_0 .alias "outfinal", 0 0, v0x28052c0_0;
+S_0x2802d50 .scope generate, "orbits[30]" "orbits[30]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2802ac8 .param/l "i" 3 258, +C4<011110>;
+S_0x2802e80 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2802d50;
+ .timescale -9 -12;
+L_0x2b0ee30/d .functor NOR 1, L_0x2b10130, L_0x2b101d0, C4<0>, C4<0>;
+L_0x2b0ee30 .delay (10000,10000,10000) L_0x2b0ee30/d;
+L_0x2b0ef20/d .functor NOT 1, L_0x2b0ee30, C4<0>, C4<0>, C4<0>;
+L_0x2b0ef20 .delay (10000,10000,10000) L_0x2b0ef20/d;
+L_0x2b0efe0/d .functor NAND 1, L_0x2b10130, L_0x2b101d0, C4<1>, C4<1>;
+L_0x2b0efe0 .delay (10000,10000,10000) L_0x2b0efe0/d;
+L_0x2b10560/d .functor NAND 1, L_0x2b0efe0, L_0x2b0ef20, C4<1>, C4<1>;
+L_0x2b10560 .delay (10000,10000,10000) L_0x2b10560/d;
+L_0x2b10670/d .functor NOT 1, L_0x2b10560, C4<0>, C4<0>, C4<0>;
+L_0x2b10670 .delay (10000,10000,10000) L_0x2b10670/d;
+v0x2803a30_0 .net "A", 0 0, L_0x2b10130; 1 drivers
+v0x2803ad0_0 .net "AnandB", 0 0, L_0x2b0efe0; 1 drivers
+v0x2803b70_0 .net "AnorB", 0 0, L_0x2b0ee30; 1 drivers
+v0x2803c20_0 .net "AorB", 0 0, L_0x2b0ef20; 1 drivers
+v0x2803d00_0 .net "AxorB", 0 0, L_0x2b10670; 1 drivers
+v0x2803db0_0 .net "B", 0 0, L_0x2b101d0; 1 drivers
+v0x2803e70_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2803ef0_0 .net "OrNorXorOut", 0 0, L_0x2b11070; 1 drivers
+v0x2803f70_0 .net "XorNor", 0 0, L_0x2b10af0; 1 drivers
+v0x2804040_0 .net "nXor", 0 0, L_0x2b10560; 1 drivers
+L_0x2b10c70 .part v0x2960210_0, 2, 1;
+L_0x2b11240 .part v0x2960210_0, 0, 1;
+S_0x28034c0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2802e80;
+ .timescale -9 -12;
+L_0x2b107d0/d .functor NOT 1, L_0x2b10c70, C4<0>, C4<0>, C4<0>;
+L_0x2b107d0 .delay (10000,10000,10000) L_0x2b107d0/d;
+L_0x2b10890/d .functor AND 1, L_0x2b10670, L_0x2b107d0, C4<1>, C4<1>;
+L_0x2b10890 .delay (20000,20000,20000) L_0x2b10890/d;
+L_0x2b109a0/d .functor AND 1, L_0x2b0ee30, L_0x2b10c70, C4<1>, C4<1>;
+L_0x2b109a0 .delay (20000,20000,20000) L_0x2b109a0/d;
+L_0x2b10af0/d .functor OR 1, L_0x2b10890, L_0x2b109a0, C4<0>, C4<0>;
+L_0x2b10af0 .delay (20000,20000,20000) L_0x2b10af0/d;
+v0x28035b0_0 .net "S", 0 0, L_0x2b10c70; 1 drivers
+v0x2803670_0 .alias "in0", 0 0, v0x2803d00_0;
+v0x2803710_0 .alias "in1", 0 0, v0x2803b70_0;
+v0x28037b0_0 .net "nS", 0 0, L_0x2b107d0; 1 drivers
+v0x2803830_0 .net "out0", 0 0, L_0x2b10890; 1 drivers
+v0x28038d0_0 .net "out1", 0 0, L_0x2b109a0; 1 drivers
+v0x28039b0_0 .alias "outfinal", 0 0, v0x2803f70_0;
+S_0x2802f70 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2802e80;
+ .timescale -9 -12;
+L_0x2b10d10/d .functor NOT 1, L_0x2b11240, C4<0>, C4<0>, C4<0>;
+L_0x2b10d10 .delay (10000,10000,10000) L_0x2b10d10/d;
+L_0x2b10dd0/d .functor AND 1, L_0x2b10af0, L_0x2b10d10, C4<1>, C4<1>;
+L_0x2b10dd0 .delay (20000,20000,20000) L_0x2b10dd0/d;
+L_0x2b10f20/d .functor AND 1, L_0x2b0ef20, L_0x2b11240, C4<1>, C4<1>;
+L_0x2b10f20 .delay (20000,20000,20000) L_0x2b10f20/d;
+L_0x2b11070/d .functor OR 1, L_0x2b10dd0, L_0x2b10f20, C4<0>, C4<0>;
+L_0x2b11070 .delay (20000,20000,20000) L_0x2b11070/d;
+v0x2803060_0 .net "S", 0 0, L_0x2b11240; 1 drivers
+v0x28030e0_0 .alias "in0", 0 0, v0x2803f70_0;
+v0x2803180_0 .alias "in1", 0 0, v0x2803c20_0;
+v0x2803220_0 .net "nS", 0 0, L_0x2b10d10; 1 drivers
+v0x28032a0_0 .net "out0", 0 0, L_0x2b10dd0; 1 drivers
+v0x2803340_0 .net "out1", 0 0, L_0x2b10f20; 1 drivers
+v0x2803420_0 .alias "outfinal", 0 0, v0x2803ef0_0;
+S_0x28019a0 .scope generate, "orbits[31]" "orbits[31]" 3 258, 3 258, S_0x2801850;
+ .timescale -9 -12;
+P_0x2801a98 .param/l "i" 3 258, +C4<011111>;
+S_0x2801b50 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x28019a0;
+ .timescale -9 -12;
+L_0x2b10270/d .functor NOR 1, L_0x2b12690, L_0x2b11380, C4<0>, C4<0>;
+L_0x2b10270 .delay (10000,10000,10000) L_0x2b10270/d;
+L_0x2b10360/d .functor NOT 1, L_0x2b10270, C4<0>, C4<0>, C4<0>;
+L_0x2b10360 .delay (10000,10000,10000) L_0x2b10360/d;
+L_0x2b11710/d .functor NAND 1, L_0x2b12690, L_0x2b11380, C4<1>, C4<1>;
+L_0x2b11710 .delay (10000,10000,10000) L_0x2b11710/d;
+L_0x2b11870/d .functor NAND 1, L_0x2b11710, L_0x2b10360, C4<1>, C4<1>;
+L_0x2b11870 .delay (10000,10000,10000) L_0x2b11870/d;
+L_0x2b11980/d .functor NOT 1, L_0x2b11870, C4<0>, C4<0>, C4<0>;
+L_0x2b11980 .delay (10000,10000,10000) L_0x2b11980/d;
+v0x2802720_0 .net "A", 0 0, L_0x2b12690; 1 drivers
+v0x28027c0_0 .net "AnandB", 0 0, L_0x2b11710; 1 drivers
+v0x2802860_0 .net "AnorB", 0 0, L_0x2b10270; 1 drivers
+v0x28028e0_0 .net "AorB", 0 0, L_0x2b10360; 1 drivers
+v0x2802990_0 .net "AxorB", 0 0, L_0x2b11980; 1 drivers
+v0x2802a40_0 .net "B", 0 0, L_0x2b11380; 1 drivers
+v0x2802b00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2802b80_0 .net "OrNorXorOut", 0 0, L_0x2b12380; 1 drivers
+v0x2802c00_0 .net "XorNor", 0 0, L_0x2b11e00; 1 drivers
+v0x2802cd0_0 .net "nXor", 0 0, L_0x2b11870; 1 drivers
+L_0x2b11f80 .part v0x2960210_0, 2, 1;
+L_0x2b12550 .part v0x2960210_0, 0, 1;
+S_0x28021b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2801b50;
+ .timescale -9 -12;
+L_0x2b11ae0/d .functor NOT 1, L_0x2b11f80, C4<0>, C4<0>, C4<0>;
+L_0x2b11ae0 .delay (10000,10000,10000) L_0x2b11ae0/d;
+L_0x2b11ba0/d .functor AND 1, L_0x2b11980, L_0x2b11ae0, C4<1>, C4<1>;
+L_0x2b11ba0 .delay (20000,20000,20000) L_0x2b11ba0/d;
+L_0x2b11cb0/d .functor AND 1, L_0x2b10270, L_0x2b11f80, C4<1>, C4<1>;
+L_0x2b11cb0 .delay (20000,20000,20000) L_0x2b11cb0/d;
+L_0x2b11e00/d .functor OR 1, L_0x2b11ba0, L_0x2b11cb0, C4<0>, C4<0>;
+L_0x2b11e00 .delay (20000,20000,20000) L_0x2b11e00/d;
+v0x28022a0_0 .net "S", 0 0, L_0x2b11f80; 1 drivers
+v0x2802360_0 .alias "in0", 0 0, v0x2802990_0;
+v0x2802400_0 .alias "in1", 0 0, v0x2802860_0;
+v0x28024a0_0 .net "nS", 0 0, L_0x2b11ae0; 1 drivers
+v0x2802520_0 .net "out0", 0 0, L_0x2b11ba0; 1 drivers
+v0x28025c0_0 .net "out1", 0 0, L_0x2b11cb0; 1 drivers
+v0x28026a0_0 .alias "outfinal", 0 0, v0x2802c00_0;
+S_0x2801c40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2801b50;
+ .timescale -9 -12;
+L_0x2b12020/d .functor NOT 1, L_0x2b12550, C4<0>, C4<0>, C4<0>;
+L_0x2b12020 .delay (10000,10000,10000) L_0x2b12020/d;
+L_0x2b120e0/d .functor AND 1, L_0x2b11e00, L_0x2b12020, C4<1>, C4<1>;
+L_0x2b120e0 .delay (20000,20000,20000) L_0x2b120e0/d;
+L_0x2b12230/d .functor AND 1, L_0x2b10360, L_0x2b12550, C4<1>, C4<1>;
+L_0x2b12230 .delay (20000,20000,20000) L_0x2b12230/d;
+L_0x2b12380/d .functor OR 1, L_0x2b120e0, L_0x2b12230, C4<0>, C4<0>;
+L_0x2b12380 .delay (20000,20000,20000) L_0x2b12380/d;
+v0x2801d30_0 .net "S", 0 0, L_0x2b12550; 1 drivers
+v0x2801dd0_0 .alias "in0", 0 0, v0x2802c00_0;
+v0x2801e70_0 .alias "in1", 0 0, v0x28028e0_0;
+v0x2801f10_0 .net "nS", 0 0, L_0x2b12020; 1 drivers
+v0x2801f90_0 .net "out0", 0 0, L_0x2b120e0; 1 drivers
+v0x2802030_0 .net "out1", 0 0, L_0x2b12230; 1 drivers
+v0x2802110_0 .alias "outfinal", 0 0, v0x2802b80_0;
+S_0x2800ed0 .scope module, "ZeroMux0case" "FourInMux" 3 390, 3 125, S_0x25e6a40;
+ .timescale -9 -12;
+L_0x2b12870/d .functor NOT 1, L_0x2a61c30, C4<0>, C4<0>, C4<0>;
+L_0x2b12870 .delay (10000,10000,10000) L_0x2b12870/d;
+L_0x2b12910/d .functor NOT 1, L_0x2a61d60, C4<0>, C4<0>, C4<0>;
+L_0x2b12910 .delay (10000,10000,10000) L_0x2b12910/d;
+L_0x2b13cb0/d .functor NAND 1, L_0x2b12870, L_0x2b12910, L_0x2a61e90, C4<1>;
+L_0x2b13cb0 .delay (10000,10000,10000) L_0x2b13cb0/d;
+L_0x2b13da0/d .functor NAND 1, L_0x2a61c30, L_0x2b12910, L_0x2a61f30, C4<1>;
+L_0x2b13da0 .delay (10000,10000,10000) L_0x2b13da0/d;
+L_0x2b13e90/d .functor NAND 1, L_0x2b12870, L_0x2a61d60, L_0x2a61fd0, C4<1>;
+L_0x2b13e90 .delay (10000,10000,10000) L_0x2b13e90/d;
+L_0x2b13f80/d .functor NAND 1, L_0x2a61c30, L_0x2a61d60, L_0x2a620c0, C4<1>;
+L_0x2b13f80 .delay (10000,10000,10000) L_0x2b13f80/d;
+L_0x2b14060/d .functor NAND 1, L_0x2b13cb0, L_0x2b13da0, L_0x2b13e90, L_0x2b13f80;
+L_0x2b14060 .delay (10000,10000,10000) L_0x2b14060/d;
+v0x2800fc0_0 .net "S0", 0 0, L_0x2a61c30; 1 drivers
+v0x2801080_0 .net "S1", 0 0, L_0x2a61d60; 1 drivers
+v0x2801120_0 .net "in0", 0 0, L_0x2a61e90; 1 drivers
+v0x28011c0_0 .net "in1", 0 0, L_0x2a61f30; 1 drivers
+v0x2801240_0 .net "in2", 0 0, L_0x2a61fd0; 1 drivers
+v0x28012e0_0 .net "in3", 0 0, L_0x2a620c0; 1 drivers
+v0x2801380_0 .net "nS0", 0 0, L_0x2b12870; 1 drivers
+v0x2801420_0 .net "nS1", 0 0, L_0x2b12910; 1 drivers
+v0x28014c0_0 .net "out", 0 0, L_0x2b14060; 1 drivers
+v0x2801560_0 .net "out0", 0 0, L_0x2b13cb0; 1 drivers
+v0x2801600_0 .net "out1", 0 0, L_0x2b13da0; 1 drivers
+v0x28016a0_0 .net "out2", 0 0, L_0x2b13e90; 1 drivers
+v0x28017b0_0 .net "out3", 0 0, L_0x2b13f80; 1 drivers
+S_0x2800510 .scope module, "OneMux0case" "FourInMux" 3 391, 3 125, S_0x25e6a40;
+ .timescale -9 -12;
+L_0x2a621b0/d .functor NOT 1, L_0x2a629f0, C4<0>, C4<0>, C4<0>;
+L_0x2a621b0 .delay (10000,10000,10000) L_0x2a621b0/d;
+L_0x2a622a0/d .functor NOT 1, L_0x2a62b20, C4<0>, C4<0>, C4<0>;
+L_0x2a622a0 .delay (10000,10000,10000) L_0x2a622a0/d;
+L_0x2a62340/d .functor NAND 1, L_0x2a621b0, L_0x2a622a0, L_0x2a62c50, C4<1>;
+L_0x2a62340 .delay (10000,10000,10000) L_0x2a62340/d;
+L_0x2a62480/d .functor NAND 1, L_0x2a629f0, L_0x2a622a0, L_0x2a62cf0, C4<1>;
+L_0x2a62480 .delay (10000,10000,10000) L_0x2a62480/d;
+L_0x2a62570/d .functor NAND 1, L_0x2a621b0, L_0x2a62b20, L_0x2a62d90, C4<1>;
+L_0x2a62570 .delay (10000,10000,10000) L_0x2a62570/d;
+L_0x2a62660/d .functor NAND 1, L_0x2a629f0, L_0x2a62b20, L_0x2a62e80, C4<1>;
+L_0x2a62660 .delay (10000,10000,10000) L_0x2a62660/d;
+L_0x2a62740/d .functor NAND 1, L_0x2a62340, L_0x2a62480, L_0x2a62570, L_0x2a62660;
+L_0x2a62740 .delay (10000,10000,10000) L_0x2a62740/d;
+v0x2800600_0 .net "S0", 0 0, L_0x2a629f0; 1 drivers
+v0x28006c0_0 .net "S1", 0 0, L_0x2a62b20; 1 drivers
+v0x2800760_0 .net "in0", 0 0, L_0x2a62c50; 1 drivers
+v0x2800800_0 .net "in1", 0 0, L_0x2a62cf0; 1 drivers
+v0x2800880_0 .net "in2", 0 0, L_0x2a62d90; 1 drivers
+v0x2800920_0 .net "in3", 0 0, L_0x2a62e80; 1 drivers
+v0x2800a00_0 .net "nS0", 0 0, L_0x2a621b0; 1 drivers
+v0x2800aa0_0 .net "nS1", 0 0, L_0x2a622a0; 1 drivers
+v0x2800b40_0 .net "out", 0 0, L_0x2a62740; 1 drivers
+v0x2800be0_0 .net "out0", 0 0, L_0x2a62340; 1 drivers
+v0x2800c80_0 .net "out1", 0 0, L_0x2a62480; 1 drivers
+v0x2800d20_0 .net "out2", 0 0, L_0x2a62570; 1 drivers
+v0x2800e30_0 .net "out3", 0 0, L_0x2a62660; 1 drivers
+S_0x27fffc0 .scope module, "TwoMux0case" "TwoInMux" 3 392, 3 109, S_0x25e6a40;
+ .timescale -9 -12;
+L_0x2a62f70/d .functor NOT 1, L_0x2a3ade0, C4<0>, C4<0>, C4<0>;
+L_0x2a62f70 .delay (10000,10000,10000) L_0x2a62f70/d;
+L_0x2b157b0/d .functor AND 1, L_0x2a3ae80, L_0x2a62f70, C4<1>, C4<1>;
+L_0x2b157b0 .delay (20000,20000,20000) L_0x2b157b0/d;
+L_0x2b158a0/d .functor AND 1, L_0x2a3af70, L_0x2a3ade0, C4<1>, C4<1>;
+L_0x2b158a0 .delay (20000,20000,20000) L_0x2b158a0/d;
+L_0x2b15990/d .functor OR 1, L_0x2b157b0, L_0x2b158a0, C4<0>, C4<0>;
+L_0x2b15990 .delay (20000,20000,20000) L_0x2b15990/d;
+v0x28000b0_0 .net "S", 0 0, L_0x2a3ade0; 1 drivers
+v0x2800170_0 .net "in0", 0 0, L_0x2a3ae80; 1 drivers
+v0x2800210_0 .net "in1", 0 0, L_0x2a3af70; 1 drivers
+v0x28002b0_0 .net "nS", 0 0, L_0x2a62f70; 1 drivers
+v0x2800330_0 .net "out0", 0 0, L_0x2b157b0; 1 drivers
+v0x28003d0_0 .net "out1", 0 0, L_0x2b158a0; 1 drivers
+v0x2800470_0 .net "outfinal", 0 0, L_0x2b15990; 1 drivers
+S_0x27fe440 .scope generate, "muxbits[1]" "muxbits[1]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27fd438 .param/l "i" 3 397, +C4<01>;
+L_0x2a142f0/d .functor OR 1, L_0x2a143f0, L_0x2a141b0, C4<0>, C4<0>;
+L_0x2a142f0 .delay (20000,20000,20000) L_0x2a142f0/d;
+v0x27ffe60_0 .net *"_s15", 0 0, L_0x2a143f0; 1 drivers
+v0x27fff20_0 .net *"_s16", 0 0, L_0x2a141b0; 1 drivers
+S_0x27ff4e0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27fe440;
+ .timescale -9 -12;
+L_0x2a107d0/d .functor NOT 1, L_0x2a123f0, C4<0>, C4<0>, C4<0>;
+L_0x2a107d0 .delay (10000,10000,10000) L_0x2a107d0/d;
+L_0x2a10870/d .functor NOT 1, L_0x2a12520, C4<0>, C4<0>, C4<0>;
+L_0x2a10870 .delay (10000,10000,10000) L_0x2a10870/d;
+L_0x2a11bf0/d .functor NAND 1, L_0x2a107d0, L_0x2a10870, L_0x2a12650, C4<1>;
+L_0x2a11bf0 .delay (10000,10000,10000) L_0x2a11bf0/d;
+L_0x2a11d30/d .functor NAND 1, L_0x2a123f0, L_0x2a10870, L_0x2a126f0, C4<1>;
+L_0x2a11d30 .delay (10000,10000,10000) L_0x2a11d30/d;
+L_0x2a11e80/d .functor NAND 1, L_0x2a107d0, L_0x2a12520, L_0x2a12790, C4<1>;
+L_0x2a11e80 .delay (10000,10000,10000) L_0x2a11e80/d;
+L_0x2a11fd0/d .functor NAND 1, L_0x2a123f0, L_0x2a12520, L_0x2a128c0, C4<1>;
+L_0x2a11fd0 .delay (10000,10000,10000) L_0x2a11fd0/d;
+L_0x2a12140/d .functor NAND 1, L_0x2a11bf0, L_0x2a11d30, L_0x2a11e80, L_0x2a11fd0;
+L_0x2a12140 .delay (10000,10000,10000) L_0x2a12140/d;
+v0x27ff5d0_0 .net "S0", 0 0, L_0x2a123f0; 1 drivers
+v0x27ff690_0 .net "S1", 0 0, L_0x2a12520; 1 drivers
+v0x27ff730_0 .net "in0", 0 0, L_0x2a12650; 1 drivers
+v0x27ff7d0_0 .net "in1", 0 0, L_0x2a126f0; 1 drivers
+v0x27ff850_0 .net "in2", 0 0, L_0x2a12790; 1 drivers
+v0x27ff8f0_0 .net "in3", 0 0, L_0x2a128c0; 1 drivers
+v0x27ff990_0 .net "nS0", 0 0, L_0x2a107d0; 1 drivers
+v0x27ffa30_0 .net "nS1", 0 0, L_0x2a10870; 1 drivers
+v0x27ffad0_0 .net "out", 0 0, L_0x2a12140; 1 drivers
+v0x27ffb70_0 .net "out0", 0 0, L_0x2a11bf0; 1 drivers
+v0x27ffc10_0 .net "out1", 0 0, L_0x2a11d30; 1 drivers
+v0x27ffcb0_0 .net "out2", 0 0, L_0x2a11e80; 1 drivers
+v0x27ffdc0_0 .net "out3", 0 0, L_0x2a11fd0; 1 drivers
+S_0x27feb20 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27fe440;
+ .timescale -9 -12;
+L_0x2a129b0/d .functor NOT 1, L_0x2a13320, C4<0>, C4<0>, C4<0>;
+L_0x2a129b0 .delay (10000,10000,10000) L_0x2a129b0/d;
+L_0x2a12aa0/d .functor NOT 1, L_0x2a13450, C4<0>, C4<0>, C4<0>;
+L_0x2a12aa0 .delay (10000,10000,10000) L_0x2a12aa0/d;
+L_0x2a12b40/d .functor NAND 1, L_0x2a129b0, L_0x2a12aa0, L_0x2a135e0, C4<1>;
+L_0x2a12b40 .delay (10000,10000,10000) L_0x2a12b40/d;
+L_0x2a12c80/d .functor NAND 1, L_0x2a13320, L_0x2a12aa0, L_0x2a13680, C4<1>;
+L_0x2a12c80 .delay (10000,10000,10000) L_0x2a12c80/d;
+L_0x2a12d70/d .functor NAND 1, L_0x2a129b0, L_0x2a13450, L_0x2a13790, C4<1>;
+L_0x2a12d70 .delay (10000,10000,10000) L_0x2a12d70/d;
+L_0x2a12ec0/d .functor NAND 1, L_0x2a13320, L_0x2a13450, L_0x2a13830, C4<1>;
+L_0x2a12ec0 .delay (10000,10000,10000) L_0x2a12ec0/d;
+L_0x2a12ff0/d .functor NAND 1, L_0x2a12b40, L_0x2a12c80, L_0x2a12d70, L_0x2a12ec0;
+L_0x2a12ff0 .delay (10000,10000,10000) L_0x2a12ff0/d;
+v0x27fec10_0 .net "S0", 0 0, L_0x2a13320; 1 drivers
+v0x27fecd0_0 .net "S1", 0 0, L_0x2a13450; 1 drivers
+v0x27fed70_0 .net "in0", 0 0, L_0x2a135e0; 1 drivers
+v0x27fee10_0 .net "in1", 0 0, L_0x2a13680; 1 drivers
+v0x27fee90_0 .net "in2", 0 0, L_0x2a13790; 1 drivers
+v0x27fef30_0 .net "in3", 0 0, L_0x2a13830; 1 drivers
+v0x27ff010_0 .net "nS0", 0 0, L_0x2a129b0; 1 drivers
+v0x27ff0b0_0 .net "nS1", 0 0, L_0x2a12aa0; 1 drivers
+v0x27ff150_0 .net "out", 0 0, L_0x2a12ff0; 1 drivers
+v0x27ff1f0_0 .net "out0", 0 0, L_0x2a12b40; 1 drivers
+v0x27ff290_0 .net "out1", 0 0, L_0x2a12c80; 1 drivers
+v0x27ff330_0 .net "out2", 0 0, L_0x2a12d70; 1 drivers
+v0x27ff440_0 .net "out3", 0 0, L_0x2a12ec0; 1 drivers
+S_0x27fe5b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27fe440;
+ .timescale -9 -12;
+L_0x2a13580/d .functor NOT 1, L_0x2a13e00, C4<0>, C4<0>, C4<0>;
+L_0x2a13580 .delay (10000,10000,10000) L_0x2a13580/d;
+L_0x2a139f0/d .functor AND 1, L_0x2a13f30, L_0x2a13580, C4<1>, C4<1>;
+L_0x2a139f0 .delay (20000,20000,20000) L_0x2a139f0/d;
+L_0x2a13ae0/d .functor AND 1, L_0x2a14070, L_0x2a13e00, C4<1>, C4<1>;
+L_0x2a13ae0 .delay (20000,20000,20000) L_0x2a13ae0/d;
+L_0x2a13bd0/d .functor OR 1, L_0x2a139f0, L_0x2a13ae0, C4<0>, C4<0>;
+L_0x2a13bd0 .delay (20000,20000,20000) L_0x2a13bd0/d;
+v0x27fe6a0_0 .net "S", 0 0, L_0x2a13e00; 1 drivers
+v0x27fe740_0 .net "in0", 0 0, L_0x2a13f30; 1 drivers
+v0x27fe7e0_0 .net "in1", 0 0, L_0x2a14070; 1 drivers
+v0x27fe880_0 .net "nS", 0 0, L_0x2a13580; 1 drivers
+v0x27fe900_0 .net "out0", 0 0, L_0x2a139f0; 1 drivers
+v0x27fe9a0_0 .net "out1", 0 0, L_0x2a13ae0; 1 drivers
+v0x27fea80_0 .net "outfinal", 0 0, L_0x2a13bd0; 1 drivers
+S_0x27fc8c0 .scope generate, "muxbits[2]" "muxbits[2]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27fb8b8 .param/l "i" 3 397, +C4<010>;
+L_0x2a162d0/d .functor OR 1, L_0x2a16ad0, L_0x2a16e50, C4<0>, C4<0>;
+L_0x2a162d0 .delay (20000,20000,20000) L_0x2a162d0/d;
+v0x27fe2e0_0 .net *"_s15", 0 0, L_0x2a16ad0; 1 drivers
+v0x27fe3a0_0 .net *"_s16", 0 0, L_0x2a16e50; 1 drivers
+S_0x27fd960 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27fc8c0;
+ .timescale -9 -12;
+L_0x2a14590/d .functor NOT 1, L_0x2a14490, C4<0>, C4<0>, C4<0>;
+L_0x2a14590 .delay (10000,10000,10000) L_0x2a14590/d;
+L_0x2a14680/d .functor NOT 1, L_0x2a14f80, C4<0>, C4<0>, C4<0>;
+L_0x2a14680 .delay (10000,10000,10000) L_0x2a14680/d;
+L_0x2a14720/d .functor NAND 1, L_0x2a14590, L_0x2a14680, L_0x2a14e30, C4<1>;
+L_0x2a14720 .delay (10000,10000,10000) L_0x2a14720/d;
+L_0x2a14860/d .functor NAND 1, L_0x2a14490, L_0x2a14680, L_0x2a15180, C4<1>;
+L_0x2a14860 .delay (10000,10000,10000) L_0x2a14860/d;
+L_0x2a14950/d .functor NAND 1, L_0x2a14590, L_0x2a14f80, L_0x2a150b0, C4<1>;
+L_0x2a14950 .delay (10000,10000,10000) L_0x2a14950/d;
+L_0x2a14a40/d .functor NAND 1, L_0x2a14490, L_0x2a14f80, L_0x2a15350, C4<1>;
+L_0x2a14a40 .delay (10000,10000,10000) L_0x2a14a40/d;
+L_0x2a14b80/d .functor NAND 1, L_0x2a14720, L_0x2a14860, L_0x2a14950, L_0x2a14a40;
+L_0x2a14b80 .delay (10000,10000,10000) L_0x2a14b80/d;
+v0x27fda50_0 .net "S0", 0 0, L_0x2a14490; 1 drivers
+v0x27fdb10_0 .net "S1", 0 0, L_0x2a14f80; 1 drivers
+v0x27fdbb0_0 .net "in0", 0 0, L_0x2a14e30; 1 drivers
+v0x27fdc50_0 .net "in1", 0 0, L_0x2a15180; 1 drivers
+v0x27fdcd0_0 .net "in2", 0 0, L_0x2a150b0; 1 drivers
+v0x27fdd70_0 .net "in3", 0 0, L_0x2a15350; 1 drivers
+v0x27fde10_0 .net "nS0", 0 0, L_0x2a14590; 1 drivers
+v0x27fdeb0_0 .net "nS1", 0 0, L_0x2a14680; 1 drivers
+v0x27fdf50_0 .net "out", 0 0, L_0x2a14b80; 1 drivers
+v0x27fdff0_0 .net "out0", 0 0, L_0x2a14720; 1 drivers
+v0x27fe090_0 .net "out1", 0 0, L_0x2a14860; 1 drivers
+v0x27fe130_0 .net "out2", 0 0, L_0x2a14950; 1 drivers
+v0x27fe240_0 .net "out3", 0 0, L_0x2a14a40; 1 drivers
+S_0x27fcfa0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27fc8c0;
+ .timescale -9 -12;
+L_0x2a15220/d .functor NOT 1, L_0x2a15d20, C4<0>, C4<0>, C4<0>;
+L_0x2a15220 .delay (10000,10000,10000) L_0x2a15220/d;
+L_0x2a15580/d .functor NOT 1, L_0x2a15440, C4<0>, C4<0>, C4<0>;
+L_0x2a15580 .delay (10000,10000,10000) L_0x2a15580/d;
+L_0x2a155e0/d .functor NAND 1, L_0x2a15220, L_0x2a15580, L_0x2a15fe0, C4<1>;
+L_0x2a155e0 .delay (10000,10000,10000) L_0x2a155e0/d;
+L_0x2a15720/d .functor NAND 1, L_0x2a15d20, L_0x2a15580, L_0x2a15e50, C4<1>;
+L_0x2a15720 .delay (10000,10000,10000) L_0x2a15720/d;
+L_0x2a15810/d .functor NAND 1, L_0x2a15220, L_0x2a15440, L_0x2a16190, C4<1>;
+L_0x2a15810 .delay (10000,10000,10000) L_0x2a15810/d;
+L_0x2a15900/d .functor NAND 1, L_0x2a15d20, L_0x2a15440, L_0x2a16080, C4<1>;
+L_0x2a15900 .delay (10000,10000,10000) L_0x2a15900/d;
+L_0x2a15a70/d .functor NAND 1, L_0x2a155e0, L_0x2a15720, L_0x2a15810, L_0x2a15900;
+L_0x2a15a70 .delay (10000,10000,10000) L_0x2a15a70/d;
+v0x27fd090_0 .net "S0", 0 0, L_0x2a15d20; 1 drivers
+v0x27fd150_0 .net "S1", 0 0, L_0x2a15440; 1 drivers
+v0x27fd1f0_0 .net "in0", 0 0, L_0x2a15fe0; 1 drivers
+v0x27fd290_0 .net "in1", 0 0, L_0x2a15e50; 1 drivers
+v0x27fd310_0 .net "in2", 0 0, L_0x2a16190; 1 drivers
+v0x27fd3b0_0 .net "in3", 0 0, L_0x2a16080; 1 drivers
+v0x27fd490_0 .net "nS0", 0 0, L_0x2a15220; 1 drivers
+v0x27fd530_0 .net "nS1", 0 0, L_0x2a15580; 1 drivers
+v0x27fd5d0_0 .net "out", 0 0, L_0x2a15a70; 1 drivers
+v0x27fd670_0 .net "out0", 0 0, L_0x2a155e0; 1 drivers
+v0x27fd710_0 .net "out1", 0 0, L_0x2a15720; 1 drivers
+v0x27fd7b0_0 .net "out2", 0 0, L_0x2a15810; 1 drivers
+v0x27fd8c0_0 .net "out3", 0 0, L_0x2a15900; 1 drivers
+S_0x27fca30 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27fc8c0;
+ .timescale -9 -12;
+L_0x2a16120/d .functor NOT 1, L_0x2a16230, C4<0>, C4<0>, C4<0>;
+L_0x2a16120 .delay (10000,10000,10000) L_0x2a16120/d;
+L_0x2a163e0/d .functor AND 1, L_0x2a16960, L_0x2a16120, C4<1>, C4<1>;
+L_0x2a163e0 .delay (20000,20000,20000) L_0x2a163e0/d;
+L_0x2a164d0/d .functor AND 1, L_0x2a16830, L_0x2a16230, C4<1>, C4<1>;
+L_0x2a164d0 .delay (20000,20000,20000) L_0x2a164d0/d;
+L_0x2a165c0/d .functor OR 1, L_0x2a163e0, L_0x2a164d0, C4<0>, C4<0>;
+L_0x2a165c0 .delay (20000,20000,20000) L_0x2a165c0/d;
+v0x27fcb20_0 .net "S", 0 0, L_0x2a16230; 1 drivers
+v0x27fcbc0_0 .net "in0", 0 0, L_0x2a16960; 1 drivers
+v0x27fcc60_0 .net "in1", 0 0, L_0x2a16830; 1 drivers
+v0x27fcd00_0 .net "nS", 0 0, L_0x2a16120; 1 drivers
+v0x27fcd80_0 .net "out0", 0 0, L_0x2a163e0; 1 drivers
+v0x27fce20_0 .net "out1", 0 0, L_0x2a164d0; 1 drivers
+v0x27fcf00_0 .net "outfinal", 0 0, L_0x2a165c0; 1 drivers
+S_0x27fad40 .scope generate, "muxbits[3]" "muxbits[3]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27f9d38 .param/l "i" 3 397, +C4<011>;
+L_0x2a19200/d .functor OR 1, L_0x2a19580, L_0x2a19390, C4<0>, C4<0>;
+L_0x2a19200 .delay (20000,20000,20000) L_0x2a19200/d;
+v0x27fc760_0 .net *"_s15", 0 0, L_0x2a19580; 1 drivers
+v0x27fc820_0 .net *"_s16", 0 0, L_0x2a19390; 1 drivers
+S_0x27fbde0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27fad40;
+ .timescale -9 -12;
+L_0x2a13720/d .functor NOT 1, L_0x2a17750, C4<0>, C4<0>, C4<0>;
+L_0x2a13720 .delay (10000,10000,10000) L_0x2a13720/d;
+L_0x2a16d50/d .functor NOT 1, L_0x2a16ef0, C4<0>, C4<0>, C4<0>;
+L_0x2a16d50 .delay (10000,10000,10000) L_0x2a16d50/d;
+L_0x2a16db0/d .functor NAND 1, L_0x2a13720, L_0x2a16d50, L_0x2a179f0, C4<1>;
+L_0x2a16db0 .delay (10000,10000,10000) L_0x2a16db0/d;
+L_0x2a170f0/d .functor NAND 1, L_0x2a17750, L_0x2a16d50, L_0x2a17880, C4<1>;
+L_0x2a170f0 .delay (10000,10000,10000) L_0x2a170f0/d;
+L_0x2a171e0/d .functor NAND 1, L_0x2a13720, L_0x2a16ef0, L_0x2a17920, C4<1>;
+L_0x2a171e0 .delay (10000,10000,10000) L_0x2a171e0/d;
+L_0x2a17330/d .functor NAND 1, L_0x2a17750, L_0x2a16ef0, L_0x2a17a90, C4<1>;
+L_0x2a17330 .delay (10000,10000,10000) L_0x2a17330/d;
+L_0x2a174a0/d .functor NAND 1, L_0x2a16db0, L_0x2a170f0, L_0x2a171e0, L_0x2a17330;
+L_0x2a174a0 .delay (10000,10000,10000) L_0x2a174a0/d;
+v0x27fbed0_0 .net "S0", 0 0, L_0x2a17750; 1 drivers
+v0x27fbf90_0 .net "S1", 0 0, L_0x2a16ef0; 1 drivers
+v0x27fc030_0 .net "in0", 0 0, L_0x2a179f0; 1 drivers
+v0x27fc0d0_0 .net "in1", 0 0, L_0x2a17880; 1 drivers
+v0x27fc150_0 .net "in2", 0 0, L_0x2a17920; 1 drivers
+v0x27fc1f0_0 .net "in3", 0 0, L_0x2a17a90; 1 drivers
+v0x27fc290_0 .net "nS0", 0 0, L_0x2a13720; 1 drivers
+v0x27fc330_0 .net "nS1", 0 0, L_0x2a16d50; 1 drivers
+v0x27fc3d0_0 .net "out", 0 0, L_0x2a174a0; 1 drivers
+v0x27fc470_0 .net "out0", 0 0, L_0x2a16db0; 1 drivers
+v0x27fc510_0 .net "out1", 0 0, L_0x2a170f0; 1 drivers
+v0x27fc5b0_0 .net "out2", 0 0, L_0x2a171e0; 1 drivers
+v0x27fc6c0_0 .net "out3", 0 0, L_0x2a17330; 1 drivers
+S_0x27fb420 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27fad40;
+ .timescale -9 -12;
+L_0x2a17b80/d .functor NOT 1, L_0x2a17c60, C4<0>, C4<0>, C4<0>;
+L_0x2a17b80 .delay (10000,10000,10000) L_0x2a17b80/d;
+L_0x2a17e80/d .functor NOT 1, L_0x2a187a0, C4<0>, C4<0>, C4<0>;
+L_0x2a17e80 .delay (10000,10000,10000) L_0x2a17e80/d;
+L_0x2a17f20/d .functor NAND 1, L_0x2a17b80, L_0x2a17e80, L_0x2a18600, C4<1>;
+L_0x2a17f20 .delay (10000,10000,10000) L_0x2a17f20/d;
+L_0x2a18060/d .functor NAND 1, L_0x2a17c60, L_0x2a17e80, L_0x2a186a0, C4<1>;
+L_0x2a18060 .delay (10000,10000,10000) L_0x2a18060/d;
+L_0x2a18150/d .functor NAND 1, L_0x2a17b80, L_0x2a187a0, L_0x2a18a90, C4<1>;
+L_0x2a18150 .delay (10000,10000,10000) L_0x2a18150/d;
+L_0x2a18240/d .functor NAND 1, L_0x2a17c60, L_0x2a187a0, L_0x2a18b30, C4<1>;
+L_0x2a18240 .delay (10000,10000,10000) L_0x2a18240/d;
+L_0x2a18350/d .functor NAND 1, L_0x2a17f20, L_0x2a18060, L_0x2a18150, L_0x2a18240;
+L_0x2a18350 .delay (10000,10000,10000) L_0x2a18350/d;
+v0x27fb510_0 .net "S0", 0 0, L_0x2a17c60; 1 drivers
+v0x27fb5d0_0 .net "S1", 0 0, L_0x2a187a0; 1 drivers
+v0x27fb670_0 .net "in0", 0 0, L_0x2a18600; 1 drivers
+v0x27fb710_0 .net "in1", 0 0, L_0x2a186a0; 1 drivers
+v0x27fb790_0 .net "in2", 0 0, L_0x2a18a90; 1 drivers
+v0x27fb830_0 .net "in3", 0 0, L_0x2a18b30; 1 drivers
+v0x27fb910_0 .net "nS0", 0 0, L_0x2a17b80; 1 drivers
+v0x27fb9b0_0 .net "nS1", 0 0, L_0x2a17e80; 1 drivers
+v0x27fba50_0 .net "out", 0 0, L_0x2a18350; 1 drivers
+v0x27fbaf0_0 .net "out0", 0 0, L_0x2a17f20; 1 drivers
+v0x27fbb90_0 .net "out1", 0 0, L_0x2a18060; 1 drivers
+v0x27fbc30_0 .net "out2", 0 0, L_0x2a18150; 1 drivers
+v0x27fbd40_0 .net "out3", 0 0, L_0x2a18240; 1 drivers
+S_0x27faeb0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27fad40;
+ .timescale -9 -12;
+L_0x2a188d0/d .functor NOT 1, L_0x2a190c0, C4<0>, C4<0>, C4<0>;
+L_0x2a188d0 .delay (10000,10000,10000) L_0x2a188d0/d;
+L_0x2a189c0/d .functor AND 1, L_0x2a18bd0, L_0x2a188d0, C4<1>, C4<1>;
+L_0x2a189c0 .delay (20000,20000,20000) L_0x2a189c0/d;
+L_0x2a18df0/d .functor AND 1, L_0x2a18cc0, L_0x2a190c0, C4<1>, C4<1>;
+L_0x2a18df0 .delay (20000,20000,20000) L_0x2a18df0/d;
+L_0x2a18ee0/d .functor OR 1, L_0x2a189c0, L_0x2a18df0, C4<0>, C4<0>;
+L_0x2a18ee0 .delay (20000,20000,20000) L_0x2a18ee0/d;
+v0x27fafa0_0 .net "S", 0 0, L_0x2a190c0; 1 drivers
+v0x27fb040_0 .net "in0", 0 0, L_0x2a18bd0; 1 drivers
+v0x27fb0e0_0 .net "in1", 0 0, L_0x2a18cc0; 1 drivers
+v0x27fb180_0 .net "nS", 0 0, L_0x2a188d0; 1 drivers
+v0x27fb200_0 .net "out0", 0 0, L_0x2a189c0; 1 drivers
+v0x27fb2a0_0 .net "out1", 0 0, L_0x2a18df0; 1 drivers
+v0x27fb380_0 .net "outfinal", 0 0, L_0x2a18ee0; 1 drivers
+S_0x27f91c0 .scope generate, "muxbits[4]" "muxbits[4]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27f81b8 .param/l "i" 3 397, +C4<0100>;
+L_0x2a16a00/d .functor OR 1, L_0x2a1bc10, L_0x2a1bdf0, C4<0>, C4<0>;
+L_0x2a16a00 .delay (20000,20000,20000) L_0x2a16a00/d;
+v0x27fabe0_0 .net *"_s15", 0 0, L_0x2a1bc10; 1 drivers
+v0x27faca0_0 .net *"_s16", 0 0, L_0x2a1bdf0; 1 drivers
+S_0x27fa260 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f91c0;
+ .timescale -9 -12;
+L_0x2a19480/d .functor NOT 1, L_0x2a19620, C4<0>, C4<0>, C4<0>;
+L_0x2a19480 .delay (10000,10000,10000) L_0x2a19480/d;
+L_0x2a19820/d .functor NOT 1, L_0x2a19750, C4<0>, C4<0>, C4<0>;
+L_0x2a19820 .delay (10000,10000,10000) L_0x2a19820/d;
+L_0x2a19880/d .functor NAND 1, L_0x2a19480, L_0x2a19820, L_0x2a19ff0, C4<1>;
+L_0x2a19880 .delay (10000,10000,10000) L_0x2a19880/d;
+L_0x2a199c0/d .functor NAND 1, L_0x2a19620, L_0x2a19820, L_0x2a1a090, C4<1>;
+L_0x2a199c0 .delay (10000,10000,10000) L_0x2a199c0/d;
+L_0x2a19ab0/d .functor NAND 1, L_0x2a19480, L_0x2a19750, L_0x2a1a130, C4<1>;
+L_0x2a19ab0 .delay (10000,10000,10000) L_0x2a19ab0/d;
+L_0x2a19bd0/d .functor NAND 1, L_0x2a19620, L_0x2a19750, L_0x2a1a510, C4<1>;
+L_0x2a19bd0 .delay (10000,10000,10000) L_0x2a19bd0/d;
+L_0x2a19d40/d .functor NAND 1, L_0x2a19880, L_0x2a199c0, L_0x2a19ab0, L_0x2a19bd0;
+L_0x2a19d40 .delay (10000,10000,10000) L_0x2a19d40/d;
+v0x27fa350_0 .net "S0", 0 0, L_0x2a19620; 1 drivers
+v0x27fa410_0 .net "S1", 0 0, L_0x2a19750; 1 drivers
+v0x27fa4b0_0 .net "in0", 0 0, L_0x2a19ff0; 1 drivers
+v0x27fa550_0 .net "in1", 0 0, L_0x2a1a090; 1 drivers
+v0x27fa5d0_0 .net "in2", 0 0, L_0x2a1a130; 1 drivers
+v0x27fa670_0 .net "in3", 0 0, L_0x2a1a510; 1 drivers
+v0x27fa710_0 .net "nS0", 0 0, L_0x2a19480; 1 drivers
+v0x27fa7b0_0 .net "nS1", 0 0, L_0x2a19820; 1 drivers
+v0x27fa850_0 .net "out", 0 0, L_0x2a19d40; 1 drivers
+v0x27fa8f0_0 .net "out0", 0 0, L_0x2a19880; 1 drivers
+v0x27fa990_0 .net "out1", 0 0, L_0x2a199c0; 1 drivers
+v0x27faa30_0 .net "out2", 0 0, L_0x2a19ab0; 1 drivers
+v0x27fab40_0 .net "out3", 0 0, L_0x2a19bd0; 1 drivers
+S_0x27f98a0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f91c0;
+ .timescale -9 -12;
+L_0x2a1a290/d .functor NOT 1, L_0x2a1aeb0, C4<0>, C4<0>, C4<0>;
+L_0x2a1a290 .delay (10000,10000,10000) L_0x2a1a290/d;
+L_0x2a1a380/d .functor NOT 1, L_0x2a1a600, C4<0>, C4<0>, C4<0>;
+L_0x2a1a380 .delay (10000,10000,10000) L_0x2a1a380/d;
+L_0x2a1a420/d .functor NAND 1, L_0x2a1a290, L_0x2a1a380, L_0x2a1a730, C4<1>;
+L_0x2a1a420 .delay (10000,10000,10000) L_0x2a1a420/d;
+L_0x2a1a8e0/d .functor NAND 1, L_0x2a1aeb0, L_0x2a1a380, L_0x2a1b240, C4<1>;
+L_0x2a1a8e0 .delay (10000,10000,10000) L_0x2a1a8e0/d;
+L_0x2a1a9d0/d .functor NAND 1, L_0x2a1a290, L_0x2a1a600, L_0x2a1b2e0, C4<1>;
+L_0x2a1a9d0 .delay (10000,10000,10000) L_0x2a1a9d0/d;
+L_0x2a1aac0/d .functor NAND 1, L_0x2a1aeb0, L_0x2a1a600, L_0x2a1afe0, C4<1>;
+L_0x2a1aac0 .delay (10000,10000,10000) L_0x2a1aac0/d;
+L_0x2a1ac00/d .functor NAND 1, L_0x2a1a420, L_0x2a1a8e0, L_0x2a1a9d0, L_0x2a1aac0;
+L_0x2a1ac00 .delay (10000,10000,10000) L_0x2a1ac00/d;
+v0x27f9990_0 .net "S0", 0 0, L_0x2a1aeb0; 1 drivers
+v0x27f9a50_0 .net "S1", 0 0, L_0x2a1a600; 1 drivers
+v0x27f9af0_0 .net "in0", 0 0, L_0x2a1a730; 1 drivers
+v0x27f9b90_0 .net "in1", 0 0, L_0x2a1b240; 1 drivers
+v0x27f9c10_0 .net "in2", 0 0, L_0x2a1b2e0; 1 drivers
+v0x27f9cb0_0 .net "in3", 0 0, L_0x2a1afe0; 1 drivers
+v0x27f9d90_0 .net "nS0", 0 0, L_0x2a1a290; 1 drivers
+v0x27f9e30_0 .net "nS1", 0 0, L_0x2a1a380; 1 drivers
+v0x27f9ed0_0 .net "out", 0 0, L_0x2a1ac00; 1 drivers
+v0x27f9f70_0 .net "out0", 0 0, L_0x2a1a420; 1 drivers
+v0x27fa010_0 .net "out1", 0 0, L_0x2a1a8e0; 1 drivers
+v0x27fa0b0_0 .net "out2", 0 0, L_0x2a1a9d0; 1 drivers
+v0x27fa1c0_0 .net "out3", 0 0, L_0x2a1aac0; 1 drivers
+S_0x27f9330 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f91c0;
+ .timescale -9 -12;
+L_0x2a1b0d0/d .functor NOT 1, L_0x2a1b380, C4<0>, C4<0>, C4<0>;
+L_0x2a1b0d0 .delay (10000,10000,10000) L_0x2a1b0d0/d;
+L_0x2a1b1c0/d .functor AND 1, L_0x2a1b420, L_0x2a1b0d0, C4<1>, C4<1>;
+L_0x2a1b1c0 .delay (20000,20000,20000) L_0x2a1b1c0/d;
+L_0x2a1b680/d .functor AND 1, L_0x2a1b510, L_0x2a1b380, C4<1>, C4<1>;
+L_0x2a1b680 .delay (20000,20000,20000) L_0x2a1b680/d;
+L_0x2a1b770/d .functor OR 1, L_0x2a1b1c0, L_0x2a1b680, C4<0>, C4<0>;
+L_0x2a1b770 .delay (20000,20000,20000) L_0x2a1b770/d;
+v0x27f9420_0 .net "S", 0 0, L_0x2a1b380; 1 drivers
+v0x27f94c0_0 .net "in0", 0 0, L_0x2a1b420; 1 drivers
+v0x27f9560_0 .net "in1", 0 0, L_0x2a1b510; 1 drivers
+v0x27f9600_0 .net "nS", 0 0, L_0x2a1b0d0; 1 drivers
+v0x27f9680_0 .net "out0", 0 0, L_0x2a1b1c0; 1 drivers
+v0x27f9720_0 .net "out1", 0 0, L_0x2a1b680; 1 drivers
+v0x27f9800_0 .net "outfinal", 0 0, L_0x2a1b770; 1 drivers
+S_0x27f7640 .scope generate, "muxbits[5]" "muxbits[5]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27f6638 .param/l "i" 3 397, +C4<0101>;
+L_0x2a1e020/d .functor OR 1, L_0x2a1e8a0, L_0x2a1e4c0, C4<0>, C4<0>;
+L_0x2a1e020 .delay (20000,20000,20000) L_0x2a1e020/d;
+v0x27f9060_0 .net *"_s15", 0 0, L_0x2a1e8a0; 1 drivers
+v0x27f9120_0 .net *"_s16", 0 0, L_0x2a1e4c0; 1 drivers
+S_0x27f86e0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f7640;
+ .timescale -9 -12;
+L_0x2a1bee0/d .functor NOT 1, L_0x2a1cab0, C4<0>, C4<0>, C4<0>;
+L_0x2a1bee0 .delay (10000,10000,10000) L_0x2a1bee0/d;
+L_0x2a1bf90/d .functor NOT 1, L_0x2a1c190, C4<0>, C4<0>, C4<0>;
+L_0x2a1bf90 .delay (10000,10000,10000) L_0x2a1bf90/d;
+L_0x2a1bff0/d .functor NAND 1, L_0x2a1bee0, L_0x2a1bf90, L_0x2a1c2c0, C4<1>;
+L_0x2a1bff0 .delay (10000,10000,10000) L_0x2a1bff0/d;
+L_0x2a1c4e0/d .functor NAND 1, L_0x2a1cab0, L_0x2a1bf90, L_0x2a1c360, C4<1>;
+L_0x2a1c4e0 .delay (10000,10000,10000) L_0x2a1c4e0/d;
+L_0x2a1c5d0/d .functor NAND 1, L_0x2a1bee0, L_0x2a1c190, L_0x2a1ceb0, C4<1>;
+L_0x2a1c5d0 .delay (10000,10000,10000) L_0x2a1c5d0/d;
+L_0x2a1c6c0/d .functor NAND 1, L_0x2a1cab0, L_0x2a1c190, L_0x2a1cbe0, C4<1>;
+L_0x2a1c6c0 .delay (10000,10000,10000) L_0x2a1c6c0/d;
+L_0x2a1c800/d .functor NAND 1, L_0x2a1bff0, L_0x2a1c4e0, L_0x2a1c5d0, L_0x2a1c6c0;
+L_0x2a1c800 .delay (10000,10000,10000) L_0x2a1c800/d;
+v0x27f87d0_0 .net "S0", 0 0, L_0x2a1cab0; 1 drivers
+v0x27f8890_0 .net "S1", 0 0, L_0x2a1c190; 1 drivers
+v0x27f8930_0 .net "in0", 0 0, L_0x2a1c2c0; 1 drivers
+v0x27f89d0_0 .net "in1", 0 0, L_0x2a1c360; 1 drivers
+v0x27f8a50_0 .net "in2", 0 0, L_0x2a1ceb0; 1 drivers
+v0x27f8af0_0 .net "in3", 0 0, L_0x2a1cbe0; 1 drivers
+v0x27f8b90_0 .net "nS0", 0 0, L_0x2a1bee0; 1 drivers
+v0x27f8c30_0 .net "nS1", 0 0, L_0x2a1bf90; 1 drivers
+v0x27f8cd0_0 .net "out", 0 0, L_0x2a1c800; 1 drivers
+v0x27f8d70_0 .net "out0", 0 0, L_0x2a1bff0; 1 drivers
+v0x27f8e10_0 .net "out1", 0 0, L_0x2a1c4e0; 1 drivers
+v0x27f8eb0_0 .net "out2", 0 0, L_0x2a1c5d0; 1 drivers
+v0x27f8fc0_0 .net "out3", 0 0, L_0x2a1c6c0; 1 drivers
+S_0x27f7d20 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f7640;
+ .timescale -9 -12;
+L_0x2a1ccd0/d .functor NOT 1, L_0x2a1cfa0, C4<0>, C4<0>, C4<0>;
+L_0x2a1ccd0 .delay (10000,10000,10000) L_0x2a1ccd0/d;
+L_0x2a1cd80/d .functor NOT 1, L_0x2a1d0d0, C4<0>, C4<0>, C4<0>;
+L_0x2a1cd80 .delay (10000,10000,10000) L_0x2a1cd80/d;
+L_0x2a1ce20/d .functor NAND 1, L_0x2a1ccd0, L_0x2a1cd80, L_0x2a1dc60, C4<1>;
+L_0x2a1ce20 .delay (10000,10000,10000) L_0x2a1ce20/d;
+L_0x2a1d360/d .functor NAND 1, L_0x2a1cfa0, L_0x2a1cd80, L_0x2a1dd00, C4<1>;
+L_0x2a1d360 .delay (10000,10000,10000) L_0x2a1d360/d;
+L_0x2a1d450/d .functor NAND 1, L_0x2a1ccd0, L_0x2a1d0d0, L_0x2a1d960, C4<1>;
+L_0x2a1d450 .delay (10000,10000,10000) L_0x2a1d450/d;
+L_0x2a1d540/d .functor NAND 1, L_0x2a1cfa0, L_0x2a1d0d0, L_0x2a1da50, C4<1>;
+L_0x2a1d540 .delay (10000,10000,10000) L_0x2a1d540/d;
+L_0x2a1d6b0/d .functor NAND 1, L_0x2a1ce20, L_0x2a1d360, L_0x2a1d450, L_0x2a1d540;
+L_0x2a1d6b0 .delay (10000,10000,10000) L_0x2a1d6b0/d;
+v0x27f7e10_0 .net "S0", 0 0, L_0x2a1cfa0; 1 drivers
+v0x27f7ed0_0 .net "S1", 0 0, L_0x2a1d0d0; 1 drivers
+v0x27f7f70_0 .net "in0", 0 0, L_0x2a1dc60; 1 drivers
+v0x27f8010_0 .net "in1", 0 0, L_0x2a1dd00; 1 drivers
+v0x27f8090_0 .net "in2", 0 0, L_0x2a1d960; 1 drivers
+v0x27f8130_0 .net "in3", 0 0, L_0x2a1da50; 1 drivers
+v0x27f8210_0 .net "nS0", 0 0, L_0x2a1ccd0; 1 drivers
+v0x27f82b0_0 .net "nS1", 0 0, L_0x2a1cd80; 1 drivers
+v0x27f8350_0 .net "out", 0 0, L_0x2a1d6b0; 1 drivers
+v0x27f83f0_0 .net "out0", 0 0, L_0x2a1ce20; 1 drivers
+v0x27f8490_0 .net "out1", 0 0, L_0x2a1d360; 1 drivers
+v0x27f8530_0 .net "out2", 0 0, L_0x2a1d450; 1 drivers
+v0x27f8640_0 .net "out3", 0 0, L_0x2a1d540; 1 drivers
+S_0x27f77b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f7640;
+ .timescale -9 -12;
+L_0x2a1db40/d .functor NOT 1, L_0x2a1e420, C4<0>, C4<0>, C4<0>;
+L_0x2a1db40 .delay (10000,10000,10000) L_0x2a1db40/d;
+L_0x2a1d200/d .functor AND 1, L_0x2a1dda0, L_0x2a1db40, C4<1>, C4<1>;
+L_0x2a1d200 .delay (20000,20000,20000) L_0x2a1d200/d;
+L_0x2a1e150/d .functor AND 1, L_0x2a1de90, L_0x2a1e420, C4<1>, C4<1>;
+L_0x2a1e150 .delay (20000,20000,20000) L_0x2a1e150/d;
+L_0x2a1e240/d .functor OR 1, L_0x2a1d200, L_0x2a1e150, C4<0>, C4<0>;
+L_0x2a1e240 .delay (20000,20000,20000) L_0x2a1e240/d;
+v0x27f78a0_0 .net "S", 0 0, L_0x2a1e420; 1 drivers
+v0x27f7940_0 .net "in0", 0 0, L_0x2a1dda0; 1 drivers
+v0x27f79e0_0 .net "in1", 0 0, L_0x2a1de90; 1 drivers
+v0x27f7a80_0 .net "nS", 0 0, L_0x2a1db40; 1 drivers
+v0x27f7b00_0 .net "out0", 0 0, L_0x2a1d200; 1 drivers
+v0x27f7ba0_0 .net "out1", 0 0, L_0x2a1e150; 1 drivers
+v0x27f7c80_0 .net "outfinal", 0 0, L_0x2a1e240; 1 drivers
+S_0x27f5ac0 .scope generate, "muxbits[6]" "muxbits[6]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27f4ab8 .param/l "i" 3 397, +C4<0110>;
+L_0x2a20660/d .functor OR 1, L_0x2a21130, L_0x2a211d0, C4<0>, C4<0>;
+L_0x2a20660 .delay (20000,20000,20000) L_0x2a20660/d;
+v0x27f74e0_0 .net *"_s15", 0 0, L_0x2a21130; 1 drivers
+v0x27f75a0_0 .net *"_s16", 0 0, L_0x2a211d0; 1 drivers
+S_0x27f6b60 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f5ac0;
+ .timescale -9 -12;
+L_0x2a1e5b0/d .functor NOT 1, L_0x2a1e940, C4<0>, C4<0>, C4<0>;
+L_0x2a1e5b0 .delay (10000,10000,10000) L_0x2a1e5b0/d;
+L_0x2a1e6a0/d .functor NOT 1, L_0x2a1ea70, C4<0>, C4<0>, C4<0>;
+L_0x2a1e6a0 .delay (10000,10000,10000) L_0x2a1e6a0/d;
+L_0x2a1e740/d .functor NAND 1, L_0x2a1e5b0, L_0x2a1e6a0, L_0x2a1eba0, C4<1>;
+L_0x2a1e740 .delay (10000,10000,10000) L_0x2a1e740/d;
+L_0x2a1ed20/d .functor NAND 1, L_0x2a1e940, L_0x2a1e6a0, L_0x2a1f6c0, C4<1>;
+L_0x2a1ed20 .delay (10000,10000,10000) L_0x2a1ed20/d;
+L_0x2a1ee10/d .functor NAND 1, L_0x2a1e5b0, L_0x2a1ea70, L_0x2a1f350, C4<1>;
+L_0x2a1ee10 .delay (10000,10000,10000) L_0x2a1ee10/d;
+L_0x2a1ef30/d .functor NAND 1, L_0x2a1e940, L_0x2a1ea70, L_0x2a1f3f0, C4<1>;
+L_0x2a1ef30 .delay (10000,10000,10000) L_0x2a1ef30/d;
+L_0x2a1f0a0/d .functor NAND 1, L_0x2a1e740, L_0x2a1ed20, L_0x2a1ee10, L_0x2a1ef30;
+L_0x2a1f0a0 .delay (10000,10000,10000) L_0x2a1f0a0/d;
+v0x27f6c50_0 .net "S0", 0 0, L_0x2a1e940; 1 drivers
+v0x27f6d10_0 .net "S1", 0 0, L_0x2a1ea70; 1 drivers
+v0x27f6db0_0 .net "in0", 0 0, L_0x2a1eba0; 1 drivers
+v0x27f6e50_0 .net "in1", 0 0, L_0x2a1f6c0; 1 drivers
+v0x27f6ed0_0 .net "in2", 0 0, L_0x2a1f350; 1 drivers
+v0x27f6f70_0 .net "in3", 0 0, L_0x2a1f3f0; 1 drivers
+v0x27f7010_0 .net "nS0", 0 0, L_0x2a1e5b0; 1 drivers
+v0x27f70b0_0 .net "nS1", 0 0, L_0x2a1e6a0; 1 drivers
+v0x27f7150_0 .net "out", 0 0, L_0x2a1f0a0; 1 drivers
+v0x27f71f0_0 .net "out0", 0 0, L_0x2a1e740; 1 drivers
+v0x27f7290_0 .net "out1", 0 0, L_0x2a1ed20; 1 drivers
+v0x27f7330_0 .net "out2", 0 0, L_0x2a1ee10; 1 drivers
+v0x27f7440_0 .net "out3", 0 0, L_0x2a1ef30; 1 drivers
+S_0x27f61a0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f5ac0;
+ .timescale -9 -12;
+L_0x2a1f4e0/d .functor NOT 1, L_0x2a20210, C4<0>, C4<0>, C4<0>;
+L_0x2a1f4e0 .delay (10000,10000,10000) L_0x2a1f4e0/d;
+L_0x2a1f5d0/d .functor NOT 1, L_0x2a1f760, C4<0>, C4<0>, C4<0>;
+L_0x2a1f5d0 .delay (10000,10000,10000) L_0x2a1f5d0/d;
+L_0x2a1faf0/d .functor NAND 1, L_0x2a1f4e0, L_0x2a1f5d0, L_0x2a1f890, C4<1>;
+L_0x2a1faf0 .delay (10000,10000,10000) L_0x2a1faf0/d;
+L_0x2a1fbe0/d .functor NAND 1, L_0x2a20210, L_0x2a1f5d0, L_0x2a1f930, C4<1>;
+L_0x2a1fbe0 .delay (10000,10000,10000) L_0x2a1fbe0/d;
+L_0x2a1fcd0/d .functor NAND 1, L_0x2a1f4e0, L_0x2a1f760, L_0x2a1f9d0, C4<1>;
+L_0x2a1fcd0 .delay (10000,10000,10000) L_0x2a1fcd0/d;
+L_0x2a1fdf0/d .functor NAND 1, L_0x2a20210, L_0x2a1f760, L_0x2a20700, C4<1>;
+L_0x2a1fdf0 .delay (10000,10000,10000) L_0x2a1fdf0/d;
+L_0x2a1ff60/d .functor NAND 1, L_0x2a1faf0, L_0x2a1fbe0, L_0x2a1fcd0, L_0x2a1fdf0;
+L_0x2a1ff60 .delay (10000,10000,10000) L_0x2a1ff60/d;
+v0x27f6290_0 .net "S0", 0 0, L_0x2a20210; 1 drivers
+v0x27f6350_0 .net "S1", 0 0, L_0x2a1f760; 1 drivers
+v0x27f63f0_0 .net "in0", 0 0, L_0x2a1f890; 1 drivers
+v0x27f6490_0 .net "in1", 0 0, L_0x2a1f930; 1 drivers
+v0x27f6510_0 .net "in2", 0 0, L_0x2a1f9d0; 1 drivers
+v0x27f65b0_0 .net "in3", 0 0, L_0x2a20700; 1 drivers
+v0x27f6690_0 .net "nS0", 0 0, L_0x2a1f4e0; 1 drivers
+v0x27f6730_0 .net "nS1", 0 0, L_0x2a1f5d0; 1 drivers
+v0x27f67d0_0 .net "out", 0 0, L_0x2a1ff60; 1 drivers
+v0x27f6870_0 .net "out0", 0 0, L_0x2a1faf0; 1 drivers
+v0x27f6910_0 .net "out1", 0 0, L_0x2a1fbe0; 1 drivers
+v0x27f69b0_0 .net "out2", 0 0, L_0x2a1fcd0; 1 drivers
+v0x27f6ac0_0 .net "out3", 0 0, L_0x2a1fdf0; 1 drivers
+S_0x27f5c30 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f5ac0;
+ .timescale -9 -12;
+L_0x2a207f0/d .functor NOT 1, L_0x2a20340, C4<0>, C4<0>, C4<0>;
+L_0x2a207f0 .delay (10000,10000,10000) L_0x2a207f0/d;
+L_0x2a208e0/d .functor AND 1, L_0x2a203e0, L_0x2a207f0, C4<1>, C4<1>;
+L_0x2a208e0 .delay (20000,20000,20000) L_0x2a208e0/d;
+L_0x2a209d0/d .functor AND 1, L_0x2a204d0, L_0x2a20340, C4<1>, C4<1>;
+L_0x2a209d0 .delay (20000,20000,20000) L_0x2a209d0/d;
+L_0x2a20ac0/d .functor OR 1, L_0x2a208e0, L_0x2a209d0, C4<0>, C4<0>;
+L_0x2a20ac0 .delay (20000,20000,20000) L_0x2a20ac0/d;
+v0x27f5d20_0 .net "S", 0 0, L_0x2a20340; 1 drivers
+v0x27f5dc0_0 .net "in0", 0 0, L_0x2a203e0; 1 drivers
+v0x27f5e60_0 .net "in1", 0 0, L_0x2a204d0; 1 drivers
+v0x27f5f00_0 .net "nS", 0 0, L_0x2a207f0; 1 drivers
+v0x27f5f80_0 .net "out0", 0 0, L_0x2a208e0; 1 drivers
+v0x27f6020_0 .net "out1", 0 0, L_0x2a209d0; 1 drivers
+v0x27f6100_0 .net "outfinal", 0 0, L_0x2a20ac0; 1 drivers
+S_0x27f40e0 .scope generate, "muxbits[7]" "muxbits[7]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2435818 .param/l "i" 3 397, +C4<0111>;
+L_0x2a232a0/d .functor OR 1, L_0x2a233e0, L_0x2a23a20, C4<0>, C4<0>;
+L_0x2a232a0 .delay (20000,20000,20000) L_0x2a232a0/d;
+v0x27f5960_0 .net *"_s15", 0 0, L_0x2a233e0; 1 drivers
+v0x27f5a20_0 .net *"_s16", 0 0, L_0x2a23a20; 1 drivers
+S_0x27f4fe0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f40e0;
+ .timescale -9 -12;
+L_0x2a20ca0/d .functor NOT 1, L_0x2a21bd0, C4<0>, C4<0>, C4<0>;
+L_0x2a20ca0 .delay (10000,10000,10000) L_0x2a20ca0/d;
+L_0x2a20d90/d .functor NOT 1, L_0x2a212c0, C4<0>, C4<0>, C4<0>;
+L_0x2a20d90 .delay (10000,10000,10000) L_0x2a20d90/d;
+L_0x2a20e30/d .functor NAND 1, L_0x2a20ca0, L_0x2a20d90, L_0x2a213f0, C4<1>;
+L_0x2a20e30 .delay (10000,10000,10000) L_0x2a20e30/d;
+L_0x2a20f70/d .functor NAND 1, L_0x2a21bd0, L_0x2a20d90, L_0x2a21490, C4<1>;
+L_0x2a20f70 .delay (10000,10000,10000) L_0x2a20f70/d;
+L_0x2a216c0/d .functor NAND 1, L_0x2a20ca0, L_0x2a212c0, L_0x2a21530, C4<1>;
+L_0x2a216c0 .delay (10000,10000,10000) L_0x2a216c0/d;
+L_0x2a217b0/d .functor NAND 1, L_0x2a21bd0, L_0x2a212c0, L_0x2a21620, C4<1>;
+L_0x2a217b0 .delay (10000,10000,10000) L_0x2a217b0/d;
+L_0x2a21920/d .functor NAND 1, L_0x2a20e30, L_0x2a20f70, L_0x2a216c0, L_0x2a217b0;
+L_0x2a21920 .delay (10000,10000,10000) L_0x2a21920/d;
+v0x27f50d0_0 .net "S0", 0 0, L_0x2a21bd0; 1 drivers
+v0x27f5190_0 .net "S1", 0 0, L_0x2a212c0; 1 drivers
+v0x27f5230_0 .net "in0", 0 0, L_0x2a213f0; 1 drivers
+v0x27f52d0_0 .net "in1", 0 0, L_0x2a21490; 1 drivers
+v0x27f5350_0 .net "in2", 0 0, L_0x2a21530; 1 drivers
+v0x27f53f0_0 .net "in3", 0 0, L_0x2a21620; 1 drivers
+v0x27f5490_0 .net "nS0", 0 0, L_0x2a20ca0; 1 drivers
+v0x27f5530_0 .net "nS1", 0 0, L_0x2a20d90; 1 drivers
+v0x27f55d0_0 .net "out", 0 0, L_0x2a21920; 1 drivers
+v0x27f5670_0 .net "out0", 0 0, L_0x2a20e30; 1 drivers
+v0x27f5710_0 .net "out1", 0 0, L_0x2a20f70; 1 drivers
+v0x27f57b0_0 .net "out2", 0 0, L_0x2a216c0; 1 drivers
+v0x27f58c0_0 .net "out3", 0 0, L_0x2a217b0; 1 drivers
+S_0x27f4640 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f40e0;
+ .timescale -9 -12;
+L_0x2a22180/d .functor NOT 1, L_0x2a21d00, C4<0>, C4<0>, C4<0>;
+L_0x2a22180 .delay (10000,10000,10000) L_0x2a22180/d;
+L_0x2a22270/d .functor NOT 1, L_0x2a21e30, C4<0>, C4<0>, C4<0>;
+L_0x2a22270 .delay (10000,10000,10000) L_0x2a22270/d;
+L_0x2a22310/d .functor NAND 1, L_0x2a22180, L_0x2a22270, L_0x2a21f60, C4<1>;
+L_0x2a22310 .delay (10000,10000,10000) L_0x2a22310/d;
+L_0x2a22450/d .functor NAND 1, L_0x2a21d00, L_0x2a22270, L_0x2a22000, C4<1>;
+L_0x2a22450 .delay (10000,10000,10000) L_0x2a22450/d;
+L_0x2a22540/d .functor NAND 1, L_0x2a22180, L_0x2a21e30, L_0x2a22ee0, C4<1>;
+L_0x2a22540 .delay (10000,10000,10000) L_0x2a22540/d;
+L_0x2a22660/d .functor NAND 1, L_0x2a21d00, L_0x2a21e30, L_0x2a22f80, C4<1>;
+L_0x2a22660 .delay (10000,10000,10000) L_0x2a22660/d;
+L_0x2a227d0/d .functor NAND 1, L_0x2a22310, L_0x2a22450, L_0x2a22540, L_0x2a22660;
+L_0x2a227d0 .delay (10000,10000,10000) L_0x2a227d0/d;
+v0x27f4730_0 .net "S0", 0 0, L_0x2a21d00; 1 drivers
+v0x27f47d0_0 .net "S1", 0 0, L_0x2a21e30; 1 drivers
+v0x27f4870_0 .net "in0", 0 0, L_0x2a21f60; 1 drivers
+v0x27f4910_0 .net "in1", 0 0, L_0x2a22000; 1 drivers
+v0x27f4990_0 .net "in2", 0 0, L_0x2a22ee0; 1 drivers
+v0x27f4a30_0 .net "in3", 0 0, L_0x2a22f80; 1 drivers
+v0x27f4b10_0 .net "nS0", 0 0, L_0x2a22180; 1 drivers
+v0x27f4bb0_0 .net "nS1", 0 0, L_0x2a22270; 1 drivers
+v0x27f4c50_0 .net "out", 0 0, L_0x2a227d0; 1 drivers
+v0x27f4cf0_0 .net "out0", 0 0, L_0x2a22310; 1 drivers
+v0x27f4d90_0 .net "out1", 0 0, L_0x2a22450; 1 drivers
+v0x27f4e30_0 .net "out2", 0 0, L_0x2a22540; 1 drivers
+v0x27f4f40_0 .net "out3", 0 0, L_0x2a22660; 1 drivers
+S_0x27f41d0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f40e0;
+ .timescale -9 -12;
+L_0x2a226f0/d .functor NOT 1, L_0x2a234e0, C4<0>, C4<0>, C4<0>;
+L_0x2a226f0 .delay (10000,10000,10000) L_0x2a226f0/d;
+L_0x2a22ad0/d .functor AND 1, L_0x2a23070, L_0x2a226f0, C4<1>, C4<1>;
+L_0x2a22ad0 .delay (20000,20000,20000) L_0x2a22ad0/d;
+L_0x2a22bc0/d .functor AND 1, L_0x2a23110, L_0x2a234e0, C4<1>, C4<1>;
+L_0x2a22bc0 .delay (20000,20000,20000) L_0x2a22bc0/d;
+L_0x2a22cb0/d .functor OR 1, L_0x2a22ad0, L_0x2a22bc0, C4<0>, C4<0>;
+L_0x2a22cb0 .delay (20000,20000,20000) L_0x2a22cb0/d;
+v0x27f42c0_0 .net "S", 0 0, L_0x2a234e0; 1 drivers
+v0x27f4340_0 .net "in0", 0 0, L_0x2a23070; 1 drivers
+v0x27f43c0_0 .net "in1", 0 0, L_0x2a23110; 1 drivers
+v0x27f4440_0 .net "nS", 0 0, L_0x2a226f0; 1 drivers
+v0x27f44c0_0 .net "out0", 0 0, L_0x2a22ad0; 1 drivers
+v0x27f4540_0 .net "out1", 0 0, L_0x2a22bc0; 1 drivers
+v0x27f45c0_0 .net "outfinal", 0 0, L_0x2a22cb0; 1 drivers
+S_0x27f0f40 .scope generate, "muxbits[8]" "muxbits[8]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27efc68 .param/l "i" 3 397, +C4<01000>;
+L_0x2a1bd80/d .functor OR 1, L_0x2a1c0d0, L_0x2a25e30, C4<0>, C4<0>;
+L_0x2a1bd80 .delay (20000,20000,20000) L_0x2a1bd80/d;
+v0x27f3fe0_0 .net *"_s15", 0 0, L_0x2a1c0d0; 1 drivers
+v0x27f4060_0 .net *"_s16", 0 0, L_0x2a25e30; 1 drivers
+S_0x27f3800 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27f0f40;
+ .timescale -9 -12;
+L_0x2a23ac0/d .functor NOT 1, L_0x2a23580, C4<0>, C4<0>, C4<0>;
+L_0x2a23ac0 .delay (10000,10000,10000) L_0x2a23ac0/d;
+L_0x2a23bb0/d .functor NOT 1, L_0x2a236b0, C4<0>, C4<0>, C4<0>;
+L_0x2a23bb0 .delay (10000,10000,10000) L_0x2a23bb0/d;
+L_0x2a23c50/d .functor NAND 1, L_0x2a23ac0, L_0x2a23bb0, L_0x2a237e0, C4<1>;
+L_0x2a23c50 .delay (10000,10000,10000) L_0x2a23c50/d;
+L_0x2a23d90/d .functor NAND 1, L_0x2a23580, L_0x2a23bb0, L_0x2a23880, C4<1>;
+L_0x2a23d90 .delay (10000,10000,10000) L_0x2a23d90/d;
+L_0x2a23ee0/d .functor NAND 1, L_0x2a23ac0, L_0x2a236b0, L_0x2a23920, C4<1>;
+L_0x2a23ee0 .delay (10000,10000,10000) L_0x2a23ee0/d;
+L_0x2a24030/d .functor NAND 1, L_0x2a23580, L_0x2a236b0, L_0x2a24920, C4<1>;
+L_0x2a24030 .delay (10000,10000,10000) L_0x2a24030/d;
+L_0x2a241a0/d .functor NAND 1, L_0x2a23c50, L_0x2a23d90, L_0x2a23ee0, L_0x2a24030;
+L_0x2a241a0 .delay (10000,10000,10000) L_0x2a241a0/d;
+v0x27f38f0_0 .net "S0", 0 0, L_0x2a23580; 1 drivers
+v0x27f3970_0 .net "S1", 0 0, L_0x2a236b0; 1 drivers
+v0x27f39f0_0 .net "in0", 0 0, L_0x2a237e0; 1 drivers
+v0x27f3a70_0 .net "in1", 0 0, L_0x2a23880; 1 drivers
+v0x27f3af0_0 .net "in2", 0 0, L_0x2a23920; 1 drivers
+v0x27f3b70_0 .net "in3", 0 0, L_0x2a24920; 1 drivers
+v0x27f3bf0_0 .net "nS0", 0 0, L_0x2a23ac0; 1 drivers
+v0x27f3c70_0 .net "nS1", 0 0, L_0x2a23bb0; 1 drivers
+v0x27f3cf0_0 .net "out", 0 0, L_0x2a241a0; 1 drivers
+v0x27f3d70_0 .net "out0", 0 0, L_0x2a23c50; 1 drivers
+v0x27f3df0_0 .net "out1", 0 0, L_0x2a23d90; 1 drivers
+v0x27f3e70_0 .net "out2", 0 0, L_0x2a23ee0; 1 drivers
+v0x27f3f60_0 .net "out3", 0 0, L_0x2a24030; 1 drivers
+S_0x27f3020 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27f0f40;
+ .timescale -9 -12;
+L_0x2a240c0/d .functor NOT 1, L_0x2a25280, C4<0>, C4<0>, C4<0>;
+L_0x2a240c0 .delay (10000,10000,10000) L_0x2a240c0/d;
+L_0x2a244a0/d .functor NOT 1, L_0x2a24a10, C4<0>, C4<0>, C4<0>;
+L_0x2a244a0 .delay (10000,10000,10000) L_0x2a244a0/d;
+L_0x2a24500/d .functor NAND 1, L_0x2a240c0, L_0x2a244a0, L_0x2a24b40, C4<1>;
+L_0x2a24500 .delay (10000,10000,10000) L_0x2a24500/d;
+L_0x2a24600/d .functor NAND 1, L_0x2a25280, L_0x2a244a0, L_0x2a24be0, C4<1>;
+L_0x2a24600 .delay (10000,10000,10000) L_0x2a24600/d;
+L_0x2a24720/d .functor NAND 1, L_0x2a240c0, L_0x2a24a10, L_0x2a24c80, C4<1>;
+L_0x2a24720 .delay (10000,10000,10000) L_0x2a24720/d;
+L_0x2a24870/d .functor NAND 1, L_0x2a25280, L_0x2a24a10, L_0x2a24d70, C4<1>;
+L_0x2a24870 .delay (10000,10000,10000) L_0x2a24870/d;
+L_0x2a24fd0/d .functor NAND 1, L_0x2a24500, L_0x2a24600, L_0x2a24720, L_0x2a24870;
+L_0x2a24fd0 .delay (10000,10000,10000) L_0x2a24fd0/d;
+v0x27f3110_0 .net "S0", 0 0, L_0x2a25280; 1 drivers
+v0x27f3190_0 .net "S1", 0 0, L_0x2a24a10; 1 drivers
+v0x27f3210_0 .net "in0", 0 0, L_0x2a24b40; 1 drivers
+v0x27f3290_0 .net "in1", 0 0, L_0x2a24be0; 1 drivers
+v0x27f3310_0 .net "in2", 0 0, L_0x2a24c80; 1 drivers
+v0x27f3390_0 .net "in3", 0 0, L_0x2a24d70; 1 drivers
+v0x27f3410_0 .net "nS0", 0 0, L_0x2a240c0; 1 drivers
+v0x27f3490_0 .net "nS1", 0 0, L_0x2a244a0; 1 drivers
+v0x27f3510_0 .net "out", 0 0, L_0x2a24fd0; 1 drivers
+v0x27f3590_0 .net "out0", 0 0, L_0x2a24500; 1 drivers
+v0x27f3610_0 .net "out1", 0 0, L_0x2a24600; 1 drivers
+v0x27f3690_0 .net "out2", 0 0, L_0x2a24720; 1 drivers
+v0x27f3780_0 .net "out3", 0 0, L_0x2a24870; 1 drivers
+S_0x27f10b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27f0f40;
+ .timescale -9 -12;
+L_0x2473930/d .functor NOT 1, L_0x2a1b950, C4<0>, C4<0>, C4<0>;
+L_0x2473930 .delay (10000,10000,10000) L_0x2473930/d;
+L_0x2a24eb0/d .functor AND 1, L_0x2a253b0, L_0x2473930, C4<1>, C4<1>;
+L_0x2a24eb0 .delay (20000,20000,20000) L_0x2a24eb0/d;
+L_0x2a25950/d .functor AND 1, L_0x2a1bce0, L_0x2a1b950, C4<1>, C4<1>;
+L_0x2a25950 .delay (20000,20000,20000) L_0x2a25950/d;
+L_0x2a25a40/d .functor OR 1, L_0x2a24eb0, L_0x2a25950, C4<0>, C4<0>;
+L_0x2a25a40 .delay (20000,20000,20000) L_0x2a25a40/d;
+v0x27f2ca0_0 .net "S", 0 0, L_0x2a1b950; 1 drivers
+v0x27f2d20_0 .net "in0", 0 0, L_0x2a253b0; 1 drivers
+v0x27f2da0_0 .net "in1", 0 0, L_0x2a1bce0; 1 drivers
+v0x27f2e20_0 .net "nS", 0 0, L_0x2473930; 1 drivers
+v0x27f2ea0_0 .net "out0", 0 0, L_0x2a24eb0; 1 drivers
+v0x27f2f20_0 .net "out1", 0 0, L_0x2a25950; 1 drivers
+v0x27f2fa0_0 .net "outfinal", 0 0, L_0x2a25a40; 1 drivers
+S_0x20734b0 .scope generate, "muxbits[9]" "muxbits[9]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x1d2bc88 .param/l "i" 3 397, +C4<01001>;
+L_0x2a280a0/d .functor OR 1, L_0x2a281e0, L_0x2a28280, C4<0>, C4<0>;
+L_0x2a280a0 .delay (20000,20000,20000) L_0x2a280a0/d;
+v0x27f0de0_0 .net *"_s15", 0 0, L_0x2a281e0; 1 drivers
+v0x27f0ea0_0 .net *"_s16", 0 0, L_0x2a28280; 1 drivers
+S_0x1e82f90 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x20734b0;
+ .timescale -9 -12;
+L_0x2a25f20/d .functor NOT 1, L_0x2a26f70, C4<0>, C4<0>, C4<0>;
+L_0x2a25f20 .delay (10000,10000,10000) L_0x2a25f20/d;
+L_0x2a26010/d .functor NOT 1, L_0x2a26570, C4<0>, C4<0>, C4<0>;
+L_0x2a26010 .delay (10000,10000,10000) L_0x2a26010/d;
+L_0x2a260b0/d .functor NAND 1, L_0x2a25f20, L_0x2a26010, L_0x2a266a0, C4<1>;
+L_0x2a260b0 .delay (10000,10000,10000) L_0x2a260b0/d;
+L_0x2a261f0/d .functor NAND 1, L_0x2a26f70, L_0x2a26010, L_0x2a26740, C4<1>;
+L_0x2a261f0 .delay (10000,10000,10000) L_0x2a261f0/d;
+L_0x2a262e0/d .functor NAND 1, L_0x2a25f20, L_0x2a26570, L_0x2a267e0, C4<1>;
+L_0x2a262e0 .delay (10000,10000,10000) L_0x2a262e0/d;
+L_0x2a26b50/d .functor NAND 1, L_0x2a26f70, L_0x2a26570, L_0x2a268d0, C4<1>;
+L_0x2a26b50 .delay (10000,10000,10000) L_0x2a26b50/d;
+L_0x2a26cc0/d .functor NAND 1, L_0x2a260b0, L_0x2a261f0, L_0x2a262e0, L_0x2a26b50;
+L_0x2a26cc0 .delay (10000,10000,10000) L_0x2a26cc0/d;
+v0x1e83080_0 .net "S0", 0 0, L_0x2a26f70; 1 drivers
+v0x1e83140_0 .net "S1", 0 0, L_0x2a26570; 1 drivers
+v0x27f06b0_0 .net "in0", 0 0, L_0x2a266a0; 1 drivers
+v0x27f0750_0 .net "in1", 0 0, L_0x2a26740; 1 drivers
+v0x27f07d0_0 .net "in2", 0 0, L_0x2a267e0; 1 drivers
+v0x27f0870_0 .net "in3", 0 0, L_0x2a268d0; 1 drivers
+v0x27f0910_0 .net "nS0", 0 0, L_0x2a25f20; 1 drivers
+v0x27f09b0_0 .net "nS1", 0 0, L_0x2a26010; 1 drivers
+v0x27f0a50_0 .net "out", 0 0, L_0x2a26cc0; 1 drivers
+v0x27f0af0_0 .net "out0", 0 0, L_0x2a260b0; 1 drivers
+v0x27f0b90_0 .net "out1", 0 0, L_0x2a261f0; 1 drivers
+v0x27f0c30_0 .net "out2", 0 0, L_0x2a262e0; 1 drivers
+v0x27f0d40_0 .net "out3", 0 0, L_0x2a26b50; 1 drivers
+S_0x1f2b3b0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x20734b0;
+ .timescale -9 -12;
+L_0x2a269c0/d .functor NOT 1, L_0x2a270a0, C4<0>, C4<0>, C4<0>;
+L_0x2a269c0 .delay (10000,10000,10000) L_0x2a269c0/d;
+L_0x2a26a60/d .functor NOT 1, L_0x2a271d0, C4<0>, C4<0>, C4<0>;
+L_0x2a26a60 .delay (10000,10000,10000) L_0x2a26a60/d;
+L_0x2a276b0/d .functor NAND 1, L_0x2a269c0, L_0x2a26a60, L_0x2a27300, C4<1>;
+L_0x2a276b0 .delay (10000,10000,10000) L_0x2a276b0/d;
+L_0x2a277f0/d .functor NAND 1, L_0x2a270a0, L_0x2a26a60, L_0x2a273a0, C4<1>;
+L_0x2a277f0 .delay (10000,10000,10000) L_0x2a277f0/d;
+L_0x2a278e0/d .functor NAND 1, L_0x2a269c0, L_0x2a271d0, L_0x2a27440, C4<1>;
+L_0x2a278e0 .delay (10000,10000,10000) L_0x2a278e0/d;
+L_0x2a27a00/d .functor NAND 1, L_0x2a270a0, L_0x2a271d0, L_0x2a27530, C4<1>;
+L_0x2a27a00 .delay (10000,10000,10000) L_0x2a27a00/d;
+L_0x2a27b70/d .functor NAND 1, L_0x2a276b0, L_0x2a277f0, L_0x2a278e0, L_0x2a27a00;
+L_0x2a27b70 .delay (10000,10000,10000) L_0x2a27b70/d;
+v0x1e82770_0 .net "S0", 0 0, L_0x2a270a0; 1 drivers
+v0x1e82830_0 .net "S1", 0 0, L_0x2a271d0; 1 drivers
+v0x1e828d0_0 .net "in0", 0 0, L_0x2a27300; 1 drivers
+v0x1e82970_0 .net "in1", 0 0, L_0x2a273a0; 1 drivers
+v0x1e829f0_0 .net "in2", 0 0, L_0x2a27440; 1 drivers
+v0x1e82a90_0 .net "in3", 0 0, L_0x2a27530; 1 drivers
+v0x1e82b30_0 .net "nS0", 0 0, L_0x2a269c0; 1 drivers
+v0x1e82bd0_0 .net "nS1", 0 0, L_0x2a26a60; 1 drivers
+v0x1e82c70_0 .net "out", 0 0, L_0x2a27b70; 1 drivers
+v0x1e82d10_0 .net "out0", 0 0, L_0x2a276b0; 1 drivers
+v0x1e82db0_0 .net "out1", 0 0, L_0x2a277f0; 1 drivers
+v0x1e82e50_0 .net "out2", 0 0, L_0x2a278e0; 1 drivers
+v0x1e82ef0_0 .net "out3", 0 0, L_0x2a27a00; 1 drivers
+S_0x20735e0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x20734b0;
+ .timescale -9 -12;
+L_0x2a283e0/d .functor NOT 1, L_0x2a28890, C4<0>, C4<0>, C4<0>;
+L_0x2a283e0 .delay (10000,10000,10000) L_0x2a283e0/d;
+L_0x2a284d0/d .functor AND 1, L_0x2a27e20, L_0x2a283e0, C4<1>, C4<1>;
+L_0x2a284d0 .delay (20000,20000,20000) L_0x2a284d0/d;
+L_0x2a285c0/d .functor AND 1, L_0x2a27f10, L_0x2a28890, C4<1>, C4<1>;
+L_0x2a285c0 .delay (20000,20000,20000) L_0x2a285c0/d;
+L_0x2a286b0/d .functor OR 1, L_0x2a284d0, L_0x2a285c0, C4<0>, C4<0>;
+L_0x2a286b0 .delay (20000,20000,20000) L_0x2a286b0/d;
+v0x20736d0_0 .net "S", 0 0, L_0x2a28890; 1 drivers
+v0x2073770_0 .net "in0", 0 0, L_0x2a27e20; 1 drivers
+v0x1f2b0b0_0 .net "in1", 0 0, L_0x2a27f10; 1 drivers
+v0x1f2b150_0 .net "nS", 0 0, L_0x2a283e0; 1 drivers
+v0x1f2b1d0_0 .net "out0", 0 0, L_0x2a284d0; 1 drivers
+v0x1f2b270_0 .net "out1", 0 0, L_0x2a285c0; 1 drivers
+v0x1f2b310_0 .net "outfinal", 0 0, L_0x2a286b0; 1 drivers
+S_0x1d2e680 .scope generate, "muxbits[10]" "muxbits[10]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x26814c8 .param/l "i" 3 397, +C4<01010>;
+L_0x2a2a970/d .functor OR 1, L_0x2a2aab0, L_0x2a2ab50, C4<0>, C4<0>;
+L_0x2a2a970 .delay (20000,20000,20000) L_0x2a2a970/d;
+v0x27efbc0_0 .net *"_s15", 0 0, L_0x2a2aab0; 1 drivers
+v0x2073410_0 .net *"_s16", 0 0, L_0x2a2ab50; 1 drivers
+S_0x1d3d400 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x1d2e680;
+ .timescale -9 -12;
+L_0x2a28370/d .functor NOT 1, L_0x2a28930, C4<0>, C4<0>, C4<0>;
+L_0x2a28370 .delay (10000,10000,10000) L_0x2a28370/d;
+L_0x2a28fb0/d .functor NOT 1, L_0x2a28a60, C4<0>, C4<0>, C4<0>;
+L_0x2a28fb0 .delay (10000,10000,10000) L_0x2a28fb0/d;
+L_0x2a29050/d .functor NAND 1, L_0x2a28370, L_0x2a28fb0, L_0x2a28b90, C4<1>;
+L_0x2a29050 .delay (10000,10000,10000) L_0x2a29050/d;
+L_0x2a29190/d .functor NAND 1, L_0x2a28930, L_0x2a28fb0, L_0x2a28c30, C4<1>;
+L_0x2a29190 .delay (10000,10000,10000) L_0x2a29190/d;
+L_0x2a29280/d .functor NAND 1, L_0x2a28370, L_0x2a28a60, L_0x2a28cd0, C4<1>;
+L_0x2a29280 .delay (10000,10000,10000) L_0x2a29280/d;
+L_0x2a293a0/d .functor NAND 1, L_0x2a28930, L_0x2a28a60, L_0x2a28dc0, C4<1>;
+L_0x2a293a0 .delay (10000,10000,10000) L_0x2a293a0/d;
+L_0x2a29510/d .functor NAND 1, L_0x2a29050, L_0x2a29190, L_0x2a29280, L_0x2a293a0;
+L_0x2a29510 .delay (10000,10000,10000) L_0x2a29510/d;
+v0x1d3d4f0_0 .net "S0", 0 0, L_0x2a28930; 1 drivers
+v0x1d3d5b0_0 .net "S1", 0 0, L_0x2a28a60; 1 drivers
+v0x1d2a250_0 .net "in0", 0 0, L_0x2a28b90; 1 drivers
+v0x1d2a2f0_0 .net "in1", 0 0, L_0x2a28c30; 1 drivers
+v0x1d2a370_0 .net "in2", 0 0, L_0x2a28cd0; 1 drivers
+v0x1d2a410_0 .net "in3", 0 0, L_0x2a28dc0; 1 drivers
+v0x1d4dac0_0 .net "nS0", 0 0, L_0x2a28370; 1 drivers
+v0x1d4db60_0 .net "nS1", 0 0, L_0x2a28fb0; 1 drivers
+v0x1d4dc00_0 .net "out", 0 0, L_0x2a29510; 1 drivers
+v0x1d4dca0_0 .net "out0", 0 0, L_0x2a29050; 1 drivers
+v0x27ef970_0 .net "out1", 0 0, L_0x2a29190; 1 drivers
+v0x27efa10_0 .net "out2", 0 0, L_0x2a29280; 1 drivers
+v0x27efb20_0 .net "out3", 0 0, L_0x2a293a0; 1 drivers
+S_0x1d2ba30 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x1d2e680;
+ .timescale -9 -12;
+L_0x2a28eb0/d .functor NOT 1, L_0x2a2a660, C4<0>, C4<0>, C4<0>;
+L_0x2a28eb0 .delay (10000,10000,10000) L_0x2a28eb0/d;
+L_0x2a29e80/d .functor NOT 1, L_0x2a297c0, C4<0>, C4<0>, C4<0>;
+L_0x2a29e80 .delay (10000,10000,10000) L_0x2a29e80/d;
+L_0x2a29f20/d .functor NAND 1, L_0x2a28eb0, L_0x2a29e80, L_0x2a298f0, C4<1>;
+L_0x2a29f20 .delay (10000,10000,10000) L_0x2a29f20/d;
+L_0x2a2a060/d .functor NAND 1, L_0x2a2a660, L_0x2a29e80, L_0x2a29990, C4<1>;
+L_0x2a2a060 .delay (10000,10000,10000) L_0x2a2a060/d;
+L_0x2a2a150/d .functor NAND 1, L_0x2a28eb0, L_0x2a297c0, L_0x2a29a30, C4<1>;
+L_0x2a2a150 .delay (10000,10000,10000) L_0x2a2a150/d;
+L_0x2a2a240/d .functor NAND 1, L_0x2a2a660, L_0x2a297c0, L_0x2a29b20, C4<1>;
+L_0x2a2a240 .delay (10000,10000,10000) L_0x2a2a240/d;
+L_0x2a2a3b0/d .functor NAND 1, L_0x2a29f20, L_0x2a2a060, L_0x2a2a150, L_0x2a2a240;
+L_0x2a2a3b0 .delay (10000,10000,10000) L_0x2a2a3b0/d;
+v0x1d2bb20_0 .net "S0", 0 0, L_0x2a2a660; 1 drivers
+v0x1d2bbe0_0 .net "S1", 0 0, L_0x2a297c0; 1 drivers
+v0x1d32190_0 .net "in0", 0 0, L_0x2a298f0; 1 drivers
+v0x1d32230_0 .net "in1", 0 0, L_0x2a29990; 1 drivers
+v0x1d322b0_0 .net "in2", 0 0, L_0x2a29a30; 1 drivers
+v0x1d32350_0 .net "in3", 0 0, L_0x2a29b20; 1 drivers
+v0x1d2fbf0_0 .net "nS0", 0 0, L_0x2a28eb0; 1 drivers
+v0x1d2fc90_0 .net "nS1", 0 0, L_0x2a29e80; 1 drivers
+v0x1d2fd30_0 .net "out", 0 0, L_0x2a2a3b0; 1 drivers
+v0x1d2fdd0_0 .net "out0", 0 0, L_0x2a29f20; 1 drivers
+v0x1d374a0_0 .net "out1", 0 0, L_0x2a2a060; 1 drivers
+v0x1d37540_0 .net "out2", 0 0, L_0x2a2a150; 1 drivers
+v0x1d37650_0 .net "out3", 0 0, L_0x2a2a240; 1 drivers
+S_0x1d35290 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x1d2e680;
+ .timescale -9 -12;
+L_0x2a29c10/d .functor NOT 1, L_0x2a0e1f0, C4<0>, C4<0>, C4<0>;
+L_0x2a29c10 .delay (10000,10000,10000) L_0x2a29c10/d;
+L_0x2a29d00/d .functor AND 1, L_0x2a0e290, L_0x2a29c10, C4<1>, C4<1>;
+L_0x2a29d00 .delay (20000,20000,20000) L_0x2a29d00/d;
+L_0x2a0df20/d .functor AND 1, L_0x2a2a7e0, L_0x2a0e1f0, C4<1>, C4<1>;
+L_0x2a0df20 .delay (20000,20000,20000) L_0x2a0df20/d;
+L_0x2a0e010/d .functor OR 1, L_0x2a29d00, L_0x2a0df20, C4<0>, C4<0>;
+L_0x2a0e010 .delay (20000,20000,20000) L_0x2a0e010/d;
+v0x1d35380_0 .net "S", 0 0, L_0x2a0e1f0; 1 drivers
+v0x1d35420_0 .net "in0", 0 0, L_0x2a0e290; 1 drivers
+v0x1d2e7b0_0 .net "in1", 0 0, L_0x2a2a7e0; 1 drivers
+v0x1d44cf0_0 .net "nS", 0 0, L_0x2a29c10; 1 drivers
+v0x1d44d70_0 .net "out0", 0 0, L_0x2a29d00; 1 drivers
+v0x1d44df0_0 .net "out1", 0 0, L_0x2a0df20; 1 drivers
+v0x1d44ed0_0 .net "outfinal", 0 0, L_0x2a0e010; 1 drivers
+S_0x2677960 .scope generate, "muxbits[11]" "muxbits[11]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x27aeeb8 .param/l "i" 3 397, +C4<01011>;
+L_0x2a2d480/d .functor OR 1, L_0x2a2d5c0, L_0x2a2d660, C4<0>, C4<0>;
+L_0x2a2d480 .delay (20000,20000,20000) L_0x2a2d480/d;
+v0x1d39b80_0 .net *"_s15", 0 0, L_0x2a2d5c0; 1 drivers
+v0x1d2e5e0_0 .net *"_s16", 0 0, L_0x2a2d660; 1 drivers
+S_0x26ba7a0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2677960;
+ .timescale -9 -12;
+L_0x2a2ac40/d .functor NOT 1, L_0x2a2c3a0, C4<0>, C4<0>, C4<0>;
+L_0x2a2ac40 .delay (10000,10000,10000) L_0x2a2ac40/d;
+L_0x2a2ad30/d .functor NOT 1, L_0x2a2b5f0, C4<0>, C4<0>, C4<0>;
+L_0x2a2ad30 .delay (10000,10000,10000) L_0x2a2ad30/d;
+L_0x2a2bc90/d .functor NAND 1, L_0x2a2ac40, L_0x2a2ad30, L_0x2a2b720, C4<1>;
+L_0x2a2bc90 .delay (10000,10000,10000) L_0x2a2bc90/d;
+L_0x2a2bdd0/d .functor NAND 1, L_0x2a2c3a0, L_0x2a2ad30, L_0x2a2b7c0, C4<1>;
+L_0x2a2bdd0 .delay (10000,10000,10000) L_0x2a2bdd0/d;
+L_0x2a2bec0/d .functor NAND 1, L_0x2a2ac40, L_0x2a2b5f0, L_0x2a2b860, C4<1>;
+L_0x2a2bec0 .delay (10000,10000,10000) L_0x2a2bec0/d;
+L_0x2a2bfb0/d .functor NAND 1, L_0x2a2c3a0, L_0x2a2b5f0, L_0x2a2b950, C4<1>;
+L_0x2a2bfb0 .delay (10000,10000,10000) L_0x2a2bfb0/d;
+L_0x2a2c0f0/d .functor NAND 1, L_0x2a2bc90, L_0x2a2bdd0, L_0x2a2bec0, L_0x2a2bfb0;
+L_0x2a2c0f0 .delay (10000,10000,10000) L_0x2a2c0f0/d;
+v0x26ba890_0 .net "S0", 0 0, L_0x2a2c3a0; 1 drivers
+v0x26bf3b0_0 .net "S1", 0 0, L_0x2a2b5f0; 1 drivers
+v0x26bf450_0 .net "in0", 0 0, L_0x2a2b720; 1 drivers
+v0x26bf4f0_0 .net "in1", 0 0, L_0x2a2b7c0; 1 drivers
+v0x26d7140_0 .net "in2", 0 0, L_0x2a2b860; 1 drivers
+v0x26d71e0_0 .net "in3", 0 0, L_0x2a2b950; 1 drivers
+v0x26d7280_0 .net "nS0", 0 0, L_0x2a2ac40; 1 drivers
+v0x1ced690_0 .net "nS1", 0 0, L_0x2a2ad30; 1 drivers
+v0x1ced730_0 .net "out", 0 0, L_0x2a2c0f0; 1 drivers
+v0x1ced7d0_0 .net "out0", 0 0, L_0x2a2bc90; 1 drivers
+v0x1ced870_0 .net "out1", 0 0, L_0x2a2bdd0; 1 drivers
+v0x1d399d0_0 .net "out2", 0 0, L_0x2a2bec0; 1 drivers
+v0x1d39ae0_0 .net "out3", 0 0, L_0x2a2bfb0; 1 drivers
+S_0x2694350 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2677960;
+ .timescale -9 -12;
+L_0x2a2ba40/d .functor NOT 1, L_0x2a2c4d0, C4<0>, C4<0>, C4<0>;
+L_0x2a2ba40 .delay (10000,10000,10000) L_0x2a2ba40/d;
+L_0x2a2bb30/d .functor NOT 1, L_0x2a2c600, C4<0>, C4<0>, C4<0>;
+L_0x2a2bb30 .delay (10000,10000,10000) L_0x2a2bb30/d;
+L_0x2a2bbd0/d .functor NAND 1, L_0x2a2ba40, L_0x2a2bb30, L_0x2a2c730, C4<1>;
+L_0x2a2bbd0 .delay (10000,10000,10000) L_0x2a2bbd0/d;
+L_0x2a2cc30/d .functor NAND 1, L_0x2a2c4d0, L_0x2a2bb30, L_0x2a2c7d0, C4<1>;
+L_0x2a2cc30 .delay (10000,10000,10000) L_0x2a2cc30/d;
+L_0x2a2cd20/d .functor NAND 1, L_0x2a2ba40, L_0x2a2c600, L_0x2a2c870, C4<1>;
+L_0x2a2cd20 .delay (10000,10000,10000) L_0x2a2cd20/d;
+L_0x2a2ce10/d .functor NAND 1, L_0x2a2c4d0, L_0x2a2c600, L_0x2a2c960, C4<1>;
+L_0x2a2ce10 .delay (10000,10000,10000) L_0x2a2ce10/d;
+L_0x2a2cf50/d .functor NAND 1, L_0x2a2bbd0, L_0x2a2cc30, L_0x2a2cd20, L_0x2a2ce10;
+L_0x2a2cf50 .delay (10000,10000,10000) L_0x2a2cf50/d;
+v0x2694440_0 .net "S0", 0 0, L_0x2a2c4d0; 1 drivers
+v0x2694500_0 .net "S1", 0 0, L_0x2a2c600; 1 drivers
+v0x2699000_0 .net "in0", 0 0, L_0x2a2c730; 1 drivers
+v0x26990a0_0 .net "in1", 0 0, L_0x2a2c7d0; 1 drivers
+v0x2699120_0 .net "in2", 0 0, L_0x2a2c870; 1 drivers
+v0x26991c0_0 .net "in3", 0 0, L_0x2a2c960; 1 drivers
+v0x269dcb0_0 .net "nS0", 0 0, L_0x2a2ba40; 1 drivers
+v0x269dd50_0 .net "nS1", 0 0, L_0x2a2bb30; 1 drivers
+v0x269ddf0_0 .net "out", 0 0, L_0x2a2cf50; 1 drivers
+v0x26b5a50_0 .net "out0", 0 0, L_0x2a2bbd0; 1 drivers
+v0x26b5af0_0 .net "out1", 0 0, L_0x2a2cc30; 1 drivers
+v0x26b5b90_0 .net "out2", 0 0, L_0x2a2cd20; 1 drivers
+v0x26ba700_0 .net "out3", 0 0, L_0x2a2ce10; 1 drivers
+S_0x267c610 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2677960;
+ .timescale -9 -12;
+L_0x2a2ca50/d .functor NOT 1, L_0x2a2dc70, C4<0>, C4<0>, C4<0>;
+L_0x2a2ca50 .delay (10000,10000,10000) L_0x2a2ca50/d;
+L_0x2a2cb40/d .functor AND 1, L_0x2a2d200, L_0x2a2ca50, C4<1>, C4<1>;
+L_0x2a2cb40 .delay (20000,20000,20000) L_0x2a2cb40/d;
+L_0x2a2d9a0/d .functor AND 1, L_0x2a2d2f0, L_0x2a2dc70, C4<1>, C4<1>;
+L_0x2a2d9a0 .delay (20000,20000,20000) L_0x2a2d9a0/d;
+L_0x2a2da90/d .functor OR 1, L_0x2a2cb40, L_0x2a2d9a0, C4<0>, C4<0>;
+L_0x2a2da90 .delay (20000,20000,20000) L_0x2a2da90/d;
+v0x267c700_0 .net "S", 0 0, L_0x2a2dc70; 1 drivers
+v0x267c7a0_0 .net "in0", 0 0, L_0x2a2d200; 1 drivers
+v0x2677ad0_0 .net "in1", 0 0, L_0x2a2d2f0; 1 drivers
+v0x2672e10_0 .net "nS", 0 0, L_0x2a2ca50; 1 drivers
+v0x26812c0_0 .net "out0", 0 0, L_0x2a2cb40; 1 drivers
+v0x2681360_0 .net "out1", 0 0, L_0x2a2d9a0; 1 drivers
+v0x2681440_0 .net "outfinal", 0 0, L_0x2a2da90; 1 drivers
+S_0x2456cf0 .scope generate, "muxbits[12]" "muxbits[12]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2793248 .param/l "i" 3 397, +C4<01100>;
+L_0x2a2fe10/d .functor OR 1, L_0x2a2ff50, L_0x2a2fff0, C4<0>, C4<0>;
+L_0x2a2fe10 .delay (20000,20000,20000) L_0x2a2fe10/d;
+v0x2672cb0_0 .net *"_s15", 0 0, L_0x2a2ff50; 1 drivers
+v0x2672d70_0 .net *"_s16", 0 0, L_0x2a2fff0; 1 drivers
+S_0x2499b90 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2456cf0;
+ .timescale -9 -12;
+L_0x2a2d750/d .functor NOT 1, L_0x2a2dd10, C4<0>, C4<0>, C4<0>;
+L_0x2a2d750 .delay (10000,10000,10000) L_0x2a2d750/d;
+L_0x2a2d840/d .functor NOT 1, L_0x2a2de40, C4<0>, C4<0>, C4<0>;
+L_0x2a2d840 .delay (10000,10000,10000) L_0x2a2d840/d;
+L_0x2a2e450/d .functor NAND 1, L_0x2a2d750, L_0x2a2d840, L_0x2a2df70, C4<1>;
+L_0x2a2e450 .delay (10000,10000,10000) L_0x2a2e450/d;
+L_0x2a2e590/d .functor NAND 1, L_0x2a2dd10, L_0x2a2d840, L_0x2a2e010, C4<1>;
+L_0x2a2e590 .delay (10000,10000,10000) L_0x2a2e590/d;
+L_0x2a2e680/d .functor NAND 1, L_0x2a2d750, L_0x2a2de40, L_0x2a2e0b0, C4<1>;
+L_0x2a2e680 .delay (10000,10000,10000) L_0x2a2e680/d;
+L_0x2a2e770/d .functor NAND 1, L_0x2a2dd10, L_0x2a2de40, L_0x2a2e1a0, C4<1>;
+L_0x2a2e770 .delay (10000,10000,10000) L_0x2a2e770/d;
+L_0x2a2e850/d .functor NAND 1, L_0x2a2e450, L_0x2a2e590, L_0x2a2e680, L_0x2a2e770;
+L_0x2a2e850 .delay (10000,10000,10000) L_0x2a2e850/d;
+v0x2499c80_0 .net "S0", 0 0, L_0x2a2dd10; 1 drivers
+v0x249e7a0_0 .net "S1", 0 0, L_0x2a2de40; 1 drivers
+v0x249e840_0 .net "in0", 0 0, L_0x2a2df70; 1 drivers
+v0x249e8e0_0 .net "in1", 0 0, L_0x2a2e010; 1 drivers
+v0x2656260_0 .net "in2", 0 0, L_0x2a2e0b0; 1 drivers
+v0x2656300_0 .net "in3", 0 0, L_0x2a2e1a0; 1 drivers
+v0x26563a0_0 .net "nS0", 0 0, L_0x2a2d750; 1 drivers
+v0x265af10_0 .net "nS1", 0 0, L_0x2a2d840; 1 drivers
+v0x265afb0_0 .net "out", 0 0, L_0x2a2e850; 1 drivers
+v0x265b050_0 .net "out0", 0 0, L_0x2a2e450; 1 drivers
+v0x265fbc0_0 .net "out1", 0 0, L_0x2a2e590; 1 drivers
+v0x265fc60_0 .net "out2", 0 0, L_0x2a2e680; 1 drivers
+v0x265fd70_0 .net "out3", 0 0, L_0x2a2e770; 1 drivers
+S_0x2478400 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2456cf0;
+ .timescale -9 -12;
+L_0x2a2e290/d .functor NOT 1, L_0x2a2f9c0, C4<0>, C4<0>, C4<0>;
+L_0x2a2e290 .delay (10000,10000,10000) L_0x2a2e290/d;
+L_0x2a2e380/d .functor NOT 1, L_0x2a2eb00, C4<0>, C4<0>, C4<0>;
+L_0x2a2e380 .delay (10000,10000,10000) L_0x2a2e380/d;
+L_0x2a2f280/d .functor NAND 1, L_0x2a2e290, L_0x2a2e380, L_0x2a2ec30, C4<1>;
+L_0x2a2f280 .delay (10000,10000,10000) L_0x2a2f280/d;
+L_0x2a2f3c0/d .functor NAND 1, L_0x2a2f9c0, L_0x2a2e380, L_0x2a2ecd0, C4<1>;
+L_0x2a2f3c0 .delay (10000,10000,10000) L_0x2a2f3c0/d;
+L_0x2a2f4b0/d .functor NAND 1, L_0x2a2e290, L_0x2a2eb00, L_0x2a2ed70, C4<1>;
+L_0x2a2f4b0 .delay (10000,10000,10000) L_0x2a2f4b0/d;
+L_0x2a2f5a0/d .functor NAND 1, L_0x2a2f9c0, L_0x2a2eb00, L_0x2a2ee60, C4<1>;
+L_0x2a2f5a0 .delay (10000,10000,10000) L_0x2a2f5a0/d;
+L_0x2a2f710/d .functor NAND 1, L_0x2a2f280, L_0x2a2f3c0, L_0x2a2f4b0, L_0x2a2f5a0;
+L_0x2a2f710 .delay (10000,10000,10000) L_0x2a2f710/d;
+v0x24784f0_0 .net "S0", 0 0, L_0x2a2f9c0; 1 drivers
+v0x24785b0_0 .net "S1", 0 0, L_0x2a2eb00; 1 drivers
+v0x247d0b0_0 .net "in0", 0 0, L_0x2a2ec30; 1 drivers
+v0x247d130_0 .net "in1", 0 0, L_0x2a2ecd0; 1 drivers
+v0x247d1b0_0 .net "in2", 0 0, L_0x2a2ed70; 1 drivers
+v0x247d250_0 .net "in3", 0 0, L_0x2a2ee60; 1 drivers
+v0x2490190_0 .net "nS0", 0 0, L_0x2a2e290; 1 drivers
+v0x2490230_0 .net "nS1", 0 0, L_0x2a2e380; 1 drivers
+v0x24902d0_0 .net "out", 0 0, L_0x2a2f710; 1 drivers
+v0x2494e40_0 .net "out0", 0 0, L_0x2a2f280; 1 drivers
+v0x2494ee0_0 .net "out1", 0 0, L_0x2a2f3c0; 1 drivers
+v0x2494f80_0 .net "out2", 0 0, L_0x2a2f4b0; 1 drivers
+v0x2499af0_0 .net "out3", 0 0, L_0x2a2f5a0; 1 drivers
+S_0x2456e20 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2456cf0;
+ .timescale -9 -12;
+L_0x2a2ef50/d .functor NOT 1, L_0x2a2faf0, C4<0>, C4<0>, C4<0>;
+L_0x2a2ef50 .delay (10000,10000,10000) L_0x2a2ef50/d;
+L_0x2a2f040/d .functor AND 1, L_0x2a2fb90, L_0x2a2ef50, C4<1>, C4<1>;
+L_0x2a2f040 .delay (20000,20000,20000) L_0x2a2f040/d;
+L_0x2a2f130/d .functor AND 1, L_0x2a2fc80, L_0x2a2faf0, C4<1>, C4<1>;
+L_0x2a2f130 .delay (20000,20000,20000) L_0x2a2f130/d;
+L_0x2a2f220/d .functor OR 1, L_0x2a2f040, L_0x2a2f130, C4<0>, C4<0>;
+L_0x2a2f220 .delay (20000,20000,20000) L_0x2a2f220/d;
+v0x245b9a0_0 .net "S", 0 0, L_0x2a2faf0; 1 drivers
+v0x245ba20_0 .net "in0", 0 0, L_0x2a2fb90; 1 drivers
+v0x245bac0_0 .net "in1", 0 0, L_0x2a2fc80; 1 drivers
+v0x245bb60_0 .net "nS", 0 0, L_0x2a2ef50; 1 drivers
+v0x2473750_0 .net "out0", 0 0, L_0x2a2f040; 1 drivers
+v0x24737f0_0 .net "out1", 0 0, L_0x2a2f130; 1 drivers
+v0x2473890_0 .net "outfinal", 0 0, L_0x2a2f220; 1 drivers
+S_0x27a0f70 .scope generate, "muxbits[13]" "muxbits[13]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2779af8 .param/l "i" 3 397, +C4<01101>;
+L_0x2a32410/d .functor OR 1, L_0x2a32550, L_0x2a325f0, C4<0>, C4<0>;
+L_0x2a32410 .delay (20000,20000,20000) L_0x2a32410/d;
+v0x24520c0_0 .net *"_s15", 0 0, L_0x2a32550; 1 drivers
+v0x2452180_0 .net *"_s16", 0 0, L_0x2a325f0; 1 drivers
+S_0x273cf00 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x27a0f70;
+ .timescale -9 -12;
+L_0x2a300e0/d .functor NOT 1, L_0x2a31350, C4<0>, C4<0>, C4<0>;
+L_0x2a300e0 .delay (10000,10000,10000) L_0x2a300e0/d;
+L_0x2a301d0/d .functor NOT 1, L_0x2a30420, C4<0>, C4<0>, C4<0>;
+L_0x2a301d0 .delay (10000,10000,10000) L_0x2a301d0/d;
+L_0x2a30c10/d .functor NAND 1, L_0x2a300e0, L_0x2a301d0, L_0x2a30550, C4<1>;
+L_0x2a30c10 .delay (10000,10000,10000) L_0x2a30c10/d;
+L_0x2a30d50/d .functor NAND 1, L_0x2a31350, L_0x2a301d0, L_0x2a305f0, C4<1>;
+L_0x2a30d50 .delay (10000,10000,10000) L_0x2a30d50/d;
+L_0x2a30e40/d .functor NAND 1, L_0x2a300e0, L_0x2a30420, L_0x2a30690, C4<1>;
+L_0x2a30e40 .delay (10000,10000,10000) L_0x2a30e40/d;
+L_0x2a30f30/d .functor NAND 1, L_0x2a31350, L_0x2a30420, L_0x2a30780, C4<1>;
+L_0x2a30f30 .delay (10000,10000,10000) L_0x2a30f30/d;
+L_0x2a310a0/d .functor NAND 1, L_0x2a30c10, L_0x2a30d50, L_0x2a30e40, L_0x2a30f30;
+L_0x2a310a0 .delay (10000,10000,10000) L_0x2a310a0/d;
+v0x273cff0_0 .net "S0", 0 0, L_0x2a31350; 1 drivers
+v0x273d0b0_0 .net "S1", 0 0, L_0x2a30420; 1 drivers
+v0x2430980_0 .net "in0", 0 0, L_0x2a30550; 1 drivers
+v0x2430a00_0 .net "in1", 0 0, L_0x2a305f0; 1 drivers
+v0x2430a80_0 .net "in2", 0 0, L_0x2a30690; 1 drivers
+v0x2430b20_0 .net "in3", 0 0, L_0x2a30780; 1 drivers
+v0x2435630_0 .net "nS0", 0 0, L_0x2a300e0; 1 drivers
+v0x24356d0_0 .net "nS1", 0 0, L_0x2a301d0; 1 drivers
+v0x2435770_0 .net "out", 0 0, L_0x2a310a0; 1 drivers
+v0x243a2e0_0 .net "out0", 0 0, L_0x2a30c10; 1 drivers
+v0x243a380_0 .net "out1", 0 0, L_0x2a30d50; 1 drivers
+v0x243a420_0 .net "out2", 0 0, L_0x2a30e40; 1 drivers
+v0x2452040_0 .net "out3", 0 0, L_0x2a30f30; 1 drivers
+S_0x27aa2f0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x27a0f70;
+ .timescale -9 -12;
+L_0x2a30870/d .functor NOT 1, L_0x2a31480, C4<0>, C4<0>, C4<0>;
+L_0x2a30870 .delay (10000,10000,10000) L_0x2a30870/d;
+L_0x2a30920/d .functor NOT 1, L_0x2a315b0, C4<0>, C4<0>, C4<0>;
+L_0x2a30920 .delay (10000,10000,10000) L_0x2a30920/d;
+L_0x2a309c0/d .functor NAND 1, L_0x2a30870, L_0x2a30920, L_0x2a316e0, C4<1>;
+L_0x2a309c0 .delay (10000,10000,10000) L_0x2a309c0/d;
+L_0x2a30b00/d .functor NAND 1, L_0x2a31480, L_0x2a30920, L_0x2a31780, C4<1>;
+L_0x2a30b00 .delay (10000,10000,10000) L_0x2a30b00/d;
+L_0x2a31ca0/d .functor NAND 1, L_0x2a30870, L_0x2a315b0, L_0x2a31820, C4<1>;
+L_0x2a31ca0 .delay (10000,10000,10000) L_0x2a31ca0/d;
+L_0x2a31dc0/d .functor NAND 1, L_0x2a31480, L_0x2a315b0, L_0x2a31910, C4<1>;
+L_0x2a31dc0 .delay (10000,10000,10000) L_0x2a31dc0/d;
+L_0x2a31f30/d .functor NAND 1, L_0x2a309c0, L_0x2a30b00, L_0x2a31ca0, L_0x2a31dc0;
+L_0x2a31f30 .delay (10000,10000,10000) L_0x2a31f30/d;
+v0x27aa3e0_0 .net "S0", 0 0, L_0x2a31480; 1 drivers
+v0x27ac7f0_0 .net "S1", 0 0, L_0x2a315b0; 1 drivers
+v0x27ac890_0 .net "in0", 0 0, L_0x2a316e0; 1 drivers
+v0x27ac930_0 .net "in1", 0 0, L_0x2a31780; 1 drivers
+v0x27aecf0_0 .net "in2", 0 0, L_0x2a31820; 1 drivers
+v0x27aed90_0 .net "in3", 0 0, L_0x2a31910; 1 drivers
+v0x27aee30_0 .net "nS0", 0 0, L_0x2a30870; 1 drivers
+v0x22fb980_0 .net "nS1", 0 0, L_0x2a30920; 1 drivers
+v0x22fba00_0 .net "out", 0 0, L_0x2a31f30; 1 drivers
+v0x22fbaa0_0 .net "out0", 0 0, L_0x2a309c0; 1 drivers
+v0x25128e0_0 .net "out1", 0 0, L_0x2a30b00; 1 drivers
+v0x2512980_0 .net "out2", 0 0, L_0x2a31ca0; 1 drivers
+v0x2512a20_0 .net "out3", 0 0, L_0x2a31dc0; 1 drivers
+S_0x27a33e0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x27a0f70;
+ .timescale -9 -12;
+L_0x2a31a00/d .functor NOT 1, L_0x2a32c10, C4<0>, C4<0>, C4<0>;
+L_0x2a31a00 .delay (10000,10000,10000) L_0x2a31a00/d;
+L_0x2a31ab0/d .functor AND 1, L_0x2a321e0, L_0x2a31a00, C4<1>, C4<1>;
+L_0x2a31ab0 .delay (20000,20000,20000) L_0x2a31ab0/d;
+L_0x2a31ba0/d .functor AND 1, L_0x2a32280, L_0x2a32c10, C4<1>, C4<1>;
+L_0x2a31ba0 .delay (20000,20000,20000) L_0x2a31ba0/d;
+L_0x2a31c40/d .functor OR 1, L_0x2a31ab0, L_0x2a31ba0, C4<0>, C4<0>;
+L_0x2a31c40 .delay (20000,20000,20000) L_0x2a31c40/d;
+v0x27a34d0_0 .net "S", 0 0, L_0x2a32c10; 1 drivers
+v0x27a58f0_0 .net "in0", 0 0, L_0x2a321e0; 1 drivers
+v0x27a5990_0 .net "in1", 0 0, L_0x2a32280; 1 drivers
+v0x27a5a30_0 .net "nS", 0 0, L_0x2a31a00; 1 drivers
+v0x27a7df0_0 .net "out0", 0 0, L_0x2a31ab0; 1 drivers
+v0x27a7e90_0 .net "out1", 0 0, L_0x2a31ba0; 1 drivers
+v0x27a7f30_0 .net "outfinal", 0 0, L_0x2a31c40; 1 drivers
+S_0x2780860 .scope generate, "muxbits[14]" "muxbits[14]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2765d48 .param/l "i" 3 397, +C4<01110>;
+L_0x2a34dc0/d .functor OR 1, L_0x2a34f00, L_0x2a34fa0, C4<0>, C4<0>;
+L_0x2a34dc0 .delay (20000,20000,20000) L_0x2a34dc0/d;
+v0x279eb00_0 .net *"_s15", 0 0, L_0x2a34f00; 1 drivers
+v0x27a0ed0_0 .net *"_s16", 0 0, L_0x2a34fa0; 1 drivers
+S_0x2795580 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2780860;
+ .timescale -9 -12;
+L_0x2a326e0/d .functor NOT 1, L_0x2a32cb0, C4<0>, C4<0>, C4<0>;
+L_0x2a326e0 .delay (10000,10000,10000) L_0x2a326e0/d;
+L_0x2a327d0/d .functor NOT 1, L_0x2a32de0, C4<0>, C4<0>, C4<0>;
+L_0x2a327d0 .delay (10000,10000,10000) L_0x2a327d0/d;
+L_0x2a32870/d .functor NAND 1, L_0x2a326e0, L_0x2a327d0, L_0x2a32f10, C4<1>;
+L_0x2a32870 .delay (10000,10000,10000) L_0x2a32870/d;
+L_0x2a329b0/d .functor NAND 1, L_0x2a32cb0, L_0x2a327d0, L_0x2a32fb0, C4<1>;
+L_0x2a329b0 .delay (10000,10000,10000) L_0x2a329b0/d;
+L_0x2a335d0/d .functor NAND 1, L_0x2a326e0, L_0x2a32de0, L_0x2a33050, C4<1>;
+L_0x2a335d0 .delay (10000,10000,10000) L_0x2a335d0/d;
+L_0x2a336c0/d .functor NAND 1, L_0x2a32cb0, L_0x2a32de0, L_0x2a33140, C4<1>;
+L_0x2a336c0 .delay (10000,10000,10000) L_0x2a336c0/d;
+L_0x2a33830/d .functor NAND 1, L_0x2a32870, L_0x2a329b0, L_0x2a335d0, L_0x2a336c0;
+L_0x2a33830 .delay (10000,10000,10000) L_0x2a33830/d;
+v0x2795670_0 .net "S0", 0 0, L_0x2a32cb0; 1 drivers
+v0x27931c0_0 .net "S1", 0 0, L_0x2a32de0; 1 drivers
+v0x2797a90_0 .net "in0", 0 0, L_0x2a32f10; 1 drivers
+v0x2797b10_0 .net "in1", 0 0, L_0x2a32fb0; 1 drivers
+v0x2797b90_0 .net "in2", 0 0, L_0x2a33050; 1 drivers
+v0x2799fa0_0 .net "in3", 0 0, L_0x2a33140; 1 drivers
+v0x279a040_0 .net "nS0", 0 0, L_0x2a326e0; 1 drivers
+v0x279a0e0_0 .net "nS1", 0 0, L_0x2a327d0; 1 drivers
+v0x279c4b0_0 .net "out", 0 0, L_0x2a33830; 1 drivers
+v0x279c530_0 .net "out0", 0 0, L_0x2a32870; 1 drivers
+v0x279c5d0_0 .net "out1", 0 0, L_0x2a329b0; 1 drivers
+v0x279e9c0_0 .net "out2", 0 0, L_0x2a335d0; 1 drivers
+v0x279ea60_0 .net "out3", 0 0, L_0x2a336c0; 1 drivers
+S_0x2789c80 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2780860;
+ .timescale -9 -12;
+L_0x2a33230/d .functor NOT 1, L_0x2a34970, C4<0>, C4<0>, C4<0>;
+L_0x2a33230 .delay (10000,10000,10000) L_0x2a33230/d;
+L_0x2a33320/d .functor NOT 1, L_0x2a33ae0, C4<0>, C4<0>, C4<0>;
+L_0x2a33320 .delay (10000,10000,10000) L_0x2a33320/d;
+L_0x2a333c0/d .functor NAND 1, L_0x2a33230, L_0x2a33320, L_0x2a33c10, C4<1>;
+L_0x2a333c0 .delay (10000,10000,10000) L_0x2a333c0/d;
+L_0x2a343b0/d .functor NAND 1, L_0x2a34970, L_0x2a33320, L_0x2a33cb0, C4<1>;
+L_0x2a343b0 .delay (10000,10000,10000) L_0x2a343b0/d;
+L_0x2a34460/d .functor NAND 1, L_0x2a33230, L_0x2a33ae0, L_0x2a33d50, C4<1>;
+L_0x2a34460 .delay (10000,10000,10000) L_0x2a34460/d;
+L_0x2a34550/d .functor NAND 1, L_0x2a34970, L_0x2a33ae0, L_0x2a33e40, C4<1>;
+L_0x2a34550 .delay (10000,10000,10000) L_0x2a34550/d;
+L_0x2a346c0/d .functor NAND 1, L_0x2a333c0, L_0x2a343b0, L_0x2a34460, L_0x2a34550;
+L_0x2a346c0 .delay (10000,10000,10000) L_0x2a346c0/d;
+v0x2789d70_0 .net "S0", 0 0, L_0x2a34970; 1 drivers
+v0x27878c0_0 .net "S1", 0 0, L_0x2a33ae0; 1 drivers
+v0x278c180_0 .net "in0", 0 0, L_0x2a33c10; 1 drivers
+v0x278c220_0 .net "in1", 0 0, L_0x2a33cb0; 1 drivers
+v0x278c2a0_0 .net "in2", 0 0, L_0x2a33d50; 1 drivers
+v0x278e680_0 .net "in3", 0 0, L_0x2a33e40; 1 drivers
+v0x278e720_0 .net "nS0", 0 0, L_0x2a33230; 1 drivers
+v0x278e7c0_0 .net "nS1", 0 0, L_0x2a33320; 1 drivers
+v0x2790b80_0 .net "out", 0 0, L_0x2a346c0; 1 drivers
+v0x2790c00_0 .net "out0", 0 0, L_0x2a333c0; 1 drivers
+v0x2790ca0_0 .net "out1", 0 0, L_0x2a343b0; 1 drivers
+v0x2793080_0 .net "out2", 0 0, L_0x2a34460; 1 drivers
+v0x2793120_0 .net "out3", 0 0, L_0x2a34550; 1 drivers
+S_0x2782d70 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2780860;
+ .timescale -9 -12;
+L_0x2a33f30/d .functor NOT 1, L_0x2a34aa0, C4<0>, C4<0>, C4<0>;
+L_0x2a33f30 .delay (10000,10000,10000) L_0x2a33f30/d;
+L_0x2a34020/d .functor AND 1, L_0x2a34b40, L_0x2a33f30, C4<1>, C4<1>;
+L_0x2a34020 .delay (20000,20000,20000) L_0x2a34020/d;
+L_0x2a34110/d .functor AND 1, L_0x2a34c30, L_0x2a34aa0, C4<1>, C4<1>;
+L_0x2a34110 .delay (20000,20000,20000) L_0x2a34110/d;
+L_0x2a34200/d .functor OR 1, L_0x2a34020, L_0x2a34110, C4<0>, C4<0>;
+L_0x2a34200 .delay (20000,20000,20000) L_0x2a34200/d;
+v0x2782e60_0 .net "S", 0 0, L_0x2a34aa0; 1 drivers
+v0x2780990_0 .net "in0", 0 0, L_0x2a34b40; 1 drivers
+v0x2785280_0 .net "in1", 0 0, L_0x2a34c30; 1 drivers
+v0x2785320_0 .net "nS", 0 0, L_0x2a33f30; 1 drivers
+v0x27853a0_0 .net "out0", 0 0, L_0x2a34020; 1 drivers
+v0x2787780_0 .net "out1", 0 0, L_0x2a34110; 1 drivers
+v0x2787820_0 .net "outfinal", 0 0, L_0x2a34200; 1 drivers
+S_0x2752b00 .scope generate, "muxbits[15]" "muxbits[15]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2745328 .param/l "i" 3 397, +C4<01111>;
+L_0x2a375d0/d .functor OR 1, L_0x2a37710, L_0x2a377b0, C4<0>, C4<0>;
+L_0x2a375d0 .delay (20000,20000,20000) L_0x2a375d0/d;
+v0x277e3f0_0 .net *"_s15", 0 0, L_0x2a37710; 1 drivers
+v0x277e4b0_0 .net *"_s16", 0 0, L_0x2a377b0; 1 drivers
+S_0x2772ab0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2752b00;
+ .timescale -9 -12;
+L_0x2a35090/d .functor NOT 1, L_0x2a36340, C4<0>, C4<0>, C4<0>;
+L_0x2a35090 .delay (10000,10000,10000) L_0x2a35090/d;
+L_0x2a35180/d .functor NOT 1, L_0x2a35440, C4<0>, C4<0>, C4<0>;
+L_0x2a35180 .delay (10000,10000,10000) L_0x2a35180/d;
+L_0x2a35220/d .functor NAND 1, L_0x2a35090, L_0x2a35180, L_0x2a35570, C4<1>;
+L_0x2a35220 .delay (10000,10000,10000) L_0x2a35220/d;
+L_0x2a34340/d .functor NAND 1, L_0x2a36340, L_0x2a35180, L_0x2986f60, C4<1>;
+L_0x2a34340 .delay (10000,10000,10000) L_0x2a34340/d;
+L_0x2a35dd0/d .functor NAND 1, L_0x2a35090, L_0x2a35440, L_0x2987000, C4<1>;
+L_0x2a35dd0 .delay (10000,10000,10000) L_0x2a35dd0/d;
+L_0x2a35f20/d .functor NAND 1, L_0x2a36340, L_0x2a35440, L_0x29870f0, C4<1>;
+L_0x2a35f20 .delay (10000,10000,10000) L_0x2a35f20/d;
+L_0x2a36090/d .functor NAND 1, L_0x2a35220, L_0x2a34340, L_0x2a35dd0, L_0x2a35f20;
+L_0x2a36090 .delay (10000,10000,10000) L_0x2a36090/d;
+v0x2774f10_0 .net "S0", 0 0, L_0x2a36340; 1 drivers
+v0x2774fd0_0 .net "S1", 0 0, L_0x2a35440; 1 drivers
+v0x2775070_0 .net "in0", 0 0, L_0x2a35570; 1 drivers
+v0x2777420_0 .net "in1", 0 0, L_0x2986f60; 1 drivers
+v0x27774a0_0 .net "in2", 0 0, L_0x2987000; 1 drivers
+v0x2777540_0 .net "in3", 0 0, L_0x29870f0; 1 drivers
+v0x2779930_0 .net "nS0", 0 0, L_0x2a35090; 1 drivers
+v0x27799d0_0 .net "nS1", 0 0, L_0x2a35180; 1 drivers
+v0x2779a70_0 .net "out", 0 0, L_0x2a36090; 1 drivers
+v0x277be40_0 .net "out0", 0 0, L_0x2a35220; 1 drivers
+v0x277bec0_0 .net "out1", 0 0, L_0x2a34340; 1 drivers
+v0x277bf60_0 .net "out2", 0 0, L_0x2a35dd0; 1 drivers
+v0x277e350_0 .net "out3", 0 0, L_0x2a35f20; 1 drivers
+S_0x27b1290 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2752b00;
+ .timescale -9 -12;
+L_0x29871e0/d .functor NOT 1, L_0x2a36470, C4<0>, C4<0>, C4<0>;
+L_0x29871e0 .delay (10000,10000,10000) L_0x29871e0/d;
+L_0x29872d0/d .functor NOT 1, L_0x2a365a0, C4<0>, C4<0>, C4<0>;
+L_0x29872d0 .delay (10000,10000,10000) L_0x29872d0/d;
+L_0x2a35610/d .functor NAND 1, L_0x29871e0, L_0x29872d0, L_0x2a366d0, C4<1>;
+L_0x2a35610 .delay (10000,10000,10000) L_0x2a35610/d;
+L_0x2a35750/d .functor NAND 1, L_0x2a36470, L_0x29872d0, L_0x29e8f40, C4<1>;
+L_0x2a35750 .delay (10000,10000,10000) L_0x2a35750/d;
+L_0x2a35840/d .functor NAND 1, L_0x29871e0, L_0x2a365a0, L_0x29e8fe0, C4<1>;
+L_0x2a35840 .delay (10000,10000,10000) L_0x2a35840/d;
+L_0x2a35960/d .functor NAND 1, L_0x2a36470, L_0x2a365a0, L_0x29e90d0, C4<1>;
+L_0x2a35960 .delay (10000,10000,10000) L_0x2a35960/d;
+L_0x2a35ad0/d .functor NAND 1, L_0x2a35610, L_0x2a35750, L_0x2a35840, L_0x2a35960;
+L_0x2a35ad0 .delay (10000,10000,10000) L_0x2a35ad0/d;
+v0x2769560_0 .net "S0", 0 0, L_0x2a36470; 1 drivers
+v0x2769620_0 .net "S1", 0 0, L_0x2a365a0; 1 drivers
+v0x27696c0_0 .net "in0", 0 0, L_0x2a366d0; 1 drivers
+v0x276bb10_0 .net "in1", 0 0, L_0x29e8f40; 1 drivers
+v0x276bb90_0 .net "in2", 0 0, L_0x29e8fe0; 1 drivers
+v0x276bc30_0 .net "in3", 0 0, L_0x29e90d0; 1 drivers
+v0x276e010_0 .net "nS0", 0 0, L_0x29871e0; 1 drivers
+v0x276e0b0_0 .net "nS1", 0 0, L_0x29872d0; 1 drivers
+v0x276e150_0 .net "out", 0 0, L_0x2a35ad0; 1 drivers
+v0x2770510_0 .net "out0", 0 0, L_0x2a35610; 1 drivers
+v0x2770590_0 .net "out1", 0 0, L_0x2a35750; 1 drivers
+v0x2770630_0 .net "out2", 0 0, L_0x2a35840; 1 drivers
+v0x2772a10_0 .net "out3", 0 0, L_0x2a35960; 1 drivers
+S_0x2764580 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2752b00;
+ .timescale -9 -12;
+L_0x29e91c0/d .functor NOT 1, L_0x2a36a90, C4<0>, C4<0>, C4<0>;
+L_0x29e91c0 .delay (10000,10000,10000) L_0x29e91c0/d;
+L_0x29e92b0/d .functor AND 1, L_0x2a36b30, L_0x29e91c0, C4<1>, C4<1>;
+L_0x29e92b0 .delay (20000,20000,20000) L_0x29e92b0/d;
+L_0x2a367c0/d .functor AND 1, L_0x2a36c20, L_0x2a36a90, C4<1>, C4<1>;
+L_0x2a367c0 .delay (20000,20000,20000) L_0x2a367c0/d;
+L_0x2a368b0/d .functor OR 1, L_0x29e92b0, L_0x2a367c0, C4<0>, C4<0>;
+L_0x2a368b0 .delay (20000,20000,20000) L_0x2a368b0/d;
+v0x2764670_0 .net "S", 0 0, L_0x2a36a90; 1 drivers
+v0x2751640_0 .net "in0", 0 0, L_0x2a36b30; 1 drivers
+v0x2752c30_0 .net "in1", 0 0, L_0x2a36c20; 1 drivers
+v0x2765b80_0 .net "nS", 0 0, L_0x29e91c0; 1 drivers
+v0x2765c00_0 .net "out0", 0 0, L_0x29e92b0; 1 drivers
+v0x2765ca0_0 .net "out1", 0 0, L_0x2a367c0; 1 drivers
+v0x27b11f0_0 .net "outfinal", 0 0, L_0x2a368b0; 1 drivers
+S_0x26bb0a0 .scope generate, "muxbits[16]" "muxbits[16]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x23ae358 .param/l "i" 3 397, +C4<010000>;
+L_0x2a39d70/d .functor OR 1, L_0x2a3ad30, L_0x2a26360, C4<0>, C4<0>;
+L_0x2a39d70 .delay (20000,20000,20000) L_0x2a39d70/d;
+v0x2751500_0 .net *"_s15", 0 0, L_0x2a3ad30; 1 drivers
+v0x27515a0_0 .net *"_s16", 0 0, L_0x2a26360; 1 drivers
+S_0x274a880 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x26bb0a0;
+ .timescale -9 -12;
+L_0x2a378a0/d .functor NOT 1, L_0x2a38770, C4<0>, C4<0>, C4<0>;
+L_0x2a378a0 .delay (10000,10000,10000) L_0x2a378a0/d;
+L_0x2a37990/d .functor NOT 1, L_0x2a388a0, C4<0>, C4<0>, C4<0>;
+L_0x2a37990 .delay (10000,10000,10000) L_0x2a37990/d;
+L_0x2a37a30/d .functor NAND 1, L_0x2a378a0, L_0x2a37990, L_0x2a389d0, C4<1>;
+L_0x2a37a30 .delay (10000,10000,10000) L_0x2a37a30/d;
+L_0x2a37b70/d .functor NAND 1, L_0x2a38770, L_0x2a37990, L_0x2a38a70, C4<1>;
+L_0x2a37b70 .delay (10000,10000,10000) L_0x2a37b70/d;
+L_0x2a37c60/d .functor NAND 1, L_0x2a378a0, L_0x2a388a0, L_0x2a38b10, C4<1>;
+L_0x2a37c60 .delay (10000,10000,10000) L_0x2a37c60/d;
+L_0x2a37db0/d .functor NAND 1, L_0x2a38770, L_0x2a388a0, L_0x2a38c00, C4<1>;
+L_0x2a37db0 .delay (10000,10000,10000) L_0x2a37db0/d;
+L_0x2a39150/d .functor NAND 1, L_0x2a37a30, L_0x2a37b70, L_0x2a37c60, L_0x2a37db0;
+L_0x2a39150 .delay (10000,10000,10000) L_0x2a39150/d;
+v0x274a970_0 .net "S0", 0 0, L_0x2a38770; 1 drivers
+v0x274be00_0 .net "S1", 0 0, L_0x2a388a0; 1 drivers
+v0x274bea0_0 .net "in0", 0 0, L_0x2a389d0; 1 drivers
+v0x274bf40_0 .net "in1", 0 0, L_0x2a38a70; 1 drivers
+v0x274d400_0 .net "in2", 0 0, L_0x2a38b10; 1 drivers
+v0x274d4a0_0 .net "in3", 0 0, L_0x2a38c00; 1 drivers
+v0x274d540_0 .net "nS0", 0 0, L_0x2a378a0; 1 drivers
+v0x274e980_0 .net "nS1", 0 0, L_0x2a37990; 1 drivers
+v0x274ea00_0 .net "out", 0 0, L_0x2a39150; 1 drivers
+v0x274eaa0_0 .net "out0", 0 0, L_0x2a37a30; 1 drivers
+v0x274ff80_0 .net "out1", 0 0, L_0x2a37b70; 1 drivers
+v0x2750020_0 .net "out2", 0 0, L_0x2a37c60; 1 drivers
+v0x27500c0_0 .net "out3", 0 0, L_0x2a37db0; 1 drivers
+S_0x267cfb0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x26bb0a0;
+ .timescale -9 -12;
+L_0x2a38cf0/d .functor NOT 1, L_0x2a3a260, C4<0>, C4<0>, C4<0>;
+L_0x2a38cf0 .delay (10000,10000,10000) L_0x2a38cf0/d;
+L_0x2a38da0/d .functor NOT 1, L_0x2a393d0, C4<0>, C4<0>, C4<0>;
+L_0x2a38da0 .delay (10000,10000,10000) L_0x2a38da0/d;
+L_0x2a38e00/d .functor NAND 1, L_0x2a38cf0, L_0x2a38da0, L_0x2a39500, C4<1>;
+L_0x2a38e00 .delay (10000,10000,10000) L_0x2a38e00/d;
+L_0x2a38f40/d .functor NAND 1, L_0x2a3a260, L_0x2a38da0, L_0x2a395a0, C4<1>;
+L_0x2a38f40 .delay (10000,10000,10000) L_0x2a38f40/d;
+L_0x2a39030/d .functor NAND 1, L_0x2a38cf0, L_0x2a393d0, L_0x2a39640, C4<1>;
+L_0x2a39030 .delay (10000,10000,10000) L_0x2a39030/d;
+L_0x2a39e40/d .functor NAND 1, L_0x2a3a260, L_0x2a393d0, L_0x2a39730, C4<1>;
+L_0x2a39e40 .delay (10000,10000,10000) L_0x2a39e40/d;
+L_0x2a39fb0/d .functor NAND 1, L_0x2a38e00, L_0x2a38f40, L_0x2a39030, L_0x2a39e40;
+L_0x2a39fb0 .delay (10000,10000,10000) L_0x2a39fb0/d;
+v0x267d0a0_0 .net "S0", 0 0, L_0x2a3a260; 1 drivers
+v0x2678300_0 .net "S1", 0 0, L_0x2a393d0; 1 drivers
+v0x26783a0_0 .net "in0", 0 0, L_0x2a39500; 1 drivers
+v0x2673650_0 .net "in1", 0 0, L_0x2a395a0; 1 drivers
+v0x2745200_0 .net "in2", 0 0, L_0x2a39640; 1 drivers
+v0x27452a0_0 .net "in3", 0 0, L_0x2a39730; 1 drivers
+v0x2746700_0 .net "nS0", 0 0, L_0x2a38cf0; 1 drivers
+v0x27467a0_0 .net "nS1", 0 0, L_0x2a38da0; 1 drivers
+v0x2747d00_0 .net "out", 0 0, L_0x2a39fb0; 1 drivers
+v0x2747da0_0 .net "out0", 0 0, L_0x2a38e00; 1 drivers
+v0x2749280_0 .net "out1", 0 0, L_0x2a38f40; 1 drivers
+v0x2749320_0 .net "out2", 0 0, L_0x2a39030; 1 drivers
+v0x27493c0_0 .net "out3", 0 0, L_0x2a39e40; 1 drivers
+S_0x26b63f0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x26bb0a0;
+ .timescale -9 -12;
+L_0x2a39820/d .functor NOT 1, L_0x2a39cd0, C4<0>, C4<0>, C4<0>;
+L_0x2a39820 .delay (10000,10000,10000) L_0x2a39820/d;
+L_0x2a39910/d .functor AND 1, L_0x2a25c20, L_0x2a39820, C4<1>, C4<1>;
+L_0x2a39910 .delay (20000,20000,20000) L_0x2a39910/d;
+L_0x2a39a00/d .functor AND 1, L_0x2a25d10, L_0x2a39cd0, C4<1>, C4<1>;
+L_0x2a39a00 .delay (20000,20000,20000) L_0x2a39a00/d;
+L_0x2a39af0/d .functor OR 1, L_0x2a39910, L_0x2a39a00, C4<0>, C4<0>;
+L_0x2a39af0 .delay (20000,20000,20000) L_0x2a39af0/d;
+v0x26b64e0_0 .net "S", 0 0, L_0x2a39cd0; 1 drivers
+v0x269e650_0 .net "in0", 0 0, L_0x2a25c20; 1 drivers
+v0x269e6d0_0 .net "in1", 0 0, L_0x2a25d10; 1 drivers
+v0x26999a0_0 .net "nS", 0 0, L_0x2a39820; 1 drivers
+v0x2699a20_0 .net "out0", 0 0, L_0x2a39910; 1 drivers
+v0x2694cf0_0 .net "out1", 0 0, L_0x2a39a00; 1 drivers
+v0x2694d90_0 .net "outfinal", 0 0, L_0x2a39af0; 1 drivers
+S_0x25f26c0 .scope generate, "muxbits[17]" "muxbits[17]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x23d0a18 .param/l "i" 3 397, +C4<010001>;
+L_0x2a3d590/d .functor OR 1, L_0x2a3d6d0, L_0x2a3d770, C4<0>, C4<0>;
+L_0x2a3d590 .delay (20000,20000,20000) L_0x2a3d590/d;
+v0x26bfd50_0 .net *"_s15", 0 0, L_0x2a3d6d0; 1 drivers
+v0x26bfe10_0 .net *"_s16", 0 0, L_0x2a3d770; 1 drivers
+S_0x25b3ad0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25f26c0;
+ .timescale -9 -12;
+L_0x2a26450/d .functor NOT 1, L_0x2a3c460, C4<0>, C4<0>, C4<0>;
+L_0x2a26450 .delay (10000,10000,10000) L_0x2a26450/d;
+L_0x2a3bc80/d .functor NOT 1, L_0x2a3b1f0, C4<0>, C4<0>, C4<0>;
+L_0x2a3bc80 .delay (10000,10000,10000) L_0x2a3bc80/d;
+L_0x2a3bd20/d .functor NAND 1, L_0x2a26450, L_0x2a3bc80, L_0x2a3b320, C4<1>;
+L_0x2a3bd20 .delay (10000,10000,10000) L_0x2a3bd20/d;
+L_0x2a3be60/d .functor NAND 1, L_0x2a3c460, L_0x2a3bc80, L_0x2a3b3c0, C4<1>;
+L_0x2a3be60 .delay (10000,10000,10000) L_0x2a3be60/d;
+L_0x2a3bf50/d .functor NAND 1, L_0x2a26450, L_0x2a3b1f0, L_0x2a3b460, C4<1>;
+L_0x2a3bf50 .delay (10000,10000,10000) L_0x2a3bf50/d;
+L_0x2a3c040/d .functor NAND 1, L_0x2a3c460, L_0x2a3b1f0, L_0x2a3b550, C4<1>;
+L_0x2a3c040 .delay (10000,10000,10000) L_0x2a3c040/d;
+L_0x2a3c1b0/d .functor NAND 1, L_0x2a3bd20, L_0x2a3be60, L_0x2a3bf50, L_0x2a3c040;
+L_0x2a3c1b0 .delay (10000,10000,10000) L_0x2a3c1b0/d;
+v0x25b3bc0_0 .net "S0", 0 0, L_0x2a3c460; 1 drivers
+v0x2660560_0 .net "S1", 0 0, L_0x2a3b1f0; 1 drivers
+v0x2660600_0 .net "in0", 0 0, L_0x2a3b320; 1 drivers
+v0x265b8b0_0 .net "in1", 0 0, L_0x2a3b3c0; 1 drivers
+v0x265b930_0 .net "in2", 0 0, L_0x2a3b460; 1 drivers
+v0x2656c00_0 .net "in3", 0 0, L_0x2a3b550; 1 drivers
+v0x2656ca0_0 .net "nS0", 0 0, L_0x2a26450; 1 drivers
+v0x26d7ae0_0 .net "nS1", 0 0, L_0x2a3bc80; 1 drivers
+v0x26d7b80_0 .net "out", 0 0, L_0x2a3c1b0; 1 drivers
+v0x26d2e70_0 .net "out0", 0 0, L_0x2a3bd20; 1 drivers
+v0x26d2f10_0 .net "out1", 0 0, L_0x2a3be60; 1 drivers
+v0x2651f90_0 .net "out2", 0 0, L_0x2a3bf50; 1 drivers
+v0x2652030_0 .net "out3", 0 0, L_0x2a3c040; 1 drivers
+S_0x25d7030 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25f26c0;
+ .timescale -9 -12;
+L_0x2a3b640/d .functor NOT 1, L_0x2a3c590, C4<0>, C4<0>, C4<0>;
+L_0x2a3b640 .delay (10000,10000,10000) L_0x2a3b640/d;
+L_0x2a3b730/d .functor NOT 1, L_0x2a3c6c0, C4<0>, C4<0>, C4<0>;
+L_0x2a3b730 .delay (10000,10000,10000) L_0x2a3b730/d;
+L_0x2a3b7d0/d .functor NAND 1, L_0x2a3b640, L_0x2a3b730, L_0x2a3c7f0, C4<1>;
+L_0x2a3b7d0 .delay (10000,10000,10000) L_0x2a3b7d0/d;
+L_0x2a3b910/d .functor NAND 1, L_0x2a3c590, L_0x2a3b730, L_0x2a3c890, C4<1>;
+L_0x2a3b910 .delay (10000,10000,10000) L_0x2a3b910/d;
+L_0x2a3ba00/d .functor NAND 1, L_0x2a3b640, L_0x2a3c6c0, L_0x2a3c930, C4<1>;
+L_0x2a3ba00 .delay (10000,10000,10000) L_0x2a3ba00/d;
+L_0x2a3bb20/d .functor NAND 1, L_0x2a3c590, L_0x2a3c6c0, L_0x2a3ca20, C4<1>;
+L_0x2a3bb20 .delay (10000,10000,10000) L_0x2a3bb20/d;
+L_0x2a3d090/d .functor NAND 1, L_0x2a3b7d0, L_0x2a3b910, L_0x2a3ba00, L_0x2a3bb20;
+L_0x2a3d090 .delay (10000,10000,10000) L_0x2a3d090/d;
+v0x25d7120_0 .net "S0", 0 0, L_0x2a3c590; 1 drivers
+v0x25d4f80_0 .net "S1", 0 0, L_0x2a3c6c0; 1 drivers
+v0x25d5020_0 .net "in0", 0 0, L_0x2a3c7f0; 1 drivers
+v0x25942c0_0 .net "in1", 0 0, L_0x2a3c890; 1 drivers
+v0x2594340_0 .net "in2", 0 0, L_0x2a3c930; 1 drivers
+v0x25bf710_0 .net "in3", 0 0, L_0x2a3ca20; 1 drivers
+v0x25bf7b0_0 .net "nS0", 0 0, L_0x2a3b640; 1 drivers
+v0x25bd660_0 .net "nS1", 0 0, L_0x2a3b730; 1 drivers
+v0x25bd700_0 .net "out", 0 0, L_0x2a3d090; 1 drivers
+v0x25b98f0_0 .net "out0", 0 0, L_0x2a3b7d0; 1 drivers
+v0x25b9990_0 .net "out1", 0 0, L_0x2a3b910; 1 drivers
+v0x25b7840_0 .net "out2", 0 0, L_0x2a3ba00; 1 drivers
+v0x25b78e0_0 .net "out3", 0 0, L_0x2a3bb20; 1 drivers
+S_0x25e0bc0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25f26c0;
+ .timescale -9 -12;
+L_0x2a3cb10/d .functor NOT 1, L_0x2a3de10, C4<0>, C4<0>, C4<0>;
+L_0x2a3cb10 .delay (10000,10000,10000) L_0x2a3cb10/d;
+L_0x2a3cc00/d .functor AND 1, L_0x2a3d310, L_0x2a3cb10, C4<1>, C4<1>;
+L_0x2a3cc00 .delay (20000,20000,20000) L_0x2a3cc00/d;
+L_0x2a3ccf0/d .functor AND 1, L_0x2a3d400, L_0x2a3de10, C4<1>, C4<1>;
+L_0x2a3ccf0 .delay (20000,20000,20000) L_0x2a3ccf0/d;
+L_0x2a3cde0/d .functor OR 1, L_0x2a3cc00, L_0x2a3ccf0, C4<0>, C4<0>;
+L_0x2a3cde0 .delay (20000,20000,20000) L_0x2a3cde0/d;
+v0x25e0cb0_0 .net "S", 0 0, L_0x2a3de10; 1 drivers
+v0x25dce50_0 .net "in0", 0 0, L_0x2a3d310; 1 drivers
+v0x25dced0_0 .net "in1", 0 0, L_0x2a3d400; 1 drivers
+v0x2596370_0 .net "nS", 0 0, L_0x2a3cb10; 1 drivers
+v0x25963f0_0 .net "out0", 0 0, L_0x2a3cc00; 1 drivers
+v0x25dada0_0 .net "out1", 0 0, L_0x2a3ccf0; 1 drivers
+v0x25dae40_0 .net "outfinal", 0 0, L_0x2a3cde0; 1 drivers
+S_0x2641070 .scope generate, "muxbits[18]" "muxbits[18]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x23f9588 .param/l "i" 3 397, +C4<010010>;
+L_0x2a3fcc0/d .functor OR 1, L_0x2a3fe00, L_0x2a3fea0, C4<0>, C4<0>;
+L_0x2a3fcc0 .delay (20000,20000,20000) L_0x2a3fcc0/d;
+v0x25f4790_0 .net *"_s15", 0 0, L_0x2a3fe00; 1 drivers
+v0x25f4850_0 .net *"_s16", 0 0, L_0x2a3fea0; 1 drivers
+S_0x2615c40 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2641070;
+ .timescale -9 -12;
+L_0x2a3d860/d .functor NOT 1, L_0x2a3deb0, C4<0>, C4<0>, C4<0>;
+L_0x2a3d860 .delay (10000,10000,10000) L_0x2a3d860/d;
+L_0x2a3d950/d .functor NOT 1, L_0x2a3dfe0, C4<0>, C4<0>, C4<0>;
+L_0x2a3d950 .delay (10000,10000,10000) L_0x2a3d950/d;
+L_0x2a3d9f0/d .functor NAND 1, L_0x2a3d860, L_0x2a3d950, L_0x2a3e110, C4<1>;
+L_0x2a3d9f0 .delay (10000,10000,10000) L_0x2a3d9f0/d;
+L_0x2a3db30/d .functor NAND 1, L_0x2a3deb0, L_0x2a3d950, L_0x2a3e1b0, C4<1>;
+L_0x2a3db30 .delay (10000,10000,10000) L_0x2a3db30/d;
+L_0x2a3dc20/d .functor NAND 1, L_0x2a3d860, L_0x2a3dfe0, L_0x2a3e250, C4<1>;
+L_0x2a3dc20 .delay (10000,10000,10000) L_0x2a3dc20/d;
+L_0x2a3dd40/d .functor NAND 1, L_0x2a3deb0, L_0x2a3dfe0, L_0x2a3e340, C4<1>;
+L_0x2a3dd40 .delay (10000,10000,10000) L_0x2a3dd40/d;
+L_0x2a3ea20/d .functor NAND 1, L_0x2a3d9f0, L_0x2a3db30, L_0x2a3dc20, L_0x2a3dd40;
+L_0x2a3ea20 .delay (10000,10000,10000) L_0x2a3ea20/d;
+v0x2615d30_0 .net "S0", 0 0, L_0x2a3deb0; 1 drivers
+v0x2611f10_0 .net "S1", 0 0, L_0x2a3dfe0; 1 drivers
+v0x2611fb0_0 .net "in0", 0 0, L_0x2a3e110; 1 drivers
+v0x259a0e0_0 .net "in1", 0 0, L_0x2a3e1b0; 1 drivers
+v0x259a160_0 .net "in2", 0 0, L_0x2a3e250; 1 drivers
+v0x26003d0_0 .net "in3", 0 0, L_0x2a3e340; 1 drivers
+v0x2600470_0 .net "nS0", 0 0, L_0x2a3d860; 1 drivers
+v0x25fe320_0 .net "nS1", 0 0, L_0x2a3d950; 1 drivers
+v0x25fe3c0_0 .net "out", 0 0, L_0x2a3ea20; 1 drivers
+v0x25fa5b0_0 .net "out0", 0 0, L_0x2a3d9f0; 1 drivers
+v0x25fa650_0 .net "out1", 0 0, L_0x2a3db30; 1 drivers
+v0x25f8500_0 .net "out2", 0 0, L_0x2a3dc20; 1 drivers
+v0x25f85a0_0 .net "out3", 0 0, L_0x2a3dd40; 1 drivers
+S_0x2635430 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2641070;
+ .timescale -9 -12;
+L_0x2a3e430/d .functor NOT 1, L_0x2a3fb90, C4<0>, C4<0>, C4<0>;
+L_0x2a3e430 .delay (10000,10000,10000) L_0x2a3e430/d;
+L_0x2a3e520/d .functor NOT 1, L_0x2a3ec90, C4<0>, C4<0>, C4<0>;
+L_0x2a3e520 .delay (10000,10000,10000) L_0x2a3e520/d;
+L_0x2a3e5c0/d .functor NAND 1, L_0x2a3e430, L_0x2a3e520, L_0x2a3edc0, C4<1>;
+L_0x2a3e5c0 .delay (10000,10000,10000) L_0x2a3e5c0/d;
+L_0x2a3e700/d .functor NAND 1, L_0x2a3fb90, L_0x2a3e520, L_0x2a3ee60, C4<1>;
+L_0x2a3e700 .delay (10000,10000,10000) L_0x2a3e700/d;
+L_0x2a3e7f0/d .functor NAND 1, L_0x2a3e430, L_0x2a3ec90, L_0x2a3ef00, C4<1>;
+L_0x2a3e7f0 .delay (10000,10000,10000) L_0x2a3e7f0/d;
+L_0x2a3e940/d .functor NAND 1, L_0x2a3fb90, L_0x2a3ec90, L_0x2a3eff0, C4<1>;
+L_0x2a3e940 .delay (10000,10000,10000) L_0x2a3e940/d;
+L_0x2a3f8e0/d .functor NAND 1, L_0x2a3e5c0, L_0x2a3e700, L_0x2a3e7f0, L_0x2a3e940;
+L_0x2a3f8e0 .delay (10000,10000,10000) L_0x2a3f8e0/d;
+v0x2635520_0 .net "S0", 0 0, L_0x2a3fb90; 1 drivers
+v0x26333a0_0 .net "S1", 0 0, L_0x2a3ec90; 1 drivers
+v0x2633440_0 .net "in0", 0 0, L_0x2a3edc0; 1 drivers
+v0x2621880_0 .net "in1", 0 0, L_0x2a3ee60; 1 drivers
+v0x2621900_0 .net "in2", 0 0, L_0x2a3ef00; 1 drivers
+v0x261db10_0 .net "in3", 0 0, L_0x2a3eff0; 1 drivers
+v0x261dbb0_0 .net "nS0", 0 0, L_0x2a3e430; 1 drivers
+v0x261ba60_0 .net "nS1", 0 0, L_0x2a3e520; 1 drivers
+v0x261bb00_0 .net "out", 0 0, L_0x2a3f8e0; 1 drivers
+v0x2617cf0_0 .net "out0", 0 0, L_0x2a3e5c0; 1 drivers
+v0x2617d90_0 .net "out1", 0 0, L_0x2a3e700; 1 drivers
+v0x259c190_0 .net "out2", 0 0, L_0x2a3e7f0; 1 drivers
+v0x259c230_0 .net "out3", 0 0, L_0x2a3e940; 1 drivers
+S_0x263efc0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2641070;
+ .timescale -9 -12;
+L_0x2a3f0e0/d .functor NOT 1, L_0x2a3f590, C4<0>, C4<0>, C4<0>;
+L_0x2a3f0e0 .delay (10000,10000,10000) L_0x2a3f0e0/d;
+L_0x2a3f1d0/d .functor AND 1, L_0x2a3f630, L_0x2a3f0e0, C4<1>, C4<1>;
+L_0x2a3f1d0 .delay (20000,20000,20000) L_0x2a3f1d0/d;
+L_0x2a3f2c0/d .functor AND 1, L_0x2a3f720, L_0x2a3f590, C4<1>, C4<1>;
+L_0x2a3f2c0 .delay (20000,20000,20000) L_0x2a3f2c0/d;
+L_0x2a3f3b0/d .functor OR 1, L_0x2a3f1d0, L_0x2a3f2c0, C4<0>, C4<0>;
+L_0x2a3f3b0 .delay (20000,20000,20000) L_0x2a3f3b0/d;
+v0x263f0b0_0 .net "S", 0 0, L_0x2a3f590; 1 drivers
+v0x259ff00_0 .net "in0", 0 0, L_0x2a3f630; 1 drivers
+v0x259ff80_0 .net "in1", 0 0, L_0x2a3f720; 1 drivers
+v0x263b250_0 .net "nS", 0 0, L_0x2a3f0e0; 1 drivers
+v0x263b2d0_0 .net "out0", 0 0, L_0x2a3f1d0; 1 drivers
+v0x26391a0_0 .net "out1", 0 0, L_0x2a3f2c0; 1 drivers
+v0x2639240_0 .net "outfinal", 0 0, L_0x2a3f3b0; 1 drivers
+S_0x23971f0 .scope generate, "muxbits[19]" "muxbits[19]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2410ec8 .param/l "i" 3 397, +C4<010011>;
+L_0x2a42470/d .functor OR 1, L_0x2a425b0, L_0x2a42650, C4<0>, C4<0>;
+L_0x2a42470 .delay (20000,20000,20000) L_0x2a42470/d;
+v0x27b4c20_0 .net *"_s15", 0 0, L_0x2a425b0; 1 drivers
+v0x27b4ce0_0 .net *"_s16", 0 0, L_0x2a42650; 1 drivers
+S_0x246f440 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x23971f0;
+ .timescale -9 -12;
+L_0x2a3ff90/d .functor NOT 1, L_0x2a415a0, C4<0>, C4<0>, C4<0>;
+L_0x2a3ff90 .delay (10000,10000,10000) L_0x2a3ff90/d;
+L_0x2a40080/d .functor NOT 1, L_0x2a40920, C4<0>, C4<0>, C4<0>;
+L_0x2a40080 .delay (10000,10000,10000) L_0x2a40080/d;
+L_0x2a40120/d .functor NAND 1, L_0x2a3ff90, L_0x2a40080, L_0x2a40a50, C4<1>;
+L_0x2a40120 .delay (10000,10000,10000) L_0x2a40120/d;
+L_0x2a40260/d .functor NAND 1, L_0x2a415a0, L_0x2a40080, L_0x2a40af0, C4<1>;
+L_0x2a40260 .delay (10000,10000,10000) L_0x2a40260/d;
+L_0x2a40350/d .functor NAND 1, L_0x2a3ff90, L_0x2a40920, L_0x2a40b90, C4<1>;
+L_0x2a40350 .delay (10000,10000,10000) L_0x2a40350/d;
+L_0x2a404a0/d .functor NAND 1, L_0x2a415a0, L_0x2a40920, L_0x2a40c80, C4<1>;
+L_0x2a404a0 .delay (10000,10000,10000) L_0x2a404a0/d;
+L_0x2a40610/d .functor NAND 1, L_0x2a40120, L_0x2a40260, L_0x2a40350, L_0x2a404a0;
+L_0x2a40610 .delay (10000,10000,10000) L_0x2a40610/d;
+v0x246f530_0 .net "S0", 0 0, L_0x2a415a0; 1 drivers
+v0x245c340_0 .net "S1", 0 0, L_0x2a40920; 1 drivers
+v0x245c3e0_0 .net "in0", 0 0, L_0x2a40a50; 1 drivers
+v0x2457690_0 .net "in1", 0 0, L_0x2a40af0; 1 drivers
+v0x2457730_0 .net "in2", 0 0, L_0x2a40b90; 1 drivers
+v0x24529e0_0 .net "in3", 0 0, L_0x2a40c80; 1 drivers
+v0x2452a80_0 .net "nS0", 0 0, L_0x2a3ff90; 1 drivers
+v0x244dd70_0 .net "nS1", 0 0, L_0x2a40080; 1 drivers
+v0x244de10_0 .net "out", 0 0, L_0x2a40610; 1 drivers
+v0x243ac80_0 .net "out0", 0 0, L_0x2a40120; 1 drivers
+v0x243ad20_0 .net "out1", 0 0, L_0x2a40260; 1 drivers
+v0x23edda0_0 .net "out2", 0 0, L_0x2a40350; 1 drivers
+v0x23ede40_0 .net "out3", 0 0, L_0x2a404a0; 1 drivers
+S_0x2431320 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x23971f0;
+ .timescale -9 -12;
+L_0x2a40820/d .functor NOT 1, L_0x2a416d0, C4<0>, C4<0>, C4<0>;
+L_0x2a40820 .delay (10000,10000,10000) L_0x2a40820/d;
+L_0x2a40e00/d .functor NOT 1, L_0x2a41800, C4<0>, C4<0>, C4<0>;
+L_0x2a40e00 .delay (10000,10000,10000) L_0x2a40e00/d;
+L_0x2a40ea0/d .functor NAND 1, L_0x2a40820, L_0x2a40e00, L_0x2a41930, C4<1>;
+L_0x2a40ea0 .delay (10000,10000,10000) L_0x2a40ea0/d;
+L_0x2a40fe0/d .functor NAND 1, L_0x2a416d0, L_0x2a40e00, L_0x2a419d0, C4<1>;
+L_0x2a40fe0 .delay (10000,10000,10000) L_0x2a40fe0/d;
+L_0x2a410d0/d .functor NAND 1, L_0x2a40820, L_0x2a41800, L_0x2a41a70, C4<1>;
+L_0x2a410d0 .delay (10000,10000,10000) L_0x2a410d0/d;
+L_0x2a411c0/d .functor NAND 1, L_0x2a416d0, L_0x2a41800, L_0x2a41b60, C4<1>;
+L_0x2a411c0 .delay (10000,10000,10000) L_0x2a411c0/d;
+L_0x2a41330/d .functor NAND 1, L_0x2a40ea0, L_0x2a40fe0, L_0x2a410d0, L_0x2a411c0;
+L_0x2a41330 .delay (10000,10000,10000) L_0x2a41330/d;
+v0x2431410_0 .net "S0", 0 0, L_0x2a416d0; 1 drivers
+v0x249a490_0 .net "S1", 0 0, L_0x2a41800; 1 drivers
+v0x249a530_0 .net "in0", 0 0, L_0x2a41930; 1 drivers
+v0x24957e0_0 .net "in1", 0 0, L_0x2a419d0; 1 drivers
+v0x2495880_0 .net "in2", 0 0, L_0x2a41a70; 1 drivers
+v0x2490b30_0 .net "in3", 0 0, L_0x2a41b60; 1 drivers
+v0x2490bd0_0 .net "nS0", 0 0, L_0x2a40820; 1 drivers
+v0x247da50_0 .net "nS1", 0 0, L_0x2a40e00; 1 drivers
+v0x247daf0_0 .net "out", 0 0, L_0x2a41330; 1 drivers
+v0x2478da0_0 .net "out0", 0 0, L_0x2a40ea0; 1 drivers
+v0x2478e40_0 .net "out1", 0 0, L_0x2a40fe0; 1 drivers
+v0x24740f0_0 .net "out2", 0 0, L_0x2a410d0; 1 drivers
+v0x2474190_0 .net "out3", 0 0, L_0x2a411c0; 1 drivers
+S_0x2395200 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x23971f0;
+ .timescale -9 -12;
+L_0x2a41c50/d .functor NOT 1, L_0x2a42100, C4<0>, C4<0>, C4<0>;
+L_0x2a41c50 .delay (10000,10000,10000) L_0x2a41c50/d;
+L_0x2a41d40/d .functor AND 1, L_0x2a421a0, L_0x2a41c50, C4<1>, C4<1>;
+L_0x2a41d40 .delay (20000,20000,20000) L_0x2a41d40/d;
+L_0x2a41e30/d .functor AND 1, L_0x2a43030, L_0x2a42100, C4<1>, C4<1>;
+L_0x2a41e30 .delay (20000,20000,20000) L_0x2a41e30/d;
+L_0x2a41f20/d .functor OR 1, L_0x2a41d40, L_0x2a41e30, C4<0>, C4<0>;
+L_0x2a41f20 .delay (20000,20000,20000) L_0x2a41f20/d;
+v0x23952f0_0 .net "S", 0 0, L_0x2a42100; 1 drivers
+v0x2391690_0 .net "in0", 0 0, L_0x2a421a0; 1 drivers
+v0x2391730_0 .net "in1", 0 0, L_0x2a43030; 1 drivers
+v0x238f6a0_0 .net "nS", 0 0, L_0x2a41c50; 1 drivers
+v0x238f720_0 .net "out0", 0 0, L_0x2a41d40; 1 drivers
+v0x2435fd0_0 .net "out1", 0 0, L_0x2a41e30; 1 drivers
+v0x2436070_0 .net "outfinal", 0 0, L_0x2a41f20; 1 drivers
+S_0x23f3620 .scope generate, "muxbits[20]" "muxbits[20]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x263fb58 .param/l "i" 3 397, +C4<010100>;
+L_0x2a44be0/d .functor OR 1, L_0x2a45ad0, L_0x2a45b70, C4<0>, C4<0>;
+L_0x2a44be0 .delay (20000,20000,20000) L_0x2a44be0/d;
+v0x239ad60_0 .net *"_s15", 0 0, L_0x2a45ad0; 1 drivers
+v0x239ae20_0 .net *"_s16", 0 0, L_0x2a45b70; 1 drivers
+S_0x23b78e0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x23f3620;
+ .timescale -9 -12;
+L_0x2a42740/d .functor NOT 1, L_0x2a43d60, C4<0>, C4<0>, C4<0>;
+L_0x2a42740 .delay (10000,10000,10000) L_0x2a42740/d;
+L_0x2a42830/d .functor NOT 1, L_0x2a43e90, C4<0>, C4<0>, C4<0>;
+L_0x2a42830 .delay (10000,10000,10000) L_0x2a42830/d;
+L_0x2a428d0/d .functor NAND 1, L_0x2a42740, L_0x2a42830, L_0x2a430d0, C4<1>;
+L_0x2a428d0 .delay (10000,10000,10000) L_0x2a428d0/d;
+L_0x2a42a10/d .functor NAND 1, L_0x2a43d60, L_0x2a42830, L_0x2a43170, C4<1>;
+L_0x2a42a10 .delay (10000,10000,10000) L_0x2a42a10/d;
+L_0x2a42b00/d .functor NAND 1, L_0x2a42740, L_0x2a43e90, L_0x2a43210, C4<1>;
+L_0x2a42b00 .delay (10000,10000,10000) L_0x2a42b00/d;
+L_0x2a42bf0/d .functor NAND 1, L_0x2a43d60, L_0x2a43e90, L_0x2a43300, C4<1>;
+L_0x2a42bf0 .delay (10000,10000,10000) L_0x2a42bf0/d;
+L_0x2a42d60/d .functor NAND 1, L_0x2a428d0, L_0x2a42a10, L_0x2a42b00, L_0x2a42bf0;
+L_0x2a42d60 .delay (10000,10000,10000) L_0x2a42d60/d;
+v0x23b79d0_0 .net "S0", 0 0, L_0x2a43d60; 1 drivers
+v0x23b3d70_0 .net "S1", 0 0, L_0x2a43e90; 1 drivers
+v0x23b3e10_0 .net "in0", 0 0, L_0x2a430d0; 1 drivers
+v0x236ef70_0 .net "in1", 0 0, L_0x2a43170; 1 drivers
+v0x236f010_0 .net "in2", 0 0, L_0x2a43210; 1 drivers
+v0x23b1d80_0 .net "in3", 0 0, L_0x2a43300; 1 drivers
+v0x23b1e20_0 .net "nS0", 0 0, L_0x2a42740; 1 drivers
+v0x23ae210_0 .net "nS1", 0 0, L_0x2a42830; 1 drivers
+v0x23ae2b0_0 .net "out", 0 0, L_0x2a42d60; 1 drivers
+v0x236cf80_0 .net "out0", 0 0, L_0x2a428d0; 1 drivers
+v0x236d020_0 .net "out1", 0 0, L_0x2a42a10; 1 drivers
+v0x239cd50_0 .net "out2", 0 0, L_0x2a42b00; 1 drivers
+v0x239cdf0_0 .net "out3", 0 0, L_0x2a42bf0; 1 drivers
+S_0x2372ae0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x23f3620;
+ .timescale -9 -12;
+L_0x2a433f0/d .functor NOT 1, L_0x2a43cc0, C4<0>, C4<0>, C4<0>;
+L_0x2a433f0 .delay (10000,10000,10000) L_0x2a433f0/d;
+L_0x2a434e0/d .functor NOT 1, L_0x2a43fc0, C4<0>, C4<0>, C4<0>;
+L_0x2a434e0 .delay (10000,10000,10000) L_0x2a434e0/d;
+L_0x2a43580/d .functor NAND 1, L_0x2a433f0, L_0x2a434e0, L_0x2a440f0, C4<1>;
+L_0x2a43580 .delay (10000,10000,10000) L_0x2a43580/d;
+L_0x2a436c0/d .functor NAND 1, L_0x2a43cc0, L_0x2a434e0, L_0x2a44190, C4<1>;
+L_0x2a436c0 .delay (10000,10000,10000) L_0x2a436c0/d;
+L_0x2a437b0/d .functor NAND 1, L_0x2a433f0, L_0x2a43fc0, L_0x2a44230, C4<1>;
+L_0x2a437b0 .delay (10000,10000,10000) L_0x2a437b0/d;
+L_0x2a438a0/d .functor NAND 1, L_0x2a43cc0, L_0x2a43fc0, L_0x2a44320, C4<1>;
+L_0x2a438a0 .delay (10000,10000,10000) L_0x2a438a0/d;
+L_0x2a43a10/d .functor NAND 1, L_0x2a43580, L_0x2a436c0, L_0x2a437b0, L_0x2a438a0;
+L_0x2a43a10 .delay (10000,10000,10000) L_0x2a43a10/d;
+v0x2372bd0_0 .net "S0", 0 0, L_0x2a43cc0; 1 drivers
+v0x23d6430_0 .net "S1", 0 0, L_0x2a43fc0; 1 drivers
+v0x23d64d0_0 .net "in0", 0 0, L_0x2a440f0; 1 drivers
+v0x23d4440_0 .net "in1", 0 0, L_0x2a44190; 1 drivers
+v0x23d44e0_0 .net "in2", 0 0, L_0x2a44230; 1 drivers
+v0x23d08d0_0 .net "in3", 0 0, L_0x2a44320; 1 drivers
+v0x23d0970_0 .net "nS0", 0 0, L_0x2a433f0; 1 drivers
+v0x23ce8e0_0 .net "nS1", 0 0, L_0x2a434e0; 1 drivers
+v0x23ce980_0 .net "out", 0 0, L_0x2a43a10; 1 drivers
+v0x23bd440_0 .net "out0", 0 0, L_0x2a43580; 1 drivers
+v0x23bd4e0_0 .net "out1", 0 0, L_0x2a436c0; 1 drivers
+v0x23b98d0_0 .net "out2", 0 0, L_0x2a437b0; 1 drivers
+v0x23b9970_0 .net "out3", 0 0, L_0x2a438a0; 1 drivers
+S_0x23f1570 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x23f3620;
+ .timescale -9 -12;
+L_0x2a44410/d .functor NOT 1, L_0x2a448c0, C4<0>, C4<0>, C4<0>;
+L_0x2a44410 .delay (10000,10000,10000) L_0x2a44410/d;
+L_0x2a44500/d .functor AND 1, L_0x2a44960, L_0x2a44410, C4<1>, C4<1>;
+L_0x2a44500 .delay (20000,20000,20000) L_0x2a44500/d;
+L_0x2a445f0/d .functor AND 1, L_0x2a44a50, L_0x2a448c0, C4<1>, C4<1>;
+L_0x2a445f0 .delay (20000,20000,20000) L_0x2a445f0/d;
+L_0x2a446e0/d .functor OR 1, L_0x2a44500, L_0x2a445f0, C4<0>, C4<0>;
+L_0x2a446e0 .delay (20000,20000,20000) L_0x2a446e0/d;
+v0x23f1660_0 .net "S", 0 0, L_0x2a448c0; 1 drivers
+v0x2374ad0_0 .net "in0", 0 0, L_0x2a44960; 1 drivers
+v0x2374b70_0 .net "in1", 0 0, L_0x2a44a50; 1 drivers
+v0x23dbf90_0 .net "nS", 0 0, L_0x2a44410; 1 drivers
+v0x23dc010_0 .net "out0", 0 0, L_0x2a44500; 1 drivers
+v0x23d9fa0_0 .net "out1", 0 0, L_0x2a445f0; 1 drivers
+v0x23da040_0 .net "outfinal", 0 0, L_0x2a446e0; 1 drivers
+S_0x263baf0 .scope generate, "muxbits[21]" "muxbits[21]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x262fc18 .param/l "i" 3 397, +C4<010101>;
+L_0x2a47170/d .functor OR 1, L_0x2a472b0, L_0x2a47350, C4<0>, C4<0>;
+L_0x2a47170 .delay (20000,20000,20000) L_0x2a47170/d;
+v0x23f7390_0 .net *"_s15", 0 0, L_0x2a472b0; 1 drivers
+v0x23f7450_0 .net *"_s16", 0 0, L_0x2a47350; 1 drivers
+S_0x237a630 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x263baf0;
+ .timescale -9 -12;
+L_0x2a44d10/d .functor NOT 1, L_0x2a455b0, C4<0>, C4<0>, C4<0>;
+L_0x2a44d10 .delay (10000,10000,10000) L_0x2a44d10/d;
+L_0x2a44e00/d .functor NOT 1, L_0x2a456e0, C4<0>, C4<0>, C4<0>;
+L_0x2a44e00 .delay (10000,10000,10000) L_0x2a44e00/d;
+L_0x2a44ea0/d .functor NAND 1, L_0x2a44d10, L_0x2a44e00, L_0x2a45810, C4<1>;
+L_0x2a44ea0 .delay (10000,10000,10000) L_0x2a44ea0/d;
+L_0x2a44fe0/d .functor NAND 1, L_0x2a455b0, L_0x2a44e00, L_0x2a458b0, C4<1>;
+L_0x2a44fe0 .delay (10000,10000,10000) L_0x2a44fe0/d;
+L_0x2a450d0/d .functor NAND 1, L_0x2a44d10, L_0x2a456e0, L_0x2a45950, C4<1>;
+L_0x2a450d0 .delay (10000,10000,10000) L_0x2a450d0/d;
+L_0x2a451c0/d .functor NAND 1, L_0x2a455b0, L_0x2a456e0, L_0x2a45c60, C4<1>;
+L_0x2a451c0 .delay (10000,10000,10000) L_0x2a451c0/d;
+L_0x2a45300/d .functor NAND 1, L_0x2a44ea0, L_0x2a44fe0, L_0x2a450d0, L_0x2a451c0;
+L_0x2a45300 .delay (10000,10000,10000) L_0x2a45300/d;
+v0x260fee0_0 .net "S0", 0 0, L_0x2a455b0; 1 drivers
+v0x2414af0_0 .net "S1", 0 0, L_0x2a456e0; 1 drivers
+v0x2414b90_0 .net "in0", 0 0, L_0x2a45810; 1 drivers
+v0x2378640_0 .net "in1", 0 0, L_0x2a458b0; 1 drivers
+v0x23786e0_0 .net "in2", 0 0, L_0x2a45950; 1 drivers
+v0x2410d80_0 .net "in3", 0 0, L_0x2a45c60; 1 drivers
+v0x2410e20_0 .net "nS0", 0 0, L_0x2a44d10; 1 drivers
+v0x240ecb0_0 .net "nS1", 0 0, L_0x2a44e00; 1 drivers
+v0x240ed50_0 .net "out", 0 0, L_0x2a45300; 1 drivers
+v0x23fd1b0_0 .net "out0", 0 0, L_0x2a44ea0; 1 drivers
+v0x23fd250_0 .net "out1", 0 0, L_0x2a44fe0; 1 drivers
+v0x23f9440_0 .net "out2", 0 0, L_0x2a450d0; 1 drivers
+v0x23f94e0_0 .net "out3", 0 0, L_0x2a451c0; 1 drivers
+S_0x2639760 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x263baf0;
+ .timescale -9 -12;
+L_0x2a45d50/d .functor NOT 1, L_0x2a46520, C4<0>, C4<0>, C4<0>;
+L_0x2a45d50 .delay (10000,10000,10000) L_0x2a45d50/d;
+L_0x2a45e00/d .functor NOT 1, L_0x2a46650, C4<0>, C4<0>, C4<0>;
+L_0x2a45e00 .delay (10000,10000,10000) L_0x2a45e00/d;
+L_0x2a45ea0/d .functor NAND 1, L_0x2a45d50, L_0x2a45e00, L_0x2a46780, C4<1>;
+L_0x2a45ea0 .delay (10000,10000,10000) L_0x2a45ea0/d;
+L_0x2a45fe0/d .functor NAND 1, L_0x2a46520, L_0x2a45e00, L_0x2a46820, C4<1>;
+L_0x2a45fe0 .delay (10000,10000,10000) L_0x2a45fe0/d;
+L_0x2a460d0/d .functor NAND 1, L_0x2a45d50, L_0x2a46650, L_0x2a468c0, C4<1>;
+L_0x2a460d0 .delay (10000,10000,10000) L_0x2a460d0/d;
+L_0x2a461c0/d .functor NAND 1, L_0x2a46520, L_0x2a46650, L_0x2a47790, C4<1>;
+L_0x2a461c0 .delay (10000,10000,10000) L_0x2a461c0/d;
+L_0x2a462a0/d .functor NAND 1, L_0x2a45ea0, L_0x2a45fe0, L_0x2a460d0, L_0x2a461c0;
+L_0x2a462a0 .delay (10000,10000,10000) L_0x2a462a0/d;
+v0x2639aa0_0 .net "S0", 0 0, L_0x2a46520; 1 drivers
+v0x2641670_0 .net "S1", 0 0, L_0x2a46650; 1 drivers
+v0x2641710_0 .net "in0", 0 0, L_0x2a46780; 1 drivers
+v0x263fd80_0 .net "in1", 0 0, L_0x2a46820; 1 drivers
+v0x263fe20_0 .net "in2", 0 0, L_0x2a468c0; 1 drivers
+v0x263fad0_0 .net "in3", 0 0, L_0x2a47790; 1 drivers
+v0x263f820_0 .net "nS0", 0 0, L_0x2a45d50; 1 drivers
+v0x263f8c0_0 .net "nS1", 0 0, L_0x2a45e00; 1 drivers
+v0x263f580_0 .net "out", 0 0, L_0x2a462a0; 1 drivers
+v0x263f620_0 .net "out0", 0 0, L_0x2a45ea0; 1 drivers
+v0x2221490_0 .net "out1", 0 0, L_0x2a45fe0; 1 drivers
+v0x2221530_0 .net "out2", 0 0, L_0x2a460d0; 1 drivers
+v0x260fe40_0 .net "out3", 0 0, L_0x2a461c0; 1 drivers
+S_0x263b850 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x263baf0;
+ .timescale -9 -12;
+L_0x2a45220/d .functor NOT 1, L_0x2a46e50, C4<0>, C4<0>, C4<0>;
+L_0x2a45220 .delay (10000,10000,10000) L_0x2a45220/d;
+L_0x2a46a90/d .functor AND 1, L_0x2a46ef0, L_0x2a45220, C4<1>, C4<1>;
+L_0x2a46a90 .delay (20000,20000,20000) L_0x2a46a90/d;
+L_0x2a46b80/d .functor AND 1, L_0x2a46fe0, L_0x2a46e50, C4<1>, C4<1>;
+L_0x2a46b80 .delay (20000,20000,20000) L_0x2a46b80/d;
+L_0x2a46c70/d .functor OR 1, L_0x2a46a90, L_0x2a46b80, C4<0>, C4<0>;
+L_0x2a46c70 .delay (20000,20000,20000) L_0x2a46c70/d;
+v0x2639f60_0 .net "S", 0 0, L_0x2a46e50; 1 drivers
+v0x263a000_0 .net "in0", 0 0, L_0x2a46ef0; 1 drivers
+v0x2639cb0_0 .net "in1", 0 0, L_0x2a46fe0; 1 drivers
+v0x2639d50_0 .net "nS", 0 0, L_0x2a45220; 1 drivers
+v0x263d270_0 .net "out0", 0 0, L_0x2a46a90; 1 drivers
+v0x263d310_0 .net "out1", 0 0, L_0x2a46b80; 1 drivers
+v0x2639a00_0 .net "outfinal", 0 0, L_0x2a46c70; 1 drivers
+S_0x261c820 .scope generate, "muxbits[22]" "muxbits[22]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2618b78 .param/l "i" 3 397, +C4<010110>;
+L_0x2a49710/d .functor OR 1, L_0x2a49850, L_0x2a4a8e0, C4<0>, C4<0>;
+L_0x2a49710 .delay (20000,20000,20000) L_0x2a49710/d;
+v0x263bda0_0 .net *"_s15", 0 0, L_0x2a49850; 1 drivers
+v0x263be60_0 .net *"_s16", 0 0, L_0x2a4a8e0; 1 drivers
+S_0x2635a30 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x261c820;
+ .timescale -9 -12;
+L_0x2a47440/d .functor NOT 1, L_0x2a47880, C4<0>, C4<0>, C4<0>;
+L_0x2a47440 .delay (10000,10000,10000) L_0x2a47440/d;
+L_0x2a47530/d .functor NOT 1, L_0x2a479b0, C4<0>, C4<0>, C4<0>;
+L_0x2a47530 .delay (10000,10000,10000) L_0x2a47530/d;
+L_0x2a475d0/d .functor NAND 1, L_0x2a47440, L_0x2a47530, L_0x2a47ae0, C4<1>;
+L_0x2a475d0 .delay (10000,10000,10000) L_0x2a475d0/d;
+L_0x2a47710/d .functor NAND 1, L_0x2a47880, L_0x2a47530, L_0x2a47b80, C4<1>;
+L_0x2a47710 .delay (10000,10000,10000) L_0x2a47710/d;
+L_0x2a486e0/d .functor NAND 1, L_0x2a47440, L_0x2a479b0, L_0x2a47c20, C4<1>;
+L_0x2a486e0 .delay (10000,10000,10000) L_0x2a486e0/d;
+L_0x2a487d0/d .functor NAND 1, L_0x2a47880, L_0x2a479b0, L_0x2a47d10, C4<1>;
+L_0x2a487d0 .delay (10000,10000,10000) L_0x2a487d0/d;
+L_0x2a488b0/d .functor NAND 1, L_0x2a475d0, L_0x2a47710, L_0x2a486e0, L_0x2a487d0;
+L_0x2a488b0 .delay (10000,10000,10000) L_0x2a488b0/d;
+v0x2635d70_0 .net "S0", 0 0, L_0x2a47880; 1 drivers
+v0x2634140_0 .net "S1", 0 0, L_0x2a479b0; 1 drivers
+v0x26341e0_0 .net "in0", 0 0, L_0x2a47ae0; 1 drivers
+v0x2633e90_0 .net "in1", 0 0, L_0x2a47b80; 1 drivers
+v0x2633f30_0 .net "in2", 0 0, L_0x2a47c20; 1 drivers
+v0x2637450_0 .net "in3", 0 0, L_0x2a47d10; 1 drivers
+v0x26374f0_0 .net "nS0", 0 0, L_0x2a47440; 1 drivers
+v0x2633be0_0 .net "nS1", 0 0, L_0x2a47530; 1 drivers
+v0x2633c80_0 .net "out", 0 0, L_0x2a488b0; 1 drivers
+v0x2633940_0 .net "out0", 0 0, L_0x2a475d0; 1 drivers
+v0x26339e0_0 .net "out1", 0 0, L_0x2a47710; 1 drivers
+v0x263c050_0 .net "out2", 0 0, L_0x2a486e0; 1 drivers
+v0x263c0f0_0 .net "out3", 0 0, L_0x2a487d0; 1 drivers
+S_0x2621e40 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x261c820;
+ .timescale -9 -12;
+L_0x2a47e00/d .functor NOT 1, L_0x2a49940, C4<0>, C4<0>, C4<0>;
+L_0x2a47e00 .delay (10000,10000,10000) L_0x2a47e00/d;
+L_0x2a47ef0/d .functor NOT 1, L_0x2a48b30, C4<0>, C4<0>, C4<0>;
+L_0x2a47ef0 .delay (10000,10000,10000) L_0x2a47ef0/d;
+L_0x2a47f90/d .functor NAND 1, L_0x2a47e00, L_0x2a47ef0, L_0x2a48c60, C4<1>;
+L_0x2a47f90 .delay (10000,10000,10000) L_0x2a47f90/d;
+L_0x2a480d0/d .functor NAND 1, L_0x2a49940, L_0x2a47ef0, L_0x2a48d00, C4<1>;
+L_0x2a480d0 .delay (10000,10000,10000) L_0x2a480d0/d;
+L_0x2a481c0/d .functor NAND 1, L_0x2a47e00, L_0x2a48b30, L_0x2a48da0, C4<1>;
+L_0x2a481c0 .delay (10000,10000,10000) L_0x2a481c0/d;
+L_0x2a482b0/d .functor NAND 1, L_0x2a49940, L_0x2a48b30, L_0x2a48e90, C4<1>;
+L_0x2a482b0 .delay (10000,10000,10000) L_0x2a482b0/d;
+L_0x2a48390/d .functor NAND 1, L_0x2a47f90, L_0x2a480d0, L_0x2a481c0, L_0x2a482b0;
+L_0x2a48390 .delay (10000,10000,10000) L_0x2a48390/d;
+v0x2623f70_0 .net "S0", 0 0, L_0x2a49940; 1 drivers
+v0x2629d30_0 .net "S1", 0 0, L_0x2a48b30; 1 drivers
+v0x2629dd0_0 .net "in0", 0 0, L_0x2a48c60; 1 drivers
+v0x2627c40_0 .net "in1", 0 0, L_0x2a48d00; 1 drivers
+v0x2627ce0_0 .net "in2", 0 0, L_0x2a48da0; 1 drivers
+v0x262fb90_0 .net "in3", 0 0, L_0x2a48e90; 1 drivers
+v0x262daa0_0 .net "nS0", 0 0, L_0x2a47e00; 1 drivers
+v0x262db40_0 .net "nS1", 0 0, L_0x2a47ef0; 1 drivers
+v0x2636230_0 .net "out", 0 0, L_0x2a48390; 1 drivers
+v0x26362d0_0 .net "out0", 0 0, L_0x2a47f90; 1 drivers
+v0x2635f80_0 .net "out1", 0 0, L_0x2a480d0; 1 drivers
+v0x2636020_0 .net "out2", 0 0, L_0x2a481c0; 1 drivers
+v0x2635cd0_0 .net "out3", 0 0, L_0x2a482b0; 1 drivers
+S_0x261c570 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x261c820;
+ .timescale -9 -12;
+L_0x2a48f80/d .functor NOT 1, L_0x2a493f0, C4<0>, C4<0>, C4<0>;
+L_0x2a48f80 .delay (10000,10000,10000) L_0x2a48f80/d;
+L_0x2a49030/d .functor AND 1, L_0x2a49490, L_0x2a48f80, C4<1>, C4<1>;
+L_0x2a49030 .delay (20000,20000,20000) L_0x2a49030/d;
+L_0x2a49120/d .functor AND 1, L_0x2a49580, L_0x2a493f0, C4<1>, C4<1>;
+L_0x2a49120 .delay (20000,20000,20000) L_0x2a49120/d;
+L_0x2a49210/d .functor OR 1, L_0x2a49030, L_0x2a49120, C4<0>, C4<0>;
+L_0x2a49210 .delay (20000,20000,20000) L_0x2a49210/d;
+v0x261fb30_0 .net "S", 0 0, L_0x2a493f0; 1 drivers
+v0x261fbd0_0 .net "in0", 0 0, L_0x2a49490; 1 drivers
+v0x261c2c0_0 .net "in1", 0 0, L_0x2a49580; 1 drivers
+v0x261c360_0 .net "nS", 0 0, L_0x2a48f80; 1 drivers
+v0x261c020_0 .net "out0", 0 0, L_0x2a49030; 1 drivers
+v0x261c0c0_0 .net "out1", 0 0, L_0x2a49120; 1 drivers
+v0x2623ed0_0 .net "outfinal", 0 0, L_0x2a49210; 1 drivers
+S_0x26046c0 .scope generate, "muxbits[23]" "muxbits[23]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x25f9098 .param/l "i" 3 397, +C4<010111>;
+L_0x2a4b6d0/d .functor OR 1, L_0x2a4ce70, L_0x2a4bf60, C4<0>, C4<0>;
+L_0x2a4b6d0 .delay (20000,20000,20000) L_0x2a4b6d0/d;
+v0x261e110_0 .net *"_s15", 0 0, L_0x2a4ce70; 1 drivers
+v0x261e1d0_0 .net *"_s16", 0 0, L_0x2a4bf60; 1 drivers
+S_0x2616750 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x26046c0;
+ .timescale -9 -12;
+L_0x2a49a70/d .functor NOT 1, L_0x2a4a280, C4<0>, C4<0>, C4<0>;
+L_0x2a49a70 .delay (10000,10000,10000) L_0x2a49a70/d;
+L_0x2a49b60/d .functor NOT 1, L_0x2a4a3b0, C4<0>, C4<0>, C4<0>;
+L_0x2a49b60 .delay (10000,10000,10000) L_0x2a49b60/d;
+L_0x2a49c00/d .functor NAND 1, L_0x2a49a70, L_0x2a49b60, L_0x2a4a4e0, C4<1>;
+L_0x2a49c00 .delay (10000,10000,10000) L_0x2a49c00/d;
+L_0x2a49d40/d .functor NAND 1, L_0x2a4a280, L_0x2a49b60, L_0x2a4a580, C4<1>;
+L_0x2a49d40 .delay (10000,10000,10000) L_0x2a49d40/d;
+L_0x2a49e30/d .functor NAND 1, L_0x2a49a70, L_0x2a4a3b0, L_0x2a4a620, C4<1>;
+L_0x2a49e30 .delay (10000,10000,10000) L_0x2a49e30/d;
+L_0x2a49f20/d .functor NAND 1, L_0x2a4a280, L_0x2a4a3b0, L_0x2a4a710, C4<1>;
+L_0x2a49f20 .delay (10000,10000,10000) L_0x2a49f20/d;
+L_0x2a4a000/d .functor NAND 1, L_0x2a49c00, L_0x2a49d40, L_0x2a49e30, L_0x2a49f20;
+L_0x2a4a000 .delay (10000,10000,10000) L_0x2a4a000/d;
+v0x2616aa0_0 .net "S0", 0 0, L_0x2a4a280; 1 drivers
+v0x2619d10_0 .net "S1", 0 0, L_0x2a4a3b0; 1 drivers
+v0x2619db0_0 .net "in0", 0 0, L_0x2a4a4e0; 1 drivers
+v0x26164a0_0 .net "in1", 0 0, L_0x2a4a580; 1 drivers
+v0x2616540_0 .net "in2", 0 0, L_0x2a4a620; 1 drivers
+v0x2616200_0 .net "in3", 0 0, L_0x2a4a710; 1 drivers
+v0x26162a0_0 .net "nS0", 0 0, L_0x2a49a70; 1 drivers
+v0x261e910_0 .net "nS1", 0 0, L_0x2a49b60; 1 drivers
+v0x261e9b0_0 .net "out", 0 0, L_0x2a4a000; 1 drivers
+v0x261e660_0 .net "out0", 0 0, L_0x2a49c00; 1 drivers
+v0x261e700_0 .net "out1", 0 0, L_0x2a49d40; 1 drivers
+v0x261e3b0_0 .net "out2", 0 0, L_0x2a49e30; 1 drivers
+v0x261e450_0 .net "out3", 0 0, L_0x2a49f20; 1 drivers
+S_0x26124d0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x26046c0;
+ .timescale -9 -12;
+L_0x2a4a800/d .functor NOT 1, L_0x2a4a980, C4<0>, C4<0>, C4<0>;
+L_0x2a4a800 .delay (10000,10000,10000) L_0x2a4a800/d;
+L_0x2a4b880/d .functor NOT 1, L_0x2a4aab0, C4<0>, C4<0>, C4<0>;
+L_0x2a4b880 .delay (10000,10000,10000) L_0x2a4b880/d;
+L_0x2a4b8e0/d .functor NAND 1, L_0x2a4a800, L_0x2a4b880, L_0x2a4abe0, C4<1>;
+L_0x2a4b8e0 .delay (10000,10000,10000) L_0x2a4b8e0/d;
+L_0x2a4ba20/d .functor NAND 1, L_0x2a4a980, L_0x2a4b880, L_0x2a4ac80, C4<1>;
+L_0x2a4ba20 .delay (10000,10000,10000) L_0x2a4ba20/d;
+L_0x2a4bb10/d .functor NAND 1, L_0x2a4a800, L_0x2a4aab0, L_0x2a4ad20, C4<1>;
+L_0x2a4bb10 .delay (10000,10000,10000) L_0x2a4bb10/d;
+L_0x2a4bc00/d .functor NAND 1, L_0x2a4a980, L_0x2a4aab0, L_0x2a4ae10, C4<1>;
+L_0x2a4bc00 .delay (10000,10000,10000) L_0x2a4bc00/d;
+L_0x2a4bce0/d .functor NAND 1, L_0x2a4b8e0, L_0x2a4ba20, L_0x2a4bb10, L_0x2a4bc00;
+L_0x2a4bce0 .delay (10000,10000,10000) L_0x2a4bce0/d;
+v0x2612810_0 .net "S0", 0 0, L_0x2a4a980; 1 drivers
+v0x2613ef0_0 .net "S1", 0 0, L_0x2a4aab0; 1 drivers
+v0x2613f90_0 .net "in0", 0 0, L_0x2a4abe0; 1 drivers
+v0x2610380_0 .net "in1", 0 0, L_0x2a4ac80; 1 drivers
+v0x2610420_0 .net "in2", 0 0, L_0x2a4ad20; 1 drivers
+v0x2618af0_0 .net "in3", 0 0, L_0x2a4ae10; 1 drivers
+v0x2618840_0 .net "nS0", 0 0, L_0x2a4a800; 1 drivers
+v0x26188e0_0 .net "nS1", 0 0, L_0x2a4b880; 1 drivers
+v0x2618590_0 .net "out", 0 0, L_0x2a4bce0; 1 drivers
+v0x2618630_0 .net "out0", 0 0, L_0x2a4b8e0; 1 drivers
+v0x26182f0_0 .net "out1", 0 0, L_0x2a4ba20; 1 drivers
+v0x2618390_0 .net "out2", 0 0, L_0x2a4bb10; 1 drivers
+v0x2616a00_0 .net "out3", 0 0, L_0x2a4bc00; 1 drivers
+S_0x260c610 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x26046c0;
+ .timescale -9 -12;
+L_0x2a4af00/d .functor NOT 1, L_0x2a4b3b0, C4<0>, C4<0>, C4<0>;
+L_0x2a4af00 .delay (10000,10000,10000) L_0x2a4af00/d;
+L_0x2a4aff0/d .functor AND 1, L_0x2a4b450, L_0x2a4af00, C4<1>, C4<1>;
+L_0x2a4aff0 .delay (20000,20000,20000) L_0x2a4aff0/d;
+L_0x2a4b0e0/d .functor AND 1, L_0x2a4b540, L_0x2a4b3b0, C4<1>, C4<1>;
+L_0x2a4b0e0 .delay (20000,20000,20000) L_0x2a4b0e0/d;
+L_0x2a4b1d0/d .functor OR 1, L_0x2a4aff0, L_0x2a4b0e0, C4<0>, C4<0>;
+L_0x2a4b1d0 .delay (20000,20000,20000) L_0x2a4b1d0/d;
+v0x260a520_0 .net "S", 0 0, L_0x2a4b3b0; 1 drivers
+v0x260a5c0_0 .net "in0", 0 0, L_0x2a4b450; 1 drivers
+v0x2612cd0_0 .net "in1", 0 0, L_0x2a4b540; 1 drivers
+v0x2612d70_0 .net "nS", 0 0, L_0x2a4af00; 1 drivers
+v0x2612a20_0 .net "out0", 0 0, L_0x2a4aff0; 1 drivers
+v0x2612ac0_0 .net "out1", 0 0, L_0x2a4b0e0; 1 drivers
+v0x2612770_0 .net "outfinal", 0 0, L_0x2a4b1d0; 1 drivers
+S_0x25f31f0 .scope generate, "muxbits[24]" "muxbits[24]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x25e3298 .param/l "i" 3 397, +C4<011000>;
+L_0x2a4db30/d .functor OR 1, L_0x2a4dc70, L_0x2a4dd10, C4<0>, C4<0>;
+L_0x2a4db30 .delay (20000,20000,20000) L_0x2a4db30/d;
+v0x26067b0_0 .net *"_s15", 0 0, L_0x2a4dc70; 1 drivers
+v0x2606870_0 .net *"_s16", 0 0, L_0x2a4dd10; 1 drivers
+S_0x2600f20 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25f31f0;
+ .timescale -9 -12;
+L_0x2a4c050/d .functor NOT 1, L_0x2a4c860, C4<0>, C4<0>, C4<0>;
+L_0x2a4c050 .delay (10000,10000,10000) L_0x2a4c050/d;
+L_0x2a4c140/d .functor NOT 1, L_0x2a4c990, C4<0>, C4<0>, C4<0>;
+L_0x2a4c140 .delay (10000,10000,10000) L_0x2a4c140/d;
+L_0x2a4c1e0/d .functor NAND 1, L_0x2a4c050, L_0x2a4c140, L_0x2a4cac0, C4<1>;
+L_0x2a4c1e0 .delay (10000,10000,10000) L_0x2a4c1e0/d;
+L_0x2a4c320/d .functor NAND 1, L_0x2a4c860, L_0x2a4c140, L_0x2a4cb60, C4<1>;
+L_0x2a4c320 .delay (10000,10000,10000) L_0x2a4c320/d;
+L_0x2a4c410/d .functor NAND 1, L_0x2a4c050, L_0x2a4c990, L_0x2a4cc00, C4<1>;
+L_0x2a4c410 .delay (10000,10000,10000) L_0x2a4c410/d;
+L_0x2a4c500/d .functor NAND 1, L_0x2a4c860, L_0x2a4c990, L_0x2a4ccf0, C4<1>;
+L_0x2a4c500 .delay (10000,10000,10000) L_0x2a4c500/d;
+L_0x2a4c5e0/d .functor NAND 1, L_0x2a4c1e0, L_0x2a4c320, L_0x2a4c410, L_0x2a4c500;
+L_0x2a4c5e0 .delay (10000,10000,10000) L_0x2a4c5e0/d;
+v0x2601270_0 .net "S0", 0 0, L_0x2a4c860; 1 drivers
+v0x2600c70_0 .net "S1", 0 0, L_0x2a4c990; 1 drivers
+v0x2600d10_0 .net "in0", 0 0, L_0x2a4cac0; 1 drivers
+v0x26009d0_0 .net "in1", 0 0, L_0x2a4cb60; 1 drivers
+v0x2600a70_0 .net "in2", 0 0, L_0x2a4cc00; 1 drivers
+v0x25ff0e0_0 .net "in3", 0 0, L_0x2a4ccf0; 1 drivers
+v0x25ff180_0 .net "nS0", 0 0, L_0x2a4c050; 1 drivers
+v0x25fee30_0 .net "nS1", 0 0, L_0x2a4c140; 1 drivers
+v0x25feed0_0 .net "out", 0 0, L_0x2a4c5e0; 1 drivers
+v0x25feb80_0 .net "out0", 0 0, L_0x2a4c1e0; 1 drivers
+v0x25fec20_0 .net "out1", 0 0, L_0x2a4c320; 1 drivers
+v0x25fe8e0_0 .net "out2", 0 0, L_0x2a4c410; 1 drivers
+v0x25fe980_0 .net "out3", 0 0, L_0x2a4c500; 1 drivers
+S_0x25fae50 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25f31f0;
+ .timescale -9 -12;
+L_0x2a4cde0/d .functor NOT 1, L_0x2a4e620, C4<0>, C4<0>, C4<0>;
+L_0x2a4cde0 .delay (10000,10000,10000) L_0x2a4cde0/d;
+L_0x2a4df00/d .functor NOT 1, L_0x2a4cf10, C4<0>, C4<0>, C4<0>;
+L_0x2a4df00 .delay (10000,10000,10000) L_0x2a4df00/d;
+L_0x2a4dfa0/d .functor NAND 1, L_0x2a4cde0, L_0x2a4df00, L_0x2a4d040, C4<1>;
+L_0x2a4dfa0 .delay (10000,10000,10000) L_0x2a4dfa0/d;
+L_0x2a4e0e0/d .functor NAND 1, L_0x2a4e620, L_0x2a4df00, L_0x2a4d0e0, C4<1>;
+L_0x2a4e0e0 .delay (10000,10000,10000) L_0x2a4e0e0/d;
+L_0x2a4e1d0/d .functor NAND 1, L_0x2a4cde0, L_0x2a4cf10, L_0x2a4d180, C4<1>;
+L_0x2a4e1d0 .delay (10000,10000,10000) L_0x2a4e1d0/d;
+L_0x2a4e2c0/d .functor NAND 1, L_0x2a4e620, L_0x2a4cf10, L_0x2a4d270, C4<1>;
+L_0x2a4e2c0 .delay (10000,10000,10000) L_0x2a4e2c0/d;
+L_0x2a4e3a0/d .functor NAND 1, L_0x2a4dfa0, L_0x2a4e0e0, L_0x2a4e1d0, L_0x2a4e2c0;
+L_0x2a4e3a0 .delay (10000,10000,10000) L_0x2a4e3a0/d;
+v0x25fb1a0_0 .net "S0", 0 0, L_0x2a4e620; 1 drivers
+v0x25fabb0_0 .net "S1", 0 0, L_0x2a4cf10; 1 drivers
+v0x25fac50_0 .net "in0", 0 0, L_0x2a4d040; 1 drivers
+v0x25f92c0_0 .net "in1", 0 0, L_0x2a4d0e0; 1 drivers
+v0x25f9360_0 .net "in2", 0 0, L_0x2a4d180; 1 drivers
+v0x25f9010_0 .net "in3", 0 0, L_0x2a4d270; 1 drivers
+v0x25fc5d0_0 .net "nS0", 0 0, L_0x2a4cde0; 1 drivers
+v0x25fc670_0 .net "nS1", 0 0, L_0x2a4df00; 1 drivers
+v0x25f8d60_0 .net "out", 0 0, L_0x2a4e3a0; 1 drivers
+v0x25f8e00_0 .net "out0", 0 0, L_0x2a4dfa0; 1 drivers
+v0x25f8ac0_0 .net "out1", 0 0, L_0x2a4e0e0; 1 drivers
+v0x25f8b60_0 .net "out2", 0 0, L_0x2a4e1d0; 1 drivers
+v0x26011d0_0 .net "out3", 0 0, L_0x2a4e2c0; 1 drivers
+S_0x25f67b0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25f31f0;
+ .timescale -9 -12;
+L_0x2a4d360/d .functor NOT 1, L_0x2a4d810, C4<0>, C4<0>, C4<0>;
+L_0x2a4d360 .delay (10000,10000,10000) L_0x2a4d360/d;
+L_0x2a4d450/d .functor AND 1, L_0x2a4d8b0, L_0x2a4d360, C4<1>, C4<1>;
+L_0x2a4d450 .delay (20000,20000,20000) L_0x2a4d450/d;
+L_0x2a4d540/d .functor AND 1, L_0x2a4d9a0, L_0x2a4d810, C4<1>, C4<1>;
+L_0x2a4d540 .delay (20000,20000,20000) L_0x2a4d540/d;
+L_0x2a4d630/d .functor OR 1, L_0x2a4d450, L_0x2a4d540, C4<0>, C4<0>;
+L_0x2a4d630 .delay (20000,20000,20000) L_0x2a4d630/d;
+v0x25f2f40_0 .net "S", 0 0, L_0x2a4d810; 1 drivers
+v0x25f2fe0_0 .net "in0", 0 0, L_0x2a4d8b0; 1 drivers
+v0x25f2ca0_0 .net "in1", 0 0, L_0x2a4d9a0; 1 drivers
+v0x25f2d40_0 .net "nS", 0 0, L_0x2a4d360; 1 drivers
+v0x25fb3b0_0 .net "out0", 0 0, L_0x2a4d450; 1 drivers
+v0x25fb450_0 .net "out1", 0 0, L_0x2a4d540; 1 drivers
+v0x25fb100_0 .net "outfinal", 0 0, L_0x2a4d630; 1 drivers
+S_0x25ddc50 .scope generate, "muxbits[25]" "muxbits[25]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x25c98e8 .param/l "i" 3 397, +C4<011001>;
+L_0x2a509b0/d .functor OR 1, L_0x2a50af0, L_0x2a50b90, C4<0>, C4<0>;
+L_0x2a509b0 .delay (20000,20000,20000) L_0x2a509b0/d;
+v0x25f34a0_0 .net *"_s15", 0 0, L_0x2a50af0; 1 drivers
+v0x25f3560_0 .net *"_s16", 0 0, L_0x2a50b90; 1 drivers
+S_0x25e6f80 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25ddc50;
+ .timescale -9 -12;
+L_0x2a4de00/d .functor NOT 1, L_0x2a4fed0, C4<0>, C4<0>, C4<0>;
+L_0x2a4de00 .delay (10000,10000,10000) L_0x2a4de00/d;
+L_0x2a4f7b0/d .functor NOT 1, L_0x2a4e750, C4<0>, C4<0>, C4<0>;
+L_0x2a4f7b0 .delay (10000,10000,10000) L_0x2a4f7b0/d;
+L_0x2a4f850/d .functor NAND 1, L_0x2a4de00, L_0x2a4f7b0, L_0x2a4e880, C4<1>;
+L_0x2a4f850 .delay (10000,10000,10000) L_0x2a4f850/d;
+L_0x2a4f990/d .functor NAND 1, L_0x2a4fed0, L_0x2a4f7b0, L_0x2a4e920, C4<1>;
+L_0x2a4f990 .delay (10000,10000,10000) L_0x2a4f990/d;
+L_0x2a4fa80/d .functor NAND 1, L_0x2a4de00, L_0x2a4e750, L_0x2a4e9c0, C4<1>;
+L_0x2a4fa80 .delay (10000,10000,10000) L_0x2a4fa80/d;
+L_0x2a4fb70/d .functor NAND 1, L_0x2a4fed0, L_0x2a4e750, L_0x2a4eab0, C4<1>;
+L_0x2a4fb70 .delay (10000,10000,10000) L_0x2a4fb70/d;
+L_0x2a4fc50/d .functor NAND 1, L_0x2a4f850, L_0x2a4f990, L_0x2a4fa80, L_0x2a4fb70;
+L_0x2a4fc50 .delay (10000,10000,10000) L_0x2a4fc50/d;
+v0x25e9110_0 .net "S0", 0 0, L_0x2a4fed0; 1 drivers
+v0x25eeed0_0 .net "S1", 0 0, L_0x2a4e750; 1 drivers
+v0x25eef70_0 .net "in0", 0 0, L_0x2a4e880; 1 drivers
+v0x25ecde0_0 .net "in1", 0 0, L_0x2a4e920; 1 drivers
+v0x25ece80_0 .net "in2", 0 0, L_0x2a4e9c0; 1 drivers
+v0x25f5590_0 .net "in3", 0 0, L_0x2a4eab0; 1 drivers
+v0x25f5630_0 .net "nS0", 0 0, L_0x2a4de00; 1 drivers
+v0x25f52e0_0 .net "nS1", 0 0, L_0x2a4f7b0; 1 drivers
+v0x25f5380_0 .net "out", 0 0, L_0x2a4fc50; 1 drivers
+v0x25f5030_0 .net "out0", 0 0, L_0x2a4f850; 1 drivers
+v0x25f50d0_0 .net "out1", 0 0, L_0x2a4f990; 1 drivers
+v0x25f4d90_0 .net "out2", 0 0, L_0x2a4fa80; 1 drivers
+v0x25f4e30_0 .net "out3", 0 0, L_0x2a4fb70; 1 drivers
+S_0x25dee70 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25ddc50;
+ .timescale -9 -12;
+L_0x2a4eba0/d .functor NOT 1, L_0x2a4f3b0, C4<0>, C4<0>, C4<0>;
+L_0x2a4eba0 .delay (10000,10000,10000) L_0x2a4eba0/d;
+L_0x2a4ec90/d .functor NOT 1, L_0x2a4f4e0, C4<0>, C4<0>, C4<0>;
+L_0x2a4ec90 .delay (10000,10000,10000) L_0x2a4ec90/d;
+L_0x2a4ed30/d .functor NAND 1, L_0x2a4eba0, L_0x2a4ec90, L_0x2a4f610, C4<1>;
+L_0x2a4ed30 .delay (10000,10000,10000) L_0x2a4ed30/d;
+L_0x2a4ee70/d .functor NAND 1, L_0x2a4f3b0, L_0x2a4ec90, L_0x2a51020, C4<1>;
+L_0x2a4ee70 .delay (10000,10000,10000) L_0x2a4ee70/d;
+L_0x2a4ef60/d .functor NAND 1, L_0x2a4eba0, L_0x2a4f4e0, L_0x2a50000, C4<1>;
+L_0x2a4ef60 .delay (10000,10000,10000) L_0x2a4ef60/d;
+L_0x2a4f050/d .functor NAND 1, L_0x2a4f3b0, L_0x2a4f4e0, L_0x2a500f0, C4<1>;
+L_0x2a4f050 .delay (10000,10000,10000) L_0x2a4f050/d;
+L_0x2a4f130/d .functor NAND 1, L_0x2a4ed30, L_0x2a4ee70, L_0x2a4ef60, L_0x2a4f050;
+L_0x2a4f130 .delay (10000,10000,10000) L_0x2a4f130/d;
+v0x25db950_0 .net "S0", 0 0, L_0x2a4f3b0; 1 drivers
+v0x25db600_0 .net "S1", 0 0, L_0x2a4f4e0; 1 drivers
+v0x25db6a0_0 .net "in0", 0 0, L_0x2a4f610; 1 drivers
+v0x25db360_0 .net "in1", 0 0, L_0x2a51020; 1 drivers
+v0x25db400_0 .net "in2", 0 0, L_0x2a50000; 1 drivers
+v0x25e3210_0 .net "in3", 0 0, L_0x2a500f0; 1 drivers
+v0x25e16d0_0 .net "nS0", 0 0, L_0x2a4eba0; 1 drivers
+v0x25e1770_0 .net "nS1", 0 0, L_0x2a4ec90; 1 drivers
+v0x25e1420_0 .net "out", 0 0, L_0x2a4f130; 1 drivers
+v0x25e14c0_0 .net "out0", 0 0, L_0x2a4ed30; 1 drivers
+v0x25e1180_0 .net "out1", 0 0, L_0x2a4ee70; 1 drivers
+v0x25e1220_0 .net "out2", 0 0, L_0x2a4ef60; 1 drivers
+v0x25e9070_0 .net "out3", 0 0, L_0x2a4f050; 1 drivers
+S_0x25dd9a0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25ddc50;
+ .timescale -9 -12;
+L_0x2a501e0/d .functor NOT 1, L_0x2a50690, C4<0>, C4<0>, C4<0>;
+L_0x2a501e0 .delay (10000,10000,10000) L_0x2a501e0/d;
+L_0x2a502d0/d .functor AND 1, L_0x2a50730, L_0x2a501e0, C4<1>, C4<1>;
+L_0x2a502d0 .delay (20000,20000,20000) L_0x2a502d0/d;
+L_0x2a503c0/d .functor AND 1, L_0x2a50820, L_0x2a50690, C4<1>, C4<1>;
+L_0x2a503c0 .delay (20000,20000,20000) L_0x2a503c0/d;
+L_0x2a504b0/d .functor OR 1, L_0x2a502d0, L_0x2a503c0, C4<0>, C4<0>;
+L_0x2a504b0 .delay (20000,20000,20000) L_0x2a504b0/d;
+v0x25dd6f0_0 .net "S", 0 0, L_0x2a50690; 1 drivers
+v0x25dd790_0 .net "in0", 0 0, L_0x2a50730; 1 drivers
+v0x25dd450_0 .net "in1", 0 0, L_0x2a50820; 1 drivers
+v0x25dd4f0_0 .net "nS", 0 0, L_0x2a501e0; 1 drivers
+v0x25dbb60_0 .net "out0", 0 0, L_0x2a502d0; 1 drivers
+v0x25dbc00_0 .net "out1", 0 0, L_0x2a503c0; 1 drivers
+v0x25db8b0_0 .net "outfinal", 0 0, L_0x2a504b0; 1 drivers
+S_0x25bfd10 .scope generate, "muxbits[26]" "muxbits[26]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x25b2308 .param/l "i" 3 397, +C4<011010>;
+L_0x2a52fd0/d .functor OR 1, L_0x2a53110, L_0x2a531b0, C4<0>, C4<0>;
+L_0x2a52fd0 .delay (20000,20000,20000) L_0x2a52fd0/d;
+v0x25d5540_0 .net *"_s15", 0 0, L_0x2a53110; 1 drivers
+v0x25d5600_0 .net *"_s16", 0 0, L_0x2a531b0; 1 drivers
+S_0x25d7b80 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25bfd10;
+ .timescale -9 -12;
+L_0x2a50c80/d .functor NOT 1, L_0x2a510c0, C4<0>, C4<0>, C4<0>;
+L_0x2a50c80 .delay (10000,10000,10000) L_0x2a50c80/d;
+L_0x2a50d70/d .functor NOT 1, L_0x2a511f0, C4<0>, C4<0>, C4<0>;
+L_0x2a50d70 .delay (10000,10000,10000) L_0x2a50d70/d;
+L_0x2a50e10/d .functor NAND 1, L_0x2a50c80, L_0x2a50d70, L_0x2a51320, C4<1>;
+L_0x2a50e10 .delay (10000,10000,10000) L_0x2a50e10/d;
+L_0x2a50f50/d .functor NAND 1, L_0x2a510c0, L_0x2a50d70, L_0x2a513c0, C4<1>;
+L_0x2a50f50 .delay (10000,10000,10000) L_0x2a50f50/d;
+L_0x2a52130/d .functor NAND 1, L_0x2a50c80, L_0x2a511f0, L_0x2a51460, C4<1>;
+L_0x2a52130 .delay (10000,10000,10000) L_0x2a52130/d;
+L_0x2a52220/d .functor NAND 1, L_0x2a510c0, L_0x2a511f0, L_0x2a51550, C4<1>;
+L_0x2a52220 .delay (10000,10000,10000) L_0x2a52220/d;
+L_0x2a52300/d .functor NAND 1, L_0x2a50e10, L_0x2a50f50, L_0x2a52130, L_0x2a52220;
+L_0x2a52300 .delay (10000,10000,10000) L_0x2a52300/d;
+v0x25d7ed0_0 .net "S0", 0 0, L_0x2a510c0; 1 drivers
+v0x25d78d0_0 .net "S1", 0 0, L_0x2a511f0; 1 drivers
+v0x25d7970_0 .net "in0", 0 0, L_0x2a51320; 1 drivers
+v0x25d7630_0 .net "in1", 0 0, L_0x2a513c0; 1 drivers
+v0x25d76d0_0 .net "in2", 0 0, L_0x2a51460; 1 drivers
+v0x25d5d40_0 .net "in3", 0 0, L_0x2a51550; 1 drivers
+v0x25d5de0_0 .net "nS0", 0 0, L_0x2a50c80; 1 drivers
+v0x25d5a90_0 .net "nS1", 0 0, L_0x2a50d70; 1 drivers
+v0x25d5b30_0 .net "out", 0 0, L_0x2a52300; 1 drivers
+v0x25d9050_0 .net "out0", 0 0, L_0x2a50e10; 1 drivers
+v0x25d90f0_0 .net "out1", 0 0, L_0x2a50f50; 1 drivers
+v0x25d57e0_0 .net "out2", 0 0, L_0x2a52130; 1 drivers
+v0x25d5880_0 .net "out3", 0 0, L_0x2a52220; 1 drivers
+S_0x25c5af0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25bfd10;
+ .timescale -9 -12;
+L_0x2a51640/d .functor NOT 1, L_0x2a51e50, C4<0>, C4<0>, C4<0>;
+L_0x2a51640 .delay (10000,10000,10000) L_0x2a51640/d;
+L_0x2a51730/d .functor NOT 1, L_0x2a51f80, C4<0>, C4<0>, C4<0>;
+L_0x2a51730 .delay (10000,10000,10000) L_0x2a51730/d;
+L_0x2a517d0/d .functor NAND 1, L_0x2a51640, L_0x2a51730, L_0x2a53640, C4<1>;
+L_0x2a517d0 .delay (10000,10000,10000) L_0x2a517d0/d;
+L_0x2a51910/d .functor NAND 1, L_0x2a51e50, L_0x2a51730, L_0x2a52580, C4<1>;
+L_0x2a51910 .delay (10000,10000,10000) L_0x2a51910/d;
+L_0x2a51a00/d .functor NAND 1, L_0x2a51640, L_0x2a51f80, L_0x2a52620, C4<1>;
+L_0x2a51a00 .delay (10000,10000,10000) L_0x2a51a00/d;
+L_0x2a51af0/d .functor NAND 1, L_0x2a51e50, L_0x2a51f80, L_0x2a52710, C4<1>;
+L_0x2a51af0 .delay (10000,10000,10000) L_0x2a51af0/d;
+L_0x2a51bd0/d .functor NAND 1, L_0x2a517d0, L_0x2a51910, L_0x2a51a00, L_0x2a51af0;
+L_0x2a51bd0 .delay (10000,10000,10000) L_0x2a51bd0/d;
+v0x25bdcc0_0 .net "S0", 0 0, L_0x2a51e50; 1 drivers
+v0x25c3a00_0 .net "S1", 0 0, L_0x2a51f80; 1 drivers
+v0x25c3aa0_0 .net "in0", 0 0, L_0x2a53640; 1 drivers
+v0x25cb950_0 .net "in1", 0 0, L_0x2a52580; 1 drivers
+v0x25cb9f0_0 .net "in2", 0 0, L_0x2a52620; 1 drivers
+v0x25c9860_0 .net "in3", 0 0, L_0x2a52710; 1 drivers
+v0x25d2010_0 .net "nS0", 0 0, L_0x2a51640; 1 drivers
+v0x25d20b0_0 .net "nS1", 0 0, L_0x2a51730; 1 drivers
+v0x25d3230_0 .net "out", 0 0, L_0x2a51bd0; 1 drivers
+v0x25d32d0_0 .net "out0", 0 0, L_0x2a517d0; 1 drivers
+v0x25cf6c0_0 .net "out1", 0 0, L_0x2a51910; 1 drivers
+v0x25cf760_0 .net "out2", 0 0, L_0x2a51a00; 1 drivers
+v0x25d7e30_0 .net "out3", 0 0, L_0x2a51af0; 1 drivers
+S_0x25be420 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25bfd10;
+ .timescale -9 -12;
+L_0x2a52800/d .functor NOT 1, L_0x2a52cb0, C4<0>, C4<0>, C4<0>;
+L_0x2a52800 .delay (10000,10000,10000) L_0x2a52800/d;
+L_0x2a528f0/d .functor AND 1, L_0x2a52d50, L_0x2a52800, C4<1>, C4<1>;
+L_0x2a528f0 .delay (20000,20000,20000) L_0x2a528f0/d;
+L_0x2a529e0/d .functor AND 1, L_0x2a52e40, L_0x2a52cb0, C4<1>, C4<1>;
+L_0x2a529e0 .delay (20000,20000,20000) L_0x2a529e0/d;
+L_0x2a52ad0/d .functor OR 1, L_0x2a528f0, L_0x2a529e0, C4<0>, C4<0>;
+L_0x2a52ad0 .delay (20000,20000,20000) L_0x2a52ad0/d;
+v0x25be170_0 .net "S", 0 0, L_0x2a52cb0; 1 drivers
+v0x25be230_0 .net "in0", 0 0, L_0x2a52d50; 1 drivers
+v0x25c1730_0 .net "in1", 0 0, L_0x2a52e40; 1 drivers
+v0x25c17d0_0 .net "nS", 0 0, L_0x2a52800; 1 drivers
+v0x25bdec0_0 .net "out0", 0 0, L_0x2a528f0; 1 drivers
+v0x25bdf60_0 .net "out1", 0 0, L_0x2a529e0; 1 drivers
+v0x25bdc20_0 .net "outfinal", 0 0, L_0x2a52ad0; 1 drivers
+S_0x25ae210 .scope generate, "muxbits[27]" "muxbits[27]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x259c818 .param/l "i" 3 397, +C4<011011>;
+L_0x2a55550/d .functor OR 1, L_0x2a55690, L_0x2a55730, C4<0>, C4<0>;
+L_0x2a55550 .delay (20000,20000,20000) L_0x2a55550/d;
+v0x25bffb0_0 .net *"_s15", 0 0, L_0x2a55690; 1 drivers
+v0x25c0070_0 .net *"_s16", 0 0, L_0x2a55730; 1 drivers
+S_0x25b8600 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25ae210;
+ .timescale -9 -12;
+L_0x2a532a0/d .functor NOT 1, L_0x2a54c50, C4<0>, C4<0>, C4<0>;
+L_0x2a532a0 .delay (10000,10000,10000) L_0x2a532a0/d;
+L_0x2a53390/d .functor NOT 1, L_0x2a536e0, C4<0>, C4<0>, C4<0>;
+L_0x2a53390 .delay (10000,10000,10000) L_0x2a53390/d;
+L_0x2a53430/d .functor NAND 1, L_0x2a532a0, L_0x2a53390, L_0x2a53810, C4<1>;
+L_0x2a53430 .delay (10000,10000,10000) L_0x2a53430/d;
+L_0x2a53570/d .functor NAND 1, L_0x2a54c50, L_0x2a53390, L_0x2a538b0, C4<1>;
+L_0x2a53570 .delay (10000,10000,10000) L_0x2a53570/d;
+L_0x2a54800/d .functor NAND 1, L_0x2a532a0, L_0x2a536e0, L_0x2a53950, C4<1>;
+L_0x2a54800 .delay (10000,10000,10000) L_0x2a54800/d;
+L_0x2a548f0/d .functor NAND 1, L_0x2a54c50, L_0x2a536e0, L_0x2a53a40, C4<1>;
+L_0x2a548f0 .delay (10000,10000,10000) L_0x2a548f0/d;
+L_0x2a549d0/d .functor NAND 1, L_0x2a53430, L_0x2a53570, L_0x2a54800, L_0x2a548f0;
+L_0x2a549d0 .delay (10000,10000,10000) L_0x2a549d0/d;
+v0x25b9f90_0 .net "S0", 0 0, L_0x2a54c50; 1 drivers
+v0x25b8350_0 .net "S1", 0 0, L_0x2a536e0; 1 drivers
+v0x25b83f0_0 .net "in0", 0 0, L_0x2a53810; 1 drivers
+v0x25bb910_0 .net "in1", 0 0, L_0x2a538b0; 1 drivers
+v0x25bb9b0_0 .net "in2", 0 0, L_0x2a53950; 1 drivers
+v0x25b80a0_0 .net "in3", 0 0, L_0x2a53a40; 1 drivers
+v0x25b8140_0 .net "nS0", 0 0, L_0x2a532a0; 1 drivers
+v0x25b7e00_0 .net "nS1", 0 0, L_0x2a53390; 1 drivers
+v0x25b7ea0_0 .net "out", 0 0, L_0x2a549d0; 1 drivers
+v0x25c0510_0 .net "out0", 0 0, L_0x2a53430; 1 drivers
+v0x25c05b0_0 .net "out1", 0 0, L_0x2a53570; 1 drivers
+v0x25c0260_0 .net "out2", 0 0, L_0x2a54800; 1 drivers
+v0x25c0300_0 .net "out3", 0 0, L_0x2a548f0; 1 drivers
+S_0x25b27e0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25ae210;
+ .timescale -9 -12;
+L_0x2a53b30/d .functor NOT 1, L_0x2a54340, C4<0>, C4<0>, C4<0>;
+L_0x2a53b30 .delay (10000,10000,10000) L_0x2a53b30/d;
+L_0x2a53c20/d .functor NOT 1, L_0x2a54470, C4<0>, C4<0>, C4<0>;
+L_0x2a53c20 .delay (10000,10000,10000) L_0x2a53c20/d;
+L_0x2a53cc0/d .functor NAND 1, L_0x2a53b30, L_0x2a53c20, L_0x2a545a0, C4<1>;
+L_0x2a53cc0 .delay (10000,10000,10000) L_0x2a53cc0/d;
+L_0x2a53e00/d .functor NAND 1, L_0x2a54340, L_0x2a53c20, L_0x2a54640, C4<1>;
+L_0x2a53e00 .delay (10000,10000,10000) L_0x2a53e00/d;
+L_0x2a53ef0/d .functor NAND 1, L_0x2a53b30, L_0x2a54470, L_0x2a546e0, C4<1>;
+L_0x2a53ef0 .delay (10000,10000,10000) L_0x2a53ef0/d;
+L_0x2a53fe0/d .functor NAND 1, L_0x2a54340, L_0x2a54470, L_0x2a55f00, C4<1>;
+L_0x2a53fe0 .delay (10000,10000,10000) L_0x2a53fe0/d;
+L_0x2a540c0/d .functor NAND 1, L_0x2a53cc0, L_0x2a53e00, L_0x2a53ef0, L_0x2a53fe0;
+L_0x2a540c0 .delay (10000,10000,10000) L_0x2a540c0/d;
+v0x25b4170_0 .net "S0", 0 0, L_0x2a54340; 1 drivers
+v0x25b2530_0 .net "S1", 0 0, L_0x2a54470; 1 drivers
+v0x25b25d0_0 .net "in0", 0 0, L_0x2a545a0; 1 drivers
+v0x25b5af0_0 .net "in1", 0 0, L_0x2a54640; 1 drivers
+v0x25b5b90_0 .net "in2", 0 0, L_0x2a546e0; 1 drivers
+v0x25b2280_0 .net "in3", 0 0, L_0x2a55f00; 1 drivers
+v0x25ba6f0_0 .net "nS0", 0 0, L_0x2a53b30; 1 drivers
+v0x25ba790_0 .net "nS1", 0 0, L_0x2a53c20; 1 drivers
+v0x25ba440_0 .net "out", 0 0, L_0x2a540c0; 1 drivers
+v0x25ba4e0_0 .net "out0", 0 0, L_0x2a53cc0; 1 drivers
+v0x25ba190_0 .net "out1", 0 0, L_0x2a53e00; 1 drivers
+v0x25ba230_0 .net "out2", 0 0, L_0x2a53ef0; 1 drivers
+v0x25b9ef0_0 .net "out3", 0 0, L_0x2a53fe0; 1 drivers
+S_0x25ac120 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25ae210;
+ .timescale -9 -12;
+L_0x2a54d80/d .functor NOT 1, L_0x2a55230, C4<0>, C4<0>, C4<0>;
+L_0x2a54d80 .delay (10000,10000,10000) L_0x2a54d80/d;
+L_0x2a54e70/d .functor AND 1, L_0x2a552d0, L_0x2a54d80, C4<1>, C4<1>;
+L_0x2a54e70 .delay (20000,20000,20000) L_0x2a54e70/d;
+L_0x2a54f60/d .functor AND 1, L_0x2a553c0, L_0x2a55230, C4<1>, C4<1>;
+L_0x2a54f60 .delay (20000,20000,20000) L_0x2a54f60/d;
+L_0x2a55050/d .functor OR 1, L_0x2a54e70, L_0x2a54f60, C4<0>, C4<0>;
+L_0x2a55050 .delay (20000,20000,20000) L_0x2a55050/d;
+v0x25b48d0_0 .net "S", 0 0, L_0x2a55230; 1 drivers
+v0x25b4990_0 .net "in0", 0 0, L_0x2a552d0; 1 drivers
+v0x25b4620_0 .net "in1", 0 0, L_0x2a553c0; 1 drivers
+v0x25b46c0_0 .net "nS", 0 0, L_0x2a54d80; 1 drivers
+v0x25b4370_0 .net "out0", 0 0, L_0x2a54e70; 1 drivers
+v0x25b4410_0 .net "out1", 0 0, L_0x2a54f60; 1 drivers
+v0x25b40d0_0 .net "outfinal", 0 0, L_0x2a55050; 1 drivers
+S_0x2596970 .scope generate, "muxbits[28]" "muxbits[28]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x2723898 .param/l "i" 3 397, +C4<011100>;
+L_0x2a57b60/d .functor OR 1, L_0x2a57ca0, L_0x2a57d40, C4<0>, C4<0>;
+L_0x2a57b60 .delay (20000,20000,20000) L_0x2a57b60/d;
+v0x25a62c0_0 .net *"_s15", 0 0, L_0x2a57ca0; 1 drivers
+v0x25a6380_0 .net *"_s16", 0 0, L_0x2a57d40; 1 drivers
+S_0x259a6a0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2596970;
+ .timescale -9 -12;
+L_0x2a55820/d .functor NOT 1, L_0x2a55ff0, C4<0>, C4<0>, C4<0>;
+L_0x2a55820 .delay (10000,10000,10000) L_0x2a55820/d;
+L_0x2a55910/d .functor NOT 1, L_0x2a56120, C4<0>, C4<0>, C4<0>;
+L_0x2a55910 .delay (10000,10000,10000) L_0x2a55910/d;
+L_0x2a559b0/d .functor NAND 1, L_0x2a55820, L_0x2a55910, L_0x2a56250, C4<1>;
+L_0x2a559b0 .delay (10000,10000,10000) L_0x2a559b0/d;
+L_0x2a55af0/d .functor NAND 1, L_0x2a55ff0, L_0x2a55910, L_0x2a562f0, C4<1>;
+L_0x2a55af0 .delay (10000,10000,10000) L_0x2a55af0/d;
+L_0x2a55be0/d .functor NAND 1, L_0x2a55820, L_0x2a56120, L_0x2a56390, C4<1>;
+L_0x2a55be0 .delay (10000,10000,10000) L_0x2a55be0/d;
+L_0x2a55cd0/d .functor NAND 1, L_0x2a55ff0, L_0x2a56120, L_0x2a56480, C4<1>;
+L_0x2a55cd0 .delay (10000,10000,10000) L_0x2a55cd0/d;
+L_0x2a55db0/d .functor NAND 1, L_0x2a559b0, L_0x2a55af0, L_0x2a55be0, L_0x2a55cd0;
+L_0x2a55db0 .delay (10000,10000,10000) L_0x2a55db0/d;
+v0x259a9e0_0 .net "S0", 0 0, L_0x2a55ff0; 1 drivers
+v0x25a2550_0 .net "S1", 0 0, L_0x2a56120; 1 drivers
+v0x25a25f0_0 .net "in0", 0 0, L_0x2a56250; 1 drivers
+v0x25a0cc0_0 .net "in1", 0 0, L_0x2a562f0; 1 drivers
+v0x25a0d60_0 .net "in2", 0 0, L_0x2a56390; 1 drivers
+v0x25a0a10_0 .net "in3", 0 0, L_0x2a56480; 1 drivers
+v0x25a0ab0_0 .net "nS0", 0 0, L_0x2a55820; 1 drivers
+v0x25a0760_0 .net "nS1", 0 0, L_0x2a55910; 1 drivers
+v0x25a0800_0 .net "out", 0 0, L_0x2a55db0; 1 drivers
+v0x25a04c0_0 .net "out0", 0 0, L_0x2a559b0; 1 drivers
+v0x25a0560_0 .net "out1", 0 0, L_0x2a55af0; 1 drivers
+v0x25a83b0_0 .net "out2", 0 0, L_0x2a55be0; 1 drivers
+v0x25a8450_0 .net "out3", 0 0, L_0x2a55cd0; 1 drivers
+S_0x259cf90 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2596970;
+ .timescale -9 -12;
+L_0x2a56570/d .functor NOT 1, L_0x2a56d80, C4<0>, C4<0>, C4<0>;
+L_0x2a56570 .delay (10000,10000,10000) L_0x2a56570/d;
+L_0x2a56660/d .functor NOT 1, L_0x2a56eb0, C4<0>, C4<0>, C4<0>;
+L_0x2a56660 .delay (10000,10000,10000) L_0x2a56660/d;
+L_0x2a56700/d .functor NAND 1, L_0x2a56570, L_0x2a56660, L_0x2a56fe0, C4<1>;
+L_0x2a56700 .delay (10000,10000,10000) L_0x2a56700/d;
+L_0x2a56840/d .functor NAND 1, L_0x2a56d80, L_0x2a56660, L_0x2a57080, C4<1>;
+L_0x2a56840 .delay (10000,10000,10000) L_0x2a56840/d;
+L_0x2a56930/d .functor NAND 1, L_0x2a56570, L_0x2a56eb0, L_0x2a58500, C4<1>;
+L_0x2a56930 .delay (10000,10000,10000) L_0x2a56930/d;
+L_0x2a56a20/d .functor NAND 1, L_0x2a56d80, L_0x2a56eb0, L_0x2a572e0, C4<1>;
+L_0x2a56a20 .delay (10000,10000,10000) L_0x2a56a20/d;
+L_0x2a56b00/d .functor NAND 1, L_0x2a56700, L_0x2a56840, L_0x2a56930, L_0x2a56a20;
+L_0x2a56b00 .delay (10000,10000,10000) L_0x2a56b00/d;
+v0x2594920_0 .net "S0", 0 0, L_0x2a56d80; 1 drivers
+v0x259cce0_0 .net "S1", 0 0, L_0x2a56eb0; 1 drivers
+v0x259cd80_0 .net "in0", 0 0, L_0x2a56fe0; 1 drivers
+v0x259ca30_0 .net "in1", 0 0, L_0x2a57080; 1 drivers
+v0x259cad0_0 .net "in2", 0 0, L_0x2a58500; 1 drivers
+v0x259c790_0 .net "in3", 0 0, L_0x2a572e0; 1 drivers
+v0x259aea0_0 .net "nS0", 0 0, L_0x2a56570; 1 drivers
+v0x259af40_0 .net "nS1", 0 0, L_0x2a56660; 1 drivers
+v0x259abf0_0 .net "out", 0 0, L_0x2a56b00; 1 drivers
+v0x259ac90_0 .net "out0", 0 0, L_0x2a56700; 1 drivers
+v0x259e1b0_0 .net "out1", 0 0, L_0x2a56840; 1 drivers
+v0x259e250_0 .net "out2", 0 0, L_0x2a56930; 1 drivers
+v0x259a940_0 .net "out3", 0 0, L_0x2a56a20; 1 drivers
+S_0x2595080 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2596970;
+ .timescale -9 -12;
+L_0x2a573d0/d .functor NOT 1, L_0x2a57840, C4<0>, C4<0>, C4<0>;
+L_0x2a573d0 .delay (10000,10000,10000) L_0x2a573d0/d;
+L_0x2a57480/d .functor AND 1, L_0x2a578e0, L_0x2a573d0, C4<1>, C4<1>;
+L_0x2a57480 .delay (20000,20000,20000) L_0x2a57480/d;
+L_0x2a57570/d .functor AND 1, L_0x2a579d0, L_0x2a57840, C4<1>, C4<1>;
+L_0x2a57570 .delay (20000,20000,20000) L_0x2a57570/d;
+L_0x2a57660/d .functor OR 1, L_0x2a57480, L_0x2a57570, C4<0>, C4<0>;
+L_0x2a57660 .delay (20000,20000,20000) L_0x2a57660/d;
+v0x2594dd0_0 .net "S", 0 0, L_0x2a57840; 1 drivers
+v0x2594e90_0 .net "in0", 0 0, L_0x2a578e0; 1 drivers
+v0x2598390_0 .net "in1", 0 0, L_0x2a579d0; 1 drivers
+v0x2598430_0 .net "nS", 0 0, L_0x2a573d0; 1 drivers
+v0x2594b20_0 .net "out0", 0 0, L_0x2a57480; 1 drivers
+v0x2594bc0_0 .net "out1", 0 0, L_0x2a57570; 1 drivers
+v0x2594880_0 .net "outfinal", 0 0, L_0x2a57660; 1 drivers
+S_0x2646f50 .scope generate, "muxbits[29]" "muxbits[29]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x264d3a8 .param/l "i" 3 397, +C4<011101>;
+L_0x2a5a530/d .functor OR 1, L_0x2a5a670, L_0x2a5a710, C4<0>, C4<0>;
+L_0x2a5a530 .delay (20000,20000,20000) L_0x2a5a530/d;
+v0x2596c10_0 .net *"_s15", 0 0, L_0x2a5a670; 1 drivers
+v0x2596cd0_0 .net *"_s16", 0 0, L_0x2a5a710; 1 drivers
+S_0x27150d0 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x2646f50;
+ .timescale -9 -12;
+L_0x2a57e30/d .functor NOT 1, L_0x2a59950, C4<0>, C4<0>, C4<0>;
+L_0x2a57e30 .delay (10000,10000,10000) L_0x2a57e30/d;
+L_0x2a57f20/d .functor NOT 1, L_0x2a585a0, C4<0>, C4<0>, C4<0>;
+L_0x2a57f20 .delay (10000,10000,10000) L_0x2a57f20/d;
+L_0x2a57fc0/d .functor NAND 1, L_0x2a57e30, L_0x2a57f20, L_0x2a586d0, C4<1>;
+L_0x2a57fc0 .delay (10000,10000,10000) L_0x2a57fc0/d;
+L_0x2a58100/d .functor NAND 1, L_0x2a59950, L_0x2a57f20, L_0x2a58770, C4<1>;
+L_0x2a58100 .delay (10000,10000,10000) L_0x2a58100/d;
+L_0x2a581f0/d .functor NAND 1, L_0x2a57e30, L_0x2a585a0, L_0x2a58810, C4<1>;
+L_0x2a581f0 .delay (10000,10000,10000) L_0x2a581f0/d;
+L_0x2a582e0/d .functor NAND 1, L_0x2a59950, L_0x2a585a0, L_0x2a58900, C4<1>;
+L_0x2a582e0 .delay (10000,10000,10000) L_0x2a582e0/d;
+L_0x2a583c0/d .functor NAND 1, L_0x2a57fc0, L_0x2a58100, L_0x2a581f0, L_0x2a582e0;
+L_0x2a583c0 .delay (10000,10000,10000) L_0x2a583c0/d;
+v0x2717fb0_0 .net "S0", 0 0, L_0x2a59950; 1 drivers
+v0x26e2350_0 .net "S1", 0 0, L_0x2a585a0; 1 drivers
+v0x26e23f0_0 .net "in0", 0 0, L_0x2a586d0; 1 drivers
+v0x273d6e0_0 .net "in1", 0 0, L_0x2a58770; 1 drivers
+v0x273d780_0 .net "in2", 0 0, L_0x2a58810; 1 drivers
+v0x2590a50_0 .net "in3", 0 0, L_0x2a58900; 1 drivers
+v0x2590af0_0 .net "nS0", 0 0, L_0x2a57e30; 1 drivers
+v0x2592540_0 .net "nS1", 0 0, L_0x2a57f20; 1 drivers
+v0x25925e0_0 .net "out", 0 0, L_0x2a583c0; 1 drivers
+v0x2597170_0 .net "out0", 0 0, L_0x2a57fc0; 1 drivers
+v0x2597210_0 .net "out1", 0 0, L_0x2a58100; 1 drivers
+v0x2596ec0_0 .net "out2", 0 0, L_0x2a581f0; 1 drivers
+v0x2596f60_0 .net "out3", 0 0, L_0x2a582e0; 1 drivers
+S_0x273a6d0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x2646f50;
+ .timescale -9 -12;
+L_0x29cdc40/d .functor NOT 1, L_0x2a59600, C4<0>, C4<0>, C4<0>;
+L_0x29cdc40 .delay (10000,10000,10000) L_0x29cdc40/d;
+L_0x29cdd30/d .functor NOT 1, L_0x2a59730, C4<0>, C4<0>, C4<0>;
+L_0x29cdd30 .delay (10000,10000,10000) L_0x29cdd30/d;
+L_0x29cddd0/d .functor NAND 1, L_0x29cdc40, L_0x29cdd30, L_0x2a59a80, C4<1>;
+L_0x29cddd0 .delay (10000,10000,10000) L_0x29cddd0/d;
+L_0x29cdf10/d .functor NAND 1, L_0x2a59600, L_0x29cdd30, L_0x2a59b20, C4<1>;
+L_0x29cdf10 .delay (10000,10000,10000) L_0x29cdf10/d;
+L_0x2a59200/d .functor NAND 1, L_0x29cdc40, L_0x2a59730, L_0x2a59bc0, C4<1>;
+L_0x2a59200 .delay (10000,10000,10000) L_0x2a59200/d;
+L_0x2a592a0/d .functor NAND 1, L_0x2a59600, L_0x2a59730, L_0x2a59cb0, C4<1>;
+L_0x2a592a0 .delay (10000,10000,10000) L_0x2a592a0/d;
+L_0x2a59380/d .functor NAND 1, L_0x29cddd0, L_0x29cdf10, L_0x2a59200, L_0x2a592a0;
+L_0x2a59380 .delay (10000,10000,10000) L_0x2a59380/d;
+v0x26f57f0_0 .net "S0", 0 0, L_0x2a59600; 1 drivers
+v0x2737890_0 .net "S1", 0 0, L_0x2a59730; 1 drivers
+v0x2737930_0 .net "in0", 0 0, L_0x2a59a80; 1 drivers
+v0x2734a50_0 .net "in1", 0 0, L_0x2a59b20; 1 drivers
+v0x2734af0_0 .net "in2", 0 0, L_0x2a59bc0; 1 drivers
+v0x2723810_0 .net "in3", 0 0, L_0x2a59cb0; 1 drivers
+v0x27209d0_0 .net "nS0", 0 0, L_0x29cdc40; 1 drivers
+v0x2720a70_0 .net "nS1", 0 0, L_0x29cdd30; 1 drivers
+v0x271db90_0 .net "out", 0 0, L_0x2a59380; 1 drivers
+v0x271dc30_0 .net "out0", 0 0, L_0x29cddd0; 1 drivers
+v0x271ad50_0 .net "out1", 0 0, L_0x29cdf10; 1 drivers
+v0x271adf0_0 .net "out2", 0 0, L_0x2a59200; 1 drivers
+v0x2717f10_0 .net "out3", 0 0, L_0x2a592a0; 1 drivers
+S_0x2701050 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x2646f50;
+ .timescale -9 -12;
+L_0x2a59da0/d .functor NOT 1, L_0x2a5a210, C4<0>, C4<0>, C4<0>;
+L_0x2a59da0 .delay (10000,10000,10000) L_0x2a59da0/d;
+L_0x2a59e50/d .functor AND 1, L_0x2a5a2b0, L_0x2a59da0, C4<1>, C4<1>;
+L_0x2a59e50 .delay (20000,20000,20000) L_0x2a59e50/d;
+L_0x2a59f40/d .functor AND 1, L_0x2a5a3a0, L_0x2a5a210, C4<1>, C4<1>;
+L_0x2a59f40 .delay (20000,20000,20000) L_0x2a59f40/d;
+L_0x2a5a030/d .functor OR 1, L_0x2a59e50, L_0x2a59f40, C4<0>, C4<0>;
+L_0x2a5a030 .delay (20000,20000,20000) L_0x2a5a030/d;
+v0x26fe210_0 .net "S", 0 0, L_0x2a5a210; 1 drivers
+v0x26fe2d0_0 .net "in0", 0 0, L_0x2a5a2b0; 1 drivers
+v0x26fb3d0_0 .net "in1", 0 0, L_0x2a5a3a0; 1 drivers
+v0x26fb470_0 .net "nS", 0 0, L_0x2a59da0; 1 drivers
+v0x26f8590_0 .net "out0", 0 0, L_0x2a59e50; 1 drivers
+v0x26f8630_0 .net "out1", 0 0, L_0x2a59f40; 1 drivers
+v0x26f5750_0 .net "outfinal", 0 0, L_0x2a5a030; 1 drivers
+S_0x26bd790 .scope generate, "muxbits[30]" "muxbits[30]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x25eea88 .param/l "i" 3 397, +C4<011110>;
+L_0x2a5c6f0/d .functor OR 1, L_0x2a5c830, L_0x2a5c8d0, C4<0>, C4<0>;
+L_0x2a5c6f0 .delay (20000,20000,20000) L_0x2a5c6f0/d;
+v0x2665160_0 .net *"_s15", 0 0, L_0x2a5c830; 1 drivers
+v0x2665220_0 .net *"_s16", 0 0, L_0x2a5c8d0; 1 drivers
+S_0x2686800 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x26bd790;
+ .timescale -9 -12;
+L_0x2a5a800/d .functor NOT 1, L_0x2a5adc0, C4<0>, C4<0>, C4<0>;
+L_0x2a5a800 .delay (10000,10000,10000) L_0x2a5a800/d;
+L_0x2a5a8f0/d .functor NOT 1, L_0x2a5aef0, C4<0>, C4<0>, C4<0>;
+L_0x2a5a8f0 .delay (10000,10000,10000) L_0x2a5a8f0/d;
+L_0x2a5a990/d .functor NAND 1, L_0x2a5a800, L_0x2a5a8f0, L_0x2a5b020, C4<1>;
+L_0x2a5a990 .delay (10000,10000,10000) L_0x2a5a990/d;
+L_0x2a5aad0/d .functor NAND 1, L_0x2a5adc0, L_0x2a5a8f0, L_0x2a5b0c0, C4<1>;
+L_0x2a5aad0 .delay (10000,10000,10000) L_0x2a5aad0/d;
+L_0x2a5abc0/d .functor NAND 1, L_0x2a5a800, L_0x2a5aef0, L_0x2a5b160, C4<1>;
+L_0x2a5abc0 .delay (10000,10000,10000) L_0x2a5abc0/d;
+L_0x2a5acb0/d .functor NAND 1, L_0x2a5adc0, L_0x2a5aef0, L_0x2a5b250, C4<1>;
+L_0x2a5acb0 .delay (10000,10000,10000) L_0x2a5acb0/d;
+L_0x2a5c150/d .functor NAND 1, L_0x2a5a990, L_0x2a5aad0, L_0x2a5abc0, L_0x2a5acb0;
+L_0x2a5c150 .delay (10000,10000,10000) L_0x2a5c150/d;
+v0x268b510_0 .net "S0", 0 0, L_0x2a5adc0; 1 drivers
+v0x267f6a0_0 .net "S1", 0 0, L_0x2a5aef0; 1 drivers
+v0x267f740_0 .net "in0", 0 0, L_0x2a5b020; 1 drivers
+v0x267a9f0_0 .net "in1", 0 0, L_0x2a5b0c0; 1 drivers
+v0x267aa90_0 .net "in2", 0 0, L_0x2a5b160; 1 drivers
+v0x2675d40_0 .net "in3", 0 0, L_0x2a5b250; 1 drivers
+v0x2675de0_0 .net "nS0", 0 0, L_0x2a5a800; 1 drivers
+v0x266ea40_0 .net "nS1", 0 0, L_0x2a5a8f0; 1 drivers
+v0x266eae0_0 .net "out", 0 0, L_0x2a5c150; 1 drivers
+v0x2669dd0_0 .net "out0", 0 0, L_0x2a5a990; 1 drivers
+v0x2669e70_0 .net "out1", 0 0, L_0x2a5aad0; 1 drivers
+v0x2648670_0 .net "out2", 0 0, L_0x2a5abc0; 1 drivers
+v0x2648710_0 .net "out3", 0 0, L_0x2a5acb0; 1 drivers
+S_0x26a3240 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x26bd790;
+ .timescale -9 -12;
+L_0x2a5b340/d .functor NOT 1, L_0x2a5bb50, C4<0>, C4<0>, C4<0>;
+L_0x2a5b340 .delay (10000,10000,10000) L_0x2a5b340/d;
+L_0x2a5b430/d .functor NOT 1, L_0x2a5bc80, C4<0>, C4<0>, C4<0>;
+L_0x2a5b430 .delay (10000,10000,10000) L_0x2a5b430/d;
+L_0x2a5b4d0/d .functor NAND 1, L_0x2a5b340, L_0x2a5b430, L_0x2a5bdb0, C4<1>;
+L_0x2a5b4d0 .delay (10000,10000,10000) L_0x2a5b4d0/d;
+L_0x2a5b610/d .functor NAND 1, L_0x2a5bb50, L_0x2a5b430, L_0x2a5be50, C4<1>;
+L_0x2a5b610 .delay (10000,10000,10000) L_0x2a5b610/d;
+L_0x2a5b700/d .functor NAND 1, L_0x2a5b340, L_0x2a5bc80, L_0x2a5bef0, C4<1>;
+L_0x2a5b700 .delay (10000,10000,10000) L_0x2a5b700/d;
+L_0x2a5b7f0/d .functor NAND 1, L_0x2a5bb50, L_0x2a5bc80, L_0x2a5bfe0, C4<1>;
+L_0x2a5b7f0 .delay (10000,10000,10000) L_0x2a5b7f0/d;
+L_0x2a5b8d0/d .functor NAND 1, L_0x2a5b4d0, L_0x2a5b610, L_0x2a5b700, L_0x2a5b7f0;
+L_0x2a5b8d0 .delay (10000,10000,10000) L_0x2a5b8d0/d;
+v0x26a7f50_0 .net "S0", 0 0, L_0x2a5bb50; 1 drivers
+v0x26a0d40_0 .net "S1", 0 0, L_0x2a5bc80; 1 drivers
+v0x26a0de0_0 .net "in0", 0 0, L_0x2a5bdb0; 1 drivers
+v0x269c090_0 .net "in1", 0 0, L_0x2a5be50; 1 drivers
+v0x269c130_0 .net "in2", 0 0, L_0x2a5bef0; 1 drivers
+v0x264d320_0 .net "in3", 0 0, L_0x2a5bfe0; 1 drivers
+v0x26973e0_0 .net "nS0", 0 0, L_0x2a5b340; 1 drivers
+v0x2697480_0 .net "nS1", 0 0, L_0x2a5b430; 1 drivers
+v0x2692750_0 .net "out", 0 0, L_0x2a5b8d0; 1 drivers
+v0x26927f0_0 .net "out0", 0 0, L_0x2a5b4d0; 1 drivers
+v0x26900e0_0 .net "out1", 0 0, L_0x2a5b610; 1 drivers
+v0x2690180_0 .net "out2", 0 0, L_0x2a5b700; 1 drivers
+v0x268b470_0 .net "out3", 0 0, L_0x2a5b7f0; 1 drivers
+S_0x26b8ae0 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x26bd790;
+ .timescale -9 -12;
+L_0x2a5d750/d .functor NOT 1, L_0x2a5c3d0, C4<0>, C4<0>, C4<0>;
+L_0x2a5d750 .delay (10000,10000,10000) L_0x2a5d750/d;
+L_0x2a5d840/d .functor AND 1, L_0x2a5c470, L_0x2a5d750, C4<1>, C4<1>;
+L_0x2a5d840 .delay (20000,20000,20000) L_0x2a5d840/d;
+L_0x2a5d930/d .functor AND 1, L_0x2a5c560, L_0x2a5c3d0, C4<1>, C4<1>;
+L_0x2a5d930 .delay (20000,20000,20000) L_0x2a5d930/d;
+L_0x2a5da20/d .functor OR 1, L_0x2a5d840, L_0x2a5d930, C4<0>, C4<0>;
+L_0x2a5da20 .delay (20000,20000,20000) L_0x2a5da20/d;
+v0x26c49c0_0 .net "S", 0 0, L_0x2a5c3d0; 1 drivers
+v0x26b3e30_0 .net "in0", 0 0, L_0x2a5c470; 1 drivers
+v0x26b3ed0_0 .net "in1", 0 0, L_0x2a5c560; 1 drivers
+v0x26b1790_0 .net "nS", 0 0, L_0x2a5d750; 1 drivers
+v0x26b1830_0 .net "out0", 0 0, L_0x2a5d840; 1 drivers
+v0x26acb20_0 .net "out1", 0 0, L_0x2a5d930; 1 drivers
+v0x26a7eb0_0 .net "outfinal", 0 0, L_0x2a5da20; 1 drivers
+S_0x25e2cb0 .scope generate, "muxbits[31]" "muxbits[31]" 3 397, 3 397, S_0x25e6a40;
+ .timescale -9 -12;
+P_0x24174c8 .param/l "i" 3 397, +C4<011111>;
+L_0x2a5e180/d .functor OR 1, L_0x2a5e280, L_0x2a5e320, C4<0>, C4<0>;
+L_0x2a5e180 .delay (20000,20000,20000) L_0x2a5e180/d;
+v0x26c9630_0 .net *"_s15", 0 0, L_0x2a5e280; 1 drivers
+v0x26c4920_0 .net *"_s16", 0 0, L_0x2a5e320; 1 drivers
+S_0x2662b10 .scope module, "ZeroMux" "FourInMux" 3 399, 3 125, S_0x25e2cb0;
+ .timescale -9 -12;
+L_0x2a5c9c0/d .functor NOT 1, L_0x2a5d1d0, C4<0>, C4<0>, C4<0>;
+L_0x2a5c9c0 .delay (10000,10000,10000) L_0x2a5c9c0/d;
+L_0x2a5cab0/d .functor NOT 1, L_0x2a5d300, C4<0>, C4<0>, C4<0>;
+L_0x2a5cab0 .delay (10000,10000,10000) L_0x2a5cab0/d;
+L_0x2a5cb50/d .functor NAND 1, L_0x2a5c9c0, L_0x2a5cab0, L_0x2a5d430, C4<1>;
+L_0x2a5cb50 .delay (10000,10000,10000) L_0x2a5cb50/d;
+L_0x2a5cc90/d .functor NAND 1, L_0x2a5d1d0, L_0x2a5cab0, L_0x2a5d4d0, C4<1>;
+L_0x2a5cc90 .delay (10000,10000,10000) L_0x2a5cc90/d;
+L_0x2a5cd80/d .functor NAND 1, L_0x2a5c9c0, L_0x2a5d300, L_0x2a5d570, C4<1>;
+L_0x2a5cd80 .delay (10000,10000,10000) L_0x2a5cd80/d;
+L_0x2a5ce70/d .functor NAND 1, L_0x2a5d1d0, L_0x2a5d300, L_0x2a5d660, C4<1>;
+L_0x2a5ce70 .delay (10000,10000,10000) L_0x2a5ce70/d;
+L_0x2a5cf50/d .functor NAND 1, L_0x2a5cb50, L_0x2a5cc90, L_0x2a5cd80, L_0x2a5ce70;
+L_0x2a5cf50 .delay (10000,10000,10000) L_0x2a5cf50/d;
+v0x265dfa0_0 .net "S0", 0 0, L_0x2a5d1d0; 1 drivers
+v0x265e060_0 .net "S1", 0 0, L_0x2a5d300; 1 drivers
+v0x26592f0_0 .net "in0", 0 0, L_0x2a5d430; 1 drivers
+v0x2659390_0 .net "in1", 0 0, L_0x2a5d4d0; 1 drivers
+v0x26dadc0_0 .net "in2", 0 0, L_0x2a5d570; 1 drivers
+v0x26dae60_0 .net "in3", 0 0, L_0x2a5d660; 1 drivers
+v0x26d5520_0 .net "nS0", 0 0, L_0x2a5c9c0; 1 drivers
+v0x26d55c0_0 .net "nS1", 0 0, L_0x2a5cab0; 1 drivers
+v0x2654640_0 .net "out", 0 0, L_0x2a5cf50; 1 drivers
+v0x26546e0_0 .net "out0", 0 0, L_0x2a5cb50; 1 drivers
+v0x26ce200_0 .net "out1", 0 0, L_0x2a5cc90; 1 drivers
+v0x26ce2a0_0 .net "out2", 0 0, L_0x2a5cd80; 1 drivers
+v0x26c9590_0 .net "out3", 0 0, L_0x2a5ce70; 1 drivers
+S_0x25c34c0 .scope module, "OneMux" "FourInMux" 3 400, 3 125, S_0x25e2cb0;
+ .timescale -9 -12;
+L_0x2a5eff0/d .functor NOT 1, L_0x2a5dc00, C4<0>, C4<0>, C4<0>;
+L_0x2a5eff0 .delay (10000,10000,10000) L_0x2a5eff0/d;
+L_0x2a5f0e0/d .functor NOT 1, L_0x2a5dd30, C4<0>, C4<0>, C4<0>;
+L_0x2a5f0e0 .delay (10000,10000,10000) L_0x2a5f0e0/d;
+L_0x2a5f180/d .functor NAND 1, L_0x2a5eff0, L_0x2a5f0e0, L_0x2a5de60, C4<1>;
+L_0x2a5f180 .delay (10000,10000,10000) L_0x2a5f180/d;
+L_0x2a5f2c0/d .functor NAND 1, L_0x2a5dc00, L_0x2a5f0e0, L_0x2a5df00, C4<1>;
+L_0x2a5f2c0 .delay (10000,10000,10000) L_0x2a5f2c0/d;
+L_0x2a5f3b0/d .functor NAND 1, L_0x2a5eff0, L_0x2a5dd30, L_0x2a5dfa0, C4<1>;
+L_0x2a5f3b0 .delay (10000,10000,10000) L_0x2a5f3b0/d;
+L_0x2a5f4a0/d .functor NAND 1, L_0x2a5dc00, L_0x2a5dd30, L_0x2a5e090, C4<1>;
+L_0x2a5f4a0 .delay (10000,10000,10000) L_0x2a5f4a0/d;
+L_0x2a5f580/d .functor NAND 1, L_0x2a5f180, L_0x2a5f2c0, L_0x2a5f3b0, L_0x2a5f4a0;
+L_0x2a5f580 .delay (10000,10000,10000) L_0x2a5f580/d;
+v0x25c5630_0 .net "S0", 0 0, L_0x2a5dc00; 1 drivers
+v0x25b1a40_0 .net "S1", 0 0, L_0x2a5dd30; 1 drivers
+v0x25b1ae0_0 .net "in0", 0 0, L_0x2a5de60; 1 drivers
+v0x25adcb0_0 .net "in1", 0 0, L_0x2a5df00; 1 drivers
+v0x25add50_0 .net "in2", 0 0, L_0x2a5dfa0; 1 drivers
+v0x25abbe0_0 .net "in3", 0 0, L_0x2a5e090; 1 drivers
+v0x25abc80_0 .net "nS0", 0 0, L_0x2a5eff0; 1 drivers
+v0x25a7e50_0 .net "nS1", 0 0, L_0x2a5f0e0; 1 drivers
+v0x25a7ef0_0 .net "out", 0 0, L_0x2a5f580; 1 drivers
+v0x25a5d80_0 .net "out0", 0 0, L_0x2a5f180; 1 drivers
+v0x25a5e20_0 .net "out1", 0 0, L_0x2a5f2c0; 1 drivers
+v0x258e2e0_0 .net "out2", 0 0, L_0x2a5f3b0; 1 drivers
+v0x258e380_0 .net "out3", 0 0, L_0x2a5f4a0; 1 drivers
+S_0x25d1250 .scope module, "TwoMux" "TwoInMux" 3 401, 3 109, S_0x25e2cb0;
+ .timescale -9 -12;
+L_0x2a2ade0/d .functor NOT 1, L_0x2a2b290, C4<0>, C4<0>, C4<0>;
+L_0x2a2ade0 .delay (10000,10000,10000) L_0x2a2ade0/d;
+L_0x2a2aed0/d .functor AND 1, L_0x2a2b330, L_0x2a2ade0, C4<1>, C4<1>;
+L_0x2a2aed0 .delay (20000,20000,20000) L_0x2a2aed0/d;
+L_0x2a2afc0/d .functor AND 1, L_0x2a2b420, L_0x2a2b290, C4<1>, C4<1>;
+L_0x2a2afc0 .delay (20000,20000,20000) L_0x2a2afc0/d;
+L_0x2a2b0b0/d .functor OR 1, L_0x2a2aed0, L_0x2a2afc0, C4<0>, C4<0>;
+L_0x2a2b0b0 .delay (20000,20000,20000) L_0x2a2b0b0/d;
+v0x25cf180_0 .net "S", 0 0, L_0x2a2b290; 1 drivers
+v0x25cf220_0 .net "in0", 0 0, L_0x2a2b330; 1 drivers
+v0x25cb3f0_0 .net "in1", 0 0, L_0x2a2b420; 1 drivers
+v0x25cb490_0 .net "nS", 0 0, L_0x2a2ade0; 1 drivers
+v0x25c9320_0 .net "out0", 0 0, L_0x2a2aed0; 1 drivers
+v0x25c93c0_0 .net "out1", 0 0, L_0x2a2afc0; 1 drivers
+v0x25c5590_0 .net "outfinal", 0 0, L_0x2a2b0b0; 1 drivers
+S_0x1f6b890 .scope module, "testALU" "ALU" 2 164, 3 8, S_0x22efd20;
+ .timescale -9 -12;
+P_0x1d35098 .param/l "size" 3 37, +C4<0100000>;
+L_0x2b3ff10/d .functor AND 1, L_0x2c14570, L_0x2c14610, C4<1>, C4<1>;
+L_0x2b3ff10 .delay (20000,20000,20000) L_0x2b3ff10/d;
+L_0x2c14700/d .functor NOT 1, L_0x2c14810, C4<0>, C4<0>, C4<0>;
+L_0x2c14700 .delay (10000,10000,10000) L_0x2c14700/d;
+L_0x2c148b0/d .functor AND 1, L_0x2c14700, L_0x2c14700, C4<1>, C4<1>;
+L_0x2c148b0 .delay (20000,20000,20000) L_0x2c148b0/d;
+RS_0x7f507e9e4aa8/0/0 .resolv tri, L_0x2baea80, L_0x2bb02e0, L_0x2bb16e0, L_0x2bb2c80;
+RS_0x7f507e9e4aa8/0/4 .resolv tri, L_0x2bb4260, L_0x2bb57b0, L_0x2bb6d10, L_0x2bb8250;
+RS_0x7f507e9e4aa8/0/8 .resolv tri, L_0x2bb98a0, L_0x2bbadf0, L_0x2bbc300, L_0x2bbd7d0;
+RS_0x7f507e9e4aa8/0/12 .resolv tri, L_0x2bbec90, L_0x2bc0160, L_0x2bc1620, L_0x2bc2ae0;
+RS_0x7f507e9e4aa8/0/16 .resolv tri, L_0x2bc40c0, L_0x2bc54d0, L_0x2bc6940, L_0x2bc7cd0;
+RS_0x7f507e9e4aa8/0/20 .resolv tri, L_0x2bc9050, L_0x2bca4a0, L_0x2bcb860, L_0x2bccd20;
+RS_0x7f507e9e4aa8/0/24 .resolv tri, L_0x2bce1f0, L_0x2bcf6b0, L_0x2bd0b90, L_0x2bd2040;
+RS_0x7f507e9e4aa8/0/28 .resolv tri, L_0x2bd3520, L_0x2bd4e20, L_0x2bd62e0, L_0x2bd77c0;
+RS_0x7f507e9e4aa8/1/0 .resolv tri, RS_0x7f507e9e4aa8/0/0, RS_0x7f507e9e4aa8/0/4, RS_0x7f507e9e4aa8/0/8, RS_0x7f507e9e4aa8/0/12;
+RS_0x7f507e9e4aa8/1/4 .resolv tri, RS_0x7f507e9e4aa8/0/16, RS_0x7f507e9e4aa8/0/20, RS_0x7f507e9e4aa8/0/24, RS_0x7f507e9e4aa8/0/28;
+RS_0x7f507e9e4aa8 .resolv tri, RS_0x7f507e9e4aa8/1/0, RS_0x7f507e9e4aa8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2415680_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9e4aa8; 32 drivers
+RS_0x7f507e9dde78/0/0 .resolv tri, L_0x2bd7eb0, L_0x2bd9ac0, L_0x2bda570, L_0x2bdafd0;
+RS_0x7f507e9dde78/0/4 .resolv tri, L_0x2bdba60, L_0x2bdc530, L_0x2bdd050, L_0x2bddab0;
+RS_0x7f507e9dde78/0/8 .resolv tri, L_0x2bde550, L_0x2bdefc0, L_0x2bdfa50, L_0x2be04c0;
+RS_0x7f507e9dde78/0/12 .resolv tri, L_0x2be0f60, L_0x2be19c0, L_0x2be2450, L_0x2be2ec0;
+RS_0x7f507e9dde78/0/16 .resolv tri, L_0x2be3960, L_0x2be43c0, L_0x2be4e60, L_0x2be58c0;
+RS_0x7f507e9dde78/0/20 .resolv tri, L_0x2be6250, L_0x2be6c00, L_0x2be7580, L_0x2be7f20;
+RS_0x7f507e9dde78/0/24 .resolv tri, L_0x2be8890, L_0x2be9210, L_0x2be9ba0, L_0x2bea5b0;
+RS_0x7f507e9dde78/0/28 .resolv tri, L_0x2beb050, L_0x2bebab0, L_0x2bec540, L_0x2becfb0;
+RS_0x7f507e9dde78/1/0 .resolv tri, RS_0x7f507e9dde78/0/0, RS_0x7f507e9dde78/0/4, RS_0x7f507e9dde78/0/8, RS_0x7f507e9dde78/0/12;
+RS_0x7f507e9dde78/1/4 .resolv tri, RS_0x7f507e9dde78/0/16, RS_0x7f507e9dde78/0/20, RS_0x7f507e9dde78/0/24, RS_0x7f507e9dde78/0/28;
+RS_0x7f507e9dde78 .resolv tri, RS_0x7f507e9dde78/1/0, RS_0x7f507e9dde78/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2418bc0_0 .net8 "AndNandOut", 31 0, RS_0x7f507e9dde78; 32 drivers
+RS_0x7f507e9f0418/0/0 .resolv tri, L_0x2b17c40, L_0x2b1a6f0, L_0x2b1d060, L_0x2b1f730;
+RS_0x7f507e9f0418/0/4 .resolv tri, L_0x2b22280, L_0x2b24bb0, L_0x2b272b0, L_0x2b29a40;
+RS_0x7f507e9f0418/0/8 .resolv tri, L_0x2b2c750, L_0x2b2ee40, L_0x2b31550, L_0x2b33e60;
+RS_0x7f507e9f0418/0/12 .resolv tri, L_0x2b365a0, L_0x2b38d50, L_0x2b3b520, L_0x2b3ddf0;
+RS_0x7f507e9f0418/0/16 .resolv tri, L_0x2b403b0, L_0x2b43a60, L_0x2b45560, L_0x2b47cc0;
+RS_0x7f507e9f0418/0/20 .resolv tri, L_0x2b4a290, L_0x2b4ddb0, L_0x2b4f690, L_0x2b51e50;
+RS_0x7f507e9f0418/0/24 .resolv tri, L_0x2b542f0, L_0x2b57f10, L_0x2b5a7b0, L_0x2b5d020;
+RS_0x7f507e9f0418/0/28 .resolv tri, L_0x2b5f890, L_0x2b62130, L_0x2b62ff0, L_0x2c13460;
+RS_0x7f507e9f0418/1/0 .resolv tri, RS_0x7f507e9f0418/0/0, RS_0x7f507e9f0418/0/4, RS_0x7f507e9f0418/0/8, RS_0x7f507e9f0418/0/12;
+RS_0x7f507e9f0418/1/4 .resolv tri, RS_0x7f507e9f0418/0/16, RS_0x7f507e9f0418/0/20, RS_0x7f507e9f0418/0/24, RS_0x7f507e9f0418/0/28;
+RS_0x7f507e9f0418 .resolv tri, RS_0x7f507e9f0418/1/0, RS_0x7f507e9f0418/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2418c40_0 .net8 "Cmd0Start", 31 0, RS_0x7f507e9f0418; 32 drivers
+RS_0x7f507e9f0448/0/0 .resolv tri, L_0x2b18b60, L_0x2b1b5c0, L_0x2b1dfa0, L_0x2b20640;
+RS_0x7f507e9f0448/0/4 .resolv tri, L_0x2b23100, L_0x2b25a40, L_0x2b28130, L_0x2b2a980;
+RS_0x7f507e9f0448/0/8 .resolv tri, L_0x2b2d550, L_0x2b2fc60, L_0x2b31aa0, L_0x2b34c70;
+RS_0x7f507e9f0448/0/12 .resolv tri, L_0x2b37400, L_0x2b39be0, L_0x2b3c4c0, L_0x2b3eea0;
+RS_0x7f507e9f0448/0/16 .resolv tri, L_0x2b420e0, L_0x2b44900, L_0x2b470b0, L_0x2b48950;
+RS_0x7f507e9f0448/0/20 .resolv tri, L_0x2b4b270, L_0x2b4ec60, L_0x2b51460, L_0x2b52cd0;
+RS_0x7f507e9f0448/0/24 .resolv tri, L_0x2b554a0, L_0x2b57790, L_0x2b59e50, L_0x2b5cac0;
+RS_0x7f507e9f0448/0/28 .resolv tri, L_0x2b5f150, L_0x2b61b80, L_0x2b65a00, L_0x2b66730;
+RS_0x7f507e9f0448/1/0 .resolv tri, RS_0x7f507e9f0448/0/0, RS_0x7f507e9f0448/0/4, RS_0x7f507e9f0448/0/8, RS_0x7f507e9f0448/0/12;
+RS_0x7f507e9f0448/1/4 .resolv tri, RS_0x7f507e9f0448/0/16, RS_0x7f507e9f0448/0/20, RS_0x7f507e9f0448/0/24, RS_0x7f507e9f0448/0/28;
+RS_0x7f507e9f0448 .resolv tri, RS_0x7f507e9f0448/1/0, RS_0x7f507e9f0448/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2415350_0 .net8 "Cmd1Start", 31 0, RS_0x7f507e9f0448; 32 drivers
+RS_0x7f507e9da848/0/0 .resolv tri, L_0x2bee390, L_0x2bef6b0, L_0x2bf09d0, L_0x2bf1ce0;
+RS_0x7f507e9da848/0/4 .resolv tri, L_0x2bf3000, L_0x2bf4380, L_0x2bf5730, L_0x2bf6a40;
+RS_0x7f507e9da848/0/8 .resolv tri, L_0x2bf7d70, L_0x2bf9090, L_0x2bfa3b0, L_0x2bfb6c0;
+RS_0x7f507e9da848/0/12 .resolv tri, L_0x2bfca00, L_0x2bfdd00, L_0x2bff020, L_0x2c00330;
+RS_0x7f507e9da848/0/16 .resolv tri, L_0x2c01660, L_0x2c02970, L_0x2c03c90, L_0x2c04fb0;
+RS_0x7f507e9da848/0/20 .resolv tri, L_0x2c062e0, L_0x2c074b0, L_0x2c085f0, L_0x2c09730;
+RS_0x7f507e9da848/0/24 .resolv tri, L_0x2c0a850, L_0x2c0b980, L_0x2c0cbd0, L_0x2c0def0;
+RS_0x7f507e9da848/0/28 .resolv tri, L_0x2c0f1f0, L_0x2c10500, L_0x2c11830, L_0x2c12b20;
+RS_0x7f507e9da848/1/0 .resolv tri, RS_0x7f507e9da848/0/0, RS_0x7f507e9da848/0/4, RS_0x7f507e9da848/0/8, RS_0x7f507e9da848/0/12;
+RS_0x7f507e9da848/1/4 .resolv tri, RS_0x7f507e9da848/0/16, RS_0x7f507e9da848/0/20, RS_0x7f507e9da848/0/24, RS_0x7f507e9da848/0/28;
+RS_0x7f507e9da848 .resolv tri, RS_0x7f507e9da848/1/0, RS_0x7f507e9da848/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x24153d0_0 .net8 "OrNorXorOut", 31 0, RS_0x7f507e9da848; 32 drivers
+RS_0x7f507e9f0178/0/0 .resolv tri, L_0x2b68d70, L_0x2b6afd0, L_0x2b6d050, L_0x2b6f2a0;
+RS_0x7f507e9f0178/0/4 .resolv tri, L_0x2b71320, L_0x2b735f0, L_0x2b75900, L_0x2b77e40;
+RS_0x7f507e9f0178/0/8 .resolv tri, L_0x2b7a0e0, L_0x2b7c410, L_0x2b7e700, L_0x2b7c370;
+RS_0x7f507e9f0178/0/12 .resolv tri, L_0x2b82b60, L_0x2b84ea0, L_0x2b866e0, L_0x2b895a0;
+RS_0x7f507e9f0178/0/16 .resolv tri, L_0x2b8a930, L_0x2b8e0e0, L_0x2b8f910, L_0x2b8d4f0;
+RS_0x7f507e9f0178/0/20 .resolv tri, L_0x2b93bb0, L_0x2b7ea10, L_0x2b98290, L_0x2b95780;
+RS_0x7f507e9f0178/0/24 .resolv tri, L_0x2b9c440, L_0x2b99f10, L_0x2ba0f30, L_0x2ba3180;
+RS_0x7f507e9f0178/0/28 .resolv tri, L_0x2ba5340, L_0x2ba6f40, L_0x2ba9860, L_0x2bad4c0;
+RS_0x7f507e9f0178/1/0 .resolv tri, RS_0x7f507e9f0178/0/0, RS_0x7f507e9f0178/0/4, RS_0x7f507e9f0178/0/8, RS_0x7f507e9f0178/0/12;
+RS_0x7f507e9f0178/1/4 .resolv tri, RS_0x7f507e9f0178/0/16, RS_0x7f507e9f0178/0/20, RS_0x7f507e9f0178/0/24, RS_0x7f507e9f0178/0/28;
+RS_0x7f507e9f0178 .resolv tri, RS_0x7f507e9f0178/1/0, RS_0x7f507e9f0178/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x24150b0_0 .net8 "SLTSum", 31 0, RS_0x7f507e9f0178; 32 drivers
+v0x2415130_0 .net "SLTflag", 0 0, L_0x2bad020; 1 drivers
+RS_0x7f507e9f0478/0/0 .resolv tri, L_0x2b19c10, L_0x2b1c560, L_0x2b1eba0, L_0x2b21450;
+RS_0x7f507e9f0478/0/4 .resolv tri, L_0x2b23b00, L_0x2b25e90, L_0x2b28770, L_0x2b212d0;
+RS_0x7f507e9f0478/0/8 .resolv tri, L_0x2b2d7d0, L_0x2b300b0, L_0x2b32a20, L_0x2b350c0;
+RS_0x7f507e9f0478/0/12 .resolv tri, L_0x2b37680, L_0x2b3a030, L_0x2b3c740, L_0x2b2ad30;
+RS_0x7f507e9f0478/0/16 .resolv tri, L_0x2b42360, L_0x2b456e0, L_0x2b47150, L_0x2b49870;
+RS_0x7f507e9f0478/0/20 .resolv tri, L_0x2b4ba50, L_0x2b4e980, L_0x2b509f0, L_0x2b53720;
+RS_0x7f507e9f0478/0/24 .resolv tri, L_0x2b56160, L_0x2b58960, L_0x2b5b050, L_0x2b5d8a0;
+RS_0x7f507e9f0478/0/28 .resolv tri, L_0x2b600f0, L_0x2b62450, L_0x2b647a0, L_0x2b3fe70;
+RS_0x7f507e9f0478/1/0 .resolv tri, RS_0x7f507e9f0478/0/0, RS_0x7f507e9f0478/0/4, RS_0x7f507e9f0478/0/8, RS_0x7f507e9f0478/0/12;
+RS_0x7f507e9f0478/1/4 .resolv tri, RS_0x7f507e9f0478/0/16, RS_0x7f507e9f0478/0/20, RS_0x7f507e9f0478/0/24, RS_0x7f507e9f0478/0/28;
+RS_0x7f507e9f0478 .resolv tri, RS_0x7f507e9f0478/1/0, RS_0x7f507e9f0478/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x25a1fd0_0 .net8 "ZeroFlag", 31 0, RS_0x7f507e9f0478; 32 drivers
+v0x25a2050_0 .net *"_s121", 0 0, L_0x2b23ba0; 1 drivers
+v0x27b6660_0 .net *"_s146", 0 0, L_0x2b25f30; 1 drivers
+v0x27b66e0_0 .net *"_s171", 0 0, L_0x2b28810; 1 drivers
+v0x25904b0_0 .net *"_s196", 0 0, L_0x2b29750; 1 drivers
+v0x2590550_0 .net *"_s21", 0 0, L_0x2b19860; 1 drivers
+v0x27b5460_0 .net *"_s221", 0 0, L_0x2b2d870; 1 drivers
+v0x27b51c0_0 .net *"_s246", 0 0, L_0x2b30150; 1 drivers
+v0x27b5260_0 .net *"_s271", 0 0, L_0x2b32ac0; 1 drivers
+v0x27b54e0_0 .net *"_s296", 0 0, L_0x2b35160; 1 drivers
+v0x27b4ff0_0 .net *"_s321", 0 0, L_0x2b37720; 1 drivers
+v0x27b4f20_0 .net *"_s346", 0 0, L_0x2b3a0d0; 1 drivers
+v0x27b4740_0 .net *"_s371", 0 0, L_0x2b3c7e0; 1 drivers
+v0x27b36f0_0 .net *"_s396", 0 0, L_0x2b2add0; 1 drivers
+v0x27b46a0_0 .net *"_s421", 0 0, L_0x2b42400; 1 drivers
+v0x27b3460_0 .net *"_s446", 0 0, L_0x2b44ad0; 1 drivers
+v0x27b3640_0 .net *"_s46", 0 0, L_0x2b1bca0; 1 drivers
+v0x27b31d0_0 .net *"_s471", 0 0, L_0x2b471f0; 1 drivers
+v0x27b33a0_0 .net *"_s496", 0 0, L_0x2b49910; 1 drivers
+v0x27b3100_0 .net *"_s521", 0 0, L_0x2b32190; 1 drivers
+v0x27b2b60_0 .net *"_s546", 0 0, L_0x2b4ea20; 1 drivers
+v0x27b2c00_0 .net *"_s571", 0 0, L_0x2b50a90; 1 drivers
+v0x27b25e0_0 .net *"_s596", 0 0, L_0x2b537c0; 1 drivers
+v0x27b2660_0 .net *"_s621", 0 0, L_0x2b56200; 1 drivers
+v0x27b2e60_0 .net *"_s646", 0 0, L_0x2b58a00; 1 drivers
+v0x262d560_0 .net *"_s671", 0 0, L_0x2b5b0f0; 1 drivers
+v0x262d600_0 .net *"_s696", 0 0, L_0x2b5d940; 1 drivers
+v0x262f630_0 .net *"_s71", 0 0, L_0x2b1ec40; 1 drivers
+v0x2627700_0 .net *"_s721", 0 0, L_0x2b60190; 1 drivers
+v0x2627780_0 .net *"_s746", 0 0, L_0x2b624f0; 1 drivers
+v0x2623970_0 .net *"_s771", 0 0, L_0x2b64840; 1 drivers
+v0x26239f0_0 .net *"_s811", 0 0, L_0x2b3ff10; 1 drivers
+v0x26297d0_0 .net *"_s814", 0 0, L_0x2c14570; 1 drivers
+v0x2629870_0 .net *"_s816", 0 0, L_0x2c14610; 1 drivers
+v0x260c0b0_0 .net *"_s818", 0 0, L_0x2c14810; 1 drivers
+v0x260c130_0 .net *"_s96", 0 0, L_0x2b214f0; 1 drivers
+v0x2609fe0_0 .net "carryin", 31 0, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; 0 drivers
+v0x260a060_0 .alias "carryout", 0 0, v0x2960740_0;
+v0x2606250_0 .alias "command", 2 0, v0x295f7a0_0;
+v0x26062d0_0 .alias "operandA", 31 0, v0x295f580_0;
+v0x2604210_0 .alias "operandB", 31 0, v0x295f6a0_0;
+v0x25eea00_0 .alias "overflow", 0 0, v0x29608f0_0;
+v0x25ec8a0_0 .alias "result", 31 0, v0x2960310_0;
+RS_0x7f507e9e4c28/0/0 .resolv tri, L_0x2b67c00, L_0x2b6a180, L_0x2b6b260, L_0x2b6e490;
+RS_0x7f507e9e4c28/0/4 .resolv tri, L_0x2b6f540, L_0x2b715a0, L_0x2b73690, L_0x2b75b80;
+RS_0x7f507e9e4c28/0/8 .resolv tri, L_0x2b77ee0, L_0x2b7a360, L_0x2b7c4b0, L_0x2b7ed90;
+RS_0x7f507e9e4c28/0/12 .resolv tri, L_0x2b80aa0, L_0x2b82de0, L_0x2b84f40, L_0x2b87240;
+RS_0x7f507e9e4c28/0/16 .resolv tri, L_0x2b89640, L_0x2b8bff0, L_0x2b8e180, L_0x2b8fe50;
+RS_0x7f507e9e4c28/0/20 .resolv tri, L_0x2b925b0, L_0x2b94110, L_0x2b96830, L_0x2b987b0;
+RS_0x7f507e9e4c28/0/24 .resolv tri, L_0x2b9a6e0, L_0x2b9c970, L_0x2b9e920, L_0x2ba11b0;
+RS_0x7f507e9e4c28/0/28 .resolv tri, L_0x2ba3220, L_0x2ba55c0, L_0x2ba7200, L_0x2ba99f0;
+RS_0x7f507e9e4c28/0/32 .resolv tri, L_0x2b3d500, L_0x2bb0510, L_0x2bb1940, L_0x2bb1d30;
+RS_0x7f507e9e4c28/0/36 .resolv tri, L_0x2bb3300, L_0x2bb4830, L_0x2bb5d90, L_0x2bb72c0;
+RS_0x7f507e9e4c28/0/40 .resolv tri, L_0x2bb8a70, L_0x2bb9e00, L_0x2bbb380, L_0x2bbc8c0;
+RS_0x7f507e9e4c28/0/44 .resolv tri, L_0x2bbdd30, L_0x2bbf210, L_0x2bc0710, L_0x2bc1c00;
+RS_0x7f507e9e4c28/0/48 .resolv tri, L_0x2bc3470, L_0x2bc4670, L_0x2bc5ab0, L_0x2bc6b20;
+RS_0x7f507e9e4c28/0/52 .resolv tri, L_0x2bc7eb0, L_0x2bc9230, L_0x2bca680, L_0x2bcba40;
+RS_0x7f507e9e4c28/0/56 .resolv tri, L_0x2bccf00, L_0x2bce3d0, L_0x2bcf890, L_0x2bd0d70;
+RS_0x7f507e9e4c28/0/60 .resolv tri, L_0x2bd2220, L_0x2bd4470, L_0x2bd5000, L_0x2bd64c0;
+RS_0x7f507e9e4c28/1/0 .resolv tri, RS_0x7f507e9e4c28/0/0, RS_0x7f507e9e4c28/0/4, RS_0x7f507e9e4c28/0/8, RS_0x7f507e9e4c28/0/12;
+RS_0x7f507e9e4c28/1/4 .resolv tri, RS_0x7f507e9e4c28/0/16, RS_0x7f507e9e4c28/0/20, RS_0x7f507e9e4c28/0/24, RS_0x7f507e9e4c28/0/28;
+RS_0x7f507e9e4c28/1/8 .resolv tri, RS_0x7f507e9e4c28/0/32, RS_0x7f507e9e4c28/0/36, RS_0x7f507e9e4c28/0/40, RS_0x7f507e9e4c28/0/44;
+RS_0x7f507e9e4c28/1/12 .resolv tri, RS_0x7f507e9e4c28/0/48, RS_0x7f507e9e4c28/0/52, RS_0x7f507e9e4c28/0/56, RS_0x7f507e9e4c28/0/60;
+RS_0x7f507e9e4c28 .resolv tri, RS_0x7f507e9e4c28/1/0, RS_0x7f507e9e4c28/1/4, RS_0x7f507e9e4c28/1/8, RS_0x7f507e9e4c28/1/12;
+v0x25ec920_0 .net8 "subtract", 31 0, RS_0x7f507e9e4c28; 64 drivers
+v0x25e8b10_0 .net "yeszero", 0 0, L_0x2c14700; 1 drivers
+v0x25e8b90_0 .alias "zero", 0 0, v0x2960030_0;
+L_0x2b17c40 .part/pv L_0x2b17a30, 1, 1, 32;
+L_0x2b17ce0 .part v0x2960210_0, 0, 1;
+L_0x2b17e10 .part v0x2960210_0, 1, 1;
+L_0x2b17f40 .part RS_0x7f507e9e4aa8, 1, 1;
+L_0x2b17fe0 .part RS_0x7f507e9e4aa8, 1, 1;
+L_0x2b180d0 .part RS_0x7f507e9da848, 1, 1;
+L_0x2b18250 .part RS_0x7f507e9f0178, 1, 1;
+L_0x2b18b60 .part/pv L_0x2b18950, 1, 1, 32;
+L_0x2b18c50 .part v0x2960210_0, 0, 1;
+L_0x2b18d80 .part v0x2960210_0, 1, 1;
+L_0x2b18f10 .part RS_0x7f507e9dde78, 1, 1;
+L_0x2b18fb0 .part RS_0x7f507e9dde78, 1, 1;
+L_0x2b190c0 .part RS_0x7f507e9da848, 1, 1;
+L_0x2b191b0 .part RS_0x7f507e9da848, 1, 1;
+L_0x2b196d0 .part/pv L_0x2b19590, 1, 1, 32;
+L_0x2b197c0 .part v0x2960210_0, 2, 1;
+L_0x2b198f0 .part RS_0x7f507e9f0418, 1, 1;
+L_0x2b19a30 .part RS_0x7f507e9f0448, 1, 1;
+L_0x2b19c10 .part/pv L_0x2b19860, 1, 1, 32;
+L_0x2b19d90 .part RS_0x7f507e9f0478, 0, 1;
+L_0x2b19b70 .part RS_0x7f507e9f0b38, 1, 1;
+L_0x2b1a6f0 .part/pv L_0x2b1a510, 2, 1, 32;
+L_0x2b19e80 .part v0x2960210_0, 0, 1;
+L_0x2b1a8e0 .part v0x2960210_0, 1, 1;
+L_0x2b1a790 .part RS_0x7f507e9e4aa8, 2, 1;
+L_0x2b1ab70 .part RS_0x7f507e9e4aa8, 2, 1;
+L_0x2b1aa10 .part RS_0x7f507e9da848, 2, 1;
+L_0x2b1acf0 .part RS_0x7f507e9f0178, 2, 1;
+L_0x2b1b5c0 .part/pv L_0x2b1b3b0, 2, 1, 32;
+L_0x2b1b660 .part v0x2960210_0, 0, 1;
+L_0x2b1ade0 .part v0x2960210_0, 1, 1;
+L_0x2b1b920 .part RS_0x7f507e9dde78, 2, 1;
+L_0x2b1b790 .part RS_0x7f507e9dde78, 2, 1;
+L_0x2b1bb60 .part RS_0x7f507e9da848, 2, 1;
+L_0x2b1ba50 .part RS_0x7f507e9da848, 2, 1;
+L_0x2b1c090 .part/pv L_0x2b1bf50, 2, 1, 32;
+L_0x2b1bc00 .part v0x2960210_0, 2, 1;
+L_0x2b1c2f0 .part RS_0x7f507e9f0418, 2, 1;
+L_0x2b1c1c0 .part RS_0x7f507e9f0448, 2, 1;
+L_0x2b1c560 .part/pv L_0x2b1bca0, 2, 1, 32;
+L_0x2b1c4b0 .part RS_0x7f507e9f0478, 1, 1;
+L_0x2b1c7e0 .part RS_0x7f507e9f0b38, 2, 1;
+L_0x2b1d060 .part/pv L_0x2b1ce50, 3, 1, 32;
+L_0x2b1d100 .part v0x2960210_0, 0, 1;
+L_0x2b1c880 .part v0x2960210_0, 1, 1;
+L_0x2b1d3a0 .part RS_0x7f507e9e4aa8, 3, 1;
+L_0x2b1d230 .part RS_0x7f507e9e4aa8, 3, 1;
+L_0x2b1d2d0 .part RS_0x7f507e9da848, 3, 1;
+L_0x2b1d440 .part RS_0x7f507e9f0178, 3, 1;
+L_0x2b1dfa0 .part/pv L_0x2b1dd90, 3, 1, 32;
+L_0x2b1d720 .part v0x2960210_0, 0, 1;
+L_0x2b1e1e0 .part v0x2960210_0, 1, 1;
+L_0x2b1e040 .part RS_0x7f507e9dde78, 3, 1;
+L_0x2b1e0e0 .part RS_0x7f507e9dde78, 3, 1;
+L_0x2b1e4d0 .part RS_0x7f507e9da848, 3, 1;
+L_0x2b1e570 .part RS_0x7f507e9da848, 3, 1;
+L_0x2b1ea60 .part/pv L_0x2b1e920, 3, 1, 32;
+L_0x2b1eb00 .part v0x2960210_0, 2, 1;
+L_0x2b1e610 .part RS_0x7f507e9f0418, 3, 1;
+L_0x2b1e700 .part RS_0x7f507e9f0448, 3, 1;
+L_0x2b1eba0 .part/pv L_0x2b1ec40, 3, 1, 32;
+L_0x2b1efc0 .part RS_0x7f507e9f0478, 2, 1;
+L_0x2b1edd0 .part RS_0x7f507e9f0b38, 3, 1;
+L_0x2b1f730 .part/pv L_0x2b1f520, 4, 1, 32;
+L_0x2b1f060 .part v0x2960210_0, 0, 1;
+L_0x2b1f190 .part v0x2960210_0, 1, 1;
+L_0x2b1f7d0 .part RS_0x7f507e9e4aa8, 4, 1;
+L_0x2b1fc90 .part RS_0x7f507e9e4aa8, 4, 1;
+L_0x2b1fa70 .part RS_0x7f507e9da848, 4, 1;
+L_0x2b1fb60 .part RS_0x7f507e9f0178, 4, 1;
+L_0x2b20640 .part/pv L_0x2b20430, 4, 1, 32;
+L_0x2b206e0 .part v0x2960210_0, 0, 1;
+L_0x2b1fd30 .part v0x2960210_0, 1, 1;
+L_0x2b1fe60 .part RS_0x7f507e9dde78, 4, 1;
+L_0x2b20810 .part RS_0x7f507e9dde78, 4, 1;
+L_0x2b208b0 .part RS_0x7f507e9da848, 4, 1;
+L_0x2b209a0 .part RS_0x7f507e9da848, 4, 1;
+L_0x2b21190 .part/pv L_0x2b21050, 4, 1, 32;
+L_0x2b20b70 .part v0x2960210_0, 2, 1;
+L_0x2b20c10 .part RS_0x7f507e9f0418, 4, 1;
+L_0x2b20d00 .part RS_0x7f507e9f0448, 4, 1;
+L_0x2b21450 .part/pv L_0x2b214f0, 4, 1, 32;
+L_0x2b21970 .part RS_0x7f507e9f0478, 3, 1;
+L_0x2b21b20 .part RS_0x7f507e9f0b38, 4, 1;
+L_0x2b22280 .part/pv L_0x2b22070, 5, 1, 32;
+L_0x2b22320 .part v0x2960210_0, 0, 1;
+L_0x2b21bc0 .part v0x2960210_0, 1, 1;
+L_0x2b21cf0 .part RS_0x7f507e9e4aa8, 5, 1;
+L_0x2b21d90 .part RS_0x7f507e9e4aa8, 5, 1;
+L_0x2b22720 .part RS_0x7f507e9da848, 5, 1;
+L_0x2b22450 .part RS_0x7f507e9f0178, 5, 1;
+L_0x2b23100 .part/pv L_0x2b22ef0, 5, 1, 32;
+L_0x2b22810 .part v0x2960210_0, 0, 1;
+L_0x2b22940 .part v0x2960210_0, 1, 1;
+L_0x2b234a0 .part RS_0x7f507e9dde78, 5, 1;
+L_0x2b23540 .part RS_0x7f507e9dde78, 5, 1;
+L_0x2b231a0 .part RS_0x7f507e9da848, 5, 1;
+L_0x2b23290 .part RS_0x7f507e9da848, 5, 1;
+L_0x2b237b0 .part/pv L_0x2b23670, 5, 1, 32;
+L_0x2b23850 .part v0x2960210_0, 2, 1;
+L_0x2b23e30 .part RS_0x7f507e9f0418, 5, 1;
+L_0x2b23f20 .part RS_0x7f507e9f0448, 5, 1;
+L_0x2b23b00 .part/pv L_0x2b23ba0, 5, 1, 32;
+L_0x2b23ce0 .part RS_0x7f507e9f0478, 4, 1;
+L_0x2b23d80 .part RS_0x7f507e9f0b38, 5, 1;
+L_0x2b24bb0 .part/pv L_0x2b249a0, 6, 1, 32;
+L_0x2b24010 .part v0x2960210_0, 0, 1;
+L_0x2b24140 .part v0x2960210_0, 1, 1;
+L_0x2b24270 .part RS_0x7f507e9e4aa8, 6, 1;
+L_0x2b24fc0 .part RS_0x7f507e9e4aa8, 6, 1;
+L_0x2b24c50 .part RS_0x7f507e9da848, 6, 1;
+L_0x2b24cf0 .part RS_0x7f507e9f0178, 6, 1;
+L_0x2b25a40 .part/pv L_0x2b25830, 6, 1, 32;
+L_0x2b25ae0 .part v0x2960210_0, 0, 1;
+L_0x2b25060 .part v0x2960210_0, 1, 1;
+L_0x2b25190 .part RS_0x7f507e9dde78, 6, 1;
+L_0x2b25230 .part RS_0x7f507e9dde78, 6, 1;
+L_0x2b252d0 .part RS_0x7f507e9da848, 6, 1;
+L_0x2b25fd0 .part RS_0x7f507e9da848, 6, 1;
+L_0x2b264d0 .part/pv L_0x2b26390, 6, 1, 32;
+L_0x2b25c10 .part v0x2960210_0, 2, 1;
+L_0x2b25cb0 .part RS_0x7f507e9f0418, 6, 1;
+L_0x2b25da0 .part RS_0x7f507e9f0448, 6, 1;
+L_0x2b25e90 .part/pv L_0x2b25f30, 6, 1, 32;
+L_0x2b26a00 .part RS_0x7f507e9f0478, 5, 1;
+L_0x2b26aa0 .part RS_0x7f507e9f0b38, 6, 1;
+L_0x2b272b0 .part/pv L_0x2b270a0, 7, 1, 32;
+L_0x2b27350 .part v0x2960210_0, 0, 1;
+L_0x2b26b90 .part v0x2960210_0, 1, 1;
+L_0x2b26cc0 .part RS_0x7f507e9e4aa8, 7, 1;
+L_0x2b26d60 .part RS_0x7f507e9e4aa8, 7, 1;
+L_0x2b26e00 .part RS_0x7f507e9da848, 7, 1;
+L_0x2b26ef0 .part RS_0x7f507e9f0178, 7, 1;
+L_0x2b28130 .part/pv L_0x2b27f20, 7, 1, 32;
+L_0x2b27480 .part v0x2960210_0, 0, 1;
+L_0x2b275b0 .part v0x2960210_0, 1, 1;
+L_0x2b276e0 .part RS_0x7f507e9dde78, 7, 1;
+L_0x2b27780 .part RS_0x7f507e9dde78, 7, 1;
+L_0x2b28630 .part RS_0x7f507e9da848, 7, 1;
+L_0x2b286d0 .part RS_0x7f507e9da848, 7, 1;
+L_0x2b284c0 .part/pv L_0x2b28380, 7, 1, 32;
+L_0x2b28560 .part v0x2960210_0, 2, 1;
+L_0x2b28bf0 .part RS_0x7f507e9f0418, 7, 1;
+L_0x2b28ce0 .part RS_0x7f507e9f0448, 7, 1;
+L_0x2b28770 .part/pv L_0x2b28810, 7, 1, 32;
+L_0x2b28950 .part RS_0x7f507e9f0478, 6, 1;
+L_0x2b289f0 .part RS_0x7f507e9f0b38, 7, 1;
+L_0x2b29a40 .part/pv L_0x2b29830, 8, 1, 32;
+L_0x2b28dd0 .part v0x2960210_0, 0, 1;
+L_0x2b28f00 .part v0x2960210_0, 1, 1;
+L_0x2b29030 .part RS_0x7f507e9e4aa8, 8, 1;
+L_0x2b1f870 .part RS_0x7f507e9e4aa8, 8, 1;
+L_0x2b290d0 .part RS_0x7f507e9da848, 8, 1;
+L_0x2b291c0 .part RS_0x7f507e9f0178, 8, 1;
+L_0x2b2a980 .part/pv L_0x2b2a770, 8, 1, 32;
+L_0x2b2aa20 .part v0x2960210_0, 0, 1;
+L_0x2b2a1b0 .part v0x2960210_0, 1, 1;
+L_0x2b2a2e0 .part RS_0x7f507e9dde78, 8, 1;
+L_0x2b2a590 .part RS_0x7f507e9dde78, 8, 1;
+L_0x2b20a40 .part RS_0x7f507e9da848, 8, 1;
+L_0x2b2b060 .part RS_0x7f507e9da848, 8, 1;
+L_0x2b2b410 .part/pv L_0x2b2b310, 8, 1, 32;
+L_0x2b21230 .part v0x2960210_0, 2, 1;
+L_0x2b2ab50 .part RS_0x7f507e9f0418, 8, 1;
+L_0x2b215a0 .part RS_0x7f507e9f0448, 8, 1;
+L_0x2b212d0 .part/pv L_0x2b29750, 8, 1, 32;
+L_0x2b2bc00 .part RS_0x7f507e9f0478, 7, 1;
+L_0x2b21a10 .part RS_0x7f507e9f0b38, 8, 1;
+L_0x2b2c750 .part/pv L_0x2b2c540, 9, 1, 32;
+L_0x2b2c7f0 .part v0x2960210_0, 0, 1;
+L_0x2b2beb0 .part v0x2960210_0, 1, 1;
+L_0x2b2bfe0 .part RS_0x7f507e9e4aa8, 9, 1;
+L_0x2b2c080 .part RS_0x7f507e9e4aa8, 9, 1;
+L_0x2b2c120 .part RS_0x7f507e9da848, 9, 1;
+L_0x2b2c210 .part RS_0x7f507e9f0178, 9, 1;
+L_0x2b2d550 .part/pv L_0x2b2d340, 9, 1, 32;
+L_0x2b2c920 .part v0x2960210_0, 0, 1;
+L_0x2b2ca50 .part v0x2960210_0, 1, 1;
+L_0x2b2cb80 .part RS_0x7f507e9dde78, 9, 1;
+L_0x2b2cc20 .part RS_0x7f507e9dde78, 9, 1;
+L_0x2b2ccc0 .part RS_0x7f507e9da848, 9, 1;
+L_0x2b2cdb0 .part RS_0x7f507e9da848, 9, 1;
+L_0x2b2dee0 .part/pv L_0x2b2dda0, 9, 1, 32;
+L_0x2b2df80 .part v0x2960210_0, 2, 1;
+L_0x2b2d5f0 .part RS_0x7f507e9f0418, 9, 1;
+L_0x2b2d6e0 .part RS_0x7f507e9f0448, 9, 1;
+L_0x2b2d7d0 .part/pv L_0x2b2d870, 9, 1, 32;
+L_0x2b2d9b0 .part RS_0x7f507e9f0478, 8, 1;
+L_0x2b2da50 .part RS_0x7f507e9f0b38, 9, 1;
+L_0x2b2ee40 .part/pv L_0x2b2ec30, 10, 1, 32;
+L_0x2b2e020 .part v0x2960210_0, 0, 1;
+L_0x2b2e150 .part v0x2960210_0, 1, 1;
+L_0x2b2e280 .part RS_0x7f507e9e4aa8, 10, 1;
+L_0x2b2e320 .part RS_0x7f507e9e4aa8, 10, 1;
+L_0x2b2e3c0 .part RS_0x7f507e9da848, 10, 1;
+L_0x2b2e4b0 .part RS_0x7f507e9f0178, 10, 1;
+L_0x2b2fc60 .part/pv L_0x2b2fa50, 10, 1, 32;
+L_0x2b2fd00 .part v0x2960210_0, 0, 1;
+L_0x2b2eee0 .part v0x2960210_0, 1, 1;
+L_0x2b2f010 .part RS_0x7f507e9dde78, 10, 1;
+L_0x2b2f0b0 .part RS_0x7f507e9dde78, 10, 1;
+L_0x2b2f150 .part RS_0x7f507e9da848, 10, 1;
+L_0x2b2f240 .part RS_0x7f507e9da848, 10, 1;
+L_0x2b305e0 .part/pv L_0x2b304e0, 10, 1, 32;
+L_0x2b2fe30 .part v0x2960210_0, 2, 1;
+L_0x2b2fed0 .part RS_0x7f507e9f0418, 10, 1;
+L_0x2b2ffc0 .part RS_0x7f507e9f0448, 10, 1;
+L_0x2b300b0 .part/pv L_0x2b30150, 10, 1, 32;
+L_0x2b30290 .part RS_0x7f507e9f0478, 9, 1;
+L_0x2b30330 .part RS_0x7f507e9f0b38, 10, 1;
+L_0x2b31550 .part/pv L_0x2b31340, 11, 1, 32;
+L_0x2b315f0 .part v0x2960210_0, 0, 1;
+L_0x2b30680 .part v0x2960210_0, 1, 1;
+L_0x2b307b0 .part RS_0x7f507e9e4aa8, 11, 1;
+L_0x2b30850 .part RS_0x7f507e9e4aa8, 11, 1;
+L_0x2b308f0 .part RS_0x7f507e9da848, 11, 1;
+L_0x2b238f0 .part RS_0x7f507e9f0178, 11, 1;
+L_0x2b31aa0 .part/pv L_0x2b31890, 11, 1, 32;
+L_0x2b31b40 .part v0x2960210_0, 0, 1;
+L_0x2b31c70 .part v0x2960210_0, 1, 1;
+L_0x2b328e0 .part RS_0x7f507e9dde78, 11, 1;
+L_0x2b32980 .part RS_0x7f507e9dde78, 11, 1;
+L_0x2b321f0 .part RS_0x7f507e9da848, 11, 1;
+L_0x2b322e0 .part RS_0x7f507e9da848, 11, 1;
+L_0x2b326c0 .part/pv L_0x2b32580, 11, 1, 32;
+L_0x2b32760 .part v0x2960210_0, 2, 1;
+L_0x2b32800 .part RS_0x7f507e9f0418, 11, 1;
+L_0x2b33190 .part RS_0x7f507e9f0448, 11, 1;
+L_0x2b32a20 .part/pv L_0x2b32ac0, 11, 1, 32;
+L_0x2b32bc0 .part RS_0x7f507e9f0478, 10, 1;
+L_0x2b32c60 .part RS_0x7f507e9f0b38, 11, 1;
+L_0x2b33e60 .part/pv L_0x2b33c50, 12, 1, 32;
+L_0x2b33280 .part v0x2960210_0, 0, 1;
+L_0x2b333b0 .part v0x2960210_0, 1, 1;
+L_0x2b334e0 .part RS_0x7f507e9e4aa8, 12, 1;
+L_0x2b33580 .part RS_0x7f507e9e4aa8, 12, 1;
+L_0x2b33620 .part RS_0x7f507e9da848, 12, 1;
+L_0x2b33710 .part RS_0x7f507e9f0178, 12, 1;
+L_0x2b34c70 .part/pv L_0x2b34a60, 12, 1, 32;
+L_0x2b34d10 .part v0x2960210_0, 0, 1;
+L_0x2b33f00 .part v0x2960210_0, 1, 1;
+L_0x2b34030 .part RS_0x7f507e9dde78, 12, 1;
+L_0x2b340d0 .part RS_0x7f507e9dde78, 12, 1;
+L_0x2b34170 .part RS_0x7f507e9da848, 12, 1;
+L_0x2b34260 .part RS_0x7f507e9da848, 12, 1;
+L_0x2b35640 .part/pv L_0x2b34560, 12, 1, 32;
+L_0x2b34e40 .part v0x2960210_0, 2, 1;
+L_0x2b34ee0 .part RS_0x7f507e9f0418, 12, 1;
+L_0x2b34fd0 .part RS_0x7f507e9f0448, 12, 1;
+L_0x2b350c0 .part/pv L_0x2b35160, 12, 1, 32;
+L_0x2b352a0 .part RS_0x7f507e9f0478, 11, 1;
+L_0x2b35340 .part RS_0x7f507e9f0b38, 12, 1;
+L_0x2b365a0 .part/pv L_0x2b36390, 13, 1, 32;
+L_0x2b36640 .part v0x2960210_0, 0, 1;
+L_0x2b356e0 .part v0x2960210_0, 1, 1;
+L_0x2b35810 .part RS_0x7f507e9e4aa8, 13, 1;
+L_0x2b358b0 .part RS_0x7f507e9e4aa8, 13, 1;
+L_0x2b35950 .part RS_0x7f507e9da848, 13, 1;
+L_0x2b35a40 .part RS_0x7f507e9f0178, 13, 1;
+L_0x2b37400 .part/pv L_0x2b371f0, 13, 1, 32;
+L_0x2b36770 .part v0x2960210_0, 0, 1;
+L_0x2b368a0 .part v0x2960210_0, 1, 1;
+L_0x2b369d0 .part RS_0x7f507e9dde78, 13, 1;
+L_0x2b36a70 .part RS_0x7f507e9dde78, 13, 1;
+L_0x2b36b10 .part RS_0x7f507e9da848, 13, 1;
+L_0x2b36c00 .part RS_0x7f507e9da848, 13, 1;
+L_0x2b37e90 .part/pv L_0x2b37d50, 13, 1, 32;
+L_0x2b37f30 .part v0x2960210_0, 2, 1;
+L_0x2b374a0 .part RS_0x7f507e9f0418, 13, 1;
+L_0x2b37590 .part RS_0x7f507e9f0448, 13, 1;
+L_0x2b37680 .part/pv L_0x2b37720, 13, 1, 32;
+L_0x2b37860 .part RS_0x7f507e9f0478, 12, 1;
+L_0x2b37900 .part RS_0x7f507e9f0b38, 13, 1;
+L_0x2b38d50 .part/pv L_0x2b38b40, 14, 1, 32;
+L_0x2b37fd0 .part v0x2960210_0, 0, 1;
+L_0x2b38100 .part v0x2960210_0, 1, 1;
+L_0x2b38230 .part RS_0x7f507e9e4aa8, 14, 1;
+L_0x2b382d0 .part RS_0x7f507e9e4aa8, 14, 1;
+L_0x2b38370 .part RS_0x7f507e9da848, 14, 1;
+L_0x2b38460 .part RS_0x7f507e9f0178, 14, 1;
+L_0x2b39be0 .part/pv L_0x2b399d0, 14, 1, 32;
+L_0x2b39c80 .part v0x2960210_0, 0, 1;
+L_0x2b38df0 .part v0x2960210_0, 1, 1;
+L_0x2b38f20 .part RS_0x7f507e9dde78, 14, 1;
+L_0x2b38fc0 .part RS_0x7f507e9dde78, 14, 1;
+L_0x2b39060 .part RS_0x7f507e9da848, 14, 1;
+L_0x2b39150 .part RS_0x7f507e9da848, 14, 1;
+L_0x2b3a6b0 .part/pv L_0x2b39510, 14, 1, 32;
+L_0x2b39db0 .part v0x2960210_0, 2, 1;
+L_0x2b39e50 .part RS_0x7f507e9f0418, 14, 1;
+L_0x2b39f40 .part RS_0x7f507e9f0448, 14, 1;
+L_0x2b3a030 .part/pv L_0x2b3a0d0, 14, 1, 32;
+L_0x2b3a210 .part RS_0x7f507e9f0478, 13, 1;
+L_0x2b3a2b0 .part RS_0x7f507e9f0b38, 14, 1;
+L_0x2b3b520 .part/pv L_0x2b3b310, 15, 1, 32;
+L_0x2b3b5c0 .part v0x2960210_0, 0, 1;
+L_0x2b3a750 .part v0x2960210_0, 1, 1;
+L_0x2b3a880 .part RS_0x7f507e9e4aa8, 15, 1;
+L_0x2b3a920 .part RS_0x7f507e9e4aa8, 15, 1;
+L_0x2b3a9c0 .part RS_0x7f507e9da848, 15, 1;
+L_0x2b3aab0 .part RS_0x7f507e9f0178, 15, 1;
+L_0x2b3c4c0 .part/pv L_0x2b3c2b0, 15, 1, 32;
+L_0x2b3b6f0 .part v0x2960210_0, 0, 1;
+L_0x2b3b820 .part v0x2960210_0, 1, 1;
+L_0x2b3b950 .part RS_0x7f507e9dde78, 15, 1;
+L_0x2b3b9f0 .part RS_0x7f507e9dde78, 15, 1;
+L_0x2b3ba90 .part RS_0x7f507e9da848, 15, 1;
+L_0x2b3bb80 .part RS_0x7f507e9da848, 15, 1;
+L_0x2b3cf60 .part/pv L_0x2b3bf40, 15, 1, 32;
+L_0x2b3d000 .part v0x2960210_0, 2, 1;
+L_0x2b3c560 .part RS_0x7f507e9f0418, 15, 1;
+L_0x2b3c650 .part RS_0x7f507e9f0448, 15, 1;
+L_0x2b3c740 .part/pv L_0x2b3c7e0, 15, 1, 32;
+L_0x2b3c920 .part RS_0x7f507e9f0478, 14, 1;
+L_0x2b3c9c0 .part RS_0x7f507e9f0b38, 15, 1;
+L_0x2b3ddf0 .part/pv L_0x2b3dbe0, 16, 1, 32;
+L_0x2b3d0a0 .part v0x2960210_0, 0, 1;
+L_0x2b3d1d0 .part v0x2960210_0, 1, 1;
+L_0x2b3d300 .part RS_0x7f507e9e4aa8, 16, 1;
+L_0x2b29fa0 .part RS_0x7f507e9e4aa8, 16, 1;
+L_0x2b2a040 .part RS_0x7f507e9da848, 16, 1;
+L_0x2b3d7b0 .part RS_0x7f507e9f0178, 16, 1;
+L_0x2b3eea0 .part/pv L_0x2b3ec90, 16, 1, 32;
+L_0x2b3ef40 .part v0x2960210_0, 0, 1;
+L_0x2b3de90 .part v0x2960210_0, 1, 1;
+L_0x2b3dfc0 .part RS_0x7f507e9dde78, 16, 1;
+L_0x2b2a380 .part RS_0x7f507e9dde78, 16, 1;
+L_0x2b2a420 .part RS_0x7f507e9da848, 16, 1;
+L_0x2b3e470 .part RS_0x7f507e9da848, 16, 1;
+L_0x2b3fb50 .part/pv L_0x2b2a510, 16, 1, 32;
+L_0x2b2b4b0 .part v0x2960210_0, 2, 1;
+L_0x2b2b550 .part RS_0x7f507e9f0418, 16, 1;
+L_0x2b2ac40 .part RS_0x7f507e9f0448, 16, 1;
+L_0x2b2ad30 .part/pv L_0x2b2add0, 16, 1, 32;
+L_0x2b2af10 .part RS_0x7f507e9f0478, 15, 1;
+L_0x2b2afb0 .part RS_0x7f507e9f0b38, 16, 1;
+L_0x2b403b0 .part/pv L_0x2b401a0, 17, 1, 32;
+L_0x2b40450 .part v0x2960210_0, 0, 1;
+L_0x2b40580 .part v0x2960210_0, 1, 1;
+L_0x2b406b0 .part RS_0x7f507e9e4aa8, 17, 1;
+L_0x2b40750 .part RS_0x7f507e9e4aa8, 17, 1;
+L_0x2b407f0 .part RS_0x7f507e9da848, 17, 1;
+L_0x2b408e0 .part RS_0x7f507e9f0178, 17, 1;
+L_0x2b420e0 .part/pv L_0x2b41ed0, 17, 1, 32;
+L_0x2b40e90 .part v0x2960210_0, 0, 1;
+L_0x2b40fc0 .part v0x2960210_0, 1, 1;
+L_0x2b410f0 .part RS_0x7f507e9dde78, 17, 1;
+L_0x2b41190 .part RS_0x7f507e9dde78, 17, 1;
+L_0x2b41230 .part RS_0x7f507e9da848, 17, 1;
+L_0x2b41320 .part RS_0x7f507e9da848, 17, 1;
+L_0x2b41820 .part/pv L_0x2b416e0, 17, 1, 32;
+L_0x2b42c80 .part v0x2960210_0, 2, 1;
+L_0x2b42180 .part RS_0x7f507e9f0418, 17, 1;
+L_0x2b42270 .part RS_0x7f507e9f0448, 17, 1;
+L_0x2b42360 .part/pv L_0x2b42400, 17, 1, 32;
+L_0x2b42540 .part RS_0x7f507e9f0478, 16, 1;
+L_0x2b425e0 .part RS_0x7f507e9f0b38, 17, 1;
+L_0x2b43a60 .part/pv L_0x2b43850, 18, 1, 32;
+L_0x2b42d20 .part v0x2960210_0, 0, 1;
+L_0x2b42e50 .part v0x2960210_0, 1, 1;
+L_0x2b42f80 .part RS_0x7f507e9e4aa8, 18, 1;
+L_0x2b43020 .part RS_0x7f507e9e4aa8, 18, 1;
+L_0x2b430c0 .part RS_0x7f507e9da848, 18, 1;
+L_0x2b431b0 .part RS_0x7f507e9f0178, 18, 1;
+L_0x2b44900 .part/pv L_0x2b446f0, 18, 1, 32;
+L_0x2b449a0 .part v0x2960210_0, 0, 1;
+L_0x2b43b00 .part v0x2960210_0, 1, 1;
+L_0x2b43c30 .part RS_0x7f507e9dde78, 18, 1;
+L_0x2b43cd0 .part RS_0x7f507e9dde78, 18, 1;
+L_0x2b43d70 .part RS_0x7f507e9da848, 18, 1;
+L_0x2b43e60 .part RS_0x7f507e9da848, 18, 1;
+L_0x2b44360 .part/pv L_0x2b44220, 18, 1, 32;
+L_0x2b44400 .part v0x2960210_0, 2, 1;
+L_0x2b444a0 .part RS_0x7f507e9f0418, 18, 1;
+L_0x2b44590 .part RS_0x7f507e9f0448, 18, 1;
+L_0x2b456e0 .part/pv L_0x2b44ad0, 18, 1, 32;
+L_0x2b44bd0 .part RS_0x7f507e9f0478, 17, 1;
+L_0x2b44c70 .part RS_0x7f507e9f0b38, 18, 1;
+L_0x2b45560 .part/pv L_0x2b45350, 19, 1, 32;
+L_0x2b46360 .part v0x2960210_0, 0, 1;
+L_0x2b45780 .part v0x2960210_0, 1, 1;
+L_0x2b458b0 .part RS_0x7f507e9e4aa8, 19, 1;
+L_0x2b45950 .part RS_0x7f507e9e4aa8, 19, 1;
+L_0x2b459f0 .part RS_0x7f507e9da848, 19, 1;
+L_0x2b45ae0 .part RS_0x7f507e9f0178, 19, 1;
+L_0x2b470b0 .part/pv L_0x2b461f0, 19, 1, 32;
+L_0x2b46400 .part v0x2960210_0, 0, 1;
+L_0x2b46530 .part v0x2960210_0, 1, 1;
+L_0x2b46660 .part RS_0x7f507e9dde78, 19, 1;
+L_0x2b46700 .part RS_0x7f507e9dde78, 19, 1;
+L_0x2b467a0 .part RS_0x7f507e9da848, 19, 1;
+L_0x2b46890 .part RS_0x7f507e9da848, 19, 1;
+L_0x2b46d90 .part/pv L_0x2b46c50, 19, 1, 32;
+L_0x2b46e30 .part v0x2960210_0, 2, 1;
+L_0x2b46ed0 .part RS_0x7f507e9f0418, 19, 1;
+L_0x2b47db0 .part RS_0x7f507e9f0448, 19, 1;
+L_0x2b47150 .part/pv L_0x2b471f0, 19, 1, 32;
+L_0x2b47330 .part RS_0x7f507e9f0478, 18, 1;
+L_0x2b473d0 .part RS_0x7f507e9f0b38, 19, 1;
+L_0x2b47cc0 .part/pv L_0x2b47ab0, 20, 1, 32;
+L_0x2b48ae0 .part v0x2960210_0, 0, 1;
+L_0x2b48c10 .part v0x2960210_0, 1, 1;
+L_0x2b47e50 .part RS_0x7f507e9e4aa8, 20, 1;
+L_0x2b47ef0 .part RS_0x7f507e9e4aa8, 20, 1;
+L_0x2b47f90 .part RS_0x7f507e9da848, 20, 1;
+L_0x2b48030 .part RS_0x7f507e9f0178, 20, 1;
+L_0x2b48950 .part/pv L_0x2b48740, 20, 1, 32;
+L_0x2b489f0 .part v0x2960210_0, 0, 1;
+L_0x2b48d40 .part v0x2960210_0, 1, 1;
+L_0x2b48e70 .part RS_0x7f507e9dde78, 20, 1;
+L_0x2b48f10 .part RS_0x7f507e9dde78, 20, 1;
+L_0x2b48fb0 .part RS_0x7f507e9da848, 20, 1;
+L_0x2b49050 .part RS_0x7f507e9da848, 20, 1;
+L_0x2b49550 .part/pv L_0x2b49410, 20, 1, 32;
+L_0x2b495f0 .part v0x2960210_0, 2, 1;
+L_0x2b49690 .part RS_0x7f507e9f0418, 20, 1;
+L_0x2b49780 .part RS_0x7f507e9f0448, 20, 1;
+L_0x2b49870 .part/pv L_0x2b49910, 20, 1, 32;
+L_0x2b4a800 .part RS_0x7f507e9f0478, 19, 1;
+L_0x2b4a8a0 .part RS_0x7f507e9f0b38, 20, 1;
+L_0x2b4a290 .part/pv L_0x2b4a080, 21, 1, 32;
+L_0x2b4a330 .part v0x2960210_0, 0, 1;
+L_0x2b4a460 .part v0x2960210_0, 1, 1;
+L_0x2b4a590 .part RS_0x7f507e9e4aa8, 21, 1;
+L_0x2b4a630 .part RS_0x7f507e9e4aa8, 21, 1;
+L_0x2b4a6d0 .part RS_0x7f507e9da848, 21, 1;
+L_0x2b4a990 .part RS_0x7f507e9f0178, 21, 1;
+L_0x2b4b270 .part/pv L_0x2b4b060, 21, 1, 32;
+L_0x2b4b310 .part v0x2960210_0, 0, 1;
+L_0x2b4b440 .part v0x2960210_0, 1, 1;
+L_0x2b4b570 .part RS_0x7f507e9dde78, 21, 1;
+L_0x2b4b610 .part RS_0x7f507e9dde78, 21, 1;
+L_0x2b4c4c0 .part RS_0x7f507e9da848, 21, 1;
+L_0x2b4c5b0 .part RS_0x7f507e9da848, 21, 1;
+L_0x2b4b730 .part/pv L_0x2b32050, 21, 1, 32;
+L_0x2b4b7d0 .part v0x2960210_0, 2, 1;
+L_0x2b4b870 .part RS_0x7f507e9f0418, 21, 1;
+L_0x2b4b960 .part RS_0x7f507e9f0448, 21, 1;
+L_0x2b4ba50 .part/pv L_0x2b32190, 21, 1, 32;
+L_0x2b4bbd0 .part RS_0x7f507e9f0478, 20, 1;
+L_0x2b4bc70 .part RS_0x7f507e9f0b38, 21, 1;
+L_0x2b4ddb0 .part/pv L_0x2b4c3b0, 22, 1, 32;
+L_0x2b4ceb0 .part v0x2960210_0, 0, 1;
+L_0x2b4cfe0 .part v0x2960210_0, 1, 1;
+L_0x2b4d110 .part RS_0x7f507e9e4aa8, 22, 1;
+L_0x2b4d1b0 .part RS_0x7f507e9e4aa8, 22, 1;
+L_0x2b4d250 .part RS_0x7f507e9da848, 22, 1;
+L_0x2b4d340 .part RS_0x7f507e9f0178, 22, 1;
+L_0x2b4ec60 .part/pv L_0x2b4da20, 22, 1, 32;
+L_0x2b4ed00 .part v0x2960210_0, 0, 1;
+L_0x2b4de50 .part v0x2960210_0, 1, 1;
+L_0x2b4df80 .part RS_0x7f507e9dde78, 22, 1;
+L_0x2b4e020 .part RS_0x7f507e9dde78, 22, 1;
+L_0x2b4e0c0 .part RS_0x7f507e9da848, 22, 1;
+L_0x2b4e160 .part RS_0x7f507e9da848, 22, 1;
+L_0x2b4e660 .part/pv L_0x2b4e520, 22, 1, 32;
+L_0x2b4e700 .part v0x2960210_0, 2, 1;
+L_0x2b4e7a0 .part RS_0x7f507e9f0418, 22, 1;
+L_0x2b4e890 .part RS_0x7f507e9f0448, 22, 1;
+L_0x2b4e980 .part/pv L_0x2b4ea20, 22, 1, 32;
+L_0x2b4eb60 .part RS_0x7f507e9f0478, 21, 1;
+L_0x2b4fca0 .part RS_0x7f507e9f0b38, 22, 1;
+L_0x2b4f690 .part/pv L_0x2b4f480, 23, 1, 32;
+L_0x2b4f730 .part v0x2960210_0, 0, 1;
+L_0x2b4f860 .part v0x2960210_0, 1, 1;
+L_0x2b4f990 .part RS_0x7f507e9e4aa8, 23, 1;
+L_0x2b4fa30 .part RS_0x7f507e9e4aa8, 23, 1;
+L_0x2b4fad0 .part RS_0x7f507e9da848, 23, 1;
+L_0x2b4fbc0 .part RS_0x7f507e9f0178, 23, 1;
+L_0x2b51460 .part/pv L_0x2b51250, 23, 1, 32;
+L_0x2b4fd40 .part v0x2960210_0, 0, 1;
+L_0x2b4fe70 .part v0x2960210_0, 1, 1;
+L_0x2b4ffa0 .part RS_0x7f507e9dde78, 23, 1;
+L_0x2b50040 .part RS_0x7f507e9dde78, 23, 1;
+L_0x2b500e0 .part RS_0x7f507e9da848, 23, 1;
+L_0x2b501d0 .part RS_0x7f507e9da848, 23, 1;
+L_0x2b506d0 .part/pv L_0x2b50590, 23, 1, 32;
+L_0x2b50770 .part v0x2960210_0, 2, 1;
+L_0x2b50810 .part RS_0x7f507e9f0418, 23, 1;
+L_0x2b50900 .part RS_0x7f507e9f0448, 23, 1;
+L_0x2b509f0 .part/pv L_0x2b50a90, 23, 1, 32;
+L_0x2b52410 .part RS_0x7f507e9f0478, 22, 1;
+L_0x2b51500 .part RS_0x7f507e9f0b38, 23, 1;
+L_0x2b51e50 .part/pv L_0x2b51c40, 24, 1, 32;
+L_0x2b51ef0 .part v0x2960210_0, 0, 1;
+L_0x2b52020 .part v0x2960210_0, 1, 1;
+L_0x2b52150 .part RS_0x7f507e9e4aa8, 24, 1;
+L_0x2b521f0 .part RS_0x7f507e9e4aa8, 24, 1;
+L_0x2b52290 .part RS_0x7f507e9da848, 24, 1;
+L_0x2b53400 .part RS_0x7f507e9f0178, 24, 1;
+L_0x2b52cd0 .part/pv L_0x2b52ac0, 24, 1, 32;
+L_0x2b52d70 .part v0x2960210_0, 0, 1;
+L_0x2b52ea0 .part v0x2960210_0, 1, 1;
+L_0x2b52fd0 .part RS_0x7f507e9dde78, 24, 1;
+L_0x2b53070 .part RS_0x7f507e9dde78, 24, 1;
+L_0x2b53110 .part RS_0x7f507e9da848, 24, 1;
+L_0x2b53200 .part RS_0x7f507e9da848, 24, 1;
+L_0x2b54750 .part/pv L_0x2b54610, 24, 1, 32;
+L_0x2b534a0 .part v0x2960210_0, 2, 1;
+L_0x2b53540 .part RS_0x7f507e9f0418, 24, 1;
+L_0x2b53630 .part RS_0x7f507e9f0448, 24, 1;
+L_0x2b53720 .part/pv L_0x2b537c0, 24, 1, 32;
+L_0x2b53900 .part RS_0x7f507e9f0478, 23, 1;
+L_0x2b539a0 .part RS_0x7f507e9f0b38, 24, 1;
+L_0x2b542f0 .part/pv L_0x2b540e0, 25, 1, 32;
+L_0x2b54390 .part v0x2960210_0, 0, 1;
+L_0x2b547f0 .part v0x2960210_0, 1, 1;
+L_0x2b54920 .part RS_0x7f507e9e4aa8, 25, 1;
+L_0x2b549c0 .part RS_0x7f507e9e4aa8, 25, 1;
+L_0x2b54a60 .part RS_0x7f507e9da848, 25, 1;
+L_0x2b54b50 .part RS_0x7f507e9f0178, 25, 1;
+L_0x2b554a0 .part/pv L_0x2b55290, 25, 1, 32;
+L_0x2b55540 .part v0x2960210_0, 0, 1;
+L_0x2b55670 .part v0x2960210_0, 1, 1;
+L_0x2b56870 .part RS_0x7f507e9dde78, 25, 1;
+L_0x2b56910 .part RS_0x7f507e9dde78, 25, 1;
+L_0x2b55850 .part RS_0x7f507e9da848, 25, 1;
+L_0x2b55940 .part RS_0x7f507e9da848, 25, 1;
+L_0x2b55e40 .part/pv L_0x2b55d00, 25, 1, 32;
+L_0x2b55ee0 .part v0x2960210_0, 2, 1;
+L_0x2b55f80 .part RS_0x7f507e9f0418, 25, 1;
+L_0x2b56070 .part RS_0x7f507e9f0448, 25, 1;
+L_0x2b56160 .part/pv L_0x2b56200, 25, 1, 32;
+L_0x2b56340 .part RS_0x7f507e9f0478, 24, 1;
+L_0x2b563e0 .part RS_0x7f507e9f0b38, 25, 1;
+L_0x2b57f10 .part/pv L_0x2b57d00, 26, 1, 32;
+L_0x2b569b0 .part v0x2960210_0, 0, 1;
+L_0x2b56ae0 .part v0x2960210_0, 1, 1;
+L_0x2b56c10 .part RS_0x7f507e9e4aa8, 26, 1;
+L_0x2b56cb0 .part RS_0x7f507e9e4aa8, 26, 1;
+L_0x2b56d50 .part RS_0x7f507e9da848, 26, 1;
+L_0x2b56e40 .part RS_0x7f507e9f0178, 26, 1;
+L_0x2b57790 .part/pv L_0x2b57580, 26, 1, 32;
+L_0x2b57830 .part v0x2960210_0, 0, 1;
+L_0x2b57960 .part v0x2960210_0, 1, 1;
+L_0x2b59100 .part RS_0x7f507e9dde78, 26, 1;
+L_0x2b57fb0 .part RS_0x7f507e9dde78, 26, 1;
+L_0x2b58050 .part RS_0x7f507e9da848, 26, 1;
+L_0x2b58140 .part RS_0x7f507e9da848, 26, 1;
+L_0x2b58640 .part/pv L_0x2b58500, 26, 1, 32;
+L_0x2b586e0 .part v0x2960210_0, 2, 1;
+L_0x2b58780 .part RS_0x7f507e9f0418, 26, 1;
+L_0x2b58870 .part RS_0x7f507e9f0448, 26, 1;
+L_0x2b58960 .part/pv L_0x2b58a00, 26, 1, 32;
+L_0x2b58b40 .part RS_0x7f507e9f0478, 25, 1;
+L_0x2b58be0 .part RS_0x7f507e9f0b38, 26, 1;
+L_0x2b5a7b0 .part/pv L_0x2b5a5a0, 27, 1, 32;
+L_0x2b5a850 .part v0x2960210_0, 0, 1;
+L_0x2b591a0 .part v0x2960210_0, 1, 1;
+L_0x2b592d0 .part RS_0x7f507e9e4aa8, 27, 1;
+L_0x2b59370 .part RS_0x7f507e9e4aa8, 27, 1;
+L_0x2b59410 .part RS_0x7f507e9da848, 27, 1;
+L_0x2b59500 .part RS_0x7f507e9f0178, 27, 1;
+L_0x2b59e50 .part/pv L_0x2b59c40, 27, 1, 32;
+L_0x2b59ef0 .part v0x2960210_0, 0, 1;
+L_0x2b5a020 .part v0x2960210_0, 1, 1;
+L_0x2b5a150 .part RS_0x7f507e9dde78, 27, 1;
+L_0x2b5a1f0 .part RS_0x7f507e9dde78, 27, 1;
+L_0x2b5bb00 .part RS_0x7f507e9da848, 27, 1;
+L_0x2b5bbf0 .part RS_0x7f507e9da848, 27, 1;
+L_0x2b5ad30 .part/pv L_0x2b5abf0, 27, 1, 32;
+L_0x2b5add0 .part v0x2960210_0, 2, 1;
+L_0x2b5ae70 .part RS_0x7f507e9f0418, 27, 1;
+L_0x2b5af60 .part RS_0x7f507e9f0448, 27, 1;
+L_0x2b5b050 .part/pv L_0x2b5b0f0, 27, 1, 32;
+L_0x2b5b230 .part RS_0x7f507e9f0478, 26, 1;
+L_0x2b5b2d0 .part RS_0x7f507e9f0b38, 27, 1;
+L_0x2b5d020 .part/pv L_0x2b5ba70, 28, 1, 32;
+L_0x2b5bce0 .part v0x2960210_0, 0, 1;
+L_0x2b5be10 .part v0x2960210_0, 1, 1;
+L_0x2b5bf40 .part RS_0x7f507e9e4aa8, 28, 1;
+L_0x2b5bfe0 .part RS_0x7f507e9e4aa8, 28, 1;
+L_0x2b5c080 .part RS_0x7f507e9da848, 28, 1;
+L_0x2b5c170 .part RS_0x7f507e9f0178, 28, 1;
+L_0x2b5cac0 .part/pv L_0x2b5c8b0, 28, 1, 32;
+L_0x2b5cb60 .part v0x2960210_0, 0, 1;
+L_0x2b5cc90 .part v0x2960210_0, 1, 1;
+L_0x2b5cdc0 .part RS_0x7f507e9dde78, 28, 1;
+L_0x2b5e2e0 .part RS_0x7f507e9dde78, 28, 1;
+L_0x2b5e380 .part RS_0x7f507e9da848, 28, 1;
+L_0x2b5d0c0 .part RS_0x7f507e9da848, 28, 1;
+L_0x2b5d580 .part/pv L_0x2b5d440, 28, 1, 32;
+L_0x2b5d620 .part v0x2960210_0, 2, 1;
+L_0x2b5d6c0 .part RS_0x7f507e9f0418, 28, 1;
+L_0x2b5d7b0 .part RS_0x7f507e9f0448, 28, 1;
+L_0x2b5d8a0 .part/pv L_0x2b5d940, 28, 1, 32;
+L_0x2b5da80 .part RS_0x7f507e9f0478, 27, 1;
+L_0x2b5db20 .part RS_0x7f507e9f0b38, 28, 1;
+L_0x2b5f890 .part/pv L_0x2b5e260, 29, 1, 32;
+L_0x2b5f930 .part v0x2960210_0, 0, 1;
+L_0x2b5e470 .part v0x2960210_0, 1, 1;
+L_0x2b5e5a0 .part RS_0x7f507e9e4aa8, 29, 1;
+L_0x2b5e640 .part RS_0x7f507e9e4aa8, 29, 1;
+L_0x2b5e6e0 .part RS_0x7f507e9da848, 29, 1;
+L_0x2b5e7d0 .part RS_0x7f507e9f0178, 29, 1;
+L_0x2b5f150 .part/pv L_0x2b5ef40, 29, 1, 32;
+L_0x2b5f1f0 .part v0x2960210_0, 0, 1;
+L_0x2b5f320 .part v0x2960210_0, 1, 1;
+L_0x2b5f450 .part RS_0x7f507e9dde78, 29, 1;
+L_0x2b5f4f0 .part RS_0x7f507e9dde78, 29, 1;
+L_0x2b5f590 .part RS_0x7f507e9da848, 29, 1;
+L_0x2b60d30 .part RS_0x7f507e9da848, 29, 1;
+L_0x2b5fdd0 .part/pv L_0x2b5fc90, 29, 1, 32;
+L_0x2b5fe70 .part v0x2960210_0, 2, 1;
+L_0x2b5ff10 .part RS_0x7f507e9f0418, 29, 1;
+L_0x2b60000 .part RS_0x7f507e9f0448, 29, 1;
+L_0x2b600f0 .part/pv L_0x2b60190, 29, 1, 32;
+L_0x2b602d0 .part RS_0x7f507e9f0478, 28, 1;
+L_0x2b60370 .part RS_0x7f507e9f0b38, 29, 1;
+L_0x2b62130 .part/pv L_0x2b60b40, 30, 1, 32;
+L_0x2b60dd0 .part v0x2960210_0, 0, 1;
+L_0x2b60f00 .part v0x2960210_0, 1, 1;
+L_0x2b61030 .part RS_0x7f507e9e4aa8, 30, 1;
+L_0x2b610d0 .part RS_0x7f507e9e4aa8, 30, 1;
+L_0x2b61170 .part RS_0x7f507e9da848, 30, 1;
+L_0x2b61260 .part RS_0x7f507e9f0178, 30, 1;
+L_0x2b61b80 .part/pv L_0x2b61970, 30, 1, 32;
+L_0x2b61c20 .part v0x2960210_0, 0, 1;
+L_0x2b61d50 .part v0x2960210_0, 1, 1;
+L_0x2b61e80 .part RS_0x7f507e9dde78, 30, 1;
+L_0x2b61f20 .part RS_0x7f507e9dde78, 30, 1;
+L_0x2b61fc0 .part RS_0x7f507e9da848, 30, 1;
+L_0x2b63550 .part RS_0x7f507e9da848, 30, 1;
+L_0x2b63a50 .part/pv L_0x2b63910, 30, 1, 32;
+L_0x2b621d0 .part v0x2960210_0, 2, 1;
+L_0x2b62270 .part RS_0x7f507e9f0418, 30, 1;
+L_0x2b62360 .part RS_0x7f507e9f0448, 30, 1;
+L_0x2b62450 .part/pv L_0x2b624f0, 30, 1, 32;
+L_0x2b62630 .part RS_0x7f507e9f0478, 29, 1;
+L_0x2b626d0 .part RS_0x7f507e9f0b38, 30, 1;
+L_0x2b62ff0 .part/pv L_0x2b62de0, 31, 1, 32;
+L_0x2b63090 .part v0x2960210_0, 0, 1;
+L_0x2b631c0 .part v0x2960210_0, 1, 1;
+L_0x2b632f0 .part RS_0x7f507e9e4aa8, 31, 1;
+L_0x2b63390 .part RS_0x7f507e9e4aa8, 31, 1;
+L_0x2b63430 .part RS_0x7f507e9da848, 31, 1;
+L_0x2b64ee0 .part RS_0x7f507e9f0178, 31, 1;
+L_0x2b65a00 .part/pv L_0x2b657f0, 31, 1, 32;
+L_0x2b63af0 .part v0x2960210_0, 0, 1;
+L_0x2b63c20 .part v0x2960210_0, 1, 1;
+L_0x2b63d50 .part RS_0x7f507e9dde78, 31, 1;
+L_0x2b63df0 .part RS_0x7f507e9dde78, 31, 1;
+L_0x2b63e90 .part RS_0x7f507e9da848, 31, 1;
+L_0x2b63f80 .part RS_0x7f507e9da848, 31, 1;
+L_0x2b64480 .part/pv L_0x2b64340, 31, 1, 32;
+L_0x2b64520 .part v0x2960210_0, 2, 1;
+L_0x2b645c0 .part RS_0x7f507e9f0418, 31, 1;
+L_0x2b646b0 .part RS_0x7f507e9f0448, 31, 1;
+L_0x2b647a0 .part/pv L_0x2b64840, 31, 1, 32;
+L_0x2b64980 .part RS_0x7f507e9f0478, 30, 1;
+L_0x2b64a20 .part RS_0x7f507e9f0b38, 31, 1;
+L_0x2c13460 .part/pv L_0x2c13280, 0, 1, 32;
+L_0x2b65aa0 .part v0x2960210_0, 0, 1;
+L_0x2b65bd0 .part v0x2960210_0, 1, 1;
+L_0x2b65d00 .part RS_0x7f507e9e4aa8, 0, 1;
+L_0x2b65da0 .part RS_0x7f507e9e4aa8, 0, 1;
+L_0x2b65e40 .part RS_0x7f507e9da848, 0, 1;
+L_0x2b65f30 .part RS_0x7f507e9f0178, 0, 1;
+L_0x2b66730 .part/pv L_0x2b66550, 0, 1, 32;
+L_0x2b667d0 .part v0x2960210_0, 0, 1;
+L_0x2b66900 .part v0x2960210_0, 1, 1;
+L_0x2b66a30 .part RS_0x7f507e9dde78, 0, 1;
+L_0x2b66ad0 .part RS_0x7f507e9dde78, 0, 1;
+L_0x2b66b70 .part RS_0x7f507e9da848, 0, 1;
+L_0x2b66c60 .part RS_0x7f507e9da848, 0, 1;
+L_0x2b4c8d0 .part/pv L_0x2b4c790, 0, 1, 32;
+L_0x2b3fbf0 .part v0x2960210_0, 2, 1;
+L_0x2b3fc90 .part RS_0x7f507e9f0418, 0, 1;
+L_0x2b3fd80 .part RS_0x7f507e9f0448, 0, 1;
+L_0x2b3fe70 .part/pv L_0x2b3ff10, 0, 1, 32;
+L_0x2c14570 .part RS_0x7f507e9f0b38, 0, 1;
+L_0x2c14610 .part RS_0x7f507e9f0b38, 0, 1;
+L_0x2c14810 .part RS_0x7f507e9f0478, 31, 1;
+S_0x2753240 .scope module, "test" "SLT32" 3 52, 3 298, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x24071c8 .param/l "size" 3 330, +C4<0100000>;
+L_0x2ba8c20/d .functor NOT 1, L_0x2ba8d30, C4<0>, C4<0>, C4<0>;
+L_0x2ba8c20 .delay (10000,10000,10000) L_0x2ba8c20/d;
+L_0x2ba8dd0/d .functor AND 1, L_0x2ba8f10, L_0x2ba8fb0, L_0x2ba8c20, C4<1>;
+L_0x2ba8dd0 .delay (20000,20000,20000) L_0x2ba8dd0/d;
+L_0x2b886f0/d .functor OR 1, L_0x2baa410, C4<0>, C4<0>, C4<0>;
+L_0x2b886f0 .delay (20000,20000,20000) L_0x2b886f0/d;
+L_0x2bab990/d .functor XOR 1, RS_0x7f507e9e4bc8, L_0x2babac0, C4<0>, C4<0>;
+L_0x2bab990 .delay (40000,40000,40000) L_0x2bab990/d;
+L_0x2babb60/d .functor NOT 1, RS_0x7f507e9e4bf8, C4<0>, C4<0>, C4<0>;
+L_0x2babb60 .delay (10000,10000,10000) L_0x2babb60/d;
+L_0x2ba6870/d .functor NOT 1, L_0x2ba6970, C4<0>, C4<0>, C4<0>;
+L_0x2ba6870 .delay (10000,10000,10000) L_0x2ba6870/d;
+L_0x2ba6a10/d .functor AND 1, L_0x2babb60, L_0x2b88880, C4<1>, C4<1>;
+L_0x2ba6a10 .delay (20000,20000,20000) L_0x2ba6a10/d;
+L_0x2b88920/d .functor AND 1, RS_0x7f507e9e4bf8, L_0x2ba6870, C4<1>, C4<1>;
+L_0x2b88920 .delay (20000,20000,20000) L_0x2b88920/d;
+L_0x2b88a60/d .functor AND 1, L_0x2ba6a10, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b88a60 .delay (20000,20000,20000) L_0x2b88a60/d;
+L_0x2b88b80/d .functor AND 1, L_0x2b88920, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b88b80 .delay (20000,20000,20000) L_0x2b88b80/d;
+L_0x2bad020/d .functor OR 1, L_0x2b88a60, L_0x2b88b80, C4<0>, C4<0>;
+L_0x2bad020 .delay (20000,20000,20000) L_0x2bad020/d;
+v0x2409470_0 .alias "A", 31 0, v0x295f580_0;
+RS_0x7f507e9f0088/0/0 .resolv tri, L_0x21be620, L_0x2b6a940, L_0x2b6ca60, L_0x2b6ec10;
+RS_0x7f507e9f0088/0/4 .resolv tri, L_0x2b70d10, L_0x2b72e50, L_0x2b75280, L_0x2b77670;
+RS_0x7f507e9f0088/0/8 .resolv tri, L_0x2b79a60, L_0x2b7bd90, L_0x2b7e070, L_0x2b80360;
+RS_0x7f507e9f0088/0/12 .resolv tri, L_0x2b824d0, L_0x2b84860, L_0x2b869b0, L_0x2b88ce0;
+RS_0x7f507e9f0088/0/16 .resolv tri, L_0x2b68120, L_0x2b8da20, L_0x2b8fbd0, L_0x2b91ca0;
+RS_0x7f507e9f0088/0/20 .resolv tri, L_0x2b93e90, L_0x2b95f80, L_0x2b96f20, L_0x2b9a640;
+RS_0x7f507e9f0088/0/24 .resolv tri, L_0x2b9adf0, L_0x2b9e880, L_0x2b9f050, L_0x2ba18c0;
+RS_0x7f507e9f0088/0/28 .resolv tri, L_0x2ba3930, L_0x2ba7160, L_0x2ba7910, L_0x2baa120;
+RS_0x7f507e9f0088/1/0 .resolv tri, RS_0x7f507e9f0088/0/0, RS_0x7f507e9f0088/0/4, RS_0x7f507e9f0088/0/8, RS_0x7f507e9f0088/0/12;
+RS_0x7f507e9f0088/1/4 .resolv tri, RS_0x7f507e9f0088/0/16, RS_0x7f507e9f0088/0/20, RS_0x7f507e9f0088/0/24, RS_0x7f507e9f0088/0/28;
+RS_0x7f507e9f0088 .resolv tri, RS_0x7f507e9f0088/1/0, RS_0x7f507e9f0088/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2411b80_0 .net8 "AddSubSLTSum", 31 0, RS_0x7f507e9f0088; 32 drivers
+v0x2411c20_0 .alias "B", 31 0, v0x295f6a0_0;
+RS_0x7f507e9f00b8/0/0 .resolv tri, L_0x2b67b10, L_0x2b6a090, L_0x2b6c240, L_0x2b6d2f0;
+RS_0x7f507e9f00b8/0/4 .resolv tri, L_0x2b70540, L_0x2b714b0, L_0x2b74a20, L_0x2b75a90;
+RS_0x7f507e9f00b8/0/8 .resolv tri, L_0x2b79200, L_0x2b7a270, L_0x2b7d820, L_0x2b7eca0;
+RS_0x7f507e9f00b8/0/12 .resolv tri, L_0x2b81cb0, L_0x2b82cf0, L_0x2b86180, L_0x2b87150;
+RS_0x7f507e9f00b8/0/16 .resolv tri, L_0x2b8a840, L_0x2b8bf00, L_0x2b8f390, L_0x2b8fd60;
+RS_0x7f507e9f00b8/0/20 .resolv tri, L_0x2b93630, L_0x2b94020, L_0x2b97d10, L_0x2b986c0;
+RS_0x7f507e9f00b8/0/24 .resolv tri, L_0x2b9bec0, L_0x2b9c880, L_0x2ba00f0, L_0x2ba10c0;
+RS_0x7f507e9f00b8/0/28 .resolv tri, L_0x2ba4500, L_0x2ba54d0, L_0x2ba8a40, L_0x2bab040;
+RS_0x7f507e9f00b8/1/0 .resolv tri, RS_0x7f507e9f00b8/0/0, RS_0x7f507e9f00b8/0/4, RS_0x7f507e9f00b8/0/8, RS_0x7f507e9f00b8/0/12;
+RS_0x7f507e9f00b8/1/4 .resolv tri, RS_0x7f507e9f00b8/0/16, RS_0x7f507e9f00b8/0/20, RS_0x7f507e9f00b8/0/24, RS_0x7f507e9f00b8/0/28;
+RS_0x7f507e9f00b8 .resolv tri, RS_0x7f507e9f00b8/1/0, RS_0x7f507e9f00b8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x24118d0_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9f00b8; 32 drivers
+v0x2411970_0 .alias "Command", 2 0, v0x295f7a0_0;
+RS_0x7f507e9f00e8/0/0 .resolv tri, L_0x2b67a20, L_0x2b69f30, L_0x2b6c150, L_0x2b6e280;
+RS_0x7f507e9f00e8/0/4 .resolv tri, L_0x2b70450, L_0x2b724a0, L_0x2b74930, L_0x2b76c20;
+RS_0x7f507e9f00e8/0/8 .resolv tri, L_0x2b79110, L_0x2b7b440, L_0x2b7d730, L_0x2b7faa0;
+RS_0x7f507e9f00e8/0/12 .resolv tri, L_0x2b81bc0, L_0x2b83d80, L_0x2b86090, L_0x2b881e0;
+RS_0x7f507e9f00e8/0/16 .resolv tri, L_0x2b8a750, L_0x2b8d0f0, L_0x2b8f2a0, L_0x2b91370;
+RS_0x7f507e9f00e8/0/20 .resolv tri, L_0x2b93540, L_0x2b95640, L_0x2b97c20, L_0x2b99ce0;
+RS_0x7f507e9f00e8/0/24 .resolv tri, L_0x2b9bdd0, L_0x2b9dec0, L_0x2ba0000, L_0x2ba2210;
+RS_0x7f507e9f00e8/0/28 .resolv tri, L_0x2ba4410, L_0x2ba65f0, L_0x2ba8950, L_0x2baaf50;
+RS_0x7f507e9f00e8/1/0 .resolv tri, RS_0x7f507e9f00e8/0/0, RS_0x7f507e9f00e8/0/4, RS_0x7f507e9f00e8/0/8, RS_0x7f507e9f00e8/0/12;
+RS_0x7f507e9f00e8/1/4 .resolv tri, RS_0x7f507e9f00e8/0/16, RS_0x7f507e9f00e8/0/20, RS_0x7f507e9f00e8/0/24, RS_0x7f507e9f00e8/0/28;
+RS_0x7f507e9f00e8 .resolv tri, RS_0x7f507e9f00e8/1/0, RS_0x7f507e9f00e8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x2411620_0 .net8 "NewVal", 31 0, RS_0x7f507e9f00e8; 32 drivers
+v0x24116c0_0 .net "Res0OF1", 0 0, L_0x2b88920; 1 drivers
+v0x2411380_0 .net "Res1OF0", 0 0, L_0x2ba6a10; 1 drivers
+v0x2411420_0 .alias "SLTSum", 31 0, v0x24150b0_0;
+v0x240fa90_0 .alias "SLTflag", 0 0, v0x2415130_0;
+v0x240fb10_0 .net "SLTflag0", 0 0, L_0x2b88a60; 1 drivers
+v0x240f7e0_0 .net "SLTflag1", 0 0, L_0x2b88b80; 1 drivers
+v0x240f880_0 .net "SLTon", 0 0, L_0x2ba8dd0; 1 drivers
+v0x2412da0_0 .net *"_s497", 0 0, L_0x2ba8d30; 1 drivers
+v0x240f530_0 .net *"_s499", 0 0, L_0x2ba8f10; 1 drivers
+v0x240f5d0_0 .net *"_s501", 0 0, L_0x2ba8fb0; 1 drivers
+v0x2412e20_0 .net *"_s521", 0 0, L_0x2baa410; 1 drivers
+v0x240f360_0 .net/s *"_s522", 0 0, C4<0>; 1 drivers
+v0x240f290_0 .net *"_s525", 0 0, L_0x2babac0; 1 drivers
+v0x2417a40_0 .net *"_s527", 0 0, L_0x2ba6970; 1 drivers
+v0x24177a0_0 .net *"_s529", 0 0, L_0x2b88880; 1 drivers
+v0x24179a0_0 .alias "carryin", 31 0, v0x2609fe0_0;
+v0x2417500_0 .alias "carryout", 0 0, v0x2960740_0;
+v0x24176f0_0 .net "nAddSubSLTSum", 0 0, L_0x2ba6870; 1 drivers
+v0x2417270_0 .net "nCmd2", 0 0, L_0x2ba8c20; 1 drivers
+v0x2417440_0 .net "nOF", 0 0, L_0x2babb60; 1 drivers
+v0x24171a0_0 .alias "overflow", 0 0, v0x29608f0_0;
+v0x2415600_0 .alias "subtract", 31 0, v0x25ec920_0;
+L_0x2b67a20 .part/pv L_0x2b67590, 1, 1, 32;
+L_0x2b67b10 .part/pv L_0x2b678e0, 1, 1, 32;
+L_0x2b67c00 .part/pv L_0x2b672c0, 1, 1, 32;
+L_0x2b67cf0 .part v0x295fe90_0, 1, 1;
+L_0x2b67d90 .part v0x2960190_0, 1, 1;
+L_0x2b67ec0 .part RS_0x7f507e9f00b8, 0, 1;
+L_0x21be620 .part/pv L_0x21be4e0, 1, 1, 32;
+L_0x2b687d0 .part RS_0x7f507e9f00e8, 1, 1;
+L_0x2b68d70 .part/pv L_0x2b68c30, 1, 1, 32;
+L_0x2b68e10 .part RS_0x7f507e9f0088, 1, 1;
+L_0x2b68fb0 .part RS_0x7f507e9f0088, 1, 1;
+L_0x2b69f30 .part/pv L_0x2b69aa0, 2, 1, 32;
+L_0x2b6a090 .part/pv L_0x2b69df0, 2, 1, 32;
+L_0x2b6a180 .part/pv L_0x2b697d0, 2, 1, 32;
+L_0x2b6a330 .part v0x295fe90_0, 2, 1;
+L_0x2b6a3d0 .part v0x2960190_0, 2, 1;
+L_0x2b6a590 .part RS_0x7f507e9f00b8, 1, 1;
+L_0x2b6a940 .part/pv L_0x2b6a800, 2, 1, 32;
+L_0x2b6ab10 .part RS_0x7f507e9f00e8, 2, 1;
+L_0x2b6afd0 .part/pv L_0x2b6ae90, 2, 1, 32;
+L_0x2b6aa70 .part RS_0x7f507e9f0088, 2, 1;
+L_0x2b6b170 .part RS_0x7f507e9f0088, 2, 1;
+L_0x2b6c150 .part/pv L_0x2b6bcc0, 3, 1, 32;
+L_0x2b6c240 .part/pv L_0x2b6c010, 3, 1, 32;
+L_0x2b6b260 .part/pv L_0x2b6b9f0, 3, 1, 32;
+L_0x2b6c450 .part v0x295fe90_0, 3, 1;
+L_0x2b6c330 .part v0x2960190_0, 3, 1;
+L_0x2b6c660 .part RS_0x7f507e9f00b8, 2, 1;
+L_0x2b6ca60 .part/pv L_0x2b6c920, 3, 1, 32;
+L_0x2b6cb00 .part RS_0x7f507e9f00e8, 3, 1;
+L_0x2b6d050 .part/pv L_0x2b6cf10, 3, 1, 32;
+L_0x2b6d0f0 .part RS_0x7f507e9f0088, 3, 1;
+L_0x2b6cbf0 .part RS_0x7f507e9f0088, 3, 1;
+L_0x2b6e280 .part/pv L_0x2b6ddf0, 4, 1, 32;
+L_0x2b6d2f0 .part/pv L_0x2b6e140, 4, 1, 32;
+L_0x2b6e490 .part/pv L_0x2b6db20, 4, 1, 32;
+L_0x2b6e370 .part v0x295fe90_0, 4, 1;
+L_0x2b6e6b0 .part v0x2960190_0, 4, 1;
+L_0x2b6e580 .part RS_0x7f507e9f00b8, 3, 1;
+L_0x2b6ec10 .part/pv L_0x2b6ead0, 4, 1, 32;
+L_0x2b6e7e0 .part RS_0x7f507e9f00e8, 4, 1;
+L_0x2b6f2a0 .part/pv L_0x2b6f160, 4, 1, 32;
+L_0x2b6ecb0 .part RS_0x7f507e9f0088, 4, 1;
+L_0x2b6f4a0 .part RS_0x7f507e9f0088, 4, 1;
+L_0x2b70450 .part/pv L_0x2b6ffc0, 5, 1, 32;
+L_0x2b70540 .part/pv L_0x2b70310, 5, 1, 32;
+L_0x2b6f540 .part/pv L_0x2b6fcf0, 5, 1, 32;
+L_0x2b707b0 .part v0x295fe90_0, 5, 1;
+L_0x2b70630 .part v0x2960190_0, 5, 1;
+L_0x2b709e0 .part RS_0x7f507e9f00b8, 4, 1;
+L_0x2b70d10 .part/pv L_0x2b70c20, 5, 1, 32;
+L_0x2b70db0 .part RS_0x7f507e9f00e8, 5, 1;
+L_0x2b71320 .part/pv L_0x2b711e0, 5, 1, 32;
+L_0x2b713c0 .part RS_0x7f507e9f0088, 5, 1;
+L_0x2b70ea0 .part RS_0x7f507e9f0088, 5, 1;
+L_0x2b724a0 .part/pv L_0x2b72010, 6, 1, 32;
+L_0x2b714b0 .part/pv L_0x2b72360, 6, 1, 32;
+L_0x2b715a0 .part/pv L_0x2b71d40, 6, 1, 32;
+L_0x2b72590 .part v0x295fe90_0, 6, 1;
+L_0x2b72630 .part v0x2960190_0, 6, 1;
+L_0x2b72a60 .part RS_0x7f507e9f00b8, 5, 1;
+L_0x2b72e50 .part/pv L_0x2b72cf0, 6, 1, 32;
+L_0x2b6d1e0 .part RS_0x7f507e9f00e8, 6, 1;
+L_0x2b735f0 .part/pv L_0x2b6f090, 6, 1, 32;
+L_0x2b73100 .part RS_0x7f507e9f0088, 6, 1;
+L_0x2b731f0 .part RS_0x7f507e9f0088, 6, 1;
+L_0x2b74930 .part/pv L_0x2b74420, 7, 1, 32;
+L_0x2b74a20 .part/pv L_0x2b747d0, 7, 1, 32;
+L_0x2b73690 .part/pv L_0x2b74150, 7, 1, 32;
+L_0x2b73780 .part v0x295fe90_0, 7, 1;
+L_0x2b74d50 .part v0x2960190_0, 7, 1;
+L_0x2b74df0 .part RS_0x7f507e9f00b8, 6, 1;
+L_0x2b75280 .part/pv L_0x2b75120, 7, 1, 32;
+L_0x2b75320 .part RS_0x7f507e9f00e8, 7, 1;
+L_0x2b75900 .part/pv L_0x2b757a0, 7, 1, 32;
+L_0x2b759a0 .part RS_0x7f507e9f0088, 7, 1;
+L_0x2b75410 .part RS_0x7f507e9f0088, 7, 1;
+L_0x2b76c20 .part/pv L_0x2b76730, 8, 1, 32;
+L_0x2b75a90 .part/pv L_0x2b76ac0, 8, 1, 32;
+L_0x2b75b80 .part/pv L_0x2b76460, 8, 1, 32;
+L_0x2b76fa0 .part v0x295fe90_0, 8, 1;
+L_0x2b77040 .part v0x2960190_0, 8, 1;
+L_0x2b76d10 .part RS_0x7f507e9f00b8, 7, 1;
+L_0x2b77670 .part/pv L_0x2b76f20, 8, 1, 32;
+L_0x2b770e0 .part RS_0x7f507e9f00e8, 8, 1;
+L_0x2b77e40 .part/pv L_0x2b733b0, 8, 1, 32;
+L_0x2b77710 .part RS_0x7f507e9f0088, 8, 1;
+L_0x2b777b0 .part RS_0x7f507e9f0088, 8, 1;
+L_0x2b79110 .part/pv L_0x2b78c20, 9, 1, 32;
+L_0x2b79200 .part/pv L_0x2b78fb0, 9, 1, 32;
+L_0x2b77ee0 .part/pv L_0x2b78950, 9, 1, 32;
+L_0x2b77fd0 .part v0x295fe90_0, 9, 1;
+L_0x2b78070 .part v0x2960190_0, 9, 1;
+L_0x2b795e0 .part RS_0x7f507e9f00b8, 8, 1;
+L_0x2b79a60 .part/pv L_0x2b79560, 9, 1, 32;
+L_0x2b79b00 .part RS_0x7f507e9f00e8, 9, 1;
+L_0x2b7a0e0 .part/pv L_0x2b79fa0, 9, 1, 32;
+L_0x2b7a180 .part RS_0x7f507e9f0088, 9, 1;
+L_0x2b79bf0 .part RS_0x7f507e9f0088, 9, 1;
+L_0x2b7b440 .part/pv L_0x2b7af30, 10, 1, 32;
+L_0x2b7a270 .part/pv L_0x2b7b2e0, 10, 1, 32;
+L_0x2b7a360 .part/pv L_0x2b7ac60, 10, 1, 32;
+L_0x2b7a450 .part v0x295fe90_0, 10, 1;
+L_0x2b7a4f0 .part v0x2960190_0, 10, 1;
+L_0x2b7b530 .part RS_0x7f507e9f00b8, 9, 1;
+L_0x2b7bd90 .part/pv L_0x2b7bc50, 10, 1, 32;
+L_0x2b7b900 .part RS_0x7f507e9f00e8, 10, 1;
+L_0x2b7c410 .part/pv L_0x2b79820, 10, 1, 32;
+L_0x2b7be30 .part RS_0x7f507e9f0088, 10, 1;
+L_0x2b7bf20 .part RS_0x7f507e9f0088, 10, 1;
+L_0x2b7d730 .part/pv L_0x2b7d240, 11, 1, 32;
+L_0x2b7d820 .part/pv L_0x2b7d5d0, 11, 1, 32;
+L_0x2b7c4b0 .part/pv L_0x2b7cf70, 11, 1, 32;
+L_0x2b7c5a0 .part v0x295fe90_0, 11, 1;
+L_0x2b7c640 .part v0x2960190_0, 11, 1;
+L_0x2b7c770 .part RS_0x7f507e9f00b8, 10, 1;
+L_0x2b7e070 .part/pv L_0x2b7df10, 11, 1, 32;
+L_0x2b7e110 .part RS_0x7f507e9f00e8, 11, 1;
+L_0x2b7e700 .part/pv L_0x2b7e5c0, 11, 1, 32;
+L_0x2b7e7a0 .part RS_0x7f507e9f0088, 11, 1;
+L_0x2b72ef0 .part RS_0x7f507e9f0088, 11, 1;
+L_0x2b7faa0 .part/pv L_0x2b7f610, 12, 1, 32;
+L_0x2b7eca0 .part/pv L_0x2b7f960, 12, 1, 32;
+L_0x2b7ed90 .part/pv L_0x2b7f340, 12, 1, 32;
+L_0x2b7ee80 .part v0x295fe90_0, 12, 1;
+L_0x2b7ef20 .part v0x2960190_0, 12, 1;
+L_0x2b7ff90 .part RS_0x7f507e9f00b8, 11, 1;
+L_0x2b80360 .part/pv L_0x2b80220, 12, 1, 32;
+L_0x2b7fb90 .part RS_0x7f507e9f00e8, 12, 1;
+L_0x2b7c370 .part/pv L_0x2b7c210, 12, 1, 32;
+L_0x2b80400 .part RS_0x7f507e9f0088, 12, 1;
+L_0x2b804f0 .part RS_0x7f507e9f0088, 12, 1;
+L_0x2b81bc0 .part/pv L_0x2b81730, 13, 1, 32;
+L_0x2b81cb0 .part/pv L_0x2b81a80, 13, 1, 32;
+L_0x2b80aa0 .part/pv L_0x2b81460, 13, 1, 32;
+L_0x2b80b90 .part v0x295fe90_0, 13, 1;
+L_0x2b80c30 .part v0x2960190_0, 13, 1;
+L_0x2b80d60 .part RS_0x7f507e9f00b8, 12, 1;
+L_0x2b824d0 .part/pv L_0x2b82390, 13, 1, 32;
+L_0x2b82570 .part RS_0x7f507e9f00e8, 13, 1;
+L_0x2b82b60 .part/pv L_0x2b82110, 13, 1, 32;
+L_0x2b82c00 .part RS_0x7f507e9f0088, 13, 1;
+L_0x2b82660 .part RS_0x7f507e9f0088, 13, 1;
+L_0x2b83d80 .part/pv L_0x2b838f0, 14, 1, 32;
+L_0x2b82cf0 .part/pv L_0x2b83c40, 14, 1, 32;
+L_0x2b82de0 .part/pv L_0x2b83620, 14, 1, 32;
+L_0x2b72760 .part v0x295fe90_0, 14, 1;
+L_0x2b84310 .part v0x2960190_0, 14, 1;
+L_0x2b83e70 .part RS_0x7f507e9f00b8, 13, 1;
+L_0x2b84860 .part/pv L_0x2b84180, 14, 1, 32;
+L_0x2b843b0 .part RS_0x7f507e9f00e8, 14, 1;
+L_0x2b84ea0 .part/pv L_0x2b80a30, 14, 1, 32;
+L_0x2b84900 .part RS_0x7f507e9f0088, 14, 1;
+L_0x2b849f0 .part RS_0x7f507e9f0088, 14, 1;
+L_0x2b86090 .part/pv L_0x2b85c00, 15, 1, 32;
+L_0x2b86180 .part/pv L_0x2b85f50, 15, 1, 32;
+L_0x2b84f40 .part/pv L_0x2b85930, 15, 1, 32;
+L_0x2b85030 .part v0x295fe90_0, 15, 1;
+L_0x2b850d0 .part v0x2960190_0, 15, 1;
+L_0x2b85200 .part RS_0x7f507e9f00b8, 14, 1;
+L_0x2b869b0 .part/pv L_0x2b86870, 15, 1, 32;
+L_0x2b86a50 .part RS_0x7f507e9f00e8, 15, 1;
+L_0x2b866e0 .part/pv L_0x2b865a0, 15, 1, 32;
+L_0x2b87060 .part RS_0x7f507e9f0088, 15, 1;
+L_0x2b86b40 .part RS_0x7f507e9f0088, 15, 1;
+L_0x2b881e0 .part/pv L_0x2b87d50, 16, 1, 32;
+L_0x2b87150 .part/pv L_0x2b880a0, 16, 1, 32;
+L_0x2b87240 .part/pv L_0x2b87a80, 16, 1, 32;
+L_0x2b87330 .part v0x295fe90_0, 16, 1;
+L_0x2b873d0 .part v0x2960190_0, 16, 1;
+L_0x2b87500 .part RS_0x7f507e9f00b8, 15, 1;
+L_0x2b88ce0 .part/pv L_0x2b774f0, 16, 1, 32;
+L_0x2b882d0 .part RS_0x7f507e9f00e8, 16, 1;
+L_0x2b895a0 .part/pv L_0x2b84620, 16, 1, 32;
+L_0x2b88d80 .part RS_0x7f507e9f0088, 16, 1;
+L_0x2b88e70 .part RS_0x7f507e9f0088, 16, 1;
+L_0x2b8a750 .part/pv L_0x2b8a2c0, 17, 1, 32;
+L_0x2b8a840 .part/pv L_0x2b8a610, 17, 1, 32;
+L_0x2b89640 .part/pv L_0x2b89ff0, 17, 1, 32;
+L_0x2b89730 .part v0x295fe90_0, 17, 1;
+L_0x2b897d0 .part v0x2960190_0, 17, 1;
+L_0x2b89900 .part RS_0x7f507e9f00b8, 16, 1;
+L_0x2b68120 .part/pv L_0x2b67fc0, 17, 1, 32;
+L_0x2b681c0 .part RS_0x7f507e9f00e8, 17, 1;
+L_0x2b8a930 .part/pv L_0x2b68620, 17, 1, 32;
+L_0x2b8a9d0 .part RS_0x7f507e9f0088, 17, 1;
+L_0x2b8aac0 .part RS_0x7f507e9f0088, 17, 1;
+L_0x2b8d0f0 .part/pv L_0x2b8cc60, 18, 1, 32;
+L_0x2b8bf00 .part/pv L_0x2b8cfb0, 18, 1, 32;
+L_0x2b8bff0 .part/pv L_0x2b8c990, 18, 1, 32;
+L_0x2b8c0e0 .part v0x295fe90_0, 18, 1;
+L_0x2b8c180 .part v0x2960190_0, 18, 1;
+L_0x2b8c2b0 .part RS_0x7f507e9f00b8, 17, 1;
+L_0x2b8da20 .part/pv L_0x2b8d8e0, 18, 1, 32;
+L_0x2b8d1e0 .part RS_0x7f507e9f00e8, 18, 1;
+L_0x2b8e0e0 .part/pv L_0x2b893e0, 18, 1, 32;
+L_0x2b8dac0 .part RS_0x7f507e9f0088, 18, 1;
+L_0x2b8dbb0 .part RS_0x7f507e9f0088, 18, 1;
+L_0x2b8f2a0 .part/pv L_0x2b8ee10, 19, 1, 32;
+L_0x2b8f390 .part/pv L_0x2b8f160, 19, 1, 32;
+L_0x2b8e180 .part/pv L_0x2b8eb40, 19, 1, 32;
+L_0x2b8e270 .part v0x295fe90_0, 19, 1;
+L_0x2b8e310 .part v0x2960190_0, 19, 1;
+L_0x2b8e440 .part RS_0x7f507e9f00b8, 18, 1;
+L_0x2b8fbd0 .part/pv L_0x2b8e730, 19, 1, 32;
+L_0x2b8fc70 .part RS_0x7f507e9f00e8, 19, 1;
+L_0x2b8f910 .part/pv L_0x2b8f7d0, 19, 1, 32;
+L_0x2b8f9b0 .part RS_0x7f507e9f0088, 19, 1;
+L_0x2b903f0 .part RS_0x7f507e9f0088, 19, 1;
+L_0x2b91370 .part/pv L_0x2b90ee0, 20, 1, 32;
+L_0x2b8fd60 .part/pv L_0x2b91230, 20, 1, 32;
+L_0x2b8fe50 .part/pv L_0x2b90c10, 20, 1, 32;
+L_0x2b8ff40 .part v0x295fe90_0, 20, 1;
+L_0x2b8ffe0 .part v0x2960190_0, 20, 1;
+L_0x2b90110 .part RS_0x7f507e9f00b8, 19, 1;
+L_0x2b91ca0 .part/pv L_0x2b91b60, 20, 1, 32;
+L_0x2b91460 .part RS_0x7f507e9f00e8, 20, 1;
+L_0x2b8d4f0 .part/pv L_0x2b8d400, 20, 1, 32;
+L_0x2b92420 .part RS_0x7f507e9f0088, 20, 1;
+L_0x2b924c0 .part RS_0x7f507e9f0088, 20, 1;
+L_0x2b93540 .part/pv L_0x2b930b0, 21, 1, 32;
+L_0x2b93630 .part/pv L_0x2b93400, 21, 1, 32;
+L_0x2b925b0 .part/pv L_0x2b92de0, 21, 1, 32;
+L_0x2b926a0 .part v0x295fe90_0, 21, 1;
+L_0x2b92740 .part v0x2960190_0, 21, 1;
+L_0x2b92870 .part RS_0x7f507e9f00b8, 20, 1;
+L_0x2b93e90 .part/pv L_0x2b92b60, 21, 1, 32;
+L_0x2b93f30 .part RS_0x7f507e9f00e8, 21, 1;
+L_0x2b93bb0 .part/pv L_0x2b93a70, 21, 1, 32;
+L_0x2b93c50 .part RS_0x7f507e9f0088, 21, 1;
+L_0x2b93d40 .part RS_0x7f507e9f0088, 21, 1;
+L_0x2b95640 .part/pv L_0x2b951b0, 22, 1, 32;
+L_0x2b94020 .part/pv L_0x2b95500, 22, 1, 32;
+L_0x2b94110 .part/pv L_0x2b94ee0, 22, 1, 32;
+L_0x2b94200 .part v0x295fe90_0, 22, 1;
+L_0x2b942a0 .part v0x2960190_0, 22, 1;
+L_0x2b943d0 .part RS_0x7f507e9f00b8, 21, 1;
+L_0x2b95f80 .part/pv L_0x2b946e0, 22, 1, 32;
+L_0x2b7e890 .part RS_0x7f507e9f00e8, 22, 1;
+L_0x2b7ea10 .part/pv L_0x2b95cd0, 22, 1, 32;
+L_0x2b7eab0 .part RS_0x7f507e9f0088, 22, 1;
+L_0x2b7eba0 .part RS_0x7f507e9f0088, 22, 1;
+L_0x2b97c20 .part/pv L_0x2b97790, 23, 1, 32;
+L_0x2b97d10 .part/pv L_0x2b97ae0, 23, 1, 32;
+L_0x2b96830 .part/pv L_0x2b974c0, 23, 1, 32;
+L_0x2b96920 .part v0x295fe90_0, 23, 1;
+L_0x2b969c0 .part v0x2960190_0, 23, 1;
+L_0x2b96af0 .part RS_0x7f507e9f00b8, 22, 1;
+L_0x2b96f20 .part/pv L_0x2b96de0, 23, 1, 32;
+L_0x2b985d0 .part RS_0x7f507e9f00e8, 23, 1;
+L_0x2b98290 .part/pv L_0x2b98150, 23, 1, 32;
+L_0x2b98330 .part RS_0x7f507e9f0088, 23, 1;
+L_0x2b98420 .part RS_0x7f507e9f0088, 23, 1;
+L_0x2b99ce0 .part/pv L_0x2b99850, 24, 1, 32;
+L_0x2b986c0 .part/pv L_0x2b99ba0, 24, 1, 32;
+L_0x2b987b0 .part/pv L_0x2b99580, 24, 1, 32;
+L_0x2b988a0 .part v0x295fe90_0, 24, 1;
+L_0x2b98940 .part v0x2960190_0, 24, 1;
+L_0x2b98a70 .part RS_0x7f507e9f00b8, 23, 1;
+L_0x2b9a640 .part/pv L_0x2b98d60, 24, 1, 32;
+L_0x2b99dd0 .part RS_0x7f507e9f00e8, 24, 1;
+L_0x2b95780 .part/pv L_0x2b9a4c0, 24, 1, 32;
+L_0x2b95820 .part RS_0x7f507e9f0088, 24, 1;
+L_0x2b95910 .part RS_0x7f507e9f0088, 24, 1;
+L_0x2b9bdd0 .part/pv L_0x2b9b940, 25, 1, 32;
+L_0x2b9bec0 .part/pv L_0x2b9bc90, 25, 1, 32;
+L_0x2b9a6e0 .part/pv L_0x2b9b670, 25, 1, 32;
+L_0x2b9a7d0 .part v0x295fe90_0, 25, 1;
+L_0x2b9a870 .part v0x2960190_0, 25, 1;
+L_0x2b9a9a0 .part RS_0x7f507e9f00b8, 24, 1;
+L_0x2b9adf0 .part/pv L_0x2b9ac90, 25, 1, 32;
+L_0x2b9ae90 .part RS_0x7f507e9f00e8, 25, 1;
+L_0x2b9c440 .part/pv L_0x2b9c300, 25, 1, 32;
+L_0x2b9c4e0 .part RS_0x7f507e9f0088, 25, 1;
+L_0x2b9c5d0 .part RS_0x7f507e9f0088, 25, 1;
+L_0x2b9dec0 .part/pv L_0x2b9da30, 26, 1, 32;
+L_0x2b9c880 .part/pv L_0x2b9dd80, 26, 1, 32;
+L_0x2b9c970 .part/pv L_0x2b9d760, 26, 1, 32;
+L_0x2b9ca60 .part v0x295fe90_0, 26, 1;
+L_0x2b9cb00 .part v0x2960190_0, 26, 1;
+L_0x2b9cc30 .part RS_0x7f507e9f00b8, 25, 1;
+L_0x2b9e880 .part/pv L_0x2b9cf40, 26, 1, 32;
+L_0x2b9dfb0 .part RS_0x7f507e9f00e8, 26, 1;
+L_0x2b99f10 .part/pv L_0x2b9e6f0, 26, 1, 32;
+L_0x2b99fb0 .part RS_0x7f507e9f0088, 26, 1;
+L_0x2b9a050 .part RS_0x7f507e9f0088, 26, 1;
+L_0x2ba0000 .part/pv L_0x2b9fb70, 27, 1, 32;
+L_0x2ba00f0 .part/pv L_0x2b9fec0, 27, 1, 32;
+L_0x2b9e920 .part/pv L_0x2b9f8a0, 27, 1, 32;
+L_0x2b9ea10 .part v0x295fe90_0, 27, 1;
+L_0x2b9eab0 .part v0x2960190_0, 27, 1;
+L_0x2b9ebe0 .part RS_0x7f507e9f00b8, 26, 1;
+L_0x2b9f050 .part/pv L_0x2b9eef0, 27, 1, 32;
+L_0x2b9f0f0 .part RS_0x7f507e9f00e8, 27, 1;
+L_0x2ba0f30 .part/pv L_0x2ba0df0, 27, 1, 32;
+L_0x2ba0fd0 .part RS_0x7f507e9f0088, 27, 1;
+L_0x2ba01e0 .part RS_0x7f507e9f0088, 27, 1;
+L_0x2ba2210 .part/pv L_0x2ba1d80, 28, 1, 32;
+L_0x2ba10c0 .part/pv L_0x2ba20d0, 28, 1, 32;
+L_0x2ba11b0 .part/pv L_0x2ba1ab0, 28, 1, 32;
+L_0x2ba12a0 .part v0x295fe90_0, 28, 1;
+L_0x2ba1340 .part v0x2960190_0, 28, 1;
+L_0x2ba1470 .part RS_0x7f507e9f00b8, 27, 1;
+L_0x2ba18c0 .part/pv L_0x2ba1760, 28, 1, 32;
+L_0x2ba1960 .part RS_0x7f507e9f00e8, 28, 1;
+L_0x2ba3180 .part/pv L_0x2ba3080, 28, 1, 32;
+L_0x2ba2300 .part RS_0x7f507e9f0088, 28, 1;
+L_0x2ba23f0 .part RS_0x7f507e9f0088, 28, 1;
+L_0x2ba4410 .part/pv L_0x2ba3f80, 29, 1, 32;
+L_0x2ba4500 .part/pv L_0x2ba42d0, 29, 1, 32;
+L_0x2ba3220 .part/pv L_0x2ba3cb0, 29, 1, 32;
+L_0x2ba3310 .part v0x295fe90_0, 29, 1;
+L_0x2ba33b0 .part v0x2960190_0, 29, 1;
+L_0x2ba34e0 .part RS_0x7f507e9f00b8, 28, 1;
+L_0x2ba3930 .part/pv L_0x2ba37d0, 29, 1, 32;
+L_0x2ba39d0 .part RS_0x7f507e9f00e8, 29, 1;
+L_0x2ba5340 .part/pv L_0x2ba5200, 29, 1, 32;
+L_0x2ba53e0 .part RS_0x7f507e9f0088, 29, 1;
+L_0x2ba45f0 .part RS_0x7f507e9f0088, 29, 1;
+L_0x2ba65f0 .part/pv L_0x2ba6160, 30, 1, 32;
+L_0x2ba54d0 .part/pv L_0x2ba64b0, 30, 1, 32;
+L_0x2ba55c0 .part/pv L_0x2ba5ed0, 30, 1, 32;
+L_0x2b82ed0 .part v0x295fe90_0, 30, 1;
+L_0x2b82f70 .part v0x2960190_0, 30, 1;
+L_0x2ba5b00 .part RS_0x7f507e9f00b8, 29, 1;
+L_0x2ba7160 .part/pv L_0x2ba5df0, 30, 1, 32;
+L_0x2ba66e0 .part RS_0x7f507e9f00e8, 30, 1;
+L_0x2ba6f40 .part/pv L_0x2ba6e00, 30, 1, 32;
+L_0x2ba6fe0 .part RS_0x7f507e9f0088, 30, 1;
+L_0x2ba2d70 .part RS_0x7f507e9f0088, 30, 1;
+L_0x2ba8950 .part/pv L_0x2ba84c0, 31, 1, 32;
+L_0x2ba8a40 .part/pv L_0x2ba8810, 31, 1, 32;
+L_0x2ba7200 .part/pv L_0x2ba81f0, 31, 1, 32;
+L_0x2ba72f0 .part v0x295fe90_0, 31, 1;
+L_0x2ba7390 .part v0x2960190_0, 31, 1;
+L_0x2ba74c0 .part RS_0x7f507e9f00b8, 30, 1;
+L_0x2ba7910 .part/pv L_0x2ba77d0, 31, 1, 32;
+L_0x2ba79b0 .part RS_0x7f507e9f00e8, 31, 1;
+L_0x2ba9860 .part/pv L_0x2ba9720, 31, 1, 32;
+L_0x2ba9900 .part RS_0x7f507e9f0088, 31, 1;
+L_0x2ba8b30 .part RS_0x7f507e9f0088, 31, 1;
+L_0x2ba8d30 .part v0x2960210_0, 2, 1;
+L_0x2ba8f10 .part v0x2960210_0, 0, 1;
+L_0x2ba8fb0 .part v0x2960210_0, 1, 1;
+L_0x2baaf50 .part/pv L_0x2baaac0, 0, 1, 32;
+L_0x2bab040 .part/pv L_0x2baae10, 0, 1, 32;
+L_0x2ba99f0 .part/pv L_0x2baa7f0, 0, 1, 32;
+L_0x2ba9ae0 .part v0x295fe90_0, 0, 1;
+L_0x2ba9b80 .part v0x2960190_0, 0, 1;
+L_0x2ba9cb0 .part RS_0x7f507e9e4c28, 0, 1;
+L_0x2baa120 .part/pv L_0x2ba9fc0, 0, 1, 32;
+L_0x2baa1c0 .part RS_0x7f507e9f00e8, 0, 1;
+L_0x2baa410 .part RS_0x7f507e9f00b8, 31, 1;
+L_0x2babac0 .part RS_0x7f507e9f00b8, 30, 1;
+L_0x2ba6970 .part RS_0x7f507e9f0088, 31, 1;
+L_0x2b88880 .part RS_0x7f507e9f00e8, 31, 1;
+L_0x2bad4c0 .part/pv L_0x2bad380, 0, 1, 32;
+L_0x2b64fd0 .part RS_0x7f507e9f0088, 0, 1;
+S_0x23f9f90 .scope module, "attempt2" "MiddleAddSubSLT" 3 326, 3 189, S_0x2753240;
+ .timescale -9 -12;
+L_0x2ba90a0/d .functor NOT 1, L_0x2ba9b80, C4<0>, C4<0>, C4<0>;
+L_0x2ba90a0 .delay (10000,10000,10000) L_0x2ba90a0/d;
+L_0x2baa6b0/d .functor NOT 1, L_0x2baa750, C4<0>, C4<0>, C4<0>;
+L_0x2baa6b0 .delay (10000,10000,10000) L_0x2baa6b0/d;
+L_0x2baa7f0/d .functor AND 1, L_0x2baa930, L_0x2baa6b0, C4<1>, C4<1>;
+L_0x2baa7f0 .delay (20000,20000,20000) L_0x2baa7f0/d;
+L_0x2baa9d0/d .functor XOR 1, L_0x2ba9ae0, L_0x2baa4c0, C4<0>, C4<0>;
+L_0x2baa9d0 .delay (40000,40000,40000) L_0x2baa9d0/d;
+L_0x2baaac0/d .functor XOR 1, L_0x2baa9d0, L_0x2ba9cb0, C4<0>, C4<0>;
+L_0x2baaac0 .delay (40000,40000,40000) L_0x2baaac0/d;
+L_0x2baabb0/d .functor AND 1, L_0x2ba9ae0, L_0x2baa4c0, C4<1>, C4<1>;
+L_0x2baabb0 .delay (20000,20000,20000) L_0x2baabb0/d;
+L_0x2baad20/d .functor AND 1, L_0x2baa9d0, L_0x2ba9cb0, C4<1>, C4<1>;
+L_0x2baad20 .delay (20000,20000,20000) L_0x2baad20/d;
+L_0x2baae10/d .functor OR 1, L_0x2baabb0, L_0x2baad20, C4<0>, C4<0>;
+L_0x2baae10 .delay (20000,20000,20000) L_0x2baae10/d;
+v0x23fb500_0 .net "A", 0 0, L_0x2ba9ae0; 1 drivers
+v0x23f7bf0_0 .net "AandB", 0 0, L_0x2baabb0; 1 drivers
+v0x23f7c90_0 .net "AddSubSLTSum", 0 0, L_0x2baaac0; 1 drivers
+v0x23f7950_0 .net "AxorB", 0 0, L_0x2baa9d0; 1 drivers
+v0x23f79f0_0 .net "B", 0 0, L_0x2ba9b80; 1 drivers
+v0x23ff800_0 .net "BornB", 0 0, L_0x2baa4c0; 1 drivers
+v0x23ff8c0_0 .net "CINandAxorB", 0 0, L_0x2baad20; 1 drivers
+v0x23fd770_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x23fd7f0_0 .net *"_s3", 0 0, L_0x2baa750; 1 drivers
+v0x2405660_0 .net *"_s5", 0 0, L_0x2baa930; 1 drivers
+v0x2405700_0 .net "carryin", 0 0, L_0x2ba9cb0; 1 drivers
+v0x2403570_0 .net "carryout", 0 0, L_0x2baae10; 1 drivers
+v0x2403610_0 .net "nB", 0 0, L_0x2ba90a0; 1 drivers
+v0x240b4c0_0 .net "nCmd2", 0 0, L_0x2baa6b0; 1 drivers
+v0x24093d0_0 .net "subtract", 0 0, L_0x2baa7f0; 1 drivers
+L_0x2baa610 .part v0x2960210_0, 0, 1;
+L_0x2baa750 .part v0x2960210_0, 2, 1;
+L_0x2baa930 .part v0x2960210_0, 0, 1;
+S_0x23f9ce0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23f9f90;
+ .timescale -9 -12;
+L_0x2ba9270/d .functor NOT 1, L_0x2baa610, C4<0>, C4<0>, C4<0>;
+L_0x2ba9270 .delay (10000,10000,10000) L_0x2ba9270/d;
+L_0x2ba9350/d .functor AND 1, L_0x2ba9b80, L_0x2ba9270, C4<1>, C4<1>;
+L_0x2ba9350 .delay (20000,20000,20000) L_0x2ba9350/d;
+L_0x2ba9480/d .functor AND 1, L_0x2ba90a0, L_0x2baa610, C4<1>, C4<1>;
+L_0x2ba9480 .delay (20000,20000,20000) L_0x2ba9480/d;
+L_0x2baa4c0/d .functor OR 1, L_0x2ba9350, L_0x2ba9480, C4<0>, C4<0>;
+L_0x2baa4c0 .delay (20000,20000,20000) L_0x2baa4c0/d;
+v0x23fa2e0_0 .net "S", 0 0, L_0x2baa610; 1 drivers
+v0x23f9a40_0 .alias "in0", 0 0, v0x23f79f0_0;
+v0x23f9ae0_0 .alias "in1", 0 0, v0x2403610_0;
+v0x23f8150_0 .net "nS", 0 0, L_0x2ba9270; 1 drivers
+v0x23f81f0_0 .net "out0", 0 0, L_0x2ba9350; 1 drivers
+v0x23f7ea0_0 .net "out1", 0 0, L_0x2ba9480; 1 drivers
+v0x23fb460_0 .alias "outfinal", 0 0, v0x23ff800_0;
+S_0x23f2080 .scope module, "setSLTresult" "TwoInMux" 3 327, 3 109, S_0x2753240;
+ .timescale -9 -12;
+L_0x2ba9d50/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba9d50 .delay (10000,10000,10000) L_0x2ba9d50/d;
+L_0x2ba9df0/d .functor AND 1, L_0x2baa1c0, L_0x2ba9d50, C4<1>, C4<1>;
+L_0x2ba9df0 .delay (20000,20000,20000) L_0x2ba9df0/d;
+L_0x2ba9f00/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba9f00 .delay (20000,20000,20000) L_0x2ba9f00/d;
+L_0x2ba9fc0/d .functor OR 1, L_0x2ba9df0, L_0x2ba9f00, C4<0>, C4<0>;
+L_0x2ba9fc0 .delay (20000,20000,20000) L_0x2ba9fc0/d;
+v0x23f5640_0 .alias "S", 0 0, v0x240f880_0;
+v0x23f56e0_0 .net "in0", 0 0, L_0x2baa1c0; 1 drivers
+v0x23f1dd0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x23f1e70_0 .net "nS", 0 0, L_0x2ba9d50; 1 drivers
+v0x23f1b30_0 .net "out0", 0 0, L_0x2ba9df0; 1 drivers
+v0x23f1bd0_0 .net "out1", 0 0, L_0x2ba9f00; 1 drivers
+v0x23fa240_0 .net "outfinal", 0 0, L_0x2ba9fc0; 1 drivers
+S_0x23f4170 .scope module, "FinalSLT" "TwoInMux" 3 354, 3 109, S_0x2753240;
+ .timescale -9 -12;
+L_0x2bad150/d .functor NOT 1, L_0x2bad020, C4<0>, C4<0>, C4<0>;
+L_0x2bad150 .delay (10000,10000,10000) L_0x2bad150/d;
+L_0x2bad1f0/d .functor AND 1, L_0x2b64fd0, L_0x2bad150, C4<1>, C4<1>;
+L_0x2bad1f0 .delay (20000,20000,20000) L_0x2bad1f0/d;
+L_0x2bad2e0/d .functor AND 1, L_0x2bad020, L_0x2bad020, C4<1>, C4<1>;
+L_0x2bad2e0 .delay (20000,20000,20000) L_0x2bad2e0/d;
+L_0x2bad380/d .functor OR 1, L_0x2bad1f0, L_0x2bad2e0, C4<0>, C4<0>;
+L_0x2bad380 .delay (20000,20000,20000) L_0x2bad380/d;
+v0x23f44c0_0 .alias "S", 0 0, v0x2415130_0;
+v0x23f3ec0_0 .net "in0", 0 0, L_0x2b64fd0; 1 drivers
+v0x23f3f60_0 .alias "in1", 0 0, v0x2415130_0;
+v0x23f3c20_0 .net "nS", 0 0, L_0x2bad150; 1 drivers
+v0x23f3cc0_0 .net "out0", 0 0, L_0x2bad1f0; 1 drivers
+v0x23f2330_0 .net "out1", 0 0, L_0x2bad2e0; 1 drivers
+v0x23f23d0_0 .net "outfinal", 0 0, L_0x2bad380; 1 drivers
+S_0x23d6ee0 .scope generate, "sltbits[1]" "sltbits[1]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x26424b8 .param/l "i" 3 332, +C4<01>;
+S_0x23dc530 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x23d6ee0;
+ .timescale -9 -12;
+L_0x2b64b10/d .functor NOT 1, L_0x2b67d90, C4<0>, C4<0>, C4<0>;
+L_0x2b64b10 .delay (10000,10000,10000) L_0x2b64b10/d;
+L_0x2b67180/d .functor NOT 1, L_0x2b67220, C4<0>, C4<0>, C4<0>;
+L_0x2b67180 .delay (10000,10000,10000) L_0x2b67180/d;
+L_0x2b672c0/d .functor AND 1, L_0x2b67400, L_0x2b67180, C4<1>, C4<1>;
+L_0x2b672c0 .delay (20000,20000,20000) L_0x2b672c0/d;
+L_0x2b674a0/d .functor XOR 1, L_0x2b67cf0, L_0x2b66f50, C4<0>, C4<0>;
+L_0x2b674a0 .delay (40000,40000,40000) L_0x2b674a0/d;
+L_0x2b67590/d .functor XOR 1, L_0x2b674a0, L_0x2b67ec0, C4<0>, C4<0>;
+L_0x2b67590 .delay (40000,40000,40000) L_0x2b67590/d;
+L_0x2b67680/d .functor AND 1, L_0x2b67cf0, L_0x2b66f50, C4<1>, C4<1>;
+L_0x2b67680 .delay (20000,20000,20000) L_0x2b67680/d;
+L_0x2b677f0/d .functor AND 1, L_0x2b674a0, L_0x2b67ec0, C4<1>, C4<1>;
+L_0x2b677f0 .delay (20000,20000,20000) L_0x2b677f0/d;
+L_0x2b678e0/d .functor OR 1, L_0x2b67680, L_0x2b677f0, C4<0>, C4<0>;
+L_0x2b678e0 .delay (20000,20000,20000) L_0x2b678e0/d;
+v0x23e2180_0 .net "A", 0 0, L_0x2b67cf0; 1 drivers
+v0x23e7f40_0 .net "AandB", 0 0, L_0x2b67680; 1 drivers
+v0x23e7fe0_0 .net "AddSubSLTSum", 0 0, L_0x2b67590; 1 drivers
+v0x23e5e50_0 .net "AxorB", 0 0, L_0x2b674a0; 1 drivers
+v0x23e5ef0_0 .net "B", 0 0, L_0x2b67d90; 1 drivers
+v0x23ee600_0 .net "BornB", 0 0, L_0x2b66f50; 1 drivers
+v0x23ee6c0_0 .net "CINandAxorB", 0 0, L_0x2b677f0; 1 drivers
+v0x23ee350_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x23ee3d0_0 .net *"_s3", 0 0, L_0x2b67220; 1 drivers
+v0x23ee0a0_0 .net *"_s5", 0 0, L_0x2b67400; 1 drivers
+v0x23ee140_0 .net "carryin", 0 0, L_0x2b67ec0; 1 drivers
+v0x23ef820_0 .net "carryout", 0 0, L_0x2b678e0; 1 drivers
+v0x23ef8c0_0 .net "nB", 0 0, L_0x2b64b10; 1 drivers
+v0x23ebcb0_0 .net "nCmd2", 0 0, L_0x2b67180; 1 drivers
+v0x23f4420_0 .net "subtract", 0 0, L_0x2b672c0; 1 drivers
+L_0x2b670e0 .part v0x2960210_0, 0, 1;
+L_0x2b67220 .part v0x2960210_0, 2, 1;
+L_0x2b67400 .part v0x2960210_0, 0, 1;
+S_0x23dace0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23dc530;
+ .timescale -9 -12;
+L_0x2b64ca0/d .functor NOT 1, L_0x2b670e0, C4<0>, C4<0>, C4<0>;
+L_0x2b64ca0 .delay (10000,10000,10000) L_0x2b64ca0/d;
+L_0x2b64d40/d .functor AND 1, L_0x2b67d90, L_0x2b64ca0, C4<1>, C4<1>;
+L_0x2b64d40 .delay (20000,20000,20000) L_0x2b64d40/d;
+L_0x2b64e30/d .functor AND 1, L_0x2b64b10, L_0x2b670e0, C4<1>, C4<1>;
+L_0x2b64e30 .delay (20000,20000,20000) L_0x2b64e30/d;
+L_0x2b66f50/d .functor OR 1, L_0x2b64d40, L_0x2b64e30, C4<0>, C4<0>;
+L_0x2b66f50 .delay (20000,20000,20000) L_0x2b66f50/d;
+v0x23dc850_0 .net "S", 0 0, L_0x2b670e0; 1 drivers
+v0x23daa50_0 .alias "in0", 0 0, v0x23e5ef0_0;
+v0x23daaf0_0 .alias "in1", 0 0, v0x23ef8c0_0;
+v0x23da7c0_0 .net "nS", 0 0, L_0x2b64ca0; 1 drivers
+v0x23da860_0 .net "out0", 0 0, L_0x2b64d40; 1 drivers
+v0x23da540_0 .net "out1", 0 0, L_0x2b64e30; 1 drivers
+v0x23e20e0_0 .alias "outfinal", 0 0, v0x23ee600_0;
+S_0x23d4c60 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x23d6ee0;
+ .timescale -9 -12;
+L_0x2b67f60/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b67f60 .delay (10000,10000,10000) L_0x2b67f60/d;
+L_0x21be350/d .functor AND 1, L_0x2b687d0, L_0x2b67f60, C4<1>, C4<1>;
+L_0x21be350 .delay (20000,20000,20000) L_0x21be350/d;
+L_0x21be440/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x21be440 .delay (20000,20000,20000) L_0x21be440/d;
+L_0x21be4e0/d .functor OR 1, L_0x21be350, L_0x21be440, C4<0>, C4<0>;
+L_0x21be4e0 .delay (20000,20000,20000) L_0x21be4e0/d;
+v0x23d83b0_0 .alias "S", 0 0, v0x240f880_0;
+v0x23d49e0_0 .net "in0", 0 0, L_0x2b687d0; 1 drivers
+v0x23d4a80_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x23dccd0_0 .net "nS", 0 0, L_0x2b67f60; 1 drivers
+v0x23dcd70_0 .net "out0", 0 0, L_0x21be350; 1 drivers
+v0x23dca40_0 .net "out1", 0 0, L_0x21be440; 1 drivers
+v0x23dc7b0_0 .net "outfinal", 0 0, L_0x21be4e0; 1 drivers
+S_0x23d6c50 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x23d6ee0;
+ .timescale -9 -12;
+L_0x2b689b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b689b0 .delay (10000,10000,10000) L_0x2b689b0/d;
+L_0x2b68aa0/d .functor AND 1, L_0x2b68e10, L_0x2b689b0, C4<1>, C4<1>;
+L_0x2b68aa0 .delay (20000,20000,20000) L_0x2b68aa0/d;
+L_0x2b68b90/d .functor AND 1, L_0x2b68fb0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b68b90 .delay (20000,20000,20000) L_0x2b68b90/d;
+L_0x2b68c30/d .functor OR 1, L_0x2b68aa0, L_0x2b68b90, C4<0>, C4<0>;
+L_0x2b68c30 .delay (20000,20000,20000) L_0x2b68c30/d;
+v0x23d7210_0 .alias "S", 0 0, v0x240f880_0;
+v0x23d69d0_0 .net "in0", 0 0, L_0x2b68e10; 1 drivers
+v0x23d6a70_0 .net "in1", 0 0, L_0x2b68fb0; 1 drivers
+v0x23d5180_0 .net "nS", 0 0, L_0x2b689b0; 1 drivers
+v0x23d5220_0 .net "out0", 0 0, L_0x2b68aa0; 1 drivers
+v0x23d4ef0_0 .net "out1", 0 0, L_0x2b68b90; 1 drivers
+v0x23d8310_0 .net "outfinal", 0 0, L_0x2b68c30; 1 drivers
+S_0x23b4310 .scope generate, "sltbits[2]" "sltbits[2]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x26a59e8 .param/l "i" 3 332, +C4<010>;
+S_0x23b8390 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x23b4310;
+ .timescale -9 -12;
+L_0x2b69050/d .functor NOT 1, L_0x2b6a3d0, C4<0>, C4<0>, C4<0>;
+L_0x2b69050 .delay (10000,10000,10000) L_0x2b69050/d;
+L_0x2b69690/d .functor NOT 1, L_0x2b69730, C4<0>, C4<0>, C4<0>;
+L_0x2b69690 .delay (10000,10000,10000) L_0x2b69690/d;
+L_0x2b697d0/d .functor AND 1, L_0x2b69910, L_0x2b69690, C4<1>, C4<1>;
+L_0x2b697d0 .delay (20000,20000,20000) L_0x2b697d0/d;
+L_0x2b699b0/d .functor XOR 1, L_0x2b6a330, L_0x2b69460, C4<0>, C4<0>;
+L_0x2b699b0 .delay (40000,40000,40000) L_0x2b699b0/d;
+L_0x2b69aa0/d .functor XOR 1, L_0x2b699b0, L_0x2b6a590, C4<0>, C4<0>;
+L_0x2b69aa0 .delay (40000,40000,40000) L_0x2b69aa0/d;
+L_0x2b69b90/d .functor AND 1, L_0x2b6a330, L_0x2b69460, C4<1>, C4<1>;
+L_0x2b69b90 .delay (20000,20000,20000) L_0x2b69b90/d;
+L_0x2b69d00/d .functor AND 1, L_0x2b699b0, L_0x2b6a590, C4<1>, C4<1>;
+L_0x2b69d00 .delay (20000,20000,20000) L_0x2b69d00/d;
+L_0x2b69df0/d .functor OR 1, L_0x2b69b90, L_0x2b69d00, C4<0>, C4<0>;
+L_0x2b69df0 .delay (20000,20000,20000) L_0x2b69df0/d;
+v0x23d1420_0 .net "A", 0 0, L_0x2b6a330; 1 drivers
+v0x23d10f0_0 .net "AandB", 0 0, L_0x2b69b90; 1 drivers
+v0x23d1190_0 .net "AddSubSLTSum", 0 0, L_0x2b69aa0; 1 drivers
+v0x23d0e70_0 .net "AxorB", 0 0, L_0x2b699b0; 1 drivers
+v0x23d0f10_0 .net "B", 0 0, L_0x2b6a3d0; 1 drivers
+v0x23cf620_0 .net "BornB", 0 0, L_0x2b69460; 1 drivers
+v0x23cf6e0_0 .net "CINandAxorB", 0 0, L_0x2b69d00; 1 drivers
+v0x23cf390_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x23cf410_0 .net *"_s3", 0 0, L_0x2b69730; 1 drivers
+v0x23d27b0_0 .net *"_s5", 0 0, L_0x2b69910; 1 drivers
+v0x23d2850_0 .net "carryin", 0 0, L_0x2b6a590; 1 drivers
+v0x23cf100_0 .net "carryout", 0 0, L_0x2b69df0; 1 drivers
+v0x23cf1a0_0 .net "nB", 0 0, L_0x2b69050; 1 drivers
+v0x23cee80_0 .net "nCmd2", 0 0, L_0x2b69690; 1 drivers
+v0x23d7170_0 .net "subtract", 0 0, L_0x2b697d0; 1 drivers
+L_0x2b695f0 .part v0x2960210_0, 0, 1;
+L_0x2b69730 .part v0x2960210_0, 2, 1;
+L_0x2b69910 .part v0x2960210_0, 0, 1;
+S_0x23bb7b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23b8390;
+ .timescale -9 -12;
+L_0x2b691e0/d .functor NOT 1, L_0x2b695f0, C4<0>, C4<0>, C4<0>;
+L_0x2b691e0 .delay (10000,10000,10000) L_0x2b691e0/d;
+L_0x2b69280/d .functor AND 1, L_0x2b6a3d0, L_0x2b691e0, C4<1>, C4<1>;
+L_0x2b69280 .delay (20000,20000,20000) L_0x2b69280/d;
+L_0x2b69370/d .functor AND 1, L_0x2b69050, L_0x2b695f0, C4<1>, C4<1>;
+L_0x2b69370 .delay (20000,20000,20000) L_0x2b69370/d;
+L_0x2b69460/d .functor OR 1, L_0x2b69280, L_0x2b69370, C4<0>, C4<0>;
+L_0x2b69460 .delay (20000,20000,20000) L_0x2b69460/d;
+v0x23b86c0_0 .net "S", 0 0, L_0x2b695f0; 1 drivers
+v0x23b8100_0 .alias "in0", 0 0, v0x23d0f10_0;
+v0x23b81a0_0 .alias "in1", 0 0, v0x23cf1a0_0;
+v0x23b7e80_0 .net "nS", 0 0, L_0x2b691e0; 1 drivers
+v0x23b7f20_0 .net "out0", 0 0, L_0x2b69280; 1 drivers
+v0x23d1610_0 .net "out1", 0 0, L_0x2b69370; 1 drivers
+v0x23d1380_0 .alias "outfinal", 0 0, v0x23cf620_0;
+S_0x23ba610 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x23b4310;
+ .timescale -9 -12;
+L_0x2b68f50/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b68f50 .delay (10000,10000,10000) L_0x2b68f50/d;
+L_0x2b6a6c0/d .functor AND 1, L_0x2b6ab10, L_0x2b68f50, C4<1>, C4<1>;
+L_0x2b6a6c0 .delay (20000,20000,20000) L_0x2b6a6c0/d;
+L_0x2b6a760/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6a760 .delay (20000,20000,20000) L_0x2b6a760/d;
+L_0x2b6a800/d .functor OR 1, L_0x2b6a6c0, L_0x2b6a760, C4<0>, C4<0>;
+L_0x2b6a800 .delay (20000,20000,20000) L_0x2b6a800/d;
+v0x23b23c0_0 .alias "S", 0 0, v0x240f880_0;
+v0x23ba380_0 .net "in0", 0 0, L_0x2b6ab10; 1 drivers
+v0x23ba420_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x23ba0f0_0 .net "nS", 0 0, L_0x2b68f50; 1 drivers
+v0x23ba190_0 .net "out0", 0 0, L_0x2b6a6c0; 1 drivers
+v0x23b9e70_0 .net "out1", 0 0, L_0x2b6a760; 1 drivers
+v0x23b8620_0 .net "outfinal", 0 0, L_0x2b6a800; 1 drivers
+S_0x23b2ac0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x23b4310;
+ .timescale -9 -12;
+L_0x2abcc70/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2abcc70 .delay (10000,10000,10000) L_0x2abcc70/d;
+L_0x2abcd60/d .functor AND 1, L_0x2b6aa70, L_0x2abcc70, C4<1>, C4<1>;
+L_0x2abcd60 .delay (20000,20000,20000) L_0x2abcd60/d;
+L_0x2b6ae30/d .functor AND 1, L_0x2b6b170, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6ae30 .delay (20000,20000,20000) L_0x2b6ae30/d;
+L_0x2b6ae90/d .functor OR 1, L_0x2abcd60, L_0x2b6ae30, C4<0>, C4<0>;
+L_0x2b6ae90 .delay (20000,20000,20000) L_0x2b6ae90/d;
+v0x23b4630_0 .alias "S", 0 0, v0x240f880_0;
+v0x23b2830_0 .net "in0", 0 0, L_0x2b6aa70; 1 drivers
+v0x23b28d0_0 .net "in1", 0 0, L_0x2b6b170; 1 drivers
+v0x23b5c50_0 .net "nS", 0 0, L_0x2abcc70; 1 drivers
+v0x23b5cf0_0 .net "out0", 0 0, L_0x2abcd60; 1 drivers
+v0x23b25a0_0 .net "out1", 0 0, L_0x2b6ae30; 1 drivers
+v0x23b2320_0 .net "outfinal", 0 0, L_0x2b6ae90; 1 drivers
+S_0x238fc40 .scope generate, "sltbits[3]" "sltbits[3]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2391f38 .param/l "i" 3 332, +C4<011>;
+S_0x239d570 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x238fc40;
+ .timescale -9 -12;
+L_0x2b6b070/d .functor NOT 1, L_0x2b6c330, C4<0>, C4<0>, C4<0>;
+L_0x2b6b070 .delay (10000,10000,10000) L_0x2b6b070/d;
+L_0x2b6b8b0/d .functor NOT 1, L_0x2b6b950, C4<0>, C4<0>, C4<0>;
+L_0x2b6b8b0 .delay (10000,10000,10000) L_0x2b6b8b0/d;
+L_0x2b6b9f0/d .functor AND 1, L_0x2b6bb30, L_0x2b6b8b0, C4<1>, C4<1>;
+L_0x2b6b9f0 .delay (20000,20000,20000) L_0x2b6b9f0/d;
+L_0x2b6bbd0/d .functor XOR 1, L_0x2b6c450, L_0x2b6b680, C4<0>, C4<0>;
+L_0x2b6bbd0 .delay (40000,40000,40000) L_0x2b6bbd0/d;
+L_0x2b6bcc0/d .functor XOR 1, L_0x2b6bbd0, L_0x2b6c660, C4<0>, C4<0>;
+L_0x2b6bcc0 .delay (40000,40000,40000) L_0x2b6bcc0/d;
+L_0x2b6bdb0/d .functor AND 1, L_0x2b6c450, L_0x2b6b680, C4<1>, C4<1>;
+L_0x2b6bdb0 .delay (20000,20000,20000) L_0x2b6bdb0/d;
+L_0x2b6bf20/d .functor AND 1, L_0x2b6bbd0, L_0x2b6c660, C4<1>, C4<1>;
+L_0x2b6bf20 .delay (20000,20000,20000) L_0x2b6bf20/d;
+L_0x2b6c010/d .functor OR 1, L_0x2b6bdb0, L_0x2b6bf20, C4<0>, C4<0>;
+L_0x2b6c010 .delay (20000,20000,20000) L_0x2b6c010/d;
+v0x239b3a0_0 .net "A", 0 0, L_0x2b6c450; 1 drivers
+v0x23aef50_0 .net "AandB", 0 0, L_0x2b6bdb0; 1 drivers
+v0x23aeff0_0 .net "AddSubSLTSum", 0 0, L_0x2b6bcc0; 1 drivers
+v0x23aecc0_0 .net "AxorB", 0 0, L_0x2b6bbd0; 1 drivers
+v0x23aed60_0 .net "B", 0 0, L_0x2b6c330; 1 drivers
+v0x23aea30_0 .net "BornB", 0 0, L_0x2b6b680; 1 drivers
+v0x23aeab0_0 .net "CINandAxorB", 0 0, L_0x2b6bf20; 1 drivers
+v0x23ae7b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x23ae830_0 .net *"_s3", 0 0, L_0x2b6b950; 1 drivers
+v0x23b00f0_0 .net *"_s5", 0 0, L_0x2b6bb30; 1 drivers
+v0x23b0190_0 .net "carryin", 0 0, L_0x2b6c660; 1 drivers
+v0x23b4ab0_0 .net "carryout", 0 0, L_0x2b6c010; 1 drivers
+v0x23b4b50_0 .net "nB", 0 0, L_0x2b6b070; 1 drivers
+v0x23b4820_0 .net "nCmd2", 0 0, L_0x2b6b8b0; 1 drivers
+v0x23b4590_0 .net "subtract", 0 0, L_0x2b6b9f0; 1 drivers
+L_0x2b6b810 .part v0x2960210_0, 0, 1;
+L_0x2b6b950 .part v0x2960210_0, 2, 1;
+L_0x2b6bb30 .part v0x2960210_0, 0, 1;
+S_0x239d2f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x239d570;
+ .timescale -9 -12;
+L_0x2b6b400/d .functor NOT 1, L_0x2b6b810, C4<0>, C4<0>, C4<0>;
+L_0x2b6b400 .delay (10000,10000,10000) L_0x2b6b400/d;
+L_0x2b6b4a0/d .functor AND 1, L_0x2b6c330, L_0x2b6b400, C4<1>, C4<1>;
+L_0x2b6b4a0 .delay (20000,20000,20000) L_0x2b6b4a0/d;
+L_0x2b6b590/d .functor AND 1, L_0x2b6b070, L_0x2b6b810, C4<1>, C4<1>;
+L_0x2b6b590 .delay (20000,20000,20000) L_0x2b6b590/d;
+L_0x2b6b680/d .functor OR 1, L_0x2b6b4a0, L_0x2b6b590, C4<0>, C4<0>;
+L_0x2b6b680 .delay (20000,20000,20000) L_0x2b6b680/d;
+v0x239d8a0_0 .net "S", 0 0, L_0x2b6b810; 1 drivers
+v0x239baa0_0 .alias "in0", 0 0, v0x23aed60_0;
+v0x239bb40_0 .alias "in1", 0 0, v0x23b4b50_0;
+v0x239b810_0 .net "nS", 0 0, L_0x2b6b400; 1 drivers
+v0x239b8b0_0 .net "out0", 0 0, L_0x2b6b4a0; 1 drivers
+v0x239b580_0 .net "out1", 0 0, L_0x2b6b590; 1 drivers
+v0x239b300_0 .alias "outfinal", 0 0, v0x23aea30_0;
+S_0x2395cb0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x238fc40;
+ .timescale -9 -12;
+L_0x2b6c4f0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6c4f0 .delay (10000,10000,10000) L_0x2b6c4f0/d;
+L_0x2b6c550/d .functor AND 1, L_0x2b6cb00, L_0x2b6c4f0, C4<1>, C4<1>;
+L_0x2b6c550 .delay (20000,20000,20000) L_0x2b6c550/d;
+L_0x2b6c880/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6c880 .delay (20000,20000,20000) L_0x2b6c880/d;
+L_0x2b6c920/d .functor OR 1, L_0x2b6c550, L_0x2b6c880, C4<0>, C4<0>;
+L_0x2b6c920 .delay (20000,20000,20000) L_0x2b6c920/d;
+v0x2395fe0_0 .alias "S", 0 0, v0x240f880_0;
+v0x23990d0_0 .net "in0", 0 0, L_0x2b6cb00; 1 drivers
+v0x2399170_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2395a20_0 .net "nS", 0 0, L_0x2b6c4f0; 1 drivers
+v0x2395ac0_0 .net "out0", 0 0, L_0x2b6c550; 1 drivers
+v0x23957a0_0 .net "out1", 0 0, L_0x2b6c880; 1 drivers
+v0x239d800_0 .net "outfinal", 0 0, L_0x2b6c920; 1 drivers
+S_0x2397f30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x238fc40;
+ .timescale -9 -12;
+L_0x2b6c790/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6c790 .delay (10000,10000,10000) L_0x2b6c790/d;
+L_0x2b6cd80/d .functor AND 1, L_0x2b6d0f0, L_0x2b6c790, C4<1>, C4<1>;
+L_0x2b6cd80 .delay (20000,20000,20000) L_0x2b6cd80/d;
+L_0x2b6ce70/d .functor AND 1, L_0x2b6cbf0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6ce70 .delay (20000,20000,20000) L_0x2b6ce70/d;
+L_0x2b6cf10/d .functor OR 1, L_0x2b6cd80, L_0x2b6ce70, C4<0>, C4<0>;
+L_0x2b6cf10 .delay (20000,20000,20000) L_0x2b6cf10/d;
+v0x238ff60_0 .alias "S", 0 0, v0x240f880_0;
+v0x2397ca0_0 .net "in0", 0 0, L_0x2b6d0f0; 1 drivers
+v0x2397d40_0 .net "in1", 0 0, L_0x2b6cbf0; 1 drivers
+v0x2397a10_0 .net "nS", 0 0, L_0x2b6c790; 1 drivers
+v0x2397ab0_0 .net "out0", 0 0, L_0x2b6cd80; 1 drivers
+v0x2397790_0 .net "out1", 0 0, L_0x2b6ce70; 1 drivers
+v0x2395f40_0 .net "outfinal", 0 0, L_0x2b6cf10; 1 drivers
+S_0x2375580 .scope generate, "sltbits[4]" "sltbits[4]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x236dd48 .param/l "i" 3 332, +C4<0100>;
+S_0x237abd0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2375580;
+ .timescale -9 -12;
+L_0x2b6a9e0/d .functor NOT 1, L_0x2b6e6b0, C4<0>, C4<0>, C4<0>;
+L_0x2b6a9e0 .delay (10000,10000,10000) L_0x2b6a9e0/d;
+L_0x2b6d9e0/d .functor NOT 1, L_0x2b6da80, C4<0>, C4<0>, C4<0>;
+L_0x2b6d9e0 .delay (10000,10000,10000) L_0x2b6d9e0/d;
+L_0x2b6db20/d .functor AND 1, L_0x2b6dc60, L_0x2b6d9e0, C4<1>, C4<1>;
+L_0x2b6db20 .delay (20000,20000,20000) L_0x2b6db20/d;
+L_0x2b6dd00/d .functor XOR 1, L_0x2b6e370, L_0x2b6d7b0, C4<0>, C4<0>;
+L_0x2b6dd00 .delay (40000,40000,40000) L_0x2b6dd00/d;
+L_0x2b6ddf0/d .functor XOR 1, L_0x2b6dd00, L_0x2b6e580, C4<0>, C4<0>;
+L_0x2b6ddf0 .delay (40000,40000,40000) L_0x2b6ddf0/d;
+L_0x2b6dee0/d .functor AND 1, L_0x2b6e370, L_0x2b6d7b0, C4<1>, C4<1>;
+L_0x2b6dee0 .delay (20000,20000,20000) L_0x2b6dee0/d;
+L_0x2b6e050/d .functor AND 1, L_0x2b6dd00, L_0x2b6e580, C4<1>, C4<1>;
+L_0x2b6e050 .delay (20000,20000,20000) L_0x2b6e050/d;
+L_0x2b6e140/d .functor OR 1, L_0x2b6dee0, L_0x2b6e050, C4<0>, C4<0>;
+L_0x2b6e140 .delay (20000,20000,20000) L_0x2b6e140/d;
+v0x2378c80_0 .net "A", 0 0, L_0x2b6e370; 1 drivers
+v0x23923d0_0 .net "AandB", 0 0, L_0x2b6dee0; 1 drivers
+v0x2392470_0 .net "AddSubSLTSum", 0 0, L_0x2b6ddf0; 1 drivers
+v0x2392140_0 .net "AxorB", 0 0, L_0x2b6dd00; 1 drivers
+v0x23921e0_0 .net "B", 0 0, L_0x2b6e6b0; 1 drivers
+v0x2391eb0_0 .net "BornB", 0 0, L_0x2b6d7b0; 1 drivers
+v0x2391f70_0 .net "CINandAxorB", 0 0, L_0x2b6e050; 1 drivers
+v0x2391c30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2391cb0_0 .net *"_s3", 0 0, L_0x2b6da80; 1 drivers
+v0x23903e0_0 .net *"_s5", 0 0, L_0x2b6dc60; 1 drivers
+v0x2390480_0 .net "carryin", 0 0, L_0x2b6e580; 1 drivers
+v0x2390150_0 .net "carryout", 0 0, L_0x2b6e140; 1 drivers
+v0x23901f0_0 .net "nB", 0 0, L_0x2b6a9e0; 1 drivers
+v0x2393570_0 .net "nCmd2", 0 0, L_0x2b6d9e0; 1 drivers
+v0x238fec0_0 .net "subtract", 0 0, L_0x2b6db20; 1 drivers
+L_0x2b6d940 .part v0x2960210_0, 0, 1;
+L_0x2b6da80 .part v0x2960210_0, 2, 1;
+L_0x2b6dc60 .part v0x2960210_0, 0, 1;
+S_0x2379380 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x237abd0;
+ .timescale -9 -12;
+L_0x2b6d530/d .functor NOT 1, L_0x2b6d940, C4<0>, C4<0>, C4<0>;
+L_0x2b6d530 .delay (10000,10000,10000) L_0x2b6d530/d;
+L_0x2b6d5d0/d .functor AND 1, L_0x2b6e6b0, L_0x2b6d530, C4<1>, C4<1>;
+L_0x2b6d5d0 .delay (20000,20000,20000) L_0x2b6d5d0/d;
+L_0x2b6d6c0/d .functor AND 1, L_0x2b6a9e0, L_0x2b6d940, C4<1>, C4<1>;
+L_0x2b6d6c0 .delay (20000,20000,20000) L_0x2b6d6c0/d;
+L_0x2b6d7b0/d .functor OR 1, L_0x2b6d5d0, L_0x2b6d6c0, C4<0>, C4<0>;
+L_0x2b6d7b0 .delay (20000,20000,20000) L_0x2b6d7b0/d;
+v0x237aef0_0 .net "S", 0 0, L_0x2b6d940; 1 drivers
+v0x23790f0_0 .alias "in0", 0 0, v0x23921e0_0;
+v0x2379190_0 .alias "in1", 0 0, v0x23901f0_0;
+v0x237c510_0 .net "nS", 0 0, L_0x2b6d530; 1 drivers
+v0x237c5b0_0 .net "out0", 0 0, L_0x2b6d5d0; 1 drivers
+v0x2378e60_0 .net "out1", 0 0, L_0x2b6d6c0; 1 drivers
+v0x2378be0_0 .alias "outfinal", 0 0, v0x2391eb0_0;
+S_0x2373300 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2375580;
+ .timescale -9 -12;
+L_0x2b6e410/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6e410 .delay (10000,10000,10000) L_0x2b6e410/d;
+L_0x2b6e620/d .functor AND 1, L_0x2b6e7e0, L_0x2b6e410, C4<1>, C4<1>;
+L_0x2b6e620 .delay (20000,20000,20000) L_0x2b6e620/d;
+L_0x2b6ea30/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6ea30 .delay (20000,20000,20000) L_0x2b6ea30/d;
+L_0x2b6ead0/d .functor OR 1, L_0x2b6e620, L_0x2b6ea30, C4<0>, C4<0>;
+L_0x2b6ead0 .delay (20000,20000,20000) L_0x2b6ead0/d;
+v0x2376a50_0 .alias "S", 0 0, v0x240f880_0;
+v0x2373080_0 .net "in0", 0 0, L_0x2b6e7e0; 1 drivers
+v0x2373120_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x237b370_0 .net "nS", 0 0, L_0x2b6e410; 1 drivers
+v0x237b410_0 .net "out0", 0 0, L_0x2b6e620; 1 drivers
+v0x237b0e0_0 .net "out1", 0 0, L_0x2b6ea30; 1 drivers
+v0x237ae50_0 .net "outfinal", 0 0, L_0x2b6ead0; 1 drivers
+S_0x23752f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2375580;
+ .timescale -9 -12;
+L_0x2b6abf0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6abf0 .delay (10000,10000,10000) L_0x2b6abf0/d;
+L_0x2b6aca0/d .functor AND 1, L_0x2b6ecb0, L_0x2b6abf0, C4<1>, C4<1>;
+L_0x2b6aca0 .delay (20000,20000,20000) L_0x2b6aca0/d;
+L_0x2b6ad90/d .functor AND 1, L_0x2b6f4a0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6ad90 .delay (20000,20000,20000) L_0x2b6ad90/d;
+L_0x2b6f160/d .functor OR 1, L_0x2b6aca0, L_0x2b6ad90, C4<0>, C4<0>;
+L_0x2b6f160 .delay (20000,20000,20000) L_0x2b6f160/d;
+v0x23758b0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2375070_0 .net "in0", 0 0, L_0x2b6ecb0; 1 drivers
+v0x2375110_0 .net "in1", 0 0, L_0x2b6f4a0; 1 drivers
+v0x2373820_0 .net "nS", 0 0, L_0x2b6abf0; 1 drivers
+v0x23738c0_0 .net "out0", 0 0, L_0x2b6aca0; 1 drivers
+v0x2373590_0 .net "out1", 0 0, L_0x2b6ad90; 1 drivers
+v0x23769b0_0 .net "outfinal", 0 0, L_0x2b6f160; 1 drivers
+S_0x24b9f10 .scope generate, "sltbits[5]" "sltbits[5]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x27b6c88 .param/l "i" 3 332, +C4<0101>;
+S_0x24dc710 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x24b9f10;
+ .timescale -9 -12;
+L_0x2b6f340/d .functor NOT 1, L_0x2b70630, C4<0>, C4<0>, C4<0>;
+L_0x2b6f340 .delay (10000,10000,10000) L_0x2b6f340/d;
+L_0x2b6fbb0/d .functor NOT 1, L_0x2b6fc50, C4<0>, C4<0>, C4<0>;
+L_0x2b6fbb0 .delay (10000,10000,10000) L_0x2b6fbb0/d;
+L_0x2b6fcf0/d .functor AND 1, L_0x2b6fe30, L_0x2b6fbb0, C4<1>, C4<1>;
+L_0x2b6fcf0 .delay (20000,20000,20000) L_0x2b6fcf0/d;
+L_0x2b6fed0/d .functor XOR 1, L_0x2b707b0, L_0x2b6f980, C4<0>, C4<0>;
+L_0x2b6fed0 .delay (40000,40000,40000) L_0x2b6fed0/d;
+L_0x2b6ffc0/d .functor XOR 1, L_0x2b6fed0, L_0x2b709e0, C4<0>, C4<0>;
+L_0x2b6ffc0 .delay (40000,40000,40000) L_0x2b6ffc0/d;
+L_0x2b700b0/d .functor AND 1, L_0x2b707b0, L_0x2b6f980, C4<1>, C4<1>;
+L_0x2b700b0 .delay (20000,20000,20000) L_0x2b700b0/d;
+L_0x2b70220/d .functor AND 1, L_0x2b6fed0, L_0x2b709e0, C4<1>, C4<1>;
+L_0x2b70220 .delay (20000,20000,20000) L_0x2b70220/d;
+L_0x2b70310/d .functor OR 1, L_0x2b700b0, L_0x2b70220, C4<0>, C4<0>;
+L_0x2b70310 .delay (20000,20000,20000) L_0x2b70310/d;
+v0x236fac0_0 .net "A", 0 0, L_0x2b707b0; 1 drivers
+v0x236f790_0 .net "AandB", 0 0, L_0x2b700b0; 1 drivers
+v0x236f830_0 .net "AddSubSLTSum", 0 0, L_0x2b6ffc0; 1 drivers
+v0x236f510_0 .net "AxorB", 0 0, L_0x2b6fed0; 1 drivers
+v0x236f5b0_0 .net "B", 0 0, L_0x2b70630; 1 drivers
+v0x236dcc0_0 .net "BornB", 0 0, L_0x2b6f980; 1 drivers
+v0x236dd80_0 .net "CINandAxorB", 0 0, L_0x2b70220; 1 drivers
+v0x236da30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x236dab0_0 .net *"_s3", 0 0, L_0x2b6fc50; 1 drivers
+v0x2370e50_0 .net *"_s5", 0 0, L_0x2b6fe30; 1 drivers
+v0x2370ef0_0 .net "carryin", 0 0, L_0x2b709e0; 1 drivers
+v0x236d7a0_0 .net "carryout", 0 0, L_0x2b70310; 1 drivers
+v0x236d840_0 .net "nB", 0 0, L_0x2b6f340; 1 drivers
+v0x236d520_0 .net "nCmd2", 0 0, L_0x2b6fbb0; 1 drivers
+v0x2375810_0 .net "subtract", 0 0, L_0x2b6fcf0; 1 drivers
+L_0x2b6fb10 .part v0x2960210_0, 0, 1;
+L_0x2b6fc50 .part v0x2960210_0, 2, 1;
+L_0x2b6fe30 .part v0x2960210_0, 0, 1;
+S_0x24d98d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x24dc710;
+ .timescale -9 -12;
+L_0x2b6f700/d .functor NOT 1, L_0x2b6fb10, C4<0>, C4<0>, C4<0>;
+L_0x2b6f700 .delay (10000,10000,10000) L_0x2b6f700/d;
+L_0x2b6f7a0/d .functor AND 1, L_0x2b70630, L_0x2b6f700, C4<1>, C4<1>;
+L_0x2b6f7a0 .delay (20000,20000,20000) L_0x2b6f7a0/d;
+L_0x2b6f890/d .functor AND 1, L_0x2b6f340, L_0x2b6fb10, C4<1>, C4<1>;
+L_0x2b6f890 .delay (20000,20000,20000) L_0x2b6f890/d;
+L_0x2b6f980/d .functor OR 1, L_0x2b6f7a0, L_0x2b6f890, C4<0>, C4<0>;
+L_0x2b6f980 .delay (20000,20000,20000) L_0x2b6f980/d;
+v0x24df5f0_0 .net "S", 0 0, L_0x2b6fb10; 1 drivers
+v0x24b7db0_0 .alias "in0", 0 0, v0x236f5b0_0;
+v0x24b7e50_0 .alias "in1", 0 0, v0x236d840_0;
+v0x25130c0_0 .net "nS", 0 0, L_0x2b6f700; 1 drivers
+v0x2513160_0 .net "out0", 0 0, L_0x2b6f7a0; 1 drivers
+v0x236fcb0_0 .net "out1", 0 0, L_0x2b6f890; 1 drivers
+v0x236fa20_0 .alias "outfinal", 0 0, v0x236dcc0_0;
+S_0x24f63b0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x24b9f10;
+ .timescale -9 -12;
+L_0x2b6f630/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6f630 .delay (10000,10000,10000) L_0x2b6f630/d;
+L_0x2b70850/d .functor AND 1, L_0x2b70db0, L_0x2b6f630, C4<1>, C4<1>;
+L_0x2b70850 .delay (20000,20000,20000) L_0x2b70850/d;
+L_0x2b708f0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b708f0 .delay (20000,20000,20000) L_0x2b708f0/d;
+L_0x2b70c20/d .functor OR 1, L_0x2b70850, L_0x2b708f0, C4<0>, C4<0>;
+L_0x2b70c20 .delay (20000,20000,20000) L_0x2b70c20/d;
+v0x24f9290_0 .alias "S", 0 0, v0x240f880_0;
+v0x24f3570_0 .net "in0", 0 0, L_0x2b70db0; 1 drivers
+v0x24f3610_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x24f0750_0 .net "nS", 0 0, L_0x2b6f630; 1 drivers
+v0x24f07f0_0 .net "out0", 0 0, L_0x2b70850; 1 drivers
+v0x24bcd50_0 .net "out1", 0 0, L_0x2b708f0; 1 drivers
+v0x24df550_0 .net "outfinal", 0 0, L_0x2b70c20; 1 drivers
+S_0x24d0e10 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x24b9f10;
+ .timescale -9 -12;
+L_0x2b70b10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b70b10 .delay (10000,10000,10000) L_0x2b70b10/d;
+L_0x2b71050/d .functor AND 1, L_0x2b713c0, L_0x2b70b10, C4<1>, C4<1>;
+L_0x2b71050 .delay (20000,20000,20000) L_0x2b71050/d;
+L_0x2b71140/d .functor AND 1, L_0x2b70ea0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b71140 .delay (20000,20000,20000) L_0x2b71140/d;
+L_0x2b711e0/d .functor OR 1, L_0x2b71050, L_0x2b71140, C4<0>, C4<0>;
+L_0x2b711e0 .delay (20000,20000,20000) L_0x2b711e0/d;
+v0x24d3cf0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2510110_0 .net "in0", 0 0, L_0x2b713c0; 1 drivers
+v0x25101b0_0 .net "in1", 0 0, L_0x2b70ea0; 1 drivers
+v0x24fee70_0 .net "nS", 0 0, L_0x2b70b10; 1 drivers
+v0x24fef10_0 .net "out0", 0 0, L_0x2b71050; 1 drivers
+v0x24fc030_0 .net "out1", 0 0, L_0x2b71140; 1 drivers
+v0x24f91f0_0 .net "outfinal", 0 0, L_0x2b711e0; 1 drivers
+S_0x248bf20 .scope generate, "sltbits[6]" "sltbits[6]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x24a89d8 .param/l "i" 3 332, +C4<0110>;
+S_0x2460f30 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x248bf20;
+ .timescale -9 -12;
+L_0x2b70f90/d .functor NOT 1, L_0x2b72630, C4<0>, C4<0>, C4<0>;
+L_0x2b70f90 .delay (10000,10000,10000) L_0x2b70f90/d;
+L_0x2b71c00/d .functor NOT 1, L_0x2b71ca0, C4<0>, C4<0>, C4<0>;
+L_0x2b71c00 .delay (10000,10000,10000) L_0x2b71c00/d;
+L_0x2b71d40/d .functor AND 1, L_0x2b71e80, L_0x2b71c00, C4<1>, C4<1>;
+L_0x2b71d40 .delay (20000,20000,20000) L_0x2b71d40/d;
+L_0x2b71f20/d .functor XOR 1, L_0x2b72590, L_0x2b719d0, C4<0>, C4<0>;
+L_0x2b71f20 .delay (40000,40000,40000) L_0x2b71f20/d;
+L_0x2b72010/d .functor XOR 1, L_0x2b71f20, L_0x2b72a60, C4<0>, C4<0>;
+L_0x2b72010 .delay (40000,40000,40000) L_0x2b72010/d;
+L_0x2b72100/d .functor AND 1, L_0x2b72590, L_0x2b719d0, C4<1>, C4<1>;
+L_0x2b72100 .delay (20000,20000,20000) L_0x2b72100/d;
+L_0x2b72270/d .functor AND 1, L_0x2b71f20, L_0x2b72a60, C4<1>, C4<1>;
+L_0x2b72270 .delay (20000,20000,20000) L_0x2b72270/d;
+L_0x2b72360/d .functor OR 1, L_0x2b72100, L_0x2b72270, C4<0>, C4<0>;
+L_0x2b72360 .delay (20000,20000,20000) L_0x2b72360/d;
+v0x24504c0_0 .net "A", 0 0, L_0x2b72590; 1 drivers
+v0x2449100_0 .net "AandB", 0 0, L_0x2b72100; 1 drivers
+v0x24491a0_0 .net "AddSubSLTSum", 0 0, L_0x2b72010; 1 drivers
+v0x2444490_0 .net "AxorB", 0 0, L_0x2b71f20; 1 drivers
+v0x2444530_0 .net "B", 0 0, L_0x2b72630; 1 drivers
+v0x243f820_0 .net "BornB", 0 0, L_0x2b719d0; 1 drivers
+v0x243f8a0_0 .net "CINandAxorB", 0 0, L_0x2b72270; 1 drivers
+v0x243d370_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x243d3f0_0 .net *"_s3", 0 0, L_0x2b71ca0; 1 drivers
+v0x241e6d0_0 .net *"_s5", 0 0, L_0x2b71e80; 1 drivers
+v0x241e770_0 .net "carryin", 0 0, L_0x2b72a60; 1 drivers
+v0x241c810_0 .net "carryout", 0 0, L_0x2b72360; 1 drivers
+v0x241c8b0_0 .net "nB", 0 0, L_0x2b70f90; 1 drivers
+v0x24d6a90_0 .net "nCmd2", 0 0, L_0x2b71c00; 1 drivers
+v0x24d3c50_0 .net "subtract", 0 0, L_0x2b71d40; 1 drivers
+L_0x2b71b60 .part v0x2960210_0, 0, 1;
+L_0x2b71ca0 .part v0x2960210_0, 2, 1;
+L_0x2b71e80 .part v0x2960210_0, 0, 1;
+S_0x245ee90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2460f30;
+ .timescale -9 -12;
+L_0x2b71750/d .functor NOT 1, L_0x2b71b60, C4<0>, C4<0>, C4<0>;
+L_0x2b71750 .delay (10000,10000,10000) L_0x2b71750/d;
+L_0x2b717f0/d .functor AND 1, L_0x2b72630, L_0x2b71750, C4<1>, C4<1>;
+L_0x2b717f0 .delay (20000,20000,20000) L_0x2b717f0/d;
+L_0x2b718e0/d .functor AND 1, L_0x2b70f90, L_0x2b71b60, C4<1>, C4<1>;
+L_0x2b718e0 .delay (20000,20000,20000) L_0x2b718e0/d;
+L_0x2b719d0/d .functor OR 1, L_0x2b717f0, L_0x2b718e0, C4<0>, C4<0>;
+L_0x2b719d0 .delay (20000,20000,20000) L_0x2b719d0/d;
+v0x2465c40_0 .net "S", 0 0, L_0x2b71b60; 1 drivers
+v0x245e940_0 .alias "in0", 0 0, v0x2444530_0;
+v0x245e9e0_0 .alias "in1", 0 0, v0x241c8b0_0;
+v0x2459d80_0 .net "nS", 0 0, L_0x2b71750; 1 drivers
+v0x2459e20_0 .net "out0", 0 0, L_0x2b717f0; 1 drivers
+v0x24550d0_0 .net "out1", 0 0, L_0x2b718e0; 1 drivers
+v0x2450420_0 .alias "outfinal", 0 0, v0x243f820_0;
+S_0x24767e0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x248bf20;
+ .timescale -9 -12;
+L_0x2b72b00/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b72b00 .delay (10000,10000,10000) L_0x2b72b00/d;
+L_0x2b72b60/d .functor AND 1, L_0x2b6d1e0, L_0x2b72b00, C4<1>, C4<1>;
+L_0x2b72b60 .delay (20000,20000,20000) L_0x2b72b60/d;
+L_0x2b72c50/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b72c50 .delay (20000,20000,20000) L_0x2b72c50/d;
+L_0x2b72cf0/d .functor OR 1, L_0x2b72b60, L_0x2b72c50, C4<0>, C4<0>;
+L_0x2b72cf0 .delay (20000,20000,20000) L_0x2b72cf0/d;
+v0x247b530_0 .alias "S", 0 0, v0x240f880_0;
+v0x2471b30_0 .net "in0", 0 0, L_0x2b6d1e0; 1 drivers
+v0x2471bd0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2422de0_0 .net "nS", 0 0, L_0x2b72b00; 1 drivers
+v0x2422e80_0 .net "out0", 0 0, L_0x2b72b60; 1 drivers
+v0x246a810_0 .net "out1", 0 0, L_0x2b72c50; 1 drivers
+v0x2465ba0_0 .net "outfinal", 0 0, L_0x2b72cf0; 1 drivers
+S_0x24872b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x248bf20;
+ .timescale -9 -12;
+L_0x2b72900/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b72900 .delay (10000,10000,10000) L_0x2b72900/d;
+L_0x2b6ef10/d .functor AND 1, L_0x2b73100, L_0x2b72900, C4<1>, C4<1>;
+L_0x2b6ef10 .delay (20000,20000,20000) L_0x2b6ef10/d;
+L_0x2b6efd0/d .functor AND 1, L_0x2b731f0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b6efd0 .delay (20000,20000,20000) L_0x2b6efd0/d;
+L_0x2b6f090/d .functor OR 1, L_0x2b6ef10, L_0x2b6efd0, C4<0>, C4<0>;
+L_0x2b6f090 .delay (20000,20000,20000) L_0x2b6f090/d;
+v0x24932c0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2482640_0 .net "in0", 0 0, L_0x2b73100; 1 drivers
+v0x24826e0_0 .net "in1", 0 0, L_0x2b731f0; 1 drivers
+v0x24805a0_0 .net "nS", 0 0, L_0x2b72900; 1 drivers
+v0x2480640_0 .net "out0", 0 0, L_0x2b6ef10; 1 drivers
+v0x2480050_0 .net "out1", 0 0, L_0x2b6efd0; 1 drivers
+v0x247b490_0 .net "outfinal", 0 0, L_0x2b6f090; 1 drivers
+S_0x23bf470 .scope generate, "sltbits[7]" "sltbits[7]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x23e1c08 .param/l "i" 3 332, +C4<0111>;
+S_0x237e1f0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x23bf470;
+ .timescale -9 -12;
+L_0x2b738b0/d .functor NOT 1, L_0x2b74d50, C4<0>, C4<0>, C4<0>;
+L_0x2b738b0 .delay (10000,10000,10000) L_0x2b738b0/d;
+L_0x2b73ff0/d .functor NOT 1, L_0x2b740b0, C4<0>, C4<0>, C4<0>;
+L_0x2b73ff0 .delay (10000,10000,10000) L_0x2b73ff0/d;
+L_0x2b74150/d .functor AND 1, L_0x2b74290, L_0x2b73ff0, C4<1>, C4<1>;
+L_0x2b74150 .delay (20000,20000,20000) L_0x2b74150/d;
+L_0x2b74330/d .functor XOR 1, L_0x2b73780, L_0x2b73d80, C4<0>, C4<0>;
+L_0x2b74330 .delay (40000,40000,40000) L_0x2b74330/d;
+L_0x2b74420/d .functor XOR 1, L_0x2b74330, L_0x2b74df0, C4<0>, C4<0>;
+L_0x2b74420 .delay (40000,40000,40000) L_0x2b74420/d;
+L_0x2b74530/d .functor AND 1, L_0x2b73780, L_0x2b73d80, C4<1>, C4<1>;
+L_0x2b74530 .delay (20000,20000,20000) L_0x2b74530/d;
+L_0x2b746c0/d .functor AND 1, L_0x2b74330, L_0x2b74df0, C4<1>, C4<1>;
+L_0x2b746c0 .delay (20000,20000,20000) L_0x2b746c0/d;
+L_0x2b747d0/d .functor OR 1, L_0x2b74530, L_0x2b746c0, C4<0>, C4<0>;
+L_0x2b747d0 .delay (20000,20000,20000) L_0x2b747d0/d;
+v0x242c760_0 .net "A", 0 0, L_0x2b73780; 1 drivers
+v0x24b0840_0 .net "AandB", 0 0, L_0x2b74530; 1 drivers
+v0x24b08e0_0 .net "AddSubSLTSum", 0 0, L_0x2b74420; 1 drivers
+v0x24ad5c0_0 .net "AxorB", 0 0, L_0x2b74330; 1 drivers
+v0x24ad660_0 .net "B", 0 0, L_0x2b74d50; 1 drivers
+v0x24a8950_0 .net "BornB", 0 0, L_0x2b73d80; 1 drivers
+v0x24a8a10_0 .net "CINandAxorB", 0 0, L_0x2b746c0; 1 drivers
+v0x24a3ce0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24a3d60_0 .net *"_s3", 0 0, L_0x2b740b0; 1 drivers
+v0x2427a50_0 .net *"_s5", 0 0, L_0x2b74290; 1 drivers
+v0x2427af0_0 .net "carryin", 0 0, L_0x2b74df0; 1 drivers
+v0x249cb80_0 .net "carryout", 0 0, L_0x2b747d0; 1 drivers
+v0x249cc20_0 .net "nB", 0 0, L_0x2b738b0; 1 drivers
+v0x2497ed0_0 .net "nCmd2", 0 0, L_0x2b73ff0; 1 drivers
+v0x2493220_0 .net "subtract", 0 0, L_0x2b74150; 1 drivers
+L_0x2b73f50 .part v0x2960210_0, 0, 1;
+L_0x2b740b0 .part v0x2960210_0, 2, 1;
+L_0x2b74290 .part v0x2960210_0, 0, 1;
+S_0x2367140 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x237e1f0;
+ .timescale -9 -12;
+L_0x2b73a60/d .functor NOT 1, L_0x2b73f50, C4<0>, C4<0>, C4<0>;
+L_0x2b73a60 .delay (10000,10000,10000) L_0x2b73a60/d;
+L_0x2b73b40/d .functor AND 1, L_0x2b74d50, L_0x2b73a60, C4<1>, C4<1>;
+L_0x2b73b40 .delay (20000,20000,20000) L_0x2b73b40/d;
+L_0x2b73c70/d .functor AND 1, L_0x2b738b0, L_0x2b73f50, C4<1>, C4<1>;
+L_0x2b73c70 .delay (20000,20000,20000) L_0x2b73c70/d;
+L_0x2b73d80/d .functor OR 1, L_0x2b73b40, L_0x2b73c70, C4<0>, C4<0>;
+L_0x2b73d80 .delay (20000,20000,20000) L_0x2b73d80/d;
+v0x23802d0_0 .net "S", 0 0, L_0x2b73f50; 1 drivers
+v0x24386c0_0 .alias "in0", 0 0, v0x24ad660_0;
+v0x2438760_0 .alias "in1", 0 0, v0x249cc20_0;
+v0x2433a10_0 .net "nS", 0 0, L_0x2b73a60; 1 drivers
+v0x2433ab0_0 .net "out0", 0 0, L_0x2b73b40; 1 drivers
+v0x242ed60_0 .net "out1", 0 0, L_0x2b73c70; 1 drivers
+v0x242c6c0_0 .alias "outfinal", 0 0, v0x24a8950_0;
+S_0x238bad0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x23bf470;
+ .timescale -9 -12;
+L_0x2b74b10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b74b10 .delay (10000,10000,10000) L_0x2b74b10/d;
+L_0x2b74bb0/d .functor AND 1, L_0x2b75320, L_0x2b74b10, C4<1>, C4<1>;
+L_0x2b74bb0 .delay (20000,20000,20000) L_0x2b74bb0/d;
+L_0x2b74cc0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b74cc0 .delay (20000,20000,20000) L_0x2b74cc0/d;
+L_0x2b75120/d .functor OR 1, L_0x2b74bb0, L_0x2b74cc0, C4<0>, C4<0>;
+L_0x2b75120 .delay (20000,20000,20000) L_0x2b75120/d;
+v0x23a09f0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2389a90_0 .net "in0", 0 0, L_0x2b75320; 1 drivers
+v0x2389b30_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2385e80_0 .net "nS", 0 0, L_0x2b74b10; 1 drivers
+v0x2385f20_0 .net "out0", 0 0, L_0x2b74bb0; 1 drivers
+v0x2383e40_0 .net "out1", 0 0, L_0x2b74cc0; 1 drivers
+v0x2380230_0 .net "outfinal", 0 0, L_0x2b75120; 1 drivers
+S_0x23ac1f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x23bf470;
+ .timescale -9 -12;
+L_0x2b74f20/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b74f20 .delay (10000,10000,10000) L_0x2b74f20/d;
+L_0x2b75030/d .functor AND 1, L_0x2b759a0, L_0x2b74f20, C4<1>, C4<1>;
+L_0x2b75030 .delay (20000,20000,20000) L_0x2b75030/d;
+L_0x2b75700/d .functor AND 1, L_0x2b75410, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b75700 .delay (20000,20000,20000) L_0x2b75700/d;
+L_0x2b757a0/d .functor OR 1, L_0x2b75030, L_0x2b75700, C4<0>, C4<0>;
+L_0x2b757a0 .delay (20000,20000,20000) L_0x2b757a0/d;
+v0x23c3120_0 .alias "S", 0 0, v0x240f880_0;
+v0x23a85e0_0 .net "in0", 0 0, L_0x2b759a0; 1 drivers
+v0x23a8680_0 .net "in1", 0 0, L_0x2b75410; 1 drivers
+v0x23a65a0_0 .net "nS", 0 0, L_0x2b74f20; 1 drivers
+v0x23a6640_0 .net "out0", 0 0, L_0x2b75030; 1 drivers
+v0x23a2990_0 .net "out1", 0 0, L_0x2b75700; 1 drivers
+v0x23a0950_0 .net "outfinal", 0 0, L_0x2b757a0; 1 drivers
+S_0x258ad10 .scope generate, "sltbits[8]" "sltbits[8]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x240c368 .param/l "i" 3 332, +C4<01000>;
+S_0x2408e90 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x258ad10;
+ .timescale -9 -12;
+L_0x2b75500/d .functor NOT 1, L_0x2b77040, C4<0>, C4<0>, C4<0>;
+L_0x2b75500 .delay (10000,10000,10000) L_0x2b75500/d;
+L_0x2b76300/d .functor NOT 1, L_0x2b763c0, C4<0>, C4<0>, C4<0>;
+L_0x2b76300 .delay (10000,10000,10000) L_0x2b76300/d;
+L_0x2b76460/d .functor AND 1, L_0x2b765a0, L_0x2b76300, C4<1>, C4<1>;
+L_0x2b76460 .delay (20000,20000,20000) L_0x2b76460/d;
+L_0x2b76640/d .functor XOR 1, L_0x2b76fa0, L_0x2b76090, C4<0>, C4<0>;
+L_0x2b76640 .delay (40000,40000,40000) L_0x2b76640/d;
+L_0x2b76730/d .functor XOR 1, L_0x2b76640, L_0x2b76d10, C4<0>, C4<0>;
+L_0x2b76730 .delay (40000,40000,40000) L_0x2b76730/d;
+L_0x2b76820/d .functor AND 1, L_0x2b76fa0, L_0x2b76090, C4<1>, C4<1>;
+L_0x2b76820 .delay (20000,20000,20000) L_0x2b76820/d;
+L_0x2b769b0/d .functor AND 1, L_0x2b76640, L_0x2b76d10, C4<1>, C4<1>;
+L_0x2b769b0 .delay (20000,20000,20000) L_0x2b769b0/d;
+L_0x2b76ac0/d .functor OR 1, L_0x2b76820, L_0x2b769b0, C4<0>, C4<0>;
+L_0x2b76ac0 .delay (20000,20000,20000) L_0x2b76ac0/d;
+v0x23eb810_0 .net "A", 0 0, L_0x2b76fa0; 1 drivers
+v0x23e79e0_0 .net "AandB", 0 0, L_0x2b76820; 1 drivers
+v0x23e7a80_0 .net "AddSubSLTSum", 0 0, L_0x2b76730; 1 drivers
+v0x23e5910_0 .net "AxorB", 0 0, L_0x2b76640; 1 drivers
+v0x23e59b0_0 .net "B", 0 0, L_0x2b77040; 1 drivers
+v0x23e1b80_0 .net "BornB", 0 0, L_0x2b76090; 1 drivers
+v0x23e1c40_0 .net "CINandAxorB", 0 0, L_0x2b769b0; 1 drivers
+v0x23dfb40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x23dfbc0_0 .net *"_s3", 0 0, L_0x2b763c0; 1 drivers
+v0x23cad10_0 .net *"_s5", 0 0, L_0x2b765a0; 1 drivers
+v0x23cadb0_0 .net "carryin", 0 0, L_0x2b76d10; 1 drivers
+v0x23c8cd0_0 .net "carryout", 0 0, L_0x2b76ac0; 1 drivers
+v0x23c8d70_0 .net "nB", 0 0, L_0x2b75500; 1 drivers
+v0x23c50c0_0 .net "nCmd2", 0 0, L_0x2b76300; 1 drivers
+v0x23c3080_0 .net "subtract", 0 0, L_0x2b76460; 1 drivers
+L_0x2b76260 .part v0x2960210_0, 0, 1;
+L_0x2b763c0 .part v0x2960210_0, 2, 1;
+L_0x2b765a0 .part v0x2960210_0, 0, 1;
+S_0x2405100 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2408e90;
+ .timescale -9 -12;
+L_0x2b75d70/d .functor NOT 1, L_0x2b76260, C4<0>, C4<0>, C4<0>;
+L_0x2b75d70 .delay (10000,10000,10000) L_0x2b75d70/d;
+L_0x2b75e50/d .functor AND 1, L_0x2b77040, L_0x2b75d70, C4<1>, C4<1>;
+L_0x2b75e50 .delay (20000,20000,20000) L_0x2b75e50/d;
+L_0x2b75f80/d .functor AND 1, L_0x2b75500, L_0x2b76260, C4<1>, C4<1>;
+L_0x2b75f80 .delay (20000,20000,20000) L_0x2b75f80/d;
+L_0x2b76090/d .functor OR 1, L_0x2b75e50, L_0x2b75f80, C4<0>, C4<0>;
+L_0x2b76090 .delay (20000,20000,20000) L_0x2b76090/d;
+v0x240b000_0 .net "S", 0 0, L_0x2b76260; 1 drivers
+v0x2403030_0 .alias "in0", 0 0, v0x23e59b0_0;
+v0x24030d0_0 .alias "in1", 0 0, v0x23c8d70_0;
+v0x23ff2a0_0 .net "nS", 0 0, L_0x2b75d70; 1 drivers
+v0x23ff340_0 .net "out0", 0 0, L_0x2b75e50; 1 drivers
+v0x23ed840_0 .net "out1", 0 0, L_0x2b75f80; 1 drivers
+v0x23eb770_0 .alias "outfinal", 0 0, v0x23e1b80_0;
+S_0x2588c50 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x258ad10;
+ .timescale -9 -12;
+L_0x2b6e920/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6e920 .delay (10000,10000,10000) L_0x2b6e920/d;
+L_0x2b6e9c0/d .functor AND 1, L_0x2b770e0, L_0x2b6e920, C4<1>, C4<1>;
+L_0x2b6e9c0 .delay (20000,20000,20000) L_0x2b6e9c0/d;
+L_0x2b76e60/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b76e60 .delay (20000,20000,20000) L_0x2b76e60/d;
+L_0x2b76f20/d .functor OR 1, L_0x2b6e9c0, L_0x2b76e60, C4<0>, C4<0>;
+L_0x2b76f20 .delay (20000,20000,20000) L_0x2b76f20/d;
+v0x2588f90_0 .alias "S", 0 0, v0x240f880_0;
+v0x25889b0_0 .net "in0", 0 0, L_0x2b770e0; 1 drivers
+v0x2588a50_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x25886b0_0 .net "nS", 0 0, L_0x2b6e920; 1 drivers
+v0x2588750_0 .net "out0", 0 0, L_0x2b6e9c0; 1 drivers
+v0x2588130_0 .net "out1", 0 0, L_0x2b76e60; 1 drivers
+v0x240af60_0 .net "outfinal", 0 0, L_0x2b76f20; 1 drivers
+S_0x258aa70 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x258ad10;
+ .timescale -9 -12;
+L_0x2b6ee90/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b6ee90 .delay (10000,10000,10000) L_0x2b6ee90/d;
+L_0x2b77260/d .functor AND 1, L_0x2b77710, L_0x2b6ee90, C4<1>, C4<1>;
+L_0x2b77260 .delay (20000,20000,20000) L_0x2b77260/d;
+L_0x2b77320/d .functor AND 1, L_0x2b777b0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b77320 .delay (20000,20000,20000) L_0x2b77320/d;
+L_0x2b733b0/d .functor OR 1, L_0x2b77260, L_0x2b77320, C4<0>, C4<0>;
+L_0x2b733b0 .delay (20000,20000,20000) L_0x2b733b0/d;
+v0x258b050_0 .alias "S", 0 0, v0x240f880_0;
+v0x258a770_0 .net "in0", 0 0, L_0x2b77710; 1 drivers
+v0x258a810_0 .net "in1", 0 0, L_0x2b777b0; 1 drivers
+v0x258a1f0_0 .net "nS", 0 0, L_0x2b6ee90; 1 drivers
+v0x258a290_0 .net "out0", 0 0, L_0x2b77260; 1 drivers
+v0x2589190_0 .net "out1", 0 0, L_0x2b77320; 1 drivers
+v0x2588ef0_0 .net "outfinal", 0 0, L_0x2b733b0; 1 drivers
+S_0x2294e40 .scope generate, "sltbits[9]" "sltbits[9]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2299de8 .param/l "i" 3 332, +C4<01001>;
+S_0x22823d0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2294e40;
+ .timescale -9 -12;
+L_0x2b778a0/d .functor NOT 1, L_0x2b78070, C4<0>, C4<0>, C4<0>;
+L_0x2b778a0 .delay (10000,10000,10000) L_0x2b778a0/d;
+L_0x2b787f0/d .functor NOT 1, L_0x2b788b0, C4<0>, C4<0>, C4<0>;
+L_0x2b787f0 .delay (10000,10000,10000) L_0x2b787f0/d;
+L_0x2b78950/d .functor AND 1, L_0x2b78a90, L_0x2b787f0, C4<1>, C4<1>;
+L_0x2b78950 .delay (20000,20000,20000) L_0x2b78950/d;
+L_0x2b78b30/d .functor XOR 1, L_0x2b77fd0, L_0x2b78580, C4<0>, C4<0>;
+L_0x2b78b30 .delay (40000,40000,40000) L_0x2b78b30/d;
+L_0x2b78c20/d .functor XOR 1, L_0x2b78b30, L_0x2b795e0, C4<0>, C4<0>;
+L_0x2b78c20 .delay (40000,40000,40000) L_0x2b78c20/d;
+L_0x2b78d10/d .functor AND 1, L_0x2b77fd0, L_0x2b78580, C4<1>, C4<1>;
+L_0x2b78d10 .delay (20000,20000,20000) L_0x2b78d10/d;
+L_0x2b78ea0/d .functor AND 1, L_0x2b78b30, L_0x2b795e0, C4<1>, C4<1>;
+L_0x2b78ea0 .delay (20000,20000,20000) L_0x2b78ea0/d;
+L_0x2b78fb0/d .functor OR 1, L_0x2b78d10, L_0x2b78ea0, C4<0>, C4<0>;
+L_0x2b78fb0 .delay (20000,20000,20000) L_0x2b78fb0/d;
+v0x2279330_0 .net "A", 0 0, L_0x2b77fd0; 1 drivers
+v0x225cbe0_0 .net "AandB", 0 0, L_0x2b78d10; 1 drivers
+v0x225cc80_0 .net "AddSubSLTSum", 0 0, L_0x2b78c20; 1 drivers
+v0x225db80_0 .net "AxorB", 0 0, L_0x2b78b30; 1 drivers
+v0x225dc20_0 .net "B", 0 0, L_0x2b78070; 1 drivers
+v0x22f4150_0 .net "BornB", 0 0, L_0x2b78580; 1 drivers
+v0x22f41d0_0 .net "CINandAxorB", 0 0, L_0x2b78ea0; 1 drivers
+v0x258c460_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x258c4e0_0 .net *"_s3", 0 0, L_0x2b788b0; 1 drivers
+v0x258c1c0_0 .net *"_s5", 0 0, L_0x2b78a90; 1 drivers
+v0x258c260_0 .net "carryin", 0 0, L_0x2b795e0; 1 drivers
+v0x258b250_0 .net "carryout", 0 0, L_0x2b78fb0; 1 drivers
+v0x258b2f0_0 .net "nB", 0 0, L_0x2b778a0; 1 drivers
+v0x2369280_0 .net "nCmd2", 0 0, L_0x2b787f0; 1 drivers
+v0x258afb0_0 .net "subtract", 0 0, L_0x2b78950; 1 drivers
+L_0x2b78750 .part v0x2960210_0, 0, 1;
+L_0x2b788b0 .part v0x2960210_0, 2, 1;
+L_0x2b78a90 .part v0x2960210_0, 0, 1;
+S_0x225f2b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22823d0;
+ .timescale -9 -12;
+L_0x2b78260/d .functor NOT 1, L_0x2b78750, C4<0>, C4<0>, C4<0>;
+L_0x2b78260 .delay (10000,10000,10000) L_0x2b78260/d;
+L_0x2b78340/d .functor AND 1, L_0x2b78070, L_0x2b78260, C4<1>, C4<1>;
+L_0x2b78340 .delay (20000,20000,20000) L_0x2b78340/d;
+L_0x2b78470/d .functor AND 1, L_0x2b778a0, L_0x2b78750, C4<1>, C4<1>;
+L_0x2b78470 .delay (20000,20000,20000) L_0x2b78470/d;
+L_0x2b78580/d .functor OR 1, L_0x2b78340, L_0x2b78470, C4<0>, C4<0>;
+L_0x2b78580 .delay (20000,20000,20000) L_0x2b78580/d;
+v0x22829c0_0 .net "S", 0 0, L_0x2b78750; 1 drivers
+v0x227ddd0_0 .alias "in0", 0 0, v0x225dc20_0;
+v0x227de70_0 .alias "in1", 0 0, v0x258b2f0_0;
+v0x227d880_0 .net "nS", 0 0, L_0x2b78260; 1 drivers
+v0x227d920_0 .net "out0", 0 0, L_0x2b78340; 1 drivers
+v0x227b270_0 .net "out1", 0 0, L_0x2b78470; 1 drivers
+v0x2279290_0 .alias "outfinal", 0 0, v0x22f4150_0;
+S_0x228ba20 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2294e40;
+ .timescale -9 -12;
+L_0x2b792f0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b792f0 .delay (10000,10000,10000) L_0x2b792f0/d;
+L_0x2b79390/d .functor AND 1, L_0x2b79b00, L_0x2b792f0, C4<1>, C4<1>;
+L_0x2b79390 .delay (20000,20000,20000) L_0x2b79390/d;
+L_0x2b794a0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b794a0 .delay (20000,20000,20000) L_0x2b794a0/d;
+L_0x2b79560/d .functor OR 1, L_0x2b79390, L_0x2b794a0, C4<0>, C4<0>;
+L_0x2b79560 .delay (20000,20000,20000) L_0x2b79560/d;
+v0x228bfd0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2261900_0 .net "in0", 0 0, L_0x2b79b00; 1 drivers
+v0x22619a0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2287470_0 .net "nS", 0 0, L_0x2b792f0; 1 drivers
+v0x2287510_0 .net "out0", 0 0, L_0x2b79390; 1 drivers
+v0x2286f20_0 .net "out1", 0 0, L_0x2b794a0; 1 drivers
+v0x2282920_0 .net "outfinal", 0 0, L_0x2b79560; 1 drivers
+S_0x22929c0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2294e40;
+ .timescale -9 -12;
+L_0x2b77bd0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b77bd0 .delay (10000,10000,10000) L_0x2b77bd0/d;
+L_0x2b77ce0/d .functor AND 1, L_0x2b7a180, L_0x2b77bd0, C4<1>, C4<1>;
+L_0x2b77ce0 .delay (20000,20000,20000) L_0x2b77ce0/d;
+L_0x2b79f00/d .functor AND 1, L_0x2b79bf0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b79f00 .delay (20000,20000,20000) L_0x2b79f00/d;
+L_0x2b79fa0/d .functor OR 1, L_0x2b77ce0, L_0x2b79f00, C4<0>, C4<0>;
+L_0x2b79fa0 .delay (20000,20000,20000) L_0x2b79fa0/d;
+v0x22953f0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2290940_0 .net "in0", 0 0, L_0x2b7a180; 1 drivers
+v0x22909e0_0 .net "in1", 0 0, L_0x2b79bf0; 1 drivers
+v0x2290430_0 .net "nS", 0 0, L_0x2b77bd0; 1 drivers
+v0x22904d0_0 .net "out0", 0 0, L_0x2b77ce0; 1 drivers
+v0x228dfb0_0 .net "out1", 0 0, L_0x2b79f00; 1 drivers
+v0x228bf30_0 .net "outfinal", 0 0, L_0x2b79fa0; 1 drivers
+S_0x22ba820 .scope generate, "sltbits[10]" "sltbits[10]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x22c8528 .param/l "i" 3 332, +C4<01010>;
+S_0x22ac4e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x22ba820;
+ .timescale -9 -12;
+L_0x2b79ce0/d .functor NOT 1, L_0x2b7a4f0, C4<0>, C4<0>, C4<0>;
+L_0x2b79ce0 .delay (10000,10000,10000) L_0x2b79ce0/d;
+L_0x2b7ab00/d .functor NOT 1, L_0x2b7abc0, C4<0>, C4<0>, C4<0>;
+L_0x2b7ab00 .delay (10000,10000,10000) L_0x2b7ab00/d;
+L_0x2b7ac60/d .functor AND 1, L_0x2b7ada0, L_0x2b7ab00, C4<1>, C4<1>;
+L_0x2b7ac60 .delay (20000,20000,20000) L_0x2b7ac60/d;
+L_0x2b7ae40/d .functor XOR 1, L_0x2b7a450, L_0x2b7a870, C4<0>, C4<0>;
+L_0x2b7ae40 .delay (40000,40000,40000) L_0x2b7ae40/d;
+L_0x2b7af30/d .functor XOR 1, L_0x2b7ae40, L_0x2b7b530, C4<0>, C4<0>;
+L_0x2b7af30 .delay (40000,40000,40000) L_0x2b7af30/d;
+L_0x2b7b040/d .functor AND 1, L_0x2b7a450, L_0x2b7a870, C4<1>, C4<1>;
+L_0x2b7b040 .delay (20000,20000,20000) L_0x2b7b040/d;
+L_0x2b7b1d0/d .functor AND 1, L_0x2b7ae40, L_0x2b7b530, C4<1>, C4<1>;
+L_0x2b7b1d0 .delay (20000,20000,20000) L_0x2b7b1d0/d;
+L_0x2b7b2e0/d .functor OR 1, L_0x2b7b040, L_0x2b7b1d0, C4<0>, C4<0>;
+L_0x2b7b2e0 .delay (20000,20000,20000) L_0x2b7b2e0/d;
+v0x229e930_0 .net "A", 0 0, L_0x2b7a450; 1 drivers
+v0x229e340_0 .net "AandB", 0 0, L_0x2b7b040; 1 drivers
+v0x229e3e0_0 .net "AddSubSLTSum", 0 0, L_0x2b7af30; 1 drivers
+v0x229bd30_0 .net "AxorB", 0 0, L_0x2b7ae40; 1 drivers
+v0x229bdd0_0 .net "B", 0 0, L_0x2b7a4f0; 1 drivers
+v0x2299d60_0 .net "BornB", 0 0, L_0x2b7a870; 1 drivers
+v0x2299e20_0 .net "CINandAxorB", 0 0, L_0x2b7b1d0; 1 drivers
+v0x2299850_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x22998d0_0 .net *"_s3", 0 0, L_0x2b7abc0; 1 drivers
+v0x22973d0_0 .net *"_s5", 0 0, L_0x2b7ada0; 1 drivers
+v0x2297470_0 .net "carryin", 0 0, L_0x2b7b530; 1 drivers
+v0x2261e50_0 .net "carryout", 0 0, L_0x2b7b2e0; 1 drivers
+v0x2261ef0_0 .net "nB", 0 0, L_0x2b79ce0; 1 drivers
+v0x225cf20_0 .net "nCmd2", 0 0, L_0x2b7ab00; 1 drivers
+v0x2295350_0 .net "subtract", 0 0, L_0x2b7ac60; 1 drivers
+L_0x2b7aa40 .part v0x2960210_0, 0, 1;
+L_0x2b7abc0 .part v0x2960210_0, 2, 1;
+L_0x2b7ada0 .part v0x2960210_0, 0, 1;
+S_0x22a7f30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22ac4e0;
+ .timescale -9 -12;
+L_0x2b7a590/d .functor NOT 1, L_0x2b7aa40, C4<0>, C4<0>, C4<0>;
+L_0x2b7a590 .delay (10000,10000,10000) L_0x2b7a590/d;
+L_0x2b7a630/d .functor AND 1, L_0x2b7a4f0, L_0x2b7a590, C4<1>, C4<1>;
+L_0x2b7a630 .delay (20000,20000,20000) L_0x2b7a630/d;
+L_0x2b7a760/d .functor AND 1, L_0x2b79ce0, L_0x2b7aa40, C4<1>, C4<1>;
+L_0x2b7a760 .delay (20000,20000,20000) L_0x2b7a760/d;
+L_0x2b7a870/d .functor OR 1, L_0x2b7a630, L_0x2b7a760, C4<0>, C4<0>;
+L_0x2b7a870 .delay (20000,20000,20000) L_0x2b7a870/d;
+v0x22aca90_0 .net "S", 0 0, L_0x2b7aa40; 1 drivers
+v0x22a79e0_0 .alias "in0", 0 0, v0x229bdd0_0;
+v0x22a7a80_0 .alias "in1", 0 0, v0x2261ef0_0;
+v0x22a33e0_0 .net "nS", 0 0, L_0x2b7a590; 1 drivers
+v0x22a3480_0 .net "out0", 0 0, L_0x2b7a630; 1 drivers
+v0x22a2e90_0 .net "out1", 0 0, L_0x2b7a760; 1 drivers
+v0x229e890_0 .alias "outfinal", 0 0, v0x2299d60_0;
+S_0x22b3480 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x22ba820;
+ .timescale -9 -12;
+L_0x2b7b5d0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b7b5d0 .delay (10000,10000,10000) L_0x2b7b5d0/d;
+L_0x2b7b670/d .functor AND 1, L_0x2b7b900, L_0x2b7b5d0, C4<1>, C4<1>;
+L_0x2b7b670 .delay (20000,20000,20000) L_0x2b7b670/d;
+L_0x2b7b780/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b7b780 .delay (20000,20000,20000) L_0x2b7b780/d;
+L_0x2b7bc50/d .functor OR 1, L_0x2b7b670, L_0x2b7b780, C4<0>, C4<0>;
+L_0x2b7bc50 .delay (20000,20000,20000) L_0x2b7bc50/d;
+v0x22b59a0_0 .alias "S", 0 0, v0x240f880_0;
+v0x22b1400_0 .net "in0", 0 0, L_0x2b7b900; 1 drivers
+v0x22b14a0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x22b0ef0_0 .net "nS", 0 0, L_0x2b7b5d0; 1 drivers
+v0x22b0f90_0 .net "out0", 0 0, L_0x2b7b670; 1 drivers
+v0x22aea70_0 .net "out1", 0 0, L_0x2b7b780; 1 drivers
+v0x22ac9f0_0 .net "outfinal", 0 0, L_0x2b7bc50; 1 drivers
+S_0x22ba310 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x22ba820;
+ .timescale -9 -12;
+L_0x2b7ba80/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b7ba80 .delay (10000,10000,10000) L_0x2b7ba80/d;
+L_0x2b7bb90/d .functor AND 1, L_0x2b7be30, L_0x2b7ba80, C4<1>, C4<1>;
+L_0x2b7bb90 .delay (20000,20000,20000) L_0x2b7bb90/d;
+L_0x2b79760/d .functor AND 1, L_0x2b7bf20, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b79760 .delay (20000,20000,20000) L_0x2b79760/d;
+L_0x2b79820/d .functor OR 1, L_0x2b7bb90, L_0x2b79760, C4<0>, C4<0>;
+L_0x2b79820 .delay (20000,20000,20000) L_0x2b79820/d;
+v0x22beea0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2266450_0 .net "in0", 0 0, L_0x2b7be30; 1 drivers
+v0x22664f0_0 .net "in1", 0 0, L_0x2b7bf20; 1 drivers
+v0x22b7e90_0 .net "nS", 0 0, L_0x2b7ba80; 1 drivers
+v0x22b7f30_0 .net "out0", 0 0, L_0x2b7bb90; 1 drivers
+v0x22b5e10_0 .net "out1", 0 0, L_0x2b79760; 1 drivers
+v0x22b5900_0 .net "outfinal", 0 0, L_0x2b79820; 1 drivers
+S_0x22e94d0 .scope generate, "sltbits[11]" "sltbits[11]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2403c08 .param/l "i" 3 332, +C4<01011>;
+S_0x22d3f40 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x22e94d0;
+ .timescale -9 -12;
+L_0x2b7c010/d .functor NOT 1, L_0x2b7c640, C4<0>, C4<0>, C4<0>;
+L_0x2b7c010 .delay (10000,10000,10000) L_0x2b7c010/d;
+L_0x2b7ce10/d .functor NOT 1, L_0x2b7ced0, C4<0>, C4<0>, C4<0>;
+L_0x2b7ce10 .delay (10000,10000,10000) L_0x2b7ce10/d;
+L_0x2b7cf70/d .functor AND 1, L_0x2b7d0b0, L_0x2b7ce10, C4<1>, C4<1>;
+L_0x2b7cf70 .delay (20000,20000,20000) L_0x2b7cf70/d;
+L_0x2b7d150/d .functor XOR 1, L_0x2b7c5a0, L_0x2b7cba0, C4<0>, C4<0>;
+L_0x2b7d150 .delay (40000,40000,40000) L_0x2b7d150/d;
+L_0x2b7d240/d .functor XOR 1, L_0x2b7d150, L_0x2b7c770, C4<0>, C4<0>;
+L_0x2b7d240 .delay (40000,40000,40000) L_0x2b7d240/d;
+L_0x2b7d330/d .functor AND 1, L_0x2b7c5a0, L_0x2b7cba0, C4<1>, C4<1>;
+L_0x2b7d330 .delay (20000,20000,20000) L_0x2b7d330/d;
+L_0x2b7d4c0/d .functor AND 1, L_0x2b7d150, L_0x2b7c770, C4<1>, C4<1>;
+L_0x2b7d4c0 .delay (20000,20000,20000) L_0x2b7d4c0/d;
+L_0x2b7d5d0/d .functor OR 1, L_0x2b7d330, L_0x2b7d4c0, C4<0>, C4<0>;
+L_0x2b7d5d0 .delay (20000,20000,20000) L_0x2b7d5d0/d;
+v0x22cd550_0 .net "A", 0 0, L_0x2b7c5a0; 1 drivers
+v0x22ccfa0_0 .net "AandB", 0 0, L_0x2b7d330; 1 drivers
+v0x22cd040_0 .net "AddSubSLTSum", 0 0, L_0x2b7d240; 1 drivers
+v0x22c89f0_0 .net "AxorB", 0 0, L_0x2b7d150; 1 drivers
+v0x22c8a90_0 .net "B", 0 0, L_0x2b7c640; 1 drivers
+v0x22c84a0_0 .net "BornB", 0 0, L_0x2b7cba0; 1 drivers
+v0x22c8560_0 .net "CINandAxorB", 0 0, L_0x2b7d4c0; 1 drivers
+v0x22669a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2266a20_0 .net *"_s3", 0 0, L_0x2b7ced0; 1 drivers
+v0x22c3ea0_0 .net *"_s5", 0 0, L_0x2b7d0b0; 1 drivers
+v0x22c3f40_0 .net "carryin", 0 0, L_0x2b7c770; 1 drivers
+v0x22c3950_0 .net "carryout", 0 0, L_0x2b7d5d0; 1 drivers
+v0x22c39f0_0 .net "nB", 0 0, L_0x2b7c010; 1 drivers
+v0x22bf350_0 .net "nCmd2", 0 0, L_0x2b7ce10; 1 drivers
+v0x22bee00_0 .net "subtract", 0 0, L_0x2b7cf70; 1 drivers
+L_0x2b7cd70 .part v0x2960210_0, 0, 1;
+L_0x2b7ced0 .part v0x2960210_0, 2, 1;
+L_0x2b7d0b0 .part v0x2960210_0, 0, 1;
+S_0x22d1ec0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22d3f40;
+ .timescale -9 -12;
+L_0x2b7c880/d .functor NOT 1, L_0x2b7cd70, C4<0>, C4<0>, C4<0>;
+L_0x2b7c880 .delay (10000,10000,10000) L_0x2b7c880/d;
+L_0x2b7c960/d .functor AND 1, L_0x2b7c640, L_0x2b7c880, C4<1>, C4<1>;
+L_0x2b7c960 .delay (20000,20000,20000) L_0x2b7c960/d;
+L_0x2b7ca90/d .functor AND 1, L_0x2b7c010, L_0x2b7cd70, C4<1>, C4<1>;
+L_0x2b7ca90 .delay (20000,20000,20000) L_0x2b7ca90/d;
+L_0x2b7cba0/d .functor OR 1, L_0x2b7c960, L_0x2b7ca90, C4<0>, C4<0>;
+L_0x2b7cba0 .delay (20000,20000,20000) L_0x2b7cba0/d;
+v0x22d6460_0 .net "S", 0 0, L_0x2b7cd70; 1 drivers
+v0x22d19b0_0 .alias "in0", 0 0, v0x22c8a90_0;
+v0x22d1a50_0 .alias "in1", 0 0, v0x22c39f0_0;
+v0x225d160_0 .net "nS", 0 0, L_0x2b7c880; 1 drivers
+v0x225d200_0 .net "out0", 0 0, L_0x2b7c960; 1 drivers
+v0x22cf530_0 .net "out1", 0 0, L_0x2b7ca90; 1 drivers
+v0x22cd4b0_0 .alias "outfinal", 0 0, v0x22c84a0_0;
+S_0x22df8e0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x22e94d0;
+ .timescale -9 -12;
+L_0x2b7dcc0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b7dcc0 .delay (10000,10000,10000) L_0x2b7dcc0/d;
+L_0x2b7dd40/d .functor AND 1, L_0x2b7e110, L_0x2b7dcc0, C4<1>, C4<1>;
+L_0x2b7dd40 .delay (20000,20000,20000) L_0x2b7dd40/d;
+L_0x2b7de50/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b7de50 .delay (20000,20000,20000) L_0x2b7de50/d;
+L_0x2b7df10/d .functor OR 1, L_0x2b7dd40, L_0x2b7de50, C4<0>, C4<0>;
+L_0x2b7df10 .delay (20000,20000,20000) L_0x2b7df10/d;
+v0x22dfed0_0 .alias "S", 0 0, v0x240f880_0;
+v0x22db2e0_0 .net "in0", 0 0, L_0x2b7e110; 1 drivers
+v0x22db380_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x22d8950_0 .net "nS", 0 0, L_0x2b7dcc0; 1 drivers
+v0x22d89f0_0 .net "out0", 0 0, L_0x2b7dd40; 1 drivers
+v0x22d68d0_0 .net "out1", 0 0, L_0x2b7de50; 1 drivers
+v0x22d63c0_0 .net "outfinal", 0 0, L_0x2b7df10; 1 drivers
+S_0x22e8f80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x22e94d0;
+ .timescale -9 -12;
+L_0x2b7d9a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b7d9a0 .delay (10000,10000,10000) L_0x2b7d9a0/d;
+L_0x2b7dab0/d .functor AND 1, L_0x2b7e7a0, L_0x2b7d9a0, C4<1>, C4<1>;
+L_0x2b7dab0 .delay (20000,20000,20000) L_0x2b7dab0/d;
+L_0x2b7dbc0/d .functor AND 1, L_0x2b72ef0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b7dbc0 .delay (20000,20000,20000) L_0x2b7dbc0/d;
+L_0x2b7e5c0/d .functor OR 1, L_0x2b7dab0, L_0x2b7dbc0, C4<0>, C4<0>;
+L_0x2b7e5c0 .delay (20000,20000,20000) L_0x2b7e5c0/d;
+v0x22ee6a0_0 .alias "S", 0 0, v0x240f880_0;
+v0x226af50_0 .net "in0", 0 0, L_0x2b7e7a0; 1 drivers
+v0x226aff0_0 .net "in1", 0 0, L_0x2b72ef0; 1 drivers
+v0x22e4980_0 .net "nS", 0 0, L_0x2b7d9a0; 1 drivers
+v0x22e4a20_0 .net "out0", 0 0, L_0x2b7dab0; 1 drivers
+v0x22e4430_0 .net "out1", 0 0, L_0x2b7dbc0; 1 drivers
+v0x22dfe30_0 .net "outfinal", 0 0, L_0x2b7e5c0; 1 drivers
+S_0x222f970 .scope generate, "sltbits[12]" "sltbits[12]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2237f18 .param/l "i" 3 332, +C4<01100>;
+S_0x22219e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x222f970;
+ .timescale -9 -12;
+L_0x2b72fe0/d .functor NOT 1, L_0x2b7ef20, C4<0>, C4<0>, C4<0>;
+L_0x2b72fe0 .delay (10000,10000,10000) L_0x2b72fe0/d;
+L_0x2b7f200/d .functor NOT 1, L_0x2b7f2a0, C4<0>, C4<0>, C4<0>;
+L_0x2b7f200 .delay (10000,10000,10000) L_0x2b7f200/d;
+L_0x2b7f340/d .functor AND 1, L_0x2b7f480, L_0x2b7f200, C4<1>, C4<1>;
+L_0x2b7f340 .delay (20000,20000,20000) L_0x2b7f340/d;
+L_0x2b7f520/d .functor XOR 1, L_0x2b7ee80, L_0x2b7e520, C4<0>, C4<0>;
+L_0x2b7f520 .delay (40000,40000,40000) L_0x2b7f520/d;
+L_0x2b7f610/d .functor XOR 1, L_0x2b7f520, L_0x2b7ff90, C4<0>, C4<0>;
+L_0x2b7f610 .delay (40000,40000,40000) L_0x2b7f610/d;
+L_0x2b7f700/d .functor AND 1, L_0x2b7ee80, L_0x2b7e520, C4<1>, C4<1>;
+L_0x2b7f700 .delay (20000,20000,20000) L_0x2b7f700/d;
+L_0x2b7f870/d .functor AND 1, L_0x2b7f520, L_0x2b7ff90, C4<1>, C4<1>;
+L_0x2b7f870 .delay (20000,20000,20000) L_0x2b7f870/d;
+L_0x2b7f960/d .functor OR 1, L_0x2b7f700, L_0x2b7f870, C4<0>, C4<0>;
+L_0x2b7f960 .delay (20000,20000,20000) L_0x2b7f960/d;
+v0x2274920_0 .net "A", 0 0, L_0x2b7ee80; 1 drivers
+v0x2274370_0 .net "AandB", 0 0, L_0x2b7f700; 1 drivers
+v0x2274410_0 .net "AddSubSLTSum", 0 0, L_0x2b7f610; 1 drivers
+v0x2271ef0_0 .net "AxorB", 0 0, L_0x2b7f520; 1 drivers
+v0x2271f90_0 .net "B", 0 0, L_0x2b7ef20; 1 drivers
+v0x226fe70_0 .net "BornB", 0 0, L_0x2b7e520; 1 drivers
+v0x226fef0_0 .net "CINandAxorB", 0 0, L_0x2b7f870; 1 drivers
+v0x226f960_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x226f9e0_0 .net *"_s3", 0 0, L_0x2b7f2a0; 1 drivers
+v0x226d4e0_0 .net *"_s5", 0 0, L_0x2b7f480; 1 drivers
+v0x226d580_0 .net "carryin", 0 0, L_0x2b7ff90; 1 drivers
+v0x226b460_0 .net "carryout", 0 0, L_0x2b7f960; 1 drivers
+v0x226b500_0 .net "nB", 0 0, L_0x2b72fe0; 1 drivers
+v0x22eeb10_0 .net "nCmd2", 0 0, L_0x2b7f200; 1 drivers
+v0x22ee600_0 .net "subtract", 0 0, L_0x2b7f340; 1 drivers
+L_0x2b7f160 .part v0x2960210_0, 0, 1;
+L_0x2b7f2a0 .part v0x2960210_0, 2, 1;
+L_0x2b7f480 .part v0x2960210_0, 0, 1;
+S_0x2202790 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22219e0;
+ .timescale -9 -12;
+L_0x2b7e200/d .functor NOT 1, L_0x2b7f160, C4<0>, C4<0>, C4<0>;
+L_0x2b7e200 .delay (10000,10000,10000) L_0x2b7e200/d;
+L_0x2b7e2e0/d .functor AND 1, L_0x2b7ef20, L_0x2b7e200, C4<1>, C4<1>;
+L_0x2b7e2e0 .delay (20000,20000,20000) L_0x2b7e2e0/d;
+L_0x2b7e410/d .functor AND 1, L_0x2b72fe0, L_0x2b7f160, C4<1>, C4<1>;
+L_0x2b7e410 .delay (20000,20000,20000) L_0x2b7e410/d;
+L_0x2b7e520/d .functor OR 1, L_0x2b7e2e0, L_0x2b7e410, C4<0>, C4<0>;
+L_0x2b7e520 .delay (20000,20000,20000) L_0x2b7e520/d;
+v0x2224250_0 .net "S", 0 0, L_0x2b7f160; 1 drivers
+v0x2203700_0 .alias "in0", 0 0, v0x2271f90_0;
+v0x22037a0_0 .alias "in1", 0 0, v0x226b500_0;
+v0x2278d80_0 .net "nS", 0 0, L_0x2b7e200; 1 drivers
+v0x2278e20_0 .net "out0", 0 0, L_0x2b7e2e0; 1 drivers
+v0x2276900_0 .net "out1", 0 0, L_0x2b7e410; 1 drivers
+v0x2274880_0 .alias "outfinal", 0 0, v0x226fe70_0;
+S_0x2229ba0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x222f970;
+ .timescale -9 -12;
+L_0x2b80030/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b80030 .delay (10000,10000,10000) L_0x2b80030/d;
+L_0x2b80090/d .functor AND 1, L_0x2b7fb90, L_0x2b80030, C4<1>, C4<1>;
+L_0x2b80090 .delay (20000,20000,20000) L_0x2b80090/d;
+L_0x2b80180/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b80180 .delay (20000,20000,20000) L_0x2b80180/d;
+L_0x2b80220/d .functor OR 1, L_0x2b80090, L_0x2b80180, C4<0>, C4<0>;
+L_0x2b80220 .delay (20000,20000,20000) L_0x2b80220/d;
+v0x2205b70_0 .alias "S", 0 0, v0x240f880_0;
+v0x2227420_0 .net "in0", 0 0, L_0x2b7fb90; 1 drivers
+v0x22274c0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2226ed0_0 .net "nS", 0 0, L_0x2b80030; 1 drivers
+v0x2226f70_0 .net "out0", 0 0, L_0x2b80090; 1 drivers
+v0x2224700_0 .net "out1", 0 0, L_0x2b80180; 1 drivers
+v0x22241b0_0 .net "outfinal", 0 0, L_0x2b80220; 1 drivers
+S_0x222f460 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x222f970;
+ .timescale -9 -12;
+L_0x2b7fd10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b7fd10 .delay (10000,10000,10000) L_0x2b7fd10/d;
+L_0x2b7fe40/d .functor AND 1, L_0x2b80400, L_0x2b7fd10, C4<1>, C4<1>;
+L_0x2b7fe40 .delay (20000,20000,20000) L_0x2b7fe40/d;
+L_0x2b7c190/d .functor AND 1, L_0x2b804f0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b7c190 .delay (20000,20000,20000) L_0x2b7c190/d;
+L_0x2b7c210/d .functor OR 1, L_0x2b7fe40, L_0x2b7c190, C4<0>, C4<0>;
+L_0x2b7c210 .delay (20000,20000,20000) L_0x2b7c210/d;
+v0x2232160_0 .alias "S", 0 0, v0x240f880_0;
+v0x222cd10_0 .net "in0", 0 0, L_0x2b80400; 1 drivers
+v0x222cdb0_0 .net "in1", 0 0, L_0x2b804f0; 1 drivers
+v0x222c800_0 .net "nS", 0 0, L_0x2b7fd10; 1 drivers
+v0x222c8a0_0 .net "out0", 0 0, L_0x2b7fe40; 1 drivers
+v0x222a0b0_0 .net "out1", 0 0, L_0x2b7c190; 1 drivers
+v0x2205ad0_0 .net "outfinal", 0 0, L_0x2b7c210; 1 drivers
+S_0x2250da0 .scope generate, "sltbits[13]" "sltbits[13]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2256bf8 .param/l "i" 3 332, +C4<01101>;
+S_0x2242dd0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2250da0;
+ .timescale -9 -12;
+L_0x2b805e0/d .functor NOT 1, L_0x2b80c30, C4<0>, C4<0>, C4<0>;
+L_0x2b805e0 .delay (10000,10000,10000) L_0x2b805e0/d;
+L_0x2b81320/d .functor NOT 1, L_0x2b813c0, C4<0>, C4<0>, C4<0>;
+L_0x2b81320 .delay (10000,10000,10000) L_0x2b81320/d;
+L_0x2b81460/d .functor AND 1, L_0x2b815a0, L_0x2b81320, C4<1>, C4<1>;
+L_0x2b81460 .delay (20000,20000,20000) L_0x2b81460/d;
+L_0x2b81640/d .functor XOR 1, L_0x2b80b90, L_0x2b810f0, C4<0>, C4<0>;
+L_0x2b81640 .delay (40000,40000,40000) L_0x2b81640/d;
+L_0x2b81730/d .functor XOR 1, L_0x2b81640, L_0x2b80d60, C4<0>, C4<0>;
+L_0x2b81730 .delay (40000,40000,40000) L_0x2b81730/d;
+L_0x2b81820/d .functor AND 1, L_0x2b80b90, L_0x2b810f0, C4<1>, C4<1>;
+L_0x2b81820 .delay (20000,20000,20000) L_0x2b81820/d;
+L_0x2b81990/d .functor AND 1, L_0x2b81640, L_0x2b80d60, C4<1>, C4<1>;
+L_0x2b81990 .delay (20000,20000,20000) L_0x2b81990/d;
+L_0x2b81a80/d .functor OR 1, L_0x2b81820, L_0x2b81990, C4<0>, C4<0>;
+L_0x2b81a80 .delay (20000,20000,20000) L_0x2b81a80/d;
+v0x223ac60_0 .net "A", 0 0, L_0x2b80b90; 1 drivers
+v0x223a670_0 .net "AandB", 0 0, L_0x2b81820; 1 drivers
+v0x223a710_0 .net "AddSubSLTSum", 0 0, L_0x2b81730; 1 drivers
+v0x22082a0_0 .net "AxorB", 0 0, L_0x2b81640; 1 drivers
+v0x2208340_0 .net "B", 0 0, L_0x2b80c30; 1 drivers
+v0x2237e90_0 .net "BornB", 0 0, L_0x2b810f0; 1 drivers
+v0x2237f50_0 .net "CINandAxorB", 0 0, L_0x2b81990; 1 drivers
+v0x2237980_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2237a00_0 .net *"_s3", 0 0, L_0x2b813c0; 1 drivers
+v0x2235230_0 .net *"_s5", 0 0, L_0x2b815a0; 1 drivers
+v0x22352d0_0 .net "carryin", 0 0, L_0x2b80d60; 1 drivers
+v0x2234d20_0 .net "carryout", 0 0, L_0x2b81a80; 1 drivers
+v0x2234dc0_0 .net "nB", 0 0, L_0x2b805e0; 1 drivers
+v0x22325d0_0 .net "nCmd2", 0 0, L_0x2b81320; 1 drivers
+v0x22320c0_0 .net "subtract", 0 0, L_0x2b81460; 1 drivers
+L_0x2b81280 .part v0x2960210_0, 0, 1;
+L_0x2b813c0 .part v0x2960210_0, 2, 1;
+L_0x2b815a0 .part v0x2960210_0, 0, 1;
+S_0x2240600 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2242dd0;
+ .timescale -9 -12;
+L_0x2b807b0/d .functor NOT 1, L_0x2b81280, C4<0>, C4<0>, C4<0>;
+L_0x2b807b0 .delay (10000,10000,10000) L_0x2b807b0/d;
+L_0x2b80f10/d .functor AND 1, L_0x2b80c30, L_0x2b807b0, C4<1>, C4<1>;
+L_0x2b80f10 .delay (20000,20000,20000) L_0x2b80f10/d;
+L_0x2b81000/d .functor AND 1, L_0x2b805e0, L_0x2b81280, C4<1>, C4<1>;
+L_0x2b81000 .delay (20000,20000,20000) L_0x2b81000/d;
+L_0x2b810f0/d .functor OR 1, L_0x2b80f10, L_0x2b81000, C4<0>, C4<0>;
+L_0x2b810f0 .delay (20000,20000,20000) L_0x2b810f0/d;
+v0x22433c0_0 .net "S", 0 0, L_0x2b81280; 1 drivers
+v0x22400b0_0 .alias "in0", 0 0, v0x2208340_0;
+v0x2240150_0 .alias "in1", 0 0, v0x2234dc0_0;
+v0x223d8e0_0 .net "nS", 0 0, L_0x2b807b0; 1 drivers
+v0x223d980_0 .net "out0", 0 0, L_0x2b80f10; 1 drivers
+v0x223d390_0 .net "out1", 0 0, L_0x2b81000; 1 drivers
+v0x223abc0_0 .alias "outfinal", 0 0, v0x2237e90_0;
+S_0x2248810 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2250da0;
+ .timescale -9 -12;
+L_0x2b80e00/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b80e00 .delay (10000,10000,10000) L_0x2b80e00/d;
+L_0x2b82200/d .functor AND 1, L_0x2b82570, L_0x2b80e00, C4<1>, C4<1>;
+L_0x2b82200 .delay (20000,20000,20000) L_0x2b82200/d;
+L_0x2b822f0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b822f0 .delay (20000,20000,20000) L_0x2b822f0/d;
+L_0x2b82390/d .functor OR 1, L_0x2b82200, L_0x2b822f0, C4<0>, C4<0>;
+L_0x2b82390 .delay (20000,20000,20000) L_0x2b82390/d;
+v0x2248e00_0 .alias "S", 0 0, v0x240f880_0;
+v0x2246040_0 .net "in0", 0 0, L_0x2b82570; 1 drivers
+v0x22460e0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x22087b0_0 .net "nS", 0 0, L_0x2b80e00; 1 drivers
+v0x2208850_0 .net "out0", 0 0, L_0x2b82200; 1 drivers
+v0x2245af0_0 .net "out1", 0 0, L_0x2b822f0; 1 drivers
+v0x2243320_0 .net "outfinal", 0 0, L_0x2b82390; 1 drivers
+S_0x224e650 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2250da0;
+ .timescale -9 -12;
+L_0x2b81e30/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b81e30 .delay (10000,10000,10000) L_0x2b81e30/d;
+L_0x2b81f40/d .functor AND 1, L_0x2b82c00, L_0x2b81e30, C4<1>, C4<1>;
+L_0x2b81f40 .delay (20000,20000,20000) L_0x2b81f40/d;
+L_0x2b82050/d .functor AND 1, L_0x2b82660, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b82050 .delay (20000,20000,20000) L_0x2b82050/d;
+L_0x2b82110/d .functor OR 1, L_0x2b81f40, L_0x2b82050, C4<0>, C4<0>;
+L_0x2b82110 .delay (20000,20000,20000) L_0x2b82110/d;
+v0x2251350_0 .alias "S", 0 0, v0x240f880_0;
+v0x224e140_0 .net "in0", 0 0, L_0x2b82c00; 1 drivers
+v0x224e1e0_0 .net "in1", 0 0, L_0x2b82660; 1 drivers
+v0x224b9f0_0 .net "nS", 0 0, L_0x2b81e30; 1 drivers
+v0x224ba90_0 .net "out0", 0 0, L_0x2b81f40; 1 drivers
+v0x224b4e0_0 .net "out1", 0 0, L_0x2b82050; 1 drivers
+v0x2248d60_0 .net "outfinal", 0 0, L_0x2b82110; 1 drivers
+S_0x221e770 .scope generate, "sltbits[14]" "sltbits[14]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x221edc8 .param/l "i" 3 332, +C4<01110>;
+S_0x22107c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x221e770;
+ .timescale -9 -12;
+L_0x2b82750/d .functor NOT 1, L_0x2b84310, C4<0>, C4<0>, C4<0>;
+L_0x2b82750 .delay (10000,10000,10000) L_0x2b82750/d;
+L_0x2b834e0/d .functor NOT 1, L_0x2b83580, C4<0>, C4<0>, C4<0>;
+L_0x2b834e0 .delay (10000,10000,10000) L_0x2b834e0/d;
+L_0x2b83620/d .functor AND 1, L_0x2b83760, L_0x2b834e0, C4<1>, C4<1>;
+L_0x2b83620 .delay (20000,20000,20000) L_0x2b83620/d;
+L_0x2b83800/d .functor XOR 1, L_0x2b72760, L_0x2b832b0, C4<0>, C4<0>;
+L_0x2b83800 .delay (40000,40000,40000) L_0x2b83800/d;
+L_0x2b838f0/d .functor XOR 1, L_0x2b83800, L_0x2b83e70, C4<0>, C4<0>;
+L_0x2b838f0 .delay (40000,40000,40000) L_0x2b838f0/d;
+L_0x2b839e0/d .functor AND 1, L_0x2b72760, L_0x2b832b0, C4<1>, C4<1>;
+L_0x2b839e0 .delay (20000,20000,20000) L_0x2b839e0/d;
+L_0x2b83b50/d .functor AND 1, L_0x2b83800, L_0x2b83e70, C4<1>, C4<1>;
+L_0x2b83b50 .delay (20000,20000,20000) L_0x2b83b50/d;
+L_0x2b83c40/d .functor OR 1, L_0x2b839e0, L_0x2b83b50, C4<0>, C4<0>;
+L_0x2b83c40 .delay (20000,20000,20000) L_0x2b83c40/d;
+v0x2259d00_0 .net "A", 0 0, L_0x2b72760; 1 drivers
+v0x22597d0_0 .net "AandB", 0 0, L_0x2b839e0; 1 drivers
+v0x2259870_0 .net "AddSubSLTSum", 0 0, L_0x2b838f0; 1 drivers
+v0x22592c0_0 .net "AxorB", 0 0, L_0x2b83800; 1 drivers
+v0x2259360_0 .net "B", 0 0, L_0x2b84310; 1 drivers
+v0x2256b70_0 .net "BornB", 0 0, L_0x2b832b0; 1 drivers
+v0x2256c30_0 .net "CINandAxorB", 0 0, L_0x2b83b50; 1 drivers
+v0x2256660_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x22566e0_0 .net *"_s3", 0 0, L_0x2b83580; 1 drivers
+v0x220af00_0 .net *"_s5", 0 0, L_0x2b83760; 1 drivers
+v0x220afa0_0 .net "carryin", 0 0, L_0x2b83e70; 1 drivers
+v0x2253f10_0 .net "carryout", 0 0, L_0x2b83c40; 1 drivers
+v0x2253fb0_0 .net "nB", 0 0, L_0x2b82750; 1 drivers
+v0x2253a00_0 .net "nCmd2", 0 0, L_0x2b834e0; 1 drivers
+v0x22512b0_0 .net "subtract", 0 0, L_0x2b83620; 1 drivers
+L_0x2b83440 .part v0x2960210_0, 0, 1;
+L_0x2b83580 .part v0x2960210_0, 2, 1;
+L_0x2b83760 .part v0x2960210_0, 0, 1;
+S_0x220e070 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x22107c0;
+ .timescale -9 -12;
+L_0x2b82900/d .functor NOT 1, L_0x2b83440, C4<0>, C4<0>, C4<0>;
+L_0x2b82900 .delay (10000,10000,10000) L_0x2b82900/d;
+L_0x2b829e0/d .functor AND 1, L_0x2b84310, L_0x2b82900, C4<1>, C4<1>;
+L_0x2b829e0 .delay (20000,20000,20000) L_0x2b829e0/d;
+L_0x2b831c0/d .functor AND 1, L_0x2b82750, L_0x2b83440, C4<1>, C4<1>;
+L_0x2b831c0 .delay (20000,20000,20000) L_0x2b831c0/d;
+L_0x2b832b0/d .functor OR 1, L_0x2b829e0, L_0x2b831c0, C4<0>, C4<0>;
+L_0x2b832b0 .delay (20000,20000,20000) L_0x2b832b0/d;
+v0x2210d70_0 .net "S", 0 0, L_0x2b83440; 1 drivers
+v0x2202ce0_0 .alias "in0", 0 0, v0x2259360_0;
+v0x2202d80_0 .alias "in1", 0 0, v0x2253fb0_0;
+v0x220db60_0 .net "nS", 0 0, L_0x2b82900; 1 drivers
+v0x220dc00_0 .net "out0", 0 0, L_0x2b829e0; 1 drivers
+v0x220b410_0 .net "out1", 0 0, L_0x2b831c0; 1 drivers
+v0x2259c60_0 .alias "outfinal", 0 0, v0x2256b70_0;
+S_0x2216590 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x221e770;
+ .timescale -9 -12;
+L_0x2b83f10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b83f10 .delay (10000,10000,10000) L_0x2b83f10/d;
+L_0x2b83fb0/d .functor AND 1, L_0x2b843b0, L_0x2b83f10, C4<1>, C4<1>;
+L_0x2b83fb0 .delay (20000,20000,20000) L_0x2b83fb0/d;
+L_0x2b840c0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b840c0 .delay (20000,20000,20000) L_0x2b840c0/d;
+L_0x2b84180/d .functor OR 1, L_0x2b83fb0, L_0x2b840c0, C4<0>, C4<0>;
+L_0x2b84180 .delay (20000,20000,20000) L_0x2b84180/d;
+v0x2218dd0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2216080_0 .net "in0", 0 0, L_0x2b843b0; 1 drivers
+v0x2216120_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2213930_0 .net "nS", 0 0, L_0x2b83f10; 1 drivers
+v0x22139d0_0 .net "out0", 0 0, L_0x2b83fb0; 1 drivers
+v0x2213420_0 .net "out1", 0 0, L_0x2b840c0; 1 drivers
+v0x2210cd0_0 .net "outfinal", 0 0, L_0x2b84180; 1 drivers
+S_0x2205580 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x221e770;
+ .timescale -9 -12;
+L_0x2b847d0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b847d0 .delay (10000,10000,10000) L_0x2b847d0/d;
+L_0x2b80880/d .functor AND 1, L_0x2b84900, L_0x2b847d0, C4<1>, C4<1>;
+L_0x2b80880 .delay (20000,20000,20000) L_0x2b80880/d;
+L_0x2b80990/d .functor AND 1, L_0x2b849f0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b80990 .delay (20000,20000,20000) L_0x2b80990/d;
+L_0x2b80a30/d .functor OR 1, L_0x2b80880, L_0x2b80990, C4<0>, C4<0>;
+L_0x2b80a30 .delay (20000,20000,20000) L_0x2b80a30/d;
+v0x221bfa0_0 .alias "S", 0 0, v0x240f880_0;
+v0x221c020_0 .net "in0", 0 0, L_0x2b84900; 1 drivers
+v0x221ba50_0 .net "in1", 0 0, L_0x2b849f0; 1 drivers
+v0x221baf0_0 .net "nS", 0 0, L_0x2b847d0; 1 drivers
+v0x2219280_0 .net "out0", 0 0, L_0x2b80880; 1 drivers
+v0x2219320_0 .net "out1", 0 0, L_0x2b80990; 1 drivers
+v0x2218d30_0 .net "outfinal", 0 0, L_0x2b80a30; 1 drivers
+S_0x263c5b0 .scope generate, "sltbits[15]" "sltbits[15]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x232d428 .param/l "i" 3 332, +C4<01111>;
+S_0x2641910 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x263c5b0;
+ .timescale -9 -12;
+L_0x2b84ae0/d .functor NOT 1, L_0x2b850d0, C4<0>, C4<0>, C4<0>;
+L_0x2b84ae0 .delay (10000,10000,10000) L_0x2b84ae0/d;
+L_0x2b857f0/d .functor NOT 1, L_0x2b85890, C4<0>, C4<0>, C4<0>;
+L_0x2b857f0 .delay (10000,10000,10000) L_0x2b857f0/d;
+L_0x2b85930/d .functor AND 1, L_0x2b85a70, L_0x2b857f0, C4<1>, C4<1>;
+L_0x2b85930 .delay (20000,20000,20000) L_0x2b85930/d;
+L_0x2b85b10/d .functor XOR 1, L_0x2b85030, L_0x2b855c0, C4<0>, C4<0>;
+L_0x2b85b10 .delay (40000,40000,40000) L_0x2b85b10/d;
+L_0x2b85c00/d .functor XOR 1, L_0x2b85b10, L_0x2b85200, C4<0>, C4<0>;
+L_0x2b85c00 .delay (40000,40000,40000) L_0x2b85c00/d;
+L_0x2b85cf0/d .functor AND 1, L_0x2b85030, L_0x2b855c0, C4<1>, C4<1>;
+L_0x2b85cf0 .delay (20000,20000,20000) L_0x2b85cf0/d;
+L_0x2b85e60/d .functor AND 1, L_0x2b85b10, L_0x2b85200, C4<1>, C4<1>;
+L_0x2b85e60 .delay (20000,20000,20000) L_0x2b85e60/d;
+L_0x2b85f50/d .functor OR 1, L_0x2b85cf0, L_0x2b85e60, C4<0>, C4<0>;
+L_0x2b85f50 .delay (20000,20000,20000) L_0x2b85f50/d;
+v0x26400b0_0 .net "A", 0 0, L_0x2b85030; 1 drivers
+v0x2643610_0 .net "AandB", 0 0, L_0x2b85cf0; 1 drivers
+v0x2643690_0 .net "AddSubSLTSum", 0 0, L_0x2b85c00; 1 drivers
+v0x2643360_0 .net "AxorB", 0 0, L_0x2b85b10; 1 drivers
+v0x26433e0_0 .net "B", 0 0, L_0x2b850d0; 1 drivers
+v0x26423d0_0 .net "BornB", 0 0, L_0x2b855c0; 1 drivers
+v0x2642120_0 .net "CINandAxorB", 0 0, L_0x2b85e60; 1 drivers
+v0x26421a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2442bb0_0 .net *"_s3", 0 0, L_0x2b85890; 1 drivers
+v0x2442c30_0 .net *"_s5", 0 0, L_0x2b85a70; 1 drivers
+v0x2794b90_0 .net "carryin", 0 0, L_0x2b85200; 1 drivers
+v0x2794c10_0 .net "carryout", 0 0, L_0x2b85f50; 1 drivers
+v0x1d47970_0 .net "nB", 0 0, L_0x2b84ae0; 1 drivers
+v0x1d479f0_0 .net "nCmd2", 0 0, L_0x2b857f0; 1 drivers
+v0x221ed40_0 .net "subtract", 0 0, L_0x2b85930; 1 drivers
+L_0x2b85750 .part v0x2960210_0, 0, 1;
+L_0x2b85890 .part v0x2960210_0, 2, 1;
+L_0x2b85a70 .part v0x2960210_0, 0, 1;
+S_0x26402e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2641910;
+ .timescale -9 -12;
+L_0x2b84cb0/d .functor NOT 1, L_0x2b85750, C4<0>, C4<0>, C4<0>;
+L_0x2b84cb0 .delay (10000,10000,10000) L_0x2b84cb0/d;
+L_0x2b85420/d .functor AND 1, L_0x2b850d0, L_0x2b84cb0, C4<1>, C4<1>;
+L_0x2b85420 .delay (20000,20000,20000) L_0x2b85420/d;
+L_0x2b854d0/d .functor AND 1, L_0x2b84ae0, L_0x2b85750, C4<1>, C4<1>;
+L_0x2b854d0 .delay (20000,20000,20000) L_0x2b854d0/d;
+L_0x2b855c0/d .functor OR 1, L_0x2b85420, L_0x2b854d0, C4<0>, C4<0>;
+L_0x2b855c0 .delay (20000,20000,20000) L_0x2b855c0/d;
+v0x2704790_0 .net "S", 0 0, L_0x2b85750; 1 drivers
+v0x26f45d0_0 .alias "in0", 0 0, v0x26433e0_0;
+v0x26eaa20_0 .alias "in1", 0 0, v0x1d47970_0;
+v0x2704090_0 .net "nS", 0 0, L_0x2b84cb0; 1 drivers
+v0x26e7200_0 .net "out0", 0 0, L_0x2b85420; 1 drivers
+v0x2735090_0 .net "out1", 0 0, L_0x2b854d0; 1 drivers
+v0x2640030_0 .alias "outfinal", 0 0, v0x26423d0_0;
+S_0x2641bc0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x263c5b0;
+ .timescale -9 -12;
+L_0x2b852a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b852a0 .delay (10000,10000,10000) L_0x2b852a0/d;
+L_0x2b85340/d .functor AND 1, L_0x2b86a50, L_0x2b852a0, C4<1>, C4<1>;
+L_0x2b85340 .delay (20000,20000,20000) L_0x2b85340/d;
+L_0x2b867d0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b867d0 .delay (20000,20000,20000) L_0x2b867d0/d;
+L_0x2b86870/d .functor OR 1, L_0x2b85340, L_0x2b867d0, C4<0>, C4<0>;
+L_0x2b86870 .delay (20000,20000,20000) L_0x2b86870/d;
+v0x278dd10_0 .alias "S", 0 0, v0x240f880_0;
+v0x275cb00_0 .net "in0", 0 0, L_0x2b86a50; 1 drivers
+v0x2750740_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2741670_0 .net "nS", 0 0, L_0x2b852a0; 1 drivers
+v0x2730ad0_0 .net "out0", 0 0, L_0x2b85340; 1 drivers
+v0x2719bd0_0 .net "out1", 0 0, L_0x2b867d0; 1 drivers
+v0x2710240_0 .net "outfinal", 0 0, L_0x2b86870; 1 drivers
+S_0x263c300 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x263c5b0;
+ .timescale -9 -12;
+L_0x2b86300/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b86300 .delay (10000,10000,10000) L_0x2b86300/d;
+L_0x2b863f0/d .functor AND 1, L_0x2b87060, L_0x2b86300, C4<1>, C4<1>;
+L_0x2b863f0 .delay (20000,20000,20000) L_0x2b863f0/d;
+L_0x2b86500/d .functor AND 1, L_0x2b86b40, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b86500 .delay (20000,20000,20000) L_0x2b86500/d;
+L_0x2b865a0/d .functor OR 1, L_0x2b863f0, L_0x2b86500, C4<0>, C4<0>;
+L_0x2b865a0 .delay (20000,20000,20000) L_0x2b865a0/d;
+v0x2641e70_0 .alias "S", 0 0, v0x240f880_0;
+v0x2641ef0_0 .net "in0", 0 0, L_0x2b87060; 1 drivers
+v0x2636810_0 .net "in1", 0 0, L_0x2b86b40; 1 drivers
+v0x26075f0_0 .net "nS", 0 0, L_0x2b86300; 1 drivers
+v0x25f6ae0_0 .net "out0", 0 0, L_0x2b863f0; 1 drivers
+v0x25c78c0_0 .net "out1", 0 0, L_0x2b86500; 1 drivers
+v0x25b2b10_0 .net "outfinal", 0 0, L_0x2b865a0; 1 drivers
+S_0x262aaf0 .scope generate, "sltbits[16]" "sltbits[16]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2317748 .param/l "i" 3 332, +C4<010000>;
+S_0x26318e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x262aaf0;
+ .timescale -9 -12;
+L_0x2b86c30/d .functor NOT 1, L_0x2b873d0, C4<0>, C4<0>, C4<0>;
+L_0x2b86c30 .delay (10000,10000,10000) L_0x2b86c30/d;
+L_0x2b87940/d .functor NOT 1, L_0x2b879e0, C4<0>, C4<0>, C4<0>;
+L_0x2b87940 .delay (10000,10000,10000) L_0x2b87940/d;
+L_0x2b87a80/d .functor AND 1, L_0x2b87bc0, L_0x2b87940, C4<1>, C4<1>;
+L_0x2b87a80 .delay (20000,20000,20000) L_0x2b87a80/d;
+L_0x2b87c60/d .functor XOR 1, L_0x2b87330, L_0x2b87710, C4<0>, C4<0>;
+L_0x2b87c60 .delay (40000,40000,40000) L_0x2b87c60/d;
+L_0x2b87d50/d .functor XOR 1, L_0x2b87c60, L_0x2b87500, C4<0>, C4<0>;
+L_0x2b87d50 .delay (40000,40000,40000) L_0x2b87d50/d;
+L_0x2b87e40/d .functor AND 1, L_0x2b87330, L_0x2b87710, C4<1>, C4<1>;
+L_0x2b87e40 .delay (20000,20000,20000) L_0x2b87e40/d;
+L_0x2b87fb0/d .functor AND 1, L_0x2b87c60, L_0x2b87500, C4<1>, C4<1>;
+L_0x2b87fb0 .delay (20000,20000,20000) L_0x2b87fb0/d;
+L_0x2b880a0/d .functor OR 1, L_0x2b87e40, L_0x2b87fb0, C4<0>, C4<0>;
+L_0x2b880a0 .delay (20000,20000,20000) L_0x2b880a0/d;
+v0x2634490_0 .net "A", 0 0, L_0x2b87330; 1 drivers
+v0x26379b0_0 .net "AandB", 0 0, L_0x2b87e40; 1 drivers
+v0x2637a30_0 .net "AddSubSLTSum", 0 0, L_0x2b87d50; 1 drivers
+v0x2637700_0 .net "AxorB", 0 0, L_0x2b87c60; 1 drivers
+v0x2637780_0 .net "B", 0 0, L_0x2b873d0; 1 drivers
+v0x2636790_0 .net "BornB", 0 0, L_0x2b87710; 1 drivers
+v0x26364e0_0 .net "CINandAxorB", 0 0, L_0x2b87fb0; 1 drivers
+v0x2636560_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x263a4c0_0 .net *"_s3", 0 0, L_0x2b879e0; 1 drivers
+v0x263a540_0 .net *"_s5", 0 0, L_0x2b87bc0; 1 drivers
+v0x263a210_0 .net "carryin", 0 0, L_0x2b87500; 1 drivers
+v0x263a290_0 .net "carryout", 0 0, L_0x2b880a0; 1 drivers
+v0x263d7d0_0 .net "nB", 0 0, L_0x2b86c30; 1 drivers
+v0x263d850_0 .net "nCmd2", 0 0, L_0x2b87940; 1 drivers
+v0x263d5a0_0 .net "subtract", 0 0, L_0x2b87a80; 1 drivers
+L_0x2b878a0 .part v0x2960210_0, 0, 1;
+L_0x2b879e0 .part v0x2960210_0, 2, 1;
+L_0x2b87bc0 .part v0x2960210_0, 0, 1;
+S_0x2630950 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26318e0;
+ .timescale -9 -12;
+L_0x2b86e00/d .functor NOT 1, L_0x2b878a0, C4<0>, C4<0>, C4<0>;
+L_0x2b86e00 .delay (10000,10000,10000) L_0x2b86e00/d;
+L_0x2b86ee0/d .functor AND 1, L_0x2b873d0, L_0x2b86e00, C4<1>, C4<1>;
+L_0x2b86ee0 .delay (20000,20000,20000) L_0x2b86ee0/d;
+L_0x2b86ff0/d .functor AND 1, L_0x2b86c30, L_0x2b878a0, C4<1>, C4<1>;
+L_0x2b86ff0 .delay (20000,20000,20000) L_0x2b86ff0/d;
+L_0x2b87710/d .functor OR 1, L_0x2b86ee0, L_0x2b86ff0, C4<0>, C4<0>;
+L_0x2b87710 .delay (20000,20000,20000) L_0x2b87710/d;
+v0x2631c30_0 .net "S", 0 0, L_0x2b878a0; 1 drivers
+v0x26306a0_0 .alias "in0", 0 0, v0x2637780_0;
+v0x2630740_0 .alias "in1", 0 0, v0x263d7d0_0;
+v0x262dda0_0 .net "nS", 0 0, L_0x2b86e00; 1 drivers
+v0x262de40_0 .net "out0", 0 0, L_0x2b86ee0; 1 drivers
+v0x26346a0_0 .net "out1", 0 0, L_0x2b86ff0; 1 drivers
+v0x26343f0_0 .alias "outfinal", 0 0, v0x2636790_0;
+S_0x262e860 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x262aaf0;
+ .timescale -9 -12;
+L_0x2b875a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b875a0 .delay (10000,10000,10000) L_0x2b875a0/d;
+L_0x2b77380/d .functor AND 1, L_0x2b882d0, L_0x2b875a0, C4<1>, C4<1>;
+L_0x2b77380 .delay (20000,20000,20000) L_0x2b77380/d;
+L_0x2b77450/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b77450 .delay (20000,20000,20000) L_0x2b77450/d;
+L_0x2b774f0/d .functor OR 1, L_0x2b77380, L_0x2b77450, C4<0>, C4<0>;
+L_0x2b774f0 .delay (20000,20000,20000) L_0x2b774f0/d;
+v0x262ff30_0 .alias "S", 0 0, v0x240f880_0;
+v0x262e5b0_0 .net "in0", 0 0, L_0x2b882d0; 1 drivers
+v0x262e650_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x262e300_0 .net "nS", 0 0, L_0x2b875a0; 1 drivers
+v0x262e3a0_0 .net "out0", 0 0, L_0x2b77380; 1 drivers
+v0x262e050_0 .net "out1", 0 0, L_0x2b77450; 1 drivers
+v0x2631b90_0 .net "outfinal", 0 0, L_0x2b774f0; 1 drivers
+S_0x262a840 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x262aaf0;
+ .timescale -9 -12;
+L_0x2b77a10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b77a10 .delay (10000,10000,10000) L_0x2b77a10/d;
+L_0x2b77b00/d .functor AND 1, L_0x2b88d80, L_0x2b77a10, C4<1>, C4<1>;
+L_0x2b77b00 .delay (20000,20000,20000) L_0x2b77b00/d;
+L_0x2b84580/d .functor AND 1, L_0x2b88e70, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b84580 .delay (20000,20000,20000) L_0x2b84580/d;
+L_0x2b84620/d .functor OR 1, L_0x2b77b00, L_0x2b84580, C4<0>, C4<0>;
+L_0x2b84620 .delay (20000,20000,20000) L_0x2b84620/d;
+v0x262bb00_0 .alias "S", 0 0, v0x240f880_0;
+v0x2627f40_0 .net "in0", 0 0, L_0x2b88d80; 1 drivers
+v0x2627fc0_0 .net "in1", 0 0, L_0x2b88e70; 1 drivers
+v0x26303f0_0 .net "nS", 0 0, L_0x2b77a10; 1 drivers
+v0x2630470_0 .net "out0", 0 0, L_0x2b77b00; 1 drivers
+v0x2630140_0 .net "out1", 0 0, L_0x2b84580; 1 drivers
+v0x262fe90_0 .net "outfinal", 0 0, L_0x2b84620; 1 drivers
+S_0x2620090 .scope generate, "sltbits[17]" "sltbits[17]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2309348 .param/l "i" 3 332, +C4<010001>;
+S_0x2622390 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2620090;
+ .timescale -9 -12;
+L_0x2b88f60/d .functor NOT 1, L_0x2b897d0, C4<0>, C4<0>, C4<0>;
+L_0x2b88f60 .delay (10000,10000,10000) L_0x2b88f60/d;
+L_0x2b89eb0/d .functor NOT 1, L_0x2b89f50, C4<0>, C4<0>, C4<0>;
+L_0x2b89eb0 .delay (10000,10000,10000) L_0x2b89eb0/d;
+L_0x2b89ff0/d .functor AND 1, L_0x2b8a130, L_0x2b89eb0, C4<1>, C4<1>;
+L_0x2b89ff0 .delay (20000,20000,20000) L_0x2b89ff0/d;
+L_0x2b8a1d0/d .functor XOR 1, L_0x2b89730, L_0x2b89c80, C4<0>, C4<0>;
+L_0x2b8a1d0 .delay (40000,40000,40000) L_0x2b8a1d0/d;
+L_0x2b8a2c0/d .functor XOR 1, L_0x2b8a1d0, L_0x2b89900, C4<0>, C4<0>;
+L_0x2b8a2c0 .delay (40000,40000,40000) L_0x2b8a2c0/d;
+L_0x2b8a3b0/d .functor AND 1, L_0x2b89730, L_0x2b89c80, C4<1>, C4<1>;
+L_0x2b8a3b0 .delay (20000,20000,20000) L_0x2b8a3b0/d;
+L_0x2b8a520/d .functor AND 1, L_0x2b8a1d0, L_0x2b89900, C4<1>, C4<1>;
+L_0x2b8a520 .delay (20000,20000,20000) L_0x2b8a520/d;
+L_0x2b8a610/d .functor OR 1, L_0x2b8a3b0, L_0x2b8a520, C4<0>, C4<0>;
+L_0x2b8a610 .delay (20000,20000,20000) L_0x2b8a610/d;
+v0x262a590_0 .net "A", 0 0, L_0x2b89730; 1 drivers
+v0x262a2e0_0 .net "AandB", 0 0, L_0x2b8a3b0; 1 drivers
+v0x262a380_0 .net "AddSubSLTSum", 0 0, L_0x2b8a2c0; 1 drivers
+v0x262a030_0 .net "AxorB", 0 0, L_0x2b8a1d0; 1 drivers
+v0x262a0b0_0 .net "B", 0 0, L_0x2b897d0; 1 drivers
+v0x2628a00_0 .net "BornB", 0 0, L_0x2b89c80; 1 drivers
+v0x2628a80_0 .net "CINandAxorB", 0 0, L_0x2b8a520; 1 drivers
+v0x2628750_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26287d0_0 .net *"_s3", 0 0, L_0x2b89f50; 1 drivers
+v0x26284a0_0 .net *"_s5", 0 0, L_0x2b8a130; 1 drivers
+v0x2628520_0 .net "carryin", 0 0, L_0x2b89900; 1 drivers
+v0x26281f0_0 .net "carryout", 0 0, L_0x2b8a610; 1 drivers
+v0x2628270_0 .net "nB", 0 0, L_0x2b88f60; 1 drivers
+v0x262bd30_0 .net "nCmd2", 0 0, L_0x2b89eb0; 1 drivers
+v0x262ba80_0 .net "subtract", 0 0, L_0x2b89ff0; 1 drivers
+L_0x2b89e10 .part v0x2960210_0, 0, 1;
+L_0x2b89f50 .part v0x2960210_0, 2, 1;
+L_0x2b8a130 .part v0x2960210_0, 0, 1;
+S_0x2625ed0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2622390;
+ .timescale -9 -12;
+L_0x2b89130/d .functor NOT 1, L_0x2b89e10, C4<0>, C4<0>, C4<0>;
+L_0x2b89130 .delay (10000,10000,10000) L_0x2b89130/d;
+L_0x2b891f0/d .functor AND 1, L_0x2b897d0, L_0x2b89130, C4<1>, C4<1>;
+L_0x2b891f0 .delay (20000,20000,20000) L_0x2b891f0/d;
+L_0x2b89bd0/d .functor AND 1, L_0x2b88f60, L_0x2b89e10, C4<1>, C4<1>;
+L_0x2b89bd0 .delay (20000,20000,20000) L_0x2b89bd0/d;
+L_0x2b89c80/d .functor OR 1, L_0x2b891f0, L_0x2b89bd0, C4<0>, C4<0>;
+L_0x2b89c80 .delay (20000,20000,20000) L_0x2b89c80/d;
+v0x2625c20_0 .net "S", 0 0, L_0x2b89e10; 1 drivers
+v0x2624c90_0 .alias "in0", 0 0, v0x262a0b0_0;
+v0x2624d30_0 .alias "in1", 0 0, v0x2628270_0;
+v0x26249e0_0 .net "nS", 0 0, L_0x2b89130; 1 drivers
+v0x2624a60_0 .net "out0", 0 0, L_0x2b891f0; 1 drivers
+v0x26220e0_0 .net "out1", 0 0, L_0x2b89bd0; 1 drivers
+v0x2622180_0 .alias "outfinal", 0 0, v0x2628a00_0;
+S_0x26241d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2620090;
+ .timescale -9 -12;
+L_0x2b899a0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b899a0 .delay (10000,10000,10000) L_0x2b899a0/d;
+L_0x2b89a20/d .functor AND 1, L_0x2b681c0, L_0x2b899a0, C4<1>, C4<1>;
+L_0x2b89a20 .delay (20000,20000,20000) L_0x2b89a20/d;
+L_0x2b89b30/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b89b30 .delay (20000,20000,20000) L_0x2b89b30/d;
+L_0x2b67fc0/d .functor OR 1, L_0x2b89a20, L_0x2b89b30, C4<0>, C4<0>;
+L_0x2b67fc0 .delay (20000,20000,20000) L_0x2b67fc0/d;
+v0x2624520_0 .alias "S", 0 0, v0x240f880_0;
+v0x2622ba0_0 .net "in0", 0 0, L_0x2b681c0; 1 drivers
+v0x2622c40_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x26228f0_0 .net "nS", 0 0, L_0x2b899a0; 1 drivers
+v0x2622990_0 .net "out0", 0 0, L_0x2b89a20; 1 drivers
+v0x2622640_0 .net "out1", 0 0, L_0x2b89b30; 1 drivers
+v0x26226e0_0 .net "outfinal", 0 0, L_0x2b67fc0; 1 drivers
+S_0x261fde0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2620090;
+ .timescale -9 -12;
+L_0x2b68340/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b68340 .delay (10000,10000,10000) L_0x2b68340/d;
+L_0x2b68470/d .functor AND 1, L_0x2b8a9d0, L_0x2b68340, C4<1>, C4<1>;
+L_0x2b68470 .delay (20000,20000,20000) L_0x2b68470/d;
+L_0x2b68580/d .functor AND 1, L_0x2b8aac0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b68580 .delay (20000,20000,20000) L_0x2b68580/d;
+L_0x2b68620/d .functor OR 1, L_0x2b68470, L_0x2b68580, C4<0>, C4<0>;
+L_0x2b68620 .delay (20000,20000,20000) L_0x2b68620/d;
+v0x261cb50_0 .alias "S", 0 0, v0x240f880_0;
+v0x261ee70_0 .net "in0", 0 0, L_0x2b8a9d0; 1 drivers
+v0x261eef0_0 .net "in1", 0 0, L_0x2b8aac0; 1 drivers
+v0x261ebc0_0 .net "nS", 0 0, L_0x2b68340; 1 drivers
+v0x261ec40_0 .net "out0", 0 0, L_0x2b68470; 1 drivers
+v0x2624730_0 .net "out1", 0 0, L_0x2b68580; 1 drivers
+v0x2624480_0 .net "outfinal", 0 0, L_0x2b68620; 1 drivers
+S_0x260b030 .scope generate, "sltbits[18]" "sltbits[18]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x23000c8 .param/l "i" 3 332, +C4<010010>;
+S_0x2610930 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x260b030;
+ .timescale -9 -12;
+L_0x2b8abb0/d .functor NOT 1, L_0x2b8c180, C4<0>, C4<0>, C4<0>;
+L_0x2b8abb0 .delay (10000,10000,10000) L_0x2b8abb0/d;
+L_0x2b8c850/d .functor NOT 1, L_0x2b8c8f0, C4<0>, C4<0>, C4<0>;
+L_0x2b8c850 .delay (10000,10000,10000) L_0x2b8c850/d;
+L_0x2b8c990/d .functor AND 1, L_0x2b8cad0, L_0x2b8c850, C4<1>, C4<1>;
+L_0x2b8c990 .delay (20000,20000,20000) L_0x2b8c990/d;
+L_0x2b8cb70/d .functor XOR 1, L_0x2b8c0e0, L_0x2b8c620, C4<0>, C4<0>;
+L_0x2b8cb70 .delay (40000,40000,40000) L_0x2b8cb70/d;
+L_0x2b8cc60/d .functor XOR 1, L_0x2b8cb70, L_0x2b8c2b0, C4<0>, C4<0>;
+L_0x2b8cc60 .delay (40000,40000,40000) L_0x2b8cc60/d;
+L_0x2b8cd50/d .functor AND 1, L_0x2b8c0e0, L_0x2b8c620, C4<1>, C4<1>;
+L_0x2b8cd50 .delay (20000,20000,20000) L_0x2b8cd50/d;
+L_0x2b8cec0/d .functor AND 1, L_0x2b8cb70, L_0x2b8c2b0, C4<1>, C4<1>;
+L_0x2b8cec0 .delay (20000,20000,20000) L_0x2b8cec0/d;
+L_0x2b8cfb0/d .functor OR 1, L_0x2b8cd50, L_0x2b8cec0, C4<0>, C4<0>;
+L_0x2b8cfb0 .delay (20000,20000,20000) L_0x2b8cfb0/d;
+v0x2610720_0 .net "A", 0 0, L_0x2b8c0e0; 1 drivers
+v0x2616f60_0 .net "AandB", 0 0, L_0x2b8cd50; 1 drivers
+v0x2617000_0 .net "AddSubSLTSum", 0 0, L_0x2b8cc60; 1 drivers
+v0x2616cb0_0 .net "AxorB", 0 0, L_0x2b8cb70; 1 drivers
+v0x2616d30_0 .net "B", 0 0, L_0x2b8c180; 1 drivers
+v0x261a270_0 .net "BornB", 0 0, L_0x2b8c620; 1 drivers
+v0x261a2f0_0 .net "CINandAxorB", 0 0, L_0x2b8cec0; 1 drivers
+v0x2619fc0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x261a040_0 .net *"_s3", 0 0, L_0x2b8c8f0; 1 drivers
+v0x2619050_0 .net *"_s5", 0 0, L_0x2b8cad0; 1 drivers
+v0x26190d0_0 .net "carryin", 0 0, L_0x2b8c2b0; 1 drivers
+v0x2618da0_0 .net "carryout", 0 0, L_0x2b8cfb0; 1 drivers
+v0x2618e20_0 .net "nB", 0 0, L_0x2b8abb0; 1 drivers
+v0x261cd80_0 .net "nCmd2", 0 0, L_0x2b8c850; 1 drivers
+v0x261cad0_0 .net "subtract", 0 0, L_0x2b8c990; 1 drivers
+L_0x2b8c7b0 .part v0x2960210_0, 0, 1;
+L_0x2b8c8f0 .part v0x2960210_0, 2, 1;
+L_0x2b8cad0 .part v0x2960210_0, 0, 1;
+S_0x2614450 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2610930;
+ .timescale -9 -12;
+L_0x2b8ad80/d .functor NOT 1, L_0x2b8c7b0, C4<0>, C4<0>, C4<0>;
+L_0x2b8ad80 .delay (10000,10000,10000) L_0x2b8ad80/d;
+L_0x2b8ae60/d .functor AND 1, L_0x2b8c180, L_0x2b8ad80, C4<1>, C4<1>;
+L_0x2b8ae60 .delay (20000,20000,20000) L_0x2b8ae60/d;
+L_0x2b8c530/d .functor AND 1, L_0x2b8abb0, L_0x2b8c7b0, C4<1>, C4<1>;
+L_0x2b8c530 .delay (20000,20000,20000) L_0x2b8c530/d;
+L_0x2b8c620/d .functor OR 1, L_0x2b8ae60, L_0x2b8c530, C4<0>, C4<0>;
+L_0x2b8c620 .delay (20000,20000,20000) L_0x2b8c620/d;
+v0x2610c80_0 .net "S", 0 0, L_0x2b8c7b0; 1 drivers
+v0x26141a0_0 .alias "in0", 0 0, v0x2616d30_0;
+v0x2614240_0 .alias "in1", 0 0, v0x2618e20_0;
+v0x2613230_0 .net "nS", 0 0, L_0x2b8ad80; 1 drivers
+v0x26132b0_0 .net "out0", 0 0, L_0x2b8ae60; 1 drivers
+v0x2612f80_0 .net "out1", 0 0, L_0x2b8c530; 1 drivers
+v0x2610680_0 .alias "outfinal", 0 0, v0x261a270_0;
+S_0x260d120 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x260b030;
+ .timescale -9 -12;
+L_0x2b8c350/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b8c350 .delay (10000,10000,10000) L_0x2b8c350/d;
+L_0x2b8c3f0/d .functor AND 1, L_0x2b8d1e0, L_0x2b8c350, C4<1>, C4<1>;
+L_0x2b8c3f0 .delay (20000,20000,20000) L_0x2b8c3f0/d;
+L_0x2b8d840/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b8d840 .delay (20000,20000,20000) L_0x2b8d840/d;
+L_0x2b8d8e0/d .functor OR 1, L_0x2b8c3f0, L_0x2b8d840, C4<0>, C4<0>;
+L_0x2b8d8e0 .delay (20000,20000,20000) L_0x2b8d8e0/d;
+v0x260d470_0 .alias "S", 0 0, v0x240f880_0;
+v0x260a820_0 .net "in0", 0 0, L_0x2b8d1e0; 1 drivers
+v0x260a8c0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2611140_0 .net "nS", 0 0, L_0x2b8c350; 1 drivers
+v0x26111e0_0 .net "out0", 0 0, L_0x2b8c3f0; 1 drivers
+v0x2610e90_0 .net "out1", 0 0, L_0x2b8d840; 1 drivers
+v0x2610be0_0 .net "outfinal", 0 0, L_0x2b8d8e0; 1 drivers
+S_0x260ad80 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x260b030;
+ .timescale -9 -12;
+L_0x2b8d620/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b8d620 .delay (10000,10000,10000) L_0x2b8d620/d;
+L_0x2b8d730/d .functor AND 1, L_0x2b8dac0, L_0x2b8d620, C4<1>, C4<1>;
+L_0x2b8d730 .delay (20000,20000,20000) L_0x2b8d730/d;
+L_0x2b89340/d .functor AND 1, L_0x2b8dbb0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b89340 .delay (20000,20000,20000) L_0x2b89340/d;
+L_0x2b893e0/d .functor OR 1, L_0x2b8d730, L_0x2b89340, C4<0>, C4<0>;
+L_0x2b893e0 .delay (20000,20000,20000) L_0x2b893e0/d;
+v0x260b360_0 .alias "S", 0 0, v0x240f880_0;
+v0x260aad0_0 .net "in0", 0 0, L_0x2b8dac0; 1 drivers
+v0x260ab50_0 .net "in1", 0 0, L_0x2b8dbb0; 1 drivers
+v0x260e610_0 .net "nS", 0 0, L_0x2b8d620; 1 drivers
+v0x260e690_0 .net "out0", 0 0, L_0x2b8d730; 1 drivers
+v0x260e360_0 .net "out1", 0 0, L_0x2b89340; 1 drivers
+v0x260d3d0_0 .net "outfinal", 0 0, L_0x2b893e0; 1 drivers
+S_0x25fc880 .scope generate, "sltbits[19]" "sltbits[19]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x22d5328 .param/l "i" 3 332, +C4<010011>;
+S_0x2606d60 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25fc880;
+ .timescale -9 -12;
+L_0x2b8dca0/d .functor NOT 1, L_0x2b8e310, C4<0>, C4<0>, C4<0>;
+L_0x2b8dca0 .delay (10000,10000,10000) L_0x2b8dca0/d;
+L_0x2b8ea00/d .functor NOT 1, L_0x2b8eaa0, C4<0>, C4<0>, C4<0>;
+L_0x2b8ea00 .delay (10000,10000,10000) L_0x2b8ea00/d;
+L_0x2b8eb40/d .functor AND 1, L_0x2b8ec80, L_0x2b8ea00, C4<1>, C4<1>;
+L_0x2b8eb40 .delay (20000,20000,20000) L_0x2b8eb40/d;
+L_0x2b8ed20/d .functor XOR 1, L_0x2b8e270, L_0x2b8e810, C4<0>, C4<0>;
+L_0x2b8ed20 .delay (40000,40000,40000) L_0x2b8ed20/d;
+L_0x2b8ee10/d .functor XOR 1, L_0x2b8ed20, L_0x2b8e440, C4<0>, C4<0>;
+L_0x2b8ee10 .delay (40000,40000,40000) L_0x2b8ee10/d;
+L_0x2b8ef00/d .functor AND 1, L_0x2b8e270, L_0x2b8e810, C4<1>, C4<1>;
+L_0x2b8ef00 .delay (20000,20000,20000) L_0x2b8ef00/d;
+L_0x2b8f070/d .functor AND 1, L_0x2b8ed20, L_0x2b8e440, C4<1>, C4<1>;
+L_0x2b8f070 .delay (20000,20000,20000) L_0x2b8f070/d;
+L_0x2b8f160/d .functor OR 1, L_0x2b8ef00, L_0x2b8f070, C4<0>, C4<0>;
+L_0x2b8f160 .delay (20000,20000,20000) L_0x2b8f160/d;
+v0x2604c70_0 .net "A", 0 0, L_0x2b8e270; 1 drivers
+v0x26087b0_0 .net "AandB", 0 0, L_0x2b8ef00; 1 drivers
+v0x2608850_0 .net "AddSubSLTSum", 0 0, L_0x2b8ee10; 1 drivers
+v0x2608500_0 .net "AxorB", 0 0, L_0x2b8ed20; 1 drivers
+v0x2608580_0 .net "B", 0 0, L_0x2b8e310; 1 drivers
+v0x2607570_0 .net "BornB", 0 0, L_0x2b8e810; 1 drivers
+v0x26072c0_0 .net "CINandAxorB", 0 0, L_0x2b8f070; 1 drivers
+v0x2607340_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26049c0_0 .net *"_s3", 0 0, L_0x2b8eaa0; 1 drivers
+v0x2604a40_0 .net *"_s5", 0 0, L_0x2b8ec80; 1 drivers
+v0x260ce70_0 .net "carryin", 0 0, L_0x2b8e440; 1 drivers
+v0x260cef0_0 .net "carryout", 0 0, L_0x2b8f160; 1 drivers
+v0x260cbc0_0 .net "nB", 0 0, L_0x2b8dca0; 1 drivers
+v0x260c910_0 .net "nCmd2", 0 0, L_0x2b8ea00; 1 drivers
+v0x260b2e0_0 .net "subtract", 0 0, L_0x2b8eb40; 1 drivers
+L_0x2b8e960 .part v0x2960210_0, 0, 1;
+L_0x2b8eaa0 .part v0x2960210_0, 2, 1;
+L_0x2b8ec80 .part v0x2960210_0, 0, 1;
+S_0x2606ab0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2606d60;
+ .timescale -9 -12;
+L_0x2b8de70/d .functor NOT 1, L_0x2b8e960, C4<0>, C4<0>, C4<0>;
+L_0x2b8de70 .delay (10000,10000,10000) L_0x2b8de70/d;
+L_0x2b8df50/d .functor AND 1, L_0x2b8e310, L_0x2b8de70, C4<1>, C4<1>;
+L_0x2b8df50 .delay (20000,20000,20000) L_0x2b8df50/d;
+L_0x2b8e080/d .functor AND 1, L_0x2b8dca0, L_0x2b8e960, C4<1>, C4<1>;
+L_0x2b8e080 .delay (20000,20000,20000) L_0x2b8e080/d;
+L_0x2b8e810/d .functor OR 1, L_0x2b8df50, L_0x2b8e080, C4<0>, C4<0>;
+L_0x2b8e810 .delay (20000,20000,20000) L_0x2b8e810/d;
+v0x26070b0_0 .net "S", 0 0, L_0x2b8e960; 1 drivers
+v0x2605480_0 .alias "in0", 0 0, v0x2608580_0;
+v0x2605520_0 .alias "in1", 0 0, v0x260cbc0_0;
+v0x26051d0_0 .net "nS", 0 0, L_0x2b8de70; 1 drivers
+v0x2605270_0 .net "out0", 0 0, L_0x2b8df50; 1 drivers
+v0x2604f20_0 .net "out1", 0 0, L_0x2b8e080; 1 drivers
+v0x2604fc0_0 .alias "outfinal", 0 0, v0x2607570_0;
+S_0x26026a0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25fc880;
+ .timescale -9 -12;
+L_0x2b8e4e0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b8e4e0 .delay (10000,10000,10000) L_0x2b8e4e0/d;
+L_0x2b8e580/d .functor AND 1, L_0x2b8fc70, L_0x2b8e4e0, C4<1>, C4<1>;
+L_0x2b8e580 .delay (20000,20000,20000) L_0x2b8e580/d;
+L_0x2b8e690/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b8e690 .delay (20000,20000,20000) L_0x2b8e690/d;
+L_0x2b8e730/d .functor OR 1, L_0x2b8e580, L_0x2b8e690, C4<0>, C4<0>;
+L_0x2b8e730 .delay (20000,20000,20000) L_0x2b8e730/d;
+v0x26029d0_0 .alias "S", 0 0, v0x240f880_0;
+v0x26023f0_0 .net "in0", 0 0, L_0x2b8fc70; 1 drivers
+v0x2602470_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2601730_0 .net "nS", 0 0, L_0x2b8e4e0; 1 drivers
+v0x26017b0_0 .net "out0", 0 0, L_0x2b8e580; 1 drivers
+v0x2601480_0 .net "out1", 0 0, L_0x2b8e690; 1 drivers
+v0x2607010_0 .net "outfinal", 0 0, L_0x2b8e730; 1 drivers
+S_0x25fb910 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25fc880;
+ .timescale -9 -12;
+L_0x2b8f510/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b8f510 .delay (10000,10000,10000) L_0x2b8f510/d;
+L_0x2b8f620/d .functor AND 1, L_0x2b8f9b0, L_0x2b8f510, C4<1>, C4<1>;
+L_0x2b8f620 .delay (20000,20000,20000) L_0x2b8f620/d;
+L_0x2b8f730/d .functor AND 1, L_0x2b903f0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b8f730 .delay (20000,20000,20000) L_0x2b8f730/d;
+L_0x2b8f7d0/d .functor OR 1, L_0x2b8f620, L_0x2b8f730, C4<0>, C4<0>;
+L_0x2b8f7d0 .delay (20000,20000,20000) L_0x2b8f7d0/d;
+v0x25fb660_0 .alias "S", 0 0, v0x240f880_0;
+v0x25fb6e0_0 .net "in0", 0 0, L_0x2b8f9b0; 1 drivers
+v0x25ff640_0 .net "in1", 0 0, L_0x2b903f0; 1 drivers
+v0x25ff6c0_0 .net "nS", 0 0, L_0x2b8f510; 1 drivers
+v0x25ff390_0 .net "out0", 0 0, L_0x2b8f620; 1 drivers
+v0x25ff410_0 .net "out1", 0 0, L_0x2b8f730; 1 drivers
+v0x2602950_0 .net "outfinal", 0 0, L_0x2b8f7d0; 1 drivers
+S_0x25eadc0 .scope generate, "sltbits[20]" "sltbits[20]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x22afe78 .param/l "i" 3 332, +C4<010100>;
+S_0x25f0ed0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25eadc0;
+ .timescale -9 -12;
+L_0x2b90490/d .functor NOT 1, L_0x2b8ffe0, C4<0>, C4<0>, C4<0>;
+L_0x2b90490 .delay (10000,10000,10000) L_0x2b90490/d;
+L_0x2b90ad0/d .functor NOT 1, L_0x2b90b70, C4<0>, C4<0>, C4<0>;
+L_0x2b90ad0 .delay (10000,10000,10000) L_0x2b90ad0/d;
+L_0x2b90c10/d .functor AND 1, L_0x2b90d50, L_0x2b90ad0, C4<1>, C4<1>;
+L_0x2b90c10 .delay (20000,20000,20000) L_0x2b90c10/d;
+L_0x2b90df0/d .functor XOR 1, L_0x2b8ff40, L_0x2b908a0, C4<0>, C4<0>;
+L_0x2b90df0 .delay (40000,40000,40000) L_0x2b90df0/d;
+L_0x2b90ee0/d .functor XOR 1, L_0x2b90df0, L_0x2b90110, C4<0>, C4<0>;
+L_0x2b90ee0 .delay (40000,40000,40000) L_0x2b90ee0/d;
+L_0x2b90fd0/d .functor AND 1, L_0x2b8ff40, L_0x2b908a0, C4<1>, C4<1>;
+L_0x2b90fd0 .delay (20000,20000,20000) L_0x2b90fd0/d;
+L_0x2b91140/d .functor AND 1, L_0x2b90df0, L_0x2b90110, C4<1>, C4<1>;
+L_0x2b91140 .delay (20000,20000,20000) L_0x2b91140/d;
+L_0x2b91230/d .functor OR 1, L_0x2b90fd0, L_0x2b91140, C4<0>, C4<0>;
+L_0x2b91230 .delay (20000,20000,20000) L_0x2b91230/d;
+v0x25f3aa0_0 .net "A", 0 0, L_0x2b8ff40; 1 drivers
+v0x25f3750_0 .net "AandB", 0 0, L_0x2b90fd0; 1 drivers
+v0x25f37d0_0 .net "AddSubSLTSum", 0 0, L_0x2b90ee0; 1 drivers
+v0x25f6d10_0 .net "AxorB", 0 0, L_0x2b90df0; 1 drivers
+v0x25f6d90_0 .net "B", 0 0, L_0x2b8ffe0; 1 drivers
+v0x25f6a60_0 .net "BornB", 0 0, L_0x2b908a0; 1 drivers
+v0x25f5af0_0 .net "CINandAxorB", 0 0, L_0x2b91140; 1 drivers
+v0x25f5b70_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25f5840_0 .net *"_s3", 0 0, L_0x2b90b70; 1 drivers
+v0x25f58c0_0 .net *"_s5", 0 0, L_0x2b90d50; 1 drivers
+v0x25f9820_0 .net "carryin", 0 0, L_0x2b90110; 1 drivers
+v0x25f98a0_0 .net "carryout", 0 0, L_0x2b91230; 1 drivers
+v0x25f9570_0 .net "nB", 0 0, L_0x2b90490; 1 drivers
+v0x25f95f0_0 .net "nCmd2", 0 0, L_0x2b90ad0; 1 drivers
+v0x25fcbb0_0 .net "subtract", 0 0, L_0x2b90c10; 1 drivers
+L_0x2b90a30 .part v0x2960210_0, 0, 1;
+L_0x2b90b70 .part v0x2960210_0, 2, 1;
+L_0x2b90d50 .part v0x2960210_0, 0, 1;
+S_0x25f0c20 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25f0ed0;
+ .timescale -9 -12;
+L_0x2b90620/d .functor NOT 1, L_0x2b90a30, C4<0>, C4<0>, C4<0>;
+L_0x2b90620 .delay (10000,10000,10000) L_0x2b90620/d;
+L_0x2b906c0/d .functor AND 1, L_0x2b8ffe0, L_0x2b90620, C4<1>, C4<1>;
+L_0x2b906c0 .delay (20000,20000,20000) L_0x2b906c0/d;
+L_0x2b907b0/d .functor AND 1, L_0x2b90490, L_0x2b90a30, C4<1>, C4<1>;
+L_0x2b907b0 .delay (20000,20000,20000) L_0x2b907b0/d;
+L_0x2b908a0/d .functor OR 1, L_0x2b906c0, L_0x2b907b0, C4<0>, C4<0>;
+L_0x2b908a0 .delay (20000,20000,20000) L_0x2b908a0/d;
+v0x25ed430_0 .net "S", 0 0, L_0x2b90a30; 1 drivers
+v0x25efc90_0 .alias "in0", 0 0, v0x25f6d90_0;
+v0x25efd30_0 .alias "in1", 0 0, v0x25f9570_0;
+v0x25ef9e0_0 .net "nS", 0 0, L_0x2b90620; 1 drivers
+v0x25efa80_0 .net "out0", 0 0, L_0x2b906c0; 1 drivers
+v0x25ed0e0_0 .net "out1", 0 0, L_0x2b907b0; 1 drivers
+v0x25f3a00_0 .alias "outfinal", 0 0, v0x25f6a60_0;
+S_0x25ef1d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25eadc0;
+ .timescale -9 -12;
+L_0x2b901b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b901b0 .delay (10000,10000,10000) L_0x2b901b0/d;
+L_0x2b90250/d .functor AND 1, L_0x2b91460, L_0x2b901b0, C4<1>, C4<1>;
+L_0x2b90250 .delay (20000,20000,20000) L_0x2b90250/d;
+L_0x2b90360/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b90360 .delay (20000,20000,20000) L_0x2b90360/d;
+L_0x2b91b60/d .functor OR 1, L_0x2b90250, L_0x2b90360, C4<0>, C4<0>;
+L_0x2b91b60 .delay (20000,20000,20000) L_0x2b91b60/d;
+v0x25ef520_0 .alias "S", 0 0, v0x240f880_0;
+v0x25edba0_0 .net "in0", 0 0, L_0x2b91460; 1 drivers
+v0x25edc40_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x25ed8f0_0 .net "nS", 0 0, L_0x2b901b0; 1 drivers
+v0x25ed990_0 .net "out0", 0 0, L_0x2b90250; 1 drivers
+v0x25ed640_0 .net "out1", 0 0, L_0x2b90360; 1 drivers
+v0x25ed390_0 .net "outfinal", 0 0, L_0x2b91b60; 1 drivers
+S_0x25e9e30 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25eadc0;
+ .timescale -9 -12;
+L_0x2b918b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b918b0 .delay (10000,10000,10000) L_0x2b918b0/d;
+L_0x2b919c0/d .functor AND 1, L_0x2b92420, L_0x2b918b0, C4<1>, C4<1>;
+L_0x2b919c0 .delay (20000,20000,20000) L_0x2b919c0/d;
+L_0x2b8d360/d .functor AND 1, L_0x2b924c0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b8d360 .delay (20000,20000,20000) L_0x2b8d360/d;
+L_0x2b8d400/d .functor OR 1, L_0x2b919c0, L_0x2b8d360, C4<0>, C4<0>;
+L_0x2b8d400 .delay (20000,20000,20000) L_0x2b8d400/d;
+v0x25eb0f0_0 .alias "S", 0 0, v0x240f880_0;
+v0x25e9b80_0 .net "in0", 0 0, L_0x2b92420; 1 drivers
+v0x25e9c00_0 .net "in1", 0 0, L_0x2b924c0; 1 drivers
+v0x25e7280_0 .net "nS", 0 0, L_0x2b918b0; 1 drivers
+v0x25e7300_0 .net "out0", 0 0, L_0x2b919c0; 1 drivers
+v0x25ef730_0 .net "out1", 0 0, L_0x2b8d360; 1 drivers
+v0x25ef480_0 .net "outfinal", 0 0, L_0x2b8d400; 1 drivers
+S_0x25d80e0 .scope generate, "sltbits[21]" "sltbits[21]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x228a9a8 .param/l "i" 3 332, +C4<010101>;
+S_0x25e1ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25d80e0;
+ .timescale -9 -12;
+L_0x2b91d40/d .functor NOT 1, L_0x2b92740, C4<0>, C4<0>, C4<0>;
+L_0x2b91d40 .delay (10000,10000,10000) L_0x2b91d40/d;
+L_0x2b92ca0/d .functor NOT 1, L_0x2b92d40, C4<0>, C4<0>, C4<0>;
+L_0x2b92ca0 .delay (10000,10000,10000) L_0x2b92ca0/d;
+L_0x2b92de0/d .functor AND 1, L_0x2b92f20, L_0x2b92ca0, C4<1>, C4<1>;
+L_0x2b92de0 .delay (20000,20000,20000) L_0x2b92de0/d;
+L_0x2b92fc0/d .functor XOR 1, L_0x2b926a0, L_0x2b921b0, C4<0>, C4<0>;
+L_0x2b92fc0 .delay (40000,40000,40000) L_0x2b92fc0/d;
+L_0x2b930b0/d .functor XOR 1, L_0x2b92fc0, L_0x2b92870, C4<0>, C4<0>;
+L_0x2b930b0 .delay (40000,40000,40000) L_0x2b930b0/d;
+L_0x2b931a0/d .functor AND 1, L_0x2b926a0, L_0x2b921b0, C4<1>, C4<1>;
+L_0x2b931a0 .delay (20000,20000,20000) L_0x2b931a0/d;
+L_0x2b93310/d .functor AND 1, L_0x2b92fc0, L_0x2b92870, C4<1>, C4<1>;
+L_0x2b93310 .delay (20000,20000,20000) L_0x2b93310/d;
+L_0x2b93400/d .functor OR 1, L_0x2b931a0, L_0x2b93310, C4<0>, C4<0>;
+L_0x2b93400 .delay (20000,20000,20000) L_0x2b93400/d;
+v0x25e3d20_0 .net "A", 0 0, L_0x2b926a0; 1 drivers
+v0x25e98d0_0 .net "AandB", 0 0, L_0x2b931a0; 1 drivers
+v0x25e9970_0 .net "AddSubSLTSum", 0 0, L_0x2b930b0; 1 drivers
+v0x25e9620_0 .net "AxorB", 0 0, L_0x2b92fc0; 1 drivers
+v0x25e96a0_0 .net "B", 0 0, L_0x2b92740; 1 drivers
+v0x25e9370_0 .net "BornB", 0 0, L_0x2b921b0; 1 drivers
+v0x25e93f0_0 .net "CINandAxorB", 0 0, L_0x2b93310; 1 drivers
+v0x25e7d40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25e7dc0_0 .net *"_s3", 0 0, L_0x2b92d40; 1 drivers
+v0x25e7a90_0 .net *"_s5", 0 0, L_0x2b92f20; 1 drivers
+v0x25e7b10_0 .net "carryin", 0 0, L_0x2b92870; 1 drivers
+v0x25e77e0_0 .net "carryout", 0 0, L_0x2b93400; 1 drivers
+v0x25e7860_0 .net "nB", 0 0, L_0x2b91d40; 1 drivers
+v0x25e7530_0 .net "nCmd2", 0 0, L_0x2b92ca0; 1 drivers
+v0x25eb070_0 .net "subtract", 0 0, L_0x2b92de0; 1 drivers
+L_0x2b92380 .part v0x2960210_0, 0, 1;
+L_0x2b92d40 .part v0x2960210_0, 2, 1;
+L_0x2b92f20 .part v0x2960210_0, 0, 1;
+S_0x25e1c30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25e1ee0;
+ .timescale -9 -12;
+L_0x2b91ed0/d .functor NOT 1, L_0x2b92380, C4<0>, C4<0>, C4<0>;
+L_0x2b91ed0 .delay (10000,10000,10000) L_0x2b91ed0/d;
+L_0x2b91f90/d .functor AND 1, L_0x2b92740, L_0x2b91ed0, C4<1>, C4<1>;
+L_0x2b91f90 .delay (20000,20000,20000) L_0x2b91f90/d;
+L_0x2b920a0/d .functor AND 1, L_0x2b91d40, L_0x2b92380, C4<1>, C4<1>;
+L_0x2b920a0 .delay (20000,20000,20000) L_0x2b920a0/d;
+L_0x2b921b0/d .functor OR 1, L_0x2b91f90, L_0x2b920a0, C4<0>, C4<0>;
+L_0x2b921b0 .delay (20000,20000,20000) L_0x2b921b0/d;
+v0x25e1980_0 .net "S", 0 0, L_0x2b92380; 1 drivers
+v0x25e5210_0 .alias "in0", 0 0, v0x25e96a0_0;
+v0x25e52b0_0 .alias "in1", 0 0, v0x25e7860_0;
+v0x25e4f60_0 .net "nS", 0 0, L_0x2b91ed0; 1 drivers
+v0x25e4fe0_0 .net "out0", 0 0, L_0x2b91f90; 1 drivers
+v0x25e3fd0_0 .net "out1", 0 0, L_0x2b920a0; 1 drivers
+v0x25e4070_0 .alias "outfinal", 0 0, v0x25e9370_0;
+S_0x25ddf00 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25d80e0;
+ .timescale -9 -12;
+L_0x2b92910/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b92910 .delay (10000,10000,10000) L_0x2b92910/d;
+L_0x2b929b0/d .functor AND 1, L_0x2b93f30, L_0x2b92910, C4<1>, C4<1>;
+L_0x2b929b0 .delay (20000,20000,20000) L_0x2b929b0/d;
+L_0x2b92ac0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b92ac0 .delay (20000,20000,20000) L_0x2b92ac0/d;
+L_0x2b92b60/d .functor OR 1, L_0x2b929b0, L_0x2b92ac0, C4<0>, C4<0>;
+L_0x2b92b60 .delay (20000,20000,20000) L_0x2b92b60/d;
+v0x25de250_0 .alias "S", 0 0, v0x240f880_0;
+v0x25e3a70_0 .net "in0", 0 0, L_0x2b93f30; 1 drivers
+v0x25e3b10_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x25e37c0_0 .net "nS", 0 0, L_0x2b92910; 1 drivers
+v0x25e3860_0 .net "out0", 0 0, L_0x2b929b0; 1 drivers
+v0x25e3510_0 .net "out1", 0 0, L_0x2b92ac0; 1 drivers
+v0x25e35b0_0 .net "outfinal", 0 0, L_0x2b92b60; 1 drivers
+S_0x25dc0c0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25d80e0;
+ .timescale -9 -12;
+L_0x2b937b0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b937b0 .delay (10000,10000,10000) L_0x2b937b0/d;
+L_0x2b938c0/d .functor AND 1, L_0x2b93c50, L_0x2b937b0, C4<1>, C4<1>;
+L_0x2b938c0 .delay (20000,20000,20000) L_0x2b938c0/d;
+L_0x2b939d0/d .functor AND 1, L_0x2b93d40, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b939d0 .delay (20000,20000,20000) L_0x2b939d0/d;
+L_0x2b93a70/d .functor OR 1, L_0x2b938c0, L_0x2b939d0, C4<0>, C4<0>;
+L_0x2b93a70 .delay (20000,20000,20000) L_0x2b93a70/d;
+v0x25d8410_0 .alias "S", 0 0, v0x240f880_0;
+v0x25dbe10_0 .net "in0", 0 0, L_0x2b93c50; 1 drivers
+v0x25dbe90_0 .net "in1", 0 0, L_0x2b93d40; 1 drivers
+v0x25df3d0_0 .net "nS", 0 0, L_0x2b937b0; 1 drivers
+v0x25df450_0 .net "out0", 0 0, L_0x2b938c0; 1 drivers
+v0x25df120_0 .net "out1", 0 0, L_0x2b939d0; 1 drivers
+v0x25de1b0_0 .net "outfinal", 0 0, L_0x2b93a70; 1 drivers
+S_0x25ca620 .scope generate, "sltbits[22]" "sltbits[22]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x227baf8 .param/l "i" 3 332, +C4<010110>;
+S_0x25d0480 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25ca620;
+ .timescale -9 -12;
+L_0x2b94760/d .functor NOT 1, L_0x2b942a0, C4<0>, C4<0>, C4<0>;
+L_0x2b94760 .delay (10000,10000,10000) L_0x2b94760/d;
+L_0x2b94da0/d .functor NOT 1, L_0x2b94e40, C4<0>, C4<0>, C4<0>;
+L_0x2b94da0 .delay (10000,10000,10000) L_0x2b94da0/d;
+L_0x2b94ee0/d .functor AND 1, L_0x2b95020, L_0x2b94da0, C4<1>, C4<1>;
+L_0x2b94ee0 .delay (20000,20000,20000) L_0x2b94ee0/d;
+L_0x2b950c0/d .functor XOR 1, L_0x2b94200, L_0x2b94b70, C4<0>, C4<0>;
+L_0x2b950c0 .delay (40000,40000,40000) L_0x2b950c0/d;
+L_0x2b951b0/d .functor XOR 1, L_0x2b950c0, L_0x2b943d0, C4<0>, C4<0>;
+L_0x2b951b0 .delay (40000,40000,40000) L_0x2b951b0/d;
+L_0x2b952a0/d .functor AND 1, L_0x2b94200, L_0x2b94b70, C4<1>, C4<1>;
+L_0x2b952a0 .delay (20000,20000,20000) L_0x2b952a0/d;
+L_0x2b95410/d .functor AND 1, L_0x2b950c0, L_0x2b943d0, C4<1>, C4<1>;
+L_0x2b95410 .delay (20000,20000,20000) L_0x2b95410/d;
+L_0x2b95500/d .functor OR 1, L_0x2b952a0, L_0x2b95410, C4<0>, C4<0>;
+L_0x2b95500 .delay (20000,20000,20000) L_0x2b95500/d;
+v0x25d3580_0 .net "A", 0 0, L_0x2b94200; 1 drivers
+v0x25d2570_0 .net "AandB", 0 0, L_0x2b952a0; 1 drivers
+v0x25d2610_0 .net "AddSubSLTSum", 0 0, L_0x2b951b0; 1 drivers
+v0x25d22c0_0 .net "AxorB", 0 0, L_0x2b950c0; 1 drivers
+v0x25d2340_0 .net "B", 0 0, L_0x2b942a0; 1 drivers
+v0x25cf9c0_0 .net "BornB", 0 0, L_0x2b94b70; 1 drivers
+v0x25cfa40_0 .net "CINandAxorB", 0 0, L_0x2b95410; 1 drivers
+v0x25d62a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25d6320_0 .net *"_s3", 0 0, L_0x2b94e40; 1 drivers
+v0x25d5ff0_0 .net *"_s5", 0 0, L_0x2b95020; 1 drivers
+v0x25d6070_0 .net "carryin", 0 0, L_0x2b943d0; 1 drivers
+v0x25d95b0_0 .net "carryout", 0 0, L_0x2b95500; 1 drivers
+v0x25d9630_0 .net "nB", 0 0, L_0x2b94760; 1 drivers
+v0x25d9300_0 .net "nCmd2", 0 0, L_0x2b94da0; 1 drivers
+v0x25d8390_0 .net "subtract", 0 0, L_0x2b94ee0; 1 drivers
+L_0x2b94d00 .part v0x2960210_0, 0, 1;
+L_0x2b94e40 .part v0x2960210_0, 2, 1;
+L_0x2b95020 .part v0x2960210_0, 0, 1;
+S_0x25d01d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25d0480;
+ .timescale -9 -12;
+L_0x2b948f0/d .functor NOT 1, L_0x2b94d00, C4<0>, C4<0>, C4<0>;
+L_0x2b948f0 .delay (10000,10000,10000) L_0x2b948f0/d;
+L_0x2b94990/d .functor AND 1, L_0x2b942a0, L_0x2b948f0, C4<1>, C4<1>;
+L_0x2b94990 .delay (20000,20000,20000) L_0x2b94990/d;
+L_0x2b94a80/d .functor AND 1, L_0x2b94760, L_0x2b94d00, C4<1>, C4<1>;
+L_0x2b94a80 .delay (20000,20000,20000) L_0x2b94a80/d;
+L_0x2b94b70/d .functor OR 1, L_0x2b94990, L_0x2b94a80, C4<0>, C4<0>;
+L_0x2b94b70 .delay (20000,20000,20000) L_0x2b94b70/d;
+v0x25d1b50_0 .net "S", 0 0, L_0x2b94d00; 1 drivers
+v0x25cff20_0 .alias "in0", 0 0, v0x25d2340_0;
+v0x25cffc0_0 .alias "in1", 0 0, v0x25d9630_0;
+v0x25cfc70_0 .net "nS", 0 0, L_0x2b948f0; 1 drivers
+v0x25cfcf0_0 .net "out0", 0 0, L_0x2b94990; 1 drivers
+v0x25d3790_0 .net "out1", 0 0, L_0x2b94a80; 1 drivers
+v0x25d34e0_0 .alias "outfinal", 0 0, v0x25cf9c0_0;
+S_0x25cc710 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25ca620;
+ .timescale -9 -12;
+L_0x2b94470/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b94470 .delay (10000,10000,10000) L_0x2b94470/d;
+L_0x2b94510/d .functor AND 1, L_0x2b7e890, L_0x2b94470, C4<1>, C4<1>;
+L_0x2b94510 .delay (20000,20000,20000) L_0x2b94510/d;
+L_0x2b94620/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b94620 .delay (20000,20000,20000) L_0x2b94620/d;
+L_0x2b946e0/d .functor OR 1, L_0x2b94510, L_0x2b94620, C4<0>, C4<0>;
+L_0x2b946e0 .delay (20000,20000,20000) L_0x2b946e0/d;
+v0x25cd740_0 .alias "S", 0 0, v0x240f880_0;
+v0x25cc460_0 .net "in0", 0 0, L_0x2b7e890; 1 drivers
+v0x25cc500_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x25c9b60_0 .net "nS", 0 0, L_0x2b94470; 1 drivers
+v0x25c9c00_0 .net "out0", 0 0, L_0x2b94510; 1 drivers
+v0x25d1d60_0 .net "out1", 0 0, L_0x2b94620; 1 drivers
+v0x25d1ab0_0 .net "outfinal", 0 0, L_0x2b946e0; 1 drivers
+S_0x25ca370 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25ca620;
+ .timescale -9 -12;
+L_0x2b95a10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b95a10 .delay (10000,10000,10000) L_0x2b95a10/d;
+L_0x2b95b20/d .functor AND 1, L_0x2b7eab0, L_0x2b95a10, C4<1>, C4<1>;
+L_0x2b95b20 .delay (20000,20000,20000) L_0x2b95b20/d;
+L_0x2b95c30/d .functor AND 1, L_0x2b7eba0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b95c30 .delay (20000,20000,20000) L_0x2b95c30/d;
+L_0x2b95cd0/d .functor OR 1, L_0x2b95b20, L_0x2b95c30, C4<0>, C4<0>;
+L_0x2b95cd0 .delay (20000,20000,20000) L_0x2b95cd0/d;
+v0x25cbcd0_0 .alias "S", 0 0, v0x240f880_0;
+v0x25ca0c0_0 .net "in0", 0 0, L_0x2b7eab0; 1 drivers
+v0x25ca140_0 .net "in1", 0 0, L_0x2b7eba0; 1 drivers
+v0x25c9e10_0 .net "nS", 0 0, L_0x2b95a10; 1 drivers
+v0x25c9e90_0 .net "out0", 0 0, L_0x2b95b20; 1 drivers
+v0x25cd950_0 .net "out1", 0 0, L_0x2b95c30; 1 drivers
+v0x25cd6a0_0 .net "outfinal", 0 0, L_0x2b95cd0; 1 drivers
+S_0x25b88b0 .scope generate, "sltbits[23]" "sltbits[23]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x22a3298 .param/l "i" 3 332, +C4<010111>;
+S_0x25c6350 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25b88b0;
+ .timescale -9 -12;
+L_0x2b95e10/d .functor NOT 1, L_0x2b969c0, C4<0>, C4<0>, C4<0>;
+L_0x2b95e10 .delay (10000,10000,10000) L_0x2b95e10/d;
+L_0x2b97380/d .functor NOT 1, L_0x2b97420, C4<0>, C4<0>, C4<0>;
+L_0x2b97380 .delay (10000,10000,10000) L_0x2b97380/d;
+L_0x2b974c0/d .functor AND 1, L_0x2b97600, L_0x2b97380, C4<1>, C4<1>;
+L_0x2b974c0 .delay (20000,20000,20000) L_0x2b974c0/d;
+L_0x2b976a0/d .functor XOR 1, L_0x2b96920, L_0x2b97150, C4<0>, C4<0>;
+L_0x2b976a0 .delay (40000,40000,40000) L_0x2b976a0/d;
+L_0x2b97790/d .functor XOR 1, L_0x2b976a0, L_0x2b96af0, C4<0>, C4<0>;
+L_0x2b97790 .delay (40000,40000,40000) L_0x2b97790/d;
+L_0x2b97880/d .functor AND 1, L_0x2b96920, L_0x2b97150, C4<1>, C4<1>;
+L_0x2b97880 .delay (20000,20000,20000) L_0x2b97880/d;
+L_0x2b979f0/d .functor AND 1, L_0x2b976a0, L_0x2b96af0, C4<1>, C4<1>;
+L_0x2b979f0 .delay (20000,20000,20000) L_0x2b979f0/d;
+L_0x2b97ae0/d .functor OR 1, L_0x2b97880, L_0x2b979f0, C4<0>, C4<0>;
+L_0x2b97ae0 .delay (20000,20000,20000) L_0x2b97ae0/d;
+v0x25c4260_0 .net "A", 0 0, L_0x2b96920; 1 drivers
+v0x25c3fb0_0 .net "AandB", 0 0, L_0x2b97880; 1 drivers
+v0x25c4050_0 .net "AddSubSLTSum", 0 0, L_0x2b97790; 1 drivers
+v0x25c7af0_0 .net "AxorB", 0 0, L_0x2b976a0; 1 drivers
+v0x25c7b70_0 .net "B", 0 0, L_0x2b969c0; 1 drivers
+v0x25c7840_0 .net "BornB", 0 0, L_0x2b97150; 1 drivers
+v0x25c68b0_0 .net "CINandAxorB", 0 0, L_0x2b979f0; 1 drivers
+v0x25c6930_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25c6600_0 .net *"_s3", 0 0, L_0x2b97420; 1 drivers
+v0x25c6680_0 .net *"_s5", 0 0, L_0x2b97600; 1 drivers
+v0x25c3d00_0 .net "carryin", 0 0, L_0x2b96af0; 1 drivers
+v0x25c3d80_0 .net "carryout", 0 0, L_0x2b97ae0; 1 drivers
+v0x25cc1b0_0 .net "nB", 0 0, L_0x2b95e10; 1 drivers
+v0x25cbf00_0 .net "nCmd2", 0 0, L_0x2b97380; 1 drivers
+v0x25cbc50_0 .net "subtract", 0 0, L_0x2b974c0; 1 drivers
+L_0x2b972e0 .part v0x2960210_0, 0, 1;
+L_0x2b97420 .part v0x2960210_0, 2, 1;
+L_0x2b97600 .part v0x2960210_0, 0, 1;
+S_0x25c60a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25c6350;
+ .timescale -9 -12;
+L_0x2b91750/d .functor NOT 1, L_0x2b972e0, C4<0>, C4<0>, C4<0>;
+L_0x2b91750 .delay (10000,10000,10000) L_0x2b91750/d;
+L_0x2b91830/d .functor AND 1, L_0x2b969c0, L_0x2b91750, C4<1>, C4<1>;
+L_0x2b91830 .delay (20000,20000,20000) L_0x2b91830/d;
+L_0x2b97060/d .functor AND 1, L_0x2b95e10, L_0x2b972e0, C4<1>, C4<1>;
+L_0x2b97060 .delay (20000,20000,20000) L_0x2b97060/d;
+L_0x2b97150/d .functor OR 1, L_0x2b91830, L_0x2b97060, C4<0>, C4<0>;
+L_0x2b97150 .delay (20000,20000,20000) L_0x2b97150/d;
+v0x25c0860_0 .net "S", 0 0, L_0x2b972e0; 1 drivers
+v0x25c5df0_0 .alias "in0", 0 0, v0x25c7b70_0;
+v0x25c5e90_0 .alias "in1", 0 0, v0x25cc1b0_0;
+v0x25c47c0_0 .net "nS", 0 0, L_0x2b91750; 1 drivers
+v0x25c4860_0 .net "out0", 0 0, L_0x2b91830; 1 drivers
+v0x25c4510_0 .net "out1", 0 0, L_0x2b97060; 1 drivers
+v0x25c45b0_0 .alias "outfinal", 0 0, v0x25c7840_0;
+S_0x25be6d0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25b88b0;
+ .timescale -9 -12;
+L_0x2b96b90/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b96b90 .delay (10000,10000,10000) L_0x2b96b90/d;
+L_0x2b96c30/d .functor AND 1, L_0x2b985d0, L_0x2b96b90, C4<1>, C4<1>;
+L_0x2b96c30 .delay (20000,20000,20000) L_0x2b96c30/d;
+L_0x2b96d40/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b96d40 .delay (20000,20000,20000) L_0x2b96d40/d;
+L_0x2b96de0/d .functor OR 1, L_0x2b96c30, L_0x2b96d40, C4<0>, C4<0>;
+L_0x2b96de0 .delay (20000,20000,20000) L_0x2b96de0/d;
+v0x25bea00_0 .alias "S", 0 0, v0x240f880_0;
+v0x25c1c90_0 .net "in0", 0 0, L_0x2b985d0; 1 drivers
+v0x25c1d10_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x25c19e0_0 .net "nS", 0 0, L_0x2b96b90; 1 drivers
+v0x25c1a60_0 .net "out0", 0 0, L_0x2b96c30; 1 drivers
+v0x25c0a70_0 .net "out1", 0 0, L_0x2b96d40; 1 drivers
+v0x25c07c0_0 .net "outfinal", 0 0, L_0x2b96de0; 1 drivers
+S_0x25bbe70 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25b88b0;
+ .timescale -9 -12;
+L_0x2b97e90/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b97e90 .delay (10000,10000,10000) L_0x2b97e90/d;
+L_0x2b97fa0/d .functor AND 1, L_0x2b98330, L_0x2b97e90, C4<1>, C4<1>;
+L_0x2b97fa0 .delay (20000,20000,20000) L_0x2b97fa0/d;
+L_0x2b980b0/d .functor AND 1, L_0x2b98420, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b980b0 .delay (20000,20000,20000) L_0x2b980b0/d;
+L_0x2b98150/d .functor OR 1, L_0x2b97fa0, L_0x2b980b0, C4<0>, C4<0>;
+L_0x2b98150 .delay (20000,20000,20000) L_0x2b98150/d;
+v0x25bbbc0_0 .alias "S", 0 0, v0x240f880_0;
+v0x25bbc40_0 .net "in0", 0 0, L_0x2b98330; 1 drivers
+v0x25bac50_0 .net "in1", 0 0, L_0x2b98420; 1 drivers
+v0x25bacd0_0 .net "nS", 0 0, L_0x2b97e90; 1 drivers
+v0x25ba9a0_0 .net "out0", 0 0, L_0x2b97fa0; 1 drivers
+v0x25baa20_0 .net "out1", 0 0, L_0x2b980b0; 1 drivers
+v0x25be980_0 .net "outfinal", 0 0, L_0x2b98150; 1 drivers
+S_0x25a6870 .scope generate, "sltbits[24]" "sltbits[24]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2244a28 .param/l "i" 3 332, +C4<011000>;
+S_0x25ac980 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25a6870;
+ .timescale -9 -12;
+L_0x2b98510/d .functor NOT 1, L_0x2b98940, C4<0>, C4<0>, C4<0>;
+L_0x2b98510 .delay (10000,10000,10000) L_0x2b98510/d;
+L_0x2b99440/d .functor NOT 1, L_0x2b994e0, C4<0>, C4<0>, C4<0>;
+L_0x2b99440 .delay (10000,10000,10000) L_0x2b99440/d;
+L_0x2b99580/d .functor AND 1, L_0x2b996c0, L_0x2b99440, C4<1>, C4<1>;
+L_0x2b99580 .delay (20000,20000,20000) L_0x2b99580/d;
+L_0x2b99760/d .functor XOR 1, L_0x2b988a0, L_0x2b99210, C4<0>, C4<0>;
+L_0x2b99760 .delay (40000,40000,40000) L_0x2b99760/d;
+L_0x2b99850/d .functor XOR 1, L_0x2b99760, L_0x2b98a70, C4<0>, C4<0>;
+L_0x2b99850 .delay (40000,40000,40000) L_0x2b99850/d;
+L_0x2b99940/d .functor AND 1, L_0x2b988a0, L_0x2b99210, C4<1>, C4<1>;
+L_0x2b99940 .delay (20000,20000,20000) L_0x2b99940/d;
+L_0x2b99ab0/d .functor AND 1, L_0x2b99760, L_0x2b98a70, C4<1>, C4<1>;
+L_0x2b99ab0 .delay (20000,20000,20000) L_0x2b99ab0/d;
+L_0x2b99ba0/d .functor OR 1, L_0x2b99940, L_0x2b99ab0, C4<0>, C4<0>;
+L_0x2b99ba0 .delay (20000,20000,20000) L_0x2b99ba0/d;
+v0x25aedc0_0 .net "A", 0 0, L_0x2b988a0; 1 drivers
+v0x25ac420_0 .net "AandB", 0 0, L_0x2b99940; 1 drivers
+v0x25ac4a0_0 .net "AddSubSLTSum", 0 0, L_0x2b99850; 1 drivers
+v0x25b2d40_0 .net "AxorB", 0 0, L_0x2b99760; 1 drivers
+v0x25b2dc0_0 .net "B", 0 0, L_0x2b98940; 1 drivers
+v0x25b2a90_0 .net "BornB", 0 0, L_0x2b99210; 1 drivers
+v0x25b6050_0 .net "CINandAxorB", 0 0, L_0x2b99ab0; 1 drivers
+v0x25b60d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25b5da0_0 .net *"_s3", 0 0, L_0x2b994e0; 1 drivers
+v0x25b5e20_0 .net *"_s5", 0 0, L_0x2b996c0; 1 drivers
+v0x25b4e30_0 .net "carryin", 0 0, L_0x2b98a70; 1 drivers
+v0x25b4eb0_0 .net "carryout", 0 0, L_0x2b99ba0; 1 drivers
+v0x25b4b80_0 .net "nB", 0 0, L_0x2b98510; 1 drivers
+v0x25b4c00_0 .net "nCmd2", 0 0, L_0x2b99440; 1 drivers
+v0x25b8be0_0 .net "subtract", 0 0, L_0x2b99580; 1 drivers
+L_0x2b993a0 .part v0x2960210_0, 0, 1;
+L_0x2b994e0 .part v0x2960210_0, 2, 1;
+L_0x2b996c0 .part v0x2960210_0, 0, 1;
+S_0x25ac6d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25ac980;
+ .timescale -9 -12;
+L_0x2b98f90/d .functor NOT 1, L_0x2b993a0, C4<0>, C4<0>, C4<0>;
+L_0x2b98f90 .delay (10000,10000,10000) L_0x2b98f90/d;
+L_0x2b99030/d .functor AND 1, L_0x2b98940, L_0x2b98f90, C4<1>, C4<1>;
+L_0x2b99030 .delay (20000,20000,20000) L_0x2b99030/d;
+L_0x2b99120/d .functor AND 1, L_0x2b98510, L_0x2b993a0, C4<1>, C4<1>;
+L_0x2b99120 .delay (20000,20000,20000) L_0x2b99120/d;
+L_0x2b99210/d .functor OR 1, L_0x2b99030, L_0x2b99120, C4<0>, C4<0>;
+L_0x2b99210 .delay (20000,20000,20000) L_0x2b99210/d;
+v0x25accd0_0 .net "S", 0 0, L_0x2b993a0; 1 drivers
+v0x25b0210_0 .alias "in0", 0 0, v0x25b2dc0_0;
+v0x25b02b0_0 .alias "in1", 0 0, v0x25b4b80_0;
+v0x25aff60_0 .net "nS", 0 0, L_0x2b98f90; 1 drivers
+v0x25b0000_0 .net "out0", 0 0, L_0x2b99030; 1 drivers
+v0x25aefd0_0 .net "out1", 0 0, L_0x2b99120; 1 drivers
+v0x25aed20_0 .alias "outfinal", 0 0, v0x25b2a90_0;
+S_0x25aea70 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25a6870;
+ .timescale -9 -12;
+L_0x2b98b10/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b98b10 .delay (10000,10000,10000) L_0x2b98b10/d;
+L_0x2b98bb0/d .functor AND 1, L_0x2b99dd0, L_0x2b98b10, C4<1>, C4<1>;
+L_0x2b98bb0 .delay (20000,20000,20000) L_0x2b98bb0/d;
+L_0x2b98cc0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b98cc0 .delay (20000,20000,20000) L_0x2b98cc0/d;
+L_0x2b98d60/d .functor OR 1, L_0x2b98bb0, L_0x2b98cc0, C4<0>, C4<0>;
+L_0x2b98d60 .delay (20000,20000,20000) L_0x2b98d60/d;
+v0x25a6660_0 .alias "S", 0 0, v0x240f880_0;
+v0x25ae7c0_0 .net "in0", 0 0, L_0x2b99dd0; 1 drivers
+v0x25ae860_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x25ae510_0 .net "nS", 0 0, L_0x2b98b10; 1 drivers
+v0x25ae5b0_0 .net "out0", 0 0, L_0x2b98bb0; 1 drivers
+v0x25acee0_0 .net "out1", 0 0, L_0x2b98cc0; 1 drivers
+v0x25acc30_0 .net "outfinal", 0 0, L_0x2b98d60; 1 drivers
+S_0x25aa3b0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25a6870;
+ .timescale -9 -12;
+L_0x2b9a200/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9a200 .delay (10000,10000,10000) L_0x2b9a200/d;
+L_0x2b9a310/d .functor AND 1, L_0x2b95820, L_0x2b9a200, C4<1>, C4<1>;
+L_0x2b9a310 .delay (20000,20000,20000) L_0x2b9a310/d;
+L_0x2b9a420/d .functor AND 1, L_0x2b95910, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9a420 .delay (20000,20000,20000) L_0x2b9a420/d;
+L_0x2b9a4c0/d .functor OR 1, L_0x2b9a310, L_0x2b9a420, C4<0>, C4<0>;
+L_0x2b9a4c0 .delay (20000,20000,20000) L_0x2b9a4c0/d;
+v0x25a6ba0_0 .alias "S", 0 0, v0x240f880_0;
+v0x25aa100_0 .net "in0", 0 0, L_0x2b95820; 1 drivers
+v0x25aa180_0 .net "in1", 0 0, L_0x2b95910; 1 drivers
+v0x25a9170_0 .net "nS", 0 0, L_0x2b9a200; 1 drivers
+v0x25a91f0_0 .net "out0", 0 0, L_0x2b9a310; 1 drivers
+v0x25a8ec0_0 .net "out1", 0 0, L_0x2b9a420; 1 drivers
+v0x25a65c0_0 .net "outfinal", 0 0, L_0x2b9a4c0; 1 drivers
+S_0x25988f0 .scope generate, "sltbits[25]" "sltbits[25]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x226fd48 .param/l "i" 3 332, +C4<011001>;
+S_0x25a2db0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x25988f0;
+ .timescale -9 -12;
+L_0x2b9af30/d .functor NOT 1, L_0x2b9a870, C4<0>, C4<0>, C4<0>;
+L_0x2b9af30 .delay (10000,10000,10000) L_0x2b9af30/d;
+L_0x2b9b530/d .functor NOT 1, L_0x2b9b5d0, C4<0>, C4<0>, C4<0>;
+L_0x2b9b530 .delay (10000,10000,10000) L_0x2b9b530/d;
+L_0x2b9b670/d .functor AND 1, L_0x2b9b7b0, L_0x2b9b530, C4<1>, C4<1>;
+L_0x2b9b670 .delay (20000,20000,20000) L_0x2b9b670/d;
+L_0x2b9b850/d .functor XOR 1, L_0x2b9a7d0, L_0x2b9b300, C4<0>, C4<0>;
+L_0x2b9b850 .delay (40000,40000,40000) L_0x2b9b850/d;
+L_0x2b9b940/d .functor XOR 1, L_0x2b9b850, L_0x2b9a9a0, C4<0>, C4<0>;
+L_0x2b9b940 .delay (40000,40000,40000) L_0x2b9b940/d;
+L_0x2b9ba30/d .functor AND 1, L_0x2b9a7d0, L_0x2b9b300, C4<1>, C4<1>;
+L_0x2b9ba30 .delay (20000,20000,20000) L_0x2b9ba30/d;
+L_0x2b9bba0/d .functor AND 1, L_0x2b9b850, L_0x2b9a9a0, C4<1>, C4<1>;
+L_0x2b9bba0 .delay (20000,20000,20000) L_0x2b9bba0/d;
+L_0x2b9bc90/d .functor OR 1, L_0x2b9ba30, L_0x2b9bba0, C4<0>, C4<0>;
+L_0x2b9bc90 .delay (20000,20000,20000) L_0x2b9bc90/d;
+v0x25a42a0_0 .net "A", 0 0, L_0x2b9a7d0; 1 drivers
+v0x25a3310_0 .net "AandB", 0 0, L_0x2b9ba30; 1 drivers
+v0x25a33b0_0 .net "AddSubSLTSum", 0 0, L_0x2b9b940; 1 drivers
+v0x25a3060_0 .net "AxorB", 0 0, L_0x2b9b850; 1 drivers
+v0x25a30e0_0 .net "B", 0 0, L_0x2b9a870; 1 drivers
+v0x25a8c10_0 .net "BornB", 0 0, L_0x2b9b300; 1 drivers
+v0x25a8c90_0 .net "CINandAxorB", 0 0, L_0x2b9bba0; 1 drivers
+v0x25a8960_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25a89e0_0 .net *"_s3", 0 0, L_0x2b9b5d0; 1 drivers
+v0x25a86b0_0 .net *"_s5", 0 0, L_0x2b9b7b0; 1 drivers
+v0x25a8730_0 .net "carryin", 0 0, L_0x2b9a9a0; 1 drivers
+v0x25a7080_0 .net "carryout", 0 0, L_0x2b9bc90; 1 drivers
+v0x25a7100_0 .net "nB", 0 0, L_0x2b9af30; 1 drivers
+v0x25a6dd0_0 .net "nCmd2", 0 0, L_0x2b9b530; 1 drivers
+v0x25a6b20_0 .net "subtract", 0 0, L_0x2b9b670; 1 drivers
+L_0x2b9b490 .part v0x2960210_0, 0, 1;
+L_0x2b9b5d0 .part v0x2960210_0, 2, 1;
+L_0x2b9b7b0 .part v0x2960210_0, 0, 1;
+S_0x25a2b00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25a2db0;
+ .timescale -9 -12;
+L_0x2b9b080/d .functor NOT 1, L_0x2b9b490, C4<0>, C4<0>, C4<0>;
+L_0x2b9b080 .delay (10000,10000,10000) L_0x2b9b080/d;
+L_0x2b9b120/d .functor AND 1, L_0x2b9a870, L_0x2b9b080, C4<1>, C4<1>;
+L_0x2b9b120 .delay (20000,20000,20000) L_0x2b9b120/d;
+L_0x2b9b210/d .functor AND 1, L_0x2b9af30, L_0x2b9b490, C4<1>, C4<1>;
+L_0x2b9b210 .delay (20000,20000,20000) L_0x2b9b210/d;
+L_0x2b9b300/d .functor OR 1, L_0x2b9b120, L_0x2b9b210, C4<0>, C4<0>;
+L_0x2b9b300 .delay (20000,20000,20000) L_0x2b9b300/d;
+v0x25a2850_0 .net "S", 0 0, L_0x2b9b490; 1 drivers
+v0x25a1220_0 .alias "in0", 0 0, v0x25a30e0_0;
+v0x25a12c0_0 .alias "in1", 0 0, v0x25a7100_0;
+v0x25a0f70_0 .net "nS", 0 0, L_0x2b9b080; 1 drivers
+v0x25a0ff0_0 .net "out0", 0 0, L_0x2b9b120; 1 drivers
+v0x25a4550_0 .net "out1", 0 0, L_0x2b9b210; 1 drivers
+v0x25a45f0_0 .alias "outfinal", 0 0, v0x25a8c10_0;
+S_0x259e710 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x25988f0;
+ .timescale -9 -12;
+L_0x2b9aa40/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9aa40 .delay (10000,10000,10000) L_0x2b9aa40/d;
+L_0x2b9aae0/d .functor AND 1, L_0x2b9ae90, L_0x2b9aa40, C4<1>, C4<1>;
+L_0x2b9aae0 .delay (20000,20000,20000) L_0x2b9aae0/d;
+L_0x2b9abf0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9abf0 .delay (20000,20000,20000) L_0x2b9abf0/d;
+L_0x2b9ac90/d .functor OR 1, L_0x2b9aae0, L_0x2b9abf0, C4<0>, C4<0>;
+L_0x2b9ac90 .delay (20000,20000,20000) L_0x2b9ac90/d;
+v0x259b1f0_0 .alias "S", 0 0, v0x240f880_0;
+v0x259e460_0 .net "in0", 0 0, L_0x2b9ae90; 1 drivers
+v0x259e500_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x259d4f0_0 .net "nS", 0 0, L_0x2b9aa40; 1 drivers
+v0x259d590_0 .net "out0", 0 0, L_0x2b9aae0; 1 drivers
+v0x259d240_0 .net "out1", 0 0, L_0x2b9abf0; 1 drivers
+v0x259d2e0_0 .net "outfinal", 0 0, L_0x2b9ac90; 1 drivers
+S_0x2598640 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x25988f0;
+ .timescale -9 -12;
+L_0x2b9c040/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9c040 .delay (10000,10000,10000) L_0x2b9c040/d;
+L_0x2b9c150/d .functor AND 1, L_0x2b9c4e0, L_0x2b9c040, C4<1>, C4<1>;
+L_0x2b9c150 .delay (20000,20000,20000) L_0x2b9c150/d;
+L_0x2b9c260/d .functor AND 1, L_0x2b9c5d0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9c260 .delay (20000,20000,20000) L_0x2b9c260/d;
+L_0x2b9c300/d .functor OR 1, L_0x2b9c150, L_0x2b9c260, C4<0>, C4<0>;
+L_0x2b9c300 .delay (20000,20000,20000) L_0x2b9c300/d;
+v0x25953b0_0 .alias "S", 0 0, v0x240f880_0;
+v0x25976d0_0 .net "in0", 0 0, L_0x2b9c4e0; 1 drivers
+v0x2597750_0 .net "in1", 0 0, L_0x2b9c5d0; 1 drivers
+v0x2597420_0 .net "nS", 0 0, L_0x2b9c040; 1 drivers
+v0x25974a0_0 .net "out0", 0 0, L_0x2b9c150; 1 drivers
+v0x259b400_0 .net "out1", 0 0, L_0x2b9c260; 1 drivers
+v0x259b150_0 .net "outfinal", 0 0, L_0x2b9c300; 1 drivers
+S_0x27a82d0 .scope generate, "sltbits[26]" "sltbits[26]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2275378 .param/l "i" 3 332, +C4<011010>;
+S_0x25912e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x27a82d0;
+ .timescale -9 -12;
+L_0x2b9c6c0/d .functor NOT 1, L_0x2b9cb00, C4<0>, C4<0>, C4<0>;
+L_0x2b9c6c0 .delay (10000,10000,10000) L_0x2b9c6c0/d;
+L_0x2b9d620/d .functor NOT 1, L_0x2b9d6c0, C4<0>, C4<0>, C4<0>;
+L_0x2b9d620 .delay (10000,10000,10000) L_0x2b9d620/d;
+L_0x2b9d760/d .functor AND 1, L_0x2b9d8a0, L_0x2b9d620, C4<1>, C4<1>;
+L_0x2b9d760 .delay (20000,20000,20000) L_0x2b9d760/d;
+L_0x2b9d940/d .functor XOR 1, L_0x2b9ca60, L_0x2b9d3f0, C4<0>, C4<0>;
+L_0x2b9d940 .delay (40000,40000,40000) L_0x2b9d940/d;
+L_0x2b9da30/d .functor XOR 1, L_0x2b9d940, L_0x2b9cc30, C4<0>, C4<0>;
+L_0x2b9da30 .delay (40000,40000,40000) L_0x2b9da30/d;
+L_0x2b9db20/d .functor AND 1, L_0x2b9ca60, L_0x2b9d3f0, C4<1>, C4<1>;
+L_0x2b9db20 .delay (20000,20000,20000) L_0x2b9db20/d;
+L_0x2b9dc90/d .functor AND 1, L_0x2b9d940, L_0x2b9cc30, C4<1>, C4<1>;
+L_0x2b9dc90 .delay (20000,20000,20000) L_0x2b9dc90/d;
+L_0x2b9dd80/d .functor OR 1, L_0x2b9db20, L_0x2b9dc90, C4<0>, C4<0>;
+L_0x2b9dd80 .delay (20000,20000,20000) L_0x2b9dd80/d;
+v0x258f1c0_0 .net "A", 0 0, L_0x2b9ca60; 1 drivers
+v0x258ee40_0 .net "AandB", 0 0, L_0x2b9db20; 1 drivers
+v0x258eee0_0 .net "AddSubSLTSum", 0 0, L_0x2b9da30; 1 drivers
+v0x2592aa0_0 .net "AxorB", 0 0, L_0x2b9d940; 1 drivers
+v0x2592b20_0 .net "B", 0 0, L_0x2b9cb00; 1 drivers
+v0x25927f0_0 .net "BornB", 0 0, L_0x2b9d3f0; 1 drivers
+v0x2592870_0 .net "CINandAxorB", 0 0, L_0x2b9dc90; 1 drivers
+v0x2591840_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25918c0_0 .net *"_s3", 0 0, L_0x2b9d6c0; 1 drivers
+v0x2591590_0 .net *"_s5", 0 0, L_0x2b9d8a0; 1 drivers
+v0x2591610_0 .net "carryin", 0 0, L_0x2b9cc30; 1 drivers
+v0x258eb90_0 .net "carryout", 0 0, L_0x2b9dd80; 1 drivers
+v0x258ec10_0 .net "nB", 0 0, L_0x2b9c6c0; 1 drivers
+v0x25955e0_0 .net "nCmd2", 0 0, L_0x2b9d620; 1 drivers
+v0x2595330_0 .net "subtract", 0 0, L_0x2b9d760; 1 drivers
+L_0x2b9d580 .part v0x2960210_0, 0, 1;
+L_0x2b9d6c0 .part v0x2960210_0, 2, 1;
+L_0x2b9d8a0 .part v0x2960210_0, 0, 1;
+S_0x2591000 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x25912e0;
+ .timescale -9 -12;
+L_0x2b9d170/d .functor NOT 1, L_0x2b9d580, C4<0>, C4<0>, C4<0>;
+L_0x2b9d170 .delay (10000,10000,10000) L_0x2b9d170/d;
+L_0x2b9d210/d .functor AND 1, L_0x2b9cb00, L_0x2b9d170, C4<1>, C4<1>;
+L_0x2b9d210 .delay (20000,20000,20000) L_0x2b9d210/d;
+L_0x2b9d300/d .functor AND 1, L_0x2b9c6c0, L_0x2b9d580, C4<1>, C4<1>;
+L_0x2b9d300 .delay (20000,20000,20000) L_0x2b9d300/d;
+L_0x2b9d3f0/d .functor OR 1, L_0x2b9d210, L_0x2b9d300, C4<0>, C4<0>;
+L_0x2b9d3f0 .delay (20000,20000,20000) L_0x2b9d3f0/d;
+v0x27ae3a0_0 .net "S", 0 0, L_0x2b9d580; 1 drivers
+v0x2590d50_0 .alias "in0", 0 0, v0x2592b20_0;
+v0x2590df0_0 .alias "in1", 0 0, v0x258ec10_0;
+v0x258f6b0_0 .net "nS", 0 0, L_0x2b9d170; 1 drivers
+v0x258f730_0 .net "out0", 0 0, L_0x2b9d210; 1 drivers
+v0x258f3d0_0 .net "out1", 0 0, L_0x2b9d300; 1 drivers
+v0x258f120_0 .alias "outfinal", 0 0, v0x25927f0_0;
+S_0x27accd0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x27a82d0;
+ .timescale -9 -12;
+L_0x2b9ccd0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9ccd0 .delay (10000,10000,10000) L_0x2b9ccd0/d;
+L_0x2b9cd70/d .functor AND 1, L_0x2b9dfb0, L_0x2b9ccd0, C4<1>, C4<1>;
+L_0x2b9cd70 .delay (20000,20000,20000) L_0x2b9cd70/d;
+L_0x2b9ce80/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9ce80 .delay (20000,20000,20000) L_0x2b9ce80/d;
+L_0x2b9cf40/d .functor OR 1, L_0x2b9cd70, L_0x2b9ce80, C4<0>, C4<0>;
+L_0x2b9cf40 .delay (20000,20000,20000) L_0x2b9cf40/d;
+v0x27acff0_0 .alias "S", 0 0, v0x240f880_0;
+v0x27abe00_0 .net "in0", 0 0, L_0x2b9dfb0; 1 drivers
+v0x27abea0_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x27af450_0 .net "nS", 0 0, L_0x2b9ccd0; 1 drivers
+v0x27af4f0_0 .net "out0", 0 0, L_0x2b9cd70; 1 drivers
+v0x27af1d0_0 .net "out1", 0 0, L_0x2b9ce80; 1 drivers
+v0x27ae300_0 .net "outfinal", 0 0, L_0x2b9cf40; 1 drivers
+S_0x27a7400 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x27a82d0;
+ .timescale -9 -12;
+L_0x2b9e430/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9e430 .delay (10000,10000,10000) L_0x2b9e430/d;
+L_0x2b9e540/d .functor AND 1, L_0x2b99fb0, L_0x2b9e430, C4<1>, C4<1>;
+L_0x2b9e540 .delay (20000,20000,20000) L_0x2b9e540/d;
+L_0x2b9e650/d .functor AND 1, L_0x2b9a050, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9e650 .delay (20000,20000,20000) L_0x2b9e650/d;
+L_0x2b9e6f0/d .functor OR 1, L_0x2b9e540, L_0x2b9e650, C4<0>, C4<0>;
+L_0x2b9e6f0 .delay (20000,20000,20000) L_0x2b9e6f0/d;
+v0x27a85d0_0 .alias "S", 0 0, v0x240f880_0;
+v0x27aaa50_0 .net "in0", 0 0, L_0x2b99fb0; 1 drivers
+v0x27aaad0_0 .net "in1", 0 0, L_0x2b9a050; 1 drivers
+v0x27aa7d0_0 .net "nS", 0 0, L_0x2b9e430; 1 drivers
+v0x27aa850_0 .net "out0", 0 0, L_0x2b9e540; 1 drivers
+v0x27a9900_0 .net "out1", 0 0, L_0x2b9e650; 1 drivers
+v0x27acf50_0 .net "outfinal", 0 0, L_0x2b9e6f0; 1 drivers
+S_0x2792690 .scope generate, "sltbits[27]" "sltbits[27]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x230e458 .param/l "i" 3 332, +C4<011011>;
+S_0x279ba90 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2792690;
+ .timescale -9 -12;
+L_0x2b9a140/d .functor NOT 1, L_0x2b9eab0, C4<0>, C4<0>, C4<0>;
+L_0x2b9a140 .delay (10000,10000,10000) L_0x2b9a140/d;
+L_0x2b9f760/d .functor NOT 1, L_0x2b9f800, C4<0>, C4<0>, C4<0>;
+L_0x2b9f760 .delay (10000,10000,10000) L_0x2b9f760/d;
+L_0x2b9f8a0/d .functor AND 1, L_0x2b9f9e0, L_0x2b9f760, C4<1>, C4<1>;
+L_0x2b9f8a0 .delay (20000,20000,20000) L_0x2b9f8a0/d;
+L_0x2b9fa80/d .functor XOR 1, L_0x2b9ea10, L_0x2b9f530, C4<0>, C4<0>;
+L_0x2b9fa80 .delay (40000,40000,40000) L_0x2b9fa80/d;
+L_0x2b9fb70/d .functor XOR 1, L_0x2b9fa80, L_0x2b9ebe0, C4<0>, C4<0>;
+L_0x2b9fb70 .delay (40000,40000,40000) L_0x2b9fb70/d;
+L_0x2b9fc60/d .functor AND 1, L_0x2b9ea10, L_0x2b9f530, C4<1>, C4<1>;
+L_0x2b9fc60 .delay (20000,20000,20000) L_0x2b9fc60/d;
+L_0x2b9fdd0/d .functor AND 1, L_0x2b9fa80, L_0x2b9ebe0, C4<1>, C4<1>;
+L_0x2b9fdd0 .delay (20000,20000,20000) L_0x2b9fdd0/d;
+L_0x2b9fec0/d .functor OR 1, L_0x2b9fc60, L_0x2b9fdd0, C4<0>, C4<0>;
+L_0x2b9fec0 .delay (20000,20000,20000) L_0x2b9fec0/d;
+v0x27a1440_0 .net "A", 0 0, L_0x2b9ea10; 1 drivers
+v0x27a04b0_0 .net "AandB", 0 0, L_0x2b9fc60; 1 drivers
+v0x27a0550_0 .net "AddSubSLTSum", 0 0, L_0x2b9fb70; 1 drivers
+v0x27a3b30_0 .net "AxorB", 0 0, L_0x2b9fa80; 1 drivers
+v0x27a3bb0_0 .net "B", 0 0, L_0x2b9eab0; 1 drivers
+v0x27a38b0_0 .net "BornB", 0 0, L_0x2b9f530; 1 drivers
+v0x27a3930_0 .net "CINandAxorB", 0 0, L_0x2b9fdd0; 1 drivers
+v0x27a29c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x27a2a40_0 .net *"_s3", 0 0, L_0x2b9f800; 1 drivers
+v0x27a6050_0 .net *"_s5", 0 0, L_0x2b9f9e0; 1 drivers
+v0x27a60d0_0 .net "carryin", 0 0, L_0x2b9ebe0; 1 drivers
+v0x27a5dd0_0 .net "carryout", 0 0, L_0x2b9fec0; 1 drivers
+v0x27a5e50_0 .net "nB", 0 0, L_0x2b9a140; 1 drivers
+v0x27a4ed0_0 .net "nCmd2", 0 0, L_0x2b9f760; 1 drivers
+v0x27a8550_0 .net "subtract", 0 0, L_0x2b9f8a0; 1 drivers
+L_0x2b9f6c0 .part v0x2960210_0, 0, 1;
+L_0x2b9f800 .part v0x2960210_0, 2, 1;
+L_0x2b9f9e0 .part v0x2960210_0, 0, 1;
+S_0x279f110 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x279ba90;
+ .timescale -9 -12;
+L_0x2b9f2b0/d .functor NOT 1, L_0x2b9f6c0, C4<0>, C4<0>, C4<0>;
+L_0x2b9f2b0 .delay (10000,10000,10000) L_0x2b9f2b0/d;
+L_0x2b9f350/d .functor AND 1, L_0x2b9eab0, L_0x2b9f2b0, C4<1>, C4<1>;
+L_0x2b9f350 .delay (20000,20000,20000) L_0x2b9f350/d;
+L_0x2b9f440/d .functor AND 1, L_0x2b9a140, L_0x2b9f6c0, C4<1>, C4<1>;
+L_0x2b9f440 .delay (20000,20000,20000) L_0x2b9f440/d;
+L_0x2b9f530/d .functor OR 1, L_0x2b9f350, L_0x2b9f440, C4<0>, C4<0>;
+L_0x2b9f530 .delay (20000,20000,20000) L_0x2b9f530/d;
+v0x279ca20_0 .net "S", 0 0, L_0x2b9f6c0; 1 drivers
+v0x279ee90_0 .alias "in0", 0 0, v0x27a3bb0_0;
+v0x279ef30_0 .alias "in1", 0 0, v0x27a5e50_0;
+v0x279dfa0_0 .net "nS", 0 0, L_0x2b9f2b0; 1 drivers
+v0x279e020_0 .net "out0", 0 0, L_0x2b9f350; 1 drivers
+v0x27a1620_0 .net "out1", 0 0, L_0x2b9f440; 1 drivers
+v0x27a13a0_0 .alias "outfinal", 0 0, v0x27a38b0_0;
+S_0x279a6f0 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2792690;
+ .timescale -9 -12;
+L_0x2b9ec80/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9ec80 .delay (10000,10000,10000) L_0x2b9ec80/d;
+L_0x2b9ed20/d .functor AND 1, L_0x2b9f0f0, L_0x2b9ec80, C4<1>, C4<1>;
+L_0x2b9ed20 .delay (20000,20000,20000) L_0x2b9ed20/d;
+L_0x2b9ee30/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9ee30 .delay (20000,20000,20000) L_0x2b9ee30/d;
+L_0x2b9eef0/d .functor OR 1, L_0x2b9ed20, L_0x2b9ee30, C4<0>, C4<0>;
+L_0x2b9eef0 .delay (20000,20000,20000) L_0x2b9eef0/d;
+v0x2797110_0 .alias "S", 0 0, v0x240f880_0;
+v0x279a470_0 .net "in0", 0 0, L_0x2b9f0f0; 1 drivers
+v0x279a510_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2799580_0 .net "nS", 0 0, L_0x2b9ec80; 1 drivers
+v0x2799620_0 .net "out0", 0 0, L_0x2b9ed20; 1 drivers
+v0x279cc00_0 .net "out1", 0 0, L_0x2b9ee30; 1 drivers
+v0x279c980_0 .net "outfinal", 0 0, L_0x2b9eef0; 1 drivers
+S_0x2795cd0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2792690;
+ .timescale -9 -12;
+L_0x2ba0b70/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba0b70 .delay (10000,10000,10000) L_0x2ba0b70/d;
+L_0x2ba0c60/d .functor AND 1, L_0x2ba0fd0, L_0x2ba0b70, C4<1>, C4<1>;
+L_0x2ba0c60 .delay (20000,20000,20000) L_0x2ba0c60/d;
+L_0x2ba0d50/d .functor AND 1, L_0x2ba01e0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba0d50 .delay (20000,20000,20000) L_0x2ba0d50/d;
+L_0x2ba0df0/d .functor OR 1, L_0x2ba0c60, L_0x2ba0d50, C4<0>, C4<0>;
+L_0x2ba0df0 .delay (20000,20000,20000) L_0x2ba0df0/d;
+v0x2795a50_0 .alias "S", 0 0, v0x240f880_0;
+v0x276d620_0 .net "in0", 0 0, L_0x2ba0fd0; 1 drivers
+v0x2795ad0_0 .net "in1", 0 0, L_0x2ba01e0; 1 drivers
+v0x27981e0_0 .net "nS", 0 0, L_0x2ba0b70; 1 drivers
+v0x2798260_0 .net "out0", 0 0, L_0x2ba0c60; 1 drivers
+v0x2797f60_0 .net "out1", 0 0, L_0x2ba0d50; 1 drivers
+v0x2797070_0 .net "outfinal", 0 0, L_0x2ba0df0; 1 drivers
+S_0x2780d30 .scope generate, "sltbits[28]" "sltbits[28]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x248f6b8 .param/l "i" 3 332, +C4<011100>;
+S_0x278a3e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2780d30;
+ .timescale -9 -12;
+L_0x2ba02d0/d .functor NOT 1, L_0x2ba1340, C4<0>, C4<0>, C4<0>;
+L_0x2ba02d0 .delay (10000,10000,10000) L_0x2ba02d0/d;
+L_0x2ba0a30/d .functor NOT 1, L_0x2ba1a10, C4<0>, C4<0>, C4<0>;
+L_0x2ba0a30 .delay (10000,10000,10000) L_0x2ba0a30/d;
+L_0x2ba1ab0/d .functor AND 1, L_0x2ba1bf0, L_0x2ba0a30, C4<1>, C4<1>;
+L_0x2ba1ab0 .delay (20000,20000,20000) L_0x2ba1ab0/d;
+L_0x2ba1c90/d .functor XOR 1, L_0x2ba12a0, L_0x2ba07c0, C4<0>, C4<0>;
+L_0x2ba1c90 .delay (40000,40000,40000) L_0x2ba1c90/d;
+L_0x2ba1d80/d .functor XOR 1, L_0x2ba1c90, L_0x2ba1470, C4<0>, C4<0>;
+L_0x2ba1d80 .delay (40000,40000,40000) L_0x2ba1d80/d;
+L_0x2ba1e70/d .functor AND 1, L_0x2ba12a0, L_0x2ba07c0, C4<1>, C4<1>;
+L_0x2ba1e70 .delay (20000,20000,20000) L_0x2ba1e70/d;
+L_0x2ba1fe0/d .functor AND 1, L_0x2ba1c90, L_0x2ba1470, C4<1>, C4<1>;
+L_0x2ba1fe0 .delay (20000,20000,20000) L_0x2ba1fe0/d;
+L_0x2ba20d0/d .functor OR 1, L_0x2ba1e70, L_0x2ba1fe0, C4<0>, C4<0>;
+L_0x2ba20d0 .delay (20000,20000,20000) L_0x2ba20d0/d;
+v0x278b830_0 .net "A", 0 0, L_0x2ba12a0; 1 drivers
+v0x278ede0_0 .net "AandB", 0 0, L_0x2ba1e70; 1 drivers
+v0x278ee60_0 .net "AddSubSLTSum", 0 0, L_0x2ba1d80; 1 drivers
+v0x278eb60_0 .net "AxorB", 0 0, L_0x2ba1c90; 1 drivers
+v0x278ebe0_0 .net "B", 0 0, L_0x2ba1340; 1 drivers
+v0x278dc90_0 .net "BornB", 0 0, L_0x2ba07c0; 1 drivers
+v0x27912e0_0 .net "CINandAxorB", 0 0, L_0x2ba1fe0; 1 drivers
+v0x2791360_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2791060_0 .net *"_s3", 0 0, L_0x2ba1a10; 1 drivers
+v0x27910e0_0 .net *"_s5", 0 0, L_0x2ba1bf0; 1 drivers
+v0x2790190_0 .net "carryin", 0 0, L_0x2ba1470; 1 drivers
+v0x2790210_0 .net "carryout", 0 0, L_0x2ba20d0; 1 drivers
+v0x27937e0_0 .net "nB", 0 0, L_0x2ba02d0; 1 drivers
+v0x2793860_0 .net "nCmd2", 0 0, L_0x2ba0a30; 1 drivers
+v0x27935e0_0 .net "subtract", 0 0, L_0x2ba1ab0; 1 drivers
+L_0x2ba0990 .part v0x2960210_0, 0, 1;
+L_0x2ba1a10 .part v0x2960210_0, 2, 1;
+L_0x2ba1bf0 .part v0x2960210_0, 0, 1;
+S_0x278a160 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x278a3e0;
+ .timescale -9 -12;
+L_0x2ba04c0/d .functor NOT 1, L_0x2ba0990, C4<0>, C4<0>, C4<0>;
+L_0x2ba04c0 .delay (10000,10000,10000) L_0x2ba04c0/d;
+L_0x2ba05a0/d .functor AND 1, L_0x2ba1340, L_0x2ba04c0, C4<1>, C4<1>;
+L_0x2ba05a0 .delay (20000,20000,20000) L_0x2ba05a0/d;
+L_0x2ba06b0/d .functor AND 1, L_0x2ba02d0, L_0x2ba0990, C4<1>, C4<1>;
+L_0x2ba06b0 .delay (20000,20000,20000) L_0x2ba06b0/d;
+L_0x2ba07c0/d .functor OR 1, L_0x2ba05a0, L_0x2ba06b0, C4<0>, C4<0>;
+L_0x2ba07c0 .delay (20000,20000,20000) L_0x2ba07c0/d;
+v0x2786e30_0 .net "S", 0 0, L_0x2ba0990; 1 drivers
+v0x2789290_0 .alias "in0", 0 0, v0x278ebe0_0;
+v0x2789330_0 .alias "in1", 0 0, v0x27937e0_0;
+v0x278c8e0_0 .net "nS", 0 0, L_0x2ba04c0; 1 drivers
+v0x278c980_0 .net "out0", 0 0, L_0x2ba05a0; 1 drivers
+v0x278c660_0 .net "out1", 0 0, L_0x2ba06b0; 1 drivers
+v0x278b790_0 .alias "outfinal", 0 0, v0x278dc90_0;
+S_0x2785760 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2780d30;
+ .timescale -9 -12;
+L_0x2ba1510/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba1510 .delay (10000,10000,10000) L_0x2ba1510/d;
+L_0x2ba15b0/d .functor AND 1, L_0x2ba1960, L_0x2ba1510, C4<1>, C4<1>;
+L_0x2ba15b0 .delay (20000,20000,20000) L_0x2ba15b0/d;
+L_0x2ba16c0/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba16c0 .delay (20000,20000,20000) L_0x2ba16c0/d;
+L_0x2ba1760/d .functor OR 1, L_0x2ba15b0, L_0x2ba16c0, C4<0>, C4<0>;
+L_0x2ba1760 .delay (20000,20000,20000) L_0x2ba1760/d;
+v0x2785a80_0 .alias "S", 0 0, v0x240f880_0;
+v0x2784860_0 .net "in0", 0 0, L_0x2ba1960; 1 drivers
+v0x2784900_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2787ee0_0 .net "nS", 0 0, L_0x2ba1510; 1 drivers
+v0x2787f80_0 .net "out0", 0 0, L_0x2ba15b0; 1 drivers
+v0x2787c60_0 .net "out1", 0 0, L_0x2ba16c0; 1 drivers
+v0x2786d90_0 .net "outfinal", 0 0, L_0x2ba1760; 1 drivers
+S_0x277fe40 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2780d30;
+ .timescale -9 -12;
+L_0x2b9e130/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b9e130 .delay (10000,10000,10000) L_0x2b9e130/d;
+L_0x2b9e240/d .functor AND 1, L_0x2ba2300, L_0x2b9e130, C4<1>, C4<1>;
+L_0x2b9e240 .delay (20000,20000,20000) L_0x2b9e240/d;
+L_0x2b9e350/d .functor AND 1, L_0x2ba23f0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2b9e350 .delay (20000,20000,20000) L_0x2b9e350/d;
+L_0x2ba3080/d .functor OR 1, L_0x2b9e240, L_0x2b9e350, C4<0>, C4<0>;
+L_0x2ba3080 .delay (20000,20000,20000) L_0x2ba3080/d;
+v0x2781030_0 .alias "S", 0 0, v0x240f880_0;
+v0x27834c0_0 .net "in0", 0 0, L_0x2ba2300; 1 drivers
+v0x2783540_0 .net "in1", 0 0, L_0x2ba23f0; 1 drivers
+v0x2783240_0 .net "nS", 0 0, L_0x2b9e130; 1 drivers
+v0x27832c0_0 .net "out0", 0 0, L_0x2b9e240; 1 drivers
+v0x2782350_0 .net "out1", 0 0, L_0x2b9e350; 1 drivers
+v0x27859e0_0 .net "outfinal", 0 0, L_0x2ba3080; 1 drivers
+S_0x276e770 .scope generate, "sltbits[29]" "sltbits[29]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x24d9cf8 .param/l "i" 3 332, +C4<011101>;
+S_0x27753e0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x276e770;
+ .timescale -9 -12;
+L_0x2ba24e0/d .functor NOT 1, L_0x2ba33b0, C4<0>, C4<0>, C4<0>;
+L_0x2ba24e0 .delay (10000,10000,10000) L_0x2ba24e0/d;
+L_0x2ba2c00/d .functor NOT 1, L_0x2ba3c10, C4<0>, C4<0>, C4<0>;
+L_0x2ba2c00 .delay (10000,10000,10000) L_0x2ba2c00/d;
+L_0x2ba3cb0/d .functor AND 1, L_0x2ba3df0, L_0x2ba2c00, C4<1>, C4<1>;
+L_0x2ba3cb0 .delay (20000,20000,20000) L_0x2ba3cb0/d;
+L_0x2ba3e90/d .functor XOR 1, L_0x2ba3310, L_0x2ba2990, C4<0>, C4<0>;
+L_0x2ba3e90 .delay (40000,40000,40000) L_0x2ba3e90/d;
+L_0x2ba3f80/d .functor XOR 1, L_0x2ba3e90, L_0x2ba34e0, C4<0>, C4<0>;
+L_0x2ba3f80 .delay (40000,40000,40000) L_0x2ba3f80/d;
+L_0x2ba4070/d .functor AND 1, L_0x2ba3310, L_0x2ba2990, C4<1>, C4<1>;
+L_0x2ba4070 .delay (20000,20000,20000) L_0x2ba4070/d;
+L_0x2ba41e0/d .functor AND 1, L_0x2ba3e90, L_0x2ba34e0, C4<1>, C4<1>;
+L_0x2ba41e0 .delay (20000,20000,20000) L_0x2ba41e0/d;
+L_0x2ba42d0/d .functor OR 1, L_0x2ba4070, L_0x2ba41e0, C4<0>, C4<0>;
+L_0x2ba42d0 .delay (20000,20000,20000) L_0x2ba42d0/d;
+v0x2779e00_0 .net "A", 0 0, L_0x2ba3310; 1 drivers
+v0x2778f10_0 .net "AandB", 0 0, L_0x2ba4070; 1 drivers
+v0x2778fb0_0 .net "AddSubSLTSum", 0 0, L_0x2ba3f80; 1 drivers
+v0x277c590_0 .net "AxorB", 0 0, L_0x2ba3e90; 1 drivers
+v0x277c610_0 .net "B", 0 0, L_0x2ba33b0; 1 drivers
+v0x277c310_0 .net "BornB", 0 0, L_0x2ba2990; 1 drivers
+v0x277c390_0 .net "CINandAxorB", 0 0, L_0x2ba41e0; 1 drivers
+v0x277b420_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x277b4a0_0 .net *"_s3", 0 0, L_0x2ba3c10; 1 drivers
+v0x277eaa0_0 .net *"_s5", 0 0, L_0x2ba3df0; 1 drivers
+v0x277eb20_0 .net "carryin", 0 0, L_0x2ba34e0; 1 drivers
+v0x277e820_0 .net "carryout", 0 0, L_0x2ba42d0; 1 drivers
+v0x277e8a0_0 .net "nB", 0 0, L_0x2ba24e0; 1 drivers
+v0x277d930_0 .net "nCmd2", 0 0, L_0x2ba2c00; 1 drivers
+v0x2780fb0_0 .net "subtract", 0 0, L_0x2ba3cb0; 1 drivers
+L_0x2ba2b60 .part v0x2960210_0, 0, 1;
+L_0x2ba3c10 .part v0x2960210_0, 2, 1;
+L_0x2ba3df0 .part v0x2960210_0, 0, 1;
+S_0x2774520 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27753e0;
+ .timescale -9 -12;
+L_0x2ba26b0/d .functor NOT 1, L_0x2ba2b60, C4<0>, C4<0>, C4<0>;
+L_0x2ba26b0 .delay (10000,10000,10000) L_0x2ba26b0/d;
+L_0x2ba2770/d .functor AND 1, L_0x2ba33b0, L_0x2ba26b0, C4<1>, C4<1>;
+L_0x2ba2770 .delay (20000,20000,20000) L_0x2ba2770/d;
+L_0x2ba2880/d .functor AND 1, L_0x2ba24e0, L_0x2ba2b60, C4<1>, C4<1>;
+L_0x2ba2880 .delay (20000,20000,20000) L_0x2ba2880/d;
+L_0x2ba2990/d .functor OR 1, L_0x2ba2770, L_0x2ba2880, C4<0>, C4<0>;
+L_0x2ba2990 .delay (20000,20000,20000) L_0x2ba2990/d;
+v0x2777b70_0 .net "S", 0 0, L_0x2ba2b60; 1 drivers
+v0x27778f0_0 .alias "in0", 0 0, v0x277c610_0;
+v0x2777990_0 .alias "in1", 0 0, v0x277e8a0_0;
+v0x2776a00_0 .net "nS", 0 0, L_0x2ba26b0; 1 drivers
+v0x2776a80_0 .net "out0", 0 0, L_0x2ba2770; 1 drivers
+v0x277a080_0 .net "out1", 0 0, L_0x2ba2880; 1 drivers
+v0x277a120_0 .alias "outfinal", 0 0, v0x277c310_0;
+S_0x2773170 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x276e770;
+ .timescale -9 -12;
+L_0x2ba3580/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba3580 .delay (10000,10000,10000) L_0x2ba3580/d;
+L_0x2ba3620/d .functor AND 1, L_0x2ba39d0, L_0x2ba3580, C4<1>, C4<1>;
+L_0x2ba3620 .delay (20000,20000,20000) L_0x2ba3620/d;
+L_0x2ba3730/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba3730 .delay (20000,20000,20000) L_0x2ba3730/d;
+L_0x2ba37d0/d .functor OR 1, L_0x2ba3620, L_0x2ba3730, C4<0>, C4<0>;
+L_0x2ba37d0 .delay (20000,20000,20000) L_0x2ba37d0/d;
+v0x276fbc0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2772ef0_0 .net "in0", 0 0, L_0x2ba39d0; 1 drivers
+v0x2772f90_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2772020_0 .net "nS", 0 0, L_0x2ba3580; 1 drivers
+v0x27720c0_0 .net "out0", 0 0, L_0x2ba3620; 1 drivers
+v0x2775660_0 .net "out1", 0 0, L_0x2ba3730; 1 drivers
+v0x2775700_0 .net "outfinal", 0 0, L_0x2ba37d0; 1 drivers
+S_0x276e4f0 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x276e770;
+ .timescale -9 -12;
+L_0x2ba3b50/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba3b50 .delay (10000,10000,10000) L_0x2ba3b50/d;
+L_0x2ba5070/d .functor AND 1, L_0x2ba53e0, L_0x2ba3b50, C4<1>, C4<1>;
+L_0x2ba5070 .delay (20000,20000,20000) L_0x2ba5070/d;
+L_0x2ba5160/d .functor AND 1, L_0x2ba45f0, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba5160 .delay (20000,20000,20000) L_0x2ba5160/d;
+L_0x2ba5200/d .functor OR 1, L_0x2ba5070, L_0x2ba5160, C4<0>, C4<0>;
+L_0x2ba5200 .delay (20000,20000,20000) L_0x2ba5200/d;
+v0x276b170_0 .alias "S", 0 0, v0x240f880_0;
+v0x276d6b0_0 .net "in0", 0 0, L_0x2ba53e0; 1 drivers
+v0x2770c70_0 .net "in1", 0 0, L_0x2ba45f0; 1 drivers
+v0x2770d10_0 .net "nS", 0 0, L_0x2ba3b50; 1 drivers
+v0x27709f0_0 .net "out0", 0 0, L_0x2ba5070; 1 drivers
+v0x2770a90_0 .net "out1", 0 0, L_0x2ba5160; 1 drivers
+v0x276fb20_0 .net "outfinal", 0 0, L_0x2ba5200; 1 drivers
+S_0x275f600 .scope generate, "sltbits[30]" "sltbits[30]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x251c3a8 .param/l "i" 3 332, +C4<011110>;
+S_0x2762fc0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x275f600;
+ .timescale -9 -12;
+L_0x2ba46e0/d .functor NOT 1, L_0x2b82f70, C4<0>, C4<0>, C4<0>;
+L_0x2ba46e0 .delay (10000,10000,10000) L_0x2ba46e0/d;
+L_0x2ba4e40/d .functor NOT 1, L_0x2ba4f00, C4<0>, C4<0>, C4<0>;
+L_0x2ba4e40 .delay (10000,10000,10000) L_0x2ba4e40/d;
+L_0x2ba5ed0/d .functor AND 1, L_0x2ba5fd0, L_0x2ba4e40, C4<1>, C4<1>;
+L_0x2ba5ed0 .delay (20000,20000,20000) L_0x2ba5ed0/d;
+L_0x2ba6070/d .functor XOR 1, L_0x2b82ed0, L_0x2ba4bd0, C4<0>, C4<0>;
+L_0x2ba6070 .delay (40000,40000,40000) L_0x2ba6070/d;
+L_0x2ba6160/d .functor XOR 1, L_0x2ba6070, L_0x2ba5b00, C4<0>, C4<0>;
+L_0x2ba6160 .delay (40000,40000,40000) L_0x2ba6160/d;
+L_0x2ba6250/d .functor AND 1, L_0x2b82ed0, L_0x2ba4bd0, C4<1>, C4<1>;
+L_0x2ba6250 .delay (20000,20000,20000) L_0x2ba6250/d;
+L_0x2ba63c0/d .functor AND 1, L_0x2ba6070, L_0x2ba5b00, C4<1>, C4<1>;
+L_0x2ba63c0 .delay (20000,20000,20000) L_0x2ba63c0/d;
+L_0x2ba64b0/d .functor OR 1, L_0x2ba6250, L_0x2ba63c0, C4<0>, C4<0>;
+L_0x2ba64b0 .delay (20000,20000,20000) L_0x2ba64b0/d;
+v0x27b1930_0 .net "A", 0 0, L_0x2b82ed0; 1 drivers
+v0x27b16c0_0 .net "AandB", 0 0, L_0x2ba6250; 1 drivers
+v0x27b1760_0 .net "AddSubSLTSum", 0 0, L_0x2ba6160; 1 drivers
+v0x27b0800_0 .net "AxorB", 0 0, L_0x2ba6070; 1 drivers
+v0x27b0880_0 .net "B", 0 0, L_0x2b82f70; 1 drivers
+v0x2769d00_0 .net "BornB", 0 0, L_0x2ba4bd0; 1 drivers
+v0x2769d80_0 .net "CINandAxorB", 0 0, L_0x2ba63c0; 1 drivers
+v0x2769a20_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2769aa0_0 .net *"_s3", 0 0, L_0x2ba4f00; 1 drivers
+v0x2768b70_0 .net *"_s5", 0 0, L_0x2ba5fd0; 1 drivers
+v0x2768bf0_0 .net "carryin", 0 0, L_0x2ba5b00; 1 drivers
+v0x276c270_0 .net "carryout", 0 0, L_0x2ba64b0; 1 drivers
+v0x276c2f0_0 .net "nB", 0 0, L_0x2ba46e0; 1 drivers
+v0x276bff0_0 .net "nCmd2", 0 0, L_0x2ba4e40; 1 drivers
+v0x276b0f0_0 .net "subtract", 0 0, L_0x2ba5ed0; 1 drivers
+L_0x2ba4da0 .part v0x2960210_0, 0, 1;
+L_0x2ba4f00 .part v0x2960210_0, 2, 1;
+L_0x2ba5fd0 .part v0x2960210_0, 0, 1;
+S_0x2764d00 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2762fc0;
+ .timescale -9 -12;
+L_0x2ba48b0/d .functor NOT 1, L_0x2ba4da0, C4<0>, C4<0>, C4<0>;
+L_0x2ba48b0 .delay (10000,10000,10000) L_0x2ba48b0/d;
+L_0x2ba4990/d .functor AND 1, L_0x2b82f70, L_0x2ba48b0, C4<1>, C4<1>;
+L_0x2ba4990 .delay (20000,20000,20000) L_0x2ba4990/d;
+L_0x2ba4ac0/d .functor AND 1, L_0x2ba46e0, L_0x2ba4da0, C4<1>, C4<1>;
+L_0x2ba4ac0 .delay (20000,20000,20000) L_0x2ba4ac0/d;
+L_0x2ba4bd0/d .functor OR 1, L_0x2ba4990, L_0x2ba4ac0, C4<0>, C4<0>;
+L_0x2ba4bd0 .delay (20000,20000,20000) L_0x2ba4bd0/d;
+v0x2763560_0 .net "S", 0 0, L_0x2ba4da0; 1 drivers
+v0x2764a80_0 .alias "in0", 0 0, v0x27b0880_0;
+v0x2764b20_0 .alias "in1", 0 0, v0x276c2f0_0;
+v0x27662c0_0 .net "nS", 0 0, L_0x2ba48b0; 1 drivers
+v0x2766360_0 .net "out0", 0 0, L_0x2ba4990; 1 drivers
+v0x2766020_0 .net "out1", 0 0, L_0x2ba4ac0; 1 drivers
+v0x27660c0_0 .alias "outfinal", 0 0, v0x2769d00_0;
+S_0x2762180 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x275f600;
+ .timescale -9 -12;
+L_0x2ba5ba0/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba5ba0 .delay (10000,10000,10000) L_0x2ba5ba0/d;
+L_0x2ba5c40/d .functor AND 1, L_0x2ba66e0, L_0x2ba5ba0, C4<1>, C4<1>;
+L_0x2ba5c40 .delay (20000,20000,20000) L_0x2ba5c40/d;
+L_0x2ba5d50/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba5d50 .delay (20000,20000,20000) L_0x2ba5d50/d;
+L_0x2ba5df0/d .functor OR 1, L_0x2ba5c40, L_0x2ba5d50, C4<0>, C4<0>;
+L_0x2ba5df0 .delay (20000,20000,20000) L_0x2ba5df0/d;
+v0x27604c0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2761f00_0 .net "in0", 0 0, L_0x2ba66e0; 1 drivers
+v0x2761f80_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2761a00_0 .net "nS", 0 0, L_0x2ba5ba0; 1 drivers
+v0x2761a80_0 .net "out0", 0 0, L_0x2ba5c40; 1 drivers
+v0x2763740_0 .net "out1", 0 0, L_0x2ba5d50; 1 drivers
+v0x27634c0_0 .net "outfinal", 0 0, L_0x2ba5df0; 1 drivers
+S_0x275f380 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x275f600;
+ .timescale -9 -12;
+L_0x2ba6b40/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba6b40 .delay (10000,10000,10000) L_0x2ba6b40/d;
+L_0x2ba6c50/d .functor AND 1, L_0x2ba6fe0, L_0x2ba6b40, C4<1>, C4<1>;
+L_0x2ba6c50 .delay (20000,20000,20000) L_0x2ba6c50/d;
+L_0x2ba6d60/d .functor AND 1, L_0x2ba2d70, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba6d60 .delay (20000,20000,20000) L_0x2ba6d60/d;
+L_0x2ba6e00/d .functor OR 1, L_0x2ba6c50, L_0x2ba6d60, C4<0>, C4<0>;
+L_0x2ba6e00 .delay (20000,20000,20000) L_0x2ba6e00/d;
+v0x275ee80_0 .alias "S", 0 0, v0x240f880_0;
+v0x275ef00_0 .net "in0", 0 0, L_0x2ba6fe0; 1 drivers
+v0x2760bc0_0 .net "in1", 0 0, L_0x2ba2d70; 1 drivers
+v0x2760c40_0 .net "nS", 0 0, L_0x2ba6b40; 1 drivers
+v0x2760940_0 .net "out0", 0 0, L_0x2ba6c50; 1 drivers
+v0x27609c0_0 .net "out1", 0 0, L_0x2ba6d60; 1 drivers
+v0x2760440_0 .net "outfinal", 0 0, L_0x2ba6e00; 1 drivers
+S_0x2752fa0 .scope generate, "sltbits[31]" "sltbits[31]" 3 332, 3 332, S_0x2753240;
+ .timescale -9 -12;
+P_0x2534b48 .param/l "i" 3 332, +C4<011111>;
+S_0x27586c0 .scope module, "attempt" "MiddleAddSubSLT" 3 334, 3 189, S_0x2752fa0;
+ .timescale -9 -12;
+L_0x2ba2e60/d .functor NOT 1, L_0x2ba7390, C4<0>, C4<0>, C4<0>;
+L_0x2ba2e60 .delay (10000,10000,10000) L_0x2ba2e60/d;
+L_0x2ba80b0/d .functor NOT 1, L_0x2ba8150, C4<0>, C4<0>, C4<0>;
+L_0x2ba80b0 .delay (10000,10000,10000) L_0x2ba80b0/d;
+L_0x2ba81f0/d .functor AND 1, L_0x2ba8330, L_0x2ba80b0, C4<1>, C4<1>;
+L_0x2ba81f0 .delay (20000,20000,20000) L_0x2ba81f0/d;
+L_0x2ba83d0/d .functor XOR 1, L_0x2ba72f0, L_0x2ba7e80, C4<0>, C4<0>;
+L_0x2ba83d0 .delay (40000,40000,40000) L_0x2ba83d0/d;
+L_0x2ba84c0/d .functor XOR 1, L_0x2ba83d0, L_0x2ba74c0, C4<0>, C4<0>;
+L_0x2ba84c0 .delay (40000,40000,40000) L_0x2ba84c0/d;
+L_0x2ba85b0/d .functor AND 1, L_0x2ba72f0, L_0x2ba7e80, C4<1>, C4<1>;
+L_0x2ba85b0 .delay (20000,20000,20000) L_0x2ba85b0/d;
+L_0x2ba8720/d .functor AND 1, L_0x2ba83d0, L_0x2ba74c0, C4<1>, C4<1>;
+L_0x2ba8720 .delay (20000,20000,20000) L_0x2ba8720/d;
+L_0x2ba8810/d .functor OR 1, L_0x2ba85b0, L_0x2ba8720, C4<0>, C4<0>;
+L_0x2ba8810 .delay (20000,20000,20000) L_0x2ba8810/d;
+v0x275b4c0_0 .net "A", 0 0, L_0x2ba72f0; 1 drivers
+v0x275b240_0 .net "AandB", 0 0, L_0x2ba85b0; 1 drivers
+v0x275b2e0_0 .net "AddSubSLTSum", 0 0, L_0x2ba84c0; 1 drivers
+v0x275ad40_0 .net "AxorB", 0 0, L_0x2ba83d0; 1 drivers
+v0x275adc0_0 .net "B", 0 0, L_0x2ba7390; 1 drivers
+v0x275ca80_0 .net "BornB", 0 0, L_0x2ba7e80; 1 drivers
+v0x275c800_0 .net "CINandAxorB", 0 0, L_0x2ba8720; 1 drivers
+v0x275c880_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x275c300_0 .net *"_s3", 0 0, L_0x2ba8150; 1 drivers
+v0x275c380_0 .net *"_s5", 0 0, L_0x2ba8330; 1 drivers
+v0x275e040_0 .net "carryin", 0 0, L_0x2ba74c0; 1 drivers
+v0x275e0c0_0 .net "carryout", 0 0, L_0x2ba8810; 1 drivers
+v0x275ddc0_0 .net "nB", 0 0, L_0x2ba2e60; 1 drivers
+v0x275de40_0 .net "nCmd2", 0 0, L_0x2ba80b0; 1 drivers
+v0x275d940_0 .net "subtract", 0 0, L_0x2ba81f0; 1 drivers
+L_0x2ba8010 .part v0x2960210_0, 0, 1;
+L_0x2ba8150 .part v0x2960210_0, 2, 1;
+L_0x2ba8330 .part v0x2960210_0, 0, 1;
+S_0x27581c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27586c0;
+ .timescale -9 -12;
+L_0x2ba2ff0/d .functor NOT 1, L_0x2ba8010, C4<0>, C4<0>, C4<0>;
+L_0x2ba2ff0 .delay (10000,10000,10000) L_0x2ba2ff0/d;
+L_0x2ba7ca0/d .functor AND 1, L_0x2ba7390, L_0x2ba2ff0, C4<1>, C4<1>;
+L_0x2ba7ca0 .delay (20000,20000,20000) L_0x2ba7ca0/d;
+L_0x2ba7d90/d .functor AND 1, L_0x2ba2e60, L_0x2ba8010, C4<1>, C4<1>;
+L_0x2ba7d90 .delay (20000,20000,20000) L_0x2ba7d90/d;
+L_0x2ba7e80/d .functor OR 1, L_0x2ba7ca0, L_0x2ba7d90, C4<0>, C4<0>;
+L_0x2ba7e80 .delay (20000,20000,20000) L_0x2ba7e80/d;
+v0x27589e0_0 .net "S", 0 0, L_0x2ba8010; 1 drivers
+v0x2759f00_0 .alias "in0", 0 0, v0x275adc0_0;
+v0x2759fa0_0 .alias "in1", 0 0, v0x275ddc0_0;
+v0x2759c80_0 .net "nS", 0 0, L_0x2ba2ff0; 1 drivers
+v0x2759d20_0 .net "out0", 0 0, L_0x2ba7ca0; 1 drivers
+v0x2759780_0 .net "out1", 0 0, L_0x2ba7d90; 1 drivers
+v0x2759820_0 .alias "outfinal", 0 0, v0x275ca80_0;
+S_0x2755640 .scope module, "setSLTres2" "TwoInMux" 3 335, 3 109, S_0x2752fa0;
+ .timescale -9 -12;
+L_0x2ba7560/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba7560 .delay (10000,10000,10000) L_0x2ba7560/d;
+L_0x2ba7600/d .functor AND 1, L_0x2ba79b0, L_0x2ba7560, C4<1>, C4<1>;
+L_0x2ba7600 .delay (20000,20000,20000) L_0x2ba7600/d;
+L_0x2ba7710/d .functor AND 1, C4<0>, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba7710 .delay (20000,20000,20000) L_0x2ba7710/d;
+L_0x2ba77d0/d .functor OR 1, L_0x2ba7600, L_0x2ba7710, C4<0>, C4<0>;
+L_0x2ba77d0 .delay (20000,20000,20000) L_0x2ba77d0/d;
+v0x2755be0_0 .alias "S", 0 0, v0x240f880_0;
+v0x2757380_0 .net "in0", 0 0, L_0x2ba79b0; 1 drivers
+v0x2757400_0 .net "in1", 0 0, C4<0>; 1 drivers
+v0x2757100_0 .net "nS", 0 0, L_0x2ba7560; 1 drivers
+v0x27571a0_0 .net "out0", 0 0, L_0x2ba7600; 1 drivers
+v0x2756c00_0 .net "out1", 0 0, L_0x2ba7710; 1 drivers
+v0x2758940_0 .net "outfinal", 0 0, L_0x2ba77d0; 1 drivers
+S_0x2754800 .scope module, "setSLTres3" "TwoInMux" 3 336, 3 109, S_0x2752fa0;
+ .timescale -9 -12;
+L_0x2ba7b30/d .functor NOT 1, L_0x2ba8dd0, C4<0>, C4<0>, C4<0>;
+L_0x2ba7b30 .delay (10000,10000,10000) L_0x2ba7b30/d;
+L_0x2ba95d0/d .functor AND 1, L_0x2ba9900, L_0x2ba7b30, C4<1>, C4<1>;
+L_0x2ba95d0 .delay (20000,20000,20000) L_0x2ba95d0/d;
+L_0x2ba9680/d .functor AND 1, L_0x2ba8b30, L_0x2ba8dd0, C4<1>, C4<1>;
+L_0x2ba9680 .delay (20000,20000,20000) L_0x2ba9680/d;
+L_0x2ba9720/d .functor OR 1, L_0x2ba95d0, L_0x2ba9680, C4<0>, C4<0>;
+L_0x2ba9720 .delay (20000,20000,20000) L_0x2ba9720/d;
+v0x2754580_0 .alias "S", 0 0, v0x240f880_0;
+v0x2754600_0 .net "in0", 0 0, L_0x2ba9900; 1 drivers
+v0x2754080_0 .net "in1", 0 0, L_0x2ba8b30; 1 drivers
+v0x2754120_0 .net "nS", 0 0, L_0x2ba7b30; 1 drivers
+v0x2755dc0_0 .net "out0", 0 0, L_0x2ba95d0; 1 drivers
+v0x2755e60_0 .net "out1", 0 0, L_0x2ba9680; 1 drivers
+v0x2755b40_0 .net "outfinal", 0 0, L_0x2ba9720; 1 drivers
+S_0x23ec510 .scope module, "trial" "AddSubSLT32" 3 53, 3 267, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x22ac8c8 .param/l "size" 3 281, +C4<0100000>;
+L_0x2bd6820/d .functor OR 1, L_0x2bd68a0, C4<0>, C4<0>, C4<0>;
+L_0x2bd6820 .delay (20000,20000,20000) L_0x2bd6820/d;
+L_0x2bc33a0/d .functor XOR 1, RS_0x7f507e9e4bc8, L_0x2b883c0, C4<0>, C4<0>;
+L_0x2bc33a0 .delay (40000,40000,40000) L_0x2bc33a0/d;
+v0x274d920_0 .alias "A", 31 0, v0x295f580_0;
+v0x274f100_0 .alias "AddSubSLTSum", 31 0, v0x2415680_0;
+v0x274f1a0_0 .alias "B", 31 0, v0x295f6a0_0;
+RS_0x7f507e9e4ad8/0/0 .resolv tri, L_0x2b3d410, L_0x2bb03d0, L_0x2bb17d0, L_0x2bb2d70;
+RS_0x7f507e9e4ad8/0/4 .resolv tri, L_0x2bb4350, L_0x2bb58a0, L_0x2bb6e00, L_0x2bb8340;
+RS_0x7f507e9e4ad8/0/8 .resolv tri, L_0x2bb9990, L_0x2bbaee0, L_0x2bbc3f0, L_0x2bbd8c0;
+RS_0x7f507e9e4ad8/0/12 .resolv tri, L_0x2bbed80, L_0x2bc0250, L_0x2bc1710, L_0x2bc2bd0;
+RS_0x7f507e9e4ad8/0/16 .resolv tri, L_0x2bc41b0, L_0x2bc55c0, L_0x2bc6a30, L_0x2bc7dc0;
+RS_0x7f507e9e4ad8/0/20 .resolv tri, L_0x2bc9140, L_0x2bca590, L_0x2bcb950, L_0x2bcce10;
+RS_0x7f507e9e4ad8/0/24 .resolv tri, L_0x2bce2e0, L_0x2bcf7a0, L_0x2bd0c80, L_0x2bd2130;
+RS_0x7f507e9e4ad8/0/28 .resolv tri, L_0x2bd3610, L_0x2bd4f10, L_0x2bd63d0, L_0x2bd78b0;
+RS_0x7f507e9e4ad8/1/0 .resolv tri, RS_0x7f507e9e4ad8/0/0, RS_0x7f507e9e4ad8/0/4, RS_0x7f507e9e4ad8/0/8, RS_0x7f507e9e4ad8/0/12;
+RS_0x7f507e9e4ad8/1/4 .resolv tri, RS_0x7f507e9e4ad8/0/16, RS_0x7f507e9e4ad8/0/20, RS_0x7f507e9e4ad8/0/24, RS_0x7f507e9e4ad8/0/28;
+RS_0x7f507e9e4ad8 .resolv tri, RS_0x7f507e9e4ad8/1/0, RS_0x7f507e9e4ad8/1/4, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>;
+v0x274ee80_0 .net8 "CarryoutWire", 31 0, RS_0x7f507e9e4ad8; 32 drivers
+v0x274ef00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x27506c0_0 .net *"_s292", 0 0, L_0x2bd68a0; 1 drivers
+v0x2750420_0 .net/s *"_s293", 0 0, C4<0>; 1 drivers
+v0x27504c0_0 .net *"_s296", 0 0, L_0x2b883c0; 1 drivers
+v0x2751c80_0 .alias "carryin", 31 0, v0x2609fe0_0;
+v0x2751d20_0 .alias "carryout", 0 0, v0x2960740_0;
+v0x2751a00_0 .alias "overflow", 0 0, v0x29608f0_0;
+v0x2751a80_0 .alias "subtract", 31 0, v0x25ec920_0;
+L_0x2baea80 .part/pv L_0x2bacc80, 1, 1, 32;
+L_0x2b3d410 .part/pv L_0x2bae940, 1, 1, 32;
+L_0x2b3d500 .part/pv L_0x2bac9b0, 1, 1, 32;
+L_0x2b3d5f0 .part v0x295fe90_0, 1, 1;
+L_0x2b3d690 .part v0x2960190_0, 1, 1;
+L_0x2baf3c0 .part RS_0x7f507e9e4ad8, 0, 1;
+L_0x2bb02e0 .part/pv L_0x2bafe50, 2, 1, 32;
+L_0x2bb03d0 .part/pv L_0x2bb01a0, 2, 1, 32;
+L_0x2bb0510 .part/pv L_0x2bafb80, 2, 1, 32;
+L_0x2bb0600 .part v0x295fe90_0, 2, 1;
+L_0x2bb0700 .part v0x2960190_0, 2, 1;
+L_0x2bb0830 .part RS_0x7f507e9e4ad8, 1, 1;
+L_0x2bb16e0 .part/pv L_0x2bb1250, 3, 1, 32;
+L_0x2bb17d0 .part/pv L_0x2bb15a0, 3, 1, 32;
+L_0x2bb1940 .part/pv L_0x2bb0f80, 3, 1, 32;
+L_0x2bb1a30 .part v0x295fe90_0, 3, 1;
+L_0x2bb1b60 .part v0x2960190_0, 3, 1;
+L_0x2bb1c90 .part RS_0x7f507e9e4ad8, 2, 1;
+L_0x2bb2c80 .part/pv L_0x2bb27d0, 4, 1, 32;
+L_0x2bb2d70 .part/pv L_0x2bb2b20, 4, 1, 32;
+L_0x2bb1d30 .part/pv L_0x2bb2500, 4, 1, 32;
+L_0x2bb2f60 .part v0x295fe90_0, 4, 1;
+L_0x2bb2e60 .part v0x2960190_0, 4, 1;
+L_0x2bb3150 .part RS_0x7f507e9e4ad8, 3, 1;
+L_0x2bb4260 .part/pv L_0x2bb3d90, 5, 1, 32;
+L_0x2bb4350 .part/pv L_0x2bb4100, 5, 1, 32;
+L_0x2bb3300 .part/pv L_0x2bb3ac0, 5, 1, 32;
+L_0x2bb4570 .part v0x295fe90_0, 5, 1;
+L_0x2bb4440 .part v0x2960190_0, 5, 1;
+L_0x2bb4790 .part RS_0x7f507e9e4ad8, 4, 1;
+L_0x2bb57b0 .part/pv L_0x2bb52c0, 6, 1, 32;
+L_0x2bb58a0 .part/pv L_0x2bb5650, 6, 1, 32;
+L_0x2bb4830 .part/pv L_0x2bb4ff0, 6, 1, 32;
+L_0x2bb5aa0 .part v0x295fe90_0, 6, 1;
+L_0x2bb5990 .part v0x2960190_0, 6, 1;
+L_0x2bb5cf0 .part RS_0x7f507e9e4ad8, 5, 1;
+L_0x2bb6d10 .part/pv L_0x2bb6840, 7, 1, 32;
+L_0x2bb6e00 .part/pv L_0x2bb6bb0, 7, 1, 32;
+L_0x2bb5d90 .part/pv L_0x2bb6570, 7, 1, 32;
+L_0x2bb7030 .part v0x295fe90_0, 7, 1;
+L_0x2bb6ef0 .part v0x2960190_0, 7, 1;
+L_0x2bb7220 .part RS_0x7f507e9e4ad8, 6, 1;
+L_0x2bb8250 .part/pv L_0x2bb7d80, 8, 1, 32;
+L_0x2bb8340 .part/pv L_0x2bb80f0, 8, 1, 32;
+L_0x2bb72c0 .part/pv L_0x2bb7ab0, 8, 1, 32;
+L_0x2bb85a0 .part v0x295fe90_0, 8, 1;
+L_0x2bb8430 .part v0x2960190_0, 8, 1;
+L_0x2bb87c0 .part RS_0x7f507e9e4ad8, 7, 1;
+L_0x2bb98a0 .part/pv L_0x2bb93d0, 9, 1, 32;
+L_0x2bb9990 .part/pv L_0x2bb9740, 9, 1, 32;
+L_0x2bb8a70 .part/pv L_0x2bb9100, 9, 1, 32;
+L_0x2bb8b60 .part v0x295fe90_0, 9, 1;
+L_0x2bb9c30 .part v0x2960190_0, 9, 1;
+L_0x2bb9d60 .part RS_0x7f507e9e4ad8, 8, 1;
+L_0x2bbadf0 .part/pv L_0x2bba920, 10, 1, 32;
+L_0x2bbaee0 .part/pv L_0x2bbac90, 10, 1, 32;
+L_0x2bb9e00 .part/pv L_0x2bba650, 10, 1, 32;
+L_0x2bb9ef0 .part v0x295fe90_0, 10, 1;
+L_0x2bbb1b0 .part v0x2960190_0, 10, 1;
+L_0x2bbb2e0 .part RS_0x7f507e9e4ad8, 9, 1;
+L_0x2bbc300 .part/pv L_0x2bbbe50, 11, 1, 32;
+L_0x2bbc3f0 .part/pv L_0x2bbc1a0, 11, 1, 32;
+L_0x2bbb380 .part/pv L_0x2bbbb80, 11, 1, 32;
+L_0x2bbb470 .part v0x295fe90_0, 11, 1;
+L_0x2bbc6f0 .part v0x2960190_0, 11, 1;
+L_0x2bbc820 .part RS_0x7f507e9e4ad8, 10, 1;
+L_0x2bbd7d0 .part/pv L_0x2bbd320, 12, 1, 32;
+L_0x2bbd8c0 .part/pv L_0x2bbd670, 12, 1, 32;
+L_0x2bbc8c0 .part/pv L_0x2bbd050, 12, 1, 32;
+L_0x2bbc9b0 .part v0x295fe90_0, 12, 1;
+L_0x2bbdbf0 .part v0x2960190_0, 12, 1;
+L_0x2bbdc90 .part RS_0x7f507e9e4ad8, 11, 1;
+L_0x2bbec90 .part/pv L_0x2bbe7e0, 13, 1, 32;
+L_0x2bbed80 .part/pv L_0x2bbeb30, 13, 1, 32;
+L_0x2bbdd30 .part/pv L_0x2bbe510, 13, 1, 32;
+L_0x2bbde20 .part v0x295fe90_0, 13, 1;
+L_0x2bbdec0 .part v0x2960190_0, 13, 1;
+L_0x2bbf170 .part RS_0x7f507e9e4ad8, 12, 1;
+L_0x2bc0160 .part/pv L_0x2bbfcb0, 14, 1, 32;
+L_0x2bc0250 .part/pv L_0x2bc0000, 14, 1, 32;
+L_0x2bbf210 .part/pv L_0x2bbf9e0, 14, 1, 32;
+L_0x2bbf300 .part v0x295fe90_0, 14, 1;
+L_0x2bbf3a0 .part v0x2960190_0, 14, 1;
+L_0x2bc0670 .part RS_0x7f507e9e4ad8, 13, 1;
+L_0x2bc1620 .part/pv L_0x2bc1170, 15, 1, 32;
+L_0x2bc1710 .part/pv L_0x2bc14c0, 15, 1, 32;
+L_0x2bc0710 .part/pv L_0x2bc0ea0, 15, 1, 32;
+L_0x2bc0800 .part v0x295fe90_0, 15, 1;
+L_0x2bc08a0 .part v0x2960190_0, 15, 1;
+L_0x2bc1b60 .part RS_0x7f507e9e4ad8, 14, 1;
+L_0x2bc2ae0 .part/pv L_0x2bc2630, 16, 1, 32;
+L_0x2bc2bd0 .part/pv L_0x2bc2980, 16, 1, 32;
+L_0x2bc1c00 .part/pv L_0x2bc2360, 16, 1, 32;
+L_0x2bc1cf0 .part v0x295fe90_0, 16, 1;
+L_0x2bc1d90 .part v0x2960190_0, 16, 1;
+L_0x2bc2fc0 .part RS_0x7f507e9e4ad8, 15, 1;
+L_0x2bc40c0 .part/pv L_0x2bc3c30, 17, 1, 32;
+L_0x2bc41b0 .part/pv L_0x2bc3f80, 17, 1, 32;
+L_0x2bc3470 .part/pv L_0x2bc3960, 17, 1, 32;
+L_0x2bc3560 .part v0x295fe90_0, 17, 1;
+L_0x2bc3600 .part v0x2960190_0, 17, 1;
+L_0x2bc45d0 .part RS_0x7f507e9e4ad8, 16, 1;
+L_0x2bc54d0 .part/pv L_0x2bc5040, 18, 1, 32;
+L_0x2bc55c0 .part/pv L_0x2bc5390, 18, 1, 32;
+L_0x2bc4670 .part/pv L_0x2bc4db0, 18, 1, 32;
+L_0x2bc4760 .part v0x295fe90_0, 18, 1;
+L_0x2bc4800 .part v0x2960190_0, 18, 1;
+L_0x2bc5a10 .part RS_0x7f507e9e4ad8, 17, 1;
+L_0x2bc6940 .part/pv L_0x2bc64b0, 19, 1, 32;
+L_0x2bc6a30 .part/pv L_0x2bc6800, 19, 1, 32;
+L_0x2bc5ab0 .part/pv L_0x2bc61e0, 19, 1, 32;
+L_0x2bc5ba0 .part v0x295fe90_0, 19, 1;
+L_0x2bc5c40 .part v0x2960190_0, 19, 1;
+L_0x2bc5d70 .part RS_0x7f507e9e4ad8, 18, 1;
+L_0x2bc7cd0 .part/pv L_0x2bc7840, 20, 1, 32;
+L_0x2bc7dc0 .part/pv L_0x2bc7b90, 20, 1, 32;
+L_0x2bc6b20 .part/pv L_0x2bc7570, 20, 1, 32;
+L_0x2bc6c10 .part v0x295fe90_0, 20, 1;
+L_0x2bc6cb0 .part v0x2960190_0, 20, 1;
+L_0x2bc6de0 .part RS_0x7f507e9e4ad8, 19, 1;
+L_0x2bc9050 .part/pv L_0x2bc8bc0, 21, 1, 32;
+L_0x2bc9140 .part/pv L_0x2bc8f10, 21, 1, 32;
+L_0x2bc7eb0 .part/pv L_0x2bc88f0, 21, 1, 32;
+L_0x2bc7fa0 .part v0x295fe90_0, 21, 1;
+L_0x2bc8040 .part v0x2960190_0, 21, 1;
+L_0x2bc8170 .part RS_0x7f507e9e4ad8, 20, 1;
+L_0x2bca4a0 .part/pv L_0x2bc9fd0, 22, 1, 32;
+L_0x2bca590 .part/pv L_0x2bca340, 22, 1, 32;
+L_0x2bc9230 .part/pv L_0x2bc9d00, 22, 1, 32;
+L_0x2bc9320 .part v0x295fe90_0, 22, 1;
+L_0x2bc93c0 .part v0x2960190_0, 22, 1;
+L_0x2bc94f0 .part RS_0x7f507e9e4ad8, 21, 1;
+L_0x2bcb860 .part/pv L_0x2bcb390, 23, 1, 32;
+L_0x2bcb950 .part/pv L_0x2bcb700, 23, 1, 32;
+L_0x2bca680 .part/pv L_0x2bcb0c0, 23, 1, 32;
+L_0x2bca770 .part v0x295fe90_0, 23, 1;
+L_0x2bca810 .part v0x2960190_0, 23, 1;
+L_0x2bca940 .part RS_0x7f507e9e4ad8, 22, 1;
+L_0x2bccd20 .part/pv L_0x2bcc7f0, 24, 1, 32;
+L_0x2bcce10 .part/pv L_0x2bccbc0, 24, 1, 32;
+L_0x2bcba40 .part/pv L_0x2bcc520, 24, 1, 32;
+L_0x2bcbb30 .part v0x295fe90_0, 24, 1;
+L_0x2bcbbd0 .part v0x2960190_0, 24, 1;
+L_0x2bcbd00 .part RS_0x7f507e9e4ad8, 23, 1;
+L_0x2bce1f0 .part/pv L_0x2bcdcc0, 25, 1, 32;
+L_0x2bce2e0 .part/pv L_0x2bce090, 25, 1, 32;
+L_0x2bccf00 .part/pv L_0x2bcd9f0, 25, 1, 32;
+L_0x2bccff0 .part v0x295fe90_0, 25, 1;
+L_0x2bcd090 .part v0x2960190_0, 25, 1;
+L_0x2bcd1c0 .part RS_0x7f507e9e4ad8, 24, 1;
+L_0x2bcf6b0 .part/pv L_0x2bcf1e0, 26, 1, 32;
+L_0x2bcf7a0 .part/pv L_0x2bcf550, 26, 1, 32;
+L_0x2bce3d0 .part/pv L_0x2bcef10, 26, 1, 32;
+L_0x2bce4c0 .part v0x295fe90_0, 26, 1;
+L_0x2bce560 .part v0x2960190_0, 26, 1;
+L_0x2bce690 .part RS_0x7f507e9e4ad8, 25, 1;
+L_0x2bd0b90 .part/pv L_0x2bd06a0, 27, 1, 32;
+L_0x2bd0c80 .part/pv L_0x2bd0a30, 27, 1, 32;
+L_0x2bcf890 .part/pv L_0x2bd03d0, 27, 1, 32;
+L_0x2bcf980 .part v0x295fe90_0, 27, 1;
+L_0x2bcfa20 .part v0x2960190_0, 27, 1;
+L_0x2bcfb50 .part RS_0x7f507e9e4ad8, 26, 1;
+L_0x2bd2040 .part/pv L_0x2bd1b70, 28, 1, 32;
+L_0x2bd2130 .part/pv L_0x2bd1ee0, 28, 1, 32;
+L_0x2bd0d70 .part/pv L_0x2bd18a0, 28, 1, 32;
+L_0x2bd0e60 .part v0x295fe90_0, 28, 1;
+L_0x2bd0f00 .part v0x2960190_0, 28, 1;
+L_0x2bd1030 .part RS_0x7f507e9e4ad8, 27, 1;
+L_0x2bd3520 .part/pv L_0x2bd3020, 29, 1, 32;
+L_0x2bd3610 .part/pv L_0x2bd33c0, 29, 1, 32;
+L_0x2bd2220 .part/pv L_0x2bd2d20, 29, 1, 32;
+L_0x2ba56b0 .part v0x295fe90_0, 29, 1;
+L_0x2ba5750 .part v0x2960190_0, 29, 1;
+L_0x2ba5880 .part RS_0x7f507e9e4ad8, 28, 1;
+L_0x2bd4e20 .part/pv L_0x2bd3bd0, 30, 1, 32;
+L_0x2bd4f10 .part/pv L_0x2bd4ce0, 30, 1, 32;
+L_0x2bd4470 .part/pv L_0x2bd3900, 30, 1, 32;
+L_0x2bd4560 .part v0x295fe90_0, 30, 1;
+L_0x2bd4600 .part v0x2960190_0, 30, 1;
+L_0x2bd4730 .part RS_0x7f507e9e4ad8, 29, 1;
+L_0x2bd62e0 .part/pv L_0x2bd5dd0, 31, 1, 32;
+L_0x2bd63d0 .part/pv L_0x2bd6180, 31, 1, 32;
+L_0x2bd5000 .part/pv L_0x2bd5b00, 31, 1, 32;
+L_0x2bd50f0 .part v0x295fe90_0, 31, 1;
+L_0x2bd5190 .part v0x2960190_0, 31, 1;
+L_0x2bd52c0 .part RS_0x7f507e9e4ad8, 30, 1;
+L_0x2bd77c0 .part/pv L_0x2bd72b0, 0, 1, 32;
+L_0x2bd78b0 .part/pv L_0x2bd7660, 0, 1, 32;
+L_0x2bd64c0 .part/pv L_0x2bd6fb0, 0, 1, 32;
+L_0x2bd65b0 .part v0x295fe90_0, 0, 1;
+L_0x2bd6650 .part v0x2960190_0, 0, 1;
+L_0x2bd6780 .part RS_0x7f507e9e4c28, 0, 1;
+L_0x2bd68a0 .part RS_0x7f507e9e4ad8, 31, 1;
+L_0x2b883c0 .part RS_0x7f507e9e4ad8, 30, 1;
+S_0x2743c70 .scope module, "attempt2" "MiddleAddSubSLT" 3 278, 3 189, S_0x23ec510;
+ .timescale -9 -12;
+L_0x2bd5360/d .functor NOT 1, L_0x2bd6650, C4<0>, C4<0>, C4<0>;
+L_0x2bd5360 .delay (10000,10000,10000) L_0x2bd5360/d;
+L_0x2bd6e70/d .functor NOT 1, L_0x2bd6f10, C4<0>, C4<0>, C4<0>;
+L_0x2bd6e70 .delay (10000,10000,10000) L_0x2bd6e70/d;
+L_0x2bd6fb0/d .functor AND 1, L_0x2bd70f0, L_0x2bd6e70, C4<1>, C4<1>;
+L_0x2bd6fb0 .delay (20000,20000,20000) L_0x2bd6fb0/d;
+L_0x2bd7190/d .functor XOR 1, L_0x2bd65b0, L_0x2bd6c40, C4<0>, C4<0>;
+L_0x2bd7190 .delay (40000,40000,40000) L_0x2bd7190/d;
+L_0x2bd72b0/d .functor XOR 1, L_0x2bd7190, L_0x2bd6780, C4<0>, C4<0>;
+L_0x2bd72b0 .delay (40000,40000,40000) L_0x2bd72b0/d;
+L_0x2bd73d0/d .functor AND 1, L_0x2bd65b0, L_0x2bd6c40, C4<1>, C4<1>;
+L_0x2bd73d0 .delay (20000,20000,20000) L_0x2bd73d0/d;
+L_0x2bd7570/d .functor AND 1, L_0x2bd7190, L_0x2bd6780, C4<1>, C4<1>;
+L_0x2bd7570 .delay (20000,20000,20000) L_0x2bd7570/d;
+L_0x2bd7660/d .functor OR 1, L_0x2bd73d0, L_0x2bd7570, C4<0>, C4<0>;
+L_0x2bd7660 .delay (20000,20000,20000) L_0x2bd7660/d;
+v0x27484e0_0 .net "A", 0 0, L_0x2bd65b0; 1 drivers
+v0x27481a0_0 .net "AandB", 0 0, L_0x2bd73d0; 1 drivers
+v0x2748240_0 .net "AddSubSLTSum", 0 0, L_0x2bd72b0; 1 drivers
+v0x2749a00_0 .net "AxorB", 0 0, L_0x2bd7190; 1 drivers
+v0x2749a80_0 .net "B", 0 0, L_0x2bd6650; 1 drivers
+v0x2749780_0 .net "BornB", 0 0, L_0x2bd6c40; 1 drivers
+v0x274afc0_0 .net "CINandAxorB", 0 0, L_0x2bd7570; 1 drivers
+v0x274b040_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x274ad20_0 .net *"_s3", 0 0, L_0x2bd6f10; 1 drivers
+v0x274ada0_0 .net *"_s5", 0 0, L_0x2bd70f0; 1 drivers
+v0x274c580_0 .net "carryin", 0 0, L_0x2bd6780; 1 drivers
+v0x274c600_0 .net "carryout", 0 0, L_0x2bd7660; 1 drivers
+v0x274c300_0 .net "nB", 0 0, L_0x2bd5360; 1 drivers
+v0x274db40_0 .net "nCmd2", 0 0, L_0x2bd6e70; 1 drivers
+v0x274d8a0_0 .net "subtract", 0 0, L_0x2bd6fb0; 1 drivers
+L_0x2bd6dd0 .part v0x2960210_0, 0, 1;
+L_0x2bd6f10 .part v0x2960210_0, 2, 1;
+L_0x2bd70f0 .part v0x2960210_0, 0, 1;
+S_0x27458c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2743c70;
+ .timescale -9 -12;
+L_0x2bd54c0/d .functor NOT 1, L_0x2bd6dd0, C4<0>, C4<0>, C4<0>;
+L_0x2bd54c0 .delay (10000,10000,10000) L_0x2bd54c0/d;
+L_0x2bd6aa0/d .functor AND 1, L_0x2bd6650, L_0x2bd54c0, C4<1>, C4<1>;
+L_0x2bd6aa0 .delay (20000,20000,20000) L_0x2bd6aa0/d;
+L_0x2bd6b50/d .functor AND 1, L_0x2bd5360, L_0x2bd6dd0, C4<1>, C4<1>;
+L_0x2bd6b50 .delay (20000,20000,20000) L_0x2bd6b50/d;
+L_0x2bd6c40/d .functor OR 1, L_0x2bd6aa0, L_0x2bd6b50, C4<0>, C4<0>;
+L_0x2bd6c40 .delay (20000,20000,20000) L_0x2bd6c40/d;
+v0x2744100_0 .net "S", 0 0, L_0x2bd6dd0; 1 drivers
+v0x2745620_0 .alias "in0", 0 0, v0x2749a80_0;
+v0x27456c0_0 .alias "in1", 0 0, v0x274c300_0;
+v0x2746e80_0 .net "nS", 0 0, L_0x2bd54c0; 1 drivers
+v0x2746f00_0 .net "out0", 0 0, L_0x2bd6aa0; 1 drivers
+v0x2746c00_0 .net "out1", 0 0, L_0x2bd6b50; 1 drivers
+v0x2748440_0 .alias "outfinal", 0 0, v0x2749780_0;
+S_0x2767860 .scope generate, "addbits[1]" "addbits[1]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x25ea758 .param/l "i" 3 283, +C4<01>;
+S_0x27675f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2767860;
+ .timescale -9 -12;
+L_0x2b650c0/d .functor NOT 1, L_0x2b3d690, C4<0>, C4<0>, C4<0>;
+L_0x2b650c0 .delay (10000,10000,10000) L_0x2b650c0/d;
+L_0x2bac850/d .functor NOT 1, L_0x2bac910, C4<0>, C4<0>, C4<0>;
+L_0x2bac850 .delay (10000,10000,10000) L_0x2bac850/d;
+L_0x2bac9b0/d .functor AND 1, L_0x2bacaf0, L_0x2bac850, C4<1>, C4<1>;
+L_0x2bac9b0 .delay (20000,20000,20000) L_0x2bac9b0/d;
+L_0x2bacb90/d .functor XOR 1, L_0x2b3d5f0, L_0x2bac5e0, C4<0>, C4<0>;
+L_0x2bacb90 .delay (40000,40000,40000) L_0x2bacb90/d;
+L_0x2bacc80/d .functor XOR 1, L_0x2bacb90, L_0x2baf3c0, C4<0>, C4<0>;
+L_0x2bacc80 .delay (40000,40000,40000) L_0x2bacc80/d;
+L_0x2bacd70/d .functor AND 1, L_0x2b3d5f0, L_0x2bac5e0, C4<1>, C4<1>;
+L_0x2bacd70 .delay (20000,20000,20000) L_0x2bacd70/d;
+L_0x2bacee0/d .functor AND 1, L_0x2bacb90, L_0x2baf3c0, C4<1>, C4<1>;
+L_0x2bacee0 .delay (20000,20000,20000) L_0x2bacee0/d;
+L_0x2bae940/d .functor OR 1, L_0x2bacd70, L_0x2bacee0, C4<0>, C4<0>;
+L_0x2bae940 .delay (20000,20000,20000) L_0x2bae940/d;
+v0x27400d0_0 .net "A", 0 0, L_0x2b3d5f0; 1 drivers
+v0x273fb30_0 .net "AandB", 0 0, L_0x2bacd70; 1 drivers
+v0x273fbd0_0 .net "AddSubSLTSum", 0 0, L_0x2bacc80; 1 drivers
+v0x2741870_0 .net "AxorB", 0 0, L_0x2bacb90; 1 drivers
+v0x27418f0_0 .net "B", 0 0, L_0x2b3d690; 1 drivers
+v0x27415f0_0 .net "BornB", 0 0, L_0x2bac5e0; 1 drivers
+v0x27410f0_0 .net "CINandAxorB", 0 0, L_0x2bacee0; 1 drivers
+v0x2741170_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2742e30_0 .net *"_s3", 0 0, L_0x2bac910; 1 drivers
+v0x2742eb0_0 .net *"_s5", 0 0, L_0x2bacaf0; 1 drivers
+v0x2742bb0_0 .net "carryin", 0 0, L_0x2baf3c0; 1 drivers
+v0x2742c30_0 .net "carryout", 0 0, L_0x2bae940; 1 drivers
+v0x27426b0_0 .net "nB", 0 0, L_0x2b650c0; 1 drivers
+v0x2744300_0 .net "nCmd2", 0 0, L_0x2bac850; 1 drivers
+v0x2744080_0 .net "subtract", 0 0, L_0x2bac9b0; 1 drivers
+L_0x2bac7b0 .part v0x2960210_0, 0, 1;
+L_0x2bac910 .part v0x2960210_0, 2, 1;
+L_0x2bacaf0 .part v0x2960210_0, 0, 1;
+S_0x273d400 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27675f0;
+ .timescale -9 -12;
+L_0x2b652b0/d .functor NOT 1, L_0x2bac7b0, C4<0>, C4<0>, C4<0>;
+L_0x2b652b0 .delay (10000,10000,10000) L_0x2b652b0/d;
+L_0x2b65370/d .functor AND 1, L_0x2b3d690, L_0x2b652b0, C4<1>, C4<1>;
+L_0x2b65370 .delay (20000,20000,20000) L_0x2b65370/d;
+L_0x2bac4d0/d .functor AND 1, L_0x2b650c0, L_0x2bac7b0, C4<1>, C4<1>;
+L_0x2bac4d0 .delay (20000,20000,20000) L_0x2bac4d0/d;
+L_0x2bac5e0/d .functor OR 1, L_0x2b65370, L_0x2bac4d0, C4<0>, C4<0>;
+L_0x2bac5e0 .delay (20000,20000,20000) L_0x2bac5e0/d;
+v0x2736710_0 .net "S", 0 0, L_0x2bac7b0; 1 drivers
+v0x273ecf0_0 .alias "in0", 0 0, v0x27418f0_0;
+v0x273ed90_0 .alias "in1", 0 0, v0x27426b0_0;
+v0x273ea70_0 .net "nS", 0 0, L_0x2b652b0; 1 drivers
+v0x273eaf0_0 .net "out0", 0 0, L_0x2b65370; 1 drivers
+v0x27402b0_0 .net "out1", 0 0, L_0x2bac4d0; 1 drivers
+v0x2740030_0 .alias "outfinal", 0 0, v0x27415f0_0;
+S_0x272ca90 .scope generate, "addbits[2]" "addbits[2]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x26bf0f8 .param/l "i" 3 283, +C4<010>;
+S_0x272ae50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x272ca90;
+ .timescale -9 -12;
+L_0x2b3d730/d .functor NOT 1, L_0x2bb0700, C4<0>, C4<0>, C4<0>;
+L_0x2b3d730 .delay (10000,10000,10000) L_0x2b3d730/d;
+L_0x2bafa40/d .functor NOT 1, L_0x2bafae0, C4<0>, C4<0>, C4<0>;
+L_0x2bafa40 .delay (10000,10000,10000) L_0x2bafa40/d;
+L_0x2bafb80/d .functor AND 1, L_0x2bafcc0, L_0x2bafa40, C4<1>, C4<1>;
+L_0x2bafb80 .delay (20000,20000,20000) L_0x2bafb80/d;
+L_0x2bafd60/d .functor XOR 1, L_0x2bb0600, L_0x2baf810, C4<0>, C4<0>;
+L_0x2bafd60 .delay (40000,40000,40000) L_0x2bafd60/d;
+L_0x2bafe50/d .functor XOR 1, L_0x2bafd60, L_0x2bb0830, C4<0>, C4<0>;
+L_0x2bafe50 .delay (40000,40000,40000) L_0x2bafe50/d;
+L_0x2baff40/d .functor AND 1, L_0x2bb0600, L_0x2baf810, C4<1>, C4<1>;
+L_0x2baff40 .delay (20000,20000,20000) L_0x2baff40/d;
+L_0x2bb00b0/d .functor AND 1, L_0x2bafd60, L_0x2bb0830, C4<1>, C4<1>;
+L_0x2bb00b0 .delay (20000,20000,20000) L_0x2bb00b0/d;
+L_0x2bb01a0/d .functor OR 1, L_0x2baff40, L_0x2bb00b0, C4<0>, C4<0>;
+L_0x2bb01a0 .delay (20000,20000,20000) L_0x2bb01a0/d;
+v0x2732c40_0 .net "A", 0 0, L_0x2bb0600; 1 drivers
+v0x2732940_0 .net "AandB", 0 0, L_0x2baff40; 1 drivers
+v0x27329e0_0 .net "AddSubSLTSum", 0 0, L_0x2bafe50; 1 drivers
+v0x2732690_0 .net "AxorB", 0 0, L_0x2bafd60; 1 drivers
+v0x2732710_0 .net "B", 0 0, L_0x2bb0700; 1 drivers
+v0x2730a50_0 .net "BornB", 0 0, L_0x2baf810; 1 drivers
+v0x2735790_0 .net "CINandAxorB", 0 0, L_0x2bb00b0; 1 drivers
+v0x2735810_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x27354e0_0 .net *"_s3", 0 0, L_0x2bafae0; 1 drivers
+v0x2735560_0 .net *"_s5", 0 0, L_0x2bafcc0; 1 drivers
+v0x2733850_0 .net "carryin", 0 0, L_0x2bb0830; 1 drivers
+v0x27338d0_0 .net "carryout", 0 0, L_0x2bb01a0; 1 drivers
+v0x27385d0_0 .net "nB", 0 0, L_0x2b3d730; 1 drivers
+v0x2738320_0 .net "nCmd2", 0 0, L_0x2bafa40; 1 drivers
+v0x2736690_0 .net "subtract", 0 0, L_0x2bafb80; 1 drivers
+L_0x2baf9a0 .part v0x2960210_0, 0, 1;
+L_0x2bafae0 .part v0x2960210_0, 2, 1;
+L_0x2bafcc0 .part v0x2960210_0, 0, 1;
+S_0x272fda0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x272ae50;
+ .timescale -9 -12;
+L_0x2baf590/d .functor NOT 1, L_0x2baf9a0, C4<0>, C4<0>, C4<0>;
+L_0x2baf590 .delay (10000,10000,10000) L_0x2baf590/d;
+L_0x2baf630/d .functor AND 1, L_0x2bb0700, L_0x2baf590, C4<1>, C4<1>;
+L_0x2baf630 .delay (20000,20000,20000) L_0x2baf630/d;
+L_0x2baf720/d .functor AND 1, L_0x2b3d730, L_0x2baf9a0, C4<1>, C4<1>;
+L_0x2baf720 .delay (20000,20000,20000) L_0x2baf720/d;
+L_0x2baf810/d .functor OR 1, L_0x2baf630, L_0x2baf720, C4<0>, C4<0>;
+L_0x2baf810 .delay (20000,20000,20000) L_0x2baf810/d;
+v0x272cdc0_0 .net "S", 0 0, L_0x2baf9a0; 1 drivers
+v0x272fb40_0 .alias "in0", 0 0, v0x2732710_0;
+v0x272fbe0_0 .alias "in1", 0 0, v0x27385d0_0;
+v0x272f890_0 .net "nS", 0 0, L_0x2baf590; 1 drivers
+v0x272f910_0 .net "out0", 0 0, L_0x2baf630; 1 drivers
+v0x272dc50_0 .net "out1", 0 0, L_0x2baf720; 1 drivers
+v0x2732ba0_0 .alias "outfinal", 0 0, v0x2730a50_0;
+S_0x271f7d0 .scope generate, "addbits[3]" "addbits[3]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x26b5778 .param/l "i" 3 283, +C4<011>;
+S_0x27245a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x271f7d0;
+ .timescale -9 -12;
+L_0x2bb06a0/d .functor NOT 1, L_0x2bb1b60, C4<0>, C4<0>, C4<0>;
+L_0x2bb06a0 .delay (10000,10000,10000) L_0x2bb06a0/d;
+L_0x2bb0e40/d .functor NOT 1, L_0x2bb0ee0, C4<0>, C4<0>, C4<0>;
+L_0x2bb0e40 .delay (10000,10000,10000) L_0x2bb0e40/d;
+L_0x2bb0f80/d .functor AND 1, L_0x2bb10c0, L_0x2bb0e40, C4<1>, C4<1>;
+L_0x2bb0f80 .delay (20000,20000,20000) L_0x2bb0f80/d;
+L_0x2bb1160/d .functor XOR 1, L_0x2bb1a30, L_0x2bb0c10, C4<0>, C4<0>;
+L_0x2bb1160 .delay (40000,40000,40000) L_0x2bb1160/d;
+L_0x2bb1250/d .functor XOR 1, L_0x2bb1160, L_0x2bb1c90, C4<0>, C4<0>;
+L_0x2bb1250 .delay (40000,40000,40000) L_0x2bb1250/d;
+L_0x2bb1340/d .functor AND 1, L_0x2bb1a30, L_0x2bb0c10, C4<1>, C4<1>;
+L_0x2bb1340 .delay (20000,20000,20000) L_0x2bb1340/d;
+L_0x2bb14b0/d .functor AND 1, L_0x2bb1160, L_0x2bb1c90, C4<1>, C4<1>;
+L_0x2bb14b0 .delay (20000,20000,20000) L_0x2bb14b0/d;
+L_0x2bb15a0/d .functor OR 1, L_0x2bb1340, L_0x2bb14b0, C4<0>, C4<0>;
+L_0x2bb15a0 .delay (20000,20000,20000) L_0x2bb15a0/d;
+v0x27271e0_0 .net "A", 0 0, L_0x2bb1a30; 1 drivers
+v0x2726e90_0 .net "AandB", 0 0, L_0x2bb1340; 1 drivers
+v0x2726f30_0 .net "AddSubSLTSum", 0 0, L_0x2bb1250; 1 drivers
+v0x2725250_0 .net "AxorB", 0 0, L_0x2bb1160; 1 drivers
+v0x27252f0_0 .net "B", 0 0, L_0x2bb1b60; 1 drivers
+v0x272a1a0_0 .net "BornB", 0 0, L_0x2bb0c10; 1 drivers
+v0x272a220_0 .net "CINandAxorB", 0 0, L_0x2bb14b0; 1 drivers
+v0x2729f40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2729fc0_0 .net *"_s3", 0 0, L_0x2bb0ee0; 1 drivers
+v0x2729c90_0 .net *"_s5", 0 0, L_0x2bb10c0; 1 drivers
+v0x2729d10_0 .net "carryin", 0 0, L_0x2bb1c90; 1 drivers
+v0x2728050_0 .net "carryout", 0 0, L_0x2bb15a0; 1 drivers
+v0x27280d0_0 .net "nB", 0 0, L_0x2bb06a0; 1 drivers
+v0x272cfa0_0 .net "nCmd2", 0 0, L_0x2bb0e40; 1 drivers
+v0x272cd40_0 .net "subtract", 0 0, L_0x2bb0f80; 1 drivers
+L_0x2bb0da0 .part v0x2960210_0, 0, 1;
+L_0x2bb0ee0 .part v0x2960210_0, 2, 1;
+L_0x2bb10c0 .part v0x2960210_0, 0, 1;
+S_0x2724340 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27245a0;
+ .timescale -9 -12;
+L_0x2bb09d0/d .functor NOT 1, L_0x2bb0da0, C4<0>, C4<0>, C4<0>;
+L_0x2bb09d0 .delay (10000,10000,10000) L_0x2bb09d0/d;
+L_0x2bb0a30/d .functor AND 1, L_0x2bb1b60, L_0x2bb09d0, C4<1>, C4<1>;
+L_0x2bb0a30 .delay (20000,20000,20000) L_0x2bb0a30/d;
+L_0x2bb0b20/d .functor AND 1, L_0x2bb06a0, L_0x2bb0da0, C4<1>, C4<1>;
+L_0x2bb0b20 .delay (20000,20000,20000) L_0x2bb0b20/d;
+L_0x2bb0c10/d .functor OR 1, L_0x2bb0a30, L_0x2bb0b20, C4<0>, C4<0>;
+L_0x2bb0c10 .delay (20000,20000,20000) L_0x2bb0c10/d;
+v0x2724090_0 .net "S", 0 0, L_0x2bb0da0; 1 drivers
+v0x2724110_0 .alias "in0", 0 0, v0x27252f0_0;
+v0x2722610_0 .alias "in1", 0 0, v0x27280d0_0;
+v0x27226b0_0 .net "nS", 0 0, L_0x2bb09d0; 1 drivers
+v0x27273a0_0 .net "out0", 0 0, L_0x2bb0a30; 1 drivers
+v0x2727440_0 .net "out1", 0 0, L_0x2bb0b20; 1 drivers
+v0x2727140_0 .alias "outfinal", 0 0, v0x272a1a0_0;
+S_0x27110d0 .scope generate, "addbits[4]" "addbits[4]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2663f98 .param/l "i" 3 283, +C4<0100>;
+S_0x2715e10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x27110d0;
+ .timescale -9 -12;
+L_0x2bb1ad0/d .functor NOT 1, L_0x2bb2e60, C4<0>, C4<0>, C4<0>;
+L_0x2bb1ad0 .delay (10000,10000,10000) L_0x2bb1ad0/d;
+L_0x2bb23a0/d .functor NOT 1, L_0x2bb2460, C4<0>, C4<0>, C4<0>;
+L_0x2bb23a0 .delay (10000,10000,10000) L_0x2bb23a0/d;
+L_0x2bb2500/d .functor AND 1, L_0x2bb2640, L_0x2bb23a0, C4<1>, C4<1>;
+L_0x2bb2500 .delay (20000,20000,20000) L_0x2bb2500/d;
+L_0x2bb26e0/d .functor XOR 1, L_0x2bb2f60, L_0x2bb2130, C4<0>, C4<0>;
+L_0x2bb26e0 .delay (40000,40000,40000) L_0x2bb26e0/d;
+L_0x2bb27d0/d .functor XOR 1, L_0x2bb26e0, L_0x2bb3150, C4<0>, C4<0>;
+L_0x2bb27d0 .delay (40000,40000,40000) L_0x2bb27d0/d;
+L_0x2bb28c0/d .functor AND 1, L_0x2bb2f60, L_0x2bb2130, C4<1>, C4<1>;
+L_0x2bb28c0 .delay (20000,20000,20000) L_0x2bb28c0/d;
+L_0x2bb2a30/d .functor AND 1, L_0x2bb26e0, L_0x2bb3150, C4<1>, C4<1>;
+L_0x2bb2a30 .delay (20000,20000,20000) L_0x2bb2a30/d;
+L_0x2bb2b20/d .functor OR 1, L_0x2bb28c0, L_0x2bb2a30, C4<0>, C4<0>;
+L_0x2bb2b20 .delay (20000,20000,20000) L_0x2bb2b20/d;
+v0x2716db0_0 .net "A", 0 0, L_0x2bb2f60; 1 drivers
+v0x271ba90_0 .net "AandB", 0 0, L_0x2bb28c0; 1 drivers
+v0x271bb30_0 .net "AddSubSLTSum", 0 0, L_0x2bb27d0; 1 drivers
+v0x271b7e0_0 .net "AxorB", 0 0, L_0x2bb26e0; 1 drivers
+v0x271b860_0 .net "B", 0 0, L_0x2bb2e60; 1 drivers
+v0x2719b50_0 .net "BornB", 0 0, L_0x2bb2130; 1 drivers
+v0x271e8d0_0 .net "CINandAxorB", 0 0, L_0x2bb2a30; 1 drivers
+v0x271e950_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x271e620_0 .net *"_s3", 0 0, L_0x2bb2460; 1 drivers
+v0x271e6a0_0 .net *"_s5", 0 0, L_0x2bb2640; 1 drivers
+v0x271c990_0 .net "carryin", 0 0, L_0x2bb3150; 1 drivers
+v0x271ca10_0 .net "carryout", 0 0, L_0x2bb2b20; 1 drivers
+v0x2721710_0 .net "nB", 0 0, L_0x2bb1ad0; 1 drivers
+v0x2721790_0 .net "nCmd2", 0 0, L_0x2bb23a0; 1 drivers
+v0x27214e0_0 .net "subtract", 0 0, L_0x2bb2500; 1 drivers
+L_0x2bb2300 .part v0x2960210_0, 0, 1;
+L_0x2bb2460 .part v0x2960210_0, 2, 1;
+L_0x2bb2640 .part v0x2960210_0, 0, 1;
+S_0x2715b60 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2715e10;
+ .timescale -9 -12;
+L_0x2bb1e90/d .functor NOT 1, L_0x2bb2300, C4<0>, C4<0>, C4<0>;
+L_0x2bb1e90 .delay (10000,10000,10000) L_0x2bb1e90/d;
+L_0x2bb1f10/d .functor AND 1, L_0x2bb2e60, L_0x2bb1e90, C4<1>, C4<1>;
+L_0x2bb1f10 .delay (20000,20000,20000) L_0x2bb1f10/d;
+L_0x2bb2020/d .functor AND 1, L_0x2bb1ad0, L_0x2bb2300, C4<1>, C4<1>;
+L_0x2bb2020 .delay (20000,20000,20000) L_0x2bb2020/d;
+L_0x2bb2130/d .functor OR 1, L_0x2bb1f10, L_0x2bb2020, C4<0>, C4<0>;
+L_0x2bb2130 .delay (20000,20000,20000) L_0x2bb2130/d;
+v0x2713ed0_0 .net "S", 0 0, L_0x2bb2300; 1 drivers
+v0x2713f70_0 .alias "in0", 0 0, v0x271b860_0;
+v0x2718c50_0 .alias "in1", 0 0, v0x2721710_0;
+v0x2718cf0_0 .net "nS", 0 0, L_0x2bb1e90; 1 drivers
+v0x27189a0_0 .net "out0", 0 0, L_0x2bb1f10; 1 drivers
+v0x2718a40_0 .net "out1", 0 0, L_0x2bb2020; 1 drivers
+v0x2716d10_0 .alias "outfinal", 0 0, v0x2719b50_0;
+S_0x270a820 .scope generate, "addbits[5]" "addbits[5]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x25ccbd8 .param/l "i" 3 283, +C4<0101>;
+S_0x270a5c0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x270a820;
+ .timescale -9 -12;
+L_0x2bb08d0/d .functor NOT 1, L_0x2bb4440, C4<0>, C4<0>, C4<0>;
+L_0x2bb08d0 .delay (10000,10000,10000) L_0x2bb08d0/d;
+L_0x2bb3960/d .functor NOT 1, L_0x2bb3a20, C4<0>, C4<0>, C4<0>;
+L_0x2bb3960 .delay (10000,10000,10000) L_0x2bb3960/d;
+L_0x2bb3ac0/d .functor AND 1, L_0x2bb3c00, L_0x2bb3960, C4<1>, C4<1>;
+L_0x2bb3ac0 .delay (20000,20000,20000) L_0x2bb3ac0/d;
+L_0x2bb3ca0/d .functor XOR 1, L_0x2bb4570, L_0x2bb36f0, C4<0>, C4<0>;
+L_0x2bb3ca0 .delay (40000,40000,40000) L_0x2bb3ca0/d;
+L_0x2bb3d90/d .functor XOR 1, L_0x2bb3ca0, L_0x2bb4790, C4<0>, C4<0>;
+L_0x2bb3d90 .delay (40000,40000,40000) L_0x2bb3d90/d;
+L_0x2bb3e80/d .functor AND 1, L_0x2bb4570, L_0x2bb36f0, C4<1>, C4<1>;
+L_0x2bb3e80 .delay (20000,20000,20000) L_0x2bb3e80/d;
+L_0x2bb3ff0/d .functor AND 1, L_0x2bb3ca0, L_0x2bb4790, C4<1>, C4<1>;
+L_0x2bb3ff0 .delay (20000,20000,20000) L_0x2bb3ff0/d;
+L_0x2bb4100/d .functor OR 1, L_0x2bb3e80, L_0x2bb3ff0, C4<0>, C4<0>;
+L_0x2bb4100 .delay (20000,20000,20000) L_0x2bb4100/d;
+v0x270d1b0_0 .net "A", 0 0, L_0x2bb4570; 1 drivers
+v0x270b4d0_0 .net "AandB", 0 0, L_0x2bb3e80; 1 drivers
+v0x270b570_0 .net "AddSubSLTSum", 0 0, L_0x2bb3d90; 1 drivers
+v0x2710420_0 .net "AxorB", 0 0, L_0x2bb3ca0; 1 drivers
+v0x27104a0_0 .net "B", 0 0, L_0x2bb4440; 1 drivers
+v0x27101c0_0 .net "BornB", 0 0, L_0x2bb36f0; 1 drivers
+v0x270ff10_0 .net "CINandAxorB", 0 0, L_0x2bb3ff0; 1 drivers
+v0x270ff90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x270e2d0_0 .net *"_s3", 0 0, L_0x2bb3a20; 1 drivers
+v0x270e350_0 .net *"_s5", 0 0, L_0x2bb3c00; 1 drivers
+v0x2713220_0 .net "carryin", 0 0, L_0x2bb4790; 1 drivers
+v0x27132a0_0 .net "carryout", 0 0, L_0x2bb4100; 1 drivers
+v0x2712fc0_0 .net "nB", 0 0, L_0x2bb08d0; 1 drivers
+v0x2713040_0 .net "nCmd2", 0 0, L_0x2bb3960; 1 drivers
+v0x2712d90_0 .net "subtract", 0 0, L_0x2bb3ac0; 1 drivers
+L_0x2bb38c0 .part v0x2960210_0, 0, 1;
+L_0x2bb3a20 .part v0x2960210_0, 2, 1;
+L_0x2bb3c00 .part v0x2960210_0, 0, 1;
+S_0x270a310 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x270a5c0;
+ .timescale -9 -12;
+L_0x2bb33f0/d .functor NOT 1, L_0x2bb38c0, C4<0>, C4<0>, C4<0>;
+L_0x2bb33f0 .delay (10000,10000,10000) L_0x2bb33f0/d;
+L_0x2bb34b0/d .functor AND 1, L_0x2bb4440, L_0x2bb33f0, C4<1>, C4<1>;
+L_0x2bb34b0 .delay (20000,20000,20000) L_0x2bb34b0/d;
+L_0x2bb35c0/d .functor AND 1, L_0x2bb08d0, L_0x2bb38c0, C4<1>, C4<1>;
+L_0x2bb35c0 .delay (20000,20000,20000) L_0x2bb35c0/d;
+L_0x2bb36f0/d .functor OR 1, L_0x2bb34b0, L_0x2bb35c0, C4<0>, C4<0>;
+L_0x2bb36f0 .delay (20000,20000,20000) L_0x2bb36f0/d;
+v0x27086d0_0 .net "S", 0 0, L_0x2bb38c0; 1 drivers
+v0x2708770_0 .alias "in0", 0 0, v0x27104a0_0;
+v0x270d620_0 .alias "in1", 0 0, v0x2712fc0_0;
+v0x270d6c0_0 .net "nS", 0 0, L_0x2bb33f0; 1 drivers
+v0x270d3c0_0 .net "out0", 0 0, L_0x2bb34b0; 1 drivers
+v0x270d460_0 .net "out1", 0 0, L_0x2bb35c0; 1 drivers
+v0x270d110_0 .alias "outfinal", 0 0, v0x27101c0_0;
+S_0x26fa1d0 .scope generate, "addbits[6]" "addbits[6]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2625158 .param/l "i" 3 283, +C4<0110>;
+S_0x26fef50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26fa1d0;
+ .timescale -9 -12;
+L_0x2bb4610/d .functor NOT 1, L_0x2bb5990, C4<0>, C4<0>, C4<0>;
+L_0x2bb4610 .delay (10000,10000,10000) L_0x2bb4610/d;
+L_0x2bb4e90/d .functor NOT 1, L_0x2bb4f50, C4<0>, C4<0>, C4<0>;
+L_0x2bb4e90 .delay (10000,10000,10000) L_0x2bb4e90/d;
+L_0x2bb4ff0/d .functor AND 1, L_0x2bb5130, L_0x2bb4e90, C4<1>, C4<1>;
+L_0x2bb4ff0 .delay (20000,20000,20000) L_0x2bb4ff0/d;
+L_0x2bb51d0/d .functor XOR 1, L_0x2bb5aa0, L_0x2bb4c20, C4<0>, C4<0>;
+L_0x2bb51d0 .delay (40000,40000,40000) L_0x2bb51d0/d;
+L_0x2bb52c0/d .functor XOR 1, L_0x2bb51d0, L_0x2bb5cf0, C4<0>, C4<0>;
+L_0x2bb52c0 .delay (40000,40000,40000) L_0x2bb52c0/d;
+L_0x2bb53b0/d .functor AND 1, L_0x2bb5aa0, L_0x2bb4c20, C4<1>, C4<1>;
+L_0x2bb53b0 .delay (20000,20000,20000) L_0x2bb53b0/d;
+L_0x2bb5540/d .functor AND 1, L_0x2bb51d0, L_0x2bb5cf0, C4<1>, C4<1>;
+L_0x2bb5540 .delay (20000,20000,20000) L_0x2bb5540/d;
+L_0x2bb5650/d .functor OR 1, L_0x2bb53b0, L_0x2bb5540, C4<0>, C4<0>;
+L_0x2bb5650 .delay (20000,20000,20000) L_0x2bb5650/d;
+v0x26ffef0_0 .net "A", 0 0, L_0x2bb5aa0; 1 drivers
+v0x2704c20_0 .net "AandB", 0 0, L_0x2bb53b0; 1 drivers
+v0x2704cc0_0 .net "AddSubSLTSum", 0 0, L_0x2bb52c0; 1 drivers
+v0x27049c0_0 .net "AxorB", 0 0, L_0x2bb51d0; 1 drivers
+v0x2704a60_0 .net "B", 0 0, L_0x2bb5990; 1 drivers
+v0x2704710_0 .net "BornB", 0 0, L_0x2bb4c20; 1 drivers
+v0x2702c90_0 .net "CINandAxorB", 0 0, L_0x2bb5540; 1 drivers
+v0x2702d10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2707a20_0 .net *"_s3", 0 0, L_0x2bb4f50; 1 drivers
+v0x2707aa0_0 .net *"_s5", 0 0, L_0x2bb5130; 1 drivers
+v0x27077c0_0 .net "carryin", 0 0, L_0x2bb5cf0; 1 drivers
+v0x2707860_0 .net "carryout", 0 0, L_0x2bb5650; 1 drivers
+v0x2707510_0 .net "nB", 0 0, L_0x2bb4610; 1 drivers
+v0x2707590_0 .net "nCmd2", 0 0, L_0x2bb4e90; 1 drivers
+v0x2705950_0 .net "subtract", 0 0, L_0x2bb4ff0; 1 drivers
+L_0x2bb4df0 .part v0x2960210_0, 0, 1;
+L_0x2bb4f50 .part v0x2960210_0, 2, 1;
+L_0x2bb5130 .part v0x2960210_0, 0, 1;
+S_0x26feca0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26fef50;
+ .timescale -9 -12;
+L_0x2bb4980/d .functor NOT 1, L_0x2bb4df0, C4<0>, C4<0>, C4<0>;
+L_0x2bb4980 .delay (10000,10000,10000) L_0x2bb4980/d;
+L_0x2bb4a20/d .functor AND 1, L_0x2bb5990, L_0x2bb4980, C4<1>, C4<1>;
+L_0x2bb4a20 .delay (20000,20000,20000) L_0x2bb4a20/d;
+L_0x2bb4b10/d .functor AND 1, L_0x2bb4610, L_0x2bb4df0, C4<1>, C4<1>;
+L_0x2bb4b10 .delay (20000,20000,20000) L_0x2bb4b10/d;
+L_0x2bb4c20/d .functor OR 1, L_0x2bb4a20, L_0x2bb4b10, C4<0>, C4<0>;
+L_0x2bb4c20 .delay (20000,20000,20000) L_0x2bb4c20/d;
+v0x26fd010_0 .net "S", 0 0, L_0x2bb4df0; 1 drivers
+v0x26fd0b0_0 .alias "in0", 0 0, v0x2704a60_0;
+v0x2701d90_0 .alias "in1", 0 0, v0x2707510_0;
+v0x2701e30_0 .net "nS", 0 0, L_0x2bb4980; 1 drivers
+v0x2701ae0_0 .net "out0", 0 0, L_0x2bb4a20; 1 drivers
+v0x2701b80_0 .net "out1", 0 0, L_0x2bb4b10; 1 drivers
+v0x26ffe50_0 .alias "outfinal", 0 0, v0x2704710_0;
+S_0x26f0ab0 .scope generate, "addbits[7]" "addbits[7]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x241de78 .param/l "i" 3 283, +C4<0111>;
+S_0x26f0850 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26f0ab0;
+ .timescale -9 -12;
+L_0x2bb5a30/d .functor NOT 1, L_0x2bb6ef0, C4<0>, C4<0>, C4<0>;
+L_0x2bb5a30 .delay (10000,10000,10000) L_0x2bb5a30/d;
+L_0x2bb6410/d .functor NOT 1, L_0x2bb64d0, C4<0>, C4<0>, C4<0>;
+L_0x2bb6410 .delay (10000,10000,10000) L_0x2bb6410/d;
+L_0x2bb6570/d .functor AND 1, L_0x2bb66b0, L_0x2bb6410, C4<1>, C4<1>;
+L_0x2bb6570 .delay (20000,20000,20000) L_0x2bb6570/d;
+L_0x2bb6750/d .functor XOR 1, L_0x2bb7030, L_0x2bb61a0, C4<0>, C4<0>;
+L_0x2bb6750 .delay (40000,40000,40000) L_0x2bb6750/d;
+L_0x2bb6840/d .functor XOR 1, L_0x2bb6750, L_0x2bb7220, C4<0>, C4<0>;
+L_0x2bb6840 .delay (40000,40000,40000) L_0x2bb6840/d;
+L_0x2bb6930/d .functor AND 1, L_0x2bb7030, L_0x2bb61a0, C4<1>, C4<1>;
+L_0x2bb6930 .delay (20000,20000,20000) L_0x2bb6930/d;
+L_0x2bb6aa0/d .functor AND 1, L_0x2bb6750, L_0x2bb7220, C4<1>, C4<1>;
+L_0x2bb6aa0 .delay (20000,20000,20000) L_0x2bb6aa0/d;
+L_0x2bb6bb0/d .functor OR 1, L_0x2bb6930, L_0x2bb6aa0, C4<0>, C4<0>;
+L_0x2bb6bb0 .delay (20000,20000,20000) L_0x2bb6bb0/d;
+v0x26f1800_0 .net "A", 0 0, L_0x2bb7030; 1 drivers
+v0x26f6490_0 .net "AandB", 0 0, L_0x2bb6930; 1 drivers
+v0x26f6530_0 .net "AddSubSLTSum", 0 0, L_0x2bb6840; 1 drivers
+v0x26f61e0_0 .net "AxorB", 0 0, L_0x2bb6750; 1 drivers
+v0x26f6260_0 .net "B", 0 0, L_0x2bb6ef0; 1 drivers
+v0x26f4550_0 .net "BornB", 0 0, L_0x2bb61a0; 1 drivers
+v0x26f92d0_0 .net "CINandAxorB", 0 0, L_0x2bb6aa0; 1 drivers
+v0x26f9350_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26f9020_0 .net *"_s3", 0 0, L_0x2bb64d0; 1 drivers
+v0x26f90a0_0 .net *"_s5", 0 0, L_0x2bb66b0; 1 drivers
+v0x26f7390_0 .net "carryin", 0 0, L_0x2bb7220; 1 drivers
+v0x26f7410_0 .net "carryout", 0 0, L_0x2bb6bb0; 1 drivers
+v0x26fc110_0 .net "nB", 0 0, L_0x2bb5a30; 1 drivers
+v0x26fc190_0 .net "nCmd2", 0 0, L_0x2bb6410; 1 drivers
+v0x26fbee0_0 .net "subtract", 0 0, L_0x2bb6570; 1 drivers
+L_0x2bb6370 .part v0x2960210_0, 0, 1;
+L_0x2bb64d0 .part v0x2960210_0, 2, 1;
+L_0x2bb66b0 .part v0x2960210_0, 0, 1;
+S_0x26f05a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26f0850;
+ .timescale -9 -12;
+L_0x2bb5ec0/d .functor NOT 1, L_0x2bb6370, C4<0>, C4<0>, C4<0>;
+L_0x2bb5ec0 .delay (10000,10000,10000) L_0x2bb5ec0/d;
+L_0x2bb5f60/d .functor AND 1, L_0x2bb6ef0, L_0x2bb5ec0, C4<1>, C4<1>;
+L_0x2bb5f60 .delay (20000,20000,20000) L_0x2bb5f60/d;
+L_0x2bb6070/d .functor AND 1, L_0x2bb5a30, L_0x2bb6370, C4<1>, C4<1>;
+L_0x2bb6070 .delay (20000,20000,20000) L_0x2bb6070/d;
+L_0x2bb61a0/d .functor OR 1, L_0x2bb5f60, L_0x2bb6070, C4<0>, C4<0>;
+L_0x2bb61a0 .delay (20000,20000,20000) L_0x2bb61a0/d;
+v0x26ee960_0 .net "S", 0 0, L_0x2bb6370; 1 drivers
+v0x26eea00_0 .alias "in0", 0 0, v0x26f6260_0;
+v0x26f3650_0 .alias "in1", 0 0, v0x26fc110_0;
+v0x26f36f0_0 .net "nS", 0 0, L_0x2bb5ec0; 1 drivers
+v0x26f33a0_0 .net "out0", 0 0, L_0x2bb5f60; 1 drivers
+v0x26f3440_0 .net "out1", 0 0, L_0x2bb6070; 1 drivers
+v0x26f1760_0 .alias "outfinal", 0 0, v0x26f4550_0;
+S_0x26e52b0 .scope generate, "addbits[8]" "addbits[8]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x238d208 .param/l "i" 3 283, +C4<01000>;
+S_0x26e5050 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26e52b0;
+ .timescale -9 -12;
+L_0x2bb70d0/d .functor NOT 1, L_0x2bb8430, C4<0>, C4<0>, C4<0>;
+L_0x2bb70d0 .delay (10000,10000,10000) L_0x2bb70d0/d;
+L_0x2bb7950/d .functor NOT 1, L_0x2bb7a10, C4<0>, C4<0>, C4<0>;
+L_0x2bb7950 .delay (10000,10000,10000) L_0x2bb7950/d;
+L_0x2bb7ab0/d .functor AND 1, L_0x2bb7bf0, L_0x2bb7950, C4<1>, C4<1>;
+L_0x2bb7ab0 .delay (20000,20000,20000) L_0x2bb7ab0/d;
+L_0x2bb7c90/d .functor XOR 1, L_0x2bb85a0, L_0x2bb76e0, C4<0>, C4<0>;
+L_0x2bb7c90 .delay (40000,40000,40000) L_0x2bb7c90/d;
+L_0x2bb7d80/d .functor XOR 1, L_0x2bb7c90, L_0x2bb87c0, C4<0>, C4<0>;
+L_0x2bb7d80 .delay (40000,40000,40000) L_0x2bb7d80/d;
+L_0x2bb7e70/d .functor AND 1, L_0x2bb85a0, L_0x2bb76e0, C4<1>, C4<1>;
+L_0x2bb7e70 .delay (20000,20000,20000) L_0x2bb7e70/d;
+L_0x2bb7fe0/d .functor AND 1, L_0x2bb7c90, L_0x2bb87c0, C4<1>, C4<1>;
+L_0x2bb7fe0 .delay (20000,20000,20000) L_0x2bb7fe0/d;
+L_0x2bb80f0/d .functor OR 1, L_0x2bb7e70, L_0x2bb7fe0, C4<0>, C4<0>;
+L_0x2bb80f0 .delay (20000,20000,20000) L_0x2bb80f0/d;
+v0x26e6000_0 .net "A", 0 0, L_0x2bb85a0; 1 drivers
+v0x26eaeb0_0 .net "AandB", 0 0, L_0x2bb7e70; 1 drivers
+v0x26eaf50_0 .net "AddSubSLTSum", 0 0, L_0x2bb7d80; 1 drivers
+v0x26eac50_0 .net "AxorB", 0 0, L_0x2bb7c90; 1 drivers
+v0x26eacf0_0 .net "B", 0 0, L_0x2bb8430; 1 drivers
+v0x26ea9a0_0 .net "BornB", 0 0, L_0x2bb76e0; 1 drivers
+v0x26e8d60_0 .net "CINandAxorB", 0 0, L_0x2bb7fe0; 1 drivers
+v0x26e8de0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26edcb0_0 .net *"_s3", 0 0, L_0x2bb7a10; 1 drivers
+v0x26edd30_0 .net *"_s5", 0 0, L_0x2bb7bf0; 1 drivers
+v0x26eda50_0 .net "carryin", 0 0, L_0x2bb87c0; 1 drivers
+v0x26edaf0_0 .net "carryout", 0 0, L_0x2bb80f0; 1 drivers
+v0x26ed7a0_0 .net "nB", 0 0, L_0x2bb70d0; 1 drivers
+v0x26ed820_0 .net "nCmd2", 0 0, L_0x2bb7950; 1 drivers
+v0x26ebbe0_0 .net "subtract", 0 0, L_0x2bb7ab0; 1 drivers
+L_0x2bb78b0 .part v0x2960210_0, 0, 1;
+L_0x2bb7a10 .part v0x2960210_0, 2, 1;
+L_0x2bb7bf0 .part v0x2960210_0, 0, 1;
+S_0x26e4da0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26e5050;
+ .timescale -9 -12;
+L_0x2bb7420/d .functor NOT 1, L_0x2bb78b0, C4<0>, C4<0>, C4<0>;
+L_0x2bb7420 .delay (10000,10000,10000) L_0x2bb7420/d;
+L_0x2bb74c0/d .functor AND 1, L_0x2bb8430, L_0x2bb7420, C4<1>, C4<1>;
+L_0x2bb74c0 .delay (20000,20000,20000) L_0x2bb74c0/d;
+L_0x2bb75d0/d .functor AND 1, L_0x2bb70d0, L_0x2bb78b0, C4<1>, C4<1>;
+L_0x2bb75d0 .delay (20000,20000,20000) L_0x2bb75d0/d;
+L_0x2bb76e0/d .functor OR 1, L_0x2bb74c0, L_0x2bb75d0, C4<0>, C4<0>;
+L_0x2bb76e0 .delay (20000,20000,20000) L_0x2bb76e0/d;
+v0x26e80b0_0 .net "S", 0 0, L_0x2bb78b0; 1 drivers
+v0x26e8150_0 .alias "in0", 0 0, v0x26eacf0_0;
+v0x26e7e50_0 .alias "in1", 0 0, v0x26ed7a0_0;
+v0x26e7ef0_0 .net "nS", 0 0, L_0x2bb7420; 1 drivers
+v0x26e7ba0_0 .net "out0", 0 0, L_0x2bb74c0; 1 drivers
+v0x26e7c40_0 .net "out1", 0 0, L_0x2bb75d0; 1 drivers
+v0x26e5f60_0 .alias "outfinal", 0 0, v0x26ea9a0_0;
+S_0x270f4f0 .scope generate, "addbits[9]" "addbits[9]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x23c67f8 .param/l "i" 3 283, +C4<01001>;
+S_0x270cc70 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x270f4f0;
+ .timescale -9 -12;
+L_0x2bb73b0/d .functor NOT 1, L_0x2bb9c30, C4<0>, C4<0>, C4<0>;
+L_0x2bb73b0 .delay (10000,10000,10000) L_0x2bb73b0/d;
+L_0x2bb8fa0/d .functor NOT 1, L_0x2bb9060, C4<0>, C4<0>, C4<0>;
+L_0x2bb8fa0 .delay (10000,10000,10000) L_0x2bb8fa0/d;
+L_0x2bb9100/d .functor AND 1, L_0x2bb9240, L_0x2bb8fa0, C4<1>, C4<1>;
+L_0x2bb9100 .delay (20000,20000,20000) L_0x2bb9100/d;
+L_0x2bb92e0/d .functor XOR 1, L_0x2bb8b60, L_0x2bb8d30, C4<0>, C4<0>;
+L_0x2bb92e0 .delay (40000,40000,40000) L_0x2bb92e0/d;
+L_0x2bb93d0/d .functor XOR 1, L_0x2bb92e0, L_0x2bb9d60, C4<0>, C4<0>;
+L_0x2bb93d0 .delay (40000,40000,40000) L_0x2bb93d0/d;
+L_0x2bb94c0/d .functor AND 1, L_0x2bb8b60, L_0x2bb8d30, C4<1>, C4<1>;
+L_0x2bb94c0 .delay (20000,20000,20000) L_0x2bb94c0/d;
+L_0x2bb9630/d .functor AND 1, L_0x2bb92e0, L_0x2bb9d60, C4<1>, C4<1>;
+L_0x2bb9630 .delay (20000,20000,20000) L_0x2bb9630/d;
+L_0x2bb9740/d .functor OR 1, L_0x2bb94c0, L_0x2bb9630, C4<0>, C4<0>;
+L_0x2bb9740 .delay (20000,20000,20000) L_0x2bb9740/d;
+v0x2707110_0 .net "A", 0 0, L_0x2bb8b60; 1 drivers
+v0x2706af0_0 .net "AandB", 0 0, L_0x2bb94c0; 1 drivers
+v0x2706b90_0 .net "AddSubSLTSum", 0 0, L_0x2bb93d0; 1 drivers
+v0x2704270_0 .net "AxorB", 0 0, L_0x2bb92e0; 1 drivers
+v0x27042f0_0 .net "B", 0 0, L_0x2bb9c30; 1 drivers
+v0x2704010_0 .net "BornB", 0 0, L_0x2bb8d30; 1 drivers
+v0x2703cd0_0 .net "CINandAxorB", 0 0, L_0x2bb9630; 1 drivers
+v0x2703d50_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2701610_0 .net *"_s3", 0 0, L_0x2bb9060; 1 drivers
+v0x2701690_0 .net *"_s5", 0 0, L_0x2bb9240; 1 drivers
+v0x27394d0_0 .net "carryin", 0 0, L_0x2bb9d60; 1 drivers
+v0x2739550_0 .net "carryout", 0 0, L_0x2bb9740; 1 drivers
+v0x26e2070_0 .net "nB", 0 0, L_0x2bb73b0; 1 drivers
+v0x26e20f0_0 .net "nCmd2", 0 0, L_0x2bb8fa0; 1 drivers
+v0x26e03a0_0 .net "subtract", 0 0, L_0x2bb9100; 1 drivers
+L_0x2bb8f00 .part v0x2960210_0, 0, 1;
+L_0x2bb9060 .part v0x2960210_0, 2, 1;
+L_0x2bb9240 .part v0x2960210_0, 0, 1;
+S_0x270c6f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x270cc70;
+ .timescale -9 -12;
+L_0x2bb8640/d .functor NOT 1, L_0x2bb8f00, C4<0>, C4<0>, C4<0>;
+L_0x2bb8640 .delay (10000,10000,10000) L_0x2bb8640/d;
+L_0x2bb8700/d .functor AND 1, L_0x2bb9c30, L_0x2bb8640, C4<1>, C4<1>;
+L_0x2bb8700 .delay (20000,20000,20000) L_0x2bb8700/d;
+L_0x2bb8c00/d .functor AND 1, L_0x2bb73b0, L_0x2bb8f00, C4<1>, C4<1>;
+L_0x2bb8c00 .delay (20000,20000,20000) L_0x2bb8c00/d;
+L_0x2bb8d30/d .functor OR 1, L_0x2bb8700, L_0x2bb8c00, C4<0>, C4<0>;
+L_0x2bb8d30 .delay (20000,20000,20000) L_0x2bb8d30/d;
+v0x2709e70_0 .net "S", 0 0, L_0x2bb8f00; 1 drivers
+v0x2709f10_0 .alias "in0", 0 0, v0x27042f0_0;
+v0x26e4900_0 .alias "in1", 0 0, v0x26e2070_0;
+v0x26e49a0_0 .net "nS", 0 0, L_0x2bb8640; 1 drivers
+v0x27098f0_0 .net "out0", 0 0, L_0x2bb8700; 1 drivers
+v0x2709990_0 .net "out1", 0 0, L_0x2bb8c00; 1 drivers
+v0x2707070_0 .alias "outfinal", 0 0, v0x2704010_0;
+S_0x272c070 .scope generate, "addbits[10]" "addbits[10]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x24068e8 .param/l "i" 3 283, +C4<01010>;
+S_0x27297f0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x272c070;
+ .timescale -9 -12;
+L_0x2bb9a80/d .functor NOT 1, L_0x2bbb1b0, C4<0>, C4<0>, C4<0>;
+L_0x2bb9a80 .delay (10000,10000,10000) L_0x2bb9a80/d;
+L_0x2bba4f0/d .functor NOT 1, L_0x2bba5b0, C4<0>, C4<0>, C4<0>;
+L_0x2bba4f0 .delay (10000,10000,10000) L_0x2bba4f0/d;
+L_0x2bba650/d .functor AND 1, L_0x2bba790, L_0x2bba4f0, C4<1>, C4<1>;
+L_0x2bba650 .delay (20000,20000,20000) L_0x2bba650/d;
+L_0x2bba830/d .functor XOR 1, L_0x2bb9ef0, L_0x2bba280, C4<0>, C4<0>;
+L_0x2bba830 .delay (40000,40000,40000) L_0x2bba830/d;
+L_0x2bba920/d .functor XOR 1, L_0x2bba830, L_0x2bbb2e0, C4<0>, C4<0>;
+L_0x2bba920 .delay (40000,40000,40000) L_0x2bba920/d;
+L_0x2bbaa10/d .functor AND 1, L_0x2bb9ef0, L_0x2bba280, C4<1>, C4<1>;
+L_0x2bbaa10 .delay (20000,20000,20000) L_0x2bbaa10/d;
+L_0x2bbab80/d .functor AND 1, L_0x2bba830, L_0x2bbb2e0, C4<1>, C4<1>;
+L_0x2bbab80 .delay (20000,20000,20000) L_0x2bbab80/d;
+L_0x2bbac90/d .functor OR 1, L_0x2bbaa10, L_0x2bbab80, C4<0>, C4<0>;
+L_0x2bbac90 .delay (20000,20000,20000) L_0x2bbac90/d;
+v0x2721030_0 .net "A", 0 0, L_0x2bb9ef0; 1 drivers
+v0x271e150_0 .net "AandB", 0 0, L_0x2bbaa10; 1 drivers
+v0x271e1f0_0 .net "AddSubSLTSum", 0 0, L_0x2bba920; 1 drivers
+v0x271b310_0 .net "AxorB", 0 0, L_0x2bba830; 1 drivers
+v0x271b3b0_0 .net "B", 0 0, L_0x2bbb1b0; 1 drivers
+v0x26e7180_0 .net "BornB", 0 0, L_0x2bba280; 1 drivers
+v0x27184d0_0 .net "CINandAxorB", 0 0, L_0x2bbab80; 1 drivers
+v0x2718550_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2715690_0 .net *"_s3", 0 0, L_0x2bba5b0; 1 drivers
+v0x2715710_0 .net *"_s5", 0 0, L_0x2bba790; 1 drivers
+v0x2712870_0 .net "carryin", 0 0, L_0x2bbb2e0; 1 drivers
+v0x2712910_0 .net "carryout", 0 0, L_0x2bbac90; 1 drivers
+v0x27122f0_0 .net "nB", 0 0, L_0x2bb9a80; 1 drivers
+v0x2712370_0 .net "nCmd2", 0 0, L_0x2bba4f0; 1 drivers
+v0x270faf0_0 .net "subtract", 0 0, L_0x2bba650; 1 drivers
+L_0x2bba450 .part v0x2960210_0, 0, 1;
+L_0x2bba5b0 .part v0x2960210_0, 2, 1;
+L_0x2bba790 .part v0x2960210_0, 0, 1;
+S_0x2729270 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x27297f0;
+ .timescale -9 -12;
+L_0x2bb9fc0/d .functor NOT 1, L_0x2bba450, C4<0>, C4<0>, C4<0>;
+L_0x2bb9fc0 .delay (10000,10000,10000) L_0x2bb9fc0/d;
+L_0x2bba060/d .functor AND 1, L_0x2bbb1b0, L_0x2bb9fc0, C4<1>, C4<1>;
+L_0x2bba060 .delay (20000,20000,20000) L_0x2bba060/d;
+L_0x2bba150/d .functor AND 1, L_0x2bb9a80, L_0x2bba450, C4<1>, C4<1>;
+L_0x2bba150 .delay (20000,20000,20000) L_0x2bba150/d;
+L_0x2bba280/d .functor OR 1, L_0x2bba060, L_0x2bba150, C4<0>, C4<0>;
+L_0x2bba280 .delay (20000,20000,20000) L_0x2bba280/d;
+v0x27269f0_0 .net "S", 0 0, L_0x2bba450; 1 drivers
+v0x2726a90_0 .alias "in0", 0 0, v0x271b3b0_0;
+v0x26e7700_0 .alias "in1", 0 0, v0x27122f0_0;
+v0x26e77a0_0 .net "nS", 0 0, L_0x2bb9fc0; 1 drivers
+v0x2726470_0 .net "out0", 0 0, L_0x2bba060; 1 drivers
+v0x2726510_0 .net "out1", 0 0, L_0x2bba150; 1 drivers
+v0x2720f90_0 .alias "outfinal", 0 0, v0x26e7180_0;
+S_0x26e1ba0 .scope generate, "addbits[11]" "addbits[11]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2210ba8 .param/l "i" 3 283, +C4<01011>;
+S_0x26ecd80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26e1ba0;
+ .timescale -9 -12;
+L_0x2bbafd0/d .functor NOT 1, L_0x2bbc6f0, C4<0>, C4<0>, C4<0>;
+L_0x2bbafd0 .delay (10000,10000,10000) L_0x2bbafd0/d;
+L_0x2bbba20/d .functor NOT 1, L_0x2bbbae0, C4<0>, C4<0>, C4<0>;
+L_0x2bbba20 .delay (10000,10000,10000) L_0x2bbba20/d;
+L_0x2bbbb80/d .functor AND 1, L_0x2bbbcc0, L_0x2bbba20, C4<1>, C4<1>;
+L_0x2bbbb80 .delay (20000,20000,20000) L_0x2bbbb80/d;
+L_0x2bbbd60/d .functor XOR 1, L_0x2bbb470, L_0x2bbb7b0, C4<0>, C4<0>;
+L_0x2bbbd60 .delay (40000,40000,40000) L_0x2bbbd60/d;
+L_0x2bbbe50/d .functor XOR 1, L_0x2bbbd60, L_0x2bbc820, C4<0>, C4<0>;
+L_0x2bbbe50 .delay (40000,40000,40000) L_0x2bbbe50/d;
+L_0x2bbbf40/d .functor AND 1, L_0x2bbb470, L_0x2bbb7b0, C4<1>, C4<1>;
+L_0x2bbbf40 .delay (20000,20000,20000) L_0x2bbbf40/d;
+L_0x2bbc0b0/d .functor AND 1, L_0x2bbbd60, L_0x2bbc820, C4<1>, C4<1>;
+L_0x2bbc0b0 .delay (20000,20000,20000) L_0x2bbc0b0/d;
+L_0x2bbc1a0/d .functor OR 1, L_0x2bbbf40, L_0x2bbc0b0, C4<0>, C4<0>;
+L_0x2bbc1a0 .delay (20000,20000,20000) L_0x2bbc1a0/d;
+v0x273ac90_0 .net "A", 0 0, L_0x2bbb470; 1 drivers
+v0x2737e50_0 .net "AandB", 0 0, L_0x2bbbf40; 1 drivers
+v0x2737ef0_0 .net "AddSubSLTSum", 0 0, L_0x2bbbe50; 1 drivers
+v0x26e9f80_0 .net "AxorB", 0 0, L_0x2bbbd60; 1 drivers
+v0x26ea000_0 .net "B", 0 0, L_0x2bbc6f0; 1 drivers
+v0x2735010_0 .net "BornB", 0 0, L_0x2bbb7b0; 1 drivers
+v0x27321f0_0 .net "CINandAxorB", 0 0, L_0x2bbc0b0; 1 drivers
+v0x2732270_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2731c70_0 .net *"_s3", 0 0, L_0x2bbbae0; 1 drivers
+v0x2731cf0_0 .net *"_s5", 0 0, L_0x2bbbcc0; 1 drivers
+v0x272f3f0_0 .net "carryin", 0 0, L_0x2bbc820; 1 drivers
+v0x272f470_0 .net "carryout", 0 0, L_0x2bbc1a0; 1 drivers
+v0x272ee70_0 .net "nB", 0 0, L_0x2bbafd0; 1 drivers
+v0x272eef0_0 .net "nCmd2", 0 0, L_0x2bbba20; 1 drivers
+v0x272c670_0 .net "subtract", 0 0, L_0x2bbbb80; 1 drivers
+L_0x2bbb980 .part v0x2960210_0, 0, 1;
+L_0x2bbbae0 .part v0x2960210_0, 2, 1;
+L_0x2bbbcc0 .part v0x2960210_0, 0, 1;
+S_0x26ea500 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26ecd80;
+ .timescale -9 -12;
+L_0x2bbb130/d .functor NOT 1, L_0x2bbb980, C4<0>, C4<0>, C4<0>;
+L_0x2bbb130 .delay (10000,10000,10000) L_0x2bbb130/d;
+L_0x2bbb5b0/d .functor AND 1, L_0x2bbc6f0, L_0x2bbb130, C4<1>, C4<1>;
+L_0x2bbb5b0 .delay (20000,20000,20000) L_0x2bbb5b0/d;
+L_0x2bbb6a0/d .functor AND 1, L_0x2bbafd0, L_0x2bbb980, C4<1>, C4<1>;
+L_0x2bbb6a0 .delay (20000,20000,20000) L_0x2bbb6a0/d;
+L_0x2bbb7b0/d .functor OR 1, L_0x2bbb5b0, L_0x2bbb6a0, C4<0>, C4<0>;
+L_0x2bbb7b0 .delay (20000,20000,20000) L_0x2bbb7b0/d;
+v0x26ed380_0 .net "S", 0 0, L_0x2bbb980; 1 drivers
+v0x273b660_0 .alias "in0", 0 0, v0x26ea000_0;
+v0x273b700_0 .alias "in1", 0 0, v0x272ee70_0;
+v0x273b3f0_0 .net "nS", 0 0, L_0x2bbb130; 1 drivers
+v0x273b470_0 .net "out0", 0 0, L_0x2bbb5b0; 1 drivers
+v0x273b150_0 .net "out1", 0 0, L_0x2bbb6a0; 1 drivers
+v0x273b1f0_0 .alias "outfinal", 0 0, v0x2735010_0;
+S_0x26d8330 .scope generate, "addbits[12]" "addbits[12]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2253de8 .param/l "i" 3 283, +C4<01100>;
+S_0x26d8080 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26d8330;
+ .timescale -9 -12;
+L_0x2bbb510/d .functor NOT 1, L_0x2bbdbf0, C4<0>, C4<0>, C4<0>;
+L_0x2bbb510 .delay (10000,10000,10000) L_0x2bbb510/d;
+L_0x2bbcef0/d .functor NOT 1, L_0x2bbcfb0, C4<0>, C4<0>, C4<0>;
+L_0x2bbcef0 .delay (10000,10000,10000) L_0x2bbcef0/d;
+L_0x2bbd050/d .functor AND 1, L_0x2bbd190, L_0x2bbcef0, C4<1>, C4<1>;
+L_0x2bbd050 .delay (20000,20000,20000) L_0x2bbd050/d;
+L_0x2bbd230/d .functor XOR 1, L_0x2bbc9b0, L_0x2bbcc80, C4<0>, C4<0>;
+L_0x2bbd230 .delay (40000,40000,40000) L_0x2bbd230/d;
+L_0x2bbd320/d .functor XOR 1, L_0x2bbd230, L_0x2bbdc90, C4<0>, C4<0>;
+L_0x2bbd320 .delay (40000,40000,40000) L_0x2bbd320/d;
+L_0x2bbd410/d .functor AND 1, L_0x2bbc9b0, L_0x2bbcc80, C4<1>, C4<1>;
+L_0x2bbd410 .delay (20000,20000,20000) L_0x2bbd410/d;
+L_0x2bbd580/d .functor AND 1, L_0x2bbd230, L_0x2bbdc90, C4<1>, C4<1>;
+L_0x2bbd580 .delay (20000,20000,20000) L_0x2bbd580/d;
+L_0x2bbd670/d .functor OR 1, L_0x2bbd410, L_0x2bbd580, C4<0>, C4<0>;
+L_0x2bbd670 .delay (20000,20000,20000) L_0x2bbd670/d;
+v0x26e4380_0 .net "A", 0 0, L_0x2bbc9b0; 1 drivers
+v0x26fb990_0 .net "AandB", 0 0, L_0x2bbd410; 1 drivers
+v0x26fba30_0 .net "AddSubSLTSum", 0 0, L_0x2bbd320; 1 drivers
+v0x26f8b50_0 .net "AxorB", 0 0, L_0x2bbd230; 1 drivers
+v0x26f8bd0_0 .net "B", 0 0, L_0x2bbdbf0; 1 drivers
+v0x26f5d10_0 .net "BornB", 0 0, L_0x2bbcc80; 1 drivers
+v0x26f5d90_0 .net "CINandAxorB", 0 0, L_0x2bbd580; 1 drivers
+v0x26f2f00_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26f2f80_0 .net *"_s3", 0 0, L_0x2bbcfb0; 1 drivers
+v0x26f2980_0 .net *"_s5", 0 0, L_0x2bbd190; 1 drivers
+v0x26f2a00_0 .net "carryin", 0 0, L_0x2bbdc90; 1 drivers
+v0x26f0100_0 .net "carryout", 0 0, L_0x2bbd670; 1 drivers
+v0x26f0180_0 .net "nB", 0 0, L_0x2bbb510; 1 drivers
+v0x26efb80_0 .net "nCmd2", 0 0, L_0x2bbcef0; 1 drivers
+v0x26ed300_0 .net "subtract", 0 0, L_0x2bbd050; 1 drivers
+L_0x2bbce50 .part v0x2960210_0, 0, 1;
+L_0x2bbcfb0 .part v0x2960210_0, 2, 1;
+L_0x2bbd190 .part v0x2960210_0, 0, 1;
+S_0x26d6260 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26d8080;
+ .timescale -9 -12;
+L_0x2bbc5e0/d .functor NOT 1, L_0x2bbce50, C4<0>, C4<0>, C4<0>;
+L_0x2bbc5e0 .delay (10000,10000,10000) L_0x2bbc5e0/d;
+L_0x2bbc660/d .functor AND 1, L_0x2bbdbf0, L_0x2bbc5e0, C4<1>, C4<1>;
+L_0x2bbc660 .delay (20000,20000,20000) L_0x2bbc660/d;
+L_0x2bbcb70/d .functor AND 1, L_0x2bbb510, L_0x2bbce50, C4<1>, C4<1>;
+L_0x2bbcb70 .delay (20000,20000,20000) L_0x2bbcb70/d;
+L_0x2bbcc80/d .functor OR 1, L_0x2bbc660, L_0x2bbcb70, C4<0>, C4<0>;
+L_0x2bbcc80 .delay (20000,20000,20000) L_0x2bbcc80/d;
+v0x26cf720_0 .net "S", 0 0, L_0x2bbce50; 1 drivers
+v0x26d5fb0_0 .alias "in0", 0 0, v0x26f8bd0_0;
+v0x26d6050_0 .alias "in1", 0 0, v0x26f0180_0;
+v0x26d4320_0 .net "nS", 0 0, L_0x2bbc5e0; 1 drivers
+v0x26d43a0_0 .net "out0", 0 0, L_0x2bbc660; 1 drivers
+v0x26fe7d0_0 .net "out1", 0 0, L_0x2bbcb70; 1 drivers
+v0x26fe870_0 .alias "outfinal", 0 0, v0x26f5d10_0;
+S_0x26c7cb0 .scope generate, "addbits[13]" "addbits[13]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2237d68 .param/l "i" 3 283, +C4<01101>;
+S_0x26c7a00 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26c7cb0;
+ .timescale -9 -12;
+L_0x2bbd9b0/d .functor NOT 1, L_0x2bbdec0, C4<0>, C4<0>, C4<0>;
+L_0x2bbd9b0 .delay (10000,10000,10000) L_0x2bbd9b0/d;
+L_0x2bbe3b0/d .functor NOT 1, L_0x2bbe470, C4<0>, C4<0>, C4<0>;
+L_0x2bbe3b0 .delay (10000,10000,10000) L_0x2bbe3b0/d;
+L_0x2bbe510/d .functor AND 1, L_0x2bbe650, L_0x2bbe3b0, C4<1>, C4<1>;
+L_0x2bbe510 .delay (20000,20000,20000) L_0x2bbe510/d;
+L_0x2bbe6f0/d .functor XOR 1, L_0x2bbde20, L_0x2bbe140, C4<0>, C4<0>;
+L_0x2bbe6f0 .delay (40000,40000,40000) L_0x2bbe6f0/d;
+L_0x2bbe7e0/d .functor XOR 1, L_0x2bbe6f0, L_0x2bbf170, C4<0>, C4<0>;
+L_0x2bbe7e0 .delay (40000,40000,40000) L_0x2bbe7e0/d;
+L_0x2bbe8d0/d .functor AND 1, L_0x2bbde20, L_0x2bbe140, C4<1>, C4<1>;
+L_0x2bbe8d0 .delay (20000,20000,20000) L_0x2bbe8d0/d;
+L_0x2bbea40/d .functor AND 1, L_0x2bbe6f0, L_0x2bbf170, C4<1>, C4<1>;
+L_0x2bbea40 .delay (20000,20000,20000) L_0x2bbea40/d;
+L_0x2bbeb30/d .functor OR 1, L_0x2bbe8d0, L_0x2bbea40, C4<0>, C4<0>;
+L_0x2bbeb30 .delay (20000,20000,20000) L_0x2bbeb30/d;
+v0x26cc920_0 .net "A", 0 0, L_0x2bbde20; 1 drivers
+v0x26cc670_0 .net "AandB", 0 0, L_0x2bbe8d0; 1 drivers
+v0x26cc710_0 .net "AddSubSLTSum", 0 0, L_0x2bbe7e0; 1 drivers
+v0x26caa30_0 .net "AxorB", 0 0, L_0x2bbe6f0; 1 drivers
+v0x26caab0_0 .net "B", 0 0, L_0x2bbdec0; 1 drivers
+v0x26d3680_0 .net "BornB", 0 0, L_0x2bbe140; 1 drivers
+v0x26d3700_0 .net "CINandAxorB", 0 0, L_0x2bbea40; 1 drivers
+v0x26d33d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26d3450_0 .net *"_s3", 0 0, L_0x2bbe470; 1 drivers
+v0x26d17f0_0 .net *"_s5", 0 0, L_0x2bbe650; 1 drivers
+v0x26d1870_0 .net "carryin", 0 0, L_0x2bbf170; 1 drivers
+v0x26d1590_0 .net "carryout", 0 0, L_0x2bbeb30; 1 drivers
+v0x26d1610_0 .net "nB", 0 0, L_0x2bbd9b0; 1 drivers
+v0x26d12e0_0 .net "nCmd2", 0 0, L_0x2bbe3b0; 1 drivers
+v0x26cf6a0_0 .net "subtract", 0 0, L_0x2bbe510; 1 drivers
+L_0x2bbe310 .part v0x2960210_0, 0, 1;
+L_0x2bbe470 .part v0x2960210_0, 2, 1;
+L_0x2bbe650 .part v0x2960210_0, 0, 1;
+S_0x26c5dc0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26c7a00;
+ .timescale -9 -12;
+L_0x2bbdb10/d .functor NOT 1, L_0x2bbe310, C4<0>, C4<0>, C4<0>;
+L_0x2bbdb10 .delay (10000,10000,10000) L_0x2bbdb10/d;
+L_0x2bbdb90/d .functor AND 1, L_0x2bbdec0, L_0x2bbdb10, C4<1>, C4<1>;
+L_0x2bbdb90 .delay (20000,20000,20000) L_0x2bbdb90/d;
+L_0x2bbe030/d .functor AND 1, L_0x2bbd9b0, L_0x2bbe310, C4<1>, C4<1>;
+L_0x2bbe030 .delay (20000,20000,20000) L_0x2bbe030/d;
+L_0x2bbe140/d .functor OR 1, L_0x2bbdb90, L_0x2bbe030, C4<0>, C4<0>;
+L_0x2bbe140 .delay (20000,20000,20000) L_0x2bbe140/d;
+v0x26c7f90_0 .net "S", 0 0, L_0x2bbe310; 1 drivers
+v0x26cea00_0 .alias "in0", 0 0, v0x26caab0_0;
+v0x26ceaa0_0 .alias "in1", 0 0, v0x26d1610_0;
+v0x26ce750_0 .net "nS", 0 0, L_0x2bbdb10; 1 drivers
+v0x26ce7d0_0 .net "out0", 0 0, L_0x2bbdb90; 1 drivers
+v0x26ccb80_0 .net "out1", 0 0, L_0x2bbe030; 1 drivers
+v0x26ccc20_0 .alias "outfinal", 0 0, v0x26d3680_0;
+S_0x26b9570 .scope generate, "addbits[14]" "addbits[14]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22062e8 .param/l "i" 3 283, +C4<01110>;
+S_0x26b78e0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26b9570;
+ .timescale -9 -12;
+L_0x2bbee70/d .functor NOT 1, L_0x2bbf3a0, C4<0>, C4<0>, C4<0>;
+L_0x2bbee70 .delay (10000,10000,10000) L_0x2bbee70/d;
+L_0x2bbf880/d .functor NOT 1, L_0x2bbf940, C4<0>, C4<0>, C4<0>;
+L_0x2bbf880 .delay (10000,10000,10000) L_0x2bbf880/d;
+L_0x2bbf9e0/d .functor AND 1, L_0x2bbfb20, L_0x2bbf880, C4<1>, C4<1>;
+L_0x2bbf9e0 .delay (20000,20000,20000) L_0x2bbf9e0/d;
+L_0x2bbfbc0/d .functor XOR 1, L_0x2bbf300, L_0x2bbf610, C4<0>, C4<0>;
+L_0x2bbfbc0 .delay (40000,40000,40000) L_0x2bbfbc0/d;
+L_0x2bbfcb0/d .functor XOR 1, L_0x2bbfbc0, L_0x2bc0670, C4<0>, C4<0>;
+L_0x2bbfcb0 .delay (40000,40000,40000) L_0x2bbfcb0/d;
+L_0x2bbfda0/d .functor AND 1, L_0x2bbf300, L_0x2bbf610, C4<1>, C4<1>;
+L_0x2bbfda0 .delay (20000,20000,20000) L_0x2bbfda0/d;
+L_0x2bbff10/d .functor AND 1, L_0x2bbfbc0, L_0x2bc0670, C4<1>, C4<1>;
+L_0x2bbff10 .delay (20000,20000,20000) L_0x2bbff10/d;
+L_0x2bc0000/d .functor OR 1, L_0x2bbfda0, L_0x2bbff10, C4<0>, C4<0>;
+L_0x2bc0000 .delay (20000,20000,20000) L_0x2bc0000/d;
+v0x26bc590_0 .net "A", 0 0, L_0x2bbf300; 1 drivers
+v0x26c5120_0 .net "AandB", 0 0, L_0x2bbfda0; 1 drivers
+v0x26c51c0_0 .net "AddSubSLTSum", 0 0, L_0x2bbfcb0; 1 drivers
+v0x26c4e70_0 .net "AxorB", 0 0, L_0x2bbfbc0; 1 drivers
+v0x26c4ef0_0 .net "B", 0 0, L_0x2bbf3a0; 1 drivers
+v0x26c3290_0 .net "BornB", 0 0, L_0x2bbf610; 1 drivers
+v0x26c3310_0 .net "CINandAxorB", 0 0, L_0x2bbff10; 1 drivers
+v0x26c3030_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26c30b0_0 .net *"_s3", 0 0, L_0x2bbf940; 1 drivers
+v0x26c1240_0 .net *"_s5", 0 0, L_0x2bbfb20; 1 drivers
+v0x26c12c0_0 .net "carryin", 0 0, L_0x2bc0670; 1 drivers
+v0x26c9d90_0 .net "carryout", 0 0, L_0x2bc0000; 1 drivers
+v0x26c9e10_0 .net "nB", 0 0, L_0x2bbee70; 1 drivers
+v0x26c9ae0_0 .net "nCmd2", 0 0, L_0x2bbf880; 1 drivers
+v0x26c7f10_0 .net "subtract", 0 0, L_0x2bbf9e0; 1 drivers
+L_0x2bbf7e0 .part v0x2960210_0, 0, 1;
+L_0x2bbf940 .part v0x2960210_0, 2, 1;
+L_0x2bbfb20 .part v0x2960210_0, 0, 1;
+S_0x26c05a0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26b78e0;
+ .timescale -9 -12;
+L_0x2bbefb0/d .functor NOT 1, L_0x2bbf7e0, C4<0>, C4<0>, C4<0>;
+L_0x2bbefb0 .delay (10000,10000,10000) L_0x2bbefb0/d;
+L_0x2bbf030/d .functor AND 1, L_0x2bbf3a0, L_0x2bbefb0, C4<1>, C4<1>;
+L_0x2bbf030 .delay (20000,20000,20000) L_0x2bbf030/d;
+L_0x2bbf520/d .functor AND 1, L_0x2bbee70, L_0x2bbf7e0, C4<1>, C4<1>;
+L_0x2bbf520 .delay (20000,20000,20000) L_0x2bbf520/d;
+L_0x2bbf610/d .functor OR 1, L_0x2bbf030, L_0x2bbf520, C4<0>, C4<0>;
+L_0x2bbf610 .delay (20000,20000,20000) L_0x2bbf610/d;
+v0x26b98a0_0 .net "S", 0 0, L_0x2bbf7e0; 1 drivers
+v0x26c02f0_0 .alias "in0", 0 0, v0x26c4ef0_0;
+v0x26c0390_0 .alias "in1", 0 0, v0x26c9e10_0;
+v0x26be4d0_0 .net "nS", 0 0, L_0x2bbefb0; 1 drivers
+v0x26be550_0 .net "out0", 0 0, L_0x2bbf030; 1 drivers
+v0x26be220_0 .net "out1", 0 0, L_0x2bbf520; 1 drivers
+v0x26be2c0_0 .alias "outfinal", 0 0, v0x26c3290_0;
+S_0x26a9350 .scope generate, "addbits[15]" "addbits[15]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22117c8 .param/l "i" 3 283, +C4<01111>;
+S_0x26b1f90 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26a9350;
+ .timescale -9 -12;
+L_0x2bc0340/d .functor NOT 1, L_0x2bc08a0, C4<0>, C4<0>, C4<0>;
+L_0x2bc0340 .delay (10000,10000,10000) L_0x2bc0340/d;
+L_0x2bc0d40/d .functor NOT 1, L_0x2bc0e00, C4<0>, C4<0>, C4<0>;
+L_0x2bc0d40 .delay (10000,10000,10000) L_0x2bc0d40/d;
+L_0x2bc0ea0/d .functor AND 1, L_0x2bc0fe0, L_0x2bc0d40, C4<1>, C4<1>;
+L_0x2bc0ea0 .delay (20000,20000,20000) L_0x2bc0ea0/d;
+L_0x2bc1080/d .functor XOR 1, L_0x2bc0800, L_0x2bc0ad0, C4<0>, C4<0>;
+L_0x2bc1080 .delay (40000,40000,40000) L_0x2bc1080/d;
+L_0x2bc1170/d .functor XOR 1, L_0x2bc1080, L_0x2bc1b60, C4<0>, C4<0>;
+L_0x2bc1170 .delay (40000,40000,40000) L_0x2bc1170/d;
+L_0x2bc1260/d .functor AND 1, L_0x2bc0800, L_0x2bc0ad0, C4<1>, C4<1>;
+L_0x2bc1260 .delay (20000,20000,20000) L_0x2bc1260/d;
+L_0x2bc13d0/d .functor AND 1, L_0x2bc1080, L_0x2bc1b60, C4<1>, C4<1>;
+L_0x2bc13d0 .delay (20000,20000,20000) L_0x2bc13d0/d;
+L_0x2bc14c0/d .functor OR 1, L_0x2bc1260, L_0x2bc13d0, C4<0>, C4<0>;
+L_0x2bc14c0 .delay (20000,20000,20000) L_0x2bc14c0/d;
+v0x26adfc0_0 .net "A", 0 0, L_0x2bc0800; 1 drivers
+v0x26b6c40_0 .net "AandB", 0 0, L_0x2bc1260; 1 drivers
+v0x26b6ce0_0 .net "AddSubSLTSum", 0 0, L_0x2bc1170; 1 drivers
+v0x26b6990_0 .net "AxorB", 0 0, L_0x2bc1080; 1 drivers
+v0x26b6a10_0 .net "B", 0 0, L_0x2bc08a0; 1 drivers
+v0x26b4b70_0 .net "BornB", 0 0, L_0x2bc0ad0; 1 drivers
+v0x26b4bf0_0 .net "CINandAxorB", 0 0, L_0x2bc13d0; 1 drivers
+v0x26b48c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26b4940_0 .net *"_s3", 0 0, L_0x2bc0e00; 1 drivers
+v0x26b2c30_0 .net *"_s5", 0 0, L_0x2bc0fe0; 1 drivers
+v0x26b2cb0_0 .net "carryin", 0 0, L_0x2bc1b60; 1 drivers
+v0x26bb8f0_0 .net "carryout", 0 0, L_0x2bc14c0; 1 drivers
+v0x26bb970_0 .net "nB", 0 0, L_0x2bc0340; 1 drivers
+v0x26bb640_0 .net "nCmd2", 0 0, L_0x2bc0d40; 1 drivers
+v0x26b9820_0 .net "subtract", 0 0, L_0x2bc0ea0; 1 drivers
+L_0x2bc0ca0 .part v0x2960210_0, 0, 1;
+L_0x2bc0e00 .part v0x2960210_0, 2, 1;
+L_0x2bc0fe0 .part v0x2960210_0, 0, 1;
+S_0x26b1ce0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26b1f90;
+ .timescale -9 -12;
+L_0x2bc0450/d .functor NOT 1, L_0x2bc0ca0, C4<0>, C4<0>, C4<0>;
+L_0x2bc0450 .delay (10000,10000,10000) L_0x2bc0450/d;
+L_0x2bc04d0/d .functor AND 1, L_0x2bc08a0, L_0x2bc0450, C4<1>, C4<1>;
+L_0x2bc04d0 .delay (20000,20000,20000) L_0x2bc04d0/d;
+L_0x2bc09c0/d .functor AND 1, L_0x2bc0340, L_0x2bc0ca0, C4<1>, C4<1>;
+L_0x2bc09c0 .delay (20000,20000,20000) L_0x2bc09c0/d;
+L_0x2bc0ad0/d .functor OR 1, L_0x2bc04d0, L_0x2bc09c0, C4<0>, C4<0>;
+L_0x2bc0ad0 .delay (20000,20000,20000) L_0x2bc0ad0/d;
+v0x26ab010_0 .net "S", 0 0, L_0x2bc0ca0; 1 drivers
+v0x26b0110_0 .alias "in0", 0 0, v0x26b6a10_0;
+v0x26b01b0_0 .alias "in1", 0 0, v0x26bb970_0;
+v0x26afeb0_0 .net "nS", 0 0, L_0x2bc0450; 1 drivers
+v0x26aff30_0 .net "out0", 0 0, L_0x2bc04d0; 1 drivers
+v0x26afc00_0 .net "out1", 0 0, L_0x2bc09c0; 1 drivers
+v0x26afca0_0 .alias "outfinal", 0 0, v0x26b4b70_0;
+S_0x26a3790 .scope generate, "addbits[16]" "addbits[16]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x221c538 .param/l "i" 3 283, +C4<010000>;
+S_0x26a1a80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26a3790;
+ .timescale -9 -12;
+L_0x2bc0940/d .functor NOT 1, L_0x2bc1d90, C4<0>, C4<0>, C4<0>;
+L_0x2bc0940 .delay (10000,10000,10000) L_0x2bc0940/d;
+L_0x2bc2200/d .functor NOT 1, L_0x2bc22c0, C4<0>, C4<0>, C4<0>;
+L_0x2bc2200 .delay (10000,10000,10000) L_0x2bc2200/d;
+L_0x2bc2360/d .functor AND 1, L_0x2bc24a0, L_0x2bc2200, C4<1>, C4<1>;
+L_0x2bc2360 .delay (20000,20000,20000) L_0x2bc2360/d;
+L_0x2bc2540/d .functor XOR 1, L_0x2bc1cf0, L_0x2bc1f90, C4<0>, C4<0>;
+L_0x2bc2540 .delay (40000,40000,40000) L_0x2bc2540/d;
+L_0x2bc2630/d .functor XOR 1, L_0x2bc2540, L_0x2bc2fc0, C4<0>, C4<0>;
+L_0x2bc2630 .delay (40000,40000,40000) L_0x2bc2630/d;
+L_0x2bc2720/d .functor AND 1, L_0x2bc1cf0, L_0x2bc1f90, C4<1>, C4<1>;
+L_0x2bc2720 .delay (20000,20000,20000) L_0x2bc2720/d;
+L_0x2bc2890/d .functor AND 1, L_0x2bc2540, L_0x2bc2fc0, C4<1>, C4<1>;
+L_0x2bc2890 .delay (20000,20000,20000) L_0x2bc2890/d;
+L_0x2bc2980/d .functor OR 1, L_0x2bc2720, L_0x2bc2890, C4<0>, C4<0>;
+L_0x2bc2980 .delay (20000,20000,20000) L_0x2bc2980/d;
+v0x26a6830_0 .net "A", 0 0, L_0x2bc1cf0; 1 drivers
+v0x26a65d0_0 .net "AandB", 0 0, L_0x2bc2720; 1 drivers
+v0x26a6670_0 .net "AddSubSLTSum", 0 0, L_0x2bc2630; 1 drivers
+v0x26a6320_0 .net "AxorB", 0 0, L_0x2bc2540; 1 drivers
+v0x26a63a0_0 .net "B", 0 0, L_0x2bc1d90; 1 drivers
+v0x26a46e0_0 .net "BornB", 0 0, L_0x2bc1f90; 1 drivers
+v0x26a4760_0 .net "CINandAxorB", 0 0, L_0x2bc2890; 1 drivers
+v0x26ad320_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26ad3a0_0 .net *"_s3", 0 0, L_0x2bc22c0; 1 drivers
+v0x26ad070_0 .net *"_s5", 0 0, L_0x2bc24a0; 1 drivers
+v0x26ad0f0_0 .net "carryin", 0 0, L_0x2bc2fc0; 1 drivers
+v0x26ab4a0_0 .net "carryout", 0 0, L_0x2bc2980; 1 drivers
+v0x26ab520_0 .net "nB", 0 0, L_0x2bc0940; 1 drivers
+v0x26ab240_0 .net "nCmd2", 0 0, L_0x2bc2200; 1 drivers
+v0x26aaf90_0 .net "subtract", 0 0, L_0x2bc2360; 1 drivers
+L_0x2bc2160 .part v0x2960210_0, 0, 1;
+L_0x2bc22c0 .part v0x2960210_0, 2, 1;
+L_0x2bc24a0 .part v0x2960210_0, 0, 1;
+S_0x26a17d0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26a1a80;
+ .timescale -9 -12;
+L_0x2bc18e0/d .functor NOT 1, L_0x2bc2160, C4<0>, C4<0>, C4<0>;
+L_0x2bc18e0 .delay (10000,10000,10000) L_0x2bc18e0/d;
+L_0x2bc1960/d .functor AND 1, L_0x2bc1d90, L_0x2bc18e0, C4<1>, C4<1>;
+L_0x2bc1960 .delay (20000,20000,20000) L_0x2bc1960/d;
+L_0x2bc1a70/d .functor AND 1, L_0x2bc0940, L_0x2bc2160, C4<1>, C4<1>;
+L_0x2bc1a70 .delay (20000,20000,20000) L_0x2bc1a70/d;
+L_0x2bc1f90/d .functor OR 1, L_0x2bc1960, L_0x2bc1a70, C4<0>, C4<0>;
+L_0x2bc1f90 .delay (20000,20000,20000) L_0x2bc1f90/d;
+v0x26a3ac0_0 .net "S", 0 0, L_0x2bc2160; 1 drivers
+v0x269fb40_0 .alias "in0", 0 0, v0x26a63a0_0;
+v0x269fbe0_0 .alias "in1", 0 0, v0x26ab520_0;
+v0x26a86b0_0 .net "nS", 0 0, L_0x2bc18e0; 1 drivers
+v0x26a8730_0 .net "out0", 0 0, L_0x2bc1960; 1 drivers
+v0x26a8400_0 .net "out1", 0 0, L_0x2bc1a70; 1 drivers
+v0x26a84a0_0 .alias "outfinal", 0 0, v0x26a46e0_0;
+S_0x2695290 .scope generate, "addbits[17]" "addbits[17]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2224c98 .param/l "i" 3 283, +C4<010001>;
+S_0x2693470 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2695290;
+ .timescale -9 -12;
+L_0x2bb0960/d .functor NOT 1, L_0x2bc3600, C4<0>, C4<0>, C4<0>;
+L_0x2bb0960 .delay (10000,10000,10000) L_0x2bb0960/d;
+L_0x2bc3820/d .functor NOT 1, L_0x2bc38c0, C4<0>, C4<0>, C4<0>;
+L_0x2bc3820 .delay (10000,10000,10000) L_0x2bc3820/d;
+L_0x2bc3960/d .functor AND 1, L_0x2bc3aa0, L_0x2bc3820, C4<1>, C4<1>;
+L_0x2bc3960 .delay (20000,20000,20000) L_0x2bc3960/d;
+L_0x2bc3b40/d .functor XOR 1, L_0x2bc3560, L_0x2bc2de0, C4<0>, C4<0>;
+L_0x2bc3b40 .delay (40000,40000,40000) L_0x2bc3b40/d;
+L_0x2bc3c30/d .functor XOR 1, L_0x2bc3b40, L_0x2bc45d0, C4<0>, C4<0>;
+L_0x2bc3c30 .delay (40000,40000,40000) L_0x2bc3c30/d;
+L_0x2bc3d20/d .functor AND 1, L_0x2bc3560, L_0x2bc2de0, C4<1>, C4<1>;
+L_0x2bc3d20 .delay (20000,20000,20000) L_0x2bc3d20/d;
+L_0x2bc3e90/d .functor AND 1, L_0x2bc3b40, L_0x2bc45d0, C4<1>, C4<1>;
+L_0x2bc3e90 .delay (20000,20000,20000) L_0x2bc3e90/d;
+L_0x2bc3f80/d .functor OR 1, L_0x2bc3d20, L_0x2bc3e90, C4<0>, C4<0>;
+L_0x2bc3f80 .delay (20000,20000,20000) L_0x2bc3f80/d;
+v0x2698120_0 .net "A", 0 0, L_0x2bc3560; 1 drivers
+v0x2697e70_0 .net "AandB", 0 0, L_0x2bc3d20; 1 drivers
+v0x2697f10_0 .net "AddSubSLTSum", 0 0, L_0x2bc3c30; 1 drivers
+v0x26961e0_0 .net "AxorB", 0 0, L_0x2bc3b40; 1 drivers
+v0x2696260_0 .net "B", 0 0, L_0x2bc3600; 1 drivers
+v0x269eea0_0 .net "BornB", 0 0, L_0x2bc2de0; 1 drivers
+v0x269ef20_0 .net "CINandAxorB", 0 0, L_0x2bc3e90; 1 drivers
+v0x269ebf0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x269ec70_0 .net *"_s3", 0 0, L_0x2bc38c0; 1 drivers
+v0x269cdd0_0 .net *"_s5", 0 0, L_0x2bc3aa0; 1 drivers
+v0x269ce50_0 .net "carryin", 0 0, L_0x2bc45d0; 1 drivers
+v0x269cb20_0 .net "carryout", 0 0, L_0x2bc3f80; 1 drivers
+v0x269cba0_0 .net "nB", 0 0, L_0x2bb0960; 1 drivers
+v0x269ae90_0 .net "nCmd2", 0 0, L_0x2bc3820; 1 drivers
+v0x26a3a40_0 .net "subtract", 0 0, L_0x2bc3960; 1 drivers
+L_0x2bc3780 .part v0x2960210_0, 0, 1;
+L_0x2bc38c0 .part v0x2960210_0, 2, 1;
+L_0x2bc3aa0 .part v0x2960210_0, 0, 1;
+S_0x26931c0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2693470;
+ .timescale -9 -12;
+L_0x2bb88f0/d .functor NOT 1, L_0x2bc3780, C4<0>, C4<0>, C4<0>;
+L_0x2bb88f0 .delay (10000,10000,10000) L_0x2bb88f0/d;
+L_0x2bb8970/d .functor AND 1, L_0x2bc3600, L_0x2bb88f0, C4<1>, C4<1>;
+L_0x2bb8970 .delay (20000,20000,20000) L_0x2bb8970/d;
+L_0x2bc2d10/d .functor AND 1, L_0x2bb0960, L_0x2bc3780, C4<1>, C4<1>;
+L_0x2bc2d10 .delay (20000,20000,20000) L_0x2bc2d10/d;
+L_0x2bc2de0/d .functor OR 1, L_0x2bb8970, L_0x2bc2d10, C4<0>, C4<0>;
+L_0x2bc2de0 .delay (20000,20000,20000) L_0x2bc2de0/d;
+v0x26955c0_0 .net "S", 0 0, L_0x2bc3780; 1 drivers
+v0x2691580_0 .alias "in0", 0 0, v0x2696260_0;
+v0x2691620_0 .alias "in1", 0 0, v0x269cba0_0;
+v0x269a1f0_0 .net "nS", 0 0, L_0x2bb88f0; 1 drivers
+v0x269a270_0 .net "out0", 0 0, L_0x2bb8970; 1 drivers
+v0x2699f40_0 .net "out1", 0 0, L_0x2bc2d10; 1 drivers
+v0x2699fe0_0 .alias "outfinal", 0 0, v0x269eea0_0;
+S_0x2684c70 .scope generate, "addbits[18]" "addbits[18]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2230468 .param/l "i" 3 283, +C4<010010>;
+S_0x2683030 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2684c70;
+ .timescale -9 -12;
+L_0x2bc42a0/d .functor NOT 1, L_0x2bc4800, C4<0>, C4<0>, C4<0>;
+L_0x2bc42a0 .delay (10000,10000,10000) L_0x2bc42a0/d;
+L_0x2bc4c70/d .functor NOT 1, L_0x2bc4d10, C4<0>, C4<0>, C4<0>;
+L_0x2bc4c70 .delay (10000,10000,10000) L_0x2bc4c70/d;
+L_0x2bc4db0/d .functor AND 1, L_0x2bc4ef0, L_0x2bc4c70, C4<1>, C4<1>;
+L_0x2bc4db0 .delay (20000,20000,20000) L_0x2bc4db0/d;
+L_0x2bc4f90/d .functor XOR 1, L_0x2bc4760, L_0x2bc4a40, C4<0>, C4<0>;
+L_0x2bc4f90 .delay (40000,40000,40000) L_0x2bc4f90/d;
+L_0x2bc5040/d .functor XOR 1, L_0x2bc4f90, L_0x2bc5a10, C4<0>, C4<0>;
+L_0x2bc5040 .delay (40000,40000,40000) L_0x2bc5040/d;
+L_0x2bc5130/d .functor AND 1, L_0x2bc4760, L_0x2bc4a40, C4<1>, C4<1>;
+L_0x2bc5130 .delay (20000,20000,20000) L_0x2bc5130/d;
+L_0x2bc52a0/d .functor AND 1, L_0x2bc4f90, L_0x2bc5a10, C4<1>, C4<1>;
+L_0x2bc52a0 .delay (20000,20000,20000) L_0x2bc52a0/d;
+L_0x2bc5390/d .functor OR 1, L_0x2bc5130, L_0x2bc52a0, C4<0>, C4<0>;
+L_0x2bc5390 .delay (20000,20000,20000) L_0x2bc5390/d;
+v0x26898e0_0 .net "A", 0 0, L_0x2bc4760; 1 drivers
+v0x2687ca0_0 .net "AandB", 0 0, L_0x2bc5130; 1 drivers
+v0x2687d40_0 .net "AddSubSLTSum", 0 0, L_0x2bc5040; 1 drivers
+v0x26908e0_0 .net "AxorB", 0 0, L_0x2bc4f90; 1 drivers
+v0x2690960_0 .net "B", 0 0, L_0x2bc4800; 1 drivers
+v0x2690630_0 .net "BornB", 0 0, L_0x2bc4a40; 1 drivers
+v0x26906b0_0 .net "CINandAxorB", 0 0, L_0x2bc52a0; 1 drivers
+v0x268ea60_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x268eae0_0 .net *"_s3", 0 0, L_0x2bc4d10; 1 drivers
+v0x268e800_0 .net *"_s5", 0 0, L_0x2bc4ef0; 1 drivers
+v0x268e880_0 .net "carryin", 0 0, L_0x2bc5a10; 1 drivers
+v0x268e550_0 .net "carryout", 0 0, L_0x2bc5390; 1 drivers
+v0x268e5d0_0 .net "nB", 0 0, L_0x2bc42a0; 1 drivers
+v0x268c910_0 .net "nCmd2", 0 0, L_0x2bc4c70; 1 drivers
+v0x2695540_0 .net "subtract", 0 0, L_0x2bc4db0; 1 drivers
+L_0x2bc4bd0 .part v0x2960210_0, 0, 1;
+L_0x2bc4d10 .part v0x2960210_0, 2, 1;
+L_0x2bc4ef0 .part v0x2960210_0, 0, 1;
+S_0x268bc70 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2683030;
+ .timescale -9 -12;
+L_0x2bc43b0/d .functor NOT 1, L_0x2bc4bd0, C4<0>, C4<0>, C4<0>;
+L_0x2bc43b0 .delay (10000,10000,10000) L_0x2bc43b0/d;
+L_0x2bc4430/d .functor AND 1, L_0x2bc4800, L_0x2bc43b0, C4<1>, C4<1>;
+L_0x2bc4430 .delay (20000,20000,20000) L_0x2bc4430/d;
+L_0x2bc4540/d .functor AND 1, L_0x2bc42a0, L_0x2bc4bd0, C4<1>, C4<1>;
+L_0x2bc4540 .delay (20000,20000,20000) L_0x2bc4540/d;
+L_0x2bc4a40/d .functor OR 1, L_0x2bc4430, L_0x2bc4540, C4<0>, C4<0>;
+L_0x2bc4a40 .delay (20000,20000,20000) L_0x2bc4a40/d;
+v0x2684fa0_0 .net "S", 0 0, L_0x2bc4bd0; 1 drivers
+v0x268b9c0_0 .alias "in0", 0 0, v0x2690960_0;
+v0x268ba60_0 .alias "in1", 0 0, v0x268e5d0_0;
+v0x2689df0_0 .net "nS", 0 0, L_0x2bc43b0; 1 drivers
+v0x2689e70_0 .net "out0", 0 0, L_0x2bc4430; 1 drivers
+v0x2689b90_0 .net "out1", 0 0, L_0x2bc4540; 1 drivers
+v0x2689c30_0 .alias "outfinal", 0 0, v0x2690630_0;
+S_0x26767d0 .scope generate, "addbits[19]" "addbits[19]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x223b158 .param/l "i" 3 283, +C4<010011>;
+S_0x2674b40 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26767d0;
+ .timescale -9 -12;
+L_0x2bc4930/d .functor NOT 1, L_0x2bc5c40, C4<0>, C4<0>, C4<0>;
+L_0x2bc4930 .delay (10000,10000,10000) L_0x2bc4930/d;
+L_0x2bc60a0/d .functor NOT 1, L_0x2bc6140, C4<0>, C4<0>, C4<0>;
+L_0x2bc60a0 .delay (10000,10000,10000) L_0x2bc60a0/d;
+L_0x2bc61e0/d .functor AND 1, L_0x2bc6320, L_0x2bc60a0, C4<1>, C4<1>;
+L_0x2bc61e0 .delay (20000,20000,20000) L_0x2bc61e0/d;
+L_0x2bc63c0/d .functor XOR 1, L_0x2bc5ba0, L_0x2bc5e70, C4<0>, C4<0>;
+L_0x2bc63c0 .delay (40000,40000,40000) L_0x2bc63c0/d;
+L_0x2bc64b0/d .functor XOR 1, L_0x2bc63c0, L_0x2bc5d70, C4<0>, C4<0>;
+L_0x2bc64b0 .delay (40000,40000,40000) L_0x2bc64b0/d;
+L_0x2bc65a0/d .functor AND 1, L_0x2bc5ba0, L_0x2bc5e70, C4<1>, C4<1>;
+L_0x2bc65a0 .delay (20000,20000,20000) L_0x2bc65a0/d;
+L_0x2bc6710/d .functor AND 1, L_0x2bc63c0, L_0x2bc5d70, C4<1>, C4<1>;
+L_0x2bc6710 .delay (20000,20000,20000) L_0x2bc6710/d;
+L_0x2bc6800/d .functor OR 1, L_0x2bc65a0, L_0x2bc6710, C4<0>, C4<0>;
+L_0x2bc6800 .delay (20000,20000,20000) L_0x2bc6800/d;
+v0x26797f0_0 .net "A", 0 0, L_0x2bc5ba0; 1 drivers
+v0x2682390_0 .net "AandB", 0 0, L_0x2bc65a0; 1 drivers
+v0x2682430_0 .net "AddSubSLTSum", 0 0, L_0x2bc64b0; 1 drivers
+v0x26803e0_0 .net "AxorB", 0 0, L_0x2bc63c0; 1 drivers
+v0x2680460_0 .net "B", 0 0, L_0x2bc5c40; 1 drivers
+v0x2680130_0 .net "BornB", 0 0, L_0x2bc5e70; 1 drivers
+v0x26801b0_0 .net "CINandAxorB", 0 0, L_0x2bc6710; 1 drivers
+v0x267e4a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x267e520_0 .net *"_s3", 0 0, L_0x2bc6140; 1 drivers
+v0x2687000_0 .net *"_s5", 0 0, L_0x2bc6320; 1 drivers
+v0x2687080_0 .net "carryin", 0 0, L_0x2bc5d70; 1 drivers
+v0x2686d50_0 .net "carryout", 0 0, L_0x2bc6800; 1 drivers
+v0x2686dd0_0 .net "nB", 0 0, L_0x2bc4930; 1 drivers
+v0x2685180_0 .net "nCmd2", 0 0, L_0x2bc60a0; 1 drivers
+v0x2684f20_0 .net "subtract", 0 0, L_0x2bc61e0; 1 drivers
+L_0x2bc6000 .part v0x2960210_0, 0, 1;
+L_0x2bc6140 .part v0x2960210_0, 2, 1;
+L_0x2bc6320 .part v0x2960210_0, 0, 1;
+S_0x267d800 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2674b40;
+ .timescale -9 -12;
+L_0x2bc5790/d .functor NOT 1, L_0x2bc6000, C4<0>, C4<0>, C4<0>;
+L_0x2bc5790 .delay (10000,10000,10000) L_0x2bc5790/d;
+L_0x2bc5810/d .functor AND 1, L_0x2bc5c40, L_0x2bc5790, C4<1>, C4<1>;
+L_0x2bc5810 .delay (20000,20000,20000) L_0x2bc5810/d;
+L_0x2bc5920/d .functor AND 1, L_0x2bc4930, L_0x2bc6000, C4<1>, C4<1>;
+L_0x2bc5920 .delay (20000,20000,20000) L_0x2bc5920/d;
+L_0x2bc5e70/d .functor OR 1, L_0x2bc5810, L_0x2bc5920, C4<0>, C4<0>;
+L_0x2bc5e70 .delay (20000,20000,20000) L_0x2bc5e70/d;
+v0x2676b00_0 .net "S", 0 0, L_0x2bc6000; 1 drivers
+v0x267d550_0 .alias "in0", 0 0, v0x2680460_0;
+v0x267d5f0_0 .alias "in1", 0 0, v0x2686dd0_0;
+v0x267b730_0 .net "nS", 0 0, L_0x2bc5790; 1 drivers
+v0x267b7b0_0 .net "out0", 0 0, L_0x2bc5810; 1 drivers
+v0x267b480_0 .net "out1", 0 0, L_0x2bc5920; 1 drivers
+v0x267b520_0 .alias "outfinal", 0 0, v0x2680130_0;
+S_0x2666600 .scope generate, "addbits[20]" "addbits[20]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22438b8 .param/l "i" 3 283, +C4<010100>;
+S_0x266f240 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2666600;
+ .timescale -9 -12;
+L_0x2bc6ec0/d .functor NOT 1, L_0x2bc6cb0, C4<0>, C4<0>, C4<0>;
+L_0x2bc6ec0 .delay (10000,10000,10000) L_0x2bc6ec0/d;
+L_0x2bc7430/d .functor NOT 1, L_0x2bc74d0, C4<0>, C4<0>, C4<0>;
+L_0x2bc7430 .delay (10000,10000,10000) L_0x2bc7430/d;
+L_0x2bc7570/d .functor AND 1, L_0x2bc76b0, L_0x2bc7430, C4<1>, C4<1>;
+L_0x2bc7570 .delay (20000,20000,20000) L_0x2bc7570/d;
+L_0x2bc7750/d .functor XOR 1, L_0x2bc6c10, L_0x2bc7200, C4<0>, C4<0>;
+L_0x2bc7750 .delay (40000,40000,40000) L_0x2bc7750/d;
+L_0x2bc7840/d .functor XOR 1, L_0x2bc7750, L_0x2bc6de0, C4<0>, C4<0>;
+L_0x2bc7840 .delay (40000,40000,40000) L_0x2bc7840/d;
+L_0x2bc7930/d .functor AND 1, L_0x2bc6c10, L_0x2bc7200, C4<1>, C4<1>;
+L_0x2bc7930 .delay (20000,20000,20000) L_0x2bc7930/d;
+L_0x2bc7aa0/d .functor AND 1, L_0x2bc7750, L_0x2bc6de0, C4<1>, C4<1>;
+L_0x2bc7aa0 .delay (20000,20000,20000) L_0x2bc7aa0/d;
+L_0x2bc7b90/d .functor OR 1, L_0x2bc7930, L_0x2bc7aa0, C4<0>, C4<0>;
+L_0x2bc7b90 .delay (20000,20000,20000) L_0x2bc7b90/d;
+v0x266b270_0 .net "A", 0 0, L_0x2bc6c10; 1 drivers
+v0x2673ea0_0 .net "AandB", 0 0, L_0x2bc7930; 1 drivers
+v0x2673f40_0 .net "AddSubSLTSum", 0 0, L_0x2bc7840; 1 drivers
+v0x2673bf0_0 .net "AxorB", 0 0, L_0x2bc7750; 1 drivers
+v0x2673c70_0 .net "B", 0 0, L_0x2bc6cb0; 1 drivers
+v0x2671dd0_0 .net "BornB", 0 0, L_0x2bc7200; 1 drivers
+v0x2671e50_0 .net "CINandAxorB", 0 0, L_0x2bc7aa0; 1 drivers
+v0x2671b20_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2671ba0_0 .net *"_s3", 0 0, L_0x2bc74d0; 1 drivers
+v0x266fee0_0 .net *"_s5", 0 0, L_0x2bc76b0; 1 drivers
+v0x266ff60_0 .net "carryin", 0 0, L_0x2bc6de0; 1 drivers
+v0x2678b50_0 .net "carryout", 0 0, L_0x2bc7b90; 1 drivers
+v0x2678bd0_0 .net "nB", 0 0, L_0x2bc6ec0; 1 drivers
+v0x26788a0_0 .net "nCmd2", 0 0, L_0x2bc7430; 1 drivers
+v0x2676a80_0 .net "subtract", 0 0, L_0x2bc7570; 1 drivers
+L_0x2bc7390 .part v0x2960210_0, 0, 1;
+L_0x2bc74d0 .part v0x2960210_0, 2, 1;
+L_0x2bc76b0 .part v0x2960210_0, 0, 1;
+S_0x266ef90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x266f240;
+ .timescale -9 -12;
+L_0x2bc6fc0/d .functor NOT 1, L_0x2bc7390, C4<0>, C4<0>, C4<0>;
+L_0x2bc6fc0 .delay (10000,10000,10000) L_0x2bc6fc0/d;
+L_0x2bc7020/d .functor AND 1, L_0x2bc6cb0, L_0x2bc6fc0, C4<1>, C4<1>;
+L_0x2bc7020 .delay (20000,20000,20000) L_0x2bc7020/d;
+L_0x2bc7110/d .functor AND 1, L_0x2bc6ec0, L_0x2bc7390, C4<1>, C4<1>;
+L_0x2bc7110 .delay (20000,20000,20000) L_0x2bc7110/d;
+L_0x2bc7200/d .functor OR 1, L_0x2bc7020, L_0x2bc7110, C4<0>, C4<0>;
+L_0x2bc7200 .delay (20000,20000,20000) L_0x2bc7200/d;
+v0x26682c0_0 .net "S", 0 0, L_0x2bc7390; 1 drivers
+v0x266d3c0_0 .alias "in0", 0 0, v0x2673c70_0;
+v0x266d460_0 .alias "in1", 0 0, v0x2678bd0_0;
+v0x266d160_0 .net "nS", 0 0, L_0x2bc6fc0; 1 drivers
+v0x266d1e0_0 .net "out0", 0 0, L_0x2bc7020; 1 drivers
+v0x266ceb0_0 .net "out1", 0 0, L_0x2bc7110; 1 drivers
+v0x266cf50_0 .alias "outfinal", 0 0, v0x2671dd0_0;
+S_0x2660db0 .scope generate, "addbits[21]" "addbits[21]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x224c4e8 .param/l "i" 3 283, +C4<010101>;
+S_0x2660b00 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2660db0;
+ .timescale -9 -12;
+L_0x2bc8280/d .functor NOT 1, L_0x2bc8040, C4<0>, C4<0>, C4<0>;
+L_0x2bc8280 .delay (10000,10000,10000) L_0x2bc8280/d;
+L_0x2bc87b0/d .functor NOT 1, L_0x2bc8850, C4<0>, C4<0>, C4<0>;
+L_0x2bc87b0 .delay (10000,10000,10000) L_0x2bc87b0/d;
+L_0x2bc88f0/d .functor AND 1, L_0x2bc8a30, L_0x2bc87b0, C4<1>, C4<1>;
+L_0x2bc88f0 .delay (20000,20000,20000) L_0x2bc88f0/d;
+L_0x2bc8ad0/d .functor XOR 1, L_0x2bc7fa0, L_0x2bc8580, C4<0>, C4<0>;
+L_0x2bc8ad0 .delay (40000,40000,40000) L_0x2bc8ad0/d;
+L_0x2bc8bc0/d .functor XOR 1, L_0x2bc8ad0, L_0x2bc8170, C4<0>, C4<0>;
+L_0x2bc8bc0 .delay (40000,40000,40000) L_0x2bc8bc0/d;
+L_0x2bc8cb0/d .functor AND 1, L_0x2bc7fa0, L_0x2bc8580, C4<1>, C4<1>;
+L_0x2bc8cb0 .delay (20000,20000,20000) L_0x2bc8cb0/d;
+L_0x2bc8e20/d .functor AND 1, L_0x2bc8ad0, L_0x2bc8170, C4<1>, C4<1>;
+L_0x2bc8e20 .delay (20000,20000,20000) L_0x2bc8e20/d;
+L_0x2bc8f10/d .functor OR 1, L_0x2bc8cb0, L_0x2bc8e20, C4<0>, C4<0>;
+L_0x2bc8f10 .delay (20000,20000,20000) L_0x2bc8f10/d;
+v0x26656b0_0 .net "A", 0 0, L_0x2bc7fa0; 1 drivers
+v0x2663ad0_0 .net "AandB", 0 0, L_0x2bc8cb0; 1 drivers
+v0x2663b70_0 .net "AddSubSLTSum", 0 0, L_0x2bc8bc0; 1 drivers
+v0x2663870_0 .net "AxorB", 0 0, L_0x2bc8ad0; 1 drivers
+v0x26638f0_0 .net "B", 0 0, L_0x2bc8040; 1 drivers
+v0x2661a50_0 .net "BornB", 0 0, L_0x2bc8580; 1 drivers
+v0x2661ad0_0 .net "CINandAxorB", 0 0, L_0x2bc8e20; 1 drivers
+v0x266a5d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x266a650_0 .net *"_s3", 0 0, L_0x2bc8850; 1 drivers
+v0x266a320_0 .net *"_s5", 0 0, L_0x2bc8a30; 1 drivers
+v0x266a3a0_0 .net "carryin", 0 0, L_0x2bc8170; 1 drivers
+v0x2668750_0 .net "carryout", 0 0, L_0x2bc8f10; 1 drivers
+v0x26687d0_0 .net "nB", 0 0, L_0x2bc8280; 1 drivers
+v0x26684f0_0 .net "nCmd2", 0 0, L_0x2bc87b0; 1 drivers
+v0x2668240_0 .net "subtract", 0 0, L_0x2bc88f0; 1 drivers
+L_0x2bc8710 .part v0x2960210_0, 0, 1;
+L_0x2bc8850 .part v0x2960210_0, 2, 1;
+L_0x2bc8a30 .part v0x2960210_0, 0, 1;
+S_0x265ece0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2660b00;
+ .timescale -9 -12;
+L_0x2bc8380/d .functor NOT 1, L_0x2bc8710, C4<0>, C4<0>, C4<0>;
+L_0x2bc8380 .delay (10000,10000,10000) L_0x2bc8380/d;
+L_0x2bc83e0/d .functor AND 1, L_0x2bc8040, L_0x2bc8380, C4<1>, C4<1>;
+L_0x2bc83e0 .delay (20000,20000,20000) L_0x2bc83e0/d;
+L_0x2bc8490/d .functor AND 1, L_0x2bc8280, L_0x2bc8710, C4<1>, C4<1>;
+L_0x2bc8490 .delay (20000,20000,20000) L_0x2bc8490/d;
+L_0x2bc8580/d .functor OR 1, L_0x2bc83e0, L_0x2bc8490, C4<0>, C4<0>;
+L_0x2bc8580 .delay (20000,20000,20000) L_0x2bc8580/d;
+v0x2658170_0 .net "S", 0 0, L_0x2bc8710; 1 drivers
+v0x265ea30_0 .alias "in0", 0 0, v0x26638f0_0;
+v0x265ead0_0 .alias "in1", 0 0, v0x26687d0_0;
+v0x265cda0_0 .net "nS", 0 0, L_0x2bc8380; 1 drivers
+v0x265ce20_0 .net "out0", 0 0, L_0x2bc83e0; 1 drivers
+v0x2665960_0 .net "out1", 0 0, L_0x2bc8490; 1 drivers
+v0x2665a00_0 .alias "outfinal", 0 0, v0x2661a50_0;
+S_0x26524f0 .scope generate, "addbits[22]" "addbits[22]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2279168 .param/l "i" 3 283, +C4<010110>;
+S_0x2650910 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26524f0;
+ .timescale -9 -12;
+L_0x2bc8210/d .functor NOT 1, L_0x2bc93c0, C4<0>, C4<0>, C4<0>;
+L_0x2bc8210 .delay (10000,10000,10000) L_0x2bc8210/d;
+L_0x2bc9ba0/d .functor NOT 1, L_0x2bc9c60, C4<0>, C4<0>, C4<0>;
+L_0x2bc9ba0 .delay (10000,10000,10000) L_0x2bc9ba0/d;
+L_0x2bc9d00/d .functor AND 1, L_0x2bc9e40, L_0x2bc9ba0, C4<1>, C4<1>;
+L_0x2bc9d00 .delay (20000,20000,20000) L_0x2bc9d00/d;
+L_0x2bc9ee0/d .functor XOR 1, L_0x2bc9320, L_0x2bc9930, C4<0>, C4<0>;
+L_0x2bc9ee0 .delay (40000,40000,40000) L_0x2bc9ee0/d;
+L_0x2bc9fd0/d .functor XOR 1, L_0x2bc9ee0, L_0x2bc94f0, C4<0>, C4<0>;
+L_0x2bc9fd0 .delay (40000,40000,40000) L_0x2bc9fd0/d;
+L_0x2bca0c0/d .functor AND 1, L_0x2bc9320, L_0x2bc9930, C4<1>, C4<1>;
+L_0x2bca0c0 .delay (20000,20000,20000) L_0x2bca0c0/d;
+L_0x2bca230/d .functor AND 1, L_0x2bc9ee0, L_0x2bc94f0, C4<1>, C4<1>;
+L_0x2bca230 .delay (20000,20000,20000) L_0x2bca230/d;
+L_0x2bca340/d .functor OR 1, L_0x2bca0c0, L_0x2bca230, C4<0>, C4<0>;
+L_0x2bca340 .delay (20000,20000,20000) L_0x2bca340/d;
+v0x26571a0_0 .net "A", 0 0, L_0x2bc9320; 1 drivers
+v0x2655380_0 .net "AandB", 0 0, L_0x2bca0c0; 1 drivers
+v0x2655420_0 .net "AddSubSLTSum", 0 0, L_0x2bc9fd0; 1 drivers
+v0x26550d0_0 .net "AxorB", 0 0, L_0x2bc9ee0; 1 drivers
+v0x2655150_0 .net "B", 0 0, L_0x2bc93c0; 1 drivers
+v0x2653440_0 .net "BornB", 0 0, L_0x2bc9930; 1 drivers
+v0x26534c0_0 .net "CINandAxorB", 0 0, L_0x2bca230; 1 drivers
+v0x265c100_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x265c180_0 .net *"_s3", 0 0, L_0x2bc9c60; 1 drivers
+v0x265be50_0 .net *"_s5", 0 0, L_0x2bc9e40; 1 drivers
+v0x265bed0_0 .net "carryin", 0 0, L_0x2bc94f0; 1 drivers
+v0x265a030_0 .net "carryout", 0 0, L_0x2bca340; 1 drivers
+v0x265a0b0_0 .net "nB", 0 0, L_0x2bc8210; 1 drivers
+v0x2659d80_0 .net "nCmd2", 0 0, L_0x2bc9ba0; 1 drivers
+v0x26580f0_0 .net "subtract", 0 0, L_0x2bc9d00; 1 drivers
+L_0x2bc9b00 .part v0x2960210_0, 0, 1;
+L_0x2bc9c60 .part v0x2960210_0, 2, 1;
+L_0x2bc9e40 .part v0x2960210_0, 0, 1;
+S_0x26506b0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2650910;
+ .timescale -9 -12;
+L_0x2bc96d0/d .functor NOT 1, L_0x2bc9b00, C4<0>, C4<0>, C4<0>;
+L_0x2bc96d0 .delay (10000,10000,10000) L_0x2bc96d0/d;
+L_0x2bc9730/d .functor AND 1, L_0x2bc93c0, L_0x2bc96d0, C4<1>, C4<1>;
+L_0x2bc9730 .delay (20000,20000,20000) L_0x2bc9730/d;
+L_0x2bc9820/d .functor AND 1, L_0x2bc8210, L_0x2bc9b00, C4<1>, C4<1>;
+L_0x2bc9820 .delay (20000,20000,20000) L_0x2bc9820/d;
+L_0x2bc9930/d .functor OR 1, L_0x2bc9730, L_0x2bc9820, C4<0>, C4<0>;
+L_0x2bc9930 .delay (20000,20000,20000) L_0x2bc9930/d;
+v0x2652820_0 .net "S", 0 0, L_0x2bc9b00; 1 drivers
+v0x2650400_0 .alias "in0", 0 0, v0x2655150_0;
+v0x26504a0_0 .alias "in1", 0 0, v0x265a0b0_0;
+v0x264e7c0_0 .net "nS", 0 0, L_0x2bc96d0; 1 drivers
+v0x264e840_0 .net "out0", 0 0, L_0x2bc9730; 1 drivers
+v0x2657450_0 .net "out1", 0 0, L_0x2bc9820; 1 drivers
+v0x26574f0_0 .alias "outfinal", 0 0, v0x2653440_0;
+S_0x26630f0 .scope generate, "addbits[23]" "addbits[23]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22f2948 .param/l "i" 3 283, +C4<010111>;
+S_0x2645f50 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26630f0;
+ .timescale -9 -12;
+L_0x2bc9590/d .functor NOT 1, L_0x2bca810, C4<0>, C4<0>, C4<0>;
+L_0x2bc9590 .delay (10000,10000,10000) L_0x2bc9590/d;
+L_0x2bcaf80/d .functor NOT 1, L_0x2bcb020, C4<0>, C4<0>, C4<0>;
+L_0x2bcaf80 .delay (10000,10000,10000) L_0x2bcaf80/d;
+L_0x2bcb0c0/d .functor AND 1, L_0x2bcb200, L_0x2bcaf80, C4<1>, C4<1>;
+L_0x2bcb0c0 .delay (20000,20000,20000) L_0x2bcb0c0/d;
+L_0x2bcb2a0/d .functor XOR 1, L_0x2bca770, L_0x2bcad50, C4<0>, C4<0>;
+L_0x2bcb2a0 .delay (40000,40000,40000) L_0x2bcb2a0/d;
+L_0x2bcb390/d .functor XOR 1, L_0x2bcb2a0, L_0x2bca940, C4<0>, C4<0>;
+L_0x2bcb390 .delay (40000,40000,40000) L_0x2bcb390/d;
+L_0x2bcb480/d .functor AND 1, L_0x2bca770, L_0x2bcad50, C4<1>, C4<1>;
+L_0x2bcb480 .delay (20000,20000,20000) L_0x2bcb480/d;
+L_0x2bcb5f0/d .functor AND 1, L_0x2bcb2a0, L_0x2bca940, C4<1>, C4<1>;
+L_0x2bcb5f0 .delay (20000,20000,20000) L_0x2bcb5f0/d;
+L_0x2bcb700/d .functor OR 1, L_0x2bcb480, L_0x2bcb5f0, C4<0>, C4<0>;
+L_0x2bcb700 .delay (20000,20000,20000) L_0x2bcb700/d;
+v0x2646a00_0 .net "A", 0 0, L_0x2bca770; 1 drivers
+v0x2644d00_0 .net "AandB", 0 0, L_0x2bcb480; 1 drivers
+v0x2644da0_0 .net "AddSubSLTSum", 0 0, L_0x2bcb390; 1 drivers
+v0x264db20_0 .net "AxorB", 0 0, L_0x2bcb2a0; 1 drivers
+v0x264dba0_0 .net "B", 0 0, L_0x2bca810; 1 drivers
+v0x264d870_0 .net "BornB", 0 0, L_0x2bcad50; 1 drivers
+v0x264d8f0_0 .net "CINandAxorB", 0 0, L_0x2bcb5f0; 1 drivers
+v0x264bca0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x264bd20_0 .net *"_s3", 0 0, L_0x2bcb020; 1 drivers
+v0x264ba40_0 .net *"_s5", 0 0, L_0x2bcb200; 1 drivers
+v0x264bac0_0 .net "carryin", 0 0, L_0x2bca940; 1 drivers
+v0x264b790_0 .net "carryout", 0 0, L_0x2bcb700; 1 drivers
+v0x264b810_0 .net "nB", 0 0, L_0x2bc9590; 1 drivers
+v0x2649b50_0 .net "nCmd2", 0 0, L_0x2bcaf80; 1 drivers
+v0x26527a0_0 .net "subtract", 0 0, L_0x2bcb0c0; 1 drivers
+L_0x2bcaee0 .part v0x2960210_0, 0, 1;
+L_0x2bcb020 .part v0x2960210_0, 2, 1;
+L_0x2bcb200 .part v0x2960210_0, 0, 1;
+S_0x26d9b90 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2645f50;
+ .timescale -9 -12;
+L_0x2bcab50/d .functor NOT 1, L_0x2bcaee0, C4<0>, C4<0>, C4<0>;
+L_0x2bcab50 .delay (10000,10000,10000) L_0x2bcab50/d;
+L_0x2bcabb0/d .functor AND 1, L_0x2bca810, L_0x2bcab50, C4<1>, C4<1>;
+L_0x2bcabb0 .delay (20000,20000,20000) L_0x2bcabb0/d;
+L_0x2bcac60/d .functor AND 1, L_0x2bc9590, L_0x2bcaee0, C4<1>, C4<1>;
+L_0x2bcac60 .delay (20000,20000,20000) L_0x2bcac60/d;
+L_0x2bcad50/d .functor OR 1, L_0x2bcabb0, L_0x2bcac60, C4<0>, C4<0>;
+L_0x2bcad50 .delay (20000,20000,20000) L_0x2bcad50/d;
+v0x26678a0_0 .net "S", 0 0, L_0x2bcaee0; 1 drivers
+v0x2648eb0_0 .alias "in0", 0 0, v0x264dba0_0;
+v0x2648f50_0 .alias "in1", 0 0, v0x264b810_0;
+v0x2648c00_0 .net "nS", 0 0, L_0x2bcab50; 1 drivers
+v0x2648c80_0 .net "out0", 0 0, L_0x2bcabb0; 1 drivers
+v0x2646ce0_0 .net "out1", 0 0, L_0x2bcac60; 1 drivers
+v0x2646d80_0 .alias "outfinal", 0 0, v0x264d870_0;
+S_0x2688ec0 .scope generate, "addbits[24]" "addbits[24]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22e6b48 .param/l "i" 3 283, +C4<011000>;
+S_0x26847d0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2688ec0;
+ .timescale -9 -12;
+L_0x2bca9e0/d .functor NOT 1, L_0x2bcbbd0, C4<0>, C4<0>, C4<0>;
+L_0x2bca9e0 .delay (10000,10000,10000) L_0x2bca9e0/d;
+L_0x2bcc3c0/d .functor NOT 1, L_0x2bcc480, C4<0>, C4<0>, C4<0>;
+L_0x2bcc3c0 .delay (10000,10000,10000) L_0x2bcc3c0/d;
+L_0x2bcc520/d .functor AND 1, L_0x2bcc660, L_0x2bcc3c0, C4<1>, C4<1>;
+L_0x2bcc520 .delay (20000,20000,20000) L_0x2bcc520/d;
+L_0x2bcc700/d .functor XOR 1, L_0x2bcbb30, L_0x2bcc150, C4<0>, C4<0>;
+L_0x2bcc700 .delay (40000,40000,40000) L_0x2bcc700/d;
+L_0x2bcc7f0/d .functor XOR 1, L_0x2bcc700, L_0x2bcbd00, C4<0>, C4<0>;
+L_0x2bcc7f0 .delay (40000,40000,40000) L_0x2bcc7f0/d;
+L_0x2bcc910/d .functor AND 1, L_0x2bcbb30, L_0x2bcc150, C4<1>, C4<1>;
+L_0x2bcc910 .delay (20000,20000,20000) L_0x2bcc910/d;
+L_0x2bccab0/d .functor AND 1, L_0x2bcc700, L_0x2bcbd00, C4<1>, C4<1>;
+L_0x2bccab0 .delay (20000,20000,20000) L_0x2bccab0/d;
+L_0x2bccbc0/d .functor OR 1, L_0x2bcc910, L_0x2bccab0, C4<0>, C4<0>;
+L_0x2bccbc0 .delay (20000,20000,20000) L_0x2bccbc0/d;
+v0x267afb0_0 .net "A", 0 0, L_0x2bcbb30; 1 drivers
+v0x2676300_0 .net "AandB", 0 0, L_0x2bcc910; 1 drivers
+v0x26763a0_0 .net "AddSubSLTSum", 0 0, L_0x2bcc7f0; 1 drivers
+v0x264ad70_0 .net "AxorB", 0 0, L_0x2bcc700; 1 drivers
+v0x264adf0_0 .net "B", 0 0, L_0x2bcbbd0; 1 drivers
+v0x2671680_0 .net "BornB", 0 0, L_0x2bcc150; 1 drivers
+v0x2671700_0 .net "CINandAxorB", 0 0, L_0x2bccab0; 1 drivers
+v0x2671100_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2671180_0 .net *"_s3", 0 0, L_0x2bcc480; 1 drivers
+v0x266ca10_0 .net *"_s5", 0 0, L_0x2bcc660; 1 drivers
+v0x266ca90_0 .net "carryin", 0 0, L_0x2bcbd00; 1 drivers
+v0x266c490_0 .net "carryout", 0 0, L_0x2bccbc0; 1 drivers
+v0x266c510_0 .net "nB", 0 0, L_0x2bca9e0; 1 drivers
+v0x2667da0_0 .net "nCmd2", 0 0, L_0x2bcc3c0; 1 drivers
+v0x2667820_0 .net "subtract", 0 0, L_0x2bcc520; 1 drivers
+L_0x2bcc320 .part v0x2960210_0, 0, 1;
+L_0x2bcc480 .part v0x2960210_0, 2, 1;
+L_0x2bcc660 .part v0x2960210_0, 0, 1;
+S_0x2684250 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26847d0;
+ .timescale -9 -12;
+L_0x2bcbef0/d .functor NOT 1, L_0x2bcc320, C4<0>, C4<0>, C4<0>;
+L_0x2bcbef0 .delay (10000,10000,10000) L_0x2bcbef0/d;
+L_0x2bcbf50/d .functor AND 1, L_0x2bcbbd0, L_0x2bcbef0, C4<1>, C4<1>;
+L_0x2bcbf50 .delay (20000,20000,20000) L_0x2bcbf50/d;
+L_0x2bcc040/d .functor AND 1, L_0x2bca9e0, L_0x2bcc320, C4<1>, C4<1>;
+L_0x2bcc040 .delay (20000,20000,20000) L_0x2bcc040/d;
+L_0x2bcc150/d .functor OR 1, L_0x2bcbf50, L_0x2bcc040, C4<0>, C4<0>;
+L_0x2bcc150 .delay (20000,20000,20000) L_0x2bcc150/d;
+v0x26894c0_0 .net "S", 0 0, L_0x2bcc320; 1 drivers
+v0x2681c60_0 .alias "in0", 0 0, v0x264adf0_0;
+v0x2681d00_0 .alias "in1", 0 0, v0x266c510_0;
+v0x264b2f0_0 .net "nS", 0 0, L_0x2bcbef0; 1 drivers
+v0x264b370_0 .net "out0", 0 0, L_0x2bcbf50; 1 drivers
+v0x267fc60_0 .net "out1", 0 0, L_0x2bcc040; 1 drivers
+v0x267fd00_0 .alias "outfinal", 0 0, v0x2671680_0;
+S_0x264ff60 .scope generate, "addbits[25]" "addbits[25]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22dc5d8 .param/l "i" 3 283, +C4<011001>;
+S_0x26af760 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x264ff60;
+ .timescale -9 -12;
+L_0x2bcbda0/d .functor NOT 1, L_0x2bcd090, C4<0>, C4<0>, C4<0>;
+L_0x2bcbda0 .delay (10000,10000,10000) L_0x2bcbda0/d;
+L_0x2bcd890/d .functor NOT 1, L_0x2bcd950, C4<0>, C4<0>, C4<0>;
+L_0x2bcd890 .delay (10000,10000,10000) L_0x2bcd890/d;
+L_0x2bcd9f0/d .functor AND 1, L_0x2bcdb30, L_0x2bcd890, C4<1>, C4<1>;
+L_0x2bcd9f0 .delay (20000,20000,20000) L_0x2bcd9f0/d;
+L_0x2bcdbd0/d .functor XOR 1, L_0x2bccff0, L_0x2bcd620, C4<0>, C4<0>;
+L_0x2bcdbd0 .delay (40000,40000,40000) L_0x2bcdbd0/d;
+L_0x2bcdcc0/d .functor XOR 1, L_0x2bcdbd0, L_0x2bcd1c0, C4<0>, C4<0>;
+L_0x2bcdcc0 .delay (40000,40000,40000) L_0x2bcdcc0/d;
+L_0x2bcdde0/d .functor AND 1, L_0x2bccff0, L_0x2bcd620, C4<1>, C4<1>;
+L_0x2bcdde0 .delay (20000,20000,20000) L_0x2bcdde0/d;
+L_0x2bcdf80/d .functor AND 1, L_0x2bcdbd0, L_0x2bcd1c0, C4<1>, C4<1>;
+L_0x2bcdf80 .delay (20000,20000,20000) L_0x2bcdf80/d;
+L_0x2bce090/d .functor OR 1, L_0x2bcdde0, L_0x2bcdf80, C4<0>, C4<0>;
+L_0x2bce090 .delay (20000,20000,20000) L_0x2bce090/d;
+v0x26a5900_0 .net "A", 0 0, L_0x2bccff0; 1 drivers
+v0x264f9e0_0 .net "AandB", 0 0, L_0x2bcdde0; 1 drivers
+v0x264fa80_0 .net "AddSubSLTSum", 0 0, L_0x2bcdcc0; 1 drivers
+v0x26a1300_0 .net "AxorB", 0 0, L_0x2bcdbd0; 1 drivers
+v0x26a1380_0 .net "B", 0 0, L_0x2bcd090; 1 drivers
+v0x269c650_0 .net "BornB", 0 0, L_0x2bcd620; 1 drivers
+v0x269c6d0_0 .net "CINandAxorB", 0 0, L_0x2bcdf80; 1 drivers
+v0x26979a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2697a20_0 .net *"_s3", 0 0, L_0x2bcd950; 1 drivers
+v0x2692cf0_0 .net *"_s5", 0 0, L_0x2bcdb30; 1 drivers
+v0x2692d70_0 .net "carryin", 0 0, L_0x2bcd1c0; 1 drivers
+v0x268e0b0_0 .net "carryout", 0 0, L_0x2bce090; 1 drivers
+v0x268e130_0 .net "nB", 0 0, L_0x2bcbda0; 1 drivers
+v0x268db30_0 .net "nCmd2", 0 0, L_0x2bcd890; 1 drivers
+v0x2689440_0 .net "subtract", 0 0, L_0x2bcd9f0; 1 drivers
+L_0x2bcd7f0 .part v0x2960210_0, 0, 1;
+L_0x2bcd950 .part v0x2960210_0, 2, 1;
+L_0x2bcdb30 .part v0x2960210_0, 0, 1;
+S_0x26af1e0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26af760;
+ .timescale -9 -12;
+L_0x2bcd3e0/d .functor NOT 1, L_0x2bcd7f0, C4<0>, C4<0>, C4<0>;
+L_0x2bcd3e0 .delay (10000,10000,10000) L_0x2bcd3e0/d;
+L_0x2bcd440/d .functor AND 1, L_0x2bcd090, L_0x2bcd3e0, C4<1>, C4<1>;
+L_0x2bcd440 .delay (20000,20000,20000) L_0x2bcd440/d;
+L_0x2bcd530/d .functor AND 1, L_0x2bcbda0, L_0x2bcd7f0, C4<1>, C4<1>;
+L_0x2bcd530 .delay (20000,20000,20000) L_0x2bcd530/d;
+L_0x2bcd620/d .functor OR 1, L_0x2bcd440, L_0x2bcd530, C4<0>, C4<0>;
+L_0x2bcd620 .delay (20000,20000,20000) L_0x2bcd620/d;
+v0x26b4470_0 .net "S", 0 0, L_0x2bcd7f0; 1 drivers
+v0x26aaaf0_0 .alias "in0", 0 0, v0x26a1380_0;
+v0x26aab90_0 .alias "in1", 0 0, v0x268e130_0;
+v0x26aa570_0 .net "nS", 0 0, L_0x2bcd3e0; 1 drivers
+v0x26aa5f0_0 .net "out0", 0 0, L_0x2bcd440; 1 drivers
+v0x26a5e80_0 .net "out1", 0 0, L_0x2bcd530; 1 drivers
+v0x26a5f20_0 .alias "outfinal", 0 0, v0x269c650_0;
+S_0x26dbd50 .scope generate, "addbits[26]" "addbits[26]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x2267c98 .param/l "i" 3 283, +C4<011010>;
+S_0x26dbae0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x26dbd50;
+ .timescale -9 -12;
+L_0x2bcd260/d .functor NOT 1, L_0x2bce560, C4<0>, C4<0>, C4<0>;
+L_0x2bcd260 .delay (10000,10000,10000) L_0x2bcd260/d;
+L_0x2bcedb0/d .functor NOT 1, L_0x2bcee70, C4<0>, C4<0>, C4<0>;
+L_0x2bcedb0 .delay (10000,10000,10000) L_0x2bcedb0/d;
+L_0x2bcef10/d .functor AND 1, L_0x2bcf050, L_0x2bcedb0, C4<1>, C4<1>;
+L_0x2bcef10 .delay (20000,20000,20000) L_0x2bcef10/d;
+L_0x2bcf0f0/d .functor XOR 1, L_0x2bce4c0, L_0x2bceb20, C4<0>, C4<0>;
+L_0x2bcf0f0 .delay (40000,40000,40000) L_0x2bcf0f0/d;
+L_0x2bcf1e0/d .functor XOR 1, L_0x2bcf0f0, L_0x2bce690, C4<0>, C4<0>;
+L_0x2bcf1e0 .delay (40000,40000,40000) L_0x2bcf1e0/d;
+L_0x2bcf2d0/d .functor AND 1, L_0x2bce4c0, L_0x2bceb20, C4<1>, C4<1>;
+L_0x2bcf2d0 .delay (20000,20000,20000) L_0x2bcf2d0/d;
+L_0x2bcf440/d .functor AND 1, L_0x2bcf0f0, L_0x2bce690, C4<1>, C4<1>;
+L_0x2bcf440 .delay (20000,20000,20000) L_0x2bcf440/d;
+L_0x2bcf550/d .functor OR 1, L_0x2bcf2d0, L_0x2bcf440, C4<0>, C4<0>;
+L_0x2bcf550 .delay (20000,20000,20000) L_0x2bcf550/d;
+v0x26d08c0_0 .net "A", 0 0, L_0x2bce4c0; 1 drivers
+v0x26d0960_0 .net "AandB", 0 0, L_0x2bcf2d0; 1 drivers
+v0x26cc1d0_0 .net "AddSubSLTSum", 0 0, L_0x2bcf1e0; 1 drivers
+v0x26cc250_0 .net "AxorB", 0 0, L_0x2bcf0f0; 1 drivers
+v0x26cbc50_0 .net "B", 0 0, L_0x2bce560; 1 drivers
+v0x26cbcd0_0 .net "BornB", 0 0, L_0x2bceb20; 1 drivers
+v0x26c7560_0 .net "CINandAxorB", 0 0, L_0x2bcf440; 1 drivers
+v0x26c75e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x26c6fe0_0 .net *"_s3", 0 0, L_0x2bcee70; 1 drivers
+v0x26c7060_0 .net *"_s5", 0 0, L_0x2bcf050; 1 drivers
+v0x26c28b0_0 .net "carryin", 0 0, L_0x2bce690; 1 drivers
+v0x26c2930_0 .net "carryout", 0 0, L_0x2bcf550; 1 drivers
+v0x26bdd50_0 .net "nB", 0 0, L_0x2bcd260; 1 drivers
+v0x26b90a0_0 .net "nCmd2", 0 0, L_0x2bcedb0; 1 drivers
+v0x26b43f0_0 .net "subtract", 0 0, L_0x2bcef10; 1 drivers
+L_0x2bcecf0 .part v0x2960210_0, 0, 1;
+L_0x2bcee70 .part v0x2960210_0, 2, 1;
+L_0x2bcf050 .part v0x2960210_0, 0, 1;
+S_0x26db840 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x26dbae0;
+ .timescale -9 -12;
+L_0x2bcd330/d .functor NOT 1, L_0x2bcecf0, C4<0>, C4<0>, C4<0>;
+L_0x2bcd330 .delay (10000,10000,10000) L_0x2bcd330/d;
+L_0x2bce920/d .functor AND 1, L_0x2bce560, L_0x2bcd330, C4<1>, C4<1>;
+L_0x2bce920 .delay (20000,20000,20000) L_0x2bce920/d;
+L_0x2bcea10/d .functor AND 1, L_0x2bcd260, L_0x2bcecf0, C4<1>, C4<1>;
+L_0x2bcea10 .delay (20000,20000,20000) L_0x2bcea10/d;
+L_0x2bceb20/d .functor OR 1, L_0x2bce920, L_0x2bcea10, C4<0>, C4<0>;
+L_0x2bceb20 .delay (20000,20000,20000) L_0x2bceb20/d;
+v0x2654c80_0 .net "S", 0 0, L_0x2bcecf0; 1 drivers
+v0x26db380_0 .alias "in0", 0 0, v0x26cbc50_0;
+v0x26db420_0 .alias "in1", 0 0, v0x26bdd50_0;
+v0x26d5ae0_0 .net "nS", 0 0, L_0x2bcd330; 1 drivers
+v0x26d5b60_0 .net "out0", 0 0, L_0x2bce920; 1 drivers
+v0x26d0e40_0 .net "out1", 0 0, L_0x2bcea10; 1 drivers
+v0x26d0ee0_0 .alias "outfinal", 0 0, v0x26cbcd0_0;
+S_0x2415e10 .scope generate, "addbits[27]" "addbits[27]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22cd388 .param/l "i" 3 283, +C4<011011>;
+S_0x2415b60 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2415e10;
+ .timescale -9 -12;
+L_0x2bce730/d .functor NOT 1, L_0x2bcfa20, C4<0>, C4<0>, C4<0>;
+L_0x2bce730 .delay (10000,10000,10000) L_0x2bce730/d;
+L_0x2bd0270/d .functor NOT 1, L_0x2bd0330, C4<0>, C4<0>, C4<0>;
+L_0x2bd0270 .delay (10000,10000,10000) L_0x2bd0270/d;
+L_0x2bd03d0/d .functor AND 1, L_0x2bd0510, L_0x2bd0270, C4<1>, C4<1>;
+L_0x2bd03d0 .delay (20000,20000,20000) L_0x2bd03d0/d;
+L_0x2bd05b0/d .functor XOR 1, L_0x2bcf980, L_0x2bcffe0, C4<0>, C4<0>;
+L_0x2bd05b0 .delay (40000,40000,40000) L_0x2bd05b0/d;
+L_0x2bd06a0/d .functor XOR 1, L_0x2bd05b0, L_0x2bcfb50, C4<0>, C4<0>;
+L_0x2bd06a0 .delay (40000,40000,40000) L_0x2bd06a0/d;
+L_0x2bd0790/d .functor AND 1, L_0x2bcf980, L_0x2bcffe0, C4<1>, C4<1>;
+L_0x2bd0790 .delay (20000,20000,20000) L_0x2bd0790/d;
+L_0x2bd0920/d .functor AND 1, L_0x2bd05b0, L_0x2bcfb50, C4<1>, C4<1>;
+L_0x2bd0920 .delay (20000,20000,20000) L_0x2bd0920/d;
+L_0x2bd0a30/d .functor OR 1, L_0x2bd0790, L_0x2bd0920, C4<0>, C4<0>;
+L_0x2bd0a30 .delay (20000,20000,20000) L_0x2bd0a30/d;
+v0x27b6ba0_0 .net "A", 0 0, L_0x2bcf980; 1 drivers
+v0x27b6900_0 .net "AandB", 0 0, L_0x2bd0790; 1 drivers
+v0x27b69a0_0 .net "AddSubSLTSum", 0 0, L_0x2bd06a0; 1 drivers
+v0x27b59a0_0 .net "AxorB", 0 0, L_0x2bd05b0; 1 drivers
+v0x27b5a20_0 .net "B", 0 0, L_0x2bcfa20; 1 drivers
+v0x27b5700_0 .net "BornB", 0 0, L_0x2bcffe0; 1 drivers
+v0x27b5780_0 .net "CINandAxorB", 0 0, L_0x2bd0920; 1 drivers
+v0x27b38e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x27b3960_0 .net *"_s3", 0 0, L_0x2bd0330; 1 drivers
+v0x265e560_0 .net *"_s5", 0 0, L_0x2bd0510; 1 drivers
+v0x265e5e0_0 .net "carryin", 0 0, L_0x2bcfb50; 1 drivers
+v0x26598b0_0 .net "carryout", 0 0, L_0x2bd0a30; 1 drivers
+v0x2659930_0 .net "nB", 0 0, L_0x2bce730; 1 drivers
+v0x26df700_0 .net "nCmd2", 0 0, L_0x2bd0270; 1 drivers
+v0x2654c00_0 .net "subtract", 0 0, L_0x2bd03d0; 1 drivers
+L_0x2bd01b0 .part v0x2960210_0, 0, 1;
+L_0x2bd0330 .part v0x2960210_0, 2, 1;
+L_0x2bd0510 .part v0x2960210_0, 0, 1;
+S_0x2419120 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2415b60;
+ .timescale -9 -12;
+L_0x2bcfd80/d .functor NOT 1, L_0x2bd01b0, C4<0>, C4<0>, C4<0>;
+L_0x2bcfd80 .delay (10000,10000,10000) L_0x2bcfd80/d;
+L_0x2bcfde0/d .functor AND 1, L_0x2bcfa20, L_0x2bcfd80, C4<1>, C4<1>;
+L_0x2bcfde0 .delay (20000,20000,20000) L_0x2bcfde0/d;
+L_0x2bcfed0/d .functor AND 1, L_0x2bce730, L_0x2bd01b0, C4<1>, C4<1>;
+L_0x2bcfed0 .delay (20000,20000,20000) L_0x2bcfed0/d;
+L_0x2bcffe0/d .functor OR 1, L_0x2bcfde0, L_0x2bcfed0, C4<0>, C4<0>;
+L_0x2bcffe0 .delay (20000,20000,20000) L_0x2bcffe0/d;
+v0x2411eb0_0 .net "S", 0 0, L_0x2bd01b0; 1 drivers
+v0x2418e70_0 .alias "in0", 0 0, v0x27b5a20_0;
+v0x2418f10_0 .alias "in1", 0 0, v0x2659930_0;
+v0x2417f00_0 .net "nS", 0 0, L_0x2bcfd80; 1 drivers
+v0x2417f80_0 .net "out0", 0 0, L_0x2bcfde0; 1 drivers
+v0x2417c50_0 .net "out1", 0 0, L_0x2bcfed0; 1 drivers
+v0x2417cf0_0 .alias "outfinal", 0 0, v0x27b5700_0;
+S_0x240a190 .scope generate, "addbits[28]" "addbits[28]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22c6068 .param/l "i" 3 283, +C4<011100>;
+S_0x2409ee0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x240a190;
+ .timescale -9 -12;
+L_0x2bcfbf0/d .functor NOT 1, L_0x2bd0f00, C4<0>, C4<0>, C4<0>;
+L_0x2bcfbf0 .delay (10000,10000,10000) L_0x2bcfbf0/d;
+L_0x2bd1740/d .functor NOT 1, L_0x2bd1800, C4<0>, C4<0>, C4<0>;
+L_0x2bd1740 .delay (10000,10000,10000) L_0x2bd1740/d;
+L_0x2bd18a0/d .functor AND 1, L_0x2bd19e0, L_0x2bd1740, C4<1>, C4<1>;
+L_0x2bd18a0 .delay (20000,20000,20000) L_0x2bd18a0/d;
+L_0x2bd1a80/d .functor XOR 1, L_0x2bd0e60, L_0x2bd1510, C4<0>, C4<0>;
+L_0x2bd1a80 .delay (40000,40000,40000) L_0x2bd1a80/d;
+L_0x2bd1b70/d .functor XOR 1, L_0x2bd1a80, L_0x2bd1030, C4<0>, C4<0>;
+L_0x2bd1b70 .delay (40000,40000,40000) L_0x2bd1b70/d;
+L_0x2bd1c60/d .functor AND 1, L_0x2bd0e60, L_0x2bd1510, C4<1>, C4<1>;
+L_0x2bd1c60 .delay (20000,20000,20000) L_0x2bd1c60/d;
+L_0x2bd1dd0/d .functor AND 1, L_0x2bd1a80, L_0x2bd1030, C4<1>, C4<1>;
+L_0x2bd1dd0 .delay (20000,20000,20000) L_0x2bd1dd0/d;
+L_0x2bd1ee0/d .functor OR 1, L_0x2bd1c60, L_0x2bd1dd0, C4<0>, C4<0>;
+L_0x2bd1ee0 .delay (20000,20000,20000) L_0x2bd1ee0/d;
+v0x240c280_0 .net "A", 0 0, L_0x2bd0e60; 1 drivers
+v0x240bfd0_0 .net "AandB", 0 0, L_0x2bd1c60; 1 drivers
+v0x240c070_0 .net "AddSubSLTSum", 0 0, L_0x2bd1b70; 1 drivers
+v0x24096d0_0 .net "AxorB", 0 0, L_0x2bd1a80; 1 drivers
+v0x2409750_0 .net "B", 0 0, L_0x2bd0f00; 1 drivers
+v0x240fff0_0 .net "BornB", 0 0, L_0x2bd1510; 1 drivers
+v0x2410070_0 .net "CINandAxorB", 0 0, L_0x2bd1dd0; 1 drivers
+v0x240fd40_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x240fdc0_0 .net *"_s3", 0 0, L_0x2bd1800; 1 drivers
+v0x2413300_0 .net *"_s5", 0 0, L_0x2bd19e0; 1 drivers
+v0x2413380_0 .net "carryin", 0 0, L_0x2bd1030; 1 drivers
+v0x2413050_0 .net "carryout", 0 0, L_0x2bd1ee0; 1 drivers
+v0x24130d0_0 .net "nB", 0 0, L_0x2bcfbf0; 1 drivers
+v0x24120e0_0 .net "nCmd2", 0 0, L_0x2bd1740; 1 drivers
+v0x2411e30_0 .net "subtract", 0 0, L_0x2bd18a0; 1 drivers
+L_0x2bd16a0 .part v0x2960210_0, 0, 1;
+L_0x2bd1800 .part v0x2960210_0, 2, 1;
+L_0x2bd19e0 .part v0x2960210_0, 0, 1;
+S_0x2409c30 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2409ee0;
+ .timescale -9 -12;
+L_0x2bd1290/d .functor NOT 1, L_0x2bd16a0, C4<0>, C4<0>, C4<0>;
+L_0x2bd1290 .delay (10000,10000,10000) L_0x2bd1290/d;
+L_0x2bd1330/d .functor AND 1, L_0x2bd0f00, L_0x2bd1290, C4<1>, C4<1>;
+L_0x2bd1330 .delay (20000,20000,20000) L_0x2bd1330/d;
+L_0x2bd1420/d .functor AND 1, L_0x2bcfbf0, L_0x2bd16a0, C4<1>, C4<1>;
+L_0x2bd1420 .delay (20000,20000,20000) L_0x2bd1420/d;
+L_0x2bd1510/d .functor OR 1, L_0x2bd1330, L_0x2bd1420, C4<0>, C4<0>;
+L_0x2bd1510 .delay (20000,20000,20000) L_0x2bd1510/d;
+v0x240b840_0 .net "S", 0 0, L_0x2bd16a0; 1 drivers
+v0x2409980_0 .alias "in0", 0 0, v0x2409750_0;
+v0x2409a20_0 .alias "in1", 0 0, v0x24130d0_0;
+v0x240d4c0_0 .net "nS", 0 0, L_0x2bd1290; 1 drivers
+v0x240d540_0 .net "out0", 0 0, L_0x2bd1330; 1 drivers
+v0x240d210_0 .net "out1", 0 0, L_0x2bd1420; 1 drivers
+v0x240d2b0_0 .alias "outfinal", 0 0, v0x240fff0_0;
+S_0x2405ec0 .scope generate, "addbits[29]" "addbits[29]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22c0648 .param/l "i" 3 283, +C4<011101>;
+S_0x2405c10 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x2405ec0;
+ .timescale -9 -12;
+L_0x2bd10d0/d .functor NOT 1, L_0x2ba5750, C4<0>, C4<0>, C4<0>;
+L_0x2bd10d0 .delay (10000,10000,10000) L_0x2bd10d0/d;
+L_0x2bd2bc0/d .functor NOT 1, L_0x2bd2c80, C4<0>, C4<0>, C4<0>;
+L_0x2bd2bc0 .delay (10000,10000,10000) L_0x2bd2bc0/d;
+L_0x2bd2d20/d .functor AND 1, L_0x2bd2e60, L_0x2bd2bc0, C4<1>, C4<1>;
+L_0x2bd2d20 .delay (20000,20000,20000) L_0x2bd2d20/d;
+L_0x2bd2f00/d .functor XOR 1, L_0x2ba56b0, L_0x2bd2990, C4<0>, C4<0>;
+L_0x2bd2f00 .delay (40000,40000,40000) L_0x2bd2f00/d;
+L_0x2bd3020/d .functor XOR 1, L_0x2bd2f00, L_0x2ba5880, C4<0>, C4<0>;
+L_0x2bd3020 .delay (40000,40000,40000) L_0x2bd3020/d;
+L_0x2bd3140/d .functor AND 1, L_0x2ba56b0, L_0x2bd2990, C4<1>, C4<1>;
+L_0x2bd3140 .delay (20000,20000,20000) L_0x2bd3140/d;
+L_0x2bd32b0/d .functor AND 1, L_0x2bd2f00, L_0x2ba5880, C4<1>, C4<1>;
+L_0x2bd32b0 .delay (20000,20000,20000) L_0x2bd32b0/d;
+L_0x2bd33c0/d .functor OR 1, L_0x2bd3140, L_0x2bd32b0, C4<0>, C4<0>;
+L_0x2bd33c0 .delay (20000,20000,20000) L_0x2bd33c0/d;
+v0x2403b20_0 .net "A", 0 0, L_0x2ba56b0; 1 drivers
+v0x2407660_0 .net "AandB", 0 0, L_0x2bd3140; 1 drivers
+v0x2407700_0 .net "AddSubSLTSum", 0 0, L_0x2bd3020; 1 drivers
+v0x24073b0_0 .net "AxorB", 0 0, L_0x2bd2f00; 1 drivers
+v0x2407430_0 .net "B", 0 0, L_0x2ba5750; 1 drivers
+v0x2406420_0 .net "BornB", 0 0, L_0x2bd2990; 1 drivers
+v0x24064a0_0 .net "CINandAxorB", 0 0, L_0x2bd32b0; 1 drivers
+v0x2406170_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24061f0_0 .net *"_s3", 0 0, L_0x2bd2c80; 1 drivers
+v0x2403870_0 .net *"_s5", 0 0, L_0x2bd2e60; 1 drivers
+v0x24038f0_0 .net "carryin", 0 0, L_0x2ba5880; 1 drivers
+v0x240bd20_0 .net "carryout", 0 0, L_0x2bd33c0; 1 drivers
+v0x240bda0_0 .net "nB", 0 0, L_0x2bd10d0; 1 drivers
+v0x240ba70_0 .net "nCmd2", 0 0, L_0x2bd2bc0; 1 drivers
+v0x240b7c0_0 .net "subtract", 0 0, L_0x2bd2d20; 1 drivers
+L_0x2bd2b20 .part v0x2960210_0, 0, 1;
+L_0x2bd2c80 .part v0x2960210_0, 2, 1;
+L_0x2bd2e60 .part v0x2960210_0, 0, 1;
+S_0x2405960 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x2405c10;
+ .timescale -9 -12;
+L_0x2bd1230/d .functor NOT 1, L_0x2bd2b20, C4<0>, C4<0>, C4<0>;
+L_0x2bd1230 .delay (10000,10000,10000) L_0x2bd1230/d;
+L_0x2bd27b0/d .functor AND 1, L_0x2ba5750, L_0x2bd1230, C4<1>, C4<1>;
+L_0x2bd27b0 .delay (20000,20000,20000) L_0x2bd27b0/d;
+L_0x2bd28a0/d .functor AND 1, L_0x2bd10d0, L_0x2bd2b20, C4<1>, C4<1>;
+L_0x2bd28a0 .delay (20000,20000,20000) L_0x2bd28a0/d;
+L_0x2bd2990/d .functor OR 1, L_0x2bd27b0, L_0x2bd28a0, C4<0>, C4<0>;
+L_0x2bd2990 .delay (20000,20000,20000) L_0x2bd2990/d;
+v0x23fda90_0 .net "S", 0 0, L_0x2bd2b20; 1 drivers
+v0x2404330_0 .alias "in0", 0 0, v0x2407430_0;
+v0x24043d0_0 .alias "in1", 0 0, v0x240bda0_0;
+v0x2404080_0 .net "nS", 0 0, L_0x2bd1230; 1 drivers
+v0x2404100_0 .net "out0", 0 0, L_0x2bd27b0; 1 drivers
+v0x2403dd0_0 .net "out1", 0 0, L_0x2bd28a0; 1 drivers
+v0x2403e70_0 .alias "outfinal", 0 0, v0x2406420_0;
+S_0x23fb710 .scope generate, "addbits[30]" "addbits[30]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22ba6f8 .param/l "i" 3 283, +C4<011110>;
+S_0x23fa7a0 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x23fb710;
+ .timescale -9 -12;
+L_0x2ba5920/d .functor NOT 1, L_0x2bd4600, C4<0>, C4<0>, C4<0>;
+L_0x2ba5920 .delay (10000,10000,10000) L_0x2ba5920/d;
+L_0x2bd37a0/d .functor NOT 1, L_0x2bd3860, C4<0>, C4<0>, C4<0>;
+L_0x2bd37a0 .delay (10000,10000,10000) L_0x2bd37a0/d;
+L_0x2bd3900/d .functor AND 1, L_0x2bd3a40, L_0x2bd37a0, C4<1>, C4<1>;
+L_0x2bd3900 .delay (20000,20000,20000) L_0x2bd3900/d;
+L_0x2bd3ae0/d .functor XOR 1, L_0x2bd4560, L_0x2bd25a0, C4<0>, C4<0>;
+L_0x2bd3ae0 .delay (40000,40000,40000) L_0x2bd3ae0/d;
+L_0x2bd3bd0/d .functor XOR 1, L_0x2bd3ae0, L_0x2bd4730, C4<0>, C4<0>;
+L_0x2bd3bd0 .delay (40000,40000,40000) L_0x2bd3bd0/d;
+L_0x2bd4a80/d .functor AND 1, L_0x2bd4560, L_0x2bd25a0, C4<1>, C4<1>;
+L_0x2bd4a80 .delay (20000,20000,20000) L_0x2bd4a80/d;
+L_0x2bd4bf0/d .functor AND 1, L_0x2bd3ae0, L_0x2bd4730, C4<1>, C4<1>;
+L_0x2bd4bf0 .delay (20000,20000,20000) L_0x2bd4bf0/d;
+L_0x2bd4ce0/d .functor OR 1, L_0x2bd4a80, L_0x2bd4bf0, C4<0>, C4<0>;
+L_0x2bd4ce0 .delay (20000,20000,20000) L_0x2bd4ce0/d;
+v0x23fe4d0_0 .net "A", 0 0, L_0x2bd4560; 1 drivers
+v0x23fe220_0 .net "AandB", 0 0, L_0x2bd4a80; 1 drivers
+v0x23fe2c0_0 .net "AddSubSLTSum", 0 0, L_0x2bd3bd0; 1 drivers
+v0x23fdf70_0 .net "AxorB", 0 0, L_0x2bd3ae0; 1 drivers
+v0x23fdff0_0 .net "B", 0 0, L_0x2bd4600; 1 drivers
+v0x23fdcc0_0 .net "BornB", 0 0, L_0x2bd25a0; 1 drivers
+v0x23fdd40_0 .net "CINandAxorB", 0 0, L_0x2bd4bf0; 1 drivers
+v0x2401800_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2401880_0 .net *"_s3", 0 0, L_0x2bd3860; 1 drivers
+v0x2401550_0 .net *"_s5", 0 0, L_0x2bd3a40; 1 drivers
+v0x24015d0_0 .net "carryin", 0 0, L_0x2bd4730; 1 drivers
+v0x24005c0_0 .net "carryout", 0 0, L_0x2bd4ce0; 1 drivers
+v0x2400640_0 .net "nB", 0 0, L_0x2ba5920; 1 drivers
+v0x2400310_0 .net "nCmd2", 0 0, L_0x2bd37a0; 1 drivers
+v0x23fda10_0 .net "subtract", 0 0, L_0x2bd3900; 1 drivers
+L_0x2bd3700 .part v0x2960210_0, 0, 1;
+L_0x2bd3860 .part v0x2960210_0, 2, 1;
+L_0x2bd3a40 .part v0x2960210_0, 0, 1;
+S_0x23fa4f0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23fa7a0;
+ .timescale -9 -12;
+L_0x2bd22c0/d .functor NOT 1, L_0x2bd3700, C4<0>, C4<0>, C4<0>;
+L_0x2bd22c0 .delay (10000,10000,10000) L_0x2bd22c0/d;
+L_0x2bd2380/d .functor AND 1, L_0x2bd4600, L_0x2bd22c0, C4<1>, C4<1>;
+L_0x2bd2380 .delay (20000,20000,20000) L_0x2bd2380/d;
+L_0x2bd2490/d .functor AND 1, L_0x2ba5920, L_0x2bd3700, C4<1>, C4<1>;
+L_0x2bd2490 .delay (20000,20000,20000) L_0x2bd2490/d;
+L_0x2bd25a0/d .functor OR 1, L_0x2bd2380, L_0x2bd2490, C4<0>, C4<0>;
+L_0x2bd25a0 .delay (20000,20000,20000) L_0x2bd25a0/d;
+v0x23fba40_0 .net "S", 0 0, L_0x2bd3700; 1 drivers
+v0x2400060_0 .alias "in0", 0 0, v0x23fdff0_0;
+v0x24000e0_0 .alias "in1", 0 0, v0x2400640_0;
+v0x23ffdb0_0 .net "nS", 0 0, L_0x2bd22c0; 1 drivers
+v0x23ffe30_0 .net "out0", 0 0, L_0x2bd2380; 1 drivers
+v0x23ffb00_0 .net "out1", 0 0, L_0x2bd2490; 1 drivers
+v0x23ffba0_0 .alias "outfinal", 0 0, v0x23fdcc0_0;
+S_0x23ec260 .scope generate, "addbits[31]" "addbits[31]" 3 283, 3 283, S_0x23ec510;
+ .timescale -9 -12;
+P_0x22b12d8 .param/l "i" 3 283, +C4<011111>;
+S_0x23efd80 .scope module, "attempt" "MiddleAddSubSLT" 3 285, 3 189, S_0x23ec260;
+ .timescale -9 -12;
+L_0x2bd47d0/d .functor NOT 1, L_0x2bd5190, C4<0>, C4<0>, C4<0>;
+L_0x2bd47d0 .delay (10000,10000,10000) L_0x2bd47d0/d;
+L_0x2bd59c0/d .functor NOT 1, L_0x2bd5a60, C4<0>, C4<0>, C4<0>;
+L_0x2bd59c0 .delay (10000,10000,10000) L_0x2bd59c0/d;
+L_0x2bd5b00/d .functor AND 1, L_0x2bd5c40, L_0x2bd59c0, C4<1>, C4<1>;
+L_0x2bd5b00 .delay (20000,20000,20000) L_0x2bd5b00/d;
+L_0x2bd5ce0/d .functor XOR 1, L_0x2bd50f0, L_0x2bd5790, C4<0>, C4<0>;
+L_0x2bd5ce0 .delay (40000,40000,40000) L_0x2bd5ce0/d;
+L_0x2bd5dd0/d .functor XOR 1, L_0x2bd5ce0, L_0x2bd52c0, C4<0>, C4<0>;
+L_0x2bd5dd0 .delay (40000,40000,40000) L_0x2bd5dd0/d;
+L_0x2bd5ef0/d .functor AND 1, L_0x2bd50f0, L_0x2bd5790, C4<1>, C4<1>;
+L_0x2bd5ef0 .delay (20000,20000,20000) L_0x2bd5ef0/d;
+L_0x2bd6090/d .functor AND 1, L_0x2bd5ce0, L_0x2bd52c0, C4<1>, C4<1>;
+L_0x2bd6090 .delay (20000,20000,20000) L_0x2bd6090/d;
+L_0x2bd6180/d .functor OR 1, L_0x2bd5ef0, L_0x2bd6090, C4<0>, C4<0>;
+L_0x2bd6180 .delay (20000,20000,20000) L_0x2bd6180/d;
+v0x23f2910_0 .net "A", 0 0, L_0x2bd50f0; 1 drivers
+v0x23f25e0_0 .net "AandB", 0 0, L_0x2bd5ef0; 1 drivers
+v0x23f2660_0 .net "AddSubSLTSum", 0 0, L_0x2bd5dd0; 1 drivers
+v0x23f5ba0_0 .net "AxorB", 0 0, L_0x2bd5ce0; 1 drivers
+v0x23f5c20_0 .net "B", 0 0, L_0x2bd5190; 1 drivers
+v0x23f58f0_0 .net "BornB", 0 0, L_0x2bd5790; 1 drivers
+v0x23f5970_0 .net "CINandAxorB", 0 0, L_0x2bd6090; 1 drivers
+v0x23f4980_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x23f4a00_0 .net *"_s3", 0 0, L_0x2bd5a60; 1 drivers
+v0x23f46d0_0 .net *"_s5", 0 0, L_0x2bd5c40; 1 drivers
+v0x23f4750_0 .net "carryin", 0 0, L_0x2bd52c0; 1 drivers
+v0x23f86b0_0 .net "carryout", 0 0, L_0x2bd6180; 1 drivers
+v0x23f8730_0 .net "nB", 0 0, L_0x2bd47d0; 1 drivers
+v0x23f8400_0 .net "nCmd2", 0 0, L_0x2bd59c0; 1 drivers
+v0x23fb9c0_0 .net "subtract", 0 0, L_0x2bd5b00; 1 drivers
+L_0x2bd5920 .part v0x2960210_0, 0, 1;
+L_0x2bd5a60 .part v0x2960210_0, 2, 1;
+L_0x2bd5c40 .part v0x2960210_0, 0, 1;
+S_0x23efad0 .scope module, "mux0" "TwoInMux" 3 205, 3 109, S_0x23efd80;
+ .timescale -9 -12;
+L_0x2bd4930/d .functor NOT 1, L_0x2bd5920, C4<0>, C4<0>, C4<0>;
+L_0x2bd4930 .delay (10000,10000,10000) L_0x2bd4930/d;
+L_0x2bd55b0/d .functor AND 1, L_0x2bd5190, L_0x2bd4930, C4<1>, C4<1>;
+L_0x2bd55b0 .delay (20000,20000,20000) L_0x2bd55b0/d;
+L_0x2bd56a0/d .functor AND 1, L_0x2bd47d0, L_0x2bd5920, C4<1>, C4<1>;
+L_0x2bd56a0 .delay (20000,20000,20000) L_0x2bd56a0/d;
+L_0x2bd5790/d .functor OR 1, L_0x2bd55b0, L_0x2bd56a0, C4<0>, C4<0>;
+L_0x2bd5790 .delay (20000,20000,20000) L_0x2bd5790/d;
+v0x23eeb60_0 .net "S", 0 0, L_0x2bd5920; 1 drivers
+v0x23eebe0_0 .alias "in0", 0 0, v0x23f5c20_0;
+v0x23ee8b0_0 .alias "in1", 0 0, v0x23f8730_0;
+v0x23ee930_0 .net "nS", 0 0, L_0x2bd4930; 1 drivers
+v0x23ebfb0_0 .net "out0", 0 0, L_0x2bd55b0; 1 drivers
+v0x23ec030_0 .net "out1", 0 0, L_0x2bd56a0; 1 drivers
+v0x23f2890_0 .alias "outfinal", 0 0, v0x23f58f0_0;
+S_0x2543140 .scope module, "trial1" "AndNand32" 3 54, 3 216, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x24b4d58 .param/l "size" 3 223, +C4<0100000>;
+v0x23eca70_0 .alias "A", 31 0, v0x295f580_0;
+v0x23ecaf0_0 .alias "AndNandOut", 31 0, v0x2418bc0_0;
+v0x23ec7c0_0 .alias "B", 31 0, v0x295f6a0_0;
+v0x23ec840_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bd7eb0 .part/pv L_0x2bd7c40, 1, 1, 32;
+L_0x2b3e060 .part v0x295fe90_0, 1, 1;
+L_0x2b3e100 .part v0x2960190_0, 1, 1;
+L_0x2bd9ac0 .part/pv L_0x2bd9870, 2, 1, 32;
+L_0x2bd9b60 .part v0x295fe90_0, 2, 1;
+L_0x2bd9c00 .part v0x2960190_0, 2, 1;
+L_0x2bda570 .part/pv L_0x2bda300, 3, 1, 32;
+L_0x2bda610 .part v0x295fe90_0, 3, 1;
+L_0x2bda700 .part v0x2960190_0, 3, 1;
+L_0x2bdafd0 .part/pv L_0x2bdad60, 4, 1, 32;
+L_0x2bdb0d0 .part v0x295fe90_0, 4, 1;
+L_0x2bdb170 .part v0x2960190_0, 4, 1;
+L_0x2bdba60 .part/pv L_0x2bdb7f0, 5, 1, 32;
+L_0x2bdbb00 .part v0x295fe90_0, 5, 1;
+L_0x2bdbc20 .part v0x2960190_0, 5, 1;
+L_0x2bdc530 .part/pv L_0x2bdc2c0, 6, 1, 32;
+L_0x2bdc660 .part v0x295fe90_0, 6, 1;
+L_0x2bdc700 .part v0x2960190_0, 6, 1;
+L_0x2bdd050 .part/pv L_0x2bdcde0, 7, 1, 32;
+L_0x2bdd0f0 .part v0x295fe90_0, 7, 1;
+L_0x2bdc7f0 .part v0x2960190_0, 7, 1;
+L_0x2bddab0 .part/pv L_0x2bdd840, 8, 1, 32;
+L_0x2bdd190 .part v0x295fe90_0, 8, 1;
+L_0x2bddc10 .part v0x2960190_0, 8, 1;
+L_0x2bde550 .part/pv L_0x2bde2e0, 9, 1, 32;
+L_0x2bde5f0 .part v0x295fe90_0, 9, 1;
+L_0x2bddd00 .part v0x2960190_0, 9, 1;
+L_0x2bdefc0 .part/pv L_0x2bded50, 10, 1, 32;
+L_0x2bde690 .part v0x295fe90_0, 10, 1;
+L_0x2bdf150 .part v0x2960190_0, 10, 1;
+L_0x2bdfa50 .part/pv L_0x2bdf7e0, 11, 1, 32;
+L_0x2bdfaf0 .part v0x295fe90_0, 11, 1;
+L_0x2bdf240 .part v0x2960190_0, 11, 1;
+L_0x2be04c0 .part/pv L_0x2be0250, 12, 1, 32;
+L_0x2bdfb90 .part v0x295fe90_0, 12, 1;
+L_0x2be0680 .part v0x2960190_0, 12, 1;
+L_0x2be0f60 .part/pv L_0x2be0cf0, 13, 1, 32;
+L_0x2be1000 .part v0x295fe90_0, 13, 1;
+L_0x2be0720 .part v0x2960190_0, 13, 1;
+L_0x2be19c0 .part/pv L_0x2be1750, 14, 1, 32;
+L_0x2be10a0 .part v0x295fe90_0, 14, 1;
+L_0x2be1140 .part v0x2960190_0, 14, 1;
+L_0x2be2450 .part/pv L_0x2be21e0, 15, 1, 32;
+L_0x2be24f0 .part v0x295fe90_0, 15, 1;
+L_0x2be1c00 .part v0x2960190_0, 15, 1;
+L_0x2be2ec0 .part/pv L_0x2be2c50, 16, 1, 32;
+L_0x2be2590 .part v0x295fe90_0, 16, 1;
+L_0x2be2630 .part v0x2960190_0, 16, 1;
+L_0x2be3960 .part/pv L_0x2be36f0, 17, 1, 32;
+L_0x2be3a00 .part v0x295fe90_0, 17, 1;
+L_0x2be3130 .part v0x2960190_0, 17, 1;
+L_0x2be43c0 .part/pv L_0x2be4150, 18, 1, 32;
+L_0x2be3aa0 .part v0x295fe90_0, 18, 1;
+L_0x2be3b40 .part v0x2960190_0, 18, 1;
+L_0x2be4e60 .part/pv L_0x2be4bf0, 19, 1, 32;
+L_0x2be4f00 .part v0x295fe90_0, 19, 1;
+L_0x2be4460 .part v0x2960190_0, 19, 1;
+L_0x2be58c0 .part/pv L_0x2be5650, 20, 1, 32;
+L_0x2be4fa0 .part v0x295fe90_0, 20, 1;
+L_0x2be5040 .part v0x2960190_0, 20, 1;
+L_0x2be6250 .part/pv L_0x2bdbba0, 21, 1, 32;
+L_0x2be62f0 .part v0x295fe90_0, 21, 1;
+L_0x2be5960 .part v0x2960190_0, 21, 1;
+L_0x2be6c00 .part/pv L_0x2be69d0, 22, 1, 32;
+L_0x2be6390 .part v0x295fe90_0, 22, 1;
+L_0x2be6430 .part v0x2960190_0, 22, 1;
+L_0x2be7580 .part/pv L_0x2be7350, 23, 1, 32;
+L_0x2be7620 .part v0x295fe90_0, 23, 1;
+L_0x2be6ca0 .part v0x2960190_0, 23, 1;
+L_0x2be7f20 .part/pv L_0x2be7cf0, 24, 1, 32;
+L_0x2be76c0 .part v0x295fe90_0, 24, 1;
+L_0x2be7760 .part v0x2960190_0, 24, 1;
+L_0x2be8890 .part/pv L_0x2be8660, 25, 1, 32;
+L_0x2be8930 .part v0x295fe90_0, 25, 1;
+L_0x2be7fc0 .part v0x2960190_0, 25, 1;
+L_0x2be9210 .part/pv L_0x2be8fe0, 26, 1, 32;
+L_0x2be89d0 .part v0x295fe90_0, 26, 1;
+L_0x2be8a70 .part v0x2960190_0, 26, 1;
+L_0x2be9ba0 .part/pv L_0x2be9970, 27, 1, 32;
+L_0x2be9c40 .part v0x295fe90_0, 27, 1;
+L_0x2be92b0 .part v0x2960190_0, 27, 1;
+L_0x2bea5b0 .part/pv L_0x2bea340, 28, 1, 32;
+L_0x2be9ce0 .part v0x295fe90_0, 28, 1;
+L_0x2be9d80 .part v0x2960190_0, 28, 1;
+L_0x2beb050 .part/pv L_0x2beade0, 29, 1, 32;
+L_0x2beb0f0 .part v0x295fe90_0, 29, 1;
+L_0x2bea650 .part v0x2960190_0, 29, 1;
+L_0x2bebab0 .part/pv L_0x2beb840, 30, 1, 32;
+L_0x2beb190 .part v0x295fe90_0, 30, 1;
+L_0x2beb230 .part v0x2960190_0, 30, 1;
+L_0x2bec540 .part/pv L_0x2bec2d0, 31, 1, 32;
+L_0x2bec5e0 .part v0x295fe90_0, 31, 1;
+L_0x2bebb50 .part v0x2960190_0, 31, 1;
+L_0x2becfb0 .part/pv L_0x2becd40, 0, 1, 32;
+L_0x2bec680 .part v0x295fe90_0, 0, 1;
+L_0x2bec720 .part v0x2960190_0, 0, 1;
+S_0x23e6960 .scope module, "attempt2" "AndNand" 3 227, 3 149, S_0x2543140;
+ .timescale -9 -12;
+L_0x2bebc40/d .functor NAND 1, L_0x2bec680, L_0x2bec720, C4<1>, C4<1>;
+L_0x2bebc40 .delay (10000,10000,10000) L_0x2bebc40/d;
+L_0x2bebda0/d .functor NOT 1, L_0x2bebc40, C4<0>, C4<0>, C4<0>;
+L_0x2bebda0 .delay (10000,10000,10000) L_0x2bebda0/d;
+v0x23e8d00_0 .net "A", 0 0, L_0x2bec680; 1 drivers
+v0x23e8d80_0 .net "AandB", 0 0, L_0x2bebda0; 1 drivers
+v0x23e8a50_0 .net "AnandB", 0 0, L_0x2bebc40; 1 drivers
+v0x23e8ad0_0 .net "AndNandOut", 0 0, L_0x2becd40; 1 drivers
+v0x23e6150_0 .net "B", 0 0, L_0x2bec720; 1 drivers
+v0x23e61d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2becf10 .part v0x2960210_0, 0, 1;
+S_0x23e66b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23e6960;
+ .timescale -9 -12;
+L_0x2beca20/d .functor NOT 1, L_0x2becf10, C4<0>, C4<0>, C4<0>;
+L_0x2beca20 .delay (10000,10000,10000) L_0x2beca20/d;
+L_0x2becae0/d .functor AND 1, L_0x2bebda0, L_0x2beca20, C4<1>, C4<1>;
+L_0x2becae0 .delay (20000,20000,20000) L_0x2becae0/d;
+L_0x2becbf0/d .functor AND 1, L_0x2bebc40, L_0x2becf10, C4<1>, C4<1>;
+L_0x2becbf0 .delay (20000,20000,20000) L_0x2becbf0/d;
+L_0x2becd40/d .functor OR 1, L_0x2becae0, L_0x2becbf0, C4<0>, C4<0>;
+L_0x2becd40 .delay (20000,20000,20000) L_0x2becd40/d;
+v0x23e6c90_0 .net "S", 0 0, L_0x2becf10; 1 drivers
+v0x23e6400_0 .alias "in0", 0 0, v0x23e8d80_0;
+v0x23e6480_0 .alias "in1", 0 0, v0x23e8a50_0;
+v0x23e9f40_0 .net "nS", 0 0, L_0x2beca20; 1 drivers
+v0x23e9fc0_0 .net "out0", 0 0, L_0x2becae0; 1 drivers
+v0x23e9c90_0 .net "out1", 0 0, L_0x2becbf0; 1 drivers
+v0x23e9d10_0 .alias "outfinal", 0 0, v0x23e8ad0_0;
+S_0x23e0600 .scope generate, "andbits[1]" "andbits[1]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22a0a58 .param/l "i" 3 231, +C4<01>;
+S_0x23e40e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23e0600;
+ .timescale -9 -12;
+L_0x2bd6a20/d .functor NAND 1, L_0x2b3e060, L_0x2b3e100, C4<1>, C4<1>;
+L_0x2bd6a20 .delay (10000,10000,10000) L_0x2bd6a20/d;
+L_0x2b88560/d .functor NOT 1, L_0x2bd6a20, C4<0>, C4<0>, C4<0>;
+L_0x2b88560 .delay (10000,10000,10000) L_0x2b88560/d;
+v0x23e8820_0 .net "A", 0 0, L_0x2b3e060; 1 drivers
+v0x23e84f0_0 .net "AandB", 0 0, L_0x2b88560; 1 drivers
+v0x23e8570_0 .net "AnandB", 0 0, L_0x2bd6a20; 1 drivers
+v0x23e8240_0 .net "AndNandOut", 0 0, L_0x2bd7c40; 1 drivers
+v0x23e82c0_0 .net "B", 0 0, L_0x2b3e100; 1 drivers
+v0x23e6c10_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bd7e10 .part v0x2960210_0, 0, 1;
+S_0x23e3e30 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23e40e0;
+ .timescale -9 -12;
+L_0x2b88690/d .functor NOT 1, L_0x2bd7e10, C4<0>, C4<0>, C4<0>;
+L_0x2b88690 .delay (10000,10000,10000) L_0x2b88690/d;
+L_0x2bd79e0/d .functor AND 1, L_0x2b88560, L_0x2b88690, C4<1>, C4<1>;
+L_0x2bd79e0 .delay (20000,20000,20000) L_0x2bd79e0/d;
+L_0x2bd7af0/d .functor AND 1, L_0x2bd6a20, L_0x2bd7e10, C4<1>, C4<1>;
+L_0x2bd7af0 .delay (20000,20000,20000) L_0x2bd7af0/d;
+L_0x2bd7c40/d .functor OR 1, L_0x2bd79e0, L_0x2bd7af0, C4<0>, C4<0>;
+L_0x2bd7c40 .delay (20000,20000,20000) L_0x2bd7c40/d;
+v0x23e2ea0_0 .net "S", 0 0, L_0x2bd7e10; 1 drivers
+v0x23e2f20_0 .alias "in0", 0 0, v0x23e84f0_0;
+v0x23e2bf0_0 .alias "in1", 0 0, v0x23e8570_0;
+v0x23e2c70_0 .net "nS", 0 0, L_0x2b88690; 1 drivers
+v0x23e0080_0 .net "out0", 0 0, L_0x2bd79e0; 1 drivers
+v0x23e0100_0 .net "out1", 0 0, L_0x2bd7af0; 1 drivers
+v0x23e87a0_0 .alias "outfinal", 0 0, v0x23e8240_0;
+S_0x23dde70 .scope generate, "andbits[2]" "andbits[2]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2296668 .param/l "i" 3 231, +C4<010>;
+S_0x23dd1f0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23dde70;
+ .timescale -9 -12;
+L_0x2bd7f50/d .functor NAND 1, L_0x2bd9b60, L_0x2bd9c00, C4<1>, C4<1>;
+L_0x2bd7f50 .delay (10000,10000,10000) L_0x2bd7f50/d;
+L_0x2b3e2f0/d .functor NOT 1, L_0x2bd7f50, C4<0>, C4<0>, C4<0>;
+L_0x2b3e2f0 .delay (10000,10000,10000) L_0x2b3e2f0/d;
+v0x23e0db0_0 .net "A", 0 0, L_0x2bd9b60; 1 drivers
+v0x23e0e50_0 .net "AandB", 0 0, L_0x2b3e2f0; 1 drivers
+v0x23e0b20_0 .net "AnandB", 0 0, L_0x2bd7f50; 1 drivers
+v0x23e0ba0_0 .net "AndNandOut", 0 0, L_0x2bd9870; 1 drivers
+v0x23e0890_0 .net "B", 0 0, L_0x2bd9c00; 1 drivers
+v0x23e0910_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bd9a20 .part v0x2960210_0, 0, 1;
+S_0x23dcf60 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23dd1f0;
+ .timescale -9 -12;
+L_0x2bd95f0/d .functor NOT 1, L_0x2bd9a20, C4<0>, C4<0>, C4<0>;
+L_0x2bd95f0 .delay (10000,10000,10000) L_0x2bd95f0/d;
+L_0x2bd9650/d .functor AND 1, L_0x2b3e2f0, L_0x2bd95f0, C4<1>, C4<1>;
+L_0x2bd9650 .delay (20000,20000,20000) L_0x2bd9650/d;
+L_0x2bd9740/d .functor AND 1, L_0x2bd7f50, L_0x2bd9a20, C4<1>, C4<1>;
+L_0x2bd9740 .delay (20000,20000,20000) L_0x2bd9740/d;
+L_0x2bd9870/d .functor OR 1, L_0x2bd9650, L_0x2bd9740, C4<0>, C4<0>;
+L_0x2bd9870 .delay (20000,20000,20000) L_0x2bd9870/d;
+v0x23de180_0 .net "S", 0 0, L_0x2bd9a20; 1 drivers
+v0x23e2940_0 .alias "in0", 0 0, v0x23e0e50_0;
+v0x23e29c0_0 .alias "in1", 0 0, v0x23e0b20_0;
+v0x23e2690_0 .net "nS", 0 0, L_0x2bd95f0; 1 drivers
+v0x23e2710_0 .net "out0", 0 0, L_0x2bd9650; 1 drivers
+v0x23e23e0_0 .net "out1", 0 0, L_0x2bd9740; 1 drivers
+v0x23e2460_0 .alias "outfinal", 0 0, v0x23e0ba0_0;
+S_0x23d56a0 .scope generate, "andbits[3]" "andbits[3]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x228d248 .param/l "i" 3 231, +C4<011>;
+S_0x23d5410 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23d56a0;
+ .timescale -9 -12;
+L_0x2bd9d30/d .functor NAND 1, L_0x2bda610, L_0x2bda700, C4<1>, C4<1>;
+L_0x2bd9d30 .delay (10000,10000,10000) L_0x2bd9d30/d;
+L_0x2bd9eb0/d .functor NOT 1, L_0x2bd9d30, C4<0>, C4<0>, C4<0>;
+L_0x2bd9eb0 .delay (10000,10000,10000) L_0x2bd9eb0/d;
+v0x23db280_0 .net "A", 0 0, L_0x2bda610; 1 drivers
+v0x23daf70_0 .net "AandB", 0 0, L_0x2bd9eb0; 1 drivers
+v0x23daff0_0 .net "AnandB", 0 0, L_0x2bd9d30; 1 drivers
+v0x23de390_0 .net "AndNandOut", 0 0, L_0x2bda300; 1 drivers
+v0x23de410_0 .net "B", 0 0, L_0x2bda700; 1 drivers
+v0x23de100_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bda4d0 .part v0x2960210_0, 0, 1;
+S_0x23d8830 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23d5410;
+ .timescale -9 -12;
+L_0x2bd9fe0/d .functor NOT 1, L_0x2bda4d0, C4<0>, C4<0>, C4<0>;
+L_0x2bd9fe0 .delay (10000,10000,10000) L_0x2bd9fe0/d;
+L_0x2bda0a0/d .functor AND 1, L_0x2bd9eb0, L_0x2bd9fe0, C4<1>, C4<1>;
+L_0x2bda0a0 .delay (20000,20000,20000) L_0x2bda0a0/d;
+L_0x2bda1b0/d .functor AND 1, L_0x2bd9d30, L_0x2bda4d0, C4<1>, C4<1>;
+L_0x2bda1b0 .delay (20000,20000,20000) L_0x2bda1b0/d;
+L_0x2bda300/d .functor OR 1, L_0x2bda0a0, L_0x2bda1b0, C4<0>, C4<0>;
+L_0x2bda300 .delay (20000,20000,20000) L_0x2bda300/d;
+v0x23d85a0_0 .net "S", 0 0, L_0x2bda4d0; 1 drivers
+v0x23d8620_0 .alias "in0", 0 0, v0x23daf70_0;
+v0x23d7690_0 .alias "in1", 0 0, v0x23daff0_0;
+v0x23d7710_0 .net "nS", 0 0, L_0x2bd9fe0; 1 drivers
+v0x23d7400_0 .net "out0", 0 0, L_0x2bda0a0; 1 drivers
+v0x23d7480_0 .net "out1", 0 0, L_0x2bda1b0; 1 drivers
+v0x23db200_0 .alias "outfinal", 0 0, v0x23de390_0;
+S_0x23cbf80 .scope generate, "andbits[4]" "andbits[4]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2283c18 .param/l "i" 3 231, +C4<0100>;
+S_0x23cbcf0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23cbf80;
+ .timescale -9 -12;
+L_0x2bda7f0/d .functor NAND 1, L_0x2bdb0d0, L_0x2bdb170, C4<1>, C4<1>;
+L_0x2bda7f0 .delay (10000,10000,10000) L_0x2bda7f0/d;
+L_0x2bda910/d .functor NOT 1, L_0x2bda7f0, C4<0>, C4<0>, C4<0>;
+L_0x2bda910 .delay (10000,10000,10000) L_0x2bda910/d;
+v0x23d2a40_0 .net "A", 0 0, L_0x2bdb0d0; 1 drivers
+v0x23d2ae0_0 .net "AandB", 0 0, L_0x2bda910; 1 drivers
+v0x23d1b30_0 .net "AnandB", 0 0, L_0x2bda7f0; 1 drivers
+v0x23d1bb0_0 .net "AndNandOut", 0 0, L_0x2bdad60; 1 drivers
+v0x23d18a0_0 .net "B", 0 0, L_0x2bdb170; 1 drivers
+v0x23d1920_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdaf30 .part v0x2960210_0, 0, 1;
+S_0x23c9210 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23cbcf0;
+ .timescale -9 -12;
+L_0x2bdaa40/d .functor NOT 1, L_0x2bdaf30, C4<0>, C4<0>, C4<0>;
+L_0x2bdaa40 .delay (10000,10000,10000) L_0x2bdaa40/d;
+L_0x2bdab00/d .functor AND 1, L_0x2bda910, L_0x2bdaa40, C4<1>, C4<1>;
+L_0x2bdab00 .delay (20000,20000,20000) L_0x2bdab00/d;
+L_0x2bdac10/d .functor AND 1, L_0x2bda7f0, L_0x2bdaf30, C4<1>, C4<1>;
+L_0x2bdac10 .delay (20000,20000,20000) L_0x2bdac10/d;
+L_0x2bdad60/d .functor OR 1, L_0x2bdab00, L_0x2bdac10, C4<0>, C4<0>;
+L_0x2bdad60 .delay (20000,20000,20000) L_0x2bdad60/d;
+v0x23ccca0_0 .net "S", 0 0, L_0x2bdaf30; 1 drivers
+v0x23cfb40_0 .alias "in0", 0 0, v0x23d2ae0_0;
+v0x23cfbc0_0 .alias "in1", 0 0, v0x23d1b30_0;
+v0x23cf8b0_0 .net "nS", 0 0, L_0x2bdaa40; 1 drivers
+v0x23cf930_0 .net "out0", 0 0, L_0x2bdab00; 1 drivers
+v0x23d2cd0_0 .net "out1", 0 0, L_0x2bdac10; 1 drivers
+v0x23d2d50_0 .alias "outfinal", 0 0, v0x23d1bb0_0;
+S_0x23cba60 .scope generate, "andbits[5]" "andbits[5]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22646e8 .param/l "i" 3 231, +C4<0101>;
+S_0x23cb7d0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23cba60;
+ .timescale -9 -12;
+L_0x2bdb070/d .functor NAND 1, L_0x2bdbb00, L_0x2bdbc20, C4<1>, C4<1>;
+L_0x2bdb070 .delay (10000,10000,10000) L_0x2bdb070/d;
+L_0x2bdb3a0/d .functor NOT 1, L_0x2bdb070, C4<0>, C4<0>, C4<0>;
+L_0x2bdb3a0 .delay (10000,10000,10000) L_0x2bdb3a0/d;
+v0x23c9810_0 .net "A", 0 0, L_0x2bdbb00; 1 drivers
+v0x23cd170_0 .net "AandB", 0 0, L_0x2bdb3a0; 1 drivers
+v0x23cd1f0_0 .net "AnandB", 0 0, L_0x2bdb070; 1 drivers
+v0x23ccee0_0 .net "AndNandOut", 0 0, L_0x2bdb7f0; 1 drivers
+v0x23ccf60_0 .net "B", 0 0, L_0x2bdbc20; 1 drivers
+v0x23ccc20_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdb9c0 .part v0x2960210_0, 0, 1;
+S_0x23cb250 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23cb7d0;
+ .timescale -9 -12;
+L_0x2bdb4d0/d .functor NOT 1, L_0x2bdb9c0, C4<0>, C4<0>, C4<0>;
+L_0x2bdb4d0 .delay (10000,10000,10000) L_0x2bdb4d0/d;
+L_0x2bdb590/d .functor AND 1, L_0x2bdb3a0, L_0x2bdb4d0, C4<1>, C4<1>;
+L_0x2bdb590 .delay (20000,20000,20000) L_0x2bdb590/d;
+L_0x2bdb6a0/d .functor AND 1, L_0x2bdb070, L_0x2bdb9c0, C4<1>, C4<1>;
+L_0x2bdb6a0 .delay (20000,20000,20000) L_0x2bdb6a0/d;
+L_0x2bdb7f0/d .functor OR 1, L_0x2bdb590, L_0x2bdb6a0, C4<0>, C4<0>;
+L_0x2bdb7f0 .delay (20000,20000,20000) L_0x2bdb7f0/d;
+v0x23c9f40_0 .net "S", 0 0, L_0x2bdb9c0; 1 drivers
+v0x23c9fc0_0 .alias "in0", 0 0, v0x23cd170_0;
+v0x23c9cb0_0 .alias "in1", 0 0, v0x23cd1f0_0;
+v0x23c9d30_0 .net "nS", 0 0, L_0x2bdb4d0; 1 drivers
+v0x23c9a20_0 .net "out0", 0 0, L_0x2bdb590; 1 drivers
+v0x23c9aa0_0 .net "out1", 0 0, L_0x2bdb6a0; 1 drivers
+v0x23c9790_0 .alias "outfinal", 0 0, v0x23ccee0_0;
+S_0x23c4060 .scope generate, "andbits[6]" "andbits[6]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2269238 .param/l "i" 3 231, +C4<0110>;
+S_0x23c3dd0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23c4060;
+ .timescale -9 -12;
+L_0x2bdbd10/d .functor NAND 1, L_0x2bdc660, L_0x2bdc700, C4<1>, C4<1>;
+L_0x2bdbd10 .delay (10000,10000,10000) L_0x2bdbd10/d;
+L_0x2bdbe70/d .functor NOT 1, L_0x2bdbd10, C4<0>, C4<0>, C4<0>;
+L_0x2bdbe70 .delay (10000,10000,10000) L_0x2bdbe70/d;
+v0x23c6330_0 .net "A", 0 0, L_0x2bdc660; 1 drivers
+v0x23c63d0_0 .net "AandB", 0 0, L_0x2bdbe70; 1 drivers
+v0x23c60a0_0 .net "AnandB", 0 0, L_0x2bdbd10; 1 drivers
+v0x23c6120_0 .net "AndNandOut", 0 0, L_0x2bdc2c0; 1 drivers
+v0x23c35c0_0 .net "B", 0 0, L_0x2bdc700; 1 drivers
+v0x23c3640_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdc490 .part v0x2960210_0, 0, 1;
+S_0x23c3b40 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23c3dd0;
+ .timescale -9 -12;
+L_0x2bdbfa0/d .functor NOT 1, L_0x2bdc490, C4<0>, C4<0>, C4<0>;
+L_0x2bdbfa0 .delay (10000,10000,10000) L_0x2bdbfa0/d;
+L_0x2bdc060/d .functor AND 1, L_0x2bdbe70, L_0x2bdbfa0, C4<1>, C4<1>;
+L_0x2bdc060 .delay (20000,20000,20000) L_0x2bdc060/d;
+L_0x2bdc170/d .functor AND 1, L_0x2bdbd10, L_0x2bdc490, C4<1>, C4<1>;
+L_0x2bdc170 .delay (20000,20000,20000) L_0x2bdc170/d;
+L_0x2bdc2c0/d .functor OR 1, L_0x2bdc060, L_0x2bdc170, C4<0>, C4<0>;
+L_0x2bdc2c0 .delay (20000,20000,20000) L_0x2bdc2c0/d;
+v0x23c4370_0 .net "S", 0 0, L_0x2bdc490; 1 drivers
+v0x23c7520_0 .alias "in0", 0 0, v0x23c63d0_0;
+v0x23c75a0_0 .alias "in1", 0 0, v0x23c60a0_0;
+v0x23c7290_0 .net "nS", 0 0, L_0x2bdbfa0; 1 drivers
+v0x23c7310_0 .net "out0", 0 0, L_0x2bdc060; 1 drivers
+v0x23c6fd0_0 .net "out1", 0 0, L_0x2bdc170; 1 drivers
+v0x23c7050_0 .alias "outfinal", 0 0, v0x23c6120_0;
+S_0x23c1640 .scope generate, "andbits[7]" "andbits[7]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2270968 .param/l "i" 3 231, +C4<0111>;
+S_0x23c1380 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23c1640;
+ .timescale -9 -12;
+L_0x2bdc5d0/d .functor NAND 1, L_0x2bdd0f0, L_0x2bdc7f0, C4<1>, C4<1>;
+L_0x2bdc5d0 .delay (10000,10000,10000) L_0x2bdc5d0/d;
+L_0x2bdc990/d .functor NOT 1, L_0x2bdc5d0, C4<0>, C4<0>, C4<0>;
+L_0x2bdc990 .delay (10000,10000,10000) L_0x2bdc990/d;
+v0x23c5e90_0 .net "A", 0 0, L_0x2bdd0f0; 1 drivers
+v0x23c5b80_0 .net "AandB", 0 0, L_0x2bdc990; 1 drivers
+v0x23c5c00_0 .net "AnandB", 0 0, L_0x2bdc5d0; 1 drivers
+v0x23c5600_0 .net "AndNandOut", 0 0, L_0x2bdcde0; 1 drivers
+v0x23c5680_0 .net "B", 0 0, L_0x2bdc7f0; 1 drivers
+v0x23c42f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdcfb0 .part v0x2960210_0, 0, 1;
+S_0x23c06e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23c1380;
+ .timescale -9 -12;
+L_0x2bdcac0/d .functor NOT 1, L_0x2bdcfb0, C4<0>, C4<0>, C4<0>;
+L_0x2bdcac0 .delay (10000,10000,10000) L_0x2bdcac0/d;
+L_0x2bdcb80/d .functor AND 1, L_0x2bdc990, L_0x2bdcac0, C4<1>, C4<1>;
+L_0x2bdcb80 .delay (20000,20000,20000) L_0x2bdcb80/d;
+L_0x2bdcc90/d .functor AND 1, L_0x2bdc5d0, L_0x2bdcfb0, C4<1>, C4<1>;
+L_0x2bdcc90 .delay (20000,20000,20000) L_0x2bdcc90/d;
+L_0x2bdcde0/d .functor OR 1, L_0x2bdcb80, L_0x2bdcc90, C4<0>, C4<0>;
+L_0x2bdcde0 .delay (20000,20000,20000) L_0x2bdcde0/d;
+v0x23c0450_0 .net "S", 0 0, L_0x2bdcfb0; 1 drivers
+v0x23c04d0_0 .alias "in0", 0 0, v0x23c5b80_0;
+v0x23bdc60_0 .alias "in1", 0 0, v0x23c5c00_0;
+v0x23bdce0_0 .net "nS", 0 0, L_0x2bdcac0; 1 drivers
+v0x23bd9e0_0 .net "out0", 0 0, L_0x2bdcb80; 1 drivers
+v0x23bda60_0 .net "out1", 0 0, L_0x2bdcc90; 1 drivers
+v0x23c5e10_0 .alias "outfinal", 0 0, v0x23c5600_0;
+S_0x23ba8a0 .scope generate, "andbits[8]" "andbits[8]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x227e5e8 .param/l "i" 3 231, +C4<01000>;
+S_0x23c01c0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23ba8a0;
+ .timescale -9 -12;
+L_0x2bdd290/d .functor NAND 1, L_0x2bdd190, L_0x2bddc10, C4<1>, C4<1>;
+L_0x2bdd290 .delay (10000,10000,10000) L_0x2bdd290/d;
+L_0x2bdd3f0/d .functor NOT 1, L_0x2bdd290, C4<0>, C4<0>, C4<0>;
+L_0x2bdd3f0 .delay (10000,10000,10000) L_0x2bdd3f0/d;
+v0x23be180_0 .net "A", 0 0, L_0x2bdd190; 1 drivers
+v0x23be220_0 .net "AandB", 0 0, L_0x2bdd3f0; 1 drivers
+v0x23bdef0_0 .net "AnandB", 0 0, L_0x2bdd290; 1 drivers
+v0x23bdf70_0 .net "AndNandOut", 0 0, L_0x2bdd840; 1 drivers
+v0x23c18d0_0 .net "B", 0 0, L_0x2bddc10; 1 drivers
+v0x23c1950_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdda10 .part v0x2960210_0, 0, 1;
+S_0x23bff30 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23c01c0;
+ .timescale -9 -12;
+L_0x2bdd520/d .functor NOT 1, L_0x2bdda10, C4<0>, C4<0>, C4<0>;
+L_0x2bdd520 .delay (10000,10000,10000) L_0x2bdd520/d;
+L_0x2bdd5e0/d .functor AND 1, L_0x2bdd3f0, L_0x2bdd520, C4<1>, C4<1>;
+L_0x2bdd5e0 .delay (20000,20000,20000) L_0x2bdd5e0/d;
+L_0x2bdd6f0/d .functor AND 1, L_0x2bdd290, L_0x2bdda10, C4<1>, C4<1>;
+L_0x2bdd6f0 .delay (20000,20000,20000) L_0x2bdd6f0/d;
+L_0x2bdd840/d .functor OR 1, L_0x2bdd5e0, L_0x2bdd6f0, C4<0>, C4<0>;
+L_0x2bdd840 .delay (20000,20000,20000) L_0x2bdd840/d;
+v0x23babb0_0 .net "S", 0 0, L_0x2bdda10; 1 drivers
+v0x23bf9b0_0 .alias "in0", 0 0, v0x23be220_0;
+v0x23bfa30_0 .alias "in1", 0 0, v0x23bdef0_0;
+v0x23be6a0_0 .net "nS", 0 0, L_0x2bdd520; 1 drivers
+v0x23be720_0 .net "out0", 0 0, L_0x2bdd5e0; 1 drivers
+v0x23be410_0 .net "out1", 0 0, L_0x2bdd6f0; 1 drivers
+v0x23be490_0 .alias "outfinal", 0 0, v0x23bdf70_0;
+S_0x23b2d50 .scope generate, "andbits[9]" "andbits[9]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2283138 .param/l "i" 3 231, +C4<01001>;
+S_0x23b6170 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23b2d50;
+ .timescale -9 -12;
+L_0x2bddb50/d .functor NAND 1, L_0x2bde5f0, L_0x2bddd00, C4<1>, C4<1>;
+L_0x2bddb50 .delay (10000,10000,10000) L_0x2bddb50/d;
+L_0x2bdde90/d .functor NOT 1, L_0x2bddb50, C4<0>, C4<0>, C4<0>;
+L_0x2bdde90 .delay (10000,10000,10000) L_0x2bdde90/d;
+v0x23b8930_0 .net "A", 0 0, L_0x2bde5f0; 1 drivers
+v0x23bbcd0_0 .net "AandB", 0 0, L_0x2bdde90; 1 drivers
+v0x23bbd50_0 .net "AnandB", 0 0, L_0x2bddb50; 1 drivers
+v0x23bba40_0 .net "AndNandOut", 0 0, L_0x2bde2e0; 1 drivers
+v0x23bbac0_0 .net "B", 0 0, L_0x2bddd00; 1 drivers
+v0x23bab30_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bde4b0 .part v0x2960210_0, 0, 1;
+S_0x23b5ee0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23b6170;
+ .timescale -9 -12;
+L_0x2bddfc0/d .functor NOT 1, L_0x2bde4b0, C4<0>, C4<0>, C4<0>;
+L_0x2bddfc0 .delay (10000,10000,10000) L_0x2bddfc0/d;
+L_0x2bde080/d .functor AND 1, L_0x2bdde90, L_0x2bddfc0, C4<1>, C4<1>;
+L_0x2bde080 .delay (20000,20000,20000) L_0x2bde080/d;
+L_0x2bde190/d .functor AND 1, L_0x2bddb50, L_0x2bde4b0, C4<1>, C4<1>;
+L_0x2bde190 .delay (20000,20000,20000) L_0x2bde190/d;
+L_0x2bde2e0/d .functor OR 1, L_0x2bde080, L_0x2bde190, C4<0>, C4<0>;
+L_0x2bde2e0 .delay (20000,20000,20000) L_0x2bde2e0/d;
+v0x23b4fd0_0 .net "S", 0 0, L_0x2bde4b0; 1 drivers
+v0x23b5050_0 .alias "in0", 0 0, v0x23bbcd0_0;
+v0x23b4d40_0 .alias "in1", 0 0, v0x23bbd50_0;
+v0x23b4dc0_0 .net "nS", 0 0, L_0x2bddfc0; 1 drivers
+v0x23b8b40_0 .net "out0", 0 0, L_0x2bde080; 1 drivers
+v0x23b8bc0_0 .net "out1", 0 0, L_0x2bde190; 1 drivers
+v0x23b88b0_0 .alias "outfinal", 0 0, v0x23bba40_0;
+S_0x23ad1d0 .scope generate, "andbits[10]" "andbits[10]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2287c88 .param/l "i" 3 231, +C4<01010>;
+S_0x23acf40 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23ad1d0;
+ .timescale -9 -12;
+L_0x2bde7c0/d .functor NAND 1, L_0x2bde690, L_0x2bdf150, C4<1>, C4<1>;
+L_0x2bde7c0 .delay (10000,10000,10000) L_0x2bde7c0/d;
+L_0x2bde900/d .functor NOT 1, L_0x2bde7c0, C4<0>, C4<0>, C4<0>;
+L_0x2bde900 .delay (10000,10000,10000) L_0x2bde900/d;
+v0x23af1e0_0 .net "A", 0 0, L_0x2bde690; 1 drivers
+v0x23af280_0 .net "AandB", 0 0, L_0x2bde900; 1 drivers
+v0x23ac730_0 .net "AnandB", 0 0, L_0x2bde7c0; 1 drivers
+v0x23ac7b0_0 .net "AndNandOut", 0 0, L_0x2bded50; 1 drivers
+v0x23b2fe0_0 .net "B", 0 0, L_0x2bdf150; 1 drivers
+v0x23b3060_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdef20 .part v0x2960210_0, 0, 1;
+S_0x23accb0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23acf40;
+ .timescale -9 -12;
+L_0x2bdea30/d .functor NOT 1, L_0x2bdef20, C4<0>, C4<0>, C4<0>;
+L_0x2bdea30 .delay (10000,10000,10000) L_0x2bdea30/d;
+L_0x2bdeaf0/d .functor AND 1, L_0x2bde900, L_0x2bdea30, C4<1>, C4<1>;
+L_0x2bdeaf0 .delay (20000,20000,20000) L_0x2bdeaf0/d;
+L_0x2bdec00/d .functor AND 1, L_0x2bde7c0, L_0x2bdef20, C4<1>, C4<1>;
+L_0x2bdec00 .delay (20000,20000,20000) L_0x2bdec00/d;
+L_0x2bded50/d .functor OR 1, L_0x2bdeaf0, L_0x2bdec00, C4<0>, C4<0>;
+L_0x2bded50 .delay (20000,20000,20000) L_0x2bded50/d;
+v0x23ad4e0_0 .net "S", 0 0, L_0x2bdef20; 1 drivers
+v0x23b0610_0 .alias "in0", 0 0, v0x23af280_0;
+v0x23b0690_0 .alias "in1", 0 0, v0x23ac730_0;
+v0x23b0380_0 .net "nS", 0 0, L_0x2bdea30; 1 drivers
+v0x23b0400_0 .net "out0", 0 0, L_0x2bdeaf0; 1 drivers
+v0x23af470_0 .net "out1", 0 0, L_0x2bdec00; 1 drivers
+v0x23af4f0_0 .alias "outfinal", 0 0, v0x23ac7b0_0;
+S_0x23a7580 .scope generate, "andbits[11]" "andbits[11]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2295e48 .param/l "i" 3 231, +C4<01011>;
+S_0x23a72f0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23a7580;
+ .timescale -9 -12;
+L_0x2bdf060/d .functor NAND 1, L_0x2bdfaf0, L_0x2bdf240, C4<1>, C4<1>;
+L_0x2bdf060 .delay (10000,10000,10000) L_0x2bdf060/d;
+L_0x2bdf390/d .functor NOT 1, L_0x2bdf060, C4<0>, C4<0>, C4<0>;
+L_0x2bdf390 .delay (10000,10000,10000) L_0x2bdf390/d;
+v0x23a98d0_0 .net "A", 0 0, L_0x2bdfaf0; 1 drivers
+v0x23a95c0_0 .net "AandB", 0 0, L_0x2bdf390; 1 drivers
+v0x23a9640_0 .net "AnandB", 0 0, L_0x2bdf060; 1 drivers
+v0x23a6ae0_0 .net "AndNandOut", 0 0, L_0x2bdf7e0; 1 drivers
+v0x23a6b60_0 .net "B", 0 0, L_0x2bdf240; 1 drivers
+v0x23ad460_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bdf9b0 .part v0x2960210_0, 0, 1;
+S_0x23a7060 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23a72f0;
+ .timescale -9 -12;
+L_0x2bdf4c0/d .functor NOT 1, L_0x2bdf9b0, C4<0>, C4<0>, C4<0>;
+L_0x2bdf4c0 .delay (10000,10000,10000) L_0x2bdf4c0/d;
+L_0x2bdf580/d .functor AND 1, L_0x2bdf390, L_0x2bdf4c0, C4<1>, C4<1>;
+L_0x2bdf580 .delay (20000,20000,20000) L_0x2bdf580/d;
+L_0x2bdf690/d .functor AND 1, L_0x2bdf060, L_0x2bdf9b0, C4<1>, C4<1>;
+L_0x2bdf690 .delay (20000,20000,20000) L_0x2bdf690/d;
+L_0x2bdf7e0/d .functor OR 1, L_0x2bdf580, L_0x2bdf690, C4<0>, C4<0>;
+L_0x2bdf7e0 .delay (20000,20000,20000) L_0x2bdf7e0/d;
+v0x23aaa40_0 .net "S", 0 0, L_0x2bdf9b0; 1 drivers
+v0x23aaac0_0 .alias "in0", 0 0, v0x23a95c0_0;
+v0x23aa7b0_0 .alias "in1", 0 0, v0x23a9640_0;
+v0x23aa830_0 .net "nS", 0 0, L_0x2bdf4c0; 1 drivers
+v0x23aa4f0_0 .net "out0", 0 0, L_0x2bdf580; 1 drivers
+v0x23aa570_0 .net "out1", 0 0, L_0x2bdf690; 1 drivers
+v0x23a9850_0 .alias "outfinal", 0 0, v0x23a6ae0_0;
+S_0x23a4b60 .scope generate, "andbits[12]" "andbits[12]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x229ee28 .param/l "i" 3 231, +C4<01100>;
+S_0x23a48a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23a4b60;
+ .timescale -9 -12;
+L_0x2bdfca0/d .functor NAND 1, L_0x2bdfb90, L_0x2be0680, C4<1>, C4<1>;
+L_0x2bdfca0 .delay (10000,10000,10000) L_0x2bdfca0/d;
+L_0x2bdfe00/d .functor NOT 1, L_0x2bdfca0, C4<0>, C4<0>, C4<0>;
+L_0x2bdfe00 .delay (10000,10000,10000) L_0x2bdfe00/d;
+v0x23a90a0_0 .net "A", 0 0, L_0x2bdfb90; 1 drivers
+v0x23a9140_0 .net "AandB", 0 0, L_0x2bdfe00; 1 drivers
+v0x23a8b20_0 .net "AnandB", 0 0, L_0x2bdfca0; 1 drivers
+v0x23a8ba0_0 .net "AndNandOut", 0 0, L_0x2be0250; 1 drivers
+v0x23a7810_0 .net "B", 0 0, L_0x2be0680; 1 drivers
+v0x23a7890_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be0420 .part v0x2960210_0, 0, 1;
+S_0x23a3c00 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23a48a0;
+ .timescale -9 -12;
+L_0x2bdff30/d .functor NOT 1, L_0x2be0420, C4<0>, C4<0>, C4<0>;
+L_0x2bdff30 .delay (10000,10000,10000) L_0x2bdff30/d;
+L_0x2bdfff0/d .functor AND 1, L_0x2bdfe00, L_0x2bdff30, C4<1>, C4<1>;
+L_0x2bdfff0 .delay (20000,20000,20000) L_0x2bdfff0/d;
+L_0x2be0100/d .functor AND 1, L_0x2bdfca0, L_0x2be0420, C4<1>, C4<1>;
+L_0x2be0100 .delay (20000,20000,20000) L_0x2be0100/d;
+L_0x2be0250/d .functor OR 1, L_0x2bdfff0, L_0x2be0100, C4<0>, C4<0>;
+L_0x2be0250 .delay (20000,20000,20000) L_0x2be0250/d;
+v0x23a4e70_0 .net "S", 0 0, L_0x2be0420; 1 drivers
+v0x23a3970_0 .alias "in0", 0 0, v0x23a9140_0;
+v0x23a39f0_0 .alias "in1", 0 0, v0x23a8b20_0;
+v0x23a0e90_0 .net "nS", 0 0, L_0x2bdff30; 1 drivers
+v0x23a0f10_0 .net "out0", 0 0, L_0x2bdfff0; 1 drivers
+v0x23a9330_0 .net "out1", 0 0, L_0x2be0100; 1 drivers
+v0x23a93b0_0 .alias "outfinal", 0 0, v0x23a8ba0_0;
+S_0x239dfb0 .scope generate, "andbits[13]" "andbits[13]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22a3978 .param/l "i" 3 231, +C4<01101>;
+S_0x239dd20 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x239dfb0;
+ .timescale -9 -12;
+L_0x2be0560/d .functor NAND 1, L_0x2be1000, L_0x2be0720, C4<1>, C4<1>;
+L_0x2be0560 .delay (10000,10000,10000) L_0x2be0560/d;
+L_0x2be08a0/d .functor NOT 1, L_0x2be0560, C4<0>, C4<0>, C4<0>;
+L_0x2be08a0 .delay (10000,10000,10000) L_0x2be08a0/d;
+v0x23a19b0_0 .net "A", 0 0, L_0x2be1000; 1 drivers
+v0x23a16a0_0 .net "AandB", 0 0, L_0x2be08a0; 1 drivers
+v0x23a1720_0 .net "AnandB", 0 0, L_0x2be0560; 1 drivers
+v0x23a1410_0 .net "AndNandOut", 0 0, L_0x2be0cf0; 1 drivers
+v0x23a1490_0 .net "B", 0 0, L_0x2be0720; 1 drivers
+v0x23a4df0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be0ec0 .part v0x2960210_0, 0, 1;
+S_0x23a36e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x239dd20;
+ .timescale -9 -12;
+L_0x2be09d0/d .functor NOT 1, L_0x2be0ec0, C4<0>, C4<0>, C4<0>;
+L_0x2be09d0 .delay (10000,10000,10000) L_0x2be09d0/d;
+L_0x2be0a90/d .functor AND 1, L_0x2be08a0, L_0x2be09d0, C4<1>, C4<1>;
+L_0x2be0a90 .delay (20000,20000,20000) L_0x2be0a90/d;
+L_0x2be0ba0/d .functor AND 1, L_0x2be0560, L_0x2be0ec0, C4<1>, C4<1>;
+L_0x2be0ba0 .delay (20000,20000,20000) L_0x2be0ba0/d;
+L_0x2be0cf0/d .functor OR 1, L_0x2be0a90, L_0x2be0ba0, C4<0>, C4<0>;
+L_0x2be0cf0 .delay (20000,20000,20000) L_0x2be0cf0/d;
+v0x23a3450_0 .net "S", 0 0, L_0x2be0ec0; 1 drivers
+v0x23a34d0_0 .alias "in0", 0 0, v0x23a16a0_0;
+v0x23a2ed0_0 .alias "in1", 0 0, v0x23a1720_0;
+v0x23a2f50_0 .net "nS", 0 0, L_0x2be09d0; 1 drivers
+v0x23a1bc0_0 .net "out0", 0 0, L_0x2be0a90; 1 drivers
+v0x23a1c40_0 .net "out1", 0 0, L_0x2be0ba0; 1 drivers
+v0x23a1930_0 .alias "outfinal", 0 0, v0x23a1410_0;
+S_0x2399360 .scope generate, "andbits[14]" "andbits[14]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22a84c8 .param/l "i" 3 231, +C4<01110>;
+S_0x2398450 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2399360;
+ .timescale -9 -12;
+L_0x2be11e0/d .functor NAND 1, L_0x2be10a0, L_0x2be1140, C4<1>, C4<1>;
+L_0x2be11e0 .delay (10000,10000,10000) L_0x2be11e0/d;
+L_0x2be1320/d .functor NOT 1, L_0x2be11e0, C4<0>, C4<0>, C4<0>;
+L_0x2be1320 .delay (10000,10000,10000) L_0x2be1320/d;
+v0x239f1a0_0 .net "A", 0 0, L_0x2be10a0; 1 drivers
+v0x239f240_0 .net "AandB", 0 0, L_0x2be1320; 1 drivers
+v0x239ef10_0 .net "AnandB", 0 0, L_0x2be11e0; 1 drivers
+v0x239ef90_0 .net "AndNandOut", 0 0, L_0x2be1750; 1 drivers
+v0x239ec50_0 .net "B", 0 0, L_0x2be1140; 1 drivers
+v0x239ecd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be1920 .part v0x2960210_0, 0, 1;
+S_0x23981c0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2398450;
+ .timescale -9 -12;
+L_0x2be1430/d .functor NOT 1, L_0x2be1920, C4<0>, C4<0>, C4<0>;
+L_0x2be1430 .delay (10000,10000,10000) L_0x2be1430/d;
+L_0x2be14f0/d .functor AND 1, L_0x2be1320, L_0x2be1430, C4<1>, C4<1>;
+L_0x2be14f0 .delay (20000,20000,20000) L_0x2be14f0/d;
+L_0x2be1600/d .functor AND 1, L_0x2be11e0, L_0x2be1920, C4<1>, C4<1>;
+L_0x2be1600 .delay (20000,20000,20000) L_0x2be1600/d;
+L_0x2be1750/d .functor OR 1, L_0x2be14f0, L_0x2be1600, C4<0>, C4<0>;
+L_0x2be1750 .delay (20000,20000,20000) L_0x2be1750/d;
+v0x2399670_0 .net "S", 0 0, L_0x2be1920; 1 drivers
+v0x239da90_0 .alias "in0", 0 0, v0x239f240_0;
+v0x239db10_0 .alias "in1", 0 0, v0x239ef10_0;
+v0x239bfc0_0 .net "nS", 0 0, L_0x2be1430; 1 drivers
+v0x239c040_0 .net "out0", 0 0, L_0x2be14f0; 1 drivers
+v0x239bd30_0 .net "out1", 0 0, L_0x2be1600; 1 drivers
+v0x239bdb0_0 .alias "outfinal", 0 0, v0x239ef90_0;
+S_0x2389fd0 .scope generate, "andbits[15]" "andbits[15]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22bce48 .param/l "i" 3 231, +C4<01111>;
+S_0x2390900 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2389fd0;
+ .timescale -9 -12;
+L_0x2be1a60/d .functor NAND 1, L_0x2be24f0, L_0x2be1c00, C4<1>, C4<1>;
+L_0x2be1a60 .delay (10000,10000,10000) L_0x2be1a60/d;
+L_0x2be1db0/d .functor NOT 1, L_0x2be1a60, C4<0>, C4<0>, C4<0>;
+L_0x2be1db0 .delay (10000,10000,10000) L_0x2be1db0/d;
+v0x23926e0_0 .net "A", 0 0, L_0x2be24f0; 1 drivers
+v0x2396460_0 .net "AandB", 0 0, L_0x2be1db0; 1 drivers
+v0x23964e0_0 .net "AnandB", 0 0, L_0x2be1a60; 1 drivers
+v0x23961d0_0 .net "AndNandOut", 0 0, L_0x2be21e0; 1 drivers
+v0x2396250_0 .net "B", 0 0, L_0x2be1c00; 1 drivers
+v0x23995f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be23b0 .part v0x2960210_0, 0, 1;
+S_0x2390670 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2390900;
+ .timescale -9 -12;
+L_0x2be1ec0/d .functor NOT 1, L_0x2be23b0, C4<0>, C4<0>, C4<0>;
+L_0x2be1ec0 .delay (10000,10000,10000) L_0x2be1ec0/d;
+L_0x2be1f80/d .functor AND 1, L_0x2be1db0, L_0x2be1ec0, C4<1>, C4<1>;
+L_0x2be1f80 .delay (20000,20000,20000) L_0x2be1f80/d;
+L_0x2be2090/d .functor AND 1, L_0x2be1a60, L_0x2be23b0, C4<1>, C4<1>;
+L_0x2be2090 .delay (20000,20000,20000) L_0x2be2090/d;
+L_0x2be21e0/d .functor OR 1, L_0x2be1f80, L_0x2be2090, C4<0>, C4<0>;
+L_0x2be21e0 .delay (20000,20000,20000) L_0x2be21e0/d;
+v0x2393a90_0 .net "S", 0 0, L_0x2be23b0; 1 drivers
+v0x2393b10_0 .alias "in0", 0 0, v0x2396460_0;
+v0x2393800_0 .alias "in1", 0 0, v0x23964e0_0;
+v0x2393880_0 .net "nS", 0 0, L_0x2be1ec0; 1 drivers
+v0x23928f0_0 .net "out0", 0 0, L_0x2be1f80; 1 drivers
+v0x2392970_0 .net "out1", 0 0, L_0x2be2090; 1 drivers
+v0x2392660_0 .alias "outfinal", 0 0, v0x23961d0_0;
+S_0x238ad00 .scope generate, "andbits[16]" "andbits[16]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22c6738 .param/l "i" 3 231, +C4<010000>;
+S_0x238aa70 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x238ad00;
+ .timescale -9 -12;
+L_0x2be1cf0/d .functor NAND 1, L_0x2be2590, L_0x2be2630, C4<1>, C4<1>;
+L_0x2be1cf0 .delay (10000,10000,10000) L_0x2be1cf0/d;
+L_0x2be2800/d .functor NOT 1, L_0x2be1cf0, C4<0>, C4<0>, C4<0>;
+L_0x2be2800 .delay (10000,10000,10000) L_0x2be2800/d;
+v0x238d9e0_0 .net "A", 0 0, L_0x2be2590; 1 drivers
+v0x238da80_0 .net "AandB", 0 0, L_0x2be2800; 1 drivers
+v0x238cd40_0 .net "AnandB", 0 0, L_0x2be1cf0; 1 drivers
+v0x238cdc0_0 .net "AndNandOut", 0 0, L_0x2be2c50; 1 drivers
+v0x238cab0_0 .net "B", 0 0, L_0x2be2630; 1 drivers
+v0x238cb30_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be2e20 .part v0x2960210_0, 0, 1;
+S_0x238a7e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x238aa70;
+ .timescale -9 -12;
+L_0x2be2930/d .functor NOT 1, L_0x2be2e20, C4<0>, C4<0>, C4<0>;
+L_0x2be2930 .delay (10000,10000,10000) L_0x2be2930/d;
+L_0x2be29f0/d .functor AND 1, L_0x2be2800, L_0x2be2930, C4<1>, C4<1>;
+L_0x2be29f0 .delay (20000,20000,20000) L_0x2be29f0/d;
+L_0x2be2b00/d .functor AND 1, L_0x2be1cf0, L_0x2be2e20, C4<1>, C4<1>;
+L_0x2be2b00 .delay (20000,20000,20000) L_0x2be2b00/d;
+L_0x2be2c50/d .functor OR 1, L_0x2be29f0, L_0x2be2b00, C4<0>, C4<0>;
+L_0x2be2c50 .delay (20000,20000,20000) L_0x2be2c50/d;
+v0x238c090_0 .net "S", 0 0, L_0x2be2e20; 1 drivers
+v0x238a550_0 .alias "in0", 0 0, v0x238da80_0;
+v0x238a5d0_0 .alias "in1", 0 0, v0x238cd40_0;
+v0x238df30_0 .net "nS", 0 0, L_0x2be2930; 1 drivers
+v0x238dfb0_0 .net "out0", 0 0, L_0x2be29f0; 1 drivers
+v0x238dca0_0 .net "out1", 0 0, L_0x2be2b00; 1 drivers
+v0x238dd20_0 .alias "outfinal", 0 0, v0x238cdc0_0;
+S_0x2384900 .scope generate, "andbits[17]" "andbits[17]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22cb288 .param/l "i" 3 231, +C4<010001>;
+S_0x23882e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2384900;
+ .timescale -9 -12;
+L_0x2be2f60/d .functor NAND 1, L_0x2be3a00, L_0x2be3130, C4<1>, C4<1>;
+L_0x2be2f60 .delay (10000,10000,10000) L_0x2be2f60/d;
+L_0x2be32c0/d .functor NOT 1, L_0x2be2f60, C4<0>, C4<0>, C4<0>;
+L_0x2be32c0 .delay (10000,10000,10000) L_0x2be32c0/d;
+v0x2384400_0 .net "A", 0 0, L_0x2be3a00; 1 drivers
+v0x238c820_0 .net "AandB", 0 0, L_0x2be32c0; 1 drivers
+v0x238c8a0_0 .net "AnandB", 0 0, L_0x2be2f60; 1 drivers
+v0x238c590_0 .net "AndNandOut", 0 0, L_0x2be36f0; 1 drivers
+v0x238c610_0 .net "B", 0 0, L_0x2be3130; 1 drivers
+v0x238c010_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be38c0 .part v0x2960210_0, 0, 1;
+S_0x2388050 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x23882e0;
+ .timescale -9 -12;
+L_0x2be33d0/d .functor NOT 1, L_0x2be38c0, C4<0>, C4<0>, C4<0>;
+L_0x2be33d0 .delay (10000,10000,10000) L_0x2be33d0/d;
+L_0x2be3490/d .functor AND 1, L_0x2be32c0, L_0x2be33d0, C4<1>, C4<1>;
+L_0x2be3490 .delay (20000,20000,20000) L_0x2be3490/d;
+L_0x2be35a0/d .functor AND 1, L_0x2be2f60, L_0x2be38c0, C4<1>, C4<1>;
+L_0x2be35a0 .delay (20000,20000,20000) L_0x2be35a0/d;
+L_0x2be36f0/d .functor OR 1, L_0x2be3490, L_0x2be35a0, C4<0>, C4<0>;
+L_0x2be36f0 .delay (20000,20000,20000) L_0x2be36f0/d;
+v0x2387d90_0 .net "S", 0 0, L_0x2be38c0; 1 drivers
+v0x2387e10_0 .alias "in0", 0 0, v0x238c820_0;
+v0x23870f0_0 .alias "in1", 0 0, v0x238c8a0_0;
+v0x2387170_0 .net "nS", 0 0, L_0x2be33d0; 1 drivers
+v0x2386e60_0 .net "out0", 0 0, L_0x2be3490; 1 drivers
+v0x2386ee0_0 .net "out1", 0 0, L_0x2be35a0; 1 drivers
+v0x2384380_0 .alias "outfinal", 0 0, v0x238c590_0;
+S_0x23814a0 .scope generate, "andbits[18]" "andbits[18]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22cdfa8 .param/l "i" 3 231, +C4<010010>;
+S_0x2381210 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23814a0;
+ .timescale -9 -12;
+L_0x2be3220/d .functor NAND 1, L_0x2be3aa0, L_0x2be3b40, C4<1>, C4<1>;
+L_0x2be3220 .delay (10000,10000,10000) L_0x2be3220/d;
+L_0x2be3d20/d .functor NOT 1, L_0x2be3220, C4<0>, C4<0>, C4<0>;
+L_0x2be3d20 .delay (10000,10000,10000) L_0x2be3d20/d;
+v0x23850b0_0 .net "A", 0 0, L_0x2be3aa0; 1 drivers
+v0x2385150_0 .net "AandB", 0 0, L_0x2be3d20; 1 drivers
+v0x2384e20_0 .net "AnandB", 0 0, L_0x2be3220; 1 drivers
+v0x2384ea0_0 .net "AndNandOut", 0 0, L_0x2be4150; 1 drivers
+v0x2384b90_0 .net "B", 0 0, L_0x2be3b40; 1 drivers
+v0x2384c10_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be4320 .part v0x2960210_0, 0, 1;
+S_0x237e730 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2381210;
+ .timescale -9 -12;
+L_0x2be3e30/d .functor NOT 1, L_0x2be4320, C4<0>, C4<0>, C4<0>;
+L_0x2be3e30 .delay (10000,10000,10000) L_0x2be3e30/d;
+L_0x2be3ef0/d .functor AND 1, L_0x2be3d20, L_0x2be3e30, C4<1>, C4<1>;
+L_0x2be3ef0 .delay (20000,20000,20000) L_0x2be3ef0/d;
+L_0x2be4000/d .functor AND 1, L_0x2be3220, L_0x2be4320, C4<1>, C4<1>;
+L_0x2be4000 .delay (20000,20000,20000) L_0x2be4000/d;
+L_0x2be4150/d .functor OR 1, L_0x2be3ef0, L_0x2be4000, C4<0>, C4<0>;
+L_0x2be4150 .delay (20000,20000,20000) L_0x2be4150/d;
+v0x23821c0_0 .net "S", 0 0, L_0x2be4320; 1 drivers
+v0x2386bd0_0 .alias "in0", 0 0, v0x2385150_0;
+v0x2386c50_0 .alias "in1", 0 0, v0x2384e20_0;
+v0x2386940_0 .net "nS", 0 0, L_0x2be3e30; 1 drivers
+v0x23869c0_0 .net "out0", 0 0, L_0x2be3ef0; 1 drivers
+v0x23863c0_0 .net "out1", 0 0, L_0x2be4000; 1 drivers
+v0x2386440_0 .alias "outfinal", 0 0, v0x2384ea0_0;
+S_0x2380f80 .scope generate, "andbits[19]" "andbits[19]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22dd928 .param/l "i" 3 231, +C4<010011>;
+S_0x2380cf0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2380f80;
+ .timescale -9 -12;
+L_0x2be4620/d .functor NAND 1, L_0x2be4f00, L_0x2be4460, C4<1>, C4<1>;
+L_0x2be4620 .delay (10000,10000,10000) L_0x2be4620/d;
+L_0x2be47a0/d .functor NOT 1, L_0x2be4620, C4<0>, C4<0>, C4<0>;
+L_0x2be47a0 .delay (10000,10000,10000) L_0x2be47a0/d;
+v0x237ed30_0 .net "A", 0 0, L_0x2be4f00; 1 drivers
+v0x2382690_0 .net "AandB", 0 0, L_0x2be47a0; 1 drivers
+v0x2382710_0 .net "AnandB", 0 0, L_0x2be4620; 1 drivers
+v0x2382400_0 .net "AndNandOut", 0 0, L_0x2be4bf0; 1 drivers
+v0x2382480_0 .net "B", 0 0, L_0x2be4460; 1 drivers
+v0x2382140_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be4dc0 .part v0x2960210_0, 0, 1;
+S_0x2380770 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2380cf0;
+ .timescale -9 -12;
+L_0x2be48d0/d .functor NOT 1, L_0x2be4dc0, C4<0>, C4<0>, C4<0>;
+L_0x2be48d0 .delay (10000,10000,10000) L_0x2be48d0/d;
+L_0x2be4990/d .functor AND 1, L_0x2be47a0, L_0x2be48d0, C4<1>, C4<1>;
+L_0x2be4990 .delay (20000,20000,20000) L_0x2be4990/d;
+L_0x2be4aa0/d .functor AND 1, L_0x2be4620, L_0x2be4dc0, C4<1>, C4<1>;
+L_0x2be4aa0 .delay (20000,20000,20000) L_0x2be4aa0/d;
+L_0x2be4bf0/d .functor OR 1, L_0x2be4990, L_0x2be4aa0, C4<0>, C4<0>;
+L_0x2be4bf0 .delay (20000,20000,20000) L_0x2be4bf0/d;
+v0x237f460_0 .net "S", 0 0, L_0x2be4dc0; 1 drivers
+v0x237f4e0_0 .alias "in0", 0 0, v0x2382690_0;
+v0x237f1d0_0 .alias "in1", 0 0, v0x2382710_0;
+v0x237f250_0 .net "nS", 0 0, L_0x2be48d0; 1 drivers
+v0x237ef40_0 .net "out0", 0 0, L_0x2be4990; 1 drivers
+v0x237efc0_0 .net "out1", 0 0, L_0x2be4aa0; 1 drivers
+v0x237ecb0_0 .alias "outfinal", 0 0, v0x2382400_0;
+S_0x2376c40 .scope generate, "andbits[20]" "andbits[20]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22e0648 .param/l "i" 3 231, +C4<010100>;
+S_0x2375d30 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2376c40;
+ .timescale -9 -12;
+L_0x2be4550/d .functor NAND 1, L_0x2be4fa0, L_0x2be5040, C4<1>, C4<1>;
+L_0x2be4550 .delay (10000,10000,10000) L_0x2be4550/d;
+L_0x2be5200/d .functor NOT 1, L_0x2be4550, C4<0>, C4<0>, C4<0>;
+L_0x2be5200 .delay (10000,10000,10000) L_0x2be5200/d;
+v0x237c7a0_0 .net "A", 0 0, L_0x2be4fa0; 1 drivers
+v0x237c840_0 .net "AandB", 0 0, L_0x2be5200; 1 drivers
+v0x237b890_0 .net "AnandB", 0 0, L_0x2be4550; 1 drivers
+v0x237b910_0 .net "AndNandOut", 0 0, L_0x2be5650; 1 drivers
+v0x237b600_0 .net "B", 0 0, L_0x2be5040; 1 drivers
+v0x237b680_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be5820 .part v0x2960210_0, 0, 1;
+S_0x2375aa0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2375d30;
+ .timescale -9 -12;
+L_0x2be5330/d .functor NOT 1, L_0x2be5820, C4<0>, C4<0>, C4<0>;
+L_0x2be5330 .delay (10000,10000,10000) L_0x2be5330/d;
+L_0x2be53f0/d .functor AND 1, L_0x2be5200, L_0x2be5330, C4<1>, C4<1>;
+L_0x2be53f0 .delay (20000,20000,20000) L_0x2be53f0/d;
+L_0x2be5500/d .functor AND 1, L_0x2be4550, L_0x2be5820, C4<1>, C4<1>;
+L_0x2be5500 .delay (20000,20000,20000) L_0x2be5500/d;
+L_0x2be5650/d .functor OR 1, L_0x2be53f0, L_0x2be5500, C4<0>, C4<0>;
+L_0x2be5650 .delay (20000,20000,20000) L_0x2be5650/d;
+v0x2376f50_0 .net "S", 0 0, L_0x2be5820; 1 drivers
+v0x23798a0_0 .alias "in0", 0 0, v0x237c840_0;
+v0x2379920_0 .alias "in1", 0 0, v0x237b890_0;
+v0x2379610_0 .net "nS", 0 0, L_0x2be5330; 1 drivers
+v0x2379690_0 .net "out0", 0 0, L_0x2be53f0; 1 drivers
+v0x237ca30_0 .net "out1", 0 0, L_0x2be5500; 1 drivers
+v0x237cab0_0 .alias "outfinal", 0 0, v0x237b910_0;
+S_0x23676f0 .scope generate, "andbits[21]" "andbits[21]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22e5198 .param/l "i" 3 231, +C4<010101>;
+S_0x236e1e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x23676f0;
+ .timescale -9 -12;
+L_0x2be5b50/d .functor NAND 1, L_0x2be62f0, L_0x2be5960, C4<1>, C4<1>;
+L_0x2be5b50 .delay (10000,10000,10000) L_0x2be5b50/d;
+L_0x2be5c90/d .functor NOT 1, L_0x2be5b50, C4<0>, C4<0>, C4<0>;
+L_0x2be5c90 .delay (10000,10000,10000) L_0x2be5c90/d;
+v0x236ffc0_0 .net "A", 0 0, L_0x2be62f0; 1 drivers
+v0x2373d40_0 .net "AandB", 0 0, L_0x2be5c90; 1 drivers
+v0x2373dc0_0 .net "AnandB", 0 0, L_0x2be5b50; 1 drivers
+v0x2373ab0_0 .net "AndNandOut", 0 0, L_0x2bdbba0; 1 drivers
+v0x2373b30_0 .net "B", 0 0, L_0x2be5960; 1 drivers
+v0x2376ed0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be61b0 .part v0x2960210_0, 0, 1;
+S_0x236df50 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x236e1e0;
+ .timescale -9 -12;
+L_0x2be5dc0/d .functor NOT 1, L_0x2be61b0, C4<0>, C4<0>, C4<0>;
+L_0x2be5dc0 .delay (10000,10000,10000) L_0x2be5dc0/d;
+L_0x2be5e80/d .functor AND 1, L_0x2be5c90, L_0x2be5dc0, C4<1>, C4<1>;
+L_0x2be5e80 .delay (20000,20000,20000) L_0x2be5e80/d;
+L_0x2be5f90/d .functor AND 1, L_0x2be5b50, L_0x2be61b0, C4<1>, C4<1>;
+L_0x2be5f90 .delay (20000,20000,20000) L_0x2be5f90/d;
+L_0x2bdbba0/d .functor OR 1, L_0x2be5e80, L_0x2be5f90, C4<0>, C4<0>;
+L_0x2bdbba0 .delay (20000,20000,20000) L_0x2bdbba0/d;
+v0x2371370_0 .net "S", 0 0, L_0x2be61b0; 1 drivers
+v0x23713f0_0 .alias "in0", 0 0, v0x2373d40_0;
+v0x23710e0_0 .alias "in1", 0 0, v0x2373dc0_0;
+v0x2371160_0 .net "nS", 0 0, L_0x2be5dc0; 1 drivers
+v0x23701d0_0 .net "out0", 0 0, L_0x2be5e80; 1 drivers
+v0x2370250_0 .net "out1", 0 0, L_0x2be5f90; 1 drivers
+v0x236ff40_0 .alias "outfinal", 0 0, v0x2373ab0_0;
+S_0x2369800 .scope generate, "andbits[22]" "andbits[22]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22e9ce8 .param/l "i" 3 231, +C4<010110>;
+S_0x2368480 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2369800;
+ .timescale -9 -12;
+L_0x2be5a50/d .functor NAND 1, L_0x2be6390, L_0x2be6430, C4<1>, C4<1>;
+L_0x2be5a50 .delay (10000,10000,10000) L_0x2be5a50/d;
+L_0x2be6620/d .functor NOT 1, L_0x2be5a50, C4<0>, C4<0>, C4<0>;
+L_0x2be6620 .delay (10000,10000,10000) L_0x2be6620/d;
+v0x236b500_0 .net "A", 0 0, L_0x2be6390; 1 drivers
+v0x236b5a0_0 .net "AandB", 0 0, L_0x2be6620; 1 drivers
+v0x236a560_0 .net "AnandB", 0 0, L_0x2be5a50; 1 drivers
+v0x236a5e0_0 .net "AndNandOut", 0 0, L_0x2be69d0; 1 drivers
+v0x236a2d0_0 .net "B", 0 0, L_0x2be6430; 1 drivers
+v0x236a350_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be6b60 .part v0x2960210_0, 0, 1;
+S_0x23681c0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2368480;
+ .timescale -9 -12;
+L_0x2be6710/d .functor NOT 1, L_0x2be6b60, C4<0>, C4<0>, C4<0>;
+L_0x2be6710 .delay (10000,10000,10000) L_0x2be6710/d;
+L_0x2be67b0/d .functor AND 1, L_0x2be6620, L_0x2be6710, C4<1>, C4<1>;
+L_0x2be67b0 .delay (20000,20000,20000) L_0x2be67b0/d;
+L_0x2be68a0/d .functor AND 1, L_0x2be5a50, L_0x2be6b60, C4<1>, C4<1>;
+L_0x2be68a0 .delay (20000,20000,20000) L_0x2be68a0/d;
+L_0x2be69d0/d .functor OR 1, L_0x2be67b0, L_0x2be68a0, C4<0>, C4<0>;
+L_0x2be69d0 .delay (20000,20000,20000) L_0x2be69d0/d;
+v0x2369e00_0 .net "S", 0 0, L_0x2be6b60; 1 drivers
+v0x2367f30_0 .alias "in0", 0 0, v0x236b5a0_0;
+v0x2367fb0_0 .alias "in1", 0 0, v0x236a560_0;
+v0x2367c70_0 .net "nS", 0 0, L_0x2be6710; 1 drivers
+v0x2367cf0_0 .net "out0", 0 0, L_0x2be67b0; 1 drivers
+v0x236b790_0 .net "out1", 0 0, L_0x2be68a0; 1 drivers
+v0x236b810_0 .alias "outfinal", 0 0, v0x236a5e0_0;
+S_0x2580300 .scope generate, "andbits[23]" "andbits[23]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x230f998 .param/l "i" 3 231, +C4<010111>;
+S_0x257f410 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2580300;
+ .timescale -9 -12;
+L_0x2be6520/d .functor NAND 1, L_0x2be7620, L_0x2be6ca0, C4<1>, C4<1>;
+L_0x2be6520 .delay (10000,10000,10000) L_0x2be6520/d;
+L_0x2be6fa0/d .functor NOT 1, L_0x2be6520, C4<0>, C4<0>, C4<0>;
+L_0x2be6fa0 .delay (10000,10000,10000) L_0x2be6fa0/d;
+v0x2584da0_0 .net "A", 0 0, L_0x2be7620; 1 drivers
+v0x2583e50_0 .net "AandB", 0 0, L_0x2be6fa0; 1 drivers
+v0x2583ed0_0 .net "AnandB", 0 0, L_0x2be6520; 1 drivers
+v0x236a040_0 .net "AndNandOut", 0 0, L_0x2be7350; 1 drivers
+v0x236a0c0_0 .net "B", 0 0, L_0x2be6ca0; 1 drivers
+v0x2369d80_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be74e0 .part v0x2960210_0, 0, 1;
+S_0x2582aa0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x257f410;
+ .timescale -9 -12;
+L_0x2be7090/d .functor NOT 1, L_0x2be74e0, C4<0>, C4<0>, C4<0>;
+L_0x2be7090 .delay (10000,10000,10000) L_0x2be7090/d;
+L_0x2be7130/d .functor AND 1, L_0x2be6fa0, L_0x2be7090, C4<1>, C4<1>;
+L_0x2be7130 .delay (20000,20000,20000) L_0x2be7130/d;
+L_0x2be7220/d .functor AND 1, L_0x2be6520, L_0x2be74e0, C4<1>, C4<1>;
+L_0x2be7220 .delay (20000,20000,20000) L_0x2be7220/d;
+L_0x2be7350/d .functor OR 1, L_0x2be7130, L_0x2be7220, C4<0>, C4<0>;
+L_0x2be7350 .delay (20000,20000,20000) L_0x2be7350/d;
+v0x2582820_0 .net "S", 0 0, L_0x2be74e0; 1 drivers
+v0x25828a0_0 .alias "in0", 0 0, v0x2583e50_0;
+v0x2581920_0 .alias "in1", 0 0, v0x2583ed0_0;
+v0x25819a0_0 .net "nS", 0 0, L_0x2be7090; 1 drivers
+v0x2584fa0_0 .net "out0", 0 0, L_0x2be7130; 1 drivers
+v0x2585020_0 .net "out1", 0 0, L_0x2be7220; 1 drivers
+v0x2584d20_0 .alias "outfinal", 0 0, v0x236a040_0;
+S_0x25793d0 .scope generate, "andbits[24]" "andbits[24]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22f9138 .param/l "i" 3 231, +C4<011000>;
+S_0x25784e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x25793d0;
+ .timescale -9 -12;
+L_0x2be6d90/d .functor NAND 1, L_0x2be76c0, L_0x2be7760, C4<1>, C4<1>;
+L_0x2be6d90 .delay (10000,10000,10000) L_0x2be6d90/d;
+L_0x2be7940/d .functor NOT 1, L_0x2be6d90, C4<0>, C4<0>, C4<0>;
+L_0x2be7940 .delay (10000,10000,10000) L_0x2be7940/d;
+v0x257ddf0_0 .net "A", 0 0, L_0x2be76c0; 1 drivers
+v0x257de90_0 .net "AandB", 0 0, L_0x2be7940; 1 drivers
+v0x257cf00_0 .net "AnandB", 0 0, L_0x2be6d90; 1 drivers
+v0x257cf80_0 .net "AndNandOut", 0 0, L_0x2be7cf0; 1 drivers
+v0x2580580_0 .net "B", 0 0, L_0x2be7760; 1 drivers
+v0x2580600_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be7e80 .part v0x2960210_0, 0, 1;
+S_0x257bb60 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x25784e0;
+ .timescale -9 -12;
+L_0x2be7a30/d .functor NOT 1, L_0x2be7e80, C4<0>, C4<0>, C4<0>;
+L_0x2be7a30 .delay (10000,10000,10000) L_0x2be7a30/d;
+L_0x2be7ad0/d .functor AND 1, L_0x2be7940, L_0x2be7a30, C4<1>, C4<1>;
+L_0x2be7ad0 .delay (20000,20000,20000) L_0x2be7ad0/d;
+L_0x2be7bc0/d .functor AND 1, L_0x2be6d90, L_0x2be7e80, C4<1>, C4<1>;
+L_0x2be7bc0 .delay (20000,20000,20000) L_0x2be7bc0/d;
+L_0x2be7cf0/d .functor OR 1, L_0x2be7ad0, L_0x2be7bc0, C4<0>, C4<0>;
+L_0x2be7cf0 .delay (20000,20000,20000) L_0x2be7cf0/d;
+v0x25796d0_0 .net "S", 0 0, L_0x2be7e80; 1 drivers
+v0x257b8e0_0 .alias "in0", 0 0, v0x257de90_0;
+v0x257b960_0 .alias "in1", 0 0, v0x257cf00_0;
+v0x257a9f0_0 .net "nS", 0 0, L_0x2be7a30; 1 drivers
+v0x257aa70_0 .net "out0", 0 0, L_0x2be7ad0; 1 drivers
+v0x257e070_0 .net "out1", 0 0, L_0x2be7bc0; 1 drivers
+v0x257e0f0_0 .alias "outfinal", 0 0, v0x257cf80_0;
+S_0x2572720 .scope generate, "andbits[25]" "andbits[25]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2318d78 .param/l "i" 3 231, +C4<011001>;
+S_0x25724a0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2572720;
+ .timescale -9 -12;
+L_0x2be7850/d .functor NAND 1, L_0x2be8930, L_0x2be7fc0, C4<1>, C4<1>;
+L_0x2be7850 .delay (10000,10000,10000) L_0x2be7850/d;
+L_0x2be82b0/d .functor NOT 1, L_0x2be7850, C4<0>, C4<0>, C4<0>;
+L_0x2be82b0 .delay (10000,10000,10000) L_0x2be82b0/d;
+v0x25771c0_0 .net "A", 0 0, L_0x2be8930; 1 drivers
+v0x2576ec0_0 .net "AandB", 0 0, L_0x2be82b0; 1 drivers
+v0x2576f40_0 .net "AnandB", 0 0, L_0x2be7850; 1 drivers
+v0x2575fd0_0 .net "AndNandOut", 0 0, L_0x2be8660; 1 drivers
+v0x2576050_0 .net "B", 0 0, L_0x2be7fc0; 1 drivers
+v0x2579650_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be87f0 .part v0x2960210_0, 0, 1;
+S_0x25715e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x25724a0;
+ .timescale -9 -12;
+L_0x2be83a0/d .functor NOT 1, L_0x2be87f0, C4<0>, C4<0>, C4<0>;
+L_0x2be83a0 .delay (10000,10000,10000) L_0x2be83a0/d;
+L_0x2be8440/d .functor AND 1, L_0x2be82b0, L_0x2be83a0, C4<1>, C4<1>;
+L_0x2be8440 .delay (20000,20000,20000) L_0x2be8440/d;
+L_0x2be8530/d .functor AND 1, L_0x2be7850, L_0x2be87f0, C4<1>, C4<1>;
+L_0x2be8530 .delay (20000,20000,20000) L_0x2be8530/d;
+L_0x2be8660/d .functor OR 1, L_0x2be8440, L_0x2be8530, C4<0>, C4<0>;
+L_0x2be8660 .delay (20000,20000,20000) L_0x2be8660/d;
+v0x2574c30_0 .net "S", 0 0, L_0x2be87f0; 1 drivers
+v0x2574cb0_0 .alias "in0", 0 0, v0x2576ec0_0;
+v0x25749b0_0 .alias "in1", 0 0, v0x2576f40_0;
+v0x2574a30_0 .net "nS", 0 0, L_0x2be83a0; 1 drivers
+v0x2573ac0_0 .net "out0", 0 0, L_0x2be8440; 1 drivers
+v0x2573b40_0 .net "out1", 0 0, L_0x2be8530; 1 drivers
+v0x2577140_0 .alias "outfinal", 0 0, v0x2575fd0_0;
+S_0x256b830 .scope generate, "andbits[26]" "andbits[26]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x22fbec8 .param/l "i" 3 231, +C4<011010>;
+S_0x256b5b0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x256b830;
+ .timescale -9 -12;
+L_0x2be80b0/d .functor NAND 1, L_0x2be89d0, L_0x2be8a70, C4<1>, C4<1>;
+L_0x2be80b0 .delay (10000,10000,10000) L_0x2be80b0/d;
+L_0x2be8c30/d .functor NOT 1, L_0x2be80b0, C4<0>, C4<0>, C4<0>;
+L_0x2be8c30 .delay (10000,10000,10000) L_0x2be8c30/d;
+v0x2570230_0 .net "A", 0 0, L_0x2be89d0; 1 drivers
+v0x25702d0_0 .net "AandB", 0 0, L_0x2be8c30; 1 drivers
+v0x256ffb0_0 .net "AnandB", 0 0, L_0x2be80b0; 1 drivers
+v0x2570030_0 .net "AndNandOut", 0 0, L_0x2be8fe0; 1 drivers
+v0x256f0e0_0 .net "B", 0 0, L_0x2be8a70; 1 drivers
+v0x256f160_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be9170 .part v0x2960210_0, 0, 1;
+S_0x256a6e0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x256b5b0;
+ .timescale -9 -12;
+L_0x2be8d20/d .functor NOT 1, L_0x2be9170, C4<0>, C4<0>, C4<0>;
+L_0x2be8d20 .delay (10000,10000,10000) L_0x2be8d20/d;
+L_0x2be8dc0/d .functor AND 1, L_0x2be8c30, L_0x2be8d20, C4<1>, C4<1>;
+L_0x2be8dc0 .delay (20000,20000,20000) L_0x2be8dc0/d;
+L_0x2be8eb0/d .functor AND 1, L_0x2be80b0, L_0x2be9170, C4<1>, C4<1>;
+L_0x2be8eb0 .delay (20000,20000,20000) L_0x2be8eb0/d;
+L_0x2be8fe0/d .functor OR 1, L_0x2be8dc0, L_0x2be8eb0, C4<0>, C4<0>;
+L_0x2be8fe0 .delay (20000,20000,20000) L_0x2be8fe0/d;
+v0x2568260_0 .net "S", 0 0, L_0x2be9170; 1 drivers
+v0x256dd30_0 .alias "in0", 0 0, v0x25702d0_0;
+v0x256ddb0_0 .alias "in1", 0 0, v0x256ffb0_0;
+v0x256dab0_0 .net "nS", 0 0, L_0x2be8d20; 1 drivers
+v0x256db30_0 .net "out0", 0 0, L_0x2be8dc0; 1 drivers
+v0x256cbe0_0 .net "out1", 0 0, L_0x2be8eb0; 1 drivers
+v0x256cc60_0 .alias "outfinal", 0 0, v0x2570030_0;
+S_0x25612b0 .scope generate, "andbits[27]" "andbits[27]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x2400f08 .param/l "i" 3 231, +C4<011011>;
+S_0x2564930 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x25612b0;
+ .timescale -9 -12;
+L_0x2be8b60/d .functor NAND 1, L_0x2be9c40, L_0x2be92b0, C4<1>, C4<1>;
+L_0x2be8b60 .delay (10000,10000,10000) L_0x2be8b60/d;
+L_0x2be95c0/d .functor NOT 1, L_0x2be8b60, C4<0>, C4<0>, C4<0>;
+L_0x2be95c0 .delay (10000,10000,10000) L_0x2be95c0/d;
+v0x2565d60_0 .net "A", 0 0, L_0x2be9c40; 1 drivers
+v0x2569330_0 .net "AandB", 0 0, L_0x2be95c0; 1 drivers
+v0x25693b0_0 .net "AnandB", 0 0, L_0x2be8b60; 1 drivers
+v0x25690b0_0 .net "AndNandOut", 0 0, L_0x2be9970; 1 drivers
+v0x2569130_0 .net "B", 0 0, L_0x2be92b0; 1 drivers
+v0x25681e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2be9b00 .part v0x2960210_0, 0, 1;
+S_0x25646b0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2564930;
+ .timescale -9 -12;
+L_0x2be96b0/d .functor NOT 1, L_0x2be9b00, C4<0>, C4<0>, C4<0>;
+L_0x2be96b0 .delay (10000,10000,10000) L_0x2be96b0/d;
+L_0x2be9750/d .functor AND 1, L_0x2be95c0, L_0x2be96b0, C4<1>, C4<1>;
+L_0x2be9750 .delay (20000,20000,20000) L_0x2be9750/d;
+L_0x2be9840/d .functor AND 1, L_0x2be8b60, L_0x2be9b00, C4<1>, C4<1>;
+L_0x2be9840 .delay (20000,20000,20000) L_0x2be9840/d;
+L_0x2be9970/d .functor OR 1, L_0x2be9750, L_0x2be9840, C4<0>, C4<0>;
+L_0x2be9970 .delay (20000,20000,20000) L_0x2be9970/d;
+v0x25637e0_0 .net "S", 0 0, L_0x2be9b00; 1 drivers
+v0x2563860_0 .alias "in0", 0 0, v0x2569330_0;
+v0x2566e30_0 .alias "in1", 0 0, v0x25693b0_0;
+v0x2566eb0_0 .net "nS", 0 0, L_0x2be96b0; 1 drivers
+v0x2566bb0_0 .net "out0", 0 0, L_0x2be9750; 1 drivers
+v0x2566c30_0 .net "out1", 0 0, L_0x2be9840; 1 drivers
+v0x2565ce0_0 .alias "outfinal", 0 0, v0x25690b0_0;
+S_0x255a380 .scope generate, "andbits[28]" "andbits[28]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x23c1028 .param/l "i" 3 231, +C4<011100>;
+S_0x255da00 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x255a380;
+ .timescale -9 -12;
+L_0x2be93a0/d .functor NAND 1, L_0x2be9ce0, L_0x2be9d80, C4<1>, C4<1>;
+L_0x2be93a0 .delay (10000,10000,10000) L_0x2be93a0/d;
+L_0x2be9f70/d .functor NOT 1, L_0x2be93a0, C4<0>, C4<0>, C4<0>;
+L_0x2be9f70 .delay (10000,10000,10000) L_0x2be9f70/d;
+v0x255eda0_0 .net "A", 0 0, L_0x2be9ce0; 1 drivers
+v0x255ee40_0 .net "AandB", 0 0, L_0x2be9f70; 1 drivers
+v0x2562430_0 .net "AnandB", 0 0, L_0x2be93a0; 1 drivers
+v0x25624b0_0 .net "AndNandOut", 0 0, L_0x2bea340; 1 drivers
+v0x25621b0_0 .net "B", 0 0, L_0x2be9d80; 1 drivers
+v0x2562230_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bea510 .part v0x2960210_0, 0, 1;
+S_0x255d780 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x255da00;
+ .timescale -9 -12;
+L_0x2bea060/d .functor NOT 1, L_0x2bea510, C4<0>, C4<0>, C4<0>;
+L_0x2bea060 .delay (10000,10000,10000) L_0x2bea060/d;
+L_0x2bea100/d .functor AND 1, L_0x2be9f70, L_0x2bea060, C4<1>, C4<1>;
+L_0x2bea100 .delay (20000,20000,20000) L_0x2bea100/d;
+L_0x2bea1f0/d .functor AND 1, L_0x2be93a0, L_0x2bea510, C4<1>, C4<1>;
+L_0x2bea1f0 .delay (20000,20000,20000) L_0x2bea1f0/d;
+L_0x2bea340/d .functor OR 1, L_0x2bea100, L_0x2bea1f0, C4<0>, C4<0>;
+L_0x2bea340 .delay (20000,20000,20000) L_0x2bea340/d;
+v0x255b2f0_0 .net "S", 0 0, L_0x2bea510; 1 drivers
+v0x255c890_0 .alias "in0", 0 0, v0x255ee40_0;
+v0x255c910_0 .alias "in1", 0 0, v0x2562430_0;
+v0x255ff10_0 .net "nS", 0 0, L_0x2bea060; 1 drivers
+v0x255ff90_0 .net "out0", 0 0, L_0x2bea100; 1 drivers
+v0x255fc90_0 .net "out1", 0 0, L_0x2bea1f0; 1 drivers
+v0x255fd10_0 .alias "outfinal", 0 0, v0x25624b0_0;
+S_0x2554340 .scope generate, "andbits[29]" "andbits[29]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x238d688 .param/l "i" 3 231, +C4<011101>;
+S_0x2553450 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2554340;
+ .timescale -9 -12;
+L_0x2be9e70/d .functor NAND 1, L_0x2beb0f0, L_0x2bea650, C4<1>, C4<1>;
+L_0x2be9e70 .delay (10000,10000,10000) L_0x2be9e70/d;
+L_0x2bea990/d .functor NOT 1, L_0x2be9e70, C4<0>, C4<0>, C4<0>;
+L_0x2bea990 .delay (10000,10000,10000) L_0x2bea990/d;
+v0x2558de0_0 .net "A", 0 0, L_0x2beb0f0; 1 drivers
+v0x2557e70_0 .net "AandB", 0 0, L_0x2bea990; 1 drivers
+v0x2557ef0_0 .net "AnandB", 0 0, L_0x2be9e70; 1 drivers
+v0x255b4f0_0 .net "AndNandOut", 0 0, L_0x2beade0; 1 drivers
+v0x255b570_0 .net "B", 0 0, L_0x2bea650; 1 drivers
+v0x255b270_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2beafb0 .part v0x2960210_0, 0, 1;
+S_0x2556ad0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x2553450;
+ .timescale -9 -12;
+L_0x2beaac0/d .functor NOT 1, L_0x2beafb0, C4<0>, C4<0>, C4<0>;
+L_0x2beaac0 .delay (10000,10000,10000) L_0x2beaac0/d;
+L_0x2beab80/d .functor AND 1, L_0x2bea990, L_0x2beaac0, C4<1>, C4<1>;
+L_0x2beab80 .delay (20000,20000,20000) L_0x2beab80/d;
+L_0x2beac90/d .functor AND 1, L_0x2be9e70, L_0x2beafb0, C4<1>, C4<1>;
+L_0x2beac90 .delay (20000,20000,20000) L_0x2beac90/d;
+L_0x2beade0/d .functor OR 1, L_0x2beab80, L_0x2beac90, C4<0>, C4<0>;
+L_0x2beade0 .delay (20000,20000,20000) L_0x2beade0/d;
+v0x2556850_0 .net "S", 0 0, L_0x2beafb0; 1 drivers
+v0x25568d0_0 .alias "in0", 0 0, v0x2557e70_0;
+v0x2555960_0 .alias "in1", 0 0, v0x2557ef0_0;
+v0x25559e0_0 .net "nS", 0 0, L_0x2beaac0; 1 drivers
+v0x2558fe0_0 .net "out0", 0 0, L_0x2beab80; 1 drivers
+v0x2559060_0 .net "out1", 0 0, L_0x2beac90; 1 drivers
+v0x2558d60_0 .alias "outfinal", 0 0, v0x255b4f0_0;
+S_0x254d410 .scope generate, "andbits[30]" "andbits[30]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x1f6b408 .param/l "i" 3 231, +C4<011110>;
+S_0x254c580 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x254d410;
+ .timescale -9 -12;
+L_0x2bea740/d .functor NAND 1, L_0x2beb190, L_0x2beb230, C4<1>, C4<1>;
+L_0x2bea740 .delay (10000,10000,10000) L_0x2bea740/d;
+L_0x2bea8a0/d .functor NOT 1, L_0x2bea740, C4<0>, C4<0>, C4<0>;
+L_0x2bea8a0 .delay (10000,10000,10000) L_0x2bea8a0/d;
+v0x2551e30_0 .net "A", 0 0, L_0x2beb190; 1 drivers
+v0x2551ed0_0 .net "AandB", 0 0, L_0x2bea8a0; 1 drivers
+v0x2550fa0_0 .net "AnandB", 0 0, L_0x2bea740; 1 drivers
+v0x2551020_0 .net "AndNandOut", 0 0, L_0x2beb840; 1 drivers
+v0x25545c0_0 .net "B", 0 0, L_0x2beb230; 1 drivers
+v0x2554640_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2beba10 .part v0x2960210_0, 0, 1;
+S_0x254fba0 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x254c580;
+ .timescale -9 -12;
+L_0x2beb520/d .functor NOT 1, L_0x2beba10, C4<0>, C4<0>, C4<0>;
+L_0x2beb520 .delay (10000,10000,10000) L_0x2beb520/d;
+L_0x2beb5e0/d .functor AND 1, L_0x2bea8a0, L_0x2beb520, C4<1>, C4<1>;
+L_0x2beb5e0 .delay (20000,20000,20000) L_0x2beb5e0/d;
+L_0x2beb6f0/d .functor AND 1, L_0x2bea740, L_0x2beba10, C4<1>, C4<1>;
+L_0x2beb6f0 .delay (20000,20000,20000) L_0x2beb6f0/d;
+L_0x2beb840/d .functor OR 1, L_0x2beb5e0, L_0x2beb6f0, C4<0>, C4<0>;
+L_0x2beb840 .delay (20000,20000,20000) L_0x2beb840/d;
+v0x254d710_0 .net "S", 0 0, L_0x2beba10; 1 drivers
+v0x254f920_0 .alias "in0", 0 0, v0x2551ed0_0;
+v0x254f9a0_0 .alias "in1", 0 0, v0x2550fa0_0;
+v0x254ea90_0 .net "nS", 0 0, L_0x2beb520; 1 drivers
+v0x254eb10_0 .net "out0", 0 0, L_0x2beb5e0; 1 drivers
+v0x25520b0_0 .net "out1", 0 0, L_0x2beb6f0; 1 drivers
+v0x2552130_0 .alias "outfinal", 0 0, v0x2551020_0;
+S_0x2546760 .scope generate, "andbits[31]" "andbits[31]" 3 231, 3 231, S_0x2543140;
+ .timescale -9 -12;
+P_0x24306c8 .param/l "i" 3 231, +C4<011111>;
+S_0x25464e0 .scope module, "attempt" "AndNand" 3 233, 3 149, S_0x2546760;
+ .timescale -9 -12;
+L_0x2beb320/d .functor NAND 1, L_0x2bec5e0, L_0x2bebb50, C4<1>, C4<1>;
+L_0x2beb320 .delay (10000,10000,10000) L_0x2beb320/d;
+L_0x2bebe80/d .functor NOT 1, L_0x2beb320, C4<0>, C4<0>, C4<0>;
+L_0x2bebe80 .delay (10000,10000,10000) L_0x2bebe80/d;
+v0x254b200_0 .net "A", 0 0, L_0x2bec5e0; 1 drivers
+v0x254af00_0 .net "AandB", 0 0, L_0x2bebe80; 1 drivers
+v0x254af80_0 .net "AnandB", 0 0, L_0x2beb320; 1 drivers
+v0x254a070_0 .net "AndNandOut", 0 0, L_0x2bec2d0; 1 drivers
+v0x254a0f0_0 .net "B", 0 0, L_0x2bebb50; 1 drivers
+v0x254d690_0 .alias "Command", 2 0, v0x295f7a0_0;
+L_0x2bec4a0 .part v0x2960210_0, 0, 1;
+S_0x2545650 .scope module, "potato" "TwoInMux" 3 161, 3 109, S_0x25464e0;
+ .timescale -9 -12;
+L_0x2bebfb0/d .functor NOT 1, L_0x2bec4a0, C4<0>, C4<0>, C4<0>;
+L_0x2bebfb0 .delay (10000,10000,10000) L_0x2bebfb0/d;
+L_0x2bec070/d .functor AND 1, L_0x2bebe80, L_0x2bebfb0, C4<1>, C4<1>;
+L_0x2bec070 .delay (20000,20000,20000) L_0x2bec070/d;
+L_0x2bec180/d .functor AND 1, L_0x2beb320, L_0x2bec4a0, C4<1>, C4<1>;
+L_0x2bec180 .delay (20000,20000,20000) L_0x2bec180/d;
+L_0x2bec2d0/d .functor OR 1, L_0x2bec070, L_0x2bec180, C4<0>, C4<0>;
+L_0x2bec2d0 .delay (20000,20000,20000) L_0x2bec2d0/d;
+v0x2548c70_0 .net "S", 0 0, L_0x2bec4a0; 1 drivers
+v0x2548cf0_0 .alias "in0", 0 0, v0x254af00_0;
+v0x25489f0_0 .alias "in1", 0 0, v0x254af80_0;
+v0x2548a70_0 .net "nS", 0 0, L_0x2bebfb0; 1 drivers
+v0x2547b60_0 .net "out0", 0 0, L_0x2bec070; 1 drivers
+v0x2547be0_0 .net "out1", 0 0, L_0x2bec180; 1 drivers
+v0x254b180_0 .alias "outfinal", 0 0, v0x254a070_0;
+S_0x2340a70 .scope module, "trial2" "OrNorXor32" 3 55, 3 239, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x23bfd58 .param/l "size" 3 246, +C4<0100000>;
+v0x2544250_0 .alias "A", 31 0, v0x295f580_0;
+v0x25442d0_0 .alias "B", 31 0, v0x295f6a0_0;
+v0x2543fd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2544050_0 .alias "OrNorXorOut", 31 0, v0x24153d0_0;
+L_0x2bee390 .part/pv L_0x2bee120, 1, 1, 32;
+L_0x2bee430 .part v0x295fe90_0, 1, 1;
+L_0x2bee4d0 .part v0x2960190_0, 1, 1;
+L_0x2bef6b0 .part/pv L_0x2bef440, 2, 1, 32;
+L_0x2bef750 .part v0x295fe90_0, 2, 1;
+L_0x2bef7f0 .part v0x2960190_0, 2, 1;
+L_0x2bf09d0 .part/pv L_0x2bf0760, 3, 1, 32;
+L_0x2bf0a70 .part v0x295fe90_0, 3, 1;
+L_0x2bf0b10 .part v0x2960190_0, 3, 1;
+L_0x2bf1ce0 .part/pv L_0x2bf1a70, 4, 1, 32;
+L_0x2bf1de0 .part v0x295fe90_0, 4, 1;
+L_0x2bf1e80 .part v0x2960190_0, 4, 1;
+L_0x2bf3000 .part/pv L_0x2bf2d90, 5, 1, 32;
+L_0x2bf30a0 .part v0x295fe90_0, 5, 1;
+L_0x2bf31c0 .part v0x2960190_0, 5, 1;
+L_0x2bf4380 .part/pv L_0x2bf4110, 6, 1, 32;
+L_0x2bf44b0 .part v0x295fe90_0, 6, 1;
+L_0x2bf4550 .part v0x2960190_0, 6, 1;
+L_0x2bf5730 .part/pv L_0x2bf54c0, 7, 1, 32;
+L_0x2bf57d0 .part v0x295fe90_0, 7, 1;
+L_0x2bf45f0 .part v0x2960190_0, 7, 1;
+L_0x2bf6a40 .part/pv L_0x2bf67d0, 8, 1, 32;
+L_0x2bf5870 .part v0x295fe90_0, 8, 1;
+L_0x2bf6ba0 .part v0x2960190_0, 8, 1;
+L_0x2bf7d70 .part/pv L_0x2bf7b00, 9, 1, 32;
+L_0x2bf7e10 .part v0x295fe90_0, 9, 1;
+L_0x2bf6c40 .part v0x2960190_0, 9, 1;
+L_0x2bf9090 .part/pv L_0x2bf8e20, 10, 1, 32;
+L_0x2bf7eb0 .part v0x295fe90_0, 10, 1;
+L_0x2bf9220 .part v0x2960190_0, 10, 1;
+L_0x2bfa3b0 .part/pv L_0x2bfa140, 11, 1, 32;
+L_0x2bfa450 .part v0x295fe90_0, 11, 1;
+L_0x2bf92c0 .part v0x2960190_0, 11, 1;
+L_0x2bfb6c0 .part/pv L_0x2bfb450, 12, 1, 32;
+L_0x2bfa4f0 .part v0x295fe90_0, 12, 1;
+L_0x2bfb880 .part v0x2960190_0, 12, 1;
+L_0x2bfca00 .part/pv L_0x2bfc790, 13, 1, 32;
+L_0x2bfcaa0 .part v0x295fe90_0, 13, 1;
+L_0x2bfb920 .part v0x2960190_0, 13, 1;
+L_0x2bfdd00 .part/pv L_0x2bfda90, 14, 1, 32;
+L_0x2bfcb40 .part v0x295fe90_0, 14, 1;
+L_0x2bfcbe0 .part v0x2960190_0, 14, 1;
+L_0x2bff020 .part/pv L_0x2bfedb0, 15, 1, 32;
+L_0x2bff0c0 .part v0x295fe90_0, 15, 1;
+L_0x2bfdda0 .part v0x2960190_0, 15, 1;
+L_0x2c00330 .part/pv L_0x2c000c0, 16, 1, 32;
+L_0x2bff160 .part v0x295fe90_0, 16, 1;
+L_0x2bff200 .part v0x2960190_0, 16, 1;
+L_0x2c01660 .part/pv L_0x2c013f0, 17, 1, 32;
+L_0x2c01700 .part v0x295fe90_0, 17, 1;
+L_0x2c003d0 .part v0x2960190_0, 17, 1;
+L_0x2c02970 .part/pv L_0x2c02700, 18, 1, 32;
+L_0x2c017a0 .part v0x295fe90_0, 18, 1;
+L_0x2c01840 .part v0x2960190_0, 18, 1;
+L_0x2c03c90 .part/pv L_0x2c03a20, 19, 1, 32;
+L_0x2c03d30 .part v0x295fe90_0, 19, 1;
+L_0x2c02a10 .part v0x2960190_0, 19, 1;
+L_0x2c04fb0 .part/pv L_0x2c04d40, 20, 1, 32;
+L_0x2c03dd0 .part v0x295fe90_0, 20, 1;
+L_0x2c03e70 .part v0x2960190_0, 20, 1;
+L_0x2c062e0 .part/pv L_0x2c06070, 21, 1, 32;
+L_0x2c06380 .part v0x295fe90_0, 21, 1;
+L_0x2c05050 .part v0x2960190_0, 21, 1;
+L_0x2c074b0 .part/pv L_0x2c07280, 22, 1, 32;
+L_0x2c06420 .part v0x295fe90_0, 22, 1;
+L_0x2c064c0 .part v0x2960190_0, 22, 1;
+L_0x2c085f0 .part/pv L_0x2c083c0, 23, 1, 32;
+L_0x2c08690 .part v0x295fe90_0, 23, 1;
+L_0x2c07550 .part v0x2960190_0, 23, 1;
+L_0x2c09730 .part/pv L_0x2c09500, 24, 1, 32;
+L_0x2c08730 .part v0x295fe90_0, 24, 1;
+L_0x2c087d0 .part v0x2960190_0, 24, 1;
+L_0x2c0a850 .part/pv L_0x2c0a620, 25, 1, 32;
+L_0x2c0a8f0 .part v0x295fe90_0, 25, 1;
+L_0x2c097d0 .part v0x2960190_0, 25, 1;
+L_0x2c0b980 .part/pv L_0x2c0b750, 26, 1, 32;
+L_0x2c0a990 .part v0x295fe90_0, 26, 1;
+L_0x2c0aa30 .part v0x2960190_0, 26, 1;
+L_0x2c0cbd0 .part/pv L_0x2c0c960, 27, 1, 32;
+L_0x2c0cc70 .part v0x295fe90_0, 27, 1;
+L_0x2c0ba20 .part v0x2960190_0, 27, 1;
+L_0x2c0def0 .part/pv L_0x2c0dc80, 28, 1, 32;
+L_0x2c0cd10 .part v0x295fe90_0, 28, 1;
+L_0x2c0cdb0 .part v0x2960190_0, 28, 1;
+L_0x2c0f1f0 .part/pv L_0x2c0ef80, 29, 1, 32;
+L_0x2c0f290 .part v0x295fe90_0, 29, 1;
+L_0x2c0df90 .part v0x2960190_0, 29, 1;
+L_0x2c10500 .part/pv L_0x2c10290, 30, 1, 32;
+L_0x2c0f330 .part v0x295fe90_0, 30, 1;
+L_0x2c0f3d0 .part v0x2960190_0, 30, 1;
+L_0x2c11830 .part/pv L_0x2c115c0, 31, 1, 32;
+L_0x2c118d0 .part v0x295fe90_0, 31, 1;
+L_0x2c105a0 .part v0x2960190_0, 31, 1;
+L_0x2c12b20 .part/pv L_0x2c128b0, 0, 1, 32;
+L_0x2c11970 .part v0x295fe90_0, 0, 1;
+L_0x2c11a10 .part v0x2960190_0, 0, 1;
+S_0x253a7f0 .scope module, "attempt2" "OrNorXor" 3 254, 3 165, S_0x2340a70;
+ .timescale -9 -12;
+L_0x2c10640/d .functor NOR 1, L_0x2c11970, L_0x2c11a10, C4<0>, C4<0>;
+L_0x2c10640 .delay (10000,10000,10000) L_0x2c10640/d;
+L_0x2c10730/d .functor NOT 1, L_0x2c10640, C4<0>, C4<0>, C4<0>;
+L_0x2c10730 .delay (10000,10000,10000) L_0x2c10730/d;
+L_0x2c11c60/d .functor NAND 1, L_0x2c11970, L_0x2c11a10, C4<1>, C4<1>;
+L_0x2c11c60 .delay (10000,10000,10000) L_0x2c11c60/d;
+L_0x2c11da0/d .functor NAND 1, L_0x2c11c60, L_0x2c10730, C4<1>, C4<1>;
+L_0x2c11da0 .delay (10000,10000,10000) L_0x2c11da0/d;
+L_0x2c11eb0/d .functor NOT 1, L_0x2c11da0, C4<0>, C4<0>, C4<0>;
+L_0x2c11eb0 .delay (10000,10000,10000) L_0x2c11eb0/d;
+v0x253f500_0 .net "A", 0 0, L_0x2c11970; 1 drivers
+v0x253f580_0 .net "AnandB", 0 0, L_0x2c11c60; 1 drivers
+v0x253e660_0 .net "AnorB", 0 0, L_0x2c10640; 1 drivers
+v0x253e6e0_0 .net "AorB", 0 0, L_0x2c10730; 1 drivers
+v0x2541d40_0 .net "AxorB", 0 0, L_0x2c11eb0; 1 drivers
+v0x2541dc0_0 .net "B", 0 0, L_0x2c11a10; 1 drivers
+v0x2541aa0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2541b20_0 .net "OrNorXorOut", 0 0, L_0x2c128b0; 1 drivers
+v0x2540c10_0 .net "XorNor", 0 0, L_0x2c12330; 1 drivers
+v0x2540c90_0 .net "nXor", 0 0, L_0x2c11da0; 1 drivers
+L_0x2c124b0 .part v0x2960210_0, 2, 1;
+L_0x2c12a80 .part v0x2960210_0, 0, 1;
+S_0x2587480 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x253a7f0;
+ .timescale -9 -12;
+L_0x2c12010/d .functor NOT 1, L_0x2c124b0, C4<0>, C4<0>, C4<0>;
+L_0x2c12010 .delay (10000,10000,10000) L_0x2c12010/d;
+L_0x2c120d0/d .functor AND 1, L_0x2c11eb0, L_0x2c12010, C4<1>, C4<1>;
+L_0x2c120d0 .delay (20000,20000,20000) L_0x2c120d0/d;
+L_0x2c121e0/d .functor AND 1, L_0x2c10640, L_0x2c124b0, C4<1>, C4<1>;
+L_0x2c121e0 .delay (20000,20000,20000) L_0x2c121e0/d;
+L_0x2c12330/d .functor OR 1, L_0x2c120d0, L_0x2c121e0, C4<0>, C4<0>;
+L_0x2c12330 .delay (20000,20000,20000) L_0x2c12330/d;
+v0x253b6b0_0 .net "S", 0 0, L_0x2c124b0; 1 drivers
+v0x2587210_0 .alias "in0", 0 0, v0x2541d40_0;
+v0x2587290_0 .alias "in1", 0 0, v0x253e660_0;
+v0x2586350_0 .net "nS", 0 0, L_0x2c12010; 1 drivers
+v0x25863d0_0 .net "out0", 0 0, L_0x2c120d0; 1 drivers
+v0x253f7e0_0 .net "out1", 0 0, L_0x2c121e0; 1 drivers
+v0x253f860_0 .alias "outfinal", 0 0, v0x2540c10_0;
+S_0x253a570 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x253a7f0;
+ .timescale -9 -12;
+L_0x2c12550/d .functor NOT 1, L_0x2c12a80, C4<0>, C4<0>, C4<0>;
+L_0x2c12550 .delay (10000,10000,10000) L_0x2c12550/d;
+L_0x2c12610/d .functor AND 1, L_0x2c12330, L_0x2c12550, C4<1>, C4<1>;
+L_0x2c12610 .delay (20000,20000,20000) L_0x2c12610/d;
+L_0x2c12760/d .functor AND 1, L_0x2c10730, L_0x2c12a80, C4<1>, C4<1>;
+L_0x2c12760 .delay (20000,20000,20000) L_0x2c12760/d;
+L_0x2c128b0/d .functor OR 1, L_0x2c12610, L_0x2c12760, C4<0>, C4<0>;
+L_0x2c128b0 .delay (20000,20000,20000) L_0x2c128b0/d;
+v0x253a070_0 .net "S", 0 0, L_0x2c12a80; 1 drivers
+v0x253a0f0_0 .alias "in0", 0 0, v0x2540c10_0;
+v0x253bdb0_0 .alias "in1", 0 0, v0x253e6e0_0;
+v0x253be30_0 .net "nS", 0 0, L_0x2c12550; 1 drivers
+v0x253bb30_0 .net "out0", 0 0, L_0x2c12610; 1 drivers
+v0x253bbb0_0 .net "out1", 0 0, L_0x2c12760; 1 drivers
+v0x253b630_0 .alias "outfinal", 0 0, v0x2541b20_0;
+S_0x2531df0 .scope generate, "orbits[1]" "orbits[1]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24a2fa8 .param/l "i" 3 258, +C4<01>;
+S_0x2533b30 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2531df0;
+ .timescale -9 -12;
+L_0x2bec810/d .functor NOR 1, L_0x2bee430, L_0x2bee4d0, C4<0>, C4<0>;
+L_0x2bec810 .delay (10000,10000,10000) L_0x2bec810/d;
+L_0x2bed360/d .functor NOT 1, L_0x2bec810, C4<0>, C4<0>, C4<0>;
+L_0x2bed360 .delay (10000,10000,10000) L_0x2bed360/d;
+L_0x2bed490/d .functor NAND 1, L_0x2bee430, L_0x2bee4d0, C4<1>, C4<1>;
+L_0x2bed490 .delay (10000,10000,10000) L_0x2bed490/d;
+L_0x2bed610/d .functor NAND 1, L_0x2bed490, L_0x2bed360, C4<1>, C4<1>;
+L_0x2bed610 .delay (10000,10000,10000) L_0x2bed610/d;
+L_0x2bed720/d .functor NOT 1, L_0x2bed610, C4<0>, C4<0>, C4<0>;
+L_0x2bed720 .delay (10000,10000,10000) L_0x2bed720/d;
+v0x25379f0_0 .net "A", 0 0, L_0x2bee430; 1 drivers
+v0x2537a90_0 .net "AnandB", 0 0, L_0x2bed490; 1 drivers
+v0x25374f0_0 .net "AnorB", 0 0, L_0x2bec810; 1 drivers
+v0x2537570_0 .net "AorB", 0 0, L_0x2bed360; 1 drivers
+v0x2539230_0 .net "AxorB", 0 0, L_0x2bed720; 1 drivers
+v0x25392b0_0 .net "B", 0 0, L_0x2bee4d0; 1 drivers
+v0x2538fb0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2539030_0 .net "OrNorXorOut", 0 0, L_0x2bee120; 1 drivers
+v0x2538ab0_0 .net "XorNor", 0 0, L_0x2bedba0; 1 drivers
+v0x2538b30_0 .net "nXor", 0 0, L_0x2bed610; 1 drivers
+L_0x2bedd20 .part v0x2960210_0, 2, 1;
+L_0x2bee2f0 .part v0x2960210_0, 0, 1;
+S_0x25366b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2533b30;
+ .timescale -9 -12;
+L_0x2bed880/d .functor NOT 1, L_0x2bedd20, C4<0>, C4<0>, C4<0>;
+L_0x2bed880 .delay (10000,10000,10000) L_0x2bed880/d;
+L_0x2bed940/d .functor AND 1, L_0x2bed720, L_0x2bed880, C4<1>, C4<1>;
+L_0x2bed940 .delay (20000,20000,20000) L_0x2bed940/d;
+L_0x2beda50/d .functor AND 1, L_0x2bec810, L_0x2bedd20, C4<1>, C4<1>;
+L_0x2beda50 .delay (20000,20000,20000) L_0x2beda50/d;
+L_0x2bedba0/d .functor OR 1, L_0x2bed940, L_0x2beda50, C4<0>, C4<0>;
+L_0x2bedba0 .delay (20000,20000,20000) L_0x2bedba0/d;
+v0x25349f0_0 .net "S", 0 0, L_0x2bedd20; 1 drivers
+v0x2536430_0 .alias "in0", 0 0, v0x2539230_0;
+v0x25364b0_0 .alias "in1", 0 0, v0x25374f0_0;
+v0x2535f30_0 .net "nS", 0 0, L_0x2bed880; 1 drivers
+v0x2535fb0_0 .net "out0", 0 0, L_0x2bed940; 1 drivers
+v0x2537c70_0 .net "out1", 0 0, L_0x2beda50; 1 drivers
+v0x2537d10_0 .alias "outfinal", 0 0, v0x2538ab0_0;
+S_0x25338b0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2533b30;
+ .timescale -9 -12;
+L_0x2beddc0/d .functor NOT 1, L_0x2bee2f0, C4<0>, C4<0>, C4<0>;
+L_0x2beddc0 .delay (10000,10000,10000) L_0x2beddc0/d;
+L_0x2bede80/d .functor AND 1, L_0x2bedba0, L_0x2beddc0, C4<1>, C4<1>;
+L_0x2bede80 .delay (20000,20000,20000) L_0x2bede80/d;
+L_0x2bedfd0/d .functor AND 1, L_0x2bed360, L_0x2bee2f0, C4<1>, C4<1>;
+L_0x2bedfd0 .delay (20000,20000,20000) L_0x2bedfd0/d;
+L_0x2bee120/d .functor OR 1, L_0x2bede80, L_0x2bedfd0, C4<0>, C4<0>;
+L_0x2bee120 .delay (20000,20000,20000) L_0x2bee120/d;
+v0x25333b0_0 .net "S", 0 0, L_0x2bee2f0; 1 drivers
+v0x2533430_0 .alias "in0", 0 0, v0x2538ab0_0;
+v0x25350f0_0 .alias "in1", 0 0, v0x2537570_0;
+v0x2535170_0 .net "nS", 0 0, L_0x2beddc0; 1 drivers
+v0x2534e70_0 .net "out0", 0 0, L_0x2bede80; 1 drivers
+v0x2534ef0_0 .net "out1", 0 0, L_0x2bedfd0; 1 drivers
+v0x2534970_0 .alias "outfinal", 0 0, v0x2539030_0;
+S_0x2528d30 .scope generate, "orbits[2]" "orbits[2]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2499838 .param/l "i" 3 258, +C4<010>;
+S_0x2528ab0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2528d30;
+ .timescale -9 -12;
+L_0x2bee570/d .functor NOR 1, L_0x2bef750, L_0x2bef7f0, C4<0>, C4<0>;
+L_0x2bee570 .delay (10000,10000,10000) L_0x2bee570/d;
+L_0x2bee680/d .functor NOT 1, L_0x2bee570, C4<0>, C4<0>, C4<0>;
+L_0x2bee680 .delay (10000,10000,10000) L_0x2bee680/d;
+L_0x2bee7b0/d .functor NAND 1, L_0x2bef750, L_0x2bef7f0, C4<1>, C4<1>;
+L_0x2bee7b0 .delay (10000,10000,10000) L_0x2bee7b0/d;
+L_0x2bee930/d .functor NAND 1, L_0x2bee7b0, L_0x2bee680, C4<1>, C4<1>;
+L_0x2bee930 .delay (10000,10000,10000) L_0x2bee930/d;
+L_0x2beea40/d .functor NOT 1, L_0x2bee930, C4<0>, C4<0>, C4<0>;
+L_0x2beea40 .delay (10000,10000,10000) L_0x2beea40/d;
+v0x252f750_0 .net "A", 0 0, L_0x2bef750; 1 drivers
+v0x252f7f0_0 .net "AnandB", 0 0, L_0x2bee7b0; 1 drivers
+v0x2530fb0_0 .net "AnorB", 0 0, L_0x2bee570; 1 drivers
+v0x2531030_0 .net "AorB", 0 0, L_0x2bee680; 1 drivers
+v0x2530d30_0 .net "AxorB", 0 0, L_0x2beea40; 1 drivers
+v0x2530db0_0 .net "B", 0 0, L_0x2bef7f0; 1 drivers
+v0x2532570_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25325f0_0 .net "OrNorXorOut", 0 0, L_0x2bef440; 1 drivers
+v0x25322f0_0 .net "XorNor", 0 0, L_0x2beeec0; 1 drivers
+v0x2532370_0 .net "nXor", 0 0, L_0x2bee930; 1 drivers
+L_0x2bef040 .part v0x2960210_0, 2, 1;
+L_0x2bef610 .part v0x2960210_0, 0, 1;
+S_0x252cbd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2528ab0;
+ .timescale -9 -12;
+L_0x2beeba0/d .functor NOT 1, L_0x2bef040, C4<0>, C4<0>, C4<0>;
+L_0x2beeba0 .delay (10000,10000,10000) L_0x2beeba0/d;
+L_0x2beec60/d .functor AND 1, L_0x2beea40, L_0x2beeba0, C4<1>, C4<1>;
+L_0x2beec60 .delay (20000,20000,20000) L_0x2beec60/d;
+L_0x2beed70/d .functor AND 1, L_0x2bee570, L_0x2bef040, C4<1>, C4<1>;
+L_0x2beed70 .delay (20000,20000,20000) L_0x2beed70/d;
+L_0x2beeec0/d .functor OR 1, L_0x2beec60, L_0x2beed70, C4<0>, C4<0>;
+L_0x2beeec0 .delay (20000,20000,20000) L_0x2beeec0/d;
+v0x252cef0_0 .net "S", 0 0, L_0x2bef040; 1 drivers
+v0x252e430_0 .alias "in0", 0 0, v0x2530d30_0;
+v0x252e4b0_0 .alias "in1", 0 0, v0x2530fb0_0;
+v0x252e1b0_0 .net "nS", 0 0, L_0x2beeba0; 1 drivers
+v0x252e230_0 .net "out0", 0 0, L_0x2beec60; 1 drivers
+v0x252f9f0_0 .net "out1", 0 0, L_0x2beed70; 1 drivers
+v0x252fa90_0 .alias "outfinal", 0 0, v0x25322f0_0;
+S_0x252a2f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2528ab0;
+ .timescale -9 -12;
+L_0x2bef0e0/d .functor NOT 1, L_0x2bef610, C4<0>, C4<0>, C4<0>;
+L_0x2bef0e0 .delay (10000,10000,10000) L_0x2bef0e0/d;
+L_0x2bef1a0/d .functor AND 1, L_0x2beeec0, L_0x2bef0e0, C4<1>, C4<1>;
+L_0x2bef1a0 .delay (20000,20000,20000) L_0x2bef1a0/d;
+L_0x2bef2f0/d .functor AND 1, L_0x2bee680, L_0x2bef610, C4<1>, C4<1>;
+L_0x2bef2f0 .delay (20000,20000,20000) L_0x2bef2f0/d;
+L_0x2bef440/d .functor OR 1, L_0x2bef1a0, L_0x2bef2f0, C4<0>, C4<0>;
+L_0x2bef440 .delay (20000,20000,20000) L_0x2bef440/d;
+v0x252a050_0 .net "S", 0 0, L_0x2bef610; 1 drivers
+v0x252a0d0_0 .alias "in0", 0 0, v0x25322f0_0;
+v0x252b8b0_0 .alias "in1", 0 0, v0x2531030_0;
+v0x252b930_0 .net "nS", 0 0, L_0x2bef0e0; 1 drivers
+v0x252b630_0 .net "out0", 0 0, L_0x2bef1a0; 1 drivers
+v0x252b6b0_0 .net "out1", 0 0, L_0x2bef2f0; 1 drivers
+v0x252ce70_0 .alias "outfinal", 0 0, v0x25325f0_0;
+S_0x251d790 .scope generate, "orbits[3]" "orbits[3]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2493648 .param/l "i" 3 258, +C4<011>;
+S_0x251f4d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x251d790;
+ .timescale -9 -12;
+L_0x2bef8d0/d .functor NOR 1, L_0x2bf0a70, L_0x2bf0b10, C4<0>, C4<0>;
+L_0x2bef8d0 .delay (10000,10000,10000) L_0x2bef8d0/d;
+L_0x2bef9c0/d .functor NOT 1, L_0x2bef8d0, C4<0>, C4<0>, C4<0>;
+L_0x2bef9c0 .delay (10000,10000,10000) L_0x2bef9c0/d;
+L_0x2befad0/d .functor NAND 1, L_0x2bf0a70, L_0x2bf0b10, C4<1>, C4<1>;
+L_0x2befad0 .delay (10000,10000,10000) L_0x2befad0/d;
+L_0x2befc50/d .functor NAND 1, L_0x2befad0, L_0x2bef9c0, C4<1>, C4<1>;
+L_0x2befc50 .delay (10000,10000,10000) L_0x2befc50/d;
+L_0x2befd60/d .functor NOT 1, L_0x2befc50, C4<0>, C4<0>, C4<0>;
+L_0x2befd60 .delay (10000,10000,10000) L_0x2befd60/d;
+v0x2524950_0 .net "A", 0 0, L_0x2bf0a70; 1 drivers
+v0x25249f0_0 .net "AnandB", 0 0, L_0x2befad0; 1 drivers
+v0x25261b0_0 .net "AnorB", 0 0, L_0x2bef8d0; 1 drivers
+v0x2526230_0 .net "AorB", 0 0, L_0x2bef9c0; 1 drivers
+v0x2525f30_0 .net "AxorB", 0 0, L_0x2befd60; 1 drivers
+v0x2525fb0_0 .net "B", 0 0, L_0x2bf0b10; 1 drivers
+v0x2527770_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x25277f0_0 .net "OrNorXorOut", 0 0, L_0x2bf0760; 1 drivers
+v0x25274d0_0 .net "XorNor", 0 0, L_0x2bf01e0; 1 drivers
+v0x2527550_0 .net "nXor", 0 0, L_0x2befc50; 1 drivers
+L_0x2bf0360 .part v0x2960210_0, 2, 1;
+L_0x2bf0930 .part v0x2960210_0, 0, 1;
+S_0x2521dd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x251f4d0;
+ .timescale -9 -12;
+L_0x2befec0/d .functor NOT 1, L_0x2bf0360, C4<0>, C4<0>, C4<0>;
+L_0x2befec0 .delay (10000,10000,10000) L_0x2befec0/d;
+L_0x2beff80/d .functor AND 1, L_0x2befd60, L_0x2befec0, C4<1>, C4<1>;
+L_0x2beff80 .delay (20000,20000,20000) L_0x2beff80/d;
+L_0x2bf0090/d .functor AND 1, L_0x2bef8d0, L_0x2bf0360, C4<1>, C4<1>;
+L_0x2bf0090 .delay (20000,20000,20000) L_0x2bf0090/d;
+L_0x2bf01e0/d .functor OR 1, L_0x2beff80, L_0x2bf0090, C4<0>, C4<0>;
+L_0x2bf01e0 .delay (20000,20000,20000) L_0x2bf01e0/d;
+v0x25220f0_0 .net "S", 0 0, L_0x2bf0360; 1 drivers
+v0x2523630_0 .alias "in0", 0 0, v0x2525f30_0;
+v0x25236b0_0 .alias "in1", 0 0, v0x25261b0_0;
+v0x25233b0_0 .net "nS", 0 0, L_0x2befec0; 1 drivers
+v0x2523430_0 .net "out0", 0 0, L_0x2beff80; 1 drivers
+v0x2524bf0_0 .net "out1", 0 0, L_0x2bf0090; 1 drivers
+v0x2524c90_0 .alias "outfinal", 0 0, v0x25274d0_0;
+S_0x251f250 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x251f4d0;
+ .timescale -9 -12;
+L_0x2bf0400/d .functor NOT 1, L_0x2bf0930, C4<0>, C4<0>, C4<0>;
+L_0x2bf0400 .delay (10000,10000,10000) L_0x2bf0400/d;
+L_0x2bf04c0/d .functor AND 1, L_0x2bf01e0, L_0x2bf0400, C4<1>, C4<1>;
+L_0x2bf04c0 .delay (20000,20000,20000) L_0x2bf04c0/d;
+L_0x2bf0610/d .functor AND 1, L_0x2bef9c0, L_0x2bf0930, C4<1>, C4<1>;
+L_0x2bf0610 .delay (20000,20000,20000) L_0x2bf0610/d;
+L_0x2bf0760/d .functor OR 1, L_0x2bf04c0, L_0x2bf0610, C4<0>, C4<0>;
+L_0x2bf0760 .delay (20000,20000,20000) L_0x2bf0760/d;
+v0x251ed50_0 .net "S", 0 0, L_0x2bf0930; 1 drivers
+v0x251edd0_0 .alias "in0", 0 0, v0x25274d0_0;
+v0x2520ab0_0 .alias "in1", 0 0, v0x2526230_0;
+v0x2520b30_0 .net "nS", 0 0, L_0x2bf0400; 1 drivers
+v0x2520830_0 .net "out0", 0 0, L_0x2bf04c0; 1 drivers
+v0x25208b0_0 .net "out1", 0 0, L_0x2bf0610; 1 drivers
+v0x2522070_0 .alias "outfinal", 0 0, v0x25277f0_0;
+S_0x2516fd0 .scope generate, "orbits[4]" "orbits[4]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2486578 .param/l "i" 3 258, +C4<0100>;
+S_0x2516ad0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2516fd0;
+ .timescale -9 -12;
+L_0x2bf0bb0/d .functor NOR 1, L_0x2bf1de0, L_0x2bf1e80, C4<0>, C4<0>;
+L_0x2bf0bb0 .delay (10000,10000,10000) L_0x2bf0bb0/d;
+L_0x2bf0cb0/d .functor NOT 1, L_0x2bf0bb0, C4<0>, C4<0>, C4<0>;
+L_0x2bf0cb0 .delay (10000,10000,10000) L_0x2bf0cb0/d;
+L_0x2bf0de0/d .functor NAND 1, L_0x2bf1de0, L_0x2bf1e80, C4<1>, C4<1>;
+L_0x2bf0de0 .delay (10000,10000,10000) L_0x2bf0de0/d;
+L_0x2bf0f60/d .functor NAND 1, L_0x2bf0de0, L_0x2bf0cb0, C4<1>, C4<1>;
+L_0x2bf0f60 .delay (10000,10000,10000) L_0x2bf0f60/d;
+L_0x2bf1070/d .functor NOT 1, L_0x2bf0f60, C4<0>, C4<0>, C4<0>;
+L_0x2bf1070 .delay (10000,10000,10000) L_0x2bf1070/d;
+v0x251c950_0 .net "A", 0 0, L_0x2bf1de0; 1 drivers
+v0x251c9f0_0 .net "AnandB", 0 0, L_0x2bf0de0; 1 drivers
+v0x251c6d0_0 .net "AnorB", 0 0, L_0x2bf0bb0; 1 drivers
+v0x251c750_0 .net "AorB", 0 0, L_0x2bf0cb0; 1 drivers
+v0x251c1d0_0 .net "AxorB", 0 0, L_0x2bf1070; 1 drivers
+v0x251c250_0 .net "B", 0 0, L_0x2bf1e80; 1 drivers
+v0x251df10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x251df90_0 .net "OrNorXorOut", 0 0, L_0x2bf1a70; 1 drivers
+v0x251dc90_0 .net "XorNor", 0 0, L_0x2bf14f0; 1 drivers
+v0x251dd10_0 .net "nXor", 0 0, L_0x2bf0f60; 1 drivers
+L_0x2bf1670 .part v0x2960210_0, 2, 1;
+L_0x2bf1c40 .part v0x2960210_0, 0, 1;
+S_0x2519650 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2516ad0;
+ .timescale -9 -12;
+L_0x2bf11d0/d .functor NOT 1, L_0x2bf1670, C4<0>, C4<0>, C4<0>;
+L_0x2bf11d0 .delay (10000,10000,10000) L_0x2bf11d0/d;
+L_0x2bf1290/d .functor AND 1, L_0x2bf1070, L_0x2bf11d0, C4<1>, C4<1>;
+L_0x2bf1290 .delay (20000,20000,20000) L_0x2bf1290/d;
+L_0x2bf13a0/d .functor AND 1, L_0x2bf0bb0, L_0x2bf1670, C4<1>, C4<1>;
+L_0x2bf13a0 .delay (20000,20000,20000) L_0x2bf13a0/d;
+L_0x2bf14f0/d .functor OR 1, L_0x2bf1290, L_0x2bf13a0, C4<0>, C4<0>;
+L_0x2bf14f0 .delay (20000,20000,20000) L_0x2bf14f0/d;
+v0x2519bd0_0 .net "S", 0 0, L_0x2bf1670; 1 drivers
+v0x251b390_0 .alias "in0", 0 0, v0x251c1d0_0;
+v0x251b410_0 .alias "in1", 0 0, v0x251c6d0_0;
+v0x251b110_0 .net "nS", 0 0, L_0x2bf11d0; 1 drivers
+v0x251b190_0 .net "out0", 0 0, L_0x2bf1290; 1 drivers
+v0x251ac10_0 .net "out1", 0 0, L_0x2bf13a0; 1 drivers
+v0x251acb0_0 .alias "outfinal", 0 0, v0x251dc90_0;
+S_0x2518810 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2516ad0;
+ .timescale -9 -12;
+L_0x2bf1710/d .functor NOT 1, L_0x2bf1c40, C4<0>, C4<0>, C4<0>;
+L_0x2bf1710 .delay (10000,10000,10000) L_0x2bf1710/d;
+L_0x2bf17d0/d .functor AND 1, L_0x2bf14f0, L_0x2bf1710, C4<1>, C4<1>;
+L_0x2bf17d0 .delay (20000,20000,20000) L_0x2bf17d0/d;
+L_0x2bf1920/d .functor AND 1, L_0x2bf0cb0, L_0x2bf1c40, C4<1>, C4<1>;
+L_0x2bf1920 .delay (20000,20000,20000) L_0x2bf1920/d;
+L_0x2bf1a70/d .functor OR 1, L_0x2bf17d0, L_0x2bf1920, C4<0>, C4<0>;
+L_0x2bf1a70 .delay (20000,20000,20000) L_0x2bf1a70/d;
+v0x2518590_0 .net "S", 0 0, L_0x2bf1c40; 1 drivers
+v0x2518610_0 .alias "in0", 0 0, v0x251dc90_0;
+v0x2518090_0 .alias "in1", 0 0, v0x251c750_0;
+v0x2518110_0 .net "nS", 0 0, L_0x2bf1710; 1 drivers
+v0x2519dd0_0 .net "out0", 0 0, L_0x2bf17d0; 1 drivers
+v0x2519e50_0 .net "out1", 0 0, L_0x2bf1920; 1 drivers
+v0x2519b50_0 .alias "outfinal", 0 0, v0x251df90_0;
+S_0x250af40 .scope generate, "orbits[5]" "orbits[5]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x247cdf8 .param/l "i" 3 258, +C4<0101>;
+S_0x2509300 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x250af40;
+ .timescale -9 -12;
+L_0x2bf1d80/d .functor NOR 1, L_0x2bf30a0, L_0x2bf31c0, C4<0>, C4<0>;
+L_0x2bf1d80 .delay (10000,10000,10000) L_0x2bf1d80/d;
+L_0x2bf1fd0/d .functor NOT 1, L_0x2bf1d80, C4<0>, C4<0>, C4<0>;
+L_0x2bf1fd0 .delay (10000,10000,10000) L_0x2bf1fd0/d;
+L_0x2bf2100/d .functor NAND 1, L_0x2bf30a0, L_0x2bf31c0, C4<1>, C4<1>;
+L_0x2bf2100 .delay (10000,10000,10000) L_0x2bf2100/d;
+L_0x2bf2280/d .functor NAND 1, L_0x2bf2100, L_0x2bf1fd0, C4<1>, C4<1>;
+L_0x2bf2280 .delay (10000,10000,10000) L_0x2bf2280/d;
+L_0x2bf2390/d .functor NOT 1, L_0x2bf2280, C4<0>, C4<0>, C4<0>;
+L_0x2bf2390 .delay (10000,10000,10000) L_0x2bf2390/d;
+v0x2514450_0 .net "A", 0 0, L_0x2bf30a0; 1 drivers
+v0x25144f0_0 .net "AnandB", 0 0, L_0x2bf2100; 1 drivers
+v0x2515c90_0 .net "AnorB", 0 0, L_0x2bf1d80; 1 drivers
+v0x2515d10_0 .net "AorB", 0 0, L_0x2bf1fd0; 1 drivers
+v0x2515a10_0 .net "AxorB", 0 0, L_0x2bf2390; 1 drivers
+v0x2515a90_0 .net "B", 0 0, L_0x2bf31c0; 1 drivers
+v0x2515510_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2515590_0 .net "OrNorXorOut", 0 0, L_0x2bf2d90; 1 drivers
+v0x2517250_0 .net "XorNor", 0 0, L_0x2bf2810; 1 drivers
+v0x25172d0_0 .net "nXor", 0 0, L_0x2bf2280; 1 drivers
+L_0x2bf2990 .part v0x2960210_0, 2, 1;
+L_0x2bf2f60 .part v0x2960210_0, 0, 1;
+S_0x253d0e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2509300;
+ .timescale -9 -12;
+L_0x2bf24f0/d .functor NOT 1, L_0x2bf2990, C4<0>, C4<0>, C4<0>;
+L_0x2bf24f0 .delay (10000,10000,10000) L_0x2bf24f0/d;
+L_0x2bf25b0/d .functor AND 1, L_0x2bf2390, L_0x2bf24f0, C4<1>, C4<1>;
+L_0x2bf25b0 .delay (20000,20000,20000) L_0x2bf25b0/d;
+L_0x2bf26c0/d .functor AND 1, L_0x2bf1d80, L_0x2bf2990, C4<1>, C4<1>;
+L_0x2bf26c0 .delay (20000,20000,20000) L_0x2bf26c0/d;
+L_0x2bf2810/d .functor OR 1, L_0x2bf25b0, L_0x2bf26c0, C4<0>, C4<0>;
+L_0x2bf2810 .delay (20000,20000,20000) L_0x2bf2810/d;
+v0x253d3d0_0 .net "S", 0 0, L_0x2bf2990; 1 drivers
+v0x253cbf0_0 .alias "in0", 0 0, v0x2515a10_0;
+v0x253cc70_0 .alias "in1", 0 0, v0x2515c90_0;
+v0x2512de0_0 .net "nS", 0 0, L_0x2bf24f0; 1 drivers
+v0x2512e60_0 .net "out0", 0 0, L_0x2bf25b0; 1 drivers
+v0x25146d0_0 .net "out1", 0 0, L_0x2bf26c0; 1 drivers
+v0x2514770_0 .alias "outfinal", 0 0, v0x2517250_0;
+S_0x250e250 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2509300;
+ .timescale -9 -12;
+L_0x2bf2a30/d .functor NOT 1, L_0x2bf2f60, C4<0>, C4<0>, C4<0>;
+L_0x2bf2a30 .delay (10000,10000,10000) L_0x2bf2a30/d;
+L_0x2bf2af0/d .functor AND 1, L_0x2bf2810, L_0x2bf2a30, C4<1>, C4<1>;
+L_0x2bf2af0 .delay (20000,20000,20000) L_0x2bf2af0/d;
+L_0x2bf2c40/d .functor AND 1, L_0x2bf1fd0, L_0x2bf2f60, C4<1>, C4<1>;
+L_0x2bf2c40 .delay (20000,20000,20000) L_0x2bf2c40/d;
+L_0x2bf2d90/d .functor OR 1, L_0x2bf2af0, L_0x2bf2c40, C4<0>, C4<0>;
+L_0x2bf2d90 .delay (20000,20000,20000) L_0x2bf2d90/d;
+v0x250dff0_0 .net "S", 0 0, L_0x2bf2f60; 1 drivers
+v0x250e070_0 .alias "in0", 0 0, v0x2517250_0;
+v0x250dd40_0 .alias "in1", 0 0, v0x2515d10_0;
+v0x250ddc0_0 .net "nS", 0 0, L_0x2bf2a30; 1 drivers
+v0x250c100_0 .net "out0", 0 0, L_0x2bf2af0; 1 drivers
+v0x250c180_0 .net "out1", 0 0, L_0x2bf2c40; 1 drivers
+v0x253d350_0 .alias "outfinal", 0 0, v0x2515590_0;
+S_0x24ff900 .scope generate, "orbits[6]" "orbits[6]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2473498 .param/l "i" 3 258, +C4<0110>;
+S_0x24fdc70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24ff900;
+ .timescale -9 -12;
+L_0x2bf3260/d .functor NOR 1, L_0x2bf44b0, L_0x2bf4550, C4<0>, C4<0>;
+L_0x2bf3260 .delay (10000,10000,10000) L_0x2bf3260/d;
+L_0x2bf3350/d .functor NOT 1, L_0x2bf3260, C4<0>, C4<0>, C4<0>;
+L_0x2bf3350 .delay (10000,10000,10000) L_0x2bf3350/d;
+L_0x2bf3480/d .functor NAND 1, L_0x2bf44b0, L_0x2bf4550, C4<1>, C4<1>;
+L_0x2bf3480 .delay (10000,10000,10000) L_0x2bf3480/d;
+L_0x2bf3600/d .functor NAND 1, L_0x2bf3480, L_0x2bf3350, C4<1>, C4<1>;
+L_0x2bf3600 .delay (10000,10000,10000) L_0x2bf3600/d;
+L_0x2bf3710/d .functor NOT 1, L_0x2bf3600, C4<0>, C4<0>, C4<0>;
+L_0x2bf3710 .delay (10000,10000,10000) L_0x2bf3710/d;
+v0x25083f0_0 .net "A", 0 0, L_0x2bf44b0; 1 drivers
+v0x2508490_0 .net "AnandB", 0 0, L_0x2bf3480; 1 drivers
+v0x2508140_0 .net "AnorB", 0 0, L_0x2bf3260; 1 drivers
+v0x25081c0_0 .net "AorB", 0 0, L_0x2bf3350; 1 drivers
+v0x2506500_0 .net "AxorB", 0 0, L_0x2bf3710; 1 drivers
+v0x2506580_0 .net "B", 0 0, L_0x2bf4550; 1 drivers
+v0x250b450_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x250b4d0_0 .net "OrNorXorOut", 0 0, L_0x2bf4110; 1 drivers
+v0x250b1f0_0 .net "XorNor", 0 0, L_0x2bf3b90; 1 drivers
+v0x250b270_0 .net "nXor", 0 0, L_0x2bf3600; 1 drivers
+L_0x2bf3d10 .part v0x2960210_0, 2, 1;
+L_0x2bf42e0 .part v0x2960210_0, 0, 1;
+S_0x25055f0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24fdc70;
+ .timescale -9 -12;
+L_0x2bf3870/d .functor NOT 1, L_0x2bf3d10, C4<0>, C4<0>, C4<0>;
+L_0x2bf3870 .delay (10000,10000,10000) L_0x2bf3870/d;
+L_0x2bf3930/d .functor AND 1, L_0x2bf3710, L_0x2bf3870, C4<1>, C4<1>;
+L_0x2bf3930 .delay (20000,20000,20000) L_0x2bf3930/d;
+L_0x2bf3a40/d .functor AND 1, L_0x2bf3260, L_0x2bf3d10, C4<1>, C4<1>;
+L_0x2bf3a40 .delay (20000,20000,20000) L_0x2bf3a40/d;
+L_0x2bf3b90/d .functor OR 1, L_0x2bf3930, L_0x2bf3a40, C4<0>, C4<0>;
+L_0x2bf3b90 .delay (20000,20000,20000) L_0x2bf3b90/d;
+v0x25058d0_0 .net "S", 0 0, L_0x2bf3d10; 1 drivers
+v0x2505340_0 .alias "in0", 0 0, v0x2506500_0;
+v0x25053c0_0 .alias "in1", 0 0, v0x2508140_0;
+v0x2503700_0 .net "nS", 0 0, L_0x2bf3870; 1 drivers
+v0x2503780_0 .net "out0", 0 0, L_0x2bf3930; 1 drivers
+v0x2508650_0 .net "out1", 0 0, L_0x2bf3a40; 1 drivers
+v0x25086f0_0 .alias "outfinal", 0 0, v0x250b1f0_0;
+S_0x2502a50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24fdc70;
+ .timescale -9 -12;
+L_0x2bf3db0/d .functor NOT 1, L_0x2bf42e0, C4<0>, C4<0>, C4<0>;
+L_0x2bf3db0 .delay (10000,10000,10000) L_0x2bf3db0/d;
+L_0x2bf3e70/d .functor AND 1, L_0x2bf3b90, L_0x2bf3db0, C4<1>, C4<1>;
+L_0x2bf3e70 .delay (20000,20000,20000) L_0x2bf3e70/d;
+L_0x2bf3fc0/d .functor AND 1, L_0x2bf3350, L_0x2bf42e0, C4<1>, C4<1>;
+L_0x2bf3fc0 .delay (20000,20000,20000) L_0x2bf3fc0/d;
+L_0x2bf4110/d .functor OR 1, L_0x2bf3e70, L_0x2bf3fc0, C4<0>, C4<0>;
+L_0x2bf4110 .delay (20000,20000,20000) L_0x2bf4110/d;
+v0x25027f0_0 .net "S", 0 0, L_0x2bf42e0; 1 drivers
+v0x2502870_0 .alias "in0", 0 0, v0x250b1f0_0;
+v0x2502540_0 .alias "in1", 0 0, v0x25081c0_0;
+v0x25025c0_0 .net "nS", 0 0, L_0x2bf3db0; 1 drivers
+v0x25008d0_0 .net "out0", 0 0, L_0x2bf3e70; 1 drivers
+v0x2500950_0 .net "out1", 0 0, L_0x2bf3fc0; 1 drivers
+v0x2505850_0 .alias "outfinal", 0 0, v0x250b4d0_0;
+S_0x24f1470 .scope generate, "orbits[7]" "orbits[7]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24220a8 .param/l "i" 3 258, +C4<0111>;
+S_0x24f11c0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24f1470;
+ .timescale -9 -12;
+L_0x2bf4420/d .functor NOR 1, L_0x2bf57d0, L_0x2bf45f0, C4<0>, C4<0>;
+L_0x2bf4420 .delay (10000,10000,10000) L_0x2bf4420/d;
+L_0x2bf4720/d .functor NOT 1, L_0x2bf4420, C4<0>, C4<0>, C4<0>;
+L_0x2bf4720 .delay (10000,10000,10000) L_0x2bf4720/d;
+L_0x2bf4830/d .functor NAND 1, L_0x2bf57d0, L_0x2bf45f0, C4<1>, C4<1>;
+L_0x2bf4830 .delay (10000,10000,10000) L_0x2bf4830/d;
+L_0x2bf49b0/d .functor NAND 1, L_0x2bf4830, L_0x2bf4720, C4<1>, C4<1>;
+L_0x2bf49b0 .delay (10000,10000,10000) L_0x2bf49b0/d;
+L_0x2bf4ac0/d .functor NOT 1, L_0x2bf49b0, C4<0>, C4<0>, C4<0>;
+L_0x2bf4ac0 .delay (10000,10000,10000) L_0x2bf4ac0/d;
+v0x24f7ff0_0 .net "A", 0 0, L_0x2bf57d0; 1 drivers
+v0x24f8090_0 .net "AnandB", 0 0, L_0x2bf4830; 1 drivers
+v0x24fcd70_0 .net "AnorB", 0 0, L_0x2bf4420; 1 drivers
+v0x24fcdf0_0 .net "AorB", 0 0, L_0x2bf4720; 1 drivers
+v0x24fcac0_0 .net "AxorB", 0 0, L_0x2bf4ac0; 1 drivers
+v0x24fcb40_0 .net "B", 0 0, L_0x2bf45f0; 1 drivers
+v0x24fae30_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24faeb0_0 .net "OrNorXorOut", 0 0, L_0x2bf54c0; 1 drivers
+v0x24ffbb0_0 .net "XorNor", 0 0, L_0x2bf4f40; 1 drivers
+v0x24ffc30_0 .net "nXor", 0 0, L_0x2bf49b0; 1 drivers
+L_0x2bf50c0 .part v0x2960210_0, 2, 1;
+L_0x2bf5690 .part v0x2960210_0, 0, 1;
+S_0x24f6e40 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24f11c0;
+ .timescale -9 -12;
+L_0x2bf4c20/d .functor NOT 1, L_0x2bf50c0, C4<0>, C4<0>, C4<0>;
+L_0x2bf4c20 .delay (10000,10000,10000) L_0x2bf4c20/d;
+L_0x2bf4ce0/d .functor AND 1, L_0x2bf4ac0, L_0x2bf4c20, C4<1>, C4<1>;
+L_0x2bf4ce0 .delay (20000,20000,20000) L_0x2bf4ce0/d;
+L_0x2bf4df0/d .functor AND 1, L_0x2bf4420, L_0x2bf50c0, C4<1>, C4<1>;
+L_0x2bf4df0 .delay (20000,20000,20000) L_0x2bf4df0/d;
+L_0x2bf4f40/d .functor OR 1, L_0x2bf4ce0, L_0x2bf4df0, C4<0>, C4<0>;
+L_0x2bf4f40 .delay (20000,20000,20000) L_0x2bf4f40/d;
+v0x24f7170_0 .net "S", 0 0, L_0x2bf50c0; 1 drivers
+v0x24f51b0_0 .alias "in0", 0 0, v0x24fcac0_0;
+v0x24f5230_0 .alias "in1", 0 0, v0x24fcd70_0;
+v0x24f9f30_0 .net "nS", 0 0, L_0x2bf4c20; 1 drivers
+v0x24f9fb0_0 .net "out0", 0 0, L_0x2bf4ce0; 1 drivers
+v0x24f9c80_0 .net "out1", 0 0, L_0x2bf4df0; 1 drivers
+v0x24f9d20_0 .alias "outfinal", 0 0, v0x24ffbb0_0;
+S_0x24ef580 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24f11c0;
+ .timescale -9 -12;
+L_0x2bf5160/d .functor NOT 1, L_0x2bf5690, C4<0>, C4<0>, C4<0>;
+L_0x2bf5160 .delay (10000,10000,10000) L_0x2bf5160/d;
+L_0x2bf5220/d .functor AND 1, L_0x2bf4f40, L_0x2bf5160, C4<1>, C4<1>;
+L_0x2bf5220 .delay (20000,20000,20000) L_0x2bf5220/d;
+L_0x2bf5370/d .functor AND 1, L_0x2bf4720, L_0x2bf5690, C4<1>, C4<1>;
+L_0x2bf5370 .delay (20000,20000,20000) L_0x2bf5370/d;
+L_0x2bf54c0/d .functor OR 1, L_0x2bf5220, L_0x2bf5370, C4<0>, C4<0>;
+L_0x2bf54c0 .delay (20000,20000,20000) L_0x2bf54c0/d;
+v0x24f42b0_0 .net "S", 0 0, L_0x2bf5690; 1 drivers
+v0x24f4330_0 .alias "in0", 0 0, v0x24ffbb0_0;
+v0x24f4000_0 .alias "in1", 0 0, v0x24fcdf0_0;
+v0x24f4080_0 .net "nS", 0 0, L_0x2bf5160; 1 drivers
+v0x24f2370_0 .net "out0", 0 0, L_0x2bf5220; 1 drivers
+v0x24f23f0_0 .net "out1", 0 0, L_0x2bf5370; 1 drivers
+v0x24f70f0_0 .alias "outfinal", 0 0, v0x24faeb0_0;
+S_0x24e5ed0 .scope generate, "orbits[8]" "orbits[8]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x245b6e8 .param/l "i" 3 258, +C4<01000>;
+S_0x24e5c70 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24e5ed0;
+ .timescale -9 -12;
+L_0x2bf5920/d .functor NOR 1, L_0x2bf5870, L_0x2bf6ba0, C4<0>, C4<0>;
+L_0x2bf5920 .delay (10000,10000,10000) L_0x2bf5920/d;
+L_0x2bf5a10/d .functor NOT 1, L_0x2bf5920, C4<0>, C4<0>, C4<0>;
+L_0x2bf5a10 .delay (10000,10000,10000) L_0x2bf5a10/d;
+L_0x2bf5b40/d .functor NAND 1, L_0x2bf5870, L_0x2bf6ba0, C4<1>, C4<1>;
+L_0x2bf5b40 .delay (10000,10000,10000) L_0x2bf5b40/d;
+L_0x2bf5cc0/d .functor NAND 1, L_0x2bf5b40, L_0x2bf5a10, C4<1>, C4<1>;
+L_0x2bf5cc0 .delay (10000,10000,10000) L_0x2bf5cc0/d;
+L_0x2bf5dd0/d .functor NOT 1, L_0x2bf5cc0, C4<0>, C4<0>, C4<0>;
+L_0x2bf5dd0 .delay (10000,10000,10000) L_0x2bf5dd0/d;
+v0x24e9980_0 .net "A", 0 0, L_0x2bf5870; 1 drivers
+v0x24e9a20_0 .net "AnandB", 0 0, L_0x2bf5b40; 1 drivers
+v0x24ee8d0_0 .net "AnorB", 0 0, L_0x2bf5920; 1 drivers
+v0x24ee950_0 .net "AorB", 0 0, L_0x2bf5a10; 1 drivers
+v0x24ee670_0 .net "AxorB", 0 0, L_0x2bf5dd0; 1 drivers
+v0x24ee6f0_0 .net "B", 0 0, L_0x2bf6ba0; 1 drivers
+v0x24ee3c0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24ee440_0 .net "OrNorXorOut", 0 0, L_0x2bf67d0; 1 drivers
+v0x24ec780_0 .net "XorNor", 0 0, L_0x2bf6250; 1 drivers
+v0x24ec800_0 .net "nXor", 0 0, L_0x2bf5cc0; 1 drivers
+L_0x2bf63d0 .part v0x2960210_0, 2, 1;
+L_0x2bf69a0 .part v0x2960210_0, 0, 1;
+S_0x24e6b80 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24e5c70;
+ .timescale -9 -12;
+L_0x2bf5f30/d .functor NOT 1, L_0x2bf63d0, C4<0>, C4<0>, C4<0>;
+L_0x2bf5f30 .delay (10000,10000,10000) L_0x2bf5f30/d;
+L_0x2bf5ff0/d .functor AND 1, L_0x2bf5dd0, L_0x2bf5f30, C4<1>, C4<1>;
+L_0x2bf5ff0 .delay (20000,20000,20000) L_0x2bf5ff0/d;
+L_0x2bf6100/d .functor AND 1, L_0x2bf5920, L_0x2bf63d0, C4<1>, C4<1>;
+L_0x2bf6100 .delay (20000,20000,20000) L_0x2bf6100/d;
+L_0x2bf6250/d .functor OR 1, L_0x2bf5ff0, L_0x2bf6100, C4<0>, C4<0>;
+L_0x2bf6250 .delay (20000,20000,20000) L_0x2bf6250/d;
+v0x24e8840_0 .net "S", 0 0, L_0x2bf63d0; 1 drivers
+v0x24ebad0_0 .alias "in0", 0 0, v0x24ee670_0;
+v0x24ebb50_0 .alias "in1", 0 0, v0x24ee8d0_0;
+v0x24eb870_0 .net "nS", 0 0, L_0x2bf5f30; 1 drivers
+v0x24eb8f0_0 .net "out0", 0 0, L_0x2bf5ff0; 1 drivers
+v0x24eb5c0_0 .net "out1", 0 0, L_0x2bf6100; 1 drivers
+v0x24eb660_0 .alias "outfinal", 0 0, v0x24ec780_0;
+S_0x24e59c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24e5c70;
+ .timescale -9 -12;
+L_0x2bf6470/d .functor NOT 1, L_0x2bf69a0, C4<0>, C4<0>, C4<0>;
+L_0x2bf6470 .delay (10000,10000,10000) L_0x2bf6470/d;
+L_0x2bf6530/d .functor AND 1, L_0x2bf6250, L_0x2bf6470, C4<1>, C4<1>;
+L_0x2bf6530 .delay (20000,20000,20000) L_0x2bf6530/d;
+L_0x2bf6680/d .functor AND 1, L_0x2bf5a10, L_0x2bf69a0, C4<1>, C4<1>;
+L_0x2bf6680 .delay (20000,20000,20000) L_0x2bf6680/d;
+L_0x2bf67d0/d .functor OR 1, L_0x2bf6530, L_0x2bf6680, C4<0>, C4<0>;
+L_0x2bf67d0 .delay (20000,20000,20000) L_0x2bf67d0/d;
+v0x24e3d80_0 .net "S", 0 0, L_0x2bf69a0; 1 drivers
+v0x24e3e00_0 .alias "in0", 0 0, v0x24ec780_0;
+v0x24e8cd0_0 .alias "in1", 0 0, v0x24ee950_0;
+v0x24e8d50_0 .net "nS", 0 0, L_0x2bf6470; 1 drivers
+v0x24e8a70_0 .net "out0", 0 0, L_0x2bf6530; 1 drivers
+v0x24e8af0_0 .net "out1", 0 0, L_0x2bf6680; 1 drivers
+v0x24e87c0_0 .alias "outfinal", 0 0, v0x24ee440_0;
+S_0x24d2a50 .scope generate, "orbits[9]" "orbits[9]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24554f8 .param/l "i" 3 258, +C4<01001>;
+S_0x24d77d0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24d2a50;
+ .timescale -9 -12;
+L_0x2bf6ae0/d .functor NOR 1, L_0x2bf7e10, L_0x2bf6c40, C4<0>, C4<0>;
+L_0x2bf6ae0 .delay (10000,10000,10000) L_0x2bf6ae0/d;
+L_0x2bf6d60/d .functor NOT 1, L_0x2bf6ae0, C4<0>, C4<0>, C4<0>;
+L_0x2bf6d60 .delay (10000,10000,10000) L_0x2bf6d60/d;
+L_0x2bf6e70/d .functor NAND 1, L_0x2bf7e10, L_0x2bf6c40, C4<1>, C4<1>;
+L_0x2bf6e70 .delay (10000,10000,10000) L_0x2bf6e70/d;
+L_0x2bf6ff0/d .functor NAND 1, L_0x2bf6e70, L_0x2bf6d60, C4<1>, C4<1>;
+L_0x2bf6ff0 .delay (10000,10000,10000) L_0x2bf6ff0/d;
+L_0x2bf7100/d .functor NOT 1, L_0x2bf6ff0, C4<0>, C4<0>, C4<0>;
+L_0x2bf7100 .delay (10000,10000,10000) L_0x2bf7100/d;
+v0x24de350_0 .net "A", 0 0, L_0x2bf7e10; 1 drivers
+v0x24de3f0_0 .net "AnandB", 0 0, L_0x2bf6e70; 1 drivers
+v0x24e30d0_0 .net "AnorB", 0 0, L_0x2bf6ae0; 1 drivers
+v0x24e3150_0 .net "AorB", 0 0, L_0x2bf6d60; 1 drivers
+v0x24e2e70_0 .net "AxorB", 0 0, L_0x2bf7100; 1 drivers
+v0x24e2ef0_0 .net "B", 0 0, L_0x2bf6c40; 1 drivers
+v0x24e2bc0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24e2c40_0 .net "OrNorXorOut", 0 0, L_0x2bf7b00; 1 drivers
+v0x24e0f80_0 .net "XorNor", 0 0, L_0x2bf7580; 1 drivers
+v0x24e1000_0 .net "nXor", 0 0, L_0x2bf6ff0; 1 drivers
+L_0x2bf7700 .part v0x2960210_0, 2, 1;
+L_0x2bf7cd0 .part v0x2960210_0, 0, 1;
+S_0x24dd450 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24d77d0;
+ .timescale -9 -12;
+L_0x2bf7260/d .functor NOT 1, L_0x2bf7700, C4<0>, C4<0>, C4<0>;
+L_0x2bf7260 .delay (10000,10000,10000) L_0x2bf7260/d;
+L_0x2bf7320/d .functor AND 1, L_0x2bf7100, L_0x2bf7260, C4<1>, C4<1>;
+L_0x2bf7320 .delay (20000,20000,20000) L_0x2bf7320/d;
+L_0x2bf7430/d .functor AND 1, L_0x2bf6ae0, L_0x2bf7700, C4<1>, C4<1>;
+L_0x2bf7430 .delay (20000,20000,20000) L_0x2bf7430/d;
+L_0x2bf7580/d .functor OR 1, L_0x2bf7320, L_0x2bf7430, C4<0>, C4<0>;
+L_0x2bf7580 .delay (20000,20000,20000) L_0x2bf7580/d;
+v0x24d8750_0 .net "S", 0 0, L_0x2bf7700; 1 drivers
+v0x24dd1a0_0 .alias "in0", 0 0, v0x24e2e70_0;
+v0x24dd220_0 .alias "in1", 0 0, v0x24e30d0_0;
+v0x24db510_0 .net "nS", 0 0, L_0x2bf7260; 1 drivers
+v0x24db590_0 .net "out0", 0 0, L_0x2bf7320; 1 drivers
+v0x24e02e0_0 .net "out1", 0 0, L_0x2bf7430; 1 drivers
+v0x24e0380_0 .alias "outfinal", 0 0, v0x24e0f80_0;
+S_0x24d7520 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24d77d0;
+ .timescale -9 -12;
+L_0x2bf77a0/d .functor NOT 1, L_0x2bf7cd0, C4<0>, C4<0>, C4<0>;
+L_0x2bf77a0 .delay (10000,10000,10000) L_0x2bf77a0/d;
+L_0x2bf7860/d .functor AND 1, L_0x2bf7580, L_0x2bf77a0, C4<1>, C4<1>;
+L_0x2bf7860 .delay (20000,20000,20000) L_0x2bf7860/d;
+L_0x2bf79b0/d .functor AND 1, L_0x2bf6d60, L_0x2bf7cd0, C4<1>, C4<1>;
+L_0x2bf79b0 .delay (20000,20000,20000) L_0x2bf79b0/d;
+L_0x2bf7b00/d .functor OR 1, L_0x2bf7860, L_0x2bf79b0, C4<0>, C4<0>;
+L_0x2bf7b00 .delay (20000,20000,20000) L_0x2bf7b00/d;
+v0x24d5890_0 .net "S", 0 0, L_0x2bf7cd0; 1 drivers
+v0x24d5910_0 .alias "in0", 0 0, v0x24e0f80_0;
+v0x24da610_0 .alias "in1", 0 0, v0x24e3150_0;
+v0x24da690_0 .net "nS", 0 0, L_0x2bf77a0; 1 drivers
+v0x24da360_0 .net "out0", 0 0, L_0x2bf7860; 1 drivers
+v0x24da3e0_0 .net "out1", 0 0, L_0x2bf79b0; 1 drivers
+v0x24d86d0_0 .alias "outfinal", 0 0, v0x24e2c40_0;
+S_0x24c9100 .scope generate, "orbits[10]" "orbits[10]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x244d038 .param/l "i" 3 258, +C4<01010>;
+S_0x24c8e50 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24c9100;
+ .timescale -9 -12;
+L_0x2bf7f90/d .functor NOR 1, L_0x2bf7eb0, L_0x2bf9220, C4<0>, C4<0>;
+L_0x2bf7f90 .delay (10000,10000,10000) L_0x2bf7f90/d;
+L_0x2bf8080/d .functor NOT 1, L_0x2bf7f90, C4<0>, C4<0>, C4<0>;
+L_0x2bf8080 .delay (10000,10000,10000) L_0x2bf8080/d;
+L_0x2bf8190/d .functor NAND 1, L_0x2bf7eb0, L_0x2bf9220, C4<1>, C4<1>;
+L_0x2bf8190 .delay (10000,10000,10000) L_0x2bf8190/d;
+L_0x2bf8310/d .functor NAND 1, L_0x2bf8190, L_0x2bf8080, C4<1>, C4<1>;
+L_0x2bf8310 .delay (10000,10000,10000) L_0x2bf8310/d;
+L_0x2bf8420/d .functor NOT 1, L_0x2bf8310, C4<0>, C4<0>, C4<0>;
+L_0x2bf8420 .delay (10000,10000,10000) L_0x2bf8420/d;
+v0x24d1b50_0 .net "A", 0 0, L_0x2bf7eb0; 1 drivers
+v0x24d1bf0_0 .net "AnandB", 0 0, L_0x2bf8190; 1 drivers
+v0x24d18a0_0 .net "AnorB", 0 0, L_0x2bf7f90; 1 drivers
+v0x24d1920_0 .net "AorB", 0 0, L_0x2bf8080; 1 drivers
+v0x24cfc10_0 .net "AxorB", 0 0, L_0x2bf8420; 1 drivers
+v0x24cfc90_0 .net "B", 0 0, L_0x2bf9220; 1 drivers
+v0x24d4990_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24d4a10_0 .net "OrNorXorOut", 0 0, L_0x2bf8e20; 1 drivers
+v0x24d46e0_0 .net "XorNor", 0 0, L_0x2bf88a0; 1 drivers
+v0x24d4760_0 .net "nXor", 0 0, L_0x2bf8310; 1 drivers
+L_0x2bf8a20 .part v0x2960210_0, 2, 1;
+L_0x2bf8ff0 .part v0x2960210_0, 0, 1;
+S_0x24cef60 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24c8e50;
+ .timescale -9 -12;
+L_0x2bf8580/d .functor NOT 1, L_0x2bf8a20, C4<0>, C4<0>, C4<0>;
+L_0x2bf8580 .delay (10000,10000,10000) L_0x2bf8580/d;
+L_0x2bf8640/d .functor AND 1, L_0x2bf8420, L_0x2bf8580, C4<1>, C4<1>;
+L_0x2bf8640 .delay (20000,20000,20000) L_0x2bf8640/d;
+L_0x2bf8750/d .functor AND 1, L_0x2bf7f90, L_0x2bf8a20, C4<1>, C4<1>;
+L_0x2bf8750 .delay (20000,20000,20000) L_0x2bf8750/d;
+L_0x2bf88a0/d .functor OR 1, L_0x2bf8640, L_0x2bf8750, C4<0>, C4<0>;
+L_0x2bf88a0 .delay (20000,20000,20000) L_0x2bf88a0/d;
+v0x24ca090_0 .net "S", 0 0, L_0x2bf8a20; 1 drivers
+v0x24ced00_0 .alias "in0", 0 0, v0x24cfc10_0;
+v0x24ced80_0 .alias "in1", 0 0, v0x24d18a0_0;
+v0x24cea50_0 .net "nS", 0 0, L_0x2bf8580; 1 drivers
+v0x24cead0_0 .net "out0", 0 0, L_0x2bf8640; 1 drivers
+v0x24cce10_0 .net "out1", 0 0, L_0x2bf8750; 1 drivers
+v0x24cceb0_0 .alias "outfinal", 0 0, v0x24d46e0_0;
+S_0x24c7210 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24c8e50;
+ .timescale -9 -12;
+L_0x2bf8ac0/d .functor NOT 1, L_0x2bf8ff0, C4<0>, C4<0>, C4<0>;
+L_0x2bf8ac0 .delay (10000,10000,10000) L_0x2bf8ac0/d;
+L_0x2bf8b80/d .functor AND 1, L_0x2bf88a0, L_0x2bf8ac0, C4<1>, C4<1>;
+L_0x2bf8b80 .delay (20000,20000,20000) L_0x2bf8b80/d;
+L_0x2bf8cd0/d .functor AND 1, L_0x2bf8080, L_0x2bf8ff0, C4<1>, C4<1>;
+L_0x2bf8cd0 .delay (20000,20000,20000) L_0x2bf8cd0/d;
+L_0x2bf8e20/d .functor OR 1, L_0x2bf8b80, L_0x2bf8cd0, C4<0>, C4<0>;
+L_0x2bf8e20 .delay (20000,20000,20000) L_0x2bf8e20/d;
+v0x24cc160_0 .net "S", 0 0, L_0x2bf8ff0; 1 drivers
+v0x24cc1e0_0 .alias "in0", 0 0, v0x24d46e0_0;
+v0x24cbf00_0 .alias "in1", 0 0, v0x24d1920_0;
+v0x24cbf80_0 .net "nS", 0 0, L_0x2bf8ac0; 1 drivers
+v0x24cbc50_0 .net "out0", 0 0, L_0x2bf8b80; 1 drivers
+v0x24cbcd0_0 .net "out1", 0 0, L_0x2bf8cd0; 1 drivers
+v0x24ca010_0 .alias "outfinal", 0 0, v0x24d4a10_0;
+S_0x24bda90 .scope generate, "orbits[11]" "orbits[11]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2443758 .param/l "i" 3 258, +C4<01011>;
+S_0x24bd7e0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24bda90;
+ .timescale -9 -12;
+L_0x2bf9130/d .functor NOR 1, L_0x2bfa450, L_0x2bf92c0, C4<0>, C4<0>;
+L_0x2bf9130 .delay (10000,10000,10000) L_0x2bf9130/d;
+L_0x2bf93c0/d .functor NOT 1, L_0x2bf9130, C4<0>, C4<0>, C4<0>;
+L_0x2bf93c0 .delay (10000,10000,10000) L_0x2bf93c0/d;
+L_0x2bf94b0/d .functor NAND 1, L_0x2bfa450, L_0x2bf92c0, C4<1>, C4<1>;
+L_0x2bf94b0 .delay (10000,10000,10000) L_0x2bf94b0/d;
+L_0x2bf9630/d .functor NAND 1, L_0x2bf94b0, L_0x2bf93c0, C4<1>, C4<1>;
+L_0x2bf9630 .delay (10000,10000,10000) L_0x2bf9630/d;
+L_0x2bf9740/d .functor NOT 1, L_0x2bf9630, C4<0>, C4<0>, C4<0>;
+L_0x2bf9740 .delay (10000,10000,10000) L_0x2bf9740/d;
+v0x24c6560_0 .net "A", 0 0, L_0x2bfa450; 1 drivers
+v0x24c6600_0 .net "AnandB", 0 0, L_0x2bf94b0; 1 drivers
+v0x24c6300_0 .net "AnorB", 0 0, L_0x2bf9130; 1 drivers
+v0x24c6380_0 .net "AorB", 0 0, L_0x2bf93c0; 1 drivers
+v0x24c6050_0 .net "AxorB", 0 0, L_0x2bf9740; 1 drivers
+v0x24c60d0_0 .net "B", 0 0, L_0x2bf92c0; 1 drivers
+v0x24c4410_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24c4490_0 .net "OrNorXorOut", 0 0, L_0x2bfa140; 1 drivers
+v0x24c9360_0 .net "XorNor", 0 0, L_0x2bf9bc0; 1 drivers
+v0x24c93e0_0 .net "nXor", 0 0, L_0x2bf9630; 1 drivers
+L_0x2bf9d40 .part v0x2960210_0, 2, 1;
+L_0x2bfa310 .part v0x2960210_0, 0, 1;
+S_0x24c3760 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24bd7e0;
+ .timescale -9 -12;
+L_0x2bf98a0/d .functor NOT 1, L_0x2bf9d40, C4<0>, C4<0>, C4<0>;
+L_0x2bf98a0 .delay (10000,10000,10000) L_0x2bf98a0/d;
+L_0x2bf9960/d .functor AND 1, L_0x2bf9740, L_0x2bf98a0, C4<1>, C4<1>;
+L_0x2bf9960 .delay (20000,20000,20000) L_0x2bf9960/d;
+L_0x2bf9a70/d .functor AND 1, L_0x2bf9130, L_0x2bf9d40, C4<1>, C4<1>;
+L_0x2bf9a70 .delay (20000,20000,20000) L_0x2bf9a70/d;
+L_0x2bf9bc0/d .functor OR 1, L_0x2bf9960, L_0x2bf9a70, C4<0>, C4<0>;
+L_0x2bf9bc0 .delay (20000,20000,20000) L_0x2bf9bc0/d;
+v0x24bea10_0 .net "S", 0 0, L_0x2bf9d40; 1 drivers
+v0x24c3500_0 .alias "in0", 0 0, v0x24c6050_0;
+v0x24c3580_0 .alias "in1", 0 0, v0x24c6300_0;
+v0x24c3250_0 .net "nS", 0 0, L_0x2bf98a0; 1 drivers
+v0x24c32d0_0 .net "out0", 0 0, L_0x2bf9960; 1 drivers
+v0x24c1610_0 .net "out1", 0 0, L_0x2bf9a70; 1 drivers
+v0x24c16b0_0 .alias "outfinal", 0 0, v0x24c9360_0;
+S_0x24bbb50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24bd7e0;
+ .timescale -9 -12;
+L_0x2bf9de0/d .functor NOT 1, L_0x2bfa310, C4<0>, C4<0>, C4<0>;
+L_0x2bf9de0 .delay (10000,10000,10000) L_0x2bf9de0/d;
+L_0x2bf9ea0/d .functor AND 1, L_0x2bf9bc0, L_0x2bf9de0, C4<1>, C4<1>;
+L_0x2bf9ea0 .delay (20000,20000,20000) L_0x2bf9ea0/d;
+L_0x2bf9ff0/d .functor AND 1, L_0x2bf93c0, L_0x2bfa310, C4<1>, C4<1>;
+L_0x2bf9ff0 .delay (20000,20000,20000) L_0x2bf9ff0/d;
+L_0x2bfa140/d .functor OR 1, L_0x2bf9ea0, L_0x2bf9ff0, C4<0>, C4<0>;
+L_0x2bfa140 .delay (20000,20000,20000) L_0x2bfa140/d;
+v0x24c0960_0 .net "S", 0 0, L_0x2bfa310; 1 drivers
+v0x24c09e0_0 .alias "in0", 0 0, v0x24c9360_0;
+v0x24c0700_0 .alias "in1", 0 0, v0x24c6380_0;
+v0x24c0780_0 .net "nS", 0 0, L_0x2bf9de0; 1 drivers
+v0x24c0450_0 .net "out0", 0 0, L_0x2bf9ea0; 1 drivers
+v0x24c04d0_0 .net "out1", 0 0, L_0x2bf9ff0; 1 drivers
+v0x24be990_0 .alias "outfinal", 0 0, v0x24c4490_0;
+S_0x24e7da0 .scope generate, "orbits[12]" "orbits[12]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x243a028 .param/l "i" 3 258, +C4<01100>;
+S_0x24e5520 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24e7da0;
+ .timescale -9 -12;
+L_0x2bf9360/d .functor NOR 1, L_0x2bfa4f0, L_0x2bfb880, C4<0>, C4<0>;
+L_0x2bf9360 .delay (10000,10000,10000) L_0x2bf9360/d;
+L_0x2bfa690/d .functor NOT 1, L_0x2bf9360, C4<0>, C4<0>, C4<0>;
+L_0x2bfa690 .delay (10000,10000,10000) L_0x2bfa690/d;
+L_0x2bfa7c0/d .functor NAND 1, L_0x2bfa4f0, L_0x2bfb880, C4<1>, C4<1>;
+L_0x2bfa7c0 .delay (10000,10000,10000) L_0x2bfa7c0/d;
+L_0x2bfa940/d .functor NAND 1, L_0x2bfa7c0, L_0x2bfa690, C4<1>, C4<1>;
+L_0x2bfa940 .delay (10000,10000,10000) L_0x2bfa940/d;
+L_0x2bfaa50/d .functor NOT 1, L_0x2bfa940, C4<0>, C4<0>, C4<0>;
+L_0x2bfaa50 .delay (10000,10000,10000) L_0x2bfaa50/d;
+v0x24b7ad0_0 .net "A", 0 0, L_0x2bfa4f0; 1 drivers
+v0x24b7b70_0 .net "AnandB", 0 0, L_0x2bfa7c0; 1 drivers
+v0x24b5d80_0 .net "AnorB", 0 0, L_0x2bf9360; 1 drivers
+v0x24b5e00_0 .net "AorB", 0 0, L_0x2bfa690; 1 drivers
+v0x24bac50_0 .net "AxorB", 0 0, L_0x2bfaa50; 1 drivers
+v0x24bacd0_0 .net "B", 0 0, L_0x2bfb880; 1 drivers
+v0x24ba9a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24baa20_0 .net "OrNorXorOut", 0 0, L_0x2bfb450; 1 drivers
+v0x24b8d10_0 .net "XorNor", 0 0, L_0x2bfaed0; 1 drivers
+v0x24b8d90_0 .net "nXor", 0 0, L_0x2bfa940; 1 drivers
+L_0x2bfb050 .part v0x2960210_0, 2, 1;
+L_0x2bfb620 .part v0x2960210_0, 0, 1;
+S_0x24dccd0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24e5520;
+ .timescale -9 -12;
+L_0x2bfabb0/d .functor NOT 1, L_0x2bfb050, C4<0>, C4<0>, C4<0>;
+L_0x2bfabb0 .delay (10000,10000,10000) L_0x2bfabb0/d;
+L_0x2bfac70/d .functor AND 1, L_0x2bfaa50, L_0x2bfabb0, C4<1>, C4<1>;
+L_0x2bfac70 .delay (20000,20000,20000) L_0x2bfac70/d;
+L_0x2bfad80/d .functor AND 1, L_0x2bf9360, L_0x2bfb050, C4<1>, C4<1>;
+L_0x2bfad80 .delay (20000,20000,20000) L_0x2bfad80/d;
+L_0x2bfaed0/d .functor OR 1, L_0x2bfac70, L_0x2bfad80, C4<0>, C4<0>;
+L_0x2bfaed0 .delay (20000,20000,20000) L_0x2bfaed0/d;
+v0x24ba550_0 .net "S", 0 0, L_0x2bfb050; 1 drivers
+v0x24d9e90_0 .alias "in0", 0 0, v0x24bac50_0;
+v0x24d9f10_0 .alias "in1", 0 0, v0x24b5d80_0;
+v0x24d7050_0 .net "nS", 0 0, L_0x2bfabb0; 1 drivers
+v0x24d70d0_0 .net "out0", 0 0, L_0x2bfac70; 1 drivers
+v0x250ef00_0 .net "out1", 0 0, L_0x2bfad80; 1 drivers
+v0x250efa0_0 .alias "outfinal", 0 0, v0x24b8d10_0;
+S_0x24e4fa0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24e5520;
+ .timescale -9 -12;
+L_0x2bfb0f0/d .functor NOT 1, L_0x2bfb620, C4<0>, C4<0>, C4<0>;
+L_0x2bfb0f0 .delay (10000,10000,10000) L_0x2bfb0f0/d;
+L_0x2bfb1b0/d .functor AND 1, L_0x2bfaed0, L_0x2bfb0f0, C4<1>, C4<1>;
+L_0x2bfb1b0 .delay (20000,20000,20000) L_0x2bfb1b0/d;
+L_0x2bfb300/d .functor AND 1, L_0x2bfa690, L_0x2bfb620, C4<1>, C4<1>;
+L_0x2bfb300 .delay (20000,20000,20000) L_0x2bfb300/d;
+L_0x2bfb450/d .functor OR 1, L_0x2bfb1b0, L_0x2bfb300, C4<0>, C4<0>;
+L_0x2bfb450 .delay (20000,20000,20000) L_0x2bfb450/d;
+v0x24e2720_0 .net "S", 0 0, L_0x2bfb620; 1 drivers
+v0x24e27a0_0 .alias "in0", 0 0, v0x24b8d10_0;
+v0x24e21a0_0 .alias "in1", 0 0, v0x24b5e00_0;
+v0x24e2220_0 .net "nS", 0 0, L_0x2bfb0f0; 1 drivers
+v0x24dfb10_0 .net "out0", 0 0, L_0x2bfb1b0; 1 drivers
+v0x24dfb90_0 .net "out1", 0 0, L_0x2bfb300; 1 drivers
+v0x24ba4d0_0 .alias "outfinal", 0 0, v0x24baa20_0;
+S_0x2504ea0 .scope generate, "orbits[13]" "orbits[13]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2434b58 .param/l "i" 3 258, +C4<01101>;
+S_0x2504920 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2504ea0;
+ .timescale -9 -12;
+L_0x2bfa590/d .functor NOR 1, L_0x2bfcaa0, L_0x2bfb920, C4<0>, C4<0>;
+L_0x2bfa590 .delay (10000,10000,10000) L_0x2bfa590/d;
+L_0x2bfb7f0/d .functor NOT 1, L_0x2bfa590, C4<0>, C4<0>, C4<0>;
+L_0x2bfb7f0 .delay (10000,10000,10000) L_0x2bfb7f0/d;
+L_0x2bfbb00/d .functor NAND 1, L_0x2bfcaa0, L_0x2bfb920, C4<1>, C4<1>;
+L_0x2bfbb00 .delay (10000,10000,10000) L_0x2bfbb00/d;
+L_0x2bfbc80/d .functor NAND 1, L_0x2bfbb00, L_0x2bfb7f0, C4<1>, C4<1>;
+L_0x2bfbc80 .delay (10000,10000,10000) L_0x2bfbc80/d;
+L_0x2bfbd90/d .functor NOT 1, L_0x2bfbc80, C4<0>, C4<0>, C4<0>;
+L_0x2bfbd90 .delay (10000,10000,10000) L_0x2bfbd90/d;
+v0x24edf20_0 .net "A", 0 0, L_0x2bfcaa0; 1 drivers
+v0x24edfc0_0 .net "AnandB", 0 0, L_0x2bfbb00; 1 drivers
+v0x24ed9a0_0 .net "AnorB", 0 0, L_0x2bfa590; 1 drivers
+v0x24eda20_0 .net "AorB", 0 0, L_0x2bfb7f0; 1 drivers
+v0x24eb120_0 .net "AxorB", 0 0, L_0x2bfbd90; 1 drivers
+v0x24eb1a0_0 .net "B", 0 0, L_0x2bfb920; 1 drivers
+v0x24eaba0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24eac20_0 .net "OrNorXorOut", 0 0, L_0x2bfc790; 1 drivers
+v0x24e8320_0 .net "XorNor", 0 0, L_0x2bfc210; 1 drivers
+v0x24e83a0_0 .net "nXor", 0 0, L_0x2bfbc80; 1 drivers
+L_0x2bfc390 .part v0x2960210_0, 2, 1;
+L_0x2bfc960 .part v0x2960210_0, 0, 1;
+S_0x24f97b0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2504920;
+ .timescale -9 -12;
+L_0x2bfbef0/d .functor NOT 1, L_0x2bfc390, C4<0>, C4<0>, C4<0>;
+L_0x2bfbef0 .delay (10000,10000,10000) L_0x2bfbef0/d;
+L_0x2bfbfb0/d .functor AND 1, L_0x2bfbd90, L_0x2bfbef0, C4<1>, C4<1>;
+L_0x2bfbfb0 .delay (20000,20000,20000) L_0x2bfbfb0/d;
+L_0x2bfc0c0/d .functor AND 1, L_0x2bfa590, L_0x2bfc390, C4<1>, C4<1>;
+L_0x2bfc0c0 .delay (20000,20000,20000) L_0x2bfc0c0/d;
+L_0x2bfc210/d .functor OR 1, L_0x2bfbfb0, L_0x2bfc0c0, C4<0>, C4<0>;
+L_0x2bfc210 .delay (20000,20000,20000) L_0x2bfc210/d;
+v0x24bd390_0 .net "S", 0 0, L_0x2bfc390; 1 drivers
+v0x24f6970_0 .alias "in0", 0 0, v0x24eb120_0;
+v0x24f69f0_0 .alias "in1", 0 0, v0x24ed9a0_0;
+v0x24f3b30_0 .net "nS", 0 0, L_0x2bfbef0; 1 drivers
+v0x24f3bb0_0 .net "out0", 0 0, L_0x2bfbfb0; 1 drivers
+v0x24f0cf0_0 .net "out1", 0 0, L_0x2bfc0c0; 1 drivers
+v0x24f0d90_0 .alias "outfinal", 0 0, v0x24e8320_0;
+S_0x25020a0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2504920;
+ .timescale -9 -12;
+L_0x2bfc430/d .functor NOT 1, L_0x2bfc960, C4<0>, C4<0>, C4<0>;
+L_0x2bfc430 .delay (10000,10000,10000) L_0x2bfc430/d;
+L_0x2bfc4f0/d .functor AND 1, L_0x2bfc210, L_0x2bfc430, C4<1>, C4<1>;
+L_0x2bfc4f0 .delay (20000,20000,20000) L_0x2bfc4f0/d;
+L_0x2bfc640/d .functor AND 1, L_0x2bfb7f0, L_0x2bfc960, C4<1>, C4<1>;
+L_0x2bfc640 .delay (20000,20000,20000) L_0x2bfc640/d;
+L_0x2bfc790/d .functor OR 1, L_0x2bfc4f0, L_0x2bfc640, C4<0>, C4<0>;
+L_0x2bfc790 .delay (20000,20000,20000) L_0x2bfc790/d;
+v0x2501b20_0 .net "S", 0 0, L_0x2bfc960; 1 drivers
+v0x2501ba0_0 .alias "in0", 0 0, v0x24e8320_0;
+v0x24ff430_0 .alias "in1", 0 0, v0x24eda20_0;
+v0x24ff4b0_0 .net "nS", 0 0, L_0x2bfc430; 1 drivers
+v0x24fc5f0_0 .net "out0", 0 0, L_0x2bfc4f0; 1 drivers
+v0x24fc670_0 .net "out1", 0 0, L_0x2bfc640; 1 drivers
+v0x24bd310_0 .alias "outfinal", 0 0, v0x24eac20_0;
+S_0x24c5bb0 .scope generate, "orbits[14]" "orbits[14]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2451568 .param/l "i" 3 258, +C4<01110>;
+S_0x24c5630 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24c5bb0;
+ .timescale -9 -12;
+L_0x2bfb9c0/d .functor NOR 1, L_0x2bfcb40, L_0x2bfcbe0, C4<0>, C4<0>;
+L_0x2bfb9c0 .delay (10000,10000,10000) L_0x2bfb9c0/d;
+L_0x2bfcd10/d .functor NOT 1, L_0x2bfb9c0, C4<0>, C4<0>, C4<0>;
+L_0x2bfcd10 .delay (10000,10000,10000) L_0x2bfcd10/d;
+L_0x2bfce20/d .functor NAND 1, L_0x2bfcb40, L_0x2bfcbe0, C4<1>, C4<1>;
+L_0x2bfce20 .delay (10000,10000,10000) L_0x2bfce20/d;
+L_0x2bfcf80/d .functor NAND 1, L_0x2bfce20, L_0x2bfcd10, C4<1>, C4<1>;
+L_0x2bfcf80 .delay (10000,10000,10000) L_0x2bfcf80/d;
+L_0x2bfd090/d .functor NOT 1, L_0x2bfcf80, C4<0>, C4<0>, C4<0>;
+L_0x2bfd090 .delay (10000,10000,10000) L_0x2bfd090/d;
+v0x24bfb90_0 .net "A", 0 0, L_0x2bfcb40; 1 drivers
+v0x24bfc10_0 .net "AnandB", 0 0, L_0x2bfce20; 1 drivers
+v0x250aaa0_0 .net "AnorB", 0 0, L_0x2bfb9c0; 1 drivers
+v0x250ab20_0 .net "AorB", 0 0, L_0x2bfcd10; 1 drivers
+v0x250a520_0 .net "AxorB", 0 0, L_0x2bfd090; 1 drivers
+v0x250a5a0_0 .net "B", 0 0, L_0x2bfcbe0; 1 drivers
+v0x2507ca0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2507d20_0 .net "OrNorXorOut", 0 0, L_0x2bfda90; 1 drivers
+v0x2507720_0 .net "XorNor", 0 0, L_0x2bfd510; 1 drivers
+v0x25077a0_0 .net "nXor", 0 0, L_0x2bfcf80; 1 drivers
+L_0x2bfd690 .part v0x2960210_0, 2, 1;
+L_0x2bfdc60 .part v0x2960210_0, 0, 1;
+S_0x2510b30 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24c5630;
+ .timescale -9 -12;
+L_0x2bfd1f0/d .functor NOT 1, L_0x2bfd690, C4<0>, C4<0>, C4<0>;
+L_0x2bfd1f0 .delay (10000,10000,10000) L_0x2bfd1f0/d;
+L_0x2bfd2b0/d .functor AND 1, L_0x2bfd090, L_0x2bfd1f0, C4<1>, C4<1>;
+L_0x2bfd2b0 .delay (20000,20000,20000) L_0x2bfd2b0/d;
+L_0x2bfd3c0/d .functor AND 1, L_0x2bfb9c0, L_0x2bfd690, C4<1>, C4<1>;
+L_0x2bfd3c0 .delay (20000,20000,20000) L_0x2bfd3c0/d;
+L_0x2bfd510/d .functor OR 1, L_0x2bfd2b0, L_0x2bfd3c0, C4<0>, C4<0>;
+L_0x2bfd510 .delay (20000,20000,20000) L_0x2bfd510/d;
+v0x2510e50_0 .net "S", 0 0, L_0x2bfd690; 1 drivers
+v0x2510670_0 .alias "in0", 0 0, v0x250a520_0;
+v0x25106f0_0 .alias "in1", 0 0, v0x250aaa0_0;
+v0x250d8a0_0 .net "nS", 0 0, L_0x2bfd1f0; 1 drivers
+v0x250d920_0 .net "out0", 0 0, L_0x2bfd2b0; 1 drivers
+v0x250d320_0 .net "out1", 0 0, L_0x2bfd3c0; 1 drivers
+v0x250d3a0_0 .alias "outfinal", 0 0, v0x2507720_0;
+S_0x24c2db0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24c5630;
+ .timescale -9 -12;
+L_0x2bfd730/d .functor NOT 1, L_0x2bfdc60, C4<0>, C4<0>, C4<0>;
+L_0x2bfd730 .delay (10000,10000,10000) L_0x2bfd730/d;
+L_0x2bfd7f0/d .functor AND 1, L_0x2bfd510, L_0x2bfd730, C4<1>, C4<1>;
+L_0x2bfd7f0 .delay (20000,20000,20000) L_0x2bfd7f0/d;
+L_0x2bfd940/d .functor AND 1, L_0x2bfcd10, L_0x2bfdc60, C4<1>, C4<1>;
+L_0x2bfd940 .delay (20000,20000,20000) L_0x2bfd940/d;
+L_0x2bfda90/d .functor OR 1, L_0x2bfd7f0, L_0x2bfd940, C4<0>, C4<0>;
+L_0x2bfda90 .delay (20000,20000,20000) L_0x2bfda90/d;
+v0x24b7600_0 .net "S", 0 0, L_0x2bfdc60; 1 drivers
+v0x24b7680_0 .alias "in0", 0 0, v0x2507720_0;
+v0x24c2830_0 .alias "in1", 0 0, v0x250ab20_0;
+v0x24c28b0_0 .net "nS", 0 0, L_0x2bfd730; 1 drivers
+v0x2511040_0 .net "out0", 0 0, L_0x2bfd7f0; 1 drivers
+v0x25110c0_0 .net "out1", 0 0, L_0x2bfd940; 1 drivers
+v0x2510dd0_0 .alias "outfinal", 0 0, v0x2507d20_0;
+S_0x24a6dc0 .scope generate, "orbits[15]" "orbits[15]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x247c5d8 .param/l "i" 3 258, +C4<01111>;
+S_0x24a5180 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24a6dc0;
+ .timescale -9 -12;
+L_0x2bfdf00/d .functor NOR 1, L_0x2bff0c0, L_0x2bfdda0, C4<0>, C4<0>;
+L_0x2bfdf00 .delay (10000,10000,10000) L_0x2bfdf00/d;
+L_0x2bfdff0/d .functor NOT 1, L_0x2bfdf00, C4<0>, C4<0>, C4<0>;
+L_0x2bfdff0 .delay (10000,10000,10000) L_0x2bfdff0/d;
+L_0x2bfe120/d .functor NAND 1, L_0x2bff0c0, L_0x2bfdda0, C4<1>, C4<1>;
+L_0x2bfe120 .delay (10000,10000,10000) L_0x2bfe120/d;
+L_0x2bfe2a0/d .functor NAND 1, L_0x2bfe120, L_0x2bfdff0, C4<1>, C4<1>;
+L_0x2bfe2a0 .delay (10000,10000,10000) L_0x2bfe2a0/d;
+L_0x2bfe3b0/d .functor NOT 1, L_0x2bfe2a0, C4<0>, C4<0>, C4<0>;
+L_0x2bfe3b0 .delay (10000,10000,10000) L_0x2bfe3b0/d;
+v0x24ce030_0 .net "A", 0 0, L_0x2bff0c0; 1 drivers
+v0x24ce0d0_0 .net "AnandB", 0 0, L_0x2bfe120; 1 drivers
+v0x24cb7b0_0 .net "AnorB", 0 0, L_0x2bfdf00; 1 drivers
+v0x24cb830_0 .net "AorB", 0 0, L_0x2bfdff0; 1 drivers
+v0x24cb230_0 .net "AxorB", 0 0, L_0x2bfe3b0; 1 drivers
+v0x24cb2b0_0 .net "B", 0 0, L_0x2bfdda0; 1 drivers
+v0x24c89b0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24c8a30_0 .net "OrNorXorOut", 0 0, L_0x2bfedb0; 1 drivers
+v0x24c8430_0 .net "XorNor", 0 0, L_0x2bfe830; 1 drivers
+v0x24c84b0_0 .net "nXor", 0 0, L_0x2bfe2a0; 1 drivers
+L_0x2bfe9b0 .part v0x2960210_0, 2, 1;
+L_0x2bfef80 .part v0x2960210_0, 0, 1;
+S_0x24a9df0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24a5180;
+ .timescale -9 -12;
+L_0x2bfe510/d .functor NOT 1, L_0x2bfe9b0, C4<0>, C4<0>, C4<0>;
+L_0x2bfe510 .delay (10000,10000,10000) L_0x2bfe510/d;
+L_0x2bfe5d0/d .functor AND 1, L_0x2bfe3b0, L_0x2bfe510, C4<1>, C4<1>;
+L_0x2bfe5d0 .delay (20000,20000,20000) L_0x2bfe5d0/d;
+L_0x2bfe6e0/d .functor AND 1, L_0x2bfdf00, L_0x2bfe9b0, C4<1>, C4<1>;
+L_0x2bfe6e0 .delay (20000,20000,20000) L_0x2bfe6e0/d;
+L_0x2bfe830/d .functor OR 1, L_0x2bfe5d0, L_0x2bfe6e0, C4<0>, C4<0>;
+L_0x2bfe830 .delay (20000,20000,20000) L_0x2bfe830/d;
+v0x24abab0_0 .net "S", 0 0, L_0x2bfe9b0; 1 drivers
+v0x24d4210_0 .alias "in0", 0 0, v0x24cb230_0;
+v0x24d4290_0 .alias "in1", 0 0, v0x24cb7b0_0;
+v0x24d13d0_0 .net "nS", 0 0, L_0x2bfe510; 1 drivers
+v0x24d1450_0 .net "out0", 0 0, L_0x2bfe5d0; 1 drivers
+v0x24ce5b0_0 .net "out1", 0 0, L_0x2bfe6e0; 1 drivers
+v0x24ce650_0 .alias "outfinal", 0 0, v0x24c8430_0;
+S_0x24addc0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24a5180;
+ .timescale -9 -12;
+L_0x2bfea50/d .functor NOT 1, L_0x2bfef80, C4<0>, C4<0>, C4<0>;
+L_0x2bfea50 .delay (10000,10000,10000) L_0x2bfea50/d;
+L_0x2bfeb10/d .functor AND 1, L_0x2bfe830, L_0x2bfea50, C4<1>, C4<1>;
+L_0x2bfeb10 .delay (20000,20000,20000) L_0x2bfeb10/d;
+L_0x2bfec60/d .functor AND 1, L_0x2bfdff0, L_0x2bfef80, C4<1>, C4<1>;
+L_0x2bfec60 .delay (20000,20000,20000) L_0x2bfec60/d;
+L_0x2bfedb0/d .functor OR 1, L_0x2bfeb10, L_0x2bfec60, C4<0>, C4<0>;
+L_0x2bfedb0 .delay (20000,20000,20000) L_0x2bfedb0/d;
+v0x24adb10_0 .net "S", 0 0, L_0x2bfef80; 1 drivers
+v0x24adb90_0 .alias "in0", 0 0, v0x24c8430_0;
+v0x24abf40_0 .alias "in1", 0 0, v0x24cb830_0;
+v0x24abfc0_0 .net "nS", 0 0, L_0x2bfea50; 1 drivers
+v0x24abce0_0 .net "out0", 0 0, L_0x2bfeb10; 1 drivers
+v0x24abd60_0 .net "out1", 0 0, L_0x2bfec60; 1 drivers
+v0x24aba30_0 .alias "outfinal", 0 0, v0x24c8a30_0;
+S_0x2496cd0 .scope generate, "orbits[16]" "orbits[16]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2499018 .param/l "i" 3 258, +C4<010000>;
+S_0x249f870 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2496cd0;
+ .timescale -9 -12;
+L_0x2bfde40/d .functor NOR 1, L_0x2bff160, L_0x2bff200, C4<0>, C4<0>;
+L_0x2bfde40 .delay (10000,10000,10000) L_0x2bfde40/d;
+L_0x2bff320/d .functor NOT 1, L_0x2bfde40, C4<0>, C4<0>, C4<0>;
+L_0x2bff320 .delay (10000,10000,10000) L_0x2bff320/d;
+L_0x2bff430/d .functor NAND 1, L_0x2bff160, L_0x2bff200, C4<1>, C4<1>;
+L_0x2bff430 .delay (10000,10000,10000) L_0x2bff430/d;
+L_0x2bff5b0/d .functor NAND 1, L_0x2bff430, L_0x2bff320, C4<1>, C4<1>;
+L_0x2bff5b0 .delay (10000,10000,10000) L_0x2bff5b0/d;
+L_0x2bff6c0/d .functor NOT 1, L_0x2bff5b0, C4<0>, C4<0>, C4<0>;
+L_0x2bff6c0 .delay (10000,10000,10000) L_0x2bff6c0/d;
+v0x24a0510_0 .net "A", 0 0, L_0x2bff160; 1 drivers
+v0x24a05b0_0 .net "AnandB", 0 0, L_0x2bff430; 1 drivers
+v0x24a9150_0 .net "AnorB", 0 0, L_0x2bfde40; 1 drivers
+v0x24a91d0_0 .net "AorB", 0 0, L_0x2bff320; 1 drivers
+v0x24a8ea0_0 .net "AxorB", 0 0, L_0x2bff6c0; 1 drivers
+v0x24a8f20_0 .net "B", 0 0, L_0x2bff200; 1 drivers
+v0x24a72d0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24a7350_0 .net "OrNorXorOut", 0 0, L_0x2c000c0; 1 drivers
+v0x24a7070_0 .net "XorNor", 0 0, L_0x2bffb40; 1 drivers
+v0x24a70f0_0 .net "nXor", 0 0, L_0x2bff5b0; 1 drivers
+L_0x2bffcc0 .part v0x2960210_0, 2, 1;
+L_0x2c00290 .part v0x2960210_0, 0, 1;
+S_0x24a4230 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x249f870;
+ .timescale -9 -12;
+L_0x2bff820/d .functor NOT 1, L_0x2bffcc0, C4<0>, C4<0>, C4<0>;
+L_0x2bff820 .delay (10000,10000,10000) L_0x2bff820/d;
+L_0x2bff8e0/d .functor AND 1, L_0x2bff6c0, L_0x2bff820, C4<1>, C4<1>;
+L_0x2bff8e0 .delay (20000,20000,20000) L_0x2bff8e0/d;
+L_0x2bff9f0/d .functor AND 1, L_0x2bfde40, L_0x2bffcc0, C4<1>, C4<1>;
+L_0x2bff9f0 .delay (20000,20000,20000) L_0x2bff9f0/d;
+L_0x2bffb40/d .functor OR 1, L_0x2bff8e0, L_0x2bff9f0, C4<0>, C4<0>;
+L_0x2bffb40 .delay (20000,20000,20000) L_0x2bffb40/d;
+v0x24a4560_0 .net "S", 0 0, L_0x2bffcc0; 1 drivers
+v0x24a2660_0 .alias "in0", 0 0, v0x24a8ea0_0;
+v0x24a26e0_0 .alias "in1", 0 0, v0x24a9150_0;
+v0x24a2400_0 .net "nS", 0 0, L_0x2bff820; 1 drivers
+v0x24a2480_0 .net "out0", 0 0, L_0x2bff8e0; 1 drivers
+v0x24a2150_0 .net "out1", 0 0, L_0x2bff9f0; 1 drivers
+v0x24a21f0_0 .alias "outfinal", 0 0, v0x24a7070_0;
+S_0x249f5c0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x249f870;
+ .timescale -9 -12;
+L_0x2bffd60/d .functor NOT 1, L_0x2c00290, C4<0>, C4<0>, C4<0>;
+L_0x2bffd60 .delay (10000,10000,10000) L_0x2bffd60/d;
+L_0x2bffe20/d .functor AND 1, L_0x2bffb40, L_0x2bffd60, C4<1>, C4<1>;
+L_0x2bffe20 .delay (20000,20000,20000) L_0x2bffe20/d;
+L_0x2bfff70/d .functor AND 1, L_0x2bff320, L_0x2c00290, C4<1>, C4<1>;
+L_0x2bfff70 .delay (20000,20000,20000) L_0x2bfff70/d;
+L_0x2c000c0/d .functor OR 1, L_0x2bffe20, L_0x2bfff70, C4<0>, C4<0>;
+L_0x2c000c0 .delay (20000,20000,20000) L_0x2c000c0/d;
+v0x249d8c0_0 .net "S", 0 0, L_0x2c00290; 1 drivers
+v0x249d940_0 .alias "in0", 0 0, v0x24a7070_0;
+v0x249d610_0 .alias "in1", 0 0, v0x24a91d0_0;
+v0x249d690_0 .net "nS", 0 0, L_0x2bffd60; 1 drivers
+v0x249b980_0 .net "out0", 0 0, L_0x2bffe20; 1 drivers
+v0x249ba00_0 .net "out1", 0 0, L_0x2bfff70; 1 drivers
+v0x24a44e0_0 .alias "outfinal", 0 0, v0x24a7350_0;
+S_0x248a390 .scope generate, "orbits[17]" "orbits[17]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24ce418 .param/l "i" 3 258, +C4<010001>;
+S_0x2488750 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x248a390;
+ .timescale -9 -12;
+L_0x2c00560/d .functor NOR 1, L_0x2c01700, L_0x2c003d0, C4<0>, C4<0>;
+L_0x2c00560 .delay (10000,10000,10000) L_0x2c00560/d;
+L_0x2c00650/d .functor NOT 1, L_0x2c00560, C4<0>, C4<0>, C4<0>;
+L_0x2c00650 .delay (10000,10000,10000) L_0x2c00650/d;
+L_0x2c00760/d .functor NAND 1, L_0x2c01700, L_0x2c003d0, C4<1>, C4<1>;
+L_0x2c00760 .delay (10000,10000,10000) L_0x2c00760/d;
+L_0x2c008e0/d .functor NAND 1, L_0x2c00760, L_0x2c00650, C4<1>, C4<1>;
+L_0x2c008e0 .delay (10000,10000,10000) L_0x2c008e0/d;
+L_0x2c009f0/d .functor NOT 1, L_0x2c008e0, C4<0>, C4<0>, C4<0>;
+L_0x2c009f0 .delay (10000,10000,10000) L_0x2c009f0/d;
+v0x2492020_0 .net "A", 0 0, L_0x2c01700; 1 drivers
+v0x24920c0_0 .net "AnandB", 0 0, L_0x2c00760; 1 drivers
+v0x249ace0_0 .net "AnorB", 0 0, L_0x2c00560; 1 drivers
+v0x249ad60_0 .net "AorB", 0 0, L_0x2c00650; 1 drivers
+v0x249aa30_0 .net "AxorB", 0 0, L_0x2c009f0; 1 drivers
+v0x249aab0_0 .net "B", 0 0, L_0x2c003d0; 1 drivers
+v0x2498c10_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2498c90_0 .net "OrNorXorOut", 0 0, L_0x2c013f0; 1 drivers
+v0x2498960_0 .net "XorNor", 0 0, L_0x2c00e70; 1 drivers
+v0x24989e0_0 .net "nXor", 0 0, L_0x2c008e0; 1 drivers
+L_0x2c00ff0 .part v0x2960210_0, 2, 1;
+L_0x2c015c0 .part v0x2960210_0, 0, 1;
+S_0x2496030 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2488750;
+ .timescale -9 -12;
+L_0x2c00b50/d .functor NOT 1, L_0x2c00ff0, C4<0>, C4<0>, C4<0>;
+L_0x2c00b50 .delay (10000,10000,10000) L_0x2c00b50/d;
+L_0x2c00c10/d .functor AND 1, L_0x2c009f0, L_0x2c00b50, C4<1>, C4<1>;
+L_0x2c00c10 .delay (20000,20000,20000) L_0x2c00c10/d;
+L_0x2c00d20/d .functor AND 1, L_0x2c00560, L_0x2c00ff0, C4<1>, C4<1>;
+L_0x2c00d20 .delay (20000,20000,20000) L_0x2c00d20/d;
+L_0x2c00e70/d .functor OR 1, L_0x2c00c10, L_0x2c00d20, C4<0>, C4<0>;
+L_0x2c00e70 .delay (20000,20000,20000) L_0x2c00e70/d;
+v0x248d440_0 .net "S", 0 0, L_0x2c00ff0; 1 drivers
+v0x2495d80_0 .alias "in0", 0 0, v0x249aa30_0;
+v0x2495e00_0 .alias "in1", 0 0, v0x249ace0_0;
+v0x2493f60_0 .net "nS", 0 0, L_0x2c00b50; 1 drivers
+v0x2493fe0_0 .net "out0", 0 0, L_0x2c00c10; 1 drivers
+v0x2493cb0_0 .net "out1", 0 0, L_0x2c00d20; 1 drivers
+v0x2493d50_0 .alias "outfinal", 0 0, v0x2498960_0;
+S_0x2491380 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2488750;
+ .timescale -9 -12;
+L_0x2c01090/d .functor NOT 1, L_0x2c015c0, C4<0>, C4<0>, C4<0>;
+L_0x2c01090 .delay (10000,10000,10000) L_0x2c01090/d;
+L_0x2c01150/d .functor AND 1, L_0x2c00e70, L_0x2c01090, C4<1>, C4<1>;
+L_0x2c01150 .delay (20000,20000,20000) L_0x2c01150/d;
+L_0x2c012a0/d .functor AND 1, L_0x2c00650, L_0x2c015c0, C4<1>, C4<1>;
+L_0x2c012a0 .delay (20000,20000,20000) L_0x2c012a0/d;
+L_0x2c013f0/d .functor OR 1, L_0x2c01150, L_0x2c012a0, C4<0>, C4<0>;
+L_0x2c013f0 .delay (20000,20000,20000) L_0x2c013f0/d;
+v0x24910d0_0 .net "S", 0 0, L_0x2c015c0; 1 drivers
+v0x2491150_0 .alias "in0", 0 0, v0x2498960_0;
+v0x248f2b0_0 .alias "in1", 0 0, v0x249ad60_0;
+v0x248f330_0 .net "nS", 0 0, L_0x2c01090; 1 drivers
+v0x248f000_0 .net "out0", 0 0, L_0x2c01150; 1 drivers
+v0x248f080_0 .net "out1", 0 0, L_0x2c012a0; 1 drivers
+v0x248d3c0_0 .alias "outfinal", 0 0, v0x2498c90_0;
+S_0x247bf20 .scope generate, "orbits[18]" "orbits[18]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24c2c18 .param/l "i" 3 258, +C4<010010>;
+S_0x247a290 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x247bf20;
+ .timescale -9 -12;
+L_0x2c00470/d .functor NOR 1, L_0x2c017a0, L_0x2c01840, C4<0>, C4<0>;
+L_0x2c00470 .delay (10000,10000,10000) L_0x2c00470/d;
+L_0x2c01940/d .functor NOT 1, L_0x2c00470, C4<0>, C4<0>, C4<0>;
+L_0x2c01940 .delay (10000,10000,10000) L_0x2c01940/d;
+L_0x2c01a70/d .functor NAND 1, L_0x2c017a0, L_0x2c01840, C4<1>, C4<1>;
+L_0x2c01a70 .delay (10000,10000,10000) L_0x2c01a70/d;
+L_0x2c01bf0/d .functor NAND 1, L_0x2c01a70, L_0x2c01940, C4<1>, C4<1>;
+L_0x2c01bf0 .delay (10000,10000,10000) L_0x2c01bf0/d;
+L_0x2c01d00/d .functor NOT 1, L_0x2c01bf0, C4<0>, C4<0>, C4<0>;
+L_0x2c01d00 .delay (10000,10000,10000) L_0x2c01d00/d;
+v0x2483ae0_0 .net "A", 0 0, L_0x2c017a0; 1 drivers
+v0x2483b80_0 .net "AnandB", 0 0, L_0x2c01a70; 1 drivers
+v0x248c720_0 .net "AnorB", 0 0, L_0x2c00470; 1 drivers
+v0x248c7a0_0 .net "AorB", 0 0, L_0x2c01940; 1 drivers
+v0x248c470_0 .net "AxorB", 0 0, L_0x2c01d00; 1 drivers
+v0x248c4f0_0 .net "B", 0 0, L_0x2c01840; 1 drivers
+v0x248a8a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x248a920_0 .net "OrNorXorOut", 0 0, L_0x2c02700; 1 drivers
+v0x248a640_0 .net "XorNor", 0 0, L_0x2c02180; 1 drivers
+v0x248a6c0_0 .net "nXor", 0 0, L_0x2c01bf0; 1 drivers
+L_0x2c02300 .part v0x2960210_0, 2, 1;
+L_0x2c028d0 .part v0x2960210_0, 0, 1;
+S_0x2487800 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x247a290;
+ .timescale -9 -12;
+L_0x2c01e60/d .functor NOT 1, L_0x2c02300, C4<0>, C4<0>, C4<0>;
+L_0x2c01e60 .delay (10000,10000,10000) L_0x2c01e60/d;
+L_0x2c01f20/d .functor AND 1, L_0x2c01d00, L_0x2c01e60, C4<1>, C4<1>;
+L_0x2c01f20 .delay (20000,20000,20000) L_0x2c01f20/d;
+L_0x2c02030/d .functor AND 1, L_0x2c00470, L_0x2c02300, C4<1>, C4<1>;
+L_0x2c02030 .delay (20000,20000,20000) L_0x2c02030/d;
+L_0x2c02180/d .functor OR 1, L_0x2c01f20, L_0x2c02030, C4<0>, C4<0>;
+L_0x2c02180 .delay (20000,20000,20000) L_0x2c02180/d;
+v0x2487b30_0 .net "S", 0 0, L_0x2c02300; 1 drivers
+v0x2485c30_0 .alias "in0", 0 0, v0x248c470_0;
+v0x2485cb0_0 .alias "in1", 0 0, v0x248c720_0;
+v0x24859d0_0 .net "nS", 0 0, L_0x2c01e60; 1 drivers
+v0x2485a50_0 .net "out0", 0 0, L_0x2c01f20; 1 drivers
+v0x2485720_0 .net "out1", 0 0, L_0x2c02030; 1 drivers
+v0x24857c0_0 .alias "outfinal", 0 0, v0x248a640_0;
+S_0x2482e40 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x247a290;
+ .timescale -9 -12;
+L_0x2c023a0/d .functor NOT 1, L_0x2c028d0, C4<0>, C4<0>, C4<0>;
+L_0x2c023a0 .delay (10000,10000,10000) L_0x2c023a0/d;
+L_0x2c02460/d .functor AND 1, L_0x2c02180, L_0x2c023a0, C4<1>, C4<1>;
+L_0x2c02460 .delay (20000,20000,20000) L_0x2c02460/d;
+L_0x2c025b0/d .functor AND 1, L_0x2c01940, L_0x2c028d0, C4<1>, C4<1>;
+L_0x2c025b0 .delay (20000,20000,20000) L_0x2c025b0/d;
+L_0x2c02700/d .functor OR 1, L_0x2c02460, L_0x2c025b0, C4<0>, C4<0>;
+L_0x2c02700 .delay (20000,20000,20000) L_0x2c02700/d;
+v0x2482b90_0 .net "S", 0 0, L_0x2c028d0; 1 drivers
+v0x2482c10_0 .alias "in0", 0 0, v0x248a640_0;
+v0x2480fb0_0 .alias "in1", 0 0, v0x248c7a0_0;
+v0x2481030_0 .net "nS", 0 0, L_0x2c023a0; 1 drivers
+v0x2480d50_0 .net "out0", 0 0, L_0x2c02460; 1 drivers
+v0x2480dd0_0 .net "out1", 0 0, L_0x2c025b0; 1 drivers
+v0x2487ab0_0 .alias "outfinal", 0 0, v0x248a920_0;
+S_0x246dba0 .scope generate, "orbits[19]" "orbits[19]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x250a908 .param/l "i" 3 258, +C4<010011>;
+S_0x246d8f0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x246dba0;
+ .timescale -9 -12;
+L_0x2c018e0/d .functor NOR 1, L_0x2c03d30, L_0x2c02a10, C4<0>, C4<0>;
+L_0x2c018e0 .delay (10000,10000,10000) L_0x2c018e0/d;
+L_0x2c02c60/d .functor NOT 1, L_0x2c018e0, C4<0>, C4<0>, C4<0>;
+L_0x2c02c60 .delay (10000,10000,10000) L_0x2c02c60/d;
+L_0x2c02d90/d .functor NAND 1, L_0x2c03d30, L_0x2c02a10, C4<1>, C4<1>;
+L_0x2c02d90 .delay (10000,10000,10000) L_0x2c02d90/d;
+L_0x2c02f10/d .functor NAND 1, L_0x2c02d90, L_0x2c02c60, C4<1>, C4<1>;
+L_0x2c02f10 .delay (10000,10000,10000) L_0x2c02f10/d;
+L_0x2c03020/d .functor NOT 1, L_0x2c02f10, C4<0>, C4<0>, C4<0>;
+L_0x2c03020 .delay (10000,10000,10000) L_0x2c03020/d;
+v0x2477270_0 .net "A", 0 0, L_0x2c03d30; 1 drivers
+v0x2477310_0 .net "AnandB", 0 0, L_0x2c02d90; 1 drivers
+v0x24755e0_0 .net "AnorB", 0 0, L_0x2c018e0; 1 drivers
+v0x2475660_0 .net "AorB", 0 0, L_0x2c02c60; 1 drivers
+v0x247e2a0_0 .net "AxorB", 0 0, L_0x2c03020; 1 drivers
+v0x247e320_0 .net "B", 0 0, L_0x2c02a10; 1 drivers
+v0x247dff0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x247e070_0 .net "OrNorXorOut", 0 0, L_0x2c03a20; 1 drivers
+v0x247c1d0_0 .net "XorNor", 0 0, L_0x2c034a0; 1 drivers
+v0x247c250_0 .net "nXor", 0 0, L_0x2c02f10; 1 drivers
+L_0x2c03620 .part v0x2960210_0, 2, 1;
+L_0x2c03bf0 .part v0x2960210_0, 0, 1;
+S_0x2470930 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x246d8f0;
+ .timescale -9 -12;
+L_0x2c03180/d .functor NOT 1, L_0x2c03620, C4<0>, C4<0>, C4<0>;
+L_0x2c03180 .delay (10000,10000,10000) L_0x2c03180/d;
+L_0x2c03240/d .functor AND 1, L_0x2c03020, L_0x2c03180, C4<1>, C4<1>;
+L_0x2c03240 .delay (20000,20000,20000) L_0x2c03240/d;
+L_0x2c03350/d .functor AND 1, L_0x2c018e0, L_0x2c03620, C4<1>, C4<1>;
+L_0x2c03350 .delay (20000,20000,20000) L_0x2c03350/d;
+L_0x2c034a0/d .functor OR 1, L_0x2c03240, L_0x2c03350, C4<0>, C4<0>;
+L_0x2c034a0 .delay (20000,20000,20000) L_0x2c034a0/d;
+v0x2472640_0 .net "S", 0 0, L_0x2c03620; 1 drivers
+v0x24795f0_0 .alias "in0", 0 0, v0x247e2a0_0;
+v0x2479670_0 .alias "in1", 0 0, v0x24755e0_0;
+v0x2479340_0 .net "nS", 0 0, L_0x2c03180; 1 drivers
+v0x24793c0_0 .net "out0", 0 0, L_0x2c03240; 1 drivers
+v0x2477520_0 .net "out1", 0 0, L_0x2c03350; 1 drivers
+v0x24775c0_0 .alias "outfinal", 0 0, v0x247c1d0_0;
+S_0x246bcb0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x246d8f0;
+ .timescale -9 -12;
+L_0x2c036c0/d .functor NOT 1, L_0x2c03bf0, C4<0>, C4<0>, C4<0>;
+L_0x2c036c0 .delay (10000,10000,10000) L_0x2c036c0/d;
+L_0x2c03780/d .functor AND 1, L_0x2c034a0, L_0x2c036c0, C4<1>, C4<1>;
+L_0x2c03780 .delay (20000,20000,20000) L_0x2c03780/d;
+L_0x2c038d0/d .functor AND 1, L_0x2c02c60, L_0x2c03bf0, C4<1>, C4<1>;
+L_0x2c038d0 .delay (20000,20000,20000) L_0x2c038d0/d;
+L_0x2c03a20/d .functor OR 1, L_0x2c03780, L_0x2c038d0, C4<0>, C4<0>;
+L_0x2c03a20 .delay (20000,20000,20000) L_0x2c03a20/d;
+v0x2474940_0 .net "S", 0 0, L_0x2c03bf0; 1 drivers
+v0x24749c0_0 .alias "in0", 0 0, v0x247c1d0_0;
+v0x2474690_0 .alias "in1", 0 0, v0x2475660_0;
+v0x2474710_0 .net "nS", 0 0, L_0x2c036c0; 1 drivers
+v0x2472870_0 .net "out0", 0 0, L_0x2c03780; 1 drivers
+v0x24728f0_0 .net "out1", 0 0, L_0x2c038d0; 1 drivers
+v0x24725c0_0 .alias "outfinal", 0 0, v0x247e070_0;
+S_0x245d830 .scope generate, "orbits[20]" "orbits[20]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24ff298 .param/l "i" 3 258, +C4<010100>;
+S_0x24663a0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x245d830;
+ .timescale -9 -12;
+L_0x2c02ab0/d .functor NOR 1, L_0x2c03dd0, L_0x2c03e70, C4<0>, C4<0>;
+L_0x2c02ab0 .delay (10000,10000,10000) L_0x2c02ab0/d;
+L_0x2c03fa0/d .functor NOT 1, L_0x2c02ab0, C4<0>, C4<0>, C4<0>;
+L_0x2c03fa0 .delay (10000,10000,10000) L_0x2c03fa0/d;
+L_0x2c040b0/d .functor NAND 1, L_0x2c03dd0, L_0x2c03e70, C4<1>, C4<1>;
+L_0x2c040b0 .delay (10000,10000,10000) L_0x2c040b0/d;
+L_0x2c04230/d .functor NAND 1, L_0x2c040b0, L_0x2c03fa0, C4<1>, C4<1>;
+L_0x2c04230 .delay (10000,10000,10000) L_0x2c04230/d;
+L_0x2c04340/d .functor NOT 1, L_0x2c04230, C4<0>, C4<0>, C4<0>;
+L_0x2c04340 .delay (10000,10000,10000) L_0x2c04340/d;
+v0x2468c80_0 .net "A", 0 0, L_0x2c03dd0; 1 drivers
+v0x2468d20_0 .net "AnandB", 0 0, L_0x2c040b0; 1 drivers
+v0x2467040_0 .net "AnorB", 0 0, L_0x2c02ab0; 1 drivers
+v0x24670c0_0 .net "AorB", 0 0, L_0x2c03fa0; 1 drivers
+v0x246fc90_0 .net "AxorB", 0 0, L_0x2c04340; 1 drivers
+v0x246fd10_0 .net "B", 0 0, L_0x2c03e70; 1 drivers
+v0x246f9e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x246fa60_0 .net "OrNorXorOut", 0 0, L_0x2c04d40; 1 drivers
+v0x246de00_0 .net "XorNor", 0 0, L_0x2c047c0; 1 drivers
+v0x246de80_0 .net "nXor", 0 0, L_0x2c04230; 1 drivers
+L_0x2c04940 .part v0x2960210_0, 2, 1;
+L_0x2c04f10 .part v0x2960210_0, 0, 1;
+S_0x246b010 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24663a0;
+ .timescale -9 -12;
+L_0x2c044a0/d .functor NOT 1, L_0x2c04940, C4<0>, C4<0>, C4<0>;
+L_0x2c044a0 .delay (10000,10000,10000) L_0x2c044a0/d;
+L_0x2c04560/d .functor AND 1, L_0x2c04340, L_0x2c044a0, C4<1>, C4<1>;
+L_0x2c04560 .delay (20000,20000,20000) L_0x2c04560/d;
+L_0x2c04670/d .functor AND 1, L_0x2c02ab0, L_0x2c04940, C4<1>, C4<1>;
+L_0x2c04670 .delay (20000,20000,20000) L_0x2c04670/d;
+L_0x2c047c0/d .functor OR 1, L_0x2c04560, L_0x2c04670, C4<0>, C4<0>;
+L_0x2c047c0 .delay (20000,20000,20000) L_0x2c047c0/d;
+v0x2462450_0 .net "S", 0 0, L_0x2c04940; 1 drivers
+v0x246ad60_0 .alias "in0", 0 0, v0x246fc90_0;
+v0x246ade0_0 .alias "in1", 0 0, v0x2467040_0;
+v0x2469190_0 .net "nS", 0 0, L_0x2c044a0; 1 drivers
+v0x2469210_0 .net "out0", 0 0, L_0x2c04560; 1 drivers
+v0x2468f30_0 .net "out1", 0 0, L_0x2c04670; 1 drivers
+v0x2468fd0_0 .alias "outfinal", 0 0, v0x246de00_0;
+S_0x24660f0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24663a0;
+ .timescale -9 -12;
+L_0x2c049e0/d .functor NOT 1, L_0x2c04f10, C4<0>, C4<0>, C4<0>;
+L_0x2c049e0 .delay (10000,10000,10000) L_0x2c049e0/d;
+L_0x2c04aa0/d .functor AND 1, L_0x2c047c0, L_0x2c049e0, C4<1>, C4<1>;
+L_0x2c04aa0 .delay (20000,20000,20000) L_0x2c04aa0/d;
+L_0x2c04bf0/d .functor AND 1, L_0x2c03fa0, L_0x2c04f10, C4<1>, C4<1>;
+L_0x2c04bf0 .delay (20000,20000,20000) L_0x2c04bf0/d;
+L_0x2c04d40/d .functor OR 1, L_0x2c04aa0, L_0x2c04bf0, C4<0>, C4<0>;
+L_0x2c04d40 .delay (20000,20000,20000) L_0x2c04d40/d;
+v0x2464520_0 .net "S", 0 0, L_0x2c04f10; 1 drivers
+v0x24645a0_0 .alias "in0", 0 0, v0x246de00_0;
+v0x24642c0_0 .alias "in1", 0 0, v0x24670c0_0;
+v0x2464340_0 .net "nS", 0 0, L_0x2c049e0; 1 drivers
+v0x2464010_0 .net "out0", 0 0, L_0x2c04aa0; 1 drivers
+v0x2464090_0 .net "out1", 0 0, L_0x2c04bf0; 1 drivers
+v0x24623d0_0 .alias "outfinal", 0 0, v0x246fa60_0;
+S_0x2450eb0 .scope generate, "orbits[21]" "orbits[21]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24bd178 .param/l "i" 3 258, +C4<010101>;
+S_0x244f220 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2450eb0;
+ .timescale -9 -12;
+L_0x2c03f10/d .functor NOR 1, L_0x2c06380, L_0x2c05050, C4<0>, C4<0>;
+L_0x2c03f10 .delay (10000,10000,10000) L_0x2c03f10/d;
+L_0x2c052d0/d .functor NOT 1, L_0x2c03f10, C4<0>, C4<0>, C4<0>;
+L_0x2c052d0 .delay (10000,10000,10000) L_0x2c052d0/d;
+L_0x2c053e0/d .functor NAND 1, L_0x2c06380, L_0x2c05050, C4<1>, C4<1>;
+L_0x2c053e0 .delay (10000,10000,10000) L_0x2c053e0/d;
+L_0x2c05560/d .functor NAND 1, L_0x2c053e0, L_0x2c052d0, C4<1>, C4<1>;
+L_0x2c05560 .delay (10000,10000,10000) L_0x2c05560/d;
+L_0x2c05670/d .functor NOT 1, L_0x2c05560, C4<0>, C4<0>, C4<0>;
+L_0x2c05670 .delay (10000,10000,10000) L_0x2c05670/d;
+v0x2458b80_0 .net "A", 0 0, L_0x2c06380; 1 drivers
+v0x2458c20_0 .net "AnandB", 0 0, L_0x2c053e0; 1 drivers
+v0x2461730_0 .net "AnorB", 0 0, L_0x2c03f10; 1 drivers
+v0x24617b0_0 .net "AorB", 0 0, L_0x2c052d0; 1 drivers
+v0x2461480_0 .net "AxorB", 0 0, L_0x2c05670; 1 drivers
+v0x2461500_0 .net "B", 0 0, L_0x2c05050; 1 drivers
+v0x245f8a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x245f920_0 .net "OrNorXorOut", 0 0, L_0x2c06070; 1 drivers
+v0x245f640_0 .net "XorNor", 0 0, L_0x2c05af0; 1 drivers
+v0x245f6c0_0 .net "nXor", 0 0, L_0x2c05560; 1 drivers
+L_0x2c05c70 .part v0x2960210_0, 2, 1;
+L_0x2c06240 .part v0x2960210_0, 0, 1;
+S_0x245cb90 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x244f220;
+ .timescale -9 -12;
+L_0x2c057d0/d .functor NOT 1, L_0x2c05c70, C4<0>, C4<0>, C4<0>;
+L_0x2c057d0 .delay (10000,10000,10000) L_0x2c057d0/d;
+L_0x2c05890/d .functor AND 1, L_0x2c05670, L_0x2c057d0, C4<1>, C4<1>;
+L_0x2c05890 .delay (20000,20000,20000) L_0x2c05890/d;
+L_0x2c059a0/d .functor AND 1, L_0x2c03f10, L_0x2c05c70, C4<1>, C4<1>;
+L_0x2c059a0 .delay (20000,20000,20000) L_0x2c059a0/d;
+L_0x2c05af0/d .functor OR 1, L_0x2c05890, L_0x2c059a0, C4<0>, C4<0>;
+L_0x2c05af0 .delay (20000,20000,20000) L_0x2c05af0/d;
+v0x2453f50_0 .net "S", 0 0, L_0x2c05c70; 1 drivers
+v0x245c8e0_0 .alias "in0", 0 0, v0x2461480_0;
+v0x245c960_0 .alias "in1", 0 0, v0x2461730_0;
+v0x245aac0_0 .net "nS", 0 0, L_0x2c057d0; 1 drivers
+v0x245ab40_0 .net "out0", 0 0, L_0x2c05890; 1 drivers
+v0x245a810_0 .net "out1", 0 0, L_0x2c059a0; 1 drivers
+v0x245a8b0_0 .alias "outfinal", 0 0, v0x245f640_0;
+S_0x2457ee0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x244f220;
+ .timescale -9 -12;
+L_0x2c05d10/d .functor NOT 1, L_0x2c06240, C4<0>, C4<0>, C4<0>;
+L_0x2c05d10 .delay (10000,10000,10000) L_0x2c05d10/d;
+L_0x2c05dd0/d .functor AND 1, L_0x2c05af0, L_0x2c05d10, C4<1>, C4<1>;
+L_0x2c05dd0 .delay (20000,20000,20000) L_0x2c05dd0/d;
+L_0x2c05f20/d .functor AND 1, L_0x2c052d0, L_0x2c06240, C4<1>, C4<1>;
+L_0x2c05f20 .delay (20000,20000,20000) L_0x2c05f20/d;
+L_0x2c06070/d .functor OR 1, L_0x2c05dd0, L_0x2c05f20, C4<0>, C4<0>;
+L_0x2c06070 .delay (20000,20000,20000) L_0x2c06070/d;
+v0x2457c30_0 .net "S", 0 0, L_0x2c06240; 1 drivers
+v0x2457cb0_0 .alias "in0", 0 0, v0x245f640_0;
+v0x2455e10_0 .alias "in1", 0 0, v0x24617b0_0;
+v0x2455e90_0 .net "nS", 0 0, L_0x2c05d10; 1 drivers
+v0x2455b60_0 .net "out0", 0 0, L_0x2c05dd0; 1 drivers
+v0x2455be0_0 .net "out1", 0 0, L_0x2c05f20; 1 drivers
+v0x2453ed0_0 .alias "outfinal", 0 0, v0x245f920_0;
+S_0x2440cc0 .scope generate, "orbits[22]" "orbits[22]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24eaf88 .param/l "i" 3 258, +C4<010110>;
+S_0x2449900 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2440cc0;
+ .timescale -9 -12;
+L_0x2c050f0/d .functor NOR 1, L_0x2c06420, L_0x2c064c0, C4<0>, C4<0>;
+L_0x2c050f0 .delay (10000,10000,10000) L_0x2c050f0/d;
+L_0x2c051e0/d .functor NOT 1, L_0x2c050f0, C4<0>, C4<0>, C4<0>;
+L_0x2c051e0 .delay (10000,10000,10000) L_0x2c051e0/d;
+L_0x2c066f0/d .functor NAND 1, L_0x2c06420, L_0x2c064c0, C4<1>, C4<1>;
+L_0x2c066f0 .delay (10000,10000,10000) L_0x2c066f0/d;
+L_0x2c06870/d .functor NAND 1, L_0x2c066f0, L_0x2c051e0, C4<1>, C4<1>;
+L_0x2c06870 .delay (10000,10000,10000) L_0x2c06870/d;
+L_0x2c06980/d .functor NOT 1, L_0x2c06870, C4<0>, C4<0>, C4<0>;
+L_0x2c06980 .delay (10000,10000,10000) L_0x2c06980/d;
+v0x244c1e0_0 .net "A", 0 0, L_0x2c06420; 1 drivers
+v0x244c280_0 .net "AnandB", 0 0, L_0x2c066f0; 1 drivers
+v0x244a5a0_0 .net "AnorB", 0 0, L_0x2c050f0; 1 drivers
+v0x244a620_0 .net "AorB", 0 0, L_0x2c051e0; 1 drivers
+v0x2453230_0 .net "AxorB", 0 0, L_0x2c06980; 1 drivers
+v0x24532b0_0 .net "B", 0 0, L_0x2c064c0; 1 drivers
+v0x2452f80_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2453000_0 .net "OrNorXorOut", 0 0, L_0x2c07280; 1 drivers
+v0x2451160_0 .net "XorNor", 0 0, L_0x2c06e00; 1 drivers
+v0x24511e0_0 .net "nXor", 0 0, L_0x2c06870; 1 drivers
+L_0x2c06f80 .part v0x2960210_0, 2, 1;
+L_0x2c07410 .part v0x2960210_0, 0, 1;
+S_0x244e580 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2449900;
+ .timescale -9 -12;
+L_0x2c06ae0/d .functor NOT 1, L_0x2c06f80, C4<0>, C4<0>, C4<0>;
+L_0x2c06ae0 .delay (10000,10000,10000) L_0x2c06ae0/d;
+L_0x2c06ba0/d .functor AND 1, L_0x2c06980, L_0x2c06ae0, C4<1>, C4<1>;
+L_0x2c06ba0 .delay (20000,20000,20000) L_0x2c06ba0/d;
+L_0x2c06cb0/d .functor AND 1, L_0x2c050f0, L_0x2c06f80, C4<1>, C4<1>;
+L_0x2c06cb0 .delay (20000,20000,20000) L_0x2c06cb0/d;
+L_0x2c06e00/d .functor OR 1, L_0x2c06ba0, L_0x2c06cb0, C4<0>, C4<0>;
+L_0x2c06e00 .delay (20000,20000,20000) L_0x2c06e00/d;
+v0x24459b0_0 .net "S", 0 0, L_0x2c06f80; 1 drivers
+v0x244e2d0_0 .alias "in0", 0 0, v0x2453230_0;
+v0x244e350_0 .alias "in1", 0 0, v0x244a5a0_0;
+v0x244c6f0_0 .net "nS", 0 0, L_0x2c06ae0; 1 drivers
+v0x244c770_0 .net "out0", 0 0, L_0x2c06ba0; 1 drivers
+v0x244c490_0 .net "out1", 0 0, L_0x2c06cb0; 1 drivers
+v0x244c530_0 .alias "outfinal", 0 0, v0x2451160_0;
+S_0x2449650 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2449900;
+ .timescale -9 -12;
+L_0x2bf1f20/d .functor NOT 1, L_0x2c07410, C4<0>, C4<0>, C4<0>;
+L_0x2bf1f20 .delay (10000,10000,10000) L_0x2bf1f20/d;
+L_0x2c07020/d .functor AND 1, L_0x2c06e00, L_0x2bf1f20, C4<1>, C4<1>;
+L_0x2c07020 .delay (20000,20000,20000) L_0x2c07020/d;
+L_0x2c07150/d .functor AND 1, L_0x2c051e0, L_0x2c07410, C4<1>, C4<1>;
+L_0x2c07150 .delay (20000,20000,20000) L_0x2c07150/d;
+L_0x2c07280/d .functor OR 1, L_0x2c07020, L_0x2c07150, C4<0>, C4<0>;
+L_0x2c07280 .delay (20000,20000,20000) L_0x2c07280/d;
+v0x2447a80_0 .net "S", 0 0, L_0x2c07410; 1 drivers
+v0x2447b00_0 .alias "in0", 0 0, v0x2451160_0;
+v0x2447820_0 .alias "in1", 0 0, v0x244a620_0;
+v0x24478a0_0 .net "nS", 0 0, L_0x2bf1f20; 1 drivers
+v0x2447570_0 .net "out0", 0 0, L_0x2c07020; 1 drivers
+v0x24475f0_0 .net "out1", 0 0, L_0x2c07150; 1 drivers
+v0x2445930_0 .alias "outfinal", 0 0, v0x2453000_0;
+S_0x24344a0 .scope generate, "orbits[23]" "orbits[23]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24d6eb8 .param/l "i" 3 258, +C4<010111>;
+S_0x2432810 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24344a0;
+ .timescale -9 -12;
+L_0x2c06560/d .functor NOR 1, L_0x2c08690, L_0x2c07550, C4<0>, C4<0>;
+L_0x2c06560 .delay (10000,10000,10000) L_0x2c06560/d;
+L_0x2c077c0/d .functor NOT 1, L_0x2c06560, C4<0>, C4<0>, C4<0>;
+L_0x2c077c0 .delay (10000,10000,10000) L_0x2c077c0/d;
+L_0x2c078b0/d .functor NAND 1, L_0x2c08690, L_0x2c07550, C4<1>, C4<1>;
+L_0x2c078b0 .delay (10000,10000,10000) L_0x2c078b0/d;
+L_0x2c079f0/d .functor NAND 1, L_0x2c078b0, L_0x2c077c0, C4<1>, C4<1>;
+L_0x2c079f0 .delay (10000,10000,10000) L_0x2c079f0/d;
+L_0x2c07ae0/d .functor NOT 1, L_0x2c079f0, C4<0>, C4<0>, C4<0>;
+L_0x2c07ae0 .delay (10000,10000,10000) L_0x2c07ae0/d;
+v0x243c1f0_0 .net "A", 0 0, L_0x2c08690; 1 drivers
+v0x2444c90_0 .net "AnandB", 0 0, L_0x2c078b0; 1 drivers
+v0x2444d30_0 .net "AnorB", 0 0, L_0x2c06560; 1 drivers
+v0x24449e0_0 .net "AorB", 0 0, L_0x2c077c0; 1 drivers
+v0x2444a60_0 .net "AxorB", 0 0, L_0x2c07ae0; 1 drivers
+v0x2442e10_0 .net "B", 0 0, L_0x2c07550; 1 drivers
+v0x2442e90_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2472170_0 .net "OrNorXorOut", 0 0, L_0x2c083c0; 1 drivers
+v0x2442900_0 .net "XorNor", 0 0, L_0x2c07ee0; 1 drivers
+v0x2442980_0 .net "nXor", 0 0, L_0x2c079f0; 1 drivers
+L_0x2c08020 .part v0x2960210_0, 2, 1;
+L_0x2c08550 .part v0x2960210_0, 0, 1;
+S_0x24374c0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2432810;
+ .timescale -9 -12;
+L_0x2c07c20/d .functor NOT 1, L_0x2c08020, C4<0>, C4<0>, C4<0>;
+L_0x2c07c20 .delay (10000,10000,10000) L_0x2c07c20/d;
+L_0x2c07cc0/d .functor AND 1, L_0x2c07ae0, L_0x2c07c20, C4<1>, C4<1>;
+L_0x2c07cc0 .delay (20000,20000,20000) L_0x2c07cc0/d;
+L_0x2c07db0/d .functor AND 1, L_0x2c06560, L_0x2c08020, C4<1>, C4<1>;
+L_0x2c07db0 .delay (20000,20000,20000) L_0x2c07db0/d;
+L_0x2c07ee0/d .functor OR 1, L_0x2c07cc0, L_0x2c07db0, C4<0>, C4<0>;
+L_0x2c07ee0 .delay (20000,20000,20000) L_0x2c07ee0/d;
+v0x2440020_0 .net "S", 0 0, L_0x2c08020; 1 drivers
+v0x24400a0_0 .alias "in0", 0 0, v0x2444a60_0;
+v0x243fd70_0 .alias "in1", 0 0, v0x2444d30_0;
+v0x243fe10_0 .net "nS", 0 0, L_0x2c07c20; 1 drivers
+v0x243e190_0 .net "out0", 0 0, L_0x2c07cc0; 1 drivers
+v0x243e230_0 .net "out1", 0 0, L_0x2c07db0; 1 drivers
+v0x243c170_0 .alias "outfinal", 0 0, v0x2442900_0;
+S_0x243b4d0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2432810;
+ .timescale -9 -12;
+L_0x2c080c0/d .functor NOT 1, L_0x2c08550, C4<0>, C4<0>, C4<0>;
+L_0x2c080c0 .delay (10000,10000,10000) L_0x2c080c0/d;
+L_0x2c08160/d .functor AND 1, L_0x2c07ee0, L_0x2c080c0, C4<1>, C4<1>;
+L_0x2c08160 .delay (20000,20000,20000) L_0x2c08160/d;
+L_0x2c08290/d .functor AND 1, L_0x2c077c0, L_0x2c08550, C4<1>, C4<1>;
+L_0x2c08290 .delay (20000,20000,20000) L_0x2c08290/d;
+L_0x2c083c0/d .functor OR 1, L_0x2c08160, L_0x2c08290, C4<0>, C4<0>;
+L_0x2c083c0 .delay (20000,20000,20000) L_0x2c083c0/d;
+v0x24347d0_0 .net "S", 0 0, L_0x2c08550; 1 drivers
+v0x243b220_0 .alias "in0", 0 0, v0x2442900_0;
+v0x243b2a0_0 .alias "in1", 0 0, v0x24449e0_0;
+v0x2439400_0 .net "nS", 0 0, L_0x2c080c0; 1 drivers
+v0x2439480_0 .net "out0", 0 0, L_0x2c08160; 1 drivers
+v0x2439150_0 .net "out1", 0 0, L_0x2c08290; 1 drivers
+v0x24391d0_0 .alias "outfinal", 0 0, v0x2472170_0;
+S_0x2425ec0 .scope generate, "orbits[24]" "orbits[24]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24bde98 .param/l "i" 3 258, +C4<011000>;
+S_0x2424280 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2425ec0;
+ .timescale -9 -12;
+L_0x2c075f0/d .functor NOR 1, L_0x2c08730, L_0x2c087d0, C4<0>, C4<0>;
+L_0x2c075f0 .delay (10000,10000,10000) L_0x2c075f0/d;
+L_0x2c076e0/d .functor NOT 1, L_0x2c075f0, C4<0>, C4<0>, C4<0>;
+L_0x2c076e0 .delay (10000,10000,10000) L_0x2c076e0/d;
+L_0x2c089f0/d .functor NAND 1, L_0x2c08730, L_0x2c087d0, C4<1>, C4<1>;
+L_0x2c089f0 .delay (10000,10000,10000) L_0x2c089f0/d;
+L_0x2c08b30/d .functor NAND 1, L_0x2c089f0, L_0x2c076e0, C4<1>, C4<1>;
+L_0x2c08b30 .delay (10000,10000,10000) L_0x2c08b30/d;
+L_0x2c08c20/d .functor NOT 1, L_0x2c08b30, C4<0>, C4<0>, C4<0>;
+L_0x2c08c20 .delay (10000,10000,10000) L_0x2c08c20/d;
+v0x242fb20_0 .net "A", 0 0, L_0x2c08730; 1 drivers
+v0x242f7f0_0 .net "AnandB", 0 0, L_0x2c089f0; 1 drivers
+v0x242f890_0 .net "AnorB", 0 0, L_0x2c075f0; 1 drivers
+v0x242db60_0 .net "AorB", 0 0, L_0x2c076e0; 1 drivers
+v0x242dbe0_0 .net "AxorB", 0 0, L_0x2c08c20; 1 drivers
+v0x2436820_0 .net "B", 0 0, L_0x2c087d0; 1 drivers
+v0x24368a0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2436570_0 .net "OrNorXorOut", 0 0, L_0x2c09500; 1 drivers
+v0x24365f0_0 .net "XorNor", 0 0, L_0x2c09020; 1 drivers
+v0x2434750_0 .net "nXor", 0 0, L_0x2c08b30; 1 drivers
+L_0x2c09160 .part v0x2960210_0, 2, 1;
+L_0x2c09690 .part v0x2960210_0, 0, 1;
+S_0x242ab30 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2424280;
+ .timescale -9 -12;
+L_0x2c08d60/d .functor NOT 1, L_0x2c09160, C4<0>, C4<0>, C4<0>;
+L_0x2c08d60 .delay (10000,10000,10000) L_0x2c08d60/d;
+L_0x2c08e00/d .functor AND 1, L_0x2c08c20, L_0x2c08d60, C4<1>, C4<1>;
+L_0x2c08e00 .delay (20000,20000,20000) L_0x2c08e00/d;
+L_0x2c08ef0/d .functor AND 1, L_0x2c075f0, L_0x2c09160, C4<1>, C4<1>;
+L_0x2c08ef0 .delay (20000,20000,20000) L_0x2c08ef0/d;
+L_0x2c09020/d .functor OR 1, L_0x2c08e00, L_0x2c08ef0, C4<0>, C4<0>;
+L_0x2c09020 .delay (20000,20000,20000) L_0x2c09020/d;
+v0x2428ef0_0 .net "S", 0 0, L_0x2c09160; 1 drivers
+v0x2428f70_0 .alias "in0", 0 0, v0x242dbe0_0;
+v0x2431b70_0 .alias "in1", 0 0, v0x242f890_0;
+v0x2431c10_0 .net "nS", 0 0, L_0x2c08d60; 1 drivers
+v0x24318c0_0 .net "out0", 0 0, L_0x2c08e00; 1 drivers
+v0x2431960_0 .net "out1", 0 0, L_0x2c08ef0; 1 drivers
+v0x242faa0_0 .alias "outfinal", 0 0, v0x24365f0_0;
+S_0x242cec0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2424280;
+ .timescale -9 -12;
+L_0x2c09200/d .functor NOT 1, L_0x2c09690, C4<0>, C4<0>, C4<0>;
+L_0x2c09200 .delay (10000,10000,10000) L_0x2c09200/d;
+L_0x2c092a0/d .functor AND 1, L_0x2c09020, L_0x2c09200, C4<1>, C4<1>;
+L_0x2c092a0 .delay (20000,20000,20000) L_0x2c092a0/d;
+L_0x2c093d0/d .functor AND 1, L_0x2c076e0, L_0x2c09690, C4<1>, C4<1>;
+L_0x2c093d0 .delay (20000,20000,20000) L_0x2c093d0/d;
+L_0x2c09500/d .functor OR 1, L_0x2c092a0, L_0x2c093d0, C4<0>, C4<0>;
+L_0x2c09500 .delay (20000,20000,20000) L_0x2c09500/d;
+v0x24261f0_0 .net "S", 0 0, L_0x2c09690; 1 drivers
+v0x242cc10_0 .alias "in0", 0 0, v0x24365f0_0;
+v0x242cc90_0 .alias "in1", 0 0, v0x242db60_0;
+v0x242b040_0 .net "nS", 0 0, L_0x2c09200; 1 drivers
+v0x242b0c0_0 .net "out0", 0 0, L_0x2c092a0; 1 drivers
+v0x242ade0_0 .net "out1", 0 0, L_0x2c093d0; 1 drivers
+v0x242ae60_0 .alias "outfinal", 0 0, v0x2436570_0;
+S_0x243d930 .scope generate, "orbits[25]" "orbits[25]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24daa18 .param/l "i" 3 258, +C4<011001>;
+S_0x2438c80 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x243d930;
+ .timescale -9 -12;
+L_0x2c08870/d .functor NOR 1, L_0x2c0a8f0, L_0x2c097d0, C4<0>, C4<0>;
+L_0x2c08870 .delay (10000,10000,10000) L_0x2c08870/d;
+L_0x2c09a20/d .functor NOT 1, L_0x2c08870, C4<0>, C4<0>, C4<0>;
+L_0x2c09a20 .delay (10000,10000,10000) L_0x2c09a20/d;
+L_0x2c09b10/d .functor NAND 1, L_0x2c0a8f0, L_0x2c097d0, C4<1>, C4<1>;
+L_0x2c09b10 .delay (10000,10000,10000) L_0x2c09b10/d;
+L_0x2c09c50/d .functor NAND 1, L_0x2c09b10, L_0x2c09a20, C4<1>, C4<1>;
+L_0x2c09c50 .delay (10000,10000,10000) L_0x2c09c50/d;
+L_0x2c09d40/d .functor NOT 1, L_0x2c09c50, C4<0>, C4<0>, C4<0>;
+L_0x2c09d40 .delay (10000,10000,10000) L_0x2c09d40/d;
+v0x24212d0_0 .net "A", 0 0, L_0x2c0a8f0; 1 drivers
+v0x241f610_0 .net "AnandB", 0 0, L_0x2c09b10; 1 drivers
+v0x241f6b0_0 .net "AnorB", 0 0, L_0x2c08870; 1 drivers
+v0x2428250_0 .net "AorB", 0 0, L_0x2c09a20; 1 drivers
+v0x24282d0_0 .net "AxorB", 0 0, L_0x2c09d40; 1 drivers
+v0x2427fa0_0 .net "B", 0 0, L_0x2c097d0; 1 drivers
+v0x2428020_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24263d0_0 .net "OrNorXorOut", 0 0, L_0x2c0a620; 1 drivers
+v0x2426450_0 .net "XorNor", 0 0, L_0x2c0a140; 1 drivers
+v0x2426170_0 .net "nXor", 0 0, L_0x2c09c50; 1 drivers
+L_0x2c0a280 .part v0x2960210_0, 2, 1;
+L_0x2c0a7b0 .part v0x2960210_0, 0, 1;
+S_0x24235e0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2438c80;
+ .timescale -9 -12;
+L_0x2c09e80/d .functor NOT 1, L_0x2c0a280, C4<0>, C4<0>, C4<0>;
+L_0x2c09e80 .delay (10000,10000,10000) L_0x2c09e80/d;
+L_0x2c09f20/d .functor AND 1, L_0x2c09d40, L_0x2c09e80, C4<1>, C4<1>;
+L_0x2c09f20 .delay (20000,20000,20000) L_0x2c09f20/d;
+L_0x2c0a010/d .functor AND 1, L_0x2c08870, L_0x2c0a280, C4<1>, C4<1>;
+L_0x2c0a010 .delay (20000,20000,20000) L_0x2c0a010/d;
+L_0x2c0a140/d .functor OR 1, L_0x2c09f20, L_0x2c0a010, C4<0>, C4<0>;
+L_0x2c0a140 .delay (20000,20000,20000) L_0x2c0a140/d;
+v0x2423330_0 .net "S", 0 0, L_0x2c0a280; 1 drivers
+v0x24233b0_0 .alias "in0", 0 0, v0x24282d0_0;
+v0x2421760_0 .alias "in1", 0 0, v0x241f6b0_0;
+v0x2421800_0 .net "nS", 0 0, L_0x2c09e80; 1 drivers
+v0x2421500_0 .net "out0", 0 0, L_0x2c09f20; 1 drivers
+v0x24215a0_0 .net "out1", 0 0, L_0x2c0a010; 1 drivers
+v0x2421250_0 .alias "outfinal", 0 0, v0x2426450_0;
+S_0x24af640 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2438c80;
+ .timescale -9 -12;
+L_0x2c0a320/d .functor NOT 1, L_0x2c0a7b0, C4<0>, C4<0>, C4<0>;
+L_0x2c0a320 .delay (10000,10000,10000) L_0x2c0a320/d;
+L_0x2c0a3c0/d .functor AND 1, L_0x2c0a140, L_0x2c0a320, C4<1>, C4<1>;
+L_0x2c0a3c0 .delay (20000,20000,20000) L_0x2c0a3c0/d;
+L_0x2c0a4f0/d .functor AND 1, L_0x2c09a20, L_0x2c0a7b0, C4<1>, C4<1>;
+L_0x2c0a4f0 .delay (20000,20000,20000) L_0x2c0a4f0/d;
+L_0x2c0a620/d .functor OR 1, L_0x2c0a3c0, L_0x2c0a4f0, C4<0>, C4<0>;
+L_0x2c0a620 .delay (20000,20000,20000) L_0x2c0a620/d;
+v0x2441f60_0 .net "S", 0 0, L_0x2c0a7b0; 1 drivers
+v0x241e970_0 .alias "in0", 0 0, v0x2426450_0;
+v0x241e9f0_0 .alias "in1", 0 0, v0x2428250_0;
+v0x241c530_0 .net "nS", 0 0, L_0x2c0a320; 1 drivers
+v0x241c5b0_0 .net "out0", 0 0, L_0x2c0a3c0; 1 drivers
+v0x241a810_0 .net "out1", 0 0, L_0x2c0a4f0; 1 drivers
+v0x241a890_0 .alias "outfinal", 0 0, v0x24263d0_0;
+S_0x24687e0 .scope generate, "orbits[26]" "orbits[26]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24f46b8 .param/l "i" 3 258, +C4<011010>;
+S_0x2468260 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x24687e0;
+ .timescale -9 -12;
+L_0x2c09870/d .functor NOR 1, L_0x2c0a990, L_0x2c0aa30, C4<0>, C4<0>;
+L_0x2c09870 .delay (10000,10000,10000) L_0x2c09870/d;
+L_0x2c09960/d .functor NOT 1, L_0x2c09870, C4<0>, C4<0>, C4<0>;
+L_0x2c09960 .delay (10000,10000,10000) L_0x2c09960/d;
+L_0x2c0ac40/d .functor NAND 1, L_0x2c0a990, L_0x2c0aa30, C4<1>, C4<1>;
+L_0x2c0ac40 .delay (10000,10000,10000) L_0x2c0ac40/d;
+L_0x2c0ad80/d .functor NAND 1, L_0x2c0ac40, L_0x2c09960, C4<1>, C4<1>;
+L_0x2c0ad80 .delay (10000,10000,10000) L_0x2c0ad80/d;
+L_0x2c0ae70/d .functor NOT 1, L_0x2c0ad80, C4<0>, C4<0>, C4<0>;
+L_0x2c0ae70 .delay (10000,10000,10000) L_0x2c0ae70/d;
+v0x244b840_0 .net "A", 0 0, L_0x2c0a990; 1 drivers
+v0x2420830_0 .net "AnandB", 0 0, L_0x2c0ac40; 1 drivers
+v0x24208d0_0 .net "AnorB", 0 0, L_0x2c09870; 1 drivers
+v0x24470d0_0 .net "AorB", 0 0, L_0x2c09960; 1 drivers
+v0x2447150_0 .net "AxorB", 0 0, L_0x2c0ae70; 1 drivers
+v0x2446b50_0 .net "B", 0 0, L_0x2c0aa30; 1 drivers
+v0x2446bd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x2442460_0 .net "OrNorXorOut", 0 0, L_0x2c0b750; 1 drivers
+v0x24424e0_0 .net "XorNor", 0 0, L_0x2c0b270; 1 drivers
+v0x2441ee0_0 .net "nXor", 0 0, L_0x2c0ad80; 1 drivers
+L_0x2c0b3b0 .part v0x2960210_0, 2, 1;
+L_0x2c0b8e0 .part v0x2960210_0, 0, 1;
+S_0x2420db0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2468260;
+ .timescale -9 -12;
+L_0x2c0afb0/d .functor NOT 1, L_0x2c0b3b0, C4<0>, C4<0>, C4<0>;
+L_0x2c0afb0 .delay (10000,10000,10000) L_0x2c0afb0/d;
+L_0x2c0b050/d .functor AND 1, L_0x2c0ae70, L_0x2c0afb0, C4<1>, C4<1>;
+L_0x2c0b050 .delay (20000,20000,20000) L_0x2c0b050/d;
+L_0x2c0b140/d .functor AND 1, L_0x2c09870, L_0x2c0b3b0, C4<1>, C4<1>;
+L_0x2c0b140 .delay (20000,20000,20000) L_0x2c0b140/d;
+L_0x2c0b270/d .functor OR 1, L_0x2c0b050, L_0x2c0b140, C4<0>, C4<0>;
+L_0x2c0b270 .delay (20000,20000,20000) L_0x2c0b270/d;
+v0x2455690_0 .net "S", 0 0, L_0x2c0b3b0; 1 drivers
+v0x2455710_0 .alias "in0", 0 0, v0x2447150_0;
+v0x24509e0_0 .alias "in1", 0 0, v0x24208d0_0;
+v0x2450a80_0 .net "nS", 0 0, L_0x2c0afb0; 1 drivers
+v0x244bd40_0 .net "out0", 0 0, L_0x2c0b050; 1 drivers
+v0x244bde0_0 .net "out1", 0 0, L_0x2c0b140; 1 drivers
+v0x244b7c0_0 .alias "outfinal", 0 0, v0x24424e0_0;
+S_0x2463b70 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2468260;
+ .timescale -9 -12;
+L_0x2c0b450/d .functor NOT 1, L_0x2c0b8e0, C4<0>, C4<0>, C4<0>;
+L_0x2c0b450 .delay (10000,10000,10000) L_0x2c0b450/d;
+L_0x2c0b4f0/d .functor AND 1, L_0x2c0b270, L_0x2c0b450, C4<1>, C4<1>;
+L_0x2c0b4f0 .delay (20000,20000,20000) L_0x2c0b4f0/d;
+L_0x2c0b620/d .functor AND 1, L_0x2c09960, L_0x2c0b8e0, C4<1>, C4<1>;
+L_0x2c0b620 .delay (20000,20000,20000) L_0x2c0b620/d;
+L_0x2c0b750/d .functor OR 1, L_0x2c0b4f0, L_0x2c0b620, C4<0>, C4<0>;
+L_0x2c0b750 .delay (20000,20000,20000) L_0x2c0b750/d;
+v0x246cf50_0 .net "S", 0 0, L_0x2c0b8e0; 1 drivers
+v0x24635f0_0 .alias "in0", 0 0, v0x24424e0_0;
+v0x2463670_0 .alias "in1", 0 0, v0x24470d0_0;
+v0x245ec80_0 .net "nS", 0 0, L_0x2c0b450; 1 drivers
+v0x245ed00_0 .net "out0", 0 0, L_0x2c0b4f0; 1 drivers
+v0x245a340_0 .net "out1", 0 0, L_0x2c0b620; 1 drivers
+v0x245a3c0_0 .alias "outfinal", 0 0, v0x2442460_0;
+S_0x2498490 .scope generate, "orbits[27]" "orbits[27]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x24fffb8 .param/l "i" 3 258, +C4<011011>;
+S_0x24937e0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2498490;
+ .timescale -9 -12;
+L_0x2c0aad0/d .functor NOR 1, L_0x2c0cc70, L_0x2c0ba20, C4<0>, C4<0>;
+L_0x2c0aad0 .delay (10000,10000,10000) L_0x2c0aad0/d;
+L_0x2c0bca0/d .functor NOT 1, L_0x2c0aad0, C4<0>, C4<0>, C4<0>;
+L_0x2c0bca0 .delay (10000,10000,10000) L_0x2c0bca0/d;
+L_0x2c0bd90/d .functor NAND 1, L_0x2c0cc70, L_0x2c0ba20, C4<1>, C4<1>;
+L_0x2c0bd90 .delay (10000,10000,10000) L_0x2c0bd90/d;
+L_0x2c0bed0/d .functor NAND 1, L_0x2c0bd90, L_0x2c0bca0, C4<1>, C4<1>;
+L_0x2c0bed0 .delay (10000,10000,10000) L_0x2c0bed0/d;
+L_0x2c0bfc0/d .functor NOT 1, L_0x2c0bed0, C4<0>, C4<0>, C4<0>;
+L_0x2c0bfc0 .delay (10000,10000,10000) L_0x2c0bfc0/d;
+v0x247ba50_0 .net "A", 0 0, L_0x2c0cc70; 1 drivers
+v0x247baf0_0 .net "AnandB", 0 0, L_0x2c0bd90; 1 drivers
+v0x24254a0_0 .net "AnorB", 0 0, L_0x2c0aad0; 1 drivers
+v0x2425520_0 .net "AorB", 0 0, L_0x2c0bca0; 1 drivers
+v0x2476da0_0 .net "AxorB", 0 0, L_0x2c0bfc0; 1 drivers
+v0x2476e20_0 .net "B", 0 0, L_0x2c0ba20; 1 drivers
+v0x24720f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x246d450_0 .net "OrNorXorOut", 0 0, L_0x2c0c960; 1 drivers
+v0x246d4d0_0 .net "XorNor", 0 0, L_0x2c0c3e0; 1 drivers
+v0x246ced0_0 .net "nXor", 0 0, L_0x2c0bed0; 1 drivers
+L_0x2c0c560 .part v0x2960210_0, 2, 1;
+L_0x2c0cb30 .part v0x2960210_0, 0, 1;
+S_0x2425a20 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x24937e0;
+ .timescale -9 -12;
+L_0x2c0c100/d .functor NOT 1, L_0x2c0c560, C4<0>, C4<0>, C4<0>;
+L_0x2c0c100 .delay (10000,10000,10000) L_0x2c0c100/d;
+L_0x2c0c1a0/d .functor AND 1, L_0x2c0bfc0, L_0x2c0c100, C4<1>, C4<1>;
+L_0x2c0c1a0 .delay (20000,20000,20000) L_0x2c0c1a0/d;
+L_0x2c0c290/d .functor AND 1, L_0x2c0aad0, L_0x2c0c560, C4<1>, C4<1>;
+L_0x2c0c290 .delay (20000,20000,20000) L_0x2c0c290/d;
+L_0x2c0c3e0/d .functor OR 1, L_0x2c0c1a0, L_0x2c0c290, C4<0>, C4<0>;
+L_0x2c0c3e0 .delay (20000,20000,20000) L_0x2c0c3e0/d;
+v0x24899f0_0 .net "S", 0 0, L_0x2c0c560; 1 drivers
+v0x2485280_0 .alias "in0", 0 0, v0x2476da0_0;
+v0x2485300_0 .alias "in1", 0 0, v0x24254a0_0;
+v0x2484d00_0 .net "nS", 0 0, L_0x2c0c100; 1 drivers
+v0x2484d80_0 .net "out0", 0 0, L_0x2c0c1a0; 1 drivers
+v0x2480390_0 .net "out1", 0 0, L_0x2c0c290; 1 drivers
+v0x2480430_0 .alias "outfinal", 0 0, v0x246d4d0_0;
+S_0x241c060 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x24937e0;
+ .timescale -9 -12;
+L_0x2c0c600/d .functor NOT 1, L_0x2c0cb30, C4<0>, C4<0>, C4<0>;
+L_0x2c0c600 .delay (10000,10000,10000) L_0x2c0c600/d;
+L_0x2c0c6c0/d .functor AND 1, L_0x2c0c3e0, L_0x2c0c600, C4<1>, C4<1>;
+L_0x2c0c6c0 .delay (20000,20000,20000) L_0x2c0c6c0/d;
+L_0x2c0c810/d .functor AND 1, L_0x2c0bca0, L_0x2c0cb30, C4<1>, C4<1>;
+L_0x2c0c810 .delay (20000,20000,20000) L_0x2c0c810/d;
+L_0x2c0c960/d .functor OR 1, L_0x2c0c6c0, L_0x2c0c810, C4<0>, C4<0>;
+L_0x2c0c960 .delay (20000,20000,20000) L_0x2c0c960/d;
+v0x248eb60_0 .net "S", 0 0, L_0x2c0cb30; 1 drivers
+v0x248ebe0_0 .alias "in0", 0 0, v0x246d4d0_0;
+v0x248e5e0_0 .alias "in1", 0 0, v0x2425520_0;
+v0x248e660_0 .net "nS", 0 0, L_0x2c0c600; 1 drivers
+v0x2489ef0_0 .net "out0", 0 0, L_0x2c0c6c0; 1 drivers
+v0x2489f70_0 .net "out1", 0 0, L_0x2c0c810; 1 drivers
+v0x2489970_0 .alias "outfinal", 0 0, v0x246d450_0;
+S_0x2433fd0 .scope generate, "orbits[28]" "orbits[28]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x251ef48 .param/l "i" 3 258, +C4<011100>;
+S_0x242f320 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2433fd0;
+ .timescale -9 -12;
+L_0x2c0bac0/d .functor NOR 1, L_0x2c0cd10, L_0x2c0cdb0, C4<0>, C4<0>;
+L_0x2c0bac0 .delay (10000,10000,10000) L_0x2c0bac0/d;
+L_0x2c0bbb0/d .functor NOT 1, L_0x2c0bac0, C4<0>, C4<0>, C4<0>;
+L_0x2c0bbb0 .delay (10000,10000,10000) L_0x2c0bbb0/d;
+L_0x2c0cff0/d .functor NAND 1, L_0x2c0cd10, L_0x2c0cdb0, C4<1>, C4<1>;
+L_0x2c0cff0 .delay (10000,10000,10000) L_0x2c0cff0/d;
+L_0x2c0d170/d .functor NAND 1, L_0x2c0cff0, L_0x2c0bbb0, C4<1>, C4<1>;
+L_0x2c0d170 .delay (10000,10000,10000) L_0x2c0d170/d;
+L_0x2c0d280/d .functor NOT 1, L_0x2c0d170, C4<0>, C4<0>, C4<0>;
+L_0x2c0d280 .delay (10000,10000,10000) L_0x2c0d280/d;
+v0x24a6920_0 .net "A", 0 0, L_0x2c0cd10; 1 drivers
+v0x24a69c0_0 .net "AnandB", 0 0, L_0x2c0cff0; 1 drivers
+v0x24a63a0_0 .net "AnorB", 0 0, L_0x2c0bac0; 1 drivers
+v0x24a6420_0 .net "AorB", 0 0, L_0x2c0bbb0; 1 drivers
+v0x24a1cb0_0 .net "AxorB", 0 0, L_0x2c0d280; 1 drivers
+v0x24a1d30_0 .net "B", 0 0, L_0x2c0cdb0; 1 drivers
+v0x24a1730_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x24a17b0_0 .net "OrNorXorOut", 0 0, L_0x2c0dc80; 1 drivers
+v0x249d140_0 .net "XorNor", 0 0, L_0x2c0d700; 1 drivers
+v0x249d1c0_0 .net "nXor", 0 0, L_0x2c0d170; 1 drivers
+L_0x2c0d880 .part v0x2960210_0, 2, 1;
+L_0x2c0de50 .part v0x2960210_0, 0, 1;
+S_0x24b0de0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x242f320;
+ .timescale -9 -12;
+L_0x2c0d3e0/d .functor NOT 1, L_0x2c0d880, C4<0>, C4<0>, C4<0>;
+L_0x2c0d3e0 .delay (10000,10000,10000) L_0x2c0d3e0/d;
+L_0x2c0d4a0/d .functor AND 1, L_0x2c0d280, L_0x2c0d3e0, C4<1>, C4<1>;
+L_0x2c0d4a0 .delay (20000,20000,20000) L_0x2c0d4a0/d;
+L_0x2c0d5b0/d .functor AND 1, L_0x2c0bac0, L_0x2c0d880, C4<1>, C4<1>;
+L_0x2c0d5b0 .delay (20000,20000,20000) L_0x2c0d5b0/d;
+L_0x2c0d700/d .functor OR 1, L_0x2c0d4a0, L_0x2c0d5b0, C4<0>, C4<0>;
+L_0x2c0d700 .delay (20000,20000,20000) L_0x2c0d700/d;
+v0x24b1320_0 .net "S", 0 0, L_0x2c0d880; 1 drivers
+v0x24ab590_0 .alias "in0", 0 0, v0x24a1cb0_0;
+v0x24ab610_0 .alias "in1", 0 0, v0x24a63a0_0;
+v0x24ab010_0 .net "nS", 0 0, L_0x2c0d3e0; 1 drivers
+v0x24ab090_0 .net "out0", 0 0, L_0x2c0d4a0; 1 drivers
+v0x242a110_0 .net "out1", 0 0, L_0x2c0d5b0; 1 drivers
+v0x242a1b0_0 .alias "outfinal", 0 0, v0x249d140_0;
+S_0x24b5160 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x242f320;
+ .timescale -9 -12;
+L_0x2c0d920/d .functor NOT 1, L_0x2c0de50, C4<0>, C4<0>, C4<0>;
+L_0x2c0d920 .delay (10000,10000,10000) L_0x2c0d920/d;
+L_0x2c0d9e0/d .functor AND 1, L_0x2c0d700, L_0x2c0d920, C4<1>, C4<1>;
+L_0x2c0d9e0 .delay (20000,20000,20000) L_0x2c0d9e0/d;
+L_0x2c0db30/d .functor AND 1, L_0x2c0bbb0, L_0x2c0de50, C4<1>, C4<1>;
+L_0x2c0db30 .delay (20000,20000,20000) L_0x2c0db30/d;
+L_0x2c0dc80/d .functor OR 1, L_0x2c0d9e0, L_0x2c0db30, C4<0>, C4<0>;
+L_0x2c0dc80 .delay (20000,20000,20000) L_0x2c0dc80/d;
+v0x242a690_0 .net "S", 0 0, L_0x2c0de50; 1 drivers
+v0x242a710_0 .alias "in0", 0 0, v0x249d140_0;
+v0x24b17b0_0 .alias "in1", 0 0, v0x24a6420_0;
+v0x24b1830_0 .net "nS", 0 0, L_0x2c0d920; 1 drivers
+v0x24b1540_0 .net "out0", 0 0, L_0x2c0d9e0; 1 drivers
+v0x24b15c0_0 .net "out1", 0 0, L_0x2c0db30; 1 drivers
+v0x24b12a0_0 .alias "outfinal", 0 0, v0x24a17b0_0;
+S_0x2359c10 .scope generate, "orbits[29]" "orbits[29]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2518288 .param/l "i" 3 258, +C4<011101>;
+S_0x235d130 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2359c10;
+ .timescale -9 -12;
+L_0x2c0ce50/d .functor NOR 1, L_0x2c0f290, L_0x2c0df90, C4<0>, C4<0>;
+L_0x2c0ce50 .delay (10000,10000,10000) L_0x2c0ce50/d;
+L_0x2c0cf40/d .functor NOT 1, L_0x2c0ce50, C4<0>, C4<0>, C4<0>;
+L_0x2c0cf40 .delay (10000,10000,10000) L_0x2c0cf40/d;
+L_0x2c0e310/d .functor NAND 1, L_0x2c0f290, L_0x2c0df90, C4<1>, C4<1>;
+L_0x2c0e310 .delay (10000,10000,10000) L_0x2c0e310/d;
+L_0x2c0e470/d .functor NAND 1, L_0x2c0e310, L_0x2c0cf40, C4<1>, C4<1>;
+L_0x2c0e470 .delay (10000,10000,10000) L_0x2c0e470/d;
+L_0x2c0e580/d .functor NOT 1, L_0x2c0e470, C4<0>, C4<0>, C4<0>;
+L_0x2c0e580 .delay (10000,10000,10000) L_0x2c0e580/d;
+v0x2363d20_0 .net "A", 0 0, L_0x2c0f290; 1 drivers
+v0x2363da0_0 .net "AnandB", 0 0, L_0x2c0e310; 1 drivers
+v0x2362e90_0 .net "AnorB", 0 0, L_0x2c0ce50; 1 drivers
+v0x2362f10_0 .net "AorB", 0 0, L_0x2c0cf40; 1 drivers
+v0x258c700_0 .net "AxorB", 0 0, L_0x2c0e580; 1 drivers
+v0x258c780_0 .net "B", 0 0, L_0x2c0df90; 1 drivers
+v0x258b4f0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x258b570_0 .net "OrNorXorOut", 0 0, L_0x2c0ef80; 1 drivers
+v0x2589430_0 .net "XorNor", 0 0, L_0x2c0ea00; 1 drivers
+v0x25894b0_0 .net "nXor", 0 0, L_0x2c0e470; 1 drivers
+L_0x2c0eb80 .part v0x2960210_0, 2, 1;
+L_0x2c0f150 .part v0x2960210_0, 0, 1;
+S_0x2361ad0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x235d130;
+ .timescale -9 -12;
+L_0x2c0e6e0/d .functor NOT 1, L_0x2c0eb80, C4<0>, C4<0>, C4<0>;
+L_0x2c0e6e0 .delay (10000,10000,10000) L_0x2c0e6e0/d;
+L_0x2c0e7a0/d .functor AND 1, L_0x2c0e580, L_0x2c0e6e0, C4<1>, C4<1>;
+L_0x2c0e7a0 .delay (20000,20000,20000) L_0x2c0e7a0/d;
+L_0x2c0e8b0/d .functor AND 1, L_0x2c0ce50, L_0x2c0eb80, C4<1>, C4<1>;
+L_0x2c0e8b0 .delay (20000,20000,20000) L_0x2c0e8b0/d;
+L_0x2c0ea00/d .functor OR 1, L_0x2c0e7a0, L_0x2c0e8b0, C4<0>, C4<0>;
+L_0x2c0ea00 .delay (20000,20000,20000) L_0x2c0ea00/d;
+v0x235e5b0_0 .net "S", 0 0, L_0x2c0eb80; 1 drivers
+v0x2361870_0 .alias "in0", 0 0, v0x258c700_0;
+v0x23618f0_0 .alias "in1", 0 0, v0x2362e90_0;
+v0x23609e0_0 .net "nS", 0 0, L_0x2c0e6e0; 1 drivers
+v0x2360a60_0 .net "out0", 0 0, L_0x2c0e7a0; 1 drivers
+v0x2363f80_0 .net "out1", 0 0, L_0x2c0e8b0; 1 drivers
+v0x2364000_0 .alias "outfinal", 0 0, v0x2589430_0;
+S_0x235ced0 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x235d130;
+ .timescale -9 -12;
+L_0x2c0ec20/d .functor NOT 1, L_0x2c0f150, C4<0>, C4<0>, C4<0>;
+L_0x2c0ec20 .delay (10000,10000,10000) L_0x2c0ec20/d;
+L_0x2c0ece0/d .functor AND 1, L_0x2c0ea00, L_0x2c0ec20, C4<1>, C4<1>;
+L_0x2c0ece0 .delay (20000,20000,20000) L_0x2c0ece0/d;
+L_0x2c0ee30/d .functor AND 1, L_0x2c0cf40, L_0x2c0f150, C4<1>, C4<1>;
+L_0x2c0ee30 .delay (20000,20000,20000) L_0x2c0ee30/d;
+L_0x2c0ef80/d .functor OR 1, L_0x2c0ece0, L_0x2c0ee30, C4<0>, C4<0>;
+L_0x2c0ef80 .delay (20000,20000,20000) L_0x2c0ef80/d;
+v0x235c070_0 .net "S", 0 0, L_0x2c0f150; 1 drivers
+v0x235c0f0_0 .alias "in0", 0 0, v0x2589430_0;
+v0x235f620_0 .alias "in1", 0 0, v0x2362f10_0;
+v0x235f6a0_0 .net "nS", 0 0, L_0x2c0ec20; 1 drivers
+v0x235f3c0_0 .net "out0", 0 0, L_0x2c0ece0; 1 drivers
+v0x235f440_0 .net "out1", 0 0, L_0x2c0ee30; 1 drivers
+v0x235e530_0 .alias "outfinal", 0 0, v0x258b570_0;
+S_0x234f490 .scope generate, "orbits[30]" "orbits[30]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x2538ca8 .param/l "i" 3 258, +C4<011110>;
+S_0x234e630 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x234f490;
+ .timescale -9 -12;
+L_0x2c0e030/d .functor NOR 1, L_0x2c0f330, L_0x2c0f3d0, C4<0>, C4<0>;
+L_0x2c0e030 .delay (10000,10000,10000) L_0x2c0e030/d;
+L_0x2c0e120/d .functor NOT 1, L_0x2c0e030, C4<0>, C4<0>, C4<0>;
+L_0x2c0e120 .delay (10000,10000,10000) L_0x2c0e120/d;
+L_0x2c0e1e0/d .functor NAND 1, L_0x2c0f330, L_0x2c0f3d0, C4<1>, C4<1>;
+L_0x2c0e1e0 .delay (10000,10000,10000) L_0x2c0e1e0/d;
+L_0x2c0f780/d .functor NAND 1, L_0x2c0e1e0, L_0x2c0e120, C4<1>, C4<1>;
+L_0x2c0f780 .delay (10000,10000,10000) L_0x2c0f780/d;
+L_0x2c0f890/d .functor NOT 1, L_0x2c0f780, C4<0>, C4<0>, C4<0>;
+L_0x2c0f890 .delay (10000,10000,10000) L_0x2c0f890/d;
+v0x2358870_0 .net "A", 0 0, L_0x2c0f330; 1 drivers
+v0x2358910_0 .net "AnandB", 0 0, L_0x2c0e1e0; 1 drivers
+v0x2358610_0 .net "AnorB", 0 0, L_0x2c0e030; 1 drivers
+v0x2358690_0 .net "AorB", 0 0, L_0x2c0e120; 1 drivers
+v0x23577b0_0 .net "AxorB", 0 0, L_0x2c0f890; 1 drivers
+v0x2357830_0 .net "B", 0 0, L_0x2c0f3d0; 1 drivers
+v0x235acd0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x235ad50_0 .net "OrNorXorOut", 0 0, L_0x2c10290; 1 drivers
+v0x235aa70_0 .net "XorNor", 0 0, L_0x2c0fd10; 1 drivers
+v0x235aaf0_0 .net "nXor", 0 0, L_0x2c0f780; 1 drivers
+L_0x2c0fe90 .part v0x2960210_0, 2, 1;
+L_0x2c10460 .part v0x2960210_0, 0, 1;
+S_0x2352ef0 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x234e630;
+ .timescale -9 -12;
+L_0x2c0f9f0/d .functor NOT 1, L_0x2c0fe90, C4<0>, C4<0>, C4<0>;
+L_0x2c0f9f0 .delay (10000,10000,10000) L_0x2c0f9f0/d;
+L_0x2c0fab0/d .functor AND 1, L_0x2c0f890, L_0x2c0f9f0, C4<1>, C4<1>;
+L_0x2c0fab0 .delay (20000,20000,20000) L_0x2c0fab0/d;
+L_0x2c0fbc0/d .functor AND 1, L_0x2c0e030, L_0x2c0fe90, C4<1>, C4<1>;
+L_0x2c0fbc0 .delay (20000,20000,20000) L_0x2c0fbc0/d;
+L_0x2c0fd10/d .functor OR 1, L_0x2c0fab0, L_0x2c0fbc0, C4<0>, C4<0>;
+L_0x2c0fd10 .delay (20000,20000,20000) L_0x2c0fd10/d;
+v0x2353dd0_0 .net "S", 0 0, L_0x2c0fe90; 1 drivers
+v0x2356410_0 .alias "in0", 0 0, v0x23577b0_0;
+v0x2356490_0 .alias "in1", 0 0, v0x2358610_0;
+v0x23561b0_0 .net "nS", 0 0, L_0x2c0f9f0; 1 drivers
+v0x2356230_0 .net "out0", 0 0, L_0x2c0fab0; 1 drivers
+v0x2355350_0 .net "out1", 0 0, L_0x2c0fbc0; 1 drivers
+v0x23553f0_0 .alias "outfinal", 0 0, v0x235aa70_0;
+S_0x2351b50 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x234e630;
+ .timescale -9 -12;
+L_0x2c0ff30/d .functor NOT 1, L_0x2c10460, C4<0>, C4<0>, C4<0>;
+L_0x2c0ff30 .delay (10000,10000,10000) L_0x2c0ff30/d;
+L_0x2c0fff0/d .functor AND 1, L_0x2c0fd10, L_0x2c0ff30, C4<1>, C4<1>;
+L_0x2c0fff0 .delay (20000,20000,20000) L_0x2c0fff0/d;
+L_0x2c10140/d .functor AND 1, L_0x2c0e120, L_0x2c10460, C4<1>, C4<1>;
+L_0x2c10140 .delay (20000,20000,20000) L_0x2c10140/d;
+L_0x2c10290/d .functor OR 1, L_0x2c0fff0, L_0x2c10140, C4<0>, C4<0>;
+L_0x2c10290 .delay (20000,20000,20000) L_0x2c10290/d;
+v0x23518f0_0 .net "S", 0 0, L_0x2c10460; 1 drivers
+v0x2351970_0 .alias "in0", 0 0, v0x235aa70_0;
+v0x2350a90_0 .alias "in1", 0 0, v0x2358690_0;
+v0x2350b10_0 .net "nS", 0 0, L_0x2c0ff30; 1 drivers
+v0x2353fb0_0 .net "out0", 0 0, L_0x2c0fff0; 1 drivers
+v0x2354030_0 .net "out1", 0 0, L_0x2c10140; 1 drivers
+v0x2353d50_0 .alias "outfinal", 0 0, v0x235ad50_0;
+S_0x2344010 .scope generate, "orbits[31]" "orbits[31]" 3 258, 3 258, S_0x2340a70;
+ .timescale -9 -12;
+P_0x238c3b8 .param/l "i" 3 258, +C4<011111>;
+S_0x2343db0 .scope module, "attempt" "OrNorXor" 3 260, 3 165, S_0x2344010;
+ .timescale -9 -12;
+L_0x2c0f470/d .functor NOR 1, L_0x2c118d0, L_0x2c105a0, C4<0>, C4<0>;
+L_0x2c0f470 .delay (10000,10000,10000) L_0x2c0f470/d;
+L_0x2c0f560/d .functor NOT 1, L_0x2c0f470, C4<0>, C4<0>, C4<0>;
+L_0x2c0f560 .delay (10000,10000,10000) L_0x2c0f560/d;
+L_0x2c10930/d .functor NAND 1, L_0x2c118d0, L_0x2c105a0, C4<1>, C4<1>;
+L_0x2c10930 .delay (10000,10000,10000) L_0x2c10930/d;
+L_0x2c10a90/d .functor NAND 1, L_0x2c10930, L_0x2c0f560, C4<1>, C4<1>;
+L_0x2c10a90 .delay (10000,10000,10000) L_0x2c10a90/d;
+L_0x2c10ba0/d .functor NOT 1, L_0x2c10a90, C4<0>, C4<0>, C4<0>;
+L_0x2c10ba0 .delay (10000,10000,10000) L_0x2c10ba0/d;
+v0x2349d30_0 .net "A", 0 0, L_0x2c118d0; 1 drivers
+v0x2349dd0_0 .net "AnandB", 0 0, L_0x2c10930; 1 drivers
+v0x234d2d0_0 .net "AnorB", 0 0, L_0x2c0f470; 1 drivers
+v0x234d350_0 .net "AorB", 0 0, L_0x2c0f560; 1 drivers
+v0x234d070_0 .net "AxorB", 0 0, L_0x2c10ba0; 1 drivers
+v0x234d0f0_0 .net "B", 0 0, L_0x2c105a0; 1 drivers
+v0x234c1e0_0 .alias "Command", 2 0, v0x295f7a0_0;
+v0x234c260_0 .net "OrNorXorOut", 0 0, L_0x2c115c0; 1 drivers
+v0x234f6f0_0 .net "XorNor", 0 0, L_0x2c11020; 1 drivers
+v0x234f770_0 .net "nXor", 0 0, L_0x2c10a90; 1 drivers
+L_0x2c111a0 .part v0x2960210_0, 2, 1;
+L_0x2c11790 .part v0x2960210_0, 0, 1;
+S_0x2348710 .scope module, "mux0" "TwoInMux" 3 184, 3 109, S_0x2343db0;
+ .timescale -9 -12;
+L_0x2c10d00/d .functor NOT 1, L_0x2c111a0, C4<0>, C4<0>, C4<0>;
+L_0x2c10d00 .delay (10000,10000,10000) L_0x2c10d00/d;
+L_0x2c10dc0/d .functor AND 1, L_0x2c10ba0, L_0x2c10d00, C4<1>, C4<1>;
+L_0x2c10dc0 .delay (20000,20000,20000) L_0x2c10dc0/d;
+L_0x2c10ed0/d .functor AND 1, L_0x2c0f470, L_0x2c111a0, C4<1>, C4<1>;
+L_0x2c10ed0 .delay (20000,20000,20000) L_0x2c10ed0/d;
+L_0x2c11020/d .functor OR 1, L_0x2c10dc0, L_0x2c10ed0, C4<0>, C4<0>;
+L_0x2c11020 .delay (20000,20000,20000) L_0x2c11020/d;
+v0x2348a10_0 .net "S", 0 0, L_0x2c111a0; 1 drivers
+v0x2347880_0 .alias "in0", 0 0, v0x234d070_0;
+v0x2347900_0 .alias "in1", 0 0, v0x234d2d0_0;
+v0x234ae20_0 .net "nS", 0 0, L_0x2c10d00; 1 drivers
+v0x234aec0_0 .net "out0", 0 0, L_0x2c10dc0; 1 drivers
+v0x234abc0_0 .net "out1", 0 0, L_0x2c10ed0; 1 drivers
+v0x234ac40_0 .alias "outfinal", 0 0, v0x234f6f0_0;
+S_0x2342f20 .scope module, "mux1" "TwoInMux" 3 185, 3 109, S_0x2343db0;
+ .timescale -9 -12;
+L_0x2c11240/d .functor NOT 1, L_0x2c11790, C4<0>, C4<0>, C4<0>;
+L_0x2c11240 .delay (10000,10000,10000) L_0x2c11240/d;
+L_0x2c11300/d .functor AND 1, L_0x2c11020, L_0x2c11240, C4<1>, C4<1>;
+L_0x2c11300 .delay (20000,20000,20000) L_0x2c11300/d;
+L_0x2c11450/d .functor AND 1, L_0x2c0f560, L_0x2c11790, C4<1>, C4<1>;
+L_0x2c11450 .delay (20000,20000,20000) L_0x2c11450/d;
+L_0x2c115c0/d .functor OR 1, L_0x2c11300, L_0x2c11450, C4<0>, C4<0>;
+L_0x2c115c0 .delay (20000,20000,20000) L_0x2c115c0/d;
+v0x23464c0_0 .net "S", 0 0, L_0x2c11790; 1 drivers
+v0x2346560_0 .alias "in0", 0 0, v0x234f6f0_0;
+v0x2346260_0 .alias "in1", 0 0, v0x234d350_0;
+v0x2346300_0 .net "nS", 0 0, L_0x2c11240; 1 drivers
+v0x23453d0_0 .net "out0", 0 0, L_0x2c11300; 1 drivers
+v0x2345470_0 .net "out1", 0 0, L_0x2c11450; 1 drivers
+v0x2348970_0 .alias "outfinal", 0 0, v0x234c260_0;
+S_0x233d1c0 .scope module, "ZeroMux0case" "FourInMux" 3 57, 3 125, S_0x1f6b890;
+ .timescale -9 -12;
+L_0x2c11ab0/d .functor NOT 1, L_0x2b65aa0, C4<0>, C4<0>, C4<0>;
+L_0x2c11ab0 .delay (10000,10000,10000) L_0x2c11ab0/d;
+L_0x2c11b50/d .functor NOT 1, L_0x2b65bd0, C4<0>, C4<0>, C4<0>;
+L_0x2c11b50 .delay (10000,10000,10000) L_0x2c11b50/d;
+L_0x2c12ed0/d .functor NAND 1, L_0x2c11ab0, L_0x2c11b50, L_0x2b65d00, C4<1>;
+L_0x2c12ed0 .delay (10000,10000,10000) L_0x2c12ed0/d;
+L_0x2c12fc0/d .functor NAND 1, L_0x2b65aa0, L_0x2c11b50, L_0x2b65da0, C4<1>;
+L_0x2c12fc0 .delay (10000,10000,10000) L_0x2c12fc0/d;
+L_0x2c130b0/d .functor NAND 1, L_0x2c11ab0, L_0x2b65bd0, L_0x2b65e40, C4<1>;
+L_0x2c130b0 .delay (10000,10000,10000) L_0x2c130b0/d;
+L_0x2c131a0/d .functor NAND 1, L_0x2b65aa0, L_0x2b65bd0, L_0x2b65f30, C4<1>;
+L_0x2c131a0 .delay (10000,10000,10000) L_0x2c131a0/d;
+L_0x2c13280/d .functor NAND 1, L_0x2c12ed0, L_0x2c12fc0, L_0x2c130b0, L_0x2c131a0;
+L_0x2c13280 .delay (10000,10000,10000) L_0x2c13280/d;
+v0x233cf60_0 .net "S0", 0 0, L_0x2b65aa0; 1 drivers
+v0x233c100_0 .net "S1", 0 0, L_0x2b65bd0; 1 drivers
+v0x233c1a0_0 .net "in0", 0 0, L_0x2b65d00; 1 drivers
+v0x233f6b0_0 .net "in1", 0 0, L_0x2b65da0; 1 drivers
+v0x233f730_0 .net "in2", 0 0, L_0x2b65e40; 1 drivers
+v0x233f450_0 .net "in3", 0 0, L_0x2b65f30; 1 drivers
+v0x233f4f0_0 .net "nS0", 0 0, L_0x2c11ab0; 1 drivers
+v0x233e5c0_0 .net "nS1", 0 0, L_0x2c11b50; 1 drivers
+v0x233e640_0 .net "out", 0 0, L_0x2c13280; 1 drivers
+v0x2341b60_0 .net "out0", 0 0, L_0x2c12ed0; 1 drivers
+v0x2341c00_0 .net "out1", 0 0, L_0x2c12fc0; 1 drivers
+v0x2341900_0 .net "out2", 0 0, L_0x2c130b0; 1 drivers
+v0x2341980_0 .net "out3", 0 0, L_0x2c131a0; 1 drivers
+S_0x2336240 .scope module, "OneMux0case" "FourInMux" 3 58, 3 125, S_0x1f6b890;
+ .timescale -9 -12;
+L_0x2b66020/d .functor NOT 1, L_0x2b667d0, C4<0>, C4<0>, C4<0>;
+L_0x2b66020 .delay (10000,10000,10000) L_0x2b66020/d;
+L_0x2b660d0/d .functor NOT 1, L_0x2b66900, C4<0>, C4<0>, C4<0>;
+L_0x2b660d0 .delay (10000,10000,10000) L_0x2b660d0/d;
+L_0x2b66150/d .functor NAND 1, L_0x2b66020, L_0x2b660d0, L_0x2b66a30, C4<1>;
+L_0x2b66150 .delay (10000,10000,10000) L_0x2b66150/d;
+L_0x2b66290/d .functor NAND 1, L_0x2b667d0, L_0x2b660d0, L_0x2b66ad0, C4<1>;
+L_0x2b66290 .delay (10000,10000,10000) L_0x2b66290/d;
+L_0x2b66380/d .functor NAND 1, L_0x2b66020, L_0x2b66900, L_0x2b66b70, C4<1>;
+L_0x2b66380 .delay (10000,10000,10000) L_0x2b66380/d;
+L_0x2b66470/d .functor NAND 1, L_0x2b667d0, L_0x2b66900, L_0x2b66c60, C4<1>;
+L_0x2b66470 .delay (10000,10000,10000) L_0x2b66470/d;
+L_0x2b66550/d .functor NAND 1, L_0x2b66150, L_0x2b66290, L_0x2b66380, L_0x2b66470;
+L_0x2b66550 .delay (10000,10000,10000) L_0x2b66550/d;
+v0x23353e0_0 .net "S0", 0 0, L_0x2b667d0; 1 drivers
+v0x2338900_0 .net "S1", 0 0, L_0x2b66900; 1 drivers
+v0x23389a0_0 .net "in0", 0 0, L_0x2b66a30; 1 drivers
+v0x23386a0_0 .net "in1", 0 0, L_0x2b66ad0; 1 drivers
+v0x2338720_0 .net "in2", 0 0, L_0x2b66b70; 1 drivers
+v0x2337840_0 .net "in3", 0 0, L_0x2b66c60; 1 drivers
+v0x23378e0_0 .net "nS0", 0 0, L_0x2b66020; 1 drivers
+v0x233ad60_0 .net "nS1", 0 0, L_0x2b660d0; 1 drivers
+v0x233ade0_0 .net "out", 0 0, L_0x2b66550; 1 drivers
+v0x233ab00_0 .net "out0", 0 0, L_0x2b66150; 1 drivers
+v0x233aba0_0 .net "out1", 0 0, L_0x2b66290; 1 drivers
+v0x2339ca0_0 .net "out2", 0 0, L_0x2b66380; 1 drivers
+v0x2339d20_0 .net "out3", 0 0, L_0x2b66470; 1 drivers
+S_0x2334040 .scope module, "TwoMux0case" "TwoInMux" 3 59, 3 109, S_0x1f6b890;
+ .timescale -9 -12;
+L_0x2b66d50/d .functor NOT 1, L_0x2b3fbf0, C4<0>, C4<0>, C4<0>;
+L_0x2b66d50 .delay (10000,10000,10000) L_0x2b66d50/d;
+L_0x2b66e00/d .functor AND 1, L_0x2b3fc90, L_0x2b66d50, C4<1>, C4<1>;
+L_0x2b66e00 .delay (20000,20000,20000) L_0x2b66e00/d;
+L_0x2b4c6a0/d .functor AND 1, L_0x2b3fd80, L_0x2b3fbf0, C4<1>, C4<1>;
+L_0x2b4c6a0 .delay (20000,20000,20000) L_0x2b4c6a0/d;
+L_0x2b4c790/d .functor OR 1, L_0x2b66e00, L_0x2b4c6a0, C4<0>, C4<0>;
+L_0x2b4c790 .delay (20000,20000,20000) L_0x2b4c790/d;
+v0x2330bc0_0 .net "S", 0 0, L_0x2b3fbf0; 1 drivers
+v0x2333de0_0 .net "in0", 0 0, L_0x2b3fc90; 1 drivers
+v0x2333e60_0 .net "in1", 0 0, L_0x2b3fd80; 1 drivers
+v0x2332f80_0 .net "nS", 0 0, L_0x2b66d50; 1 drivers
+v0x2333020_0 .net "out0", 0 0, L_0x2b66e00; 1 drivers
+v0x23364a0_0 .net "out1", 0 0, L_0x2b4c6a0; 1 drivers
+v0x2336520_0 .net "outfinal", 0 0, L_0x2b4c790; 1 drivers
+S_0x2321990 .scope generate, "muxbits[1]" "muxbits[1]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x25e4918 .param/l "i" 3 64, +C4<01>;
+L_0x2b19860/d .functor OR 1, L_0x2b19d90, L_0x2b19b70, C4<0>, C4<0>;
+L_0x2b19860 .delay (20000,20000,20000) L_0x2b19860/d;
+v0x2331980_0 .net *"_s15", 0 0, L_0x2b19d90; 1 drivers
+v0x2330b20_0 .net *"_s16", 0 0, L_0x2b19b70; 1 drivers
+S_0x2329dc0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2321990;
+ .timescale -9 -12;
+L_0x2b153e0/d .functor NOT 1, L_0x2b17ce0, C4<0>, C4<0>, C4<0>;
+L_0x2b153e0 .delay (10000,10000,10000) L_0x2b153e0/d;
+L_0x2b15480/d .functor NOT 1, L_0x2b17e10, C4<0>, C4<0>, C4<0>;
+L_0x2b15480 .delay (10000,10000,10000) L_0x2b15480/d;
+L_0x2b15520/d .functor NAND 1, L_0x2b153e0, L_0x2b15480, L_0x2b17f40, C4<1>;
+L_0x2b15520 .delay (10000,10000,10000) L_0x2b15520/d;
+L_0x2b15660/d .functor NAND 1, L_0x2b17ce0, L_0x2b15480, L_0x2b17fe0, C4<1>;
+L_0x2b15660 .delay (10000,10000,10000) L_0x2b15660/d;
+L_0x2b15750/d .functor NAND 1, L_0x2b153e0, L_0x2b17e10, L_0x2b180d0, C4<1>;
+L_0x2b15750 .delay (10000,10000,10000) L_0x2b15750/d;
+L_0x2b17920/d .functor NAND 1, L_0x2b17ce0, L_0x2b17e10, L_0x2b18250, C4<1>;
+L_0x2b17920 .delay (10000,10000,10000) L_0x2b17920/d;
+L_0x2b17a30/d .functor NAND 1, L_0x2b15520, L_0x2b15660, L_0x2b15750, L_0x2b17920;
+L_0x2b17a30 .delay (10000,10000,10000) L_0x2b17a30/d;
+v0x232d360_0 .net "S0", 0 0, L_0x2b17ce0; 1 drivers
+v0x232d100_0 .net "S1", 0 0, L_0x2b17e10; 1 drivers
+v0x232d1a0_0 .net "in0", 0 0, L_0x2b17f40; 1 drivers
+v0x232c270_0 .net "in1", 0 0, L_0x2b17fe0; 1 drivers
+v0x232c2f0_0 .net "in2", 0 0, L_0x2b180d0; 1 drivers
+v0x232f780_0 .net "in3", 0 0, L_0x2b18250; 1 drivers
+v0x232f820_0 .net "nS0", 0 0, L_0x2b153e0; 1 drivers
+v0x232f520_0 .net "nS1", 0 0, L_0x2b15480; 1 drivers
+v0x232f5a0_0 .net "out", 0 0, L_0x2b17a30; 1 drivers
+v0x232e6c0_0 .net "out0", 0 0, L_0x2b15520; 1 drivers
+v0x232e760_0 .net "out1", 0 0, L_0x2b15660; 1 drivers
+v0x2331be0_0 .net "out2", 0 0, L_0x2b15750; 1 drivers
+v0x2331c60_0 .net "out3", 0 0, L_0x2b17920; 1 drivers
+S_0x2326550 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2321990;
+ .timescale -9 -12;
+L_0x2b18390/d .functor NOT 1, L_0x2b18c50, C4<0>, C4<0>, C4<0>;
+L_0x2b18390 .delay (10000,10000,10000) L_0x2b18390/d;
+L_0x2b18480/d .functor NOT 1, L_0x2b18d80, C4<0>, C4<0>, C4<0>;
+L_0x2b18480 .delay (10000,10000,10000) L_0x2b18480/d;
+L_0x2b18520/d .functor NAND 1, L_0x2b18390, L_0x2b18480, L_0x2b18f10, C4<1>;
+L_0x2b18520 .delay (10000,10000,10000) L_0x2b18520/d;
+L_0x2b18660/d .functor NAND 1, L_0x2b18c50, L_0x2b18480, L_0x2b18fb0, C4<1>;
+L_0x2b18660 .delay (10000,10000,10000) L_0x2b18660/d;
+L_0x2b18750/d .functor NAND 1, L_0x2b18390, L_0x2b18d80, L_0x2b190c0, C4<1>;
+L_0x2b18750 .delay (10000,10000,10000) L_0x2b18750/d;
+L_0x2b18840/d .functor NAND 1, L_0x2b18c50, L_0x2b18d80, L_0x2b191b0, C4<1>;
+L_0x2b18840 .delay (10000,10000,10000) L_0x2b18840/d;
+L_0x2b18950/d .functor NAND 1, L_0x2b18520, L_0x2b18660, L_0x2b18750, L_0x2b18840;
+L_0x2b18950 .delay (10000,10000,10000) L_0x2b18950/d;
+v0x23262f0_0 .net "S0", 0 0, L_0x2b18c50; 1 drivers
+v0x2325460_0 .net "S1", 0 0, L_0x2b18d80; 1 drivers
+v0x2325500_0 .net "in0", 0 0, L_0x2b18f10; 1 drivers
+v0x2328a00_0 .net "in1", 0 0, L_0x2b18fb0; 1 drivers
+v0x2328a80_0 .net "in2", 0 0, L_0x2b190c0; 1 drivers
+v0x23287a0_0 .net "in3", 0 0, L_0x2b191b0; 1 drivers
+v0x2328840_0 .net "nS0", 0 0, L_0x2b18390; 1 drivers
+v0x2327910_0 .net "nS1", 0 0, L_0x2b18480; 1 drivers
+v0x2327990_0 .net "out", 0 0, L_0x2b18950; 1 drivers
+v0x232aeb0_0 .net "out0", 0 0, L_0x2b18520; 1 drivers
+v0x232af50_0 .net "out1", 0 0, L_0x2b18660; 1 drivers
+v0x232ac50_0 .net "out2", 0 0, L_0x2b18750; 1 drivers
+v0x232acd0_0 .net "out3", 0 0, L_0x2b18840; 1 drivers
+S_0x2320b00 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2321990;
+ .timescale -9 -12;
+L_0x2b18eb0/d .functor NOT 1, L_0x2b197c0, C4<0>, C4<0>, C4<0>;
+L_0x2b18eb0 .delay (10000,10000,10000) L_0x2b18eb0/d;
+L_0x2b193b0/d .functor AND 1, L_0x2b198f0, L_0x2b18eb0, C4<1>, C4<1>;
+L_0x2b193b0 .delay (20000,20000,20000) L_0x2b193b0/d;
+L_0x2b194a0/d .functor AND 1, L_0x2b19a30, L_0x2b197c0, C4<1>, C4<1>;
+L_0x2b194a0 .delay (20000,20000,20000) L_0x2b194a0/d;
+L_0x2b19590/d .functor OR 1, L_0x2b193b0, L_0x2b194a0, C4<0>, C4<0>;
+L_0x2b19590 .delay (20000,20000,20000) L_0x2b19590/d;
+v0x2321c90_0 .net "S", 0 0, L_0x2b197c0; 1 drivers
+v0x23240a0_0 .net "in0", 0 0, L_0x2b198f0; 1 drivers
+v0x2324140_0 .net "in1", 0 0, L_0x2b19a30; 1 drivers
+v0x2323e40_0 .net "nS", 0 0, L_0x2b18eb0; 1 drivers
+v0x2323ec0_0 .net "out0", 0 0, L_0x2b193b0; 1 drivers
+v0x2322fb0_0 .net "out1", 0 0, L_0x2b194a0; 1 drivers
+v0x2323030_0 .net "outfinal", 0 0, L_0x2b19590; 1 drivers
+S_0x2314c20 .scope generate, "muxbits[2]" "muxbits[2]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26478f8 .param/l "i" 3 64, +C4<010>;
+L_0x2b1bca0/d .functor OR 1, L_0x2b1c4b0, L_0x2b1c7e0, C4<0>, C4<0>;
+L_0x2b1bca0 .delay (20000,20000,20000) L_0x2b1bca0/d;
+v0x231e5b0_0 .net *"_s15", 0 0, L_0x2b1c4b0; 1 drivers
+v0x2321bf0_0 .net *"_s16", 0 0, L_0x2b1c7e0; 1 drivers
+S_0x231bcc0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2314c20;
+ .timescale -9 -12;
+L_0x2b19f80/d .functor NOT 1, L_0x2b19e80, C4<0>, C4<0>, C4<0>;
+L_0x2b19f80 .delay (10000,10000,10000) L_0x2b19f80/d;
+L_0x2b1a070/d .functor NOT 1, L_0x2b1a8e0, C4<0>, C4<0>, C4<0>;
+L_0x2b1a070 .delay (10000,10000,10000) L_0x2b1a070/d;
+L_0x2b1a110/d .functor NAND 1, L_0x2b19f80, L_0x2b1a070, L_0x2b1a790, C4<1>;
+L_0x2b1a110 .delay (10000,10000,10000) L_0x2b1a110/d;
+L_0x2b1a250/d .functor NAND 1, L_0x2b19e80, L_0x2b1a070, L_0x2b1ab70, C4<1>;
+L_0x2b1a250 .delay (10000,10000,10000) L_0x2b1a250/d;
+L_0x2b1a340/d .functor NAND 1, L_0x2b19f80, L_0x2b1a8e0, L_0x2b1aa10, C4<1>;
+L_0x2b1a340 .delay (10000,10000,10000) L_0x2b1a340/d;
+L_0x2b1a430/d .functor NAND 1, L_0x2b19e80, L_0x2b1a8e0, L_0x2b1acf0, C4<1>;
+L_0x2b1a430 .delay (10000,10000,10000) L_0x2b1a430/d;
+L_0x2b1a510/d .functor NAND 1, L_0x2b1a110, L_0x2b1a250, L_0x2b1a340, L_0x2b1a430;
+L_0x2b1a510 .delay (10000,10000,10000) L_0x2b1a510/d;
+v0x231ba60_0 .net "S0", 0 0, L_0x2b19e80; 1 drivers
+v0x231b5c0_0 .net "S1", 0 0, L_0x2b1a8e0; 1 drivers
+v0x231b660_0 .net "in0", 0 0, L_0x2b1a790; 1 drivers
+v0x2366410_0 .net "in1", 0 0, L_0x2b1ab70; 1 drivers
+v0x2366490_0 .net "in2", 0 0, L_0x2b1aa10; 1 drivers
+v0x23661c0_0 .net "in3", 0 0, L_0x2b1acf0; 1 drivers
+v0x2366260_0 .net "nS0", 0 0, L_0x2b19f80; 1 drivers
+v0x2365340_0 .net "nS1", 0 0, L_0x2b1a070; 1 drivers
+v0x23653c0_0 .net "out", 0 0, L_0x2b1a510; 1 drivers
+v0x231f6d0_0 .net "out0", 0 0, L_0x2b1a110; 1 drivers
+v0x231f770_0 .net "out1", 0 0, L_0x2b1a250; 1 drivers
+v0x231f440_0 .net "out2", 0 0, L_0x2b1a340; 1 drivers
+v0x231f4c0_0 .net "out3", 0 0, L_0x2b1a430; 1 drivers
+S_0x2317b00 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2314c20;
+ .timescale -9 -12;
+L_0x2b1ac10/d .functor NOT 1, L_0x2b1b660, C4<0>, C4<0>, C4<0>;
+L_0x2b1ac10 .delay (10000,10000,10000) L_0x2b1ac10/d;
+L_0x2b1af20/d .functor NOT 1, L_0x2b1ade0, C4<0>, C4<0>, C4<0>;
+L_0x2b1af20 .delay (10000,10000,10000) L_0x2b1af20/d;
+L_0x2b1af80/d .functor NAND 1, L_0x2b1ac10, L_0x2b1af20, L_0x2b1b920, C4<1>;
+L_0x2b1af80 .delay (10000,10000,10000) L_0x2b1af80/d;
+L_0x2b1b0c0/d .functor NAND 1, L_0x2b1b660, L_0x2b1af20, L_0x2b1b790, C4<1>;
+L_0x2b1b0c0 .delay (10000,10000,10000) L_0x2b1b0c0/d;
+L_0x2b1b1b0/d .functor NAND 1, L_0x2b1ac10, L_0x2b1ade0, L_0x2b1bb60, C4<1>;
+L_0x2b1b1b0 .delay (10000,10000,10000) L_0x2b1b1b0/d;
+L_0x2b1b2a0/d .functor NAND 1, L_0x2b1b660, L_0x2b1ade0, L_0x2b1ba50, C4<1>;
+L_0x2b1b2a0 .delay (10000,10000,10000) L_0x2b1b2a0/d;
+L_0x2b1b3b0/d .functor NAND 1, L_0x2b1af80, L_0x2b1b0c0, L_0x2b1b1b0, L_0x2b1b2a0;
+L_0x2b1b3b0 .delay (10000,10000,10000) L_0x2b1b3b0/d;
+v0x2317660_0 .net "S0", 0 0, L_0x2b1b660; 1 drivers
+v0x2319280_0 .net "S1", 0 0, L_0x2b1ade0; 1 drivers
+v0x2319320_0 .net "in0", 0 0, L_0x2b1b920; 1 drivers
+v0x2319020_0 .net "in1", 0 0, L_0x2b1b790; 1 drivers
+v0x23190a0_0 .net "in2", 0 0, L_0x2b1bb60; 1 drivers
+v0x2318b80_0 .net "in3", 0 0, L_0x2b1ba50; 1 drivers
+v0x2318c20_0 .net "nS0", 0 0, L_0x2b1ac10; 1 drivers
+v0x231a7a0_0 .net "nS1", 0 0, L_0x2b1af20; 1 drivers
+v0x231a820_0 .net "out", 0 0, L_0x2b1b3b0; 1 drivers
+v0x231a540_0 .net "out0", 0 0, L_0x2b1af80; 1 drivers
+v0x231a5e0_0 .net "out1", 0 0, L_0x2b1b0c0; 1 drivers
+v0x231a0a0_0 .net "out2", 0 0, L_0x2b1b1b0; 1 drivers
+v0x231a120_0 .net "out3", 0 0, L_0x2b1b2a0; 1 drivers
+S_0x2316840 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2314c20;
+ .timescale -9 -12;
+L_0x2b1b830/d .functor NOT 1, L_0x2b1bc00, C4<0>, C4<0>, C4<0>;
+L_0x2b1b830 .delay (10000,10000,10000) L_0x2b1b830/d;
+L_0x2b1bd70/d .functor AND 1, L_0x2b1c2f0, L_0x2b1b830, C4<1>, C4<1>;
+L_0x2b1bd70 .delay (20000,20000,20000) L_0x2b1bd70/d;
+L_0x2b1be60/d .functor AND 1, L_0x2b1c1c0, L_0x2b1bc00, C4<1>, C4<1>;
+L_0x2b1be60 .delay (20000,20000,20000) L_0x2b1be60/d;
+L_0x2b1bf50/d .functor OR 1, L_0x2b1bd70, L_0x2b1be60, C4<0>, C4<0>;
+L_0x2b1bf50 .delay (20000,20000,20000) L_0x2b1bf50/d;
+v0x2315160_0 .net "S", 0 0, L_0x2b1bc00; 1 drivers
+v0x23165e0_0 .net "in0", 0 0, L_0x2b1c2f0; 1 drivers
+v0x2316680_0 .net "in1", 0 0, L_0x2b1c1c0; 1 drivers
+v0x2316140_0 .net "nS", 0 0, L_0x2b1b830; 1 drivers
+v0x23161c0_0 .net "out0", 0 0, L_0x2b1bd70; 1 drivers
+v0x2317d60_0 .net "out1", 0 0, L_0x2b1be60; 1 drivers
+v0x2317de0_0 .net "outfinal", 0 0, L_0x2b1bf50; 1 drivers
+S_0x230a7a0 .scope generate, "muxbits[3]" "muxbits[3]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26d5948 .param/l "i" 3 64, +C4<011>;
+L_0x2b1ec40/d .functor OR 1, L_0x2b1efc0, L_0x2b1edd0, C4<0>, C4<0>;
+L_0x2b1ec40 .delay (20000,20000,20000) L_0x2b1ec40/d;
+v0x2315320_0 .net *"_s15", 0 0, L_0x2b1efc0; 1 drivers
+v0x23150c0_0 .net *"_s16", 0 0, L_0x2b1edd0; 1 drivers
+S_0x2311160 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x230a7a0;
+ .timescale -9 -12;
+L_0x2b1c600/d .functor NOT 1, L_0x2b1d100, C4<0>, C4<0>, C4<0>;
+L_0x2b1c600 .delay (10000,10000,10000) L_0x2b1c600/d;
+L_0x2b1c6f0/d .functor NOT 1, L_0x2b1c880, C4<0>, C4<0>, C4<0>;
+L_0x2b1c6f0 .delay (10000,10000,10000) L_0x2b1c6f0/d;
+L_0x2b1ca20/d .functor NAND 1, L_0x2b1c600, L_0x2b1c6f0, L_0x2b1d3a0, C4<1>;
+L_0x2b1ca20 .delay (10000,10000,10000) L_0x2b1ca20/d;
+L_0x2b1cb60/d .functor NAND 1, L_0x2b1d100, L_0x2b1c6f0, L_0x2b1d230, C4<1>;
+L_0x2b1cb60 .delay (10000,10000,10000) L_0x2b1cb60/d;
+L_0x2b1cc50/d .functor NAND 1, L_0x2b1c600, L_0x2b1c880, L_0x2b1d2d0, C4<1>;
+L_0x2b1cc50 .delay (10000,10000,10000) L_0x2b1cc50/d;
+L_0x2b1cd40/d .functor NAND 1, L_0x2b1d100, L_0x2b1c880, L_0x2b1d440, C4<1>;
+L_0x2b1cd40 .delay (10000,10000,10000) L_0x2b1cd40/d;
+L_0x2b1ce50/d .functor NAND 1, L_0x2b1ca20, L_0x2b1cb60, L_0x2b1cc50, L_0x2b1cd40;
+L_0x2b1ce50 .delay (10000,10000,10000) L_0x2b1ce50/d;
+v0x2310cc0_0 .net "S0", 0 0, L_0x2b1d100; 1 drivers
+v0x23128e0_0 .net "S1", 0 0, L_0x2b1c880; 1 drivers
+v0x2312980_0 .net "in0", 0 0, L_0x2b1d3a0; 1 drivers
+v0x2312680_0 .net "in1", 0 0, L_0x2b1d230; 1 drivers
+v0x2312700_0 .net "in2", 0 0, L_0x2b1d2d0; 1 drivers
+v0x23121e0_0 .net "in3", 0 0, L_0x2b1d440; 1 drivers
+v0x2312280_0 .net "nS0", 0 0, L_0x2b1c600; 1 drivers
+v0x2313e00_0 .net "nS1", 0 0, L_0x2b1c6f0; 1 drivers
+v0x2313e80_0 .net "out", 0 0, L_0x2b1ce50; 1 drivers
+v0x2313ba0_0 .net "out0", 0 0, L_0x2b1ca20; 1 drivers
+v0x2313c40_0 .net "out1", 0 0, L_0x2b1cb60; 1 drivers
+v0x2313700_0 .net "out2", 0 0, L_0x2b1cc50; 1 drivers
+v0x2313780_0 .net "out3", 0 0, L_0x2b1cd40; 1 drivers
+S_0x230cd60 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x230a7a0;
+ .timescale -9 -12;
+L_0x2b1d530/d .functor NOT 1, L_0x2b1d720, C4<0>, C4<0>, C4<0>;
+L_0x2b1d530 .delay (10000,10000,10000) L_0x2b1d530/d;
+L_0x2b1d8f0/d .functor NOT 1, L_0x2b1e1e0, C4<0>, C4<0>, C4<0>;
+L_0x2b1d8f0 .delay (10000,10000,10000) L_0x2b1d8f0/d;
+L_0x2b1d990/d .functor NAND 1, L_0x2b1d530, L_0x2b1d8f0, L_0x2b1e040, C4<1>;
+L_0x2b1d990 .delay (10000,10000,10000) L_0x2b1d990/d;
+L_0x2b1dad0/d .functor NAND 1, L_0x2b1d720, L_0x2b1d8f0, L_0x2b1e0e0, C4<1>;
+L_0x2b1dad0 .delay (10000,10000,10000) L_0x2b1dad0/d;
+L_0x2b1dbc0/d .functor NAND 1, L_0x2b1d530, L_0x2b1e1e0, L_0x2b1e4d0, C4<1>;
+L_0x2b1dbc0 .delay (10000,10000,10000) L_0x2b1dbc0/d;
+L_0x2b1dcb0/d .functor NAND 1, L_0x2b1d720, L_0x2b1e1e0, L_0x2b1e570, C4<1>;
+L_0x2b1dcb0 .delay (10000,10000,10000) L_0x2b1dcb0/d;
+L_0x2b1dd90/d .functor NAND 1, L_0x2b1d990, L_0x2b1dad0, L_0x2b1dbc0, L_0x2b1dcb0;
+L_0x2b1dd90 .delay (10000,10000,10000) L_0x2b1dd90/d;
+v0x230e980_0 .net "S0", 0 0, L_0x2b1d720; 1 drivers
+v0x230e720_0 .net "S1", 0 0, L_0x2b1e1e0; 1 drivers
+v0x230e7c0_0 .net "in0", 0 0, L_0x2b1e040; 1 drivers
+v0x230e280_0 .net "in1", 0 0, L_0x2b1e0e0; 1 drivers
+v0x230e300_0 .net "in2", 0 0, L_0x2b1e4d0; 1 drivers
+v0x230fea0_0 .net "in3", 0 0, L_0x2b1e570; 1 drivers
+v0x230ff40_0 .net "nS0", 0 0, L_0x2b1d530; 1 drivers
+v0x230fc40_0 .net "nS1", 0 0, L_0x2b1d8f0; 1 drivers
+v0x230fcc0_0 .net "out", 0 0, L_0x2b1dd90; 1 drivers
+v0x230f7a0_0 .net "out0", 0 0, L_0x2b1d990; 1 drivers
+v0x230f840_0 .net "out1", 0 0, L_0x2b1dad0; 1 drivers
+v0x23113c0_0 .net "out2", 0 0, L_0x2b1dbc0; 1 drivers
+v0x2311440_0 .net "out3", 0 0, L_0x2b1dcb0; 1 drivers
+S_0x230bf40 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x230a7a0;
+ .timescale -9 -12;
+L_0x2b1e310/d .functor NOT 1, L_0x2b1eb00, C4<0>, C4<0>, C4<0>;
+L_0x2b1e310 .delay (10000,10000,10000) L_0x2b1e310/d;
+L_0x2b1e400/d .functor AND 1, L_0x2b1e610, L_0x2b1e310, C4<1>, C4<1>;
+L_0x2b1e400 .delay (20000,20000,20000) L_0x2b1e400/d;
+L_0x2b1e830/d .functor AND 1, L_0x2b1e700, L_0x2b1eb00, C4<1>, C4<1>;
+L_0x2b1e830 .delay (20000,20000,20000) L_0x2b1e830/d;
+L_0x2b1e920/d .functor OR 1, L_0x2b1e400, L_0x2b1e830, C4<0>, C4<0>;
+L_0x2b1e920 .delay (20000,20000,20000) L_0x2b1e920/d;
+v0x230aaa0_0 .net "S", 0 0, L_0x2b1eb00; 1 drivers
+v0x230bce0_0 .net "in0", 0 0, L_0x2b1e610; 1 drivers
+v0x230bd80_0 .net "in1", 0 0, L_0x2b1e700; 1 drivers
+v0x230d460_0 .net "nS", 0 0, L_0x2b1e310; 1 drivers
+v0x230d4e0_0 .net "out0", 0 0, L_0x2b1e400; 1 drivers
+v0x230d200_0 .net "out1", 0 0, L_0x2b1e830; 1 drivers
+v0x230d280_0 .net "outfinal", 0 0, L_0x2b1e920; 1 drivers
+S_0x22fa460 .scope generate, "muxbits[4]" "muxbits[4]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x2651258 .param/l "i" 3 64, +C4<0100>;
+L_0x2b214f0/d .functor OR 1, L_0x2b21970, L_0x2b21b20, C4<0>, C4<0>;
+L_0x2b214f0 .delay (20000,20000,20000) L_0x2b214f0/d;
+v0x2309260_0 .net *"_s15", 0 0, L_0x2b21970; 1 drivers
+v0x230aa00_0 .net *"_s16", 0 0, L_0x2b21b20; 1 drivers
+S_0x2303d60 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22fa460;
+ .timescale -9 -12;
+L_0x2b1eec0/d .functor NOT 1, L_0x2b1f060, C4<0>, C4<0>, C4<0>;
+L_0x2b1eec0 .delay (10000,10000,10000) L_0x2b1eec0/d;
+L_0x2b19330/d .functor NOT 1, L_0x2b1f190, C4<0>, C4<0>, C4<0>;
+L_0x2b19330 .delay (10000,10000,10000) L_0x2b19330/d;
+L_0x2b1ecf0/d .functor NAND 1, L_0x2b1eec0, L_0x2b19330, L_0x2b1f7d0, C4<1>;
+L_0x2b1ecf0 .delay (10000,10000,10000) L_0x2b1ecf0/d;
+L_0x2b1f2b0/d .functor NAND 1, L_0x2b1f060, L_0x2b19330, L_0x2b1fc90, C4<1>;
+L_0x2b1f2b0 .delay (10000,10000,10000) L_0x2b1f2b0/d;
+L_0x2b1f360/d .functor NAND 1, L_0x2b1eec0, L_0x2b1f190, L_0x2b1fa70, C4<1>;
+L_0x2b1f360 .delay (10000,10000,10000) L_0x2b1f360/d;
+L_0x2b1f410/d .functor NAND 1, L_0x2b1f060, L_0x2b1f190, L_0x2b1fb60, C4<1>;
+L_0x2b1f410 .delay (10000,10000,10000) L_0x2b1f410/d;
+L_0x2b1f520/d .functor NAND 1, L_0x2b1ecf0, L_0x2b1f2b0, L_0x2b1f360, L_0x2b1f410;
+L_0x2b1f520 .delay (10000,10000,10000) L_0x2b1f520/d;
+v0x2305500_0 .net "S0", 0 0, L_0x2b1f060; 1 drivers
+v0x23052a0_0 .net "S1", 0 0, L_0x2b1f190; 1 drivers
+v0x2305340_0 .net "in0", 0 0, L_0x2b1f7d0; 1 drivers
+v0x2306a40_0 .net "in1", 0 0, L_0x2b1fc90; 1 drivers
+v0x2306ac0_0 .net "in2", 0 0, L_0x2b1fa70; 1 drivers
+v0x23067e0_0 .net "in3", 0 0, L_0x2b1fb60; 1 drivers
+v0x2306880_0 .net "nS0", 0 0, L_0x2b1eec0; 1 drivers
+v0x2307f80_0 .net "nS1", 0 0, L_0x2b19330; 1 drivers
+v0x2308000_0 .net "out", 0 0, L_0x2b1f520; 1 drivers
+v0x2307d20_0 .net "out0", 0 0, L_0x2b1ecf0; 1 drivers
+v0x2307dc0_0 .net "out1", 0 0, L_0x2b1f2b0; 1 drivers
+v0x23094c0_0 .net "out2", 0 0, L_0x2b1f360; 1 drivers
+v0x2309540_0 .net "out3", 0 0, L_0x2b1f410; 1 drivers
+S_0x22fe860 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22fa460;
+ .timescale -9 -12;
+L_0x2b1f980/d .functor NOT 1, L_0x2b206e0, C4<0>, C4<0>, C4<0>;
+L_0x2b1f980 .delay (10000,10000,10000) L_0x2b1f980/d;
+L_0x2b1ff70/d .functor NOT 1, L_0x2b1fd30, C4<0>, C4<0>, C4<0>;
+L_0x2b1ff70 .delay (10000,10000,10000) L_0x2b1ff70/d;
+L_0x2b1ffd0/d .functor NAND 1, L_0x2b1f980, L_0x2b1ff70, L_0x2b1fe60, C4<1>;
+L_0x2b1ffd0 .delay (10000,10000,10000) L_0x2b1ffd0/d;
+L_0x2b20110/d .functor NAND 1, L_0x2b206e0, L_0x2b1ff70, L_0x2b20810, C4<1>;
+L_0x2b20110 .delay (10000,10000,10000) L_0x2b20110/d;
+L_0x2b20200/d .functor NAND 1, L_0x2b1f980, L_0x2b1fd30, L_0x2b208b0, C4<1>;
+L_0x2b20200 .delay (10000,10000,10000) L_0x2b20200/d;
+L_0x2b202f0/d .functor NAND 1, L_0x2b206e0, L_0x2b1fd30, L_0x2b209a0, C4<1>;
+L_0x2b202f0 .delay (10000,10000,10000) L_0x2b202f0/d;
+L_0x2b20430/d .functor NAND 1, L_0x2b1ffd0, L_0x2b20110, L_0x2b20200, L_0x2b202f0;
+L_0x2b20430 .delay (10000,10000,10000) L_0x2b20430/d;
+v0x2300000_0 .net "S0", 0 0, L_0x2b206e0; 1 drivers
+v0x22ffda0_0 .net "S1", 0 0, L_0x2b1fd30; 1 drivers
+v0x22ffe40_0 .net "in0", 0 0, L_0x2b1fe60; 1 drivers
+v0x2301540_0 .net "in1", 0 0, L_0x2b20810; 1 drivers
+v0x23015c0_0 .net "in2", 0 0, L_0x2b208b0; 1 drivers
+v0x23012e0_0 .net "in3", 0 0, L_0x2b209a0; 1 drivers
+v0x2301380_0 .net "nS0", 0 0, L_0x2b1f980; 1 drivers
+v0x2302a80_0 .net "nS1", 0 0, L_0x2b1ff70; 1 drivers
+v0x2302b00_0 .net "out", 0 0, L_0x2b20430; 1 drivers
+v0x2302820_0 .net "out0", 0 0, L_0x2b1ffd0; 1 drivers
+v0x23028c0_0 .net "out1", 0 0, L_0x2b20110; 1 drivers
+v0x2303fc0_0 .net "out2", 0 0, L_0x2b20200; 1 drivers
+v0x2304040_0 .net "out3", 0 0, L_0x2b202f0; 1 drivers
+S_0x22fc040 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22fa460;
+ .timescale -9 -12;
+L_0x2b1b9c0/d .functor NOT 1, L_0x2b20b70, C4<0>, C4<0>, C4<0>;
+L_0x2b1b9c0 .delay (10000,10000,10000) L_0x2b1b9c0/d;
+L_0x2b20e70/d .functor AND 1, L_0x2b20c10, L_0x2b1b9c0, C4<1>, C4<1>;
+L_0x2b20e70 .delay (20000,20000,20000) L_0x2b20e70/d;
+L_0x2b20f60/d .functor AND 1, L_0x2b20d00, L_0x2b20b70, C4<1>, C4<1>;
+L_0x2b20f60 .delay (20000,20000,20000) L_0x2b20f60/d;
+L_0x2b21050/d .functor OR 1, L_0x2b20e70, L_0x2b20f60, C4<0>, C4<0>;
+L_0x2b21050 .delay (20000,20000,20000) L_0x2b21050/d;
+v0x22fa9a0_0 .net "S", 0 0, L_0x2b20b70; 1 drivers
+v0x22fd580_0 .net "in0", 0 0, L_0x2b20c10; 1 drivers
+v0x22fd620_0 .net "in1", 0 0, L_0x2b20d00; 1 drivers
+v0x22fd320_0 .net "nS", 0 0, L_0x2b1b9c0; 1 drivers
+v0x22fd3a0_0 .net "out0", 0 0, L_0x2b20e70; 1 drivers
+v0x22feac0_0 .net "out1", 0 0, L_0x2b20f60; 1 drivers
+v0x22feb40_0 .net "outfinal", 0 0, L_0x2b21050; 1 drivers
+S_0x22d9c70 .scope generate, "muxbits[5]" "muxbits[5]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26a5ce8 .param/l "i" 3 64, +C4<0101>;
+L_0x2b23ba0/d .functor OR 1, L_0x2b23ce0, L_0x2b23d80, C4<0>, C4<0>;
+L_0x2b23ba0 .delay (20000,20000,20000) L_0x2b23ba0/d;
+v0x22fab60_0 .net *"_s15", 0 0, L_0x2b23ce0; 1 drivers
+v0x22fa900_0 .net *"_s16", 0 0, L_0x2b23d80; 1 drivers
+S_0x22f69a0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22d9c70;
+ .timescale -9 -12;
+L_0x2b1c750/d .functor NOT 1, L_0x2b22320, C4<0>, C4<0>, C4<0>;
+L_0x2b1c750 .delay (10000,10000,10000) L_0x2b1c750/d;
+L_0x2b21720/d .functor NOT 1, L_0x2b21bc0, C4<0>, C4<0>, C4<0>;
+L_0x2b21720 .delay (10000,10000,10000) L_0x2b21720/d;
+L_0x2b21780/d .functor NAND 1, L_0x2b1c750, L_0x2b21720, L_0x2b21cf0, C4<1>;
+L_0x2b21780 .delay (10000,10000,10000) L_0x2b21780/d;
+L_0x2b21880/d .functor NAND 1, L_0x2b22320, L_0x2b21720, L_0x2b21d90, C4<1>;
+L_0x2b21880 .delay (10000,10000,10000) L_0x2b21880/d;
+L_0x2b21e70/d .functor NAND 1, L_0x2b1c750, L_0x2b21bc0, L_0x2b22720, C4<1>;
+L_0x2b21e70 .delay (10000,10000,10000) L_0x2b21e70/d;
+L_0x2b21f60/d .functor NAND 1, L_0x2b22320, L_0x2b21bc0, L_0x2b22450, C4<1>;
+L_0x2b21f60 .delay (10000,10000,10000) L_0x2b21f60/d;
+L_0x2b22070/d .functor NAND 1, L_0x2b21780, L_0x2b21880, L_0x2b21e70, L_0x2b21f60;
+L_0x2b22070 .delay (10000,10000,10000) L_0x2b22070/d;
+v0x22f6500_0 .net "S0", 0 0, L_0x2b22320; 1 drivers
+v0x22f8120_0 .net "S1", 0 0, L_0x2b21bc0; 1 drivers
+v0x22f81c0_0 .net "in0", 0 0, L_0x2b21cf0; 1 drivers
+v0x22f7ec0_0 .net "in1", 0 0, L_0x2b21d90; 1 drivers
+v0x22f7f40_0 .net "in2", 0 0, L_0x2b22720; 1 drivers
+v0x22f7a20_0 .net "in3", 0 0, L_0x2b22450; 1 drivers
+v0x22f7ac0_0 .net "nS0", 0 0, L_0x2b1c750; 1 drivers
+v0x22f9640_0 .net "nS1", 0 0, L_0x2b21720; 1 drivers
+v0x22f96c0_0 .net "out", 0 0, L_0x2b22070; 1 drivers
+v0x22f93e0_0 .net "out0", 0 0, L_0x2b21780; 1 drivers
+v0x22f9480_0 .net "out1", 0 0, L_0x2b21880; 1 drivers
+v0x22f8f40_0 .net "out2", 0 0, L_0x2b21e70; 1 drivers
+v0x22f8fc0_0 .net "out3", 0 0, L_0x2b21f60; 1 drivers
+S_0x22e9e50 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22d9c70;
+ .timescale -9 -12;
+L_0x2b22540/d .functor NOT 1, L_0x2b22810, C4<0>, C4<0>, C4<0>;
+L_0x2b22540 .delay (10000,10000,10000) L_0x2b22540/d;
+L_0x2b225f0/d .functor NOT 1, L_0x2b22940, C4<0>, C4<0>, C4<0>;
+L_0x2b225f0 .delay (10000,10000,10000) L_0x2b225f0/d;
+L_0x2b22690/d .functor NAND 1, L_0x2b22540, L_0x2b225f0, L_0x2b234a0, C4<1>;
+L_0x2b22690 .delay (10000,10000,10000) L_0x2b22690/d;
+L_0x2b22bd0/d .functor NAND 1, L_0x2b22810, L_0x2b225f0, L_0x2b23540, C4<1>;
+L_0x2b22bd0 .delay (10000,10000,10000) L_0x2b22bd0/d;
+L_0x2b22cc0/d .functor NAND 1, L_0x2b22540, L_0x2b22940, L_0x2b231a0, C4<1>;
+L_0x2b22cc0 .delay (10000,10000,10000) L_0x2b22cc0/d;
+L_0x2b22db0/d .functor NAND 1, L_0x2b22810, L_0x2b22940, L_0x2b23290, C4<1>;
+L_0x2b22db0 .delay (10000,10000,10000) L_0x2b22db0/d;
+L_0x2b22ef0/d .functor NAND 1, L_0x2b22690, L_0x2b22bd0, L_0x2b22cc0, L_0x2b22db0;
+L_0x2b22ef0 .delay (10000,10000,10000) L_0x2b22ef0/d;
+v0x22e7dd0_0 .net "S0", 0 0, L_0x2b22810; 1 drivers
+v0x231d250_0 .net "S1", 0 0, L_0x2b22940; 1 drivers
+v0x231d2f0_0 .net "in0", 0 0, L_0x2b234a0; 1 drivers
+v0x231d000_0 .net "in1", 0 0, L_0x2b23540; 1 drivers
+v0x231d080_0 .net "in2", 0 0, L_0x2b231a0; 1 drivers
+v0x22f3e90_0 .net "in3", 0 0, L_0x2b23290; 1 drivers
+v0x22f3f30_0 .net "nS0", 0 0, L_0x2b22540; 1 drivers
+v0x22f56e0_0 .net "nS1", 0 0, L_0x2b225f0; 1 drivers
+v0x22f5760_0 .net "out", 0 0, L_0x2b22ef0; 1 drivers
+v0x22f5480_0 .net "out0", 0 0, L_0x2b22690; 1 drivers
+v0x22f5520_0 .net "out1", 0 0, L_0x2b22bd0; 1 drivers
+v0x22f6c00_0 .net "out2", 0 0, L_0x2b22cc0; 1 drivers
+v0x22f6c80_0 .net "out3", 0 0, L_0x2b22db0; 1 drivers
+S_0x22e07b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22d9c70;
+ .timescale -9 -12;
+L_0x2b22a70/d .functor NOT 1, L_0x2b23850, C4<0>, C4<0>, C4<0>;
+L_0x2b22a70 .delay (10000,10000,10000) L_0x2b22a70/d;
+L_0x2b1d6a0/d .functor AND 1, L_0x2b23e30, L_0x2b22a70, C4<1>, C4<1>;
+L_0x2b1d6a0 .delay (20000,20000,20000) L_0x2b1d6a0/d;
+L_0x2b23410/d .functor AND 1, L_0x2b23f20, L_0x2b23850, C4<1>, C4<1>;
+L_0x2b23410 .delay (20000,20000,20000) L_0x2b23410/d;
+L_0x2b23670/d .functor OR 1, L_0x2b1d6a0, L_0x2b23410, C4<0>, C4<0>;
+L_0x2b23670 .delay (20000,20000,20000) L_0x2b23670/d;
+v0x22dbd00_0 .net "S", 0 0, L_0x2b23850; 1 drivers
+v0x22de730_0 .net "in0", 0 0, L_0x2b23e30; 1 drivers
+v0x22de7d0_0 .net "in1", 0 0, L_0x2b23f20; 1 drivers
+v0x22e5300_0 .net "nS", 0 0, L_0x2b22a70; 1 drivers
+v0x22e5380_0 .net "out0", 0 0, L_0x2b1d6a0; 1 drivers
+v0x22e3280_0 .net "out1", 0 0, L_0x2b23410; 1 drivers
+v0x22e3300_0 .net "outfinal", 0 0, L_0x2b23670; 1 drivers
+S_0x22b91b0 .scope generate, "muxbits[6]" "muxbits[6]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x268f3a8 .param/l "i" 3 64, +C4<0110>;
+L_0x2b25f30/d .functor OR 1, L_0x2b26a00, L_0x2b26aa0, C4<0>, C4<0>;
+L_0x2b25f30 .delay (20000,20000,20000) L_0x2b25f30/d;
+v0x22d5260_0 .net *"_s15", 0 0, L_0x2b26a00; 1 drivers
+v0x22dbc60_0 .net *"_s16", 0 0, L_0x2b26aa0; 1 drivers
+S_0x22d4330 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22b91b0;
+ .timescale -9 -12;
+L_0x2b243b0/d .functor NOT 1, L_0x2b24010, C4<0>, C4<0>, C4<0>;
+L_0x2b243b0 .delay (10000,10000,10000) L_0x2b243b0/d;
+L_0x2b244a0/d .functor NOT 1, L_0x2b24140, C4<0>, C4<0>, C4<0>;
+L_0x2b244a0 .delay (10000,10000,10000) L_0x2b244a0/d;
+L_0x2b24540/d .functor NAND 1, L_0x2b243b0, L_0x2b244a0, L_0x2b24270, C4<1>;
+L_0x2b24540 .delay (10000,10000,10000) L_0x2b24540/d;
+L_0x2b24680/d .functor NAND 1, L_0x2b24010, L_0x2b244a0, L_0x2b24fc0, C4<1>;
+L_0x2b24680 .delay (10000,10000,10000) L_0x2b24680/d;
+L_0x2b24770/d .functor NAND 1, L_0x2b243b0, L_0x2b24140, L_0x2b24c50, C4<1>;
+L_0x2b24770 .delay (10000,10000,10000) L_0x2b24770/d;
+L_0x2b24860/d .functor NAND 1, L_0x2b24010, L_0x2b24140, L_0x2b24cf0, C4<1>;
+L_0x2b24860 .delay (10000,10000,10000) L_0x2b24860/d;
+L_0x2b249a0/d .functor NAND 1, L_0x2b24540, L_0x2b24680, L_0x2b24770, L_0x2b24860;
+L_0x2b249a0 .delay (10000,10000,10000) L_0x2b249a0/d;
+v0x22d25f0_0 .net "S0", 0 0, L_0x2b24010; 1 drivers
+v0x22d2360_0 .net "S1", 0 0, L_0x2b24140; 1 drivers
+v0x22d2400_0 .net "in0", 0 0, L_0x2b24270; 1 drivers
+v0x22d0850_0 .net "in1", 0 0, L_0x2b24fc0; 1 drivers
+v0x22d08d0_0 .net "in2", 0 0, L_0x2b24c50; 1 drivers
+v0x22d8fd0_0 .net "in3", 0 0, L_0x2b24cf0; 1 drivers
+v0x22d9070_0 .net "nS0", 0 0, L_0x2b243b0; 1 drivers
+v0x22d8d40_0 .net "nS1", 0 0, L_0x2b244a0; 1 drivers
+v0x22d8dc0_0 .net "out", 0 0, L_0x2b249a0; 1 drivers
+v0x22d7000_0 .net "out0", 0 0, L_0x2b24540; 1 drivers
+v0x22d70a0_0 .net "out1", 0 0, L_0x2b24680; 1 drivers
+v0x22d6d70_0 .net "out2", 0 0, L_0x2b24770; 1 drivers
+v0x22d6df0_0 .net "out3", 0 0, L_0x2b24860; 1 drivers
+S_0x22c9370 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22b91b0;
+ .timescale -9 -12;
+L_0x2b24de0/d .functor NOT 1, L_0x2b25ae0, C4<0>, C4<0>, C4<0>;
+L_0x2b24de0 .delay (10000,10000,10000) L_0x2b24de0/d;
+L_0x2b24ed0/d .functor NOT 1, L_0x2b25060, C4<0>, C4<0>, C4<0>;
+L_0x2b24ed0 .delay (10000,10000,10000) L_0x2b24ed0/d;
+L_0x2b253f0/d .functor NAND 1, L_0x2b24de0, L_0x2b24ed0, L_0x2b25190, C4<1>;
+L_0x2b253f0 .delay (10000,10000,10000) L_0x2b253f0/d;
+L_0x2b254e0/d .functor NAND 1, L_0x2b25ae0, L_0x2b24ed0, L_0x2b25230, C4<1>;
+L_0x2b254e0 .delay (10000,10000,10000) L_0x2b254e0/d;
+L_0x2b255d0/d .functor NAND 1, L_0x2b24de0, L_0x2b25060, L_0x2b252d0, C4<1>;
+L_0x2b255d0 .delay (10000,10000,10000) L_0x2b255d0/d;
+L_0x2b256c0/d .functor NAND 1, L_0x2b25ae0, L_0x2b25060, L_0x2b25fd0, C4<1>;
+L_0x2b256c0 .delay (10000,10000,10000) L_0x2b256c0/d;
+L_0x2b25830/d .functor NAND 1, L_0x2b253f0, L_0x2b254e0, L_0x2b255d0, L_0x2b256c0;
+L_0x2b25830 .delay (10000,10000,10000) L_0x2b25830/d;
+v0x22c72f0_0 .net "S0", 0 0, L_0x2b25ae0; 1 drivers
+v0x22cfbb0_0 .net "S1", 0 0, L_0x2b25060; 1 drivers
+v0x22cfc50_0 .net "in0", 0 0, L_0x2b25190; 1 drivers
+v0x22cf920_0 .net "in1", 0 0, L_0x2b25230; 1 drivers
+v0x22cf9a0_0 .net "in2", 0 0, L_0x2b252d0; 1 drivers
+v0x22cdbe0_0 .net "in3", 0 0, L_0x2b25fd0; 1 drivers
+v0x22cdc80_0 .net "nS0", 0 0, L_0x2b24de0; 1 drivers
+v0x22cd950_0 .net "nS1", 0 0, L_0x2b24ed0; 1 drivers
+v0x22cd9d0_0 .net "out", 0 0, L_0x2b25830; 1 drivers
+v0x22cbe40_0 .net "out0", 0 0, L_0x2b253f0; 1 drivers
+v0x22cbee0_0 .net "out1", 0 0, L_0x2b254e0; 1 drivers
+v0x22d45c0_0 .net "out2", 0 0, L_0x2b255d0; 1 drivers
+v0x22d4640_0 .net "out3", 0 0, L_0x2b256c0; 1 drivers
+S_0x22bfcd0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22b91b0;
+ .timescale -9 -12;
+L_0x2b260c0/d .functor NOT 1, L_0x2b25c10, C4<0>, C4<0>, C4<0>;
+L_0x2b260c0 .delay (10000,10000,10000) L_0x2b260c0/d;
+L_0x2b261b0/d .functor AND 1, L_0x2b25cb0, L_0x2b260c0, C4<1>, C4<1>;
+L_0x2b261b0 .delay (20000,20000,20000) L_0x2b261b0/d;
+L_0x2b262a0/d .functor AND 1, L_0x2b25da0, L_0x2b25c10, C4<1>, C4<1>;
+L_0x2b262a0 .delay (20000,20000,20000) L_0x2b262a0/d;
+L_0x2b26390/d .functor OR 1, L_0x2b261b0, L_0x2b262a0, C4<0>, C4<0>;
+L_0x2b26390 .delay (20000,20000,20000) L_0x2b26390/d;
+v0x22bad60_0 .net "S", 0 0, L_0x2b25c10; 1 drivers
+v0x22bdc50_0 .net "in0", 0 0, L_0x2b25cb0; 1 drivers
+v0x22bdcf0_0 .net "in1", 0 0, L_0x2b25da0; 1 drivers
+v0x22c4820_0 .net "nS", 0 0, L_0x2b260c0; 1 drivers
+v0x22c48a0_0 .net "out0", 0 0, L_0x2b261b0; 1 drivers
+v0x22c27a0_0 .net "out1", 0 0, L_0x2b262a0; 1 drivers
+v0x22c2820_0 .net "outfinal", 0 0, L_0x2b26390; 1 drivers
+S_0x229d190 .scope generate, "muxbits[7]" "muxbits[7]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x264b158 .param/l "i" 3 64, +C4<0111>;
+L_0x2b28810/d .functor OR 1, L_0x2b28950, L_0x2b289f0, C4<0>, C4<0>;
+L_0x2b28810 .delay (20000,20000,20000) L_0x2b28810/d;
+v0x22baf50_0 .net *"_s15", 0 0, L_0x2b28950; 1 drivers
+v0x22bacc0_0 .net *"_s16", 0 0, L_0x2b289f0; 1 drivers
+S_0x22b18a0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x229d190;
+ .timescale -9 -12;
+L_0x2b248c0/d .functor NOT 1, L_0x2b27350, C4<0>, C4<0>, C4<0>;
+L_0x2b248c0 .delay (10000,10000,10000) L_0x2b248c0/d;
+L_0x2b265c0/d .functor NOT 1, L_0x2b26b90, C4<0>, C4<0>, C4<0>;
+L_0x2b265c0 .delay (10000,10000,10000) L_0x2b265c0/d;
+L_0x2b26620/d .functor NAND 1, L_0x2b248c0, L_0x2b265c0, L_0x2b26cc0, C4<1>;
+L_0x2b26620 .delay (10000,10000,10000) L_0x2b26620/d;
+L_0x2b26720/d .functor NAND 1, L_0x2b27350, L_0x2b265c0, L_0x2b26d60, C4<1>;
+L_0x2b26720 .delay (10000,10000,10000) L_0x2b26720/d;
+L_0x2b267d0/d .functor NAND 1, L_0x2b248c0, L_0x2b26b90, L_0x2b26e00, C4<1>;
+L_0x2b267d0 .delay (10000,10000,10000) L_0x2b267d0/d;
+L_0x2b268f0/d .functor NAND 1, L_0x2b27350, L_0x2b26b90, L_0x2b26ef0, C4<1>;
+L_0x2b268f0 .delay (10000,10000,10000) L_0x2b268f0/d;
+L_0x2b270a0/d .functor NAND 1, L_0x2b26620, L_0x2b26720, L_0x2b267d0, L_0x2b268f0;
+L_0x2b270a0 .delay (10000,10000,10000) L_0x2b270a0/d;
+v0x22afd90_0 .net "S0", 0 0, L_0x2b27350; 1 drivers
+v0x22b8510_0 .net "S1", 0 0, L_0x2b26b90; 1 drivers
+v0x22b85b0_0 .net "in0", 0 0, L_0x2b26cc0; 1 drivers
+v0x22b8280_0 .net "in1", 0 0, L_0x2b26d60; 1 drivers
+v0x22b8300_0 .net "in2", 0 0, L_0x2b26e00; 1 drivers
+v0x22b6540_0 .net "in3", 0 0, L_0x2b26ef0; 1 drivers
+v0x22b65e0_0 .net "nS0", 0 0, L_0x2b248c0; 1 drivers
+v0x22b62b0_0 .net "nS1", 0 0, L_0x2b265c0; 1 drivers
+v0x22b6330_0 .net "out", 0 0, L_0x2b270a0; 1 drivers
+v0x22b47a0_0 .net "out0", 0 0, L_0x2b26620; 1 drivers
+v0x22b4840_0 .net "out1", 0 0, L_0x2b26720; 1 drivers
+v0x22bb1b0_0 .net "out2", 0 0, L_0x2b267d0; 1 drivers
+v0x22bb230_0 .net "out3", 0 0, L_0x2b268f0; 1 drivers
+S_0x22af0f0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x229d190;
+ .timescale -9 -12;
+L_0x2b192a0/d .functor NOT 1, L_0x2b27480, C4<0>, C4<0>, C4<0>;
+L_0x2b192a0 .delay (10000,10000,10000) L_0x2b192a0/d;
+L_0x2b27a60/d .functor NOT 1, L_0x2b275b0, C4<0>, C4<0>, C4<0>;
+L_0x2b27a60 .delay (10000,10000,10000) L_0x2b27a60/d;
+L_0x2b27ac0/d .functor NAND 1, L_0x2b192a0, L_0x2b27a60, L_0x2b276e0, C4<1>;
+L_0x2b27ac0 .delay (10000,10000,10000) L_0x2b27ac0/d;
+L_0x2b27c00/d .functor NAND 1, L_0x2b27480, L_0x2b27a60, L_0x2b27780, C4<1>;
+L_0x2b27c00 .delay (10000,10000,10000) L_0x2b27c00/d;
+L_0x2b27cf0/d .functor NAND 1, L_0x2b192a0, L_0x2b275b0, L_0x2b28630, C4<1>;
+L_0x2b27cf0 .delay (10000,10000,10000) L_0x2b27cf0/d;
+L_0x2b27de0/d .functor NAND 1, L_0x2b27480, L_0x2b275b0, L_0x2b286d0, C4<1>;
+L_0x2b27de0 .delay (10000,10000,10000) L_0x2b27de0/d;
+L_0x2b27f20/d .functor NAND 1, L_0x2b27ac0, L_0x2b27c00, L_0x2b27cf0, L_0x2b27de0;
+L_0x2b27f20 .delay (10000,10000,10000) L_0x2b27f20/d;
+v0x22aee60_0 .net "S0", 0 0, L_0x2b27480; 1 drivers
+v0x22ad120_0 .net "S1", 0 0, L_0x2b275b0; 1 drivers
+v0x22ad1c0_0 .net "in0", 0 0, L_0x2b276e0; 1 drivers
+v0x22ace90_0 .net "in1", 0 0, L_0x2b27780; 1 drivers
+v0x22acf10_0 .net "in2", 0 0, L_0x2b28630; 1 drivers
+v0x22ab380_0 .net "in3", 0 0, L_0x2b286d0; 1 drivers
+v0x22ab420_0 .net "nS0", 0 0, L_0x2b192a0; 1 drivers
+v0x22b3b00_0 .net "nS1", 0 0, L_0x2b27a60; 1 drivers
+v0x22b3b80_0 .net "out", 0 0, L_0x2b27f20; 1 drivers
+v0x22b3870_0 .net "out0", 0 0, L_0x2b27ac0; 1 drivers
+v0x22b3910_0 .net "out1", 0 0, L_0x2b27c00; 1 drivers
+v0x22b1b30_0 .net "out2", 0 0, L_0x2b27cf0; 1 drivers
+v0x22b1bb0_0 .net "out3", 0 0, L_0x2b27de0; 1 drivers
+S_0x22a3d60 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x229d190;
+ .timescale -9 -12;
+L_0x2b27e40/d .functor NOT 1, L_0x2b28560, C4<0>, C4<0>, C4<0>;
+L_0x2b27e40 .delay (10000,10000,10000) L_0x2b27e40/d;
+L_0x2b28220/d .functor AND 1, L_0x2b28bf0, L_0x2b27e40, C4<1>, C4<1>;
+L_0x2b28220 .delay (20000,20000,20000) L_0x2b28220/d;
+L_0x2b282d0/d .functor AND 1, L_0x2b28ce0, L_0x2b28560, C4<1>, C4<1>;
+L_0x2b282d0 .delay (20000,20000,20000) L_0x2b282d0/d;
+L_0x2b28380/d .functor OR 1, L_0x2b28220, L_0x2b282d0, C4<0>, C4<0>;
+L_0x2b28380 .delay (20000,20000,20000) L_0x2b28380/d;
+v0x229f2b0_0 .net "S", 0 0, L_0x2b28560; 1 drivers
+v0x22a1ce0_0 .net "in0", 0 0, L_0x2b28bf0; 1 drivers
+v0x22a1d80_0 .net "in1", 0 0, L_0x2b28ce0; 1 drivers
+v0x22a88b0_0 .net "nS", 0 0, L_0x2b27e40; 1 drivers
+v0x22a8930_0 .net "out0", 0 0, L_0x2b28220; 1 drivers
+v0x22a6830_0 .net "out1", 0 0, L_0x2b282d0; 1 drivers
+v0x22a68b0_0 .net "outfinal", 0 0, L_0x2b28380; 1 drivers
+S_0x2287df0 .scope generate, "muxbits[8]" "muxbits[8]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x265f0e8 .param/l "i" 3 64, +C4<01000>;
+L_0x2b29750/d .functor OR 1, L_0x2b2bc00, L_0x2b21a10, C4<0>, C4<0>;
+L_0x2b29750 .delay (20000,20000,20000) L_0x2b29750/d;
+v0x22986f0_0 .net *"_s15", 0 0, L_0x2b2bc00; 1 drivers
+v0x229f210_0 .net *"_s16", 0 0, L_0x2b21a10; 1 drivers
+S_0x22977c0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2287df0;
+ .timescale -9 -12;
+L_0x2b28ae0/d .functor NOT 1, L_0x2b28dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b28ae0 .delay (10000,10000,10000) L_0x2b28ae0/d;
+L_0x2b29270/d .functor NOT 1, L_0x2b28f00, C4<0>, C4<0>, C4<0>;
+L_0x2b29270 .delay (10000,10000,10000) L_0x2b29270/d;
+L_0x2b29310/d .functor NAND 1, L_0x2b28ae0, L_0x2b29270, L_0x2b29030, C4<1>;
+L_0x2b29310 .delay (10000,10000,10000) L_0x2b29310/d;
+L_0x2b29450/d .functor NAND 1, L_0x2b28dd0, L_0x2b29270, L_0x2b1f870, C4<1>;
+L_0x2b29450 .delay (10000,10000,10000) L_0x2b29450/d;
+L_0x2b29570/d .functor NAND 1, L_0x2b28ae0, L_0x2b28f00, L_0x2b290d0, C4<1>;
+L_0x2b29570 .delay (10000,10000,10000) L_0x2b29570/d;
+L_0x2b296c0/d .functor NAND 1, L_0x2b28dd0, L_0x2b28f00, L_0x2b291c0, C4<1>;
+L_0x2b296c0 .delay (10000,10000,10000) L_0x2b296c0/d;
+L_0x2b29830/d .functor NAND 1, L_0x2b29310, L_0x2b29450, L_0x2b29570, L_0x2b296c0;
+L_0x2b29830 .delay (10000,10000,10000) L_0x2b29830/d;
+v0x2295a80_0 .net "S0", 0 0, L_0x2b28dd0; 1 drivers
+v0x22957f0_0 .net "S1", 0 0, L_0x2b28f00; 1 drivers
+v0x2295890_0 .net "in0", 0 0, L_0x2b29030; 1 drivers
+v0x2293ce0_0 .net "in1", 0 0, L_0x2b1f870; 1 drivers
+v0x2293d60_0 .net "in2", 0 0, L_0x2b290d0; 1 drivers
+v0x229c4f0_0 .net "in3", 0 0, L_0x2b291c0; 1 drivers
+v0x229c590_0 .net "nS0", 0 0, L_0x2b28ae0; 1 drivers
+v0x229c260_0 .net "nS1", 0 0, L_0x2b29270; 1 drivers
+v0x229c2e0_0 .net "out", 0 0, L_0x2b29830; 1 drivers
+v0x229a490_0 .net "out0", 0 0, L_0x2b29310; 1 drivers
+v0x229a530_0 .net "out1", 0 0, L_0x2b29450; 1 drivers
+v0x229a200_0 .net "out2", 0 0, L_0x2b29570; 1 drivers
+v0x229a280_0 .net "out3", 0 0, L_0x2b296c0; 1 drivers
+S_0x228c3d0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2287df0;
+ .timescale -9 -12;
+L_0x2b29ae0/d .functor NOT 1, L_0x2b2aa20, C4<0>, C4<0>, C4<0>;
+L_0x2b29ae0 .delay (10000,10000,10000) L_0x2b29ae0/d;
+L_0x2b29b90/d .functor NOT 1, L_0x2b2a1b0, C4<0>, C4<0>, C4<0>;
+L_0x2b29b90 .delay (10000,10000,10000) L_0x2b29b90/d;
+L_0x2b29bf0/d .functor NAND 1, L_0x2b29ae0, L_0x2b29b90, L_0x2b2a2e0, C4<1>;
+L_0x2b29bf0 .delay (10000,10000,10000) L_0x2b29bf0/d;
+L_0x2b29d30/d .functor NAND 1, L_0x2b2aa20, L_0x2b29b90, L_0x2b2a590, C4<1>;
+L_0x2b29d30 .delay (10000,10000,10000) L_0x2b29d30/d;
+L_0x2b29e20/d .functor NAND 1, L_0x2b29ae0, L_0x2b2a1b0, L_0x2b20a40, C4<1>;
+L_0x2b29e20 .delay (10000,10000,10000) L_0x2b29e20/d;
+L_0x2b29f10/d .functor NAND 1, L_0x2b2aa20, L_0x2b2a1b0, L_0x2b2b060, C4<1>;
+L_0x2b29f10 .delay (10000,10000,10000) L_0x2b29f10/d;
+L_0x2b2a770/d .functor NAND 1, L_0x2b29bf0, L_0x2b29d30, L_0x2b29e20, L_0x2b29f10;
+L_0x2b2a770 .delay (10000,10000,10000) L_0x2b2a770/d;
+v0x228a8c0_0 .net "S0", 0 0, L_0x2b2aa20; 1 drivers
+v0x2293040_0 .net "S1", 0 0, L_0x2b2a1b0; 1 drivers
+v0x22930e0_0 .net "in0", 0 0, L_0x2b2a2e0; 1 drivers
+v0x2292db0_0 .net "in1", 0 0, L_0x2b2a590; 1 drivers
+v0x2292e30_0 .net "in2", 0 0, L_0x2b20a40; 1 drivers
+v0x2291070_0 .net "in3", 0 0, L_0x2b2b060; 1 drivers
+v0x2291110_0 .net "nS0", 0 0, L_0x2b29ae0; 1 drivers
+v0x2290de0_0 .net "nS1", 0 0, L_0x2b29b90; 1 drivers
+v0x2290e60_0 .net "out", 0 0, L_0x2b2a770; 1 drivers
+v0x228f2d0_0 .net "out0", 0 0, L_0x2b29bf0; 1 drivers
+v0x228f370_0 .net "out1", 0 0, L_0x2b29d30; 1 drivers
+v0x2297a50_0 .net "out2", 0 0, L_0x2b29e20; 1 drivers
+v0x2297ad0_0 .net "out3", 0 0, L_0x2b29f10; 1 drivers
+S_0x2285d70 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2287df0;
+ .timescale -9 -12;
+L_0x2b2b100/d .functor NOT 1, L_0x2b21230, C4<0>, C4<0>, C4<0>;
+L_0x2b2b100 .delay (10000,10000,10000) L_0x2b2b100/d;
+L_0x2b2b1b0/d .functor AND 1, L_0x2b2ab50, L_0x2b2b100, C4<1>, C4<1>;
+L_0x2b2b1b0 .delay (20000,20000,20000) L_0x2b2b1b0/d;
+L_0x2b2b260/d .functor AND 1, L_0x2b215a0, L_0x2b21230, C4<1>, C4<1>;
+L_0x2b2b260 .delay (20000,20000,20000) L_0x2b2b260/d;
+L_0x2b2b310/d .functor OR 1, L_0x2b2b1b0, L_0x2b2b260, C4<0>, C4<0>;
+L_0x2b2b310 .delay (20000,20000,20000) L_0x2b2b310/d;
+v0x22812c0_0 .net "S", 0 0, L_0x2b21230; 1 drivers
+v0x228e630_0 .net "in0", 0 0, L_0x2b2ab50; 1 drivers
+v0x228e6d0_0 .net "in1", 0 0, L_0x2b215a0; 1 drivers
+v0x228e3a0_0 .net "nS", 0 0, L_0x2b2b100; 1 drivers
+v0x228e420_0 .net "out0", 0 0, L_0x2b2b1b0; 1 drivers
+v0x228c660_0 .net "out1", 0 0, L_0x2b2b260; 1 drivers
+v0x228c6e0_0 .net "outfinal", 0 0, L_0x2b2b310; 1 drivers
+S_0x226d8d0 .scope generate, "muxbits[9]" "muxbits[9]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26a1e88 .param/l "i" 3 64, +C4<01001>;
+L_0x2b2d870/d .functor OR 1, L_0x2b2d9b0, L_0x2b2da50, C4<0>, C4<0>;
+L_0x2b2d870 .delay (20000,20000,20000) L_0x2b2d870/d;
+v0x22832a0_0 .net *"_s15", 0 0, L_0x2b2d9b0; 1 drivers
+v0x2281220_0 .net *"_s16", 0 0, L_0x2b2da50; 1 drivers
+S_0x2273210 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x226d8d0;
+ .timescale -9 -12;
+L_0x2b2b6c0/d .functor NOT 1, L_0x2b2c7f0, C4<0>, C4<0>, C4<0>;
+L_0x2b2b6c0 .delay (10000,10000,10000) L_0x2b2b6c0/d;
+L_0x2b2b770/d .functor NOT 1, L_0x2b2beb0, C4<0>, C4<0>, C4<0>;
+L_0x2b2b770 .delay (10000,10000,10000) L_0x2b2b770/d;
+L_0x2b2b810/d .functor NAND 1, L_0x2b2b6c0, L_0x2b2b770, L_0x2b2bfe0, C4<1>;
+L_0x2b2b810 .delay (10000,10000,10000) L_0x2b2b810/d;
+L_0x2b2b950/d .functor NAND 1, L_0x2b2c7f0, L_0x2b2b770, L_0x2b2c080, C4<1>;
+L_0x2b2b950 .delay (10000,10000,10000) L_0x2b2b950/d;
+L_0x2b2ba70/d .functor NAND 1, L_0x2b2b6c0, L_0x2b2beb0, L_0x2b2c120, C4<1>;
+L_0x2b2ba70 .delay (10000,10000,10000) L_0x2b2ba70/d;
+L_0x2b2c400/d .functor NAND 1, L_0x2b2c7f0, L_0x2b2beb0, L_0x2b2c210, C4<1>;
+L_0x2b2c400 .delay (10000,10000,10000) L_0x2b2c400/d;
+L_0x2b2c540/d .functor NAND 1, L_0x2b2b810, L_0x2b2b950, L_0x2b2ba70, L_0x2b2c400;
+L_0x2b2c540 .delay (10000,10000,10000) L_0x2b2c540/d;
+v0x227ba30_0 .net "S0", 0 0, L_0x2b2c7f0; 1 drivers
+v0x227b7a0_0 .net "S1", 0 0, L_0x2b2beb0; 1 drivers
+v0x227b840_0 .net "in0", 0 0, L_0x2b2bfe0; 1 drivers
+v0x22799c0_0 .net "in1", 0 0, L_0x2b2c080; 1 drivers
+v0x2279a40_0 .net "in2", 0 0, L_0x2b2c120; 1 drivers
+v0x2279730_0 .net "in3", 0 0, L_0x2b2c210; 1 drivers
+v0x22797d0_0 .net "nS0", 0 0, L_0x2b2b6c0; 1 drivers
+v0x2277c20_0 .net "nS1", 0 0, L_0x2b2b770; 1 drivers
+v0x2277ca0_0 .net "out", 0 0, L_0x2b2c540; 1 drivers
+v0x227e750_0 .net "out0", 0 0, L_0x2b2b810; 1 drivers
+v0x227e7f0_0 .net "out1", 0 0, L_0x2b2b950; 1 drivers
+v0x227c6d0_0 .net "out2", 0 0, L_0x2b2ba70; 1 drivers
+v0x227c750_0 .net "out3", 0 0, L_0x2b2c400; 1 drivers
+S_0x22722e0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x226d8d0;
+ .timescale -9 -12;
+L_0x2b2c300/d .functor NOT 1, L_0x2b2c920, C4<0>, C4<0>, C4<0>;
+L_0x2b2c300 .delay (10000,10000,10000) L_0x2b2c300/d;
+L_0x2b2cea0/d .functor NOT 1, L_0x2b2ca50, C4<0>, C4<0>, C4<0>;
+L_0x2b2cea0 .delay (10000,10000,10000) L_0x2b2cea0/d;
+L_0x2b2cf00/d .functor NAND 1, L_0x2b2c300, L_0x2b2cea0, L_0x2b2cb80, C4<1>;
+L_0x2b2cf00 .delay (10000,10000,10000) L_0x2b2cf00/d;
+L_0x2b2cff0/d .functor NAND 1, L_0x2b2c920, L_0x2b2cea0, L_0x2b2cc20, C4<1>;
+L_0x2b2cff0 .delay (10000,10000,10000) L_0x2b2cff0/d;
+L_0x2b2d0e0/d .functor NAND 1, L_0x2b2c300, L_0x2b2ca50, L_0x2b2ccc0, C4<1>;
+L_0x2b2d0e0 .delay (10000,10000,10000) L_0x2b2d0e0/d;
+L_0x2b2d1d0/d .functor NAND 1, L_0x2b2c920, L_0x2b2ca50, L_0x2b2cdb0, C4<1>;
+L_0x2b2d1d0 .delay (10000,10000,10000) L_0x2b2d1d0/d;
+L_0x2b2d340/d .functor NAND 1, L_0x2b2cf00, L_0x2b2cff0, L_0x2b2d0e0, L_0x2b2d1d0;
+L_0x2b2d340 .delay (10000,10000,10000) L_0x2b2d340/d;
+v0x22705a0_0 .net "S0", 0 0, L_0x2b2c920; 1 drivers
+v0x2270310_0 .net "S1", 0 0, L_0x2b2ca50; 1 drivers
+v0x22703b0_0 .net "in0", 0 0, L_0x2b2cb80; 1 drivers
+v0x226e800_0 .net "in1", 0 0, L_0x2b2cc20; 1 drivers
+v0x226e880_0 .net "in2", 0 0, L_0x2b2ccc0; 1 drivers
+v0x2276f80_0 .net "in3", 0 0, L_0x2b2cdb0; 1 drivers
+v0x2277020_0 .net "nS0", 0 0, L_0x2b2c300; 1 drivers
+v0x2276cf0_0 .net "nS1", 0 0, L_0x2b2cea0; 1 drivers
+v0x2276d70_0 .net "out", 0 0, L_0x2b2d340; 1 drivers
+v0x2274fb0_0 .net "out0", 0 0, L_0x2b2cf00; 1 drivers
+v0x2275050_0 .net "out1", 0 0, L_0x2b2cff0; 1 drivers
+v0x2274d20_0 .net "out2", 0 0, L_0x2b2d0e0; 1 drivers
+v0x2274da0_0 .net "out3", 0 0, L_0x2b2d1d0; 1 drivers
+S_0x226bb90 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x226d8d0;
+ .timescale -9 -12;
+L_0x2b2c460/d .functor NOT 1, L_0x2b2df80, C4<0>, C4<0>, C4<0>;
+L_0x2b2c460 .delay (10000,10000,10000) L_0x2b2c460/d;
+L_0x2b2dc00/d .functor AND 1, L_0x2b2d5f0, L_0x2b2c460, C4<1>, C4<1>;
+L_0x2b2dc00 .delay (20000,20000,20000) L_0x2b2dc00/d;
+L_0x2b2dcb0/d .functor AND 1, L_0x2b2d6e0, L_0x2b2df80, C4<1>, C4<1>;
+L_0x2b2dcb0 .delay (20000,20000,20000) L_0x2b2dcb0/d;
+L_0x2b2dda0/d .functor OR 1, L_0x2b2dc00, L_0x2b2dcb0, C4<0>, C4<0>;
+L_0x2b2dda0 .delay (20000,20000,20000) L_0x2b2dda0/d;
+v0x226dc00_0 .net "S", 0 0, L_0x2b2df80; 1 drivers
+v0x226b900_0 .net "in0", 0 0, L_0x2b2d5f0; 1 drivers
+v0x226b9a0_0 .net "in1", 0 0, L_0x2b2d6e0; 1 drivers
+v0x2269df0_0 .net "nS", 0 0, L_0x2b2c460; 1 drivers
+v0x2269e70_0 .net "out0", 0 0, L_0x2b2dc00; 1 drivers
+v0x2272570_0 .net "out1", 0 0, L_0x2b2dcb0; 1 drivers
+v0x22725f0_0 .net "outfinal", 0 0, L_0x2b2dda0; 1 drivers
+S_0x22dadd0 .scope generate, "muxbits[10]" "muxbits[10]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26f2d68 .param/l "i" 3 64, +C4<01010>;
+L_0x2b30150/d .functor OR 1, L_0x2b30290, L_0x2b30330, C4<0>, C4<0>;
+L_0x2b30150 .delay (20000,20000,20000) L_0x2b30150/d;
+v0x22652a0_0 .net *"_s15", 0 0, L_0x2b30290; 1 drivers
+v0x226db60_0 .net *"_s16", 0 0, L_0x2b30330; 1 drivers
+S_0x225fab0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22dadd0;
+ .timescale -9 -12;
+L_0x2b2db40/d .functor NOT 1, L_0x2b2e020, C4<0>, C4<0>, C4<0>;
+L_0x2b2db40 .delay (10000,10000,10000) L_0x2b2db40/d;
+L_0x2b2e6a0/d .functor NOT 1, L_0x2b2e150, C4<0>, C4<0>, C4<0>;
+L_0x2b2e6a0 .delay (10000,10000,10000) L_0x2b2e6a0/d;
+L_0x2b2e740/d .functor NAND 1, L_0x2b2db40, L_0x2b2e6a0, L_0x2b2e280, C4<1>;
+L_0x2b2e740 .delay (10000,10000,10000) L_0x2b2e740/d;
+L_0x2b2e880/d .functor NAND 1, L_0x2b2e020, L_0x2b2e6a0, L_0x2b2e320, C4<1>;
+L_0x2b2e880 .delay (10000,10000,10000) L_0x2b2e880/d;
+L_0x2b2e970/d .functor NAND 1, L_0x2b2db40, L_0x2b2e150, L_0x2b2e3c0, C4<1>;
+L_0x2b2e970 .delay (10000,10000,10000) L_0x2b2e970/d;
+L_0x2b2eac0/d .functor NAND 1, L_0x2b2e020, L_0x2b2e150, L_0x2b2e4b0, C4<1>;
+L_0x2b2eac0 .delay (10000,10000,10000) L_0x2b2eac0/d;
+L_0x2b2ec30/d .functor NAND 1, L_0x2b2e740, L_0x2b2e880, L_0x2b2e970, L_0x2b2eac0;
+L_0x2b2ec30 .delay (10000,10000,10000) L_0x2b2ec30/d;
+v0x225f820_0 .net "S0", 0 0, L_0x2b2e020; 1 drivers
+v0x225d930_0 .net "S1", 0 0, L_0x2b2e150; 1 drivers
+v0x225d9d0_0 .net "in0", 0 0, L_0x2b2e280; 1 drivers
+v0x225d670_0 .net "in1", 0 0, L_0x2b2e320; 1 drivers
+v0x225d6f0_0 .net "in2", 0 0, L_0x2b2e3c0; 1 drivers
+v0x225ba30_0 .net "in3", 0 0, L_0x2b2e4b0; 1 drivers
+v0x225bad0_0 .net "nS0", 0 0, L_0x2b2db40; 1 drivers
+v0x22627d0_0 .net "nS1", 0 0, L_0x2b2e6a0; 1 drivers
+v0x2262850_0 .net "out", 0 0, L_0x2b2ec30; 1 drivers
+v0x2260750_0 .net "out0", 0 0, L_0x2b2e740; 1 drivers
+v0x22607f0_0 .net "out1", 0 0, L_0x2b2e880; 1 drivers
+v0x2267320_0 .net "out2", 0 0, L_0x2b2e970; 1 drivers
+v0x22673a0_0 .net "out3", 0 0, L_0x2b2eac0; 1 drivers
+S_0x22a7d20 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22dadd0;
+ .timescale -9 -12;
+L_0x2b2e5a0/d .functor NOT 1, L_0x2b2fd00, C4<0>, C4<0>, C4<0>;
+L_0x2b2e5a0 .delay (10000,10000,10000) L_0x2b2e5a0/d;
+L_0x2b2f560/d .functor NOT 1, L_0x2b2eee0, C4<0>, C4<0>, C4<0>;
+L_0x2b2f560 .delay (10000,10000,10000) L_0x2b2f560/d;
+L_0x2b2f5c0/d .functor NAND 1, L_0x2b2e5a0, L_0x2b2f560, L_0x2b2f010, C4<1>;
+L_0x2b2f5c0 .delay (10000,10000,10000) L_0x2b2f5c0/d;
+L_0x2b2f700/d .functor NAND 1, L_0x2b2fd00, L_0x2b2f560, L_0x2b2f0b0, C4<1>;
+L_0x2b2f700 .delay (10000,10000,10000) L_0x2b2f700/d;
+L_0x2b2f7f0/d .functor NAND 1, L_0x2b2e5a0, L_0x2b2eee0, L_0x2b2f150, C4<1>;
+L_0x2b2f7f0 .delay (10000,10000,10000) L_0x2b2f7f0/d;
+L_0x2b2f8e0/d .functor NAND 1, L_0x2b2fd00, L_0x2b2eee0, L_0x2b2f240, C4<1>;
+L_0x2b2f8e0 .delay (10000,10000,10000) L_0x2b2f8e0/d;
+L_0x2b2fa50/d .functor NAND 1, L_0x2b2f5c0, L_0x2b2f700, L_0x2b2f7f0, L_0x2b2f8e0;
+L_0x2b2fa50 .delay (10000,10000,10000) L_0x2b2fa50/d;
+v0x22a31d0_0 .net "S0", 0 0, L_0x2b2fd00; 1 drivers
+v0x229e680_0 .net "S1", 0 0, L_0x2b2eee0; 1 drivers
+v0x229e720_0 .net "in0", 0 0, L_0x2b2f010; 1 drivers
+v0x2261c40_0 .net "in1", 0 0, L_0x2b2f0b0; 1 drivers
+v0x2261cc0_0 .net "in2", 0 0, L_0x2b2f150; 1 drivers
+v0x2287260_0 .net "in3", 0 0, L_0x2b2f240; 1 drivers
+v0x2287300_0 .net "nS0", 0 0, L_0x2b2e5a0; 1 drivers
+v0x2282710_0 .net "nS1", 0 0, L_0x2b2f560; 1 drivers
+v0x2282790_0 .net "out", 0 0, L_0x2b2fa50; 1 drivers
+v0x227dbc0_0 .net "out0", 0 0, L_0x2b2f5c0; 1 drivers
+v0x227dc60_0 .net "out1", 0 0, L_0x2b2f700; 1 drivers
+v0x22ed4a0_0 .net "out2", 0 0, L_0x2b2f7f0; 1 drivers
+v0x22ed520_0 .net "out3", 0 0, L_0x2b2f8e0; 1 drivers
+S_0x22c87e0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22dadd0;
+ .timescale -9 -12;
+L_0x2b2eb50/d .functor NOT 1, L_0x2b2fe30, C4<0>, C4<0>, C4<0>;
+L_0x2b2eb50 .delay (10000,10000,10000) L_0x2b2eb50/d;
+L_0x2b2f380/d .functor AND 1, L_0x2b2fed0, L_0x2b2eb50, C4<1>, C4<1>;
+L_0x2b2f380 .delay (20000,20000,20000) L_0x2b2f380/d;
+L_0x2b2f430/d .functor AND 1, L_0x2b2ffc0, L_0x2b2fe30, C4<1>, C4<1>;
+L_0x2b2f430 .delay (20000,20000,20000) L_0x2b2f430/d;
+L_0x2b304e0/d .functor OR 1, L_0x2b2f380, L_0x2b2f430, C4<0>, C4<0>;
+L_0x2b304e0 .delay (20000,20000,20000) L_0x2b304e0/d;
+v0x22dfcc0_0 .net "S", 0 0, L_0x2b2fe30; 1 drivers
+v0x22c3c90_0 .net "in0", 0 0, L_0x2b2fed0; 1 drivers
+v0x22c3d30_0 .net "in1", 0 0, L_0x2b2ffc0; 1 drivers
+v0x2266790_0 .net "nS", 0 0, L_0x2b2eb50; 1 drivers
+v0x2266810_0 .net "out0", 0 0, L_0x2b2f380; 1 drivers
+v0x22bf140_0 .net "out1", 0 0, L_0x2b2f430; 1 drivers
+v0x22bf1c0_0 .net "outfinal", 0 0, L_0x2b304e0; 1 drivers
+S_0x2247660 .scope generate, "muxbits[11]" "muxbits[11]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x2723c38 .param/l "i" 3 64, +C4<01011>;
+L_0x2b32ac0/d .functor OR 1, L_0x2b32bc0, L_0x2b32c60, C4<0>, C4<0>;
+L_0x2b32ac0 .delay (20000,20000,20000) L_0x2b32ac0/d;
+v0x22e4770_0 .net *"_s15", 0 0, L_0x2b32bc0; 1 drivers
+v0x22dfc20_0 .net *"_s16", 0 0, L_0x2b32c60; 1 drivers
+S_0x22572a0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2247660;
+ .timescale -9 -12;
+L_0x2b30420/d .functor NOT 1, L_0x2b315f0, C4<0>, C4<0>, C4<0>;
+L_0x2b30420 .delay (10000,10000,10000) L_0x2b30420/d;
+L_0x2b30db0/d .functor NOT 1, L_0x2b30680, C4<0>, C4<0>, C4<0>;
+L_0x2b30db0 .delay (10000,10000,10000) L_0x2b30db0/d;
+L_0x2b30e50/d .functor NAND 1, L_0x2b30420, L_0x2b30db0, L_0x2b307b0, C4<1>;
+L_0x2b30e50 .delay (10000,10000,10000) L_0x2b30e50/d;
+L_0x2b30f90/d .functor NAND 1, L_0x2b315f0, L_0x2b30db0, L_0x2b30850, C4<1>;
+L_0x2b30f90 .delay (10000,10000,10000) L_0x2b30f90/d;
+L_0x2b31080/d .functor NAND 1, L_0x2b30420, L_0x2b30680, L_0x2b308f0, C4<1>;
+L_0x2b31080 .delay (10000,10000,10000) L_0x2b31080/d;
+L_0x2b311d0/d .functor NAND 1, L_0x2b315f0, L_0x2b30680, L_0x2b238f0, C4<1>;
+L_0x2b311d0 .delay (10000,10000,10000) L_0x2b311d0/d;
+L_0x2b31340/d .functor NAND 1, L_0x2b30e50, L_0x2b30f90, L_0x2b31080, L_0x2b311d0;
+L_0x2b31340 .delay (10000,10000,10000) L_0x2b31340/d;
+v0x2257010_0 .net "S0", 0 0, L_0x2b315f0; 1 drivers
+v0x2255500_0 .net "S1", 0 0, L_0x2b30680; 1 drivers
+v0x22555a0_0 .net "in0", 0 0, L_0x2b307b0; 1 drivers
+v0x22f2d30_0 .net "in1", 0 0, L_0x2b30850; 1 drivers
+v0x22f2db0_0 .net "in2", 0 0, L_0x2b308f0; 1 drivers
+v0x22ef470_0 .net "in3", 0 0, L_0x2b238f0; 1 drivers
+v0x22ef510_0 .net "nS0", 0 0, L_0x2b30420; 1 drivers
+v0x22ef220_0 .net "nS1", 0 0, L_0x2b30db0; 1 drivers
+v0x22ef2a0_0 .net "out", 0 0, L_0x2b31340; 1 drivers
+v0x22eefa0_0 .net "out0", 0 0, L_0x2b30e50; 1 drivers
+v0x22ef040_0 .net "out1", 0 0, L_0x2b30f90; 1 drivers
+v0x22e92c0_0 .net "out2", 0 0, L_0x2b31080; 1 drivers
+v0x22e9340_0 .net "out3", 0 0, L_0x2b311d0; 1 drivers
+S_0x224eaf0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2247660;
+ .timescale -9 -12;
+L_0x2b239e0/d .functor NOT 1, L_0x2b31b40, C4<0>, C4<0>, C4<0>;
+L_0x2b239e0 .delay (10000,10000,10000) L_0x2b239e0/d;
+L_0x2b23a90/d .functor NOT 1, L_0x2b31c70, C4<0>, C4<0>, C4<0>;
+L_0x2b23a90 .delay (10000,10000,10000) L_0x2b23a90/d;
+L_0x2b309e0/d .functor NAND 1, L_0x2b239e0, L_0x2b23a90, L_0x2b328e0, C4<1>;
+L_0x2b309e0 .delay (10000,10000,10000) L_0x2b309e0/d;
+L_0x2b30b20/d .functor NAND 1, L_0x2b31b40, L_0x2b23a90, L_0x2b32980, C4<1>;
+L_0x2b30b20 .delay (10000,10000,10000) L_0x2b30b20/d;
+L_0x2b30c10/d .functor NAND 1, L_0x2b239e0, L_0x2b31c70, L_0x2b321f0, C4<1>;
+L_0x2b30c10 .delay (10000,10000,10000) L_0x2b30c10/d;
+L_0x2b31720/d .functor NAND 1, L_0x2b31b40, L_0x2b31c70, L_0x2b322e0, C4<1>;
+L_0x2b31720 .delay (10000,10000,10000) L_0x2b31720/d;
+L_0x2b31890/d .functor NAND 1, L_0x2b309e0, L_0x2b30b20, L_0x2b30c10, L_0x2b31720;
+L_0x2b31890 .delay (10000,10000,10000) L_0x2b31890/d;
+v0x224cfe0_0 .net "S0", 0 0, L_0x2b31b40; 1 drivers
+v0x22519e0_0 .net "S1", 0 0, L_0x2b31c70; 1 drivers
+v0x2251a80_0 .net "in0", 0 0, L_0x2b328e0; 1 drivers
+v0x2251750_0 .net "in1", 0 0, L_0x2b32980; 1 drivers
+v0x22517d0_0 .net "in2", 0 0, L_0x2b321f0; 1 drivers
+v0x224fc40_0 .net "in3", 0 0, L_0x2b322e0; 1 drivers
+v0x224fce0_0 .net "nS0", 0 0, L_0x2b239e0; 1 drivers
+v0x2254640_0 .net "nS1", 0 0, L_0x2b23a90; 1 drivers
+v0x22546c0_0 .net "out", 0 0, L_0x2b31890; 1 drivers
+v0x22543b0_0 .net "out0", 0 0, L_0x2b309e0; 1 drivers
+v0x2254450_0 .net "out1", 0 0, L_0x2b30b20; 1 drivers
+v0x22528a0_0 .net "out2", 0 0, L_0x2b30c10; 1 drivers
+v0x2252920_0 .net "out3", 0 0, L_0x2b31720; 1 drivers
+S_0x224c120 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2247660;
+ .timescale -9 -12;
+L_0x2b31260/d .functor NOT 1, L_0x2b32760, C4<0>, C4<0>, C4<0>;
+L_0x2b31260 .delay (10000,10000,10000) L_0x2b31260/d;
+L_0x2b32420/d .functor AND 1, L_0x2b32800, L_0x2b31260, C4<1>, C4<1>;
+L_0x2b32420 .delay (20000,20000,20000) L_0x2b32420/d;
+L_0x2b324d0/d .functor AND 1, L_0x2b33190, L_0x2b32760, C4<1>, C4<1>;
+L_0x2b324d0 .delay (20000,20000,20000) L_0x2b324d0/d;
+L_0x2b32580/d .functor OR 1, L_0x2b32420, L_0x2b324d0, C4<0>, C4<0>;
+L_0x2b32580 .delay (20000,20000,20000) L_0x2b32580/d;
+v0x2249780_0 .net "S", 0 0, L_0x2b32760; 1 drivers
+v0x224be90_0 .net "in0", 0 0, L_0x2b32800; 1 drivers
+v0x224bf30_0 .net "in1", 0 0, L_0x2b33190; 1 drivers
+v0x224a380_0 .net "nS", 0 0, L_0x2b31260; 1 drivers
+v0x224a400_0 .net "out0", 0 0, L_0x2b32420; 1 drivers
+v0x224ed80_0 .net "out1", 0 0, L_0x2b324d0; 1 drivers
+v0x224ee00_0 .net "outfinal", 0 0, L_0x2b32580; 1 drivers
+S_0x22300a0 .scope generate, "muxbits[12]" "muxbits[12]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x2709cd8 .param/l "i" 3 64, +C4<01100>;
+L_0x2b35160/d .functor OR 1, L_0x2b352a0, L_0x2b35340, C4<0>, C4<0>;
+L_0x2b35160 .delay (20000,20000,20000) L_0x2b35160/d;
+v0x2244940_0 .net *"_s15", 0 0, L_0x2b352a0; 1 drivers
+v0x22496e0_0 .net *"_s16", 0 0, L_0x2b35340; 1 drivers
+S_0x22394c0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22300a0;
+ .timescale -9 -12;
+L_0x2b32d50/d .functor NOT 1, L_0x2b33280, C4<0>, C4<0>, C4<0>;
+L_0x2b32d50 .delay (10000,10000,10000) L_0x2b32d50/d;
+L_0x2b32e40/d .functor NOT 1, L_0x2b333b0, C4<0>, C4<0>, C4<0>;
+L_0x2b32e40 .delay (10000,10000,10000) L_0x2b32e40/d;
+L_0x2b32ee0/d .functor NAND 1, L_0x2b32d50, L_0x2b32e40, L_0x2b334e0, C4<1>;
+L_0x2b32ee0 .delay (10000,10000,10000) L_0x2b32ee0/d;
+L_0x2b33020/d .functor NAND 1, L_0x2b33280, L_0x2b32e40, L_0x2b33580, C4<1>;
+L_0x2b33020 .delay (10000,10000,10000) L_0x2b33020/d;
+L_0x2b339c0/d .functor NAND 1, L_0x2b32d50, L_0x2b333b0, L_0x2b33620, C4<1>;
+L_0x2b339c0 .delay (10000,10000,10000) L_0x2b339c0/d;
+L_0x2b33ae0/d .functor NAND 1, L_0x2b33280, L_0x2b333b0, L_0x2b33710, C4<1>;
+L_0x2b33ae0 .delay (10000,10000,10000) L_0x2b33ae0/d;
+L_0x2b33c50/d .functor NAND 1, L_0x2b32ee0, L_0x2b33020, L_0x2b339c0, L_0x2b33ae0;
+L_0x2b33c50 .delay (10000,10000,10000) L_0x2b33c50/d;
+v0x223e260_0 .net "S0", 0 0, L_0x2b33280; 1 drivers
+v0x223c1e0_0 .net "S1", 0 0, L_0x2b333b0; 1 drivers
+v0x223c280_0 .net "in0", 0 0, L_0x2b334e0; 1 drivers
+v0x2240f80_0 .net "in1", 0 0, L_0x2b33580; 1 drivers
+v0x2241000_0 .net "in2", 0 0, L_0x2b33620; 1 drivers
+v0x223ef00_0 .net "in3", 0 0, L_0x2b33710; 1 drivers
+v0x223efa0_0 .net "nS0", 0 0, L_0x2b32d50; 1 drivers
+v0x2243ca0_0 .net "nS1", 0 0, L_0x2b32e40; 1 drivers
+v0x2243d20_0 .net "out", 0 0, L_0x2b33c50; 1 drivers
+v0x2241c20_0 .net "out0", 0 0, L_0x2b32ee0; 1 drivers
+v0x2241cc0_0 .net "out1", 0 0, L_0x2b33020; 1 drivers
+v0x22469c0_0 .net "out2", 0 0, L_0x2b339c0; 1 drivers
+v0x2246a40_0 .net "out3", 0 0, L_0x2b33ae0; 1 drivers
+S_0x2230f60 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22300a0;
+ .timescale -9 -12;
+L_0x2b33800/d .functor NOT 1, L_0x2b34d10, C4<0>, C4<0>, C4<0>;
+L_0x2b33800 .delay (10000,10000,10000) L_0x2b33800/d;
+L_0x2b338b0/d .functor NOT 1, L_0x2b33f00, C4<0>, C4<0>, C4<0>;
+L_0x2b338b0 .delay (10000,10000,10000) L_0x2b338b0/d;
+L_0x2b33910/d .functor NAND 1, L_0x2b33800, L_0x2b338b0, L_0x2b34030, C4<1>;
+L_0x2b33910 .delay (10000,10000,10000) L_0x2b33910/d;
+L_0x2b34710/d .functor NAND 1, L_0x2b34d10, L_0x2b338b0, L_0x2b340d0, C4<1>;
+L_0x2b34710 .delay (10000,10000,10000) L_0x2b34710/d;
+L_0x2b34800/d .functor NAND 1, L_0x2b33800, L_0x2b33f00, L_0x2b34170, C4<1>;
+L_0x2b34800 .delay (10000,10000,10000) L_0x2b34800/d;
+L_0x2b348f0/d .functor NAND 1, L_0x2b34d10, L_0x2b33f00, L_0x2b34260, C4<1>;
+L_0x2b348f0 .delay (10000,10000,10000) L_0x2b348f0/d;
+L_0x2b34a60/d .functor NAND 1, L_0x2b33910, L_0x2b34710, L_0x2b34800, L_0x2b348f0;
+L_0x2b34a60 .delay (10000,10000,10000) L_0x2b34a60/d;
+v0x2235960_0 .net "S0", 0 0, L_0x2b34d10; 1 drivers
+v0x22356d0_0 .net "S1", 0 0, L_0x2b33f00; 1 drivers
+v0x2235770_0 .net "in0", 0 0, L_0x2b34030; 1 drivers
+v0x2233bc0_0 .net "in1", 0 0, L_0x2b340d0; 1 drivers
+v0x2233c40_0 .net "in2", 0 0, L_0x2b34170; 1 drivers
+v0x22385c0_0 .net "in3", 0 0, L_0x2b34260; 1 drivers
+v0x2238660_0 .net "nS0", 0 0, L_0x2b33800; 1 drivers
+v0x2238330_0 .net "nS1", 0 0, L_0x2b338b0; 1 drivers
+v0x22383b0_0 .net "out", 0 0, L_0x2b34a60; 1 drivers
+v0x2236820_0 .net "out0", 0 0, L_0x2b33910; 1 drivers
+v0x22368c0_0 .net "out1", 0 0, L_0x2b34710; 1 drivers
+v0x223b540_0 .net "out2", 0 0, L_0x2b34800; 1 drivers
+v0x223b5c0_0 .net "out3", 0 0, L_0x2b348f0; 1 drivers
+S_0x222fe10 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22300a0;
+ .timescale -9 -12;
+L_0x2b33b70/d .functor NOT 1, L_0x2b34e40, C4<0>, C4<0>, C4<0>;
+L_0x2b33b70 .delay (10000,10000,10000) L_0x2b33b70/d;
+L_0x2b343a0/d .functor AND 1, L_0x2b34ee0, L_0x2b33b70, C4<1>, C4<1>;
+L_0x2b343a0 .delay (20000,20000,20000) L_0x2b343a0/d;
+L_0x2b34470/d .functor AND 1, L_0x2b34fd0, L_0x2b34e40, C4<1>, C4<1>;
+L_0x2b34470 .delay (20000,20000,20000) L_0x2b34470/d;
+L_0x2b34560/d .functor OR 1, L_0x2b343a0, L_0x2b34470, C4<0>, C4<0>;
+L_0x2b34560 .delay (20000,20000,20000) L_0x2b34560/d;
+v0x222b740_0 .net "S", 0 0, L_0x2b34e40; 1 drivers
+v0x222e300_0 .net "in0", 0 0, L_0x2b34ee0; 1 drivers
+v0x222e3a0_0 .net "in1", 0 0, L_0x2b34fd0; 1 drivers
+v0x2232d00_0 .net "nS", 0 0, L_0x2b33b70; 1 drivers
+v0x2232d80_0 .net "out0", 0 0, L_0x2b343a0; 1 drivers
+v0x2232a70_0 .net "out1", 0 0, L_0x2b34470; 1 drivers
+v0x2232af0_0 .net "outfinal", 0 0, L_0x2b34560; 1 drivers
+S_0x22122c0 .scope generate, "muxbits[13]" "muxbits[13]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26e3268 .param/l "i" 3 64, +C4<01101>;
+L_0x2b37720/d .functor OR 1, L_0x2b37860, L_0x2b37900, C4<0>, C4<0>;
+L_0x2b37720 .delay (20000,20000,20000) L_0x2b37720/d;
+v0x222d250_0 .net *"_s15", 0 0, L_0x2b37860; 1 drivers
+v0x222b6a0_0 .net *"_s16", 0 0, L_0x2b37900; 1 drivers
+S_0x2223000 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22122c0;
+ .timescale -9 -12;
+L_0x2b35430/d .functor NOT 1, L_0x2b36640, C4<0>, C4<0>, C4<0>;
+L_0x2b35430 .delay (10000,10000,10000) L_0x2b35430/d;
+L_0x2b35520/d .functor NOT 1, L_0x2b356e0, C4<0>, C4<0>, C4<0>;
+L_0x2b35520 .delay (10000,10000,10000) L_0x2b35520/d;
+L_0x2b35ed0/d .functor NAND 1, L_0x2b35430, L_0x2b35520, L_0x2b35810, C4<1>;
+L_0x2b35ed0 .delay (10000,10000,10000) L_0x2b35ed0/d;
+L_0x2b36010/d .functor NAND 1, L_0x2b36640, L_0x2b35520, L_0x2b358b0, C4<1>;
+L_0x2b36010 .delay (10000,10000,10000) L_0x2b36010/d;
+L_0x2b36100/d .functor NAND 1, L_0x2b35430, L_0x2b356e0, L_0x2b35950, C4<1>;
+L_0x2b36100 .delay (10000,10000,10000) L_0x2b36100/d;
+L_0x2b36220/d .functor NAND 1, L_0x2b36640, L_0x2b356e0, L_0x2b35a40, C4<1>;
+L_0x2b36220 .delay (10000,10000,10000) L_0x2b36220/d;
+L_0x2b36390/d .functor NAND 1, L_0x2b35ed0, L_0x2b36010, L_0x2b36100, L_0x2b36220;
+L_0x2b36390 .delay (10000,10000,10000) L_0x2b36390/d;
+v0x2227da0_0 .net "S0", 0 0, L_0x2b36640; 1 drivers
+v0x2227e40_0 .net "S1", 0 0, L_0x2b356e0; 1 drivers
+v0x2225d20_0 .net "in0", 0 0, L_0x2b35810; 1 drivers
+v0x2225dc0_0 .net "in1", 0 0, L_0x2b358b0; 1 drivers
+v0x222a7e0_0 .net "in2", 0 0, L_0x2b35950; 1 drivers
+v0x222a880_0 .net "in3", 0 0, L_0x2b35a40; 1 drivers
+v0x222a550_0 .net "nS0", 0 0, L_0x2b35430; 1 drivers
+v0x222a5d0_0 .net "nS1", 0 0, L_0x2b35520; 1 drivers
+v0x2228a40_0 .net "out", 0 0, L_0x2b36390; 1 drivers
+v0x2228ae0_0 .net "out0", 0 0, L_0x2b35ed0; 1 drivers
+v0x222d440_0 .net "out1", 0 0, L_0x2b36010; 1 drivers
+v0x222d4c0_0 .net "out2", 0 0, L_0x2b36100; 1 drivers
+v0x222d1b0_0 .net "out3", 0 0, L_0x2b36220; 1 drivers
+S_0x221c920 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22122c0;
+ .timescale -9 -12;
+L_0x2b35b30/d .functor NOT 1, L_0x2b36770, C4<0>, C4<0>, C4<0>;
+L_0x2b35b30 .delay (10000,10000,10000) L_0x2b35b30/d;
+L_0x2b35be0/d .functor NOT 1, L_0x2b368a0, C4<0>, C4<0>, C4<0>;
+L_0x2b35be0 .delay (10000,10000,10000) L_0x2b35be0/d;
+L_0x2b35c80/d .functor NAND 1, L_0x2b35b30, L_0x2b35be0, L_0x2b369d0, C4<1>;
+L_0x2b35c80 .delay (10000,10000,10000) L_0x2b35c80/d;
+L_0x2b35dc0/d .functor NAND 1, L_0x2b36770, L_0x2b35be0, L_0x2b36a70, C4<1>;
+L_0x2b35dc0 .delay (10000,10000,10000) L_0x2b35dc0/d;
+L_0x2b36f90/d .functor NAND 1, L_0x2b35b30, L_0x2b368a0, L_0x2b36b10, C4<1>;
+L_0x2b36f90 .delay (10000,10000,10000) L_0x2b36f90/d;
+L_0x2b37080/d .functor NAND 1, L_0x2b36770, L_0x2b368a0, L_0x2b36c00, C4<1>;
+L_0x2b37080 .delay (10000,10000,10000) L_0x2b37080/d;
+L_0x2b371f0/d .functor NAND 1, L_0x2b35c80, L_0x2b35dc0, L_0x2b36f90, L_0x2b37080;
+L_0x2b371f0 .delay (10000,10000,10000) L_0x2b371f0/d;
+v0x2217c00_0 .net "S0", 0 0, L_0x2b36770; 1 drivers
+v0x221a8a0_0 .net "S1", 0 0, L_0x2b368a0; 1 drivers
+v0x221a940_0 .net "in0", 0 0, L_0x2b369d0; 1 drivers
+v0x221f640_0 .net "in1", 0 0, L_0x2b36a70; 1 drivers
+v0x221f6c0_0 .net "in2", 0 0, L_0x2b36b10; 1 drivers
+v0x221d5c0_0 .net "in3", 0 0, L_0x2b36c00; 1 drivers
+v0x221d640_0 .net "nS0", 0 0, L_0x2b35b30; 1 drivers
+v0x2222360_0 .net "nS1", 0 0, L_0x2b35be0; 1 drivers
+v0x2222400_0 .net "out", 0 0, L_0x2b371f0; 1 drivers
+v0x22202e0_0 .net "out0", 0 0, L_0x2b35c80; 1 drivers
+v0x2220360_0 .net "out1", 0 0, L_0x2b35dc0; 1 drivers
+v0x2225080_0 .net "out2", 0 0, L_0x2b36f90; 1 drivers
+v0x2225120_0 .net "out3", 0 0, L_0x2b37080; 1 drivers
+S_0x2216cc0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22122c0;
+ .timescale -9 -12;
+L_0x2b36cf0/d .functor NOT 1, L_0x2b37f30, C4<0>, C4<0>, C4<0>;
+L_0x2b36cf0 .delay (10000,10000,10000) L_0x2b36cf0/d;
+L_0x2b36de0/d .functor AND 1, L_0x2b374a0, L_0x2b36cf0, C4<1>, C4<1>;
+L_0x2b36de0 .delay (20000,20000,20000) L_0x2b36de0/d;
+L_0x2b36ed0/d .functor AND 1, L_0x2b37590, L_0x2b37f30, C4<1>, C4<1>;
+L_0x2b36ed0 .delay (20000,20000,20000) L_0x2b36ed0/d;
+L_0x2b37d50/d .functor OR 1, L_0x2b36de0, L_0x2b36ed0, C4<0>, C4<0>;
+L_0x2b37d50 .delay (20000,20000,20000) L_0x2b37d50/d;
+v0x2216a30_0 .net "S", 0 0, L_0x2b37f30; 1 drivers
+v0x2216ad0_0 .net "in0", 0 0, L_0x2b374a0; 1 drivers
+v0x2214f20_0 .net "in1", 0 0, L_0x2b37590; 1 drivers
+v0x2214fc0_0 .net "nS", 0 0, L_0x2b36cf0; 1 drivers
+v0x2219c00_0 .net "out0", 0 0, L_0x2b36de0; 1 drivers
+v0x2219ca0_0 .net "out1", 0 0, L_0x2b36ed0; 1 drivers
+v0x2217b80_0 .net "outfinal", 0 0, L_0x2b37d50; 1 drivers
+S_0x2211170 .scope generate, "muxbits[14]" "muxbits[14]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x26ff358 .param/l "i" 3 64, +C4<01110>;
+L_0x2b3a0d0/d .functor OR 1, L_0x2b3a210, L_0x2b3a2b0, C4<0>, C4<0>;
+L_0x2b3a0d0 .delay (20000,20000,20000) L_0x2b3a0d0/d;
+v0x2213760_0 .net *"_s15", 0 0, L_0x2b3a210; 1 drivers
+v0x22163c0_0 .net *"_s16", 0 0, L_0x2b3a2b0; 1 drivers
+S_0x2213dd0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2211170;
+ .timescale -9 -12;
+L_0x2b379f0/d .functor NOT 1, L_0x2b37fd0, C4<0>, C4<0>, C4<0>;
+L_0x2b379f0 .delay (10000,10000,10000) L_0x2b379f0/d;
+L_0x2b37ae0/d .functor NOT 1, L_0x2b38100, C4<0>, C4<0>, C4<0>;
+L_0x2b37ae0 .delay (10000,10000,10000) L_0x2b37ae0/d;
+L_0x2b37b80/d .functor NAND 1, L_0x2b379f0, L_0x2b37ae0, L_0x2b38230, C4<1>;
+L_0x2b37b80 .delay (10000,10000,10000) L_0x2b37b80/d;
+L_0x2b38860/d .functor NAND 1, L_0x2b37fd0, L_0x2b37ae0, L_0x2b382d0, C4<1>;
+L_0x2b38860 .delay (10000,10000,10000) L_0x2b38860/d;
+L_0x2b38910/d .functor NAND 1, L_0x2b379f0, L_0x2b38100, L_0x2b38370, C4<1>;
+L_0x2b38910 .delay (10000,10000,10000) L_0x2b38910/d;
+L_0x2b38a00/d .functor NAND 1, L_0x2b37fd0, L_0x2b38100, L_0x2b38460, C4<1>;
+L_0x2b38a00 .delay (10000,10000,10000) L_0x2b38a00/d;
+L_0x2b38b40/d .functor NAND 1, L_0x2b37b80, L_0x2b38860, L_0x2b38910, L_0x2b38a00;
+L_0x2b38b40 .delay (10000,10000,10000) L_0x2b38b40/d;
+v0x2232400_0 .net "S0", 0 0, L_0x2b37fd0; 1 drivers
+v0x2235060_0 .net "S1", 0 0, L_0x2b38100; 1 drivers
+v0x2237cc0_0 .net "in0", 0 0, L_0x2b38230; 1 drivers
+v0x22085e0_0 .net "in1", 0 0, L_0x2b382d0; 1 drivers
+v0x224b820_0 .net "in2", 0 0, L_0x2b38370; 1 drivers
+v0x224e480_0 .net "in3", 0 0, L_0x2b38460; 1 drivers
+v0x22510e0_0 .net "nS0", 0 0, L_0x2b379f0; 1 drivers
+v0x2253d40_0 .net "nS1", 0 0, L_0x2b37ae0; 1 drivers
+v0x22569a0_0 .net "out", 0 0, L_0x2b38b40; 1 drivers
+v0x2259600_0 .net "out0", 0 0, L_0x2b37b80; 1 drivers
+v0x220b240_0 .net "out1", 0 0, L_0x2b38860; 1 drivers
+v0x220dea0_0 .net "out2", 0 0, L_0x2b38910; 1 drivers
+v0x2210b00_0 .net "out3", 0 0, L_0x2b38a00; 1 drivers
+S_0x2214060 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2211170;
+ .timescale -9 -12;
+L_0x2b38550/d .functor NOT 1, L_0x2b39c80, C4<0>, C4<0>, C4<0>;
+L_0x2b38550 .delay (10000,10000,10000) L_0x2b38550/d;
+L_0x2b38640/d .functor NOT 1, L_0x2b38df0, C4<0>, C4<0>, C4<0>;
+L_0x2b38640 .delay (10000,10000,10000) L_0x2b38640/d;
+L_0x2b386e0/d .functor NAND 1, L_0x2b38550, L_0x2b38640, L_0x2b38f20, C4<1>;
+L_0x2b386e0 .delay (10000,10000,10000) L_0x2b386e0/d;
+L_0x2b396c0/d .functor NAND 1, L_0x2b39c80, L_0x2b38640, L_0x2b38fc0, C4<1>;
+L_0x2b396c0 .delay (10000,10000,10000) L_0x2b396c0/d;
+L_0x2b39770/d .functor NAND 1, L_0x2b38550, L_0x2b38df0, L_0x2b39060, C4<1>;
+L_0x2b39770 .delay (10000,10000,10000) L_0x2b39770/d;
+L_0x2b39860/d .functor NAND 1, L_0x2b39c80, L_0x2b38df0, L_0x2b39150, C4<1>;
+L_0x2b39860 .delay (10000,10000,10000) L_0x2b39860/d;
+L_0x2b399d0/d .functor NAND 1, L_0x2b386e0, L_0x2b396c0, L_0x2b39770, L_0x2b39860;
+L_0x2b399d0 .delay (10000,10000,10000) L_0x2b399d0/d;
+v0x2219770_0 .net "S0", 0 0, L_0x2b39c80; 1 drivers
+v0x22199f0_0 .net "S1", 0 0, L_0x2b38df0; 1 drivers
+v0x2216fe0_0 .net "in0", 0 0, L_0x2b38f20; 1 drivers
+v0x2214380_0 .net "in1", 0 0, L_0x2b38fc0; 1 drivers
+v0x2211720_0 .net "in2", 0 0, L_0x2b39060; 1 drivers
+v0x220eac0_0 .net "in3", 0 0, L_0x2b39150; 1 drivers
+v0x220be60_0 .net "nS0", 0 0, L_0x2b38550; 1 drivers
+v0x2209200_0 .net "nS1", 0 0, L_0x2b38640; 1 drivers
+v0x2205fc0_0 .net "out", 0 0, L_0x2b399d0; 1 drivers
+v0x2206240_0 .net "out0", 0 0, L_0x2b386e0; 1 drivers
+v0x2229ee0_0 .net "out1", 0 0, L_0x2b396c0; 1 drivers
+v0x222cb40_0 .net "out2", 0 0, L_0x2b39770; 1 drivers
+v0x222f7a0_0 .net "out3", 0 0, L_0x2b39860; 1 drivers
+S_0x220f660 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2211170;
+ .timescale -9 -12;
+L_0x2b39240/d .functor NOT 1, L_0x2b39db0, C4<0>, C4<0>, C4<0>;
+L_0x2b39240 .delay (10000,10000,10000) L_0x2b39240/d;
+L_0x2b39330/d .functor AND 1, L_0x2b39e50, L_0x2b39240, C4<1>, C4<1>;
+L_0x2b39330 .delay (20000,20000,20000) L_0x2b39330/d;
+L_0x2b39420/d .functor AND 1, L_0x2b39f40, L_0x2b39db0, C4<1>, C4<1>;
+L_0x2b39420 .delay (20000,20000,20000) L_0x2b39420/d;
+L_0x2b39510/d .functor OR 1, L_0x2b39330, L_0x2b39420, C4<0>, C4<0>;
+L_0x2b39510 .delay (20000,20000,20000) L_0x2b39510/d;
+v0x2224e70_0 .net "S", 0 0, L_0x2b39db0; 1 drivers
+v0x2221ed0_0 .net "in0", 0 0, L_0x2b39e50; 1 drivers
+v0x2222150_0 .net "in1", 0 0, L_0x2b39f40; 1 drivers
+v0x221f1b0_0 .net "nS", 0 0, L_0x2b39240; 1 drivers
+v0x221f430_0 .net "out0", 0 0, L_0x2b39330; 1 drivers
+v0x221c490_0 .net "out1", 0 0, L_0x2b39420; 1 drivers
+v0x221c710_0 .net "outfinal", 0 0, L_0x2b39510; 1 drivers
+S_0x220e7a0 .scope generate, "muxbits[15]" "muxbits[15]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x271be98 .param/l "i" 3 64, +C4<01111>;
+L_0x2b3c7e0/d .functor OR 1, L_0x2b3c920, L_0x2b3c9c0, C4<0>, C4<0>;
+L_0x2b3c7e0 .delay (20000,20000,20000) L_0x2b3c7e0/d;
+v0x2227b90_0 .net *"_s15", 0 0, L_0x2b3c920; 1 drivers
+v0x2224bf0_0 .net *"_s16", 0 0, L_0x2b3c9c0; 1 drivers
+S_0x2211400 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x220e7a0;
+ .timescale -9 -12;
+L_0x2b3a3a0/d .functor NOT 1, L_0x2b3b5c0, C4<0>, C4<0>, C4<0>;
+L_0x2b3a3a0 .delay (10000,10000,10000) L_0x2b3a3a0/d;
+L_0x2b3a490/d .functor NOT 1, L_0x2b3a750, C4<0>, C4<0>, C4<0>;
+L_0x2b3a490 .delay (10000,10000,10000) L_0x2b3a490/d;
+L_0x2b3a530/d .functor NAND 1, L_0x2b3a3a0, L_0x2b3a490, L_0x2b3a880, C4<1>;
+L_0x2b3a530 .delay (10000,10000,10000) L_0x2b3a530/d;
+L_0x2b39650/d .functor NAND 1, L_0x2b3b5c0, L_0x2b3a490, L_0x2b3a920, C4<1>;
+L_0x2b39650 .delay (10000,10000,10000) L_0x2b39650/d;
+L_0x2b3b0e0/d .functor NAND 1, L_0x2b3a3a0, L_0x2b3a750, L_0x2b3a9c0, C4<1>;
+L_0x2b3b0e0 .delay (10000,10000,10000) L_0x2b3b0e0/d;
+L_0x2b3b1d0/d .functor NAND 1, L_0x2b3b5c0, L_0x2b3a750, L_0x2b3aab0, C4<1>;
+L_0x2b3b1d0 .delay (10000,10000,10000) L_0x2b3b1d0/d;
+L_0x2b3b310/d .functor NAND 1, L_0x2b3a530, L_0x2b39650, L_0x2b3b0e0, L_0x2b3b1d0;
+L_0x2b3b310 .delay (10000,10000,10000) L_0x2b3b310/d;
+v0x2240af0_0 .net "S0", 0 0, L_0x2b3b5c0; 1 drivers
+v0x2240d70_0 .net "S1", 0 0, L_0x2b3a750; 1 drivers
+v0x223ddd0_0 .net "in0", 0 0, L_0x2b3a880; 1 drivers
+v0x223e050_0 .net "in1", 0 0, L_0x2b3a920; 1 drivers
+v0x223b0b0_0 .net "in2", 0 0, L_0x2b3a9c0; 1 drivers
+v0x223b330_0 .net "in3", 0 0, L_0x2b3aab0; 1 drivers
+v0x22388e0_0 .net "nS0", 0 0, L_0x2b3a3a0; 1 drivers
+v0x2235c80_0 .net "nS1", 0 0, L_0x2b3a490; 1 drivers
+v0x2233020_0 .net "out", 0 0, L_0x2b3b310; 1 drivers
+v0x22303c0_0 .net "out0", 0 0, L_0x2b3a530; 1 drivers
+v0x222d760_0 .net "out1", 0 0, L_0x2b39650; 1 drivers
+v0x222ab00_0 .net "out2", 0 0, L_0x2b3b0e0; 1 drivers
+v0x2227910_0 .net "out3", 0 0, L_0x2b3b1d0; 1 drivers
+S_0x220ca00 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x220e7a0;
+ .timescale -9 -12;
+L_0x2b27900/d .functor NOT 1, L_0x2b3b6f0, C4<0>, C4<0>, C4<0>;
+L_0x2b27900 .delay (10000,10000,10000) L_0x2b27900/d;
+L_0x2b3adb0/d .functor NOT 1, L_0x2b3b820, C4<0>, C4<0>, C4<0>;
+L_0x2b3adb0 .delay (10000,10000,10000) L_0x2b3adb0/d;
+L_0x2b3ae50/d .functor NAND 1, L_0x2b27900, L_0x2b3adb0, L_0x2b3b950, C4<1>;
+L_0x2b3ae50 .delay (10000,10000,10000) L_0x2b3ae50/d;
+L_0x2b3af90/d .functor NAND 1, L_0x2b3b6f0, L_0x2b3adb0, L_0x2b3b9f0, C4<1>;
+L_0x2b3af90 .delay (10000,10000,10000) L_0x2b3af90/d;
+L_0x2b3b030/d .functor NAND 1, L_0x2b27900, L_0x2b3b820, L_0x2b3ba90, C4<1>;
+L_0x2b3b030 .delay (10000,10000,10000) L_0x2b3b030/d;
+L_0x2b3c140/d .functor NAND 1, L_0x2b3b6f0, L_0x2b3b820, L_0x2b3bb80, C4<1>;
+L_0x2b3c140 .delay (10000,10000,10000) L_0x2b3c140/d;
+L_0x2b3c2b0/d .functor NAND 1, L_0x2b3ae50, L_0x2b3af90, L_0x2b3b030, L_0x2b3c140;
+L_0x2b3c2b0 .delay (10000,10000,10000) L_0x2b3c2b0/d;
+v0x225e480_0 .net "S0", 0 0, L_0x2b3b6f0; 1 drivers
+v0x22790c0_0 .net "S1", 0 0, L_0x2b3b820; 1 drivers
+v0x22575c0_0 .net "in0", 0 0, L_0x2b3b950; 1 drivers
+v0x2254960_0 .net "in1", 0 0, L_0x2b3b9f0; 1 drivers
+v0x2251d00_0 .net "in2", 0 0, L_0x2b3ba90; 1 drivers
+v0x224f0a0_0 .net "in3", 0 0, L_0x2b3bb80; 1 drivers
+v0x224c440_0 .net "nS0", 0 0, L_0x2b27900; 1 drivers
+v0x2249250_0 .net "nS1", 0 0, L_0x2b3adb0; 1 drivers
+v0x22494d0_0 .net "out", 0 0, L_0x2b3c2b0; 1 drivers
+v0x2246530_0 .net "out0", 0 0, L_0x2b3ae50; 1 drivers
+v0x22467b0_0 .net "out1", 0 0, L_0x2b3af90; 1 drivers
+v0x2243810_0 .net "out2", 0 0, L_0x2b3b030; 1 drivers
+v0x2243a90_0 .net "out3", 0 0, L_0x2b3c140; 1 drivers
+S_0x220e510 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x220e7a0;
+ .timescale -9 -12;
+L_0x2b3bc70/d .functor NOT 1, L_0x2b3d000, C4<0>, C4<0>, C4<0>;
+L_0x2b3bc70 .delay (10000,10000,10000) L_0x2b3bc70/d;
+L_0x2b3bd60/d .functor AND 1, L_0x2b3c560, L_0x2b3bc70, C4<1>, C4<1>;
+L_0x2b3bd60 .delay (20000,20000,20000) L_0x2b3bd60/d;
+L_0x2b3be50/d .functor AND 1, L_0x2b3c650, L_0x2b3d000, C4<1>, C4<1>;
+L_0x2b3be50 .delay (20000,20000,20000) L_0x2b3be50/d;
+L_0x2b3bf40/d .functor OR 1, L_0x2b3bd60, L_0x2b3be50, C4<0>, C4<0>;
+L_0x2b3bf40 .delay (20000,20000,20000) L_0x2b3bf40/d;
+v0x22ee940_0 .net "S", 0 0, L_0x2b3d000; 1 drivers
+v0x22f28a0_0 .net "in0", 0 0, L_0x2b3c560; 1 drivers
+v0x226c6d0_0 .net "in1", 0 0, L_0x2b3c650; 1 drivers
+v0x226fca0_0 .net "nS", 0 0, L_0x2b3bc70; 1 drivers
+v0x22710e0_0 .net "out0", 0 0, L_0x2b3bd60; 1 drivers
+v0x22746b0_0 .net "out1", 0 0, L_0x2b3be50; 1 drivers
+v0x2275af0_0 .net "outfinal", 0 0, L_0x2b3bf40; 1 drivers
+S_0x22070f0 .scope generate, "muxbits[16]" "muxbits[16]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x275af38 .param/l "i" 3 64, +C4<010000>;
+L_0x2b2add0/d .functor OR 1, L_0x2b2af10, L_0x2b2afb0, C4<0>, C4<0>;
+L_0x2b2add0 .delay (20000,20000,20000) L_0x2b2add0/d;
+v0x22eb5f0_0 .net *"_s15", 0 0, L_0x2b2af10; 1 drivers
+v0x226b290_0 .net *"_s16", 0 0, L_0x2b2afb0; 1 drivers
+S_0x2209da0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22070f0;
+ .timescale -9 -12;
+L_0x2b3cab0/d .functor NOT 1, L_0x2b3d0a0, C4<0>, C4<0>, C4<0>;
+L_0x2b3cab0 .delay (10000,10000,10000) L_0x2b3cab0/d;
+L_0x2b3cba0/d .functor NOT 1, L_0x2b3d1d0, C4<0>, C4<0>, C4<0>;
+L_0x2b3cba0 .delay (10000,10000,10000) L_0x2b3cba0/d;
+L_0x2b3cc40/d .functor NAND 1, L_0x2b3cab0, L_0x2b3cba0, L_0x2b3d300, C4<1>;
+L_0x2b3cc40 .delay (10000,10000,10000) L_0x2b3cc40/d;
+L_0x2b3cd80/d .functor NAND 1, L_0x2b3d0a0, L_0x2b3cba0, L_0x2b29fa0, C4<1>;
+L_0x2b3cd80 .delay (10000,10000,10000) L_0x2b3cd80/d;
+L_0x2b3ce70/d .functor NAND 1, L_0x2b3cab0, L_0x2b3d1d0, L_0x2b2a040, C4<1>;
+L_0x2b3ce70 .delay (10000,10000,10000) L_0x2b3ce70/d;
+L_0x2b3dad0/d .functor NAND 1, L_0x2b3d0a0, L_0x2b3d1d0, L_0x2b3d7b0, C4<1>;
+L_0x2b3dad0 .delay (10000,10000,10000) L_0x2b3dad0/d;
+L_0x2b3dbe0/d .functor NAND 1, L_0x2b3cc40, L_0x2b3cd80, L_0x2b3ce70, L_0x2b3dad0;
+L_0x2b3dbe0 .delay (10000,10000,10000) L_0x2b3dbe0/d;
+v0x22d3130_0 .net "S0", 0 0, L_0x2b3d0a0; 1 drivers
+v0x2267bf0_0 .net "S1", 0 0, L_0x2b3d1d0; 1 drivers
+v0x22d6700_0 .net "in0", 0 0, L_0x2b3d300; 1 drivers
+v0x22d7b40_0 .net "in1", 0 0, L_0x2b29fa0; 1 drivers
+v0x22db110_0 .net "in2", 0 0, L_0x2b2a040; 1 drivers
+v0x2268ac0_0 .net "in3", 0 0, L_0x2b3d7b0; 1 drivers
+v0x22dc530_0 .net "nS0", 0 0, L_0x2b3cab0; 1 drivers
+v0x22dd400_0 .net "nS1", 0 0, L_0x2b3cba0; 1 drivers
+v0x22e1080_0 .net "out", 0 0, L_0x2b3dbe0; 1 drivers
+v0x22e1f50_0 .net "out0", 0 0, L_0x2b3cc40; 1 drivers
+v0x22e5bd0_0 .net "out1", 0 0, L_0x2b3cd80; 1 drivers
+v0x22e6aa0_0 .net "out2", 0 0, L_0x2b3ce70; 1 drivers
+v0x22ea720_0 .net "out3", 0 0, L_0x2b3dad0; 1 drivers
+S_0x220b8b0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22070f0;
+ .timescale -9 -12;
+L_0x2b3d8a0/d .functor NOT 1, L_0x2b3ef40, C4<0>, C4<0>, C4<0>;
+L_0x2b3d8a0 .delay (10000,10000,10000) L_0x2b3d8a0/d;
+L_0x2b3d990/d .functor NOT 1, L_0x2b3de90, C4<0>, C4<0>, C4<0>;
+L_0x2b3d990 .delay (10000,10000,10000) L_0x2b3d990/d;
+L_0x2b2a130/d .functor NAND 1, L_0x2b3d8a0, L_0x2b3d990, L_0x2b3dfc0, C4<1>;
+L_0x2b2a130 .delay (10000,10000,10000) L_0x2b2a130/d;
+L_0x2b3e940/d .functor NAND 1, L_0x2b3ef40, L_0x2b3d990, L_0x2b2a380, C4<1>;
+L_0x2b3e940 .delay (10000,10000,10000) L_0x2b3e940/d;
+L_0x2b3ea30/d .functor NAND 1, L_0x2b3d8a0, L_0x2b3de90, L_0x2b2a420, C4<1>;
+L_0x2b3ea30 .delay (10000,10000,10000) L_0x2b3ea30/d;
+L_0x2b3eb20/d .functor NAND 1, L_0x2b3ef40, L_0x2b3de90, L_0x2b3e470, C4<1>;
+L_0x2b3eb20 .delay (10000,10000,10000) L_0x2b3eb20/d;
+L_0x2b3ec90/d .functor NAND 1, L_0x2b2a130, L_0x2b3e940, L_0x2b3ea30, L_0x2b3eb20;
+L_0x2b3ec90 .delay (10000,10000,10000) L_0x2b3ec90/d;
+v0x22b7080_0 .net "S0", 0 0, L_0x2b3ef40; 1 drivers
+v0x22ba650_0 .net "S1", 0 0, L_0x2b3de90; 1 drivers
+v0x22bba50_0 .net "in0", 0 0, L_0x2b3dfc0; 1 drivers
+v0x22bc920_0 .net "in1", 0 0, L_0x2b2a380; 1 drivers
+v0x22c05a0_0 .net "in2", 0 0, L_0x2b2a420; 1 drivers
+v0x22c1470_0 .net "in3", 0 0, L_0x2b3e470; 1 drivers
+v0x22c50f0_0 .net "nS0", 0 0, L_0x2b3d8a0; 1 drivers
+v0x22c5fc0_0 .net "nS1", 0 0, L_0x2b3d990; 1 drivers
+v0x22c9c40_0 .net "out", 0 0, L_0x2b3ec90; 1 drivers
+v0x22cab10_0 .net "out0", 0 0, L_0x2b2a130; 1 drivers
+v0x22cd2e0_0 .net "out1", 0 0, L_0x2b3e940; 1 drivers
+v0x22ce720_0 .net "out2", 0 0, L_0x2b3ea30; 1 drivers
+v0x22d1cf0_0 .net "out3", 0 0, L_0x2b3eb20; 1 drivers
+S_0x220bb40 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22070f0;
+ .timescale -9 -12;
+L_0x2b3e560/d .functor NOT 1, L_0x2b2b4b0, C4<0>, C4<0>, C4<0>;
+L_0x2b3e560 .delay (10000,10000,10000) L_0x2b3e560/d;
+L_0x2b3e650/d .functor AND 1, L_0x2b2b550, L_0x2b3e560, C4<1>, C4<1>;
+L_0x2b3e650 .delay (20000,20000,20000) L_0x2b3e650/d;
+L_0x2b3e740/d .functor AND 1, L_0x2b2ac40, L_0x2b2b4b0, C4<1>, C4<1>;
+L_0x2b3e740 .delay (20000,20000,20000) L_0x2b3e740/d;
+L_0x2b2a510/d .functor OR 1, L_0x2b3e650, L_0x2b3e740, C4<0>, C4<0>;
+L_0x2b2a510 .delay (20000,20000,20000) L_0x2b2a510/d;
+v0x22aa050_0 .net "S", 0 0, L_0x2b2b4b0; 1 drivers
+v0x22ac820_0 .net "in0", 0 0, L_0x2b2b550; 1 drivers
+v0x2263f70_0 .net "in1", 0 0, L_0x2b2ac40; 1 drivers
+v0x22adc60_0 .net "nS", 0 0, L_0x2b3e560; 1 drivers
+v0x22b1230_0 .net "out0", 0 0, L_0x2b3e650; 1 drivers
+v0x22b2670_0 .net "out1", 0 0, L_0x2b3e740; 1 drivers
+v0x22b5c40_0 .net "outfinal", 0 0, L_0x2b2a510; 1 drivers
+S_0x2206450 .scope generate, "muxbits[17]" "muxbits[17]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x2756df8 .param/l "i" 3 64, +C4<010001>;
+L_0x2b42400/d .functor OR 1, L_0x2b42540, L_0x2b425e0, C4<0>, C4<0>;
+L_0x2b42400 .delay (20000,20000,20000) L_0x2b42400/d;
+v0x22a5500_0 .net *"_s15", 0 0, L_0x2b42540; 1 drivers
+v0x22a9180_0 .net *"_s16", 0 0, L_0x2b425e0; 1 drivers
+S_0x2208c50 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2206450;
+ .timescale -9 -12;
+L_0x2b2bca0/d .functor NOT 1, L_0x2b40450, C4<0>, C4<0>, C4<0>;
+L_0x2b2bca0 .delay (10000,10000,10000) L_0x2b2bca0/d;
+L_0x2b2bd90/d .functor NOT 1, L_0x2b40580, C4<0>, C4<0>, C4<0>;
+L_0x2b2bd90 .delay (10000,10000,10000) L_0x2b2bd90/d;
+L_0x2b2be30/d .functor NAND 1, L_0x2b2bca0, L_0x2b2bd90, L_0x2b406b0, C4<1>;
+L_0x2b2be30 .delay (10000,10000,10000) L_0x2b2be30/d;
+L_0x2b3f970/d .functor NAND 1, L_0x2b40450, L_0x2b2bd90, L_0x2b40750, C4<1>;
+L_0x2b3f970 .delay (10000,10000,10000) L_0x2b3f970/d;
+L_0x2b3fa60/d .functor NAND 1, L_0x2b2bca0, L_0x2b40580, L_0x2b407f0, C4<1>;
+L_0x2b3fa60 .delay (10000,10000,10000) L_0x2b3fa60/d;
+L_0x2b40090/d .functor NAND 1, L_0x2b40450, L_0x2b40580, L_0x2b408e0, C4<1>;
+L_0x2b40090 .delay (10000,10000,10000) L_0x2b40090/d;
+L_0x2b401a0/d .functor NAND 1, L_0x2b2be30, L_0x2b3f970, L_0x2b3fa60, L_0x2b40090;
+L_0x2b401a0 .delay (10000,10000,10000) L_0x2b401a0/d;
+v0x2289590_0 .net "S0", 0 0, L_0x2b40450; 1 drivers
+v0x228bd60_0 .net "S1", 0 0, L_0x2b40580; 1 drivers
+v0x228d1a0_0 .net "in0", 0 0, L_0x2b406b0; 1 drivers
+v0x2290770_0 .net "in1", 0 0, L_0x2b40750; 1 drivers
+v0x2291bb0_0 .net "in2", 0 0, L_0x2b407f0; 1 drivers
+v0x2295180_0 .net "in3", 0 0, L_0x2b408e0; 1 drivers
+v0x22965c0_0 .net "nS0", 0 0, L_0x2b2bca0; 1 drivers
+v0x2299b90_0 .net "nS1", 0 0, L_0x2b2bd90; 1 drivers
+v0x229afd0_0 .net "out", 0 0, L_0x2b401a0; 1 drivers
+v0x229fae0_0 .net "out0", 0 0, L_0x2b2be30; 1 drivers
+v0x22a09b0_0 .net "out1", 0 0, L_0x2b3f970; 1 drivers
+v0x22a4630_0 .net "out2", 0 0, L_0x2b3fa60; 1 drivers
+v0x22630a0_0 .net "out3", 0 0, L_0x2b40090; 1 drivers
+S_0x2208ee0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2206450;
+ .timescale -9 -12;
+L_0x2b409d0/d .functor NOT 1, L_0x2b40e90, C4<0>, C4<0>, C4<0>;
+L_0x2b409d0 .delay (10000,10000,10000) L_0x2b409d0/d;
+L_0x2b419a0/d .functor NOT 1, L_0x2b40fc0, C4<0>, C4<0>, C4<0>;
+L_0x2b419a0 .delay (10000,10000,10000) L_0x2b419a0/d;
+L_0x2b41a40/d .functor NAND 1, L_0x2b409d0, L_0x2b419a0, L_0x2b410f0, C4<1>;
+L_0x2b41a40 .delay (10000,10000,10000) L_0x2b41a40/d;
+L_0x2b41b80/d .functor NAND 1, L_0x2b40e90, L_0x2b419a0, L_0x2b41190, C4<1>;
+L_0x2b41b80 .delay (10000,10000,10000) L_0x2b41b80/d;
+L_0x2b41c70/d .functor NAND 1, L_0x2b409d0, L_0x2b40fc0, L_0x2b41230, C4<1>;
+L_0x2b41c70 .delay (10000,10000,10000) L_0x2b41c70/d;
+L_0x2b41d60/d .functor NAND 1, L_0x2b40e90, L_0x2b40fc0, L_0x2b41320, C4<1>;
+L_0x2b41d60 .delay (10000,10000,10000) L_0x2b41d60/d;
+L_0x2b41ed0/d .functor NAND 1, L_0x2b41a40, L_0x2b41b80, L_0x2b41c70, L_0x2b41d60;
+L_0x2b41ed0 .delay (10000,10000,10000) L_0x2b41ed0/d;
+v0x2267110_0 .net "S0", 0 0, L_0x2b40e90; 1 drivers
+v0x2268f40_0 .net "S1", 0 0, L_0x2b40fc0; 1 drivers
+v0x2269190_0 .net "in0", 0 0, L_0x2b410f0; 1 drivers
+v0x2262340_0 .net "in1", 0 0, L_0x2b41190; 1 drivers
+v0x22625c0_0 .net "in2", 0 0, L_0x2b41230; 1 drivers
+v0x22643f0_0 .net "in3", 0 0, L_0x2b41320; 1 drivers
+v0x2264640_0 .net "nS0", 0 0, L_0x2b409d0; 1 drivers
+v0x227a4f0_0 .net "nS1", 0 0, L_0x2b419a0; 1 drivers
+v0x227f020_0 .net "out", 0 0, L_0x2b41ed0; 1 drivers
+v0x227fef0_0 .net "out0", 0 0, L_0x2b41a40; 1 drivers
+v0x2283b70_0 .net "out1", 0 0, L_0x2b41b80; 1 drivers
+v0x2284a40_0 .net "out2", 0 0, L_0x2b41c70; 1 drivers
+v0x22886c0_0 .net "out3", 0 0, L_0x2b41d60; 1 drivers
+S_0x22043d0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2206450;
+ .timescale -9 -12;
+L_0x2b41410/d .functor NOT 1, L_0x2b42c80, C4<0>, C4<0>, C4<0>;
+L_0x2b41410 .delay (10000,10000,10000) L_0x2b41410/d;
+L_0x2b41500/d .functor AND 1, L_0x2b42180, L_0x2b41410, C4<1>, C4<1>;
+L_0x2b41500 .delay (20000,20000,20000) L_0x2b41500/d;
+L_0x2b415f0/d .functor AND 1, L_0x2b42270, L_0x2b42c80, C4<1>, C4<1>;
+L_0x2b415f0 .delay (20000,20000,20000) L_0x2b415f0/d;
+L_0x2b416e0/d .functor OR 1, L_0x2b41500, L_0x2b415f0, C4<0>, C4<0>;
+L_0x2b416e0 .delay (20000,20000,20000) L_0x2b416e0/d;
+v0x2280370_0 .net "S", 0 0, L_0x2b42c80; 1 drivers
+v0x22805c0_0 .net "in0", 0 0, L_0x2b42180; 1 drivers
+v0x2279ce0_0 .net "in1", 0 0, L_0x2b42270; 1 drivers
+v0x22752d0_0 .net "nS", 0 0, L_0x2b41410; 1 drivers
+v0x22708c0_0 .net "out0", 0 0, L_0x2b41500; 1 drivers
+v0x226beb0_0 .net "out1", 0 0, L_0x2b415f0; 1 drivers
+v0x2266e90_0 .net "outfinal", 0 0, L_0x2b416e0; 1 drivers
+S_0x2258160 .scope generate, "muxbits[18]" "muxbits[18]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x27428a8 .param/l "i" 3 64, +C4<010010>;
+L_0x2b44ad0/d .functor OR 1, L_0x2b44bd0, L_0x2b44c70, C4<0>, C4<0>;
+L_0x2b44ad0 .delay (20000,20000,20000) L_0x2b44ad0/d;
+v0x227e2c0_0 .net *"_s15", 0 0, L_0x2b44bd0; 1 drivers
+v0x227e540_0 .net *"_s16", 0 0, L_0x2b44c70; 1 drivers
+S_0x22015c0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2258160;
+ .timescale -9 -12;
+L_0x2b426d0/d .functor NOT 1, L_0x2b42d20, C4<0>, C4<0>, C4<0>;
+L_0x2b426d0 .delay (10000,10000,10000) L_0x2b426d0/d;
+L_0x2b427c0/d .functor NOT 1, L_0x2b42e50, C4<0>, C4<0>, C4<0>;
+L_0x2b427c0 .delay (10000,10000,10000) L_0x2b427c0/d;
+L_0x2b42860/d .functor NAND 1, L_0x2b426d0, L_0x2b427c0, L_0x2b42f80, C4<1>;
+L_0x2b42860 .delay (10000,10000,10000) L_0x2b42860/d;
+L_0x2b429a0/d .functor NAND 1, L_0x2b42d20, L_0x2b427c0, L_0x2b43020, C4<1>;
+L_0x2b429a0 .delay (10000,10000,10000) L_0x2b429a0/d;
+L_0x2b42a90/d .functor NAND 1, L_0x2b426d0, L_0x2b42e50, L_0x2b430c0, C4<1>;
+L_0x2b42a90 .delay (10000,10000,10000) L_0x2b42a90/d;
+L_0x2b42b80/d .functor NAND 1, L_0x2b42d20, L_0x2b42e50, L_0x2b431b0, C4<1>;
+L_0x2b42b80 .delay (10000,10000,10000) L_0x2b42b80/d;
+L_0x2b43850/d .functor NAND 1, L_0x2b42860, L_0x2b429a0, L_0x2b42a90, L_0x2b42b80;
+L_0x2b43850 .delay (10000,10000,10000) L_0x2b43850/d;
+v0x22a1080_0 .net "S0", 0 0, L_0x2b42d20; 1 drivers
+v0x229a7b0_0 .net "S1", 0 0, L_0x2b42e50; 1 drivers
+v0x2295da0_0 .net "in0", 0 0, L_0x2b42f80; 1 drivers
+v0x2291390_0 .net "in1", 0 0, L_0x2b43020; 1 drivers
+v0x228c980_0 .net "in2", 0 0, L_0x2b430c0; 1 drivers
+v0x2287960_0 .net "in3", 0 0, L_0x2b431b0; 1 drivers
+v0x2287be0_0 .net "nS0", 0 0, L_0x2b426d0; 1 drivers
+v0x2289a10_0 .net "nS1", 0 0, L_0x2b427c0; 1 drivers
+v0x2289c60_0 .net "out", 0 0, L_0x2b43850; 1 drivers
+v0x2282e10_0 .net "out0", 0 0, L_0x2b42860; 1 drivers
+v0x2283090_0 .net "out1", 0 0, L_0x2b429a0; 1 drivers
+v0x2284ec0_0 .net "out2", 0 0, L_0x2b42a90; 1 drivers
+v0x2285110_0 .net "out3", 0 0, L_0x2b42b80; 1 drivers
+S_0x22031f0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2258160;
+ .timescale -9 -12;
+L_0x2b432a0/d .functor NOT 1, L_0x2b449a0, C4<0>, C4<0>, C4<0>;
+L_0x2b432a0 .delay (10000,10000,10000) L_0x2b432a0/d;
+L_0x2b43350/d .functor NOT 1, L_0x2b43b00, C4<0>, C4<0>, C4<0>;
+L_0x2b43350 .delay (10000,10000,10000) L_0x2b43350/d;
+L_0x2b433f0/d .functor NAND 1, L_0x2b432a0, L_0x2b43350, L_0x2b43c30, C4<1>;
+L_0x2b433f0 .delay (10000,10000,10000) L_0x2b433f0/d;
+L_0x2b43530/d .functor NAND 1, L_0x2b449a0, L_0x2b43350, L_0x2b43cd0, C4<1>;
+L_0x2b43530 .delay (10000,10000,10000) L_0x2b43530/d;
+L_0x2b43620/d .functor NAND 1, L_0x2b432a0, L_0x2b43b00, L_0x2b43d70, C4<1>;
+L_0x2b43620 .delay (10000,10000,10000) L_0x2b43620/d;
+L_0x2b43740/d .functor NAND 1, L_0x2b449a0, L_0x2b43b00, L_0x2b43e60, C4<1>;
+L_0x2b43740 .delay (10000,10000,10000) L_0x2b43740/d;
+L_0x2b446f0/d .functor NAND 1, L_0x2b433f0, L_0x2b43530, L_0x2b43620, L_0x2b43740;
+L_0x2b446f0 .delay (10000,10000,10000) L_0x2b446f0/d;
+v0x22b1e50_0 .net "S0", 0 0, L_0x2b449a0; 1 drivers
+v0x22ad440_0 .net "S1", 0 0, L_0x2b43b00; 1 drivers
+v0x22a8420_0 .net "in0", 0 0, L_0x2b43c30; 1 drivers
+v0x22a86a0_0 .net "in1", 0 0, L_0x2b43cd0; 1 drivers
+v0x22aa4d0_0 .net "in2", 0 0, L_0x2b43d70; 1 drivers
+v0x22aa720_0 .net "in3", 0 0, L_0x2b43e60; 1 drivers
+v0x22a38d0_0 .net "nS0", 0 0, L_0x2b432a0; 1 drivers
+v0x22a3b50_0 .net "nS1", 0 0, L_0x2b43350; 1 drivers
+v0x22a5980_0 .net "out", 0 0, L_0x2b446f0; 1 drivers
+v0x22a5bd0_0 .net "out0", 0 0, L_0x2b433f0; 1 drivers
+v0x229ed80_0 .net "out1", 0 0, L_0x2b43530; 1 drivers
+v0x229f000_0 .net "out2", 0 0, L_0x2b43620; 1 drivers
+v0x22a0e30_0 .net "out3", 0 0, L_0x2b43740; 1 drivers
+S_0x22034b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2258160;
+ .timescale -9 -12;
+L_0x2b43f50/d .functor NOT 1, L_0x2b44400, C4<0>, C4<0>, C4<0>;
+L_0x2b43f50 .delay (10000,10000,10000) L_0x2b43f50/d;
+L_0x2b44040/d .functor AND 1, L_0x2b444a0, L_0x2b43f50, C4<1>, C4<1>;
+L_0x2b44040 .delay (20000,20000,20000) L_0x2b44040/d;
+L_0x2b44130/d .functor AND 1, L_0x2b44590, L_0x2b44400, C4<1>, C4<1>;
+L_0x2b44130 .delay (20000,20000,20000) L_0x2b44130/d;
+L_0x2b44220/d .functor OR 1, L_0x2b44040, L_0x2b44130, C4<0>, C4<0>;
+L_0x2b44220 .delay (20000,20000,20000) L_0x2b44220/d;
+v0x22bf840_0 .net "S", 0 0, L_0x2b44400; 1 drivers
+v0x22bfac0_0 .net "in0", 0 0, L_0x2b444a0; 1 drivers
+v0x22c18f0_0 .net "in1", 0 0, L_0x2b44590; 1 drivers
+v0x22c1b40_0 .net "nS", 0 0, L_0x2b43f50; 1 drivers
+v0x22bcda0_0 .net "out0", 0 0, L_0x2b44040; 1 drivers
+v0x22bcff0_0 .net "out1", 0 0, L_0x2b44130; 1 drivers
+v0x22b6860_0 .net "outfinal", 0 0, L_0x2b44220; 1 drivers
+S_0x2227210 .scope generate, "muxbits[19]" "muxbits[19]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x275f078 .param/l "i" 3 64, +C4<010011>;
+L_0x2b471f0/d .functor OR 1, L_0x2b47330, L_0x2b473d0, C4<0>, C4<0>;
+L_0x2b471f0 .delay (20000,20000,20000) L_0x2b471f0/d;
+v0x22c6440_0 .net *"_s15", 0 0, L_0x2b47330; 1 drivers
+v0x22c6690_0 .net *"_s16", 0 0, L_0x2b473d0; 1 drivers
+S_0x22217d0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2227210;
+ .timescale -9 -12;
+L_0x2b44d60/d .functor NOT 1, L_0x2b46360, C4<0>, C4<0>, C4<0>;
+L_0x2b44d60 .delay (10000,10000,10000) L_0x2b44d60/d;
+L_0x2b44e50/d .functor NOT 1, L_0x2b45780, C4<0>, C4<0>, C4<0>;
+L_0x2b44e50 .delay (10000,10000,10000) L_0x2b44e50/d;
+L_0x2b44ef0/d .functor NAND 1, L_0x2b44d60, L_0x2b44e50, L_0x2b458b0, C4<1>;
+L_0x2b44ef0 .delay (10000,10000,10000) L_0x2b44ef0/d;
+L_0x2b45030/d .functor NAND 1, L_0x2b46360, L_0x2b44e50, L_0x2b45950, C4<1>;
+L_0x2b45030 .delay (10000,10000,10000) L_0x2b45030/d;
+L_0x2b45120/d .functor NAND 1, L_0x2b44d60, L_0x2b45780, L_0x2b459f0, C4<1>;
+L_0x2b45120 .delay (10000,10000,10000) L_0x2b45120/d;
+L_0x2b45210/d .functor NAND 1, L_0x2b46360, L_0x2b45780, L_0x2b45ae0, C4<1>;
+L_0x2b45210 .delay (10000,10000,10000) L_0x2b45210/d;
+L_0x2b45350/d .functor NAND 1, L_0x2b44ef0, L_0x2b45030, L_0x2b45120, L_0x2b45210;
+L_0x2b45350 .delay (10000,10000,10000) L_0x2b45350/d;
+v0x22db7d0_0 .net "S0", 0 0, L_0x2b46360; 1 drivers
+v0x22dba50_0 .net "S1", 0 0, L_0x2b45780; 1 drivers
+v0x22dd880_0 .net "in0", 0 0, L_0x2b458b0; 1 drivers
+v0x22ddad0_0 .net "in1", 0 0, L_0x2b45950; 1 drivers
+v0x22d7320_0 .net "in2", 0 0, L_0x2b459f0; 1 drivers
+v0x22d2910_0 .net "in3", 0 0, L_0x2b45ae0; 1 drivers
+v0x22cdf00_0 .net "nS0", 0 0, L_0x2b44d60; 1 drivers
+v0x22c8ee0_0 .net "nS1", 0 0, L_0x2b44e50; 1 drivers
+v0x22c9160_0 .net "out", 0 0, L_0x2b45350; 1 drivers
+v0x22caf90_0 .net "out0", 0 0, L_0x2b44ef0; 1 drivers
+v0x22cb1e0_0 .net "out1", 0 0, L_0x2b45030; 1 drivers
+v0x22c4390_0 .net "out2", 0 0, L_0x2b45120; 1 drivers
+v0x22c4610_0 .net "out3", 0 0, L_0x2b45210; 1 drivers
+S_0x22058c0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2227210;
+ .timescale -9 -12;
+L_0x2b45bd0/d .functor NOT 1, L_0x2b46400, C4<0>, C4<0>, C4<0>;
+L_0x2b45bd0 .delay (10000,10000,10000) L_0x2b45bd0/d;
+L_0x2b45cc0/d .functor NOT 1, L_0x2b46530, C4<0>, C4<0>, C4<0>;
+L_0x2b45cc0 .delay (10000,10000,10000) L_0x2b45cc0/d;
+L_0x2b45d60/d .functor NAND 1, L_0x2b45bd0, L_0x2b45cc0, L_0x2b46660, C4<1>;
+L_0x2b45d60 .delay (10000,10000,10000) L_0x2b45d60/d;
+L_0x2b45ea0/d .functor NAND 1, L_0x2b46400, L_0x2b45cc0, L_0x2b46700, C4<1>;
+L_0x2b45ea0 .delay (10000,10000,10000) L_0x2b45ea0/d;
+L_0x2b45f90/d .functor NAND 1, L_0x2b45bd0, L_0x2b46530, L_0x2b467a0, C4<1>;
+L_0x2b45f90 .delay (10000,10000,10000) L_0x2b45f90/d;
+L_0x2b46080/d .functor NAND 1, L_0x2b46400, L_0x2b46530, L_0x2b46890, C4<1>;
+L_0x2b46080 .delay (10000,10000,10000) L_0x2b46080/d;
+L_0x2b461f0/d .functor NAND 1, L_0x2b45d60, L_0x2b45ea0, L_0x2b45f90, L_0x2b46080;
+L_0x2b461f0 .delay (10000,10000,10000) L_0x2b461f0/d;
+v0x2313850_0 .net "S0", 0 0, L_0x2b46400; 1 drivers
+v0x22e99c0_0 .net "S1", 0 0, L_0x2b46530; 1 drivers
+v0x22e9c40_0 .net "in0", 0 0, L_0x2b46660; 1 drivers
+v0x22eba70_0 .net "in1", 0 0, L_0x2b46700; 1 drivers
+v0x22ebcc0_0 .net "in2", 0 0, L_0x2b467a0; 1 drivers
+v0x22e4e70_0 .net "in3", 0 0, L_0x2b46890; 1 drivers
+v0x22e50f0_0 .net "nS0", 0 0, L_0x2b45bd0; 1 drivers
+v0x22e6f20_0 .net "nS1", 0 0, L_0x2b45cc0; 1 drivers
+v0x22e7170_0 .net "out", 0 0, L_0x2b461f0; 1 drivers
+v0x22e0320_0 .net "out0", 0 0, L_0x2b45d60; 1 drivers
+v0x22e05a0_0 .net "out1", 0 0, L_0x2b45ea0; 1 drivers
+v0x22e23d0_0 .net "out2", 0 0, L_0x2b45f90; 1 drivers
+v0x22e2620_0 .net "out3", 0 0, L_0x2b46080; 1 drivers
+S_0x22244f0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2227210;
+ .timescale -9 -12;
+L_0x2b46980/d .functor NOT 1, L_0x2b46e30, C4<0>, C4<0>, C4<0>;
+L_0x2b46980 .delay (10000,10000,10000) L_0x2b46980/d;
+L_0x2b46a70/d .functor AND 1, L_0x2b46ed0, L_0x2b46980, C4<1>, C4<1>;
+L_0x2b46a70 .delay (20000,20000,20000) L_0x2b46a70/d;
+L_0x2b46b60/d .functor AND 1, L_0x2b47db0, L_0x2b46e30, C4<1>, C4<1>;
+L_0x2b46b60 .delay (20000,20000,20000) L_0x2b46b60/d;
+L_0x2b46c50/d .functor OR 1, L_0x2b46a70, L_0x2b46b60, C4<0>, C4<0>;
+L_0x2b46c50 .delay (20000,20000,20000) L_0x2b46c50/d;
+v0x22fa5b0_0 .net "S", 0 0, L_0x2b46e30; 1 drivers
+v0x230ceb0_0 .net "in0", 0 0, L_0x2b46ed0; 1 drivers
+v0x22f6650_0 .net "in1", 0 0, L_0x2b47db0; 1 drivers
+v0x230e3d0_0 .net "nS", 0 0, L_0x2b46980; 1 drivers
+v0x230f8f0_0 .net "out0", 0 0, L_0x2b46a70; 1 drivers
+v0x2310e10_0 .net "out1", 0 0, L_0x2b46b60; 1 drivers
+v0x2312330_0 .net "outfinal", 0 0, L_0x2b46c50; 1 drivers
+S_0x22403f0 .scope generate, "muxbits[20]" "muxbits[20]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x25c7678 .param/l "i" 3 64, +C4<010100>;
+L_0x2b49910/d .functor OR 1, L_0x2b4a800, L_0x2b4a8a0, C4<0>, C4<0>;
+L_0x2b49910 .delay (20000,20000,20000) L_0x2b49910/d;
+v0x231b710_0 .net *"_s15", 0 0, L_0x2b4a800; 1 drivers
+v0x22f9090_0 .net *"_s16", 0 0, L_0x2b4a8a0; 1 drivers
+S_0x223a9b0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x22403f0;
+ .timescale -9 -12;
+L_0x2b474c0/d .functor NOT 1, L_0x2b48ae0, C4<0>, C4<0>, C4<0>;
+L_0x2b474c0 .delay (10000,10000,10000) L_0x2b474c0/d;
+L_0x2b475b0/d .functor NOT 1, L_0x2b48c10, C4<0>, C4<0>, C4<0>;
+L_0x2b475b0 .delay (10000,10000,10000) L_0x2b475b0/d;
+L_0x2b47650/d .functor NAND 1, L_0x2b474c0, L_0x2b475b0, L_0x2b47e50, C4<1>;
+L_0x2b47650 .delay (10000,10000,10000) L_0x2b47650/d;
+L_0x2b47790/d .functor NAND 1, L_0x2b48ae0, L_0x2b475b0, L_0x2b47ef0, C4<1>;
+L_0x2b47790 .delay (10000,10000,10000) L_0x2b47790/d;
+L_0x2b47880/d .functor NAND 1, L_0x2b474c0, L_0x2b48c10, L_0x2b47f90, C4<1>;
+L_0x2b47880 .delay (10000,10000,10000) L_0x2b47880/d;
+L_0x2b47970/d .functor NAND 1, L_0x2b48ae0, L_0x2b48c10, L_0x2b48030, C4<1>;
+L_0x2b47970 .delay (10000,10000,10000) L_0x2b47970/d;
+L_0x2b47ab0/d .functor NAND 1, L_0x2b47650, L_0x2b47790, L_0x2b47880, L_0x2b47970;
+L_0x2b47ab0 .delay (10000,10000,10000) L_0x2b47ab0/d;
+v0x23e3740_0 .net "S0", 0 0, L_0x2b48ae0; 1 drivers
+v0x23e95a0_0 .net "S1", 0 0, L_0x2b48c10; 1 drivers
+v0x2400e60_0 .net "in0", 0 0, L_0x2b47e50; 1 drivers
+v0x2406cc0_0 .net "in1", 0 0, L_0x2b47ef0; 1 drivers
+v0x240cb20_0 .net "in2", 0 0, L_0x2b47f90; 1 drivers
+v0x258bd90_0 .net "in3", 0 0, L_0x2b48030; 1 drivers
+v0x22fbe20_0 .net "nS0", 0 0, L_0x2b474c0; 1 drivers
+v0x2314d70_0 .net "nS1", 0 0, L_0x2b475b0; 1 drivers
+v0x2316290_0 .net "out", 0 0, L_0x2b47ab0; 1 drivers
+v0x23177b0_0 .net "out0", 0 0, L_0x2b47650; 1 drivers
+v0x2318cd0_0 .net "out1", 0 0, L_0x2b47790; 1 drivers
+v0x231a1f0_0 .net "out2", 0 0, L_0x2b47880; 1 drivers
+v0x22f7b70_0 .net "out3", 0 0, L_0x2b47970; 1 drivers
+S_0x223d6d0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x22403f0;
+ .timescale -9 -12;
+L_0x2b48120/d .functor NOT 1, L_0x2b489f0, C4<0>, C4<0>, C4<0>;
+L_0x2b48120 .delay (10000,10000,10000) L_0x2b48120/d;
+L_0x2b48210/d .functor NOT 1, L_0x2b48d40, C4<0>, C4<0>, C4<0>;
+L_0x2b48210 .delay (10000,10000,10000) L_0x2b48210/d;
+L_0x2b482b0/d .functor NAND 1, L_0x2b48120, L_0x2b48210, L_0x2b48e70, C4<1>;
+L_0x2b482b0 .delay (10000,10000,10000) L_0x2b482b0/d;
+L_0x2b483f0/d .functor NAND 1, L_0x2b489f0, L_0x2b48210, L_0x2b48f10, C4<1>;
+L_0x2b483f0 .delay (10000,10000,10000) L_0x2b483f0/d;
+L_0x2b484e0/d .functor NAND 1, L_0x2b48120, L_0x2b48d40, L_0x2b48fb0, C4<1>;
+L_0x2b484e0 .delay (10000,10000,10000) L_0x2b484e0/d;
+L_0x2b485d0/d .functor NAND 1, L_0x2b489f0, L_0x2b48d40, L_0x2b49050, C4<1>;
+L_0x2b485d0 .delay (10000,10000,10000) L_0x2b485d0/d;
+L_0x2b48740/d .functor NAND 1, L_0x2b482b0, L_0x2b483f0, L_0x2b484e0, L_0x2b485d0;
+L_0x2b48740 .delay (10000,10000,10000) L_0x2b48740/d;
+v0x241d3f0_0 .net "S0", 0 0, L_0x2b489f0; 1 drivers
+v0x2438a40_0 .net "S1", 0 0, L_0x2b48d40; 1 drivers
+v0x1f6b360_0 .net "in0", 0 0, L_0x2b48e70; 1 drivers
+v0x2381d40_0 .net "in1", 0 0, L_0x2b48f10; 1 drivers
+v0x2387990_0 .net "in2", 0 0, L_0x2b48fb0; 1 drivers
+v0x236ae00_0 .net "in3", 0 0, L_0x2b49050; 1 drivers
+v0x238d5e0_0 .net "nS0", 0 0, L_0x2b48120; 1 drivers
+v0x239e850_0 .net "nS1", 0 0, L_0x2b48210; 1 drivers
+v0x23a44a0_0 .net "out", 0 0, L_0x2b48740; 1 drivers
+v0x23aa0f0_0 .net "out0", 0 0, L_0x2b482b0; 1 drivers
+v0x23c0f80_0 .net "out1", 0 0, L_0x2b483f0; 1 drivers
+v0x23c6bd0_0 .net "out2", 0 0, L_0x2b484e0; 1 drivers
+v0x23cc820_0 .net "out3", 0 0, L_0x2b485d0; 1 drivers
+S_0x2202ad0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x22403f0;
+ .timescale -9 -12;
+L_0x2b49140/d .functor NOT 1, L_0x2b495f0, C4<0>, C4<0>, C4<0>;
+L_0x2b49140 .delay (10000,10000,10000) L_0x2b49140/d;
+L_0x2b49230/d .functor AND 1, L_0x2b49690, L_0x2b49140, C4<1>, C4<1>;
+L_0x2b49230 .delay (20000,20000,20000) L_0x2b49230/d;
+L_0x2b49320/d .functor AND 1, L_0x2b49780, L_0x2b495f0, C4<1>, C4<1>;
+L_0x2b49320 .delay (20000,20000,20000) L_0x2b49320/d;
+L_0x2b49410/d .functor OR 1, L_0x2b49230, L_0x2b49320, C4<0>, C4<0>;
+L_0x2b49410 .delay (20000,20000,20000) L_0x2b49410/d;
+v0x24b0ba0_0 .net "S", 0 0, L_0x2b495f0; 1 drivers
+v0x24b4cb0_0 .net "in0", 0 0, L_0x2b49690; 1 drivers
+v0x242b8e0_0 .net "in1", 0 0, L_0x2b49780; 1 drivers
+v0x242f0e0_0 .net "nS", 0 0, L_0x2b49140; 1 drivers
+v0x2430620_0 .net "out0", 0 0, L_0x2b49230; 1 drivers
+v0x2433d90_0 .net "out1", 0 0, L_0x2b49320; 1 drivers
+v0x24352d0_0 .net "outfinal", 0 0, L_0x2b49410; 1 drivers
+S_0x2259ee0 .scope generate, "muxbits[21]" "muxbits[21]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x25f0a58 .param/l "i" 3 64, +C4<010101>;
+L_0x2b32190/d .functor OR 1, L_0x2b4bbd0, L_0x2b4bc70, C4<0>, C4<0>;
+L_0x2b32190 .delay (20000,20000,20000) L_0x2b32190/d;
+v0x24ac7e0_0 .net *"_s15", 0 0, L_0x2b4bbd0; 1 drivers
+v0x242a450_0 .net *"_s16", 0 0, L_0x2b4bc70; 1 drivers
+S_0x2243110 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2259ee0;
+ .timescale -9 -12;
+L_0x2b49a90/d .functor NOT 1, L_0x2b4a330, C4<0>, C4<0>, C4<0>;
+L_0x2b49a90 .delay (10000,10000,10000) L_0x2b49a90/d;
+L_0x2b49b80/d .functor NOT 1, L_0x2b4a460, C4<0>, C4<0>, C4<0>;
+L_0x2b49b80 .delay (10000,10000,10000) L_0x2b49b80/d;
+L_0x2b49c20/d .functor NAND 1, L_0x2b49a90, L_0x2b49b80, L_0x2b4a590, C4<1>;
+L_0x2b49c20 .delay (10000,10000,10000) L_0x2b49c20/d;
+L_0x2b49d60/d .functor NAND 1, L_0x2b4a330, L_0x2b49b80, L_0x2b4a630, C4<1>;
+L_0x2b49d60 .delay (10000,10000,10000) L_0x2b49d60/d;
+L_0x2b49e50/d .functor NAND 1, L_0x2b49a90, L_0x2b4a460, L_0x2b4a6d0, C4<1>;
+L_0x2b49e50 .delay (10000,10000,10000) L_0x2b49e50/d;
+L_0x2b49f40/d .functor NAND 1, L_0x2b4a330, L_0x2b4a460, L_0x2b4a990, C4<1>;
+L_0x2b49f40 .delay (10000,10000,10000) L_0x2b49f40/d;
+L_0x2b4a080/d .functor NAND 1, L_0x2b49c20, L_0x2b49d60, L_0x2b49e50, L_0x2b49f40;
+L_0x2b4a080 .delay (10000,10000,10000) L_0x2b4a080/d;
+v0x248fe30_0 .net "S0", 0 0, L_0x2b4a330; 1 drivers
+v0x24935a0_0 .net "S1", 0 0, L_0x2b4a460; 1 drivers
+v0x2494ae0_0 .net "in0", 0 0, L_0x2b4a590; 1 drivers
+v0x2426c70_0 .net "in1", 0 0, L_0x2b4a630; 1 drivers
+v0x2498250_0 .net "in2", 0 0, L_0x2b4a6d0; 1 drivers
+v0x2499790_0 .net "in3", 0 0, L_0x2b4a990; 1 drivers
+v0x249cf00_0 .net "nS0", 0 0, L_0x2b49a90; 1 drivers
+v0x249e440_0 .net "nS1", 0 0, L_0x2b49b80; 1 drivers
+v0x24a1a70_0 .net "out", 0 0, L_0x2b4a080; 1 drivers
+v0x24a2f00_0 .net "out0", 0 0, L_0x2b49c20; 1 drivers
+v0x24a66e0_0 .net "out1", 0 0, L_0x2b49d60; 1 drivers
+v0x24a7b70_0 .net "out2", 0 0, L_0x2b49e50; 1 drivers
+v0x24ab350_0 .net "out3", 0 0, L_0x2b49f40; 1 drivers
+S_0x2245e30 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2259ee0;
+ .timescale -9 -12;
+L_0x2b4aa80/d .functor NOT 1, L_0x2b4b310, C4<0>, C4<0>, C4<0>;
+L_0x2b4aa80 .delay (10000,10000,10000) L_0x2b4aa80/d;
+L_0x2b4ab30/d .functor NOT 1, L_0x2b4b440, C4<0>, C4<0>, C4<0>;
+L_0x2b4ab30 .delay (10000,10000,10000) L_0x2b4ab30/d;
+L_0x2b4abd0/d .functor NAND 1, L_0x2b4aa80, L_0x2b4ab30, L_0x2b4b570, C4<1>;
+L_0x2b4abd0 .delay (10000,10000,10000) L_0x2b4abd0/d;
+L_0x2b4ad10/d .functor NAND 1, L_0x2b4b310, L_0x2b4ab30, L_0x2b4b610, C4<1>;
+L_0x2b4ad10 .delay (10000,10000,10000) L_0x2b4ad10/d;
+L_0x2b4ae00/d .functor NAND 1, L_0x2b4aa80, L_0x2b4b440, L_0x2b4c4c0, C4<1>;
+L_0x2b4ae00 .delay (10000,10000,10000) L_0x2b4ae00/d;
+L_0x2b4aef0/d .functor NAND 1, L_0x2b4b310, L_0x2b4b440, L_0x2b4c5b0, C4<1>;
+L_0x2b4aef0 .delay (10000,10000,10000) L_0x2b4aef0/d;
+L_0x2b4b060/d .functor NAND 1, L_0x2b4abd0, L_0x2b4ad10, L_0x2b4ae00, L_0x2b4aef0;
+L_0x2b4b060 .delay (10000,10000,10000) L_0x2b4b060/d;
+v0x2471eb0_0 .net "S0", 0 0, L_0x2b4b310; 1 drivers
+v0x24733f0_0 .net "S1", 0 0, L_0x2b4b440; 1 drivers
+v0x2476b60_0 .net "in0", 0 0, L_0x2b4b570; 1 drivers
+v0x24780a0_0 .net "in1", 0 0, L_0x2b4b610; 1 drivers
+v0x247b810_0 .net "in2", 0 0, L_0x2b4c4c0; 1 drivers
+v0x247cd50_0 .net "in3", 0 0, L_0x2b4c5b0; 1 drivers
+v0x24257e0_0 .net "nS0", 0 0, L_0x2b4aa80; 1 drivers
+v0x2481850_0 .net "nS1", 0 0, L_0x2b4ab30; 1 drivers
+v0x2485040_0 .net "out", 0 0, L_0x2b4b060; 1 drivers
+v0x24864d0_0 .net "out0", 0 0, L_0x2b4abd0; 1 drivers
+v0x2489cb0_0 .net "out1", 0 0, L_0x2b4ad10; 1 drivers
+v0x248b140_0 .net "out2", 0 0, L_0x2b4ae00; 1 drivers
+v0x248e920_0 .net "out3", 0 0, L_0x2b4aef0; 1 drivers
+S_0x2248b50 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2259ee0;
+ .timescale -9 -12;
+L_0x2b4af80/d .functor NOT 1, L_0x2b4b7d0, C4<0>, C4<0>, C4<0>;
+L_0x2b4af80 .delay (10000,10000,10000) L_0x2b4af80/d;
+L_0x2b31e70/d .functor AND 1, L_0x2b4b870, L_0x2b4af80, C4<1>, C4<1>;
+L_0x2b31e70 .delay (20000,20000,20000) L_0x2b31e70/d;
+L_0x2b31f60/d .functor AND 1, L_0x2b4b960, L_0x2b4b7d0, C4<1>, C4<1>;
+L_0x2b31f60 .delay (20000,20000,20000) L_0x2b31f60/d;
+L_0x2b32050/d .functor OR 1, L_0x2b31e70, L_0x2b31f60, C4<0>, C4<0>;
+L_0x2b32050 .delay (20000,20000,20000) L_0x2b32050/d;
+v0x2463930_0 .net "S", 0 0, L_0x2b4b7d0; 1 drivers
+v0x2464dc0_0 .net "in0", 0 0, L_0x2b4b870; 1 drivers
+v0x2422000_0 .net "in1", 0 0, L_0x2b4b960; 1 drivers
+v0x24685a0_0 .net "nS", 0 0, L_0x2b4af80; 1 drivers
+v0x2469a30_0 .net "out0", 0 0, L_0x2b31e70; 1 drivers
+v0x246d210_0 .net "out1", 0 0, L_0x2b31f60; 1 drivers
+v0x246e6a0_0 .net "outfinal", 0 0, L_0x2b32050; 1 drivers
+S_0x221eab0 .scope generate, "muxbits[22]" "muxbits[22]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d278c8 .param/l "i" 3 64, +C4<010110>;
+L_0x2b4ea20/d .functor OR 1, L_0x2b4eb60, L_0x2b4fca0, C4<0>, C4<0>;
+L_0x2b4ea20 .delay (20000,20000,20000) L_0x2b4ea20/d;
+v0x245b640_0 .net *"_s15", 0 0, L_0x2b4eb60; 1 drivers
+v0x2460140_0 .net *"_s16", 0 0, L_0x2b4fca0; 1 drivers
+S_0x225a130 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x221eab0;
+ .timescale -9 -12;
+L_0x2b4bd60/d .functor NOT 1, L_0x2b4ceb0, C4<0>, C4<0>, C4<0>;
+L_0x2b4bd60 .delay (10000,10000,10000) L_0x2b4bd60/d;
+L_0x2b4be50/d .functor NOT 1, L_0x2b4cfe0, C4<0>, C4<0>, C4<0>;
+L_0x2b4be50 .delay (10000,10000,10000) L_0x2b4be50/d;
+L_0x2b4bef0/d .functor NAND 1, L_0x2b4bd60, L_0x2b4be50, L_0x2b4d110, C4<1>;
+L_0x2b4bef0 .delay (10000,10000,10000) L_0x2b4bef0/d;
+L_0x2b4c030/d .functor NAND 1, L_0x2b4ceb0, L_0x2b4be50, L_0x2b4d1b0, C4<1>;
+L_0x2b4c030 .delay (10000,10000,10000) L_0x2b4c030/d;
+L_0x2b4c120/d .functor NAND 1, L_0x2b4bd60, L_0x2b4cfe0, L_0x2b4d250, C4<1>;
+L_0x2b4c120 .delay (10000,10000,10000) L_0x2b4c120/d;
+L_0x2b4c240/d .functor NAND 1, L_0x2b4ceb0, L_0x2b4cfe0, L_0x2b4d340, C4<1>;
+L_0x2b4c240 .delay (10000,10000,10000) L_0x2b4c240/d;
+L_0x2b4c3b0/d .functor NAND 1, L_0x2b4bef0, L_0x2b4c030, L_0x2b4c120, L_0x2b4c240;
+L_0x2b4c3b0 .delay (10000,10000,10000) L_0x2b4c3b0/d;
+v0x2442220_0 .net "S0", 0 0, L_0x2b4ceb0; 1 drivers
+v0x24436b0_0 .net "S1", 0 0, L_0x2b4cfe0; 1 drivers
+v0x2446e90_0 .net "in0", 0 0, L_0x2b4d110; 1 drivers
+v0x2448320_0 .net "in1", 0 0, L_0x2b4d1b0; 1 drivers
+v0x244bb00_0 .net "in2", 0 0, L_0x2b4d250; 1 drivers
+v0x244cf90_0 .net "in3", 0 0, L_0x2b4d340; 1 drivers
+v0x24507a0_0 .net "nS0", 0 0, L_0x2b4bd60; 1 drivers
+v0x2420b70_0 .net "nS1", 0 0, L_0x2b4be50; 1 drivers
+v0x2451ce0_0 .net "out", 0 0, L_0x2b4c3b0; 1 drivers
+v0x2455450_0 .net "out0", 0 0, L_0x2b4bef0; 1 drivers
+v0x241bdf0_0 .net "out1", 0 0, L_0x2b4c030; 1 drivers
+v0x2456990_0 .net "out2", 0 0, L_0x2b4c120; 1 drivers
+v0x245a100_0 .net "out3", 0 0, L_0x2b4c240; 1 drivers
+S_0x2219070 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x221eab0;
+ .timescale -9 -12;
+L_0x2b4d430/d .functor NOT 1, L_0x2b4ed00, C4<0>, C4<0>, C4<0>;
+L_0x2b4d430 .delay (10000,10000,10000) L_0x2b4d430/d;
+L_0x2b4d520/d .functor NOT 1, L_0x2b4de50, C4<0>, C4<0>, C4<0>;
+L_0x2b4d520 .delay (10000,10000,10000) L_0x2b4d520/d;
+L_0x2b4d5c0/d .functor NAND 1, L_0x2b4d430, L_0x2b4d520, L_0x2b4df80, C4<1>;
+L_0x2b4d5c0 .delay (10000,10000,10000) L_0x2b4d5c0/d;
+L_0x2b4d700/d .functor NAND 1, L_0x2b4ed00, L_0x2b4d520, L_0x2b4e020, C4<1>;
+L_0x2b4d700 .delay (10000,10000,10000) L_0x2b4d700/d;
+L_0x2b4d7f0/d .functor NAND 1, L_0x2b4d430, L_0x2b4de50, L_0x2b4e0c0, C4<1>;
+L_0x2b4d7f0 .delay (10000,10000,10000) L_0x2b4d7f0/d;
+L_0x2b4d8e0/d .functor NAND 1, L_0x2b4ed00, L_0x2b4de50, L_0x2b4e160, C4<1>;
+L_0x2b4d8e0 .delay (10000,10000,10000) L_0x2b4d8e0/d;
+L_0x2b4da20/d .functor NAND 1, L_0x2b4d5c0, L_0x2b4d700, L_0x2b4d7f0, L_0x2b4d8e0;
+L_0x2b4da20 .delay (10000,10000,10000) L_0x2b4da20/d;
+v0x2456170_0 .net "S0", 0 0, L_0x2b4ed00; 1 drivers
+v0x24514c0_0 .net "S1", 0 0, L_0x2b4de50; 1 drivers
+v0x243de00_0 .net "in0", 0 0, L_0x2b4df80; 1 drivers
+v0x243df80_0 .net "in1", 0 0, L_0x2b4e020; 1 drivers
+v0x2439760_0 .net "in2", 0 0, L_0x2b4e0c0; 1 drivers
+v0x2434ab0_0 .net "in3", 0 0, L_0x2b4e160; 1 drivers
+v0x242fe00_0 .net "nS0", 0 0, L_0x2b4d430; 1 drivers
+v0x241cbd0_0 .net "nS1", 0 0, L_0x2b4d520; 1 drivers
+v0x241ba80_0 .net "out", 0 0, L_0x2b4da20; 1 drivers
+v0x2439f80_0 .net "out0", 0 0, L_0x2b4d5c0; 1 drivers
+v0x243d6f0_0 .net "out1", 0 0, L_0x2b4d700; 1 drivers
+v0x241e250_0 .net "out2", 0 0, L_0x2b4d7f0; 1 drivers
+v0x243ea60_0 .net "out3", 0 0, L_0x2b4d8e0; 1 drivers
+S_0x221bd90 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x221eab0;
+ .timescale -9 -12;
+L_0x2b4e250/d .functor NOT 1, L_0x2b4e700, C4<0>, C4<0>, C4<0>;
+L_0x2b4e250 .delay (10000,10000,10000) L_0x2b4e250/d;
+L_0x2b4e340/d .functor AND 1, L_0x2b4e7a0, L_0x2b4e250, C4<1>, C4<1>;
+L_0x2b4e340 .delay (20000,20000,20000) L_0x2b4e340/d;
+L_0x2b4e430/d .functor AND 1, L_0x2b4e890, L_0x2b4e700, C4<1>, C4<1>;
+L_0x2b4e430 .delay (20000,20000,20000) L_0x2b4e430/d;
+L_0x2b4e520/d .functor OR 1, L_0x2b4e340, L_0x2b4e430, C4<0>, C4<0>;
+L_0x2b4e520 .delay (20000,20000,20000) L_0x2b4e520/d;
+v0x247ef40_0 .net "S", 0 0, L_0x2b4e700; 1 drivers
+v0x2480ad0_0 .net "in0", 0 0, L_0x2b4e7a0; 1 drivers
+v0x247c530_0 .net "in1", 0 0, L_0x2b4e890; 1 drivers
+v0x2477880_0 .net "nS", 0 0, L_0x2b4e250; 1 drivers
+v0x2472bd0_0 .net "out0", 0 0, L_0x2b4e340; 1 drivers
+v0x245f3c0_0 .net "out1", 0 0, L_0x2b4e430; 1 drivers
+v0x245ae20_0 .net "outfinal", 0 0, L_0x2b4e520; 1 drivers
+S_0x2619900 .scope generate, "muxbits[23]" "muxbits[23]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1cee118 .param/l "i" 3 64, +C4<010111>;
+L_0x2b50a90/d .functor OR 1, L_0x2b52410, L_0x2b51500, C4<0>, C4<0>;
+L_0x2b50a90 .delay (20000,20000,20000) L_0x2b50a90/d;
+v0x24942c0_0 .net *"_s15", 0 0, L_0x2b52410; 1 drivers
+v0x248f610_0 .net *"_s16", 0 0, L_0x2b51500; 1 drivers
+S_0x263ce60 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2619900;
+ .timescale -9 -12;
+L_0x2b4ee30/d .functor NOT 1, L_0x2b4f730, C4<0>, C4<0>, C4<0>;
+L_0x2b4ee30 .delay (10000,10000,10000) L_0x2b4ee30/d;
+L_0x2b4ef20/d .functor NOT 1, L_0x2b4f860, C4<0>, C4<0>, C4<0>;
+L_0x2b4ef20 .delay (10000,10000,10000) L_0x2b4ef20/d;
+L_0x2b4efc0/d .functor NAND 1, L_0x2b4ee30, L_0x2b4ef20, L_0x2b4f990, C4<1>;
+L_0x2b4efc0 .delay (10000,10000,10000) L_0x2b4efc0/d;
+L_0x2b4f100/d .functor NAND 1, L_0x2b4f730, L_0x2b4ef20, L_0x2b4fa30, C4<1>;
+L_0x2b4f100 .delay (10000,10000,10000) L_0x2b4f100/d;
+L_0x2b4f1f0/d .functor NAND 1, L_0x2b4ee30, L_0x2b4f860, L_0x2b4fad0, C4<1>;
+L_0x2b4f1f0 .delay (10000,10000,10000) L_0x2b4f1f0/d;
+L_0x2b4f310/d .functor NAND 1, L_0x2b4f730, L_0x2b4f860, L_0x2b4fbc0, C4<1>;
+L_0x2b4f310 .delay (10000,10000,10000) L_0x2b4f310/d;
+L_0x2b4f480/d .functor NAND 1, L_0x2b4efc0, L_0x2b4f100, L_0x2b4f1f0, L_0x2b4f310;
+L_0x2b4f480 .delay (10000,10000,10000) L_0x2b4f480/d;
+v0x250d660_0 .net "S0", 0 0, L_0x2b4f730; 1 drivers
+v0x2510450_0 .net "S1", 0 0, L_0x2b4f860; 1 drivers
+v0x24bfed0_0 .net "in0", 0 0, L_0x2b4f990; 1 drivers
+v0x24c0050_0 .net "in1", 0 0, L_0x2b4fa30; 1 drivers
+v0x24c2b70_0 .net "in2", 0 0, L_0x2b4fad0; 1 drivers
+v0x24c5970_0 .net "in3", 0 0, L_0x2b4fbc0; 1 drivers
+v0x24c8770_0 .net "nS0", 0 0, L_0x2b4ee30; 1 drivers
+v0x24cb570_0 .net "nS1", 0 0, L_0x2b4ef20; 1 drivers
+v0x24ce370_0 .net "out", 0 0, L_0x2b4f480; 1 drivers
+v0x24d1190_0 .net "out0", 0 0, L_0x2b4efc0; 1 drivers
+v0x24d3fd0_0 .net "out1", 0 0, L_0x2b4f100; 1 drivers
+v0x249dc20_0 .net "out2", 0 0, L_0x2b4f1f0; 1 drivers
+v0x2498f70_0 .net "out3", 0 0, L_0x2b4f310; 1 drivers
+S_0x2637040 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2619900;
+ .timescale -9 -12;
+L_0x2b50c40/d .functor NOT 1, L_0x2b4fd40, C4<0>, C4<0>, C4<0>;
+L_0x2b50c40 .delay (10000,10000,10000) L_0x2b50c40/d;
+L_0x2b50cf0/d .functor NOT 1, L_0x2b4fe70, C4<0>, C4<0>, C4<0>;
+L_0x2b50cf0 .delay (10000,10000,10000) L_0x2b50cf0/d;
+L_0x2b50d90/d .functor NAND 1, L_0x2b50c40, L_0x2b50cf0, L_0x2b4ffa0, C4<1>;
+L_0x2b50d90 .delay (10000,10000,10000) L_0x2b50d90/d;
+L_0x2b50ed0/d .functor NAND 1, L_0x2b4fd40, L_0x2b50cf0, L_0x2b50040, C4<1>;
+L_0x2b50ed0 .delay (10000,10000,10000) L_0x2b50ed0/d;
+L_0x2b50fc0/d .functor NAND 1, L_0x2b50c40, L_0x2b4fe70, L_0x2b500e0, C4<1>;
+L_0x2b50fc0 .delay (10000,10000,10000) L_0x2b50fc0/d;
+L_0x2b510e0/d .functor NAND 1, L_0x2b4fd40, L_0x2b4fe70, L_0x2b501d0, C4<1>;
+L_0x2b510e0 .delay (10000,10000,10000) L_0x2b510e0/d;
+L_0x2b51250/d .functor NAND 1, L_0x2b50d90, L_0x2b50ed0, L_0x2b50fc0, L_0x2b510e0;
+L_0x2b51250 .delay (10000,10000,10000) L_0x2b51250/d;
+v0x24edce0_0 .net "S0", 0 0, L_0x2b4fd40; 1 drivers
+v0x24f0ab0_0 .net "S1", 0 0, L_0x2b4fe70; 1 drivers
+v0x24f38f0_0 .net "in0", 0 0, L_0x2b4ffa0; 1 drivers
+v0x24b7390_0 .net "in1", 0 0, L_0x2b50040; 1 drivers
+v0x24bd0d0_0 .net "in2", 0 0, L_0x2b500e0; 1 drivers
+v0x24f6730_0 .net "in3", 0 0, L_0x2b501d0; 1 drivers
+v0x24f9570_0 .net "nS0", 0 0, L_0x2b50c40; 1 drivers
+v0x24fc3b0_0 .net "nS1", 0 0, L_0x2b50cf0; 1 drivers
+v0x24ff1f0_0 .net "out", 0 0, L_0x2b51250; 1 drivers
+v0x2501e60_0 .net "out0", 0 0, L_0x2b50d90; 1 drivers
+v0x2504c60_0 .net "out1", 0 0, L_0x2b50ed0; 1 drivers
+v0x2507a60_0 .net "out2", 0 0, L_0x2b50fc0; 1 drivers
+v0x250a860_0 .net "out3", 0 0, L_0x2b510e0; 1 drivers
+S_0x261f720 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2619900;
+ .timescale -9 -12;
+L_0x2b502c0/d .functor NOT 1, L_0x2b50770, C4<0>, C4<0>, C4<0>;
+L_0x2b502c0 .delay (10000,10000,10000) L_0x2b502c0/d;
+L_0x2b503b0/d .functor AND 1, L_0x2b50810, L_0x2b502c0, C4<1>, C4<1>;
+L_0x2b503b0 .delay (20000,20000,20000) L_0x2b503b0/d;
+L_0x2b504a0/d .functor AND 1, L_0x2b50900, L_0x2b50770, C4<1>, C4<1>;
+L_0x2b504a0 .delay (20000,20000,20000) L_0x2b504a0/d;
+L_0x2b50590/d .functor OR 1, L_0x2b503b0, L_0x2b504a0, C4<0>, C4<0>;
+L_0x2b50590 .delay (20000,20000,20000) L_0x2b50590/d;
+v0x24d9c50_0 .net "S", 0 0, L_0x2b50770; 1 drivers
+v0x24dca90_0 .net "in0", 0 0, L_0x2b50810; 1 drivers
+v0x24df8d0_0 .net "in1", 0 0, L_0x2b50900; 1 drivers
+v0x24e24e0_0 .net "nS", 0 0, L_0x2b502c0; 1 drivers
+v0x24e52e0_0 .net "out0", 0 0, L_0x2b503b0; 1 drivers
+v0x24e80e0_0 .net "out1", 0 0, L_0x2b504a0; 1 drivers
+v0x24eaee0_0 .net "outfinal", 0 0, L_0x2b50590; 1 drivers
+S_0x25dea60 .scope generate, "muxbits[24]" "muxbits[24]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d23f68 .param/l "i" 3 64, +C4<011000>;
+L_0x2b537c0/d .functor OR 1, L_0x2b53900, L_0x2b539a0, C4<0>, C4<0>;
+L_0x2b537c0 .delay (20000,20000,20000) L_0x2b537c0/d;
+v0x24d6e10_0 .net *"_s15", 0 0, L_0x2b53900; 1 drivers
+v0x24ba290_0 .net *"_s16", 0 0, L_0x2b539a0; 1 drivers
+S_0x2613ae0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x25dea60;
+ .timescale -9 -12;
+L_0x2b515f0/d .functor NOT 1, L_0x2b51ef0, C4<0>, C4<0>, C4<0>;
+L_0x2b515f0 .delay (10000,10000,10000) L_0x2b515f0/d;
+L_0x2b516e0/d .functor NOT 1, L_0x2b52020, C4<0>, C4<0>, C4<0>;
+L_0x2b516e0 .delay (10000,10000,10000) L_0x2b516e0/d;
+L_0x2b51780/d .functor NAND 1, L_0x2b515f0, L_0x2b516e0, L_0x2b52150, C4<1>;
+L_0x2b51780 .delay (10000,10000,10000) L_0x2b51780/d;
+L_0x2b518c0/d .functor NAND 1, L_0x2b51ef0, L_0x2b516e0, L_0x2b521f0, C4<1>;
+L_0x2b518c0 .delay (10000,10000,10000) L_0x2b518c0/d;
+L_0x2b519b0/d .functor NAND 1, L_0x2b515f0, L_0x2b52020, L_0x2b52290, C4<1>;
+L_0x2b519b0 .delay (10000,10000,10000) L_0x2b519b0/d;
+L_0x2b51ad0/d .functor NAND 1, L_0x2b51ef0, L_0x2b52020, L_0x2b53400, C4<1>;
+L_0x2b51ad0 .delay (10000,10000,10000) L_0x2b51ad0/d;
+L_0x2b51c40/d .functor NAND 1, L_0x2b51780, L_0x2b518c0, L_0x2b519b0, L_0x2b51ad0;
+L_0x2b51c40 .delay (10000,10000,10000) L_0x2b51c40/d;
+v0x24f4610_0 .net "S0", 0 0, L_0x2b51ef0; 1 drivers
+v0x24f17d0_0 .net "S1", 0 0, L_0x2b52020; 1 drivers
+v0x24dffe0_0 .net "in0", 0 0, L_0x2b52150; 1 drivers
+v0x24e0160_0 .net "in1", 0 0, L_0x2b521f0; 1 drivers
+v0x24dd7b0_0 .net "in2", 0 0, L_0x2b52290; 1 drivers
+v0x24da970_0 .net "in3", 0 0, L_0x2b53400; 1 drivers
+v0x24d7b30_0 .net "nS0", 0 0, L_0x2b515f0; 1 drivers
+v0x24d4cf0_0 .net "nS1", 0 0, L_0x2b516e0; 1 drivers
+v0x24d1eb0_0 .net "out", 0 0, L_0x2b51c40; 1 drivers
+v0x24bddf0_0 .net "out0", 0 0, L_0x2b51780; 1 drivers
+v0x24bafb0_0 .net "out1", 0 0, L_0x2b518c0; 1 drivers
+v0x24b8170_0 .net "out2", 0 0, L_0x2b519b0; 1 drivers
+v0x24b7020_0 .net "out3", 0 0, L_0x2b51ad0; 1 drivers
+S_0x25fc1c0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x25dea60;
+ .timescale -9 -12;
+L_0x2b51b60/d .functor NOT 1, L_0x2b52d70, C4<0>, C4<0>, C4<0>;
+L_0x2b51b60 .delay (10000,10000,10000) L_0x2b51b60/d;
+L_0x2b52500/d .functor NOT 1, L_0x2b52ea0, C4<0>, C4<0>, C4<0>;
+L_0x2b52500 .delay (10000,10000,10000) L_0x2b52500/d;
+L_0x2b525a0/d .functor NAND 1, L_0x2b51b60, L_0x2b52500, L_0x2b52fd0, C4<1>;
+L_0x2b525a0 .delay (10000,10000,10000) L_0x2b525a0/d;
+L_0x2b526e0/d .functor NAND 1, L_0x2b52d70, L_0x2b52500, L_0x2b53070, C4<1>;
+L_0x2b526e0 .delay (10000,10000,10000) L_0x2b526e0/d;
+L_0x2b52800/d .functor NAND 1, L_0x2b51b60, L_0x2b52ea0, L_0x2b53110, C4<1>;
+L_0x2b52800 .delay (10000,10000,10000) L_0x2b52800/d;
+L_0x2b52950/d .functor NAND 1, L_0x2b52d70, L_0x2b52ea0, L_0x2b53200, C4<1>;
+L_0x2b52950 .delay (10000,10000,10000) L_0x2b52950/d;
+L_0x2b52ac0/d .functor NAND 1, L_0x2b525a0, L_0x2b526e0, L_0x2b52800, L_0x2b52950;
+L_0x2b52ac0 .delay (10000,10000,10000) L_0x2b52ac0/d;
+v0x25181e0_0 .net "S0", 0 0, L_0x2b52d70; 1 drivers
+v0x25197a0_0 .net "S1", 0 0, L_0x2b52ea0; 1 drivers
+v0x251ad60_0 .net "in0", 0 0, L_0x2b52fd0; 1 drivers
+v0x251c320_0 .net "in1", 0 0, L_0x2b53070; 1 drivers
+v0x251d8e0_0 .net "in2", 0 0, L_0x2b53110; 1 drivers
+v0x251eea0_0 .net "in3", 0 0, L_0x2b53200; 1 drivers
+v0x2515660_0 .net "nS0", 0 0, L_0x2b51b60; 1 drivers
+v0x2531f40_0 .net "nS1", 0 0, L_0x2b52500; 1 drivers
+v0x2533500_0 .net "out", 0 0, L_0x2b52ac0; 1 drivers
+v0x24fff10_0 .net "out0", 0 0, L_0x2b525a0; 1 drivers
+v0x24fd0d0_0 .net "out1", 0 0, L_0x2b526e0; 1 drivers
+v0x24fa290_0 .net "out2", 0 0, L_0x2b52800; 1 drivers
+v0x24f7450_0 .net "out3", 0 0, L_0x2b52950; 1 drivers
+S_0x25f63a0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x25dea60;
+ .timescale -9 -12;
+L_0x2b532f0/d .functor NOT 1, L_0x2b534a0, C4<0>, C4<0>, C4<0>;
+L_0x2b532f0 .delay (10000,10000,10000) L_0x2b532f0/d;
+L_0x2b54430/d .functor AND 1, L_0x2b53540, L_0x2b532f0, C4<1>, C4<1>;
+L_0x2b54430 .delay (20000,20000,20000) L_0x2b54430/d;
+L_0x2b54520/d .functor AND 1, L_0x2b53630, L_0x2b534a0, C4<1>, C4<1>;
+L_0x2b54520 .delay (20000,20000,20000) L_0x2b54520/d;
+L_0x2b54610/d .functor OR 1, L_0x2b54430, L_0x2b54520, C4<0>, C4<0>;
+L_0x2b54610 .delay (20000,20000,20000) L_0x2b54610/d;
+v0x2536080_0 .net "S", 0 0, L_0x2b534a0; 1 drivers
+v0x2537640_0 .net "in0", 0 0, L_0x2b53540; 1 drivers
+v0x2538c00_0 .net "in1", 0 0, L_0x2b53630; 1 drivers
+v0x253a1c0_0 .net "nS", 0 0, L_0x2b532f0; 1 drivers
+v0x2516c20_0 .net "out0", 0 0, L_0x2b54430; 1 drivers
+v0x253b780_0 .net "out1", 0 0, L_0x2b54520; 1 drivers
+v0x253cd40_0 .net "outfinal", 0 0, L_0x2b54610; 1 drivers
+S_0x25bb500 .scope generate, "muxbits[25]" "muxbits[25]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d23478 .param/l "i" 3 64, +C4<011001>;
+L_0x2b56200/d .functor OR 1, L_0x2b56340, L_0x2b563e0, C4<0>, C4<0>;
+L_0x2b56200 .delay (20000,20000,20000) L_0x2b56200/d;
+v0x2369b00_0 .net *"_s15", 0 0, L_0x2b56340; 1 drivers
+v0x2534ac0_0 .net *"_s16", 0 0, L_0x2b563e0; 1 drivers
+S_0x25d8c40 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x25bb500;
+ .timescale -9 -12;
+L_0x2b53a90/d .functor NOT 1, L_0x2b54390, C4<0>, C4<0>, C4<0>;
+L_0x2b53a90 .delay (10000,10000,10000) L_0x2b53a90/d;
+L_0x2b53b80/d .functor NOT 1, L_0x2b547f0, C4<0>, C4<0>, C4<0>;
+L_0x2b53b80 .delay (10000,10000,10000) L_0x2b53b80/d;
+L_0x2b53c20/d .functor NAND 1, L_0x2b53a90, L_0x2b53b80, L_0x2b54920, C4<1>;
+L_0x2b53c20 .delay (10000,10000,10000) L_0x2b53c20/d;
+L_0x2b53d60/d .functor NAND 1, L_0x2b54390, L_0x2b53b80, L_0x2b549c0, C4<1>;
+L_0x2b53d60 .delay (10000,10000,10000) L_0x2b53d60/d;
+L_0x2b53e50/d .functor NAND 1, L_0x2b53a90, L_0x2b547f0, L_0x2b54a60, C4<1>;
+L_0x2b53e50 .delay (10000,10000,10000) L_0x2b53e50/d;
+L_0x2b53f70/d .functor NAND 1, L_0x2b54390, L_0x2b547f0, L_0x2b54b50, C4<1>;
+L_0x2b53f70 .delay (10000,10000,10000) L_0x2b53f70/d;
+L_0x2b540e0/d .functor NAND 1, L_0x2b53c20, L_0x2b53d60, L_0x2b53e50, L_0x2b53f70;
+L_0x2b540e0 .delay (10000,10000,10000) L_0x2b540e0/d;
+v0x23aca30_0 .net "S0", 0 0, L_0x2b54390; 1 drivers
+v0x23a6de0_0 .net "S1", 0 0, L_0x2b547f0; 1 drivers
+v0x23a8e20_0 .net "in0", 0 0, L_0x2b54920; 1 drivers
+v0x23a1190_0 .net "in1", 0 0, L_0x2b549c0; 1 drivers
+v0x23a31d0_0 .net "in2", 0 0, L_0x2b54a60; 1 drivers
+v0x238a2d0_0 .net "in3", 0 0, L_0x2b54b50; 1 drivers
+v0x238c310_0 .net "nS0", 0 0, L_0x2b53a90; 1 drivers
+v0x2384680_0 .net "nS1", 0 0, L_0x2b53b80; 1 drivers
+v0x23866c0_0 .net "out", 0 0, L_0x2b540e0; 1 drivers
+v0x237ea30_0 .net "out0", 0 0, L_0x2b53c20; 1 drivers
+v0x2380a70_0 .net "out1", 0 0, L_0x2b53d60; 1 drivers
+v0x23679f0_0 .net "out2", 0 0, L_0x2b53e50; 1 drivers
+v0x236b280_0 .net "out3", 0 0, L_0x2b53f70; 1 drivers
+S_0x25d2e20 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x25bb500;
+ .timescale -9 -12;
+L_0x2b54c40/d .functor NOT 1, L_0x2b55540, C4<0>, C4<0>, C4<0>;
+L_0x2b54c40 .delay (10000,10000,10000) L_0x2b54c40/d;
+L_0x2b54d30/d .functor NOT 1, L_0x2b55670, C4<0>, C4<0>, C4<0>;
+L_0x2b54d30 .delay (10000,10000,10000) L_0x2b54d30/d;
+L_0x2b54dd0/d .functor NAND 1, L_0x2b54c40, L_0x2b54d30, L_0x2b56870, C4<1>;
+L_0x2b54dd0 .delay (10000,10000,10000) L_0x2b54dd0/d;
+L_0x2b54f10/d .functor NAND 1, L_0x2b55540, L_0x2b54d30, L_0x2b56910, C4<1>;
+L_0x2b54f10 .delay (10000,10000,10000) L_0x2b54f10/d;
+L_0x2b55000/d .functor NAND 1, L_0x2b54c40, L_0x2b55670, L_0x2b55850, C4<1>;
+L_0x2b55000 .delay (10000,10000,10000) L_0x2b55000/d;
+L_0x2b55120/d .functor NAND 1, L_0x2b55540, L_0x2b55670, L_0x2b55940, C4<1>;
+L_0x2b55120 .delay (10000,10000,10000) L_0x2b55120/d;
+L_0x2b55290/d .functor NAND 1, L_0x2b54dd0, L_0x2b54f10, L_0x2b55000, L_0x2b55120;
+L_0x2b55290 .delay (10000,10000,10000) L_0x2b55290/d;
+v0x2642c70_0 .net "S0", 0 0, L_0x2b55540; 1 drivers
+v0x25a3bb0_0 .net "S1", 0 0, L_0x2b55670; 1 drivers
+v0x240cfa0_0 .net "in0", 0 0, L_0x2b56870; 1 drivers
+v0x2407140_0 .net "in1", 0 0, L_0x2b56910; 1 drivers
+v0x24012e0_0 .net "in2", 0 0, L_0x2b55850; 1 drivers
+v0x23e9a20_0 .net "in3", 0 0, L_0x2b55940; 1 drivers
+v0x23e0380_0 .net "nS0", 0 0, L_0x2b54c40; 1 drivers
+v0x23e3bc0_0 .net "nS1", 0 0, L_0x2b54d30; 1 drivers
+v0x23c9510_0 .net "out", 0 0, L_0x2b55290; 1 drivers
+v0x23cb550_0 .net "out0", 0 0, L_0x2b54dd0; 1 drivers
+v0x23c38c0_0 .net "out1", 0 0, L_0x2b54f10; 1 drivers
+v0x23c5900_0 .net "out2", 0 0, L_0x2b55000; 1 drivers
+v0x23bfcb0_0 .net "out3", 0 0, L_0x2b55120; 1 drivers
+S_0x25c1320 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x25bb500;
+ .timescale -9 -12;
+L_0x2b55a30/d .functor NOT 1, L_0x2b55ee0, C4<0>, C4<0>, C4<0>;
+L_0x2b55a30 .delay (10000,10000,10000) L_0x2b55a30/d;
+L_0x2b55b20/d .functor AND 1, L_0x2b55f80, L_0x2b55a30, C4<1>, C4<1>;
+L_0x2b55b20 .delay (20000,20000,20000) L_0x2b55b20/d;
+L_0x2b55c10/d .functor AND 1, L_0x2b56070, L_0x2b55ee0, C4<1>, C4<1>;
+L_0x2b55c10 .delay (20000,20000,20000) L_0x2b55c10/d;
+L_0x2b55d00/d .functor OR 1, L_0x2b55b20, L_0x2b55c10, C4<0>, C4<0>;
+L_0x2b55d00 .delay (20000,20000,20000) L_0x2b55d00/d;
+v0x25f0530_0 .net "S", 0 0, L_0x2b55ee0; 1 drivers
+v0x2601fe0_0 .net "in0", 0 0, L_0x2b55f80; 1 drivers
+v0x2607e10_0 .net "in1", 0 0, L_0x2b56070; 1 drivers
+v0x260dc70_0 .net "nS", 0 0, L_0x2b55a30; 1 drivers
+v0x2625530_0 .net "out0", 0 0, L_0x2b55b20; 1 drivers
+v0x262b390_0 .net "out1", 0 0, L_0x2b55c10; 1 drivers
+v0x26311f0_0 .net "outfinal", 0 0, L_0x2b55d00; 1 drivers
+S_0x2646500 .scope generate, "muxbits[26]" "muxbits[26]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d3b9c8 .param/l "i" 3 64, +C4<011010>;
+L_0x2b58a00/d .functor OR 1, L_0x2b58b40, L_0x2b58be0, C4<0>, C4<0>;
+L_0x2b58a00 .delay (20000,20000,20000) L_0x2b58a00/d;
+v0x25e4870_0 .net *"_s15", 0 0, L_0x2b58b40; 1 drivers
+v0x25ea6d0_0 .net *"_s16", 0 0, L_0x2b58be0; 1 drivers
+S_0x25b56e0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2646500;
+ .timescale -9 -12;
+L_0x2b564d0/d .functor NOT 1, L_0x2b569b0, C4<0>, C4<0>, C4<0>;
+L_0x2b564d0 .delay (10000,10000,10000) L_0x2b564d0/d;
+L_0x2b565c0/d .functor NOT 1, L_0x2b56ae0, C4<0>, C4<0>, C4<0>;
+L_0x2b565c0 .delay (10000,10000,10000) L_0x2b565c0/d;
+L_0x2b56660/d .functor NAND 1, L_0x2b564d0, L_0x2b565c0, L_0x2b56c10, C4<1>;
+L_0x2b56660 .delay (10000,10000,10000) L_0x2b56660/d;
+L_0x2b567a0/d .functor NAND 1, L_0x2b569b0, L_0x2b565c0, L_0x2b56cb0, C4<1>;
+L_0x2b567a0 .delay (10000,10000,10000) L_0x2b567a0/d;
+L_0x2b57a70/d .functor NAND 1, L_0x2b564d0, L_0x2b56ae0, L_0x2b56d50, C4<1>;
+L_0x2b57a70 .delay (10000,10000,10000) L_0x2b57a70/d;
+L_0x2b57b90/d .functor NAND 1, L_0x2b569b0, L_0x2b56ae0, L_0x2b56e40, C4<1>;
+L_0x2b57b90 .delay (10000,10000,10000) L_0x2b57b90/d;
+L_0x2b57d00/d .functor NAND 1, L_0x2b56660, L_0x2b567a0, L_0x2b57a70, L_0x2b57b90;
+L_0x2b57d00 .delay (10000,10000,10000) L_0x2b57d00/d;
+v0x2659670_0 .net "S0", 0 0, L_0x2b569b0; 1 drivers
+v0x265abb0_0 .net "S1", 0 0, L_0x2b56ae0; 1 drivers
+v0x265e320_0 .net "in0", 0 0, L_0x2b56c10; 1 drivers
+v0x265f860_0 .net "in1", 0 0, L_0x2b56cb0; 1 drivers
+v0x2647850_0 .net "in2", 0 0, L_0x2b56d50; 1 drivers
+v0x2662ed0_0 .net "in3", 0 0, L_0x2b56e40; 1 drivers
+v0x20b5e10_0 .net "nS0", 0 0, L_0x2b564d0; 1 drivers
+v0x20b6230_0 .net "nS1", 0 0, L_0x2b565c0; 1 drivers
+v0x25a9a10_0 .net "out", 0 0, L_0x2b57d00; 1 drivers
+v0x25af870_0 .net "out0", 0 0, L_0x2b56660; 1 drivers
+v0x2592150_0 .net "out1", 0 0, L_0x2b567a0; 1 drivers
+v0x25c7150_0 .net "out2", 0 0, L_0x2b57a70; 1 drivers
+v0x25ccfb0_0 .net "out3", 0 0, L_0x2b57b90; 1 drivers
+S_0x259dda0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2646500;
+ .timescale -9 -12;
+L_0x2b56f30/d .functor NOT 1, L_0x2b57830, C4<0>, C4<0>, C4<0>;
+L_0x2b56f30 .delay (10000,10000,10000) L_0x2b56f30/d;
+L_0x2b57020/d .functor NOT 1, L_0x2b57960, C4<0>, C4<0>, C4<0>;
+L_0x2b57020 .delay (10000,10000,10000) L_0x2b57020/d;
+L_0x2b570c0/d .functor NAND 1, L_0x2b56f30, L_0x2b57020, L_0x2b59100, C4<1>;
+L_0x2b570c0 .delay (10000,10000,10000) L_0x2b570c0/d;
+L_0x2b57200/d .functor NAND 1, L_0x2b57830, L_0x2b57020, L_0x2b57fb0, C4<1>;
+L_0x2b57200 .delay (10000,10000,10000) L_0x2b57200/d;
+L_0x2b572f0/d .functor NAND 1, L_0x2b56f30, L_0x2b57960, L_0x2b58050, C4<1>;
+L_0x2b572f0 .delay (10000,10000,10000) L_0x2b572f0/d;
+L_0x2b57410/d .functor NAND 1, L_0x2b57830, L_0x2b57960, L_0x2b58140, C4<1>;
+L_0x2b57410 .delay (10000,10000,10000) L_0x2b57410/d;
+L_0x2b57580/d .functor NAND 1, L_0x2b570c0, L_0x2b57200, L_0x2b572f0, L_0x2b57410;
+L_0x2b57580 .delay (10000,10000,10000) L_0x2b57580/d;
+v0x26c3b30_0 .net "S0", 0 0, L_0x2b57830; 1 drivers
+v0x26c7320_0 .net "S1", 0 0, L_0x2b57960; 1 drivers
+v0x26c87b0_0 .net "in0", 0 0, L_0x2b59100; 1 drivers
+v0x26cbf90_0 .net "in1", 0 0, L_0x2b57fb0; 1 drivers
+v0x26cd420_0 .net "in2", 0 0, L_0x2b58050; 1 drivers
+v0x26d0c00_0 .net "in3", 0 0, L_0x2b58140; 1 drivers
+v0x26d2090_0 .net "nS0", 0 0, L_0x2b56f30; 1 drivers
+v0x26d58a0_0 .net "nS1", 0 0, L_0x2b57020; 1 drivers
+v0x26d6de0_0 .net "out", 0 0, L_0x2b57580; 1 drivers
+v0x26549c0_0 .net "out0", 0 0, L_0x2b570c0; 1 drivers
+v0x26db140_0 .net "out1", 0 0, L_0x2b57200; 1 drivers
+v0x26df250_0 .net "out2", 0 0, L_0x2b572f0; 1 drivers
+v0x2655f00_0 .net "out3", 0 0, L_0x2b57410; 1 drivers
+S_0x2597f80 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2646500;
+ .timescale -9 -12;
+L_0x2b58230/d .functor NOT 1, L_0x2b586e0, C4<0>, C4<0>, C4<0>;
+L_0x2b58230 .delay (10000,10000,10000) L_0x2b58230/d;
+L_0x2b58320/d .functor AND 1, L_0x2b58780, L_0x2b58230, C4<1>, C4<1>;
+L_0x2b58320 .delay (20000,20000,20000) L_0x2b58320/d;
+L_0x2b58410/d .functor AND 1, L_0x2b58870, L_0x2b586e0, C4<1>, C4<1>;
+L_0x2b58410 .delay (20000,20000,20000) L_0x2b58410/d;
+L_0x2b58500/d .functor OR 1, L_0x2b58320, L_0x2b58410, C4<0>, C4<0>;
+L_0x2b58500 .delay (20000,20000,20000) L_0x2b58500/d;
+v0x26b8e60_0 .net "S", 0 0, L_0x2b586e0; 1 drivers
+v0x26ba3a0_0 .net "in0", 0 0, L_0x2b58780; 1 drivers
+v0x26bdb10_0 .net "in1", 0 0, L_0x2b58870; 1 drivers
+v0x26bf050_0 .net "nS", 0 0, L_0x2b58230; 1 drivers
+v0x26511b0_0 .net "out0", 0 0, L_0x2b58320; 1 drivers
+v0x26c2490_0 .net "out1", 0 0, L_0x2b58410; 1 drivers
+v0x26c2690_0 .net "outfinal", 0 0, L_0x2b58500; 1 drivers
+S_0x2412990 .scope generate, "muxbits[27]" "muxbits[27]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d3aa88 .param/l "i" 3 64, +C4<011011>;
+L_0x2b5b0f0/d .functor OR 1, L_0x2b5b230, L_0x2b5b2d0, C4<0>, C4<0>;
+L_0x2b5b0f0 .delay (20000,20000,20000) L_0x2b5b0f0/d;
+v0x26b41b0_0 .net *"_s15", 0 0, L_0x2b5b230; 1 drivers
+v0x26b56f0_0 .net *"_s16", 0 0, L_0x2b5b2d0; 1 drivers
+S_0x26dc600 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x2412990;
+ .timescale -9 -12;
+L_0x2b58cd0/d .functor NOT 1, L_0x2b5a850, C4<0>, C4<0>, C4<0>;
+L_0x2b58cd0 .delay (10000,10000,10000) L_0x2b58cd0/d;
+L_0x2b58dc0/d .functor NOT 1, L_0x2b591a0, C4<0>, C4<0>, C4<0>;
+L_0x2b58dc0 .delay (10000,10000,10000) L_0x2b58dc0/d;
+L_0x2b58e60/d .functor NAND 1, L_0x2b58cd0, L_0x2b58dc0, L_0x2b592d0, C4<1>;
+L_0x2b58e60 .delay (10000,10000,10000) L_0x2b58e60/d;
+L_0x2b58fa0/d .functor NAND 1, L_0x2b5a850, L_0x2b58dc0, L_0x2b59370, C4<1>;
+L_0x2b58fa0 .delay (10000,10000,10000) L_0x2b58fa0/d;
+L_0x2b5a310/d .functor NAND 1, L_0x2b58cd0, L_0x2b591a0, L_0x2b59410, C4<1>;
+L_0x2b5a310 .delay (10000,10000,10000) L_0x2b5a310/d;
+L_0x2b5a430/d .functor NAND 1, L_0x2b5a850, L_0x2b591a0, L_0x2b59500, C4<1>;
+L_0x2b5a430 .delay (10000,10000,10000) L_0x2b5a430/d;
+L_0x2b5a5a0/d .functor NAND 1, L_0x2b58e60, L_0x2b58fa0, L_0x2b5a310, L_0x2b5a430;
+L_0x2b5a5a0 .delay (10000,10000,10000) L_0x2b5a5a0/d;
+v0x2697760_0 .net "S0", 0 0, L_0x2b5a850; 1 drivers
+v0x2698ca0_0 .net "S1", 0 0, L_0x2b591a0; 1 drivers
+v0x269c410_0 .net "in0", 0 0, L_0x2b592d0; 1 drivers
+v0x269d950_0 .net "in1", 0 0, L_0x2b59370; 1 drivers
+v0x26a10c0_0 .net "in2", 0 0, L_0x2b59410; 1 drivers
+v0x26a2460_0 .net "in3", 0 0, L_0x2b59500; 1 drivers
+v0x26a5c40_0 .net "nS0", 0 0, L_0x2b58cd0; 1 drivers
+v0x26a70d0_0 .net "nS1", 0 0, L_0x2b58dc0; 1 drivers
+v0x26aa8b0_0 .net "out", 0 0, L_0x2b5a5a0; 1 drivers
+v0x264fd20_0 .net "out0", 0 0, L_0x2b58e60; 1 drivers
+v0x26abd40_0 .net "out1", 0 0, L_0x2b58fa0; 1 drivers
+v0x26af520_0 .net "out2", 0 0, L_0x2b5a310; 1 drivers
+v0x26b09b0_0 .net "out3", 0 0, L_0x2b5a430; 1 drivers
+S_0x27b6250 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x2412990;
+ .timescale -9 -12;
+L_0x2b595f0/d .functor NOT 1, L_0x2b59ef0, C4<0>, C4<0>, C4<0>;
+L_0x2b595f0 .delay (10000,10000,10000) L_0x2b595f0/d;
+L_0x2b596e0/d .functor NOT 1, L_0x2b5a020, C4<0>, C4<0>, C4<0>;
+L_0x2b596e0 .delay (10000,10000,10000) L_0x2b596e0/d;
+L_0x2b59780/d .functor NAND 1, L_0x2b595f0, L_0x2b596e0, L_0x2b5a150, C4<1>;
+L_0x2b59780 .delay (10000,10000,10000) L_0x2b59780/d;
+L_0x2b598c0/d .functor NAND 1, L_0x2b59ef0, L_0x2b596e0, L_0x2b5a1f0, C4<1>;
+L_0x2b598c0 .delay (10000,10000,10000) L_0x2b598c0/d;
+L_0x2b599b0/d .functor NAND 1, L_0x2b595f0, L_0x2b5a020, L_0x2b5bb00, C4<1>;
+L_0x2b599b0 .delay (10000,10000,10000) L_0x2b599b0/d;
+L_0x2b59ad0/d .functor NAND 1, L_0x2b59ef0, L_0x2b5a020, L_0x2b5bbf0, C4<1>;
+L_0x2b59ad0 .delay (10000,10000,10000) L_0x2b59ad0/d;
+L_0x2b59c40/d .functor NAND 1, L_0x2b59780, L_0x2b598c0, L_0x2b599b0, L_0x2b59ad0;
+L_0x2b59c40 .delay (10000,10000,10000) L_0x2b59c40/d;
+v0x267c2b0_0 .net "S0", 0 0, L_0x2b59ef0; 1 drivers
+v0x267fa20_0 .net "S1", 0 0, L_0x2b5a020; 1 drivers
+v0x2646290_0 .net "in0", 0 0, L_0x2b5a150; 1 drivers
+v0x2680f60_0 .net "in1", 0 0, L_0x2b5a1f0; 1 drivers
+v0x2684590_0 .net "in2", 0 0, L_0x2b5bb00; 1 drivers
+v0x2685a20_0 .net "in3", 0 0, L_0x2b5bbf0; 1 drivers
+v0x2689200_0 .net "nS0", 0 0, L_0x2b595f0; 1 drivers
+v0x268a690_0 .net "nS1", 0 0, L_0x2b596e0; 1 drivers
+v0x268de70_0 .net "out", 0 0, L_0x2b59c40; 1 drivers
+v0x268f300_0 .net "out0", 0 0, L_0x2b59780; 1 drivers
+v0x264c540_0 .net "out1", 0 0, L_0x2b598c0; 1 drivers
+v0x2692ab0_0 .net "out2", 0 0, L_0x2b599b0; 1 drivers
+v0x2693ff0_0 .net "out3", 0 0, L_0x2b59ad0; 1 drivers
+S_0x24187b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x2412990;
+ .timescale -9 -12;
+L_0x2b59b60/d .functor NOT 1, L_0x2b5add0, C4<0>, C4<0>, C4<0>;
+L_0x2b59b60 .delay (10000,10000,10000) L_0x2b59b60/d;
+L_0x2b5aa10/d .functor AND 1, L_0x2b5ae70, L_0x2b59b60, C4<1>, C4<1>;
+L_0x2b5aa10 .delay (20000,20000,20000) L_0x2b5aa10/d;
+L_0x2b5ab00/d .functor AND 1, L_0x2b5af60, L_0x2b5add0, C4<1>, C4<1>;
+L_0x2b5ab00 .delay (20000,20000,20000) L_0x2b5ab00/d;
+L_0x2b5abf0/d .functor OR 1, L_0x2b5aa10, L_0x2b5ab00, C4<0>, C4<0>;
+L_0x2b5abf0 .delay (20000,20000,20000) L_0x2b5abf0/d;
+v0x266dc60_0 .net "S", 0 0, L_0x2b5add0; 1 drivers
+v0x2671440_0 .net "in0", 0 0, L_0x2b5ae70; 1 drivers
+v0x2672950_0 .net "in1", 0 0, L_0x2b5af60; 1 drivers
+v0x26760c0_0 .net "nS", 0 0, L_0x2b59b60; 1 drivers
+v0x2677600_0 .net "out0", 0 0, L_0x2b5aa10; 1 drivers
+v0x267ad70_0 .net "out1", 0 0, L_0x2b5ab00; 1 drivers
+v0x264b0b0_0 .net "outfinal", 0 0, L_0x2b5abf0; 1 drivers
+S_0x23ddaa0 .scope generate, "muxbits[28]" "muxbits[28]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d2f118 .param/l "i" 3 64, +C4<011100>;
+L_0x2b5d940/d .functor OR 1, L_0x2b5da80, L_0x2b5db20, C4<0>, C4<0>;
+L_0x2b5d940 .delay (20000,20000,20000) L_0x2b5d940/d;
+v0x2668ff0_0 .net *"_s15", 0 0, L_0x2b5da80; 1 drivers
+v0x266c7d0_0 .net *"_s16", 0 0, L_0x2b5db20; 1 drivers
+S_0x23fb050 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x23ddaa0;
+ .timescale -9 -12;
+L_0x2b5b3c0/d .functor NOT 1, L_0x2b5bce0, C4<0>, C4<0>, C4<0>;
+L_0x2b5b3c0 .delay (10000,10000,10000) L_0x2b5b3c0/d;
+L_0x2b5b4b0/d .functor NOT 1, L_0x2b5be10, C4<0>, C4<0>, C4<0>;
+L_0x2b5b4b0 .delay (10000,10000,10000) L_0x2b5b4b0/d;
+L_0x2b5b550/d .functor NAND 1, L_0x2b5b3c0, L_0x2b5b4b0, L_0x2b5bf40, C4<1>;
+L_0x2b5b550 .delay (10000,10000,10000) L_0x2b5b550/d;
+L_0x2b5b690/d .functor NAND 1, L_0x2b5bce0, L_0x2b5b4b0, L_0x2b5bfe0, C4<1>;
+L_0x2b5b690 .delay (10000,10000,10000) L_0x2b5b690/d;
+L_0x2b5b7b0/d .functor NAND 1, L_0x2b5b3c0, L_0x2b5be10, L_0x2b5c080, C4<1>;
+L_0x2b5b7b0 .delay (10000,10000,10000) L_0x2b5b7b0/d;
+L_0x2b5b900/d .functor NAND 1, L_0x2b5bce0, L_0x2b5be10, L_0x2b5c170, C4<1>;
+L_0x2b5b900 .delay (10000,10000,10000) L_0x2b5b900/d;
+L_0x2b5ba70/d .functor NAND 1, L_0x2b5b550, L_0x2b5b690, L_0x2b5b7b0, L_0x2b5b900;
+L_0x2b5ba70 .delay (10000,10000,10000) L_0x2b5ba70/d;
+v0x2698480_0 .net "S0", 0 0, L_0x2b5bce0; 1 drivers
+v0x26937d0_0 .net "S1", 0 0, L_0x2b5be10; 1 drivers
+v0x2680740_0 .net "in0", 0 0, L_0x2b5bf40; 1 drivers
+v0x2682110_0 .net "in1", 0 0, L_0x2b5bfe0; 1 drivers
+v0x267ba90_0 .net "in2", 0 0, L_0x2b5c080; 1 drivers
+v0x2676de0_0 .net "in3", 0 0, L_0x2b5c170; 1 drivers
+v0x2672130_0 .net "nS0", 0 0, L_0x2b5b3c0; 1 drivers
+v0x26635f0_0 .net "nS1", 0 0, L_0x2b5b4b0; 1 drivers
+v0x265f040_0 .net "out", 0 0, L_0x2b5ba70; 1 drivers
+v0x265a390_0 .net "out0", 0 0, L_0x2b5b550; 1 drivers
+v0x26556e0_0 .net "out1", 0 0, L_0x2b5b690; 1 drivers
+v0x2664370_0 .net "out2", 0 0, L_0x2b5b7b0; 1 drivers
+v0x2667b60_0 .net "out3", 0 0, L_0x2b5b900; 1 drivers
+S_0x23f5230 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x23ddaa0;
+ .timescale -9 -12;
+L_0x2b5c260/d .functor NOT 1, L_0x2b5cb60, C4<0>, C4<0>, C4<0>;
+L_0x2b5c260 .delay (10000,10000,10000) L_0x2b5c260/d;
+L_0x2b5c350/d .functor NOT 1, L_0x2b5cc90, C4<0>, C4<0>, C4<0>;
+L_0x2b5c350 .delay (10000,10000,10000) L_0x2b5c350/d;
+L_0x2b5c3f0/d .functor NAND 1, L_0x2b5c260, L_0x2b5c350, L_0x2b5cdc0, C4<1>;
+L_0x2b5c3f0 .delay (10000,10000,10000) L_0x2b5c3f0/d;
+L_0x2b5c530/d .functor NAND 1, L_0x2b5cb60, L_0x2b5c350, L_0x2b5e2e0, C4<1>;
+L_0x2b5c530 .delay (10000,10000,10000) L_0x2b5c530/d;
+L_0x2b5c620/d .functor NAND 1, L_0x2b5c260, L_0x2b5cc90, L_0x2b5e380, C4<1>;
+L_0x2b5c620 .delay (10000,10000,10000) L_0x2b5c620/d;
+L_0x2b5c740/d .functor NAND 1, L_0x2b5cb60, L_0x2b5cc90, L_0x2b5d0c0, C4<1>;
+L_0x2b5c740 .delay (10000,10000,10000) L_0x2b5c740/d;
+L_0x2b5c8b0/d .functor NAND 1, L_0x2b5c3f0, L_0x2b5c530, L_0x2b5c620, L_0x2b5c740;
+L_0x2b5c8b0 .delay (10000,10000,10000) L_0x2b5c8b0/d;
+v0x26efec0_0 .net "S0", 0 0, L_0x2b5cb60; 1 drivers
+v0x26f2cc0_0 .net "S1", 0 0, L_0x2b5cc90; 1 drivers
+v0x26f5ad0_0 .net "in0", 0 0, L_0x2b5cdc0; 1 drivers
+v0x26f8910_0 .net "in1", 0 0, L_0x2b5e2e0; 1 drivers
+v0x26fb750_0 .net "in2", 0 0, L_0x2b5e380; 1 drivers
+v0x26fe590_0 .net "in3", 0 0, L_0x2b5d0c0; 1 drivers
+v0x26d65c0_0 .net "nS0", 0 0, L_0x2b5c260; 1 drivers
+v0x26c2db0_0 .net "nS1", 0 0, L_0x2b5c350; 1 drivers
+v0x26be830_0 .net "out", 0 0, L_0x2b5c8b0; 1 drivers
+v0x26b9b80_0 .net "out0", 0 0, L_0x2b5c3f0; 1 drivers
+v0x26b4ed0_0 .net "out1", 0 0, L_0x2b5c530; 1 drivers
+v0x26a1de0_0 .net "out2", 0 0, L_0x2b5c620; 1 drivers
+v0x269d130_0 .net "out3", 0 0, L_0x2b5c740; 1 drivers
+S_0x23ef410 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x23ddaa0;
+ .timescale -9 -12;
+L_0x2b5d1b0/d .functor NOT 1, L_0x2b5d620, C4<0>, C4<0>, C4<0>;
+L_0x2b5d1b0 .delay (10000,10000,10000) L_0x2b5d1b0/d;
+L_0x2b5d260/d .functor AND 1, L_0x2b5d6c0, L_0x2b5d1b0, C4<1>, C4<1>;
+L_0x2b5d260 .delay (20000,20000,20000) L_0x2b5d260/d;
+L_0x2b5d350/d .functor AND 1, L_0x2b5d7b0, L_0x2b5d620, C4<1>, C4<1>;
+L_0x2b5d350 .delay (20000,20000,20000) L_0x2b5d350/d;
+L_0x2b5d440/d .functor OR 1, L_0x2b5d260, L_0x2b5d350, C4<0>, C4<0>;
+L_0x2b5d440 .delay (20000,20000,20000) L_0x2b5d440/d;
+v0x272f1b0_0 .net "S", 0 0, L_0x2b5d620; 1 drivers
+v0x2731fb0_0 .net "in0", 0 0, L_0x2b5d6c0; 1 drivers
+v0x2734dd0_0 .net "in1", 0 0, L_0x2b5d7b0; 1 drivers
+v0x2737c10_0 .net "nS", 0 0, L_0x2b5d1b0; 1 drivers
+v0x273aa50_0 .net "out0", 0 0, L_0x2b5d260; 1 drivers
+v0x26ea2c0_0 .net "out1", 0 0, L_0x2b5d350; 1 drivers
+v0x26ed0c0_0 .net "outfinal", 0 0, L_0x2b5d440; 1 drivers
+S_0x23b5880 .scope generate, "muxbits[29]" "muxbits[29]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d35f18 .param/l "i" 3 64, +C4<011101>;
+L_0x2b60190/d .functor OR 1, L_0x2b602d0, L_0x2b60370, C4<0>, C4<0>;
+L_0x2b60190 .delay (20000,20000,20000) L_0x2b60190/d;
+v0x27295b0_0 .net *"_s15", 0 0, L_0x2b602d0; 1 drivers
+v0x272c3b0_0 .net *"_s16", 0 0, L_0x2b60370; 1 drivers
+S_0x23d7f40 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x23b5880;
+ .timescale -9 -12;
+L_0x2b5dc10/d .functor NOT 1, L_0x2b5f930, C4<0>, C4<0>, C4<0>;
+L_0x2b5dc10 .delay (10000,10000,10000) L_0x2b5dc10/d;
+L_0x2b5dd00/d .functor NOT 1, L_0x2b5e470, C4<0>, C4<0>, C4<0>;
+L_0x2b5dd00 .delay (10000,10000,10000) L_0x2b5dd00/d;
+L_0x2b5dda0/d .functor NAND 1, L_0x2b5dc10, L_0x2b5dd00, L_0x2b5e5a0, C4<1>;
+L_0x2b5dda0 .delay (10000,10000,10000) L_0x2b5dda0/d;
+L_0x2b5dee0/d .functor NAND 1, L_0x2b5f930, L_0x2b5dd00, L_0x2b5e640, C4<1>;
+L_0x2b5dee0 .delay (10000,10000,10000) L_0x2b5dee0/d;
+L_0x2b5dfd0/d .functor NAND 1, L_0x2b5dc10, L_0x2b5e470, L_0x2b5e6e0, C4<1>;
+L_0x2b5dfd0 .delay (10000,10000,10000) L_0x2b5dfd0/d;
+L_0x2b5e0f0/d .functor NAND 1, L_0x2b5f930, L_0x2b5e470, L_0x2b5e7d0, C4<1>;
+L_0x2b5e0f0 .delay (10000,10000,10000) L_0x2b5e0f0/d;
+L_0x2b5e260/d .functor NAND 1, L_0x2b5dda0, L_0x2b5dee0, L_0x2b5dfd0, L_0x2b5e0f0;
+L_0x2b5e260 .delay (10000,10000,10000) L_0x2b5e260/d;
+v0x270ca30_0 .net "S0", 0 0, L_0x2b5f930; 1 drivers
+v0x270f830_0 .net "S1", 0 0, L_0x2b5e470; 1 drivers
+v0x2712630_0 .net "in0", 0 0, L_0x2b5e5a0; 1 drivers
+v0x2715450_0 .net "in1", 0 0, L_0x2b5e640; 1 drivers
+v0x2718290_0 .net "in2", 0 0, L_0x2b5e6e0; 1 drivers
+v0x271b0d0_0 .net "in3", 0 0, L_0x2b5e7d0; 1 drivers
+v0x271df10_0 .net "nS0", 0 0, L_0x2b5dc10; 1 drivers
+v0x26e1930_0 .net "nS1", 0 0, L_0x2b5dd00; 1 drivers
+v0x26e74c0_0 .net "out", 0 0, L_0x2b5e260; 1 drivers
+v0x2720d50_0 .net "out0", 0 0, L_0x2b5dda0; 1 drivers
+v0x2723b90_0 .net "out1", 0 0, L_0x2b5dee0; 1 drivers
+v0x2723dd0_0 .net "out2", 0 0, L_0x2b5dfd0; 1 drivers
+v0x27267b0_0 .net "out3", 0 0, L_0x2b5e0f0; 1 drivers
+S_0x23d23e0 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x23b5880;
+ .timescale -9 -12;
+L_0x2b5e8c0/d .functor NOT 1, L_0x2b5f1f0, C4<0>, C4<0>, C4<0>;
+L_0x2b5e8c0 .delay (10000,10000,10000) L_0x2b5e8c0/d;
+L_0x2b5e9b0/d .functor NOT 1, L_0x2b5f320, C4<0>, C4<0>, C4<0>;
+L_0x2b5e9b0 .delay (10000,10000,10000) L_0x2b5e9b0/d;
+L_0x2b5ea50/d .functor NAND 1, L_0x2b5e8c0, L_0x2b5e9b0, L_0x2b5f450, C4<1>;
+L_0x2b5ea50 .delay (10000,10000,10000) L_0x2b5ea50/d;
+L_0x2b5eb90/d .functor NAND 1, L_0x2b5f1f0, L_0x2b5e9b0, L_0x2b5f4f0, C4<1>;
+L_0x2b5eb90 .delay (10000,10000,10000) L_0x2b5eb90/d;
+L_0x2b5ec80/d .functor NAND 1, L_0x2b5e8c0, L_0x2b5f320, L_0x2b5f590, C4<1>;
+L_0x2b5ec80 .delay (10000,10000,10000) L_0x2b5ec80/d;
+L_0x2b5edd0/d .functor NAND 1, L_0x2b5f1f0, L_0x2b5f320, L_0x2b60d30, C4<1>;
+L_0x2b5edd0 .delay (10000,10000,10000) L_0x2b5edd0/d;
+L_0x2b5ef40/d .functor NAND 1, L_0x2b5ea50, L_0x2b5eb90, L_0x2b5ec80, L_0x2b5edd0;
+L_0x2b5ef40 .delay (10000,10000,10000) L_0x2b5ef40/d;
+v0x27020f0_0 .net "S0", 0 0, L_0x2b5f1f0; 1 drivers
+v0x26ff2b0_0 .net "S1", 0 0, L_0x2b5f320; 1 drivers
+v0x26fc470_0 .net "in0", 0 0, L_0x2b5f450; 1 drivers
+v0x26f9630_0 .net "in1", 0 0, L_0x2b5f4f0; 1 drivers
+v0x26f67f0_0 .net "in2", 0 0, L_0x2b5f590; 1 drivers
+v0x26f39b0_0 .net "in3", 0 0, L_0x2b60d30; 1 drivers
+v0x26e31c0_0 .net "nS0", 0 0, L_0x2b5e8c0; 1 drivers
+v0x26e2710_0 .net "nS1", 0 0, L_0x2b5e9b0; 1 drivers
+v0x26e15c0_0 .net "out", 0 0, L_0x2b5ef40; 1 drivers
+v0x27013d0_0 .net "out0", 0 0, L_0x2b5ea50; 1 drivers
+v0x26e46c0_0 .net "out1", 0 0, L_0x2b5eb90; 1 drivers
+v0x2706e30_0 .net "out2", 0 0, L_0x2b5ec80; 1 drivers
+v0x2709c30_0 .net "out3", 0 0, L_0x2b5edd0; 1 drivers
+S_0x23bb3e0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x23b5880;
+ .timescale -9 -12;
+L_0x2b5ee60/d .functor NOT 1, L_0x2b5fe70, C4<0>, C4<0>, C4<0>;
+L_0x2b5ee60 .delay (10000,10000,10000) L_0x2b5ee60/d;
+L_0x2b5fab0/d .functor AND 1, L_0x2b5ff10, L_0x2b5ee60, C4<1>, C4<1>;
+L_0x2b5fab0 .delay (20000,20000,20000) L_0x2b5fab0/d;
+L_0x2b5fba0/d .functor AND 1, L_0x2b60000, L_0x2b5fe70, C4<1>, C4<1>;
+L_0x2b5fba0 .delay (20000,20000,20000) L_0x2b5fba0/d;
+L_0x2b5fc90/d .functor OR 1, L_0x2b5fab0, L_0x2b5fba0, C4<0>, C4<0>;
+L_0x2b5fc90 .delay (20000,20000,20000) L_0x2b5fc90/d;
+v0x2738930_0 .net "S", 0 0, L_0x2b5fe70; 1 drivers
+v0x2735af0_0 .net "in0", 0 0, L_0x2b5ff10; 1 drivers
+v0x2721a70_0 .net "in1", 0 0, L_0x2b60000; 1 drivers
+v0x271ec30_0 .net "nS", 0 0, L_0x2b5ee60; 1 drivers
+v0x271bdf0_0 .net "out0", 0 0, L_0x2b5fab0; 1 drivers
+v0x2718fb0_0 .net "out1", 0 0, L_0x2b5fba0; 1 drivers
+v0x2716170_0 .net "outfinal", 0 0, L_0x2b5fc90; 1 drivers
+S_0x237c140 .scope generate, "muxbits[30]" "muxbits[30]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1d36378 .param/l "i" 3 64, +C4<011110>;
+L_0x2b624f0/d .functor OR 1, L_0x2b62630, L_0x2b626d0, C4<0>, C4<0>;
+L_0x2b624f0 .delay (20000,20000,20000) L_0x2b624f0/d;
+v0x275c450_0 .net *"_s15", 0 0, L_0x2b62630; 1 drivers
+v0x275da10_0 .net *"_s16", 0 0, L_0x2b626d0; 1 drivers
+S_0x23afd20 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x237c140;
+ .timescale -9 -12;
+L_0x2b60460/d .functor NOT 1, L_0x2b60dd0, C4<0>, C4<0>, C4<0>;
+L_0x2b60460 .delay (10000,10000,10000) L_0x2b60460/d;
+L_0x2b60550/d .functor NOT 1, L_0x2b60f00, C4<0>, C4<0>, C4<0>;
+L_0x2b60550 .delay (10000,10000,10000) L_0x2b60550/d;
+L_0x2b605f0/d .functor NAND 1, L_0x2b60460, L_0x2b60550, L_0x2b61030, C4<1>;
+L_0x2b605f0 .delay (10000,10000,10000) L_0x2b605f0/d;
+L_0x2b60730/d .functor NAND 1, L_0x2b60dd0, L_0x2b60550, L_0x2b610d0, C4<1>;
+L_0x2b60730 .delay (10000,10000,10000) L_0x2b60730/d;
+L_0x2b60880/d .functor NAND 1, L_0x2b60460, L_0x2b60f00, L_0x2b61170, C4<1>;
+L_0x2b60880 .delay (10000,10000,10000) L_0x2b60880/d;
+L_0x2b609d0/d .functor NAND 1, L_0x2b60dd0, L_0x2b60f00, L_0x2b61260, C4<1>;
+L_0x2b609d0 .delay (10000,10000,10000) L_0x2b609d0/d;
+L_0x2b60b40/d .functor NAND 1, L_0x2b605f0, L_0x2b60730, L_0x2b60880, L_0x2b609d0;
+L_0x2b60b40 .delay (10000,10000,10000) L_0x2b60b40/d;
+v0x2760590_0 .net "S0", 0 0, L_0x2b60dd0; 1 drivers
+v0x2761b50_0 .net "S1", 0 0, L_0x2b60f00; 1 drivers
+v0x2763110_0 .net "in0", 0 0, L_0x2b61030; 1 drivers
+v0x2741240_0 .net "in1", 0 0, L_0x2b610d0; 1 drivers
+v0x2742800_0 .net "in2", 0 0, L_0x2b61170; 1 drivers
+v0x2743dc0_0 .net "in3", 0 0, L_0x2b61260; 1 drivers
+v0x27541d0_0 .net "nS0", 0 0, L_0x2b60460; 1 drivers
+v0x2755790_0 .net "nS1", 0 0, L_0x2b60550; 1 drivers
+v0x2756d50_0 .net "out", 0 0, L_0x2b60b40; 1 drivers
+v0x273fc80_0 .net "out0", 0 0, L_0x2b605f0; 1 drivers
+v0x2758310_0 .net "out1", 0 0, L_0x2b60730; 1 drivers
+v0x27598d0_0 .net "out2", 0 0, L_0x2b60880; 1 drivers
+v0x275ae90_0 .net "out3", 0 0, L_0x2b609d0; 1 drivers
+S_0x2398d00 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x237c140;
+ .timescale -9 -12;
+L_0x2b61350/d .functor NOT 1, L_0x2b61c20, C4<0>, C4<0>, C4<0>;
+L_0x2b61350 .delay (10000,10000,10000) L_0x2b61350/d;
+L_0x2b61440/d .functor NOT 1, L_0x2b61d50, C4<0>, C4<0>, C4<0>;
+L_0x2b61440 .delay (10000,10000,10000) L_0x2b61440/d;
+L_0x2b614e0/d .functor NAND 1, L_0x2b61350, L_0x2b61440, L_0x2b61e80, C4<1>;
+L_0x2b614e0 .delay (10000,10000,10000) L_0x2b614e0/d;
+L_0x2b61620/d .functor NAND 1, L_0x2b61c20, L_0x2b61440, L_0x2b61f20, C4<1>;
+L_0x2b61620 .delay (10000,10000,10000) L_0x2b61620/d;
+L_0x2b61710/d .functor NAND 1, L_0x2b61350, L_0x2b61d50, L_0x2b61fc0, C4<1>;
+L_0x2b61710 .delay (10000,10000,10000) L_0x2b61710/d;
+L_0x2b61800/d .functor NAND 1, L_0x2b61c20, L_0x2b61d50, L_0x2b63550, C4<1>;
+L_0x2b61800 .delay (10000,10000,10000) L_0x2b61800/d;
+L_0x2b61970/d .functor NAND 1, L_0x2b614e0, L_0x2b61620, L_0x2b61710, L_0x2b61800;
+L_0x2b61970 .delay (10000,10000,10000) L_0x2b61970/d;
+v0x262b810_0 .net "S0", 0 0, L_0x2b61c20; 1 drivers
+v0x26259b0_0 .net "S1", 0 0, L_0x2b61d50; 1 drivers
+v0x260e0f0_0 .net "in0", 0 0, L_0x2b61e80; 1 drivers
+v0x2608290_0 .net "in1", 0 0, L_0x2b61f20; 1 drivers
+v0x25f09b0_0 .net "in2", 0 0, L_0x2b61fc0; 1 drivers
+v0x25eab50_0 .net "in3", 0 0, L_0x2b63550; 1 drivers
+v0x25e4cf0_0 .net "nS0", 0 0, L_0x2b61350; 1 drivers
+v0x25cd430_0 .net "nS1", 0 0, L_0x2b61440; 1 drivers
+v0x25c75d0_0 .net "out", 0 0, L_0x2b61970; 1 drivers
+v0x25afcf0_0 .net "out0", 0 0, L_0x2b614e0; 1 drivers
+v0x25a9e90_0 .net "out1", 0 0, L_0x2b61620; 1 drivers
+v0x25a4030_0 .net "out2", 0 0, L_0x2b61710; 1 drivers
+v0x275efd0_0 .net "out3", 0 0, L_0x2b61800; 1 drivers
+S_0x23931a0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x237c140;
+ .timescale -9 -12;
+L_0x2b63640/d .functor NOT 1, L_0x2b621d0, C4<0>, C4<0>, C4<0>;
+L_0x2b63640 .delay (10000,10000,10000) L_0x2b63640/d;
+L_0x2b63730/d .functor AND 1, L_0x2b62270, L_0x2b63640, C4<1>, C4<1>;
+L_0x2b63730 .delay (20000,20000,20000) L_0x2b63730/d;
+L_0x2b63820/d .functor AND 1, L_0x2b62360, L_0x2b621d0, C4<1>, C4<1>;
+L_0x2b63820 .delay (20000,20000,20000) L_0x2b63820/d;
+L_0x2b63910/d .functor OR 1, L_0x2b63730, L_0x2b63820, C4<0>, C4<0>;
+L_0x2b63910 .delay (20000,20000,20000) L_0x2b63910/d;
+v0x27479c0_0 .net "S", 0 0, L_0x2b621d0; 1 drivers
+v0x2744e40_0 .net "in0", 0 0, L_0x2b62270; 1 drivers
+v0x2765840_0 .net "in1", 0 0, L_0x2b62360; 1 drivers
+v0x1d410e0_0 .net "nS", 0 0, L_0x2b63640; 1 drivers
+v0x1d3bc20_0 .net "out0", 0 0, L_0x2b63730; 1 drivers
+v0x26430f0_0 .net "out1", 0 0, L_0x2b63820; 1 drivers
+v0x2631670_0 .net "outfinal", 0 0, L_0x2b63910; 1 drivers
+S_0x24b2060 .scope generate, "muxbits[31]" "muxbits[31]" 3 64, 3 64, S_0x1f6b890;
+ .timescale -9 -12;
+P_0x1dd20e8 .param/l "i" 3 64, +C4<011111>;
+L_0x2b64840/d .functor OR 1, L_0x2b64980, L_0x2b64a20, C4<0>, C4<0>;
+L_0x2b64840 .delay (20000,20000,20000) L_0x2b64840/d;
+v0x274d0c0_0 .net *"_s15", 0 0, L_0x2b64980; 1 drivers
+v0x274a540_0 .net *"_s16", 0 0, L_0x2b64a20; 1 drivers
+S_0x23765e0 .scope module, "ZeroMux" "FourInMux" 3 66, 3 125, S_0x24b2060;
+ .timescale -9 -12;
+L_0x2b627c0/d .functor NOT 1, L_0x2b63090, C4<0>, C4<0>, C4<0>;
+L_0x2b627c0 .delay (10000,10000,10000) L_0x2b627c0/d;
+L_0x2b628b0/d .functor NOT 1, L_0x2b631c0, C4<0>, C4<0>, C4<0>;
+L_0x2b628b0 .delay (10000,10000,10000) L_0x2b628b0/d;
+L_0x2b62950/d .functor NAND 1, L_0x2b627c0, L_0x2b628b0, L_0x2b632f0, C4<1>;
+L_0x2b62950 .delay (10000,10000,10000) L_0x2b62950/d;
+L_0x2b62a90/d .functor NAND 1, L_0x2b63090, L_0x2b628b0, L_0x2b63390, C4<1>;
+L_0x2b62a90 .delay (10000,10000,10000) L_0x2b62a90/d;
+L_0x2b62b80/d .functor NAND 1, L_0x2b627c0, L_0x2b631c0, L_0x2b63430, C4<1>;
+L_0x2b62b80 .delay (10000,10000,10000) L_0x2b62b80/d;
+L_0x2b62c70/d .functor NAND 1, L_0x2b63090, L_0x2b631c0, L_0x2b64ee0, C4<1>;
+L_0x2b62c70 .delay (10000,10000,10000) L_0x2b62c70/d;
+L_0x2b62de0/d .functor NAND 1, L_0x2b62950, L_0x2b62a90, L_0x2b62b80, L_0x2b62c70;
+L_0x2b62de0 .delay (10000,10000,10000) L_0x2b62de0/d;
+v0x23a3090_0 .net "S0", 0 0, L_0x2b63090; 1 drivers
+v0x23a1050_0 .net "S1", 0 0, L_0x2b631c0; 1 drivers
+v0x23a8ce0_0 .net "in0", 0 0, L_0x2b632f0; 1 drivers
+v0x23a6ca0_0 .net "in1", 0 0, L_0x2b63390; 1 drivers
+v0x23ac8f0_0 .net "in2", 0 0, L_0x2b63430; 1 drivers
+v0x23bfb70_0 .net "in3", 0 0, L_0x2b64ee0; 1 drivers
+v0x23c57c0_0 .net "nS0", 0 0, L_0x2b627c0; 1 drivers
+v0x23c3780_0 .net "nS1", 0 0, L_0x2b628b0; 1 drivers
+v0x23cb410_0 .net "out", 0 0, L_0x2b62de0; 1 drivers
+v0x23c93d0_0 .net "out0", 0 0, L_0x2b62950; 1 drivers
+v0x23e0240_0 .net "out1", 0 0, L_0x2b62a90; 1 drivers
+v0x27527c0_0 .net "out2", 0 0, L_0x2b62b80; 1 drivers
+v0x274fc40_0 .net "out3", 0 0, L_0x2b62c70; 1 drivers
+S_0x2370a80 .scope module, "OneMux" "FourInMux" 3 67, 3 125, S_0x24b2060;
+ .timescale -9 -12;
+L_0x2b62d00/d .functor NOT 1, L_0x2b63af0, C4<0>, C4<0>, C4<0>;
+L_0x2b62d00 .delay (10000,10000,10000) L_0x2b62d00/d;
+L_0x2b3ac30/d .functor NOT 1, L_0x2b63c20, C4<0>, C4<0>, C4<0>;
+L_0x2b3ac30 .delay (10000,10000,10000) L_0x2b3ac30/d;
+L_0x2b3acd0/d .functor NAND 1, L_0x2b62d00, L_0x2b3ac30, L_0x2b63d50, C4<1>;
+L_0x2b3acd0 .delay (10000,10000,10000) L_0x2b3acd0/d;
+L_0x2b65470/d .functor NAND 1, L_0x2b63af0, L_0x2b3ac30, L_0x2b63df0, C4<1>;
+L_0x2b65470 .delay (10000,10000,10000) L_0x2b65470/d;
+L_0x2b65560/d .functor NAND 1, L_0x2b62d00, L_0x2b63c20, L_0x2b63e90, C4<1>;
+L_0x2b65560 .delay (10000,10000,10000) L_0x2b65560/d;
+L_0x2b65680/d .functor NAND 1, L_0x2b63af0, L_0x2b63c20, L_0x2b63f80, C4<1>;
+L_0x2b65680 .delay (10000,10000,10000) L_0x2b65680/d;
+L_0x2b657f0/d .functor NAND 1, L_0x2b3acd0, L_0x2b65470, L_0x2b65560, L_0x2b65680;
+L_0x2b657f0 .delay (10000,10000,10000) L_0x2b657f0/d;
+v0x252c3f0_0 .net "S0", 0 0, L_0x2b63af0; 1 drivers
+v0x2529870_0 .net "S1", 0 0, L_0x2b63c20; 1 drivers
+v0x2526cf0_0 .net "in0", 0 0, L_0x2b63d50; 1 drivers
+v0x2524170_0 .net "in1", 0 0, L_0x2b63df0; 1 drivers
+v0x25215f0_0 .net "in2", 0 0, L_0x2b63e90; 1 drivers
+v0x23699c0_0 .net "in3", 0 0, L_0x2b63f80; 1 drivers
+v0x23678b0_0 .net "nS0", 0 0, L_0x2b62d00; 1 drivers
+v0x2380930_0 .net "nS1", 0 0, L_0x2b3ac30; 1 drivers
+v0x237e8f0_0 .net "out", 0 0, L_0x2b657f0; 1 drivers
+v0x2386580_0 .net "out0", 0 0, L_0x2b3acd0; 1 drivers
+v0x2384540_0 .net "out1", 0 0, L_0x2b65470; 1 drivers
+v0x238c1d0_0 .net "out2", 0 0, L_0x2b65560; 1 drivers
+v0x238a190_0 .net "out3", 0 0, L_0x2b65680; 1 drivers
+S_0x249f0b0 .scope module, "TwoMux" "TwoInMux" 3 68, 3 109, S_0x24b2060;
+ .timescale -9 -12;
+L_0x2b64070/d .functor NOT 1, L_0x2b64520, C4<0>, C4<0>, C4<0>;
+L_0x2b64070 .delay (10000,10000,10000) L_0x2b64070/d;
+L_0x2b64160/d .functor AND 1, L_0x2b645c0, L_0x2b64070, C4<1>, C4<1>;
+L_0x2b64160 .delay (20000,20000,20000) L_0x2b64160/d;
+L_0x2b64250/d .functor AND 1, L_0x2b646b0, L_0x2b64520, C4<1>, C4<1>;
+L_0x2b64250 .delay (20000,20000,20000) L_0x2b64250/d;
+L_0x2b64340/d .functor OR 1, L_0x2b64160, L_0x2b64250, C4<0>, C4<0>;
+L_0x2b64340 .delay (20000,20000,20000) L_0x2b64340/d;
+v0x1d33020_0 .net "S", 0 0, L_0x2b64520; 1 drivers
+v0x1d2c820_0 .net "in0", 0 0, L_0x2b645c0; 1 drivers
+v0x1d22e40_0 .net "in1", 0 0, L_0x2b646b0; 1 drivers
+v0x236b130_0 .net "nS", 0 0, L_0x2b64070; 1 drivers
+v0x27ee2c0_0 .net "out0", 0 0, L_0x2b64160; 1 drivers
+v0x1d3b070_0 .net "out1", 0 0, L_0x2b64250; 1 drivers
+v0x1d4dd80_0 .net "outfinal", 0 0, L_0x2b64340; 1 drivers
+    .scope S_0x22efd20;
+T_0 ;
+    %vpi_call 2 167 "$dumpfile", "FullALU.vcd";
+    %vpi_call 2 168 "$dumpvars";
+    %vpi_call 2 170 "$display", "Test 4 Bit Adder Functionality";
+    %vpi_call 2 172 "$display", " A   | B    |Command| Out|ExpectedOut|Cout|OF";
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 176 "$display", "%b | %b | %b | %b | Expect 0110| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 1, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 6, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 180 "$display", "%b | %b | %b | %b | Expect 0111| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 5, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 13, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 184 "$display", "%b | %b | %b | %b | Expect 0010| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 188 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 8, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 3, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 192 "$display", "%b | %b | %b | %b | Expect 1011| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 12, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 2, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 196 "$display", "%b | %b | %b | %b | Expect 1110| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 200 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 7, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 9, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 204 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 13, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 12, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 208 "$display", "%b | %b | %b | %b | Expect 1001| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 14, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 10, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 212 "$display", "%b | %b | %b | %b | Expect 1000| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 5, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 6, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 216 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 7, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 220 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 7, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 7, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 224 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 8, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 228 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 8, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 13, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 232 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 12, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 236 "$display", "%b | %b | %b | %b | Expect XXXX| %b | %b ", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x295ff30_0, v0x2960870_0, v0x2960980_0;
+    %vpi_call 2 238 "$display", "Test 4 Bit SLT Functionality";
+    %vpi_call 2 240 "$display", " A   | B    |Command| Out|ExpectedOut|Cout|OF |SLTflag";
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 244 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 4, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 2, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 248 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 14, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 252 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 4, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 14, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 256 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 14, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 260 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 14, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 264 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 13, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 13, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 268 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 5, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 272 "$display", "%b | %b | %b | %b | Expect 0000| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %movi 8, 9, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 276 "$display", "%b | %b | %b | %b | Expect 0001| %b | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960440_0, v0x2960870_0, v0x2960980_0, v0x2960640_0;
+    %vpi_call 2 278 "$display", "Test 4 Bit AND/NAND Functionality";
+    %vpi_call 2 280 "$display", " A   | B    |Command| Out    |ExpectedOut-AND";
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 4, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 284 "$display", "%b | %b |   %b |  %b  | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 10, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 4, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 288 "$display", "%b | %b |   %b |  %b  | 1010", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 4, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 292 "$display", "%b | %b |   %b |  %b  | 0101", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 4, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 296 "$display", "%b | %b |   %b |  %b  | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %vpi_call 2 299 "$display", " A   | B    |Command| Out    |ExpectedOut-NAND";
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 5, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 303 "$display", "%b | %b |   %b |  %b  | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 10, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 5, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 307 "$display", "%b | %b |   %b |  %b  | 0101", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 5, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 311 "$display", "%b | %b |   %b |  %b  | 1010", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 5, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 315 "$display", "%b | %b |   %b |  %b  | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960110_0;
+    %vpi_call 2 317 "$display", "Test 4 Bit OR/NOR/XOR Functionality";
+    %vpi_call 2 319 "$display", " A   | B    |Command  | Out     |ExpectedOut-OR";
+    %movi 8, 10, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 1, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 323 "$display", "%b | %b |    %b  |  %b   | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 1, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 327 "$display", "%b | %b |    %b  |  %b   | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %set/v v0x2960210_0, 1, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 331 "$display", "%b | %b |    %b  |  %b   | 1011", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %vpi_call 2 333 "$display", " A   | B    |Command  | Out     |ExpectedOut-NOR";
+    %movi 8, 10, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 6, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 337 "$display", "%b | %b |    %b  |  %b   | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 6, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 341 "$display", "%b | %b |    %b  |  %b   | 0000", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 6, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 345 "$display", "%b | %b |    %b  |  %b   | 0100", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %vpi_call 2 347 "$display", " A   | B    |Command  | Out     |ExpectedOut-XOR";
+    %movi 8, 10, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 2, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 351 "$display", "%b | %b |    %b  |  %b   | 1111", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 2, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 355 "$display", "%b | %b |    %b  |  %b   | 1010", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 2, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 359 "$display", "%b | %b |    %b  |  %b   | 1011", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x29603c0_0;
+    %vpi_call 2 361 "$display", "Test 4 Bit ALU Functionality";
+    %vpi_call 2 363 "$display", " A   | B    |Command     | Out     |ExpectedOut | COut | OF |SLT|Zero";
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 4, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 368 "$display", "%b | %b | %b - AND  |  %b   | 1111       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 5, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 373 "$display", "%b | %b | %b - NAND |  %b   | 1111       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 1, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 378 "$display", "%b | %b | %b - OR   |  %b   | 1111       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 6, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 383 "$display", "%b | %b | %b - NOR  |  %b   | 0100       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 2, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 388 "$display", "%b | %b | %b - XOR  |  %b   | 1011       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 393 "$display", "%b | %b | %b - ADD  |  %b   | 0110       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 12, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 397 "$display", "%b | %b | %b - ADD  |  %b   | XXXX       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 1, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 402 "$display", "%b | %b | %b - SUB  |  %b   | 1110       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 9, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 3, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 1, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 406 "$display", "%b | %b | %b - SUB  |  %b   | XXXX       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 4, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 2, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 412 "$display", "%b | %b | %b - SLT  |  %b   | 0010       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x2960640_0, v0x295ffb0_0;
+    %movi 8, 9, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 5, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 416 "$display", "%b | %b | %b - SLT  |  %b   | XXXX       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x2960640_0, v0x295ffb0_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 420 "$display", "%b | %b | %b - SLT  |  %b   | XXXX       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x2960640_0, v0x295ffb0_0;
+    %set/v v0x295fe90_0, 0, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 4, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 428 "$display", "%b | %b | %b - AND  |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 15, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 15, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 5, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 431 "$display", "%b | %b | %b - NAND |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %set/v v0x295fe90_0, 0, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %set/v v0x2960210_0, 1, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 434 "$display", "%b | %b | %b - OR   |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 4, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 6, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 436 "$display", "%b | %b | %b - NOR  |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 11, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 11, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 2, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 439 "$display", "%b | %b | %b - XOR  |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 14, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %set/v v0x2960210_0, 0, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 442 "$display", "%b | %b | %b - ADD  |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %movi 8, 2, 32;
+    %set/v v0x295fe90_0, 8, 32;
+    %movi 8, 2, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 1, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 445 "$display", "%b | %b | %b - SUB  |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %set/v v0x295fe90_0, 0, 32;
+    %set/v v0x2960190_0, 0, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 449 "$display", "%b | %b | %b - SLT  |  %b   | 0000       | %b    | %b  | %b | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960290_0, v0x2960870_0, v0x2960980_0, v0x29604c0_0, v0x295ffb0_0;
+    %vpi_call 2 455 "$display", " A  \011\011\011\011 | B \011\011\011  \011 |Command    \011 | Out \011   \011\011\011\011 |ExpectedOut \011| COut | OF |Zero";
+    %set/v v0x295fe90_0, 1, 32;
+    %movi 8, 4294967294, 32;
+    %set/v v0x2960190_0, 8, 32;
+    %movi 8, 3, 3;
+    %set/v v0x2960210_0, 8, 3;
+    %delay 1000000, 0;
+    %vpi_call 2 457 "$display", "%b | %b | %b - SLT  |  %b   | 00000000000000000000000000000001       | %b    | %b  | %b", v0x295fe90_0, v0x2960190_0, v0x2960210_0, v0x2960310_0, v0x2960740_0, v0x29608f0_0, v0x2960030_0;
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "testing.t.v";
+    "./alu.v";
diff --git a/testing.t.v b/testing.t.v
new file mode 100644
index 0000000..83c4676
--- /dev/null
+++ b/testing.t.v
@@ -0,0 +1,464 @@
+// Intermediate testbench
+`timescale 1 ns / 1 ps
+`include "alu.v"
+
+/*
+module testBasicFunctions();
+// we begin by testing the basic AND/NAND, OR/NOR/XOR, and ADD/SUB/SLT modules
+wire AndNandOut;
+reg A, B;
+reg[2:0] Command;
+//reg S;
+wire OneBitFinalOut;
+wire AddSubSLTSum, carryout, subtract; //overflow - we don't calculate overflow except with the most significant bit, so we don't worry about it here
+reg carryin;
+wire OrNorXorOut;
+reg S0, S1;
+reg in0, in1, in2, in3;
+wire muxout;
+// test mux functionality: 	
+	FourInMux testmux(muxout, S0, S1, in0, in1, in2, in3);
+// test ADD/SUB/SLT
+	MiddleAddSubSLT testadd(AddSubSLTSum, carryout, subtract, A, B, Command, carryin);
+// test AND/NAND
+    AndNand testand(AndNandOut, A, B, Command); 
+// test OR/NOR/XOR
+	OrNorXor testor(OrNorXorOut, A, B, Command);
+initial begin
+	$dumpfile("SmallALU.vcd");
+	$dumpvars();
+
+
+// test mux
+	$display("Four Input Multiplexer");
+	$display("S0 S1 |in0 in1 in2 in3| Output");
+	S0 = 0; S1 = 0; in0 = 1'bx; in1 = 0; in2 = 0; in3 = 0; #1000
+	$display(" %b %b  | %b   %b   %b   %b | %b", S0, S1, in0, in1, in2, in3, muxout);
+	S0 = 1; S1 = 0; in0 = 0; in1 = 1'bx; in2 = 0; in3 = 0; #1000
+	$display(" %b %b  | %b   %b   %b   %b | %b", S0, S1, in0, in1, in2, in3, muxout);
+	S0 = 0; S1 = 1; in0 = 0; in1 = 0; in2 = 1'bx; in3 = 0; #1000
+	$display(" %b %b  | %b   %b   %b   %b | %b", S0, S1, in0, in1, in2, in3, muxout);
+	S0 = 1; S1 = 1; in0 = 0; in1 = 0; in2 = 0; in3 = 1'bx; #1000
+	$display(" %b %b  | %b   %b   %b   %b | %b", S0, S1, in0, in1, in2, in3, muxout);
+// just the adder - proper behavior
+	$display("Adder/Subtractor");
+    $display("A B | Command |Out|ExpectOut|Carryout-Add");
+	// adding
+    A=1;B=1;Command=3'b000; carryin = 0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=1;B=0;Command=3'b000; carryin = 0; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=0;B=1;Command=3'b000; carryin = 0; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout);   					 
+	A=0;B=0;Command=3'b000; carryin = 0; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+	// subtracting - carrying must be set to 1 for subtraction
+    $display("A B | Command |Out|ExpectOut|Carryout-Sub");
+    A=1;B=1;Command=3'b001; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=1;B=0;Command=3'b001; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=0;B=1;Command=3'b001; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout);   					 
+	A=0;B=0;Command=3'b001; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+	// SLT - this should look exactly like the subtraction, since nothing has been done to distinguish one from the other
+    $display("A B | Command |Out|ExpectOut|Carryout-SLT");
+    A=1;B=1;Command=3'b011; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=1;B=0;Command=3'b011; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout);
+    A=0;B=1;Command=3'b011; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 1 | %b", A, B, Command, AddSubSLTSum, carryout);   					 
+	A=0;B=0;Command=3'b011; carryin = 1; #1000 
+    $display("%b  %b |   %b |  %b | 0 | %b", A, B, Command, AddSubSLTSum, carryout);
+// Exhaustively testing AND/NAND 
+    $display("A B |Command|Out|ExpectOut-AND");
+    A=0;B=0;Command=3'b100; #1000 
+    $display("%b  %b |   %b |  %b  | 0", A, B, Command, AndNandOut);
+    A=0;B=1;Command=3'b100; #1000 
+    $display("%b  %b |   %b |  %b  | 0", A, B, Command, AndNandOut);
+    A=1;B=0;Command=3'b100; #1000 
+    $display("%b  %b |   %b |  %b  | 0", A, B, Command, AndNandOut);
+    A=1;B=1;Command=3'b100; #1000 
+    $display("%b  %b |   %b |  %b  | 1", A, B, Command, AndNandOut);
+    $display("A B |Command|Out|ExpectOut-NAND");
+    A=0;B=0;Command=3'b101; #1000 
+    $display("%b  %b |   %b |  %b  | 1", A, B, Command, AndNandOut);
+    A=0;B=1;Command=3'b101; #1000 
+    $display("%b  %b |   %b |  %b  | 1", A, B, Command, AndNandOut);
+    A=1;B=0;Command=3'b101; #1000 
+    $display("%b  %b |   %b |  %b  | 1", A, B, Command, AndNandOut);
+    A=1;B=1;Command=3'b101; #1000 
+    $display("%b  %b |   %b |  %b  | 0", A, B, Command, AndNandOut);
+// Exhaustively testing OR/NOR/XOR
+    $display("A B |Command|Out|ExpectOut-OR");
+	A=1; B=1; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 1", A, B, Command, OrNorXorOut);
+	A=1; B=0; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 1", A, B, Command, OrNorXorOut);
+	A=0; B=1; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 1", A, B, Command, OrNorXorOut);
+	A=0; B=0; Command=3'b111; #1000
+	$display("%b %b |    %b  |  %b   | 0", A, B, Command, OrNorXorOut);
+    $display("A B |Command|Out|ExpectOut-NOR");
+	A=1; B=1; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 0", A, B, Command, OrNorXorOut);
+	A=1; B=0; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 0", A, B, Command, OrNorXorOut);
+	A=0; B=1; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 0", A, B, Command, OrNorXorOut);
+	A=0; B=0; Command=3'b110; #1000
+	$display("%b %b |    %b  |  %b   | 1", A, B, Command, OrNorXorOut);
+    $display("A B |Command|Out|ExpectOut-XOR");
+	A=1; B=1; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 0", A, B, Command, OrNorXorOut);
+	A=1; B=0; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 1", A, B, Command, OrNorXorOut);
+	A=0; B=1; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 1 ", A, B, Command, OrNorXorOut);
+	A=0; B=0; Command=3'b010; #1000
+	$display("%b %b |    %b  |  %b   | 0", A, B, Command, OrNorXorOut);
+end
+endmodule
+*/
+
+module test32Adder();
+parameter size = 32; 
+wire  [size-1:0] OneBitFinalOut;
+wire [size-1:0] OrNorXorOut;
+wire [size-1:0] AndNandOut;
+wire [size-1:0] AddSubSLTSum; 
+wire [size-1:0] SLTSum; 
+wire carryout; 
+wire overflow; 
+wire SLTflag;
+wire SLTflag1;
+wire [size-1:0]ZeroFlag;
+wire AllZeros;
+wire [size-1:0] subtract; 
+reg [size-1:0] A, B; 
+reg [2:0] Command;
+reg [size-1:0]carryin; 
+wire Cmd0Start [size-1:0];
+wire Cmd1Start [size-1:0]; 
+wire [size-1:0] CarryoutWire;
+
+// creating new variables for ALU to make sure nothing gets mixed up
+wire  [size-1:0] OneBitFinalOut2;
+wire AllZeros2;
+wire carryout2;
+wire overflow2;
+
+ 
+AddSubSLT32 trial(AddSubSLTSum, carryout, overflow, subtract, A, B, Command, carryin);
+
+SLT32 test2(SLTSum, carryout, overflow, SLTflag1, subtract, A, B, Command, carryin);
+
+AndNand32 trial1(AndNandOut, A, B, Command);
+
+OrNorXor32 trial2(OrNorXorOut, A, B, Command);
+
+Bitslice32 superalu(OneBitFinalOut, AddSubSLTSum, SLTSum, carryout, overflow, SLTflag,  OrNorXorOut, AndNandOut, subtract, ZeroFlag, AllZeros, A, B, Command, carryin);
+
+ALU testALU(OneBitFinalOut2, carryout2, AllZeros2, overflow2, A, B, Command);
+
+initial begin
+	$dumpfile("FullALU.vcd");
+	$dumpvars();
+
+$display("Test 4 Bit Adder Functionality");
+// there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically
+$display(" A   | B    |Command| Out|ExpectedOut|Cout|OF"); 
+
+//Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW
+A = 4'b0010; B = 4'b0100; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 0110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Pos < 7 | 1 + 6 = 7 | 1 = 0001 | 6 = 0110 | 7 = 0111 | NO OVERFLOW
+A = 4'b0001; B = 4'b0110; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 0111| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Neg > 0 | 5 + -3 = 2 | 5 = 0101 | -3 = 1101 | 2 = 0010 | NO OVERFLOW
+A = 4'b0101; B = 4'b1101; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 0010| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Neg > 0 | 2 + -1 = 1 | 2 = 0010 | -1 = 1111 | 1 = 0001 | NO OVERFLOW
+A = 4'b0010; B = 4'b1111; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 0001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Neg < 0 | -8 + 3 = -5 | -8 = 1000 | 3 = 0011 | -5 = 1011 | NO OVERFLOW
+A = 4'b1000; B = 4'b0011; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 1011| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Neg < 0 | -4 + 2 = -2 | -4 = 1100 | 2 = 0010 | -2 = 1110 | NO OVERFLOW
+A = 4'b1100; B = 4'b0010; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 1110| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Neg = 0 | -5 + 5 = 0 | -5 = 1101 | 5 = 0101 | 0 = 0000 | NO OVERFLOW
+A = 4'b1011; B = 4'b0101; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Neg = 0 | -7 + 7 = 0 | -7 = 1001 | 7 = 0111 | 0 = 0000 | NO OVERFLOW
+A = 4'b0111; B = 4'b1001; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Neg + Neg > -8 | -3 + -4 = -7 | -3 = 1101 | -4 = 1100 | -7 = 1001 | NO OVERFLOW
+A = 4'b1101; B = 4'b1100; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 1001| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Neg + Neg > -8 | -2 + -6 = -8 | -2 = 1110 | -6 = 1010 | -8 = 1000 | NO OVERFLOW
+A = 4'b1110; B = 4'b1010; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect 1000| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Pos > 7 | 5 + 6 = 11 | 5 = 0101 | 6 = 0110 |  | OVERFLOW
+A = 4'b0101; B = 4'b0110; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Pos > 7 | 2 + 7 = 9 | 2 = 0010 | 7 = 0111 |  | OVERFLOW
+A = 4'b0010; B = 4'b0111; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Pos + Pos > 7 | 7 + 7 = 14 | 7 = 0111 | 7 = 0111 |  | OVERFLOW
+A = 4'b0111; B = 4'b0111; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Neg + Neg < -8 | -8 + -1 = -9 | -8 = 1000 | -1 = 1111 |  | OVERFLOW
+A = 4'b1000; B = 4'b1111; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Neg + Neg < -8 | -8 + -3 = -11 | -8 = 1000 | -3 = 1101 |  | OVERFLOW
+A = 4'b1000; B = 4'b1101; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+//Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 |  | OVERFLOW
+A = 4'b1011; B = 4'b1100; Command =3'b000; #1000
+$display("%b | %b | %b | %b | Expect XXXX| %b | %b ", A, B, Command, AddSubSLTSum, carryout, overflow);
+
+$display("Test 4 Bit SLT Functionality");
+// there are too many possibilities even for just a four bit adder/subtractor, which means we need to choose our test cases strategically. We chose to not specifically test the subtractor, since it is part of the SLT, and if the SLT is working, then the subtractor is, too.
+$display(" A   | B    |Command| Out|ExpectedOut|Cout|OF |SLTflag"); 
+
+// A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100
+A = 4'b0010; B = 4'b0100; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010
+A = 4'b0100; B = 4'b0010; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A < B, A < 0 | B > 0 | No Overflow | A = -2 = 1110 | B = 4 = 0100
+A = 4'b1110; B = 4'b0100; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A > B, A > 0 | B < 0 | No Overflow | A = 4 = 0100| B = -2 = 1110
+A = 4'b0100; B = 4'b1110; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A < B, A < 0 | B < 0 | No Overflow | A = -2 = 1110 | B = -1 = 1111
+A = 4'b1110; B = 4'b1111; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A > B, A < 0 | B < 0 | No Overflow | A = -1 = 1111 | B = -2 = 1110
+A = 4'b1111; B = 4'b1110; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A = B, A < 0 | B < 0 | No Overflow | A = -3 = 1101 | B = -3 = 1101
+A = 4'b1101; B = 4'b1101; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A = B, A > 0 | B > 0 | No Overflow | A = 5 = 0101 | B = 5 = 0101
+A = 4'b0101; B = 4'b0101; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0000| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101
+A = 4'b1001; B = 4'b0101; Command =3'b011; #1000
+$display("%b | %b | %b | %b | Expect 0001| %b | %b | %b", A, B, Command, SLTSum, carryout, overflow, SLTflag1);
+
+$display("Test 4 Bit AND/NAND Functionality");
+// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. 
+$display(" A   | B    |Command| Out    |ExpectedOut-AND"); 
+
+// A = B | A = 1111 | AND = 1111
+    A=4'b1111;B=4'b1111;Command=3'b100; #1000 
+    $display("%b | %b |   %b |  %b  | 1111", A, B, Command, AndNandOut);
+
+//  A = 1111 | B = 1010 | AND = 1010
+    A=4'b1111;B=4'b1010;Command=3'b100; #1000 
+    $display("%b | %b |   %b |  %b  | 1010", A, B, Command, AndNandOut);
+
+//  A = 1111 | B = 0101 | AND = 0101
+    A=4'b1111;B=4'b0101;Command=3'b100; #1000 
+    $display("%b | %b |   %b |  %b  | 0101", A, B, Command, AndNandOut);
+
+//  A = 1111 | B = 0000 | AND = 0000
+    A=4'b1111;B=4'b0000;Command=3'b100; #1000 
+    $display("%b | %b |   %b |  %b  | 0000", A, B, Command, AndNandOut);
+
+
+$display(" A   | B    |Command| Out    |ExpectedOut-NAND"); 
+
+// A = B | A = 1111 | NAND = 0000
+    A=4'b1111;B=4'b1111;Command=3'b101; #1000 
+    $display("%b | %b |   %b |  %b  | 0000", A, B, Command, AndNandOut);
+
+//  A = 1111 | B = 1010 | NAND = 0101
+    A=4'b1111;B=4'b1010;Command=3'b101; #1000 
+    $display("%b | %b |   %b |  %b  | 0101", A, B, Command, AndNandOut);
+
+//  A = 1111 | B = 0101 | NAND = 1010
+    A=4'b1111;B=4'b0101;Command=3'b101; #1000 
+    $display("%b | %b |   %b |  %b  | 1010", A, B, Command, AndNandOut);
+
+//  A = 1111 | B = 0000 | NAND = 1111
+    A=4'b1111;B=4'b0000;Command=3'b101; #1000 
+    $display("%b | %b |   %b |  %b  | 1111", A, B, Command, AndNandOut);
+
+$display("Test 4 Bit OR/NOR/XOR Functionality");
+// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. 
+$display(" A   | B    |Command  | Out     |ExpectedOut-OR"); 
+
+// A = 1010 | B = 0101 | OR = 1111
+	A=4'b1010; B=4'b0101; Command=3'b111; #1000
+	$display("%b | %b |    %b  |  %b   | 1111", A, B, Command, OrNorXorOut);
+
+// A = 1111 | B = 0101 | OR = 1111
+	A=4'b1111; B=4'b0101; Command=3'b111; #1000
+	$display("%b | %b |    %b  |  %b   | 1111", A, B, Command, OrNorXorOut);
+
+// A = 1011 | B = 0000 | OR = 1011
+	A=4'b1011; B=4'b0000; Command=3'b111; #1000
+	$display("%b | %b |    %b  |  %b   | 1011", A, B, Command, OrNorXorOut);
+
+$display(" A   | B    |Command  | Out     |ExpectedOut-NOR"); 
+
+// A = 1010 | B = 0101 | NOR = 0000
+	A=4'b1010; B=4'b0101; Command=3'b110; #1000
+	$display("%b | %b |    %b  |  %b   | 0000", A, B, Command, OrNorXorOut);
+
+// A = 1111 | B = 0101 | NOR = 0000
+	A=4'b1111; B=4'b0101; Command=3'b110; #1000
+	$display("%b | %b |    %b  |  %b   | 0000", A, B, Command, OrNorXorOut);
+
+// A = 1011 | B = 0000 | NOR = 0100
+	A=4'b1011; B=4'b0000; Command=3'b110; #1000
+	$display("%b | %b |    %b  |  %b   | 0100", A, B, Command, OrNorXorOut);
+
+$display(" A   | B    |Command  | Out     |ExpectedOut-XOR"); 
+
+// A = 1010 | B = 0101 | XOR = 1111
+	A=4'b1010; B=4'b0101; Command=3'b010; #1000
+	$display("%b | %b |    %b  |  %b   | 1111", A, B, Command, OrNorXorOut);
+
+// A = 1111 | B = 0101 | XOR = 1010
+	A=4'b1111; B=4'b0101; Command=3'b010; #1000
+	$display("%b | %b |    %b  |  %b   | 1010", A, B, Command, OrNorXorOut);
+
+// A = 1011 | B = 0000 | XOR = 1011
+	A=4'b1011; B=4'b0000; Command=3'b010; #1000
+	$display("%b | %b |    %b  |  %b   | 1011", A, B, Command, OrNorXorOut);
+
+$display("Test 4 Bit ALU Functionality");
+// there are too many possibilities even for just a four bit AND/NAND, which means we need to choose our test cases strategically. 
+$display(" A   | B    |Command     | Out     |ExpectedOut | COut | OF |SLT|Zero"); 
+
+// Test AND
+// A = B | A = 1111 | AND = 1111
+    A=4'b1111;B=4'b1111;Command=3'b100; #1000 
+    $display("%b | %b | %b - AND  |  %b   | 1111       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test NAND
+//  A = 1111 | B = 0000 | NAND = 1111
+    A=4'b1111;B=4'b0000;Command=3'b101; #1000 
+    $display("%b | %b | %b - NAND |  %b   | 1111       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test OR
+// A = 1111 | B = 0101 | OR = 1111
+	A=4'b1111; B=4'b0101; Command=3'b111; #1000
+    $display("%b | %b | %b - OR   |  %b   | 1111       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test NOR
+// A = 1011 | B = 0000 | NOR = 0100
+	A=4'b1011; B=4'b0000; Command=3'b110; #1000
+    $display("%b | %b | %b - NOR  |  %b   | 0100       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test XOR
+// A = 1011 | B = 0000 | XOR = 1011
+	A=4'b1011; B=4'b0000; Command=3'b010; #1000
+    $display("%b | %b | %b - XOR  |  %b   | 1011       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test ADD
+//Pos + Pos < 7 | 2 + 4 = 6 | 2 = 0010 | 4 = 0100 | 6 = 0110 | NO OVERFLOW
+A = 4'b0010; B = 4'b0100; Command =3'b000; #1000
+    $display("%b | %b | %b - ADD  |  %b   | 0110       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+//Neg + Neg < -8 | -5 + -4 = -9 | -5 = 1011 | -4 = 1100 |  | OVERFLOW
+A = 4'b1011; B = 4'b1100; Command =3'b000; #1000
+    $display("%b | %b | %b - ADD  |  %b   | XXXX       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test SUB
+// A < B, A > 0 | B > 0 | No Overflow | A = 2 = 0010 | B = 4 = 0100
+A = 4'b0010; B = 4'b0100; Command =3'b001; #1000
+    $display("%b | %b | %b - SUB  |  %b   | 1110       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 3 = 0011
+A = 4'b1001; B = 4'b0011; Command =3'b001; #1000
+    $display("%b | %b | %b - SUB  |  %b   | XXXX       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+// Test SLT
+
+// A > B, A > 0 | B > 0 | No Overflow | A = 4 = 0100 | B = 2 = 0010
+A = 4'b0100; B = 4'b0010; Command =3'b011; #1000
+    $display("%b | %b | %b - SLT  |  %b   | 0010       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag1, AllZeros);
+
+// A < B, A < 0 | B > 0 | Overflow | A = -7 = 1001 | B = 5 = 0101
+A = 4'b1001; B = 4'b0101; Command =3'b011; #1000
+    $display("%b | %b | %b - SLT  |  %b   | XXXX       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag1, AllZeros);
+
+// A < B, A < 0 | B > 0 | Overflow | A = 2 = 0010 | B = 4 = 0100
+A = 4'b0010; B = 4'b0100; Command =3'b011; #1000
+    $display("%b | %b | %b - SLT  |  %b   | XXXX       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag1, AllZeros);
+
+
+
+// Test Zero 
+
+
+    A=4'b0000;B=4'b1111;Command=3'b100; #1000 
+    $display("%b | %b | %b - AND  |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+    A=4'b1111;B=4'b1111;Command=3'b101; #1000 
+    $display("%b | %b | %b - NAND |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+	A=4'b0000; B=4'b0000; Command=3'b111; #1000
+    $display("%b | %b | %b - OR   |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+	A=4'b1011; B=4'b0100; Command=3'b110; #1000
+    $display("%b | %b | %b - NOR  |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+	A=4'b1011; B=4'b1011; Command=3'b010; #1000
+    $display("%b | %b | %b - XOR  |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+A = 4'b0010; B = 4'b1110; Command =3'b000; #1000
+    $display("%b | %b | %b - ADD  |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+A = 4'b0010; B = 4'b0010; Command =3'b001; #1000
+    $display("%b | %b | %b - SUB  |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+
+
+A = 4'b0000; B = 4'b0000; Command =3'b011; #1000
+    $display("%b | %b | %b - SLT  |  %b   | 0000       | %b    | %b  | %b | %b", A, B, Command, OneBitFinalOut, carryout, overflow, SLTflag, AllZeros);
+ 
+
+
+
+// test the ALU module (should be same as BitSlice32)
+$display(" A  				 | B 			  	 |Command    	 | Out 	   				 |ExpectedOut 	| COut | OF |Zero"); 
+A = 32'b11111111111111111111111111111111; B = 32'b11111111111111111111111111111110; Command =3'b011; #1000
+    $display("%b | %b | %b - SLT  |  %b   | 00000000000000000000000000000001       | %b    | %b  | %b", A, B, Command, OneBitFinalOut2, carryout2, overflow2, AllZeros2);
+
+
+end
+
+endmodule
+
+